Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 28
- Boot result: PASS
- Warnings: 1
- Errors: 1
- Kernel Warnings: 19
1 13:20:32.852929 lava-dispatcher, installed at version: 2023.06
2 13:20:32.853152 start: 0 validate
3 13:20:32.853296 Start time: 2023-09-06 13:20:32.853287+00:00 (UTC)
4 13:20:32.853480 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:20:32.853628 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 13:20:33.122716 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:20:33.123593 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.46-cip4-14-g09ffd7fb38ff%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:21:26.390832 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:21:26.391543 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.46-cip4-14-g09ffd7fb38ff%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:21:26.647131 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:21:26.647870 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.46-cip4-14-g09ffd7fb38ff%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 13:21:29.393371 validate duration: 56.54
14 13:21:29.393676 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:21:29.393804 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:21:29.393921 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:21:29.394093 Not decompressing ramdisk as can be used compressed.
18 13:21:29.394197 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/arm64/rootfs.cpio.gz
19 13:21:29.394297 saving as /var/lib/lava/dispatcher/tmp/11445610/tftp-deploy-rfkqokb0/ramdisk/rootfs.cpio.gz
20 13:21:29.394363 total size: 8181372 (7 MB)
21 13:21:29.652167 progress 0 % (0 MB)
22 13:21:29.654659 progress 5 % (0 MB)
23 13:21:29.656902 progress 10 % (0 MB)
24 13:21:29.659175 progress 15 % (1 MB)
25 13:21:29.661404 progress 20 % (1 MB)
26 13:21:29.663905 progress 25 % (1 MB)
27 13:21:29.666079 progress 30 % (2 MB)
28 13:21:29.668414 progress 35 % (2 MB)
29 13:21:29.670554 progress 40 % (3 MB)
30 13:21:29.672875 progress 45 % (3 MB)
31 13:21:29.675046 progress 50 % (3 MB)
32 13:21:29.677358 progress 55 % (4 MB)
33 13:21:29.679502 progress 60 % (4 MB)
34 13:21:29.681910 progress 65 % (5 MB)
35 13:21:29.684087 progress 70 % (5 MB)
36 13:21:29.686439 progress 75 % (5 MB)
37 13:21:29.688634 progress 80 % (6 MB)
38 13:21:29.690867 progress 85 % (6 MB)
39 13:21:29.693118 progress 90 % (7 MB)
40 13:21:29.695425 progress 95 % (7 MB)
41 13:21:29.697616 progress 100 % (7 MB)
42 13:21:29.697817 7 MB downloaded in 0.30 s (25.71 MB/s)
43 13:21:29.698003 end: 1.1.1 http-download (duration 00:00:00) [common]
45 13:21:29.698278 end: 1.1 download-retry (duration 00:00:00) [common]
46 13:21:29.698378 start: 1.2 download-retry (timeout 00:10:00) [common]
47 13:21:29.698490 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 13:21:29.698646 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.46-cip4-14-g09ffd7fb38ff/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 13:21:29.698730 saving as /var/lib/lava/dispatcher/tmp/11445610/tftp-deploy-rfkqokb0/kernel/Image
50 13:21:29.698805 total size: 49220096 (46 MB)
51 13:21:29.698881 No compression specified
52 13:21:29.700110 progress 0 % (0 MB)
53 13:21:29.713385 progress 5 % (2 MB)
54 13:21:29.727225 progress 10 % (4 MB)
55 13:21:29.740476 progress 15 % (7 MB)
56 13:21:29.753461 progress 20 % (9 MB)
57 13:21:29.767126 progress 25 % (11 MB)
58 13:21:29.780090 progress 30 % (14 MB)
59 13:21:29.793083 progress 35 % (16 MB)
60 13:21:29.806202 progress 40 % (18 MB)
61 13:21:29.819914 progress 45 % (21 MB)
62 13:21:29.833899 progress 50 % (23 MB)
63 13:21:29.847622 progress 55 % (25 MB)
64 13:21:29.861513 progress 60 % (28 MB)
65 13:21:29.874620 progress 65 % (30 MB)
66 13:21:29.887886 progress 70 % (32 MB)
67 13:21:29.901280 progress 75 % (35 MB)
68 13:21:29.914178 progress 80 % (37 MB)
69 13:21:29.927609 progress 85 % (39 MB)
70 13:21:29.940829 progress 90 % (42 MB)
71 13:21:29.954088 progress 95 % (44 MB)
72 13:21:29.967083 progress 100 % (46 MB)
73 13:21:29.967270 46 MB downloaded in 0.27 s (174.85 MB/s)
74 13:21:29.967550 end: 1.2.1 http-download (duration 00:00:00) [common]
76 13:21:29.967792 end: 1.2 download-retry (duration 00:00:00) [common]
77 13:21:29.967913 start: 1.3 download-retry (timeout 00:09:59) [common]
78 13:21:29.967998 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 13:21:29.968142 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.46-cip4-14-g09ffd7fb38ff/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 13:21:29.968212 saving as /var/lib/lava/dispatcher/tmp/11445610/tftp-deploy-rfkqokb0/dtb/mt8192-asurada-spherion-r0.dtb
81 13:21:29.968303 total size: 47278 (0 MB)
82 13:21:29.968364 No compression specified
83 13:21:29.969550 progress 69 % (0 MB)
84 13:21:29.969824 progress 100 % (0 MB)
85 13:21:29.969979 0 MB downloaded in 0.00 s (26.94 MB/s)
86 13:21:29.970103 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:21:29.970325 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:21:29.970410 start: 1.4 download-retry (timeout 00:09:59) [common]
90 13:21:29.970492 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 13:21:29.970609 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.46-cip4-14-g09ffd7fb38ff/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 13:21:29.970676 saving as /var/lib/lava/dispatcher/tmp/11445610/tftp-deploy-rfkqokb0/modules/modules.tar
93 13:21:29.970736 total size: 8610736 (8 MB)
94 13:21:29.970797 Using unxz to decompress xz
95 13:21:29.974968 progress 0 % (0 MB)
96 13:21:29.998127 progress 5 % (0 MB)
97 13:21:30.023005 progress 10 % (0 MB)
98 13:21:30.055747 progress 15 % (1 MB)
99 13:21:30.088126 progress 20 % (1 MB)
100 13:21:30.114321 progress 25 % (2 MB)
101 13:21:30.140008 progress 30 % (2 MB)
102 13:21:30.165390 progress 35 % (2 MB)
103 13:21:30.194281 progress 40 % (3 MB)
104 13:21:30.221745 progress 45 % (3 MB)
105 13:21:30.248387 progress 50 % (4 MB)
106 13:21:30.274694 progress 55 % (4 MB)
107 13:21:30.300016 progress 60 % (4 MB)
108 13:21:30.324810 progress 65 % (5 MB)
109 13:21:30.349666 progress 70 % (5 MB)
110 13:21:30.384027 progress 75 % (6 MB)
111 13:21:30.409807 progress 80 % (6 MB)
112 13:21:30.437227 progress 85 % (7 MB)
113 13:21:30.463664 progress 90 % (7 MB)
114 13:21:30.487880 progress 95 % (7 MB)
115 13:21:30.513848 progress 100 % (8 MB)
116 13:21:30.519719 8 MB downloaded in 0.55 s (14.96 MB/s)
117 13:21:30.520041 end: 1.4.1 http-download (duration 00:00:01) [common]
119 13:21:30.520359 end: 1.4 download-retry (duration 00:00:01) [common]
120 13:21:30.520453 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 13:21:30.520553 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 13:21:30.520638 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:21:30.520724 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 13:21:30.520955 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11445610/lava-overlay-wkdynrwu
125 13:21:30.521092 makedir: /var/lib/lava/dispatcher/tmp/11445610/lava-overlay-wkdynrwu/lava-11445610/bin
126 13:21:30.521205 makedir: /var/lib/lava/dispatcher/tmp/11445610/lava-overlay-wkdynrwu/lava-11445610/tests
127 13:21:30.521337 makedir: /var/lib/lava/dispatcher/tmp/11445610/lava-overlay-wkdynrwu/lava-11445610/results
128 13:21:30.521486 Creating /var/lib/lava/dispatcher/tmp/11445610/lava-overlay-wkdynrwu/lava-11445610/bin/lava-add-keys
129 13:21:30.521670 Creating /var/lib/lava/dispatcher/tmp/11445610/lava-overlay-wkdynrwu/lava-11445610/bin/lava-add-sources
130 13:21:30.521843 Creating /var/lib/lava/dispatcher/tmp/11445610/lava-overlay-wkdynrwu/lava-11445610/bin/lava-background-process-start
131 13:21:30.522005 Creating /var/lib/lava/dispatcher/tmp/11445610/lava-overlay-wkdynrwu/lava-11445610/bin/lava-background-process-stop
132 13:21:30.522171 Creating /var/lib/lava/dispatcher/tmp/11445610/lava-overlay-wkdynrwu/lava-11445610/bin/lava-common-functions
133 13:21:30.522332 Creating /var/lib/lava/dispatcher/tmp/11445610/lava-overlay-wkdynrwu/lava-11445610/bin/lava-echo-ipv4
134 13:21:30.522494 Creating /var/lib/lava/dispatcher/tmp/11445610/lava-overlay-wkdynrwu/lava-11445610/bin/lava-install-packages
135 13:21:30.522656 Creating /var/lib/lava/dispatcher/tmp/11445610/lava-overlay-wkdynrwu/lava-11445610/bin/lava-installed-packages
136 13:21:30.522815 Creating /var/lib/lava/dispatcher/tmp/11445610/lava-overlay-wkdynrwu/lava-11445610/bin/lava-os-build
137 13:21:30.522976 Creating /var/lib/lava/dispatcher/tmp/11445610/lava-overlay-wkdynrwu/lava-11445610/bin/lava-probe-channel
138 13:21:30.523135 Creating /var/lib/lava/dispatcher/tmp/11445610/lava-overlay-wkdynrwu/lava-11445610/bin/lava-probe-ip
139 13:21:30.523296 Creating /var/lib/lava/dispatcher/tmp/11445610/lava-overlay-wkdynrwu/lava-11445610/bin/lava-target-ip
140 13:21:30.523488 Creating /var/lib/lava/dispatcher/tmp/11445610/lava-overlay-wkdynrwu/lava-11445610/bin/lava-target-mac
141 13:21:30.523617 Creating /var/lib/lava/dispatcher/tmp/11445610/lava-overlay-wkdynrwu/lava-11445610/bin/lava-target-storage
142 13:21:30.523748 Creating /var/lib/lava/dispatcher/tmp/11445610/lava-overlay-wkdynrwu/lava-11445610/bin/lava-test-case
143 13:21:30.523877 Creating /var/lib/lava/dispatcher/tmp/11445610/lava-overlay-wkdynrwu/lava-11445610/bin/lava-test-event
144 13:21:30.524002 Creating /var/lib/lava/dispatcher/tmp/11445610/lava-overlay-wkdynrwu/lava-11445610/bin/lava-test-feedback
145 13:21:30.524129 Creating /var/lib/lava/dispatcher/tmp/11445610/lava-overlay-wkdynrwu/lava-11445610/bin/lava-test-raise
146 13:21:30.524265 Creating /var/lib/lava/dispatcher/tmp/11445610/lava-overlay-wkdynrwu/lava-11445610/bin/lava-test-reference
147 13:21:30.524392 Creating /var/lib/lava/dispatcher/tmp/11445610/lava-overlay-wkdynrwu/lava-11445610/bin/lava-test-runner
148 13:21:30.524522 Creating /var/lib/lava/dispatcher/tmp/11445610/lava-overlay-wkdynrwu/lava-11445610/bin/lava-test-set
149 13:21:30.524653 Creating /var/lib/lava/dispatcher/tmp/11445610/lava-overlay-wkdynrwu/lava-11445610/bin/lava-test-shell
150 13:21:30.524788 Updating /var/lib/lava/dispatcher/tmp/11445610/lava-overlay-wkdynrwu/lava-11445610/bin/lava-install-packages (oe)
151 13:21:30.524942 Updating /var/lib/lava/dispatcher/tmp/11445610/lava-overlay-wkdynrwu/lava-11445610/bin/lava-installed-packages (oe)
152 13:21:30.525065 Creating /var/lib/lava/dispatcher/tmp/11445610/lava-overlay-wkdynrwu/lava-11445610/environment
153 13:21:30.525181 LAVA metadata
154 13:21:30.525257 - LAVA_JOB_ID=11445610
155 13:21:30.525324 - LAVA_DISPATCHER_IP=192.168.201.1
156 13:21:30.525435 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 13:21:30.525529 skipped lava-vland-overlay
158 13:21:30.525634 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 13:21:30.525750 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 13:21:30.525844 skipped lava-multinode-overlay
161 13:21:30.525949 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 13:21:30.526064 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 13:21:30.526166 Loading test definitions
164 13:21:30.526294 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 13:21:30.526398 Using /lava-11445610 at stage 0
166 13:21:30.526790 uuid=11445610_1.5.2.3.1 testdef=None
167 13:21:30.526884 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 13:21:30.527002 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 13:21:30.527693 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 13:21:30.527920 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 13:21:30.528582 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 13:21:30.528818 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 13:21:30.529697 runner path: /var/lib/lava/dispatcher/tmp/11445610/lava-overlay-wkdynrwu/lava-11445610/0/tests/0_dmesg test_uuid 11445610_1.5.2.3.1
176 13:21:30.529892 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 13:21:30.530256 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:59) [common]
179 13:21:30.530358 Using /lava-11445610 at stage 1
180 13:21:30.530688 uuid=11445610_1.5.2.3.5 testdef=None
181 13:21:30.530781 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 13:21:30.530865 start: 1.5.2.3.6 test-overlay (timeout 00:09:59) [common]
183 13:21:30.531490 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 13:21:30.531781 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:59) [common]
186 13:21:30.533083 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 13:21:30.533438 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
189 13:21:30.534382 runner path: /var/lib/lava/dispatcher/tmp/11445610/lava-overlay-wkdynrwu/lava-11445610/1/tests/1_bootrr test_uuid 11445610_1.5.2.3.5
190 13:21:30.534572 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 13:21:30.534837 Creating lava-test-runner.conf files
193 13:21:30.534902 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11445610/lava-overlay-wkdynrwu/lava-11445610/0 for stage 0
194 13:21:30.535027 - 0_dmesg
195 13:21:30.535139 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11445610/lava-overlay-wkdynrwu/lava-11445610/1 for stage 1
196 13:21:30.535262 - 1_bootrr
197 13:21:30.535445 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 13:21:30.535533 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
199 13:21:30.543645 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 13:21:30.543760 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
201 13:21:30.543846 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 13:21:30.543931 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 13:21:30.544016 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
204 13:21:30.793677 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 13:21:30.794074 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
206 13:21:30.794193 extracting modules file /var/lib/lava/dispatcher/tmp/11445610/tftp-deploy-rfkqokb0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11445610/extract-overlay-ramdisk-99qbgd40/ramdisk
207 13:21:31.021758 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 13:21:31.021931 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
209 13:21:31.022031 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11445610/compress-overlay-4l0y3w6p/overlay-1.5.2.4.tar.gz to ramdisk
210 13:21:31.022105 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11445610/compress-overlay-4l0y3w6p/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11445610/extract-overlay-ramdisk-99qbgd40/ramdisk
211 13:21:31.030529 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 13:21:31.030653 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
213 13:21:31.030742 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 13:21:31.030832 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
215 13:21:31.030917 Building ramdisk /var/lib/lava/dispatcher/tmp/11445610/extract-overlay-ramdisk-99qbgd40/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11445610/extract-overlay-ramdisk-99qbgd40/ramdisk
216 13:21:31.437172 >> 145167 blocks
217 13:21:33.708939 rename /var/lib/lava/dispatcher/tmp/11445610/extract-overlay-ramdisk-99qbgd40/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11445610/tftp-deploy-rfkqokb0/ramdisk/ramdisk.cpio.gz
218 13:21:33.709392 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 13:21:33.709516 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
220 13:21:33.709621 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
221 13:21:33.709733 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11445610/tftp-deploy-rfkqokb0/kernel/Image'
222 13:21:46.592618 Returned 0 in 12 seconds
223 13:21:46.693271 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11445610/tftp-deploy-rfkqokb0/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11445610/tftp-deploy-rfkqokb0/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11445610/tftp-deploy-rfkqokb0/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11445610/tftp-deploy-rfkqokb0/kernel/image.itb
224 13:21:47.097518 output: FIT description: Kernel Image image with one or more FDT blobs
225 13:21:47.097919 output: Created: Wed Sep 6 14:21:47 2023
226 13:21:47.098011 output: Image 0 (kernel-1)
227 13:21:47.098079 output: Description:
228 13:21:47.098144 output: Created: Wed Sep 6 14:21:47 2023
229 13:21:47.098207 output: Type: Kernel Image
230 13:21:47.098267 output: Compression: lzma compressed
231 13:21:47.098328 output: Data Size: 11038222 Bytes = 10779.51 KiB = 10.53 MiB
232 13:21:47.098391 output: Architecture: AArch64
233 13:21:47.098452 output: OS: Linux
234 13:21:47.098512 output: Load Address: 0x00000000
235 13:21:47.098567 output: Entry Point: 0x00000000
236 13:21:47.098637 output: Hash algo: crc32
237 13:21:47.098701 output: Hash value: eae831c7
238 13:21:47.098797 output: Image 1 (fdt-1)
239 13:21:47.098859 output: Description: mt8192-asurada-spherion-r0
240 13:21:47.098915 output: Created: Wed Sep 6 14:21:47 2023
241 13:21:47.098971 output: Type: Flat Device Tree
242 13:21:47.099026 output: Compression: uncompressed
243 13:21:47.099080 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
244 13:21:47.099135 output: Architecture: AArch64
245 13:21:47.099189 output: Hash algo: crc32
246 13:21:47.099242 output: Hash value: cc4352de
247 13:21:47.099296 output: Image 2 (ramdisk-1)
248 13:21:47.099350 output: Description: unavailable
249 13:21:47.099430 output: Created: Wed Sep 6 14:21:47 2023
250 13:21:47.099498 output: Type: RAMDisk Image
251 13:21:47.099552 output: Compression: Unknown Compression
252 13:21:47.099606 output: Data Size: 21372432 Bytes = 20871.52 KiB = 20.38 MiB
253 13:21:47.099661 output: Architecture: AArch64
254 13:21:47.099714 output: OS: Linux
255 13:21:47.099768 output: Load Address: unavailable
256 13:21:47.099822 output: Entry Point: unavailable
257 13:21:47.099876 output: Hash algo: crc32
258 13:21:47.099929 output: Hash value: 96260112
259 13:21:47.099982 output: Default Configuration: 'conf-1'
260 13:21:47.100036 output: Configuration 0 (conf-1)
261 13:21:47.100090 output: Description: mt8192-asurada-spherion-r0
262 13:21:47.100143 output: Kernel: kernel-1
263 13:21:47.100196 output: Init Ramdisk: ramdisk-1
264 13:21:47.100249 output: FDT: fdt-1
265 13:21:47.100303 output: Loadables: kernel-1
266 13:21:47.100356 output:
267 13:21:47.100558 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
268 13:21:47.100663 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
269 13:21:47.100768 end: 1.5 prepare-tftp-overlay (duration 00:00:17) [common]
270 13:21:47.100864 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:42) [common]
271 13:21:47.100950 No LXC device requested
272 13:21:47.101034 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 13:21:47.101120 start: 1.7 deploy-device-env (timeout 00:09:42) [common]
274 13:21:47.101199 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 13:21:47.101271 Checking files for TFTP limit of 4294967296 bytes.
276 13:21:47.101791 end: 1 tftp-deploy (duration 00:00:18) [common]
277 13:21:47.101896 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 13:21:47.101992 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 13:21:47.102110 substitutions:
280 13:21:47.102177 - {DTB}: 11445610/tftp-deploy-rfkqokb0/dtb/mt8192-asurada-spherion-r0.dtb
281 13:21:47.102244 - {INITRD}: 11445610/tftp-deploy-rfkqokb0/ramdisk/ramdisk.cpio.gz
282 13:21:47.102304 - {KERNEL}: 11445610/tftp-deploy-rfkqokb0/kernel/Image
283 13:21:47.102362 - {LAVA_MAC}: None
284 13:21:47.102419 - {PRESEED_CONFIG}: None
285 13:21:47.102475 - {PRESEED_LOCAL}: None
286 13:21:47.102530 - {RAMDISK}: 11445610/tftp-deploy-rfkqokb0/ramdisk/ramdisk.cpio.gz
287 13:21:47.102584 - {ROOT_PART}: None
288 13:21:47.102639 - {ROOT}: None
289 13:21:47.102693 - {SERVER_IP}: 192.168.201.1
290 13:21:47.102747 - {TEE}: None
291 13:21:47.102801 Parsed boot commands:
292 13:21:47.102857 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 13:21:47.103045 Parsed boot commands: tftpboot 192.168.201.1 11445610/tftp-deploy-rfkqokb0/kernel/image.itb 11445610/tftp-deploy-rfkqokb0/kernel/cmdline
294 13:21:47.103138 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 13:21:47.103226 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 13:21:47.103321 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 13:21:47.103456 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 13:21:47.103533 Not connected, no need to disconnect.
299 13:21:47.103611 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 13:21:47.103692 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 13:21:47.103760 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
302 13:21:47.107938 Setting prompt string to ['lava-test: # ']
303 13:21:47.108354 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 13:21:47.108475 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 13:21:47.108595 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 13:21:47.108904 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 13:21:47.109149 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
308 13:21:52.256804 >> Command sent successfully.
309 13:21:52.259169 Returned 0 in 5 seconds
310 13:21:52.359865 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 13:21:52.361205 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 13:21:52.361717 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 13:21:52.362282 Setting prompt string to 'Starting depthcharge on Spherion...'
315 13:21:52.362666 Changing prompt to 'Starting depthcharge on Spherion...'
316 13:21:52.363108 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 13:21:52.364939 [Enter `^Ec?' for help]
318 13:21:52.534954
319 13:21:52.535625
320 13:21:52.536083 F0: 102B 0000
321 13:21:52.536426
322 13:21:52.536868 F3: 1001 0000 [0200]
323 13:21:52.537292
324 13:21:52.538258 F3: 1001 0000
325 13:21:52.538707
326 13:21:52.539117 F7: 102D 0000
327 13:21:52.539552
328 13:21:52.541755 F1: 0000 0000
329 13:21:52.542158
330 13:21:52.542510 V0: 0000 0000 [0001]
331 13:21:52.542816
332 13:21:52.545171 00: 0007 8000
333 13:21:52.545689
334 13:21:52.546003 01: 0000 0000
335 13:21:52.546300
336 13:21:52.547863 BP: 0C00 0209 [0000]
337 13:21:52.548259
338 13:21:52.548573 G0: 1182 0000
339 13:21:52.548863
340 13:21:52.551451 EC: 0000 0021 [4000]
341 13:21:52.551882
342 13:21:52.552196 S7: 0000 0000 [0000]
343 13:21:52.552489
344 13:21:52.554923 CC: 0000 0000 [0001]
345 13:21:52.555315
346 13:21:52.555688 T0: 0000 0040 [010F]
347 13:21:52.556035
348 13:21:52.556385 Jump to BL
349 13:21:52.556696
350 13:21:52.581345
351 13:21:52.581776
352 13:21:52.582088
353 13:21:52.588995 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 13:21:52.592421 ARM64: Exception handlers installed.
355 13:21:52.596259 ARM64: Testing exception
356 13:21:52.599298 ARM64: Done test exception
357 13:21:52.606220 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 13:21:52.617100 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 13:21:52.623068 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 13:21:52.633705 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 13:21:52.640100 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 13:21:52.646840 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 13:21:52.658467 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 13:21:52.665321 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 13:21:52.684291 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 13:21:52.687212 WDT: Last reset was cold boot
367 13:21:52.690977 SPI1(PAD0) initialized at 2873684 Hz
368 13:21:52.694406 SPI5(PAD0) initialized at 992727 Hz
369 13:21:52.697737 VBOOT: Loading verstage.
370 13:21:52.704600 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 13:21:52.707919 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 13:21:52.711028 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 13:21:52.714278 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 13:21:52.722018 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 13:21:52.728442 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 13:21:52.739512 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
377 13:21:52.740057
378 13:21:52.740405
379 13:21:52.749174 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 13:21:52.753157 ARM64: Exception handlers installed.
381 13:21:52.756272 ARM64: Testing exception
382 13:21:52.756707 ARM64: Done test exception
383 13:21:52.762560 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 13:21:52.765991 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 13:21:52.780282 Probing TPM: . done!
386 13:21:52.780718 TPM ready after 0 ms
387 13:21:52.787444 Connected to device vid:did:rid of 1ae0:0028:00
388 13:21:52.794356 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
389 13:21:52.835600 Initialized TPM device CR50 revision 0
390 13:21:52.847079 tlcl_send_startup: Startup return code is 0
391 13:21:52.847550 TPM: setup succeeded
392 13:21:52.858406 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 13:21:52.867204 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 13:21:52.879436 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 13:21:52.889768 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 13:21:52.893269 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 13:21:52.896826 in-header: 03 07 00 00 08 00 00 00
398 13:21:52.900346 in-data: aa e4 47 04 13 02 00 00
399 13:21:52.900777 Chrome EC: UHEPI supported
400 13:21:52.907295 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 13:21:52.912782 in-header: 03 9d 00 00 08 00 00 00
402 13:21:52.916480 in-data: 10 20 20 08 00 00 00 00
403 13:21:52.916917 Phase 1
404 13:21:52.923669 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 13:21:52.927766 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 13:21:52.935066 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 13:21:52.935549 Recovery requested (1009000e)
408 13:21:52.944119 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 13:21:52.949441 tlcl_extend: response is 0
410 13:21:52.957907 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 13:21:52.963245 tlcl_extend: response is 0
412 13:21:52.969368 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 13:21:52.991286 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
414 13:21:52.997860 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 13:21:52.998390
416 13:21:52.998840
417 13:21:53.005173 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 13:21:53.008867 ARM64: Exception handlers installed.
419 13:21:53.012119 ARM64: Testing exception
420 13:21:53.015692 ARM64: Done test exception
421 13:21:53.036545 pmic_efuse_setting: Set efuses in 11 msecs
422 13:21:53.039936 pmwrap_interface_init: Select PMIF_VLD_RDY
423 13:21:53.043146 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 13:21:53.050300 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 13:21:53.054414 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 13:21:53.058065 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 13:21:53.065524 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 13:21:53.069348 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 13:21:53.072797 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 13:21:53.076392 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 13:21:53.083928 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 13:21:53.086538 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 13:21:53.093318 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 13:21:53.096758 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 13:21:53.100440 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 13:21:53.106905 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 13:21:53.113726 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 13:21:53.120039 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 13:21:53.123608 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 13:21:53.130230 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 13:21:53.137733 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 13:21:53.140629 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 13:21:53.148179 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 13:21:53.151662 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 13:21:53.158725 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 13:21:53.161736 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 13:21:53.169127 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 13:21:53.175871 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 13:21:53.179203 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 13:21:53.182744 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 13:21:53.189875 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 13:21:53.193606 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 13:21:53.200232 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 13:21:53.204497 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 13:21:53.207549 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 13:21:53.215147 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 13:21:53.218644 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 13:21:53.225912 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 13:21:53.228875 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 13:21:53.235762 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 13:21:53.239082 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 13:21:53.242768 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 13:21:53.245826 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 13:21:53.252674 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 13:21:53.256179 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 13:21:53.259443 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 13:21:53.266010 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 13:21:53.269650 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 13:21:53.272693 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 13:21:53.279402 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 13:21:53.282722 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 13:21:53.285668 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 13:21:53.289516 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 13:21:53.298613 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 13:21:53.305958 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 13:21:53.312432 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 13:21:53.318858 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 13:21:53.328907 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 13:21:53.332446 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 13:21:53.335269 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 13:21:53.342542 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 13:21:53.348904 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x33
483 13:21:53.352516 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 13:21:53.360150 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
485 13:21:53.363999 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 13:21:53.372873 [RTC]rtc_get_frequency_meter,154: input=15, output=794
487 13:21:53.375939 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
488 13:21:53.382817 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
489 13:21:53.386312 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
490 13:21:53.389325 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
491 13:21:53.392829 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
492 13:21:53.395980 ADC[4]: Raw value=898150 ID=7
493 13:21:53.399254 ADC[3]: Raw value=213440 ID=1
494 13:21:53.402456 RAM Code: 0x71
495 13:21:53.406207 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
496 13:21:53.409471 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
497 13:21:53.419306 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
498 13:21:53.426531 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
499 13:21:53.429743 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
500 13:21:53.433086 in-header: 03 07 00 00 08 00 00 00
501 13:21:53.436269 in-data: aa e4 47 04 13 02 00 00
502 13:21:53.436366 Chrome EC: UHEPI supported
503 13:21:53.443496 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
504 13:21:53.447577 in-header: 03 d5 00 00 08 00 00 00
505 13:21:53.451447 in-data: 98 20 60 08 00 00 00 00
506 13:21:53.454983 MRC: failed to locate region type 0.
507 13:21:53.462655 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
508 13:21:53.466534 DRAM-K: Running full calibration
509 13:21:53.469480 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
510 13:21:53.473065 header.status = 0x0
511 13:21:53.476452 header.version = 0x6 (expected: 0x6)
512 13:21:53.479515 header.size = 0xd00 (expected: 0xd00)
513 13:21:53.480057 header.flags = 0x0
514 13:21:53.486460 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
515 13:21:53.505134 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
516 13:21:53.512110 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
517 13:21:53.514849 dram_init: ddr_geometry: 2
518 13:21:53.518353 [EMI] MDL number = 2
519 13:21:53.518785 [EMI] Get MDL freq = 0
520 13:21:53.521398 dram_init: ddr_type: 0
521 13:21:53.521832 is_discrete_lpddr4: 1
522 13:21:53.524772 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
523 13:21:53.525205
524 13:21:53.525541
525 13:21:53.528402 [Bian_co] ETT version 0.0.0.1
526 13:21:53.535150 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
527 13:21:53.535726
528 13:21:53.538763 dramc_set_vcore_voltage set vcore to 650000
529 13:21:53.541726 Read voltage for 800, 4
530 13:21:53.542157 Vio18 = 0
531 13:21:53.542501 Vcore = 650000
532 13:21:53.544716 Vdram = 0
533 13:21:53.545149 Vddq = 0
534 13:21:53.545492 Vmddr = 0
535 13:21:53.547918 dram_init: config_dvfs: 1
536 13:21:53.551659 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
537 13:21:53.557953 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
538 13:21:53.561553 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
539 13:21:53.564876 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
540 13:21:53.568297 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
541 13:21:53.571911 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
542 13:21:53.575051 MEM_TYPE=3, freq_sel=18
543 13:21:53.578153 sv_algorithm_assistance_LP4_1600
544 13:21:53.581515 ============ PULL DRAM RESETB DOWN ============
545 13:21:53.584739 ========== PULL DRAM RESETB DOWN end =========
546 13:21:53.591288 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
547 13:21:53.594856 ===================================
548 13:21:53.598276 LPDDR4 DRAM CONFIGURATION
549 13:21:53.601409 ===================================
550 13:21:53.601841 EX_ROW_EN[0] = 0x0
551 13:21:53.605122 EX_ROW_EN[1] = 0x0
552 13:21:53.605577 LP4Y_EN = 0x0
553 13:21:53.608523 WORK_FSP = 0x0
554 13:21:53.608956 WL = 0x2
555 13:21:53.611745 RL = 0x2
556 13:21:53.612177 BL = 0x2
557 13:21:53.614733 RPST = 0x0
558 13:21:53.615166 RD_PRE = 0x0
559 13:21:53.618111 WR_PRE = 0x1
560 13:21:53.618541 WR_PST = 0x0
561 13:21:53.621982 DBI_WR = 0x0
562 13:21:53.622518 DBI_RD = 0x0
563 13:21:53.625069 OTF = 0x1
564 13:21:53.628082 ===================================
565 13:21:53.631641 ===================================
566 13:21:53.632077 ANA top config
567 13:21:53.634510 ===================================
568 13:21:53.638148 DLL_ASYNC_EN = 0
569 13:21:53.641769 ALL_SLAVE_EN = 1
570 13:21:53.644793 NEW_RANK_MODE = 1
571 13:21:53.645227 DLL_IDLE_MODE = 1
572 13:21:53.648043 LP45_APHY_COMB_EN = 1
573 13:21:53.651894 TX_ODT_DIS = 1
574 13:21:53.655233 NEW_8X_MODE = 1
575 13:21:53.658705 ===================================
576 13:21:53.662346 ===================================
577 13:21:53.662780 data_rate = 1600
578 13:21:53.665979 CKR = 1
579 13:21:53.669848 DQ_P2S_RATIO = 8
580 13:21:53.673191 ===================================
581 13:21:53.673624 CA_P2S_RATIO = 8
582 13:21:53.677307 DQ_CA_OPEN = 0
583 13:21:53.680882 DQ_SEMI_OPEN = 0
584 13:21:53.684405 CA_SEMI_OPEN = 0
585 13:21:53.684841 CA_FULL_RATE = 0
586 13:21:53.688253 DQ_CKDIV4_EN = 1
587 13:21:53.691680 CA_CKDIV4_EN = 1
588 13:21:53.695765 CA_PREDIV_EN = 0
589 13:21:53.696195 PH8_DLY = 0
590 13:21:53.699837 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
591 13:21:53.703152 DQ_AAMCK_DIV = 4
592 13:21:53.706936 CA_AAMCK_DIV = 4
593 13:21:53.707406 CA_ADMCK_DIV = 4
594 13:21:53.710734 DQ_TRACK_CA_EN = 0
595 13:21:53.713795 CA_PICK = 800
596 13:21:53.717684 CA_MCKIO = 800
597 13:21:53.721480 MCKIO_SEMI = 0
598 13:21:53.721991 PLL_FREQ = 3068
599 13:21:53.725097 DQ_UI_PI_RATIO = 32
600 13:21:53.728746 CA_UI_PI_RATIO = 0
601 13:21:53.732136 ===================================
602 13:21:53.735951 ===================================
603 13:21:53.736402 memory_type:LPDDR4
604 13:21:53.739912 GP_NUM : 10
605 13:21:53.740337 SRAM_EN : 1
606 13:21:53.743543 MD32_EN : 0
607 13:21:53.746576 ===================================
608 13:21:53.749702 [ANA_INIT] >>>>>>>>>>>>>>
609 13:21:53.753510 <<<<<< [CONFIGURE PHASE]: ANA_TX
610 13:21:53.756052 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
611 13:21:53.759522 ===================================
612 13:21:53.760045 data_rate = 1600,PCW = 0X7600
613 13:21:53.762919 ===================================
614 13:21:53.766090 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
615 13:21:53.773087 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
616 13:21:53.779719 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
617 13:21:53.782800 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
618 13:21:53.786385 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
619 13:21:53.789864 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
620 13:21:53.793606 [ANA_INIT] flow start
621 13:21:53.794060 [ANA_INIT] PLL >>>>>>>>
622 13:21:53.797055 [ANA_INIT] PLL <<<<<<<<
623 13:21:53.801105 [ANA_INIT] MIDPI >>>>>>>>
624 13:21:53.801648 [ANA_INIT] MIDPI <<<<<<<<
625 13:21:53.804409 [ANA_INIT] DLL >>>>>>>>
626 13:21:53.804845 [ANA_INIT] flow end
627 13:21:53.811498 ============ LP4 DIFF to SE enter ============
628 13:21:53.815111 ============ LP4 DIFF to SE exit ============
629 13:21:53.815826 [ANA_INIT] <<<<<<<<<<<<<
630 13:21:53.818989 [Flow] Enable top DCM control >>>>>
631 13:21:53.822088 [Flow] Enable top DCM control <<<<<
632 13:21:53.826219 Enable DLL master slave shuffle
633 13:21:53.829917 ==============================================================
634 13:21:53.833079 Gating Mode config
635 13:21:53.840068 ==============================================================
636 13:21:53.840988 Config description:
637 13:21:53.849896 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
638 13:21:53.856408 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
639 13:21:53.863003 SELPH_MODE 0: By rank 1: By Phase
640 13:21:53.866394 ==============================================================
641 13:21:53.870389 GAT_TRACK_EN = 1
642 13:21:53.873085 RX_GATING_MODE = 2
643 13:21:53.876719 RX_GATING_TRACK_MODE = 2
644 13:21:53.879563 SELPH_MODE = 1
645 13:21:53.883452 PICG_EARLY_EN = 1
646 13:21:53.886368 VALID_LAT_VALUE = 1
647 13:21:53.889700 ==============================================================
648 13:21:53.893258 Enter into Gating configuration >>>>
649 13:21:53.896300 Exit from Gating configuration <<<<
650 13:21:53.899773 Enter into DVFS_PRE_config >>>>>
651 13:21:53.913290 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
652 13:21:53.913868 Exit from DVFS_PRE_config <<<<<
653 13:21:53.916319 Enter into PICG configuration >>>>
654 13:21:53.919899 Exit from PICG configuration <<<<
655 13:21:53.922835 [RX_INPUT] configuration >>>>>
656 13:21:53.926557 [RX_INPUT] configuration <<<<<
657 13:21:53.933158 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
658 13:21:53.936899 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
659 13:21:53.943755 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
660 13:21:53.951114 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
661 13:21:53.954714 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
662 13:21:53.962256 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
663 13:21:53.966046 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
664 13:21:53.969725 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
665 13:21:53.973741 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
666 13:21:53.977074 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
667 13:21:53.980955 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
668 13:21:53.987676 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
669 13:21:53.991613 ===================================
670 13:21:53.992022 LPDDR4 DRAM CONFIGURATION
671 13:21:53.994822 ===================================
672 13:21:53.999127 EX_ROW_EN[0] = 0x0
673 13:21:53.999596 EX_ROW_EN[1] = 0x0
674 13:21:54.003165 LP4Y_EN = 0x0
675 13:21:54.003732 WORK_FSP = 0x0
676 13:21:54.006262 WL = 0x2
677 13:21:54.006697 RL = 0x2
678 13:21:54.010222 BL = 0x2
679 13:21:54.010653 RPST = 0x0
680 13:21:54.013489 RD_PRE = 0x0
681 13:21:54.013912 WR_PRE = 0x1
682 13:21:54.014251 WR_PST = 0x0
683 13:21:54.017917 DBI_WR = 0x0
684 13:21:54.018451 DBI_RD = 0x0
685 13:21:54.021214 OTF = 0x1
686 13:21:54.025376 ===================================
687 13:21:54.028511 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
688 13:21:54.032629 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
689 13:21:54.036526 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
690 13:21:54.039799 ===================================
691 13:21:54.043355 LPDDR4 DRAM CONFIGURATION
692 13:21:54.047509 ===================================
693 13:21:54.048033 EX_ROW_EN[0] = 0x10
694 13:21:54.050724 EX_ROW_EN[1] = 0x0
695 13:21:54.051432 LP4Y_EN = 0x0
696 13:21:54.054703 WORK_FSP = 0x0
697 13:21:54.055345 WL = 0x2
698 13:21:54.057814 RL = 0x2
699 13:21:54.058241 BL = 0x2
700 13:21:54.058581 RPST = 0x0
701 13:21:54.061990 RD_PRE = 0x0
702 13:21:54.062437 WR_PRE = 0x1
703 13:21:54.065499 WR_PST = 0x0
704 13:21:54.065935 DBI_WR = 0x0
705 13:21:54.068853 DBI_RD = 0x0
706 13:21:54.069287 OTF = 0x1
707 13:21:54.073092 ===================================
708 13:21:54.079603 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
709 13:21:54.083271 nWR fixed to 40
710 13:21:54.087258 [ModeRegInit_LP4] CH0 RK0
711 13:21:54.087740 [ModeRegInit_LP4] CH0 RK1
712 13:21:54.091179 [ModeRegInit_LP4] CH1 RK0
713 13:21:54.091653 [ModeRegInit_LP4] CH1 RK1
714 13:21:54.094920 match AC timing 13
715 13:21:54.098897 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
716 13:21:54.102490 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
717 13:21:54.105997 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
718 13:21:54.113361 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
719 13:21:54.117221 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
720 13:21:54.117718 [EMI DOE] emi_dcm 0
721 13:21:54.121330 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
722 13:21:54.124921 ==
723 13:21:54.125354 Dram Type= 6, Freq= 0, CH_0, rank 0
724 13:21:54.128873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
725 13:21:54.132552 ==
726 13:21:54.136043 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
727 13:21:54.143364 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
728 13:21:54.151058 [CA 0] Center 38 (7~69) winsize 63
729 13:21:54.155529 [CA 1] Center 38 (7~69) winsize 63
730 13:21:54.159348 [CA 2] Center 35 (5~66) winsize 62
731 13:21:54.162612 [CA 3] Center 35 (5~66) winsize 62
732 13:21:54.165866 [CA 4] Center 34 (4~65) winsize 62
733 13:21:54.166302 [CA 5] Center 34 (4~64) winsize 61
734 13:21:54.170058
735 13:21:54.173915 [CmdBusTrainingLP45] Vref(ca) range 1: 32
736 13:21:54.174510
737 13:21:54.177519 [CATrainingPosCal] consider 1 rank data
738 13:21:54.178116 u2DelayCellTimex100 = 270/100 ps
739 13:21:54.180947 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
740 13:21:54.184462 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
741 13:21:54.188346 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
742 13:21:54.192725 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
743 13:21:54.196014 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
744 13:21:54.200136 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
745 13:21:54.200568
746 13:21:54.204008 CA PerBit enable=1, Macro0, CA PI delay=34
747 13:21:54.204544
748 13:21:54.207837 [CBTSetCACLKResult] CA Dly = 34
749 13:21:54.208472 CS Dly: 6 (0~37)
750 13:21:54.208853 ==
751 13:21:54.211329 Dram Type= 6, Freq= 0, CH_0, rank 1
752 13:21:54.215555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
753 13:21:54.215991 ==
754 13:21:54.222961 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
755 13:21:54.229813 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
756 13:21:54.237578 [CA 0] Center 38 (7~69) winsize 63
757 13:21:54.241516 [CA 1] Center 37 (7~68) winsize 62
758 13:21:54.244317 [CA 2] Center 35 (5~66) winsize 62
759 13:21:54.247772 [CA 3] Center 35 (5~66) winsize 62
760 13:21:54.251022 [CA 4] Center 34 (4~65) winsize 62
761 13:21:54.254786 [CA 5] Center 34 (4~65) winsize 62
762 13:21:54.255235
763 13:21:54.257826 [CmdBusTrainingLP45] Vref(ca) range 1: 30
764 13:21:54.258252
765 13:21:54.261042 [CATrainingPosCal] consider 2 rank data
766 13:21:54.264289 u2DelayCellTimex100 = 270/100 ps
767 13:21:54.267849 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
768 13:21:54.270856 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
769 13:21:54.274398 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
770 13:21:54.277676 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
771 13:21:54.284805 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
772 13:21:54.288033 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
773 13:21:54.288460
774 13:21:54.290929 CA PerBit enable=1, Macro0, CA PI delay=34
775 13:21:54.291449
776 13:21:54.295114 [CBTSetCACLKResult] CA Dly = 34
777 13:21:54.295813 CS Dly: 6 (0~38)
778 13:21:54.296166
779 13:21:54.297618 ----->DramcWriteLeveling(PI) begin...
780 13:21:54.298256 ==
781 13:21:54.301279 Dram Type= 6, Freq= 0, CH_0, rank 0
782 13:21:54.307920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 13:21:54.308493 ==
784 13:21:54.310913 Write leveling (Byte 0): 32 => 32
785 13:21:54.311472 Write leveling (Byte 1): 32 => 32
786 13:21:54.314252 DramcWriteLeveling(PI) end<-----
787 13:21:54.314734
788 13:21:54.317365 ==
789 13:21:54.317937 Dram Type= 6, Freq= 0, CH_0, rank 0
790 13:21:54.324037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
791 13:21:54.324583 ==
792 13:21:54.327489 [Gating] SW mode calibration
793 13:21:54.334023 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
794 13:21:54.337880 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
795 13:21:54.344226 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
796 13:21:54.347727 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
797 13:21:54.350644 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
798 13:21:54.357741 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
799 13:21:54.361075 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 13:21:54.364211 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 13:21:54.370901 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 13:21:54.374699 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 13:21:54.378320 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 13:21:54.382176 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 13:21:54.385634 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 13:21:54.392911 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 13:21:54.396154 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 13:21:54.399705 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 13:21:54.403581 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 13:21:54.410563 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 13:21:54.413814 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 13:21:54.417256 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 13:21:54.420209 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
814 13:21:54.427029 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 13:21:54.430593 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 13:21:54.433517 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 13:21:54.440121 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 13:21:54.443795 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 13:21:54.446597 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 13:21:54.453272 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 13:21:54.456911 0 9 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
822 13:21:54.459824 0 9 12 | B1->B0 | 2727 3232 | 0 0 | (0 0) (0 0)
823 13:21:54.467062 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
824 13:21:54.470589 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
825 13:21:54.473513 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
826 13:21:54.480217 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
827 13:21:54.483447 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
828 13:21:54.486727 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
829 13:21:54.493566 0 10 8 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 0)
830 13:21:54.497037 0 10 12 | B1->B0 | 2f2f 2424 | 1 0 | (1 0) (0 0)
831 13:21:54.500409 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 13:21:54.506935 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 13:21:54.510045 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 13:21:54.513600 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 13:21:54.520280 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 13:21:54.523892 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 13:21:54.527112 0 11 8 | B1->B0 | 2525 2e2e | 0 1 | (0 0) (0 0)
838 13:21:54.530931 0 11 12 | B1->B0 | 3939 3f3f | 0 1 | (0 0) (0 0)
839 13:21:54.537614 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
840 13:21:54.540643 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
841 13:21:54.543826 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
842 13:21:54.550400 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
843 13:21:54.554027 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
844 13:21:54.557077 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
845 13:21:54.563763 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
846 13:21:54.566706 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
847 13:21:54.570426 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 13:21:54.576928 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 13:21:54.580705 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 13:21:54.583830 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 13:21:54.590541 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 13:21:54.593380 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 13:21:54.596946 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 13:21:54.603690 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 13:21:54.606569 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 13:21:54.610023 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 13:21:54.616909 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 13:21:54.620606 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 13:21:54.623567 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 13:21:54.627028 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
861 13:21:54.633443 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
862 13:21:54.637259 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
863 13:21:54.640356 Total UI for P1: 0, mck2ui 16
864 13:21:54.643847 best dqsien dly found for B0: ( 0, 14, 6)
865 13:21:54.646832 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 13:21:54.650140 Total UI for P1: 0, mck2ui 16
867 13:21:54.652896 best dqsien dly found for B1: ( 0, 14, 10)
868 13:21:54.656755 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
869 13:21:54.660397 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
870 13:21:54.660514
871 13:21:54.666986 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
872 13:21:54.670331 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
873 13:21:54.670501 [Gating] SW calibration Done
874 13:21:54.673937 ==
875 13:21:54.677312 Dram Type= 6, Freq= 0, CH_0, rank 0
876 13:21:54.680397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
877 13:21:54.680622 ==
878 13:21:54.680742 RX Vref Scan: 0
879 13:21:54.680850
880 13:21:54.683997 RX Vref 0 -> 0, step: 1
881 13:21:54.684239
882 13:21:54.686984 RX Delay -130 -> 252, step: 16
883 13:21:54.690587 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
884 13:21:54.693502 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
885 13:21:54.697188 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
886 13:21:54.704205 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
887 13:21:54.706914 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
888 13:21:54.710136 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
889 13:21:54.713507 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
890 13:21:54.716855 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
891 13:21:54.723428 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
892 13:21:54.726859 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
893 13:21:54.730331 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
894 13:21:54.733693 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
895 13:21:54.736998 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
896 13:21:54.743867 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
897 13:21:54.747311 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
898 13:21:54.750125 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
899 13:21:54.750688 ==
900 13:21:54.753723 Dram Type= 6, Freq= 0, CH_0, rank 0
901 13:21:54.757591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
902 13:21:54.760593 ==
903 13:21:54.761245 DQS Delay:
904 13:21:54.761731 DQS0 = 0, DQS1 = 0
905 13:21:54.764139 DQM Delay:
906 13:21:54.764561 DQM0 = 81, DQM1 = 70
907 13:21:54.764968 DQ Delay:
908 13:21:54.766878 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
909 13:21:54.770543 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
910 13:21:54.774058 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
911 13:21:54.776877 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
912 13:21:54.777301
913 13:21:54.777638
914 13:21:54.780943 ==
915 13:21:54.781462 Dram Type= 6, Freq= 0, CH_0, rank 0
916 13:21:54.787631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
917 13:21:54.788140 ==
918 13:21:54.788485
919 13:21:54.788794
920 13:21:54.789187 TX Vref Scan disable
921 13:21:54.791480 == TX Byte 0 ==
922 13:21:54.794753 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
923 13:21:54.801440 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
924 13:21:54.801966 == TX Byte 1 ==
925 13:21:54.804396 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
926 13:21:54.808135 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
927 13:21:54.811847 ==
928 13:21:54.814460 Dram Type= 6, Freq= 0, CH_0, rank 0
929 13:21:54.818044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
930 13:21:54.818470 ==
931 13:21:54.829852 TX Vref=22, minBit 3, minWin=26, winSum=431
932 13:21:54.833499 TX Vref=24, minBit 0, minWin=27, winSum=438
933 13:21:54.836702 TX Vref=26, minBit 14, minWin=26, winSum=438
934 13:21:54.840443 TX Vref=28, minBit 3, minWin=27, winSum=445
935 13:21:54.843256 TX Vref=30, minBit 5, minWin=27, winSum=443
936 13:21:54.846782 TX Vref=32, minBit 1, minWin=27, winSum=440
937 13:21:54.853558 [TxChooseVref] Worse bit 3, Min win 27, Win sum 445, Final Vref 28
938 13:21:54.854026
939 13:21:54.857098 Final TX Range 1 Vref 28
940 13:21:54.857530
941 13:21:54.858015 ==
942 13:21:54.860365 Dram Type= 6, Freq= 0, CH_0, rank 0
943 13:21:54.863210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
944 13:21:54.863827 ==
945 13:21:54.864177
946 13:21:54.866900
947 13:21:54.867514 TX Vref Scan disable
948 13:21:54.869789 == TX Byte 0 ==
949 13:21:54.873501 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
950 13:21:54.876872 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
951 13:21:54.879934 == TX Byte 1 ==
952 13:21:54.883821 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
953 13:21:54.886677 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
954 13:21:54.890114
955 13:21:54.890539 [DATLAT]
956 13:21:54.890879 Freq=800, CH0 RK0
957 13:21:54.891243
958 13:21:54.893634 DATLAT Default: 0xa
959 13:21:54.894064 0, 0xFFFF, sum = 0
960 13:21:54.896633 1, 0xFFFF, sum = 0
961 13:21:54.897090 2, 0xFFFF, sum = 0
962 13:21:54.899969 3, 0xFFFF, sum = 0
963 13:21:54.900408 4, 0xFFFF, sum = 0
964 13:21:54.903517 5, 0xFFFF, sum = 0
965 13:21:54.906680 6, 0xFFFF, sum = 0
966 13:21:54.907164 7, 0xFFFF, sum = 0
967 13:21:54.910022 8, 0xFFFF, sum = 0
968 13:21:54.910458 9, 0x0, sum = 1
969 13:21:54.910802 10, 0x0, sum = 2
970 13:21:54.913363 11, 0x0, sum = 3
971 13:21:54.913956 12, 0x0, sum = 4
972 13:21:54.916630 best_step = 10
973 13:21:54.917061
974 13:21:54.917397 ==
975 13:21:54.920345 Dram Type= 6, Freq= 0, CH_0, rank 0
976 13:21:54.923427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
977 13:21:54.923864 ==
978 13:21:54.926999 RX Vref Scan: 1
979 13:21:54.927482
980 13:21:54.927829 Set Vref Range= 32 -> 127
981 13:21:54.928149
982 13:21:54.930477 RX Vref 32 -> 127, step: 1
983 13:21:54.930950
984 13:21:54.933286 RX Delay -111 -> 252, step: 8
985 13:21:54.933716
986 13:21:54.936881 Set Vref, RX VrefLevel [Byte0]: 32
987 13:21:54.940073 [Byte1]: 32
988 13:21:54.940501
989 13:21:54.943829 Set Vref, RX VrefLevel [Byte0]: 33
990 13:21:54.946991 [Byte1]: 33
991 13:21:54.950591
992 13:21:54.951120 Set Vref, RX VrefLevel [Byte0]: 34
993 13:21:54.953974 [Byte1]: 34
994 13:21:54.958061
995 13:21:54.958488 Set Vref, RX VrefLevel [Byte0]: 35
996 13:21:54.961426 [Byte1]: 35
997 13:21:54.965611
998 13:21:54.966064 Set Vref, RX VrefLevel [Byte0]: 36
999 13:21:54.969138 [Byte1]: 36
1000 13:21:54.973515
1001 13:21:54.974052 Set Vref, RX VrefLevel [Byte0]: 37
1002 13:21:54.976792 [Byte1]: 37
1003 13:21:54.980859
1004 13:21:54.981286 Set Vref, RX VrefLevel [Byte0]: 38
1005 13:21:54.984366 [Byte1]: 38
1006 13:21:54.989101
1007 13:21:54.989530 Set Vref, RX VrefLevel [Byte0]: 39
1008 13:21:54.991988 [Byte1]: 39
1009 13:21:54.996961
1010 13:21:54.997388 Set Vref, RX VrefLevel [Byte0]: 40
1011 13:21:54.999692 [Byte1]: 40
1012 13:21:55.003993
1013 13:21:55.004421 Set Vref, RX VrefLevel [Byte0]: 41
1014 13:21:55.007173 [Byte1]: 41
1015 13:21:55.011240
1016 13:21:55.011323 Set Vref, RX VrefLevel [Byte0]: 42
1017 13:21:55.014577 [Byte1]: 42
1018 13:21:55.018866
1019 13:21:55.018955 Set Vref, RX VrefLevel [Byte0]: 43
1020 13:21:55.022577 [Byte1]: 43
1021 13:21:55.026629
1022 13:21:55.026805 Set Vref, RX VrefLevel [Byte0]: 44
1023 13:21:55.030001 [Byte1]: 44
1024 13:21:55.034199
1025 13:21:55.034318 Set Vref, RX VrefLevel [Byte0]: 45
1026 13:21:55.037758 [Byte1]: 45
1027 13:21:55.042672
1028 13:21:55.042796 Set Vref, RX VrefLevel [Byte0]: 46
1029 13:21:55.045852 [Byte1]: 46
1030 13:21:55.050361
1031 13:21:55.050812 Set Vref, RX VrefLevel [Byte0]: 47
1032 13:21:55.053529 [Byte1]: 47
1033 13:21:55.057751
1034 13:21:55.058163 Set Vref, RX VrefLevel [Byte0]: 48
1035 13:21:55.061522 [Byte1]: 48
1036 13:21:55.065750
1037 13:21:55.066161 Set Vref, RX VrefLevel [Byte0]: 49
1038 13:21:55.069070 [Byte1]: 49
1039 13:21:55.073239
1040 13:21:55.073659 Set Vref, RX VrefLevel [Byte0]: 50
1041 13:21:55.076613 [Byte1]: 50
1042 13:21:55.080600
1043 13:21:55.081019 Set Vref, RX VrefLevel [Byte0]: 51
1044 13:21:55.083650 [Byte1]: 51
1045 13:21:55.088518
1046 13:21:55.089032 Set Vref, RX VrefLevel [Byte0]: 52
1047 13:21:55.091555 [Byte1]: 52
1048 13:21:55.095665
1049 13:21:55.096272 Set Vref, RX VrefLevel [Byte0]: 53
1050 13:21:55.099173 [Byte1]: 53
1051 13:21:55.103417
1052 13:21:55.104000 Set Vref, RX VrefLevel [Byte0]: 54
1053 13:21:55.106680 [Byte1]: 54
1054 13:21:55.111052
1055 13:21:55.111608 Set Vref, RX VrefLevel [Byte0]: 55
1056 13:21:55.114158 [Byte1]: 55
1057 13:21:55.118809
1058 13:21:55.119359 Set Vref, RX VrefLevel [Byte0]: 56
1059 13:21:55.122168 [Byte1]: 56
1060 13:21:55.126717
1061 13:21:55.127430 Set Vref, RX VrefLevel [Byte0]: 57
1062 13:21:55.129474 [Byte1]: 57
1063 13:21:55.133987
1064 13:21:55.134595 Set Vref, RX VrefLevel [Byte0]: 58
1065 13:21:55.137507 [Byte1]: 58
1066 13:21:55.141947
1067 13:21:55.142426 Set Vref, RX VrefLevel [Byte0]: 59
1068 13:21:55.145157 [Byte1]: 59
1069 13:21:55.149590
1070 13:21:55.150099 Set Vref, RX VrefLevel [Byte0]: 60
1071 13:21:55.152845 [Byte1]: 60
1072 13:21:55.157251
1073 13:21:55.157820 Set Vref, RX VrefLevel [Byte0]: 61
1074 13:21:55.160074 [Byte1]: 61
1075 13:21:55.164491
1076 13:21:55.165074 Set Vref, RX VrefLevel [Byte0]: 62
1077 13:21:55.167845 [Byte1]: 62
1078 13:21:55.172038
1079 13:21:55.172533 Set Vref, RX VrefLevel [Byte0]: 63
1080 13:21:55.175668 [Byte1]: 63
1081 13:21:55.179891
1082 13:21:55.180343 Set Vref, RX VrefLevel [Byte0]: 64
1083 13:21:55.182966 [Byte1]: 64
1084 13:21:55.187617
1085 13:21:55.188032 Set Vref, RX VrefLevel [Byte0]: 65
1086 13:21:55.190892 [Byte1]: 65
1087 13:21:55.194917
1088 13:21:55.195333 Set Vref, RX VrefLevel [Byte0]: 66
1089 13:21:55.198725 [Byte1]: 66
1090 13:21:55.203199
1091 13:21:55.203762 Set Vref, RX VrefLevel [Byte0]: 67
1092 13:21:55.206256 [Byte1]: 67
1093 13:21:55.210925
1094 13:21:55.211483 Set Vref, RX VrefLevel [Byte0]: 68
1095 13:21:55.213791 [Byte1]: 68
1096 13:21:55.218570
1097 13:21:55.219086 Set Vref, RX VrefLevel [Byte0]: 69
1098 13:21:55.221545 [Byte1]: 69
1099 13:21:55.225847
1100 13:21:55.226462 Set Vref, RX VrefLevel [Byte0]: 70
1101 13:21:55.229100 [Byte1]: 70
1102 13:21:55.233684
1103 13:21:55.234124 Set Vref, RX VrefLevel [Byte0]: 71
1104 13:21:55.236608 [Byte1]: 71
1105 13:21:55.241413
1106 13:21:55.241826 Set Vref, RX VrefLevel [Byte0]: 72
1107 13:21:55.244534 [Byte1]: 72
1108 13:21:55.248426
1109 13:21:55.248841 Set Vref, RX VrefLevel [Byte0]: 73
1110 13:21:55.251953 [Byte1]: 73
1111 13:21:55.256634
1112 13:21:55.257223 Set Vref, RX VrefLevel [Byte0]: 74
1113 13:21:55.259412 [Byte1]: 74
1114 13:21:55.263889
1115 13:21:55.264503 Set Vref, RX VrefLevel [Byte0]: 75
1116 13:21:55.267319 [Byte1]: 75
1117 13:21:55.271639
1118 13:21:55.272092 Set Vref, RX VrefLevel [Byte0]: 76
1119 13:21:55.274618 [Byte1]: 76
1120 13:21:55.279574
1121 13:21:55.279997 Set Vref, RX VrefLevel [Byte0]: 77
1122 13:21:55.282781 [Byte1]: 77
1123 13:21:55.286601
1124 13:21:55.287024 Set Vref, RX VrefLevel [Byte0]: 78
1125 13:21:55.290100 [Byte1]: 78
1126 13:21:55.294832
1127 13:21:55.295257 Set Vref, RX VrefLevel [Byte0]: 79
1128 13:21:55.297962 [Byte1]: 79
1129 13:21:55.302229
1130 13:21:55.302650 Set Vref, RX VrefLevel [Byte0]: 80
1131 13:21:55.305342 [Byte1]: 80
1132 13:21:55.309476
1133 13:21:55.309558 Final RX Vref Byte 0 = 64 to rank0
1134 13:21:55.312801 Final RX Vref Byte 1 = 56 to rank0
1135 13:21:55.316197 Final RX Vref Byte 0 = 64 to rank1
1136 13:21:55.319753 Final RX Vref Byte 1 = 56 to rank1==
1137 13:21:55.323325 Dram Type= 6, Freq= 0, CH_0, rank 0
1138 13:21:55.329499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1139 13:21:55.329671 ==
1140 13:21:55.329758 DQS Delay:
1141 13:21:55.329834 DQS0 = 0, DQS1 = 0
1142 13:21:55.332983 DQM Delay:
1143 13:21:55.333123 DQM0 = 81, DQM1 = 67
1144 13:21:55.336636 DQ Delay:
1145 13:21:55.339821 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1146 13:21:55.340013 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1147 13:21:55.343050 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1148 13:21:55.349899 DQ12 =72, DQ13 =72, DQ14 =76, DQ15 =76
1149 13:21:55.350117
1150 13:21:55.350236
1151 13:21:55.356365 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a2a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
1152 13:21:55.359318 CH0 RK0: MR19=606, MR18=2A2A
1153 13:21:55.366419 CH0_RK0: MR19=0x606, MR18=0x2A2A, DQSOSC=399, MR23=63, INC=92, DEC=61
1154 13:21:55.366845
1155 13:21:55.369826 ----->DramcWriteLeveling(PI) begin...
1156 13:21:55.370259 ==
1157 13:21:55.373195 Dram Type= 6, Freq= 0, CH_0, rank 1
1158 13:21:55.376099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1159 13:21:55.376592 ==
1160 13:21:55.379522 Write leveling (Byte 0): 32 => 32
1161 13:21:55.383474 Write leveling (Byte 1): 31 => 31
1162 13:21:55.386624 DramcWriteLeveling(PI) end<-----
1163 13:21:55.387048
1164 13:21:55.387423 ==
1165 13:21:55.389973 Dram Type= 6, Freq= 0, CH_0, rank 1
1166 13:21:55.393398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1167 13:21:55.393829 ==
1168 13:21:55.396500 [Gating] SW mode calibration
1169 13:21:55.403149 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1170 13:21:55.409491 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1171 13:21:55.413427 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1172 13:21:55.416308 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1173 13:21:55.422873 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1174 13:21:55.426110 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 13:21:55.429833 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 13:21:55.436205 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 13:21:55.439724 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 13:21:55.442877 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 13:21:55.449584 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 13:21:55.453224 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 13:21:55.456411 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 13:21:55.503518 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 13:21:55.504293 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 13:21:55.504765 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 13:21:55.505545 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 13:21:55.505899 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 13:21:55.506214 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 13:21:55.506519 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1189 13:21:55.506819 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1190 13:21:55.507112 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 13:21:55.507435 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 13:21:55.547941 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 13:21:55.548404 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 13:21:55.549059 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 13:21:55.549404 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 13:21:55.549770 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 13:21:55.550083 0 9 8 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
1198 13:21:55.550377 0 9 12 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1199 13:21:55.550724 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1200 13:21:55.551024 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1201 13:21:55.551309 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1202 13:21:55.551634 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1203 13:21:55.577292 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1204 13:21:55.578024 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1205 13:21:55.578408 0 10 8 | B1->B0 | 3030 2b2b | 1 0 | (1 0) (1 0)
1206 13:21:55.578853 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1207 13:21:55.579298 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 13:21:55.579805 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 13:21:55.581436 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 13:21:55.585146 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 13:21:55.588316 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 13:21:55.594910 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1213 13:21:55.598205 0 11 8 | B1->B0 | 3232 3c3b | 0 1 | (1 1) (0 0)
1214 13:21:55.601875 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1215 13:21:55.608312 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1216 13:21:55.611781 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1217 13:21:55.614890 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1218 13:21:55.618718 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 13:21:55.626257 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1220 13:21:55.629581 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1221 13:21:55.633291 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1222 13:21:55.636655 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1223 13:21:55.643615 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 13:21:55.647073 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 13:21:55.650847 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 13:21:55.653869 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 13:21:55.660405 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 13:21:55.663990 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 13:21:55.667617 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 13:21:55.670723 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 13:21:55.677682 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1232 13:21:55.680749 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1233 13:21:55.684166 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1234 13:21:55.690848 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1235 13:21:55.693902 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1236 13:21:55.697358 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1237 13:21:55.703916 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1238 13:21:55.707468 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1239 13:21:55.710689 Total UI for P1: 0, mck2ui 16
1240 13:21:55.714280 best dqsien dly found for B0: ( 0, 14, 8)
1241 13:21:55.717837 Total UI for P1: 0, mck2ui 16
1242 13:21:55.720987 best dqsien dly found for B1: ( 0, 14, 8)
1243 13:21:55.724281 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1244 13:21:55.727510 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1245 13:21:55.728029
1246 13:21:55.730920 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1247 13:21:55.734571 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1248 13:21:55.737668 [Gating] SW calibration Done
1249 13:21:55.738185 ==
1250 13:21:55.740844 Dram Type= 6, Freq= 0, CH_0, rank 1
1251 13:21:55.744946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1252 13:21:55.745466 ==
1253 13:21:55.747442 RX Vref Scan: 0
1254 13:21:55.747860
1255 13:21:55.751013 RX Vref 0 -> 0, step: 1
1256 13:21:55.751613
1257 13:21:55.751966 RX Delay -130 -> 252, step: 16
1258 13:21:55.757606 iDelay=222, Bit 0, Center 77 (-34 ~ 189) 224
1259 13:21:55.760613 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1260 13:21:55.764440 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1261 13:21:55.767514 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1262 13:21:55.770860 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1263 13:21:55.777669 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1264 13:21:55.780614 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1265 13:21:55.784349 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1266 13:21:55.787586 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1267 13:21:55.790820 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1268 13:21:55.797596 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1269 13:21:55.800607 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1270 13:21:55.803914 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1271 13:21:55.807444 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1272 13:21:55.811112 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1273 13:21:55.817735 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1274 13:21:55.818154 ==
1275 13:21:55.820781 Dram Type= 6, Freq= 0, CH_0, rank 1
1276 13:21:55.824249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1277 13:21:55.824694 ==
1278 13:21:55.825032 DQS Delay:
1279 13:21:55.828012 DQS0 = 0, DQS1 = 0
1280 13:21:55.828431 DQM Delay:
1281 13:21:55.831118 DQM0 = 79, DQM1 = 69
1282 13:21:55.831578 DQ Delay:
1283 13:21:55.833928 DQ0 =77, DQ1 =85, DQ2 =69, DQ3 =69
1284 13:21:55.837613 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =101
1285 13:21:55.841117 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1286 13:21:55.844587 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1287 13:21:55.845216
1288 13:21:55.845558
1289 13:21:55.845864 ==
1290 13:21:55.847712 Dram Type= 6, Freq= 0, CH_0, rank 1
1291 13:21:55.851182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1292 13:21:55.854304 ==
1293 13:21:55.854822
1294 13:21:55.855193
1295 13:21:55.855647 TX Vref Scan disable
1296 13:21:55.858054 == TX Byte 0 ==
1297 13:21:55.861200 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1298 13:21:55.864145 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1299 13:21:55.868108 == TX Byte 1 ==
1300 13:21:55.870972 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1301 13:21:55.874781 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1302 13:21:55.875308 ==
1303 13:21:55.877449 Dram Type= 6, Freq= 0, CH_0, rank 1
1304 13:21:55.884259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1305 13:21:55.884681 ==
1306 13:21:55.896179 TX Vref=22, minBit 9, minWin=26, winSum=433
1307 13:21:55.899543 TX Vref=24, minBit 9, minWin=26, winSum=439
1308 13:21:55.902631 TX Vref=26, minBit 11, minWin=26, winSum=441
1309 13:21:55.905783 TX Vref=28, minBit 1, minWin=27, winSum=440
1310 13:21:55.909243 TX Vref=30, minBit 1, minWin=27, winSum=441
1311 13:21:55.915923 TX Vref=32, minBit 15, minWin=26, winSum=440
1312 13:21:55.919472 [TxChooseVref] Worse bit 1, Min win 27, Win sum 441, Final Vref 30
1313 13:21:55.919895
1314 13:21:55.923059 Final TX Range 1 Vref 30
1315 13:21:55.923519
1316 13:21:55.923854 ==
1317 13:21:55.926103 Dram Type= 6, Freq= 0, CH_0, rank 1
1318 13:21:55.930048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1319 13:21:55.930466 ==
1320 13:21:55.932456
1321 13:21:55.932866
1322 13:21:55.933191 TX Vref Scan disable
1323 13:21:55.936170 == TX Byte 0 ==
1324 13:21:55.939770 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1325 13:21:55.942699 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1326 13:21:55.946085 == TX Byte 1 ==
1327 13:21:55.949696 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1328 13:21:55.953124 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1329 13:21:55.956649
1330 13:21:55.957218 [DATLAT]
1331 13:21:55.957764 Freq=800, CH0 RK1
1332 13:21:55.958230
1333 13:21:55.959900 DATLAT Default: 0xa
1334 13:21:55.960462 0, 0xFFFF, sum = 0
1335 13:21:55.962827 1, 0xFFFF, sum = 0
1336 13:21:55.963334 2, 0xFFFF, sum = 0
1337 13:21:55.966224 3, 0xFFFF, sum = 0
1338 13:21:55.966842 4, 0xFFFF, sum = 0
1339 13:21:55.969700 5, 0xFFFF, sum = 0
1340 13:21:55.970278 6, 0xFFFF, sum = 0
1341 13:21:55.973254 7, 0xFFFF, sum = 0
1342 13:21:55.976281 8, 0xFFFF, sum = 0
1343 13:21:55.976720 9, 0x0, sum = 1
1344 13:21:55.977064 10, 0x0, sum = 2
1345 13:21:55.979868 11, 0x0, sum = 3
1346 13:21:55.980289 12, 0x0, sum = 4
1347 13:21:55.983267 best_step = 10
1348 13:21:55.983755
1349 13:21:55.984087 ==
1350 13:21:55.986411 Dram Type= 6, Freq= 0, CH_0, rank 1
1351 13:21:55.990019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1352 13:21:55.990448 ==
1353 13:21:55.993002 RX Vref Scan: 0
1354 13:21:55.993418
1355 13:21:55.993746 RX Vref 0 -> 0, step: 1
1356 13:21:55.994051
1357 13:21:55.995901 RX Delay -111 -> 252, step: 8
1358 13:21:56.003198 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1359 13:21:56.007011 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1360 13:21:56.009930 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1361 13:21:56.013251 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1362 13:21:56.016051 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1363 13:21:56.022979 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1364 13:21:56.026319 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1365 13:21:56.029657 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1366 13:21:56.033304 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1367 13:21:56.036439 iDelay=209, Bit 9, Center 52 (-63 ~ 168) 232
1368 13:21:56.043266 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1369 13:21:56.046714 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1370 13:21:56.049649 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1371 13:21:56.053274 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1372 13:21:56.056294 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1373 13:21:56.064760 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1374 13:21:56.065415 ==
1375 13:21:56.066301 Dram Type= 6, Freq= 0, CH_0, rank 1
1376 13:21:56.069667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 13:21:56.070093 ==
1378 13:21:56.070425 DQS Delay:
1379 13:21:56.072704 DQS0 = 0, DQS1 = 0
1380 13:21:56.073254 DQM Delay:
1381 13:21:56.076433 DQM0 = 79, DQM1 = 69
1382 13:21:56.076879 DQ Delay:
1383 13:21:56.079525 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1384 13:21:56.083093 DQ4 =76, DQ5 =64, DQ6 =92, DQ7 =92
1385 13:21:56.086136 DQ8 =60, DQ9 =52, DQ10 =72, DQ11 =64
1386 13:21:56.089757 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =76
1387 13:21:56.090245
1388 13:21:56.090597
1389 13:21:56.096369 [DQSOSCAuto] RK1, (LSB)MR18= 0x4520, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
1390 13:21:56.099110 CH0 RK1: MR19=606, MR18=4520
1391 13:21:56.105651 CH0_RK1: MR19=0x606, MR18=0x4520, DQSOSC=392, MR23=63, INC=96, DEC=64
1392 13:21:56.109114 [RxdqsGatingPostProcess] freq 800
1393 13:21:56.116112 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1394 13:21:56.119071 Pre-setting of DQS Precalculation
1395 13:21:56.122629 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1396 13:21:56.122717 ==
1397 13:21:56.126222 Dram Type= 6, Freq= 0, CH_1, rank 0
1398 13:21:56.129402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1399 13:21:56.129532 ==
1400 13:21:56.135847 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1401 13:21:56.142302 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1402 13:21:56.151593 [CA 0] Center 36 (6~66) winsize 61
1403 13:21:56.154238 [CA 1] Center 36 (6~67) winsize 62
1404 13:21:56.157664 [CA 2] Center 34 (5~64) winsize 60
1405 13:21:56.160818 [CA 3] Center 34 (4~64) winsize 61
1406 13:21:56.164289 [CA 4] Center 34 (4~64) winsize 61
1407 13:21:56.167350 [CA 5] Center 34 (4~64) winsize 61
1408 13:21:56.167584
1409 13:21:56.171313 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1410 13:21:56.171596
1411 13:21:56.174416 [CATrainingPosCal] consider 1 rank data
1412 13:21:56.177685 u2DelayCellTimex100 = 270/100 ps
1413 13:21:56.181028 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1414 13:21:56.184014 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1415 13:21:56.190848 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1416 13:21:56.194365 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1417 13:21:56.197409 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1418 13:21:56.200863 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1419 13:21:56.200964
1420 13:21:56.203899 CA PerBit enable=1, Macro0, CA PI delay=34
1421 13:21:56.203972
1422 13:21:56.207473 [CBTSetCACLKResult] CA Dly = 34
1423 13:21:56.207589 CS Dly: 5 (0~36)
1424 13:21:56.207656 ==
1425 13:21:56.210649 Dram Type= 6, Freq= 0, CH_1, rank 1
1426 13:21:56.217883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1427 13:21:56.217963 ==
1428 13:21:56.220678 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1429 13:21:56.227616 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1430 13:21:56.237307 [CA 0] Center 36 (6~67) winsize 62
1431 13:21:56.240449 [CA 1] Center 36 (6~67) winsize 62
1432 13:21:56.243596 [CA 2] Center 35 (5~65) winsize 61
1433 13:21:56.247247 [CA 3] Center 33 (3~64) winsize 62
1434 13:21:56.250148 [CA 4] Center 34 (4~65) winsize 62
1435 13:21:56.253408 [CA 5] Center 33 (3~64) winsize 62
1436 13:21:56.253501
1437 13:21:56.256919 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1438 13:21:56.257053
1439 13:21:56.260429 [CATrainingPosCal] consider 2 rank data
1440 13:21:56.263994 u2DelayCellTimex100 = 270/100 ps
1441 13:21:56.266942 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1442 13:21:56.270788 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1443 13:21:56.278063 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1444 13:21:56.278303 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1445 13:21:56.281581 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1446 13:21:56.284996 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1447 13:21:56.285171
1448 13:21:56.292608 CA PerBit enable=1, Macro0, CA PI delay=34
1449 13:21:56.292855
1450 13:21:56.293043 [CBTSetCACLKResult] CA Dly = 34
1451 13:21:56.296495 CS Dly: 6 (0~38)
1452 13:21:56.296757
1453 13:21:56.300009 ----->DramcWriteLeveling(PI) begin...
1454 13:21:56.300339 ==
1455 13:21:56.304068 Dram Type= 6, Freq= 0, CH_1, rank 0
1456 13:21:56.308159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1457 13:21:56.308580 ==
1458 13:21:56.311537 Write leveling (Byte 0): 29 => 29
1459 13:21:56.311997 Write leveling (Byte 1): 30 => 30
1460 13:21:56.314530 DramcWriteLeveling(PI) end<-----
1461 13:21:56.315045
1462 13:21:56.317924 ==
1463 13:21:56.318531 Dram Type= 6, Freq= 0, CH_1, rank 0
1464 13:21:56.324654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1465 13:21:56.325253 ==
1466 13:21:56.328143 [Gating] SW mode calibration
1467 13:21:56.334714 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1468 13:21:56.338200 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1469 13:21:56.344574 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1470 13:21:56.347710 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1471 13:21:56.351483 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1472 13:21:56.357565 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 13:21:56.360940 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 13:21:56.364555 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 13:21:56.368140 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 13:21:56.374667 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 13:21:56.378309 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 13:21:56.381399 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 13:21:56.387859 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 13:21:56.391192 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 13:21:56.394739 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 13:21:56.401315 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 13:21:56.404787 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 13:21:56.407718 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 13:21:56.414280 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 13:21:56.417815 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 13:21:56.421206 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1488 13:21:56.428034 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 13:21:56.431619 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 13:21:56.434546 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 13:21:56.441314 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 13:21:56.444919 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 13:21:56.447612 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 13:21:56.454337 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 13:21:56.457895 0 9 8 | B1->B0 | 2a2a 2525 | 0 0 | (0 0) (0 0)
1496 13:21:56.461046 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1497 13:21:56.464405 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1498 13:21:56.471498 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1499 13:21:56.474569 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1500 13:21:56.477473 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1501 13:21:56.484302 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1502 13:21:56.487618 0 10 4 | B1->B0 | 3434 3333 | 0 0 | (0 0) (0 0)
1503 13:21:56.491043 0 10 8 | B1->B0 | 2f2f 2c2c | 0 0 | (1 0) (1 0)
1504 13:21:56.497867 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 13:21:56.501175 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 13:21:56.504480 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 13:21:56.511130 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 13:21:56.514276 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 13:21:56.517712 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 13:21:56.524327 0 11 4 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
1511 13:21:56.527926 0 11 8 | B1->B0 | 3535 3636 | 0 0 | (0 0) (0 0)
1512 13:21:56.531525 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1513 13:21:56.538175 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 13:21:56.541094 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1515 13:21:56.544417 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1516 13:21:56.551234 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 13:21:56.554286 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1518 13:21:56.557791 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1519 13:21:56.561246 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1520 13:21:56.567902 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 13:21:56.571095 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 13:21:56.574453 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 13:21:56.580966 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 13:21:56.584363 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 13:21:56.587978 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 13:21:56.594779 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 13:21:56.598204 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 13:21:56.600988 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 13:21:56.607807 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 13:21:56.611092 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1531 13:21:56.614442 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1532 13:21:56.620620 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1533 13:21:56.624133 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1534 13:21:56.627228 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1535 13:21:56.633613 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1536 13:21:56.636977 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1537 13:21:56.640281 Total UI for P1: 0, mck2ui 16
1538 13:21:56.643731 best dqsien dly found for B0: ( 0, 14, 8)
1539 13:21:56.647081 Total UI for P1: 0, mck2ui 16
1540 13:21:56.650749 best dqsien dly found for B1: ( 0, 14, 8)
1541 13:21:56.653757 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1542 13:21:56.657664 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1543 13:21:56.658124
1544 13:21:56.660886 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1545 13:21:56.664202 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1546 13:21:56.667067 [Gating] SW calibration Done
1547 13:21:56.667545 ==
1548 13:21:56.670828 Dram Type= 6, Freq= 0, CH_1, rank 0
1549 13:21:56.674009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1550 13:21:56.674436 ==
1551 13:21:56.677451 RX Vref Scan: 0
1552 13:21:56.677936
1553 13:21:56.680802 RX Vref 0 -> 0, step: 1
1554 13:21:56.681227
1555 13:21:56.683972 RX Delay -130 -> 252, step: 16
1556 13:21:56.687306 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1557 13:21:56.690782 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1558 13:21:56.693738 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1559 13:21:56.697352 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1560 13:21:56.700641 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1561 13:21:56.707182 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1562 13:21:56.710850 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1563 13:21:56.713739 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1564 13:21:56.717353 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1565 13:21:56.720424 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1566 13:21:56.727525 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1567 13:21:56.730536 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1568 13:21:56.733691 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1569 13:21:56.737182 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1570 13:21:56.744221 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1571 13:21:56.747218 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1572 13:21:56.747741 ==
1573 13:21:56.750310 Dram Type= 6, Freq= 0, CH_1, rank 0
1574 13:21:56.754102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1575 13:21:56.754701 ==
1576 13:21:56.755260 DQS Delay:
1577 13:21:56.757471 DQS0 = 0, DQS1 = 0
1578 13:21:56.758116 DQM Delay:
1579 13:21:56.760324 DQM0 = 81, DQM1 = 71
1580 13:21:56.760896 DQ Delay:
1581 13:21:56.763815 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1582 13:21:56.767238 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1583 13:21:56.770692 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1584 13:21:56.774117 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1585 13:21:56.774626
1586 13:21:56.774966
1587 13:21:56.775296 ==
1588 13:21:56.777478 Dram Type= 6, Freq= 0, CH_1, rank 0
1589 13:21:56.780958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1590 13:21:56.784003 ==
1591 13:21:56.784426
1592 13:21:56.784817
1593 13:21:56.785137 TX Vref Scan disable
1594 13:21:56.787312 == TX Byte 0 ==
1595 13:21:56.790347 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1596 13:21:56.794273 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1597 13:21:56.797360 == TX Byte 1 ==
1598 13:21:56.800750 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1599 13:21:56.803630 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1600 13:21:56.804059 ==
1601 13:21:56.807220 Dram Type= 6, Freq= 0, CH_1, rank 0
1602 13:21:56.813855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1603 13:21:56.814286 ==
1604 13:21:56.825717 TX Vref=22, minBit 1, minWin=26, winSum=436
1605 13:21:56.829072 TX Vref=24, minBit 0, minWin=27, winSum=441
1606 13:21:56.832443 TX Vref=26, minBit 4, minWin=27, winSum=446
1607 13:21:56.835593 TX Vref=28, minBit 4, minWin=27, winSum=448
1608 13:21:56.838648 TX Vref=30, minBit 4, minWin=27, winSum=448
1609 13:21:56.845680 TX Vref=32, minBit 4, minWin=27, winSum=444
1610 13:21:56.848728 [TxChooseVref] Worse bit 4, Min win 27, Win sum 448, Final Vref 28
1611 13:21:56.849158
1612 13:21:56.852234 Final TX Range 1 Vref 28
1613 13:21:56.852661
1614 13:21:56.853000 ==
1615 13:21:56.856025 Dram Type= 6, Freq= 0, CH_1, rank 0
1616 13:21:56.859614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1617 13:21:56.860043 ==
1618 13:21:56.860379
1619 13:21:56.860689
1620 13:21:56.862939 TX Vref Scan disable
1621 13:21:56.866580 == TX Byte 0 ==
1622 13:21:56.869606 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1623 13:21:56.872923 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1624 13:21:56.876522 == TX Byte 1 ==
1625 13:21:56.879795 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1626 13:21:56.882677 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1627 13:21:56.882786
1628 13:21:56.886075 [DATLAT]
1629 13:21:56.886189 Freq=800, CH1 RK0
1630 13:21:56.886286
1631 13:21:56.889643 DATLAT Default: 0xa
1632 13:21:56.889749 0, 0xFFFF, sum = 0
1633 13:21:56.892609 1, 0xFFFF, sum = 0
1634 13:21:56.892707 2, 0xFFFF, sum = 0
1635 13:21:56.896078 3, 0xFFFF, sum = 0
1636 13:21:56.896201 4, 0xFFFF, sum = 0
1637 13:21:56.899362 5, 0xFFFF, sum = 0
1638 13:21:56.899460 6, 0xFFFF, sum = 0
1639 13:21:56.902487 7, 0xFFFF, sum = 0
1640 13:21:56.902561 8, 0xFFFF, sum = 0
1641 13:21:56.906067 9, 0x0, sum = 1
1642 13:21:56.906139 10, 0x0, sum = 2
1643 13:21:56.909213 11, 0x0, sum = 3
1644 13:21:56.909329 12, 0x0, sum = 4
1645 13:21:56.912552 best_step = 10
1646 13:21:56.912632
1647 13:21:56.912698 ==
1648 13:21:56.916250 Dram Type= 6, Freq= 0, CH_1, rank 0
1649 13:21:56.919125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1650 13:21:56.919222 ==
1651 13:21:56.919289 RX Vref Scan: 1
1652 13:21:56.922341
1653 13:21:56.922427 Set Vref Range= 32 -> 127
1654 13:21:56.922492
1655 13:21:56.925783 RX Vref 32 -> 127, step: 1
1656 13:21:56.925865
1657 13:21:56.929392 RX Delay -111 -> 252, step: 8
1658 13:21:56.929474
1659 13:21:56.932739 Set Vref, RX VrefLevel [Byte0]: 32
1660 13:21:56.935781 [Byte1]: 32
1661 13:21:56.935864
1662 13:21:56.939552 Set Vref, RX VrefLevel [Byte0]: 33
1663 13:21:56.942540 [Byte1]: 33
1664 13:21:56.945864
1665 13:21:56.945961 Set Vref, RX VrefLevel [Byte0]: 34
1666 13:21:56.949203 [Byte1]: 34
1667 13:21:56.953386
1668 13:21:56.953469 Set Vref, RX VrefLevel [Byte0]: 35
1669 13:21:56.957034 [Byte1]: 35
1670 13:21:56.960870
1671 13:21:56.960954 Set Vref, RX VrefLevel [Byte0]: 36
1672 13:21:56.967512 [Byte1]: 36
1673 13:21:56.967596
1674 13:21:56.971032 Set Vref, RX VrefLevel [Byte0]: 37
1675 13:21:56.974037 [Byte1]: 37
1676 13:21:56.974144
1677 13:21:56.978087 Set Vref, RX VrefLevel [Byte0]: 38
1678 13:21:56.980856 [Byte1]: 38
1679 13:21:56.980935
1680 13:21:56.983960 Set Vref, RX VrefLevel [Byte0]: 39
1681 13:21:56.987394 [Byte1]: 39
1682 13:21:56.991668
1683 13:21:56.991746 Set Vref, RX VrefLevel [Byte0]: 40
1684 13:21:56.995349 [Byte1]: 40
1685 13:21:56.999128
1686 13:21:56.999204 Set Vref, RX VrefLevel [Byte0]: 41
1687 13:21:57.002797 [Byte1]: 41
1688 13:21:57.006884
1689 13:21:57.006965 Set Vref, RX VrefLevel [Byte0]: 42
1690 13:21:57.009964 [Byte1]: 42
1691 13:21:57.014709
1692 13:21:57.014785 Set Vref, RX VrefLevel [Byte0]: 43
1693 13:21:57.017792 [Byte1]: 43
1694 13:21:57.022022
1695 13:21:57.022101 Set Vref, RX VrefLevel [Byte0]: 44
1696 13:21:57.025291 [Byte1]: 44
1697 13:21:57.030168
1698 13:21:57.030286 Set Vref, RX VrefLevel [Byte0]: 45
1699 13:21:57.033435 [Byte1]: 45
1700 13:21:57.038065
1701 13:21:57.038489 Set Vref, RX VrefLevel [Byte0]: 46
1702 13:21:57.041064 [Byte1]: 46
1703 13:21:57.045432
1704 13:21:57.046031 Set Vref, RX VrefLevel [Byte0]: 47
1705 13:21:57.048757 [Byte1]: 47
1706 13:21:57.053079
1707 13:21:57.053530 Set Vref, RX VrefLevel [Byte0]: 48
1708 13:21:57.056447 [Byte1]: 48
1709 13:21:57.061306
1710 13:21:57.061882 Set Vref, RX VrefLevel [Byte0]: 49
1711 13:21:57.064159 [Byte1]: 49
1712 13:21:57.068503
1713 13:21:57.069028 Set Vref, RX VrefLevel [Byte0]: 50
1714 13:21:57.071997 [Byte1]: 50
1715 13:21:57.076086
1716 13:21:57.076510 Set Vref, RX VrefLevel [Byte0]: 51
1717 13:21:57.079014 [Byte1]: 51
1718 13:21:57.083574
1719 13:21:57.083681 Set Vref, RX VrefLevel [Byte0]: 52
1720 13:21:57.086651 [Byte1]: 52
1721 13:21:57.091276
1722 13:21:57.091359 Set Vref, RX VrefLevel [Byte0]: 53
1723 13:21:57.094364 [Byte1]: 53
1724 13:21:57.098643
1725 13:21:57.098731 Set Vref, RX VrefLevel [Byte0]: 54
1726 13:21:57.102077 [Byte1]: 54
1727 13:21:57.106126
1728 13:21:57.106220 Set Vref, RX VrefLevel [Byte0]: 55
1729 13:21:57.109895 [Byte1]: 55
1730 13:21:57.114383
1731 13:21:57.114495 Set Vref, RX VrefLevel [Byte0]: 56
1732 13:21:57.117382 [Byte1]: 56
1733 13:21:57.122185
1734 13:21:57.122320 Set Vref, RX VrefLevel [Byte0]: 57
1735 13:21:57.125113 [Byte1]: 57
1736 13:21:57.129248
1737 13:21:57.129400 Set Vref, RX VrefLevel [Byte0]: 58
1738 13:21:57.132625 [Byte1]: 58
1739 13:21:57.137331
1740 13:21:57.137532 Set Vref, RX VrefLevel [Byte0]: 59
1741 13:21:57.140123 [Byte1]: 59
1742 13:21:57.144905
1743 13:21:57.145146 Set Vref, RX VrefLevel [Byte0]: 60
1744 13:21:57.148130 [Byte1]: 60
1745 13:21:57.152557
1746 13:21:57.152924 Set Vref, RX VrefLevel [Byte0]: 61
1747 13:21:57.155846 [Byte1]: 61
1748 13:21:57.160176
1749 13:21:57.160744 Set Vref, RX VrefLevel [Byte0]: 62
1750 13:21:57.163467 [Byte1]: 62
1751 13:21:57.168168
1752 13:21:57.168606 Set Vref, RX VrefLevel [Byte0]: 63
1753 13:21:57.171091 [Byte1]: 63
1754 13:21:57.175677
1755 13:21:57.176110 Set Vref, RX VrefLevel [Byte0]: 64
1756 13:21:57.178991 [Byte1]: 64
1757 13:21:57.182988
1758 13:21:57.183456 Set Vref, RX VrefLevel [Byte0]: 65
1759 13:21:57.186617 [Byte1]: 65
1760 13:21:57.190899
1761 13:21:57.191322 Set Vref, RX VrefLevel [Byte0]: 66
1762 13:21:57.193906 [Byte1]: 66
1763 13:21:57.198693
1764 13:21:57.199114 Set Vref, RX VrefLevel [Byte0]: 67
1765 13:21:57.202517 [Byte1]: 67
1766 13:21:57.206304
1767 13:21:57.206973 Set Vref, RX VrefLevel [Byte0]: 68
1768 13:21:57.209232 [Byte1]: 68
1769 13:21:57.213989
1770 13:21:57.214522 Set Vref, RX VrefLevel [Byte0]: 69
1771 13:21:57.217286 [Byte1]: 69
1772 13:21:57.221275
1773 13:21:57.222040 Set Vref, RX VrefLevel [Byte0]: 70
1774 13:21:57.224977 [Byte1]: 70
1775 13:21:57.229192
1776 13:21:57.232441 Set Vref, RX VrefLevel [Byte0]: 71
1777 13:21:57.235320 [Byte1]: 71
1778 13:21:57.235776
1779 13:21:57.238737 Set Vref, RX VrefLevel [Byte0]: 72
1780 13:21:57.242279 [Byte1]: 72
1781 13:21:57.242923
1782 13:21:57.245647 Set Vref, RX VrefLevel [Byte0]: 73
1783 13:21:57.248788 [Byte1]: 73
1784 13:21:57.251857
1785 13:21:57.252277 Set Vref, RX VrefLevel [Byte0]: 74
1786 13:21:57.255484 [Byte1]: 74
1787 13:21:57.259710
1788 13:21:57.260262 Final RX Vref Byte 0 = 63 to rank0
1789 13:21:57.263071 Final RX Vref Byte 1 = 54 to rank0
1790 13:21:57.266522 Final RX Vref Byte 0 = 63 to rank1
1791 13:21:57.269742 Final RX Vref Byte 1 = 54 to rank1==
1792 13:21:57.272869 Dram Type= 6, Freq= 0, CH_1, rank 0
1793 13:21:57.279411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1794 13:21:57.279969 ==
1795 13:21:57.280342 DQS Delay:
1796 13:21:57.280661 DQS0 = 0, DQS1 = 0
1797 13:21:57.283213 DQM Delay:
1798 13:21:57.283916 DQM0 = 80, DQM1 = 72
1799 13:21:57.286458 DQ Delay:
1800 13:21:57.289624 DQ0 =88, DQ1 =72, DQ2 =68, DQ3 =76
1801 13:21:57.289999 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
1802 13:21:57.293317 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1803 13:21:57.296308 DQ12 =80, DQ13 =80, DQ14 =76, DQ15 =80
1804 13:21:57.299313
1805 13:21:57.299594
1806 13:21:57.306246 [DQSOSCAuto] RK0, (LSB)MR18= 0xf18, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
1807 13:21:57.309851 CH1 RK0: MR19=606, MR18=F18
1808 13:21:57.315791 CH1_RK0: MR19=0x606, MR18=0xF18, DQSOSC=403, MR23=63, INC=90, DEC=60
1809 13:21:57.316033
1810 13:21:57.319335 ----->DramcWriteLeveling(PI) begin...
1811 13:21:57.319522 ==
1812 13:21:57.322895 Dram Type= 6, Freq= 0, CH_1, rank 1
1813 13:21:57.326505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1814 13:21:57.326689 ==
1815 13:21:57.329469 Write leveling (Byte 0): 27 => 27
1816 13:21:57.332845 Write leveling (Byte 1): 28 => 28
1817 13:21:57.336135 DramcWriteLeveling(PI) end<-----
1818 13:21:57.336317
1819 13:21:57.336470 ==
1820 13:21:57.339815 Dram Type= 6, Freq= 0, CH_1, rank 1
1821 13:21:57.342639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1822 13:21:57.342856 ==
1823 13:21:57.346203 [Gating] SW mode calibration
1824 13:21:57.353061 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1825 13:21:57.359189 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1826 13:21:57.363004 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1827 13:21:57.365955 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1828 13:21:57.372553 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1829 13:21:57.376117 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 13:21:57.379548 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 13:21:57.386089 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 13:21:57.389416 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 13:21:57.392679 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 13:21:57.396019 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 13:21:57.402648 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 13:21:57.405740 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 13:21:57.408937 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 13:21:57.415933 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 13:21:57.419023 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 13:21:57.422959 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 13:21:57.428974 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 13:21:57.432512 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 13:21:57.436618 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1844 13:21:57.442643 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1845 13:21:57.445768 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 13:21:57.449206 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 13:21:57.455774 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 13:21:57.459607 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 13:21:57.462473 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 13:21:57.469390 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 13:21:57.472357 0 9 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1852 13:21:57.475826 0 9 8 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1853 13:21:57.482455 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 13:21:57.486006 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1855 13:21:57.489047 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1856 13:21:57.495733 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1857 13:21:57.498928 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1858 13:21:57.502452 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1859 13:21:57.505906 0 10 4 | B1->B0 | 3333 2a2a | 1 0 | (1 1) (0 0)
1860 13:21:57.512518 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
1861 13:21:57.515845 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 13:21:57.518997 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 13:21:57.525536 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 13:21:57.528746 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 13:21:57.531985 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 13:21:57.538712 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 13:21:57.542088 0 11 4 | B1->B0 | 2b2b 3a3a | 0 0 | (0 0) (0 0)
1868 13:21:57.545485 0 11 8 | B1->B0 | 3e3e 4646 | 1 0 | (1 1) (0 0)
1869 13:21:57.552221 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 13:21:57.555294 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 13:21:57.558490 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1872 13:21:57.565325 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1873 13:21:57.568656 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1874 13:21:57.571980 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1875 13:21:57.578888 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1876 13:21:57.582247 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 13:21:57.585675 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 13:21:57.591825 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 13:21:57.595223 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 13:21:57.598639 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 13:21:57.605356 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 13:21:57.608684 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 13:21:57.612347 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 13:21:57.618928 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 13:21:57.622101 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 13:21:57.626309 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 13:21:57.628725 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 13:21:57.635390 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 13:21:57.638662 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 13:21:57.642010 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 13:21:57.649064 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1892 13:21:57.652260 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1893 13:21:57.655800 Total UI for P1: 0, mck2ui 16
1894 13:21:57.659230 best dqsien dly found for B0: ( 0, 14, 4)
1895 13:21:57.662559 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1896 13:21:57.665896 Total UI for P1: 0, mck2ui 16
1897 13:21:57.669401 best dqsien dly found for B1: ( 0, 14, 8)
1898 13:21:57.672261 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1899 13:21:57.675436 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1900 13:21:57.675588
1901 13:21:57.679076 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1902 13:21:57.685852 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1903 13:21:57.685936 [Gating] SW calibration Done
1904 13:21:57.686002 ==
1905 13:21:57.689302 Dram Type= 6, Freq= 0, CH_1, rank 1
1906 13:21:57.695886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1907 13:21:57.695980 ==
1908 13:21:57.696106 RX Vref Scan: 0
1909 13:21:57.696197
1910 13:21:57.698893 RX Vref 0 -> 0, step: 1
1911 13:21:57.698975
1912 13:21:57.702586 RX Delay -130 -> 252, step: 16
1913 13:21:57.706149 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1914 13:21:57.709127 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1915 13:21:57.712689 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1916 13:21:57.719568 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1917 13:21:57.722282 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1918 13:21:57.726021 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1919 13:21:57.728913 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1920 13:21:57.732425 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1921 13:21:57.735579 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1922 13:21:57.742348 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1923 13:21:57.745821 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1924 13:21:57.748796 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1925 13:21:57.752613 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1926 13:21:57.759307 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1927 13:21:57.762214 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1928 13:21:57.765864 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1929 13:21:57.765946 ==
1930 13:21:57.769445 Dram Type= 6, Freq= 0, CH_1, rank 1
1931 13:21:57.772561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1932 13:21:57.772650 ==
1933 13:21:57.775970 DQS Delay:
1934 13:21:57.776064 DQS0 = 0, DQS1 = 0
1935 13:21:57.779119 DQM Delay:
1936 13:21:57.779201 DQM0 = 77, DQM1 = 73
1937 13:21:57.779267 DQ Delay:
1938 13:21:57.782460 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =69
1939 13:21:57.786049 DQ4 =69, DQ5 =85, DQ6 =93, DQ7 =77
1940 13:21:57.789069 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
1941 13:21:57.792713 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1942 13:21:57.792796
1943 13:21:57.792862
1944 13:21:57.792922 ==
1945 13:21:57.795743 Dram Type= 6, Freq= 0, CH_1, rank 1
1946 13:21:57.802335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1947 13:21:57.802425 ==
1948 13:21:57.802490
1949 13:21:57.802550
1950 13:21:57.802609 TX Vref Scan disable
1951 13:21:57.806142 == TX Byte 0 ==
1952 13:21:57.809756 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1953 13:21:57.813109 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1954 13:21:57.815949 == TX Byte 1 ==
1955 13:21:57.819160 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1956 13:21:57.826152 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1957 13:21:57.826235 ==
1958 13:21:57.829051 Dram Type= 6, Freq= 0, CH_1, rank 1
1959 13:21:57.832721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1960 13:21:57.832803 ==
1961 13:21:57.845198 TX Vref=22, minBit 1, minWin=27, winSum=448
1962 13:21:57.848182 TX Vref=24, minBit 1, minWin=28, winSum=454
1963 13:21:57.851599 TX Vref=26, minBit 1, minWin=28, winSum=456
1964 13:21:57.855253 TX Vref=28, minBit 0, minWin=28, winSum=459
1965 13:21:57.858266 TX Vref=30, minBit 0, minWin=28, winSum=461
1966 13:21:57.865471 TX Vref=32, minBit 1, minWin=27, winSum=457
1967 13:21:57.868162 [TxChooseVref] Worse bit 0, Min win 28, Win sum 461, Final Vref 30
1968 13:21:57.868245
1969 13:21:57.871678 Final TX Range 1 Vref 30
1970 13:21:57.871761
1971 13:21:57.871826 ==
1972 13:21:57.875226 Dram Type= 6, Freq= 0, CH_1, rank 1
1973 13:21:57.878213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1974 13:21:57.878296 ==
1975 13:21:57.881280
1976 13:21:57.881377
1977 13:21:57.881473 TX Vref Scan disable
1978 13:21:57.884921 == TX Byte 0 ==
1979 13:21:57.888172 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1980 13:21:57.891869 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1981 13:21:57.894880 == TX Byte 1 ==
1982 13:21:57.898468 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1983 13:21:57.901592 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1984 13:21:57.905508
1985 13:21:57.905601 [DATLAT]
1986 13:21:57.905686 Freq=800, CH1 RK1
1987 13:21:57.905762
1988 13:21:57.908460 DATLAT Default: 0xa
1989 13:21:57.908541 0, 0xFFFF, sum = 0
1990 13:21:57.911569 1, 0xFFFF, sum = 0
1991 13:21:57.911653 2, 0xFFFF, sum = 0
1992 13:21:57.914889 3, 0xFFFF, sum = 0
1993 13:21:57.914973 4, 0xFFFF, sum = 0
1994 13:21:57.918211 5, 0xFFFF, sum = 0
1995 13:21:57.918297 6, 0xFFFF, sum = 0
1996 13:21:57.921767 7, 0xFFFF, sum = 0
1997 13:21:57.924697 8, 0xFFFF, sum = 0
1998 13:21:57.924782 9, 0x0, sum = 1
1999 13:21:57.924849 10, 0x0, sum = 2
2000 13:21:57.928263 11, 0x0, sum = 3
2001 13:21:57.928347 12, 0x0, sum = 4
2002 13:21:57.931263 best_step = 10
2003 13:21:57.931345
2004 13:21:57.931449 ==
2005 13:21:57.934883 Dram Type= 6, Freq= 0, CH_1, rank 1
2006 13:21:57.938448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2007 13:21:57.938539 ==
2008 13:21:57.941665 RX Vref Scan: 0
2009 13:21:57.941778
2010 13:21:57.941912 RX Vref 0 -> 0, step: 1
2011 13:21:57.941992
2012 13:21:57.944551 RX Delay -111 -> 252, step: 8
2013 13:21:57.951613 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2014 13:21:57.954987 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2015 13:21:57.958122 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2016 13:21:57.961222 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2017 13:21:57.968073 iDelay=209, Bit 4, Center 72 (-47 ~ 192) 240
2018 13:21:57.971525 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2019 13:21:57.974628 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2020 13:21:57.978231 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2021 13:21:57.981383 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2022 13:21:57.984548 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2023 13:21:57.991486 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2024 13:21:57.994588 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2025 13:21:57.998175 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2026 13:21:58.001714 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2027 13:21:58.007936 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2028 13:21:58.011746 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2029 13:21:58.011865 ==
2030 13:21:58.014760 Dram Type= 6, Freq= 0, CH_1, rank 1
2031 13:21:58.018252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2032 13:21:58.018350 ==
2033 13:21:58.018451 DQS Delay:
2034 13:21:58.021716 DQS0 = 0, DQS1 = 0
2035 13:21:58.021800 DQM Delay:
2036 13:21:58.024582 DQM0 = 77, DQM1 = 73
2037 13:21:58.024669 DQ Delay:
2038 13:21:58.028028 DQ0 =80, DQ1 =72, DQ2 =68, DQ3 =72
2039 13:21:58.031421 DQ4 =72, DQ5 =88, DQ6 =88, DQ7 =76
2040 13:21:58.034651 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
2041 13:21:58.038014 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2042 13:21:58.038115
2043 13:21:58.038183
2044 13:21:58.048133 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e37, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
2045 13:21:58.048225 CH1 RK1: MR19=606, MR18=1E37
2046 13:21:58.055029 CH1_RK1: MR19=0x606, MR18=0x1E37, DQSOSC=395, MR23=63, INC=94, DEC=63
2047 13:21:58.058097 [RxdqsGatingPostProcess] freq 800
2048 13:21:58.064679 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2049 13:21:58.068165 Pre-setting of DQS Precalculation
2050 13:21:58.071230 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2051 13:21:58.078122 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2052 13:21:58.084645 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2053 13:21:58.084729
2054 13:21:58.088466
2055 13:21:58.088552 [Calibration Summary] 1600 Mbps
2056 13:21:58.091504 CH 0, Rank 0
2057 13:21:58.091590 SW Impedance : PASS
2058 13:21:58.094968 DUTY Scan : NO K
2059 13:21:58.098082 ZQ Calibration : PASS
2060 13:21:58.098189 Jitter Meter : NO K
2061 13:21:58.101524 CBT Training : PASS
2062 13:21:58.104817 Write leveling : PASS
2063 13:21:58.104894 RX DQS gating : PASS
2064 13:21:58.108240 RX DQ/DQS(RDDQC) : PASS
2065 13:21:58.111629 TX DQ/DQS : PASS
2066 13:21:58.111715 RX DATLAT : PASS
2067 13:21:58.115110 RX DQ/DQS(Engine): PASS
2068 13:21:58.115194 TX OE : NO K
2069 13:21:58.118182 All Pass.
2070 13:21:58.118299
2071 13:21:58.118399 CH 0, Rank 1
2072 13:21:58.121357 SW Impedance : PASS
2073 13:21:58.121444 DUTY Scan : NO K
2074 13:21:58.124883 ZQ Calibration : PASS
2075 13:21:58.128553 Jitter Meter : NO K
2076 13:21:58.128639 CBT Training : PASS
2077 13:21:58.131384 Write leveling : PASS
2078 13:21:58.135115 RX DQS gating : PASS
2079 13:21:58.135200 RX DQ/DQS(RDDQC) : PASS
2080 13:21:58.138177 TX DQ/DQS : PASS
2081 13:21:58.141472 RX DATLAT : PASS
2082 13:21:58.141584 RX DQ/DQS(Engine): PASS
2083 13:21:58.144577 TX OE : NO K
2084 13:21:58.144682 All Pass.
2085 13:21:58.144776
2086 13:21:58.148101 CH 1, Rank 0
2087 13:21:58.148216 SW Impedance : PASS
2088 13:21:58.151323 DUTY Scan : NO K
2089 13:21:58.154919 ZQ Calibration : PASS
2090 13:21:58.155032 Jitter Meter : NO K
2091 13:21:58.158513 CBT Training : PASS
2092 13:21:58.161394 Write leveling : PASS
2093 13:21:58.161506 RX DQS gating : PASS
2094 13:21:58.165098 RX DQ/DQS(RDDQC) : PASS
2095 13:21:58.165183 TX DQ/DQS : PASS
2096 13:21:58.168537 RX DATLAT : PASS
2097 13:21:58.171727 RX DQ/DQS(Engine): PASS
2098 13:21:58.171813 TX OE : NO K
2099 13:21:58.174707 All Pass.
2100 13:21:58.174791
2101 13:21:58.174858 CH 1, Rank 1
2102 13:21:58.178133 SW Impedance : PASS
2103 13:21:58.178219 DUTY Scan : NO K
2104 13:21:58.181361 ZQ Calibration : PASS
2105 13:21:58.185335 Jitter Meter : NO K
2106 13:21:58.185419 CBT Training : PASS
2107 13:21:58.188595 Write leveling : PASS
2108 13:21:58.191615 RX DQS gating : PASS
2109 13:21:58.191728 RX DQ/DQS(RDDQC) : PASS
2110 13:21:58.195175 TX DQ/DQS : PASS
2111 13:21:58.198155 RX DATLAT : PASS
2112 13:21:58.198260 RX DQ/DQS(Engine): PASS
2113 13:21:58.202107 TX OE : NO K
2114 13:21:58.202219 All Pass.
2115 13:21:58.202325
2116 13:21:58.204919 DramC Write-DBI off
2117 13:21:58.208123 PER_BANK_REFRESH: Hybrid Mode
2118 13:21:58.208204 TX_TRACKING: ON
2119 13:21:58.211678 [GetDramInforAfterCalByMRR] Vendor 6.
2120 13:21:58.215047 [GetDramInforAfterCalByMRR] Revision 606.
2121 13:21:58.218429 [GetDramInforAfterCalByMRR] Revision 2 0.
2122 13:21:58.221438 MR0 0x3b3b
2123 13:21:58.221517 MR8 0x5151
2124 13:21:58.225244 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2125 13:21:58.225356
2126 13:21:58.225452 MR0 0x3b3b
2127 13:21:58.228340 MR8 0x5151
2128 13:21:58.231896 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2129 13:21:58.232013
2130 13:21:58.238377 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2131 13:21:58.245122 [FAST_K] Save calibration result to emmc
2132 13:21:58.248085 [FAST_K] Save calibration result to emmc
2133 13:21:58.248191 dram_init: config_dvfs: 1
2134 13:21:58.251863 dramc_set_vcore_voltage set vcore to 662500
2135 13:21:58.254905 Read voltage for 1200, 2
2136 13:21:58.254990 Vio18 = 0
2137 13:21:58.258387 Vcore = 662500
2138 13:21:58.258473 Vdram = 0
2139 13:21:58.258541 Vddq = 0
2140 13:21:58.261547 Vmddr = 0
2141 13:21:58.265236 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2142 13:21:58.271491 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2143 13:21:58.271579 MEM_TYPE=3, freq_sel=15
2144 13:21:58.275252 sv_algorithm_assistance_LP4_1600
2145 13:21:58.281825 ============ PULL DRAM RESETB DOWN ============
2146 13:21:58.284874 ========== PULL DRAM RESETB DOWN end =========
2147 13:21:58.288056 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2148 13:21:58.291606 ===================================
2149 13:21:58.294684 LPDDR4 DRAM CONFIGURATION
2150 13:21:58.298034 ===================================
2151 13:21:58.298158 EX_ROW_EN[0] = 0x0
2152 13:21:58.301635 EX_ROW_EN[1] = 0x0
2153 13:21:58.304782 LP4Y_EN = 0x0
2154 13:21:58.304892 WORK_FSP = 0x0
2155 13:21:58.308070 WL = 0x4
2156 13:21:58.308151 RL = 0x4
2157 13:21:58.311842 BL = 0x2
2158 13:21:58.311938 RPST = 0x0
2159 13:21:58.315135 RD_PRE = 0x0
2160 13:21:58.315230 WR_PRE = 0x1
2161 13:21:58.318418 WR_PST = 0x0
2162 13:21:58.318501 DBI_WR = 0x0
2163 13:21:58.321279 DBI_RD = 0x0
2164 13:21:58.321365 OTF = 0x1
2165 13:21:58.324759 ===================================
2166 13:21:58.328522 ===================================
2167 13:21:58.331308 ANA top config
2168 13:21:58.334853 ===================================
2169 13:21:58.334937 DLL_ASYNC_EN = 0
2170 13:21:58.338109 ALL_SLAVE_EN = 0
2171 13:21:58.341596 NEW_RANK_MODE = 1
2172 13:21:58.344703 DLL_IDLE_MODE = 1
2173 13:21:58.348105 LP45_APHY_COMB_EN = 1
2174 13:21:58.348210 TX_ODT_DIS = 1
2175 13:21:58.351522 NEW_8X_MODE = 1
2176 13:21:58.355137 ===================================
2177 13:21:58.358196 ===================================
2178 13:21:58.361301 data_rate = 2400
2179 13:21:58.365509 CKR = 1
2180 13:21:58.368247 DQ_P2S_RATIO = 8
2181 13:21:58.371200 ===================================
2182 13:21:58.371305 CA_P2S_RATIO = 8
2183 13:21:58.374865 DQ_CA_OPEN = 0
2184 13:21:58.378008 DQ_SEMI_OPEN = 0
2185 13:21:58.381603 CA_SEMI_OPEN = 0
2186 13:21:58.384539 CA_FULL_RATE = 0
2187 13:21:58.388230 DQ_CKDIV4_EN = 0
2188 13:21:58.388311 CA_CKDIV4_EN = 0
2189 13:21:58.391354 CA_PREDIV_EN = 0
2190 13:21:58.394986 PH8_DLY = 17
2191 13:21:58.398102 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2192 13:21:58.401730 DQ_AAMCK_DIV = 4
2193 13:21:58.404505 CA_AAMCK_DIV = 4
2194 13:21:58.404591 CA_ADMCK_DIV = 4
2195 13:21:58.407893 DQ_TRACK_CA_EN = 0
2196 13:21:58.411260 CA_PICK = 1200
2197 13:21:58.414448 CA_MCKIO = 1200
2198 13:21:58.418186 MCKIO_SEMI = 0
2199 13:21:58.421333 PLL_FREQ = 2366
2200 13:21:58.424807 DQ_UI_PI_RATIO = 32
2201 13:21:58.424891 CA_UI_PI_RATIO = 0
2202 13:21:58.427864 ===================================
2203 13:21:58.431015 ===================================
2204 13:21:58.434581 memory_type:LPDDR4
2205 13:21:58.437874 GP_NUM : 10
2206 13:21:58.437986 SRAM_EN : 1
2207 13:21:58.441904 MD32_EN : 0
2208 13:21:58.444893 ===================================
2209 13:21:58.447744 [ANA_INIT] >>>>>>>>>>>>>>
2210 13:21:58.451470 <<<<<< [CONFIGURE PHASE]: ANA_TX
2211 13:21:58.454677 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2212 13:21:58.458123 ===================================
2213 13:21:58.458220 data_rate = 2400,PCW = 0X5b00
2214 13:21:58.461251 ===================================
2215 13:21:58.464394 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2216 13:21:58.471356 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2217 13:21:58.478213 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2218 13:21:58.481093 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2219 13:21:58.484575 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2220 13:21:58.487885 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2221 13:21:58.490907 [ANA_INIT] flow start
2222 13:21:58.490984 [ANA_INIT] PLL >>>>>>>>
2223 13:21:58.494633 [ANA_INIT] PLL <<<<<<<<
2224 13:21:58.498255 [ANA_INIT] MIDPI >>>>>>>>
2225 13:21:58.501217 [ANA_INIT] MIDPI <<<<<<<<
2226 13:21:58.501295 [ANA_INIT] DLL >>>>>>>>
2227 13:21:58.504817 [ANA_INIT] DLL <<<<<<<<
2228 13:21:58.504893 [ANA_INIT] flow end
2229 13:21:58.511491 ============ LP4 DIFF to SE enter ============
2230 13:21:58.514483 ============ LP4 DIFF to SE exit ============
2231 13:21:58.518253 [ANA_INIT] <<<<<<<<<<<<<
2232 13:21:58.521523 [Flow] Enable top DCM control >>>>>
2233 13:21:58.524731 [Flow] Enable top DCM control <<<<<
2234 13:21:58.524819 Enable DLL master slave shuffle
2235 13:21:58.531978 ==============================================================
2236 13:21:58.534844 Gating Mode config
2237 13:21:58.538528 ==============================================================
2238 13:21:58.541610 Config description:
2239 13:21:58.551802 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2240 13:21:58.558469 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2241 13:21:58.561756 SELPH_MODE 0: By rank 1: By Phase
2242 13:21:58.568202 ==============================================================
2243 13:21:58.571281 GAT_TRACK_EN = 1
2244 13:21:58.574868 RX_GATING_MODE = 2
2245 13:21:58.578320 RX_GATING_TRACK_MODE = 2
2246 13:21:58.581382 SELPH_MODE = 1
2247 13:21:58.581467 PICG_EARLY_EN = 1
2248 13:21:58.584864 VALID_LAT_VALUE = 1
2249 13:21:58.591537 ==============================================================
2250 13:21:58.594719 Enter into Gating configuration >>>>
2251 13:21:58.597834 Exit from Gating configuration <<<<
2252 13:21:58.601214 Enter into DVFS_PRE_config >>>>>
2253 13:21:58.611557 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2254 13:21:58.614708 Exit from DVFS_PRE_config <<<<<
2255 13:21:58.618219 Enter into PICG configuration >>>>
2256 13:21:58.621291 Exit from PICG configuration <<<<
2257 13:21:58.624723 [RX_INPUT] configuration >>>>>
2258 13:21:58.628148 [RX_INPUT] configuration <<<<<
2259 13:21:58.631330 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2260 13:21:58.638356 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2261 13:21:58.645176 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2262 13:21:58.651310 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2263 13:21:58.654865 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2264 13:21:58.661368 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2265 13:21:58.665119 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2266 13:21:58.671383 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2267 13:21:58.674957 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2268 13:21:58.678391 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2269 13:21:58.681356 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2270 13:21:58.688112 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2271 13:21:58.691051 ===================================
2272 13:21:58.694844 LPDDR4 DRAM CONFIGURATION
2273 13:21:58.697974 ===================================
2274 13:21:58.698056 EX_ROW_EN[0] = 0x0
2275 13:21:58.701127 EX_ROW_EN[1] = 0x0
2276 13:21:58.701267 LP4Y_EN = 0x0
2277 13:21:58.704215 WORK_FSP = 0x0
2278 13:21:58.704317 WL = 0x4
2279 13:21:58.707924 RL = 0x4
2280 13:21:58.708000 BL = 0x2
2281 13:21:58.710973 RPST = 0x0
2282 13:21:58.711073 RD_PRE = 0x0
2283 13:21:58.714236 WR_PRE = 0x1
2284 13:21:58.714316 WR_PST = 0x0
2285 13:21:58.717823 DBI_WR = 0x0
2286 13:21:58.717899 DBI_RD = 0x0
2287 13:21:58.721291 OTF = 0x1
2288 13:21:58.724147 ===================================
2289 13:21:58.727950 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2290 13:21:58.730987 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2291 13:21:58.737724 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2292 13:21:58.741094 ===================================
2293 13:21:58.741178 LPDDR4 DRAM CONFIGURATION
2294 13:21:58.744615 ===================================
2295 13:21:58.748279 EX_ROW_EN[0] = 0x10
2296 13:21:58.751236 EX_ROW_EN[1] = 0x0
2297 13:21:58.751339 LP4Y_EN = 0x0
2298 13:21:58.754869 WORK_FSP = 0x0
2299 13:21:58.754954 WL = 0x4
2300 13:21:58.757723 RL = 0x4
2301 13:21:58.757808 BL = 0x2
2302 13:21:58.761212 RPST = 0x0
2303 13:21:58.761296 RD_PRE = 0x0
2304 13:21:58.764269 WR_PRE = 0x1
2305 13:21:58.764346 WR_PST = 0x0
2306 13:21:58.767985 DBI_WR = 0x0
2307 13:21:58.768075 DBI_RD = 0x0
2308 13:21:58.770916 OTF = 0x1
2309 13:21:58.774375 ===================================
2310 13:21:58.781148 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2311 13:21:58.781263 ==
2312 13:21:58.784184 Dram Type= 6, Freq= 0, CH_0, rank 0
2313 13:21:58.787856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2314 13:21:58.787938 ==
2315 13:21:58.791380 [Duty_Offset_Calibration]
2316 13:21:58.791495 B0:2 B1:0 CA:3
2317 13:21:58.791560
2318 13:21:58.794270 [DutyScan_Calibration_Flow] k_type=0
2319 13:21:58.804621
2320 13:21:58.804703 ==CLK 0==
2321 13:21:58.808140 Final CLK duty delay cell = 0
2322 13:21:58.810789 [0] MAX Duty = 5031%(X100), DQS PI = 12
2323 13:21:58.814412 [0] MIN Duty = 4906%(X100), DQS PI = 54
2324 13:21:58.814487 [0] AVG Duty = 4968%(X100)
2325 13:21:58.820097
2326 13:21:58.820957 CH0 CLK Duty spec in!! Max-Min= 125%
2327 13:21:58.824591 [DutyScan_Calibration_Flow] ====Done====
2328 13:21:58.824669
2329 13:21:58.827520 [DutyScan_Calibration_Flow] k_type=1
2330 13:21:58.842834
2331 13:21:58.842928 ==DQS 0 ==
2332 13:21:58.846113 Final DQS duty delay cell = 0
2333 13:21:58.849480 [0] MAX Duty = 5062%(X100), DQS PI = 12
2334 13:21:58.852769 [0] MIN Duty = 4907%(X100), DQS PI = 46
2335 13:21:58.856352 [0] AVG Duty = 4984%(X100)
2336 13:21:58.856422
2337 13:21:58.856482 ==DQS 1 ==
2338 13:21:58.859752 Final DQS duty delay cell = -4
2339 13:21:58.863144 [-4] MAX Duty = 5000%(X100), DQS PI = 36
2340 13:21:58.865966 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2341 13:21:58.869620 [-4] AVG Duty = 4937%(X100)
2342 13:21:58.869696
2343 13:21:58.872592 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2344 13:21:58.872667
2345 13:21:58.876103 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2346 13:21:58.879908 [DutyScan_Calibration_Flow] ====Done====
2347 13:21:58.879980
2348 13:21:58.882567 [DutyScan_Calibration_Flow] k_type=3
2349 13:21:58.900851
2350 13:21:58.900932 ==DQM 0 ==
2351 13:21:58.904117 Final DQM duty delay cell = 0
2352 13:21:58.907091 [0] MAX Duty = 5124%(X100), DQS PI = 10
2353 13:21:58.910970 [0] MIN Duty = 4876%(X100), DQS PI = 48
2354 13:21:58.911051 [0] AVG Duty = 5000%(X100)
2355 13:21:58.914136
2356 13:21:58.914216 ==DQM 1 ==
2357 13:21:58.917047 Final DQM duty delay cell = 4
2358 13:21:58.920516 [4] MAX Duty = 5124%(X100), DQS PI = 50
2359 13:21:58.923577 [4] MIN Duty = 5000%(X100), DQS PI = 14
2360 13:21:58.927014 [4] AVG Duty = 5062%(X100)
2361 13:21:58.927099
2362 13:21:58.930662 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2363 13:21:58.930754
2364 13:21:58.933947 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2365 13:21:58.937013 [DutyScan_Calibration_Flow] ====Done====
2366 13:21:58.937091
2367 13:21:58.940525 [DutyScan_Calibration_Flow] k_type=2
2368 13:21:58.955553
2369 13:21:58.955639 ==DQ 0 ==
2370 13:21:58.958765 Final DQ duty delay cell = -4
2371 13:21:58.962215 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2372 13:21:58.965572 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2373 13:21:58.969131 [-4] AVG Duty = 4969%(X100)
2374 13:21:58.969209
2375 13:21:58.969295 ==DQ 1 ==
2376 13:21:58.972165 Final DQ duty delay cell = -4
2377 13:21:58.975693 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2378 13:21:58.978555 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2379 13:21:58.982188 [-4] AVG Duty = 4938%(X100)
2380 13:21:58.982361
2381 13:21:58.985682 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2382 13:21:58.985785
2383 13:21:58.988654 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2384 13:21:58.992108 [DutyScan_Calibration_Flow] ====Done====
2385 13:21:58.992185 ==
2386 13:21:58.995613 Dram Type= 6, Freq= 0, CH_1, rank 0
2387 13:21:58.998510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2388 13:21:58.998593 ==
2389 13:21:59.002052 [Duty_Offset_Calibration]
2390 13:21:59.002126 B0:1 B1:-2 CA:0
2391 13:21:59.002189
2392 13:21:59.005672 [DutyScan_Calibration_Flow] k_type=0
2393 13:21:59.016251
2394 13:21:59.016323 ==CLK 0==
2395 13:21:59.019184 Final CLK duty delay cell = 0
2396 13:21:59.022693 [0] MAX Duty = 5062%(X100), DQS PI = 30
2397 13:21:59.025701 [0] MIN Duty = 4876%(X100), DQS PI = 2
2398 13:21:59.025784 [0] AVG Duty = 4969%(X100)
2399 13:21:59.029296
2400 13:21:59.032781 CH1 CLK Duty spec in!! Max-Min= 186%
2401 13:21:59.035788 [DutyScan_Calibration_Flow] ====Done====
2402 13:21:59.035864
2403 13:21:59.039304 [DutyScan_Calibration_Flow] k_type=1
2404 13:21:59.054339
2405 13:21:59.054424 ==DQS 0 ==
2406 13:21:59.057709 Final DQS duty delay cell = -4
2407 13:21:59.061110 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2408 13:21:59.064440 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2409 13:21:59.067769 [-4] AVG Duty = 4969%(X100)
2410 13:21:59.067846
2411 13:21:59.067928 ==DQS 1 ==
2412 13:21:59.071064 Final DQS duty delay cell = 0
2413 13:21:59.074251 [0] MAX Duty = 5093%(X100), DQS PI = 0
2414 13:21:59.077637 [0] MIN Duty = 4875%(X100), DQS PI = 26
2415 13:21:59.081194 [0] AVG Duty = 4984%(X100)
2416 13:21:59.081271
2417 13:21:59.084684 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2418 13:21:59.084785
2419 13:21:59.087924 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2420 13:21:59.091075 [DutyScan_Calibration_Flow] ====Done====
2421 13:21:59.091150
2422 13:21:59.094548 [DutyScan_Calibration_Flow] k_type=3
2423 13:21:59.111336
2424 13:21:59.111473 ==DQM 0 ==
2425 13:21:59.114615 Final DQM duty delay cell = 0
2426 13:21:59.117702 [0] MAX Duty = 5000%(X100), DQS PI = 22
2427 13:21:59.121352 [0] MIN Duty = 4876%(X100), DQS PI = 2
2428 13:21:59.121428 [0] AVG Duty = 4938%(X100)
2429 13:21:59.124285
2430 13:21:59.124368 ==DQM 1 ==
2431 13:21:59.127708 Final DQM duty delay cell = 0
2432 13:21:59.131201 [0] MAX Duty = 5031%(X100), DQS PI = 36
2433 13:21:59.134652 [0] MIN Duty = 4907%(X100), DQS PI = 0
2434 13:21:59.134752 [0] AVG Duty = 4969%(X100)
2435 13:21:59.137710
2436 13:21:59.141275 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2437 13:21:59.141358
2438 13:21:59.144233 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2439 13:21:59.147620 [DutyScan_Calibration_Flow] ====Done====
2440 13:21:59.147726
2441 13:21:59.151266 [DutyScan_Calibration_Flow] k_type=2
2442 13:21:59.167801
2443 13:21:59.167885 ==DQ 0 ==
2444 13:21:59.170949 Final DQ duty delay cell = 0
2445 13:21:59.174229 [0] MAX Duty = 5093%(X100), DQS PI = 20
2446 13:21:59.177107 [0] MIN Duty = 4907%(X100), DQS PI = 56
2447 13:21:59.177191 [0] AVG Duty = 5000%(X100)
2448 13:21:59.181162
2449 13:21:59.181268 ==DQ 1 ==
2450 13:21:59.184192 Final DQ duty delay cell = 0
2451 13:21:59.187212 [0] MAX Duty = 5125%(X100), DQS PI = 36
2452 13:21:59.190528 [0] MIN Duty = 4969%(X100), DQS PI = 26
2453 13:21:59.190611 [0] AVG Duty = 5047%(X100)
2454 13:21:59.190676
2455 13:21:59.194340 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2456 13:21:59.197227
2457 13:21:59.200731 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2458 13:21:59.204297 [DutyScan_Calibration_Flow] ====Done====
2459 13:21:59.207361 nWR fixed to 30
2460 13:21:59.207500 [ModeRegInit_LP4] CH0 RK0
2461 13:21:59.210553 [ModeRegInit_LP4] CH0 RK1
2462 13:21:59.214102 [ModeRegInit_LP4] CH1 RK0
2463 13:21:59.214184 [ModeRegInit_LP4] CH1 RK1
2464 13:21:59.217819 match AC timing 7
2465 13:21:59.220624 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2466 13:21:59.224105 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2467 13:21:59.230939 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2468 13:21:59.233922 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2469 13:21:59.241014 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2470 13:21:59.241096 ==
2471 13:21:59.243991 Dram Type= 6, Freq= 0, CH_0, rank 0
2472 13:21:59.247120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2473 13:21:59.247203 ==
2474 13:21:59.253886 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2475 13:21:59.257252 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2476 13:21:59.267618 [CA 0] Center 40 (10~71) winsize 62
2477 13:21:59.270737 [CA 1] Center 39 (9~70) winsize 62
2478 13:21:59.274137 [CA 2] Center 36 (6~66) winsize 61
2479 13:21:59.277674 [CA 3] Center 35 (5~66) winsize 62
2480 13:21:59.280609 [CA 4] Center 34 (4~65) winsize 62
2481 13:21:59.283934 [CA 5] Center 33 (3~63) winsize 61
2482 13:21:59.284016
2483 13:21:59.287346 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2484 13:21:59.287496
2485 13:21:59.290494 [CATrainingPosCal] consider 1 rank data
2486 13:21:59.294322 u2DelayCellTimex100 = 270/100 ps
2487 13:21:59.297447 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2488 13:21:59.304326 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2489 13:21:59.307525 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2490 13:21:59.310563 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2491 13:21:59.314150 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2492 13:21:59.317544 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2493 13:21:59.317628
2494 13:21:59.320524 CA PerBit enable=1, Macro0, CA PI delay=33
2495 13:21:59.320608
2496 13:21:59.323883 [CBTSetCACLKResult] CA Dly = 33
2497 13:21:59.323966 CS Dly: 7 (0~38)
2498 13:21:59.327354 ==
2499 13:21:59.330982 Dram Type= 6, Freq= 0, CH_0, rank 1
2500 13:21:59.333933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2501 13:21:59.334016 ==
2502 13:21:59.337367 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2503 13:21:59.343824 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2504 13:21:59.353402 [CA 0] Center 40 (10~71) winsize 62
2505 13:21:59.356737 [CA 1] Center 39 (9~70) winsize 62
2506 13:21:59.360230 [CA 2] Center 35 (5~66) winsize 62
2507 13:21:59.363516 [CA 3] Center 35 (5~66) winsize 62
2508 13:21:59.366596 [CA 4] Center 34 (4~65) winsize 62
2509 13:21:59.369930 [CA 5] Center 33 (3~63) winsize 61
2510 13:21:59.370012
2511 13:21:59.373285 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2512 13:21:59.373367
2513 13:21:59.376666 [CATrainingPosCal] consider 2 rank data
2514 13:21:59.380318 u2DelayCellTimex100 = 270/100 ps
2515 13:21:59.383272 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2516 13:21:59.390402 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2517 13:21:59.393518 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2518 13:21:59.396768 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2519 13:21:59.400351 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2520 13:21:59.403504 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2521 13:21:59.403586
2522 13:21:59.406576 CA PerBit enable=1, Macro0, CA PI delay=33
2523 13:21:59.406658
2524 13:21:59.410059 [CBTSetCACLKResult] CA Dly = 33
2525 13:21:59.410141 CS Dly: 8 (0~40)
2526 13:21:59.410207
2527 13:21:59.413289 ----->DramcWriteLeveling(PI) begin...
2528 13:21:59.416701 ==
2529 13:21:59.420546 Dram Type= 6, Freq= 0, CH_0, rank 0
2530 13:21:59.423499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2531 13:21:59.423581 ==
2532 13:21:59.427034 Write leveling (Byte 0): 33 => 33
2533 13:21:59.430455 Write leveling (Byte 1): 30 => 30
2534 13:21:59.433377 DramcWriteLeveling(PI) end<-----
2535 13:21:59.433459
2536 13:21:59.433524 ==
2537 13:21:59.437150 Dram Type= 6, Freq= 0, CH_0, rank 0
2538 13:21:59.440253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2539 13:21:59.440334 ==
2540 13:21:59.444032 [Gating] SW mode calibration
2541 13:21:59.450209 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2542 13:21:59.453942 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2543 13:21:59.460394 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 13:21:59.463979 0 15 4 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
2545 13:21:59.467417 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2546 13:21:59.473348 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2547 13:21:59.476804 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2548 13:21:59.480291 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2549 13:21:59.486738 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2550 13:21:59.490354 0 15 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2551 13:21:59.493829 1 0 0 | B1->B0 | 2f2f 2626 | 0 1 | (0 0) (1 0)
2552 13:21:59.499976 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2553 13:21:59.503293 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2554 13:21:59.506761 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2555 13:21:59.513298 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2556 13:21:59.516682 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2557 13:21:59.520392 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2558 13:21:59.526277 1 0 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2559 13:21:59.529784 1 1 0 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2560 13:21:59.533258 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 13:21:59.539319 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 13:21:59.542702 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2563 13:21:59.546093 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2564 13:21:59.552672 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2565 13:21:59.556280 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2566 13:21:59.559773 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2567 13:21:59.566445 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2568 13:21:59.569400 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2569 13:21:59.572522 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 13:21:59.579500 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 13:21:59.582711 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 13:21:59.586234 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 13:21:59.593038 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 13:21:59.596098 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 13:21:59.599538 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 13:21:59.606089 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 13:21:59.609361 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 13:21:59.612619 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 13:21:59.619698 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 13:21:59.622924 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2581 13:21:59.626214 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2582 13:21:59.629245 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2583 13:21:59.635871 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2584 13:21:59.639532 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2585 13:21:59.642440 Total UI for P1: 0, mck2ui 16
2586 13:21:59.645877 best dqsien dly found for B0: ( 1, 3, 30)
2587 13:21:59.649450 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2588 13:21:59.652543 Total UI for P1: 0, mck2ui 16
2589 13:21:59.655941 best dqsien dly found for B1: ( 1, 4, 2)
2590 13:21:59.659409 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2591 13:21:59.663165 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2592 13:21:59.663248
2593 13:21:59.669612 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2594 13:21:59.672830 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2595 13:21:59.672913 [Gating] SW calibration Done
2596 13:21:59.676339 ==
2597 13:21:59.679733 Dram Type= 6, Freq= 0, CH_0, rank 0
2598 13:21:59.682783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2599 13:21:59.682866 ==
2600 13:21:59.682931 RX Vref Scan: 0
2601 13:21:59.682992
2602 13:21:59.686319 RX Vref 0 -> 0, step: 1
2603 13:21:59.686402
2604 13:21:59.689750 RX Delay -40 -> 252, step: 8
2605 13:21:59.692935 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2606 13:21:59.696319 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2607 13:21:59.699774 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2608 13:21:59.706366 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2609 13:21:59.709872 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2610 13:21:59.713064 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2611 13:21:59.716807 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2612 13:21:59.719566 iDelay=200, Bit 7, Center 119 (40 ~ 199) 160
2613 13:21:59.726203 iDelay=200, Bit 8, Center 95 (16 ~ 175) 160
2614 13:21:59.729952 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2615 13:21:59.732949 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2616 13:21:59.736218 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2617 13:21:59.739415 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2618 13:21:59.746506 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2619 13:21:59.749638 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2620 13:21:59.753065 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2621 13:21:59.753148 ==
2622 13:21:59.756145 Dram Type= 6, Freq= 0, CH_0, rank 0
2623 13:21:59.759556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2624 13:21:59.759639 ==
2625 13:21:59.762971 DQS Delay:
2626 13:21:59.763078 DQS0 = 0, DQS1 = 0
2627 13:21:59.763171 DQM Delay:
2628 13:21:59.765991 DQM0 = 111, DQM1 = 103
2629 13:21:59.766072 DQ Delay:
2630 13:21:59.769616 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2631 13:21:59.772750 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =119
2632 13:21:59.776130 DQ8 =95, DQ9 =87, DQ10 =103, DQ11 =99
2633 13:21:59.782914 DQ12 =111, DQ13 =107, DQ14 =115, DQ15 =111
2634 13:21:59.782998
2635 13:21:59.783063
2636 13:21:59.783123 ==
2637 13:21:59.785912 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 13:21:59.789527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 13:21:59.789609 ==
2640 13:21:59.789681
2641 13:21:59.789748
2642 13:21:59.793029 TX Vref Scan disable
2643 13:21:59.793110 == TX Byte 0 ==
2644 13:21:59.799734 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2645 13:21:59.802864 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2646 13:21:59.802946 == TX Byte 1 ==
2647 13:21:59.809544 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2648 13:21:59.812557 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2649 13:21:59.812665 ==
2650 13:21:59.816111 Dram Type= 6, Freq= 0, CH_0, rank 0
2651 13:21:59.819037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2652 13:21:59.819133 ==
2653 13:21:59.832195 TX Vref=22, minBit 7, minWin=25, winSum=413
2654 13:21:59.835499 TX Vref=24, minBit 1, minWin=26, winSum=423
2655 13:21:59.838730 TX Vref=26, minBit 7, minWin=26, winSum=432
2656 13:21:59.842168 TX Vref=28, minBit 4, minWin=26, winSum=430
2657 13:21:59.845810 TX Vref=30, minBit 2, minWin=26, winSum=431
2658 13:21:59.848985 TX Vref=32, minBit 2, minWin=26, winSum=428
2659 13:21:59.855687 [TxChooseVref] Worse bit 7, Min win 26, Win sum 432, Final Vref 26
2660 13:21:59.855769
2661 13:21:59.859104 Final TX Range 1 Vref 26
2662 13:21:59.859186
2663 13:21:59.859251 ==
2664 13:21:59.862066 Dram Type= 6, Freq= 0, CH_0, rank 0
2665 13:21:59.865615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2666 13:21:59.865697 ==
2667 13:21:59.865763
2668 13:21:59.869181
2669 13:21:59.869262 TX Vref Scan disable
2670 13:21:59.872375 == TX Byte 0 ==
2671 13:21:59.875264 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2672 13:21:59.878965 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2673 13:21:59.882434 == TX Byte 1 ==
2674 13:21:59.885238 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2675 13:21:59.889127 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2676 13:21:59.889209
2677 13:21:59.892120 [DATLAT]
2678 13:21:59.892201 Freq=1200, CH0 RK0
2679 13:21:59.892266
2680 13:21:59.895713 DATLAT Default: 0xd
2681 13:21:59.895794 0, 0xFFFF, sum = 0
2682 13:21:59.899236 1, 0xFFFF, sum = 0
2683 13:21:59.899319 2, 0xFFFF, sum = 0
2684 13:21:59.902247 3, 0xFFFF, sum = 0
2685 13:21:59.902330 4, 0xFFFF, sum = 0
2686 13:21:59.905522 5, 0xFFFF, sum = 0
2687 13:21:59.905605 6, 0xFFFF, sum = 0
2688 13:21:59.908723 7, 0xFFFF, sum = 0
2689 13:21:59.908806 8, 0xFFFF, sum = 0
2690 13:21:59.912173 9, 0xFFFF, sum = 0
2691 13:21:59.915718 10, 0xFFFF, sum = 0
2692 13:21:59.915800 11, 0xFFFF, sum = 0
2693 13:21:59.918804 12, 0x0, sum = 1
2694 13:21:59.918886 13, 0x0, sum = 2
2695 13:21:59.922317 14, 0x0, sum = 3
2696 13:21:59.922400 15, 0x0, sum = 4
2697 13:21:59.922467 best_step = 13
2698 13:21:59.922526
2699 13:21:59.925454 ==
2700 13:21:59.929066 Dram Type= 6, Freq= 0, CH_0, rank 0
2701 13:21:59.932462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2702 13:21:59.932545 ==
2703 13:21:59.932610 RX Vref Scan: 1
2704 13:21:59.932669
2705 13:21:59.935646 Set Vref Range= 32 -> 127
2706 13:21:59.935727
2707 13:21:59.939098 RX Vref 32 -> 127, step: 1
2708 13:21:59.939179
2709 13:21:59.942140 RX Delay -37 -> 252, step: 4
2710 13:21:59.942221
2711 13:21:59.945506 Set Vref, RX VrefLevel [Byte0]: 32
2712 13:21:59.949019 [Byte1]: 32
2713 13:21:59.949101
2714 13:21:59.952372 Set Vref, RX VrefLevel [Byte0]: 33
2715 13:21:59.955336 [Byte1]: 33
2716 13:21:59.955453
2717 13:21:59.959021 Set Vref, RX VrefLevel [Byte0]: 34
2718 13:21:59.962019 [Byte1]: 34
2719 13:21:59.966568
2720 13:21:59.966649 Set Vref, RX VrefLevel [Byte0]: 35
2721 13:21:59.969889 [Byte1]: 35
2722 13:21:59.974555
2723 13:21:59.974636 Set Vref, RX VrefLevel [Byte0]: 36
2724 13:21:59.978110 [Byte1]: 36
2725 13:21:59.982368
2726 13:21:59.982461 Set Vref, RX VrefLevel [Byte0]: 37
2727 13:21:59.986084 [Byte1]: 37
2728 13:21:59.990505
2729 13:21:59.990589 Set Vref, RX VrefLevel [Byte0]: 38
2730 13:21:59.993673 [Byte1]: 38
2731 13:21:59.998845
2732 13:21:59.998921 Set Vref, RX VrefLevel [Byte0]: 39
2733 13:22:00.002268 [Byte1]: 39
2734 13:22:00.006645
2735 13:22:00.006719 Set Vref, RX VrefLevel [Byte0]: 40
2736 13:22:00.009830 [Byte1]: 40
2737 13:22:00.014348
2738 13:22:00.014436 Set Vref, RX VrefLevel [Byte0]: 41
2739 13:22:00.018190 [Byte1]: 41
2740 13:22:00.022462
2741 13:22:00.022546 Set Vref, RX VrefLevel [Byte0]: 42
2742 13:22:00.026060 [Byte1]: 42
2743 13:22:00.030346
2744 13:22:00.030428 Set Vref, RX VrefLevel [Byte0]: 43
2745 13:22:00.033946 [Byte1]: 43
2746 13:22:00.038542
2747 13:22:00.038623 Set Vref, RX VrefLevel [Byte0]: 44
2748 13:22:00.041829 [Byte1]: 44
2749 13:22:00.046704
2750 13:22:00.046785 Set Vref, RX VrefLevel [Byte0]: 45
2751 13:22:00.049991 [Byte1]: 45
2752 13:22:00.054519
2753 13:22:00.054601 Set Vref, RX VrefLevel [Byte0]: 46
2754 13:22:00.057886 [Byte1]: 46
2755 13:22:00.062593
2756 13:22:00.062674 Set Vref, RX VrefLevel [Byte0]: 47
2757 13:22:00.065768 [Byte1]: 47
2758 13:22:00.070673
2759 13:22:00.070781 Set Vref, RX VrefLevel [Byte0]: 48
2760 13:22:00.074090 [Byte1]: 48
2761 13:22:00.078501
2762 13:22:00.078582 Set Vref, RX VrefLevel [Byte0]: 49
2763 13:22:00.081797 [Byte1]: 49
2764 13:22:00.086704
2765 13:22:00.086786 Set Vref, RX VrefLevel [Byte0]: 50
2766 13:22:00.090008 [Byte1]: 50
2767 13:22:00.094763
2768 13:22:00.094844 Set Vref, RX VrefLevel [Byte0]: 51
2769 13:22:00.098297 [Byte1]: 51
2770 13:22:00.102764
2771 13:22:00.102848 Set Vref, RX VrefLevel [Byte0]: 52
2772 13:22:00.105985 [Byte1]: 52
2773 13:22:00.110576
2774 13:22:00.110663 Set Vref, RX VrefLevel [Byte0]: 53
2775 13:22:00.113770 [Byte1]: 53
2776 13:22:00.118480
2777 13:22:00.118566 Set Vref, RX VrefLevel [Byte0]: 54
2778 13:22:00.121857 [Byte1]: 54
2779 13:22:00.126514
2780 13:22:00.126598 Set Vref, RX VrefLevel [Byte0]: 55
2781 13:22:00.130078 [Byte1]: 55
2782 13:22:00.134303
2783 13:22:00.137656 Set Vref, RX VrefLevel [Byte0]: 56
2784 13:22:00.141151 [Byte1]: 56
2785 13:22:00.141234
2786 13:22:00.144500 Set Vref, RX VrefLevel [Byte0]: 57
2787 13:22:00.147556 [Byte1]: 57
2788 13:22:00.147631
2789 13:22:00.151069 Set Vref, RX VrefLevel [Byte0]: 58
2790 13:22:00.154816 [Byte1]: 58
2791 13:22:00.158567
2792 13:22:00.158648 Set Vref, RX VrefLevel [Byte0]: 59
2793 13:22:00.162303 [Byte1]: 59
2794 13:22:00.166911
2795 13:22:00.166985 Set Vref, RX VrefLevel [Byte0]: 60
2796 13:22:00.169993 [Byte1]: 60
2797 13:22:00.174340
2798 13:22:00.174431 Set Vref, RX VrefLevel [Byte0]: 61
2799 13:22:00.178144 [Byte1]: 61
2800 13:22:00.182852
2801 13:22:00.182932 Set Vref, RX VrefLevel [Byte0]: 62
2802 13:22:00.185976 [Byte1]: 62
2803 13:22:00.190724
2804 13:22:00.190827 Set Vref, RX VrefLevel [Byte0]: 63
2805 13:22:00.193701 [Byte1]: 63
2806 13:22:00.198843
2807 13:22:00.198922 Set Vref, RX VrefLevel [Byte0]: 64
2808 13:22:00.202474 [Byte1]: 64
2809 13:22:00.206635
2810 13:22:00.206717 Set Vref, RX VrefLevel [Byte0]: 65
2811 13:22:00.210081 [Byte1]: 65
2812 13:22:00.214324
2813 13:22:00.214421 Set Vref, RX VrefLevel [Byte0]: 66
2814 13:22:00.217955 [Byte1]: 66
2815 13:22:00.222530
2816 13:22:00.222607 Set Vref, RX VrefLevel [Byte0]: 67
2817 13:22:00.225701 [Byte1]: 67
2818 13:22:00.230479
2819 13:22:00.230580 Set Vref, RX VrefLevel [Byte0]: 68
2820 13:22:00.234061 [Byte1]: 68
2821 13:22:00.238342
2822 13:22:00.238421 Set Vref, RX VrefLevel [Byte0]: 69
2823 13:22:00.242110 [Byte1]: 69
2824 13:22:00.246300
2825 13:22:00.246376 Set Vref, RX VrefLevel [Byte0]: 70
2826 13:22:00.249625 [Byte1]: 70
2827 13:22:00.254440
2828 13:22:00.254520 Set Vref, RX VrefLevel [Byte0]: 71
2829 13:22:00.258195 [Byte1]: 71
2830 13:22:00.262699
2831 13:22:00.262781 Set Vref, RX VrefLevel [Byte0]: 72
2832 13:22:00.266338 [Byte1]: 72
2833 13:22:00.270551
2834 13:22:00.270633 Set Vref, RX VrefLevel [Byte0]: 73
2835 13:22:00.274169 [Byte1]: 73
2836 13:22:00.278440
2837 13:22:00.278521 Final RX Vref Byte 0 = 61 to rank0
2838 13:22:00.282261 Final RX Vref Byte 1 = 54 to rank0
2839 13:22:00.285416 Final RX Vref Byte 0 = 61 to rank1
2840 13:22:00.288355 Final RX Vref Byte 1 = 54 to rank1==
2841 13:22:00.291915 Dram Type= 6, Freq= 0, CH_0, rank 0
2842 13:22:00.298391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2843 13:22:00.298487 ==
2844 13:22:00.298567 DQS Delay:
2845 13:22:00.298670 DQS0 = 0, DQS1 = 0
2846 13:22:00.302335 DQM Delay:
2847 13:22:00.302429 DQM0 = 112, DQM1 = 101
2848 13:22:00.305239 DQ Delay:
2849 13:22:00.308521 DQ0 =112, DQ1 =112, DQ2 =112, DQ3 =108
2850 13:22:00.311892 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2851 13:22:00.315500 DQ8 =92, DQ9 =86, DQ10 =104, DQ11 =94
2852 13:22:00.318647 DQ12 =106, DQ13 =106, DQ14 =116, DQ15 =110
2853 13:22:00.318774
2854 13:22:00.318901
2855 13:22:00.325660 [DQSOSCAuto] RK0, (LSB)MR18= 0xfffe, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
2856 13:22:00.328420 CH0 RK0: MR19=303, MR18=FFFE
2857 13:22:00.335264 CH0_RK0: MR19=0x303, MR18=0xFFFE, DQSOSC=410, MR23=63, INC=39, DEC=26
2858 13:22:00.335388
2859 13:22:00.338586 ----->DramcWriteLeveling(PI) begin...
2860 13:22:00.338705 ==
2861 13:22:00.342365 Dram Type= 6, Freq= 0, CH_0, rank 1
2862 13:22:00.345041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2863 13:22:00.345124 ==
2864 13:22:00.348534 Write leveling (Byte 0): 31 => 31
2865 13:22:00.351898 Write leveling (Byte 1): 29 => 29
2866 13:22:00.355260 DramcWriteLeveling(PI) end<-----
2867 13:22:00.355368
2868 13:22:00.355477 ==
2869 13:22:00.358440 Dram Type= 6, Freq= 0, CH_0, rank 1
2870 13:22:00.365043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2871 13:22:00.365127 ==
2872 13:22:00.365192 [Gating] SW mode calibration
2873 13:22:00.375109 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2874 13:22:00.378473 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2875 13:22:00.381679 0 15 0 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
2876 13:22:00.388423 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2877 13:22:00.391941 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2878 13:22:00.395487 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2879 13:22:00.401778 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2880 13:22:00.405045 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2881 13:22:00.408561 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2882 13:22:00.415103 0 15 28 | B1->B0 | 3434 2424 | 0 0 | (0 1) (1 0)
2883 13:22:00.418828 1 0 0 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
2884 13:22:00.421626 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2885 13:22:00.428259 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2886 13:22:00.431664 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2887 13:22:00.435110 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2888 13:22:00.441900 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2889 13:22:00.444895 1 0 24 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2890 13:22:00.448451 1 0 28 | B1->B0 | 2727 4545 | 1 0 | (0 0) (0 0)
2891 13:22:00.455112 1 1 0 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
2892 13:22:00.458664 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2893 13:22:00.461516 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2894 13:22:00.468119 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2895 13:22:00.471447 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2896 13:22:00.474716 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2897 13:22:00.481536 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2898 13:22:00.485264 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2899 13:22:00.488262 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 13:22:00.491770 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 13:22:00.498124 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 13:22:00.501615 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 13:22:00.504848 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 13:22:00.512056 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 13:22:00.515226 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 13:22:00.518307 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 13:22:00.525006 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 13:22:00.528233 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 13:22:00.531504 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 13:22:00.538490 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 13:22:00.541644 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 13:22:00.545091 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 13:22:00.551579 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 13:22:00.555083 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2915 13:22:00.558513 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 13:22:00.562273 Total UI for P1: 0, mck2ui 16
2917 13:22:00.565436 best dqsien dly found for B0: ( 1, 3, 28)
2918 13:22:00.569001 Total UI for P1: 0, mck2ui 16
2919 13:22:00.571947 best dqsien dly found for B1: ( 1, 3, 30)
2920 13:22:00.575499 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2921 13:22:00.578543 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2922 13:22:00.578624
2923 13:22:00.581873 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2924 13:22:00.588725 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2925 13:22:00.588807 [Gating] SW calibration Done
2926 13:22:00.588872 ==
2927 13:22:00.591639 Dram Type= 6, Freq= 0, CH_0, rank 1
2928 13:22:00.598427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2929 13:22:00.598528 ==
2930 13:22:00.598608 RX Vref Scan: 0
2931 13:22:00.598669
2932 13:22:00.601770 RX Vref 0 -> 0, step: 1
2933 13:22:00.601851
2934 13:22:00.605549 RX Delay -40 -> 252, step: 8
2935 13:22:00.608259 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2936 13:22:00.611888 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2937 13:22:00.615479 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2938 13:22:00.618383 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2939 13:22:00.625115 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2940 13:22:00.628678 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2941 13:22:00.632233 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2942 13:22:00.635224 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2943 13:22:00.638947 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2944 13:22:00.641790 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2945 13:22:00.648701 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2946 13:22:00.652301 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2947 13:22:00.655266 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2948 13:22:00.658551 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2949 13:22:00.665048 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2950 13:22:00.668289 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2951 13:22:00.668371 ==
2952 13:22:00.671950 Dram Type= 6, Freq= 0, CH_0, rank 1
2953 13:22:00.675139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2954 13:22:00.675291 ==
2955 13:22:00.678407 DQS Delay:
2956 13:22:00.678534 DQS0 = 0, DQS1 = 0
2957 13:22:00.678600 DQM Delay:
2958 13:22:00.681831 DQM0 = 112, DQM1 = 101
2959 13:22:00.681905 DQ Delay:
2960 13:22:00.685099 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2961 13:22:00.688321 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =123
2962 13:22:00.691528 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2963 13:22:00.695178 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =107
2964 13:22:00.695259
2965 13:22:00.699295
2966 13:22:00.699437 ==
2967 13:22:00.701707 Dram Type= 6, Freq= 0, CH_0, rank 1
2968 13:22:00.705060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2969 13:22:00.705158 ==
2970 13:22:00.705236
2971 13:22:00.705296
2972 13:22:00.708438 TX Vref Scan disable
2973 13:22:00.708535 == TX Byte 0 ==
2974 13:22:00.715103 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2975 13:22:00.718438 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2976 13:22:00.718513 == TX Byte 1 ==
2977 13:22:00.725387 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2978 13:22:00.728358 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2979 13:22:00.728440 ==
2980 13:22:00.731942 Dram Type= 6, Freq= 0, CH_0, rank 1
2981 13:22:00.734981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2982 13:22:00.735073 ==
2983 13:22:00.747885 TX Vref=22, minBit 2, minWin=26, winSum=429
2984 13:22:00.750552 TX Vref=24, minBit 2, minWin=26, winSum=431
2985 13:22:00.753908 TX Vref=26, minBit 0, minWin=27, winSum=434
2986 13:22:00.757535 TX Vref=28, minBit 12, minWin=26, winSum=438
2987 13:22:00.761109 TX Vref=30, minBit 1, minWin=27, winSum=445
2988 13:22:00.763923 TX Vref=32, minBit 8, minWin=26, winSum=440
2989 13:22:00.770769 [TxChooseVref] Worse bit 1, Min win 27, Win sum 445, Final Vref 30
2990 13:22:00.770851
2991 13:22:00.774353 Final TX Range 1 Vref 30
2992 13:22:00.774435
2993 13:22:00.774500 ==
2994 13:22:00.777425 Dram Type= 6, Freq= 0, CH_0, rank 1
2995 13:22:00.780941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2996 13:22:00.781023 ==
2997 13:22:00.781088
2998 13:22:00.784316
2999 13:22:00.784392 TX Vref Scan disable
3000 13:22:00.787188 == TX Byte 0 ==
3001 13:22:00.790866 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3002 13:22:00.794374 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3003 13:22:00.797374 == TX Byte 1 ==
3004 13:22:00.800898 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3005 13:22:00.804030 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3006 13:22:00.804136
3007 13:22:00.807260 [DATLAT]
3008 13:22:00.807402 Freq=1200, CH0 RK1
3009 13:22:00.807494
3010 13:22:00.810609 DATLAT Default: 0xd
3011 13:22:00.810700 0, 0xFFFF, sum = 0
3012 13:22:00.814026 1, 0xFFFF, sum = 0
3013 13:22:00.814134 2, 0xFFFF, sum = 0
3014 13:22:00.817353 3, 0xFFFF, sum = 0
3015 13:22:00.817501 4, 0xFFFF, sum = 0
3016 13:22:00.820522 5, 0xFFFF, sum = 0
3017 13:22:00.820627 6, 0xFFFF, sum = 0
3018 13:22:00.824398 7, 0xFFFF, sum = 0
3019 13:22:00.827661 8, 0xFFFF, sum = 0
3020 13:22:00.827747 9, 0xFFFF, sum = 0
3021 13:22:00.830811 10, 0xFFFF, sum = 0
3022 13:22:00.830919 11, 0xFFFF, sum = 0
3023 13:22:00.834014 12, 0x0, sum = 1
3024 13:22:00.834115 13, 0x0, sum = 2
3025 13:22:00.836995 14, 0x0, sum = 3
3026 13:22:00.837105 15, 0x0, sum = 4
3027 13:22:00.837198 best_step = 13
3028 13:22:00.837290
3029 13:22:00.840639 ==
3030 13:22:00.843732 Dram Type= 6, Freq= 0, CH_0, rank 1
3031 13:22:00.847229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3032 13:22:00.847329 ==
3033 13:22:00.847445 RX Vref Scan: 0
3034 13:22:00.847506
3035 13:22:00.850711 RX Vref 0 -> 0, step: 1
3036 13:22:00.850814
3037 13:22:00.853720 RX Delay -37 -> 252, step: 4
3038 13:22:00.857104 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3039 13:22:00.863519 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3040 13:22:00.866988 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3041 13:22:00.870427 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3042 13:22:00.873415 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3043 13:22:00.876909 iDelay=195, Bit 5, Center 102 (35 ~ 170) 136
3044 13:22:00.883896 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3045 13:22:00.887177 iDelay=195, Bit 7, Center 118 (43 ~ 194) 152
3046 13:22:00.890419 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3047 13:22:00.893210 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3048 13:22:00.896776 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3049 13:22:00.903348 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3050 13:22:00.906689 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3051 13:22:00.910072 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3052 13:22:00.913405 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3053 13:22:00.916862 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3054 13:22:00.920213 ==
3055 13:22:00.923195 Dram Type= 6, Freq= 0, CH_0, rank 1
3056 13:22:00.926838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3057 13:22:00.926913 ==
3058 13:22:00.926975 DQS Delay:
3059 13:22:00.930097 DQS0 = 0, DQS1 = 0
3060 13:22:00.930170 DQM Delay:
3061 13:22:00.933074 DQM0 = 111, DQM1 = 101
3062 13:22:00.933146 DQ Delay:
3063 13:22:00.936907 DQ0 =108, DQ1 =112, DQ2 =108, DQ3 =108
3064 13:22:00.940140 DQ4 =112, DQ5 =102, DQ6 =120, DQ7 =118
3065 13:22:00.943356 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =94
3066 13:22:00.946918 DQ12 =110, DQ13 =108, DQ14 =114, DQ15 =110
3067 13:22:00.946992
3068 13:22:00.947062
3069 13:22:00.956903 [DQSOSCAuto] RK1, (LSB)MR18= 0x12fa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 403 ps
3070 13:22:00.956998 CH0 RK1: MR19=403, MR18=12FA
3071 13:22:00.963477 CH0_RK1: MR19=0x403, MR18=0x12FA, DQSOSC=403, MR23=63, INC=40, DEC=26
3072 13:22:00.966874 [RxdqsGatingPostProcess] freq 1200
3073 13:22:00.973243 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3074 13:22:00.976839 best DQS0 dly(2T, 0.5T) = (0, 11)
3075 13:22:00.980443 best DQS1 dly(2T, 0.5T) = (0, 12)
3076 13:22:00.983232 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3077 13:22:00.986880 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3078 13:22:00.986955 best DQS0 dly(2T, 0.5T) = (0, 11)
3079 13:22:00.989951 best DQS1 dly(2T, 0.5T) = (0, 11)
3080 13:22:00.993527 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3081 13:22:00.997213 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3082 13:22:01.000173 Pre-setting of DQS Precalculation
3083 13:22:01.006805 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3084 13:22:01.006914 ==
3085 13:22:01.010165 Dram Type= 6, Freq= 0, CH_1, rank 0
3086 13:22:01.013658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3087 13:22:01.013740 ==
3088 13:22:01.020385 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3089 13:22:01.026643 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3090 13:22:01.033722 [CA 0] Center 37 (7~67) winsize 61
3091 13:22:01.036732 [CA 1] Center 37 (7~68) winsize 62
3092 13:22:01.040081 [CA 2] Center 34 (4~64) winsize 61
3093 13:22:01.043597 [CA 3] Center 34 (4~64) winsize 61
3094 13:22:01.046859 [CA 4] Center 34 (4~64) winsize 61
3095 13:22:01.050370 [CA 5] Center 33 (3~63) winsize 61
3096 13:22:01.050451
3097 13:22:01.053428 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3098 13:22:01.053509
3099 13:22:01.056890 [CATrainingPosCal] consider 1 rank data
3100 13:22:01.060036 u2DelayCellTimex100 = 270/100 ps
3101 13:22:01.064402 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3102 13:22:01.067029 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3103 13:22:01.073265 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3104 13:22:01.076642 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3105 13:22:01.080103 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3106 13:22:01.083713 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3107 13:22:01.083795
3108 13:22:01.087080 CA PerBit enable=1, Macro0, CA PI delay=33
3109 13:22:01.087176
3110 13:22:01.089915 [CBTSetCACLKResult] CA Dly = 33
3111 13:22:01.090061 CS Dly: 6 (0~37)
3112 13:22:01.090191 ==
3113 13:22:01.093457 Dram Type= 6, Freq= 0, CH_1, rank 1
3114 13:22:01.100006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3115 13:22:01.100087 ==
3116 13:22:01.103673 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3117 13:22:01.110409 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3118 13:22:01.119123 [CA 0] Center 37 (7~67) winsize 61
3119 13:22:01.122624 [CA 1] Center 37 (7~68) winsize 62
3120 13:22:01.125717 [CA 2] Center 34 (4~65) winsize 62
3121 13:22:01.129252 [CA 3] Center 33 (3~64) winsize 62
3122 13:22:01.132846 [CA 4] Center 34 (4~64) winsize 61
3123 13:22:01.135664 [CA 5] Center 32 (2~63) winsize 62
3124 13:22:01.135736
3125 13:22:01.139340 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3126 13:22:01.139441
3127 13:22:01.142547 [CATrainingPosCal] consider 2 rank data
3128 13:22:01.145779 u2DelayCellTimex100 = 270/100 ps
3129 13:22:01.149139 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3130 13:22:01.152707 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3131 13:22:01.159021 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3132 13:22:01.162784 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3133 13:22:01.165666 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3134 13:22:01.169301 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3135 13:22:01.169375
3136 13:22:01.172297 CA PerBit enable=1, Macro0, CA PI delay=33
3137 13:22:01.172371
3138 13:22:01.176169 [CBTSetCACLKResult] CA Dly = 33
3139 13:22:01.176242 CS Dly: 7 (0~39)
3140 13:22:01.176303
3141 13:22:01.179305 ----->DramcWriteLeveling(PI) begin...
3142 13:22:01.179446 ==
3143 13:22:01.182500 Dram Type= 6, Freq= 0, CH_1, rank 0
3144 13:22:01.189127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3145 13:22:01.189233 ==
3146 13:22:01.192932 Write leveling (Byte 0): 25 => 25
3147 13:22:01.195738 Write leveling (Byte 1): 30 => 30
3148 13:22:01.195813 DramcWriteLeveling(PI) end<-----
3149 13:22:01.199730
3150 13:22:01.199804 ==
3151 13:22:01.202300 Dram Type= 6, Freq= 0, CH_1, rank 0
3152 13:22:01.206027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3153 13:22:01.206103 ==
3154 13:22:01.209406 [Gating] SW mode calibration
3155 13:22:01.215880 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3156 13:22:01.219167 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3157 13:22:01.225840 0 15 0 | B1->B0 | 2e2e 2929 | 0 1 | (0 0) (0 0)
3158 13:22:01.228917 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3159 13:22:01.232320 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3160 13:22:01.239058 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3161 13:22:01.242089 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3162 13:22:01.245375 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3163 13:22:01.252184 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3164 13:22:01.255750 0 15 28 | B1->B0 | 2e2e 2f2f | 0 0 | (0 0) (0 1)
3165 13:22:01.259020 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3166 13:22:01.265608 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3167 13:22:01.268880 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3168 13:22:01.272263 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3169 13:22:01.278964 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3170 13:22:01.282540 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3171 13:22:01.285433 1 0 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3172 13:22:01.292576 1 0 28 | B1->B0 | 4040 4141 | 0 0 | (1 1) (0 0)
3173 13:22:01.296061 1 1 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3174 13:22:01.298910 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3175 13:22:01.302246 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3176 13:22:01.309283 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3177 13:22:01.312325 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3178 13:22:01.315806 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3179 13:22:01.322539 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3180 13:22:01.325540 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3181 13:22:01.329001 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3182 13:22:01.335770 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 13:22:01.339278 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 13:22:01.342351 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 13:22:01.349085 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 13:22:01.352491 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 13:22:01.355301 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 13:22:01.362062 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 13:22:01.365679 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 13:22:01.368588 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 13:22:01.375549 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 13:22:01.378688 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 13:22:01.382422 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 13:22:01.388449 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 13:22:01.392115 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 13:22:01.395705 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3197 13:22:01.401946 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 13:22:01.402021 Total UI for P1: 0, mck2ui 16
3199 13:22:01.409039 best dqsien dly found for B0: ( 1, 3, 28)
3200 13:22:01.409122 Total UI for P1: 0, mck2ui 16
3201 13:22:01.412161 best dqsien dly found for B1: ( 1, 3, 28)
3202 13:22:01.418523 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3203 13:22:01.421920 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3204 13:22:01.422030
3205 13:22:01.425165 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3206 13:22:01.428761 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3207 13:22:01.432148 [Gating] SW calibration Done
3208 13:22:01.432246 ==
3209 13:22:01.435286 Dram Type= 6, Freq= 0, CH_1, rank 0
3210 13:22:01.439268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3211 13:22:01.439394 ==
3212 13:22:01.442070 RX Vref Scan: 0
3213 13:22:01.442200
3214 13:22:01.442351 RX Vref 0 -> 0, step: 1
3215 13:22:01.442454
3216 13:22:01.445150 RX Delay -40 -> 252, step: 8
3217 13:22:01.448758 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3218 13:22:01.455409 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3219 13:22:01.458381 iDelay=208, Bit 2, Center 99 (24 ~ 175) 152
3220 13:22:01.462065 iDelay=208, Bit 3, Center 111 (40 ~ 183) 144
3221 13:22:01.465382 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3222 13:22:01.468648 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3223 13:22:01.471779 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3224 13:22:01.478991 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3225 13:22:01.481860 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3226 13:22:01.485444 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
3227 13:22:01.488697 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
3228 13:22:01.492339 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3229 13:22:01.498714 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3230 13:22:01.501864 iDelay=208, Bit 13, Center 115 (40 ~ 191) 152
3231 13:22:01.505824 iDelay=208, Bit 14, Center 111 (40 ~ 183) 144
3232 13:22:01.508807 iDelay=208, Bit 15, Center 111 (40 ~ 183) 144
3233 13:22:01.508884 ==
3234 13:22:01.512564 Dram Type= 6, Freq= 0, CH_1, rank 0
3235 13:22:01.518652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3236 13:22:01.518728 ==
3237 13:22:01.518792 DQS Delay:
3238 13:22:01.518851 DQS0 = 0, DQS1 = 0
3239 13:22:01.522433 DQM Delay:
3240 13:22:01.522510 DQM0 = 114, DQM1 = 107
3241 13:22:01.525332 DQ Delay:
3242 13:22:01.528512 DQ0 =119, DQ1 =111, DQ2 =99, DQ3 =111
3243 13:22:01.532519 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3244 13:22:01.535201 DQ8 =95, DQ9 =99, DQ10 =107, DQ11 =103
3245 13:22:01.538890 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3246 13:22:01.538971
3247 13:22:01.539036
3248 13:22:01.539096 ==
3249 13:22:01.542526 Dram Type= 6, Freq= 0, CH_1, rank 0
3250 13:22:01.545749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3251 13:22:01.545831 ==
3252 13:22:01.545895
3253 13:22:01.545955
3254 13:22:01.549076 TX Vref Scan disable
3255 13:22:01.552230 == TX Byte 0 ==
3256 13:22:01.555549 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3257 13:22:01.559264 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3258 13:22:01.562481 == TX Byte 1 ==
3259 13:22:01.565604 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3260 13:22:01.569222 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3261 13:22:01.569319 ==
3262 13:22:01.572002 Dram Type= 6, Freq= 0, CH_1, rank 0
3263 13:22:01.575446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3264 13:22:01.578608 ==
3265 13:22:01.589121 TX Vref=22, minBit 4, minWin=25, winSum=416
3266 13:22:01.592760 TX Vref=24, minBit 3, minWin=25, winSum=420
3267 13:22:01.595634 TX Vref=26, minBit 1, minWin=26, winSum=428
3268 13:22:01.598968 TX Vref=28, minBit 1, minWin=26, winSum=428
3269 13:22:01.602518 TX Vref=30, minBit 8, minWin=26, winSum=429
3270 13:22:01.605859 TX Vref=32, minBit 9, minWin=25, winSum=426
3271 13:22:01.612577 [TxChooseVref] Worse bit 8, Min win 26, Win sum 429, Final Vref 30
3272 13:22:01.612656
3273 13:22:01.616202 Final TX Range 1 Vref 30
3274 13:22:01.616275
3275 13:22:01.616339 ==
3276 13:22:01.619095 Dram Type= 6, Freq= 0, CH_1, rank 0
3277 13:22:01.622830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3278 13:22:01.622906 ==
3279 13:22:01.622967
3280 13:22:01.625805
3281 13:22:01.625875 TX Vref Scan disable
3282 13:22:01.628894 == TX Byte 0 ==
3283 13:22:01.632605 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3284 13:22:01.635596 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3285 13:22:01.639212 == TX Byte 1 ==
3286 13:22:01.642169 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3287 13:22:01.645532 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3288 13:22:01.645611
3289 13:22:01.649517 [DATLAT]
3290 13:22:01.649590 Freq=1200, CH1 RK0
3291 13:22:01.649653
3292 13:22:01.652483 DATLAT Default: 0xd
3293 13:22:01.652552 0, 0xFFFF, sum = 0
3294 13:22:01.655872 1, 0xFFFF, sum = 0
3295 13:22:01.655943 2, 0xFFFF, sum = 0
3296 13:22:01.659304 3, 0xFFFF, sum = 0
3297 13:22:01.659425 4, 0xFFFF, sum = 0
3298 13:22:01.662257 5, 0xFFFF, sum = 0
3299 13:22:01.662326 6, 0xFFFF, sum = 0
3300 13:22:01.665564 7, 0xFFFF, sum = 0
3301 13:22:01.665656 8, 0xFFFF, sum = 0
3302 13:22:01.669042 9, 0xFFFF, sum = 0
3303 13:22:01.672266 10, 0xFFFF, sum = 0
3304 13:22:01.672371 11, 0xFFFF, sum = 0
3305 13:22:01.675960 12, 0x0, sum = 1
3306 13:22:01.676114 13, 0x0, sum = 2
3307 13:22:01.676265 14, 0x0, sum = 3
3308 13:22:01.679239 15, 0x0, sum = 4
3309 13:22:01.679318 best_step = 13
3310 13:22:01.679391
3311 13:22:01.682349 ==
3312 13:22:01.682429 Dram Type= 6, Freq= 0, CH_1, rank 0
3313 13:22:01.688807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3314 13:22:01.688883 ==
3315 13:22:01.688947 RX Vref Scan: 1
3316 13:22:01.689003
3317 13:22:01.692524 Set Vref Range= 32 -> 127
3318 13:22:01.692599
3319 13:22:01.695571 RX Vref 32 -> 127, step: 1
3320 13:22:01.695702
3321 13:22:01.698785 RX Delay -21 -> 252, step: 4
3322 13:22:01.698886
3323 13:22:01.702136 Set Vref, RX VrefLevel [Byte0]: 32
3324 13:22:01.705362 [Byte1]: 32
3325 13:22:01.705449
3326 13:22:01.709102 Set Vref, RX VrefLevel [Byte0]: 33
3327 13:22:01.712306 [Byte1]: 33
3328 13:22:01.712396
3329 13:22:01.715756 Set Vref, RX VrefLevel [Byte0]: 34
3330 13:22:01.719056 [Byte1]: 34
3331 13:22:01.723420
3332 13:22:01.723513 Set Vref, RX VrefLevel [Byte0]: 35
3333 13:22:01.726569 [Byte1]: 35
3334 13:22:01.731195
3335 13:22:01.731298 Set Vref, RX VrefLevel [Byte0]: 36
3336 13:22:01.734791 [Byte1]: 36
3337 13:22:01.738913
3338 13:22:01.738986 Set Vref, RX VrefLevel [Byte0]: 37
3339 13:22:01.742458 [Byte1]: 37
3340 13:22:01.747198
3341 13:22:01.747299 Set Vref, RX VrefLevel [Byte0]: 38
3342 13:22:01.750659 [Byte1]: 38
3343 13:22:01.754869
3344 13:22:01.754968 Set Vref, RX VrefLevel [Byte0]: 39
3345 13:22:01.758494 [Byte1]: 39
3346 13:22:01.763133
3347 13:22:01.763236 Set Vref, RX VrefLevel [Byte0]: 40
3348 13:22:01.766108 [Byte1]: 40
3349 13:22:01.770862
3350 13:22:01.770930 Set Vref, RX VrefLevel [Byte0]: 41
3351 13:22:01.773824 [Byte1]: 41
3352 13:22:01.778563
3353 13:22:01.778635 Set Vref, RX VrefLevel [Byte0]: 42
3354 13:22:01.782069 [Byte1]: 42
3355 13:22:01.786653
3356 13:22:01.786732 Set Vref, RX VrefLevel [Byte0]: 43
3357 13:22:01.789921 [Byte1]: 43
3358 13:22:01.794618
3359 13:22:01.794743 Set Vref, RX VrefLevel [Byte0]: 44
3360 13:22:01.798233 [Byte1]: 44
3361 13:22:01.802455
3362 13:22:01.802552 Set Vref, RX VrefLevel [Byte0]: 45
3363 13:22:01.805813 [Byte1]: 45
3364 13:22:01.810824
3365 13:22:01.810925 Set Vref, RX VrefLevel [Byte0]: 46
3366 13:22:01.813783 [Byte1]: 46
3367 13:22:01.818236
3368 13:22:01.818313 Set Vref, RX VrefLevel [Byte0]: 47
3369 13:22:01.821847 [Byte1]: 47
3370 13:22:01.826211
3371 13:22:01.826285 Set Vref, RX VrefLevel [Byte0]: 48
3372 13:22:01.829484 [Byte1]: 48
3373 13:22:01.834166
3374 13:22:01.834247 Set Vref, RX VrefLevel [Byte0]: 49
3375 13:22:01.837505 [Byte1]: 49
3376 13:22:01.842077
3377 13:22:01.842169 Set Vref, RX VrefLevel [Byte0]: 50
3378 13:22:01.845490 [Byte1]: 50
3379 13:22:01.849865
3380 13:22:01.849935 Set Vref, RX VrefLevel [Byte0]: 51
3381 13:22:01.853320 [Byte1]: 51
3382 13:22:01.857949
3383 13:22:01.858019 Set Vref, RX VrefLevel [Byte0]: 52
3384 13:22:01.861092 [Byte1]: 52
3385 13:22:01.866032
3386 13:22:01.866135 Set Vref, RX VrefLevel [Byte0]: 53
3387 13:22:01.869153 [Byte1]: 53
3388 13:22:01.873641
3389 13:22:01.873759 Set Vref, RX VrefLevel [Byte0]: 54
3390 13:22:01.877325 [Byte1]: 54
3391 13:22:01.881863
3392 13:22:01.881936 Set Vref, RX VrefLevel [Byte0]: 55
3393 13:22:01.885002 [Byte1]: 55
3394 13:22:01.890009
3395 13:22:01.890114 Set Vref, RX VrefLevel [Byte0]: 56
3396 13:22:01.893023 [Byte1]: 56
3397 13:22:01.897749
3398 13:22:01.897830 Set Vref, RX VrefLevel [Byte0]: 57
3399 13:22:01.900977 [Byte1]: 57
3400 13:22:01.905425
3401 13:22:01.905498 Set Vref, RX VrefLevel [Byte0]: 58
3402 13:22:01.908844 [Byte1]: 58
3403 13:22:01.913281
3404 13:22:01.913350 Set Vref, RX VrefLevel [Byte0]: 59
3405 13:22:01.916855 [Byte1]: 59
3406 13:22:01.921496
3407 13:22:01.921570 Set Vref, RX VrefLevel [Byte0]: 60
3408 13:22:01.924440 [Byte1]: 60
3409 13:22:01.929375
3410 13:22:01.929449 Set Vref, RX VrefLevel [Byte0]: 61
3411 13:22:01.932390 [Byte1]: 61
3412 13:22:01.937769
3413 13:22:01.937842 Set Vref, RX VrefLevel [Byte0]: 62
3414 13:22:01.940391 [Byte1]: 62
3415 13:22:01.945134
3416 13:22:01.945212 Set Vref, RX VrefLevel [Byte0]: 63
3417 13:22:01.948578 [Byte1]: 63
3418 13:22:01.952981
3419 13:22:01.953050 Set Vref, RX VrefLevel [Byte0]: 64
3420 13:22:01.956043 [Byte1]: 64
3421 13:22:01.960776
3422 13:22:01.960874 Final RX Vref Byte 0 = 53 to rank0
3423 13:22:01.964198 Final RX Vref Byte 1 = 49 to rank0
3424 13:22:01.967603 Final RX Vref Byte 0 = 53 to rank1
3425 13:22:01.970790 Final RX Vref Byte 1 = 49 to rank1==
3426 13:22:01.974482 Dram Type= 6, Freq= 0, CH_1, rank 0
3427 13:22:01.980748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3428 13:22:01.980826 ==
3429 13:22:01.980924 DQS Delay:
3430 13:22:01.980986 DQS0 = 0, DQS1 = 0
3431 13:22:01.984436 DQM Delay:
3432 13:22:01.984536 DQM0 = 114, DQM1 = 104
3433 13:22:01.987974 DQ Delay:
3434 13:22:01.991126 DQ0 =116, DQ1 =112, DQ2 =104, DQ3 =112
3435 13:22:01.994154 DQ4 =112, DQ5 =124, DQ6 =124, DQ7 =112
3436 13:22:01.998023 DQ8 =92, DQ9 =96, DQ10 =102, DQ11 =100
3437 13:22:02.001378 DQ12 =112, DQ13 =110, DQ14 =114, DQ15 =110
3438 13:22:02.001481
3439 13:22:02.001579
3440 13:22:02.007820 [DQSOSCAuto] RK0, (LSB)MR18= 0xf2f9, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 415 ps
3441 13:22:02.011495 CH1 RK0: MR19=303, MR18=F2F9
3442 13:22:02.017796 CH1_RK0: MR19=0x303, MR18=0xF2F9, DQSOSC=412, MR23=63, INC=38, DEC=25
3443 13:22:02.017899
3444 13:22:02.021233 ----->DramcWriteLeveling(PI) begin...
3445 13:22:02.021334 ==
3446 13:22:02.024599 Dram Type= 6, Freq= 0, CH_1, rank 1
3447 13:22:02.027816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3448 13:22:02.027919 ==
3449 13:22:02.030948 Write leveling (Byte 0): 24 => 24
3450 13:22:02.034702 Write leveling (Byte 1): 27 => 27
3451 13:22:02.037688 DramcWriteLeveling(PI) end<-----
3452 13:22:02.037759
3453 13:22:02.037820 ==
3454 13:22:02.041006 Dram Type= 6, Freq= 0, CH_1, rank 1
3455 13:22:02.047613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3456 13:22:02.047689 ==
3457 13:22:02.047761 [Gating] SW mode calibration
3458 13:22:02.057720 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3459 13:22:02.061200 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3460 13:22:02.064367 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3461 13:22:02.071337 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3462 13:22:02.074149 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3463 13:22:02.077598 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3464 13:22:02.084475 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3465 13:22:02.087577 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3466 13:22:02.091017 0 15 24 | B1->B0 | 3434 2424 | 0 0 | (0 1) (0 0)
3467 13:22:02.097710 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
3468 13:22:02.101324 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3469 13:22:02.104515 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3470 13:22:02.111217 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3471 13:22:02.114284 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3472 13:22:02.117569 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3473 13:22:02.124392 1 0 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3474 13:22:02.127906 1 0 24 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
3475 13:22:02.130901 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3476 13:22:02.134495 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 13:22:02.141257 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 13:22:02.144376 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 13:22:02.148058 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 13:22:02.154521 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 13:22:02.157426 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3482 13:22:02.160802 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3483 13:22:02.167466 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3484 13:22:02.170885 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 13:22:02.174675 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 13:22:02.180806 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 13:22:02.184258 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 13:22:02.187579 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 13:22:02.194044 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 13:22:02.197702 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 13:22:02.200908 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 13:22:02.207364 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 13:22:02.211058 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 13:22:02.214098 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 13:22:02.220961 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 13:22:02.224056 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 13:22:02.227583 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3498 13:22:02.234236 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3499 13:22:02.237224 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 13:22:02.240785 Total UI for P1: 0, mck2ui 16
3501 13:22:02.244179 best dqsien dly found for B0: ( 1, 3, 22)
3502 13:22:02.247049 Total UI for P1: 0, mck2ui 16
3503 13:22:02.250263 best dqsien dly found for B1: ( 1, 3, 26)
3504 13:22:02.253820 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3505 13:22:02.257554 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3506 13:22:02.257650
3507 13:22:02.260645 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3508 13:22:02.263642 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3509 13:22:02.266942 [Gating] SW calibration Done
3510 13:22:02.267045 ==
3511 13:22:02.270539 Dram Type= 6, Freq= 0, CH_1, rank 1
3512 13:22:02.273483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3513 13:22:02.277051 ==
3514 13:22:02.277156 RX Vref Scan: 0
3515 13:22:02.277246
3516 13:22:02.280152 RX Vref 0 -> 0, step: 1
3517 13:22:02.280256
3518 13:22:02.283583 RX Delay -40 -> 252, step: 8
3519 13:22:02.286689 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3520 13:22:02.290119 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3521 13:22:02.293599 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3522 13:22:02.296807 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3523 13:22:02.303270 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3524 13:22:02.307095 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3525 13:22:02.309918 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3526 13:22:02.313545 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3527 13:22:02.316665 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3528 13:22:02.319963 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3529 13:22:02.326886 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3530 13:22:02.329828 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
3531 13:22:02.333309 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3532 13:22:02.336411 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3533 13:22:02.342934 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3534 13:22:02.346520 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3535 13:22:02.346593 ==
3536 13:22:02.349557 Dram Type= 6, Freq= 0, CH_1, rank 1
3537 13:22:02.353242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3538 13:22:02.353316 ==
3539 13:22:02.353378 DQS Delay:
3540 13:22:02.356816 DQS0 = 0, DQS1 = 0
3541 13:22:02.356892 DQM Delay:
3542 13:22:02.359497 DQM0 = 110, DQM1 = 105
3543 13:22:02.359565 DQ Delay:
3544 13:22:02.362862 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3545 13:22:02.366304 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3546 13:22:02.369681 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =95
3547 13:22:02.372936 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3548 13:22:02.376346
3549 13:22:02.376426
3550 13:22:02.376493 ==
3551 13:22:02.379543 Dram Type= 6, Freq= 0, CH_1, rank 1
3552 13:22:02.383099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3553 13:22:02.383235 ==
3554 13:22:02.383342
3555 13:22:02.383464
3556 13:22:02.386435 TX Vref Scan disable
3557 13:22:02.386545 == TX Byte 0 ==
3558 13:22:02.393364 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3559 13:22:02.396147 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3560 13:22:02.396253 == TX Byte 1 ==
3561 13:22:02.402812 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3562 13:22:02.406225 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3563 13:22:02.406327 ==
3564 13:22:02.409126 Dram Type= 6, Freq= 0, CH_1, rank 1
3565 13:22:02.412620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3566 13:22:02.412726 ==
3567 13:22:02.425069 TX Vref=22, minBit 1, minWin=26, winSum=422
3568 13:22:02.428867 TX Vref=24, minBit 1, minWin=26, winSum=423
3569 13:22:02.431920 TX Vref=26, minBit 8, minWin=26, winSum=432
3570 13:22:02.435487 TX Vref=28, minBit 8, minWin=26, winSum=431
3571 13:22:02.438507 TX Vref=30, minBit 1, minWin=26, winSum=429
3572 13:22:02.445176 TX Vref=32, minBit 4, minWin=26, winSum=430
3573 13:22:02.448722 [TxChooseVref] Worse bit 8, Min win 26, Win sum 432, Final Vref 26
3574 13:22:02.448805
3575 13:22:02.451621 Final TX Range 1 Vref 26
3576 13:22:02.451705
3577 13:22:02.451765 ==
3578 13:22:02.455275 Dram Type= 6, Freq= 0, CH_1, rank 1
3579 13:22:02.458698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3580 13:22:02.458775 ==
3581 13:22:02.461723
3582 13:22:02.461793
3583 13:22:02.461852 TX Vref Scan disable
3584 13:22:02.465040 == TX Byte 0 ==
3585 13:22:02.468477 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3586 13:22:02.471529 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3587 13:22:02.475275 == TX Byte 1 ==
3588 13:22:02.478015 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3589 13:22:02.485261 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3590 13:22:02.485356
3591 13:22:02.485455 [DATLAT]
3592 13:22:02.485548 Freq=1200, CH1 RK1
3593 13:22:02.485619
3594 13:22:02.488157 DATLAT Default: 0xd
3595 13:22:02.488254 0, 0xFFFF, sum = 0
3596 13:22:02.491361 1, 0xFFFF, sum = 0
3597 13:22:02.494703 2, 0xFFFF, sum = 0
3598 13:22:02.494831 3, 0xFFFF, sum = 0
3599 13:22:02.498520 4, 0xFFFF, sum = 0
3600 13:22:02.498620 5, 0xFFFF, sum = 0
3601 13:22:02.501891 6, 0xFFFF, sum = 0
3602 13:22:02.501995 7, 0xFFFF, sum = 0
3603 13:22:02.504873 8, 0xFFFF, sum = 0
3604 13:22:02.504993 9, 0xFFFF, sum = 0
3605 13:22:02.508286 10, 0xFFFF, sum = 0
3606 13:22:02.508368 11, 0xFFFF, sum = 0
3607 13:22:02.511359 12, 0x0, sum = 1
3608 13:22:02.511470 13, 0x0, sum = 2
3609 13:22:02.514873 14, 0x0, sum = 3
3610 13:22:02.514973 15, 0x0, sum = 4
3611 13:22:02.517798 best_step = 13
3612 13:22:02.517869
3613 13:22:02.517930 ==
3614 13:22:02.521225 Dram Type= 6, Freq= 0, CH_1, rank 1
3615 13:22:02.524587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3616 13:22:02.524663 ==
3617 13:22:02.524726 RX Vref Scan: 0
3618 13:22:02.528324
3619 13:22:02.528405 RX Vref 0 -> 0, step: 1
3620 13:22:02.528469
3621 13:22:02.531060 RX Delay -21 -> 252, step: 4
3622 13:22:02.537893 iDelay=195, Bit 0, Center 112 (39 ~ 186) 148
3623 13:22:02.541119 iDelay=195, Bit 1, Center 108 (39 ~ 178) 140
3624 13:22:02.544368 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3625 13:22:02.548003 iDelay=195, Bit 3, Center 106 (35 ~ 178) 144
3626 13:22:02.550907 iDelay=195, Bit 4, Center 106 (35 ~ 178) 144
3627 13:22:02.557570 iDelay=195, Bit 5, Center 120 (51 ~ 190) 140
3628 13:22:02.561304 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3629 13:22:02.564552 iDelay=195, Bit 7, Center 108 (39 ~ 178) 140
3630 13:22:02.567475 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
3631 13:22:02.571067 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3632 13:22:02.577535 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3633 13:22:02.580678 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3634 13:22:02.584137 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3635 13:22:02.587145 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3636 13:22:02.590777 iDelay=195, Bit 14, Center 114 (51 ~ 178) 128
3637 13:22:02.597324 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3638 13:22:02.597396 ==
3639 13:22:02.600947 Dram Type= 6, Freq= 0, CH_1, rank 1
3640 13:22:02.604306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3641 13:22:02.604392 ==
3642 13:22:02.604457 DQS Delay:
3643 13:22:02.607379 DQS0 = 0, DQS1 = 0
3644 13:22:02.607460 DQM Delay:
3645 13:22:02.610539 DQM0 = 110, DQM1 = 108
3646 13:22:02.610606 DQ Delay:
3647 13:22:02.614277 DQ0 =112, DQ1 =108, DQ2 =100, DQ3 =106
3648 13:22:02.617542 DQ4 =106, DQ5 =120, DQ6 =122, DQ7 =108
3649 13:22:02.620910 DQ8 =94, DQ9 =100, DQ10 =110, DQ11 =100
3650 13:22:02.624139 DQ12 =116, DQ13 =116, DQ14 =114, DQ15 =116
3651 13:22:02.624248
3652 13:22:02.624339
3653 13:22:02.633690 [DQSOSCAuto] RK1, (LSB)MR18= 0xfc0c, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 411 ps
3654 13:22:02.636982 CH1 RK1: MR19=304, MR18=FC0C
3655 13:22:02.643365 CH1_RK1: MR19=0x304, MR18=0xFC0C, DQSOSC=405, MR23=63, INC=39, DEC=26
3656 13:22:02.647201 [RxdqsGatingPostProcess] freq 1200
3657 13:22:02.650428 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3658 13:22:02.653590 best DQS0 dly(2T, 0.5T) = (0, 11)
3659 13:22:02.656855 best DQS1 dly(2T, 0.5T) = (0, 11)
3660 13:22:02.660567 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3661 13:22:02.663643 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3662 13:22:02.666495 best DQS0 dly(2T, 0.5T) = (0, 11)
3663 13:22:02.670360 best DQS1 dly(2T, 0.5T) = (0, 11)
3664 13:22:02.673404 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3665 13:22:02.676490 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3666 13:22:02.680081 Pre-setting of DQS Precalculation
3667 13:22:02.683678 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3668 13:22:02.690251 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3669 13:22:02.699769 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3670 13:22:02.699877
3671 13:22:02.699943
3672 13:22:02.703561 [Calibration Summary] 2400 Mbps
3673 13:22:02.703642 CH 0, Rank 0
3674 13:22:02.706686 SW Impedance : PASS
3675 13:22:02.706758 DUTY Scan : NO K
3676 13:22:02.709668 ZQ Calibration : PASS
3677 13:22:02.713309 Jitter Meter : NO K
3678 13:22:02.713438 CBT Training : PASS
3679 13:22:02.716621 Write leveling : PASS
3680 13:22:02.719520 RX DQS gating : PASS
3681 13:22:02.719597 RX DQ/DQS(RDDQC) : PASS
3682 13:22:02.723009 TX DQ/DQS : PASS
3683 13:22:02.723113 RX DATLAT : PASS
3684 13:22:02.726723 RX DQ/DQS(Engine): PASS
3685 13:22:02.729559 TX OE : NO K
3686 13:22:02.729630 All Pass.
3687 13:22:02.729696
3688 13:22:02.729754 CH 0, Rank 1
3689 13:22:02.732900 SW Impedance : PASS
3690 13:22:02.736693 DUTY Scan : NO K
3691 13:22:02.736821 ZQ Calibration : PASS
3692 13:22:02.739576 Jitter Meter : NO K
3693 13:22:02.743304 CBT Training : PASS
3694 13:22:02.743393 Write leveling : PASS
3695 13:22:02.746337 RX DQS gating : PASS
3696 13:22:02.749434 RX DQ/DQS(RDDQC) : PASS
3697 13:22:02.749524 TX DQ/DQS : PASS
3698 13:22:02.752841 RX DATLAT : PASS
3699 13:22:02.756254 RX DQ/DQS(Engine): PASS
3700 13:22:02.756333 TX OE : NO K
3701 13:22:02.759922 All Pass.
3702 13:22:02.760000
3703 13:22:02.760062 CH 1, Rank 0
3704 13:22:02.762647 SW Impedance : PASS
3705 13:22:02.762757 DUTY Scan : NO K
3706 13:22:02.766448 ZQ Calibration : PASS
3707 13:22:02.769814 Jitter Meter : NO K
3708 13:22:02.769981 CBT Training : PASS
3709 13:22:02.772669 Write leveling : PASS
3710 13:22:02.775825 RX DQS gating : PASS
3711 13:22:02.775903 RX DQ/DQS(RDDQC) : PASS
3712 13:22:02.779516 TX DQ/DQS : PASS
3713 13:22:02.779634 RX DATLAT : PASS
3714 13:22:02.782917 RX DQ/DQS(Engine): PASS
3715 13:22:02.785887 TX OE : NO K
3716 13:22:02.785985 All Pass.
3717 13:22:02.786082
3718 13:22:02.786176 CH 1, Rank 1
3719 13:22:02.789515 SW Impedance : PASS
3720 13:22:02.792598 DUTY Scan : NO K
3721 13:22:02.792672 ZQ Calibration : PASS
3722 13:22:02.796019 Jitter Meter : NO K
3723 13:22:02.799094 CBT Training : PASS
3724 13:22:02.799224 Write leveling : PASS
3725 13:22:02.802838 RX DQS gating : PASS
3726 13:22:02.805848 RX DQ/DQS(RDDQC) : PASS
3727 13:22:02.805998 TX DQ/DQS : PASS
3728 13:22:02.809782 RX DATLAT : PASS
3729 13:22:02.812342 RX DQ/DQS(Engine): PASS
3730 13:22:02.812419 TX OE : NO K
3731 13:22:02.816136 All Pass.
3732 13:22:02.816212
3733 13:22:02.816281 DramC Write-DBI off
3734 13:22:02.819136 PER_BANK_REFRESH: Hybrid Mode
3735 13:22:02.819237 TX_TRACKING: ON
3736 13:22:02.829144 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3737 13:22:02.832203 [FAST_K] Save calibration result to emmc
3738 13:22:02.835885 dramc_set_vcore_voltage set vcore to 650000
3739 13:22:02.838829 Read voltage for 600, 5
3740 13:22:02.838949 Vio18 = 0
3741 13:22:02.842416 Vcore = 650000
3742 13:22:02.842532 Vdram = 0
3743 13:22:02.842617 Vddq = 0
3744 13:22:02.845402 Vmddr = 0
3745 13:22:02.848883 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3746 13:22:02.855530 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3747 13:22:02.855708 MEM_TYPE=3, freq_sel=19
3748 13:22:02.859073 sv_algorithm_assistance_LP4_1600
3749 13:22:02.861956 ============ PULL DRAM RESETB DOWN ============
3750 13:22:02.869062 ========== PULL DRAM RESETB DOWN end =========
3751 13:22:02.872248 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3752 13:22:02.875871 ===================================
3753 13:22:02.878902 LPDDR4 DRAM CONFIGURATION
3754 13:22:02.882438 ===================================
3755 13:22:02.882592 EX_ROW_EN[0] = 0x0
3756 13:22:02.885507 EX_ROW_EN[1] = 0x0
3757 13:22:02.888961 LP4Y_EN = 0x0
3758 13:22:02.889119 WORK_FSP = 0x0
3759 13:22:02.892175 WL = 0x2
3760 13:22:02.892321 RL = 0x2
3761 13:22:02.895598 BL = 0x2
3762 13:22:02.895727 RPST = 0x0
3763 13:22:02.898473 RD_PRE = 0x0
3764 13:22:02.898585 WR_PRE = 0x1
3765 13:22:02.902620 WR_PST = 0x0
3766 13:22:02.902749 DBI_WR = 0x0
3767 13:22:02.905381 DBI_RD = 0x0
3768 13:22:02.905489 OTF = 0x1
3769 13:22:02.909012 ===================================
3770 13:22:02.912041 ===================================
3771 13:22:02.915776 ANA top config
3772 13:22:02.918859 ===================================
3773 13:22:02.918975 DLL_ASYNC_EN = 0
3774 13:22:02.922186 ALL_SLAVE_EN = 1
3775 13:22:02.925216 NEW_RANK_MODE = 1
3776 13:22:02.928938 DLL_IDLE_MODE = 1
3777 13:22:02.929044 LP45_APHY_COMB_EN = 1
3778 13:22:02.932231 TX_ODT_DIS = 1
3779 13:22:02.935677 NEW_8X_MODE = 1
3780 13:22:02.938487 ===================================
3781 13:22:02.942233 ===================================
3782 13:22:02.945133 data_rate = 1200
3783 13:22:02.948686 CKR = 1
3784 13:22:02.951852 DQ_P2S_RATIO = 8
3785 13:22:02.955305 ===================================
3786 13:22:02.955392 CA_P2S_RATIO = 8
3787 13:22:02.958863 DQ_CA_OPEN = 0
3788 13:22:02.961880 DQ_SEMI_OPEN = 0
3789 13:22:02.965463 CA_SEMI_OPEN = 0
3790 13:22:02.968190 CA_FULL_RATE = 0
3791 13:22:02.971556 DQ_CKDIV4_EN = 1
3792 13:22:02.971639 CA_CKDIV4_EN = 1
3793 13:22:02.974862 CA_PREDIV_EN = 0
3794 13:22:02.978402 PH8_DLY = 0
3795 13:22:02.981537 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3796 13:22:02.984821 DQ_AAMCK_DIV = 4
3797 13:22:02.988240 CA_AAMCK_DIV = 4
3798 13:22:02.988325 CA_ADMCK_DIV = 4
3799 13:22:02.991702 DQ_TRACK_CA_EN = 0
3800 13:22:02.995052 CA_PICK = 600
3801 13:22:02.998327 CA_MCKIO = 600
3802 13:22:03.001392 MCKIO_SEMI = 0
3803 13:22:03.005166 PLL_FREQ = 2288
3804 13:22:03.008367 DQ_UI_PI_RATIO = 32
3805 13:22:03.008478 CA_UI_PI_RATIO = 0
3806 13:22:03.011758 ===================================
3807 13:22:03.014854 ===================================
3808 13:22:03.018081 memory_type:LPDDR4
3809 13:22:03.021711 GP_NUM : 10
3810 13:22:03.021836 SRAM_EN : 1
3811 13:22:03.024751 MD32_EN : 0
3812 13:22:03.028273 ===================================
3813 13:22:03.031189 [ANA_INIT] >>>>>>>>>>>>>>
3814 13:22:03.034608 <<<<<< [CONFIGURE PHASE]: ANA_TX
3815 13:22:03.038464 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3816 13:22:03.041224 ===================================
3817 13:22:03.041344 data_rate = 1200,PCW = 0X5800
3818 13:22:03.044880 ===================================
3819 13:22:03.047936 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3820 13:22:03.054772 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3821 13:22:03.061291 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3822 13:22:03.064776 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3823 13:22:03.068561 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3824 13:22:03.071495 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3825 13:22:03.075030 [ANA_INIT] flow start
3826 13:22:03.075144 [ANA_INIT] PLL >>>>>>>>
3827 13:22:03.078308 [ANA_INIT] PLL <<<<<<<<
3828 13:22:03.081324 [ANA_INIT] MIDPI >>>>>>>>
3829 13:22:03.084899 [ANA_INIT] MIDPI <<<<<<<<
3830 13:22:03.084981 [ANA_INIT] DLL >>>>>>>>
3831 13:22:03.088125 [ANA_INIT] flow end
3832 13:22:03.091259 ============ LP4 DIFF to SE enter ============
3833 13:22:03.094859 ============ LP4 DIFF to SE exit ============
3834 13:22:03.098053 [ANA_INIT] <<<<<<<<<<<<<
3835 13:22:03.101168 [Flow] Enable top DCM control >>>>>
3836 13:22:03.104732 [Flow] Enable top DCM control <<<<<
3837 13:22:03.107917 Enable DLL master slave shuffle
3838 13:22:03.114624 ==============================================================
3839 13:22:03.114741 Gating Mode config
3840 13:22:03.121388 ==============================================================
3841 13:22:03.121476 Config description:
3842 13:22:03.130943 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3843 13:22:03.137663 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3844 13:22:03.144237 SELPH_MODE 0: By rank 1: By Phase
3845 13:22:03.147628 ==============================================================
3846 13:22:03.151102 GAT_TRACK_EN = 1
3847 13:22:03.154157 RX_GATING_MODE = 2
3848 13:22:03.157892 RX_GATING_TRACK_MODE = 2
3849 13:22:03.160703 SELPH_MODE = 1
3850 13:22:03.164316 PICG_EARLY_EN = 1
3851 13:22:03.168021 VALID_LAT_VALUE = 1
3852 13:22:03.171108 ==============================================================
3853 13:22:03.174631 Enter into Gating configuration >>>>
3854 13:22:03.178023 Exit from Gating configuration <<<<
3855 13:22:03.181163 Enter into DVFS_PRE_config >>>>>
3856 13:22:03.194116 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3857 13:22:03.197423 Exit from DVFS_PRE_config <<<<<
3858 13:22:03.201062 Enter into PICG configuration >>>>
3859 13:22:03.204246 Exit from PICG configuration <<<<
3860 13:22:03.204344 [RX_INPUT] configuration >>>>>
3861 13:22:03.207680 [RX_INPUT] configuration <<<<<
3862 13:22:03.214247 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3863 13:22:03.217414 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3864 13:22:03.224292 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3865 13:22:03.230787 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3866 13:22:03.237334 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3867 13:22:03.243913 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3868 13:22:03.247127 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3869 13:22:03.250699 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3870 13:22:03.257354 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3871 13:22:03.260806 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3872 13:22:03.263799 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3873 13:22:03.267324 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3874 13:22:03.270517 ===================================
3875 13:22:03.273840 LPDDR4 DRAM CONFIGURATION
3876 13:22:03.276807 ===================================
3877 13:22:03.280463 EX_ROW_EN[0] = 0x0
3878 13:22:03.280565 EX_ROW_EN[1] = 0x0
3879 13:22:03.283870 LP4Y_EN = 0x0
3880 13:22:03.283944 WORK_FSP = 0x0
3881 13:22:03.287198 WL = 0x2
3882 13:22:03.287297 RL = 0x2
3883 13:22:03.290283 BL = 0x2
3884 13:22:03.290382 RPST = 0x0
3885 13:22:03.293818 RD_PRE = 0x0
3886 13:22:03.293893 WR_PRE = 0x1
3887 13:22:03.296722 WR_PST = 0x0
3888 13:22:03.300287 DBI_WR = 0x0
3889 13:22:03.300364 DBI_RD = 0x0
3890 13:22:03.303239 OTF = 0x1
3891 13:22:03.306872 ===================================
3892 13:22:03.310303 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3893 13:22:03.313480 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3894 13:22:03.316981 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3895 13:22:03.319966 ===================================
3896 13:22:03.323273 LPDDR4 DRAM CONFIGURATION
3897 13:22:03.326432 ===================================
3898 13:22:03.330114 EX_ROW_EN[0] = 0x10
3899 13:22:03.330231 EX_ROW_EN[1] = 0x0
3900 13:22:03.333158 LP4Y_EN = 0x0
3901 13:22:03.333292 WORK_FSP = 0x0
3902 13:22:03.336834 WL = 0x2
3903 13:22:03.336948 RL = 0x2
3904 13:22:03.339601 BL = 0x2
3905 13:22:03.339716 RPST = 0x0
3906 13:22:03.343304 RD_PRE = 0x0
3907 13:22:03.343451 WR_PRE = 0x1
3908 13:22:03.346381 WR_PST = 0x0
3909 13:22:03.349863 DBI_WR = 0x0
3910 13:22:03.349966 DBI_RD = 0x0
3911 13:22:03.353361 OTF = 0x1
3912 13:22:03.356371 ===================================
3913 13:22:03.359898 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3914 13:22:03.365081 nWR fixed to 30
3915 13:22:03.368499 [ModeRegInit_LP4] CH0 RK0
3916 13:22:03.368588 [ModeRegInit_LP4] CH0 RK1
3917 13:22:03.371585 [ModeRegInit_LP4] CH1 RK0
3918 13:22:03.375187 [ModeRegInit_LP4] CH1 RK1
3919 13:22:03.375292 match AC timing 17
3920 13:22:03.381257 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3921 13:22:03.384568 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3922 13:22:03.388169 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3923 13:22:03.394589 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3924 13:22:03.398006 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3925 13:22:03.398115 ==
3926 13:22:03.401704 Dram Type= 6, Freq= 0, CH_0, rank 0
3927 13:22:03.404698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3928 13:22:03.404771 ==
3929 13:22:03.411241 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3930 13:22:03.418091 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3931 13:22:03.421346 [CA 0] Center 37 (7~67) winsize 61
3932 13:22:03.425072 [CA 1] Center 36 (6~67) winsize 62
3933 13:22:03.427900 [CA 2] Center 35 (5~65) winsize 61
3934 13:22:03.431266 [CA 3] Center 35 (5~65) winsize 61
3935 13:22:03.434431 [CA 4] Center 34 (4~65) winsize 62
3936 13:22:03.437920 [CA 5] Center 34 (4~64) winsize 61
3937 13:22:03.438027
3938 13:22:03.441272 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3939 13:22:03.441377
3940 13:22:03.444763 [CATrainingPosCal] consider 1 rank data
3941 13:22:03.447740 u2DelayCellTimex100 = 270/100 ps
3942 13:22:03.451255 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3943 13:22:03.454452 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
3944 13:22:03.457822 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3945 13:22:03.461461 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3946 13:22:03.464475 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3947 13:22:03.470843 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3948 13:22:03.470948
3949 13:22:03.474162 CA PerBit enable=1, Macro0, CA PI delay=34
3950 13:22:03.474274
3951 13:22:03.477527 [CBTSetCACLKResult] CA Dly = 34
3952 13:22:03.477626 CS Dly: 7 (0~38)
3953 13:22:03.477695 ==
3954 13:22:03.481062 Dram Type= 6, Freq= 0, CH_0, rank 1
3955 13:22:03.484460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3956 13:22:03.487660 ==
3957 13:22:03.490595 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3958 13:22:03.497704 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3959 13:22:03.500871 [CA 0] Center 37 (7~67) winsize 61
3960 13:22:03.503982 [CA 1] Center 37 (7~67) winsize 61
3961 13:22:03.507614 [CA 2] Center 35 (5~65) winsize 61
3962 13:22:03.510895 [CA 3] Center 35 (5~65) winsize 61
3963 13:22:03.514023 [CA 4] Center 34 (4~65) winsize 62
3964 13:22:03.517498 [CA 5] Center 33 (3~64) winsize 62
3965 13:22:03.517572
3966 13:22:03.520457 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3967 13:22:03.520591
3968 13:22:03.523909 [CATrainingPosCal] consider 2 rank data
3969 13:22:03.527267 u2DelayCellTimex100 = 270/100 ps
3970 13:22:03.530666 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3971 13:22:03.533764 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3972 13:22:03.537178 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3973 13:22:03.544073 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3974 13:22:03.547263 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3975 13:22:03.550597 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3976 13:22:03.550694
3977 13:22:03.554096 CA PerBit enable=1, Macro0, CA PI delay=34
3978 13:22:03.554169
3979 13:22:03.557061 [CBTSetCACLKResult] CA Dly = 34
3980 13:22:03.557137 CS Dly: 6 (0~37)
3981 13:22:03.557198
3982 13:22:03.560237 ----->DramcWriteLeveling(PI) begin...
3983 13:22:03.563722 ==
3984 13:22:03.563808 Dram Type= 6, Freq= 0, CH_0, rank 0
3985 13:22:03.570426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3986 13:22:03.570503 ==
3987 13:22:03.573945 Write leveling (Byte 0): 32 => 32
3988 13:22:03.577046 Write leveling (Byte 1): 32 => 32
3989 13:22:03.580665 DramcWriteLeveling(PI) end<-----
3990 13:22:03.580751
3991 13:22:03.580836 ==
3992 13:22:03.583528 Dram Type= 6, Freq= 0, CH_0, rank 0
3993 13:22:03.586962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3994 13:22:03.587063 ==
3995 13:22:03.590446 [Gating] SW mode calibration
3996 13:22:03.597113 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3997 13:22:03.600151 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3998 13:22:03.606740 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3999 13:22:03.610335 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4000 13:22:03.613701 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4001 13:22:03.620054 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
4002 13:22:03.623651 0 9 16 | B1->B0 | 3131 2929 | 0 0 | (0 0) (0 0)
4003 13:22:03.626627 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4004 13:22:03.633642 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 13:22:03.636817 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 13:22:03.640250 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4007 13:22:03.646564 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 13:22:03.650210 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 13:22:03.653060 0 10 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4010 13:22:03.659729 0 10 16 | B1->B0 | 3232 3c3c | 0 0 | (1 1) (0 0)
4011 13:22:03.663258 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 13:22:03.666325 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 13:22:03.673408 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 13:22:03.676292 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 13:22:03.680059 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 13:22:03.686623 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 13:22:03.689685 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 13:22:03.693369 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4019 13:22:03.699321 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 13:22:03.702996 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 13:22:03.706623 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 13:22:03.712630 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 13:22:03.716029 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 13:22:03.719619 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 13:22:03.725829 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 13:22:03.729139 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 13:22:03.732700 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 13:22:03.739272 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 13:22:03.742556 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 13:22:03.745923 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 13:22:03.752287 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 13:22:03.755489 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 13:22:03.759243 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4034 13:22:03.765477 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4035 13:22:03.769307 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 13:22:03.772262 Total UI for P1: 0, mck2ui 16
4037 13:22:03.775911 best dqsien dly found for B0: ( 0, 13, 14)
4038 13:22:03.778837 Total UI for P1: 0, mck2ui 16
4039 13:22:03.782063 best dqsien dly found for B1: ( 0, 13, 18)
4040 13:22:03.785579 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4041 13:22:03.788582 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4042 13:22:03.788682
4043 13:22:03.792010 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4044 13:22:03.795526 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4045 13:22:03.798768 [Gating] SW calibration Done
4046 13:22:03.798861 ==
4047 13:22:03.801905 Dram Type= 6, Freq= 0, CH_0, rank 0
4048 13:22:03.805045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4049 13:22:03.808422 ==
4050 13:22:03.808503 RX Vref Scan: 0
4051 13:22:03.808575
4052 13:22:03.812118 RX Vref 0 -> 0, step: 1
4053 13:22:03.812197
4054 13:22:03.815047 RX Delay -230 -> 252, step: 16
4055 13:22:03.818536 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4056 13:22:03.821677 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4057 13:22:03.825291 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4058 13:22:03.831989 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4059 13:22:03.835128 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4060 13:22:03.838439 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4061 13:22:03.841480 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4062 13:22:03.845177 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4063 13:22:03.851615 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4064 13:22:03.854807 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4065 13:22:03.858054 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4066 13:22:03.861517 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4067 13:22:03.867884 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4068 13:22:03.871269 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4069 13:22:03.874783 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4070 13:22:03.878401 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4071 13:22:03.878486 ==
4072 13:22:03.881412 Dram Type= 6, Freq= 0, CH_0, rank 0
4073 13:22:03.887876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4074 13:22:03.887967 ==
4075 13:22:03.888034 DQS Delay:
4076 13:22:03.891441 DQS0 = 0, DQS1 = 0
4077 13:22:03.891547 DQM Delay:
4078 13:22:03.894945 DQM0 = 38, DQM1 = 30
4079 13:22:03.895023 DQ Delay:
4080 13:22:03.898254 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4081 13:22:03.901455 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4082 13:22:03.904806 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4083 13:22:03.908006 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4084 13:22:03.908091
4085 13:22:03.908156
4086 13:22:03.908226 ==
4087 13:22:03.911094 Dram Type= 6, Freq= 0, CH_0, rank 0
4088 13:22:03.914794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4089 13:22:03.914900 ==
4090 13:22:03.914992
4091 13:22:03.915085
4092 13:22:03.918320 TX Vref Scan disable
4093 13:22:03.921219 == TX Byte 0 ==
4094 13:22:03.924704 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4095 13:22:03.927676 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4096 13:22:03.931277 == TX Byte 1 ==
4097 13:22:03.934356 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4098 13:22:03.937850 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4099 13:22:03.937958 ==
4100 13:22:03.941318 Dram Type= 6, Freq= 0, CH_0, rank 0
4101 13:22:03.944926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4102 13:22:03.947911 ==
4103 13:22:03.948027
4104 13:22:03.948119
4105 13:22:03.948213 TX Vref Scan disable
4106 13:22:03.951572 == TX Byte 0 ==
4107 13:22:03.955066 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4108 13:22:03.961323 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4109 13:22:03.961416 == TX Byte 1 ==
4110 13:22:03.964538 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4111 13:22:03.971667 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4112 13:22:03.971759
4113 13:22:03.971837 [DATLAT]
4114 13:22:03.971899 Freq=600, CH0 RK0
4115 13:22:03.971964
4116 13:22:03.974995 DATLAT Default: 0x9
4117 13:22:03.975105 0, 0xFFFF, sum = 0
4118 13:22:03.978859 1, 0xFFFF, sum = 0
4119 13:22:03.978962 2, 0xFFFF, sum = 0
4120 13:22:03.981559 3, 0xFFFF, sum = 0
4121 13:22:03.984902 4, 0xFFFF, sum = 0
4122 13:22:03.985017 5, 0xFFFF, sum = 0
4123 13:22:03.988644 6, 0xFFFF, sum = 0
4124 13:22:03.988759 7, 0xFFFF, sum = 0
4125 13:22:03.991604 8, 0x0, sum = 1
4126 13:22:03.991708 9, 0x0, sum = 2
4127 13:22:03.991814 10, 0x0, sum = 3
4128 13:22:03.994648 11, 0x0, sum = 4
4129 13:22:03.994755 best_step = 9
4130 13:22:03.994847
4131 13:22:03.994935 ==
4132 13:22:03.998472 Dram Type= 6, Freq= 0, CH_0, rank 0
4133 13:22:04.004535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 13:22:04.004641 ==
4135 13:22:04.004739 RX Vref Scan: 1
4136 13:22:04.004830
4137 13:22:04.008302 RX Vref 0 -> 0, step: 1
4138 13:22:04.008415
4139 13:22:04.011540 RX Delay -195 -> 252, step: 8
4140 13:22:04.011616
4141 13:22:04.014888 Set Vref, RX VrefLevel [Byte0]: 61
4142 13:22:04.017922 [Byte1]: 54
4143 13:22:04.017999
4144 13:22:04.021679 Final RX Vref Byte 0 = 61 to rank0
4145 13:22:04.024986 Final RX Vref Byte 1 = 54 to rank0
4146 13:22:04.027826 Final RX Vref Byte 0 = 61 to rank1
4147 13:22:04.031178 Final RX Vref Byte 1 = 54 to rank1==
4148 13:22:04.035026 Dram Type= 6, Freq= 0, CH_0, rank 0
4149 13:22:04.038319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4150 13:22:04.038401 ==
4151 13:22:04.041553 DQS Delay:
4152 13:22:04.041628 DQS0 = 0, DQS1 = 0
4153 13:22:04.041692 DQM Delay:
4154 13:22:04.044541 DQM0 = 34, DQM1 = 29
4155 13:22:04.044618 DQ Delay:
4156 13:22:04.048156 DQ0 =36, DQ1 =36, DQ2 =32, DQ3 =32
4157 13:22:04.051261 DQ4 =32, DQ5 =20, DQ6 =40, DQ7 =48
4158 13:22:04.054711 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4159 13:22:04.057748 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =36
4160 13:22:04.057849
4161 13:22:04.057941
4162 13:22:04.068273 [DQSOSCAuto] RK0, (LSB)MR18= 0x4544, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
4163 13:22:04.071242 CH0 RK0: MR19=808, MR18=4544
4164 13:22:04.074425 CH0_RK0: MR19=0x808, MR18=0x4544, DQSOSC=396, MR23=63, INC=167, DEC=111
4165 13:22:04.074505
4166 13:22:04.081161 ----->DramcWriteLeveling(PI) begin...
4167 13:22:04.081266 ==
4168 13:22:04.084628 Dram Type= 6, Freq= 0, CH_0, rank 1
4169 13:22:04.087637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4170 13:22:04.087743 ==
4171 13:22:04.091505 Write leveling (Byte 0): 31 => 31
4172 13:22:04.094477 Write leveling (Byte 1): 30 => 30
4173 13:22:04.097800 DramcWriteLeveling(PI) end<-----
4174 13:22:04.097899
4175 13:22:04.097965 ==
4176 13:22:04.101343 Dram Type= 6, Freq= 0, CH_0, rank 1
4177 13:22:04.104653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4178 13:22:04.104731 ==
4179 13:22:04.107848 [Gating] SW mode calibration
4180 13:22:04.114761 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4181 13:22:04.121228 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4182 13:22:04.124196 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4183 13:22:04.127573 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4184 13:22:04.134497 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4185 13:22:04.137607 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
4186 13:22:04.141139 0 9 16 | B1->B0 | 2f2f 2424 | 1 0 | (1 1) (0 0)
4187 13:22:04.144400 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 13:22:04.150833 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 13:22:04.154525 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4190 13:22:04.157552 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4191 13:22:04.163883 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4192 13:22:04.167599 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4193 13:22:04.170465 0 10 12 | B1->B0 | 2a2a 3434 | 1 0 | (0 0) (0 0)
4194 13:22:04.177232 0 10 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4195 13:22:04.180537 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 13:22:04.183653 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 13:22:04.190269 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 13:22:04.193785 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 13:22:04.197331 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 13:22:04.203722 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 13:22:04.207059 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4202 13:22:04.210589 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 13:22:04.217137 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 13:22:04.220245 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 13:22:04.223365 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 13:22:04.230383 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 13:22:04.233977 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 13:22:04.236682 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 13:22:04.244006 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 13:22:04.246688 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 13:22:04.250118 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 13:22:04.256908 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 13:22:04.260306 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 13:22:04.263523 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 13:22:04.270068 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 13:22:04.273597 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 13:22:04.277345 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4218 13:22:04.283821 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4219 13:22:04.283900 Total UI for P1: 0, mck2ui 16
4220 13:22:04.290180 best dqsien dly found for B0: ( 0, 13, 12)
4221 13:22:04.290284 Total UI for P1: 0, mck2ui 16
4222 13:22:04.293693 best dqsien dly found for B1: ( 0, 13, 14)
4223 13:22:04.300025 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4224 13:22:04.303326 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4225 13:22:04.303498
4226 13:22:04.306629 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4227 13:22:04.310418 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4228 13:22:04.313646 [Gating] SW calibration Done
4229 13:22:04.313735 ==
4230 13:22:04.316609 Dram Type= 6, Freq= 0, CH_0, rank 1
4231 13:22:04.320034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4232 13:22:04.320109 ==
4233 13:22:04.323498 RX Vref Scan: 0
4234 13:22:04.323598
4235 13:22:04.323674 RX Vref 0 -> 0, step: 1
4236 13:22:04.323734
4237 13:22:04.326758 RX Delay -230 -> 252, step: 16
4238 13:22:04.330347 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4239 13:22:04.336730 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4240 13:22:04.340309 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4241 13:22:04.343840 iDelay=218, Bit 3, Center 25 (-150 ~ 201) 352
4242 13:22:04.346959 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4243 13:22:04.353261 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4244 13:22:04.356928 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4245 13:22:04.359839 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4246 13:22:04.363502 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4247 13:22:04.366726 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4248 13:22:04.373330 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4249 13:22:04.377054 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4250 13:22:04.379853 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4251 13:22:04.384444 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4252 13:22:04.389520 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4253 13:22:04.392974 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4254 13:22:04.393060 ==
4255 13:22:04.396090 Dram Type= 6, Freq= 0, CH_0, rank 1
4256 13:22:04.399661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4257 13:22:04.399768 ==
4258 13:22:04.402615 DQS Delay:
4259 13:22:04.402769 DQS0 = 0, DQS1 = 0
4260 13:22:04.406121 DQM Delay:
4261 13:22:04.406279 DQM0 = 38, DQM1 = 29
4262 13:22:04.406376 DQ Delay:
4263 13:22:04.409294 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =25
4264 13:22:04.412597 DQ4 =41, DQ5 =17, DQ6 =49, DQ7 =49
4265 13:22:04.416020 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4266 13:22:04.419443 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =41
4267 13:22:04.419525
4268 13:22:04.419590
4269 13:22:04.422562 ==
4270 13:22:04.422645 Dram Type= 6, Freq= 0, CH_0, rank 1
4271 13:22:04.429058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4272 13:22:04.429138 ==
4273 13:22:04.429223
4274 13:22:04.429290
4275 13:22:04.432437 TX Vref Scan disable
4276 13:22:04.432512 == TX Byte 0 ==
4277 13:22:04.439236 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4278 13:22:04.442239 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4279 13:22:04.442317 == TX Byte 1 ==
4280 13:22:04.449196 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4281 13:22:04.452042 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4282 13:22:04.452123 ==
4283 13:22:04.455702 Dram Type= 6, Freq= 0, CH_0, rank 1
4284 13:22:04.459090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4285 13:22:04.459201 ==
4286 13:22:04.459292
4287 13:22:04.459430
4288 13:22:04.461992 TX Vref Scan disable
4289 13:22:04.465467 == TX Byte 0 ==
4290 13:22:04.468663 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4291 13:22:04.472307 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4292 13:22:04.475285 == TX Byte 1 ==
4293 13:22:04.478640 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4294 13:22:04.482586 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4295 13:22:04.482666
4296 13:22:04.485612 [DATLAT]
4297 13:22:04.485704 Freq=600, CH0 RK1
4298 13:22:04.485781
4299 13:22:04.489025 DATLAT Default: 0x9
4300 13:22:04.489108 0, 0xFFFF, sum = 0
4301 13:22:04.491967 1, 0xFFFF, sum = 0
4302 13:22:04.492051 2, 0xFFFF, sum = 0
4303 13:22:04.495177 3, 0xFFFF, sum = 0
4304 13:22:04.495284 4, 0xFFFF, sum = 0
4305 13:22:04.498663 5, 0xFFFF, sum = 0
4306 13:22:04.498770 6, 0xFFFF, sum = 0
4307 13:22:04.501755 7, 0xFFFF, sum = 0
4308 13:22:04.501873 8, 0x0, sum = 1
4309 13:22:04.505277 9, 0x0, sum = 2
4310 13:22:04.505378 10, 0x0, sum = 3
4311 13:22:04.508610 11, 0x0, sum = 4
4312 13:22:04.508699 best_step = 9
4313 13:22:04.508767
4314 13:22:04.508832 ==
4315 13:22:04.511706 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 13:22:04.518443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 13:22:04.518560 ==
4318 13:22:04.518659 RX Vref Scan: 0
4319 13:22:04.518754
4320 13:22:04.522047 RX Vref 0 -> 0, step: 1
4321 13:22:04.522160
4322 13:22:04.524881 RX Delay -195 -> 252, step: 8
4323 13:22:04.528073 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4324 13:22:04.534746 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4325 13:22:04.538592 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4326 13:22:04.541605 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4327 13:22:04.544813 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4328 13:22:04.551600 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4329 13:22:04.554550 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4330 13:22:04.558260 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4331 13:22:04.561182 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4332 13:22:04.564452 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4333 13:22:04.571194 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4334 13:22:04.574704 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4335 13:22:04.577771 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4336 13:22:04.581328 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4337 13:22:04.587913 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4338 13:22:04.591395 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4339 13:22:04.591517 ==
4340 13:22:04.594703 Dram Type= 6, Freq= 0, CH_0, rank 1
4341 13:22:04.597653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 13:22:04.597728 ==
4343 13:22:04.600849 DQS Delay:
4344 13:22:04.600957 DQS0 = 0, DQS1 = 0
4345 13:22:04.601022 DQM Delay:
4346 13:22:04.604450 DQM0 = 34, DQM1 = 27
4347 13:22:04.604523 DQ Delay:
4348 13:22:04.607879 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4349 13:22:04.610845 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4350 13:22:04.614597 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4351 13:22:04.617990 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =36
4352 13:22:04.618076
4353 13:22:04.618140
4354 13:22:04.627276 [DQSOSCAuto] RK1, (LSB)MR18= 0x6e3c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4355 13:22:04.630995 CH0 RK1: MR19=808, MR18=6E3C
4356 13:22:04.633976 CH0_RK1: MR19=0x808, MR18=0x6E3C, DQSOSC=389, MR23=63, INC=173, DEC=115
4357 13:22:04.637435 [RxdqsGatingPostProcess] freq 600
4358 13:22:04.644231 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4359 13:22:04.647126 Pre-setting of DQS Precalculation
4360 13:22:04.650637 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4361 13:22:04.650716 ==
4362 13:22:04.653791 Dram Type= 6, Freq= 0, CH_1, rank 0
4363 13:22:04.660609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4364 13:22:04.660690 ==
4365 13:22:04.663724 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4366 13:22:04.670325 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4367 13:22:04.674429 [CA 0] Center 35 (5~66) winsize 62
4368 13:22:04.677109 [CA 1] Center 35 (5~66) winsize 62
4369 13:22:04.680603 [CA 2] Center 34 (4~65) winsize 62
4370 13:22:04.684233 [CA 3] Center 34 (3~65) winsize 63
4371 13:22:04.687125 [CA 4] Center 34 (4~65) winsize 62
4372 13:22:04.690682 [CA 5] Center 33 (3~64) winsize 62
4373 13:22:04.690786
4374 13:22:04.693790 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4375 13:22:04.693900
4376 13:22:04.697337 [CATrainingPosCal] consider 1 rank data
4377 13:22:04.700282 u2DelayCellTimex100 = 270/100 ps
4378 13:22:04.706927 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4379 13:22:04.710150 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4380 13:22:04.713590 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4381 13:22:04.716679 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4382 13:22:04.720152 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4383 13:22:04.723552 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4384 13:22:04.723638
4385 13:22:04.726554 CA PerBit enable=1, Macro0, CA PI delay=33
4386 13:22:04.726656
4387 13:22:04.730312 [CBTSetCACLKResult] CA Dly = 33
4388 13:22:04.733659 CS Dly: 4 (0~35)
4389 13:22:04.733759 ==
4390 13:22:04.736664 Dram Type= 6, Freq= 0, CH_1, rank 1
4391 13:22:04.740317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4392 13:22:04.740425 ==
4393 13:22:04.746848 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4394 13:22:04.749793 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4395 13:22:04.754468 [CA 0] Center 36 (6~66) winsize 61
4396 13:22:04.757597 [CA 1] Center 36 (6~66) winsize 61
4397 13:22:04.760623 [CA 2] Center 34 (4~65) winsize 62
4398 13:22:04.764062 [CA 3] Center 34 (3~65) winsize 63
4399 13:22:04.767678 [CA 4] Center 34 (4~65) winsize 62
4400 13:22:04.770522 [CA 5] Center 33 (3~64) winsize 62
4401 13:22:04.770615
4402 13:22:04.774569 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4403 13:22:04.774656
4404 13:22:04.777524 [CATrainingPosCal] consider 2 rank data
4405 13:22:04.780664 u2DelayCellTimex100 = 270/100 ps
4406 13:22:04.784008 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4407 13:22:04.787337 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4408 13:22:04.794191 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4409 13:22:04.797348 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4410 13:22:04.800508 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4411 13:22:04.804169 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4412 13:22:04.804245
4413 13:22:04.807236 CA PerBit enable=1, Macro0, CA PI delay=33
4414 13:22:04.807355
4415 13:22:04.810892 [CBTSetCACLKResult] CA Dly = 33
4416 13:22:04.811028 CS Dly: 4 (0~36)
4417 13:22:04.811119
4418 13:22:04.813792 ----->DramcWriteLeveling(PI) begin...
4419 13:22:04.817295 ==
4420 13:22:04.820966 Dram Type= 6, Freq= 0, CH_1, rank 0
4421 13:22:04.823741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4422 13:22:04.823827 ==
4423 13:22:04.827358 Write leveling (Byte 0): 28 => 28
4424 13:22:04.830515 Write leveling (Byte 1): 29 => 29
4425 13:22:04.834035 DramcWriteLeveling(PI) end<-----
4426 13:22:04.834152
4427 13:22:04.834250 ==
4428 13:22:04.837623 Dram Type= 6, Freq= 0, CH_1, rank 0
4429 13:22:04.840518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4430 13:22:04.840629 ==
4431 13:22:04.843547 [Gating] SW mode calibration
4432 13:22:04.850091 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4433 13:22:04.856801 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4434 13:22:04.860406 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4435 13:22:04.863724 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4436 13:22:04.870652 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4437 13:22:04.873651 0 9 12 | B1->B0 | 3131 3030 | 0 0 | (0 1) (0 1)
4438 13:22:04.877116 0 9 16 | B1->B0 | 2525 2424 | 0 0 | (1 1) (0 0)
4439 13:22:04.883715 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4440 13:22:04.887107 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 13:22:04.890106 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4442 13:22:04.893889 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4443 13:22:04.900471 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4444 13:22:04.903201 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4445 13:22:04.907188 0 10 12 | B1->B0 | 2f2f 302f | 0 1 | (0 0) (0 0)
4446 13:22:04.913696 0 10 16 | B1->B0 | 4646 4343 | 0 0 | (0 0) (1 1)
4447 13:22:04.916905 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 13:22:04.920455 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 13:22:04.927015 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 13:22:04.930046 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 13:22:04.934113 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 13:22:04.940332 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 13:22:04.943771 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4454 13:22:04.947001 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 13:22:04.953196 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 13:22:04.956808 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 13:22:04.960131 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 13:22:04.966495 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 13:22:04.969829 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 13:22:04.973126 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 13:22:04.979937 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 13:22:04.983066 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 13:22:04.986562 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 13:22:04.992962 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 13:22:04.996623 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 13:22:04.999732 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 13:22:05.006192 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 13:22:05.009848 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 13:22:05.013248 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4470 13:22:05.019510 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4471 13:22:05.019601 Total UI for P1: 0, mck2ui 16
4472 13:22:05.026228 best dqsien dly found for B0: ( 0, 13, 12)
4473 13:22:05.029789 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 13:22:05.032739 Total UI for P1: 0, mck2ui 16
4475 13:22:05.036328 best dqsien dly found for B1: ( 0, 13, 16)
4476 13:22:05.039831 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4477 13:22:05.042689 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4478 13:22:05.042802
4479 13:22:05.046352 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4480 13:22:05.049688 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4481 13:22:05.053113 [Gating] SW calibration Done
4482 13:22:05.053217 ==
4483 13:22:05.056119 Dram Type= 6, Freq= 0, CH_1, rank 0
4484 13:22:05.059686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4485 13:22:05.059765 ==
4486 13:22:05.062811 RX Vref Scan: 0
4487 13:22:05.062884
4488 13:22:05.065896 RX Vref 0 -> 0, step: 1
4489 13:22:05.065981
4490 13:22:05.066054 RX Delay -230 -> 252, step: 16
4491 13:22:05.073225 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4492 13:22:05.076081 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4493 13:22:05.079259 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4494 13:22:05.082655 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4495 13:22:05.089294 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4496 13:22:05.092653 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4497 13:22:05.096250 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4498 13:22:05.099241 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4499 13:22:05.105889 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4500 13:22:05.109077 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4501 13:22:05.112615 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4502 13:22:05.116090 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4503 13:22:05.122526 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4504 13:22:05.125331 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4505 13:22:05.128997 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4506 13:22:05.132172 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4507 13:22:05.132279 ==
4508 13:22:05.135719 Dram Type= 6, Freq= 0, CH_1, rank 0
4509 13:22:05.141996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4510 13:22:05.142112 ==
4511 13:22:05.142209 DQS Delay:
4512 13:22:05.145560 DQS0 = 0, DQS1 = 0
4513 13:22:05.145668 DQM Delay:
4514 13:22:05.145762 DQM0 = 37, DQM1 = 29
4515 13:22:05.148604 DQ Delay:
4516 13:22:05.152210 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4517 13:22:05.155551 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4518 13:22:05.158615 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4519 13:22:05.162224 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4520 13:22:05.162332
4521 13:22:05.162427
4522 13:22:05.162515 ==
4523 13:22:05.165325 Dram Type= 6, Freq= 0, CH_1, rank 0
4524 13:22:05.169080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4525 13:22:05.169190 ==
4526 13:22:05.169284
4527 13:22:05.169375
4528 13:22:05.171881 TX Vref Scan disable
4529 13:22:05.171980 == TX Byte 0 ==
4530 13:22:05.178646 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4531 13:22:05.182326 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4532 13:22:05.182429 == TX Byte 1 ==
4533 13:22:05.188560 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4534 13:22:05.191801 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4535 13:22:05.191877 ==
4536 13:22:05.195171 Dram Type= 6, Freq= 0, CH_1, rank 0
4537 13:22:05.198172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4538 13:22:05.201794 ==
4539 13:22:05.201886
4540 13:22:05.202005
4541 13:22:05.202068 TX Vref Scan disable
4542 13:22:05.205416 == TX Byte 0 ==
4543 13:22:05.208468 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4544 13:22:05.215518 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4545 13:22:05.215612 == TX Byte 1 ==
4546 13:22:05.218457 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4547 13:22:05.225308 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4548 13:22:05.225423
4549 13:22:05.225521 [DATLAT]
4550 13:22:05.225611 Freq=600, CH1 RK0
4551 13:22:05.225703
4552 13:22:05.228460 DATLAT Default: 0x9
4553 13:22:05.228563 0, 0xFFFF, sum = 0
4554 13:22:05.231968 1, 0xFFFF, sum = 0
4555 13:22:05.232048 2, 0xFFFF, sum = 0
4556 13:22:05.235657 3, 0xFFFF, sum = 0
4557 13:22:05.238484 4, 0xFFFF, sum = 0
4558 13:22:05.238594 5, 0xFFFF, sum = 0
4559 13:22:05.241964 6, 0xFFFF, sum = 0
4560 13:22:05.242067 7, 0xFFFF, sum = 0
4561 13:22:05.245712 8, 0x0, sum = 1
4562 13:22:05.245822 9, 0x0, sum = 2
4563 13:22:05.245928 10, 0x0, sum = 3
4564 13:22:05.248658 11, 0x0, sum = 4
4565 13:22:05.248748 best_step = 9
4566 13:22:05.248843
4567 13:22:05.248932 ==
4568 13:22:05.252320 Dram Type= 6, Freq= 0, CH_1, rank 0
4569 13:22:05.258562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 13:22:05.258673 ==
4571 13:22:05.258768 RX Vref Scan: 1
4572 13:22:05.258862
4573 13:22:05.261677 RX Vref 0 -> 0, step: 1
4574 13:22:05.261810
4575 13:22:05.265208 RX Delay -195 -> 252, step: 8
4576 13:22:05.265308
4577 13:22:05.268285 Set Vref, RX VrefLevel [Byte0]: 53
4578 13:22:05.271625 [Byte1]: 49
4579 13:22:05.271708
4580 13:22:05.275151 Final RX Vref Byte 0 = 53 to rank0
4581 13:22:05.278209 Final RX Vref Byte 1 = 49 to rank0
4582 13:22:05.281703 Final RX Vref Byte 0 = 53 to rank1
4583 13:22:05.284893 Final RX Vref Byte 1 = 49 to rank1==
4584 13:22:05.288371 Dram Type= 6, Freq= 0, CH_1, rank 0
4585 13:22:05.291482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4586 13:22:05.291562 ==
4587 13:22:05.294864 DQS Delay:
4588 13:22:05.294967 DQS0 = 0, DQS1 = 0
4589 13:22:05.298312 DQM Delay:
4590 13:22:05.298413 DQM0 = 39, DQM1 = 28
4591 13:22:05.298509 DQ Delay:
4592 13:22:05.301800 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4593 13:22:05.304653 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4594 13:22:05.307979 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4595 13:22:05.311606 DQ12 =40, DQ13 =36, DQ14 =40, DQ15 =36
4596 13:22:05.311712
4597 13:22:05.311805
4598 13:22:05.321339 [DQSOSCAuto] RK0, (LSB)MR18= 0x2633, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 402 ps
4599 13:22:05.324508 CH1 RK0: MR19=808, MR18=2633
4600 13:22:05.331559 CH1_RK0: MR19=0x808, MR18=0x2633, DQSOSC=400, MR23=63, INC=163, DEC=109
4601 13:22:05.331660
4602 13:22:05.334552 ----->DramcWriteLeveling(PI) begin...
4603 13:22:05.334665 ==
4604 13:22:05.338165 Dram Type= 6, Freq= 0, CH_1, rank 1
4605 13:22:05.341569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4606 13:22:05.341680 ==
4607 13:22:05.344533 Write leveling (Byte 0): 30 => 30
4608 13:22:05.347593 Write leveling (Byte 1): 28 => 28
4609 13:22:05.351277 DramcWriteLeveling(PI) end<-----
4610 13:22:05.351359
4611 13:22:05.351463 ==
4612 13:22:05.354772 Dram Type= 6, Freq= 0, CH_1, rank 1
4613 13:22:05.357987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4614 13:22:05.358091 ==
4615 13:22:05.361444 [Gating] SW mode calibration
4616 13:22:05.368047 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4617 13:22:05.374185 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4618 13:22:05.377806 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4619 13:22:05.380810 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4620 13:22:05.387261 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4621 13:22:05.390748 0 9 12 | B1->B0 | 3232 2a2a | 1 1 | (1 0) (1 0)
4622 13:22:05.394040 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4623 13:22:05.400835 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4624 13:22:05.404327 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4625 13:22:05.407109 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4626 13:22:05.414089 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4627 13:22:05.416964 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4628 13:22:05.420310 0 10 8 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
4629 13:22:05.426939 0 10 12 | B1->B0 | 3131 3b3a | 0 1 | (0 0) (1 1)
4630 13:22:05.430904 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 13:22:05.433761 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 13:22:05.440084 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4633 13:22:05.443442 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 13:22:05.447105 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 13:22:05.453674 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 13:22:05.457056 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4637 13:22:05.460360 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4638 13:22:05.467202 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 13:22:05.470185 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 13:22:05.473680 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 13:22:05.480218 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 13:22:05.483442 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 13:22:05.486742 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 13:22:05.493466 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 13:22:05.496976 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 13:22:05.500047 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 13:22:05.506774 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 13:22:05.509948 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 13:22:05.513781 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 13:22:05.520006 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 13:22:05.523401 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 13:22:05.526283 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 13:22:05.530248 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4654 13:22:05.533471 Total UI for P1: 0, mck2ui 16
4655 13:22:05.536730 best dqsien dly found for B0: ( 0, 13, 10)
4656 13:22:05.542859 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4657 13:22:05.546401 Total UI for P1: 0, mck2ui 16
4658 13:22:05.549531 best dqsien dly found for B1: ( 0, 13, 12)
4659 13:22:05.553453 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4660 13:22:05.556489 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4661 13:22:05.556582
4662 13:22:05.559571 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4663 13:22:05.563172 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4664 13:22:05.566623 [Gating] SW calibration Done
4665 13:22:05.566726 ==
4666 13:22:05.569525 Dram Type= 6, Freq= 0, CH_1, rank 1
4667 13:22:05.573146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4668 13:22:05.573252 ==
4669 13:22:05.576145 RX Vref Scan: 0
4670 13:22:05.576245
4671 13:22:05.580055 RX Vref 0 -> 0, step: 1
4672 13:22:05.580133
4673 13:22:05.580199 RX Delay -230 -> 252, step: 16
4674 13:22:05.586304 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4675 13:22:05.589912 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4676 13:22:05.593183 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4677 13:22:05.596565 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4678 13:22:05.603167 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4679 13:22:05.606107 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4680 13:22:05.609697 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4681 13:22:05.612950 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4682 13:22:05.619638 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4683 13:22:05.622742 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4684 13:22:05.626318 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4685 13:22:05.629442 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4686 13:22:05.632648 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4687 13:22:05.639183 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4688 13:22:05.642633 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4689 13:22:05.645993 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4690 13:22:05.646096 ==
4691 13:22:05.649235 Dram Type= 6, Freq= 0, CH_1, rank 1
4692 13:22:05.656126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4693 13:22:05.656209 ==
4694 13:22:05.656275 DQS Delay:
4695 13:22:05.656337 DQS0 = 0, DQS1 = 0
4696 13:22:05.659037 DQM Delay:
4697 13:22:05.659139 DQM0 = 34, DQM1 = 29
4698 13:22:05.662537 DQ Delay:
4699 13:22:05.665807 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4700 13:22:05.668978 DQ4 =33, DQ5 =49, DQ6 =41, DQ7 =33
4701 13:22:05.669100 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4702 13:22:05.675596 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4703 13:22:05.675710
4704 13:22:05.675815
4705 13:22:05.675907 ==
4706 13:22:05.679227 Dram Type= 6, Freq= 0, CH_1, rank 1
4707 13:22:05.682226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4708 13:22:05.682306 ==
4709 13:22:05.682374
4710 13:22:05.682442
4711 13:22:05.685843 TX Vref Scan disable
4712 13:22:05.685915 == TX Byte 0 ==
4713 13:22:05.692300 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4714 13:22:05.696028 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4715 13:22:05.696104 == TX Byte 1 ==
4716 13:22:05.702125 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4717 13:22:05.705722 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4718 13:22:05.705808 ==
4719 13:22:05.709315 Dram Type= 6, Freq= 0, CH_1, rank 1
4720 13:22:05.712177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4721 13:22:05.712287 ==
4722 13:22:05.712374
4723 13:22:05.712437
4724 13:22:05.715657 TX Vref Scan disable
4725 13:22:05.719227 == TX Byte 0 ==
4726 13:22:05.722116 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4727 13:22:05.725651 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4728 13:22:05.729142 == TX Byte 1 ==
4729 13:22:05.732483 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4730 13:22:05.738814 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4731 13:22:05.738924
4732 13:22:05.739018 [DATLAT]
4733 13:22:05.739109 Freq=600, CH1 RK1
4734 13:22:05.739197
4735 13:22:05.742293 DATLAT Default: 0x9
4736 13:22:05.742376 0, 0xFFFF, sum = 0
4737 13:22:05.745469 1, 0xFFFF, sum = 0
4738 13:22:05.745554 2, 0xFFFF, sum = 0
4739 13:22:05.748957 3, 0xFFFF, sum = 0
4740 13:22:05.749041 4, 0xFFFF, sum = 0
4741 13:22:05.752256 5, 0xFFFF, sum = 0
4742 13:22:05.755673 6, 0xFFFF, sum = 0
4743 13:22:05.755758 7, 0xFFFF, sum = 0
4744 13:22:05.755824 8, 0x0, sum = 1
4745 13:22:05.759013 9, 0x0, sum = 2
4746 13:22:05.759098 10, 0x0, sum = 3
4747 13:22:05.762184 11, 0x0, sum = 4
4748 13:22:05.762268 best_step = 9
4749 13:22:05.762333
4750 13:22:05.762393 ==
4751 13:22:05.765241 Dram Type= 6, Freq= 0, CH_1, rank 1
4752 13:22:05.772140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4753 13:22:05.772228 ==
4754 13:22:05.772295 RX Vref Scan: 0
4755 13:22:05.772356
4756 13:22:05.775280 RX Vref 0 -> 0, step: 1
4757 13:22:05.775363
4758 13:22:05.778394 RX Delay -195 -> 252, step: 8
4759 13:22:05.782255 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4760 13:22:05.788873 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4761 13:22:05.791882 iDelay=205, Bit 2, Center 20 (-139 ~ 180) 320
4762 13:22:05.795349 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4763 13:22:05.798413 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4764 13:22:05.805101 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4765 13:22:05.808571 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4766 13:22:05.812219 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4767 13:22:05.815194 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4768 13:22:05.818673 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4769 13:22:05.825161 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4770 13:22:05.828391 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4771 13:22:05.831679 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4772 13:22:05.835215 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4773 13:22:05.841793 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4774 13:22:05.845080 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4775 13:22:05.845167 ==
4776 13:22:05.848202 Dram Type= 6, Freq= 0, CH_1, rank 1
4777 13:22:05.851404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4778 13:22:05.851492 ==
4779 13:22:05.854780 DQS Delay:
4780 13:22:05.854862 DQS0 = 0, DQS1 = 0
4781 13:22:05.854928 DQM Delay:
4782 13:22:05.858134 DQM0 = 35, DQM1 = 29
4783 13:22:05.858218 DQ Delay:
4784 13:22:05.861381 DQ0 =40, DQ1 =32, DQ2 =20, DQ3 =32
4785 13:22:05.864566 DQ4 =32, DQ5 =48, DQ6 =44, DQ7 =32
4786 13:22:05.868121 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =20
4787 13:22:05.871293 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4788 13:22:05.871382
4789 13:22:05.871476
4790 13:22:05.881535 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d5c, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
4791 13:22:05.884885 CH1 RK1: MR19=808, MR18=3D5C
4792 13:22:05.887903 CH1_RK1: MR19=0x808, MR18=0x3D5C, DQSOSC=392, MR23=63, INC=170, DEC=113
4793 13:22:05.891366 [RxdqsGatingPostProcess] freq 600
4794 13:22:05.897957 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4795 13:22:05.901193 Pre-setting of DQS Precalculation
4796 13:22:05.904639 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4797 13:22:05.914159 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4798 13:22:05.920753 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4799 13:22:05.920834
4800 13:22:05.920921
4801 13:22:05.924292 [Calibration Summary] 1200 Mbps
4802 13:22:05.924372 CH 0, Rank 0
4803 13:22:05.928083 SW Impedance : PASS
4804 13:22:05.928173 DUTY Scan : NO K
4805 13:22:05.930870 ZQ Calibration : PASS
4806 13:22:05.934368 Jitter Meter : NO K
4807 13:22:05.934447 CBT Training : PASS
4808 13:22:05.937643 Write leveling : PASS
4809 13:22:05.940673 RX DQS gating : PASS
4810 13:22:05.940752 RX DQ/DQS(RDDQC) : PASS
4811 13:22:05.944182 TX DQ/DQS : PASS
4812 13:22:05.947150 RX DATLAT : PASS
4813 13:22:05.947234 RX DQ/DQS(Engine): PASS
4814 13:22:05.950670 TX OE : NO K
4815 13:22:05.950753 All Pass.
4816 13:22:05.950846
4817 13:22:05.953825 CH 0, Rank 1
4818 13:22:05.953906 SW Impedance : PASS
4819 13:22:05.956943 DUTY Scan : NO K
4820 13:22:05.960592 ZQ Calibration : PASS
4821 13:22:05.960675 Jitter Meter : NO K
4822 13:22:05.964014 CBT Training : PASS
4823 13:22:05.967356 Write leveling : PASS
4824 13:22:05.967446 RX DQS gating : PASS
4825 13:22:05.970601 RX DQ/DQS(RDDQC) : PASS
4826 13:22:05.974044 TX DQ/DQS : PASS
4827 13:22:05.974128 RX DATLAT : PASS
4828 13:22:05.976990 RX DQ/DQS(Engine): PASS
4829 13:22:05.977073 TX OE : NO K
4830 13:22:05.980613 All Pass.
4831 13:22:05.980695
4832 13:22:05.980760 CH 1, Rank 0
4833 13:22:05.983545 SW Impedance : PASS
4834 13:22:05.987145 DUTY Scan : NO K
4835 13:22:05.987228 ZQ Calibration : PASS
4836 13:22:05.990426 Jitter Meter : NO K
4837 13:22:05.990512 CBT Training : PASS
4838 13:22:05.993742 Write leveling : PASS
4839 13:22:05.996928 RX DQS gating : PASS
4840 13:22:05.997004 RX DQ/DQS(RDDQC) : PASS
4841 13:22:06.000185 TX DQ/DQS : PASS
4842 13:22:06.003464 RX DATLAT : PASS
4843 13:22:06.003584 RX DQ/DQS(Engine): PASS
4844 13:22:06.006839 TX OE : NO K
4845 13:22:06.006922 All Pass.
4846 13:22:06.007007
4847 13:22:06.010376 CH 1, Rank 1
4848 13:22:06.010457 SW Impedance : PASS
4849 13:22:06.013307 DUTY Scan : NO K
4850 13:22:06.017101 ZQ Calibration : PASS
4851 13:22:06.017182 Jitter Meter : NO K
4852 13:22:06.020110 CBT Training : PASS
4853 13:22:06.023710 Write leveling : PASS
4854 13:22:06.023787 RX DQS gating : PASS
4855 13:22:06.026605 RX DQ/DQS(RDDQC) : PASS
4856 13:22:06.030152 TX DQ/DQS : PASS
4857 13:22:06.030230 RX DATLAT : PASS
4858 13:22:06.033216 RX DQ/DQS(Engine): PASS
4859 13:22:06.036714 TX OE : NO K
4860 13:22:06.036802 All Pass.
4861 13:22:06.036880
4862 13:22:06.036943 DramC Write-DBI off
4863 13:22:06.040061 PER_BANK_REFRESH: Hybrid Mode
4864 13:22:06.043666 TX_TRACKING: ON
4865 13:22:06.049539 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4866 13:22:06.053011 [FAST_K] Save calibration result to emmc
4867 13:22:06.059636 dramc_set_vcore_voltage set vcore to 662500
4868 13:22:06.059718 Read voltage for 933, 3
4869 13:22:06.062854 Vio18 = 0
4870 13:22:06.062934 Vcore = 662500
4871 13:22:06.062998 Vdram = 0
4872 13:22:06.066040 Vddq = 0
4873 13:22:06.066122 Vmddr = 0
4874 13:22:06.069581 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4875 13:22:06.076160 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4876 13:22:06.079790 MEM_TYPE=3, freq_sel=17
4877 13:22:06.079877 sv_algorithm_assistance_LP4_1600
4878 13:22:06.086582 ============ PULL DRAM RESETB DOWN ============
4879 13:22:06.089561 ========== PULL DRAM RESETB DOWN end =========
4880 13:22:06.093178 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4881 13:22:06.096560 ===================================
4882 13:22:06.099613 LPDDR4 DRAM CONFIGURATION
4883 13:22:06.102752 ===================================
4884 13:22:06.105914 EX_ROW_EN[0] = 0x0
4885 13:22:06.106011 EX_ROW_EN[1] = 0x0
4886 13:22:06.109628 LP4Y_EN = 0x0
4887 13:22:06.109759 WORK_FSP = 0x0
4888 13:22:06.112849 WL = 0x3
4889 13:22:06.112931 RL = 0x3
4890 13:22:06.116131 BL = 0x2
4891 13:22:06.116213 RPST = 0x0
4892 13:22:06.120035 RD_PRE = 0x0
4893 13:22:06.120119 WR_PRE = 0x1
4894 13:22:06.122266 WR_PST = 0x0
4895 13:22:06.125638 DBI_WR = 0x0
4896 13:22:06.125714 DBI_RD = 0x0
4897 13:22:06.129301 OTF = 0x1
4898 13:22:06.132706 ===================================
4899 13:22:06.135788 ===================================
4900 13:22:06.135865 ANA top config
4901 13:22:06.139385 ===================================
4902 13:22:06.142419 DLL_ASYNC_EN = 0
4903 13:22:06.145863 ALL_SLAVE_EN = 1
4904 13:22:06.145984 NEW_RANK_MODE = 1
4905 13:22:06.149055 DLL_IDLE_MODE = 1
4906 13:22:06.152082 LP45_APHY_COMB_EN = 1
4907 13:22:06.155608 TX_ODT_DIS = 1
4908 13:22:06.155699 NEW_8X_MODE = 1
4909 13:22:06.158662 ===================================
4910 13:22:06.162197 ===================================
4911 13:22:06.165654 data_rate = 1866
4912 13:22:06.168895 CKR = 1
4913 13:22:06.171878 DQ_P2S_RATIO = 8
4914 13:22:06.175819 ===================================
4915 13:22:06.178919 CA_P2S_RATIO = 8
4916 13:22:06.182475 DQ_CA_OPEN = 0
4917 13:22:06.182553 DQ_SEMI_OPEN = 0
4918 13:22:06.185335 CA_SEMI_OPEN = 0
4919 13:22:06.188627 CA_FULL_RATE = 0
4920 13:22:06.192129 DQ_CKDIV4_EN = 1
4921 13:22:06.195307 CA_CKDIV4_EN = 1
4922 13:22:06.198299 CA_PREDIV_EN = 0
4923 13:22:06.198406 PH8_DLY = 0
4924 13:22:06.201708 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4925 13:22:06.205415 DQ_AAMCK_DIV = 4
4926 13:22:06.208778 CA_AAMCK_DIV = 4
4927 13:22:06.212106 CA_ADMCK_DIV = 4
4928 13:22:06.215112 DQ_TRACK_CA_EN = 0
4929 13:22:06.215216 CA_PICK = 933
4930 13:22:06.218646 CA_MCKIO = 933
4931 13:22:06.221589 MCKIO_SEMI = 0
4932 13:22:06.225151 PLL_FREQ = 3732
4933 13:22:06.228340 DQ_UI_PI_RATIO = 32
4934 13:22:06.231968 CA_UI_PI_RATIO = 0
4935 13:22:06.235090 ===================================
4936 13:22:06.238428 ===================================
4937 13:22:06.241638 memory_type:LPDDR4
4938 13:22:06.241721 GP_NUM : 10
4939 13:22:06.245120 SRAM_EN : 1
4940 13:22:06.245203 MD32_EN : 0
4941 13:22:06.248323 ===================================
4942 13:22:06.251681 [ANA_INIT] >>>>>>>>>>>>>>
4943 13:22:06.254818 <<<<<< [CONFIGURE PHASE]: ANA_TX
4944 13:22:06.258552 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4945 13:22:06.261742 ===================================
4946 13:22:06.265011 data_rate = 1866,PCW = 0X8f00
4947 13:22:06.268488 ===================================
4948 13:22:06.271515 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4949 13:22:06.274655 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4950 13:22:06.281905 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4951 13:22:06.288175 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4952 13:22:06.291681 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4953 13:22:06.294937 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4954 13:22:06.295049 [ANA_INIT] flow start
4955 13:22:06.298375 [ANA_INIT] PLL >>>>>>>>
4956 13:22:06.301740 [ANA_INIT] PLL <<<<<<<<
4957 13:22:06.301822 [ANA_INIT] MIDPI >>>>>>>>
4958 13:22:06.304553 [ANA_INIT] MIDPI <<<<<<<<
4959 13:22:06.308087 [ANA_INIT] DLL >>>>>>>>
4960 13:22:06.308171 [ANA_INIT] flow end
4961 13:22:06.315026 ============ LP4 DIFF to SE enter ============
4962 13:22:06.317924 ============ LP4 DIFF to SE exit ============
4963 13:22:06.318022 [ANA_INIT] <<<<<<<<<<<<<
4964 13:22:06.321487 [Flow] Enable top DCM control >>>>>
4965 13:22:06.324764 [Flow] Enable top DCM control <<<<<
4966 13:22:06.328235 Enable DLL master slave shuffle
4967 13:22:06.334748 ==============================================================
4968 13:22:06.337769 Gating Mode config
4969 13:22:06.341131 ==============================================================
4970 13:22:06.344355 Config description:
4971 13:22:06.354482 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4972 13:22:06.361650 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4973 13:22:06.364487 SELPH_MODE 0: By rank 1: By Phase
4974 13:22:06.371054 ==============================================================
4975 13:22:06.374769 GAT_TRACK_EN = 1
4976 13:22:06.377765 RX_GATING_MODE = 2
4977 13:22:06.377843 RX_GATING_TRACK_MODE = 2
4978 13:22:06.381237 SELPH_MODE = 1
4979 13:22:06.384421 PICG_EARLY_EN = 1
4980 13:22:06.388034 VALID_LAT_VALUE = 1
4981 13:22:06.394638 ==============================================================
4982 13:22:06.397908 Enter into Gating configuration >>>>
4983 13:22:06.401093 Exit from Gating configuration <<<<
4984 13:22:06.404341 Enter into DVFS_PRE_config >>>>>
4985 13:22:06.414371 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4986 13:22:06.417595 Exit from DVFS_PRE_config <<<<<
4987 13:22:06.421445 Enter into PICG configuration >>>>
4988 13:22:06.424265 Exit from PICG configuration <<<<
4989 13:22:06.427723 [RX_INPUT] configuration >>>>>
4990 13:22:06.431060 [RX_INPUT] configuration <<<<<
4991 13:22:06.434527 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4992 13:22:06.441513 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4993 13:22:06.447447 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4994 13:22:06.454217 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4995 13:22:06.457778 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4996 13:22:06.464365 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4997 13:22:06.467775 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4998 13:22:06.473938 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4999 13:22:06.477439 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5000 13:22:06.480459 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5001 13:22:06.484216 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5002 13:22:06.490348 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5003 13:22:06.493852 ===================================
5004 13:22:06.497465 LPDDR4 DRAM CONFIGURATION
5005 13:22:06.500407 ===================================
5006 13:22:06.500504 EX_ROW_EN[0] = 0x0
5007 13:22:06.503966 EX_ROW_EN[1] = 0x0
5008 13:22:06.504085 LP4Y_EN = 0x0
5009 13:22:06.507485 WORK_FSP = 0x0
5010 13:22:06.507571 WL = 0x3
5011 13:22:06.510831 RL = 0x3
5012 13:22:06.510915 BL = 0x2
5013 13:22:06.514175 RPST = 0x0
5014 13:22:06.514256 RD_PRE = 0x0
5015 13:22:06.517109 WR_PRE = 0x1
5016 13:22:06.517196 WR_PST = 0x0
5017 13:22:06.520458 DBI_WR = 0x0
5018 13:22:06.520541 DBI_RD = 0x0
5019 13:22:06.523596 OTF = 0x1
5020 13:22:06.527348 ===================================
5021 13:22:06.530223 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5022 13:22:06.533715 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5023 13:22:06.540539 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5024 13:22:06.543914 ===================================
5025 13:22:06.544021 LPDDR4 DRAM CONFIGURATION
5026 13:22:06.546888 ===================================
5027 13:22:06.550362 EX_ROW_EN[0] = 0x10
5028 13:22:06.553613 EX_ROW_EN[1] = 0x0
5029 13:22:06.553696 LP4Y_EN = 0x0
5030 13:22:06.556807 WORK_FSP = 0x0
5031 13:22:06.556894 WL = 0x3
5032 13:22:06.560031 RL = 0x3
5033 13:22:06.560110 BL = 0x2
5034 13:22:06.563586 RPST = 0x0
5035 13:22:06.563666 RD_PRE = 0x0
5036 13:22:06.566859 WR_PRE = 0x1
5037 13:22:06.566941 WR_PST = 0x0
5038 13:22:06.570117 DBI_WR = 0x0
5039 13:22:06.570192 DBI_RD = 0x0
5040 13:22:06.573802 OTF = 0x1
5041 13:22:06.576985 ===================================
5042 13:22:06.583396 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5043 13:22:06.587158 nWR fixed to 30
5044 13:22:06.587242 [ModeRegInit_LP4] CH0 RK0
5045 13:22:06.590091 [ModeRegInit_LP4] CH0 RK1
5046 13:22:06.593728 [ModeRegInit_LP4] CH1 RK0
5047 13:22:06.596817 [ModeRegInit_LP4] CH1 RK1
5048 13:22:06.596916 match AC timing 9
5049 13:22:06.603290 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5050 13:22:06.606800 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5051 13:22:06.610331 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5052 13:22:06.617008 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5053 13:22:06.619853 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5054 13:22:06.619936 ==
5055 13:22:06.623162 Dram Type= 6, Freq= 0, CH_0, rank 0
5056 13:22:06.626760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5057 13:22:06.626852 ==
5058 13:22:06.633114 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5059 13:22:06.639740 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5060 13:22:06.642915 [CA 0] Center 38 (8~69) winsize 62
5061 13:22:06.646476 [CA 1] Center 38 (7~69) winsize 63
5062 13:22:06.650093 [CA 2] Center 35 (5~65) winsize 61
5063 13:22:06.652949 [CA 3] Center 35 (5~65) winsize 61
5064 13:22:06.656542 [CA 4] Center 34 (4~65) winsize 62
5065 13:22:06.660104 [CA 5] Center 33 (3~64) winsize 62
5066 13:22:06.660180
5067 13:22:06.663322 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5068 13:22:06.663403
5069 13:22:06.666295 [CATrainingPosCal] consider 1 rank data
5070 13:22:06.669787 u2DelayCellTimex100 = 270/100 ps
5071 13:22:06.672714 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5072 13:22:06.676103 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5073 13:22:06.679594 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5074 13:22:06.683101 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5075 13:22:06.686089 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5076 13:22:06.689683 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5077 13:22:06.692795
5078 13:22:06.696320 CA PerBit enable=1, Macro0, CA PI delay=33
5079 13:22:06.696402
5080 13:22:06.699456 [CBTSetCACLKResult] CA Dly = 33
5081 13:22:06.699536 CS Dly: 6 (0~37)
5082 13:22:06.699600 ==
5083 13:22:06.703041 Dram Type= 6, Freq= 0, CH_0, rank 1
5084 13:22:06.705859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5085 13:22:06.705960 ==
5086 13:22:06.713114 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5087 13:22:06.719789 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5088 13:22:06.722797 [CA 0] Center 38 (8~69) winsize 62
5089 13:22:06.726114 [CA 1] Center 38 (8~69) winsize 62
5090 13:22:06.729039 [CA 2] Center 35 (5~66) winsize 62
5091 13:22:06.732366 [CA 3] Center 35 (5~66) winsize 62
5092 13:22:06.736150 [CA 4] Center 34 (3~65) winsize 63
5093 13:22:06.739760 [CA 5] Center 33 (3~64) winsize 62
5094 13:22:06.739848
5095 13:22:06.742774 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5096 13:22:06.742849
5097 13:22:06.746292 [CATrainingPosCal] consider 2 rank data
5098 13:22:06.749287 u2DelayCellTimex100 = 270/100 ps
5099 13:22:06.752693 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5100 13:22:06.755852 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5101 13:22:06.759448 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5102 13:22:06.762322 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5103 13:22:06.768953 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5104 13:22:06.772368 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5105 13:22:06.772451
5106 13:22:06.775980 CA PerBit enable=1, Macro0, CA PI delay=33
5107 13:22:06.776059
5108 13:22:06.778871 [CBTSetCACLKResult] CA Dly = 33
5109 13:22:06.778943 CS Dly: 7 (0~39)
5110 13:22:06.779006
5111 13:22:06.782594 ----->DramcWriteLeveling(PI) begin...
5112 13:22:06.782674 ==
5113 13:22:06.786046 Dram Type= 6, Freq= 0, CH_0, rank 0
5114 13:22:06.792454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5115 13:22:06.792534 ==
5116 13:22:06.795630 Write leveling (Byte 0): 28 => 28
5117 13:22:06.795710 Write leveling (Byte 1): 28 => 28
5118 13:22:06.799033 DramcWriteLeveling(PI) end<-----
5119 13:22:06.799114
5120 13:22:06.802293 ==
5121 13:22:06.805394 Dram Type= 6, Freq= 0, CH_0, rank 0
5122 13:22:06.809026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5123 13:22:06.809105 ==
5124 13:22:06.812049 [Gating] SW mode calibration
5125 13:22:06.819173 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5126 13:22:06.822202 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5127 13:22:06.828817 0 14 0 | B1->B0 | 2323 2e2e | 1 0 | (1 1) (0 0)
5128 13:22:06.831862 0 14 4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
5129 13:22:06.835272 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5130 13:22:06.841888 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5131 13:22:06.845196 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5132 13:22:06.848242 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5133 13:22:06.855211 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5134 13:22:06.858351 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5135 13:22:06.861729 0 15 0 | B1->B0 | 3131 2d2d | 1 0 | (1 1) (0 0)
5136 13:22:06.868379 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5137 13:22:06.871886 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5138 13:22:06.875005 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5139 13:22:06.881813 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5140 13:22:06.885026 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5141 13:22:06.888212 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5142 13:22:06.894833 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5143 13:22:06.898518 1 0 0 | B1->B0 | 2d2d 3c3c | 0 0 | (0 0) (0 0)
5144 13:22:06.901628 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 13:22:06.907781 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 13:22:06.911404 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 13:22:06.915004 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 13:22:06.921258 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 13:22:06.925035 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 13:22:06.927741 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 13:22:06.934367 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5152 13:22:06.938088 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5153 13:22:06.940965 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 13:22:06.947697 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 13:22:06.951121 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 13:22:06.954498 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 13:22:06.960964 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 13:22:06.964251 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 13:22:06.967558 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 13:22:06.974156 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 13:22:06.977571 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 13:22:06.980619 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 13:22:06.987604 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 13:22:06.990595 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 13:22:06.994167 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 13:22:06.998209 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5167 13:22:07.004338 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5168 13:22:07.007704 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 13:22:07.011081 Total UI for P1: 0, mck2ui 16
5170 13:22:07.014023 best dqsien dly found for B0: ( 1, 2, 30)
5171 13:22:07.017496 Total UI for P1: 0, mck2ui 16
5172 13:22:07.020676 best dqsien dly found for B1: ( 1, 3, 2)
5173 13:22:07.023935 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5174 13:22:07.027477 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5175 13:22:07.027574
5176 13:22:07.030878 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5177 13:22:07.034081 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5178 13:22:07.037466 [Gating] SW calibration Done
5179 13:22:07.037543 ==
5180 13:22:07.040468 Dram Type= 6, Freq= 0, CH_0, rank 0
5181 13:22:07.043975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5182 13:22:07.047510 ==
5183 13:22:07.047588 RX Vref Scan: 0
5184 13:22:07.047662
5185 13:22:07.050924 RX Vref 0 -> 0, step: 1
5186 13:22:07.051002
5187 13:22:07.053666 RX Delay -80 -> 252, step: 8
5188 13:22:07.057133 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5189 13:22:07.060537 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5190 13:22:07.064090 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5191 13:22:07.067139 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5192 13:22:07.070140 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5193 13:22:07.076763 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5194 13:22:07.080178 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5195 13:22:07.083755 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5196 13:22:07.086798 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5197 13:22:07.090376 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5198 13:22:07.096951 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5199 13:22:07.100393 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5200 13:22:07.103738 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5201 13:22:07.106750 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5202 13:22:07.110436 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5203 13:22:07.116813 iDelay=208, Bit 15, Center 87 (-16 ~ 191) 208
5204 13:22:07.116895 ==
5205 13:22:07.120198 Dram Type= 6, Freq= 0, CH_0, rank 0
5206 13:22:07.123225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5207 13:22:07.123306 ==
5208 13:22:07.123379 DQS Delay:
5209 13:22:07.126585 DQS0 = 0, DQS1 = 0
5210 13:22:07.126657 DQM Delay:
5211 13:22:07.130143 DQM0 = 96, DQM1 = 82
5212 13:22:07.130220 DQ Delay:
5213 13:22:07.133220 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5214 13:22:07.136415 DQ4 =99, DQ5 =79, DQ6 =103, DQ7 =107
5215 13:22:07.139931 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5216 13:22:07.143070 DQ12 =87, DQ13 =87, DQ14 =91, DQ15 =87
5217 13:22:07.143171
5218 13:22:07.143236
5219 13:22:07.143309 ==
5220 13:22:07.146889 Dram Type= 6, Freq= 0, CH_0, rank 0
5221 13:22:07.153308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5222 13:22:07.153389 ==
5223 13:22:07.153455
5224 13:22:07.153515
5225 13:22:07.153573 TX Vref Scan disable
5226 13:22:07.156208 == TX Byte 0 ==
5227 13:22:07.159787 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5228 13:22:07.163179 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5229 13:22:07.166733 == TX Byte 1 ==
5230 13:22:07.169654 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5231 13:22:07.173242 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5232 13:22:07.176404 ==
5233 13:22:07.179955 Dram Type= 6, Freq= 0, CH_0, rank 0
5234 13:22:07.183318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5235 13:22:07.183432 ==
5236 13:22:07.183496
5237 13:22:07.183555
5238 13:22:07.186329 TX Vref Scan disable
5239 13:22:07.186410 == TX Byte 0 ==
5240 13:22:07.193023 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5241 13:22:07.196188 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5242 13:22:07.196303 == TX Byte 1 ==
5243 13:22:07.203442 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5244 13:22:07.206428 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5245 13:22:07.206509
5246 13:22:07.206573 [DATLAT]
5247 13:22:07.209608 Freq=933, CH0 RK0
5248 13:22:07.209699
5249 13:22:07.209776 DATLAT Default: 0xd
5250 13:22:07.213172 0, 0xFFFF, sum = 0
5251 13:22:07.213276 1, 0xFFFF, sum = 0
5252 13:22:07.216177 2, 0xFFFF, sum = 0
5253 13:22:07.216280 3, 0xFFFF, sum = 0
5254 13:22:07.219702 4, 0xFFFF, sum = 0
5255 13:22:07.219805 5, 0xFFFF, sum = 0
5256 13:22:07.223312 6, 0xFFFF, sum = 0
5257 13:22:07.223416 7, 0xFFFF, sum = 0
5258 13:22:07.226089 8, 0xFFFF, sum = 0
5259 13:22:07.229300 9, 0xFFFF, sum = 0
5260 13:22:07.229391 10, 0x0, sum = 1
5261 13:22:07.229475 11, 0x0, sum = 2
5262 13:22:07.232763 12, 0x0, sum = 3
5263 13:22:07.232861 13, 0x0, sum = 4
5264 13:22:07.236129 best_step = 11
5265 13:22:07.236241
5266 13:22:07.236337 ==
5267 13:22:07.239575 Dram Type= 6, Freq= 0, CH_0, rank 0
5268 13:22:07.243072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5269 13:22:07.243161 ==
5270 13:22:07.246174 RX Vref Scan: 1
5271 13:22:07.246274
5272 13:22:07.246339 RX Vref 0 -> 0, step: 1
5273 13:22:07.246409
5274 13:22:07.249562 RX Delay -69 -> 252, step: 4
5275 13:22:07.249663
5276 13:22:07.252715 Set Vref, RX VrefLevel [Byte0]: 61
5277 13:22:07.255958 [Byte1]: 54
5278 13:22:07.260077
5279 13:22:07.260159 Final RX Vref Byte 0 = 61 to rank0
5280 13:22:07.263619 Final RX Vref Byte 1 = 54 to rank0
5281 13:22:07.267178 Final RX Vref Byte 0 = 61 to rank1
5282 13:22:07.269975 Final RX Vref Byte 1 = 54 to rank1==
5283 13:22:07.273706 Dram Type= 6, Freq= 0, CH_0, rank 0
5284 13:22:07.280397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 13:22:07.280480 ==
5286 13:22:07.280547 DQS Delay:
5287 13:22:07.280620 DQS0 = 0, DQS1 = 0
5288 13:22:07.283427 DQM Delay:
5289 13:22:07.283504 DQM0 = 95, DQM1 = 83
5290 13:22:07.286971 DQ Delay:
5291 13:22:07.290041 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5292 13:22:07.293538 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =106
5293 13:22:07.296889 DQ8 =78, DQ9 =70, DQ10 =82, DQ11 =80
5294 13:22:07.300111 DQ12 =86, DQ13 =88, DQ14 =94, DQ15 =90
5295 13:22:07.300203
5296 13:22:07.300278
5297 13:22:07.306488 [DQSOSCAuto] RK0, (LSB)MR18= 0x1616, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 414 ps
5298 13:22:07.309966 CH0 RK0: MR19=505, MR18=1616
5299 13:22:07.316255 CH0_RK0: MR19=0x505, MR18=0x1616, DQSOSC=414, MR23=63, INC=63, DEC=42
5300 13:22:07.316336
5301 13:22:07.319778 ----->DramcWriteLeveling(PI) begin...
5302 13:22:07.319866 ==
5303 13:22:07.323151 Dram Type= 6, Freq= 0, CH_0, rank 1
5304 13:22:07.326217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5305 13:22:07.326311 ==
5306 13:22:07.329551 Write leveling (Byte 0): 34 => 34
5307 13:22:07.333175 Write leveling (Byte 1): 29 => 29
5308 13:22:07.336154 DramcWriteLeveling(PI) end<-----
5309 13:22:07.336232
5310 13:22:07.336308 ==
5311 13:22:07.339605 Dram Type= 6, Freq= 0, CH_0, rank 1
5312 13:22:07.342685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5313 13:22:07.346171 ==
5314 13:22:07.346261 [Gating] SW mode calibration
5315 13:22:07.352590 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5316 13:22:07.359295 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5317 13:22:07.362949 0 14 0 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
5318 13:22:07.369776 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5319 13:22:07.372653 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5320 13:22:07.376478 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5321 13:22:07.382493 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5322 13:22:07.385988 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5323 13:22:07.389619 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5324 13:22:07.395981 0 14 28 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (0 0)
5325 13:22:07.399259 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5326 13:22:07.402761 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5327 13:22:07.409233 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5328 13:22:07.412341 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5329 13:22:07.415988 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5330 13:22:07.422325 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5331 13:22:07.425445 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5332 13:22:07.428954 0 15 28 | B1->B0 | 2424 3535 | 1 0 | (0 0) (0 0)
5333 13:22:07.435692 1 0 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5334 13:22:07.438682 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 13:22:07.442034 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5336 13:22:07.448764 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 13:22:07.452481 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 13:22:07.455425 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 13:22:07.462591 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 13:22:07.465475 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5341 13:22:07.469123 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5342 13:22:07.472284 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 13:22:07.478953 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 13:22:07.482139 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 13:22:07.485305 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 13:22:07.491881 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 13:22:07.495575 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 13:22:07.498506 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 13:22:07.505304 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 13:22:07.508834 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 13:22:07.511938 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 13:22:07.518541 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 13:22:07.521884 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 13:22:07.525208 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 13:22:07.531539 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 13:22:07.535053 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5357 13:22:07.538189 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5358 13:22:07.541892 Total UI for P1: 0, mck2ui 16
5359 13:22:07.544671 best dqsien dly found for B0: ( 1, 2, 28)
5360 13:22:07.548062 Total UI for P1: 0, mck2ui 16
5361 13:22:07.551674 best dqsien dly found for B1: ( 1, 2, 30)
5362 13:22:07.554600 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5363 13:22:07.558503 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5364 13:22:07.558583
5365 13:22:07.564831 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5366 13:22:07.567765 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5367 13:22:07.571368 [Gating] SW calibration Done
5368 13:22:07.571465 ==
5369 13:22:07.574528 Dram Type= 6, Freq= 0, CH_0, rank 1
5370 13:22:07.577981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5371 13:22:07.578066 ==
5372 13:22:07.578131 RX Vref Scan: 0
5373 13:22:07.581340
5374 13:22:07.581425 RX Vref 0 -> 0, step: 1
5375 13:22:07.581491
5376 13:22:07.584544 RX Delay -80 -> 252, step: 8
5377 13:22:07.587986 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5378 13:22:07.591043 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5379 13:22:07.597709 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5380 13:22:07.601320 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5381 13:22:07.604090 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5382 13:22:07.607709 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5383 13:22:07.610944 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5384 13:22:07.617425 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5385 13:22:07.621024 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5386 13:22:07.624000 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5387 13:22:07.627283 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5388 13:22:07.630795 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5389 13:22:07.637279 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5390 13:22:07.640441 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5391 13:22:07.644153 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5392 13:22:07.647579 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5393 13:22:07.647658 ==
5394 13:22:07.650506 Dram Type= 6, Freq= 0, CH_0, rank 1
5395 13:22:07.657182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5396 13:22:07.657264 ==
5397 13:22:07.657344 DQS Delay:
5398 13:22:07.657411 DQS0 = 0, DQS1 = 0
5399 13:22:07.660778 DQM Delay:
5400 13:22:07.660851 DQM0 = 91, DQM1 = 82
5401 13:22:07.663987 DQ Delay:
5402 13:22:07.667387 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5403 13:22:07.670254 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =107
5404 13:22:07.674074 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5405 13:22:07.677098 DQ12 =91, DQ13 =87, DQ14 =91, DQ15 =87
5406 13:22:07.677173
5407 13:22:07.677237
5408 13:22:07.677305 ==
5409 13:22:07.680704 Dram Type= 6, Freq= 0, CH_0, rank 1
5410 13:22:07.684007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5411 13:22:07.684091 ==
5412 13:22:07.684156
5413 13:22:07.684244
5414 13:22:07.686897 TX Vref Scan disable
5415 13:22:07.686994 == TX Byte 0 ==
5416 13:22:07.693298 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5417 13:22:07.696929 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5418 13:22:07.700484 == TX Byte 1 ==
5419 13:22:07.703392 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5420 13:22:07.707039 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5421 13:22:07.707143 ==
5422 13:22:07.710087 Dram Type= 6, Freq= 0, CH_0, rank 1
5423 13:22:07.713872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5424 13:22:07.713969 ==
5425 13:22:07.716618
5426 13:22:07.716702
5427 13:22:07.716773 TX Vref Scan disable
5428 13:22:07.720077 == TX Byte 0 ==
5429 13:22:07.723758 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5430 13:22:07.730511 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5431 13:22:07.730591 == TX Byte 1 ==
5432 13:22:07.733282 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5433 13:22:07.739878 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5434 13:22:07.739982
5435 13:22:07.740062 [DATLAT]
5436 13:22:07.740123 Freq=933, CH0 RK1
5437 13:22:07.740191
5438 13:22:07.743165 DATLAT Default: 0xb
5439 13:22:07.743254 0, 0xFFFF, sum = 0
5440 13:22:07.746569 1, 0xFFFF, sum = 0
5441 13:22:07.746707 2, 0xFFFF, sum = 0
5442 13:22:07.750353 3, 0xFFFF, sum = 0
5443 13:22:07.753440 4, 0xFFFF, sum = 0
5444 13:22:07.753534 5, 0xFFFF, sum = 0
5445 13:22:07.756689 6, 0xFFFF, sum = 0
5446 13:22:07.756776 7, 0xFFFF, sum = 0
5447 13:22:07.759767 8, 0xFFFF, sum = 0
5448 13:22:07.759846 9, 0xFFFF, sum = 0
5449 13:22:07.763210 10, 0x0, sum = 1
5450 13:22:07.763284 11, 0x0, sum = 2
5451 13:22:07.766627 12, 0x0, sum = 3
5452 13:22:07.766708 13, 0x0, sum = 4
5453 13:22:07.766789 best_step = 11
5454 13:22:07.766860
5455 13:22:07.769680 ==
5456 13:22:07.773227 Dram Type= 6, Freq= 0, CH_0, rank 1
5457 13:22:07.776359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5458 13:22:07.776437 ==
5459 13:22:07.776514 RX Vref Scan: 0
5460 13:22:07.776578
5461 13:22:07.780010 RX Vref 0 -> 0, step: 1
5462 13:22:07.780088
5463 13:22:07.782967 RX Delay -69 -> 252, step: 4
5464 13:22:07.786506 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5465 13:22:07.793028 iDelay=199, Bit 1, Center 96 (7 ~ 186) 180
5466 13:22:07.796370 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5467 13:22:07.799610 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5468 13:22:07.802811 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5469 13:22:07.806434 iDelay=199, Bit 5, Center 82 (-9 ~ 174) 184
5470 13:22:07.809443 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5471 13:22:07.816049 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5472 13:22:07.819720 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5473 13:22:07.822924 iDelay=199, Bit 9, Center 68 (-21 ~ 158) 180
5474 13:22:07.825961 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5475 13:22:07.829578 iDelay=199, Bit 11, Center 80 (-9 ~ 170) 180
5476 13:22:07.836495 iDelay=199, Bit 12, Center 90 (-5 ~ 186) 192
5477 13:22:07.839196 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5478 13:22:07.842657 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5479 13:22:07.846111 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5480 13:22:07.846190 ==
5481 13:22:07.849452 Dram Type= 6, Freq= 0, CH_0, rank 1
5482 13:22:07.855936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5483 13:22:07.856029 ==
5484 13:22:07.856112 DQS Delay:
5485 13:22:07.856176 DQS0 = 0, DQS1 = 0
5486 13:22:07.859219 DQM Delay:
5487 13:22:07.859336 DQM0 = 92, DQM1 = 85
5488 13:22:07.862581 DQ Delay:
5489 13:22:07.866196 DQ0 =90, DQ1 =96, DQ2 =88, DQ3 =88
5490 13:22:07.869041 DQ4 =90, DQ5 =82, DQ6 =104, DQ7 =104
5491 13:22:07.872778 DQ8 =78, DQ9 =68, DQ10 =86, DQ11 =80
5492 13:22:07.875834 DQ12 =90, DQ13 =92, DQ14 =94, DQ15 =92
5493 13:22:07.875922
5494 13:22:07.875995
5495 13:22:07.882801 [DQSOSCAuto] RK1, (LSB)MR18= 0x3314, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 405 ps
5496 13:22:07.885675 CH0 RK1: MR19=505, MR18=3314
5497 13:22:07.892392 CH0_RK1: MR19=0x505, MR18=0x3314, DQSOSC=405, MR23=63, INC=66, DEC=44
5498 13:22:07.896095 [RxdqsGatingPostProcess] freq 933
5499 13:22:07.898991 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5500 13:22:07.902277 best DQS0 dly(2T, 0.5T) = (0, 10)
5501 13:22:07.905749 best DQS1 dly(2T, 0.5T) = (0, 11)
5502 13:22:07.909284 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5503 13:22:07.912373 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5504 13:22:07.915448 best DQS0 dly(2T, 0.5T) = (0, 10)
5505 13:22:07.918890 best DQS1 dly(2T, 0.5T) = (0, 10)
5506 13:22:07.922334 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5507 13:22:07.925560 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5508 13:22:07.928739 Pre-setting of DQS Precalculation
5509 13:22:07.932224 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5510 13:22:07.932304 ==
5511 13:22:07.935791 Dram Type= 6, Freq= 0, CH_1, rank 0
5512 13:22:07.942278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5513 13:22:07.942373 ==
5514 13:22:07.945774 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5515 13:22:07.951855 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5516 13:22:07.955839 [CA 0] Center 37 (7~67) winsize 61
5517 13:22:07.958908 [CA 1] Center 37 (7~68) winsize 62
5518 13:22:07.962303 [CA 2] Center 35 (5~65) winsize 61
5519 13:22:07.965822 [CA 3] Center 34 (4~65) winsize 62
5520 13:22:07.968714 [CA 4] Center 34 (5~64) winsize 60
5521 13:22:07.972219 [CA 5] Center 34 (4~64) winsize 61
5522 13:22:07.972298
5523 13:22:07.975587 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5524 13:22:07.975659
5525 13:22:07.978710 [CATrainingPosCal] consider 1 rank data
5526 13:22:07.982182 u2DelayCellTimex100 = 270/100 ps
5527 13:22:07.985151 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5528 13:22:07.991805 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5529 13:22:07.995113 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5530 13:22:07.998763 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5531 13:22:08.001646 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5532 13:22:08.005076 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5533 13:22:08.005152
5534 13:22:08.008161 CA PerBit enable=1, Macro0, CA PI delay=34
5535 13:22:08.008236
5536 13:22:08.011542 [CBTSetCACLKResult] CA Dly = 34
5537 13:22:08.011649 CS Dly: 5 (0~36)
5538 13:22:08.015298 ==
5539 13:22:08.018491 Dram Type= 6, Freq= 0, CH_1, rank 1
5540 13:22:08.021943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5541 13:22:08.022017 ==
5542 13:22:08.024723 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5543 13:22:08.031562 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5544 13:22:08.035407 [CA 0] Center 37 (7~68) winsize 62
5545 13:22:08.038984 [CA 1] Center 37 (7~68) winsize 62
5546 13:22:08.041929 [CA 2] Center 35 (5~65) winsize 61
5547 13:22:08.045563 [CA 3] Center 34 (4~64) winsize 61
5548 13:22:08.049019 [CA 4] Center 35 (5~65) winsize 61
5549 13:22:08.051967 [CA 5] Center 33 (3~64) winsize 62
5550 13:22:08.052057
5551 13:22:08.055560 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5552 13:22:08.055638
5553 13:22:08.058583 [CATrainingPosCal] consider 2 rank data
5554 13:22:08.061933 u2DelayCellTimex100 = 270/100 ps
5555 13:22:08.065234 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5556 13:22:08.071980 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5557 13:22:08.075290 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5558 13:22:08.078230 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5559 13:22:08.081653 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5560 13:22:08.085200 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5561 13:22:08.085308
5562 13:22:08.088236 CA PerBit enable=1, Macro0, CA PI delay=34
5563 13:22:08.088346
5564 13:22:08.091607 [CBTSetCACLKResult] CA Dly = 34
5565 13:22:08.091688 CS Dly: 6 (0~39)
5566 13:22:08.095063
5567 13:22:08.098278 ----->DramcWriteLeveling(PI) begin...
5568 13:22:08.098385 ==
5569 13:22:08.101692 Dram Type= 6, Freq= 0, CH_1, rank 0
5570 13:22:08.104982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5571 13:22:08.105062 ==
5572 13:22:08.108385 Write leveling (Byte 0): 25 => 25
5573 13:22:08.111296 Write leveling (Byte 1): 28 => 28
5574 13:22:08.114730 DramcWriteLeveling(PI) end<-----
5575 13:22:08.114831
5576 13:22:08.114934 ==
5577 13:22:08.117928 Dram Type= 6, Freq= 0, CH_1, rank 0
5578 13:22:08.121580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5579 13:22:08.121653 ==
5580 13:22:08.124684 [Gating] SW mode calibration
5581 13:22:08.131135 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5582 13:22:08.137887 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5583 13:22:08.141289 0 14 0 | B1->B0 | 3333 3333 | 0 0 | (0 0) (0 0)
5584 13:22:08.144801 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5585 13:22:08.151443 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5586 13:22:08.154691 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5587 13:22:08.157931 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5588 13:22:08.164901 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5589 13:22:08.167658 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5590 13:22:08.171185 0 14 28 | B1->B0 | 3030 3030 | 0 0 | (0 1) (0 1)
5591 13:22:08.177680 0 15 0 | B1->B0 | 2626 2828 | 0 0 | (0 0) (0 0)
5592 13:22:08.181050 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5593 13:22:08.184334 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5594 13:22:08.190806 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5595 13:22:08.194206 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5596 13:22:08.197638 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5597 13:22:08.204611 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5598 13:22:08.207725 0 15 28 | B1->B0 | 2b2b 3433 | 1 1 | (0 0) (1 1)
5599 13:22:08.210923 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5600 13:22:08.217490 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 13:22:08.220549 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 13:22:08.224291 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 13:22:08.230809 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 13:22:08.234316 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 13:22:08.237330 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 13:22:08.243882 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 13:22:08.247350 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 13:22:08.250294 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 13:22:08.257145 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 13:22:08.260232 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 13:22:08.263688 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 13:22:08.267381 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 13:22:08.274037 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 13:22:08.277527 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 13:22:08.280429 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 13:22:08.287050 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 13:22:08.290432 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 13:22:08.293426 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 13:22:08.300806 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 13:22:08.303603 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 13:22:08.307187 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 13:22:08.313572 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5623 13:22:08.317128 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5624 13:22:08.320801 Total UI for P1: 0, mck2ui 16
5625 13:22:08.323633 best dqsien dly found for B1: ( 1, 2, 28)
5626 13:22:08.327327 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 13:22:08.330153 Total UI for P1: 0, mck2ui 16
5628 13:22:08.333345 best dqsien dly found for B0: ( 1, 2, 30)
5629 13:22:08.337279 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5630 13:22:08.340092 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5631 13:22:08.340207
5632 13:22:08.346634 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5633 13:22:08.350136 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5634 13:22:08.350215 [Gating] SW calibration Done
5635 13:22:08.353683 ==
5636 13:22:08.353765 Dram Type= 6, Freq= 0, CH_1, rank 0
5637 13:22:08.360414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5638 13:22:08.360528 ==
5639 13:22:08.360662 RX Vref Scan: 0
5640 13:22:08.360783
5641 13:22:08.363589 RX Vref 0 -> 0, step: 1
5642 13:22:08.363700
5643 13:22:08.367207 RX Delay -80 -> 252, step: 8
5644 13:22:08.370029 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5645 13:22:08.373737 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5646 13:22:08.376853 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5647 13:22:08.383275 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5648 13:22:08.386791 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5649 13:22:08.390219 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5650 13:22:08.393150 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5651 13:22:08.396613 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5652 13:22:08.399859 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5653 13:22:08.406352 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5654 13:22:08.409695 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5655 13:22:08.413307 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5656 13:22:08.416581 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5657 13:22:08.420073 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5658 13:22:08.426691 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5659 13:22:08.430177 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5660 13:22:08.430253 ==
5661 13:22:08.433311 Dram Type= 6, Freq= 0, CH_1, rank 0
5662 13:22:08.436714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5663 13:22:08.436788 ==
5664 13:22:08.439546 DQS Delay:
5665 13:22:08.439662 DQS0 = 0, DQS1 = 0
5666 13:22:08.439755 DQM Delay:
5667 13:22:08.443215 DQM0 = 94, DQM1 = 86
5668 13:22:08.443328 DQ Delay:
5669 13:22:08.446447 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5670 13:22:08.449755 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5671 13:22:08.452751 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =87
5672 13:22:08.456397 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5673 13:22:08.456472
5674 13:22:08.456539
5675 13:22:08.456600 ==
5676 13:22:08.459519 Dram Type= 6, Freq= 0, CH_1, rank 0
5677 13:22:08.466261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5678 13:22:08.466347 ==
5679 13:22:08.466412
5680 13:22:08.466495
5681 13:22:08.466566 TX Vref Scan disable
5682 13:22:08.469788 == TX Byte 0 ==
5683 13:22:08.472936 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5684 13:22:08.479854 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5685 13:22:08.479950 == TX Byte 1 ==
5686 13:22:08.483544 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5687 13:22:08.489717 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5688 13:22:08.489810 ==
5689 13:22:08.492799 Dram Type= 6, Freq= 0, CH_1, rank 0
5690 13:22:08.496366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5691 13:22:08.496487 ==
5692 13:22:08.496627
5693 13:22:08.496752
5694 13:22:08.499331 TX Vref Scan disable
5695 13:22:08.499466 == TX Byte 0 ==
5696 13:22:08.506401 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5697 13:22:08.509760 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5698 13:22:08.509852 == TX Byte 1 ==
5699 13:22:08.516141 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5700 13:22:08.519357 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5701 13:22:08.519471
5702 13:22:08.519568 [DATLAT]
5703 13:22:08.522674 Freq=933, CH1 RK0
5704 13:22:08.522763
5705 13:22:08.522863 DATLAT Default: 0xd
5706 13:22:08.526327 0, 0xFFFF, sum = 0
5707 13:22:08.526428 1, 0xFFFF, sum = 0
5708 13:22:08.529282 2, 0xFFFF, sum = 0
5709 13:22:08.529378 3, 0xFFFF, sum = 0
5710 13:22:08.532942 4, 0xFFFF, sum = 0
5711 13:22:08.536304 5, 0xFFFF, sum = 0
5712 13:22:08.536381 6, 0xFFFF, sum = 0
5713 13:22:08.539513 7, 0xFFFF, sum = 0
5714 13:22:08.539590 8, 0xFFFF, sum = 0
5715 13:22:08.542469 9, 0xFFFF, sum = 0
5716 13:22:08.542545 10, 0x0, sum = 1
5717 13:22:08.546203 11, 0x0, sum = 2
5718 13:22:08.546278 12, 0x0, sum = 3
5719 13:22:08.546341 13, 0x0, sum = 4
5720 13:22:08.549272 best_step = 11
5721 13:22:08.549348
5722 13:22:08.549458 ==
5723 13:22:08.552850 Dram Type= 6, Freq= 0, CH_1, rank 0
5724 13:22:08.555979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 13:22:08.556051 ==
5726 13:22:08.559241 RX Vref Scan: 1
5727 13:22:08.559330
5728 13:22:08.559435 RX Vref 0 -> 0, step: 1
5729 13:22:08.563009
5730 13:22:08.563087 RX Delay -69 -> 252, step: 4
5731 13:22:08.563152
5732 13:22:08.566097 Set Vref, RX VrefLevel [Byte0]: 53
5733 13:22:08.569204 [Byte1]: 49
5734 13:22:08.573575
5735 13:22:08.573658 Final RX Vref Byte 0 = 53 to rank0
5736 13:22:08.577292 Final RX Vref Byte 1 = 49 to rank0
5737 13:22:08.580331 Final RX Vref Byte 0 = 53 to rank1
5738 13:22:08.583837 Final RX Vref Byte 1 = 49 to rank1==
5739 13:22:08.587013 Dram Type= 6, Freq= 0, CH_1, rank 0
5740 13:22:08.593885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 13:22:08.593968 ==
5742 13:22:08.594034 DQS Delay:
5743 13:22:08.596772 DQS0 = 0, DQS1 = 0
5744 13:22:08.596854 DQM Delay:
5745 13:22:08.596919 DQM0 = 95, DQM1 = 88
5746 13:22:08.600348 DQ Delay:
5747 13:22:08.603351 DQ0 =100, DQ1 =90, DQ2 =84, DQ3 =94
5748 13:22:08.607101 DQ4 =92, DQ5 =106, DQ6 =108, DQ7 =92
5749 13:22:08.610317 DQ8 =76, DQ9 =80, DQ10 =88, DQ11 =80
5750 13:22:08.613635 DQ12 =100, DQ13 =92, DQ14 =94, DQ15 =94
5751 13:22:08.613717
5752 13:22:08.613782
5753 13:22:08.620402 [DQSOSCAuto] RK0, (LSB)MR18= 0x40d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 420 ps
5754 13:22:08.623366 CH1 RK0: MR19=505, MR18=40D
5755 13:22:08.629918 CH1_RK0: MR19=0x505, MR18=0x40D, DQSOSC=417, MR23=63, INC=62, DEC=41
5756 13:22:08.630001
5757 13:22:08.633125 ----->DramcWriteLeveling(PI) begin...
5758 13:22:08.633234 ==
5759 13:22:08.636909 Dram Type= 6, Freq= 0, CH_1, rank 1
5760 13:22:08.639687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5761 13:22:08.639770 ==
5762 13:22:08.643204 Write leveling (Byte 0): 27 => 27
5763 13:22:08.646727 Write leveling (Byte 1): 27 => 27
5764 13:22:08.649838 DramcWriteLeveling(PI) end<-----
5765 13:22:08.649943
5766 13:22:08.650007 ==
5767 13:22:08.653418 Dram Type= 6, Freq= 0, CH_1, rank 1
5768 13:22:08.656470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5769 13:22:08.656546 ==
5770 13:22:08.659974 [Gating] SW mode calibration
5771 13:22:08.666321 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5772 13:22:08.672759 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5773 13:22:08.676590 0 14 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5774 13:22:08.683019 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5775 13:22:08.686501 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5776 13:22:08.690168 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5777 13:22:08.696006 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5778 13:22:08.699529 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5779 13:22:08.703910 0 14 24 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 0)
5780 13:22:08.709385 0 14 28 | B1->B0 | 2828 2424 | 0 0 | (0 0) (0 0)
5781 13:22:08.713005 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5782 13:22:08.715934 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5783 13:22:08.722963 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5784 13:22:08.725943 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5785 13:22:08.729424 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5786 13:22:08.735892 0 15 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5787 13:22:08.739506 0 15 24 | B1->B0 | 2424 3131 | 0 0 | (0 0) (0 0)
5788 13:22:08.742632 0 15 28 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5789 13:22:08.745827 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 13:22:08.752692 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 13:22:08.756269 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 13:22:08.759252 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 13:22:08.765851 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 13:22:08.768977 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 13:22:08.772413 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5796 13:22:08.779293 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5797 13:22:08.782396 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 13:22:08.786209 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 13:22:08.792558 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 13:22:08.795639 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 13:22:08.799160 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 13:22:08.805749 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 13:22:08.809011 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 13:22:08.812965 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 13:22:08.818847 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 13:22:08.822531 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 13:22:08.825569 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 13:22:08.832643 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 13:22:08.835785 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 13:22:08.838677 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 13:22:08.845806 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5812 13:22:08.848729 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5813 13:22:08.851836 Total UI for P1: 0, mck2ui 16
5814 13:22:08.855269 best dqsien dly found for B0: ( 1, 2, 24)
5815 13:22:08.858600 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 13:22:08.862273 Total UI for P1: 0, mck2ui 16
5817 13:22:08.865584 best dqsien dly found for B1: ( 1, 2, 28)
5818 13:22:08.868514 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5819 13:22:08.872137 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5820 13:22:08.872221
5821 13:22:08.878692 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5822 13:22:08.881536 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5823 13:22:08.881624 [Gating] SW calibration Done
5824 13:22:08.885192 ==
5825 13:22:08.888305 Dram Type= 6, Freq= 0, CH_1, rank 1
5826 13:22:08.891412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5827 13:22:08.891488 ==
5828 13:22:08.891557 RX Vref Scan: 0
5829 13:22:08.891618
5830 13:22:08.894783 RX Vref 0 -> 0, step: 1
5831 13:22:08.894857
5832 13:22:08.898668 RX Delay -80 -> 252, step: 8
5833 13:22:08.901472 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5834 13:22:08.904898 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5835 13:22:08.908187 iDelay=208, Bit 2, Center 79 (-16 ~ 175) 192
5836 13:22:08.914801 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5837 13:22:08.918101 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5838 13:22:08.921528 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5839 13:22:08.924440 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5840 13:22:08.928176 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5841 13:22:08.934673 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5842 13:22:08.937849 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5843 13:22:08.941438 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5844 13:22:08.944344 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5845 13:22:08.947744 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5846 13:22:08.954392 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5847 13:22:08.957872 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5848 13:22:08.961116 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5849 13:22:08.961193 ==
5850 13:22:08.964212 Dram Type= 6, Freq= 0, CH_1, rank 1
5851 13:22:08.967508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5852 13:22:08.967586 ==
5853 13:22:08.970944 DQS Delay:
5854 13:22:08.971019 DQS0 = 0, DQS1 = 0
5855 13:22:08.971082 DQM Delay:
5856 13:22:08.974544 DQM0 = 93, DQM1 = 88
5857 13:22:08.974648 DQ Delay:
5858 13:22:08.977470 DQ0 =95, DQ1 =91, DQ2 =79, DQ3 =91
5859 13:22:08.980624 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5860 13:22:08.984170 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5861 13:22:08.987610 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5862 13:22:08.987699
5863 13:22:08.987761
5864 13:22:08.990577 ==
5865 13:22:08.990685 Dram Type= 6, Freq= 0, CH_1, rank 1
5866 13:22:08.997498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5867 13:22:08.997580 ==
5868 13:22:08.997644
5869 13:22:08.997702
5870 13:22:09.000579 TX Vref Scan disable
5871 13:22:09.000654 == TX Byte 0 ==
5872 13:22:09.004171 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5873 13:22:09.010818 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5874 13:22:09.010914 == TX Byte 1 ==
5875 13:22:09.014043 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5876 13:22:09.020198 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5877 13:22:09.020295 ==
5878 13:22:09.023586 Dram Type= 6, Freq= 0, CH_1, rank 1
5879 13:22:09.027337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5880 13:22:09.027442 ==
5881 13:22:09.027505
5882 13:22:09.027564
5883 13:22:09.030184 TX Vref Scan disable
5884 13:22:09.033673 == TX Byte 0 ==
5885 13:22:09.036848 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5886 13:22:09.040431 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5887 13:22:09.044044 == TX Byte 1 ==
5888 13:22:09.046863 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5889 13:22:09.050258 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5890 13:22:09.050365
5891 13:22:09.053759 [DATLAT]
5892 13:22:09.053852 Freq=933, CH1 RK1
5893 13:22:09.053918
5894 13:22:09.056871 DATLAT Default: 0xb
5895 13:22:09.056947 0, 0xFFFF, sum = 0
5896 13:22:09.059926 1, 0xFFFF, sum = 0
5897 13:22:09.060012 2, 0xFFFF, sum = 0
5898 13:22:09.063326 3, 0xFFFF, sum = 0
5899 13:22:09.063424 4, 0xFFFF, sum = 0
5900 13:22:09.067096 5, 0xFFFF, sum = 0
5901 13:22:09.067174 6, 0xFFFF, sum = 0
5902 13:22:09.069795 7, 0xFFFF, sum = 0
5903 13:22:09.069869 8, 0xFFFF, sum = 0
5904 13:22:09.073142 9, 0xFFFF, sum = 0
5905 13:22:09.073218 10, 0x0, sum = 1
5906 13:22:09.076550 11, 0x0, sum = 2
5907 13:22:09.076627 12, 0x0, sum = 3
5908 13:22:09.079895 13, 0x0, sum = 4
5909 13:22:09.079969 best_step = 11
5910 13:22:09.080031
5911 13:22:09.080090 ==
5912 13:22:09.083029 Dram Type= 6, Freq= 0, CH_1, rank 1
5913 13:22:09.089551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5914 13:22:09.089640 ==
5915 13:22:09.089714 RX Vref Scan: 0
5916 13:22:09.089788
5917 13:22:09.093208 RX Vref 0 -> 0, step: 1
5918 13:22:09.093292
5919 13:22:09.096686 RX Delay -69 -> 252, step: 4
5920 13:22:09.099962 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5921 13:22:09.103392 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5922 13:22:09.109473 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5923 13:22:09.112998 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5924 13:22:09.116398 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5925 13:22:09.119807 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5926 13:22:09.122749 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5927 13:22:09.129721 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5928 13:22:09.133072 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5929 13:22:09.136157 iDelay=203, Bit 9, Center 84 (-9 ~ 178) 188
5930 13:22:09.139584 iDelay=203, Bit 10, Center 94 (3 ~ 186) 184
5931 13:22:09.142560 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5932 13:22:09.145954 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5933 13:22:09.152610 iDelay=203, Bit 13, Center 98 (7 ~ 190) 184
5934 13:22:09.155660 iDelay=203, Bit 14, Center 100 (15 ~ 186) 172
5935 13:22:09.158964 iDelay=203, Bit 15, Center 98 (7 ~ 190) 184
5936 13:22:09.159041 ==
5937 13:22:09.162244 Dram Type= 6, Freq= 0, CH_1, rank 1
5938 13:22:09.165977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5939 13:22:09.166053 ==
5940 13:22:09.169314 DQS Delay:
5941 13:22:09.169387 DQS0 = 0, DQS1 = 0
5942 13:22:09.172239 DQM Delay:
5943 13:22:09.172310 DQM0 = 92, DQM1 = 91
5944 13:22:09.172370 DQ Delay:
5945 13:22:09.175881 DQ0 =96, DQ1 =86, DQ2 =82, DQ3 =88
5946 13:22:09.178967 DQ4 =90, DQ5 =102, DQ6 =104, DQ7 =88
5947 13:22:09.182089 DQ8 =78, DQ9 =84, DQ10 =94, DQ11 =84
5948 13:22:09.185784 DQ12 =98, DQ13 =98, DQ14 =100, DQ15 =98
5949 13:22:09.189196
5950 13:22:09.189274
5951 13:22:09.195252 [DQSOSCAuto] RK1, (LSB)MR18= 0x1125, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 416 ps
5952 13:22:09.198781 CH1 RK1: MR19=505, MR18=1125
5953 13:22:09.205700 CH1_RK1: MR19=0x505, MR18=0x1125, DQSOSC=410, MR23=63, INC=64, DEC=42
5954 13:22:09.208880 [RxdqsGatingPostProcess] freq 933
5955 13:22:09.211915 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5956 13:22:09.215502 best DQS0 dly(2T, 0.5T) = (0, 10)
5957 13:22:09.218892 best DQS1 dly(2T, 0.5T) = (0, 10)
5958 13:22:09.222244 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5959 13:22:09.225571 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5960 13:22:09.228628 best DQS0 dly(2T, 0.5T) = (0, 10)
5961 13:22:09.231962 best DQS1 dly(2T, 0.5T) = (0, 10)
5962 13:22:09.235051 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5963 13:22:09.238861 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5964 13:22:09.242382 Pre-setting of DQS Precalculation
5965 13:22:09.245017 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5966 13:22:09.251566 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5967 13:22:09.261743 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5968 13:22:09.261827
5969 13:22:09.261898
5970 13:22:09.265133 [Calibration Summary] 1866 Mbps
5971 13:22:09.265207 CH 0, Rank 0
5972 13:22:09.268212 SW Impedance : PASS
5973 13:22:09.268289 DUTY Scan : NO K
5974 13:22:09.271564 ZQ Calibration : PASS
5975 13:22:09.275054 Jitter Meter : NO K
5976 13:22:09.275128 CBT Training : PASS
5977 13:22:09.278132 Write leveling : PASS
5978 13:22:09.278212 RX DQS gating : PASS
5979 13:22:09.281603 RX DQ/DQS(RDDQC) : PASS
5980 13:22:09.284829 TX DQ/DQS : PASS
5981 13:22:09.284922 RX DATLAT : PASS
5982 13:22:09.288659 RX DQ/DQS(Engine): PASS
5983 13:22:09.291635 TX OE : NO K
5984 13:22:09.291712 All Pass.
5985 13:22:09.291781
5986 13:22:09.291842 CH 0, Rank 1
5987 13:22:09.294965 SW Impedance : PASS
5988 13:22:09.297899 DUTY Scan : NO K
5989 13:22:09.297976 ZQ Calibration : PASS
5990 13:22:09.301449 Jitter Meter : NO K
5991 13:22:09.304548 CBT Training : PASS
5992 13:22:09.304620 Write leveling : PASS
5993 13:22:09.308368 RX DQS gating : PASS
5994 13:22:09.311049 RX DQ/DQS(RDDQC) : PASS
5995 13:22:09.311140 TX DQ/DQS : PASS
5996 13:22:09.314367 RX DATLAT : PASS
5997 13:22:09.318327 RX DQ/DQS(Engine): PASS
5998 13:22:09.318402 TX OE : NO K
5999 13:22:09.321195 All Pass.
6000 13:22:09.321271
6001 13:22:09.321333 CH 1, Rank 0
6002 13:22:09.324666 SW Impedance : PASS
6003 13:22:09.324742 DUTY Scan : NO K
6004 13:22:09.327700 ZQ Calibration : PASS
6005 13:22:09.330936 Jitter Meter : NO K
6006 13:22:09.331012 CBT Training : PASS
6007 13:22:09.334340 Write leveling : PASS
6008 13:22:09.337653 RX DQS gating : PASS
6009 13:22:09.337729 RX DQ/DQS(RDDQC) : PASS
6010 13:22:09.341215 TX DQ/DQS : PASS
6011 13:22:09.343996 RX DATLAT : PASS
6012 13:22:09.344071 RX DQ/DQS(Engine): PASS
6013 13:22:09.347542 TX OE : NO K
6014 13:22:09.347617 All Pass.
6015 13:22:09.347679
6016 13:22:09.350832 CH 1, Rank 1
6017 13:22:09.350909 SW Impedance : PASS
6018 13:22:09.354224 DUTY Scan : NO K
6019 13:22:09.357567 ZQ Calibration : PASS
6020 13:22:09.357645 Jitter Meter : NO K
6021 13:22:09.360427 CBT Training : PASS
6022 13:22:09.360498 Write leveling : PASS
6023 13:22:09.363921 RX DQS gating : PASS
6024 13:22:09.367665 RX DQ/DQS(RDDQC) : PASS
6025 13:22:09.367741 TX DQ/DQS : PASS
6026 13:22:09.370791 RX DATLAT : PASS
6027 13:22:09.374182 RX DQ/DQS(Engine): PASS
6028 13:22:09.374257 TX OE : NO K
6029 13:22:09.377019 All Pass.
6030 13:22:09.377096
6031 13:22:09.377159 DramC Write-DBI off
6032 13:22:09.380716 PER_BANK_REFRESH: Hybrid Mode
6033 13:22:09.383942 TX_TRACKING: ON
6034 13:22:09.390355 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6035 13:22:09.394018 [FAST_K] Save calibration result to emmc
6036 13:22:09.397593 dramc_set_vcore_voltage set vcore to 650000
6037 13:22:09.400687 Read voltage for 400, 6
6038 13:22:09.400770 Vio18 = 0
6039 13:22:09.403593 Vcore = 650000
6040 13:22:09.403676 Vdram = 0
6041 13:22:09.403742 Vddq = 0
6042 13:22:09.407054 Vmddr = 0
6043 13:22:09.410462 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6044 13:22:09.417220 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6045 13:22:09.417311 MEM_TYPE=3, freq_sel=20
6046 13:22:09.420675 sv_algorithm_assistance_LP4_800
6047 13:22:09.426868 ============ PULL DRAM RESETB DOWN ============
6048 13:22:09.430532 ========== PULL DRAM RESETB DOWN end =========
6049 13:22:09.433945 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6050 13:22:09.437090 ===================================
6051 13:22:09.440371 LPDDR4 DRAM CONFIGURATION
6052 13:22:09.443545 ===================================
6053 13:22:09.446619 EX_ROW_EN[0] = 0x0
6054 13:22:09.446703 EX_ROW_EN[1] = 0x0
6055 13:22:09.450213 LP4Y_EN = 0x0
6056 13:22:09.450296 WORK_FSP = 0x0
6057 13:22:09.453129 WL = 0x2
6058 13:22:09.453212 RL = 0x2
6059 13:22:09.456578 BL = 0x2
6060 13:22:09.456662 RPST = 0x0
6061 13:22:09.460266 RD_PRE = 0x0
6062 13:22:09.460349 WR_PRE = 0x1
6063 13:22:09.463232 WR_PST = 0x0
6064 13:22:09.463313 DBI_WR = 0x0
6065 13:22:09.466276 DBI_RD = 0x0
6066 13:22:09.466358 OTF = 0x1
6067 13:22:09.469857 ===================================
6068 13:22:09.473032 ===================================
6069 13:22:09.476499 ANA top config
6070 13:22:09.480351 ===================================
6071 13:22:09.483307 DLL_ASYNC_EN = 0
6072 13:22:09.483427 ALL_SLAVE_EN = 1
6073 13:22:09.486420 NEW_RANK_MODE = 1
6074 13:22:09.489411 DLL_IDLE_MODE = 1
6075 13:22:09.493001 LP45_APHY_COMB_EN = 1
6076 13:22:09.493083 TX_ODT_DIS = 1
6077 13:22:09.496471 NEW_8X_MODE = 1
6078 13:22:09.500215 ===================================
6079 13:22:09.503148 ===================================
6080 13:22:09.506249 data_rate = 800
6081 13:22:09.509252 CKR = 1
6082 13:22:09.512564 DQ_P2S_RATIO = 4
6083 13:22:09.516235 ===================================
6084 13:22:09.519640 CA_P2S_RATIO = 4
6085 13:22:09.523045 DQ_CA_OPEN = 0
6086 13:22:09.523157 DQ_SEMI_OPEN = 1
6087 13:22:09.526238 CA_SEMI_OPEN = 1
6088 13:22:09.529188 CA_FULL_RATE = 0
6089 13:22:09.532653 DQ_CKDIV4_EN = 0
6090 13:22:09.535839 CA_CKDIV4_EN = 1
6091 13:22:09.535921 CA_PREDIV_EN = 0
6092 13:22:09.539293 PH8_DLY = 0
6093 13:22:09.542516 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6094 13:22:09.545492 DQ_AAMCK_DIV = 0
6095 13:22:09.549106 CA_AAMCK_DIV = 0
6096 13:22:09.552298 CA_ADMCK_DIV = 4
6097 13:22:09.555817 DQ_TRACK_CA_EN = 0
6098 13:22:09.555939 CA_PICK = 800
6099 13:22:09.558975 CA_MCKIO = 400
6100 13:22:09.562321 MCKIO_SEMI = 400
6101 13:22:09.565555 PLL_FREQ = 3016
6102 13:22:09.569260 DQ_UI_PI_RATIO = 32
6103 13:22:09.572161 CA_UI_PI_RATIO = 32
6104 13:22:09.575622 ===================================
6105 13:22:09.578665 ===================================
6106 13:22:09.582233 memory_type:LPDDR4
6107 13:22:09.582316 GP_NUM : 10
6108 13:22:09.585175 SRAM_EN : 1
6109 13:22:09.585258 MD32_EN : 0
6110 13:22:09.588756 ===================================
6111 13:22:09.592178 [ANA_INIT] >>>>>>>>>>>>>>
6112 13:22:09.595924 <<<<<< [CONFIGURE PHASE]: ANA_TX
6113 13:22:09.598675 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6114 13:22:09.601909 ===================================
6115 13:22:09.605568 data_rate = 800,PCW = 0X7400
6116 13:22:09.608575 ===================================
6117 13:22:09.611761 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6118 13:22:09.615292 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6119 13:22:09.628301 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6120 13:22:09.631837 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6121 13:22:09.634786 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6122 13:22:09.638240 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6123 13:22:09.641295 [ANA_INIT] flow start
6124 13:22:09.644834 [ANA_INIT] PLL >>>>>>>>
6125 13:22:09.644943 [ANA_INIT] PLL <<<<<<<<
6126 13:22:09.648086 [ANA_INIT] MIDPI >>>>>>>>
6127 13:22:09.651240 [ANA_INIT] MIDPI <<<<<<<<
6128 13:22:09.655100 [ANA_INIT] DLL >>>>>>>>
6129 13:22:09.655222 [ANA_INIT] flow end
6130 13:22:09.657961 ============ LP4 DIFF to SE enter ============
6131 13:22:09.664883 ============ LP4 DIFF to SE exit ============
6132 13:22:09.664994 [ANA_INIT] <<<<<<<<<<<<<
6133 13:22:09.668102 [Flow] Enable top DCM control >>>>>
6134 13:22:09.671044 [Flow] Enable top DCM control <<<<<
6135 13:22:09.674413 Enable DLL master slave shuffle
6136 13:22:09.680908 ==============================================================
6137 13:22:09.680993 Gating Mode config
6138 13:22:09.687599 ==============================================================
6139 13:22:09.691199 Config description:
6140 13:22:09.700946 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6141 13:22:09.707616 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6142 13:22:09.710685 SELPH_MODE 0: By rank 1: By Phase
6143 13:22:09.717415 ==============================================================
6144 13:22:09.721087 GAT_TRACK_EN = 0
6145 13:22:09.724008 RX_GATING_MODE = 2
6146 13:22:09.724218 RX_GATING_TRACK_MODE = 2
6147 13:22:09.727978 SELPH_MODE = 1
6148 13:22:09.731047 PICG_EARLY_EN = 1
6149 13:22:09.733889 VALID_LAT_VALUE = 1
6150 13:22:09.740642 ==============================================================
6151 13:22:09.744469 Enter into Gating configuration >>>>
6152 13:22:09.747107 Exit from Gating configuration <<<<
6153 13:22:09.750706 Enter into DVFS_PRE_config >>>>>
6154 13:22:09.760463 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6155 13:22:09.763872 Exit from DVFS_PRE_config <<<<<
6156 13:22:09.767111 Enter into PICG configuration >>>>
6157 13:22:09.770378 Exit from PICG configuration <<<<
6158 13:22:09.773877 [RX_INPUT] configuration >>>>>
6159 13:22:09.777220 [RX_INPUT] configuration <<<<<
6160 13:22:09.780416 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6161 13:22:09.786900 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6162 13:22:09.793478 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6163 13:22:09.800576 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6164 13:22:09.803583 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6165 13:22:09.810231 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6166 13:22:09.813672 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6167 13:22:09.820651 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6168 13:22:09.823634 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6169 13:22:09.827012 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6170 13:22:09.830104 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6171 13:22:09.836784 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6172 13:22:09.840215 ===================================
6173 13:22:09.843470 LPDDR4 DRAM CONFIGURATION
6174 13:22:09.846602 ===================================
6175 13:22:09.846688 EX_ROW_EN[0] = 0x0
6176 13:22:09.849978 EX_ROW_EN[1] = 0x0
6177 13:22:09.850062 LP4Y_EN = 0x0
6178 13:22:09.853237 WORK_FSP = 0x0
6179 13:22:09.853321 WL = 0x2
6180 13:22:09.856602 RL = 0x2
6181 13:22:09.856686 BL = 0x2
6182 13:22:09.859722 RPST = 0x0
6183 13:22:09.859806 RD_PRE = 0x0
6184 13:22:09.863177 WR_PRE = 0x1
6185 13:22:09.863259 WR_PST = 0x0
6186 13:22:09.866808 DBI_WR = 0x0
6187 13:22:09.866890 DBI_RD = 0x0
6188 13:22:09.869969 OTF = 0x1
6189 13:22:09.872972 ===================================
6190 13:22:09.876637 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6191 13:22:09.879926 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6192 13:22:09.886503 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6193 13:22:09.890019 ===================================
6194 13:22:09.890104 LPDDR4 DRAM CONFIGURATION
6195 13:22:09.893501 ===================================
6196 13:22:09.896632 EX_ROW_EN[0] = 0x10
6197 13:22:09.899844 EX_ROW_EN[1] = 0x0
6198 13:22:09.899927 LP4Y_EN = 0x0
6199 13:22:09.903011 WORK_FSP = 0x0
6200 13:22:09.903126 WL = 0x2
6201 13:22:09.906554 RL = 0x2
6202 13:22:09.906636 BL = 0x2
6203 13:22:09.910027 RPST = 0x0
6204 13:22:09.910114 RD_PRE = 0x0
6205 13:22:09.913116 WR_PRE = 0x1
6206 13:22:09.913199 WR_PST = 0x0
6207 13:22:09.916343 DBI_WR = 0x0
6208 13:22:09.916460 DBI_RD = 0x0
6209 13:22:09.919423 OTF = 0x1
6210 13:22:09.922990 ===================================
6211 13:22:09.929384 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6212 13:22:09.933238 nWR fixed to 30
6213 13:22:09.936102 [ModeRegInit_LP4] CH0 RK0
6214 13:22:09.936185 [ModeRegInit_LP4] CH0 RK1
6215 13:22:09.939228 [ModeRegInit_LP4] CH1 RK0
6216 13:22:09.942714 [ModeRegInit_LP4] CH1 RK1
6217 13:22:09.942834 match AC timing 19
6218 13:22:09.949287 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6219 13:22:09.952639 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6220 13:22:09.956159 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6221 13:22:09.962317 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6222 13:22:09.965883 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6223 13:22:09.965989 ==
6224 13:22:09.969021 Dram Type= 6, Freq= 0, CH_0, rank 0
6225 13:22:09.972710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6226 13:22:09.972818 ==
6227 13:22:09.979409 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6228 13:22:09.985639 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6229 13:22:09.989260 [CA 0] Center 36 (8~64) winsize 57
6230 13:22:09.992305 [CA 1] Center 36 (8~64) winsize 57
6231 13:22:09.995831 [CA 2] Center 36 (8~64) winsize 57
6232 13:22:09.999493 [CA 3] Center 36 (8~64) winsize 57
6233 13:22:09.999599 [CA 4] Center 36 (8~64) winsize 57
6234 13:22:10.002403 [CA 5] Center 36 (8~64) winsize 57
6235 13:22:10.002521
6236 13:22:10.009240 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6237 13:22:10.009357
6238 13:22:10.012221 [CATrainingPosCal] consider 1 rank data
6239 13:22:10.015363 u2DelayCellTimex100 = 270/100 ps
6240 13:22:10.019147 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 13:22:10.022312 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 13:22:10.025635 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 13:22:10.028871 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 13:22:10.032279 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 13:22:10.035808 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 13:22:10.035890
6247 13:22:10.038643 CA PerBit enable=1, Macro0, CA PI delay=36
6248 13:22:10.038727
6249 13:22:10.042233 [CBTSetCACLKResult] CA Dly = 36
6250 13:22:10.045319 CS Dly: 1 (0~32)
6251 13:22:10.045418 ==
6252 13:22:10.048797 Dram Type= 6, Freq= 0, CH_0, rank 1
6253 13:22:10.052162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6254 13:22:10.052264 ==
6255 13:22:10.058574 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6256 13:22:10.061884 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6257 13:22:10.065611 [CA 0] Center 36 (8~64) winsize 57
6258 13:22:10.068633 [CA 1] Center 36 (8~64) winsize 57
6259 13:22:10.072054 [CA 2] Center 36 (8~64) winsize 57
6260 13:22:10.075606 [CA 3] Center 36 (8~64) winsize 57
6261 13:22:10.078672 [CA 4] Center 36 (8~64) winsize 57
6262 13:22:10.082142 [CA 5] Center 36 (8~64) winsize 57
6263 13:22:10.082225
6264 13:22:10.085283 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6265 13:22:10.085367
6266 13:22:10.088413 [CATrainingPosCal] consider 2 rank data
6267 13:22:10.091815 u2DelayCellTimex100 = 270/100 ps
6268 13:22:10.094888 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 13:22:10.101606 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 13:22:10.105060 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 13:22:10.108735 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 13:22:10.111809 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 13:22:10.114956 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 13:22:10.115040
6275 13:22:10.118167 CA PerBit enable=1, Macro0, CA PI delay=36
6276 13:22:10.118252
6277 13:22:10.121811 [CBTSetCACLKResult] CA Dly = 36
6278 13:22:10.121895 CS Dly: 1 (0~32)
6279 13:22:10.121962
6280 13:22:10.128062 ----->DramcWriteLeveling(PI) begin...
6281 13:22:10.128167 ==
6282 13:22:10.131703 Dram Type= 6, Freq= 0, CH_0, rank 0
6283 13:22:10.135054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6284 13:22:10.135160 ==
6285 13:22:10.138339 Write leveling (Byte 0): 40 => 8
6286 13:22:10.141450 Write leveling (Byte 1): 40 => 8
6287 13:22:10.144678 DramcWriteLeveling(PI) end<-----
6288 13:22:10.144787
6289 13:22:10.144893 ==
6290 13:22:10.148253 Dram Type= 6, Freq= 0, CH_0, rank 0
6291 13:22:10.151535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6292 13:22:10.151616 ==
6293 13:22:10.155117 [Gating] SW mode calibration
6294 13:22:10.161449 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6295 13:22:10.168193 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6296 13:22:10.171089 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6297 13:22:10.175020 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6298 13:22:10.181605 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6299 13:22:10.184427 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6300 13:22:10.187602 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6301 13:22:10.194520 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6302 13:22:10.197699 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6303 13:22:10.201161 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6304 13:22:10.207693 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6305 13:22:10.207787 Total UI for P1: 0, mck2ui 16
6306 13:22:10.211159 best dqsien dly found for B0: ( 0, 14, 24)
6307 13:22:10.214174 Total UI for P1: 0, mck2ui 16
6308 13:22:10.217718 best dqsien dly found for B1: ( 0, 14, 24)
6309 13:22:10.223997 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6310 13:22:10.227367 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6311 13:22:10.227457
6312 13:22:10.231111 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6313 13:22:10.234247 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6314 13:22:10.237618 [Gating] SW calibration Done
6315 13:22:10.237701 ==
6316 13:22:10.240770 Dram Type= 6, Freq= 0, CH_0, rank 0
6317 13:22:10.244608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6318 13:22:10.244692 ==
6319 13:22:10.247552 RX Vref Scan: 0
6320 13:22:10.247636
6321 13:22:10.247702 RX Vref 0 -> 0, step: 1
6322 13:22:10.247764
6323 13:22:10.250661 RX Delay -410 -> 252, step: 16
6324 13:22:10.257690 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6325 13:22:10.260725 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6326 13:22:10.263777 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6327 13:22:10.267272 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6328 13:22:10.270834 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6329 13:22:10.277418 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6330 13:22:10.280415 iDelay=230, Bit 6, Center -35 (-282 ~ 213) 496
6331 13:22:10.283792 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6332 13:22:10.287241 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6333 13:22:10.293567 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6334 13:22:10.297277 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6335 13:22:10.300795 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6336 13:22:10.307490 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6337 13:22:10.310504 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6338 13:22:10.313786 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6339 13:22:10.316861 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6340 13:22:10.316943 ==
6341 13:22:10.320485 Dram Type= 6, Freq= 0, CH_0, rank 0
6342 13:22:10.327029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6343 13:22:10.327111 ==
6344 13:22:10.327175 DQS Delay:
6345 13:22:10.330611 DQS0 = 59, DQS1 = 59
6346 13:22:10.330692 DQM Delay:
6347 13:22:10.333499 DQM0 = 17, DQM1 = 10
6348 13:22:10.333595 DQ Delay:
6349 13:22:10.336855 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6350 13:22:10.340218 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6351 13:22:10.343590 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6352 13:22:10.347031 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6353 13:22:10.347121
6354 13:22:10.347241
6355 13:22:10.347333 ==
6356 13:22:10.350133 Dram Type= 6, Freq= 0, CH_0, rank 0
6357 13:22:10.353055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6358 13:22:10.353149 ==
6359 13:22:10.353233
6360 13:22:10.353327
6361 13:22:10.356921 TX Vref Scan disable
6362 13:22:10.357002 == TX Byte 0 ==
6363 13:22:10.363333 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6364 13:22:10.366675 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6365 13:22:10.366758 == TX Byte 1 ==
6366 13:22:10.373436 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6367 13:22:10.376335 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6368 13:22:10.376431 ==
6369 13:22:10.380000 Dram Type= 6, Freq= 0, CH_0, rank 0
6370 13:22:10.383122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6371 13:22:10.383203 ==
6372 13:22:10.383299
6373 13:22:10.383404
6374 13:22:10.386710 TX Vref Scan disable
6375 13:22:10.386790 == TX Byte 0 ==
6376 13:22:10.393106 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6377 13:22:10.396044 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6378 13:22:10.396125 == TX Byte 1 ==
6379 13:22:10.402950 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6380 13:22:10.406217 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6381 13:22:10.406301
6382 13:22:10.406399 [DATLAT]
6383 13:22:10.409693 Freq=400, CH0 RK0
6384 13:22:10.409775
6385 13:22:10.409888 DATLAT Default: 0xf
6386 13:22:10.413185 0, 0xFFFF, sum = 0
6387 13:22:10.413281 1, 0xFFFF, sum = 0
6388 13:22:10.416207 2, 0xFFFF, sum = 0
6389 13:22:10.416288 3, 0xFFFF, sum = 0
6390 13:22:10.419642 4, 0xFFFF, sum = 0
6391 13:22:10.419733 5, 0xFFFF, sum = 0
6392 13:22:10.422882 6, 0xFFFF, sum = 0
6393 13:22:10.422972 7, 0xFFFF, sum = 0
6394 13:22:10.426320 8, 0xFFFF, sum = 0
6395 13:22:10.429251 9, 0xFFFF, sum = 0
6396 13:22:10.429341 10, 0xFFFF, sum = 0
6397 13:22:10.432820 11, 0xFFFF, sum = 0
6398 13:22:10.432902 12, 0xFFFF, sum = 0
6399 13:22:10.435885 13, 0x0, sum = 1
6400 13:22:10.435977 14, 0x0, sum = 2
6401 13:22:10.439538 15, 0x0, sum = 3
6402 13:22:10.439628 16, 0x0, sum = 4
6403 13:22:10.439715 best_step = 14
6404 13:22:10.443269
6405 13:22:10.443350 ==
6406 13:22:10.446254 Dram Type= 6, Freq= 0, CH_0, rank 0
6407 13:22:10.449735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6408 13:22:10.449835 ==
6409 13:22:10.449930 RX Vref Scan: 1
6410 13:22:10.450012
6411 13:22:10.452836 RX Vref 0 -> 0, step: 1
6412 13:22:10.452937
6413 13:22:10.456033 RX Delay -359 -> 252, step: 8
6414 13:22:10.456118
6415 13:22:10.459595 Set Vref, RX VrefLevel [Byte0]: 61
6416 13:22:10.462359 [Byte1]: 54
6417 13:22:10.466633
6418 13:22:10.466714 Final RX Vref Byte 0 = 61 to rank0
6419 13:22:10.469665 Final RX Vref Byte 1 = 54 to rank0
6420 13:22:10.473627 Final RX Vref Byte 0 = 61 to rank1
6421 13:22:10.476387 Final RX Vref Byte 1 = 54 to rank1==
6422 13:22:10.479884 Dram Type= 6, Freq= 0, CH_0, rank 0
6423 13:22:10.486670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6424 13:22:10.486753 ==
6425 13:22:10.486818 DQS Delay:
6426 13:22:10.489782 DQS0 = 60, DQS1 = 68
6427 13:22:10.489863 DQM Delay:
6428 13:22:10.489927 DQM0 = 14, DQM1 = 13
6429 13:22:10.493267 DQ Delay:
6430 13:22:10.496302 DQ0 =12, DQ1 =16, DQ2 =12, DQ3 =12
6431 13:22:10.499586 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6432 13:22:10.499709 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6433 13:22:10.502960 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6434 13:22:10.506498
6435 13:22:10.506579
6436 13:22:10.512944 [DQSOSCAuto] RK0, (LSB)MR18= 0x8080, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6437 13:22:10.516344 CH0 RK0: MR19=C0C, MR18=8080
6438 13:22:10.522962 CH0_RK0: MR19=0xC0C, MR18=0x8080, DQSOSC=393, MR23=63, INC=382, DEC=254
6439 13:22:10.523046 ==
6440 13:22:10.526372 Dram Type= 6, Freq= 0, CH_0, rank 1
6441 13:22:10.529860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6442 13:22:10.529956 ==
6443 13:22:10.532641 [Gating] SW mode calibration
6444 13:22:10.539124 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6445 13:22:10.545688 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6446 13:22:10.549252 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6447 13:22:10.552664 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6448 13:22:10.559286 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6449 13:22:10.562544 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6450 13:22:10.565762 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6451 13:22:10.572106 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6452 13:22:10.575631 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6453 13:22:10.579254 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6454 13:22:10.585905 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6455 13:22:10.586000 Total UI for P1: 0, mck2ui 16
6456 13:22:10.592573 best dqsien dly found for B0: ( 0, 14, 24)
6457 13:22:10.592651 Total UI for P1: 0, mck2ui 16
6458 13:22:10.599153 best dqsien dly found for B1: ( 0, 14, 24)
6459 13:22:10.602238 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6460 13:22:10.605171 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6461 13:22:10.605260
6462 13:22:10.609217 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6463 13:22:10.611886 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6464 13:22:10.615203 [Gating] SW calibration Done
6465 13:22:10.615293 ==
6466 13:22:10.618611 Dram Type= 6, Freq= 0, CH_0, rank 1
6467 13:22:10.622303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6468 13:22:10.622427 ==
6469 13:22:10.625233 RX Vref Scan: 0
6470 13:22:10.625313
6471 13:22:10.625379 RX Vref 0 -> 0, step: 1
6472 13:22:10.625475
6473 13:22:10.629003 RX Delay -410 -> 252, step: 16
6474 13:22:10.634906 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6475 13:22:10.638497 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6476 13:22:10.642062 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6477 13:22:10.645195 iDelay=230, Bit 3, Center -51 (-314 ~ 213) 528
6478 13:22:10.651816 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6479 13:22:10.655202 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6480 13:22:10.658164 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6481 13:22:10.661556 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6482 13:22:10.667957 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6483 13:22:10.671712 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6484 13:22:10.675166 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6485 13:22:10.678671 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6486 13:22:10.684720 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6487 13:22:10.688266 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6488 13:22:10.691588 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6489 13:22:10.697727 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6490 13:22:10.697812 ==
6491 13:22:10.701193 Dram Type= 6, Freq= 0, CH_0, rank 1
6492 13:22:10.704238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6493 13:22:10.704316 ==
6494 13:22:10.704380 DQS Delay:
6495 13:22:10.707781 DQS0 = 59, DQS1 = 59
6496 13:22:10.707864 DQM Delay:
6497 13:22:10.711441 DQM0 = 15, DQM1 = 10
6498 13:22:10.711534 DQ Delay:
6499 13:22:10.714363 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =8
6500 13:22:10.717596 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6501 13:22:10.720825 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6502 13:22:10.724364 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6503 13:22:10.724440
6504 13:22:10.724512
6505 13:22:10.724574 ==
6506 13:22:10.727543 Dram Type= 6, Freq= 0, CH_0, rank 1
6507 13:22:10.730822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6508 13:22:10.730896 ==
6509 13:22:10.730959
6510 13:22:10.734279
6511 13:22:10.734359 TX Vref Scan disable
6512 13:22:10.737419 == TX Byte 0 ==
6513 13:22:10.740827 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6514 13:22:10.744252 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6515 13:22:10.747530 == TX Byte 1 ==
6516 13:22:10.751265 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6517 13:22:10.753891 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6518 13:22:10.753974 ==
6519 13:22:10.757566 Dram Type= 6, Freq= 0, CH_0, rank 1
6520 13:22:10.760626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6521 13:22:10.760700 ==
6522 13:22:10.760774
6523 13:22:10.763941
6524 13:22:10.764015 TX Vref Scan disable
6525 13:22:10.767299 == TX Byte 0 ==
6526 13:22:10.770350 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6527 13:22:10.773699 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6528 13:22:10.777200 == TX Byte 1 ==
6529 13:22:10.780770 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6530 13:22:10.783972 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6531 13:22:10.784054
6532 13:22:10.784118 [DATLAT]
6533 13:22:10.787172 Freq=400, CH0 RK1
6534 13:22:10.787254
6535 13:22:10.790286 DATLAT Default: 0xe
6536 13:22:10.790368 0, 0xFFFF, sum = 0
6537 13:22:10.794157 1, 0xFFFF, sum = 0
6538 13:22:10.794240 2, 0xFFFF, sum = 0
6539 13:22:10.797352 3, 0xFFFF, sum = 0
6540 13:22:10.797435 4, 0xFFFF, sum = 0
6541 13:22:10.800053 5, 0xFFFF, sum = 0
6542 13:22:10.800136 6, 0xFFFF, sum = 0
6543 13:22:10.803812 7, 0xFFFF, sum = 0
6544 13:22:10.803895 8, 0xFFFF, sum = 0
6545 13:22:10.806559 9, 0xFFFF, sum = 0
6546 13:22:10.806674 10, 0xFFFF, sum = 0
6547 13:22:10.810514 11, 0xFFFF, sum = 0
6548 13:22:10.810598 12, 0xFFFF, sum = 0
6549 13:22:10.813259 13, 0x0, sum = 1
6550 13:22:10.813342 14, 0x0, sum = 2
6551 13:22:10.817048 15, 0x0, sum = 3
6552 13:22:10.817131 16, 0x0, sum = 4
6553 13:22:10.820235 best_step = 14
6554 13:22:10.820316
6555 13:22:10.820381 ==
6556 13:22:10.823520 Dram Type= 6, Freq= 0, CH_0, rank 1
6557 13:22:10.826579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6558 13:22:10.826661 ==
6559 13:22:10.830034 RX Vref Scan: 0
6560 13:22:10.830115
6561 13:22:10.830180 RX Vref 0 -> 0, step: 1
6562 13:22:10.830241
6563 13:22:10.833405 RX Delay -359 -> 252, step: 8
6564 13:22:10.841369 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6565 13:22:10.844596 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6566 13:22:10.847899 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6567 13:22:10.851365 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6568 13:22:10.857665 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6569 13:22:10.861336 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6570 13:22:10.864254 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6571 13:22:10.867983 iDelay=217, Bit 7, Center -40 (-295 ~ 216) 512
6572 13:22:10.874810 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6573 13:22:10.877648 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6574 13:22:10.881379 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6575 13:22:10.884324 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6576 13:22:10.891297 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6577 13:22:10.894718 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6578 13:22:10.897583 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6579 13:22:10.904164 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6580 13:22:10.904251 ==
6581 13:22:10.907582 Dram Type= 6, Freq= 0, CH_0, rank 1
6582 13:22:10.911253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6583 13:22:10.911377 ==
6584 13:22:10.911462 DQS Delay:
6585 13:22:10.914528 DQS0 = 60, DQS1 = 72
6586 13:22:10.914650 DQM Delay:
6587 13:22:10.917598 DQM0 = 11, DQM1 = 18
6588 13:22:10.917714 DQ Delay:
6589 13:22:10.920598 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6590 13:22:10.924263 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =20
6591 13:22:10.927740 DQ8 =12, DQ9 =0, DQ10 =20, DQ11 =12
6592 13:22:10.930833 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6593 13:22:10.930917
6594 13:22:10.930996
6595 13:22:10.937408 [DQSOSCAuto] RK1, (LSB)MR18= 0xcb80, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6596 13:22:10.941071 CH0 RK1: MR19=C0C, MR18=CB80
6597 13:22:10.947292 CH0_RK1: MR19=0xC0C, MR18=0xCB80, DQSOSC=384, MR23=63, INC=400, DEC=267
6598 13:22:10.951332 [RxdqsGatingPostProcess] freq 400
6599 13:22:10.957221 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6600 13:22:10.960540 best DQS0 dly(2T, 0.5T) = (0, 10)
6601 13:22:10.960624 best DQS1 dly(2T, 0.5T) = (0, 10)
6602 13:22:10.963897 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6603 13:22:10.967120 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6604 13:22:10.970836 best DQS0 dly(2T, 0.5T) = (0, 10)
6605 13:22:10.973834 best DQS1 dly(2T, 0.5T) = (0, 10)
6606 13:22:10.977168 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6607 13:22:10.980414 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6608 13:22:10.984074 Pre-setting of DQS Precalculation
6609 13:22:10.990249 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6610 13:22:10.990341 ==
6611 13:22:10.993893 Dram Type= 6, Freq= 0, CH_1, rank 0
6612 13:22:10.996893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6613 13:22:10.996995 ==
6614 13:22:11.003735 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6615 13:22:11.010196 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6616 13:22:11.010280 [CA 0] Center 36 (8~64) winsize 57
6617 13:22:11.013674 [CA 1] Center 36 (8~64) winsize 57
6618 13:22:11.016855 [CA 2] Center 36 (8~64) winsize 57
6619 13:22:11.019917 [CA 3] Center 36 (8~64) winsize 57
6620 13:22:11.023536 [CA 4] Center 36 (8~64) winsize 57
6621 13:22:11.026847 [CA 5] Center 36 (8~64) winsize 57
6622 13:22:11.026928
6623 13:22:11.030207 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6624 13:22:11.030288
6625 13:22:11.033218 [CATrainingPosCal] consider 1 rank data
6626 13:22:11.037078 u2DelayCellTimex100 = 270/100 ps
6627 13:22:11.040144 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 13:22:11.046931 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 13:22:11.049781 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 13:22:11.053438 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 13:22:11.056811 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 13:22:11.060032 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 13:22:11.060179
6634 13:22:11.063242 CA PerBit enable=1, Macro0, CA PI delay=36
6635 13:22:11.063327
6636 13:22:11.066624 [CBTSetCACLKResult] CA Dly = 36
6637 13:22:11.066706 CS Dly: 1 (0~32)
6638 13:22:11.069810 ==
6639 13:22:11.072781 Dram Type= 6, Freq= 0, CH_1, rank 1
6640 13:22:11.076588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6641 13:22:11.076678 ==
6642 13:22:11.079650 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6643 13:22:11.086096 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6644 13:22:11.089784 [CA 0] Center 36 (8~64) winsize 57
6645 13:22:11.093126 [CA 1] Center 36 (8~64) winsize 57
6646 13:22:11.096175 [CA 2] Center 36 (8~64) winsize 57
6647 13:22:11.099784 [CA 3] Center 36 (8~64) winsize 57
6648 13:22:11.102774 [CA 4] Center 36 (8~64) winsize 57
6649 13:22:11.106453 [CA 5] Center 36 (8~64) winsize 57
6650 13:22:11.106541
6651 13:22:11.109404 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6652 13:22:11.109489
6653 13:22:11.112725 [CATrainingPosCal] consider 2 rank data
6654 13:22:11.116162 u2DelayCellTimex100 = 270/100 ps
6655 13:22:11.119908 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 13:22:11.122657 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 13:22:11.126566 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 13:22:11.129663 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 13:22:11.133226 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 13:22:11.139814 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 13:22:11.139896
6662 13:22:11.142749 CA PerBit enable=1, Macro0, CA PI delay=36
6663 13:22:11.142866
6664 13:22:11.145962 [CBTSetCACLKResult] CA Dly = 36
6665 13:22:11.146040 CS Dly: 1 (0~32)
6666 13:22:11.146104
6667 13:22:11.149485 ----->DramcWriteLeveling(PI) begin...
6668 13:22:11.149606 ==
6669 13:22:11.152849 Dram Type= 6, Freq= 0, CH_1, rank 0
6670 13:22:11.159426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6671 13:22:11.159524 ==
6672 13:22:11.162574 Write leveling (Byte 0): 40 => 8
6673 13:22:11.162666 Write leveling (Byte 1): 40 => 8
6674 13:22:11.166015 DramcWriteLeveling(PI) end<-----
6675 13:22:11.166103
6676 13:22:11.166181 ==
6677 13:22:11.169626 Dram Type= 6, Freq= 0, CH_1, rank 0
6678 13:22:11.175962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6679 13:22:11.176046 ==
6680 13:22:11.179341 [Gating] SW mode calibration
6681 13:22:11.186131 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6682 13:22:11.189260 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6683 13:22:11.196183 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6684 13:22:11.199306 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6685 13:22:11.202526 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6686 13:22:11.209276 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6687 13:22:11.212787 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6688 13:22:11.216150 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6689 13:22:11.222602 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6690 13:22:11.226465 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6691 13:22:11.229210 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6692 13:22:11.232746 Total UI for P1: 0, mck2ui 16
6693 13:22:11.235856 best dqsien dly found for B0: ( 0, 14, 24)
6694 13:22:11.239340 Total UI for P1: 0, mck2ui 16
6695 13:22:11.242496 best dqsien dly found for B1: ( 0, 14, 24)
6696 13:22:11.246116 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6697 13:22:11.249157 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6698 13:22:11.249261
6699 13:22:11.252593 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6700 13:22:11.259195 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6701 13:22:11.259297 [Gating] SW calibration Done
6702 13:22:11.259450 ==
6703 13:22:11.262158 Dram Type= 6, Freq= 0, CH_1, rank 0
6704 13:22:11.269110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6705 13:22:11.269194 ==
6706 13:22:11.269291 RX Vref Scan: 0
6707 13:22:11.269378
6708 13:22:11.272370 RX Vref 0 -> 0, step: 1
6709 13:22:11.272455
6710 13:22:11.275929 RX Delay -410 -> 252, step: 16
6711 13:22:11.278799 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6712 13:22:11.282453 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6713 13:22:11.289054 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6714 13:22:11.292126 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6715 13:22:11.295111 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6716 13:22:11.298970 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6717 13:22:11.305076 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6718 13:22:11.308320 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6719 13:22:11.311802 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6720 13:22:11.315331 iDelay=230, Bit 9, Center -67 (-330 ~ 197) 528
6721 13:22:11.321711 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6722 13:22:11.325254 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6723 13:22:11.328184 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6724 13:22:11.335043 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6725 13:22:11.338436 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6726 13:22:11.341265 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6727 13:22:11.341344 ==
6728 13:22:11.344924 Dram Type= 6, Freq= 0, CH_1, rank 0
6729 13:22:11.347950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6730 13:22:11.351611 ==
6731 13:22:11.351691 DQS Delay:
6732 13:22:11.351757 DQS0 = 51, DQS1 = 67
6733 13:22:11.354780 DQM Delay:
6734 13:22:11.354856 DQM0 = 13, DQM1 = 16
6735 13:22:11.358070 DQ Delay:
6736 13:22:11.358172 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6737 13:22:11.361532 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6738 13:22:11.364346 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6739 13:22:11.367938 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6740 13:22:11.368029
6741 13:22:11.368111
6742 13:22:11.371004 ==
6743 13:22:11.371096 Dram Type= 6, Freq= 0, CH_1, rank 0
6744 13:22:11.377639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6745 13:22:11.377731 ==
6746 13:22:11.377826
6747 13:22:11.377908
6748 13:22:11.380928 TX Vref Scan disable
6749 13:22:11.381015 == TX Byte 0 ==
6750 13:22:11.384511 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6751 13:22:11.391287 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6752 13:22:11.391398 == TX Byte 1 ==
6753 13:22:11.394269 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6754 13:22:11.400924 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6755 13:22:11.401018 ==
6756 13:22:11.404035 Dram Type= 6, Freq= 0, CH_1, rank 0
6757 13:22:11.407824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6758 13:22:11.407918 ==
6759 13:22:11.408004
6760 13:22:11.408085
6761 13:22:11.410638 TX Vref Scan disable
6762 13:22:11.410718 == TX Byte 0 ==
6763 13:22:11.414452 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6764 13:22:11.420869 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6765 13:22:11.420959 == TX Byte 1 ==
6766 13:22:11.424285 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6767 13:22:11.431123 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6768 13:22:11.431211
6769 13:22:11.431326 [DATLAT]
6770 13:22:11.431429 Freq=400, CH1 RK0
6771 13:22:11.431523
6772 13:22:11.433901 DATLAT Default: 0xf
6773 13:22:11.437360 0, 0xFFFF, sum = 0
6774 13:22:11.437450 1, 0xFFFF, sum = 0
6775 13:22:11.440941 2, 0xFFFF, sum = 0
6776 13:22:11.441025 3, 0xFFFF, sum = 0
6777 13:22:11.444407 4, 0xFFFF, sum = 0
6778 13:22:11.444483 5, 0xFFFF, sum = 0
6779 13:22:11.447338 6, 0xFFFF, sum = 0
6780 13:22:11.447441 7, 0xFFFF, sum = 0
6781 13:22:11.450635 8, 0xFFFF, sum = 0
6782 13:22:11.450739 9, 0xFFFF, sum = 0
6783 13:22:11.454055 10, 0xFFFF, sum = 0
6784 13:22:11.454131 11, 0xFFFF, sum = 0
6785 13:22:11.457240 12, 0xFFFF, sum = 0
6786 13:22:11.457315 13, 0x0, sum = 1
6787 13:22:11.460778 14, 0x0, sum = 2
6788 13:22:11.460850 15, 0x0, sum = 3
6789 13:22:11.464150 16, 0x0, sum = 4
6790 13:22:11.464228 best_step = 14
6791 13:22:11.464290
6792 13:22:11.464349 ==
6793 13:22:11.467153 Dram Type= 6, Freq= 0, CH_1, rank 0
6794 13:22:11.470591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6795 13:22:11.474137 ==
6796 13:22:11.474221 RX Vref Scan: 1
6797 13:22:11.474306
6798 13:22:11.477039 RX Vref 0 -> 0, step: 1
6799 13:22:11.477115
6800 13:22:11.480627 RX Delay -375 -> 252, step: 8
6801 13:22:11.480706
6802 13:22:11.484130 Set Vref, RX VrefLevel [Byte0]: 53
6803 13:22:11.486979 [Byte1]: 49
6804 13:22:11.487113
6805 13:22:11.490649 Final RX Vref Byte 0 = 53 to rank0
6806 13:22:11.493676 Final RX Vref Byte 1 = 49 to rank0
6807 13:22:11.497404 Final RX Vref Byte 0 = 53 to rank1
6808 13:22:11.500631 Final RX Vref Byte 1 = 49 to rank1==
6809 13:22:11.503625 Dram Type= 6, Freq= 0, CH_1, rank 0
6810 13:22:11.506607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6811 13:22:11.510048 ==
6812 13:22:11.510162 DQS Delay:
6813 13:22:11.510235 DQS0 = 52, DQS1 = 68
6814 13:22:11.513499 DQM Delay:
6815 13:22:11.513585 DQM0 = 10, DQM1 = 14
6816 13:22:11.516543 DQ Delay:
6817 13:22:11.516655 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6818 13:22:11.520119 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =8
6819 13:22:11.523282 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6820 13:22:11.526707 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6821 13:22:11.526824
6822 13:22:11.526970
6823 13:22:11.536727 [DQSOSCAuto] RK0, (LSB)MR18= 0x5b6f, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 398 ps
6824 13:22:11.539944 CH1 RK0: MR19=C0C, MR18=5B6F
6825 13:22:11.546417 CH1_RK0: MR19=0xC0C, MR18=0x5B6F, DQSOSC=395, MR23=63, INC=378, DEC=252
6826 13:22:11.546506 ==
6827 13:22:11.549755 Dram Type= 6, Freq= 0, CH_1, rank 1
6828 13:22:11.553210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6829 13:22:11.553323 ==
6830 13:22:11.556455 [Gating] SW mode calibration
6831 13:22:11.563291 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6832 13:22:11.569461 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6833 13:22:11.572997 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6834 13:22:11.576455 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6835 13:22:11.579298 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6836 13:22:11.585955 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6837 13:22:11.588975 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6838 13:22:11.595781 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6839 13:22:11.599453 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6840 13:22:11.602582 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6841 13:22:11.609329 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6842 13:22:11.609412 Total UI for P1: 0, mck2ui 16
6843 13:22:11.612398 best dqsien dly found for B0: ( 0, 14, 24)
6844 13:22:11.616250 Total UI for P1: 0, mck2ui 16
6845 13:22:11.618789 best dqsien dly found for B1: ( 0, 14, 24)
6846 13:22:11.625523 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6847 13:22:11.628971 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6848 13:22:11.629057
6849 13:22:11.631876 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6850 13:22:11.635434 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6851 13:22:11.639012 [Gating] SW calibration Done
6852 13:22:11.639092 ==
6853 13:22:11.641913 Dram Type= 6, Freq= 0, CH_1, rank 1
6854 13:22:11.645333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6855 13:22:11.645420 ==
6856 13:22:11.648946 RX Vref Scan: 0
6857 13:22:11.649042
6858 13:22:11.649111 RX Vref 0 -> 0, step: 1
6859 13:22:11.649174
6860 13:22:11.651775 RX Delay -410 -> 252, step: 16
6861 13:22:11.658251 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6862 13:22:11.661872 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6863 13:22:11.665082 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6864 13:22:11.668166 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6865 13:22:11.675400 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6866 13:22:11.678149 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6867 13:22:11.681728 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6868 13:22:11.685101 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6869 13:22:11.691396 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6870 13:22:11.694857 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6871 13:22:11.698131 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6872 13:22:11.701809 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6873 13:22:11.707786 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6874 13:22:11.711411 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6875 13:22:11.714410 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6876 13:22:11.721614 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6877 13:22:11.721698 ==
6878 13:22:11.724531 Dram Type= 6, Freq= 0, CH_1, rank 1
6879 13:22:11.727628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6880 13:22:11.727707 ==
6881 13:22:11.727783 DQS Delay:
6882 13:22:11.731017 DQS0 = 59, DQS1 = 59
6883 13:22:11.731101 DQM Delay:
6884 13:22:11.734227 DQM0 = 18, DQM1 = 12
6885 13:22:11.734305 DQ Delay:
6886 13:22:11.737855 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6887 13:22:11.740861 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6888 13:22:11.744382 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6889 13:22:11.747891 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6890 13:22:11.747981
6891 13:22:11.748048
6892 13:22:11.748119 ==
6893 13:22:11.750858 Dram Type= 6, Freq= 0, CH_1, rank 1
6894 13:22:11.754624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6895 13:22:11.754724 ==
6896 13:22:11.754790
6897 13:22:11.754852
6898 13:22:11.757455 TX Vref Scan disable
6899 13:22:11.761057 == TX Byte 0 ==
6900 13:22:11.764166 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6901 13:22:11.767520 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6902 13:22:11.771172 == TX Byte 1 ==
6903 13:22:11.774039 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6904 13:22:11.777337 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6905 13:22:11.777417 ==
6906 13:22:11.780847 Dram Type= 6, Freq= 0, CH_1, rank 1
6907 13:22:11.784420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6908 13:22:11.784509 ==
6909 13:22:11.784587
6910 13:22:11.787305
6911 13:22:11.787416 TX Vref Scan disable
6912 13:22:11.790578 == TX Byte 0 ==
6913 13:22:11.793892 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6914 13:22:11.797419 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6915 13:22:11.800986 == TX Byte 1 ==
6916 13:22:11.803783 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6917 13:22:11.807239 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6918 13:22:11.807317
6919 13:22:11.807435 [DATLAT]
6920 13:22:11.810960 Freq=400, CH1 RK1
6921 13:22:11.811073
6922 13:22:11.811182 DATLAT Default: 0xe
6923 13:22:11.813873 0, 0xFFFF, sum = 0
6924 13:22:11.813955 1, 0xFFFF, sum = 0
6925 13:22:11.817483 2, 0xFFFF, sum = 0
6926 13:22:11.820430 3, 0xFFFF, sum = 0
6927 13:22:11.820515 4, 0xFFFF, sum = 0
6928 13:22:11.824168 5, 0xFFFF, sum = 0
6929 13:22:11.824262 6, 0xFFFF, sum = 0
6930 13:22:11.827128 7, 0xFFFF, sum = 0
6931 13:22:11.827235 8, 0xFFFF, sum = 0
6932 13:22:11.830568 9, 0xFFFF, sum = 0
6933 13:22:11.830645 10, 0xFFFF, sum = 0
6934 13:22:11.833749 11, 0xFFFF, sum = 0
6935 13:22:11.833824 12, 0xFFFF, sum = 0
6936 13:22:11.837441 13, 0x0, sum = 1
6937 13:22:11.837570 14, 0x0, sum = 2
6938 13:22:11.840438 15, 0x0, sum = 3
6939 13:22:11.840540 16, 0x0, sum = 4
6940 13:22:11.843984 best_step = 14
6941 13:22:11.844087
6942 13:22:11.844183 ==
6943 13:22:11.847218 Dram Type= 6, Freq= 0, CH_1, rank 1
6944 13:22:11.850259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6945 13:22:11.850348 ==
6946 13:22:11.850443 RX Vref Scan: 0
6947 13:22:11.853607
6948 13:22:11.853686 RX Vref 0 -> 0, step: 1
6949 13:22:11.853797
6950 13:22:11.857043 RX Delay -359 -> 252, step: 8
6951 13:22:11.864350 iDelay=217, Bit 0, Center -40 (-287 ~ 208) 496
6952 13:22:11.868138 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6953 13:22:11.871175 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6954 13:22:11.874755 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6955 13:22:11.880928 iDelay=217, Bit 4, Center -44 (-295 ~ 208) 504
6956 13:22:11.884320 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6957 13:22:11.887465 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6958 13:22:11.893940 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6959 13:22:11.897679 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6960 13:22:11.900754 iDelay=217, Bit 9, Center -60 (-319 ~ 200) 520
6961 13:22:11.904128 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6962 13:22:11.910763 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6963 13:22:11.914130 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6964 13:22:11.917350 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6965 13:22:11.920981 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6966 13:22:11.927439 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6967 13:22:11.927581 ==
6968 13:22:11.930487 Dram Type= 6, Freq= 0, CH_1, rank 1
6969 13:22:11.934071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6970 13:22:11.934154 ==
6971 13:22:11.934237 DQS Delay:
6972 13:22:11.937734 DQS0 = 60, DQS1 = 64
6973 13:22:11.937819 DQM Delay:
6974 13:22:11.940692 DQM0 = 13, DQM1 = 11
6975 13:22:11.940776 DQ Delay:
6976 13:22:11.944291 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6977 13:22:11.947363 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6978 13:22:11.950653 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6979 13:22:11.953759 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6980 13:22:11.953840
6981 13:22:11.953932
6982 13:22:11.960556 [DQSOSCAuto] RK1, (LSB)MR18= 0x7fae, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 393 ps
6983 13:22:11.964120 CH1 RK1: MR19=C0C, MR18=7FAE
6984 13:22:11.970567 CH1_RK1: MR19=0xC0C, MR18=0x7FAE, DQSOSC=388, MR23=63, INC=392, DEC=261
6985 13:22:11.974232 [RxdqsGatingPostProcess] freq 400
6986 13:22:11.980342 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6987 13:22:11.983752 best DQS0 dly(2T, 0.5T) = (0, 10)
6988 13:22:11.983861 best DQS1 dly(2T, 0.5T) = (0, 10)
6989 13:22:11.987479 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6990 13:22:11.990349 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6991 13:22:11.993807 best DQS0 dly(2T, 0.5T) = (0, 10)
6992 13:22:11.997535 best DQS1 dly(2T, 0.5T) = (0, 10)
6993 13:22:12.000551 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6994 13:22:12.003542 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6995 13:22:12.006792 Pre-setting of DQS Precalculation
6996 13:22:12.013496 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6997 13:22:12.020119 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6998 13:22:12.027158 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6999 13:22:12.027253
7000 13:22:12.027358
7001 13:22:12.030441 [Calibration Summary] 800 Mbps
7002 13:22:12.030519 CH 0, Rank 0
7003 13:22:12.033639 SW Impedance : PASS
7004 13:22:12.036649 DUTY Scan : NO K
7005 13:22:12.036758 ZQ Calibration : PASS
7006 13:22:12.040427 Jitter Meter : NO K
7007 13:22:12.043331 CBT Training : PASS
7008 13:22:12.043436 Write leveling : PASS
7009 13:22:12.046529 RX DQS gating : PASS
7010 13:22:12.046647 RX DQ/DQS(RDDQC) : PASS
7011 13:22:12.049915 TX DQ/DQS : PASS
7012 13:22:12.053557 RX DATLAT : PASS
7013 13:22:12.053641 RX DQ/DQS(Engine): PASS
7014 13:22:12.056725 TX OE : NO K
7015 13:22:12.056804 All Pass.
7016 13:22:12.056897
7017 13:22:12.060168 CH 0, Rank 1
7018 13:22:12.060252 SW Impedance : PASS
7019 13:22:12.063502 DUTY Scan : NO K
7020 13:22:12.066651 ZQ Calibration : PASS
7021 13:22:12.066727 Jitter Meter : NO K
7022 13:22:12.069876 CBT Training : PASS
7023 13:22:12.073179 Write leveling : NO K
7024 13:22:12.073261 RX DQS gating : PASS
7025 13:22:12.076800 RX DQ/DQS(RDDQC) : PASS
7026 13:22:12.079799 TX DQ/DQS : PASS
7027 13:22:12.079880 RX DATLAT : PASS
7028 13:22:12.083162 RX DQ/DQS(Engine): PASS
7029 13:22:12.086687 TX OE : NO K
7030 13:22:12.086767 All Pass.
7031 13:22:12.086860
7032 13:22:12.086941 CH 1, Rank 0
7033 13:22:12.090205 SW Impedance : PASS
7034 13:22:12.093376 DUTY Scan : NO K
7035 13:22:12.093488 ZQ Calibration : PASS
7036 13:22:12.096269 Jitter Meter : NO K
7037 13:22:12.099957 CBT Training : PASS
7038 13:22:12.100045 Write leveling : PASS
7039 13:22:12.103231 RX DQS gating : PASS
7040 13:22:12.103358 RX DQ/DQS(RDDQC) : PASS
7041 13:22:12.106518 TX DQ/DQS : PASS
7042 13:22:12.110025 RX DATLAT : PASS
7043 13:22:12.110128 RX DQ/DQS(Engine): PASS
7044 13:22:12.112795 TX OE : NO K
7045 13:22:12.112909 All Pass.
7046 13:22:12.113016
7047 13:22:12.116325 CH 1, Rank 1
7048 13:22:12.116435 SW Impedance : PASS
7049 13:22:12.119780 DUTY Scan : NO K
7050 13:22:12.122947 ZQ Calibration : PASS
7051 13:22:12.123028 Jitter Meter : NO K
7052 13:22:12.126478 CBT Training : PASS
7053 13:22:12.129903 Write leveling : NO K
7054 13:22:12.129986 RX DQS gating : PASS
7055 13:22:12.132872 RX DQ/DQS(RDDQC) : PASS
7056 13:22:12.136201 TX DQ/DQS : PASS
7057 13:22:12.136284 RX DATLAT : PASS
7058 13:22:12.139763 RX DQ/DQS(Engine): PASS
7059 13:22:12.142901 TX OE : NO K
7060 13:22:12.142983 All Pass.
7061 13:22:12.143048
7062 13:22:12.143107 DramC Write-DBI off
7063 13:22:12.146052 PER_BANK_REFRESH: Hybrid Mode
7064 13:22:12.149299 TX_TRACKING: ON
7065 13:22:12.156152 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7066 13:22:12.162704 [FAST_K] Save calibration result to emmc
7067 13:22:12.166284 dramc_set_vcore_voltage set vcore to 725000
7068 13:22:12.166365 Read voltage for 1600, 0
7069 13:22:12.169335 Vio18 = 0
7070 13:22:12.169415 Vcore = 725000
7071 13:22:12.169480 Vdram = 0
7072 13:22:12.172893 Vddq = 0
7073 13:22:12.172974 Vmddr = 0
7074 13:22:12.176176 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7075 13:22:12.182478 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7076 13:22:12.185672 MEM_TYPE=3, freq_sel=13
7077 13:22:12.189433 sv_algorithm_assistance_LP4_3733
7078 13:22:12.192268 ============ PULL DRAM RESETB DOWN ============
7079 13:22:12.195814 ========== PULL DRAM RESETB DOWN end =========
7080 13:22:12.202420 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7081 13:22:12.206096 ===================================
7082 13:22:12.206180 LPDDR4 DRAM CONFIGURATION
7083 13:22:12.209314 ===================================
7084 13:22:12.212811 EX_ROW_EN[0] = 0x0
7085 13:22:12.212894 EX_ROW_EN[1] = 0x0
7086 13:22:12.215438 LP4Y_EN = 0x0
7087 13:22:12.215534 WORK_FSP = 0x1
7088 13:22:12.219110 WL = 0x5
7089 13:22:12.219192 RL = 0x5
7090 13:22:12.222574 BL = 0x2
7091 13:22:12.225374 RPST = 0x0
7092 13:22:12.225476 RD_PRE = 0x0
7093 13:22:12.229027 WR_PRE = 0x1
7094 13:22:12.229132 WR_PST = 0x1
7095 13:22:12.232532 DBI_WR = 0x0
7096 13:22:12.232618 DBI_RD = 0x0
7097 13:22:12.235519 OTF = 0x1
7098 13:22:12.238818 ===================================
7099 13:22:12.242541 ===================================
7100 13:22:12.242644 ANA top config
7101 13:22:12.245382 ===================================
7102 13:22:12.249252 DLL_ASYNC_EN = 0
7103 13:22:12.252452 ALL_SLAVE_EN = 0
7104 13:22:12.252582 NEW_RANK_MODE = 1
7105 13:22:12.255520 DLL_IDLE_MODE = 1
7106 13:22:12.258888 LP45_APHY_COMB_EN = 1
7107 13:22:12.262582 TX_ODT_DIS = 0
7108 13:22:12.262660 NEW_8X_MODE = 1
7109 13:22:12.265447 ===================================
7110 13:22:12.268683 ===================================
7111 13:22:12.272231 data_rate = 3200
7112 13:22:12.275766 CKR = 1
7113 13:22:12.278781 DQ_P2S_RATIO = 8
7114 13:22:12.282140 ===================================
7115 13:22:12.285417 CA_P2S_RATIO = 8
7116 13:22:12.288500 DQ_CA_OPEN = 0
7117 13:22:12.288635 DQ_SEMI_OPEN = 0
7118 13:22:12.292305 CA_SEMI_OPEN = 0
7119 13:22:12.295232 CA_FULL_RATE = 0
7120 13:22:12.298421 DQ_CKDIV4_EN = 0
7121 13:22:12.301665 CA_CKDIV4_EN = 0
7122 13:22:12.305248 CA_PREDIV_EN = 0
7123 13:22:12.308519 PH8_DLY = 12
7124 13:22:12.308596 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7125 13:22:12.311987 DQ_AAMCK_DIV = 4
7126 13:22:12.314823 CA_AAMCK_DIV = 4
7127 13:22:12.318116 CA_ADMCK_DIV = 4
7128 13:22:12.321620 DQ_TRACK_CA_EN = 0
7129 13:22:12.325271 CA_PICK = 1600
7130 13:22:12.328061 CA_MCKIO = 1600
7131 13:22:12.328139 MCKIO_SEMI = 0
7132 13:22:12.331838 PLL_FREQ = 3068
7133 13:22:12.334780 DQ_UI_PI_RATIO = 32
7134 13:22:12.338444 CA_UI_PI_RATIO = 0
7135 13:22:12.341700 ===================================
7136 13:22:12.344742 ===================================
7137 13:22:12.347960 memory_type:LPDDR4
7138 13:22:12.348081 GP_NUM : 10
7139 13:22:12.351507 SRAM_EN : 1
7140 13:22:12.354530 MD32_EN : 0
7141 13:22:12.358272 ===================================
7142 13:22:12.358357 [ANA_INIT] >>>>>>>>>>>>>>
7143 13:22:12.361586 <<<<<< [CONFIGURE PHASE]: ANA_TX
7144 13:22:12.364405 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7145 13:22:12.367729 ===================================
7146 13:22:12.371494 data_rate = 3200,PCW = 0X7600
7147 13:22:12.374438 ===================================
7148 13:22:12.378066 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7149 13:22:12.384477 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7150 13:22:12.387834 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7151 13:22:12.394131 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7152 13:22:12.397677 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7153 13:22:12.401200 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7154 13:22:12.401312 [ANA_INIT] flow start
7155 13:22:12.404642 [ANA_INIT] PLL >>>>>>>>
7156 13:22:12.407878 [ANA_INIT] PLL <<<<<<<<
7157 13:22:12.410845 [ANA_INIT] MIDPI >>>>>>>>
7158 13:22:12.410922 [ANA_INIT] MIDPI <<<<<<<<
7159 13:22:12.414230 [ANA_INIT] DLL >>>>>>>>
7160 13:22:12.417180 [ANA_INIT] DLL <<<<<<<<
7161 13:22:12.417289 [ANA_INIT] flow end
7162 13:22:12.421001 ============ LP4 DIFF to SE enter ============
7163 13:22:12.427741 ============ LP4 DIFF to SE exit ============
7164 13:22:12.427825 [ANA_INIT] <<<<<<<<<<<<<
7165 13:22:12.430934 [Flow] Enable top DCM control >>>>>
7166 13:22:12.433961 [Flow] Enable top DCM control <<<<<
7167 13:22:12.437442 Enable DLL master slave shuffle
7168 13:22:12.444019 ==============================================================
7169 13:22:12.444101 Gating Mode config
7170 13:22:12.450236 ==============================================================
7171 13:22:12.453776 Config description:
7172 13:22:12.463953 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7173 13:22:12.470132 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7174 13:22:12.473558 SELPH_MODE 0: By rank 1: By Phase
7175 13:22:12.480468 ==============================================================
7176 13:22:12.483356 GAT_TRACK_EN = 1
7177 13:22:12.487153 RX_GATING_MODE = 2
7178 13:22:12.490024 RX_GATING_TRACK_MODE = 2
7179 13:22:12.490124 SELPH_MODE = 1
7180 13:22:12.493728 PICG_EARLY_EN = 1
7181 13:22:12.497094 VALID_LAT_VALUE = 1
7182 13:22:12.503297 ==============================================================
7183 13:22:12.506943 Enter into Gating configuration >>>>
7184 13:22:12.510185 Exit from Gating configuration <<<<
7185 13:22:12.513552 Enter into DVFS_PRE_config >>>>>
7186 13:22:12.523660 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7187 13:22:12.526625 Exit from DVFS_PRE_config <<<<<
7188 13:22:12.530245 Enter into PICG configuration >>>>
7189 13:22:12.533007 Exit from PICG configuration <<<<
7190 13:22:12.536332 [RX_INPUT] configuration >>>>>
7191 13:22:12.539950 [RX_INPUT] configuration <<<<<
7192 13:22:12.543276 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7193 13:22:12.549588 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7194 13:22:12.556128 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7195 13:22:12.562812 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7196 13:22:12.569349 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7197 13:22:12.572537 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7198 13:22:12.579261 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7199 13:22:12.582575 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7200 13:22:12.585740 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7201 13:22:12.589034 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7202 13:22:12.596163 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7203 13:22:12.599543 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7204 13:22:12.602900 ===================================
7205 13:22:12.605838 LPDDR4 DRAM CONFIGURATION
7206 13:22:12.609620 ===================================
7207 13:22:12.609705 EX_ROW_EN[0] = 0x0
7208 13:22:12.612802 EX_ROW_EN[1] = 0x0
7209 13:22:12.612901 LP4Y_EN = 0x0
7210 13:22:12.615685 WORK_FSP = 0x1
7211 13:22:12.615767 WL = 0x5
7212 13:22:12.619192 RL = 0x5
7213 13:22:12.619290 BL = 0x2
7214 13:22:12.622491 RPST = 0x0
7215 13:22:12.625742 RD_PRE = 0x0
7216 13:22:12.625872 WR_PRE = 0x1
7217 13:22:12.629281 WR_PST = 0x1
7218 13:22:12.629364 DBI_WR = 0x0
7219 13:22:12.632246 DBI_RD = 0x0
7220 13:22:12.632328 OTF = 0x1
7221 13:22:12.635779 ===================================
7222 13:22:12.639346 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7223 13:22:12.645623 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7224 13:22:12.648981 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7225 13:22:12.652056 ===================================
7226 13:22:12.655292 LPDDR4 DRAM CONFIGURATION
7227 13:22:12.658791 ===================================
7228 13:22:12.658874 EX_ROW_EN[0] = 0x10
7229 13:22:12.661916 EX_ROW_EN[1] = 0x0
7230 13:22:12.661999 LP4Y_EN = 0x0
7231 13:22:12.665601 WORK_FSP = 0x1
7232 13:22:12.665684 WL = 0x5
7233 13:22:12.668692 RL = 0x5
7234 13:22:12.668800 BL = 0x2
7235 13:22:12.671839 RPST = 0x0
7236 13:22:12.675531 RD_PRE = 0x0
7237 13:22:12.675619 WR_PRE = 0x1
7238 13:22:12.678385 WR_PST = 0x1
7239 13:22:12.678490 DBI_WR = 0x0
7240 13:22:12.681544 DBI_RD = 0x0
7241 13:22:12.681626 OTF = 0x1
7242 13:22:12.685161 ===================================
7243 13:22:12.691754 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7244 13:22:12.691870 ==
7245 13:22:12.695245 Dram Type= 6, Freq= 0, CH_0, rank 0
7246 13:22:12.698729 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7247 13:22:12.698822 ==
7248 13:22:12.701704 [Duty_Offset_Calibration]
7249 13:22:12.705121 B0:2 B1:0 CA:3
7250 13:22:12.705219
7251 13:22:12.708532 [DutyScan_Calibration_Flow] k_type=0
7252 13:22:12.716879
7253 13:22:12.716959 ==CLK 0==
7254 13:22:12.720011 Final CLK duty delay cell = 0
7255 13:22:12.723172 [0] MAX Duty = 5031%(X100), DQS PI = 12
7256 13:22:12.726701 [0] MIN Duty = 4907%(X100), DQS PI = 2
7257 13:22:12.726787 [0] AVG Duty = 4969%(X100)
7258 13:22:12.729987
7259 13:22:12.733464 CH0 CLK Duty spec in!! Max-Min= 124%
7260 13:22:12.736932 [DutyScan_Calibration_Flow] ====Done====
7261 13:22:12.737046
7262 13:22:12.740172 [DutyScan_Calibration_Flow] k_type=1
7263 13:22:12.756954
7264 13:22:12.757047 ==DQS 0 ==
7265 13:22:12.759799 Final DQS duty delay cell = 0
7266 13:22:12.763349 [0] MAX Duty = 5094%(X100), DQS PI = 30
7267 13:22:12.766763 [0] MIN Duty = 4875%(X100), DQS PI = 50
7268 13:22:12.769782 [0] AVG Duty = 4984%(X100)
7269 13:22:12.769867
7270 13:22:12.769934 ==DQS 1 ==
7271 13:22:12.773560 Final DQS duty delay cell = 0
7272 13:22:12.776323 [0] MAX Duty = 5156%(X100), DQS PI = 32
7273 13:22:12.780177 [0] MIN Duty = 5031%(X100), DQS PI = 12
7274 13:22:12.783191 [0] AVG Duty = 5093%(X100)
7275 13:22:12.783276
7276 13:22:12.786615 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7277 13:22:12.786705
7278 13:22:12.789749 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7279 13:22:12.793432 [DutyScan_Calibration_Flow] ====Done====
7280 13:22:12.793522
7281 13:22:12.796270 [DutyScan_Calibration_Flow] k_type=3
7282 13:22:12.814618
7283 13:22:12.814710 ==DQM 0 ==
7284 13:22:12.817719 Final DQM duty delay cell = 0
7285 13:22:12.821357 [0] MAX Duty = 5156%(X100), DQS PI = 14
7286 13:22:12.824838 [0] MIN Duty = 4875%(X100), DQS PI = 0
7287 13:22:12.827941 [0] AVG Duty = 5015%(X100)
7288 13:22:12.828060
7289 13:22:12.828157 ==DQM 1 ==
7290 13:22:12.831344 Final DQM duty delay cell = 4
7291 13:22:12.834394 [4] MAX Duty = 5187%(X100), DQS PI = 60
7292 13:22:12.838193 [4] MIN Duty = 5000%(X100), DQS PI = 14
7293 13:22:12.841009 [4] AVG Duty = 5093%(X100)
7294 13:22:12.841095
7295 13:22:12.844252 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7296 13:22:12.844337
7297 13:22:12.847730 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7298 13:22:12.850836 [DutyScan_Calibration_Flow] ====Done====
7299 13:22:12.850921
7300 13:22:12.854324 [DutyScan_Calibration_Flow] k_type=2
7301 13:22:12.870913
7302 13:22:12.871001 ==DQ 0 ==
7303 13:22:12.874427 Final DQ duty delay cell = -4
7304 13:22:12.877600 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7305 13:22:12.880998 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7306 13:22:12.884078 [-4] AVG Duty = 4938%(X100)
7307 13:22:12.884162
7308 13:22:12.884230 ==DQ 1 ==
7309 13:22:12.887899 Final DQ duty delay cell = 0
7310 13:22:12.890835 [0] MAX Duty = 5156%(X100), DQS PI = 60
7311 13:22:12.894351 [0] MIN Duty = 5000%(X100), DQS PI = 16
7312 13:22:12.897630 [0] AVG Duty = 5078%(X100)
7313 13:22:12.897715
7314 13:22:12.900471 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7315 13:22:12.900555
7316 13:22:12.903899 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7317 13:22:12.907393 [DutyScan_Calibration_Flow] ====Done====
7318 13:22:12.907478 ==
7319 13:22:12.910507 Dram Type= 6, Freq= 0, CH_1, rank 0
7320 13:22:12.914171 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7321 13:22:12.914255 ==
7322 13:22:12.917021 [Duty_Offset_Calibration]
7323 13:22:12.917106 B0:1 B1:-2 CA:0
7324 13:22:12.917172
7325 13:22:12.920680 [DutyScan_Calibration_Flow] k_type=0
7326 13:22:12.931773
7327 13:22:12.931862 ==CLK 0==
7328 13:22:12.935208 Final CLK duty delay cell = 0
7329 13:22:12.938198 [0] MAX Duty = 5062%(X100), DQS PI = 20
7330 13:22:12.941561 [0] MIN Duty = 4813%(X100), DQS PI = 60
7331 13:22:12.944908 [0] AVG Duty = 4937%(X100)
7332 13:22:12.944993
7333 13:22:12.948059 CH1 CLK Duty spec in!! Max-Min= 249%
7334 13:22:12.951438 [DutyScan_Calibration_Flow] ====Done====
7335 13:22:12.951522
7336 13:22:12.954487 [DutyScan_Calibration_Flow] k_type=1
7337 13:22:12.970372
7338 13:22:12.970468 ==DQS 0 ==
7339 13:22:12.973834 Final DQS duty delay cell = -4
7340 13:22:12.976995 [-4] MAX Duty = 5000%(X100), DQS PI = 28
7341 13:22:12.980678 [-4] MIN Duty = 4844%(X100), DQS PI = 44
7342 13:22:12.984023 [-4] AVG Duty = 4922%(X100)
7343 13:22:12.984106
7344 13:22:12.984171 ==DQS 1 ==
7345 13:22:12.987477 Final DQS duty delay cell = 0
7346 13:22:12.990243 [0] MAX Duty = 5062%(X100), DQS PI = 0
7347 13:22:12.993589 [0] MIN Duty = 4844%(X100), DQS PI = 24
7348 13:22:12.997073 [0] AVG Duty = 4953%(X100)
7349 13:22:12.997155
7350 13:22:13.000607 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7351 13:22:13.000691
7352 13:22:13.003411 CH1 DQS 1 Duty spec in!! Max-Min= 218%
7353 13:22:13.006988 [DutyScan_Calibration_Flow] ====Done====
7354 13:22:13.007070
7355 13:22:13.010088 [DutyScan_Calibration_Flow] k_type=3
7356 13:22:13.027930
7357 13:22:13.028048 ==DQM 0 ==
7358 13:22:13.031060 Final DQM duty delay cell = 0
7359 13:22:13.034646 [0] MAX Duty = 5031%(X100), DQS PI = 24
7360 13:22:13.038104 [0] MIN Duty = 4813%(X100), DQS PI = 56
7361 13:22:13.040988 [0] AVG Duty = 4922%(X100)
7362 13:22:13.041073
7363 13:22:13.041140 ==DQM 1 ==
7364 13:22:13.044397 Final DQM duty delay cell = 0
7365 13:22:13.047711 [0] MAX Duty = 5062%(X100), DQS PI = 34
7366 13:22:13.051147 [0] MIN Duty = 4875%(X100), DQS PI = 26
7367 13:22:13.054643 [0] AVG Duty = 4968%(X100)
7368 13:22:13.054729
7369 13:22:13.057634 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7370 13:22:13.057712
7371 13:22:13.061304 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7372 13:22:13.064282 [DutyScan_Calibration_Flow] ====Done====
7373 13:22:13.064359
7374 13:22:13.068087 [DutyScan_Calibration_Flow] k_type=2
7375 13:22:13.085149
7376 13:22:13.085240 ==DQ 0 ==
7377 13:22:13.088376 Final DQ duty delay cell = 0
7378 13:22:13.091184 [0] MAX Duty = 5093%(X100), DQS PI = 22
7379 13:22:13.094706 [0] MIN Duty = 4907%(X100), DQS PI = 62
7380 13:22:13.094790 [0] AVG Duty = 5000%(X100)
7381 13:22:13.098098
7382 13:22:13.098180 ==DQ 1 ==
7383 13:22:13.101577 Final DQ duty delay cell = 0
7384 13:22:13.104895 [0] MAX Duty = 5125%(X100), DQS PI = 34
7385 13:22:13.107844 [0] MIN Duty = 4969%(X100), DQS PI = 24
7386 13:22:13.107938 [0] AVG Duty = 5047%(X100)
7387 13:22:13.108004
7388 13:22:13.111529 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7389 13:22:13.114425
7390 13:22:13.118315 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7391 13:22:13.121042 [DutyScan_Calibration_Flow] ====Done====
7392 13:22:13.124314 nWR fixed to 30
7393 13:22:13.124409 [ModeRegInit_LP4] CH0 RK0
7394 13:22:13.127810 [ModeRegInit_LP4] CH0 RK1
7395 13:22:13.130921 [ModeRegInit_LP4] CH1 RK0
7396 13:22:13.134511 [ModeRegInit_LP4] CH1 RK1
7397 13:22:13.134601 match AC timing 5
7398 13:22:13.140974 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7399 13:22:13.144191 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7400 13:22:13.147532 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7401 13:22:13.154189 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7402 13:22:13.157399 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7403 13:22:13.157488 [MiockJmeterHQA]
7404 13:22:13.157555
7405 13:22:13.160849 [DramcMiockJmeter] u1RxGatingPI = 0
7406 13:22:13.164323 0 : 4252, 4027
7407 13:22:13.164403 4 : 4253, 4026
7408 13:22:13.167342 8 : 4254, 4029
7409 13:22:13.167429 12 : 4252, 4027
7410 13:22:13.167495 16 : 4253, 4027
7411 13:22:13.171004 20 : 4253, 4027
7412 13:22:13.171074 24 : 4253, 4027
7413 13:22:13.174337 28 : 4365, 4140
7414 13:22:13.174422 32 : 4252, 4027
7415 13:22:13.177789 36 : 4254, 4029
7416 13:22:13.177874 40 : 4253, 4026
7417 13:22:13.180882 44 : 4363, 4140
7418 13:22:13.180968 48 : 4252, 4027
7419 13:22:13.181036 52 : 4361, 4137
7420 13:22:13.183917 56 : 4253, 4027
7421 13:22:13.184003 60 : 4250, 4027
7422 13:22:13.187464 64 : 4250, 4027
7423 13:22:13.187550 68 : 4252, 4029
7424 13:22:13.190914 72 : 4250, 4026
7425 13:22:13.191001 76 : 4249, 4027
7426 13:22:13.194081 80 : 4363, 4140
7427 13:22:13.194167 84 : 4250, 4027
7428 13:22:13.194235 88 : 4252, 4029
7429 13:22:13.197887 92 : 4250, 4026
7430 13:22:13.197972 96 : 4360, 4138
7431 13:22:13.200559 100 : 4249, 4027
7432 13:22:13.200644 104 : 4250, 3465
7433 13:22:13.204099 108 : 4250, 0
7434 13:22:13.204184 112 : 4361, 0
7435 13:22:13.204253 116 : 4252, 0
7436 13:22:13.207696 120 : 4250, 0
7437 13:22:13.207782 124 : 4250, 0
7438 13:22:13.210541 128 : 4250, 0
7439 13:22:13.210627 132 : 4360, 0
7440 13:22:13.210695 136 : 4250, 0
7441 13:22:13.213805 140 : 4250, 0
7442 13:22:13.213891 144 : 4361, 0
7443 13:22:13.213959 148 : 4360, 0
7444 13:22:13.217495 152 : 4363, 0
7445 13:22:13.217582 156 : 4250, 0
7446 13:22:13.221194 160 : 4360, 0
7447 13:22:13.221282 164 : 4361, 0
7448 13:22:13.221351 168 : 4250, 0
7449 13:22:13.224047 172 : 4250, 0
7450 13:22:13.224135 176 : 4250, 0
7451 13:22:13.227546 180 : 4253, 0
7452 13:22:13.227634 184 : 4250, 0
7453 13:22:13.227703 188 : 4360, 0
7454 13:22:13.230612 192 : 4250, 0
7455 13:22:13.230698 196 : 4361, 0
7456 13:22:13.234192 200 : 4361, 0
7457 13:22:13.234294 204 : 4363, 0
7458 13:22:13.234364 208 : 4250, 0
7459 13:22:13.237298 212 : 4250, 0
7460 13:22:13.237385 216 : 4250, 0
7461 13:22:13.237453 220 : 4252, 0
7462 13:22:13.240870 224 : 4250, 0
7463 13:22:13.240959 228 : 4250, 0
7464 13:22:13.243895 232 : 4252, 1
7465 13:22:13.243982 236 : 4250, 1109
7466 13:22:13.247091 240 : 4249, 4027
7467 13:22:13.247177 244 : 4360, 4137
7468 13:22:13.250688 248 : 4252, 4029
7469 13:22:13.250787 252 : 4250, 4027
7470 13:22:13.250858 256 : 4250, 4027
7471 13:22:13.253580 260 : 4252, 4029
7472 13:22:13.253672 264 : 4250, 4026
7473 13:22:13.257042 268 : 4250, 4027
7474 13:22:13.257130 272 : 4249, 4027
7475 13:22:13.260354 276 : 4250, 4027
7476 13:22:13.260434 280 : 4250, 4026
7477 13:22:13.263605 284 : 4360, 4138
7478 13:22:13.263696 288 : 4360, 4138
7479 13:22:13.266923 292 : 4250, 4026
7480 13:22:13.267006 296 : 4363, 4140
7481 13:22:13.270353 300 : 4360, 4138
7482 13:22:13.270469 304 : 4250, 4027
7483 13:22:13.274233 308 : 4250, 4027
7484 13:22:13.274314 312 : 4252, 4029
7485 13:22:13.274391 316 : 4250, 4027
7486 13:22:13.276805 320 : 4250, 4027
7487 13:22:13.276910 324 : 4250, 4027
7488 13:22:13.280541 328 : 4252, 4029
7489 13:22:13.280621 332 : 4250, 4026
7490 13:22:13.283473 336 : 4360, 4138
7491 13:22:13.283549 340 : 4360, 4138
7492 13:22:13.286654 344 : 4250, 4027
7493 13:22:13.286732 348 : 4363, 4139
7494 13:22:13.290335 352 : 4360, 4111
7495 13:22:13.290445 356 : 4250, 2752
7496 13:22:13.293892 360 : 4250, 0
7497 13:22:13.293969
7498 13:22:13.294032 MIOCK jitter meter ch=0
7499 13:22:13.294094
7500 13:22:13.297007 1T = (360-108) = 252 dly cells
7501 13:22:13.303581 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7502 13:22:13.303660 ==
7503 13:22:13.307182 Dram Type= 6, Freq= 0, CH_0, rank 0
7504 13:22:13.310153 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7505 13:22:13.310231 ==
7506 13:22:13.316626 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7507 13:22:13.320441 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7508 13:22:13.323170 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7509 13:22:13.330312 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7510 13:22:13.339736 [CA 0] Center 44 (14~75) winsize 62
7511 13:22:13.343106 [CA 1] Center 43 (13~74) winsize 62
7512 13:22:13.346352 [CA 2] Center 40 (11~69) winsize 59
7513 13:22:13.349842 [CA 3] Center 39 (10~68) winsize 59
7514 13:22:13.352755 [CA 4] Center 37 (8~67) winsize 60
7515 13:22:13.356150 [CA 5] Center 37 (7~67) winsize 61
7516 13:22:13.356245
7517 13:22:13.359624 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7518 13:22:13.359702
7519 13:22:13.366092 [CATrainingPosCal] consider 1 rank data
7520 13:22:13.366174 u2DelayCellTimex100 = 258/100 ps
7521 13:22:13.372555 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7522 13:22:13.376022 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7523 13:22:13.379561 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7524 13:22:13.382734 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7525 13:22:13.386096 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7526 13:22:13.389606 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7527 13:22:13.389686
7528 13:22:13.393328 CA PerBit enable=1, Macro0, CA PI delay=37
7529 13:22:13.393419
7530 13:22:13.396088 [CBTSetCACLKResult] CA Dly = 37
7531 13:22:13.399415 CS Dly: 11 (0~42)
7532 13:22:13.402868 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7533 13:22:13.405988 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7534 13:22:13.406076 ==
7535 13:22:13.409496 Dram Type= 6, Freq= 0, CH_0, rank 1
7536 13:22:13.416151 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7537 13:22:13.416243 ==
7538 13:22:13.419201 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7539 13:22:13.422766 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7540 13:22:13.429364 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7541 13:22:13.435941 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7542 13:22:13.443799 [CA 0] Center 44 (14~75) winsize 62
7543 13:22:13.447026 [CA 1] Center 43 (13~74) winsize 62
7544 13:22:13.450327 [CA 2] Center 39 (10~69) winsize 60
7545 13:22:13.453433 [CA 3] Center 39 (10~69) winsize 60
7546 13:22:13.456574 [CA 4] Center 37 (8~67) winsize 60
7547 13:22:13.460336 [CA 5] Center 37 (7~67) winsize 61
7548 13:22:13.460421
7549 13:22:13.463203 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7550 13:22:13.463288
7551 13:22:13.470257 [CATrainingPosCal] consider 2 rank data
7552 13:22:13.470343 u2DelayCellTimex100 = 258/100 ps
7553 13:22:13.476586 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7554 13:22:13.480146 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7555 13:22:13.483171 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7556 13:22:13.486815 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7557 13:22:13.489910 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7558 13:22:13.493159 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7559 13:22:13.493245
7560 13:22:13.496528 CA PerBit enable=1, Macro0, CA PI delay=37
7561 13:22:13.496615
7562 13:22:13.499997 [CBTSetCACLKResult] CA Dly = 37
7563 13:22:13.503402 CS Dly: 11 (0~43)
7564 13:22:13.506639 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7565 13:22:13.510083 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7566 13:22:13.510171
7567 13:22:13.513515 ----->DramcWriteLeveling(PI) begin...
7568 13:22:13.513601 ==
7569 13:22:13.516265 Dram Type= 6, Freq= 0, CH_0, rank 0
7570 13:22:13.522901 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7571 13:22:13.522986 ==
7572 13:22:13.526509 Write leveling (Byte 0): 35 => 35
7573 13:22:13.529759 Write leveling (Byte 1): 27 => 27
7574 13:22:13.529844 DramcWriteLeveling(PI) end<-----
7575 13:22:13.533102
7576 13:22:13.533186 ==
7577 13:22:13.536000 Dram Type= 6, Freq= 0, CH_0, rank 0
7578 13:22:13.539581 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7579 13:22:13.539666 ==
7580 13:22:13.542929 [Gating] SW mode calibration
7581 13:22:13.549471 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7582 13:22:13.552873 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7583 13:22:13.559468 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7584 13:22:13.562611 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7585 13:22:13.565861 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 13:22:13.572485 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7587 13:22:13.576010 1 4 16 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
7588 13:22:13.579063 1 4 20 | B1->B0 | 2525 3434 | 1 1 | (1 1) (1 1)
7589 13:22:13.585563 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7590 13:22:13.589029 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7591 13:22:13.592669 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7592 13:22:13.598799 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7593 13:22:13.602790 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7594 13:22:13.605859 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7595 13:22:13.612050 1 5 16 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
7596 13:22:13.615318 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
7597 13:22:13.619028 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
7598 13:22:13.625786 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7599 13:22:13.628870 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 13:22:13.631965 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 13:22:13.638671 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 13:22:13.642369 1 6 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7603 13:22:13.645337 1 6 16 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
7604 13:22:13.652165 1 6 20 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
7605 13:22:13.655353 1 6 24 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
7606 13:22:13.658456 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7607 13:22:13.665176 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 13:22:13.668274 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 13:22:13.671706 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 13:22:13.678796 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 13:22:13.681439 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7612 13:22:13.684855 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7613 13:22:13.691743 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7614 13:22:13.695081 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 13:22:13.698991 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 13:22:13.704741 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 13:22:13.708373 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 13:22:13.711611 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 13:22:13.718601 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 13:22:13.721558 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 13:22:13.724824 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 13:22:13.731293 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 13:22:13.734469 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 13:22:13.738146 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 13:22:13.744734 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 13:22:13.747698 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 13:22:13.751367 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7628 13:22:13.757945 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7629 13:22:13.758037 Total UI for P1: 0, mck2ui 16
7630 13:22:13.764410 best dqsien dly found for B0: ( 1, 9, 16)
7631 13:22:13.767677 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7632 13:22:13.770848 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7633 13:22:13.773940 Total UI for P1: 0, mck2ui 16
7634 13:22:13.777443 best dqsien dly found for B1: ( 1, 9, 22)
7635 13:22:13.781009 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7636 13:22:13.784334 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7637 13:22:13.784421
7638 13:22:13.790670 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7639 13:22:13.793866 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7640 13:22:13.797216 [Gating] SW calibration Done
7641 13:22:13.797290 ==
7642 13:22:13.800374 Dram Type= 6, Freq= 0, CH_0, rank 0
7643 13:22:13.803619 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7644 13:22:13.803722 ==
7645 13:22:13.803816 RX Vref Scan: 0
7646 13:22:13.803909
7647 13:22:13.807266 RX Vref 0 -> 0, step: 1
7648 13:22:13.807366
7649 13:22:13.810416 RX Delay 0 -> 252, step: 8
7650 13:22:13.813442 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7651 13:22:13.817216 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7652 13:22:13.823793 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7653 13:22:13.827086 iDelay=200, Bit 3, Center 123 (72 ~ 175) 104
7654 13:22:13.830068 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
7655 13:22:13.833397 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
7656 13:22:13.836581 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7657 13:22:13.843675 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7658 13:22:13.846532 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7659 13:22:13.850105 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7660 13:22:13.853244 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7661 13:22:13.856654 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7662 13:22:13.863366 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7663 13:22:13.866406 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7664 13:22:13.869934 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7665 13:22:13.873191 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7666 13:22:13.873294 ==
7667 13:22:13.876485 Dram Type= 6, Freq= 0, CH_0, rank 0
7668 13:22:13.882950 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7669 13:22:13.883071 ==
7670 13:22:13.883171 DQS Delay:
7671 13:22:13.886422 DQS0 = 0, DQS1 = 0
7672 13:22:13.886524 DQM Delay:
7673 13:22:13.886594 DQM0 = 129, DQM1 = 124
7674 13:22:13.889807 DQ Delay:
7675 13:22:13.893410 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7676 13:22:13.896279 DQ4 =131, DQ5 =111, DQ6 =139, DQ7 =143
7677 13:22:13.899947 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7678 13:22:13.902824 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7679 13:22:13.902900
7680 13:22:13.902963
7681 13:22:13.903022 ==
7682 13:22:13.905869 Dram Type= 6, Freq= 0, CH_0, rank 0
7683 13:22:13.912753 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7684 13:22:13.912837 ==
7685 13:22:13.912902
7686 13:22:13.912962
7687 13:22:13.913020 TX Vref Scan disable
7688 13:22:13.916213 == TX Byte 0 ==
7689 13:22:13.919316 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7690 13:22:13.925871 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7691 13:22:13.925954 == TX Byte 1 ==
7692 13:22:13.929555 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7693 13:22:13.936054 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7694 13:22:13.936139 ==
7695 13:22:13.939269 Dram Type= 6, Freq= 0, CH_0, rank 0
7696 13:22:13.942590 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7697 13:22:13.942669 ==
7698 13:22:13.956073
7699 13:22:13.959068 TX Vref early break, caculate TX vref
7700 13:22:13.963003 TX Vref=16, minBit 8, minWin=20, winSum=357
7701 13:22:13.965684 TX Vref=18, minBit 11, minWin=21, winSum=366
7702 13:22:13.969394 TX Vref=20, minBit 8, minWin=22, winSum=375
7703 13:22:13.972774 TX Vref=22, minBit 4, minWin=23, winSum=386
7704 13:22:13.975961 TX Vref=24, minBit 4, minWin=24, winSum=396
7705 13:22:13.982368 TX Vref=26, minBit 4, minWin=24, winSum=403
7706 13:22:13.985730 TX Vref=28, minBit 0, minWin=25, winSum=407
7707 13:22:13.989411 TX Vref=30, minBit 8, minWin=23, winSum=401
7708 13:22:13.992618 TX Vref=32, minBit 9, minWin=22, winSum=390
7709 13:22:13.995865 TX Vref=34, minBit 8, minWin=21, winSum=379
7710 13:22:14.002606 [TxChooseVref] Worse bit 0, Min win 25, Win sum 407, Final Vref 28
7711 13:22:14.002690
7712 13:22:14.005682 Final TX Range 0 Vref 28
7713 13:22:14.005765
7714 13:22:14.005828 ==
7715 13:22:14.009186 Dram Type= 6, Freq= 0, CH_0, rank 0
7716 13:22:14.012246 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7717 13:22:14.012320 ==
7718 13:22:14.012383
7719 13:22:14.012441
7720 13:22:14.015318 TX Vref Scan disable
7721 13:22:14.021994 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7722 13:22:14.022073 == TX Byte 0 ==
7723 13:22:14.025520 u2DelayCellOfst[0]=15 cells (4 PI)
7724 13:22:14.029077 u2DelayCellOfst[1]=18 cells (5 PI)
7725 13:22:14.032560 u2DelayCellOfst[2]=15 cells (4 PI)
7726 13:22:14.035251 u2DelayCellOfst[3]=15 cells (4 PI)
7727 13:22:14.039127 u2DelayCellOfst[4]=7 cells (2 PI)
7728 13:22:14.042228 u2DelayCellOfst[5]=0 cells (0 PI)
7729 13:22:14.045625 u2DelayCellOfst[6]=22 cells (6 PI)
7730 13:22:14.048815 u2DelayCellOfst[7]=18 cells (5 PI)
7731 13:22:14.052229 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7732 13:22:14.055549 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7733 13:22:14.058835 == TX Byte 1 ==
7734 13:22:14.062037 u2DelayCellOfst[8]=0 cells (0 PI)
7735 13:22:14.062142 u2DelayCellOfst[9]=3 cells (1 PI)
7736 13:22:14.065490 u2DelayCellOfst[10]=7 cells (2 PI)
7737 13:22:14.068614 u2DelayCellOfst[11]=7 cells (2 PI)
7738 13:22:14.072198 u2DelayCellOfst[12]=11 cells (3 PI)
7739 13:22:14.075149 u2DelayCellOfst[13]=11 cells (3 PI)
7740 13:22:14.078757 u2DelayCellOfst[14]=15 cells (4 PI)
7741 13:22:14.081869 u2DelayCellOfst[15]=11 cells (3 PI)
7742 13:22:14.085129 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7743 13:22:14.091984 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7744 13:22:14.092061 DramC Write-DBI on
7745 13:22:14.092125 ==
7746 13:22:14.095387 Dram Type= 6, Freq= 0, CH_0, rank 0
7747 13:22:14.098537 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7748 13:22:14.101741 ==
7749 13:22:14.101845
7750 13:22:14.101927
7751 13:22:14.102001 TX Vref Scan disable
7752 13:22:14.105450 == TX Byte 0 ==
7753 13:22:14.108835 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7754 13:22:14.112384 == TX Byte 1 ==
7755 13:22:14.115346 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7756 13:22:14.119251 DramC Write-DBI off
7757 13:22:14.119352
7758 13:22:14.119482 [DATLAT]
7759 13:22:14.119545 Freq=1600, CH0 RK0
7760 13:22:14.119603
7761 13:22:14.122138 DATLAT Default: 0xf
7762 13:22:14.122234 0, 0xFFFF, sum = 0
7763 13:22:14.125610 1, 0xFFFF, sum = 0
7764 13:22:14.128679 2, 0xFFFF, sum = 0
7765 13:22:14.128784 3, 0xFFFF, sum = 0
7766 13:22:14.132591 4, 0xFFFF, sum = 0
7767 13:22:14.132691 5, 0xFFFF, sum = 0
7768 13:22:14.135304 6, 0xFFFF, sum = 0
7769 13:22:14.135461 7, 0xFFFF, sum = 0
7770 13:22:14.138579 8, 0xFFFF, sum = 0
7771 13:22:14.138661 9, 0xFFFF, sum = 0
7772 13:22:14.142139 10, 0xFFFF, sum = 0
7773 13:22:14.142243 11, 0xFFFF, sum = 0
7774 13:22:14.145621 12, 0xFFFF, sum = 0
7775 13:22:14.145724 13, 0xEFFF, sum = 0
7776 13:22:14.149033 14, 0x0, sum = 1
7777 13:22:14.149137 15, 0x0, sum = 2
7778 13:22:14.151895 16, 0x0, sum = 3
7779 13:22:14.151975 17, 0x0, sum = 4
7780 13:22:14.155344 best_step = 15
7781 13:22:14.155452
7782 13:22:14.155514 ==
7783 13:22:14.158385 Dram Type= 6, Freq= 0, CH_0, rank 0
7784 13:22:14.161829 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7785 13:22:14.161938 ==
7786 13:22:14.165338 RX Vref Scan: 1
7787 13:22:14.165447
7788 13:22:14.165545 Set Vref Range= 24 -> 127
7789 13:22:14.165634
7790 13:22:14.168279 RX Vref 24 -> 127, step: 1
7791 13:22:14.168384
7792 13:22:14.171669 RX Delay 11 -> 252, step: 4
7793 13:22:14.171788
7794 13:22:14.175390 Set Vref, RX VrefLevel [Byte0]: 24
7795 13:22:14.178273 [Byte1]: 24
7796 13:22:14.178381
7797 13:22:14.182178 Set Vref, RX VrefLevel [Byte0]: 25
7798 13:22:14.185160 [Byte1]: 25
7799 13:22:14.188971
7800 13:22:14.189046 Set Vref, RX VrefLevel [Byte0]: 26
7801 13:22:14.191654 [Byte1]: 26
7802 13:22:14.195794
7803 13:22:14.195900 Set Vref, RX VrefLevel [Byte0]: 27
7804 13:22:14.199474 [Byte1]: 27
7805 13:22:14.203376
7806 13:22:14.203468 Set Vref, RX VrefLevel [Byte0]: 28
7807 13:22:14.207293 [Byte1]: 28
7808 13:22:14.211123
7809 13:22:14.211238 Set Vref, RX VrefLevel [Byte0]: 29
7810 13:22:14.214773 [Byte1]: 29
7811 13:22:14.218902
7812 13:22:14.218987 Set Vref, RX VrefLevel [Byte0]: 30
7813 13:22:14.221893 [Byte1]: 30
7814 13:22:14.226700
7815 13:22:14.226802 Set Vref, RX VrefLevel [Byte0]: 31
7816 13:22:14.230059 [Byte1]: 31
7817 13:22:14.234015
7818 13:22:14.234122 Set Vref, RX VrefLevel [Byte0]: 32
7819 13:22:14.237713 [Byte1]: 32
7820 13:22:14.241784
7821 13:22:14.241899 Set Vref, RX VrefLevel [Byte0]: 33
7822 13:22:14.245001 [Byte1]: 33
7823 13:22:14.249180
7824 13:22:14.249304 Set Vref, RX VrefLevel [Byte0]: 34
7825 13:22:14.252400 [Byte1]: 34
7826 13:22:14.256796
7827 13:22:14.256922 Set Vref, RX VrefLevel [Byte0]: 35
7828 13:22:14.260012 [Byte1]: 35
7829 13:22:14.264525
7830 13:22:14.264598 Set Vref, RX VrefLevel [Byte0]: 36
7831 13:22:14.267805 [Byte1]: 36
7832 13:22:14.272119
7833 13:22:14.272247 Set Vref, RX VrefLevel [Byte0]: 37
7834 13:22:14.275636 [Byte1]: 37
7835 13:22:14.279602
7836 13:22:14.279677 Set Vref, RX VrefLevel [Byte0]: 38
7837 13:22:14.283211 [Byte1]: 38
7838 13:22:14.287481
7839 13:22:14.287577 Set Vref, RX VrefLevel [Byte0]: 39
7840 13:22:14.290363 [Byte1]: 39
7841 13:22:14.294870
7842 13:22:14.294967 Set Vref, RX VrefLevel [Byte0]: 40
7843 13:22:14.298532 [Byte1]: 40
7844 13:22:14.302632
7845 13:22:14.302740 Set Vref, RX VrefLevel [Byte0]: 41
7846 13:22:14.305540 [Byte1]: 41
7847 13:22:14.309914
7848 13:22:14.310019 Set Vref, RX VrefLevel [Byte0]: 42
7849 13:22:14.313416 [Byte1]: 42
7850 13:22:14.317795
7851 13:22:14.317922 Set Vref, RX VrefLevel [Byte0]: 43
7852 13:22:14.321144 [Byte1]: 43
7853 13:22:14.325496
7854 13:22:14.325613 Set Vref, RX VrefLevel [Byte0]: 44
7855 13:22:14.329019 [Byte1]: 44
7856 13:22:14.332876
7857 13:22:14.332992 Set Vref, RX VrefLevel [Byte0]: 45
7858 13:22:14.336317 [Byte1]: 45
7859 13:22:14.340480
7860 13:22:14.340593 Set Vref, RX VrefLevel [Byte0]: 46
7861 13:22:14.343886 [Byte1]: 46
7862 13:22:14.348270
7863 13:22:14.348425 Set Vref, RX VrefLevel [Byte0]: 47
7864 13:22:14.351297 [Byte1]: 47
7865 13:22:14.355968
7866 13:22:14.356074 Set Vref, RX VrefLevel [Byte0]: 48
7867 13:22:14.359101 [Byte1]: 48
7868 13:22:14.363249
7869 13:22:14.363357 Set Vref, RX VrefLevel [Byte0]: 49
7870 13:22:14.366699 [Byte1]: 49
7871 13:22:14.371023
7872 13:22:14.371107 Set Vref, RX VrefLevel [Byte0]: 50
7873 13:22:14.374593 [Byte1]: 50
7874 13:22:14.378491
7875 13:22:14.378576 Set Vref, RX VrefLevel [Byte0]: 51
7876 13:22:14.381826 [Byte1]: 51
7877 13:22:14.386245
7878 13:22:14.386329 Set Vref, RX VrefLevel [Byte0]: 52
7879 13:22:14.389299 [Byte1]: 52
7880 13:22:14.393595
7881 13:22:14.393684 Set Vref, RX VrefLevel [Byte0]: 53
7882 13:22:14.397253 [Byte1]: 53
7883 13:22:14.401453
7884 13:22:14.401532 Set Vref, RX VrefLevel [Byte0]: 54
7885 13:22:14.404657 [Byte1]: 54
7886 13:22:14.408891
7887 13:22:14.408975 Set Vref, RX VrefLevel [Byte0]: 55
7888 13:22:14.412166 [Byte1]: 55
7889 13:22:14.416484
7890 13:22:14.416560 Set Vref, RX VrefLevel [Byte0]: 56
7891 13:22:14.419960 [Byte1]: 56
7892 13:22:14.424406
7893 13:22:14.424482 Set Vref, RX VrefLevel [Byte0]: 57
7894 13:22:14.427763 [Byte1]: 57
7895 13:22:14.432360
7896 13:22:14.432434 Set Vref, RX VrefLevel [Byte0]: 58
7897 13:22:14.435149 [Byte1]: 58
7898 13:22:14.439415
7899 13:22:14.439489 Set Vref, RX VrefLevel [Byte0]: 59
7900 13:22:14.443058 [Byte1]: 59
7901 13:22:14.447230
7902 13:22:14.447329 Set Vref, RX VrefLevel [Byte0]: 60
7903 13:22:14.450314 [Byte1]: 60
7904 13:22:14.455081
7905 13:22:14.455168 Set Vref, RX VrefLevel [Byte0]: 61
7906 13:22:14.458088 [Byte1]: 61
7907 13:22:14.462113
7908 13:22:14.462196 Set Vref, RX VrefLevel [Byte0]: 62
7909 13:22:14.466056 [Byte1]: 62
7910 13:22:14.469989
7911 13:22:14.470111 Set Vref, RX VrefLevel [Byte0]: 63
7912 13:22:14.473680 [Byte1]: 63
7913 13:22:14.477764
7914 13:22:14.477838 Set Vref, RX VrefLevel [Byte0]: 64
7915 13:22:14.481072 [Byte1]: 64
7916 13:22:14.485007
7917 13:22:14.485099 Set Vref, RX VrefLevel [Byte0]: 65
7918 13:22:14.488514 [Byte1]: 65
7919 13:22:14.492631
7920 13:22:14.492727 Set Vref, RX VrefLevel [Byte0]: 66
7921 13:22:14.496545 [Byte1]: 66
7922 13:22:14.500483
7923 13:22:14.500584 Set Vref, RX VrefLevel [Byte0]: 67
7924 13:22:14.504065 [Byte1]: 67
7925 13:22:14.508255
7926 13:22:14.508353 Set Vref, RX VrefLevel [Byte0]: 68
7927 13:22:14.511672 [Byte1]: 68
7928 13:22:14.515863
7929 13:22:14.515970 Set Vref, RX VrefLevel [Byte0]: 69
7930 13:22:14.518713 [Byte1]: 69
7931 13:22:14.523195
7932 13:22:14.523301 Set Vref, RX VrefLevel [Byte0]: 70
7933 13:22:14.526514 [Byte1]: 70
7934 13:22:14.531032
7935 13:22:14.531134 Set Vref, RX VrefLevel [Byte0]: 71
7936 13:22:14.534289 [Byte1]: 71
7937 13:22:14.538258
7938 13:22:14.538360 Set Vref, RX VrefLevel [Byte0]: 72
7939 13:22:14.542184 [Byte1]: 72
7940 13:22:14.546096
7941 13:22:14.546175 Set Vref, RX VrefLevel [Byte0]: 73
7942 13:22:14.549802 [Byte1]: 73
7943 13:22:14.554045
7944 13:22:14.554134 Set Vref, RX VrefLevel [Byte0]: 74
7945 13:22:14.556851 [Byte1]: 74
7946 13:22:14.561071
7947 13:22:14.561149 Set Vref, RX VrefLevel [Byte0]: 75
7948 13:22:14.564637 [Byte1]: 75
7949 13:22:14.568970
7950 13:22:14.569043 Set Vref, RX VrefLevel [Byte0]: 76
7951 13:22:14.572153 [Byte1]: 76
7952 13:22:14.576737
7953 13:22:14.576812 Set Vref, RX VrefLevel [Byte0]: 77
7954 13:22:14.579657 [Byte1]: 77
7955 13:22:14.584286
7956 13:22:14.584368 Final RX Vref Byte 0 = 63 to rank0
7957 13:22:14.587650 Final RX Vref Byte 1 = 61 to rank0
7958 13:22:14.591035 Final RX Vref Byte 0 = 63 to rank1
7959 13:22:14.593932 Final RX Vref Byte 1 = 61 to rank1==
7960 13:22:14.597372 Dram Type= 6, Freq= 0, CH_0, rank 0
7961 13:22:14.604164 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7962 13:22:14.604271 ==
7963 13:22:14.604369 DQS Delay:
7964 13:22:14.604460 DQS0 = 0, DQS1 = 0
7965 13:22:14.607267 DQM Delay:
7966 13:22:14.607375 DQM0 = 126, DQM1 = 120
7967 13:22:14.610612 DQ Delay:
7968 13:22:14.614228 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7969 13:22:14.617433 DQ4 =126, DQ5 =112, DQ6 =132, DQ7 =138
7970 13:22:14.620853 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7971 13:22:14.623981 DQ12 =126, DQ13 =124, DQ14 =132, DQ15 =128
7972 13:22:14.624053
7973 13:22:14.624115
7974 13:22:14.624175
7975 13:22:14.627089 [DramC_TX_OE_Calibration] TA2
7976 13:22:14.630384 Original DQ_B0 (3 6) =30, OEN = 27
7977 13:22:14.633687 Original DQ_B1 (3 6) =30, OEN = 27
7978 13:22:14.637174 24, 0x0, End_B0=24 End_B1=24
7979 13:22:14.637250 25, 0x0, End_B0=25 End_B1=25
7980 13:22:14.640852 26, 0x0, End_B0=26 End_B1=26
7981 13:22:14.644223 27, 0x0, End_B0=27 End_B1=27
7982 13:22:14.646960 28, 0x0, End_B0=28 End_B1=28
7983 13:22:14.650491 29, 0x0, End_B0=29 End_B1=29
7984 13:22:14.650571 30, 0x0, End_B0=30 End_B1=30
7985 13:22:14.653934 31, 0x4141, End_B0=30 End_B1=30
7986 13:22:14.657267 Byte0 end_step=30 best_step=27
7987 13:22:14.660722 Byte1 end_step=30 best_step=27
7988 13:22:14.663891 Byte0 TX OE(2T, 0.5T) = (3, 3)
7989 13:22:14.667086 Byte1 TX OE(2T, 0.5T) = (3, 3)
7990 13:22:14.667194
7991 13:22:14.667312
7992 13:22:14.673634 [DQSOSCAuto] RK0, (LSB)MR18= 0x1515, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
7993 13:22:14.677138 CH0 RK0: MR19=303, MR18=1515
7994 13:22:14.683693 CH0_RK0: MR19=0x303, MR18=0x1515, DQSOSC=399, MR23=63, INC=23, DEC=15
7995 13:22:14.683779
7996 13:22:14.686641 ----->DramcWriteLeveling(PI) begin...
7997 13:22:14.686745 ==
7998 13:22:14.690263 Dram Type= 6, Freq= 0, CH_0, rank 1
7999 13:22:14.693203 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8000 13:22:14.693303 ==
8001 13:22:14.697047 Write leveling (Byte 0): 32 => 32
8002 13:22:14.700000 Write leveling (Byte 1): 27 => 27
8003 13:22:14.703485 DramcWriteLeveling(PI) end<-----
8004 13:22:14.703563
8005 13:22:14.703628 ==
8006 13:22:14.706560 Dram Type= 6, Freq= 0, CH_0, rank 1
8007 13:22:14.710579 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8008 13:22:14.710667 ==
8009 13:22:14.713080 [Gating] SW mode calibration
8010 13:22:14.719759 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8011 13:22:14.726434 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8012 13:22:14.729941 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8013 13:22:14.736845 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8014 13:22:14.739920 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8015 13:22:14.743282 1 4 12 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
8016 13:22:14.750027 1 4 16 | B1->B0 | 2322 3434 | 1 1 | (0 0) (1 1)
8017 13:22:14.753019 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8018 13:22:14.756253 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8019 13:22:14.762993 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8020 13:22:14.766696 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8021 13:22:14.769786 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8022 13:22:14.773215 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8023 13:22:14.779798 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 0) (1 0)
8024 13:22:14.782826 1 5 16 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
8025 13:22:14.786494 1 5 20 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
8026 13:22:14.792603 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8027 13:22:14.796179 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8028 13:22:14.799322 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8029 13:22:14.806402 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8030 13:22:14.809609 1 6 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8031 13:22:14.812524 1 6 12 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
8032 13:22:14.819357 1 6 16 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
8033 13:22:14.822807 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8034 13:22:14.825997 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8035 13:22:14.832988 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8036 13:22:14.835723 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8037 13:22:14.839282 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8038 13:22:14.846004 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8039 13:22:14.848913 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8040 13:22:14.852638 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8041 13:22:14.858942 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8042 13:22:14.862563 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8043 13:22:14.865525 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 13:22:14.872359 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 13:22:14.875460 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 13:22:14.878923 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 13:22:14.885539 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 13:22:14.889221 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 13:22:14.892258 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 13:22:14.898901 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 13:22:14.902446 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 13:22:14.905509 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 13:22:14.911979 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 13:22:14.915489 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8055 13:22:14.919103 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8056 13:22:14.925507 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8057 13:22:14.925646 Total UI for P1: 0, mck2ui 16
8058 13:22:14.932436 best dqsien dly found for B0: ( 1, 9, 10)
8059 13:22:14.935318 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8060 13:22:14.939145 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8061 13:22:14.942205 Total UI for P1: 0, mck2ui 16
8062 13:22:14.945757 best dqsien dly found for B1: ( 1, 9, 20)
8063 13:22:14.948736 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8064 13:22:14.952289 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8065 13:22:14.952398
8066 13:22:14.955430 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8067 13:22:14.961712 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8068 13:22:14.961798 [Gating] SW calibration Done
8069 13:22:14.965634 ==
8070 13:22:14.965718 Dram Type= 6, Freq= 0, CH_0, rank 1
8071 13:22:14.971834 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8072 13:22:14.971919 ==
8073 13:22:14.971987 RX Vref Scan: 0
8074 13:22:14.972049
8075 13:22:14.975399 RX Vref 0 -> 0, step: 1
8076 13:22:14.975483
8077 13:22:14.978434 RX Delay 0 -> 252, step: 8
8078 13:22:14.981824 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8079 13:22:14.984856 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8080 13:22:14.988501 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8081 13:22:14.995261 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8082 13:22:14.998028 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8083 13:22:15.001649 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8084 13:22:15.004699 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8085 13:22:15.007924 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8086 13:22:15.014741 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8087 13:22:15.018310 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8088 13:22:15.021338 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8089 13:22:15.024951 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8090 13:22:15.028337 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8091 13:22:15.034835 iDelay=200, Bit 13, Center 123 (64 ~ 183) 120
8092 13:22:15.037795 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8093 13:22:15.041468 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8094 13:22:15.041550 ==
8095 13:22:15.044301 Dram Type= 6, Freq= 0, CH_0, rank 1
8096 13:22:15.047655 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8097 13:22:15.051218 ==
8098 13:22:15.051306 DQS Delay:
8099 13:22:15.051394 DQS0 = 0, DQS1 = 0
8100 13:22:15.054653 DQM Delay:
8101 13:22:15.054732 DQM0 = 128, DQM1 = 121
8102 13:22:15.058005 DQ Delay:
8103 13:22:15.060871 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8104 13:22:15.064479 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8105 13:22:15.067412 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8106 13:22:15.071240 DQ12 =127, DQ13 =123, DQ14 =131, DQ15 =127
8107 13:22:15.071322
8108 13:22:15.071403
8109 13:22:15.071468 ==
8110 13:22:15.074103 Dram Type= 6, Freq= 0, CH_0, rank 1
8111 13:22:15.077531 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8112 13:22:15.080669 ==
8113 13:22:15.080754
8114 13:22:15.080821
8115 13:22:15.080883 TX Vref Scan disable
8116 13:22:15.084357 == TX Byte 0 ==
8117 13:22:15.087765 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8118 13:22:15.090837 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8119 13:22:15.094392 == TX Byte 1 ==
8120 13:22:15.097859 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8121 13:22:15.101079 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8122 13:22:15.101163 ==
8123 13:22:15.104356 Dram Type= 6, Freq= 0, CH_0, rank 1
8124 13:22:15.111258 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8125 13:22:15.111349 ==
8126 13:22:15.122911
8127 13:22:15.126406 TX Vref early break, caculate TX vref
8128 13:22:15.130072 TX Vref=16, minBit 1, minWin=22, winSum=368
8129 13:22:15.133027 TX Vref=18, minBit 0, minWin=22, winSum=372
8130 13:22:15.136206 TX Vref=20, minBit 8, minWin=22, winSum=376
8131 13:22:15.139813 TX Vref=22, minBit 8, minWin=23, winSum=392
8132 13:22:15.143299 TX Vref=24, minBit 1, minWin=23, winSum=399
8133 13:22:15.150024 TX Vref=26, minBit 1, minWin=24, winSum=406
8134 13:22:15.153246 TX Vref=28, minBit 8, minWin=25, winSum=412
8135 13:22:15.156398 TX Vref=30, minBit 8, minWin=24, winSum=403
8136 13:22:15.159585 TX Vref=32, minBit 8, minWin=22, winSum=393
8137 13:22:15.162820 TX Vref=34, minBit 8, minWin=22, winSum=388
8138 13:22:15.169271 [TxChooseVref] Worse bit 8, Min win 25, Win sum 412, Final Vref 28
8139 13:22:15.169352
8140 13:22:15.172978 Final TX Range 0 Vref 28
8141 13:22:15.173053
8142 13:22:15.173116 ==
8143 13:22:15.176042 Dram Type= 6, Freq= 0, CH_0, rank 1
8144 13:22:15.179292 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8145 13:22:15.179367 ==
8146 13:22:15.179442
8147 13:22:15.179503
8148 13:22:15.182754 TX Vref Scan disable
8149 13:22:15.188999 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8150 13:22:15.189085 == TX Byte 0 ==
8151 13:22:15.192557 u2DelayCellOfst[0]=11 cells (3 PI)
8152 13:22:15.196438 u2DelayCellOfst[1]=18 cells (5 PI)
8153 13:22:15.199144 u2DelayCellOfst[2]=11 cells (3 PI)
8154 13:22:15.202797 u2DelayCellOfst[3]=11 cells (3 PI)
8155 13:22:15.205625 u2DelayCellOfst[4]=3 cells (1 PI)
8156 13:22:15.209576 u2DelayCellOfst[5]=0 cells (0 PI)
8157 13:22:15.212322 u2DelayCellOfst[6]=18 cells (5 PI)
8158 13:22:15.215806 u2DelayCellOfst[7]=18 cells (5 PI)
8159 13:22:15.219186 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8160 13:22:15.222572 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8161 13:22:15.225972 == TX Byte 1 ==
8162 13:22:15.226086 u2DelayCellOfst[8]=0 cells (0 PI)
8163 13:22:15.228985 u2DelayCellOfst[9]=0 cells (0 PI)
8164 13:22:15.232569 u2DelayCellOfst[10]=7 cells (2 PI)
8165 13:22:15.235496 u2DelayCellOfst[11]=7 cells (2 PI)
8166 13:22:15.239159 u2DelayCellOfst[12]=15 cells (4 PI)
8167 13:22:15.242504 u2DelayCellOfst[13]=11 cells (3 PI)
8168 13:22:15.245706 u2DelayCellOfst[14]=15 cells (4 PI)
8169 13:22:15.248960 u2DelayCellOfst[15]=11 cells (3 PI)
8170 13:22:15.252135 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8171 13:22:15.258654 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8172 13:22:15.258754 DramC Write-DBI on
8173 13:22:15.258824 ==
8174 13:22:15.262463 Dram Type= 6, Freq= 0, CH_0, rank 1
8175 13:22:15.268986 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8176 13:22:15.269066 ==
8177 13:22:15.269171
8178 13:22:15.269247
8179 13:22:15.269306 TX Vref Scan disable
8180 13:22:15.272443 == TX Byte 0 ==
8181 13:22:15.276091 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8182 13:22:15.279260 == TX Byte 1 ==
8183 13:22:15.282451 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8184 13:22:15.285312 DramC Write-DBI off
8185 13:22:15.285388
8186 13:22:15.285465 [DATLAT]
8187 13:22:15.285554 Freq=1600, CH0 RK1
8188 13:22:15.285617
8189 13:22:15.288756 DATLAT Default: 0xf
8190 13:22:15.292410 0, 0xFFFF, sum = 0
8191 13:22:15.292534 1, 0xFFFF, sum = 0
8192 13:22:15.295544 2, 0xFFFF, sum = 0
8193 13:22:15.295623 3, 0xFFFF, sum = 0
8194 13:22:15.298453 4, 0xFFFF, sum = 0
8195 13:22:15.298566 5, 0xFFFF, sum = 0
8196 13:22:15.301999 6, 0xFFFF, sum = 0
8197 13:22:15.302128 7, 0xFFFF, sum = 0
8198 13:22:15.305754 8, 0xFFFF, sum = 0
8199 13:22:15.305837 9, 0xFFFF, sum = 0
8200 13:22:15.308950 10, 0xFFFF, sum = 0
8201 13:22:15.309061 11, 0xFFFF, sum = 0
8202 13:22:15.312152 12, 0xFFFF, sum = 0
8203 13:22:15.312289 13, 0xCFFF, sum = 0
8204 13:22:15.315147 14, 0x0, sum = 1
8205 13:22:15.315247 15, 0x0, sum = 2
8206 13:22:15.318320 16, 0x0, sum = 3
8207 13:22:15.318409 17, 0x0, sum = 4
8208 13:22:15.321993 best_step = 15
8209 13:22:15.322077
8210 13:22:15.322143 ==
8211 13:22:15.325617 Dram Type= 6, Freq= 0, CH_0, rank 1
8212 13:22:15.328422 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8213 13:22:15.328507 ==
8214 13:22:15.332191 RX Vref Scan: 0
8215 13:22:15.332275
8216 13:22:15.332340 RX Vref 0 -> 0, step: 1
8217 13:22:15.332402
8218 13:22:15.334853 RX Delay 3 -> 252, step: 4
8219 13:22:15.341993 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8220 13:22:15.345295 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8221 13:22:15.348261 iDelay=191, Bit 2, Center 120 (67 ~ 174) 108
8222 13:22:15.351625 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8223 13:22:15.355121 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8224 13:22:15.361937 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8225 13:22:15.364770 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8226 13:22:15.368368 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8227 13:22:15.371311 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8228 13:22:15.374751 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8229 13:22:15.381552 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8230 13:22:15.384662 iDelay=191, Bit 11, Center 110 (51 ~ 170) 120
8231 13:22:15.387842 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8232 13:22:15.391108 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8233 13:22:15.394803 iDelay=191, Bit 14, Center 126 (67 ~ 186) 120
8234 13:22:15.401410 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8235 13:22:15.401499 ==
8236 13:22:15.404928 Dram Type= 6, Freq= 0, CH_0, rank 1
8237 13:22:15.408225 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8238 13:22:15.408310 ==
8239 13:22:15.408376 DQS Delay:
8240 13:22:15.411249 DQS0 = 0, DQS1 = 0
8241 13:22:15.411333 DQM Delay:
8242 13:22:15.414872 DQM0 = 124, DQM1 = 117
8243 13:22:15.414956 DQ Delay:
8244 13:22:15.417840 DQ0 =124, DQ1 =124, DQ2 =120, DQ3 =122
8245 13:22:15.421318 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8246 13:22:15.424081 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =110
8247 13:22:15.430903 DQ12 =124, DQ13 =122, DQ14 =126, DQ15 =124
8248 13:22:15.430988
8249 13:22:15.431054
8250 13:22:15.431114
8251 13:22:15.434215 [DramC_TX_OE_Calibration] TA2
8252 13:22:15.434299 Original DQ_B0 (3 6) =30, OEN = 27
8253 13:22:15.437337 Original DQ_B1 (3 6) =30, OEN = 27
8254 13:22:15.440615 24, 0x0, End_B0=24 End_B1=24
8255 13:22:15.444457 25, 0x0, End_B0=25 End_B1=25
8256 13:22:15.447376 26, 0x0, End_B0=26 End_B1=26
8257 13:22:15.450656 27, 0x0, End_B0=27 End_B1=27
8258 13:22:15.450741 28, 0x0, End_B0=28 End_B1=28
8259 13:22:15.454234 29, 0x0, End_B0=29 End_B1=29
8260 13:22:15.457335 30, 0x0, End_B0=30 End_B1=30
8261 13:22:15.460479 31, 0x4141, End_B0=30 End_B1=30
8262 13:22:15.464582 Byte0 end_step=30 best_step=27
8263 13:22:15.464665 Byte1 end_step=30 best_step=27
8264 13:22:15.467216 Byte0 TX OE(2T, 0.5T) = (3, 3)
8265 13:22:15.470760 Byte1 TX OE(2T, 0.5T) = (3, 3)
8266 13:22:15.470844
8267 13:22:15.470909
8268 13:22:15.480436 [DQSOSCAuto] RK1, (LSB)MR18= 0x210f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8269 13:22:15.480520 CH0 RK1: MR19=303, MR18=210F
8270 13:22:15.487184 CH0_RK1: MR19=0x303, MR18=0x210F, DQSOSC=393, MR23=63, INC=23, DEC=15
8271 13:22:15.490436 [RxdqsGatingPostProcess] freq 1600
8272 13:22:15.496895 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8273 13:22:15.500010 best DQS0 dly(2T, 0.5T) = (1, 1)
8274 13:22:15.503642 best DQS1 dly(2T, 0.5T) = (1, 1)
8275 13:22:15.506751 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8276 13:22:15.510351 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8277 13:22:15.513407 best DQS0 dly(2T, 0.5T) = (1, 1)
8278 13:22:15.513518 best DQS1 dly(2T, 0.5T) = (1, 1)
8279 13:22:15.517037 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8280 13:22:15.519978 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8281 13:22:15.523657 Pre-setting of DQS Precalculation
8282 13:22:15.529889 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8283 13:22:15.529985 ==
8284 13:22:15.533359 Dram Type= 6, Freq= 0, CH_1, rank 0
8285 13:22:15.537001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8286 13:22:15.537080 ==
8287 13:22:15.543453 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8288 13:22:15.546446 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8289 13:22:15.550040 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8290 13:22:15.556109 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8291 13:22:15.565858 [CA 0] Center 42 (13~71) winsize 59
8292 13:22:15.568703 [CA 1] Center 42 (13~72) winsize 60
8293 13:22:15.572243 [CA 2] Center 38 (9~67) winsize 59
8294 13:22:15.575550 [CA 3] Center 37 (8~67) winsize 60
8295 13:22:15.578532 [CA 4] Center 38 (9~67) winsize 59
8296 13:22:15.582120 [CA 5] Center 36 (7~66) winsize 60
8297 13:22:15.582206
8298 13:22:15.585515 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8299 13:22:15.585605
8300 13:22:15.588837 [CATrainingPosCal] consider 1 rank data
8301 13:22:15.592344 u2DelayCellTimex100 = 258/100 ps
8302 13:22:15.598781 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8303 13:22:15.601720 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8304 13:22:15.605127 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8305 13:22:15.608772 CA3 delay=37 (8~67),Diff = 1 PI (3 cell)
8306 13:22:15.612110 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8307 13:22:15.615406 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8308 13:22:15.615497
8309 13:22:15.618659 CA PerBit enable=1, Macro0, CA PI delay=36
8310 13:22:15.618748
8311 13:22:15.621628 [CBTSetCACLKResult] CA Dly = 36
8312 13:22:15.625259 CS Dly: 9 (0~40)
8313 13:22:15.628419 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8314 13:22:15.632027 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8315 13:22:15.632104 ==
8316 13:22:15.635082 Dram Type= 6, Freq= 0, CH_1, rank 1
8317 13:22:15.638641 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8318 13:22:15.641586 ==
8319 13:22:15.644673 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8320 13:22:15.648187 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8321 13:22:15.654950 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8322 13:22:15.661458 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8323 13:22:15.668572 [CA 0] Center 42 (13~71) winsize 59
8324 13:22:15.672088 [CA 1] Center 42 (12~72) winsize 61
8325 13:22:15.675145 [CA 2] Center 37 (8~67) winsize 60
8326 13:22:15.678537 [CA 3] Center 36 (7~66) winsize 60
8327 13:22:15.681855 [CA 4] Center 37 (8~67) winsize 60
8328 13:22:15.685343 [CA 5] Center 36 (6~66) winsize 61
8329 13:22:15.685429
8330 13:22:15.688527 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8331 13:22:15.688613
8332 13:22:15.692107 [CATrainingPosCal] consider 2 rank data
8333 13:22:15.695040 u2DelayCellTimex100 = 258/100 ps
8334 13:22:15.701490 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8335 13:22:15.704946 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8336 13:22:15.708473 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8337 13:22:15.711342 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8338 13:22:15.715162 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8339 13:22:15.718587 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8340 13:22:15.718666
8341 13:22:15.721718 CA PerBit enable=1, Macro0, CA PI delay=36
8342 13:22:15.721826
8343 13:22:15.724396 [CBTSetCACLKResult] CA Dly = 36
8344 13:22:15.728495 CS Dly: 11 (0~44)
8345 13:22:15.731680 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8346 13:22:15.734703 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8347 13:22:15.734816
8348 13:22:15.737794 ----->DramcWriteLeveling(PI) begin...
8349 13:22:15.737879 ==
8350 13:22:15.741590 Dram Type= 6, Freq= 0, CH_1, rank 0
8351 13:22:15.747884 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8352 13:22:15.747968 ==
8353 13:22:15.750995 Write leveling (Byte 0): 24 => 24
8354 13:22:15.754088 Write leveling (Byte 1): 28 => 28
8355 13:22:15.754166 DramcWriteLeveling(PI) end<-----
8356 13:22:15.758066
8357 13:22:15.758179 ==
8358 13:22:15.760849 Dram Type= 6, Freq= 0, CH_1, rank 0
8359 13:22:15.764438 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8360 13:22:15.764543 ==
8361 13:22:15.767356 [Gating] SW mode calibration
8362 13:22:15.774163 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8363 13:22:15.777722 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8364 13:22:15.784137 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 13:22:15.787458 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 13:22:15.790556 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 13:22:15.797145 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 13:22:15.800651 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 13:22:15.803768 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 13:22:15.810443 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 13:22:15.813781 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 13:22:15.816890 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8373 13:22:15.823619 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8374 13:22:15.826967 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8375 13:22:15.830554 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8376 13:22:15.836971 1 5 16 | B1->B0 | 2828 2323 | 0 0 | (1 0) (1 0)
8377 13:22:15.840580 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 13:22:15.843700 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 13:22:15.850259 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 13:22:15.853255 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 13:22:15.856886 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 13:22:15.863305 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 13:22:15.866228 1 6 12 | B1->B0 | 2525 2828 | 0 1 | (0 0) (0 0)
8384 13:22:15.870011 1 6 16 | B1->B0 | 3f3f 3e3d | 1 1 | (0 0) (1 1)
8385 13:22:15.876582 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 13:22:15.879576 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 13:22:15.883145 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 13:22:15.889918 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 13:22:15.893150 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 13:22:15.895985 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 13:22:15.902894 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 13:22:15.906186 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8393 13:22:15.909291 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 13:22:15.916335 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 13:22:15.919473 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 13:22:15.923254 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 13:22:15.929172 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 13:22:15.932429 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 13:22:15.935832 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 13:22:15.942704 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 13:22:15.945687 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 13:22:15.949279 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 13:22:15.955877 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 13:22:15.958987 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 13:22:15.962517 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 13:22:15.968942 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 13:22:15.972328 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8408 13:22:15.975849 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8409 13:22:15.982649 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 13:22:15.985645 Total UI for P1: 0, mck2ui 16
8411 13:22:15.988792 best dqsien dly found for B0: ( 1, 9, 14)
8412 13:22:15.988870 Total UI for P1: 0, mck2ui 16
8413 13:22:15.995378 best dqsien dly found for B1: ( 1, 9, 16)
8414 13:22:15.998715 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8415 13:22:16.002080 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8416 13:22:16.002190
8417 13:22:16.005208 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8418 13:22:16.008832 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8419 13:22:16.011702 [Gating] SW calibration Done
8420 13:22:16.011786 ==
8421 13:22:16.015541 Dram Type= 6, Freq= 0, CH_1, rank 0
8422 13:22:16.018598 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8423 13:22:16.018674 ==
8424 13:22:16.021595 RX Vref Scan: 0
8425 13:22:16.021677
8426 13:22:16.025018 RX Vref 0 -> 0, step: 1
8427 13:22:16.025111
8428 13:22:16.025179 RX Delay 0 -> 252, step: 8
8429 13:22:16.031519 iDelay=208, Bit 0, Center 135 (80 ~ 191) 112
8430 13:22:16.034962 iDelay=208, Bit 1, Center 127 (64 ~ 191) 128
8431 13:22:16.038412 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8432 13:22:16.041733 iDelay=208, Bit 3, Center 131 (72 ~ 191) 120
8433 13:22:16.044813 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8434 13:22:16.051838 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8435 13:22:16.054860 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8436 13:22:16.058039 iDelay=208, Bit 7, Center 131 (72 ~ 191) 120
8437 13:22:16.061729 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8438 13:22:16.064711 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8439 13:22:16.071788 iDelay=208, Bit 10, Center 123 (72 ~ 175) 104
8440 13:22:16.074779 iDelay=208, Bit 11, Center 115 (56 ~ 175) 120
8441 13:22:16.077838 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8442 13:22:16.081371 iDelay=208, Bit 13, Center 131 (72 ~ 191) 120
8443 13:22:16.084725 iDelay=208, Bit 14, Center 131 (72 ~ 191) 120
8444 13:22:16.091166 iDelay=208, Bit 15, Center 131 (72 ~ 191) 120
8445 13:22:16.091254 ==
8446 13:22:16.094468 Dram Type= 6, Freq= 0, CH_1, rank 0
8447 13:22:16.098365 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8448 13:22:16.098447 ==
8449 13:22:16.098525 DQS Delay:
8450 13:22:16.101078 DQS0 = 0, DQS1 = 0
8451 13:22:16.101152 DQM Delay:
8452 13:22:16.104440 DQM0 = 133, DQM1 = 124
8453 13:22:16.104515 DQ Delay:
8454 13:22:16.107970 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8455 13:22:16.111233 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =131
8456 13:22:16.114420 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =115
8457 13:22:16.121238 DQ12 =135, DQ13 =131, DQ14 =131, DQ15 =131
8458 13:22:16.121384
8459 13:22:16.121481
8460 13:22:16.121594 ==
8461 13:22:16.123820 Dram Type= 6, Freq= 0, CH_1, rank 0
8462 13:22:16.127615 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8463 13:22:16.127740 ==
8464 13:22:16.127808
8465 13:22:16.127868
8466 13:22:16.130543 TX Vref Scan disable
8467 13:22:16.130614 == TX Byte 0 ==
8468 13:22:16.137806 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8469 13:22:16.140815 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8470 13:22:16.140949 == TX Byte 1 ==
8471 13:22:16.147506 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8472 13:22:16.150748 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8473 13:22:16.150824 ==
8474 13:22:16.153733 Dram Type= 6, Freq= 0, CH_1, rank 0
8475 13:22:16.157383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8476 13:22:16.157464 ==
8477 13:22:16.171932
8478 13:22:16.175489 TX Vref early break, caculate TX vref
8479 13:22:16.178691 TX Vref=16, minBit 11, minWin=21, winSum=363
8480 13:22:16.181864 TX Vref=18, minBit 3, minWin=22, winSum=369
8481 13:22:16.185411 TX Vref=20, minBit 3, minWin=23, winSum=386
8482 13:22:16.188395 TX Vref=22, minBit 0, minWin=24, winSum=391
8483 13:22:16.191886 TX Vref=24, minBit 0, minWin=24, winSum=401
8484 13:22:16.198481 TX Vref=26, minBit 5, minWin=24, winSum=410
8485 13:22:16.202049 TX Vref=28, minBit 0, minWin=25, winSum=415
8486 13:22:16.205011 TX Vref=30, minBit 0, minWin=24, winSum=408
8487 13:22:16.208423 TX Vref=32, minBit 0, minWin=24, winSum=404
8488 13:22:16.212046 TX Vref=34, minBit 1, minWin=23, winSum=394
8489 13:22:16.214866 TX Vref=36, minBit 6, minWin=22, winSum=382
8490 13:22:16.221564 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 28
8491 13:22:16.221645
8492 13:22:16.225276 Final TX Range 0 Vref 28
8493 13:22:16.225361
8494 13:22:16.225426 ==
8495 13:22:16.228231 Dram Type= 6, Freq= 0, CH_1, rank 0
8496 13:22:16.231816 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8497 13:22:16.231893 ==
8498 13:22:16.234815
8499 13:22:16.234897
8500 13:22:16.234961 TX Vref Scan disable
8501 13:22:16.241657 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8502 13:22:16.241767 == TX Byte 0 ==
8503 13:22:16.245074 u2DelayCellOfst[0]=22 cells (6 PI)
8504 13:22:16.248259 u2DelayCellOfst[1]=18 cells (5 PI)
8505 13:22:16.251589 u2DelayCellOfst[2]=0 cells (0 PI)
8506 13:22:16.255041 u2DelayCellOfst[3]=7 cells (2 PI)
8507 13:22:16.258340 u2DelayCellOfst[4]=11 cells (3 PI)
8508 13:22:16.261458 u2DelayCellOfst[5]=26 cells (7 PI)
8509 13:22:16.264513 u2DelayCellOfst[6]=22 cells (6 PI)
8510 13:22:16.268165 u2DelayCellOfst[7]=7 cells (2 PI)
8511 13:22:16.271586 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8512 13:22:16.274697 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8513 13:22:16.277839 == TX Byte 1 ==
8514 13:22:16.281465 u2DelayCellOfst[8]=0 cells (0 PI)
8515 13:22:16.284369 u2DelayCellOfst[9]=7 cells (2 PI)
8516 13:22:16.288037 u2DelayCellOfst[10]=15 cells (4 PI)
8517 13:22:16.291131 u2DelayCellOfst[11]=11 cells (3 PI)
8518 13:22:16.291224 u2DelayCellOfst[12]=18 cells (5 PI)
8519 13:22:16.295022 u2DelayCellOfst[13]=22 cells (6 PI)
8520 13:22:16.297939 u2DelayCellOfst[14]=22 cells (6 PI)
8521 13:22:16.301340 u2DelayCellOfst[15]=22 cells (6 PI)
8522 13:22:16.307793 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8523 13:22:16.311060 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8524 13:22:16.311137 DramC Write-DBI on
8525 13:22:16.314269 ==
8526 13:22:16.317710 Dram Type= 6, Freq= 0, CH_1, rank 0
8527 13:22:16.321162 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8528 13:22:16.321256 ==
8529 13:22:16.321324
8530 13:22:16.321385
8531 13:22:16.324299 TX Vref Scan disable
8532 13:22:16.324417 == TX Byte 0 ==
8533 13:22:16.331207 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8534 13:22:16.331319 == TX Byte 1 ==
8535 13:22:16.334047 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8536 13:22:16.337601 DramC Write-DBI off
8537 13:22:16.337699
8538 13:22:16.337766 [DATLAT]
8539 13:22:16.341216 Freq=1600, CH1 RK0
8540 13:22:16.341295
8541 13:22:16.341370 DATLAT Default: 0xf
8542 13:22:16.344555 0, 0xFFFF, sum = 0
8543 13:22:16.344648 1, 0xFFFF, sum = 0
8544 13:22:16.347659 2, 0xFFFF, sum = 0
8545 13:22:16.347750 3, 0xFFFF, sum = 0
8546 13:22:16.351254 4, 0xFFFF, sum = 0
8547 13:22:16.351332 5, 0xFFFF, sum = 0
8548 13:22:16.354132 6, 0xFFFF, sum = 0
8549 13:22:16.354220 7, 0xFFFF, sum = 0
8550 13:22:16.357840 8, 0xFFFF, sum = 0
8551 13:22:16.357923 9, 0xFFFF, sum = 0
8552 13:22:16.360921 10, 0xFFFF, sum = 0
8553 13:22:16.364315 11, 0xFFFF, sum = 0
8554 13:22:16.364408 12, 0xFFFF, sum = 0
8555 13:22:16.367425 13, 0x8FFF, sum = 0
8556 13:22:16.367513 14, 0x0, sum = 1
8557 13:22:16.370904 15, 0x0, sum = 2
8558 13:22:16.371011 16, 0x0, sum = 3
8559 13:22:16.371082 17, 0x0, sum = 4
8560 13:22:16.374470 best_step = 15
8561 13:22:16.374544
8562 13:22:16.374619 ==
8563 13:22:16.377398 Dram Type= 6, Freq= 0, CH_1, rank 0
8564 13:22:16.381224 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8565 13:22:16.381301 ==
8566 13:22:16.384145 RX Vref Scan: 1
8567 13:22:16.384231
8568 13:22:16.387839 Set Vref Range= 24 -> 127
8569 13:22:16.387942
8570 13:22:16.388043 RX Vref 24 -> 127, step: 1
8571 13:22:16.388134
8572 13:22:16.390612 RX Delay 11 -> 252, step: 4
8573 13:22:16.390690
8574 13:22:16.393968 Set Vref, RX VrefLevel [Byte0]: 24
8575 13:22:16.397174 [Byte1]: 24
8576 13:22:16.397257
8577 13:22:16.400936 Set Vref, RX VrefLevel [Byte0]: 25
8578 13:22:16.403919 [Byte1]: 25
8579 13:22:16.408296
8580 13:22:16.408376 Set Vref, RX VrefLevel [Byte0]: 26
8581 13:22:16.411611 [Byte1]: 26
8582 13:22:16.415929
8583 13:22:16.416003 Set Vref, RX VrefLevel [Byte0]: 27
8584 13:22:16.418808 [Byte1]: 27
8585 13:22:16.423441
8586 13:22:16.423540 Set Vref, RX VrefLevel [Byte0]: 28
8587 13:22:16.426801 [Byte1]: 28
8588 13:22:16.431173
8589 13:22:16.431285 Set Vref, RX VrefLevel [Byte0]: 29
8590 13:22:16.434674 [Byte1]: 29
8591 13:22:16.438784
8592 13:22:16.438890 Set Vref, RX VrefLevel [Byte0]: 30
8593 13:22:16.441714 [Byte1]: 30
8594 13:22:16.446365
8595 13:22:16.446448 Set Vref, RX VrefLevel [Byte0]: 31
8596 13:22:16.449889 [Byte1]: 31
8597 13:22:16.454202
8598 13:22:16.454286 Set Vref, RX VrefLevel [Byte0]: 32
8599 13:22:16.457281 [Byte1]: 32
8600 13:22:16.461413
8601 13:22:16.461496 Set Vref, RX VrefLevel [Byte0]: 33
8602 13:22:16.464864 [Byte1]: 33
8603 13:22:16.469208
8604 13:22:16.469306 Set Vref, RX VrefLevel [Byte0]: 34
8605 13:22:16.472387 [Byte1]: 34
8606 13:22:16.476938
8607 13:22:16.477035 Set Vref, RX VrefLevel [Byte0]: 35
8608 13:22:16.479970 [Byte1]: 35
8609 13:22:16.484191
8610 13:22:16.484297 Set Vref, RX VrefLevel [Byte0]: 36
8611 13:22:16.487602 [Byte1]: 36
8612 13:22:16.491758
8613 13:22:16.491836 Set Vref, RX VrefLevel [Byte0]: 37
8614 13:22:16.494946 [Byte1]: 37
8615 13:22:16.499577
8616 13:22:16.499674 Set Vref, RX VrefLevel [Byte0]: 38
8617 13:22:16.502523 [Byte1]: 38
8618 13:22:16.507140
8619 13:22:16.510430 Set Vref, RX VrefLevel [Byte0]: 39
8620 13:22:16.513783 [Byte1]: 39
8621 13:22:16.513877
8622 13:22:16.516764 Set Vref, RX VrefLevel [Byte0]: 40
8623 13:22:16.520166 [Byte1]: 40
8624 13:22:16.520253
8625 13:22:16.523855 Set Vref, RX VrefLevel [Byte0]: 41
8626 13:22:16.526822 [Byte1]: 41
8627 13:22:16.526906
8628 13:22:16.530447 Set Vref, RX VrefLevel [Byte0]: 42
8629 13:22:16.533401 [Byte1]: 42
8630 13:22:16.537538
8631 13:22:16.537624 Set Vref, RX VrefLevel [Byte0]: 43
8632 13:22:16.540991 [Byte1]: 43
8633 13:22:16.544938
8634 13:22:16.545017 Set Vref, RX VrefLevel [Byte0]: 44
8635 13:22:16.548384 [Byte1]: 44
8636 13:22:16.552782
8637 13:22:16.552862 Set Vref, RX VrefLevel [Byte0]: 45
8638 13:22:16.556337 [Byte1]: 45
8639 13:22:16.560485
8640 13:22:16.560575 Set Vref, RX VrefLevel [Byte0]: 46
8641 13:22:16.563627 [Byte1]: 46
8642 13:22:16.567861
8643 13:22:16.567939 Set Vref, RX VrefLevel [Byte0]: 47
8644 13:22:16.571446 [Byte1]: 47
8645 13:22:16.576114
8646 13:22:16.576192 Set Vref, RX VrefLevel [Byte0]: 48
8647 13:22:16.578899 [Byte1]: 48
8648 13:22:16.583533
8649 13:22:16.583622 Set Vref, RX VrefLevel [Byte0]: 49
8650 13:22:16.586684 [Byte1]: 49
8651 13:22:16.591223
8652 13:22:16.591318 Set Vref, RX VrefLevel [Byte0]: 50
8653 13:22:16.594086 [Byte1]: 50
8654 13:22:16.598325
8655 13:22:16.598408 Set Vref, RX VrefLevel [Byte0]: 51
8656 13:22:16.601972 [Byte1]: 51
8657 13:22:16.606162
8658 13:22:16.606264 Set Vref, RX VrefLevel [Byte0]: 52
8659 13:22:16.609763 [Byte1]: 52
8660 13:22:16.614090
8661 13:22:16.614178 Set Vref, RX VrefLevel [Byte0]: 53
8662 13:22:16.617057 [Byte1]: 53
8663 13:22:16.621276
8664 13:22:16.621353 Set Vref, RX VrefLevel [Byte0]: 54
8665 13:22:16.624584 [Byte1]: 54
8666 13:22:16.628904
8667 13:22:16.628997 Set Vref, RX VrefLevel [Byte0]: 55
8668 13:22:16.632015 [Byte1]: 55
8669 13:22:16.636396
8670 13:22:16.636482 Set Vref, RX VrefLevel [Byte0]: 56
8671 13:22:16.639836 [Byte1]: 56
8672 13:22:16.644377
8673 13:22:16.644458 Set Vref, RX VrefLevel [Byte0]: 57
8674 13:22:16.647520 [Byte1]: 57
8675 13:22:16.652065
8676 13:22:16.652196 Set Vref, RX VrefLevel [Byte0]: 58
8677 13:22:16.655181 [Byte1]: 58
8678 13:22:16.659499
8679 13:22:16.659620 Set Vref, RX VrefLevel [Byte0]: 59
8680 13:22:16.662455 [Byte1]: 59
8681 13:22:16.666831
8682 13:22:16.666931 Set Vref, RX VrefLevel [Byte0]: 60
8683 13:22:16.670464 [Byte1]: 60
8684 13:22:16.674653
8685 13:22:16.674761 Set Vref, RX VrefLevel [Byte0]: 61
8686 13:22:16.678314 [Byte1]: 61
8687 13:22:16.682507
8688 13:22:16.682615 Set Vref, RX VrefLevel [Byte0]: 62
8689 13:22:16.685317 [Byte1]: 62
8690 13:22:16.689957
8691 13:22:16.690032 Set Vref, RX VrefLevel [Byte0]: 63
8692 13:22:16.693320 [Byte1]: 63
8693 13:22:16.697311
8694 13:22:16.697419 Set Vref, RX VrefLevel [Byte0]: 64
8695 13:22:16.700546 [Byte1]: 64
8696 13:22:16.704780
8697 13:22:16.708259 Set Vref, RX VrefLevel [Byte0]: 65
8698 13:22:16.711861 [Byte1]: 65
8699 13:22:16.711936
8700 13:22:16.714851 Set Vref, RX VrefLevel [Byte0]: 66
8701 13:22:16.718414 [Byte1]: 66
8702 13:22:16.718486
8703 13:22:16.721410 Set Vref, RX VrefLevel [Byte0]: 67
8704 13:22:16.724852 [Byte1]: 67
8705 13:22:16.724954
8706 13:22:16.728057 Set Vref, RX VrefLevel [Byte0]: 68
8707 13:22:16.731125 [Byte1]: 68
8708 13:22:16.735325
8709 13:22:16.735441 Set Vref, RX VrefLevel [Byte0]: 69
8710 13:22:16.739038 [Byte1]: 69
8711 13:22:16.742838
8712 13:22:16.742915 Set Vref, RX VrefLevel [Byte0]: 70
8713 13:22:16.746352 [Byte1]: 70
8714 13:22:16.750803
8715 13:22:16.750885 Set Vref, RX VrefLevel [Byte0]: 71
8716 13:22:16.754350 [Byte1]: 71
8717 13:22:16.758674
8718 13:22:16.758775 Set Vref, RX VrefLevel [Byte0]: 72
8719 13:22:16.761863 [Byte1]: 72
8720 13:22:16.766072
8721 13:22:16.766154 Final RX Vref Byte 0 = 58 to rank0
8722 13:22:16.769563 Final RX Vref Byte 1 = 50 to rank0
8723 13:22:16.772447 Final RX Vref Byte 0 = 58 to rank1
8724 13:22:16.776089 Final RX Vref Byte 1 = 50 to rank1==
8725 13:22:16.779225 Dram Type= 6, Freq= 0, CH_1, rank 0
8726 13:22:16.785681 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8727 13:22:16.785764 ==
8728 13:22:16.785828 DQS Delay:
8729 13:22:16.785887 DQS0 = 0, DQS1 = 0
8730 13:22:16.789368 DQM Delay:
8731 13:22:16.789459 DQM0 = 130, DQM1 = 122
8732 13:22:16.792640 DQ Delay:
8733 13:22:16.795765 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =128
8734 13:22:16.799465 DQ4 =128, DQ5 =142, DQ6 =140, DQ7 =126
8735 13:22:16.802487 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =114
8736 13:22:16.805733 DQ12 =132, DQ13 =130, DQ14 =132, DQ15 =130
8737 13:22:16.805835
8738 13:22:16.805913
8739 13:22:16.805974
8740 13:22:16.809151 [DramC_TX_OE_Calibration] TA2
8741 13:22:16.812158 Original DQ_B0 (3 6) =30, OEN = 27
8742 13:22:16.815815 Original DQ_B1 (3 6) =30, OEN = 27
8743 13:22:16.818817 24, 0x0, End_B0=24 End_B1=24
8744 13:22:16.818894 25, 0x0, End_B0=25 End_B1=25
8745 13:22:16.822448 26, 0x0, End_B0=26 End_B1=26
8746 13:22:16.825260 27, 0x0, End_B0=27 End_B1=27
8747 13:22:16.828923 28, 0x0, End_B0=28 End_B1=28
8748 13:22:16.832062 29, 0x0, End_B0=29 End_B1=29
8749 13:22:16.832157 30, 0x0, End_B0=30 End_B1=30
8750 13:22:16.835303 31, 0x4141, End_B0=30 End_B1=30
8751 13:22:16.838946 Byte0 end_step=30 best_step=27
8752 13:22:16.841987 Byte1 end_step=30 best_step=27
8753 13:22:16.845475 Byte0 TX OE(2T, 0.5T) = (3, 3)
8754 13:22:16.848730 Byte1 TX OE(2T, 0.5T) = (3, 3)
8755 13:22:16.848822
8756 13:22:16.848889
8757 13:22:16.855609 [DQSOSCAuto] RK0, (LSB)MR18= 0x80c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
8758 13:22:16.858722 CH1 RK0: MR19=303, MR18=80C
8759 13:22:16.865564 CH1_RK0: MR19=0x303, MR18=0x80C, DQSOSC=403, MR23=63, INC=22, DEC=15
8760 13:22:16.865646
8761 13:22:16.868841 ----->DramcWriteLeveling(PI) begin...
8762 13:22:16.868930 ==
8763 13:22:16.872325 Dram Type= 6, Freq= 0, CH_1, rank 1
8764 13:22:16.875336 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8765 13:22:16.875454 ==
8766 13:22:16.878625 Write leveling (Byte 0): 25 => 25
8767 13:22:16.881985 Write leveling (Byte 1): 27 => 27
8768 13:22:16.885531 DramcWriteLeveling(PI) end<-----
8769 13:22:16.885608
8770 13:22:16.885671 ==
8771 13:22:16.888448 Dram Type= 6, Freq= 0, CH_1, rank 1
8772 13:22:16.891407 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8773 13:22:16.891527 ==
8774 13:22:16.895178 [Gating] SW mode calibration
8775 13:22:16.901805 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8776 13:22:16.907959 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8777 13:22:16.911704 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 13:22:16.918386 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8779 13:22:16.921449 1 4 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8780 13:22:16.925048 1 4 12 | B1->B0 | 2b2b 3434 | 0 1 | (1 1) (1 1)
8781 13:22:16.931583 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8782 13:22:16.935415 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8783 13:22:16.937791 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8784 13:22:16.941639 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 13:22:16.948330 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8786 13:22:16.951686 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8787 13:22:16.954758 1 5 8 | B1->B0 | 3434 2626 | 1 0 | (1 0) (0 0)
8788 13:22:16.961660 1 5 12 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
8789 13:22:16.964720 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 13:22:16.968135 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8791 13:22:16.974468 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 13:22:16.978244 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 13:22:16.981162 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 13:22:16.987980 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8795 13:22:16.991296 1 6 8 | B1->B0 | 2424 4545 | 0 0 | (0 0) (0 0)
8796 13:22:16.994676 1 6 12 | B1->B0 | 403f 4646 | 1 0 | (0 0) (0 0)
8797 13:22:17.001080 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 13:22:17.004866 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 13:22:17.007723 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 13:22:17.014413 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 13:22:17.017713 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 13:22:17.021014 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 13:22:17.027878 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8804 13:22:17.031431 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8805 13:22:17.034514 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 13:22:17.041040 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 13:22:17.044584 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 13:22:17.047322 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 13:22:17.053937 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 13:22:17.057473 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 13:22:17.060743 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 13:22:17.067640 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 13:22:17.070725 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 13:22:17.074269 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 13:22:17.080848 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 13:22:17.083799 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 13:22:17.087581 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 13:22:17.093850 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 13:22:17.097369 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8820 13:22:17.100739 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8821 13:22:17.106925 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8822 13:22:17.107037 Total UI for P1: 0, mck2ui 16
8823 13:22:17.110776 best dqsien dly found for B0: ( 1, 9, 10)
8824 13:22:17.116840 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8825 13:22:17.120380 Total UI for P1: 0, mck2ui 16
8826 13:22:17.123664 best dqsien dly found for B1: ( 1, 9, 14)
8827 13:22:17.127243 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8828 13:22:17.130080 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8829 13:22:17.130190
8830 13:22:17.133543 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8831 13:22:17.137191 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8832 13:22:17.140050 [Gating] SW calibration Done
8833 13:22:17.140142 ==
8834 13:22:17.143667 Dram Type= 6, Freq= 0, CH_1, rank 1
8835 13:22:17.147115 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8836 13:22:17.147195 ==
8837 13:22:17.150409 RX Vref Scan: 0
8838 13:22:17.150508
8839 13:22:17.154169 RX Vref 0 -> 0, step: 1
8840 13:22:17.154274
8841 13:22:17.154376 RX Delay 0 -> 252, step: 8
8842 13:22:17.160150 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8843 13:22:17.163593 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8844 13:22:17.166603 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8845 13:22:17.170124 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8846 13:22:17.173289 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8847 13:22:17.180116 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8848 13:22:17.183499 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8849 13:22:17.186898 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8850 13:22:17.190069 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8851 13:22:17.193138 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8852 13:22:17.199624 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8853 13:22:17.202794 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8854 13:22:17.206253 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8855 13:22:17.209732 iDelay=200, Bit 13, Center 135 (72 ~ 199) 128
8856 13:22:17.216427 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8857 13:22:17.220254 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8858 13:22:17.220352 ==
8859 13:22:17.222829 Dram Type= 6, Freq= 0, CH_1, rank 1
8860 13:22:17.226296 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8861 13:22:17.226399 ==
8862 13:22:17.229611 DQS Delay:
8863 13:22:17.229713 DQS0 = 0, DQS1 = 0
8864 13:22:17.229798 DQM Delay:
8865 13:22:17.233017 DQM0 = 131, DQM1 = 127
8866 13:22:17.233105 DQ Delay:
8867 13:22:17.236138 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8868 13:22:17.239520 DQ4 =131, DQ5 =139, DQ6 =139, DQ7 =131
8869 13:22:17.242588 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8870 13:22:17.249128 DQ12 =135, DQ13 =135, DQ14 =131, DQ15 =131
8871 13:22:17.249224
8872 13:22:17.249301
8873 13:22:17.249364 ==
8874 13:22:17.252620 Dram Type= 6, Freq= 0, CH_1, rank 1
8875 13:22:17.256334 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8876 13:22:17.256440 ==
8877 13:22:17.256582
8878 13:22:17.256684
8879 13:22:17.259052 TX Vref Scan disable
8880 13:22:17.259169 == TX Byte 0 ==
8881 13:22:17.265461 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8882 13:22:17.268837 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8883 13:22:17.268925 == TX Byte 1 ==
8884 13:22:17.276182 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8885 13:22:17.278984 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8886 13:22:17.279099 ==
8887 13:22:17.282470 Dram Type= 6, Freq= 0, CH_1, rank 1
8888 13:22:17.285562 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8889 13:22:17.285667 ==
8890 13:22:17.300513
8891 13:22:17.303895 TX Vref early break, caculate TX vref
8892 13:22:17.307483 TX Vref=16, minBit 0, minWin=22, winSum=379
8893 13:22:17.310508 TX Vref=18, minBit 0, minWin=22, winSum=389
8894 13:22:17.314241 TX Vref=20, minBit 0, minWin=23, winSum=400
8895 13:22:17.317283 TX Vref=22, minBit 0, minWin=24, winSum=406
8896 13:22:17.320231 TX Vref=24, minBit 0, minWin=25, winSum=412
8897 13:22:17.327118 TX Vref=26, minBit 0, minWin=25, winSum=422
8898 13:22:17.330947 TX Vref=28, minBit 5, minWin=25, winSum=425
8899 13:22:17.333738 TX Vref=30, minBit 1, minWin=25, winSum=420
8900 13:22:17.337072 TX Vref=32, minBit 1, minWin=25, winSum=415
8901 13:22:17.340326 TX Vref=34, minBit 1, minWin=24, winSum=404
8902 13:22:17.343432 TX Vref=36, minBit 0, minWin=23, winSum=396
8903 13:22:17.350544 [TxChooseVref] Worse bit 5, Min win 25, Win sum 425, Final Vref 28
8904 13:22:17.350660
8905 13:22:17.353544 Final TX Range 0 Vref 28
8906 13:22:17.353650
8907 13:22:17.353757 ==
8908 13:22:17.356557 Dram Type= 6, Freq= 0, CH_1, rank 1
8909 13:22:17.360138 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8910 13:22:17.360221 ==
8911 13:22:17.360309
8912 13:22:17.363638
8913 13:22:17.363716 TX Vref Scan disable
8914 13:22:17.369930 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8915 13:22:17.370044 == TX Byte 0 ==
8916 13:22:17.373110 u2DelayCellOfst[0]=18 cells (5 PI)
8917 13:22:17.376673 u2DelayCellOfst[1]=15 cells (4 PI)
8918 13:22:17.380248 u2DelayCellOfst[2]=0 cells (0 PI)
8919 13:22:17.383350 u2DelayCellOfst[3]=11 cells (3 PI)
8920 13:22:17.386631 u2DelayCellOfst[4]=11 cells (3 PI)
8921 13:22:17.390159 u2DelayCellOfst[5]=26 cells (7 PI)
8922 13:22:17.393589 u2DelayCellOfst[6]=22 cells (6 PI)
8923 13:22:17.396503 u2DelayCellOfst[7]=11 cells (3 PI)
8924 13:22:17.399952 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8925 13:22:17.403443 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8926 13:22:17.406279 == TX Byte 1 ==
8927 13:22:17.409766 u2DelayCellOfst[8]=0 cells (0 PI)
8928 13:22:17.412793 u2DelayCellOfst[9]=7 cells (2 PI)
8929 13:22:17.416396 u2DelayCellOfst[10]=15 cells (4 PI)
8930 13:22:17.420003 u2DelayCellOfst[11]=7 cells (2 PI)
8931 13:22:17.422970 u2DelayCellOfst[12]=15 cells (4 PI)
8932 13:22:17.423081 u2DelayCellOfst[13]=18 cells (5 PI)
8933 13:22:17.426094 u2DelayCellOfst[14]=22 cells (6 PI)
8934 13:22:17.429882 u2DelayCellOfst[15]=18 cells (5 PI)
8935 13:22:17.436489 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8936 13:22:17.439694 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8937 13:22:17.443204 DramC Write-DBI on
8938 13:22:17.443290 ==
8939 13:22:17.446071 Dram Type= 6, Freq= 0, CH_1, rank 1
8940 13:22:17.449793 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8941 13:22:17.449912 ==
8942 13:22:17.450006
8943 13:22:17.450107
8944 13:22:17.452853 TX Vref Scan disable
8945 13:22:17.452957 == TX Byte 0 ==
8946 13:22:17.459655 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8947 13:22:17.459772 == TX Byte 1 ==
8948 13:22:17.462933 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8949 13:22:17.465697 DramC Write-DBI off
8950 13:22:17.465809
8951 13:22:17.465909 [DATLAT]
8952 13:22:17.469237 Freq=1600, CH1 RK1
8953 13:22:17.469314
8954 13:22:17.469378 DATLAT Default: 0xf
8955 13:22:17.472766 0, 0xFFFF, sum = 0
8956 13:22:17.472854 1, 0xFFFF, sum = 0
8957 13:22:17.476163 2, 0xFFFF, sum = 0
8958 13:22:17.476256 3, 0xFFFF, sum = 0
8959 13:22:17.479077 4, 0xFFFF, sum = 0
8960 13:22:17.479194 5, 0xFFFF, sum = 0
8961 13:22:17.482463 6, 0xFFFF, sum = 0
8962 13:22:17.485947 7, 0xFFFF, sum = 0
8963 13:22:17.486036 8, 0xFFFF, sum = 0
8964 13:22:17.488922 9, 0xFFFF, sum = 0
8965 13:22:17.489014 10, 0xFFFF, sum = 0
8966 13:22:17.492413 11, 0xFFFF, sum = 0
8967 13:22:17.492493 12, 0xFFFF, sum = 0
8968 13:22:17.495519 13, 0x8FFF, sum = 0
8969 13:22:17.495609 14, 0x0, sum = 1
8970 13:22:17.499065 15, 0x0, sum = 2
8971 13:22:17.499144 16, 0x0, sum = 3
8972 13:22:17.502632 17, 0x0, sum = 4
8973 13:22:17.502762 best_step = 15
8974 13:22:17.502836
8975 13:22:17.502898 ==
8976 13:22:17.505573 Dram Type= 6, Freq= 0, CH_1, rank 1
8977 13:22:17.509072 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8978 13:22:17.512281 ==
8979 13:22:17.512361 RX Vref Scan: 0
8980 13:22:17.512438
8981 13:22:17.515780 RX Vref 0 -> 0, step: 1
8982 13:22:17.515861
8983 13:22:17.515927 RX Delay 11 -> 252, step: 4
8984 13:22:17.523065 iDelay=195, Bit 0, Center 136 (83 ~ 190) 108
8985 13:22:17.526145 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
8986 13:22:17.529676 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8987 13:22:17.533062 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8988 13:22:17.536002 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
8989 13:22:17.543009 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
8990 13:22:17.545905 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8991 13:22:17.549325 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8992 13:22:17.552668 iDelay=195, Bit 8, Center 108 (51 ~ 166) 116
8993 13:22:17.556362 iDelay=195, Bit 9, Center 114 (59 ~ 170) 112
8994 13:22:17.562613 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8995 13:22:17.565735 iDelay=195, Bit 11, Center 118 (63 ~ 174) 112
8996 13:22:17.568930 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8997 13:22:17.572457 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8998 13:22:17.579284 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
8999 13:22:17.582355 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
9000 13:22:17.582433 ==
9001 13:22:17.586046 Dram Type= 6, Freq= 0, CH_1, rank 1
9002 13:22:17.589032 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9003 13:22:17.589123 ==
9004 13:22:17.592501 DQS Delay:
9005 13:22:17.592629 DQS0 = 0, DQS1 = 0
9006 13:22:17.592725 DQM Delay:
9007 13:22:17.595786 DQM0 = 129, DQM1 = 124
9008 13:22:17.595859 DQ Delay:
9009 13:22:17.599316 DQ0 =136, DQ1 =128, DQ2 =116, DQ3 =126
9010 13:22:17.602407 DQ4 =124, DQ5 =140, DQ6 =140, DQ7 =126
9011 13:22:17.605728 DQ8 =108, DQ9 =114, DQ10 =128, DQ11 =118
9012 13:22:17.612197 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
9013 13:22:17.612287
9014 13:22:17.612353
9015 13:22:17.612425
9016 13:22:17.615962 [DramC_TX_OE_Calibration] TA2
9017 13:22:17.616043 Original DQ_B0 (3 6) =30, OEN = 27
9018 13:22:17.619153 Original DQ_B1 (3 6) =30, OEN = 27
9019 13:22:17.622599 24, 0x0, End_B0=24 End_B1=24
9020 13:22:17.625570 25, 0x0, End_B0=25 End_B1=25
9021 13:22:17.629158 26, 0x0, End_B0=26 End_B1=26
9022 13:22:17.632185 27, 0x0, End_B0=27 End_B1=27
9023 13:22:17.632263 28, 0x0, End_B0=28 End_B1=28
9024 13:22:17.635844 29, 0x0, End_B0=29 End_B1=29
9025 13:22:17.639003 30, 0x0, End_B0=30 End_B1=30
9026 13:22:17.642530 31, 0x4141, End_B0=30 End_B1=30
9027 13:22:17.645343 Byte0 end_step=30 best_step=27
9028 13:22:17.645420 Byte1 end_step=30 best_step=27
9029 13:22:17.648933 Byte0 TX OE(2T, 0.5T) = (3, 3)
9030 13:22:17.652400 Byte1 TX OE(2T, 0.5T) = (3, 3)
9031 13:22:17.652485
9032 13:22:17.652550
9033 13:22:17.662396 [DQSOSCAuto] RK1, (LSB)MR18= 0x131f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
9034 13:22:17.662487 CH1 RK1: MR19=303, MR18=131F
9035 13:22:17.668478 CH1_RK1: MR19=0x303, MR18=0x131F, DQSOSC=394, MR23=63, INC=23, DEC=15
9036 13:22:17.671980 [RxdqsGatingPostProcess] freq 1600
9037 13:22:17.678562 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9038 13:22:17.682158 best DQS0 dly(2T, 0.5T) = (1, 1)
9039 13:22:17.685305 best DQS1 dly(2T, 0.5T) = (1, 1)
9040 13:22:17.688599 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9041 13:22:17.692172 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9042 13:22:17.692265 best DQS0 dly(2T, 0.5T) = (1, 1)
9043 13:22:17.695327 best DQS1 dly(2T, 0.5T) = (1, 1)
9044 13:22:17.698624 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9045 13:22:17.701837 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9046 13:22:17.705299 Pre-setting of DQS Precalculation
9047 13:22:17.712111 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9048 13:22:17.718348 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9049 13:22:17.725082 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9050 13:22:17.725175
9051 13:22:17.725243
9052 13:22:17.728021 [Calibration Summary] 3200 Mbps
9053 13:22:17.728138 CH 0, Rank 0
9054 13:22:17.731543 SW Impedance : PASS
9055 13:22:17.735210 DUTY Scan : NO K
9056 13:22:17.735289 ZQ Calibration : PASS
9057 13:22:17.738212 Jitter Meter : NO K
9058 13:22:17.741094 CBT Training : PASS
9059 13:22:17.741168 Write leveling : PASS
9060 13:22:17.744747 RX DQS gating : PASS
9061 13:22:17.748387 RX DQ/DQS(RDDQC) : PASS
9062 13:22:17.748467 TX DQ/DQS : PASS
9063 13:22:17.751179 RX DATLAT : PASS
9064 13:22:17.754499 RX DQ/DQS(Engine): PASS
9065 13:22:17.754608 TX OE : PASS
9066 13:22:17.757957 All Pass.
9067 13:22:17.758069
9068 13:22:17.758196 CH 0, Rank 1
9069 13:22:17.761145 SW Impedance : PASS
9070 13:22:17.761262 DUTY Scan : NO K
9071 13:22:17.764809 ZQ Calibration : PASS
9072 13:22:17.767619 Jitter Meter : NO K
9073 13:22:17.767700 CBT Training : PASS
9074 13:22:17.771309 Write leveling : PASS
9075 13:22:17.774426 RX DQS gating : PASS
9076 13:22:17.774543 RX DQ/DQS(RDDQC) : PASS
9077 13:22:17.778006 TX DQ/DQS : PASS
9078 13:22:17.780864 RX DATLAT : PASS
9079 13:22:17.780976 RX DQ/DQS(Engine): PASS
9080 13:22:17.784655 TX OE : PASS
9081 13:22:17.784788 All Pass.
9082 13:22:17.784885
9083 13:22:17.787422 CH 1, Rank 0
9084 13:22:17.787532 SW Impedance : PASS
9085 13:22:17.791086 DUTY Scan : NO K
9086 13:22:17.791217 ZQ Calibration : PASS
9087 13:22:17.794327 Jitter Meter : NO K
9088 13:22:17.797578 CBT Training : PASS
9089 13:22:17.797682 Write leveling : PASS
9090 13:22:17.801103 RX DQS gating : PASS
9091 13:22:17.804047 RX DQ/DQS(RDDQC) : PASS
9092 13:22:17.804135 TX DQ/DQS : PASS
9093 13:22:17.807658 RX DATLAT : PASS
9094 13:22:17.811019 RX DQ/DQS(Engine): PASS
9095 13:22:17.811166 TX OE : PASS
9096 13:22:17.814227 All Pass.
9097 13:22:17.814335
9098 13:22:17.814435 CH 1, Rank 1
9099 13:22:17.817329 SW Impedance : PASS
9100 13:22:17.817452 DUTY Scan : NO K
9101 13:22:17.820666 ZQ Calibration : PASS
9102 13:22:17.824347 Jitter Meter : NO K
9103 13:22:17.824432 CBT Training : PASS
9104 13:22:17.827264 Write leveling : PASS
9105 13:22:17.830803 RX DQS gating : PASS
9106 13:22:17.830906 RX DQ/DQS(RDDQC) : PASS
9107 13:22:17.833809 TX DQ/DQS : PASS
9108 13:22:17.837743 RX DATLAT : PASS
9109 13:22:17.837825 RX DQ/DQS(Engine): PASS
9110 13:22:17.840581 TX OE : PASS
9111 13:22:17.840655 All Pass.
9112 13:22:17.840754
9113 13:22:17.843727 DramC Write-DBI on
9114 13:22:17.847261 PER_BANK_REFRESH: Hybrid Mode
9115 13:22:17.847363 TX_TRACKING: ON
9116 13:22:17.857185 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9117 13:22:17.863605 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9118 13:22:17.870655 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9119 13:22:17.873833 [FAST_K] Save calibration result to emmc
9120 13:22:17.876808 sync common calibartion params.
9121 13:22:17.879824 sync cbt_mode0:1, 1:1
9122 13:22:17.883461 dram_init: ddr_geometry: 2
9123 13:22:17.883551 dram_init: ddr_geometry: 2
9124 13:22:17.887080 dram_init: ddr_geometry: 2
9125 13:22:17.890361 0:dram_rank_size:100000000
9126 13:22:17.893405 1:dram_rank_size:100000000
9127 13:22:17.896395 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9128 13:22:17.900212 DFS_SHUFFLE_HW_MODE: ON
9129 13:22:17.903155 dramc_set_vcore_voltage set vcore to 725000
9130 13:22:17.906449 Read voltage for 1600, 0
9131 13:22:17.906534 Vio18 = 0
9132 13:22:17.906598 Vcore = 725000
9133 13:22:17.910234 Vdram = 0
9134 13:22:17.910314 Vddq = 0
9135 13:22:17.910401 Vmddr = 0
9136 13:22:17.913271 switch to 3200 Mbps bootup
9137 13:22:17.916392 [DramcRunTimeConfig]
9138 13:22:17.916483 PHYPLL
9139 13:22:17.916549 DPM_CONTROL_AFTERK: ON
9140 13:22:17.919777 PER_BANK_REFRESH: ON
9141 13:22:17.923089 REFRESH_OVERHEAD_REDUCTION: ON
9142 13:22:17.923173 CMD_PICG_NEW_MODE: OFF
9143 13:22:17.926408 XRTWTW_NEW_MODE: ON
9144 13:22:17.929604 XRTRTR_NEW_MODE: ON
9145 13:22:17.929719 TX_TRACKING: ON
9146 13:22:17.933289 RDSEL_TRACKING: OFF
9147 13:22:17.933396 DQS Precalculation for DVFS: ON
9148 13:22:17.936343 RX_TRACKING: OFF
9149 13:22:17.936564 HW_GATING DBG: ON
9150 13:22:17.939640 ZQCS_ENABLE_LP4: ON
9151 13:22:17.939729 RX_PICG_NEW_MODE: ON
9152 13:22:17.942852 TX_PICG_NEW_MODE: ON
9153 13:22:17.946105 ENABLE_RX_DCM_DPHY: ON
9154 13:22:17.949604 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9155 13:22:17.949726 DUMMY_READ_FOR_TRACKING: OFF
9156 13:22:17.953280 !!! SPM_CONTROL_AFTERK: OFF
9157 13:22:17.956318 !!! SPM could not control APHY
9158 13:22:17.960021 IMPEDANCE_TRACKING: ON
9159 13:22:17.960114 TEMP_SENSOR: ON
9160 13:22:17.963023 HW_SAVE_FOR_SR: OFF
9161 13:22:17.963103 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9162 13:22:17.969747 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9163 13:22:17.969881 Read ODT Tracking: ON
9164 13:22:17.972778 Refresh Rate DeBounce: ON
9165 13:22:17.972901 DFS_NO_QUEUE_FLUSH: ON
9166 13:22:17.976360 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9167 13:22:17.979895 ENABLE_DFS_RUNTIME_MRW: OFF
9168 13:22:17.982876 DDR_RESERVE_NEW_MODE: ON
9169 13:22:17.982984 MR_CBT_SWITCH_FREQ: ON
9170 13:22:17.986520 =========================
9171 13:22:18.005916 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9172 13:22:18.009257 dram_init: ddr_geometry: 2
9173 13:22:18.027150 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9174 13:22:18.030324 dram_init: dram init end (result: 0)
9175 13:22:18.037291 DRAM-K: Full calibration passed in 24561 msecs
9176 13:22:18.040498 MRC: failed to locate region type 0.
9177 13:22:18.040581 DRAM rank0 size:0x100000000,
9178 13:22:18.043751 DRAM rank1 size=0x100000000
9179 13:22:18.053453 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9180 13:22:18.060203 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9181 13:22:18.067177 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9182 13:22:18.073887 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9183 13:22:18.077176 DRAM rank0 size:0x100000000,
9184 13:22:18.080525 DRAM rank1 size=0x100000000
9185 13:22:18.080614 CBMEM:
9186 13:22:18.083683 IMD: root @ 0xfffff000 254 entries.
9187 13:22:18.087269 IMD: root @ 0xffffec00 62 entries.
9188 13:22:18.090158 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9189 13:22:18.093794 WARNING: RO_VPD is uninitialized or empty.
9190 13:22:18.100295 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9191 13:22:18.107225 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9192 13:22:18.120140 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9193 13:22:18.131226 BS: romstage times (exec / console): total (unknown) / 24029 ms
9194 13:22:18.131355
9195 13:22:18.131477
9196 13:22:18.141684 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9197 13:22:18.144326 ARM64: Exception handlers installed.
9198 13:22:18.148214 ARM64: Testing exception
9199 13:22:18.151310 ARM64: Done test exception
9200 13:22:18.151435 Enumerating buses...
9201 13:22:18.154312 Show all devs... Before device enumeration.
9202 13:22:18.157665 Root Device: enabled 1
9203 13:22:18.161188 CPU_CLUSTER: 0: enabled 1
9204 13:22:18.161268 CPU: 00: enabled 1
9205 13:22:18.164134 Compare with tree...
9206 13:22:18.164208 Root Device: enabled 1
9207 13:22:18.168134 CPU_CLUSTER: 0: enabled 1
9208 13:22:18.170670 CPU: 00: enabled 1
9209 13:22:18.170743 Root Device scanning...
9210 13:22:18.174359 scan_static_bus for Root Device
9211 13:22:18.177374 CPU_CLUSTER: 0 enabled
9212 13:22:18.180798 scan_static_bus for Root Device done
9213 13:22:18.184187 scan_bus: bus Root Device finished in 8 msecs
9214 13:22:18.184302 done
9215 13:22:18.190949 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9216 13:22:18.194181 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9217 13:22:18.200840 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9218 13:22:18.204079 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9219 13:22:18.207310 Allocating resources...
9220 13:22:18.210552 Reading resources...
9221 13:22:18.214658 Root Device read_resources bus 0 link: 0
9222 13:22:18.214733 DRAM rank0 size:0x100000000,
9223 13:22:18.217475 DRAM rank1 size=0x100000000
9224 13:22:18.220845 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9225 13:22:18.223936 CPU: 00 missing read_resources
9226 13:22:18.231158 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9227 13:22:18.234228 Root Device read_resources bus 0 link: 0 done
9228 13:22:18.234304 Done reading resources.
9229 13:22:18.240796 Show resources in subtree (Root Device)...After reading.
9230 13:22:18.244314 Root Device child on link 0 CPU_CLUSTER: 0
9231 13:22:18.247122 CPU_CLUSTER: 0 child on link 0 CPU: 00
9232 13:22:18.257077 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9233 13:22:18.257195 CPU: 00
9234 13:22:18.260215 Root Device assign_resources, bus 0 link: 0
9235 13:22:18.263987 CPU_CLUSTER: 0 missing set_resources
9236 13:22:18.270416 Root Device assign_resources, bus 0 link: 0 done
9237 13:22:18.270502 Done setting resources.
9238 13:22:18.276942 Show resources in subtree (Root Device)...After assigning values.
9239 13:22:18.280484 Root Device child on link 0 CPU_CLUSTER: 0
9240 13:22:18.283549 CPU_CLUSTER: 0 child on link 0 CPU: 00
9241 13:22:18.293701 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9242 13:22:18.293785 CPU: 00
9243 13:22:18.297213 Done allocating resources.
9244 13:22:18.303495 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9245 13:22:18.303587 Enabling resources...
9246 13:22:18.303692 done.
9247 13:22:18.309994 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9248 13:22:18.310077 Initializing devices...
9249 13:22:18.313610 Root Device init
9250 13:22:18.313693 init hardware done!
9251 13:22:18.316633 0x00000018: ctrlr->caps
9252 13:22:18.320535 52.000 MHz: ctrlr->f_max
9253 13:22:18.320641 0.400 MHz: ctrlr->f_min
9254 13:22:18.324531 0x40ff8080: ctrlr->voltages
9255 13:22:18.327094 sclk: 390625
9256 13:22:18.327217 Bus Width = 1
9257 13:22:18.327316 sclk: 390625
9258 13:22:18.330354 Bus Width = 1
9259 13:22:18.330436 Early init status = 3
9260 13:22:18.336409 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9261 13:22:18.340039 in-header: 03 fc 00 00 01 00 00 00
9262 13:22:18.343675 in-data: 00
9263 13:22:18.346635 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9264 13:22:18.350045 in-header: 03 fd 00 00 00 00 00 00
9265 13:22:18.353327 in-data:
9266 13:22:18.356829 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9267 13:22:18.360510 in-header: 03 fc 00 00 01 00 00 00
9268 13:22:18.363224 in-data: 00
9269 13:22:18.366750 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9270 13:22:18.371101 in-header: 03 fd 00 00 00 00 00 00
9271 13:22:18.374757 in-data:
9272 13:22:18.377867 [SSUSB] Setting up USB HOST controller...
9273 13:22:18.380944 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9274 13:22:18.384422 [SSUSB] phy power-on done.
9275 13:22:18.388109 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9276 13:22:18.394713 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9277 13:22:18.397725 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9278 13:22:18.404808 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9279 13:22:18.411619 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9280 13:22:18.417566 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9281 13:22:18.424210 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9282 13:22:18.431005 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9283 13:22:18.434358 SPM: binary array size = 0x9dc
9284 13:22:18.437461 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9285 13:22:18.443952 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9286 13:22:18.450888 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9287 13:22:18.457329 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9288 13:22:18.460556 configure_display: Starting display init
9289 13:22:18.494541 anx7625_power_on_init: Init interface.
9290 13:22:18.498130 anx7625_disable_pd_protocol: Disabled PD feature.
9291 13:22:18.501099 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9292 13:22:18.529053 anx7625_start_dp_work: Secure OCM version=00
9293 13:22:18.532404 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9294 13:22:18.547329 sp_tx_get_edid_block: EDID Block = 1
9295 13:22:18.649490 Extracted contents:
9296 13:22:18.653154 header: 00 ff ff ff ff ff ff 00
9297 13:22:18.656228 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9298 13:22:18.659729 version: 01 04
9299 13:22:18.662822 basic params: 95 1f 11 78 0a
9300 13:22:18.666306 chroma info: 76 90 94 55 54 90 27 21 50 54
9301 13:22:18.669588 established: 00 00 00
9302 13:22:18.676630 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9303 13:22:18.679296 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9304 13:22:18.685880 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9305 13:22:18.692898 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9306 13:22:18.699075 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9307 13:22:18.702594 extensions: 00
9308 13:22:18.702677 checksum: fb
9309 13:22:18.702742
9310 13:22:18.705889 Manufacturer: IVO Model 57d Serial Number 0
9311 13:22:18.708948 Made week 0 of 2020
9312 13:22:18.709035 EDID version: 1.4
9313 13:22:18.712715 Digital display
9314 13:22:18.715963 6 bits per primary color channel
9315 13:22:18.716048 DisplayPort interface
9316 13:22:18.719246 Maximum image size: 31 cm x 17 cm
9317 13:22:18.722497 Gamma: 220%
9318 13:22:18.722594 Check DPMS levels
9319 13:22:18.725771 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9320 13:22:18.732253 First detailed timing is preferred timing
9321 13:22:18.732356 Established timings supported:
9322 13:22:18.735898 Standard timings supported:
9323 13:22:18.738777 Detailed timings
9324 13:22:18.742363 Hex of detail: 383680a07038204018303c0035ae10000019
9325 13:22:18.745904 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9326 13:22:18.752053 0780 0798 07c8 0820 hborder 0
9327 13:22:18.755910 0438 043b 0447 0458 vborder 0
9328 13:22:18.758837 -hsync -vsync
9329 13:22:18.758920 Did detailed timing
9330 13:22:18.765408 Hex of detail: 000000000000000000000000000000000000
9331 13:22:18.768713 Manufacturer-specified data, tag 0
9332 13:22:18.771916 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9333 13:22:18.775278 ASCII string: InfoVision
9334 13:22:18.778606 Hex of detail: 000000fe00523134304e574635205248200a
9335 13:22:18.782015 ASCII string: R140NWF5 RH
9336 13:22:18.782109 Checksum
9337 13:22:18.785466 Checksum: 0xfb (valid)
9338 13:22:18.788488 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9339 13:22:18.792047 DSI data_rate: 832800000 bps
9340 13:22:18.798665 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9341 13:22:18.802228 anx7625_parse_edid: pixelclock(138800).
9342 13:22:18.805236 hactive(1920), hsync(48), hfp(24), hbp(88)
9343 13:22:18.808525 vactive(1080), vsync(12), vfp(3), vbp(17)
9344 13:22:18.811646 anx7625_dsi_config: config dsi.
9345 13:22:18.818196 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9346 13:22:18.831615 anx7625_dsi_config: success to config DSI
9347 13:22:18.834716 anx7625_dp_start: MIPI phy setup OK.
9348 13:22:18.838635 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9349 13:22:18.841798 mtk_ddp_mode_set invalid vrefresh 60
9350 13:22:18.845261 main_disp_path_setup
9351 13:22:18.845369 ovl_layer_smi_id_en
9352 13:22:18.847974 ovl_layer_smi_id_en
9353 13:22:18.848048 ccorr_config
9354 13:22:18.848110 aal_config
9355 13:22:18.851248 gamma_config
9356 13:22:18.851355 postmask_config
9357 13:22:18.854566 dither_config
9358 13:22:18.857761 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9359 13:22:18.864531 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9360 13:22:18.868136 Root Device init finished in 551 msecs
9361 13:22:18.871497 CPU_CLUSTER: 0 init
9362 13:22:18.877904 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9363 13:22:18.881478 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9364 13:22:18.884422 APU_MBOX 0x190000b0 = 0x10001
9365 13:22:18.888522 APU_MBOX 0x190001b0 = 0x10001
9366 13:22:18.891073 APU_MBOX 0x190005b0 = 0x10001
9367 13:22:18.894644 APU_MBOX 0x190006b0 = 0x10001
9368 13:22:18.897782 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9369 13:22:18.910524 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9370 13:22:18.923122 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9371 13:22:18.929470 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9372 13:22:18.941095 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9373 13:22:18.950263 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9374 13:22:18.954140 CPU_CLUSTER: 0 init finished in 81 msecs
9375 13:22:18.957451 Devices initialized
9376 13:22:18.960453 Show all devs... After init.
9377 13:22:18.960537 Root Device: enabled 1
9378 13:22:18.963745 CPU_CLUSTER: 0: enabled 1
9379 13:22:18.967251 CPU: 00: enabled 1
9380 13:22:18.970281 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9381 13:22:18.973690 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9382 13:22:18.977231 ELOG: NV offset 0x57f000 size 0x1000
9383 13:22:18.983393 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9384 13:22:18.990016 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9385 13:22:18.993094 ELOG: Event(17) added with size 13 at 2023-09-06 13:22:22 UTC
9386 13:22:18.999781 out: cmd=0x121: 03 db 21 01 00 00 00 00
9387 13:22:19.003309 in-header: 03 6a 00 00 2c 00 00 00
9388 13:22:19.016534 in-data: f5 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9389 13:22:19.020127 ELOG: Event(A1) added with size 10 at 2023-09-06 13:22:22 UTC
9390 13:22:19.026331 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9391 13:22:19.032821 ELOG: Event(A0) added with size 9 at 2023-09-06 13:22:22 UTC
9392 13:22:19.036423 elog_add_boot_reason: Logged dev mode boot
9393 13:22:19.042904 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9394 13:22:19.042985 Finalize devices...
9395 13:22:19.045901 Devices finalized
9396 13:22:19.049316 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9397 13:22:19.053181 Writing coreboot table at 0xffe64000
9398 13:22:19.059644 0. 000000000010a000-0000000000113fff: RAMSTAGE
9399 13:22:19.062671 1. 0000000040000000-00000000400fffff: RAM
9400 13:22:19.065937 2. 0000000040100000-000000004032afff: RAMSTAGE
9401 13:22:19.069049 3. 000000004032b000-00000000545fffff: RAM
9402 13:22:19.072946 4. 0000000054600000-000000005465ffff: BL31
9403 13:22:19.079201 5. 0000000054660000-00000000ffe63fff: RAM
9404 13:22:19.082758 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9405 13:22:19.085842 7. 0000000100000000-000000023fffffff: RAM
9406 13:22:19.089155 Passing 5 GPIOs to payload:
9407 13:22:19.092380 NAME | PORT | POLARITY | VALUE
9408 13:22:19.099230 EC in RW | 0x000000aa | low | undefined
9409 13:22:19.102198 EC interrupt | 0x00000005 | low | undefined
9410 13:22:19.109281 TPM interrupt | 0x000000ab | high | undefined
9411 13:22:19.112370 SD card detect | 0x00000011 | high | undefined
9412 13:22:19.116032 speaker enable | 0x00000093 | high | undefined
9413 13:22:19.118943 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9414 13:22:19.122414 in-header: 03 f9 00 00 02 00 00 00
9415 13:22:19.125975 in-data: 02 00
9416 13:22:19.129730 ADC[4]: Raw value=896300 ID=7
9417 13:22:19.132722 ADC[3]: Raw value=212700 ID=1
9418 13:22:19.132803 RAM Code: 0x71
9419 13:22:19.136053 ADC[6]: Raw value=75092 ID=0
9420 13:22:19.138961 ADC[5]: Raw value=211960 ID=1
9421 13:22:19.139079 SKU Code: 0x1
9422 13:22:19.145636 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 2dff
9423 13:22:19.145723 coreboot table: 964 bytes.
9424 13:22:19.148803 IMD ROOT 0. 0xfffff000 0x00001000
9425 13:22:19.152438 IMD SMALL 1. 0xffffe000 0x00001000
9426 13:22:19.155495 RO MCACHE 2. 0xffffc000 0x00001104
9427 13:22:19.158687 CONSOLE 3. 0xfff7c000 0x00080000
9428 13:22:19.162544 FMAP 4. 0xfff7b000 0x00000452
9429 13:22:19.165485 TIME STAMP 5. 0xfff7a000 0x00000910
9430 13:22:19.169200 VBOOT WORK 6. 0xfff66000 0x00014000
9431 13:22:19.172028 RAMOOPS 7. 0xffe66000 0x00100000
9432 13:22:19.175537 COREBOOT 8. 0xffe64000 0x00002000
9433 13:22:19.179218 IMD small region:
9434 13:22:19.182054 IMD ROOT 0. 0xffffec00 0x00000400
9435 13:22:19.185410 VPD 1. 0xffffeb80 0x0000006c
9436 13:22:19.188545 MMC STATUS 2. 0xffffeb60 0x00000004
9437 13:22:19.192530 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9438 13:22:19.195607 Probing TPM: done!
9439 13:22:19.198996 Connected to device vid:did:rid of 1ae0:0028:00
9440 13:22:19.209967 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9441 13:22:19.213624 Initialized TPM device CR50 revision 0
9442 13:22:19.216912 Checking cr50 for pending updates
9443 13:22:19.221294 Reading cr50 TPM mode
9444 13:22:19.229752 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9445 13:22:19.236450 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9446 13:22:19.276523 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9447 13:22:19.280013 Checking segment from ROM address 0x40100000
9448 13:22:19.282785 Checking segment from ROM address 0x4010001c
9449 13:22:19.289444 Loading segment from ROM address 0x40100000
9450 13:22:19.289567 code (compression=0)
9451 13:22:19.296622 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9452 13:22:19.306306 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9453 13:22:19.306424 it's not compressed!
9454 13:22:19.313079 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9455 13:22:19.316481 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9456 13:22:19.336846 Loading segment from ROM address 0x4010001c
9457 13:22:19.336983 Entry Point 0x80000000
9458 13:22:19.339873 Loaded segments
9459 13:22:19.343502 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9460 13:22:19.349942 Jumping to boot code at 0x80000000(0xffe64000)
9461 13:22:19.356385 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9462 13:22:19.363397 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9463 13:22:19.370957 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9464 13:22:19.374673 Checking segment from ROM address 0x40100000
9465 13:22:19.377834 Checking segment from ROM address 0x4010001c
9466 13:22:19.384825 Loading segment from ROM address 0x40100000
9467 13:22:19.384919 code (compression=1)
9468 13:22:19.391265 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9469 13:22:19.401176 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9470 13:22:19.401261 using LZMA
9471 13:22:19.409583 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9472 13:22:19.416069 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9473 13:22:19.419788 Loading segment from ROM address 0x4010001c
9474 13:22:19.419878 Entry Point 0x54601000
9475 13:22:19.422760 Loaded segments
9476 13:22:19.426436 NOTICE: MT8192 bl31_setup
9477 13:22:19.433309 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9478 13:22:19.436558 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9479 13:22:19.439803 WARNING: region 0:
9480 13:22:19.442957 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9481 13:22:19.443050 WARNING: region 1:
9482 13:22:19.450046 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9483 13:22:19.453029 WARNING: region 2:
9484 13:22:19.456327 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9485 13:22:19.460333 WARNING: region 3:
9486 13:22:19.463381 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9487 13:22:19.466942 WARNING: region 4:
9488 13:22:19.473248 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9489 13:22:19.473333 WARNING: region 5:
9490 13:22:19.476590 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9491 13:22:19.479870 WARNING: region 6:
9492 13:22:19.483161 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9493 13:22:19.483246 WARNING: region 7:
9494 13:22:19.489724 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9495 13:22:19.496378 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9496 13:22:19.499819 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9497 13:22:19.503609 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9498 13:22:19.509738 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9499 13:22:19.513359 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9500 13:22:19.516587 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9501 13:22:19.523483 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9502 13:22:19.526575 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9503 13:22:19.533019 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9504 13:22:19.536274 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9505 13:22:19.539725 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9506 13:22:19.546494 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9507 13:22:19.550150 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9508 13:22:19.553023 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9509 13:22:19.559761 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9510 13:22:19.562928 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9511 13:22:19.569733 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9512 13:22:19.573504 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9513 13:22:19.576303 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9514 13:22:19.583010 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9515 13:22:19.586366 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9516 13:22:19.589768 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9517 13:22:19.596397 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9518 13:22:19.599593 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9519 13:22:19.606116 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9520 13:22:19.609555 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9521 13:22:19.612765 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9522 13:22:19.619971 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9523 13:22:19.622989 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9524 13:22:19.629694 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9525 13:22:19.632785 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9526 13:22:19.636218 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9527 13:22:19.642845 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9528 13:22:19.646580 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9529 13:22:19.649581 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9530 13:22:19.653125 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9531 13:22:19.659599 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9532 13:22:19.663195 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9533 13:22:19.666356 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9534 13:22:19.669518 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9535 13:22:19.673086 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9536 13:22:19.679664 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9537 13:22:19.683245 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9538 13:22:19.686245 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9539 13:22:19.693625 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9540 13:22:19.696426 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9541 13:22:19.700031 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9542 13:22:19.702945 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9543 13:22:19.710031 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9544 13:22:19.713171 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9545 13:22:19.719808 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9546 13:22:19.723059 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9547 13:22:19.726674 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9548 13:22:19.733441 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9549 13:22:19.736584 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9550 13:22:19.743320 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9551 13:22:19.746305 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9552 13:22:19.752960 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9553 13:22:19.756537 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9554 13:22:19.759989 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9555 13:22:19.766472 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9556 13:22:19.770283 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9557 13:22:19.776688 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9558 13:22:19.779806 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9559 13:22:19.786666 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9560 13:22:19.789598 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9561 13:22:19.793136 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9562 13:22:19.799563 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9563 13:22:19.803068 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9564 13:22:19.809770 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9565 13:22:19.813484 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9566 13:22:19.820060 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9567 13:22:19.823322 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9568 13:22:19.826375 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9569 13:22:19.833204 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9570 13:22:19.836311 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9571 13:22:19.843243 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9572 13:22:19.846653 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9573 13:22:19.853339 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9574 13:22:19.856817 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9575 13:22:19.859846 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9576 13:22:19.866624 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9577 13:22:19.870262 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9578 13:22:19.876721 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9579 13:22:19.879598 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9580 13:22:19.886181 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9581 13:22:19.889631 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9582 13:22:19.893343 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9583 13:22:19.899900 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9584 13:22:19.903335 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9585 13:22:19.909784 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9586 13:22:19.913269 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9587 13:22:19.919529 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9588 13:22:19.923496 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9589 13:22:19.929939 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9590 13:22:19.933662 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9591 13:22:19.936570 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9592 13:22:19.940175 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9593 13:22:19.946598 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9594 13:22:19.950189 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9595 13:22:19.953097 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9596 13:22:19.959852 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9597 13:22:19.963435 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9598 13:22:19.966720 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9599 13:22:19.973078 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9600 13:22:19.976576 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9601 13:22:19.983298 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9602 13:22:19.986279 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9603 13:22:19.989740 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9604 13:22:19.996777 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9605 13:22:19.999845 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9606 13:22:20.006880 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9607 13:22:20.010340 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9608 13:22:20.013278 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9609 13:22:20.020283 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9610 13:22:20.023307 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9611 13:22:20.026742 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9612 13:22:20.033119 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9613 13:22:20.036682 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9614 13:22:20.040409 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9615 13:22:20.043195 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9616 13:22:20.049959 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9617 13:22:20.053330 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9618 13:22:20.056422 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9619 13:22:20.063460 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9620 13:22:20.066541 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9621 13:22:20.070017 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9622 13:22:20.076505 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9623 13:22:20.080298 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9624 13:22:20.086870 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9625 13:22:20.090115 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9626 13:22:20.093302 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9627 13:22:20.100392 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9628 13:22:20.103424 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9629 13:22:20.106450 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9630 13:22:20.113328 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9631 13:22:20.116686 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9632 13:22:20.123184 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9633 13:22:20.126686 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9634 13:22:20.129747 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9635 13:22:20.136410 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9636 13:22:20.139798 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9637 13:22:20.146397 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9638 13:22:20.150135 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9639 13:22:20.153132 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9640 13:22:20.160318 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9641 13:22:20.163175 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9642 13:22:20.170073 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9643 13:22:20.173186 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9644 13:22:20.176592 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9645 13:22:20.183244 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9646 13:22:20.186214 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9647 13:22:20.189960 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9648 13:22:20.196500 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9649 13:22:20.199689 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9650 13:22:20.206411 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9651 13:22:20.209657 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9652 13:22:20.213028 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9653 13:22:20.219914 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9654 13:22:20.223640 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9655 13:22:20.229996 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9656 13:22:20.232832 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9657 13:22:20.236222 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9658 13:22:20.243204 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9659 13:22:20.245988 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9660 13:22:20.252495 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9661 13:22:20.256202 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9662 13:22:20.259653 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9663 13:22:20.266224 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9664 13:22:20.269442 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9665 13:22:20.275815 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9666 13:22:20.279553 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9667 13:22:20.282417 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9668 13:22:20.288944 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9669 13:22:20.292480 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9670 13:22:20.296035 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9671 13:22:20.302718 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9672 13:22:20.306175 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9673 13:22:20.312061 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9674 13:22:20.315530 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9675 13:22:20.318865 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9676 13:22:20.325595 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9677 13:22:20.329122 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9678 13:22:20.335885 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9679 13:22:20.339025 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9680 13:22:20.342554 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9681 13:22:20.348996 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9682 13:22:20.352365 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9683 13:22:20.358991 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9684 13:22:20.362480 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9685 13:22:20.365426 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9686 13:22:20.372013 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9687 13:22:20.375289 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9688 13:22:20.382003 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9689 13:22:20.385433 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9690 13:22:20.391968 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9691 13:22:20.395066 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9692 13:22:20.398343 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9693 13:22:20.404958 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9694 13:22:20.408379 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9695 13:22:20.415180 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9696 13:22:20.418524 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9697 13:22:20.424710 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9698 13:22:20.428392 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9699 13:22:20.431795 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9700 13:22:20.438249 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9701 13:22:20.441163 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9702 13:22:20.448020 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9703 13:22:20.451462 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9704 13:22:20.454729 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9705 13:22:20.461226 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9706 13:22:20.464672 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9707 13:22:20.471175 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9708 13:22:20.474263 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9709 13:22:20.481035 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9710 13:22:20.484416 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9711 13:22:20.487546 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9712 13:22:20.494010 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9713 13:22:20.497489 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9714 13:22:20.504231 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9715 13:22:20.507755 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9716 13:22:20.514165 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9717 13:22:20.517146 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9718 13:22:20.520936 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9719 13:22:20.527357 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9720 13:22:20.530440 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9721 13:22:20.536998 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9722 13:22:20.540460 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9723 13:22:20.547139 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9724 13:22:20.550561 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9725 13:22:20.553565 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9726 13:22:20.557158 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9727 13:22:20.560153 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9728 13:22:20.567054 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9729 13:22:20.570209 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9730 13:22:20.573647 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9731 13:22:20.580055 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9732 13:22:20.583385 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9733 13:22:20.590008 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9734 13:22:20.594121 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9735 13:22:20.596725 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9736 13:22:20.602992 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9737 13:22:20.606437 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9738 13:22:20.609856 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9739 13:22:20.616188 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9740 13:22:20.619403 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9741 13:22:20.626158 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9742 13:22:20.629964 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9743 13:22:20.633107 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9744 13:22:20.639422 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9745 13:22:20.642477 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9746 13:22:20.646247 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9747 13:22:20.652945 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9748 13:22:20.655988 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9749 13:22:20.662609 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9750 13:22:20.666098 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9751 13:22:20.669130 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9752 13:22:20.675576 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9753 13:22:20.679643 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9754 13:22:20.682550 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9755 13:22:20.689289 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9756 13:22:20.692274 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9757 13:22:20.699113 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9758 13:22:20.702532 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9759 13:22:20.705506 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9760 13:22:20.712244 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9761 13:22:20.715217 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9762 13:22:20.722280 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9763 13:22:20.725355 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9764 13:22:20.728650 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9765 13:22:20.731674 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9766 13:22:20.735143 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9767 13:22:20.741829 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9768 13:22:20.745059 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9769 13:22:20.748404 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9770 13:22:20.751539 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9771 13:22:20.758304 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9772 13:22:20.761484 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9773 13:22:20.765058 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9774 13:22:20.768590 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9775 13:22:20.775046 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9776 13:22:20.778070 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9777 13:22:20.781717 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9778 13:22:20.788214 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9779 13:22:20.791773 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9780 13:22:20.797943 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9781 13:22:20.801083 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9782 13:22:20.807879 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9783 13:22:20.811330 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9784 13:22:20.814443 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9785 13:22:20.821020 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9786 13:22:20.824733 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9787 13:22:20.831092 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9788 13:22:20.834075 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9789 13:22:20.841012 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9790 13:22:20.844264 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9791 13:22:20.847843 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9792 13:22:20.854208 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9793 13:22:20.857480 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9794 13:22:20.860789 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9795 13:22:20.867255 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9796 13:22:20.870602 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9797 13:22:20.877740 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9798 13:22:20.880681 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9799 13:22:20.887102 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9800 13:22:20.890696 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9801 13:22:20.893778 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9802 13:22:20.900351 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9803 13:22:20.903615 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9804 13:22:20.910536 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9805 13:22:20.914081 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9806 13:22:20.920532 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9807 13:22:20.923742 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9808 13:22:20.927353 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9809 13:22:20.933734 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9810 13:22:20.936798 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9811 13:22:20.944002 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9812 13:22:20.946728 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9813 13:22:20.950108 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9814 13:22:20.957248 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9815 13:22:20.960326 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9816 13:22:20.963353 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9817 13:22:20.969971 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9818 13:22:20.973687 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9819 13:22:20.980278 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9820 13:22:20.983718 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9821 13:22:20.990195 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9822 13:22:20.993656 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9823 13:22:20.999798 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9824 13:22:21.003158 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9825 13:22:21.006593 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9826 13:22:21.013211 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9827 13:22:21.016588 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9828 13:22:21.022967 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9829 13:22:21.026812 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9830 13:22:21.029677 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9831 13:22:21.036215 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9832 13:22:21.039972 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9833 13:22:21.046268 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9834 13:22:21.049596 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9835 13:22:21.053377 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9836 13:22:21.059899 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9837 13:22:21.063309 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9838 13:22:21.069952 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9839 13:22:21.073082 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9840 13:22:21.076232 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9841 13:22:21.083018 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9842 13:22:21.086135 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9843 13:22:21.092858 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9844 13:22:21.096511 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9845 13:22:21.099488 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9846 13:22:21.106145 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9847 13:22:21.109639 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9848 13:22:21.116422 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9849 13:22:21.119504 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9850 13:22:21.125892 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9851 13:22:21.129385 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9852 13:22:21.132843 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9853 13:22:21.139444 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9854 13:22:21.142283 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9855 13:22:21.149663 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9856 13:22:21.152250 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9857 13:22:21.158799 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9858 13:22:21.162301 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9859 13:22:21.168929 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9860 13:22:21.172042 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9861 13:22:21.175606 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9862 13:22:21.182131 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9863 13:22:21.185800 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9864 13:22:21.192438 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9865 13:22:21.195480 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9866 13:22:21.202212 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9867 13:22:21.205704 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9868 13:22:21.208671 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9869 13:22:21.215464 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9870 13:22:21.218599 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9871 13:22:21.225254 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9872 13:22:21.228699 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9873 13:22:21.235482 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9874 13:22:21.238713 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9875 13:22:21.241966 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9876 13:22:21.248705 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9877 13:22:21.251800 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9878 13:22:21.258986 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9879 13:22:21.261860 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9880 13:22:21.268421 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9881 13:22:21.271869 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9882 13:22:21.278637 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9883 13:22:21.281535 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9884 13:22:21.285095 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9885 13:22:21.291840 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9886 13:22:21.295192 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9887 13:22:21.301481 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9888 13:22:21.304933 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9889 13:22:21.311283 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9890 13:22:21.314860 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9891 13:22:21.318513 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9892 13:22:21.325239 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9893 13:22:21.328132 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9894 13:22:21.334822 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9895 13:22:21.338390 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9896 13:22:21.344872 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9897 13:22:21.348309 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9898 13:22:21.351157 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9899 13:22:21.358017 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9900 13:22:21.361030 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9901 13:22:21.367944 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9902 13:22:21.371255 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9903 13:22:21.377580 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9904 13:22:21.381078 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9905 13:22:21.387791 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9906 13:22:21.391467 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9907 13:22:21.397861 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9908 13:22:21.401318 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9909 13:22:21.407827 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9910 13:22:21.410879 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9911 13:22:21.417405 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9912 13:22:21.420800 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9913 13:22:21.428059 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9914 13:22:21.431058 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9915 13:22:21.437663 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9916 13:22:21.441384 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9917 13:22:21.447811 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9918 13:22:21.450823 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9919 13:22:21.457237 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9920 13:22:21.460606 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9921 13:22:21.467524 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9922 13:22:21.470522 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9923 13:22:21.477299 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9924 13:22:21.480687 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9925 13:22:21.487247 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9926 13:22:21.490592 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9927 13:22:21.497214 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9928 13:22:21.500688 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9929 13:22:21.503876 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9930 13:22:21.507349 INFO: [APUAPC] vio 0
9931 13:22:21.510539 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9932 13:22:21.517345 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9933 13:22:21.520733 INFO: [APUAPC] D0_APC_0: 0x400510
9934 13:22:21.524215 INFO: [APUAPC] D0_APC_1: 0x0
9935 13:22:21.527117 INFO: [APUAPC] D0_APC_2: 0x1540
9936 13:22:21.527252 INFO: [APUAPC] D0_APC_3: 0x0
9937 13:22:21.533826 INFO: [APUAPC] D1_APC_0: 0xffffffff
9938 13:22:21.536928 INFO: [APUAPC] D1_APC_1: 0xffffffff
9939 13:22:21.540764 INFO: [APUAPC] D1_APC_2: 0x3fffff
9940 13:22:21.540871 INFO: [APUAPC] D1_APC_3: 0x0
9941 13:22:21.544147 INFO: [APUAPC] D2_APC_0: 0xffffffff
9942 13:22:21.546862 INFO: [APUAPC] D2_APC_1: 0xffffffff
9943 13:22:21.550400 INFO: [APUAPC] D2_APC_2: 0x3fffff
9944 13:22:21.553441 INFO: [APUAPC] D2_APC_3: 0x0
9945 13:22:21.557098 INFO: [APUAPC] D3_APC_0: 0xffffffff
9946 13:22:21.560116 INFO: [APUAPC] D3_APC_1: 0xffffffff
9947 13:22:21.563691 INFO: [APUAPC] D3_APC_2: 0x3fffff
9948 13:22:21.567259 INFO: [APUAPC] D3_APC_3: 0x0
9949 13:22:21.570416 INFO: [APUAPC] D4_APC_0: 0xffffffff
9950 13:22:21.573639 INFO: [APUAPC] D4_APC_1: 0xffffffff
9951 13:22:21.577162 INFO: [APUAPC] D4_APC_2: 0x3fffff
9952 13:22:21.580126 INFO: [APUAPC] D4_APC_3: 0x0
9953 13:22:21.584135 INFO: [APUAPC] D5_APC_0: 0xffffffff
9954 13:22:21.586884 INFO: [APUAPC] D5_APC_1: 0xffffffff
9955 13:22:21.590011 INFO: [APUAPC] D5_APC_2: 0x3fffff
9956 13:22:21.593641 INFO: [APUAPC] D5_APC_3: 0x0
9957 13:22:21.596826 INFO: [APUAPC] D6_APC_0: 0xffffffff
9958 13:22:21.600209 INFO: [APUAPC] D6_APC_1: 0xffffffff
9959 13:22:21.603487 INFO: [APUAPC] D6_APC_2: 0x3fffff
9960 13:22:21.607222 INFO: [APUAPC] D6_APC_3: 0x0
9961 13:22:21.609954 INFO: [APUAPC] D7_APC_0: 0xffffffff
9962 13:22:21.613443 INFO: [APUAPC] D7_APC_1: 0xffffffff
9963 13:22:21.617030 INFO: [APUAPC] D7_APC_2: 0x3fffff
9964 13:22:21.619829 INFO: [APUAPC] D7_APC_3: 0x0
9965 13:22:21.623207 INFO: [APUAPC] D8_APC_0: 0xffffffff
9966 13:22:21.626697 INFO: [APUAPC] D8_APC_1: 0xffffffff
9967 13:22:21.629932 INFO: [APUAPC] D8_APC_2: 0x3fffff
9968 13:22:21.633279 INFO: [APUAPC] D8_APC_3: 0x0
9969 13:22:21.636368 INFO: [APUAPC] D9_APC_0: 0xffffffff
9970 13:22:21.639940 INFO: [APUAPC] D9_APC_1: 0xffffffff
9971 13:22:21.643511 INFO: [APUAPC] D9_APC_2: 0x3fffff
9972 13:22:21.646416 INFO: [APUAPC] D9_APC_3: 0x0
9973 13:22:21.650041 INFO: [APUAPC] D10_APC_0: 0xffffffff
9974 13:22:21.652942 INFO: [APUAPC] D10_APC_1: 0xffffffff
9975 13:22:21.656117 INFO: [APUAPC] D10_APC_2: 0x3fffff
9976 13:22:21.659478 INFO: [APUAPC] D10_APC_3: 0x0
9977 13:22:21.663093 INFO: [APUAPC] D11_APC_0: 0xffffffff
9978 13:22:21.666190 INFO: [APUAPC] D11_APC_1: 0xffffffff
9979 13:22:21.669268 INFO: [APUAPC] D11_APC_2: 0x3fffff
9980 13:22:21.672772 INFO: [APUAPC] D11_APC_3: 0x0
9981 13:22:21.676219 INFO: [APUAPC] D12_APC_0: 0xffffffff
9982 13:22:21.679491 INFO: [APUAPC] D12_APC_1: 0xffffffff
9983 13:22:21.682648 INFO: [APUAPC] D12_APC_2: 0x3fffff
9984 13:22:21.686150 INFO: [APUAPC] D12_APC_3: 0x0
9985 13:22:21.689484 INFO: [APUAPC] D13_APC_0: 0xffffffff
9986 13:22:21.692396 INFO: [APUAPC] D13_APC_1: 0xffffffff
9987 13:22:21.695714 INFO: [APUAPC] D13_APC_2: 0x3fffff
9988 13:22:21.699773 INFO: [APUAPC] D13_APC_3: 0x0
9989 13:22:21.702489 INFO: [APUAPC] D14_APC_0: 0xffffffff
9990 13:22:21.705778 INFO: [APUAPC] D14_APC_1: 0xffffffff
9991 13:22:21.708896 INFO: [APUAPC] D14_APC_2: 0x3fffff
9992 13:22:21.712544 INFO: [APUAPC] D14_APC_3: 0x0
9993 13:22:21.715523 INFO: [APUAPC] D15_APC_0: 0xffffffff
9994 13:22:21.719069 INFO: [APUAPC] D15_APC_1: 0xffffffff
9995 13:22:21.722315 INFO: [APUAPC] D15_APC_2: 0x3fffff
9996 13:22:21.725841 INFO: [APUAPC] D15_APC_3: 0x0
9997 13:22:21.729135 INFO: [APUAPC] APC_CON: 0x4
9998 13:22:21.732415 INFO: [NOCDAPC] D0_APC_0: 0x0
9999 13:22:21.735471 INFO: [NOCDAPC] D0_APC_1: 0x0
10000 13:22:21.738767 INFO: [NOCDAPC] D1_APC_0: 0x0
10001 13:22:21.738882 INFO: [NOCDAPC] D1_APC_1: 0xfff
10002 13:22:21.742030 INFO: [NOCDAPC] D2_APC_0: 0x0
10003 13:22:21.745778 INFO: [NOCDAPC] D2_APC_1: 0xfff
10004 13:22:21.749154 INFO: [NOCDAPC] D3_APC_0: 0x0
10005 13:22:21.752196 INFO: [NOCDAPC] D3_APC_1: 0xfff
10006 13:22:21.755686 INFO: [NOCDAPC] D4_APC_0: 0x0
10007 13:22:21.758759 INFO: [NOCDAPC] D4_APC_1: 0xfff
10008 13:22:21.762519 INFO: [NOCDAPC] D5_APC_0: 0x0
10009 13:22:21.765674 INFO: [NOCDAPC] D5_APC_1: 0xfff
10010 13:22:21.768825 INFO: [NOCDAPC] D6_APC_0: 0x0
10011 13:22:21.771978 INFO: [NOCDAPC] D6_APC_1: 0xfff
10012 13:22:21.772061 INFO: [NOCDAPC] D7_APC_0: 0x0
10013 13:22:21.775368 INFO: [NOCDAPC] D7_APC_1: 0xfff
10014 13:22:21.778583 INFO: [NOCDAPC] D8_APC_0: 0x0
10015 13:22:21.782475 INFO: [NOCDAPC] D8_APC_1: 0xfff
10016 13:22:21.785368 INFO: [NOCDAPC] D9_APC_0: 0x0
10017 13:22:21.788528 INFO: [NOCDAPC] D9_APC_1: 0xfff
10018 13:22:21.792104 INFO: [NOCDAPC] D10_APC_0: 0x0
10019 13:22:21.795091 INFO: [NOCDAPC] D10_APC_1: 0xfff
10020 13:22:21.798549 INFO: [NOCDAPC] D11_APC_0: 0x0
10021 13:22:21.801939 INFO: [NOCDAPC] D11_APC_1: 0xfff
10022 13:22:21.805051 INFO: [NOCDAPC] D12_APC_0: 0x0
10023 13:22:21.808247 INFO: [NOCDAPC] D12_APC_1: 0xfff
10024 13:22:21.811812 INFO: [NOCDAPC] D13_APC_0: 0x0
10025 13:22:21.815263 INFO: [NOCDAPC] D13_APC_1: 0xfff
10026 13:22:21.815397 INFO: [NOCDAPC] D14_APC_0: 0x0
10027 13:22:21.818189 INFO: [NOCDAPC] D14_APC_1: 0xfff
10028 13:22:21.821790 INFO: [NOCDAPC] D15_APC_0: 0x0
10029 13:22:21.825451 INFO: [NOCDAPC] D15_APC_1: 0xfff
10030 13:22:21.828818 INFO: [NOCDAPC] APC_CON: 0x4
10031 13:22:21.831641 INFO: [APUAPC] set_apusys_apc done
10032 13:22:21.835431 INFO: [DEVAPC] devapc_init done
10033 13:22:21.838221 INFO: GICv3 without legacy support detected.
10034 13:22:21.845033 INFO: ARM GICv3 driver initialized in EL3
10035 13:22:21.848230 INFO: Maximum SPI INTID supported: 639
10036 13:22:21.851779 INFO: BL31: Initializing runtime services
10037 13:22:21.858184 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10038 13:22:21.858269 INFO: SPM: enable CPC mode
10039 13:22:21.864988 INFO: mcdi ready for mcusys-off-idle and system suspend
10040 13:22:21.868644 INFO: BL31: Preparing for EL3 exit to normal world
10041 13:22:21.875150 INFO: Entry point address = 0x80000000
10042 13:22:21.875236 INFO: SPSR = 0x8
10043 13:22:21.880939
10044 13:22:21.881021
10045 13:22:21.881087
10046 13:22:21.884528 Starting depthcharge on Spherion...
10047 13:22:21.884612
10048 13:22:21.884677 Wipe memory regions:
10049 13:22:21.884738
10050 13:22:21.885491 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10051 13:22:21.885596 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10052 13:22:21.885679 Setting prompt string to ['asurada:']
10053 13:22:21.885759 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10054 13:22:21.887581 [0x00000040000000, 0x00000054600000)
10055 13:22:22.009961
10056 13:22:22.010106 [0x00000054660000, 0x00000080000000)
10057 13:22:22.270577
10058 13:22:22.270728 [0x000000821a7280, 0x000000ffe64000)
10059 13:22:23.015356
10060 13:22:23.015535 [0x00000100000000, 0x00000240000000)
10061 13:22:24.905354
10062 13:22:24.908710 Initializing XHCI USB controller at 0x11200000.
10063 13:22:25.946198
10064 13:22:25.949495 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10065 13:22:25.949604
10066 13:22:25.949713
10067 13:22:25.949806
10068 13:22:25.950123 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10070 13:22:26.050501 asurada: tftpboot 192.168.201.1 11445610/tftp-deploy-rfkqokb0/kernel/image.itb 11445610/tftp-deploy-rfkqokb0/kernel/cmdline
10071 13:22:26.050700 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10072 13:22:26.050820 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10073 13:22:26.054913 tftpboot 192.168.201.1 11445610/tftp-deploy-rfkqokb0/kernel/image.itp-deploy-rfkqokb0/kernel/cmdline
10074 13:22:26.055025
10075 13:22:26.055120 Waiting for link
10076 13:22:26.215456
10077 13:22:26.215610 R8152: Initializing
10078 13:22:26.215708
10079 13:22:26.218802 Version 6 (ocp_data = 5c30)
10080 13:22:26.218923
10081 13:22:26.222233 R8152: Done initializing
10082 13:22:26.222338
10083 13:22:26.222446 Adding net device
10084 13:22:28.125475
10085 13:22:28.125653 done.
10086 13:22:28.125726
10087 13:22:28.125791 MAC: 00:24:32:30:78:ff
10088 13:22:28.125866
10089 13:22:28.129026 Sending DHCP discover... done.
10090 13:22:28.129122
10091 13:22:28.131981 Waiting for reply... done.
10092 13:22:28.132062
10093 13:22:28.135201 Sending DHCP request... done.
10094 13:22:28.135305
10095 13:22:28.139947 Waiting for reply... done.
10096 13:22:28.140037
10097 13:22:28.140104 My ip is 192.168.201.21
10098 13:22:28.140176
10099 13:22:28.143591 The DHCP server ip is 192.168.201.1
10100 13:22:28.143693
10101 13:22:28.150074 TFTP server IP predefined by user: 192.168.201.1
10102 13:22:28.150158
10103 13:22:28.156621 Bootfile predefined by user: 11445610/tftp-deploy-rfkqokb0/kernel/image.itb
10104 13:22:28.156730
10105 13:22:28.160011 Sending tftp read request... done.
10106 13:22:28.160130
10107 13:22:28.163682 Waiting for the transfer...
10108 13:22:28.163759
10109 13:22:28.714170 00000000 ################################################################
10110 13:22:28.714322
10111 13:22:29.264148 00080000 ################################################################
10112 13:22:29.264287
10113 13:22:29.808929 00100000 ################################################################
10114 13:22:29.809110
10115 13:22:30.349933 00180000 ################################################################
10116 13:22:30.350091
10117 13:22:30.895820 00200000 ################################################################
10118 13:22:30.895972
10119 13:22:31.456798 00280000 ################################################################
10120 13:22:31.456953
10121 13:22:32.009533 00300000 ################################################################
10122 13:22:32.009686
10123 13:22:32.567618 00380000 ################################################################
10124 13:22:32.567801
10125 13:22:33.126447 00400000 ################################################################
10126 13:22:33.126627
10127 13:22:33.692490 00480000 ################################################################
10128 13:22:33.692627
10129 13:22:34.268259 00500000 ################################################################
10130 13:22:34.268443
10131 13:22:34.836050 00580000 ################################################################
10132 13:22:34.836187
10133 13:22:35.394970 00600000 ################################################################
10134 13:22:35.395150
10135 13:22:35.961974 00680000 ################################################################
10136 13:22:35.962119
10137 13:22:36.531706 00700000 ################################################################
10138 13:22:36.531895
10139 13:22:37.091015 00780000 ################################################################
10140 13:22:37.091158
10141 13:22:37.654940 00800000 ################################################################
10142 13:22:37.655117
10143 13:22:38.208940 00880000 ################################################################
10144 13:22:38.209116
10145 13:22:38.768146 00900000 ################################################################
10146 13:22:38.768282
10147 13:22:39.328480 00980000 ################################################################
10148 13:22:39.328619
10149 13:22:39.895139 00a00000 ################################################################
10150 13:22:39.895293
10151 13:22:40.463238 00a80000 ################################################################
10152 13:22:40.463425
10153 13:22:41.037128 00b00000 ################################################################
10154 13:22:41.037283
10155 13:22:41.607320 00b80000 ################################################################
10156 13:22:41.607509
10157 13:22:42.169962 00c00000 ################################################################
10158 13:22:42.170116
10159 13:22:42.735505 00c80000 ################################################################
10160 13:22:42.735651
10161 13:22:43.301829 00d00000 ################################################################
10162 13:22:43.301983
10163 13:22:43.867665 00d80000 ################################################################
10164 13:22:43.867831
10165 13:22:44.438257 00e00000 ################################################################
10166 13:22:44.438418
10167 13:22:45.011276 00e80000 ################################################################
10168 13:22:45.011478
10169 13:22:45.586921 00f00000 ################################################################
10170 13:22:45.587062
10171 13:22:46.163009 00f80000 ################################################################
10172 13:22:46.163158
10173 13:22:46.712257 01000000 ################################################################
10174 13:22:46.712427
10175 13:22:47.276961 01080000 ################################################################
10176 13:22:47.277099
10177 13:22:47.854648 01100000 ################################################################
10178 13:22:47.854785
10179 13:22:48.438456 01180000 ################################################################
10180 13:22:48.438612
10181 13:22:49.017687 01200000 ################################################################
10182 13:22:49.017878
10183 13:22:49.609868 01280000 ################################################################
10184 13:22:49.610061
10185 13:22:50.170465 01300000 ################################################################
10186 13:22:50.170677
10187 13:22:50.735732 01380000 ################################################################
10188 13:22:50.735887
10189 13:22:51.308390 01400000 ################################################################
10190 13:22:51.308546
10191 13:22:51.892858 01480000 ################################################################
10192 13:22:51.893038
10193 13:22:52.489540 01500000 ################################################################
10194 13:22:52.489691
10195 13:22:53.053039 01580000 ################################################################
10196 13:22:53.053193
10197 13:22:53.620181 01600000 ################################################################
10198 13:22:53.620336
10199 13:22:54.189597 01680000 ################################################################
10200 13:22:54.189754
10201 13:22:54.781773 01700000 ################################################################
10202 13:22:54.781928
10203 13:22:55.338630 01780000 ################################################################
10204 13:22:55.338789
10205 13:22:55.914097 01800000 ################################################################
10206 13:22:55.914252
10207 13:22:56.490423 01880000 ################################################################
10208 13:22:56.490584
10209 13:22:57.049392 01900000 ################################################################
10210 13:22:57.049532
10211 13:22:57.613692 01980000 ################################################################
10212 13:22:57.613874
10213 13:22:58.180676 01a00000 ################################################################
10214 13:22:58.180819
10215 13:22:58.732267 01a80000 ################################################################
10216 13:22:58.732406
10217 13:22:59.303909 01b00000 ################################################################
10218 13:22:59.304053
10219 13:22:59.876264 01b80000 ################################################################
10220 13:22:59.876421
10221 13:23:00.444165 01c00000 ################################################################
10222 13:23:00.444707
10223 13:23:01.022191 01c80000 ################################################################
10224 13:23:01.022346
10225 13:23:01.606838 01d00000 ################################################################
10226 13:23:01.607018
10227 13:23:02.187832 01d80000 ################################################################
10228 13:23:02.187984
10229 13:23:02.774895 01e00000 ################################################################
10230 13:23:02.775043
10231 13:23:03.291555 01e80000 ########################################################### done.
10232 13:23:03.291704
10233 13:23:03.294992 The bootfile was 32459966 bytes long.
10234 13:23:03.295083
10235 13:23:03.298295 Sending tftp read request... done.
10236 13:23:03.298377
10237 13:23:03.298442 Waiting for the transfer...
10238 13:23:03.298503
10239 13:23:03.301381 00000000 # done.
10240 13:23:03.301465
10241 13:23:03.308117 Command line loaded dynamically from TFTP file: 11445610/tftp-deploy-rfkqokb0/kernel/cmdline
10242 13:23:03.308201
10243 13:23:03.321341 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10244 13:23:03.321428
10245 13:23:03.324450 Loading FIT.
10246 13:23:03.324531
10247 13:23:03.327824 Image ramdisk-1 has 21372432 bytes.
10248 13:23:03.327906
10249 13:23:03.330943 Image fdt-1 has 47278 bytes.
10250 13:23:03.331025
10251 13:23:03.331090 Image kernel-1 has 11038222 bytes.
10252 13:23:03.334687
10253 13:23:03.340836 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10254 13:23:03.340920
10255 13:23:03.360506 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10256 13:23:03.360598
10257 13:23:03.364475 Choosing best match conf-1 for compat google,spherion-rev2.
10258 13:23:03.368395
10259 13:23:03.372983 Connected to device vid:did:rid of 1ae0:0028:00
10260 13:23:03.379952
10261 13:23:03.383450 tpm_get_response: command 0x17b, return code 0x0
10262 13:23:03.383534
10263 13:23:03.386702 ec_init: CrosEC protocol v3 supported (256, 248)
10264 13:23:03.390815
10265 13:23:03.394212 tpm_cleanup: add release locality here.
10266 13:23:03.394295
10267 13:23:03.394359 Shutting down all USB controllers.
10268 13:23:03.397451
10269 13:23:03.397531 Removing current net device
10270 13:23:03.397597
10271 13:23:03.404497 Exiting depthcharge with code 4 at timestamp: 70819225
10272 13:23:03.404579
10273 13:23:03.407350 LZMA decompressing kernel-1 to 0x821a6718
10274 13:23:03.407442
10275 13:23:03.410875 LZMA decompressing kernel-1 to 0x40000000
10276 13:23:04.797590
10277 13:23:04.797755 jumping to kernel
10278 13:23:04.798196 end: 2.2.4 bootloader-commands (duration 00:00:43) [common]
10279 13:23:04.798310 start: 2.2.5 auto-login-action (timeout 00:03:42) [common]
10280 13:23:04.798414 Setting prompt string to ['Linux version [0-9]']
10281 13:23:04.798510 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10282 13:23:04.798604 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10283 13:23:04.879523
10284 13:23:04.883255 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10285 13:23:04.886674 start: 2.2.5.1 login-action (timeout 00:03:42) [common]
10286 13:23:04.886769 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10287 13:23:04.886841 Setting prompt string to []
10288 13:23:04.886924 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10289 13:23:04.886998 Using line separator: #'\n'#
10290 13:23:04.887057 No login prompt set.
10291 13:23:04.887116 Parsing kernel messages
10292 13:23:04.887171 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10293 13:23:04.887272 [login-action] Waiting for messages, (timeout 00:03:42)
10294 13:23:04.906141 [ 0.000000] Linux version 6.1.46-cip4 (KernelCI@build-j36642-arm64-gcc-10-defconfig-arm64-chromebook-rxg94) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Sep 6 13:11:19 UTC 2023
10295 13:23:04.909848 [ 0.000000] random: crng init done
10296 13:23:04.916145 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10297 13:23:04.919168 [ 0.000000] efi: UEFI not found.
10298 13:23:04.925861 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10299 13:23:04.932636 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10300 13:23:04.942194 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10301 13:23:04.952520 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10302 13:23:04.958754 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10303 13:23:04.965237 [ 0.000000] printk: bootconsole [mtk8250] enabled
10304 13:23:04.972149 [ 0.000000] NUMA: No NUMA configuration found
10305 13:23:04.978896 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10306 13:23:04.981519 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10307 13:23:04.985084 [ 0.000000] Zone ranges:
10308 13:23:04.991764 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10309 13:23:04.994784 [ 0.000000] DMA32 empty
10310 13:23:05.001549 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10311 13:23:05.005131 [ 0.000000] Movable zone start for each node
10312 13:23:05.007983 [ 0.000000] Early memory node ranges
10313 13:23:05.014876 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10314 13:23:05.021220 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10315 13:23:05.028286 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10316 13:23:05.034721 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10317 13:23:05.041679 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10318 13:23:05.048231 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10319 13:23:05.104104 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10320 13:23:05.110869 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10321 13:23:05.117479 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10322 13:23:05.120380 [ 0.000000] psci: probing for conduit method from DT.
10323 13:23:05.127400 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10324 13:23:05.130152 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10325 13:23:05.137278 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10326 13:23:05.140187 [ 0.000000] psci: SMC Calling Convention v1.2
10327 13:23:05.146956 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10328 13:23:05.150572 [ 0.000000] Detected VIPT I-cache on CPU0
10329 13:23:05.156842 [ 0.000000] CPU features: detected: GIC system register CPU interface
10330 13:23:05.163560 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10331 13:23:05.170008 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10332 13:23:05.176546 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10333 13:23:05.183200 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10334 13:23:05.193048 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10335 13:23:05.196607 [ 0.000000] alternatives: applying boot alternatives
10336 13:23:05.203079 [ 0.000000] Fallback order for Node 0: 0
10337 13:23:05.210118 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10338 13:23:05.213214 [ 0.000000] Policy zone: Normal
10339 13:23:05.226342 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10340 13:23:05.236248 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10341 13:23:05.248214 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10342 13:23:05.258293 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10343 13:23:05.265048 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10344 13:23:05.267945 <6>[ 0.000000] software IO TLB: area num 8.
10345 13:23:05.325137 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10346 13:23:05.474681 <6>[ 0.000000] Memory: 7948684K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 404084K reserved, 32768K cma-reserved)
10347 13:23:05.481163 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10348 13:23:05.487872 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10349 13:23:05.491206 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10350 13:23:05.497686 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10351 13:23:05.504378 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10352 13:23:05.507375 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10353 13:23:05.517653 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10354 13:23:05.524045 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10355 13:23:05.530798 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10356 13:23:05.537270 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10357 13:23:05.540554 <6>[ 0.000000] GICv3: 608 SPIs implemented
10358 13:23:05.544036 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10359 13:23:05.550458 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10360 13:23:05.554026 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10361 13:23:05.560605 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10362 13:23:05.573620 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10363 13:23:05.586994 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10364 13:23:05.593744 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10365 13:23:05.601357 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10366 13:23:05.614419 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10367 13:23:05.620798 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10368 13:23:05.627747 <6>[ 0.009184] Console: colour dummy device 80x25
10369 13:23:05.637937 <6>[ 0.013920] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10370 13:23:05.644176 <6>[ 0.024362] pid_max: default: 32768 minimum: 301
10371 13:23:05.647667 <6>[ 0.029232] LSM: Security Framework initializing
10372 13:23:05.654127 <6>[ 0.034169] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10373 13:23:05.664141 <6>[ 0.041982] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10374 13:23:05.671006 <6>[ 0.051465] cblist_init_generic: Setting adjustable number of callback queues.
10375 13:23:05.677127 <6>[ 0.058958] cblist_init_generic: Setting shift to 3 and lim to 1.
10376 13:23:05.687215 <6>[ 0.065295] cblist_init_generic: Setting adjustable number of callback queues.
10377 13:23:05.693972 <6>[ 0.072767] cblist_init_generic: Setting shift to 3 and lim to 1.
10378 13:23:05.697560 <6>[ 0.079206] rcu: Hierarchical SRCU implementation.
10379 13:23:05.703849 <6>[ 0.084250] rcu: Max phase no-delay instances is 1000.
10380 13:23:05.710657 <6>[ 0.091319] EFI services will not be available.
10381 13:23:05.713749 <6>[ 0.096288] smp: Bringing up secondary CPUs ...
10382 13:23:05.722335 <6>[ 0.101343] Detected VIPT I-cache on CPU1
10383 13:23:05.728705 <6>[ 0.101414] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10384 13:23:05.735107 <6>[ 0.101447] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10385 13:23:05.738813 <6>[ 0.101780] Detected VIPT I-cache on CPU2
10386 13:23:05.748624 <6>[ 0.101832] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10387 13:23:05.755179 <6>[ 0.101848] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10388 13:23:05.758123 <6>[ 0.102107] Detected VIPT I-cache on CPU3
10389 13:23:05.764968 <6>[ 0.102153] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10390 13:23:05.771806 <6>[ 0.102168] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10391 13:23:05.775281 <6>[ 0.102473] CPU features: detected: Spectre-v4
10392 13:23:05.781969 <6>[ 0.102479] CPU features: detected: Spectre-BHB
10393 13:23:05.785325 <6>[ 0.102484] Detected PIPT I-cache on CPU4
10394 13:23:05.791492 <6>[ 0.102540] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10395 13:23:05.797967 <6>[ 0.102556] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10396 13:23:05.805317 <6>[ 0.102847] Detected PIPT I-cache on CPU5
10397 13:23:05.811255 <6>[ 0.102908] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10398 13:23:05.817930 <6>[ 0.102925] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10399 13:23:05.821517 <6>[ 0.103209] Detected PIPT I-cache on CPU6
10400 13:23:05.828222 <6>[ 0.103272] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10401 13:23:05.834744 <6>[ 0.103289] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10402 13:23:05.841183 <6>[ 0.103586] Detected PIPT I-cache on CPU7
10403 13:23:05.847804 <6>[ 0.103650] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10404 13:23:05.854457 <6>[ 0.103667] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10405 13:23:05.857755 <6>[ 0.103714] smp: Brought up 1 node, 8 CPUs
10406 13:23:05.864179 <6>[ 0.245115] SMP: Total of 8 processors activated.
10407 13:23:05.867762 <6>[ 0.250036] CPU features: detected: 32-bit EL0 Support
10408 13:23:05.877440 <6>[ 0.255431] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10409 13:23:05.884514 <6>[ 0.264232] CPU features: detected: Common not Private translations
10410 13:23:05.890860 <6>[ 0.270707] CPU features: detected: CRC32 instructions
10411 13:23:05.894236 <6>[ 0.276058] CPU features: detected: RCpc load-acquire (LDAPR)
10412 13:23:05.900725 <6>[ 0.282017] CPU features: detected: LSE atomic instructions
10413 13:23:05.907841 <6>[ 0.287799] CPU features: detected: Privileged Access Never
10414 13:23:05.914085 <6>[ 0.293578] CPU features: detected: RAS Extension Support
10415 13:23:05.920815 <6>[ 0.299187] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10416 13:23:05.924305 <6>[ 0.306409] CPU: All CPU(s) started at EL2
10417 13:23:05.930669 <6>[ 0.310752] alternatives: applying system-wide alternatives
10418 13:23:05.939788 <6>[ 0.321456] devtmpfs: initialized
10419 13:23:05.951882 <6>[ 0.330420] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10420 13:23:05.961905 <6>[ 0.340383] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10421 13:23:05.968970 <6>[ 0.348398] pinctrl core: initialized pinctrl subsystem
10422 13:23:05.972211 <6>[ 0.355048] DMI not present or invalid.
10423 13:23:05.978872 <6>[ 0.359461] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10424 13:23:05.988376 <6>[ 0.366253] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10425 13:23:05.995049 <6>[ 0.373832] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10426 13:23:06.004827 <6>[ 0.382047] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10427 13:23:06.008318 <6>[ 0.390289] audit: initializing netlink subsys (disabled)
10428 13:23:06.018184 <5>[ 0.395983] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10429 13:23:06.025011 <6>[ 0.396695] thermal_sys: Registered thermal governor 'step_wise'
10430 13:23:06.031879 <6>[ 0.403953] thermal_sys: Registered thermal governor 'power_allocator'
10431 13:23:06.034572 <6>[ 0.410208] cpuidle: using governor menu
10432 13:23:06.041193 <6>[ 0.421168] NET: Registered PF_QIPCRTR protocol family
10433 13:23:06.047915 <6>[ 0.426650] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10434 13:23:06.051058 <6>[ 0.433757] ASID allocator initialised with 32768 entries
10435 13:23:06.058718 <6>[ 0.440323] Serial: AMBA PL011 UART driver
10436 13:23:06.067628 <4>[ 0.449056] Trying to register duplicate clock ID: 134
10437 13:23:06.121733 <6>[ 0.506496] KASLR enabled
10438 13:23:06.135843 <6>[ 0.514247] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10439 13:23:06.142328 <6>[ 0.521262] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10440 13:23:06.149008 <6>[ 0.527752] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10441 13:23:06.155927 <6>[ 0.534758] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10442 13:23:06.162358 <6>[ 0.541243] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10443 13:23:06.168919 <6>[ 0.548247] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10444 13:23:06.175430 <6>[ 0.554731] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10445 13:23:06.181837 <6>[ 0.561734] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10446 13:23:06.185100 <6>[ 0.569242] ACPI: Interpreter disabled.
10447 13:23:06.193996 <6>[ 0.575646] iommu: Default domain type: Translated
10448 13:23:06.200462 <6>[ 0.580757] iommu: DMA domain TLB invalidation policy: strict mode
10449 13:23:06.203824 <5>[ 0.587410] SCSI subsystem initialized
10450 13:23:06.210166 <6>[ 0.591576] usbcore: registered new interface driver usbfs
10451 13:23:06.217237 <6>[ 0.597307] usbcore: registered new interface driver hub
10452 13:23:06.220325 <6>[ 0.602858] usbcore: registered new device driver usb
10453 13:23:06.227278 <6>[ 0.608946] pps_core: LinuxPPS API ver. 1 registered
10454 13:23:06.237239 <6>[ 0.614139] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10455 13:23:06.240593 <6>[ 0.623487] PTP clock support registered
10456 13:23:06.244193 <6>[ 0.627730] EDAC MC: Ver: 3.0.0
10457 13:23:06.251556 <6>[ 0.632883] FPGA manager framework
10458 13:23:06.257607 <6>[ 0.636561] Advanced Linux Sound Architecture Driver Initialized.
10459 13:23:06.261346 <6>[ 0.643335] vgaarb: loaded
10460 13:23:06.267847 <6>[ 0.646503] clocksource: Switched to clocksource arch_sys_counter
10461 13:23:06.271241 <5>[ 0.652939] VFS: Disk quotas dquot_6.6.0
10462 13:23:06.277549 <6>[ 0.657124] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10463 13:23:06.280569 <6>[ 0.664311] pnp: PnP ACPI: disabled
10464 13:23:06.289395 <6>[ 0.670968] NET: Registered PF_INET protocol family
10465 13:23:06.298979 <6>[ 0.676547] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10466 13:23:06.310404 <6>[ 0.688855] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10467 13:23:06.320138 <6>[ 0.697669] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10468 13:23:06.327052 <6>[ 0.705639] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10469 13:23:06.333809 <6>[ 0.714338] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10470 13:23:06.345925 <6>[ 0.724082] TCP: Hash tables configured (established 65536 bind 65536)
10471 13:23:06.352082 <6>[ 0.730945] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10472 13:23:06.358815 <6>[ 0.738144] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10473 13:23:06.365762 <6>[ 0.745842] NET: Registered PF_UNIX/PF_LOCAL protocol family
10474 13:23:06.372080 <6>[ 0.751984] RPC: Registered named UNIX socket transport module.
10475 13:23:06.375093 <6>[ 0.758137] RPC: Registered udp transport module.
10476 13:23:06.381801 <6>[ 0.763068] RPC: Registered tcp transport module.
10477 13:23:06.388428 <6>[ 0.767998] RPC: Registered tcp NFSv4.1 backchannel transport module.
10478 13:23:06.391750 <6>[ 0.774665] PCI: CLS 0 bytes, default 64
10479 13:23:06.395036 <6>[ 0.779027] Unpacking initramfs...
10480 13:23:06.421220 <6>[ 0.799221] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10481 13:23:06.431158 <6>[ 0.807864] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10482 13:23:06.433923 <6>[ 0.816690] kvm [1]: IPA Size Limit: 40 bits
10483 13:23:06.441017 <6>[ 0.821213] kvm [1]: GICv3: no GICV resource entry
10484 13:23:06.443780 <6>[ 0.826236] kvm [1]: disabling GICv2 emulation
10485 13:23:06.450811 <6>[ 0.830924] kvm [1]: GIC system register CPU interface enabled
10486 13:23:06.453936 <6>[ 0.837104] kvm [1]: vgic interrupt IRQ18
10487 13:23:06.460536 <6>[ 0.841466] kvm [1]: VHE mode initialized successfully
10488 13:23:06.467193 <5>[ 0.847854] Initialise system trusted keyrings
10489 13:23:06.473574 <6>[ 0.852653] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10490 13:23:06.481120 <6>[ 0.862667] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10491 13:23:06.487656 <5>[ 0.869032] NFS: Registering the id_resolver key type
10492 13:23:06.491057 <5>[ 0.874339] Key type id_resolver registered
10493 13:23:06.497644 <5>[ 0.878755] Key type id_legacy registered
10494 13:23:06.504357 <6>[ 0.883035] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10495 13:23:06.510805 <6>[ 0.889958] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10496 13:23:06.517723 <6>[ 0.897734] 9p: Installing v9fs 9p2000 file system support
10497 13:23:06.553316 <5>[ 0.935136] Key type asymmetric registered
10498 13:23:06.556634 <5>[ 0.939465] Asymmetric key parser 'x509' registered
10499 13:23:06.566626 <6>[ 0.944634] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10500 13:23:06.569928 <6>[ 0.952253] io scheduler mq-deadline registered
10501 13:23:06.573303 <6>[ 0.957016] io scheduler kyber registered
10502 13:23:06.592357 <6>[ 0.974041] EINJ: ACPI disabled.
10503 13:23:06.624538 <4>[ 0.999812] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10504 13:23:06.634434 <4>[ 1.010455] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10505 13:23:06.649400 <6>[ 1.031190] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10506 13:23:06.657477 <6>[ 1.039290] printk: console [ttyS0] disabled
10507 13:23:06.685347 <6>[ 1.063945] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10508 13:23:06.692133 <6>[ 1.073446] printk: console [ttyS0] enabled
10509 13:23:06.695668 <6>[ 1.073446] printk: console [ttyS0] enabled
10510 13:23:06.702124 <6>[ 1.082342] printk: bootconsole [mtk8250] disabled
10511 13:23:06.705588 <6>[ 1.082342] printk: bootconsole [mtk8250] disabled
10512 13:23:06.711976 <6>[ 1.093650] SuperH (H)SCI(F) driver initialized
10513 13:23:06.715253 <6>[ 1.098944] msm_serial: driver initialized
10514 13:23:06.729736 <6>[ 1.107886] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10515 13:23:06.739362 <6>[ 1.116437] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10516 13:23:06.746315 <6>[ 1.124983] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10517 13:23:06.756153 <6>[ 1.133612] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10518 13:23:06.762831 <6>[ 1.142319] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10519 13:23:06.772486 <6>[ 1.151031] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10520 13:23:06.782799 <6>[ 1.159571] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10521 13:23:06.789671 <6>[ 1.168378] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10522 13:23:06.798987 <6>[ 1.176922] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10523 13:23:06.810585 <6>[ 1.192470] loop: module loaded
10524 13:23:06.817395 <6>[ 1.198439] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10525 13:23:06.839540 <4>[ 1.221172] mtk-pmic-keys: Failed to locate of_node [id: -1]
10526 13:23:06.846142 <6>[ 1.228046] megasas: 07.719.03.00-rc1
10527 13:23:06.855893 <6>[ 1.237607] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10528 13:23:06.864448 <6>[ 1.245879] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10529 13:23:06.881028 <6>[ 1.262602] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10530 13:23:06.937832 <6>[ 1.312854] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10531 13:23:07.323696 <6>[ 1.705112] Freeing initrd memory: 20868K
10532 13:23:07.339213 <6>[ 1.720820] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10533 13:23:07.349984 <6>[ 1.731751] tun: Universal TUN/TAP device driver, 1.6
10534 13:23:07.353296 <6>[ 1.737807] thunder_xcv, ver 1.0
10535 13:23:07.356684 <6>[ 1.741314] thunder_bgx, ver 1.0
10536 13:23:07.360122 <6>[ 1.744809] nicpf, ver 1.0
10537 13:23:07.370409 <6>[ 1.748816] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10538 13:23:07.373968 <6>[ 1.756291] hns3: Copyright (c) 2017 Huawei Corporation.
10539 13:23:07.380762 <6>[ 1.761877] hclge is initializing
10540 13:23:07.383987 <6>[ 1.765461] e1000: Intel(R) PRO/1000 Network Driver
10541 13:23:07.390604 <6>[ 1.770590] e1000: Copyright (c) 1999-2006 Intel Corporation.
10542 13:23:07.393712 <6>[ 1.776603] e1000e: Intel(R) PRO/1000 Network Driver
10543 13:23:07.400880 <6>[ 1.781818] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10544 13:23:07.407324 <6>[ 1.788004] igb: Intel(R) Gigabit Ethernet Network Driver
10545 13:23:07.413481 <6>[ 1.793653] igb: Copyright (c) 2007-2014 Intel Corporation.
10546 13:23:07.420274 <6>[ 1.799491] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10547 13:23:07.427537 <6>[ 1.806009] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10548 13:23:07.430481 <6>[ 1.812467] sky2: driver version 1.30
10549 13:23:07.436591 <6>[ 1.817444] VFIO - User Level meta-driver version: 0.3
10550 13:23:07.443675 <6>[ 1.825610] usbcore: registered new interface driver usb-storage
10551 13:23:07.450764 <6>[ 1.832064] usbcore: registered new device driver onboard-usb-hub
10552 13:23:07.459548 <6>[ 1.841129] mt6397-rtc mt6359-rtc: registered as rtc0
10553 13:23:07.469430 <6>[ 1.846601] mt6397-rtc mt6359-rtc: setting system clock to 2023-09-06T13:23:10 UTC (1694006590)
10554 13:23:07.472599 <6>[ 1.856189] i2c_dev: i2c /dev entries driver
10555 13:23:07.489836 <6>[ 1.867945] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10556 13:23:07.510359 <6>[ 1.891926] cpu cpu0: EM: created perf domain
10557 13:23:07.513763 <6>[ 1.896940] cpu cpu4: EM: created perf domain
10558 13:23:07.521216 <6>[ 1.902572] sdhci: Secure Digital Host Controller Interface driver
10559 13:23:07.527247 <6>[ 1.909003] sdhci: Copyright(c) Pierre Ossman
10560 13:23:07.534174 <6>[ 1.913968] Synopsys Designware Multimedia Card Interface Driver
10561 13:23:07.541102 <6>[ 1.920612] sdhci-pltfm: SDHCI platform and OF driver helper
10562 13:23:07.543824 <6>[ 1.920615] mmc0: CQHCI version 5.10
10563 13:23:07.550715 <6>[ 1.930848] ledtrig-cpu: registered to indicate activity on CPUs
10564 13:23:07.557125 <6>[ 1.937922] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10565 13:23:07.563978 <6>[ 1.944975] usbcore: registered new interface driver usbhid
10566 13:23:07.567299 <6>[ 1.950798] usbhid: USB HID core driver
10567 13:23:07.573845 <6>[ 1.955009] spi_master spi0: will run message pump with realtime priority
10568 13:23:07.616770 <6>[ 1.991989] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10569 13:23:07.635746 <6>[ 2.007125] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10570 13:23:07.638950 <6>[ 2.021614] mmc0: Command Queue Engine enabled
10571 13:23:07.645930 <6>[ 2.026390] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10572 13:23:07.652175 <6>[ 2.033110] cros-ec-spi spi0.0: Chrome EC device registered
10573 13:23:07.655805 <6>[ 2.033616] mmcblk0: mmc0:0001 DA4128 116 GiB
10574 13:23:07.670850 <6>[ 2.052358] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10575 13:23:07.678448 <6>[ 2.060018] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10576 13:23:07.688033 <6>[ 2.063565] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10577 13:23:07.691526 <6>[ 2.065905] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10578 13:23:07.698152 <6>[ 2.075783] NET: Registered PF_PACKET protocol family
10579 13:23:07.704881 <6>[ 2.080506] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10580 13:23:07.708282 <6>[ 2.085136] 9pnet: Installing 9P2000 support
10581 13:23:07.715016 <5>[ 2.096147] Key type dns_resolver registered
10582 13:23:07.718510 <6>[ 2.101134] registered taskstats version 1
10583 13:23:07.724764 <5>[ 2.105521] Loading compiled-in X.509 certificates
10584 13:23:07.753953 <4>[ 2.129179] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10585 13:23:07.763932 <4>[ 2.139911] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10586 13:23:07.770976 <3>[ 2.150466] debugfs: File 'uA_load' in directory '/' already present!
10587 13:23:07.777710 <3>[ 2.157233] debugfs: File 'min_uV' in directory '/' already present!
10588 13:23:07.784184 <3>[ 2.163868] debugfs: File 'max_uV' in directory '/' already present!
10589 13:23:07.790454 <3>[ 2.170546] debugfs: File 'constraint_flags' in directory '/' already present!
10590 13:23:07.801855 <3>[ 2.180258] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10591 13:23:07.810737 <6>[ 2.192532] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10592 13:23:07.817869 <6>[ 2.199391] xhci-mtk 11200000.usb: xHCI Host Controller
10593 13:23:07.824300 <6>[ 2.204893] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10594 13:23:07.834646 <6>[ 2.212742] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10595 13:23:07.840968 <6>[ 2.222153] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10596 13:23:07.847752 <6>[ 2.228219] xhci-mtk 11200000.usb: xHCI Host Controller
10597 13:23:07.854381 <6>[ 2.233694] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10598 13:23:07.860825 <6>[ 2.241341] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10599 13:23:07.867588 <6>[ 2.249082] hub 1-0:1.0: USB hub found
10600 13:23:07.871099 <6>[ 2.253101] hub 1-0:1.0: 1 port detected
10601 13:23:07.877397 <6>[ 2.257398] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10602 13:23:07.884432 <6>[ 2.266132] hub 2-0:1.0: USB hub found
10603 13:23:07.888032 <6>[ 2.270147] hub 2-0:1.0: 1 port detected
10604 13:23:07.896569 <6>[ 2.278225] mtk-msdc 11f70000.mmc: Got CD GPIO
10605 13:23:07.906591 <6>[ 2.283992] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10606 13:23:07.913037 <6>[ 2.292028] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10607 13:23:07.923135 <4>[ 2.299932] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10608 13:23:07.929708 <6>[ 2.309461] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10609 13:23:07.939733 <6>[ 2.317541] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10610 13:23:07.946578 <6>[ 2.325623] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10611 13:23:07.956318 <6>[ 2.333549] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10612 13:23:07.962905 <6>[ 2.341427] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10613 13:23:07.972794 <6>[ 2.349249] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10614 13:23:07.982528 <6>[ 2.359872] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10615 13:23:07.988993 <6>[ 2.368228] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10616 13:23:07.998960 <6>[ 2.376593] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10617 13:23:08.005953 <6>[ 2.384932] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10618 13:23:08.015921 <6>[ 2.393283] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10619 13:23:08.022212 <6>[ 2.401622] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10620 13:23:08.032156 <6>[ 2.409970] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10621 13:23:08.038911 <6>[ 2.418309] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10622 13:23:08.048957 <6>[ 2.426660] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10623 13:23:08.055343 <6>[ 2.434999] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10624 13:23:08.065199 <6>[ 2.443346] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10625 13:23:08.071532 <6>[ 2.451685] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10626 13:23:08.081654 <6>[ 2.460022] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10627 13:23:08.088250 <6>[ 2.468361] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10628 13:23:08.098121 <6>[ 2.476698] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10629 13:23:08.104532 <6>[ 2.485519] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10630 13:23:08.111345 <6>[ 2.492708] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10631 13:23:08.117747 <6>[ 2.499488] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10632 13:23:08.124838 <6>[ 2.506262] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10633 13:23:08.134844 <6>[ 2.513204] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10634 13:23:08.141131 <6>[ 2.520044] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10635 13:23:08.151376 <6>[ 2.529176] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10636 13:23:08.161154 <6>[ 2.538296] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10637 13:23:08.170833 <6>[ 2.547589] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10638 13:23:08.181141 <6>[ 2.557082] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10639 13:23:08.187507 <6>[ 2.566553] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10640 13:23:08.197651 <6>[ 2.575677] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10641 13:23:08.207509 <6>[ 2.585145] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10642 13:23:08.217316 <6>[ 2.594266] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10643 13:23:08.227247 <6>[ 2.603561] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10644 13:23:08.236865 <6>[ 2.613721] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10645 13:23:08.246891 <6>[ 2.625305] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10646 13:23:08.276461 <6>[ 2.654903] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10647 13:23:08.304269 <6>[ 2.686016] hub 2-1:1.0: USB hub found
10648 13:23:08.307961 <6>[ 2.690519] hub 2-1:1.0: 3 ports detected
10649 13:23:08.428409 <6>[ 2.806706] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10650 13:23:08.583129 <6>[ 2.964733] hub 1-1:1.0: USB hub found
10651 13:23:08.586335 <6>[ 2.969270] hub 1-1:1.0: 4 ports detected
10652 13:23:08.660720 <6>[ 3.039084] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10653 13:23:08.908285 <6>[ 3.286823] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10654 13:23:09.041120 <6>[ 3.422798] hub 1-1.4:1.0: USB hub found
10655 13:23:09.044483 <6>[ 3.427471] hub 1-1.4:1.0: 2 ports detected
10656 13:23:09.340051 <6>[ 3.718798] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10657 13:23:09.532318 <6>[ 3.910795] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10658 13:23:20.541412 <6>[ 14.927784] ALSA device list:
10659 13:23:20.547757 <6>[ 14.931073] No soundcards found.
10660 13:23:20.555855 <6>[ 14.939014] Freeing unused kernel memory: 8384K
10661 13:23:20.559124 <6>[ 14.944039] Run /init as init process
10662 13:23:20.586830 Starting syslogd: OK
10663 13:23:20.594404 Starting klogd: OK
10664 13:23:20.600656 Running sysctl: OK
10665 13:23:20.607136 Populating /dev using udev: <30>[ 14.992269] udevd[187]: starting version 3.2.9
10666 13:23:20.617116 <27>[ 15.000050] udevd[187]: specified user 'tss' unknown
10667 13:23:20.623216 <27>[ 15.005485] udevd[187]: specified group 'tss' unknown
10668 13:23:20.627072 <30>[ 15.011798] udevd[188]: starting eudev-3.2.9
10669 13:23:20.664509 <27>[ 15.047573] udevd[188]: specified user 'tss' unknown
10670 13:23:20.670974 <27>[ 15.052933] udevd[188]: specified group 'tss' unknown
10671 13:23:20.792163 <6>[ 15.172013] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10672 13:23:20.802225 <6>[ 15.185188] remoteproc remoteproc0: scp is available
10673 13:23:20.808817 <6>[ 15.190759] remoteproc remoteproc0: powering up scp
10674 13:23:20.814898 <6>[ 15.195950] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10675 13:23:20.821953 <6>[ 15.204430] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10676 13:23:20.828266 <6>[ 15.205305] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10677 13:23:20.838108 <6>[ 15.217747] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10678 13:23:20.848069 <6>[ 15.226484] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10679 13:23:20.876198 <4>[ 15.256153] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10680 13:23:20.879636 <6>[ 15.258825] usbcore: registered new interface driver r8152
10681 13:23:20.889280 <4>[ 15.264646] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10682 13:23:20.896252 <3>[ 15.277240] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10683 13:23:20.902430 <6>[ 15.277715] mc: Linux media interface: v0.10
10684 13:23:20.909036 <3>[ 15.285564] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10685 13:23:20.919239 <3>[ 15.285578] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10686 13:23:20.925874 <6>[ 15.302805] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10687 13:23:20.933361 <3>[ 15.306385] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10688 13:23:20.939226 <6>[ 15.316262] videodev: Linux video capture interface: v2.00
10689 13:23:20.949472 <3>[ 15.322342] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10690 13:23:20.955839 <6>[ 15.335418] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10691 13:23:20.962898 <6>[ 15.335450] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10692 13:23:20.969232 <6>[ 15.335457] remoteproc remoteproc0: remote processor scp is now up
10693 13:23:20.979119 <3>[ 15.336103] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10694 13:23:20.986352 <3>[ 15.336110] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10695 13:23:20.992909 <3>[ 15.336118] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10696 13:23:21.003252 <4>[ 15.345208] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10697 13:23:21.006741 <4>[ 15.345208] Fallback method does not support PEC.
10698 13:23:21.016762 <6>[ 15.351592] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10699 13:23:21.026819 <3>[ 15.351766] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10700 13:23:21.033530 <6>[ 15.352061] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10701 13:23:21.043896 <6>[ 15.354771] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10702 13:23:21.050369 <6>[ 15.356541] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10703 13:23:21.053445 <6>[ 15.356547] pci_bus 0000:00: root bus resource [bus 00-ff]
10704 13:23:21.063614 <6>[ 15.356553] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10705 13:23:21.073378 <6>[ 15.356558] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10706 13:23:21.076820 <6>[ 15.356589] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10707 13:23:21.086491 <6>[ 15.356608] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10708 13:23:21.089699 <6>[ 15.356692] pci 0000:00:00.0: supports D1 D2
10709 13:23:21.096272 <6>[ 15.356696] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10710 13:23:21.106765 <6>[ 15.358321] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10711 13:23:21.112934 <3>[ 15.366234] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10712 13:23:21.123050 <3>[ 15.366239] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10713 13:23:21.126106 <6>[ 15.374524] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10714 13:23:21.135977 <3>[ 15.375830] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10715 13:23:21.145903 <4>[ 15.382233] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10716 13:23:21.152472 <4>[ 15.382239] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10717 13:23:21.162648 <3>[ 15.382418] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10718 13:23:21.169065 <6>[ 15.396072] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10719 13:23:21.179220 <6>[ 15.396926] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10720 13:23:21.186250 <3>[ 15.406920] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10721 13:23:21.195800 <3>[ 15.407353] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10722 13:23:21.202295 <6>[ 15.414310] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10723 13:23:21.212735 <3>[ 15.423810] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10724 13:23:21.218909 <6>[ 15.430817] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10725 13:23:21.225835 <3>[ 15.437413] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10726 13:23:21.235556 <3>[ 15.437429] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10727 13:23:21.241769 <3>[ 15.437436] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10728 13:23:21.248684 <6>[ 15.444985] pci 0000:01:00.0: supports D1 D2
10729 13:23:21.251761 <6>[ 15.445254] usbcore: registered new interface driver cdc_ether
10730 13:23:21.261638 <3>[ 15.450357] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10731 13:23:21.268367 <6>[ 15.450585] usbcore: registered new interface driver r8153_ecm
10732 13:23:21.274927 <6>[ 15.460259] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10733 13:23:21.278204 <6>[ 15.460562] Bluetooth: Core ver 2.22
10734 13:23:21.285015 <6>[ 15.460634] NET: Registered PF_BLUETOOTH protocol family
10735 13:23:21.291568 <6>[ 15.460637] Bluetooth: HCI device and connection manager initialized
10736 13:23:21.294772 <6>[ 15.460650] Bluetooth: HCI socket layer initialized
10737 13:23:21.301196 <6>[ 15.460656] Bluetooth: L2CAP socket layer initialized
10738 13:23:21.304508 <6>[ 15.460666] Bluetooth: SCO socket layer initialized
10739 13:23:21.311208 <6>[ 15.479638] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10740 13:23:21.318378 <6>[ 15.486317] r8152 2-1.3:1.0 eth0: v1.12.13
10741 13:23:21.324493 <6>[ 15.495909] usbcore: registered new interface driver btusb
10742 13:23:21.334243 <6>[ 15.495956] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10743 13:23:21.341250 <6>[ 15.496167] usbcore: registered new interface driver uvcvideo
10744 13:23:21.350815 <4>[ 15.496303] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10745 13:23:21.357378 <3>[ 15.496319] Bluetooth: hci0: Failed to load firmware file (-2)
10746 13:23:21.364225 <3>[ 15.496324] Bluetooth: hci0: Failed to set up firmware (-2)
10747 13:23:21.374006 <4>[ 15.496327] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10748 13:23:21.380482 <6>[ 15.498610] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10749 13:23:21.390579 <6>[ 15.498666] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10750 13:23:21.397179 <6>[ 15.498672] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10751 13:23:21.403836 <6>[ 15.498681] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10752 13:23:21.413564 <6>[ 15.498694] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10753 13:23:21.420636 <6>[ 15.498707] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10754 13:23:21.426755 <6>[ 15.498720] pci 0000:00:00.0: PCI bridge to [bus 01]
10755 13:23:21.433962 <6>[ 15.498726] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10756 13:23:21.440206 <6>[ 15.498981] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10757 13:23:21.446912 <6>[ 15.500030] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10758 13:23:21.453390 <6>[ 15.500257] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10759 13:23:21.460123 <6>[ 15.511129] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10760 13:23:21.469873 <6>[ 15.848845] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10761 13:23:21.476295 <5>[ 15.848926] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10762 13:23:21.486374 <6>[ 15.859575] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10763 13:23:21.514119 <5>[ 15.893589] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10764 13:23:21.520030 <4>[ 15.900464] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10765 13:23:21.527091 <6>[ 15.909335] cfg80211: failed to load regulatory.db
10766 13:23:21.577959 <6>[ 15.957905] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10767 13:23:21.584333 <6>[ 15.965424] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10768 13:23:21.608480 <6>[ 15.992145] mt7921e 0000:01:00.0: ASIC revision: 79610010
10769 13:23:21.714179 <4>[ 16.090991] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10770 13:23:21.736902 done
10771 13:23:21.745497 Saving random seed: OK
10772 13:23:21.759146 Starting network: OK
10773 13:23:21.793364 Starting dropbear sshd: <6>[ 16.176891] NET: Registered PF_INET6 protocol family
10774 13:23:21.800367 <6>[ 16.183498] Segment Routing with IPv6
10775 13:23:21.803423 <6>[ 16.187449] In-situ OAM (IOAM) with IPv6
10776 13:23:21.806759 OK
10777 13:23:21.817607 /bin/sh: can't access tty; job control turned off
10778 13:23:21.817915 Matched prompt #10: / #
10780 13:23:21.818144 Setting prompt string to ['/ #']
10781 13:23:21.818257 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10783 13:23:21.818486 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10784 13:23:21.818615 start: 2.2.6 expect-shell-connection (timeout 00:03:25) [common]
10785 13:23:21.818723 Setting prompt string to ['/ #']
10786 13:23:21.818799 Forcing a shell prompt, looking for ['/ #']
10788 13:23:21.869069 / #
10789 13:23:21.869209 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10790 13:23:21.869340 Waiting using forced prompt support (timeout 00:02:30)
10791 13:23:21.869493 <4>[ 16.211369] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10792 13:23:21.874732
10793 13:23:21.875014 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10794 13:23:21.875118 start: 2.2.7 export-device-env (timeout 00:03:25) [common]
10795 13:23:21.875231 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10796 13:23:21.875363 end: 2.2 depthcharge-retry (duration 00:01:35) [common]
10797 13:23:21.875508 end: 2 depthcharge-action (duration 00:01:35) [common]
10798 13:23:21.875613 start: 3 lava-test-retry (timeout 00:01:00) [common]
10799 13:23:21.875715 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10800 13:23:21.875802 Using namespace: common
10802 13:23:21.976229 / # #
10803 13:23:21.976411 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10804 13:23:21.976557 #<4>[ 16.331255] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10805 13:23:21.981489
10806 13:23:21.981761 Using /lava-11445610
10808 13:23:22.082138 / # export SHELL=/bin/sh
10809 13:23:22.082368 export SHELL=/bin/sh<4>[ 16.451374] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10810 13:23:22.087532
10812 13:23:22.188085 / # . /lava-11445610/environment
10813 13:23:22.231570 . /lava-11445610/environment<4>[ 16.571349] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10814 13:23:22.231712
10816 13:23:22.332233 / # /lava-11445610/bin/lava-test-runner /lava-11445610/0
10817 13:23:22.332399 Test shell timeout: 10s (minimum of the action and connection timeout)
10818 13:23:22.332813 /lava-11445610/bin/lava-test-runner /lava-11445610/0<4>[ 16.691525] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10819 13:23:22.337429
10820 13:23:22.379524 + export 'TESTRUN_ID=0_dmesg'
10821 13:23:22.379651 + cd /lava-114456<8>[ 16.747418] <LAVA_SIGNAL_STARTRUN 0_dmesg 11445610_1.5.2.3.1>
10822 13:23:22.379721 10/0/tests/0_dmesg
10823 13:23:22.379785 + cat uuid
10824 13:23:22.379844 + UUID=11445610_1.5.2.3.1
10825 13:23:22.379902 + set +x
10826 13:23:22.379959 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10827 13:23:22.380196 Received signal: <STARTRUN> 0_dmesg 11445610_1.5.2.3.1
10828 13:23:22.380267 Starting test lava.0_dmesg (11445610_1.5.2.3.1)
10829 13:23:22.380391 Skipping test definition patterns.
10830 13:23:22.387974 <8>[ 16.766556] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10831 13:23:22.388229 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10833 13:23:22.404407 <8>[ 16.784606] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10834 13:23:22.404675 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10836 13:23:22.428528 <8>[ 16.808885] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10837 13:23:22.428799 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10839 13:23:22.441694 <4>[ 16.812428] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10840 13:23:22.441784 + set +x
10841 13:23:22.448543 <8>[ 16.829149] <LAVA_SIGNAL_ENDRUN 0_dmesg 11445610_1.5.2.3.1>
10842 13:23:22.448799 Received signal: <ENDRUN> 0_dmesg 11445610_1.5.2.3.1
10843 13:23:22.448885 Ending use of test pattern.
10844 13:23:22.448949 Ending test lava.0_dmesg (11445610_1.5.2.3.1), duration 0.07
10846 13:23:22.451644 <LAVA_TEST_RUNNER EXIT>
10847 13:23:22.451897 ok: lava_test_shell seems to have completed
10848 13:23:22.452004 alert: pass
crit: pass
emerg: pass
10849 13:23:22.452092 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10850 13:23:22.452175 end: 3 lava-test-retry (duration 00:00:01) [common]
10851 13:23:22.452257 start: 4 lava-test-retry (timeout 00:01:00) [common]
10852 13:23:22.452339 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10853 13:23:22.452404 Using namespace: common
10855 13:23:22.552725 / # #
10856 13:23:22.552894 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10857 13:23:22.553031 Using /lava-11445610
10859 13:23:22.653389 export SHELL=/bin/sh
10860 13:23:22.653625 #<4>[ 16.938479] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10861 13:23:22.653736
10863 13:23:22.754268 / # export SHELL=/bin/sh. /lava-11445610/environment
10864 13:23:22.754499
10865 13:23:22.754607 / # <4>[ 17.059854] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10867 13:23:22.855120 . /lava-11445610/environment/lava-11445610/bin/lava-test-runner /lava-11445610/1
10868 13:23:22.855285 Test shell timeout: 10s (minimum of the action and connection timeout)
10869 13:23:22.855463
10870 13:23:22.855535 / # <4>[ 17.183110] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10871 13:23:22.860769 /lava-11445610/bin/lava-test-runner /lava-11445610/1
10872 13:23:22.903505 + export 'TESTRUN_ID=1_bootrr'
10873 13:23:22.903626 <8>[ 17.268511] <LAVA_SIGNAL_STARTRUN 1_bootrr 11445610_1.5.2.3.5>
10874 13:23:22.903695 + cd /lava-11445610/1/tests/1_bootrr
10875 13:23:22.903758 + cat uuid
10876 13:23:22.903818 + UUID=11445610_1.5.2.3.5
10877 13:23:22.903877 + set +x
10878 13:23:22.903937 + export 'PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-11445610/1/../bin:/sbin:/usr/sbin:/bin:/usr/bin'
10879 13:23:22.904175 Received signal: <STARTRUN> 1_bootrr 11445610_1.5.2.3.5
10880 13:23:22.904241 Starting test lava.1_bootrr (11445610_1.5.2.3.5)
10881 13:23:22.904320 Skipping test definition patterns.
10882 13:23:22.912240 + cd /opt/bootr<8>[ 17.291615] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10883 13:23:22.912325 r/libexec/bootrr
10884 13:23:22.912560 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10886 13:23:22.915655 + sh helpers/bootrr-auto
10887 13:23:22.919178 /lava-11445610/1/../bin/lava-test-case
10888 13:23:22.926092 /lava-11445610/1/../bin/lava-test-case
10889 13:23:22.933069 <8>[ 17.314867] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10890 13:23:22.933324 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10892 13:23:22.939639 <3>[ 17.315509] mt7921e 0000:01:00.0: hardware init failed
10893 13:23:22.942726 /usr/bin/tpm2_getcap
10894 13:23:22.974461 /lava-11445610/1/../bin/lava-test-case
10895 13:23:22.980931 <8>[ 17.361692] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
10896 13:23:22.981191 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10898 13:23:23.006348 /lava-11445610/1/../bin/lava-tes<8>[ 17.385899] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10899 13:23:23.006440 t-case
10900 13:23:23.006678 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10902 13:23:23.015915 /lava-11445610/1/../bin/lava-test-case
10903 13:23:23.022732 <8>[ 17.402481] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10904 13:23:23.022987 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10906 13:23:23.032878 /lava-11445610/1/../bin/lava-test-case
10907 13:23:23.039228 <8>[ 17.420069] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10908 13:23:23.039509 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10910 13:23:23.049746 /lava-11445610/1/../bin/lava-test-case
10911 13:23:23.060126 <8>[ 17.440235] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10912 13:23:23.060383 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10914 13:23:23.071304 /lava-11445610/1/../bin/lava-test-case
10915 13:23:23.077823 <8>[ 17.459136] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10916 13:23:23.078111 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10918 13:23:23.087766 /lava-11445610/1/../bin/lava-test-case
10919 13:23:23.094536 <8>[ 17.474605] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10920 13:23:23.094791 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10922 13:23:23.104798 /lava-11445610/1/../bin/lava-test-case
10923 13:23:23.111679 <8>[ 17.493229] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10924 13:23:23.111986 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10926 13:23:23.121508 /lava-11445610/1/../bin/lava-test-case
10927 13:23:23.128085 <8>[ 17.508117] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10928 13:23:23.128342 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10930 13:23:23.139028 /lava-11445610/1/../bin/lava-test-case
10931 13:23:23.146070 <8>[ 17.525996] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10932 13:23:23.146335 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10934 13:23:23.156959 /lava-11445610/1/../bin/lava-test-case
10935 13:23:23.167046 <8>[ 17.545698] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10936 13:23:23.167306 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10938 13:23:23.177516 /lava-11445610/1/../bin/lava-test-case
10939 13:23:23.183717 <8>[ 17.565013] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10940 13:23:23.183976 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10942 13:23:23.196755 /lava-11445610/1/../bin/lava-test-case
10943 13:23:23.202974 <8>[ 17.583342] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10944 13:23:23.203234 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10946 13:23:23.218770 /lava-11445610/1/../bin/lava-tes<8>[ 17.598408] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
10947 13:23:23.218857 t-case
10948 13:23:23.219116 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10950 13:23:23.240218 /lava-11445610/1/../bin/lava-tes<8>[ 17.620064] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
10951 13:23:23.240327 t-case
10952 13:23:23.240588 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10954 13:23:23.251173 /lava-11445610/1/../bin/lava-test-case
10955 13:23:23.260981 <8>[ 17.639742] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
10956 13:23:23.261241 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10958 13:23:23.269594 /lava-11445610/1/../bin/lava-test-case
10959 13:23:23.279719 <8>[ 17.660143] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
10960 13:23:23.279977 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10962 13:23:23.289256 /lava-11445610/1/../bin/lava-test-case
10963 13:23:23.295808 <8>[ 17.675582] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
10964 13:23:23.296066 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10966 13:23:23.306165 /lava-11445610/1/../bin/lava-test-case
10967 13:23:23.312357 <8>[ 17.694731] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
10968 13:23:23.312615 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10970 13:23:23.324116 /lava-11445610/1/../bin/lava-test-case
10971 13:23:23.330096 <8>[ 17.710270] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
10972 13:23:23.330354 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10974 13:23:23.341277 /lava-11445610/1/../bin/lava-test-case
10975 13:23:23.347561 <8>[ 17.728879] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
10976 13:23:23.347822 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10978 13:23:23.356756 /lava-11445610/1/../bin/lava-test-case
10979 13:23:23.363698 <8>[ 17.743549] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
10980 13:23:23.363956 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10982 13:23:23.374773 /lava-11445610/1/../bin/lava-test-case
10983 13:23:23.381539 <8>[ 17.761394] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
10984 13:23:23.381797 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
10986 13:23:23.393229 /lava-11445610/1/../bin/lava-test-case
10987 13:23:23.400047 <8>[ 17.781167] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
10988 13:23:23.400322 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
10990 13:23:23.408809 /lava-11445610/1/../bin/lava-test-case
10991 13:23:23.415610 <8>[ 17.795883] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
10992 13:23:23.415901 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
10994 13:23:23.427542 /lava-11445610/1/../bin/lava-test-case
10995 13:23:23.434069 <8>[ 17.814437] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
10996 13:23:23.434329 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
10998 13:23:23.442471 /lava-11445610/1/../bin/lava-test-case
10999 13:23:23.449408 <8>[ 17.829290] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11000 13:23:23.449664 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11002 13:23:23.459631 /lava-11445610/1/../bin/lava-test-case
11003 13:23:23.465772 <8>[ 17.846309] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11004 13:23:23.466029 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11006 13:23:23.477013 /lava-11445610/1/../bin/lava-test-case
11007 13:23:23.483879 <8>[ 17.864031] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11008 13:23:23.484158 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11010 13:23:23.493819 /lava-11445610/1/../bin/lava-test-case
11011 13:23:23.500624 <8>[ 17.881580] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11012 13:23:23.500886 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11014 13:23:23.512705 /lava-11445610/1/../bin/lava-test-case
11015 13:23:23.519570 <8>[ 17.899995] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11016 13:23:23.519829 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11018 13:23:23.528905 /lava-11445610/1/../bin/lava-test-case
11019 13:23:23.535632 <8>[ 17.916527] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11020 13:23:23.535890 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11022 13:23:23.547989 /lava-11445610/1/../bin/lava-test-case
11023 13:23:23.554309 <8>[ 17.935007] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11024 13:23:23.554564 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11026 13:23:23.571310 /lava-11445610/1/../bin/lava-tes<8>[ 17.950762] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11027 13:23:23.571421 t-case
11028 13:23:23.571659 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11030 13:23:23.581881 /lava-11445610/1/../bin/lava-test-case
11031 13:23:23.588289 <8>[ 17.968483] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11032 13:23:23.588547 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11034 13:23:23.598787 /lava-11445610/1/../bin/lava-test-case
11035 13:23:23.605140 <8>[ 17.987385] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11036 13:23:23.605403 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11038 13:23:23.615862 /lava-11445610/1/../bin/lava-test-case
11039 13:23:23.622532 <8>[ 18.003510] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11040 13:23:23.622789 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11042 13:23:23.634382 /lava-11445610/1/../bin/lava-test-case
11043 13:23:23.641060 <8>[ 18.021205] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11044 13:23:23.641317 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11046 13:23:23.649495 /lava-11445610/1/../bin/lava-test-case
11047 13:23:23.655991 <8>[ 18.036368] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11048 13:23:23.656246 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11050 13:23:23.667970 /lava-11445610/1/../bin/lava-test-case
11051 13:23:23.674328 <8>[ 18.054801] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11052 13:23:23.674582 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11054 13:23:23.683102 /lava-11445610/1/../bin/lava-test-case
11055 13:23:23.689386 <8>[ 18.069842] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11056 13:23:23.689644 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11058 13:23:23.700913 /lava-11445610/1/../bin/lava-test-case
11059 13:23:23.707224 <8>[ 18.087998] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11060 13:23:23.707506 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11062 13:23:23.716445 /lava-11445610/1/../bin/lava-test-case
11063 13:23:23.722945 <8>[ 18.103206] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11064 13:23:23.723201 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11066 13:23:23.733280 /lava-11445610/1/../bin/lava-test-case
11067 13:23:23.740432 <8>[ 18.122129] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11068 13:23:23.740689 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11070 13:23:23.756439 /lava-11445610/1/../bin/lava-tes<8>[ 18.136185] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11071 13:23:23.756525 t-case
11072 13:23:23.756762 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11074 13:23:23.769419 /lava-11445610/1/../bin/lava-test-case
11075 13:23:23.775899 <8>[ 18.156653] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11076 13:23:23.776160 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11078 13:23:23.790359 /lava-11445610/1/../bin/lava-tes<8>[ 18.170084] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11079 13:23:23.790445 t-case
11080 13:23:23.790682 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11082 13:23:23.805993 /lava-11445610/1/../bin/lava-test-case
11083 13:23:23.812157 <8>[ 18.192750] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11084 13:23:23.812412 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11086 13:23:23.822490 /lava-11445610/1/../bin/lava-test-case
11087 13:23:23.829120 <8>[ 18.209224] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11088 13:23:23.829377 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11090 13:23:23.846620 /lava-11445610/1/../bin/lava-tes<8>[ 18.226416] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11091 13:23:23.846743 t-case
11092 13:23:23.847011 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11094 13:23:23.858085 /lava-11445610/1/../bin/lava-test-case
11095 13:23:23.864117 <8>[ 18.244275] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11096 13:23:23.864375 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11098 13:23:23.872637 /lava-11445610/1/../bin/lava-test-case
11099 13:23:23.878936 <8>[ 18.260368] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11100 13:23:23.879192 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11102 13:23:23.890611 /lava-11445610/1/../bin/lava-test-case
11103 13:23:23.896973 <8>[ 18.277260] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11104 13:23:23.897227 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11106 13:23:23.907895 /lava-11445610/1/../bin/lava-test-case
11107 13:23:23.914449 <8>[ 18.294475] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11108 13:23:23.914707 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11110 13:23:23.925005 /lava-11445610/1/../bin/lava-test-case
11111 13:23:23.931490 <8>[ 18.311245] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11112 13:23:23.931745 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11114 13:23:23.941475 /lava-11445610/1/../bin/lava-test-case
11115 13:23:23.951568 <8>[ 18.331296] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11116 13:23:23.951827 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11118 13:23:23.961058 /lava-11445610/1/../bin/lava-test-case
11119 13:23:23.967712 <8>[ 18.347976] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11120 13:23:23.967973 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11122 13:23:23.983621 /lava-11445610/1/../bin/lava-tes<8>[ 18.362982] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11123 13:23:23.983737 t-case
11124 13:23:23.983976 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11126 13:23:23.992726 /lava-11445610/1/../bin/lava-test-case
11127 13:23:23.999092 <8>[ 18.380220] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11128 13:23:23.999362 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11130 13:23:24.006950 /lava-11445610/1/../bin/lava-test-case
11131 13:23:24.018258 <8>[ 18.398239] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11132 13:23:24.018511 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11134 13:23:24.025277 /lava-11445610/1/../bin/lava-test-case
11135 13:23:24.031850 <8>[ 18.412359] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11136 13:23:24.032104 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11138 13:23:24.045105 /lava-11445610/1/../bin/lava-test-case
11139 13:23:24.051987 <8>[ 18.433409] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11140 13:23:24.052244 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11142 13:23:24.067626 /lava-11445610/1/../bin/lava-tes<8>[ 18.447354] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11143 13:23:24.067711 t-case
11144 13:23:24.067946 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11146 13:23:24.078978 /lava-11445610/1/../bin/lava-test-case
11147 13:23:24.085245 <8>[ 18.465564] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11148 13:23:24.085503 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11150 13:23:24.093577 /lava-11445610/1/../bin/lava-test-case
11151 13:23:24.100140 <8>[ 18.480261] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11152 13:23:24.100395 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11154 13:23:24.113867 /lava-11445610/1/../bin/lava-test-case
11155 13:23:24.120457 <8>[ 18.500693] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11156 13:23:24.120714 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11158 13:23:24.130313 /lava-11445610/1/../bin/lava-test-case
11159 13:23:24.136784 <8>[ 18.517584] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11160 13:23:24.137042 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11162 13:23:24.148183 /lava-11445610/1/../bin/lava-test-case
11163 13:23:24.155282 <8>[ 18.535622] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11164 13:23:24.155596 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11166 13:23:24.165018 /lava-11445610/1/../bin/lava-test-case
11167 13:23:24.171316 <8>[ 18.552305] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11168 13:23:24.171668 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11170 13:23:24.183547 /lava-11445610/1/../bin/lava-test-case
11171 13:23:24.190086 <8>[ 18.570838] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11172 13:23:24.190441 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11174 13:23:24.199966 /lava-11445610/1/../bin/lava-test-case
11175 13:23:24.206487 <8>[ 18.588004] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11176 13:23:24.206757 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11178 13:23:24.217304 /lava-11445610/1/../bin/lava-test-case
11179 13:23:24.223754 <8>[ 18.605268] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11180 13:23:24.224017 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11182 13:23:24.234802 /lava-11445610/1/../bin/lava-test-case
11183 13:23:24.241022 <8>[ 18.622305] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11184 13:23:24.241318 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11186 13:23:24.252025 /lava-11445610/1/../bin/lava-test-case
11187 13:23:24.258999 <8>[ 18.640204] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11188 13:23:24.259254 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11190 13:23:24.270410 /lava-11445610/1/../bin/lava-test-case
11191 13:23:24.276942 <8>[ 18.657000] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11192 13:23:24.277197 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11194 13:23:24.286664 /lava-11445610/1/../bin/lava-test-case
11195 13:23:24.292978 <8>[ 18.673554] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11196 13:23:24.293231 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11198 13:23:24.304008 /lava-11445610/1/../bin/lava-test-case
11199 13:23:24.310735 <8>[ 18.691059] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11200 13:23:24.310995 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11202 13:23:24.320682 /lava-11445610/1/../bin/lava-test-case
11203 13:23:24.327029 <8>[ 18.707469] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11204 13:23:24.327315 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11206 13:23:24.339918 /lava-11445610/1/../bin/lava-test-case
11207 13:23:24.346328 <8>[ 18.726716] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11208 13:23:24.346603 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11210 13:23:24.356133 /lava-11445610/1/../bin/lava-test-case
11211 13:23:24.362496 <8>[ 18.743310] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11212 13:23:24.362748 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11214 13:23:24.378519 /lava-11445610/1/../bin/lava-tes<8>[ 18.758331] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11215 13:23:24.378609 t-case
11216 13:23:24.378846 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11218 13:23:24.389657 /lava-11445610/1/../bin/lava-test-case
11219 13:23:24.396058 <8>[ 18.776792] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11220 13:23:24.396306 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11222 13:23:24.404961 /lava-11445610/1/../bin/lava-test-case
11223 13:23:24.411462 <8>[ 18.792036] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11224 13:23:24.411715 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11226 13:23:24.423001 /lava-11445610/1/../bin/lava-test-case
11227 13:23:24.429280 <8>[ 18.809593] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11228 13:23:24.429556 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11230 13:23:24.438075 /lava-11445610/1/../bin/lava-test-case
11231 13:23:24.444727 <8>[ 18.825212] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11232 13:23:24.445009 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11234 13:23:24.456756 /lava-11445610/1/../bin/lava-test-case
11235 13:23:24.462854 <8>[ 18.844139] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11236 13:23:24.463115 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11238 13:23:24.472077 /lava-11445610/1/../bin/lava-test-case
11239 13:23:24.478473 <8>[ 18.859181] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11240 13:23:24.478729 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11242 13:23:24.492535 /lava-11445610/1/../bin/lava-test-case
11243 13:23:24.499154 <8>[ 18.880410] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11244 13:23:24.499414 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11246 13:23:24.507901 /lava-11445610/1/../bin/lava-test-case
11247 13:23:24.514568 <8>[ 18.895932] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11248 13:23:24.514820 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11250 13:23:24.527208 /lava-11445610/1/../bin/lava-test-case
11251 13:23:24.533846 <8>[ 18.913851] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11252 13:23:24.534135 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11254 13:23:24.549283 /lava-11445610/1/../bin/lava-tes<8>[ 18.928922] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11255 13:23:24.549392 t-case
11256 13:23:24.549663 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11258 13:23:24.559675 /lava-11445610/1/../bin/lava-test-case
11259 13:23:24.565930 <8>[ 18.947670] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11260 13:23:24.566215 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11262 13:23:24.579187 /lava-11445610/1/../bin/lava-test-case
11263 13:23:24.585809 <8>[ 18.966292] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11264 13:23:24.586089 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11266 13:23:24.594307 /lava-11445610/1/../bin/lava-test-case
11267 13:23:24.601429 <8>[ 18.981017] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11268 13:23:24.601715 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11270 13:23:24.621164 /lava-11445610/1/../bin/lava-tes<8>[ 19.000946] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11271 13:23:24.621278 t-case
11272 13:23:24.621550 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11274 13:23:24.635173 /lava-11445610/1/../bin/lava-tes<8>[ 19.015018] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11275 13:23:24.635283 t-case
11276 13:23:24.635557 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11278 13:23:24.646318 /lava-11445610/1/../bin/lava-test-case
11279 13:23:24.652837 <8>[ 19.033466] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11280 13:23:24.653115 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11282 13:23:24.667135 /lava-11445610/1/../bin/lava-tes<8>[ 19.047181] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11283 13:23:24.667280 t-case
11284 13:23:24.667631 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11286 13:23:25.681752 /lava-11445610/1/../bin/lava-test-case
11287 13:23:25.688257 <8>[ 20.069002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11288 13:23:25.688555 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11290 13:23:25.695996 /lava-11445610/1/../bin/lava-test-case
11291 13:23:25.705880 <8>[ 20.085515] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11292 13:23:25.706160 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11294 13:23:26.718371 /lava-11445610/1/../bin/lava-test-case
11295 13:23:26.725172 <8>[ 21.105907] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11296 13:23:26.725484 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11298 13:23:26.733346 /lava-11445610/1/../bin/lava-test-case
11299 13:23:26.743137 <8>[ 21.122847] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11300 13:23:26.743415 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11302 13:23:27.757361 /lava-11445610/1/../bin/lava-test-case
11303 13:23:27.764236 <8>[ 22.144961] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11304 13:23:27.764501 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11306 13:23:27.782199 /lava-11445610/1/../bin/lava-tes<8>[ 22.162073] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11307 13:23:27.782326 t-case
11308 13:23:27.782600 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11310 13:23:28.794021 /lava-11445610/1/../bin/lava-test-case
11311 13:23:28.800799 <8>[ 23.183084] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11312 13:23:28.801092 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11314 13:23:28.817091 /lava-11445610/1/../bin/lava-tes<8>[ 23.197755] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11315 13:23:28.817202 t-case
11316 13:23:28.817471 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11318 13:23:29.830358 /lava-11445610/1/../bin/lava-test-case
11319 13:23:29.840240 <8>[ 24.221140] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11320 13:23:29.840511 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11322 13:23:29.851006 /lava-11445610/1/../bin/lava-test-case
11323 13:23:29.858093 <8>[ 24.238868] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11324 13:23:29.858352 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11326 13:23:30.874093 /lava-11445610/1/../bin/lava-test-case
11327 13:23:30.881302 <8>[ 25.263543] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11328 13:23:30.881574 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11330 13:23:30.891715 /lava-11445610/1/../bin/lava-test-case
11331 13:23:30.898822 <8>[ 25.279775] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11332 13:23:30.899076 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11334 13:23:31.911714 /lava-11445610/1/../bin/lava-test-case
11335 13:23:31.918440 <8>[ 26.299846] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11336 13:23:31.918747 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11338 13:23:31.929385 /lava-11445610/1/../bin/lava-test-case
11339 13:23:31.935533 <8>[ 26.317168] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11340 13:23:31.935796 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11342 13:23:31.944553 /lava-11445610/1/../bin/lava-test-case
11343 13:23:31.951339 <8>[ 26.332377] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11344 13:23:31.951641 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11346 13:23:32.965592 /lava-11445610/1/../bin/lava-test-case
11347 13:23:32.972527 <8>[ 27.354211] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11348 13:23:32.972850 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11350 13:23:32.981607 /lava-11445610/1/../bin/lava-test-case
11351 13:23:32.988168 <8>[ 27.370432] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11352 13:23:32.988522 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11354 13:23:33.001427 /lava-11445610/1/../bin/lava-test-case
11355 13:23:33.007685 <8>[ 27.388913] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11356 13:23:33.008000 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11358 13:23:33.023184 /lava-11445610/1/../bin/lava-tes<8>[ 27.403710] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11359 13:23:33.023342 t-case
11360 13:23:33.023608 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11362 13:23:33.034754 /lava-11445610/1/../bin/lava-test-case
11363 13:23:33.041562 <8>[ 27.423630] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11364 13:23:33.041864 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11366 13:23:33.052403 /lava-11445610/1/../bin/lava-test-case
11367 13:23:33.058870 <8>[ 27.440580] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11368 13:23:33.059153 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11370 13:23:33.070916 /lava-11445610/1/../bin/lava-test-case
11371 13:23:33.077280 <8>[ 27.458913] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11372 13:23:33.077582 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11374 13:23:33.092845 /lava-11445610/1/../bin/lava-tes<8>[ 27.473724] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11375 13:23:33.092965 t-case
11376 13:23:33.093234 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11378 13:23:33.105225 /lava-11445610/1/../bin/lava-test-case
11379 13:23:33.111736 <8>[ 27.493106] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11380 13:23:33.112004 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11382 13:23:33.129400 /lava-11445610/1/../bin/lava-tes<8>[ 27.510289] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11383 13:23:33.129489 t-case
11384 13:23:33.129725 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11386 13:23:33.140173 /lava-11445610/1/../bin/lava-test-case
11387 13:23:33.146904 <8>[ 27.528158] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11388 13:23:33.147157 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11390 13:23:33.157771 /lava-11445610/1/../bin/lava-test-case
11391 13:23:33.164886 <8>[ 27.545538] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11392 13:23:33.165178 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11394 13:23:33.173023 /lava-11445610/1/../bin/lava-test-case
11395 13:23:33.183479 <8>[ 27.562920] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11396 13:23:33.183768 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11398 13:23:33.193705 /lava-11445610/1/../bin/lava-test-case
11399 13:23:33.200474 <8>[ 27.581477] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11400 13:23:33.200729 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11402 13:23:33.209280 /lava-11445610/1/../bin/lava-test-case
11403 13:23:33.216091 <8>[ 27.597405] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11404 13:23:33.216346 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11406 13:23:33.230256 /lava-11445610/1/../bin/lava-test-case
11407 13:23:33.236756 <8>[ 27.619480] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11408 13:23:33.237012 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11410 13:23:33.253059 /lava-11445610/1/../bin/lava-tes<8>[ 27.633862] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11411 13:23:33.253173 t-case
11412 13:23:33.253445 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11414 13:23:33.266934 /lava-11445610/1/../bin/lava-test-case
11415 13:23:33.273325 <8>[ 27.656372] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11416 13:23:33.273606 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11418 13:23:33.283820 /lava-11445610/1/../bin/lava-test-case
11419 13:23:33.290515 <8>[ 27.671102] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11420 13:23:33.290773 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11422 13:23:33.303912 /lava-11445610/1/../bin/lava-test-case
11423 13:23:33.310971 <8>[ 27.692683] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11424 13:23:33.311258 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11426 13:23:33.318983 /lava-11445610/1/../bin/lava-test-case
11427 13:23:33.325426 <8>[ 27.707819] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11428 13:23:33.325684 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11430 13:23:34.342153 /lava-11445610/1/../bin/lava-test-case
11431 13:23:34.348641 <8>[ 28.730257] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11432 13:23:34.348992 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11434 13:23:35.361962 /lava-11445610/1/../bin/lava-test-case
11435 13:23:35.368708 <8>[ 29.751713] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11436 13:23:35.369002 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11438 13:23:35.379651 /lava-11445610/1/../bin/lava-test-case
11439 13:23:35.386048 <8>[ 29.767645] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11440 13:23:35.386349 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11442 13:23:35.396619 /lava-11445610/1/../bin/lava-test-case
11443 13:23:35.402920 <8>[ 29.786887] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11444 13:23:35.403212 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11446 13:23:35.420814 /lava-11445610/1/../bin/lava-tes<8>[ 29.801672] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11447 13:23:35.420927 t-case
11448 13:23:35.421167 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11450 13:23:35.430559 /lava-11445610/1/../bin/lava-test-case
11451 13:23:35.436876 <8>[ 29.819652] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11452 13:23:35.437135 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11454 13:23:35.453906 /lava-11445610/1/../bin/lava-tes<8>[ 29.834785] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11455 13:23:35.454028 t-case
11456 13:23:35.454298 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11458 13:23:35.464720 /lava-11445610/1/../bin/lava-test-case
11459 13:23:35.471353 <8>[ 29.852613] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11460 13:23:35.471760 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11462 13:23:35.480679 /lava-11445610/1/../bin/lava-test-case
11463 13:23:35.487341 <8>[ 29.869021] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11464 13:23:35.487721 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11466 13:23:35.497821 /lava-11445610/1/../bin/lava-test-case
11467 13:23:35.504280 <8>[ 29.887071] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11468 13:23:35.504578 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11470 13:23:35.514805 /lava-11445610/1/../bin/lava-test-case
11471 13:23:35.521209 <8>[ 29.903381] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11472 13:23:35.521506 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11474 13:23:35.531785 /lava-11445610/1/../bin/lava-test-case
11475 13:23:35.538454 <8>[ 29.921006] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11476 13:23:35.538749 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11478 13:23:35.554406 /lava-11445610/1/../bin/lava-tes<8>[ 29.935581] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11479 13:23:35.554526 t-case
11480 13:23:35.554803 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11482 13:23:35.565622 /lava-11445610/1/../bin/lava-test-case
11483 13:23:35.572465 <8>[ 29.955083] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11484 13:23:35.572747 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11486 13:23:35.582371 /lava-11445610/1/../bin/lava-test-case
11487 13:23:35.589105 <8>[ 29.970734] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11488 13:23:35.589389 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11490 13:23:35.603831 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11492 13:23:35.606731 /lava-11445610/1/../bin/lava-tes<8>[ 29.987939] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11493 13:23:35.606844 t-case
11494 13:23:35.616606 /lava-11445610/1/../bin/lava-test-case
11495 13:23:35.623396 <8>[ 30.006639] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11496 13:23:35.623668 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11498 13:23:35.635051 /lava-11445610/1/../bin/lava-test-case
11499 13:23:35.641177 <8>[ 30.025416] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11500 13:23:35.641454 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11502 13:23:35.653263 /lava-11445610/1/../bin/lava-test-case
11503 13:23:35.659379 <8>[ 30.041008] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11504 13:23:35.659686 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11506 13:23:35.669685 /lava-11445610/1/../bin/lava-test-case
11507 13:23:35.679754 <8>[ 30.061261] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11508 13:23:35.680016 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11510 13:23:35.687239 /lava-11445610/1/../bin/lava-test-case
11511 13:23:35.694094 <8>[ 30.076082] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11512 13:23:35.694373 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11514 13:23:35.706004 /lava-11445610/1/../bin/lava-test-case
11515 13:23:35.712969 <8>[ 30.094530] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11516 13:23:35.713250 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11518 13:23:36.722934 /lava-11445610/1/../bin/lava-test-case
11519 13:23:36.729696 <8>[ 31.111442] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11520 13:23:36.730000 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11522 13:23:37.742841 /lava-11445610/1/../bin/lava-test-case
11523 13:23:37.749692 <8>[ 32.132125] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11524 13:23:37.749954 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11525 13:23:37.750043 Bad test result: blocked
11526 13:23:37.758923 /lava-11445610/1/../bin/lava-test-case
11527 13:23:37.765472 <8>[ 32.148549] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11528 13:23:37.765729 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11530 13:23:38.780578 /lava-11445610/1/../bin/lava-test-case
11531 13:23:38.787124 <8>[ 33.169022] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11532 13:23:38.787428 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11534 13:23:38.795076 /lava-11445610/1/../bin/lava-test-case
11535 13:23:38.801264 <8>[ 33.184092] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11536 13:23:38.801520 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11538 13:23:38.813775 /lava-11445610/1/../bin/lava-test-case
11539 13:23:38.820673 <8>[ 33.202528] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11540 13:23:38.820928 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11542 13:23:38.831178 /lava-11445610/1/../bin/lava-test-case
11543 13:23:38.837460 <8>[ 33.220715] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11544 13:23:38.837716 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11546 13:23:38.846805 /lava-11445610/1/../bin/lava-test-case
11547 13:23:38.853067 <8>[ 33.234999] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11548 13:23:38.853324 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11550 13:23:38.867267 /lava-11445610/1/../bin/lava-test-case
11551 13:23:38.873489 <8>[ 33.255251] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11552 13:23:38.873748 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11554 13:23:38.881583 /lava-11445610/1/../bin/lava-test-case
11555 13:23:38.888179 <8>[ 33.270929] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11556 13:23:38.888440 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11558 13:23:39.902461 /lava-11445610/1/../bin/lava-test-case
11559 13:23:39.908707 <8>[ 34.291012] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11560 13:23:39.908974 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11562 13:23:39.918947 /lava-11445610/1/../bin/lava-test-case
11563 13:23:39.925126 <8>[ 34.309187] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11564 13:23:39.925384 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11566 13:23:40.940246 /lava-11445610/1/../bin/lava-test-case
11567 13:23:40.946538 <8>[ 35.328987] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11568 13:23:40.946844 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11570 13:23:40.954124 /lava-11445610/1/../bin/lava-test-case
11571 13:23:40.961413 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11573 13:23:40.964324 <8>[ 35.345433] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11574 13:23:41.976874 /lava-11445610/1/../bin/lava-test-case
11575 13:23:41.982827 <8>[ 36.365744] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11576 13:23:41.983110 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11578 13:23:41.991034 /lava-11445610/1/../bin/lava-test-case
11579 13:23:42.001222 <8>[ 36.382328] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11580 13:23:42.001486 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11582 13:23:43.014449 /lava-11445610/1/../bin/lava-test-case
11583 13:23:43.021197 <8>[ 37.403914] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11584 13:23:43.021522 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11586 13:23:43.029745 /lava-11445610/1/../bin/lava-test-case
11587 13:23:43.036414 <8>[ 37.419871] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11588 13:23:43.036697 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11590 13:23:43.048589 /lava-11445610/1/../bin/lava-test-case
11591 13:23:43.054663 <8>[ 37.437526] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11592 13:23:43.054939 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11594 13:23:43.064337 /lava-11445610/1/../bin/lava-test-case
11595 13:23:43.070778 <8>[ 37.453379] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11596 13:23:43.071053 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11598 13:23:43.079336 /lava-11445610/1/../bin/lava-test-case
11599 13:23:43.085915 <8>[ 37.468782] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11600 13:23:43.086165 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11602 13:23:43.096313 /lava-11445610/1/../bin/lava-test-case
11603 13:23:43.102610 <8>[ 37.485764] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11604 13:23:43.102866 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11606 13:23:43.120386 /lava-11445610/1/../bin/lava-tes<8>[ 37.502077] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11607 13:23:43.120475 t-case
11608 13:23:43.120712 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11610 13:23:43.130402 /lava-11445610/1/../bin/lava-test-case
11611 13:23:43.136767 <8>[ 37.520390] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11612 13:23:43.137039 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11614 13:23:43.147236 /lava-11445610/1/../bin/lava-test-case
11615 13:23:43.153977 <8>[ 37.536247] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11616 13:23:43.154232 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11618 13:23:43.172080 /lava-11445610/1/../bin/lava-tes<8>[ 37.553938] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11619 13:23:43.172165 t-case
11620 13:23:43.172403 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11622 13:23:43.175097 + set +x
11623 13:23:43.178719 <8>[ 37.564001] <LAVA_SIGNAL_ENDRUN 1_bootrr 11445610_1.5.2.3.5>
11624 13:23:43.178973 Received signal: <ENDRUN> 1_bootrr 11445610_1.5.2.3.5
11625 13:23:43.179051 Ending use of test pattern.
11626 13:23:43.179116 Ending test lava.1_bootrr (11445610_1.5.2.3.5), duration 20.27
11628 13:23:43.182753 <LAVA_TEST_RUNNER EXIT>
11629 13:23:43.183018 ok: lava_test_shell seems to have completed
11630 13:23:43.184026 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: pass
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11631 13:23:43.184169 end: 4.1 lava-test-shell (duration 00:00:21) [common]
11632 13:23:43.184258 end: 4 lava-test-retry (duration 00:00:21) [common]
11633 13:23:43.184349 start: 5 finalize (timeout 00:07:46) [common]
11634 13:23:43.184441 start: 5.1 power-off (timeout 00:00:30) [common]
11635 13:23:43.184600 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11636 13:23:43.262014 >> Command sent successfully.
11637 13:23:43.264400 Returned 0 in 0 seconds
11638 13:23:43.364806 end: 5.1 power-off (duration 00:00:00) [common]
11640 13:23:43.365153 start: 5.2 read-feedback (timeout 00:07:46) [common]
11641 13:23:43.365428 Listened to connection for namespace 'common' for up to 1s
11642 13:23:44.366392 Finalising connection for namespace 'common'
11643 13:23:44.366555 Disconnecting from shell: Finalise
11644 13:23:44.366637 / #
11645 13:23:44.466970 end: 5.2 read-feedback (duration 00:00:01) [common]
11646 13:23:44.467170 end: 5 finalize (duration 00:00:01) [common]
11647 13:23:44.467315 Cleaning after the job
11648 13:23:44.467487 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11445610/tftp-deploy-rfkqokb0/ramdisk
11649 13:23:44.470807 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11445610/tftp-deploy-rfkqokb0/kernel
11650 13:23:44.479281 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11445610/tftp-deploy-rfkqokb0/dtb
11651 13:23:44.479522 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11445610/tftp-deploy-rfkqokb0/modules
11652 13:23:44.486863 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11445610
11653 13:23:44.537795 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11445610
11654 13:23:44.537956 Job finished correctly