Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 39
- Boot result: PASS
- Warnings: 1
- Errors: 1
- Kernel Warnings: 25
1 13:29:54.846500 lava-dispatcher, installed at version: 2023.06
2 13:29:54.846719 start: 0 validate
3 13:29:54.846858 Start time: 2023-09-08 13:29:54.846850+00:00 (UTC)
4 13:29:54.846996 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:29:54.847144 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 13:29:55.115865 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:29:55.116094 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.52-cip5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:29:55.382400 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:29:55.382723 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.52-cip5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:29:55.651657 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:29:55.652147 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 13:29:56.184575 Using caching service: 'http://localhost/cache/?uri=%s'
13 13:29:56.185289 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.52-cip5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 13:29:56.461824 validate duration: 1.62
16 13:29:56.462999 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 13:29:56.463545 start: 1.1 download-retry (timeout 00:10:00) [common]
18 13:29:56.464107 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 13:29:56.464710 Not decompressing ramdisk as can be used compressed.
20 13:29:56.465178 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/initrd.cpio.gz
21 13:29:56.465534 saving as /var/lib/lava/dispatcher/tmp/11471176/tftp-deploy-5nyrh5z2/ramdisk/initrd.cpio.gz
22 13:29:56.465868 total size: 4665412 (4 MB)
23 13:29:56.470744 progress 0 % (0 MB)
24 13:29:56.478429 progress 5 % (0 MB)
25 13:29:56.484964 progress 10 % (0 MB)
26 13:29:56.489770 progress 15 % (0 MB)
27 13:29:56.493444 progress 20 % (0 MB)
28 13:29:56.496485 progress 25 % (1 MB)
29 13:29:56.499214 progress 30 % (1 MB)
30 13:29:56.501652 progress 35 % (1 MB)
31 13:29:56.503897 progress 40 % (1 MB)
32 13:29:56.506278 progress 45 % (2 MB)
33 13:29:56.508305 progress 50 % (2 MB)
34 13:29:56.510306 progress 55 % (2 MB)
35 13:29:56.512103 progress 60 % (2 MB)
36 13:29:56.513827 progress 65 % (2 MB)
37 13:29:56.515519 progress 70 % (3 MB)
38 13:29:56.517071 progress 75 % (3 MB)
39 13:29:56.518615 progress 80 % (3 MB)
40 13:29:56.520376 progress 85 % (3 MB)
41 13:29:56.521758 progress 90 % (4 MB)
42 13:29:56.523133 progress 95 % (4 MB)
43 13:29:56.524543 progress 100 % (4 MB)
44 13:29:56.524716 4 MB downloaded in 0.06 s (75.58 MB/s)
45 13:29:56.524888 end: 1.1.1 http-download (duration 00:00:00) [common]
47 13:29:56.525163 end: 1.1 download-retry (duration 00:00:00) [common]
48 13:29:56.525253 start: 1.2 download-retry (timeout 00:10:00) [common]
49 13:29:56.525339 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 13:29:56.525474 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.52-cip5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 13:29:56.525544 saving as /var/lib/lava/dispatcher/tmp/11471176/tftp-deploy-5nyrh5z2/kernel/Image
52 13:29:56.525604 total size: 49220096 (46 MB)
53 13:29:56.525667 No compression specified
54 13:29:56.526744 progress 0 % (0 MB)
55 13:29:56.539563 progress 5 % (2 MB)
56 13:29:56.552287 progress 10 % (4 MB)
57 13:29:56.565006 progress 15 % (7 MB)
58 13:29:56.578038 progress 20 % (9 MB)
59 13:29:56.590754 progress 25 % (11 MB)
60 13:29:56.603502 progress 30 % (14 MB)
61 13:29:56.616246 progress 35 % (16 MB)
62 13:29:56.628931 progress 40 % (18 MB)
63 13:29:56.641568 progress 45 % (21 MB)
64 13:29:56.654499 progress 50 % (23 MB)
65 13:29:56.667268 progress 55 % (25 MB)
66 13:29:56.680274 progress 60 % (28 MB)
67 13:29:56.693185 progress 65 % (30 MB)
68 13:29:56.705865 progress 70 % (32 MB)
69 13:29:56.718705 progress 75 % (35 MB)
70 13:29:56.731213 progress 80 % (37 MB)
71 13:29:56.743992 progress 85 % (39 MB)
72 13:29:56.756712 progress 90 % (42 MB)
73 13:29:56.769292 progress 95 % (44 MB)
74 13:29:56.782411 progress 100 % (46 MB)
75 13:29:56.782575 46 MB downloaded in 0.26 s (182.67 MB/s)
76 13:29:56.782780 end: 1.2.1 http-download (duration 00:00:00) [common]
78 13:29:56.783158 end: 1.2 download-retry (duration 00:00:00) [common]
79 13:29:56.783279 start: 1.3 download-retry (timeout 00:10:00) [common]
80 13:29:56.783406 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 13:29:56.783588 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.52-cip5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 13:29:56.783691 saving as /var/lib/lava/dispatcher/tmp/11471176/tftp-deploy-5nyrh5z2/dtb/mt8192-asurada-spherion-r0.dtb
83 13:29:56.783785 total size: 47278 (0 MB)
84 13:29:56.783880 No compression specified
85 13:29:56.785315 progress 69 % (0 MB)
86 13:29:56.785595 progress 100 % (0 MB)
87 13:29:56.785753 0 MB downloaded in 0.00 s (22.95 MB/s)
88 13:29:56.785874 end: 1.3.1 http-download (duration 00:00:00) [common]
90 13:29:56.786094 end: 1.3 download-retry (duration 00:00:00) [common]
91 13:29:56.786177 start: 1.4 download-retry (timeout 00:10:00) [common]
92 13:29:56.786265 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 13:29:56.786384 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/full.rootfs.tar.xz
94 13:29:56.786451 saving as /var/lib/lava/dispatcher/tmp/11471176/tftp-deploy-5nyrh5z2/nfsrootfs/full.rootfs.tar
95 13:29:56.786520 total size: 125290964 (119 MB)
96 13:29:56.786611 Using unxz to decompress xz
97 13:29:56.794150 progress 0 % (0 MB)
98 13:29:57.119043 progress 5 % (6 MB)
99 13:29:57.449856 progress 10 % (11 MB)
100 13:29:57.778966 progress 15 % (17 MB)
101 13:29:57.962945 progress 20 % (23 MB)
102 13:29:58.136885 progress 25 % (29 MB)
103 13:29:58.484228 progress 30 % (35 MB)
104 13:29:58.832908 progress 35 % (41 MB)
105 13:29:59.219942 progress 40 % (47 MB)
106 13:29:59.597503 progress 45 % (53 MB)
107 13:29:59.985187 progress 50 % (59 MB)
108 13:30:00.334671 progress 55 % (65 MB)
109 13:30:00.696156 progress 60 % (71 MB)
110 13:30:01.031632 progress 65 % (77 MB)
111 13:30:01.394363 progress 70 % (83 MB)
112 13:30:01.774075 progress 75 % (89 MB)
113 13:30:02.189742 progress 80 % (95 MB)
114 13:30:02.602694 progress 85 % (101 MB)
115 13:30:02.845310 progress 90 % (107 MB)
116 13:30:03.179057 progress 95 % (113 MB)
117 13:30:03.548092 progress 100 % (119 MB)
118 13:30:03.553736 119 MB downloaded in 6.77 s (17.66 MB/s)
119 13:30:03.553986 end: 1.4.1 http-download (duration 00:00:07) [common]
121 13:30:03.554237 end: 1.4 download-retry (duration 00:00:07) [common]
122 13:30:03.554324 start: 1.5 download-retry (timeout 00:09:53) [common]
123 13:30:03.554413 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 13:30:03.554568 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.52-cip5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 13:30:03.554636 saving as /var/lib/lava/dispatcher/tmp/11471176/tftp-deploy-5nyrh5z2/modules/modules.tar
126 13:30:03.554696 total size: 8615576 (8 MB)
127 13:30:03.554768 Using unxz to decompress xz
128 13:30:03.558768 progress 0 % (0 MB)
129 13:30:03.580334 progress 5 % (0 MB)
130 13:30:03.602386 progress 10 % (0 MB)
131 13:30:03.627899 progress 15 % (1 MB)
132 13:30:03.652891 progress 20 % (1 MB)
133 13:30:03.678326 progress 25 % (2 MB)
134 13:30:03.704215 progress 30 % (2 MB)
135 13:30:03.730665 progress 35 % (2 MB)
136 13:30:03.755196 progress 40 % (3 MB)
137 13:30:03.779286 progress 45 % (3 MB)
138 13:30:03.805305 progress 50 % (4 MB)
139 13:30:03.830052 progress 55 % (4 MB)
140 13:30:03.854436 progress 60 % (4 MB)
141 13:30:03.876927 progress 65 % (5 MB)
142 13:30:03.904309 progress 70 % (5 MB)
143 13:30:03.928066 progress 75 % (6 MB)
144 13:30:03.953909 progress 80 % (6 MB)
145 13:30:03.983766 progress 85 % (7 MB)
146 13:30:04.010012 progress 90 % (7 MB)
147 13:30:04.033963 progress 95 % (7 MB)
148 13:30:04.056779 progress 100 % (8 MB)
149 13:30:04.063029 8 MB downloaded in 0.51 s (16.16 MB/s)
150 13:30:04.063279 end: 1.5.1 http-download (duration 00:00:01) [common]
152 13:30:04.063548 end: 1.5 download-retry (duration 00:00:01) [common]
153 13:30:04.063639 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 13:30:04.063735 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 13:30:06.161130 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/11471176/extract-nfsrootfs-tmw6wty7
156 13:30:06.161336 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 13:30:06.161436 start: 1.6.2 lava-overlay (timeout 00:09:50) [common]
158 13:30:06.161607 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11471176/lava-overlay-q8hie60t
159 13:30:06.161744 makedir: /var/lib/lava/dispatcher/tmp/11471176/lava-overlay-q8hie60t/lava-11471176/bin
160 13:30:06.161847 makedir: /var/lib/lava/dispatcher/tmp/11471176/lava-overlay-q8hie60t/lava-11471176/tests
161 13:30:06.161947 makedir: /var/lib/lava/dispatcher/tmp/11471176/lava-overlay-q8hie60t/lava-11471176/results
162 13:30:06.162049 Creating /var/lib/lava/dispatcher/tmp/11471176/lava-overlay-q8hie60t/lava-11471176/bin/lava-add-keys
163 13:30:06.162191 Creating /var/lib/lava/dispatcher/tmp/11471176/lava-overlay-q8hie60t/lava-11471176/bin/lava-add-sources
164 13:30:06.162322 Creating /var/lib/lava/dispatcher/tmp/11471176/lava-overlay-q8hie60t/lava-11471176/bin/lava-background-process-start
165 13:30:06.162449 Creating /var/lib/lava/dispatcher/tmp/11471176/lava-overlay-q8hie60t/lava-11471176/bin/lava-background-process-stop
166 13:30:06.162581 Creating /var/lib/lava/dispatcher/tmp/11471176/lava-overlay-q8hie60t/lava-11471176/bin/lava-common-functions
167 13:30:06.162711 Creating /var/lib/lava/dispatcher/tmp/11471176/lava-overlay-q8hie60t/lava-11471176/bin/lava-echo-ipv4
168 13:30:06.162836 Creating /var/lib/lava/dispatcher/tmp/11471176/lava-overlay-q8hie60t/lava-11471176/bin/lava-install-packages
169 13:30:06.162971 Creating /var/lib/lava/dispatcher/tmp/11471176/lava-overlay-q8hie60t/lava-11471176/bin/lava-installed-packages
170 13:30:06.163129 Creating /var/lib/lava/dispatcher/tmp/11471176/lava-overlay-q8hie60t/lava-11471176/bin/lava-os-build
171 13:30:06.163287 Creating /var/lib/lava/dispatcher/tmp/11471176/lava-overlay-q8hie60t/lava-11471176/bin/lava-probe-channel
172 13:30:06.163414 Creating /var/lib/lava/dispatcher/tmp/11471176/lava-overlay-q8hie60t/lava-11471176/bin/lava-probe-ip
173 13:30:06.163537 Creating /var/lib/lava/dispatcher/tmp/11471176/lava-overlay-q8hie60t/lava-11471176/bin/lava-target-ip
174 13:30:06.163665 Creating /var/lib/lava/dispatcher/tmp/11471176/lava-overlay-q8hie60t/lava-11471176/bin/lava-target-mac
175 13:30:06.163815 Creating /var/lib/lava/dispatcher/tmp/11471176/lava-overlay-q8hie60t/lava-11471176/bin/lava-target-storage
176 13:30:06.164018 Creating /var/lib/lava/dispatcher/tmp/11471176/lava-overlay-q8hie60t/lava-11471176/bin/lava-test-case
177 13:30:06.164145 Creating /var/lib/lava/dispatcher/tmp/11471176/lava-overlay-q8hie60t/lava-11471176/bin/lava-test-event
178 13:30:06.164269 Creating /var/lib/lava/dispatcher/tmp/11471176/lava-overlay-q8hie60t/lava-11471176/bin/lava-test-feedback
179 13:30:06.164392 Creating /var/lib/lava/dispatcher/tmp/11471176/lava-overlay-q8hie60t/lava-11471176/bin/lava-test-raise
180 13:30:06.164514 Creating /var/lib/lava/dispatcher/tmp/11471176/lava-overlay-q8hie60t/lava-11471176/bin/lava-test-reference
181 13:30:06.164647 Creating /var/lib/lava/dispatcher/tmp/11471176/lava-overlay-q8hie60t/lava-11471176/bin/lava-test-runner
182 13:30:06.164780 Creating /var/lib/lava/dispatcher/tmp/11471176/lava-overlay-q8hie60t/lava-11471176/bin/lava-test-set
183 13:30:06.164904 Creating /var/lib/lava/dispatcher/tmp/11471176/lava-overlay-q8hie60t/lava-11471176/bin/lava-test-shell
184 13:30:06.165031 Updating /var/lib/lava/dispatcher/tmp/11471176/lava-overlay-q8hie60t/lava-11471176/bin/lava-install-packages (oe)
185 13:30:06.165181 Updating /var/lib/lava/dispatcher/tmp/11471176/lava-overlay-q8hie60t/lava-11471176/bin/lava-installed-packages (oe)
186 13:30:06.165326 Creating /var/lib/lava/dispatcher/tmp/11471176/lava-overlay-q8hie60t/lava-11471176/environment
187 13:30:06.165455 LAVA metadata
188 13:30:06.165529 - LAVA_JOB_ID=11471176
189 13:30:06.165592 - LAVA_DISPATCHER_IP=192.168.201.1
190 13:30:06.165691 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:50) [common]
191 13:30:06.165756 skipped lava-vland-overlay
192 13:30:06.165829 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 13:30:06.165905 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:50) [common]
194 13:30:06.165964 skipped lava-multinode-overlay
195 13:30:06.166035 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 13:30:06.166110 start: 1.6.2.3 test-definition (timeout 00:09:50) [common]
197 13:30:06.166181 Loading test definitions
198 13:30:06.166266 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:50) [common]
199 13:30:06.166338 Using /lava-11471176 at stage 0
200 13:30:06.166645 uuid=11471176_1.6.2.3.1 testdef=None
201 13:30:06.166732 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 13:30:06.166815 start: 1.6.2.3.2 test-overlay (timeout 00:09:50) [common]
203 13:30:06.167318 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 13:30:06.167534 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:50) [common]
206 13:30:06.168199 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 13:30:06.168424 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:50) [common]
209 13:30:06.169048 runner path: /var/lib/lava/dispatcher/tmp/11471176/lava-overlay-q8hie60t/lava-11471176/0/tests/0_dmesg test_uuid 11471176_1.6.2.3.1
210 13:30:06.169201 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 13:30:06.169423 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:50) [common]
213 13:30:06.169494 Using /lava-11471176 at stage 1
214 13:30:06.169797 uuid=11471176_1.6.2.3.5 testdef=None
215 13:30:06.169883 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 13:30:06.169965 start: 1.6.2.3.6 test-overlay (timeout 00:09:50) [common]
217 13:30:06.170421 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 13:30:06.170630 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:50) [common]
220 13:30:06.171257 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 13:30:06.171479 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:50) [common]
223 13:30:06.172215 runner path: /var/lib/lava/dispatcher/tmp/11471176/lava-overlay-q8hie60t/lava-11471176/1/tests/1_bootrr test_uuid 11471176_1.6.2.3.5
224 13:30:06.172362 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 13:30:06.172562 Creating lava-test-runner.conf files
227 13:30:06.172623 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11471176/lava-overlay-q8hie60t/lava-11471176/0 for stage 0
228 13:30:06.172710 - 0_dmesg
229 13:30:06.172787 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11471176/lava-overlay-q8hie60t/lava-11471176/1 for stage 1
230 13:30:06.172875 - 1_bootrr
231 13:30:06.172966 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 13:30:06.173049 start: 1.6.2.4 compress-overlay (timeout 00:09:50) [common]
233 13:30:06.180342 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 13:30:06.180443 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:50) [common]
235 13:30:06.180527 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 13:30:06.180609 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 13:30:06.180692 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:50) [common]
238 13:30:06.300686 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 13:30:06.301078 start: 1.6.4 extract-modules (timeout 00:09:50) [common]
240 13:30:06.301202 extracting modules file /var/lib/lava/dispatcher/tmp/11471176/tftp-deploy-5nyrh5z2/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11471176/extract-nfsrootfs-tmw6wty7
241 13:30:06.523694 extracting modules file /var/lib/lava/dispatcher/tmp/11471176/tftp-deploy-5nyrh5z2/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11471176/extract-overlay-ramdisk-j00jjnp3/ramdisk
242 13:30:06.747870 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 13:30:06.748085 start: 1.6.5 apply-overlay-tftp (timeout 00:09:50) [common]
244 13:30:06.748183 [common] Applying overlay to NFS
245 13:30:06.748257 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11471176/compress-overlay-sxqh95ss/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11471176/extract-nfsrootfs-tmw6wty7
246 13:30:06.756217 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 13:30:06.756326 start: 1.6.6 configure-preseed-file (timeout 00:09:50) [common]
248 13:30:06.756417 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 13:30:06.756500 start: 1.6.7 compress-ramdisk (timeout 00:09:50) [common]
250 13:30:06.756573 Building ramdisk /var/lib/lava/dispatcher/tmp/11471176/extract-overlay-ramdisk-j00jjnp3/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11471176/extract-overlay-ramdisk-j00jjnp3/ramdisk
251 13:30:07.053979 >> 119260 blocks
252 13:30:08.992377 rename /var/lib/lava/dispatcher/tmp/11471176/extract-overlay-ramdisk-j00jjnp3/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11471176/tftp-deploy-5nyrh5z2/ramdisk/ramdisk.cpio.gz
253 13:30:08.992822 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 13:30:08.992945 start: 1.6.8 prepare-kernel (timeout 00:09:47) [common]
255 13:30:08.993046 start: 1.6.8.1 prepare-fit (timeout 00:09:47) [common]
256 13:30:08.993158 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11471176/tftp-deploy-5nyrh5z2/kernel/Image'
257 13:30:21.884352 Returned 0 in 12 seconds
258 13:30:21.985030 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11471176/tftp-deploy-5nyrh5z2/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11471176/tftp-deploy-5nyrh5z2/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11471176/tftp-deploy-5nyrh5z2/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11471176/tftp-deploy-5nyrh5z2/kernel/image.itb
259 13:30:22.367653 output: FIT description: Kernel Image image with one or more FDT blobs
260 13:30:22.368084 output: Created: Fri Sep 8 14:30:22 2023
261 13:30:22.368196 output: Image 0 (kernel-1)
262 13:30:22.368302 output: Description:
263 13:30:22.368401 output: Created: Fri Sep 8 14:30:22 2023
264 13:30:22.368498 output: Type: Kernel Image
265 13:30:22.368592 output: Compression: lzma compressed
266 13:30:22.368686 output: Data Size: 11040095 Bytes = 10781.34 KiB = 10.53 MiB
267 13:30:22.368779 output: Architecture: AArch64
268 13:30:22.368880 output: OS: Linux
269 13:30:22.368973 output: Load Address: 0x00000000
270 13:30:22.369069 output: Entry Point: 0x00000000
271 13:30:22.369158 output: Hash algo: crc32
272 13:30:22.369246 output: Hash value: 41c180c9
273 13:30:22.369339 output: Image 1 (fdt-1)
274 13:30:22.369426 output: Description: mt8192-asurada-spherion-r0
275 13:30:22.369512 output: Created: Fri Sep 8 14:30:22 2023
276 13:30:22.369596 output: Type: Flat Device Tree
277 13:30:22.369687 output: Compression: uncompressed
278 13:30:22.369776 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
279 13:30:22.369863 output: Architecture: AArch64
280 13:30:22.369950 output: Hash algo: crc32
281 13:30:22.370036 output: Hash value: cc4352de
282 13:30:22.370127 output: Image 2 (ramdisk-1)
283 13:30:22.370213 output: Description: unavailable
284 13:30:22.370299 output: Created: Fri Sep 8 14:30:22 2023
285 13:30:22.370386 output: Type: RAMDisk Image
286 13:30:22.370476 output: Compression: Unknown Compression
287 13:30:22.370565 output: Data Size: 17772488 Bytes = 17355.95 KiB = 16.95 MiB
288 13:30:22.370658 output: Architecture: AArch64
289 13:30:22.370746 output: OS: Linux
290 13:30:22.370831 output: Load Address: unavailable
291 13:30:22.370917 output: Entry Point: unavailable
292 13:30:22.371004 output: Hash algo: crc32
293 13:30:22.371093 output: Hash value: e1ada1b9
294 13:30:22.371183 output: Default Configuration: 'conf-1'
295 13:30:22.371267 output: Configuration 0 (conf-1)
296 13:30:22.371369 output: Description: mt8192-asurada-spherion-r0
297 13:30:22.371457 output: Kernel: kernel-1
298 13:30:22.371552 output: Init Ramdisk: ramdisk-1
299 13:30:22.371647 output: FDT: fdt-1
300 13:30:22.371732 output: Loadables: kernel-1
301 13:30:22.371820 output:
302 13:30:22.372085 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
303 13:30:22.372224 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
304 13:30:22.372369 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
305 13:30:22.372507 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:34) [common]
306 13:30:22.372618 No LXC device requested
307 13:30:22.372736 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 13:30:22.372858 start: 1.8 deploy-device-env (timeout 00:09:34) [common]
309 13:30:22.372971 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 13:30:22.373076 Checking files for TFTP limit of 4294967296 bytes.
311 13:30:22.373768 end: 1 tftp-deploy (duration 00:00:26) [common]
312 13:30:22.373904 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 13:30:22.374030 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 13:30:22.374210 substitutions:
315 13:30:22.374308 - {DTB}: 11471176/tftp-deploy-5nyrh5z2/dtb/mt8192-asurada-spherion-r0.dtb
316 13:30:22.374407 - {INITRD}: 11471176/tftp-deploy-5nyrh5z2/ramdisk/ramdisk.cpio.gz
317 13:30:22.374502 - {KERNEL}: 11471176/tftp-deploy-5nyrh5z2/kernel/Image
318 13:30:22.374595 - {LAVA_MAC}: None
319 13:30:22.374685 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/11471176/extract-nfsrootfs-tmw6wty7
320 13:30:22.374774 - {NFS_SERVER_IP}: 192.168.201.1
321 13:30:22.374865 - {PRESEED_CONFIG}: None
322 13:30:22.374953 - {PRESEED_LOCAL}: None
323 13:30:22.375041 - {RAMDISK}: 11471176/tftp-deploy-5nyrh5z2/ramdisk/ramdisk.cpio.gz
324 13:30:22.375127 - {ROOT_PART}: None
325 13:30:22.375216 - {ROOT}: None
326 13:30:22.375305 - {SERVER_IP}: 192.168.201.1
327 13:30:22.375393 - {TEE}: None
328 13:30:22.375481 Parsed boot commands:
329 13:30:22.375568 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 13:30:22.375804 Parsed boot commands: tftpboot 192.168.201.1 11471176/tftp-deploy-5nyrh5z2/kernel/image.itb 11471176/tftp-deploy-5nyrh5z2/kernel/cmdline
331 13:30:22.375932 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 13:30:22.376055 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 13:30:22.376190 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 13:30:22.376313 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 13:30:22.376422 Not connected, no need to disconnect.
336 13:30:22.376535 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 13:30:22.376661 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 13:30:22.376762 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
339 13:30:22.381051 Setting prompt string to ['lava-test: # ']
340 13:30:22.381486 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 13:30:22.381639 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 13:30:22.381774 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 13:30:22.381902 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 13:30:22.382248 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
345 13:30:27.527724 >> Command sent successfully.
346 13:30:27.530242 Returned 0 in 5 seconds
347 13:30:27.630669 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 13:30:27.631029 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 13:30:27.631136 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 13:30:27.631226 Setting prompt string to 'Starting depthcharge on Spherion...'
352 13:30:27.631297 Changing prompt to 'Starting depthcharge on Spherion...'
353 13:30:27.631368 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 13:30:27.631644 [Enter `^Ec?' for help]
355 13:30:27.805820
356 13:30:27.805979
357 13:30:27.806055 F0: 102B 0000
358 13:30:27.806120
359 13:30:27.806181 F3: 1001 0000 [0200]
360 13:30:27.808838
361 13:30:27.808927 F3: 1001 0000
362 13:30:27.808995
363 13:30:27.809058 F7: 102D 0000
364 13:30:27.809118
365 13:30:27.812091 F1: 0000 0000
366 13:30:27.812185
367 13:30:27.812253 V0: 0000 0000 [0001]
368 13:30:27.812327
369 13:30:27.815797 00: 0007 8000
370 13:30:27.815934
371 13:30:27.816006 01: 0000 0000
372 13:30:27.816070
373 13:30:27.818753 BP: 0C00 0209 [0000]
374 13:30:27.818840
375 13:30:27.818907 G0: 1182 0000
376 13:30:27.818969
377 13:30:27.821949 EC: 0000 0021 [4000]
378 13:30:27.822034
379 13:30:27.822101 S7: 0000 0000 [0000]
380 13:30:27.822164
381 13:30:27.826223 CC: 0000 0000 [0001]
382 13:30:27.826322
383 13:30:27.826392 T0: 0000 0040 [010F]
384 13:30:27.826455
385 13:30:27.826515 Jump to BL
386 13:30:27.826574
387 13:30:27.852425
388 13:30:27.852617
389 13:30:27.852706
390 13:30:27.859805 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 13:30:27.863699 ARM64: Exception handlers installed.
392 13:30:27.866579 ARM64: Testing exception
393 13:30:27.870174 ARM64: Done test exception
394 13:30:27.876570 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 13:30:27.887003 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 13:30:27.893343 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 13:30:27.903514 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 13:30:27.910139 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 13:30:27.919891 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 13:30:27.930464 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 13:30:27.936631 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 13:30:27.955362 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 13:30:27.958221 WDT: Last reset was cold boot
404 13:30:27.961482 SPI1(PAD0) initialized at 2873684 Hz
405 13:30:27.964851 SPI5(PAD0) initialized at 992727 Hz
406 13:30:27.968390 VBOOT: Loading verstage.
407 13:30:27.975311 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 13:30:27.978649 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 13:30:27.981476 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 13:30:27.984745 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 13:30:27.992809 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 13:30:27.999278 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 13:30:28.010234 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
414 13:30:28.010361
415 13:30:28.010456
416 13:30:28.020446 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 13:30:28.023633 ARM64: Exception handlers installed.
418 13:30:28.027019 ARM64: Testing exception
419 13:30:28.027114 ARM64: Done test exception
420 13:30:28.034516 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 13:30:28.037599 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 13:30:28.051162 Probing TPM: . done!
423 13:30:28.051295 TPM ready after 0 ms
424 13:30:28.059168 Connected to device vid:did:rid of 1ae0:0028:00
425 13:30:28.065769 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
426 13:30:28.124047 Initialized TPM device CR50 revision 0
427 13:30:28.135623 tlcl_send_startup: Startup return code is 0
428 13:30:28.135797 TPM: setup succeeded
429 13:30:28.146679 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 13:30:28.155495 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 13:30:28.167710 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 13:30:28.177675 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 13:30:28.181337 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 13:30:28.186196 in-header: 03 07 00 00 08 00 00 00
435 13:30:28.189992 in-data: aa e4 47 04 13 02 00 00
436 13:30:28.193260 Chrome EC: UHEPI supported
437 13:30:28.200820 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 13:30:28.204202 in-header: 03 95 00 00 08 00 00 00
439 13:30:28.207789 in-data: 18 20 20 08 00 00 00 00
440 13:30:28.207970 Phase 1
441 13:30:28.211390 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 13:30:28.219024 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 13:30:28.222531 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 13:30:28.225998 Recovery requested (1009000e)
445 13:30:28.235188 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 13:30:28.240215 tlcl_extend: response is 0
447 13:30:28.249442 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 13:30:28.254896 tlcl_extend: response is 0
449 13:30:28.262242 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 13:30:28.282186 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
451 13:30:28.288380 BS: bootblock times (exec / console): total (unknown) / 148 ms
452 13:30:28.288546
453 13:30:28.288640
454 13:30:28.298684 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 13:30:28.301948 ARM64: Exception handlers installed.
456 13:30:28.305510 ARM64: Testing exception
457 13:30:28.305633 ARM64: Done test exception
458 13:30:28.327214 pmic_efuse_setting: Set efuses in 11 msecs
459 13:30:28.330804 pmwrap_interface_init: Select PMIF_VLD_RDY
460 13:30:28.337323 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 13:30:28.340751 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 13:30:28.347860 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 13:30:28.351089 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 13:30:28.354664 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 13:30:28.362729 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 13:30:28.366504 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 13:30:28.370273 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 13:30:28.373362 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 13:30:28.380748 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 13:30:28.384448 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 13:30:28.387974 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 13:30:28.395240 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 13:30:28.399455 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 13:30:28.406092 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 13:30:28.410070 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 13:30:28.417752 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 13:30:28.421656 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 13:30:28.428683 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 13:30:28.432751 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 13:30:28.439660 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 13:30:28.443462 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 13:30:28.450911 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 13:30:28.455320 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 13:30:28.462185 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 13:30:28.465914 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 13:30:28.473266 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 13:30:28.476290 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 13:30:28.479820 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 13:30:28.487887 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 13:30:28.491545 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 13:30:28.495300 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 13:30:28.502080 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 13:30:28.505911 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 13:30:28.513110 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 13:30:28.516756 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 13:30:28.520537 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 13:30:28.527880 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 13:30:28.531396 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 13:30:28.534649 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 13:30:28.538466 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 13:30:28.545489 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 13:30:28.548923 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 13:30:28.553000 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 13:30:28.556815 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 13:30:28.559927 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 13:30:28.567226 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 13:30:28.571024 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 13:30:28.574533 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 13:30:28.578203 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 13:30:28.582007 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 13:30:28.589240 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 13:30:28.600356 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 13:30:28.604089 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 13:30:28.611270 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 13:30:28.618532 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 13:30:28.625647 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 13:30:28.629295 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 13:30:28.632650 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 13:30:28.640399 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x15
520 13:30:28.647862 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 13:30:28.651190 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
522 13:30:28.654643 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 13:30:28.664930 [RTC]rtc_get_frequency_meter,154: input=15, output=850
524 13:30:28.674612 [RTC]rtc_get_frequency_meter,154: input=7, output=723
525 13:30:28.684266 [RTC]rtc_get_frequency_meter,154: input=11, output=788
526 13:30:28.693447 [RTC]rtc_get_frequency_meter,154: input=13, output=820
527 13:30:28.703417 [RTC]rtc_get_frequency_meter,154: input=12, output=803
528 13:30:28.712634 [RTC]rtc_get_frequency_meter,154: input=11, output=787
529 13:30:28.722208 [RTC]rtc_get_frequency_meter,154: input=12, output=803
530 13:30:28.726518 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
531 13:30:28.729952 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
532 13:30:28.734408 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
533 13:30:28.741330 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
534 13:30:28.744750 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
535 13:30:28.748723 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
536 13:30:28.752043 ADC[4]: Raw value=904064 ID=7
537 13:30:28.752158 ADC[3]: Raw value=213916 ID=1
538 13:30:28.755727 RAM Code: 0x71
539 13:30:28.759703 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
540 13:30:28.763240 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
541 13:30:28.774301 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
542 13:30:28.778529 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
543 13:30:28.781470 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
544 13:30:28.785691 in-header: 03 07 00 00 08 00 00 00
545 13:30:28.789556 in-data: aa e4 47 04 13 02 00 00
546 13:30:28.793157 Chrome EC: UHEPI supported
547 13:30:28.807313 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
548 13:30:28.807528 in-header: 03 95 00 00 08 00 00 00
549 13:30:28.807871 in-data: 18 20 20 08 00 00 00 00
550 13:30:28.811581 MRC: failed to locate region type 0.
551 13:30:28.815470 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
552 13:30:28.818998 DRAM-K: Running full calibration
553 13:30:28.826159 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 13:30:28.826310 header.status = 0x0
555 13:30:28.829912 header.version = 0x6 (expected: 0x6)
556 13:30:28.833875 header.size = 0xd00 (expected: 0xd00)
557 13:30:28.837599 header.flags = 0x0
558 13:30:28.840716 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
559 13:30:28.861171 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
560 13:30:28.868440 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
561 13:30:28.868585 dram_init: ddr_geometry: 2
562 13:30:28.871881 [EMI] MDL number = 2
563 13:30:28.875583 [EMI] Get MDL freq = 0
564 13:30:28.875688 dram_init: ddr_type: 0
565 13:30:28.879548 is_discrete_lpddr4: 1
566 13:30:28.882820 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
567 13:30:28.882911
568 13:30:28.882979
569 13:30:28.883043 [Bian_co] ETT version 0.0.0.1
570 13:30:28.890578 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
571 13:30:28.890683
572 13:30:28.894432 dramc_set_vcore_voltage set vcore to 650000
573 13:30:28.894528 Read voltage for 800, 4
574 13:30:28.898127 Vio18 = 0
575 13:30:28.898219 Vcore = 650000
576 13:30:28.898288 Vdram = 0
577 13:30:28.898351 Vddq = 0
578 13:30:28.901120 Vmddr = 0
579 13:30:28.901217 dram_init: config_dvfs: 1
580 13:30:28.908606 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
581 13:30:28.912290 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
582 13:30:28.915454 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
583 13:30:28.919328 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
584 13:30:28.925255 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
585 13:30:28.928919 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
586 13:30:28.929051 MEM_TYPE=3, freq_sel=18
587 13:30:28.931762 sv_algorithm_assistance_LP4_1600
588 13:30:28.935644 ============ PULL DRAM RESETB DOWN ============
589 13:30:28.939814 ========== PULL DRAM RESETB DOWN end =========
590 13:30:28.947185 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
591 13:30:28.950704 ===================================
592 13:30:28.950815 LPDDR4 DRAM CONFIGURATION
593 13:30:28.954520 ===================================
594 13:30:28.957515 EX_ROW_EN[0] = 0x0
595 13:30:28.957616 EX_ROW_EN[1] = 0x0
596 13:30:28.960722 LP4Y_EN = 0x0
597 13:30:28.960814 WORK_FSP = 0x0
598 13:30:28.964170 WL = 0x2
599 13:30:28.964262 RL = 0x2
600 13:30:28.967497 BL = 0x2
601 13:30:28.967586 RPST = 0x0
602 13:30:28.971080 RD_PRE = 0x0
603 13:30:28.974448 WR_PRE = 0x1
604 13:30:28.974541 WR_PST = 0x0
605 13:30:28.977348 DBI_WR = 0x0
606 13:30:28.977440 DBI_RD = 0x0
607 13:30:28.980702 OTF = 0x1
608 13:30:28.984452 ===================================
609 13:30:28.987262 ===================================
610 13:30:28.987358 ANA top config
611 13:30:28.990753 ===================================
612 13:30:28.994141 DLL_ASYNC_EN = 0
613 13:30:28.997254 ALL_SLAVE_EN = 1
614 13:30:28.997348 NEW_RANK_MODE = 1
615 13:30:29.000923 DLL_IDLE_MODE = 1
616 13:30:29.003863 LP45_APHY_COMB_EN = 1
617 13:30:29.007538 TX_ODT_DIS = 1
618 13:30:29.007655 NEW_8X_MODE = 1
619 13:30:29.010545 ===================================
620 13:30:29.013591 ===================================
621 13:30:29.017422 data_rate = 1600
622 13:30:29.020565 CKR = 1
623 13:30:29.024393 DQ_P2S_RATIO = 8
624 13:30:29.027251 ===================================
625 13:30:29.031044 CA_P2S_RATIO = 8
626 13:30:29.034591 DQ_CA_OPEN = 0
627 13:30:29.034686 DQ_SEMI_OPEN = 0
628 13:30:29.038088 CA_SEMI_OPEN = 0
629 13:30:29.041017 CA_FULL_RATE = 0
630 13:30:29.044280 DQ_CKDIV4_EN = 1
631 13:30:29.047929 CA_CKDIV4_EN = 1
632 13:30:29.048026 CA_PREDIV_EN = 0
633 13:30:29.051506 PH8_DLY = 0
634 13:30:29.054590 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
635 13:30:29.057598 DQ_AAMCK_DIV = 4
636 13:30:29.061370 CA_AAMCK_DIV = 4
637 13:30:29.064478 CA_ADMCK_DIV = 4
638 13:30:29.064572 DQ_TRACK_CA_EN = 0
639 13:30:29.067540 CA_PICK = 800
640 13:30:29.070875 CA_MCKIO = 800
641 13:30:29.074511 MCKIO_SEMI = 0
642 13:30:29.078152 PLL_FREQ = 3068
643 13:30:29.082059 DQ_UI_PI_RATIO = 32
644 13:30:29.082175 CA_UI_PI_RATIO = 0
645 13:30:29.085709 ===================================
646 13:30:29.089216 ===================================
647 13:30:29.092944 memory_type:LPDDR4
648 13:30:29.093040 GP_NUM : 10
649 13:30:29.096590 SRAM_EN : 1
650 13:30:29.099388 MD32_EN : 0
651 13:30:29.103381 ===================================
652 13:30:29.103509 [ANA_INIT] >>>>>>>>>>>>>>
653 13:30:29.106944 <<<<<< [CONFIGURE PHASE]: ANA_TX
654 13:30:29.110157 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
655 13:30:29.113820 ===================================
656 13:30:29.117014 data_rate = 1600,PCW = 0X7600
657 13:30:29.120170 ===================================
658 13:30:29.123688 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
659 13:30:29.127380 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
660 13:30:29.133560 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
661 13:30:29.137067 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
662 13:30:29.140118 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
663 13:30:29.146620 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
664 13:30:29.146771 [ANA_INIT] flow start
665 13:30:29.149956 [ANA_INIT] PLL >>>>>>>>
666 13:30:29.153639 [ANA_INIT] PLL <<<<<<<<
667 13:30:29.153759 [ANA_INIT] MIDPI >>>>>>>>
668 13:30:29.157138 [ANA_INIT] MIDPI <<<<<<<<
669 13:30:29.159864 [ANA_INIT] DLL >>>>>>>>
670 13:30:29.159987 [ANA_INIT] flow end
671 13:30:29.163496 ============ LP4 DIFF to SE enter ============
672 13:30:29.170135 ============ LP4 DIFF to SE exit ============
673 13:30:29.170257 [ANA_INIT] <<<<<<<<<<<<<
674 13:30:29.173255 [Flow] Enable top DCM control >>>>>
675 13:30:29.176753 [Flow] Enable top DCM control <<<<<
676 13:30:29.180230 Enable DLL master slave shuffle
677 13:30:29.186636 ==============================================================
678 13:30:29.186768 Gating Mode config
679 13:30:29.193471 ==============================================================
680 13:30:29.196414 Config description:
681 13:30:29.206793 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
682 13:30:29.213173 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
683 13:30:29.216785 SELPH_MODE 0: By rank 1: By Phase
684 13:30:29.222973 ==============================================================
685 13:30:29.226427 GAT_TRACK_EN = 1
686 13:30:29.230246 RX_GATING_MODE = 2
687 13:30:29.230371 RX_GATING_TRACK_MODE = 2
688 13:30:29.233335 SELPH_MODE = 1
689 13:30:29.236394 PICG_EARLY_EN = 1
690 13:30:29.240130 VALID_LAT_VALUE = 1
691 13:30:29.246695 ==============================================================
692 13:30:29.249818 Enter into Gating configuration >>>>
693 13:30:29.253205 Exit from Gating configuration <<<<
694 13:30:29.256666 Enter into DVFS_PRE_config >>>>>
695 13:30:29.266438 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
696 13:30:29.269645 Exit from DVFS_PRE_config <<<<<
697 13:30:29.273093 Enter into PICG configuration >>>>
698 13:30:29.276836 Exit from PICG configuration <<<<
699 13:30:29.279757 [RX_INPUT] configuration >>>>>
700 13:30:29.283161 [RX_INPUT] configuration <<<<<
701 13:30:29.286356 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
702 13:30:29.292791 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
703 13:30:29.299728 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
704 13:30:29.306356 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
705 13:30:29.309416 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
706 13:30:29.316658 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
707 13:30:29.319515 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
708 13:30:29.326437 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
709 13:30:29.329440 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
710 13:30:29.333222 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
711 13:30:29.336141 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
712 13:30:29.342610 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
713 13:30:29.346315 ===================================
714 13:30:29.346391 LPDDR4 DRAM CONFIGURATION
715 13:30:29.349240 ===================================
716 13:30:29.353036 EX_ROW_EN[0] = 0x0
717 13:30:29.355941 EX_ROW_EN[1] = 0x0
718 13:30:29.356016 LP4Y_EN = 0x0
719 13:30:29.359451 WORK_FSP = 0x0
720 13:30:29.359539 WL = 0x2
721 13:30:29.362324 RL = 0x2
722 13:30:29.362428 BL = 0x2
723 13:30:29.365972 RPST = 0x0
724 13:30:29.366091 RD_PRE = 0x0
725 13:30:29.369376 WR_PRE = 0x1
726 13:30:29.369468 WR_PST = 0x0
727 13:30:29.372698 DBI_WR = 0x0
728 13:30:29.372790 DBI_RD = 0x0
729 13:30:29.375628 OTF = 0x1
730 13:30:29.379199 ===================================
731 13:30:29.382159 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
732 13:30:29.385577 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
733 13:30:29.392381 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
734 13:30:29.395598 ===================================
735 13:30:29.395702 LPDDR4 DRAM CONFIGURATION
736 13:30:29.399022 ===================================
737 13:30:29.402263 EX_ROW_EN[0] = 0x10
738 13:30:29.405871 EX_ROW_EN[1] = 0x0
739 13:30:29.406014 LP4Y_EN = 0x0
740 13:30:29.409345 WORK_FSP = 0x0
741 13:30:29.409470 WL = 0x2
742 13:30:29.412385 RL = 0x2
743 13:30:29.412470 BL = 0x2
744 13:30:29.416030 RPST = 0x0
745 13:30:29.416123 RD_PRE = 0x0
746 13:30:29.419011 WR_PRE = 0x1
747 13:30:29.419123 WR_PST = 0x0
748 13:30:29.422087 DBI_WR = 0x0
749 13:30:29.422194 DBI_RD = 0x0
750 13:30:29.425623 OTF = 0x1
751 13:30:29.429146 ===================================
752 13:30:29.435507 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
753 13:30:29.438785 nWR fixed to 40
754 13:30:29.438914 [ModeRegInit_LP4] CH0 RK0
755 13:30:29.442408 [ModeRegInit_LP4] CH0 RK1
756 13:30:29.445244 [ModeRegInit_LP4] CH1 RK0
757 13:30:29.448582 [ModeRegInit_LP4] CH1 RK1
758 13:30:29.448678 match AC timing 13
759 13:30:29.455511 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
760 13:30:29.458490 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
761 13:30:29.462131 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
762 13:30:29.468821 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
763 13:30:29.472511 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
764 13:30:29.472643 [EMI DOE] emi_dcm 0
765 13:30:29.478646 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
766 13:30:29.478792 ==
767 13:30:29.482575 Dram Type= 6, Freq= 0, CH_0, rank 0
768 13:30:29.485541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
769 13:30:29.485637 ==
770 13:30:29.492193 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
771 13:30:29.495492 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
772 13:30:29.505694 [CA 0] Center 37 (7~68) winsize 62
773 13:30:29.508947 [CA 1] Center 37 (6~68) winsize 63
774 13:30:29.512600 [CA 2] Center 35 (4~66) winsize 63
775 13:30:29.515986 [CA 3] Center 35 (4~66) winsize 63
776 13:30:29.518941 [CA 4] Center 33 (3~64) winsize 62
777 13:30:29.522602 [CA 5] Center 33 (3~64) winsize 62
778 13:30:29.522689
779 13:30:29.525544 [CmdBusTrainingLP45] Vref(ca) range 1: 34
780 13:30:29.525632
781 13:30:29.529249 [CATrainingPosCal] consider 1 rank data
782 13:30:29.532372 u2DelayCellTimex100 = 270/100 ps
783 13:30:29.535799 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
784 13:30:29.541998 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
785 13:30:29.545793 CA2 delay=35 (4~66),Diff = 2 PI (14 cell)
786 13:30:29.548718 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
787 13:30:29.552421 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
788 13:30:29.555533 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
789 13:30:29.555643
790 13:30:29.558547 CA PerBit enable=1, Macro0, CA PI delay=33
791 13:30:29.558652
792 13:30:29.562173 [CBTSetCACLKResult] CA Dly = 33
793 13:30:29.565352 CS Dly: 6 (0~37)
794 13:30:29.565456 ==
795 13:30:29.568920 Dram Type= 6, Freq= 0, CH_0, rank 1
796 13:30:29.571660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
797 13:30:29.571779 ==
798 13:30:29.578691 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
799 13:30:29.581696 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
800 13:30:29.592574 [CA 0] Center 38 (7~69) winsize 63
801 13:30:29.595827 [CA 1] Center 37 (7~68) winsize 62
802 13:30:29.598924 [CA 2] Center 35 (4~66) winsize 63
803 13:30:29.602404 [CA 3] Center 35 (4~66) winsize 63
804 13:30:29.605385 [CA 4] Center 34 (3~65) winsize 63
805 13:30:29.608948 [CA 5] Center 33 (3~64) winsize 62
806 13:30:29.609036
807 13:30:29.612287 [CmdBusTrainingLP45] Vref(ca) range 1: 32
808 13:30:29.612375
809 13:30:29.615842 [CATrainingPosCal] consider 2 rank data
810 13:30:29.618558 u2DelayCellTimex100 = 270/100 ps
811 13:30:29.621968 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
812 13:30:29.628571 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
813 13:30:29.632158 CA2 delay=35 (4~66),Diff = 2 PI (14 cell)
814 13:30:29.635113 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
815 13:30:29.638927 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
816 13:30:29.641741 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
817 13:30:29.641969
818 13:30:29.645141 CA PerBit enable=1, Macro0, CA PI delay=33
819 13:30:29.645246
820 13:30:29.648582 [CBTSetCACLKResult] CA Dly = 33
821 13:30:29.652146 CS Dly: 6 (0~38)
822 13:30:29.652234
823 13:30:29.655277 ----->DramcWriteLeveling(PI) begin...
824 13:30:29.655360 ==
825 13:30:29.661137 Dram Type= 6, Freq= 0, CH_0, rank 0
826 13:30:29.662594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
827 13:30:29.662718 ==
828 13:30:29.666590 Write leveling (Byte 0): 29 => 29
829 13:30:29.666695 Write leveling (Byte 1): 27 => 27
830 13:30:29.670129 DramcWriteLeveling(PI) end<-----
831 13:30:29.670262
832 13:30:29.670391 ==
833 13:30:29.673297 Dram Type= 6, Freq= 0, CH_0, rank 0
834 13:30:29.679711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
835 13:30:29.679838 ==
836 13:30:29.683496 [Gating] SW mode calibration
837 13:30:29.687520 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
838 13:30:29.693757 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
839 13:30:29.697081 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
840 13:30:29.703736 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
841 13:30:29.707081 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
842 13:30:29.710434 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
843 13:30:29.717032 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 13:30:29.720549 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 13:30:29.723400 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 13:30:29.730309 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 13:30:29.733450 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 13:30:29.736525 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 13:30:29.743945 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 13:30:29.746796 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 13:30:29.749921 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 13:30:29.756545 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 13:30:29.760103 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 13:30:29.763165 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 13:30:29.769892 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 13:30:29.773775 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
857 13:30:29.776703 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
858 13:30:29.783383 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
859 13:30:29.786762 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 13:30:29.789497 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 13:30:29.796696 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 13:30:29.800160 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 13:30:29.803017 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 13:30:29.806403 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
865 13:30:29.813212 0 9 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
866 13:30:29.816234 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
867 13:30:29.819858 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
868 13:30:29.826497 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
869 13:30:29.829745 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
870 13:30:29.833014 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
871 13:30:29.839860 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
872 13:30:29.843460 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
873 13:30:29.846573 0 10 8 | B1->B0 | 3434 2424 | 0 0 | (0 1) (1 0)
874 13:30:29.853422 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
875 13:30:29.856341 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 13:30:29.859702 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 13:30:29.866511 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 13:30:29.869481 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 13:30:29.873133 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
880 13:30:29.880035 0 11 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
881 13:30:29.883252 0 11 8 | B1->B0 | 2a2a 3d3d | 0 0 | (0 0) (1 1)
882 13:30:29.886210 0 11 12 | B1->B0 | 3c3b 4646 | 1 0 | (0 0) (0 0)
883 13:30:29.892885 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
884 13:30:29.896319 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
885 13:30:29.899515 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
886 13:30:29.905964 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 13:30:29.909515 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
888 13:30:29.913141 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
889 13:30:29.919487 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
890 13:30:29.922985 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
891 13:30:29.926300 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
892 13:30:29.929125 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
893 13:30:29.935873 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
894 13:30:29.939109 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
895 13:30:29.943067 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
896 13:30:29.949541 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
897 13:30:29.952607 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 13:30:29.955852 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 13:30:29.962432 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 13:30:29.965957 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 13:30:29.968938 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 13:30:29.975944 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 13:30:29.979100 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 13:30:29.982726 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 13:30:29.988822 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
906 13:30:29.992661 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
907 13:30:29.995693 Total UI for P1: 0, mck2ui 16
908 13:30:29.999250 best dqsien dly found for B0: ( 0, 14, 8)
909 13:30:30.002200 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
910 13:30:30.005514 Total UI for P1: 0, mck2ui 16
911 13:30:30.008871 best dqsien dly found for B1: ( 0, 14, 12)
912 13:30:30.012164 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
913 13:30:30.015653 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
914 13:30:30.015740
915 13:30:30.022344 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
916 13:30:30.025195 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
917 13:30:30.029266 [Gating] SW calibration Done
918 13:30:30.029376 ==
919 13:30:30.029477 Dram Type= 6, Freq= 0, CH_0, rank 0
920 13:30:30.036007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 13:30:30.036127 ==
922 13:30:30.036228 RX Vref Scan: 0
923 13:30:30.036326
924 13:30:30.039486 RX Vref 0 -> 0, step: 1
925 13:30:30.039578
926 13:30:30.043199 RX Delay -130 -> 252, step: 16
927 13:30:30.046004 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
928 13:30:30.049777 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
929 13:30:30.052838 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
930 13:30:30.059543 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
931 13:30:30.062543 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
932 13:30:30.066078 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
933 13:30:30.069132 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
934 13:30:30.072831 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
935 13:30:30.079255 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
936 13:30:30.082724 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
937 13:30:30.085754 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
938 13:30:30.089492 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
939 13:30:30.092492 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
940 13:30:30.099363 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
941 13:30:30.102401 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
942 13:30:30.105523 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
943 13:30:30.105625 ==
944 13:30:30.109146 Dram Type= 6, Freq= 0, CH_0, rank 0
945 13:30:30.112542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
946 13:30:30.115981 ==
947 13:30:30.116083 DQS Delay:
948 13:30:30.116179 DQS0 = 0, DQS1 = 0
949 13:30:30.119348 DQM Delay:
950 13:30:30.119461 DQM0 = 87, DQM1 = 75
951 13:30:30.119558 DQ Delay:
952 13:30:30.122267 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
953 13:30:30.126066 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =93
954 13:30:30.129061 DQ8 =61, DQ9 =53, DQ10 =77, DQ11 =69
955 13:30:30.132488 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
956 13:30:30.132591
957 13:30:30.132688
958 13:30:30.135945 ==
959 13:30:30.138938 Dram Type= 6, Freq= 0, CH_0, rank 0
960 13:30:30.142360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
961 13:30:30.142477 ==
962 13:30:30.142574
963 13:30:30.142668
964 13:30:30.145722 TX Vref Scan disable
965 13:30:30.145835 == TX Byte 0 ==
966 13:30:30.152376 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
967 13:30:30.155863 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
968 13:30:30.155990 == TX Byte 1 ==
969 13:30:30.162233 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
970 13:30:30.165683 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
971 13:30:30.165793 ==
972 13:30:30.168561 Dram Type= 6, Freq= 0, CH_0, rank 0
973 13:30:30.172226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 13:30:30.172331 ==
975 13:30:30.185666 TX Vref=22, minBit 1, minWin=26, winSum=437
976 13:30:30.189061 TX Vref=24, minBit 1, minWin=26, winSum=439
977 13:30:30.192106 TX Vref=26, minBit 0, minWin=27, winSum=444
978 13:30:30.195739 TX Vref=28, minBit 1, minWin=27, winSum=447
979 13:30:30.198849 TX Vref=30, minBit 1, minWin=27, winSum=454
980 13:30:30.202374 TX Vref=32, minBit 6, minWin=27, winSum=445
981 13:30:30.208955 [TxChooseVref] Worse bit 1, Min win 27, Win sum 454, Final Vref 30
982 13:30:30.209064
983 13:30:30.212040 Final TX Range 1 Vref 30
984 13:30:30.212144
985 13:30:30.212236 ==
986 13:30:30.215713 Dram Type= 6, Freq= 0, CH_0, rank 0
987 13:30:30.219128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 13:30:30.219234 ==
989 13:30:30.219331
990 13:30:30.221947
991 13:30:30.222034 TX Vref Scan disable
992 13:30:30.225965 == TX Byte 0 ==
993 13:30:30.228877 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
994 13:30:30.235490 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
995 13:30:30.235576 == TX Byte 1 ==
996 13:30:30.238878 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
997 13:30:30.242290 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
998 13:30:30.245767
999 13:30:30.245853 [DATLAT]
1000 13:30:30.245920 Freq=800, CH0 RK0
1001 13:30:30.245984
1002 13:30:30.249010 DATLAT Default: 0xa
1003 13:30:30.249095 0, 0xFFFF, sum = 0
1004 13:30:30.252585 1, 0xFFFF, sum = 0
1005 13:30:30.252674 2, 0xFFFF, sum = 0
1006 13:30:30.255737 3, 0xFFFF, sum = 0
1007 13:30:30.255822 4, 0xFFFF, sum = 0
1008 13:30:30.258734 5, 0xFFFF, sum = 0
1009 13:30:30.262352 6, 0xFFFF, sum = 0
1010 13:30:30.262439 7, 0xFFFF, sum = 0
1011 13:30:30.265254 8, 0xFFFF, sum = 0
1012 13:30:30.265340 9, 0x0, sum = 1
1013 13:30:30.265410 10, 0x0, sum = 2
1014 13:30:30.269097 11, 0x0, sum = 3
1015 13:30:30.269182 12, 0x0, sum = 4
1016 13:30:30.272325 best_step = 10
1017 13:30:30.272410
1018 13:30:30.272477 ==
1019 13:30:30.275629 Dram Type= 6, Freq= 0, CH_0, rank 0
1020 13:30:30.278597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1021 13:30:30.278702 ==
1022 13:30:30.282123 RX Vref Scan: 1
1023 13:30:30.282208
1024 13:30:30.285140 Set Vref Range= 32 -> 127
1025 13:30:30.285229
1026 13:30:30.285296 RX Vref 32 -> 127, step: 1
1027 13:30:30.285359
1028 13:30:30.288850 RX Delay -111 -> 252, step: 8
1029 13:30:30.288933
1030 13:30:30.292431 Set Vref, RX VrefLevel [Byte0]: 32
1031 13:30:30.295203 [Byte1]: 32
1032 13:30:30.295313
1033 13:30:30.298592 Set Vref, RX VrefLevel [Byte0]: 33
1034 13:30:30.301688 [Byte1]: 33
1035 13:30:30.305926
1036 13:30:30.306027 Set Vref, RX VrefLevel [Byte0]: 34
1037 13:30:30.309804 [Byte1]: 34
1038 13:30:30.314041
1039 13:30:30.314160 Set Vref, RX VrefLevel [Byte0]: 35
1040 13:30:30.317214 [Byte1]: 35
1041 13:30:30.321927
1042 13:30:30.322133 Set Vref, RX VrefLevel [Byte0]: 36
1043 13:30:30.325567 [Byte1]: 36
1044 13:30:30.329573
1045 13:30:30.329690 Set Vref, RX VrefLevel [Byte0]: 37
1046 13:30:30.332824 [Byte1]: 37
1047 13:30:30.337173
1048 13:30:30.337259 Set Vref, RX VrefLevel [Byte0]: 38
1049 13:30:30.340681 [Byte1]: 38
1050 13:30:30.344966
1051 13:30:30.345053 Set Vref, RX VrefLevel [Byte0]: 39
1052 13:30:30.348313 [Byte1]: 39
1053 13:30:30.352536
1054 13:30:30.352624 Set Vref, RX VrefLevel [Byte0]: 40
1055 13:30:30.355707 [Byte1]: 40
1056 13:30:30.359385
1057 13:30:30.359472 Set Vref, RX VrefLevel [Byte0]: 41
1058 13:30:30.363061 [Byte1]: 41
1059 13:30:30.367308
1060 13:30:30.367393 Set Vref, RX VrefLevel [Byte0]: 42
1061 13:30:30.370298 [Byte1]: 42
1062 13:30:30.375119
1063 13:30:30.375204 Set Vref, RX VrefLevel [Byte0]: 43
1064 13:30:30.377969 [Byte1]: 43
1065 13:30:30.382675
1066 13:30:30.382758 Set Vref, RX VrefLevel [Byte0]: 44
1067 13:30:30.385956 [Byte1]: 44
1068 13:30:30.390094
1069 13:30:30.390184 Set Vref, RX VrefLevel [Byte0]: 45
1070 13:30:30.393770 [Byte1]: 45
1071 13:30:30.397949
1072 13:30:30.398034 Set Vref, RX VrefLevel [Byte0]: 46
1073 13:30:30.400952 [Byte1]: 46
1074 13:30:30.405442
1075 13:30:30.405524 Set Vref, RX VrefLevel [Byte0]: 47
1076 13:30:30.408944 [Byte1]: 47
1077 13:30:30.413343
1078 13:30:30.413426 Set Vref, RX VrefLevel [Byte0]: 48
1079 13:30:30.416429 [Byte1]: 48
1080 13:30:30.420723
1081 13:30:30.420809 Set Vref, RX VrefLevel [Byte0]: 49
1082 13:30:30.424398 [Byte1]: 49
1083 13:30:30.428484
1084 13:30:30.428572 Set Vref, RX VrefLevel [Byte0]: 50
1085 13:30:30.431394 [Byte1]: 50
1086 13:30:30.436012
1087 13:30:30.436098 Set Vref, RX VrefLevel [Byte0]: 51
1088 13:30:30.439359 [Byte1]: 51
1089 13:30:30.443419
1090 13:30:30.443503 Set Vref, RX VrefLevel [Byte0]: 52
1091 13:30:30.447010 [Byte1]: 52
1092 13:30:30.451198
1093 13:30:30.451284 Set Vref, RX VrefLevel [Byte0]: 53
1094 13:30:30.454611 [Byte1]: 53
1095 13:30:30.458876
1096 13:30:30.458980 Set Vref, RX VrefLevel [Byte0]: 54
1097 13:30:30.462091 [Byte1]: 54
1098 13:30:30.466849
1099 13:30:30.466937 Set Vref, RX VrefLevel [Byte0]: 55
1100 13:30:30.469939 [Byte1]: 55
1101 13:30:30.474072
1102 13:30:30.474156 Set Vref, RX VrefLevel [Byte0]: 56
1103 13:30:30.477755 [Byte1]: 56
1104 13:30:30.481963
1105 13:30:30.482047 Set Vref, RX VrefLevel [Byte0]: 57
1106 13:30:30.485065 [Byte1]: 57
1107 13:30:30.489517
1108 13:30:30.489601 Set Vref, RX VrefLevel [Byte0]: 58
1109 13:30:30.492830 [Byte1]: 58
1110 13:30:30.497362
1111 13:30:30.497476 Set Vref, RX VrefLevel [Byte0]: 59
1112 13:30:30.500863 [Byte1]: 59
1113 13:30:30.505181
1114 13:30:30.505293 Set Vref, RX VrefLevel [Byte0]: 60
1115 13:30:30.508105 [Byte1]: 60
1116 13:30:30.512189
1117 13:30:30.512293 Set Vref, RX VrefLevel [Byte0]: 61
1118 13:30:30.515537 [Byte1]: 61
1119 13:30:30.520465
1120 13:30:30.520588 Set Vref, RX VrefLevel [Byte0]: 62
1121 13:30:30.523489 [Byte1]: 62
1122 13:30:30.527770
1123 13:30:30.527892 Set Vref, RX VrefLevel [Byte0]: 63
1124 13:30:30.531248 [Byte1]: 63
1125 13:30:30.535367
1126 13:30:30.535478 Set Vref, RX VrefLevel [Byte0]: 64
1127 13:30:30.538430 [Byte1]: 64
1128 13:30:30.542933
1129 13:30:30.543046 Set Vref, RX VrefLevel [Byte0]: 65
1130 13:30:30.546187 [Byte1]: 65
1131 13:30:30.550957
1132 13:30:30.551072 Set Vref, RX VrefLevel [Byte0]: 66
1133 13:30:30.553994 [Byte1]: 66
1134 13:30:30.558035
1135 13:30:30.558154 Set Vref, RX VrefLevel [Byte0]: 67
1136 13:30:30.561684 [Byte1]: 67
1137 13:30:30.565849
1138 13:30:30.565971 Set Vref, RX VrefLevel [Byte0]: 68
1139 13:30:30.569170 [Byte1]: 68
1140 13:30:30.573741
1141 13:30:30.573833 Set Vref, RX VrefLevel [Byte0]: 69
1142 13:30:30.576763 [Byte1]: 69
1143 13:30:30.581048
1144 13:30:30.581133 Set Vref, RX VrefLevel [Byte0]: 70
1145 13:30:30.584608 [Byte1]: 70
1146 13:30:30.588928
1147 13:30:30.589014 Set Vref, RX VrefLevel [Byte0]: 71
1148 13:30:30.591989 [Byte1]: 71
1149 13:30:30.596708
1150 13:30:30.600170 Set Vref, RX VrefLevel [Byte0]: 72
1151 13:30:30.602907 [Byte1]: 72
1152 13:30:30.603050
1153 13:30:30.606020 Set Vref, RX VrefLevel [Byte0]: 73
1154 13:30:30.609455 [Byte1]: 73
1155 13:30:30.609548
1156 13:30:30.613222 Set Vref, RX VrefLevel [Byte0]: 74
1157 13:30:30.616259 [Byte1]: 74
1158 13:30:30.619693
1159 13:30:30.619829 Final RX Vref Byte 0 = 56 to rank0
1160 13:30:30.623062 Final RX Vref Byte 1 = 61 to rank0
1161 13:30:30.626047 Final RX Vref Byte 0 = 56 to rank1
1162 13:30:30.629190 Final RX Vref Byte 1 = 61 to rank1==
1163 13:30:30.632798 Dram Type= 6, Freq= 0, CH_0, rank 0
1164 13:30:30.639184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1165 13:30:30.639326 ==
1166 13:30:30.639457 DQS Delay:
1167 13:30:30.642386 DQS0 = 0, DQS1 = 0
1168 13:30:30.642520 DQM Delay:
1169 13:30:30.642644 DQM0 = 88, DQM1 = 76
1170 13:30:30.645917 DQ Delay:
1171 13:30:30.649228 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1172 13:30:30.652599 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1173 13:30:30.655997 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =72
1174 13:30:30.659075 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1175 13:30:30.659212
1176 13:30:30.659342
1177 13:30:30.665634 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c26, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
1178 13:30:30.668637 CH0 RK0: MR19=606, MR18=2C26
1179 13:30:30.675362 CH0_RK0: MR19=0x606, MR18=0x2C26, DQSOSC=398, MR23=63, INC=93, DEC=62
1180 13:30:30.675505
1181 13:30:30.678593 ----->DramcWriteLeveling(PI) begin...
1182 13:30:30.678733 ==
1183 13:30:30.681869 Dram Type= 6, Freq= 0, CH_0, rank 1
1184 13:30:30.685459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1185 13:30:30.685601 ==
1186 13:30:30.688476 Write leveling (Byte 0): 31 => 31
1187 13:30:30.692245 Write leveling (Byte 1): 29 => 29
1188 13:30:30.695277 DramcWriteLeveling(PI) end<-----
1189 13:30:30.695415
1190 13:30:30.695539 ==
1191 13:30:30.698329 Dram Type= 6, Freq= 0, CH_0, rank 1
1192 13:30:30.701920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1193 13:30:30.705028 ==
1194 13:30:30.705170 [Gating] SW mode calibration
1195 13:30:30.711856 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1196 13:30:30.718536 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1197 13:30:30.762220 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1198 13:30:30.762655 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1199 13:30:30.762797 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1200 13:30:30.762924 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 13:30:30.763050 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 13:30:30.763195 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 13:30:30.763323 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 13:30:30.763449 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 13:30:30.763571 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 13:30:30.763716 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 13:30:30.806579 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 13:30:30.806806 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 13:30:30.807152 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 13:30:30.807285 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 13:30:30.807408 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 13:30:30.807530 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 13:30:30.807673 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 13:30:30.807796 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1215 13:30:30.807925 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1216 13:30:30.808049 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1217 13:30:30.810996 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 13:30:30.814472 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 13:30:30.820816 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 13:30:30.824211 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 13:30:30.827713 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 13:30:30.834408 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1223 13:30:30.837635 0 9 8 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
1224 13:30:30.841080 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1225 13:30:30.847551 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1226 13:30:30.850668 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1227 13:30:30.854405 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1228 13:30:30.860836 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1229 13:30:30.863809 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1230 13:30:30.867223 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
1231 13:30:30.873587 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
1232 13:30:30.877262 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1233 13:30:30.880265 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 13:30:30.886933 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 13:30:30.890610 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 13:30:30.893546 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 13:30:30.896830 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 13:30:30.904206 0 11 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
1239 13:30:30.908399 0 11 8 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
1240 13:30:30.912075 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1241 13:30:30.915134 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1242 13:30:30.922479 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1243 13:30:30.925685 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1244 13:30:30.929113 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1245 13:30:30.932656 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1246 13:30:30.939376 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1247 13:30:30.943016 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1248 13:30:30.946476 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 13:30:30.953122 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 13:30:30.956153 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 13:30:30.959615 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 13:30:30.966156 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 13:30:30.969654 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 13:30:30.972504 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 13:30:30.979447 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 13:30:30.982471 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 13:30:30.985603 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 13:30:30.992393 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 13:30:30.996012 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 13:30:30.999008 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 13:30:31.002648 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 13:30:31.009051 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1263 13:30:31.012286 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1264 13:30:31.015786 Total UI for P1: 0, mck2ui 16
1265 13:30:31.018768 best dqsien dly found for B0: ( 0, 14, 4)
1266 13:30:31.022426 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 13:30:31.025598 Total UI for P1: 0, mck2ui 16
1268 13:30:31.029077 best dqsien dly found for B1: ( 0, 14, 8)
1269 13:30:31.031955 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1270 13:30:31.038692 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1271 13:30:31.038820
1272 13:30:31.042198 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1273 13:30:31.045763 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1274 13:30:31.048807 [Gating] SW calibration Done
1275 13:30:31.048909 ==
1276 13:30:31.052223 Dram Type= 6, Freq= 0, CH_0, rank 1
1277 13:30:31.055516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1278 13:30:31.055631 ==
1279 13:30:31.055751 RX Vref Scan: 0
1280 13:30:31.055880
1281 13:30:31.058819 RX Vref 0 -> 0, step: 1
1282 13:30:31.058907
1283 13:30:31.062073 RX Delay -130 -> 252, step: 16
1284 13:30:31.065662 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1285 13:30:31.069168 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1286 13:30:31.075378 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1287 13:30:31.078796 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1288 13:30:31.081626 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1289 13:30:31.085211 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1290 13:30:31.088408 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1291 13:30:31.095180 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1292 13:30:31.098253 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1293 13:30:31.101459 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1294 13:30:31.105062 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1295 13:30:31.111354 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1296 13:30:31.114904 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1297 13:30:31.118594 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1298 13:30:31.121235 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1299 13:30:31.124857 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1300 13:30:31.124964 ==
1301 13:30:31.128031 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 13:30:31.134580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 13:30:31.134713 ==
1304 13:30:31.134828 DQS Delay:
1305 13:30:31.137972 DQS0 = 0, DQS1 = 0
1306 13:30:31.138103 DQM Delay:
1307 13:30:31.141510 DQM0 = 86, DQM1 = 76
1308 13:30:31.141644 DQ Delay:
1309 13:30:31.144546 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1310 13:30:31.147932 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1311 13:30:31.151689 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1312 13:30:31.154732 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1313 13:30:31.154826
1314 13:30:31.154892
1315 13:30:31.154982 ==
1316 13:30:31.157836 Dram Type= 6, Freq= 0, CH_0, rank 1
1317 13:30:31.161380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1318 13:30:31.161460 ==
1319 13:30:31.161543
1320 13:30:31.161608
1321 13:30:31.164722 TX Vref Scan disable
1322 13:30:31.167870 == TX Byte 0 ==
1323 13:30:31.171220 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1324 13:30:31.174644 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1325 13:30:31.177763 == TX Byte 1 ==
1326 13:30:31.181095 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1327 13:30:31.184872 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1328 13:30:31.184980 ==
1329 13:30:31.187602 Dram Type= 6, Freq= 0, CH_0, rank 1
1330 13:30:31.191268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1331 13:30:31.194365 ==
1332 13:30:31.205886 TX Vref=22, minBit 0, minWin=27, winSum=439
1333 13:30:31.209042 TX Vref=24, minBit 1, minWin=27, winSum=444
1334 13:30:31.212594 TX Vref=26, minBit 1, minWin=27, winSum=446
1335 13:30:31.215632 TX Vref=28, minBit 2, minWin=27, winSum=450
1336 13:30:31.218702 TX Vref=30, minBit 0, minWin=28, winSum=453
1337 13:30:31.222498 TX Vref=32, minBit 4, minWin=27, winSum=451
1338 13:30:31.229326 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 30
1339 13:30:31.229423
1340 13:30:31.232331 Final TX Range 1 Vref 30
1341 13:30:31.232411
1342 13:30:31.232475 ==
1343 13:30:31.235875 Dram Type= 6, Freq= 0, CH_0, rank 1
1344 13:30:31.239004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1345 13:30:31.239113 ==
1346 13:30:31.241827
1347 13:30:31.241928
1348 13:30:31.242033 TX Vref Scan disable
1349 13:30:31.245829 == TX Byte 0 ==
1350 13:30:31.248817 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1351 13:30:31.255874 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1352 13:30:31.255979 == TX Byte 1 ==
1353 13:30:31.258900 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1354 13:30:31.265746 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1355 13:30:31.265835
1356 13:30:31.265902 [DATLAT]
1357 13:30:31.265963 Freq=800, CH0 RK1
1358 13:30:31.266023
1359 13:30:31.268717 DATLAT Default: 0xa
1360 13:30:31.268803 0, 0xFFFF, sum = 0
1361 13:30:31.272241 1, 0xFFFF, sum = 0
1362 13:30:31.272325 2, 0xFFFF, sum = 0
1363 13:30:31.275538 3, 0xFFFF, sum = 0
1364 13:30:31.278583 4, 0xFFFF, sum = 0
1365 13:30:31.278667 5, 0xFFFF, sum = 0
1366 13:30:31.282175 6, 0xFFFF, sum = 0
1367 13:30:31.282261 7, 0xFFFF, sum = 0
1368 13:30:31.285424 8, 0xFFFF, sum = 0
1369 13:30:31.285509 9, 0x0, sum = 1
1370 13:30:31.288618 10, 0x0, sum = 2
1371 13:30:31.288703 11, 0x0, sum = 3
1372 13:30:31.288770 12, 0x0, sum = 4
1373 13:30:31.291936 best_step = 10
1374 13:30:31.292019
1375 13:30:31.292084 ==
1376 13:30:31.295498 Dram Type= 6, Freq= 0, CH_0, rank 1
1377 13:30:31.298636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1378 13:30:31.298724 ==
1379 13:30:31.302107 RX Vref Scan: 0
1380 13:30:31.302191
1381 13:30:31.302256 RX Vref 0 -> 0, step: 1
1382 13:30:31.302318
1383 13:30:31.305254 RX Delay -95 -> 252, step: 8
1384 13:30:31.312581 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1385 13:30:31.315722 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1386 13:30:31.327237 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1387 13:30:31.327435 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1388 13:30:31.329029 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1389 13:30:31.332162 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1390 13:30:31.335451 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1391 13:30:31.338739 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1392 13:30:31.341863 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1393 13:30:31.345425 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1394 13:30:31.351804 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1395 13:30:31.355281 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1396 13:30:31.358778 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1397 13:30:31.361771 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1398 13:30:31.368429 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1399 13:30:31.372095 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1400 13:30:31.372180 ==
1401 13:30:31.375153 Dram Type= 6, Freq= 0, CH_0, rank 1
1402 13:30:31.378900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1403 13:30:31.378984 ==
1404 13:30:31.381822 DQS Delay:
1405 13:30:31.381901 DQS0 = 0, DQS1 = 0
1406 13:30:31.381966 DQM Delay:
1407 13:30:31.385267 DQM0 = 86, DQM1 = 77
1408 13:30:31.385366 DQ Delay:
1409 13:30:31.388618 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1410 13:30:31.391665 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1411 13:30:31.394961 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1412 13:30:31.398099 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =84
1413 13:30:31.398235
1414 13:30:31.398331
1415 13:30:31.408209 [DQSOSCAuto] RK1, (LSB)MR18= 0x231f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 401 ps
1416 13:30:31.408309 CH0 RK1: MR19=606, MR18=231F
1417 13:30:31.414879 CH0_RK1: MR19=0x606, MR18=0x231F, DQSOSC=401, MR23=63, INC=91, DEC=61
1418 13:30:31.417969 [RxdqsGatingPostProcess] freq 800
1419 13:30:31.424666 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1420 13:30:31.428537 Pre-setting of DQS Precalculation
1421 13:30:31.431626 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1422 13:30:31.431738 ==
1423 13:30:31.434566 Dram Type= 6, Freq= 0, CH_1, rank 0
1424 13:30:31.441348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1425 13:30:31.441466 ==
1426 13:30:31.444961 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1427 13:30:31.451538 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1428 13:30:31.460545 [CA 0] Center 37 (6~68) winsize 63
1429 13:30:31.463925 [CA 1] Center 37 (6~68) winsize 63
1430 13:30:31.467311 [CA 2] Center 35 (5~65) winsize 61
1431 13:30:31.470476 [CA 3] Center 34 (4~65) winsize 62
1432 13:30:31.474060 [CA 4] Center 34 (4~65) winsize 62
1433 13:30:31.477026 [CA 5] Center 33 (3~64) winsize 62
1434 13:30:31.477108
1435 13:30:31.480711 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1436 13:30:31.480793
1437 13:30:31.483899 [CATrainingPosCal] consider 1 rank data
1438 13:30:31.487582 u2DelayCellTimex100 = 270/100 ps
1439 13:30:31.490466 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1440 13:30:31.496993 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1441 13:30:31.500386 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1442 13:30:31.503852 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1443 13:30:31.507276 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1444 13:30:31.510577 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1445 13:30:31.510674
1446 13:30:31.513887 CA PerBit enable=1, Macro0, CA PI delay=33
1447 13:30:31.513979
1448 13:30:31.516902 [CBTSetCACLKResult] CA Dly = 33
1449 13:30:31.516981 CS Dly: 4 (0~35)
1450 13:30:31.520589 ==
1451 13:30:31.523778 Dram Type= 6, Freq= 0, CH_1, rank 1
1452 13:30:31.527302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1453 13:30:31.527400 ==
1454 13:30:31.530426 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1455 13:30:31.536645 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1456 13:30:31.547029 [CA 0] Center 36 (6~67) winsize 62
1457 13:30:31.549935 [CA 1] Center 36 (6~67) winsize 62
1458 13:30:31.553497 [CA 2] Center 34 (4~65) winsize 62
1459 13:30:31.556965 [CA 3] Center 34 (3~65) winsize 63
1460 13:30:31.560245 [CA 4] Center 34 (4~65) winsize 62
1461 13:30:31.563643 [CA 5] Center 33 (3~64) winsize 62
1462 13:30:31.563761
1463 13:30:31.566944 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1464 13:30:31.567052
1465 13:30:31.570276 [CATrainingPosCal] consider 2 rank data
1466 13:30:31.574553 u2DelayCellTimex100 = 270/100 ps
1467 13:30:31.578101 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1468 13:30:31.581658 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1469 13:30:31.585229 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1470 13:30:31.589008 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1471 13:30:31.592708 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1472 13:30:31.596219 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1473 13:30:31.596334
1474 13:30:31.599867 CA PerBit enable=1, Macro0, CA PI delay=33
1475 13:30:31.599976
1476 13:30:31.602945 [CBTSetCACLKResult] CA Dly = 33
1477 13:30:31.606296 CS Dly: 5 (0~37)
1478 13:30:31.606407
1479 13:30:31.609523 ----->DramcWriteLeveling(PI) begin...
1480 13:30:31.609631 ==
1481 13:30:31.613055 Dram Type= 6, Freq= 0, CH_1, rank 0
1482 13:30:31.616171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1483 13:30:31.616289 ==
1484 13:30:31.619614 Write leveling (Byte 0): 27 => 27
1485 13:30:31.623147 Write leveling (Byte 1): 28 => 28
1486 13:30:31.626373 DramcWriteLeveling(PI) end<-----
1487 13:30:31.626495
1488 13:30:31.626592 ==
1489 13:30:31.629525 Dram Type= 6, Freq= 0, CH_1, rank 0
1490 13:30:31.632919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1491 13:30:31.633034 ==
1492 13:30:31.636560 [Gating] SW mode calibration
1493 13:30:31.643120 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1494 13:30:31.649369 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1495 13:30:31.652985 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1496 13:30:31.656285 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1497 13:30:31.662695 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 13:30:31.666046 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 13:30:31.669009 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 13:30:31.675910 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 13:30:31.679414 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 13:30:31.682759 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 13:30:31.689616 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 13:30:31.692556 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 13:30:31.695669 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 13:30:31.702291 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 13:30:31.705948 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 13:30:31.709031 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 13:30:31.715373 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 13:30:31.718667 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 13:30:31.722237 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 13:30:31.729014 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1513 13:30:31.732035 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 13:30:31.735575 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 13:30:31.741617 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 13:30:31.745173 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 13:30:31.748871 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 13:30:31.754878 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 13:30:31.758537 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 13:30:31.761551 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 13:30:31.768512 0 9 8 | B1->B0 | 2f2f 3232 | 1 1 | (1 1) (1 1)
1522 13:30:31.772069 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1523 13:30:31.775008 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1524 13:30:31.781994 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1525 13:30:31.784945 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1526 13:30:31.788369 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1527 13:30:31.794906 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1528 13:30:31.798033 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
1529 13:30:31.801548 0 10 8 | B1->B0 | 2626 2323 | 1 0 | (1 0) (0 0)
1530 13:30:31.808253 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 13:30:31.811250 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 13:30:31.814815 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 13:30:31.821144 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 13:30:31.824667 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 13:30:31.827632 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 13:30:31.834422 0 11 4 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
1537 13:30:31.837676 0 11 8 | B1->B0 | 3e3e 4141 | 0 0 | (0 0) (0 0)
1538 13:30:31.841191 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1539 13:30:31.844220 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1540 13:30:31.851295 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1541 13:30:31.854520 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1542 13:30:31.857916 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1543 13:30:31.864747 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1544 13:30:31.867934 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1545 13:30:31.870951 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1546 13:30:31.877849 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 13:30:31.881399 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 13:30:31.884778 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 13:30:31.891183 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 13:30:31.894609 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 13:30:31.897633 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 13:30:31.904346 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 13:30:31.907817 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 13:30:31.911018 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 13:30:31.917505 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 13:30:31.921208 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 13:30:31.924713 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 13:30:31.931206 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 13:30:31.934214 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 13:30:31.937392 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 13:30:31.944006 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 13:30:31.944095 Total UI for P1: 0, mck2ui 16
1563 13:30:31.950652 best dqsien dly found for B0: ( 0, 14, 6)
1564 13:30:31.950738 Total UI for P1: 0, mck2ui 16
1565 13:30:31.953844 best dqsien dly found for B1: ( 0, 14, 6)
1566 13:30:31.960894 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1567 13:30:31.964192 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1568 13:30:31.964280
1569 13:30:31.967405 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1570 13:30:31.970487 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1571 13:30:31.973634 [Gating] SW calibration Done
1572 13:30:31.973762 ==
1573 13:30:31.977214 Dram Type= 6, Freq= 0, CH_1, rank 0
1574 13:30:31.980819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1575 13:30:31.980899 ==
1576 13:30:31.983690 RX Vref Scan: 0
1577 13:30:31.983796
1578 13:30:31.983914 RX Vref 0 -> 0, step: 1
1579 13:30:31.983986
1580 13:30:31.987090 RX Delay -130 -> 252, step: 16
1581 13:30:31.990607 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1582 13:30:31.996973 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1583 13:30:32.000511 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1584 13:30:32.003987 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1585 13:30:32.006954 iDelay=222, Bit 4, Center 77 (-34 ~ 189) 224
1586 13:30:32.010564 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1587 13:30:32.017139 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1588 13:30:32.020212 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1589 13:30:32.023878 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1590 13:30:32.026704 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1591 13:30:32.030169 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1592 13:30:32.036707 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1593 13:30:32.040328 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1594 13:30:32.043400 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1595 13:30:32.046954 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1596 13:30:32.050083 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1597 13:30:32.053105 ==
1598 13:30:32.056801 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 13:30:32.060344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 13:30:32.060439 ==
1601 13:30:32.060512 DQS Delay:
1602 13:30:32.063425 DQS0 = 0, DQS1 = 0
1603 13:30:32.063526 DQM Delay:
1604 13:30:32.066399 DQM0 = 85, DQM1 = 80
1605 13:30:32.066477 DQ Delay:
1606 13:30:32.070093 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1607 13:30:32.073072 DQ4 =77, DQ5 =101, DQ6 =93, DQ7 =85
1608 13:30:32.076363 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1609 13:30:32.080123 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1610 13:30:32.080234
1611 13:30:32.080328
1612 13:30:32.080436 ==
1613 13:30:32.083430 Dram Type= 6, Freq= 0, CH_1, rank 0
1614 13:30:32.086638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1615 13:30:32.086731 ==
1616 13:30:32.086799
1617 13:30:32.086864
1618 13:30:32.090026 TX Vref Scan disable
1619 13:30:32.093408 == TX Byte 0 ==
1620 13:30:32.096259 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1621 13:30:32.099629 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1622 13:30:32.103073 == TX Byte 1 ==
1623 13:30:32.106706 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1624 13:30:32.109563 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1625 13:30:32.109648 ==
1626 13:30:32.113362 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 13:30:32.119938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 13:30:32.120039 ==
1629 13:30:32.131216 TX Vref=22, minBit 1, minWin=27, winSum=443
1630 13:30:32.134493 TX Vref=24, minBit 2, minWin=27, winSum=445
1631 13:30:32.137818 TX Vref=26, minBit 2, minWin=27, winSum=452
1632 13:30:32.141421 TX Vref=28, minBit 5, minWin=27, winSum=455
1633 13:30:32.144521 TX Vref=30, minBit 0, minWin=27, winSum=455
1634 13:30:32.148106 TX Vref=32, minBit 0, minWin=27, winSum=450
1635 13:30:32.155072 [TxChooseVref] Worse bit 5, Min win 27, Win sum 455, Final Vref 28
1636 13:30:32.155177
1637 13:30:32.158208 Final TX Range 1 Vref 28
1638 13:30:32.158323
1639 13:30:32.158441 ==
1640 13:30:32.161250 Dram Type= 6, Freq= 0, CH_1, rank 0
1641 13:30:32.164952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1642 13:30:32.165134 ==
1643 13:30:32.165270
1644 13:30:32.165407
1645 13:30:32.168052 TX Vref Scan disable
1646 13:30:32.171805 == TX Byte 0 ==
1647 13:30:32.174642 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1648 13:30:32.178440 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1649 13:30:32.181354 == TX Byte 1 ==
1650 13:30:32.184425 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1651 13:30:32.187972 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1652 13:30:32.188099
1653 13:30:32.191250 [DATLAT]
1654 13:30:32.191370 Freq=800, CH1 RK0
1655 13:30:32.191474
1656 13:30:32.194555 DATLAT Default: 0xa
1657 13:30:32.194671 0, 0xFFFF, sum = 0
1658 13:30:32.197808 1, 0xFFFF, sum = 0
1659 13:30:32.197896 2, 0xFFFF, sum = 0
1660 13:30:32.201068 3, 0xFFFF, sum = 0
1661 13:30:32.201202 4, 0xFFFF, sum = 0
1662 13:30:32.204391 5, 0xFFFF, sum = 0
1663 13:30:32.204484 6, 0xFFFF, sum = 0
1664 13:30:32.207827 7, 0xFFFF, sum = 0
1665 13:30:32.210929 8, 0xFFFF, sum = 0
1666 13:30:32.211019 9, 0x0, sum = 1
1667 13:30:32.211109 10, 0x0, sum = 2
1668 13:30:32.214395 11, 0x0, sum = 3
1669 13:30:32.214511 12, 0x0, sum = 4
1670 13:30:32.217764 best_step = 10
1671 13:30:32.217908
1672 13:30:32.218026 ==
1673 13:30:32.221201 Dram Type= 6, Freq= 0, CH_1, rank 0
1674 13:30:32.224382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1675 13:30:32.224468 ==
1676 13:30:32.227542 RX Vref Scan: 1
1677 13:30:32.227653
1678 13:30:32.227749 Set Vref Range= 32 -> 127
1679 13:30:32.227839
1680 13:30:32.230977 RX Vref 32 -> 127, step: 1
1681 13:30:32.231061
1682 13:30:32.234700 RX Delay -95 -> 252, step: 8
1683 13:30:32.234785
1684 13:30:32.237632 Set Vref, RX VrefLevel [Byte0]: 32
1685 13:30:32.241001 [Byte1]: 32
1686 13:30:32.241120
1687 13:30:32.244441 Set Vref, RX VrefLevel [Byte0]: 33
1688 13:30:32.247802 [Byte1]: 33
1689 13:30:32.251474
1690 13:30:32.251604 Set Vref, RX VrefLevel [Byte0]: 34
1691 13:30:32.254489 [Byte1]: 34
1692 13:30:32.258886
1693 13:30:32.259007 Set Vref, RX VrefLevel [Byte0]: 35
1694 13:30:32.262479 [Byte1]: 35
1695 13:30:32.266766
1696 13:30:32.266899 Set Vref, RX VrefLevel [Byte0]: 36
1697 13:30:32.269813 [Byte1]: 36
1698 13:30:32.274199
1699 13:30:32.274328 Set Vref, RX VrefLevel [Byte0]: 37
1700 13:30:32.277397 [Byte1]: 37
1701 13:30:32.281597
1702 13:30:32.281683 Set Vref, RX VrefLevel [Byte0]: 38
1703 13:30:32.285222 [Byte1]: 38
1704 13:30:32.289695
1705 13:30:32.289776 Set Vref, RX VrefLevel [Byte0]: 39
1706 13:30:32.292624 [Byte1]: 39
1707 13:30:32.296714
1708 13:30:32.296800 Set Vref, RX VrefLevel [Byte0]: 40
1709 13:30:32.300156 [Byte1]: 40
1710 13:30:32.304986
1711 13:30:32.305094 Set Vref, RX VrefLevel [Byte0]: 41
1712 13:30:32.308111 [Byte1]: 41
1713 13:30:32.312157
1714 13:30:32.312260 Set Vref, RX VrefLevel [Byte0]: 42
1715 13:30:32.315226 [Byte1]: 42
1716 13:30:32.319499
1717 13:30:32.319611 Set Vref, RX VrefLevel [Byte0]: 43
1718 13:30:32.322754 [Byte1]: 43
1719 13:30:32.327608
1720 13:30:32.327730 Set Vref, RX VrefLevel [Byte0]: 44
1721 13:30:32.330518 [Byte1]: 44
1722 13:30:32.334906
1723 13:30:32.335042 Set Vref, RX VrefLevel [Byte0]: 45
1724 13:30:32.338519 [Byte1]: 45
1725 13:30:32.342635
1726 13:30:32.342772 Set Vref, RX VrefLevel [Byte0]: 46
1727 13:30:32.345815 [Byte1]: 46
1728 13:30:32.350382
1729 13:30:32.350475 Set Vref, RX VrefLevel [Byte0]: 47
1730 13:30:32.353615 [Byte1]: 47
1731 13:30:32.358039
1732 13:30:32.358163 Set Vref, RX VrefLevel [Byte0]: 48
1733 13:30:32.361073 [Byte1]: 48
1734 13:30:32.365440
1735 13:30:32.365565 Set Vref, RX VrefLevel [Byte0]: 49
1736 13:30:32.368486 [Byte1]: 49
1737 13:30:32.373345
1738 13:30:32.373465 Set Vref, RX VrefLevel [Byte0]: 50
1739 13:30:32.376445 [Byte1]: 50
1740 13:30:32.380758
1741 13:30:32.380860 Set Vref, RX VrefLevel [Byte0]: 51
1742 13:30:32.383806 [Byte1]: 51
1743 13:30:32.388090
1744 13:30:32.388192 Set Vref, RX VrefLevel [Byte0]: 52
1745 13:30:32.391806 [Byte1]: 52
1746 13:30:32.396033
1747 13:30:32.396147 Set Vref, RX VrefLevel [Byte0]: 53
1748 13:30:32.398926 [Byte1]: 53
1749 13:30:32.403634
1750 13:30:32.403765 Set Vref, RX VrefLevel [Byte0]: 54
1751 13:30:32.406448 [Byte1]: 54
1752 13:30:32.411275
1753 13:30:32.411382 Set Vref, RX VrefLevel [Byte0]: 55
1754 13:30:32.414476 [Byte1]: 55
1755 13:30:32.418558
1756 13:30:32.418675 Set Vref, RX VrefLevel [Byte0]: 56
1757 13:30:32.422099 [Byte1]: 56
1758 13:30:32.426019
1759 13:30:32.426109 Set Vref, RX VrefLevel [Byte0]: 57
1760 13:30:32.429621 [Byte1]: 57
1761 13:30:32.433534
1762 13:30:32.433632 Set Vref, RX VrefLevel [Byte0]: 58
1763 13:30:32.437077 [Byte1]: 58
1764 13:30:32.441132
1765 13:30:32.441231 Set Vref, RX VrefLevel [Byte0]: 59
1766 13:30:32.444779 [Byte1]: 59
1767 13:30:32.449201
1768 13:30:32.449327 Set Vref, RX VrefLevel [Byte0]: 60
1769 13:30:32.452224 [Byte1]: 60
1770 13:30:32.456435
1771 13:30:32.456534 Set Vref, RX VrefLevel [Byte0]: 61
1772 13:30:32.460159 [Byte1]: 61
1773 13:30:32.463957
1774 13:30:32.464045 Set Vref, RX VrefLevel [Byte0]: 62
1775 13:30:32.467173 [Byte1]: 62
1776 13:30:32.471690
1777 13:30:32.471846 Set Vref, RX VrefLevel [Byte0]: 63
1778 13:30:32.475378 [Byte1]: 63
1779 13:30:32.479749
1780 13:30:32.479874 Set Vref, RX VrefLevel [Byte0]: 64
1781 13:30:32.482655 [Byte1]: 64
1782 13:30:32.486846
1783 13:30:32.486957 Set Vref, RX VrefLevel [Byte0]: 65
1784 13:30:32.489988 [Byte1]: 65
1785 13:30:32.494389
1786 13:30:32.494481 Set Vref, RX VrefLevel [Byte0]: 66
1787 13:30:32.498014 [Byte1]: 66
1788 13:30:32.502378
1789 13:30:32.502501 Set Vref, RX VrefLevel [Byte0]: 67
1790 13:30:32.505796 [Byte1]: 67
1791 13:30:32.509617
1792 13:30:32.509709 Set Vref, RX VrefLevel [Byte0]: 68
1793 13:30:32.513244 [Byte1]: 68
1794 13:30:32.517054
1795 13:30:32.517141 Set Vref, RX VrefLevel [Byte0]: 69
1796 13:30:32.520572 [Byte1]: 69
1797 13:30:32.524703
1798 13:30:32.524811 Set Vref, RX VrefLevel [Byte0]: 70
1799 13:30:32.528346 [Byte1]: 70
1800 13:30:32.532539
1801 13:30:32.532641 Set Vref, RX VrefLevel [Byte0]: 71
1802 13:30:32.535609 [Byte1]: 71
1803 13:30:32.540131
1804 13:30:32.540263 Set Vref, RX VrefLevel [Byte0]: 72
1805 13:30:32.543515 [Byte1]: 72
1806 13:30:32.547614
1807 13:30:32.547740 Set Vref, RX VrefLevel [Byte0]: 73
1808 13:30:32.551233 [Byte1]: 73
1809 13:30:32.555094
1810 13:30:32.555216 Set Vref, RX VrefLevel [Byte0]: 74
1811 13:30:32.558454 [Byte1]: 74
1812 13:30:32.562654
1813 13:30:32.562748 Final RX Vref Byte 0 = 60 to rank0
1814 13:30:32.566418 Final RX Vref Byte 1 = 58 to rank0
1815 13:30:32.569457 Final RX Vref Byte 0 = 60 to rank1
1816 13:30:32.572925 Final RX Vref Byte 1 = 58 to rank1==
1817 13:30:32.575842 Dram Type= 6, Freq= 0, CH_1, rank 0
1818 13:30:32.582395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1819 13:30:32.582490 ==
1820 13:30:32.582556 DQS Delay:
1821 13:30:32.585926 DQS0 = 0, DQS1 = 0
1822 13:30:32.586035 DQM Delay:
1823 13:30:32.586128 DQM0 = 86, DQM1 = 81
1824 13:30:32.589030 DQ Delay:
1825 13:30:32.592722 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1826 13:30:32.595799 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
1827 13:30:32.599521 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
1828 13:30:32.602644 DQ12 =88, DQ13 =92, DQ14 =88, DQ15 =88
1829 13:30:32.602746
1830 13:30:32.602838
1831 13:30:32.609212 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a2d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
1832 13:30:32.612825 CH1 RK0: MR19=606, MR18=1A2D
1833 13:30:32.619276 CH1_RK0: MR19=0x606, MR18=0x1A2D, DQSOSC=398, MR23=63, INC=93, DEC=62
1834 13:30:32.619386
1835 13:30:32.622486 ----->DramcWriteLeveling(PI) begin...
1836 13:30:32.622592 ==
1837 13:30:32.626015 Dram Type= 6, Freq= 0, CH_1, rank 1
1838 13:30:32.628859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1839 13:30:32.628956 ==
1840 13:30:32.632628 Write leveling (Byte 0): 26 => 26
1841 13:30:32.635461 Write leveling (Byte 1): 27 => 27
1842 13:30:32.639078 DramcWriteLeveling(PI) end<-----
1843 13:30:32.639158
1844 13:30:32.639231 ==
1845 13:30:32.642073 Dram Type= 6, Freq= 0, CH_1, rank 1
1846 13:30:32.645449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1847 13:30:32.645535 ==
1848 13:30:32.648806 [Gating] SW mode calibration
1849 13:30:32.655698 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1850 13:30:32.662146 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1851 13:30:32.665622 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1852 13:30:32.672033 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1853 13:30:32.675758 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 13:30:32.678815 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 13:30:32.685340 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 13:30:32.689576 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 13:30:32.691933 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 13:30:32.698680 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 13:30:32.701689 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 13:30:32.705363 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 13:30:32.711926 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 13:30:32.714831 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 13:30:32.718102 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 13:30:32.721771 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 13:30:32.728596 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 13:30:32.731405 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 13:30:32.734922 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1868 13:30:32.741567 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1869 13:30:32.744707 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 13:30:32.748320 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 13:30:32.754648 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 13:30:32.758005 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 13:30:32.761495 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 13:30:32.768082 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 13:30:32.771207 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1876 13:30:32.774539 0 9 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1877 13:30:32.781278 0 9 8 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
1878 13:30:32.784411 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1879 13:30:32.787987 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1880 13:30:32.794578 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1881 13:30:32.798184 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1882 13:30:32.800962 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1883 13:30:32.807946 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1884 13:30:32.811025 0 10 4 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (1 0)
1885 13:30:32.814595 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
1886 13:30:32.820952 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 13:30:32.824550 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 13:30:32.828079 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 13:30:32.834602 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 13:30:32.837504 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 13:30:32.841220 0 11 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1892 13:30:32.847703 0 11 4 | B1->B0 | 2424 3f3f | 0 1 | (0 0) (0 0)
1893 13:30:32.850652 0 11 8 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
1894 13:30:32.854254 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1895 13:30:32.860830 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1896 13:30:32.864238 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1897 13:30:32.867530 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1898 13:30:32.874344 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1899 13:30:32.877351 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1900 13:30:32.880620 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1901 13:30:32.887489 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1902 13:30:32.891045 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 13:30:32.894100 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 13:30:32.900742 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 13:30:32.903817 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 13:30:32.907387 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 13:30:32.913781 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 13:30:32.916958 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 13:30:32.920673 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 13:30:32.927036 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 13:30:32.930507 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 13:30:32.933489 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 13:30:32.937239 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 13:30:32.943720 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 13:30:32.946968 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 13:30:32.950190 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1917 13:30:32.953739 Total UI for P1: 0, mck2ui 16
1918 13:30:32.956760 best dqsien dly found for B0: ( 0, 14, 2)
1919 13:30:32.963453 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 13:30:32.967067 Total UI for P1: 0, mck2ui 16
1921 13:30:32.970053 best dqsien dly found for B1: ( 0, 14, 4)
1922 13:30:32.973419 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1923 13:30:32.976345 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1924 13:30:32.976444
1925 13:30:32.979685 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1926 13:30:32.982961 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1927 13:30:32.986467 [Gating] SW calibration Done
1928 13:30:32.986582 ==
1929 13:30:32.989856 Dram Type= 6, Freq= 0, CH_1, rank 1
1930 13:30:32.992974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1931 13:30:32.993057 ==
1932 13:30:32.996640 RX Vref Scan: 0
1933 13:30:32.996768
1934 13:30:32.999629 RX Vref 0 -> 0, step: 1
1935 13:30:32.999714
1936 13:30:32.999777 RX Delay -130 -> 252, step: 16
1937 13:30:33.006470 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1938 13:30:33.009444 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1939 13:30:33.013139 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1940 13:30:33.016190 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1941 13:30:33.019390 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1942 13:30:33.025790 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1943 13:30:33.029143 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1944 13:30:33.032683 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1945 13:30:33.036103 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1946 13:30:33.039021 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1947 13:30:33.045835 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1948 13:30:33.049269 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1949 13:30:33.052274 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1950 13:30:33.055952 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1951 13:30:33.062637 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1952 13:30:33.065681 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1953 13:30:33.065786 ==
1954 13:30:33.069445 Dram Type= 6, Freq= 0, CH_1, rank 1
1955 13:30:33.072553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1956 13:30:33.072661 ==
1957 13:30:33.075988 DQS Delay:
1958 13:30:33.076079 DQS0 = 0, DQS1 = 0
1959 13:30:33.076152 DQM Delay:
1960 13:30:33.078939 DQM0 = 83, DQM1 = 80
1961 13:30:33.079018 DQ Delay:
1962 13:30:33.082622 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =77
1963 13:30:33.086013 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =85
1964 13:30:33.089417 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1965 13:30:33.092268 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1966 13:30:33.092386
1967 13:30:33.092453
1968 13:30:33.092535 ==
1969 13:30:33.095697 Dram Type= 6, Freq= 0, CH_1, rank 1
1970 13:30:33.102392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1971 13:30:33.102506 ==
1972 13:30:33.102576
1973 13:30:33.102637
1974 13:30:33.102696 TX Vref Scan disable
1975 13:30:33.105921 == TX Byte 0 ==
1976 13:30:33.109068 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1977 13:30:33.115846 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1978 13:30:33.115974 == TX Byte 1 ==
1979 13:30:33.118961 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1980 13:30:33.125539 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1981 13:30:33.125666 ==
1982 13:30:33.128618 Dram Type= 6, Freq= 0, CH_1, rank 1
1983 13:30:33.132265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1984 13:30:33.132376 ==
1985 13:30:33.144363 TX Vref=22, minBit 1, minWin=27, winSum=447
1986 13:30:33.148075 TX Vref=24, minBit 0, minWin=27, winSum=450
1987 13:30:33.151298 TX Vref=26, minBit 3, minWin=27, winSum=452
1988 13:30:33.154827 TX Vref=28, minBit 6, minWin=27, winSum=454
1989 13:30:33.157968 TX Vref=30, minBit 2, minWin=27, winSum=454
1990 13:30:33.161475 TX Vref=32, minBit 4, minWin=27, winSum=455
1991 13:30:33.168380 [TxChooseVref] Worse bit 4, Min win 27, Win sum 455, Final Vref 32
1992 13:30:33.168490
1993 13:30:33.171255 Final TX Range 1 Vref 32
1994 13:30:33.171334
1995 13:30:33.171406 ==
1996 13:30:33.174972 Dram Type= 6, Freq= 0, CH_1, rank 1
1997 13:30:33.177995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1998 13:30:33.178110 ==
1999 13:30:33.180822
2000 13:30:33.180903
2001 13:30:33.180972 TX Vref Scan disable
2002 13:30:33.184623 == TX Byte 0 ==
2003 13:30:33.187982 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2004 13:30:33.194284 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2005 13:30:33.194405 == TX Byte 1 ==
2006 13:30:33.197473 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2007 13:30:33.204409 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2008 13:30:33.204519
2009 13:30:33.204587 [DATLAT]
2010 13:30:33.204649 Freq=800, CH1 RK1
2011 13:30:33.204720
2012 13:30:33.208117 DATLAT Default: 0xa
2013 13:30:33.208206 0, 0xFFFF, sum = 0
2014 13:30:33.210993 1, 0xFFFF, sum = 0
2015 13:30:33.211076 2, 0xFFFF, sum = 0
2016 13:30:33.214823 3, 0xFFFF, sum = 0
2017 13:30:33.217856 4, 0xFFFF, sum = 0
2018 13:30:33.217949 5, 0xFFFF, sum = 0
2019 13:30:33.220882 6, 0xFFFF, sum = 0
2020 13:30:33.220960 7, 0xFFFF, sum = 0
2021 13:30:33.224578 8, 0xFFFF, sum = 0
2022 13:30:33.224658 9, 0x0, sum = 1
2023 13:30:33.224722 10, 0x0, sum = 2
2024 13:30:33.227706 11, 0x0, sum = 3
2025 13:30:33.227817 12, 0x0, sum = 4
2026 13:30:33.231405 best_step = 10
2027 13:30:33.231503
2028 13:30:33.231616 ==
2029 13:30:33.234397 Dram Type= 6, Freq= 0, CH_1, rank 1
2030 13:30:33.237918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2031 13:30:33.238039 ==
2032 13:30:33.241218 RX Vref Scan: 0
2033 13:30:33.241339
2034 13:30:33.241448 RX Vref 0 -> 0, step: 1
2035 13:30:33.244066
2036 13:30:33.244182 RX Delay -95 -> 252, step: 8
2037 13:30:33.251212 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2038 13:30:33.254804 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2039 13:30:33.257896 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2040 13:30:33.261364 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
2041 13:30:33.264843 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2042 13:30:33.270920 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2043 13:30:33.274540 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2044 13:30:33.277576 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2045 13:30:33.281238 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2046 13:30:33.284564 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2047 13:30:33.291173 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
2048 13:30:33.294081 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
2049 13:30:33.297756 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2050 13:30:33.300715 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2051 13:30:33.307178 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2052 13:30:33.310733 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2053 13:30:33.310872 ==
2054 13:30:33.314172 Dram Type= 6, Freq= 0, CH_1, rank 1
2055 13:30:33.317396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2056 13:30:33.317516 ==
2057 13:30:33.320403 DQS Delay:
2058 13:30:33.320486 DQS0 = 0, DQS1 = 0
2059 13:30:33.320553 DQM Delay:
2060 13:30:33.324056 DQM0 = 86, DQM1 = 81
2061 13:30:33.324134 DQ Delay:
2062 13:30:33.327045 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =80
2063 13:30:33.330830 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
2064 13:30:33.333896 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =72
2065 13:30:33.336989 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2066 13:30:33.337133
2067 13:30:33.337248
2068 13:30:33.347352 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e3a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
2069 13:30:33.347506 CH1 RK1: MR19=606, MR18=1E3A
2070 13:30:33.353786 CH1_RK1: MR19=0x606, MR18=0x1E3A, DQSOSC=395, MR23=63, INC=94, DEC=63
2071 13:30:33.356993 [RxdqsGatingPostProcess] freq 800
2072 13:30:33.363589 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2073 13:30:33.367167 Pre-setting of DQS Precalculation
2074 13:30:33.369899 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2075 13:30:33.380194 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2076 13:30:33.386638 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2077 13:30:33.386794
2078 13:30:33.386900
2079 13:30:33.389879 [Calibration Summary] 1600 Mbps
2080 13:30:33.389993 CH 0, Rank 0
2081 13:30:33.393471 SW Impedance : PASS
2082 13:30:33.393597 DUTY Scan : NO K
2083 13:30:33.396426 ZQ Calibration : PASS
2084 13:30:33.399840 Jitter Meter : NO K
2085 13:30:33.399962 CBT Training : PASS
2086 13:30:33.403396 Write leveling : PASS
2087 13:30:33.406781 RX DQS gating : PASS
2088 13:30:33.406875 RX DQ/DQS(RDDQC) : PASS
2089 13:30:33.409643 TX DQ/DQS : PASS
2090 13:30:33.413039 RX DATLAT : PASS
2091 13:30:33.413158 RX DQ/DQS(Engine): PASS
2092 13:30:33.416680 TX OE : NO K
2093 13:30:33.416787 All Pass.
2094 13:30:33.416892
2095 13:30:33.419564 CH 0, Rank 1
2096 13:30:33.419670 SW Impedance : PASS
2097 13:30:33.423315 DUTY Scan : NO K
2098 13:30:33.426266 ZQ Calibration : PASS
2099 13:30:33.426393 Jitter Meter : NO K
2100 13:30:33.429395 CBT Training : PASS
2101 13:30:33.433040 Write leveling : PASS
2102 13:30:33.433164 RX DQS gating : PASS
2103 13:30:33.436282 RX DQ/DQS(RDDQC) : PASS
2104 13:30:33.436368 TX DQ/DQS : PASS
2105 13:30:33.439710 RX DATLAT : PASS
2106 13:30:33.442752 RX DQ/DQS(Engine): PASS
2107 13:30:33.442867 TX OE : NO K
2108 13:30:33.446422 All Pass.
2109 13:30:33.446532
2110 13:30:33.446639 CH 1, Rank 0
2111 13:30:33.449419 SW Impedance : PASS
2112 13:30:33.449537 DUTY Scan : NO K
2113 13:30:33.452567 ZQ Calibration : PASS
2114 13:30:33.456090 Jitter Meter : NO K
2115 13:30:33.456178 CBT Training : PASS
2116 13:30:33.459434 Write leveling : PASS
2117 13:30:33.462490 RX DQS gating : PASS
2118 13:30:33.462574 RX DQ/DQS(RDDQC) : PASS
2119 13:30:33.466191 TX DQ/DQS : PASS
2120 13:30:33.469088 RX DATLAT : PASS
2121 13:30:33.469196 RX DQ/DQS(Engine): PASS
2122 13:30:33.472540 TX OE : NO K
2123 13:30:33.472654 All Pass.
2124 13:30:33.472760
2125 13:30:33.476061 CH 1, Rank 1
2126 13:30:33.476172 SW Impedance : PASS
2127 13:30:33.479574 DUTY Scan : NO K
2128 13:30:33.482462 ZQ Calibration : PASS
2129 13:30:33.482577 Jitter Meter : NO K
2130 13:30:33.486138 CBT Training : PASS
2131 13:30:33.486262 Write leveling : PASS
2132 13:30:33.489771 RX DQS gating : PASS
2133 13:30:33.492798 RX DQ/DQS(RDDQC) : PASS
2134 13:30:33.492882 TX DQ/DQS : PASS
2135 13:30:33.495725 RX DATLAT : PASS
2136 13:30:33.499163 RX DQ/DQS(Engine): PASS
2137 13:30:33.499245 TX OE : NO K
2138 13:30:33.502449 All Pass.
2139 13:30:33.502569
2140 13:30:33.502677 DramC Write-DBI off
2141 13:30:33.505649 PER_BANK_REFRESH: Hybrid Mode
2142 13:30:33.509358 TX_TRACKING: ON
2143 13:30:33.512432 [GetDramInforAfterCalByMRR] Vendor 6.
2144 13:30:33.515941 [GetDramInforAfterCalByMRR] Revision 606.
2145 13:30:33.519146 [GetDramInforAfterCalByMRR] Revision 2 0.
2146 13:30:33.519246 MR0 0x3b3b
2147 13:30:33.519316 MR8 0x5151
2148 13:30:33.522451 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2149 13:30:33.525605
2150 13:30:33.525736 MR0 0x3b3b
2151 13:30:33.525838 MR8 0x5151
2152 13:30:33.528963 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2153 13:30:33.529069
2154 13:30:33.539222 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2155 13:30:33.542386 [FAST_K] Save calibration result to emmc
2156 13:30:33.545418 [FAST_K] Save calibration result to emmc
2157 13:30:33.548888 dram_init: config_dvfs: 1
2158 13:30:33.551965 dramc_set_vcore_voltage set vcore to 662500
2159 13:30:33.555229 Read voltage for 1200, 2
2160 13:30:33.555310 Vio18 = 0
2161 13:30:33.555375 Vcore = 662500
2162 13:30:33.558811 Vdram = 0
2163 13:30:33.558889 Vddq = 0
2164 13:30:33.558952 Vmddr = 0
2165 13:30:33.565370 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2166 13:30:33.568417 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2167 13:30:33.572138 MEM_TYPE=3, freq_sel=15
2168 13:30:33.575052 sv_algorithm_assistance_LP4_1600
2169 13:30:33.578449 ============ PULL DRAM RESETB DOWN ============
2170 13:30:33.584917 ========== PULL DRAM RESETB DOWN end =========
2171 13:30:33.588280 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2172 13:30:33.591492 ===================================
2173 13:30:33.595027 LPDDR4 DRAM CONFIGURATION
2174 13:30:33.598325 ===================================
2175 13:30:33.598430 EX_ROW_EN[0] = 0x0
2176 13:30:33.601896 EX_ROW_EN[1] = 0x0
2177 13:30:33.601980 LP4Y_EN = 0x0
2178 13:30:33.604783 WORK_FSP = 0x0
2179 13:30:33.604861 WL = 0x4
2180 13:30:33.608371 RL = 0x4
2181 13:30:33.608463 BL = 0x2
2182 13:30:33.611692 RPST = 0x0
2183 13:30:33.611773 RD_PRE = 0x0
2184 13:30:33.614956 WR_PRE = 0x1
2185 13:30:33.618422 WR_PST = 0x0
2186 13:30:33.618533 DBI_WR = 0x0
2187 13:30:33.621748 DBI_RD = 0x0
2188 13:30:33.621838 OTF = 0x1
2189 13:30:33.625214 ===================================
2190 13:30:33.628091 ===================================
2191 13:30:33.628172 ANA top config
2192 13:30:33.631362 ===================================
2193 13:30:33.635148 DLL_ASYNC_EN = 0
2194 13:30:33.638426 ALL_SLAVE_EN = 0
2195 13:30:33.641316 NEW_RANK_MODE = 1
2196 13:30:33.644653 DLL_IDLE_MODE = 1
2197 13:30:33.644762 LP45_APHY_COMB_EN = 1
2198 13:30:33.648179 TX_ODT_DIS = 1
2199 13:30:33.651108 NEW_8X_MODE = 1
2200 13:30:33.654828 ===================================
2201 13:30:33.657879 ===================================
2202 13:30:33.661561 data_rate = 2400
2203 13:30:33.664465 CKR = 1
2204 13:30:33.664566 DQ_P2S_RATIO = 8
2205 13:30:33.668013 ===================================
2206 13:30:33.671598 CA_P2S_RATIO = 8
2207 13:30:33.674706 DQ_CA_OPEN = 0
2208 13:30:33.678247 DQ_SEMI_OPEN = 0
2209 13:30:33.681254 CA_SEMI_OPEN = 0
2210 13:30:33.684660 CA_FULL_RATE = 0
2211 13:30:33.684773 DQ_CKDIV4_EN = 0
2212 13:30:33.688068 CA_CKDIV4_EN = 0
2213 13:30:33.691457 CA_PREDIV_EN = 0
2214 13:30:33.694506 PH8_DLY = 17
2215 13:30:33.698062 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2216 13:30:33.701113 DQ_AAMCK_DIV = 4
2217 13:30:33.701199 CA_AAMCK_DIV = 4
2218 13:30:33.704825 CA_ADMCK_DIV = 4
2219 13:30:33.707759 DQ_TRACK_CA_EN = 0
2220 13:30:33.711356 CA_PICK = 1200
2221 13:30:33.714468 CA_MCKIO = 1200
2222 13:30:33.717880 MCKIO_SEMI = 0
2223 13:30:33.720990 PLL_FREQ = 2366
2224 13:30:33.724367 DQ_UI_PI_RATIO = 32
2225 13:30:33.724468 CA_UI_PI_RATIO = 0
2226 13:30:33.727858 ===================================
2227 13:30:33.731269 ===================================
2228 13:30:33.734153 memory_type:LPDDR4
2229 13:30:33.737649 GP_NUM : 10
2230 13:30:33.737767 SRAM_EN : 1
2231 13:30:33.741144 MD32_EN : 0
2232 13:30:33.743893 ===================================
2233 13:30:33.747776 [ANA_INIT] >>>>>>>>>>>>>>
2234 13:30:33.751171 <<<<<< [CONFIGURE PHASE]: ANA_TX
2235 13:30:33.754110 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2236 13:30:33.757264 ===================================
2237 13:30:33.757389 data_rate = 2400,PCW = 0X5b00
2238 13:30:33.760797 ===================================
2239 13:30:33.763816 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2240 13:30:33.770950 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2241 13:30:33.777695 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2242 13:30:33.780841 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2243 13:30:33.784305 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2244 13:30:33.787261 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2245 13:30:33.790760 [ANA_INIT] flow start
2246 13:30:33.790883 [ANA_INIT] PLL >>>>>>>>
2247 13:30:33.794106 [ANA_INIT] PLL <<<<<<<<
2248 13:30:33.797485 [ANA_INIT] MIDPI >>>>>>>>
2249 13:30:33.800556 [ANA_INIT] MIDPI <<<<<<<<
2250 13:30:33.800689 [ANA_INIT] DLL >>>>>>>>
2251 13:30:33.804043 [ANA_INIT] DLL <<<<<<<<
2252 13:30:33.807096 [ANA_INIT] flow end
2253 13:30:33.810726 ============ LP4 DIFF to SE enter ============
2254 13:30:33.813854 ============ LP4 DIFF to SE exit ============
2255 13:30:33.817376 [ANA_INIT] <<<<<<<<<<<<<
2256 13:30:33.820348 [Flow] Enable top DCM control >>>>>
2257 13:30:33.823812 [Flow] Enable top DCM control <<<<<
2258 13:30:33.827508 Enable DLL master slave shuffle
2259 13:30:33.830542 ==============================================================
2260 13:30:33.834177 Gating Mode config
2261 13:30:33.837305 ==============================================================
2262 13:30:33.840478 Config description:
2263 13:30:33.850141 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2264 13:30:33.857096 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2265 13:30:33.860096 SELPH_MODE 0: By rank 1: By Phase
2266 13:30:33.866859 ==============================================================
2267 13:30:33.870058 GAT_TRACK_EN = 1
2268 13:30:33.873497 RX_GATING_MODE = 2
2269 13:30:33.877087 RX_GATING_TRACK_MODE = 2
2270 13:30:33.880010 SELPH_MODE = 1
2271 13:30:33.883765 PICG_EARLY_EN = 1
2272 13:30:33.886840 VALID_LAT_VALUE = 1
2273 13:30:33.889897 ==============================================================
2274 13:30:33.893571 Enter into Gating configuration >>>>
2275 13:30:33.897016 Exit from Gating configuration <<<<
2276 13:30:33.899935 Enter into DVFS_PRE_config >>>>>
2277 13:30:33.910086 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2278 13:30:33.913629 Exit from DVFS_PRE_config <<<<<
2279 13:30:33.916811 Enter into PICG configuration >>>>
2280 13:30:33.919721 Exit from PICG configuration <<<<
2281 13:30:33.923452 [RX_INPUT] configuration >>>>>
2282 13:30:33.926776 [RX_INPUT] configuration <<<<<
2283 13:30:33.933001 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2284 13:30:33.936657 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2285 13:30:33.943073 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2286 13:30:33.949559 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2287 13:30:33.956307 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2288 13:30:33.963170 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2289 13:30:33.965978 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2290 13:30:33.969509 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2291 13:30:33.972921 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2292 13:30:33.979753 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2293 13:30:33.982897 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2294 13:30:33.986499 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2295 13:30:33.989618 ===================================
2296 13:30:33.992695 LPDDR4 DRAM CONFIGURATION
2297 13:30:33.996221 ===================================
2298 13:30:33.996338 EX_ROW_EN[0] = 0x0
2299 13:30:33.999767 EX_ROW_EN[1] = 0x0
2300 13:30:34.002699 LP4Y_EN = 0x0
2301 13:30:34.002815 WORK_FSP = 0x0
2302 13:30:34.005855 WL = 0x4
2303 13:30:34.005963 RL = 0x4
2304 13:30:34.009728 BL = 0x2
2305 13:30:34.009847 RPST = 0x0
2306 13:30:34.012647 RD_PRE = 0x0
2307 13:30:34.012763 WR_PRE = 0x1
2308 13:30:34.016394 WR_PST = 0x0
2309 13:30:34.016509 DBI_WR = 0x0
2310 13:30:34.019462 DBI_RD = 0x0
2311 13:30:34.019566 OTF = 0x1
2312 13:30:34.022533 ===================================
2313 13:30:34.026079 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2314 13:30:34.032480 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2315 13:30:34.035543 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2316 13:30:34.039261 ===================================
2317 13:30:34.042403 LPDDR4 DRAM CONFIGURATION
2318 13:30:34.046020 ===================================
2319 13:30:34.046157 EX_ROW_EN[0] = 0x10
2320 13:30:34.048877 EX_ROW_EN[1] = 0x0
2321 13:30:34.052238 LP4Y_EN = 0x0
2322 13:30:34.052351 WORK_FSP = 0x0
2323 13:30:34.055713 WL = 0x4
2324 13:30:34.055821 RL = 0x4
2325 13:30:34.059087 BL = 0x2
2326 13:30:34.059203 RPST = 0x0
2327 13:30:34.062765 RD_PRE = 0x0
2328 13:30:34.062885 WR_PRE = 0x1
2329 13:30:34.065746 WR_PST = 0x0
2330 13:30:34.065854 DBI_WR = 0x0
2331 13:30:34.069251 DBI_RD = 0x0
2332 13:30:34.069350 OTF = 0x1
2333 13:30:34.072575 ===================================
2334 13:30:34.079016 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2335 13:30:34.079153 ==
2336 13:30:34.082451 Dram Type= 6, Freq= 0, CH_0, rank 0
2337 13:30:34.085608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2338 13:30:34.085720 ==
2339 13:30:34.089175 [Duty_Offset_Calibration]
2340 13:30:34.092189 B0:2 B1:0 CA:4
2341 13:30:34.092307
2342 13:30:34.095841 [DutyScan_Calibration_Flow] k_type=0
2343 13:30:34.103174
2344 13:30:34.103315 ==CLK 0==
2345 13:30:34.106033 Final CLK duty delay cell = -4
2346 13:30:34.109611 [-4] MAX Duty = 5031%(X100), DQS PI = 18
2347 13:30:34.113105 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2348 13:30:34.116352 [-4] AVG Duty = 4937%(X100)
2349 13:30:34.116471
2350 13:30:34.119385 CH0 CLK Duty spec in!! Max-Min= 187%
2351 13:30:34.123061 [DutyScan_Calibration_Flow] ====Done====
2352 13:30:34.123179
2353 13:30:34.125836 [DutyScan_Calibration_Flow] k_type=1
2354 13:30:34.141692
2355 13:30:34.141926 ==DQS 0 ==
2356 13:30:34.145368 Final DQS duty delay cell = -4
2357 13:30:34.148351 [-4] MAX Duty = 4969%(X100), DQS PI = 14
2358 13:30:34.151992 [-4] MIN Duty = 4876%(X100), DQS PI = 2
2359 13:30:34.154934 [-4] AVG Duty = 4922%(X100)
2360 13:30:34.155043
2361 13:30:34.155139 ==DQS 1 ==
2362 13:30:34.158447 Final DQS duty delay cell = 0
2363 13:30:34.161854 [0] MAX Duty = 5125%(X100), DQS PI = 50
2364 13:30:34.165109 [0] MIN Duty = 5000%(X100), DQS PI = 0
2365 13:30:34.168145 [0] AVG Duty = 5062%(X100)
2366 13:30:34.168260
2367 13:30:34.171721 CH0 DQS 0 Duty spec in!! Max-Min= 93%
2368 13:30:34.171826
2369 13:30:34.174735 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2370 13:30:34.178170 [DutyScan_Calibration_Flow] ====Done====
2371 13:30:34.178281
2372 13:30:34.181560 [DutyScan_Calibration_Flow] k_type=3
2373 13:30:34.198534
2374 13:30:34.198716 ==DQM 0 ==
2375 13:30:34.202255 Final DQM duty delay cell = 0
2376 13:30:34.205096 [0] MAX Duty = 5125%(X100), DQS PI = 20
2377 13:30:34.208766 [0] MIN Duty = 4844%(X100), DQS PI = 50
2378 13:30:34.211800 [0] AVG Duty = 4984%(X100)
2379 13:30:34.211934
2380 13:30:34.212044 ==DQM 1 ==
2381 13:30:34.215472 Final DQM duty delay cell = 0
2382 13:30:34.218446 [0] MAX Duty = 4969%(X100), DQS PI = 0
2383 13:30:34.221762 [0] MIN Duty = 4875%(X100), DQS PI = 22
2384 13:30:34.225247 [0] AVG Duty = 4922%(X100)
2385 13:30:34.225370
2386 13:30:34.228273 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2387 13:30:34.228380
2388 13:30:34.231901 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2389 13:30:34.235436 [DutyScan_Calibration_Flow] ====Done====
2390 13:30:34.235566
2391 13:30:34.238210 [DutyScan_Calibration_Flow] k_type=2
2392 13:30:34.255266
2393 13:30:34.255446 ==DQ 0 ==
2394 13:30:34.258086 Final DQ duty delay cell = 0
2395 13:30:34.261797 [0] MAX Duty = 5125%(X100), DQS PI = 18
2396 13:30:34.264809 [0] MIN Duty = 4969%(X100), DQS PI = 50
2397 13:30:34.264918 [0] AVG Duty = 5047%(X100)
2398 13:30:34.268138
2399 13:30:34.268256 ==DQ 1 ==
2400 13:30:34.271525 Final DQ duty delay cell = 0
2401 13:30:34.274957 [0] MAX Duty = 5125%(X100), DQS PI = 6
2402 13:30:34.277949 [0] MIN Duty = 4938%(X100), DQS PI = 16
2403 13:30:34.278068 [0] AVG Duty = 5031%(X100)
2404 13:30:34.281023
2405 13:30:34.284346 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2406 13:30:34.284454
2407 13:30:34.287745 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2408 13:30:34.291215 [DutyScan_Calibration_Flow] ====Done====
2409 13:30:34.291337 ==
2410 13:30:34.294188 Dram Type= 6, Freq= 0, CH_1, rank 0
2411 13:30:34.297834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2412 13:30:34.297954 ==
2413 13:30:34.301114 [Duty_Offset_Calibration]
2414 13:30:34.301223 B0:0 B1:-1 CA:3
2415 13:30:34.301320
2416 13:30:34.304349 [DutyScan_Calibration_Flow] k_type=0
2417 13:30:34.315059
2418 13:30:34.315230 ==CLK 0==
2419 13:30:34.317990 Final CLK duty delay cell = 0
2420 13:30:34.321725 [0] MAX Duty = 5156%(X100), DQS PI = 0
2421 13:30:34.324678 [0] MIN Duty = 5000%(X100), DQS PI = 36
2422 13:30:34.324809 [0] AVG Duty = 5078%(X100)
2423 13:30:34.328208
2424 13:30:34.331380 CH1 CLK Duty spec in!! Max-Min= 156%
2425 13:30:34.334674 [DutyScan_Calibration_Flow] ====Done====
2426 13:30:34.334802
2427 13:30:34.337799 [DutyScan_Calibration_Flow] k_type=1
2428 13:30:34.354472
2429 13:30:34.354654 ==DQS 0 ==
2430 13:30:34.357427 Final DQS duty delay cell = 0
2431 13:30:34.360428 [0] MAX Duty = 5187%(X100), DQS PI = 28
2432 13:30:34.364134 [0] MIN Duty = 4907%(X100), DQS PI = 38
2433 13:30:34.367223 [0] AVG Duty = 5047%(X100)
2434 13:30:34.367339
2435 13:30:34.367443 ==DQS 1 ==
2436 13:30:34.370781 Final DQS duty delay cell = 0
2437 13:30:34.373828 [0] MAX Duty = 5156%(X100), DQS PI = 8
2438 13:30:34.377422 [0] MIN Duty = 5031%(X100), DQS PI = 20
2439 13:30:34.380692 [0] AVG Duty = 5093%(X100)
2440 13:30:34.380812
2441 13:30:34.384267 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2442 13:30:34.384419
2443 13:30:34.387256 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2444 13:30:34.390283 [DutyScan_Calibration_Flow] ====Done====
2445 13:30:34.390419
2446 13:30:34.393725 [DutyScan_Calibration_Flow] k_type=3
2447 13:30:34.410533
2448 13:30:34.410719 ==DQM 0 ==
2449 13:30:34.414048 Final DQM duty delay cell = 0
2450 13:30:34.417522 [0] MAX Duty = 5031%(X100), DQS PI = 26
2451 13:30:34.420345 [0] MIN Duty = 4813%(X100), DQS PI = 38
2452 13:30:34.424094 [0] AVG Duty = 4922%(X100)
2453 13:30:34.424211
2454 13:30:34.424307 ==DQM 1 ==
2455 13:30:34.427151 Final DQM duty delay cell = 0
2456 13:30:34.430852 [0] MAX Duty = 5000%(X100), DQS PI = 34
2457 13:30:34.433672 [0] MIN Duty = 4844%(X100), DQS PI = 0
2458 13:30:34.437011 [0] AVG Duty = 4922%(X100)
2459 13:30:34.437135
2460 13:30:34.440387 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2461 13:30:34.440479
2462 13:30:34.443638 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2463 13:30:34.447178 [DutyScan_Calibration_Flow] ====Done====
2464 13:30:34.447299
2465 13:30:34.450092 [DutyScan_Calibration_Flow] k_type=2
2466 13:30:34.466167
2467 13:30:34.466341 ==DQ 0 ==
2468 13:30:34.469978 Final DQ duty delay cell = -4
2469 13:30:34.473002 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2470 13:30:34.476024 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2471 13:30:34.479646 [-4] AVG Duty = 4922%(X100)
2472 13:30:34.479764
2473 13:30:34.479865 ==DQ 1 ==
2474 13:30:34.482759 Final DQ duty delay cell = 0
2475 13:30:34.486103 [0] MAX Duty = 5031%(X100), DQS PI = 26
2476 13:30:34.489440 [0] MIN Duty = 4844%(X100), DQS PI = 62
2477 13:30:34.492873 [0] AVG Duty = 4937%(X100)
2478 13:30:34.492999
2479 13:30:34.496096 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2480 13:30:34.496211
2481 13:30:34.499545 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2482 13:30:34.502339 [DutyScan_Calibration_Flow] ====Done====
2483 13:30:34.505995 nWR fixed to 30
2484 13:30:34.509636 [ModeRegInit_LP4] CH0 RK0
2485 13:30:34.509765 [ModeRegInit_LP4] CH0 RK1
2486 13:30:34.512794 [ModeRegInit_LP4] CH1 RK0
2487 13:30:34.515614 [ModeRegInit_LP4] CH1 RK1
2488 13:30:34.515736 match AC timing 7
2489 13:30:34.522445 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2490 13:30:34.525960 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2491 13:30:34.529062 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2492 13:30:34.535865 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2493 13:30:34.538813 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2494 13:30:34.538934 ==
2495 13:30:34.542397 Dram Type= 6, Freq= 0, CH_0, rank 0
2496 13:30:34.545716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2497 13:30:34.545839 ==
2498 13:30:34.552319 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2499 13:30:34.558704 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2500 13:30:34.566391 [CA 0] Center 39 (9~70) winsize 62
2501 13:30:34.570064 [CA 1] Center 39 (9~69) winsize 61
2502 13:30:34.573079 [CA 2] Center 35 (5~66) winsize 62
2503 13:30:34.576872 [CA 3] Center 35 (5~66) winsize 62
2504 13:30:34.579708 [CA 4] Center 34 (4~64) winsize 61
2505 13:30:34.583453 [CA 5] Center 33 (3~64) winsize 62
2506 13:30:34.583575
2507 13:30:34.586477 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2508 13:30:34.586585
2509 13:30:34.589664 [CATrainingPosCal] consider 1 rank data
2510 13:30:34.593425 u2DelayCellTimex100 = 270/100 ps
2511 13:30:34.596097 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2512 13:30:34.603075 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2513 13:30:34.606091 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2514 13:30:34.609627 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2515 13:30:34.613110 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2516 13:30:34.616414 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2517 13:30:34.616529
2518 13:30:34.619848 CA PerBit enable=1, Macro0, CA PI delay=33
2519 13:30:34.619975
2520 13:30:34.622770 [CBTSetCACLKResult] CA Dly = 33
2521 13:30:34.625780 CS Dly: 7 (0~38)
2522 13:30:34.625895 ==
2523 13:30:34.629318 Dram Type= 6, Freq= 0, CH_0, rank 1
2524 13:30:34.632482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2525 13:30:34.632620 ==
2526 13:30:34.639104 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2527 13:30:34.642774 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2528 13:30:34.652284 [CA 0] Center 39 (9~70) winsize 62
2529 13:30:34.655869 [CA 1] Center 39 (9~70) winsize 62
2530 13:30:34.658722 [CA 2] Center 35 (5~66) winsize 62
2531 13:30:34.662364 [CA 3] Center 35 (5~66) winsize 62
2532 13:30:34.665831 [CA 4] Center 34 (4~65) winsize 62
2533 13:30:34.668556 [CA 5] Center 33 (3~64) winsize 62
2534 13:30:34.668688
2535 13:30:34.672059 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2536 13:30:34.672169
2537 13:30:34.675088 [CATrainingPosCal] consider 2 rank data
2538 13:30:34.678889 u2DelayCellTimex100 = 270/100 ps
2539 13:30:34.681959 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2540 13:30:34.688511 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2541 13:30:34.691634 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2542 13:30:34.695287 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2543 13:30:34.698883 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2544 13:30:34.701820 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2545 13:30:34.701937
2546 13:30:34.705298 CA PerBit enable=1, Macro0, CA PI delay=33
2547 13:30:34.705412
2548 13:30:34.708679 [CBTSetCACLKResult] CA Dly = 33
2549 13:30:34.711595 CS Dly: 8 (0~41)
2550 13:30:34.711702
2551 13:30:34.715020 ----->DramcWriteLeveling(PI) begin...
2552 13:30:34.715142 ==
2553 13:30:34.718708 Dram Type= 6, Freq= 0, CH_0, rank 0
2554 13:30:34.721636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2555 13:30:34.721750 ==
2556 13:30:34.724899 Write leveling (Byte 0): 32 => 32
2557 13:30:34.728455 Write leveling (Byte 1): 27 => 27
2558 13:30:34.731377 DramcWriteLeveling(PI) end<-----
2559 13:30:34.731496
2560 13:30:34.731595 ==
2561 13:30:34.735054 Dram Type= 6, Freq= 0, CH_0, rank 0
2562 13:30:34.737965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2563 13:30:34.738095 ==
2564 13:30:34.741862 [Gating] SW mode calibration
2565 13:30:34.748469 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2566 13:30:34.755018 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2567 13:30:34.758005 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2568 13:30:34.761820 0 15 4 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
2569 13:30:34.768199 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2570 13:30:34.771695 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2571 13:30:34.774893 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2572 13:30:34.781466 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2573 13:30:34.784509 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2574 13:30:34.788084 0 15 28 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
2575 13:30:34.794913 1 0 0 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
2576 13:30:34.797880 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2577 13:30:34.801442 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2578 13:30:34.807624 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2579 13:30:34.811126 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2580 13:30:34.814497 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2581 13:30:34.821453 1 0 24 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
2582 13:30:34.824453 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2583 13:30:34.828183 1 1 0 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2584 13:30:34.834183 1 1 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2585 13:30:34.837843 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2586 13:30:34.840807 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2587 13:30:34.847428 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2588 13:30:34.850888 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2589 13:30:34.854233 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2590 13:30:34.860836 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2591 13:30:34.863887 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2592 13:30:34.867606 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 13:30:34.871019 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 13:30:34.877732 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 13:30:34.880691 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 13:30:34.883999 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 13:30:34.890837 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 13:30:34.893873 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 13:30:34.897640 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 13:30:34.904499 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 13:30:34.907610 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 13:30:34.910699 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 13:30:34.917439 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 13:30:34.920894 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 13:30:34.924148 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 13:30:34.930386 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2607 13:30:34.933854 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2608 13:30:34.937271 Total UI for P1: 0, mck2ui 16
2609 13:30:34.940628 best dqsien dly found for B0: ( 1, 3, 28)
2610 13:30:34.944158 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2611 13:30:34.947242 Total UI for P1: 0, mck2ui 16
2612 13:30:34.950279 best dqsien dly found for B1: ( 1, 4, 0)
2613 13:30:34.953913 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2614 13:30:34.957386 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2615 13:30:34.957510
2616 13:30:34.963714 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2617 13:30:34.966925 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2618 13:30:34.967046 [Gating] SW calibration Done
2619 13:30:34.970510 ==
2620 13:30:34.973390 Dram Type= 6, Freq= 0, CH_0, rank 0
2621 13:30:34.977042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2622 13:30:34.977164 ==
2623 13:30:34.977262 RX Vref Scan: 0
2624 13:30:34.977358
2625 13:30:34.980047 RX Vref 0 -> 0, step: 1
2626 13:30:34.980155
2627 13:30:34.983794 RX Delay -40 -> 252, step: 8
2628 13:30:34.987334 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2629 13:30:34.990253 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2630 13:30:34.993542 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2631 13:30:35.000028 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2632 13:30:35.003642 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2633 13:30:35.006748 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2634 13:30:35.010470 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2635 13:30:35.013309 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2636 13:30:35.020158 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2637 13:30:35.023821 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2638 13:30:35.026663 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2639 13:30:35.030014 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2640 13:30:35.033524 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2641 13:30:35.040339 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2642 13:30:35.043061 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2643 13:30:35.046437 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2644 13:30:35.046580 ==
2645 13:30:35.049954 Dram Type= 6, Freq= 0, CH_0, rank 0
2646 13:30:35.053142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2647 13:30:35.056559 ==
2648 13:30:35.056692 DQS Delay:
2649 13:30:35.056801 DQS0 = 0, DQS1 = 0
2650 13:30:35.059693 DQM Delay:
2651 13:30:35.059812 DQM0 = 117, DQM1 = 108
2652 13:30:35.063082 DQ Delay:
2653 13:30:35.066451 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2654 13:30:35.069879 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2655 13:30:35.072913 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2656 13:30:35.076449 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =115
2657 13:30:35.076585
2658 13:30:35.076692
2659 13:30:35.076792 ==
2660 13:30:35.079967 Dram Type= 6, Freq= 0, CH_0, rank 0
2661 13:30:35.083019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2662 13:30:35.083136 ==
2663 13:30:35.083236
2664 13:30:35.085956
2665 13:30:35.086063 TX Vref Scan disable
2666 13:30:35.089590 == TX Byte 0 ==
2667 13:30:35.093077 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2668 13:30:35.096107 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2669 13:30:35.099511 == TX Byte 1 ==
2670 13:30:35.102840 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2671 13:30:35.106577 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2672 13:30:35.106708 ==
2673 13:30:35.109598 Dram Type= 6, Freq= 0, CH_0, rank 0
2674 13:30:35.116380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2675 13:30:35.116508 ==
2676 13:30:35.127390 TX Vref=22, minBit 10, minWin=24, winSum=410
2677 13:30:35.130466 TX Vref=24, minBit 4, minWin=25, winSum=417
2678 13:30:35.134022 TX Vref=26, minBit 4, minWin=25, winSum=425
2679 13:30:35.137312 TX Vref=28, minBit 4, minWin=25, winSum=428
2680 13:30:35.140237 TX Vref=30, minBit 10, minWin=26, winSum=430
2681 13:30:35.147193 TX Vref=32, minBit 12, minWin=26, winSum=430
2682 13:30:35.150345 [TxChooseVref] Worse bit 10, Min win 26, Win sum 430, Final Vref 30
2683 13:30:35.150459
2684 13:30:35.153624 Final TX Range 1 Vref 30
2685 13:30:35.153723
2686 13:30:35.153789 ==
2687 13:30:35.156933 Dram Type= 6, Freq= 0, CH_0, rank 0
2688 13:30:35.160408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2689 13:30:35.163463 ==
2690 13:30:35.163577
2691 13:30:35.163701
2692 13:30:35.163795 TX Vref Scan disable
2693 13:30:35.167011 == TX Byte 0 ==
2694 13:30:35.170819 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2695 13:30:35.176769 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2696 13:30:35.176907 == TX Byte 1 ==
2697 13:30:35.180234 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2698 13:30:35.186748 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2699 13:30:35.186911
2700 13:30:35.187012 [DATLAT]
2701 13:30:35.187119 Freq=1200, CH0 RK0
2702 13:30:35.187243
2703 13:30:35.190350 DATLAT Default: 0xd
2704 13:30:35.190469 0, 0xFFFF, sum = 0
2705 13:30:35.193503 1, 0xFFFF, sum = 0
2706 13:30:35.197216 2, 0xFFFF, sum = 0
2707 13:30:35.197357 3, 0xFFFF, sum = 0
2708 13:30:35.200130 4, 0xFFFF, sum = 0
2709 13:30:35.200252 5, 0xFFFF, sum = 0
2710 13:30:35.203772 6, 0xFFFF, sum = 0
2711 13:30:35.203918 7, 0xFFFF, sum = 0
2712 13:30:35.206620 8, 0xFFFF, sum = 0
2713 13:30:35.206733 9, 0xFFFF, sum = 0
2714 13:30:35.210555 10, 0xFFFF, sum = 0
2715 13:30:35.210688 11, 0xFFFF, sum = 0
2716 13:30:35.213350 12, 0x0, sum = 1
2717 13:30:35.213471 13, 0x0, sum = 2
2718 13:30:35.217286 14, 0x0, sum = 3
2719 13:30:35.217417 15, 0x0, sum = 4
2720 13:30:35.220243 best_step = 13
2721 13:30:35.220382
2722 13:30:35.220484 ==
2723 13:30:35.223418 Dram Type= 6, Freq= 0, CH_0, rank 0
2724 13:30:35.226912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2725 13:30:35.227024 ==
2726 13:30:35.230169 RX Vref Scan: 1
2727 13:30:35.230283
2728 13:30:35.230377 Set Vref Range= 32 -> 127
2729 13:30:35.230470
2730 13:30:35.233092 RX Vref 32 -> 127, step: 1
2731 13:30:35.233212
2732 13:30:35.236708 RX Delay -21 -> 252, step: 4
2733 13:30:35.236813
2734 13:30:35.239616 Set Vref, RX VrefLevel [Byte0]: 32
2735 13:30:35.243015 [Byte1]: 32
2736 13:30:35.243113
2737 13:30:35.246602 Set Vref, RX VrefLevel [Byte0]: 33
2738 13:30:35.249471 [Byte1]: 33
2739 13:30:35.253402
2740 13:30:35.253529 Set Vref, RX VrefLevel [Byte0]: 34
2741 13:30:35.256810 [Byte1]: 34
2742 13:30:35.261404
2743 13:30:35.261532 Set Vref, RX VrefLevel [Byte0]: 35
2744 13:30:35.264672 [Byte1]: 35
2745 13:30:35.269717
2746 13:30:35.269865 Set Vref, RX VrefLevel [Byte0]: 36
2747 13:30:35.272685 [Byte1]: 36
2748 13:30:35.277619
2749 13:30:35.277737 Set Vref, RX VrefLevel [Byte0]: 37
2750 13:30:35.280513 [Byte1]: 37
2751 13:30:35.285645
2752 13:30:35.285768 Set Vref, RX VrefLevel [Byte0]: 38
2753 13:30:35.288451 [Byte1]: 38
2754 13:30:35.293305
2755 13:30:35.293438 Set Vref, RX VrefLevel [Byte0]: 39
2756 13:30:35.296392 [Byte1]: 39
2757 13:30:35.301308
2758 13:30:35.301435 Set Vref, RX VrefLevel [Byte0]: 40
2759 13:30:35.304246 [Byte1]: 40
2760 13:30:35.309191
2761 13:30:35.309317 Set Vref, RX VrefLevel [Byte0]: 41
2762 13:30:35.312789 [Byte1]: 41
2763 13:30:35.317101
2764 13:30:35.317238 Set Vref, RX VrefLevel [Byte0]: 42
2765 13:30:35.320598 [Byte1]: 42
2766 13:30:35.324804
2767 13:30:35.324930 Set Vref, RX VrefLevel [Byte0]: 43
2768 13:30:35.328505 [Byte1]: 43
2769 13:30:35.332736
2770 13:30:35.332858 Set Vref, RX VrefLevel [Byte0]: 44
2771 13:30:35.336418 [Byte1]: 44
2772 13:30:35.340627
2773 13:30:35.340765 Set Vref, RX VrefLevel [Byte0]: 45
2774 13:30:35.344367 [Byte1]: 45
2775 13:30:35.348943
2776 13:30:35.349070 Set Vref, RX VrefLevel [Byte0]: 46
2777 13:30:35.351976 [Byte1]: 46
2778 13:30:35.356872
2779 13:30:35.356970 Set Vref, RX VrefLevel [Byte0]: 47
2780 13:30:35.360129 [Byte1]: 47
2781 13:30:35.364652
2782 13:30:35.364762 Set Vref, RX VrefLevel [Byte0]: 48
2783 13:30:35.368066 [Byte1]: 48
2784 13:30:35.372608
2785 13:30:35.372740 Set Vref, RX VrefLevel [Byte0]: 49
2786 13:30:35.375882 [Byte1]: 49
2787 13:30:35.380322
2788 13:30:35.380455 Set Vref, RX VrefLevel [Byte0]: 50
2789 13:30:35.383947 [Byte1]: 50
2790 13:30:35.388701
2791 13:30:35.388832 Set Vref, RX VrefLevel [Byte0]: 51
2792 13:30:35.391697 [Byte1]: 51
2793 13:30:35.396437
2794 13:30:35.396564 Set Vref, RX VrefLevel [Byte0]: 52
2795 13:30:35.399997 [Byte1]: 52
2796 13:30:35.404086
2797 13:30:35.404193 Set Vref, RX VrefLevel [Byte0]: 53
2798 13:30:35.407645 [Byte1]: 53
2799 13:30:35.411914
2800 13:30:35.412008 Set Vref, RX VrefLevel [Byte0]: 54
2801 13:30:35.415617 [Byte1]: 54
2802 13:30:35.420373
2803 13:30:35.420497 Set Vref, RX VrefLevel [Byte0]: 55
2804 13:30:35.423460 [Byte1]: 55
2805 13:30:35.428030
2806 13:30:35.428159 Set Vref, RX VrefLevel [Byte0]: 56
2807 13:30:35.431543 [Byte1]: 56
2808 13:30:35.435853
2809 13:30:35.436002 Set Vref, RX VrefLevel [Byte0]: 57
2810 13:30:35.438964 [Byte1]: 57
2811 13:30:35.443674
2812 13:30:35.443796 Set Vref, RX VrefLevel [Byte0]: 58
2813 13:30:35.446973 [Byte1]: 58
2814 13:30:35.452059
2815 13:30:35.452176 Set Vref, RX VrefLevel [Byte0]: 59
2816 13:30:35.455122 [Byte1]: 59
2817 13:30:35.459942
2818 13:30:35.460072 Set Vref, RX VrefLevel [Byte0]: 60
2819 13:30:35.463060 [Byte1]: 60
2820 13:30:35.467759
2821 13:30:35.467883 Set Vref, RX VrefLevel [Byte0]: 61
2822 13:30:35.470577 [Byte1]: 61
2823 13:30:35.475856
2824 13:30:35.476005 Set Vref, RX VrefLevel [Byte0]: 62
2825 13:30:35.478759 [Byte1]: 62
2826 13:30:35.483356
2827 13:30:35.483483 Set Vref, RX VrefLevel [Byte0]: 63
2828 13:30:35.486608 [Byte1]: 63
2829 13:30:35.491433
2830 13:30:35.491565 Set Vref, RX VrefLevel [Byte0]: 64
2831 13:30:35.494948 [Byte1]: 64
2832 13:30:35.499163
2833 13:30:35.499281 Set Vref, RX VrefLevel [Byte0]: 65
2834 13:30:35.502626 [Byte1]: 65
2835 13:30:35.507272
2836 13:30:35.507382 Set Vref, RX VrefLevel [Byte0]: 66
2837 13:30:35.510622 [Byte1]: 66
2838 13:30:35.514915
2839 13:30:35.515016 Set Vref, RX VrefLevel [Byte0]: 67
2840 13:30:35.518614 [Byte1]: 67
2841 13:30:35.522857
2842 13:30:35.522979 Set Vref, RX VrefLevel [Byte0]: 68
2843 13:30:35.526333 [Byte1]: 68
2844 13:30:35.530684
2845 13:30:35.530808 Set Vref, RX VrefLevel [Byte0]: 69
2846 13:30:35.534040 [Byte1]: 69
2847 13:30:35.539424
2848 13:30:35.539567 Final RX Vref Byte 0 = 55 to rank0
2849 13:30:35.542372 Final RX Vref Byte 1 = 43 to rank0
2850 13:30:35.545284 Final RX Vref Byte 0 = 55 to rank1
2851 13:30:35.549026 Final RX Vref Byte 1 = 43 to rank1==
2852 13:30:35.552017 Dram Type= 6, Freq= 0, CH_0, rank 0
2853 13:30:35.558558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2854 13:30:35.558695 ==
2855 13:30:35.558803 DQS Delay:
2856 13:30:35.562376 DQS0 = 0, DQS1 = 0
2857 13:30:35.562485 DQM Delay:
2858 13:30:35.562590 DQM0 = 116, DQM1 = 102
2859 13:30:35.565436 DQ Delay:
2860 13:30:35.569004 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2861 13:30:35.571910 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =120
2862 13:30:35.575440 DQ8 =92, DQ9 =88, DQ10 =104, DQ11 =96
2863 13:30:35.578870 DQ12 =110, DQ13 =106, DQ14 =112, DQ15 =110
2864 13:30:35.578985
2865 13:30:35.579072
2866 13:30:35.585143 [DQSOSCAuto] RK0, (LSB)MR18= 0xfb, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 410 ps
2867 13:30:35.588734 CH0 RK0: MR19=403, MR18=FB
2868 13:30:35.595179 CH0_RK0: MR19=0x403, MR18=0xFB, DQSOSC=410, MR23=63, INC=39, DEC=26
2869 13:30:35.595381
2870 13:30:35.598634 ----->DramcWriteLeveling(PI) begin...
2871 13:30:35.598821 ==
2872 13:30:35.602234 Dram Type= 6, Freq= 0, CH_0, rank 1
2873 13:30:35.605620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2874 13:30:35.605886 ==
2875 13:30:35.608685 Write leveling (Byte 0): 34 => 34
2876 13:30:35.612186 Write leveling (Byte 1): 28 => 28
2877 13:30:35.615057 DramcWriteLeveling(PI) end<-----
2878 13:30:35.615302
2879 13:30:35.615458 ==
2880 13:30:35.618736 Dram Type= 6, Freq= 0, CH_0, rank 1
2881 13:30:35.621856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2882 13:30:35.625403 ==
2883 13:30:35.625637 [Gating] SW mode calibration
2884 13:30:35.635556 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2885 13:30:35.638740 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2886 13:30:35.642109 0 15 0 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
2887 13:30:35.648172 0 15 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2888 13:30:35.651895 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2889 13:30:35.654832 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2890 13:30:35.661729 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2891 13:30:35.665388 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2892 13:30:35.668313 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2893 13:30:35.675006 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
2894 13:30:35.678785 1 0 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
2895 13:30:35.681830 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2896 13:30:35.688120 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2897 13:30:35.691706 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2898 13:30:35.695249 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2899 13:30:35.701710 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2900 13:30:35.704702 1 0 24 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (0 0)
2901 13:30:35.708124 1 0 28 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2902 13:30:35.714824 1 1 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
2903 13:30:35.717958 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2904 13:30:35.721426 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2905 13:30:35.727951 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2906 13:30:35.731595 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2907 13:30:35.734470 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2908 13:30:35.741195 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2909 13:30:35.744836 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2910 13:30:35.747911 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2911 13:30:35.751529 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 13:30:35.757750 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 13:30:35.761585 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 13:30:35.764421 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 13:30:35.771733 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 13:30:35.774655 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 13:30:35.777803 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 13:30:35.784543 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 13:30:35.787625 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 13:30:35.791262 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 13:30:35.797944 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 13:30:35.800991 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 13:30:35.804597 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 13:30:35.811256 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2925 13:30:35.814383 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2926 13:30:35.817424 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2927 13:30:35.820741 Total UI for P1: 0, mck2ui 16
2928 13:30:35.824491 best dqsien dly found for B0: ( 1, 3, 26)
2929 13:30:35.830863 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2930 13:30:35.831021 Total UI for P1: 0, mck2ui 16
2931 13:30:35.837507 best dqsien dly found for B1: ( 1, 4, 0)
2932 13:30:35.840829 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2933 13:30:35.844171 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2934 13:30:35.844298
2935 13:30:35.847331 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2936 13:30:35.850909 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2937 13:30:35.853979 [Gating] SW calibration Done
2938 13:30:35.854094 ==
2939 13:30:35.857635 Dram Type= 6, Freq= 0, CH_0, rank 1
2940 13:30:35.860891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2941 13:30:35.861004 ==
2942 13:30:35.864163 RX Vref Scan: 0
2943 13:30:35.864272
2944 13:30:35.864367 RX Vref 0 -> 0, step: 1
2945 13:30:35.864466
2946 13:30:35.867562 RX Delay -40 -> 252, step: 8
2947 13:30:35.870894 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2948 13:30:35.877366 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2949 13:30:35.880436 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2950 13:30:35.884012 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2951 13:30:35.887129 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2952 13:30:35.890815 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2953 13:30:35.897534 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2954 13:30:35.900561 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2955 13:30:35.904000 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2956 13:30:35.907382 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2957 13:30:35.910362 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2958 13:30:35.917216 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2959 13:30:35.920375 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2960 13:30:35.923445 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2961 13:30:35.927224 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2962 13:30:35.930120 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2963 13:30:35.933543 ==
2964 13:30:35.936719 Dram Type= 6, Freq= 0, CH_0, rank 1
2965 13:30:35.940467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2966 13:30:35.940566 ==
2967 13:30:35.940634 DQS Delay:
2968 13:30:35.943699 DQS0 = 0, DQS1 = 0
2969 13:30:35.943823 DQM Delay:
2970 13:30:35.947039 DQM0 = 117, DQM1 = 105
2971 13:30:35.947137 DQ Delay:
2972 13:30:35.950420 DQ0 =111, DQ1 =119, DQ2 =115, DQ3 =111
2973 13:30:35.953589 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =123
2974 13:30:35.956539 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2975 13:30:35.960059 DQ12 =111, DQ13 =111, DQ14 =115, DQ15 =111
2976 13:30:35.960152
2977 13:30:35.960220
2978 13:30:35.960281 ==
2979 13:30:35.963183 Dram Type= 6, Freq= 0, CH_0, rank 1
2980 13:30:35.969879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2981 13:30:35.970016 ==
2982 13:30:35.970114
2983 13:30:35.970227
2984 13:30:35.970333 TX Vref Scan disable
2985 13:30:35.973462 == TX Byte 0 ==
2986 13:30:35.976878 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2987 13:30:35.980104 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2988 13:30:35.983504 == TX Byte 1 ==
2989 13:30:35.987226 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2990 13:30:35.990460 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2991 13:30:35.993482 ==
2992 13:30:35.997242 Dram Type= 6, Freq= 0, CH_0, rank 1
2993 13:30:36.000203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2994 13:30:36.000290 ==
2995 13:30:36.011750 TX Vref=22, minBit 1, minWin=25, winSum=417
2996 13:30:36.015266 TX Vref=24, minBit 15, minWin=25, winSum=422
2997 13:30:36.018539 TX Vref=26, minBit 4, minWin=26, winSum=427
2998 13:30:36.021825 TX Vref=28, minBit 13, minWin=25, winSum=426
2999 13:30:36.025327 TX Vref=30, minBit 12, minWin=25, winSum=428
3000 13:30:36.031612 TX Vref=32, minBit 10, minWin=26, winSum=429
3001 13:30:36.035167 [TxChooseVref] Worse bit 10, Min win 26, Win sum 429, Final Vref 32
3002 13:30:36.035299
3003 13:30:36.038263 Final TX Range 1 Vref 32
3004 13:30:36.038383
3005 13:30:36.038482 ==
3006 13:30:36.041854 Dram Type= 6, Freq= 0, CH_0, rank 1
3007 13:30:36.048152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3008 13:30:36.048289 ==
3009 13:30:36.048398
3010 13:30:36.048504
3011 13:30:36.048595 TX Vref Scan disable
3012 13:30:36.052270 == TX Byte 0 ==
3013 13:30:36.055547 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3014 13:30:36.059059 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3015 13:30:36.062183 == TX Byte 1 ==
3016 13:30:36.065485 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3017 13:30:36.072305 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3018 13:30:36.072446
3019 13:30:36.072545 [DATLAT]
3020 13:30:36.072653 Freq=1200, CH0 RK1
3021 13:30:36.072749
3022 13:30:36.075384 DATLAT Default: 0xd
3023 13:30:36.075492 0, 0xFFFF, sum = 0
3024 13:30:36.078450 1, 0xFFFF, sum = 0
3025 13:30:36.081976 2, 0xFFFF, sum = 0
3026 13:30:36.082104 3, 0xFFFF, sum = 0
3027 13:30:36.085229 4, 0xFFFF, sum = 0
3028 13:30:36.085351 5, 0xFFFF, sum = 0
3029 13:30:36.088688 6, 0xFFFF, sum = 0
3030 13:30:36.088802 7, 0xFFFF, sum = 0
3031 13:30:36.092093 8, 0xFFFF, sum = 0
3032 13:30:36.092213 9, 0xFFFF, sum = 0
3033 13:30:36.095079 10, 0xFFFF, sum = 0
3034 13:30:36.095196 11, 0xFFFF, sum = 0
3035 13:30:36.098559 12, 0x0, sum = 1
3036 13:30:36.098678 13, 0x0, sum = 2
3037 13:30:36.101642 14, 0x0, sum = 3
3038 13:30:36.101766 15, 0x0, sum = 4
3039 13:30:36.105330 best_step = 13
3040 13:30:36.105451
3041 13:30:36.105554 ==
3042 13:30:36.108489 Dram Type= 6, Freq= 0, CH_0, rank 1
3043 13:30:36.111549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3044 13:30:36.111672 ==
3045 13:30:36.111773 RX Vref Scan: 0
3046 13:30:36.115066
3047 13:30:36.115188 RX Vref 0 -> 0, step: 1
3048 13:30:36.115285
3049 13:30:36.118257 RX Delay -21 -> 252, step: 4
3050 13:30:36.121824 iDelay=195, Bit 0, Center 112 (47 ~ 178) 132
3051 13:30:36.128506 iDelay=195, Bit 1, Center 118 (47 ~ 190) 144
3052 13:30:36.131867 iDelay=195, Bit 2, Center 112 (47 ~ 178) 132
3053 13:30:36.134852 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3054 13:30:36.138505 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3055 13:30:36.141670 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3056 13:30:36.148591 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3057 13:30:36.151473 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3058 13:30:36.155090 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3059 13:30:36.158626 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3060 13:30:36.161483 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3061 13:30:36.168158 iDelay=195, Bit 11, Center 96 (31 ~ 162) 132
3062 13:30:36.171697 iDelay=195, Bit 12, Center 108 (43 ~ 174) 132
3063 13:30:36.175237 iDelay=195, Bit 13, Center 108 (43 ~ 174) 132
3064 13:30:36.178128 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3065 13:30:36.181914 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3066 13:30:36.184854 ==
3067 13:30:36.184971 Dram Type= 6, Freq= 0, CH_0, rank 1
3068 13:30:36.191605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3069 13:30:36.191741 ==
3070 13:30:36.191853 DQS Delay:
3071 13:30:36.195195 DQS0 = 0, DQS1 = 0
3072 13:30:36.195311 DQM Delay:
3073 13:30:36.198481 DQM0 = 116, DQM1 = 104
3074 13:30:36.198597 DQ Delay:
3075 13:30:36.202050 DQ0 =112, DQ1 =118, DQ2 =112, DQ3 =112
3076 13:30:36.204905 DQ4 =118, DQ5 =110, DQ6 =126, DQ7 =122
3077 13:30:36.208054 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =96
3078 13:30:36.211683 DQ12 =108, DQ13 =108, DQ14 =116, DQ15 =112
3079 13:30:36.211813
3080 13:30:36.211926
3081 13:30:36.221447 [DQSOSCAuto] RK1, (LSB)MR18= 0xfaf7, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 412 ps
3082 13:30:36.221598 CH0 RK1: MR19=303, MR18=FAF7
3083 13:30:36.228341 CH0_RK1: MR19=0x303, MR18=0xFAF7, DQSOSC=412, MR23=63, INC=38, DEC=25
3084 13:30:36.231290 [RxdqsGatingPostProcess] freq 1200
3085 13:30:36.238093 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3086 13:30:36.241688 best DQS0 dly(2T, 0.5T) = (0, 11)
3087 13:30:36.244574 best DQS1 dly(2T, 0.5T) = (0, 12)
3088 13:30:36.247731 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3089 13:30:36.251182 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3090 13:30:36.254506 best DQS0 dly(2T, 0.5T) = (0, 11)
3091 13:30:36.257982 best DQS1 dly(2T, 0.5T) = (0, 12)
3092 13:30:36.261347 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3093 13:30:36.261473 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3094 13:30:36.264680 Pre-setting of DQS Precalculation
3095 13:30:36.271276 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3096 13:30:36.271415 ==
3097 13:30:36.274734 Dram Type= 6, Freq= 0, CH_1, rank 0
3098 13:30:36.277621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3099 13:30:36.277734 ==
3100 13:30:36.284196 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3101 13:30:36.290972 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3102 13:30:36.298633 [CA 0] Center 38 (8~68) winsize 61
3103 13:30:36.301736 [CA 1] Center 37 (7~68) winsize 62
3104 13:30:36.305200 [CA 2] Center 35 (5~65) winsize 61
3105 13:30:36.308518 [CA 3] Center 34 (4~64) winsize 61
3106 13:30:36.311406 [CA 4] Center 34 (4~65) winsize 62
3107 13:30:36.314954 [CA 5] Center 34 (4~64) winsize 61
3108 13:30:36.315075
3109 13:30:36.318049 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3110 13:30:36.318162
3111 13:30:36.321730 [CATrainingPosCal] consider 1 rank data
3112 13:30:36.325002 u2DelayCellTimex100 = 270/100 ps
3113 13:30:36.328472 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3114 13:30:36.334580 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3115 13:30:36.338232 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3116 13:30:36.341768 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
3117 13:30:36.344526 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3118 13:30:36.348355 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3119 13:30:36.348481
3120 13:30:36.351439 CA PerBit enable=1, Macro0, CA PI delay=34
3121 13:30:36.351567
3122 13:30:36.354686 [CBTSetCACLKResult] CA Dly = 34
3123 13:30:36.354798 CS Dly: 5 (0~36)
3124 13:30:36.358173 ==
3125 13:30:36.361510 Dram Type= 6, Freq= 0, CH_1, rank 1
3126 13:30:36.364505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3127 13:30:36.364625 ==
3128 13:30:36.368000 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3129 13:30:36.374545 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3130 13:30:36.383997 [CA 0] Center 37 (7~68) winsize 62
3131 13:30:36.386996 [CA 1] Center 38 (8~68) winsize 61
3132 13:30:36.390637 [CA 2] Center 35 (5~65) winsize 61
3133 13:30:36.393601 [CA 3] Center 34 (4~64) winsize 61
3134 13:30:36.397321 [CA 4] Center 34 (4~64) winsize 61
3135 13:30:36.400340 [CA 5] Center 33 (4~63) winsize 60
3136 13:30:36.400453
3137 13:30:36.404027 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3138 13:30:36.404112
3139 13:30:36.406940 [CATrainingPosCal] consider 2 rank data
3140 13:30:36.410595 u2DelayCellTimex100 = 270/100 ps
3141 13:30:36.413919 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3142 13:30:36.420370 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3143 13:30:36.423394 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3144 13:30:36.427107 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3145 13:30:36.430183 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3146 13:30:36.433328 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3147 13:30:36.433442
3148 13:30:36.436751 CA PerBit enable=1, Macro0, CA PI delay=33
3149 13:30:36.436875
3150 13:30:36.439926 [CBTSetCACLKResult] CA Dly = 33
3151 13:30:36.443469 CS Dly: 6 (0~39)
3152 13:30:36.443582
3153 13:30:36.446647 ----->DramcWriteLeveling(PI) begin...
3154 13:30:36.446758 ==
3155 13:30:36.449660 Dram Type= 6, Freq= 0, CH_1, rank 0
3156 13:30:36.453444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3157 13:30:36.453558 ==
3158 13:30:36.456893 Write leveling (Byte 0): 25 => 25
3159 13:30:36.459783 Write leveling (Byte 1): 26 => 26
3160 13:30:36.462818 DramcWriteLeveling(PI) end<-----
3161 13:30:36.462954
3162 13:30:36.463056 ==
3163 13:30:36.466755 Dram Type= 6, Freq= 0, CH_1, rank 0
3164 13:30:36.469748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3165 13:30:36.469884 ==
3166 13:30:36.473233 [Gating] SW mode calibration
3167 13:30:36.479528 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3168 13:30:36.486395 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3169 13:30:36.489810 0 15 0 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
3170 13:30:36.492693 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3171 13:30:36.499527 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3172 13:30:36.502553 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3173 13:30:36.505885 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3174 13:30:36.512654 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3175 13:30:36.515765 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3176 13:30:36.519380 0 15 28 | B1->B0 | 2e2e 2626 | 1 1 | (1 0) (1 0)
3177 13:30:36.526176 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3178 13:30:36.529502 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3179 13:30:36.533007 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3180 13:30:36.539573 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3181 13:30:36.542627 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3182 13:30:36.545603 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3183 13:30:36.552446 1 0 24 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
3184 13:30:36.556086 1 0 28 | B1->B0 | 3838 4545 | 1 0 | (0 0) (0 0)
3185 13:30:36.558981 1 1 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3186 13:30:36.565667 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3187 13:30:36.569359 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3188 13:30:36.572046 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3189 13:30:36.578976 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3190 13:30:36.581950 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3191 13:30:36.585419 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3192 13:30:36.591882 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3193 13:30:36.595446 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 13:30:36.598778 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 13:30:36.605458 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 13:30:36.608558 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 13:30:36.612189 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 13:30:36.618324 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 13:30:36.621887 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 13:30:36.625121 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 13:30:36.632281 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 13:30:36.634948 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 13:30:36.638237 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 13:30:36.645327 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 13:30:36.648402 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 13:30:36.652002 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 13:30:36.658029 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3208 13:30:36.661752 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3209 13:30:36.664816 Total UI for P1: 0, mck2ui 16
3210 13:30:36.668060 best dqsien dly found for B0: ( 1, 3, 24)
3211 13:30:36.671706 Total UI for P1: 0, mck2ui 16
3212 13:30:36.675005 best dqsien dly found for B1: ( 1, 3, 26)
3213 13:30:36.677873 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3214 13:30:36.681159 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3215 13:30:36.681257
3216 13:30:36.684810 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3217 13:30:36.687699 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3218 13:30:36.691344 [Gating] SW calibration Done
3219 13:30:36.691464 ==
3220 13:30:36.694613 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 13:30:36.698431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 13:30:36.698554 ==
3223 13:30:36.701321 RX Vref Scan: 0
3224 13:30:36.701431
3225 13:30:36.704778 RX Vref 0 -> 0, step: 1
3226 13:30:36.704903
3227 13:30:36.705001 RX Delay -40 -> 252, step: 8
3228 13:30:36.711221 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3229 13:30:36.714859 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3230 13:30:36.717920 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3231 13:30:36.721594 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3232 13:30:36.724760 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3233 13:30:36.731288 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3234 13:30:36.734291 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3235 13:30:36.738051 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3236 13:30:36.741159 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3237 13:30:36.744407 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3238 13:30:36.751122 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3239 13:30:36.754618 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3240 13:30:36.757852 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3241 13:30:36.760906 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3242 13:30:36.767668 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3243 13:30:36.771302 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3244 13:30:36.771442 ==
3245 13:30:36.774297 Dram Type= 6, Freq= 0, CH_1, rank 0
3246 13:30:36.777717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3247 13:30:36.777841 ==
3248 13:30:36.777943 DQS Delay:
3249 13:30:36.781252 DQS0 = 0, DQS1 = 0
3250 13:30:36.781371 DQM Delay:
3251 13:30:36.784304 DQM0 = 117, DQM1 = 114
3252 13:30:36.784414 DQ Delay:
3253 13:30:36.787851 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =119
3254 13:30:36.790958 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =115
3255 13:30:36.794220 DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =107
3256 13:30:36.800698 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =123
3257 13:30:36.800821
3258 13:30:36.800915
3259 13:30:36.800995 ==
3260 13:30:36.803984 Dram Type= 6, Freq= 0, CH_1, rank 0
3261 13:30:36.807189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3262 13:30:36.807287 ==
3263 13:30:36.807393
3264 13:30:36.807478
3265 13:30:36.810674 TX Vref Scan disable
3266 13:30:36.810764 == TX Byte 0 ==
3267 13:30:36.817249 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3268 13:30:36.820798 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3269 13:30:36.820903 == TX Byte 1 ==
3270 13:30:36.827513 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3271 13:30:36.830594 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3272 13:30:36.830688 ==
3273 13:30:36.833838 Dram Type= 6, Freq= 0, CH_1, rank 0
3274 13:30:36.837399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3275 13:30:36.837501 ==
3276 13:30:36.849528 TX Vref=22, minBit 9, minWin=24, winSum=406
3277 13:30:36.853035 TX Vref=24, minBit 1, minWin=25, winSum=414
3278 13:30:36.856540 TX Vref=26, minBit 8, minWin=24, winSum=418
3279 13:30:36.859713 TX Vref=28, minBit 9, minWin=24, winSum=418
3280 13:30:36.862711 TX Vref=30, minBit 3, minWin=26, winSum=425
3281 13:30:36.869398 TX Vref=32, minBit 9, minWin=25, winSum=421
3282 13:30:36.873086 [TxChooseVref] Worse bit 3, Min win 26, Win sum 425, Final Vref 30
3283 13:30:36.873218
3284 13:30:36.876332 Final TX Range 1 Vref 30
3285 13:30:36.876443
3286 13:30:36.876539 ==
3287 13:30:36.879378 Dram Type= 6, Freq= 0, CH_1, rank 0
3288 13:30:36.882647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3289 13:30:36.885938 ==
3290 13:30:36.886061
3291 13:30:36.886163
3292 13:30:36.886265 TX Vref Scan disable
3293 13:30:36.889727 == TX Byte 0 ==
3294 13:30:36.892734 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3295 13:30:36.899154 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3296 13:30:36.899297 == TX Byte 1 ==
3297 13:30:36.902604 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3298 13:30:36.909558 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3299 13:30:36.909706
3300 13:30:36.909810 [DATLAT]
3301 13:30:36.909905 Freq=1200, CH1 RK0
3302 13:30:36.910017
3303 13:30:36.912839 DATLAT Default: 0xd
3304 13:30:36.912950 0, 0xFFFF, sum = 0
3305 13:30:36.916060 1, 0xFFFF, sum = 0
3306 13:30:36.919284 2, 0xFFFF, sum = 0
3307 13:30:36.919404 3, 0xFFFF, sum = 0
3308 13:30:36.922815 4, 0xFFFF, sum = 0
3309 13:30:36.922932 5, 0xFFFF, sum = 0
3310 13:30:36.925958 6, 0xFFFF, sum = 0
3311 13:30:36.926070 7, 0xFFFF, sum = 0
3312 13:30:36.929020 8, 0xFFFF, sum = 0
3313 13:30:36.929130 9, 0xFFFF, sum = 0
3314 13:30:36.932646 10, 0xFFFF, sum = 0
3315 13:30:36.932756 11, 0xFFFF, sum = 0
3316 13:30:36.935694 12, 0x0, sum = 1
3317 13:30:36.935806 13, 0x0, sum = 2
3318 13:30:36.939181 14, 0x0, sum = 3
3319 13:30:36.939300 15, 0x0, sum = 4
3320 13:30:36.942444 best_step = 13
3321 13:30:36.942557
3322 13:30:36.942653 ==
3323 13:30:36.946030 Dram Type= 6, Freq= 0, CH_1, rank 0
3324 13:30:36.949040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3325 13:30:36.949150 ==
3326 13:30:36.949244 RX Vref Scan: 1
3327 13:30:36.952181
3328 13:30:36.952287 Set Vref Range= 32 -> 127
3329 13:30:36.952381
3330 13:30:36.955789 RX Vref 32 -> 127, step: 1
3331 13:30:36.955896
3332 13:30:36.958845 RX Delay -13 -> 252, step: 4
3333 13:30:36.958953
3334 13:30:36.962514 Set Vref, RX VrefLevel [Byte0]: 32
3335 13:30:36.965712 [Byte1]: 32
3336 13:30:36.965823
3337 13:30:36.969275 Set Vref, RX VrefLevel [Byte0]: 33
3338 13:30:36.971893 [Byte1]: 33
3339 13:30:36.975654
3340 13:30:36.975770 Set Vref, RX VrefLevel [Byte0]: 34
3341 13:30:36.979229 [Byte1]: 34
3342 13:30:36.983626
3343 13:30:36.983737 Set Vref, RX VrefLevel [Byte0]: 35
3344 13:30:36.987175 [Byte1]: 35
3345 13:30:36.991694
3346 13:30:36.991820 Set Vref, RX VrefLevel [Byte0]: 36
3347 13:30:36.994809 [Byte1]: 36
3348 13:30:36.999487
3349 13:30:36.999623 Set Vref, RX VrefLevel [Byte0]: 37
3350 13:30:37.002482 [Byte1]: 37
3351 13:30:37.007607
3352 13:30:37.007742 Set Vref, RX VrefLevel [Byte0]: 38
3353 13:30:37.010783 [Byte1]: 38
3354 13:30:37.015356
3355 13:30:37.015481 Set Vref, RX VrefLevel [Byte0]: 39
3356 13:30:37.018355 [Byte1]: 39
3357 13:30:37.023026
3358 13:30:37.023152 Set Vref, RX VrefLevel [Byte0]: 40
3359 13:30:37.026304 [Byte1]: 40
3360 13:30:37.030917
3361 13:30:37.031094 Set Vref, RX VrefLevel [Byte0]: 41
3362 13:30:37.034101 [Byte1]: 41
3363 13:30:37.039176
3364 13:30:37.039366 Set Vref, RX VrefLevel [Byte0]: 42
3365 13:30:37.042303 [Byte1]: 42
3366 13:30:37.046612
3367 13:30:37.046811 Set Vref, RX VrefLevel [Byte0]: 43
3368 13:30:37.050410 [Byte1]: 43
3369 13:30:37.054650
3370 13:30:37.054846 Set Vref, RX VrefLevel [Byte0]: 44
3371 13:30:37.057659 [Byte1]: 44
3372 13:30:37.062701
3373 13:30:37.062887 Set Vref, RX VrefLevel [Byte0]: 45
3374 13:30:37.065729 [Byte1]: 45
3375 13:30:37.070536
3376 13:30:37.070722 Set Vref, RX VrefLevel [Byte0]: 46
3377 13:30:37.073888 [Byte1]: 46
3378 13:30:37.078549
3379 13:30:37.078719 Set Vref, RX VrefLevel [Byte0]: 47
3380 13:30:37.081530 [Byte1]: 47
3381 13:30:37.085947
3382 13:30:37.086112 Set Vref, RX VrefLevel [Byte0]: 48
3383 13:30:37.089711 [Byte1]: 48
3384 13:30:37.094263
3385 13:30:37.094463 Set Vref, RX VrefLevel [Byte0]: 49
3386 13:30:37.097429 [Byte1]: 49
3387 13:30:37.102214
3388 13:30:37.102387 Set Vref, RX VrefLevel [Byte0]: 50
3389 13:30:37.105099 [Byte1]: 50
3390 13:30:37.110015
3391 13:30:37.110209 Set Vref, RX VrefLevel [Byte0]: 51
3392 13:30:37.112886 [Byte1]: 51
3393 13:30:37.117480
3394 13:30:37.117640 Set Vref, RX VrefLevel [Byte0]: 52
3395 13:30:37.120697 [Byte1]: 52
3396 13:30:37.125445
3397 13:30:37.125610 Set Vref, RX VrefLevel [Byte0]: 53
3398 13:30:37.129208 [Byte1]: 53
3399 13:30:37.133442
3400 13:30:37.133618 Set Vref, RX VrefLevel [Byte0]: 54
3401 13:30:37.136798 [Byte1]: 54
3402 13:30:37.141522
3403 13:30:37.141683 Set Vref, RX VrefLevel [Byte0]: 55
3404 13:30:37.144493 [Byte1]: 55
3405 13:30:37.149349
3406 13:30:37.149470 Set Vref, RX VrefLevel [Byte0]: 56
3407 13:30:37.152371 [Byte1]: 56
3408 13:30:37.157279
3409 13:30:37.157373 Set Vref, RX VrefLevel [Byte0]: 57
3410 13:30:37.160365 [Byte1]: 57
3411 13:30:37.164735
3412 13:30:37.164828 Set Vref, RX VrefLevel [Byte0]: 58
3413 13:30:37.168360 [Byte1]: 58
3414 13:30:37.172728
3415 13:30:37.172829 Set Vref, RX VrefLevel [Byte0]: 59
3416 13:30:37.176270 [Byte1]: 59
3417 13:30:37.180970
3418 13:30:37.181100 Set Vref, RX VrefLevel [Byte0]: 60
3419 13:30:37.183999 [Byte1]: 60
3420 13:30:37.188632
3421 13:30:37.188757 Set Vref, RX VrefLevel [Byte0]: 61
3422 13:30:37.191627 [Byte1]: 61
3423 13:30:37.196572
3424 13:30:37.196670 Set Vref, RX VrefLevel [Byte0]: 62
3425 13:30:37.199473 [Byte1]: 62
3426 13:30:37.204025
3427 13:30:37.204129 Set Vref, RX VrefLevel [Byte0]: 63
3428 13:30:37.207604 [Byte1]: 63
3429 13:30:37.212467
3430 13:30:37.212569 Set Vref, RX VrefLevel [Byte0]: 64
3431 13:30:37.215293 [Byte1]: 64
3432 13:30:37.220324
3433 13:30:37.220424 Set Vref, RX VrefLevel [Byte0]: 65
3434 13:30:37.223166 [Byte1]: 65
3435 13:30:37.227729
3436 13:30:37.227850 Set Vref, RX VrefLevel [Byte0]: 66
3437 13:30:37.231080 [Byte1]: 66
3438 13:30:37.235770
3439 13:30:37.235896 Set Vref, RX VrefLevel [Byte0]: 67
3440 13:30:37.239151 [Byte1]: 67
3441 13:30:37.243559
3442 13:30:37.243694 Set Vref, RX VrefLevel [Byte0]: 68
3443 13:30:37.247126 [Byte1]: 68
3444 13:30:37.251782
3445 13:30:37.251924 Set Vref, RX VrefLevel [Byte0]: 69
3446 13:30:37.254726 [Byte1]: 69
3447 13:30:37.259729
3448 13:30:37.259853 Set Vref, RX VrefLevel [Byte0]: 70
3449 13:30:37.262693 [Byte1]: 70
3450 13:30:37.267687
3451 13:30:37.267785 Set Vref, RX VrefLevel [Byte0]: 71
3452 13:30:37.270735 [Byte1]: 71
3453 13:30:37.275088
3454 13:30:37.275182 Final RX Vref Byte 0 = 51 to rank0
3455 13:30:37.278567 Final RX Vref Byte 1 = 58 to rank0
3456 13:30:37.281555 Final RX Vref Byte 0 = 51 to rank1
3457 13:30:37.285200 Final RX Vref Byte 1 = 58 to rank1==
3458 13:30:37.288223 Dram Type= 6, Freq= 0, CH_1, rank 0
3459 13:30:37.294911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3460 13:30:37.295034 ==
3461 13:30:37.295126 DQS Delay:
3462 13:30:37.298351 DQS0 = 0, DQS1 = 0
3463 13:30:37.298464 DQM Delay:
3464 13:30:37.298567 DQM0 = 117, DQM1 = 116
3465 13:30:37.301419 DQ Delay:
3466 13:30:37.304939 DQ0 =124, DQ1 =112, DQ2 =108, DQ3 =116
3467 13:30:37.308447 DQ4 =112, DQ5 =124, DQ6 =128, DQ7 =112
3468 13:30:37.311403 DQ8 =102, DQ9 =106, DQ10 =118, DQ11 =110
3469 13:30:37.314396 DQ12 =124, DQ13 =122, DQ14 =122, DQ15 =124
3470 13:30:37.314503
3471 13:30:37.314595
3472 13:30:37.324467 [DQSOSCAuto] RK0, (LSB)MR18= 0xeffc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 417 ps
3473 13:30:37.324595 CH1 RK0: MR19=303, MR18=EFFC
3474 13:30:37.330989 CH1_RK0: MR19=0x303, MR18=0xEFFC, DQSOSC=411, MR23=63, INC=38, DEC=25
3475 13:30:37.331145
3476 13:30:37.334310 ----->DramcWriteLeveling(PI) begin...
3477 13:30:37.334435 ==
3478 13:30:37.337791 Dram Type= 6, Freq= 0, CH_1, rank 1
3479 13:30:37.344471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3480 13:30:37.344617 ==
3481 13:30:37.347802 Write leveling (Byte 0): 25 => 25
3482 13:30:37.350954 Write leveling (Byte 1): 28 => 28
3483 13:30:37.354621 DramcWriteLeveling(PI) end<-----
3484 13:30:37.354745
3485 13:30:37.354851 ==
3486 13:30:37.357627 Dram Type= 6, Freq= 0, CH_1, rank 1
3487 13:30:37.361214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3488 13:30:37.361341 ==
3489 13:30:37.364498 [Gating] SW mode calibration
3490 13:30:37.371248 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3491 13:30:37.374485 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3492 13:30:37.381042 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3493 13:30:37.384628 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3494 13:30:37.387605 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3495 13:30:37.394580 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3496 13:30:37.397361 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3497 13:30:37.401100 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
3498 13:30:37.407307 0 15 24 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
3499 13:30:37.410639 0 15 28 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
3500 13:30:37.414115 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3501 13:30:37.420730 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3502 13:30:37.423725 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3503 13:30:37.427471 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3504 13:30:37.434104 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3505 13:30:37.436961 1 0 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3506 13:30:37.440267 1 0 24 | B1->B0 | 2525 4444 | 0 0 | (0 0) (0 0)
3507 13:30:37.446633 1 0 28 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
3508 13:30:37.450377 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 13:30:37.453240 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 13:30:37.460020 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3511 13:30:37.463370 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 13:30:37.466616 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3513 13:30:37.473375 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3514 13:30:37.476336 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3515 13:30:37.479526 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3516 13:30:37.486151 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 13:30:37.489622 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 13:30:37.492723 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 13:30:37.499683 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 13:30:37.502811 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 13:30:37.509424 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 13:30:37.512661 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 13:30:37.515512 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 13:30:37.522130 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 13:30:37.525609 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 13:30:37.528713 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 13:30:37.535780 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 13:30:37.539066 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 13:30:37.541889 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3530 13:30:37.548796 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3531 13:30:37.548943 Total UI for P1: 0, mck2ui 16
3532 13:30:37.551891 best dqsien dly found for B0: ( 1, 3, 20)
3533 13:30:37.558651 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3534 13:30:37.561468 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 13:30:37.565031 Total UI for P1: 0, mck2ui 16
3536 13:30:37.568447 best dqsien dly found for B1: ( 1, 3, 26)
3537 13:30:37.571485 best DQS0 dly(MCK, UI, PI) = (1, 3, 20)
3538 13:30:37.574725 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3539 13:30:37.574853
3540 13:30:37.581140 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 20)
3541 13:30:37.584728 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3542 13:30:37.584859 [Gating] SW calibration Done
3543 13:30:37.587921 ==
3544 13:30:37.591482 Dram Type= 6, Freq= 0, CH_1, rank 1
3545 13:30:37.594437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3546 13:30:37.594565 ==
3547 13:30:37.594667 RX Vref Scan: 0
3548 13:30:37.594762
3549 13:30:37.598248 RX Vref 0 -> 0, step: 1
3550 13:30:37.598364
3551 13:30:37.601226 RX Delay -40 -> 252, step: 8
3552 13:30:37.604313 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3553 13:30:37.607880 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3554 13:30:37.614435 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3555 13:30:37.617477 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3556 13:30:37.620912 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3557 13:30:37.624448 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3558 13:30:37.627782 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3559 13:30:37.634501 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3560 13:30:37.637188 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3561 13:30:37.640937 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3562 13:30:37.643919 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3563 13:30:37.646890 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3564 13:30:37.653686 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3565 13:30:37.657254 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3566 13:30:37.660324 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3567 13:30:37.663343 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3568 13:30:37.663463 ==
3569 13:30:37.666978 Dram Type= 6, Freq= 0, CH_1, rank 1
3570 13:30:37.673741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3571 13:30:37.673889 ==
3572 13:30:37.673997 DQS Delay:
3573 13:30:37.676822 DQS0 = 0, DQS1 = 0
3574 13:30:37.676938 DQM Delay:
3575 13:30:37.680387 DQM0 = 117, DQM1 = 114
3576 13:30:37.680486 DQ Delay:
3577 13:30:37.683279 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3578 13:30:37.686893 DQ4 =119, DQ5 =127, DQ6 =123, DQ7 =119
3579 13:30:37.689747 DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =111
3580 13:30:37.693384 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3581 13:30:37.693488
3582 13:30:37.693559
3583 13:30:37.693624 ==
3584 13:30:37.696854 Dram Type= 6, Freq= 0, CH_1, rank 1
3585 13:30:37.702852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3586 13:30:37.702956 ==
3587 13:30:37.703028
3588 13:30:37.703104
3589 13:30:37.703163 TX Vref Scan disable
3590 13:30:37.706741 == TX Byte 0 ==
3591 13:30:37.709830 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3592 13:30:37.716408 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3593 13:30:37.716535 == TX Byte 1 ==
3594 13:30:37.719895 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3595 13:30:37.726510 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3596 13:30:37.726686 ==
3597 13:30:37.729608 Dram Type= 6, Freq= 0, CH_1, rank 1
3598 13:30:37.733254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3599 13:30:37.733416 ==
3600 13:30:37.744830 TX Vref=22, minBit 2, minWin=25, winSum=420
3601 13:30:37.748197 TX Vref=24, minBit 9, minWin=24, winSum=420
3602 13:30:37.751191 TX Vref=26, minBit 9, minWin=25, winSum=427
3603 13:30:37.754828 TX Vref=28, minBit 9, minWin=25, winSum=430
3604 13:30:37.757678 TX Vref=30, minBit 9, minWin=25, winSum=430
3605 13:30:37.764763 TX Vref=32, minBit 9, minWin=25, winSum=429
3606 13:30:37.767581 [TxChooseVref] Worse bit 9, Min win 25, Win sum 430, Final Vref 28
3607 13:30:37.767688
3608 13:30:37.771336 Final TX Range 1 Vref 28
3609 13:30:37.771432
3610 13:30:37.771500 ==
3611 13:30:37.774323 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 13:30:37.777840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 13:30:37.780912 ==
3614 13:30:37.781009
3615 13:30:37.781077
3616 13:30:37.781139 TX Vref Scan disable
3617 13:30:37.784429 == TX Byte 0 ==
3618 13:30:37.787432 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3619 13:30:37.794374 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3620 13:30:37.794494 == TX Byte 1 ==
3621 13:30:37.797372 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3622 13:30:37.804550 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3623 13:30:37.804670
3624 13:30:37.804740 [DATLAT]
3625 13:30:37.804802 Freq=1200, CH1 RK1
3626 13:30:37.804863
3627 13:30:37.807604 DATLAT Default: 0xd
3628 13:30:37.810823 0, 0xFFFF, sum = 0
3629 13:30:37.810916 1, 0xFFFF, sum = 0
3630 13:30:37.813648 2, 0xFFFF, sum = 0
3631 13:30:37.813737 3, 0xFFFF, sum = 0
3632 13:30:37.817257 4, 0xFFFF, sum = 0
3633 13:30:37.817349 5, 0xFFFF, sum = 0
3634 13:30:37.820334 6, 0xFFFF, sum = 0
3635 13:30:37.820424 7, 0xFFFF, sum = 0
3636 13:30:37.823868 8, 0xFFFF, sum = 0
3637 13:30:37.823968 9, 0xFFFF, sum = 0
3638 13:30:37.827446 10, 0xFFFF, sum = 0
3639 13:30:37.827538 11, 0xFFFF, sum = 0
3640 13:30:37.830423 12, 0x0, sum = 1
3641 13:30:37.830505 13, 0x0, sum = 2
3642 13:30:37.834082 14, 0x0, sum = 3
3643 13:30:37.834173 15, 0x0, sum = 4
3644 13:30:37.837026 best_step = 13
3645 13:30:37.837103
3646 13:30:37.837167 ==
3647 13:30:37.840249 Dram Type= 6, Freq= 0, CH_1, rank 1
3648 13:30:37.843147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3649 13:30:37.843245 ==
3650 13:30:37.846940 RX Vref Scan: 0
3651 13:30:37.847064
3652 13:30:37.847162 RX Vref 0 -> 0, step: 1
3653 13:30:37.847257
3654 13:30:37.850235 RX Delay -13 -> 252, step: 4
3655 13:30:37.856786 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3656 13:30:37.860040 iDelay=195, Bit 1, Center 112 (47 ~ 178) 132
3657 13:30:37.863396 iDelay=195, Bit 2, Center 108 (43 ~ 174) 132
3658 13:30:37.866643 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3659 13:30:37.873105 iDelay=195, Bit 4, Center 116 (51 ~ 182) 132
3660 13:30:37.876069 iDelay=195, Bit 5, Center 126 (59 ~ 194) 136
3661 13:30:37.879763 iDelay=195, Bit 6, Center 124 (59 ~ 190) 132
3662 13:30:37.882734 iDelay=195, Bit 7, Center 116 (51 ~ 182) 132
3663 13:30:37.886183 iDelay=195, Bit 8, Center 104 (43 ~ 166) 124
3664 13:30:37.892714 iDelay=195, Bit 9, Center 106 (43 ~ 170) 128
3665 13:30:37.896208 iDelay=195, Bit 10, Center 118 (59 ~ 178) 120
3666 13:30:37.899296 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3667 13:30:37.902657 iDelay=195, Bit 12, Center 126 (67 ~ 186) 120
3668 13:30:37.906251 iDelay=195, Bit 13, Center 122 (59 ~ 186) 128
3669 13:30:37.912387 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3670 13:30:37.916145 iDelay=195, Bit 15, Center 126 (67 ~ 186) 120
3671 13:30:37.916299 ==
3672 13:30:37.919177 Dram Type= 6, Freq= 0, CH_1, rank 1
3673 13:30:37.922195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3674 13:30:37.922319 ==
3675 13:30:37.925830 DQS Delay:
3676 13:30:37.925950 DQS0 = 0, DQS1 = 0
3677 13:30:37.928868 DQM Delay:
3678 13:30:37.928999 DQM0 = 116, DQM1 = 116
3679 13:30:37.929114 DQ Delay:
3680 13:30:37.932449 DQ0 =118, DQ1 =112, DQ2 =108, DQ3 =114
3681 13:30:37.938882 DQ4 =116, DQ5 =126, DQ6 =124, DQ7 =116
3682 13:30:37.941912 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =110
3683 13:30:37.945537 DQ12 =126, DQ13 =122, DQ14 =122, DQ15 =126
3684 13:30:37.945676
3685 13:30:37.945790
3686 13:30:37.951829 [DQSOSCAuto] RK1, (LSB)MR18= 0xf406, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 415 ps
3687 13:30:37.955458 CH1 RK1: MR19=304, MR18=F406
3688 13:30:37.961918 CH1_RK1: MR19=0x304, MR18=0xF406, DQSOSC=407, MR23=63, INC=39, DEC=26
3689 13:30:37.965339 [RxdqsGatingPostProcess] freq 1200
3690 13:30:37.971519 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3691 13:30:37.975151 best DQS0 dly(2T, 0.5T) = (0, 11)
3692 13:30:37.975294 best DQS1 dly(2T, 0.5T) = (0, 11)
3693 13:30:37.978343 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3694 13:30:37.981488 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3695 13:30:37.984733 best DQS0 dly(2T, 0.5T) = (0, 11)
3696 13:30:37.988053 best DQS1 dly(2T, 0.5T) = (0, 11)
3697 13:30:37.991539 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3698 13:30:37.994755 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3699 13:30:37.998164 Pre-setting of DQS Precalculation
3700 13:30:38.004266 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3701 13:30:38.011083 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3702 13:30:38.017798 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3703 13:30:38.017969
3704 13:30:38.018087
3705 13:30:38.020894 [Calibration Summary] 2400 Mbps
3706 13:30:38.021009 CH 0, Rank 0
3707 13:30:38.024718 SW Impedance : PASS
3708 13:30:38.027653 DUTY Scan : NO K
3709 13:30:38.027769 ZQ Calibration : PASS
3710 13:30:38.030864 Jitter Meter : NO K
3711 13:30:38.034391 CBT Training : PASS
3712 13:30:38.034521 Write leveling : PASS
3713 13:30:38.037319 RX DQS gating : PASS
3714 13:30:38.040918 RX DQ/DQS(RDDQC) : PASS
3715 13:30:38.041045 TX DQ/DQS : PASS
3716 13:30:38.043846 RX DATLAT : PASS
3717 13:30:38.047450 RX DQ/DQS(Engine): PASS
3718 13:30:38.047565 TX OE : NO K
3719 13:30:38.050427 All Pass.
3720 13:30:38.050535
3721 13:30:38.050643 CH 0, Rank 1
3722 13:30:38.053642 SW Impedance : PASS
3723 13:30:38.053754 DUTY Scan : NO K
3724 13:30:38.057101 ZQ Calibration : PASS
3725 13:30:38.060284 Jitter Meter : NO K
3726 13:30:38.060407 CBT Training : PASS
3727 13:30:38.063828 Write leveling : PASS
3728 13:30:38.066922 RX DQS gating : PASS
3729 13:30:38.067042 RX DQ/DQS(RDDQC) : PASS
3730 13:30:38.070549 TX DQ/DQS : PASS
3731 13:30:38.073634 RX DATLAT : PASS
3732 13:30:38.073741 RX DQ/DQS(Engine): PASS
3733 13:30:38.077202 TX OE : NO K
3734 13:30:38.077300 All Pass.
3735 13:30:38.077376
3736 13:30:38.080586 CH 1, Rank 0
3737 13:30:38.080684 SW Impedance : PASS
3738 13:30:38.083756 DUTY Scan : NO K
3739 13:30:38.087049 ZQ Calibration : PASS
3740 13:30:38.087205 Jitter Meter : NO K
3741 13:30:38.090182 CBT Training : PASS
3742 13:30:38.093673 Write leveling : PASS
3743 13:30:38.093836 RX DQS gating : PASS
3744 13:30:38.096750 RX DQ/DQS(RDDQC) : PASS
3745 13:30:38.096891 TX DQ/DQS : PASS
3746 13:30:38.100210 RX DATLAT : PASS
3747 13:30:38.103158 RX DQ/DQS(Engine): PASS
3748 13:30:38.103333 TX OE : NO K
3749 13:30:38.106548 All Pass.
3750 13:30:38.106689
3751 13:30:38.106800 CH 1, Rank 1
3752 13:30:38.109911 SW Impedance : PASS
3753 13:30:38.110046 DUTY Scan : NO K
3754 13:30:38.112855 ZQ Calibration : PASS
3755 13:30:38.116328 Jitter Meter : NO K
3756 13:30:38.116429 CBT Training : PASS
3757 13:30:38.119475 Write leveling : PASS
3758 13:30:38.123183 RX DQS gating : PASS
3759 13:30:38.123292 RX DQ/DQS(RDDQC) : PASS
3760 13:30:38.126304 TX DQ/DQS : PASS
3761 13:30:38.129348 RX DATLAT : PASS
3762 13:30:38.129467 RX DQ/DQS(Engine): PASS
3763 13:30:38.132985 TX OE : NO K
3764 13:30:38.133093 All Pass.
3765 13:30:38.133206
3766 13:30:38.135946 DramC Write-DBI off
3767 13:30:38.139607 PER_BANK_REFRESH: Hybrid Mode
3768 13:30:38.139736 TX_TRACKING: ON
3769 13:30:38.149044 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3770 13:30:38.152580 [FAST_K] Save calibration result to emmc
3771 13:30:38.155687 dramc_set_vcore_voltage set vcore to 650000
3772 13:30:38.159477 Read voltage for 600, 5
3773 13:30:38.159616 Vio18 = 0
3774 13:30:38.162526 Vcore = 650000
3775 13:30:38.162646 Vdram = 0
3776 13:30:38.162742 Vddq = 0
3777 13:30:38.162841 Vmddr = 0
3778 13:30:38.169137 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3779 13:30:38.175356 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3780 13:30:38.175515 MEM_TYPE=3, freq_sel=19
3781 13:30:38.179236 sv_algorithm_assistance_LP4_1600
3782 13:30:38.182359 ============ PULL DRAM RESETB DOWN ============
3783 13:30:38.188926 ========== PULL DRAM RESETB DOWN end =========
3784 13:30:38.192098 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3785 13:30:38.195499 ===================================
3786 13:30:38.198469 LPDDR4 DRAM CONFIGURATION
3787 13:30:38.202009 ===================================
3788 13:30:38.202131 EX_ROW_EN[0] = 0x0
3789 13:30:38.205055 EX_ROW_EN[1] = 0x0
3790 13:30:38.205169 LP4Y_EN = 0x0
3791 13:30:38.208546 WORK_FSP = 0x0
3792 13:30:38.211746 WL = 0x2
3793 13:30:38.211864 RL = 0x2
3794 13:30:38.215345 BL = 0x2
3795 13:30:38.215488 RPST = 0x0
3796 13:30:38.218474 RD_PRE = 0x0
3797 13:30:38.218586 WR_PRE = 0x1
3798 13:30:38.221617 WR_PST = 0x0
3799 13:30:38.221724 DBI_WR = 0x0
3800 13:30:38.225343 DBI_RD = 0x0
3801 13:30:38.225462 OTF = 0x1
3802 13:30:38.228327 ===================================
3803 13:30:38.231594 ===================================
3804 13:30:38.235129 ANA top config
3805 13:30:38.238049 ===================================
3806 13:30:38.238165 DLL_ASYNC_EN = 0
3807 13:30:38.241267 ALL_SLAVE_EN = 1
3808 13:30:38.244752 NEW_RANK_MODE = 1
3809 13:30:38.247727 DLL_IDLE_MODE = 1
3810 13:30:38.251339 LP45_APHY_COMB_EN = 1
3811 13:30:38.251467 TX_ODT_DIS = 1
3812 13:30:38.254276 NEW_8X_MODE = 1
3813 13:30:38.257920 ===================================
3814 13:30:38.260941 ===================================
3815 13:30:38.264630 data_rate = 1200
3816 13:30:38.267703 CKR = 1
3817 13:30:38.270911 DQ_P2S_RATIO = 8
3818 13:30:38.273904 ===================================
3819 13:30:38.277724 CA_P2S_RATIO = 8
3820 13:30:38.277847 DQ_CA_OPEN = 0
3821 13:30:38.280705 DQ_SEMI_OPEN = 0
3822 13:30:38.283765 CA_SEMI_OPEN = 0
3823 13:30:38.287466 CA_FULL_RATE = 0
3824 13:30:38.290536 DQ_CKDIV4_EN = 1
3825 13:30:38.293937 CA_CKDIV4_EN = 1
3826 13:30:38.294083 CA_PREDIV_EN = 0
3827 13:30:38.297038 PH8_DLY = 0
3828 13:30:38.300520 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3829 13:30:38.304015 DQ_AAMCK_DIV = 4
3830 13:30:38.307070 CA_AAMCK_DIV = 4
3831 13:30:38.310055 CA_ADMCK_DIV = 4
3832 13:30:38.313709 DQ_TRACK_CA_EN = 0
3833 13:30:38.313846 CA_PICK = 600
3834 13:30:38.316919 CA_MCKIO = 600
3835 13:30:38.320188 MCKIO_SEMI = 0
3836 13:30:38.323521 PLL_FREQ = 2288
3837 13:30:38.326539 DQ_UI_PI_RATIO = 32
3838 13:30:38.329996 CA_UI_PI_RATIO = 0
3839 13:30:38.333324 ===================================
3840 13:30:38.336586 ===================================
3841 13:30:38.336723 memory_type:LPDDR4
3842 13:30:38.340123 GP_NUM : 10
3843 13:30:38.343541 SRAM_EN : 1
3844 13:30:38.343655 MD32_EN : 0
3845 13:30:38.346717 ===================================
3846 13:30:38.349722 [ANA_INIT] >>>>>>>>>>>>>>
3847 13:30:38.353405 <<<<<< [CONFIGURE PHASE]: ANA_TX
3848 13:30:38.356343 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3849 13:30:38.359838 ===================================
3850 13:30:38.362897 data_rate = 1200,PCW = 0X5800
3851 13:30:38.366507 ===================================
3852 13:30:38.369350 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3853 13:30:38.376051 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3854 13:30:38.379120 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3855 13:30:38.385884 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3856 13:30:38.388934 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3857 13:30:38.392421 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3858 13:30:38.392528 [ANA_INIT] flow start
3859 13:30:38.395895 [ANA_INIT] PLL >>>>>>>>
3860 13:30:38.399355 [ANA_INIT] PLL <<<<<<<<
3861 13:30:38.399461 [ANA_INIT] MIDPI >>>>>>>>
3862 13:30:38.402393 [ANA_INIT] MIDPI <<<<<<<<
3863 13:30:38.405435 [ANA_INIT] DLL >>>>>>>>
3864 13:30:38.405571 [ANA_INIT] flow end
3865 13:30:38.412376 ============ LP4 DIFF to SE enter ============
3866 13:30:38.415378 ============ LP4 DIFF to SE exit ============
3867 13:30:38.418482 [ANA_INIT] <<<<<<<<<<<<<
3868 13:30:38.422266 [Flow] Enable top DCM control >>>>>
3869 13:30:38.425145 [Flow] Enable top DCM control <<<<<
3870 13:30:38.428497 Enable DLL master slave shuffle
3871 13:30:38.431706 ==============================================================
3872 13:30:38.435262 Gating Mode config
3873 13:30:38.438451 ==============================================================
3874 13:30:38.441878 Config description:
3875 13:30:38.451494 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3876 13:30:38.458109 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3877 13:30:38.461784 SELPH_MODE 0: By rank 1: By Phase
3878 13:30:38.467857 ==============================================================
3879 13:30:38.471475 GAT_TRACK_EN = 1
3880 13:30:38.474555 RX_GATING_MODE = 2
3881 13:30:38.478297 RX_GATING_TRACK_MODE = 2
3882 13:30:38.481397 SELPH_MODE = 1
3883 13:30:38.484412 PICG_EARLY_EN = 1
3884 13:30:38.488083 VALID_LAT_VALUE = 1
3885 13:30:38.491013 ==============================================================
3886 13:30:38.494019 Enter into Gating configuration >>>>
3887 13:30:38.497769 Exit from Gating configuration <<<<
3888 13:30:38.500586 Enter into DVFS_PRE_config >>>>>
3889 13:30:38.513771 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3890 13:30:38.517270 Exit from DVFS_PRE_config <<<<<
3891 13:30:38.520355 Enter into PICG configuration >>>>
3892 13:30:38.520546 Exit from PICG configuration <<<<
3893 13:30:38.524122 [RX_INPUT] configuration >>>>>
3894 13:30:38.527249 [RX_INPUT] configuration <<<<<
3895 13:30:38.533451 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3896 13:30:38.536839 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3897 13:30:38.543331 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3898 13:30:38.550109 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3899 13:30:38.556613 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3900 13:30:38.563188 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3901 13:30:38.566558 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3902 13:30:38.569899 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3903 13:30:38.576481 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3904 13:30:38.579778 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3905 13:30:38.582930 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3906 13:30:38.589734 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3907 13:30:38.592745 ===================================
3908 13:30:38.592849 LPDDR4 DRAM CONFIGURATION
3909 13:30:38.596418 ===================================
3910 13:30:38.599527 EX_ROW_EN[0] = 0x0
3911 13:30:38.599657 EX_ROW_EN[1] = 0x0
3912 13:30:38.602615 LP4Y_EN = 0x0
3913 13:30:38.602722 WORK_FSP = 0x0
3914 13:30:38.606095 WL = 0x2
3915 13:30:38.609143 RL = 0x2
3916 13:30:38.609260 BL = 0x2
3917 13:30:38.612623 RPST = 0x0
3918 13:30:38.612739 RD_PRE = 0x0
3919 13:30:38.615702 WR_PRE = 0x1
3920 13:30:38.615818 WR_PST = 0x0
3921 13:30:38.618934 DBI_WR = 0x0
3922 13:30:38.619050 DBI_RD = 0x0
3923 13:30:38.622303 OTF = 0x1
3924 13:30:38.625831 ===================================
3925 13:30:38.628769 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3926 13:30:38.632687 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3927 13:30:38.639110 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3928 13:30:38.641872 ===================================
3929 13:30:38.642065 LPDDR4 DRAM CONFIGURATION
3930 13:30:38.645312 ===================================
3931 13:30:38.648834 EX_ROW_EN[0] = 0x10
3932 13:30:38.651960 EX_ROW_EN[1] = 0x0
3933 13:30:38.652065 LP4Y_EN = 0x0
3934 13:30:38.655566 WORK_FSP = 0x0
3935 13:30:38.655676 WL = 0x2
3936 13:30:38.658632 RL = 0x2
3937 13:30:38.658747 BL = 0x2
3938 13:30:38.662043 RPST = 0x0
3939 13:30:38.662155 RD_PRE = 0x0
3940 13:30:38.665015 WR_PRE = 0x1
3941 13:30:38.665137 WR_PST = 0x0
3942 13:30:38.668508 DBI_WR = 0x0
3943 13:30:38.668639 DBI_RD = 0x0
3944 13:30:38.671452 OTF = 0x1
3945 13:30:38.674843 ===================================
3946 13:30:38.681881 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3947 13:30:38.685077 nWR fixed to 30
3948 13:30:38.685204 [ModeRegInit_LP4] CH0 RK0
3949 13:30:38.688409 [ModeRegInit_LP4] CH0 RK1
3950 13:30:38.691915 [ModeRegInit_LP4] CH1 RK0
3951 13:30:38.694896 [ModeRegInit_LP4] CH1 RK1
3952 13:30:38.695008 match AC timing 17
3953 13:30:38.701193 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3954 13:30:38.704854 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3955 13:30:38.707741 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3956 13:30:38.714382 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3957 13:30:38.718022 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3958 13:30:38.718165 ==
3959 13:30:38.721030 Dram Type= 6, Freq= 0, CH_0, rank 0
3960 13:30:38.724165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3961 13:30:38.724306 ==
3962 13:30:38.730930 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3963 13:30:38.737489 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3964 13:30:38.741097 [CA 0] Center 36 (6~67) winsize 62
3965 13:30:38.743974 [CA 1] Center 36 (5~67) winsize 63
3966 13:30:38.747567 [CA 2] Center 34 (4~65) winsize 62
3967 13:30:38.750852 [CA 3] Center 34 (4~65) winsize 62
3968 13:30:38.754096 [CA 4] Center 33 (3~64) winsize 62
3969 13:30:38.757179 [CA 5] Center 33 (3~64) winsize 62
3970 13:30:38.757308
3971 13:30:38.760811 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3972 13:30:38.760922
3973 13:30:38.763702 [CATrainingPosCal] consider 1 rank data
3974 13:30:38.767297 u2DelayCellTimex100 = 270/100 ps
3975 13:30:38.770281 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3976 13:30:38.773694 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
3977 13:30:38.777079 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3978 13:30:38.783435 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3979 13:30:38.786591 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3980 13:30:38.790046 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3981 13:30:38.790169
3982 13:30:38.793564 CA PerBit enable=1, Macro0, CA PI delay=33
3983 13:30:38.793678
3984 13:30:38.796737 [CBTSetCACLKResult] CA Dly = 33
3985 13:30:38.796861 CS Dly: 5 (0~36)
3986 13:30:38.796957 ==
3987 13:30:38.799915 Dram Type= 6, Freq= 0, CH_0, rank 1
3988 13:30:38.806400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3989 13:30:38.806548 ==
3990 13:30:38.809377 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3991 13:30:38.816267 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3992 13:30:38.819762 [CA 0] Center 36 (6~67) winsize 62
3993 13:30:38.822917 [CA 1] Center 36 (6~67) winsize 62
3994 13:30:38.826700 [CA 2] Center 34 (4~65) winsize 62
3995 13:30:38.829584 [CA 3] Center 34 (4~65) winsize 62
3996 13:30:38.833052 [CA 4] Center 34 (3~65) winsize 63
3997 13:30:38.835838 [CA 5] Center 33 (3~64) winsize 62
3998 13:30:38.835960
3999 13:30:38.839519 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4000 13:30:38.839632
4001 13:30:38.846114 [CATrainingPosCal] consider 2 rank data
4002 13:30:38.846257 u2DelayCellTimex100 = 270/100 ps
4003 13:30:38.852321 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4004 13:30:38.855855 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4005 13:30:38.859250 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4006 13:30:38.862440 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4007 13:30:38.865667 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4008 13:30:38.868616 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4009 13:30:38.868739
4010 13:30:38.872349 CA PerBit enable=1, Macro0, CA PI delay=33
4011 13:30:38.872468
4012 13:30:38.875424 [CBTSetCACLKResult] CA Dly = 33
4013 13:30:38.878809 CS Dly: 5 (0~37)
4014 13:30:38.878920
4015 13:30:38.882240 ----->DramcWriteLeveling(PI) begin...
4016 13:30:38.882389 ==
4017 13:30:38.885191 Dram Type= 6, Freq= 0, CH_0, rank 0
4018 13:30:38.888328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4019 13:30:38.888517 ==
4020 13:30:38.891930 Write leveling (Byte 0): 31 => 31
4021 13:30:38.895120 Write leveling (Byte 1): 31 => 31
4022 13:30:38.898729 DramcWriteLeveling(PI) end<-----
4023 13:30:38.898927
4024 13:30:38.899063 ==
4025 13:30:38.901765 Dram Type= 6, Freq= 0, CH_0, rank 0
4026 13:30:38.904681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4027 13:30:38.904853 ==
4028 13:30:38.908364 [Gating] SW mode calibration
4029 13:30:38.914864 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4030 13:30:38.921704 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4031 13:30:38.924687 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4032 13:30:38.931343 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4033 13:30:38.934358 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4034 13:30:38.938099 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
4035 13:30:38.944517 0 9 16 | B1->B0 | 2e2e 2727 | 0 0 | (0 1) (0 0)
4036 13:30:38.947957 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 13:30:38.950911 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 13:30:38.957573 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 13:30:38.960606 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4040 13:30:38.964448 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 13:30:38.970609 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 13:30:38.973740 0 10 12 | B1->B0 | 2323 3130 | 0 1 | (0 0) (0 0)
4043 13:30:38.977659 0 10 16 | B1->B0 | 3737 4040 | 0 0 | (0 0) (1 1)
4044 13:30:38.984124 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 13:30:38.987135 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 13:30:38.990627 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 13:30:38.996962 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 13:30:39.000471 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 13:30:39.003614 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 13:30:39.010647 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 13:30:39.013688 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4052 13:30:39.016622 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 13:30:39.023500 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 13:30:39.026651 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 13:30:39.029759 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 13:30:39.036368 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 13:30:39.039997 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 13:30:39.043167 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 13:30:39.049991 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 13:30:39.052797 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 13:30:39.056641 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 13:30:39.063004 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 13:30:39.066228 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 13:30:39.069229 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 13:30:39.075873 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 13:30:39.079457 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 13:30:39.082743 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4068 13:30:39.085970 Total UI for P1: 0, mck2ui 16
4069 13:30:39.089197 best dqsien dly found for B0: ( 0, 13, 14)
4070 13:30:39.095797 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4071 13:30:39.096006 Total UI for P1: 0, mck2ui 16
4072 13:30:39.102308 best dqsien dly found for B1: ( 0, 13, 16)
4073 13:30:39.105327 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4074 13:30:39.109000 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4075 13:30:39.109157
4076 13:30:39.112091 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4077 13:30:39.115660 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4078 13:30:39.118819 [Gating] SW calibration Done
4079 13:30:39.118966 ==
4080 13:30:39.121928 Dram Type= 6, Freq= 0, CH_0, rank 0
4081 13:30:39.125691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4082 13:30:39.125836 ==
4083 13:30:39.128623 RX Vref Scan: 0
4084 13:30:39.128744
4085 13:30:39.132126 RX Vref 0 -> 0, step: 1
4086 13:30:39.132244
4087 13:30:39.132342 RX Delay -230 -> 252, step: 16
4088 13:30:39.138713 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4089 13:30:39.142094 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4090 13:30:39.145359 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4091 13:30:39.148343 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4092 13:30:39.154768 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4093 13:30:39.158218 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4094 13:30:39.161808 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4095 13:30:39.164886 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4096 13:30:39.171599 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4097 13:30:39.174615 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4098 13:30:39.178328 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4099 13:30:39.181455 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4100 13:30:39.188098 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4101 13:30:39.190968 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4102 13:30:39.194484 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4103 13:30:39.197798 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4104 13:30:39.197924 ==
4105 13:30:39.201284 Dram Type= 6, Freq= 0, CH_0, rank 0
4106 13:30:39.207602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4107 13:30:39.207718 ==
4108 13:30:39.207791 DQS Delay:
4109 13:30:39.211293 DQS0 = 0, DQS1 = 0
4110 13:30:39.211380 DQM Delay:
4111 13:30:39.211447 DQM0 = 43, DQM1 = 33
4112 13:30:39.214190 DQ Delay:
4113 13:30:39.217978 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4114 13:30:39.221120 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4115 13:30:39.224017 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4116 13:30:39.227075 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4117 13:30:39.227170
4118 13:30:39.227238
4119 13:30:39.227300 ==
4120 13:30:39.230719 Dram Type= 6, Freq= 0, CH_0, rank 0
4121 13:30:39.233828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4122 13:30:39.233921 ==
4123 13:30:39.233989
4124 13:30:39.234051
4125 13:30:39.237284 TX Vref Scan disable
4126 13:30:39.240255 == TX Byte 0 ==
4127 13:30:39.243835 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4128 13:30:39.246827 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4129 13:30:39.250432 == TX Byte 1 ==
4130 13:30:39.253657 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4131 13:30:39.256956 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4132 13:30:39.257055 ==
4133 13:30:39.260555 Dram Type= 6, Freq= 0, CH_0, rank 0
4134 13:30:39.266716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4135 13:30:39.266829 ==
4136 13:30:39.266900
4137 13:30:39.266963
4138 13:30:39.267023 TX Vref Scan disable
4139 13:30:39.270884 == TX Byte 0 ==
4140 13:30:39.274521 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4141 13:30:39.280711 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4142 13:30:39.280823 == TX Byte 1 ==
4143 13:30:39.284449 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4144 13:30:39.291100 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4145 13:30:39.291214
4146 13:30:39.291283 [DATLAT]
4147 13:30:39.291346 Freq=600, CH0 RK0
4148 13:30:39.291406
4149 13:30:39.294011 DATLAT Default: 0x9
4150 13:30:39.297725 0, 0xFFFF, sum = 0
4151 13:30:39.297850 1, 0xFFFF, sum = 0
4152 13:30:39.300768 2, 0xFFFF, sum = 0
4153 13:30:39.300891 3, 0xFFFF, sum = 0
4154 13:30:39.303986 4, 0xFFFF, sum = 0
4155 13:30:39.304074 5, 0xFFFF, sum = 0
4156 13:30:39.307471 6, 0xFFFF, sum = 0
4157 13:30:39.307591 7, 0xFFFF, sum = 0
4158 13:30:39.310377 8, 0x0, sum = 1
4159 13:30:39.310486 9, 0x0, sum = 2
4160 13:30:39.313681 10, 0x0, sum = 3
4161 13:30:39.313795 11, 0x0, sum = 4
4162 13:30:39.313901 best_step = 9
4163 13:30:39.313994
4164 13:30:39.316939 ==
4165 13:30:39.320594 Dram Type= 6, Freq= 0, CH_0, rank 0
4166 13:30:39.323567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4167 13:30:39.323680 ==
4168 13:30:39.323777 RX Vref Scan: 1
4169 13:30:39.323868
4170 13:30:39.327192 RX Vref 0 -> 0, step: 1
4171 13:30:39.327271
4172 13:30:39.330132 RX Delay -195 -> 252, step: 8
4173 13:30:39.330241
4174 13:30:39.333917 Set Vref, RX VrefLevel [Byte0]: 55
4175 13:30:39.336867 [Byte1]: 43
4176 13:30:39.336978
4177 13:30:39.340360 Final RX Vref Byte 0 = 55 to rank0
4178 13:30:39.343219 Final RX Vref Byte 1 = 43 to rank0
4179 13:30:39.346964 Final RX Vref Byte 0 = 55 to rank1
4180 13:30:39.349840 Final RX Vref Byte 1 = 43 to rank1==
4181 13:30:39.353476 Dram Type= 6, Freq= 0, CH_0, rank 0
4182 13:30:39.359900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4183 13:30:39.360018 ==
4184 13:30:39.360088 DQS Delay:
4185 13:30:39.360150 DQS0 = 0, DQS1 = 0
4186 13:30:39.363462 DQM Delay:
4187 13:30:39.363538 DQM0 = 41, DQM1 = 34
4188 13:30:39.366676 DQ Delay:
4189 13:30:39.369736 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =36
4190 13:30:39.373173 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =44
4191 13:30:39.376610 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =28
4192 13:30:39.379571 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4193 13:30:39.379660
4194 13:30:39.379729
4195 13:30:39.386300 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c43, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
4196 13:30:39.389514 CH0 RK0: MR19=808, MR18=4C43
4197 13:30:39.396164 CH0_RK0: MR19=0x808, MR18=0x4C43, DQSOSC=395, MR23=63, INC=168, DEC=112
4198 13:30:39.396268
4199 13:30:39.399597 ----->DramcWriteLeveling(PI) begin...
4200 13:30:39.399708 ==
4201 13:30:39.402594 Dram Type= 6, Freq= 0, CH_0, rank 1
4202 13:30:39.405573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4203 13:30:39.405657 ==
4204 13:30:39.408959 Write leveling (Byte 0): 36 => 36
4205 13:30:39.412312 Write leveling (Byte 1): 30 => 30
4206 13:30:39.415796 DramcWriteLeveling(PI) end<-----
4207 13:30:39.415921
4208 13:30:39.416008 ==
4209 13:30:39.418820 Dram Type= 6, Freq= 0, CH_0, rank 1
4210 13:30:39.422074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4211 13:30:39.425927 ==
4212 13:30:39.426031 [Gating] SW mode calibration
4213 13:30:39.435129 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4214 13:30:39.438799 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4215 13:30:39.441795 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4216 13:30:39.448852 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4217 13:30:39.451752 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4218 13:30:39.455439 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
4219 13:30:39.462090 0 9 16 | B1->B0 | 2f2f 2424 | 0 0 | (1 1) (0 0)
4220 13:30:39.465042 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4221 13:30:39.468794 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4222 13:30:39.474751 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 13:30:39.477954 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 13:30:39.481879 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 13:30:39.488152 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 13:30:39.491305 0 10 12 | B1->B0 | 2323 3433 | 0 1 | (0 0) (0 0)
4227 13:30:39.494969 0 10 16 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
4228 13:30:39.501694 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 13:30:39.504658 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 13:30:39.507790 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 13:30:39.514994 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 13:30:39.517712 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 13:30:39.521177 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4234 13:30:39.527678 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4235 13:30:39.531131 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4236 13:30:39.534181 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 13:30:39.540818 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 13:30:39.544469 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 13:30:39.547352 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 13:30:39.553991 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 13:30:39.557586 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 13:30:39.560533 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 13:30:39.567000 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 13:30:39.570624 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 13:30:39.573696 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 13:30:39.580240 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 13:30:39.583498 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 13:30:39.587372 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 13:30:39.593808 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 13:30:39.596699 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4251 13:30:39.599830 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4252 13:30:39.603530 Total UI for P1: 0, mck2ui 16
4253 13:30:39.606395 best dqsien dly found for B0: ( 0, 13, 12)
4254 13:30:39.613124 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4255 13:30:39.616840 Total UI for P1: 0, mck2ui 16
4256 13:30:39.619772 best dqsien dly found for B1: ( 0, 13, 16)
4257 13:30:39.623333 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4258 13:30:39.626617 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4259 13:30:39.626757
4260 13:30:39.629806 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4261 13:30:39.632974 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4262 13:30:39.636381 [Gating] SW calibration Done
4263 13:30:39.636496 ==
4264 13:30:39.639245 Dram Type= 6, Freq= 0, CH_0, rank 1
4265 13:30:39.642477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4266 13:30:39.646342 ==
4267 13:30:39.646482 RX Vref Scan: 0
4268 13:30:39.646588
4269 13:30:39.649438 RX Vref 0 -> 0, step: 1
4270 13:30:39.649557
4271 13:30:39.652536 RX Delay -230 -> 252, step: 16
4272 13:30:39.656040 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4273 13:30:39.659085 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4274 13:30:39.662650 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4275 13:30:39.669195 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4276 13:30:39.672255 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4277 13:30:39.676021 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4278 13:30:39.678902 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4279 13:30:39.682720 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4280 13:30:39.688840 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4281 13:30:39.692205 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4282 13:30:39.695672 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4283 13:30:39.698974 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4284 13:30:39.705067 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4285 13:30:39.708536 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4286 13:30:39.712111 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4287 13:30:39.715032 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4288 13:30:39.718803 ==
4289 13:30:39.721905 Dram Type= 6, Freq= 0, CH_0, rank 1
4290 13:30:39.725388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4291 13:30:39.725507 ==
4292 13:30:39.725611 DQS Delay:
4293 13:30:39.728473 DQS0 = 0, DQS1 = 0
4294 13:30:39.728581 DQM Delay:
4295 13:30:39.731884 DQM0 = 40, DQM1 = 34
4296 13:30:39.731996 DQ Delay:
4297 13:30:39.735224 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4298 13:30:39.738075 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4299 13:30:39.741820 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =25
4300 13:30:39.744772 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4301 13:30:39.744898
4302 13:30:39.744997
4303 13:30:39.745094 ==
4304 13:30:39.748444 Dram Type= 6, Freq= 0, CH_0, rank 1
4305 13:30:39.751731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4306 13:30:39.751853 ==
4307 13:30:39.751953
4308 13:30:39.752048
4309 13:30:39.754985 TX Vref Scan disable
4310 13:30:39.758376 == TX Byte 0 ==
4311 13:30:39.761390 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
4312 13:30:39.764471 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
4313 13:30:39.767977 == TX Byte 1 ==
4314 13:30:39.771558 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4315 13:30:39.774676 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4316 13:30:39.774800 ==
4317 13:30:39.777737 Dram Type= 6, Freq= 0, CH_0, rank 1
4318 13:30:39.784458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4319 13:30:39.784593 ==
4320 13:30:39.784700
4321 13:30:39.784793
4322 13:30:39.784888 TX Vref Scan disable
4323 13:30:39.789286 == TX Byte 0 ==
4324 13:30:39.792384 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
4325 13:30:39.798812 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
4326 13:30:39.798957 == TX Byte 1 ==
4327 13:30:39.802355 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4328 13:30:39.808791 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4329 13:30:39.808925
4330 13:30:39.809027 [DATLAT]
4331 13:30:39.809122 Freq=600, CH0 RK1
4332 13:30:39.809231
4333 13:30:39.812188 DATLAT Default: 0x9
4334 13:30:39.815641 0, 0xFFFF, sum = 0
4335 13:30:39.815755 1, 0xFFFF, sum = 0
4336 13:30:39.818930 2, 0xFFFF, sum = 0
4337 13:30:39.819043 3, 0xFFFF, sum = 0
4338 13:30:39.821925 4, 0xFFFF, sum = 0
4339 13:30:39.822045 5, 0xFFFF, sum = 0
4340 13:30:39.825034 6, 0xFFFF, sum = 0
4341 13:30:39.825150 7, 0xFFFF, sum = 0
4342 13:30:39.828775 8, 0x0, sum = 1
4343 13:30:39.828905 9, 0x0, sum = 2
4344 13:30:39.831793 10, 0x0, sum = 3
4345 13:30:39.831915 11, 0x0, sum = 4
4346 13:30:39.832015 best_step = 9
4347 13:30:39.834851
4348 13:30:39.834950 ==
4349 13:30:39.838397 Dram Type= 6, Freq= 0, CH_0, rank 1
4350 13:30:39.841851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 13:30:39.841992 ==
4352 13:30:39.842099 RX Vref Scan: 0
4353 13:30:39.842210
4354 13:30:39.845181 RX Vref 0 -> 0, step: 1
4355 13:30:39.845301
4356 13:30:39.848256 RX Delay -195 -> 252, step: 8
4357 13:30:39.854916 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4358 13:30:39.857990 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4359 13:30:39.861212 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4360 13:30:39.864518 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4361 13:30:39.871215 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4362 13:30:39.874145 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4363 13:30:39.877730 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4364 13:30:39.880886 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4365 13:30:39.887685 iDelay=205, Bit 8, Center 24 (-123 ~ 172) 296
4366 13:30:39.890734 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4367 13:30:39.893886 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4368 13:30:39.897591 iDelay=205, Bit 11, Center 28 (-115 ~ 172) 288
4369 13:30:39.903824 iDelay=205, Bit 12, Center 36 (-115 ~ 188) 304
4370 13:30:39.907352 iDelay=205, Bit 13, Center 40 (-107 ~ 188) 296
4371 13:30:39.910783 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4372 13:30:39.913822 iDelay=205, Bit 15, Center 40 (-107 ~ 188) 296
4373 13:30:39.913949 ==
4374 13:30:39.916921 Dram Type= 6, Freq= 0, CH_0, rank 1
4375 13:30:39.923609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4376 13:30:39.923741 ==
4377 13:30:39.923841 DQS Delay:
4378 13:30:39.926990 DQS0 = 0, DQS1 = 0
4379 13:30:39.927096 DQM Delay:
4380 13:30:39.927164 DQM0 = 41, DQM1 = 34
4381 13:30:39.930536 DQ Delay:
4382 13:30:39.933574 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4383 13:30:39.937421 DQ4 =44, DQ5 =28, DQ6 =52, DQ7 =48
4384 13:30:39.940320 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =28
4385 13:30:39.943589 DQ12 =36, DQ13 =40, DQ14 =48, DQ15 =40
4386 13:30:39.943713
4387 13:30:39.943810
4388 13:30:39.949925 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e39, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
4389 13:30:39.953585 CH0 RK1: MR19=808, MR18=3E39
4390 13:30:39.959669 CH0_RK1: MR19=0x808, MR18=0x3E39, DQSOSC=398, MR23=63, INC=165, DEC=110
4391 13:30:39.963339 [RxdqsGatingPostProcess] freq 600
4392 13:30:39.966388 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4393 13:30:39.969737 Pre-setting of DQS Precalculation
4394 13:30:39.976231 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4395 13:30:39.976361 ==
4396 13:30:39.980005 Dram Type= 6, Freq= 0, CH_1, rank 0
4397 13:30:39.982845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4398 13:30:39.982964 ==
4399 13:30:39.989704 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4400 13:30:39.996415 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4401 13:30:39.999338 [CA 0] Center 36 (6~66) winsize 61
4402 13:30:40.003037 [CA 1] Center 36 (6~66) winsize 61
4403 13:30:40.006560 [CA 2] Center 34 (4~65) winsize 62
4404 13:30:40.009771 [CA 3] Center 34 (3~65) winsize 63
4405 13:30:40.012937 [CA 4] Center 34 (4~65) winsize 62
4406 13:30:40.016357 [CA 5] Center 34 (4~65) winsize 62
4407 13:30:40.016476
4408 13:30:40.019429 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4409 13:30:40.019539
4410 13:30:40.022396 [CATrainingPosCal] consider 1 rank data
4411 13:30:40.026144 u2DelayCellTimex100 = 270/100 ps
4412 13:30:40.028954 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4413 13:30:40.032801 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4414 13:30:40.035617 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4415 13:30:40.039327 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4416 13:30:40.042443 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4417 13:30:40.045671 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4418 13:30:40.045791
4419 13:30:40.052565 CA PerBit enable=1, Macro0, CA PI delay=34
4420 13:30:40.052696
4421 13:30:40.055437 [CBTSetCACLKResult] CA Dly = 34
4422 13:30:40.055577 CS Dly: 4 (0~35)
4423 13:30:40.055675 ==
4424 13:30:40.058893 Dram Type= 6, Freq= 0, CH_1, rank 1
4425 13:30:40.062101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4426 13:30:40.062223 ==
4427 13:30:40.069195 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4428 13:30:40.075206 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4429 13:30:40.078959 [CA 0] Center 36 (6~66) winsize 61
4430 13:30:40.081785 [CA 1] Center 36 (6~66) winsize 61
4431 13:30:40.085168 [CA 2] Center 34 (4~65) winsize 62
4432 13:30:40.088812 [CA 3] Center 34 (3~65) winsize 63
4433 13:30:40.091878 [CA 4] Center 34 (4~64) winsize 61
4434 13:30:40.095343 [CA 5] Center 33 (3~64) winsize 62
4435 13:30:40.095462
4436 13:30:40.098597 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4437 13:30:40.098713
4438 13:30:40.101736 [CATrainingPosCal] consider 2 rank data
4439 13:30:40.104886 u2DelayCellTimex100 = 270/100 ps
4440 13:30:40.108378 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4441 13:30:40.111604 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4442 13:30:40.115297 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4443 13:30:40.121569 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4444 13:30:40.124558 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
4445 13:30:40.128271 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4446 13:30:40.128394
4447 13:30:40.131239 CA PerBit enable=1, Macro0, CA PI delay=34
4448 13:30:40.131349
4449 13:30:40.134784 [CBTSetCACLKResult] CA Dly = 34
4450 13:30:40.134900 CS Dly: 5 (0~38)
4451 13:30:40.134998
4452 13:30:40.137794 ----->DramcWriteLeveling(PI) begin...
4453 13:30:40.141136 ==
4454 13:30:40.144294 Dram Type= 6, Freq= 0, CH_1, rank 0
4455 13:30:40.147886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4456 13:30:40.147995 ==
4457 13:30:40.150991 Write leveling (Byte 0): 30 => 30
4458 13:30:40.154097 Write leveling (Byte 1): 30 => 30
4459 13:30:40.157802 DramcWriteLeveling(PI) end<-----
4460 13:30:40.157916
4461 13:30:40.158011 ==
4462 13:30:40.160938 Dram Type= 6, Freq= 0, CH_1, rank 0
4463 13:30:40.164433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4464 13:30:40.164545 ==
4465 13:30:40.167405 [Gating] SW mode calibration
4466 13:30:40.174155 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4467 13:30:40.180473 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4468 13:30:40.184071 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4469 13:30:40.187083 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4470 13:30:40.193792 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4471 13:30:40.197301 0 9 12 | B1->B0 | 3131 2f2f | 0 0 | (0 0) (0 1)
4472 13:30:40.200515 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 13:30:40.207254 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 13:30:40.210044 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 13:30:40.213513 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 13:30:40.219764 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 13:30:40.223557 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 13:30:40.226310 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 13:30:40.233336 0 10 12 | B1->B0 | 3030 3232 | 1 0 | (0 0) (0 0)
4480 13:30:40.236445 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 13:30:40.239683 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 13:30:40.246320 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 13:30:40.249693 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 13:30:40.252814 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 13:30:40.259317 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 13:30:40.263007 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 13:30:40.265904 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4488 13:30:40.272745 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 13:30:40.275874 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 13:30:40.279052 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 13:30:40.285596 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 13:30:40.289215 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 13:30:40.292444 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 13:30:40.298811 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 13:30:40.301842 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 13:30:40.305482 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 13:30:40.311876 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 13:30:40.315056 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 13:30:40.318435 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 13:30:40.325134 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 13:30:40.328215 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 13:30:40.331826 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 13:30:40.338344 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4504 13:30:40.341410 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 13:30:40.345172 Total UI for P1: 0, mck2ui 16
4506 13:30:40.348200 best dqsien dly found for B0: ( 0, 13, 14)
4507 13:30:40.351500 Total UI for P1: 0, mck2ui 16
4508 13:30:40.354798 best dqsien dly found for B1: ( 0, 13, 12)
4509 13:30:40.357885 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4510 13:30:40.361366 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4511 13:30:40.361497
4512 13:30:40.364434 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4513 13:30:40.371017 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4514 13:30:40.371162 [Gating] SW calibration Done
4515 13:30:40.374786 ==
4516 13:30:40.374880 Dram Type= 6, Freq= 0, CH_1, rank 0
4517 13:30:40.381535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4518 13:30:40.381651 ==
4519 13:30:40.381746 RX Vref Scan: 0
4520 13:30:40.381831
4521 13:30:40.384392 RX Vref 0 -> 0, step: 1
4522 13:30:40.384481
4523 13:30:40.387801 RX Delay -230 -> 252, step: 16
4524 13:30:40.390762 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4525 13:30:40.394434 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4526 13:30:40.400959 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4527 13:30:40.404031 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4528 13:30:40.407077 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4529 13:30:40.410576 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4530 13:30:40.417287 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4531 13:30:40.420257 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4532 13:30:40.423801 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4533 13:30:40.427274 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4534 13:30:40.433403 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4535 13:30:40.436806 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4536 13:30:40.440467 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4537 13:30:40.443355 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4538 13:30:40.450179 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4539 13:30:40.453223 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4540 13:30:40.453351 ==
4541 13:30:40.456660 Dram Type= 6, Freq= 0, CH_1, rank 0
4542 13:30:40.460189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4543 13:30:40.460311 ==
4544 13:30:40.463166 DQS Delay:
4545 13:30:40.463249 DQS0 = 0, DQS1 = 0
4546 13:30:40.463359 DQM Delay:
4547 13:30:40.466736 DQM0 = 45, DQM1 = 39
4548 13:30:40.466854 DQ Delay:
4549 13:30:40.469826 DQ0 =57, DQ1 =41, DQ2 =25, DQ3 =41
4550 13:30:40.473383 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4551 13:30:40.476332 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =41
4552 13:30:40.479873 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4553 13:30:40.479995
4554 13:30:40.480086
4555 13:30:40.480151 ==
4556 13:30:40.482901 Dram Type= 6, Freq= 0, CH_1, rank 0
4557 13:30:40.489762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4558 13:30:40.489891 ==
4559 13:30:40.489991
4560 13:30:40.490092
4561 13:30:40.490182 TX Vref Scan disable
4562 13:30:40.493138 == TX Byte 0 ==
4563 13:30:40.496693 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4564 13:30:40.503374 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4565 13:30:40.503513 == TX Byte 1 ==
4566 13:30:40.506269 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4567 13:30:40.513173 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4568 13:30:40.513306 ==
4569 13:30:40.516181 Dram Type= 6, Freq= 0, CH_1, rank 0
4570 13:30:40.519790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4571 13:30:40.519913 ==
4572 13:30:40.520002
4573 13:30:40.520065
4574 13:30:40.522866 TX Vref Scan disable
4575 13:30:40.526503 == TX Byte 0 ==
4576 13:30:40.529600 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4577 13:30:40.532560 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4578 13:30:40.535961 == TX Byte 1 ==
4579 13:30:40.539369 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4580 13:30:40.542592 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4581 13:30:40.542715
4582 13:30:40.546038 [DATLAT]
4583 13:30:40.546164 Freq=600, CH1 RK0
4584 13:30:40.546274
4585 13:30:40.549103 DATLAT Default: 0x9
4586 13:30:40.549214 0, 0xFFFF, sum = 0
4587 13:30:40.552600 1, 0xFFFF, sum = 0
4588 13:30:40.552713 2, 0xFFFF, sum = 0
4589 13:30:40.555828 3, 0xFFFF, sum = 0
4590 13:30:40.555949 4, 0xFFFF, sum = 0
4591 13:30:40.558728 5, 0xFFFF, sum = 0
4592 13:30:40.558843 6, 0xFFFF, sum = 0
4593 13:30:40.562405 7, 0xFFFF, sum = 0
4594 13:30:40.562510 8, 0x0, sum = 1
4595 13:30:40.565550 9, 0x0, sum = 2
4596 13:30:40.565664 10, 0x0, sum = 3
4597 13:30:40.568665 11, 0x0, sum = 4
4598 13:30:40.568756 best_step = 9
4599 13:30:40.568849
4600 13:30:40.568930 ==
4601 13:30:40.572061 Dram Type= 6, Freq= 0, CH_1, rank 0
4602 13:30:40.575144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4603 13:30:40.578660 ==
4604 13:30:40.578775 RX Vref Scan: 1
4605 13:30:40.578885
4606 13:30:40.582159 RX Vref 0 -> 0, step: 1
4607 13:30:40.582246
4608 13:30:40.585292 RX Delay -195 -> 252, step: 8
4609 13:30:40.585376
4610 13:30:40.588460 Set Vref, RX VrefLevel [Byte0]: 51
4611 13:30:40.591751 [Byte1]: 58
4612 13:30:40.591879
4613 13:30:40.595261 Final RX Vref Byte 0 = 51 to rank0
4614 13:30:40.598364 Final RX Vref Byte 1 = 58 to rank0
4615 13:30:40.601680 Final RX Vref Byte 0 = 51 to rank1
4616 13:30:40.605026 Final RX Vref Byte 1 = 58 to rank1==
4617 13:30:40.608150 Dram Type= 6, Freq= 0, CH_1, rank 0
4618 13:30:40.611659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4619 13:30:40.611788 ==
4620 13:30:40.614771 DQS Delay:
4621 13:30:40.614885 DQS0 = 0, DQS1 = 0
4622 13:30:40.614992 DQM Delay:
4623 13:30:40.617848 DQM0 = 46, DQM1 = 38
4624 13:30:40.617959 DQ Delay:
4625 13:30:40.621675 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4626 13:30:40.624577 DQ4 =40, DQ5 =52, DQ6 =60, DQ7 =40
4627 13:30:40.627706 DQ8 =24, DQ9 =28, DQ10 =40, DQ11 =28
4628 13:30:40.631639 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =44
4629 13:30:40.631757
4630 13:30:40.631870
4631 13:30:40.641149 [DQSOSCAuto] RK0, (LSB)MR18= 0x253e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 402 ps
4632 13:30:40.644569 CH1 RK0: MR19=808, MR18=253E
4633 13:30:40.647966 CH1_RK0: MR19=0x808, MR18=0x253E, DQSOSC=398, MR23=63, INC=165, DEC=110
4634 13:30:40.650729
4635 13:30:40.654043 ----->DramcWriteLeveling(PI) begin...
4636 13:30:40.654168 ==
4637 13:30:40.657525 Dram Type= 6, Freq= 0, CH_1, rank 1
4638 13:30:40.661216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4639 13:30:40.661331 ==
4640 13:30:40.664184 Write leveling (Byte 0): 27 => 27
4641 13:30:40.667822 Write leveling (Byte 1): 27 => 27
4642 13:30:40.670794 DramcWriteLeveling(PI) end<-----
4643 13:30:40.670918
4644 13:30:40.671027 ==
4645 13:30:40.673793 Dram Type= 6, Freq= 0, CH_1, rank 1
4646 13:30:40.677389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4647 13:30:40.677514 ==
4648 13:30:40.680438 [Gating] SW mode calibration
4649 13:30:40.687473 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4650 13:30:40.693464 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4651 13:30:40.696768 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4652 13:30:40.700107 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4653 13:30:40.706694 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4654 13:30:40.710219 0 9 12 | B1->B0 | 3232 2e2e | 1 0 | (1 0) (0 0)
4655 13:30:40.713215 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4656 13:30:40.719806 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4657 13:30:40.723593 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4658 13:30:40.726612 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4659 13:30:40.733196 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4660 13:30:40.736051 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4661 13:30:40.742935 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
4662 13:30:40.745799 0 10 12 | B1->B0 | 3333 4040 | 0 1 | (0 0) (0 0)
4663 13:30:40.749341 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 13:30:40.755871 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4665 13:30:40.758974 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4666 13:30:40.762625 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4667 13:30:40.768706 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 13:30:40.772355 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 13:30:40.775811 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 13:30:40.782620 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4671 13:30:40.785841 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 13:30:40.788781 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 13:30:40.795591 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 13:30:40.798454 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 13:30:40.801726 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 13:30:40.808546 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 13:30:40.811649 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 13:30:40.815015 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 13:30:40.821700 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 13:30:40.825004 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 13:30:40.827949 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 13:30:40.834671 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 13:30:40.838091 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 13:30:40.841151 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 13:30:40.847708 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4686 13:30:40.851330 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4687 13:30:40.854413 Total UI for P1: 0, mck2ui 16
4688 13:30:40.857438 best dqsien dly found for B0: ( 0, 13, 8)
4689 13:30:40.861210 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4690 13:30:40.864201 Total UI for P1: 0, mck2ui 16
4691 13:30:40.867236 best dqsien dly found for B1: ( 0, 13, 10)
4692 13:30:40.870651 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4693 13:30:40.873791 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4694 13:30:40.876981
4695 13:30:40.880406 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4696 13:30:40.883672 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4697 13:30:40.887401 [Gating] SW calibration Done
4698 13:30:40.887516 ==
4699 13:30:40.890350 Dram Type= 6, Freq= 0, CH_1, rank 1
4700 13:30:40.893976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4701 13:30:40.894094 ==
4702 13:30:40.894202 RX Vref Scan: 0
4703 13:30:40.897062
4704 13:30:40.897175 RX Vref 0 -> 0, step: 1
4705 13:30:40.897273
4706 13:30:40.900085 RX Delay -230 -> 252, step: 16
4707 13:30:40.903747 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4708 13:30:40.909988 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4709 13:30:40.913401 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4710 13:30:40.916798 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4711 13:30:40.920400 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4712 13:30:40.923434 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4713 13:30:40.929892 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4714 13:30:40.933014 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4715 13:30:40.936426 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4716 13:30:40.940097 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4717 13:30:40.946607 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4718 13:30:40.949704 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4719 13:30:40.953283 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4720 13:30:40.956382 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4721 13:30:40.962632 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4722 13:30:40.966217 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4723 13:30:40.966315 ==
4724 13:30:40.969189 Dram Type= 6, Freq= 0, CH_1, rank 1
4725 13:30:40.972806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4726 13:30:40.972932 ==
4727 13:30:40.975803 DQS Delay:
4728 13:30:40.975924 DQS0 = 0, DQS1 = 0
4729 13:30:40.979441 DQM Delay:
4730 13:30:40.979547 DQM0 = 41, DQM1 = 40
4731 13:30:40.979649 DQ Delay:
4732 13:30:40.982821 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41
4733 13:30:40.986236 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4734 13:30:40.989159 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4735 13:30:40.992485 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4736 13:30:40.992619
4737 13:30:40.992717
4738 13:30:40.995753 ==
4739 13:30:40.998857 Dram Type= 6, Freq= 0, CH_1, rank 1
4740 13:30:41.002700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4741 13:30:41.002829 ==
4742 13:30:41.002934
4743 13:30:41.003006
4744 13:30:41.005792 TX Vref Scan disable
4745 13:30:41.005895 == TX Byte 0 ==
4746 13:30:41.012312 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4747 13:30:41.015722 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4748 13:30:41.015849 == TX Byte 1 ==
4749 13:30:41.022034 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4750 13:30:41.025666 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4751 13:30:41.025787 ==
4752 13:30:41.028692 Dram Type= 6, Freq= 0, CH_1, rank 1
4753 13:30:41.032285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4754 13:30:41.032368 ==
4755 13:30:41.032433
4756 13:30:41.032511
4757 13:30:41.035267 TX Vref Scan disable
4758 13:30:41.038854 == TX Byte 0 ==
4759 13:30:41.042208 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4760 13:30:41.044923 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4761 13:30:41.048428 == TX Byte 1 ==
4762 13:30:41.051605 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4763 13:30:41.055247 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4764 13:30:41.055340
4765 13:30:41.058163 [DATLAT]
4766 13:30:41.058255 Freq=600, CH1 RK1
4767 13:30:41.058345
4768 13:30:41.061820 DATLAT Default: 0x9
4769 13:30:41.061911 0, 0xFFFF, sum = 0
4770 13:30:41.064951 1, 0xFFFF, sum = 0
4771 13:30:41.065043 2, 0xFFFF, sum = 0
4772 13:30:41.068004 3, 0xFFFF, sum = 0
4773 13:30:41.071655 4, 0xFFFF, sum = 0
4774 13:30:41.071751 5, 0xFFFF, sum = 0
4775 13:30:41.074594 6, 0xFFFF, sum = 0
4776 13:30:41.074686 7, 0xFFFF, sum = 0
4777 13:30:41.078305 8, 0x0, sum = 1
4778 13:30:41.078396 9, 0x0, sum = 2
4779 13:30:41.078487 10, 0x0, sum = 3
4780 13:30:41.081438 11, 0x0, sum = 4
4781 13:30:41.081528 best_step = 9
4782 13:30:41.081617
4783 13:30:41.081701 ==
4784 13:30:41.084280 Dram Type= 6, Freq= 0, CH_1, rank 1
4785 13:30:41.091064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4786 13:30:41.091202 ==
4787 13:30:41.091309 RX Vref Scan: 0
4788 13:30:41.091405
4789 13:30:41.094135 RX Vref 0 -> 0, step: 1
4790 13:30:41.094247
4791 13:30:41.097758 RX Delay -179 -> 252, step: 8
4792 13:30:41.101000 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4793 13:30:41.107696 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4794 13:30:41.110646 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4795 13:30:41.114260 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4796 13:30:41.117620 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4797 13:30:41.124210 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4798 13:30:41.127155 iDelay=205, Bit 6, Center 48 (-99 ~ 196) 296
4799 13:30:41.130655 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4800 13:30:41.133630 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4801 13:30:41.140580 iDelay=205, Bit 9, Center 28 (-123 ~ 180) 304
4802 13:30:41.143602 iDelay=205, Bit 10, Center 44 (-107 ~ 196) 304
4803 13:30:41.147192 iDelay=205, Bit 11, Center 32 (-123 ~ 188) 312
4804 13:30:41.150525 iDelay=205, Bit 12, Center 48 (-107 ~ 204) 312
4805 13:30:41.156693 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4806 13:30:41.160170 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4807 13:30:41.163822 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4808 13:30:41.163936 ==
4809 13:30:41.166786 Dram Type= 6, Freq= 0, CH_1, rank 1
4810 13:30:41.170531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4811 13:30:41.170638 ==
4812 13:30:41.173472 DQS Delay:
4813 13:30:41.173583 DQS0 = 0, DQS1 = 0
4814 13:30:41.176590 DQM Delay:
4815 13:30:41.176708 DQM0 = 41, DQM1 = 39
4816 13:30:41.180354 DQ Delay:
4817 13:30:41.180432 DQ0 =44, DQ1 =40, DQ2 =32, DQ3 =40
4818 13:30:41.183149 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36
4819 13:30:41.186220 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4820 13:30:41.189901 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =44
4821 13:30:41.190012
4822 13:30:41.192951
4823 13:30:41.199492 [DQSOSCAuto] RK1, (LSB)MR18= 0x3155, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4824 13:30:41.203255 CH1 RK1: MR19=808, MR18=3155
4825 13:30:41.209459 CH1_RK1: MR19=0x808, MR18=0x3155, DQSOSC=393, MR23=63, INC=169, DEC=113
4826 13:30:41.212914 [RxdqsGatingPostProcess] freq 600
4827 13:30:41.215889 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4828 13:30:41.219565 Pre-setting of DQS Precalculation
4829 13:30:41.226186 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4830 13:30:41.232671 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4831 13:30:41.239116 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4832 13:30:41.239241
4833 13:30:41.239341
4834 13:30:41.242699 [Calibration Summary] 1200 Mbps
4835 13:30:41.242814 CH 0, Rank 0
4836 13:30:41.245565 SW Impedance : PASS
4837 13:30:41.249120 DUTY Scan : NO K
4838 13:30:41.249231 ZQ Calibration : PASS
4839 13:30:41.252215 Jitter Meter : NO K
4840 13:30:41.255335 CBT Training : PASS
4841 13:30:41.255449 Write leveling : PASS
4842 13:30:41.258856 RX DQS gating : PASS
4843 13:30:41.262030 RX DQ/DQS(RDDQC) : PASS
4844 13:30:41.262146 TX DQ/DQS : PASS
4845 13:30:41.265251 RX DATLAT : PASS
4846 13:30:41.268379 RX DQ/DQS(Engine): PASS
4847 13:30:41.268491 TX OE : NO K
4848 13:30:41.271755 All Pass.
4849 13:30:41.271860
4850 13:30:41.271970 CH 0, Rank 1
4851 13:30:41.275408 SW Impedance : PASS
4852 13:30:41.275516 DUTY Scan : NO K
4853 13:30:41.278499 ZQ Calibration : PASS
4854 13:30:41.281657 Jitter Meter : NO K
4855 13:30:41.281762 CBT Training : PASS
4856 13:30:41.285404 Write leveling : PASS
4857 13:30:41.288976 RX DQS gating : PASS
4858 13:30:41.289086 RX DQ/DQS(RDDQC) : PASS
4859 13:30:41.292067 TX DQ/DQS : PASS
4860 13:30:41.292157 RX DATLAT : PASS
4861 13:30:41.294980 RX DQ/DQS(Engine): PASS
4862 13:30:41.298649 TX OE : NO K
4863 13:30:41.298761 All Pass.
4864 13:30:41.298868
4865 13:30:41.301589 CH 1, Rank 0
4866 13:30:41.301706 SW Impedance : PASS
4867 13:30:41.304598 DUTY Scan : NO K
4868 13:30:41.304706 ZQ Calibration : PASS
4869 13:30:41.308628 Jitter Meter : NO K
4870 13:30:41.311544 CBT Training : PASS
4871 13:30:41.311658 Write leveling : PASS
4872 13:30:41.315073 RX DQS gating : PASS
4873 13:30:41.317905 RX DQ/DQS(RDDQC) : PASS
4874 13:30:41.318009 TX DQ/DQS : PASS
4875 13:30:41.321532 RX DATLAT : PASS
4876 13:30:41.325002 RX DQ/DQS(Engine): PASS
4877 13:30:41.325122 TX OE : NO K
4878 13:30:41.327927 All Pass.
4879 13:30:41.328006
4880 13:30:41.328086 CH 1, Rank 1
4881 13:30:41.331454 SW Impedance : PASS
4882 13:30:41.331564 DUTY Scan : NO K
4883 13:30:41.334462 ZQ Calibration : PASS
4884 13:30:41.338132 Jitter Meter : NO K
4885 13:30:41.338238 CBT Training : PASS
4886 13:30:41.341081 Write leveling : PASS
4887 13:30:41.344480 RX DQS gating : PASS
4888 13:30:41.344587 RX DQ/DQS(RDDQC) : PASS
4889 13:30:41.347430 TX DQ/DQS : PASS
4890 13:30:41.351040 RX DATLAT : PASS
4891 13:30:41.351148 RX DQ/DQS(Engine): PASS
4892 13:30:41.354055 TX OE : NO K
4893 13:30:41.354169 All Pass.
4894 13:30:41.354266
4895 13:30:41.357712 DramC Write-DBI off
4896 13:30:41.360896 PER_BANK_REFRESH: Hybrid Mode
4897 13:30:41.361001 TX_TRACKING: ON
4898 13:30:41.370423 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4899 13:30:41.373783 [FAST_K] Save calibration result to emmc
4900 13:30:41.377192 dramc_set_vcore_voltage set vcore to 662500
4901 13:30:41.380347 Read voltage for 933, 3
4902 13:30:41.380454 Vio18 = 0
4903 13:30:41.380549 Vcore = 662500
4904 13:30:41.383482 Vdram = 0
4905 13:30:41.383585 Vddq = 0
4906 13:30:41.383676 Vmddr = 0
4907 13:30:41.390149 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4908 13:30:41.393525 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4909 13:30:41.397039 MEM_TYPE=3, freq_sel=17
4910 13:30:41.399966 sv_algorithm_assistance_LP4_1600
4911 13:30:41.403193 ============ PULL DRAM RESETB DOWN ============
4912 13:30:41.409622 ========== PULL DRAM RESETB DOWN end =========
4913 13:30:41.413063 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4914 13:30:41.416351 ===================================
4915 13:30:41.419480 LPDDR4 DRAM CONFIGURATION
4916 13:30:41.422859 ===================================
4917 13:30:41.422968 EX_ROW_EN[0] = 0x0
4918 13:30:41.426204 EX_ROW_EN[1] = 0x0
4919 13:30:41.426311 LP4Y_EN = 0x0
4920 13:30:41.429523 WORK_FSP = 0x0
4921 13:30:41.429641 WL = 0x3
4922 13:30:41.432802 RL = 0x3
4923 13:30:41.436219 BL = 0x2
4924 13:30:41.436331 RPST = 0x0
4925 13:30:41.439213 RD_PRE = 0x0
4926 13:30:41.439324 WR_PRE = 0x1
4927 13:30:41.442958 WR_PST = 0x0
4928 13:30:41.443069 DBI_WR = 0x0
4929 13:30:41.445932 DBI_RD = 0x0
4930 13:30:41.446055 OTF = 0x1
4931 13:30:41.449214 ===================================
4932 13:30:41.452678 ===================================
4933 13:30:41.455728 ANA top config
4934 13:30:41.459198 ===================================
4935 13:30:41.459310 DLL_ASYNC_EN = 0
4936 13:30:41.462476 ALL_SLAVE_EN = 1
4937 13:30:41.466144 NEW_RANK_MODE = 1
4938 13:30:41.469029 DLL_IDLE_MODE = 1
4939 13:30:41.472821 LP45_APHY_COMB_EN = 1
4940 13:30:41.472933 TX_ODT_DIS = 1
4941 13:30:41.475859 NEW_8X_MODE = 1
4942 13:30:41.478903 ===================================
4943 13:30:41.482433 ===================================
4944 13:30:41.485324 data_rate = 1866
4945 13:30:41.489201 CKR = 1
4946 13:30:41.492384 DQ_P2S_RATIO = 8
4947 13:30:41.495748 ===================================
4948 13:30:41.495858 CA_P2S_RATIO = 8
4949 13:30:41.498801 DQ_CA_OPEN = 0
4950 13:30:41.501789 DQ_SEMI_OPEN = 0
4951 13:30:41.505658 CA_SEMI_OPEN = 0
4952 13:30:41.508581 CA_FULL_RATE = 0
4953 13:30:41.512408 DQ_CKDIV4_EN = 1
4954 13:30:41.515315 CA_CKDIV4_EN = 1
4955 13:30:41.515422 CA_PREDIV_EN = 0
4956 13:30:41.518348 PH8_DLY = 0
4957 13:30:41.521797 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4958 13:30:41.525016 DQ_AAMCK_DIV = 4
4959 13:30:41.528528 CA_AAMCK_DIV = 4
4960 13:30:41.531439 CA_ADMCK_DIV = 4
4961 13:30:41.531560 DQ_TRACK_CA_EN = 0
4962 13:30:41.534991 CA_PICK = 933
4963 13:30:41.538160 CA_MCKIO = 933
4964 13:30:41.541305 MCKIO_SEMI = 0
4965 13:30:41.544850 PLL_FREQ = 3732
4966 13:30:41.547853 DQ_UI_PI_RATIO = 32
4967 13:30:41.551729 CA_UI_PI_RATIO = 0
4968 13:30:41.554406 ===================================
4969 13:30:41.557736 ===================================
4970 13:30:41.557846 memory_type:LPDDR4
4971 13:30:41.561249 GP_NUM : 10
4972 13:30:41.564788 SRAM_EN : 1
4973 13:30:41.564879 MD32_EN : 0
4974 13:30:41.567687 ===================================
4975 13:30:41.571383 [ANA_INIT] >>>>>>>>>>>>>>
4976 13:30:41.574414 <<<<<< [CONFIGURE PHASE]: ANA_TX
4977 13:30:41.578102 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4978 13:30:41.581121 ===================================
4979 13:30:41.584627 data_rate = 1866,PCW = 0X8f00
4980 13:30:41.587555 ===================================
4981 13:30:41.591089 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4982 13:30:41.594252 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4983 13:30:41.600874 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4984 13:30:41.604277 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4985 13:30:41.611056 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4986 13:30:41.614161 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4987 13:30:41.614275 [ANA_INIT] flow start
4988 13:30:41.616964 [ANA_INIT] PLL >>>>>>>>
4989 13:30:41.620608 [ANA_INIT] PLL <<<<<<<<
4990 13:30:41.620715 [ANA_INIT] MIDPI >>>>>>>>
4991 13:30:41.623574 [ANA_INIT] MIDPI <<<<<<<<
4992 13:30:41.627373 [ANA_INIT] DLL >>>>>>>>
4993 13:30:41.627489 [ANA_INIT] flow end
4994 13:30:41.633478 ============ LP4 DIFF to SE enter ============
4995 13:30:41.637074 ============ LP4 DIFF to SE exit ============
4996 13:30:41.637198 [ANA_INIT] <<<<<<<<<<<<<
4997 13:30:41.640057 [Flow] Enable top DCM control >>>>>
4998 13:30:41.643572 [Flow] Enable top DCM control <<<<<
4999 13:30:41.646935 Enable DLL master slave shuffle
5000 13:30:41.653572 ==============================================================
5001 13:30:41.656581 Gating Mode config
5002 13:30:41.659668 ==============================================================
5003 13:30:41.663323 Config description:
5004 13:30:41.673586 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5005 13:30:41.679589 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5006 13:30:41.683107 SELPH_MODE 0: By rank 1: By Phase
5007 13:30:41.689753 ==============================================================
5008 13:30:41.692635 GAT_TRACK_EN = 1
5009 13:30:41.696350 RX_GATING_MODE = 2
5010 13:30:41.699425 RX_GATING_TRACK_MODE = 2
5011 13:30:41.702847 SELPH_MODE = 1
5012 13:30:41.705702 PICG_EARLY_EN = 1
5013 13:30:41.705804 VALID_LAT_VALUE = 1
5014 13:30:41.712552 ==============================================================
5015 13:30:41.715629 Enter into Gating configuration >>>>
5016 13:30:41.719230 Exit from Gating configuration <<<<
5017 13:30:41.722342 Enter into DVFS_PRE_config >>>>>
5018 13:30:41.732147 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5019 13:30:41.735800 Exit from DVFS_PRE_config <<<<<
5020 13:30:41.738616 Enter into PICG configuration >>>>
5021 13:30:41.741865 Exit from PICG configuration <<<<
5022 13:30:41.745411 [RX_INPUT] configuration >>>>>
5023 13:30:41.748480 [RX_INPUT] configuration <<<<<
5024 13:30:41.755410 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5025 13:30:41.758421 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5026 13:30:41.765053 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5027 13:30:41.771695 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5028 13:30:41.778287 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5029 13:30:41.784526 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5030 13:30:41.788308 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5031 13:30:41.791347 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5032 13:30:41.794438 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5033 13:30:41.800992 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5034 13:30:41.804653 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5035 13:30:41.807709 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5036 13:30:41.811168 ===================================
5037 13:30:41.814802 LPDDR4 DRAM CONFIGURATION
5038 13:30:41.817455 ===================================
5039 13:30:41.820929 EX_ROW_EN[0] = 0x0
5040 13:30:41.821023 EX_ROW_EN[1] = 0x0
5041 13:30:41.824494 LP4Y_EN = 0x0
5042 13:30:41.824577 WORK_FSP = 0x0
5043 13:30:41.827580 WL = 0x3
5044 13:30:41.827662 RL = 0x3
5045 13:30:41.830720 BL = 0x2
5046 13:30:41.830824 RPST = 0x0
5047 13:30:41.834402 RD_PRE = 0x0
5048 13:30:41.834505 WR_PRE = 0x1
5049 13:30:41.837552 WR_PST = 0x0
5050 13:30:41.841131 DBI_WR = 0x0
5051 13:30:41.841238 DBI_RD = 0x0
5052 13:30:41.844159 OTF = 0x1
5053 13:30:41.847696 ===================================
5054 13:30:41.850828 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5055 13:30:41.853688 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5056 13:30:41.857447 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5057 13:30:41.860332 ===================================
5058 13:30:41.863680 LPDDR4 DRAM CONFIGURATION
5059 13:30:41.867038 ===================================
5060 13:30:41.870572 EX_ROW_EN[0] = 0x10
5061 13:30:41.870689 EX_ROW_EN[1] = 0x0
5062 13:30:41.873523 LP4Y_EN = 0x0
5063 13:30:41.873629 WORK_FSP = 0x0
5064 13:30:41.876568 WL = 0x3
5065 13:30:41.876670 RL = 0x3
5066 13:30:41.880183 BL = 0x2
5067 13:30:41.883608 RPST = 0x0
5068 13:30:41.883715 RD_PRE = 0x0
5069 13:30:41.886462 WR_PRE = 0x1
5070 13:30:41.886576 WR_PST = 0x0
5071 13:30:41.889898 DBI_WR = 0x0
5072 13:30:41.890013 DBI_RD = 0x0
5073 13:30:41.893529 OTF = 0x1
5074 13:30:41.896664 ===================================
5075 13:30:41.903186 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5076 13:30:41.906222 nWR fixed to 30
5077 13:30:41.906340 [ModeRegInit_LP4] CH0 RK0
5078 13:30:41.910006 [ModeRegInit_LP4] CH0 RK1
5079 13:30:41.913211 [ModeRegInit_LP4] CH1 RK0
5080 13:30:41.913327 [ModeRegInit_LP4] CH1 RK1
5081 13:30:41.916536 match AC timing 9
5082 13:30:41.919723 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5083 13:30:41.925884 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5084 13:30:41.929354 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5085 13:30:41.935822 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5086 13:30:41.939062 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5087 13:30:41.939147 ==
5088 13:30:41.942512 Dram Type= 6, Freq= 0, CH_0, rank 0
5089 13:30:41.945749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5090 13:30:41.945870 ==
5091 13:30:41.952332 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5092 13:30:41.959310 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5093 13:30:41.962563 [CA 0] Center 37 (7~68) winsize 62
5094 13:30:41.965930 [CA 1] Center 37 (7~68) winsize 62
5095 13:30:41.968656 [CA 2] Center 34 (4~65) winsize 62
5096 13:30:41.971856 [CA 3] Center 34 (4~65) winsize 62
5097 13:30:41.975631 [CA 4] Center 33 (3~63) winsize 61
5098 13:30:41.978907 [CA 5] Center 32 (2~63) winsize 62
5099 13:30:41.978992
5100 13:30:41.982043 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5101 13:30:41.982128
5102 13:30:41.984988 [CATrainingPosCal] consider 1 rank data
5103 13:30:41.988590 u2DelayCellTimex100 = 270/100 ps
5104 13:30:41.991857 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5105 13:30:41.995368 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5106 13:30:41.999016 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5107 13:30:42.001877 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5108 13:30:42.005040 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5109 13:30:42.011627 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5110 13:30:42.011714
5111 13:30:42.014844 CA PerBit enable=1, Macro0, CA PI delay=32
5112 13:30:42.014928
5113 13:30:42.017969 [CBTSetCACLKResult] CA Dly = 32
5114 13:30:42.018053 CS Dly: 5 (0~36)
5115 13:30:42.018119 ==
5116 13:30:42.021467 Dram Type= 6, Freq= 0, CH_0, rank 1
5117 13:30:42.025163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5118 13:30:42.028152 ==
5119 13:30:42.031035 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5120 13:30:42.037779 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5121 13:30:42.041441 [CA 0] Center 37 (7~68) winsize 62
5122 13:30:42.044693 [CA 1] Center 37 (7~68) winsize 62
5123 13:30:42.047775 [CA 2] Center 35 (5~65) winsize 61
5124 13:30:42.050690 [CA 3] Center 34 (4~65) winsize 62
5125 13:30:42.054435 [CA 4] Center 33 (3~64) winsize 62
5126 13:30:42.057470 [CA 5] Center 32 (2~63) winsize 62
5127 13:30:42.057560
5128 13:30:42.060509 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5129 13:30:42.060592
5130 13:30:42.063894 [CATrainingPosCal] consider 2 rank data
5131 13:30:42.067466 u2DelayCellTimex100 = 270/100 ps
5132 13:30:42.070680 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5133 13:30:42.073755 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5134 13:30:42.080823 CA2 delay=35 (5~65),Diff = 3 PI (18 cell)
5135 13:30:42.083895 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5136 13:30:42.086994 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5137 13:30:42.090406 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5138 13:30:42.090522
5139 13:30:42.093417 CA PerBit enable=1, Macro0, CA PI delay=32
5140 13:30:42.093500
5141 13:30:42.096960 [CBTSetCACLKResult] CA Dly = 32
5142 13:30:42.100511 CS Dly: 6 (0~39)
5143 13:30:42.100593
5144 13:30:42.103603 ----->DramcWriteLeveling(PI) begin...
5145 13:30:42.103687 ==
5146 13:30:42.107105 Dram Type= 6, Freq= 0, CH_0, rank 0
5147 13:30:42.109973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5148 13:30:42.110057 ==
5149 13:30:42.113768 Write leveling (Byte 0): 32 => 32
5150 13:30:42.116765 Write leveling (Byte 1): 30 => 30
5151 13:30:42.119928 DramcWriteLeveling(PI) end<-----
5152 13:30:42.120027
5153 13:30:42.120093 ==
5154 13:30:42.123579 Dram Type= 6, Freq= 0, CH_0, rank 0
5155 13:30:42.126460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5156 13:30:42.126544 ==
5157 13:30:42.130200 [Gating] SW mode calibration
5158 13:30:42.136216 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5159 13:30:42.143232 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5160 13:30:42.146206 0 14 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5161 13:30:42.149922 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5162 13:30:42.156480 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5163 13:30:42.159584 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5164 13:30:42.162599 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5165 13:30:42.169137 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5166 13:30:42.172794 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5167 13:30:42.175841 0 14 28 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (0 0)
5168 13:30:42.182114 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5169 13:30:42.185840 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5170 13:30:42.189249 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 13:30:42.195780 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5172 13:30:42.198897 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5173 13:30:42.205692 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5174 13:30:42.208533 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5175 13:30:42.211921 0 15 28 | B1->B0 | 2323 3737 | 0 1 | (0 0) (0 0)
5176 13:30:42.218415 1 0 0 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
5177 13:30:42.222179 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 13:30:42.225321 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 13:30:42.231606 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 13:30:42.235271 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 13:30:42.238204 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 13:30:42.244911 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 13:30:42.248474 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5184 13:30:42.251457 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5185 13:30:42.258508 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5186 13:30:42.261502 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 13:30:42.264652 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 13:30:42.271221 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 13:30:42.274247 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 13:30:42.277993 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 13:30:42.284657 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 13:30:42.287649 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 13:30:42.290833 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 13:30:42.297193 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 13:30:42.300776 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 13:30:42.304311 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 13:30:42.310384 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 13:30:42.313957 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5199 13:30:42.317033 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5200 13:30:42.323673 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5201 13:30:42.323780 Total UI for P1: 0, mck2ui 16
5202 13:30:42.330395 best dqsien dly found for B0: ( 1, 2, 26)
5203 13:30:42.333957 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5204 13:30:42.336985 Total UI for P1: 0, mck2ui 16
5205 13:30:42.340518 best dqsien dly found for B1: ( 1, 3, 2)
5206 13:30:42.343875 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5207 13:30:42.347140 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5208 13:30:42.347321
5209 13:30:42.350110 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5210 13:30:42.353879 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5211 13:30:42.356843 [Gating] SW calibration Done
5212 13:30:42.356944 ==
5213 13:30:42.360134 Dram Type= 6, Freq= 0, CH_0, rank 0
5214 13:30:42.363619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5215 13:30:42.366739 ==
5216 13:30:42.366877 RX Vref Scan: 0
5217 13:30:42.366988
5218 13:30:42.369750 RX Vref 0 -> 0, step: 1
5219 13:30:42.369857
5220 13:30:42.372933 RX Delay -80 -> 252, step: 8
5221 13:30:42.376524 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5222 13:30:42.379482 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5223 13:30:42.383238 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5224 13:30:42.386302 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5225 13:30:42.389506 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5226 13:30:42.396302 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5227 13:30:42.399761 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5228 13:30:42.402505 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5229 13:30:42.406027 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5230 13:30:42.409055 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5231 13:30:42.415718 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5232 13:30:42.419143 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5233 13:30:42.422458 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5234 13:30:42.425813 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5235 13:30:42.429164 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5236 13:30:42.435487 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5237 13:30:42.435600 ==
5238 13:30:42.438757 Dram Type= 6, Freq= 0, CH_0, rank 0
5239 13:30:42.442085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5240 13:30:42.442237 ==
5241 13:30:42.442347 DQS Delay:
5242 13:30:42.445100 DQS0 = 0, DQS1 = 0
5243 13:30:42.445187 DQM Delay:
5244 13:30:42.448722 DQM0 = 100, DQM1 = 89
5245 13:30:42.448824 DQ Delay:
5246 13:30:42.451775 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5247 13:30:42.455491 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =111
5248 13:30:42.458647 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5249 13:30:42.461703 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5250 13:30:42.461778
5251 13:30:42.461842
5252 13:30:42.461919 ==
5253 13:30:42.465408 Dram Type= 6, Freq= 0, CH_0, rank 0
5254 13:30:42.468773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5255 13:30:42.472063 ==
5256 13:30:42.472156
5257 13:30:42.472277
5258 13:30:42.472343 TX Vref Scan disable
5259 13:30:42.474989 == TX Byte 0 ==
5260 13:30:42.478696 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5261 13:30:42.481676 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5262 13:30:42.484880 == TX Byte 1 ==
5263 13:30:42.488476 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5264 13:30:42.491672 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5265 13:30:42.494858 ==
5266 13:30:42.498334 Dram Type= 6, Freq= 0, CH_0, rank 0
5267 13:30:42.501393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5268 13:30:42.501491 ==
5269 13:30:42.501559
5270 13:30:42.501631
5271 13:30:42.504512 TX Vref Scan disable
5272 13:30:42.504596 == TX Byte 0 ==
5273 13:30:42.511368 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5274 13:30:42.514678 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5275 13:30:42.514795 == TX Byte 1 ==
5276 13:30:42.521232 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5277 13:30:42.524347 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5278 13:30:42.524430
5279 13:30:42.524494 [DATLAT]
5280 13:30:42.527613 Freq=933, CH0 RK0
5281 13:30:42.527715
5282 13:30:42.527808 DATLAT Default: 0xd
5283 13:30:42.531231 0, 0xFFFF, sum = 0
5284 13:30:42.531333 1, 0xFFFF, sum = 0
5285 13:30:42.534568 2, 0xFFFF, sum = 0
5286 13:30:42.537346 3, 0xFFFF, sum = 0
5287 13:30:42.537422 4, 0xFFFF, sum = 0
5288 13:30:42.540785 5, 0xFFFF, sum = 0
5289 13:30:42.540892 6, 0xFFFF, sum = 0
5290 13:30:42.544401 7, 0xFFFF, sum = 0
5291 13:30:42.544509 8, 0xFFFF, sum = 0
5292 13:30:42.547297 9, 0xFFFF, sum = 0
5293 13:30:42.547402 10, 0x0, sum = 1
5294 13:30:42.551333 11, 0x0, sum = 2
5295 13:30:42.551437 12, 0x0, sum = 3
5296 13:30:42.553945 13, 0x0, sum = 4
5297 13:30:42.554023 best_step = 11
5298 13:30:42.554085
5299 13:30:42.554146 ==
5300 13:30:42.557056 Dram Type= 6, Freq= 0, CH_0, rank 0
5301 13:30:42.560867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5302 13:30:42.560964 ==
5303 13:30:42.563869 RX Vref Scan: 1
5304 13:30:42.563981
5305 13:30:42.567673 RX Vref 0 -> 0, step: 1
5306 13:30:42.567773
5307 13:30:42.567863 RX Delay -61 -> 252, step: 4
5308 13:30:42.567960
5309 13:30:42.570657 Set Vref, RX VrefLevel [Byte0]: 55
5310 13:30:42.573619 [Byte1]: 43
5311 13:30:42.578705
5312 13:30:42.578779 Final RX Vref Byte 0 = 55 to rank0
5313 13:30:42.582247 Final RX Vref Byte 1 = 43 to rank0
5314 13:30:42.585281 Final RX Vref Byte 0 = 55 to rank1
5315 13:30:42.588460 Final RX Vref Byte 1 = 43 to rank1==
5316 13:30:42.592137 Dram Type= 6, Freq= 0, CH_0, rank 0
5317 13:30:42.598262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5318 13:30:42.598374 ==
5319 13:30:42.598471 DQS Delay:
5320 13:30:42.601915 DQS0 = 0, DQS1 = 0
5321 13:30:42.602015 DQM Delay:
5322 13:30:42.602105 DQM0 = 99, DQM1 = 86
5323 13:30:42.604822 DQ Delay:
5324 13:30:42.608562 DQ0 =100, DQ1 =98, DQ2 =94, DQ3 =96
5325 13:30:42.611475 DQ4 =98, DQ5 =90, DQ6 =110, DQ7 =106
5326 13:30:42.615002 DQ8 =78, DQ9 =72, DQ10 =86, DQ11 =82
5327 13:30:42.618026 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =94
5328 13:30:42.618128
5329 13:30:42.618218
5330 13:30:42.624448 [DQSOSCAuto] RK0, (LSB)MR18= 0x150f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
5331 13:30:42.627962 CH0 RK0: MR19=505, MR18=150F
5332 13:30:42.634378 CH0_RK0: MR19=0x505, MR18=0x150F, DQSOSC=415, MR23=63, INC=62, DEC=41
5333 13:30:42.634490
5334 13:30:42.637981 ----->DramcWriteLeveling(PI) begin...
5335 13:30:42.638056 ==
5336 13:30:42.640925 Dram Type= 6, Freq= 0, CH_0, rank 1
5337 13:30:42.644314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5338 13:30:42.644393 ==
5339 13:30:42.647844 Write leveling (Byte 0): 33 => 33
5340 13:30:42.650918 Write leveling (Byte 1): 29 => 29
5341 13:30:42.654032 DramcWriteLeveling(PI) end<-----
5342 13:30:42.654142
5343 13:30:42.654234 ==
5344 13:30:42.657462 Dram Type= 6, Freq= 0, CH_0, rank 1
5345 13:30:42.663777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5346 13:30:42.663891 ==
5347 13:30:42.663971 [Gating] SW mode calibration
5348 13:30:42.674083 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5349 13:30:42.677200 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5350 13:30:42.683830 0 14 0 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
5351 13:30:42.687102 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5352 13:30:42.690683 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5353 13:30:42.697362 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5354 13:30:42.700508 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5355 13:30:42.703641 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5356 13:30:42.710365 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
5357 13:30:42.714092 0 14 28 | B1->B0 | 3131 2828 | 1 0 | (1 1) (1 0)
5358 13:30:42.717209 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5359 13:30:42.723419 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 13:30:42.727000 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 13:30:42.730416 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 13:30:42.733844 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5363 13:30:42.739876 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5364 13:30:42.743243 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5365 13:30:42.749628 0 15 28 | B1->B0 | 2f2f 3d3d | 1 1 | (0 0) (1 1)
5366 13:30:42.753522 1 0 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5367 13:30:42.756559 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 13:30:42.763431 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 13:30:42.766314 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 13:30:42.769812 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 13:30:42.776346 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 13:30:42.779373 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 13:30:42.782942 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5374 13:30:42.789649 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5375 13:30:42.792673 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 13:30:42.795853 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 13:30:42.802588 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 13:30:42.805675 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 13:30:42.809374 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 13:30:42.815720 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 13:30:42.818796 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 13:30:42.822315 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 13:30:42.828927 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 13:30:42.831862 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 13:30:42.835304 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 13:30:42.841857 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 13:30:42.844912 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 13:30:42.848366 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 13:30:42.854927 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5390 13:30:42.858329 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5391 13:30:42.861641 Total UI for P1: 0, mck2ui 16
5392 13:30:42.864934 best dqsien dly found for B0: ( 1, 2, 28)
5393 13:30:42.868156 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5394 13:30:42.871232 Total UI for P1: 0, mck2ui 16
5395 13:30:42.874752 best dqsien dly found for B1: ( 1, 3, 0)
5396 13:30:42.878171 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5397 13:30:42.881601 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5398 13:30:42.881689
5399 13:30:42.887836 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5400 13:30:42.891399 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5401 13:30:42.891484 [Gating] SW calibration Done
5402 13:30:42.894379 ==
5403 13:30:42.897863 Dram Type= 6, Freq= 0, CH_0, rank 1
5404 13:30:42.901332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5405 13:30:42.901432 ==
5406 13:30:42.901501 RX Vref Scan: 0
5407 13:30:42.901563
5408 13:30:42.904145 RX Vref 0 -> 0, step: 1
5409 13:30:42.904223
5410 13:30:42.907921 RX Delay -80 -> 252, step: 8
5411 13:30:42.910972 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5412 13:30:42.914593 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5413 13:30:42.917407 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5414 13:30:42.924339 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5415 13:30:42.927412 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5416 13:30:42.931044 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5417 13:30:42.933839 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5418 13:30:42.937403 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5419 13:30:42.940460 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5420 13:30:42.946982 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5421 13:30:42.950831 iDelay=200, Bit 10, Center 87 (0 ~ 175) 176
5422 13:30:42.953653 iDelay=200, Bit 11, Center 87 (0 ~ 175) 176
5423 13:30:42.957224 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5424 13:30:42.960387 iDelay=200, Bit 13, Center 91 (0 ~ 183) 184
5425 13:30:42.967073 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5426 13:30:42.970399 iDelay=200, Bit 15, Center 95 (8 ~ 183) 176
5427 13:30:42.970491 ==
5428 13:30:42.973833 Dram Type= 6, Freq= 0, CH_0, rank 1
5429 13:30:42.976828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5430 13:30:42.976915 ==
5431 13:30:42.976982 DQS Delay:
5432 13:30:42.980362 DQS0 = 0, DQS1 = 0
5433 13:30:42.980451 DQM Delay:
5434 13:30:42.983338 DQM0 = 98, DQM1 = 88
5435 13:30:42.983424 DQ Delay:
5436 13:30:42.986859 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5437 13:30:42.989731 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5438 13:30:42.993392 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =87
5439 13:30:42.996469 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =95
5440 13:30:42.996547
5441 13:30:42.996613
5442 13:30:42.996691 ==
5443 13:30:43.000094 Dram Type= 6, Freq= 0, CH_0, rank 1
5444 13:30:43.006527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5445 13:30:43.006661 ==
5446 13:30:43.006769
5447 13:30:43.006861
5448 13:30:43.006973 TX Vref Scan disable
5449 13:30:43.009937 == TX Byte 0 ==
5450 13:30:43.013591 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5451 13:30:43.019709 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5452 13:30:43.019828 == TX Byte 1 ==
5453 13:30:43.023172 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5454 13:30:43.029910 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5455 13:30:43.030003 ==
5456 13:30:43.032979 Dram Type= 6, Freq= 0, CH_0, rank 1
5457 13:30:43.036497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5458 13:30:43.036595 ==
5459 13:30:43.036674
5460 13:30:43.036750
5461 13:30:43.039517 TX Vref Scan disable
5462 13:30:43.042987 == TX Byte 0 ==
5463 13:30:43.046049 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5464 13:30:43.049829 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5465 13:30:43.052456 == TX Byte 1 ==
5466 13:30:43.055854 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5467 13:30:43.059096 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5468 13:30:43.059191
5469 13:30:43.059309 [DATLAT]
5470 13:30:43.062498 Freq=933, CH0 RK1
5471 13:30:43.062589
5472 13:30:43.066044 DATLAT Default: 0xb
5473 13:30:43.066195 0, 0xFFFF, sum = 0
5474 13:30:43.069087 1, 0xFFFF, sum = 0
5475 13:30:43.069173 2, 0xFFFF, sum = 0
5476 13:30:43.072745 3, 0xFFFF, sum = 0
5477 13:30:43.072858 4, 0xFFFF, sum = 0
5478 13:30:43.075879 5, 0xFFFF, sum = 0
5479 13:30:43.075980 6, 0xFFFF, sum = 0
5480 13:30:43.079295 7, 0xFFFF, sum = 0
5481 13:30:43.079367 8, 0xFFFF, sum = 0
5482 13:30:43.082738 9, 0xFFFF, sum = 0
5483 13:30:43.082816 10, 0x0, sum = 1
5484 13:30:43.085611 11, 0x0, sum = 2
5485 13:30:43.085712 12, 0x0, sum = 3
5486 13:30:43.089457 13, 0x0, sum = 4
5487 13:30:43.089531 best_step = 11
5488 13:30:43.089596
5489 13:30:43.089653 ==
5490 13:30:43.092474 Dram Type= 6, Freq= 0, CH_0, rank 1
5491 13:30:43.095878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5492 13:30:43.098949 ==
5493 13:30:43.099025 RX Vref Scan: 0
5494 13:30:43.099088
5495 13:30:43.102065 RX Vref 0 -> 0, step: 1
5496 13:30:43.102133
5497 13:30:43.105760 RX Delay -61 -> 252, step: 4
5498 13:30:43.108857 iDelay=199, Bit 0, Center 94 (7 ~ 182) 176
5499 13:30:43.112492 iDelay=199, Bit 1, Center 98 (7 ~ 190) 184
5500 13:30:43.118514 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5501 13:30:43.122256 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5502 13:30:43.125437 iDelay=199, Bit 4, Center 100 (11 ~ 190) 180
5503 13:30:43.128441 iDelay=199, Bit 5, Center 86 (-5 ~ 178) 184
5504 13:30:43.132048 iDelay=199, Bit 6, Center 108 (19 ~ 198) 180
5505 13:30:43.135231 iDelay=199, Bit 7, Center 104 (15 ~ 194) 180
5506 13:30:43.141632 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5507 13:30:43.144586 iDelay=199, Bit 9, Center 74 (-13 ~ 162) 176
5508 13:30:43.148119 iDelay=199, Bit 10, Center 90 (3 ~ 178) 176
5509 13:30:43.151157 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5510 13:30:43.154903 iDelay=199, Bit 12, Center 90 (3 ~ 178) 176
5511 13:30:43.161419 iDelay=199, Bit 13, Center 92 (7 ~ 178) 172
5512 13:30:43.164695 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5513 13:30:43.167911 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5514 13:30:43.168019 ==
5515 13:30:43.171244 Dram Type= 6, Freq= 0, CH_0, rank 1
5516 13:30:43.174734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5517 13:30:43.174824 ==
5518 13:30:43.177921 DQS Delay:
5519 13:30:43.178004 DQS0 = 0, DQS1 = 0
5520 13:30:43.181030 DQM Delay:
5521 13:30:43.181151 DQM0 = 96, DQM1 = 86
5522 13:30:43.181219 DQ Delay:
5523 13:30:43.184505 DQ0 =94, DQ1 =98, DQ2 =90, DQ3 =94
5524 13:30:43.187816 DQ4 =100, DQ5 =86, DQ6 =108, DQ7 =104
5525 13:30:43.191107 DQ8 =76, DQ9 =74, DQ10 =90, DQ11 =80
5526 13:30:43.194355 DQ12 =90, DQ13 =92, DQ14 =98, DQ15 =94
5527 13:30:43.197297
5528 13:30:43.197385
5529 13:30:43.204381 [DQSOSCAuto] RK1, (LSB)MR18= 0x100e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 416 ps
5530 13:30:43.207378 CH0 RK1: MR19=505, MR18=100E
5531 13:30:43.213686 CH0_RK1: MR19=0x505, MR18=0x100E, DQSOSC=416, MR23=63, INC=62, DEC=41
5532 13:30:43.217290 [RxdqsGatingPostProcess] freq 933
5533 13:30:43.220318 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5534 13:30:43.223922 best DQS0 dly(2T, 0.5T) = (0, 10)
5535 13:30:43.227077 best DQS1 dly(2T, 0.5T) = (0, 11)
5536 13:30:43.230365 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5537 13:30:43.233948 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5538 13:30:43.236982 best DQS0 dly(2T, 0.5T) = (0, 10)
5539 13:30:43.240415 best DQS1 dly(2T, 0.5T) = (0, 11)
5540 13:30:43.243596 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5541 13:30:43.247188 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5542 13:30:43.250073 Pre-setting of DQS Precalculation
5543 13:30:43.253728 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5544 13:30:43.253850 ==
5545 13:30:43.256832 Dram Type= 6, Freq= 0, CH_1, rank 0
5546 13:30:43.263616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5547 13:30:43.263751 ==
5548 13:30:43.266504 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5549 13:30:43.273455 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5550 13:30:43.276771 [CA 0] Center 36 (6~67) winsize 62
5551 13:30:43.279971 [CA 1] Center 36 (6~67) winsize 62
5552 13:30:43.283030 [CA 2] Center 35 (4~66) winsize 63
5553 13:30:43.286704 [CA 3] Center 34 (4~65) winsize 62
5554 13:30:43.289735 [CA 4] Center 34 (4~65) winsize 62
5555 13:30:43.293299 [CA 5] Center 34 (4~64) winsize 61
5556 13:30:43.293403
5557 13:30:43.296245 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5558 13:30:43.296359
5559 13:30:43.299620 [CATrainingPosCal] consider 1 rank data
5560 13:30:43.302708 u2DelayCellTimex100 = 270/100 ps
5561 13:30:43.306377 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5562 13:30:43.312799 CA1 delay=36 (6~67),Diff = 2 PI (12 cell)
5563 13:30:43.316426 CA2 delay=35 (4~66),Diff = 1 PI (6 cell)
5564 13:30:43.319437 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5565 13:30:43.322447 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5566 13:30:43.326200 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5567 13:30:43.326311
5568 13:30:43.329276 CA PerBit enable=1, Macro0, CA PI delay=34
5569 13:30:43.329379
5570 13:30:43.332597 [CBTSetCACLKResult] CA Dly = 34
5571 13:30:43.336035 CS Dly: 5 (0~36)
5572 13:30:43.336124 ==
5573 13:30:43.338928 Dram Type= 6, Freq= 0, CH_1, rank 1
5574 13:30:43.342693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5575 13:30:43.342782 ==
5576 13:30:43.348929 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5577 13:30:43.352364 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5578 13:30:43.356946 [CA 0] Center 36 (6~67) winsize 62
5579 13:30:43.359918 [CA 1] Center 37 (7~67) winsize 61
5580 13:30:43.363063 [CA 2] Center 34 (4~65) winsize 62
5581 13:30:43.366779 [CA 3] Center 34 (3~65) winsize 63
5582 13:30:43.369730 [CA 4] Center 34 (4~65) winsize 62
5583 13:30:43.373382 [CA 5] Center 33 (3~64) winsize 62
5584 13:30:43.373476
5585 13:30:43.376251 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5586 13:30:43.376338
5587 13:30:43.379748 [CATrainingPosCal] consider 2 rank data
5588 13:30:43.382696 u2DelayCellTimex100 = 270/100 ps
5589 13:30:43.386276 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5590 13:30:43.392522 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5591 13:30:43.396078 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
5592 13:30:43.399231 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5593 13:30:43.402750 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5594 13:30:43.405591 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5595 13:30:43.405710
5596 13:30:43.409005 CA PerBit enable=1, Macro0, CA PI delay=34
5597 13:30:43.409109
5598 13:30:43.412306 [CBTSetCACLKResult] CA Dly = 34
5599 13:30:43.415499 CS Dly: 6 (0~38)
5600 13:30:43.415664
5601 13:30:43.418826 ----->DramcWriteLeveling(PI) begin...
5602 13:30:43.418941 ==
5603 13:30:43.422482 Dram Type= 6, Freq= 0, CH_1, rank 0
5604 13:30:43.425524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5605 13:30:43.425631 ==
5606 13:30:43.428695 Write leveling (Byte 0): 27 => 27
5607 13:30:43.432369 Write leveling (Byte 1): 29 => 29
5608 13:30:43.435355 DramcWriteLeveling(PI) end<-----
5609 13:30:43.435467
5610 13:30:43.435562 ==
5611 13:30:43.438337 Dram Type= 6, Freq= 0, CH_1, rank 0
5612 13:30:43.441795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5613 13:30:43.441902 ==
5614 13:30:43.445152 [Gating] SW mode calibration
5615 13:30:43.451700 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5616 13:30:43.458640 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5617 13:30:43.461494 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5618 13:30:43.468167 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5619 13:30:43.471417 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5620 13:30:43.474853 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5621 13:30:43.481426 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5622 13:30:43.484434 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5623 13:30:43.487997 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5624 13:30:43.494323 0 14 28 | B1->B0 | 2f2f 2626 | 0 0 | (0 1) (1 0)
5625 13:30:43.497617 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5626 13:30:43.501421 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5627 13:30:43.507721 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5628 13:30:43.510635 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5629 13:30:43.513791 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5630 13:30:43.520944 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5631 13:30:43.524124 0 15 24 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
5632 13:30:43.526998 0 15 28 | B1->B0 | 3232 3939 | 0 0 | (0 0) (0 0)
5633 13:30:43.533758 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 13:30:43.537481 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5635 13:30:43.540547 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 13:30:43.546924 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5637 13:30:43.550342 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 13:30:43.553856 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 13:30:43.560504 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 13:30:43.563135 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5641 13:30:43.566639 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5642 13:30:43.573214 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 13:30:43.576893 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 13:30:43.579871 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 13:30:43.586881 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 13:30:43.589880 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 13:30:43.592867 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 13:30:43.599876 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 13:30:43.603134 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 13:30:43.606444 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 13:30:43.612899 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 13:30:43.616421 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 13:30:43.619622 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 13:30:43.626379 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 13:30:43.629787 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5656 13:30:43.632611 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5657 13:30:43.639245 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5658 13:30:43.639381 Total UI for P1: 0, mck2ui 16
5659 13:30:43.645893 best dqsien dly found for B0: ( 1, 2, 26)
5660 13:30:43.646002 Total UI for P1: 0, mck2ui 16
5661 13:30:43.652741 best dqsien dly found for B1: ( 1, 2, 26)
5662 13:30:43.655764 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5663 13:30:43.659089 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5664 13:30:43.659179
5665 13:30:43.662289 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5666 13:30:43.665704 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5667 13:30:43.668683 [Gating] SW calibration Done
5668 13:30:43.668772 ==
5669 13:30:43.672085 Dram Type= 6, Freq= 0, CH_1, rank 0
5670 13:30:43.675545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5671 13:30:43.675648 ==
5672 13:30:43.678630 RX Vref Scan: 0
5673 13:30:43.678715
5674 13:30:43.678781 RX Vref 0 -> 0, step: 1
5675 13:30:43.678842
5676 13:30:43.682266 RX Delay -80 -> 252, step: 8
5677 13:30:43.688797 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5678 13:30:43.691892 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5679 13:30:43.695511 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5680 13:30:43.698622 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5681 13:30:43.701557 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5682 13:30:43.705133 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5683 13:30:43.711861 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5684 13:30:43.714943 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5685 13:30:43.718272 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5686 13:30:43.721234 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5687 13:30:43.724938 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5688 13:30:43.731155 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5689 13:30:43.734844 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5690 13:30:43.737839 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5691 13:30:43.741396 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5692 13:30:43.744571 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5693 13:30:43.744686 ==
5694 13:30:43.747929 Dram Type= 6, Freq= 0, CH_1, rank 0
5695 13:30:43.754510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5696 13:30:43.754624 ==
5697 13:30:43.754696 DQS Delay:
5698 13:30:43.757589 DQS0 = 0, DQS1 = 0
5699 13:30:43.757666 DQM Delay:
5700 13:30:43.761069 DQM0 = 97, DQM1 = 94
5701 13:30:43.761148 DQ Delay:
5702 13:30:43.764426 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =99
5703 13:30:43.767842 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5704 13:30:43.770563 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =87
5705 13:30:43.774083 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5706 13:30:43.774170
5707 13:30:43.774237
5708 13:30:43.774317 ==
5709 13:30:43.777532 Dram Type= 6, Freq= 0, CH_1, rank 0
5710 13:30:43.780893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5711 13:30:43.780988 ==
5712 13:30:43.781058
5713 13:30:43.784148
5714 13:30:43.784233 TX Vref Scan disable
5715 13:30:43.787457 == TX Byte 0 ==
5716 13:30:43.790565 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5717 13:30:43.794120 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5718 13:30:43.797635 == TX Byte 1 ==
5719 13:30:43.800766 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5720 13:30:43.804434 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5721 13:30:43.804519 ==
5722 13:30:43.807391 Dram Type= 6, Freq= 0, CH_1, rank 0
5723 13:30:43.814093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5724 13:30:43.814181 ==
5725 13:30:43.814268
5726 13:30:43.814366
5727 13:30:43.814469 TX Vref Scan disable
5728 13:30:43.818120 == TX Byte 0 ==
5729 13:30:43.821324 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5730 13:30:43.827682 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5731 13:30:43.827806 == TX Byte 1 ==
5732 13:30:43.830932 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5733 13:30:43.837691 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5734 13:30:43.837782
5735 13:30:43.837862 [DATLAT]
5736 13:30:43.837927 Freq=933, CH1 RK0
5737 13:30:43.837989
5738 13:30:43.841399 DATLAT Default: 0xd
5739 13:30:43.844446 0, 0xFFFF, sum = 0
5740 13:30:43.844546 1, 0xFFFF, sum = 0
5741 13:30:43.847693 2, 0xFFFF, sum = 0
5742 13:30:43.847771 3, 0xFFFF, sum = 0
5743 13:30:43.851066 4, 0xFFFF, sum = 0
5744 13:30:43.851151 5, 0xFFFF, sum = 0
5745 13:30:43.854166 6, 0xFFFF, sum = 0
5746 13:30:43.854243 7, 0xFFFF, sum = 0
5747 13:30:43.857760 8, 0xFFFF, sum = 0
5748 13:30:43.857898 9, 0xFFFF, sum = 0
5749 13:30:43.860624 10, 0x0, sum = 1
5750 13:30:43.860707 11, 0x0, sum = 2
5751 13:30:43.864247 12, 0x0, sum = 3
5752 13:30:43.864325 13, 0x0, sum = 4
5753 13:30:43.867247 best_step = 11
5754 13:30:43.867324
5755 13:30:43.867405 ==
5756 13:30:43.870640 Dram Type= 6, Freq= 0, CH_1, rank 0
5757 13:30:43.874039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5758 13:30:43.874139 ==
5759 13:30:43.874205 RX Vref Scan: 1
5760 13:30:43.876949
5761 13:30:43.877027 RX Vref 0 -> 0, step: 1
5762 13:30:43.877106
5763 13:30:43.880412 RX Delay -61 -> 252, step: 4
5764 13:30:43.880511
5765 13:30:43.883374 Set Vref, RX VrefLevel [Byte0]: 51
5766 13:30:43.886612 [Byte1]: 58
5767 13:30:43.890866
5768 13:30:43.890974 Final RX Vref Byte 0 = 51 to rank0
5769 13:30:43.893951 Final RX Vref Byte 1 = 58 to rank0
5770 13:30:43.897016 Final RX Vref Byte 0 = 51 to rank1
5771 13:30:43.900470 Final RX Vref Byte 1 = 58 to rank1==
5772 13:30:43.903420 Dram Type= 6, Freq= 0, CH_1, rank 0
5773 13:30:43.909996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5774 13:30:43.910107 ==
5775 13:30:43.910184 DQS Delay:
5776 13:30:43.913674 DQS0 = 0, DQS1 = 0
5777 13:30:43.913752 DQM Delay:
5778 13:30:43.913833 DQM0 = 97, DQM1 = 95
5779 13:30:43.916650 DQ Delay:
5780 13:30:43.920370 DQ0 =104, DQ1 =92, DQ2 =88, DQ3 =96
5781 13:30:43.923325 DQ4 =96, DQ5 =106, DQ6 =108, DQ7 =92
5782 13:30:43.926678 DQ8 =82, DQ9 =88, DQ10 =92, DQ11 =90
5783 13:30:43.930168 DQ12 =106, DQ13 =106, DQ14 =100, DQ15 =100
5784 13:30:43.930247
5785 13:30:43.930310
5786 13:30:43.936863 [DQSOSCAuto] RK0, (LSB)MR18= 0x817, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 419 ps
5787 13:30:43.939854 CH1 RK0: MR19=505, MR18=817
5788 13:30:43.946658 CH1_RK0: MR19=0x505, MR18=0x817, DQSOSC=414, MR23=63, INC=63, DEC=42
5789 13:30:43.946773
5790 13:30:43.949776 ----->DramcWriteLeveling(PI) begin...
5791 13:30:43.949889 ==
5792 13:30:43.953321 Dram Type= 6, Freq= 0, CH_1, rank 1
5793 13:30:43.956307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5794 13:30:43.956391 ==
5795 13:30:43.959789 Write leveling (Byte 0): 25 => 25
5796 13:30:43.963327 Write leveling (Byte 1): 29 => 29
5797 13:30:43.966456 DramcWriteLeveling(PI) end<-----
5798 13:30:43.966568
5799 13:30:43.966663 ==
5800 13:30:43.969401 Dram Type= 6, Freq= 0, CH_1, rank 1
5801 13:30:43.976429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5802 13:30:43.976518 ==
5803 13:30:43.976586 [Gating] SW mode calibration
5804 13:30:43.985785 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5805 13:30:43.989279 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5806 13:30:43.996003 0 14 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5807 13:30:43.999019 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5808 13:30:44.002062 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5809 13:30:44.009082 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5810 13:30:44.012188 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5811 13:30:44.015804 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5812 13:30:44.021858 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
5813 13:30:44.025516 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (1 0) (1 0)
5814 13:30:44.028690 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5815 13:30:44.035180 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5816 13:30:44.038618 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5817 13:30:44.041851 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5818 13:30:44.048323 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5819 13:30:44.051496 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5820 13:30:44.055179 0 15 24 | B1->B0 | 2424 3131 | 0 0 | (0 0) (0 0)
5821 13:30:44.061926 0 15 28 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5822 13:30:44.065113 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 13:30:44.068304 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5824 13:30:44.074945 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 13:30:44.078320 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5826 13:30:44.081522 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5827 13:30:44.088200 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5828 13:30:44.091535 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 13:30:44.094440 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5830 13:30:44.101678 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 13:30:44.104724 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 13:30:44.108190 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 13:30:44.114924 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 13:30:44.117809 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 13:30:44.120932 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 13:30:44.127650 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 13:30:44.130966 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 13:30:44.134415 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 13:30:44.141047 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 13:30:44.144028 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 13:30:44.147351 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 13:30:44.154251 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 13:30:44.157337 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 13:30:44.160953 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 13:30:44.167147 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5846 13:30:44.167230 Total UI for P1: 0, mck2ui 16
5847 13:30:44.170777 best dqsien dly found for B0: ( 1, 2, 26)
5848 13:30:44.176870 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5849 13:30:44.180335 Total UI for P1: 0, mck2ui 16
5850 13:30:44.183540 best dqsien dly found for B1: ( 1, 2, 28)
5851 13:30:44.187190 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5852 13:30:44.190125 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5853 13:30:44.190224
5854 13:30:44.193450 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5855 13:30:44.197160 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5856 13:30:44.200235 [Gating] SW calibration Done
5857 13:30:44.200314 ==
5858 13:30:44.203517 Dram Type= 6, Freq= 0, CH_1, rank 1
5859 13:30:44.206701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5860 13:30:44.210242 ==
5861 13:30:44.210386 RX Vref Scan: 0
5862 13:30:44.210510
5863 13:30:44.213378 RX Vref 0 -> 0, step: 1
5864 13:30:44.213478
5865 13:30:44.216275 RX Delay -80 -> 252, step: 8
5866 13:30:44.219761 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5867 13:30:44.222903 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5868 13:30:44.226675 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5869 13:30:44.229717 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5870 13:30:44.232728 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5871 13:30:44.239470 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5872 13:30:44.243080 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5873 13:30:44.246068 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5874 13:30:44.249744 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5875 13:30:44.252775 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5876 13:30:44.259362 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5877 13:30:44.262416 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5878 13:30:44.265554 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5879 13:30:44.269242 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5880 13:30:44.272390 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5881 13:30:44.278615 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5882 13:30:44.278698 ==
5883 13:30:44.282300 Dram Type= 6, Freq= 0, CH_1, rank 1
5884 13:30:44.285249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5885 13:30:44.285346 ==
5886 13:30:44.285413 DQS Delay:
5887 13:30:44.288806 DQS0 = 0, DQS1 = 0
5888 13:30:44.288897 DQM Delay:
5889 13:30:44.292171 DQM0 = 96, DQM1 = 93
5890 13:30:44.292259 DQ Delay:
5891 13:30:44.295313 DQ0 =103, DQ1 =91, DQ2 =83, DQ3 =95
5892 13:30:44.298212 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =91
5893 13:30:44.301946 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5894 13:30:44.305359 DQ12 =103, DQ13 =103, DQ14 =95, DQ15 =95
5895 13:30:44.305484
5896 13:30:44.305614
5897 13:30:44.305694 ==
5898 13:30:44.308697 Dram Type= 6, Freq= 0, CH_1, rank 1
5899 13:30:44.314874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5900 13:30:44.314959 ==
5901 13:30:44.315026
5902 13:30:44.315107
5903 13:30:44.315167 TX Vref Scan disable
5904 13:30:44.317954 == TX Byte 0 ==
5905 13:30:44.321512 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5906 13:30:44.328308 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5907 13:30:44.328395 == TX Byte 1 ==
5908 13:30:44.331140 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5909 13:30:44.337957 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5910 13:30:44.338068 ==
5911 13:30:44.341295 Dram Type= 6, Freq= 0, CH_1, rank 1
5912 13:30:44.344655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5913 13:30:44.344768 ==
5914 13:30:44.344891
5915 13:30:44.344985
5916 13:30:44.347834 TX Vref Scan disable
5917 13:30:44.350773 == TX Byte 0 ==
5918 13:30:44.354430 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5919 13:30:44.357675 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5920 13:30:44.361194 == TX Byte 1 ==
5921 13:30:44.363863 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5922 13:30:44.367766 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5923 13:30:44.367874
5924 13:30:44.367986 [DATLAT]
5925 13:30:44.370708 Freq=933, CH1 RK1
5926 13:30:44.370837
5927 13:30:44.373944 DATLAT Default: 0xb
5928 13:30:44.374049 0, 0xFFFF, sum = 0
5929 13:30:44.377445 1, 0xFFFF, sum = 0
5930 13:30:44.377570 2, 0xFFFF, sum = 0
5931 13:30:44.380587 3, 0xFFFF, sum = 0
5932 13:30:44.380695 4, 0xFFFF, sum = 0
5933 13:30:44.383736 5, 0xFFFF, sum = 0
5934 13:30:44.383878 6, 0xFFFF, sum = 0
5935 13:30:44.387434 7, 0xFFFF, sum = 0
5936 13:30:44.387558 8, 0xFFFF, sum = 0
5937 13:30:44.390404 9, 0xFFFF, sum = 0
5938 13:30:44.390484 10, 0x0, sum = 1
5939 13:30:44.393446 11, 0x0, sum = 2
5940 13:30:44.393536 12, 0x0, sum = 3
5941 13:30:44.396939 13, 0x0, sum = 4
5942 13:30:44.397060 best_step = 11
5943 13:30:44.397154
5944 13:30:44.397265 ==
5945 13:30:44.400349 Dram Type= 6, Freq= 0, CH_1, rank 1
5946 13:30:44.406773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5947 13:30:44.406897 ==
5948 13:30:44.406986 RX Vref Scan: 0
5949 13:30:44.407069
5950 13:30:44.409837 RX Vref 0 -> 0, step: 1
5951 13:30:44.409938
5952 13:30:44.413842 RX Delay -61 -> 252, step: 4
5953 13:30:44.416951 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5954 13:30:44.420477 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5955 13:30:44.427065 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5956 13:30:44.430327 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5957 13:30:44.433334 iDelay=199, Bit 4, Center 98 (7 ~ 190) 184
5958 13:30:44.436976 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5959 13:30:44.440068 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5960 13:30:44.443131 iDelay=199, Bit 7, Center 94 (3 ~ 186) 184
5961 13:30:44.449431 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5962 13:30:44.453447 iDelay=199, Bit 9, Center 86 (-1 ~ 174) 176
5963 13:30:44.456379 iDelay=199, Bit 10, Center 96 (7 ~ 186) 180
5964 13:30:44.459419 iDelay=199, Bit 11, Center 88 (-1 ~ 178) 180
5965 13:30:44.462765 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5966 13:30:44.469299 iDelay=199, Bit 13, Center 104 (15 ~ 194) 180
5967 13:30:44.473068 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
5968 13:30:44.476203 iDelay=199, Bit 15, Center 102 (15 ~ 190) 176
5969 13:30:44.476285 ==
5970 13:30:44.479182 Dram Type= 6, Freq= 0, CH_1, rank 1
5971 13:30:44.482797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5972 13:30:44.485882 ==
5973 13:30:44.485996 DQS Delay:
5974 13:30:44.486096 DQS0 = 0, DQS1 = 0
5975 13:30:44.489726 DQM Delay:
5976 13:30:44.489831 DQM0 = 97, DQM1 = 95
5977 13:30:44.492702 DQ Delay:
5978 13:30:44.495701 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =94
5979 13:30:44.499416 DQ4 =98, DQ5 =106, DQ6 =104, DQ7 =94
5980 13:30:44.502537 DQ8 =82, DQ9 =86, DQ10 =96, DQ11 =88
5981 13:30:44.505885 DQ12 =106, DQ13 =104, DQ14 =102, DQ15 =102
5982 13:30:44.505992
5983 13:30:44.506093
5984 13:30:44.512438 [DQSOSCAuto] RK1, (LSB)MR18= 0xc23, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 418 ps
5985 13:30:44.515384 CH1 RK1: MR19=505, MR18=C23
5986 13:30:44.522155 CH1_RK1: MR19=0x505, MR18=0xC23, DQSOSC=410, MR23=63, INC=64, DEC=42
5987 13:30:44.525199 [RxdqsGatingPostProcess] freq 933
5988 13:30:44.528881 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5989 13:30:44.531987 best DQS0 dly(2T, 0.5T) = (0, 10)
5990 13:30:44.535061 best DQS1 dly(2T, 0.5T) = (0, 10)
5991 13:30:44.538249 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5992 13:30:44.541804 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5993 13:30:44.545405 best DQS0 dly(2T, 0.5T) = (0, 10)
5994 13:30:44.548546 best DQS1 dly(2T, 0.5T) = (0, 10)
5995 13:30:44.551746 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5996 13:30:44.554777 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5997 13:30:44.558320 Pre-setting of DQS Precalculation
5998 13:30:44.564917 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5999 13:30:44.571417 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6000 13:30:44.577946 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6001 13:30:44.578076
6002 13:30:44.578187
6003 13:30:44.581050 [Calibration Summary] 1866 Mbps
6004 13:30:44.581161 CH 0, Rank 0
6005 13:30:44.584538 SW Impedance : PASS
6006 13:30:44.587743 DUTY Scan : NO K
6007 13:30:44.587867 ZQ Calibration : PASS
6008 13:30:44.591212 Jitter Meter : NO K
6009 13:30:44.594080 CBT Training : PASS
6010 13:30:44.594210 Write leveling : PASS
6011 13:30:44.597780 RX DQS gating : PASS
6012 13:30:44.600866 RX DQ/DQS(RDDQC) : PASS
6013 13:30:44.600959 TX DQ/DQS : PASS
6014 13:30:44.604573 RX DATLAT : PASS
6015 13:30:44.607729 RX DQ/DQS(Engine): PASS
6016 13:30:44.607835 TX OE : NO K
6017 13:30:44.607948 All Pass.
6018 13:30:44.610619
6019 13:30:44.610697 CH 0, Rank 1
6020 13:30:44.614314 SW Impedance : PASS
6021 13:30:44.614406 DUTY Scan : NO K
6022 13:30:44.617227 ZQ Calibration : PASS
6023 13:30:44.620429 Jitter Meter : NO K
6024 13:30:44.620510 CBT Training : PASS
6025 13:30:44.623986 Write leveling : PASS
6026 13:30:44.624083 RX DQS gating : PASS
6027 13:30:44.627446 RX DQ/DQS(RDDQC) : PASS
6028 13:30:44.630704 TX DQ/DQS : PASS
6029 13:30:44.630825 RX DATLAT : PASS
6030 13:30:44.633483 RX DQ/DQS(Engine): PASS
6031 13:30:44.637247 TX OE : NO K
6032 13:30:44.637375 All Pass.
6033 13:30:44.637499
6034 13:30:44.637593 CH 1, Rank 0
6035 13:30:44.640066 SW Impedance : PASS
6036 13:30:44.643651 DUTY Scan : NO K
6037 13:30:44.643771 ZQ Calibration : PASS
6038 13:30:44.647254 Jitter Meter : NO K
6039 13:30:44.650338 CBT Training : PASS
6040 13:30:44.650416 Write leveling : PASS
6041 13:30:44.653394 RX DQS gating : PASS
6042 13:30:44.657558 RX DQ/DQS(RDDQC) : PASS
6043 13:30:44.657649 TX DQ/DQS : PASS
6044 13:30:44.660277 RX DATLAT : PASS
6045 13:30:44.663440 RX DQ/DQS(Engine): PASS
6046 13:30:44.663513 TX OE : NO K
6047 13:30:44.667004 All Pass.
6048 13:30:44.667093
6049 13:30:44.667181 CH 1, Rank 1
6050 13:30:44.670010 SW Impedance : PASS
6051 13:30:44.670082 DUTY Scan : NO K
6052 13:30:44.673076 ZQ Calibration : PASS
6053 13:30:44.676772 Jitter Meter : NO K
6054 13:30:44.676856 CBT Training : PASS
6055 13:30:44.679909 Write leveling : PASS
6056 13:30:44.683451 RX DQS gating : PASS
6057 13:30:44.683534 RX DQ/DQS(RDDQC) : PASS
6058 13:30:44.686583 TX DQ/DQS : PASS
6059 13:30:44.690068 RX DATLAT : PASS
6060 13:30:44.690152 RX DQ/DQS(Engine): PASS
6061 13:30:44.692820 TX OE : NO K
6062 13:30:44.692903 All Pass.
6063 13:30:44.692968
6064 13:30:44.696492 DramC Write-DBI off
6065 13:30:44.699790 PER_BANK_REFRESH: Hybrid Mode
6066 13:30:44.699901 TX_TRACKING: ON
6067 13:30:44.709465 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6068 13:30:44.713161 [FAST_K] Save calibration result to emmc
6069 13:30:44.715866 dramc_set_vcore_voltage set vcore to 650000
6070 13:30:44.719531 Read voltage for 400, 6
6071 13:30:44.719617 Vio18 = 0
6072 13:30:44.719683 Vcore = 650000
6073 13:30:44.722558 Vdram = 0
6074 13:30:44.722642 Vddq = 0
6075 13:30:44.722707 Vmddr = 0
6076 13:30:44.729468 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6077 13:30:44.732469 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6078 13:30:44.735912 MEM_TYPE=3, freq_sel=20
6079 13:30:44.739276 sv_algorithm_assistance_LP4_800
6080 13:30:44.742785 ============ PULL DRAM RESETB DOWN ============
6081 13:30:44.745757 ========== PULL DRAM RESETB DOWN end =========
6082 13:30:44.752384 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6083 13:30:44.756004 ===================================
6084 13:30:44.759179 LPDDR4 DRAM CONFIGURATION
6085 13:30:44.762049 ===================================
6086 13:30:44.762151 EX_ROW_EN[0] = 0x0
6087 13:30:44.765878 EX_ROW_EN[1] = 0x0
6088 13:30:44.765979 LP4Y_EN = 0x0
6089 13:30:44.768818 WORK_FSP = 0x0
6090 13:30:44.768923 WL = 0x2
6091 13:30:44.771844 RL = 0x2
6092 13:30:44.771952 BL = 0x2
6093 13:30:44.775488 RPST = 0x0
6094 13:30:44.775587 RD_PRE = 0x0
6095 13:30:44.778528 WR_PRE = 0x1
6096 13:30:44.778612 WR_PST = 0x0
6097 13:30:44.782125 DBI_WR = 0x0
6098 13:30:44.782208 DBI_RD = 0x0
6099 13:30:44.785138 OTF = 0x1
6100 13:30:44.788900 ===================================
6101 13:30:44.792144 ===================================
6102 13:30:44.792228 ANA top config
6103 13:30:44.795154 ===================================
6104 13:30:44.798538 DLL_ASYNC_EN = 0
6105 13:30:44.801695 ALL_SLAVE_EN = 1
6106 13:30:44.804745 NEW_RANK_MODE = 1
6107 13:30:44.808212 DLL_IDLE_MODE = 1
6108 13:30:44.808296 LP45_APHY_COMB_EN = 1
6109 13:30:44.811556 TX_ODT_DIS = 1
6110 13:30:44.814789 NEW_8X_MODE = 1
6111 13:30:44.817912 ===================================
6112 13:30:44.821334 ===================================
6113 13:30:44.824824 data_rate = 800
6114 13:30:44.827833 CKR = 1
6115 13:30:44.831119 DQ_P2S_RATIO = 4
6116 13:30:44.834425 ===================================
6117 13:30:44.834511 CA_P2S_RATIO = 4
6118 13:30:44.837829 DQ_CA_OPEN = 0
6119 13:30:44.841147 DQ_SEMI_OPEN = 1
6120 13:30:44.844236 CA_SEMI_OPEN = 1
6121 13:30:44.847566 CA_FULL_RATE = 0
6122 13:30:44.850979 DQ_CKDIV4_EN = 0
6123 13:30:44.851067 CA_CKDIV4_EN = 1
6124 13:30:44.854409 CA_PREDIV_EN = 0
6125 13:30:44.857378 PH8_DLY = 0
6126 13:30:44.861157 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6127 13:30:44.864273 DQ_AAMCK_DIV = 0
6128 13:30:44.867392 CA_AAMCK_DIV = 0
6129 13:30:44.867476 CA_ADMCK_DIV = 4
6130 13:30:44.870439 DQ_TRACK_CA_EN = 0
6131 13:30:44.874030 CA_PICK = 800
6132 13:30:44.876974 CA_MCKIO = 400
6133 13:30:44.880612 MCKIO_SEMI = 400
6134 13:30:44.883633 PLL_FREQ = 3016
6135 13:30:44.887332 DQ_UI_PI_RATIO = 32
6136 13:30:44.890473 CA_UI_PI_RATIO = 32
6137 13:30:44.893460 ===================================
6138 13:30:44.897266 ===================================
6139 13:30:44.897366 memory_type:LPDDR4
6140 13:30:44.900397 GP_NUM : 10
6141 13:30:44.903263 SRAM_EN : 1
6142 13:30:44.903381 MD32_EN : 0
6143 13:30:44.906971 ===================================
6144 13:30:44.910116 [ANA_INIT] >>>>>>>>>>>>>>
6145 13:30:44.913658 <<<<<< [CONFIGURE PHASE]: ANA_TX
6146 13:30:44.916574 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6147 13:30:44.919849 ===================================
6148 13:30:44.923289 data_rate = 800,PCW = 0X7400
6149 13:30:44.926868 ===================================
6150 13:30:44.929842 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6151 13:30:44.933280 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6152 13:30:44.946393 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6153 13:30:44.949722 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6154 13:30:44.952671 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6155 13:30:44.956061 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6156 13:30:44.959994 [ANA_INIT] flow start
6157 13:30:44.962616 [ANA_INIT] PLL >>>>>>>>
6158 13:30:44.962736 [ANA_INIT] PLL <<<<<<<<
6159 13:30:44.966117 [ANA_INIT] MIDPI >>>>>>>>
6160 13:30:44.969265 [ANA_INIT] MIDPI <<<<<<<<
6161 13:30:44.969392 [ANA_INIT] DLL >>>>>>>>
6162 13:30:44.972973 [ANA_INIT] flow end
6163 13:30:44.975992 ============ LP4 DIFF to SE enter ============
6164 13:30:44.982629 ============ LP4 DIFF to SE exit ============
6165 13:30:44.982758 [ANA_INIT] <<<<<<<<<<<<<
6166 13:30:44.985594 [Flow] Enable top DCM control >>>>>
6167 13:30:44.988744 [Flow] Enable top DCM control <<<<<
6168 13:30:44.992399 Enable DLL master slave shuffle
6169 13:30:44.998964 ==============================================================
6170 13:30:44.999052 Gating Mode config
6171 13:30:45.005720 ==============================================================
6172 13:30:45.008633 Config description:
6173 13:30:45.018616 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6174 13:30:45.025071 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6175 13:30:45.028363 SELPH_MODE 0: By rank 1: By Phase
6176 13:30:45.034906 ==============================================================
6177 13:30:45.038511 GAT_TRACK_EN = 0
6178 13:30:45.041426 RX_GATING_MODE = 2
6179 13:30:45.041531 RX_GATING_TRACK_MODE = 2
6180 13:30:45.045220 SELPH_MODE = 1
6181 13:30:45.048283 PICG_EARLY_EN = 1
6182 13:30:45.051803 VALID_LAT_VALUE = 1
6183 13:30:45.058212 ==============================================================
6184 13:30:45.061095 Enter into Gating configuration >>>>
6185 13:30:45.064410 Exit from Gating configuration <<<<
6186 13:30:45.068274 Enter into DVFS_PRE_config >>>>>
6187 13:30:45.077526 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6188 13:30:45.081269 Exit from DVFS_PRE_config <<<<<
6189 13:30:45.084182 Enter into PICG configuration >>>>
6190 13:30:45.087831 Exit from PICG configuration <<<<
6191 13:30:45.090875 [RX_INPUT] configuration >>>>>
6192 13:30:45.093941 [RX_INPUT] configuration <<<<<
6193 13:30:45.097118 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6194 13:30:45.103669 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6195 13:30:45.110921 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6196 13:30:45.116905 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6197 13:30:45.123649 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6198 13:30:45.130130 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6199 13:30:45.133584 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6200 13:30:45.136587 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6201 13:30:45.140069 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6202 13:30:45.146626 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6203 13:30:45.150020 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6204 13:30:45.153503 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6205 13:30:45.156516 ===================================
6206 13:30:45.160241 LPDDR4 DRAM CONFIGURATION
6207 13:30:45.163213 ===================================
6208 13:30:45.163297 EX_ROW_EN[0] = 0x0
6209 13:30:45.166290 EX_ROW_EN[1] = 0x0
6210 13:30:45.169966 LP4Y_EN = 0x0
6211 13:30:45.170045 WORK_FSP = 0x0
6212 13:30:45.172992 WL = 0x2
6213 13:30:45.173064 RL = 0x2
6214 13:30:45.176596 BL = 0x2
6215 13:30:45.176678 RPST = 0x0
6216 13:30:45.179880 RD_PRE = 0x0
6217 13:30:45.179977 WR_PRE = 0x1
6218 13:30:45.183195 WR_PST = 0x0
6219 13:30:45.183268 DBI_WR = 0x0
6220 13:30:45.186349 DBI_RD = 0x0
6221 13:30:45.186433 OTF = 0x1
6222 13:30:45.189636 ===================================
6223 13:30:45.193128 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6224 13:30:45.199629 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6225 13:30:45.202654 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6226 13:30:45.206471 ===================================
6227 13:30:45.209379 LPDDR4 DRAM CONFIGURATION
6228 13:30:45.212479 ===================================
6229 13:30:45.212574 EX_ROW_EN[0] = 0x10
6230 13:30:45.215868 EX_ROW_EN[1] = 0x0
6231 13:30:45.219160 LP4Y_EN = 0x0
6232 13:30:45.219247 WORK_FSP = 0x0
6233 13:30:45.222191 WL = 0x2
6234 13:30:45.222305 RL = 0x2
6235 13:30:45.225931 BL = 0x2
6236 13:30:45.226040 RPST = 0x0
6237 13:30:45.228999 RD_PRE = 0x0
6238 13:30:45.229103 WR_PRE = 0x1
6239 13:30:45.232067 WR_PST = 0x0
6240 13:30:45.232181 DBI_WR = 0x0
6241 13:30:45.235616 DBI_RD = 0x0
6242 13:30:45.235720 OTF = 0x1
6243 13:30:45.238928 ===================================
6244 13:30:45.245343 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6245 13:30:45.250107 nWR fixed to 30
6246 13:30:45.253550 [ModeRegInit_LP4] CH0 RK0
6247 13:30:45.253645 [ModeRegInit_LP4] CH0 RK1
6248 13:30:45.256799 [ModeRegInit_LP4] CH1 RK0
6249 13:30:45.260039 [ModeRegInit_LP4] CH1 RK1
6250 13:30:45.260129 match AC timing 19
6251 13:30:45.266745 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6252 13:30:45.269804 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6253 13:30:45.272798 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6254 13:30:45.280027 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6255 13:30:45.283026 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6256 13:30:45.283124 ==
6257 13:30:45.286070 Dram Type= 6, Freq= 0, CH_0, rank 0
6258 13:30:45.289622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6259 13:30:45.289699 ==
6260 13:30:45.296162 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6261 13:30:45.302997 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6262 13:30:45.305922 [CA 0] Center 36 (8~64) winsize 57
6263 13:30:45.309145 [CA 1] Center 36 (8~64) winsize 57
6264 13:30:45.312413 [CA 2] Center 36 (8~64) winsize 57
6265 13:30:45.315994 [CA 3] Center 36 (8~64) winsize 57
6266 13:30:45.318851 [CA 4] Center 36 (8~64) winsize 57
6267 13:30:45.322393 [CA 5] Center 36 (8~64) winsize 57
6268 13:30:45.322508
6269 13:30:45.326100 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6270 13:30:45.326200
6271 13:30:45.329230 [CATrainingPosCal] consider 1 rank data
6272 13:30:45.332161 u2DelayCellTimex100 = 270/100 ps
6273 13:30:45.335733 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 13:30:45.338863 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 13:30:45.342349 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 13:30:45.345789 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 13:30:45.348939 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 13:30:45.351863 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 13:30:45.351968
6280 13:30:45.358544 CA PerBit enable=1, Macro0, CA PI delay=36
6281 13:30:45.358637
6282 13:30:45.362080 [CBTSetCACLKResult] CA Dly = 36
6283 13:30:45.362167 CS Dly: 1 (0~32)
6284 13:30:45.362254 ==
6285 13:30:45.364926 Dram Type= 6, Freq= 0, CH_0, rank 1
6286 13:30:45.368468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6287 13:30:45.368557 ==
6288 13:30:45.375324 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6289 13:30:45.381345 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6290 13:30:45.384753 [CA 0] Center 36 (8~64) winsize 57
6291 13:30:45.388515 [CA 1] Center 36 (8~64) winsize 57
6292 13:30:45.391525 [CA 2] Center 36 (8~64) winsize 57
6293 13:30:45.395073 [CA 3] Center 36 (8~64) winsize 57
6294 13:30:45.398140 [CA 4] Center 36 (8~64) winsize 57
6295 13:30:45.401257 [CA 5] Center 36 (8~64) winsize 57
6296 13:30:45.401370
6297 13:30:45.404463 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6298 13:30:45.404550
6299 13:30:45.407558 [CATrainingPosCal] consider 2 rank data
6300 13:30:45.411142 u2DelayCellTimex100 = 270/100 ps
6301 13:30:45.414903 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 13:30:45.417744 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 13:30:45.421066 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 13:30:45.424254 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 13:30:45.427492 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 13:30:45.430769 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 13:30:45.430889
6308 13:30:45.437428 CA PerBit enable=1, Macro0, CA PI delay=36
6309 13:30:45.437542
6310 13:30:45.437650 [CBTSetCACLKResult] CA Dly = 36
6311 13:30:45.440529 CS Dly: 1 (0~32)
6312 13:30:45.440640
6313 13:30:45.444043 ----->DramcWriteLeveling(PI) begin...
6314 13:30:45.444154 ==
6315 13:30:45.447127 Dram Type= 6, Freq= 0, CH_0, rank 0
6316 13:30:45.450786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6317 13:30:45.450890 ==
6318 13:30:45.453576 Write leveling (Byte 0): 40 => 8
6319 13:30:45.456974 Write leveling (Byte 1): 40 => 8
6320 13:30:45.460465 DramcWriteLeveling(PI) end<-----
6321 13:30:45.460574
6322 13:30:45.460666 ==
6323 13:30:45.463522 Dram Type= 6, Freq= 0, CH_0, rank 0
6324 13:30:45.470610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6325 13:30:45.470722 ==
6326 13:30:45.470821 [Gating] SW mode calibration
6327 13:30:45.480129 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6328 13:30:45.483699 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6329 13:30:45.486652 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6330 13:30:45.493394 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6331 13:30:45.496918 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6332 13:30:45.499953 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6333 13:30:45.506743 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6334 13:30:45.509538 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6335 13:30:45.516707 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6336 13:30:45.519697 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6337 13:30:45.522906 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6338 13:30:45.526265 Total UI for P1: 0, mck2ui 16
6339 13:30:45.529442 best dqsien dly found for B0: ( 0, 14, 24)
6340 13:30:45.532808 Total UI for P1: 0, mck2ui 16
6341 13:30:45.536343 best dqsien dly found for B1: ( 0, 14, 24)
6342 13:30:45.539640 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6343 13:30:45.543014 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6344 13:30:45.543101
6345 13:30:45.545928 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6346 13:30:45.552733 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6347 13:30:45.552837 [Gating] SW calibration Done
6348 13:30:45.555793 ==
6349 13:30:45.555877 Dram Type= 6, Freq= 0, CH_0, rank 0
6350 13:30:45.562670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6351 13:30:45.562778 ==
6352 13:30:45.562844 RX Vref Scan: 0
6353 13:30:45.562914
6354 13:30:45.566019 RX Vref 0 -> 0, step: 1
6355 13:30:45.566102
6356 13:30:45.568869 RX Delay -410 -> 252, step: 16
6357 13:30:45.572359 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6358 13:30:45.575546 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6359 13:30:45.582470 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6360 13:30:45.585266 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6361 13:30:45.588969 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6362 13:30:45.595508 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6363 13:30:45.598577 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6364 13:30:45.602032 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6365 13:30:45.605044 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6366 13:30:45.611760 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6367 13:30:45.615408 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6368 13:30:45.618695 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6369 13:30:45.621647 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6370 13:30:45.628322 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6371 13:30:45.631915 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6372 13:30:45.634810 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6373 13:30:45.634926 ==
6374 13:30:45.637856 Dram Type= 6, Freq= 0, CH_0, rank 0
6375 13:30:45.644364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6376 13:30:45.644493 ==
6377 13:30:45.644602 DQS Delay:
6378 13:30:45.647965 DQS0 = 35, DQS1 = 51
6379 13:30:45.648046 DQM Delay:
6380 13:30:45.648111 DQM0 = 4, DQM1 = 9
6381 13:30:45.651315 DQ Delay:
6382 13:30:45.654468 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6383 13:30:45.654579 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6384 13:30:45.657408 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6385 13:30:45.661160 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6386 13:30:45.661263
6387 13:30:45.664034
6388 13:30:45.664131 ==
6389 13:30:45.667526 Dram Type= 6, Freq= 0, CH_0, rank 0
6390 13:30:45.670835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6391 13:30:45.670942 ==
6392 13:30:45.671034
6393 13:30:45.671128
6394 13:30:45.674025 TX Vref Scan disable
6395 13:30:45.674127 == TX Byte 0 ==
6396 13:30:45.677183 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6397 13:30:45.683896 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6398 13:30:45.684025 == TX Byte 1 ==
6399 13:30:45.687583 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6400 13:30:45.694038 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6401 13:30:45.694155 ==
6402 13:30:45.697197 Dram Type= 6, Freq= 0, CH_0, rank 0
6403 13:30:45.700670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6404 13:30:45.700779 ==
6405 13:30:45.700877
6406 13:30:45.700968
6407 13:30:45.703896 TX Vref Scan disable
6408 13:30:45.703980 == TX Byte 0 ==
6409 13:30:45.710376 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6410 13:30:45.713953 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6411 13:30:45.714063 == TX Byte 1 ==
6412 13:30:45.720050 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6413 13:30:45.723438 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6414 13:30:45.723550
6415 13:30:45.723656 [DATLAT]
6416 13:30:45.726936 Freq=400, CH0 RK0
6417 13:30:45.727051
6418 13:30:45.727154 DATLAT Default: 0xf
6419 13:30:45.730482 0, 0xFFFF, sum = 0
6420 13:30:45.730594 1, 0xFFFF, sum = 0
6421 13:30:45.733491 2, 0xFFFF, sum = 0
6422 13:30:45.733600 3, 0xFFFF, sum = 0
6423 13:30:45.736586 4, 0xFFFF, sum = 0
6424 13:30:45.736703 5, 0xFFFF, sum = 0
6425 13:30:45.740077 6, 0xFFFF, sum = 0
6426 13:30:45.740196 7, 0xFFFF, sum = 0
6427 13:30:45.743116 8, 0xFFFF, sum = 0
6428 13:30:45.743227 9, 0xFFFF, sum = 0
6429 13:30:45.746527 10, 0xFFFF, sum = 0
6430 13:30:45.750086 11, 0xFFFF, sum = 0
6431 13:30:45.750199 12, 0xFFFF, sum = 0
6432 13:30:45.753148 13, 0x0, sum = 1
6433 13:30:45.753260 14, 0x0, sum = 2
6434 13:30:45.756423 15, 0x0, sum = 3
6435 13:30:45.756513 16, 0x0, sum = 4
6436 13:30:45.756600 best_step = 14
6437 13:30:45.756681
6438 13:30:45.759535 ==
6439 13:30:45.763205 Dram Type= 6, Freq= 0, CH_0, rank 0
6440 13:30:45.766160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6441 13:30:45.766247 ==
6442 13:30:45.766350 RX Vref Scan: 1
6443 13:30:45.766455
6444 13:30:45.769222 RX Vref 0 -> 0, step: 1
6445 13:30:45.769306
6446 13:30:45.772826 RX Delay -343 -> 252, step: 8
6447 13:30:45.772911
6448 13:30:45.776228 Set Vref, RX VrefLevel [Byte0]: 55
6449 13:30:45.779015 [Byte1]: 43
6450 13:30:45.782887
6451 13:30:45.782976 Final RX Vref Byte 0 = 55 to rank0
6452 13:30:45.786671 Final RX Vref Byte 1 = 43 to rank0
6453 13:30:45.789817 Final RX Vref Byte 0 = 55 to rank1
6454 13:30:45.793367 Final RX Vref Byte 1 = 43 to rank1==
6455 13:30:45.796448 Dram Type= 6, Freq= 0, CH_0, rank 0
6456 13:30:45.802982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6457 13:30:45.803074 ==
6458 13:30:45.803165 DQS Delay:
6459 13:30:45.806616 DQS0 = 44, DQS1 = 56
6460 13:30:45.806694 DQM Delay:
6461 13:30:45.806776 DQM0 = 10, DQM1 = 13
6462 13:30:45.809506 DQ Delay:
6463 13:30:45.812616 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6464 13:30:45.816302 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6465 13:30:45.816390 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6466 13:30:45.822578 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6467 13:30:45.822667
6468 13:30:45.822753
6469 13:30:45.828992 [DQSOSCAuto] RK0, (LSB)MR18= 0x887c, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 392 ps
6470 13:30:45.832338 CH0 RK0: MR19=C0C, MR18=887C
6471 13:30:45.838916 CH0_RK0: MR19=0xC0C, MR18=0x887C, DQSOSC=392, MR23=63, INC=384, DEC=256
6472 13:30:45.839013 ==
6473 13:30:45.842512 Dram Type= 6, Freq= 0, CH_0, rank 1
6474 13:30:45.845510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6475 13:30:45.845606 ==
6476 13:30:45.849077 [Gating] SW mode calibration
6477 13:30:45.855552 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6478 13:30:45.861907 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6479 13:30:45.865528 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6480 13:30:45.869118 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6481 13:30:45.875307 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6482 13:30:45.878303 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6483 13:30:45.882029 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6484 13:30:45.888631 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6485 13:30:45.891485 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6486 13:30:45.895318 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6487 13:30:45.901930 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6488 13:30:45.904729 Total UI for P1: 0, mck2ui 16
6489 13:30:45.908376 best dqsien dly found for B0: ( 0, 14, 24)
6490 13:30:45.911540 Total UI for P1: 0, mck2ui 16
6491 13:30:45.914926 best dqsien dly found for B1: ( 0, 14, 24)
6492 13:30:45.917966 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6493 13:30:45.921559 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6494 13:30:45.921648
6495 13:30:45.924626 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6496 13:30:45.927583 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6497 13:30:45.931165 [Gating] SW calibration Done
6498 13:30:45.931248 ==
6499 13:30:45.934666 Dram Type= 6, Freq= 0, CH_0, rank 1
6500 13:30:45.937533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6501 13:30:45.941070 ==
6502 13:30:45.941158 RX Vref Scan: 0
6503 13:30:45.941244
6504 13:30:45.944756 RX Vref 0 -> 0, step: 1
6505 13:30:45.944842
6506 13:30:45.947385 RX Delay -410 -> 252, step: 16
6507 13:30:45.951167 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6508 13:30:45.954134 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6509 13:30:45.957709 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6510 13:30:45.963938 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6511 13:30:45.967347 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6512 13:30:45.970415 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6513 13:30:45.974084 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6514 13:30:45.980192 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6515 13:30:45.983896 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6516 13:30:45.986915 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6517 13:30:45.993762 iDelay=230, Bit 10, Center -43 (-282 ~ 197) 480
6518 13:30:45.996640 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6519 13:30:46.000385 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6520 13:30:46.003452 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6521 13:30:46.010070 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6522 13:30:46.013641 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6523 13:30:46.013758 ==
6524 13:30:46.016470 Dram Type= 6, Freq= 0, CH_0, rank 1
6525 13:30:46.019753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6526 13:30:46.019861 ==
6527 13:30:46.022819 DQS Delay:
6528 13:30:46.022931 DQS0 = 35, DQS1 = 51
6529 13:30:46.026602 DQM Delay:
6530 13:30:46.026711 DQM0 = 8, DQM1 = 10
6531 13:30:46.026807 DQ Delay:
6532 13:30:46.029821 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6533 13:30:46.032882 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6534 13:30:46.036422 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6535 13:30:46.039725 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6536 13:30:46.039813
6537 13:30:46.039915
6538 13:30:46.039981 ==
6539 13:30:46.042667 Dram Type= 6, Freq= 0, CH_0, rank 1
6540 13:30:46.049249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6541 13:30:46.049342 ==
6542 13:30:46.049430
6543 13:30:46.049511
6544 13:30:46.049590 TX Vref Scan disable
6545 13:30:46.052655 == TX Byte 0 ==
6546 13:30:46.056328 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6547 13:30:46.059192 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6548 13:30:46.062591 == TX Byte 1 ==
6549 13:30:46.065642 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6550 13:30:46.069370 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6551 13:30:46.069456 ==
6552 13:30:46.072179 Dram Type= 6, Freq= 0, CH_0, rank 1
6553 13:30:46.079116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6554 13:30:46.079205 ==
6555 13:30:46.079291
6556 13:30:46.079371
6557 13:30:46.082275 TX Vref Scan disable
6558 13:30:46.082361 == TX Byte 0 ==
6559 13:30:46.085418 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6560 13:30:46.089072 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6561 13:30:46.092000 == TX Byte 1 ==
6562 13:30:46.095667 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6563 13:30:46.098816 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6564 13:30:46.102324
6565 13:30:46.102412 [DATLAT]
6566 13:30:46.102499 Freq=400, CH0 RK1
6567 13:30:46.102580
6568 13:30:46.105393 DATLAT Default: 0xe
6569 13:30:46.105479 0, 0xFFFF, sum = 0
6570 13:30:46.108467 1, 0xFFFF, sum = 0
6571 13:30:46.108580 2, 0xFFFF, sum = 0
6572 13:30:46.112007 3, 0xFFFF, sum = 0
6573 13:30:46.115255 4, 0xFFFF, sum = 0
6574 13:30:46.115362 5, 0xFFFF, sum = 0
6575 13:30:46.118760 6, 0xFFFF, sum = 0
6576 13:30:46.118865 7, 0xFFFF, sum = 0
6577 13:30:46.121818 8, 0xFFFF, sum = 0
6578 13:30:46.121919 9, 0xFFFF, sum = 0
6579 13:30:46.124762 10, 0xFFFF, sum = 0
6580 13:30:46.124839 11, 0xFFFF, sum = 0
6581 13:30:46.128231 12, 0xFFFF, sum = 0
6582 13:30:46.128305 13, 0x0, sum = 1
6583 13:30:46.131498 14, 0x0, sum = 2
6584 13:30:46.131602 15, 0x0, sum = 3
6585 13:30:46.134901 16, 0x0, sum = 4
6586 13:30:46.135001 best_step = 14
6587 13:30:46.135065
6588 13:30:46.135124 ==
6589 13:30:46.138318 Dram Type= 6, Freq= 0, CH_0, rank 1
6590 13:30:46.141680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6591 13:30:46.144947 ==
6592 13:30:46.145026 RX Vref Scan: 0
6593 13:30:46.145090
6594 13:30:46.147849 RX Vref 0 -> 0, step: 1
6595 13:30:46.147946
6596 13:30:46.151503 RX Delay -343 -> 252, step: 8
6597 13:30:46.157955 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6598 13:30:46.161308 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6599 13:30:46.164690 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6600 13:30:46.168241 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6601 13:30:46.174309 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6602 13:30:46.177925 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6603 13:30:46.180913 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6604 13:30:46.184408 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6605 13:30:46.190716 iDelay=209, Bit 8, Center -56 (-295 ~ 184) 480
6606 13:30:46.194327 iDelay=209, Bit 9, Center -56 (-295 ~ 184) 480
6607 13:30:46.197483 iDelay=209, Bit 10, Center -44 (-279 ~ 192) 472
6608 13:30:46.200953 iDelay=209, Bit 11, Center -52 (-287 ~ 184) 472
6609 13:30:46.207254 iDelay=209, Bit 12, Center -40 (-279 ~ 200) 480
6610 13:30:46.210867 iDelay=209, Bit 13, Center -36 (-271 ~ 200) 472
6611 13:30:46.213869 iDelay=209, Bit 14, Center -36 (-271 ~ 200) 472
6612 13:30:46.220137 iDelay=209, Bit 15, Center -40 (-279 ~ 200) 480
6613 13:30:46.220229 ==
6614 13:30:46.223739 Dram Type= 6, Freq= 0, CH_0, rank 1
6615 13:30:46.226816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6616 13:30:46.226897 ==
6617 13:30:46.226980 DQS Delay:
6618 13:30:46.230057 DQS0 = 44, DQS1 = 56
6619 13:30:46.230143 DQM Delay:
6620 13:30:46.233554 DQM0 = 9, DQM1 = 11
6621 13:30:46.233640 DQ Delay:
6622 13:30:46.236989 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6623 13:30:46.239798 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6624 13:30:46.243296 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6625 13:30:46.246394 DQ12 =16, DQ13 =20, DQ14 =20, DQ15 =16
6626 13:30:46.246480
6627 13:30:46.246566
6628 13:30:46.253381 [DQSOSCAuto] RK1, (LSB)MR18= 0x807c, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
6629 13:30:46.256336 CH0 RK1: MR19=C0C, MR18=807C
6630 13:30:46.263435 CH0_RK1: MR19=0xC0C, MR18=0x807C, DQSOSC=393, MR23=63, INC=382, DEC=254
6631 13:30:46.266378 [RxdqsGatingPostProcess] freq 400
6632 13:30:46.272914 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6633 13:30:46.276730 best DQS0 dly(2T, 0.5T) = (0, 10)
6634 13:30:46.279675 best DQS1 dly(2T, 0.5T) = (0, 10)
6635 13:30:46.282770 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6636 13:30:46.286324 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6637 13:30:46.286416 best DQS0 dly(2T, 0.5T) = (0, 10)
6638 13:30:46.289874 best DQS1 dly(2T, 0.5T) = (0, 10)
6639 13:30:46.292553 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6640 13:30:46.296215 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6641 13:30:46.299422 Pre-setting of DQS Precalculation
6642 13:30:46.306042 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6643 13:30:46.306158 ==
6644 13:30:46.309488 Dram Type= 6, Freq= 0, CH_1, rank 0
6645 13:30:46.312712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6646 13:30:46.312797 ==
6647 13:30:46.319171 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6648 13:30:46.325829 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6649 13:30:46.328797 [CA 0] Center 36 (8~64) winsize 57
6650 13:30:46.328897 [CA 1] Center 36 (8~64) winsize 57
6651 13:30:46.332592 [CA 2] Center 36 (8~64) winsize 57
6652 13:30:46.335789 [CA 3] Center 36 (8~64) winsize 57
6653 13:30:46.338790 [CA 4] Center 36 (8~64) winsize 57
6654 13:30:46.342241 [CA 5] Center 36 (8~64) winsize 57
6655 13:30:46.342356
6656 13:30:46.345414 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6657 13:30:46.345516
6658 13:30:46.352370 [CATrainingPosCal] consider 1 rank data
6659 13:30:46.352488 u2DelayCellTimex100 = 270/100 ps
6660 13:30:46.359002 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 13:30:46.362184 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 13:30:46.365403 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 13:30:46.368377 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 13:30:46.371671 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 13:30:46.374933 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 13:30:46.375041
6667 13:30:46.378322 CA PerBit enable=1, Macro0, CA PI delay=36
6668 13:30:46.378398
6669 13:30:46.381573 [CBTSetCACLKResult] CA Dly = 36
6670 13:30:46.385172 CS Dly: 1 (0~32)
6671 13:30:46.385254 ==
6672 13:30:46.388357 Dram Type= 6, Freq= 0, CH_1, rank 1
6673 13:30:46.392029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6674 13:30:46.392116 ==
6675 13:30:46.398378 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6676 13:30:46.404937 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6677 13:30:46.405029 [CA 0] Center 36 (8~64) winsize 57
6678 13:30:46.408085 [CA 1] Center 36 (8~64) winsize 57
6679 13:30:46.411254 [CA 2] Center 36 (8~64) winsize 57
6680 13:30:46.414778 [CA 3] Center 36 (8~64) winsize 57
6681 13:30:46.417624 [CA 4] Center 36 (8~64) winsize 57
6682 13:30:46.421348 [CA 5] Center 36 (8~64) winsize 57
6683 13:30:46.421462
6684 13:30:46.424472 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6685 13:30:46.424562
6686 13:30:46.428031 [CATrainingPosCal] consider 2 rank data
6687 13:30:46.431122 u2DelayCellTimex100 = 270/100 ps
6688 13:30:46.434229 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 13:30:46.441067 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 13:30:46.443842 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 13:30:46.447434 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 13:30:46.450446 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 13:30:46.454239 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 13:30:46.454359
6695 13:30:46.457070 CA PerBit enable=1, Macro0, CA PI delay=36
6696 13:30:46.457159
6697 13:30:46.460587 [CBTSetCACLKResult] CA Dly = 36
6698 13:30:46.463664 CS Dly: 1 (0~32)
6699 13:30:46.463768
6700 13:30:46.467405 ----->DramcWriteLeveling(PI) begin...
6701 13:30:46.467494 ==
6702 13:30:46.470266 Dram Type= 6, Freq= 0, CH_1, rank 0
6703 13:30:46.473848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6704 13:30:46.473936 ==
6705 13:30:46.477089 Write leveling (Byte 0): 40 => 8
6706 13:30:46.480181 Write leveling (Byte 1): 40 => 8
6707 13:30:46.483757 DramcWriteLeveling(PI) end<-----
6708 13:30:46.483869
6709 13:30:46.483969 ==
6710 13:30:46.486952 Dram Type= 6, Freq= 0, CH_1, rank 0
6711 13:30:46.489969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6712 13:30:46.490057 ==
6713 13:30:46.493300 [Gating] SW mode calibration
6714 13:30:46.500129 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6715 13:30:46.506349 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6716 13:30:46.510245 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6717 13:30:46.513283 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6718 13:30:46.519871 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6719 13:30:46.523343 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6720 13:30:46.526705 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6721 13:30:46.532676 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6722 13:30:46.536382 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6723 13:30:46.539550 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6724 13:30:46.546241 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6725 13:30:46.549118 Total UI for P1: 0, mck2ui 16
6726 13:30:46.552789 best dqsien dly found for B0: ( 0, 14, 24)
6727 13:30:46.556402 Total UI for P1: 0, mck2ui 16
6728 13:30:46.559421 best dqsien dly found for B1: ( 0, 14, 24)
6729 13:30:46.562973 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6730 13:30:46.565926 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6731 13:30:46.566013
6732 13:30:46.569532 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6733 13:30:46.572568 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6734 13:30:46.575861 [Gating] SW calibration Done
6735 13:30:46.575959 ==
6736 13:30:46.579377 Dram Type= 6, Freq= 0, CH_1, rank 0
6737 13:30:46.582111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6738 13:30:46.585969 ==
6739 13:30:46.586047 RX Vref Scan: 0
6740 13:30:46.586132
6741 13:30:46.588832 RX Vref 0 -> 0, step: 1
6742 13:30:46.588927
6743 13:30:46.592198 RX Delay -410 -> 252, step: 16
6744 13:30:46.595807 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6745 13:30:46.599049 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6746 13:30:46.602576 iDelay=230, Bit 2, Center -43 (-282 ~ 197) 480
6747 13:30:46.608591 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6748 13:30:46.612197 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6749 13:30:46.615273 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6750 13:30:46.618842 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6751 13:30:46.625396 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6752 13:30:46.628889 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6753 13:30:46.631670 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6754 13:30:46.635102 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6755 13:30:46.641824 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6756 13:30:46.645040 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6757 13:30:46.648635 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6758 13:30:46.654909 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6759 13:30:46.657893 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6760 13:30:46.657980 ==
6761 13:30:46.661720 Dram Type= 6, Freq= 0, CH_1, rank 0
6762 13:30:46.664529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6763 13:30:46.664616 ==
6764 13:30:46.668214 DQS Delay:
6765 13:30:46.668292 DQS0 = 43, DQS1 = 51
6766 13:30:46.671062 DQM Delay:
6767 13:30:46.671137 DQM0 = 13, DQM1 = 13
6768 13:30:46.671217 DQ Delay:
6769 13:30:46.674633 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6770 13:30:46.677753 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6771 13:30:46.681425 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6772 13:30:46.684535 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6773 13:30:46.684608
6774 13:30:46.684668
6775 13:30:46.684726 ==
6776 13:30:46.687536 Dram Type= 6, Freq= 0, CH_1, rank 0
6777 13:30:46.694555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6778 13:30:46.694633 ==
6779 13:30:46.694695
6780 13:30:46.694754
6781 13:30:46.694811 TX Vref Scan disable
6782 13:30:46.697735 == TX Byte 0 ==
6783 13:30:46.701120 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6784 13:30:46.704460 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6785 13:30:46.707513 == TX Byte 1 ==
6786 13:30:46.710810 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6787 13:30:46.714248 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6788 13:30:46.714331 ==
6789 13:30:46.717657 Dram Type= 6, Freq= 0, CH_1, rank 0
6790 13:30:46.724049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6791 13:30:46.724133 ==
6792 13:30:46.724199
6793 13:30:46.724260
6794 13:30:46.724319 TX Vref Scan disable
6795 13:30:46.727114 == TX Byte 0 ==
6796 13:30:46.730804 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6797 13:30:46.733728 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6798 13:30:46.737171 == TX Byte 1 ==
6799 13:30:46.740538 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6800 13:30:46.743685 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6801 13:30:46.746772
6802 13:30:46.746857 [DATLAT]
6803 13:30:46.746926 Freq=400, CH1 RK0
6804 13:30:46.746988
6805 13:30:46.750350 DATLAT Default: 0xf
6806 13:30:46.750433 0, 0xFFFF, sum = 0
6807 13:30:46.753338 1, 0xFFFF, sum = 0
6808 13:30:46.753413 2, 0xFFFF, sum = 0
6809 13:30:46.756779 3, 0xFFFF, sum = 0
6810 13:30:46.756861 4, 0xFFFF, sum = 0
6811 13:30:46.760480 5, 0xFFFF, sum = 0
6812 13:30:46.763435 6, 0xFFFF, sum = 0
6813 13:30:46.763545 7, 0xFFFF, sum = 0
6814 13:30:46.767062 8, 0xFFFF, sum = 0
6815 13:30:46.767138 9, 0xFFFF, sum = 0
6816 13:30:46.769931 10, 0xFFFF, sum = 0
6817 13:30:46.770010 11, 0xFFFF, sum = 0
6818 13:30:46.773689 12, 0xFFFF, sum = 0
6819 13:30:46.773781 13, 0x0, sum = 1
6820 13:30:46.776632 14, 0x0, sum = 2
6821 13:30:46.776701 15, 0x0, sum = 3
6822 13:30:46.780361 16, 0x0, sum = 4
6823 13:30:46.780445 best_step = 14
6824 13:30:46.780510
6825 13:30:46.780570 ==
6826 13:30:46.783255 Dram Type= 6, Freq= 0, CH_1, rank 0
6827 13:30:46.786938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6828 13:30:46.787022 ==
6829 13:30:46.790006 RX Vref Scan: 1
6830 13:30:46.790115
6831 13:30:46.793120 RX Vref 0 -> 0, step: 1
6832 13:30:46.793202
6833 13:30:46.796575 RX Delay -343 -> 252, step: 8
6834 13:30:46.796658
6835 13:30:46.800240 Set Vref, RX VrefLevel [Byte0]: 51
6836 13:30:46.800323 [Byte1]: 58
6837 13:30:46.805362
6838 13:30:46.805444 Final RX Vref Byte 0 = 51 to rank0
6839 13:30:46.809337 Final RX Vref Byte 1 = 58 to rank0
6840 13:30:46.811960 Final RX Vref Byte 0 = 51 to rank1
6841 13:30:46.815690 Final RX Vref Byte 1 = 58 to rank1==
6842 13:30:46.819006 Dram Type= 6, Freq= 0, CH_1, rank 0
6843 13:30:46.825017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6844 13:30:46.825104 ==
6845 13:30:46.825170 DQS Delay:
6846 13:30:46.828662 DQS0 = 44, DQS1 = 56
6847 13:30:46.828746 DQM Delay:
6848 13:30:46.828811 DQM0 = 9, DQM1 = 13
6849 13:30:46.831574 DQ Delay:
6850 13:30:46.835292 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6851 13:30:46.838292 DQ4 =4, DQ5 =16, DQ6 =20, DQ7 =4
6852 13:30:46.838368 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =4
6853 13:30:46.841684 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =20
6854 13:30:46.844987
6855 13:30:46.845082
6856 13:30:46.851742 [DQSOSCAuto] RK0, (LSB)MR18= 0x6a91, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 396 ps
6857 13:30:46.854877 CH1 RK0: MR19=C0C, MR18=6A91
6858 13:30:46.861409 CH1_RK0: MR19=0xC0C, MR18=0x6A91, DQSOSC=391, MR23=63, INC=386, DEC=257
6859 13:30:46.861496 ==
6860 13:30:46.864456 Dram Type= 6, Freq= 0, CH_1, rank 1
6861 13:30:46.868148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6862 13:30:46.868232 ==
6863 13:30:46.871328 [Gating] SW mode calibration
6864 13:30:46.877893 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6865 13:30:46.884551 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6866 13:30:46.887642 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6867 13:30:46.891067 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6868 13:30:46.897726 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6869 13:30:46.900887 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6870 13:30:46.904532 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6871 13:30:46.911064 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6872 13:30:46.913788 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6873 13:30:46.917154 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6874 13:30:46.923811 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6875 13:30:46.927084 Total UI for P1: 0, mck2ui 16
6876 13:30:46.930572 best dqsien dly found for B0: ( 0, 14, 24)
6877 13:30:46.933387 Total UI for P1: 0, mck2ui 16
6878 13:30:46.936782 best dqsien dly found for B1: ( 0, 14, 24)
6879 13:30:46.940396 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6880 13:30:46.943376 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6881 13:30:46.943464
6882 13:30:46.946752 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6883 13:30:46.950081 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6884 13:30:46.953426 [Gating] SW calibration Done
6885 13:30:46.953514 ==
6886 13:30:46.956457 Dram Type= 6, Freq= 0, CH_1, rank 1
6887 13:30:46.960204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6888 13:30:46.963177 ==
6889 13:30:46.963263 RX Vref Scan: 0
6890 13:30:46.963366
6891 13:30:46.966651 RX Vref 0 -> 0, step: 1
6892 13:30:46.966737
6893 13:30:46.969720 RX Delay -410 -> 252, step: 16
6894 13:30:46.972985 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6895 13:30:46.976435 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6896 13:30:46.979416 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6897 13:30:46.986596 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6898 13:30:46.989603 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6899 13:30:46.993160 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6900 13:30:46.996103 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6901 13:30:47.002778 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6902 13:30:47.005853 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6903 13:30:47.009407 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6904 13:30:47.012613 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6905 13:30:47.019261 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6906 13:30:47.022829 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6907 13:30:47.025885 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6908 13:30:47.032615 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6909 13:30:47.035498 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6910 13:30:47.035588 ==
6911 13:30:47.038942 Dram Type= 6, Freq= 0, CH_1, rank 1
6912 13:30:47.042140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6913 13:30:47.042229 ==
6914 13:30:47.045632 DQS Delay:
6915 13:30:47.045719 DQS0 = 43, DQS1 = 51
6916 13:30:47.045806 DQM Delay:
6917 13:30:47.048987 DQM0 = 9, DQM1 = 14
6918 13:30:47.049077 DQ Delay:
6919 13:30:47.052565 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6920 13:30:47.055827 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6921 13:30:47.058621 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6922 13:30:47.062329 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6923 13:30:47.062417
6924 13:30:47.062503
6925 13:30:47.062586 ==
6926 13:30:47.065475 Dram Type= 6, Freq= 0, CH_1, rank 1
6927 13:30:47.068916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6928 13:30:47.071899 ==
6929 13:30:47.071994
6930 13:30:47.072081
6931 13:30:47.072164 TX Vref Scan disable
6932 13:30:47.075568 == TX Byte 0 ==
6933 13:30:47.078520 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6934 13:30:47.081915 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6935 13:30:47.085084 == TX Byte 1 ==
6936 13:30:47.088172 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6937 13:30:47.091475 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6938 13:30:47.091562 ==
6939 13:30:47.095114 Dram Type= 6, Freq= 0, CH_1, rank 1
6940 13:30:47.101574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6941 13:30:47.101664 ==
6942 13:30:47.101752
6943 13:30:47.101816
6944 13:30:47.101876 TX Vref Scan disable
6945 13:30:47.104985 == TX Byte 0 ==
6946 13:30:47.107893 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6947 13:30:47.111802 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6948 13:30:47.114754 == TX Byte 1 ==
6949 13:30:47.117904 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6950 13:30:47.121420 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6951 13:30:47.121504
6952 13:30:47.124712 [DATLAT]
6953 13:30:47.124786 Freq=400, CH1 RK1
6954 13:30:47.124849
6955 13:30:47.127848 DATLAT Default: 0xe
6956 13:30:47.127950 0, 0xFFFF, sum = 0
6957 13:30:47.131316 1, 0xFFFF, sum = 0
6958 13:30:47.131401 2, 0xFFFF, sum = 0
6959 13:30:47.134178 3, 0xFFFF, sum = 0
6960 13:30:47.134262 4, 0xFFFF, sum = 0
6961 13:30:47.137421 5, 0xFFFF, sum = 0
6962 13:30:47.137510 6, 0xFFFF, sum = 0
6963 13:30:47.140818 7, 0xFFFF, sum = 0
6964 13:30:47.144639 8, 0xFFFF, sum = 0
6965 13:30:47.144752 9, 0xFFFF, sum = 0
6966 13:30:47.147429 10, 0xFFFF, sum = 0
6967 13:30:47.147546 11, 0xFFFF, sum = 0
6968 13:30:47.150876 12, 0xFFFF, sum = 0
6969 13:30:47.150961 13, 0x0, sum = 1
6970 13:30:47.154152 14, 0x0, sum = 2
6971 13:30:47.154238 15, 0x0, sum = 3
6972 13:30:47.157528 16, 0x0, sum = 4
6973 13:30:47.157617 best_step = 14
6974 13:30:47.157683
6975 13:30:47.157745 ==
6976 13:30:47.160914 Dram Type= 6, Freq= 0, CH_1, rank 1
6977 13:30:47.163909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6978 13:30:47.164000 ==
6979 13:30:47.167274 RX Vref Scan: 0
6980 13:30:47.167361
6981 13:30:47.170861 RX Vref 0 -> 0, step: 1
6982 13:30:47.170971
6983 13:30:47.171066 RX Delay -343 -> 252, step: 8
6984 13:30:47.179866 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6985 13:30:47.182817 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6986 13:30:47.186251 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6987 13:30:47.192576 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6988 13:30:47.195661 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6989 13:30:47.199270 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6990 13:30:47.202425 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6991 13:30:47.209081 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6992 13:30:47.212669 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6993 13:30:47.215687 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6994 13:30:47.218810 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6995 13:30:47.225437 iDelay=217, Bit 11, Center -48 (-295 ~ 200) 496
6996 13:30:47.229232 iDelay=217, Bit 12, Center -32 (-279 ~ 216) 496
6997 13:30:47.232224 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6998 13:30:47.238713 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6999 13:30:47.241692 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
7000 13:30:47.241768 ==
7001 13:30:47.245044 Dram Type= 6, Freq= 0, CH_1, rank 1
7002 13:30:47.248435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7003 13:30:47.248533 ==
7004 13:30:47.251922 DQS Delay:
7005 13:30:47.252005 DQS0 = 48, DQS1 = 52
7006 13:30:47.252071 DQM Delay:
7007 13:30:47.254883 DQM0 = 11, DQM1 = 10
7008 13:30:47.254968 DQ Delay:
7009 13:30:47.258424 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =12
7010 13:30:47.261385 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
7011 13:30:47.264837 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7012 13:30:47.268436 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
7013 13:30:47.268517
7014 13:30:47.268601
7015 13:30:47.278037 [DQSOSCAuto] RK1, (LSB)MR18= 0x70a6, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
7016 13:30:47.278144 CH1 RK1: MR19=C0C, MR18=70A6
7017 13:30:47.284802 CH1_RK1: MR19=0xC0C, MR18=0x70A6, DQSOSC=389, MR23=63, INC=390, DEC=260
7018 13:30:47.287755 [RxdqsGatingPostProcess] freq 400
7019 13:30:47.294349 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7020 13:30:47.298054 best DQS0 dly(2T, 0.5T) = (0, 10)
7021 13:30:47.301417 best DQS1 dly(2T, 0.5T) = (0, 10)
7022 13:30:47.304341 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7023 13:30:47.307787 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7024 13:30:47.310990 best DQS0 dly(2T, 0.5T) = (0, 10)
7025 13:30:47.314595 best DQS1 dly(2T, 0.5T) = (0, 10)
7026 13:30:47.317492 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7027 13:30:47.320643 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7028 13:30:47.324099 Pre-setting of DQS Precalculation
7029 13:30:47.327105 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7030 13:30:47.333972 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7031 13:30:47.340479 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7032 13:30:47.343662
7033 13:30:47.343749
7034 13:30:47.343853 [Calibration Summary] 800 Mbps
7035 13:30:47.346766 CH 0, Rank 0
7036 13:30:47.346877 SW Impedance : PASS
7037 13:30:47.350261 DUTY Scan : NO K
7038 13:30:47.353560 ZQ Calibration : PASS
7039 13:30:47.353645 Jitter Meter : NO K
7040 13:30:47.356813 CBT Training : PASS
7041 13:30:47.360468 Write leveling : PASS
7042 13:30:47.360552 RX DQS gating : PASS
7043 13:30:47.363549 RX DQ/DQS(RDDQC) : PASS
7044 13:30:47.366984 TX DQ/DQS : PASS
7045 13:30:47.367063 RX DATLAT : PASS
7046 13:30:47.369937 RX DQ/DQS(Engine): PASS
7047 13:30:47.373567 TX OE : NO K
7048 13:30:47.373650 All Pass.
7049 13:30:47.373734
7050 13:30:47.373814 CH 0, Rank 1
7051 13:30:47.376388 SW Impedance : PASS
7052 13:30:47.379719 DUTY Scan : NO K
7053 13:30:47.379794 ZQ Calibration : PASS
7054 13:30:47.383025 Jitter Meter : NO K
7055 13:30:47.386570 CBT Training : PASS
7056 13:30:47.386647 Write leveling : NO K
7057 13:30:47.389763 RX DQS gating : PASS
7058 13:30:47.392864 RX DQ/DQS(RDDQC) : PASS
7059 13:30:47.392942 TX DQ/DQS : PASS
7060 13:30:47.396198 RX DATLAT : PASS
7061 13:30:47.399653 RX DQ/DQS(Engine): PASS
7062 13:30:47.399729 TX OE : NO K
7063 13:30:47.402603 All Pass.
7064 13:30:47.402681
7065 13:30:47.402764 CH 1, Rank 0
7066 13:30:47.406217 SW Impedance : PASS
7067 13:30:47.406304 DUTY Scan : NO K
7068 13:30:47.409090 ZQ Calibration : PASS
7069 13:30:47.412749 Jitter Meter : NO K
7070 13:30:47.412838 CBT Training : PASS
7071 13:30:47.415742 Write leveling : PASS
7072 13:30:47.419463 RX DQS gating : PASS
7073 13:30:47.419549 RX DQ/DQS(RDDQC) : PASS
7074 13:30:47.422442 TX DQ/DQS : PASS
7075 13:30:47.425471 RX DATLAT : PASS
7076 13:30:47.425557 RX DQ/DQS(Engine): PASS
7077 13:30:47.429108 TX OE : NO K
7078 13:30:47.429193 All Pass.
7079 13:30:47.429280
7080 13:30:47.432174 CH 1, Rank 1
7081 13:30:47.432259 SW Impedance : PASS
7082 13:30:47.435862 DUTY Scan : NO K
7083 13:30:47.438950 ZQ Calibration : PASS
7084 13:30:47.439037 Jitter Meter : NO K
7085 13:30:47.441996 CBT Training : PASS
7086 13:30:47.442082 Write leveling : NO K
7087 13:30:47.445631 RX DQS gating : PASS
7088 13:30:47.448838 RX DQ/DQS(RDDQC) : PASS
7089 13:30:47.448936 TX DQ/DQS : PASS
7090 13:30:47.452367 RX DATLAT : PASS
7091 13:30:47.455392 RX DQ/DQS(Engine): PASS
7092 13:30:47.455572 TX OE : NO K
7093 13:30:47.458897 All Pass.
7094 13:30:47.459024
7095 13:30:47.459120 DramC Write-DBI off
7096 13:30:47.462188 PER_BANK_REFRESH: Hybrid Mode
7097 13:30:47.465472 TX_TRACKING: ON
7098 13:30:47.471822 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7099 13:30:47.475392 [FAST_K] Save calibration result to emmc
7100 13:30:47.481635 dramc_set_vcore_voltage set vcore to 725000
7101 13:30:47.481736 Read voltage for 1600, 0
7102 13:30:47.481825 Vio18 = 0
7103 13:30:47.485151 Vcore = 725000
7104 13:30:47.485237 Vdram = 0
7105 13:30:47.485328 Vddq = 0
7106 13:30:47.488093 Vmddr = 0
7107 13:30:47.491671 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7108 13:30:47.498156 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7109 13:30:47.501544 MEM_TYPE=3, freq_sel=13
7110 13:30:47.501626 sv_algorithm_assistance_LP4_3733
7111 13:30:47.508381 ============ PULL DRAM RESETB DOWN ============
7112 13:30:47.511407 ========== PULL DRAM RESETB DOWN end =========
7113 13:30:47.514426 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7114 13:30:47.518164 ===================================
7115 13:30:47.521131 LPDDR4 DRAM CONFIGURATION
7116 13:30:47.524796 ===================================
7117 13:30:47.527740 EX_ROW_EN[0] = 0x0
7118 13:30:47.527849 EX_ROW_EN[1] = 0x0
7119 13:30:47.531392 LP4Y_EN = 0x0
7120 13:30:47.531477 WORK_FSP = 0x1
7121 13:30:47.534447 WL = 0x5
7122 13:30:47.534533 RL = 0x5
7123 13:30:47.537635 BL = 0x2
7124 13:30:47.537721 RPST = 0x0
7125 13:30:47.541289 RD_PRE = 0x0
7126 13:30:47.541375 WR_PRE = 0x1
7127 13:30:47.544423 WR_PST = 0x1
7128 13:30:47.547411 DBI_WR = 0x0
7129 13:30:47.547497 DBI_RD = 0x0
7130 13:30:47.551092 OTF = 0x1
7131 13:30:47.554073 ===================================
7132 13:30:47.557227 ===================================
7133 13:30:47.557313 ANA top config
7134 13:30:47.561024 ===================================
7135 13:30:47.564023 DLL_ASYNC_EN = 0
7136 13:30:47.567540 ALL_SLAVE_EN = 0
7137 13:30:47.567652 NEW_RANK_MODE = 1
7138 13:30:47.570472 DLL_IDLE_MODE = 1
7139 13:30:47.573759 LP45_APHY_COMB_EN = 1
7140 13:30:47.577164 TX_ODT_DIS = 0
7141 13:30:47.580236 NEW_8X_MODE = 1
7142 13:30:47.583874 ===================================
7143 13:30:47.586744 ===================================
7144 13:30:47.586830 data_rate = 3200
7145 13:30:47.590125 CKR = 1
7146 13:30:47.593418 DQ_P2S_RATIO = 8
7147 13:30:47.596839 ===================================
7148 13:30:47.600581 CA_P2S_RATIO = 8
7149 13:30:47.603744 DQ_CA_OPEN = 0
7150 13:30:47.606719 DQ_SEMI_OPEN = 0
7151 13:30:47.606806 CA_SEMI_OPEN = 0
7152 13:30:47.610438 CA_FULL_RATE = 0
7153 13:30:47.613150 DQ_CKDIV4_EN = 0
7154 13:30:47.616442 CA_CKDIV4_EN = 0
7155 13:30:47.619844 CA_PREDIV_EN = 0
7156 13:30:47.623391 PH8_DLY = 12
7157 13:30:47.626513 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7158 13:30:47.626632 DQ_AAMCK_DIV = 4
7159 13:30:47.629976 CA_AAMCK_DIV = 4
7160 13:30:47.632862 CA_ADMCK_DIV = 4
7161 13:30:47.636679 DQ_TRACK_CA_EN = 0
7162 13:30:47.639592 CA_PICK = 1600
7163 13:30:47.642828 CA_MCKIO = 1600
7164 13:30:47.646444 MCKIO_SEMI = 0
7165 13:30:47.646553 PLL_FREQ = 3068
7166 13:30:47.649599 DQ_UI_PI_RATIO = 32
7167 13:30:47.652624 CA_UI_PI_RATIO = 0
7168 13:30:47.656370 ===================================
7169 13:30:47.659371 ===================================
7170 13:30:47.662553 memory_type:LPDDR4
7171 13:30:47.666176 GP_NUM : 10
7172 13:30:47.666293 SRAM_EN : 1
7173 13:30:47.669355 MD32_EN : 0
7174 13:30:47.672538 ===================================
7175 13:30:47.672676 [ANA_INIT] >>>>>>>>>>>>>>
7176 13:30:47.675475 <<<<<< [CONFIGURE PHASE]: ANA_TX
7177 13:30:47.678931 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7178 13:30:47.682251 ===================================
7179 13:30:47.685570 data_rate = 3200,PCW = 0X7600
7180 13:30:47.689059 ===================================
7181 13:30:47.692173 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7182 13:30:47.698845 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7183 13:30:47.705437 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7184 13:30:47.708492 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7185 13:30:47.712220 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7186 13:30:47.715216 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7187 13:30:47.718848 [ANA_INIT] flow start
7188 13:30:47.718972 [ANA_INIT] PLL >>>>>>>>
7189 13:30:47.721834 [ANA_INIT] PLL <<<<<<<<
7190 13:30:47.725577 [ANA_INIT] MIDPI >>>>>>>>
7191 13:30:47.728787 [ANA_INIT] MIDPI <<<<<<<<
7192 13:30:47.728901 [ANA_INIT] DLL >>>>>>>>
7193 13:30:47.732178 [ANA_INIT] DLL <<<<<<<<
7194 13:30:47.732271 [ANA_INIT] flow end
7195 13:30:47.738328 ============ LP4 DIFF to SE enter ============
7196 13:30:47.741973 ============ LP4 DIFF to SE exit ============
7197 13:30:47.744955 [ANA_INIT] <<<<<<<<<<<<<
7198 13:30:47.748108 [Flow] Enable top DCM control >>>>>
7199 13:30:47.751711 [Flow] Enable top DCM control <<<<<
7200 13:30:47.754810 Enable DLL master slave shuffle
7201 13:30:47.758024 ==============================================================
7202 13:30:47.761723 Gating Mode config
7203 13:30:47.764768 ==============================================================
7204 13:30:47.767982 Config description:
7205 13:30:47.777746 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7206 13:30:47.784466 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7207 13:30:47.787809 SELPH_MODE 0: By rank 1: By Phase
7208 13:30:47.794672 ==============================================================
7209 13:30:47.797452 GAT_TRACK_EN = 1
7210 13:30:47.801085 RX_GATING_MODE = 2
7211 13:30:47.804511 RX_GATING_TRACK_MODE = 2
7212 13:30:47.807391 SELPH_MODE = 1
7213 13:30:47.810700 PICG_EARLY_EN = 1
7214 13:30:47.814211 VALID_LAT_VALUE = 1
7215 13:30:47.817726 ==============================================================
7216 13:30:47.820675 Enter into Gating configuration >>>>
7217 13:30:47.824265 Exit from Gating configuration <<<<
7218 13:30:47.827409 Enter into DVFS_PRE_config >>>>>
7219 13:30:47.840411 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7220 13:30:47.840544 Exit from DVFS_PRE_config <<<<<
7221 13:30:47.843840 Enter into PICG configuration >>>>
7222 13:30:47.847146 Exit from PICG configuration <<<<
7223 13:30:47.850600 [RX_INPUT] configuration >>>>>
7224 13:30:47.853672 [RX_INPUT] configuration <<<<<
7225 13:30:47.860372 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7226 13:30:47.863520 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7227 13:30:47.870330 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7228 13:30:47.876563 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7229 13:30:47.883406 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7230 13:30:47.890076 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7231 13:30:47.892980 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7232 13:30:47.896626 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7233 13:30:47.903018 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7234 13:30:47.906397 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7235 13:30:47.909905 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7236 13:30:47.912827 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7237 13:30:47.916317 ===================================
7238 13:30:47.919697 LPDDR4 DRAM CONFIGURATION
7239 13:30:47.922956 ===================================
7240 13:30:47.925984 EX_ROW_EN[0] = 0x0
7241 13:30:47.926094 EX_ROW_EN[1] = 0x0
7242 13:30:47.929537 LP4Y_EN = 0x0
7243 13:30:47.929644 WORK_FSP = 0x1
7244 13:30:47.932725 WL = 0x5
7245 13:30:47.932836 RL = 0x5
7246 13:30:47.936370 BL = 0x2
7247 13:30:47.936480 RPST = 0x0
7248 13:30:47.939542 RD_PRE = 0x0
7249 13:30:47.939656 WR_PRE = 0x1
7250 13:30:47.942756 WR_PST = 0x1
7251 13:30:47.945877 DBI_WR = 0x0
7252 13:30:47.945997 DBI_RD = 0x0
7253 13:30:47.949437 OTF = 0x1
7254 13:30:47.952438 ===================================
7255 13:30:47.955960 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7256 13:30:47.958772 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7257 13:30:47.962503 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7258 13:30:47.965541 ===================================
7259 13:30:47.969112 LPDDR4 DRAM CONFIGURATION
7260 13:30:47.972192 ===================================
7261 13:30:47.975324 EX_ROW_EN[0] = 0x10
7262 13:30:47.975439 EX_ROW_EN[1] = 0x0
7263 13:30:47.979093 LP4Y_EN = 0x0
7264 13:30:47.979211 WORK_FSP = 0x1
7265 13:30:47.982060 WL = 0x5
7266 13:30:47.982166 RL = 0x5
7267 13:30:47.985134 BL = 0x2
7268 13:30:47.988914 RPST = 0x0
7269 13:30:47.989036 RD_PRE = 0x0
7270 13:30:47.991996 WR_PRE = 0x1
7271 13:30:47.992113 WR_PST = 0x1
7272 13:30:47.995610 DBI_WR = 0x0
7273 13:30:47.995725 DBI_RD = 0x0
7274 13:30:47.998613 OTF = 0x1
7275 13:30:48.001632 ===================================
7276 13:30:48.008031 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7277 13:30:48.008112 ==
7278 13:30:48.011562 Dram Type= 6, Freq= 0, CH_0, rank 0
7279 13:30:48.014938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7280 13:30:48.015017 ==
7281 13:30:48.018406 [Duty_Offset_Calibration]
7282 13:30:48.018513 B0:2 B1:0 CA:4
7283 13:30:48.018608
7284 13:30:48.021176 [DutyScan_Calibration_Flow] k_type=0
7285 13:30:48.031285
7286 13:30:48.031398 ==CLK 0==
7287 13:30:48.034065 Final CLK duty delay cell = -4
7288 13:30:48.037648 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7289 13:30:48.041298 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7290 13:30:48.044185 [-4] AVG Duty = 4937%(X100)
7291 13:30:48.044292
7292 13:30:48.047778 CH0 CLK Duty spec in!! Max-Min= 187%
7293 13:30:48.050872 [DutyScan_Calibration_Flow] ====Done====
7294 13:30:48.050978
7295 13:30:48.054119 [DutyScan_Calibration_Flow] k_type=1
7296 13:30:48.070500
7297 13:30:48.070626 ==DQS 0 ==
7298 13:30:48.073593 Final DQS duty delay cell = -4
7299 13:30:48.076711 [-4] MAX Duty = 4938%(X100), DQS PI = 46
7300 13:30:48.080427 [-4] MIN Duty = 4782%(X100), DQS PI = 2
7301 13:30:48.083527 [-4] AVG Duty = 4860%(X100)
7302 13:30:48.083635
7303 13:30:48.083739 ==DQS 1 ==
7304 13:30:48.086639 Final DQS duty delay cell = 0
7305 13:30:48.090344 [0] MAX Duty = 5187%(X100), DQS PI = 0
7306 13:30:48.093297 [0] MIN Duty = 4969%(X100), DQS PI = 12
7307 13:30:48.096707 [0] AVG Duty = 5078%(X100)
7308 13:30:48.096817
7309 13:30:48.099767 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7310 13:30:48.099878
7311 13:30:48.103531 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7312 13:30:48.106576 [DutyScan_Calibration_Flow] ====Done====
7313 13:30:48.106695
7314 13:30:48.110029 [DutyScan_Calibration_Flow] k_type=3
7315 13:30:48.127897
7316 13:30:48.128023 ==DQM 0 ==
7317 13:30:48.131334 Final DQM duty delay cell = 0
7318 13:30:48.134183 [0] MAX Duty = 5124%(X100), DQS PI = 22
7319 13:30:48.137471 [0] MIN Duty = 4844%(X100), DQS PI = 56
7320 13:30:48.140814 [0] AVG Duty = 4984%(X100)
7321 13:30:48.140934
7322 13:30:48.141036 ==DQM 1 ==
7323 13:30:48.144402 Final DQM duty delay cell = 0
7324 13:30:48.147512 [0] MAX Duty = 5000%(X100), DQS PI = 2
7325 13:30:48.150657 [0] MIN Duty = 4844%(X100), DQS PI = 10
7326 13:30:48.154253 [0] AVG Duty = 4922%(X100)
7327 13:30:48.154361
7328 13:30:48.157295 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7329 13:30:48.157408
7330 13:30:48.161006 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7331 13:30:48.164077 [DutyScan_Calibration_Flow] ====Done====
7332 13:30:48.164198
7333 13:30:48.166991 [DutyScan_Calibration_Flow] k_type=2
7334 13:30:48.184854
7335 13:30:48.184967 ==DQ 0 ==
7336 13:30:48.188455 Final DQ duty delay cell = 0
7337 13:30:48.191568 [0] MAX Duty = 5124%(X100), DQS PI = 20
7338 13:30:48.195177 [0] MIN Duty = 4938%(X100), DQS PI = 12
7339 13:30:48.195284 [0] AVG Duty = 5031%(X100)
7340 13:30:48.198375
7341 13:30:48.198486 ==DQ 1 ==
7342 13:30:48.201373 Final DQ duty delay cell = 0
7343 13:30:48.204893 [0] MAX Duty = 5187%(X100), DQS PI = 4
7344 13:30:48.208023 [0] MIN Duty = 4907%(X100), DQS PI = 34
7345 13:30:48.208135 [0] AVG Duty = 5047%(X100)
7346 13:30:48.211555
7347 13:30:48.214489 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7348 13:30:48.214599
7349 13:30:48.218154 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7350 13:30:48.221332 [DutyScan_Calibration_Flow] ====Done====
7351 13:30:48.221439 ==
7352 13:30:48.224399 Dram Type= 6, Freq= 0, CH_1, rank 0
7353 13:30:48.227574 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7354 13:30:48.227681 ==
7355 13:30:48.231206 [Duty_Offset_Calibration]
7356 13:30:48.231317 B0:0 B1:-1 CA:3
7357 13:30:48.231411
7358 13:30:48.234131 [DutyScan_Calibration_Flow] k_type=0
7359 13:30:48.244219
7360 13:30:48.244301 ==CLK 0==
7361 13:30:48.247875 Final CLK duty delay cell = -4
7362 13:30:48.250858 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7363 13:30:48.254116 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7364 13:30:48.257682 [-4] AVG Duty = 4922%(X100)
7365 13:30:48.257789
7366 13:30:48.260904 CH1 CLK Duty spec in!! Max-Min= 156%
7367 13:30:48.263894 [DutyScan_Calibration_Flow] ====Done====
7368 13:30:48.263978
7369 13:30:48.267119 [DutyScan_Calibration_Flow] k_type=1
7370 13:30:48.283696
7371 13:30:48.283815 ==DQS 0 ==
7372 13:30:48.286772 Final DQS duty delay cell = 0
7373 13:30:48.289868 [0] MAX Duty = 5250%(X100), DQS PI = 28
7374 13:30:48.293600 [0] MIN Duty = 4907%(X100), DQS PI = 60
7375 13:30:48.296759 [0] AVG Duty = 5078%(X100)
7376 13:30:48.296871
7377 13:30:48.296965 ==DQS 1 ==
7378 13:30:48.299794 Final DQS duty delay cell = -4
7379 13:30:48.303431 [-4] MAX Duty = 5000%(X100), DQS PI = 28
7380 13:30:48.306522 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7381 13:30:48.310141 [-4] AVG Duty = 4922%(X100)
7382 13:30:48.310256
7383 13:30:48.313137 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7384 13:30:48.313248
7385 13:30:48.316179 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7386 13:30:48.319838 [DutyScan_Calibration_Flow] ====Done====
7387 13:30:48.319956
7388 13:30:48.322869 [DutyScan_Calibration_Flow] k_type=3
7389 13:30:48.340699
7390 13:30:48.340813 ==DQM 0 ==
7391 13:30:48.344144 Final DQM duty delay cell = 0
7392 13:30:48.347008 [0] MAX Duty = 5062%(X100), DQS PI = 30
7393 13:30:48.350955 [0] MIN Duty = 4750%(X100), DQS PI = 40
7394 13:30:48.354082 [0] AVG Duty = 4906%(X100)
7395 13:30:48.354187
7396 13:30:48.354285 ==DQM 1 ==
7397 13:30:48.357173 Final DQM duty delay cell = 0
7398 13:30:48.360814 [0] MAX Duty = 5000%(X100), DQS PI = 32
7399 13:30:48.363708 [0] MIN Duty = 4813%(X100), DQS PI = 10
7400 13:30:48.367235 [0] AVG Duty = 4906%(X100)
7401 13:30:48.367336
7402 13:30:48.370195 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7403 13:30:48.370307
7404 13:30:48.373630 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7405 13:30:48.376774 [DutyScan_Calibration_Flow] ====Done====
7406 13:30:48.376852
7407 13:30:48.379826 [DutyScan_Calibration_Flow] k_type=2
7408 13:30:48.397232
7409 13:30:48.397343 ==DQ 0 ==
7410 13:30:48.400382 Final DQ duty delay cell = -4
7411 13:30:48.403523 [-4] MAX Duty = 4938%(X100), DQS PI = 16
7412 13:30:48.407026 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7413 13:30:48.410171 [-4] AVG Duty = 4875%(X100)
7414 13:30:48.410271
7415 13:30:48.410362 ==DQ 1 ==
7416 13:30:48.413123 Final DQ duty delay cell = 0
7417 13:30:48.416926 [0] MAX Duty = 5031%(X100), DQS PI = 32
7418 13:30:48.419803 [0] MIN Duty = 4875%(X100), DQS PI = 52
7419 13:30:48.423434 [0] AVG Duty = 4953%(X100)
7420 13:30:48.423547
7421 13:30:48.426552 CH1 DQ 0 Duty spec in!! Max-Min= 125%
7422 13:30:48.426652
7423 13:30:48.429636 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7424 13:30:48.433266 [DutyScan_Calibration_Flow] ====Done====
7425 13:30:48.436318 nWR fixed to 30
7426 13:30:48.439900 [ModeRegInit_LP4] CH0 RK0
7427 13:30:48.440015 [ModeRegInit_LP4] CH0 RK1
7428 13:30:48.443118 [ModeRegInit_LP4] CH1 RK0
7429 13:30:48.446126 [ModeRegInit_LP4] CH1 RK1
7430 13:30:48.446239 match AC timing 5
7431 13:30:48.452866 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7432 13:30:48.455888 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7433 13:30:48.459293 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7434 13:30:48.466183 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7435 13:30:48.469595 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7436 13:30:48.472604 [MiockJmeterHQA]
7437 13:30:48.472726
7438 13:30:48.476219 [DramcMiockJmeter] u1RxGatingPI = 0
7439 13:30:48.476303 0 : 4363, 4137
7440 13:30:48.476371 4 : 4252, 4027
7441 13:30:48.479147 8 : 4253, 4026
7442 13:30:48.479232 12 : 4253, 4027
7443 13:30:48.482785 16 : 4253, 4026
7444 13:30:48.482869 20 : 4363, 4138
7445 13:30:48.486129 24 : 4252, 4026
7446 13:30:48.486213 28 : 4363, 4137
7447 13:30:48.486280 32 : 4253, 4026
7448 13:30:48.489400 36 : 4252, 4027
7449 13:30:48.489484 40 : 4252, 4027
7450 13:30:48.492648 44 : 4361, 4138
7451 13:30:48.492731 48 : 4363, 4138
7452 13:30:48.495436 52 : 4250, 4026
7453 13:30:48.495547 56 : 4252, 4027
7454 13:30:48.499151 60 : 4252, 4027
7455 13:30:48.499235 64 : 4250, 4026
7456 13:30:48.499303 68 : 4252, 4027
7457 13:30:48.502556 72 : 4360, 4137
7458 13:30:48.502641 76 : 4250, 4027
7459 13:30:48.505598 80 : 4249, 4027
7460 13:30:48.505682 84 : 4250, 4026
7461 13:30:48.508591 88 : 4250, 4027
7462 13:30:48.508675 92 : 4249, 4027
7463 13:30:48.512245 96 : 4361, 3110
7464 13:30:48.512329 100 : 4361, 0
7465 13:30:48.512396 104 : 4250, 0
7466 13:30:48.515210 108 : 4249, 0
7467 13:30:48.515294 112 : 4363, 0
7468 13:30:48.518717 116 : 4250, 0
7469 13:30:48.518801 120 : 4250, 0
7470 13:30:48.518869 124 : 4250, 0
7471 13:30:48.521871 128 : 4250, 0
7472 13:30:48.521955 132 : 4250, 0
7473 13:30:48.525459 136 : 4249, 0
7474 13:30:48.525544 140 : 4252, 0
7475 13:30:48.525611 144 : 4361, 0
7476 13:30:48.528573 148 : 4250, 0
7477 13:30:48.528657 152 : 4360, 0
7478 13:30:48.528723 156 : 4250, 0
7479 13:30:48.531746 160 : 4361, 0
7480 13:30:48.531857 164 : 4249, 0
7481 13:30:48.535575 168 : 4250, 0
7482 13:30:48.535690 172 : 4250, 0
7483 13:30:48.535798 176 : 4249, 0
7484 13:30:48.538648 180 : 4252, 0
7485 13:30:48.538762 184 : 4250, 0
7486 13:30:48.541713 188 : 4249, 0
7487 13:30:48.541830 192 : 4250, 0
7488 13:30:48.541931 196 : 4360, 0
7489 13:30:48.544881 200 : 4250, 0
7490 13:30:48.544989 204 : 4360, 0
7491 13:30:48.548539 208 : 4249, 0
7492 13:30:48.548644 212 : 4361, 0
7493 13:30:48.548743 216 : 4249, 0
7494 13:30:48.551576 220 : 4250, 485
7495 13:30:48.551688 224 : 4249, 3983
7496 13:30:48.554709 228 : 4249, 4027
7497 13:30:48.554815 232 : 4360, 4137
7498 13:30:48.558459 236 : 4250, 4026
7499 13:30:48.558572 240 : 4249, 4027
7500 13:30:48.561485 244 : 4360, 4137
7501 13:30:48.561596 248 : 4250, 4026
7502 13:30:48.564486 252 : 4250, 4027
7503 13:30:48.564593 256 : 4361, 4138
7504 13:30:48.568065 260 : 4249, 4027
7505 13:30:48.568142 264 : 4250, 4026
7506 13:30:48.568206 268 : 4250, 4027
7507 13:30:48.571414 272 : 4252, 4030
7508 13:30:48.571518 276 : 4250, 4027
7509 13:30:48.574369 280 : 4250, 4027
7510 13:30:48.574453 284 : 4361, 4137
7511 13:30:48.577707 288 : 4250, 4027
7512 13:30:48.577811 292 : 4249, 4027
7513 13:30:48.581098 296 : 4360, 4137
7514 13:30:48.581209 300 : 4250, 4026
7515 13:30:48.584365 304 : 4250, 4026
7516 13:30:48.584466 308 : 4360, 4138
7517 13:30:48.588004 312 : 4249, 4027
7518 13:30:48.588088 316 : 4250, 4026
7519 13:30:48.590950 320 : 4250, 4026
7520 13:30:48.591034 324 : 4250, 4027
7521 13:30:48.594370 328 : 4249, 4027
7522 13:30:48.594454 332 : 4250, 4017
7523 13:30:48.594521 336 : 4363, 2325
7524 13:30:48.597636 340 : 4250, 4
7525 13:30:48.597760
7526 13:30:48.601184 MIOCK jitter meter ch=0
7527 13:30:48.601292
7528 13:30:48.604095 1T = (340-100) = 240 dly cells
7529 13:30:48.607564 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7530 13:30:48.607670 ==
7531 13:30:48.610871 Dram Type= 6, Freq= 0, CH_0, rank 0
7532 13:30:48.617677 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7533 13:30:48.617763 ==
7534 13:30:48.620703 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7535 13:30:48.627360 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7536 13:30:48.630887 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7537 13:30:48.637038 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7538 13:30:48.645196 [CA 0] Center 43 (13~74) winsize 62
7539 13:30:48.648217 [CA 1] Center 42 (12~73) winsize 62
7540 13:30:48.651386 [CA 2] Center 37 (8~67) winsize 60
7541 13:30:48.654501 [CA 3] Center 37 (8~67) winsize 60
7542 13:30:48.658133 [CA 4] Center 36 (6~66) winsize 61
7543 13:30:48.661162 [CA 5] Center 35 (5~66) winsize 62
7544 13:30:48.661267
7545 13:30:48.664948 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7546 13:30:48.665056
7547 13:30:48.670902 [CATrainingPosCal] consider 1 rank data
7548 13:30:48.670988 u2DelayCellTimex100 = 271/100 ps
7549 13:30:48.677547 CA0 delay=43 (13~74),Diff = 8 PI (28 cell)
7550 13:30:48.681137 CA1 delay=42 (12~73),Diff = 7 PI (25 cell)
7551 13:30:48.684349 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7552 13:30:48.687650 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7553 13:30:48.691028 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7554 13:30:48.693820 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7555 13:30:48.693944
7556 13:30:48.698083 CA PerBit enable=1, Macro0, CA PI delay=35
7557 13:30:48.698203
7558 13:30:48.700426 [CBTSetCACLKResult] CA Dly = 35
7559 13:30:48.703793 CS Dly: 11 (0~42)
7560 13:30:48.707326 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7561 13:30:48.710321 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7562 13:30:48.710435 ==
7563 13:30:48.713846 Dram Type= 6, Freq= 0, CH_0, rank 1
7564 13:30:48.720035 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7565 13:30:48.720118 ==
7566 13:30:48.723648 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7567 13:30:48.729834 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7568 13:30:48.733362 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7569 13:30:48.739925 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7570 13:30:48.748588 [CA 0] Center 44 (14~75) winsize 62
7571 13:30:48.751604 [CA 1] Center 44 (14~74) winsize 61
7572 13:30:48.754757 [CA 2] Center 39 (10~69) winsize 60
7573 13:30:48.758400 [CA 3] Center 39 (10~68) winsize 59
7574 13:30:48.761457 [CA 4] Center 37 (7~67) winsize 61
7575 13:30:48.764574 [CA 5] Center 36 (7~66) winsize 60
7576 13:30:48.764658
7577 13:30:48.768213 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7578 13:30:48.768298
7579 13:30:48.774420 [CATrainingPosCal] consider 2 rank data
7580 13:30:48.774504 u2DelayCellTimex100 = 271/100 ps
7581 13:30:48.781164 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7582 13:30:48.784285 CA1 delay=43 (14~73),Diff = 7 PI (25 cell)
7583 13:30:48.787446 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7584 13:30:48.791005 CA3 delay=38 (10~67),Diff = 2 PI (7 cell)
7585 13:30:48.794552 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7586 13:30:48.797643 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7587 13:30:48.797727
7588 13:30:48.800943 CA PerBit enable=1, Macro0, CA PI delay=36
7589 13:30:48.801027
7590 13:30:48.804598 [CBTSetCACLKResult] CA Dly = 36
7591 13:30:48.807666 CS Dly: 11 (0~43)
7592 13:30:48.811024 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7593 13:30:48.814215 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7594 13:30:48.814299
7595 13:30:48.817296 ----->DramcWriteLeveling(PI) begin...
7596 13:30:48.820794 ==
7597 13:30:48.823863 Dram Type= 6, Freq= 0, CH_0, rank 0
7598 13:30:48.827495 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7599 13:30:48.827569 ==
7600 13:30:48.830541 Write leveling (Byte 0): 36 => 36
7601 13:30:48.833642 Write leveling (Byte 1): 28 => 28
7602 13:30:48.837067 DramcWriteLeveling(PI) end<-----
7603 13:30:48.837141
7604 13:30:48.837204 ==
7605 13:30:48.840447 Dram Type= 6, Freq= 0, CH_0, rank 0
7606 13:30:48.843627 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7607 13:30:48.843700 ==
7608 13:30:48.847088 [Gating] SW mode calibration
7609 13:30:48.853855 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7610 13:30:48.860629 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7611 13:30:48.863645 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7612 13:30:48.866729 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7613 13:30:48.873573 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7614 13:30:48.876621 1 4 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7615 13:30:48.880207 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7616 13:30:48.886756 1 4 20 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
7617 13:30:48.889792 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7618 13:30:48.893431 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7619 13:30:48.899472 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7620 13:30:48.903174 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7621 13:30:48.906136 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7622 13:30:48.912667 1 5 12 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 0)
7623 13:30:48.916293 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7624 13:30:48.919232 1 5 20 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
7625 13:30:48.926158 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
7626 13:30:48.929008 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7627 13:30:48.932543 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7628 13:30:48.939348 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7629 13:30:48.942341 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7630 13:30:48.945924 1 6 12 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
7631 13:30:48.952220 1 6 16 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
7632 13:30:48.955789 1 6 20 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
7633 13:30:48.958591 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7634 13:30:48.965448 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7635 13:30:48.968584 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7636 13:30:48.972212 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7637 13:30:48.978470 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7638 13:30:48.981519 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7639 13:30:48.985096 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7640 13:30:48.991443 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7641 13:30:48.994627 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7642 13:30:48.998154 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 13:30:49.004806 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 13:30:49.007848 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 13:30:49.011025 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 13:30:49.017983 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 13:30:49.021087 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 13:30:49.024751 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 13:30:49.030673 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 13:30:49.034432 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 13:30:49.040806 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 13:30:49.044348 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 13:30:49.047424 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7654 13:30:49.053618 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7655 13:30:49.057087 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7656 13:30:49.060552 Total UI for P1: 0, mck2ui 16
7657 13:30:49.063513 best dqsien dly found for B0: ( 1, 9, 10)
7658 13:30:49.066996 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7659 13:30:49.073761 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7660 13:30:49.073849 Total UI for P1: 0, mck2ui 16
7661 13:30:49.079990 best dqsien dly found for B1: ( 1, 9, 20)
7662 13:30:49.083597 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7663 13:30:49.086674 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7664 13:30:49.086759
7665 13:30:49.089887 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7666 13:30:49.093370 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7667 13:30:49.096708 [Gating] SW calibration Done
7668 13:30:49.096792 ==
7669 13:30:49.099799 Dram Type= 6, Freq= 0, CH_0, rank 0
7670 13:30:49.103395 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7671 13:30:49.103479 ==
7672 13:30:49.106431 RX Vref Scan: 0
7673 13:30:49.106514
7674 13:30:49.106580 RX Vref 0 -> 0, step: 1
7675 13:30:49.106641
7676 13:30:49.110125 RX Delay 0 -> 252, step: 8
7677 13:30:49.113165 iDelay=192, Bit 0, Center 135 (80 ~ 191) 112
7678 13:30:49.119883 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7679 13:30:49.123331 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7680 13:30:49.126098 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7681 13:30:49.129705 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7682 13:30:49.132798 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7683 13:30:49.139735 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7684 13:30:49.142959 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7685 13:30:49.146204 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7686 13:30:49.149385 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7687 13:30:49.152838 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7688 13:30:49.158973 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7689 13:30:49.162724 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
7690 13:30:49.165687 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7691 13:30:49.169087 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7692 13:30:49.175809 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7693 13:30:49.175939 ==
7694 13:30:49.178966 Dram Type= 6, Freq= 0, CH_0, rank 0
7695 13:30:49.181880 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7696 13:30:49.181958 ==
7697 13:30:49.182039 DQS Delay:
7698 13:30:49.185679 DQS0 = 0, DQS1 = 0
7699 13:30:49.185760 DQM Delay:
7700 13:30:49.188826 DQM0 = 131, DQM1 = 125
7701 13:30:49.188896 DQ Delay:
7702 13:30:49.191858 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
7703 13:30:49.195444 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7704 13:30:49.198473 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =119
7705 13:30:49.204915 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7706 13:30:49.204992
7707 13:30:49.205069
7708 13:30:49.205129 ==
7709 13:30:49.208558 Dram Type= 6, Freq= 0, CH_0, rank 0
7710 13:30:49.211617 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7711 13:30:49.211720 ==
7712 13:30:49.211822
7713 13:30:49.211921
7714 13:30:49.214817 TX Vref Scan disable
7715 13:30:49.214917 == TX Byte 0 ==
7716 13:30:49.221391 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7717 13:30:49.225117 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7718 13:30:49.225196 == TX Byte 1 ==
7719 13:30:49.231675 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7720 13:30:49.234424 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7721 13:30:49.234507 ==
7722 13:30:49.238100 Dram Type= 6, Freq= 0, CH_0, rank 0
7723 13:30:49.241120 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7724 13:30:49.241203 ==
7725 13:30:49.257258
7726 13:30:49.260214 TX Vref early break, caculate TX vref
7727 13:30:49.263875 TX Vref=16, minBit 1, minWin=20, winSum=360
7728 13:30:49.266716 TX Vref=18, minBit 1, minWin=21, winSum=371
7729 13:30:49.270251 TX Vref=20, minBit 1, minWin=22, winSum=377
7730 13:30:49.273769 TX Vref=22, minBit 6, minWin=23, winSum=392
7731 13:30:49.276792 TX Vref=24, minBit 3, minWin=23, winSum=403
7732 13:30:49.283808 TX Vref=26, minBit 1, minWin=23, winSum=408
7733 13:30:49.286982 TX Vref=28, minBit 1, minWin=24, winSum=411
7734 13:30:49.290120 TX Vref=30, minBit 7, minWin=23, winSum=411
7735 13:30:49.293221 TX Vref=32, minBit 4, minWin=23, winSum=401
7736 13:30:49.296824 TX Vref=34, minBit 0, minWin=22, winSum=390
7737 13:30:49.303585 TX Vref=36, minBit 7, minWin=22, winSum=383
7738 13:30:49.306490 [TxChooseVref] Worse bit 1, Min win 24, Win sum 411, Final Vref 28
7739 13:30:49.306606
7740 13:30:49.310025 Final TX Range 0 Vref 28
7741 13:30:49.310140
7742 13:30:49.310244 ==
7743 13:30:49.312998 Dram Type= 6, Freq= 0, CH_0, rank 0
7744 13:30:49.316182 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7745 13:30:49.319862 ==
7746 13:30:49.319970
7747 13:30:49.320037
7748 13:30:49.320097 TX Vref Scan disable
7749 13:30:49.326608 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7750 13:30:49.326721 == TX Byte 0 ==
7751 13:30:49.329747 u2DelayCellOfst[0]=14 cells (4 PI)
7752 13:30:49.333388 u2DelayCellOfst[1]=18 cells (5 PI)
7753 13:30:49.336431 u2DelayCellOfst[2]=14 cells (4 PI)
7754 13:30:49.339356 u2DelayCellOfst[3]=14 cells (4 PI)
7755 13:30:49.342694 u2DelayCellOfst[4]=10 cells (3 PI)
7756 13:30:49.346144 u2DelayCellOfst[5]=0 cells (0 PI)
7757 13:30:49.349239 u2DelayCellOfst[6]=21 cells (6 PI)
7758 13:30:49.352402 u2DelayCellOfst[7]=18 cells (5 PI)
7759 13:30:49.355932 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7760 13:30:49.362339 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7761 13:30:49.362420 == TX Byte 1 ==
7762 13:30:49.365847 u2DelayCellOfst[8]=0 cells (0 PI)
7763 13:30:49.368776 u2DelayCellOfst[9]=0 cells (0 PI)
7764 13:30:49.372362 u2DelayCellOfst[10]=7 cells (2 PI)
7765 13:30:49.375620 u2DelayCellOfst[11]=0 cells (0 PI)
7766 13:30:49.378935 u2DelayCellOfst[12]=10 cells (3 PI)
7767 13:30:49.382542 u2DelayCellOfst[13]=10 cells (3 PI)
7768 13:30:49.385353 u2DelayCellOfst[14]=14 cells (4 PI)
7769 13:30:49.388923 u2DelayCellOfst[15]=10 cells (3 PI)
7770 13:30:49.391996 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7771 13:30:49.395635 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7772 13:30:49.398853 DramC Write-DBI on
7773 13:30:49.398929 ==
7774 13:30:49.401821 Dram Type= 6, Freq= 0, CH_0, rank 0
7775 13:30:49.405373 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7776 13:30:49.405451 ==
7777 13:30:49.405557
7778 13:30:49.405647
7779 13:30:49.408419 TX Vref Scan disable
7780 13:30:49.411361 == TX Byte 0 ==
7781 13:30:49.415078 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7782 13:30:49.415197 == TX Byte 1 ==
7783 13:30:49.421800 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7784 13:30:49.421881 DramC Write-DBI off
7785 13:30:49.421946
7786 13:30:49.424964 [DATLAT]
7787 13:30:49.425040 Freq=1600, CH0 RK0
7788 13:30:49.425121
7789 13:30:49.428088 DATLAT Default: 0xf
7790 13:30:49.428168 0, 0xFFFF, sum = 0
7791 13:30:49.431270 1, 0xFFFF, sum = 0
7792 13:30:49.431351 2, 0xFFFF, sum = 0
7793 13:30:49.434880 3, 0xFFFF, sum = 0
7794 13:30:49.434957 4, 0xFFFF, sum = 0
7795 13:30:49.438091 5, 0xFFFF, sum = 0
7796 13:30:49.438166 6, 0xFFFF, sum = 0
7797 13:30:49.441235 7, 0xFFFF, sum = 0
7798 13:30:49.441310 8, 0xFFFF, sum = 0
7799 13:30:49.444822 9, 0xFFFF, sum = 0
7800 13:30:49.444897 10, 0xFFFF, sum = 0
7801 13:30:49.447667 11, 0xFFFF, sum = 0
7802 13:30:49.451016 12, 0xFFFF, sum = 0
7803 13:30:49.451158 13, 0xFFFF, sum = 0
7804 13:30:49.454697 14, 0x0, sum = 1
7805 13:30:49.454819 15, 0x0, sum = 2
7806 13:30:49.457731 16, 0x0, sum = 3
7807 13:30:49.457812 17, 0x0, sum = 4
7808 13:30:49.457917 best_step = 15
7809 13:30:49.461131
7810 13:30:49.461222 ==
7811 13:30:49.464094 Dram Type= 6, Freq= 0, CH_0, rank 0
7812 13:30:49.467753 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7813 13:30:49.467864 ==
7814 13:30:49.467965 RX Vref Scan: 1
7815 13:30:49.468027
7816 13:30:49.470661 Set Vref Range= 24 -> 127
7817 13:30:49.470800
7818 13:30:49.474300 RX Vref 24 -> 127, step: 1
7819 13:30:49.474395
7820 13:30:49.477461 RX Delay 11 -> 252, step: 4
7821 13:30:49.477573
7822 13:30:49.480417 Set Vref, RX VrefLevel [Byte0]: 24
7823 13:30:49.484082 [Byte1]: 24
7824 13:30:49.484164
7825 13:30:49.487393 Set Vref, RX VrefLevel [Byte0]: 25
7826 13:30:49.490786 [Byte1]: 25
7827 13:30:49.490869
7828 13:30:49.493539 Set Vref, RX VrefLevel [Byte0]: 26
7829 13:30:49.497058 [Byte1]: 26
7830 13:30:49.501178
7831 13:30:49.501263 Set Vref, RX VrefLevel [Byte0]: 27
7832 13:30:49.504266 [Byte1]: 27
7833 13:30:49.508523
7834 13:30:49.508618 Set Vref, RX VrefLevel [Byte0]: 28
7835 13:30:49.512080 [Byte1]: 28
7836 13:30:49.516268
7837 13:30:49.516348 Set Vref, RX VrefLevel [Byte0]: 29
7838 13:30:49.519811 [Byte1]: 29
7839 13:30:49.524099
7840 13:30:49.524208 Set Vref, RX VrefLevel [Byte0]: 30
7841 13:30:49.527296 [Byte1]: 30
7842 13:30:49.531532
7843 13:30:49.531614 Set Vref, RX VrefLevel [Byte0]: 31
7844 13:30:49.534610 [Byte1]: 31
7845 13:30:49.538958
7846 13:30:49.539038 Set Vref, RX VrefLevel [Byte0]: 32
7847 13:30:49.542584 [Byte1]: 32
7848 13:30:49.546868
7849 13:30:49.546963 Set Vref, RX VrefLevel [Byte0]: 33
7850 13:30:49.550000 [Byte1]: 33
7851 13:30:49.554210
7852 13:30:49.554293 Set Vref, RX VrefLevel [Byte0]: 34
7853 13:30:49.557625 [Byte1]: 34
7854 13:30:49.561726
7855 13:30:49.561810 Set Vref, RX VrefLevel [Byte0]: 35
7856 13:30:49.565143 [Byte1]: 35
7857 13:30:49.569415
7858 13:30:49.569496 Set Vref, RX VrefLevel [Byte0]: 36
7859 13:30:49.572894 [Byte1]: 36
7860 13:30:49.576936
7861 13:30:49.577044 Set Vref, RX VrefLevel [Byte0]: 37
7862 13:30:49.580303 [Byte1]: 37
7863 13:30:49.584577
7864 13:30:49.584659 Set Vref, RX VrefLevel [Byte0]: 38
7865 13:30:49.588362 [Byte1]: 38
7866 13:30:49.592498
7867 13:30:49.592581 Set Vref, RX VrefLevel [Byte0]: 39
7868 13:30:49.595540 [Byte1]: 39
7869 13:30:49.600009
7870 13:30:49.600091 Set Vref, RX VrefLevel [Byte0]: 40
7871 13:30:49.603391 [Byte1]: 40
7872 13:30:49.607656
7873 13:30:49.607742 Set Vref, RX VrefLevel [Byte0]: 41
7874 13:30:49.611066 [Byte1]: 41
7875 13:30:49.615323
7876 13:30:49.615415 Set Vref, RX VrefLevel [Byte0]: 42
7877 13:30:49.618466 [Byte1]: 42
7878 13:30:49.622728
7879 13:30:49.622809 Set Vref, RX VrefLevel [Byte0]: 43
7880 13:30:49.626169 [Byte1]: 43
7881 13:30:49.630533
7882 13:30:49.630630 Set Vref, RX VrefLevel [Byte0]: 44
7883 13:30:49.633588 [Byte1]: 44
7884 13:30:49.637925
7885 13:30:49.638007 Set Vref, RX VrefLevel [Byte0]: 45
7886 13:30:49.641721 [Byte1]: 45
7887 13:30:49.645966
7888 13:30:49.646087 Set Vref, RX VrefLevel [Byte0]: 46
7889 13:30:49.649087 [Byte1]: 46
7890 13:30:49.653353
7891 13:30:49.653430 Set Vref, RX VrefLevel [Byte0]: 47
7892 13:30:49.656289 [Byte1]: 47
7893 13:30:49.660714
7894 13:30:49.660794 Set Vref, RX VrefLevel [Byte0]: 48
7895 13:30:49.664439 [Byte1]: 48
7896 13:30:49.668752
7897 13:30:49.668835 Set Vref, RX VrefLevel [Byte0]: 49
7898 13:30:49.671891 [Byte1]: 49
7899 13:30:49.676147
7900 13:30:49.676229 Set Vref, RX VrefLevel [Byte0]: 50
7901 13:30:49.679642 [Byte1]: 50
7902 13:30:49.683720
7903 13:30:49.683828 Set Vref, RX VrefLevel [Byte0]: 51
7904 13:30:49.687165 [Byte1]: 51
7905 13:30:49.691345
7906 13:30:49.691456 Set Vref, RX VrefLevel [Byte0]: 52
7907 13:30:49.694515 [Byte1]: 52
7908 13:30:49.698819
7909 13:30:49.698913 Set Vref, RX VrefLevel [Byte0]: 53
7910 13:30:49.702526 [Byte1]: 53
7911 13:30:49.706654
7912 13:30:49.706736 Set Vref, RX VrefLevel [Byte0]: 54
7913 13:30:49.710082 [Byte1]: 54
7914 13:30:49.714097
7915 13:30:49.714179 Set Vref, RX VrefLevel [Byte0]: 55
7916 13:30:49.717505 [Byte1]: 55
7917 13:30:49.721963
7918 13:30:49.722044 Set Vref, RX VrefLevel [Byte0]: 56
7919 13:30:49.725410 [Byte1]: 56
7920 13:30:49.729433
7921 13:30:49.729515 Set Vref, RX VrefLevel [Byte0]: 57
7922 13:30:49.732927 [Byte1]: 57
7923 13:30:49.737147
7924 13:30:49.737262 Set Vref, RX VrefLevel [Byte0]: 58
7925 13:30:49.743597 [Byte1]: 58
7926 13:30:49.743680
7927 13:30:49.746567 Set Vref, RX VrefLevel [Byte0]: 59
7928 13:30:49.750261 [Byte1]: 59
7929 13:30:49.750343
7930 13:30:49.753420 Set Vref, RX VrefLevel [Byte0]: 60
7931 13:30:49.756549 [Byte1]: 60
7932 13:30:49.760134
7933 13:30:49.760216 Set Vref, RX VrefLevel [Byte0]: 61
7934 13:30:49.763237 [Byte1]: 61
7935 13:30:49.767484
7936 13:30:49.767564 Set Vref, RX VrefLevel [Byte0]: 62
7937 13:30:49.771150 [Byte1]: 62
7938 13:30:49.775247
7939 13:30:49.775328 Set Vref, RX VrefLevel [Byte0]: 63
7940 13:30:49.778556 [Byte1]: 63
7941 13:30:49.782849
7942 13:30:49.782927 Set Vref, RX VrefLevel [Byte0]: 64
7943 13:30:49.785843 [Byte1]: 64
7944 13:30:49.790613
7945 13:30:49.790694 Set Vref, RX VrefLevel [Byte0]: 65
7946 13:30:49.793578 [Byte1]: 65
7947 13:30:49.797928
7948 13:30:49.798010 Set Vref, RX VrefLevel [Byte0]: 66
7949 13:30:49.801447 [Byte1]: 66
7950 13:30:49.805860
7951 13:30:49.805934 Set Vref, RX VrefLevel [Byte0]: 67
7952 13:30:49.808951 [Byte1]: 67
7953 13:30:49.813143
7954 13:30:49.813228 Set Vref, RX VrefLevel [Byte0]: 68
7955 13:30:49.816545 [Byte1]: 68
7956 13:30:49.820982
7957 13:30:49.821066 Set Vref, RX VrefLevel [Byte0]: 69
7958 13:30:49.823866 [Byte1]: 69
7959 13:30:49.828535
7960 13:30:49.828653 Set Vref, RX VrefLevel [Byte0]: 70
7961 13:30:49.831491 [Byte1]: 70
7962 13:30:49.835833
7963 13:30:49.835951 Set Vref, RX VrefLevel [Byte0]: 71
7964 13:30:49.839465 [Byte1]: 71
7965 13:30:49.843810
7966 13:30:49.843923 Set Vref, RX VrefLevel [Byte0]: 72
7967 13:30:49.847104 [Byte1]: 72
7968 13:30:49.851339
7969 13:30:49.851418 Set Vref, RX VrefLevel [Byte0]: 73
7970 13:30:49.854423 [Byte1]: 73
7971 13:30:49.858775
7972 13:30:49.858854 Set Vref, RX VrefLevel [Byte0]: 74
7973 13:30:49.861805 [Byte1]: 74
7974 13:30:49.866751
7975 13:30:49.866860 Set Vref, RX VrefLevel [Byte0]: 75
7976 13:30:49.869913 [Byte1]: 75
7977 13:30:49.874165
7978 13:30:49.874245 Final RX Vref Byte 0 = 55 to rank0
7979 13:30:49.876999 Final RX Vref Byte 1 = 63 to rank0
7980 13:30:49.880845 Final RX Vref Byte 0 = 55 to rank1
7981 13:30:49.884172 Final RX Vref Byte 1 = 63 to rank1==
7982 13:30:49.887382 Dram Type= 6, Freq= 0, CH_0, rank 0
7983 13:30:49.893511 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7984 13:30:49.893593 ==
7985 13:30:49.893657 DQS Delay:
7986 13:30:49.897447 DQS0 = 0, DQS1 = 0
7987 13:30:49.897527 DQM Delay:
7988 13:30:49.900378 DQM0 = 128, DQM1 = 123
7989 13:30:49.900458 DQ Delay:
7990 13:30:49.903825 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7991 13:30:49.906972 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134
7992 13:30:49.909952 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =120
7993 13:30:49.913618 DQ12 =130, DQ13 =130, DQ14 =132, DQ15 =128
7994 13:30:49.913704
7995 13:30:49.913769
7996 13:30:49.913827
7997 13:30:49.916739 [DramC_TX_OE_Calibration] TA2
7998 13:30:49.919752 Original DQ_B0 (3 6) =30, OEN = 27
7999 13:30:49.923369 Original DQ_B1 (3 6) =30, OEN = 27
8000 13:30:49.926405 24, 0x0, End_B0=24 End_B1=24
8001 13:30:49.929785 25, 0x0, End_B0=25 End_B1=25
8002 13:30:49.929859 26, 0x0, End_B0=26 End_B1=26
8003 13:30:49.933209 27, 0x0, End_B0=27 End_B1=27
8004 13:30:49.936381 28, 0x0, End_B0=28 End_B1=28
8005 13:30:49.939777 29, 0x0, End_B0=29 End_B1=29
8006 13:30:49.942748 30, 0x0, End_B0=30 End_B1=30
8007 13:30:49.942826 31, 0x5151, End_B0=30 End_B1=30
8008 13:30:49.946065 Byte0 end_step=30 best_step=27
8009 13:30:49.949934 Byte1 end_step=30 best_step=27
8010 13:30:49.952865 Byte0 TX OE(2T, 0.5T) = (3, 3)
8011 13:30:49.955937 Byte1 TX OE(2T, 0.5T) = (3, 3)
8012 13:30:49.956014
8013 13:30:49.956077
8014 13:30:49.962642 [DQSOSCAuto] RK0, (LSB)MR18= 0x1411, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 399 ps
8015 13:30:49.965771 CH0 RK0: MR19=303, MR18=1411
8016 13:30:49.972564 CH0_RK0: MR19=0x303, MR18=0x1411, DQSOSC=399, MR23=63, INC=23, DEC=15
8017 13:30:49.972649
8018 13:30:49.975640 ----->DramcWriteLeveling(PI) begin...
8019 13:30:49.975714 ==
8020 13:30:49.979495 Dram Type= 6, Freq= 0, CH_0, rank 1
8021 13:30:49.982630 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8022 13:30:49.985759 ==
8023 13:30:49.985842 Write leveling (Byte 0): 34 => 34
8024 13:30:49.988841 Write leveling (Byte 1): 26 => 26
8025 13:30:49.992416 DramcWriteLeveling(PI) end<-----
8026 13:30:49.992502
8027 13:30:49.992572 ==
8028 13:30:49.995374 Dram Type= 6, Freq= 0, CH_0, rank 1
8029 13:30:50.002249 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8030 13:30:50.002332 ==
8031 13:30:50.005695 [Gating] SW mode calibration
8032 13:30:50.011801 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8033 13:30:50.015696 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8034 13:30:50.022221 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8035 13:30:50.025259 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 13:30:50.028345 1 4 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8037 13:30:50.034887 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8038 13:30:50.038408 1 4 16 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
8039 13:30:50.041791 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8040 13:30:50.048518 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8041 13:30:50.051418 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8042 13:30:50.055027 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8043 13:30:50.061796 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8044 13:30:50.064780 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
8045 13:30:50.068514 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
8046 13:30:50.074691 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8047 13:30:50.077778 1 5 20 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
8048 13:30:50.081444 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8049 13:30:50.087696 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8050 13:30:50.091350 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8051 13:30:50.094368 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8052 13:30:50.100990 1 6 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8053 13:30:50.104122 1 6 12 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
8054 13:30:50.107753 1 6 16 | B1->B0 | 3030 4646 | 1 0 | (0 0) (0 0)
8055 13:30:50.114181 1 6 20 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8056 13:30:50.117699 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8057 13:30:50.120683 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8058 13:30:50.127492 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8059 13:30:50.130603 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8060 13:30:50.133587 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8061 13:30:50.140520 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8062 13:30:50.143851 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8063 13:30:50.147269 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8064 13:30:50.153396 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 13:30:50.157087 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 13:30:50.160132 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 13:30:50.166570 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 13:30:50.170023 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 13:30:50.173140 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 13:30:50.179814 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 13:30:50.182899 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 13:30:50.186661 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 13:30:50.192805 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 13:30:50.196492 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 13:30:50.199451 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 13:30:50.206271 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8077 13:30:50.209216 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8078 13:30:50.212839 Total UI for P1: 0, mck2ui 16
8079 13:30:50.215884 best dqsien dly found for B0: ( 1, 9, 8)
8080 13:30:50.219082 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8081 13:30:50.225637 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8082 13:30:50.229179 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8083 13:30:50.232333 Total UI for P1: 0, mck2ui 16
8084 13:30:50.235803 best dqsien dly found for B1: ( 1, 9, 18)
8085 13:30:50.239100 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8086 13:30:50.242258 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8087 13:30:50.242340
8088 13:30:50.245597 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8089 13:30:50.252010 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8090 13:30:50.252125 [Gating] SW calibration Done
8091 13:30:50.252219 ==
8092 13:30:50.255510 Dram Type= 6, Freq= 0, CH_0, rank 1
8093 13:30:50.261920 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8094 13:30:50.262002 ==
8095 13:30:50.262065 RX Vref Scan: 0
8096 13:30:50.262128
8097 13:30:50.264908 RX Vref 0 -> 0, step: 1
8098 13:30:50.264988
8099 13:30:50.268589 RX Delay 0 -> 252, step: 8
8100 13:30:50.271474 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8101 13:30:50.275062 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8102 13:30:50.278076 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8103 13:30:50.284964 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8104 13:30:50.288069 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8105 13:30:50.291765 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8106 13:30:50.294872 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8107 13:30:50.297940 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8108 13:30:50.304824 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8109 13:30:50.307744 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8110 13:30:50.310875 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8111 13:30:50.314460 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8112 13:30:50.317387 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8113 13:30:50.324084 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8114 13:30:50.327665 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8115 13:30:50.331098 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8116 13:30:50.331179 ==
8117 13:30:50.334040 Dram Type= 6, Freq= 0, CH_0, rank 1
8118 13:30:50.337778 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8119 13:30:50.340817 ==
8120 13:30:50.340913 DQS Delay:
8121 13:30:50.340992 DQS0 = 0, DQS1 = 0
8122 13:30:50.343853 DQM Delay:
8123 13:30:50.343972 DQM0 = 132, DQM1 = 127
8124 13:30:50.347327 DQ Delay:
8125 13:30:50.350781 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8126 13:30:50.354193 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =143
8127 13:30:50.357841 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =119
8128 13:30:50.360533 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
8129 13:30:50.360635
8130 13:30:50.360702
8131 13:30:50.360775 ==
8132 13:30:50.364049 Dram Type= 6, Freq= 0, CH_0, rank 1
8133 13:30:50.367293 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8134 13:30:50.370634 ==
8135 13:30:50.370751
8136 13:30:50.370844
8137 13:30:50.370908 TX Vref Scan disable
8138 13:30:50.373820 == TX Byte 0 ==
8139 13:30:50.377320 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8140 13:30:50.380266 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8141 13:30:50.383753 == TX Byte 1 ==
8142 13:30:50.387476 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8143 13:30:50.390559 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8144 13:30:50.393731 ==
8145 13:30:50.396761 Dram Type= 6, Freq= 0, CH_0, rank 1
8146 13:30:50.400412 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8147 13:30:50.400493 ==
8148 13:30:50.414568
8149 13:30:50.417654 TX Vref early break, caculate TX vref
8150 13:30:50.421273 TX Vref=16, minBit 1, minWin=22, winSum=374
8151 13:30:50.424444 TX Vref=18, minBit 3, minWin=22, winSum=378
8152 13:30:50.427590 TX Vref=20, minBit 9, minWin=23, winSum=392
8153 13:30:50.430603 TX Vref=22, minBit 1, minWin=24, winSum=398
8154 13:30:50.434156 TX Vref=24, minBit 3, minWin=24, winSum=405
8155 13:30:50.441060 TX Vref=26, minBit 0, minWin=25, winSum=412
8156 13:30:50.444125 TX Vref=28, minBit 0, minWin=25, winSum=411
8157 13:30:50.447074 TX Vref=30, minBit 0, minWin=24, winSum=404
8158 13:30:50.450696 TX Vref=32, minBit 1, minWin=24, winSum=402
8159 13:30:50.453681 TX Vref=34, minBit 1, minWin=23, winSum=392
8160 13:30:50.460764 TX Vref=36, minBit 0, minWin=22, winSum=385
8161 13:30:50.463892 [TxChooseVref] Worse bit 0, Min win 25, Win sum 412, Final Vref 26
8162 13:30:50.463982
8163 13:30:50.467028 Final TX Range 0 Vref 26
8164 13:30:50.467125
8165 13:30:50.467190 ==
8166 13:30:50.470082 Dram Type= 6, Freq= 0, CH_0, rank 1
8167 13:30:50.473475 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8168 13:30:50.476890 ==
8169 13:30:50.476972
8170 13:30:50.477037
8171 13:30:50.477097 TX Vref Scan disable
8172 13:30:50.483627 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8173 13:30:50.483710 == TX Byte 0 ==
8174 13:30:50.487263 u2DelayCellOfst[0]=10 cells (3 PI)
8175 13:30:50.490184 u2DelayCellOfst[1]=14 cells (4 PI)
8176 13:30:50.493624 u2DelayCellOfst[2]=10 cells (3 PI)
8177 13:30:50.496812 u2DelayCellOfst[3]=10 cells (3 PI)
8178 13:30:50.499822 u2DelayCellOfst[4]=7 cells (2 PI)
8179 13:30:50.503567 u2DelayCellOfst[5]=0 cells (0 PI)
8180 13:30:50.506759 u2DelayCellOfst[6]=18 cells (5 PI)
8181 13:30:50.509787 u2DelayCellOfst[7]=18 cells (5 PI)
8182 13:30:50.513315 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8183 13:30:50.516261 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8184 13:30:50.519911 == TX Byte 1 ==
8185 13:30:50.523031 u2DelayCellOfst[8]=0 cells (0 PI)
8186 13:30:50.526033 u2DelayCellOfst[9]=0 cells (0 PI)
8187 13:30:50.529664 u2DelayCellOfst[10]=3 cells (1 PI)
8188 13:30:50.532857 u2DelayCellOfst[11]=0 cells (0 PI)
8189 13:30:50.535923 u2DelayCellOfst[12]=10 cells (3 PI)
8190 13:30:50.539490 u2DelayCellOfst[13]=10 cells (3 PI)
8191 13:30:50.542866 u2DelayCellOfst[14]=14 cells (4 PI)
8192 13:30:50.545821 u2DelayCellOfst[15]=10 cells (3 PI)
8193 13:30:50.549423 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8194 13:30:50.552448 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8195 13:30:50.556127 DramC Write-DBI on
8196 13:30:50.556210 ==
8197 13:30:50.559193 Dram Type= 6, Freq= 0, CH_0, rank 1
8198 13:30:50.562901 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8199 13:30:50.562984 ==
8200 13:30:50.563049
8201 13:30:50.563123
8202 13:30:50.565719 TX Vref Scan disable
8203 13:30:50.569123 == TX Byte 0 ==
8204 13:30:50.572342 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8205 13:30:50.572451 == TX Byte 1 ==
8206 13:30:50.578920 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8207 13:30:50.579003 DramC Write-DBI off
8208 13:30:50.579067
8209 13:30:50.579127 [DATLAT]
8210 13:30:50.582561 Freq=1600, CH0 RK1
8211 13:30:50.582646
8212 13:30:50.585343 DATLAT Default: 0xf
8213 13:30:50.585416 0, 0xFFFF, sum = 0
8214 13:30:50.588679 1, 0xFFFF, sum = 0
8215 13:30:50.588751 2, 0xFFFF, sum = 0
8216 13:30:50.591771 3, 0xFFFF, sum = 0
8217 13:30:50.591845 4, 0xFFFF, sum = 0
8218 13:30:50.595198 5, 0xFFFF, sum = 0
8219 13:30:50.595274 6, 0xFFFF, sum = 0
8220 13:30:50.598705 7, 0xFFFF, sum = 0
8221 13:30:50.598781 8, 0xFFFF, sum = 0
8222 13:30:50.602175 9, 0xFFFF, sum = 0
8223 13:30:50.602262 10, 0xFFFF, sum = 0
8224 13:30:50.605250 11, 0xFFFF, sum = 0
8225 13:30:50.605357 12, 0xFFFF, sum = 0
8226 13:30:50.608390 13, 0xFFFF, sum = 0
8227 13:30:50.612113 14, 0x0, sum = 1
8228 13:30:50.612191 15, 0x0, sum = 2
8229 13:30:50.612267 16, 0x0, sum = 3
8230 13:30:50.615103 17, 0x0, sum = 4
8231 13:30:50.615186 best_step = 15
8232 13:30:50.615250
8233 13:30:50.618608 ==
8234 13:30:50.618694 Dram Type= 6, Freq= 0, CH_0, rank 1
8235 13:30:50.625266 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8236 13:30:50.625348 ==
8237 13:30:50.625418 RX Vref Scan: 0
8238 13:30:50.625481
8239 13:30:50.628328 RX Vref 0 -> 0, step: 1
8240 13:30:50.628402
8241 13:30:50.631350 RX Delay 19 -> 252, step: 4
8242 13:30:50.634991 iDelay=187, Bit 0, Center 126 (75 ~ 178) 104
8243 13:30:50.638110 iDelay=187, Bit 1, Center 132 (79 ~ 186) 108
8244 13:30:50.644335 iDelay=187, Bit 2, Center 124 (71 ~ 178) 108
8245 13:30:50.647877 iDelay=187, Bit 3, Center 126 (75 ~ 178) 104
8246 13:30:50.651146 iDelay=187, Bit 4, Center 132 (83 ~ 182) 100
8247 13:30:50.654682 iDelay=187, Bit 5, Center 118 (63 ~ 174) 112
8248 13:30:50.657630 iDelay=187, Bit 6, Center 136 (87 ~ 186) 100
8249 13:30:50.664272 iDelay=187, Bit 7, Center 134 (83 ~ 186) 104
8250 13:30:50.667923 iDelay=187, Bit 8, Center 114 (63 ~ 166) 104
8251 13:30:50.671073 iDelay=187, Bit 9, Center 110 (59 ~ 162) 104
8252 13:30:50.674669 iDelay=187, Bit 10, Center 128 (75 ~ 182) 108
8253 13:30:50.677706 iDelay=187, Bit 11, Center 120 (67 ~ 174) 108
8254 13:30:50.684447 iDelay=187, Bit 12, Center 126 (75 ~ 178) 104
8255 13:30:50.687611 iDelay=187, Bit 13, Center 130 (79 ~ 182) 104
8256 13:30:50.690721 iDelay=187, Bit 14, Center 134 (83 ~ 186) 104
8257 13:30:50.694202 iDelay=187, Bit 15, Center 128 (75 ~ 182) 108
8258 13:30:50.697560 ==
8259 13:30:50.697647 Dram Type= 6, Freq= 0, CH_0, rank 1
8260 13:30:50.703725 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8261 13:30:50.703831 ==
8262 13:30:50.703951 DQS Delay:
8263 13:30:50.707011 DQS0 = 0, DQS1 = 0
8264 13:30:50.707151 DQM Delay:
8265 13:30:50.710646 DQM0 = 128, DQM1 = 123
8266 13:30:50.710755 DQ Delay:
8267 13:30:50.714065 DQ0 =126, DQ1 =132, DQ2 =124, DQ3 =126
8268 13:30:50.717337 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134
8269 13:30:50.720279 DQ8 =114, DQ9 =110, DQ10 =128, DQ11 =120
8270 13:30:50.723827 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =128
8271 13:30:50.723958
8272 13:30:50.724053
8273 13:30:50.724154
8274 13:30:50.726893 [DramC_TX_OE_Calibration] TA2
8275 13:30:50.729991 Original DQ_B0 (3 6) =30, OEN = 27
8276 13:30:50.733733 Original DQ_B1 (3 6) =30, OEN = 27
8277 13:30:50.736898 24, 0x0, End_B0=24 End_B1=24
8278 13:30:50.740021 25, 0x0, End_B0=25 End_B1=25
8279 13:30:50.743696 26, 0x0, End_B0=26 End_B1=26
8280 13:30:50.743805 27, 0x0, End_B0=27 End_B1=27
8281 13:30:50.746584 28, 0x0, End_B0=28 End_B1=28
8282 13:30:50.749597 29, 0x0, End_B0=29 End_B1=29
8283 13:30:50.753370 30, 0x0, End_B0=30 End_B1=30
8284 13:30:50.756703 31, 0x4141, End_B0=30 End_B1=30
8285 13:30:50.756787 Byte0 end_step=30 best_step=27
8286 13:30:50.759623 Byte1 end_step=30 best_step=27
8287 13:30:50.763240 Byte0 TX OE(2T, 0.5T) = (3, 3)
8288 13:30:50.766309 Byte1 TX OE(2T, 0.5T) = (3, 3)
8289 13:30:50.766394
8290 13:30:50.766460
8291 13:30:50.776167 [DQSOSCAuto] RK1, (LSB)MR18= 0x1513, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
8292 13:30:50.776249 CH0 RK1: MR19=303, MR18=1513
8293 13:30:50.782890 CH0_RK1: MR19=0x303, MR18=0x1513, DQSOSC=399, MR23=63, INC=23, DEC=15
8294 13:30:50.785871 [RxdqsGatingPostProcess] freq 1600
8295 13:30:50.792708 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8296 13:30:50.796080 best DQS0 dly(2T, 0.5T) = (1, 1)
8297 13:30:50.799561 best DQS1 dly(2T, 0.5T) = (1, 1)
8298 13:30:50.802399 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8299 13:30:50.802475 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8300 13:30:50.805931 best DQS0 dly(2T, 0.5T) = (1, 1)
8301 13:30:50.808936 best DQS1 dly(2T, 0.5T) = (1, 1)
8302 13:30:50.812389 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8303 13:30:50.815915 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8304 13:30:50.818832 Pre-setting of DQS Precalculation
8305 13:30:50.825265 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8306 13:30:50.825360 ==
8307 13:30:50.828930 Dram Type= 6, Freq= 0, CH_1, rank 0
8308 13:30:50.831851 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8309 13:30:50.831965 ==
8310 13:30:50.838666 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8311 13:30:50.841833 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8312 13:30:50.845430 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8313 13:30:50.851756 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8314 13:30:50.860696 [CA 0] Center 42 (12~72) winsize 61
8315 13:30:50.864189 [CA 1] Center 43 (13~73) winsize 61
8316 13:30:50.867542 [CA 2] Center 38 (9~68) winsize 60
8317 13:30:50.870979 [CA 3] Center 37 (8~67) winsize 60
8318 13:30:50.874244 [CA 4] Center 38 (8~68) winsize 61
8319 13:30:50.877092 [CA 5] Center 37 (7~67) winsize 61
8320 13:30:50.877197
8321 13:30:50.880817 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8322 13:30:50.880900
8323 13:30:50.883892 [CATrainingPosCal] consider 1 rank data
8324 13:30:50.887609 u2DelayCellTimex100 = 271/100 ps
8325 13:30:50.893918 CA0 delay=42 (12~72),Diff = 5 PI (18 cell)
8326 13:30:50.897452 CA1 delay=43 (13~73),Diff = 6 PI (21 cell)
8327 13:30:50.900195 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8328 13:30:50.903620 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8329 13:30:50.906797 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8330 13:30:50.910251 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8331 13:30:50.910337
8332 13:30:50.913565 CA PerBit enable=1, Macro0, CA PI delay=37
8333 13:30:50.913675
8334 13:30:50.917095 [CBTSetCACLKResult] CA Dly = 37
8335 13:30:50.920461 CS Dly: 8 (0~39)
8336 13:30:50.923395 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8337 13:30:50.926840 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8338 13:30:50.926945 ==
8339 13:30:50.930180 Dram Type= 6, Freq= 0, CH_1, rank 1
8340 13:30:50.936900 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8341 13:30:50.937019 ==
8342 13:30:50.939844 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8343 13:30:50.946747 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8344 13:30:50.949920 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8345 13:30:50.956573 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8346 13:30:50.963974 [CA 0] Center 42 (12~72) winsize 61
8347 13:30:50.967011 [CA 1] Center 43 (14~72) winsize 59
8348 13:30:50.970503 [CA 2] Center 38 (8~68) winsize 61
8349 13:30:50.973847 [CA 3] Center 37 (7~67) winsize 61
8350 13:30:50.977244 [CA 4] Center 37 (8~67) winsize 60
8351 13:30:50.980459 [CA 5] Center 37 (7~67) winsize 61
8352 13:30:50.980546
8353 13:30:50.983493 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8354 13:30:50.983593
8355 13:30:50.990358 [CATrainingPosCal] consider 2 rank data
8356 13:30:50.990441 u2DelayCellTimex100 = 271/100 ps
8357 13:30:50.996666 CA0 delay=42 (12~72),Diff = 5 PI (18 cell)
8358 13:30:51.000406 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8359 13:30:51.003127 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8360 13:30:51.006659 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8361 13:30:51.009867 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8362 13:30:51.013348 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8363 13:30:51.013430
8364 13:30:51.016775 CA PerBit enable=1, Macro0, CA PI delay=37
8365 13:30:51.016858
8366 13:30:51.020226 [CBTSetCACLKResult] CA Dly = 37
8367 13:30:51.023249 CS Dly: 9 (0~42)
8368 13:30:51.026618 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8369 13:30:51.029484 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8370 13:30:51.029566
8371 13:30:51.032747 ----->DramcWriteLeveling(PI) begin...
8372 13:30:51.032830 ==
8373 13:30:51.036088 Dram Type= 6, Freq= 0, CH_1, rank 0
8374 13:30:51.043180 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8375 13:30:51.043264 ==
8376 13:30:51.046304 Write leveling (Byte 0): 27 => 27
8377 13:30:51.049614 Write leveling (Byte 1): 27 => 27
8378 13:30:51.049696 DramcWriteLeveling(PI) end<-----
8379 13:30:51.053110
8380 13:30:51.053192 ==
8381 13:30:51.056233 Dram Type= 6, Freq= 0, CH_1, rank 0
8382 13:30:51.059419 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8383 13:30:51.059502 ==
8384 13:30:51.063065 [Gating] SW mode calibration
8385 13:30:51.069253 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8386 13:30:51.076239 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8387 13:30:51.078877 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 13:30:51.082462 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 13:30:51.088831 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 13:30:51.092110 1 4 12 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
8391 13:30:51.095687 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8392 13:30:51.101854 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8393 13:30:51.105043 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8394 13:30:51.108537 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8395 13:30:51.115151 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8396 13:30:51.118273 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8397 13:30:51.121917 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8398 13:30:51.128412 1 5 12 | B1->B0 | 3232 2424 | 1 0 | (1 0) (0 1)
8399 13:30:51.131255 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8400 13:30:51.134592 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8401 13:30:51.141484 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8402 13:30:51.144784 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8403 13:30:51.147951 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8404 13:30:51.154933 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 13:30:51.157710 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8406 13:30:51.160886 1 6 12 | B1->B0 | 3333 4545 | 0 0 | (0 0) (0 0)
8407 13:30:51.167538 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8408 13:30:51.170610 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8409 13:30:51.174338 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 13:30:51.180468 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 13:30:51.183965 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8412 13:30:51.187489 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8413 13:30:51.193967 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8414 13:30:51.197059 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8415 13:30:51.200775 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8416 13:30:51.206876 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 13:30:51.210532 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 13:30:51.213299 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 13:30:51.219947 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 13:30:51.223607 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 13:30:51.226705 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 13:30:51.233545 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 13:30:51.236553 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 13:30:51.239969 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 13:30:51.246836 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 13:30:51.249862 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 13:30:51.253416 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 13:30:51.259533 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 13:30:51.263064 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 13:30:51.266526 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8431 13:30:51.273098 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8432 13:30:51.276554 Total UI for P1: 0, mck2ui 16
8433 13:30:51.279717 best dqsien dly found for B0: ( 1, 9, 12)
8434 13:30:51.282761 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8435 13:30:51.286398 Total UI for P1: 0, mck2ui 16
8436 13:30:51.289505 best dqsien dly found for B1: ( 1, 9, 14)
8437 13:30:51.292440 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8438 13:30:51.295767 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8439 13:30:51.295876
8440 13:30:51.299432 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8441 13:30:51.305696 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8442 13:30:51.305778 [Gating] SW calibration Done
8443 13:30:51.305843 ==
8444 13:30:51.309323 Dram Type= 6, Freq= 0, CH_1, rank 0
8445 13:30:51.315501 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8446 13:30:51.315609 ==
8447 13:30:51.315702 RX Vref Scan: 0
8448 13:30:51.315789
8449 13:30:51.319003 RX Vref 0 -> 0, step: 1
8450 13:30:51.319084
8451 13:30:51.321922 RX Delay 0 -> 252, step: 8
8452 13:30:51.325582 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8453 13:30:51.328582 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8454 13:30:51.332199 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8455 13:30:51.338914 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8456 13:30:51.342067 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8457 13:30:51.345149 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8458 13:30:51.348686 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8459 13:30:51.352164 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8460 13:30:51.358604 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8461 13:30:51.361995 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8462 13:30:51.364923 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8463 13:30:51.368213 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8464 13:30:51.371594 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8465 13:30:51.378288 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8466 13:30:51.381727 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8467 13:30:51.385016 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8468 13:30:51.385156 ==
8469 13:30:51.388332 Dram Type= 6, Freq= 0, CH_1, rank 0
8470 13:30:51.391218 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8471 13:30:51.394897 ==
8472 13:30:51.395005 DQS Delay:
8473 13:30:51.395099 DQS0 = 0, DQS1 = 0
8474 13:30:51.397912 DQM Delay:
8475 13:30:51.397993 DQM0 = 135, DQM1 = 129
8476 13:30:51.401232 DQ Delay:
8477 13:30:51.404433 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8478 13:30:51.408106 DQ4 =127, DQ5 =147, DQ6 =147, DQ7 =131
8479 13:30:51.411153 DQ8 =111, DQ9 =119, DQ10 =127, DQ11 =127
8480 13:30:51.414310 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8481 13:30:51.414416
8482 13:30:51.414507
8483 13:30:51.414594 ==
8484 13:30:51.417400 Dram Type= 6, Freq= 0, CH_1, rank 0
8485 13:30:51.420930 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8486 13:30:51.424042 ==
8487 13:30:51.424124
8488 13:30:51.424186
8489 13:30:51.424245 TX Vref Scan disable
8490 13:30:51.427510 == TX Byte 0 ==
8491 13:30:51.430676 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8492 13:30:51.434423 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8493 13:30:51.437484 == TX Byte 1 ==
8494 13:30:51.440595 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8495 13:30:51.444379 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8496 13:30:51.447351 ==
8497 13:30:51.450494 Dram Type= 6, Freq= 0, CH_1, rank 0
8498 13:30:51.453995 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8499 13:30:51.454079 ==
8500 13:30:51.466638
8501 13:30:51.470182 TX Vref early break, caculate TX vref
8502 13:30:51.473675 TX Vref=16, minBit 8, minWin=21, winSum=365
8503 13:30:51.476531 TX Vref=18, minBit 8, minWin=21, winSum=374
8504 13:30:51.479841 TX Vref=20, minBit 8, minWin=22, winSum=388
8505 13:30:51.483285 TX Vref=22, minBit 8, minWin=23, winSum=395
8506 13:30:51.486375 TX Vref=24, minBit 8, minWin=23, winSum=403
8507 13:30:51.493165 TX Vref=26, minBit 8, minWin=24, winSum=411
8508 13:30:51.496504 TX Vref=28, minBit 0, minWin=25, winSum=414
8509 13:30:51.499917 TX Vref=30, minBit 9, minWin=24, winSum=413
8510 13:30:51.502706 TX Vref=32, minBit 9, minWin=24, winSum=406
8511 13:30:51.506111 TX Vref=34, minBit 0, minWin=24, winSum=394
8512 13:30:51.512565 TX Vref=36, minBit 9, minWin=22, winSum=384
8513 13:30:51.516167 [TxChooseVref] Worse bit 0, Min win 25, Win sum 414, Final Vref 28
8514 13:30:51.516252
8515 13:30:51.519333 Final TX Range 0 Vref 28
8516 13:30:51.519416
8517 13:30:51.519482 ==
8518 13:30:51.522885 Dram Type= 6, Freq= 0, CH_1, rank 0
8519 13:30:51.525761 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8520 13:30:51.529294 ==
8521 13:30:51.529377
8522 13:30:51.529441
8523 13:30:51.529502 TX Vref Scan disable
8524 13:30:51.536067 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8525 13:30:51.536157 == TX Byte 0 ==
8526 13:30:51.539119 u2DelayCellOfst[0]=18 cells (5 PI)
8527 13:30:51.542830 u2DelayCellOfst[1]=10 cells (3 PI)
8528 13:30:51.545959 u2DelayCellOfst[2]=0 cells (0 PI)
8529 13:30:51.548972 u2DelayCellOfst[3]=7 cells (2 PI)
8530 13:30:51.552633 u2DelayCellOfst[4]=10 cells (3 PI)
8531 13:30:51.555775 u2DelayCellOfst[5]=18 cells (5 PI)
8532 13:30:51.558905 u2DelayCellOfst[6]=14 cells (4 PI)
8533 13:30:51.562391 u2DelayCellOfst[7]=7 cells (2 PI)
8534 13:30:51.565203 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8535 13:30:51.568762 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8536 13:30:51.572163 == TX Byte 1 ==
8537 13:30:51.575601 u2DelayCellOfst[8]=0 cells (0 PI)
8538 13:30:51.578686 u2DelayCellOfst[9]=7 cells (2 PI)
8539 13:30:51.581695 u2DelayCellOfst[10]=14 cells (4 PI)
8540 13:30:51.585308 u2DelayCellOfst[11]=3 cells (1 PI)
8541 13:30:51.588610 u2DelayCellOfst[12]=14 cells (4 PI)
8542 13:30:51.591831 u2DelayCellOfst[13]=18 cells (5 PI)
8543 13:30:51.595230 u2DelayCellOfst[14]=18 cells (5 PI)
8544 13:30:51.598330 u2DelayCellOfst[15]=18 cells (5 PI)
8545 13:30:51.601869 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8546 13:30:51.605265 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8547 13:30:51.608167 DramC Write-DBI on
8548 13:30:51.608319 ==
8549 13:30:51.611498 Dram Type= 6, Freq= 0, CH_1, rank 0
8550 13:30:51.614805 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8551 13:30:51.614889 ==
8552 13:30:51.614979
8553 13:30:51.615052
8554 13:30:51.617950 TX Vref Scan disable
8555 13:30:51.621378 == TX Byte 0 ==
8556 13:30:51.624466 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8557 13:30:51.624573 == TX Byte 1 ==
8558 13:30:51.631133 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8559 13:30:51.631298 DramC Write-DBI off
8560 13:30:51.631422
8561 13:30:51.631532 [DATLAT]
8562 13:30:51.634585 Freq=1600, CH1 RK0
8563 13:30:51.634695
8564 13:30:51.637719 DATLAT Default: 0xf
8565 13:30:51.637825 0, 0xFFFF, sum = 0
8566 13:30:51.641488 1, 0xFFFF, sum = 0
8567 13:30:51.641593 2, 0xFFFF, sum = 0
8568 13:30:51.644538 3, 0xFFFF, sum = 0
8569 13:30:51.644645 4, 0xFFFF, sum = 0
8570 13:30:51.647731 5, 0xFFFF, sum = 0
8571 13:30:51.647838 6, 0xFFFF, sum = 0
8572 13:30:51.650855 7, 0xFFFF, sum = 0
8573 13:30:51.650954 8, 0xFFFF, sum = 0
8574 13:30:51.654514 9, 0xFFFF, sum = 0
8575 13:30:51.654614 10, 0xFFFF, sum = 0
8576 13:30:51.657681 11, 0xFFFF, sum = 0
8577 13:30:51.657753 12, 0xFFFF, sum = 0
8578 13:30:51.660792 13, 0xFFFF, sum = 0
8579 13:30:51.660893 14, 0x0, sum = 1
8580 13:30:51.664500 15, 0x0, sum = 2
8581 13:30:51.664610 16, 0x0, sum = 3
8582 13:30:51.667550 17, 0x0, sum = 4
8583 13:30:51.667653 best_step = 15
8584 13:30:51.667758
8585 13:30:51.667849 ==
8586 13:30:51.671086 Dram Type= 6, Freq= 0, CH_1, rank 0
8587 13:30:51.677720 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8588 13:30:51.677833 ==
8589 13:30:51.677929 RX Vref Scan: 1
8590 13:30:51.678019
8591 13:30:51.680516 Set Vref Range= 24 -> 127
8592 13:30:51.680613
8593 13:30:51.684195 RX Vref 24 -> 127, step: 1
8594 13:30:51.684298
8595 13:30:51.687127 RX Delay 11 -> 252, step: 4
8596 13:30:51.687233
8597 13:30:51.690830 Set Vref, RX VrefLevel [Byte0]: 24
8598 13:30:51.693839 [Byte1]: 24
8599 13:30:51.693941
8600 13:30:51.697344 Set Vref, RX VrefLevel [Byte0]: 25
8601 13:30:51.700149 [Byte1]: 25
8602 13:30:51.700256
8603 13:30:51.703811 Set Vref, RX VrefLevel [Byte0]: 26
8604 13:30:51.707090 [Byte1]: 26
8605 13:30:51.710203
8606 13:30:51.710289 Set Vref, RX VrefLevel [Byte0]: 27
8607 13:30:51.713551 [Byte1]: 27
8608 13:30:51.717787
8609 13:30:51.717870 Set Vref, RX VrefLevel [Byte0]: 28
8610 13:30:51.721304 [Byte1]: 28
8611 13:30:51.725868
8612 13:30:51.725951 Set Vref, RX VrefLevel [Byte0]: 29
8613 13:30:51.728921 [Byte1]: 29
8614 13:30:51.733153
8615 13:30:51.733239 Set Vref, RX VrefLevel [Byte0]: 30
8616 13:30:51.736707 [Byte1]: 30
8617 13:30:51.740950
8618 13:30:51.741033 Set Vref, RX VrefLevel [Byte0]: 31
8619 13:30:51.744080 [Byte1]: 31
8620 13:30:51.748490
8621 13:30:51.748572 Set Vref, RX VrefLevel [Byte0]: 32
8622 13:30:51.751651 [Byte1]: 32
8623 13:30:51.756006
8624 13:30:51.756089 Set Vref, RX VrefLevel [Byte0]: 33
8625 13:30:51.759030 [Byte1]: 33
8626 13:30:51.763838
8627 13:30:51.763950 Set Vref, RX VrefLevel [Byte0]: 34
8628 13:30:51.766919 [Byte1]: 34
8629 13:30:51.771179
8630 13:30:51.771254 Set Vref, RX VrefLevel [Byte0]: 35
8631 13:30:51.774239 [Byte1]: 35
8632 13:30:51.779046
8633 13:30:51.779121 Set Vref, RX VrefLevel [Byte0]: 36
8634 13:30:51.782034 [Byte1]: 36
8635 13:30:51.786275
8636 13:30:51.786348 Set Vref, RX VrefLevel [Byte0]: 37
8637 13:30:51.789828 [Byte1]: 37
8638 13:30:51.794323
8639 13:30:51.794396 Set Vref, RX VrefLevel [Byte0]: 38
8640 13:30:51.797294 [Byte1]: 38
8641 13:30:51.801679
8642 13:30:51.801752 Set Vref, RX VrefLevel [Byte0]: 39
8643 13:30:51.805129 [Byte1]: 39
8644 13:30:51.809474
8645 13:30:51.809559 Set Vref, RX VrefLevel [Byte0]: 40
8646 13:30:51.812751 [Byte1]: 40
8647 13:30:51.816762
8648 13:30:51.816839 Set Vref, RX VrefLevel [Byte0]: 41
8649 13:30:51.820170 [Byte1]: 41
8650 13:30:51.824737
8651 13:30:51.824817 Set Vref, RX VrefLevel [Byte0]: 42
8652 13:30:51.827910 [Byte1]: 42
8653 13:30:51.832430
8654 13:30:51.832505 Set Vref, RX VrefLevel [Byte0]: 43
8655 13:30:51.835340 [Byte1]: 43
8656 13:30:51.840015
8657 13:30:51.840097 Set Vref, RX VrefLevel [Byte0]: 44
8658 13:30:51.842990 [Byte1]: 44
8659 13:30:51.847192
8660 13:30:51.847275 Set Vref, RX VrefLevel [Byte0]: 45
8661 13:30:51.850385 [Byte1]: 45
8662 13:30:51.855056
8663 13:30:51.855138 Set Vref, RX VrefLevel [Byte0]: 46
8664 13:30:51.858078 [Byte1]: 46
8665 13:30:51.862352
8666 13:30:51.862434 Set Vref, RX VrefLevel [Byte0]: 47
8667 13:30:51.866099 [Byte1]: 47
8668 13:30:51.870523
8669 13:30:51.870609 Set Vref, RX VrefLevel [Byte0]: 48
8670 13:30:51.873521 [Byte1]: 48
8671 13:30:51.877952
8672 13:30:51.878034 Set Vref, RX VrefLevel [Byte0]: 49
8673 13:30:51.880902 [Byte1]: 49
8674 13:30:51.885600
8675 13:30:51.885681 Set Vref, RX VrefLevel [Byte0]: 50
8676 13:30:51.888680 [Byte1]: 50
8677 13:30:51.893027
8678 13:30:51.893109 Set Vref, RX VrefLevel [Byte0]: 51
8679 13:30:51.896707 [Byte1]: 51
8680 13:30:51.900690
8681 13:30:51.900775 Set Vref, RX VrefLevel [Byte0]: 52
8682 13:30:51.903680 [Byte1]: 52
8683 13:30:51.908144
8684 13:30:51.908226 Set Vref, RX VrefLevel [Byte0]: 53
8685 13:30:51.911774 [Byte1]: 53
8686 13:30:51.915763
8687 13:30:51.915867 Set Vref, RX VrefLevel [Byte0]: 54
8688 13:30:51.919127 [Byte1]: 54
8689 13:30:51.923703
8690 13:30:51.923813 Set Vref, RX VrefLevel [Byte0]: 55
8691 13:30:51.926648 [Byte1]: 55
8692 13:30:51.931177
8693 13:30:51.931283 Set Vref, RX VrefLevel [Byte0]: 56
8694 13:30:51.934539 [Byte1]: 56
8695 13:30:51.938915
8696 13:30:51.938996 Set Vref, RX VrefLevel [Byte0]: 57
8697 13:30:51.941945 [Byte1]: 57
8698 13:30:51.946133
8699 13:30:51.946233 Set Vref, RX VrefLevel [Byte0]: 58
8700 13:30:51.949873 [Byte1]: 58
8701 13:30:51.953857
8702 13:30:51.953960 Set Vref, RX VrefLevel [Byte0]: 59
8703 13:30:51.957111 [Byte1]: 59
8704 13:30:51.961362
8705 13:30:51.961435 Set Vref, RX VrefLevel [Byte0]: 60
8706 13:30:51.964750 [Byte1]: 60
8707 13:30:51.968984
8708 13:30:51.969088 Set Vref, RX VrefLevel [Byte0]: 61
8709 13:30:51.972630 [Byte1]: 61
8710 13:30:51.977016
8711 13:30:51.977088 Set Vref, RX VrefLevel [Byte0]: 62
8712 13:30:51.980187 [Byte1]: 62
8713 13:30:51.984419
8714 13:30:51.984493 Set Vref, RX VrefLevel [Byte0]: 63
8715 13:30:51.987546 [Byte1]: 63
8716 13:30:51.991634
8717 13:30:51.991737 Set Vref, RX VrefLevel [Byte0]: 64
8718 13:30:51.995334 [Byte1]: 64
8719 13:30:51.999577
8720 13:30:51.999675 Set Vref, RX VrefLevel [Byte0]: 65
8721 13:30:52.002684 [Byte1]: 65
8722 13:30:52.007220
8723 13:30:52.010215 Set Vref, RX VrefLevel [Byte0]: 66
8724 13:30:52.013973 [Byte1]: 66
8725 13:30:52.014047
8726 13:30:52.016935 Set Vref, RX VrefLevel [Byte0]: 67
8727 13:30:52.020035 [Byte1]: 67
8728 13:30:52.020111
8729 13:30:52.023638 Set Vref, RX VrefLevel [Byte0]: 68
8730 13:30:52.026538 [Byte1]: 68
8731 13:30:52.030039
8732 13:30:52.030143 Set Vref, RX VrefLevel [Byte0]: 69
8733 13:30:52.033421 [Byte1]: 69
8734 13:30:52.037926
8735 13:30:52.038000 Set Vref, RX VrefLevel [Byte0]: 70
8736 13:30:52.041185 [Byte1]: 70
8737 13:30:52.045563
8738 13:30:52.045642 Set Vref, RX VrefLevel [Byte0]: 71
8739 13:30:52.048530 [Byte1]: 71
8740 13:30:52.052949
8741 13:30:52.053026 Final RX Vref Byte 0 = 54 to rank0
8742 13:30:52.056059 Final RX Vref Byte 1 = 62 to rank0
8743 13:30:52.059729 Final RX Vref Byte 0 = 54 to rank1
8744 13:30:52.062816 Final RX Vref Byte 1 = 62 to rank1==
8745 13:30:52.066398 Dram Type= 6, Freq= 0, CH_1, rank 0
8746 13:30:52.072512 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8747 13:30:52.072618 ==
8748 13:30:52.072712 DQS Delay:
8749 13:30:52.072799 DQS0 = 0, DQS1 = 0
8750 13:30:52.076410 DQM Delay:
8751 13:30:52.076512 DQM0 = 132, DQM1 = 128
8752 13:30:52.079517 DQ Delay:
8753 13:30:52.082557 DQ0 =138, DQ1 =128, DQ2 =118, DQ3 =132
8754 13:30:52.086217 DQ4 =126, DQ5 =142, DQ6 =146, DQ7 =126
8755 13:30:52.089239 DQ8 =114, DQ9 =116, DQ10 =128, DQ11 =120
8756 13:30:52.092373 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =138
8757 13:30:52.092474
8758 13:30:52.092562
8759 13:30:52.092649
8760 13:30:52.095866 [DramC_TX_OE_Calibration] TA2
8761 13:30:52.099083 Original DQ_B0 (3 6) =30, OEN = 27
8762 13:30:52.102152 Original DQ_B1 (3 6) =30, OEN = 27
8763 13:30:52.105928 24, 0x0, End_B0=24 End_B1=24
8764 13:30:52.106034 25, 0x0, End_B0=25 End_B1=25
8765 13:30:52.108823 26, 0x0, End_B0=26 End_B1=26
8766 13:30:52.112443 27, 0x0, End_B0=27 End_B1=27
8767 13:30:52.115351 28, 0x0, End_B0=28 End_B1=28
8768 13:30:52.118834 29, 0x0, End_B0=29 End_B1=29
8769 13:30:52.118940 30, 0x0, End_B0=30 End_B1=30
8770 13:30:52.122440 31, 0x4141, End_B0=30 End_B1=30
8771 13:30:52.125577 Byte0 end_step=30 best_step=27
8772 13:30:52.128706 Byte1 end_step=30 best_step=27
8773 13:30:52.132188 Byte0 TX OE(2T, 0.5T) = (3, 3)
8774 13:30:52.135130 Byte1 TX OE(2T, 0.5T) = (3, 3)
8775 13:30:52.135231
8776 13:30:52.135309
8777 13:30:52.141930 [DQSOSCAuto] RK0, (LSB)MR18= 0xa13, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 404 ps
8778 13:30:52.145440 CH1 RK0: MR19=303, MR18=A13
8779 13:30:52.151571 CH1_RK0: MR19=0x303, MR18=0xA13, DQSOSC=400, MR23=63, INC=23, DEC=15
8780 13:30:52.151683
8781 13:30:52.155109 ----->DramcWriteLeveling(PI) begin...
8782 13:30:52.155215 ==
8783 13:30:52.158354 Dram Type= 6, Freq= 0, CH_1, rank 1
8784 13:30:52.161332 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8785 13:30:52.161433 ==
8786 13:30:52.165124 Write leveling (Byte 0): 23 => 23
8787 13:30:52.168172 Write leveling (Byte 1): 26 => 26
8788 13:30:52.171122 DramcWriteLeveling(PI) end<-----
8789 13:30:52.171224
8790 13:30:52.171315 ==
8791 13:30:52.174602 Dram Type= 6, Freq= 0, CH_1, rank 1
8792 13:30:52.177705 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8793 13:30:52.181045 ==
8794 13:30:52.181148 [Gating] SW mode calibration
8795 13:30:52.191065 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8796 13:30:52.194643 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8797 13:30:52.197948 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8798 13:30:52.204056 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8799 13:30:52.207100 1 4 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
8800 13:30:52.210915 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8801 13:30:52.217579 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8802 13:30:52.220507 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8803 13:30:52.223898 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8804 13:30:52.230491 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8805 13:30:52.234093 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8806 13:30:52.237158 1 5 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8807 13:30:52.243723 1 5 8 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 1)
8808 13:30:52.246885 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8809 13:30:52.250435 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8810 13:30:52.256976 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 13:30:52.259954 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 13:30:52.266390 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8813 13:30:52.270052 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8814 13:30:52.273154 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8815 13:30:52.279811 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8816 13:30:52.283339 1 6 12 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
8817 13:30:52.286393 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8818 13:30:52.293356 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8819 13:30:52.296395 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 13:30:52.299383 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8821 13:30:52.305888 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8822 13:30:52.309606 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8823 13:30:52.312548 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8824 13:30:52.319338 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8825 13:30:52.322434 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8826 13:30:52.325635 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 13:30:52.332103 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 13:30:52.335564 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 13:30:52.338801 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 13:30:52.345830 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 13:30:52.349277 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 13:30:52.352182 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 13:30:52.359308 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 13:30:52.362331 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 13:30:52.365287 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 13:30:52.371745 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 13:30:52.375367 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 13:30:52.378489 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8839 13:30:52.385023 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8840 13:30:52.388038 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8841 13:30:52.391705 Total UI for P1: 0, mck2ui 16
8842 13:30:52.394552 best dqsien dly found for B0: ( 1, 9, 6)
8843 13:30:52.397947 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8844 13:30:52.401621 Total UI for P1: 0, mck2ui 16
8845 13:30:52.404503 best dqsien dly found for B1: ( 1, 9, 12)
8846 13:30:52.407880 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8847 13:30:52.411502 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8848 13:30:52.411598
8849 13:30:52.417658 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8850 13:30:52.421348 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8851 13:30:52.424442 [Gating] SW calibration Done
8852 13:30:52.424522 ==
8853 13:30:52.427565 Dram Type= 6, Freq= 0, CH_1, rank 1
8854 13:30:52.430726 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8855 13:30:52.430810 ==
8856 13:30:52.430895 RX Vref Scan: 0
8857 13:30:52.430975
8858 13:30:52.434388 RX Vref 0 -> 0, step: 1
8859 13:30:52.434471
8860 13:30:52.437613 RX Delay 0 -> 252, step: 8
8861 13:30:52.440940 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8862 13:30:52.444445 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8863 13:30:52.450563 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8864 13:30:52.453811 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8865 13:30:52.457151 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8866 13:30:52.460659 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8867 13:30:52.463629 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8868 13:30:52.470390 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8869 13:30:52.473966 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8870 13:30:52.477411 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8871 13:30:52.480333 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8872 13:30:52.483384 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8873 13:30:52.490077 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8874 13:30:52.493856 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8875 13:30:52.496694 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8876 13:30:52.500162 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8877 13:30:52.500246 ==
8878 13:30:52.503757 Dram Type= 6, Freq= 0, CH_1, rank 1
8879 13:30:52.509881 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8880 13:30:52.509966 ==
8881 13:30:52.510051 DQS Delay:
8882 13:30:52.513334 DQS0 = 0, DQS1 = 0
8883 13:30:52.513458 DQM Delay:
8884 13:30:52.516922 DQM0 = 132, DQM1 = 130
8885 13:30:52.517005 DQ Delay:
8886 13:30:52.520342 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8887 13:30:52.523452 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8888 13:30:52.526486 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8889 13:30:52.529607 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8890 13:30:52.529690
8891 13:30:52.529775
8892 13:30:52.529854 ==
8893 13:30:52.533120 Dram Type= 6, Freq= 0, CH_1, rank 1
8894 13:30:52.539668 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8895 13:30:52.539782 ==
8896 13:30:52.539883
8897 13:30:52.540004
8898 13:30:52.540083 TX Vref Scan disable
8899 13:30:52.543545 == TX Byte 0 ==
8900 13:30:52.546498 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8901 13:30:52.552988 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8902 13:30:52.553073 == TX Byte 1 ==
8903 13:30:52.556715 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8904 13:30:52.563210 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8905 13:30:52.563294 ==
8906 13:30:52.566028 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 13:30:52.569676 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 13:30:52.569796 ==
8909 13:30:52.583442
8910 13:30:52.586187 TX Vref early break, caculate TX vref
8911 13:30:52.589692 TX Vref=16, minBit 9, minWin=20, winSum=375
8912 13:30:52.592850 TX Vref=18, minBit 9, minWin=22, winSum=383
8913 13:30:52.596574 TX Vref=20, minBit 9, minWin=22, winSum=393
8914 13:30:52.599646 TX Vref=22, minBit 9, minWin=24, winSum=402
8915 13:30:52.602543 TX Vref=24, minBit 9, minWin=23, winSum=407
8916 13:30:52.609445 TX Vref=26, minBit 9, minWin=24, winSum=419
8917 13:30:52.612457 TX Vref=28, minBit 9, minWin=25, winSum=422
8918 13:30:52.616082 TX Vref=30, minBit 0, minWin=25, winSum=414
8919 13:30:52.619267 TX Vref=32, minBit 8, minWin=24, winSum=408
8920 13:30:52.622730 TX Vref=34, minBit 9, minWin=23, winSum=403
8921 13:30:52.629113 TX Vref=36, minBit 9, minWin=23, winSum=396
8922 13:30:52.632136 [TxChooseVref] Worse bit 9, Min win 25, Win sum 422, Final Vref 28
8923 13:30:52.632241
8924 13:30:52.635720 Final TX Range 0 Vref 28
8925 13:30:52.635806
8926 13:30:52.635927 ==
8927 13:30:52.638887 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 13:30:52.642053 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 13:30:52.645378 ==
8930 13:30:52.645462
8931 13:30:52.645546
8932 13:30:52.645625 TX Vref Scan disable
8933 13:30:52.652588 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8934 13:30:52.652680 == TX Byte 0 ==
8935 13:30:52.655521 u2DelayCellOfst[0]=10 cells (3 PI)
8936 13:30:52.659042 u2DelayCellOfst[1]=7 cells (2 PI)
8937 13:30:52.662602 u2DelayCellOfst[2]=0 cells (0 PI)
8938 13:30:52.665726 u2DelayCellOfst[3]=3 cells (1 PI)
8939 13:30:52.668871 u2DelayCellOfst[4]=7 cells (2 PI)
8940 13:30:52.671977 u2DelayCellOfst[5]=10 cells (3 PI)
8941 13:30:52.675445 u2DelayCellOfst[6]=14 cells (4 PI)
8942 13:30:52.678860 u2DelayCellOfst[7]=3 cells (1 PI)
8943 13:30:52.682023 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8944 13:30:52.685311 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8945 13:30:52.688763 == TX Byte 1 ==
8946 13:30:52.691562 u2DelayCellOfst[8]=0 cells (0 PI)
8947 13:30:52.695093 u2DelayCellOfst[9]=3 cells (1 PI)
8948 13:30:52.698292 u2DelayCellOfst[10]=10 cells (3 PI)
8949 13:30:52.701965 u2DelayCellOfst[11]=7 cells (2 PI)
8950 13:30:52.704984 u2DelayCellOfst[12]=14 cells (4 PI)
8951 13:30:52.708074 u2DelayCellOfst[13]=14 cells (4 PI)
8952 13:30:52.711637 u2DelayCellOfst[14]=18 cells (5 PI)
8953 13:30:52.711739 u2DelayCellOfst[15]=18 cells (5 PI)
8954 13:30:52.718115 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8955 13:30:52.721350 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8956 13:30:52.724984 DramC Write-DBI on
8957 13:30:52.725065 ==
8958 13:30:52.727968 Dram Type= 6, Freq= 0, CH_1, rank 1
8959 13:30:52.731509 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8960 13:30:52.731590 ==
8961 13:30:52.731653
8962 13:30:52.731712
8963 13:30:52.734439 TX Vref Scan disable
8964 13:30:52.734521 == TX Byte 0 ==
8965 13:30:52.740957 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8966 13:30:52.741083 == TX Byte 1 ==
8967 13:30:52.744632 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8968 13:30:52.747677 DramC Write-DBI off
8969 13:30:52.747768
8970 13:30:52.747835 [DATLAT]
8971 13:30:52.751332 Freq=1600, CH1 RK1
8972 13:30:52.751415
8973 13:30:52.751479 DATLAT Default: 0xf
8974 13:30:52.754355 0, 0xFFFF, sum = 0
8975 13:30:52.757377 1, 0xFFFF, sum = 0
8976 13:30:52.757469 2, 0xFFFF, sum = 0
8977 13:30:52.761087 3, 0xFFFF, sum = 0
8978 13:30:52.761189 4, 0xFFFF, sum = 0
8979 13:30:52.764145 5, 0xFFFF, sum = 0
8980 13:30:52.764264 6, 0xFFFF, sum = 0
8981 13:30:52.767629 7, 0xFFFF, sum = 0
8982 13:30:52.767745 8, 0xFFFF, sum = 0
8983 13:30:52.770773 9, 0xFFFF, sum = 0
8984 13:30:52.770857 10, 0xFFFF, sum = 0
8985 13:30:52.773890 11, 0xFFFF, sum = 0
8986 13:30:52.773974 12, 0xFFFF, sum = 0
8987 13:30:52.777617 13, 0xFFFF, sum = 0
8988 13:30:52.777728 14, 0x0, sum = 1
8989 13:30:52.780768 15, 0x0, sum = 2
8990 13:30:52.780880 16, 0x0, sum = 3
8991 13:30:52.783769 17, 0x0, sum = 4
8992 13:30:52.783870 best_step = 15
8993 13:30:52.783956
8994 13:30:52.784017 ==
8995 13:30:52.787581 Dram Type= 6, Freq= 0, CH_1, rank 1
8996 13:30:52.794133 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8997 13:30:52.794240 ==
8998 13:30:52.794339 RX Vref Scan: 0
8999 13:30:52.794431
9000 13:30:52.796949 RX Vref 0 -> 0, step: 1
9001 13:30:52.797018
9002 13:30:52.800709 RX Delay 19 -> 252, step: 4
9003 13:30:52.804020 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
9004 13:30:52.807043 iDelay=195, Bit 1, Center 128 (75 ~ 182) 108
9005 13:30:52.810855 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
9006 13:30:52.816906 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
9007 13:30:52.820453 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
9008 13:30:52.823795 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
9009 13:30:52.826965 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
9010 13:30:52.830086 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
9011 13:30:52.836957 iDelay=195, Bit 8, Center 114 (63 ~ 166) 104
9012 13:30:52.839991 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9013 13:30:52.843391 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9014 13:30:52.846907 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9015 13:30:52.852960 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
9016 13:30:52.856605 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9017 13:30:52.859687 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
9018 13:30:52.862786 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
9019 13:30:52.862857 ==
9020 13:30:52.866501 Dram Type= 6, Freq= 0, CH_1, rank 1
9021 13:30:52.872498 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9022 13:30:52.872577 ==
9023 13:30:52.872642 DQS Delay:
9024 13:30:52.876003 DQS0 = 0, DQS1 = 0
9025 13:30:52.876076 DQM Delay:
9026 13:30:52.879627 DQM0 = 131, DQM1 = 128
9027 13:30:52.879730 DQ Delay:
9028 13:30:52.882574 DQ0 =134, DQ1 =128, DQ2 =120, DQ3 =128
9029 13:30:52.885655 DQ4 =130, DQ5 =142, DQ6 =140, DQ7 =128
9030 13:30:52.889340 DQ8 =114, DQ9 =118, DQ10 =128, DQ11 =120
9031 13:30:52.892536 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =138
9032 13:30:52.892621
9033 13:30:52.892687
9034 13:30:52.892746
9035 13:30:52.895550 [DramC_TX_OE_Calibration] TA2
9036 13:30:52.899165 Original DQ_B0 (3 6) =30, OEN = 27
9037 13:30:52.902647 Original DQ_B1 (3 6) =30, OEN = 27
9038 13:30:52.906017 24, 0x0, End_B0=24 End_B1=24
9039 13:30:52.909236 25, 0x0, End_B0=25 End_B1=25
9040 13:30:52.909347 26, 0x0, End_B0=26 End_B1=26
9041 13:30:52.912485 27, 0x0, End_B0=27 End_B1=27
9042 13:30:52.915771 28, 0x0, End_B0=28 End_B1=28
9043 13:30:52.918771 29, 0x0, End_B0=29 End_B1=29
9044 13:30:52.918857 30, 0x0, End_B0=30 End_B1=30
9045 13:30:52.922467 31, 0x4545, End_B0=30 End_B1=30
9046 13:30:52.925447 Byte0 end_step=30 best_step=27
9047 13:30:52.928714 Byte1 end_step=30 best_step=27
9048 13:30:52.932259 Byte0 TX OE(2T, 0.5T) = (3, 3)
9049 13:30:52.935394 Byte1 TX OE(2T, 0.5T) = (3, 3)
9050 13:30:52.935476
9051 13:30:52.935545
9052 13:30:52.942232 [DQSOSCAuto] RK1, (LSB)MR18= 0xc1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
9053 13:30:52.945173 CH1 RK1: MR19=303, MR18=C1A
9054 13:30:52.951750 CH1_RK1: MR19=0x303, MR18=0xC1A, DQSOSC=396, MR23=63, INC=23, DEC=15
9055 13:30:52.955493 [RxdqsGatingPostProcess] freq 1600
9056 13:30:52.961584 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9057 13:30:52.961666 best DQS0 dly(2T, 0.5T) = (1, 1)
9058 13:30:52.965268 best DQS1 dly(2T, 0.5T) = (1, 1)
9059 13:30:52.968402 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9060 13:30:52.971561 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9061 13:30:52.974511 best DQS0 dly(2T, 0.5T) = (1, 1)
9062 13:30:52.978298 best DQS1 dly(2T, 0.5T) = (1, 1)
9063 13:30:52.981317 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9064 13:30:52.984775 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9065 13:30:52.988274 Pre-setting of DQS Precalculation
9066 13:30:52.991181 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9067 13:30:53.000941 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9068 13:30:53.007679 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9069 13:30:53.007793
9070 13:30:53.007912
9071 13:30:53.011166 [Calibration Summary] 3200 Mbps
9072 13:30:53.011249 CH 0, Rank 0
9073 13:30:53.014127 SW Impedance : PASS
9074 13:30:53.014235 DUTY Scan : NO K
9075 13:30:53.017755 ZQ Calibration : PASS
9076 13:30:53.021118 Jitter Meter : NO K
9077 13:30:53.021200 CBT Training : PASS
9078 13:30:53.024423 Write leveling : PASS
9079 13:30:53.027330 RX DQS gating : PASS
9080 13:30:53.027439 RX DQ/DQS(RDDQC) : PASS
9081 13:30:53.031013 TX DQ/DQS : PASS
9082 13:30:53.033889 RX DATLAT : PASS
9083 13:30:53.033994 RX DQ/DQS(Engine): PASS
9084 13:30:53.037258 TX OE : PASS
9085 13:30:53.037333 All Pass.
9086 13:30:53.037394
9087 13:30:53.040868 CH 0, Rank 1
9088 13:30:53.040950 SW Impedance : PASS
9089 13:30:53.043794 DUTY Scan : NO K
9090 13:30:53.047312 ZQ Calibration : PASS
9091 13:30:53.047395 Jitter Meter : NO K
9092 13:30:53.051024 CBT Training : PASS
9093 13:30:53.054168 Write leveling : PASS
9094 13:30:53.054251 RX DQS gating : PASS
9095 13:30:53.057117 RX DQ/DQS(RDDQC) : PASS
9096 13:30:53.060572 TX DQ/DQS : PASS
9097 13:30:53.060655 RX DATLAT : PASS
9098 13:30:53.063579 RX DQ/DQS(Engine): PASS
9099 13:30:53.067298 TX OE : PASS
9100 13:30:53.067383 All Pass.
9101 13:30:53.067449
9102 13:30:53.067508 CH 1, Rank 0
9103 13:30:53.070397 SW Impedance : PASS
9104 13:30:53.073524 DUTY Scan : NO K
9105 13:30:53.073606 ZQ Calibration : PASS
9106 13:30:53.077260 Jitter Meter : NO K
9107 13:30:53.080264 CBT Training : PASS
9108 13:30:53.080346 Write leveling : PASS
9109 13:30:53.083456 RX DQS gating : PASS
9110 13:30:53.083538 RX DQ/DQS(RDDQC) : PASS
9111 13:30:53.086555 TX DQ/DQS : PASS
9112 13:30:53.090174 RX DATLAT : PASS
9113 13:30:53.090255 RX DQ/DQS(Engine): PASS
9114 13:30:53.093190 TX OE : PASS
9115 13:30:53.093272 All Pass.
9116 13:30:53.093356
9117 13:30:53.096526 CH 1, Rank 1
9118 13:30:53.096607 SW Impedance : PASS
9119 13:30:53.099995 DUTY Scan : NO K
9120 13:30:53.103147 ZQ Calibration : PASS
9121 13:30:53.103229 Jitter Meter : NO K
9122 13:30:53.106247 CBT Training : PASS
9123 13:30:53.109877 Write leveling : PASS
9124 13:30:53.109963 RX DQS gating : PASS
9125 13:30:53.113357 RX DQ/DQS(RDDQC) : PASS
9126 13:30:53.116367 TX DQ/DQS : PASS
9127 13:30:53.116450 RX DATLAT : PASS
9128 13:30:53.119403 RX DQ/DQS(Engine): PASS
9129 13:30:53.123149 TX OE : PASS
9130 13:30:53.123232 All Pass.
9131 13:30:53.123297
9132 13:30:53.126109 DramC Write-DBI on
9133 13:30:53.126191 PER_BANK_REFRESH: Hybrid Mode
9134 13:30:53.129649 TX_TRACKING: ON
9135 13:30:53.139779 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9136 13:30:53.145929 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9137 13:30:53.152777 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9138 13:30:53.155867 [FAST_K] Save calibration result to emmc
9139 13:30:53.159020 sync common calibartion params.
9140 13:30:53.162191 sync cbt_mode0:1, 1:1
9141 13:30:53.162268 dram_init: ddr_geometry: 2
9142 13:30:53.165743 dram_init: ddr_geometry: 2
9143 13:30:53.168703 dram_init: ddr_geometry: 2
9144 13:30:53.172339 0:dram_rank_size:100000000
9145 13:30:53.172420 1:dram_rank_size:100000000
9146 13:30:53.178664 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9147 13:30:53.182283 DFS_SHUFFLE_HW_MODE: ON
9148 13:30:53.185426 dramc_set_vcore_voltage set vcore to 725000
9149 13:30:53.188506 Read voltage for 1600, 0
9150 13:30:53.188586 Vio18 = 0
9151 13:30:53.188680 Vcore = 725000
9152 13:30:53.192222 Vdram = 0
9153 13:30:53.192297 Vddq = 0
9154 13:30:53.192358 Vmddr = 0
9155 13:30:53.195204 switch to 3200 Mbps bootup
9156 13:30:53.195307 [DramcRunTimeConfig]
9157 13:30:53.198932 PHYPLL
9158 13:30:53.199004 DPM_CONTROL_AFTERK: ON
9159 13:30:53.201939 PER_BANK_REFRESH: ON
9160 13:30:53.205358 REFRESH_OVERHEAD_REDUCTION: ON
9161 13:30:53.205483 CMD_PICG_NEW_MODE: OFF
9162 13:30:53.208308 XRTWTW_NEW_MODE: ON
9163 13:30:53.208386 XRTRTR_NEW_MODE: ON
9164 13:30:53.211980 TX_TRACKING: ON
9165 13:30:53.212060 RDSEL_TRACKING: OFF
9166 13:30:53.214813 DQS Precalculation for DVFS: ON
9167 13:30:53.218346 RX_TRACKING: OFF
9168 13:30:53.218422 HW_GATING DBG: ON
9169 13:30:53.221347 ZQCS_ENABLE_LP4: ON
9170 13:30:53.221429 RX_PICG_NEW_MODE: ON
9171 13:30:53.225039 TX_PICG_NEW_MODE: ON
9172 13:30:53.228027 ENABLE_RX_DCM_DPHY: ON
9173 13:30:53.231785 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9174 13:30:53.231891 DUMMY_READ_FOR_TRACKING: OFF
9175 13:30:53.234925 !!! SPM_CONTROL_AFTERK: OFF
9176 13:30:53.237800 !!! SPM could not control APHY
9177 13:30:53.241099 IMPEDANCE_TRACKING: ON
9178 13:30:53.241176 TEMP_SENSOR: ON
9179 13:30:53.244463 HW_SAVE_FOR_SR: OFF
9180 13:30:53.244570 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9181 13:30:53.251206 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9182 13:30:53.251313 Read ODT Tracking: ON
9183 13:30:53.254630 Refresh Rate DeBounce: ON
9184 13:30:53.257957 DFS_NO_QUEUE_FLUSH: ON
9185 13:30:53.260919 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9186 13:30:53.261000 ENABLE_DFS_RUNTIME_MRW: OFF
9187 13:30:53.264613 DDR_RESERVE_NEW_MODE: ON
9188 13:30:53.267539 MR_CBT_SWITCH_FREQ: ON
9189 13:30:53.267648 =========================
9190 13:30:53.287216 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9191 13:30:53.290798 dram_init: ddr_geometry: 2
9192 13:30:53.308684 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9193 13:30:53.312166 dram_init: dram init end (result: 0)
9194 13:30:53.318938 DRAM-K: Full calibration passed in 24487 msecs
9195 13:30:53.321825 MRC: failed to locate region type 0.
9196 13:30:53.321910 DRAM rank0 size:0x100000000,
9197 13:30:53.325541 DRAM rank1 size=0x100000000
9198 13:30:53.335194 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9199 13:30:53.341729 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9200 13:30:53.351634 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9201 13:30:53.358314 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9202 13:30:53.358430 DRAM rank0 size:0x100000000,
9203 13:30:53.361223 DRAM rank1 size=0x100000000
9204 13:30:53.361332 CBMEM:
9205 13:30:53.364584 IMD: root @ 0xfffff000 254 entries.
9206 13:30:53.368043 IMD: root @ 0xffffec00 62 entries.
9207 13:30:53.374795 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9208 13:30:53.377794 WARNING: RO_VPD is uninitialized or empty.
9209 13:30:53.381306 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9210 13:30:53.388845 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9211 13:30:53.401703 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9212 13:30:53.413331 BS: romstage times (exec / console): total (unknown) / 24004 ms
9213 13:30:53.413444
9214 13:30:53.413538
9215 13:30:53.423468 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9216 13:30:53.426313 ARM64: Exception handlers installed.
9217 13:30:53.429572 ARM64: Testing exception
9218 13:30:53.432867 ARM64: Done test exception
9219 13:30:53.432970 Enumerating buses...
9220 13:30:53.436107 Show all devs... Before device enumeration.
9221 13:30:53.439643 Root Device: enabled 1
9222 13:30:53.442648 CPU_CLUSTER: 0: enabled 1
9223 13:30:53.442753 CPU: 00: enabled 1
9224 13:30:53.446259 Compare with tree...
9225 13:30:53.446335 Root Device: enabled 1
9226 13:30:53.449427 CPU_CLUSTER: 0: enabled 1
9227 13:30:53.452915 CPU: 00: enabled 1
9228 13:30:53.452987 Root Device scanning...
9229 13:30:53.455770 scan_static_bus for Root Device
9230 13:30:53.459303 CPU_CLUSTER: 0 enabled
9231 13:30:53.462809 scan_static_bus for Root Device done
9232 13:30:53.465793 scan_bus: bus Root Device finished in 8 msecs
9233 13:30:53.465911 done
9234 13:30:53.472367 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9235 13:30:53.475921 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9236 13:30:53.482074 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9237 13:30:53.485777 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9238 13:30:53.488751 Allocating resources...
9239 13:30:53.492347 Reading resources...
9240 13:30:53.495604 Root Device read_resources bus 0 link: 0
9241 13:30:53.498710 DRAM rank0 size:0x100000000,
9242 13:30:53.498790 DRAM rank1 size=0x100000000
9243 13:30:53.505416 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9244 13:30:53.505497 CPU: 00 missing read_resources
9245 13:30:53.512182 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9246 13:30:53.515331 Root Device read_resources bus 0 link: 0 done
9247 13:30:53.518358 Done reading resources.
9248 13:30:53.522067 Show resources in subtree (Root Device)...After reading.
9249 13:30:53.525066 Root Device child on link 0 CPU_CLUSTER: 0
9250 13:30:53.528580 CPU_CLUSTER: 0 child on link 0 CPU: 00
9251 13:30:53.538033 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9252 13:30:53.538150 CPU: 00
9253 13:30:53.544833 Root Device assign_resources, bus 0 link: 0
9254 13:30:53.548237 CPU_CLUSTER: 0 missing set_resources
9255 13:30:53.551334 Root Device assign_resources, bus 0 link: 0 done
9256 13:30:53.551445 Done setting resources.
9257 13:30:53.558092 Show resources in subtree (Root Device)...After assigning values.
9258 13:30:53.561581 Root Device child on link 0 CPU_CLUSTER: 0
9259 13:30:53.564456 CPU_CLUSTER: 0 child on link 0 CPU: 00
9260 13:30:53.574638 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9261 13:30:53.574757 CPU: 00
9262 13:30:53.577724 Done allocating resources.
9263 13:30:53.584341 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9264 13:30:53.584426 Enabling resources...
9265 13:30:53.587580 done.
9266 13:30:53.591185 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9267 13:30:53.594129 Initializing devices...
9268 13:30:53.594212 Root Device init
9269 13:30:53.597885 init hardware done!
9270 13:30:53.597969 0x00000018: ctrlr->caps
9271 13:30:53.600992 52.000 MHz: ctrlr->f_max
9272 13:30:53.604663 0.400 MHz: ctrlr->f_min
9273 13:30:53.604748 0x40ff8080: ctrlr->voltages
9274 13:30:53.607761 sclk: 390625
9275 13:30:53.607843 Bus Width = 1
9276 13:30:53.610947 sclk: 390625
9277 13:30:53.611029 Bus Width = 1
9278 13:30:53.614062 Early init status = 3
9279 13:30:53.617203 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9280 13:30:53.621019 in-header: 03 fc 00 00 01 00 00 00
9281 13:30:53.624060 in-data: 00
9282 13:30:53.627158 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9283 13:30:53.631986 in-header: 03 fd 00 00 00 00 00 00
9284 13:30:53.635087 in-data:
9285 13:30:53.638593 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9286 13:30:53.641745 in-header: 03 fc 00 00 01 00 00 00
9287 13:30:53.645430 in-data: 00
9288 13:30:53.648376 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9289 13:30:53.652993 in-header: 03 fd 00 00 00 00 00 00
9290 13:30:53.656341 in-data:
9291 13:30:53.659615 [SSUSB] Setting up USB HOST controller...
9292 13:30:53.663108 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9293 13:30:53.666067 [SSUSB] phy power-on done.
9294 13:30:53.669561 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9295 13:30:53.676473 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9296 13:30:53.679630 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9297 13:30:53.686337 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9298 13:30:53.692723 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9299 13:30:53.699145 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9300 13:30:53.705832 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9301 13:30:53.712432 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9302 13:30:53.715555 SPM: binary array size = 0x9dc
9303 13:30:53.719227 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9304 13:30:53.725364 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9305 13:30:53.732167 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9306 13:30:53.738850 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9307 13:30:53.741817 configure_display: Starting display init
9308 13:30:53.776325 anx7625_power_on_init: Init interface.
9309 13:30:53.779660 anx7625_disable_pd_protocol: Disabled PD feature.
9310 13:30:53.783124 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9311 13:30:53.811051 anx7625_start_dp_work: Secure OCM version=00
9312 13:30:53.814196 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9313 13:30:53.828968 sp_tx_get_edid_block: EDID Block = 1
9314 13:30:53.931468 Extracted contents:
9315 13:30:53.934393 header: 00 ff ff ff ff ff ff 00
9316 13:30:53.938328 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9317 13:30:53.941471 version: 01 04
9318 13:30:53.944373 basic params: 95 1f 11 78 0a
9319 13:30:53.948058 chroma info: 76 90 94 55 54 90 27 21 50 54
9320 13:30:53.951129 established: 00 00 00
9321 13:30:53.957745 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9322 13:30:53.964273 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9323 13:30:53.967756 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9324 13:30:53.974597 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9325 13:30:53.980734 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9326 13:30:53.984161 extensions: 00
9327 13:30:53.984267 checksum: fb
9328 13:30:53.984337
9329 13:30:53.990319 Manufacturer: IVO Model 57d Serial Number 0
9330 13:30:53.990423 Made week 0 of 2020
9331 13:30:53.994168 EDID version: 1.4
9332 13:30:53.994262 Digital display
9333 13:30:53.996927 6 bits per primary color channel
9334 13:30:54.000227 DisplayPort interface
9335 13:30:54.000359 Maximum image size: 31 cm x 17 cm
9336 13:30:54.003652 Gamma: 220%
9337 13:30:54.003755 Check DPMS levels
9338 13:30:54.010487 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9339 13:30:54.013413 First detailed timing is preferred timing
9340 13:30:54.016791 Established timings supported:
9341 13:30:54.016918 Standard timings supported:
9342 13:30:54.020093 Detailed timings
9343 13:30:54.023138 Hex of detail: 383680a07038204018303c0035ae10000019
9344 13:30:54.029705 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9345 13:30:54.033410 0780 0798 07c8 0820 hborder 0
9346 13:30:54.036590 0438 043b 0447 0458 vborder 0
9347 13:30:54.039800 -hsync -vsync
9348 13:30:54.039884 Did detailed timing
9349 13:30:54.046729 Hex of detail: 000000000000000000000000000000000000
9350 13:30:54.049612 Manufacturer-specified data, tag 0
9351 13:30:54.052609 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9352 13:30:54.056446 ASCII string: InfoVision
9353 13:30:54.059542 Hex of detail: 000000fe00523134304e574635205248200a
9354 13:30:54.062514 ASCII string: R140NWF5 RH
9355 13:30:54.062597 Checksum
9356 13:30:54.066113 Checksum: 0xfb (valid)
9357 13:30:54.069211 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9358 13:30:54.072595 DSI data_rate: 832800000 bps
9359 13:30:54.079034 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9360 13:30:54.082775 anx7625_parse_edid: pixelclock(138800).
9361 13:30:54.085827 hactive(1920), hsync(48), hfp(24), hbp(88)
9362 13:30:54.089085 vactive(1080), vsync(12), vfp(3), vbp(17)
9363 13:30:54.092746 anx7625_dsi_config: config dsi.
9364 13:30:54.099123 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9365 13:30:54.113334 anx7625_dsi_config: success to config DSI
9366 13:30:54.116507 anx7625_dp_start: MIPI phy setup OK.
9367 13:30:54.120029 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9368 13:30:54.123565 mtk_ddp_mode_set invalid vrefresh 60
9369 13:30:54.126460 main_disp_path_setup
9370 13:30:54.126562 ovl_layer_smi_id_en
9371 13:30:54.129801 ovl_layer_smi_id_en
9372 13:30:54.129892 ccorr_config
9373 13:30:54.129956 aal_config
9374 13:30:54.132818 gamma_config
9375 13:30:54.132905 postmask_config
9376 13:30:54.136505 dither_config
9377 13:30:54.139573 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9378 13:30:54.146447 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9379 13:30:54.149532 Root Device init finished in 551 msecs
9380 13:30:54.152814 CPU_CLUSTER: 0 init
9381 13:30:54.159341 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9382 13:30:54.166089 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9383 13:30:54.166178 APU_MBOX 0x190000b0 = 0x10001
9384 13:30:54.169043 APU_MBOX 0x190001b0 = 0x10001
9385 13:30:54.172686 APU_MBOX 0x190005b0 = 0x10001
9386 13:30:54.175912 APU_MBOX 0x190006b0 = 0x10001
9387 13:30:54.182253 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9388 13:30:54.192436 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9389 13:30:54.204843 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9390 13:30:54.211561 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9391 13:30:54.222791 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9392 13:30:54.232171 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9393 13:30:54.235175 CPU_CLUSTER: 0 init finished in 81 msecs
9394 13:30:54.238673 Devices initialized
9395 13:30:54.242383 Show all devs... After init.
9396 13:30:54.242470 Root Device: enabled 1
9397 13:30:54.245498 CPU_CLUSTER: 0: enabled 1
9398 13:30:54.248566 CPU: 00: enabled 1
9399 13:30:54.251665 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9400 13:30:54.255249 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9401 13:30:54.258349 ELOG: NV offset 0x57f000 size 0x1000
9402 13:30:54.265640 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9403 13:30:54.272248 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9404 13:30:54.275347 ELOG: Event(17) added with size 13 at 2023-09-08 13:30:57 UTC
9405 13:30:54.281494 out: cmd=0x121: 03 db 21 01 00 00 00 00
9406 13:30:54.285043 in-header: 03 ed 00 00 2c 00 00 00
9407 13:30:54.294955 in-data: 72 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9408 13:30:54.301826 ELOG: Event(A1) added with size 10 at 2023-09-08 13:30:57 UTC
9409 13:30:54.308274 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9410 13:30:54.314757 ELOG: Event(A0) added with size 9 at 2023-09-08 13:30:57 UTC
9411 13:30:54.317707 elog_add_boot_reason: Logged dev mode boot
9412 13:30:54.324397 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9413 13:30:54.324485 Finalize devices...
9414 13:30:54.327815 Devices finalized
9415 13:30:54.330856 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9416 13:30:54.334409 Writing coreboot table at 0xffe64000
9417 13:30:54.337829 0. 000000000010a000-0000000000113fff: RAMSTAGE
9418 13:30:54.344414 1. 0000000040000000-00000000400fffff: RAM
9419 13:30:54.347448 2. 0000000040100000-000000004032afff: RAMSTAGE
9420 13:30:54.351160 3. 000000004032b000-00000000545fffff: RAM
9421 13:30:54.354195 4. 0000000054600000-000000005465ffff: BL31
9422 13:30:54.357280 5. 0000000054660000-00000000ffe63fff: RAM
9423 13:30:54.363849 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9424 13:30:54.367430 7. 0000000100000000-000000023fffffff: RAM
9425 13:30:54.370604 Passing 5 GPIOs to payload:
9426 13:30:54.373815 NAME | PORT | POLARITY | VALUE
9427 13:30:54.380899 EC in RW | 0x000000aa | low | undefined
9428 13:30:54.383955 EC interrupt | 0x00000005 | low | undefined
9429 13:30:54.390765 TPM interrupt | 0x000000ab | high | undefined
9430 13:30:54.393940 SD card detect | 0x00000011 | high | undefined
9431 13:30:54.396966 speaker enable | 0x00000093 | high | undefined
9432 13:30:54.400324 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9433 13:30:54.404116 in-header: 03 f9 00 00 02 00 00 00
9434 13:30:54.407233 in-data: 02 00
9435 13:30:54.411045 ADC[4]: Raw value=903325 ID=7
9436 13:30:54.413791 ADC[3]: Raw value=213916 ID=1
9437 13:30:54.413905 RAM Code: 0x71
9438 13:30:54.417213 ADC[6]: Raw value=74630 ID=0
9439 13:30:54.420859 ADC[5]: Raw value=213546 ID=1
9440 13:30:54.420940 SKU Code: 0x1
9441 13:30:54.427613 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 957a
9442 13:30:54.427728 coreboot table: 964 bytes.
9443 13:30:54.430375 IMD ROOT 0. 0xfffff000 0x00001000
9444 13:30:54.433875 IMD SMALL 1. 0xffffe000 0x00001000
9445 13:30:54.437310 RO MCACHE 2. 0xffffc000 0x00001104
9446 13:30:54.440372 CONSOLE 3. 0xfff7c000 0x00080000
9447 13:30:54.443788 FMAP 4. 0xfff7b000 0x00000452
9448 13:30:54.446761 TIME STAMP 5. 0xfff7a000 0x00000910
9449 13:30:54.450320 VBOOT WORK 6. 0xfff66000 0x00014000
9450 13:30:54.453805 RAMOOPS 7. 0xffe66000 0x00100000
9451 13:30:54.456989 COREBOOT 8. 0xffe64000 0x00002000
9452 13:30:54.460106 IMD small region:
9453 13:30:54.463730 IMD ROOT 0. 0xffffec00 0x00000400
9454 13:30:54.466711 VPD 1. 0xffffeb80 0x0000006c
9455 13:30:54.469718 MMC STATUS 2. 0xffffeb60 0x00000004
9456 13:30:54.476510 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9457 13:30:54.476595 Probing TPM: done!
9458 13:30:54.483355 Connected to device vid:did:rid of 1ae0:0028:00
9459 13:30:54.489904 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9460 13:30:54.493102 Initialized TPM device CR50 revision 0
9461 13:30:54.496714 Checking cr50 for pending updates
9462 13:30:54.502141 Reading cr50 TPM mode
9463 13:30:54.511146 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9464 13:30:54.517580 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9465 13:30:54.557967 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9466 13:30:54.560875 Checking segment from ROM address 0x40100000
9467 13:30:54.564445 Checking segment from ROM address 0x4010001c
9468 13:30:54.571352 Loading segment from ROM address 0x40100000
9469 13:30:54.571438 code (compression=0)
9470 13:30:54.580994 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9471 13:30:54.587669 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9472 13:30:54.587755 it's not compressed!
9473 13:30:54.594519 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9474 13:30:54.597462 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9475 13:30:54.618231 Loading segment from ROM address 0x4010001c
9476 13:30:54.618319 Entry Point 0x80000000
9477 13:30:54.621708 Loaded segments
9478 13:30:54.624601 BS: BS_PAYLOAD_LOAD run times (exec / console): 49 / 61 ms
9479 13:30:54.630978 Jumping to boot code at 0x80000000(0xffe64000)
9480 13:30:54.637718 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9481 13:30:54.644375 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9482 13:30:54.652530 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9483 13:30:54.655922 Checking segment from ROM address 0x40100000
9484 13:30:54.659375 Checking segment from ROM address 0x4010001c
9485 13:30:54.666132 Loading segment from ROM address 0x40100000
9486 13:30:54.666216 code (compression=1)
9487 13:30:54.672798 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9488 13:30:54.682472 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9489 13:30:54.682561 using LZMA
9490 13:30:54.691096 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9491 13:30:54.697896 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9492 13:30:54.700938 Loading segment from ROM address 0x4010001c
9493 13:30:54.701022 Entry Point 0x54601000
9494 13:30:54.704694 Loaded segments
9495 13:30:54.707621 NOTICE: MT8192 bl31_setup
9496 13:30:54.714907 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9497 13:30:54.717913 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9498 13:30:54.721134 WARNING: region 0:
9499 13:30:54.724490 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9500 13:30:54.724599 WARNING: region 1:
9501 13:30:54.731225 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9502 13:30:54.734616 WARNING: region 2:
9503 13:30:54.737950 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9504 13:30:54.741545 WARNING: region 3:
9505 13:30:54.744664 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9506 13:30:54.747763 WARNING: region 4:
9507 13:30:54.754443 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9508 13:30:54.754554 WARNING: region 5:
9509 13:30:54.757985 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9510 13:30:54.761093 WARNING: region 6:
9511 13:30:54.764582 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9512 13:30:54.767500 WARNING: region 7:
9513 13:30:54.771227 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9514 13:30:54.777643 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9515 13:30:54.781276 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9516 13:30:54.784308 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9517 13:30:54.791168 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9518 13:30:54.794266 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9519 13:30:54.797340 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9520 13:30:54.804074 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9521 13:30:54.807705 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9522 13:30:54.814348 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9523 13:30:54.817503 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9524 13:30:54.820553 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9525 13:30:54.827290 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9526 13:30:54.831050 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9527 13:30:54.834408 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9528 13:30:54.840717 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9529 13:30:54.843939 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9530 13:30:54.850604 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9531 13:30:54.853844 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9532 13:30:54.857373 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9533 13:30:54.864182 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9534 13:30:54.867050 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9535 13:30:54.873681 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9536 13:30:54.877203 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9537 13:30:54.880563 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9538 13:30:54.886971 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9539 13:30:54.890353 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9540 13:30:54.896853 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9541 13:30:54.900485 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9542 13:30:54.903598 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9543 13:30:54.910520 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9544 13:30:54.913465 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9545 13:30:54.920333 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9546 13:30:54.923304 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9547 13:30:54.926932 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9548 13:30:54.930054 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9549 13:30:54.936755 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9550 13:30:54.939751 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9551 13:30:54.943150 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9552 13:30:54.946331 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9553 13:30:54.953391 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9554 13:30:54.956627 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9555 13:30:54.959868 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9556 13:30:54.963235 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9557 13:30:54.969435 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9558 13:30:54.973105 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9559 13:30:54.976309 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9560 13:30:54.983017 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9561 13:30:54.986539 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9562 13:30:54.989933 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9563 13:30:54.996659 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9564 13:30:54.999481 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9565 13:30:55.002826 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9566 13:30:55.009635 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9567 13:30:55.012803 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9568 13:30:55.019560 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9569 13:30:55.022507 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9570 13:30:55.029360 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9571 13:30:55.032949 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9572 13:30:55.039232 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9573 13:30:55.042753 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9574 13:30:55.046337 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9575 13:30:55.052381 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9576 13:30:55.056172 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9577 13:30:55.062633 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9578 13:30:55.066013 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9579 13:30:55.072438 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9580 13:30:55.075536 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9581 13:30:55.082306 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9582 13:30:55.085489 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9583 13:30:55.089129 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9584 13:30:55.095689 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9585 13:30:55.099058 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9586 13:30:55.105729 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9587 13:30:55.108706 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9588 13:30:55.115613 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9589 13:30:55.118988 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9590 13:30:55.122515 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9591 13:30:55.128702 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9592 13:30:55.132401 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9593 13:30:55.138568 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9594 13:30:55.142252 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9595 13:30:55.148365 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9596 13:30:55.151826 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9597 13:30:55.158621 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9598 13:30:55.161783 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9599 13:30:55.165554 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9600 13:30:55.172023 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9601 13:30:55.175027 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9602 13:30:55.181655 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9603 13:30:55.185033 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9604 13:30:55.191668 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9605 13:30:55.195279 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9606 13:30:55.201906 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9607 13:30:55.204904 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9608 13:30:55.208263 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9609 13:30:55.214905 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9610 13:30:55.218630 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9611 13:30:55.221489 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9612 13:30:55.228366 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9613 13:30:55.231316 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9614 13:30:55.235020 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9615 13:30:55.241129 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9616 13:30:55.244833 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9617 13:30:55.247994 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9618 13:30:55.254435 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9619 13:30:55.258233 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9620 13:30:55.264408 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9621 13:30:55.268099 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9622 13:30:55.271204 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9623 13:30:55.277665 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9624 13:30:55.281272 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9625 13:30:55.288090 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9626 13:30:55.291171 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9627 13:30:55.294514 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9628 13:30:55.301083 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9629 13:30:55.304008 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9630 13:30:55.307749 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9631 13:30:55.314356 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9632 13:30:55.317769 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9633 13:30:55.320769 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9634 13:30:55.327313 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9635 13:30:55.331018 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9636 13:30:55.334009 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9637 13:30:55.337480 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9638 13:30:55.344126 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9639 13:30:55.347085 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9640 13:30:55.353895 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9641 13:30:55.357044 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9642 13:30:55.360580 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9643 13:30:55.367417 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9644 13:30:55.370596 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9645 13:30:55.377308 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9646 13:30:55.380270 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9647 13:30:55.383721 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9648 13:30:55.390441 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9649 13:30:55.393553 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9650 13:30:55.400426 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9651 13:30:55.403810 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9652 13:30:55.406572 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9653 13:30:55.413366 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9654 13:30:55.416396 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9655 13:30:55.423592 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9656 13:30:55.426514 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9657 13:30:55.430042 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9658 13:30:55.436740 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9659 13:30:55.439795 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9660 13:30:55.446866 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9661 13:30:55.449934 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9662 13:30:55.453125 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9663 13:30:55.459745 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9664 13:30:55.463160 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9665 13:30:55.466158 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9666 13:30:55.473031 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9667 13:30:55.476168 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9668 13:30:55.482641 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9669 13:30:55.486320 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9670 13:30:55.492987 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9671 13:30:55.496209 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9672 13:30:55.499278 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9673 13:30:55.505940 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9674 13:30:55.509450 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9675 13:30:55.512496 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9676 13:30:55.519545 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9677 13:30:55.522330 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9678 13:30:55.528957 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9679 13:30:55.532430 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9680 13:30:55.535948 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9681 13:30:55.542576 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9682 13:30:55.545748 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9683 13:30:55.552212 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9684 13:30:55.555240 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9685 13:30:55.562015 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9686 13:30:55.565610 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9687 13:30:55.568925 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9688 13:30:55.575008 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9689 13:30:55.578681 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9690 13:30:55.584894 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9691 13:30:55.588405 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9692 13:30:55.591605 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9693 13:30:55.598009 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9694 13:30:55.601089 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9695 13:30:55.607834 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9696 13:30:55.611400 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9697 13:30:55.614975 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9698 13:30:55.621047 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9699 13:30:55.624722 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9700 13:30:55.631029 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9701 13:30:55.634079 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9702 13:30:55.637554 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9703 13:30:55.644266 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9704 13:30:55.647650 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9705 13:30:55.654123 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9706 13:30:55.657523 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9707 13:30:55.664378 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9708 13:30:55.667287 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9709 13:30:55.670512 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9710 13:30:55.676965 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9711 13:30:55.680778 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9712 13:30:55.686888 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9713 13:30:55.690463 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9714 13:30:55.693624 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9715 13:30:55.700144 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9716 13:30:55.703741 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9717 13:30:55.710206 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9718 13:30:55.713703 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9719 13:30:55.719786 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9720 13:30:55.723384 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9721 13:30:55.729939 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9722 13:30:55.732993 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9723 13:30:55.736412 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9724 13:30:55.743037 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9725 13:30:55.746217 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9726 13:30:55.752668 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9727 13:30:55.756433 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9728 13:30:55.762637 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9729 13:30:55.765958 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9730 13:30:55.769342 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9731 13:30:55.776029 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9732 13:30:55.779179 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9733 13:30:55.785946 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9734 13:30:55.789015 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9735 13:30:55.795594 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9736 13:30:55.799311 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9737 13:30:55.802396 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9738 13:30:55.808958 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9739 13:30:55.812013 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9740 13:30:55.818751 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9741 13:30:55.821724 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9742 13:30:55.828572 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9743 13:30:55.831556 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9744 13:30:55.835331 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9745 13:30:55.838331 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9746 13:30:55.841316 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9747 13:30:55.847996 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9748 13:30:55.851137 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9749 13:30:55.858014 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9750 13:30:55.861025 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9751 13:30:55.864442 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9752 13:30:55.871348 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9753 13:30:55.874127 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9754 13:30:55.877492 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9755 13:30:55.884198 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9756 13:30:55.887340 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9757 13:30:55.894209 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9758 13:30:55.897306 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9759 13:30:55.900866 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9760 13:30:55.907672 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9761 13:30:55.910543 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9762 13:30:55.913679 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9763 13:30:55.920469 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9764 13:30:55.924012 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9765 13:30:55.930050 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9766 13:30:55.933770 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9767 13:30:55.936854 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9768 13:30:55.943601 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9769 13:30:55.947266 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9770 13:30:55.953584 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9771 13:30:55.956491 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9772 13:30:55.960197 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9773 13:30:55.966258 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9774 13:30:55.969796 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9775 13:30:55.972801 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9776 13:30:55.979520 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9777 13:30:55.983090 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9778 13:30:55.989212 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9779 13:30:55.992534 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9780 13:30:55.996268 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9781 13:30:56.002349 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9782 13:30:56.005580 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9783 13:30:56.009329 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9784 13:30:56.012151 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9785 13:30:56.019219 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9786 13:30:56.022267 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9787 13:30:56.025458 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9788 13:30:56.029023 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9789 13:30:56.035180 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9790 13:30:56.038860 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9791 13:30:56.041926 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9792 13:30:56.045610 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9793 13:30:56.051711 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9794 13:30:56.055199 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9795 13:30:56.058397 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9796 13:30:56.065400 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9797 13:30:56.068497 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9798 13:30:56.075008 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9799 13:30:56.077993 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9800 13:30:56.084794 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9801 13:30:56.088278 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9802 13:30:56.091343 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9803 13:30:56.098087 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9804 13:30:56.101096 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9805 13:30:56.107663 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9806 13:30:56.111187 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9807 13:30:56.114631 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9808 13:30:56.120855 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9809 13:30:56.124166 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9810 13:30:56.130636 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9811 13:30:56.134089 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9812 13:30:56.140458 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9813 13:30:56.144136 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9814 13:30:56.147245 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9815 13:30:56.154013 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9816 13:30:56.157103 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9817 13:30:56.163685 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9818 13:30:56.166760 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9819 13:30:56.169992 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9820 13:30:56.176611 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9821 13:30:56.180220 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9822 13:30:56.186874 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9823 13:30:56.189987 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9824 13:30:56.196599 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9825 13:30:56.199621 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9826 13:30:56.206390 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9827 13:30:56.209440 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9828 13:30:56.212990 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9829 13:30:56.219582 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9830 13:30:56.222972 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9831 13:30:56.229299 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9832 13:30:56.232856 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9833 13:30:56.236043 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9834 13:30:56.242588 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9835 13:30:56.245838 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9836 13:30:56.252575 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9837 13:30:56.256132 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9838 13:30:56.262367 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9839 13:30:56.265430 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9840 13:30:56.269104 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9841 13:30:56.275783 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9842 13:30:56.278572 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9843 13:30:56.285467 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9844 13:30:56.288967 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9845 13:30:56.292064 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9846 13:30:56.298750 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9847 13:30:56.302125 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9848 13:30:56.308453 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9849 13:30:56.311584 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9850 13:30:56.318115 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9851 13:30:56.321917 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9852 13:30:56.324928 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9853 13:30:56.331554 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9854 13:30:56.335175 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9855 13:30:56.341433 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9856 13:30:56.344992 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9857 13:30:56.351102 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9858 13:30:56.354269 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9859 13:30:56.357785 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9860 13:30:56.364359 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9861 13:30:56.367573 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9862 13:30:56.374384 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9863 13:30:56.377383 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9864 13:30:56.384004 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9865 13:30:56.387433 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9866 13:30:56.390877 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9867 13:30:56.397311 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9868 13:30:56.400409 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9869 13:30:56.406960 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9870 13:30:56.410589 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9871 13:30:56.416677 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9872 13:30:56.420247 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9873 13:30:56.423889 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9874 13:30:56.429975 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9875 13:30:56.433418 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9876 13:30:56.440338 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9877 13:30:56.443313 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9878 13:30:56.450140 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9879 13:30:56.453290 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9880 13:30:56.459750 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9881 13:30:56.462950 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9882 13:30:56.469734 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9883 13:30:56.472851 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9884 13:30:56.475891 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9885 13:30:56.482530 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9886 13:30:56.486273 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9887 13:30:56.492664 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9888 13:30:56.495702 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9889 13:30:56.502578 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9890 13:30:56.505507 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9891 13:30:56.509297 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9892 13:30:56.515704 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9893 13:30:56.518720 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9894 13:30:56.525347 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9895 13:30:56.528903 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9896 13:30:56.535751 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9897 13:30:56.538759 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9898 13:30:56.545671 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9899 13:30:56.548680 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9900 13:30:56.551740 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9901 13:30:56.558513 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9902 13:30:56.561576 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9903 13:30:56.568263 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9904 13:30:56.571219 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9905 13:30:56.578319 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9906 13:30:56.581512 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9907 13:30:56.587637 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9908 13:30:56.591117 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9909 13:30:56.597789 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9910 13:30:56.600900 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9911 13:30:56.604333 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9912 13:30:56.611097 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9913 13:30:56.614177 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9914 13:30:56.620875 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9915 13:30:56.624349 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9916 13:30:56.630498 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9917 13:30:56.633828 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9918 13:30:56.637530 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9919 13:30:56.644078 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9920 13:30:56.647179 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9921 13:30:56.653949 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9922 13:30:56.657050 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9923 13:30:56.663700 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9924 13:30:56.666757 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9925 13:30:56.673444 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9926 13:30:56.676989 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9927 13:30:56.683226 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9928 13:30:56.686860 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9929 13:30:56.693280 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9930 13:30:56.696729 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9931 13:30:56.703013 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9932 13:30:56.706440 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9933 13:30:56.712940 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9934 13:30:56.716316 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9935 13:30:56.722872 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9936 13:30:56.726441 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9937 13:30:56.733172 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9938 13:30:56.736036 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9939 13:30:56.742818 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9940 13:30:56.746467 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9941 13:30:56.752548 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9942 13:30:56.755627 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9943 13:30:56.762534 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9944 13:30:56.765653 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9945 13:30:56.772444 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9946 13:30:56.776110 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9947 13:30:56.782383 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9948 13:30:56.785737 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9949 13:30:56.788892 INFO: [APUAPC] vio 0
9950 13:30:56.792042 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9951 13:30:56.798797 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9952 13:30:56.801831 INFO: [APUAPC] D0_APC_0: 0x400510
9953 13:30:56.805540 INFO: [APUAPC] D0_APC_1: 0x0
9954 13:30:56.808990 INFO: [APUAPC] D0_APC_2: 0x1540
9955 13:30:56.809072 INFO: [APUAPC] D0_APC_3: 0x0
9956 13:30:56.815121 INFO: [APUAPC] D1_APC_0: 0xffffffff
9957 13:30:56.818759 INFO: [APUAPC] D1_APC_1: 0xffffffff
9958 13:30:56.821632 INFO: [APUAPC] D1_APC_2: 0x3fffff
9959 13:30:56.821727 INFO: [APUAPC] D1_APC_3: 0x0
9960 13:30:56.825029 INFO: [APUAPC] D2_APC_0: 0xffffffff
9961 13:30:56.831460 INFO: [APUAPC] D2_APC_1: 0xffffffff
9962 13:30:56.834621 INFO: [APUAPC] D2_APC_2: 0x3fffff
9963 13:30:56.834705 INFO: [APUAPC] D2_APC_3: 0x0
9964 13:30:56.838246 INFO: [APUAPC] D3_APC_0: 0xffffffff
9965 13:30:56.844983 INFO: [APUAPC] D3_APC_1: 0xffffffff
9966 13:30:56.845084 INFO: [APUAPC] D3_APC_2: 0x3fffff
9967 13:30:56.847866 INFO: [APUAPC] D3_APC_3: 0x0
9968 13:30:56.851216 INFO: [APUAPC] D4_APC_0: 0xffffffff
9969 13:30:56.854622 INFO: [APUAPC] D4_APC_1: 0xffffffff
9970 13:30:56.858290 INFO: [APUAPC] D4_APC_2: 0x3fffff
9971 13:30:56.861175 INFO: [APUAPC] D4_APC_3: 0x0
9972 13:30:56.864273 INFO: [APUAPC] D5_APC_0: 0xffffffff
9973 13:30:56.867885 INFO: [APUAPC] D5_APC_1: 0xffffffff
9974 13:30:56.871003 INFO: [APUAPC] D5_APC_2: 0x3fffff
9975 13:30:56.874075 INFO: [APUAPC] D5_APC_3: 0x0
9976 13:30:56.877818 INFO: [APUAPC] D6_APC_0: 0xffffffff
9977 13:30:56.880939 INFO: [APUAPC] D6_APC_1: 0xffffffff
9978 13:30:56.884068 INFO: [APUAPC] D6_APC_2: 0x3fffff
9979 13:30:56.887417 INFO: [APUAPC] D6_APC_3: 0x0
9980 13:30:56.890845 INFO: [APUAPC] D7_APC_0: 0xffffffff
9981 13:30:56.894212 INFO: [APUAPC] D7_APC_1: 0xffffffff
9982 13:30:56.897268 INFO: [APUAPC] D7_APC_2: 0x3fffff
9983 13:30:56.900904 INFO: [APUAPC] D7_APC_3: 0x0
9984 13:30:56.903894 INFO: [APUAPC] D8_APC_0: 0xffffffff
9985 13:30:56.906967 INFO: [APUAPC] D8_APC_1: 0xffffffff
9986 13:30:56.910603 INFO: [APUAPC] D8_APC_2: 0x3fffff
9987 13:30:56.914154 INFO: [APUAPC] D8_APC_3: 0x0
9988 13:30:56.917315 INFO: [APUAPC] D9_APC_0: 0xffffffff
9989 13:30:56.920433 INFO: [APUAPC] D9_APC_1: 0xffffffff
9990 13:30:56.923575 INFO: [APUAPC] D9_APC_2: 0x3fffff
9991 13:30:56.927056 INFO: [APUAPC] D9_APC_3: 0x0
9992 13:30:56.930036 INFO: [APUAPC] D10_APC_0: 0xffffffff
9993 13:30:56.933654 INFO: [APUAPC] D10_APC_1: 0xffffffff
9994 13:30:56.936973 INFO: [APUAPC] D10_APC_2: 0x3fffff
9995 13:30:56.939957 INFO: [APUAPC] D10_APC_3: 0x0
9996 13:30:56.943664 INFO: [APUAPC] D11_APC_0: 0xffffffff
9997 13:30:56.946693 INFO: [APUAPC] D11_APC_1: 0xffffffff
9998 13:30:56.949740 INFO: [APUAPC] D11_APC_2: 0x3fffff
9999 13:30:56.953375 INFO: [APUAPC] D11_APC_3: 0x0
10000 13:30:56.956998 INFO: [APUAPC] D12_APC_0: 0xffffffff
10001 13:30:56.960029 INFO: [APUAPC] D12_APC_1: 0xffffffff
10002 13:30:56.963689 INFO: [APUAPC] D12_APC_2: 0x3fffff
10003 13:30:56.966780 INFO: [APUAPC] D12_APC_3: 0x0
10004 13:30:56.969826 INFO: [APUAPC] D13_APC_0: 0xffffffff
10005 13:30:56.973543 INFO: [APUAPC] D13_APC_1: 0xffffffff
10006 13:30:56.976736 INFO: [APUAPC] D13_APC_2: 0x3fffff
10007 13:30:56.979697 INFO: [APUAPC] D13_APC_3: 0x0
10008 13:30:56.982753 INFO: [APUAPC] D14_APC_0: 0xffffffff
10009 13:30:56.989644 INFO: [APUAPC] D14_APC_1: 0xffffffff
10010 13:30:56.992722 INFO: [APUAPC] D14_APC_2: 0x3fffff
10011 13:30:56.993477 INFO: [APUAPC] D14_APC_3: 0x0
10012 13:30:56.996172 INFO: [APUAPC] D15_APC_0: 0xffffffff
10013 13:30:57.002626 INFO: [APUAPC] D15_APC_1: 0xffffffff
10014 13:30:57.006157 INFO: [APUAPC] D15_APC_2: 0x3fffff
10015 13:30:57.006394 INFO: [APUAPC] D15_APC_3: 0x0
10016 13:30:57.009104 INFO: [APUAPC] APC_CON: 0x4
10017 13:30:57.012702 INFO: [NOCDAPC] D0_APC_0: 0x0
10018 13:30:57.015797 INFO: [NOCDAPC] D0_APC_1: 0x0
10019 13:30:57.018817 INFO: [NOCDAPC] D1_APC_0: 0x0
10020 13:30:57.022542 INFO: [NOCDAPC] D1_APC_1: 0xfff
10021 13:30:57.025490 INFO: [NOCDAPC] D2_APC_0: 0x0
10022 13:30:57.028959 INFO: [NOCDAPC] D2_APC_1: 0xfff
10023 13:30:57.032222 INFO: [NOCDAPC] D3_APC_0: 0x0
10024 13:30:57.035632 INFO: [NOCDAPC] D3_APC_1: 0xfff
10025 13:30:57.035944 INFO: [NOCDAPC] D4_APC_0: 0x0
10026 13:30:57.038716 INFO: [NOCDAPC] D4_APC_1: 0xfff
10027 13:30:57.042148 INFO: [NOCDAPC] D5_APC_0: 0x0
10028 13:30:57.045486 INFO: [NOCDAPC] D5_APC_1: 0xfff
10029 13:30:57.048621 INFO: [NOCDAPC] D6_APC_0: 0x0
10030 13:30:57.051701 INFO: [NOCDAPC] D6_APC_1: 0xfff
10031 13:30:57.055460 INFO: [NOCDAPC] D7_APC_0: 0x0
10032 13:30:57.058466 INFO: [NOCDAPC] D7_APC_1: 0xfff
10033 13:30:57.062225 INFO: [NOCDAPC] D8_APC_0: 0x0
10034 13:30:57.065190 INFO: [NOCDAPC] D8_APC_1: 0xfff
10035 13:30:57.068777 INFO: [NOCDAPC] D9_APC_0: 0x0
10036 13:30:57.072294 INFO: [NOCDAPC] D9_APC_1: 0xfff
10037 13:30:57.072621 INFO: [NOCDAPC] D10_APC_0: 0x0
10038 13:30:57.075190 INFO: [NOCDAPC] D10_APC_1: 0xfff
10039 13:30:57.078912 INFO: [NOCDAPC] D11_APC_0: 0x0
10040 13:30:57.081859 INFO: [NOCDAPC] D11_APC_1: 0xfff
10041 13:30:57.084951 INFO: [NOCDAPC] D12_APC_0: 0x0
10042 13:30:57.088779 INFO: [NOCDAPC] D12_APC_1: 0xfff
10043 13:30:57.091824 INFO: [NOCDAPC] D13_APC_0: 0x0
10044 13:30:57.095009 INFO: [NOCDAPC] D13_APC_1: 0xfff
10045 13:30:57.098071 INFO: [NOCDAPC] D14_APC_0: 0x0
10046 13:30:57.101633 INFO: [NOCDAPC] D14_APC_1: 0xfff
10047 13:30:57.104687 INFO: [NOCDAPC] D15_APC_0: 0x0
10048 13:30:57.108229 INFO: [NOCDAPC] D15_APC_1: 0xfff
10049 13:30:57.111604 INFO: [NOCDAPC] APC_CON: 0x4
10050 13:30:57.114695 INFO: [APUAPC] set_apusys_apc done
10051 13:30:57.117956 INFO: [DEVAPC] devapc_init done
10052 13:30:57.121387 INFO: GICv3 without legacy support detected.
10053 13:30:57.124838 INFO: ARM GICv3 driver initialized in EL3
10054 13:30:57.127835 INFO: Maximum SPI INTID supported: 639
10055 13:30:57.131664 INFO: BL31: Initializing runtime services
10056 13:30:57.137567 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10057 13:30:57.141042 INFO: SPM: enable CPC mode
10058 13:30:57.147768 INFO: mcdi ready for mcusys-off-idle and system suspend
10059 13:30:57.151135 INFO: BL31: Preparing for EL3 exit to normal world
10060 13:30:57.154558 INFO: Entry point address = 0x80000000
10061 13:30:57.157555 INFO: SPSR = 0x8
10062 13:30:57.162659
10063 13:30:57.162912
10064 13:30:57.163134
10065 13:30:57.165623 Starting depthcharge on Spherion...
10066 13:30:57.165847
10067 13:30:57.166024 Wipe memory regions:
10068 13:30:57.166189
10069 13:30:57.167591 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10070 13:30:57.167893 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10071 13:30:57.168733 Setting prompt string to ['asurada:']
10072 13:30:57.168968 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10073 13:30:57.169333 [0x00000040000000, 0x00000054600000)
10074 13:30:57.291786
10075 13:30:57.292330 [0x00000054660000, 0x00000080000000)
10076 13:30:57.552341
10077 13:30:57.552807 [0x000000821a7280, 0x000000ffe64000)
10078 13:30:58.296313
10079 13:30:58.296474 [0x00000100000000, 0x00000240000000)
10080 13:31:00.186456
10081 13:31:00.189794 Initializing XHCI USB controller at 0x11200000.
10082 13:31:01.227738
10083 13:31:01.230812 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10084 13:31:01.231057
10085 13:31:01.231212
10086 13:31:01.231353
10087 13:31:01.231787 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10089 13:31:01.332365 asurada: tftpboot 192.168.201.1 11471176/tftp-deploy-5nyrh5z2/kernel/image.itb 11471176/tftp-deploy-5nyrh5z2/kernel/cmdline
10090 13:31:01.332715 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10091 13:31:01.332945 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10092 13:31:01.337526 tftpboot 192.168.201.1 11471176/tftp-deploy-5nyrh5z2/kernel/image.ittp-deploy-5nyrh5z2/kernel/cmdline
10093 13:31:01.337780
10094 13:31:01.337966 Waiting for link
10095 13:31:01.497927
10096 13:31:01.498070 R8152: Initializing
10097 13:31:01.498142
10098 13:31:01.500892 Version 6 (ocp_data = 5c30)
10099 13:31:01.500966
10100 13:31:01.504514 R8152: Done initializing
10101 13:31:01.504599
10102 13:31:01.504665 Adding net device
10103 13:31:03.547631
10104 13:31:03.547763 done.
10105 13:31:03.547834
10106 13:31:03.547896 MAC: 00:24:32:30:7c:7b
10107 13:31:03.548021
10108 13:31:03.550543 Sending DHCP discover... done.
10109 13:31:03.550628
10110 13:31:03.554297 Waiting for reply... done.
10111 13:31:03.554406
10112 13:31:03.556924 Sending DHCP request... done.
10113 13:31:03.557002
10114 13:31:03.561901 Waiting for reply... done.
10115 13:31:03.561980
10116 13:31:03.562046 My ip is 192.168.201.14
10117 13:31:03.562106
10118 13:31:03.565280 The DHCP server ip is 192.168.201.1
10119 13:31:03.565368
10120 13:31:03.571985 TFTP server IP predefined by user: 192.168.201.1
10121 13:31:03.572098
10122 13:31:03.578496 Bootfile predefined by user: 11471176/tftp-deploy-5nyrh5z2/kernel/image.itb
10123 13:31:03.578585
10124 13:31:03.581587 Sending tftp read request... done.
10125 13:31:03.581673
10126 13:31:03.585772 Waiting for the transfer...
10127 13:31:03.585857
10128 13:31:04.129603 00000000 ################################################################
10129 13:31:04.129754
10130 13:31:04.664329 00080000 ################################################################
10131 13:31:04.664505
10132 13:31:05.202016 00100000 ################################################################
10133 13:31:05.202185
10134 13:31:05.735233 00180000 ################################################################
10135 13:31:05.735387
10136 13:31:06.275017 00200000 ################################################################
10137 13:31:06.275195
10138 13:31:06.812869 00280000 ################################################################
10139 13:31:06.813025
10140 13:31:07.355067 00300000 ################################################################
10141 13:31:07.355232
10142 13:31:07.893754 00380000 ################################################################
10143 13:31:07.893915
10144 13:31:08.418781 00400000 ################################################################
10145 13:31:08.418939
10146 13:31:08.957061 00480000 ################################################################
10147 13:31:08.957233
10148 13:31:09.496059 00500000 ################################################################
10149 13:31:09.496195
10150 13:31:10.038620 00580000 ################################################################
10151 13:31:10.038769
10152 13:31:10.589234 00600000 ################################################################
10153 13:31:10.589384
10154 13:31:11.138217 00680000 ################################################################
10155 13:31:11.138357
10156 13:31:11.665939 00700000 ################################################################
10157 13:31:11.666092
10158 13:31:12.212551 00780000 ################################################################
10159 13:31:12.212706
10160 13:31:12.756472 00800000 ################################################################
10161 13:31:12.756620
10162 13:31:13.290604 00880000 ################################################################
10163 13:31:13.290757
10164 13:31:13.821607 00900000 ################################################################
10165 13:31:13.821777
10166 13:31:14.367661 00980000 ################################################################
10167 13:31:14.367868
10168 13:31:14.904656 00a00000 ################################################################
10169 13:31:14.904796
10170 13:31:15.449583 00a80000 ################################################################
10171 13:31:15.449745
10172 13:31:15.978420 00b00000 ################################################################
10173 13:31:15.978617
10174 13:31:16.524666 00b80000 ################################################################
10175 13:31:16.524816
10176 13:31:17.055894 00c00000 ################################################################
10177 13:31:17.056076
10178 13:31:17.578004 00c80000 ################################################################
10179 13:31:17.578143
10180 13:31:18.111470 00d00000 ################################################################
10181 13:31:18.111617
10182 13:31:18.662737 00d80000 ################################################################
10183 13:31:18.662886
10184 13:31:19.204541 00e00000 ################################################################
10185 13:31:19.204682
10186 13:31:19.738230 00e80000 ################################################################
10187 13:31:19.738384
10188 13:31:20.280431 00f00000 ################################################################
10189 13:31:20.280584
10190 13:31:20.842941 00f80000 ################################################################
10191 13:31:20.843185
10192 13:31:21.410250 01000000 ################################################################
10193 13:31:21.411017
10194 13:31:21.989411 01080000 ################################################################
10195 13:31:21.989551
10196 13:31:22.559826 01100000 ################################################################
10197 13:31:22.560002
10198 13:31:23.112623 01180000 ################################################################
10199 13:31:23.112764
10200 13:31:23.671375 01200000 ################################################################
10201 13:31:23.671536
10202 13:31:24.219897 01280000 ################################################################
10203 13:31:24.220044
10204 13:31:24.773929 01300000 ################################################################
10205 13:31:24.774069
10206 13:31:25.311628 01380000 ################################################################
10207 13:31:25.311775
10208 13:31:25.842584 01400000 ################################################################
10209 13:31:25.842724
10210 13:31:26.368702 01480000 ################################################################
10211 13:31:26.368843
10212 13:31:26.899684 01500000 ################################################################
10213 13:31:26.899863
10214 13:31:27.456128 01580000 ################################################################
10215 13:31:27.456280
10216 13:31:28.043951 01600000 ################################################################
10217 13:31:28.044503
10218 13:31:28.648095 01680000 ################################################################
10219 13:31:28.648241
10220 13:31:29.291359 01700000 ################################################################
10221 13:31:29.291518
10222 13:31:29.879065 01780000 ################################################################
10223 13:31:29.879250
10224 13:31:30.413387 01800000 ################################################################
10225 13:31:30.413544
10226 13:31:30.933568 01880000 ################################################################
10227 13:31:30.933719
10228 13:31:31.459259 01900000 ################################################################
10229 13:31:31.459409
10230 13:31:31.998608 01980000 ################################################################
10231 13:31:31.998799
10232 13:31:32.524447 01a00000 ################################################################
10233 13:31:32.524591
10234 13:31:33.063896 01a80000 ################################################################
10235 13:31:33.064091
10236 13:31:33.610945 01b00000 ################################################################
10237 13:31:33.611089
10238 13:31:33.636821 01b80000 #### done.
10239 13:31:33.636910
10240 13:31:33.639861 The bootfile was 28861894 bytes long.
10241 13:31:33.639969
10242 13:31:33.643434 Sending tftp read request... done.
10243 13:31:33.643517
10244 13:31:33.646772 Waiting for the transfer...
10245 13:31:33.646855
10246 13:31:33.646921 00000000 # done.
10247 13:31:33.646983
10248 13:31:33.656728 Command line loaded dynamically from TFTP file: 11471176/tftp-deploy-5nyrh5z2/kernel/cmdline
10249 13:31:33.656827
10250 13:31:33.676478 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11471176/extract-nfsrootfs-tmw6wty7,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10251 13:31:33.676918
10252 13:31:33.679979 Loading FIT.
10253 13:31:33.680400
10254 13:31:33.683412 Image ramdisk-1 has 17772488 bytes.
10255 13:31:33.683834
10256 13:31:33.684227 Image fdt-1 has 47278 bytes.
10257 13:31:33.684546
10258 13:31:33.686317 Image kernel-1 has 11040095 bytes.
10259 13:31:33.686742
10260 13:31:33.696474 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10261 13:31:33.696898
10262 13:31:33.712785 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10263 13:31:33.713241
10264 13:31:33.719250 Choosing best match conf-1 for compat google,spherion-rev2.
10265 13:31:33.723344
10266 13:31:33.727980 Connected to device vid:did:rid of 1ae0:0028:00
10267 13:31:33.735348
10268 13:31:33.738142 tpm_get_response: command 0x17b, return code 0x0
10269 13:31:33.738605
10270 13:31:33.741742 ec_init: CrosEC protocol v3 supported (256, 248)
10271 13:31:33.745964
10272 13:31:33.748726 tpm_cleanup: add release locality here.
10273 13:31:33.749203
10274 13:31:33.749542 Shutting down all USB controllers.
10275 13:31:33.752203
10276 13:31:33.752729 Removing current net device
10277 13:31:33.753095
10278 13:31:33.759038 Exiting depthcharge with code 4 at timestamp: 65902412
10279 13:31:33.759497
10280 13:31:33.762415 LZMA decompressing kernel-1 to 0x821a6718
10281 13:31:33.763018
10282 13:31:33.765398 LZMA decompressing kernel-1 to 0x40000000
10283 13:31:35.153455
10284 13:31:35.154076 jumping to kernel
10285 13:31:35.155570 end: 2.2.4 bootloader-commands (duration 00:00:38) [common]
10286 13:31:35.156266 start: 2.2.5 auto-login-action (timeout 00:03:47) [common]
10287 13:31:35.156711 Setting prompt string to ['Linux version [0-9]']
10288 13:31:35.157236 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10289 13:31:35.157811 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10290 13:31:35.234917
10291 13:31:35.238290 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10292 13:31:35.242142 start: 2.2.5.1 login-action (timeout 00:03:47) [common]
10293 13:31:35.242591 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10294 13:31:35.242945 Setting prompt string to []
10295 13:31:35.243320 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10296 13:31:35.243756 Using line separator: #'\n'#
10297 13:31:35.244220 No login prompt set.
10298 13:31:35.244663 Parsing kernel messages
10299 13:31:35.245040 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10300 13:31:35.245660 [login-action] Waiting for messages, (timeout 00:03:47)
10301 13:31:35.261515 [ 0.000000] Linux version 6.1.52-cip5 (KernelCI@build-j38933-arm64-gcc-10-defconfig-arm64-chromebook-kgx6p) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Sep 8 13:10:51 UTC 2023
10302 13:31:35.264539 [ 0.000000] random: crng init done
10303 13:31:35.271090 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10304 13:31:35.274493 [ 0.000000] efi: UEFI not found.
10305 13:31:35.280835 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10306 13:31:35.290735 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10307 13:31:35.297377 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10308 13:31:35.307172 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10309 13:31:35.314250 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10310 13:31:35.320513 [ 0.000000] printk: bootconsole [mtk8250] enabled
10311 13:31:35.326965 [ 0.000000] NUMA: No NUMA configuration found
10312 13:31:35.333528 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10313 13:31:35.340015 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10314 13:31:35.340574 [ 0.000000] Zone ranges:
10315 13:31:35.346631 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10316 13:31:35.350249 [ 0.000000] DMA32 empty
10317 13:31:35.356476 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10318 13:31:35.359823 [ 0.000000] Movable zone start for each node
10319 13:31:35.363122 [ 0.000000] Early memory node ranges
10320 13:31:35.369812 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10321 13:31:35.376400 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10322 13:31:35.382750 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10323 13:31:35.389826 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10324 13:31:35.396998 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10325 13:31:35.402642 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10326 13:31:35.459243 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10327 13:31:35.465768 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10328 13:31:35.472171 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10329 13:31:35.475667 [ 0.000000] psci: probing for conduit method from DT.
10330 13:31:35.482043 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10331 13:31:35.485049 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10332 13:31:35.491580 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10333 13:31:35.495212 [ 0.000000] psci: SMC Calling Convention v1.2
10334 13:31:35.501546 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10335 13:31:35.505140 [ 0.000000] Detected VIPT I-cache on CPU0
10336 13:31:35.512067 [ 0.000000] CPU features: detected: GIC system register CPU interface
10337 13:31:35.518002 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10338 13:31:35.525484 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10339 13:31:35.531634 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10340 13:31:35.541256 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10341 13:31:35.548368 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10342 13:31:35.551332 [ 0.000000] alternatives: applying boot alternatives
10343 13:31:35.558012 [ 0.000000] Fallback order for Node 0: 0
10344 13:31:35.564731 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10345 13:31:35.568354 [ 0.000000] Policy zone: Normal
10346 13:31:35.591015 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11471176/extract-nfsrootfs-tmw6wty7,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10347 13:31:35.601312 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10348 13:31:35.612450 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10349 13:31:35.621915 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10350 13:31:35.629154 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10351 13:31:35.632249 <6>[ 0.000000] software IO TLB: area num 8.
10352 13:31:35.689861 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10353 13:31:35.838513 <6>[ 0.000000] Memory: 7952132K/8385536K available (17984K kernel code, 4098K rwdata, 17468K rodata, 8384K init, 616K bss, 400636K reserved, 32768K cma-reserved)
10354 13:31:35.845108 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10355 13:31:35.851585 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10356 13:31:35.855236 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10357 13:31:35.861542 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10358 13:31:35.868193 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10359 13:31:35.871641 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10360 13:31:35.881794 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10361 13:31:35.888324 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10362 13:31:35.894608 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10363 13:31:35.901193 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10364 13:31:35.904688 <6>[ 0.000000] GICv3: 608 SPIs implemented
10365 13:31:35.908266 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10366 13:31:35.914885 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10367 13:31:35.917674 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10368 13:31:35.924436 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10369 13:31:35.937431 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10370 13:31:35.950499 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10371 13:31:35.957120 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10372 13:31:35.965344 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10373 13:31:35.978637 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10374 13:31:35.984844 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10375 13:31:35.991962 <6>[ 0.009182] Console: colour dummy device 80x25
10376 13:31:36.001922 <6>[ 0.013907] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10377 13:31:36.008397 <6>[ 0.024349] pid_max: default: 32768 minimum: 301
10378 13:31:36.011966 <6>[ 0.029220] LSM: Security Framework initializing
10379 13:31:36.018597 <6>[ 0.034159] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10380 13:31:36.028482 <6>[ 0.042018] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10381 13:31:36.038224 <6>[ 0.051429] cblist_init_generic: Setting adjustable number of callback queues.
10382 13:31:36.041676 <6>[ 0.058872] cblist_init_generic: Setting shift to 3 and lim to 1.
10383 13:31:36.051609 <6>[ 0.065211] cblist_init_generic: Setting adjustable number of callback queues.
10384 13:31:36.058339 <6>[ 0.072683] cblist_init_generic: Setting shift to 3 and lim to 1.
10385 13:31:36.061298 <6>[ 0.079122] rcu: Hierarchical SRCU implementation.
10386 13:31:36.068131 <6>[ 0.084137] rcu: Max phase no-delay instances is 1000.
10387 13:31:36.074488 <6>[ 0.091205] EFI services will not be available.
10388 13:31:36.078087 <6>[ 0.096159] smp: Bringing up secondary CPUs ...
10389 13:31:36.086322 <6>[ 0.101238] Detected VIPT I-cache on CPU1
10390 13:31:36.093063 <6>[ 0.101309] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10391 13:31:36.099434 <6>[ 0.101341] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10392 13:31:36.102681 <6>[ 0.101673] Detected VIPT I-cache on CPU2
10393 13:31:36.112867 <6>[ 0.101721] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10394 13:31:36.119329 <6>[ 0.101736] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10395 13:31:36.122492 <6>[ 0.101992] Detected VIPT I-cache on CPU3
10396 13:31:36.129221 <6>[ 0.102037] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10397 13:31:36.135851 <6>[ 0.102050] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10398 13:31:36.142510 <6>[ 0.102352] CPU features: detected: Spectre-v4
10399 13:31:36.145991 <6>[ 0.102358] CPU features: detected: Spectre-BHB
10400 13:31:36.148959 <6>[ 0.102363] Detected PIPT I-cache on CPU4
10401 13:31:36.155428 <6>[ 0.102420] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10402 13:31:36.165345 <6>[ 0.102436] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10403 13:31:36.168541 <6>[ 0.102727] Detected PIPT I-cache on CPU5
10404 13:31:36.175168 <6>[ 0.102789] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10405 13:31:36.181552 <6>[ 0.102805] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10406 13:31:36.185137 <6>[ 0.103090] Detected PIPT I-cache on CPU6
10407 13:31:36.194908 <6>[ 0.103155] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10408 13:31:36.201618 <6>[ 0.103171] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10409 13:31:36.204539 <6>[ 0.103470] Detected PIPT I-cache on CPU7
10410 13:31:36.211231 <6>[ 0.103535] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10411 13:31:36.217779 <6>[ 0.103552] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10412 13:31:36.220969 <6>[ 0.103600] smp: Brought up 1 node, 8 CPUs
10413 13:31:36.227663 <6>[ 0.245016] SMP: Total of 8 processors activated.
10414 13:31:36.234180 <6>[ 0.249937] CPU features: detected: 32-bit EL0 Support
10415 13:31:36.240762 <6>[ 0.255299] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10416 13:31:36.247051 <6>[ 0.264099] CPU features: detected: Common not Private translations
10417 13:31:36.254162 <6>[ 0.270574] CPU features: detected: CRC32 instructions
10418 13:31:36.260670 <6>[ 0.275926] CPU features: detected: RCpc load-acquire (LDAPR)
10419 13:31:36.264145 <6>[ 0.281923] CPU features: detected: LSE atomic instructions
10420 13:31:36.270630 <6>[ 0.287704] CPU features: detected: Privileged Access Never
10421 13:31:36.277180 <6>[ 0.293519] CPU features: detected: RAS Extension Support
10422 13:31:36.283621 <6>[ 0.299128] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10423 13:31:36.287290 <6>[ 0.306348] CPU: All CPU(s) started at EL2
10424 13:31:36.293707 <6>[ 0.310692] alternatives: applying system-wide alternatives
10425 13:31:36.303676 <6>[ 0.321400] devtmpfs: initialized
10426 13:31:36.319374 <6>[ 0.330239] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10427 13:31:36.325723 <6>[ 0.340204] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10428 13:31:36.332165 <6>[ 0.348234] pinctrl core: initialized pinctrl subsystem
10429 13:31:36.335552 <6>[ 0.354863] DMI not present or invalid.
10430 13:31:36.342107 <6>[ 0.359274] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10431 13:31:36.352134 <6>[ 0.366132] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10432 13:31:36.358782 <6>[ 0.373720] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10433 13:31:36.368696 <6>[ 0.381935] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10434 13:31:36.371661 <6>[ 0.390177] audit: initializing netlink subsys (disabled)
10435 13:31:36.381729 <5>[ 0.395869] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10436 13:31:36.388559 <6>[ 0.396563] thermal_sys: Registered thermal governor 'step_wise'
10437 13:31:36.394980 <6>[ 0.403836] thermal_sys: Registered thermal governor 'power_allocator'
10438 13:31:36.398068 <6>[ 0.410093] cpuidle: using governor menu
10439 13:31:36.404919 <6>[ 0.421058] NET: Registered PF_QIPCRTR protocol family
10440 13:31:36.411341 <6>[ 0.426552] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10441 13:31:36.417914 <6>[ 0.433656] ASID allocator initialised with 32768 entries
10442 13:31:36.420835 <6>[ 0.440220] Serial: AMBA PL011 UART driver
10443 13:31:36.431787 <4>[ 0.448942] Trying to register duplicate clock ID: 134
10444 13:31:36.485864 <6>[ 0.506231] KASLR enabled
10445 13:31:36.499562 <6>[ 0.513885] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10446 13:31:36.506431 <6>[ 0.520899] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10447 13:31:36.512944 <6>[ 0.527388] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10448 13:31:36.519305 <6>[ 0.534394] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10449 13:31:36.525626 <6>[ 0.540881] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10450 13:31:36.532628 <6>[ 0.547887] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10451 13:31:36.539197 <6>[ 0.554373] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10452 13:31:36.545792 <6>[ 0.561377] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10453 13:31:36.548835 <6>[ 0.568819] ACPI: Interpreter disabled.
10454 13:31:36.557774 <6>[ 0.575258] iommu: Default domain type: Translated
10455 13:31:36.564199 <6>[ 0.580370] iommu: DMA domain TLB invalidation policy: strict mode
10456 13:31:36.567799 <5>[ 0.587027] SCSI subsystem initialized
10457 13:31:36.574488 <6>[ 0.591275] usbcore: registered new interface driver usbfs
10458 13:31:36.580813 <6>[ 0.597005] usbcore: registered new interface driver hub
10459 13:31:36.583991 <6>[ 0.602556] usbcore: registered new device driver usb
10460 13:31:36.590913 <6>[ 0.608670] pps_core: LinuxPPS API ver. 1 registered
10461 13:31:36.601192 <6>[ 0.613865] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10462 13:31:36.604184 <6>[ 0.623208] PTP clock support registered
10463 13:31:36.607561 <6>[ 0.627452] EDAC MC: Ver: 3.0.0
10464 13:31:36.615224 <6>[ 0.632628] FPGA manager framework
10465 13:31:36.621535 <6>[ 0.636302] Advanced Linux Sound Architecture Driver Initialized.
10466 13:31:36.624898 <6>[ 0.643066] vgaarb: loaded
10467 13:31:36.631820 <6>[ 0.646236] clocksource: Switched to clocksource arch_sys_counter
10468 13:31:36.634635 <5>[ 0.652679] VFS: Disk quotas dquot_6.6.0
10469 13:31:36.641202 <6>[ 0.656868] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10470 13:31:36.644735 <6>[ 0.664056] pnp: PnP ACPI: disabled
10471 13:31:36.653366 <6>[ 0.670714] NET: Registered PF_INET protocol family
10472 13:31:36.659539 <6>[ 0.675991] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10473 13:31:36.674082 <6>[ 0.688294] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10474 13:31:36.684229 <6>[ 0.697109] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10475 13:31:36.690549 <6>[ 0.705080] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10476 13:31:36.700168 <6>[ 0.713781] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10477 13:31:36.707135 <6>[ 0.723540] TCP: Hash tables configured (established 65536 bind 65536)
10478 13:31:36.713676 <6>[ 0.730403] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10479 13:31:36.723624 <6>[ 0.737603] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10480 13:31:36.730175 <6>[ 0.745303] NET: Registered PF_UNIX/PF_LOCAL protocol family
10481 13:31:36.736357 <6>[ 0.751463] RPC: Registered named UNIX socket transport module.
10482 13:31:36.739765 <6>[ 0.757619] RPC: Registered udp transport module.
10483 13:31:36.743468 <6>[ 0.762549] RPC: Registered tcp transport module.
10484 13:31:36.752858 <6>[ 0.767481] RPC: Registered tcp NFSv4.1 backchannel transport module.
10485 13:31:36.756267 <6>[ 0.774150] PCI: CLS 0 bytes, default 64
10486 13:31:36.759735 <6>[ 0.778554] Unpacking initramfs...
10487 13:31:36.776721 <6>[ 0.790858] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10488 13:31:36.786527 <6>[ 0.799522] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10489 13:31:36.789553 <6>[ 0.808371] kvm [1]: IPA Size Limit: 40 bits
10490 13:31:36.796505 <6>[ 0.812905] kvm [1]: GICv3: no GICV resource entry
10491 13:31:36.799815 <6>[ 0.817926] kvm [1]: disabling GICv2 emulation
10492 13:31:36.806199 <6>[ 0.822610] kvm [1]: GIC system register CPU interface enabled
10493 13:31:36.809783 <6>[ 0.828802] kvm [1]: vgic interrupt IRQ18
10494 13:31:36.816232 <6>[ 0.833161] kvm [1]: VHE mode initialized successfully
10495 13:31:36.822754 <5>[ 0.839702] Initialise system trusted keyrings
10496 13:31:36.829097 <6>[ 0.844511] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10497 13:31:36.836770 <6>[ 0.854463] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10498 13:31:36.843234 <5>[ 0.860849] NFS: Registering the id_resolver key type
10499 13:31:36.846717 <5>[ 0.866147] Key type id_resolver registered
10500 13:31:36.853344 <5>[ 0.870564] Key type id_legacy registered
10501 13:31:36.860224 <6>[ 0.874845] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10502 13:31:36.866465 <6>[ 0.881769] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10503 13:31:36.872799 <6>[ 0.889478] 9p: Installing v9fs 9p2000 file system support
10504 13:31:36.909408 <5>[ 0.927039] Key type asymmetric registered
10505 13:31:36.912551 <5>[ 0.931372] Asymmetric key parser 'x509' registered
10506 13:31:36.922660 <6>[ 0.936516] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10507 13:31:36.925785 <6>[ 0.944128] io scheduler mq-deadline registered
10508 13:31:36.929216 <6>[ 0.948910] io scheduler kyber registered
10509 13:31:36.948081 <6>[ 0.966014] EINJ: ACPI disabled.
10510 13:31:36.980801 <4>[ 0.991797] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10511 13:31:36.990481 <4>[ 1.002447] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10512 13:31:37.005594 <6>[ 1.023275] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10513 13:31:37.013431 <6>[ 1.031303] printk: console [ttyS0] disabled
10514 13:31:37.041900 <6>[ 1.055956] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10515 13:31:37.047830 <6>[ 1.065457] printk: console [ttyS0] enabled
10516 13:31:37.051601 <6>[ 1.065457] printk: console [ttyS0] enabled
10517 13:31:37.058076 <6>[ 1.074354] printk: bootconsole [mtk8250] disabled
10518 13:31:37.061762 <6>[ 1.074354] printk: bootconsole [mtk8250] disabled
10519 13:31:37.068135 <6>[ 1.085597] SuperH (H)SCI(F) driver initialized
10520 13:31:37.071063 <6>[ 1.090870] msm_serial: driver initialized
10521 13:31:37.085720 <6>[ 1.099859] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10522 13:31:37.096032 <6>[ 1.108408] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10523 13:31:37.102289 <6>[ 1.116950] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10524 13:31:37.112249 <6>[ 1.125578] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10525 13:31:37.121890 <6>[ 1.134286] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10526 13:31:37.128481 <6>[ 1.143006] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10527 13:31:37.138461 <6>[ 1.151548] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10528 13:31:37.145714 <6>[ 1.160362] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10529 13:31:37.155065 <6>[ 1.168910] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10530 13:31:37.167030 <6>[ 1.184514] loop: module loaded
10531 13:31:37.174011 <6>[ 1.190584] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10532 13:31:37.196739 <4>[ 1.213789] mtk-pmic-keys: Failed to locate of_node [id: -1]
10533 13:31:37.203166 <6>[ 1.220647] megasas: 07.719.03.00-rc1
10534 13:31:37.212871 <6>[ 1.230162] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10535 13:31:37.220612 <6>[ 1.237620] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10536 13:31:37.236703 <6>[ 1.254198] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10537 13:31:37.293637 <6>[ 1.304033] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10538 13:31:37.506195 <6>[ 1.524131] Freeing initrd memory: 17352K
10539 13:31:37.517068 <6>[ 1.534338] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10540 13:31:37.527846 <6>[ 1.545393] tun: Universal TUN/TAP device driver, 1.6
10541 13:31:37.531214 <6>[ 1.551478] thunder_xcv, ver 1.0
10542 13:31:37.534583 <6>[ 1.554984] thunder_bgx, ver 1.0
10543 13:31:37.538011 <6>[ 1.558483] nicpf, ver 1.0
10544 13:31:37.548792 <6>[ 1.562517] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10545 13:31:37.551588 <6>[ 1.569994] hns3: Copyright (c) 2017 Huawei Corporation.
10546 13:31:37.555293 <6>[ 1.575582] hclge is initializing
10547 13:31:37.562112 <6>[ 1.579162] e1000: Intel(R) PRO/1000 Network Driver
10548 13:31:37.568569 <6>[ 1.584290] e1000: Copyright (c) 1999-2006 Intel Corporation.
10549 13:31:37.572109 <6>[ 1.590305] e1000e: Intel(R) PRO/1000 Network Driver
10550 13:31:37.578444 <6>[ 1.595520] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10551 13:31:37.585639 <6>[ 1.601705] igb: Intel(R) Gigabit Ethernet Network Driver
10552 13:31:37.591613 <6>[ 1.607355] igb: Copyright (c) 2007-2014 Intel Corporation.
10553 13:31:37.598287 <6>[ 1.613192] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10554 13:31:37.605092 <6>[ 1.619710] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10555 13:31:37.608261 <6>[ 1.626173] sky2: driver version 1.30
10556 13:31:37.614421 <6>[ 1.631174] VFIO - User Level meta-driver version: 0.3
10557 13:31:37.622201 <6>[ 1.639403] usbcore: registered new interface driver usb-storage
10558 13:31:37.628509 <6>[ 1.645862] usbcore: registered new device driver onboard-usb-hub
10559 13:31:37.637685 <6>[ 1.654992] mt6397-rtc mt6359-rtc: registered as rtc0
10560 13:31:37.647150 <6>[ 1.660454] mt6397-rtc mt6359-rtc: setting system clock to 2023-09-08T13:31:41 UTC (1694179901)
10561 13:31:37.650151 <6>[ 1.670037] i2c_dev: i2c /dev entries driver
10562 13:31:37.667586 <6>[ 1.681687] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10563 13:31:37.687693 <6>[ 1.705681] cpu cpu0: EM: created perf domain
10564 13:31:37.691321 <6>[ 1.710619] cpu cpu4: EM: created perf domain
10565 13:31:37.698878 <6>[ 1.716212] sdhci: Secure Digital Host Controller Interface driver
10566 13:31:37.705199 <6>[ 1.722643] sdhci: Copyright(c) Pierre Ossman
10567 13:31:37.712061 <6>[ 1.727593] Synopsys Designware Multimedia Card Interface Driver
10568 13:31:37.718346 <6>[ 1.734221] sdhci-pltfm: SDHCI platform and OF driver helper
10569 13:31:37.721534 <6>[ 1.734368] mmc0: CQHCI version 5.10
10570 13:31:37.728557 <6>[ 1.744431] ledtrig-cpu: registered to indicate activity on CPUs
10571 13:31:37.735233 <6>[ 1.751420] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10572 13:31:37.741598 <6>[ 1.758471] usbcore: registered new interface driver usbhid
10573 13:31:37.745109 <6>[ 1.764293] usbhid: USB HID core driver
10574 13:31:37.751414 <6>[ 1.768498] spi_master spi0: will run message pump with realtime priority
10575 13:31:37.794243 <6>[ 1.805507] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10576 13:31:37.814070 <6>[ 1.821584] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10577 13:31:37.817482 <6>[ 1.835196] mmc0: Command Queue Engine enabled
10578 13:31:37.824459 <6>[ 1.839978] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10579 13:31:37.830902 <6>[ 1.846909] cros-ec-spi spi0.0: Chrome EC device registered
10580 13:31:37.833977 <6>[ 1.847248] mmcblk0: mmc0:0001 DA4128 116 GiB
10581 13:31:37.845550 <6>[ 1.863600] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10582 13:31:37.853460 <6>[ 1.871053] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10583 13:31:37.859703 <6>[ 1.876946] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10584 13:31:37.866397 <6>[ 1.882878] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10585 13:31:37.876733 <6>[ 1.882997] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10586 13:31:37.883529 <6>[ 1.900029] NET: Registered PF_PACKET protocol family
10587 13:31:37.887038 <6>[ 1.905426] 9pnet: Installing 9P2000 support
10588 13:31:37.893397 <5>[ 1.909990] Key type dns_resolver registered
10589 13:31:37.896614 <6>[ 1.914952] registered taskstats version 1
10590 13:31:37.903271 <5>[ 1.919339] Loading compiled-in X.509 certificates
10591 13:31:37.932593 <4>[ 1.943295] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10592 13:31:37.942275 <4>[ 1.954138] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10593 13:31:37.949151 <3>[ 1.964694] debugfs: File 'uA_load' in directory '/' already present!
10594 13:31:37.955582 <3>[ 1.971401] debugfs: File 'min_uV' in directory '/' already present!
10595 13:31:37.962402 <3>[ 1.978021] debugfs: File 'max_uV' in directory '/' already present!
10596 13:31:37.969003 <3>[ 1.984632] debugfs: File 'constraint_flags' in directory '/' already present!
10597 13:31:37.980232 <3>[ 1.994398] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10598 13:31:37.989597 <6>[ 2.007332] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10599 13:31:37.996608 <6>[ 2.014119] xhci-mtk 11200000.usb: xHCI Host Controller
10600 13:31:38.003565 <6>[ 2.019625] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10601 13:31:38.013367 <6>[ 2.027523] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10602 13:31:38.020276 <6>[ 2.036961] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10603 13:31:38.026480 <6>[ 2.043044] xhci-mtk 11200000.usb: xHCI Host Controller
10604 13:31:38.033499 <6>[ 2.048521] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10605 13:31:38.039987 <6>[ 2.056165] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10606 13:31:38.046368 <6>[ 2.063793] hub 1-0:1.0: USB hub found
10607 13:31:38.050035 <6>[ 2.067802] hub 1-0:1.0: 1 port detected
10608 13:31:38.056214 <6>[ 2.072051] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10609 13:31:38.063381 <6>[ 2.080691] hub 2-0:1.0: USB hub found
10610 13:31:38.066312 <6>[ 2.084704] hub 2-0:1.0: 1 port detected
10611 13:31:38.075729 <6>[ 2.092906] mtk-msdc 11f70000.mmc: Got CD GPIO
10612 13:31:38.085278 <6>[ 2.099266] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10613 13:31:38.092039 <6>[ 2.107286] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10614 13:31:38.102084 <4>[ 2.115197] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10615 13:31:38.108700 <6>[ 2.124721] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10616 13:31:38.118649 <6>[ 2.132799] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10617 13:31:38.125632 <6>[ 2.140894] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10618 13:31:38.135348 <6>[ 2.148830] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10619 13:31:38.141717 <6>[ 2.156646] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10620 13:31:38.151879 <6>[ 2.164463] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10621 13:31:38.161785 <6>[ 2.175157] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10622 13:31:38.168755 <6>[ 2.183537] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10623 13:31:38.178286 <6>[ 2.191875] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10624 13:31:38.185055 <6>[ 2.200214] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10625 13:31:38.195129 <6>[ 2.208552] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10626 13:31:38.201459 <6>[ 2.216890] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10627 13:31:38.211175 <6>[ 2.225228] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10628 13:31:38.218218 <6>[ 2.233565] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10629 13:31:38.227732 <6>[ 2.241904] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10630 13:31:38.237846 <6>[ 2.250248] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10631 13:31:38.244448 <6>[ 2.258588] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10632 13:31:38.254287 <6>[ 2.266926] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10633 13:31:38.260827 <6>[ 2.275264] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10634 13:31:38.270718 <6>[ 2.283602] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10635 13:31:38.277165 <6>[ 2.291939] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10636 13:31:38.284031 <6>[ 2.300778] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10637 13:31:38.290499 <6>[ 2.307965] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10638 13:31:38.297175 <6>[ 2.314748] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10639 13:31:38.304275 <6>[ 2.321506] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10640 13:31:38.314506 <6>[ 2.328438] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10641 13:31:38.321246 <6>[ 2.335209] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10642 13:31:38.330541 <6>[ 2.344336] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10643 13:31:38.340824 <6>[ 2.353456] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10644 13:31:38.350467 <6>[ 2.362759] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10645 13:31:38.360399 <6>[ 2.372227] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10646 13:31:38.366758 <6>[ 2.381695] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10647 13:31:38.377231 <6>[ 2.390815] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10648 13:31:38.387234 <6>[ 2.400282] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10649 13:31:38.396225 <6>[ 2.409401] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10650 13:31:38.406380 <6>[ 2.418695] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10651 13:31:38.416100 <6>[ 2.428855] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10652 13:31:38.426125 <6>[ 2.440388] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10653 13:31:38.432661 <6>[ 2.450110] Trying to probe devices needed for running init ...
10654 13:31:38.456221 <6>[ 2.470736] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10655 13:31:38.484611 <6>[ 2.502016] hub 2-1:1.0: USB hub found
10656 13:31:38.487213 <6>[ 2.506504] hub 2-1:1.0: 3 ports detected
10657 13:31:38.607823 <6>[ 2.622506] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10658 13:31:38.762641 <6>[ 2.780624] hub 1-1:1.0: USB hub found
10659 13:31:38.766133 <6>[ 2.785140] hub 1-1:1.0: 4 ports detected
10660 13:31:38.840160 <6>[ 2.854598] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10661 13:31:39.088364 <6>[ 3.102556] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10662 13:31:39.219934 <6>[ 3.237796] hub 1-1.4:1.0: USB hub found
10663 13:31:39.223454 <6>[ 3.242327] hub 1-1.4:1.0: 2 ports detected
10664 13:31:39.520083 <6>[ 3.534554] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10665 13:31:39.711939 <6>[ 3.726553] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10666 13:31:50.713456 <6>[ 14.735552] ALSA device list:
10667 13:31:50.719181 <6>[ 14.738849] No soundcards found.
10668 13:31:50.727574 <6>[ 14.746803] Freeing unused kernel memory: 8384K
10669 13:31:50.730914 <6>[ 14.751817] Run /init as init process
10670 13:31:50.742472 Loading, please wait...
10671 13:31:50.762606 Starting version 247.3-7+deb11u2
10672 13:31:50.945956 <6>[ 14.962067] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10673 13:31:50.960362 <6>[ 14.979343] remoteproc remoteproc0: scp is available
10674 13:31:50.966952 <6>[ 14.984915] remoteproc remoteproc0: powering up scp
10675 13:31:50.973147 <6>[ 14.990102] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10676 13:31:50.980060 <6>[ 14.998570] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10677 13:31:50.991354 <6>[ 15.007432] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10678 13:31:50.997946 <3>[ 15.010293] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10679 13:31:51.008133 <6>[ 15.015217] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10680 13:31:51.014703 <3>[ 15.023251] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10681 13:31:51.024656 <4>[ 15.023395] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10682 13:31:51.031289 <6>[ 15.031927] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10683 13:31:51.040776 <3>[ 15.040003] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10684 13:31:51.047397 <4>[ 15.041582] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10685 13:31:51.054374 <6>[ 15.058619] usbcore: registered new interface driver r8152
10686 13:31:51.060648 <6>[ 15.058741] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10687 13:31:51.064136 <6>[ 15.065878] mc: Linux media interface: v0.10
10688 13:31:51.074733 <3>[ 15.090665] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10689 13:31:51.081521 <3>[ 15.099071] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10690 13:31:51.091540 <3>[ 15.107232] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10691 13:31:51.097692 <6>[ 15.115209] videodev: Linux video capture interface: v2.00
10692 13:31:51.104838 <3>[ 15.115363] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10693 13:31:51.114096 <3>[ 15.129186] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10694 13:31:51.120995 <6>[ 15.131800] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10695 13:31:51.127503 <6>[ 15.131812] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10696 13:31:51.137425 <3>[ 15.137396] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10697 13:31:51.143893 <6>[ 15.139056] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10698 13:31:51.153618 <6>[ 15.142914] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10699 13:31:51.160243 <6>[ 15.145885] remoteproc remoteproc0: remote processor scp is now up
10700 13:31:51.166927 <3>[ 15.152970] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10701 13:31:51.176944 <6>[ 15.153064] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10702 13:31:51.183804 <6>[ 15.171561] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10703 13:31:51.193307 <3>[ 15.177499] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10704 13:31:51.200395 <3>[ 15.177502] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10705 13:31:51.206581 <3>[ 15.177537] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10706 13:31:51.213333 <6>[ 15.183945] pci_bus 0000:00: root bus resource [bus 00-ff]
10707 13:31:51.223010 <3>[ 15.192013] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10708 13:31:51.230086 <3>[ 15.192015] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10709 13:31:51.239663 <3>[ 15.192018] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10710 13:31:51.246198 <3>[ 15.192021] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10711 13:31:51.252791 <3>[ 15.192036] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10712 13:31:51.263018 <6>[ 15.201356] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10713 13:31:51.269516 <4>[ 15.208186] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10714 13:31:51.276066 <4>[ 15.208186] Fallback method does not support PEC.
10715 13:31:51.286131 <6>[ 15.299443] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10716 13:31:51.292397 <6>[ 15.299444] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10717 13:31:51.302756 <6>[ 15.300027] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10718 13:31:51.309398 <6>[ 15.309548] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10719 13:31:51.318905 <6>[ 15.317146] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10720 13:31:51.325709 <6>[ 15.326676] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10721 13:31:51.335722 <4>[ 15.337578] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10722 13:31:51.339118 <6>[ 15.342025] pci 0000:00:00.0: supports D1 D2
10723 13:31:51.345866 <4>[ 15.349496] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10724 13:31:51.355202 <6>[ 15.358473] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10725 13:31:51.358706 <6>[ 15.359497] usbcore: registered new interface driver cdc_ether
10726 13:31:51.368780 <6>[ 15.359523] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10727 13:31:51.375415 <6>[ 15.359782] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10728 13:31:51.381576 <6>[ 15.359817] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10729 13:31:51.388394 <6>[ 15.359833] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10730 13:31:51.398275 <6>[ 15.359848] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10731 13:31:51.401797 <6>[ 15.359963] pci 0000:01:00.0: supports D1 D2
10732 13:31:51.408652 <6>[ 15.359965] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10733 13:31:51.415078 <6>[ 15.370442] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10734 13:31:51.418239 <6>[ 15.378877] Bluetooth: Core ver 2.22
10735 13:31:51.424859 <6>[ 15.378938] usbcore: registered new interface driver r8153_ecm
10736 13:31:51.434744 <6>[ 15.384486] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10737 13:31:51.437886 <6>[ 15.392757] NET: Registered PF_BLUETOOTH protocol family
10738 13:31:51.448127 <6>[ 15.398931] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10739 13:31:51.454349 <6>[ 15.406400] Bluetooth: HCI device and connection manager initialized
10740 13:31:51.457625 <6>[ 15.406421] Bluetooth: HCI socket layer initialized
10741 13:31:51.464271 <6>[ 15.407622] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10742 13:31:51.477855 <6>[ 15.408788] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10743 13:31:51.484973 <6>[ 15.408897] usbcore: registered new interface driver uvcvideo
10744 13:31:51.487869 <6>[ 15.410360] r8152 2-1.3:1.0 eth0: v1.12.13
10745 13:31:51.494659 <6>[ 15.413907] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10746 13:31:51.501315 <6>[ 15.417675] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10747 13:31:51.508356 <6>[ 15.421343] Bluetooth: L2CAP socket layer initialized
10748 13:31:51.514564 <6>[ 15.425874] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10749 13:31:51.521689 <6>[ 15.426821] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10750 13:31:51.528345 <6>[ 15.432726] Bluetooth: SCO socket layer initialized
10751 13:31:51.535292 <6>[ 15.439594] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10752 13:31:51.541758 <6>[ 15.490402] usbcore: registered new interface driver btusb
10753 13:31:51.551693 <4>[ 15.491343] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10754 13:31:51.558133 <3>[ 15.491359] Bluetooth: hci0: Failed to load firmware file (-2)
10755 13:31:51.564813 <3>[ 15.491365] Bluetooth: hci0: Failed to set up firmware (-2)
10756 13:31:51.574932 <4>[ 15.491372] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10757 13:31:51.577848 <6>[ 15.502339] pci 0000:00:00.0: PCI bridge to [bus 01]
10758 13:31:51.587803 <3>[ 15.514360] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10759 13:31:51.594886 <6>[ 15.520713] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10760 13:31:51.604898 <3>[ 15.548779] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10761 13:31:51.611294 <6>[ 15.552016] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10762 13:31:51.617650 <6>[ 15.635874] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10763 13:31:51.624522 <6>[ 15.642676] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10764 13:31:51.639827 <5>[ 15.655753] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10765 13:31:51.661806 <5>[ 15.677919] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10766 13:31:51.668465 <4>[ 15.684843] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10767 13:31:51.675196 <6>[ 15.693750] cfg80211: failed to load regulatory.db
10768 13:31:51.723501 <6>[ 15.739622] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10769 13:31:51.730226 <6>[ 15.747140] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10770 13:31:51.754448 <6>[ 15.773911] mt7921e 0000:01:00.0: ASIC revision: 79610010
10771 13:31:51.861846 <4>[ 15.874871] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10772 13:31:51.877971 Begin: Loading essential drivers ... done.
10773 13:31:51.881316 Begin: Running /scripts/init-premount ... done.
10774 13:31:51.888097 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10775 13:31:51.898068 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10776 13:31:51.901213 Device /sys/class/net/enx002432307c7b found
10777 13:31:51.901340 done.
10778 13:31:51.981009 IP-Config: enx002432307c7b hardware address 00:2<4>[ 15.994220] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10779 13:31:51.984338 4:32:30:7c:7b mtu 1500 DHCP
10780 13:31:52.101383 <4>[ 16.114147] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10781 13:31:52.221029 <4>[ 16.233731] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10782 13:31:52.341103 <4>[ 16.353907] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10783 13:31:52.460795 <4>[ 16.473748] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10784 13:31:52.581533 <4>[ 16.593865] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10785 13:31:52.700857 <4>[ 16.713716] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10786 13:31:52.820726 <4>[ 16.833791] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10787 13:31:52.940700 <4>[ 16.953743] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10788 13:31:53.052566 <3>[ 17.071804] mt7921e 0000:01:00.0: hardware init failed
10789 13:31:53.140921 IP-Config: no response after 2 secs - giving up
10790 13:31:53.151632 <6>[ 17.170870] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10791 13:31:53.186310 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10792 13:31:53.192944 IP-Config: enx002432307c7b complete (dhcp from 192.168.201.1):
10793 13:31:53.199992 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10794 13:31:53.206457 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10795 13:31:53.212945 host : mt8192-asurada-spherion-r0-cbg-2
10796 13:31:53.219641 domain : lava-rack
10797 13:31:53.222506 rootserver: 192.168.201.1 rootpath:
10798 13:31:53.222829 filename :
10799 13:31:53.282519 done.
10800 13:31:53.290174 Begin: Running /scripts/nfs-bottom ... done.
10801 13:31:53.310801 Begin: Running /scripts/init-bottom ... done.
10802 13:31:54.550933 <6>[ 18.570350] NET: Registered PF_INET6 protocol family
10803 13:31:54.558099 <6>[ 18.577885] Segment Routing with IPv6
10804 13:31:54.561484 <6>[ 18.581868] In-situ OAM (IOAM) with IPv6
10805 13:31:54.689523 <30>[ 18.689138] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10806 13:31:54.692520 <30>[ 18.713521] systemd[1]: Detected architecture arm64.
10807 13:31:54.715318
10808 13:31:54.718280 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10809 13:31:54.718389
10810 13:31:54.733067 <30>[ 18.752913] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10811 13:31:55.616664 <30>[ 19.633030] systemd[1]: Queued start job for default target Graphical Interface.
10812 13:31:55.653373 <30>[ 19.672922] systemd[1]: Created slice system-getty.slice.
10813 13:31:55.659559 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10814 13:31:55.676020 <30>[ 19.696031] systemd[1]: Created slice system-modprobe.slice.
10815 13:31:55.682964 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10816 13:31:55.699661 <30>[ 19.719822] systemd[1]: Created slice system-serial\x2dgetty.slice.
10817 13:31:55.709808 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10818 13:31:55.723675 <30>[ 19.743576] systemd[1]: Created slice User and Session Slice.
10819 13:31:55.730191 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10820 13:31:55.750960 <30>[ 19.767395] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10821 13:31:55.761001 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10822 13:31:55.778743 <30>[ 19.795183] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10823 13:31:55.785510 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10824 13:31:55.810102 <30>[ 19.823114] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10825 13:31:55.816780 <30>[ 19.835363] systemd[1]: Reached target Local Encrypted Volumes.
10826 13:31:55.823281 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10827 13:31:55.838863 <30>[ 19.858985] systemd[1]: Reached target Paths.
10828 13:31:55.845736 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10829 13:31:55.858833 <30>[ 19.878530] systemd[1]: Reached target Remote File Systems.
10830 13:31:55.865294 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10831 13:31:55.883081 <30>[ 19.902901] systemd[1]: Reached target Slices.
10832 13:31:55.889570 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10833 13:31:55.903020 <30>[ 19.922545] systemd[1]: Reached target Swap.
10834 13:31:55.906311 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10835 13:31:55.926552 <30>[ 19.943000] systemd[1]: Listening on initctl Compatibility Named Pipe.
10836 13:31:55.932762 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10837 13:31:55.939601 <30>[ 19.959190] systemd[1]: Listening on Journal Audit Socket.
10838 13:31:55.946228 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10839 13:31:55.964097 <30>[ 19.984105] systemd[1]: Listening on Journal Socket (/dev/log).
10840 13:31:55.971046 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10841 13:31:55.987181 <30>[ 20.007077] systemd[1]: Listening on Journal Socket.
10842 13:31:55.993735 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10843 13:31:56.011468 <30>[ 20.028047] systemd[1]: Listening on Network Service Netlink Socket.
10844 13:31:56.017793 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10845 13:31:56.033428 <30>[ 20.053431] systemd[1]: Listening on udev Control Socket.
10846 13:31:56.040093 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10847 13:31:56.054883 <30>[ 20.074968] systemd[1]: Listening on udev Kernel Socket.
10848 13:31:56.061493 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10849 13:31:56.102537 <30>[ 20.122661] systemd[1]: Mounting Huge Pages File System...
10850 13:31:56.109049 Mounting [0;1;39mHuge Pages File System[0m...
10851 13:31:56.127421 <30>[ 20.146971] systemd[1]: Mounting POSIX Message Queue File System...
10852 13:31:56.134051 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10853 13:31:56.155150 <30>[ 20.175093] systemd[1]: Mounting Kernel Debug File System...
10854 13:31:56.161615 Mounting [0;1;39mKernel Debug File System[0m...
10855 13:31:56.178367 <30>[ 20.195167] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10856 13:31:56.191093 <30>[ 20.207793] systemd[1]: Starting Create list of static device nodes for the current kernel...
10857 13:31:56.197634 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10858 13:31:56.219041 <30>[ 20.238879] systemd[1]: Starting Load Kernel Module configfs...
10859 13:31:56.226025 Starting [0;1;39mLoad Kernel Module configfs[0m...
10860 13:31:56.241972 <30>[ 20.262078] systemd[1]: Starting Load Kernel Module drm...
10861 13:31:56.249099 Starting [0;1;39mLoad Kernel Module drm[0m...
10862 13:31:56.267325 <30>[ 20.287393] systemd[1]: Starting Load Kernel Module fuse...
10863 13:31:56.274218 Starting [0;1;39mLoad Kernel Module fuse[0m...
10864 13:31:56.311165 <30>[ 20.327546] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10865 13:31:56.318184 <6>[ 20.337762] fuse: init (API version 7.37)
10866 13:31:56.355242 <30>[ 20.375166] systemd[1]: Starting Journal Service...
10867 13:31:56.361805 Starting [0;1;39mJournal Service[0m...
10868 13:31:56.383416 <30>[ 20.403008] systemd[1]: Starting Load Kernel Modules...
10869 13:31:56.389567 Starting [0;1;39mLoad Kernel Modules[0m...
10870 13:31:56.409354 <30>[ 20.426125] systemd[1]: Starting Remount Root and Kernel File Systems...
10871 13:31:56.415648 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10872 13:31:56.435435 <30>[ 20.455216] systemd[1]: Starting Coldplug All udev Devices...
10873 13:31:56.441817 Starting [0;1;39mColdplug All udev Devices[0m...
10874 13:31:56.459738 <30>[ 20.479743] systemd[1]: Mounted Huge Pages File System.
10875 13:31:56.466424 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10876 13:31:56.483193 <30>[ 20.503227] systemd[1]: Mounted POSIX Message Queue File System.
10877 13:31:56.490159 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10878 13:31:56.507032 <30>[ 20.527187] systemd[1]: Mounted Kernel Debug File System.
10879 13:31:56.513557 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10880 13:31:56.533940 <3>[ 20.550283] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10881 13:31:56.543772 <30>[ 20.560354] systemd[1]: Finished Create list of static device nodes for the current kernel.
10882 13:31:56.554378 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10883 13:31:56.564596 <3>[ 20.579896] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10884 13:31:56.571149 <30>[ 20.590240] systemd[1]: modprobe@configfs.service: Succeeded.
10885 13:31:56.577511 <30>[ 20.597142] systemd[1]: Finished Load Kernel Module configfs.
10886 13:31:56.584103 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10887 13:31:56.600454 <30>[ 20.619826] systemd[1]: modprobe@drm.service: Succeeded.
10888 13:31:56.610041 <3>[ 20.621752] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10889 13:31:56.616514 <30>[ 20.626073] systemd[1]: Finished Load Kernel Module drm.
10890 13:31:56.619885 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10891 13:31:56.635555 <30>[ 20.655171] systemd[1]: modprobe@fuse.service: Succeeded.
10892 13:31:56.645154 <3>[ 20.655518] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 13:31:56.651836 <30>[ 20.661582] systemd[1]: Finished Load Kernel Module fuse.
10894 13:31:56.655341 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10895 13:31:56.674920 <3>[ 20.691559] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10896 13:31:56.681611 <30>[ 20.691999] systemd[1]: Finished Load Kernel Modules.
10897 13:31:56.685311 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10898 13:31:56.700428 <30>[ 20.719835] systemd[1]: Finished Remount Root and Kernel File Systems.
10899 13:31:56.710468 <3>[ 20.723369] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10900 13:31:56.716984 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10901 13:31:56.742867 <3>[ 20.759602] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10902 13:31:56.767281 <30>[ 20.786619] systemd[1]: Mounting FUSE Control File System...
10903 13:31:56.777097 <3>[ 20.791452] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10904 13:31:56.780364 Mounting [0;1;39mFUSE Control File System[0m...
10905 13:31:56.799450 <30>[ 20.819160] systemd[1]: Mounting Kernel Configuration File System...
10906 13:31:56.809642 <3>[ 20.823133] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10907 13:31:56.816401 Mounting [0;1;39mKernel Configuration File System[0m...
10908 13:31:56.839645 <3>[ 20.856272] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10909 13:31:56.849948 <30>[ 20.856884] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10910 13:31:56.859155 <30>[ 20.874263] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10911 13:31:56.891769 <30>[ 20.911340] systemd[1]: Starting Load/Save Random Seed...
10912 13:31:56.898585 Starting [0;1;39mLoad/Save Random Seed[0m...
10913 13:31:56.913698 <30>[ 20.933222] systemd[1]: Starting Apply Kernel Variables...
10914 13:31:56.933789 Starting [0;1;39mApply Kernel Variable<4>[ 20.943319] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10915 13:31:56.936678 s[0m...
10916 13:31:56.943701 <3>[ 20.959641] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10917 13:31:56.954741 <30>[ 20.974915] systemd[1]: Starting Create System Users...
10918 13:31:56.961425 Starting [0;1;39mCreate System Users[0m...
10919 13:31:56.978778 <30>[ 20.998777] systemd[1]: Started Journal Service.
10920 13:31:56.985103 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10921 13:31:57.008145 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10922 13:31:57.022356 See 'systemctl status systemd-udev-trigger.service' for details.
10923 13:31:57.039398 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10924 13:31:57.055047 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10925 13:31:57.071549 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10926 13:31:57.088573 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10927 13:31:57.108669 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10928 13:31:57.168052 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10929 13:31:57.189365 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10930 13:31:57.232360 <46>[ 21.249262] systemd-journald[298]: Received client request to flush runtime journal.
10931 13:31:57.286667 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10932 13:31:57.299098 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10933 13:31:57.314892 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10934 13:31:57.387172 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10935 13:31:58.662685 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10936 13:31:58.695269 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10937 13:31:58.754947 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10938 13:31:58.797966 Starting [0;1;39mNetwork Service[0m...
10939 13:31:59.121974 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10940 13:31:59.166958 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10941 13:31:59.188356 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10942 13:31:59.482855 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10943 13:31:59.501868 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10944 13:31:59.556215 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10945 13:31:59.571761 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10946 13:31:59.592525 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10947 13:31:59.622213 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10948 13:31:59.694600 Starting [0;1;39mNetwork Name Resolution[0m...
10949 13:31:59.722708 Starting [0;1;39mNetwork Time Synchronization[0m...
10950 13:31:59.747234 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10951 13:31:59.763062 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10952 13:31:59.807354 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10953 13:31:59.967739 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10954 13:31:59.987302 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10955 13:32:00.010070 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10956 13:32:00.026630 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10957 13:32:00.046411 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10958 13:32:00.145751 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10959 13:32:00.179872 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10960 13:32:00.227324 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10961 13:32:00.263342 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10962 13:32:00.274445 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10963 13:32:00.536970 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10964 13:32:00.550198 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10965 13:32:00.567050 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10966 13:32:00.619054 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10967 13:32:01.022366 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10968 13:32:01.410945 Starting [0;1;39mUser Login Management[0m...
10969 13:32:01.427963 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10970 13:32:01.445269 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10971 13:32:01.461333 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10972 13:32:01.499098 Starting [0;1;39mPermit User Sessions[0m...
10973 13:32:01.608946 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10974 13:32:01.647283 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10975 13:32:01.665554 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10976 13:32:01.682131 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10977 13:32:01.709451 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10978 13:32:01.732508 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10979 13:32:01.756674 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10980 13:32:01.780674 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10981 13:32:01.845812 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10982 13:32:01.886278 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10983 13:32:01.993698
10984 13:32:01.993869
10985 13:32:01.996804 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10986 13:32:01.996928
10987 13:32:02.000151 debian-bullseye-arm64 login: root (automatic login)
10988 13:32:02.000270
10989 13:32:02.000377
10990 13:32:02.316598 Linux debian-bullseye-arm64 6.1.52-cip5 #1 SMP PREEMPT Fri Sep 8 13:10:51 UTC 2023 aarch64
10991 13:32:02.316807
10992 13:32:02.323161 The programs included with the Debian GNU/Linux system are free software;
10993 13:32:02.329564 the exact distribution terms for each program are described in the
10994 13:32:02.333267 individual files in /usr/share/doc/*/copyright.
10995 13:32:02.333397
10996 13:32:02.339562 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10997 13:32:02.342802 permitted by applicable law.
10998 13:32:02.436871 Matched prompt #10: / #
11000 13:32:02.437298 Setting prompt string to ['/ #']
11001 13:32:02.437449 end: 2.2.5.1 login-action (duration 00:00:27) [common]
11003 13:32:02.437790 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
11004 13:32:02.437934 start: 2.2.6 expect-shell-connection (timeout 00:03:20) [common]
11005 13:32:02.438054 Setting prompt string to ['/ #']
11006 13:32:02.438162 Forcing a shell prompt, looking for ['/ #']
11008 13:32:02.488445 / #
11009 13:32:02.488609 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11010 13:32:02.488731 Waiting using forced prompt support (timeout 00:02:30)
11011 13:32:02.492975
11012 13:32:02.493300 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11013 13:32:02.493445 start: 2.2.7 export-device-env (timeout 00:03:20) [common]
11015 13:32:02.593848 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11471176/extract-nfsrootfs-tmw6wty7'
11016 13:32:02.598751 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11471176/extract-nfsrootfs-tmw6wty7'
11018 13:32:02.699337 / # export NFS_SERVER_IP='192.168.201.1'
11019 13:32:02.704840 export NFS_SERVER_IP='192.168.201.1'
11020 13:32:02.705140 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11021 13:32:02.705280 end: 2.2 depthcharge-retry (duration 00:01:40) [common]
11022 13:32:02.705400 end: 2 depthcharge-action (duration 00:01:40) [common]
11023 13:32:02.705554 start: 3 lava-test-retry (timeout 00:01:00) [common]
11024 13:32:02.705687 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11025 13:32:02.705793 Using namespace: common
11027 13:32:02.806197 / # #
11028 13:32:02.806391 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11029 13:32:02.811746 #
11030 13:32:02.812060 Using /lava-11471176
11032 13:32:02.912408 / # export SHELL=/bin/sh
11033 13:32:02.917873 export SHELL=/bin/sh
11035 13:32:03.018491 / # . /lava-11471176/environment
11036 13:32:03.024176 . /lava-11471176/environment
11038 13:32:03.130456 / # /lava-11471176/bin/lava-test-runner /lava-11471176/0
11039 13:32:03.130671 Test shell timeout: 10s (minimum of the action and connection timeout)
11040 13:32:03.136093 /lava-11471176/bin/lava-test-runner /lava-11471176/0
11041 13:32:03.389596 + export TESTRUN_ID=0_dmesg
11042 13:32:03.393096 + cd /lava-11471176/0/tests/0_dmesg
11043 13:32:03.396167 + cat uuid
11044 13:32:03.409794 + UUID=11471176_1.<8>[ 27.427310] <LAVA_SIGNAL_STARTRUN 0_dmesg 11471176_1.6.2.3.1>
11045 13:32:03.409919 6.2.3.1
11046 13:32:03.410033 + set +x
11047 13:32:03.410334 Received signal: <STARTRUN> 0_dmesg 11471176_1.6.2.3.1
11048 13:32:03.410452 Starting test lava.0_dmesg (11471176_1.6.2.3.1)
11049 13:32:03.410662 Skipping test definition patterns.
11050 13:32:03.416189 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11051 13:32:03.525093 <8>[ 27.542355] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11052 13:32:03.525466 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11054 13:32:03.608577 <8>[ 27.626004] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11055 13:32:03.608937 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11057 13:32:03.693392 <8>[ 27.711146] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11058 13:32:03.693769 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11060 13:32:03.700308 + <8>[ 27.720819] <LAVA_SIGNAL_ENDRUN 0_dmesg 11471176_1.6.2.3.1>
11061 13:32:03.700428 set +x
11062 13:32:03.700706 Received signal: <ENDRUN> 0_dmesg 11471176_1.6.2.3.1
11063 13:32:03.700824 Ending use of test pattern.
11064 13:32:03.700919 Ending test lava.0_dmesg (11471176_1.6.2.3.1), duration 0.29
11066 13:32:03.708729 <LAVA_TEST_RUNNER EXIT>
11067 13:32:03.708988 ok: lava_test_shell seems to have completed
11068 13:32:03.709145 alert: pass
crit: pass
emerg: pass
11069 13:32:03.709268 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11070 13:32:03.709384 end: 3 lava-test-retry (duration 00:00:01) [common]
11071 13:32:03.709500 start: 4 lava-test-retry (timeout 00:01:00) [common]
11072 13:32:03.709620 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
11073 13:32:03.709714 Using namespace: common
11075 13:32:03.810040 / # #
11076 13:32:03.810210 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11077 13:32:03.810351 Using /lava-11471176
11079 13:32:03.910651 export SHELL=/bin/sh
11080 13:32:03.910918 #
11082 13:32:04.011516 / # export SHELL=/bin/sh. /lava-11471176/environment
11083 13:32:04.011724
11085 13:32:04.112283 / # . /lava-11471176/environment/lava-11471176/bin/lava-test-runner /lava-11471176/1
11086 13:32:04.112459 Test shell timeout: 10s (minimum of the action and connection timeout)
11087 13:32:04.112578
11088 13:32:04.117624 / # /lava-11471176/bin/lava-test-runner /lava-11471176/1
11089 13:32:04.253750 + export TESTRUN_ID=1_bootrr
11090 13:32:04.257070 + cd /lava-11471176/1/tests/1_bootrr
11091 13:32:04.260016 + cat uuid
11092 13:32:04.274844 + UUID=11471176_<8>[ 28.292615] <LAVA_SIGNAL_STARTRUN 1_bootrr 11471176_1.6.2.3.5>
11093 13:32:04.275017 1.6.2.3.5
11094 13:32:04.275092 + set +x
11095 13:32:04.275351 Received signal: <STARTRUN> 1_bootrr 11471176_1.6.2.3.5
11096 13:32:04.275419 Starting test lava.1_bootrr (11471176_1.6.2.3.5)
11097 13:32:04.275511 Skipping test definition patterns.
11098 13:32:04.288407 + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-11471176/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
11099 13:32:04.291149 + cd /opt/bootrr/libexec/bootrr
11100 13:32:04.291277 + sh helpers/bootrr-auto
11101 13:32:04.365076 /lava-11471176/1/../bin/lava-test-case
11102 13:32:04.398548 <8>[ 28.416038] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
11103 13:32:04.398900 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
11105 13:32:04.448749 /lava-11471176/1/../bin/lava-test-case
11106 13:32:04.478541 <8>[ 28.496099] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
11107 13:32:04.478859 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
11109 13:32:04.505645 /lava-11471176/1/../bin/lava-test-case
11110 13:32:04.533852 <8>[ 28.551543] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>
11111 13:32:04.534172 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
11113 13:32:04.600686 /lava-11471176/1/../bin/lava-test-case
11114 13:32:04.629492 <8>[ 28.646873] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
11115 13:32:04.629835 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
11117 13:32:04.669923 /lava-11471176/1/../bin/lava-test-case
11118 13:32:04.702008 <8>[ 28.719690] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
11119 13:32:04.702322 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
11121 13:32:04.738586 /lava-11471176/1/../bin/lava-test-case
11122 13:32:04.771789 <8>[ 28.789130] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
11123 13:32:04.772212 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
11125 13:32:04.812902 /lava-11471176/1/../bin/lava-test-case
11126 13:32:04.848667 <8>[ 28.866577] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
11127 13:32:04.849037 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
11129 13:32:04.890577 /lava-11471176/1/../bin/lava-test-case
11130 13:32:04.922886 <8>[ 28.940410] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
11131 13:32:04.923267 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
11133 13:32:04.956676 /lava-11471176/1/../bin/lava-test-case
11134 13:32:04.991275 <8>[ 29.009030] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
11135 13:32:04.991597 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
11137 13:32:05.034199 /lava-11471176/1/../bin/lava-test-case
11138 13:32:05.069523 <8>[ 29.087047] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
11139 13:32:05.069859 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
11141 13:32:05.095264 /lava-11471176/1/../bin/lava-test-case
11142 13:32:05.128090 <8>[ 29.145684] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
11143 13:32:05.128423 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
11145 13:32:05.169594 /lava-11471176/1/../bin/lava-test-case
11146 13:32:05.201538 <8>[ 29.219469] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
11147 13:32:05.201870 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
11149 13:32:05.246316 /lava-11471176/1/../bin/lava-test-case
11150 13:32:05.280131 <8>[ 29.297852] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
11151 13:32:05.280461 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
11153 13:32:05.323084 /lava-11471176/1/../bin/lava-test-case
11154 13:32:05.355292 <8>[ 29.373195] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
11155 13:32:05.355676 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
11157 13:32:05.393020 /lava-11471176/1/../bin/lava-test-case
11158 13:32:05.424606 <8>[ 29.442221] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
11159 13:32:05.424934 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11161 13:32:05.448162 /lava-11471176/1/../bin/lava-test-case
11162 13:32:05.476190 <8>[ 29.493703] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
11163 13:32:05.476534 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11165 13:32:05.511323 /lava-11471176/1/../bin/lava-test-case
11166 13:32:05.541046 <8>[ 29.558667] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
11167 13:32:05.541356 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11169 13:32:05.565051 /lava-11471176/1/../bin/lava-test-case
11170 13:32:05.594385 <8>[ 29.612090] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
11171 13:32:05.594692 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11173 13:32:05.631953 /lava-11471176/1/../bin/lava-test-case
11174 13:32:05.662599 <8>[ 29.680202] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
11175 13:32:05.662955 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11177 13:32:05.691996 /lava-11471176/1/../bin/lava-test-case
11178 13:32:05.720269 <8>[ 29.737845] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
11179 13:32:05.720621 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11181 13:32:05.755421 /lava-11471176/1/../bin/lava-test-case
11182 13:32:05.784389 <8>[ 29.802136] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
11183 13:32:05.784703 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11185 13:32:05.808402 /lava-11471176/1/../bin/lava-test-case
11186 13:32:05.838904 <8>[ 29.856438] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
11187 13:32:05.839217 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11189 13:32:05.878908 /lava-11471176/1/../bin/lava-test-case
11190 13:32:05.909564 <8>[ 29.927275] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
11191 13:32:05.909921 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11193 13:32:05.932347 /lava-11471176/1/../bin/lava-test-case
11194 13:32:05.960864 <8>[ 29.978467] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
11195 13:32:05.961212 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11197 13:32:05.996621 /lava-11471176/1/../bin/lava-test-case
11198 13:32:06.027046 <8>[ 30.044977] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11199 13:32:06.027380 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11201 13:32:06.072823 /lava-11471176/1/../bin/lava-test-case
11202 13:32:06.105039 <8>[ 30.122889] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11203 13:32:06.105359 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11205 13:32:06.127995 /lava-11471176/1/../bin/lava-test-case
11206 13:32:06.155660 <8>[ 30.173122] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11207 13:32:06.155992 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11209 13:32:06.194545 /lava-11471176/1/../bin/lava-test-case
11210 13:32:06.226193 <8>[ 30.244126] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11211 13:32:06.226530 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11213 13:32:06.249541 /lava-11471176/1/../bin/lava-test-case
11214 13:32:06.278833 <8>[ 30.296613] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11215 13:32:06.279148 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11217 13:32:06.315782 /lava-11471176/1/../bin/lava-test-case
11218 13:32:06.348235 <8>[ 30.366110] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11219 13:32:06.348561 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11221 13:32:06.383009 /lava-11471176/1/../bin/lava-test-case
11222 13:32:06.412761 <8>[ 30.430166] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11223 13:32:06.413083 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11225 13:32:06.455330 /lava-11471176/1/../bin/lava-test-case
11226 13:32:06.483923 <8>[ 30.501971] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11227 13:32:06.484368 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11229 13:32:06.519824 /lava-11471176/1/../bin/lava-test-case
11230 13:32:06.551006 <8>[ 30.568831] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11231 13:32:06.551318 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11233 13:32:06.574987 /lava-11471176/1/../bin/lava-test-case
11234 13:32:06.604924 <8>[ 30.622895] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11235 13:32:06.605231 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11237 13:32:06.641156 /lava-11471176/1/../bin/lava-test-case
11238 13:32:06.669800 <8>[ 30.687987] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11239 13:32:06.670118 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11241 13:32:06.707498 /lava-11471176/1/../bin/lava-test-case
11242 13:32:06.737852 <8>[ 30.755507] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11243 13:32:06.738217 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11245 13:32:06.767419 /lava-11471176/1/../bin/lava-test-case
11246 13:32:06.797587 <8>[ 30.815245] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11247 13:32:06.797892 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11249 13:32:06.833992 /lava-11471176/1/../bin/lava-test-case
11250 13:32:06.864028 <8>[ 30.881854] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11251 13:32:06.864362 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11253 13:32:06.885353 /lava-11471176/1/../bin/lava-test-case
11254 13:32:06.912324 <8>[ 30.930397] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11255 13:32:06.912628 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11257 13:32:06.950007 /lava-11471176/1/../bin/lava-test-case
11258 13:32:06.978121 <8>[ 30.996197] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11259 13:32:06.978474 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11261 13:32:07.000757 /lava-11471176/1/../bin/lava-test-case
11262 13:32:07.029072 <8>[ 31.046765] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11263 13:32:07.029424 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11265 13:32:07.066578 /lava-11471176/1/../bin/lava-test-case
11266 13:32:07.095260 <8>[ 31.113156] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11267 13:32:07.095602 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11269 13:32:07.123990 /lava-11471176/1/../bin/lava-test-case
11270 13:32:07.152368 <8>[ 31.170144] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11271 13:32:07.152675 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11273 13:32:07.188543 /lava-11471176/1/../bin/lava-test-case
11274 13:32:07.220207 <8>[ 31.238319] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11275 13:32:07.220515 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11277 13:32:07.243911 /lava-11471176/1/../bin/lava-test-case
11278 13:32:07.271957 <8>[ 31.289742] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11279 13:32:07.272269 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11281 13:32:07.309791 /lava-11471176/1/../bin/lava-test-case
11282 13:32:07.341354 <8>[ 31.358964] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11283 13:32:07.341657 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11285 13:32:07.364391 /lava-11471176/1/../bin/lava-test-case
11286 13:32:07.394166 <8>[ 31.412455] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11287 13:32:07.394478 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11289 13:32:07.430727 /lava-11471176/1/../bin/lava-test-case
11290 13:32:07.461666 <8>[ 31.479518] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11291 13:32:07.461977 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11293 13:32:07.491019 /lava-11471176/1/../bin/lava-test-case
11294 13:32:07.519913 <8>[ 31.537825] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11295 13:32:07.520223 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11297 13:32:07.557178 /lava-11471176/1/../bin/lava-test-case
11298 13:32:07.588684 <8>[ 31.606318] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11299 13:32:07.588991 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11301 13:32:07.622822 /lava-11471176/1/../bin/lava-test-case
11302 13:32:07.651480 <8>[ 31.669230] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11303 13:32:07.651782 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11305 13:32:07.673743 /lava-11471176/1/../bin/lava-test-case
11306 13:32:07.702999 <8>[ 31.720772] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11307 13:32:07.703301 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11309 13:32:07.739523 /lava-11471176/1/../bin/lava-test-case
11310 13:32:07.770437 <8>[ 31.788281] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11311 13:32:07.770757 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11313 13:32:07.792582 /lava-11471176/1/../bin/lava-test-case
11314 13:32:07.823662 <8>[ 31.841731] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11315 13:32:07.823931 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11317 13:32:07.866600 /lava-11471176/1/../bin/lava-test-case
11318 13:32:07.895715 <8>[ 31.913690] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11319 13:32:07.896053 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11321 13:32:07.933195 /lava-11471176/1/../bin/lava-test-case
11322 13:32:07.965093 <8>[ 31.982810] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11323 13:32:07.965400 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11325 13:32:07.999694 /lava-11471176/1/../bin/lava-test-case
11326 13:32:08.031693 <8>[ 32.049799] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11327 13:32:08.032007 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11329 13:32:08.070883 /lava-11471176/1/../bin/lava-test-case
11330 13:32:08.102207 <8>[ 32.120270] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11331 13:32:08.102520 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11333 13:32:08.140343 /lava-11471176/1/../bin/lava-test-case
11334 13:32:08.171800 <8>[ 32.190013] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11335 13:32:08.172184 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11337 13:32:08.201019 /lava-11471176/1/../bin/lava-test-case
11338 13:32:08.229232 <8>[ 32.247389] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11339 13:32:08.229538 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11341 13:32:08.263990 /lava-11471176/1/../bin/lava-test-case
11342 13:32:08.295046 <8>[ 32.312894] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11343 13:32:08.295361 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11345 13:32:08.329714 /lava-11471176/1/../bin/lava-test-case
11346 13:32:08.357925 <8>[ 32.375898] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11347 13:32:08.358237 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11349 13:32:08.380188 /lava-11471176/1/../bin/lava-test-case
11350 13:32:08.409546 <8>[ 32.427506] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11351 13:32:08.409856 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11353 13:32:08.445909 /lava-11471176/1/../bin/lava-test-case
11354 13:32:08.474689 <8>[ 32.492791] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11355 13:32:08.475000 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11357 13:32:08.496978 /lava-11471176/1/../bin/lava-test-case
11358 13:32:08.524900 <8>[ 32.542990] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11359 13:32:08.525216 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11361 13:32:08.569519 /lava-11471176/1/../bin/lava-test-case
11362 13:32:08.598749 <8>[ 32.616773] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11363 13:32:08.599082 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11365 13:32:08.621584 /lava-11471176/1/../bin/lava-test-case
11366 13:32:08.653356 <8>[ 32.671654] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11367 13:32:08.653668 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11369 13:32:08.692176 /lava-11471176/1/../bin/lava-test-case
11370 13:32:08.720923 <8>[ 32.739210] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11371 13:32:08.721259 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11373 13:32:08.756615 /lava-11471176/1/../bin/lava-test-case
11374 13:32:08.787807 <8>[ 32.806077] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11375 13:32:08.788144 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11377 13:32:08.825007 /lava-11471176/1/../bin/lava-test-case
11378 13:32:08.853015 <8>[ 32.871329] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11379 13:32:08.853343 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11381 13:32:08.897072 /lava-11471176/1/../bin/lava-test-case
11382 13:32:08.927578 <8>[ 32.945801] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11383 13:32:08.927934 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11385 13:32:08.963701 /lava-11471176/1/../bin/lava-test-case
11386 13:32:08.996761 <8>[ 33.015011] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11387 13:32:08.997135 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11389 13:32:09.035230 /lava-11471176/1/../bin/lava-test-case
11390 13:32:09.063540 <8>[ 33.081641] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11391 13:32:09.063864 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11393 13:32:09.101011 /lava-11471176/1/../bin/lava-test-case
11394 13:32:09.132623 <8>[ 33.150646] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11395 13:32:09.132946 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11397 13:32:09.167654 /lava-11471176/1/../bin/lava-test-case
11398 13:32:09.198720 <8>[ 33.216981] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11399 13:32:09.199031 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11401 13:32:09.240750 /lava-11471176/1/../bin/lava-test-case
11402 13:32:09.272189 <8>[ 33.290254] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11403 13:32:09.272536 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11405 13:32:09.310194 /lava-11471176/1/../bin/lava-test-case
11406 13:32:09.340214 <8>[ 33.358119] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11407 13:32:09.340566 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11409 13:32:09.373683 /lava-11471176/1/../bin/lava-test-case
11410 13:32:09.401511 <8>[ 33.419856] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11411 13:32:09.401843 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11413 13:32:09.436032 /lava-11471176/1/../bin/lava-test-case
11414 13:32:09.464431 <8>[ 33.482510] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11415 13:32:09.464752 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11417 13:32:09.501072 /lava-11471176/1/../bin/lava-test-case
11418 13:32:09.529535 <8>[ 33.547575] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11419 13:32:09.529877 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11421 13:32:09.571970 /lava-11471176/1/../bin/lava-test-case
11422 13:32:09.600888 <8>[ 33.618900] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11423 13:32:09.601249 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11425 13:32:09.636426 /lava-11471176/1/../bin/lava-test-case
11426 13:32:09.668551 <8>[ 33.686604] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11427 13:32:09.668859 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11429 13:32:09.693831 /lava-11471176/1/../bin/lava-test-case
11430 13:32:09.724842 <8>[ 33.742785] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11431 13:32:09.725244 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11433 13:32:09.761841 /lava-11471176/1/../bin/lava-test-case
11434 13:32:09.791385 <8>[ 33.809674] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11435 13:32:09.791735 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11437 13:32:09.814282 /lava-11471176/1/../bin/lava-test-case
11438 13:32:09.845342 <8>[ 33.863406] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11439 13:32:09.845692 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11441 13:32:09.880029 /lava-11471176/1/../bin/lava-test-case
11442 13:32:09.910125 <8>[ 33.928143] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11443 13:32:09.910454 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11445 13:32:09.940443 /lava-11471176/1/../bin/lava-test-case
11446 13:32:09.970228 <8>[ 33.988467] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11447 13:32:09.970564 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11449 13:32:10.006908 /lava-11471176/1/../bin/lava-test-case
11450 13:32:10.035728 <8>[ 34.054152] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11451 13:32:10.036067 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11453 13:32:10.059347 /lava-11471176/1/../bin/lava-test-case
11454 13:32:10.091506 <8>[ 34.109350] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11455 13:32:10.091832 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11457 13:32:10.128388 /lava-11471176/1/../bin/lava-test-case
11458 13:32:10.158722 <8>[ 34.177205] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11459 13:32:10.159086 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11461 13:32:10.182312 /lava-11471176/1/../bin/lava-test-case
11462 13:32:10.212355 <8>[ 34.230678] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11463 13:32:10.212681 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11465 13:32:10.251730 /lava-11471176/1/../bin/lava-test-case
11466 13:32:10.283186 <8>[ 34.301581] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11467 13:32:10.283514 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11469 13:32:10.313415 /lava-11471176/1/../bin/lava-test-case
11470 13:32:10.344630 <8>[ 34.362871] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11471 13:32:10.344946 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11473 13:32:10.384425 /lava-11471176/1/../bin/lava-test-case
11474 13:32:10.416056 <8>[ 34.434083] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11475 13:32:10.416365 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11477 13:32:10.452263 /lava-11471176/1/../bin/lava-test-case
11478 13:32:10.481731 <8>[ 34.500147] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11479 13:32:10.482056 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11481 13:32:10.505199 /lava-11471176/1/../bin/lava-test-case
11482 13:32:10.537102 <8>[ 34.555531] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11483 13:32:10.537444 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11485 13:32:10.574575 /lava-11471176/1/../bin/lava-test-case
11486 13:32:10.604306 <8>[ 34.622645] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11487 13:32:10.604636 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11489 13:32:10.634978 /lava-11471176/1/../bin/lava-test-case
11490 13:32:10.663542 <8>[ 34.682066] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11491 13:32:10.663914 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11493 13:32:10.699570 /lava-11471176/1/../bin/lava-test-case
11494 13:32:10.728993 <8>[ 34.747581] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11495 13:32:10.729332 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11497 13:32:10.751599 /lava-11471176/1/../bin/lava-test-case
11498 13:32:10.779233 <8>[ 34.797560] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11499 13:32:10.779567 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11501 13:32:11.835696 /lava-11471176/1/../bin/lava-test-case
11502 13:32:11.868259 <8>[ 35.886754] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11503 13:32:11.868604 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11505 13:32:11.890535 /lava-11471176/1/../bin/lava-test-case
11506 13:32:11.917870 <8>[ 35.936573] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11507 13:32:11.918216 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11509 13:32:12.968490 /lava-11471176/1/../bin/lava-test-case
11510 13:32:12.998802 <8>[ 37.017646] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11511 13:32:12.999145 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11513 13:32:13.019514 /lava-11471176/1/../bin/lava-test-case
11514 13:32:13.046850 <8>[ 37.065613] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11515 13:32:13.047185 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11517 13:32:14.096953 /lava-11471176/1/../bin/lava-test-case
11518 13:32:14.128840 <8>[ 38.147570] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11519 13:32:14.129164 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11521 13:32:14.151993 /lava-11471176/1/../bin/lava-test-case
11522 13:32:14.182347 <8>[ 38.200763] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11523 13:32:14.182667 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11525 13:32:15.231581 /lava-11471176/1/../bin/lava-test-case
11526 13:32:15.267088 <8>[ 39.285723] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11527 13:32:15.267421 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11529 13:32:15.288525 /lava-11471176/1/../bin/lava-test-case
11530 13:32:15.318341 <8>[ 39.336854] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11531 13:32:15.318674 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11533 13:32:16.369362 /lava-11471176/1/../bin/lava-test-case
11534 13:32:16.399445 <8>[ 40.418187] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11535 13:32:16.399784 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11537 13:32:16.423435 /lava-11471176/1/../bin/lava-test-case
11538 13:32:16.452280 <8>[ 40.471018] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11539 13:32:16.452606 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11541 13:32:17.502513 /lava-11471176/1/../bin/lava-test-case
11542 13:32:17.531294 <8>[ 41.550586] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11543 13:32:17.531649 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11545 13:32:17.555805 /lava-11471176/1/../bin/lava-test-case
11546 13:32:17.587281 <8>[ 41.606453] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11547 13:32:17.587649 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11549 13:32:18.634874 /lava-11471176/1/../bin/lava-test-case
11550 13:32:18.669815 <8>[ 42.689087] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11551 13:32:18.670127 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11553 13:32:18.695882 /lava-11471176/1/../bin/lava-test-case
11554 13:32:18.724638 <8>[ 42.743826] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11555 13:32:18.724961 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11557 13:32:18.747717 /lava-11471176/1/../bin/lava-test-case
11558 13:32:18.780276 <8>[ 42.799716] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11559 13:32:18.780602 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11561 13:32:19.832753 /lava-11471176/1/../bin/lava-test-case
11562 13:32:19.867270 <8>[ 43.886014] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11563 13:32:19.867592 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11565 13:32:19.893432 /lava-11471176/1/../bin/lava-test-case
11566 13:32:19.922192 <8>[ 43.941507] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11567 13:32:19.922531 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11569 13:32:19.962153 /lava-11471176/1/../bin/lava-test-case
11570 13:32:19.992967 <8>[ 44.012573] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11571 13:32:19.993285 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11573 13:32:20.019513 /lava-11471176/1/../bin/lava-test-case
11574 13:32:20.055810 <8>[ 44.074769] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11575 13:32:20.056186 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11577 13:32:20.100080 /lava-11471176/1/../bin/lava-test-case
11578 13:32:20.134456 <8>[ 44.153687] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11579 13:32:20.134802 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11581 13:32:20.179185 /lava-11471176/1/../bin/lava-test-case
11582 13:32:20.208442 <8>[ 44.228063] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11583 13:32:20.208769 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11585 13:32:20.248413 /lava-11471176/1/../bin/lava-test-case
11586 13:32:20.282976 <8>[ 44.302505] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11587 13:32:20.283307 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11589 13:32:20.309480 /lava-11471176/1/../bin/lava-test-case
11590 13:32:20.343658 <8>[ 44.362618] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11591 13:32:20.343986 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11593 13:32:20.388048 /lava-11471176/1/../bin/lava-test-case
11594 13:32:20.422158 <8>[ 44.441287] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11595 13:32:20.422483 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11597 13:32:20.459561 /lava-11471176/1/../bin/lava-test-case
11598 13:32:20.491110 <8>[ 44.510570] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11599 13:32:20.491428 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11601 13:32:20.522461 /lava-11471176/1/../bin/lava-test-case
11602 13:32:20.556959 <8>[ 44.576421] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11603 13:32:20.557280 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11605 13:32:20.601186 /lava-11471176/1/../bin/lava-test-case
11606 13:32:20.630459 <8>[ 44.650105] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11607 13:32:20.630770 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11609 13:32:20.654606 /lava-11471176/1/../bin/lava-test-case
11610 13:32:20.684288 <8>[ 44.703590] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11611 13:32:20.684598 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11613 13:32:20.725077 /lava-11471176/1/../bin/lava-test-case
11614 13:32:20.754542 <8>[ 44.774126] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11615 13:32:20.754917 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11617 13:32:20.780279 /lava-11471176/1/../bin/lava-test-case
11618 13:32:20.813431 <8>[ 44.833019] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11619 13:32:20.813762 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11621 13:32:20.862529 /lava-11471176/1/../bin/lava-test-case
11622 13:32:20.892422 <8>[ 44.912164] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11623 13:32:20.892736 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11625 13:32:20.918404 /lava-11471176/1/../bin/lava-test-case
11626 13:32:20.951007 <8>[ 44.970187] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11627 13:32:20.951370 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11629 13:32:20.991722 /lava-11471176/1/../bin/lava-test-case
11630 13:32:21.023852 <8>[ 45.043194] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11631 13:32:21.024184 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11633 13:32:21.049124 /lava-11471176/1/../bin/lava-test-case
11634 13:32:21.078020 <8>[ 45.097741] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11635 13:32:21.078333 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11637 13:32:21.115042 /lava-11471176/1/../bin/lava-test-case
11638 13:32:21.148199 <8>[ 45.167596] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11639 13:32:21.148496 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11641 13:32:21.180955 /lava-11471176/1/../bin/lava-test-case
11642 13:32:21.213375 <8>[ 45.232275] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11643 13:32:21.214049 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11645 13:32:22.133195 <6>[ 46.158672] vpu: disabling
11646 13:32:22.135985 <6>[ 46.161788] vproc2: disabling
11647 13:32:22.140453 <6>[ 46.166014] vproc1: disabling
11648 13:32:22.143985 <6>[ 46.169603] vaud18: disabling
11649 13:32:22.150931 <6>[ 46.173341] vsram_others: disabling
11650 13:32:22.153806 <6>[ 46.177563] va09: disabling
11651 13:32:22.157401 <6>[ 46.180973] vsram_md: disabling
11652 13:32:22.160806 <6>[ 46.184789] Vgpu: disabling
11653 13:32:22.272779 /lava-11471176/1/../bin/lava-test-case
11654 13:32:22.308302 <8>[ 46.327305] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11655 13:32:22.309018 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11657 13:32:23.361250 /lava-11471176/1/../bin/lava-test-case
11658 13:32:23.398777 <8>[ 47.418372] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11659 13:32:23.399594 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11661 13:32:23.426799 /lava-11471176/1/../bin/lava-test-case
11662 13:32:23.463210 <8>[ 47.482499] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11663 13:32:23.464006 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11665 13:32:23.510522 /lava-11471176/1/../bin/lava-test-case
11666 13:32:23.549305 <8>[ 47.568924] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11667 13:32:23.549970 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11669 13:32:23.577936 /lava-11471176/1/../bin/lava-test-case
11670 13:32:23.610907 <8>[ 47.630539] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11671 13:32:23.611273 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11673 13:32:23.654620 /lava-11471176/1/../bin/lava-test-case
11674 13:32:23.692794 <8>[ 47.712260] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11675 13:32:23.693388 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11677 13:32:23.729182 /lava-11471176/1/../bin/lava-test-case
11678 13:32:23.767460 <8>[ 47.786665] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11679 13:32:23.768249 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11681 13:32:23.807296 /lava-11471176/1/../bin/lava-test-case
11682 13:32:23.842356 <8>[ 47.862033] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11683 13:32:23.843115 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11685 13:32:23.870267 /lava-11471176/1/../bin/lava-test-case
11686 13:32:23.902531 <8>[ 47.922531] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11687 13:32:23.902836 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11689 13:32:23.941727 /lava-11471176/1/../bin/lava-test-case
11690 13:32:23.972699 <8>[ 47.992200] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11691 13:32:23.972967 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11693 13:32:23.999552 /lava-11471176/1/../bin/lava-test-case
11694 13:32:24.030961 <8>[ 48.050749] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11695 13:32:24.031234 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11697 13:32:24.073815 /lava-11471176/1/../bin/lava-test-case
11698 13:32:24.104980 <8>[ 48.124742] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11699 13:32:24.105248 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11701 13:32:24.130087 /lava-11471176/1/../bin/lava-test-case
11702 13:32:24.162343 <8>[ 48.181806] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11703 13:32:24.162616 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11705 13:32:24.205677 /lava-11471176/1/../bin/lava-test-case
11706 13:32:24.238675 <8>[ 48.258896] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11707 13:32:24.238953 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11709 13:32:24.261302 /lava-11471176/1/../bin/lava-test-case
11710 13:32:24.288206 <8>[ 48.308281] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11711 13:32:24.288478 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11713 13:32:24.324918 /lava-11471176/1/../bin/lava-test-case
11714 13:32:24.355581 <8>[ 48.375321] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11715 13:32:24.355853 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11717 13:32:24.384280 /lava-11471176/1/../bin/lava-test-case
11718 13:32:24.413300 <8>[ 48.433067] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11719 13:32:24.413587 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11721 13:32:24.448207 /lava-11471176/1/../bin/lava-test-case
11722 13:32:24.475666 <8>[ 48.495614] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11723 13:32:24.475948 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11725 13:32:24.498499 /lava-11471176/1/../bin/lava-test-case
11726 13:32:24.527272 <8>[ 48.547283] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11727 13:32:24.527544 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11729 13:32:24.563816 /lava-11471176/1/../bin/lava-test-case
11730 13:32:24.599537 <8>[ 48.619102] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11731 13:32:24.600518 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11733 13:32:24.627968 /lava-11471176/1/../bin/lava-test-case
11734 13:32:24.665479 <8>[ 48.685057] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11735 13:32:24.666194 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11737 13:32:24.716937 /lava-11471176/1/../bin/lava-test-case
11738 13:32:24.752312 <8>[ 48.772055] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11739 13:32:24.753191 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11741 13:32:25.796560 /lava-11471176/1/../bin/lava-test-case
11742 13:32:25.837316 <8>[ 49.856919] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11743 13:32:25.838035 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11745 13:32:26.882954 /lava-11471176/1/../bin/lava-test-case
11746 13:32:26.918471 <8>[ 50.938607] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11747 13:32:26.918765 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11748 13:32:26.918862 Bad test result: blocked
11749 13:32:26.943411 /lava-11471176/1/../bin/lava-test-case
11750 13:32:26.973599 <8>[ 50.993656] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11751 13:32:26.973874 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11753 13:32:28.026075 /lava-11471176/1/../bin/lava-test-case
11754 13:32:28.066932 <8>[ 52.087142] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11755 13:32:28.067662 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11757 13:32:28.095378 /lava-11471176/1/../bin/lava-test-case
11758 13:32:28.134841 <8>[ 52.154688] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11759 13:32:28.135647 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11761 13:32:28.184545 /lava-11471176/1/../bin/lava-test-case
11762 13:32:28.227123 <8>[ 52.247053] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11763 13:32:28.227866 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11765 13:32:28.270754 /lava-11471176/1/../bin/lava-test-case
11766 13:32:28.305936 <8>[ 52.325769] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11767 13:32:28.306640 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11769 13:32:28.333278 /lava-11471176/1/../bin/lava-test-case
11770 13:32:28.366925 <8>[ 52.386722] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11771 13:32:28.367308 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11773 13:32:28.411404 /lava-11471176/1/../bin/lava-test-case
11774 13:32:28.443542 <8>[ 52.463576] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11775 13:32:28.443873 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11777 13:32:28.466418 /lava-11471176/1/../bin/lava-test-case
11778 13:32:28.495529 <8>[ 52.515971] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11779 13:32:28.495835 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11781 13:32:29.544179 /lava-11471176/1/../bin/lava-test-case
11782 13:32:29.578231 <8>[ 53.598823] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11783 13:32:29.578530 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11785 13:32:29.604212 /lava-11471176/1/../bin/lava-test-case
11786 13:32:29.635136 <8>[ 53.655713] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11787 13:32:29.635624 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11789 13:32:30.686095 /lava-11471176/1/../bin/lava-test-case
11790 13:32:30.720517 <8>[ 54.741304] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11791 13:32:30.720820 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11793 13:32:30.742465 /lava-11471176/1/../bin/lava-test-case
11794 13:32:30.785413 <8>[ 54.805737] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11795 13:32:30.785813 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11797 13:32:31.841532 /lava-11471176/1/../bin/lava-test-case
11798 13:32:31.878559 <8>[ 55.898759] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11799 13:32:31.879275 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11801 13:32:31.902412 /lava-11471176/1/../bin/lava-test-case
11802 13:32:31.938592 <8>[ 55.958740] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11803 13:32:31.939298 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11805 13:32:33.000645 /lava-11471176/1/../bin/lava-test-case
11806 13:32:33.045472 <8>[ 57.066052] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11807 13:32:33.046244 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11809 13:32:33.073935 /lava-11471176/1/../bin/lava-test-case
11810 13:32:33.108682 <8>[ 57.129381] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11811 13:32:33.109379 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11813 13:32:33.153222 /lava-11471176/1/../bin/lava-test-case
11814 13:32:33.190390 <8>[ 57.211108] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11815 13:32:33.191115 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11817 13:32:33.231977 /lava-11471176/1/../bin/lava-test-case
11818 13:32:33.265470 <8>[ 57.286191] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11819 13:32:33.266166 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11821 13:32:33.291346 /lava-11471176/1/../bin/lava-test-case
11822 13:32:33.328481 <8>[ 57.348901] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11823 13:32:33.329309 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11825 13:32:33.380354 /lava-11471176/1/../bin/lava-test-case
11826 13:32:33.412995 <8>[ 57.433428] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11827 13:32:33.414029 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11829 13:32:33.437510 /lava-11471176/1/../bin/lava-test-case
11830 13:32:33.467663 <8>[ 57.488619] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11831 13:32:33.467944 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11833 13:32:33.507489 /lava-11471176/1/../bin/lava-test-case
11834 13:32:33.538114 <8>[ 57.559240] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11835 13:32:33.538393 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11837 13:32:33.562157 /lava-11471176/1/../bin/lava-test-case
11838 13:32:33.594082 <8>[ 57.614918] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11839 13:32:33.594356 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11841 13:32:33.634686 /lava-11471176/1/../bin/lava-test-case
11842 13:32:33.663205 <8>[ 57.684054] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11843 13:32:33.663481 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11845 13:32:33.679064 + <8>[ 57.703279] <LAVA_SIGNAL_ENDRUN 1_bootrr 11471176_1.6.2.3.5>
11846 13:32:33.679325 Received signal: <ENDRUN> 1_bootrr 11471176_1.6.2.3.5
11847 13:32:33.679411 Ending use of test pattern.
11848 13:32:33.679487 Ending test lava.1_bootrr (11471176_1.6.2.3.5), duration 29.40
11850 13:32:33.682075 set +x
11851 13:32:33.686312 <LAVA_TEST_RUNNER EXIT>
11852 13:32:33.686595 ok: lava_test_shell seems to have completed
11853 13:32:33.687795 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: skip
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11854 13:32:33.687986 end: 4.1 lava-test-shell (duration 00:00:30) [common]
11855 13:32:33.688087 end: 4 lava-test-retry (duration 00:00:30) [common]
11856 13:32:33.688192 start: 5 finalize (timeout 00:07:23) [common]
11857 13:32:33.688296 start: 5.1 power-off (timeout 00:00:30) [common]
11858 13:32:33.688465 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11859 13:32:33.764313 >> Command sent successfully.
11860 13:32:33.766960 Returned 0 in 0 seconds
11861 13:32:33.867378 end: 5.1 power-off (duration 00:00:00) [common]
11863 13:32:33.867752 start: 5.2 read-feedback (timeout 00:07:23) [common]
11864 13:32:33.868077 Listened to connection for namespace 'common' for up to 1s
11865 13:32:34.868231 Finalising connection for namespace 'common'
11866 13:32:34.868892 Disconnecting from shell: Finalise
11867 13:32:34.869375 / #
11868 13:32:34.970445 end: 5.2 read-feedback (duration 00:00:01) [common]
11869 13:32:34.971142 end: 5 finalize (duration 00:00:01) [common]
11870 13:32:34.971776 Cleaning after the job
11871 13:32:34.972413 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11471176/tftp-deploy-5nyrh5z2/ramdisk
11872 13:32:34.984042 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11471176/tftp-deploy-5nyrh5z2/kernel
11873 13:32:35.019910 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11471176/tftp-deploy-5nyrh5z2/dtb
11874 13:32:35.020291 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11471176/tftp-deploy-5nyrh5z2/nfsrootfs
11875 13:32:35.093793 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11471176/tftp-deploy-5nyrh5z2/modules
11876 13:32:35.101535 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11471176
11877 13:32:35.472247 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11471176
11878 13:32:35.472428 Job finished correctly