Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 34
- Boot result: PASS
- Warnings: 1
- Errors: 1
- Kernel Warnings: 22
1 13:30:37.275207 lava-dispatcher, installed at version: 2023.06
2 13:30:37.275449 start: 0 validate
3 13:30:37.275621 Start time: 2023-09-08 13:30:37.275612+00:00 (UTC)
4 13:30:37.275789 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:30:37.275992 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 13:30:37.549050 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:30:37.549230 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.52-cip5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:30:37.813913 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:30:37.814104 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.52-cip5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:30:38.079100 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:30:38.079265 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.52-cip5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 13:30:38.608333 validate duration: 1.33
14 13:30:38.608594 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:30:38.608691 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:30:38.608821 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:30:38.608947 Not decompressing ramdisk as can be used compressed.
18 13:30:38.609034 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230623.0/arm64/rootfs.cpio.gz
19 13:30:38.609103 saving as /var/lib/lava/dispatcher/tmp/11471188/tftp-deploy-0wnm07x2/ramdisk/rootfs.cpio.gz
20 13:30:38.609167 total size: 34390042 (32 MB)
21 13:30:38.612453 progress 0 % (0 MB)
22 13:30:38.624231 progress 5 % (1 MB)
23 13:30:38.637008 progress 10 % (3 MB)
24 13:30:38.648666 progress 15 % (4 MB)
25 13:30:38.661917 progress 20 % (6 MB)
26 13:30:38.674283 progress 25 % (8 MB)
27 13:30:38.685600 progress 30 % (9 MB)
28 13:30:38.698066 progress 35 % (11 MB)
29 13:30:38.710482 progress 40 % (13 MB)
30 13:30:38.723556 progress 45 % (14 MB)
31 13:30:38.735880 progress 50 % (16 MB)
32 13:30:38.750395 progress 55 % (18 MB)
33 13:30:38.763193 progress 60 % (19 MB)
34 13:30:38.776649 progress 65 % (21 MB)
35 13:30:38.788810 progress 70 % (22 MB)
36 13:30:38.801633 progress 75 % (24 MB)
37 13:30:38.815459 progress 80 % (26 MB)
38 13:30:38.828124 progress 85 % (27 MB)
39 13:30:38.841579 progress 90 % (29 MB)
40 13:30:38.855919 progress 95 % (31 MB)
41 13:30:38.869958 progress 100 % (32 MB)
42 13:30:38.870168 32 MB downloaded in 0.26 s (125.66 MB/s)
43 13:30:38.870396 end: 1.1.1 http-download (duration 00:00:00) [common]
45 13:30:38.870642 end: 1.1 download-retry (duration 00:00:00) [common]
46 13:30:38.870729 start: 1.2 download-retry (timeout 00:10:00) [common]
47 13:30:38.870817 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 13:30:38.870953 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.52-cip5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 13:30:38.871029 saving as /var/lib/lava/dispatcher/tmp/11471188/tftp-deploy-0wnm07x2/kernel/Image
50 13:30:38.871122 total size: 49220096 (46 MB)
51 13:30:38.871215 No compression specified
52 13:30:38.872681 progress 0 % (0 MB)
53 13:30:38.885621 progress 5 % (2 MB)
54 13:30:38.898465 progress 10 % (4 MB)
55 13:30:38.911739 progress 15 % (7 MB)
56 13:30:38.925325 progress 20 % (9 MB)
57 13:30:38.938650 progress 25 % (11 MB)
58 13:30:38.951974 progress 30 % (14 MB)
59 13:30:38.965007 progress 35 % (16 MB)
60 13:30:38.978189 progress 40 % (18 MB)
61 13:30:38.990986 progress 45 % (21 MB)
62 13:30:39.003622 progress 50 % (23 MB)
63 13:30:39.016076 progress 55 % (25 MB)
64 13:30:39.028591 progress 60 % (28 MB)
65 13:30:39.041125 progress 65 % (30 MB)
66 13:30:39.053707 progress 70 % (32 MB)
67 13:30:39.066307 progress 75 % (35 MB)
68 13:30:39.078810 progress 80 % (37 MB)
69 13:30:39.091254 progress 85 % (39 MB)
70 13:30:39.104054 progress 90 % (42 MB)
71 13:30:39.116625 progress 95 % (44 MB)
72 13:30:39.129336 progress 100 % (46 MB)
73 13:30:39.129467 46 MB downloaded in 0.26 s (181.70 MB/s)
74 13:30:39.129620 end: 1.2.1 http-download (duration 00:00:00) [common]
76 13:30:39.129856 end: 1.2 download-retry (duration 00:00:00) [common]
77 13:30:39.129945 start: 1.3 download-retry (timeout 00:09:59) [common]
78 13:30:39.130034 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 13:30:39.130166 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.52-cip5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 13:30:39.130236 saving as /var/lib/lava/dispatcher/tmp/11471188/tftp-deploy-0wnm07x2/dtb/mt8192-asurada-spherion-r0.dtb
81 13:30:39.130298 total size: 47278 (0 MB)
82 13:30:39.130359 No compression specified
83 13:30:39.131471 progress 69 % (0 MB)
84 13:30:39.131743 progress 100 % (0 MB)
85 13:30:39.131900 0 MB downloaded in 0.00 s (28.18 MB/s)
86 13:30:39.132028 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:30:39.132252 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:30:39.132338 start: 1.4 download-retry (timeout 00:09:59) [common]
90 13:30:39.132422 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 13:30:39.132531 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.52-cip5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 13:30:39.132614 saving as /var/lib/lava/dispatcher/tmp/11471188/tftp-deploy-0wnm07x2/modules/modules.tar
93 13:30:39.132681 total size: 8615576 (8 MB)
94 13:30:39.132743 Using unxz to decompress xz
95 13:30:39.136147 progress 0 % (0 MB)
96 13:30:39.157962 progress 5 % (0 MB)
97 13:30:39.187252 progress 10 % (0 MB)
98 13:30:39.221697 progress 15 % (1 MB)
99 13:30:39.248333 progress 20 % (1 MB)
100 13:30:39.274246 progress 25 % (2 MB)
101 13:30:39.300251 progress 30 % (2 MB)
102 13:30:39.328196 progress 35 % (2 MB)
103 13:30:39.354601 progress 40 % (3 MB)
104 13:30:39.379443 progress 45 % (3 MB)
105 13:30:39.406418 progress 50 % (4 MB)
106 13:30:39.432795 progress 55 % (4 MB)
107 13:30:39.457982 progress 60 % (4 MB)
108 13:30:39.480673 progress 65 % (5 MB)
109 13:30:39.508229 progress 70 % (5 MB)
110 13:30:39.532844 progress 75 % (6 MB)
111 13:30:39.559461 progress 80 % (6 MB)
112 13:30:39.589805 progress 85 % (7 MB)
113 13:30:39.616663 progress 90 % (7 MB)
114 13:30:39.642259 progress 95 % (7 MB)
115 13:30:39.667979 progress 100 % (8 MB)
116 13:30:39.675073 8 MB downloaded in 0.54 s (15.15 MB/s)
117 13:30:39.675412 end: 1.4.1 http-download (duration 00:00:01) [common]
119 13:30:39.675860 end: 1.4 download-retry (duration 00:00:01) [common]
120 13:30:39.675953 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 13:30:39.676052 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 13:30:39.676157 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:30:39.676263 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 13:30:39.676561 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11471188/lava-overlay-7erwvjrq
125 13:30:39.676694 makedir: /var/lib/lava/dispatcher/tmp/11471188/lava-overlay-7erwvjrq/lava-11471188/bin
126 13:30:39.676824 makedir: /var/lib/lava/dispatcher/tmp/11471188/lava-overlay-7erwvjrq/lava-11471188/tests
127 13:30:39.676940 makedir: /var/lib/lava/dispatcher/tmp/11471188/lava-overlay-7erwvjrq/lava-11471188/results
128 13:30:39.677069 Creating /var/lib/lava/dispatcher/tmp/11471188/lava-overlay-7erwvjrq/lava-11471188/bin/lava-add-keys
129 13:30:39.677212 Creating /var/lib/lava/dispatcher/tmp/11471188/lava-overlay-7erwvjrq/lava-11471188/bin/lava-add-sources
130 13:30:39.677358 Creating /var/lib/lava/dispatcher/tmp/11471188/lava-overlay-7erwvjrq/lava-11471188/bin/lava-background-process-start
131 13:30:39.677484 Creating /var/lib/lava/dispatcher/tmp/11471188/lava-overlay-7erwvjrq/lava-11471188/bin/lava-background-process-stop
132 13:30:39.677608 Creating /var/lib/lava/dispatcher/tmp/11471188/lava-overlay-7erwvjrq/lava-11471188/bin/lava-common-functions
133 13:30:39.677730 Creating /var/lib/lava/dispatcher/tmp/11471188/lava-overlay-7erwvjrq/lava-11471188/bin/lava-echo-ipv4
134 13:30:39.677854 Creating /var/lib/lava/dispatcher/tmp/11471188/lava-overlay-7erwvjrq/lava-11471188/bin/lava-install-packages
135 13:30:39.677976 Creating /var/lib/lava/dispatcher/tmp/11471188/lava-overlay-7erwvjrq/lava-11471188/bin/lava-installed-packages
136 13:30:39.678096 Creating /var/lib/lava/dispatcher/tmp/11471188/lava-overlay-7erwvjrq/lava-11471188/bin/lava-os-build
137 13:30:39.678219 Creating /var/lib/lava/dispatcher/tmp/11471188/lava-overlay-7erwvjrq/lava-11471188/bin/lava-probe-channel
138 13:30:39.678342 Creating /var/lib/lava/dispatcher/tmp/11471188/lava-overlay-7erwvjrq/lava-11471188/bin/lava-probe-ip
139 13:30:39.678465 Creating /var/lib/lava/dispatcher/tmp/11471188/lava-overlay-7erwvjrq/lava-11471188/bin/lava-target-ip
140 13:30:39.678591 Creating /var/lib/lava/dispatcher/tmp/11471188/lava-overlay-7erwvjrq/lava-11471188/bin/lava-target-mac
141 13:30:39.678714 Creating /var/lib/lava/dispatcher/tmp/11471188/lava-overlay-7erwvjrq/lava-11471188/bin/lava-target-storage
142 13:30:39.678842 Creating /var/lib/lava/dispatcher/tmp/11471188/lava-overlay-7erwvjrq/lava-11471188/bin/lava-test-case
143 13:30:39.678966 Creating /var/lib/lava/dispatcher/tmp/11471188/lava-overlay-7erwvjrq/lava-11471188/bin/lava-test-event
144 13:30:39.679089 Creating /var/lib/lava/dispatcher/tmp/11471188/lava-overlay-7erwvjrq/lava-11471188/bin/lava-test-feedback
145 13:30:39.679212 Creating /var/lib/lava/dispatcher/tmp/11471188/lava-overlay-7erwvjrq/lava-11471188/bin/lava-test-raise
146 13:30:39.679335 Creating /var/lib/lava/dispatcher/tmp/11471188/lava-overlay-7erwvjrq/lava-11471188/bin/lava-test-reference
147 13:30:39.679456 Creating /var/lib/lava/dispatcher/tmp/11471188/lava-overlay-7erwvjrq/lava-11471188/bin/lava-test-runner
148 13:30:39.679577 Creating /var/lib/lava/dispatcher/tmp/11471188/lava-overlay-7erwvjrq/lava-11471188/bin/lava-test-set
149 13:30:39.679701 Creating /var/lib/lava/dispatcher/tmp/11471188/lava-overlay-7erwvjrq/lava-11471188/bin/lava-test-shell
150 13:30:39.679826 Updating /var/lib/lava/dispatcher/tmp/11471188/lava-overlay-7erwvjrq/lava-11471188/bin/lava-install-packages (oe)
151 13:30:39.679975 Updating /var/lib/lava/dispatcher/tmp/11471188/lava-overlay-7erwvjrq/lava-11471188/bin/lava-installed-packages (oe)
152 13:30:39.680104 Creating /var/lib/lava/dispatcher/tmp/11471188/lava-overlay-7erwvjrq/lava-11471188/environment
153 13:30:39.680208 LAVA metadata
154 13:30:39.680286 - LAVA_JOB_ID=11471188
155 13:30:39.680353 - LAVA_DISPATCHER_IP=192.168.201.1
156 13:30:39.680457 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 13:30:39.680527 skipped lava-vland-overlay
158 13:30:39.680603 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 13:30:39.680684 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 13:30:39.680753 skipped lava-multinode-overlay
161 13:30:39.680832 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 13:30:39.680917 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 13:30:39.680994 Loading test definitions
164 13:30:39.681086 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 13:30:39.681159 Using /lava-11471188 at stage 0
166 13:30:39.681458 uuid=11471188_1.5.2.3.1 testdef=None
167 13:30:39.681548 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 13:30:39.681634 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 13:30:39.682143 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 13:30:39.682369 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 13:30:39.682977 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 13:30:39.683205 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 13:30:39.683799 runner path: /var/lib/lava/dispatcher/tmp/11471188/lava-overlay-7erwvjrq/lava-11471188/0/tests/0_cros-ec test_uuid 11471188_1.5.2.3.1
176 13:30:39.683951 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 13:30:39.684165 Creating lava-test-runner.conf files
179 13:30:39.684230 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11471188/lava-overlay-7erwvjrq/lava-11471188/0 for stage 0
180 13:30:39.684318 - 0_cros-ec
181 13:30:39.684418 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 13:30:39.684505 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 13:30:39.691233 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 13:30:39.691346 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 13:30:39.691438 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 13:30:39.691544 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 13:30:39.691633 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 13:30:40.633705 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 13:30:40.634075 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 13:30:40.634194 extracting modules file /var/lib/lava/dispatcher/tmp/11471188/tftp-deploy-0wnm07x2/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11471188/extract-overlay-ramdisk-4pbnkkxs/ramdisk
191 13:30:40.855903 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 13:30:40.856085 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 13:30:40.856187 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11471188/compress-overlay-h_tn8zzb/overlay-1.5.2.4.tar.gz to ramdisk
194 13:30:40.856261 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11471188/compress-overlay-h_tn8zzb/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11471188/extract-overlay-ramdisk-4pbnkkxs/ramdisk
195 13:30:40.862785 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 13:30:40.862901 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 13:30:40.862994 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 13:30:40.863087 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 13:30:40.863165 Building ramdisk /var/lib/lava/dispatcher/tmp/11471188/extract-overlay-ramdisk-4pbnkkxs/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11471188/extract-overlay-ramdisk-4pbnkkxs/ramdisk
200 13:30:41.487815 >> 270929 blocks
201 13:30:46.590988 rename /var/lib/lava/dispatcher/tmp/11471188/extract-overlay-ramdisk-4pbnkkxs/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11471188/tftp-deploy-0wnm07x2/ramdisk/ramdisk.cpio.gz
202 13:30:46.591445 end: 1.5.7 compress-ramdisk (duration 00:00:06) [common]
203 13:30:46.591600 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
204 13:30:46.591738 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
205 13:30:46.591878 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11471188/tftp-deploy-0wnm07x2/kernel/Image'
206 13:30:59.609322 Returned 0 in 13 seconds
207 13:30:59.709885 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11471188/tftp-deploy-0wnm07x2/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11471188/tftp-deploy-0wnm07x2/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11471188/tftp-deploy-0wnm07x2/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11471188/tftp-deploy-0wnm07x2/kernel/image.itb
208 13:31:00.341868 output: FIT description: Kernel Image image with one or more FDT blobs
209 13:31:00.342240 output: Created: Fri Sep 8 14:31:00 2023
210 13:31:00.342347 output: Image 0 (kernel-1)
211 13:31:00.342446 output: Description:
212 13:31:00.342540 output: Created: Fri Sep 8 14:31:00 2023
213 13:31:00.342633 output: Type: Kernel Image
214 13:31:00.342725 output: Compression: lzma compressed
215 13:31:00.342815 output: Data Size: 11040095 Bytes = 10781.34 KiB = 10.53 MiB
216 13:31:00.342903 output: Architecture: AArch64
217 13:31:00.342989 output: OS: Linux
218 13:31:00.343075 output: Load Address: 0x00000000
219 13:31:00.343159 output: Entry Point: 0x00000000
220 13:31:00.343242 output: Hash algo: crc32
221 13:31:00.343325 output: Hash value: 41c180c9
222 13:31:00.343408 output: Image 1 (fdt-1)
223 13:31:00.343491 output: Description: mt8192-asurada-spherion-r0
224 13:31:00.343574 output: Created: Fri Sep 8 14:31:00 2023
225 13:31:00.343657 output: Type: Flat Device Tree
226 13:31:00.343740 output: Compression: uncompressed
227 13:31:00.343822 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 13:31:00.343905 output: Architecture: AArch64
229 13:31:00.343988 output: Hash algo: crc32
230 13:31:00.344070 output: Hash value: cc4352de
231 13:31:00.344152 output: Image 2 (ramdisk-1)
232 13:31:00.344235 output: Description: unavailable
233 13:31:00.344317 output: Created: Fri Sep 8 14:31:00 2023
234 13:31:00.344418 output: Type: RAMDisk Image
235 13:31:00.344515 output: Compression: Unknown Compression
236 13:31:00.344597 output: Data Size: 47515113 Bytes = 46401.48 KiB = 45.31 MiB
237 13:31:00.344680 output: Architecture: AArch64
238 13:31:00.344801 output: OS: Linux
239 13:31:00.344903 output: Load Address: unavailable
240 13:31:00.344999 output: Entry Point: unavailable
241 13:31:00.345082 output: Hash algo: crc32
242 13:31:00.345170 output: Hash value: 77d6370a
243 13:31:00.345229 output: Default Configuration: 'conf-1'
244 13:31:00.345283 output: Configuration 0 (conf-1)
245 13:31:00.345337 output: Description: mt8192-asurada-spherion-r0
246 13:31:00.345390 output: Kernel: kernel-1
247 13:31:00.345443 output: Init Ramdisk: ramdisk-1
248 13:31:00.345497 output: FDT: fdt-1
249 13:31:00.345550 output: Loadables: kernel-1
250 13:31:00.345603 output:
251 13:31:00.345786 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 13:31:00.345881 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 13:31:00.346010 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 13:31:00.346101 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 13:31:00.346181 No LXC device requested
256 13:31:00.346258 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 13:31:00.346343 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 13:31:00.346422 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 13:31:00.346491 Checking files for TFTP limit of 4294967296 bytes.
260 13:31:00.346976 end: 1 tftp-deploy (duration 00:00:22) [common]
261 13:31:00.347082 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 13:31:00.347175 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 13:31:00.347291 substitutions:
264 13:31:00.347358 - {DTB}: 11471188/tftp-deploy-0wnm07x2/dtb/mt8192-asurada-spherion-r0.dtb
265 13:31:00.347423 - {INITRD}: 11471188/tftp-deploy-0wnm07x2/ramdisk/ramdisk.cpio.gz
266 13:31:00.347483 - {KERNEL}: 11471188/tftp-deploy-0wnm07x2/kernel/Image
267 13:31:00.347540 - {LAVA_MAC}: None
268 13:31:00.347596 - {PRESEED_CONFIG}: None
269 13:31:00.347651 - {PRESEED_LOCAL}: None
270 13:31:00.347706 - {RAMDISK}: 11471188/tftp-deploy-0wnm07x2/ramdisk/ramdisk.cpio.gz
271 13:31:00.347783 - {ROOT_PART}: None
272 13:31:00.347840 - {ROOT}: None
273 13:31:00.347895 - {SERVER_IP}: 192.168.201.1
274 13:31:00.347949 - {TEE}: None
275 13:31:00.348003 Parsed boot commands:
276 13:31:00.348057 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 13:31:00.348234 Parsed boot commands: tftpboot 192.168.201.1 11471188/tftp-deploy-0wnm07x2/kernel/image.itb 11471188/tftp-deploy-0wnm07x2/kernel/cmdline
278 13:31:00.348322 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 13:31:00.348406 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 13:31:00.348496 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 13:31:00.348581 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 13:31:00.348651 Not connected, no need to disconnect.
283 13:31:00.348724 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 13:31:00.348845 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 13:31:00.348914 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
286 13:31:00.352205 Setting prompt string to ['lava-test: # ']
287 13:31:00.352565 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 13:31:00.352692 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 13:31:00.352830 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 13:31:00.352957 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 13:31:00.353164 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
292 13:31:05.487757 >> Command sent successfully.
293 13:31:05.490200 Returned 0 in 5 seconds
294 13:31:05.590579 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 13:31:05.590902 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 13:31:05.591005 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 13:31:05.591094 Setting prompt string to 'Starting depthcharge on Spherion...'
299 13:31:05.591160 Changing prompt to 'Starting depthcharge on Spherion...'
300 13:31:05.591230 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 13:31:05.591493 [Enter `^Ec?' for help]
302 13:31:05.763941
303 13:31:05.764081
304 13:31:05.764189 F0: 102B 0000
305 13:31:05.764291
306 13:31:05.764352 F3: 1001 0000 [0200]
307 13:31:05.764411
308 13:31:05.767757 F3: 1001 0000
309 13:31:05.767853
310 13:31:05.767924 F7: 102D 0000
311 13:31:05.767986
312 13:31:05.768045 F1: 0000 0000
313 13:31:05.768103
314 13:31:05.771979 V0: 0000 0000 [0001]
315 13:31:05.772064
316 13:31:05.772130 00: 0007 8000
317 13:31:05.772236
318 13:31:05.775099 01: 0000 0000
319 13:31:05.775184
320 13:31:05.775250 BP: 0C00 0209 [0000]
321 13:31:05.775312
322 13:31:05.778562 G0: 1182 0000
323 13:31:05.778667
324 13:31:05.778761 EC: 0000 0021 [4000]
325 13:31:05.778852
326 13:31:05.782368 S7: 0000 0000 [0000]
327 13:31:05.782470
328 13:31:05.782563 CC: 0000 0000 [0001]
329 13:31:05.782657
330 13:31:05.785342 T0: 0000 0040 [010F]
331 13:31:05.785422
332 13:31:05.785487 Jump to BL
333 13:31:05.785553
334 13:31:05.811173
335 13:31:05.811300
336 13:31:05.811393
337 13:31:05.818848 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 13:31:05.822420 ARM64: Exception handlers installed.
339 13:31:05.826170 ARM64: Testing exception
340 13:31:05.826261 ARM64: Done test exception
341 13:31:05.833856 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 13:31:05.845616 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 13:31:05.852492 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 13:31:05.862577 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 13:31:05.869369 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 13:31:05.875902 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 13:31:05.887567 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 13:31:05.894174 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 13:31:05.913667 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 13:31:05.917258 WDT: Last reset was cold boot
351 13:31:05.920357 SPI1(PAD0) initialized at 2873684 Hz
352 13:31:05.923619 SPI5(PAD0) initialized at 992727 Hz
353 13:31:05.927028 VBOOT: Loading verstage.
354 13:31:05.933920 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 13:31:05.937037 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 13:31:05.940700 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 13:31:05.943721 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 13:31:05.951464 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 13:31:05.958162 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 13:31:05.968549 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 13:31:05.968635
362 13:31:05.968704
363 13:31:05.979315 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 13:31:05.982397 ARM64: Exception handlers installed.
365 13:31:05.985335 ARM64: Testing exception
366 13:31:05.985451 ARM64: Done test exception
367 13:31:05.992154 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 13:31:05.995547 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 13:31:06.009554 Probing TPM: . done!
370 13:31:06.009666 TPM ready after 0 ms
371 13:31:06.016765 Connected to device vid:did:rid of 1ae0:0028:00
372 13:31:06.024021 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 13:31:06.081078 Initialized TPM device CR50 revision 0
374 13:31:06.092620 tlcl_send_startup: Startup return code is 0
375 13:31:06.092733 TPM: setup succeeded
376 13:31:06.104161 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 13:31:06.113073 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 13:31:06.123314 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 13:31:06.132619 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 13:31:06.136298 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 13:31:06.144957 in-header: 03 07 00 00 08 00 00 00
382 13:31:06.148148 in-data: aa e4 47 04 13 02 00 00
383 13:31:06.151696 Chrome EC: UHEPI supported
384 13:31:06.158612 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 13:31:06.162431 in-header: 03 ad 00 00 08 00 00 00
386 13:31:06.165937 in-data: 00 20 20 08 00 00 00 00
387 13:31:06.166025 Phase 1
388 13:31:06.169743 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 13:31:06.177735 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 13:31:06.181475 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 13:31:06.185096 Recovery requested (1009000e)
392 13:31:06.196332 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 13:31:06.200117 tlcl_extend: response is 0
394 13:31:06.208772 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 13:31:06.214563 tlcl_extend: response is 0
396 13:31:06.221605 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 13:31:06.241639 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 13:31:06.248991 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 13:31:06.249080
400 13:31:06.249165
401 13:31:06.258719 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 13:31:06.262107 ARM64: Exception handlers installed.
403 13:31:06.262194 ARM64: Testing exception
404 13:31:06.265576 ARM64: Done test exception
405 13:31:06.287108 pmic_efuse_setting: Set efuses in 11 msecs
406 13:31:06.290187 pmwrap_interface_init: Select PMIF_VLD_RDY
407 13:31:06.296996 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 13:31:06.300993 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 13:31:06.307462 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 13:31:06.310941 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 13:31:06.314322 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 13:31:06.321802 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 13:31:06.325147 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 13:31:06.328968 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 13:31:06.332960 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 13:31:06.340430 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 13:31:06.344424 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 13:31:06.347997 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 13:31:06.351483 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 13:31:06.358520 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 13:31:06.365312 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 13:31:06.372723 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 13:31:06.376546 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 13:31:06.383822 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 13:31:06.387635 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 13:31:06.394257 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 13:31:06.397399 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 13:31:06.404936 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 13:31:06.411522 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 13:31:06.415085 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 13:31:06.421597 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 13:31:06.427997 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 13:31:06.431518 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 13:31:06.434814 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 13:31:06.441570 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 13:31:06.444654 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 13:31:06.451398 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 13:31:06.454775 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 13:31:06.461652 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 13:31:06.464929 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 13:31:06.471673 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 13:31:06.474607 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 13:31:06.481887 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 13:31:06.484626 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 13:31:06.491356 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 13:31:06.494618 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 13:31:06.498014 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 13:31:06.505043 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 13:31:06.508221 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 13:31:06.512438 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 13:31:06.516008 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 13:31:06.519287 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 13:31:06.525975 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 13:31:06.529543 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 13:31:06.532789 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 13:31:06.539097 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 13:31:06.542834 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 13:31:06.549402 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 13:31:06.559391 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 13:31:06.563095 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 13:31:06.569872 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 13:31:06.579380 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 13:31:06.582808 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 13:31:06.589715 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 13:31:06.593019 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 13:31:06.599983 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x11
467 13:31:06.606372 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 13:31:06.609789 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 13:31:06.612868 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 13:31:06.624421 [RTC]rtc_get_frequency_meter,154: input=15, output=773
471 13:31:06.633584 [RTC]rtc_get_frequency_meter,154: input=23, output=954
472 13:31:06.642968 [RTC]rtc_get_frequency_meter,154: input=19, output=865
473 13:31:06.652674 [RTC]rtc_get_frequency_meter,154: input=17, output=818
474 13:31:06.662478 [RTC]rtc_get_frequency_meter,154: input=16, output=796
475 13:31:06.665420 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
476 13:31:06.672357 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
477 13:31:06.675907 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
478 13:31:06.678772 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
479 13:31:06.682608 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
480 13:31:06.686104 ADC[4]: Raw value=903245 ID=7
481 13:31:06.689591 ADC[3]: Raw value=213179 ID=1
482 13:31:06.689678 RAM Code: 0x71
483 13:31:06.693522 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
484 13:31:06.700995 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
485 13:31:06.708517 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
486 13:31:06.716115 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
487 13:31:06.720117 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
488 13:31:06.723685 in-header: 03 07 00 00 08 00 00 00
489 13:31:06.723771 in-data: aa e4 47 04 13 02 00 00
490 13:31:06.727457 Chrome EC: UHEPI supported
491 13:31:06.734919 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
492 13:31:06.738965 in-header: 03 ed 00 00 08 00 00 00
493 13:31:06.742346 in-data: 80 20 60 08 00 00 00 00
494 13:31:06.746375 MRC: failed to locate region type 0.
495 13:31:06.752454 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
496 13:31:06.752573 DRAM-K: Running full calibration
497 13:31:06.759319 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
498 13:31:06.762955 header.status = 0x0
499 13:31:06.765898 header.version = 0x6 (expected: 0x6)
500 13:31:06.769422 header.size = 0xd00 (expected: 0xd00)
501 13:31:06.769528 header.flags = 0x0
502 13:31:06.776033 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
503 13:31:06.794436 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
504 13:31:06.801602 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
505 13:31:06.805690 dram_init: ddr_geometry: 2
506 13:31:06.805804 [EMI] MDL number = 2
507 13:31:06.809579 [EMI] Get MDL freq = 0
508 13:31:06.809683 dram_init: ddr_type: 0
509 13:31:06.813390 is_discrete_lpddr4: 1
510 13:31:06.816939 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
511 13:31:06.817017
512 13:31:06.817082
513 13:31:06.817161 [Bian_co] ETT version 0.0.0.1
514 13:31:06.824658 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
515 13:31:06.824775
516 13:31:06.827473 dramc_set_vcore_voltage set vcore to 650000
517 13:31:06.827587 Read voltage for 800, 4
518 13:31:06.830782 Vio18 = 0
519 13:31:06.830888 Vcore = 650000
520 13:31:06.830981 Vdram = 0
521 13:31:06.834568 Vddq = 0
522 13:31:06.834677 Vmddr = 0
523 13:31:06.837533 dram_init: config_dvfs: 1
524 13:31:06.841389 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
525 13:31:06.847904 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
526 13:31:06.851305 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
527 13:31:06.854976 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
528 13:31:06.857921 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
529 13:31:06.861433 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
530 13:31:06.864947 MEM_TYPE=3, freq_sel=18
531 13:31:06.867708 sv_algorithm_assistance_LP4_1600
532 13:31:06.871430 ============ PULL DRAM RESETB DOWN ============
533 13:31:06.874655 ========== PULL DRAM RESETB DOWN end =========
534 13:31:06.881151 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
535 13:31:06.884417 ===================================
536 13:31:06.884501 LPDDR4 DRAM CONFIGURATION
537 13:31:06.887994 ===================================
538 13:31:06.891185 EX_ROW_EN[0] = 0x0
539 13:31:06.894507 EX_ROW_EN[1] = 0x0
540 13:31:06.894590 LP4Y_EN = 0x0
541 13:31:06.897938 WORK_FSP = 0x0
542 13:31:06.898022 WL = 0x2
543 13:31:06.901253 RL = 0x2
544 13:31:06.901337 BL = 0x2
545 13:31:06.904973 RPST = 0x0
546 13:31:06.905055 RD_PRE = 0x0
547 13:31:06.908215 WR_PRE = 0x1
548 13:31:06.908297 WR_PST = 0x0
549 13:31:06.911622 DBI_WR = 0x0
550 13:31:06.911705 DBI_RD = 0x0
551 13:31:06.914942 OTF = 0x1
552 13:31:06.917916 ===================================
553 13:31:06.921353 ===================================
554 13:31:06.921436 ANA top config
555 13:31:06.924639 ===================================
556 13:31:06.927785 DLL_ASYNC_EN = 0
557 13:31:06.931145 ALL_SLAVE_EN = 1
558 13:31:06.934675 NEW_RANK_MODE = 1
559 13:31:06.934759 DLL_IDLE_MODE = 1
560 13:31:06.937915 LP45_APHY_COMB_EN = 1
561 13:31:06.941275 TX_ODT_DIS = 1
562 13:31:06.944856 NEW_8X_MODE = 1
563 13:31:06.947829 ===================================
564 13:31:06.951230 ===================================
565 13:31:06.951302 data_rate = 1600
566 13:31:06.954983 CKR = 1
567 13:31:06.957942 DQ_P2S_RATIO = 8
568 13:31:06.961651 ===================================
569 13:31:06.964700 CA_P2S_RATIO = 8
570 13:31:06.968306 DQ_CA_OPEN = 0
571 13:31:06.971615 DQ_SEMI_OPEN = 0
572 13:31:06.971699 CA_SEMI_OPEN = 0
573 13:31:06.975138 CA_FULL_RATE = 0
574 13:31:06.978163 DQ_CKDIV4_EN = 1
575 13:31:06.981423 CA_CKDIV4_EN = 1
576 13:31:06.984590 CA_PREDIV_EN = 0
577 13:31:06.988606 PH8_DLY = 0
578 13:31:06.988721 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
579 13:31:06.991620 DQ_AAMCK_DIV = 4
580 13:31:06.995003 CA_AAMCK_DIV = 4
581 13:31:06.998114 CA_ADMCK_DIV = 4
582 13:31:07.002229 DQ_TRACK_CA_EN = 0
583 13:31:07.005032 CA_PICK = 800
584 13:31:07.005115 CA_MCKIO = 800
585 13:31:07.008017 MCKIO_SEMI = 0
586 13:31:07.011893 PLL_FREQ = 3068
587 13:31:07.014702 DQ_UI_PI_RATIO = 32
588 13:31:07.018410 CA_UI_PI_RATIO = 0
589 13:31:07.021615 ===================================
590 13:31:07.024820 ===================================
591 13:31:07.028269 memory_type:LPDDR4
592 13:31:07.028353 GP_NUM : 10
593 13:31:07.031591 SRAM_EN : 1
594 13:31:07.031676 MD32_EN : 0
595 13:31:07.034784 ===================================
596 13:31:07.038801 [ANA_INIT] >>>>>>>>>>>>>>
597 13:31:07.042501 <<<<<< [CONFIGURE PHASE]: ANA_TX
598 13:31:07.046181 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
599 13:31:07.049841 ===================================
600 13:31:07.049926 data_rate = 1600,PCW = 0X7600
601 13:31:07.053790 ===================================
602 13:31:07.057691 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
603 13:31:07.061504 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
604 13:31:07.068971 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
605 13:31:07.072311 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
606 13:31:07.075710 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
607 13:31:07.079086 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
608 13:31:07.082492 [ANA_INIT] flow start
609 13:31:07.082605 [ANA_INIT] PLL >>>>>>>>
610 13:31:07.085861 [ANA_INIT] PLL <<<<<<<<
611 13:31:07.089101 [ANA_INIT] MIDPI >>>>>>>>
612 13:31:07.092524 [ANA_INIT] MIDPI <<<<<<<<
613 13:31:07.092644 [ANA_INIT] DLL >>>>>>>>
614 13:31:07.095799 [ANA_INIT] flow end
615 13:31:07.099324 ============ LP4 DIFF to SE enter ============
616 13:31:07.102671 ============ LP4 DIFF to SE exit ============
617 13:31:07.105978 [ANA_INIT] <<<<<<<<<<<<<
618 13:31:07.109348 [Flow] Enable top DCM control >>>>>
619 13:31:07.112943 [Flow] Enable top DCM control <<<<<
620 13:31:07.115789 Enable DLL master slave shuffle
621 13:31:07.122876 ==============================================================
622 13:31:07.123008 Gating Mode config
623 13:31:07.129349 ==============================================================
624 13:31:07.129481 Config description:
625 13:31:07.139343 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
626 13:31:07.145843 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
627 13:31:07.152692 SELPH_MODE 0: By rank 1: By Phase
628 13:31:07.156078 ==============================================================
629 13:31:07.159368 GAT_TRACK_EN = 1
630 13:31:07.163273 RX_GATING_MODE = 2
631 13:31:07.166930 RX_GATING_TRACK_MODE = 2
632 13:31:07.170548 SELPH_MODE = 1
633 13:31:07.170634 PICG_EARLY_EN = 1
634 13:31:07.174075 VALID_LAT_VALUE = 1
635 13:31:07.181167 ==============================================================
636 13:31:07.184741 Enter into Gating configuration >>>>
637 13:31:07.188369 Exit from Gating configuration <<<<
638 13:31:07.192263 Enter into DVFS_PRE_config >>>>>
639 13:31:07.203407 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
640 13:31:07.203528 Exit from DVFS_PRE_config <<<<<
641 13:31:07.206544 Enter into PICG configuration >>>>
642 13:31:07.210400 Exit from PICG configuration <<<<
643 13:31:07.214082 [RX_INPUT] configuration >>>>>
644 13:31:07.217463 [RX_INPUT] configuration <<<<<
645 13:31:07.221755 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
646 13:31:07.225050 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
647 13:31:07.232739 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
648 13:31:07.240170 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
649 13:31:07.247272 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
650 13:31:07.251453 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
651 13:31:07.255002 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
652 13:31:07.258765 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
653 13:31:07.262269 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
654 13:31:07.270062 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
655 13:31:07.270157 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
656 13:31:07.277664 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
657 13:31:07.281563 ===================================
658 13:31:07.281650 LPDDR4 DRAM CONFIGURATION
659 13:31:07.284959 ===================================
660 13:31:07.288924 EX_ROW_EN[0] = 0x0
661 13:31:07.289010 EX_ROW_EN[1] = 0x0
662 13:31:07.292810 LP4Y_EN = 0x0
663 13:31:07.292911 WORK_FSP = 0x0
664 13:31:07.296112 WL = 0x2
665 13:31:07.296197 RL = 0x2
666 13:31:07.300117 BL = 0x2
667 13:31:07.300202 RPST = 0x0
668 13:31:07.300269 RD_PRE = 0x0
669 13:31:07.303918 WR_PRE = 0x1
670 13:31:07.304002 WR_PST = 0x0
671 13:31:07.307471 DBI_WR = 0x0
672 13:31:07.307572 DBI_RD = 0x0
673 13:31:07.311151 OTF = 0x1
674 13:31:07.314640 ===================================
675 13:31:07.318061 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
676 13:31:07.321955 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
677 13:31:07.325931 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
678 13:31:07.329391 ===================================
679 13:31:07.333188 LPDDR4 DRAM CONFIGURATION
680 13:31:07.333278 ===================================
681 13:31:07.336585 EX_ROW_EN[0] = 0x10
682 13:31:07.340583 EX_ROW_EN[1] = 0x0
683 13:31:07.340698 LP4Y_EN = 0x0
684 13:31:07.344264 WORK_FSP = 0x0
685 13:31:07.344365 WL = 0x2
686 13:31:07.344457 RL = 0x2
687 13:31:07.348252 BL = 0x2
688 13:31:07.348336 RPST = 0x0
689 13:31:07.351929 RD_PRE = 0x0
690 13:31:07.352085 WR_PRE = 0x1
691 13:31:07.355386 WR_PST = 0x0
692 13:31:07.355472 DBI_WR = 0x0
693 13:31:07.359238 DBI_RD = 0x0
694 13:31:07.359382 OTF = 0x1
695 13:31:07.363157 ===================================
696 13:31:07.370505 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
697 13:31:07.374017 nWR fixed to 40
698 13:31:07.374102 [ModeRegInit_LP4] CH0 RK0
699 13:31:07.377939 [ModeRegInit_LP4] CH0 RK1
700 13:31:07.381612 [ModeRegInit_LP4] CH1 RK0
701 13:31:07.381697 [ModeRegInit_LP4] CH1 RK1
702 13:31:07.385408 match AC timing 13
703 13:31:07.389280 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
704 13:31:07.392705 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
705 13:31:07.396542 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
706 13:31:07.400289 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
707 13:31:07.407560 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
708 13:31:07.407645 [EMI DOE] emi_dcm 0
709 13:31:07.411349 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
710 13:31:07.411466 ==
711 13:31:07.414975 Dram Type= 6, Freq= 0, CH_0, rank 0
712 13:31:07.419052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
713 13:31:07.419141 ==
714 13:31:07.426458 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
715 13:31:07.429656 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
716 13:31:07.440680 [CA 0] Center 38 (7~69) winsize 63
717 13:31:07.444535 [CA 1] Center 38 (7~69) winsize 63
718 13:31:07.448093 [CA 2] Center 35 (5~66) winsize 62
719 13:31:07.451736 [CA 3] Center 35 (5~66) winsize 62
720 13:31:07.455745 [CA 4] Center 35 (4~66) winsize 63
721 13:31:07.459375 [CA 5] Center 34 (4~64) winsize 61
722 13:31:07.459496
723 13:31:07.462842 [CmdBusTrainingLP45] Vref(ca) range 1: 32
724 13:31:07.462946
725 13:31:07.466320 [CATrainingPosCal] consider 1 rank data
726 13:31:07.466425 u2DelayCellTimex100 = 270/100 ps
727 13:31:07.472843 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
728 13:31:07.476531 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
729 13:31:07.479379 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
730 13:31:07.482883 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
731 13:31:07.486128 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
732 13:31:07.490043 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
733 13:31:07.490129
734 13:31:07.492809 CA PerBit enable=1, Macro0, CA PI delay=34
735 13:31:07.492937
736 13:31:07.496240 [CBTSetCACLKResult] CA Dly = 34
737 13:31:07.499576 CS Dly: 5 (0~36)
738 13:31:07.499699 ==
739 13:31:07.503123 Dram Type= 6, Freq= 0, CH_0, rank 1
740 13:31:07.506364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
741 13:31:07.506473 ==
742 13:31:07.513172 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
743 13:31:07.516349 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
744 13:31:07.526540 [CA 0] Center 38 (7~69) winsize 63
745 13:31:07.530034 [CA 1] Center 38 (8~69) winsize 62
746 13:31:07.533425 [CA 2] Center 36 (6~67) winsize 62
747 13:31:07.536698 [CA 3] Center 35 (5~66) winsize 62
748 13:31:07.540198 [CA 4] Center 35 (4~66) winsize 63
749 13:31:07.543579 [CA 5] Center 34 (4~65) winsize 62
750 13:31:07.543705
751 13:31:07.546729 [CmdBusTrainingLP45] Vref(ca) range 1: 32
752 13:31:07.546856
753 13:31:07.550121 [CATrainingPosCal] consider 2 rank data
754 13:31:07.553595 u2DelayCellTimex100 = 270/100 ps
755 13:31:07.556808 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
756 13:31:07.560212 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
757 13:31:07.566852 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
758 13:31:07.570082 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
759 13:31:07.573485 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
760 13:31:07.576899 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
761 13:31:07.577022
762 13:31:07.580357 CA PerBit enable=1, Macro0, CA PI delay=34
763 13:31:07.580484
764 13:31:07.583750 [CBTSetCACLKResult] CA Dly = 34
765 13:31:07.583876 CS Dly: 6 (0~38)
766 13:31:07.583993
767 13:31:07.586747 ----->DramcWriteLeveling(PI) begin...
768 13:31:07.586877 ==
769 13:31:07.590215 Dram Type= 6, Freq= 0, CH_0, rank 0
770 13:31:07.596900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
771 13:31:07.597024 ==
772 13:31:07.600164 Write leveling (Byte 0): 32 => 32
773 13:31:07.603679 Write leveling (Byte 1): 31 => 31
774 13:31:07.603802 DramcWriteLeveling(PI) end<-----
775 13:31:07.607065
776 13:31:07.607190 ==
777 13:31:07.610606 Dram Type= 6, Freq= 0, CH_0, rank 0
778 13:31:07.613446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 13:31:07.613557 ==
780 13:31:07.617082 [Gating] SW mode calibration
781 13:31:07.624506 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
782 13:31:07.628074 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
783 13:31:07.631724 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
784 13:31:07.635581 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
785 13:31:07.642399 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 13:31:07.645400 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 13:31:07.649146 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 13:31:07.656336 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 13:31:07.659635 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 13:31:07.662563 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 13:31:07.666193 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 13:31:07.672910 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 13:31:07.676402 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 13:31:07.679388 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 13:31:07.686295 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 13:31:07.689618 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 13:31:07.693011 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 13:31:07.699667 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 13:31:07.702920 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
800 13:31:07.706525 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
801 13:31:07.712685 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
802 13:31:07.716150 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 13:31:07.719575 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 13:31:07.726185 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 13:31:07.729836 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 13:31:07.733153 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 13:31:07.739934 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 13:31:07.742829 0 9 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
809 13:31:07.746601 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
810 13:31:07.749811 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
811 13:31:07.756211 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 13:31:07.759881 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 13:31:07.763031 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 13:31:07.769819 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 13:31:07.773192 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 13:31:07.776622 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
817 13:31:07.783182 0 10 8 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
818 13:31:07.786324 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
819 13:31:07.789661 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 13:31:07.796707 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 13:31:07.800092 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 13:31:07.803256 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 13:31:07.809983 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 13:31:07.813501 0 11 4 | B1->B0 | 2323 3333 | 0 0 | (0 0) (1 1)
825 13:31:07.816427 0 11 8 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
826 13:31:07.819814 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 13:31:07.826566 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 13:31:07.830062 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 13:31:07.833249 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 13:31:07.840251 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 13:31:07.843494 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
832 13:31:07.846871 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
833 13:31:07.853724 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
834 13:31:07.857437 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 13:31:07.860183 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 13:31:07.866733 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 13:31:07.870314 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 13:31:07.873547 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 13:31:07.880153 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 13:31:07.883564 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 13:31:07.886994 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 13:31:07.890392 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 13:31:07.896860 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 13:31:07.900317 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 13:31:07.903778 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 13:31:07.910504 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 13:31:07.914107 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
848 13:31:07.916970 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
849 13:31:07.923797 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
850 13:31:07.923885 Total UI for P1: 0, mck2ui 16
851 13:31:07.930414 best dqsien dly found for B0: ( 0, 14, 2)
852 13:31:07.933754 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 13:31:07.936948 Total UI for P1: 0, mck2ui 16
854 13:31:07.940463 best dqsien dly found for B1: ( 0, 14, 10)
855 13:31:07.943705 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
856 13:31:07.947078 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
857 13:31:07.947239
858 13:31:07.950761 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
859 13:31:07.954003 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
860 13:31:07.957242 [Gating] SW calibration Done
861 13:31:07.957431 ==
862 13:31:07.960606 Dram Type= 6, Freq= 0, CH_0, rank 0
863 13:31:07.964017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
864 13:31:07.964189 ==
865 13:31:07.967373 RX Vref Scan: 0
866 13:31:07.967486
867 13:31:07.970552 RX Vref 0 -> 0, step: 1
868 13:31:07.970663
869 13:31:07.970810 RX Delay -130 -> 252, step: 16
870 13:31:07.977384 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
871 13:31:07.980443 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
872 13:31:07.983750 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
873 13:31:07.987099 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
874 13:31:07.990544 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
875 13:31:07.997532 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
876 13:31:08.000906 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
877 13:31:08.004361 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
878 13:31:08.007622 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
879 13:31:08.010610 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
880 13:31:08.017271 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
881 13:31:08.020647 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
882 13:31:08.024130 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
883 13:31:08.027419 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
884 13:31:08.030708 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
885 13:31:08.037531 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
886 13:31:08.037648 ==
887 13:31:08.040771 Dram Type= 6, Freq= 0, CH_0, rank 0
888 13:31:08.044351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
889 13:31:08.044466 ==
890 13:31:08.044572 DQS Delay:
891 13:31:08.047817 DQS0 = 0, DQS1 = 0
892 13:31:08.047925 DQM Delay:
893 13:31:08.050766 DQM0 = 89, DQM1 = 80
894 13:31:08.050881 DQ Delay:
895 13:31:08.054118 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
896 13:31:08.057761 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
897 13:31:08.060759 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
898 13:31:08.064517 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =93
899 13:31:08.064634
900 13:31:08.064740
901 13:31:08.064844 ==
902 13:31:08.067898 Dram Type= 6, Freq= 0, CH_0, rank 0
903 13:31:08.071134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 13:31:08.071243 ==
905 13:31:08.071340
906 13:31:08.071432
907 13:31:08.074228 TX Vref Scan disable
908 13:31:08.077742 == TX Byte 0 ==
909 13:31:08.080882 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
910 13:31:08.084517 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
911 13:31:08.087552 == TX Byte 1 ==
912 13:31:08.090981 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
913 13:31:08.094386 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
914 13:31:08.094473 ==
915 13:31:08.097678 Dram Type= 6, Freq= 0, CH_0, rank 0
916 13:31:08.103999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
917 13:31:08.104110 ==
918 13:31:08.115765 TX Vref=22, minBit 11, minWin=26, winSum=440
919 13:31:08.119192 TX Vref=24, minBit 8, minWin=27, winSum=443
920 13:31:08.122588 TX Vref=26, minBit 8, minWin=27, winSum=447
921 13:31:08.126151 TX Vref=28, minBit 14, minWin=27, winSum=453
922 13:31:08.129574 TX Vref=30, minBit 5, minWin=28, winSum=456
923 13:31:08.133104 TX Vref=32, minBit 10, minWin=27, winSum=455
924 13:31:08.139437 [TxChooseVref] Worse bit 5, Min win 28, Win sum 456, Final Vref 30
925 13:31:08.139526
926 13:31:08.142712 Final TX Range 1 Vref 30
927 13:31:08.142800
928 13:31:08.142867 ==
929 13:31:08.146109 Dram Type= 6, Freq= 0, CH_0, rank 0
930 13:31:08.149427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 13:31:08.149514 ==
932 13:31:08.149582
933 13:31:08.153020
934 13:31:08.153105 TX Vref Scan disable
935 13:31:08.155841 == TX Byte 0 ==
936 13:31:08.159687 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
937 13:31:08.162724 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
938 13:31:08.166019 == TX Byte 1 ==
939 13:31:08.169606 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
940 13:31:08.172806 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
941 13:31:08.176251
942 13:31:08.176336 [DATLAT]
943 13:31:08.176404 Freq=800, CH0 RK0
944 13:31:08.176466
945 13:31:08.179270 DATLAT Default: 0xa
946 13:31:08.179353 0, 0xFFFF, sum = 0
947 13:31:08.182669 1, 0xFFFF, sum = 0
948 13:31:08.182753 2, 0xFFFF, sum = 0
949 13:31:08.186453 3, 0xFFFF, sum = 0
950 13:31:08.186541 4, 0xFFFF, sum = 0
951 13:31:08.189845 5, 0xFFFF, sum = 0
952 13:31:08.189930 6, 0xFFFF, sum = 0
953 13:31:08.192769 7, 0xFFFF, sum = 0
954 13:31:08.192868 8, 0xFFFF, sum = 0
955 13:31:08.196589 9, 0x0, sum = 1
956 13:31:08.196701 10, 0x0, sum = 2
957 13:31:08.199649 11, 0x0, sum = 3
958 13:31:08.199751 12, 0x0, sum = 4
959 13:31:08.202983 best_step = 10
960 13:31:08.203147
961 13:31:08.203259 ==
962 13:31:08.206343 Dram Type= 6, Freq= 0, CH_0, rank 0
963 13:31:08.209770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
964 13:31:08.209854 ==
965 13:31:08.212748 RX Vref Scan: 1
966 13:31:08.212848
967 13:31:08.212911 Set Vref Range= 32 -> 127
968 13:31:08.212973
969 13:31:08.216242 RX Vref 32 -> 127, step: 1
970 13:31:08.216325
971 13:31:08.219598 RX Delay -95 -> 252, step: 8
972 13:31:08.219699
973 13:31:08.222906 Set Vref, RX VrefLevel [Byte0]: 32
974 13:31:08.226397 [Byte1]: 32
975 13:31:08.226482
976 13:31:08.229769 Set Vref, RX VrefLevel [Byte0]: 33
977 13:31:08.232693 [Byte1]: 33
978 13:31:08.236623
979 13:31:08.236709 Set Vref, RX VrefLevel [Byte0]: 34
980 13:31:08.239626 [Byte1]: 34
981 13:31:08.243824
982 13:31:08.243923 Set Vref, RX VrefLevel [Byte0]: 35
983 13:31:08.247529 [Byte1]: 35
984 13:31:08.251574
985 13:31:08.251657 Set Vref, RX VrefLevel [Byte0]: 36
986 13:31:08.254977 [Byte1]: 36
987 13:31:08.258975
988 13:31:08.259059 Set Vref, RX VrefLevel [Byte0]: 37
989 13:31:08.262281 [Byte1]: 37
990 13:31:08.267038
991 13:31:08.267122 Set Vref, RX VrefLevel [Byte0]: 38
992 13:31:08.270441 [Byte1]: 38
993 13:31:08.274264
994 13:31:08.274348 Set Vref, RX VrefLevel [Byte0]: 39
995 13:31:08.277487 [Byte1]: 39
996 13:31:08.281807
997 13:31:08.281907 Set Vref, RX VrefLevel [Byte0]: 40
998 13:31:08.285341 [Byte1]: 40
999 13:31:08.289975
1000 13:31:08.290058 Set Vref, RX VrefLevel [Byte0]: 41
1001 13:31:08.293248 [Byte1]: 41
1002 13:31:08.297384
1003 13:31:08.297469 Set Vref, RX VrefLevel [Byte0]: 42
1004 13:31:08.301060 [Byte1]: 42
1005 13:31:08.305153
1006 13:31:08.305237 Set Vref, RX VrefLevel [Byte0]: 43
1007 13:31:08.308088 [Byte1]: 43
1008 13:31:08.312384
1009 13:31:08.312468 Set Vref, RX VrefLevel [Byte0]: 44
1010 13:31:08.315708 [Byte1]: 44
1011 13:31:08.320637
1012 13:31:08.320760 Set Vref, RX VrefLevel [Byte0]: 45
1013 13:31:08.323849 [Byte1]: 45
1014 13:31:08.327607
1015 13:31:08.327692 Set Vref, RX VrefLevel [Byte0]: 46
1016 13:31:08.330704 [Byte1]: 46
1017 13:31:08.335301
1018 13:31:08.335385 Set Vref, RX VrefLevel [Byte0]: 47
1019 13:31:08.338422 [Byte1]: 47
1020 13:31:08.342806
1021 13:31:08.342891 Set Vref, RX VrefLevel [Byte0]: 48
1022 13:31:08.345961 [Byte1]: 48
1023 13:31:08.350212
1024 13:31:08.350296 Set Vref, RX VrefLevel [Byte0]: 49
1025 13:31:08.353514 [Byte1]: 49
1026 13:31:08.358411
1027 13:31:08.358495 Set Vref, RX VrefLevel [Byte0]: 50
1028 13:31:08.361010 [Byte1]: 50
1029 13:31:08.365911
1030 13:31:08.365995 Set Vref, RX VrefLevel [Byte0]: 51
1031 13:31:08.369089 [Byte1]: 51
1032 13:31:08.373074
1033 13:31:08.373157 Set Vref, RX VrefLevel [Byte0]: 52
1034 13:31:08.376566 [Byte1]: 52
1035 13:31:08.380696
1036 13:31:08.380842 Set Vref, RX VrefLevel [Byte0]: 53
1037 13:31:08.384345 [Byte1]: 53
1038 13:31:08.388248
1039 13:31:08.388332 Set Vref, RX VrefLevel [Byte0]: 54
1040 13:31:08.391881 [Byte1]: 54
1041 13:31:08.396021
1042 13:31:08.396109 Set Vref, RX VrefLevel [Byte0]: 55
1043 13:31:08.399572 [Byte1]: 55
1044 13:31:08.403394
1045 13:31:08.403467 Set Vref, RX VrefLevel [Byte0]: 56
1046 13:31:08.406524 [Byte1]: 56
1047 13:31:08.410938
1048 13:31:08.411056 Set Vref, RX VrefLevel [Byte0]: 57
1049 13:31:08.414526 [Byte1]: 57
1050 13:31:08.418941
1051 13:31:08.419019 Set Vref, RX VrefLevel [Byte0]: 58
1052 13:31:08.421987 [Byte1]: 58
1053 13:31:08.426282
1054 13:31:08.426367 Set Vref, RX VrefLevel [Byte0]: 59
1055 13:31:08.429729 [Byte1]: 59
1056 13:31:08.434147
1057 13:31:08.434234 Set Vref, RX VrefLevel [Byte0]: 60
1058 13:31:08.437214 [Byte1]: 60
1059 13:31:08.441461
1060 13:31:08.441537 Set Vref, RX VrefLevel [Byte0]: 61
1061 13:31:08.444883 [Byte1]: 61
1062 13:31:08.449214
1063 13:31:08.449295 Set Vref, RX VrefLevel [Byte0]: 62
1064 13:31:08.452499 [Byte1]: 62
1065 13:31:08.456443
1066 13:31:08.456529 Set Vref, RX VrefLevel [Byte0]: 63
1067 13:31:08.459784 [Byte1]: 63
1068 13:31:08.464120
1069 13:31:08.464204 Set Vref, RX VrefLevel [Byte0]: 64
1070 13:31:08.467506 [Byte1]: 64
1071 13:31:08.471993
1072 13:31:08.472120 Set Vref, RX VrefLevel [Byte0]: 65
1073 13:31:08.475020 [Byte1]: 65
1074 13:31:08.479453
1075 13:31:08.479588 Set Vref, RX VrefLevel [Byte0]: 66
1076 13:31:08.482927 [Byte1]: 66
1077 13:31:08.486985
1078 13:31:08.487113 Set Vref, RX VrefLevel [Byte0]: 67
1079 13:31:08.490515 [Byte1]: 67
1080 13:31:08.494854
1081 13:31:08.494974 Set Vref, RX VrefLevel [Byte0]: 68
1082 13:31:08.498163 [Byte1]: 68
1083 13:31:08.502112
1084 13:31:08.502236 Set Vref, RX VrefLevel [Byte0]: 69
1085 13:31:08.505354 [Byte1]: 69
1086 13:31:08.509882
1087 13:31:08.510012 Set Vref, RX VrefLevel [Byte0]: 70
1088 13:31:08.513253 [Byte1]: 70
1089 13:31:08.517677
1090 13:31:08.517817 Set Vref, RX VrefLevel [Byte0]: 71
1091 13:31:08.520492 [Byte1]: 71
1092 13:31:08.524885
1093 13:31:08.525017 Set Vref, RX VrefLevel [Byte0]: 72
1094 13:31:08.528204 [Byte1]: 72
1095 13:31:08.532403
1096 13:31:08.532539 Set Vref, RX VrefLevel [Byte0]: 73
1097 13:31:08.535843 [Byte1]: 73
1098 13:31:08.540439
1099 13:31:08.540571 Set Vref, RX VrefLevel [Byte0]: 74
1100 13:31:08.543768 [Byte1]: 74
1101 13:31:08.548258
1102 13:31:08.548385 Set Vref, RX VrefLevel [Byte0]: 75
1103 13:31:08.551065 [Byte1]: 75
1104 13:31:08.555222
1105 13:31:08.555326 Set Vref, RX VrefLevel [Byte0]: 76
1106 13:31:08.558574 [Byte1]: 76
1107 13:31:08.563030
1108 13:31:08.563114 Final RX Vref Byte 0 = 61 to rank0
1109 13:31:08.566595 Final RX Vref Byte 1 = 62 to rank0
1110 13:31:08.570009 Final RX Vref Byte 0 = 61 to rank1
1111 13:31:08.573355 Final RX Vref Byte 1 = 62 to rank1==
1112 13:31:08.576520 Dram Type= 6, Freq= 0, CH_0, rank 0
1113 13:31:08.580067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1114 13:31:08.583117 ==
1115 13:31:08.583202 DQS Delay:
1116 13:31:08.583269 DQS0 = 0, DQS1 = 0
1117 13:31:08.586337 DQM Delay:
1118 13:31:08.586421 DQM0 = 93, DQM1 = 82
1119 13:31:08.589972 DQ Delay:
1120 13:31:08.590056 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1121 13:31:08.593542 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1122 13:31:08.596821 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1123 13:31:08.603173 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =92
1124 13:31:08.603258
1125 13:31:08.603325
1126 13:31:08.609672 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e3a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1127 13:31:08.613333 CH0 RK0: MR19=606, MR18=3E3A
1128 13:31:08.619887 CH0_RK0: MR19=0x606, MR18=0x3E3A, DQSOSC=394, MR23=63, INC=95, DEC=63
1129 13:31:08.619973
1130 13:31:08.623265 ----->DramcWriteLeveling(PI) begin...
1131 13:31:08.623352 ==
1132 13:31:08.626695 Dram Type= 6, Freq= 0, CH_0, rank 1
1133 13:31:08.630134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1134 13:31:08.630218 ==
1135 13:31:08.633543 Write leveling (Byte 0): 30 => 30
1136 13:31:08.636691 Write leveling (Byte 1): 26 => 26
1137 13:31:08.640188 DramcWriteLeveling(PI) end<-----
1138 13:31:08.640297
1139 13:31:08.640392 ==
1140 13:31:08.643662 Dram Type= 6, Freq= 0, CH_0, rank 1
1141 13:31:08.647004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1142 13:31:08.647081 ==
1143 13:31:08.650371 [Gating] SW mode calibration
1144 13:31:08.656572 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1145 13:31:08.663533 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1146 13:31:08.667234 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1147 13:31:08.670532 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1148 13:31:08.676825 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 13:31:08.680074 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 13:31:08.683580 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 13:31:08.690222 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 13:31:08.734341 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 13:31:08.734452 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 13:31:08.734703 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 13:31:08.734771 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 13:31:08.735122 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 13:31:08.735711 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 13:31:08.735797 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 13:31:08.736044 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 13:31:08.736114 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 13:31:08.736246 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 13:31:08.765024 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 13:31:08.765123 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1164 13:31:08.765397 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1165 13:31:08.765655 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 13:31:08.765727 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 13:31:08.765809 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 13:31:08.765886 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 13:31:08.768784 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 13:31:08.772371 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 13:31:08.775809 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 13:31:08.782475 0 9 8 | B1->B0 | 2b2b 3434 | 1 0 | (1 1) (0 0)
1173 13:31:08.785683 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1174 13:31:08.789170 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1175 13:31:08.795483 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 13:31:08.798908 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 13:31:08.802326 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 13:31:08.805823 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 13:31:08.812250 0 10 4 | B1->B0 | 3333 2f2f | 1 1 | (1 0) (1 0)
1180 13:31:08.815585 0 10 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1181 13:31:08.819228 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 13:31:08.826127 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 13:31:08.829171 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 13:31:08.832967 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 13:31:08.839240 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 13:31:08.842642 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 13:31:08.845968 0 11 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1188 13:31:08.852693 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1189 13:31:08.856278 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 13:31:08.859082 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 13:31:08.865888 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 13:31:08.869421 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 13:31:08.873248 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 13:31:08.876711 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1195 13:31:08.880636 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1196 13:31:08.887980 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 13:31:08.890980 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 13:31:08.894442 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 13:31:08.898439 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 13:31:08.905242 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 13:31:08.908856 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 13:31:08.911863 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 13:31:08.918759 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 13:31:08.921747 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 13:31:08.925086 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 13:31:08.928369 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 13:31:08.935237 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 13:31:08.938569 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 13:31:08.941720 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 13:31:08.948500 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 13:31:08.952262 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 13:31:08.955386 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1213 13:31:08.962145 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1214 13:31:08.962271 Total UI for P1: 0, mck2ui 16
1215 13:31:08.968577 best dqsien dly found for B0: ( 0, 14, 8)
1216 13:31:08.968679 Total UI for P1: 0, mck2ui 16
1217 13:31:08.975516 best dqsien dly found for B1: ( 0, 14, 8)
1218 13:31:08.978708 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1219 13:31:08.982008 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1220 13:31:08.982090
1221 13:31:08.985323 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1222 13:31:08.988738 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1223 13:31:08.992244 [Gating] SW calibration Done
1224 13:31:08.992341 ==
1225 13:31:08.995557 Dram Type= 6, Freq= 0, CH_0, rank 1
1226 13:31:08.999138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1227 13:31:08.999221 ==
1228 13:31:09.002107 RX Vref Scan: 0
1229 13:31:09.002189
1230 13:31:09.002253 RX Vref 0 -> 0, step: 1
1231 13:31:09.002313
1232 13:31:09.005742 RX Delay -130 -> 252, step: 16
1233 13:31:09.008832 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1234 13:31:09.011969 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1235 13:31:09.018872 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1236 13:31:09.022443 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1237 13:31:09.025567 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1238 13:31:09.028895 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1239 13:31:09.032001 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1240 13:31:09.038978 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1241 13:31:09.042335 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1242 13:31:09.045455 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1243 13:31:09.049043 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1244 13:31:09.052085 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1245 13:31:09.058786 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1246 13:31:09.062243 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
1247 13:31:09.065845 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1248 13:31:09.068713 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1249 13:31:09.068820 ==
1250 13:31:09.072087 Dram Type= 6, Freq= 0, CH_0, rank 1
1251 13:31:09.079077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1252 13:31:09.079182 ==
1253 13:31:09.079342 DQS Delay:
1254 13:31:09.082359 DQS0 = 0, DQS1 = 0
1255 13:31:09.082459 DQM Delay:
1256 13:31:09.082547 DQM0 = 89, DQM1 = 79
1257 13:31:09.086081 DQ Delay:
1258 13:31:09.089037 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1259 13:31:09.092206 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1260 13:31:09.095451 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1261 13:31:09.099014 DQ12 =77, DQ13 =77, DQ14 =93, DQ15 =85
1262 13:31:09.099096
1263 13:31:09.099161
1264 13:31:09.099221 ==
1265 13:31:09.102498 Dram Type= 6, Freq= 0, CH_0, rank 1
1266 13:31:09.105863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1267 13:31:09.105948 ==
1268 13:31:09.106013
1269 13:31:09.106072
1270 13:31:09.109302 TX Vref Scan disable
1271 13:31:09.109385 == TX Byte 0 ==
1272 13:31:09.116031 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1273 13:31:09.119306 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1274 13:31:09.119407 == TX Byte 1 ==
1275 13:31:09.125698 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1276 13:31:09.129528 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1277 13:31:09.129612 ==
1278 13:31:09.132629 Dram Type= 6, Freq= 0, CH_0, rank 1
1279 13:31:09.135602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1280 13:31:09.135686 ==
1281 13:31:09.150253 TX Vref=22, minBit 8, minWin=27, winSum=445
1282 13:31:09.153610 TX Vref=24, minBit 8, minWin=27, winSum=448
1283 13:31:09.156871 TX Vref=26, minBit 8, minWin=27, winSum=451
1284 13:31:09.160448 TX Vref=28, minBit 1, minWin=28, winSum=452
1285 13:31:09.163696 TX Vref=30, minBit 1, minWin=28, winSum=457
1286 13:31:09.167200 TX Vref=32, minBit 6, minWin=28, winSum=455
1287 13:31:09.173739 [TxChooseVref] Worse bit 1, Min win 28, Win sum 457, Final Vref 30
1288 13:31:09.173823
1289 13:31:09.176876 Final TX Range 1 Vref 30
1290 13:31:09.176960
1291 13:31:09.177026 ==
1292 13:31:09.180278 Dram Type= 6, Freq= 0, CH_0, rank 1
1293 13:31:09.183552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1294 13:31:09.183636 ==
1295 13:31:09.183702
1296 13:31:09.186913
1297 13:31:09.187027 TX Vref Scan disable
1298 13:31:09.190516 == TX Byte 0 ==
1299 13:31:09.193437 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1300 13:31:09.200078 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1301 13:31:09.200200 == TX Byte 1 ==
1302 13:31:09.203405 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1303 13:31:09.209881 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1304 13:31:09.210007
1305 13:31:09.210117 [DATLAT]
1306 13:31:09.210230 Freq=800, CH0 RK1
1307 13:31:09.210343
1308 13:31:09.213345 DATLAT Default: 0xa
1309 13:31:09.213462 0, 0xFFFF, sum = 0
1310 13:31:09.216654 1, 0xFFFF, sum = 0
1311 13:31:09.216813 2, 0xFFFF, sum = 0
1312 13:31:09.219834 3, 0xFFFF, sum = 0
1313 13:31:09.219986 4, 0xFFFF, sum = 0
1314 13:31:09.223284 5, 0xFFFF, sum = 0
1315 13:31:09.226702 6, 0xFFFF, sum = 0
1316 13:31:09.226825 7, 0xFFFF, sum = 0
1317 13:31:09.230097 8, 0xFFFF, sum = 0
1318 13:31:09.230222 9, 0x0, sum = 1
1319 13:31:09.230335 10, 0x0, sum = 2
1320 13:31:09.233383 11, 0x0, sum = 3
1321 13:31:09.233504 12, 0x0, sum = 4
1322 13:31:09.236696 best_step = 10
1323 13:31:09.236841
1324 13:31:09.236952 ==
1325 13:31:09.240068 Dram Type= 6, Freq= 0, CH_0, rank 1
1326 13:31:09.243561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1327 13:31:09.243681 ==
1328 13:31:09.247099 RX Vref Scan: 0
1329 13:31:09.247216
1330 13:31:09.247327 RX Vref 0 -> 0, step: 1
1331 13:31:09.247467
1332 13:31:09.250137 RX Delay -79 -> 252, step: 8
1333 13:31:09.256881 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1334 13:31:09.260028 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1335 13:31:09.263418 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1336 13:31:09.267230 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1337 13:31:09.269982 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1338 13:31:09.276842 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1339 13:31:09.280237 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1340 13:31:09.283694 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1341 13:31:09.286876 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1342 13:31:09.290192 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1343 13:31:09.297032 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1344 13:31:09.300046 iDelay=209, Bit 11, Center 76 (-23 ~ 176) 200
1345 13:31:09.303879 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1346 13:31:09.306964 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1347 13:31:09.310399 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1348 13:31:09.316938 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1349 13:31:09.317022 ==
1350 13:31:09.320266 Dram Type= 6, Freq= 0, CH_0, rank 1
1351 13:31:09.323572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1352 13:31:09.323655 ==
1353 13:31:09.323721 DQS Delay:
1354 13:31:09.326971 DQS0 = 0, DQS1 = 0
1355 13:31:09.327054 DQM Delay:
1356 13:31:09.330393 DQM0 = 90, DQM1 = 80
1357 13:31:09.330475 DQ Delay:
1358 13:31:09.333823 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1359 13:31:09.337053 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1360 13:31:09.340433 DQ8 =72, DQ9 =68, DQ10 =80, DQ11 =76
1361 13:31:09.343884 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1362 13:31:09.343967
1363 13:31:09.344033
1364 13:31:09.350510 [DQSOSCAuto] RK1, (LSB)MR18= 0x421d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
1365 13:31:09.353732 CH0 RK1: MR19=606, MR18=421D
1366 13:31:09.360671 CH0_RK1: MR19=0x606, MR18=0x421D, DQSOSC=393, MR23=63, INC=95, DEC=63
1367 13:31:09.363940 [RxdqsGatingPostProcess] freq 800
1368 13:31:09.370418 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1369 13:31:09.370528 Pre-setting of DQS Precalculation
1370 13:31:09.377480 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1371 13:31:09.377569 ==
1372 13:31:09.380774 Dram Type= 6, Freq= 0, CH_1, rank 0
1373 13:31:09.384167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1374 13:31:09.384252 ==
1375 13:31:09.390548 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1376 13:31:09.397419 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1377 13:31:09.405076 [CA 0] Center 36 (6~67) winsize 62
1378 13:31:09.408570 [CA 1] Center 36 (6~67) winsize 62
1379 13:31:09.412182 [CA 2] Center 34 (4~65) winsize 62
1380 13:31:09.415572 [CA 3] Center 34 (3~65) winsize 63
1381 13:31:09.418971 [CA 4] Center 34 (4~65) winsize 62
1382 13:31:09.421950 [CA 5] Center 33 (3~64) winsize 62
1383 13:31:09.422033
1384 13:31:09.425193 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1385 13:31:09.425278
1386 13:31:09.428663 [CATrainingPosCal] consider 1 rank data
1387 13:31:09.431948 u2DelayCellTimex100 = 270/100 ps
1388 13:31:09.435413 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1389 13:31:09.438335 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1390 13:31:09.445413 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1391 13:31:09.448729 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1392 13:31:09.452162 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1393 13:31:09.455298 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1394 13:31:09.455381
1395 13:31:09.458676 CA PerBit enable=1, Macro0, CA PI delay=33
1396 13:31:09.458759
1397 13:31:09.461792 [CBTSetCACLKResult] CA Dly = 33
1398 13:31:09.461902 CS Dly: 5 (0~36)
1399 13:31:09.461996 ==
1400 13:31:09.465134 Dram Type= 6, Freq= 0, CH_1, rank 1
1401 13:31:09.471994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1402 13:31:09.472080 ==
1403 13:31:09.475371 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1404 13:31:09.481818 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1405 13:31:09.491620 [CA 0] Center 36 (6~67) winsize 62
1406 13:31:09.494852 [CA 1] Center 37 (6~68) winsize 63
1407 13:31:09.498133 [CA 2] Center 35 (4~66) winsize 63
1408 13:31:09.501659 [CA 3] Center 34 (4~65) winsize 62
1409 13:31:09.504645 [CA 4] Center 34 (4~65) winsize 62
1410 13:31:09.508543 [CA 5] Center 34 (4~65) winsize 62
1411 13:31:09.508647
1412 13:31:09.511506 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1413 13:31:09.511597
1414 13:31:09.515141 [CATrainingPosCal] consider 2 rank data
1415 13:31:09.518331 u2DelayCellTimex100 = 270/100 ps
1416 13:31:09.521601 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1417 13:31:09.524683 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1418 13:31:09.528282 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1419 13:31:09.535481 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1420 13:31:09.535567 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1421 13:31:09.539338 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1422 13:31:09.542922
1423 13:31:09.546665 CA PerBit enable=1, Macro0, CA PI delay=34
1424 13:31:09.546761
1425 13:31:09.546831 [CBTSetCACLKResult] CA Dly = 34
1426 13:31:09.550124 CS Dly: 6 (0~38)
1427 13:31:09.550221
1428 13:31:09.554064 ----->DramcWriteLeveling(PI) begin...
1429 13:31:09.554154 ==
1430 13:31:09.557608 Dram Type= 6, Freq= 0, CH_1, rank 0
1431 13:31:09.561199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1432 13:31:09.561312 ==
1433 13:31:09.565260 Write leveling (Byte 0): 28 => 28
1434 13:31:09.568365 Write leveling (Byte 1): 28 => 28
1435 13:31:09.568483 DramcWriteLeveling(PI) end<-----
1436 13:31:09.568592
1437 13:31:09.568685 ==
1438 13:31:09.571815 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 13:31:09.578444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 13:31:09.578560 ==
1441 13:31:09.581994 [Gating] SW mode calibration
1442 13:31:09.588465 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1443 13:31:09.591803 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1444 13:31:09.598343 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1445 13:31:09.601670 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1446 13:31:09.605094 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1447 13:31:09.611850 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 13:31:09.615370 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 13:31:09.618380 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 13:31:09.621830 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 13:31:09.628724 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 13:31:09.632152 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 13:31:09.635462 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 13:31:09.642137 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 13:31:09.645552 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 13:31:09.648538 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 13:31:09.655488 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 13:31:09.659028 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 13:31:09.661885 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 13:31:09.668536 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1461 13:31:09.672147 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1462 13:31:09.675486 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 13:31:09.682320 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 13:31:09.685391 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 13:31:09.689214 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 13:31:09.695523 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 13:31:09.698799 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 13:31:09.702125 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 13:31:09.705687 0 9 4 | B1->B0 | 2323 2828 | 1 1 | (1 1) (1 1)
1470 13:31:09.712114 0 9 8 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1471 13:31:09.715448 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1472 13:31:09.718855 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 13:31:09.725579 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 13:31:09.729109 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 13:31:09.732502 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 13:31:09.739075 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1477 13:31:09.742277 0 10 4 | B1->B0 | 2828 2828 | 1 0 | (1 0) (0 0)
1478 13:31:09.745785 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 13:31:09.752491 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 13:31:09.755660 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 13:31:09.759106 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 13:31:09.765885 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 13:31:09.769181 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 13:31:09.772219 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 13:31:09.775531 0 11 4 | B1->B0 | 2c2c 3838 | 0 0 | (0 0) (1 1)
1486 13:31:09.782526 0 11 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1487 13:31:09.785824 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1488 13:31:09.788899 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 13:31:09.795799 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 13:31:09.799018 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 13:31:09.802614 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 13:31:09.809216 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 13:31:09.812649 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1494 13:31:09.815567 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 13:31:09.822183 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 13:31:09.825702 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 13:31:09.829096 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 13:31:09.835464 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 13:31:09.838862 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 13:31:09.842344 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 13:31:09.849013 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 13:31:09.852372 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 13:31:09.855739 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 13:31:09.862342 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 13:31:09.865794 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 13:31:09.868792 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 13:31:09.872382 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 13:31:09.879342 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1509 13:31:09.882531 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1510 13:31:09.885706 Total UI for P1: 0, mck2ui 16
1511 13:31:09.889238 best dqsien dly found for B0: ( 0, 14, 0)
1512 13:31:09.892235 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1513 13:31:09.898921 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 13:31:09.899005 Total UI for P1: 0, mck2ui 16
1515 13:31:09.905572 best dqsien dly found for B1: ( 0, 14, 6)
1516 13:31:09.909112 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1517 13:31:09.912399 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1518 13:31:09.912484
1519 13:31:09.915966 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1520 13:31:09.919310 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1521 13:31:09.922829 [Gating] SW calibration Done
1522 13:31:09.922940 ==
1523 13:31:09.926167 Dram Type= 6, Freq= 0, CH_1, rank 0
1524 13:31:09.929023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1525 13:31:09.929147 ==
1526 13:31:09.932518 RX Vref Scan: 0
1527 13:31:09.932641
1528 13:31:09.932783 RX Vref 0 -> 0, step: 1
1529 13:31:09.932916
1530 13:31:09.935879 RX Delay -130 -> 252, step: 16
1531 13:31:09.939476 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1532 13:31:09.945772 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1533 13:31:09.949052 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1534 13:31:09.952559 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1535 13:31:09.955997 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1536 13:31:09.959045 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1537 13:31:09.966146 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1538 13:31:09.969103 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1539 13:31:09.972582 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1540 13:31:09.975953 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1541 13:31:09.979308 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1542 13:31:09.986103 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1543 13:31:09.989149 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1544 13:31:09.992596 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1545 13:31:09.996025 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1546 13:31:09.999225 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1547 13:31:09.999326 ==
1548 13:31:10.002344 Dram Type= 6, Freq= 0, CH_1, rank 0
1549 13:31:10.009431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1550 13:31:10.009514 ==
1551 13:31:10.009594 DQS Delay:
1552 13:31:10.012451 DQS0 = 0, DQS1 = 0
1553 13:31:10.012525 DQM Delay:
1554 13:31:10.012588 DQM0 = 92, DQM1 = 85
1555 13:31:10.015931 DQ Delay:
1556 13:31:10.019108 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1557 13:31:10.022584 DQ4 =93, DQ5 =101, DQ6 =101, DQ7 =93
1558 13:31:10.026030 DQ8 =69, DQ9 =69, DQ10 =93, DQ11 =77
1559 13:31:10.029378 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1560 13:31:10.029467
1561 13:31:10.029535
1562 13:31:10.029599 ==
1563 13:31:10.032742 Dram Type= 6, Freq= 0, CH_1, rank 0
1564 13:31:10.035907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1565 13:31:10.035992 ==
1566 13:31:10.036063
1567 13:31:10.036126
1568 13:31:10.039270 TX Vref Scan disable
1569 13:31:10.042701 == TX Byte 0 ==
1570 13:31:10.045702 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1571 13:31:10.049176 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1572 13:31:10.052971 == TX Byte 1 ==
1573 13:31:10.056390 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1574 13:31:10.059418 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1575 13:31:10.059501 ==
1576 13:31:10.062789 Dram Type= 6, Freq= 0, CH_1, rank 0
1577 13:31:10.066020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1578 13:31:10.066114 ==
1579 13:31:10.080196 TX Vref=22, minBit 8, minWin=27, winSum=447
1580 13:31:10.083572 TX Vref=24, minBit 8, minWin=27, winSum=449
1581 13:31:10.086882 TX Vref=26, minBit 1, minWin=28, winSum=456
1582 13:31:10.090117 TX Vref=28, minBit 1, minWin=28, winSum=456
1583 13:31:10.093278 TX Vref=30, minBit 8, minWin=28, winSum=459
1584 13:31:10.096966 TX Vref=32, minBit 12, minWin=27, winSum=457
1585 13:31:10.103399 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 30
1586 13:31:10.103484
1587 13:31:10.106949 Final TX Range 1 Vref 30
1588 13:31:10.107033
1589 13:31:10.107098 ==
1590 13:31:10.110072 Dram Type= 6, Freq= 0, CH_1, rank 0
1591 13:31:10.113269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1592 13:31:10.113352 ==
1593 13:31:10.113417
1594 13:31:10.117432
1595 13:31:10.117514 TX Vref Scan disable
1596 13:31:10.120980 == TX Byte 0 ==
1597 13:31:10.124190 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1598 13:31:10.127551 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1599 13:31:10.131141 == TX Byte 1 ==
1600 13:31:10.133981 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1601 13:31:10.137360 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1602 13:31:10.137445
1603 13:31:10.141076 [DATLAT]
1604 13:31:10.141159 Freq=800, CH1 RK0
1605 13:31:10.141225
1606 13:31:10.144643 DATLAT Default: 0xa
1607 13:31:10.144761 0, 0xFFFF, sum = 0
1608 13:31:10.147483 1, 0xFFFF, sum = 0
1609 13:31:10.147567 2, 0xFFFF, sum = 0
1610 13:31:10.150902 3, 0xFFFF, sum = 0
1611 13:31:10.150987 4, 0xFFFF, sum = 0
1612 13:31:10.154402 5, 0xFFFF, sum = 0
1613 13:31:10.154487 6, 0xFFFF, sum = 0
1614 13:31:10.157729 7, 0xFFFF, sum = 0
1615 13:31:10.157813 8, 0xFFFF, sum = 0
1616 13:31:10.160853 9, 0x0, sum = 1
1617 13:31:10.160937 10, 0x0, sum = 2
1618 13:31:10.164489 11, 0x0, sum = 3
1619 13:31:10.164573 12, 0x0, sum = 4
1620 13:31:10.164641 best_step = 10
1621 13:31:10.167916
1622 13:31:10.168029 ==
1623 13:31:10.171211 Dram Type= 6, Freq= 0, CH_1, rank 0
1624 13:31:10.174169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1625 13:31:10.174253 ==
1626 13:31:10.174319 RX Vref Scan: 1
1627 13:31:10.174391
1628 13:31:10.178083 Set Vref Range= 32 -> 127
1629 13:31:10.178166
1630 13:31:10.181251 RX Vref 32 -> 127, step: 1
1631 13:31:10.181334
1632 13:31:10.184272 RX Delay -95 -> 252, step: 8
1633 13:31:10.184382
1634 13:31:10.187761 Set Vref, RX VrefLevel [Byte0]: 32
1635 13:31:10.191158 [Byte1]: 32
1636 13:31:10.191242
1637 13:31:10.194624 Set Vref, RX VrefLevel [Byte0]: 33
1638 13:31:10.198257 [Byte1]: 33
1639 13:31:10.198343
1640 13:31:10.201251 Set Vref, RX VrefLevel [Byte0]: 34
1641 13:31:10.204554 [Byte1]: 34
1642 13:31:10.208242
1643 13:31:10.208327 Set Vref, RX VrefLevel [Byte0]: 35
1644 13:31:10.211133 [Byte1]: 35
1645 13:31:10.215534
1646 13:31:10.215619 Set Vref, RX VrefLevel [Byte0]: 36
1647 13:31:10.221953 [Byte1]: 36
1648 13:31:10.222039
1649 13:31:10.225097 Set Vref, RX VrefLevel [Byte0]: 37
1650 13:31:10.228621 [Byte1]: 37
1651 13:31:10.228756
1652 13:31:10.232178 Set Vref, RX VrefLevel [Byte0]: 38
1653 13:31:10.235054 [Byte1]: 38
1654 13:31:10.235185
1655 13:31:10.238795 Set Vref, RX VrefLevel [Byte0]: 39
1656 13:31:10.241825 [Byte1]: 39
1657 13:31:10.245822
1658 13:31:10.245946 Set Vref, RX VrefLevel [Byte0]: 40
1659 13:31:10.249083 [Byte1]: 40
1660 13:31:10.253571
1661 13:31:10.253697 Set Vref, RX VrefLevel [Byte0]: 41
1662 13:31:10.257006 [Byte1]: 41
1663 13:31:10.261210
1664 13:31:10.261333 Set Vref, RX VrefLevel [Byte0]: 42
1665 13:31:10.264588 [Byte1]: 42
1666 13:31:10.269012
1667 13:31:10.269142 Set Vref, RX VrefLevel [Byte0]: 43
1668 13:31:10.271885 [Byte1]: 43
1669 13:31:10.276364
1670 13:31:10.276492 Set Vref, RX VrefLevel [Byte0]: 44
1671 13:31:10.279818 [Byte1]: 44
1672 13:31:10.284096
1673 13:31:10.284217 Set Vref, RX VrefLevel [Byte0]: 45
1674 13:31:10.286955 [Byte1]: 45
1675 13:31:10.291677
1676 13:31:10.291752 Set Vref, RX VrefLevel [Byte0]: 46
1677 13:31:10.295069 [Byte1]: 46
1678 13:31:10.298966
1679 13:31:10.299075 Set Vref, RX VrefLevel [Byte0]: 47
1680 13:31:10.302385 [Byte1]: 47
1681 13:31:10.306516
1682 13:31:10.306643 Set Vref, RX VrefLevel [Byte0]: 48
1683 13:31:10.310433 [Byte1]: 48
1684 13:31:10.314216
1685 13:31:10.314312 Set Vref, RX VrefLevel [Byte0]: 49
1686 13:31:10.317378 [Byte1]: 49
1687 13:31:10.321954
1688 13:31:10.322122 Set Vref, RX VrefLevel [Byte0]: 50
1689 13:31:10.325511 [Byte1]: 50
1690 13:31:10.329559
1691 13:31:10.329644 Set Vref, RX VrefLevel [Byte0]: 51
1692 13:31:10.332670 [Byte1]: 51
1693 13:31:10.336918
1694 13:31:10.337033 Set Vref, RX VrefLevel [Byte0]: 52
1695 13:31:10.340257 [Byte1]: 52
1696 13:31:10.344879
1697 13:31:10.344964 Set Vref, RX VrefLevel [Byte0]: 53
1698 13:31:10.347859 [Byte1]: 53
1699 13:31:10.352215
1700 13:31:10.352299 Set Vref, RX VrefLevel [Byte0]: 54
1701 13:31:10.355659 [Byte1]: 54
1702 13:31:10.360018
1703 13:31:10.360102 Set Vref, RX VrefLevel [Byte0]: 55
1704 13:31:10.362961 [Byte1]: 55
1705 13:31:10.367554
1706 13:31:10.367637 Set Vref, RX VrefLevel [Byte0]: 56
1707 13:31:10.370493 [Byte1]: 56
1708 13:31:10.375315
1709 13:31:10.375396 Set Vref, RX VrefLevel [Byte0]: 57
1710 13:31:10.378644 [Byte1]: 57
1711 13:31:10.382924
1712 13:31:10.383007 Set Vref, RX VrefLevel [Byte0]: 58
1713 13:31:10.385755 [Byte1]: 58
1714 13:31:10.390220
1715 13:31:10.390345 Set Vref, RX VrefLevel [Byte0]: 59
1716 13:31:10.393625 [Byte1]: 59
1717 13:31:10.397686
1718 13:31:10.397812 Set Vref, RX VrefLevel [Byte0]: 60
1719 13:31:10.401360 [Byte1]: 60
1720 13:31:10.405252
1721 13:31:10.405374 Set Vref, RX VrefLevel [Byte0]: 61
1722 13:31:10.408718 [Byte1]: 61
1723 13:31:10.412967
1724 13:31:10.413090 Set Vref, RX VrefLevel [Byte0]: 62
1725 13:31:10.416438 [Byte1]: 62
1726 13:31:10.420866
1727 13:31:10.420988 Set Vref, RX VrefLevel [Byte0]: 63
1728 13:31:10.423793 [Byte1]: 63
1729 13:31:10.428533
1730 13:31:10.428660 Set Vref, RX VrefLevel [Byte0]: 64
1731 13:31:10.431439 [Byte1]: 64
1732 13:31:10.435647
1733 13:31:10.435768 Set Vref, RX VrefLevel [Byte0]: 65
1734 13:31:10.439232 [Byte1]: 65
1735 13:31:10.443427
1736 13:31:10.443538 Set Vref, RX VrefLevel [Byte0]: 66
1737 13:31:10.446807 [Byte1]: 66
1738 13:31:10.451200
1739 13:31:10.451289 Set Vref, RX VrefLevel [Byte0]: 67
1740 13:31:10.454781 [Byte1]: 67
1741 13:31:10.458541
1742 13:31:10.458655 Set Vref, RX VrefLevel [Byte0]: 68
1743 13:31:10.461910 [Byte1]: 68
1744 13:31:10.466347
1745 13:31:10.466429 Set Vref, RX VrefLevel [Byte0]: 69
1746 13:31:10.469813 [Byte1]: 69
1747 13:31:10.474029
1748 13:31:10.474134 Set Vref, RX VrefLevel [Byte0]: 70
1749 13:31:10.477530 [Byte1]: 70
1750 13:31:10.481324
1751 13:31:10.481430 Set Vref, RX VrefLevel [Byte0]: 71
1752 13:31:10.484627 [Byte1]: 71
1753 13:31:10.489015
1754 13:31:10.489124 Set Vref, RX VrefLevel [Byte0]: 72
1755 13:31:10.492458 [Byte1]: 72
1756 13:31:10.496713
1757 13:31:10.496841 Set Vref, RX VrefLevel [Byte0]: 73
1758 13:31:10.500159 [Byte1]: 73
1759 13:31:10.504216
1760 13:31:10.504302 Set Vref, RX VrefLevel [Byte0]: 74
1761 13:31:10.507575 [Byte1]: 74
1762 13:31:10.511734
1763 13:31:10.511837 Set Vref, RX VrefLevel [Byte0]: 75
1764 13:31:10.515178 [Byte1]: 75
1765 13:31:10.519494
1766 13:31:10.519611 Set Vref, RX VrefLevel [Byte0]: 76
1767 13:31:10.522604 [Byte1]: 76
1768 13:31:10.527298
1769 13:31:10.527398 Set Vref, RX VrefLevel [Byte0]: 77
1770 13:31:10.530285 [Byte1]: 77
1771 13:31:10.534747
1772 13:31:10.534859 Set Vref, RX VrefLevel [Byte0]: 78
1773 13:31:10.537874 [Byte1]: 78
1774 13:31:10.542082
1775 13:31:10.542214 Final RX Vref Byte 0 = 53 to rank0
1776 13:31:10.545637 Final RX Vref Byte 1 = 60 to rank0
1777 13:31:10.548634 Final RX Vref Byte 0 = 53 to rank1
1778 13:31:10.552346 Final RX Vref Byte 1 = 60 to rank1==
1779 13:31:10.555456 Dram Type= 6, Freq= 0, CH_1, rank 0
1780 13:31:10.561890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1781 13:31:10.562043 ==
1782 13:31:10.562196 DQS Delay:
1783 13:31:10.562319 DQS0 = 0, DQS1 = 0
1784 13:31:10.565216 DQM Delay:
1785 13:31:10.565304 DQM0 = 91, DQM1 = 81
1786 13:31:10.568920 DQ Delay:
1787 13:31:10.572037 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
1788 13:31:10.575390 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =84
1789 13:31:10.578949 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =76
1790 13:31:10.582182 DQ12 =92, DQ13 =88, DQ14 =84, DQ15 =88
1791 13:31:10.582258
1792 13:31:10.582322
1793 13:31:10.588779 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d4a, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1794 13:31:10.592209 CH1 RK0: MR19=606, MR18=2D4A
1795 13:31:10.598766 CH1_RK0: MR19=0x606, MR18=0x2D4A, DQSOSC=391, MR23=63, INC=96, DEC=64
1796 13:31:10.598877
1797 13:31:10.602136 ----->DramcWriteLeveling(PI) begin...
1798 13:31:10.602251 ==
1799 13:31:10.605581 Dram Type= 6, Freq= 0, CH_1, rank 1
1800 13:31:10.608772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1801 13:31:10.608886 ==
1802 13:31:10.611915 Write leveling (Byte 0): 26 => 26
1803 13:31:10.615349 Write leveling (Byte 1): 30 => 30
1804 13:31:10.618700 DramcWriteLeveling(PI) end<-----
1805 13:31:10.618825
1806 13:31:10.618940 ==
1807 13:31:10.621974 Dram Type= 6, Freq= 0, CH_1, rank 1
1808 13:31:10.625460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1809 13:31:10.625584 ==
1810 13:31:10.628822 [Gating] SW mode calibration
1811 13:31:10.635360 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1812 13:31:10.642321 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1813 13:31:10.645849 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1814 13:31:10.648703 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1815 13:31:10.655281 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 13:31:10.659047 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 13:31:10.662007 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 13:31:10.668758 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 13:31:10.672196 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 13:31:10.675597 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 13:31:10.682328 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 13:31:10.685895 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 13:31:10.688796 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 13:31:10.695603 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 13:31:10.699185 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 13:31:10.702572 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 13:31:10.705938 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 13:31:10.712691 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 13:31:10.716063 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1830 13:31:10.719227 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1831 13:31:10.725892 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1832 13:31:10.729488 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 13:31:10.732477 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 13:31:10.739229 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 13:31:10.742527 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 13:31:10.745988 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 13:31:10.752659 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 13:31:10.755819 0 9 4 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
1839 13:31:10.759159 0 9 8 | B1->B0 | 3434 3232 | 0 1 | (0 0) (1 1)
1840 13:31:10.765668 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 13:31:10.769189 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 13:31:10.772306 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 13:31:10.776070 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 13:31:10.782582 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 13:31:10.786037 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 13:31:10.789433 0 10 4 | B1->B0 | 2f2f 2f2f | 0 1 | (0 0) (1 0)
1847 13:31:10.795924 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 13:31:10.799176 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 13:31:10.802347 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 13:31:10.809243 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 13:31:10.812573 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 13:31:10.815989 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 13:31:10.822773 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 13:31:10.826091 0 11 4 | B1->B0 | 2f2f 2929 | 1 1 | (0 0) (0 0)
1855 13:31:10.829273 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 13:31:10.835983 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 13:31:10.839290 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 13:31:10.842912 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 13:31:10.845932 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 13:31:10.853137 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 13:31:10.856175 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 13:31:10.859644 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1863 13:31:10.865997 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1864 13:31:10.869548 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 13:31:10.872636 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 13:31:10.879749 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 13:31:10.882955 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 13:31:10.886827 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 13:31:10.893311 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 13:31:10.896306 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 13:31:10.899990 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 13:31:10.906798 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 13:31:10.909605 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 13:31:10.913144 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 13:31:10.919587 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 13:31:10.922835 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 13:31:10.926265 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 13:31:10.929729 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1879 13:31:10.933030 Total UI for P1: 0, mck2ui 16
1880 13:31:10.936395 best dqsien dly found for B0: ( 0, 14, 2)
1881 13:31:10.939692 Total UI for P1: 0, mck2ui 16
1882 13:31:10.943323 best dqsien dly found for B1: ( 0, 14, 2)
1883 13:31:10.946509 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1884 13:31:10.949859 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1885 13:31:10.952938
1886 13:31:10.956318 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1887 13:31:10.959757 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1888 13:31:10.963194 [Gating] SW calibration Done
1889 13:31:10.963277 ==
1890 13:31:10.966259 Dram Type= 6, Freq= 0, CH_1, rank 1
1891 13:31:10.969600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1892 13:31:10.969705 ==
1893 13:31:10.969773 RX Vref Scan: 0
1894 13:31:10.969836
1895 13:31:10.972985 RX Vref 0 -> 0, step: 1
1896 13:31:10.973063
1897 13:31:10.976304 RX Delay -130 -> 252, step: 16
1898 13:31:10.979624 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1899 13:31:10.982899 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1900 13:31:10.989577 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1901 13:31:10.992918 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1902 13:31:10.996733 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1903 13:31:10.999500 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1904 13:31:11.003266 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1905 13:31:11.006532 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1906 13:31:11.013174 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1907 13:31:11.016677 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1908 13:31:11.020331 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1909 13:31:11.023212 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1910 13:31:11.026563 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1911 13:31:11.033035 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1912 13:31:11.036345 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1913 13:31:11.039936 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1914 13:31:11.040010 ==
1915 13:31:11.043234 Dram Type= 6, Freq= 0, CH_1, rank 1
1916 13:31:11.046562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1917 13:31:11.046645 ==
1918 13:31:11.050202 DQS Delay:
1919 13:31:11.050311 DQS0 = 0, DQS1 = 0
1920 13:31:11.053548 DQM Delay:
1921 13:31:11.053629 DQM0 = 89, DQM1 = 81
1922 13:31:11.053700 DQ Delay:
1923 13:31:11.056502 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1924 13:31:11.059951 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =85
1925 13:31:11.063337 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1926 13:31:11.066483 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =93
1927 13:31:11.066591
1928 13:31:11.066683
1929 13:31:11.069882 ==
1930 13:31:11.069964 Dram Type= 6, Freq= 0, CH_1, rank 1
1931 13:31:11.076700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1932 13:31:11.076823 ==
1933 13:31:11.076889
1934 13:31:11.076949
1935 13:31:11.080204 TX Vref Scan disable
1936 13:31:11.080288 == TX Byte 0 ==
1937 13:31:11.083275 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1938 13:31:11.090247 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1939 13:31:11.090364 == TX Byte 1 ==
1940 13:31:11.093308 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1941 13:31:11.100362 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1942 13:31:11.100475 ==
1943 13:31:11.103283 Dram Type= 6, Freq= 0, CH_1, rank 1
1944 13:31:11.106749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1945 13:31:11.106862 ==
1946 13:31:11.119981 TX Vref=22, minBit 13, minWin=27, winSum=453
1947 13:31:11.123360 TX Vref=24, minBit 15, minWin=27, winSum=454
1948 13:31:11.126952 TX Vref=26, minBit 15, minWin=27, winSum=457
1949 13:31:11.129878 TX Vref=28, minBit 8, minWin=28, winSum=459
1950 13:31:11.133341 TX Vref=30, minBit 8, minWin=28, winSum=459
1951 13:31:11.140151 TX Vref=32, minBit 8, minWin=28, winSum=458
1952 13:31:11.143203 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 28
1953 13:31:11.143310
1954 13:31:11.147085 Final TX Range 1 Vref 28
1955 13:31:11.147192
1956 13:31:11.147297 ==
1957 13:31:11.149894 Dram Type= 6, Freq= 0, CH_1, rank 1
1958 13:31:11.153443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1959 13:31:11.153556 ==
1960 13:31:11.156786
1961 13:31:11.156892
1962 13:31:11.156998 TX Vref Scan disable
1963 13:31:11.160063 == TX Byte 0 ==
1964 13:31:11.163521 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1965 13:31:11.166779 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1966 13:31:11.170110 == TX Byte 1 ==
1967 13:31:11.173936 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1968 13:31:11.176883 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1969 13:31:11.180602
1970 13:31:11.180686 [DATLAT]
1971 13:31:11.180762 Freq=800, CH1 RK1
1972 13:31:11.180827
1973 13:31:11.183383 DATLAT Default: 0xa
1974 13:31:11.183467 0, 0xFFFF, sum = 0
1975 13:31:11.186653 1, 0xFFFF, sum = 0
1976 13:31:11.186773 2, 0xFFFF, sum = 0
1977 13:31:11.190049 3, 0xFFFF, sum = 0
1978 13:31:11.190136 4, 0xFFFF, sum = 0
1979 13:31:11.193754 5, 0xFFFF, sum = 0
1980 13:31:11.193835 6, 0xFFFF, sum = 0
1981 13:31:11.196898 7, 0xFFFF, sum = 0
1982 13:31:11.200209 8, 0xFFFF, sum = 0
1983 13:31:11.200324 9, 0x0, sum = 1
1984 13:31:11.200424 10, 0x0, sum = 2
1985 13:31:11.203758 11, 0x0, sum = 3
1986 13:31:11.203861 12, 0x0, sum = 4
1987 13:31:11.207088 best_step = 10
1988 13:31:11.207199
1989 13:31:11.207305 ==
1990 13:31:11.210434 Dram Type= 6, Freq= 0, CH_1, rank 1
1991 13:31:11.213610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1992 13:31:11.213715 ==
1993 13:31:11.216873 RX Vref Scan: 0
1994 13:31:11.216979
1995 13:31:11.217081 RX Vref 0 -> 0, step: 1
1996 13:31:11.217185
1997 13:31:11.220157 RX Delay -95 -> 252, step: 8
1998 13:31:11.226765 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
1999 13:31:11.230162 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2000 13:31:11.233559 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2001 13:31:11.237125 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2002 13:31:11.240095 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2003 13:31:11.247000 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2004 13:31:11.249965 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2005 13:31:11.253775 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2006 13:31:11.256828 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2007 13:31:11.260158 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2008 13:31:11.266822 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2009 13:31:11.270210 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2010 13:31:11.273486 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2011 13:31:11.276813 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2012 13:31:11.280435 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2013 13:31:11.287110 iDelay=209, Bit 15, Center 92 (-23 ~ 208) 232
2014 13:31:11.287197 ==
2015 13:31:11.290321 Dram Type= 6, Freq= 0, CH_1, rank 1
2016 13:31:11.293738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2017 13:31:11.293832 ==
2018 13:31:11.293926 DQS Delay:
2019 13:31:11.297259 DQS0 = 0, DQS1 = 0
2020 13:31:11.297343 DQM Delay:
2021 13:31:11.300418 DQM0 = 92, DQM1 = 83
2022 13:31:11.300501 DQ Delay:
2023 13:31:11.303537 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2024 13:31:11.307185 DQ4 =92, DQ5 =108, DQ6 =96, DQ7 =88
2025 13:31:11.310537 DQ8 =68, DQ9 =76, DQ10 =84, DQ11 =80
2026 13:31:11.313812 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =92
2027 13:31:11.313895
2028 13:31:11.313961
2029 13:31:11.321134 [DQSOSCAuto] RK1, (LSB)MR18= 0x370c, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
2030 13:31:11.323856 CH1 RK1: MR19=606, MR18=370C
2031 13:31:11.330653 CH1_RK1: MR19=0x606, MR18=0x370C, DQSOSC=395, MR23=63, INC=94, DEC=63
2032 13:31:11.333646 [RxdqsGatingPostProcess] freq 800
2033 13:31:11.340443 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2034 13:31:11.340553 Pre-setting of DQS Precalculation
2035 13:31:11.347164 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2036 13:31:11.353834 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2037 13:31:11.360616 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2038 13:31:11.360723
2039 13:31:11.360818
2040 13:31:11.363683 [Calibration Summary] 1600 Mbps
2041 13:31:11.367163 CH 0, Rank 0
2042 13:31:11.367249 SW Impedance : PASS
2043 13:31:11.370549 DUTY Scan : NO K
2044 13:31:11.370643 ZQ Calibration : PASS
2045 13:31:11.374140 Jitter Meter : NO K
2046 13:31:11.377154 CBT Training : PASS
2047 13:31:11.377246 Write leveling : PASS
2048 13:31:11.380553 RX DQS gating : PASS
2049 13:31:11.383981 RX DQ/DQS(RDDQC) : PASS
2050 13:31:11.384066 TX DQ/DQS : PASS
2051 13:31:11.387384 RX DATLAT : PASS
2052 13:31:11.390701 RX DQ/DQS(Engine): PASS
2053 13:31:11.390807 TX OE : NO K
2054 13:31:11.393931 All Pass.
2055 13:31:11.394009
2056 13:31:11.394108 CH 0, Rank 1
2057 13:31:11.397038 SW Impedance : PASS
2058 13:31:11.397148 DUTY Scan : NO K
2059 13:31:11.400446 ZQ Calibration : PASS
2060 13:31:11.404023 Jitter Meter : NO K
2061 13:31:11.404119 CBT Training : PASS
2062 13:31:11.407195 Write leveling : PASS
2063 13:31:11.407287 RX DQS gating : PASS
2064 13:31:11.411083 RX DQ/DQS(RDDQC) : PASS
2065 13:31:11.414030 TX DQ/DQS : PASS
2066 13:31:11.414199 RX DATLAT : PASS
2067 13:31:11.417687 RX DQ/DQS(Engine): PASS
2068 13:31:11.420756 TX OE : NO K
2069 13:31:11.420908 All Pass.
2070 13:31:11.421076
2071 13:31:11.421202 CH 1, Rank 0
2072 13:31:11.424098 SW Impedance : PASS
2073 13:31:11.427545 DUTY Scan : NO K
2074 13:31:11.427627 ZQ Calibration : PASS
2075 13:31:11.430729 Jitter Meter : NO K
2076 13:31:11.434067 CBT Training : PASS
2077 13:31:11.434195 Write leveling : PASS
2078 13:31:11.437636 RX DQS gating : PASS
2079 13:31:11.440508 RX DQ/DQS(RDDQC) : PASS
2080 13:31:11.440631 TX DQ/DQS : PASS
2081 13:31:11.443965 RX DATLAT : PASS
2082 13:31:11.444091 RX DQ/DQS(Engine): PASS
2083 13:31:11.447367 TX OE : NO K
2084 13:31:11.447494 All Pass.
2085 13:31:11.447611
2086 13:31:11.450862 CH 1, Rank 1
2087 13:31:11.450988 SW Impedance : PASS
2088 13:31:11.454251 DUTY Scan : NO K
2089 13:31:11.457612 ZQ Calibration : PASS
2090 13:31:11.457738 Jitter Meter : NO K
2091 13:31:11.460686 CBT Training : PASS
2092 13:31:11.464194 Write leveling : PASS
2093 13:31:11.464315 RX DQS gating : PASS
2094 13:31:11.467575 RX DQ/DQS(RDDQC) : PASS
2095 13:31:11.471073 TX DQ/DQS : PASS
2096 13:31:11.471198 RX DATLAT : PASS
2097 13:31:11.473835 RX DQ/DQS(Engine): PASS
2098 13:31:11.477215 TX OE : NO K
2099 13:31:11.477322 All Pass.
2100 13:31:11.477417
2101 13:31:11.480619 DramC Write-DBI off
2102 13:31:11.480717 PER_BANK_REFRESH: Hybrid Mode
2103 13:31:11.483812 TX_TRACKING: ON
2104 13:31:11.487107 [GetDramInforAfterCalByMRR] Vendor 6.
2105 13:31:11.490366 [GetDramInforAfterCalByMRR] Revision 606.
2106 13:31:11.493918 [GetDramInforAfterCalByMRR] Revision 2 0.
2107 13:31:11.494036 MR0 0x3b3b
2108 13:31:11.497088 MR8 0x5151
2109 13:31:11.500761 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2110 13:31:11.500854
2111 13:31:11.500930 MR0 0x3b3b
2112 13:31:11.500993 MR8 0x5151
2113 13:31:11.507496 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2114 13:31:11.507581
2115 13:31:11.513883 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2116 13:31:11.517701 [FAST_K] Save calibration result to emmc
2117 13:31:11.520473 [FAST_K] Save calibration result to emmc
2118 13:31:11.524248 dram_init: config_dvfs: 1
2119 13:31:11.527363 dramc_set_vcore_voltage set vcore to 662500
2120 13:31:11.530718 Read voltage for 1200, 2
2121 13:31:11.530847 Vio18 = 0
2122 13:31:11.534144 Vcore = 662500
2123 13:31:11.534270 Vdram = 0
2124 13:31:11.534385 Vddq = 0
2125 13:31:11.534496 Vmddr = 0
2126 13:31:11.540910 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2127 13:31:11.544368 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2128 13:31:11.547291 MEM_TYPE=3, freq_sel=15
2129 13:31:11.550878 sv_algorithm_assistance_LP4_1600
2130 13:31:11.554183 ============ PULL DRAM RESETB DOWN ============
2131 13:31:11.560886 ========== PULL DRAM RESETB DOWN end =========
2132 13:31:11.564023 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2133 13:31:11.567764 ===================================
2134 13:31:11.571358 LPDDR4 DRAM CONFIGURATION
2135 13:31:11.574416 ===================================
2136 13:31:11.574501 EX_ROW_EN[0] = 0x0
2137 13:31:11.577866 EX_ROW_EN[1] = 0x0
2138 13:31:11.577991 LP4Y_EN = 0x0
2139 13:31:11.580765 WORK_FSP = 0x0
2140 13:31:11.580892 WL = 0x4
2141 13:31:11.584199 RL = 0x4
2142 13:31:11.584303 BL = 0x2
2143 13:31:11.587503 RPST = 0x0
2144 13:31:11.587620 RD_PRE = 0x0
2145 13:31:11.590965 WR_PRE = 0x1
2146 13:31:11.591070 WR_PST = 0x0
2147 13:31:11.594438 DBI_WR = 0x0
2148 13:31:11.594568 DBI_RD = 0x0
2149 13:31:11.597377 OTF = 0x1
2150 13:31:11.600799 ===================================
2151 13:31:11.604486 ===================================
2152 13:31:11.604601 ANA top config
2153 13:31:11.607837 ===================================
2154 13:31:11.610864 DLL_ASYNC_EN = 0
2155 13:31:11.614609 ALL_SLAVE_EN = 0
2156 13:31:11.617792 NEW_RANK_MODE = 1
2157 13:31:11.617902 DLL_IDLE_MODE = 1
2158 13:31:11.621104 LP45_APHY_COMB_EN = 1
2159 13:31:11.624406 TX_ODT_DIS = 1
2160 13:31:11.627486 NEW_8X_MODE = 1
2161 13:31:11.630822 ===================================
2162 13:31:11.634448 ===================================
2163 13:31:11.637854 data_rate = 2400
2164 13:31:11.637960 CKR = 1
2165 13:31:11.641072 DQ_P2S_RATIO = 8
2166 13:31:11.644541 ===================================
2167 13:31:11.648055 CA_P2S_RATIO = 8
2168 13:31:11.651314 DQ_CA_OPEN = 0
2169 13:31:11.654389 DQ_SEMI_OPEN = 0
2170 13:31:11.654494 CA_SEMI_OPEN = 0
2171 13:31:11.658076 CA_FULL_RATE = 0
2172 13:31:11.661472 DQ_CKDIV4_EN = 0
2173 13:31:11.664594 CA_CKDIV4_EN = 0
2174 13:31:11.667836 CA_PREDIV_EN = 0
2175 13:31:11.671603 PH8_DLY = 17
2176 13:31:11.671718 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2177 13:31:11.674452 DQ_AAMCK_DIV = 4
2178 13:31:11.677877 CA_AAMCK_DIV = 4
2179 13:31:11.681213 CA_ADMCK_DIV = 4
2180 13:31:11.684593 DQ_TRACK_CA_EN = 0
2181 13:31:11.687921 CA_PICK = 1200
2182 13:31:11.691182 CA_MCKIO = 1200
2183 13:31:11.691285 MCKIO_SEMI = 0
2184 13:31:11.694618 PLL_FREQ = 2366
2185 13:31:11.697910 DQ_UI_PI_RATIO = 32
2186 13:31:11.701137 CA_UI_PI_RATIO = 0
2187 13:31:11.704719 ===================================
2188 13:31:11.708021 ===================================
2189 13:31:11.711183 memory_type:LPDDR4
2190 13:31:11.711272 GP_NUM : 10
2191 13:31:11.714826 SRAM_EN : 1
2192 13:31:11.714937 MD32_EN : 0
2193 13:31:11.717962 ===================================
2194 13:31:11.721535 [ANA_INIT] >>>>>>>>>>>>>>
2195 13:31:11.724949 <<<<<< [CONFIGURE PHASE]: ANA_TX
2196 13:31:11.727743 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2197 13:31:11.731402 ===================================
2198 13:31:11.734791 data_rate = 2400,PCW = 0X5b00
2199 13:31:11.738408 ===================================
2200 13:31:11.741252 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2201 13:31:11.748307 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2202 13:31:11.751619 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2203 13:31:11.758578 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2204 13:31:11.761429 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2205 13:31:11.764721 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2206 13:31:11.764822 [ANA_INIT] flow start
2207 13:31:11.768280 [ANA_INIT] PLL >>>>>>>>
2208 13:31:11.771728 [ANA_INIT] PLL <<<<<<<<
2209 13:31:11.771815 [ANA_INIT] MIDPI >>>>>>>>
2210 13:31:11.774959 [ANA_INIT] MIDPI <<<<<<<<
2211 13:31:11.778149 [ANA_INIT] DLL >>>>>>>>
2212 13:31:11.778240 [ANA_INIT] DLL <<<<<<<<
2213 13:31:11.781387 [ANA_INIT] flow end
2214 13:31:11.785166 ============ LP4 DIFF to SE enter ============
2215 13:31:11.787923 ============ LP4 DIFF to SE exit ============
2216 13:31:11.791234 [ANA_INIT] <<<<<<<<<<<<<
2217 13:31:11.794897 [Flow] Enable top DCM control >>>>>
2218 13:31:11.798349 [Flow] Enable top DCM control <<<<<
2219 13:31:11.801746 Enable DLL master slave shuffle
2220 13:31:11.808045 ==============================================================
2221 13:31:11.808130 Gating Mode config
2222 13:31:11.814752 ==============================================================
2223 13:31:11.814837 Config description:
2224 13:31:11.825230 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2225 13:31:11.831405 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2226 13:31:11.837745 SELPH_MODE 0: By rank 1: By Phase
2227 13:31:11.841334 ==============================================================
2228 13:31:11.844536 GAT_TRACK_EN = 1
2229 13:31:11.847757 RX_GATING_MODE = 2
2230 13:31:11.851331 RX_GATING_TRACK_MODE = 2
2231 13:31:11.854701 SELPH_MODE = 1
2232 13:31:11.858118 PICG_EARLY_EN = 1
2233 13:31:11.861689 VALID_LAT_VALUE = 1
2234 13:31:11.864587 ==============================================================
2235 13:31:11.871274 Enter into Gating configuration >>>>
2236 13:31:11.871376 Exit from Gating configuration <<<<
2237 13:31:11.874799 Enter into DVFS_PRE_config >>>>>
2238 13:31:11.888277 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2239 13:31:11.891546 Exit from DVFS_PRE_config <<<<<
2240 13:31:11.894840 Enter into PICG configuration >>>>
2241 13:31:11.898221 Exit from PICG configuration <<<<
2242 13:31:11.898322 [RX_INPUT] configuration >>>>>
2243 13:31:11.901552 [RX_INPUT] configuration <<<<<
2244 13:31:11.908261 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2245 13:31:11.911307 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2246 13:31:11.918244 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2247 13:31:11.924553 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2248 13:31:11.931285 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2249 13:31:11.938094 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2250 13:31:11.941493 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2251 13:31:11.944479 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2252 13:31:11.948074 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2253 13:31:11.954686 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2254 13:31:11.958069 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2255 13:31:11.961528 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2256 13:31:11.964856 ===================================
2257 13:31:11.968087 LPDDR4 DRAM CONFIGURATION
2258 13:31:11.971579 ===================================
2259 13:31:11.974995 EX_ROW_EN[0] = 0x0
2260 13:31:11.975100 EX_ROW_EN[1] = 0x0
2261 13:31:11.978659 LP4Y_EN = 0x0
2262 13:31:11.978766 WORK_FSP = 0x0
2263 13:31:11.981292 WL = 0x4
2264 13:31:11.981402 RL = 0x4
2265 13:31:11.984783 BL = 0x2
2266 13:31:11.984872 RPST = 0x0
2267 13:31:11.987927 RD_PRE = 0x0
2268 13:31:11.988029 WR_PRE = 0x1
2269 13:31:11.991545 WR_PST = 0x0
2270 13:31:11.991652 DBI_WR = 0x0
2271 13:31:11.994525 DBI_RD = 0x0
2272 13:31:11.994629 OTF = 0x1
2273 13:31:11.998609 ===================================
2274 13:31:12.001788 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2275 13:31:12.007973 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2276 13:31:12.011309 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2277 13:31:12.014737 ===================================
2278 13:31:12.018144 LPDDR4 DRAM CONFIGURATION
2279 13:31:12.021450 ===================================
2280 13:31:12.021531 EX_ROW_EN[0] = 0x10
2281 13:31:12.024907 EX_ROW_EN[1] = 0x0
2282 13:31:12.024982 LP4Y_EN = 0x0
2283 13:31:12.028302 WORK_FSP = 0x0
2284 13:31:12.031737 WL = 0x4
2285 13:31:12.031838 RL = 0x4
2286 13:31:12.035085 BL = 0x2
2287 13:31:12.035186 RPST = 0x0
2288 13:31:12.038555 RD_PRE = 0x0
2289 13:31:12.038654 WR_PRE = 0x1
2290 13:31:12.041785 WR_PST = 0x0
2291 13:31:12.041890 DBI_WR = 0x0
2292 13:31:12.044945 DBI_RD = 0x0
2293 13:31:12.045117 OTF = 0x1
2294 13:31:12.048056 ===================================
2295 13:31:12.054535 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2296 13:31:12.054648 ==
2297 13:31:12.057886 Dram Type= 6, Freq= 0, CH_0, rank 0
2298 13:31:12.061457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2299 13:31:12.061609 ==
2300 13:31:12.065095 [Duty_Offset_Calibration]
2301 13:31:12.068231 B0:2 B1:0 CA:1
2302 13:31:12.068414
2303 13:31:12.071566 [DutyScan_Calibration_Flow] k_type=0
2304 13:31:12.078935
2305 13:31:12.079044 ==CLK 0==
2306 13:31:12.081825 Final CLK duty delay cell = -4
2307 13:31:12.085493 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2308 13:31:12.088486 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2309 13:31:12.092067 [-4] AVG Duty = 4953%(X100)
2310 13:31:12.092149
2311 13:31:12.095209 CH0 CLK Duty spec in!! Max-Min= 156%
2312 13:31:12.098566 [DutyScan_Calibration_Flow] ====Done====
2313 13:31:12.098673
2314 13:31:12.101948 [DutyScan_Calibration_Flow] k_type=1
2315 13:31:12.117440
2316 13:31:12.117555 ==DQS 0 ==
2317 13:31:12.120874 Final DQS duty delay cell = 0
2318 13:31:12.124056 [0] MAX Duty = 5187%(X100), DQS PI = 30
2319 13:31:12.127474 [0] MIN Duty = 4938%(X100), DQS PI = 0
2320 13:31:12.127558 [0] AVG Duty = 5062%(X100)
2321 13:31:12.130868
2322 13:31:12.130977 ==DQS 1 ==
2323 13:31:12.134420 Final DQS duty delay cell = -4
2324 13:31:12.137448 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2325 13:31:12.141116 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2326 13:31:12.144327 [-4] AVG Duty = 5031%(X100)
2327 13:31:12.144405
2328 13:31:12.147531 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2329 13:31:12.147634
2330 13:31:12.151073 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2331 13:31:12.154418 [DutyScan_Calibration_Flow] ====Done====
2332 13:31:12.154525
2333 13:31:12.157382 [DutyScan_Calibration_Flow] k_type=3
2334 13:31:12.174263
2335 13:31:12.174382 ==DQM 0 ==
2336 13:31:12.177623 Final DQM duty delay cell = 0
2337 13:31:12.180895 [0] MAX Duty = 5062%(X100), DQS PI = 24
2338 13:31:12.184233 [0] MIN Duty = 4813%(X100), DQS PI = 2
2339 13:31:12.184338 [0] AVG Duty = 4937%(X100)
2340 13:31:12.187392
2341 13:31:12.187495 ==DQM 1 ==
2342 13:31:12.190870 Final DQM duty delay cell = 0
2343 13:31:12.194316 [0] MAX Duty = 5187%(X100), DQS PI = 46
2344 13:31:12.197636 [0] MIN Duty = 5000%(X100), DQS PI = 22
2345 13:31:12.197720 [0] AVG Duty = 5093%(X100)
2346 13:31:12.200639
2347 13:31:12.204089 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2348 13:31:12.204192
2349 13:31:12.207353 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2350 13:31:12.210645 [DutyScan_Calibration_Flow] ====Done====
2351 13:31:12.210755
2352 13:31:12.214027 [DutyScan_Calibration_Flow] k_type=2
2353 13:31:12.230737
2354 13:31:12.230860 ==DQ 0 ==
2355 13:31:12.234101 Final DQ duty delay cell = -4
2356 13:31:12.237519 [-4] MAX Duty = 5031%(X100), DQS PI = 32
2357 13:31:12.240528 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2358 13:31:12.243886 [-4] AVG Duty = 4953%(X100)
2359 13:31:12.243972
2360 13:31:12.244058 ==DQ 1 ==
2361 13:31:12.247262 Final DQ duty delay cell = 4
2362 13:31:12.250595 [4] MAX Duty = 5093%(X100), DQS PI = 4
2363 13:31:12.254016 [4] MIN Duty = 5031%(X100), DQS PI = 0
2364 13:31:12.254102 [4] AVG Duty = 5062%(X100)
2365 13:31:12.257517
2366 13:31:12.261019 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2367 13:31:12.261106
2368 13:31:12.264254 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2369 13:31:12.267527 [DutyScan_Calibration_Flow] ====Done====
2370 13:31:12.267614 ==
2371 13:31:12.270735 Dram Type= 6, Freq= 0, CH_1, rank 0
2372 13:31:12.274193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2373 13:31:12.274280 ==
2374 13:31:12.277718 [Duty_Offset_Calibration]
2375 13:31:12.277803 B0:0 B1:-1 CA:2
2376 13:31:12.277887
2377 13:31:12.280867 [DutyScan_Calibration_Flow] k_type=0
2378 13:31:12.290959
2379 13:31:12.291076 ==CLK 0==
2380 13:31:12.294387 Final CLK duty delay cell = 0
2381 13:31:12.297863 [0] MAX Duty = 5156%(X100), DQS PI = 16
2382 13:31:12.301295 [0] MIN Duty = 4938%(X100), DQS PI = 44
2383 13:31:12.301449 [0] AVG Duty = 5047%(X100)
2384 13:31:12.304063
2385 13:31:12.307399 CH1 CLK Duty spec in!! Max-Min= 218%
2386 13:31:12.310735 [DutyScan_Calibration_Flow] ====Done====
2387 13:31:12.310816
2388 13:31:12.314115 [DutyScan_Calibration_Flow] k_type=1
2389 13:31:12.330352
2390 13:31:12.330447 ==DQS 0 ==
2391 13:31:12.333920 Final DQS duty delay cell = 0
2392 13:31:12.337102 [0] MAX Duty = 5093%(X100), DQS PI = 24
2393 13:31:12.340417 [0] MIN Duty = 4969%(X100), DQS PI = 0
2394 13:31:12.340502 [0] AVG Duty = 5031%(X100)
2395 13:31:12.343684
2396 13:31:12.343755 ==DQS 1 ==
2397 13:31:12.347174 Final DQS duty delay cell = 0
2398 13:31:12.350488 [0] MAX Duty = 5156%(X100), DQS PI = 0
2399 13:31:12.353909 [0] MIN Duty = 4813%(X100), DQS PI = 36
2400 13:31:12.353987 [0] AVG Duty = 4984%(X100)
2401 13:31:12.354051
2402 13:31:12.360581 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2403 13:31:12.360667
2404 13:31:12.363818 CH1 DQS 1 Duty spec in!! Max-Min= 343%
2405 13:31:12.367366 [DutyScan_Calibration_Flow] ====Done====
2406 13:31:12.367463
2407 13:31:12.370229 [DutyScan_Calibration_Flow] k_type=3
2408 13:31:12.387797
2409 13:31:12.387884 ==DQM 0 ==
2410 13:31:12.390876 Final DQM duty delay cell = 4
2411 13:31:12.394200 [4] MAX Duty = 5093%(X100), DQS PI = 20
2412 13:31:12.397515 [4] MIN Duty = 4969%(X100), DQS PI = 28
2413 13:31:12.400939 [4] AVG Duty = 5031%(X100)
2414 13:31:12.401025
2415 13:31:12.401093 ==DQM 1 ==
2416 13:31:12.404011 Final DQM duty delay cell = 0
2417 13:31:12.407363 [0] MAX Duty = 5249%(X100), DQS PI = 60
2418 13:31:12.410740 [0] MIN Duty = 4875%(X100), DQS PI = 36
2419 13:31:12.414502 [0] AVG Duty = 5062%(X100)
2420 13:31:12.414588
2421 13:31:12.417591 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2422 13:31:12.417676
2423 13:31:12.420845 CH1 DQM 1 Duty spec in!! Max-Min= 374%
2424 13:31:12.424374 [DutyScan_Calibration_Flow] ====Done====
2425 13:31:12.424459
2426 13:31:12.427661 [DutyScan_Calibration_Flow] k_type=2
2427 13:31:12.444077
2428 13:31:12.444162 ==DQ 0 ==
2429 13:31:12.447678 Final DQ duty delay cell = 0
2430 13:31:12.450578 [0] MAX Duty = 5062%(X100), DQS PI = 20
2431 13:31:12.454355 [0] MIN Duty = 4938%(X100), DQS PI = 44
2432 13:31:12.454455 [0] AVG Duty = 5000%(X100)
2433 13:31:12.457581
2434 13:31:12.457668 ==DQ 1 ==
2435 13:31:12.461210 Final DQ duty delay cell = 0
2436 13:31:12.464173 [0] MAX Duty = 5062%(X100), DQS PI = 4
2437 13:31:12.467579 [0] MIN Duty = 4813%(X100), DQS PI = 36
2438 13:31:12.467666 [0] AVG Duty = 4937%(X100)
2439 13:31:12.467734
2440 13:31:12.470644 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2441 13:31:12.470731
2442 13:31:12.477372 CH1 DQ 1 Duty spec in!! Max-Min= 249%
2443 13:31:12.480930 [DutyScan_Calibration_Flow] ====Done====
2444 13:31:12.484326 nWR fixed to 30
2445 13:31:12.484410 [ModeRegInit_LP4] CH0 RK0
2446 13:31:12.487744 [ModeRegInit_LP4] CH0 RK1
2447 13:31:12.490680 [ModeRegInit_LP4] CH1 RK0
2448 13:31:12.490764 [ModeRegInit_LP4] CH1 RK1
2449 13:31:12.494311 match AC timing 7
2450 13:31:12.497604 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2451 13:31:12.501120 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2452 13:31:12.507383 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2453 13:31:12.510693 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2454 13:31:12.517348 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2455 13:31:12.517466 ==
2456 13:31:12.520628 Dram Type= 6, Freq= 0, CH_0, rank 0
2457 13:31:12.523847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2458 13:31:12.523965 ==
2459 13:31:12.530713 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2460 13:31:12.534034 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2461 13:31:12.543977 [CA 0] Center 38 (7~69) winsize 63
2462 13:31:12.547346 [CA 1] Center 38 (8~69) winsize 62
2463 13:31:12.550392 [CA 2] Center 35 (5~66) winsize 62
2464 13:31:12.553827 [CA 3] Center 35 (4~66) winsize 63
2465 13:31:12.557121 [CA 4] Center 34 (4~65) winsize 62
2466 13:31:12.560799 [CA 5] Center 33 (3~63) winsize 61
2467 13:31:12.560960
2468 13:31:12.564313 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2469 13:31:12.564415
2470 13:31:12.567837 [CATrainingPosCal] consider 1 rank data
2471 13:31:12.570671 u2DelayCellTimex100 = 270/100 ps
2472 13:31:12.573859 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2473 13:31:12.577614 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2474 13:31:12.583996 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2475 13:31:12.587151 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2476 13:31:12.590848 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2477 13:31:12.594053 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2478 13:31:12.594141
2479 13:31:12.597009 CA PerBit enable=1, Macro0, CA PI delay=33
2480 13:31:12.597088
2481 13:31:12.600489 [CBTSetCACLKResult] CA Dly = 33
2482 13:31:12.600572 CS Dly: 6 (0~37)
2483 13:31:12.603992 ==
2484 13:31:12.604068 Dram Type= 6, Freq= 0, CH_0, rank 1
2485 13:31:12.610413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2486 13:31:12.610512 ==
2487 13:31:12.613922 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2488 13:31:12.620516 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2489 13:31:12.629535 [CA 0] Center 39 (8~70) winsize 63
2490 13:31:12.633025 [CA 1] Center 38 (8~69) winsize 62
2491 13:31:12.636339 [CA 2] Center 35 (5~66) winsize 62
2492 13:31:12.639851 [CA 3] Center 35 (5~66) winsize 62
2493 13:31:12.642856 [CA 4] Center 34 (4~65) winsize 62
2494 13:31:12.646696 [CA 5] Center 34 (4~64) winsize 61
2495 13:31:12.646797
2496 13:31:12.649704 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2497 13:31:12.649789
2498 13:31:12.652987 [CATrainingPosCal] consider 2 rank data
2499 13:31:12.656361 u2DelayCellTimex100 = 270/100 ps
2500 13:31:12.659931 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2501 13:31:12.663099 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2502 13:31:12.666403 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2503 13:31:12.673073 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2504 13:31:12.676439 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2505 13:31:12.679969 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2506 13:31:12.680045
2507 13:31:12.683313 CA PerBit enable=1, Macro0, CA PI delay=33
2508 13:31:12.683384
2509 13:31:12.686620 [CBTSetCACLKResult] CA Dly = 33
2510 13:31:12.686692 CS Dly: 7 (0~39)
2511 13:31:12.686754
2512 13:31:12.689998 ----->DramcWriteLeveling(PI) begin...
2513 13:31:12.690073 ==
2514 13:31:12.693226 Dram Type= 6, Freq= 0, CH_0, rank 0
2515 13:31:12.700243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2516 13:31:12.700327 ==
2517 13:31:12.703407 Write leveling (Byte 0): 35 => 35
2518 13:31:12.706850 Write leveling (Byte 1): 32 => 32
2519 13:31:12.706934 DramcWriteLeveling(PI) end<-----
2520 13:31:12.707009
2521 13:31:12.710018 ==
2522 13:31:12.713219 Dram Type= 6, Freq= 0, CH_0, rank 0
2523 13:31:12.716771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2524 13:31:12.716866 ==
2525 13:31:12.719779 [Gating] SW mode calibration
2526 13:31:12.727109 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2527 13:31:12.729857 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2528 13:31:12.736526 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2529 13:31:12.739939 0 15 4 | B1->B0 | 2e2d 3434 | 1 1 | (1 1) (1 1)
2530 13:31:12.743285 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 13:31:12.750174 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 13:31:12.753517 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 13:31:12.757116 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 13:31:12.763572 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2535 13:31:12.766932 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2536 13:31:12.770297 1 0 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
2537 13:31:12.773555 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2538 13:31:12.780508 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 13:31:12.783488 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 13:31:12.786823 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 13:31:12.793639 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 13:31:12.796996 1 0 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2543 13:31:12.800143 1 0 28 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2544 13:31:12.807158 1 1 0 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
2545 13:31:12.811031 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 13:31:12.813882 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 13:31:12.820109 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 13:31:12.823464 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 13:31:12.827084 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 13:31:12.833575 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 13:31:12.836863 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2552 13:31:12.840359 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 13:31:12.846723 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2554 13:31:12.850050 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 13:31:12.853568 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 13:31:12.860278 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 13:31:12.863861 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 13:31:12.866835 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 13:31:12.870365 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 13:31:12.877185 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 13:31:12.880132 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 13:31:12.883867 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 13:31:12.890341 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 13:31:12.893777 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 13:31:12.896925 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 13:31:12.903971 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 13:31:12.907363 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2568 13:31:12.910570 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2569 13:31:12.914119 Total UI for P1: 0, mck2ui 16
2570 13:31:12.917176 best dqsien dly found for B0: ( 1, 3, 28)
2571 13:31:12.920401 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2572 13:31:12.923599 Total UI for P1: 0, mck2ui 16
2573 13:31:12.927285 best dqsien dly found for B1: ( 1, 4, 0)
2574 13:31:12.930708 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2575 13:31:12.934070 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2576 13:31:12.937478
2577 13:31:12.940764 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2578 13:31:12.944097 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2579 13:31:12.947675 [Gating] SW calibration Done
2580 13:31:12.947761 ==
2581 13:31:12.950614 Dram Type= 6, Freq= 0, CH_0, rank 0
2582 13:31:12.954362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2583 13:31:12.954438 ==
2584 13:31:12.954503 RX Vref Scan: 0
2585 13:31:12.954560
2586 13:31:12.957382 RX Vref 0 -> 0, step: 1
2587 13:31:12.957466
2588 13:31:12.960731 RX Delay -40 -> 252, step: 8
2589 13:31:12.964195 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2590 13:31:12.967639 iDelay=208, Bit 1, Center 123 (56 ~ 191) 136
2591 13:31:12.971024 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2592 13:31:12.977493 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2593 13:31:12.981126 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2594 13:31:12.984004 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2595 13:31:12.987375 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2596 13:31:12.991063 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2597 13:31:12.997429 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2598 13:31:13.000722 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2599 13:31:13.004595 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2600 13:31:13.007581 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2601 13:31:13.010921 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2602 13:31:13.017229 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2603 13:31:13.021106 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2604 13:31:13.024208 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2605 13:31:13.024293 ==
2606 13:31:13.027717 Dram Type= 6, Freq= 0, CH_0, rank 0
2607 13:31:13.031107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2608 13:31:13.031193 ==
2609 13:31:13.034054 DQS Delay:
2610 13:31:13.034151 DQS0 = 0, DQS1 = 0
2611 13:31:13.037289 DQM Delay:
2612 13:31:13.037373 DQM0 = 123, DQM1 = 110
2613 13:31:13.041050 DQ Delay:
2614 13:31:13.043863 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2615 13:31:13.047269 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2616 13:31:13.050763 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2617 13:31:13.054179 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2618 13:31:13.054263
2619 13:31:13.054329
2620 13:31:13.054391 ==
2621 13:31:13.057538 Dram Type= 6, Freq= 0, CH_0, rank 0
2622 13:31:13.060774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2623 13:31:13.060859 ==
2624 13:31:13.060927
2625 13:31:13.060990
2626 13:31:13.064333 TX Vref Scan disable
2627 13:31:13.067598 == TX Byte 0 ==
2628 13:31:13.071045 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2629 13:31:13.074530 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2630 13:31:13.074661 == TX Byte 1 ==
2631 13:31:13.081010 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2632 13:31:13.084357 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2633 13:31:13.084486 ==
2634 13:31:13.087561 Dram Type= 6, Freq= 0, CH_0, rank 0
2635 13:31:13.090855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2636 13:31:13.090945 ==
2637 13:31:13.104422 TX Vref=22, minBit 3, minWin=24, winSum=403
2638 13:31:13.107732 TX Vref=24, minBit 4, minWin=24, winSum=409
2639 13:31:13.110915 TX Vref=26, minBit 0, minWin=25, winSum=412
2640 13:31:13.114140 TX Vref=28, minBit 7, minWin=24, winSum=418
2641 13:31:13.117389 TX Vref=30, minBit 3, minWin=25, winSum=417
2642 13:31:13.120846 TX Vref=32, minBit 0, minWin=25, winSum=416
2643 13:31:13.127348 [TxChooseVref] Worse bit 3, Min win 25, Win sum 417, Final Vref 30
2644 13:31:13.127463
2645 13:31:13.130658 Final TX Range 1 Vref 30
2646 13:31:13.130772
2647 13:31:13.130878 ==
2648 13:31:13.133940 Dram Type= 6, Freq= 0, CH_0, rank 0
2649 13:31:13.137380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2650 13:31:13.137472 ==
2651 13:31:13.137581
2652 13:31:13.140718
2653 13:31:13.140834 TX Vref Scan disable
2654 13:31:13.143934 == TX Byte 0 ==
2655 13:31:13.147468 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2656 13:31:13.150444 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2657 13:31:13.153938 == TX Byte 1 ==
2658 13:31:13.157245 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2659 13:31:13.160718 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2660 13:31:13.160828
2661 13:31:13.163965 [DATLAT]
2662 13:31:13.164093 Freq=1200, CH0 RK0
2663 13:31:13.164203
2664 13:31:13.167005 DATLAT Default: 0xd
2665 13:31:13.167112 0, 0xFFFF, sum = 0
2666 13:31:13.170383 1, 0xFFFF, sum = 0
2667 13:31:13.170504 2, 0xFFFF, sum = 0
2668 13:31:13.173937 3, 0xFFFF, sum = 0
2669 13:31:13.174033 4, 0xFFFF, sum = 0
2670 13:31:13.177355 5, 0xFFFF, sum = 0
2671 13:31:13.177445 6, 0xFFFF, sum = 0
2672 13:31:13.180621 7, 0xFFFF, sum = 0
2673 13:31:13.180741 8, 0xFFFF, sum = 0
2674 13:31:13.183853 9, 0xFFFF, sum = 0
2675 13:31:13.187540 10, 0xFFFF, sum = 0
2676 13:31:13.187657 11, 0xFFFF, sum = 0
2677 13:31:13.190981 12, 0x0, sum = 1
2678 13:31:13.191087 13, 0x0, sum = 2
2679 13:31:13.191192 14, 0x0, sum = 3
2680 13:31:13.194340 15, 0x0, sum = 4
2681 13:31:13.194446 best_step = 13
2682 13:31:13.194548
2683 13:31:13.197683 ==
2684 13:31:13.197761 Dram Type= 6, Freq= 0, CH_0, rank 0
2685 13:31:13.204150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2686 13:31:13.204232 ==
2687 13:31:13.204338 RX Vref Scan: 1
2688 13:31:13.204439
2689 13:31:13.207752 Set Vref Range= 32 -> 127
2690 13:31:13.207861
2691 13:31:13.210761 RX Vref 32 -> 127, step: 1
2692 13:31:13.210865
2693 13:31:13.214342 RX Delay -13 -> 252, step: 4
2694 13:31:13.214449
2695 13:31:13.217373 Set Vref, RX VrefLevel [Byte0]: 32
2696 13:31:13.220654 [Byte1]: 32
2697 13:31:13.220780
2698 13:31:13.224095 Set Vref, RX VrefLevel [Byte0]: 33
2699 13:31:13.227735 [Byte1]: 33
2700 13:31:13.227840
2701 13:31:13.230870 Set Vref, RX VrefLevel [Byte0]: 34
2702 13:31:13.234357 [Byte1]: 34
2703 13:31:13.238198
2704 13:31:13.238323 Set Vref, RX VrefLevel [Byte0]: 35
2705 13:31:13.241353 [Byte1]: 35
2706 13:31:13.246482
2707 13:31:13.246567 Set Vref, RX VrefLevel [Byte0]: 36
2708 13:31:13.249398 [Byte1]: 36
2709 13:31:13.253643
2710 13:31:13.253761 Set Vref, RX VrefLevel [Byte0]: 37
2711 13:31:13.257745 [Byte1]: 37
2712 13:31:13.261873
2713 13:31:13.261957 Set Vref, RX VrefLevel [Byte0]: 38
2714 13:31:13.265192 [Byte1]: 38
2715 13:31:13.269574
2716 13:31:13.269657 Set Vref, RX VrefLevel [Byte0]: 39
2717 13:31:13.272978 [Byte1]: 39
2718 13:31:13.277366
2719 13:31:13.277457 Set Vref, RX VrefLevel [Byte0]: 40
2720 13:31:13.280835 [Byte1]: 40
2721 13:31:13.285420
2722 13:31:13.285528 Set Vref, RX VrefLevel [Byte0]: 41
2723 13:31:13.288830 [Byte1]: 41
2724 13:31:13.293291
2725 13:31:13.293375 Set Vref, RX VrefLevel [Byte0]: 42
2726 13:31:13.296681 [Byte1]: 42
2727 13:31:13.301313
2728 13:31:13.301396 Set Vref, RX VrefLevel [Byte0]: 43
2729 13:31:13.304334 [Byte1]: 43
2730 13:31:13.309147
2731 13:31:13.309230 Set Vref, RX VrefLevel [Byte0]: 44
2732 13:31:13.312468 [Byte1]: 44
2733 13:31:13.317151
2734 13:31:13.317260 Set Vref, RX VrefLevel [Byte0]: 45
2735 13:31:13.320095 [Byte1]: 45
2736 13:31:13.325198
2737 13:31:13.325332 Set Vref, RX VrefLevel [Byte0]: 46
2738 13:31:13.328061 [Byte1]: 46
2739 13:31:13.332881
2740 13:31:13.333005 Set Vref, RX VrefLevel [Byte0]: 47
2741 13:31:13.336249 [Byte1]: 47
2742 13:31:13.340969
2743 13:31:13.341093 Set Vref, RX VrefLevel [Byte0]: 48
2744 13:31:13.343775 [Byte1]: 48
2745 13:31:13.348735
2746 13:31:13.348864 Set Vref, RX VrefLevel [Byte0]: 49
2747 13:31:13.351901 [Byte1]: 49
2748 13:31:13.356637
2749 13:31:13.356766 Set Vref, RX VrefLevel [Byte0]: 50
2750 13:31:13.359852 [Byte1]: 50
2751 13:31:13.364261
2752 13:31:13.364385 Set Vref, RX VrefLevel [Byte0]: 51
2753 13:31:13.367467 [Byte1]: 51
2754 13:31:13.372221
2755 13:31:13.372350 Set Vref, RX VrefLevel [Byte0]: 52
2756 13:31:13.375270 [Byte1]: 52
2757 13:31:13.380217
2758 13:31:13.380336 Set Vref, RX VrefLevel [Byte0]: 53
2759 13:31:13.383481 [Byte1]: 53
2760 13:31:13.388096
2761 13:31:13.388218 Set Vref, RX VrefLevel [Byte0]: 54
2762 13:31:13.391248 [Byte1]: 54
2763 13:31:13.395886
2764 13:31:13.396011 Set Vref, RX VrefLevel [Byte0]: 55
2765 13:31:13.399139 [Byte1]: 55
2766 13:31:13.403900
2767 13:31:13.404024 Set Vref, RX VrefLevel [Byte0]: 56
2768 13:31:13.406795 [Byte1]: 56
2769 13:31:13.411866
2770 13:31:13.411963 Set Vref, RX VrefLevel [Byte0]: 57
2771 13:31:13.414808 [Byte1]: 57
2772 13:31:13.419547
2773 13:31:13.419695 Set Vref, RX VrefLevel [Byte0]: 58
2774 13:31:13.422830 [Byte1]: 58
2775 13:31:13.427349
2776 13:31:13.427462 Set Vref, RX VrefLevel [Byte0]: 59
2777 13:31:13.430908 [Byte1]: 59
2778 13:31:13.435185
2779 13:31:13.435298 Set Vref, RX VrefLevel [Byte0]: 60
2780 13:31:13.438450 [Byte1]: 60
2781 13:31:13.443228
2782 13:31:13.443329 Set Vref, RX VrefLevel [Byte0]: 61
2783 13:31:13.446446 [Byte1]: 61
2784 13:31:13.450937
2785 13:31:13.451020 Set Vref, RX VrefLevel [Byte0]: 62
2786 13:31:13.454254 [Byte1]: 62
2787 13:31:13.459031
2788 13:31:13.459115 Set Vref, RX VrefLevel [Byte0]: 63
2789 13:31:13.462103 [Byte1]: 63
2790 13:31:13.467028
2791 13:31:13.467112 Set Vref, RX VrefLevel [Byte0]: 64
2792 13:31:13.470042 [Byte1]: 64
2793 13:31:13.474599
2794 13:31:13.474718 Set Vref, RX VrefLevel [Byte0]: 65
2795 13:31:13.478052 [Byte1]: 65
2796 13:31:13.482888
2797 13:31:13.482997 Set Vref, RX VrefLevel [Byte0]: 66
2798 13:31:13.486274 [Byte1]: 66
2799 13:31:13.490789
2800 13:31:13.490891 Set Vref, RX VrefLevel [Byte0]: 67
2801 13:31:13.493682 [Byte1]: 67
2802 13:31:13.498376
2803 13:31:13.498478 Set Vref, RX VrefLevel [Byte0]: 68
2804 13:31:13.501886 [Byte1]: 68
2805 13:31:13.506263
2806 13:31:13.506365 Set Vref, RX VrefLevel [Byte0]: 69
2807 13:31:13.509994 [Byte1]: 69
2808 13:31:13.514406
2809 13:31:13.514510 Final RX Vref Byte 0 = 59 to rank0
2810 13:31:13.517418 Final RX Vref Byte 1 = 50 to rank0
2811 13:31:13.520664 Final RX Vref Byte 0 = 59 to rank1
2812 13:31:13.524179 Final RX Vref Byte 1 = 50 to rank1==
2813 13:31:13.527345 Dram Type= 6, Freq= 0, CH_0, rank 0
2814 13:31:13.534410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2815 13:31:13.534497 ==
2816 13:31:13.534565 DQS Delay:
2817 13:31:13.534627 DQS0 = 0, DQS1 = 0
2818 13:31:13.537325 DQM Delay:
2819 13:31:13.537409 DQM0 = 122, DQM1 = 109
2820 13:31:13.540855 DQ Delay:
2821 13:31:13.544226 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2822 13:31:13.547586 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2823 13:31:13.550866 DQ8 =102, DQ9 =94, DQ10 =110, DQ11 =106
2824 13:31:13.554386 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2825 13:31:13.554471
2826 13:31:13.554539
2827 13:31:13.561211 [DQSOSCAuto] RK0, (LSB)MR18= 0xb08, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
2828 13:31:13.564565 CH0 RK0: MR19=404, MR18=B08
2829 13:31:13.571207 CH0_RK0: MR19=0x404, MR18=0xB08, DQSOSC=405, MR23=63, INC=39, DEC=26
2830 13:31:13.571294
2831 13:31:13.574671 ----->DramcWriteLeveling(PI) begin...
2832 13:31:13.574758 ==
2833 13:31:13.577593 Dram Type= 6, Freq= 0, CH_0, rank 1
2834 13:31:13.581270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2835 13:31:13.581396 ==
2836 13:31:13.584847 Write leveling (Byte 0): 36 => 36
2837 13:31:13.588214 Write leveling (Byte 1): 29 => 29
2838 13:31:13.591089 DramcWriteLeveling(PI) end<-----
2839 13:31:13.591212
2840 13:31:13.591326 ==
2841 13:31:13.595014 Dram Type= 6, Freq= 0, CH_0, rank 1
2842 13:31:13.597903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2843 13:31:13.598037 ==
2844 13:31:13.601259 [Gating] SW mode calibration
2845 13:31:13.608008 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2846 13:31:13.614672 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2847 13:31:13.618098 0 15 0 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
2848 13:31:13.624670 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2849 13:31:13.628139 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2850 13:31:13.631142 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2851 13:31:13.634522 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2852 13:31:13.641300 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 13:31:13.644803 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2854 13:31:13.648241 0 15 28 | B1->B0 | 3232 2e2e | 1 0 | (1 0) (0 0)
2855 13:31:13.654939 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2856 13:31:13.658533 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2857 13:31:13.661402 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2858 13:31:13.668165 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2859 13:31:13.671549 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 13:31:13.674678 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 13:31:13.681560 1 0 24 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
2862 13:31:13.685025 1 0 28 | B1->B0 | 3131 3c3c | 0 0 | (0 0) (0 0)
2863 13:31:13.688352 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2864 13:31:13.695211 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2865 13:31:13.698536 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 13:31:13.701569 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 13:31:13.704869 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 13:31:13.711471 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 13:31:13.714843 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 13:31:13.718209 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2871 13:31:13.724934 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 13:31:13.728111 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 13:31:13.731750 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 13:31:13.738390 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 13:31:13.742104 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 13:31:13.745119 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 13:31:13.751498 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 13:31:13.754912 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 13:31:13.758605 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 13:31:13.765035 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 13:31:13.768279 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 13:31:13.771812 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 13:31:13.778613 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 13:31:13.781787 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 13:31:13.785411 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 13:31:13.791715 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2887 13:31:13.795584 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2888 13:31:13.798501 Total UI for P1: 0, mck2ui 16
2889 13:31:13.801885 best dqsien dly found for B0: ( 1, 3, 28)
2890 13:31:13.805334 Total UI for P1: 0, mck2ui 16
2891 13:31:13.808904 best dqsien dly found for B1: ( 1, 3, 28)
2892 13:31:13.812098 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2893 13:31:13.815418 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2894 13:31:13.815504
2895 13:31:13.818758 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2896 13:31:13.821744 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2897 13:31:13.825306 [Gating] SW calibration Done
2898 13:31:13.825440 ==
2899 13:31:13.828701 Dram Type= 6, Freq= 0, CH_0, rank 1
2900 13:31:13.831887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2901 13:31:13.831990 ==
2902 13:31:13.835321 RX Vref Scan: 0
2903 13:31:13.835407
2904 13:31:13.835474 RX Vref 0 -> 0, step: 1
2905 13:31:13.835537
2906 13:31:13.838687 RX Delay -40 -> 252, step: 8
2907 13:31:13.845394 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2908 13:31:13.848405 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2909 13:31:13.851783 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2910 13:31:13.855423 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2911 13:31:13.858928 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2912 13:31:13.862172 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2913 13:31:13.868814 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2914 13:31:13.872041 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2915 13:31:13.875138 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2916 13:31:13.878452 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2917 13:31:13.882092 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2918 13:31:13.888701 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2919 13:31:13.892284 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2920 13:31:13.895363 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2921 13:31:13.898984 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2922 13:31:13.902798 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2923 13:31:13.905540 ==
2924 13:31:13.905629 Dram Type= 6, Freq= 0, CH_0, rank 1
2925 13:31:13.912069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2926 13:31:13.912197 ==
2927 13:31:13.912316 DQS Delay:
2928 13:31:13.915321 DQS0 = 0, DQS1 = 0
2929 13:31:13.915446 DQM Delay:
2930 13:31:13.918958 DQM0 = 119, DQM1 = 108
2931 13:31:13.919084 DQ Delay:
2932 13:31:13.921951 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2933 13:31:13.925287 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =123
2934 13:31:13.928518 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2935 13:31:13.931928 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2936 13:31:13.932056
2937 13:31:13.932168
2938 13:31:13.932281 ==
2939 13:31:13.935389 Dram Type= 6, Freq= 0, CH_0, rank 1
2940 13:31:13.938971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2941 13:31:13.941874 ==
2942 13:31:13.942008
2943 13:31:13.942122
2944 13:31:13.942230 TX Vref Scan disable
2945 13:31:13.945131 == TX Byte 0 ==
2946 13:31:13.948543 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2947 13:31:13.951906 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2948 13:31:13.955302 == TX Byte 1 ==
2949 13:31:13.958835 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2950 13:31:13.962207 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2951 13:31:13.965543 ==
2952 13:31:13.968941 Dram Type= 6, Freq= 0, CH_0, rank 1
2953 13:31:13.971701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2954 13:31:13.971783 ==
2955 13:31:13.983877 TX Vref=22, minBit 4, minWin=24, winSum=416
2956 13:31:13.987043 TX Vref=24, minBit 0, minWin=26, winSum=424
2957 13:31:13.990438 TX Vref=26, minBit 2, minWin=25, winSum=427
2958 13:31:13.993759 TX Vref=28, minBit 2, minWin=25, winSum=428
2959 13:31:13.997204 TX Vref=30, minBit 4, minWin=26, winSum=433
2960 13:31:14.000475 TX Vref=32, minBit 1, minWin=26, winSum=428
2961 13:31:14.006932 [TxChooseVref] Worse bit 4, Min win 26, Win sum 433, Final Vref 30
2962 13:31:14.007017
2963 13:31:14.010533 Final TX Range 1 Vref 30
2964 13:31:14.010617
2965 13:31:14.010683 ==
2966 13:31:14.013986 Dram Type= 6, Freq= 0, CH_0, rank 1
2967 13:31:14.017168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2968 13:31:14.017252 ==
2969 13:31:14.017317
2970 13:31:14.017378
2971 13:31:14.020547 TX Vref Scan disable
2972 13:31:14.023910 == TX Byte 0 ==
2973 13:31:14.027283 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2974 13:31:14.030440 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2975 13:31:14.034209 == TX Byte 1 ==
2976 13:31:14.037184 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2977 13:31:14.040610 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2978 13:31:14.040693
2979 13:31:14.043899 [DATLAT]
2980 13:31:14.043973 Freq=1200, CH0 RK1
2981 13:31:14.044036
2982 13:31:14.047277 DATLAT Default: 0xd
2983 13:31:14.047377 0, 0xFFFF, sum = 0
2984 13:31:14.050529 1, 0xFFFF, sum = 0
2985 13:31:14.050602 2, 0xFFFF, sum = 0
2986 13:31:14.053971 3, 0xFFFF, sum = 0
2987 13:31:14.054042 4, 0xFFFF, sum = 0
2988 13:31:14.057462 5, 0xFFFF, sum = 0
2989 13:31:14.057533 6, 0xFFFF, sum = 0
2990 13:31:14.060740 7, 0xFFFF, sum = 0
2991 13:31:14.060817 8, 0xFFFF, sum = 0
2992 13:31:14.064212 9, 0xFFFF, sum = 0
2993 13:31:14.064298 10, 0xFFFF, sum = 0
2994 13:31:14.067716 11, 0xFFFF, sum = 0
2995 13:31:14.067804 12, 0x0, sum = 1
2996 13:31:14.071023 13, 0x0, sum = 2
2997 13:31:14.071109 14, 0x0, sum = 3
2998 13:31:14.073943 15, 0x0, sum = 4
2999 13:31:14.074029 best_step = 13
3000 13:31:14.074096
3001 13:31:14.074157 ==
3002 13:31:14.077524 Dram Type= 6, Freq= 0, CH_0, rank 1
3003 13:31:14.084553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3004 13:31:14.084683 ==
3005 13:31:14.084807 RX Vref Scan: 0
3006 13:31:14.084920
3007 13:31:14.087814 RX Vref 0 -> 0, step: 1
3008 13:31:14.087933
3009 13:31:14.091080 RX Delay -21 -> 252, step: 4
3010 13:31:14.094571 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3011 13:31:14.097491 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3012 13:31:14.104117 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3013 13:31:14.107738 iDelay=195, Bit 3, Center 116 (51 ~ 182) 132
3014 13:31:14.110855 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3015 13:31:14.114407 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3016 13:31:14.117760 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3017 13:31:14.120902 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3018 13:31:14.127308 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3019 13:31:14.130676 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3020 13:31:14.134530 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3021 13:31:14.137317 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3022 13:31:14.141116 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3023 13:31:14.147323 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3024 13:31:14.150803 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3025 13:31:14.154059 iDelay=195, Bit 15, Center 116 (55 ~ 178) 124
3026 13:31:14.154142 ==
3027 13:31:14.157557 Dram Type= 6, Freq= 0, CH_0, rank 1
3028 13:31:14.160959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3029 13:31:14.161042 ==
3030 13:31:14.164417 DQS Delay:
3031 13:31:14.164499 DQS0 = 0, DQS1 = 0
3032 13:31:14.167394 DQM Delay:
3033 13:31:14.167475 DQM0 = 120, DQM1 = 108
3034 13:31:14.170833 DQ Delay:
3035 13:31:14.174289 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =116
3036 13:31:14.177847 DQ4 =122, DQ5 =114, DQ6 =126, DQ7 =124
3037 13:31:14.181375 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3038 13:31:14.184161 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =116
3039 13:31:14.184243
3040 13:31:14.184308
3041 13:31:14.190853 [DQSOSCAuto] RK1, (LSB)MR18= 0xdf6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 405 ps
3042 13:31:14.194151 CH0 RK1: MR19=403, MR18=DF6
3043 13:31:14.200939 CH0_RK1: MR19=0x403, MR18=0xDF6, DQSOSC=405, MR23=63, INC=39, DEC=26
3044 13:31:14.204352 [RxdqsGatingPostProcess] freq 1200
3045 13:31:14.207645 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3046 13:31:14.210894 best DQS0 dly(2T, 0.5T) = (0, 11)
3047 13:31:14.214369 best DQS1 dly(2T, 0.5T) = (0, 12)
3048 13:31:14.217719 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3049 13:31:14.221557 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3050 13:31:14.224269 best DQS0 dly(2T, 0.5T) = (0, 11)
3051 13:31:14.227544 best DQS1 dly(2T, 0.5T) = (0, 11)
3052 13:31:14.230990 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3053 13:31:14.234387 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3054 13:31:14.237509 Pre-setting of DQS Precalculation
3055 13:31:14.241181 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3056 13:31:14.241277 ==
3057 13:31:14.244421 Dram Type= 6, Freq= 0, CH_1, rank 0
3058 13:31:14.251203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3059 13:31:14.251286 ==
3060 13:31:14.254639 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3061 13:31:14.261406 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3062 13:31:14.269770 [CA 0] Center 37 (7~68) winsize 62
3063 13:31:14.273140 [CA 1] Center 37 (7~68) winsize 62
3064 13:31:14.276254 [CA 2] Center 35 (5~65) winsize 61
3065 13:31:14.279876 [CA 3] Center 34 (4~65) winsize 62
3066 13:31:14.282943 [CA 4] Center 34 (4~64) winsize 61
3067 13:31:14.286208 [CA 5] Center 33 (3~64) winsize 62
3068 13:31:14.286290
3069 13:31:14.289497 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3070 13:31:14.289579
3071 13:31:14.292915 [CATrainingPosCal] consider 1 rank data
3072 13:31:14.296287 u2DelayCellTimex100 = 270/100 ps
3073 13:31:14.299332 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3074 13:31:14.302657 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3075 13:31:14.309930 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3076 13:31:14.312999 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3077 13:31:14.316326 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3078 13:31:14.319723 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3079 13:31:14.319812
3080 13:31:14.322722 CA PerBit enable=1, Macro0, CA PI delay=33
3081 13:31:14.322858
3082 13:31:14.326085 [CBTSetCACLKResult] CA Dly = 33
3083 13:31:14.326201 CS Dly: 5 (0~36)
3084 13:31:14.326314 ==
3085 13:31:14.329455 Dram Type= 6, Freq= 0, CH_1, rank 1
3086 13:31:14.336413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3087 13:31:14.336514 ==
3088 13:31:14.339876 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3089 13:31:14.346517 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3090 13:31:14.355119 [CA 0] Center 38 (8~68) winsize 61
3091 13:31:14.358574 [CA 1] Center 38 (7~69) winsize 63
3092 13:31:14.361910 [CA 2] Center 35 (5~66) winsize 62
3093 13:31:14.365232 [CA 3] Center 34 (4~65) winsize 62
3094 13:31:14.368690 [CA 4] Center 35 (5~65) winsize 61
3095 13:31:14.372074 [CA 5] Center 34 (4~64) winsize 61
3096 13:31:14.372158
3097 13:31:14.375494 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3098 13:31:14.375580
3099 13:31:14.378890 [CATrainingPosCal] consider 2 rank data
3100 13:31:14.382071 u2DelayCellTimex100 = 270/100 ps
3101 13:31:14.385468 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3102 13:31:14.388482 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3103 13:31:14.395529 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3104 13:31:14.398514 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3105 13:31:14.402402 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
3106 13:31:14.405261 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3107 13:31:14.405346
3108 13:31:14.408617 CA PerBit enable=1, Macro0, CA PI delay=34
3109 13:31:14.408700
3110 13:31:14.412389 [CBTSetCACLKResult] CA Dly = 34
3111 13:31:14.412474 CS Dly: 6 (0~39)
3112 13:31:14.412539
3113 13:31:14.415775 ----->DramcWriteLeveling(PI) begin...
3114 13:31:14.415884 ==
3115 13:31:14.418754 Dram Type= 6, Freq= 0, CH_1, rank 0
3116 13:31:14.425704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3117 13:31:14.425840 ==
3118 13:31:14.428587 Write leveling (Byte 0): 25 => 25
3119 13:31:14.432334 Write leveling (Byte 1): 28 => 28
3120 13:31:14.432436 DramcWriteLeveling(PI) end<-----
3121 13:31:14.435898
3122 13:31:14.436033 ==
3123 13:31:14.438861 Dram Type= 6, Freq= 0, CH_1, rank 0
3124 13:31:14.441950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3125 13:31:14.442059 ==
3126 13:31:14.445456 [Gating] SW mode calibration
3127 13:31:14.452051 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3128 13:31:14.455447 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3129 13:31:14.462454 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3130 13:31:14.465228 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3131 13:31:14.468701 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3132 13:31:14.475413 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3133 13:31:14.478888 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3134 13:31:14.482177 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3135 13:31:14.488901 0 15 24 | B1->B0 | 3030 2929 | 0 0 | (0 0) (1 0)
3136 13:31:14.492291 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3137 13:31:14.495428 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3138 13:31:14.502514 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3139 13:31:14.505401 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3140 13:31:14.508602 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3141 13:31:14.515282 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3142 13:31:14.518772 1 0 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3143 13:31:14.522170 1 0 24 | B1->B0 | 3a3a 4242 | 0 0 | (0 0) (0 0)
3144 13:31:14.525611 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 13:31:14.532945 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3146 13:31:14.535541 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 13:31:14.539007 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 13:31:14.545748 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 13:31:14.549099 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 13:31:14.551967 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 13:31:14.558877 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3152 13:31:14.562090 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3153 13:31:14.565601 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 13:31:14.572502 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 13:31:14.575402 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 13:31:14.578742 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 13:31:14.585712 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 13:31:14.589058 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 13:31:14.592241 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 13:31:14.598847 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 13:31:14.602139 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 13:31:14.605491 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 13:31:14.608874 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 13:31:14.615607 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 13:31:14.619324 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 13:31:14.622744 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 13:31:14.629225 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3168 13:31:14.632481 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3169 13:31:14.635651 Total UI for P1: 0, mck2ui 16
3170 13:31:14.639315 best dqsien dly found for B0: ( 1, 3, 24)
3171 13:31:14.642568 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3172 13:31:14.646395 Total UI for P1: 0, mck2ui 16
3173 13:31:14.649082 best dqsien dly found for B1: ( 1, 3, 26)
3174 13:31:14.652382 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3175 13:31:14.655564 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3176 13:31:14.655646
3177 13:31:14.662332 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3178 13:31:14.665796 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3179 13:31:14.665878 [Gating] SW calibration Done
3180 13:31:14.669141 ==
3181 13:31:14.672580 Dram Type= 6, Freq= 0, CH_1, rank 0
3182 13:31:14.675784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3183 13:31:14.675909 ==
3184 13:31:14.676023 RX Vref Scan: 0
3185 13:31:14.676135
3186 13:31:14.679172 RX Vref 0 -> 0, step: 1
3187 13:31:14.679294
3188 13:31:14.682134 RX Delay -40 -> 252, step: 8
3189 13:31:14.685485 iDelay=200, Bit 0, Center 119 (56 ~ 183) 128
3190 13:31:14.688937 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3191 13:31:14.692266 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3192 13:31:14.698801 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3193 13:31:14.702167 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3194 13:31:14.705462 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3195 13:31:14.709117 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3196 13:31:14.712212 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3197 13:31:14.718911 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3198 13:31:14.722529 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3199 13:31:14.725827 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3200 13:31:14.729238 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3201 13:31:14.732184 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3202 13:31:14.738975 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3203 13:31:14.742249 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3204 13:31:14.745739 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3205 13:31:14.745857 ==
3206 13:31:14.749508 Dram Type= 6, Freq= 0, CH_1, rank 0
3207 13:31:14.752454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3208 13:31:14.752574 ==
3209 13:31:14.756112 DQS Delay:
3210 13:31:14.756232 DQS0 = 0, DQS1 = 0
3211 13:31:14.756343 DQM Delay:
3212 13:31:14.759123 DQM0 = 120, DQM1 = 113
3213 13:31:14.759243 DQ Delay:
3214 13:31:14.762459 DQ0 =119, DQ1 =115, DQ2 =111, DQ3 =123
3215 13:31:14.765798 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =119
3216 13:31:14.769094 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3217 13:31:14.775908 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3218 13:31:14.776034
3219 13:31:14.776158
3220 13:31:14.776219 ==
3221 13:31:14.779101 Dram Type= 6, Freq= 0, CH_1, rank 0
3222 13:31:14.782586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3223 13:31:14.782668 ==
3224 13:31:14.782734
3225 13:31:14.782793
3226 13:31:14.785916 TX Vref Scan disable
3227 13:31:14.785997 == TX Byte 0 ==
3228 13:31:14.792770 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3229 13:31:14.796137 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3230 13:31:14.796219 == TX Byte 1 ==
3231 13:31:14.802729 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3232 13:31:14.806052 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3233 13:31:14.806134 ==
3234 13:31:14.809487 Dram Type= 6, Freq= 0, CH_1, rank 0
3235 13:31:14.812376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3236 13:31:14.812459 ==
3237 13:31:14.825173 TX Vref=22, minBit 1, minWin=24, winSum=403
3238 13:31:14.828624 TX Vref=24, minBit 11, minWin=24, winSum=407
3239 13:31:14.832092 TX Vref=26, minBit 3, minWin=25, winSum=414
3240 13:31:14.835414 TX Vref=28, minBit 8, minWin=25, winSum=422
3241 13:31:14.838551 TX Vref=30, minBit 10, minWin=25, winSum=424
3242 13:31:14.845709 TX Vref=32, minBit 11, minWin=25, winSum=421
3243 13:31:14.848767 [TxChooseVref] Worse bit 10, Min win 25, Win sum 424, Final Vref 30
3244 13:31:14.848875
3245 13:31:14.852574 Final TX Range 1 Vref 30
3246 13:31:14.852679
3247 13:31:14.852775 ==
3248 13:31:14.855090 Dram Type= 6, Freq= 0, CH_1, rank 0
3249 13:31:14.858557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3250 13:31:14.861800 ==
3251 13:31:14.861873
3252 13:31:14.861934
3253 13:31:14.861991 TX Vref Scan disable
3254 13:31:14.865239 == TX Byte 0 ==
3255 13:31:14.868616 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3256 13:31:14.875332 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3257 13:31:14.875416 == TX Byte 1 ==
3258 13:31:14.878696 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3259 13:31:14.881709 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3260 13:31:14.885564
3261 13:31:14.885647 [DATLAT]
3262 13:31:14.885713 Freq=1200, CH1 RK0
3263 13:31:14.885775
3264 13:31:14.888715 DATLAT Default: 0xd
3265 13:31:14.888815 0, 0xFFFF, sum = 0
3266 13:31:14.892063 1, 0xFFFF, sum = 0
3267 13:31:14.892148 2, 0xFFFF, sum = 0
3268 13:31:14.895616 3, 0xFFFF, sum = 0
3269 13:31:14.895700 4, 0xFFFF, sum = 0
3270 13:31:14.898503 5, 0xFFFF, sum = 0
3271 13:31:14.902250 6, 0xFFFF, sum = 0
3272 13:31:14.902348 7, 0xFFFF, sum = 0
3273 13:31:14.905279 8, 0xFFFF, sum = 0
3274 13:31:14.905364 9, 0xFFFF, sum = 0
3275 13:31:14.908432 10, 0xFFFF, sum = 0
3276 13:31:14.908517 11, 0xFFFF, sum = 0
3277 13:31:14.912049 12, 0x0, sum = 1
3278 13:31:14.912134 13, 0x0, sum = 2
3279 13:31:14.915497 14, 0x0, sum = 3
3280 13:31:14.915580 15, 0x0, sum = 4
3281 13:31:14.915647 best_step = 13
3282 13:31:14.915707
3283 13:31:14.918942 ==
3284 13:31:14.921981 Dram Type= 6, Freq= 0, CH_1, rank 0
3285 13:31:14.925191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3286 13:31:14.925273 ==
3287 13:31:14.925337 RX Vref Scan: 1
3288 13:31:14.925396
3289 13:31:14.928923 Set Vref Range= 32 -> 127
3290 13:31:14.929004
3291 13:31:14.931947 RX Vref 32 -> 127, step: 1
3292 13:31:14.932031
3293 13:31:14.935320 RX Delay -13 -> 252, step: 4
3294 13:31:14.935401
3295 13:31:14.938578 Set Vref, RX VrefLevel [Byte0]: 32
3296 13:31:14.942030 [Byte1]: 32
3297 13:31:14.942110
3298 13:31:14.945505 Set Vref, RX VrefLevel [Byte0]: 33
3299 13:31:14.948841 [Byte1]: 33
3300 13:31:14.948922
3301 13:31:14.951929 Set Vref, RX VrefLevel [Byte0]: 34
3302 13:31:14.955525 [Byte1]: 34
3303 13:31:14.959515
3304 13:31:14.959625 Set Vref, RX VrefLevel [Byte0]: 35
3305 13:31:14.962943 [Byte1]: 35
3306 13:31:14.967423
3307 13:31:14.967498 Set Vref, RX VrefLevel [Byte0]: 36
3308 13:31:14.970954 [Byte1]: 36
3309 13:31:14.975408
3310 13:31:14.975543 Set Vref, RX VrefLevel [Byte0]: 37
3311 13:31:14.978449 [Byte1]: 37
3312 13:31:14.983275
3313 13:31:14.983384 Set Vref, RX VrefLevel [Byte0]: 38
3314 13:31:14.986491 [Byte1]: 38
3315 13:31:14.990957
3316 13:31:14.991038 Set Vref, RX VrefLevel [Byte0]: 39
3317 13:31:14.994333 [Byte1]: 39
3318 13:31:14.998846
3319 13:31:14.998928 Set Vref, RX VrefLevel [Byte0]: 40
3320 13:31:15.002249 [Byte1]: 40
3321 13:31:15.006996
3322 13:31:15.007078 Set Vref, RX VrefLevel [Byte0]: 41
3323 13:31:15.010073 [Byte1]: 41
3324 13:31:15.014900
3325 13:31:15.014981 Set Vref, RX VrefLevel [Byte0]: 42
3326 13:31:15.018157 [Byte1]: 42
3327 13:31:15.022989
3328 13:31:15.023069 Set Vref, RX VrefLevel [Byte0]: 43
3329 13:31:15.025847 [Byte1]: 43
3330 13:31:15.030344
3331 13:31:15.030487 Set Vref, RX VrefLevel [Byte0]: 44
3332 13:31:15.033832 [Byte1]: 44
3333 13:31:15.038577
3334 13:31:15.038655 Set Vref, RX VrefLevel [Byte0]: 45
3335 13:31:15.041911 [Byte1]: 45
3336 13:31:15.046303
3337 13:31:15.046402 Set Vref, RX VrefLevel [Byte0]: 46
3338 13:31:15.049827 [Byte1]: 46
3339 13:31:15.054326
3340 13:31:15.054443 Set Vref, RX VrefLevel [Byte0]: 47
3341 13:31:15.057557 [Byte1]: 47
3342 13:31:15.062037
3343 13:31:15.062156 Set Vref, RX VrefLevel [Byte0]: 48
3344 13:31:15.065395 [Byte1]: 48
3345 13:31:15.070232
3346 13:31:15.070352 Set Vref, RX VrefLevel [Byte0]: 49
3347 13:31:15.073540 [Byte1]: 49
3348 13:31:15.077841
3349 13:31:15.077961 Set Vref, RX VrefLevel [Byte0]: 50
3350 13:31:15.081373 [Byte1]: 50
3351 13:31:15.085868
3352 13:31:15.085992 Set Vref, RX VrefLevel [Byte0]: 51
3353 13:31:15.089189 [Byte1]: 51
3354 13:31:15.093876
3355 13:31:15.094004 Set Vref, RX VrefLevel [Byte0]: 52
3356 13:31:15.097160 [Byte1]: 52
3357 13:31:15.101526
3358 13:31:15.101642 Set Vref, RX VrefLevel [Byte0]: 53
3359 13:31:15.104918 [Byte1]: 53
3360 13:31:15.109620
3361 13:31:15.109735 Set Vref, RX VrefLevel [Byte0]: 54
3362 13:31:15.112906 [Byte1]: 54
3363 13:31:15.117413
3364 13:31:15.117536 Set Vref, RX VrefLevel [Byte0]: 55
3365 13:31:15.120534 [Byte1]: 55
3366 13:31:15.125325
3367 13:31:15.125432 Set Vref, RX VrefLevel [Byte0]: 56
3368 13:31:15.128491 [Byte1]: 56
3369 13:31:15.133183
3370 13:31:15.133265 Set Vref, RX VrefLevel [Byte0]: 57
3371 13:31:15.136498 [Byte1]: 57
3372 13:31:15.141186
3373 13:31:15.141270 Set Vref, RX VrefLevel [Byte0]: 58
3374 13:31:15.144063 [Byte1]: 58
3375 13:31:15.148933
3376 13:31:15.149015 Set Vref, RX VrefLevel [Byte0]: 59
3377 13:31:15.152500 [Byte1]: 59
3378 13:31:15.156799
3379 13:31:15.156882 Set Vref, RX VrefLevel [Byte0]: 60
3380 13:31:15.159961 [Byte1]: 60
3381 13:31:15.164997
3382 13:31:15.165078 Set Vref, RX VrefLevel [Byte0]: 61
3383 13:31:15.167743 [Byte1]: 61
3384 13:31:15.172440
3385 13:31:15.172521 Set Vref, RX VrefLevel [Byte0]: 62
3386 13:31:15.175743 [Byte1]: 62
3387 13:31:15.180247
3388 13:31:15.180329 Set Vref, RX VrefLevel [Byte0]: 63
3389 13:31:15.184042 [Byte1]: 63
3390 13:31:15.188227
3391 13:31:15.188311 Set Vref, RX VrefLevel [Byte0]: 64
3392 13:31:15.192005 [Byte1]: 64
3393 13:31:15.196310
3394 13:31:15.196419 Set Vref, RX VrefLevel [Byte0]: 65
3395 13:31:15.199802 [Byte1]: 65
3396 13:31:15.204187
3397 13:31:15.204267 Set Vref, RX VrefLevel [Byte0]: 66
3398 13:31:15.207489 [Byte1]: 66
3399 13:31:15.211940
3400 13:31:15.212024 Final RX Vref Byte 0 = 52 to rank0
3401 13:31:15.215332 Final RX Vref Byte 1 = 58 to rank0
3402 13:31:15.218485 Final RX Vref Byte 0 = 52 to rank1
3403 13:31:15.222087 Final RX Vref Byte 1 = 58 to rank1==
3404 13:31:15.225555 Dram Type= 6, Freq= 0, CH_1, rank 0
3405 13:31:15.231896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3406 13:31:15.232025 ==
3407 13:31:15.232138 DQS Delay:
3408 13:31:15.232249 DQS0 = 0, DQS1 = 0
3409 13:31:15.235218 DQM Delay:
3410 13:31:15.235341 DQM0 = 119, DQM1 = 113
3411 13:31:15.238505 DQ Delay:
3412 13:31:15.241974 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3413 13:31:15.245330 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =116
3414 13:31:15.248880 DQ8 =102, DQ9 =100, DQ10 =116, DQ11 =108
3415 13:31:15.252368 DQ12 =122, DQ13 =118, DQ14 =120, DQ15 =120
3416 13:31:15.252489
3417 13:31:15.252604
3418 13:31:15.258549 [DQSOSCAuto] RK0, (LSB)MR18= 0x114, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps
3419 13:31:15.261897 CH1 RK0: MR19=404, MR18=114
3420 13:31:15.268711 CH1_RK0: MR19=0x404, MR18=0x114, DQSOSC=402, MR23=63, INC=40, DEC=27
3421 13:31:15.268875
3422 13:31:15.271941 ----->DramcWriteLeveling(PI) begin...
3423 13:31:15.272036 ==
3424 13:31:15.275310 Dram Type= 6, Freq= 0, CH_1, rank 1
3425 13:31:15.278695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3426 13:31:15.278771 ==
3427 13:31:15.282134 Write leveling (Byte 0): 26 => 26
3428 13:31:15.285388 Write leveling (Byte 1): 28 => 28
3429 13:31:15.289053 DramcWriteLeveling(PI) end<-----
3430 13:31:15.289195
3431 13:31:15.289266 ==
3432 13:31:15.292329 Dram Type= 6, Freq= 0, CH_1, rank 1
3433 13:31:15.295425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3434 13:31:15.298987 ==
3435 13:31:15.299072 [Gating] SW mode calibration
3436 13:31:15.305855 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3437 13:31:15.312637 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3438 13:31:15.316324 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 13:31:15.322590 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 13:31:15.325894 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3441 13:31:15.329132 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3442 13:31:15.335703 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3443 13:31:15.339007 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3444 13:31:15.342297 0 15 24 | B1->B0 | 3030 3434 | 0 1 | (0 1) (1 0)
3445 13:31:15.349099 0 15 28 | B1->B0 | 2323 2d2d | 0 1 | (1 0) (1 0)
3446 13:31:15.352433 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 13:31:15.355782 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 13:31:15.359305 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 13:31:15.365870 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3450 13:31:15.369171 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3451 13:31:15.372471 1 0 20 | B1->B0 | 2524 2323 | 1 0 | (0 0) (0 0)
3452 13:31:15.379271 1 0 24 | B1->B0 | 3535 2727 | 0 0 | (1 1) (0 0)
3453 13:31:15.382579 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 13:31:15.386019 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 13:31:15.392566 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 13:31:15.396144 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 13:31:15.399301 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 13:31:15.406189 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 13:31:15.409362 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3460 13:31:15.412508 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3461 13:31:15.419233 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3462 13:31:15.422696 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 13:31:15.426015 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 13:31:15.429392 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 13:31:15.435804 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 13:31:15.439251 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 13:31:15.445985 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 13:31:15.449351 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 13:31:15.452683 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 13:31:15.455613 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 13:31:15.462344 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 13:31:15.465622 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 13:31:15.469266 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 13:31:15.475903 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 13:31:15.479407 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 13:31:15.482384 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3477 13:31:15.489390 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3478 13:31:15.489475 Total UI for P1: 0, mck2ui 16
3479 13:31:15.495710 best dqsien dly found for B1: ( 1, 3, 24)
3480 13:31:15.499152 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 13:31:15.502383 Total UI for P1: 0, mck2ui 16
3482 13:31:15.505627 best dqsien dly found for B0: ( 1, 3, 26)
3483 13:31:15.509013 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3484 13:31:15.512621 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3485 13:31:15.512702
3486 13:31:15.516015 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3487 13:31:15.518951 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3488 13:31:15.522233 [Gating] SW calibration Done
3489 13:31:15.522319 ==
3490 13:31:15.525632 Dram Type= 6, Freq= 0, CH_1, rank 1
3491 13:31:15.529054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3492 13:31:15.532483 ==
3493 13:31:15.532588 RX Vref Scan: 0
3494 13:31:15.532683
3495 13:31:15.536025 RX Vref 0 -> 0, step: 1
3496 13:31:15.536110
3497 13:31:15.536178 RX Delay -40 -> 252, step: 8
3498 13:31:15.542509 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3499 13:31:15.545969 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3500 13:31:15.549181 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3501 13:31:15.552499 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3502 13:31:15.555887 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3503 13:31:15.562525 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3504 13:31:15.565796 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3505 13:31:15.569313 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3506 13:31:15.572556 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3507 13:31:15.575770 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3508 13:31:15.582483 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3509 13:31:15.585355 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3510 13:31:15.588888 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3511 13:31:15.592304 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3512 13:31:15.598688 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3513 13:31:15.602026 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3514 13:31:15.602142 ==
3515 13:31:15.605779 Dram Type= 6, Freq= 0, CH_1, rank 1
3516 13:31:15.608635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3517 13:31:15.608747 ==
3518 13:31:15.608852 DQS Delay:
3519 13:31:15.612020 DQS0 = 0, DQS1 = 0
3520 13:31:15.612104 DQM Delay:
3521 13:31:15.615532 DQM0 = 120, DQM1 = 113
3522 13:31:15.615642 DQ Delay:
3523 13:31:15.618865 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =123
3524 13:31:15.622520 DQ4 =123, DQ5 =131, DQ6 =123, DQ7 =115
3525 13:31:15.625416 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3526 13:31:15.628776 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3527 13:31:15.632060
3528 13:31:15.632183
3529 13:31:15.632297 ==
3530 13:31:15.635491 Dram Type= 6, Freq= 0, CH_1, rank 1
3531 13:31:15.638824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3532 13:31:15.638952 ==
3533 13:31:15.639066
3534 13:31:15.639177
3535 13:31:15.642182 TX Vref Scan disable
3536 13:31:15.642306 == TX Byte 0 ==
3537 13:31:15.648746 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3538 13:31:15.652103 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3539 13:31:15.652226 == TX Byte 1 ==
3540 13:31:15.658848 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3541 13:31:15.662419 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3542 13:31:15.662530 ==
3543 13:31:15.665314 Dram Type= 6, Freq= 0, CH_1, rank 1
3544 13:31:15.668646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3545 13:31:15.668764 ==
3546 13:31:15.681146 TX Vref=22, minBit 1, minWin=25, winSum=417
3547 13:31:15.684583 TX Vref=24, minBit 9, minWin=25, winSum=420
3548 13:31:15.687447 TX Vref=26, minBit 1, minWin=25, winSum=428
3549 13:31:15.690823 TX Vref=28, minBit 1, minWin=26, winSum=429
3550 13:31:15.694230 TX Vref=30, minBit 1, minWin=26, winSum=429
3551 13:31:15.701154 TX Vref=32, minBit 0, minWin=26, winSum=425
3552 13:31:15.704455 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 28
3553 13:31:15.704567
3554 13:31:15.707547 Final TX Range 1 Vref 28
3555 13:31:15.707660
3556 13:31:15.707756 ==
3557 13:31:15.710757 Dram Type= 6, Freq= 0, CH_1, rank 1
3558 13:31:15.714145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3559 13:31:15.714230 ==
3560 13:31:15.717262
3561 13:31:15.717346
3562 13:31:15.717412 TX Vref Scan disable
3563 13:31:15.720913 == TX Byte 0 ==
3564 13:31:15.724026 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3565 13:31:15.727403 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3566 13:31:15.730921 == TX Byte 1 ==
3567 13:31:15.733771 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3568 13:31:15.737630 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3569 13:31:15.740517
3570 13:31:15.740629 [DATLAT]
3571 13:31:15.740726 Freq=1200, CH1 RK1
3572 13:31:15.740837
3573 13:31:15.744158 DATLAT Default: 0xd
3574 13:31:15.744271 0, 0xFFFF, sum = 0
3575 13:31:15.747433 1, 0xFFFF, sum = 0
3576 13:31:15.747538 2, 0xFFFF, sum = 0
3577 13:31:15.750684 3, 0xFFFF, sum = 0
3578 13:31:15.754063 4, 0xFFFF, sum = 0
3579 13:31:15.754173 5, 0xFFFF, sum = 0
3580 13:31:15.756919 6, 0xFFFF, sum = 0
3581 13:31:15.757033 7, 0xFFFF, sum = 0
3582 13:31:15.760680 8, 0xFFFF, sum = 0
3583 13:31:15.760792 9, 0xFFFF, sum = 0
3584 13:31:15.764190 10, 0xFFFF, sum = 0
3585 13:31:15.764304 11, 0xFFFF, sum = 0
3586 13:31:15.767275 12, 0x0, sum = 1
3587 13:31:15.767380 13, 0x0, sum = 2
3588 13:31:15.770335 14, 0x0, sum = 3
3589 13:31:15.770450 15, 0x0, sum = 4
3590 13:31:15.770548 best_step = 13
3591 13:31:15.773970
3592 13:31:15.774080 ==
3593 13:31:15.777399 Dram Type= 6, Freq= 0, CH_1, rank 1
3594 13:31:15.780759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3595 13:31:15.780862 ==
3596 13:31:15.780954 RX Vref Scan: 0
3597 13:31:15.781044
3598 13:31:15.783690 RX Vref 0 -> 0, step: 1
3599 13:31:15.783806
3600 13:31:15.787073 RX Delay -13 -> 252, step: 4
3601 13:31:15.790461 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3602 13:31:15.797035 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3603 13:31:15.800415 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3604 13:31:15.803810 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3605 13:31:15.807252 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3606 13:31:15.810481 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3607 13:31:15.817527 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3608 13:31:15.820281 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3609 13:31:15.823870 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3610 13:31:15.827150 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3611 13:31:15.830393 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3612 13:31:15.837191 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3613 13:31:15.840286 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3614 13:31:15.843787 iDelay=195, Bit 13, Center 122 (59 ~ 186) 128
3615 13:31:15.847032 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3616 13:31:15.850258 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3617 13:31:15.853618 ==
3618 13:31:15.857047 Dram Type= 6, Freq= 0, CH_1, rank 1
3619 13:31:15.860446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3620 13:31:15.860519 ==
3621 13:31:15.860581 DQS Delay:
3622 13:31:15.863838 DQS0 = 0, DQS1 = 0
3623 13:31:15.863937 DQM Delay:
3624 13:31:15.867190 DQM0 = 119, DQM1 = 114
3625 13:31:15.867289 DQ Delay:
3626 13:31:15.870568 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3627 13:31:15.874022 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3628 13:31:15.876962 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =108
3629 13:31:15.880430 DQ12 =122, DQ13 =122, DQ14 =120, DQ15 =124
3630 13:31:15.880511
3631 13:31:15.880576
3632 13:31:15.890577 [DQSOSCAuto] RK1, (LSB)MR18= 0xaef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 406 ps
3633 13:31:15.890660 CH1 RK1: MR19=403, MR18=AEF
3634 13:31:15.897312 CH1_RK1: MR19=0x403, MR18=0xAEF, DQSOSC=406, MR23=63, INC=39, DEC=26
3635 13:31:15.900654 [RxdqsGatingPostProcess] freq 1200
3636 13:31:15.906934 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3637 13:31:15.910324 best DQS0 dly(2T, 0.5T) = (0, 11)
3638 13:31:15.913649 best DQS1 dly(2T, 0.5T) = (0, 11)
3639 13:31:15.917040 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3640 13:31:15.920290 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3641 13:31:15.923357 best DQS0 dly(2T, 0.5T) = (0, 11)
3642 13:31:15.923439 best DQS1 dly(2T, 0.5T) = (0, 11)
3643 13:31:15.927025 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3644 13:31:15.930436 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3645 13:31:15.933506 Pre-setting of DQS Precalculation
3646 13:31:15.940281 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3647 13:31:15.946876 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3648 13:31:15.953274 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3649 13:31:15.953359
3650 13:31:15.953424
3651 13:31:15.956916 [Calibration Summary] 2400 Mbps
3652 13:31:15.959863 CH 0, Rank 0
3653 13:31:15.959948 SW Impedance : PASS
3654 13:31:15.963337 DUTY Scan : NO K
3655 13:31:15.963421 ZQ Calibration : PASS
3656 13:31:15.966780 Jitter Meter : NO K
3657 13:31:15.970236 CBT Training : PASS
3658 13:31:15.970346 Write leveling : PASS
3659 13:31:15.973577 RX DQS gating : PASS
3660 13:31:15.976643 RX DQ/DQS(RDDQC) : PASS
3661 13:31:15.976769 TX DQ/DQS : PASS
3662 13:31:15.980137 RX DATLAT : PASS
3663 13:31:15.983633 RX DQ/DQS(Engine): PASS
3664 13:31:15.983718 TX OE : NO K
3665 13:31:15.986746 All Pass.
3666 13:31:15.986858
3667 13:31:15.986924 CH 0, Rank 1
3668 13:31:15.990021 SW Impedance : PASS
3669 13:31:15.990104 DUTY Scan : NO K
3670 13:31:15.993527 ZQ Calibration : PASS
3671 13:31:15.996464 Jitter Meter : NO K
3672 13:31:15.996549 CBT Training : PASS
3673 13:31:15.999869 Write leveling : PASS
3674 13:31:16.003349 RX DQS gating : PASS
3675 13:31:16.003447 RX DQ/DQS(RDDQC) : PASS
3676 13:31:16.006688 TX DQ/DQS : PASS
3677 13:31:16.006771 RX DATLAT : PASS
3678 13:31:16.010042 RX DQ/DQS(Engine): PASS
3679 13:31:16.013499 TX OE : NO K
3680 13:31:16.013582 All Pass.
3681 13:31:16.013646
3682 13:31:16.013704 CH 1, Rank 0
3683 13:31:16.016900 SW Impedance : PASS
3684 13:31:16.020080 DUTY Scan : NO K
3685 13:31:16.020189 ZQ Calibration : PASS
3686 13:31:16.023427 Jitter Meter : NO K
3687 13:31:16.026972 CBT Training : PASS
3688 13:31:16.027057 Write leveling : PASS
3689 13:31:16.030404 RX DQS gating : PASS
3690 13:31:16.033119 RX DQ/DQS(RDDQC) : PASS
3691 13:31:16.033205 TX DQ/DQS : PASS
3692 13:31:16.036777 RX DATLAT : PASS
3693 13:31:16.039774 RX DQ/DQS(Engine): PASS
3694 13:31:16.039859 TX OE : NO K
3695 13:31:16.043288 All Pass.
3696 13:31:16.043372
3697 13:31:16.043439 CH 1, Rank 1
3698 13:31:16.046510 SW Impedance : PASS
3699 13:31:16.046595 DUTY Scan : NO K
3700 13:31:16.049965 ZQ Calibration : PASS
3701 13:31:16.053227 Jitter Meter : NO K
3702 13:31:16.053312 CBT Training : PASS
3703 13:31:16.056706 Write leveling : PASS
3704 13:31:16.056811 RX DQS gating : PASS
3705 13:31:16.060067 RX DQ/DQS(RDDQC) : PASS
3706 13:31:16.063098 TX DQ/DQS : PASS
3707 13:31:16.063202 RX DATLAT : PASS
3708 13:31:16.066320 RX DQ/DQS(Engine): PASS
3709 13:31:16.070204 TX OE : NO K
3710 13:31:16.070326 All Pass.
3711 13:31:16.070404
3712 13:31:16.072910 DramC Write-DBI off
3713 13:31:16.073007 PER_BANK_REFRESH: Hybrid Mode
3714 13:31:16.076445 TX_TRACKING: ON
3715 13:31:16.086419 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3716 13:31:16.089960 [FAST_K] Save calibration result to emmc
3717 13:31:16.092940 dramc_set_vcore_voltage set vcore to 650000
3718 13:31:16.093033 Read voltage for 600, 5
3719 13:31:16.096273 Vio18 = 0
3720 13:31:16.096358 Vcore = 650000
3721 13:31:16.096425 Vdram = 0
3722 13:31:16.099720 Vddq = 0
3723 13:31:16.099794 Vmddr = 0
3724 13:31:16.103020 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3725 13:31:16.109927 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3726 13:31:16.113383 MEM_TYPE=3, freq_sel=19
3727 13:31:16.116233 sv_algorithm_assistance_LP4_1600
3728 13:31:16.119703 ============ PULL DRAM RESETB DOWN ============
3729 13:31:16.123077 ========== PULL DRAM RESETB DOWN end =========
3730 13:31:16.129600 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3731 13:31:16.132912 ===================================
3732 13:31:16.132997 LPDDR4 DRAM CONFIGURATION
3733 13:31:16.136308 ===================================
3734 13:31:16.139545 EX_ROW_EN[0] = 0x0
3735 13:31:16.139630 EX_ROW_EN[1] = 0x0
3736 13:31:16.142886 LP4Y_EN = 0x0
3737 13:31:16.142971 WORK_FSP = 0x0
3738 13:31:16.146207 WL = 0x2
3739 13:31:16.149496 RL = 0x2
3740 13:31:16.149575 BL = 0x2
3741 13:31:16.153222 RPST = 0x0
3742 13:31:16.153306 RD_PRE = 0x0
3743 13:31:16.156338 WR_PRE = 0x1
3744 13:31:16.156417 WR_PST = 0x0
3745 13:31:16.159873 DBI_WR = 0x0
3746 13:31:16.159945 DBI_RD = 0x0
3747 13:31:16.162775 OTF = 0x1
3748 13:31:16.166313 ===================================
3749 13:31:16.169398 ===================================
3750 13:31:16.169484 ANA top config
3751 13:31:16.173144 ===================================
3752 13:31:16.176297 DLL_ASYNC_EN = 0
3753 13:31:16.179266 ALL_SLAVE_EN = 1
3754 13:31:16.179342 NEW_RANK_MODE = 1
3755 13:31:16.182660 DLL_IDLE_MODE = 1
3756 13:31:16.186023 LP45_APHY_COMB_EN = 1
3757 13:31:16.189438 TX_ODT_DIS = 1
3758 13:31:16.189529 NEW_8X_MODE = 1
3759 13:31:16.192702 ===================================
3760 13:31:16.196110 ===================================
3761 13:31:16.199757 data_rate = 1200
3762 13:31:16.202741 CKR = 1
3763 13:31:16.206060 DQ_P2S_RATIO = 8
3764 13:31:16.209597 ===================================
3765 13:31:16.212453 CA_P2S_RATIO = 8
3766 13:31:16.215931 DQ_CA_OPEN = 0
3767 13:31:16.219096 DQ_SEMI_OPEN = 0
3768 13:31:16.219167 CA_SEMI_OPEN = 0
3769 13:31:16.222537 CA_FULL_RATE = 0
3770 13:31:16.226021 DQ_CKDIV4_EN = 1
3771 13:31:16.229341 CA_CKDIV4_EN = 1
3772 13:31:16.232681 CA_PREDIV_EN = 0
3773 13:31:16.236100 PH8_DLY = 0
3774 13:31:16.236175 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3775 13:31:16.238958 DQ_AAMCK_DIV = 4
3776 13:31:16.242345 CA_AAMCK_DIV = 4
3777 13:31:16.245708 CA_ADMCK_DIV = 4
3778 13:31:16.249374 DQ_TRACK_CA_EN = 0
3779 13:31:16.252608 CA_PICK = 600
3780 13:31:16.252720 CA_MCKIO = 600
3781 13:31:16.255776 MCKIO_SEMI = 0
3782 13:31:16.259015 PLL_FREQ = 2288
3783 13:31:16.262357 DQ_UI_PI_RATIO = 32
3784 13:31:16.265930 CA_UI_PI_RATIO = 0
3785 13:31:16.268903 ===================================
3786 13:31:16.272436 ===================================
3787 13:31:16.275523 memory_type:LPDDR4
3788 13:31:16.275631 GP_NUM : 10
3789 13:31:16.278846 SRAM_EN : 1
3790 13:31:16.278946 MD32_EN : 0
3791 13:31:16.282339 ===================================
3792 13:31:16.286134 [ANA_INIT] >>>>>>>>>>>>>>
3793 13:31:16.289181 <<<<<< [CONFIGURE PHASE]: ANA_TX
3794 13:31:16.292416 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3795 13:31:16.295937 ===================================
3796 13:31:16.298950 data_rate = 1200,PCW = 0X5800
3797 13:31:16.302272 ===================================
3798 13:31:16.305759 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3799 13:31:16.309152 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3800 13:31:16.315487 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3801 13:31:16.318990 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3802 13:31:16.325879 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3803 13:31:16.328696 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3804 13:31:16.328810 [ANA_INIT] flow start
3805 13:31:16.332388 [ANA_INIT] PLL >>>>>>>>
3806 13:31:16.335409 [ANA_INIT] PLL <<<<<<<<
3807 13:31:16.335495 [ANA_INIT] MIDPI >>>>>>>>
3808 13:31:16.338850 [ANA_INIT] MIDPI <<<<<<<<
3809 13:31:16.342219 [ANA_INIT] DLL >>>>>>>>
3810 13:31:16.342305 [ANA_INIT] flow end
3811 13:31:16.345609 ============ LP4 DIFF to SE enter ============
3812 13:31:16.352299 ============ LP4 DIFF to SE exit ============
3813 13:31:16.352379 [ANA_INIT] <<<<<<<<<<<<<
3814 13:31:16.355869 [Flow] Enable top DCM control >>>>>
3815 13:31:16.359170 [Flow] Enable top DCM control <<<<<
3816 13:31:16.362228 Enable DLL master slave shuffle
3817 13:31:16.369144 ==============================================================
3818 13:31:16.369221 Gating Mode config
3819 13:31:16.375737 ==============================================================
3820 13:31:16.379047 Config description:
3821 13:31:16.388646 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3822 13:31:16.395763 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3823 13:31:16.398635 SELPH_MODE 0: By rank 1: By Phase
3824 13:31:16.405348 ==============================================================
3825 13:31:16.408709 GAT_TRACK_EN = 1
3826 13:31:16.412029 RX_GATING_MODE = 2
3827 13:31:16.412152 RX_GATING_TRACK_MODE = 2
3828 13:31:16.415556 SELPH_MODE = 1
3829 13:31:16.418808 PICG_EARLY_EN = 1
3830 13:31:16.422428 VALID_LAT_VALUE = 1
3831 13:31:16.428882 ==============================================================
3832 13:31:16.432300 Enter into Gating configuration >>>>
3833 13:31:16.435357 Exit from Gating configuration <<<<
3834 13:31:16.438910 Enter into DVFS_PRE_config >>>>>
3835 13:31:16.448265 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3836 13:31:16.451902 Exit from DVFS_PRE_config <<<<<
3837 13:31:16.455372 Enter into PICG configuration >>>>
3838 13:31:16.458313 Exit from PICG configuration <<<<
3839 13:31:16.461624 [RX_INPUT] configuration >>>>>
3840 13:31:16.465208 [RX_INPUT] configuration <<<<<
3841 13:31:16.468457 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3842 13:31:16.475283 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3843 13:31:16.481766 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3844 13:31:16.488757 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3845 13:31:16.491582 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3846 13:31:16.498323 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3847 13:31:16.501436 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3848 13:31:16.508459 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3849 13:31:16.511455 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3850 13:31:16.514934 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3851 13:31:16.518365 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3852 13:31:16.524746 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3853 13:31:16.528199 ===================================
3854 13:31:16.528316 LPDDR4 DRAM CONFIGURATION
3855 13:31:16.531613 ===================================
3856 13:31:16.535045 EX_ROW_EN[0] = 0x0
3857 13:31:16.538491 EX_ROW_EN[1] = 0x0
3858 13:31:16.538593 LP4Y_EN = 0x0
3859 13:31:16.541507 WORK_FSP = 0x0
3860 13:31:16.541590 WL = 0x2
3861 13:31:16.544902 RL = 0x2
3862 13:31:16.544984 BL = 0x2
3863 13:31:16.548346 RPST = 0x0
3864 13:31:16.548456 RD_PRE = 0x0
3865 13:31:16.551677 WR_PRE = 0x1
3866 13:31:16.551785 WR_PST = 0x0
3867 13:31:16.555318 DBI_WR = 0x0
3868 13:31:16.555426 DBI_RD = 0x0
3869 13:31:16.558013 OTF = 0x1
3870 13:31:16.561867 ===================================
3871 13:31:16.564934 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3872 13:31:16.568554 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3873 13:31:16.575090 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3874 13:31:16.578527 ===================================
3875 13:31:16.578610 LPDDR4 DRAM CONFIGURATION
3876 13:31:16.581841 ===================================
3877 13:31:16.585242 EX_ROW_EN[0] = 0x10
3878 13:31:16.585324 EX_ROW_EN[1] = 0x0
3879 13:31:16.588057 LP4Y_EN = 0x0
3880 13:31:16.591780 WORK_FSP = 0x0
3881 13:31:16.591879 WL = 0x2
3882 13:31:16.594806 RL = 0x2
3883 13:31:16.594888 BL = 0x2
3884 13:31:16.598123 RPST = 0x0
3885 13:31:16.598204 RD_PRE = 0x0
3886 13:31:16.601649 WR_PRE = 0x1
3887 13:31:16.601731 WR_PST = 0x0
3888 13:31:16.604841 DBI_WR = 0x0
3889 13:31:16.604922 DBI_RD = 0x0
3890 13:31:16.608206 OTF = 0x1
3891 13:31:16.611336 ===================================
3892 13:31:16.617854 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3893 13:31:16.621325 nWR fixed to 30
3894 13:31:16.621421 [ModeRegInit_LP4] CH0 RK0
3895 13:31:16.624909 [ModeRegInit_LP4] CH0 RK1
3896 13:31:16.627819 [ModeRegInit_LP4] CH1 RK0
3897 13:31:16.631061 [ModeRegInit_LP4] CH1 RK1
3898 13:31:16.631178 match AC timing 17
3899 13:31:16.634519 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3900 13:31:16.641015 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3901 13:31:16.644748 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3902 13:31:16.647576 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3903 13:31:16.654428 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3904 13:31:16.654510 ==
3905 13:31:16.657616 Dram Type= 6, Freq= 0, CH_0, rank 0
3906 13:31:16.661021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3907 13:31:16.661161 ==
3908 13:31:16.667471 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3909 13:31:16.674427 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3910 13:31:16.677618 [CA 0] Center 36 (6~67) winsize 62
3911 13:31:16.680999 [CA 1] Center 36 (6~67) winsize 62
3912 13:31:16.684048 [CA 2] Center 34 (4~65) winsize 62
3913 13:31:16.687729 [CA 3] Center 34 (3~65) winsize 63
3914 13:31:16.690507 [CA 4] Center 33 (3~64) winsize 62
3915 13:31:16.693989 [CA 5] Center 33 (3~64) winsize 62
3916 13:31:16.694124
3917 13:31:16.696950 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3918 13:31:16.697094
3919 13:31:16.700522 [CATrainingPosCal] consider 1 rank data
3920 13:31:16.703743 u2DelayCellTimex100 = 270/100 ps
3921 13:31:16.707141 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3922 13:31:16.710479 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3923 13:31:16.714049 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3924 13:31:16.717011 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3925 13:31:16.720360 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3926 13:31:16.723613 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3927 13:31:16.723697
3928 13:31:16.730452 CA PerBit enable=1, Macro0, CA PI delay=33
3929 13:31:16.730566
3930 13:31:16.730665 [CBTSetCACLKResult] CA Dly = 33
3931 13:31:16.733542 CS Dly: 4 (0~35)
3932 13:31:16.733643 ==
3933 13:31:16.737178 Dram Type= 6, Freq= 0, CH_0, rank 1
3934 13:31:16.740465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3935 13:31:16.740550 ==
3936 13:31:16.747065 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3937 13:31:16.753481 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3938 13:31:16.757012 [CA 0] Center 36 (6~67) winsize 62
3939 13:31:16.759982 [CA 1] Center 36 (6~67) winsize 62
3940 13:31:16.763577 [CA 2] Center 34 (4~65) winsize 62
3941 13:31:16.766877 [CA 3] Center 34 (4~65) winsize 62
3942 13:31:16.770057 [CA 4] Center 34 (3~65) winsize 63
3943 13:31:16.773359 [CA 5] Center 33 (3~64) winsize 62
3944 13:31:16.773445
3945 13:31:16.776950 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3946 13:31:16.777035
3947 13:31:16.780305 [CATrainingPosCal] consider 2 rank data
3948 13:31:16.783554 u2DelayCellTimex100 = 270/100 ps
3949 13:31:16.787019 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3950 13:31:16.789960 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3951 13:31:16.793251 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3952 13:31:16.796467 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3953 13:31:16.799861 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3954 13:31:16.806366 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3955 13:31:16.806481
3956 13:31:16.809798 CA PerBit enable=1, Macro0, CA PI delay=33
3957 13:31:16.809910
3958 13:31:16.813458 [CBTSetCACLKResult] CA Dly = 33
3959 13:31:16.813537 CS Dly: 5 (0~38)
3960 13:31:16.813603
3961 13:31:16.816474 ----->DramcWriteLeveling(PI) begin...
3962 13:31:16.816576 ==
3963 13:31:16.819909 Dram Type= 6, Freq= 0, CH_0, rank 0
3964 13:31:16.826580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3965 13:31:16.826698 ==
3966 13:31:16.829764 Write leveling (Byte 0): 35 => 35
3967 13:31:16.829851 Write leveling (Byte 1): 30 => 30
3968 13:31:16.833087 DramcWriteLeveling(PI) end<-----
3969 13:31:16.833172
3970 13:31:16.836507 ==
3971 13:31:16.836593 Dram Type= 6, Freq= 0, CH_0, rank 0
3972 13:31:16.843084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3973 13:31:16.843203 ==
3974 13:31:16.846260 [Gating] SW mode calibration
3975 13:31:16.853392 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3976 13:31:16.856648 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3977 13:31:16.863065 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3978 13:31:16.866325 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3979 13:31:16.869661 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3980 13:31:16.876138 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
3981 13:31:16.879605 0 9 16 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
3982 13:31:16.883352 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 13:31:16.889523 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 13:31:16.893028 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 13:31:16.896331 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 13:31:16.899802 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 13:31:16.906430 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 13:31:16.909744 0 10 12 | B1->B0 | 2d2d 3f3f | 0 0 | (0 0) (0 0)
3989 13:31:16.913101 0 10 16 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
3990 13:31:16.919751 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 13:31:16.922786 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 13:31:16.925956 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 13:31:16.932567 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 13:31:16.936144 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 13:31:16.939638 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 13:31:16.945997 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 13:31:16.949437 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3998 13:31:16.952822 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 13:31:16.959076 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 13:31:16.962860 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 13:31:16.965849 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 13:31:16.972822 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 13:31:16.975973 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 13:31:16.979443 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 13:31:16.985977 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 13:31:16.989246 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 13:31:16.992695 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 13:31:16.999501 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 13:31:17.002406 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 13:31:17.006003 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 13:31:17.012703 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 13:31:17.015847 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4013 13:31:17.019013 Total UI for P1: 0, mck2ui 16
4014 13:31:17.022423 best dqsien dly found for B0: ( 0, 13, 10)
4015 13:31:17.026154 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4016 13:31:17.029030 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 13:31:17.032575 Total UI for P1: 0, mck2ui 16
4018 13:31:17.035859 best dqsien dly found for B1: ( 0, 13, 14)
4019 13:31:17.039164 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4020 13:31:17.046025 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4021 13:31:17.046134
4022 13:31:17.049404 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4023 13:31:17.052225 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4024 13:31:17.055706 [Gating] SW calibration Done
4025 13:31:17.055821 ==
4026 13:31:17.059034 Dram Type= 6, Freq= 0, CH_0, rank 0
4027 13:31:17.062517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4028 13:31:17.062623 ==
4029 13:31:17.065790 RX Vref Scan: 0
4030 13:31:17.065900
4031 13:31:17.066008 RX Vref 0 -> 0, step: 1
4032 13:31:17.066102
4033 13:31:17.068698 RX Delay -230 -> 252, step: 16
4034 13:31:17.072486 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4035 13:31:17.078745 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4036 13:31:17.081981 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4037 13:31:17.085515 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4038 13:31:17.088782 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4039 13:31:17.095482 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4040 13:31:17.098905 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4041 13:31:17.102298 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4042 13:31:17.105723 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4043 13:31:17.108842 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4044 13:31:17.115456 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4045 13:31:17.118763 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4046 13:31:17.121749 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4047 13:31:17.125550 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4048 13:31:17.131799 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4049 13:31:17.135113 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4050 13:31:17.135204 ==
4051 13:31:17.138732 Dram Type= 6, Freq= 0, CH_0, rank 0
4052 13:31:17.141915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4053 13:31:17.142000 ==
4054 13:31:17.145280 DQS Delay:
4055 13:31:17.145364 DQS0 = 0, DQS1 = 0
4056 13:31:17.145431 DQM Delay:
4057 13:31:17.148456 DQM0 = 53, DQM1 = 42
4058 13:31:17.148567 DQ Delay:
4059 13:31:17.152001 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4060 13:31:17.155396 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4061 13:31:17.158816 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4062 13:31:17.162079 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4063 13:31:17.162164
4064 13:31:17.162230
4065 13:31:17.162291 ==
4066 13:31:17.165208 Dram Type= 6, Freq= 0, CH_0, rank 0
4067 13:31:17.171933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4068 13:31:17.172018 ==
4069 13:31:17.172084
4070 13:31:17.172146
4071 13:31:17.172205 TX Vref Scan disable
4072 13:31:17.175511 == TX Byte 0 ==
4073 13:31:17.178748 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4074 13:31:17.185686 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4075 13:31:17.185771 == TX Byte 1 ==
4076 13:31:17.189085 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4077 13:31:17.195875 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4078 13:31:17.195958 ==
4079 13:31:17.198749 Dram Type= 6, Freq= 0, CH_0, rank 0
4080 13:31:17.202235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4081 13:31:17.202338 ==
4082 13:31:17.202464
4083 13:31:17.202596
4084 13:31:17.205475 TX Vref Scan disable
4085 13:31:17.208860 == TX Byte 0 ==
4086 13:31:17.212073 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4087 13:31:17.215447 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4088 13:31:17.218984 == TX Byte 1 ==
4089 13:31:17.221847 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4090 13:31:17.225483 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4091 13:31:17.225581
4092 13:31:17.225677 [DATLAT]
4093 13:31:17.228591 Freq=600, CH0 RK0
4094 13:31:17.228702
4095 13:31:17.228821 DATLAT Default: 0x9
4096 13:31:17.232014 0, 0xFFFF, sum = 0
4097 13:31:17.232113 1, 0xFFFF, sum = 0
4098 13:31:17.235466 2, 0xFFFF, sum = 0
4099 13:31:17.238925 3, 0xFFFF, sum = 0
4100 13:31:17.239037 4, 0xFFFF, sum = 0
4101 13:31:17.242150 5, 0xFFFF, sum = 0
4102 13:31:17.242234 6, 0xFFFF, sum = 0
4103 13:31:17.245320 7, 0xFFFF, sum = 0
4104 13:31:17.245404 8, 0x0, sum = 1
4105 13:31:17.245470 9, 0x0, sum = 2
4106 13:31:17.248619 10, 0x0, sum = 3
4107 13:31:17.248717 11, 0x0, sum = 4
4108 13:31:17.251825 best_step = 9
4109 13:31:17.251908
4110 13:31:17.251973 ==
4111 13:31:17.255525 Dram Type= 6, Freq= 0, CH_0, rank 0
4112 13:31:17.258830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4113 13:31:17.258913 ==
4114 13:31:17.262225 RX Vref Scan: 1
4115 13:31:17.262307
4116 13:31:17.262371 RX Vref 0 -> 0, step: 1
4117 13:31:17.262432
4118 13:31:17.265674 RX Delay -179 -> 252, step: 8
4119 13:31:17.265760
4120 13:31:17.268725 Set Vref, RX VrefLevel [Byte0]: 59
4121 13:31:17.272022 [Byte1]: 50
4122 13:31:17.275981
4123 13:31:17.276064 Final RX Vref Byte 0 = 59 to rank0
4124 13:31:17.279418 Final RX Vref Byte 1 = 50 to rank0
4125 13:31:17.282518 Final RX Vref Byte 0 = 59 to rank1
4126 13:31:17.285934 Final RX Vref Byte 1 = 50 to rank1==
4127 13:31:17.289288 Dram Type= 6, Freq= 0, CH_0, rank 0
4128 13:31:17.296036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4129 13:31:17.296119 ==
4130 13:31:17.296185 DQS Delay:
4131 13:31:17.299276 DQS0 = 0, DQS1 = 0
4132 13:31:17.299358 DQM Delay:
4133 13:31:17.299424 DQM0 = 50, DQM1 = 37
4134 13:31:17.302616 DQ Delay:
4135 13:31:17.305905 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =48
4136 13:31:17.309655 DQ4 =52, DQ5 =40, DQ6 =64, DQ7 =56
4137 13:31:17.312672 DQ8 =32, DQ9 =24, DQ10 =36, DQ11 =32
4138 13:31:17.315940 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4139 13:31:17.316023
4140 13:31:17.316088
4141 13:31:17.322581 [DQSOSCAuto] RK0, (LSB)MR18= 0x524d, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
4142 13:31:17.325904 CH0 RK0: MR19=808, MR18=524D
4143 13:31:17.332543 CH0_RK0: MR19=0x808, MR18=0x524D, DQSOSC=394, MR23=63, INC=168, DEC=112
4144 13:31:17.332628
4145 13:31:17.335969 ----->DramcWriteLeveling(PI) begin...
4146 13:31:17.336053 ==
4147 13:31:17.339310 Dram Type= 6, Freq= 0, CH_0, rank 1
4148 13:31:17.342692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 13:31:17.342776 ==
4150 13:31:17.345627 Write leveling (Byte 0): 35 => 35
4151 13:31:17.348989 Write leveling (Byte 1): 31 => 31
4152 13:31:17.352640 DramcWriteLeveling(PI) end<-----
4153 13:31:17.352723
4154 13:31:17.352826 ==
4155 13:31:17.355812 Dram Type= 6, Freq= 0, CH_0, rank 1
4156 13:31:17.359563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4157 13:31:17.359646 ==
4158 13:31:17.362431 [Gating] SW mode calibration
4159 13:31:17.368942 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4160 13:31:17.375846 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4161 13:31:17.379213 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4162 13:31:17.382306 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4163 13:31:17.389196 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4164 13:31:17.392445 0 9 12 | B1->B0 | 3131 3131 | 0 1 | (0 1) (1 0)
4165 13:31:17.395883 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4166 13:31:17.402557 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 13:31:17.405856 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 13:31:17.408984 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 13:31:17.415951 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 13:31:17.419392 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 13:31:17.422313 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 13:31:17.429182 0 10 12 | B1->B0 | 2e2e 3030 | 0 0 | (1 1) (0 0)
4173 13:31:17.432484 0 10 16 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
4174 13:31:17.435897 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 13:31:17.442392 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 13:31:17.445829 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 13:31:17.449124 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 13:31:17.455852 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 13:31:17.459203 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 13:31:17.462687 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 13:31:17.468854 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 13:31:17.472186 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 13:31:17.475727 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 13:31:17.478950 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 13:31:17.485916 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 13:31:17.489054 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 13:31:17.492328 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 13:31:17.498906 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 13:31:17.502309 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 13:31:17.505656 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 13:31:17.512235 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 13:31:17.515793 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 13:31:17.519142 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 13:31:17.525904 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 13:31:17.528701 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 13:31:17.532133 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4197 13:31:17.538843 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 13:31:17.538969 Total UI for P1: 0, mck2ui 16
4199 13:31:17.545657 best dqsien dly found for B0: ( 0, 13, 12)
4200 13:31:17.545785 Total UI for P1: 0, mck2ui 16
4201 13:31:17.551986 best dqsien dly found for B1: ( 0, 13, 14)
4202 13:31:17.555289 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4203 13:31:17.558466 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4204 13:31:17.558591
4205 13:31:17.562339 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4206 13:31:17.565185 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4207 13:31:17.569124 [Gating] SW calibration Done
4208 13:31:17.569209 ==
4209 13:31:17.572213 Dram Type= 6, Freq= 0, CH_0, rank 1
4210 13:31:17.575454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4211 13:31:17.575538 ==
4212 13:31:17.578625 RX Vref Scan: 0
4213 13:31:17.578708
4214 13:31:17.578774 RX Vref 0 -> 0, step: 1
4215 13:31:17.578835
4216 13:31:17.582076 RX Delay -230 -> 252, step: 16
4217 13:31:17.588715 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4218 13:31:17.592108 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4219 13:31:17.595100 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4220 13:31:17.598761 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4221 13:31:17.602055 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4222 13:31:17.608502 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4223 13:31:17.611581 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4224 13:31:17.615070 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4225 13:31:17.618408 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4226 13:31:17.625412 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4227 13:31:17.628487 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4228 13:31:17.631917 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4229 13:31:17.635531 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4230 13:31:17.641961 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4231 13:31:17.645342 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4232 13:31:17.648623 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4233 13:31:17.648712 ==
4234 13:31:17.651585 Dram Type= 6, Freq= 0, CH_0, rank 1
4235 13:31:17.655024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4236 13:31:17.655101 ==
4237 13:31:17.658454 DQS Delay:
4238 13:31:17.658551 DQS0 = 0, DQS1 = 0
4239 13:31:17.661752 DQM Delay:
4240 13:31:17.661851 DQM0 = 47, DQM1 = 40
4241 13:31:17.661959 DQ Delay:
4242 13:31:17.664922 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4243 13:31:17.668310 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4244 13:31:17.671787 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4245 13:31:17.674901 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =41
4246 13:31:17.674984
4247 13:31:17.675068
4248 13:31:17.678561 ==
4249 13:31:17.678644 Dram Type= 6, Freq= 0, CH_0, rank 1
4250 13:31:17.684874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4251 13:31:17.684963 ==
4252 13:31:17.685029
4253 13:31:17.685091
4254 13:31:17.687976 TX Vref Scan disable
4255 13:31:17.688054 == TX Byte 0 ==
4256 13:31:17.691657 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4257 13:31:17.698362 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4258 13:31:17.698446 == TX Byte 1 ==
4259 13:31:17.701771 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4260 13:31:17.708434 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4261 13:31:17.708522 ==
4262 13:31:17.711879 Dram Type= 6, Freq= 0, CH_0, rank 1
4263 13:31:17.714808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4264 13:31:17.714891 ==
4265 13:31:17.714955
4266 13:31:17.715015
4267 13:31:17.718102 TX Vref Scan disable
4268 13:31:17.721521 == TX Byte 0 ==
4269 13:31:17.725046 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4270 13:31:17.728495 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4271 13:31:17.731656 == TX Byte 1 ==
4272 13:31:17.734782 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4273 13:31:17.738427 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4274 13:31:17.738510
4275 13:31:17.741353 [DATLAT]
4276 13:31:17.741434 Freq=600, CH0 RK1
4277 13:31:17.741499
4278 13:31:17.744797 DATLAT Default: 0x9
4279 13:31:17.744894 0, 0xFFFF, sum = 0
4280 13:31:17.748052 1, 0xFFFF, sum = 0
4281 13:31:17.748138 2, 0xFFFF, sum = 0
4282 13:31:17.751679 3, 0xFFFF, sum = 0
4283 13:31:17.751771 4, 0xFFFF, sum = 0
4284 13:31:17.754930 5, 0xFFFF, sum = 0
4285 13:31:17.755014 6, 0xFFFF, sum = 0
4286 13:31:17.757946 7, 0xFFFF, sum = 0
4287 13:31:17.758063 8, 0x0, sum = 1
4288 13:31:17.761211 9, 0x0, sum = 2
4289 13:31:17.761288 10, 0x0, sum = 3
4290 13:31:17.764828 11, 0x0, sum = 4
4291 13:31:17.764901 best_step = 9
4292 13:31:17.764962
4293 13:31:17.765019 ==
4294 13:31:17.767854 Dram Type= 6, Freq= 0, CH_0, rank 1
4295 13:31:17.771196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4296 13:31:17.774665 ==
4297 13:31:17.774774 RX Vref Scan: 0
4298 13:31:17.774865
4299 13:31:17.778053 RX Vref 0 -> 0, step: 1
4300 13:31:17.778160
4301 13:31:17.781559 RX Delay -179 -> 252, step: 8
4302 13:31:17.784905 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4303 13:31:17.788272 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4304 13:31:17.794478 iDelay=205, Bit 2, Center 48 (-99 ~ 196) 296
4305 13:31:17.797979 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4306 13:31:17.801124 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4307 13:31:17.804368 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4308 13:31:17.808386 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4309 13:31:17.814488 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4310 13:31:17.817795 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4311 13:31:17.821228 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4312 13:31:17.824296 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4313 13:31:17.827936 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4314 13:31:17.834391 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4315 13:31:17.837776 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280
4316 13:31:17.841248 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4317 13:31:17.844579 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4318 13:31:17.844703 ==
4319 13:31:17.847951 Dram Type= 6, Freq= 0, CH_0, rank 1
4320 13:31:17.854221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4321 13:31:17.854343 ==
4322 13:31:17.854453 DQS Delay:
4323 13:31:17.857614 DQS0 = 0, DQS1 = 0
4324 13:31:17.857728 DQM Delay:
4325 13:31:17.857838 DQM0 = 48, DQM1 = 41
4326 13:31:17.860889 DQ Delay:
4327 13:31:17.864297 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =44
4328 13:31:17.867720 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4329 13:31:17.870934 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4330 13:31:17.874605 DQ12 =48, DQ13 =48, DQ14 =52, DQ15 =52
4331 13:31:17.874728
4332 13:31:17.874832
4333 13:31:17.880934 [DQSOSCAuto] RK1, (LSB)MR18= 0x5e2d, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
4334 13:31:17.884152 CH0 RK1: MR19=808, MR18=5E2D
4335 13:31:17.890759 CH0_RK1: MR19=0x808, MR18=0x5E2D, DQSOSC=392, MR23=63, INC=170, DEC=113
4336 13:31:17.894268 [RxdqsGatingPostProcess] freq 600
4337 13:31:17.897432 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4338 13:31:17.900763 Pre-setting of DQS Precalculation
4339 13:31:17.907471 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4340 13:31:17.907592 ==
4341 13:31:17.910806 Dram Type= 6, Freq= 0, CH_1, rank 0
4342 13:31:17.914431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4343 13:31:17.914560 ==
4344 13:31:17.920978 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4345 13:31:17.927833 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4346 13:31:17.930697 [CA 0] Center 35 (5~66) winsize 62
4347 13:31:17.934035 [CA 1] Center 35 (5~66) winsize 62
4348 13:31:17.937563 [CA 2] Center 34 (4~65) winsize 62
4349 13:31:17.940628 [CA 3] Center 34 (3~65) winsize 63
4350 13:31:17.943893 [CA 4] Center 34 (4~65) winsize 62
4351 13:31:17.947236 [CA 5] Center 34 (3~65) winsize 63
4352 13:31:17.947356
4353 13:31:17.950571 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4354 13:31:17.950674
4355 13:31:17.953908 [CATrainingPosCal] consider 1 rank data
4356 13:31:17.957351 u2DelayCellTimex100 = 270/100 ps
4357 13:31:17.960936 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4358 13:31:17.964345 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4359 13:31:17.967534 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4360 13:31:17.970840 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4361 13:31:17.974375 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4362 13:31:17.977344 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4363 13:31:17.977471
4364 13:31:17.980440 CA PerBit enable=1, Macro0, CA PI delay=34
4365 13:31:17.980558
4366 13:31:17.983736 [CBTSetCACLKResult] CA Dly = 34
4367 13:31:17.987219 CS Dly: 4 (0~35)
4368 13:31:17.987345 ==
4369 13:31:17.990928 Dram Type= 6, Freq= 0, CH_1, rank 1
4370 13:31:17.994038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4371 13:31:17.994169 ==
4372 13:31:18.000588 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4373 13:31:18.007505 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4374 13:31:18.010808 [CA 0] Center 35 (5~66) winsize 62
4375 13:31:18.013943 [CA 1] Center 36 (5~67) winsize 63
4376 13:31:18.017236 [CA 2] Center 34 (4~65) winsize 62
4377 13:31:18.020684 [CA 3] Center 34 (4~65) winsize 62
4378 13:31:18.024019 [CA 4] Center 34 (4~65) winsize 62
4379 13:31:18.027118 [CA 5] Center 34 (3~65) winsize 63
4380 13:31:18.027224
4381 13:31:18.030781 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4382 13:31:18.030862
4383 13:31:18.034211 [CATrainingPosCal] consider 2 rank data
4384 13:31:18.037024 u2DelayCellTimex100 = 270/100 ps
4385 13:31:18.040426 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4386 13:31:18.043812 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4387 13:31:18.047353 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4388 13:31:18.050451 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4389 13:31:18.053930 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4390 13:31:18.057394 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4391 13:31:18.057481
4392 13:31:18.060532 CA PerBit enable=1, Macro0, CA PI delay=34
4393 13:31:18.060643
4394 13:31:18.064004 [CBTSetCACLKResult] CA Dly = 34
4395 13:31:18.067432 CS Dly: 4 (0~36)
4396 13:31:18.067519
4397 13:31:18.070385 ----->DramcWriteLeveling(PI) begin...
4398 13:31:18.070473 ==
4399 13:31:18.073877 Dram Type= 6, Freq= 0, CH_1, rank 0
4400 13:31:18.077279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4401 13:31:18.077366 ==
4402 13:31:18.080412 Write leveling (Byte 0): 28 => 28
4403 13:31:18.084283 Write leveling (Byte 1): 29 => 29
4404 13:31:18.087131 DramcWriteLeveling(PI) end<-----
4405 13:31:18.087259
4406 13:31:18.087370 ==
4407 13:31:18.090489 Dram Type= 6, Freq= 0, CH_1, rank 0
4408 13:31:18.094106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4409 13:31:18.094232 ==
4410 13:31:18.097181 [Gating] SW mode calibration
4411 13:31:18.103912 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4412 13:31:18.110371 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4413 13:31:18.113542 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4414 13:31:18.120395 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4415 13:31:18.123924 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4416 13:31:18.127250 0 9 12 | B1->B0 | 2e2e 2f2f | 1 1 | (1 1) (1 0)
4417 13:31:18.130584 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 13:31:18.137468 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 13:31:18.140355 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 13:31:18.143915 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 13:31:18.150450 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 13:31:18.154143 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 13:31:18.157206 0 10 8 | B1->B0 | 2525 2626 | 0 0 | (0 0) (0 0)
4424 13:31:18.164159 0 10 12 | B1->B0 | 3a3a 3c3c | 0 0 | (0 0) (0 0)
4425 13:31:18.167652 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 13:31:18.170596 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 13:31:18.177412 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 13:31:18.180350 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 13:31:18.184092 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 13:31:18.190559 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 13:31:18.193829 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 13:31:18.197401 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4433 13:31:18.203783 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 13:31:18.207691 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 13:31:18.210325 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 13:31:18.213784 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 13:31:18.220879 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 13:31:18.223706 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 13:31:18.227214 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 13:31:18.233959 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 13:31:18.237176 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 13:31:18.240513 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 13:31:18.247032 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 13:31:18.250350 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 13:31:18.253640 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 13:31:18.260204 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 13:31:18.263663 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4448 13:31:18.266942 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4449 13:31:18.270298 Total UI for P1: 0, mck2ui 16
4450 13:31:18.273612 best dqsien dly found for B0: ( 0, 13, 8)
4451 13:31:18.280492 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 13:31:18.280574 Total UI for P1: 0, mck2ui 16
4453 13:31:18.286847 best dqsien dly found for B1: ( 0, 13, 10)
4454 13:31:18.290408 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4455 13:31:18.293441 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4456 13:31:18.293523
4457 13:31:18.296699 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4458 13:31:18.300171 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4459 13:31:18.303582 [Gating] SW calibration Done
4460 13:31:18.303664 ==
4461 13:31:18.306920 Dram Type= 6, Freq= 0, CH_1, rank 0
4462 13:31:18.310327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4463 13:31:18.310484 ==
4464 13:31:18.313717 RX Vref Scan: 0
4465 13:31:18.313870
4466 13:31:18.313983 RX Vref 0 -> 0, step: 1
4467 13:31:18.314092
4468 13:31:18.317000 RX Delay -230 -> 252, step: 16
4469 13:31:18.320401 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4470 13:31:18.327041 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4471 13:31:18.330123 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4472 13:31:18.333877 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4473 13:31:18.337306 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4474 13:31:18.343311 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4475 13:31:18.346827 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4476 13:31:18.350110 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4477 13:31:18.353504 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4478 13:31:18.356827 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4479 13:31:18.363531 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4480 13:31:18.366563 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4481 13:31:18.369824 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4482 13:31:18.373167 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4483 13:31:18.380060 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4484 13:31:18.383382 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4485 13:31:18.383503 ==
4486 13:31:18.386685 Dram Type= 6, Freq= 0, CH_1, rank 0
4487 13:31:18.389695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4488 13:31:18.389826 ==
4489 13:31:18.393293 DQS Delay:
4490 13:31:18.393417 DQS0 = 0, DQS1 = 0
4491 13:31:18.393536 DQM Delay:
4492 13:31:18.396908 DQM0 = 50, DQM1 = 39
4493 13:31:18.397035 DQ Delay:
4494 13:31:18.399652 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4495 13:31:18.403015 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4496 13:31:18.406332 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4497 13:31:18.409933 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4498 13:31:18.410016
4499 13:31:18.410081
4500 13:31:18.410145 ==
4501 13:31:18.413549 Dram Type= 6, Freq= 0, CH_1, rank 0
4502 13:31:18.419796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4503 13:31:18.419895 ==
4504 13:31:18.419961
4505 13:31:18.420025
4506 13:31:18.420083 TX Vref Scan disable
4507 13:31:18.423316 == TX Byte 0 ==
4508 13:31:18.426824 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4509 13:31:18.430211 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4510 13:31:18.433855 == TX Byte 1 ==
4511 13:31:18.437131 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4512 13:31:18.440062 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4513 13:31:18.443552 ==
4514 13:31:18.447436 Dram Type= 6, Freq= 0, CH_1, rank 0
4515 13:31:18.450613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4516 13:31:18.450695 ==
4517 13:31:18.450781
4518 13:31:18.450863
4519 13:31:18.453480 TX Vref Scan disable
4520 13:31:18.453572 == TX Byte 0 ==
4521 13:31:18.460275 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4522 13:31:18.463649 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4523 13:31:18.463768 == TX Byte 1 ==
4524 13:31:18.470000 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4525 13:31:18.473173 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4526 13:31:18.473328
4527 13:31:18.473478 [DATLAT]
4528 13:31:18.477030 Freq=600, CH1 RK0
4529 13:31:18.477155
4530 13:31:18.477273 DATLAT Default: 0x9
4531 13:31:18.480253 0, 0xFFFF, sum = 0
4532 13:31:18.480382 1, 0xFFFF, sum = 0
4533 13:31:18.483156 2, 0xFFFF, sum = 0
4534 13:31:18.486577 3, 0xFFFF, sum = 0
4535 13:31:18.486707 4, 0xFFFF, sum = 0
4536 13:31:18.489940 5, 0xFFFF, sum = 0
4537 13:31:18.490067 6, 0xFFFF, sum = 0
4538 13:31:18.493420 7, 0xFFFF, sum = 0
4539 13:31:18.493544 8, 0x0, sum = 1
4540 13:31:18.493665 9, 0x0, sum = 2
4541 13:31:18.496558 10, 0x0, sum = 3
4542 13:31:18.496683 11, 0x0, sum = 4
4543 13:31:18.499892 best_step = 9
4544 13:31:18.500015
4545 13:31:18.500122 ==
4546 13:31:18.503247 Dram Type= 6, Freq= 0, CH_1, rank 0
4547 13:31:18.506718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4548 13:31:18.506846 ==
4549 13:31:18.509890 RX Vref Scan: 1
4550 13:31:18.510014
4551 13:31:18.510124 RX Vref 0 -> 0, step: 1
4552 13:31:18.510230
4553 13:31:18.513379 RX Delay -179 -> 252, step: 8
4554 13:31:18.513503
4555 13:31:18.516848 Set Vref, RX VrefLevel [Byte0]: 52
4556 13:31:18.519881 [Byte1]: 58
4557 13:31:18.523748
4558 13:31:18.523851 Final RX Vref Byte 0 = 52 to rank0
4559 13:31:18.527348 Final RX Vref Byte 1 = 58 to rank0
4560 13:31:18.530779 Final RX Vref Byte 0 = 52 to rank1
4561 13:31:18.533943 Final RX Vref Byte 1 = 58 to rank1==
4562 13:31:18.537383 Dram Type= 6, Freq= 0, CH_1, rank 0
4563 13:31:18.543820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4564 13:31:18.543908 ==
4565 13:31:18.543994 DQS Delay:
4566 13:31:18.544074 DQS0 = 0, DQS1 = 0
4567 13:31:18.547418 DQM Delay:
4568 13:31:18.547504 DQM0 = 48, DQM1 = 39
4569 13:31:18.550570 DQ Delay:
4570 13:31:18.554023 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4571 13:31:18.557216 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =44
4572 13:31:18.560976 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4573 13:31:18.564002 DQ12 =52, DQ13 =44, DQ14 =44, DQ15 =44
4574 13:31:18.564113
4575 13:31:18.564208
4576 13:31:18.570200 [DQSOSCAuto] RK0, (LSB)MR18= 0x436a, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 397 ps
4577 13:31:18.573623 CH1 RK0: MR19=808, MR18=436A
4578 13:31:18.580763 CH1_RK0: MR19=0x808, MR18=0x436A, DQSOSC=389, MR23=63, INC=173, DEC=115
4579 13:31:18.580850
4580 13:31:18.583730 ----->DramcWriteLeveling(PI) begin...
4581 13:31:18.583817 ==
4582 13:31:18.587190 Dram Type= 6, Freq= 0, CH_1, rank 1
4583 13:31:18.590575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4584 13:31:18.590662 ==
4585 13:31:18.593543 Write leveling (Byte 0): 31 => 31
4586 13:31:18.596897 Write leveling (Byte 1): 29 => 29
4587 13:31:18.600319 DramcWriteLeveling(PI) end<-----
4588 13:31:18.600404
4589 13:31:18.600471 ==
4590 13:31:18.603738 Dram Type= 6, Freq= 0, CH_1, rank 1
4591 13:31:18.607087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4592 13:31:18.607173 ==
4593 13:31:18.610481 [Gating] SW mode calibration
4594 13:31:18.616820 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4595 13:31:18.623703 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4596 13:31:18.626996 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4597 13:31:18.630325 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4598 13:31:18.636665 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4599 13:31:18.640100 0 9 12 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 0)
4600 13:31:18.643584 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 13:31:18.650121 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 13:31:18.653584 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 13:31:18.657264 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 13:31:18.663148 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 13:31:18.666637 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 13:31:18.670235 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 13:31:18.676446 0 10 12 | B1->B0 | 3939 2d2d | 0 1 | (0 0) (0 0)
4608 13:31:18.679687 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 13:31:18.683318 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 13:31:18.689717 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 13:31:18.693483 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 13:31:18.696437 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 13:31:18.703315 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 13:31:18.706653 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 13:31:18.710089 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 13:31:18.716430 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 13:31:18.719782 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 13:31:18.722917 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 13:31:18.729580 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 13:31:18.733095 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 13:31:18.736562 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 13:31:18.743284 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 13:31:18.746197 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 13:31:18.749569 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 13:31:18.756421 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 13:31:18.760100 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 13:31:18.763158 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 13:31:18.769565 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 13:31:18.772763 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 13:31:18.775991 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4631 13:31:18.782506 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4632 13:31:18.785834 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4633 13:31:18.789419 Total UI for P1: 0, mck2ui 16
4634 13:31:18.792496 best dqsien dly found for B0: ( 0, 13, 12)
4635 13:31:18.795788 Total UI for P1: 0, mck2ui 16
4636 13:31:18.799322 best dqsien dly found for B1: ( 0, 13, 10)
4637 13:31:18.802821 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4638 13:31:18.806194 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4639 13:31:18.806268
4640 13:31:18.809239 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4641 13:31:18.812686 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4642 13:31:18.816087 [Gating] SW calibration Done
4643 13:31:18.816212 ==
4644 13:31:18.819465 Dram Type= 6, Freq= 0, CH_1, rank 1
4645 13:31:18.822580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4646 13:31:18.822700 ==
4647 13:31:18.825826 RX Vref Scan: 0
4648 13:31:18.825968
4649 13:31:18.829133 RX Vref 0 -> 0, step: 1
4650 13:31:18.829224
4651 13:31:18.829303 RX Delay -230 -> 252, step: 16
4652 13:31:18.835930 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4653 13:31:18.839402 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4654 13:31:18.842779 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4655 13:31:18.846130 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4656 13:31:18.852428 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4657 13:31:18.856027 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4658 13:31:18.859028 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4659 13:31:18.862753 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4660 13:31:18.866040 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4661 13:31:18.872582 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4662 13:31:18.875896 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4663 13:31:18.879291 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4664 13:31:18.882584 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4665 13:31:18.889642 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4666 13:31:18.892840 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4667 13:31:18.896206 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4668 13:31:18.896282 ==
4669 13:31:18.899176 Dram Type= 6, Freq= 0, CH_1, rank 1
4670 13:31:18.902472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4671 13:31:18.902556 ==
4672 13:31:18.905880 DQS Delay:
4673 13:31:18.905964 DQS0 = 0, DQS1 = 0
4674 13:31:18.909435 DQM Delay:
4675 13:31:18.909518 DQM0 = 51, DQM1 = 45
4676 13:31:18.909585 DQ Delay:
4677 13:31:18.912682 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4678 13:31:18.916170 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4679 13:31:18.919098 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4680 13:31:18.922579 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4681 13:31:18.922657
4682 13:31:18.922722
4683 13:31:18.926020 ==
4684 13:31:18.929425 Dram Type= 6, Freq= 0, CH_1, rank 1
4685 13:31:18.932251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4686 13:31:18.932331 ==
4687 13:31:18.932396
4688 13:31:18.932456
4689 13:31:18.935676 TX Vref Scan disable
4690 13:31:18.935761 == TX Byte 0 ==
4691 13:31:18.942385 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4692 13:31:18.945443 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4693 13:31:18.945528 == TX Byte 1 ==
4694 13:31:18.952201 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4695 13:31:18.955523 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4696 13:31:18.955608 ==
4697 13:31:18.958469 Dram Type= 6, Freq= 0, CH_1, rank 1
4698 13:31:18.962305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4699 13:31:18.962391 ==
4700 13:31:18.962459
4701 13:31:18.962521
4702 13:31:18.965607 TX Vref Scan disable
4703 13:31:18.968479 == TX Byte 0 ==
4704 13:31:18.972143 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4705 13:31:18.975208 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4706 13:31:18.978867 == TX Byte 1 ==
4707 13:31:18.981771 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4708 13:31:18.985280 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4709 13:31:18.988429
4710 13:31:18.988532 [DATLAT]
4711 13:31:18.988625 Freq=600, CH1 RK1
4712 13:31:18.988717
4713 13:31:18.991782 DATLAT Default: 0x9
4714 13:31:18.991880 0, 0xFFFF, sum = 0
4715 13:31:18.995329 1, 0xFFFF, sum = 0
4716 13:31:18.995458 2, 0xFFFF, sum = 0
4717 13:31:18.998788 3, 0xFFFF, sum = 0
4718 13:31:18.998909 4, 0xFFFF, sum = 0
4719 13:31:19.002105 5, 0xFFFF, sum = 0
4720 13:31:19.002226 6, 0xFFFF, sum = 0
4721 13:31:19.005441 7, 0xFFFF, sum = 0
4722 13:31:19.005568 8, 0x0, sum = 1
4723 13:31:19.008414 9, 0x0, sum = 2
4724 13:31:19.008536 10, 0x0, sum = 3
4725 13:31:19.011865 11, 0x0, sum = 4
4726 13:31:19.011990 best_step = 9
4727 13:31:19.012104
4728 13:31:19.012208 ==
4729 13:31:19.015070 Dram Type= 6, Freq= 0, CH_1, rank 1
4730 13:31:19.021876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4731 13:31:19.021996 ==
4732 13:31:19.022112 RX Vref Scan: 0
4733 13:31:19.022223
4734 13:31:19.025220 RX Vref 0 -> 0, step: 1
4735 13:31:19.025337
4736 13:31:19.028249 RX Delay -179 -> 252, step: 8
4737 13:31:19.031808 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4738 13:31:19.035122 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4739 13:31:19.041936 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4740 13:31:19.044908 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4741 13:31:19.048356 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4742 13:31:19.051729 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4743 13:31:19.055265 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4744 13:31:19.061575 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4745 13:31:19.064968 iDelay=205, Bit 8, Center 24 (-123 ~ 172) 296
4746 13:31:19.068887 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4747 13:31:19.071492 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4748 13:31:19.078279 iDelay=205, Bit 11, Center 36 (-115 ~ 188) 304
4749 13:31:19.081810 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4750 13:31:19.085036 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4751 13:31:19.088616 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4752 13:31:19.091847 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4753 13:31:19.095093 ==
4754 13:31:19.095210 Dram Type= 6, Freq= 0, CH_1, rank 1
4755 13:31:19.101942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4756 13:31:19.102029 ==
4757 13:31:19.102111 DQS Delay:
4758 13:31:19.104982 DQS0 = 0, DQS1 = 0
4759 13:31:19.105066 DQM Delay:
4760 13:31:19.108432 DQM0 = 48, DQM1 = 41
4761 13:31:19.108543 DQ Delay:
4762 13:31:19.111825 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =44
4763 13:31:19.115256 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =44
4764 13:31:19.118306 DQ8 =24, DQ9 =32, DQ10 =40, DQ11 =36
4765 13:31:19.121968 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =52
4766 13:31:19.122053
4767 13:31:19.122120
4768 13:31:19.128327 [DQSOSCAuto] RK1, (LSB)MR18= 0x541c, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4769 13:31:19.131830 CH1 RK1: MR19=808, MR18=541C
4770 13:31:19.138220 CH1_RK1: MR19=0x808, MR18=0x541C, DQSOSC=393, MR23=63, INC=169, DEC=113
4771 13:31:19.141711 [RxdqsGatingPostProcess] freq 600
4772 13:31:19.144976 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4773 13:31:19.148379 Pre-setting of DQS Precalculation
4774 13:31:19.154899 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4775 13:31:19.161542 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4776 13:31:19.168454 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4777 13:31:19.168571
4778 13:31:19.168670
4779 13:31:19.171723 [Calibration Summary] 1200 Mbps
4780 13:31:19.171809 CH 0, Rank 0
4781 13:31:19.175153 SW Impedance : PASS
4782 13:31:19.178522 DUTY Scan : NO K
4783 13:31:19.178648 ZQ Calibration : PASS
4784 13:31:19.181907 Jitter Meter : NO K
4785 13:31:19.185248 CBT Training : PASS
4786 13:31:19.185376 Write leveling : PASS
4787 13:31:19.188636 RX DQS gating : PASS
4788 13:31:19.192234 RX DQ/DQS(RDDQC) : PASS
4789 13:31:19.192350 TX DQ/DQS : PASS
4790 13:31:19.195140 RX DATLAT : PASS
4791 13:31:19.195246 RX DQ/DQS(Engine): PASS
4792 13:31:19.198906 TX OE : NO K
4793 13:31:19.199022 All Pass.
4794 13:31:19.199120
4795 13:31:19.202266 CH 0, Rank 1
4796 13:31:19.202378 SW Impedance : PASS
4797 13:31:19.205478 DUTY Scan : NO K
4798 13:31:19.208703 ZQ Calibration : PASS
4799 13:31:19.208816 Jitter Meter : NO K
4800 13:31:19.211949 CBT Training : PASS
4801 13:31:19.215343 Write leveling : PASS
4802 13:31:19.215447 RX DQS gating : PASS
4803 13:31:19.218733 RX DQ/DQS(RDDQC) : PASS
4804 13:31:19.221832 TX DQ/DQS : PASS
4805 13:31:19.221942 RX DATLAT : PASS
4806 13:31:19.225078 RX DQ/DQS(Engine): PASS
4807 13:31:19.228721 TX OE : NO K
4808 13:31:19.228819 All Pass.
4809 13:31:19.228886
4810 13:31:19.228948 CH 1, Rank 0
4811 13:31:19.231706 SW Impedance : PASS
4812 13:31:19.235448 DUTY Scan : NO K
4813 13:31:19.235550 ZQ Calibration : PASS
4814 13:31:19.238375 Jitter Meter : NO K
4815 13:31:19.241736 CBT Training : PASS
4816 13:31:19.241810 Write leveling : PASS
4817 13:31:19.245192 RX DQS gating : PASS
4818 13:31:19.245263 RX DQ/DQS(RDDQC) : PASS
4819 13:31:19.248584 TX DQ/DQS : PASS
4820 13:31:19.252044 RX DATLAT : PASS
4821 13:31:19.252119 RX DQ/DQS(Engine): PASS
4822 13:31:19.255018 TX OE : NO K
4823 13:31:19.255117 All Pass.
4824 13:31:19.255229
4825 13:31:19.258239 CH 1, Rank 1
4826 13:31:19.258340 SW Impedance : PASS
4827 13:31:19.261859 DUTY Scan : NO K
4828 13:31:19.265066 ZQ Calibration : PASS
4829 13:31:19.265140 Jitter Meter : NO K
4830 13:31:19.268244 CBT Training : PASS
4831 13:31:19.271611 Write leveling : PASS
4832 13:31:19.271712 RX DQS gating : PASS
4833 13:31:19.275332 RX DQ/DQS(RDDQC) : PASS
4834 13:31:19.278155 TX DQ/DQS : PASS
4835 13:31:19.278231 RX DATLAT : PASS
4836 13:31:19.281577 RX DQ/DQS(Engine): PASS
4837 13:31:19.284819 TX OE : NO K
4838 13:31:19.284891 All Pass.
4839 13:31:19.284952
4840 13:31:19.285010 DramC Write-DBI off
4841 13:31:19.288197 PER_BANK_REFRESH: Hybrid Mode
4842 13:31:19.291488 TX_TRACKING: ON
4843 13:31:19.298542 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4844 13:31:19.301510 [FAST_K] Save calibration result to emmc
4845 13:31:19.308269 dramc_set_vcore_voltage set vcore to 662500
4846 13:31:19.308357 Read voltage for 933, 3
4847 13:31:19.308426 Vio18 = 0
4848 13:31:19.311590 Vcore = 662500
4849 13:31:19.311677 Vdram = 0
4850 13:31:19.311745 Vddq = 0
4851 13:31:19.314897 Vmddr = 0
4852 13:31:19.318195 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4853 13:31:19.325235 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4854 13:31:19.325361 MEM_TYPE=3, freq_sel=17
4855 13:31:19.328485 sv_algorithm_assistance_LP4_1600
4856 13:31:19.334913 ============ PULL DRAM RESETB DOWN ============
4857 13:31:19.338465 ========== PULL DRAM RESETB DOWN end =========
4858 13:31:19.341495 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4859 13:31:19.344798 ===================================
4860 13:31:19.348362 LPDDR4 DRAM CONFIGURATION
4861 13:31:19.351718 ===================================
4862 13:31:19.354803 EX_ROW_EN[0] = 0x0
4863 13:31:19.354929 EX_ROW_EN[1] = 0x0
4864 13:31:19.358280 LP4Y_EN = 0x0
4865 13:31:19.358407 WORK_FSP = 0x0
4866 13:31:19.361681 WL = 0x3
4867 13:31:19.361805 RL = 0x3
4868 13:31:19.365413 BL = 0x2
4869 13:31:19.365538 RPST = 0x0
4870 13:31:19.367949 RD_PRE = 0x0
4871 13:31:19.368055 WR_PRE = 0x1
4872 13:31:19.371403 WR_PST = 0x0
4873 13:31:19.371508 DBI_WR = 0x0
4874 13:31:19.375009 DBI_RD = 0x0
4875 13:31:19.375094 OTF = 0x1
4876 13:31:19.378367 ===================================
4877 13:31:19.381193 ===================================
4878 13:31:19.384913 ANA top config
4879 13:31:19.387846 ===================================
4880 13:31:19.391245 DLL_ASYNC_EN = 0
4881 13:31:19.391368 ALL_SLAVE_EN = 1
4882 13:31:19.394802 NEW_RANK_MODE = 1
4883 13:31:19.398300 DLL_IDLE_MODE = 1
4884 13:31:19.401424 LP45_APHY_COMB_EN = 1
4885 13:31:19.401552 TX_ODT_DIS = 1
4886 13:31:19.404627 NEW_8X_MODE = 1
4887 13:31:19.407992 ===================================
4888 13:31:19.411280 ===================================
4889 13:31:19.414696 data_rate = 1866
4890 13:31:19.417902 CKR = 1
4891 13:31:19.421475 DQ_P2S_RATIO = 8
4892 13:31:19.424838 ===================================
4893 13:31:19.427729 CA_P2S_RATIO = 8
4894 13:31:19.427851 DQ_CA_OPEN = 0
4895 13:31:19.430998 DQ_SEMI_OPEN = 0
4896 13:31:19.434817 CA_SEMI_OPEN = 0
4897 13:31:19.437700 CA_FULL_RATE = 0
4898 13:31:19.441490 DQ_CKDIV4_EN = 1
4899 13:31:19.444403 CA_CKDIV4_EN = 1
4900 13:31:19.444495 CA_PREDIV_EN = 0
4901 13:31:19.447900 PH8_DLY = 0
4902 13:31:19.451254 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4903 13:31:19.454884 DQ_AAMCK_DIV = 4
4904 13:31:19.457854 CA_AAMCK_DIV = 4
4905 13:31:19.461045 CA_ADMCK_DIV = 4
4906 13:31:19.461126 DQ_TRACK_CA_EN = 0
4907 13:31:19.464580 CA_PICK = 933
4908 13:31:19.467841 CA_MCKIO = 933
4909 13:31:19.471193 MCKIO_SEMI = 0
4910 13:31:19.474789 PLL_FREQ = 3732
4911 13:31:19.478019 DQ_UI_PI_RATIO = 32
4912 13:31:19.481263 CA_UI_PI_RATIO = 0
4913 13:31:19.484286 ===================================
4914 13:31:19.487441 ===================================
4915 13:31:19.487563 memory_type:LPDDR4
4916 13:31:19.491167 GP_NUM : 10
4917 13:31:19.494231 SRAM_EN : 1
4918 13:31:19.494358 MD32_EN : 0
4919 13:31:19.497467 ===================================
4920 13:31:19.500885 [ANA_INIT] >>>>>>>>>>>>>>
4921 13:31:19.504613 <<<<<< [CONFIGURE PHASE]: ANA_TX
4922 13:31:19.508041 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4923 13:31:19.510828 ===================================
4924 13:31:19.514219 data_rate = 1866,PCW = 0X8f00
4925 13:31:19.517459 ===================================
4926 13:31:19.521046 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4927 13:31:19.524187 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4928 13:31:19.530766 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4929 13:31:19.534088 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4930 13:31:19.537331 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4931 13:31:19.540974 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4932 13:31:19.543854 [ANA_INIT] flow start
4933 13:31:19.547248 [ANA_INIT] PLL >>>>>>>>
4934 13:31:19.547333 [ANA_INIT] PLL <<<<<<<<
4935 13:31:19.550789 [ANA_INIT] MIDPI >>>>>>>>
4936 13:31:19.553828 [ANA_INIT] MIDPI <<<<<<<<
4937 13:31:19.553912 [ANA_INIT] DLL >>>>>>>>
4938 13:31:19.557234 [ANA_INIT] flow end
4939 13:31:19.560869 ============ LP4 DIFF to SE enter ============
4940 13:31:19.567445 ============ LP4 DIFF to SE exit ============
4941 13:31:19.567531 [ANA_INIT] <<<<<<<<<<<<<
4942 13:31:19.571051 [Flow] Enable top DCM control >>>>>
4943 13:31:19.574029 [Flow] Enable top DCM control <<<<<
4944 13:31:19.577449 Enable DLL master slave shuffle
4945 13:31:19.584013 ==============================================================
4946 13:31:19.584100 Gating Mode config
4947 13:31:19.590911 ==============================================================
4948 13:31:19.594163 Config description:
4949 13:31:19.600366 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4950 13:31:19.607013 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4951 13:31:19.613751 SELPH_MODE 0: By rank 1: By Phase
4952 13:31:19.617110 ==============================================================
4953 13:31:19.620619 GAT_TRACK_EN = 1
4954 13:31:19.623610 RX_GATING_MODE = 2
4955 13:31:19.627001 RX_GATING_TRACK_MODE = 2
4956 13:31:19.630618 SELPH_MODE = 1
4957 13:31:19.634121 PICG_EARLY_EN = 1
4958 13:31:19.637147 VALID_LAT_VALUE = 1
4959 13:31:19.644178 ==============================================================
4960 13:31:19.647021 Enter into Gating configuration >>>>
4961 13:31:19.650351 Exit from Gating configuration <<<<
4962 13:31:19.653730 Enter into DVFS_PRE_config >>>>>
4963 13:31:19.664213 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4964 13:31:19.666941 Exit from DVFS_PRE_config <<<<<
4965 13:31:19.670410 Enter into PICG configuration >>>>
4966 13:31:19.673772 Exit from PICG configuration <<<<
4967 13:31:19.676831 [RX_INPUT] configuration >>>>>
4968 13:31:19.676921 [RX_INPUT] configuration <<<<<
4969 13:31:19.683642 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4970 13:31:19.690395 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4971 13:31:19.693708 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4972 13:31:19.700016 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4973 13:31:19.706825 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4974 13:31:19.713784 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4975 13:31:19.717059 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4976 13:31:19.720449 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4977 13:31:19.726896 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4978 13:31:19.730030 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4979 13:31:19.733469 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4980 13:31:19.740129 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4981 13:31:19.743408 ===================================
4982 13:31:19.743523 LPDDR4 DRAM CONFIGURATION
4983 13:31:19.746621 ===================================
4984 13:31:19.750136 EX_ROW_EN[0] = 0x0
4985 13:31:19.750216 EX_ROW_EN[1] = 0x0
4986 13:31:19.753428 LP4Y_EN = 0x0
4987 13:31:19.753503 WORK_FSP = 0x0
4988 13:31:19.756890 WL = 0x3
4989 13:31:19.756965 RL = 0x3
4990 13:31:19.759910 BL = 0x2
4991 13:31:19.763345 RPST = 0x0
4992 13:31:19.763419 RD_PRE = 0x0
4993 13:31:19.766633 WR_PRE = 0x1
4994 13:31:19.766710 WR_PST = 0x0
4995 13:31:19.770079 DBI_WR = 0x0
4996 13:31:19.770153 DBI_RD = 0x0
4997 13:31:19.773338 OTF = 0x1
4998 13:31:19.776422 ===================================
4999 13:31:19.779852 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5000 13:31:19.783301 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5001 13:31:19.786342 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5002 13:31:19.790187 ===================================
5003 13:31:19.793732 LPDDR4 DRAM CONFIGURATION
5004 13:31:19.796345 ===================================
5005 13:31:19.799821 EX_ROW_EN[0] = 0x10
5006 13:31:19.799906 EX_ROW_EN[1] = 0x0
5007 13:31:19.802927 LP4Y_EN = 0x0
5008 13:31:19.803012 WORK_FSP = 0x0
5009 13:31:19.806356 WL = 0x3
5010 13:31:19.806442 RL = 0x3
5011 13:31:19.809797 BL = 0x2
5012 13:31:19.809882 RPST = 0x0
5013 13:31:19.812882 RD_PRE = 0x0
5014 13:31:19.816165 WR_PRE = 0x1
5015 13:31:19.816250 WR_PST = 0x0
5016 13:31:19.819636 DBI_WR = 0x0
5017 13:31:19.819722 DBI_RD = 0x0
5018 13:31:19.823218 OTF = 0x1
5019 13:31:19.826287 ===================================
5020 13:31:19.829366 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5021 13:31:19.835392 nWR fixed to 30
5022 13:31:19.838448 [ModeRegInit_LP4] CH0 RK0
5023 13:31:19.838568 [ModeRegInit_LP4] CH0 RK1
5024 13:31:19.841577 [ModeRegInit_LP4] CH1 RK0
5025 13:31:19.845004 [ModeRegInit_LP4] CH1 RK1
5026 13:31:19.845114 match AC timing 9
5027 13:31:19.851323 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5028 13:31:19.855089 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5029 13:31:19.858095 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5030 13:31:19.865023 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5031 13:31:19.868524 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5032 13:31:19.868638 ==
5033 13:31:19.871347 Dram Type= 6, Freq= 0, CH_0, rank 0
5034 13:31:19.874875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5035 13:31:19.874961 ==
5036 13:31:19.881577 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5037 13:31:19.888173 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5038 13:31:19.891451 [CA 0] Center 38 (7~69) winsize 63
5039 13:31:19.894832 [CA 1] Center 38 (7~69) winsize 63
5040 13:31:19.898541 [CA 2] Center 35 (5~66) winsize 62
5041 13:31:19.901269 [CA 3] Center 35 (5~65) winsize 61
5042 13:31:19.904800 [CA 4] Center 35 (5~65) winsize 61
5043 13:31:19.908202 [CA 5] Center 33 (3~64) winsize 62
5044 13:31:19.908292
5045 13:31:19.911362 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5046 13:31:19.911447
5047 13:31:19.914909 [CATrainingPosCal] consider 1 rank data
5048 13:31:19.918270 u2DelayCellTimex100 = 270/100 ps
5049 13:31:19.921766 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5050 13:31:19.925066 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5051 13:31:19.928139 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5052 13:31:19.932198 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5053 13:31:19.935102 CA4 delay=35 (5~65),Diff = 2 PI (12 cell)
5054 13:31:19.938146 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5055 13:31:19.938252
5056 13:31:19.944969 CA PerBit enable=1, Macro0, CA PI delay=33
5057 13:31:19.945055
5058 13:31:19.945123 [CBTSetCACLKResult] CA Dly = 33
5059 13:31:19.948243 CS Dly: 7 (0~38)
5060 13:31:19.948329 ==
5061 13:31:19.951734 Dram Type= 6, Freq= 0, CH_0, rank 1
5062 13:31:19.954883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5063 13:31:19.954970 ==
5064 13:31:19.961720 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5065 13:31:19.968441 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5066 13:31:19.971475 [CA 0] Center 38 (8~69) winsize 62
5067 13:31:19.974855 [CA 1] Center 38 (8~69) winsize 62
5068 13:31:19.978542 [CA 2] Center 36 (6~66) winsize 61
5069 13:31:19.981820 [CA 3] Center 35 (5~66) winsize 62
5070 13:31:19.984697 [CA 4] Center 34 (4~65) winsize 62
5071 13:31:19.988346 [CA 5] Center 34 (4~64) winsize 61
5072 13:31:19.988450
5073 13:31:19.991585 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5074 13:31:19.991694
5075 13:31:19.994977 [CATrainingPosCal] consider 2 rank data
5076 13:31:19.998334 u2DelayCellTimex100 = 270/100 ps
5077 13:31:20.001950 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5078 13:31:20.004999 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5079 13:31:20.008325 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5080 13:31:20.011630 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5081 13:31:20.014756 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5082 13:31:20.018023 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5083 13:31:20.018108
5084 13:31:20.024993 CA PerBit enable=1, Macro0, CA PI delay=34
5085 13:31:20.025078
5086 13:31:20.028285 [CBTSetCACLKResult] CA Dly = 34
5087 13:31:20.028371 CS Dly: 7 (0~39)
5088 13:31:20.028438
5089 13:31:20.031315 ----->DramcWriteLeveling(PI) begin...
5090 13:31:20.031401 ==
5091 13:31:20.034756 Dram Type= 6, Freq= 0, CH_0, rank 0
5092 13:31:20.037849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5093 13:31:20.037935 ==
5094 13:31:20.041869 Write leveling (Byte 0): 31 => 31
5095 13:31:20.044693 Write leveling (Byte 1): 29 => 29
5096 13:31:20.048087 DramcWriteLeveling(PI) end<-----
5097 13:31:20.048175
5098 13:31:20.048242 ==
5099 13:31:20.051385 Dram Type= 6, Freq= 0, CH_0, rank 0
5100 13:31:20.058034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5101 13:31:20.058120 ==
5102 13:31:20.058188 [Gating] SW mode calibration
5103 13:31:20.067879 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5104 13:31:20.071654 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5105 13:31:20.074738 0 14 0 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
5106 13:31:20.081452 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 13:31:20.084743 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 13:31:20.087763 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 13:31:20.094520 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 13:31:20.098027 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 13:31:20.101649 0 14 24 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
5112 13:31:20.107955 0 14 28 | B1->B0 | 3131 2323 | 0 0 | (1 0) (0 0)
5113 13:31:20.111241 0 15 0 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5114 13:31:20.114500 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 13:31:20.121426 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 13:31:20.124314 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 13:31:20.127796 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 13:31:20.134201 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 13:31:20.137645 0 15 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
5120 13:31:20.140976 0 15 28 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
5121 13:31:20.147619 1 0 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5122 13:31:20.150722 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 13:31:20.154164 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 13:31:20.160632 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 13:31:20.164082 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 13:31:20.167530 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 13:31:20.174022 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 13:31:20.177394 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5129 13:31:20.180804 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5130 13:31:20.187478 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 13:31:20.190699 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 13:31:20.193994 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 13:31:20.200473 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 13:31:20.203925 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 13:31:20.207537 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 13:31:20.214055 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 13:31:20.217309 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 13:31:20.220345 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 13:31:20.223845 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 13:31:20.230529 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 13:31:20.233902 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 13:31:20.237022 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 13:31:20.243785 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5144 13:31:20.247081 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5145 13:31:20.250431 Total UI for P1: 0, mck2ui 16
5146 13:31:20.253896 best dqsien dly found for B0: ( 1, 2, 24)
5147 13:31:20.256832 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 13:31:20.260450 Total UI for P1: 0, mck2ui 16
5149 13:31:20.263448 best dqsien dly found for B1: ( 1, 2, 30)
5150 13:31:20.266967 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5151 13:31:20.270346 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5152 13:31:20.273420
5153 13:31:20.276894 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5154 13:31:20.280043 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5155 13:31:20.283983 [Gating] SW calibration Done
5156 13:31:20.284069 ==
5157 13:31:20.286829 Dram Type= 6, Freq= 0, CH_0, rank 0
5158 13:31:20.290098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5159 13:31:20.290184 ==
5160 13:31:20.290252 RX Vref Scan: 0
5161 13:31:20.290315
5162 13:31:20.293684 RX Vref 0 -> 0, step: 1
5163 13:31:20.293770
5164 13:31:20.297111 RX Delay -80 -> 252, step: 8
5165 13:31:20.300435 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5166 13:31:20.303477 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5167 13:31:20.310239 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5168 13:31:20.313537 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5169 13:31:20.316851 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5170 13:31:20.320154 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5171 13:31:20.323688 iDelay=208, Bit 6, Center 119 (32 ~ 207) 176
5172 13:31:20.326564 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5173 13:31:20.333475 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5174 13:31:20.336939 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5175 13:31:20.340334 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5176 13:31:20.343270 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5177 13:31:20.346532 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5178 13:31:20.350148 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5179 13:31:20.356942 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5180 13:31:20.360216 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5181 13:31:20.360320 ==
5182 13:31:20.363589 Dram Type= 6, Freq= 0, CH_0, rank 0
5183 13:31:20.366754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5184 13:31:20.366840 ==
5185 13:31:20.369822 DQS Delay:
5186 13:31:20.369908 DQS0 = 0, DQS1 = 0
5187 13:31:20.369975 DQM Delay:
5188 13:31:20.373036 DQM0 = 106, DQM1 = 90
5189 13:31:20.373131 DQ Delay:
5190 13:31:20.376744 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5191 13:31:20.379944 DQ4 =107, DQ5 =99, DQ6 =119, DQ7 =115
5192 13:31:20.383311 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5193 13:31:20.386439 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5194 13:31:20.386541
5195 13:31:20.386633
5196 13:31:20.386721 ==
5197 13:31:20.389805 Dram Type= 6, Freq= 0, CH_0, rank 0
5198 13:31:20.396675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5199 13:31:20.396824 ==
5200 13:31:20.396895
5201 13:31:20.396965
5202 13:31:20.397028 TX Vref Scan disable
5203 13:31:20.400047 == TX Byte 0 ==
5204 13:31:20.403990 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5205 13:31:20.406809 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5206 13:31:20.410230 == TX Byte 1 ==
5207 13:31:20.413734 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5208 13:31:20.420435 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5209 13:31:20.420511 ==
5210 13:31:20.423613 Dram Type= 6, Freq= 0, CH_0, rank 0
5211 13:31:20.426781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5212 13:31:20.426859 ==
5213 13:31:20.426924
5214 13:31:20.426984
5215 13:31:20.429777 TX Vref Scan disable
5216 13:31:20.429890 == TX Byte 0 ==
5217 13:31:20.436676 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5218 13:31:20.440148 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5219 13:31:20.440227 == TX Byte 1 ==
5220 13:31:20.446390 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5221 13:31:20.449866 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5222 13:31:20.449942
5223 13:31:20.450006 [DATLAT]
5224 13:31:20.453342 Freq=933, CH0 RK0
5225 13:31:20.453425
5226 13:31:20.453490 DATLAT Default: 0xd
5227 13:31:20.456677 0, 0xFFFF, sum = 0
5228 13:31:20.456808 1, 0xFFFF, sum = 0
5229 13:31:20.460089 2, 0xFFFF, sum = 0
5230 13:31:20.463246 3, 0xFFFF, sum = 0
5231 13:31:20.463352 4, 0xFFFF, sum = 0
5232 13:31:20.466494 5, 0xFFFF, sum = 0
5233 13:31:20.466579 6, 0xFFFF, sum = 0
5234 13:31:20.469787 7, 0xFFFF, sum = 0
5235 13:31:20.469872 8, 0xFFFF, sum = 0
5236 13:31:20.473116 9, 0xFFFF, sum = 0
5237 13:31:20.473245 10, 0x0, sum = 1
5238 13:31:20.476217 11, 0x0, sum = 2
5239 13:31:20.476301 12, 0x0, sum = 3
5240 13:31:20.476368 13, 0x0, sum = 4
5241 13:31:20.479735 best_step = 11
5242 13:31:20.479850
5243 13:31:20.479972 ==
5244 13:31:20.483081 Dram Type= 6, Freq= 0, CH_0, rank 0
5245 13:31:20.486379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5246 13:31:20.486455 ==
5247 13:31:20.489761 RX Vref Scan: 1
5248 13:31:20.489848
5249 13:31:20.489947 RX Vref 0 -> 0, step: 1
5250 13:31:20.492961
5251 13:31:20.493035 RX Delay -53 -> 252, step: 4
5252 13:31:20.493097
5253 13:31:20.496216 Set Vref, RX VrefLevel [Byte0]: 59
5254 13:31:20.499634 [Byte1]: 50
5255 13:31:20.504125
5256 13:31:20.504236 Final RX Vref Byte 0 = 59 to rank0
5257 13:31:20.507533 Final RX Vref Byte 1 = 50 to rank0
5258 13:31:20.510907 Final RX Vref Byte 0 = 59 to rank1
5259 13:31:20.513779 Final RX Vref Byte 1 = 50 to rank1==
5260 13:31:20.517144 Dram Type= 6, Freq= 0, CH_0, rank 0
5261 13:31:20.523732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5262 13:31:20.523835 ==
5263 13:31:20.523928 DQS Delay:
5264 13:31:20.524017 DQS0 = 0, DQS1 = 0
5265 13:31:20.527275 DQM Delay:
5266 13:31:20.527357 DQM0 = 107, DQM1 = 92
5267 13:31:20.530521 DQ Delay:
5268 13:31:20.533933 DQ0 =106, DQ1 =108, DQ2 =102, DQ3 =106
5269 13:31:20.537862 DQ4 =108, DQ5 =98, DQ6 =118, DQ7 =114
5270 13:31:20.540609 DQ8 =84, DQ9 =78, DQ10 =92, DQ11 =90
5271 13:31:20.544039 DQ12 =98, DQ13 =96, DQ14 =102, DQ15 =100
5272 13:31:20.544122
5273 13:31:20.544187
5274 13:31:20.550521 [DQSOSCAuto] RK0, (LSB)MR18= 0x2521, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
5275 13:31:20.553890 CH0 RK0: MR19=505, MR18=2521
5276 13:31:20.560408 CH0_RK0: MR19=0x505, MR18=0x2521, DQSOSC=410, MR23=63, INC=64, DEC=42
5277 13:31:20.560492
5278 13:31:20.563890 ----->DramcWriteLeveling(PI) begin...
5279 13:31:20.563975 ==
5280 13:31:20.567076 Dram Type= 6, Freq= 0, CH_0, rank 1
5281 13:31:20.570583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5282 13:31:20.570667 ==
5283 13:31:20.573507 Write leveling (Byte 0): 35 => 35
5284 13:31:20.576838 Write leveling (Byte 1): 28 => 28
5285 13:31:20.580220 DramcWriteLeveling(PI) end<-----
5286 13:31:20.580331
5287 13:31:20.580465 ==
5288 13:31:20.583791 Dram Type= 6, Freq= 0, CH_0, rank 1
5289 13:31:20.590578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5290 13:31:20.590686 ==
5291 13:31:20.590781 [Gating] SW mode calibration
5292 13:31:20.600418 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5293 13:31:20.603593 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5294 13:31:20.607110 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 13:31:20.613682 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 13:31:20.617058 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 13:31:20.620372 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 13:31:20.626693 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 13:31:20.630528 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 13:31:20.633583 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
5301 13:31:20.640503 0 14 28 | B1->B0 | 2d2d 2525 | 0 0 | (1 0) (0 0)
5302 13:31:20.643535 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 13:31:20.646938 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 13:31:20.653732 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 13:31:20.656672 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 13:31:20.660061 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 13:31:20.667027 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 13:31:20.670015 0 15 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5309 13:31:20.673340 0 15 28 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
5310 13:31:20.680008 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 13:31:20.683662 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 13:31:20.686632 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 13:31:20.693158 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 13:31:20.696415 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 13:31:20.699999 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 13:31:20.706462 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5317 13:31:20.709830 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5318 13:31:20.713227 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 13:31:20.716686 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 13:31:20.723416 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 13:31:20.726446 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 13:31:20.730127 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 13:31:20.736775 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 13:31:20.740002 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 13:31:20.743422 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 13:31:20.749753 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 13:31:20.753088 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 13:31:20.756483 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 13:31:20.762839 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 13:31:20.766286 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 13:31:20.769656 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 13:31:20.776525 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 13:31:20.779632 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5334 13:31:20.783156 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 13:31:20.786503 Total UI for P1: 0, mck2ui 16
5336 13:31:20.789592 best dqsien dly found for B0: ( 1, 2, 28)
5337 13:31:20.792926 Total UI for P1: 0, mck2ui 16
5338 13:31:20.796297 best dqsien dly found for B1: ( 1, 2, 28)
5339 13:31:20.799701 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5340 13:31:20.803372 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5341 13:31:20.803443
5342 13:31:20.810397 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5343 13:31:20.813052 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5344 13:31:20.813126 [Gating] SW calibration Done
5345 13:31:20.816581 ==
5346 13:31:20.819337 Dram Type= 6, Freq= 0, CH_0, rank 1
5347 13:31:20.822793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5348 13:31:20.822924 ==
5349 13:31:20.823041 RX Vref Scan: 0
5350 13:31:20.823151
5351 13:31:20.826067 RX Vref 0 -> 0, step: 1
5352 13:31:20.826192
5353 13:31:20.829186 RX Delay -80 -> 252, step: 8
5354 13:31:20.832916 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5355 13:31:20.835882 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5356 13:31:20.839212 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5357 13:31:20.846188 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5358 13:31:20.849367 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5359 13:31:20.852468 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5360 13:31:20.855984 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5361 13:31:20.859351 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5362 13:31:20.862733 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5363 13:31:20.869434 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5364 13:31:20.872458 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5365 13:31:20.875931 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5366 13:31:20.879251 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5367 13:31:20.882740 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5368 13:31:20.885781 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5369 13:31:20.892369 iDelay=208, Bit 15, Center 91 (0 ~ 183) 184
5370 13:31:20.892455 ==
5371 13:31:20.895958 Dram Type= 6, Freq= 0, CH_0, rank 1
5372 13:31:20.899397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5373 13:31:20.899483 ==
5374 13:31:20.899551 DQS Delay:
5375 13:31:20.902517 DQS0 = 0, DQS1 = 0
5376 13:31:20.902602 DQM Delay:
5377 13:31:20.905919 DQM0 = 104, DQM1 = 89
5378 13:31:20.906004 DQ Delay:
5379 13:31:20.909155 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5380 13:31:20.912713 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =111
5381 13:31:20.915707 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5382 13:31:20.919149 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =91
5383 13:31:20.919235
5384 13:31:20.919302
5385 13:31:20.919364 ==
5386 13:31:20.922591 Dram Type= 6, Freq= 0, CH_0, rank 1
5387 13:31:20.929152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5388 13:31:20.929237 ==
5389 13:31:20.929304
5390 13:31:20.929367
5391 13:31:20.929426 TX Vref Scan disable
5392 13:31:20.932592 == TX Byte 0 ==
5393 13:31:20.935711 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5394 13:31:20.939047 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5395 13:31:20.942175 == TX Byte 1 ==
5396 13:31:20.945836 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5397 13:31:20.952619 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5398 13:31:20.952747 ==
5399 13:31:20.955893 Dram Type= 6, Freq= 0, CH_0, rank 1
5400 13:31:20.958870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5401 13:31:20.958998 ==
5402 13:31:20.959118
5403 13:31:20.959234
5404 13:31:20.962381 TX Vref Scan disable
5405 13:31:20.962509 == TX Byte 0 ==
5406 13:31:20.968849 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5407 13:31:20.972108 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5408 13:31:20.972228 == TX Byte 1 ==
5409 13:31:20.979011 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5410 13:31:20.982645 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5411 13:31:20.982754
5412 13:31:20.982848 [DATLAT]
5413 13:31:20.985815 Freq=933, CH0 RK1
5414 13:31:20.985933
5415 13:31:20.986035 DATLAT Default: 0xb
5416 13:31:20.989096 0, 0xFFFF, sum = 0
5417 13:31:20.989181 1, 0xFFFF, sum = 0
5418 13:31:20.992456 2, 0xFFFF, sum = 0
5419 13:31:20.992540 3, 0xFFFF, sum = 0
5420 13:31:20.995389 4, 0xFFFF, sum = 0
5421 13:31:20.995474 5, 0xFFFF, sum = 0
5422 13:31:20.998885 6, 0xFFFF, sum = 0
5423 13:31:21.002085 7, 0xFFFF, sum = 0
5424 13:31:21.002170 8, 0xFFFF, sum = 0
5425 13:31:21.005551 9, 0xFFFF, sum = 0
5426 13:31:21.005638 10, 0x0, sum = 1
5427 13:31:21.009063 11, 0x0, sum = 2
5428 13:31:21.009140 12, 0x0, sum = 3
5429 13:31:21.009229 13, 0x0, sum = 4
5430 13:31:21.012452 best_step = 11
5431 13:31:21.012583
5432 13:31:21.012687 ==
5433 13:31:21.015846 Dram Type= 6, Freq= 0, CH_0, rank 1
5434 13:31:21.018840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5435 13:31:21.018983 ==
5436 13:31:21.022278 RX Vref Scan: 0
5437 13:31:21.022382
5438 13:31:21.022475 RX Vref 0 -> 0, step: 1
5439 13:31:21.025189
5440 13:31:21.025295 RX Delay -53 -> 252, step: 4
5441 13:31:21.033048 iDelay=203, Bit 0, Center 104 (19 ~ 190) 172
5442 13:31:21.036171 iDelay=203, Bit 1, Center 106 (19 ~ 194) 176
5443 13:31:21.039747 iDelay=203, Bit 2, Center 102 (15 ~ 190) 176
5444 13:31:21.042721 iDelay=203, Bit 3, Center 98 (15 ~ 182) 168
5445 13:31:21.046278 iDelay=203, Bit 4, Center 104 (19 ~ 190) 172
5446 13:31:21.052694 iDelay=203, Bit 5, Center 96 (11 ~ 182) 172
5447 13:31:21.056383 iDelay=203, Bit 6, Center 114 (27 ~ 202) 176
5448 13:31:21.059477 iDelay=203, Bit 7, Center 112 (27 ~ 198) 172
5449 13:31:21.062861 iDelay=203, Bit 8, Center 84 (-1 ~ 170) 172
5450 13:31:21.066172 iDelay=203, Bit 9, Center 80 (-1 ~ 162) 164
5451 13:31:21.069576 iDelay=203, Bit 10, Center 94 (11 ~ 178) 168
5452 13:31:21.076106 iDelay=203, Bit 11, Center 92 (11 ~ 174) 164
5453 13:31:21.079660 iDelay=203, Bit 12, Center 98 (15 ~ 182) 168
5454 13:31:21.082912 iDelay=203, Bit 13, Center 94 (11 ~ 178) 168
5455 13:31:21.086080 iDelay=203, Bit 14, Center 102 (15 ~ 190) 176
5456 13:31:21.089525 iDelay=203, Bit 15, Center 100 (19 ~ 182) 164
5457 13:31:21.092760 ==
5458 13:31:21.096277 Dram Type= 6, Freq= 0, CH_0, rank 1
5459 13:31:21.099497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5460 13:31:21.099601 ==
5461 13:31:21.099703 DQS Delay:
5462 13:31:21.102866 DQS0 = 0, DQS1 = 0
5463 13:31:21.102970 DQM Delay:
5464 13:31:21.106089 DQM0 = 104, DQM1 = 93
5465 13:31:21.106193 DQ Delay:
5466 13:31:21.109548 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =98
5467 13:31:21.112958 DQ4 =104, DQ5 =96, DQ6 =114, DQ7 =112
5468 13:31:21.115895 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =92
5469 13:31:21.119837 DQ12 =98, DQ13 =94, DQ14 =102, DQ15 =100
5470 13:31:21.119943
5471 13:31:21.120013
5472 13:31:21.126223 [DQSOSCAuto] RK1, (LSB)MR18= 0x2506, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 410 ps
5473 13:31:21.129696 CH0 RK1: MR19=505, MR18=2506
5474 13:31:21.136389 CH0_RK1: MR19=0x505, MR18=0x2506, DQSOSC=410, MR23=63, INC=64, DEC=42
5475 13:31:21.139672 [RxdqsGatingPostProcess] freq 933
5476 13:31:21.146309 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5477 13:31:21.149529 best DQS0 dly(2T, 0.5T) = (0, 10)
5478 13:31:21.152857 best DQS1 dly(2T, 0.5T) = (0, 10)
5479 13:31:21.155914 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5480 13:31:21.159374 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5481 13:31:21.159455 best DQS0 dly(2T, 0.5T) = (0, 10)
5482 13:31:21.162760 best DQS1 dly(2T, 0.5T) = (0, 10)
5483 13:31:21.166198 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5484 13:31:21.169505 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5485 13:31:21.172538 Pre-setting of DQS Precalculation
5486 13:31:21.179387 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5487 13:31:21.179473 ==
5488 13:31:21.182740 Dram Type= 6, Freq= 0, CH_1, rank 0
5489 13:31:21.185741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5490 13:31:21.185818 ==
5491 13:31:21.192441 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5492 13:31:21.198979 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5493 13:31:21.202571 [CA 0] Center 37 (7~68) winsize 62
5494 13:31:21.205843 [CA 1] Center 38 (7~69) winsize 63
5495 13:31:21.208656 [CA 2] Center 35 (5~66) winsize 62
5496 13:31:21.212319 [CA 3] Center 34 (4~65) winsize 62
5497 13:31:21.215665 [CA 4] Center 35 (5~65) winsize 61
5498 13:31:21.218989 [CA 5] Center 34 (4~65) winsize 62
5499 13:31:21.219096
5500 13:31:21.221835 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5501 13:31:21.221937
5502 13:31:21.225146 [CATrainingPosCal] consider 1 rank data
5503 13:31:21.228537 u2DelayCellTimex100 = 270/100 ps
5504 13:31:21.232012 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5505 13:31:21.235482 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5506 13:31:21.238510 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5507 13:31:21.241830 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5508 13:31:21.245226 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5509 13:31:21.248875 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5510 13:31:21.248960
5511 13:31:21.251740 CA PerBit enable=1, Macro0, CA PI delay=34
5512 13:31:21.255186
5513 13:31:21.255273 [CBTSetCACLKResult] CA Dly = 34
5514 13:31:21.258520 CS Dly: 6 (0~37)
5515 13:31:21.258609 ==
5516 13:31:21.262055 Dram Type= 6, Freq= 0, CH_1, rank 1
5517 13:31:21.265115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5518 13:31:21.265191 ==
5519 13:31:21.271689 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5520 13:31:21.278367 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5521 13:31:21.281820 [CA 0] Center 38 (7~69) winsize 63
5522 13:31:21.285258 [CA 1] Center 38 (7~69) winsize 63
5523 13:31:21.288211 [CA 2] Center 36 (6~66) winsize 61
5524 13:31:21.291603 [CA 3] Center 35 (5~66) winsize 62
5525 13:31:21.294870 [CA 4] Center 35 (5~65) winsize 61
5526 13:31:21.298640 [CA 5] Center 35 (5~65) winsize 61
5527 13:31:21.298724
5528 13:31:21.301721 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5529 13:31:21.301806
5530 13:31:21.305098 [CATrainingPosCal] consider 2 rank data
5531 13:31:21.308462 u2DelayCellTimex100 = 270/100 ps
5532 13:31:21.311791 CA0 delay=37 (7~68),Diff = 2 PI (12 cell)
5533 13:31:21.315263 CA1 delay=38 (7~69),Diff = 3 PI (18 cell)
5534 13:31:21.318076 CA2 delay=36 (6~66),Diff = 1 PI (6 cell)
5535 13:31:21.321704 CA3 delay=35 (5~65),Diff = 0 PI (0 cell)
5536 13:31:21.324748 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
5537 13:31:21.328293 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5538 13:31:21.331648
5539 13:31:21.334986 CA PerBit enable=1, Macro0, CA PI delay=35
5540 13:31:21.335072
5541 13:31:21.337915 [CBTSetCACLKResult] CA Dly = 35
5542 13:31:21.338000 CS Dly: 7 (0~39)
5543 13:31:21.338068
5544 13:31:21.341362 ----->DramcWriteLeveling(PI) begin...
5545 13:31:21.341447 ==
5546 13:31:21.344657 Dram Type= 6, Freq= 0, CH_1, rank 0
5547 13:31:21.348035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5548 13:31:21.351055 ==
5549 13:31:21.351139 Write leveling (Byte 0): 26 => 26
5550 13:31:21.354853 Write leveling (Byte 1): 30 => 30
5551 13:31:21.357681 DramcWriteLeveling(PI) end<-----
5552 13:31:21.357765
5553 13:31:21.357832 ==
5554 13:31:21.361092 Dram Type= 6, Freq= 0, CH_1, rank 0
5555 13:31:21.367831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5556 13:31:21.367959 ==
5557 13:31:21.368077 [Gating] SW mode calibration
5558 13:31:21.377848 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5559 13:31:21.381014 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5560 13:31:21.387438 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 13:31:21.391015 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 13:31:21.394271 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 13:31:21.400765 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 13:31:21.403797 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 13:31:21.407233 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5566 13:31:21.413867 0 14 24 | B1->B0 | 3434 3030 | 0 1 | (0 0) (1 0)
5567 13:31:21.417109 0 14 28 | B1->B0 | 2727 2424 | 0 0 | (1 1) (0 0)
5568 13:31:21.420715 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 13:31:21.427558 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 13:31:21.430459 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 13:31:21.433692 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 13:31:21.440557 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 13:31:21.443963 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 13:31:21.446898 0 15 24 | B1->B0 | 2626 2b2b | 0 0 | (0 0) (1 1)
5575 13:31:21.453993 0 15 28 | B1->B0 | 3f3f 4343 | 0 0 | (0 0) (0 0)
5576 13:31:21.457338 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 13:31:21.460487 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 13:31:21.466898 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 13:31:21.470363 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 13:31:21.473744 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 13:31:21.479818 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 13:31:21.483523 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5583 13:31:21.486618 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 13:31:21.489894 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 13:31:21.496499 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 13:31:21.500065 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 13:31:21.503419 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 13:31:21.509810 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 13:31:21.513368 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 13:31:21.516676 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 13:31:21.523387 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 13:31:21.526581 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 13:31:21.529960 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 13:31:21.536757 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 13:31:21.540228 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 13:31:21.543526 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 13:31:21.549910 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 13:31:21.553369 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5599 13:31:21.556967 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5600 13:31:21.560323 Total UI for P1: 0, mck2ui 16
5601 13:31:21.563504 best dqsien dly found for B0: ( 1, 2, 24)
5602 13:31:21.566857 Total UI for P1: 0, mck2ui 16
5603 13:31:21.569870 best dqsien dly found for B1: ( 1, 2, 26)
5604 13:31:21.573234 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5605 13:31:21.576813 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5606 13:31:21.576936
5607 13:31:21.579951 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5608 13:31:21.586615 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5609 13:31:21.586749 [Gating] SW calibration Done
5610 13:31:21.586844 ==
5611 13:31:21.589630 Dram Type= 6, Freq= 0, CH_1, rank 0
5612 13:31:21.597078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5613 13:31:21.597164 ==
5614 13:31:21.597231 RX Vref Scan: 0
5615 13:31:21.597302
5616 13:31:21.599924 RX Vref 0 -> 0, step: 1
5617 13:31:21.600041
5618 13:31:21.603384 RX Delay -80 -> 252, step: 8
5619 13:31:21.606658 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5620 13:31:21.610001 iDelay=208, Bit 1, Center 99 (16 ~ 183) 168
5621 13:31:21.613410 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5622 13:31:21.619898 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5623 13:31:21.622983 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5624 13:31:21.626659 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5625 13:31:21.629665 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5626 13:31:21.633363 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5627 13:31:21.636429 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5628 13:31:21.643285 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5629 13:31:21.646393 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5630 13:31:21.649897 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5631 13:31:21.652745 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5632 13:31:21.656359 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5633 13:31:21.662717 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5634 13:31:21.666504 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5635 13:31:21.666591 ==
5636 13:31:21.669551 Dram Type= 6, Freq= 0, CH_1, rank 0
5637 13:31:21.672922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5638 13:31:21.673006 ==
5639 13:31:21.673071 DQS Delay:
5640 13:31:21.676256 DQS0 = 0, DQS1 = 0
5641 13:31:21.676339 DQM Delay:
5642 13:31:21.679590 DQM0 = 103, DQM1 = 95
5643 13:31:21.679673 DQ Delay:
5644 13:31:21.682943 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =103
5645 13:31:21.686371 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =103
5646 13:31:21.689719 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5647 13:31:21.693116 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99
5648 13:31:21.693200
5649 13:31:21.693265
5650 13:31:21.693338 ==
5651 13:31:21.696376 Dram Type= 6, Freq= 0, CH_1, rank 0
5652 13:31:21.703024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5653 13:31:21.703149 ==
5654 13:31:21.703249
5655 13:31:21.703341
5656 13:31:21.703431 TX Vref Scan disable
5657 13:31:21.706618 == TX Byte 0 ==
5658 13:31:21.710127 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5659 13:31:21.716764 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5660 13:31:21.716873 == TX Byte 1 ==
5661 13:31:21.719716 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5662 13:31:21.726647 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5663 13:31:21.726801 ==
5664 13:31:21.730007 Dram Type= 6, Freq= 0, CH_1, rank 0
5665 13:31:21.733439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5666 13:31:21.733534 ==
5667 13:31:21.733605
5668 13:31:21.733684
5669 13:31:21.736570 TX Vref Scan disable
5670 13:31:21.736669 == TX Byte 0 ==
5671 13:31:21.743397 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5672 13:31:21.746666 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5673 13:31:21.746765 == TX Byte 1 ==
5674 13:31:21.753508 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5675 13:31:21.756657 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5676 13:31:21.756782
5677 13:31:21.756865 [DATLAT]
5678 13:31:21.759677 Freq=933, CH1 RK0
5679 13:31:21.759762
5680 13:31:21.759826 DATLAT Default: 0xd
5681 13:31:21.763020 0, 0xFFFF, sum = 0
5682 13:31:21.763095 1, 0xFFFF, sum = 0
5683 13:31:21.766428 2, 0xFFFF, sum = 0
5684 13:31:21.766502 3, 0xFFFF, sum = 0
5685 13:31:21.769968 4, 0xFFFF, sum = 0
5686 13:31:21.770055 5, 0xFFFF, sum = 0
5687 13:31:21.773166 6, 0xFFFF, sum = 0
5688 13:31:21.773252 7, 0xFFFF, sum = 0
5689 13:31:21.776513 8, 0xFFFF, sum = 0
5690 13:31:21.779939 9, 0xFFFF, sum = 0
5691 13:31:21.780073 10, 0x0, sum = 1
5692 13:31:21.780196 11, 0x0, sum = 2
5693 13:31:21.783319 12, 0x0, sum = 3
5694 13:31:21.783449 13, 0x0, sum = 4
5695 13:31:21.786233 best_step = 11
5696 13:31:21.786365
5697 13:31:21.786491 ==
5698 13:31:21.789728 Dram Type= 6, Freq= 0, CH_1, rank 0
5699 13:31:21.792987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5700 13:31:21.793124 ==
5701 13:31:21.796126 RX Vref Scan: 1
5702 13:31:21.796262
5703 13:31:21.796385 RX Vref 0 -> 0, step: 1
5704 13:31:21.796514
5705 13:31:21.800142 RX Delay -53 -> 252, step: 4
5706 13:31:21.800278
5707 13:31:21.803400 Set Vref, RX VrefLevel [Byte0]: 52
5708 13:31:21.806436 [Byte1]: 58
5709 13:31:21.811030
5710 13:31:21.811155 Final RX Vref Byte 0 = 52 to rank0
5711 13:31:21.813984 Final RX Vref Byte 1 = 58 to rank0
5712 13:31:21.816987 Final RX Vref Byte 0 = 52 to rank1
5713 13:31:21.820466 Final RX Vref Byte 1 = 58 to rank1==
5714 13:31:21.823753 Dram Type= 6, Freq= 0, CH_1, rank 0
5715 13:31:21.830274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5716 13:31:21.830406 ==
5717 13:31:21.830535 DQS Delay:
5718 13:31:21.833675 DQS0 = 0, DQS1 = 0
5719 13:31:21.833826 DQM Delay:
5720 13:31:21.833952 DQM0 = 104, DQM1 = 97
5721 13:31:21.836978 DQ Delay:
5722 13:31:21.840279 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5723 13:31:21.843372 DQ4 =102, DQ5 =112, DQ6 =114, DQ7 =102
5724 13:31:21.846611 DQ8 =88, DQ9 =84, DQ10 =100, DQ11 =94
5725 13:31:21.849800 DQ12 =106, DQ13 =102, DQ14 =102, DQ15 =102
5726 13:31:21.849877
5727 13:31:21.849959
5728 13:31:21.859935 [DQSOSCAuto] RK0, (LSB)MR18= 0x1932, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5729 13:31:21.860015 CH1 RK0: MR19=505, MR18=1932
5730 13:31:21.866566 CH1_RK0: MR19=0x505, MR18=0x1932, DQSOSC=406, MR23=63, INC=65, DEC=43
5731 13:31:21.866654
5732 13:31:21.869917 ----->DramcWriteLeveling(PI) begin...
5733 13:31:21.870004 ==
5734 13:31:21.873249 Dram Type= 6, Freq= 0, CH_1, rank 1
5735 13:31:21.876527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5736 13:31:21.879944 ==
5737 13:31:21.880030 Write leveling (Byte 0): 29 => 29
5738 13:31:21.883155 Write leveling (Byte 1): 28 => 28
5739 13:31:21.886936 DramcWriteLeveling(PI) end<-----
5740 13:31:21.887021
5741 13:31:21.887104 ==
5742 13:31:21.889927 Dram Type= 6, Freq= 0, CH_1, rank 1
5743 13:31:21.896655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5744 13:31:21.896770 ==
5745 13:31:21.896874 [Gating] SW mode calibration
5746 13:31:21.906620 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5747 13:31:21.910081 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5748 13:31:21.913322 0 14 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5749 13:31:21.919925 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 13:31:21.923296 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 13:31:21.926562 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 13:31:21.932966 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5753 13:31:21.936427 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 13:31:21.939664 0 14 24 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 0)
5755 13:31:21.946420 0 14 28 | B1->B0 | 2323 2e2e | 0 0 | (1 0) (0 1)
5756 13:31:21.949611 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5757 13:31:21.952962 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 13:31:21.959852 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 13:31:21.962888 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 13:31:21.966336 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 13:31:21.972781 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 13:31:21.976123 0 15 24 | B1->B0 | 2f2f 2626 | 0 0 | (0 0) (0 0)
5763 13:31:21.979431 0 15 28 | B1->B0 | 4444 3e3e | 0 0 | (0 0) (0 0)
5764 13:31:21.986211 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5765 13:31:21.989445 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 13:31:21.993082 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 13:31:22.000007 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 13:31:22.003026 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 13:31:22.006496 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 13:31:22.012724 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 13:31:22.016045 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5772 13:31:22.019593 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 13:31:22.026217 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 13:31:22.029945 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 13:31:22.032743 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 13:31:22.039662 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 13:31:22.042820 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 13:31:22.046291 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 13:31:22.049689 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 13:31:22.056509 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 13:31:22.059488 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 13:31:22.062794 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 13:31:22.069600 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 13:31:22.072933 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 13:31:22.076399 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 13:31:22.082946 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5787 13:31:22.086398 Total UI for P1: 0, mck2ui 16
5788 13:31:22.089273 best dqsien dly found for B1: ( 1, 2, 22)
5789 13:31:22.092558 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5790 13:31:22.096242 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 13:31:22.099368 Total UI for P1: 0, mck2ui 16
5792 13:31:22.102961 best dqsien dly found for B0: ( 1, 2, 26)
5793 13:31:22.106050 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5794 13:31:22.109273 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5795 13:31:22.109357
5796 13:31:22.116116 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5797 13:31:22.119844 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5798 13:31:22.119941 [Gating] SW calibration Done
5799 13:31:22.122905 ==
5800 13:31:22.126134 Dram Type= 6, Freq= 0, CH_1, rank 1
5801 13:31:22.129279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5802 13:31:22.129362 ==
5803 13:31:22.129457 RX Vref Scan: 0
5804 13:31:22.129534
5805 13:31:22.132829 RX Vref 0 -> 0, step: 1
5806 13:31:22.132929
5807 13:31:22.136172 RX Delay -80 -> 252, step: 8
5808 13:31:22.139525 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5809 13:31:22.142541 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5810 13:31:22.145931 iDelay=200, Bit 2, Center 91 (8 ~ 175) 168
5811 13:31:22.152687 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5812 13:31:22.155794 iDelay=200, Bit 4, Center 99 (8 ~ 191) 184
5813 13:31:22.159387 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5814 13:31:22.162799 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5815 13:31:22.165874 iDelay=200, Bit 7, Center 99 (8 ~ 191) 184
5816 13:31:22.169276 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5817 13:31:22.176108 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5818 13:31:22.179322 iDelay=200, Bit 10, Center 99 (8 ~ 191) 184
5819 13:31:22.182798 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5820 13:31:22.186102 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5821 13:31:22.189366 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5822 13:31:22.192704 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5823 13:31:22.199175 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5824 13:31:22.199259 ==
5825 13:31:22.202566 Dram Type= 6, Freq= 0, CH_1, rank 1
5826 13:31:22.206044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5827 13:31:22.206129 ==
5828 13:31:22.206196 DQS Delay:
5829 13:31:22.209069 DQS0 = 0, DQS1 = 0
5830 13:31:22.209154 DQM Delay:
5831 13:31:22.212456 DQM0 = 101, DQM1 = 95
5832 13:31:22.212580 DQ Delay:
5833 13:31:22.215983 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5834 13:31:22.219029 DQ4 =99, DQ5 =111, DQ6 =107, DQ7 =99
5835 13:31:22.222636 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =87
5836 13:31:22.225731 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5837 13:31:22.225862
5838 13:31:22.225982
5839 13:31:22.226100 ==
5840 13:31:22.229163 Dram Type= 6, Freq= 0, CH_1, rank 1
5841 13:31:22.235802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5842 13:31:22.235932 ==
5843 13:31:22.236051
5844 13:31:22.236164
5845 13:31:22.236276 TX Vref Scan disable
5846 13:31:22.239188 == TX Byte 0 ==
5847 13:31:22.242375 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5848 13:31:22.245853 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5849 13:31:22.249314 == TX Byte 1 ==
5850 13:31:22.252320 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5851 13:31:22.259115 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5852 13:31:22.259239 ==
5853 13:31:22.262247 Dram Type= 6, Freq= 0, CH_1, rank 1
5854 13:31:22.265623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5855 13:31:22.265736 ==
5856 13:31:22.265841
5857 13:31:22.265944
5858 13:31:22.269362 TX Vref Scan disable
5859 13:31:22.269480 == TX Byte 0 ==
5860 13:31:22.276014 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5861 13:31:22.278971 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5862 13:31:22.279090 == TX Byte 1 ==
5863 13:31:22.285914 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5864 13:31:22.288953 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5865 13:31:22.289067
5866 13:31:22.289178 [DATLAT]
5867 13:31:22.292247 Freq=933, CH1 RK1
5868 13:31:22.292357
5869 13:31:22.292452 DATLAT Default: 0xb
5870 13:31:22.295673 0, 0xFFFF, sum = 0
5871 13:31:22.295782 1, 0xFFFF, sum = 0
5872 13:31:22.299106 2, 0xFFFF, sum = 0
5873 13:31:22.299225 3, 0xFFFF, sum = 0
5874 13:31:22.302329 4, 0xFFFF, sum = 0
5875 13:31:22.302438 5, 0xFFFF, sum = 0
5876 13:31:22.305783 6, 0xFFFF, sum = 0
5877 13:31:22.305898 7, 0xFFFF, sum = 0
5878 13:31:22.309036 8, 0xFFFF, sum = 0
5879 13:31:22.312329 9, 0xFFFF, sum = 0
5880 13:31:22.312438 10, 0x0, sum = 1
5881 13:31:22.312536 11, 0x0, sum = 2
5882 13:31:22.315636 12, 0x0, sum = 3
5883 13:31:22.315754 13, 0x0, sum = 4
5884 13:31:22.318961 best_step = 11
5885 13:31:22.319077
5886 13:31:22.319176 ==
5887 13:31:22.322231 Dram Type= 6, Freq= 0, CH_1, rank 1
5888 13:31:22.325865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5889 13:31:22.325950 ==
5890 13:31:22.328860 RX Vref Scan: 0
5891 13:31:22.328936
5892 13:31:22.329000 RX Vref 0 -> 0, step: 1
5893 13:31:22.329061
5894 13:31:22.332239 RX Delay -53 -> 252, step: 4
5895 13:31:22.339461 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5896 13:31:22.342830 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5897 13:31:22.346137 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5898 13:31:22.349478 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5899 13:31:22.352884 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5900 13:31:22.359787 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5901 13:31:22.362791 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5902 13:31:22.365930 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5903 13:31:22.369530 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5904 13:31:22.373019 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5905 13:31:22.379472 iDelay=199, Bit 10, Center 100 (15 ~ 186) 172
5906 13:31:22.382588 iDelay=199, Bit 11, Center 94 (7 ~ 182) 176
5907 13:31:22.385692 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5908 13:31:22.388881 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5909 13:31:22.392636 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5910 13:31:22.399062 iDelay=199, Bit 15, Center 104 (15 ~ 194) 180
5911 13:31:22.399187 ==
5912 13:31:22.402360 Dram Type= 6, Freq= 0, CH_1, rank 1
5913 13:31:22.405764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5914 13:31:22.405843 ==
5915 13:31:22.405916 DQS Delay:
5916 13:31:22.409164 DQS0 = 0, DQS1 = 0
5917 13:31:22.409249 DQM Delay:
5918 13:31:22.412489 DQM0 = 104, DQM1 = 97
5919 13:31:22.412583 DQ Delay:
5920 13:31:22.415902 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =102
5921 13:31:22.419140 DQ4 =106, DQ5 =114, DQ6 =110, DQ7 =102
5922 13:31:22.422593 DQ8 =84, DQ9 =88, DQ10 =100, DQ11 =94
5923 13:31:22.425624 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =104
5924 13:31:22.425715
5925 13:31:22.425790
5926 13:31:22.435470 [DQSOSCAuto] RK1, (LSB)MR18= 0x1efb, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 412 ps
5927 13:31:22.439001 CH1 RK1: MR19=504, MR18=1EFB
5928 13:31:22.442229 CH1_RK1: MR19=0x504, MR18=0x1EFB, DQSOSC=412, MR23=63, INC=63, DEC=42
5929 13:31:22.445731 [RxdqsGatingPostProcess] freq 933
5930 13:31:22.452337 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5931 13:31:22.455542 best DQS0 dly(2T, 0.5T) = (0, 10)
5932 13:31:22.459025 best DQS1 dly(2T, 0.5T) = (0, 10)
5933 13:31:22.462398 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5934 13:31:22.465849 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5935 13:31:22.469116 best DQS0 dly(2T, 0.5T) = (0, 10)
5936 13:31:22.472090 best DQS1 dly(2T, 0.5T) = (0, 10)
5937 13:31:22.475881 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5938 13:31:22.478974 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5939 13:31:22.479059 Pre-setting of DQS Precalculation
5940 13:31:22.485690 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5941 13:31:22.492507 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5942 13:31:22.498748 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5943 13:31:22.498832
5944 13:31:22.498898
5945 13:31:22.502504 [Calibration Summary] 1866 Mbps
5946 13:31:22.505557 CH 0, Rank 0
5947 13:31:22.505682 SW Impedance : PASS
5948 13:31:22.508737 DUTY Scan : NO K
5949 13:31:22.508871 ZQ Calibration : PASS
5950 13:31:22.512089 Jitter Meter : NO K
5951 13:31:22.515495 CBT Training : PASS
5952 13:31:22.515623 Write leveling : PASS
5953 13:31:22.518998 RX DQS gating : PASS
5954 13:31:22.522223 RX DQ/DQS(RDDQC) : PASS
5955 13:31:22.522345 TX DQ/DQS : PASS
5956 13:31:22.525555 RX DATLAT : PASS
5957 13:31:22.528908 RX DQ/DQS(Engine): PASS
5958 13:31:22.528993 TX OE : NO K
5959 13:31:22.532214 All Pass.
5960 13:31:22.532297
5961 13:31:22.532363 CH 0, Rank 1
5962 13:31:22.535582 SW Impedance : PASS
5963 13:31:22.535696 DUTY Scan : NO K
5964 13:31:22.538737 ZQ Calibration : PASS
5965 13:31:22.542429 Jitter Meter : NO K
5966 13:31:22.542553 CBT Training : PASS
5967 13:31:22.545351 Write leveling : PASS
5968 13:31:22.548655 RX DQS gating : PASS
5969 13:31:22.548780 RX DQ/DQS(RDDQC) : PASS
5970 13:31:22.552469 TX DQ/DQS : PASS
5971 13:31:22.552591 RX DATLAT : PASS
5972 13:31:22.555321 RX DQ/DQS(Engine): PASS
5973 13:31:22.558826 TX OE : NO K
5974 13:31:22.558934 All Pass.
5975 13:31:22.559029
5976 13:31:22.559120 CH 1, Rank 0
5977 13:31:22.561993 SW Impedance : PASS
5978 13:31:22.565326 DUTY Scan : NO K
5979 13:31:22.565444 ZQ Calibration : PASS
5980 13:31:22.568998 Jitter Meter : NO K
5981 13:31:22.571845 CBT Training : PASS
5982 13:31:22.571968 Write leveling : PASS
5983 13:31:22.575164 RX DQS gating : PASS
5984 13:31:22.578834 RX DQ/DQS(RDDQC) : PASS
5985 13:31:22.578946 TX DQ/DQS : PASS
5986 13:31:22.581955 RX DATLAT : PASS
5987 13:31:22.585532 RX DQ/DQS(Engine): PASS
5988 13:31:22.585630 TX OE : NO K
5989 13:31:22.588518 All Pass.
5990 13:31:22.588629
5991 13:31:22.588726 CH 1, Rank 1
5992 13:31:22.591771 SW Impedance : PASS
5993 13:31:22.591907 DUTY Scan : NO K
5994 13:31:22.595504 ZQ Calibration : PASS
5995 13:31:22.598442 Jitter Meter : NO K
5996 13:31:22.598567 CBT Training : PASS
5997 13:31:22.601960 Write leveling : PASS
5998 13:31:22.605660 RX DQS gating : PASS
5999 13:31:22.605780 RX DQ/DQS(RDDQC) : PASS
6000 13:31:22.608487 TX DQ/DQS : PASS
6001 13:31:22.608602 RX DATLAT : PASS
6002 13:31:22.611815 RX DQ/DQS(Engine): PASS
6003 13:31:22.615149 TX OE : NO K
6004 13:31:22.615270 All Pass.
6005 13:31:22.615381
6006 13:31:22.618583 DramC Write-DBI off
6007 13:31:22.618707 PER_BANK_REFRESH: Hybrid Mode
6008 13:31:22.621984 TX_TRACKING: ON
6009 13:31:22.632438 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6010 13:31:22.635190 [FAST_K] Save calibration result to emmc
6011 13:31:22.638572 dramc_set_vcore_voltage set vcore to 650000
6012 13:31:22.638704 Read voltage for 400, 6
6013 13:31:22.642065 Vio18 = 0
6014 13:31:22.642189 Vcore = 650000
6015 13:31:22.642302 Vdram = 0
6016 13:31:22.644995 Vddq = 0
6017 13:31:22.645119 Vmddr = 0
6018 13:31:22.651620 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6019 13:31:22.655429 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6020 13:31:22.658387 MEM_TYPE=3, freq_sel=20
6021 13:31:22.661594 sv_algorithm_assistance_LP4_800
6022 13:31:22.665225 ============ PULL DRAM RESETB DOWN ============
6023 13:31:22.668460 ========== PULL DRAM RESETB DOWN end =========
6024 13:31:22.675193 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6025 13:31:22.678095 ===================================
6026 13:31:22.678216 LPDDR4 DRAM CONFIGURATION
6027 13:31:22.681877 ===================================
6028 13:31:22.685273 EX_ROW_EN[0] = 0x0
6029 13:31:22.685386 EX_ROW_EN[1] = 0x0
6030 13:31:22.688148 LP4Y_EN = 0x0
6031 13:31:22.688267 WORK_FSP = 0x0
6032 13:31:22.691798 WL = 0x2
6033 13:31:22.695091 RL = 0x2
6034 13:31:22.695218 BL = 0x2
6035 13:31:22.698073 RPST = 0x0
6036 13:31:22.698200 RD_PRE = 0x0
6037 13:31:22.701817 WR_PRE = 0x1
6038 13:31:22.701969 WR_PST = 0x0
6039 13:31:22.704806 DBI_WR = 0x0
6040 13:31:22.704931 DBI_RD = 0x0
6041 13:31:22.708396 OTF = 0x1
6042 13:31:22.711465 ===================================
6043 13:31:22.714897 ===================================
6044 13:31:22.715018 ANA top config
6045 13:31:22.718279 ===================================
6046 13:31:22.721527 DLL_ASYNC_EN = 0
6047 13:31:22.725061 ALL_SLAVE_EN = 1
6048 13:31:22.725171 NEW_RANK_MODE = 1
6049 13:31:22.728433 DLL_IDLE_MODE = 1
6050 13:31:22.731623 LP45_APHY_COMB_EN = 1
6051 13:31:22.735177 TX_ODT_DIS = 1
6052 13:31:22.735345 NEW_8X_MODE = 1
6053 13:31:22.738222 ===================================
6054 13:31:22.741470 ===================================
6055 13:31:22.744982 data_rate = 800
6056 13:31:22.748100 CKR = 1
6057 13:31:22.751429 DQ_P2S_RATIO = 4
6058 13:31:22.754891 ===================================
6059 13:31:22.758311 CA_P2S_RATIO = 4
6060 13:31:22.761598 DQ_CA_OPEN = 0
6061 13:31:22.765031 DQ_SEMI_OPEN = 1
6062 13:31:22.765127 CA_SEMI_OPEN = 1
6063 13:31:22.768067 CA_FULL_RATE = 0
6064 13:31:22.771304 DQ_CKDIV4_EN = 0
6065 13:31:22.774366 CA_CKDIV4_EN = 1
6066 13:31:22.777628 CA_PREDIV_EN = 0
6067 13:31:22.781372 PH8_DLY = 0
6068 13:31:22.781455 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6069 13:31:22.784590 DQ_AAMCK_DIV = 0
6070 13:31:22.787972 CA_AAMCK_DIV = 0
6071 13:31:22.791247 CA_ADMCK_DIV = 4
6072 13:31:22.794688 DQ_TRACK_CA_EN = 0
6073 13:31:22.797772 CA_PICK = 800
6074 13:31:22.797855 CA_MCKIO = 400
6075 13:31:22.801309 MCKIO_SEMI = 400
6076 13:31:22.804425 PLL_FREQ = 3016
6077 13:31:22.807877 DQ_UI_PI_RATIO = 32
6078 13:31:22.811107 CA_UI_PI_RATIO = 32
6079 13:31:22.814454 ===================================
6080 13:31:22.817765 ===================================
6081 13:31:22.821151 memory_type:LPDDR4
6082 13:31:22.821234 GP_NUM : 10
6083 13:31:22.824389 SRAM_EN : 1
6084 13:31:22.824473 MD32_EN : 0
6085 13:31:22.827866 ===================================
6086 13:31:22.831141 [ANA_INIT] >>>>>>>>>>>>>>
6087 13:31:22.834465 <<<<<< [CONFIGURE PHASE]: ANA_TX
6088 13:31:22.837664 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6089 13:31:22.840928 ===================================
6090 13:31:22.844371 data_rate = 800,PCW = 0X7400
6091 13:31:22.847627 ===================================
6092 13:31:22.850927 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6093 13:31:22.858137 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6094 13:31:22.867810 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6095 13:31:22.871217 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6096 13:31:22.874501 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6097 13:31:22.877926 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6098 13:31:22.881297 [ANA_INIT] flow start
6099 13:31:22.884640 [ANA_INIT] PLL >>>>>>>>
6100 13:31:22.884725 [ANA_INIT] PLL <<<<<<<<
6101 13:31:22.887713 [ANA_INIT] MIDPI >>>>>>>>
6102 13:31:22.891185 [ANA_INIT] MIDPI <<<<<<<<
6103 13:31:22.891287 [ANA_INIT] DLL >>>>>>>>
6104 13:31:22.894565 [ANA_INIT] flow end
6105 13:31:22.897486 ============ LP4 DIFF to SE enter ============
6106 13:31:22.904217 ============ LP4 DIFF to SE exit ============
6107 13:31:22.904335 [ANA_INIT] <<<<<<<<<<<<<
6108 13:31:22.907767 [Flow] Enable top DCM control >>>>>
6109 13:31:22.911055 [Flow] Enable top DCM control <<<<<
6110 13:31:22.914439 Enable DLL master slave shuffle
6111 13:31:22.921143 ==============================================================
6112 13:31:22.921227 Gating Mode config
6113 13:31:22.927918 ==============================================================
6114 13:31:22.930809 Config description:
6115 13:31:22.937739 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6116 13:31:22.944390 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6117 13:31:22.950892 SELPH_MODE 0: By rank 1: By Phase
6118 13:31:22.957497 ==============================================================
6119 13:31:22.957584 GAT_TRACK_EN = 0
6120 13:31:22.960884 RX_GATING_MODE = 2
6121 13:31:22.964134 RX_GATING_TRACK_MODE = 2
6122 13:31:22.967544 SELPH_MODE = 1
6123 13:31:22.970782 PICG_EARLY_EN = 1
6124 13:31:22.974206 VALID_LAT_VALUE = 1
6125 13:31:22.981047 ==============================================================
6126 13:31:22.983933 Enter into Gating configuration >>>>
6127 13:31:22.987400 Exit from Gating configuration <<<<
6128 13:31:22.990742 Enter into DVFS_PRE_config >>>>>
6129 13:31:23.000966 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6130 13:31:23.004172 Exit from DVFS_PRE_config <<<<<
6131 13:31:23.007488 Enter into PICG configuration >>>>
6132 13:31:23.011265 Exit from PICG configuration <<<<
6133 13:31:23.014096 [RX_INPUT] configuration >>>>>
6134 13:31:23.014198 [RX_INPUT] configuration <<<<<
6135 13:31:23.020549 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6136 13:31:23.027318 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6137 13:31:23.030629 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6138 13:31:23.037577 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6139 13:31:23.044054 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6140 13:31:23.050736 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6141 13:31:23.053821 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6142 13:31:23.057109 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6143 13:31:23.064081 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6144 13:31:23.067407 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6145 13:31:23.070807 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6146 13:31:23.077101 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6147 13:31:23.080441 ===================================
6148 13:31:23.080524 LPDDR4 DRAM CONFIGURATION
6149 13:31:23.084181 ===================================
6150 13:31:23.087175 EX_ROW_EN[0] = 0x0
6151 13:31:23.087262 EX_ROW_EN[1] = 0x0
6152 13:31:23.090970 LP4Y_EN = 0x0
6153 13:31:23.091061 WORK_FSP = 0x0
6154 13:31:23.093713 WL = 0x2
6155 13:31:23.093799 RL = 0x2
6156 13:31:23.096973 BL = 0x2
6157 13:31:23.100331 RPST = 0x0
6158 13:31:23.100414 RD_PRE = 0x0
6159 13:31:23.103957 WR_PRE = 0x1
6160 13:31:23.104086 WR_PST = 0x0
6161 13:31:23.106988 DBI_WR = 0x0
6162 13:31:23.107119 DBI_RD = 0x0
6163 13:31:23.110290 OTF = 0x1
6164 13:31:23.113887 ===================================
6165 13:31:23.116961 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6166 13:31:23.120341 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6167 13:31:23.123373 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6168 13:31:23.126958 ===================================
6169 13:31:23.130339 LPDDR4 DRAM CONFIGURATION
6170 13:31:23.133715 ===================================
6171 13:31:23.137028 EX_ROW_EN[0] = 0x10
6172 13:31:23.137113 EX_ROW_EN[1] = 0x0
6173 13:31:23.140316 LP4Y_EN = 0x0
6174 13:31:23.140400 WORK_FSP = 0x0
6175 13:31:23.143519 WL = 0x2
6176 13:31:23.143603 RL = 0x2
6177 13:31:23.146907 BL = 0x2
6178 13:31:23.146989 RPST = 0x0
6179 13:31:23.150106 RD_PRE = 0x0
6180 13:31:23.150190 WR_PRE = 0x1
6181 13:31:23.153593 WR_PST = 0x0
6182 13:31:23.156970 DBI_WR = 0x0
6183 13:31:23.157053 DBI_RD = 0x0
6184 13:31:23.160277 OTF = 0x1
6185 13:31:23.163498 ===================================
6186 13:31:23.167286 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6187 13:31:23.172224 nWR fixed to 30
6188 13:31:23.175420 [ModeRegInit_LP4] CH0 RK0
6189 13:31:23.175505 [ModeRegInit_LP4] CH0 RK1
6190 13:31:23.178651 [ModeRegInit_LP4] CH1 RK0
6191 13:31:23.182207 [ModeRegInit_LP4] CH1 RK1
6192 13:31:23.182291 match AC timing 19
6193 13:31:23.188877 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6194 13:31:23.192336 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6195 13:31:23.195155 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6196 13:31:23.202436 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6197 13:31:23.205397 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6198 13:31:23.205481 ==
6199 13:31:23.208910 Dram Type= 6, Freq= 0, CH_0, rank 0
6200 13:31:23.212187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6201 13:31:23.212272 ==
6202 13:31:23.219086 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6203 13:31:23.225338 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6204 13:31:23.229035 [CA 0] Center 36 (8~64) winsize 57
6205 13:31:23.232409 [CA 1] Center 36 (8~64) winsize 57
6206 13:31:23.232493 [CA 2] Center 36 (8~64) winsize 57
6207 13:31:23.235275 [CA 3] Center 36 (8~64) winsize 57
6208 13:31:23.239126 [CA 4] Center 36 (8~64) winsize 57
6209 13:31:23.241952 [CA 5] Center 36 (8~64) winsize 57
6210 13:31:23.242037
6211 13:31:23.245391 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6212 13:31:23.245475
6213 13:31:23.252117 [CATrainingPosCal] consider 1 rank data
6214 13:31:23.252201 u2DelayCellTimex100 = 270/100 ps
6215 13:31:23.255312 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 13:31:23.262205 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 13:31:23.265474 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 13:31:23.268768 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 13:31:23.272153 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 13:31:23.275457 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 13:31:23.275542
6222 13:31:23.278670 CA PerBit enable=1, Macro0, CA PI delay=36
6223 13:31:23.278754
6224 13:31:23.281831 [CBTSetCACLKResult] CA Dly = 36
6225 13:31:23.285164 CS Dly: 1 (0~32)
6226 13:31:23.285248 ==
6227 13:31:23.289105 Dram Type= 6, Freq= 0, CH_0, rank 1
6228 13:31:23.292082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6229 13:31:23.292166 ==
6230 13:31:23.298387 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6231 13:31:23.301710 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6232 13:31:23.305496 [CA 0] Center 36 (8~64) winsize 57
6233 13:31:23.308424 [CA 1] Center 36 (8~64) winsize 57
6234 13:31:23.311875 [CA 2] Center 36 (8~64) winsize 57
6235 13:31:23.315293 [CA 3] Center 36 (8~64) winsize 57
6236 13:31:23.318521 [CA 4] Center 36 (8~64) winsize 57
6237 13:31:23.321913 [CA 5] Center 36 (8~64) winsize 57
6238 13:31:23.321999
6239 13:31:23.325273 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6240 13:31:23.325359
6241 13:31:23.328524 [CATrainingPosCal] consider 2 rank data
6242 13:31:23.331799 u2DelayCellTimex100 = 270/100 ps
6243 13:31:23.335332 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 13:31:23.338639 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 13:31:23.341900 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 13:31:23.345120 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 13:31:23.351865 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 13:31:23.355265 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 13:31:23.355367
6250 13:31:23.358553 CA PerBit enable=1, Macro0, CA PI delay=36
6251 13:31:23.358663
6252 13:31:23.362093 [CBTSetCACLKResult] CA Dly = 36
6253 13:31:23.362204 CS Dly: 1 (0~32)
6254 13:31:23.362301
6255 13:31:23.364854 ----->DramcWriteLeveling(PI) begin...
6256 13:31:23.364956 ==
6257 13:31:23.368196 Dram Type= 6, Freq= 0, CH_0, rank 0
6258 13:31:23.375110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6259 13:31:23.375213 ==
6260 13:31:23.378409 Write leveling (Byte 0): 40 => 8
6261 13:31:23.378489 Write leveling (Byte 1): 32 => 0
6262 13:31:23.381859 DramcWriteLeveling(PI) end<-----
6263 13:31:23.381937
6264 13:31:23.382004 ==
6265 13:31:23.385158 Dram Type= 6, Freq= 0, CH_0, rank 0
6266 13:31:23.391466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6267 13:31:23.391579 ==
6268 13:31:23.394731 [Gating] SW mode calibration
6269 13:31:23.401440 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6270 13:31:23.404810 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6271 13:31:23.411432 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6272 13:31:23.415002 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6273 13:31:23.418425 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6274 13:31:23.424573 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6275 13:31:23.427929 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6276 13:31:23.431445 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6277 13:31:23.438074 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6278 13:31:23.441367 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6279 13:31:23.444452 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6280 13:31:23.448011 Total UI for P1: 0, mck2ui 16
6281 13:31:23.451803 best dqsien dly found for B0: ( 0, 14, 24)
6282 13:31:23.454594 Total UI for P1: 0, mck2ui 16
6283 13:31:23.458044 best dqsien dly found for B1: ( 0, 14, 24)
6284 13:31:23.461530 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6285 13:31:23.465245 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6286 13:31:23.465330
6287 13:31:23.468254 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6288 13:31:23.474871 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6289 13:31:23.474987 [Gating] SW calibration Done
6290 13:31:23.475095 ==
6291 13:31:23.478101 Dram Type= 6, Freq= 0, CH_0, rank 0
6292 13:31:23.484703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6293 13:31:23.484843 ==
6294 13:31:23.484940 RX Vref Scan: 0
6295 13:31:23.485041
6296 13:31:23.488305 RX Vref 0 -> 0, step: 1
6297 13:31:23.488414
6298 13:31:23.491482 RX Delay -410 -> 252, step: 16
6299 13:31:23.494752 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6300 13:31:23.497973 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6301 13:31:23.504615 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6302 13:31:23.507753 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6303 13:31:23.511305 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6304 13:31:23.514351 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6305 13:31:23.521268 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6306 13:31:23.524455 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6307 13:31:23.527815 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6308 13:31:23.531203 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6309 13:31:23.537486 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6310 13:31:23.540908 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6311 13:31:23.544476 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6312 13:31:23.547769 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6313 13:31:23.554255 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6314 13:31:23.557407 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6315 13:31:23.557526 ==
6316 13:31:23.561158 Dram Type= 6, Freq= 0, CH_0, rank 0
6317 13:31:23.564020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6318 13:31:23.564143 ==
6319 13:31:23.567613 DQS Delay:
6320 13:31:23.567733 DQS0 = 27, DQS1 = 43
6321 13:31:23.570547 DQM Delay:
6322 13:31:23.570667 DQM0 = 13, DQM1 = 13
6323 13:31:23.570780 DQ Delay:
6324 13:31:23.574473 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =8
6325 13:31:23.577500 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6326 13:31:23.580618 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6327 13:31:23.583971 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6328 13:31:23.584093
6329 13:31:23.584205
6330 13:31:23.584313 ==
6331 13:31:23.587182 Dram Type= 6, Freq= 0, CH_0, rank 0
6332 13:31:23.593994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 13:31:23.594080 ==
6334 13:31:23.594145
6335 13:31:23.594204
6336 13:31:23.594260 TX Vref Scan disable
6337 13:31:23.597218 == TX Byte 0 ==
6338 13:31:23.600432 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6339 13:31:23.604266 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6340 13:31:23.607719 == TX Byte 1 ==
6341 13:31:23.610665 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6342 13:31:23.614074 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6343 13:31:23.614155 ==
6344 13:31:23.617446 Dram Type= 6, Freq= 0, CH_0, rank 0
6345 13:31:23.623799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6346 13:31:23.623893 ==
6347 13:31:23.623957
6348 13:31:23.624014
6349 13:31:23.627561 TX Vref Scan disable
6350 13:31:23.627641 == TX Byte 0 ==
6351 13:31:23.630852 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6352 13:31:23.634043 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6353 13:31:23.637481 == TX Byte 1 ==
6354 13:31:23.640932 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6355 13:31:23.643756 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6356 13:31:23.647257
6357 13:31:23.647336 [DATLAT]
6358 13:31:23.647399 Freq=400, CH0 RK0
6359 13:31:23.647470
6360 13:31:23.650968 DATLAT Default: 0xf
6361 13:31:23.651112 0, 0xFFFF, sum = 0
6362 13:31:23.653876 1, 0xFFFF, sum = 0
6363 13:31:23.653987 2, 0xFFFF, sum = 0
6364 13:31:23.657163 3, 0xFFFF, sum = 0
6365 13:31:23.657245 4, 0xFFFF, sum = 0
6366 13:31:23.660499 5, 0xFFFF, sum = 0
6367 13:31:23.663688 6, 0xFFFF, sum = 0
6368 13:31:23.663796 7, 0xFFFF, sum = 0
6369 13:31:23.667108 8, 0xFFFF, sum = 0
6370 13:31:23.667213 9, 0xFFFF, sum = 0
6371 13:31:23.670648 10, 0xFFFF, sum = 0
6372 13:31:23.670752 11, 0xFFFF, sum = 0
6373 13:31:23.674018 12, 0xFFFF, sum = 0
6374 13:31:23.674129 13, 0x0, sum = 1
6375 13:31:23.677430 14, 0x0, sum = 2
6376 13:31:23.677502 15, 0x0, sum = 3
6377 13:31:23.680347 16, 0x0, sum = 4
6378 13:31:23.680446 best_step = 14
6379 13:31:23.680536
6380 13:31:23.680624 ==
6381 13:31:23.683453 Dram Type= 6, Freq= 0, CH_0, rank 0
6382 13:31:23.687215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6383 13:31:23.687290 ==
6384 13:31:23.690188 RX Vref Scan: 1
6385 13:31:23.690258
6386 13:31:23.693515 RX Vref 0 -> 0, step: 1
6387 13:31:23.693599
6388 13:31:23.693665 RX Delay -327 -> 252, step: 8
6389 13:31:23.696769
6390 13:31:23.696853 Set Vref, RX VrefLevel [Byte0]: 59
6391 13:31:23.700506 [Byte1]: 50
6392 13:31:23.706282
6393 13:31:23.706366 Final RX Vref Byte 0 = 59 to rank0
6394 13:31:23.708994 Final RX Vref Byte 1 = 50 to rank0
6395 13:31:23.712457 Final RX Vref Byte 0 = 59 to rank1
6396 13:31:23.716093 Final RX Vref Byte 1 = 50 to rank1==
6397 13:31:23.719535 Dram Type= 6, Freq= 0, CH_0, rank 0
6398 13:31:23.725650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6399 13:31:23.725733 ==
6400 13:31:23.725801 DQS Delay:
6401 13:31:23.729261 DQS0 = 28, DQS1 = 48
6402 13:31:23.729344 DQM Delay:
6403 13:31:23.729410 DQM0 = 12, DQM1 = 14
6404 13:31:23.732479 DQ Delay:
6405 13:31:23.736042 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6406 13:31:23.736125 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =20
6407 13:31:23.739075 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6408 13:31:23.742407 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6409 13:31:23.742491
6410 13:31:23.746046
6411 13:31:23.752714 [DQSOSCAuto] RK0, (LSB)MR18= 0xa39c, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 389 ps
6412 13:31:23.755588 CH0 RK0: MR19=C0C, MR18=A39C
6413 13:31:23.762305 CH0_RK0: MR19=0xC0C, MR18=0xA39C, DQSOSC=389, MR23=63, INC=390, DEC=260
6414 13:31:23.762407 ==
6415 13:31:23.765809 Dram Type= 6, Freq= 0, CH_0, rank 1
6416 13:31:23.769295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6417 13:31:23.769380 ==
6418 13:31:23.772170 [Gating] SW mode calibration
6419 13:31:23.779047 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6420 13:31:23.785675 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6421 13:31:23.789154 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6422 13:31:23.792596 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6423 13:31:23.799119 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6424 13:31:23.802193 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6425 13:31:23.805547 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6426 13:31:23.809294 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6427 13:31:23.815877 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6428 13:31:23.818690 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6429 13:31:23.822017 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6430 13:31:23.825618 Total UI for P1: 0, mck2ui 16
6431 13:31:23.829174 best dqsien dly found for B0: ( 0, 14, 24)
6432 13:31:23.832403 Total UI for P1: 0, mck2ui 16
6433 13:31:23.835216 best dqsien dly found for B1: ( 0, 14, 24)
6434 13:31:23.838440 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6435 13:31:23.845309 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6436 13:31:23.845445
6437 13:31:23.848928 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6438 13:31:23.852247 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6439 13:31:23.855300 [Gating] SW calibration Done
6440 13:31:23.855426 ==
6441 13:31:23.858546 Dram Type= 6, Freq= 0, CH_0, rank 1
6442 13:31:23.862104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6443 13:31:23.862222 ==
6444 13:31:23.862337 RX Vref Scan: 0
6445 13:31:23.865355
6446 13:31:23.865475 RX Vref 0 -> 0, step: 1
6447 13:31:23.865587
6448 13:31:23.868794 RX Delay -410 -> 252, step: 16
6449 13:31:23.872217 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6450 13:31:23.878832 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6451 13:31:23.881854 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6452 13:31:23.885652 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6453 13:31:23.889230 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6454 13:31:23.895143 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6455 13:31:23.898575 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6456 13:31:23.902069 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6457 13:31:23.905360 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6458 13:31:23.912165 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6459 13:31:23.915168 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6460 13:31:23.918510 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6461 13:31:23.921831 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6462 13:31:23.928621 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6463 13:31:23.932314 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6464 13:31:23.935017 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6465 13:31:23.935094 ==
6466 13:31:23.938851 Dram Type= 6, Freq= 0, CH_0, rank 1
6467 13:31:23.941711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6468 13:31:23.945050 ==
6469 13:31:23.945132 DQS Delay:
6470 13:31:23.945198 DQS0 = 27, DQS1 = 43
6471 13:31:23.948411 DQM Delay:
6472 13:31:23.948532 DQM0 = 9, DQM1 = 14
6473 13:31:23.951807 DQ Delay:
6474 13:31:23.951893 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6475 13:31:23.955275 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6476 13:31:23.958330 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6477 13:31:23.961808 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =16
6478 13:31:23.961894
6479 13:31:23.961960
6480 13:31:23.962022 ==
6481 13:31:23.964928 Dram Type= 6, Freq= 0, CH_0, rank 1
6482 13:31:23.971590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6483 13:31:23.971668 ==
6484 13:31:23.971740
6485 13:31:23.971803
6486 13:31:23.975084 TX Vref Scan disable
6487 13:31:23.975159 == TX Byte 0 ==
6488 13:31:23.978708 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6489 13:31:23.981573 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6490 13:31:23.984954 == TX Byte 1 ==
6491 13:31:23.988192 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6492 13:31:23.991556 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6493 13:31:23.995243 ==
6494 13:31:23.995326 Dram Type= 6, Freq= 0, CH_0, rank 1
6495 13:31:24.001749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6496 13:31:24.001882 ==
6497 13:31:24.002048
6498 13:31:24.002165
6499 13:31:24.005163 TX Vref Scan disable
6500 13:31:24.005239 == TX Byte 0 ==
6501 13:31:24.008006 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6502 13:31:24.011842 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6503 13:31:24.014743 == TX Byte 1 ==
6504 13:31:24.018269 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6505 13:31:24.021588 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6506 13:31:24.024545
6507 13:31:24.024621 [DATLAT]
6508 13:31:24.024684 Freq=400, CH0 RK1
6509 13:31:24.024746
6510 13:31:24.027892 DATLAT Default: 0xe
6511 13:31:24.027963 0, 0xFFFF, sum = 0
6512 13:31:24.031277 1, 0xFFFF, sum = 0
6513 13:31:24.031349 2, 0xFFFF, sum = 0
6514 13:31:24.034571 3, 0xFFFF, sum = 0
6515 13:31:24.034656 4, 0xFFFF, sum = 0
6516 13:31:24.038008 5, 0xFFFF, sum = 0
6517 13:31:24.041213 6, 0xFFFF, sum = 0
6518 13:31:24.041314 7, 0xFFFF, sum = 0
6519 13:31:24.044729 8, 0xFFFF, sum = 0
6520 13:31:24.044876 9, 0xFFFF, sum = 0
6521 13:31:24.047836 10, 0xFFFF, sum = 0
6522 13:31:24.047921 11, 0xFFFF, sum = 0
6523 13:31:24.051179 12, 0xFFFF, sum = 0
6524 13:31:24.051264 13, 0x0, sum = 1
6525 13:31:24.054616 14, 0x0, sum = 2
6526 13:31:24.054700 15, 0x0, sum = 3
6527 13:31:24.057898 16, 0x0, sum = 4
6528 13:31:24.057983 best_step = 14
6529 13:31:24.058071
6530 13:31:24.058145 ==
6531 13:31:24.061372 Dram Type= 6, Freq= 0, CH_0, rank 1
6532 13:31:24.064715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6533 13:31:24.064835 ==
6534 13:31:24.067771 RX Vref Scan: 0
6535 13:31:24.067865
6536 13:31:24.071052 RX Vref 0 -> 0, step: 1
6537 13:31:24.071124
6538 13:31:24.071185 RX Delay -327 -> 252, step: 8
6539 13:31:24.080034 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6540 13:31:24.083902 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6541 13:31:24.086536 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6542 13:31:24.089888 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6543 13:31:24.096652 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6544 13:31:24.099669 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6545 13:31:24.102916 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6546 13:31:24.106254 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6547 13:31:24.112983 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6548 13:31:24.116696 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6549 13:31:24.119962 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6550 13:31:24.126519 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6551 13:31:24.129506 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6552 13:31:24.132948 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6553 13:31:24.136373 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6554 13:31:24.142856 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6555 13:31:24.142940 ==
6556 13:31:24.146230 Dram Type= 6, Freq= 0, CH_0, rank 1
6557 13:31:24.149527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6558 13:31:24.149604 ==
6559 13:31:24.149678 DQS Delay:
6560 13:31:24.152976 DQS0 = 28, DQS1 = 44
6561 13:31:24.153051 DQM Delay:
6562 13:31:24.156352 DQM0 = 10, DQM1 = 15
6563 13:31:24.156425 DQ Delay:
6564 13:31:24.159876 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6565 13:31:24.162734 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6566 13:31:24.166530 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6567 13:31:24.170199 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6568 13:31:24.170284
6569 13:31:24.170360
6570 13:31:24.176480 [DQSOSCAuto] RK1, (LSB)MR18= 0xb065, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 387 ps
6571 13:31:24.179385 CH0 RK1: MR19=C0C, MR18=B065
6572 13:31:24.186106 CH0_RK1: MR19=0xC0C, MR18=0xB065, DQSOSC=387, MR23=63, INC=394, DEC=262
6573 13:31:24.189385 [RxdqsGatingPostProcess] freq 400
6574 13:31:24.195945 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6575 13:31:24.199313 best DQS0 dly(2T, 0.5T) = (0, 10)
6576 13:31:24.199439 best DQS1 dly(2T, 0.5T) = (0, 10)
6577 13:31:24.202854 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6578 13:31:24.206023 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6579 13:31:24.208988 best DQS0 dly(2T, 0.5T) = (0, 10)
6580 13:31:24.212710 best DQS1 dly(2T, 0.5T) = (0, 10)
6581 13:31:24.215957 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6582 13:31:24.219469 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6583 13:31:24.222623 Pre-setting of DQS Precalculation
6584 13:31:24.228967 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6585 13:31:24.229053 ==
6586 13:31:24.232451 Dram Type= 6, Freq= 0, CH_1, rank 0
6587 13:31:24.235941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6588 13:31:24.236031 ==
6589 13:31:24.242786 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6590 13:31:24.245743 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6591 13:31:24.249323 [CA 0] Center 36 (8~64) winsize 57
6592 13:31:24.252484 [CA 1] Center 36 (8~64) winsize 57
6593 13:31:24.255916 [CA 2] Center 36 (8~64) winsize 57
6594 13:31:24.259341 [CA 3] Center 36 (8~64) winsize 57
6595 13:31:24.262361 [CA 4] Center 36 (8~64) winsize 57
6596 13:31:24.265901 [CA 5] Center 36 (8~64) winsize 57
6597 13:31:24.265984
6598 13:31:24.269044 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6599 13:31:24.269126
6600 13:31:24.272531 [CATrainingPosCal] consider 1 rank data
6601 13:31:24.275853 u2DelayCellTimex100 = 270/100 ps
6602 13:31:24.279167 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 13:31:24.282647 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 13:31:24.285647 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 13:31:24.292367 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 13:31:24.295592 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 13:31:24.298963 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 13:31:24.299046
6609 13:31:24.302374 CA PerBit enable=1, Macro0, CA PI delay=36
6610 13:31:24.302458
6611 13:31:24.305656 [CBTSetCACLKResult] CA Dly = 36
6612 13:31:24.305750 CS Dly: 1 (0~32)
6613 13:31:24.305819 ==
6614 13:31:24.308882 Dram Type= 6, Freq= 0, CH_1, rank 1
6615 13:31:24.315589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6616 13:31:24.315673 ==
6617 13:31:24.318897 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6618 13:31:24.325738 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6619 13:31:24.328852 [CA 0] Center 36 (8~64) winsize 57
6620 13:31:24.332102 [CA 1] Center 36 (8~64) winsize 57
6621 13:31:24.335715 [CA 2] Center 36 (8~64) winsize 57
6622 13:31:24.338527 [CA 3] Center 36 (8~64) winsize 57
6623 13:31:24.342359 [CA 4] Center 36 (8~64) winsize 57
6624 13:31:24.345343 [CA 5] Center 36 (8~64) winsize 57
6625 13:31:24.345465
6626 13:31:24.348663 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6627 13:31:24.348797
6628 13:31:24.352111 [CATrainingPosCal] consider 2 rank data
6629 13:31:24.355517 u2DelayCellTimex100 = 270/100 ps
6630 13:31:24.358738 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 13:31:24.362018 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 13:31:24.365374 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 13:31:24.368692 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 13:31:24.371844 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 13:31:24.375188 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 13:31:24.375302
6637 13:31:24.381884 CA PerBit enable=1, Macro0, CA PI delay=36
6638 13:31:24.382052
6639 13:31:24.385257 [CBTSetCACLKResult] CA Dly = 36
6640 13:31:24.385387 CS Dly: 1 (0~32)
6641 13:31:24.385485
6642 13:31:24.388611 ----->DramcWriteLeveling(PI) begin...
6643 13:31:24.388718 ==
6644 13:31:24.391981 Dram Type= 6, Freq= 0, CH_1, rank 0
6645 13:31:24.395266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6646 13:31:24.395351 ==
6647 13:31:24.398469 Write leveling (Byte 0): 40 => 8
6648 13:31:24.401885 Write leveling (Byte 1): 32 => 0
6649 13:31:24.405310 DramcWriteLeveling(PI) end<-----
6650 13:31:24.405463
6651 13:31:24.405608 ==
6652 13:31:24.408450 Dram Type= 6, Freq= 0, CH_1, rank 0
6653 13:31:24.411590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6654 13:31:24.415561 ==
6655 13:31:24.415646 [Gating] SW mode calibration
6656 13:31:24.425080 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6657 13:31:24.428454 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6658 13:31:24.431786 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6659 13:31:24.438562 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6660 13:31:24.442131 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6661 13:31:24.445090 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6662 13:31:24.451686 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6663 13:31:24.455144 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6664 13:31:24.458456 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6665 13:31:24.465432 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6666 13:31:24.468804 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6667 13:31:24.471900 Total UI for P1: 0, mck2ui 16
6668 13:31:24.475437 best dqsien dly found for B0: ( 0, 14, 24)
6669 13:31:24.478423 Total UI for P1: 0, mck2ui 16
6670 13:31:24.481673 best dqsien dly found for B1: ( 0, 14, 24)
6671 13:31:24.485199 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6672 13:31:24.488491 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6673 13:31:24.488593
6674 13:31:24.491679 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6675 13:31:24.495268 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6676 13:31:24.498398 [Gating] SW calibration Done
6677 13:31:24.498488 ==
6678 13:31:24.501774 Dram Type= 6, Freq= 0, CH_1, rank 0
6679 13:31:24.505332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6680 13:31:24.505413 ==
6681 13:31:24.508733 RX Vref Scan: 0
6682 13:31:24.508819
6683 13:31:24.512179 RX Vref 0 -> 0, step: 1
6684 13:31:24.512263
6685 13:31:24.512338 RX Delay -410 -> 252, step: 16
6686 13:31:24.518605 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6687 13:31:24.521983 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6688 13:31:24.525374 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6689 13:31:24.528781 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6690 13:31:24.535204 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6691 13:31:24.538868 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6692 13:31:24.541611 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6693 13:31:24.545066 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6694 13:31:24.551481 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6695 13:31:24.555177 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6696 13:31:24.558532 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6697 13:31:24.562047 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6698 13:31:24.568341 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6699 13:31:24.571956 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6700 13:31:24.574989 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6701 13:31:24.581835 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6702 13:31:24.581923 ==
6703 13:31:24.585316 Dram Type= 6, Freq= 0, CH_1, rank 0
6704 13:31:24.588577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6705 13:31:24.588688 ==
6706 13:31:24.588807 DQS Delay:
6707 13:31:24.591522 DQS0 = 27, DQS1 = 43
6708 13:31:24.591606 DQM Delay:
6709 13:31:24.594926 DQM0 = 8, DQM1 = 17
6710 13:31:24.595017 DQ Delay:
6711 13:31:24.598292 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6712 13:31:24.601757 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6713 13:31:24.604946 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6714 13:31:24.608154 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6715 13:31:24.608261
6716 13:31:24.608360
6717 13:31:24.608463 ==
6718 13:31:24.611724 Dram Type= 6, Freq= 0, CH_1, rank 0
6719 13:31:24.615597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 13:31:24.615702 ==
6721 13:31:24.615796
6722 13:31:24.615886
6723 13:31:24.618249 TX Vref Scan disable
6724 13:31:24.618333 == TX Byte 0 ==
6725 13:31:24.624959 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6726 13:31:24.628154 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6727 13:31:24.628269 == TX Byte 1 ==
6728 13:31:24.635112 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6729 13:31:24.638456 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6730 13:31:24.638572 ==
6731 13:31:24.641403 Dram Type= 6, Freq= 0, CH_1, rank 0
6732 13:31:24.645878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6733 13:31:24.645997 ==
6734 13:31:24.646100
6735 13:31:24.646193
6736 13:31:24.648258 TX Vref Scan disable
6737 13:31:24.651623 == TX Byte 0 ==
6738 13:31:24.654935 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6739 13:31:24.658155 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6740 13:31:24.658266 == TX Byte 1 ==
6741 13:31:24.664556 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6742 13:31:24.667940 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6743 13:31:24.668036
6744 13:31:24.668106 [DATLAT]
6745 13:31:24.671293 Freq=400, CH1 RK0
6746 13:31:24.671383
6747 13:31:24.671453 DATLAT Default: 0xf
6748 13:31:24.674754 0, 0xFFFF, sum = 0
6749 13:31:24.674841 1, 0xFFFF, sum = 0
6750 13:31:24.678016 2, 0xFFFF, sum = 0
6751 13:31:24.681088 3, 0xFFFF, sum = 0
6752 13:31:24.681223 4, 0xFFFF, sum = 0
6753 13:31:24.684502 5, 0xFFFF, sum = 0
6754 13:31:24.684628 6, 0xFFFF, sum = 0
6755 13:31:24.687965 7, 0xFFFF, sum = 0
6756 13:31:24.688092 8, 0xFFFF, sum = 0
6757 13:31:24.690876 9, 0xFFFF, sum = 0
6758 13:31:24.690994 10, 0xFFFF, sum = 0
6759 13:31:24.694323 11, 0xFFFF, sum = 0
6760 13:31:24.694445 12, 0xFFFF, sum = 0
6761 13:31:24.697641 13, 0x0, sum = 1
6762 13:31:24.697758 14, 0x0, sum = 2
6763 13:31:24.701075 15, 0x0, sum = 3
6764 13:31:24.701202 16, 0x0, sum = 4
6765 13:31:24.704374 best_step = 14
6766 13:31:24.704502
6767 13:31:24.704612 ==
6768 13:31:24.707723 Dram Type= 6, Freq= 0, CH_1, rank 0
6769 13:31:24.711348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6770 13:31:24.711470 ==
6771 13:31:24.711578 RX Vref Scan: 1
6772 13:31:24.714336
6773 13:31:24.714467 RX Vref 0 -> 0, step: 1
6774 13:31:24.714567
6775 13:31:24.717809 RX Delay -327 -> 252, step: 8
6776 13:31:24.717937
6777 13:31:24.721300 Set Vref, RX VrefLevel [Byte0]: 52
6778 13:31:24.724370 [Byte1]: 58
6779 13:31:24.728353
6780 13:31:24.728465 Final RX Vref Byte 0 = 52 to rank0
6781 13:31:24.731732 Final RX Vref Byte 1 = 58 to rank0
6782 13:31:24.735064 Final RX Vref Byte 0 = 52 to rank1
6783 13:31:24.738251 Final RX Vref Byte 1 = 58 to rank1==
6784 13:31:24.741851 Dram Type= 6, Freq= 0, CH_1, rank 0
6785 13:31:24.748108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6786 13:31:24.748222 ==
6787 13:31:24.748321 DQS Delay:
6788 13:31:24.751636 DQS0 = 32, DQS1 = 44
6789 13:31:24.751737 DQM Delay:
6790 13:31:24.751829 DQM0 = 11, DQM1 = 15
6791 13:31:24.755289 DQ Delay:
6792 13:31:24.758769 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6793 13:31:24.758872 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6794 13:31:24.761824 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =8
6795 13:31:24.764958 DQ12 =28, DQ13 =24, DQ14 =20, DQ15 =20
6796 13:31:24.765065
6797 13:31:24.765159
6798 13:31:24.774976 [DQSOSCAuto] RK0, (LSB)MR18= 0x8dc7, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6799 13:31:24.778300 CH1 RK0: MR19=C0C, MR18=8DC7
6800 13:31:24.784894 CH1_RK0: MR19=0xC0C, MR18=0x8DC7, DQSOSC=385, MR23=63, INC=398, DEC=265
6801 13:31:24.785000 ==
6802 13:31:24.788414 Dram Type= 6, Freq= 0, CH_1, rank 1
6803 13:31:24.791469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6804 13:31:24.791582 ==
6805 13:31:24.794862 [Gating] SW mode calibration
6806 13:31:24.801768 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6807 13:31:24.805205 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6808 13:31:24.811541 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6809 13:31:24.814878 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6810 13:31:24.818071 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6811 13:31:24.824685 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6812 13:31:24.828084 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6813 13:31:24.831486 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6814 13:31:24.838372 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6815 13:31:24.841609 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6816 13:31:24.845090 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6817 13:31:24.847825 Total UI for P1: 0, mck2ui 16
6818 13:31:24.851201 best dqsien dly found for B0: ( 0, 14, 24)
6819 13:31:24.854824 Total UI for P1: 0, mck2ui 16
6820 13:31:24.858112 best dqsien dly found for B1: ( 0, 14, 24)
6821 13:31:24.861291 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6822 13:31:24.864592 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6823 13:31:24.868062
6824 13:31:24.871316 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6825 13:31:24.874489 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6826 13:31:24.877784 [Gating] SW calibration Done
6827 13:31:24.877907 ==
6828 13:31:24.881093 Dram Type= 6, Freq= 0, CH_1, rank 1
6829 13:31:24.884828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6830 13:31:24.884920 ==
6831 13:31:24.885006 RX Vref Scan: 0
6832 13:31:24.885086
6833 13:31:24.887792 RX Vref 0 -> 0, step: 1
6834 13:31:24.887879
6835 13:31:24.891478 RX Delay -410 -> 252, step: 16
6836 13:31:24.894407 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6837 13:31:24.901264 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6838 13:31:24.904573 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6839 13:31:24.908228 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6840 13:31:24.911174 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6841 13:31:24.917821 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6842 13:31:24.921260 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6843 13:31:24.924458 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6844 13:31:24.927816 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6845 13:31:24.931072 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6846 13:31:24.937913 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6847 13:31:24.941340 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6848 13:31:24.944770 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6849 13:31:24.951238 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6850 13:31:24.955121 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6851 13:31:24.957992 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6852 13:31:24.958078 ==
6853 13:31:24.961388 Dram Type= 6, Freq= 0, CH_1, rank 1
6854 13:31:24.964492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6855 13:31:24.964605 ==
6856 13:31:24.968046 DQS Delay:
6857 13:31:24.968131 DQS0 = 35, DQS1 = 43
6858 13:31:24.971202 DQM Delay:
6859 13:31:24.971286 DQM0 = 16, DQM1 = 20
6860 13:31:24.971353 DQ Delay:
6861 13:31:24.974927 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6862 13:31:24.978126 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6863 13:31:24.981516 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6864 13:31:24.984725 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6865 13:31:24.984835
6866 13:31:24.984902
6867 13:31:24.988361 ==
6868 13:31:24.988444 Dram Type= 6, Freq= 0, CH_1, rank 1
6869 13:31:24.994482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6870 13:31:24.994569 ==
6871 13:31:24.994638
6872 13:31:24.994746
6873 13:31:24.997876 TX Vref Scan disable
6874 13:31:24.997962 == TX Byte 0 ==
6875 13:31:25.001377 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6876 13:31:25.005009 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6877 13:31:25.008169 == TX Byte 1 ==
6878 13:31:25.011586 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6879 13:31:25.014900 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6880 13:31:25.017934 ==
6881 13:31:25.021017 Dram Type= 6, Freq= 0, CH_1, rank 1
6882 13:31:25.024281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6883 13:31:25.024365 ==
6884 13:31:25.024431
6885 13:31:25.024522
6886 13:31:25.027913 TX Vref Scan disable
6887 13:31:25.027996 == TX Byte 0 ==
6888 13:31:25.031097 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6889 13:31:25.037639 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6890 13:31:25.037725 == TX Byte 1 ==
6891 13:31:25.041116 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6892 13:31:25.047781 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6893 13:31:25.047867
6894 13:31:25.047948 [DATLAT]
6895 13:31:25.048008 Freq=400, CH1 RK1
6896 13:31:25.048087
6897 13:31:25.050809 DATLAT Default: 0xe
6898 13:31:25.050895 0, 0xFFFF, sum = 0
6899 13:31:25.054261 1, 0xFFFF, sum = 0
6900 13:31:25.057761 2, 0xFFFF, sum = 0
6901 13:31:25.057846 3, 0xFFFF, sum = 0
6902 13:31:25.060603 4, 0xFFFF, sum = 0
6903 13:31:25.060679 5, 0xFFFF, sum = 0
6904 13:31:25.064091 6, 0xFFFF, sum = 0
6905 13:31:25.064178 7, 0xFFFF, sum = 0
6906 13:31:25.067530 8, 0xFFFF, sum = 0
6907 13:31:25.067614 9, 0xFFFF, sum = 0
6908 13:31:25.070737 10, 0xFFFF, sum = 0
6909 13:31:25.070821 11, 0xFFFF, sum = 0
6910 13:31:25.074072 12, 0xFFFF, sum = 0
6911 13:31:25.074195 13, 0x0, sum = 1
6912 13:31:25.077457 14, 0x0, sum = 2
6913 13:31:25.077548 15, 0x0, sum = 3
6914 13:31:25.080593 16, 0x0, sum = 4
6915 13:31:25.080725 best_step = 14
6916 13:31:25.080854
6917 13:31:25.080968 ==
6918 13:31:25.084122 Dram Type= 6, Freq= 0, CH_1, rank 1
6919 13:31:25.087279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6920 13:31:25.090647 ==
6921 13:31:25.090771 RX Vref Scan: 0
6922 13:31:25.090881
6923 13:31:25.094090 RX Vref 0 -> 0, step: 1
6924 13:31:25.094214
6925 13:31:25.097524 RX Delay -327 -> 252, step: 8
6926 13:31:25.100720 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6927 13:31:25.107187 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6928 13:31:25.110440 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6929 13:31:25.114120 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6930 13:31:25.117035 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6931 13:31:25.123556 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6932 13:31:25.126892 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6933 13:31:25.130273 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6934 13:31:25.133713 iDelay=217, Bit 8, Center -40 (-271 ~ 192) 464
6935 13:31:25.140435 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6936 13:31:25.143881 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6937 13:31:25.147214 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6938 13:31:25.153472 iDelay=217, Bit 12, Center -16 (-247 ~ 216) 464
6939 13:31:25.156966 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6940 13:31:25.160441 iDelay=217, Bit 14, Center -24 (-255 ~ 208) 464
6941 13:31:25.163252 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6942 13:31:25.163366 ==
6943 13:31:25.166811 Dram Type= 6, Freq= 0, CH_1, rank 1
6944 13:31:25.173444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6945 13:31:25.173530 ==
6946 13:31:25.173597 DQS Delay:
6947 13:31:25.176691 DQS0 = 32, DQS1 = 40
6948 13:31:25.176801 DQM Delay:
6949 13:31:25.180441 DQM0 = 13, DQM1 = 15
6950 13:31:25.180555 DQ Delay:
6951 13:31:25.183352 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =16
6952 13:31:25.187004 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =8
6953 13:31:25.189987 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =12
6954 13:31:25.193538 DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =24
6955 13:31:25.193647
6956 13:31:25.193748
6957 13:31:25.200193 [DQSOSCAuto] RK1, (LSB)MR18= 0xa74f, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 389 ps
6958 13:31:25.203710 CH1 RK1: MR19=C0C, MR18=A74F
6959 13:31:25.209960 CH1_RK1: MR19=0xC0C, MR18=0xA74F, DQSOSC=389, MR23=63, INC=390, DEC=260
6960 13:31:25.213308 [RxdqsGatingPostProcess] freq 400
6961 13:31:25.216742 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6962 13:31:25.219810 best DQS0 dly(2T, 0.5T) = (0, 10)
6963 13:31:25.223473 best DQS1 dly(2T, 0.5T) = (0, 10)
6964 13:31:25.226539 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6965 13:31:25.229896 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6966 13:31:25.233200 best DQS0 dly(2T, 0.5T) = (0, 10)
6967 13:31:25.236720 best DQS1 dly(2T, 0.5T) = (0, 10)
6968 13:31:25.239804 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6969 13:31:25.243123 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6970 13:31:25.246525 Pre-setting of DQS Precalculation
6971 13:31:25.249966 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6972 13:31:25.259952 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6973 13:31:25.266293 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6974 13:31:25.266379
6975 13:31:25.266445
6976 13:31:25.269752 [Calibration Summary] 800 Mbps
6977 13:31:25.269837 CH 0, Rank 0
6978 13:31:25.273209 SW Impedance : PASS
6979 13:31:25.273294 DUTY Scan : NO K
6980 13:31:25.276511 ZQ Calibration : PASS
6981 13:31:25.279895 Jitter Meter : NO K
6982 13:31:25.279979 CBT Training : PASS
6983 13:31:25.283345 Write leveling : PASS
6984 13:31:25.286563 RX DQS gating : PASS
6985 13:31:25.286647 RX DQ/DQS(RDDQC) : PASS
6986 13:31:25.289678 TX DQ/DQS : PASS
6987 13:31:25.289761 RX DATLAT : PASS
6988 13:31:25.293127 RX DQ/DQS(Engine): PASS
6989 13:31:25.296405 TX OE : NO K
6990 13:31:25.296515 All Pass.
6991 13:31:25.296615
6992 13:31:25.296709 CH 0, Rank 1
6993 13:31:25.300041 SW Impedance : PASS
6994 13:31:25.302907 DUTY Scan : NO K
6995 13:31:25.303014 ZQ Calibration : PASS
6996 13:31:25.306090 Jitter Meter : NO K
6997 13:31:25.309609 CBT Training : PASS
6998 13:31:25.309720 Write leveling : NO K
6999 13:31:25.312960 RX DQS gating : PASS
7000 13:31:25.316253 RX DQ/DQS(RDDQC) : PASS
7001 13:31:25.316358 TX DQ/DQS : PASS
7002 13:31:25.319485 RX DATLAT : PASS
7003 13:31:25.322947 RX DQ/DQS(Engine): PASS
7004 13:31:25.323060 TX OE : NO K
7005 13:31:25.326160 All Pass.
7006 13:31:25.326270
7007 13:31:25.326366 CH 1, Rank 0
7008 13:31:25.329377 SW Impedance : PASS
7009 13:31:25.329497 DUTY Scan : NO K
7010 13:31:25.332810 ZQ Calibration : PASS
7011 13:31:25.336183 Jitter Meter : NO K
7012 13:31:25.336261 CBT Training : PASS
7013 13:31:25.339454 Write leveling : PASS
7014 13:31:25.339581 RX DQS gating : PASS
7015 13:31:25.342778 RX DQ/DQS(RDDQC) : PASS
7016 13:31:25.346185 TX DQ/DQS : PASS
7017 13:31:25.346311 RX DATLAT : PASS
7018 13:31:25.349425 RX DQ/DQS(Engine): PASS
7019 13:31:25.352857 TX OE : NO K
7020 13:31:25.352983 All Pass.
7021 13:31:25.353093
7022 13:31:25.353203 CH 1, Rank 1
7023 13:31:25.356183 SW Impedance : PASS
7024 13:31:25.359233 DUTY Scan : NO K
7025 13:31:25.359355 ZQ Calibration : PASS
7026 13:31:25.362624 Jitter Meter : NO K
7027 13:31:25.366156 CBT Training : PASS
7028 13:31:25.366279 Write leveling : NO K
7029 13:31:25.369641 RX DQS gating : PASS
7030 13:31:25.372480 RX DQ/DQS(RDDQC) : PASS
7031 13:31:25.372608 TX DQ/DQS : PASS
7032 13:31:25.375907 RX DATLAT : PASS
7033 13:31:25.379744 RX DQ/DQS(Engine): PASS
7034 13:31:25.379858 TX OE : NO K
7035 13:31:25.382662 All Pass.
7036 13:31:25.382746
7037 13:31:25.382813 DramC Write-DBI off
7038 13:31:25.386015 PER_BANK_REFRESH: Hybrid Mode
7039 13:31:25.386102 TX_TRACKING: ON
7040 13:31:25.395844 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7041 13:31:25.399133 [FAST_K] Save calibration result to emmc
7042 13:31:25.402709 dramc_set_vcore_voltage set vcore to 725000
7043 13:31:25.405923 Read voltage for 1600, 0
7044 13:31:25.406010 Vio18 = 0
7045 13:31:25.409118 Vcore = 725000
7046 13:31:25.409204 Vdram = 0
7047 13:31:25.409272 Vddq = 0
7048 13:31:25.409335 Vmddr = 0
7049 13:31:25.416083 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7050 13:31:25.422492 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7051 13:31:25.422579 MEM_TYPE=3, freq_sel=13
7052 13:31:25.425935 sv_algorithm_assistance_LP4_3733
7053 13:31:25.429246 ============ PULL DRAM RESETB DOWN ============
7054 13:31:25.435908 ========== PULL DRAM RESETB DOWN end =========
7055 13:31:25.439437 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7056 13:31:25.442218 ===================================
7057 13:31:25.445566 LPDDR4 DRAM CONFIGURATION
7058 13:31:25.449364 ===================================
7059 13:31:25.449494 EX_ROW_EN[0] = 0x0
7060 13:31:25.452522 EX_ROW_EN[1] = 0x0
7061 13:31:25.455523 LP4Y_EN = 0x0
7062 13:31:25.455626 WORK_FSP = 0x1
7063 13:31:25.458846 WL = 0x5
7064 13:31:25.458923 RL = 0x5
7065 13:31:25.462289 BL = 0x2
7066 13:31:25.462389 RPST = 0x0
7067 13:31:25.465768 RD_PRE = 0x0
7068 13:31:25.465841 WR_PRE = 0x1
7069 13:31:25.469129 WR_PST = 0x1
7070 13:31:25.469205 DBI_WR = 0x0
7071 13:31:25.472406 DBI_RD = 0x0
7072 13:31:25.472507 OTF = 0x1
7073 13:31:25.475856 ===================================
7074 13:31:25.478735 ===================================
7075 13:31:25.482095 ANA top config
7076 13:31:25.485499 ===================================
7077 13:31:25.485610 DLL_ASYNC_EN = 0
7078 13:31:25.489047 ALL_SLAVE_EN = 0
7079 13:31:25.492622 NEW_RANK_MODE = 1
7080 13:31:25.495511 DLL_IDLE_MODE = 1
7081 13:31:25.499113 LP45_APHY_COMB_EN = 1
7082 13:31:25.499197 TX_ODT_DIS = 0
7083 13:31:25.502487 NEW_8X_MODE = 1
7084 13:31:25.505375 ===================================
7085 13:31:25.508922 ===================================
7086 13:31:25.512344 data_rate = 3200
7087 13:31:25.515602 CKR = 1
7088 13:31:25.519050 DQ_P2S_RATIO = 8
7089 13:31:25.522070 ===================================
7090 13:31:25.522154 CA_P2S_RATIO = 8
7091 13:31:25.525071 DQ_CA_OPEN = 0
7092 13:31:25.528604 DQ_SEMI_OPEN = 0
7093 13:31:25.531832 CA_SEMI_OPEN = 0
7094 13:31:25.535293 CA_FULL_RATE = 0
7095 13:31:25.538634 DQ_CKDIV4_EN = 0
7096 13:31:25.538720 CA_CKDIV4_EN = 0
7097 13:31:25.541918 CA_PREDIV_EN = 0
7098 13:31:25.545464 PH8_DLY = 12
7099 13:31:25.548655 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7100 13:31:25.551704 DQ_AAMCK_DIV = 4
7101 13:31:25.555036 CA_AAMCK_DIV = 4
7102 13:31:25.555131 CA_ADMCK_DIV = 4
7103 13:31:25.558648 DQ_TRACK_CA_EN = 0
7104 13:31:25.561539 CA_PICK = 1600
7105 13:31:25.564952 CA_MCKIO = 1600
7106 13:31:25.568305 MCKIO_SEMI = 0
7107 13:31:25.571834 PLL_FREQ = 3068
7108 13:31:25.574841 DQ_UI_PI_RATIO = 32
7109 13:31:25.578161 CA_UI_PI_RATIO = 0
7110 13:31:25.581501 ===================================
7111 13:31:25.581625 ===================================
7112 13:31:25.584718 memory_type:LPDDR4
7113 13:31:25.588157 GP_NUM : 10
7114 13:31:25.588258 SRAM_EN : 1
7115 13:31:25.591441 MD32_EN : 0
7116 13:31:25.594808 ===================================
7117 13:31:25.598332 [ANA_INIT] >>>>>>>>>>>>>>
7118 13:31:25.601781 <<<<<< [CONFIGURE PHASE]: ANA_TX
7119 13:31:25.605113 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7120 13:31:25.608109 ===================================
7121 13:31:25.608193 data_rate = 3200,PCW = 0X7600
7122 13:31:25.611689 ===================================
7123 13:31:25.614931 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7124 13:31:25.621730 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7125 13:31:25.628049 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7126 13:31:25.631175 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7127 13:31:25.634756 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7128 13:31:25.638339 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7129 13:31:25.641632 [ANA_INIT] flow start
7130 13:31:25.644552 [ANA_INIT] PLL >>>>>>>>
7131 13:31:25.644676 [ANA_INIT] PLL <<<<<<<<
7132 13:31:25.648399 [ANA_INIT] MIDPI >>>>>>>>
7133 13:31:25.651956 [ANA_INIT] MIDPI <<<<<<<<
7134 13:31:25.652085 [ANA_INIT] DLL >>>>>>>>
7135 13:31:25.654637 [ANA_INIT] DLL <<<<<<<<
7136 13:31:25.657871 [ANA_INIT] flow end
7137 13:31:25.661078 ============ LP4 DIFF to SE enter ============
7138 13:31:25.664552 ============ LP4 DIFF to SE exit ============
7139 13:31:25.668008 [ANA_INIT] <<<<<<<<<<<<<
7140 13:31:25.671299 [Flow] Enable top DCM control >>>>>
7141 13:31:25.674352 [Flow] Enable top DCM control <<<<<
7142 13:31:25.677700 Enable DLL master slave shuffle
7143 13:31:25.681127 ==============================================================
7144 13:31:25.684474 Gating Mode config
7145 13:31:25.691415 ==============================================================
7146 13:31:25.691540 Config description:
7147 13:31:25.701184 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7148 13:31:25.707555 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7149 13:31:25.714118 SELPH_MODE 0: By rank 1: By Phase
7150 13:31:25.717430 ==============================================================
7151 13:31:25.720738 GAT_TRACK_EN = 1
7152 13:31:25.724412 RX_GATING_MODE = 2
7153 13:31:25.727623 RX_GATING_TRACK_MODE = 2
7154 13:31:25.730576 SELPH_MODE = 1
7155 13:31:25.734085 PICG_EARLY_EN = 1
7156 13:31:25.737751 VALID_LAT_VALUE = 1
7157 13:31:25.740606 ==============================================================
7158 13:31:25.743956 Enter into Gating configuration >>>>
7159 13:31:25.747286 Exit from Gating configuration <<<<
7160 13:31:25.750622 Enter into DVFS_PRE_config >>>>>
7161 13:31:25.763944 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7162 13:31:25.767270 Exit from DVFS_PRE_config <<<<<
7163 13:31:25.767395 Enter into PICG configuration >>>>
7164 13:31:25.770766 Exit from PICG configuration <<<<
7165 13:31:25.773776 [RX_INPUT] configuration >>>>>
7166 13:31:25.777145 [RX_INPUT] configuration <<<<<
7167 13:31:25.783733 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7168 13:31:25.787359 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7169 13:31:25.793953 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7170 13:31:25.800387 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7171 13:31:25.806996 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7172 13:31:25.813375 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7173 13:31:25.816652 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7174 13:31:25.820117 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7175 13:31:25.823388 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7176 13:31:25.830180 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7177 13:31:25.833958 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7178 13:31:25.836721 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7179 13:31:25.840064 ===================================
7180 13:31:25.843498 LPDDR4 DRAM CONFIGURATION
7181 13:31:25.846831 ===================================
7182 13:31:25.849892 EX_ROW_EN[0] = 0x0
7183 13:31:25.850006 EX_ROW_EN[1] = 0x0
7184 13:31:25.853470 LP4Y_EN = 0x0
7185 13:31:25.853554 WORK_FSP = 0x1
7186 13:31:25.857095 WL = 0x5
7187 13:31:25.857180 RL = 0x5
7188 13:31:25.860240 BL = 0x2
7189 13:31:25.860325 RPST = 0x0
7190 13:31:25.863321 RD_PRE = 0x0
7191 13:31:25.863405 WR_PRE = 0x1
7192 13:31:25.866694 WR_PST = 0x1
7193 13:31:25.866778 DBI_WR = 0x0
7194 13:31:25.870282 DBI_RD = 0x0
7195 13:31:25.870365 OTF = 0x1
7196 13:31:25.873686 ===================================
7197 13:31:25.879864 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7198 13:31:25.883378 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7199 13:31:25.886785 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7200 13:31:25.890217 ===================================
7201 13:31:25.893234 LPDDR4 DRAM CONFIGURATION
7202 13:31:25.896662 ===================================
7203 13:31:25.896795 EX_ROW_EN[0] = 0x10
7204 13:31:25.899815 EX_ROW_EN[1] = 0x0
7205 13:31:25.902975 LP4Y_EN = 0x0
7206 13:31:25.903100 WORK_FSP = 0x1
7207 13:31:25.907082 WL = 0x5
7208 13:31:25.907204 RL = 0x5
7209 13:31:25.909732 BL = 0x2
7210 13:31:25.909856 RPST = 0x0
7211 13:31:25.913010 RD_PRE = 0x0
7212 13:31:25.913135 WR_PRE = 0x1
7213 13:31:25.916339 WR_PST = 0x1
7214 13:31:25.916470 DBI_WR = 0x0
7215 13:31:25.919807 DBI_RD = 0x0
7216 13:31:25.919928 OTF = 0x1
7217 13:31:25.923144 ===================================
7218 13:31:25.929827 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7219 13:31:25.929952 ==
7220 13:31:25.932812 Dram Type= 6, Freq= 0, CH_0, rank 0
7221 13:31:25.936296 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7222 13:31:25.939556 ==
7223 13:31:25.939665 [Duty_Offset_Calibration]
7224 13:31:25.942904 B0:2 B1:0 CA:1
7225 13:31:25.943018
7226 13:31:25.946670 [DutyScan_Calibration_Flow] k_type=0
7227 13:31:25.954630
7228 13:31:25.954743 ==CLK 0==
7229 13:31:25.957745 Final CLK duty delay cell = -4
7230 13:31:25.961299 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7231 13:31:25.964346 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7232 13:31:25.967584 [-4] AVG Duty = 4922%(X100)
7233 13:31:25.967687
7234 13:31:25.971061 CH0 CLK Duty spec in!! Max-Min= 156%
7235 13:31:25.974268 [DutyScan_Calibration_Flow] ====Done====
7236 13:31:25.974351
7237 13:31:25.977546 [DutyScan_Calibration_Flow] k_type=1
7238 13:31:25.994144
7239 13:31:25.994227 ==DQS 0 ==
7240 13:31:25.997487 Final DQS duty delay cell = 0
7241 13:31:26.000629 [0] MAX Duty = 5249%(X100), DQS PI = 32
7242 13:31:26.003699 [0] MIN Duty = 4969%(X100), DQS PI = 0
7243 13:31:26.003824 [0] AVG Duty = 5109%(X100)
7244 13:31:26.007451
7245 13:31:26.007572 ==DQS 1 ==
7246 13:31:26.010281 Final DQS duty delay cell = -4
7247 13:31:26.013669 [-4] MAX Duty = 5125%(X100), DQS PI = 30
7248 13:31:26.017264 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7249 13:31:26.020233 [-4] AVG Duty = 5000%(X100)
7250 13:31:26.020317
7251 13:31:26.023542 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7252 13:31:26.023626
7253 13:31:26.027361 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7254 13:31:26.030152 [DutyScan_Calibration_Flow] ====Done====
7255 13:31:26.030236
7256 13:31:26.033467 [DutyScan_Calibration_Flow] k_type=3
7257 13:31:26.051165
7258 13:31:26.051250 ==DQM 0 ==
7259 13:31:26.054567 Final DQM duty delay cell = 0
7260 13:31:26.058122 [0] MAX Duty = 5093%(X100), DQS PI = 26
7261 13:31:26.061435 [0] MIN Duty = 4813%(X100), DQS PI = 50
7262 13:31:26.061542 [0] AVG Duty = 4953%(X100)
7263 13:31:26.064556
7264 13:31:26.064677 ==DQM 1 ==
7265 13:31:26.068278 Final DQM duty delay cell = 0
7266 13:31:26.071385 [0] MAX Duty = 5249%(X100), DQS PI = 28
7267 13:31:26.074921 [0] MIN Duty = 5031%(X100), DQS PI = 6
7268 13:31:26.075046 [0] AVG Duty = 5140%(X100)
7269 13:31:26.077951
7270 13:31:26.081085 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7271 13:31:26.081221
7272 13:31:26.084596 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7273 13:31:26.087949 [DutyScan_Calibration_Flow] ====Done====
7274 13:31:26.088075
7275 13:31:26.091237 [DutyScan_Calibration_Flow] k_type=2
7276 13:31:26.108825
7277 13:31:26.108936 ==DQ 0 ==
7278 13:31:26.112058 Final DQ duty delay cell = 0
7279 13:31:26.115394 [0] MAX Duty = 5124%(X100), DQS PI = 34
7280 13:31:26.118290 [0] MIN Duty = 5000%(X100), DQS PI = 16
7281 13:31:26.118438 [0] AVG Duty = 5062%(X100)
7282 13:31:26.118577
7283 13:31:26.122015 ==DQ 1 ==
7284 13:31:26.125164 Final DQ duty delay cell = 0
7285 13:31:26.128465 [0] MAX Duty = 4969%(X100), DQS PI = 42
7286 13:31:26.131720 [0] MIN Duty = 4875%(X100), DQS PI = 10
7287 13:31:26.131829 [0] AVG Duty = 4922%(X100)
7288 13:31:26.131922
7289 13:31:26.135123 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7290 13:31:26.138453
7291 13:31:26.138556 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7292 13:31:26.145183 [DutyScan_Calibration_Flow] ====Done====
7293 13:31:26.145316 ==
7294 13:31:26.148605 Dram Type= 6, Freq= 0, CH_1, rank 0
7295 13:31:26.151909 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7296 13:31:26.152031 ==
7297 13:31:26.155134 [Duty_Offset_Calibration]
7298 13:31:26.155245 B0:0 B1:-1 CA:2
7299 13:31:26.155337
7300 13:31:26.158250 [DutyScan_Calibration_Flow] k_type=0
7301 13:31:26.168643
7302 13:31:26.168757 ==CLK 0==
7303 13:31:26.171957 Final CLK duty delay cell = 0
7304 13:31:26.175212 [0] MAX Duty = 5156%(X100), DQS PI = 10
7305 13:31:26.178624 [0] MIN Duty = 4938%(X100), DQS PI = 44
7306 13:31:26.178745 [0] AVG Duty = 5047%(X100)
7307 13:31:26.182141
7308 13:31:26.185099 CH1 CLK Duty spec in!! Max-Min= 218%
7309 13:31:26.188412 [DutyScan_Calibration_Flow] ====Done====
7310 13:31:26.188522
7311 13:31:26.191768 [DutyScan_Calibration_Flow] k_type=1
7312 13:31:26.208274
7313 13:31:26.208375 ==DQS 0 ==
7314 13:31:26.211778 Final DQS duty delay cell = 0
7315 13:31:26.214974 [0] MAX Duty = 5124%(X100), DQS PI = 26
7316 13:31:26.218451 [0] MIN Duty = 4969%(X100), DQS PI = 2
7317 13:31:26.221786 [0] AVG Duty = 5046%(X100)
7318 13:31:26.221891
7319 13:31:26.221984 ==DQS 1 ==
7320 13:31:26.224681 Final DQS duty delay cell = 0
7321 13:31:26.228260 [0] MAX Duty = 5187%(X100), DQS PI = 0
7322 13:31:26.231337 [0] MIN Duty = 4844%(X100), DQS PI = 34
7323 13:31:26.235086 [0] AVG Duty = 5015%(X100)
7324 13:31:26.235189
7325 13:31:26.237912 CH1 DQS 0 Duty spec in!! Max-Min= 155%
7326 13:31:26.238013
7327 13:31:26.241852 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7328 13:31:26.245110 [DutyScan_Calibration_Flow] ====Done====
7329 13:31:26.245197
7330 13:31:26.247866 [DutyScan_Calibration_Flow] k_type=3
7331 13:31:26.266315
7332 13:31:26.266423 ==DQM 0 ==
7333 13:31:26.269167 Final DQM duty delay cell = 4
7334 13:31:26.272638 [4] MAX Duty = 5125%(X100), DQS PI = 8
7335 13:31:26.275593 [4] MIN Duty = 5000%(X100), DQS PI = 30
7336 13:31:26.279016 [4] AVG Duty = 5062%(X100)
7337 13:31:26.279136
7338 13:31:26.279228 ==DQM 1 ==
7339 13:31:26.282431 Final DQM duty delay cell = 0
7340 13:31:26.285965 [0] MAX Duty = 5281%(X100), DQS PI = 58
7341 13:31:26.289137 [0] MIN Duty = 4876%(X100), DQS PI = 34
7342 13:31:26.292668 [0] AVG Duty = 5078%(X100)
7343 13:31:26.292806
7344 13:31:26.296015 CH1 DQM 0 Duty spec in!! Max-Min= 125%
7345 13:31:26.296116
7346 13:31:26.299248 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7347 13:31:26.302189 [DutyScan_Calibration_Flow] ====Done====
7348 13:31:26.302306
7349 13:31:26.305593 [DutyScan_Calibration_Flow] k_type=2
7350 13:31:26.322742
7351 13:31:26.322855 ==DQ 0 ==
7352 13:31:26.326446 Final DQ duty delay cell = 0
7353 13:31:26.329711 [0] MAX Duty = 5093%(X100), DQS PI = 22
7354 13:31:26.332592 [0] MIN Duty = 4969%(X100), DQS PI = 2
7355 13:31:26.332699 [0] AVG Duty = 5031%(X100)
7356 13:31:26.332823
7357 13:31:26.335980 ==DQ 1 ==
7358 13:31:26.339399 Final DQ duty delay cell = 0
7359 13:31:26.342803 [0] MAX Duty = 5062%(X100), DQS PI = 0
7360 13:31:26.346055 [0] MIN Duty = 4813%(X100), DQS PI = 34
7361 13:31:26.346230 [0] AVG Duty = 4937%(X100)
7362 13:31:26.346371
7363 13:31:26.349585 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7364 13:31:26.349740
7365 13:31:26.353158 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7366 13:31:26.359763 [DutyScan_Calibration_Flow] ====Done====
7367 13:31:26.362884 nWR fixed to 30
7368 13:31:26.362981 [ModeRegInit_LP4] CH0 RK0
7369 13:31:26.366281 [ModeRegInit_LP4] CH0 RK1
7370 13:31:26.369243 [ModeRegInit_LP4] CH1 RK0
7371 13:31:26.369340 [ModeRegInit_LP4] CH1 RK1
7372 13:31:26.372615 match AC timing 5
7373 13:31:26.376257 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7374 13:31:26.379726 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7375 13:31:26.385861 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7376 13:31:26.389321 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7377 13:31:26.395709 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7378 13:31:26.395794 [MiockJmeterHQA]
7379 13:31:26.395860
7380 13:31:26.399266 [DramcMiockJmeter] u1RxGatingPI = 0
7381 13:31:26.402515 0 : 4252, 4027
7382 13:31:26.402602 4 : 4252, 4027
7383 13:31:26.402670 8 : 4252, 4027
7384 13:31:26.405909 12 : 4363, 4138
7385 13:31:26.406024 16 : 4253, 4027
7386 13:31:26.409362 20 : 4252, 4027
7387 13:31:26.409449 24 : 4252, 4027
7388 13:31:26.412928 28 : 4252, 4027
7389 13:31:26.413014 32 : 4363, 4138
7390 13:31:26.415925 36 : 4253, 4027
7391 13:31:26.416012 40 : 4252, 4026
7392 13:31:26.416080 44 : 4253, 4026
7393 13:31:26.419414 48 : 4255, 4029
7394 13:31:26.419500 52 : 4252, 4029
7395 13:31:26.422434 56 : 4363, 4138
7396 13:31:26.422525 60 : 4363, 4137
7397 13:31:26.425936 64 : 4250, 4027
7398 13:31:26.426023 68 : 4250, 4027
7399 13:31:26.426090 72 : 4249, 4027
7400 13:31:26.429188 76 : 4250, 4027
7401 13:31:26.429308 80 : 4252, 4029
7402 13:31:26.432429 84 : 4253, 4029
7403 13:31:26.432544 88 : 4250, 3659
7404 13:31:26.435776 92 : 4250, 0
7405 13:31:26.435884 96 : 4252, 0
7406 13:31:26.435979 100 : 4250, 0
7407 13:31:26.439253 104 : 4250, 0
7408 13:31:26.439353 108 : 4249, 0
7409 13:31:26.439445 112 : 4250, 0
7410 13:31:26.442686 116 : 4250, 0
7411 13:31:26.442800 120 : 4250, 0
7412 13:31:26.445816 124 : 4252, 0
7413 13:31:26.445927 128 : 4250, 0
7414 13:31:26.446034 132 : 4250, 0
7415 13:31:26.449427 136 : 4252, 0
7416 13:31:26.449543 140 : 4361, 0
7417 13:31:26.452697 144 : 4250, 0
7418 13:31:26.452819 148 : 4361, 0
7419 13:31:26.452919 152 : 4250, 0
7420 13:31:26.455681 156 : 4250, 0
7421 13:31:26.455795 160 : 4250, 0
7422 13:31:26.459198 164 : 4250, 0
7423 13:31:26.459304 168 : 4250, 0
7424 13:31:26.459400 172 : 4250, 0
7425 13:31:26.462773 176 : 4252, 0
7426 13:31:26.462886 180 : 4250, 0
7427 13:31:26.465721 184 : 4250, 0
7428 13:31:26.465826 188 : 4255, 0
7429 13:31:26.465922 192 : 4361, 0
7430 13:31:26.469083 196 : 4250, 0
7431 13:31:26.469174 200 : 4361, 2
7432 13:31:26.472384 204 : 4249, 2290
7433 13:31:26.472491 208 : 4361, 4137
7434 13:31:26.472591 212 : 4253, 4029
7435 13:31:26.475809 216 : 4249, 4027
7436 13:31:26.475925 220 : 4361, 4137
7437 13:31:26.479059 224 : 4250, 4027
7438 13:31:26.479168 228 : 4252, 4030
7439 13:31:26.482433 232 : 4363, 4139
7440 13:31:26.482549 236 : 4360, 4138
7441 13:31:26.486057 240 : 4252, 4029
7442 13:31:26.486144 244 : 4361, 4137
7443 13:31:26.489468 248 : 4252, 4029
7444 13:31:26.489553 252 : 4250, 4026
7445 13:31:26.492377 256 : 4255, 4029
7446 13:31:26.492463 260 : 4362, 4140
7447 13:31:26.495546 264 : 4252, 4029
7448 13:31:26.495636 268 : 4250, 4026
7449 13:31:26.495704 272 : 4255, 4029
7450 13:31:26.498874 276 : 4250, 4027
7451 13:31:26.498963 280 : 4250, 4027
7452 13:31:26.502172 284 : 4363, 4139
7453 13:31:26.502260 288 : 4360, 4137
7454 13:31:26.505764 292 : 4250, 4026
7455 13:31:26.505850 296 : 4361, 4138
7456 13:31:26.508771 300 : 4253, 4029
7457 13:31:26.508858 304 : 4250, 4027
7458 13:31:26.512165 308 : 4253, 4029
7459 13:31:26.512253 312 : 4362, 4131
7460 13:31:26.515373 316 : 4249, 2191
7461 13:31:26.515460 320 : 4250, 10
7462 13:31:26.515529
7463 13:31:26.518666 MIOCK jitter meter ch=0
7464 13:31:26.518753
7465 13:31:26.522116 1T = (320-92) = 228 dly cells
7466 13:31:26.525466 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7467 13:31:26.525555 ==
7468 13:31:26.528908 Dram Type= 6, Freq= 0, CH_0, rank 0
7469 13:31:26.535281 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7470 13:31:26.535370 ==
7471 13:31:26.538947 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7472 13:31:26.545253 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7473 13:31:26.548958 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7474 13:31:26.555108 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7475 13:31:26.563058 [CA 0] Center 42 (13~72) winsize 60
7476 13:31:26.566023 [CA 1] Center 42 (12~72) winsize 61
7477 13:31:26.569570 [CA 2] Center 37 (8~67) winsize 60
7478 13:31:26.572998 [CA 3] Center 37 (7~67) winsize 61
7479 13:31:26.575970 [CA 4] Center 36 (6~66) winsize 61
7480 13:31:26.579415 [CA 5] Center 35 (5~65) winsize 61
7481 13:31:26.579502
7482 13:31:26.582639 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7483 13:31:26.582723
7484 13:31:26.585986 [CATrainingPosCal] consider 1 rank data
7485 13:31:26.589418 u2DelayCellTimex100 = 285/100 ps
7486 13:31:26.592543 CA0 delay=42 (13~72),Diff = 7 PI (23 cell)
7487 13:31:26.599569 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7488 13:31:26.602448 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7489 13:31:26.606064 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7490 13:31:26.609533 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7491 13:31:26.612503 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7492 13:31:26.612625
7493 13:31:26.615946 CA PerBit enable=1, Macro0, CA PI delay=35
7494 13:31:26.616023
7495 13:31:26.619202 [CBTSetCACLKResult] CA Dly = 35
7496 13:31:26.622358 CS Dly: 9 (0~40)
7497 13:31:26.625705 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7498 13:31:26.629378 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7499 13:31:26.629481 ==
7500 13:31:26.632212 Dram Type= 6, Freq= 0, CH_0, rank 1
7501 13:31:26.635594 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7502 13:31:26.638881 ==
7503 13:31:26.642261 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7504 13:31:26.645805 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7505 13:31:26.652478 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7506 13:31:26.658805 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7507 13:31:26.666074 [CA 0] Center 43 (13~73) winsize 61
7508 13:31:26.669530 [CA 1] Center 43 (13~73) winsize 61
7509 13:31:26.672717 [CA 2] Center 38 (8~68) winsize 61
7510 13:31:26.676335 [CA 3] Center 38 (8~68) winsize 61
7511 13:31:26.679199 [CA 4] Center 36 (6~66) winsize 61
7512 13:31:26.682762 [CA 5] Center 36 (6~66) winsize 61
7513 13:31:26.682847
7514 13:31:26.686014 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7515 13:31:26.686098
7516 13:31:26.689349 [CATrainingPosCal] consider 2 rank data
7517 13:31:26.692853 u2DelayCellTimex100 = 285/100 ps
7518 13:31:26.696126 CA0 delay=42 (13~72),Diff = 7 PI (23 cell)
7519 13:31:26.703017 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7520 13:31:26.706198 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7521 13:31:26.709585 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7522 13:31:26.712427 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7523 13:31:26.716274 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7524 13:31:26.716377
7525 13:31:26.719110 CA PerBit enable=1, Macro0, CA PI delay=35
7526 13:31:26.719213
7527 13:31:26.722253 [CBTSetCACLKResult] CA Dly = 35
7528 13:31:26.725760 CS Dly: 10 (0~43)
7529 13:31:26.729320 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7530 13:31:26.732876 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7531 13:31:26.732954
7532 13:31:26.735711 ----->DramcWriteLeveling(PI) begin...
7533 13:31:26.735815 ==
7534 13:31:26.739099 Dram Type= 6, Freq= 0, CH_0, rank 0
7535 13:31:26.742409 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7536 13:31:26.745856 ==
7537 13:31:26.745971 Write leveling (Byte 0): 36 => 36
7538 13:31:26.749307 Write leveling (Byte 1): 31 => 31
7539 13:31:26.752702 DramcWriteLeveling(PI) end<-----
7540 13:31:26.752799
7541 13:31:26.752865 ==
7542 13:31:26.755922 Dram Type= 6, Freq= 0, CH_0, rank 0
7543 13:31:26.762676 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7544 13:31:26.762767 ==
7545 13:31:26.762834 [Gating] SW mode calibration
7546 13:31:26.772895 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7547 13:31:26.775746 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7548 13:31:26.782673 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7549 13:31:26.785655 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7550 13:31:26.788877 1 4 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
7551 13:31:26.795512 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7552 13:31:26.798849 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7553 13:31:26.802290 1 4 20 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
7554 13:31:26.808864 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7555 13:31:26.812197 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7556 13:31:26.815493 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7557 13:31:26.818794 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7558 13:31:26.825298 1 5 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
7559 13:31:26.828489 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
7560 13:31:26.831896 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7561 13:31:26.838646 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
7562 13:31:26.841979 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7563 13:31:26.845289 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7564 13:31:26.852269 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7565 13:31:26.855263 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7566 13:31:26.858650 1 6 8 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
7567 13:31:26.865062 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7568 13:31:26.868535 1 6 16 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
7569 13:31:26.871925 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7570 13:31:26.878723 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7571 13:31:26.882200 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7572 13:31:26.885279 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7573 13:31:26.892027 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7574 13:31:26.895258 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7575 13:31:26.898516 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7576 13:31:26.905273 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7577 13:31:26.908404 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7578 13:31:26.911703 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 13:31:26.918759 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 13:31:26.921816 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 13:31:26.925181 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 13:31:26.931842 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 13:31:26.935023 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 13:31:26.938285 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 13:31:26.944822 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 13:31:26.948487 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 13:31:26.952035 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 13:31:26.954814 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 13:31:26.961657 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 13:31:26.965090 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7591 13:31:26.968521 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7592 13:31:26.975247 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7593 13:31:26.978309 Total UI for P1: 0, mck2ui 16
7594 13:31:26.981519 best dqsien dly found for B0: ( 1, 9, 10)
7595 13:31:26.984994 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7596 13:31:26.988546 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7597 13:31:26.994926 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7598 13:31:26.998005 Total UI for P1: 0, mck2ui 16
7599 13:31:27.001375 best dqsien dly found for B1: ( 1, 9, 22)
7600 13:31:27.004379 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7601 13:31:27.008294 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7602 13:31:27.008379
7603 13:31:27.011221 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7604 13:31:27.014566 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7605 13:31:27.018246 [Gating] SW calibration Done
7606 13:31:27.018331 ==
7607 13:31:27.021511 Dram Type= 6, Freq= 0, CH_0, rank 0
7608 13:31:27.024877 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7609 13:31:27.024976 ==
7610 13:31:27.027728 RX Vref Scan: 0
7611 13:31:27.027811
7612 13:31:27.031266 RX Vref 0 -> 0, step: 1
7613 13:31:27.031398
7614 13:31:27.031506 RX Delay 0 -> 252, step: 8
7615 13:31:27.037752 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7616 13:31:27.040985 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7617 13:31:27.044842 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7618 13:31:27.047731 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7619 13:31:27.051129 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7620 13:31:27.054512 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7621 13:31:27.060881 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7622 13:31:27.064682 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7623 13:31:27.067981 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7624 13:31:27.071172 iDelay=200, Bit 9, Center 111 (64 ~ 159) 96
7625 13:31:27.074642 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7626 13:31:27.081308 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7627 13:31:27.084632 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7628 13:31:27.087628 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7629 13:31:27.091343 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7630 13:31:27.094428 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7631 13:31:27.097892 ==
7632 13:31:27.101244 Dram Type= 6, Freq= 0, CH_0, rank 0
7633 13:31:27.104468 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7634 13:31:27.104605 ==
7635 13:31:27.104717 DQS Delay:
7636 13:31:27.107935 DQS0 = 0, DQS1 = 0
7637 13:31:27.108052 DQM Delay:
7638 13:31:27.111287 DQM0 = 138, DQM1 = 125
7639 13:31:27.111409 DQ Delay:
7640 13:31:27.114218 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7641 13:31:27.117653 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7642 13:31:27.120978 DQ8 =119, DQ9 =111, DQ10 =123, DQ11 =119
7643 13:31:27.124305 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7644 13:31:27.124418
7645 13:31:27.124527
7646 13:31:27.124631 ==
7647 13:31:27.127667 Dram Type= 6, Freq= 0, CH_0, rank 0
7648 13:31:27.133898 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7649 13:31:27.134014 ==
7650 13:31:27.134122
7651 13:31:27.134230
7652 13:31:27.134333 TX Vref Scan disable
7653 13:31:27.137852 == TX Byte 0 ==
7654 13:31:27.140898 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7655 13:31:27.147681 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7656 13:31:27.147808 == TX Byte 1 ==
7657 13:31:27.150916 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7658 13:31:27.157671 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7659 13:31:27.157823 ==
7660 13:31:27.160885 Dram Type= 6, Freq= 0, CH_0, rank 0
7661 13:31:27.163939 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7662 13:31:27.164071 ==
7663 13:31:27.176871
7664 13:31:27.180170 TX Vref early break, caculate TX vref
7665 13:31:27.183411 TX Vref=16, minBit 7, minWin=22, winSum=377
7666 13:31:27.186813 TX Vref=18, minBit 6, minWin=23, winSum=386
7667 13:31:27.190340 TX Vref=20, minBit 12, minWin=23, winSum=397
7668 13:31:27.193666 TX Vref=22, minBit 7, minWin=24, winSum=409
7669 13:31:27.196801 TX Vref=24, minBit 5, minWin=25, winSum=414
7670 13:31:27.203561 TX Vref=26, minBit 12, minWin=25, winSum=423
7671 13:31:27.206905 TX Vref=28, minBit 2, minWin=26, winSum=431
7672 13:31:27.210166 TX Vref=30, minBit 0, minWin=25, winSum=420
7673 13:31:27.213565 TX Vref=32, minBit 0, minWin=25, winSum=412
7674 13:31:27.216567 TX Vref=34, minBit 11, minWin=24, winSum=405
7675 13:31:27.223265 [TxChooseVref] Worse bit 2, Min win 26, Win sum 431, Final Vref 28
7676 13:31:27.223393
7677 13:31:27.226429 Final TX Range 0 Vref 28
7678 13:31:27.226536
7679 13:31:27.226631 ==
7680 13:31:27.229783 Dram Type= 6, Freq= 0, CH_0, rank 0
7681 13:31:27.233242 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7682 13:31:27.233342 ==
7683 13:31:27.233432
7684 13:31:27.233521
7685 13:31:27.236644 TX Vref Scan disable
7686 13:31:27.242966 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7687 13:31:27.243054 == TX Byte 0 ==
7688 13:31:27.246212 u2DelayCellOfst[0]=13 cells (4 PI)
7689 13:31:27.249632 u2DelayCellOfst[1]=17 cells (5 PI)
7690 13:31:27.252814 u2DelayCellOfst[2]=10 cells (3 PI)
7691 13:31:27.256085 u2DelayCellOfst[3]=13 cells (4 PI)
7692 13:31:27.259648 u2DelayCellOfst[4]=10 cells (3 PI)
7693 13:31:27.262757 u2DelayCellOfst[5]=0 cells (0 PI)
7694 13:31:27.266591 u2DelayCellOfst[6]=17 cells (5 PI)
7695 13:31:27.269347 u2DelayCellOfst[7]=13 cells (4 PI)
7696 13:31:27.272528 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7697 13:31:27.275922 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7698 13:31:27.279208 == TX Byte 1 ==
7699 13:31:27.282619 u2DelayCellOfst[8]=0 cells (0 PI)
7700 13:31:27.285795 u2DelayCellOfst[9]=0 cells (0 PI)
7701 13:31:27.289200 u2DelayCellOfst[10]=6 cells (2 PI)
7702 13:31:27.289308 u2DelayCellOfst[11]=3 cells (1 PI)
7703 13:31:27.292522 u2DelayCellOfst[12]=13 cells (4 PI)
7704 13:31:27.296007 u2DelayCellOfst[13]=10 cells (3 PI)
7705 13:31:27.299123 u2DelayCellOfst[14]=13 cells (4 PI)
7706 13:31:27.302465 u2DelayCellOfst[15]=10 cells (3 PI)
7707 13:31:27.309231 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7708 13:31:27.312174 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7709 13:31:27.312299 DramC Write-DBI on
7710 13:31:27.315664 ==
7711 13:31:27.315781 Dram Type= 6, Freq= 0, CH_0, rank 0
7712 13:31:27.322451 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7713 13:31:27.322566 ==
7714 13:31:27.322664
7715 13:31:27.322757
7716 13:31:27.325834 TX Vref Scan disable
7717 13:31:27.325945 == TX Byte 0 ==
7718 13:31:27.332386 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7719 13:31:27.332509 == TX Byte 1 ==
7720 13:31:27.335298 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7721 13:31:27.338754 DramC Write-DBI off
7722 13:31:27.338868
7723 13:31:27.338966 [DATLAT]
7724 13:31:27.342135 Freq=1600, CH0 RK0
7725 13:31:27.342248
7726 13:31:27.342349 DATLAT Default: 0xf
7727 13:31:27.345570 0, 0xFFFF, sum = 0
7728 13:31:27.345685 1, 0xFFFF, sum = 0
7729 13:31:27.348976 2, 0xFFFF, sum = 0
7730 13:31:27.349105 3, 0xFFFF, sum = 0
7731 13:31:27.352488 4, 0xFFFF, sum = 0
7732 13:31:27.352605 5, 0xFFFF, sum = 0
7733 13:31:27.355621 6, 0xFFFF, sum = 0
7734 13:31:27.355743 7, 0xFFFF, sum = 0
7735 13:31:27.358948 8, 0xFFFF, sum = 0
7736 13:31:27.359068 9, 0xFFFF, sum = 0
7737 13:31:27.362343 10, 0xFFFF, sum = 0
7738 13:31:27.365592 11, 0xFFFF, sum = 0
7739 13:31:27.365721 12, 0xFFFF, sum = 0
7740 13:31:27.368836 13, 0xFFFF, sum = 0
7741 13:31:27.368968 14, 0x0, sum = 1
7742 13:31:27.372639 15, 0x0, sum = 2
7743 13:31:27.372770 16, 0x0, sum = 3
7744 13:31:27.372887 17, 0x0, sum = 4
7745 13:31:27.375803 best_step = 15
7746 13:31:27.375924
7747 13:31:27.376040 ==
7748 13:31:27.378852 Dram Type= 6, Freq= 0, CH_0, rank 0
7749 13:31:27.382231 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7750 13:31:27.382358 ==
7751 13:31:27.385419 RX Vref Scan: 1
7752 13:31:27.385541
7753 13:31:27.388966 Set Vref Range= 24 -> 127
7754 13:31:27.389092
7755 13:31:27.389208 RX Vref 24 -> 127, step: 1
7756 13:31:27.389322
7757 13:31:27.392284 RX Delay 19 -> 252, step: 4
7758 13:31:27.392408
7759 13:31:27.395218 Set Vref, RX VrefLevel [Byte0]: 24
7760 13:31:27.398582 [Byte1]: 24
7761 13:31:27.398690
7762 13:31:27.401943 Set Vref, RX VrefLevel [Byte0]: 25
7763 13:31:27.405450 [Byte1]: 25
7764 13:31:27.409361
7765 13:31:27.409449 Set Vref, RX VrefLevel [Byte0]: 26
7766 13:31:27.412723 [Byte1]: 26
7767 13:31:27.417033
7768 13:31:27.417147 Set Vref, RX VrefLevel [Byte0]: 27
7769 13:31:27.420631 [Byte1]: 27
7770 13:31:27.424664
7771 13:31:27.424758 Set Vref, RX VrefLevel [Byte0]: 28
7772 13:31:27.427833 [Byte1]: 28
7773 13:31:27.432060
7774 13:31:27.432177 Set Vref, RX VrefLevel [Byte0]: 29
7775 13:31:27.435373 [Byte1]: 29
7776 13:31:27.439779
7777 13:31:27.439866 Set Vref, RX VrefLevel [Byte0]: 30
7778 13:31:27.443355 [Byte1]: 30
7779 13:31:27.447271
7780 13:31:27.447360 Set Vref, RX VrefLevel [Byte0]: 31
7781 13:31:27.450532 [Byte1]: 31
7782 13:31:27.454814
7783 13:31:27.454902 Set Vref, RX VrefLevel [Byte0]: 32
7784 13:31:27.457976 [Byte1]: 32
7785 13:31:27.462734
7786 13:31:27.462822 Set Vref, RX VrefLevel [Byte0]: 33
7787 13:31:27.466000 [Byte1]: 33
7788 13:31:27.470093
7789 13:31:27.470180 Set Vref, RX VrefLevel [Byte0]: 34
7790 13:31:27.473434 [Byte1]: 34
7791 13:31:27.477736
7792 13:31:27.477836 Set Vref, RX VrefLevel [Byte0]: 35
7793 13:31:27.480863 [Byte1]: 35
7794 13:31:27.485135
7795 13:31:27.485235 Set Vref, RX VrefLevel [Byte0]: 36
7796 13:31:27.488746 [Byte1]: 36
7797 13:31:27.492667
7798 13:31:27.492772 Set Vref, RX VrefLevel [Byte0]: 37
7799 13:31:27.496394 [Byte1]: 37
7800 13:31:27.500320
7801 13:31:27.500406 Set Vref, RX VrefLevel [Byte0]: 38
7802 13:31:27.503603 [Byte1]: 38
7803 13:31:27.507696
7804 13:31:27.507806 Set Vref, RX VrefLevel [Byte0]: 39
7805 13:31:27.511137 [Byte1]: 39
7806 13:31:27.515502
7807 13:31:27.515612 Set Vref, RX VrefLevel [Byte0]: 40
7808 13:31:27.518760 [Byte1]: 40
7809 13:31:27.523223
7810 13:31:27.523324 Set Vref, RX VrefLevel [Byte0]: 41
7811 13:31:27.526031 [Byte1]: 41
7812 13:31:27.530541
7813 13:31:27.530665 Set Vref, RX VrefLevel [Byte0]: 42
7814 13:31:27.533856 [Byte1]: 42
7815 13:31:27.537926
7816 13:31:27.538051 Set Vref, RX VrefLevel [Byte0]: 43
7817 13:31:27.541429 [Byte1]: 43
7818 13:31:27.545801
7819 13:31:27.545922 Set Vref, RX VrefLevel [Byte0]: 44
7820 13:31:27.549306 [Byte1]: 44
7821 13:31:27.553102
7822 13:31:27.553220 Set Vref, RX VrefLevel [Byte0]: 45
7823 13:31:27.556427 [Byte1]: 45
7824 13:31:27.560645
7825 13:31:27.560748 Set Vref, RX VrefLevel [Byte0]: 46
7826 13:31:27.564094 [Byte1]: 46
7827 13:31:27.568486
7828 13:31:27.568595 Set Vref, RX VrefLevel [Byte0]: 47
7829 13:31:27.571899 [Byte1]: 47
7830 13:31:27.576334
7831 13:31:27.576417 Set Vref, RX VrefLevel [Byte0]: 48
7832 13:31:27.579243 [Byte1]: 48
7833 13:31:27.583803
7834 13:31:27.583886 Set Vref, RX VrefLevel [Byte0]: 49
7835 13:31:27.587180 [Byte1]: 49
7836 13:31:27.591356
7837 13:31:27.591439 Set Vref, RX VrefLevel [Byte0]: 50
7838 13:31:27.594471 [Byte1]: 50
7839 13:31:27.598776
7840 13:31:27.598859 Set Vref, RX VrefLevel [Byte0]: 51
7841 13:31:27.602388 [Byte1]: 51
7842 13:31:27.606330
7843 13:31:27.606413 Set Vref, RX VrefLevel [Byte0]: 52
7844 13:31:27.609535 [Byte1]: 52
7845 13:31:27.613965
7846 13:31:27.614048 Set Vref, RX VrefLevel [Byte0]: 53
7847 13:31:27.617302 [Byte1]: 53
7848 13:31:27.621560
7849 13:31:27.621660 Set Vref, RX VrefLevel [Byte0]: 54
7850 13:31:27.624919 [Byte1]: 54
7851 13:31:27.629357
7852 13:31:27.629446 Set Vref, RX VrefLevel [Byte0]: 55
7853 13:31:27.632338 [Byte1]: 55
7854 13:31:27.636766
7855 13:31:27.636854 Set Vref, RX VrefLevel [Byte0]: 56
7856 13:31:27.640065 [Byte1]: 56
7857 13:31:27.644291
7858 13:31:27.644422 Set Vref, RX VrefLevel [Byte0]: 57
7859 13:31:27.647707 [Byte1]: 57
7860 13:31:27.651627
7861 13:31:27.651754 Set Vref, RX VrefLevel [Byte0]: 58
7862 13:31:27.655069 [Byte1]: 58
7863 13:31:27.659041
7864 13:31:27.659146 Set Vref, RX VrefLevel [Byte0]: 59
7865 13:31:27.662847 [Byte1]: 59
7866 13:31:27.666771
7867 13:31:27.666898 Set Vref, RX VrefLevel [Byte0]: 60
7868 13:31:27.670462 [Byte1]: 60
7869 13:31:27.674779
7870 13:31:27.674895 Set Vref, RX VrefLevel [Byte0]: 61
7871 13:31:27.677530 [Byte1]: 61
7872 13:31:27.682157
7873 13:31:27.682274 Set Vref, RX VrefLevel [Byte0]: 62
7874 13:31:27.685555 [Byte1]: 62
7875 13:31:27.689922
7876 13:31:27.690061 Set Vref, RX VrefLevel [Byte0]: 63
7877 13:31:27.692719 [Byte1]: 63
7878 13:31:27.697387
7879 13:31:27.697515 Set Vref, RX VrefLevel [Byte0]: 64
7880 13:31:27.700624 [Byte1]: 64
7881 13:31:27.704970
7882 13:31:27.705088 Set Vref, RX VrefLevel [Byte0]: 65
7883 13:31:27.707937 [Byte1]: 65
7884 13:31:27.712230
7885 13:31:27.712354 Set Vref, RX VrefLevel [Byte0]: 66
7886 13:31:27.715505 [Byte1]: 66
7887 13:31:27.719796
7888 13:31:27.719879 Set Vref, RX VrefLevel [Byte0]: 67
7889 13:31:27.722990 [Byte1]: 67
7890 13:31:27.727341
7891 13:31:27.727445 Set Vref, RX VrefLevel [Byte0]: 68
7892 13:31:27.730887 [Byte1]: 68
7893 13:31:27.735327
7894 13:31:27.735437 Set Vref, RX VrefLevel [Byte0]: 69
7895 13:31:27.738305 [Byte1]: 69
7896 13:31:27.742593
7897 13:31:27.742698 Set Vref, RX VrefLevel [Byte0]: 70
7898 13:31:27.746123 [Byte1]: 70
7899 13:31:27.750011
7900 13:31:27.750120 Set Vref, RX VrefLevel [Byte0]: 71
7901 13:31:27.753390 [Byte1]: 71
7902 13:31:27.757694
7903 13:31:27.757836 Set Vref, RX VrefLevel [Byte0]: 72
7904 13:31:27.761113 [Byte1]: 72
7905 13:31:27.765232
7906 13:31:27.765355 Set Vref, RX VrefLevel [Byte0]: 73
7907 13:31:27.768724 [Byte1]: 73
7908 13:31:27.772871
7909 13:31:27.772994 Set Vref, RX VrefLevel [Byte0]: 74
7910 13:31:27.776296 [Byte1]: 74
7911 13:31:27.780337
7912 13:31:27.780464 Set Vref, RX VrefLevel [Byte0]: 75
7913 13:31:27.783574 [Byte1]: 75
7914 13:31:27.788387
7915 13:31:27.788508 Set Vref, RX VrefLevel [Byte0]: 76
7916 13:31:27.791709 [Byte1]: 76
7917 13:31:27.795570
7918 13:31:27.795693 Set Vref, RX VrefLevel [Byte0]: 77
7919 13:31:27.798924 [Byte1]: 77
7920 13:31:27.803134
7921 13:31:27.803258 Set Vref, RX VrefLevel [Byte0]: 78
7922 13:31:27.806350 [Byte1]: 78
7923 13:31:27.810859
7924 13:31:27.810944 Final RX Vref Byte 0 = 63 to rank0
7925 13:31:27.813994 Final RX Vref Byte 1 = 60 to rank0
7926 13:31:27.817518 Final RX Vref Byte 0 = 63 to rank1
7927 13:31:27.820595 Final RX Vref Byte 1 = 60 to rank1==
7928 13:31:27.824311 Dram Type= 6, Freq= 0, CH_0, rank 0
7929 13:31:27.830723 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7930 13:31:27.830813 ==
7931 13:31:27.830881 DQS Delay:
7932 13:31:27.830943 DQS0 = 0, DQS1 = 0
7933 13:31:27.834090 DQM Delay:
7934 13:31:27.834181 DQM0 = 136, DQM1 = 124
7935 13:31:27.837818 DQ Delay:
7936 13:31:27.840698 DQ0 =136, DQ1 =136, DQ2 =132, DQ3 =134
7937 13:31:27.844185 DQ4 =138, DQ5 =126, DQ6 =146, DQ7 =142
7938 13:31:27.847563 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =118
7939 13:31:27.850735 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =132
7940 13:31:27.850821
7941 13:31:27.850885
7942 13:31:27.850946
7943 13:31:27.854147 [DramC_TX_OE_Calibration] TA2
7944 13:31:27.857647 Original DQ_B0 (3 6) =30, OEN = 27
7945 13:31:27.861105 Original DQ_B1 (3 6) =30, OEN = 27
7946 13:31:27.861180 24, 0x0, End_B0=24 End_B1=24
7947 13:31:27.864367 25, 0x0, End_B0=25 End_B1=25
7948 13:31:27.867485 26, 0x0, End_B0=26 End_B1=26
7949 13:31:27.870873 27, 0x0, End_B0=27 End_B1=27
7950 13:31:27.874189 28, 0x0, End_B0=28 End_B1=28
7951 13:31:27.874271 29, 0x0, End_B0=29 End_B1=29
7952 13:31:27.877868 30, 0x0, End_B0=30 End_B1=30
7953 13:31:27.880902 31, 0x4141, End_B0=30 End_B1=30
7954 13:31:27.884518 Byte0 end_step=30 best_step=27
7955 13:31:27.887710 Byte1 end_step=30 best_step=27
7956 13:31:27.891273 Byte0 TX OE(2T, 0.5T) = (3, 3)
7957 13:31:27.891359 Byte1 TX OE(2T, 0.5T) = (3, 3)
7958 13:31:27.891424
7959 13:31:27.891483
7960 13:31:27.900990 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
7961 13:31:27.904302 CH0 RK0: MR19=303, MR18=1E1C
7962 13:31:27.910727 CH0_RK0: MR19=0x303, MR18=0x1E1C, DQSOSC=394, MR23=63, INC=23, DEC=15
7963 13:31:27.910820
7964 13:31:27.914034 ----->DramcWriteLeveling(PI) begin...
7965 13:31:27.914112 ==
7966 13:31:27.917900 Dram Type= 6, Freq= 0, CH_0, rank 1
7967 13:31:27.920599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7968 13:31:27.920686 ==
7969 13:31:27.923980 Write leveling (Byte 0): 38 => 38
7970 13:31:27.927438 Write leveling (Byte 1): 30 => 30
7971 13:31:27.930804 DramcWriteLeveling(PI) end<-----
7972 13:31:27.930890
7973 13:31:27.930957 ==
7974 13:31:27.933924 Dram Type= 6, Freq= 0, CH_0, rank 1
7975 13:31:27.937718 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7976 13:31:27.937855 ==
7977 13:31:27.940560 [Gating] SW mode calibration
7978 13:31:27.947386 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7979 13:31:27.954087 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7980 13:31:27.957481 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7981 13:31:27.960423 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7982 13:31:27.967417 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7983 13:31:27.970388 1 4 12 | B1->B0 | 2424 2d2d | 0 1 | (0 0) (1 1)
7984 13:31:27.973938 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7985 13:31:27.980730 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7986 13:31:27.983930 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7987 13:31:27.987403 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7988 13:31:27.993865 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7989 13:31:27.997079 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7990 13:31:28.000502 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7991 13:31:28.007109 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 0)
7992 13:31:28.010394 1 5 16 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
7993 13:31:28.013758 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7994 13:31:28.020462 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7995 13:31:28.023998 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7996 13:31:28.026974 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7997 13:31:28.030159 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7998 13:31:28.036912 1 6 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
7999 13:31:28.040451 1 6 12 | B1->B0 | 3131 4444 | 0 0 | (0 0) (0 0)
8000 13:31:28.043695 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8001 13:31:28.050084 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8002 13:31:28.053501 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8003 13:31:28.056979 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8004 13:31:28.063836 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8005 13:31:28.067200 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8006 13:31:28.070367 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8007 13:31:28.076980 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8008 13:31:28.080203 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8009 13:31:28.083560 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 13:31:28.090335 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 13:31:28.093793 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 13:31:28.096849 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 13:31:28.103753 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 13:31:28.106788 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 13:31:28.110114 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 13:31:28.117104 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 13:31:28.120141 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 13:31:28.123590 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 13:31:28.130120 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 13:31:28.133549 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 13:31:28.136777 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 13:31:28.143226 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 13:31:28.146739 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8024 13:31:28.149867 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8025 13:31:28.156394 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8026 13:31:28.156519 Total UI for P1: 0, mck2ui 16
8027 13:31:28.160017 best dqsien dly found for B0: ( 1, 9, 14)
8028 13:31:28.163317 Total UI for P1: 0, mck2ui 16
8029 13:31:28.166677 best dqsien dly found for B1: ( 1, 9, 14)
8030 13:31:28.170003 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8031 13:31:28.176683 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8032 13:31:28.176808
8033 13:31:28.180131 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8034 13:31:28.183416 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8035 13:31:28.186894 [Gating] SW calibration Done
8036 13:31:28.187015 ==
8037 13:31:28.190172 Dram Type= 6, Freq= 0, CH_0, rank 1
8038 13:31:28.193637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8039 13:31:28.193764 ==
8040 13:31:28.193897 RX Vref Scan: 0
8041 13:31:28.194011
8042 13:31:28.197148 RX Vref 0 -> 0, step: 1
8043 13:31:28.197271
8044 13:31:28.200433 RX Delay 0 -> 252, step: 8
8045 13:31:28.203505 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8046 13:31:28.206848 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8047 13:31:28.213295 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8048 13:31:28.216620 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8049 13:31:28.220118 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8050 13:31:28.223356 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8051 13:31:28.226875 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8052 13:31:28.233731 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8053 13:31:28.236650 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8054 13:31:28.239855 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8055 13:31:28.243265 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8056 13:31:28.246530 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8057 13:31:28.253306 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8058 13:31:28.256597 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8059 13:31:28.260015 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8060 13:31:28.263002 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8061 13:31:28.263085 ==
8062 13:31:28.266617 Dram Type= 6, Freq= 0, CH_0, rank 1
8063 13:31:28.273214 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8064 13:31:28.273297 ==
8065 13:31:28.273362 DQS Delay:
8066 13:31:28.273422 DQS0 = 0, DQS1 = 0
8067 13:31:28.276520 DQM Delay:
8068 13:31:28.276601 DQM0 = 136, DQM1 = 125
8069 13:31:28.279851 DQ Delay:
8070 13:31:28.283293 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8071 13:31:28.286278 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8072 13:31:28.289682 DQ8 =119, DQ9 =111, DQ10 =123, DQ11 =123
8073 13:31:28.293058 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8074 13:31:28.293172
8075 13:31:28.293252
8076 13:31:28.293358 ==
8077 13:31:28.296205 Dram Type= 6, Freq= 0, CH_0, rank 1
8078 13:31:28.299639 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8079 13:31:28.302979 ==
8080 13:31:28.303087
8081 13:31:28.303182
8082 13:31:28.303281 TX Vref Scan disable
8083 13:31:28.306126 == TX Byte 0 ==
8084 13:31:28.309407 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8085 13:31:28.312818 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8086 13:31:28.316416 == TX Byte 1 ==
8087 13:31:28.319440 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8088 13:31:28.322908 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8089 13:31:28.326404 ==
8090 13:31:28.326510 Dram Type= 6, Freq= 0, CH_0, rank 1
8091 13:31:28.332596 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8092 13:31:28.332674 ==
8093 13:31:28.346972
8094 13:31:28.350414 TX Vref early break, caculate TX vref
8095 13:31:28.353562 TX Vref=16, minBit 0, minWin=23, winSum=386
8096 13:31:28.356982 TX Vref=18, minBit 1, minWin=24, winSum=398
8097 13:31:28.360106 TX Vref=20, minBit 8, minWin=24, winSum=407
8098 13:31:28.363699 TX Vref=22, minBit 0, minWin=24, winSum=414
8099 13:31:28.366521 TX Vref=24, minBit 0, minWin=25, winSum=419
8100 13:31:28.373540 TX Vref=26, minBit 0, minWin=26, winSum=430
8101 13:31:28.376712 TX Vref=28, minBit 0, minWin=26, winSum=432
8102 13:31:28.379823 TX Vref=30, minBit 0, minWin=26, winSum=430
8103 13:31:28.383360 TX Vref=32, minBit 0, minWin=25, winSum=419
8104 13:31:28.386636 TX Vref=34, minBit 0, minWin=25, winSum=411
8105 13:31:28.390010 TX Vref=36, minBit 2, minWin=24, winSum=401
8106 13:31:28.396663 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 28
8107 13:31:28.396796
8108 13:31:28.400081 Final TX Range 0 Vref 28
8109 13:31:28.400158
8110 13:31:28.400222 ==
8111 13:31:28.403393 Dram Type= 6, Freq= 0, CH_0, rank 1
8112 13:31:28.406813 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8113 13:31:28.406926 ==
8114 13:31:28.407048
8115 13:31:28.407159
8116 13:31:28.409999 TX Vref Scan disable
8117 13:31:28.416606 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8118 13:31:28.416715 == TX Byte 0 ==
8119 13:31:28.420008 u2DelayCellOfst[0]=17 cells (5 PI)
8120 13:31:28.423526 u2DelayCellOfst[1]=20 cells (6 PI)
8121 13:31:28.426483 u2DelayCellOfst[2]=13 cells (4 PI)
8122 13:31:28.429974 u2DelayCellOfst[3]=13 cells (4 PI)
8123 13:31:28.433114 u2DelayCellOfst[4]=10 cells (3 PI)
8124 13:31:28.436499 u2DelayCellOfst[5]=0 cells (0 PI)
8125 13:31:28.439954 u2DelayCellOfst[6]=20 cells (6 PI)
8126 13:31:28.443126 u2DelayCellOfst[7]=20 cells (6 PI)
8127 13:31:28.446177 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8128 13:31:28.449824 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8129 13:31:28.453207 == TX Byte 1 ==
8130 13:31:28.456722 u2DelayCellOfst[8]=3 cells (1 PI)
8131 13:31:28.459635 u2DelayCellOfst[9]=0 cells (0 PI)
8132 13:31:28.463023 u2DelayCellOfst[10]=6 cells (2 PI)
8133 13:31:28.463107 u2DelayCellOfst[11]=6 cells (2 PI)
8134 13:31:28.466492 u2DelayCellOfst[12]=13 cells (4 PI)
8135 13:31:28.469617 u2DelayCellOfst[13]=13 cells (4 PI)
8136 13:31:28.472922 u2DelayCellOfst[14]=13 cells (4 PI)
8137 13:31:28.476610 u2DelayCellOfst[15]=10 cells (3 PI)
8138 13:31:28.482953 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8139 13:31:28.486299 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8140 13:31:28.486383 DramC Write-DBI on
8141 13:31:28.486450 ==
8142 13:31:28.489413 Dram Type= 6, Freq= 0, CH_0, rank 1
8143 13:31:28.496505 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8144 13:31:28.496589 ==
8145 13:31:28.496656
8146 13:31:28.496716
8147 13:31:28.496784 TX Vref Scan disable
8148 13:31:28.500190 == TX Byte 0 ==
8149 13:31:28.503994 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8150 13:31:28.507199 == TX Byte 1 ==
8151 13:31:28.510596 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8152 13:31:28.510680 DramC Write-DBI off
8153 13:31:28.513850
8154 13:31:28.513934 [DATLAT]
8155 13:31:28.513999 Freq=1600, CH0 RK1
8156 13:31:28.514061
8157 13:31:28.517132 DATLAT Default: 0xf
8158 13:31:28.517215 0, 0xFFFF, sum = 0
8159 13:31:28.520176 1, 0xFFFF, sum = 0
8160 13:31:28.520261 2, 0xFFFF, sum = 0
8161 13:31:28.523477 3, 0xFFFF, sum = 0
8162 13:31:28.526930 4, 0xFFFF, sum = 0
8163 13:31:28.527022 5, 0xFFFF, sum = 0
8164 13:31:28.530271 6, 0xFFFF, sum = 0
8165 13:31:28.530386 7, 0xFFFF, sum = 0
8166 13:31:28.533722 8, 0xFFFF, sum = 0
8167 13:31:28.533807 9, 0xFFFF, sum = 0
8168 13:31:28.536979 10, 0xFFFF, sum = 0
8169 13:31:28.537091 11, 0xFFFF, sum = 0
8170 13:31:28.540341 12, 0xFFFF, sum = 0
8171 13:31:28.540455 13, 0xFFFF, sum = 0
8172 13:31:28.543327 14, 0x0, sum = 1
8173 13:31:28.543442 15, 0x0, sum = 2
8174 13:31:28.546794 16, 0x0, sum = 3
8175 13:31:28.546904 17, 0x0, sum = 4
8176 13:31:28.550081 best_step = 15
8177 13:31:28.550155
8178 13:31:28.550218 ==
8179 13:31:28.553553 Dram Type= 6, Freq= 0, CH_0, rank 1
8180 13:31:28.556722 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8181 13:31:28.556806 ==
8182 13:31:28.559766 RX Vref Scan: 0
8183 13:31:28.559850
8184 13:31:28.559916 RX Vref 0 -> 0, step: 1
8185 13:31:28.559977
8186 13:31:28.563458 RX Delay 11 -> 252, step: 4
8187 13:31:28.566641 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8188 13:31:28.573008 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8189 13:31:28.576637 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8190 13:31:28.579585 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8191 13:31:28.582860 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8192 13:31:28.589474 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8193 13:31:28.592961 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8194 13:31:28.596376 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8195 13:31:28.599863 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8196 13:31:28.602740 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8197 13:31:28.609434 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8198 13:31:28.612742 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8199 13:31:28.616112 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8200 13:31:28.619546 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8201 13:31:28.622817 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8202 13:31:28.629271 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8203 13:31:28.629384 ==
8204 13:31:28.632731 Dram Type= 6, Freq= 0, CH_0, rank 1
8205 13:31:28.636174 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8206 13:31:28.636287 ==
8207 13:31:28.636399 DQS Delay:
8208 13:31:28.639447 DQS0 = 0, DQS1 = 0
8209 13:31:28.639558 DQM Delay:
8210 13:31:28.642710 DQM0 = 133, DQM1 = 123
8211 13:31:28.642828 DQ Delay:
8212 13:31:28.646246 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =130
8213 13:31:28.649130 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8214 13:31:28.652990 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8215 13:31:28.656244 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8216 13:31:28.656326
8217 13:31:28.656390
8218 13:31:28.659279
8219 13:31:28.659360 [DramC_TX_OE_Calibration] TA2
8220 13:31:28.663062 Original DQ_B0 (3 6) =30, OEN = 27
8221 13:31:28.665994 Original DQ_B1 (3 6) =30, OEN = 27
8222 13:31:28.669326 24, 0x0, End_B0=24 End_B1=24
8223 13:31:28.672976 25, 0x0, End_B0=25 End_B1=25
8224 13:31:28.675924 26, 0x0, End_B0=26 End_B1=26
8225 13:31:28.676007 27, 0x0, End_B0=27 End_B1=27
8226 13:31:28.679343 28, 0x0, End_B0=28 End_B1=28
8227 13:31:28.682684 29, 0x0, End_B0=29 End_B1=29
8228 13:31:28.686172 30, 0x0, End_B0=30 End_B1=30
8229 13:31:28.686256 31, 0x4141, End_B0=30 End_B1=30
8230 13:31:28.689572 Byte0 end_step=30 best_step=27
8231 13:31:28.692505 Byte1 end_step=30 best_step=27
8232 13:31:28.695894 Byte0 TX OE(2T, 0.5T) = (3, 3)
8233 13:31:28.699409 Byte1 TX OE(2T, 0.5T) = (3, 3)
8234 13:31:28.699491
8235 13:31:28.699555
8236 13:31:28.705848 [DQSOSCAuto] RK1, (LSB)MR18= 0x210e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8237 13:31:28.709005 CH0 RK1: MR19=303, MR18=210E
8238 13:31:28.715853 CH0_RK1: MR19=0x303, MR18=0x210E, DQSOSC=393, MR23=63, INC=23, DEC=15
8239 13:31:28.719162 [RxdqsGatingPostProcess] freq 1600
8240 13:31:28.725901 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8241 13:31:28.729389 best DQS0 dly(2T, 0.5T) = (1, 1)
8242 13:31:28.729473 best DQS1 dly(2T, 0.5T) = (1, 1)
8243 13:31:28.732232 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8244 13:31:28.735673 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8245 13:31:28.739117 best DQS0 dly(2T, 0.5T) = (1, 1)
8246 13:31:28.742498 best DQS1 dly(2T, 0.5T) = (1, 1)
8247 13:31:28.745669 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8248 13:31:28.748993 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8249 13:31:28.752429 Pre-setting of DQS Precalculation
8250 13:31:28.755931 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8251 13:31:28.756015 ==
8252 13:31:28.759544 Dram Type= 6, Freq= 0, CH_1, rank 0
8253 13:31:28.765506 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8254 13:31:28.765589 ==
8255 13:31:28.768964 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8256 13:31:28.775799 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8257 13:31:28.778932 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8258 13:31:28.785424 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8259 13:31:28.793480 [CA 0] Center 42 (12~72) winsize 61
8260 13:31:28.796507 [CA 1] Center 42 (12~72) winsize 61
8261 13:31:28.800059 [CA 2] Center 38 (9~68) winsize 60
8262 13:31:28.803602 [CA 3] Center 37 (8~67) winsize 60
8263 13:31:28.806657 [CA 4] Center 37 (8~67) winsize 60
8264 13:31:28.809886 [CA 5] Center 37 (7~67) winsize 61
8265 13:31:28.809999
8266 13:31:28.813512 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8267 13:31:28.813625
8268 13:31:28.816496 [CATrainingPosCal] consider 1 rank data
8269 13:31:28.820223 u2DelayCellTimex100 = 285/100 ps
8270 13:31:28.823181 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8271 13:31:28.829871 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8272 13:31:28.833210 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8273 13:31:28.836721 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8274 13:31:28.840155 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8275 13:31:28.843096 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8276 13:31:28.843204
8277 13:31:28.846745 CA PerBit enable=1, Macro0, CA PI delay=37
8278 13:31:28.846829
8279 13:31:28.849891 [CBTSetCACLKResult] CA Dly = 37
8280 13:31:28.849975 CS Dly: 8 (0~39)
8281 13:31:28.857128 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8282 13:31:28.860224 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8283 13:31:28.860307 ==
8284 13:31:28.863094 Dram Type= 6, Freq= 0, CH_1, rank 1
8285 13:31:28.866469 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8286 13:31:28.866553 ==
8287 13:31:28.873229 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8288 13:31:28.876842 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8289 13:31:28.883135 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8290 13:31:28.886495 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8291 13:31:28.896745 [CA 0] Center 41 (12~71) winsize 60
8292 13:31:28.899602 [CA 1] Center 41 (12~71) winsize 60
8293 13:31:28.903232 [CA 2] Center 38 (9~67) winsize 59
8294 13:31:28.906775 [CA 3] Center 37 (8~67) winsize 60
8295 13:31:28.909740 [CA 4] Center 37 (8~67) winsize 60
8296 13:31:28.913005 [CA 5] Center 37 (7~67) winsize 61
8297 13:31:28.913094
8298 13:31:28.916389 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8299 13:31:28.916511
8300 13:31:28.919511 [CATrainingPosCal] consider 2 rank data
8301 13:31:28.923022 u2DelayCellTimex100 = 285/100 ps
8302 13:31:28.926441 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8303 13:31:28.933078 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8304 13:31:28.936368 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8305 13:31:28.939425 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8306 13:31:28.942757 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8307 13:31:28.946059 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8308 13:31:28.946172
8309 13:31:28.949484 CA PerBit enable=1, Macro0, CA PI delay=37
8310 13:31:28.949593
8311 13:31:28.952654 [CBTSetCACLKResult] CA Dly = 37
8312 13:31:28.955885 CS Dly: 9 (0~42)
8313 13:31:28.959435 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8314 13:31:28.962505 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8315 13:31:28.962587
8316 13:31:28.966383 ----->DramcWriteLeveling(PI) begin...
8317 13:31:28.966466 ==
8318 13:31:28.969371 Dram Type= 6, Freq= 0, CH_1, rank 0
8319 13:31:28.975927 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8320 13:31:28.976011 ==
8321 13:31:28.978965 Write leveling (Byte 0): 24 => 24
8322 13:31:28.979047 Write leveling (Byte 1): 26 => 26
8323 13:31:28.982335 DramcWriteLeveling(PI) end<-----
8324 13:31:28.982444
8325 13:31:28.985700 ==
8326 13:31:28.985800 Dram Type= 6, Freq= 0, CH_1, rank 0
8327 13:31:28.992395 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8328 13:31:28.992477 ==
8329 13:31:28.996086 [Gating] SW mode calibration
8330 13:31:29.002235 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8331 13:31:29.005920 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8332 13:31:29.012531 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 13:31:29.015847 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 13:31:29.018813 1 4 8 | B1->B0 | 2c2c 3333 | 1 0 | (0 0) (0 0)
8335 13:31:29.025379 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8336 13:31:29.028955 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8337 13:31:29.032465 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8338 13:31:29.039179 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8339 13:31:29.042632 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8340 13:31:29.045361 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8341 13:31:29.052100 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8342 13:31:29.055438 1 5 8 | B1->B0 | 2e2e 2626 | 0 0 | (1 0) (1 0)
8343 13:31:29.058653 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
8344 13:31:29.065427 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8345 13:31:29.068911 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 13:31:29.071937 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8347 13:31:29.075504 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8348 13:31:29.081885 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8349 13:31:29.085372 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8350 13:31:29.088632 1 6 8 | B1->B0 | 3838 4242 | 0 0 | (0 0) (0 0)
8351 13:31:29.095358 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8352 13:31:29.098687 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8353 13:31:29.101967 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8354 13:31:29.108685 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8355 13:31:29.111726 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8356 13:31:29.115073 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8357 13:31:29.121625 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8358 13:31:29.125220 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8359 13:31:29.128541 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8360 13:31:29.135430 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 13:31:29.138771 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 13:31:29.142006 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 13:31:29.148397 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 13:31:29.151832 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 13:31:29.155439 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 13:31:29.161580 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 13:31:29.165142 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 13:31:29.168556 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 13:31:29.175317 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 13:31:29.178402 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 13:31:29.181741 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 13:31:29.188449 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 13:31:29.191951 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 13:31:29.195298 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8375 13:31:29.201723 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8376 13:31:29.201830 Total UI for P1: 0, mck2ui 16
8377 13:31:29.205182 best dqsien dly found for B0: ( 1, 9, 8)
8378 13:31:29.211624 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 13:31:29.215217 Total UI for P1: 0, mck2ui 16
8380 13:31:29.218458 best dqsien dly found for B1: ( 1, 9, 10)
8381 13:31:29.221561 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8382 13:31:29.224985 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8383 13:31:29.225073
8384 13:31:29.228586 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8385 13:31:29.231812 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8386 13:31:29.234782 [Gating] SW calibration Done
8387 13:31:29.234894 ==
8388 13:31:29.238181 Dram Type= 6, Freq= 0, CH_1, rank 0
8389 13:31:29.241355 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8390 13:31:29.241487 ==
8391 13:31:29.245064 RX Vref Scan: 0
8392 13:31:29.245188
8393 13:31:29.245301 RX Vref 0 -> 0, step: 1
8394 13:31:29.248303
8395 13:31:29.248430 RX Delay 0 -> 252, step: 8
8396 13:31:29.251841 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8397 13:31:29.258047 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8398 13:31:29.261548 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8399 13:31:29.264951 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8400 13:31:29.268266 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8401 13:31:29.271568 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8402 13:31:29.278391 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8403 13:31:29.281584 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8404 13:31:29.284895 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8405 13:31:29.288387 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8406 13:31:29.291199 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8407 13:31:29.298102 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8408 13:31:29.301724 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8409 13:31:29.304452 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8410 13:31:29.307986 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8411 13:31:29.314757 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8412 13:31:29.314849 ==
8413 13:31:29.317641 Dram Type= 6, Freq= 0, CH_1, rank 0
8414 13:31:29.321420 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8415 13:31:29.321506 ==
8416 13:31:29.321574 DQS Delay:
8417 13:31:29.324939 DQS0 = 0, DQS1 = 0
8418 13:31:29.325023 DQM Delay:
8419 13:31:29.327933 DQM0 = 136, DQM1 = 130
8420 13:31:29.328017 DQ Delay:
8421 13:31:29.331447 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =139
8422 13:31:29.334446 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8423 13:31:29.338116 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8424 13:31:29.341161 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =139
8425 13:31:29.341286
8426 13:31:29.341401
8427 13:31:29.341512 ==
8428 13:31:29.344298 Dram Type= 6, Freq= 0, CH_1, rank 0
8429 13:31:29.351039 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8430 13:31:29.351165 ==
8431 13:31:29.351286
8432 13:31:29.351395
8433 13:31:29.351507 TX Vref Scan disable
8434 13:31:29.354868 == TX Byte 0 ==
8435 13:31:29.358356 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8436 13:31:29.365160 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8437 13:31:29.365284 == TX Byte 1 ==
8438 13:31:29.368136 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8439 13:31:29.374967 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8440 13:31:29.375091 ==
8441 13:31:29.378359 Dram Type= 6, Freq= 0, CH_1, rank 0
8442 13:31:29.381691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8443 13:31:29.381814 ==
8444 13:31:29.394785
8445 13:31:29.398182 TX Vref early break, caculate TX vref
8446 13:31:29.401650 TX Vref=16, minBit 10, minWin=22, winSum=375
8447 13:31:29.405015 TX Vref=18, minBit 10, minWin=22, winSum=386
8448 13:31:29.407950 TX Vref=20, minBit 2, minWin=24, winSum=398
8449 13:31:29.411392 TX Vref=22, minBit 10, minWin=24, winSum=406
8450 13:31:29.414836 TX Vref=24, minBit 0, minWin=25, winSum=412
8451 13:31:29.421787 TX Vref=26, minBit 10, minWin=25, winSum=424
8452 13:31:29.424589 TX Vref=28, minBit 15, minWin=25, winSum=425
8453 13:31:29.427776 TX Vref=30, minBit 10, minWin=25, winSum=423
8454 13:31:29.431096 TX Vref=32, minBit 0, minWin=25, winSum=412
8455 13:31:29.434614 TX Vref=34, minBit 10, minWin=24, winSum=404
8456 13:31:29.441738 TX Vref=36, minBit 6, minWin=24, winSum=397
8457 13:31:29.444634 [TxChooseVref] Worse bit 15, Min win 25, Win sum 425, Final Vref 28
8458 13:31:29.444763
8459 13:31:29.448118 Final TX Range 0 Vref 28
8460 13:31:29.448242
8461 13:31:29.448357 ==
8462 13:31:29.451024 Dram Type= 6, Freq= 0, CH_1, rank 0
8463 13:31:29.454491 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8464 13:31:29.457598 ==
8465 13:31:29.457719
8466 13:31:29.457832
8467 13:31:29.457944 TX Vref Scan disable
8468 13:31:29.464456 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8469 13:31:29.464581 == TX Byte 0 ==
8470 13:31:29.467842 u2DelayCellOfst[0]=13 cells (4 PI)
8471 13:31:29.471515 u2DelayCellOfst[1]=10 cells (3 PI)
8472 13:31:29.474527 u2DelayCellOfst[2]=0 cells (0 PI)
8473 13:31:29.477875 u2DelayCellOfst[3]=6 cells (2 PI)
8474 13:31:29.481286 u2DelayCellOfst[4]=6 cells (2 PI)
8475 13:31:29.484277 u2DelayCellOfst[5]=17 cells (5 PI)
8476 13:31:29.488007 u2DelayCellOfst[6]=17 cells (5 PI)
8477 13:31:29.491354 u2DelayCellOfst[7]=6 cells (2 PI)
8478 13:31:29.494852 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8479 13:31:29.497758 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8480 13:31:29.500973 == TX Byte 1 ==
8481 13:31:29.504556 u2DelayCellOfst[8]=0 cells (0 PI)
8482 13:31:29.507742 u2DelayCellOfst[9]=3 cells (1 PI)
8483 13:31:29.511175 u2DelayCellOfst[10]=10 cells (3 PI)
8484 13:31:29.514543 u2DelayCellOfst[11]=3 cells (1 PI)
8485 13:31:29.514626 u2DelayCellOfst[12]=13 cells (4 PI)
8486 13:31:29.517939 u2DelayCellOfst[13]=17 cells (5 PI)
8487 13:31:29.520713 u2DelayCellOfst[14]=17 cells (5 PI)
8488 13:31:29.524126 u2DelayCellOfst[15]=17 cells (5 PI)
8489 13:31:29.531103 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8490 13:31:29.534050 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8491 13:31:29.534149 DramC Write-DBI on
8492 13:31:29.537646 ==
8493 13:31:29.537730 Dram Type= 6, Freq= 0, CH_1, rank 0
8494 13:31:29.544016 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8495 13:31:29.544121 ==
8496 13:31:29.544216
8497 13:31:29.544291
8498 13:31:29.547398 TX Vref Scan disable
8499 13:31:29.547481 == TX Byte 0 ==
8500 13:31:29.554085 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8501 13:31:29.554168 == TX Byte 1 ==
8502 13:31:29.557187 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8503 13:31:29.560651 DramC Write-DBI off
8504 13:31:29.560734
8505 13:31:29.560825 [DATLAT]
8506 13:31:29.564323 Freq=1600, CH1 RK0
8507 13:31:29.564418
8508 13:31:29.564498 DATLAT Default: 0xf
8509 13:31:29.567423 0, 0xFFFF, sum = 0
8510 13:31:29.567506 1, 0xFFFF, sum = 0
8511 13:31:29.570701 2, 0xFFFF, sum = 0
8512 13:31:29.570783 3, 0xFFFF, sum = 0
8513 13:31:29.574112 4, 0xFFFF, sum = 0
8514 13:31:29.574196 5, 0xFFFF, sum = 0
8515 13:31:29.577411 6, 0xFFFF, sum = 0
8516 13:31:29.577493 7, 0xFFFF, sum = 0
8517 13:31:29.580714 8, 0xFFFF, sum = 0
8518 13:31:29.580820 9, 0xFFFF, sum = 0
8519 13:31:29.584073 10, 0xFFFF, sum = 0
8520 13:31:29.587599 11, 0xFFFF, sum = 0
8521 13:31:29.587682 12, 0xFFFF, sum = 0
8522 13:31:29.590943 13, 0xFFFF, sum = 0
8523 13:31:29.591026 14, 0x0, sum = 1
8524 13:31:29.594059 15, 0x0, sum = 2
8525 13:31:29.594142 16, 0x0, sum = 3
8526 13:31:29.594208 17, 0x0, sum = 4
8527 13:31:29.597404 best_step = 15
8528 13:31:29.597485
8529 13:31:29.597548 ==
8530 13:31:29.600478 Dram Type= 6, Freq= 0, CH_1, rank 0
8531 13:31:29.603859 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8532 13:31:29.603941 ==
8533 13:31:29.607526 RX Vref Scan: 1
8534 13:31:29.607608
8535 13:31:29.610553 Set Vref Range= 24 -> 127
8536 13:31:29.610635
8537 13:31:29.610699 RX Vref 24 -> 127, step: 1
8538 13:31:29.610759
8539 13:31:29.613890 RX Delay 19 -> 252, step: 4
8540 13:31:29.613972
8541 13:31:29.617318 Set Vref, RX VrefLevel [Byte0]: 24
8542 13:31:29.620572 [Byte1]: 24
8543 13:31:29.620654
8544 13:31:29.624004 Set Vref, RX VrefLevel [Byte0]: 25
8545 13:31:29.627451 [Byte1]: 25
8546 13:31:29.631349
8547 13:31:29.631430 Set Vref, RX VrefLevel [Byte0]: 26
8548 13:31:29.634601 [Byte1]: 26
8549 13:31:29.638948
8550 13:31:29.639032 Set Vref, RX VrefLevel [Byte0]: 27
8551 13:31:29.642210 [Byte1]: 27
8552 13:31:29.646758
8553 13:31:29.646841 Set Vref, RX VrefLevel [Byte0]: 28
8554 13:31:29.649658 [Byte1]: 28
8555 13:31:29.654034
8556 13:31:29.654117 Set Vref, RX VrefLevel [Byte0]: 29
8557 13:31:29.657357 [Byte1]: 29
8558 13:31:29.661745
8559 13:31:29.661859 Set Vref, RX VrefLevel [Byte0]: 30
8560 13:31:29.665136 [Byte1]: 30
8561 13:31:29.669227
8562 13:31:29.669309 Set Vref, RX VrefLevel [Byte0]: 31
8563 13:31:29.672243 [Byte1]: 31
8564 13:31:29.676392
8565 13:31:29.676476 Set Vref, RX VrefLevel [Byte0]: 32
8566 13:31:29.679787 [Byte1]: 32
8567 13:31:29.684068
8568 13:31:29.684145 Set Vref, RX VrefLevel [Byte0]: 33
8569 13:31:29.687417 [Byte1]: 33
8570 13:31:29.691717
8571 13:31:29.691796 Set Vref, RX VrefLevel [Byte0]: 34
8572 13:31:29.695167 [Byte1]: 34
8573 13:31:29.699278
8574 13:31:29.699354 Set Vref, RX VrefLevel [Byte0]: 35
8575 13:31:29.702838 [Byte1]: 35
8576 13:31:29.706736
8577 13:31:29.706821 Set Vref, RX VrefLevel [Byte0]: 36
8578 13:31:29.710056 [Byte1]: 36
8579 13:31:29.714338
8580 13:31:29.714416 Set Vref, RX VrefLevel [Byte0]: 37
8581 13:31:29.717701 [Byte1]: 37
8582 13:31:29.721878
8583 13:31:29.721963 Set Vref, RX VrefLevel [Byte0]: 38
8584 13:31:29.725508 [Byte1]: 38
8585 13:31:29.729845
8586 13:31:29.729928 Set Vref, RX VrefLevel [Byte0]: 39
8587 13:31:29.733302 [Byte1]: 39
8588 13:31:29.737486
8589 13:31:29.737569 Set Vref, RX VrefLevel [Byte0]: 40
8590 13:31:29.740296 [Byte1]: 40
8591 13:31:29.744588
8592 13:31:29.744671 Set Vref, RX VrefLevel [Byte0]: 41
8593 13:31:29.748039 [Byte1]: 41
8594 13:31:29.752469
8595 13:31:29.752593 Set Vref, RX VrefLevel [Byte0]: 42
8596 13:31:29.755791 [Byte1]: 42
8597 13:31:29.760071
8598 13:31:29.760152 Set Vref, RX VrefLevel [Byte0]: 43
8599 13:31:29.763314 [Byte1]: 43
8600 13:31:29.767824
8601 13:31:29.767922 Set Vref, RX VrefLevel [Byte0]: 44
8602 13:31:29.770939 [Byte1]: 44
8603 13:31:29.775200
8604 13:31:29.775320 Set Vref, RX VrefLevel [Byte0]: 45
8605 13:31:29.778413 [Byte1]: 45
8606 13:31:29.782814
8607 13:31:29.782917 Set Vref, RX VrefLevel [Byte0]: 46
8608 13:31:29.785973 [Byte1]: 46
8609 13:31:29.790348
8610 13:31:29.790422 Set Vref, RX VrefLevel [Byte0]: 47
8611 13:31:29.793426 [Byte1]: 47
8612 13:31:29.797873
8613 13:31:29.797955 Set Vref, RX VrefLevel [Byte0]: 48
8614 13:31:29.801209 [Byte1]: 48
8615 13:31:29.805666
8616 13:31:29.805747 Set Vref, RX VrefLevel [Byte0]: 49
8617 13:31:29.808495 [Byte1]: 49
8618 13:31:29.813235
8619 13:31:29.813344 Set Vref, RX VrefLevel [Byte0]: 50
8620 13:31:29.816058 [Byte1]: 50
8621 13:31:29.820445
8622 13:31:29.820542 Set Vref, RX VrefLevel [Byte0]: 51
8623 13:31:29.823815 [Byte1]: 51
8624 13:31:29.827927
8625 13:31:29.828009 Set Vref, RX VrefLevel [Byte0]: 52
8626 13:31:29.831642 [Byte1]: 52
8627 13:31:29.835790
8628 13:31:29.835877 Set Vref, RX VrefLevel [Byte0]: 53
8629 13:31:29.839000 [Byte1]: 53
8630 13:31:29.843074
8631 13:31:29.843157 Set Vref, RX VrefLevel [Byte0]: 54
8632 13:31:29.846780 [Byte1]: 54
8633 13:31:29.850671
8634 13:31:29.850754 Set Vref, RX VrefLevel [Byte0]: 55
8635 13:31:29.854117 [Byte1]: 55
8636 13:31:29.858400
8637 13:31:29.858486 Set Vref, RX VrefLevel [Byte0]: 56
8638 13:31:29.861737 [Byte1]: 56
8639 13:31:29.866214
8640 13:31:29.866297 Set Vref, RX VrefLevel [Byte0]: 57
8641 13:31:29.869063 [Byte1]: 57
8642 13:31:29.873510
8643 13:31:29.873593 Set Vref, RX VrefLevel [Byte0]: 58
8644 13:31:29.876755 [Byte1]: 58
8645 13:31:29.881232
8646 13:31:29.881406 Set Vref, RX VrefLevel [Byte0]: 59
8647 13:31:29.884331 [Byte1]: 59
8648 13:31:29.888650
8649 13:31:29.888735 Set Vref, RX VrefLevel [Byte0]: 60
8650 13:31:29.892075 [Byte1]: 60
8651 13:31:29.896215
8652 13:31:29.896300 Set Vref, RX VrefLevel [Byte0]: 61
8653 13:31:29.899368 [Byte1]: 61
8654 13:31:29.903876
8655 13:31:29.903960 Set Vref, RX VrefLevel [Byte0]: 62
8656 13:31:29.906986 [Byte1]: 62
8657 13:31:29.911384
8658 13:31:29.911463 Set Vref, RX VrefLevel [Byte0]: 63
8659 13:31:29.914785 [Byte1]: 63
8660 13:31:29.918839
8661 13:31:29.918970 Set Vref, RX VrefLevel [Byte0]: 64
8662 13:31:29.922010 [Byte1]: 64
8663 13:31:29.926341
8664 13:31:29.926444 Set Vref, RX VrefLevel [Byte0]: 65
8665 13:31:29.929953 [Byte1]: 65
8666 13:31:29.934211
8667 13:31:29.934307 Set Vref, RX VrefLevel [Byte0]: 66
8668 13:31:29.937225 [Byte1]: 66
8669 13:31:29.941597
8670 13:31:29.941680 Set Vref, RX VrefLevel [Byte0]: 67
8671 13:31:29.944948 [Byte1]: 67
8672 13:31:29.949336
8673 13:31:29.949423 Set Vref, RX VrefLevel [Byte0]: 68
8674 13:31:29.952197 [Byte1]: 68
8675 13:31:29.956973
8676 13:31:29.957055 Set Vref, RX VrefLevel [Byte0]: 69
8677 13:31:29.960324 [Byte1]: 69
8678 13:31:29.964301
8679 13:31:29.964383 Set Vref, RX VrefLevel [Byte0]: 70
8680 13:31:29.968016 [Byte1]: 70
8681 13:31:29.971879
8682 13:31:29.971961 Set Vref, RX VrefLevel [Byte0]: 71
8683 13:31:29.975290 [Byte1]: 71
8684 13:31:29.979813
8685 13:31:29.979896 Set Vref, RX VrefLevel [Byte0]: 72
8686 13:31:29.982759 [Byte1]: 72
8687 13:31:29.987080
8688 13:31:29.987153 Set Vref, RX VrefLevel [Byte0]: 73
8689 13:31:29.990256 [Byte1]: 73
8690 13:31:29.994332
8691 13:31:29.994454 Set Vref, RX VrefLevel [Byte0]: 74
8692 13:31:29.997876 [Byte1]: 74
8693 13:31:30.001957
8694 13:31:30.002075 Set Vref, RX VrefLevel [Byte0]: 75
8695 13:31:30.005376 [Byte1]: 75
8696 13:31:30.010101
8697 13:31:30.010224 Set Vref, RX VrefLevel [Byte0]: 76
8698 13:31:30.013128 [Byte1]: 76
8699 13:31:30.017453
8700 13:31:30.017576 Set Vref, RX VrefLevel [Byte0]: 77
8701 13:31:30.020636 [Byte1]: 77
8702 13:31:30.025121
8703 13:31:30.025245 Final RX Vref Byte 0 = 57 to rank0
8704 13:31:30.028337 Final RX Vref Byte 1 = 65 to rank0
8705 13:31:30.031856 Final RX Vref Byte 0 = 57 to rank1
8706 13:31:30.035184 Final RX Vref Byte 1 = 65 to rank1==
8707 13:31:30.038660 Dram Type= 6, Freq= 0, CH_1, rank 0
8708 13:31:30.041472 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8709 13:31:30.045178 ==
8710 13:31:30.045297 DQS Delay:
8711 13:31:30.045412 DQS0 = 0, DQS1 = 0
8712 13:31:30.048089 DQM Delay:
8713 13:31:30.048207 DQM0 = 133, DQM1 = 129
8714 13:31:30.051431 DQ Delay:
8715 13:31:30.054867 DQ0 =136, DQ1 =128, DQ2 =122, DQ3 =132
8716 13:31:30.058583 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
8717 13:31:30.061369 DQ8 =116, DQ9 =118, DQ10 =134, DQ11 =122
8718 13:31:30.064731 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =136
8719 13:31:30.064879
8720 13:31:30.064988
8721 13:31:30.065094
8722 13:31:30.068121 [DramC_TX_OE_Calibration] TA2
8723 13:31:30.071629 Original DQ_B0 (3 6) =30, OEN = 27
8724 13:31:30.074896 Original DQ_B1 (3 6) =30, OEN = 27
8725 13:31:30.077879 24, 0x0, End_B0=24 End_B1=24
8726 13:31:30.078001 25, 0x0, End_B0=25 End_B1=25
8727 13:31:30.081270 26, 0x0, End_B0=26 End_B1=26
8728 13:31:30.084833 27, 0x0, End_B0=27 End_B1=27
8729 13:31:30.087894 28, 0x0, End_B0=28 End_B1=28
8730 13:31:30.087999 29, 0x0, End_B0=29 End_B1=29
8731 13:31:30.091268 30, 0x0, End_B0=30 End_B1=30
8732 13:31:30.094689 31, 0x4141, End_B0=30 End_B1=30
8733 13:31:30.098256 Byte0 end_step=30 best_step=27
8734 13:31:30.101416 Byte1 end_step=30 best_step=27
8735 13:31:30.104831 Byte0 TX OE(2T, 0.5T) = (3, 3)
8736 13:31:30.104951 Byte1 TX OE(2T, 0.5T) = (3, 3)
8737 13:31:30.107926
8738 13:31:30.108046
8739 13:31:30.114687 [DQSOSCAuto] RK0, (LSB)MR18= 0x1725, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8740 13:31:30.118161 CH1 RK0: MR19=303, MR18=1725
8741 13:31:30.125072 CH1_RK0: MR19=0x303, MR18=0x1725, DQSOSC=391, MR23=63, INC=24, DEC=16
8742 13:31:30.125165
8743 13:31:30.127910 ----->DramcWriteLeveling(PI) begin...
8744 13:31:30.128015 ==
8745 13:31:30.131430 Dram Type= 6, Freq= 0, CH_1, rank 1
8746 13:31:30.134737 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8747 13:31:30.134867 ==
8748 13:31:30.138053 Write leveling (Byte 0): 26 => 26
8749 13:31:30.141488 Write leveling (Byte 1): 28 => 28
8750 13:31:30.144667 DramcWriteLeveling(PI) end<-----
8751 13:31:30.144759
8752 13:31:30.144862 ==
8753 13:31:30.147901 Dram Type= 6, Freq= 0, CH_1, rank 1
8754 13:31:30.151244 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8755 13:31:30.151344 ==
8756 13:31:30.154749 [Gating] SW mode calibration
8757 13:31:30.161726 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8758 13:31:30.167810 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8759 13:31:30.171402 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8760 13:31:30.174547 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8761 13:31:30.181582 1 4 8 | B1->B0 | 3131 2323 | 1 0 | (0 0) (0 0)
8762 13:31:30.184514 1 4 12 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (0 0)
8763 13:31:30.187930 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8764 13:31:30.194411 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8765 13:31:30.198051 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8766 13:31:30.200977 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8767 13:31:30.208030 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8768 13:31:30.211013 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8769 13:31:30.214391 1 5 8 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 0)
8770 13:31:30.220950 1 5 12 | B1->B0 | 2323 3333 | 0 0 | (1 0) (0 1)
8771 13:31:30.224175 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 13:31:30.227813 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8773 13:31:30.234303 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8774 13:31:30.237713 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8775 13:31:30.240912 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8776 13:31:30.248094 1 6 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8777 13:31:30.250904 1 6 8 | B1->B0 | 4343 2424 | 0 0 | (0 0) (0 0)
8778 13:31:30.254461 1 6 12 | B1->B0 | 4646 3333 | 0 0 | (0 0) (0 0)
8779 13:31:30.258013 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8780 13:31:30.264333 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8781 13:31:30.267814 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8782 13:31:30.270769 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8783 13:31:30.277474 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8784 13:31:30.281192 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8785 13:31:30.284029 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8786 13:31:30.290846 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8787 13:31:30.294230 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 13:31:30.297710 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 13:31:30.304103 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 13:31:30.307170 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 13:31:30.310772 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 13:31:30.317456 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 13:31:30.320591 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 13:31:30.323922 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 13:31:30.330839 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 13:31:30.333743 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 13:31:30.337150 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 13:31:30.343826 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 13:31:30.347260 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 13:31:30.350439 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 13:31:30.357398 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8802 13:31:30.360746 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 13:31:30.364125 Total UI for P1: 0, mck2ui 16
8804 13:31:30.367375 best dqsien dly found for B0: ( 1, 9, 8)
8805 13:31:30.370671 Total UI for P1: 0, mck2ui 16
8806 13:31:30.374060 best dqsien dly found for B1: ( 1, 9, 8)
8807 13:31:30.377595 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8808 13:31:30.380862 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8809 13:31:30.380945
8810 13:31:30.384015 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8811 13:31:30.387417 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8812 13:31:30.390824 [Gating] SW calibration Done
8813 13:31:30.390908 ==
8814 13:31:30.394165 Dram Type= 6, Freq= 0, CH_1, rank 1
8815 13:31:30.397701 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8816 13:31:30.397785 ==
8817 13:31:30.400508 RX Vref Scan: 0
8818 13:31:30.400591
8819 13:31:30.403931 RX Vref 0 -> 0, step: 1
8820 13:31:30.404015
8821 13:31:30.404081 RX Delay 0 -> 252, step: 8
8822 13:31:30.410679 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8823 13:31:30.413894 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8824 13:31:30.417344 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8825 13:31:30.420466 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8826 13:31:30.423965 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8827 13:31:30.427262 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8828 13:31:30.433888 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8829 13:31:30.437308 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8830 13:31:30.440678 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8831 13:31:30.443921 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8832 13:31:30.447241 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8833 13:31:30.453971 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8834 13:31:30.457234 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8835 13:31:30.460219 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8836 13:31:30.463707 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8837 13:31:30.470273 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8838 13:31:30.470359 ==
8839 13:31:30.473764 Dram Type= 6, Freq= 0, CH_1, rank 1
8840 13:31:30.477197 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8841 13:31:30.477321 ==
8842 13:31:30.477415 DQS Delay:
8843 13:31:30.480054 DQS0 = 0, DQS1 = 0
8844 13:31:30.480127 DQM Delay:
8845 13:31:30.483534 DQM0 = 136, DQM1 = 131
8846 13:31:30.483607 DQ Delay:
8847 13:31:30.487378 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8848 13:31:30.490290 DQ4 =135, DQ5 =147, DQ6 =139, DQ7 =135
8849 13:31:30.493826 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8850 13:31:30.496605 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8851 13:31:30.496707
8852 13:31:30.496812
8853 13:31:30.500009 ==
8854 13:31:30.503496 Dram Type= 6, Freq= 0, CH_1, rank 1
8855 13:31:30.506968 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8856 13:31:30.507052 ==
8857 13:31:30.507135
8858 13:31:30.507205
8859 13:31:30.510433 TX Vref Scan disable
8860 13:31:30.510516 == TX Byte 0 ==
8861 13:31:30.513377 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8862 13:31:30.520099 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8863 13:31:30.520187 == TX Byte 1 ==
8864 13:31:30.523784 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8865 13:31:30.530251 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8866 13:31:30.530337 ==
8867 13:31:30.533515 Dram Type= 6, Freq= 0, CH_1, rank 1
8868 13:31:30.536738 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8869 13:31:30.536863 ==
8870 13:31:30.550473
8871 13:31:30.554310 TX Vref early break, caculate TX vref
8872 13:31:30.557159 TX Vref=16, minBit 9, minWin=22, winSum=381
8873 13:31:30.561036 TX Vref=18, minBit 8, minWin=23, winSum=391
8874 13:31:30.563916 TX Vref=20, minBit 9, minWin=23, winSum=400
8875 13:31:30.567859 TX Vref=22, minBit 8, minWin=24, winSum=403
8876 13:31:30.570714 TX Vref=24, minBit 12, minWin=24, winSum=411
8877 13:31:30.577072 TX Vref=26, minBit 11, minWin=23, winSum=418
8878 13:31:30.580742 TX Vref=28, minBit 9, minWin=25, winSum=420
8879 13:31:30.584223 TX Vref=30, minBit 9, minWin=24, winSum=412
8880 13:31:30.587087 TX Vref=32, minBit 9, minWin=24, winSum=408
8881 13:31:30.590518 TX Vref=34, minBit 8, minWin=23, winSum=399
8882 13:31:30.594101 TX Vref=36, minBit 9, minWin=23, winSum=395
8883 13:31:30.600599 [TxChooseVref] Worse bit 9, Min win 25, Win sum 420, Final Vref 28
8884 13:31:30.600685
8885 13:31:30.603661 Final TX Range 0 Vref 28
8886 13:31:30.603746
8887 13:31:30.603814 ==
8888 13:31:30.607020 Dram Type= 6, Freq= 0, CH_1, rank 1
8889 13:31:30.610426 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8890 13:31:30.610513 ==
8891 13:31:30.610581
8892 13:31:30.610650
8893 13:31:30.613973 TX Vref Scan disable
8894 13:31:30.620673 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8895 13:31:30.620788 == TX Byte 0 ==
8896 13:31:30.623932 u2DelayCellOfst[0]=17 cells (5 PI)
8897 13:31:30.627046 u2DelayCellOfst[1]=13 cells (4 PI)
8898 13:31:30.630555 u2DelayCellOfst[2]=0 cells (0 PI)
8899 13:31:30.633772 u2DelayCellOfst[3]=6 cells (2 PI)
8900 13:31:30.637254 u2DelayCellOfst[4]=6 cells (2 PI)
8901 13:31:30.640833 u2DelayCellOfst[5]=20 cells (6 PI)
8902 13:31:30.644091 u2DelayCellOfst[6]=20 cells (6 PI)
8903 13:31:30.647204 u2DelayCellOfst[7]=6 cells (2 PI)
8904 13:31:30.650709 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8905 13:31:30.653793 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8906 13:31:30.657423 == TX Byte 1 ==
8907 13:31:30.660325 u2DelayCellOfst[8]=0 cells (0 PI)
8908 13:31:30.660403 u2DelayCellOfst[9]=3 cells (1 PI)
8909 13:31:30.663891 u2DelayCellOfst[10]=10 cells (3 PI)
8910 13:31:30.666933 u2DelayCellOfst[11]=6 cells (2 PI)
8911 13:31:30.670675 u2DelayCellOfst[12]=17 cells (5 PI)
8912 13:31:30.673537 u2DelayCellOfst[13]=17 cells (5 PI)
8913 13:31:30.676903 u2DelayCellOfst[14]=20 cells (6 PI)
8914 13:31:30.680371 u2DelayCellOfst[15]=20 cells (6 PI)
8915 13:31:30.683826 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8916 13:31:30.690338 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8917 13:31:30.690448 DramC Write-DBI on
8918 13:31:30.690543 ==
8919 13:31:30.693660 Dram Type= 6, Freq= 0, CH_1, rank 1
8920 13:31:30.700402 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8921 13:31:30.700487 ==
8922 13:31:30.700555
8923 13:31:30.700616
8924 13:31:30.700675 TX Vref Scan disable
8925 13:31:30.703907 == TX Byte 0 ==
8926 13:31:30.707389 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8927 13:31:30.710815 == TX Byte 1 ==
8928 13:31:30.713794 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8929 13:31:30.717321 DramC Write-DBI off
8930 13:31:30.717407
8931 13:31:30.717473 [DATLAT]
8932 13:31:30.717536 Freq=1600, CH1 RK1
8933 13:31:30.717596
8934 13:31:30.720591 DATLAT Default: 0xf
8935 13:31:30.720675 0, 0xFFFF, sum = 0
8936 13:31:30.724096 1, 0xFFFF, sum = 0
8937 13:31:30.724181 2, 0xFFFF, sum = 0
8938 13:31:30.727205 3, 0xFFFF, sum = 0
8939 13:31:30.730510 4, 0xFFFF, sum = 0
8940 13:31:30.730597 5, 0xFFFF, sum = 0
8941 13:31:30.733702 6, 0xFFFF, sum = 0
8942 13:31:30.733788 7, 0xFFFF, sum = 0
8943 13:31:30.737623 8, 0xFFFF, sum = 0
8944 13:31:30.737709 9, 0xFFFF, sum = 0
8945 13:31:30.740992 10, 0xFFFF, sum = 0
8946 13:31:30.741078 11, 0xFFFF, sum = 0
8947 13:31:30.744122 12, 0xFFFF, sum = 0
8948 13:31:30.744207 13, 0xFFFF, sum = 0
8949 13:31:30.747029 14, 0x0, sum = 1
8950 13:31:30.747115 15, 0x0, sum = 2
8951 13:31:30.750758 16, 0x0, sum = 3
8952 13:31:30.750847 17, 0x0, sum = 4
8953 13:31:30.753850 best_step = 15
8954 13:31:30.753939
8955 13:31:30.754005 ==
8956 13:31:30.757395 Dram Type= 6, Freq= 0, CH_1, rank 1
8957 13:31:30.760527 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8958 13:31:30.760612 ==
8959 13:31:30.760678 RX Vref Scan: 0
8960 13:31:30.764040
8961 13:31:30.764124 RX Vref 0 -> 0, step: 1
8962 13:31:30.764191
8963 13:31:30.767449 RX Delay 19 -> 252, step: 4
8964 13:31:30.770628 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
8965 13:31:30.777418 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8966 13:31:30.780333 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8967 13:31:30.783858 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8968 13:31:30.787252 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8969 13:31:30.790273 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8970 13:31:30.793644 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8971 13:31:30.800515 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
8972 13:31:30.803540 iDelay=195, Bit 8, Center 114 (67 ~ 162) 96
8973 13:31:30.806865 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8974 13:31:30.810309 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8975 13:31:30.813739 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8976 13:31:30.820374 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8977 13:31:30.823354 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8978 13:31:30.827165 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8979 13:31:30.830479 iDelay=195, Bit 15, Center 142 (91 ~ 194) 104
8980 13:31:30.830596 ==
8981 13:31:30.833796 Dram Type= 6, Freq= 0, CH_1, rank 1
8982 13:31:30.837165 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8983 13:31:30.840125 ==
8984 13:31:30.840234 DQS Delay:
8985 13:31:30.840335 DQS0 = 0, DQS1 = 0
8986 13:31:30.843448 DQM Delay:
8987 13:31:30.843549 DQM0 = 133, DQM1 = 130
8988 13:31:30.847106 DQ Delay:
8989 13:31:30.850319 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
8990 13:31:30.853670 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =130
8991 13:31:30.856890 DQ8 =114, DQ9 =118, DQ10 =130, DQ11 =124
8992 13:31:30.860121 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =142
8993 13:31:30.860205
8994 13:31:30.860271
8995 13:31:30.860332
8996 13:31:30.863510 [DramC_TX_OE_Calibration] TA2
8997 13:31:30.867050 Original DQ_B0 (3 6) =30, OEN = 27
8998 13:31:30.870532 Original DQ_B1 (3 6) =30, OEN = 27
8999 13:31:30.873870 24, 0x0, End_B0=24 End_B1=24
9000 13:31:30.873954 25, 0x0, End_B0=25 End_B1=25
9001 13:31:30.876798 26, 0x0, End_B0=26 End_B1=26
9002 13:31:30.880039 27, 0x0, End_B0=27 End_B1=27
9003 13:31:30.883414 28, 0x0, End_B0=28 End_B1=28
9004 13:31:30.883525 29, 0x0, End_B0=29 End_B1=29
9005 13:31:30.886883 30, 0x0, End_B0=30 End_B1=30
9006 13:31:30.890380 31, 0x4141, End_B0=30 End_B1=30
9007 13:31:30.893712 Byte0 end_step=30 best_step=27
9008 13:31:30.896612 Byte1 end_step=30 best_step=27
9009 13:31:30.899935 Byte0 TX OE(2T, 0.5T) = (3, 3)
9010 13:31:30.900053 Byte1 TX OE(2T, 0.5T) = (3, 3)
9011 13:31:30.903432
9012 13:31:30.903562
9013 13:31:30.910198 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b06, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 396 ps
9014 13:31:30.913650 CH1 RK1: MR19=303, MR18=1B06
9015 13:31:30.919948 CH1_RK1: MR19=0x303, MR18=0x1B06, DQSOSC=396, MR23=63, INC=23, DEC=15
9016 13:31:30.923331 [RxdqsGatingPostProcess] freq 1600
9017 13:31:30.926845 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9018 13:31:30.930187 best DQS0 dly(2T, 0.5T) = (1, 1)
9019 13:31:30.933743 best DQS1 dly(2T, 0.5T) = (1, 1)
9020 13:31:30.936767 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9021 13:31:30.940145 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9022 13:31:30.943154 best DQS0 dly(2T, 0.5T) = (1, 1)
9023 13:31:30.946462 best DQS1 dly(2T, 0.5T) = (1, 1)
9024 13:31:30.949718 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9025 13:31:30.953202 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9026 13:31:30.956761 Pre-setting of DQS Precalculation
9027 13:31:30.960254 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9028 13:31:30.966769 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9029 13:31:30.973298 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9030 13:31:30.973386
9031 13:31:30.973453
9032 13:31:30.976551 [Calibration Summary] 3200 Mbps
9033 13:31:30.979805 CH 0, Rank 0
9034 13:31:30.979885 SW Impedance : PASS
9035 13:31:30.982988 DUTY Scan : NO K
9036 13:31:30.986431 ZQ Calibration : PASS
9037 13:31:30.986532 Jitter Meter : NO K
9038 13:31:30.989738 CBT Training : PASS
9039 13:31:30.993141 Write leveling : PASS
9040 13:31:30.993244 RX DQS gating : PASS
9041 13:31:30.996562 RX DQ/DQS(RDDQC) : PASS
9042 13:31:30.999439 TX DQ/DQS : PASS
9043 13:31:30.999552 RX DATLAT : PASS
9044 13:31:31.002903 RX DQ/DQS(Engine): PASS
9045 13:31:31.006338 TX OE : PASS
9046 13:31:31.006455 All Pass.
9047 13:31:31.006556
9048 13:31:31.006650 CH 0, Rank 1
9049 13:31:31.009528 SW Impedance : PASS
9050 13:31:31.012937 DUTY Scan : NO K
9051 13:31:31.013044 ZQ Calibration : PASS
9052 13:31:31.016288 Jitter Meter : NO K
9053 13:31:31.016402 CBT Training : PASS
9054 13:31:31.019365 Write leveling : PASS
9055 13:31:31.023017 RX DQS gating : PASS
9056 13:31:31.023123 RX DQ/DQS(RDDQC) : PASS
9057 13:31:31.026082 TX DQ/DQS : PASS
9058 13:31:31.029564 RX DATLAT : PASS
9059 13:31:31.029667 RX DQ/DQS(Engine): PASS
9060 13:31:31.032653 TX OE : PASS
9061 13:31:31.032770 All Pass.
9062 13:31:31.032871
9063 13:31:31.036114 CH 1, Rank 0
9064 13:31:31.036217 SW Impedance : PASS
9065 13:31:31.039368 DUTY Scan : NO K
9066 13:31:31.042698 ZQ Calibration : PASS
9067 13:31:31.042808 Jitter Meter : NO K
9068 13:31:31.046204 CBT Training : PASS
9069 13:31:31.049586 Write leveling : PASS
9070 13:31:31.049694 RX DQS gating : PASS
9071 13:31:31.052668 RX DQ/DQS(RDDQC) : PASS
9072 13:31:31.056065 TX DQ/DQS : PASS
9073 13:31:31.056167 RX DATLAT : PASS
9074 13:31:31.060004 RX DQ/DQS(Engine): PASS
9075 13:31:31.060104 TX OE : PASS
9076 13:31:31.063098 All Pass.
9077 13:31:31.063209
9078 13:31:31.063306 CH 1, Rank 1
9079 13:31:31.066015 SW Impedance : PASS
9080 13:31:31.066128 DUTY Scan : NO K
9081 13:31:31.069497 ZQ Calibration : PASS
9082 13:31:31.073003 Jitter Meter : NO K
9083 13:31:31.073087 CBT Training : PASS
9084 13:31:31.075865 Write leveling : PASS
9085 13:31:31.079214 RX DQS gating : PASS
9086 13:31:31.079298 RX DQ/DQS(RDDQC) : PASS
9087 13:31:31.082566 TX DQ/DQS : PASS
9088 13:31:31.085836 RX DATLAT : PASS
9089 13:31:31.085955 RX DQ/DQS(Engine): PASS
9090 13:31:31.089284 TX OE : PASS
9091 13:31:31.089385 All Pass.
9092 13:31:31.089482
9093 13:31:31.092599 DramC Write-DBI on
9094 13:31:31.095945 PER_BANK_REFRESH: Hybrid Mode
9095 13:31:31.096050 TX_TRACKING: ON
9096 13:31:31.105932 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9097 13:31:31.112783 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9098 13:31:31.118890 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9099 13:31:31.125773 [FAST_K] Save calibration result to emmc
9100 13:31:31.125889 sync common calibartion params.
9101 13:31:31.129289 sync cbt_mode0:1, 1:1
9102 13:31:31.132304 dram_init: ddr_geometry: 2
9103 13:31:31.132416 dram_init: ddr_geometry: 2
9104 13:31:31.135543 dram_init: ddr_geometry: 2
9105 13:31:31.138929 0:dram_rank_size:100000000
9106 13:31:31.142319 1:dram_rank_size:100000000
9107 13:31:31.145439 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9108 13:31:31.148860 DFS_SHUFFLE_HW_MODE: ON
9109 13:31:31.152056 dramc_set_vcore_voltage set vcore to 725000
9110 13:31:31.155589 Read voltage for 1600, 0
9111 13:31:31.155674 Vio18 = 0
9112 13:31:31.155739 Vcore = 725000
9113 13:31:31.158979 Vdram = 0
9114 13:31:31.159062 Vddq = 0
9115 13:31:31.159128 Vmddr = 0
9116 13:31:31.162448 switch to 3200 Mbps bootup
9117 13:31:31.165855 [DramcRunTimeConfig]
9118 13:31:31.165938 PHYPLL
9119 13:31:31.166012 DPM_CONTROL_AFTERK: ON
9120 13:31:31.169090 PER_BANK_REFRESH: ON
9121 13:31:31.172110 REFRESH_OVERHEAD_REDUCTION: ON
9122 13:31:31.172193 CMD_PICG_NEW_MODE: OFF
9123 13:31:31.175720 XRTWTW_NEW_MODE: ON
9124 13:31:31.178672 XRTRTR_NEW_MODE: ON
9125 13:31:31.178755 TX_TRACKING: ON
9126 13:31:31.181937 RDSEL_TRACKING: OFF
9127 13:31:31.182025 DQS Precalculation for DVFS: ON
9128 13:31:31.185857 RX_TRACKING: OFF
9129 13:31:31.185942 HW_GATING DBG: ON
9130 13:31:31.188717 ZQCS_ENABLE_LP4: ON
9131 13:31:31.188818 RX_PICG_NEW_MODE: ON
9132 13:31:31.192302 TX_PICG_NEW_MODE: ON
9133 13:31:31.195169 ENABLE_RX_DCM_DPHY: ON
9134 13:31:31.198540 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9135 13:31:31.198624 DUMMY_READ_FOR_TRACKING: OFF
9136 13:31:31.201819 !!! SPM_CONTROL_AFTERK: OFF
9137 13:31:31.205129 !!! SPM could not control APHY
9138 13:31:31.208504 IMPEDANCE_TRACKING: ON
9139 13:31:31.208592 TEMP_SENSOR: ON
9140 13:31:31.211761 HW_SAVE_FOR_SR: OFF
9141 13:31:31.211845 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9142 13:31:31.218794 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9143 13:31:31.218908 Read ODT Tracking: ON
9144 13:31:31.221739 Refresh Rate DeBounce: ON
9145 13:31:31.225120 DFS_NO_QUEUE_FLUSH: ON
9146 13:31:31.228445 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9147 13:31:31.228530 ENABLE_DFS_RUNTIME_MRW: OFF
9148 13:31:31.231706 DDR_RESERVE_NEW_MODE: ON
9149 13:31:31.235148 MR_CBT_SWITCH_FREQ: ON
9150 13:31:31.235232 =========================
9151 13:31:31.254786 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9152 13:31:31.258195 dram_init: ddr_geometry: 2
9153 13:31:31.276361 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9154 13:31:31.280082 dram_init: dram init end (result: 0)
9155 13:31:31.286339 DRAM-K: Full calibration passed in 24520 msecs
9156 13:31:31.289547 MRC: failed to locate region type 0.
9157 13:31:31.289631 DRAM rank0 size:0x100000000,
9158 13:31:31.292732 DRAM rank1 size=0x100000000
9159 13:31:31.302883 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9160 13:31:31.309412 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9161 13:31:31.316201 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9162 13:31:31.322475 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9163 13:31:31.325902 DRAM rank0 size:0x100000000,
9164 13:31:31.329227 DRAM rank1 size=0x100000000
9165 13:31:31.329312 CBMEM:
9166 13:31:31.332709 IMD: root @ 0xfffff000 254 entries.
9167 13:31:31.336062 IMD: root @ 0xffffec00 62 entries.
9168 13:31:31.338881 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9169 13:31:31.345805 WARNING: RO_VPD is uninitialized or empty.
9170 13:31:31.349148 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9171 13:31:31.356722 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9172 13:31:31.368870 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9173 13:31:31.380472 BS: romstage times (exec / console): total (unknown) / 24016 ms
9174 13:31:31.380561
9175 13:31:31.380628
9176 13:31:31.390223 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9177 13:31:31.393636 ARM64: Exception handlers installed.
9178 13:31:31.397131 ARM64: Testing exception
9179 13:31:31.400120 ARM64: Done test exception
9180 13:31:31.400194 Enumerating buses...
9181 13:31:31.403642 Show all devs... Before device enumeration.
9182 13:31:31.406865 Root Device: enabled 1
9183 13:31:31.410509 CPU_CLUSTER: 0: enabled 1
9184 13:31:31.410593 CPU: 00: enabled 1
9185 13:31:31.413536 Compare with tree...
9186 13:31:31.413621 Root Device: enabled 1
9187 13:31:31.416735 CPU_CLUSTER: 0: enabled 1
9188 13:31:31.420273 CPU: 00: enabled 1
9189 13:31:31.420356 Root Device scanning...
9190 13:31:31.424026 scan_static_bus for Root Device
9191 13:31:31.426818 CPU_CLUSTER: 0 enabled
9192 13:31:31.430213 scan_static_bus for Root Device done
9193 13:31:31.433231 scan_bus: bus Root Device finished in 8 msecs
9194 13:31:31.433341 done
9195 13:31:31.439820 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9196 13:31:31.443202 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9197 13:31:31.450094 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9198 13:31:31.453715 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9199 13:31:31.457007 Allocating resources...
9200 13:31:31.460061 Reading resources...
9201 13:31:31.463089 Root Device read_resources bus 0 link: 0
9202 13:31:31.463171 DRAM rank0 size:0x100000000,
9203 13:31:31.466407 DRAM rank1 size=0x100000000
9204 13:31:31.469892 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9205 13:31:31.473203 CPU: 00 missing read_resources
9206 13:31:31.479973 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9207 13:31:31.482896 Root Device read_resources bus 0 link: 0 done
9208 13:31:31.482980 Done reading resources.
9209 13:31:31.489869 Show resources in subtree (Root Device)...After reading.
9210 13:31:31.493352 Root Device child on link 0 CPU_CLUSTER: 0
9211 13:31:31.496423 CPU_CLUSTER: 0 child on link 0 CPU: 00
9212 13:31:31.506280 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9213 13:31:31.506366 CPU: 00
9214 13:31:31.509820 Root Device assign_resources, bus 0 link: 0
9215 13:31:31.512912 CPU_CLUSTER: 0 missing set_resources
9216 13:31:31.519504 Root Device assign_resources, bus 0 link: 0 done
9217 13:31:31.519588 Done setting resources.
9218 13:31:31.526311 Show resources in subtree (Root Device)...After assigning values.
9219 13:31:31.529420 Root Device child on link 0 CPU_CLUSTER: 0
9220 13:31:31.533251 CPU_CLUSTER: 0 child on link 0 CPU: 00
9221 13:31:31.543053 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9222 13:31:31.543139 CPU: 00
9223 13:31:31.546207 Done allocating resources.
9224 13:31:31.549465 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9225 13:31:31.552663 Enabling resources...
9226 13:31:31.552780 done.
9227 13:31:31.559529 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9228 13:31:31.559643 Initializing devices...
9229 13:31:31.563038 Root Device init
9230 13:31:31.563150 init hardware done!
9231 13:31:31.566078 0x00000018: ctrlr->caps
9232 13:31:31.569694 52.000 MHz: ctrlr->f_max
9233 13:31:31.569781 0.400 MHz: ctrlr->f_min
9234 13:31:31.572730 0x40ff8080: ctrlr->voltages
9235 13:31:31.572822 sclk: 390625
9236 13:31:31.576162 Bus Width = 1
9237 13:31:31.576245 sclk: 390625
9238 13:31:31.579503 Bus Width = 1
9239 13:31:31.579584 Early init status = 3
9240 13:31:31.586008 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9241 13:31:31.589487 in-header: 03 fc 00 00 01 00 00 00
9242 13:31:31.589568 in-data: 00
9243 13:31:31.595812 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9244 13:31:31.599610 in-header: 03 fd 00 00 00 00 00 00
9245 13:31:31.602772 in-data:
9246 13:31:31.605712 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9247 13:31:31.610012 in-header: 03 fc 00 00 01 00 00 00
9248 13:31:31.613576 in-data: 00
9249 13:31:31.616420 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9250 13:31:31.622183 in-header: 03 fd 00 00 00 00 00 00
9251 13:31:31.625497 in-data:
9252 13:31:31.628854 [SSUSB] Setting up USB HOST controller...
9253 13:31:31.632015 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9254 13:31:31.635390 [SSUSB] phy power-on done.
9255 13:31:31.638716 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9256 13:31:31.645030 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9257 13:31:31.648542 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9258 13:31:31.654908 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9259 13:31:31.661596 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9260 13:31:31.668627 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9261 13:31:31.674995 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9262 13:31:31.681782 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9263 13:31:31.685254 SPM: binary array size = 0x9dc
9264 13:31:31.688380 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9265 13:31:31.694974 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9266 13:31:31.701381 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9267 13:31:31.704812 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9268 13:31:31.711358 configure_display: Starting display init
9269 13:31:31.745387 anx7625_power_on_init: Init interface.
9270 13:31:31.748627 anx7625_disable_pd_protocol: Disabled PD feature.
9271 13:31:31.751619 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9272 13:31:31.779817 anx7625_start_dp_work: Secure OCM version=00
9273 13:31:31.782766 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9274 13:31:31.797671 sp_tx_get_edid_block: EDID Block = 1
9275 13:31:31.900459 Extracted contents:
9276 13:31:31.903725 header: 00 ff ff ff ff ff ff 00
9277 13:31:31.906926 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9278 13:31:31.910323 version: 01 04
9279 13:31:31.913898 basic params: 95 1f 11 78 0a
9280 13:31:31.916851 chroma info: 76 90 94 55 54 90 27 21 50 54
9281 13:31:31.920267 established: 00 00 00
9282 13:31:31.924039 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9283 13:31:31.930316 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9284 13:31:31.937035 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9285 13:31:31.943606 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9286 13:31:31.950289 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9287 13:31:31.953520 extensions: 00
9288 13:31:31.953632 checksum: fb
9289 13:31:31.953726
9290 13:31:31.956776 Manufacturer: IVO Model 57d Serial Number 0
9291 13:31:31.960070 Made week 0 of 2020
9292 13:31:31.960174 EDID version: 1.4
9293 13:31:31.963475 Digital display
9294 13:31:31.967038 6 bits per primary color channel
9295 13:31:31.967155 DisplayPort interface
9296 13:31:31.970355 Maximum image size: 31 cm x 17 cm
9297 13:31:31.973747 Gamma: 220%
9298 13:31:31.973847 Check DPMS levels
9299 13:31:31.976692 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9300 13:31:31.980384 First detailed timing is preferred timing
9301 13:31:31.983491 Established timings supported:
9302 13:31:31.986758 Standard timings supported:
9303 13:31:31.986861 Detailed timings
9304 13:31:31.993686 Hex of detail: 383680a07038204018303c0035ae10000019
9305 13:31:31.996821 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9306 13:31:32.003269 0780 0798 07c8 0820 hborder 0
9307 13:31:32.007044 0438 043b 0447 0458 vborder 0
9308 13:31:32.007147 -hsync -vsync
9309 13:31:32.009896 Did detailed timing
9310 13:31:32.013396 Hex of detail: 000000000000000000000000000000000000
9311 13:31:32.016763 Manufacturer-specified data, tag 0
9312 13:31:32.023176 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9313 13:31:32.023279 ASCII string: InfoVision
9314 13:31:32.030089 Hex of detail: 000000fe00523134304e574635205248200a
9315 13:31:32.033124 ASCII string: R140NWF5 RH
9316 13:31:32.033224 Checksum
9317 13:31:32.033315 Checksum: 0xfb (valid)
9318 13:31:32.040320 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9319 13:31:32.043179 DSI data_rate: 832800000 bps
9320 13:31:32.046496 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9321 13:31:32.050059 anx7625_parse_edid: pixelclock(138800).
9322 13:31:32.056651 hactive(1920), hsync(48), hfp(24), hbp(88)
9323 13:31:32.059753 vactive(1080), vsync(12), vfp(3), vbp(17)
9324 13:31:32.063140 anx7625_dsi_config: config dsi.
9325 13:31:32.069829 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9326 13:31:32.082601 anx7625_dsi_config: success to config DSI
9327 13:31:32.085544 anx7625_dp_start: MIPI phy setup OK.
9328 13:31:32.088940 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9329 13:31:32.092415 mtk_ddp_mode_set invalid vrefresh 60
9330 13:31:32.095639 main_disp_path_setup
9331 13:31:32.095722 ovl_layer_smi_id_en
9332 13:31:32.099093 ovl_layer_smi_id_en
9333 13:31:32.099175 ccorr_config
9334 13:31:32.099240 aal_config
9335 13:31:32.102401 gamma_config
9336 13:31:32.102483 postmask_config
9337 13:31:32.105406 dither_config
9338 13:31:32.108790 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9339 13:31:32.115735 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9340 13:31:32.118780 Root Device init finished in 553 msecs
9341 13:31:32.122218 CPU_CLUSTER: 0 init
9342 13:31:32.128989 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9343 13:31:32.132194 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9344 13:31:32.135497 APU_MBOX 0x190000b0 = 0x10001
9345 13:31:32.138950 APU_MBOX 0x190001b0 = 0x10001
9346 13:31:32.141997 APU_MBOX 0x190005b0 = 0x10001
9347 13:31:32.145273 APU_MBOX 0x190006b0 = 0x10001
9348 13:31:32.148930 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9349 13:31:32.161454 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9350 13:31:32.173903 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9351 13:31:32.180359 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9352 13:31:32.191812 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9353 13:31:32.201371 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9354 13:31:32.204425 CPU_CLUSTER: 0 init finished in 81 msecs
9355 13:31:32.208012 Devices initialized
9356 13:31:32.210920 Show all devs... After init.
9357 13:31:32.211004 Root Device: enabled 1
9358 13:31:32.214520 CPU_CLUSTER: 0: enabled 1
9359 13:31:32.217701 CPU: 00: enabled 1
9360 13:31:32.220939 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9361 13:31:32.224561 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9362 13:31:32.227487 ELOG: NV offset 0x57f000 size 0x1000
9363 13:31:32.234250 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9364 13:31:32.240959 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9365 13:31:32.244287 ELOG: Event(17) added with size 13 at 2023-09-08 13:31:31 UTC
9366 13:31:32.250657 out: cmd=0x121: 03 db 21 01 00 00 00 00
9367 13:31:32.254131 in-header: 03 1e 00 00 2c 00 00 00
9368 13:31:32.263840 in-data: 41 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9369 13:31:32.270652 ELOG: Event(A1) added with size 10 at 2023-09-08 13:31:31 UTC
9370 13:31:32.277202 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9371 13:31:32.283966 ELOG: Event(A0) added with size 9 at 2023-09-08 13:31:31 UTC
9372 13:31:32.287590 elog_add_boot_reason: Logged dev mode boot
9373 13:31:32.290931 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9374 13:31:32.294042 Finalize devices...
9375 13:31:32.297129 Devices finalized
9376 13:31:32.300743 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9377 13:31:32.304307 Writing coreboot table at 0xffe64000
9378 13:31:32.307172 0. 000000000010a000-0000000000113fff: RAMSTAGE
9379 13:31:32.310750 1. 0000000040000000-00000000400fffff: RAM
9380 13:31:32.316969 2. 0000000040100000-000000004032afff: RAMSTAGE
9381 13:31:32.320374 3. 000000004032b000-00000000545fffff: RAM
9382 13:31:32.323771 4. 0000000054600000-000000005465ffff: BL31
9383 13:31:32.327097 5. 0000000054660000-00000000ffe63fff: RAM
9384 13:31:32.333943 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9385 13:31:32.336748 7. 0000000100000000-000000023fffffff: RAM
9386 13:31:32.340447 Passing 5 GPIOs to payload:
9387 13:31:32.343409 NAME | PORT | POLARITY | VALUE
9388 13:31:32.347256 EC in RW | 0x000000aa | low | undefined
9389 13:31:32.353647 EC interrupt | 0x00000005 | low | undefined
9390 13:31:32.356553 TPM interrupt | 0x000000ab | high | undefined
9391 13:31:32.363470 SD card detect | 0x00000011 | high | undefined
9392 13:31:32.366649 speaker enable | 0x00000093 | high | undefined
9393 13:31:32.370015 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9394 13:31:32.373753 in-header: 03 f9 00 00 02 00 00 00
9395 13:31:32.376642 in-data: 02 00
9396 13:31:32.376726 ADC[4]: Raw value=901032 ID=7
9397 13:31:32.380232 ADC[3]: Raw value=213179 ID=1
9398 13:31:32.383788 RAM Code: 0x71
9399 13:31:32.383873 ADC[6]: Raw value=74502 ID=0
9400 13:31:32.386884 ADC[5]: Raw value=212072 ID=1
9401 13:31:32.389914 SKU Code: 0x1
9402 13:31:32.393733 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 5bd8
9403 13:31:32.396613 coreboot table: 964 bytes.
9404 13:31:32.400059 IMD ROOT 0. 0xfffff000 0x00001000
9405 13:31:32.403248 IMD SMALL 1. 0xffffe000 0x00001000
9406 13:31:32.406774 RO MCACHE 2. 0xffffc000 0x00001104
9407 13:31:32.410180 CONSOLE 3. 0xfff7c000 0x00080000
9408 13:31:32.413482 FMAP 4. 0xfff7b000 0x00000452
9409 13:31:32.416738 TIME STAMP 5. 0xfff7a000 0x00000910
9410 13:31:32.419872 VBOOT WORK 6. 0xfff66000 0x00014000
9411 13:31:32.423238 RAMOOPS 7. 0xffe66000 0x00100000
9412 13:31:32.426800 COREBOOT 8. 0xffe64000 0x00002000
9413 13:31:32.426911 IMD small region:
9414 13:31:32.430051 IMD ROOT 0. 0xffffec00 0x00000400
9415 13:31:32.436879 VPD 1. 0xffffeb80 0x0000006c
9416 13:31:32.439679 MMC STATUS 2. 0xffffeb60 0x00000004
9417 13:31:32.443505 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9418 13:31:32.446461 Probing TPM: done!
9419 13:31:32.450354 Connected to device vid:did:rid of 1ae0:0028:00
9420 13:31:32.460194 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9421 13:31:32.463709 Initialized TPM device CR50 revision 0
9422 13:31:32.466991 Checking cr50 for pending updates
9423 13:31:32.470819 Reading cr50 TPM mode
9424 13:31:32.479903 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9425 13:31:32.486418 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9426 13:31:32.526502 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9427 13:31:32.529850 Checking segment from ROM address 0x40100000
9428 13:31:32.533403 Checking segment from ROM address 0x4010001c
9429 13:31:32.539635 Loading segment from ROM address 0x40100000
9430 13:31:32.539720 code (compression=0)
9431 13:31:32.546249 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9432 13:31:32.556507 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9433 13:31:32.556594 it's not compressed!
9434 13:31:32.562727 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9435 13:31:32.566197 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9436 13:31:32.586924 Loading segment from ROM address 0x4010001c
9437 13:31:32.587023 Entry Point 0x80000000
9438 13:31:32.590093 Loaded segments
9439 13:31:32.593679 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9440 13:31:32.600216 Jumping to boot code at 0x80000000(0xffe64000)
9441 13:31:32.606741 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9442 13:31:32.613136 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9443 13:31:32.621275 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9444 13:31:32.624547 Checking segment from ROM address 0x40100000
9445 13:31:32.628026 Checking segment from ROM address 0x4010001c
9446 13:31:32.634872 Loading segment from ROM address 0x40100000
9447 13:31:32.634955 code (compression=1)
9448 13:31:32.641214 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9449 13:31:32.651250 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9450 13:31:32.651348 using LZMA
9451 13:31:32.659538 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9452 13:31:32.666153 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9453 13:31:32.669350 Loading segment from ROM address 0x4010001c
9454 13:31:32.669492 Entry Point 0x54601000
9455 13:31:32.672736 Loaded segments
9456 13:31:32.675978 NOTICE: MT8192 bl31_setup
9457 13:31:32.683141 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9458 13:31:32.686278 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9459 13:31:32.690025 WARNING: region 0:
9460 13:31:32.693190 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9461 13:31:32.693324 WARNING: region 1:
9462 13:31:32.699897 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9463 13:31:32.703124 WARNING: region 2:
9464 13:31:32.706684 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9465 13:31:32.709896 WARNING: region 3:
9466 13:31:32.713124 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9467 13:31:32.716536 WARNING: region 4:
9468 13:31:32.719803 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9469 13:31:32.723522 WARNING: region 5:
9470 13:31:32.726360 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9471 13:31:32.729925 WARNING: region 6:
9472 13:31:32.733182 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9473 13:31:32.733256 WARNING: region 7:
9474 13:31:32.740131 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9475 13:31:32.746781 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9476 13:31:32.749862 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9477 13:31:32.753171 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9478 13:31:32.759878 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9479 13:31:32.763360 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9480 13:31:32.766640 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9481 13:31:32.773357 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9482 13:31:32.776406 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9483 13:31:32.779700 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9484 13:31:32.786336 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9485 13:31:32.789753 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9486 13:31:32.796344 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9487 13:31:32.799781 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9488 13:31:32.803358 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9489 13:31:32.809762 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9490 13:31:32.813381 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9491 13:31:32.816479 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9492 13:31:32.823419 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9493 13:31:32.826903 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9494 13:31:32.833541 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9495 13:31:32.836366 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9496 13:31:32.840060 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9497 13:31:32.846556 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9498 13:31:32.849943 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9499 13:31:32.853282 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9500 13:31:32.860338 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9501 13:31:32.863680 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9502 13:31:32.870107 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9503 13:31:32.874032 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9504 13:31:32.877003 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9505 13:31:32.883390 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9506 13:31:32.886941 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9507 13:31:32.890431 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9508 13:31:32.897016 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9509 13:31:32.900391 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9510 13:31:32.903811 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9511 13:31:32.906972 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9512 13:31:32.913470 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9513 13:31:32.917179 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9514 13:31:32.920227 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9515 13:31:32.923732 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9516 13:31:32.930153 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9517 13:31:32.933533 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9518 13:31:32.937246 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9519 13:31:32.940071 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9520 13:31:32.946979 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9521 13:31:32.949941 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9522 13:31:32.953534 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9523 13:31:32.960247 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9524 13:31:32.964123 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9525 13:31:32.966939 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9526 13:31:32.974431 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9527 13:31:32.977050 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9528 13:31:32.983719 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9529 13:31:32.987158 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9530 13:31:32.990335 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9531 13:31:32.997112 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9532 13:31:33.000426 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9533 13:31:33.007222 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9534 13:31:33.010745 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9535 13:31:33.017156 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9536 13:31:33.020650 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9537 13:31:33.027054 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9538 13:31:33.030237 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9539 13:31:33.033985 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9540 13:31:33.040485 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9541 13:31:33.043932 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9542 13:31:33.050736 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9543 13:31:33.054308 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9544 13:31:33.060598 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9545 13:31:33.063912 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9546 13:31:33.067218 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9547 13:31:33.073745 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9548 13:31:33.077236 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9549 13:31:33.083914 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9550 13:31:33.087383 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9551 13:31:33.093810 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9552 13:31:33.097510 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9553 13:31:33.100712 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9554 13:31:33.107468 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9555 13:31:33.110399 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9556 13:31:33.117467 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9557 13:31:33.120889 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9558 13:31:33.127603 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9559 13:31:33.130661 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9560 13:31:33.134183 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9561 13:31:33.140761 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9562 13:31:33.144245 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9563 13:31:33.150873 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9564 13:31:33.154224 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9565 13:31:33.157700 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9566 13:31:33.164063 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9567 13:31:33.167489 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9568 13:31:33.173986 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9569 13:31:33.177351 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9570 13:31:33.184251 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9571 13:31:33.187671 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9572 13:31:33.190792 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9573 13:31:33.194102 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9574 13:31:33.201059 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9575 13:31:33.204303 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9576 13:31:33.207693 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9577 13:31:33.214199 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9578 13:31:33.217808 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9579 13:31:33.224455 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9580 13:31:33.228045 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9581 13:31:33.230812 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9582 13:31:33.237640 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9583 13:31:33.240671 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9584 13:31:33.247549 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9585 13:31:33.250910 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9586 13:31:33.254078 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9587 13:31:33.261086 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9588 13:31:33.264385 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9589 13:31:33.267897 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9590 13:31:33.274198 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9591 13:31:33.278019 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9592 13:31:33.280769 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9593 13:31:33.287833 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9594 13:31:33.290828 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9595 13:31:33.294334 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9596 13:31:33.297606 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9597 13:31:33.304445 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9598 13:31:33.307855 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9599 13:31:33.310843 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9600 13:31:33.317794 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9601 13:31:33.321391 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9602 13:31:33.324335 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9603 13:31:33.331105 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9604 13:31:33.334298 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9605 13:31:33.341180 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9606 13:31:33.344252 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9607 13:31:33.347867 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9608 13:31:33.354434 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9609 13:31:33.357831 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9610 13:31:33.364564 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9611 13:31:33.367981 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9612 13:31:33.370930 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9613 13:31:33.377847 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9614 13:31:33.381106 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9615 13:31:33.384361 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9616 13:31:33.391238 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9617 13:31:33.394635 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9618 13:31:33.401228 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9619 13:31:33.404493 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9620 13:31:33.407857 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9621 13:31:33.414396 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9622 13:31:33.417786 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9623 13:31:33.421202 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9624 13:31:33.427819 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9625 13:31:33.431556 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9626 13:31:33.437841 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9627 13:31:33.441539 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9628 13:31:33.444932 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9629 13:31:33.451672 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9630 13:31:33.454884 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9631 13:31:33.461224 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9632 13:31:33.465051 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9633 13:31:33.467739 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9634 13:31:33.474668 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9635 13:31:33.478093 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9636 13:31:33.481019 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9637 13:31:33.487577 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9638 13:31:33.491330 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9639 13:31:33.497748 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9640 13:31:33.501106 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9641 13:31:33.504496 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9642 13:31:33.511396 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9643 13:31:33.514418 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9644 13:31:33.521511 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9645 13:31:33.524380 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9646 13:31:33.527901 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9647 13:31:33.534285 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9648 13:31:33.537591 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9649 13:31:33.544241 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9650 13:31:33.548073 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9651 13:31:33.551125 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9652 13:31:33.558070 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9653 13:31:33.560877 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9654 13:31:33.564442 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9655 13:31:33.571138 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9656 13:31:33.574131 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9657 13:31:33.580726 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9658 13:31:33.584044 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9659 13:31:33.587316 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9660 13:31:33.594055 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9661 13:31:33.597509 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9662 13:31:33.603839 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9663 13:31:33.607328 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9664 13:31:33.614037 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9665 13:31:33.617430 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9666 13:31:33.620406 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9667 13:31:33.627122 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9668 13:31:33.630587 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9669 13:31:33.637538 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9670 13:31:33.640649 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9671 13:31:33.643723 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9672 13:31:33.650405 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9673 13:31:33.653878 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9674 13:31:33.660553 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9675 13:31:33.663726 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9676 13:31:33.667701 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9677 13:31:33.673898 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9678 13:31:33.677087 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9679 13:31:33.683673 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9680 13:31:33.687031 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9681 13:31:33.694109 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9682 13:31:33.697450 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9683 13:31:33.700317 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9684 13:31:33.707067 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9685 13:31:33.710722 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9686 13:31:33.717112 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9687 13:31:33.720655 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9688 13:31:33.724162 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9689 13:31:33.730457 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9690 13:31:33.733942 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9691 13:31:33.740106 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9692 13:31:33.743750 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9693 13:31:33.750249 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9694 13:31:33.753470 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9695 13:31:33.757157 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9696 13:31:33.763513 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9697 13:31:33.767088 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9698 13:31:33.773514 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9699 13:31:33.776746 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9700 13:31:33.780281 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9701 13:31:33.786752 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9702 13:31:33.790099 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9703 13:31:33.797187 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9704 13:31:33.800071 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9705 13:31:33.803648 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9706 13:31:33.806877 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9707 13:31:33.810006 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9708 13:31:33.817175 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9709 13:31:33.820115 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9710 13:31:33.823554 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9711 13:31:33.830228 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9712 13:31:33.833584 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9713 13:31:33.840031 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9714 13:31:33.843489 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9715 13:31:33.846807 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9716 13:31:33.853849 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9717 13:31:33.856881 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9718 13:31:33.859910 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9719 13:31:33.866520 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9720 13:31:33.869824 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9721 13:31:33.876918 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9722 13:31:33.879750 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9723 13:31:33.883434 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9724 13:31:33.889795 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9725 13:31:33.893388 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9726 13:31:33.896703 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9727 13:31:33.903235 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9728 13:31:33.906785 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9729 13:31:33.909711 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9730 13:31:33.916509 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9731 13:31:33.919598 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9732 13:31:33.926457 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9733 13:31:33.930023 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9734 13:31:33.933264 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9735 13:31:33.939519 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9736 13:31:33.943243 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9737 13:31:33.946337 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9738 13:31:33.953146 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9739 13:31:33.956202 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9740 13:31:33.959851 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9741 13:31:33.966019 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9742 13:31:33.969399 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9743 13:31:33.972659 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9744 13:31:33.979582 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9745 13:31:33.982987 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9746 13:31:33.986433 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9747 13:31:33.989251 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9748 13:31:33.993233 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9749 13:31:33.999928 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9750 13:31:34.003050 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9751 13:31:34.006333 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9752 13:31:34.012682 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9753 13:31:34.016056 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9754 13:31:34.019535 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9755 13:31:34.022779 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9756 13:31:34.029593 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9757 13:31:34.032535 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9758 13:31:34.039118 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9759 13:31:34.042820 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9760 13:31:34.046149 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9761 13:31:34.052608 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9762 13:31:34.055821 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9763 13:31:34.062619 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9764 13:31:34.065706 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9765 13:31:34.069322 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9766 13:31:34.075919 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9767 13:31:34.079204 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9768 13:31:34.085871 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9769 13:31:34.089258 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9770 13:31:34.095415 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9771 13:31:34.099034 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9772 13:31:34.102094 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9773 13:31:34.108852 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9774 13:31:34.112216 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9775 13:31:34.118861 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9776 13:31:34.122417 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9777 13:31:34.125322 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9778 13:31:34.131774 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9779 13:31:34.135100 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9780 13:31:34.141868 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9781 13:31:34.145368 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9782 13:31:34.148499 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9783 13:31:34.155235 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9784 13:31:34.158866 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9785 13:31:34.165520 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9786 13:31:34.168516 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9787 13:31:34.174840 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9788 13:31:34.178499 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9789 13:31:34.181509 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9790 13:31:34.188320 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9791 13:31:34.191726 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9792 13:31:34.198356 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9793 13:31:34.201823 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9794 13:31:34.204697 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9795 13:31:34.211647 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9796 13:31:34.214829 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9797 13:31:34.221603 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9798 13:31:34.225035 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9799 13:31:34.228056 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9800 13:31:34.234804 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9801 13:31:34.238485 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9802 13:31:34.244749 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9803 13:31:34.248132 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9804 13:31:34.251469 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9805 13:31:34.258299 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9806 13:31:34.261110 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9807 13:31:34.267702 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9808 13:31:34.271255 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9809 13:31:34.277958 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9810 13:31:34.281129 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9811 13:31:34.284427 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9812 13:31:34.291202 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9813 13:31:34.294627 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9814 13:31:34.300962 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9815 13:31:34.304449 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9816 13:31:34.307687 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9817 13:31:34.314804 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9818 13:31:34.317616 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9819 13:31:34.324373 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9820 13:31:34.328079 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9821 13:31:34.331257 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9822 13:31:34.337707 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9823 13:31:34.341111 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9824 13:31:34.347742 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9825 13:31:34.350895 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9826 13:31:34.354293 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9827 13:31:34.361003 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9828 13:31:34.364444 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9829 13:31:34.370872 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9830 13:31:34.374056 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9831 13:31:34.380640 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9832 13:31:34.383953 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9833 13:31:34.390909 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9834 13:31:34.394049 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9835 13:31:34.397384 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9836 13:31:34.404248 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9837 13:31:34.407403 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9838 13:31:34.413717 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9839 13:31:34.417231 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9840 13:31:34.424379 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9841 13:31:34.427087 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9842 13:31:34.430651 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9843 13:31:34.437092 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9844 13:31:34.440620 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9845 13:31:34.447086 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9846 13:31:34.450642 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9847 13:31:34.456773 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9848 13:31:34.460149 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9849 13:31:34.463403 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9850 13:31:34.470053 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9851 13:31:34.473712 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9852 13:31:34.480529 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9853 13:31:34.483857 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9854 13:31:34.490265 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9855 13:31:34.493734 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9856 13:31:34.497153 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9857 13:31:34.503432 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9858 13:31:34.506901 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9859 13:31:34.513439 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9860 13:31:34.516825 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9861 13:31:34.523596 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9862 13:31:34.526593 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9863 13:31:34.530500 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9864 13:31:34.536643 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9865 13:31:34.540167 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9866 13:31:34.546701 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9867 13:31:34.550020 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9868 13:31:34.556689 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9869 13:31:34.560068 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9870 13:31:34.563527 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9871 13:31:34.569915 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9872 13:31:34.573240 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9873 13:31:34.579922 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9874 13:31:34.583291 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9875 13:31:34.590165 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9876 13:31:34.593375 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9877 13:31:34.596713 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9878 13:31:34.603724 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9879 13:31:34.606564 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9880 13:31:34.613315 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9881 13:31:34.616692 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9882 13:31:34.623274 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9883 13:31:34.626641 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9884 13:31:34.633176 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9885 13:31:34.636465 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9886 13:31:34.643008 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9887 13:31:34.646622 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9888 13:31:34.652946 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9889 13:31:34.656057 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9890 13:31:34.662927 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9891 13:31:34.666093 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9892 13:31:34.672978 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9893 13:31:34.676116 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9894 13:31:34.679560 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9895 13:31:34.685834 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9896 13:31:34.689245 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9897 13:31:34.695931 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9898 13:31:34.699383 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9899 13:31:34.706202 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9900 13:31:34.709551 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9901 13:31:34.715741 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9902 13:31:34.722455 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9903 13:31:34.725943 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9904 13:31:34.732288 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9905 13:31:34.735814 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9906 13:31:34.742223 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9907 13:31:34.745519 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9908 13:31:34.752484 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9909 13:31:34.755683 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9910 13:31:34.755804 INFO: [APUAPC] vio 0
9911 13:31:34.763106 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9912 13:31:34.766217 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9913 13:31:34.769668 INFO: [APUAPC] D0_APC_0: 0x400510
9914 13:31:34.773061 INFO: [APUAPC] D0_APC_1: 0x0
9915 13:31:34.776389 INFO: [APUAPC] D0_APC_2: 0x1540
9916 13:31:34.779450 INFO: [APUAPC] D0_APC_3: 0x0
9917 13:31:34.782786 INFO: [APUAPC] D1_APC_0: 0xffffffff
9918 13:31:34.786283 INFO: [APUAPC] D1_APC_1: 0xffffffff
9919 13:31:34.789799 INFO: [APUAPC] D1_APC_2: 0x3fffff
9920 13:31:34.793175 INFO: [APUAPC] D1_APC_3: 0x0
9921 13:31:34.796123 INFO: [APUAPC] D2_APC_0: 0xffffffff
9922 13:31:34.799347 INFO: [APUAPC] D2_APC_1: 0xffffffff
9923 13:31:34.802744 INFO: [APUAPC] D2_APC_2: 0x3fffff
9924 13:31:34.806069 INFO: [APUAPC] D2_APC_3: 0x0
9925 13:31:34.809437 INFO: [APUAPC] D3_APC_0: 0xffffffff
9926 13:31:34.812892 INFO: [APUAPC] D3_APC_1: 0xffffffff
9927 13:31:34.816449 INFO: [APUAPC] D3_APC_2: 0x3fffff
9928 13:31:34.819277 INFO: [APUAPC] D3_APC_3: 0x0
9929 13:31:34.823091 INFO: [APUAPC] D4_APC_0: 0xffffffff
9930 13:31:34.826361 INFO: [APUAPC] D4_APC_1: 0xffffffff
9931 13:31:34.829754 INFO: [APUAPC] D4_APC_2: 0x3fffff
9932 13:31:34.829850 INFO: [APUAPC] D4_APC_3: 0x0
9933 13:31:34.832699 INFO: [APUAPC] D5_APC_0: 0xffffffff
9934 13:31:34.836124 INFO: [APUAPC] D5_APC_1: 0xffffffff
9935 13:31:34.839481 INFO: [APUAPC] D5_APC_2: 0x3fffff
9936 13:31:34.842545 INFO: [APUAPC] D5_APC_3: 0x0
9937 13:31:34.846008 INFO: [APUAPC] D6_APC_0: 0xffffffff
9938 13:31:34.849162 INFO: [APUAPC] D6_APC_1: 0xffffffff
9939 13:31:34.852560 INFO: [APUAPC] D6_APC_2: 0x3fffff
9940 13:31:34.855951 INFO: [APUAPC] D6_APC_3: 0x0
9941 13:31:34.859437 INFO: [APUAPC] D7_APC_0: 0xffffffff
9942 13:31:34.862620 INFO: [APUAPC] D7_APC_1: 0xffffffff
9943 13:31:34.866339 INFO: [APUAPC] D7_APC_2: 0x3fffff
9944 13:31:34.869448 INFO: [APUAPC] D7_APC_3: 0x0
9945 13:31:34.872595 INFO: [APUAPC] D8_APC_0: 0xffffffff
9946 13:31:34.876047 INFO: [APUAPC] D8_APC_1: 0xffffffff
9947 13:31:34.879319 INFO: [APUAPC] D8_APC_2: 0x3fffff
9948 13:31:34.882799 INFO: [APUAPC] D8_APC_3: 0x0
9949 13:31:34.886126 INFO: [APUAPC] D9_APC_0: 0xffffffff
9950 13:31:34.889024 INFO: [APUAPC] D9_APC_1: 0xffffffff
9951 13:31:34.892571 INFO: [APUAPC] D9_APC_2: 0x3fffff
9952 13:31:34.895875 INFO: [APUAPC] D9_APC_3: 0x0
9953 13:31:34.899351 INFO: [APUAPC] D10_APC_0: 0xffffffff
9954 13:31:34.902639 INFO: [APUAPC] D10_APC_1: 0xffffffff
9955 13:31:34.905860 INFO: [APUAPC] D10_APC_2: 0x3fffff
9956 13:31:34.909178 INFO: [APUAPC] D10_APC_3: 0x0
9957 13:31:34.912668 INFO: [APUAPC] D11_APC_0: 0xffffffff
9958 13:31:34.915936 INFO: [APUAPC] D11_APC_1: 0xffffffff
9959 13:31:34.919052 INFO: [APUAPC] D11_APC_2: 0x3fffff
9960 13:31:34.922698 INFO: [APUAPC] D11_APC_3: 0x0
9961 13:31:34.925986 INFO: [APUAPC] D12_APC_0: 0xffffffff
9962 13:31:34.929680 INFO: [APUAPC] D12_APC_1: 0xffffffff
9963 13:31:34.932395 INFO: [APUAPC] D12_APC_2: 0x3fffff
9964 13:31:34.935772 INFO: [APUAPC] D12_APC_3: 0x0
9965 13:31:34.939283 INFO: [APUAPC] D13_APC_0: 0xffffffff
9966 13:31:34.942404 INFO: [APUAPC] D13_APC_1: 0xffffffff
9967 13:31:34.945881 INFO: [APUAPC] D13_APC_2: 0x3fffff
9968 13:31:34.949230 INFO: [APUAPC] D13_APC_3: 0x0
9969 13:31:34.952812 INFO: [APUAPC] D14_APC_0: 0xffffffff
9970 13:31:34.956010 INFO: [APUAPC] D14_APC_1: 0xffffffff
9971 13:31:34.958960 INFO: [APUAPC] D14_APC_2: 0x3fffff
9972 13:31:34.962448 INFO: [APUAPC] D14_APC_3: 0x0
9973 13:31:34.965930 INFO: [APUAPC] D15_APC_0: 0xffffffff
9974 13:31:34.968835 INFO: [APUAPC] D15_APC_1: 0xffffffff
9975 13:31:34.972468 INFO: [APUAPC] D15_APC_2: 0x3fffff
9976 13:31:34.975847 INFO: [APUAPC] D15_APC_3: 0x0
9977 13:31:34.978871 INFO: [APUAPC] APC_CON: 0x4
9978 13:31:34.982051 INFO: [NOCDAPC] D0_APC_0: 0x0
9979 13:31:34.985670 INFO: [NOCDAPC] D0_APC_1: 0x0
9980 13:31:34.988755 INFO: [NOCDAPC] D1_APC_0: 0x0
9981 13:31:34.992153 INFO: [NOCDAPC] D1_APC_1: 0xfff
9982 13:31:34.992253 INFO: [NOCDAPC] D2_APC_0: 0x0
9983 13:31:34.995541 INFO: [NOCDAPC] D2_APC_1: 0xfff
9984 13:31:34.998952 INFO: [NOCDAPC] D3_APC_0: 0x0
9985 13:31:35.002383 INFO: [NOCDAPC] D3_APC_1: 0xfff
9986 13:31:35.005727 INFO: [NOCDAPC] D4_APC_0: 0x0
9987 13:31:35.008925 INFO: [NOCDAPC] D4_APC_1: 0xfff
9988 13:31:35.012208 INFO: [NOCDAPC] D5_APC_0: 0x0
9989 13:31:35.015774 INFO: [NOCDAPC] D5_APC_1: 0xfff
9990 13:31:35.018819 INFO: [NOCDAPC] D6_APC_0: 0x0
9991 13:31:35.022448 INFO: [NOCDAPC] D6_APC_1: 0xfff
9992 13:31:35.022526 INFO: [NOCDAPC] D7_APC_0: 0x0
9993 13:31:35.025362 INFO: [NOCDAPC] D7_APC_1: 0xfff
9994 13:31:35.028946 INFO: [NOCDAPC] D8_APC_0: 0x0
9995 13:31:35.032076 INFO: [NOCDAPC] D8_APC_1: 0xfff
9996 13:31:35.035407 INFO: [NOCDAPC] D9_APC_0: 0x0
9997 13:31:35.038939 INFO: [NOCDAPC] D9_APC_1: 0xfff
9998 13:31:35.042239 INFO: [NOCDAPC] D10_APC_0: 0x0
9999 13:31:35.045659 INFO: [NOCDAPC] D10_APC_1: 0xfff
10000 13:31:35.049072 INFO: [NOCDAPC] D11_APC_0: 0x0
10001 13:31:35.051902 INFO: [NOCDAPC] D11_APC_1: 0xfff
10002 13:31:35.055338 INFO: [NOCDAPC] D12_APC_0: 0x0
10003 13:31:35.058447 INFO: [NOCDAPC] D12_APC_1: 0xfff
10004 13:31:35.061946 INFO: [NOCDAPC] D13_APC_0: 0x0
10005 13:31:35.065545 INFO: [NOCDAPC] D13_APC_1: 0xfff
10006 13:31:35.065654 INFO: [NOCDAPC] D14_APC_0: 0x0
10007 13:31:35.068411 INFO: [NOCDAPC] D14_APC_1: 0xfff
10008 13:31:35.072051 INFO: [NOCDAPC] D15_APC_0: 0x0
10009 13:31:35.075722 INFO: [NOCDAPC] D15_APC_1: 0xfff
10010 13:31:35.078407 INFO: [NOCDAPC] APC_CON: 0x4
10011 13:31:35.082222 INFO: [APUAPC] set_apusys_apc done
10012 13:31:35.085581 INFO: [DEVAPC] devapc_init done
10013 13:31:35.088793 INFO: GICv3 without legacy support detected.
10014 13:31:35.092000 INFO: ARM GICv3 driver initialized in EL3
10015 13:31:35.098705 INFO: Maximum SPI INTID supported: 639
10016 13:31:35.102269 INFO: BL31: Initializing runtime services
10017 13:31:35.108549 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10018 13:31:35.108657 INFO: SPM: enable CPC mode
10019 13:31:35.115315 INFO: mcdi ready for mcusys-off-idle and system suspend
10020 13:31:35.118621 INFO: BL31: Preparing for EL3 exit to normal world
10021 13:31:35.122020 INFO: Entry point address = 0x80000000
10022 13:31:35.125320 INFO: SPSR = 0x8
10023 13:31:35.131002
10024 13:31:35.131112
10025 13:31:35.131208
10026 13:31:35.134573 Starting depthcharge on Spherion...
10027 13:31:35.134658
10028 13:31:35.134724 Wipe memory regions:
10029 13:31:35.134786
10030 13:31:35.135408 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10031 13:31:35.135505 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10032 13:31:35.135591 Setting prompt string to ['asurada:']
10033 13:31:35.135667 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10034 13:31:35.137952 [0x00000040000000, 0x00000054600000)
10035 13:31:35.260398
10036 13:31:35.260578 [0x00000054660000, 0x00000080000000)
10037 13:31:35.520524
10038 13:31:35.520713 [0x000000821a7280, 0x000000ffe64000)
10039 13:31:36.265157
10040 13:31:36.265309 [0x00000100000000, 0x00000240000000)
10041 13:31:38.155248
10042 13:31:38.158571 Initializing XHCI USB controller at 0x11200000.
10043 13:31:39.197165
10044 13:31:39.200529 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10045 13:31:39.200637
10046 13:31:39.200730
10047 13:31:39.200839
10048 13:31:39.201144 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10050 13:31:39.301527 asurada: tftpboot 192.168.201.1 11471188/tftp-deploy-0wnm07x2/kernel/image.itb 11471188/tftp-deploy-0wnm07x2/kernel/cmdline
10051 13:31:39.301692 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10052 13:31:39.301832 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10053 13:31:39.306011 tftpboot 192.168.201.1 11471188/tftp-deploy-0wnm07x2/kernel/image.ittp-deploy-0wnm07x2/kernel/cmdline
10054 13:31:39.306100
10055 13:31:39.306202 Waiting for link
10056 13:31:39.466283
10057 13:31:39.466423 R8152: Initializing
10058 13:31:39.466498
10059 13:31:39.469722 Version 9 (ocp_data = 6010)
10060 13:31:39.469806
10061 13:31:39.473272 R8152: Done initializing
10062 13:31:39.473345
10063 13:31:39.473425 Adding net device
10064 13:31:41.418539
10065 13:31:41.418716 done.
10066 13:31:41.418831
10067 13:31:41.418926 MAC: 00:e0:4c:72:2d:d6
10068 13:31:41.419021
10069 13:31:41.422339 Sending DHCP discover... done.
10070 13:31:41.422482
10071 13:31:41.425749 Waiting for reply... done.
10072 13:31:41.425851
10073 13:31:41.428622 Sending DHCP request... done.
10074 13:31:41.428734
10075 13:31:41.428823 Waiting for reply... done.
10076 13:31:41.428889
10077 13:31:41.432145 My ip is 192.168.201.21
10078 13:31:41.432231
10079 13:31:41.435163 The DHCP server ip is 192.168.201.1
10080 13:31:41.435276
10081 13:31:41.438394 TFTP server IP predefined by user: 192.168.201.1
10082 13:31:41.438509
10083 13:31:41.444986 Bootfile predefined by user: 11471188/tftp-deploy-0wnm07x2/kernel/image.itb
10084 13:31:41.445076
10085 13:31:41.448458 Sending tftp read request... done.
10086 13:31:41.448567
10087 13:31:41.451930 Waiting for the transfer...
10088 13:31:41.452013
10089 13:31:41.711678 00000000 ################################################################
10090 13:31:41.711839
10091 13:31:41.965105 00080000 ################################################################
10092 13:31:41.965298
10093 13:31:42.216397 00100000 ################################################################
10094 13:31:42.216559
10095 13:31:42.463121 00180000 ################################################################
10096 13:31:42.463253
10097 13:31:42.711238 00200000 ################################################################
10098 13:31:42.711427
10099 13:31:42.963573 00280000 ################################################################
10100 13:31:42.963798
10101 13:31:43.212333 00300000 ################################################################
10102 13:31:43.212499
10103 13:31:43.452867 00380000 ################################################################
10104 13:31:43.453020
10105 13:31:43.699901 00400000 ################################################################
10106 13:31:43.700062
10107 13:31:43.948603 00480000 ################################################################
10108 13:31:43.948792
10109 13:31:44.208723 00500000 ################################################################
10110 13:31:44.208876
10111 13:31:44.462234 00580000 ################################################################
10112 13:31:44.462439
10113 13:31:44.712635 00600000 ################################################################
10114 13:31:44.712816
10115 13:31:44.964846 00680000 ################################################################
10116 13:31:44.965030
10117 13:31:45.210857 00700000 ################################################################
10118 13:31:45.211028
10119 13:31:45.524804 00780000 ################################################################
10120 13:31:45.524957
10121 13:31:45.867499 00800000 ################################################################
10122 13:31:45.867663
10123 13:31:46.184004 00880000 ################################################################
10124 13:31:46.184169
10125 13:31:46.434559 00900000 ################################################################
10126 13:31:46.434699
10127 13:31:46.703263 00980000 ################################################################
10128 13:31:46.703444
10129 13:31:46.967153 00a00000 ################################################################
10130 13:31:46.967309
10131 13:31:47.225541 00a80000 ################################################################
10132 13:31:47.225718
10133 13:31:47.480789 00b00000 ################################################################
10134 13:31:47.480932
10135 13:31:47.729243 00b80000 ################################################################
10136 13:31:47.729390
10137 13:31:47.986241 00c00000 ################################################################
10138 13:31:47.986399
10139 13:31:48.230592 00c80000 ################################################################
10140 13:31:48.230738
10141 13:31:48.481929 00d00000 ################################################################
10142 13:31:48.482082
10143 13:31:48.728173 00d80000 ################################################################
10144 13:31:48.728328
10145 13:31:48.976115 00e00000 ################################################################
10146 13:31:48.976270
10147 13:31:49.221205 00e80000 ################################################################
10148 13:31:49.221341
10149 13:31:49.492206 00f00000 ################################################################
10150 13:31:49.492401
10151 13:31:49.760340 00f80000 ################################################################
10152 13:31:49.760483
10153 13:31:50.017458 01000000 ################################################################
10154 13:31:50.017658
10155 13:31:50.292191 01080000 ################################################################
10156 13:31:50.292362
10157 13:31:50.583228 01100000 ################################################################
10158 13:31:50.583405
10159 13:31:50.902062 01180000 ################################################################
10160 13:31:50.902278
10161 13:31:51.147421 01200000 ################################################################
10162 13:31:51.147583
10163 13:31:51.405495 01280000 ################################################################
10164 13:31:51.405673
10165 13:31:51.666581 01300000 ################################################################
10166 13:31:51.666791
10167 13:31:51.947974 01380000 ################################################################
10168 13:31:51.948139
10169 13:31:52.230694 01400000 ################################################################
10170 13:31:52.230850
10171 13:31:52.498920 01480000 ################################################################
10172 13:31:52.499092
10173 13:31:52.781572 01500000 ################################################################
10174 13:31:52.781776
10175 13:31:53.047759 01580000 ################################################################
10176 13:31:53.047903
10177 13:31:53.300509 01600000 ################################################################
10178 13:31:53.300685
10179 13:31:53.547503 01680000 ################################################################
10180 13:31:53.547701
10181 13:31:53.795066 01700000 ################################################################
10182 13:31:53.795211
10183 13:31:54.044144 01780000 ################################################################
10184 13:31:54.044344
10185 13:31:54.295666 01800000 ################################################################
10186 13:31:54.295836
10187 13:31:54.543061 01880000 ################################################################
10188 13:31:54.543241
10189 13:31:54.788973 01900000 ################################################################
10190 13:31:54.789181
10191 13:31:55.035250 01980000 ################################################################
10192 13:31:55.035414
10193 13:31:55.286039 01a00000 ################################################################
10194 13:31:55.286183
10195 13:31:55.533446 01a80000 ################################################################
10196 13:31:55.533593
10197 13:31:55.867145 01b00000 ################################################################
10198 13:31:55.867330
10199 13:31:56.206549 01b80000 ################################################################
10200 13:31:56.206713
10201 13:31:56.512138 01c00000 ################################################################
10202 13:31:56.512331
10203 13:31:56.762468 01c80000 ################################################################
10204 13:31:56.762608
10205 13:31:57.024510 01d00000 ################################################################
10206 13:31:57.024676
10207 13:31:57.293132 01d80000 ################################################################
10208 13:31:57.293273
10209 13:31:57.548731 01e00000 ################################################################
10210 13:31:57.549063
10211 13:31:57.807477 01e80000 ################################################################
10212 13:31:57.807644
10213 13:31:58.066155 01f00000 ################################################################
10214 13:31:58.066327
10215 13:31:58.314182 01f80000 ################################################################
10216 13:31:58.314345
10217 13:31:58.559580 02000000 ################################################################
10218 13:31:58.559769
10219 13:31:58.806116 02080000 ################################################################
10220 13:31:58.806316
10221 13:31:59.058370 02100000 ################################################################
10222 13:31:59.058512
10223 13:31:59.307505 02180000 ################################################################
10224 13:31:59.307672
10225 13:31:59.555510 02200000 ################################################################
10226 13:31:59.555678
10227 13:31:59.807900 02280000 ################################################################
10228 13:31:59.808064
10229 13:32:00.059990 02300000 ################################################################
10230 13:32:00.060157
10231 13:32:00.308055 02380000 ################################################################
10232 13:32:00.308199
10233 13:32:00.556905 02400000 ################################################################
10234 13:32:00.557039
10235 13:32:00.865556 02480000 ################################################################
10236 13:32:00.865700
10237 13:32:01.175299 02500000 ################################################################
10238 13:32:01.175453
10239 13:32:01.423783 02580000 ################################################################
10240 13:32:01.423955
10241 13:32:01.675830 02600000 ################################################################
10242 13:32:01.676026
10243 13:32:01.938602 02680000 ################################################################
10244 13:32:01.938773
10245 13:32:02.186285 02700000 ################################################################
10246 13:32:02.186469
10247 13:32:02.431360 02780000 ################################################################
10248 13:32:02.431523
10249 13:32:02.683807 02800000 ################################################################
10250 13:32:02.683978
10251 13:32:02.927283 02880000 ################################################################
10252 13:32:02.927447
10253 13:32:03.174289 02900000 ################################################################
10254 13:32:03.174476
10255 13:32:03.417059 02980000 ################################################################
10256 13:32:03.417211
10257 13:32:03.673345 02a00000 ################################################################
10258 13:32:03.673507
10259 13:32:03.923603 02a80000 ################################################################
10260 13:32:03.923781
10261 13:32:04.170286 02b00000 ################################################################
10262 13:32:04.170493
10263 13:32:04.416847 02b80000 ################################################################
10264 13:32:04.417000
10265 13:32:04.666724 02c00000 ################################################################
10266 13:32:04.666863
10267 13:32:04.918524 02c80000 ################################################################
10268 13:32:04.918665
10269 13:32:05.169139 02d00000 ################################################################
10270 13:32:05.169284
10271 13:32:05.429907 02d80000 ################################################################
10272 13:32:05.430100
10273 13:32:05.688339 02e00000 ################################################################
10274 13:32:05.688533
10275 13:32:05.959633 02e80000 ################################################################
10276 13:32:05.959836
10277 13:32:06.211688 02f00000 ################################################################
10278 13:32:06.211841
10279 13:32:06.459581 02f80000 ################################################################
10280 13:32:06.459785
10281 13:32:06.716004 03000000 ################################################################
10282 13:32:06.716208
10283 13:32:06.967852 03080000 ################################################################
10284 13:32:06.968046
10285 13:32:07.218517 03100000 ################################################################
10286 13:32:07.218668
10287 13:32:07.467790 03180000 ################################################################
10288 13:32:07.467999
10289 13:32:07.724839 03200000 ################################################################
10290 13:32:07.724983
10291 13:32:07.978811 03280000 ################################################################
10292 13:32:07.978953
10293 13:32:08.229158 03300000 ################################################################
10294 13:32:08.229296
10295 13:32:08.479268 03380000 ################################################################
10296 13:32:08.479442
10297 13:32:08.730978 03400000 ################################################################
10298 13:32:08.731187
10299 13:32:08.978619 03480000 ################################################################
10300 13:32:08.978763
10301 13:32:09.225951 03500000 ################################################################
10302 13:32:09.226100
10303 13:32:09.472292 03580000 ################################################################
10304 13:32:09.472492
10305 13:32:09.723405 03600000 ################################################################
10306 13:32:09.723551
10307 13:32:09.974937 03680000 ################################################################
10308 13:32:09.975127
10309 13:32:10.232048 03700000 ################################################################
10310 13:32:10.232199
10311 13:32:10.429320 03780000 ################################################## done.
10312 13:32:10.429466
10313 13:32:10.432421 The bootfile was 58604522 bytes long.
10314 13:32:10.432552
10315 13:32:10.435533 Sending tftp read request... done.
10316 13:32:10.435658
10317 13:32:10.435772 Waiting for the transfer...
10318 13:32:10.435883
10319 13:32:10.439524 00000000 # done.
10320 13:32:10.439654
10321 13:32:10.446087 Command line loaded dynamically from TFTP file: 11471188/tftp-deploy-0wnm07x2/kernel/cmdline
10322 13:32:10.446214
10323 13:32:10.459145 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10324 13:32:10.459231
10325 13:32:10.462634 Loading FIT.
10326 13:32:10.462718
10327 13:32:10.465921 Image ramdisk-1 has 47515113 bytes.
10328 13:32:10.466006
10329 13:32:10.466071 Image fdt-1 has 47278 bytes.
10330 13:32:10.468911
10331 13:32:10.468994 Image kernel-1 has 11040095 bytes.
10332 13:32:10.469061
10333 13:32:10.478928 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10334 13:32:10.479013
10335 13:32:10.495124 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10336 13:32:10.498560
10337 13:32:10.501995 Choosing best match conf-1 for compat google,spherion-rev2.
10338 13:32:10.506295
10339 13:32:10.510682 Connected to device vid:did:rid of 1ae0:0028:00
10340 13:32:10.518181
10341 13:32:10.521176 tpm_get_response: command 0x17b, return code 0x0
10342 13:32:10.521264
10343 13:32:10.524457 ec_init: CrosEC protocol v3 supported (256, 248)
10344 13:32:10.528147
10345 13:32:10.531924 tpm_cleanup: add release locality here.
10346 13:32:10.532023
10347 13:32:10.532103 Shutting down all USB controllers.
10348 13:32:10.535180
10349 13:32:10.535263 Removing current net device
10350 13:32:10.535329
10351 13:32:10.542205 Exiting depthcharge with code 4 at timestamp: 64727272
10352 13:32:10.542295
10353 13:32:10.544959 LZMA decompressing kernel-1 to 0x821a6718
10354 13:32:10.545043
10355 13:32:10.548525 LZMA decompressing kernel-1 to 0x40000000
10356 13:32:11.936101
10357 13:32:11.936251 jumping to kernel
10358 13:32:11.936681 end: 2.2.4 bootloader-commands (duration 00:00:37) [common]
10359 13:32:11.936817 start: 2.2.5 auto-login-action (timeout 00:03:48) [common]
10360 13:32:11.936895 Setting prompt string to ['Linux version [0-9]']
10361 13:32:11.936963 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10362 13:32:11.937071 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10363 13:32:12.017898
10364 13:32:12.021050 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10365 13:32:12.024702 start: 2.2.5.1 login-action (timeout 00:03:48) [common]
10366 13:32:12.024830 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10367 13:32:12.024902 Setting prompt string to []
10368 13:32:12.024979 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10369 13:32:12.025050 Using line separator: #'\n'#
10370 13:32:12.025108 No login prompt set.
10371 13:32:12.025169 Parsing kernel messages
10372 13:32:12.025224 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10373 13:32:12.025324 [login-action] Waiting for messages, (timeout 00:03:48)
10374 13:32:12.044664 [ 0.000000] Linux version 6.1.52-cip5 (KernelCI@build-j38933-arm64-gcc-10-defconfig-arm64-chromebook-kgx6p) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Sep 8 13:10:51 UTC 2023
10375 13:32:12.047766 [ 0.000000] random: crng init done
10376 13:32:12.054412 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10377 13:32:12.054495 [ 0.000000] efi: UEFI not found.
10378 13:32:12.064266 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10379 13:32:12.071267 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10380 13:32:12.080876 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10381 13:32:12.090926 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10382 13:32:12.097609 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10383 13:32:12.100953 [ 0.000000] printk: bootconsole [mtk8250] enabled
10384 13:32:12.109350 [ 0.000000] NUMA: No NUMA configuration found
10385 13:32:12.116011 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10386 13:32:12.122698 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10387 13:32:12.122781 [ 0.000000] Zone ranges:
10388 13:32:12.129817 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10389 13:32:12.132605 [ 0.000000] DMA32 empty
10390 13:32:12.139465 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10391 13:32:12.142826 [ 0.000000] Movable zone start for each node
10392 13:32:12.146189 [ 0.000000] Early memory node ranges
10393 13:32:12.152542 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10394 13:32:12.159321 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10395 13:32:12.165956 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10396 13:32:12.172518 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10397 13:32:12.179037 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10398 13:32:12.185479 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10399 13:32:12.242191 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10400 13:32:12.248969 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10401 13:32:12.255823 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10402 13:32:12.258729 [ 0.000000] psci: probing for conduit method from DT.
10403 13:32:12.265609 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10404 13:32:12.269081 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10405 13:32:12.275564 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10406 13:32:12.278675 [ 0.000000] psci: SMC Calling Convention v1.2
10407 13:32:12.285355 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10408 13:32:12.288576 [ 0.000000] Detected VIPT I-cache on CPU0
10409 13:32:12.295109 [ 0.000000] CPU features: detected: GIC system register CPU interface
10410 13:32:12.301954 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10411 13:32:12.308446 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10412 13:32:12.315221 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10413 13:32:12.321678 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10414 13:32:12.331929 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10415 13:32:12.335026 [ 0.000000] alternatives: applying boot alternatives
10416 13:32:12.341807 [ 0.000000] Fallback order for Node 0: 0
10417 13:32:12.348236 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10418 13:32:12.351527 [ 0.000000] Policy zone: Normal
10419 13:32:12.364957 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10420 13:32:12.375432 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10421 13:32:12.385702 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10422 13:32:12.395437 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10423 13:32:12.402247 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10424 13:32:12.405602 <6>[ 0.000000] software IO TLB: area num 8.
10425 13:32:12.462060 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10426 13:32:12.611205 <6>[ 0.000000] Memory: 7923092K/8385536K available (17984K kernel code, 4098K rwdata, 17468K rodata, 8384K init, 616K bss, 429676K reserved, 32768K cma-reserved)
10427 13:32:12.617578 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10428 13:32:12.624178 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10429 13:32:12.627671 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10430 13:32:12.634155 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10431 13:32:12.640970 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10432 13:32:12.644279 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10433 13:32:12.653974 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10434 13:32:12.660947 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10435 13:32:12.667449 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10436 13:32:12.674327 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10437 13:32:12.677589 <6>[ 0.000000] GICv3: 608 SPIs implemented
10438 13:32:12.680548 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10439 13:32:12.687126 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10440 13:32:12.690826 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10441 13:32:12.697540 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10442 13:32:12.710427 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10443 13:32:12.720708 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10444 13:32:12.730319 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10445 13:32:12.737720 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10446 13:32:12.750911 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10447 13:32:12.757745 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10448 13:32:12.763905 <6>[ 0.009184] Console: colour dummy device 80x25
10449 13:32:12.774243 <6>[ 0.013913] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10450 13:32:12.780587 <6>[ 0.024354] pid_max: default: 32768 minimum: 301
10451 13:32:12.784027 <6>[ 0.029225] LSM: Security Framework initializing
10452 13:32:12.790824 <6>[ 0.034164] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10453 13:32:12.800395 <6>[ 0.041979] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10454 13:32:12.807221 <6>[ 0.051390] cblist_init_generic: Setting adjustable number of callback queues.
10455 13:32:12.813842 <6>[ 0.058832] cblist_init_generic: Setting shift to 3 and lim to 1.
10456 13:32:12.823926 <6>[ 0.065169] cblist_init_generic: Setting adjustable number of callback queues.
10457 13:32:12.827281 <6>[ 0.072596] cblist_init_generic: Setting shift to 3 and lim to 1.
10458 13:32:12.833979 <6>[ 0.078985] rcu: Hierarchical SRCU implementation.
10459 13:32:12.840698 <6>[ 0.084000] rcu: Max phase no-delay instances is 1000.
10460 13:32:12.847356 <6>[ 0.091032] EFI services will not be available.
10461 13:32:12.850691 <6>[ 0.095959] smp: Bringing up secondary CPUs ...
10462 13:32:12.858139 <6>[ 0.101036] Detected VIPT I-cache on CPU1
10463 13:32:12.865132 <6>[ 0.101105] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10464 13:32:12.871631 <6>[ 0.101135] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10465 13:32:12.874930 <6>[ 0.101475] Detected VIPT I-cache on CPU2
10466 13:32:12.881687 <6>[ 0.101524] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10467 13:32:12.891505 <6>[ 0.101540] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10468 13:32:12.894768 <6>[ 0.101795] Detected VIPT I-cache on CPU3
10469 13:32:12.901600 <6>[ 0.101840] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10470 13:32:12.908144 <6>[ 0.101854] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10471 13:32:12.911269 <6>[ 0.102158] CPU features: detected: Spectre-v4
10472 13:32:12.917973 <6>[ 0.102164] CPU features: detected: Spectre-BHB
10473 13:32:12.921185 <6>[ 0.102169] Detected PIPT I-cache on CPU4
10474 13:32:12.927646 <6>[ 0.102226] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10475 13:32:12.934545 <6>[ 0.102243] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10476 13:32:12.940943 <6>[ 0.102537] Detected PIPT I-cache on CPU5
10477 13:32:12.947661 <6>[ 0.102600] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10478 13:32:12.954499 <6>[ 0.102617] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10479 13:32:12.957719 <6>[ 0.102901] Detected PIPT I-cache on CPU6
10480 13:32:12.964639 <6>[ 0.102967] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10481 13:32:12.971082 <6>[ 0.102984] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10482 13:32:12.977859 <6>[ 0.103280] Detected PIPT I-cache on CPU7
10483 13:32:12.984151 <6>[ 0.103346] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10484 13:32:12.990969 <6>[ 0.103362] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10485 13:32:12.994517 <6>[ 0.103411] smp: Brought up 1 node, 8 CPUs
10486 13:32:13.000768 <6>[ 0.244736] SMP: Total of 8 processors activated.
10487 13:32:13.004271 <6>[ 0.249688] CPU features: detected: 32-bit EL0 Support
10488 13:32:13.014060 <6>[ 0.255083] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10489 13:32:13.020582 <6>[ 0.263884] CPU features: detected: Common not Private translations
10490 13:32:13.024188 <6>[ 0.270360] CPU features: detected: CRC32 instructions
10491 13:32:13.030548 <6>[ 0.275711] CPU features: detected: RCpc load-acquire (LDAPR)
10492 13:32:13.037231 <6>[ 0.281671] CPU features: detected: LSE atomic instructions
10493 13:32:13.043943 <6>[ 0.287452] CPU features: detected: Privileged Access Never
10494 13:32:13.047247 <6>[ 0.293232] CPU features: detected: RAS Extension Support
10495 13:32:13.057133 <6>[ 0.298840] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10496 13:32:13.060473 <6>[ 0.306108] CPU: All CPU(s) started at EL2
10497 13:32:13.066992 <6>[ 0.310425] alternatives: applying system-wide alternatives
10498 13:32:13.075907 <6>[ 0.321142] devtmpfs: initialized
10499 13:32:13.088127 <6>[ 0.329962] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10500 13:32:13.098241 <6>[ 0.339925] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10501 13:32:13.101431 <6>[ 0.347525] pinctrl core: initialized pinctrl subsystem
10502 13:32:13.108823 <6>[ 0.354146] DMI not present or invalid.
10503 13:32:13.115873 <6>[ 0.358560] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10504 13:32:13.122474 <6>[ 0.365425] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10505 13:32:13.132077 <6>[ 0.373010] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10506 13:32:13.138804 <6>[ 0.381233] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10507 13:32:13.145673 <6>[ 0.389475] audit: initializing netlink subsys (disabled)
10508 13:32:13.152483 <5>[ 0.395167] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10509 13:32:13.159251 <6>[ 0.395857] thermal_sys: Registered thermal governor 'step_wise'
10510 13:32:13.165398 <6>[ 0.403135] thermal_sys: Registered thermal governor 'power_allocator'
10511 13:32:13.169164 <6>[ 0.409392] cpuidle: using governor menu
10512 13:32:13.175614 <6>[ 0.420355] NET: Registered PF_QIPCRTR protocol family
10513 13:32:13.182197 <6>[ 0.425838] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10514 13:32:13.189158 <6>[ 0.432943] ASID allocator initialised with 32768 entries
10515 13:32:13.191990 <6>[ 0.439504] Serial: AMBA PL011 UART driver
10516 13:32:13.203352 <4>[ 0.448215] Trying to register duplicate clock ID: 134
10517 13:32:13.257003 <6>[ 0.505612] KASLR enabled
10518 13:32:13.271862 <6>[ 0.513337] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10519 13:32:13.278012 <6>[ 0.520349] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10520 13:32:13.284790 <6>[ 0.526839] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10521 13:32:13.291412 <6>[ 0.533844] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10522 13:32:13.297851 <6>[ 0.540332] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10523 13:32:13.304674 <6>[ 0.547335] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10524 13:32:13.311548 <6>[ 0.553823] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10525 13:32:13.318145 <6>[ 0.560827] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10526 13:32:13.321361 <6>[ 0.568334] ACPI: Interpreter disabled.
10527 13:32:13.329628 <6>[ 0.574753] iommu: Default domain type: Translated
10528 13:32:13.336307 <6>[ 0.579864] iommu: DMA domain TLB invalidation policy: strict mode
10529 13:32:13.339691 <5>[ 0.586512] SCSI subsystem initialized
10530 13:32:13.346210 <6>[ 0.590671] usbcore: registered new interface driver usbfs
10531 13:32:13.352681 <6>[ 0.596403] usbcore: registered new interface driver hub
10532 13:32:13.356105 <6>[ 0.601956] usbcore: registered new device driver usb
10533 13:32:13.362881 <6>[ 0.608043] pps_core: LinuxPPS API ver. 1 registered
10534 13:32:13.372729 <6>[ 0.613237] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10535 13:32:13.376405 <6>[ 0.622585] PTP clock support registered
10536 13:32:13.379310 <6>[ 0.626827] EDAC MC: Ver: 3.0.0
10537 13:32:13.386719 <6>[ 0.631973] FPGA manager framework
10538 13:32:13.393471 <6>[ 0.635651] Advanced Linux Sound Architecture Driver Initialized.
10539 13:32:13.396551 <6>[ 0.642419] vgaarb: loaded
10540 13:32:13.403498 <6>[ 0.645591] clocksource: Switched to clocksource arch_sys_counter
10541 13:32:13.406490 <5>[ 0.652019] VFS: Disk quotas dquot_6.6.0
10542 13:32:13.413279 <6>[ 0.656204] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10543 13:32:13.416705 <6>[ 0.663389] pnp: PnP ACPI: disabled
10544 13:32:13.425188 <6>[ 0.670053] NET: Registered PF_INET protocol family
10545 13:32:13.435033 <6>[ 0.675638] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10546 13:32:13.445955 <6>[ 0.687935] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10547 13:32:13.456346 <6>[ 0.696748] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10548 13:32:13.462450 <6>[ 0.704718] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10549 13:32:13.469142 <6>[ 0.713418] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10550 13:32:13.481306 <6>[ 0.723169] TCP: Hash tables configured (established 65536 bind 65536)
10551 13:32:13.487900 <6>[ 0.730027] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10552 13:32:13.494426 <6>[ 0.737227] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10553 13:32:13.501136 <6>[ 0.744922] NET: Registered PF_UNIX/PF_LOCAL protocol family
10554 13:32:13.507546 <6>[ 0.751064] RPC: Registered named UNIX socket transport module.
10555 13:32:13.510842 <6>[ 0.757216] RPC: Registered udp transport module.
10556 13:32:13.517766 <6>[ 0.762148] RPC: Registered tcp transport module.
10557 13:32:13.524081 <6>[ 0.767080] RPC: Registered tcp NFSv4.1 backchannel transport module.
10558 13:32:13.527915 <6>[ 0.773749] PCI: CLS 0 bytes, default 64
10559 13:32:13.531142 <6>[ 0.778140] Unpacking initramfs...
10560 13:32:13.548468 <6>[ 0.790210] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10561 13:32:13.558114 <6>[ 0.798872] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10562 13:32:13.561525 <6>[ 0.807731] kvm [1]: IPA Size Limit: 40 bits
10563 13:32:13.568244 <6>[ 0.812260] kvm [1]: GICv3: no GICV resource entry
10564 13:32:13.571846 <6>[ 0.817281] kvm [1]: disabling GICv2 emulation
10565 13:32:13.577932 <6>[ 0.821969] kvm [1]: GIC system register CPU interface enabled
10566 13:32:13.581391 <6>[ 0.828165] kvm [1]: vgic interrupt IRQ18
10567 13:32:13.587960 <6>[ 0.832574] kvm [1]: VHE mode initialized successfully
10568 13:32:13.594625 <5>[ 0.839101] Initialise system trusted keyrings
10569 13:32:13.601090 <6>[ 0.843921] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10570 13:32:13.608675 <6>[ 0.854073] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10571 13:32:13.615503 <5>[ 0.860515] NFS: Registering the id_resolver key type
10572 13:32:13.618946 <5>[ 0.865819] Key type id_resolver registered
10573 13:32:13.625783 <5>[ 0.870233] Key type id_legacy registered
10574 13:32:13.632041 <6>[ 0.874513] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10575 13:32:13.638825 <6>[ 0.881433] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10576 13:32:13.645471 <6>[ 0.889195] 9p: Installing v9fs 9p2000 file system support
10577 13:32:13.681967 <5>[ 0.927221] Key type asymmetric registered
10578 13:32:13.685323 <5>[ 0.931550] Asymmetric key parser 'x509' registered
10579 13:32:13.695302 <6>[ 0.936705] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10580 13:32:13.698697 <6>[ 0.944318] io scheduler mq-deadline registered
10581 13:32:13.702015 <6>[ 0.949080] io scheduler kyber registered
10582 13:32:13.721025 <6>[ 0.966041] EINJ: ACPI disabled.
10583 13:32:13.753050 <4>[ 0.991430] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10584 13:32:13.762878 <4>[ 1.002044] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10585 13:32:13.777493 <6>[ 1.022669] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10586 13:32:13.785406 <6>[ 1.030640] printk: console [ttyS0] disabled
10587 13:32:13.813412 <6>[ 1.055284] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10588 13:32:13.820138 <6>[ 1.064757] printk: console [ttyS0] enabled
10589 13:32:13.823619 <6>[ 1.064757] printk: console [ttyS0] enabled
10590 13:32:13.829963 <6>[ 1.073651] printk: bootconsole [mtk8250] disabled
10591 13:32:13.833392 <6>[ 1.073651] printk: bootconsole [mtk8250] disabled
10592 13:32:13.839888 <6>[ 1.084848] SuperH (H)SCI(F) driver initialized
10593 13:32:13.843146 <6>[ 1.090115] msm_serial: driver initialized
10594 13:32:13.857613 <6>[ 1.099045] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10595 13:32:13.867379 <6>[ 1.107592] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10596 13:32:13.874190 <6>[ 1.116134] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10597 13:32:13.883989 <6>[ 1.124761] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10598 13:32:13.890295 <6>[ 1.133468] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10599 13:32:13.900481 <6>[ 1.142180] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10600 13:32:13.910124 <6>[ 1.150727] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10601 13:32:13.917426 <6>[ 1.159545] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10602 13:32:13.926955 <6>[ 1.168090] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10603 13:32:13.935523 <6>[ 1.183694] loop: module loaded
10604 13:32:13.944603 <6>[ 1.189687] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10605 13:32:13.967613 <4>[ 1.213012] mtk-pmic-keys: Failed to locate of_node [id: -1]
10606 13:32:13.974632 <6>[ 1.219818] megasas: 07.719.03.00-rc1
10607 13:32:13.984342 <6>[ 1.229306] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10608 13:32:13.991873 <6>[ 1.236966] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10609 13:32:14.008278 <6>[ 1.253484] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10610 13:32:14.064142 <6>[ 1.302573] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10611 13:32:15.553250 <6>[ 2.798571] Freeing initrd memory: 46396K
10612 13:32:15.563367 <6>[ 2.808988] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10613 13:32:15.574623 <6>[ 2.819877] tun: Universal TUN/TAP device driver, 1.6
10614 13:32:15.577527 <6>[ 2.825950] thunder_xcv, ver 1.0
10615 13:32:15.580997 <6>[ 2.829448] thunder_bgx, ver 1.0
10616 13:32:15.584415 <6>[ 2.832945] nicpf, ver 1.0
10617 13:32:15.595058 <6>[ 2.836946] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10618 13:32:15.598474 <6>[ 2.844422] hns3: Copyright (c) 2017 Huawei Corporation.
10619 13:32:15.601503 <6>[ 2.850011] hclge is initializing
10620 13:32:15.608016 <6>[ 2.853594] e1000: Intel(R) PRO/1000 Network Driver
10621 13:32:15.614613 <6>[ 2.858724] e1000: Copyright (c) 1999-2006 Intel Corporation.
10622 13:32:15.617824 <6>[ 2.864737] e1000e: Intel(R) PRO/1000 Network Driver
10623 13:32:15.624902 <6>[ 2.869952] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10624 13:32:15.631518 <6>[ 2.876139] igb: Intel(R) Gigabit Ethernet Network Driver
10625 13:32:15.637805 <6>[ 2.881789] igb: Copyright (c) 2007-2014 Intel Corporation.
10626 13:32:15.644561 <6>[ 2.887628] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10627 13:32:15.651420 <6>[ 2.894162] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10628 13:32:15.654249 <6>[ 2.900628] sky2: driver version 1.30
10629 13:32:15.661001 <6>[ 2.905622] VFIO - User Level meta-driver version: 0.3
10630 13:32:15.668298 <6>[ 2.913845] usbcore: registered new interface driver usb-storage
10631 13:32:15.675143 <6>[ 2.920290] usbcore: registered new device driver onboard-usb-hub
10632 13:32:15.683768 <6>[ 2.929358] mt6397-rtc mt6359-rtc: registered as rtc0
10633 13:32:15.694155 <6>[ 2.934827] mt6397-rtc mt6359-rtc: setting system clock to 2023-09-08T13:32:14 UTC (1694179934)
10634 13:32:15.697072 <6>[ 2.944385] i2c_dev: i2c /dev entries driver
10635 13:32:15.713938 <6>[ 2.956008] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10636 13:32:15.733615 <6>[ 2.978989] cpu cpu0: EM: created perf domain
10637 13:32:15.736960 <6>[ 2.983917] cpu cpu4: EM: created perf domain
10638 13:32:15.744334 <6>[ 2.989492] sdhci: Secure Digital Host Controller Interface driver
10639 13:32:15.750655 <6>[ 2.995924] sdhci: Copyright(c) Pierre Ossman
10640 13:32:15.757371 <6>[ 3.000882] Synopsys Designware Multimedia Card Interface Driver
10641 13:32:15.763883 <6>[ 3.007521] sdhci-pltfm: SDHCI platform and OF driver helper
10642 13:32:15.767384 <6>[ 3.007599] mmc0: CQHCI version 5.10
10643 13:32:15.773774 <6>[ 3.017993] ledtrig-cpu: registered to indicate activity on CPUs
10644 13:32:15.780743 <6>[ 3.025055] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10645 13:32:15.787012 <6>[ 3.032114] usbcore: registered new interface driver usbhid
10646 13:32:15.790433 <6>[ 3.037937] usbhid: USB HID core driver
10647 13:32:15.800203 <6>[ 3.042143] spi_master spi0: will run message pump with realtime priority
10648 13:32:15.839411 <6>[ 3.078283] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10649 13:32:15.858540 <6>[ 3.093377] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10650 13:32:15.864951 <6>[ 3.108160] cros-ec-spi spi0.0: Chrome EC device registered
10651 13:32:15.868478 <6>[ 3.114184] mmc0: Command Queue Engine enabled
10652 13:32:15.874684 <6>[ 3.118926] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10653 13:32:15.881180 <6>[ 3.126436] mmcblk0: mmc0:0001 DA4128 116 GiB
10654 13:32:15.891547 <6>[ 3.136961] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10655 13:32:15.901624 <6>[ 3.141123] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10656 13:32:15.908269 <6>[ 3.144290] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10657 13:32:15.911785 <6>[ 3.153413] NET: Registered PF_PACKET protocol family
10658 13:32:15.918166 <6>[ 3.158121] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10659 13:32:15.921408 <6>[ 3.162764] 9pnet: Installing 9P2000 support
10660 13:32:15.928106 <6>[ 3.168607] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10661 13:32:15.934560 <5>[ 3.172489] Key type dns_resolver registered
10662 13:32:15.937701 <6>[ 3.183942] registered taskstats version 1
10663 13:32:15.944642 <5>[ 3.188321] Loading compiled-in X.509 certificates
10664 13:32:15.971986 <4>[ 3.210626] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10665 13:32:15.981846 <4>[ 3.221367] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10666 13:32:15.988431 <3>[ 3.231900] debugfs: File 'uA_load' in directory '/' already present!
10667 13:32:15.995029 <3>[ 3.238661] debugfs: File 'min_uV' in directory '/' already present!
10668 13:32:16.002024 <3>[ 3.245285] debugfs: File 'max_uV' in directory '/' already present!
10669 13:32:16.008521 <3>[ 3.251897] debugfs: File 'constraint_flags' in directory '/' already present!
10670 13:32:16.019507 <3>[ 3.261561] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10671 13:32:16.030110 <6>[ 3.275661] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10672 13:32:16.037202 <6>[ 3.282583] xhci-mtk 11200000.usb: xHCI Host Controller
10673 13:32:16.043742 <6>[ 3.288081] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10674 13:32:16.054039 <6>[ 3.295953] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10675 13:32:16.060496 <6>[ 3.305399] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10676 13:32:16.066956 <6>[ 3.311488] xhci-mtk 11200000.usb: xHCI Host Controller
10677 13:32:16.073882 <6>[ 3.316971] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10678 13:32:16.080025 <6>[ 3.324625] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10679 13:32:16.086872 <6>[ 3.332339] hub 1-0:1.0: USB hub found
10680 13:32:16.090280 <6>[ 3.336352] hub 1-0:1.0: 1 port detected
10681 13:32:16.099954 <6>[ 3.340632] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10682 13:32:16.103342 <6>[ 3.349200] hub 2-0:1.0: USB hub found
10683 13:32:16.106866 <6>[ 3.353209] hub 2-0:1.0: 1 port detected
10684 13:32:16.114844 <6>[ 3.360397] mtk-msdc 11f70000.mmc: Got CD GPIO
10685 13:32:16.126786 <6>[ 3.368881] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10686 13:32:16.133096 <6>[ 3.376916] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10687 13:32:16.143459 <4>[ 3.384832] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10688 13:32:16.153481 <6>[ 3.394373] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10689 13:32:16.159695 <6>[ 3.402450] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10690 13:32:16.166472 <6>[ 3.410487] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10691 13:32:16.176309 <6>[ 3.418403] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10692 13:32:16.182998 <6>[ 3.426221] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10693 13:32:16.193221 <6>[ 3.434037] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10694 13:32:16.202954 <6>[ 3.444429] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10695 13:32:16.209688 <6>[ 3.452786] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10696 13:32:16.219616 <6>[ 3.461136] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10697 13:32:16.225800 <6>[ 3.469474] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10698 13:32:16.235881 <6>[ 3.477814] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10699 13:32:16.242582 <6>[ 3.486153] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10700 13:32:16.252428 <6>[ 3.494496] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10701 13:32:16.259156 <6>[ 3.502835] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10702 13:32:16.269133 <6>[ 3.511173] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10703 13:32:16.278722 <6>[ 3.519513] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10704 13:32:16.285825 <6>[ 3.527851] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10705 13:32:16.295400 <6>[ 3.536202] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10706 13:32:16.302135 <6>[ 3.544541] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10707 13:32:16.312319 <6>[ 3.552880] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10708 13:32:16.318625 <6>[ 3.561218] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10709 13:32:16.325306 <6>[ 3.569949] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10710 13:32:16.332206 <6>[ 3.577102] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10711 13:32:16.338491 <6>[ 3.583859] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10712 13:32:16.345359 <6>[ 3.590625] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10713 13:32:16.355275 <6>[ 3.597562] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10714 13:32:16.362015 <6>[ 3.604411] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10715 13:32:16.371840 <6>[ 3.613542] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10716 13:32:16.381890 <6>[ 3.622665] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10717 13:32:16.392147 <6>[ 3.631960] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10718 13:32:16.402038 <6>[ 3.641428] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10719 13:32:16.408438 <6>[ 3.650896] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10720 13:32:16.418485 <6>[ 3.660016] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10721 13:32:16.428665 <6>[ 3.669482] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10722 13:32:16.438384 <6>[ 3.678602] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10723 13:32:16.448176 <6>[ 3.687896] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10724 13:32:16.458237 <6>[ 3.698057] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10725 13:32:16.468133 <6>[ 3.709647] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10726 13:32:16.515364 <6>[ 3.757860] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10727 13:32:16.670380 <6>[ 3.915884] hub 1-1:1.0: USB hub found
10728 13:32:16.673377 <6>[ 3.920412] hub 1-1:1.0: 4 ports detected
10729 13:32:16.795403 <6>[ 4.037908] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10730 13:32:16.821286 <6>[ 4.066990] hub 2-1:1.0: USB hub found
10731 13:32:16.824439 <6>[ 4.071427] hub 2-1:1.0: 3 ports detected
10732 13:32:16.995775 <6>[ 4.237860] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10733 13:32:17.128178 <6>[ 4.373609] hub 1-1.4:1.0: USB hub found
10734 13:32:17.131240 <6>[ 4.378194] hub 1-1.4:1.0: 2 ports detected
10735 13:32:17.207667 <6>[ 4.450045] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10736 13:32:17.427656 <6>[ 4.669912] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10737 13:32:17.619361 <6>[ 4.861890] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10738 13:32:28.764376 <6>[ 16.014873] ALSA device list:
10739 13:32:28.771036 <6>[ 16.018166] No soundcards found.
10740 13:32:28.779321 <6>[ 16.026166] Freeing unused kernel memory: 8384K
10741 13:32:28.782665 <6>[ 16.031189] Run /init as init process
10742 13:32:28.830612 <6>[ 16.077373] NET: Registered PF_INET6 protocol family
10743 13:32:28.837393 <6>[ 16.083662] Segment Routing with IPv6
10744 13:32:28.840688 <6>[ 16.087598] In-situ OAM (IOAM) with IPv6
10745 13:32:28.874689 <30>[ 16.101548] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10746 13:32:28.877715 <30>[ 16.125520] systemd[1]: Detected architecture arm64.
10747 13:32:28.881259
10748 13:32:28.884288 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10749 13:32:28.884398
10750 13:32:28.899395 <30>[ 16.145945] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10751 13:32:29.036469 <30>[ 16.280028] systemd[1]: Queued start job for default target Graphical Interface.
10752 13:32:29.067459 <30>[ 16.314398] systemd[1]: Created slice system-getty.slice.
10753 13:32:29.073884 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10754 13:32:29.091380 <30>[ 16.338295] systemd[1]: Created slice system-modprobe.slice.
10755 13:32:29.098007 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10756 13:32:29.115084 <30>[ 16.362278] systemd[1]: Created slice system-serial\x2dgetty.slice.
10757 13:32:29.125417 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10758 13:32:29.140172 <30>[ 16.386978] systemd[1]: Created slice User and Session Slice.
10759 13:32:29.146567 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10760 13:32:29.167282 <30>[ 16.410484] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10761 13:32:29.176888 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10762 13:32:29.194871 <30>[ 16.438466] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10763 13:32:29.201325 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10764 13:32:29.225838 <30>[ 16.466353] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10765 13:32:29.232506 <30>[ 16.478595] systemd[1]: Reached target Local Encrypted Volumes.
10766 13:32:29.239250 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10767 13:32:29.255375 <30>[ 16.502371] systemd[1]: Reached target Paths.
10768 13:32:29.258785 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10769 13:32:29.274675 <30>[ 16.521879] systemd[1]: Reached target Remote File Systems.
10770 13:32:29.281434 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10771 13:32:29.299364 <30>[ 16.546256] systemd[1]: Reached target Slices.
10772 13:32:29.305700 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10773 13:32:29.318895 <30>[ 16.565895] systemd[1]: Reached target Swap.
10774 13:32:29.322077 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10775 13:32:29.342489 <30>[ 16.586394] systemd[1]: Listening on initctl Compatibility Named Pipe.
10776 13:32:29.349162 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10777 13:32:29.356165 <30>[ 16.601547] systemd[1]: Listening on Journal Audit Socket.
10778 13:32:29.362674 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10779 13:32:29.375595 <30>[ 16.622348] systemd[1]: Listening on Journal Socket (/dev/log).
10780 13:32:29.382035 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10781 13:32:29.400203 <30>[ 16.647143] systemd[1]: Listening on Journal Socket.
10782 13:32:29.406607 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10783 13:32:29.419709 <30>[ 16.666579] systemd[1]: Listening on Network Service Netlink Socket.
10784 13:32:29.429779 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10785 13:32:29.444289 <30>[ 16.691088] systemd[1]: Listening on udev Control Socket.
10786 13:32:29.450465 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10787 13:32:29.467735 <30>[ 16.714956] systemd[1]: Listening on udev Kernel Socket.
10788 13:32:29.474343 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10789 13:32:29.527057 <30>[ 16.774119] systemd[1]: Mounting Huge Pages File System...
10790 13:32:29.533506 Mounting [0;1;39mHuge Pages File System[0m...
10791 13:32:29.550178 <30>[ 16.797084] systemd[1]: Mounting POSIX Message Queue File System...
10792 13:32:29.556807 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10793 13:32:29.572685 <30>[ 16.819688] systemd[1]: Mounting Kernel Debug File System...
10794 13:32:29.579412 Mounting [0;1;39mKernel Debug File System[0m...
10795 13:32:29.598416 <30>[ 16.842110] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10796 13:32:29.610014 <30>[ 16.853798] systemd[1]: Starting Create list of static device nodes for the current kernel...
10797 13:32:29.616745 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10798 13:32:29.639491 <30>[ 16.886603] systemd[1]: Starting Load Kernel Module configfs...
10799 13:32:29.646096 Starting [0;1;39mLoad Kernel Module configfs[0m...
10800 13:32:29.663428 <30>[ 16.910530] systemd[1]: Starting Load Kernel Module drm...
10801 13:32:29.670332 Starting [0;1;39mLoad Kernel Module drm[0m...
10802 13:32:29.686559 <30>[ 16.930328] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10803 13:32:29.735776 <30>[ 16.982627] systemd[1]: Starting Journal Service...
10804 13:32:29.738686 Starting [0;1;39mJournal Service[0m...
10805 13:32:29.759898 <30>[ 17.006764] systemd[1]: Starting Load Kernel Modules...
10806 13:32:29.766530 Starting [0;1;39mLoad Kernel Modules[0m...
10807 13:32:29.823117 <30>[ 17.066896] systemd[1]: Starting Remount Root and Kernel File Systems...
10808 13:32:29.829403 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10809 13:32:29.845794 <30>[ 17.092760] systemd[1]: Starting Coldplug All udev Devices...
10810 13:32:29.852059 Starting [0;1;39mColdplug All udev Devices[0m...
10811 13:32:29.869925 <30>[ 17.116742] systemd[1]: Started Journal Service.
10812 13:32:29.876140 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10813 13:32:29.894287 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10814 13:32:29.911818 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10815 13:32:29.927985 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10816 13:32:29.948023 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10817 13:32:29.965906 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10818 13:32:29.985525 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10819 13:32:30.004726 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10820 13:32:30.025297 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10821 13:32:30.039020 See 'systemctl status systemd-remount-fs.service' for details.
10822 13:32:30.087571 Mounting [0;1;39mKernel Configuration File System[0m...
10823 13:32:30.108030 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10824 13:32:30.120766 <46>[ 17.364806] systemd-journald[178]: Received client request to flush runtime journal.
10825 13:32:30.132638 Starting [0;1;39mLoad/Save Random Seed[0m...
10826 13:32:30.151916 Starting [0;1;39mApply Kernel Variables[0m...
10827 13:32:30.171994 Starting [0;1;39mCreate System Users[0m...
10828 13:32:30.192105 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10829 13:32:30.207950 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10830 13:32:30.227727 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10831 13:32:30.240617 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10832 13:32:30.256762 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10833 13:32:30.276655 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10834 13:32:30.327748 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10835 13:32:30.357821 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10836 13:32:30.371369 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10837 13:32:30.387111 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10838 13:32:30.431379 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10839 13:32:30.455749 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10840 13:32:30.476359 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10841 13:32:30.496618 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10842 13:32:30.577429 Starting [0;1;39mNetwork Service[0m...
10843 13:32:30.595442 Starting [0;1;39mNetwork Time Synchronization[0m...
10844 13:32:30.622499 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10845 13:32:30.642046 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10846 13:32:30.669322 <6>[ 17.912936] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10847 13:32:30.676077 <6>[ 17.919731] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10848 13:32:30.689440 [[0;32m OK [0m] Started [0;1;39mNetwork Tim<6>[ 17.931569] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10849 13:32:30.699441 e Synchronizatio<3>[ 17.936715] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10850 13:32:30.705846 <6>[ 17.940529] remoteproc remoteproc0: scp is available
10851 13:32:30.708916 <6>[ 17.940606] remoteproc remoteproc0: powering up scp
10852 13:32:30.718929 <6>[ 17.940611] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10853 13:32:30.722143 <6>[ 17.940632] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10854 13:32:30.732329 <6>[ 17.941600] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10855 13:32:30.732458 n[0m.
10856 13:32:30.742142 <3>[ 17.984653] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10857 13:32:30.745478 <6>[ 17.988086] usbcore: registered new interface driver r8152
10858 13:32:30.755720 <3>[ 17.992952] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10859 13:32:30.762018 <3>[ 17.993157] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10860 13:32:30.769030 <6>[ 18.007808] mc: Linux media interface: v0.10
10861 13:32:30.775541 <3>[ 18.015470] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10862 13:32:30.782186 <6>[ 18.020545] usbcore: registered new interface driver cdc_ether
10863 13:32:30.788696 <6>[ 18.022644] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10864 13:32:30.798512 <3>[ 18.027975] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10865 13:32:30.805471 <3>[ 18.027983] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10866 13:32:30.812363 <3>[ 18.027986] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10867 13:32:30.822562 <3>[ 18.028057] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10868 13:32:30.829419 <6>[ 18.029257] videodev: Linux video capture interface: v2.00
10869 13:32:30.832336 <6>[ 18.035286] Bluetooth: Core ver 2.22
10870 13:32:30.839381 <3>[ 18.041838] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10871 13:32:30.849372 <4>[ 18.046811] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10872 13:32:30.853161 <4>[ 18.046811] Fallback method does not support PEC.
10873 13:32:30.860714 <6>[ 18.050015] NET: Registered PF_BLUETOOTH protocol family
10874 13:32:30.867025 <4>[ 18.050711] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10875 13:32:30.873835 <4>[ 18.050831] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10876 13:32:30.880286 <3>[ 18.057963] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10877 13:32:30.890393 <3>[ 18.057969] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10878 13:32:30.896863 <3>[ 18.058046] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10879 13:32:30.903659 <6>[ 18.063224] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10880 13:32:30.910411 <6>[ 18.063230] pci_bus 0000:00: root bus resource [bus 00-ff]
10881 13:32:30.917611 <6>[ 18.063234] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10882 13:32:30.927265 <6>[ 18.063237] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10883 13:32:30.934339 <6>[ 18.063265] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10884 13:32:30.941046 <6>[ 18.063279] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10885 13:32:30.947567 <6>[ 18.063346] pci 0000:00:00.0: supports D1 D2
10886 13:32:30.953957 <6>[ 18.063349] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10887 13:32:30.960561 <3>[ 18.063990] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10888 13:32:30.970304 <6>[ 18.064476] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10889 13:32:30.977449 <6>[ 18.064593] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10890 13:32:30.983848 <6>[ 18.064619] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10891 13:32:30.990441 <6>[ 18.064636] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10892 13:32:31.000348 <6>[ 18.064651] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10893 13:32:31.003678 <6>[ 18.064757] pci 0000:01:00.0: supports D1 D2
10894 13:32:31.010464 <6>[ 18.064758] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10895 13:32:31.018281 <6>[ 18.066050] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10896 13:32:31.025136 <6>[ 18.066050] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10897 13:32:31.032177 <6>[ 18.066059] Bluetooth: HCI device and connection manager initialized
10898 13:32:31.038433 <6>[ 18.066093] Bluetooth: HCI socket layer initialized
10899 13:32:31.042127 <6>[ 18.066105] Bluetooth: L2CAP socket layer initialized
10900 13:32:31.049422 <6>[ 18.066136] Bluetooth: SCO socket layer initialized
10901 13:32:31.055734 <6>[ 18.073749] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10902 13:32:31.062407 <6>[ 18.073799] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10903 13:32:31.072536 <6>[ 18.073803] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10904 13:32:31.078872 <6>[ 18.073812] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10905 13:32:31.089513 <6>[ 18.073824] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10906 13:32:31.095552 <6>[ 18.073837] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10907 13:32:31.098916 <6>[ 18.073851] pci 0000:00:00.0: PCI bridge to [bus 01]
10908 13:32:31.109597 <6>[ 18.073857] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10909 13:32:31.115870 <3>[ 18.074134] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10910 13:32:31.125900 <3>[ 18.074141] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10911 13:32:31.132346 <3>[ 18.074151] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10912 13:32:31.142535 <3>[ 18.074155] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10913 13:32:31.149152 <6>[ 18.074162] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10914 13:32:31.155576 <3>[ 18.074197] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10915 13:32:31.162209 <6>[ 18.075890] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10916 13:32:31.169248 <6>[ 18.079743] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10917 13:32:31.175300 <6>[ 18.079918] remoteproc remoteproc0: remote processor scp is now up
10918 13:32:31.182167 <3>[ 18.112633] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10919 13:32:31.189294 <6>[ 18.120075] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10920 13:32:31.198628 <3>[ 18.126752] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10921 13:32:31.208967 <6>[ 18.138157] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10922 13:32:31.218572 <6>[ 18.144528] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10923 13:32:31.225567 <6>[ 18.150998] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10924 13:32:31.236005 <6>[ 18.155983] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10925 13:32:31.242355 <6>[ 18.159989] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10926 13:32:31.252362 <3>[ 18.167308] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 13:32:31.259505 <6>[ 18.171005] usbcore: registered new interface driver r8153_ecm
10928 13:32:31.265823 <6>[ 18.178501] r8152 2-1.3:1.0: load rtl8153b-2 v1 10/23/19 successfully
10929 13:32:31.272394 <5>[ 18.191219] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10930 13:32:31.279119 <6>[ 18.200216] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10931 13:32:31.286134 <6>[ 18.206707] usbcore: registered new interface driver btusb
10932 13:32:31.295787 <4>[ 18.207540] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10933 13:32:31.302332 <3>[ 18.207569] Bluetooth: hci0: Failed to load firmware file (-2)
10934 13:32:31.309023 <3>[ 18.207573] Bluetooth: hci0: Failed to set up firmware (-2)
10935 13:32:31.318752 <4>[ 18.207577] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10936 13:32:31.331699 <6>[ 18.216494] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10937 13:32:31.338327 <5>[ 18.217238] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10938 13:32:31.348738 <4>[ 18.217293] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10939 13:32:31.351962 <6>[ 18.217299] cfg80211: failed to load regulatory.db
10940 13:32:31.358210 <6>[ 18.229720] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10941 13:32:31.365563 <6>[ 18.236967] usbcore: registered new interface driver uvcvideo
10942 13:32:31.369219 <6>[ 18.245782] r8152 2-1.3:1.0 eth0: v1.12.13
10943 13:32:31.379558 <3>[ 18.274554] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10944 13:32:31.386760 <3>[ 18.275308] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10945 13:32:31.396665 <3>[ 18.276092] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10946 13:32:31.400309 <6>[ 18.294806] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10947 13:32:31.410778 <3>[ 18.301947] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 13:32:31.417562 <6>[ 18.307181] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10949 13:32:31.424528 <6>[ 18.307288] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10950 13:32:31.431300 <6>[ 18.327673] mt7921e 0000:01:00.0: ASIC revision: 79610010
10951 13:32:31.438390 <3>[ 18.355690] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 13:32:31.448692 <4>[ 18.453006] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10953 13:32:31.458109 <3>[ 18.481967] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10954 13:32:31.468541 <4>[ 18.595373] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10955 13:32:31.474845 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10956 13:32:31.500173 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10957 13:32:31.586862 <4>[ 18.827461] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10958 13:32:31.663985 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10959 13:32:31.678908 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10960 13:32:31.701994 [[0;32m OK [<4>[ 18.943874] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10961 13:32:31.708702 0m] Reached target [0;1;39mSystem Time Set[0m.
10962 13:32:31.715065 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10963 13:32:31.738344 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10964 13:32:31.782474 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10965 13:32:31.804730 Starting [0;1;39mNetwork Name Resolution[0m...
10966 13:32:31.824670 <4>[ 19.065373] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10967 13:32:31.841289 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10968 13:32:31.855110 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10969 13:32:31.874155 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10970 13:32:31.889902 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10971 13:32:31.903000 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10972 13:32:31.923747 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10973 13:32:31.947024 [[0;32m OK [0m] Reached targ<4>[ 19.186278] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10974 13:32:31.947133 et [0;1;39mSockets[0m.
10975 13:32:31.964962 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10976 13:32:32.003856 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10977 13:32:32.041851 Starting [0;1;39mUser Login Management[0m...
10978 13:32:32.063916 <4>[ 19.304614] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10979 13:32:32.082665 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10980 13:32:32.100266 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10981 13:32:32.115757 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10982 13:32:32.131007 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10983 13:32:32.149962 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10984 13:32:32.187233 <4>[ 19.428015] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10985 13:32:32.198790 Starting [0;1;39mPermit User Sessions[0m...
10986 13:32:32.217310 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10987 13:32:32.235514 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10988 13:32:32.246612 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10989 13:32:32.268480 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10990 13:32:32.289241 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10991 13:32:32.307588 <4>[ 19.548617] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10992 13:32:32.316415 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10993 13:32:32.331497 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10994 13:32:32.379813 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10995 13:32:32.428668 <4>[ 19.669667] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10996 13:32:32.435245 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10997 13:32:32.490634
10998 13:32:32.490745
10999 13:32:32.494039 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11000 13:32:32.494124
11001 13:32:32.497580 debian-bullseye-arm64 login: root (automatic login)
11002 13:32:32.497666
11003 13:32:32.497733
11004 13:32:32.516805 Linux debian-bullseye-arm64 6.1.52-cip5 #1 SMP PREEMPT Fri Sep 8 13:10:51 UTC 2023 aarch64
11005 13:32:32.516895
11006 13:32:32.523779 The programs included with the Debian GNU/Linux system are free software;
11007 13:32:32.530317 the exact distribution terms for each program are described in the
11008 13:32:32.533769 individual files in /usr/share/doc/*/copyright.
11009 13:32:32.533854
11010 13:32:32.540060 Debian GNU/Linu<3>[ 19.786082] mt7921e 0000:01:00.0: hardware init failed
11011 13:32:32.543771 x comes with ABSOLUTELY NO WARRANTY, to the extent
11012 13:32:32.546932 permitted by applicable law.
11013 13:32:32.547432 Matched prompt #10: / #
11015 13:32:32.547788 Setting prompt string to ['/ #']
11016 13:32:32.547939 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11018 13:32:32.548282 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11019 13:32:32.548425 start: 2.2.6 expect-shell-connection (timeout 00:03:28) [common]
11020 13:32:32.548547 Setting prompt string to ['/ #']
11021 13:32:32.548658 Forcing a shell prompt, looking for ['/ #']
11023 13:32:32.598951 / #
11024 13:32:32.599096 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11025 13:32:32.599218 Waiting using forced prompt support (timeout 00:02:30)
11026 13:32:32.604074
11027 13:32:32.604348 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11028 13:32:32.604439 start: 2.2.7 export-device-env (timeout 00:03:28) [common]
11029 13:32:32.604532 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11030 13:32:32.604621 end: 2.2 depthcharge-retry (duration 00:01:32) [common]
11031 13:32:32.604703 end: 2 depthcharge-action (duration 00:01:32) [common]
11032 13:32:32.604828 start: 3 lava-test-retry (timeout 00:05:00) [common]
11033 13:32:32.604915 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11034 13:32:32.604989 Using namespace: common
11036 13:32:32.705311 / # #
11037 13:32:32.705559 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11038 13:32:32.705815 <6>[ 19.865612] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c722dd6: link becomes ready
11039 13:32:32.705936 <6>[ 19.873631] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
11040 13:32:32.710136 #
11041 13:32:32.710458 Using /lava-11471188
11043 13:32:32.810883 / # export SHELL=/bin/sh
11044 13:32:32.815685 export SHELL=/bin/sh
11046 13:32:32.916205 / # . /lava-11471188/environment
11047 13:32:32.921241 . /lava-11471188/environment
11049 13:32:33.021767 / # /lava-11471188/bin/lava-test-runner /lava-11471188/0
11050 13:32:33.021903 Test shell timeout: 10s (minimum of the action and connection timeout)
11051 13:32:33.027027 /lava-11471188/bin/lava-test-runner /lava-11471188/0
11052 13:32:33.047069 + export TESTRUN_ID=0_cros-ec
11053 13:32:33.053986 + c<8>[ 20.299336] <LAVA_SIGNAL_STARTRUN 0_cros-ec 11471188_1.5.2.3.1>
11054 13:32:33.054271 Received signal: <STARTRUN> 0_cros-ec 11471188_1.5.2.3.1
11055 13:32:33.054377 Starting test lava.0_cros-ec (11471188_1.5.2.3.1)
11056 13:32:33.054493 Skipping test definition patterns.
11057 13:32:33.057121 d /lava-11471188/0/tests/0_cros-ec
11058 13:32:33.057196 + cat uuid
11059 13:32:33.060162 + UUID=11471188_1.5.2.3.1
11060 13:32:33.060234 + set +x
11061 13:32:33.066880 + python3 -m cros.runners.lava_runner -v
11062 13:32:33.450465 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
11063 13:32:33.456977 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11064 13:32:33.460302
11065 13:32:33.463855 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11067 13:32:33.467106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11068 13:32:33.473828 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
11069 13:32:33.480461 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11070 13:32:33.480555
11071 13:32:33.490740 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=ski<8
11072 13:32:33.490839 Bad test result: ski<8
11073 13:32:33.493549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=ski<8>[ 20.740933] <LAVA_SIGNAL_ENDRUN 0_cros-ec 11471188_1.5.2.3.1>
11074 13:32:33.493635 p>
11075 13:32:33.493868 Received signal: <ENDRUN> 0_cros-ec 11471188_1.5.2.3.1
11076 13:32:33.493946 Ending use of test pattern.
11077 13:32:33.494007 Ending test lava.0_cros-ec (11471188_1.5.2.3.1), duration 0.44
11079 13:32:33.500348 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
11080 13:32:33.507027 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11081 13:32:33.507112
11082 13:32:33.513478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11083 13:32:33.513735 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11085 13:32:33.520002 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11086 13:32:33.523304 Checks the standard ABI for the main Embedded Controller. ... ok
11087 13:32:33.526711
11088 13:32:33.529910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11089 13:32:33.530182 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11091 13:32:33.536729 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
11092 13:32:33.539849 Checks the main Embedded controller character device. ... ok
11093 13:32:33.543409
11094 13:32:33.546623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11095 13:32:33.546894 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11097 13:32:33.553058 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11098 13:32:33.559623 Checks basic comunication with the main Embedded controller. ... ok
11099 13:32:33.559704
11100 13:32:33.566468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11101 13:32:33.566753 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11103 13:32:33.569545 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11104 13:32:33.576420 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11105 13:32:33.576518
11106 13:32:33.582749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11107 13:32:33.583003 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11109 13:32:33.589553 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11110 13:32:33.596173 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11111 13:32:33.596258
11112 13:32:33.602775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11113 13:32:33.603030 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11115 13:32:33.608864 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
11116 13:32:33.615568 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11117 13:32:33.615696
11118 13:32:33.622383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11119 13:32:33.622690 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11121 13:32:33.625808 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11122 13:32:33.635724 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11123 13:32:33.635852
11124 13:32:33.638722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11125 13:32:33.639024 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11127 13:32:33.645416 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11128 13:32:33.652376 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11129 13:32:33.655721
11130 13:32:33.658908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11131 13:32:33.659163 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11133 13:32:33.665519 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11134 13:32:33.672189 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11135 13:32:33.672276
11136 13:32:33.678761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11137 13:32:33.679016 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11139 13:32:33.681744 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11140 13:32:33.692002 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11141 13:32:33.692088
11142 13:32:33.698760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11143 13:32:33.699015 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11145 13:32:33.702004 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
11146 13:32:33.711853 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11147 13:32:33.711939
11148 13:32:33.718550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11149 13:32:33.718847 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11151 13:32:33.724915 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
11152 13:32:33.728238 Check the cros battery ABI. ... skipped 'No BAT found'
11153 13:32:33.728358
11154 13:32:33.734906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11155 13:32:33.735206 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11157 13:32:33.741670 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
11158 13:32:33.748414 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11159 13:32:33.748527
11160 13:32:33.755240 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11162 13:32:33.758439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11163 13:32:33.761440 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
11164 13:32:33.767954 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11165 13:32:33.768068
11166 13:32:33.774684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11167 13:32:33.774981 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11169 13:32:33.781498 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
11170 13:32:33.788132 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11171 13:32:33.788242
11172 13:32:33.794492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11173 13:32:33.794605
11174 13:32:33.794876 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11176 13:32:33.800898 ----------------------------------------------------------------------
11177 13:32:33.804237 Ran 18 tests in 0.007s
11178 13:32:33.804347
11179 13:32:33.804446 OK (skipped=15)
11180 13:32:33.804552 + set +x
11181 13:32:33.807658 <LAVA_TEST_RUNNER EXIT>
11182 13:32:33.807952 ok: lava_test_shell seems to have completed
11183 13:32:33.808279 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11184 13:32:33.808418 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11185 13:32:33.808550 end: 3 lava-test-retry (duration 00:00:01) [common]
11186 13:32:33.808678 start: 4 finalize (timeout 00:08:05) [common]
11187 13:32:33.808816 start: 4.1 power-off (timeout 00:00:30) [common]
11188 13:32:33.809122 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11189 13:32:33.885012 >> Command sent successfully.
11190 13:32:33.887366 Returned 0 in 0 seconds
11191 13:32:33.987790 end: 4.1 power-off (duration 00:00:00) [common]
11193 13:32:33.988221 start: 4.2 read-feedback (timeout 00:08:05) [common]
11194 13:32:33.988513 Listened to connection for namespace 'common' for up to 1s
11195 13:32:34.988855 Finalising connection for namespace 'common'
11196 13:32:34.989097 Disconnecting from shell: Finalise
11197 13:32:34.989239 / #
11198 13:32:35.089617 end: 4.2 read-feedback (duration 00:00:01) [common]
11199 13:32:35.089842 end: 4 finalize (duration 00:00:01) [common]
11200 13:32:35.090051 Cleaning after the job
11201 13:32:35.090209 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11471188/tftp-deploy-0wnm07x2/ramdisk
11202 13:32:35.095106 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11471188/tftp-deploy-0wnm07x2/kernel
11203 13:32:35.101251 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11471188/tftp-deploy-0wnm07x2/dtb
11204 13:32:35.101470 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11471188/tftp-deploy-0wnm07x2/modules
11205 13:32:35.107278 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11471188
11206 13:32:35.217288 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11471188
11207 13:32:35.217482 Job finished correctly