Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 135
- Boot result: PASS
- Warnings: 1
- Errors: 0
- Kernel Warnings: 22
1 13:30:24.520758 lava-dispatcher, installed at version: 2023.06
2 13:30:24.520921 start: 0 validate
3 13:30:24.521034 Start time: 2023-09-08 13:30:24.521028+00:00 (UTC)
4 13:30:24.521173 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:30:24.521330 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 13:30:25.071280 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:30:25.071462 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.52-cip5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:30:25.341131 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:30:25.341705 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.52-cip5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:30:25.613019 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:30:25.613539 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.52-cip5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 13:30:25.889027 validate duration: 1.37
14 13:30:25.889958 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:30:25.890076 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:30:25.890155 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:30:25.890272 Not decompressing ramdisk as can be used compressed.
18 13:30:25.890353 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/rootfs.cpio.gz
19 13:30:25.890408 saving as /var/lib/lava/dispatcher/tmp/11471181/tftp-deploy-gextz524/ramdisk/rootfs.cpio.gz
20 13:30:25.890461 total size: 84918747 (80 MB)
21 13:30:25.896982 progress 0 % (0 MB)
22 13:30:25.923076 progress 5 % (4 MB)
23 13:30:25.937685 progress 10 % (8 MB)
24 13:30:25.952630 progress 15 % (12 MB)
25 13:30:25.967564 progress 20 % (16 MB)
26 13:30:25.982615 progress 25 % (20 MB)
27 13:30:25.997569 progress 30 % (24 MB)
28 13:30:26.012306 progress 35 % (28 MB)
29 13:30:26.026886 progress 40 % (32 MB)
30 13:30:26.041457 progress 45 % (36 MB)
31 13:30:26.055894 progress 50 % (40 MB)
32 13:30:26.070787 progress 55 % (44 MB)
33 13:30:26.085704 progress 60 % (48 MB)
34 13:30:26.100467 progress 65 % (52 MB)
35 13:30:26.115267 progress 70 % (56 MB)
36 13:30:26.129870 progress 75 % (60 MB)
37 13:30:26.144481 progress 80 % (64 MB)
38 13:30:26.158880 progress 85 % (68 MB)
39 13:30:26.173531 progress 90 % (72 MB)
40 13:30:26.188095 progress 95 % (76 MB)
41 13:30:26.202736 progress 100 % (80 MB)
42 13:30:26.202882 80 MB downloaded in 0.31 s (259.22 MB/s)
43 13:30:26.203041 end: 1.1.1 http-download (duration 00:00:00) [common]
45 13:30:26.203255 end: 1.1 download-retry (duration 00:00:00) [common]
46 13:30:26.203322 start: 1.2 download-retry (timeout 00:10:00) [common]
47 13:30:26.203385 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 13:30:26.203533 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.52-cip5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 13:30:26.203589 saving as /var/lib/lava/dispatcher/tmp/11471181/tftp-deploy-gextz524/kernel/Image
50 13:30:26.203636 total size: 49220096 (46 MB)
51 13:30:26.203690 No compression specified
52 13:30:26.204838 progress 0 % (0 MB)
53 13:30:26.213555 progress 5 % (2 MB)
54 13:30:26.222120 progress 10 % (4 MB)
55 13:30:26.230665 progress 15 % (7 MB)
56 13:30:26.239160 progress 20 % (9 MB)
57 13:30:26.247743 progress 25 % (11 MB)
58 13:30:26.256165 progress 30 % (14 MB)
59 13:30:26.264604 progress 35 % (16 MB)
60 13:30:26.273076 progress 40 % (18 MB)
61 13:30:26.281690 progress 45 % (21 MB)
62 13:30:26.290173 progress 50 % (23 MB)
63 13:30:26.298759 progress 55 % (25 MB)
64 13:30:26.307279 progress 60 % (28 MB)
65 13:30:26.315871 progress 65 % (30 MB)
66 13:30:26.324430 progress 70 % (32 MB)
67 13:30:26.332958 progress 75 % (35 MB)
68 13:30:26.341435 progress 80 % (37 MB)
69 13:30:26.349886 progress 85 % (39 MB)
70 13:30:26.358416 progress 90 % (42 MB)
71 13:30:26.366764 progress 95 % (44 MB)
72 13:30:26.375269 progress 100 % (46 MB)
73 13:30:26.375359 46 MB downloaded in 0.17 s (273.35 MB/s)
74 13:30:26.375487 end: 1.2.1 http-download (duration 00:00:00) [common]
76 13:30:26.375691 end: 1.2 download-retry (duration 00:00:00) [common]
77 13:30:26.375757 start: 1.3 download-retry (timeout 00:10:00) [common]
78 13:30:26.375824 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 13:30:26.375947 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.52-cip5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 13:30:26.376008 saving as /var/lib/lava/dispatcher/tmp/11471181/tftp-deploy-gextz524/dtb/mt8192-asurada-spherion-r0.dtb
81 13:30:26.376056 total size: 47278 (0 MB)
82 13:30:26.376104 No compression specified
83 13:30:26.377275 progress 69 % (0 MB)
84 13:30:26.377494 progress 100 % (0 MB)
85 13:30:26.377621 0 MB downloaded in 0.00 s (28.85 MB/s)
86 13:30:26.377728 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:30:26.377912 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:30:26.378009 start: 1.4 download-retry (timeout 00:10:00) [common]
90 13:30:26.378095 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 13:30:26.378192 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.52-cip5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 13:30:26.378249 saving as /var/lib/lava/dispatcher/tmp/11471181/tftp-deploy-gextz524/modules/modules.tar
93 13:30:26.378297 total size: 8615576 (8 MB)
94 13:30:26.378351 Using unxz to decompress xz
95 13:30:26.381951 progress 0 % (0 MB)
96 13:30:26.400881 progress 5 % (0 MB)
97 13:30:26.419798 progress 10 % (0 MB)
98 13:30:26.442342 progress 15 % (1 MB)
99 13:30:26.464089 progress 20 % (1 MB)
100 13:30:26.485856 progress 25 % (2 MB)
101 13:30:26.508055 progress 30 % (2 MB)
102 13:30:26.531359 progress 35 % (2 MB)
103 13:30:26.552637 progress 40 % (3 MB)
104 13:30:26.573211 progress 45 % (3 MB)
105 13:30:26.595577 progress 50 % (4 MB)
106 13:30:26.617246 progress 55 % (4 MB)
107 13:30:26.638219 progress 60 % (4 MB)
108 13:30:26.657380 progress 65 % (5 MB)
109 13:30:26.680546 progress 70 % (5 MB)
110 13:30:26.700896 progress 75 % (6 MB)
111 13:30:26.723385 progress 80 % (6 MB)
112 13:30:26.749190 progress 85 % (7 MB)
113 13:30:26.771400 progress 90 % (7 MB)
114 13:30:26.791872 progress 95 % (7 MB)
115 13:30:26.811266 progress 100 % (8 MB)
116 13:30:26.816890 8 MB downloaded in 0.44 s (18.73 MB/s)
117 13:30:26.817106 end: 1.4.1 http-download (duration 00:00:00) [common]
119 13:30:26.817333 end: 1.4 download-retry (duration 00:00:00) [common]
120 13:30:26.817421 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 13:30:26.817513 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 13:30:26.817591 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:30:26.817666 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 13:30:26.817860 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11471181/lava-overlay-fv6n3qzk
125 13:30:26.817974 makedir: /var/lib/lava/dispatcher/tmp/11471181/lava-overlay-fv6n3qzk/lava-11471181/bin
126 13:30:26.818064 makedir: /var/lib/lava/dispatcher/tmp/11471181/lava-overlay-fv6n3qzk/lava-11471181/tests
127 13:30:26.818145 makedir: /var/lib/lava/dispatcher/tmp/11471181/lava-overlay-fv6n3qzk/lava-11471181/results
128 13:30:26.818247 Creating /var/lib/lava/dispatcher/tmp/11471181/lava-overlay-fv6n3qzk/lava-11471181/bin/lava-add-keys
129 13:30:26.818395 Creating /var/lib/lava/dispatcher/tmp/11471181/lava-overlay-fv6n3qzk/lava-11471181/bin/lava-add-sources
130 13:30:26.818501 Creating /var/lib/lava/dispatcher/tmp/11471181/lava-overlay-fv6n3qzk/lava-11471181/bin/lava-background-process-start
131 13:30:26.818605 Creating /var/lib/lava/dispatcher/tmp/11471181/lava-overlay-fv6n3qzk/lava-11471181/bin/lava-background-process-stop
132 13:30:26.818703 Creating /var/lib/lava/dispatcher/tmp/11471181/lava-overlay-fv6n3qzk/lava-11471181/bin/lava-common-functions
133 13:30:26.818805 Creating /var/lib/lava/dispatcher/tmp/11471181/lava-overlay-fv6n3qzk/lava-11471181/bin/lava-echo-ipv4
134 13:30:26.818901 Creating /var/lib/lava/dispatcher/tmp/11471181/lava-overlay-fv6n3qzk/lava-11471181/bin/lava-install-packages
135 13:30:26.818996 Creating /var/lib/lava/dispatcher/tmp/11471181/lava-overlay-fv6n3qzk/lava-11471181/bin/lava-installed-packages
136 13:30:26.819090 Creating /var/lib/lava/dispatcher/tmp/11471181/lava-overlay-fv6n3qzk/lava-11471181/bin/lava-os-build
137 13:30:26.819185 Creating /var/lib/lava/dispatcher/tmp/11471181/lava-overlay-fv6n3qzk/lava-11471181/bin/lava-probe-channel
138 13:30:26.819282 Creating /var/lib/lava/dispatcher/tmp/11471181/lava-overlay-fv6n3qzk/lava-11471181/bin/lava-probe-ip
139 13:30:26.819376 Creating /var/lib/lava/dispatcher/tmp/11471181/lava-overlay-fv6n3qzk/lava-11471181/bin/lava-target-ip
140 13:30:26.819473 Creating /var/lib/lava/dispatcher/tmp/11471181/lava-overlay-fv6n3qzk/lava-11471181/bin/lava-target-mac
141 13:30:26.819568 Creating /var/lib/lava/dispatcher/tmp/11471181/lava-overlay-fv6n3qzk/lava-11471181/bin/lava-target-storage
142 13:30:26.819666 Creating /var/lib/lava/dispatcher/tmp/11471181/lava-overlay-fv6n3qzk/lava-11471181/bin/lava-test-case
143 13:30:26.819763 Creating /var/lib/lava/dispatcher/tmp/11471181/lava-overlay-fv6n3qzk/lava-11471181/bin/lava-test-event
144 13:30:26.819858 Creating /var/lib/lava/dispatcher/tmp/11471181/lava-overlay-fv6n3qzk/lava-11471181/bin/lava-test-feedback
145 13:30:26.819953 Creating /var/lib/lava/dispatcher/tmp/11471181/lava-overlay-fv6n3qzk/lava-11471181/bin/lava-test-raise
146 13:30:26.820048 Creating /var/lib/lava/dispatcher/tmp/11471181/lava-overlay-fv6n3qzk/lava-11471181/bin/lava-test-reference
147 13:30:26.820143 Creating /var/lib/lava/dispatcher/tmp/11471181/lava-overlay-fv6n3qzk/lava-11471181/bin/lava-test-runner
148 13:30:26.820237 Creating /var/lib/lava/dispatcher/tmp/11471181/lava-overlay-fv6n3qzk/lava-11471181/bin/lava-test-set
149 13:30:26.820343 Creating /var/lib/lava/dispatcher/tmp/11471181/lava-overlay-fv6n3qzk/lava-11471181/bin/lava-test-shell
150 13:30:26.820453 Updating /var/lib/lava/dispatcher/tmp/11471181/lava-overlay-fv6n3qzk/lava-11471181/bin/lava-install-packages (oe)
151 13:30:26.820578 Updating /var/lib/lava/dispatcher/tmp/11471181/lava-overlay-fv6n3qzk/lava-11471181/bin/lava-installed-packages (oe)
152 13:30:26.820681 Creating /var/lib/lava/dispatcher/tmp/11471181/lava-overlay-fv6n3qzk/lava-11471181/environment
153 13:30:26.820764 LAVA metadata
154 13:30:26.820826 - LAVA_JOB_ID=11471181
155 13:30:26.820879 - LAVA_DISPATCHER_IP=192.168.201.1
156 13:30:26.820967 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 13:30:26.821022 skipped lava-vland-overlay
158 13:30:26.821082 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 13:30:26.821147 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 13:30:26.821197 skipped lava-multinode-overlay
161 13:30:26.821255 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 13:30:26.821320 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 13:30:26.821379 Loading test definitions
164 13:30:26.821451 start: 1.5.2.3.1 git-repo-action (timeout 00:09:59) [common]
165 13:30:26.821511 Using /lava-11471181 at stage 0
166 13:30:26.821590 Fetching tests from https://github.com/kernelci/kernelci-core
167 13:30:26.821675 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/11471181/lava-overlay-fv6n3qzk/lava-11471181/0/tests/0_sleep'
168 13:30:27.490637 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/11471181/lava-overlay-fv6n3qzk/lava-11471181/0/tests/0_sleep
169 13:30:27.491694 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/11471181/lava-overlay-fv6n3qzk/lava-11471181/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 13:30:27.492109 uuid=11471181_1.5.2.3.1 testdef=None
171 13:30:27.492262 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 13:30:27.492583 start: 1.5.2.3.2 test-overlay (timeout 00:09:58) [common]
174 13:30:27.493198 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 13:30:27.493483 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:58) [common]
177 13:30:27.494471 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 13:30:27.494818 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:58) [common]
180 13:30:27.495749 runner path: /var/lib/lava/dispatcher/tmp/11471181/lava-overlay-fv6n3qzk/lava-11471181/0/tests/0_sleep test_uuid 11471181_1.5.2.3.1
181 13:30:27.495878 sleep_params='mem freeze'
182 13:30:27.496017 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 13:30:27.496188 Creating lava-test-runner.conf files
185 13:30:27.496237 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11471181/lava-overlay-fv6n3qzk/lava-11471181/0 for stage 0
186 13:30:27.496332 - 0_sleep
187 13:30:27.496430 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 13:30:27.496498 start: 1.5.2.4 compress-overlay (timeout 00:09:58) [common]
189 13:30:27.596106 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 13:30:27.596251 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:58) [common]
191 13:30:27.596340 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 13:30:27.596418 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 13:30:27.596486 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
194 13:30:29.194613 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
195 13:30:29.194916 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
196 13:30:29.195031 extracting modules file /var/lib/lava/dispatcher/tmp/11471181/tftp-deploy-gextz524/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11471181/extract-overlay-ramdisk-1pz54c8d/ramdisk
197 13:30:29.334274 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 13:30:29.334458 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
199 13:30:29.334551 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11471181/compress-overlay-5cizy6a4/overlay-1.5.2.4.tar.gz to ramdisk
200 13:30:29.334623 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11471181/compress-overlay-5cizy6a4/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11471181/extract-overlay-ramdisk-1pz54c8d/ramdisk
201 13:30:29.398647 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 13:30:29.398786 start: 1.5.6 configure-preseed-file (timeout 00:09:56) [common]
203 13:30:29.398868 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 13:30:29.398935 start: 1.5.7 compress-ramdisk (timeout 00:09:56) [common]
205 13:30:29.398999 Building ramdisk /var/lib/lava/dispatcher/tmp/11471181/extract-overlay-ramdisk-1pz54c8d/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11471181/extract-overlay-ramdisk-1pz54c8d/ramdisk
206 13:30:30.039545 >> 563352 blocks
207 13:30:38.559807 rename /var/lib/lava/dispatcher/tmp/11471181/extract-overlay-ramdisk-1pz54c8d/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11471181/tftp-deploy-gextz524/ramdisk/ramdisk.cpio.gz
208 13:30:38.560190 end: 1.5.7 compress-ramdisk (duration 00:00:09) [common]
209 13:30:38.560370 start: 1.5.8 prepare-kernel (timeout 00:09:47) [common]
210 13:30:38.560525 start: 1.5.8.1 prepare-fit (timeout 00:09:47) [common]
211 13:30:38.560675 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11471181/tftp-deploy-gextz524/kernel/Image'
212 13:30:51.485643 Returned 0 in 12 seconds
213 13:30:51.586204 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11471181/tftp-deploy-gextz524/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11471181/tftp-deploy-gextz524/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11471181/tftp-deploy-gextz524/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11471181/tftp-deploy-gextz524/kernel/image.itb
214 13:30:52.241834 output: FIT description: Kernel Image image with one or more FDT blobs
215 13:30:52.242098 output: Created: Fri Sep 8 14:30:52 2023
216 13:30:52.242186 output: Image 0 (kernel-1)
217 13:30:52.242253 output: Description:
218 13:30:52.242317 output: Created: Fri Sep 8 14:30:52 2023
219 13:30:52.242381 output: Type: Kernel Image
220 13:30:52.242453 output: Compression: lzma compressed
221 13:30:52.242518 output: Data Size: 11040095 Bytes = 10781.34 KiB = 10.53 MiB
222 13:30:52.242584 output: Architecture: AArch64
223 13:30:52.242647 output: OS: Linux
224 13:30:52.242708 output: Load Address: 0x00000000
225 13:30:52.242768 output: Entry Point: 0x00000000
226 13:30:52.242829 output: Hash algo: crc32
227 13:30:52.242888 output: Hash value: 41c180c9
228 13:30:52.242948 output: Image 1 (fdt-1)
229 13:30:52.243014 output: Description: mt8192-asurada-spherion-r0
230 13:30:52.243075 output: Created: Fri Sep 8 14:30:52 2023
231 13:30:52.243135 output: Type: Flat Device Tree
232 13:30:52.243205 output: Compression: uncompressed
233 13:30:52.243270 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
234 13:30:52.243329 output: Architecture: AArch64
235 13:30:52.243388 output: Hash algo: crc32
236 13:30:52.243454 output: Hash value: cc4352de
237 13:30:52.243532 output: Image 2 (ramdisk-1)
238 13:30:52.243589 output: Description: unavailable
239 13:30:52.243646 output: Created: Fri Sep 8 14:30:52 2023
240 13:30:52.243703 output: Type: RAMDisk Image
241 13:30:52.243760 output: Compression: Unknown Compression
242 13:30:52.243815 output: Data Size: 98319756 Bytes = 96015.39 KiB = 93.77 MiB
243 13:30:52.243873 output: Architecture: AArch64
244 13:30:52.243929 output: OS: Linux
245 13:30:52.243985 output: Load Address: unavailable
246 13:30:52.244042 output: Entry Point: unavailable
247 13:30:52.244098 output: Hash algo: crc32
248 13:30:52.244155 output: Hash value: 975d1f2e
249 13:30:52.244212 output: Default Configuration: 'conf-1'
250 13:30:52.244269 output: Configuration 0 (conf-1)
251 13:30:52.244346 output: Description: mt8192-asurada-spherion-r0
252 13:30:52.244403 output: Kernel: kernel-1
253 13:30:52.244457 output: Init Ramdisk: ramdisk-1
254 13:30:52.244512 output: FDT: fdt-1
255 13:30:52.244585 output: Loadables: kernel-1
256 13:30:52.244655 output:
257 13:30:52.244824 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
258 13:30:52.244943 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
259 13:30:52.245033 end: 1.5 prepare-tftp-overlay (duration 00:00:25) [common]
260 13:30:52.245123 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:34) [common]
261 13:30:52.245196 No LXC device requested
262 13:30:52.245269 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 13:30:52.245346 start: 1.7 deploy-device-env (timeout 00:09:34) [common]
264 13:30:52.245416 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 13:30:52.245500 Checking files for TFTP limit of 4294967296 bytes.
266 13:30:52.245923 end: 1 tftp-deploy (duration 00:00:26) [common]
267 13:30:52.246023 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 13:30:52.246104 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 13:30:52.246208 substitutions:
270 13:30:52.246267 - {DTB}: 11471181/tftp-deploy-gextz524/dtb/mt8192-asurada-spherion-r0.dtb
271 13:30:52.246327 - {INITRD}: 11471181/tftp-deploy-gextz524/ramdisk/ramdisk.cpio.gz
272 13:30:52.246385 - {KERNEL}: 11471181/tftp-deploy-gextz524/kernel/Image
273 13:30:52.246441 - {LAVA_MAC}: None
274 13:30:52.246497 - {PRESEED_CONFIG}: None
275 13:30:52.246552 - {PRESEED_LOCAL}: None
276 13:30:52.246608 - {RAMDISK}: 11471181/tftp-deploy-gextz524/ramdisk/ramdisk.cpio.gz
277 13:30:52.246664 - {ROOT_PART}: None
278 13:30:52.246719 - {ROOT}: None
279 13:30:52.246774 - {SERVER_IP}: 192.168.201.1
280 13:30:52.246829 - {TEE}: None
281 13:30:52.246883 Parsed boot commands:
282 13:30:52.246940 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 13:30:52.247106 Parsed boot commands: tftpboot 192.168.201.1 11471181/tftp-deploy-gextz524/kernel/image.itb 11471181/tftp-deploy-gextz524/kernel/cmdline
284 13:30:52.247188 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 13:30:52.247266 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 13:30:52.247349 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 13:30:52.247425 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 13:30:52.247499 Not connected, no need to disconnect.
289 13:30:52.247569 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 13:30:52.247644 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 13:30:52.247703 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
292 13:30:52.250742 Setting prompt string to ['lava-test: # ']
293 13:30:52.251025 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 13:30:52.251130 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 13:30:52.251234 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 13:30:52.251320 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 13:30:52.251502 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
298 13:30:57.387104 >> Command sent successfully.
299 13:30:57.395628 Returned 0 in 5 seconds
300 13:30:57.496609 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 13:30:57.497624 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 13:30:57.498152 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 13:30:57.498556 Setting prompt string to 'Starting depthcharge on Spherion...'
305 13:30:57.498815 Changing prompt to 'Starting depthcharge on Spherion...'
306 13:30:57.499071 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 13:30:57.500069 [Enter `^Ec?' for help]
308 13:30:57.669775
309 13:30:57.670231
310 13:30:57.670518 F0: 102B 0000
311 13:30:57.670765
312 13:30:57.670997 F3: 1001 0000 [0200]
313 13:30:57.671256
314 13:30:57.673048 F3: 1001 0000
315 13:30:57.673348
316 13:30:57.673587 F7: 102D 0000
317 13:30:57.673819
318 13:30:57.674048 F1: 0000 0000
319 13:30:57.676895
320 13:30:57.677288 V0: 0000 0000 [0001]
321 13:30:57.677573
322 13:30:57.677817 00: 0007 8000
323 13:30:57.678072
324 13:30:57.680164 01: 0000 0000
325 13:30:57.680566
326 13:30:57.680826 BP: 0C00 0209 [0000]
327 13:30:57.681057
328 13:30:57.683804 G0: 1182 0000
329 13:30:57.684161
330 13:30:57.684465 EC: 0000 0021 [4000]
331 13:30:57.684703
332 13:30:57.687066 S7: 0000 0000 [0000]
333 13:30:57.687428
334 13:30:57.687683 CC: 0000 0000 [0001]
335 13:30:57.687908
336 13:30:57.690288 T0: 0000 0040 [010F]
337 13:30:57.690647
338 13:30:57.690904 Jump to BL
339 13:30:57.691128
340 13:30:57.716507
341 13:30:57.716992
342 13:30:57.717297
343 13:30:57.723752 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 13:30:57.727387 ARM64: Exception handlers installed.
345 13:30:57.730934 ARM64: Testing exception
346 13:30:57.734693 ARM64: Done test exception
347 13:30:57.741929 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 13:30:57.749408 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 13:30:57.755812 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 13:30:57.767432 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 13:30:57.773880 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 13:30:57.783869 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 13:30:57.794511 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 13:30:57.801207 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 13:30:57.818674 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 13:30:57.822054 WDT: Last reset was cold boot
357 13:30:57.826200 SPI1(PAD0) initialized at 2873684 Hz
358 13:30:57.829008 SPI5(PAD0) initialized at 992727 Hz
359 13:30:57.832130 VBOOT: Loading verstage.
360 13:30:57.838990 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 13:30:57.842760 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 13:30:57.845855 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 13:30:57.849374 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 13:30:57.856518 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 13:30:57.863550 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 13:30:57.874464 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
367 13:30:57.874960
368 13:30:57.875257
369 13:30:57.883946 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 13:30:57.887487 ARM64: Exception handlers installed.
371 13:30:57.890371 ARM64: Testing exception
372 13:30:57.890710 ARM64: Done test exception
373 13:30:57.897024 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 13:30:57.900639 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 13:30:57.915495 Probing TPM: . done!
376 13:30:57.915928 TPM ready after 0 ms
377 13:30:57.921527 Connected to device vid:did:rid of 1ae0:0028:00
378 13:30:57.929034 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
379 13:30:57.979237 Initialized TPM device CR50 revision 0
380 13:30:57.983083 tlcl_send_startup: Startup return code is 0
381 13:30:57.989384 TPM: setup succeeded
382 13:30:58.005720 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 13:30:58.013031 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 13:30:58.021547 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 13:30:58.031375 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 13:30:58.034611 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 13:30:58.037947 in-header: 03 07 00 00 08 00 00 00
388 13:30:58.040695 in-data: aa e4 47 04 13 02 00 00
389 13:30:58.044328 Chrome EC: UHEPI supported
390 13:30:58.050997 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 13:30:58.055287 in-header: 03 95 00 00 08 00 00 00
392 13:30:58.058256 in-data: 18 20 20 08 00 00 00 00
393 13:30:58.058740 Phase 1
394 13:30:58.062019 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 13:30:58.069492 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 13:30:58.073229 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 13:30:58.076328 Recovery requested (1009000e)
398 13:30:58.085559 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 13:30:58.091227 tlcl_extend: response is 0
400 13:30:58.100948 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 13:30:58.106391 tlcl_extend: response is 0
402 13:30:58.113092 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 13:30:58.133853 read SPI 0x210d4 0x2173b: 15145 us, 9047 KB/s, 72.376 Mbps
404 13:30:58.140567 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 13:30:58.140948
406 13:30:58.141196
407 13:30:58.148190 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 13:30:58.151936 ARM64: Exception handlers installed.
409 13:30:58.155514 ARM64: Testing exception
410 13:30:58.159112 ARM64: Done test exception
411 13:30:58.179029 pmic_efuse_setting: Set efuses in 11 msecs
412 13:30:58.182233 pmwrap_interface_init: Select PMIF_VLD_RDY
413 13:30:58.188704 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 13:30:58.192108 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 13:30:58.198798 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 13:30:58.202135 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 13:30:58.208482 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 13:30:58.212002 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 13:30:58.215585 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 13:30:58.222032 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 13:30:58.225373 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 13:30:58.232038 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 13:30:58.235273 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 13:30:58.238643 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 13:30:58.245252 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 13:30:58.252426 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 13:30:58.255487 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 13:30:58.263262 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 13:30:58.267189 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 13:30:58.274414 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 13:30:58.278101 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 13:30:58.285960 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 13:30:58.289148 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 13:30:58.296840 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 13:30:58.303441 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 13:30:58.307149 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 13:30:58.310633 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 13:30:58.317715 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 13:30:58.321364 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 13:30:58.328607 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 13:30:58.332358 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 13:30:58.339658 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 13:30:58.343190 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 13:30:58.346820 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 13:30:58.351010 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 13:30:58.357977 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 13:30:58.361409 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 13:30:58.369265 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 13:30:58.372810 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 13:30:58.376836 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 13:30:58.383908 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 13:30:58.387089 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 13:30:58.390868 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 13:30:58.395005 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 13:30:58.398698 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 13:30:58.405856 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 13:30:58.410326 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 13:30:58.413913 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 13:30:58.417200 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 13:30:58.420858 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 13:30:58.424593 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 13:30:58.427966 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 13:30:58.435130 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 13:30:58.442620 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 13:30:58.449505 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 13:30:58.453432 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 13:30:58.464515 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 13:30:58.471856 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 13:30:58.475364 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 13:30:58.478937 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 13:30:58.486161 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 13:30:58.493603 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x15
473 13:30:58.497543 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 13:30:58.500559 [RTC]rtc_osc_init,62: osc32con val = 0xde70
475 13:30:58.507792 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 13:30:58.516197 [RTC]rtc_get_frequency_meter,154: input=15, output=763
477 13:30:58.526049 [RTC]rtc_get_frequency_meter,154: input=23, output=947
478 13:30:58.535385 [RTC]rtc_get_frequency_meter,154: input=19, output=856
479 13:30:58.544841 [RTC]rtc_get_frequency_meter,154: input=17, output=809
480 13:30:58.554698 [RTC]rtc_get_frequency_meter,154: input=16, output=787
481 13:30:58.563713 [RTC]rtc_get_frequency_meter,154: input=16, output=786
482 13:30:58.573991 [RTC]rtc_get_frequency_meter,154: input=17, output=810
483 13:30:58.577776 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
484 13:30:58.584621 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
485 13:30:58.588208 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
486 13:30:58.592152 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
487 13:30:58.595262 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
488 13:30:58.599435 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
489 13:30:58.603327 ADC[4]: Raw value=670063 ID=5
490 13:30:58.607008 ADC[3]: Raw value=212917 ID=1
491 13:30:58.607363 RAM Code: 0x51
492 13:30:58.610593 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
493 13:30:58.617736 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
494 13:30:58.625248 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
495 13:30:58.628994 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
496 13:30:58.632016 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
497 13:30:58.636599 in-header: 03 07 00 00 08 00 00 00
498 13:30:58.640818 in-data: aa e4 47 04 13 02 00 00
499 13:30:58.643924 Chrome EC: UHEPI supported
500 13:30:58.650652 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
501 13:30:58.654735 in-header: 03 95 00 00 08 00 00 00
502 13:30:58.658474 in-data: 18 20 20 08 00 00 00 00
503 13:30:58.658832 MRC: failed to locate region type 0.
504 13:30:58.665766 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
505 13:30:58.669566 DRAM-K: Running full calibration
506 13:30:58.677320 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
507 13:30:58.677748 header.status = 0x0
508 13:30:58.679822 header.version = 0x6 (expected: 0x6)
509 13:30:58.683825 header.size = 0xd00 (expected: 0xd00)
510 13:30:58.687414 header.flags = 0x0
511 13:30:58.690796 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
512 13:30:58.710370 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps
513 13:30:58.717021 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
514 13:30:58.720778 dram_init: ddr_geometry: 0
515 13:30:58.721131 [EMI] MDL number = 0
516 13:30:58.724040 [EMI] Get MDL freq = 0
517 13:30:58.724132 dram_init: ddr_type: 0
518 13:30:58.728004 is_discrete_lpddr4: 1
519 13:30:58.731578 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
520 13:30:58.731646
521 13:30:58.731715
522 13:30:58.731763 [Bian_co] ETT version 0.0.0.1
523 13:30:58.739598 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
524 13:30:58.740047
525 13:30:58.743270 dramc_set_vcore_voltage set vcore to 650000
526 13:30:58.743721 Read voltage for 800, 4
527 13:30:58.743980 Vio18 = 0
528 13:30:58.746809 Vcore = 650000
529 13:30:58.747182 Vdram = 0
530 13:30:58.747536 Vddq = 0
531 13:30:58.750480 Vmddr = 0
532 13:30:58.750549 dram_init: config_dvfs: 1
533 13:30:58.757554 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
534 13:30:58.761913 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
535 13:30:58.764762 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
536 13:30:58.768428 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
537 13:30:58.772733 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
538 13:30:58.776457 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
539 13:30:58.780400 MEM_TYPE=3, freq_sel=18
540 13:30:58.783954 sv_algorithm_assistance_LP4_1600
541 13:30:58.787796 ============ PULL DRAM RESETB DOWN ============
542 13:30:58.791421 ========== PULL DRAM RESETB DOWN end =========
543 13:30:58.794866 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
544 13:30:58.798733 ===================================
545 13:30:58.802429 LPDDR4 DRAM CONFIGURATION
546 13:30:58.806341 ===================================
547 13:30:58.806721 EX_ROW_EN[0] = 0x0
548 13:30:58.810186 EX_ROW_EN[1] = 0x0
549 13:30:58.810540 LP4Y_EN = 0x0
550 13:30:58.810789 WORK_FSP = 0x0
551 13:30:58.814126 WL = 0x2
552 13:30:58.814634 RL = 0x2
553 13:30:58.817273 BL = 0x2
554 13:30:58.817645 RPST = 0x0
555 13:30:58.820854 RD_PRE = 0x0
556 13:30:58.821147 WR_PRE = 0x1
557 13:30:58.825199 WR_PST = 0x0
558 13:30:58.825589 DBI_WR = 0x0
559 13:30:58.828775 DBI_RD = 0x0
560 13:30:58.829064 OTF = 0x1
561 13:30:58.832192 ===================================
562 13:30:58.836139 ===================================
563 13:30:58.836535 ANA top config
564 13:30:58.839961 ===================================
565 13:30:58.843731 DLL_ASYNC_EN = 0
566 13:30:58.843818 ALL_SLAVE_EN = 1
567 13:30:58.846516 NEW_RANK_MODE = 1
568 13:30:58.850046 DLL_IDLE_MODE = 1
569 13:30:58.853417 LP45_APHY_COMB_EN = 1
570 13:30:58.853483 TX_ODT_DIS = 1
571 13:30:58.856722 NEW_8X_MODE = 1
572 13:30:58.859904 ===================================
573 13:30:58.863222 ===================================
574 13:30:58.867168 data_rate = 1600
575 13:30:58.870490 CKR = 1
576 13:30:58.874829 DQ_P2S_RATIO = 8
577 13:30:58.877992 ===================================
578 13:30:58.878069 CA_P2S_RATIO = 8
579 13:30:58.881613 DQ_CA_OPEN = 0
580 13:30:58.885033 DQ_SEMI_OPEN = 0
581 13:30:58.888588 CA_SEMI_OPEN = 0
582 13:30:58.888988 CA_FULL_RATE = 0
583 13:30:58.892063 DQ_CKDIV4_EN = 1
584 13:30:58.895284 CA_CKDIV4_EN = 1
585 13:30:58.898739 CA_PREDIV_EN = 0
586 13:30:58.902406 PH8_DLY = 0
587 13:30:58.905518 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
588 13:30:58.905920 DQ_AAMCK_DIV = 4
589 13:30:58.909872 CA_AAMCK_DIV = 4
590 13:30:58.913436 CA_ADMCK_DIV = 4
591 13:30:58.913835 DQ_TRACK_CA_EN = 0
592 13:30:58.916925 CA_PICK = 800
593 13:30:58.919747 CA_MCKIO = 800
594 13:30:58.924095 MCKIO_SEMI = 0
595 13:30:58.927296 PLL_FREQ = 3068
596 13:30:58.930643 DQ_UI_PI_RATIO = 32
597 13:30:58.931013 CA_UI_PI_RATIO = 0
598 13:30:58.934039 ===================================
599 13:30:58.937765 ===================================
600 13:30:58.941174 memory_type:LPDDR4
601 13:30:58.945038 GP_NUM : 10
602 13:30:58.945484 SRAM_EN : 1
603 13:30:58.948562 MD32_EN : 0
604 13:30:58.952187 ===================================
605 13:30:58.952558 [ANA_INIT] >>>>>>>>>>>>>>
606 13:30:58.956173 <<<<<< [CONFIGURE PHASE]: ANA_TX
607 13:30:58.959138 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
608 13:30:58.962818 ===================================
609 13:30:58.966593 data_rate = 1600,PCW = 0X7600
610 13:30:58.966684 ===================================
611 13:30:58.970357 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
612 13:30:58.977302 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
613 13:30:58.984179 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
614 13:30:58.987208 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
615 13:30:58.990368 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
616 13:30:58.994040 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
617 13:30:58.997383 [ANA_INIT] flow start
618 13:30:58.997473 [ANA_INIT] PLL >>>>>>>>
619 13:30:59.000646 [ANA_INIT] PLL <<<<<<<<
620 13:30:59.004824 [ANA_INIT] MIDPI >>>>>>>>
621 13:30:59.007312 [ANA_INIT] MIDPI <<<<<<<<
622 13:30:59.007611 [ANA_INIT] DLL >>>>>>>>
623 13:30:59.010735 [ANA_INIT] flow end
624 13:30:59.014224 ============ LP4 DIFF to SE enter ============
625 13:30:59.017464 ============ LP4 DIFF to SE exit ============
626 13:30:59.020733 [ANA_INIT] <<<<<<<<<<<<<
627 13:30:59.024048 [Flow] Enable top DCM control >>>>>
628 13:30:59.027677 [Flow] Enable top DCM control <<<<<
629 13:30:59.031168 Enable DLL master slave shuffle
630 13:30:59.037383 ==============================================================
631 13:30:59.037837 Gating Mode config
632 13:30:59.044136 ==============================================================
633 13:30:59.044642 Config description:
634 13:30:59.054077 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
635 13:30:59.060542 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
636 13:30:59.067547 SELPH_MODE 0: By rank 1: By Phase
637 13:30:59.071152 ==============================================================
638 13:30:59.074121 GAT_TRACK_EN = 1
639 13:30:59.077166 RX_GATING_MODE = 2
640 13:30:59.080715 RX_GATING_TRACK_MODE = 2
641 13:30:59.084055 SELPH_MODE = 1
642 13:30:59.087406 PICG_EARLY_EN = 1
643 13:30:59.090929 VALID_LAT_VALUE = 1
644 13:30:59.094261 ==============================================================
645 13:30:59.097108 Enter into Gating configuration >>>>
646 13:30:59.101028 Exit from Gating configuration <<<<
647 13:30:59.104038 Enter into DVFS_PRE_config >>>>>
648 13:30:59.117101 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
649 13:30:59.117550 Exit from DVFS_PRE_config <<<<<
650 13:30:59.120564 Enter into PICG configuration >>>>
651 13:30:59.123691 Exit from PICG configuration <<<<
652 13:30:59.127367 [RX_INPUT] configuration >>>>>
653 13:30:59.131066 [RX_INPUT] configuration <<<<<
654 13:30:59.137519 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
655 13:30:59.140910 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
656 13:30:59.147381 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
657 13:30:59.154106 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
658 13:30:59.161153 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
659 13:30:59.168058 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
660 13:30:59.171297 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
661 13:30:59.174281 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
662 13:30:59.177780 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
663 13:30:59.184149 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
664 13:30:59.187372 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
665 13:30:59.190732 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
666 13:30:59.194829 ===================================
667 13:30:59.197399 LPDDR4 DRAM CONFIGURATION
668 13:30:59.200671 ===================================
669 13:30:59.201027 EX_ROW_EN[0] = 0x0
670 13:30:59.204446 EX_ROW_EN[1] = 0x0
671 13:30:59.204802 LP4Y_EN = 0x0
672 13:30:59.207628 WORK_FSP = 0x0
673 13:30:59.208053 WL = 0x2
674 13:30:59.210781 RL = 0x2
675 13:30:59.211236 BL = 0x2
676 13:30:59.214035 RPST = 0x0
677 13:30:59.214418 RD_PRE = 0x0
678 13:30:59.217840 WR_PRE = 0x1
679 13:30:59.220991 WR_PST = 0x0
680 13:30:59.221348 DBI_WR = 0x0
681 13:30:59.224020 DBI_RD = 0x0
682 13:30:59.224407 OTF = 0x1
683 13:30:59.227693 ===================================
684 13:30:59.231438 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
685 13:30:59.234669 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
686 13:30:59.241419 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
687 13:30:59.244497 ===================================
688 13:30:59.247606 LPDDR4 DRAM CONFIGURATION
689 13:30:59.250817 ===================================
690 13:30:59.251177 EX_ROW_EN[0] = 0x10
691 13:30:59.254334 EX_ROW_EN[1] = 0x0
692 13:30:59.254689 LP4Y_EN = 0x0
693 13:30:59.257502 WORK_FSP = 0x0
694 13:30:59.257857 WL = 0x2
695 13:30:59.260723 RL = 0x2
696 13:30:59.261154 BL = 0x2
697 13:30:59.264219 RPST = 0x0
698 13:30:59.264610 RD_PRE = 0x0
699 13:30:59.267452 WR_PRE = 0x1
700 13:30:59.267527 WR_PST = 0x0
701 13:30:59.270760 DBI_WR = 0x0
702 13:30:59.270835 DBI_RD = 0x0
703 13:30:59.274642 OTF = 0x1
704 13:30:59.277694 ===================================
705 13:30:59.284002 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
706 13:30:59.287557 nWR fixed to 40
707 13:30:59.290828 [ModeRegInit_LP4] CH0 RK0
708 13:30:59.291189 [ModeRegInit_LP4] CH0 RK1
709 13:30:59.294170 [ModeRegInit_LP4] CH1 RK0
710 13:30:59.297376 [ModeRegInit_LP4] CH1 RK1
711 13:30:59.297457 match AC timing 12
712 13:30:59.303841 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
713 13:30:59.307615 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
714 13:30:59.310651 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
715 13:30:59.317305 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
716 13:30:59.320655 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
717 13:30:59.320730 [EMI DOE] emi_dcm 0
718 13:30:59.327641 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
719 13:30:59.327720 ==
720 13:30:59.330712 Dram Type= 6, Freq= 0, CH_0, rank 0
721 13:30:59.333841 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
722 13:30:59.333918 ==
723 13:30:59.340627 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
724 13:30:59.343919 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
725 13:30:59.354689 [CA 0] Center 37 (7~68) winsize 62
726 13:30:59.358129 [CA 1] Center 37 (7~68) winsize 62
727 13:30:59.361513 [CA 2] Center 35 (5~66) winsize 62
728 13:30:59.364515 [CA 3] Center 35 (5~66) winsize 62
729 13:30:59.367963 [CA 4] Center 34 (4~65) winsize 62
730 13:30:59.371253 [CA 5] Center 33 (3~64) winsize 62
731 13:30:59.371329
732 13:30:59.375435 [CmdBusTrainingLP45] Vref(ca) range 1: 32
733 13:30:59.376036
734 13:30:59.377910 [CATrainingPosCal] consider 1 rank data
735 13:30:59.381808 u2DelayCellTimex100 = 270/100 ps
736 13:30:59.384919 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
737 13:30:59.388024 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
738 13:30:59.394506 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
739 13:30:59.397978 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
740 13:30:59.401149 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
741 13:30:59.404007 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
742 13:30:59.404085
743 13:30:59.407936 CA PerBit enable=1, Macro0, CA PI delay=33
744 13:30:59.408016
745 13:30:59.411107 [CBTSetCACLKResult] CA Dly = 33
746 13:30:59.411183 CS Dly: 6 (0~37)
747 13:30:59.414298 ==
748 13:30:59.417599 Dram Type= 6, Freq= 0, CH_0, rank 1
749 13:30:59.421497 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
750 13:30:59.421583 ==
751 13:30:59.424362 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 13:30:59.431193 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 13:30:59.441268 [CA 0] Center 37 (7~68) winsize 62
754 13:30:59.444096 [CA 1] Center 37 (6~68) winsize 63
755 13:30:59.447834 [CA 2] Center 35 (4~66) winsize 63
756 13:30:59.450962 [CA 3] Center 35 (5~66) winsize 62
757 13:30:59.454229 [CA 4] Center 33 (3~64) winsize 62
758 13:30:59.457508 [CA 5] Center 34 (3~65) winsize 63
759 13:30:59.457882
760 13:30:59.461150 [CmdBusTrainingLP45] Vref(ca) range 1: 34
761 13:30:59.461507
762 13:30:59.464037 [CATrainingPosCal] consider 2 rank data
763 13:30:59.467265 u2DelayCellTimex100 = 270/100 ps
764 13:30:59.471283 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
765 13:30:59.474182 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
766 13:30:59.480942 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
767 13:30:59.483862 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
768 13:30:59.487219 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
769 13:30:59.490545 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
770 13:30:59.490908
771 13:30:59.494153 CA PerBit enable=1, Macro0, CA PI delay=33
772 13:30:59.494515
773 13:30:59.497253 [CBTSetCACLKResult] CA Dly = 33
774 13:30:59.497638 CS Dly: 6 (0~37)
775 13:30:59.497929
776 13:30:59.500412 ----->DramcWriteLeveling(PI) begin...
777 13:30:59.503917 ==
778 13:30:59.507057 Dram Type= 6, Freq= 0, CH_0, rank 0
779 13:30:59.510179 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
780 13:30:59.510479 ==
781 13:30:59.514541 Write leveling (Byte 0): 31 => 31
782 13:30:59.517384 Write leveling (Byte 1): 27 => 27
783 13:30:59.521057 DramcWriteLeveling(PI) end<-----
784 13:30:59.521415
785 13:30:59.521679 ==
786 13:30:59.524488 Dram Type= 6, Freq= 0, CH_0, rank 0
787 13:30:59.527847 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
788 13:30:59.527938 ==
789 13:30:59.531365 [Gating] SW mode calibration
790 13:30:59.538850 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
791 13:30:59.541745 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
792 13:30:59.545249 0 6 0 | B1->B0 | 3333 3131 | 1 1 | (1 0) (1 0)
793 13:30:59.552475 0 6 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
794 13:30:59.555629 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 13:30:59.559098 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 13:30:59.565934 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 13:30:59.569259 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 13:30:59.572432 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 13:30:59.579160 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 13:30:59.582815 0 7 0 | B1->B0 | 2424 2c2c | 0 0 | (0 0) (1 1)
801 13:30:59.585795 0 7 4 | B1->B0 | 3e3e 3e3e | 1 1 | (0 0) (0 0)
802 13:30:59.589229 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
803 13:30:59.595739 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
804 13:30:59.599058 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
805 13:30:59.602446 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
806 13:30:59.609249 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
807 13:30:59.612640 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
808 13:30:59.615666 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
809 13:30:59.622430 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
810 13:30:59.625978 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
811 13:30:59.629333 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
812 13:30:59.635748 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
813 13:30:59.639341 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
814 13:30:59.642273 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
815 13:30:59.649022 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
816 13:30:59.653011 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
817 13:30:59.656130 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
818 13:30:59.659724 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
819 13:30:59.666612 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
820 13:30:59.669925 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
821 13:30:59.673038 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
822 13:30:59.679845 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
823 13:30:59.682948 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
824 13:30:59.686428 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 13:30:59.689751 Total UI for P1: 0, mck2ui 16
826 13:30:59.692612 best dqsien dly found for B0: ( 0, 9, 30)
827 13:30:59.695941 Total UI for P1: 0, mck2ui 16
828 13:30:59.699224 best dqsien dly found for B1: ( 0, 9, 30)
829 13:30:59.702401 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
830 13:30:59.706099 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
831 13:30:59.706170
832 13:30:59.713220 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
833 13:30:59.715845 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
834 13:30:59.715952 [Gating] SW calibration Done
835 13:30:59.719510 ==
836 13:30:59.722489 Dram Type= 6, Freq= 0, CH_0, rank 0
837 13:30:59.726010 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
838 13:30:59.726102 ==
839 13:30:59.726169 RX Vref Scan: 0
840 13:30:59.726230
841 13:30:59.729235 RX Vref 0 -> 0, step: 1
842 13:30:59.729310
843 13:30:59.732584 RX Delay -130 -> 252, step: 16
844 13:30:59.735881 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
845 13:30:59.739115 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
846 13:30:59.742865 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
847 13:30:59.749690 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
848 13:30:59.753233 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
849 13:30:59.756211 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
850 13:30:59.759517 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
851 13:30:59.763004 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
852 13:30:59.769604 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
853 13:30:59.773188 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
854 13:30:59.776053 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
855 13:30:59.779880 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
856 13:30:59.783054 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
857 13:30:59.789528 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
858 13:30:59.792561 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
859 13:30:59.796228 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
860 13:30:59.796623 ==
861 13:30:59.799696 Dram Type= 6, Freq= 0, CH_0, rank 0
862 13:30:59.803150 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
863 13:30:59.803620 ==
864 13:30:59.806542 DQS Delay:
865 13:30:59.806990 DQS0 = 0, DQS1 = 0
866 13:30:59.809807 DQM Delay:
867 13:30:59.810165 DQM0 = 82, DQM1 = 74
868 13:30:59.810420 DQ Delay:
869 13:30:59.813286 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
870 13:30:59.816263 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
871 13:30:59.819923 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
872 13:30:59.823459 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
873 13:30:59.823908
874 13:30:59.824181
875 13:30:59.826307 ==
876 13:30:59.829496 Dram Type= 6, Freq= 0, CH_0, rank 0
877 13:30:59.832451 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
878 13:30:59.832812 ==
879 13:30:59.833072
880 13:30:59.833293
881 13:30:59.836123 TX Vref Scan disable
882 13:30:59.836580 == TX Byte 0 ==
883 13:30:59.839477 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
884 13:30:59.846701 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
885 13:30:59.847187 == TX Byte 1 ==
886 13:30:59.850045 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
887 13:30:59.856137 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
888 13:30:59.856523 ==
889 13:30:59.859748 Dram Type= 6, Freq= 0, CH_0, rank 0
890 13:30:59.863728 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
891 13:30:59.864218 ==
892 13:30:59.876767 TX Vref=22, minBit 4, minWin=27, winSum=444
893 13:30:59.880089 TX Vref=24, minBit 0, minWin=27, winSum=445
894 13:30:59.883826 TX Vref=26, minBit 4, minWin=28, winSum=455
895 13:30:59.887233 TX Vref=28, minBit 4, minWin=28, winSum=457
896 13:30:59.890100 TX Vref=30, minBit 0, minWin=28, winSum=454
897 13:30:59.893409 TX Vref=32, minBit 0, minWin=28, winSum=453
898 13:30:59.900267 [TxChooseVref] Worse bit 4, Min win 28, Win sum 457, Final Vref 28
899 13:30:59.900720
900 13:30:59.903452 Final TX Range 1 Vref 28
901 13:30:59.903946
902 13:30:59.904248 ==
903 13:30:59.907012 Dram Type= 6, Freq= 0, CH_0, rank 0
904 13:30:59.909880 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
905 13:30:59.910257 ==
906 13:30:59.910538
907 13:30:59.910775
908 13:30:59.913630 TX Vref Scan disable
909 13:30:59.916937 == TX Byte 0 ==
910 13:30:59.920478 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
911 13:30:59.923457 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
912 13:30:59.927630 == TX Byte 1 ==
913 13:30:59.930361 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
914 13:30:59.934204 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
915 13:30:59.934668
916 13:30:59.937550 [DATLAT]
917 13:30:59.938016 Freq=800, CH0 RK0
918 13:30:59.938295
919 13:30:59.940058 DATLAT Default: 0xa
920 13:30:59.940449 0, 0xFFFF, sum = 0
921 13:30:59.943689 1, 0xFFFF, sum = 0
922 13:30:59.944062 2, 0xFFFF, sum = 0
923 13:30:59.947065 3, 0xFFFF, sum = 0
924 13:30:59.947489 4, 0xFFFF, sum = 0
925 13:30:59.950505 5, 0xFFFF, sum = 0
926 13:30:59.950869 6, 0xFFFF, sum = 0
927 13:30:59.954176 7, 0xFFFF, sum = 0
928 13:30:59.954645 8, 0x0, sum = 1
929 13:30:59.957267 9, 0x0, sum = 2
930 13:30:59.957669 10, 0x0, sum = 3
931 13:30:59.960114 11, 0x0, sum = 4
932 13:30:59.960445 best_step = 9
933 13:30:59.960680
934 13:30:59.960895 ==
935 13:30:59.963868 Dram Type= 6, Freq= 0, CH_0, rank 0
936 13:30:59.966928 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
937 13:30:59.967301 ==
938 13:30:59.970476 RX Vref Scan: 1
939 13:30:59.970832
940 13:30:59.973872 Set Vref Range= 32 -> 127
941 13:30:59.974333
942 13:30:59.974585 RX Vref 32 -> 127, step: 1
943 13:30:59.974812
944 13:30:59.977250 RX Delay -111 -> 252, step: 8
945 13:30:59.977604
946 13:30:59.980169 Set Vref, RX VrefLevel [Byte0]: 32
947 13:30:59.983705 [Byte1]: 32
948 13:30:59.987353
949 13:30:59.987863 Set Vref, RX VrefLevel [Byte0]: 33
950 13:30:59.991056 [Byte1]: 33
951 13:30:59.994824
952 13:30:59.995233 Set Vref, RX VrefLevel [Byte0]: 34
953 13:30:59.998197 [Byte1]: 34
954 13:31:00.002765
955 13:31:00.003227 Set Vref, RX VrefLevel [Byte0]: 35
956 13:31:00.006555 [Byte1]: 35
957 13:31:00.010535
958 13:31:00.010996 Set Vref, RX VrefLevel [Byte0]: 36
959 13:31:00.013699 [Byte1]: 36
960 13:31:00.018231
961 13:31:00.018698 Set Vref, RX VrefLevel [Byte0]: 37
962 13:31:00.021202 [Byte1]: 37
963 13:31:00.025542
964 13:31:00.025993 Set Vref, RX VrefLevel [Byte0]: 38
965 13:31:00.029071 [Byte1]: 38
966 13:31:00.033986
967 13:31:00.034479 Set Vref, RX VrefLevel [Byte0]: 39
968 13:31:00.036997 [Byte1]: 39
969 13:31:00.040669
970 13:31:00.041125 Set Vref, RX VrefLevel [Byte0]: 40
971 13:31:00.044216 [Byte1]: 40
972 13:31:00.048661
973 13:31:00.049057 Set Vref, RX VrefLevel [Byte0]: 41
974 13:31:00.052004 [Byte1]: 41
975 13:31:00.056263
976 13:31:00.056682 Set Vref, RX VrefLevel [Byte0]: 42
977 13:31:00.059460 [Byte1]: 42
978 13:31:00.064059
979 13:31:00.064589 Set Vref, RX VrefLevel [Byte0]: 43
980 13:31:00.067347 [Byte1]: 43
981 13:31:00.072004
982 13:31:00.072546 Set Vref, RX VrefLevel [Byte0]: 44
983 13:31:00.075242 [Byte1]: 44
984 13:31:00.079511
985 13:31:00.080000 Set Vref, RX VrefLevel [Byte0]: 45
986 13:31:00.082800 [Byte1]: 45
987 13:31:00.086542
988 13:31:00.086945 Set Vref, RX VrefLevel [Byte0]: 46
989 13:31:00.090188 [Byte1]: 46
990 13:31:00.094521
991 13:31:00.094877 Set Vref, RX VrefLevel [Byte0]: 47
992 13:31:00.097638 [Byte1]: 47
993 13:31:00.102225
994 13:31:00.102300 Set Vref, RX VrefLevel [Byte0]: 48
995 13:31:00.105366 [Byte1]: 48
996 13:31:00.109747
997 13:31:00.110146 Set Vref, RX VrefLevel [Byte0]: 49
998 13:31:00.113344 [Byte1]: 49
999 13:31:00.117370
1000 13:31:00.117721 Set Vref, RX VrefLevel [Byte0]: 50
1001 13:31:00.120748 [Byte1]: 50
1002 13:31:00.124563
1003 13:31:00.124914 Set Vref, RX VrefLevel [Byte0]: 51
1004 13:31:00.128827 [Byte1]: 51
1005 13:31:00.132757
1006 13:31:00.133114 Set Vref, RX VrefLevel [Byte0]: 52
1007 13:31:00.136106 [Byte1]: 52
1008 13:31:00.140598
1009 13:31:00.141100 Set Vref, RX VrefLevel [Byte0]: 53
1010 13:31:00.144013 [Byte1]: 53
1011 13:31:00.147989
1012 13:31:00.148367 Set Vref, RX VrefLevel [Byte0]: 54
1013 13:31:00.151248 [Byte1]: 54
1014 13:31:00.155578
1015 13:31:00.156012 Set Vref, RX VrefLevel [Byte0]: 55
1016 13:31:00.159034 [Byte1]: 55
1017 13:31:00.163202
1018 13:31:00.163561 Set Vref, RX VrefLevel [Byte0]: 56
1019 13:31:00.167297 [Byte1]: 56
1020 13:31:00.171005
1021 13:31:00.171417 Set Vref, RX VrefLevel [Byte0]: 57
1022 13:31:00.174044 [Byte1]: 57
1023 13:31:00.178530
1024 13:31:00.178969 Set Vref, RX VrefLevel [Byte0]: 58
1025 13:31:00.181608 [Byte1]: 58
1026 13:31:00.186689
1027 13:31:00.187038 Set Vref, RX VrefLevel [Byte0]: 59
1028 13:31:00.189958 [Byte1]: 59
1029 13:31:00.193785
1030 13:31:00.194136 Set Vref, RX VrefLevel [Byte0]: 60
1031 13:31:00.197286 [Byte1]: 60
1032 13:31:00.201783
1033 13:31:00.202160 Set Vref, RX VrefLevel [Byte0]: 61
1034 13:31:00.205210 [Byte1]: 61
1035 13:31:00.209166
1036 13:31:00.209514 Set Vref, RX VrefLevel [Byte0]: 62
1037 13:31:00.212711 [Byte1]: 62
1038 13:31:00.216829
1039 13:31:00.219776 Set Vref, RX VrefLevel [Byte0]: 63
1040 13:31:00.220133 [Byte1]: 63
1041 13:31:00.224347
1042 13:31:00.224754 Set Vref, RX VrefLevel [Byte0]: 64
1043 13:31:00.227702 [Byte1]: 64
1044 13:31:00.232095
1045 13:31:00.232597 Set Vref, RX VrefLevel [Byte0]: 65
1046 13:31:00.235895 [Byte1]: 65
1047 13:31:00.239500
1048 13:31:00.239918 Set Vref, RX VrefLevel [Byte0]: 66
1049 13:31:00.243139 [Byte1]: 66
1050 13:31:00.247455
1051 13:31:00.247913 Set Vref, RX VrefLevel [Byte0]: 67
1052 13:31:00.250853 [Byte1]: 67
1053 13:31:00.255038
1054 13:31:00.255507 Set Vref, RX VrefLevel [Byte0]: 68
1055 13:31:00.258327 [Byte1]: 68
1056 13:31:00.262593
1057 13:31:00.262940 Set Vref, RX VrefLevel [Byte0]: 69
1058 13:31:00.266091 [Byte1]: 69
1059 13:31:00.270362
1060 13:31:00.270820 Set Vref, RX VrefLevel [Byte0]: 70
1061 13:31:00.273867 [Byte1]: 70
1062 13:31:00.277722
1063 13:31:00.278095 Set Vref, RX VrefLevel [Byte0]: 71
1064 13:31:00.281668 [Byte1]: 71
1065 13:31:00.285673
1066 13:31:00.286022 Set Vref, RX VrefLevel [Byte0]: 72
1067 13:31:00.289147 [Byte1]: 72
1068 13:31:00.293402
1069 13:31:00.293752 Set Vref, RX VrefLevel [Byte0]: 73
1070 13:31:00.296502 [Byte1]: 73
1071 13:31:00.300604
1072 13:31:00.300980 Final RX Vref Byte 0 = 54 to rank0
1073 13:31:00.303966 Final RX Vref Byte 1 = 55 to rank0
1074 13:31:00.307746 Final RX Vref Byte 0 = 54 to rank1
1075 13:31:00.311262 Final RX Vref Byte 1 = 55 to rank1==
1076 13:31:00.314407 Dram Type= 6, Freq= 0, CH_0, rank 0
1077 13:31:00.320885 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1078 13:31:00.321256 ==
1079 13:31:00.321499 DQS Delay:
1080 13:31:00.321773 DQS0 = 0, DQS1 = 0
1081 13:31:00.323879 DQM Delay:
1082 13:31:00.324128 DQM0 = 83, DQM1 = 73
1083 13:31:00.327711 DQ Delay:
1084 13:31:00.330847 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1085 13:31:00.331209 DQ4 =88, DQ5 =72, DQ6 =88, DQ7 =92
1086 13:31:00.334765 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1087 13:31:00.340820 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1088 13:31:00.341222
1089 13:31:00.341463
1090 13:31:00.347747 [DQSOSCAuto] RK0, (LSB)MR18= 0x3131, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
1091 13:31:00.350721 CH0 RK0: MR19=606, MR18=3131
1092 13:31:00.357549 CH0_RK0: MR19=0x606, MR18=0x3131, DQSOSC=397, MR23=63, INC=93, DEC=62
1093 13:31:00.357894
1094 13:31:00.360803 ----->DramcWriteLeveling(PI) begin...
1095 13:31:00.361149 ==
1096 13:31:00.364602 Dram Type= 6, Freq= 0, CH_0, rank 1
1097 13:31:00.367914 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1098 13:31:00.368413 ==
1099 13:31:00.371203 Write leveling (Byte 0): 28 => 28
1100 13:31:00.374384 Write leveling (Byte 1): 28 => 28
1101 13:31:00.377550 DramcWriteLeveling(PI) end<-----
1102 13:31:00.377968
1103 13:31:00.378218 ==
1104 13:31:00.380522 Dram Type= 6, Freq= 0, CH_0, rank 1
1105 13:31:00.384425 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1106 13:31:00.384863 ==
1107 13:31:00.387879 [Gating] SW mode calibration
1108 13:31:00.394422 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1109 13:31:00.400918 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1110 13:31:00.404577 0 6 0 | B1->B0 | 3030 3030 | 0 0 | (0 0) (0 0)
1111 13:31:00.407357 0 6 4 | B1->B0 | 2525 2424 | 0 0 | (1 0) (1 0)
1112 13:31:00.414710 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1113 13:31:00.417518 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1114 13:31:00.420740 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1115 13:31:00.427984 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1116 13:31:00.430991 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1117 13:31:00.434425 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1118 13:31:00.437856 0 7 0 | B1->B0 | 2e2e 3232 | 0 0 | (0 0) (1 1)
1119 13:31:00.444155 0 7 4 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1120 13:31:00.447833 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1121 13:31:00.451121 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1122 13:31:00.458141 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1123 13:31:00.461084 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1124 13:31:00.464076 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1125 13:31:00.471354 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1126 13:31:00.474346 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1127 13:31:00.477732 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1128 13:31:00.484023 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1129 13:31:00.487645 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1130 13:31:00.491066 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1131 13:31:00.497628 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1132 13:31:00.501160 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1133 13:31:00.504507 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1134 13:31:00.511486 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1135 13:31:00.514594 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1136 13:31:00.518195 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1137 13:31:00.524446 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1138 13:31:00.528332 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1139 13:31:00.531423 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1140 13:31:00.535409 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1141 13:31:00.541737 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1142 13:31:00.544566 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1143 13:31:00.547893 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1144 13:31:00.551072 Total UI for P1: 0, mck2ui 16
1145 13:31:00.554887 best dqsien dly found for B0: ( 0, 9, 30)
1146 13:31:00.558149 Total UI for P1: 0, mck2ui 16
1147 13:31:00.561099 best dqsien dly found for B1: ( 0, 9, 30)
1148 13:31:00.564189 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1149 13:31:00.568379 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1150 13:31:00.568860
1151 13:31:00.574849 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1152 13:31:00.578061 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1153 13:31:00.581080 [Gating] SW calibration Done
1154 13:31:00.581424 ==
1155 13:31:00.584835 Dram Type= 6, Freq= 0, CH_0, rank 1
1156 13:31:00.587799 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1157 13:31:00.588146 ==
1158 13:31:00.588421 RX Vref Scan: 0
1159 13:31:00.588640
1160 13:31:00.590831 RX Vref 0 -> 0, step: 1
1161 13:31:00.591174
1162 13:31:00.594443 RX Delay -130 -> 252, step: 16
1163 13:31:00.638658 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1164 13:31:00.639163 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1165 13:31:00.639446 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1166 13:31:00.639978 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1167 13:31:00.640243 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1168 13:31:00.640514 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1169 13:31:00.640739 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1170 13:31:00.640961 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1171 13:31:00.641180 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1172 13:31:00.641395 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1173 13:31:00.641660 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1174 13:31:00.660618 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1175 13:31:00.661102 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1176 13:31:00.661381 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1177 13:31:00.661902 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1178 13:31:00.662167 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1179 13:31:00.662396 ==
1180 13:31:00.662623 Dram Type= 6, Freq= 0, CH_0, rank 1
1181 13:31:00.668340 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1182 13:31:00.668845 ==
1183 13:31:00.669131 DQS Delay:
1184 13:31:00.669366 DQS0 = 0, DQS1 = 0
1185 13:31:00.671367 DQM Delay:
1186 13:31:00.671731 DQM0 = 84, DQM1 = 74
1187 13:31:00.675308 DQ Delay:
1188 13:31:00.678377 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1189 13:31:00.678876 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1190 13:31:00.681069 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1191 13:31:00.684615 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1192 13:31:00.687990
1193 13:31:00.688465
1194 13:31:00.688736 ==
1195 13:31:00.690913 Dram Type= 6, Freq= 0, CH_0, rank 1
1196 13:31:00.694045 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1197 13:31:00.694406 ==
1198 13:31:00.694673
1199 13:31:00.694906
1200 13:31:00.697648 TX Vref Scan disable
1201 13:31:00.698027 == TX Byte 0 ==
1202 13:31:00.704487 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1203 13:31:00.708271 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1204 13:31:00.708791 == TX Byte 1 ==
1205 13:31:00.714382 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1206 13:31:00.718024 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1207 13:31:00.718516 ==
1208 13:31:00.721097 Dram Type= 6, Freq= 0, CH_0, rank 1
1209 13:31:00.723940 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1210 13:31:00.724365 ==
1211 13:31:00.737749 TX Vref=22, minBit 0, minWin=27, winSum=446
1212 13:31:00.741287 TX Vref=24, minBit 7, minWin=27, winSum=448
1213 13:31:00.744305 TX Vref=26, minBit 0, minWin=28, winSum=454
1214 13:31:00.747449 TX Vref=28, minBit 2, minWin=28, winSum=458
1215 13:31:00.751091 TX Vref=30, minBit 2, minWin=28, winSum=458
1216 13:31:00.754240 TX Vref=32, minBit 2, minWin=28, winSum=458
1217 13:31:00.760713 [TxChooseVref] Worse bit 2, Min win 28, Win sum 458, Final Vref 28
1218 13:31:00.760845
1219 13:31:00.764490 Final TX Range 1 Vref 28
1220 13:31:00.764600
1221 13:31:00.764669 ==
1222 13:31:00.767748 Dram Type= 6, Freq= 0, CH_0, rank 1
1223 13:31:00.771467 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1224 13:31:00.771605 ==
1225 13:31:00.771700
1226 13:31:00.771785
1227 13:31:00.775441 TX Vref Scan disable
1228 13:31:00.779183 == TX Byte 0 ==
1229 13:31:00.782661 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1230 13:31:00.785479 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1231 13:31:00.785551 == TX Byte 1 ==
1232 13:31:00.792830 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1233 13:31:00.796252 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1234 13:31:00.796356
1235 13:31:00.796438 [DATLAT]
1236 13:31:00.799834 Freq=800, CH0 RK1
1237 13:31:00.799951
1238 13:31:00.800036 DATLAT Default: 0x9
1239 13:31:00.803606 0, 0xFFFF, sum = 0
1240 13:31:00.803684 1, 0xFFFF, sum = 0
1241 13:31:00.806603 2, 0xFFFF, sum = 0
1242 13:31:00.806663 3, 0xFFFF, sum = 0
1243 13:31:00.810111 4, 0xFFFF, sum = 0
1244 13:31:00.810171 5, 0xFFFF, sum = 0
1245 13:31:00.813320 6, 0xFFFF, sum = 0
1246 13:31:00.813376 7, 0xFFFF, sum = 0
1247 13:31:00.816760 8, 0x0, sum = 1
1248 13:31:00.816834 9, 0x0, sum = 2
1249 13:31:00.819944 10, 0x0, sum = 3
1250 13:31:00.820001 11, 0x0, sum = 4
1251 13:31:00.820049 best_step = 9
1252 13:31:00.823291
1253 13:31:00.823359 ==
1254 13:31:00.826394 Dram Type= 6, Freq= 0, CH_0, rank 1
1255 13:31:00.830153 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1256 13:31:00.830233 ==
1257 13:31:00.830287 RX Vref Scan: 0
1258 13:31:00.830335
1259 13:31:00.833166 RX Vref 0 -> 0, step: 1
1260 13:31:00.833308
1261 13:31:00.836766 RX Delay -111 -> 252, step: 8
1262 13:31:00.839726 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1263 13:31:00.846165 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1264 13:31:00.849518 iDelay=217, Bit 2, Center 80 (-39 ~ 200) 240
1265 13:31:00.853161 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1266 13:31:00.856418 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1267 13:31:00.859468 iDelay=217, Bit 5, Center 72 (-47 ~ 192) 240
1268 13:31:00.866460 iDelay=217, Bit 6, Center 96 (-23 ~ 216) 240
1269 13:31:00.869491 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1270 13:31:00.873141 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1271 13:31:00.876192 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1272 13:31:00.879795 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1273 13:31:00.886081 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1274 13:31:00.889314 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1275 13:31:00.892916 iDelay=217, Bit 13, Center 80 (-39 ~ 200) 240
1276 13:31:00.896400 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1277 13:31:00.899318 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1278 13:31:00.902816 ==
1279 13:31:00.906644 Dram Type= 6, Freq= 0, CH_0, rank 1
1280 13:31:00.909718 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1281 13:31:00.909777 ==
1282 13:31:00.909842 DQS Delay:
1283 13:31:00.912688 DQS0 = 0, DQS1 = 0
1284 13:31:00.912764 DQM Delay:
1285 13:31:00.916262 DQM0 = 85, DQM1 = 74
1286 13:31:00.916345 DQ Delay:
1287 13:31:00.919649 DQ0 =80, DQ1 =88, DQ2 =80, DQ3 =80
1288 13:31:00.922997 DQ4 =88, DQ5 =72, DQ6 =96, DQ7 =96
1289 13:31:00.926334 DQ8 =64, DQ9 =60, DQ10 =72, DQ11 =64
1290 13:31:00.930270 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1291 13:31:00.930708
1292 13:31:00.930956
1293 13:31:00.936473 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f3f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1294 13:31:00.939982 CH0 RK1: MR19=606, MR18=3F3F
1295 13:31:00.946835 CH0_RK1: MR19=0x606, MR18=0x3F3F, DQSOSC=393, MR23=63, INC=95, DEC=63
1296 13:31:00.949738 [RxdqsGatingPostProcess] freq 800
1297 13:31:00.953658 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1298 13:31:00.957082 Pre-setting of DQS Precalculation
1299 13:31:00.963553 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1300 13:31:00.963903 ==
1301 13:31:00.966482 Dram Type= 6, Freq= 0, CH_1, rank 0
1302 13:31:00.969978 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1303 13:31:00.970196 ==
1304 13:31:00.976619 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1305 13:31:00.983099 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1306 13:31:00.990319 [CA 0] Center 37 (6~68) winsize 63
1307 13:31:00.994034 [CA 1] Center 37 (6~68) winsize 63
1308 13:31:00.996895 [CA 2] Center 34 (4~65) winsize 62
1309 13:31:01.000124 [CA 3] Center 34 (4~65) winsize 62
1310 13:31:01.003730 [CA 4] Center 33 (3~64) winsize 62
1311 13:31:01.006793 [CA 5] Center 33 (3~64) winsize 62
1312 13:31:01.006877
1313 13:31:01.009826 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1314 13:31:01.009887
1315 13:31:01.013288 [CATrainingPosCal] consider 1 rank data
1316 13:31:01.016645 u2DelayCellTimex100 = 270/100 ps
1317 13:31:01.019909 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1318 13:31:01.023463 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1319 13:31:01.030398 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1320 13:31:01.033910 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1321 13:31:01.037067 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1322 13:31:01.040777 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1323 13:31:01.041215
1324 13:31:01.044133 CA PerBit enable=1, Macro0, CA PI delay=33
1325 13:31:01.044648
1326 13:31:01.047720 [CBTSetCACLKResult] CA Dly = 33
1327 13:31:01.048201 CS Dly: 5 (0~36)
1328 13:31:01.048504 ==
1329 13:31:01.050488 Dram Type= 6, Freq= 0, CH_1, rank 1
1330 13:31:01.057198 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1331 13:31:01.057658 ==
1332 13:31:01.061003 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1333 13:31:01.067304 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1334 13:31:01.076191 [CA 0] Center 37 (6~68) winsize 63
1335 13:31:01.079489 [CA 1] Center 37 (6~68) winsize 63
1336 13:31:01.082628 [CA 2] Center 34 (4~65) winsize 62
1337 13:31:01.086412 [CA 3] Center 34 (4~65) winsize 62
1338 13:31:01.089924 [CA 4] Center 33 (3~64) winsize 62
1339 13:31:01.092635 [CA 5] Center 33 (3~64) winsize 62
1340 13:31:01.092978
1341 13:31:01.096126 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1342 13:31:01.096574
1343 13:31:01.099562 [CATrainingPosCal] consider 2 rank data
1344 13:31:01.103096 u2DelayCellTimex100 = 270/100 ps
1345 13:31:01.106127 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1346 13:31:01.109463 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1347 13:31:01.115945 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1348 13:31:01.119570 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1349 13:31:01.122775 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1350 13:31:01.125744 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1351 13:31:01.126013
1352 13:31:01.129575 CA PerBit enable=1, Macro0, CA PI delay=33
1353 13:31:01.130062
1354 13:31:01.133016 [CBTSetCACLKResult] CA Dly = 33
1355 13:31:01.133500 CS Dly: 5 (0~37)
1356 13:31:01.133770
1357 13:31:01.136420 ----->DramcWriteLeveling(PI) begin...
1358 13:31:01.139410 ==
1359 13:31:01.142829 Dram Type= 6, Freq= 0, CH_1, rank 0
1360 13:31:01.146834 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1361 13:31:01.147351 ==
1362 13:31:01.149646 Write leveling (Byte 0): 23 => 23
1363 13:31:01.153287 Write leveling (Byte 1): 27 => 27
1364 13:31:01.156646 DramcWriteLeveling(PI) end<-----
1365 13:31:01.157101
1366 13:31:01.157352 ==
1367 13:31:01.159339 Dram Type= 6, Freq= 0, CH_1, rank 0
1368 13:31:01.162802 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1369 13:31:01.163187 ==
1370 13:31:01.166781 [Gating] SW mode calibration
1371 13:31:01.173274 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1372 13:31:01.176192 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1373 13:31:01.183183 0 6 0 | B1->B0 | 3030 2424 | 0 0 | (0 1) (1 0)
1374 13:31:01.186477 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1375 13:31:01.189671 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1376 13:31:01.196501 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1377 13:31:01.199242 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1378 13:31:01.202962 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1379 13:31:01.210304 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1380 13:31:01.213019 0 6 28 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
1381 13:31:01.215923 0 7 0 | B1->B0 | 2d2d 4040 | 1 0 | (0 0) (1 1)
1382 13:31:01.222783 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1383 13:31:01.226104 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1384 13:31:01.230087 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1385 13:31:01.236889 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1386 13:31:01.240111 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1387 13:31:01.243358 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1388 13:31:01.249543 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1389 13:31:01.253050 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1390 13:31:01.255945 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1391 13:31:01.262802 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1392 13:31:01.265960 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1393 13:31:01.269600 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1394 13:31:01.272612 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1395 13:31:01.279676 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1396 13:31:01.283095 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1397 13:31:01.286310 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1398 13:31:01.293071 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1399 13:31:01.296337 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1400 13:31:01.299177 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1401 13:31:01.306149 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1402 13:31:01.309517 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1403 13:31:01.312713 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1404 13:31:01.319383 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1405 13:31:01.322974 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1406 13:31:01.326165 Total UI for P1: 0, mck2ui 16
1407 13:31:01.329265 best dqsien dly found for B0: ( 0, 9, 30)
1408 13:31:01.332582 Total UI for P1: 0, mck2ui 16
1409 13:31:01.335975 best dqsien dly found for B1: ( 0, 9, 30)
1410 13:31:01.339505 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1411 13:31:01.342802 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1412 13:31:01.343261
1413 13:31:01.346622 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1414 13:31:01.349500 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1415 13:31:01.352868 [Gating] SW calibration Done
1416 13:31:01.353214 ==
1417 13:31:01.356675 Dram Type= 6, Freq= 0, CH_1, rank 0
1418 13:31:01.359509 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1419 13:31:01.359877 ==
1420 13:31:01.362487 RX Vref Scan: 0
1421 13:31:01.362859
1422 13:31:01.366476 RX Vref 0 -> 0, step: 1
1423 13:31:01.366822
1424 13:31:01.369419 RX Delay -130 -> 252, step: 16
1425 13:31:01.372944 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1426 13:31:01.376213 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1427 13:31:01.379606 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1428 13:31:01.382670 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1429 13:31:01.386894 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1430 13:31:01.392877 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1431 13:31:01.396271 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1432 13:31:01.399323 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1433 13:31:01.402842 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1434 13:31:01.406670 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1435 13:31:01.413221 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1436 13:31:01.416533 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1437 13:31:01.419361 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1438 13:31:01.422841 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1439 13:31:01.425975 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1440 13:31:01.433640 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1441 13:31:01.434082 ==
1442 13:31:01.437551 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 13:31:01.440920 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1444 13:31:01.441310 ==
1445 13:31:01.441557 DQS Delay:
1446 13:31:01.444403 DQS0 = 0, DQS1 = 0
1447 13:31:01.444780 DQM Delay:
1448 13:31:01.445063 DQM0 = 81, DQM1 = 73
1449 13:31:01.448208 DQ Delay:
1450 13:31:01.448769 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1451 13:31:01.451909 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1452 13:31:01.456084 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1453 13:31:01.459285 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1454 13:31:01.459631
1455 13:31:01.459877
1456 13:31:01.460096 ==
1457 13:31:01.463018 Dram Type= 6, Freq= 0, CH_1, rank 0
1458 13:31:01.466219 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1459 13:31:01.466296 ==
1460 13:31:01.466349
1461 13:31:01.469331
1462 13:31:01.469405 TX Vref Scan disable
1463 13:31:01.473087 == TX Byte 0 ==
1464 13:31:01.476323 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1465 13:31:01.479659 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1466 13:31:01.483435 == TX Byte 1 ==
1467 13:31:01.486256 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1468 13:31:01.490441 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1469 13:31:01.490938 ==
1470 13:31:01.493847 Dram Type= 6, Freq= 0, CH_1, rank 0
1471 13:31:01.499515 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1472 13:31:01.499863 ==
1473 13:31:01.511532 TX Vref=22, minBit 3, minWin=27, winSum=445
1474 13:31:01.514913 TX Vref=24, minBit 9, minWin=27, winSum=448
1475 13:31:01.518650 TX Vref=26, minBit 9, minWin=27, winSum=449
1476 13:31:01.522063 TX Vref=28, minBit 0, minWin=28, winSum=457
1477 13:31:01.525349 TX Vref=30, minBit 0, minWin=28, winSum=459
1478 13:31:01.528357 TX Vref=32, minBit 0, minWin=28, winSum=455
1479 13:31:01.535371 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 30
1480 13:31:01.535821
1481 13:31:01.538959 Final TX Range 1 Vref 30
1482 13:31:01.539372
1483 13:31:01.539619 ==
1484 13:31:01.542247 Dram Type= 6, Freq= 0, CH_1, rank 0
1485 13:31:01.545536 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1486 13:31:01.545981 ==
1487 13:31:01.546231
1488 13:31:01.546448
1489 13:31:01.548562 TX Vref Scan disable
1490 13:31:01.551894 == TX Byte 0 ==
1491 13:31:01.555552 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1492 13:31:01.559227 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1493 13:31:01.562108 == TX Byte 1 ==
1494 13:31:01.565312 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1495 13:31:01.568433 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1496 13:31:01.568879
1497 13:31:01.571898 [DATLAT]
1498 13:31:01.572240 Freq=800, CH1 RK0
1499 13:31:01.572509
1500 13:31:01.575614 DATLAT Default: 0xa
1501 13:31:01.576168 0, 0xFFFF, sum = 0
1502 13:31:01.579059 1, 0xFFFF, sum = 0
1503 13:31:01.579469 2, 0xFFFF, sum = 0
1504 13:31:01.582554 3, 0xFFFF, sum = 0
1505 13:31:01.583014 4, 0xFFFF, sum = 0
1506 13:31:01.585675 5, 0xFFFF, sum = 0
1507 13:31:01.586117 6, 0xFFFF, sum = 0
1508 13:31:01.588913 7, 0xFFFF, sum = 0
1509 13:31:01.589425 8, 0x0, sum = 1
1510 13:31:01.591922 9, 0x0, sum = 2
1511 13:31:01.592270 10, 0x0, sum = 3
1512 13:31:01.595343 11, 0x0, sum = 4
1513 13:31:01.595694 best_step = 9
1514 13:31:01.595936
1515 13:31:01.596154 ==
1516 13:31:01.598978 Dram Type= 6, Freq= 0, CH_1, rank 0
1517 13:31:01.605391 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1518 13:31:01.605857 ==
1519 13:31:01.606127 RX Vref Scan: 1
1520 13:31:01.606358
1521 13:31:01.608661 Set Vref Range= 32 -> 127
1522 13:31:01.609007
1523 13:31:01.612037 RX Vref 32 -> 127, step: 1
1524 13:31:01.612430
1525 13:31:01.612681 RX Delay -111 -> 252, step: 8
1526 13:31:01.612900
1527 13:31:01.615332 Set Vref, RX VrefLevel [Byte0]: 32
1528 13:31:01.618506 [Byte1]: 32
1529 13:31:01.622830
1530 13:31:01.623290 Set Vref, RX VrefLevel [Byte0]: 33
1531 13:31:01.625805 [Byte1]: 33
1532 13:31:01.630722
1533 13:31:01.631067 Set Vref, RX VrefLevel [Byte0]: 34
1534 13:31:01.634069 [Byte1]: 34
1535 13:31:01.638477
1536 13:31:01.638933 Set Vref, RX VrefLevel [Byte0]: 35
1537 13:31:01.641409 [Byte1]: 35
1538 13:31:01.645746
1539 13:31:01.646139 Set Vref, RX VrefLevel [Byte0]: 36
1540 13:31:01.649022 [Byte1]: 36
1541 13:31:01.654111
1542 13:31:01.654567 Set Vref, RX VrefLevel [Byte0]: 37
1543 13:31:01.657392 [Byte1]: 37
1544 13:31:01.661135
1545 13:31:01.661491 Set Vref, RX VrefLevel [Byte0]: 38
1546 13:31:01.663908 [Byte1]: 38
1547 13:31:01.668842
1548 13:31:01.669334 Set Vref, RX VrefLevel [Byte0]: 39
1549 13:31:01.672017 [Byte1]: 39
1550 13:31:01.676171
1551 13:31:01.676691 Set Vref, RX VrefLevel [Byte0]: 40
1552 13:31:01.679754 [Byte1]: 40
1553 13:31:01.684156
1554 13:31:01.684691 Set Vref, RX VrefLevel [Byte0]: 41
1555 13:31:01.687122 [Byte1]: 41
1556 13:31:01.691663
1557 13:31:01.692227 Set Vref, RX VrefLevel [Byte0]: 42
1558 13:31:01.694925 [Byte1]: 42
1559 13:31:01.699224
1560 13:31:01.699713 Set Vref, RX VrefLevel [Byte0]: 43
1561 13:31:01.702424 [Byte1]: 43
1562 13:31:01.706937
1563 13:31:01.707318 Set Vref, RX VrefLevel [Byte0]: 44
1564 13:31:01.710132 [Byte1]: 44
1565 13:31:01.714924
1566 13:31:01.715388 Set Vref, RX VrefLevel [Byte0]: 45
1567 13:31:01.717948 [Byte1]: 45
1568 13:31:01.722109
1569 13:31:01.722566 Set Vref, RX VrefLevel [Byte0]: 46
1570 13:31:01.725763 [Byte1]: 46
1571 13:31:01.730170
1572 13:31:01.730665 Set Vref, RX VrefLevel [Byte0]: 47
1573 13:31:01.733451 [Byte1]: 47
1574 13:31:01.737454
1575 13:31:01.737940 Set Vref, RX VrefLevel [Byte0]: 48
1576 13:31:01.741096 [Byte1]: 48
1577 13:31:01.745124
1578 13:31:01.745505 Set Vref, RX VrefLevel [Byte0]: 49
1579 13:31:01.748076 [Byte1]: 49
1580 13:31:01.752750
1581 13:31:01.753098 Set Vref, RX VrefLevel [Byte0]: 50
1582 13:31:01.756259 [Byte1]: 50
1583 13:31:01.760421
1584 13:31:01.760876 Set Vref, RX VrefLevel [Byte0]: 51
1585 13:31:01.763716 [Byte1]: 51
1586 13:31:01.768593
1587 13:31:01.769080 Set Vref, RX VrefLevel [Byte0]: 52
1588 13:31:01.771459 [Byte1]: 52
1589 13:31:01.776418
1590 13:31:01.776912 Set Vref, RX VrefLevel [Byte0]: 53
1591 13:31:01.779508 [Byte1]: 53
1592 13:31:01.783719
1593 13:31:01.784214 Set Vref, RX VrefLevel [Byte0]: 54
1594 13:31:01.786562 [Byte1]: 54
1595 13:31:01.791260
1596 13:31:01.791747 Set Vref, RX VrefLevel [Byte0]: 55
1597 13:31:01.794417 [Byte1]: 55
1598 13:31:01.798677
1599 13:31:01.799164 Set Vref, RX VrefLevel [Byte0]: 56
1600 13:31:01.801996 [Byte1]: 56
1601 13:31:01.806802
1602 13:31:01.807288 Set Vref, RX VrefLevel [Byte0]: 57
1603 13:31:01.809548 [Byte1]: 57
1604 13:31:01.813810
1605 13:31:01.814187 Set Vref, RX VrefLevel [Byte0]: 58
1606 13:31:01.817172 [Byte1]: 58
1607 13:31:01.821768
1608 13:31:01.822255 Set Vref, RX VrefLevel [Byte0]: 59
1609 13:31:01.825514 [Byte1]: 59
1610 13:31:01.829762
1611 13:31:01.830202 Set Vref, RX VrefLevel [Byte0]: 60
1612 13:31:01.832780 [Byte1]: 60
1613 13:31:01.837147
1614 13:31:01.837633 Set Vref, RX VrefLevel [Byte0]: 61
1615 13:31:01.839878 [Byte1]: 61
1616 13:31:01.844580
1617 13:31:01.845063 Set Vref, RX VrefLevel [Byte0]: 62
1618 13:31:01.847952 [Byte1]: 62
1619 13:31:01.852819
1620 13:31:01.853318 Set Vref, RX VrefLevel [Byte0]: 63
1621 13:31:01.855420 [Byte1]: 63
1622 13:31:01.859651
1623 13:31:01.860029 Set Vref, RX VrefLevel [Byte0]: 64
1624 13:31:01.863569 [Byte1]: 64
1625 13:31:01.867576
1626 13:31:01.868072 Set Vref, RX VrefLevel [Byte0]: 65
1627 13:31:01.870980 [Byte1]: 65
1628 13:31:01.875235
1629 13:31:01.875725 Set Vref, RX VrefLevel [Byte0]: 66
1630 13:31:01.878640 [Byte1]: 66
1631 13:31:01.883039
1632 13:31:01.883532 Set Vref, RX VrefLevel [Byte0]: 67
1633 13:31:01.886209 [Byte1]: 67
1634 13:31:01.890360
1635 13:31:01.890882 Set Vref, RX VrefLevel [Byte0]: 68
1636 13:31:01.893589 [Byte1]: 68
1637 13:31:01.898042
1638 13:31:01.898523 Set Vref, RX VrefLevel [Byte0]: 69
1639 13:31:01.901572 [Byte1]: 69
1640 13:31:01.905629
1641 13:31:01.906011 Set Vref, RX VrefLevel [Byte0]: 70
1642 13:31:01.909285 [Byte1]: 70
1643 13:31:01.913550
1644 13:31:01.913994 Set Vref, RX VrefLevel [Byte0]: 71
1645 13:31:01.916446 [Byte1]: 71
1646 13:31:01.921155
1647 13:31:01.921672 Set Vref, RX VrefLevel [Byte0]: 72
1648 13:31:01.924260 [Byte1]: 72
1649 13:31:01.928548
1650 13:31:01.929017 Set Vref, RX VrefLevel [Byte0]: 73
1651 13:31:01.932609 [Byte1]: 73
1652 13:31:01.936323
1653 13:31:01.936811 Set Vref, RX VrefLevel [Byte0]: 74
1654 13:31:01.940029 [Byte1]: 74
1655 13:31:01.944176
1656 13:31:01.944700 Set Vref, RX VrefLevel [Byte0]: 75
1657 13:31:01.947671 [Byte1]: 75
1658 13:31:01.951682
1659 13:31:01.952165 Set Vref, RX VrefLevel [Byte0]: 76
1660 13:31:01.955167 [Byte1]: 76
1661 13:31:01.959803
1662 13:31:01.960329 Set Vref, RX VrefLevel [Byte0]: 77
1663 13:31:01.962936 [Byte1]: 77
1664 13:31:01.967532
1665 13:31:01.968009 Final RX Vref Byte 0 = 60 to rank0
1666 13:31:01.969956 Final RX Vref Byte 1 = 57 to rank0
1667 13:31:01.973680 Final RX Vref Byte 0 = 60 to rank1
1668 13:31:01.976733 Final RX Vref Byte 1 = 57 to rank1==
1669 13:31:01.980122 Dram Type= 6, Freq= 0, CH_1, rank 0
1670 13:31:01.986928 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1671 13:31:01.987421 ==
1672 13:31:01.987696 DQS Delay:
1673 13:31:01.987932 DQS0 = 0, DQS1 = 0
1674 13:31:01.990574 DQM Delay:
1675 13:31:01.991067 DQM0 = 81, DQM1 = 74
1676 13:31:01.993748 DQ Delay:
1677 13:31:01.997072 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =80
1678 13:31:02.000075 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
1679 13:31:02.003285 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =64
1680 13:31:02.006824 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1681 13:31:02.007320
1682 13:31:02.007597
1683 13:31:02.014228 [DQSOSCAuto] RK0, (LSB)MR18= 0x5252, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
1684 13:31:02.017680 CH1 RK0: MR19=606, MR18=5252
1685 13:31:02.021232 CH1_RK0: MR19=0x606, MR18=0x5252, DQSOSC=389, MR23=63, INC=97, DEC=65
1686 13:31:02.021721
1687 13:31:02.027818 ----->DramcWriteLeveling(PI) begin...
1688 13:31:02.028406 ==
1689 13:31:02.031393 Dram Type= 6, Freq= 0, CH_1, rank 1
1690 13:31:02.034425 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1691 13:31:02.034814 ==
1692 13:31:02.037663 Write leveling (Byte 0): 24 => 24
1693 13:31:02.040863 Write leveling (Byte 1): 24 => 24
1694 13:31:02.044389 DramcWriteLeveling(PI) end<-----
1695 13:31:02.044879
1696 13:31:02.045148 ==
1697 13:31:02.047536 Dram Type= 6, Freq= 0, CH_1, rank 1
1698 13:31:02.051242 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1699 13:31:02.051727 ==
1700 13:31:02.054591 [Gating] SW mode calibration
1701 13:31:02.061221 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1702 13:31:02.064086 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1703 13:31:02.070692 0 6 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
1704 13:31:02.074542 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1705 13:31:02.078154 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1706 13:31:02.083947 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1707 13:31:02.087754 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1708 13:31:02.091051 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1709 13:31:02.097504 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1710 13:31:02.100629 0 6 28 | B1->B0 | 2525 2e2e | 0 0 | (0 0) (0 0)
1711 13:31:02.103672 0 7 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
1712 13:31:02.110830 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1713 13:31:02.114537 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1714 13:31:02.117927 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1715 13:31:02.123981 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1716 13:31:02.127636 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1717 13:31:02.131041 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1718 13:31:02.137563 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1719 13:31:02.141115 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1720 13:31:02.144395 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1721 13:31:02.150504 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1722 13:31:02.154190 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1723 13:31:02.158166 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1724 13:31:02.163897 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1725 13:31:02.167555 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1726 13:31:02.171063 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1727 13:31:02.177264 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1728 13:31:02.180734 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1729 13:31:02.184605 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1730 13:31:02.187952 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1731 13:31:02.194092 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1732 13:31:02.197559 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1733 13:31:02.200839 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1734 13:31:02.207364 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1735 13:31:02.210946 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1736 13:31:02.213825 Total UI for P1: 0, mck2ui 16
1737 13:31:02.217033 best dqsien dly found for B0: ( 0, 9, 28)
1738 13:31:02.220998 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1739 13:31:02.224189 Total UI for P1: 0, mck2ui 16
1740 13:31:02.227423 best dqsien dly found for B1: ( 0, 9, 30)
1741 13:31:02.230908 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1742 13:31:02.234061 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1743 13:31:02.234613
1744 13:31:02.240892 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1745 13:31:02.244109 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1746 13:31:02.247353 [Gating] SW calibration Done
1747 13:31:02.247836 ==
1748 13:31:02.250626 Dram Type= 6, Freq= 0, CH_1, rank 1
1749 13:31:02.253896 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1750 13:31:02.254291 ==
1751 13:31:02.254558 RX Vref Scan: 0
1752 13:31:02.254799
1753 13:31:02.257432 RX Vref 0 -> 0, step: 1
1754 13:31:02.257910
1755 13:31:02.260480 RX Delay -130 -> 252, step: 16
1756 13:31:02.264373 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1757 13:31:02.267263 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1758 13:31:02.273654 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1759 13:31:02.277201 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1760 13:31:02.280396 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1761 13:31:02.283700 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1762 13:31:02.287171 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1763 13:31:02.293863 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1764 13:31:02.297158 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1765 13:31:02.300472 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1766 13:31:02.303948 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1767 13:31:02.307266 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1768 13:31:02.313912 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1769 13:31:02.316740 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1770 13:31:02.320524 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1771 13:31:02.323758 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1772 13:31:02.324255 ==
1773 13:31:02.327300 Dram Type= 6, Freq= 0, CH_1, rank 1
1774 13:31:02.333698 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1775 13:31:02.334194 ==
1776 13:31:02.334470 DQS Delay:
1777 13:31:02.337108 DQS0 = 0, DQS1 = 0
1778 13:31:02.337597 DQM Delay:
1779 13:31:02.337875 DQM0 = 86, DQM1 = 74
1780 13:31:02.339868 DQ Delay:
1781 13:31:02.343782 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1782 13:31:02.347129 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1783 13:31:02.350134 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =69
1784 13:31:02.353282 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1785 13:31:02.353668
1786 13:31:02.353949
1787 13:31:02.354186 ==
1788 13:31:02.356755 Dram Type= 6, Freq= 0, CH_1, rank 1
1789 13:31:02.360087 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1790 13:31:02.360619 ==
1791 13:31:02.360900
1792 13:31:02.361136
1793 13:31:02.363175 TX Vref Scan disable
1794 13:31:02.366952 == TX Byte 0 ==
1795 13:31:02.370228 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1796 13:31:02.373137 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1797 13:31:02.376728 == TX Byte 1 ==
1798 13:31:02.380186 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1799 13:31:02.383153 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1800 13:31:02.383543 ==
1801 13:31:02.386718 Dram Type= 6, Freq= 0, CH_1, rank 1
1802 13:31:02.389926 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1803 13:31:02.390460 ==
1804 13:31:02.403983 TX Vref=22, minBit 8, minWin=27, winSum=451
1805 13:31:02.407042 TX Vref=24, minBit 0, minWin=28, winSum=451
1806 13:31:02.410794 TX Vref=26, minBit 8, minWin=27, winSum=454
1807 13:31:02.414169 TX Vref=28, minBit 9, minWin=27, winSum=456
1808 13:31:02.417513 TX Vref=30, minBit 9, minWin=27, winSum=456
1809 13:31:02.420716 TX Vref=32, minBit 0, minWin=28, winSum=457
1810 13:31:02.427589 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 32
1811 13:31:02.428082
1812 13:31:02.431072 Final TX Range 1 Vref 32
1813 13:31:02.431537
1814 13:31:02.431823 ==
1815 13:31:02.434018 Dram Type= 6, Freq= 0, CH_1, rank 1
1816 13:31:02.437501 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1817 13:31:02.437990 ==
1818 13:31:02.438268
1819 13:31:02.440946
1820 13:31:02.441431 TX Vref Scan disable
1821 13:31:02.444094 == TX Byte 0 ==
1822 13:31:02.447749 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1823 13:31:02.450869 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1824 13:31:02.454377 == TX Byte 1 ==
1825 13:31:02.457280 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1826 13:31:02.460857 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1827 13:31:02.464076
1828 13:31:02.464613 [DATLAT]
1829 13:31:02.464903 Freq=800, CH1 RK1
1830 13:31:02.465147
1831 13:31:02.467237 DATLAT Default: 0x9
1832 13:31:02.467613 0, 0xFFFF, sum = 0
1833 13:31:02.471003 1, 0xFFFF, sum = 0
1834 13:31:02.471504 2, 0xFFFF, sum = 0
1835 13:31:02.474464 3, 0xFFFF, sum = 0
1836 13:31:02.474959 4, 0xFFFF, sum = 0
1837 13:31:02.477600 5, 0xFFFF, sum = 0
1838 13:31:02.480901 6, 0xFFFF, sum = 0
1839 13:31:02.481394 7, 0xFFFF, sum = 0
1840 13:31:02.481675 8, 0x0, sum = 1
1841 13:31:02.484217 9, 0x0, sum = 2
1842 13:31:02.484755 10, 0x0, sum = 3
1843 13:31:02.487345 11, 0x0, sum = 4
1844 13:31:02.487832 best_step = 9
1845 13:31:02.488104
1846 13:31:02.488379 ==
1847 13:31:02.491001 Dram Type= 6, Freq= 0, CH_1, rank 1
1848 13:31:02.497295 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1849 13:31:02.497788 ==
1850 13:31:02.498064 RX Vref Scan: 0
1851 13:31:02.498304
1852 13:31:02.500363 RX Vref 0 -> 0, step: 1
1853 13:31:02.500852
1854 13:31:02.503585 RX Delay -111 -> 252, step: 8
1855 13:31:02.507160 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1856 13:31:02.510905 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
1857 13:31:02.517367 iDelay=209, Bit 2, Center 72 (-47 ~ 192) 240
1858 13:31:02.520521 iDelay=209, Bit 3, Center 80 (-39 ~ 200) 240
1859 13:31:02.523732 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1860 13:31:02.526893 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
1861 13:31:02.530415 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1862 13:31:02.537705 iDelay=209, Bit 7, Center 80 (-39 ~ 200) 240
1863 13:31:02.540265 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1864 13:31:02.543975 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
1865 13:31:02.547686 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1866 13:31:02.550882 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1867 13:31:02.556939 iDelay=209, Bit 12, Center 88 (-31 ~ 208) 240
1868 13:31:02.560236 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1869 13:31:02.563971 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1870 13:31:02.567026 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1871 13:31:02.567520 ==
1872 13:31:02.570777 Dram Type= 6, Freq= 0, CH_1, rank 1
1873 13:31:02.577274 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1874 13:31:02.577772 ==
1875 13:31:02.578050 DQS Delay:
1876 13:31:02.578286 DQS0 = 0, DQS1 = 0
1877 13:31:02.580318 DQM Delay:
1878 13:31:02.580811 DQM0 = 83, DQM1 = 75
1879 13:31:02.584020 DQ Delay:
1880 13:31:02.587224 DQ0 =88, DQ1 =80, DQ2 =72, DQ3 =80
1881 13:31:02.587715 DQ4 =84, DQ5 =92, DQ6 =92, DQ7 =80
1882 13:31:02.591098 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =68
1883 13:31:02.597100 DQ12 =88, DQ13 =84, DQ14 =80, DQ15 =84
1884 13:31:02.597586
1885 13:31:02.597862
1886 13:31:02.603979 [DQSOSCAuto] RK1, (LSB)MR18= 0x3737, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1887 13:31:02.607044 CH1 RK1: MR19=606, MR18=3737
1888 13:31:02.613658 CH1_RK1: MR19=0x606, MR18=0x3737, DQSOSC=395, MR23=63, INC=94, DEC=63
1889 13:31:02.616773 [RxdqsGatingPostProcess] freq 800
1890 13:31:02.620869 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1891 13:31:02.623177 Pre-setting of DQS Precalculation
1892 13:31:02.630290 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1893 13:31:02.637044 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1894 13:31:02.643992 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1895 13:31:02.644526
1896 13:31:02.644804
1897 13:31:02.647220 [Calibration Summary] 1600 Mbps
1898 13:31:02.647728 CH 0, Rank 0
1899 13:31:02.650576 SW Impedance : PASS
1900 13:31:02.651076 DUTY Scan : NO K
1901 13:31:02.653848 ZQ Calibration : PASS
1902 13:31:02.656967 Jitter Meter : NO K
1903 13:31:02.657420 CBT Training : PASS
1904 13:31:02.660359 Write leveling : PASS
1905 13:31:02.663992 RX DQS gating : PASS
1906 13:31:02.664531 RX DQ/DQS(RDDQC) : PASS
1907 13:31:02.667165 TX DQ/DQS : PASS
1908 13:31:02.670469 RX DATLAT : PASS
1909 13:31:02.670958 RX DQ/DQS(Engine): PASS
1910 13:31:02.674225 TX OE : NO K
1911 13:31:02.674715 All Pass.
1912 13:31:02.674995
1913 13:31:02.677030 CH 0, Rank 1
1914 13:31:02.677490 SW Impedance : PASS
1915 13:31:02.680665 DUTY Scan : NO K
1916 13:31:02.683662 ZQ Calibration : PASS
1917 13:31:02.684148 Jitter Meter : NO K
1918 13:31:02.686992 CBT Training : PASS
1919 13:31:02.690264 Write leveling : PASS
1920 13:31:02.690748 RX DQS gating : PASS
1921 13:31:02.693663 RX DQ/DQS(RDDQC) : PASS
1922 13:31:02.694142 TX DQ/DQS : PASS
1923 13:31:02.696889 RX DATLAT : PASS
1924 13:31:02.700243 RX DQ/DQS(Engine): PASS
1925 13:31:02.700774 TX OE : NO K
1926 13:31:02.703804 All Pass.
1927 13:31:02.704329
1928 13:31:02.704647 CH 1, Rank 0
1929 13:31:02.706619 SW Impedance : PASS
1930 13:31:02.707039 DUTY Scan : NO K
1931 13:31:02.710061 ZQ Calibration : PASS
1932 13:31:02.713347 Jitter Meter : NO K
1933 13:31:02.713736 CBT Training : PASS
1934 13:31:02.716680 Write leveling : PASS
1935 13:31:02.719642 RX DQS gating : PASS
1936 13:31:02.720136 RX DQ/DQS(RDDQC) : PASS
1937 13:31:02.723259 TX DQ/DQS : PASS
1938 13:31:02.726584 RX DATLAT : PASS
1939 13:31:02.726984 RX DQ/DQS(Engine): PASS
1940 13:31:02.729925 TX OE : NO K
1941 13:31:02.730292 All Pass.
1942 13:31:02.730561
1943 13:31:02.733171 CH 1, Rank 1
1944 13:31:02.733540 SW Impedance : PASS
1945 13:31:02.736796 DUTY Scan : NO K
1946 13:31:02.739684 ZQ Calibration : PASS
1947 13:31:02.740079 Jitter Meter : NO K
1948 13:31:02.743813 CBT Training : PASS
1949 13:31:02.744351 Write leveling : PASS
1950 13:31:02.746807 RX DQS gating : PASS
1951 13:31:02.749873 RX DQ/DQS(RDDQC) : PASS
1952 13:31:02.750311 TX DQ/DQS : PASS
1953 13:31:02.753474 RX DATLAT : PASS
1954 13:31:02.756827 RX DQ/DQS(Engine): PASS
1955 13:31:02.757178 TX OE : NO K
1956 13:31:02.759765 All Pass.
1957 13:31:02.760115
1958 13:31:02.760397 DramC Write-DBI off
1959 13:31:02.763458 PER_BANK_REFRESH: Hybrid Mode
1960 13:31:02.766586 TX_TRACKING: ON
1961 13:31:02.770124 [GetDramInforAfterCalByMRR] Vendor 6.
1962 13:31:02.773384 [GetDramInforAfterCalByMRR] Revision 606.
1963 13:31:02.777099 [GetDramInforAfterCalByMRR] Revision 2 0.
1964 13:31:02.777583 MR0 0x3939
1965 13:31:02.777864 MR8 0x1111
1966 13:31:02.780330 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1967 13:31:02.783476
1968 13:31:02.783958 MR0 0x3939
1969 13:31:02.784249 MR8 0x1111
1970 13:31:02.786620 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1971 13:31:02.787107
1972 13:31:02.796971 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1973 13:31:02.799962 [FAST_K] Save calibration result to emmc
1974 13:31:02.803689 [FAST_K] Save calibration result to emmc
1975 13:31:02.806601 dram_init: config_dvfs: 1
1976 13:31:02.809950 dramc_set_vcore_voltage set vcore to 662500
1977 13:31:02.813217 Read voltage for 1200, 2
1978 13:31:02.813656 Vio18 = 0
1979 13:31:02.813928 Vcore = 662500
1980 13:31:02.816919 Vdram = 0
1981 13:31:02.817397 Vddq = 0
1982 13:31:02.817684 Vmddr = 0
1983 13:31:02.823513 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1984 13:31:02.826653 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1985 13:31:02.829572 MEM_TYPE=3, freq_sel=15
1986 13:31:02.833709 sv_algorithm_assistance_LP4_1600
1987 13:31:02.836413 ============ PULL DRAM RESETB DOWN ============
1988 13:31:02.840335 ========== PULL DRAM RESETB DOWN end =========
1989 13:31:02.847308 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1990 13:31:02.850022 ===================================
1991 13:31:02.850379 LPDDR4 DRAM CONFIGURATION
1992 13:31:02.853092 ===================================
1993 13:31:02.856551 EX_ROW_EN[0] = 0x0
1994 13:31:02.859677 EX_ROW_EN[1] = 0x0
1995 13:31:02.860024 LP4Y_EN = 0x0
1996 13:31:02.863591 WORK_FSP = 0x0
1997 13:31:02.864047 WL = 0x4
1998 13:31:02.866573 RL = 0x4
1999 13:31:02.866957 BL = 0x2
2000 13:31:02.870182 RPST = 0x0
2001 13:31:02.870648 RD_PRE = 0x0
2002 13:31:02.873338 WR_PRE = 0x1
2003 13:31:02.873687 WR_PST = 0x0
2004 13:31:02.876641 DBI_WR = 0x0
2005 13:31:02.877092 DBI_RD = 0x0
2006 13:31:02.880030 OTF = 0x1
2007 13:31:02.883280 ===================================
2008 13:31:02.886868 ===================================
2009 13:31:02.887325 ANA top config
2010 13:31:02.890038 ===================================
2011 13:31:02.893541 DLL_ASYNC_EN = 0
2012 13:31:02.896955 ALL_SLAVE_EN = 0
2013 13:31:02.899935 NEW_RANK_MODE = 1
2014 13:31:02.900359 DLL_IDLE_MODE = 1
2015 13:31:02.903339 LP45_APHY_COMB_EN = 1
2016 13:31:02.906348 TX_ODT_DIS = 1
2017 13:31:02.909752 NEW_8X_MODE = 1
2018 13:31:02.913408 ===================================
2019 13:31:02.916899 ===================================
2020 13:31:02.919882 data_rate = 2400
2021 13:31:02.920393 CKR = 1
2022 13:31:02.923535 DQ_P2S_RATIO = 8
2023 13:31:02.926879 ===================================
2024 13:31:02.930019 CA_P2S_RATIO = 8
2025 13:31:02.933659 DQ_CA_OPEN = 0
2026 13:31:02.936381 DQ_SEMI_OPEN = 0
2027 13:31:02.936776 CA_SEMI_OPEN = 0
2028 13:31:02.939869 CA_FULL_RATE = 0
2029 13:31:02.943161 DQ_CKDIV4_EN = 0
2030 13:31:02.946959 CA_CKDIV4_EN = 0
2031 13:31:02.949739 CA_PREDIV_EN = 0
2032 13:31:02.953333 PH8_DLY = 17
2033 13:31:02.953822 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2034 13:31:02.956625 DQ_AAMCK_DIV = 4
2035 13:31:02.960046 CA_AAMCK_DIV = 4
2036 13:31:02.963043 CA_ADMCK_DIV = 4
2037 13:31:02.966108 DQ_TRACK_CA_EN = 0
2038 13:31:02.969994 CA_PICK = 1200
2039 13:31:02.972903 CA_MCKIO = 1200
2040 13:31:02.973321 MCKIO_SEMI = 0
2041 13:31:02.976505 PLL_FREQ = 2366
2042 13:31:02.980328 DQ_UI_PI_RATIO = 32
2043 13:31:02.983264 CA_UI_PI_RATIO = 0
2044 13:31:02.986462 ===================================
2045 13:31:02.989652 ===================================
2046 13:31:02.993679 memory_type:LPDDR4
2047 13:31:02.994169 GP_NUM : 10
2048 13:31:02.996943 SRAM_EN : 1
2049 13:31:02.999921 MD32_EN : 0
2050 13:31:03.000466 ===================================
2051 13:31:03.003333 [ANA_INIT] >>>>>>>>>>>>>>
2052 13:31:03.006348 <<<<<< [CONFIGURE PHASE]: ANA_TX
2053 13:31:03.009938 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2054 13:31:03.013007 ===================================
2055 13:31:03.016091 data_rate = 2400,PCW = 0X5b00
2056 13:31:03.019788 ===================================
2057 13:31:03.023330 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2058 13:31:03.030081 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2059 13:31:03.033714 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2060 13:31:03.039982 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2061 13:31:03.043335 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2062 13:31:03.046850 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2063 13:31:03.047338 [ANA_INIT] flow start
2064 13:31:03.049849 [ANA_INIT] PLL >>>>>>>>
2065 13:31:03.052832 [ANA_INIT] PLL <<<<<<<<
2066 13:31:03.053225 [ANA_INIT] MIDPI >>>>>>>>
2067 13:31:03.056175 [ANA_INIT] MIDPI <<<<<<<<
2068 13:31:03.059902 [ANA_INIT] DLL >>>>>>>>
2069 13:31:03.060431 [ANA_INIT] DLL <<<<<<<<
2070 13:31:03.062859 [ANA_INIT] flow end
2071 13:31:03.066494 ============ LP4 DIFF to SE enter ============
2072 13:31:03.069615 ============ LP4 DIFF to SE exit ============
2073 13:31:03.073191 [ANA_INIT] <<<<<<<<<<<<<
2074 13:31:03.077106 [Flow] Enable top DCM control >>>>>
2075 13:31:03.080059 [Flow] Enable top DCM control <<<<<
2076 13:31:03.083697 Enable DLL master slave shuffle
2077 13:31:03.089585 ==============================================================
2078 13:31:03.090050 Gating Mode config
2079 13:31:03.096214 ==============================================================
2080 13:31:03.096632 Config description:
2081 13:31:03.106539 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2082 13:31:03.113265 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2083 13:31:03.120038 SELPH_MODE 0: By rank 1: By Phase
2084 13:31:03.123553 ==============================================================
2085 13:31:03.126428 GAT_TRACK_EN = 1
2086 13:31:03.129771 RX_GATING_MODE = 2
2087 13:31:03.132958 RX_GATING_TRACK_MODE = 2
2088 13:31:03.136583 SELPH_MODE = 1
2089 13:31:03.139835 PICG_EARLY_EN = 1
2090 13:31:03.143161 VALID_LAT_VALUE = 1
2091 13:31:03.149935 ==============================================================
2092 13:31:03.153008 Enter into Gating configuration >>>>
2093 13:31:03.156203 Exit from Gating configuration <<<<
2094 13:31:03.159720 Enter into DVFS_PRE_config >>>>>
2095 13:31:03.169777 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2096 13:31:03.173057 Exit from DVFS_PRE_config <<<<<
2097 13:31:03.176350 Enter into PICG configuration >>>>
2098 13:31:03.179534 Exit from PICG configuration <<<<
2099 13:31:03.182727 [RX_INPUT] configuration >>>>>
2100 13:31:03.183223 [RX_INPUT] configuration <<<<<
2101 13:31:03.189436 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2102 13:31:03.196130 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2103 13:31:03.200001 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2104 13:31:03.206218 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2105 13:31:03.212741 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2106 13:31:03.219569 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2107 13:31:03.223134 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2108 13:31:03.225856 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2109 13:31:03.232759 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2110 13:31:03.236099 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2111 13:31:03.239716 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2112 13:31:03.242925 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2113 13:31:03.246468 ===================================
2114 13:31:03.249394 LPDDR4 DRAM CONFIGURATION
2115 13:31:03.252648 ===================================
2116 13:31:03.256260 EX_ROW_EN[0] = 0x0
2117 13:31:03.256796 EX_ROW_EN[1] = 0x0
2118 13:31:03.259827 LP4Y_EN = 0x0
2119 13:31:03.260352 WORK_FSP = 0x0
2120 13:31:03.262944 WL = 0x4
2121 13:31:03.263437 RL = 0x4
2122 13:31:03.265930 BL = 0x2
2123 13:31:03.266245 RPST = 0x0
2124 13:31:03.270216 RD_PRE = 0x0
2125 13:31:03.270744 WR_PRE = 0x1
2126 13:31:03.272740 WR_PST = 0x0
2127 13:31:03.273208 DBI_WR = 0x0
2128 13:31:03.275995 DBI_RD = 0x0
2129 13:31:03.276429 OTF = 0x1
2130 13:31:03.279921 ===================================
2131 13:31:03.286191 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2132 13:31:03.289509 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2133 13:31:03.292712 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2134 13:31:03.296510 ===================================
2135 13:31:03.299549 LPDDR4 DRAM CONFIGURATION
2136 13:31:03.303107 ===================================
2137 13:31:03.306162 EX_ROW_EN[0] = 0x10
2138 13:31:03.306656 EX_ROW_EN[1] = 0x0
2139 13:31:03.309133 LP4Y_EN = 0x0
2140 13:31:03.309946 WORK_FSP = 0x0
2141 13:31:03.312761 WL = 0x4
2142 13:31:03.313153 RL = 0x4
2143 13:31:03.315833 BL = 0x2
2144 13:31:03.316224 RPST = 0x0
2145 13:31:03.319929 RD_PRE = 0x0
2146 13:31:03.320422 WR_PRE = 0x1
2147 13:31:03.322859 WR_PST = 0x0
2148 13:31:03.323323 DBI_WR = 0x0
2149 13:31:03.326377 DBI_RD = 0x0
2150 13:31:03.326830 OTF = 0x1
2151 13:31:03.329555 ===================================
2152 13:31:03.336310 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2153 13:31:03.336775 ==
2154 13:31:03.339642 Dram Type= 6, Freq= 0, CH_0, rank 0
2155 13:31:03.343275 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2156 13:31:03.346660 ==
2157 13:31:03.347120 [Duty_Offset_Calibration]
2158 13:31:03.349841 B0:0 B1:2 CA:1
2159 13:31:03.350296
2160 13:31:03.352932 [DutyScan_Calibration_Flow] k_type=0
2161 13:31:03.361156
2162 13:31:03.361639 ==CLK 0==
2163 13:31:03.364970 Final CLK duty delay cell = 0
2164 13:31:03.368035 [0] MAX Duty = 5093%(X100), DQS PI = 12
2165 13:31:03.371311 [0] MIN Duty = 4938%(X100), DQS PI = 52
2166 13:31:03.374676 [0] AVG Duty = 5015%(X100)
2167 13:31:03.375065
2168 13:31:03.377919 CH0 CLK Duty spec in!! Max-Min= 155%
2169 13:31:03.381025 [DutyScan_Calibration_Flow] ====Done====
2170 13:31:03.381409
2171 13:31:03.384200 [DutyScan_Calibration_Flow] k_type=1
2172 13:31:03.401128
2173 13:31:03.401612 ==DQS 0 ==
2174 13:31:03.404062 Final DQS duty delay cell = 0
2175 13:31:03.407384 [0] MAX Duty = 5125%(X100), DQS PI = 20
2176 13:31:03.410666 [0] MIN Duty = 5000%(X100), DQS PI = 6
2177 13:31:03.411089 [0] AVG Duty = 5062%(X100)
2178 13:31:03.414162
2179 13:31:03.414651 ==DQS 1 ==
2180 13:31:03.417102 Final DQS duty delay cell = 0
2181 13:31:03.420272 [0] MAX Duty = 5031%(X100), DQS PI = 56
2182 13:31:03.424142 [0] MIN Duty = 4906%(X100), DQS PI = 16
2183 13:31:03.426998 [0] AVG Duty = 4968%(X100)
2184 13:31:03.427383
2185 13:31:03.430235 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2186 13:31:03.430632
2187 13:31:03.434537 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2188 13:31:03.437024 [DutyScan_Calibration_Flow] ====Done====
2189 13:31:03.437511
2190 13:31:03.440148 [DutyScan_Calibration_Flow] k_type=3
2191 13:31:03.458153
2192 13:31:03.458627 ==DQM 0 ==
2193 13:31:03.461259 Final DQM duty delay cell = 0
2194 13:31:03.464502 [0] MAX Duty = 5124%(X100), DQS PI = 20
2195 13:31:03.467776 [0] MIN Duty = 4969%(X100), DQS PI = 40
2196 13:31:03.471207 [0] AVG Duty = 5046%(X100)
2197 13:31:03.471700
2198 13:31:03.471982 ==DQM 1 ==
2199 13:31:03.474368 Final DQM duty delay cell = 4
2200 13:31:03.478065 [4] MAX Duty = 5187%(X100), DQS PI = 52
2201 13:31:03.481042 [4] MIN Duty = 5000%(X100), DQS PI = 18
2202 13:31:03.484774 [4] AVG Duty = 5093%(X100)
2203 13:31:03.485263
2204 13:31:03.488092 CH0 DQM 0 Duty spec in!! Max-Min= 155%
2205 13:31:03.488636
2206 13:31:03.490959 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2207 13:31:03.494806 [DutyScan_Calibration_Flow] ====Done====
2208 13:31:03.495293
2209 13:31:03.497447 [DutyScan_Calibration_Flow] k_type=2
2210 13:31:03.513063
2211 13:31:03.513544 ==DQ 0 ==
2212 13:31:03.516467 Final DQ duty delay cell = -4
2213 13:31:03.519731 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2214 13:31:03.522797 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2215 13:31:03.526318 [-4] AVG Duty = 4937%(X100)
2216 13:31:03.526856
2217 13:31:03.527157 ==DQ 1 ==
2218 13:31:03.529672 Final DQ duty delay cell = -4
2219 13:31:03.532583 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2220 13:31:03.536269 [-4] MIN Duty = 4876%(X100), DQS PI = 62
2221 13:31:03.539903 [-4] AVG Duty = 4969%(X100)
2222 13:31:03.540451
2223 13:31:03.543027 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2224 13:31:03.543552
2225 13:31:03.546349 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2226 13:31:03.549688 [DutyScan_Calibration_Flow] ====Done====
2227 13:31:03.550179 ==
2228 13:31:03.552869 Dram Type= 6, Freq= 0, CH_1, rank 0
2229 13:31:03.556106 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2230 13:31:03.556674 ==
2231 13:31:03.559613 [Duty_Offset_Calibration]
2232 13:31:03.559996 B0:0 B1:4 CA:-5
2233 13:31:03.560270
2234 13:31:03.563031 [DutyScan_Calibration_Flow] k_type=0
2235 13:31:03.573670
2236 13:31:03.574158 ==CLK 0==
2237 13:31:03.576955 Final CLK duty delay cell = 0
2238 13:31:03.580312 [0] MAX Duty = 5094%(X100), DQS PI = 24
2239 13:31:03.583720 [0] MIN Duty = 4875%(X100), DQS PI = 46
2240 13:31:03.584211 [0] AVG Duty = 4984%(X100)
2241 13:31:03.586863
2242 13:31:03.590206 CH1 CLK Duty spec in!! Max-Min= 219%
2243 13:31:03.593429 [DutyScan_Calibration_Flow] ====Done====
2244 13:31:03.593909
2245 13:31:03.596799 [DutyScan_Calibration_Flow] k_type=1
2246 13:31:03.611967
2247 13:31:03.612486 ==DQS 0 ==
2248 13:31:03.615188 Final DQS duty delay cell = 0
2249 13:31:03.619011 [0] MAX Duty = 5125%(X100), DQS PI = 16
2250 13:31:03.622006 [0] MIN Duty = 4875%(X100), DQS PI = 40
2251 13:31:03.622394 [0] AVG Duty = 5000%(X100)
2252 13:31:03.625437
2253 13:31:03.625804 ==DQS 1 ==
2254 13:31:03.628648 Final DQS duty delay cell = -4
2255 13:31:03.631915 [-4] MAX Duty = 5000%(X100), DQS PI = 4
2256 13:31:03.635278 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2257 13:31:03.639133 [-4] AVG Duty = 4953%(X100)
2258 13:31:03.639621
2259 13:31:03.641875 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2260 13:31:03.642363
2261 13:31:03.645560 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2262 13:31:03.648805 [DutyScan_Calibration_Flow] ====Done====
2263 13:31:03.649288
2264 13:31:03.651949 [DutyScan_Calibration_Flow] k_type=3
2265 13:31:03.666881
2266 13:31:03.667391 ==DQM 0 ==
2267 13:31:03.670356 Final DQM duty delay cell = -4
2268 13:31:03.674202 [-4] MAX Duty = 5093%(X100), DQS PI = 30
2269 13:31:03.677321 [-4] MIN Duty = 4875%(X100), DQS PI = 38
2270 13:31:03.680067 [-4] AVG Duty = 4984%(X100)
2271 13:31:03.680472
2272 13:31:03.680744 ==DQM 1 ==
2273 13:31:03.683866 Final DQM duty delay cell = -4
2274 13:31:03.687223 [-4] MAX Duty = 5062%(X100), DQS PI = 4
2275 13:31:03.690157 [-4] MIN Duty = 4906%(X100), DQS PI = 42
2276 13:31:03.693984 [-4] AVG Duty = 4984%(X100)
2277 13:31:03.694476
2278 13:31:03.696678 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2279 13:31:03.697169
2280 13:31:03.700329 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2281 13:31:03.703319 [DutyScan_Calibration_Flow] ====Done====
2282 13:31:03.703709
2283 13:31:03.707093 [DutyScan_Calibration_Flow] k_type=2
2284 13:31:03.723961
2285 13:31:03.724513 ==DQ 0 ==
2286 13:31:03.727036 Final DQ duty delay cell = 0
2287 13:31:03.731075 [0] MAX Duty = 5062%(X100), DQS PI = 0
2288 13:31:03.734268 [0] MIN Duty = 4969%(X100), DQS PI = 42
2289 13:31:03.734752 [0] AVG Duty = 5015%(X100)
2290 13:31:03.735030
2291 13:31:03.737861 ==DQ 1 ==
2292 13:31:03.738366 Final DQ duty delay cell = 0
2293 13:31:03.744480 [0] MAX Duty = 5000%(X100), DQS PI = 6
2294 13:31:03.747584 [0] MIN Duty = 4907%(X100), DQS PI = 0
2295 13:31:03.748071 [0] AVG Duty = 4953%(X100)
2296 13:31:03.748378
2297 13:31:03.751059 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2298 13:31:03.751439
2299 13:31:03.754326 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2300 13:31:03.757254 [DutyScan_Calibration_Flow] ====Done====
2301 13:31:03.762771 nWR fixed to 30
2302 13:31:03.766212 [ModeRegInit_LP4] CH0 RK0
2303 13:31:03.766476 [ModeRegInit_LP4] CH0 RK1
2304 13:31:03.769049 [ModeRegInit_LP4] CH1 RK0
2305 13:31:03.772971 [ModeRegInit_LP4] CH1 RK1
2306 13:31:03.773355 match AC timing 6
2307 13:31:03.779283 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2308 13:31:03.782999 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2309 13:31:03.786044 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2310 13:31:03.792665 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2311 13:31:03.796626 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2312 13:31:03.797083 ==
2313 13:31:03.799530 Dram Type= 6, Freq= 0, CH_0, rank 0
2314 13:31:03.803029 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2315 13:31:03.803484 ==
2316 13:31:03.809207 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2317 13:31:03.815509 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2318 13:31:03.823342 [CA 0] Center 39 (9~70) winsize 62
2319 13:31:03.826547 [CA 1] Center 39 (9~70) winsize 62
2320 13:31:03.830030 [CA 2] Center 36 (5~67) winsize 63
2321 13:31:03.833528 [CA 3] Center 35 (5~66) winsize 62
2322 13:31:03.836853 [CA 4] Center 34 (3~65) winsize 63
2323 13:31:03.840207 [CA 5] Center 33 (3~64) winsize 62
2324 13:31:03.840774
2325 13:31:03.843527 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2326 13:31:03.843944
2327 13:31:03.846655 [CATrainingPosCal] consider 1 rank data
2328 13:31:03.850232 u2DelayCellTimex100 = 270/100 ps
2329 13:31:03.853402 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2330 13:31:03.856622 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2331 13:31:03.863404 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2332 13:31:03.867089 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2333 13:31:03.869951 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2334 13:31:03.873649 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2335 13:31:03.874098
2336 13:31:03.876812 CA PerBit enable=1, Macro0, CA PI delay=33
2337 13:31:03.877272
2338 13:31:03.879951 [CBTSetCACLKResult] CA Dly = 33
2339 13:31:03.880334 CS Dly: 7 (0~38)
2340 13:31:03.880597 ==
2341 13:31:03.883422 Dram Type= 6, Freq= 0, CH_0, rank 1
2342 13:31:03.889745 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2343 13:31:03.890175 ==
2344 13:31:03.893218 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2345 13:31:03.899548 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2346 13:31:03.908958 [CA 0] Center 39 (8~70) winsize 63
2347 13:31:03.912222 [CA 1] Center 39 (8~70) winsize 63
2348 13:31:03.915411 [CA 2] Center 36 (5~67) winsize 63
2349 13:31:03.918901 [CA 3] Center 35 (4~66) winsize 63
2350 13:31:03.922372 [CA 4] Center 33 (3~64) winsize 62
2351 13:31:03.926040 [CA 5] Center 34 (3~65) winsize 63
2352 13:31:03.926492
2353 13:31:03.928860 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2354 13:31:03.929215
2355 13:31:03.932106 [CATrainingPosCal] consider 2 rank data
2356 13:31:03.935392 u2DelayCellTimex100 = 270/100 ps
2357 13:31:03.939390 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2358 13:31:03.942819 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2359 13:31:03.948991 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2360 13:31:03.952502 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2361 13:31:03.955779 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2362 13:31:03.959167 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2363 13:31:03.959649
2364 13:31:03.962464 CA PerBit enable=1, Macro0, CA PI delay=33
2365 13:31:03.962947
2366 13:31:03.965431 [CBTSetCACLKResult] CA Dly = 33
2367 13:31:03.965811 CS Dly: 7 (0~39)
2368 13:31:03.966073
2369 13:31:03.969583 ----->DramcWriteLeveling(PI) begin...
2370 13:31:03.972542 ==
2371 13:31:03.975745 Dram Type= 6, Freq= 0, CH_0, rank 0
2372 13:31:03.979084 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2373 13:31:03.979571 ==
2374 13:31:03.982798 Write leveling (Byte 0): 28 => 28
2375 13:31:03.985806 Write leveling (Byte 1): 25 => 25
2376 13:31:03.988924 DramcWriteLeveling(PI) end<-----
2377 13:31:03.989407
2378 13:31:03.989673 ==
2379 13:31:03.992469 Dram Type= 6, Freq= 0, CH_0, rank 0
2380 13:31:03.995577 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2381 13:31:03.995955 ==
2382 13:31:03.999018 [Gating] SW mode calibration
2383 13:31:04.005993 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2384 13:31:04.008954 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2385 13:31:04.015381 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2386 13:31:04.018799 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2387 13:31:04.022218 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2388 13:31:04.028392 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2389 13:31:04.032051 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2390 13:31:04.035609 0 11 20 | B1->B0 | 2e2e 2c2c | 0 0 | (1 0) (1 0)
2391 13:31:04.042489 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2392 13:31:04.045238 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2393 13:31:04.048527 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2394 13:31:04.055382 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2395 13:31:04.058836 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2396 13:31:04.061889 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2397 13:31:04.068677 0 12 16 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2398 13:31:04.071799 0 12 20 | B1->B0 | 3939 3d3d | 0 0 | (0 0) (0 0)
2399 13:31:04.075142 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2400 13:31:04.082162 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2401 13:31:04.085783 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2402 13:31:04.088854 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2403 13:31:04.095797 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2404 13:31:04.098493 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2405 13:31:04.101877 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2406 13:31:04.109114 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2407 13:31:04.111640 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2408 13:31:04.115244 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2409 13:31:04.118570 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2410 13:31:04.125300 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2411 13:31:04.128388 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2412 13:31:04.131813 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2413 13:31:04.138606 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2414 13:31:04.142213 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2415 13:31:04.145621 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2416 13:31:04.152436 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2417 13:31:04.155536 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2418 13:31:04.158733 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2419 13:31:04.165380 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2420 13:31:04.168899 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2421 13:31:04.171889 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2422 13:31:04.179315 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2423 13:31:04.179930 Total UI for P1: 0, mck2ui 16
2424 13:31:04.185824 best dqsien dly found for B0: ( 0, 15, 18)
2425 13:31:04.188397 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2426 13:31:04.191885 Total UI for P1: 0, mck2ui 16
2427 13:31:04.195767 best dqsien dly found for B1: ( 0, 15, 20)
2428 13:31:04.198879 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2429 13:31:04.201883 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2430 13:31:04.202231
2431 13:31:04.205643 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2432 13:31:04.209072 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2433 13:31:04.211857 [Gating] SW calibration Done
2434 13:31:04.212228 ==
2435 13:31:04.214927 Dram Type= 6, Freq= 0, CH_0, rank 0
2436 13:31:04.218376 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2437 13:31:04.218853 ==
2438 13:31:04.222518 RX Vref Scan: 0
2439 13:31:04.222986
2440 13:31:04.225376 RX Vref 0 -> 0, step: 1
2441 13:31:04.225731
2442 13:31:04.225983 RX Delay -40 -> 252, step: 8
2443 13:31:04.231675 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2444 13:31:04.235335 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2445 13:31:04.238416 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2446 13:31:04.241753 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2447 13:31:04.245502 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2448 13:31:04.252077 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2449 13:31:04.255181 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2450 13:31:04.259237 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2451 13:31:04.262182 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2452 13:31:04.265316 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2453 13:31:04.272029 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2454 13:31:04.276038 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2455 13:31:04.278845 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2456 13:31:04.281897 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2457 13:31:04.285522 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2458 13:31:04.292256 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2459 13:31:04.292782 ==
2460 13:31:04.295439 Dram Type= 6, Freq= 0, CH_0, rank 0
2461 13:31:04.299000 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2462 13:31:04.299565 ==
2463 13:31:04.299942 DQS Delay:
2464 13:31:04.302121 DQS0 = 0, DQS1 = 0
2465 13:31:04.302480 DQM Delay:
2466 13:31:04.305539 DQM0 = 115, DQM1 = 106
2467 13:31:04.305925 DQ Delay:
2468 13:31:04.308479 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2469 13:31:04.312176 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2470 13:31:04.315348 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2471 13:31:04.318704 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2472 13:31:04.319178
2473 13:31:04.319460
2474 13:31:04.319677 ==
2475 13:31:04.322361 Dram Type= 6, Freq= 0, CH_0, rank 0
2476 13:31:04.329020 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2477 13:31:04.329384 ==
2478 13:31:04.329634
2479 13:31:04.329857
2480 13:31:04.331629 TX Vref Scan disable
2481 13:31:04.331915 == TX Byte 0 ==
2482 13:31:04.335189 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2483 13:31:04.342244 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2484 13:31:04.342699 == TX Byte 1 ==
2485 13:31:04.345637 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2486 13:31:04.352038 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2487 13:31:04.352550 ==
2488 13:31:04.355728 Dram Type= 6, Freq= 0, CH_0, rank 0
2489 13:31:04.358675 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2490 13:31:04.359140 ==
2491 13:31:04.370625 TX Vref=22, minBit 10, minWin=24, winSum=412
2492 13:31:04.373988 TX Vref=24, minBit 9, minWin=25, winSum=421
2493 13:31:04.377225 TX Vref=26, minBit 9, minWin=25, winSum=426
2494 13:31:04.380839 TX Vref=28, minBit 13, minWin=25, winSum=431
2495 13:31:04.384115 TX Vref=30, minBit 8, minWin=26, winSum=433
2496 13:31:04.390285 TX Vref=32, minBit 8, minWin=26, winSum=438
2497 13:31:04.393666 [TxChooseVref] Worse bit 8, Min win 26, Win sum 438, Final Vref 32
2498 13:31:04.394136
2499 13:31:04.397009 Final TX Range 1 Vref 32
2500 13:31:04.397422
2501 13:31:04.397705 ==
2502 13:31:04.400615 Dram Type= 6, Freq= 0, CH_0, rank 0
2503 13:31:04.403666 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2504 13:31:04.404059 ==
2505 13:31:04.407013
2506 13:31:04.407390
2507 13:31:04.407665 TX Vref Scan disable
2508 13:31:04.410731 == TX Byte 0 ==
2509 13:31:04.414040 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2510 13:31:04.417093 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2511 13:31:04.420172 == TX Byte 1 ==
2512 13:31:04.423637 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2513 13:31:04.427107 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2514 13:31:04.430825
2515 13:31:04.431303 [DATLAT]
2516 13:31:04.431589 Freq=1200, CH0 RK0
2517 13:31:04.431832
2518 13:31:04.433709 DATLAT Default: 0xd
2519 13:31:04.434091 0, 0xFFFF, sum = 0
2520 13:31:04.436883 1, 0xFFFF, sum = 0
2521 13:31:04.437239 2, 0xFFFF, sum = 0
2522 13:31:04.440327 3, 0xFFFF, sum = 0
2523 13:31:04.440624 4, 0xFFFF, sum = 0
2524 13:31:04.444145 5, 0xFFFF, sum = 0
2525 13:31:04.444748 6, 0xFFFF, sum = 0
2526 13:31:04.447253 7, 0xFFFF, sum = 0
2527 13:31:04.450805 8, 0xFFFF, sum = 0
2528 13:31:04.451262 9, 0xFFFF, sum = 0
2529 13:31:04.454024 10, 0xFFFF, sum = 0
2530 13:31:04.454478 11, 0x0, sum = 1
2531 13:31:04.457376 12, 0x0, sum = 2
2532 13:31:04.457863 13, 0x0, sum = 3
2533 13:31:04.458156 14, 0x0, sum = 4
2534 13:31:04.460620 best_step = 12
2535 13:31:04.460968
2536 13:31:04.461216 ==
2537 13:31:04.464104 Dram Type= 6, Freq= 0, CH_0, rank 0
2538 13:31:04.467295 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2539 13:31:04.467750 ==
2540 13:31:04.470814 RX Vref Scan: 1
2541 13:31:04.471268
2542 13:31:04.473912 Set Vref Range= 32 -> 127
2543 13:31:04.474263
2544 13:31:04.474509 RX Vref 32 -> 127, step: 1
2545 13:31:04.474725
2546 13:31:04.477916 RX Delay -21 -> 252, step: 4
2547 13:31:04.478266
2548 13:31:04.480857 Set Vref, RX VrefLevel [Byte0]: 32
2549 13:31:04.484044 [Byte1]: 32
2550 13:31:04.486911
2551 13:31:04.487258 Set Vref, RX VrefLevel [Byte0]: 33
2552 13:31:04.490596 [Byte1]: 33
2553 13:31:04.495322
2554 13:31:04.495809 Set Vref, RX VrefLevel [Byte0]: 34
2555 13:31:04.498469 [Byte1]: 34
2556 13:31:04.503373
2557 13:31:04.503860 Set Vref, RX VrefLevel [Byte0]: 35
2558 13:31:04.506917 [Byte1]: 35
2559 13:31:04.511028
2560 13:31:04.511500 Set Vref, RX VrefLevel [Byte0]: 36
2561 13:31:04.513951 [Byte1]: 36
2562 13:31:04.518866
2563 13:31:04.519462 Set Vref, RX VrefLevel [Byte0]: 37
2564 13:31:04.522339 [Byte1]: 37
2565 13:31:04.527307
2566 13:31:04.527783 Set Vref, RX VrefLevel [Byte0]: 38
2567 13:31:04.530215 [Byte1]: 38
2568 13:31:04.535068
2569 13:31:04.535527 Set Vref, RX VrefLevel [Byte0]: 39
2570 13:31:04.537974 [Byte1]: 39
2571 13:31:04.542804
2572 13:31:04.543295 Set Vref, RX VrefLevel [Byte0]: 40
2573 13:31:04.546285 [Byte1]: 40
2574 13:31:04.550738
2575 13:31:04.551239 Set Vref, RX VrefLevel [Byte0]: 41
2576 13:31:04.553560 [Byte1]: 41
2577 13:31:04.558446
2578 13:31:04.558926 Set Vref, RX VrefLevel [Byte0]: 42
2579 13:31:04.562275 [Byte1]: 42
2580 13:31:04.566409
2581 13:31:04.566893 Set Vref, RX VrefLevel [Byte0]: 43
2582 13:31:04.569563 [Byte1]: 43
2583 13:31:04.574741
2584 13:31:04.575230 Set Vref, RX VrefLevel [Byte0]: 44
2585 13:31:04.577707 [Byte1]: 44
2586 13:31:04.582488
2587 13:31:04.582976 Set Vref, RX VrefLevel [Byte0]: 45
2588 13:31:04.585594 [Byte1]: 45
2589 13:31:04.590167
2590 13:31:04.590656 Set Vref, RX VrefLevel [Byte0]: 46
2591 13:31:04.593337 [Byte1]: 46
2592 13:31:04.598159
2593 13:31:04.598652 Set Vref, RX VrefLevel [Byte0]: 47
2594 13:31:04.601556 [Byte1]: 47
2595 13:31:04.605923
2596 13:31:04.606356 Set Vref, RX VrefLevel [Byte0]: 48
2597 13:31:04.609551 [Byte1]: 48
2598 13:31:04.613981
2599 13:31:04.614469 Set Vref, RX VrefLevel [Byte0]: 49
2600 13:31:04.617190 [Byte1]: 49
2601 13:31:04.622254
2602 13:31:04.622759 Set Vref, RX VrefLevel [Byte0]: 50
2603 13:31:04.626099 [Byte1]: 50
2604 13:31:04.629742
2605 13:31:04.630129 Set Vref, RX VrefLevel [Byte0]: 51
2606 13:31:04.632824 [Byte1]: 51
2607 13:31:04.637597
2608 13:31:04.637988 Set Vref, RX VrefLevel [Byte0]: 52
2609 13:31:04.641010 [Byte1]: 52
2610 13:31:04.645811
2611 13:31:04.646253 Set Vref, RX VrefLevel [Byte0]: 53
2612 13:31:04.648783 [Byte1]: 53
2613 13:31:04.653392
2614 13:31:04.653854 Set Vref, RX VrefLevel [Byte0]: 54
2615 13:31:04.656476 [Byte1]: 54
2616 13:31:04.661863
2617 13:31:04.662322 Set Vref, RX VrefLevel [Byte0]: 55
2618 13:31:04.664614 [Byte1]: 55
2619 13:31:04.669041
2620 13:31:04.669503 Set Vref, RX VrefLevel [Byte0]: 56
2621 13:31:04.672874 [Byte1]: 56
2622 13:31:04.677250
2623 13:31:04.677733 Set Vref, RX VrefLevel [Byte0]: 57
2624 13:31:04.680694 [Byte1]: 57
2625 13:31:04.685445
2626 13:31:04.685930 Set Vref, RX VrefLevel [Byte0]: 58
2627 13:31:04.688769 [Byte1]: 58
2628 13:31:04.693196
2629 13:31:04.693581 Set Vref, RX VrefLevel [Byte0]: 59
2630 13:31:04.695954 [Byte1]: 59
2631 13:31:04.700837
2632 13:31:04.701301 Set Vref, RX VrefLevel [Byte0]: 60
2633 13:31:04.704336 [Byte1]: 60
2634 13:31:04.709191
2635 13:31:04.709631 Set Vref, RX VrefLevel [Byte0]: 61
2636 13:31:04.712392 [Byte1]: 61
2637 13:31:04.716674
2638 13:31:04.717278 Set Vref, RX VrefLevel [Byte0]: 62
2639 13:31:04.719767 [Byte1]: 62
2640 13:31:04.724671
2641 13:31:04.725047 Set Vref, RX VrefLevel [Byte0]: 63
2642 13:31:04.728047 [Byte1]: 63
2643 13:31:04.732575
2644 13:31:04.732851 Set Vref, RX VrefLevel [Byte0]: 64
2645 13:31:04.736357 [Byte1]: 64
2646 13:31:04.740369
2647 13:31:04.740813 Set Vref, RX VrefLevel [Byte0]: 65
2648 13:31:04.743797 [Byte1]: 65
2649 13:31:04.748872
2650 13:31:04.749379 Set Vref, RX VrefLevel [Byte0]: 66
2651 13:31:04.751994 [Byte1]: 66
2652 13:31:04.756701
2653 13:31:04.757130 Final RX Vref Byte 0 = 47 to rank0
2654 13:31:04.759660 Final RX Vref Byte 1 = 49 to rank0
2655 13:31:04.763047 Final RX Vref Byte 0 = 47 to rank1
2656 13:31:04.766465 Final RX Vref Byte 1 = 49 to rank1==
2657 13:31:04.769977 Dram Type= 6, Freq= 0, CH_0, rank 0
2658 13:31:04.776962 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2659 13:31:04.777406 ==
2660 13:31:04.777655 DQS Delay:
2661 13:31:04.777871 DQS0 = 0, DQS1 = 0
2662 13:31:04.779777 DQM Delay:
2663 13:31:04.780119 DQM0 = 113, DQM1 = 105
2664 13:31:04.783401 DQ Delay:
2665 13:31:04.786242 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =108
2666 13:31:04.789809 DQ4 =118, DQ5 =104, DQ6 =124, DQ7 =120
2667 13:31:04.793457 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2668 13:31:04.796581 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2669 13:31:04.796958
2670 13:31:04.797211
2671 13:31:04.803528 [DQSOSCAuto] RK0, (LSB)MR18= 0x909, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
2672 13:31:04.806581 CH0 RK0: MR19=404, MR18=909
2673 13:31:04.813189 CH0_RK0: MR19=0x404, MR18=0x909, DQSOSC=406, MR23=63, INC=39, DEC=26
2674 13:31:04.813594
2675 13:31:04.816566 ----->DramcWriteLeveling(PI) begin...
2676 13:31:04.816913 ==
2677 13:31:04.819822 Dram Type= 6, Freq= 0, CH_0, rank 1
2678 13:31:04.823181 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2679 13:31:04.823593 ==
2680 13:31:04.826708 Write leveling (Byte 0): 28 => 28
2681 13:31:04.830073 Write leveling (Byte 1): 25 => 25
2682 13:31:04.832947 DramcWriteLeveling(PI) end<-----
2683 13:31:04.833293
2684 13:31:04.833540 ==
2685 13:31:04.836551 Dram Type= 6, Freq= 0, CH_0, rank 1
2686 13:31:04.840039 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2687 13:31:04.843157 ==
2688 13:31:04.843497 [Gating] SW mode calibration
2689 13:31:04.849993 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2690 13:31:04.856672 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2691 13:31:04.860339 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2692 13:31:04.866387 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2693 13:31:04.869912 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2694 13:31:04.873113 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2695 13:31:04.880252 0 11 16 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
2696 13:31:04.883374 0 11 20 | B1->B0 | 2e2e 2424 | 0 0 | (0 1) (0 0)
2697 13:31:04.886810 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2698 13:31:04.893181 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2699 13:31:04.896637 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2700 13:31:04.899419 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2701 13:31:04.906244 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2702 13:31:04.910165 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2703 13:31:04.913066 0 12 16 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2704 13:31:04.919820 0 12 20 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
2705 13:31:04.923035 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2706 13:31:04.926492 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2707 13:31:04.929689 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2708 13:31:04.935908 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2709 13:31:04.939817 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2710 13:31:04.943575 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2711 13:31:04.949757 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2712 13:31:04.953079 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2713 13:31:04.956376 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2714 13:31:04.962767 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2715 13:31:04.966269 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2716 13:31:04.969466 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2717 13:31:04.976037 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2718 13:31:04.979500 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2719 13:31:04.982727 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2720 13:31:04.989692 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2721 13:31:04.992948 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2722 13:31:04.995972 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2723 13:31:05.003062 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2724 13:31:05.006671 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2725 13:31:05.010052 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2726 13:31:05.016302 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2727 13:31:05.019236 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2728 13:31:05.022959 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2729 13:31:05.025995 Total UI for P1: 0, mck2ui 16
2730 13:31:05.029195 best dqsien dly found for B0: ( 0, 15, 16)
2731 13:31:05.032898 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2732 13:31:05.035892 Total UI for P1: 0, mck2ui 16
2733 13:31:05.039678 best dqsien dly found for B1: ( 0, 15, 18)
2734 13:31:05.043504 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2735 13:31:05.049801 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2736 13:31:05.050290
2737 13:31:05.053679 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2738 13:31:05.056361 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2739 13:31:05.059386 [Gating] SW calibration Done
2740 13:31:05.059780 ==
2741 13:31:05.063069 Dram Type= 6, Freq= 0, CH_0, rank 1
2742 13:31:05.066773 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2743 13:31:05.067262 ==
2744 13:31:05.067542 RX Vref Scan: 0
2745 13:31:05.069949
2746 13:31:05.070434 RX Vref 0 -> 0, step: 1
2747 13:31:05.070713
2748 13:31:05.073039 RX Delay -40 -> 252, step: 8
2749 13:31:05.076053 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2750 13:31:05.079570 iDelay=200, Bit 1, Center 119 (40 ~ 199) 160
2751 13:31:05.086449 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2752 13:31:05.089886 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2753 13:31:05.093075 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2754 13:31:05.096184 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2755 13:31:05.100046 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2756 13:31:05.106528 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2757 13:31:05.109529 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2758 13:31:05.112535 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2759 13:31:05.116099 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2760 13:31:05.119431 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2761 13:31:05.126386 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2762 13:31:05.129550 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2763 13:31:05.132888 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2764 13:31:05.136560 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2765 13:31:05.136912 ==
2766 13:31:05.139342 Dram Type= 6, Freq= 0, CH_0, rank 1
2767 13:31:05.143151 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2768 13:31:05.146380 ==
2769 13:31:05.146859 DQS Delay:
2770 13:31:05.147138 DQS0 = 0, DQS1 = 0
2771 13:31:05.149774 DQM Delay:
2772 13:31:05.150248 DQM0 = 115, DQM1 = 107
2773 13:31:05.153430 DQ Delay:
2774 13:31:05.156143 DQ0 =107, DQ1 =119, DQ2 =115, DQ3 =111
2775 13:31:05.159272 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2776 13:31:05.162575 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2777 13:31:05.166544 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =115
2778 13:31:05.166980
2779 13:31:05.167226
2780 13:31:05.167441 ==
2781 13:31:05.169446 Dram Type= 6, Freq= 0, CH_0, rank 1
2782 13:31:05.172828 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2783 13:31:05.173249 ==
2784 13:31:05.173501
2785 13:31:05.173715
2786 13:31:05.176580 TX Vref Scan disable
2787 13:31:05.179888 == TX Byte 0 ==
2788 13:31:05.183013 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2789 13:31:05.186347 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2790 13:31:05.189789 == TX Byte 1 ==
2791 13:31:05.192996 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2792 13:31:05.196040 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2793 13:31:05.196409 ==
2794 13:31:05.199652 Dram Type= 6, Freq= 0, CH_0, rank 1
2795 13:31:05.202456 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2796 13:31:05.206024 ==
2797 13:31:05.216358 TX Vref=22, minBit 8, minWin=25, winSum=420
2798 13:31:05.219734 TX Vref=24, minBit 8, minWin=25, winSum=421
2799 13:31:05.222866 TX Vref=26, minBit 8, minWin=26, winSum=429
2800 13:31:05.226338 TX Vref=28, minBit 9, minWin=26, winSum=433
2801 13:31:05.229821 TX Vref=30, minBit 8, minWin=26, winSum=437
2802 13:31:05.232780 TX Vref=32, minBit 9, minWin=26, winSum=436
2803 13:31:05.239708 [TxChooseVref] Worse bit 8, Min win 26, Win sum 437, Final Vref 30
2804 13:31:05.240056
2805 13:31:05.243339 Final TX Range 1 Vref 30
2806 13:31:05.243758
2807 13:31:05.244006 ==
2808 13:31:05.246594 Dram Type= 6, Freq= 0, CH_0, rank 1
2809 13:31:05.249912 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2810 13:31:05.250260 ==
2811 13:31:05.250501
2812 13:31:05.253206
2813 13:31:05.253549 TX Vref Scan disable
2814 13:31:05.256715 == TX Byte 0 ==
2815 13:31:05.259635 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2816 13:31:05.263222 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2817 13:31:05.266820 == TX Byte 1 ==
2818 13:31:05.269917 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2819 13:31:05.273486 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2820 13:31:05.274038
2821 13:31:05.276376 [DATLAT]
2822 13:31:05.276727 Freq=1200, CH0 RK1
2823 13:31:05.276979
2824 13:31:05.280484 DATLAT Default: 0xc
2825 13:31:05.280943 0, 0xFFFF, sum = 0
2826 13:31:05.283503 1, 0xFFFF, sum = 0
2827 13:31:05.283970 2, 0xFFFF, sum = 0
2828 13:31:05.286684 3, 0xFFFF, sum = 0
2829 13:31:05.287172 4, 0xFFFF, sum = 0
2830 13:31:05.290095 5, 0xFFFF, sum = 0
2831 13:31:05.290561 6, 0xFFFF, sum = 0
2832 13:31:05.293241 7, 0xFFFF, sum = 0
2833 13:31:05.293631 8, 0xFFFF, sum = 0
2834 13:31:05.296825 9, 0xFFFF, sum = 0
2835 13:31:05.300161 10, 0xFFFF, sum = 0
2836 13:31:05.300729 11, 0x0, sum = 1
2837 13:31:05.301026 12, 0x0, sum = 2
2838 13:31:05.303554 13, 0x0, sum = 3
2839 13:31:05.304053 14, 0x0, sum = 4
2840 13:31:05.306907 best_step = 12
2841 13:31:05.307427
2842 13:31:05.307712 ==
2843 13:31:05.310135 Dram Type= 6, Freq= 0, CH_0, rank 1
2844 13:31:05.313043 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2845 13:31:05.313434 ==
2846 13:31:05.316583 RX Vref Scan: 0
2847 13:31:05.317141
2848 13:31:05.317430 RX Vref 0 -> 0, step: 1
2849 13:31:05.317673
2850 13:31:05.320201 RX Delay -21 -> 252, step: 4
2851 13:31:05.326989 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2852 13:31:05.329784 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2853 13:31:05.333710 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2854 13:31:05.336104 iDelay=199, Bit 3, Center 108 (39 ~ 178) 140
2855 13:31:05.339733 iDelay=199, Bit 4, Center 118 (47 ~ 190) 144
2856 13:31:05.346355 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2857 13:31:05.349905 iDelay=199, Bit 6, Center 124 (55 ~ 194) 140
2858 13:31:05.353739 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2859 13:31:05.356852 iDelay=199, Bit 8, Center 94 (31 ~ 158) 128
2860 13:31:05.359886 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2861 13:31:05.366824 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
2862 13:31:05.369818 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2863 13:31:05.373307 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
2864 13:31:05.376542 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2865 13:31:05.380242 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
2866 13:31:05.386715 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2867 13:31:05.387165 ==
2868 13:31:05.389705 Dram Type= 6, Freq= 0, CH_0, rank 1
2869 13:31:05.393614 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2870 13:31:05.393964 ==
2871 13:31:05.394226 DQS Delay:
2872 13:31:05.397059 DQS0 = 0, DQS1 = 0
2873 13:31:05.397522 DQM Delay:
2874 13:31:05.399865 DQM0 = 115, DQM1 = 105
2875 13:31:05.400211 DQ Delay:
2876 13:31:05.403382 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2877 13:31:05.406757 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =124
2878 13:31:05.410103 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =96
2879 13:31:05.413803 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
2880 13:31:05.414280
2881 13:31:05.414555
2882 13:31:05.423207 [DQSOSCAuto] RK1, (LSB)MR18= 0xc0c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
2883 13:31:05.426677 CH0 RK1: MR19=404, MR18=C0C
2884 13:31:05.429755 CH0_RK1: MR19=0x404, MR18=0xC0C, DQSOSC=405, MR23=63, INC=39, DEC=26
2885 13:31:05.432992 [RxdqsGatingPostProcess] freq 1200
2886 13:31:05.439915 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2887 13:31:05.443417 Pre-setting of DQS Precalculation
2888 13:31:05.446611 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2889 13:31:05.446914 ==
2890 13:31:05.449993 Dram Type= 6, Freq= 0, CH_1, rank 0
2891 13:31:05.456645 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2892 13:31:05.457094 ==
2893 13:31:05.460337 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2894 13:31:05.466719 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2895 13:31:05.475814 [CA 0] Center 37 (7~68) winsize 62
2896 13:31:05.478915 [CA 1] Center 37 (7~68) winsize 62
2897 13:31:05.481848 [CA 2] Center 34 (4~65) winsize 62
2898 13:31:05.485105 [CA 3] Center 33 (3~64) winsize 62
2899 13:31:05.488341 [CA 4] Center 32 (2~63) winsize 62
2900 13:31:05.491710 [CA 5] Center 32 (2~63) winsize 62
2901 13:31:05.492189
2902 13:31:05.494881 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2903 13:31:05.495383
2904 13:31:05.498726 [CATrainingPosCal] consider 1 rank data
2905 13:31:05.501773 u2DelayCellTimex100 = 270/100 ps
2906 13:31:05.505321 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2907 13:31:05.511894 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2908 13:31:05.515163 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2909 13:31:05.518097 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2910 13:31:05.521342 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2911 13:31:05.524681 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2912 13:31:05.525037
2913 13:31:05.528239 CA PerBit enable=1, Macro0, CA PI delay=32
2914 13:31:05.528559
2915 13:31:05.531733 [CBTSetCACLKResult] CA Dly = 32
2916 13:31:05.532193 CS Dly: 6 (0~37)
2917 13:31:05.534517 ==
2918 13:31:05.538118 Dram Type= 6, Freq= 0, CH_1, rank 1
2919 13:31:05.541505 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2920 13:31:05.541865 ==
2921 13:31:05.544389 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2922 13:31:05.551798 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2923 13:31:05.560637 [CA 0] Center 37 (7~68) winsize 62
2924 13:31:05.563611 [CA 1] Center 37 (6~68) winsize 63
2925 13:31:05.567241 [CA 2] Center 34 (3~65) winsize 63
2926 13:31:05.570500 [CA 3] Center 33 (3~64) winsize 62
2927 13:31:05.573726 [CA 4] Center 32 (2~63) winsize 62
2928 13:31:05.577678 [CA 5] Center 32 (2~63) winsize 62
2929 13:31:05.578189
2930 13:31:05.580591 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2931 13:31:05.580975
2932 13:31:05.583895 [CATrainingPosCal] consider 2 rank data
2933 13:31:05.587225 u2DelayCellTimex100 = 270/100 ps
2934 13:31:05.590326 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2935 13:31:05.593717 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2936 13:31:05.600398 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2937 13:31:05.603704 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2938 13:31:05.606858 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2939 13:31:05.610561 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2940 13:31:05.611013
2941 13:31:05.613772 CA PerBit enable=1, Macro0, CA PI delay=32
2942 13:31:05.614157
2943 13:31:05.616813 [CBTSetCACLKResult] CA Dly = 32
2944 13:31:05.617267 CS Dly: 6 (0~38)
2945 13:31:05.617542
2946 13:31:05.620006 ----->DramcWriteLeveling(PI) begin...
2947 13:31:05.623717 ==
2948 13:31:05.626919 Dram Type= 6, Freq= 0, CH_1, rank 0
2949 13:31:05.630259 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2950 13:31:05.630613 ==
2951 13:31:05.633501 Write leveling (Byte 0): 20 => 20
2952 13:31:05.636552 Write leveling (Byte 1): 23 => 23
2953 13:31:05.640183 DramcWriteLeveling(PI) end<-----
2954 13:31:05.640650
2955 13:31:05.640966 ==
2956 13:31:05.643564 Dram Type= 6, Freq= 0, CH_1, rank 0
2957 13:31:05.647141 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2958 13:31:05.647607 ==
2959 13:31:05.650299 [Gating] SW mode calibration
2960 13:31:05.656733 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2961 13:31:05.663541 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2962 13:31:05.666531 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2963 13:31:05.670420 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2964 13:31:05.673542 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2965 13:31:05.680339 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
2966 13:31:05.683208 0 11 16 | B1->B0 | 3131 2a2a | 1 0 | (1 1) (0 0)
2967 13:31:05.686447 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2968 13:31:05.693267 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2969 13:31:05.697038 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2970 13:31:05.700051 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2971 13:31:05.706513 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2972 13:31:05.710141 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2973 13:31:05.713230 0 12 12 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
2974 13:31:05.719958 0 12 16 | B1->B0 | 2c2c 3d3d | 0 0 | (1 1) (0 0)
2975 13:31:05.723159 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2976 13:31:05.726964 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2977 13:31:05.733490 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2978 13:31:05.736745 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2979 13:31:05.739788 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2980 13:31:05.746842 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2981 13:31:05.750183 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2982 13:31:05.753206 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2983 13:31:05.760376 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2984 13:31:05.763205 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 13:31:05.766948 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 13:31:05.773165 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 13:31:05.776467 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 13:31:05.780039 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2989 13:31:05.783800 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2990 13:31:05.790417 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2991 13:31:05.793166 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2992 13:31:05.797024 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2993 13:31:05.803708 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2994 13:31:05.806930 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2995 13:31:05.810021 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2996 13:31:05.817091 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2997 13:31:05.820077 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2998 13:31:05.823122 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2999 13:31:05.829841 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3000 13:31:05.833507 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3001 13:31:05.836344 Total UI for P1: 0, mck2ui 16
3002 13:31:05.839845 best dqsien dly found for B0: ( 0, 15, 16)
3003 13:31:05.843150 Total UI for P1: 0, mck2ui 16
3004 13:31:05.847158 best dqsien dly found for B1: ( 0, 15, 18)
3005 13:31:05.850079 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3006 13:31:05.853258 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3007 13:31:05.853637
3008 13:31:05.856710 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3009 13:31:05.860121 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3010 13:31:05.864009 [Gating] SW calibration Done
3011 13:31:05.864573 ==
3012 13:31:05.867121 Dram Type= 6, Freq= 0, CH_1, rank 0
3013 13:31:05.870247 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3014 13:31:05.870646 ==
3015 13:31:05.873738 RX Vref Scan: 0
3016 13:31:05.874226
3017 13:31:05.876944 RX Vref 0 -> 0, step: 1
3018 13:31:05.877320
3019 13:31:05.877581 RX Delay -40 -> 252, step: 8
3020 13:31:05.883467 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3021 13:31:05.887248 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3022 13:31:05.890561 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3023 13:31:05.893803 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3024 13:31:05.896710 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3025 13:31:05.903353 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3026 13:31:05.906918 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3027 13:31:05.910118 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3028 13:31:05.913504 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3029 13:31:05.917209 iDelay=208, Bit 9, Center 103 (32 ~ 175) 144
3030 13:31:05.923482 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3031 13:31:05.926608 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3032 13:31:05.930056 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3033 13:31:05.933599 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3034 13:31:05.937268 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3035 13:31:05.943407 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3036 13:31:05.943861 ==
3037 13:31:05.946749 Dram Type= 6, Freq= 0, CH_1, rank 0
3038 13:31:05.950945 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3039 13:31:05.951409 ==
3040 13:31:05.951703 DQS Delay:
3041 13:31:05.953653 DQS0 = 0, DQS1 = 0
3042 13:31:05.953998 DQM Delay:
3043 13:31:05.957199 DQM0 = 116, DQM1 = 109
3044 13:31:05.957620 DQ Delay:
3045 13:31:05.959990 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3046 13:31:05.963603 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3047 13:31:05.967124 DQ8 =87, DQ9 =103, DQ10 =111, DQ11 =95
3048 13:31:05.970104 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3049 13:31:05.970448
3050 13:31:05.970690
3051 13:31:05.970908 ==
3052 13:31:05.973723 Dram Type= 6, Freq= 0, CH_1, rank 0
3053 13:31:05.980409 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3054 13:31:05.980873 ==
3055 13:31:05.981133
3056 13:31:05.981349
3057 13:31:05.981554 TX Vref Scan disable
3058 13:31:05.984299 == TX Byte 0 ==
3059 13:31:05.987530 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3060 13:31:05.994258 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3061 13:31:05.994672 == TX Byte 1 ==
3062 13:31:05.997201 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3063 13:31:06.000391 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3064 13:31:06.003982 ==
3065 13:31:06.007221 Dram Type= 6, Freq= 0, CH_1, rank 0
3066 13:31:06.010996 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3067 13:31:06.011472 ==
3068 13:31:06.021621 TX Vref=22, minBit 3, minWin=24, winSum=407
3069 13:31:06.025248 TX Vref=24, minBit 9, minWin=25, winSum=416
3070 13:31:06.028137 TX Vref=26, minBit 1, minWin=25, winSum=421
3071 13:31:06.031967 TX Vref=28, minBit 0, minWin=26, winSum=426
3072 13:31:06.034899 TX Vref=30, minBit 1, minWin=26, winSum=426
3073 13:31:06.039132 TX Vref=32, minBit 9, minWin=25, winSum=426
3074 13:31:06.045306 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 28
3075 13:31:06.045670
3076 13:31:06.048554 Final TX Range 1 Vref 28
3077 13:31:06.048900
3078 13:31:06.049140 ==
3079 13:31:06.051841 Dram Type= 6, Freq= 0, CH_1, rank 0
3080 13:31:06.055085 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3081 13:31:06.055536 ==
3082 13:31:06.055806
3083 13:31:06.056020
3084 13:31:06.058760 TX Vref Scan disable
3085 13:31:06.061962 == TX Byte 0 ==
3086 13:31:06.065459 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3087 13:31:06.068531 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3088 13:31:06.071678 == TX Byte 1 ==
3089 13:31:06.075276 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3090 13:31:06.078545 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3091 13:31:06.078894
3092 13:31:06.081908 [DATLAT]
3093 13:31:06.082359 Freq=1200, CH1 RK0
3094 13:31:06.082618
3095 13:31:06.085657 DATLAT Default: 0xd
3096 13:31:06.086123 0, 0xFFFF, sum = 0
3097 13:31:06.088933 1, 0xFFFF, sum = 0
3098 13:31:06.089455 2, 0xFFFF, sum = 0
3099 13:31:06.091462 3, 0xFFFF, sum = 0
3100 13:31:06.091813 4, 0xFFFF, sum = 0
3101 13:31:06.095225 5, 0xFFFF, sum = 0
3102 13:31:06.095615 6, 0xFFFF, sum = 0
3103 13:31:06.098676 7, 0xFFFF, sum = 0
3104 13:31:06.099168 8, 0xFFFF, sum = 0
3105 13:31:06.101842 9, 0xFFFF, sum = 0
3106 13:31:06.105187 10, 0xFFFF, sum = 0
3107 13:31:06.105539 11, 0x0, sum = 1
3108 13:31:06.105787 12, 0x0, sum = 2
3109 13:31:06.108332 13, 0x0, sum = 3
3110 13:31:06.108709 14, 0x0, sum = 4
3111 13:31:06.111867 best_step = 12
3112 13:31:06.112213
3113 13:31:06.112494 ==
3114 13:31:06.115392 Dram Type= 6, Freq= 0, CH_1, rank 0
3115 13:31:06.118605 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3116 13:31:06.118953 ==
3117 13:31:06.121583 RX Vref Scan: 1
3118 13:31:06.121929
3119 13:31:06.122177 Set Vref Range= 32 -> 127
3120 13:31:06.122396
3121 13:31:06.125489 RX Vref 32 -> 127, step: 1
3122 13:31:06.125658
3123 13:31:06.128051 RX Delay -29 -> 252, step: 4
3124 13:31:06.128158
3125 13:31:06.131623 Set Vref, RX VrefLevel [Byte0]: 32
3126 13:31:06.134944 [Byte1]: 32
3127 13:31:06.135292
3128 13:31:06.138557 Set Vref, RX VrefLevel [Byte0]: 33
3129 13:31:06.142339 [Byte1]: 33
3130 13:31:06.145972
3131 13:31:06.146317 Set Vref, RX VrefLevel [Byte0]: 34
3132 13:31:06.149632 [Byte1]: 34
3133 13:31:06.154277
3134 13:31:06.154745 Set Vref, RX VrefLevel [Byte0]: 35
3135 13:31:06.157919 [Byte1]: 35
3136 13:31:06.162241
3137 13:31:06.162637 Set Vref, RX VrefLevel [Byte0]: 36
3138 13:31:06.165935 [Byte1]: 36
3139 13:31:06.170187
3140 13:31:06.170691 Set Vref, RX VrefLevel [Byte0]: 37
3141 13:31:06.173722 [Byte1]: 37
3142 13:31:06.177807
3143 13:31:06.178271 Set Vref, RX VrefLevel [Byte0]: 38
3144 13:31:06.181451 [Byte1]: 38
3145 13:31:06.186189
3146 13:31:06.186675 Set Vref, RX VrefLevel [Byte0]: 39
3147 13:31:06.189457 [Byte1]: 39
3148 13:31:06.194417
3149 13:31:06.194913 Set Vref, RX VrefLevel [Byte0]: 40
3150 13:31:06.197341 [Byte1]: 40
3151 13:31:06.201908
3152 13:31:06.202300 Set Vref, RX VrefLevel [Byte0]: 41
3153 13:31:06.205036 [Byte1]: 41
3154 13:31:06.209814
3155 13:31:06.210254 Set Vref, RX VrefLevel [Byte0]: 42
3156 13:31:06.213414 [Byte1]: 42
3157 13:31:06.218164
3158 13:31:06.218683 Set Vref, RX VrefLevel [Byte0]: 43
3159 13:31:06.221417 [Byte1]: 43
3160 13:31:06.225894
3161 13:31:06.226269 Set Vref, RX VrefLevel [Byte0]: 44
3162 13:31:06.228914 [Byte1]: 44
3163 13:31:06.233654
3164 13:31:06.234123 Set Vref, RX VrefLevel [Byte0]: 45
3165 13:31:06.237107 [Byte1]: 45
3166 13:31:06.241865
3167 13:31:06.242212 Set Vref, RX VrefLevel [Byte0]: 46
3168 13:31:06.244792 [Byte1]: 46
3169 13:31:06.249631
3170 13:31:06.250042 Set Vref, RX VrefLevel [Byte0]: 47
3171 13:31:06.252909 [Byte1]: 47
3172 13:31:06.257438
3173 13:31:06.257783 Set Vref, RX VrefLevel [Byte0]: 48
3174 13:31:06.261045 [Byte1]: 48
3175 13:31:06.266130
3176 13:31:06.266596 Set Vref, RX VrefLevel [Byte0]: 49
3177 13:31:06.269172 [Byte1]: 49
3178 13:31:06.273631
3179 13:31:06.274038 Set Vref, RX VrefLevel [Byte0]: 50
3180 13:31:06.277058 [Byte1]: 50
3181 13:31:06.281673
3182 13:31:06.282041 Set Vref, RX VrefLevel [Byte0]: 51
3183 13:31:06.284971 [Byte1]: 51
3184 13:31:06.289824
3185 13:31:06.290279 Set Vref, RX VrefLevel [Byte0]: 52
3186 13:31:06.292763 [Byte1]: 52
3187 13:31:06.297539
3188 13:31:06.298017 Set Vref, RX VrefLevel [Byte0]: 53
3189 13:31:06.300649 [Byte1]: 53
3190 13:31:06.305477
3191 13:31:06.305825 Set Vref, RX VrefLevel [Byte0]: 54
3192 13:31:06.308564 [Byte1]: 54
3193 13:31:06.313562
3194 13:31:06.313969 Set Vref, RX VrefLevel [Byte0]: 55
3195 13:31:06.316552 [Byte1]: 55
3196 13:31:06.321374
3197 13:31:06.321851 Set Vref, RX VrefLevel [Byte0]: 56
3198 13:31:06.324878 [Byte1]: 56
3199 13:31:06.329082
3200 13:31:06.329508 Set Vref, RX VrefLevel [Byte0]: 57
3201 13:31:06.332181 [Byte1]: 57
3202 13:31:06.337141
3203 13:31:06.337489 Set Vref, RX VrefLevel [Byte0]: 58
3204 13:31:06.340470 [Byte1]: 58
3205 13:31:06.345451
3206 13:31:06.345809 Set Vref, RX VrefLevel [Byte0]: 59
3207 13:31:06.348143 [Byte1]: 59
3208 13:31:06.353061
3209 13:31:06.353476 Set Vref, RX VrefLevel [Byte0]: 60
3210 13:31:06.356949 [Byte1]: 60
3211 13:31:06.361413
3212 13:31:06.361824 Set Vref, RX VrefLevel [Byte0]: 61
3213 13:31:06.364306 [Byte1]: 61
3214 13:31:06.369470
3215 13:31:06.369941 Set Vref, RX VrefLevel [Byte0]: 62
3216 13:31:06.372465 [Byte1]: 62
3217 13:31:06.376904
3218 13:31:06.377344 Set Vref, RX VrefLevel [Byte0]: 63
3219 13:31:06.380233 [Byte1]: 63
3220 13:31:06.385003
3221 13:31:06.385447 Set Vref, RX VrefLevel [Byte0]: 64
3222 13:31:06.388435 [Byte1]: 64
3223 13:31:06.393106
3224 13:31:06.393521 Final RX Vref Byte 0 = 53 to rank0
3225 13:31:06.396463 Final RX Vref Byte 1 = 49 to rank0
3226 13:31:06.399335 Final RX Vref Byte 0 = 53 to rank1
3227 13:31:06.403007 Final RX Vref Byte 1 = 49 to rank1==
3228 13:31:06.406130 Dram Type= 6, Freq= 0, CH_1, rank 0
3229 13:31:06.412963 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3230 13:31:06.413415 ==
3231 13:31:06.413783 DQS Delay:
3232 13:31:06.415883 DQS0 = 0, DQS1 = 0
3233 13:31:06.416454 DQM Delay:
3234 13:31:06.416754 DQM0 = 115, DQM1 = 105
3235 13:31:06.419499 DQ Delay:
3236 13:31:06.422332 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3237 13:31:06.425871 DQ4 =114, DQ5 =126, DQ6 =122, DQ7 =112
3238 13:31:06.429085 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =98
3239 13:31:06.432728 DQ12 =112, DQ13 =116, DQ14 =114, DQ15 =112
3240 13:31:06.433074
3241 13:31:06.433318
3242 13:31:06.439877 [DQSOSCAuto] RK0, (LSB)MR18= 0x1717, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
3243 13:31:06.442655 CH1 RK0: MR19=404, MR18=1717
3244 13:31:06.449675 CH1_RK0: MR19=0x404, MR18=0x1717, DQSOSC=401, MR23=63, INC=40, DEC=27
3245 13:31:06.450129
3246 13:31:06.452334 ----->DramcWriteLeveling(PI) begin...
3247 13:31:06.452701 ==
3248 13:31:06.456036 Dram Type= 6, Freq= 0, CH_1, rank 1
3249 13:31:06.459253 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3250 13:31:06.463005 ==
3251 13:31:06.463470 Write leveling (Byte 0): 21 => 21
3252 13:31:06.466014 Write leveling (Byte 1): 22 => 22
3253 13:31:06.469104 DramcWriteLeveling(PI) end<-----
3254 13:31:06.469448
3255 13:31:06.469692 ==
3256 13:31:06.472477 Dram Type= 6, Freq= 0, CH_1, rank 1
3257 13:31:06.478757 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3258 13:31:06.479152 ==
3259 13:31:06.482209 [Gating] SW mode calibration
3260 13:31:06.488996 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3261 13:31:06.492596 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3262 13:31:06.499527 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3263 13:31:06.502319 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3264 13:31:06.505751 0 11 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3265 13:31:06.512603 0 11 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
3266 13:31:06.516059 0 11 16 | B1->B0 | 3232 2323 | 0 0 | (0 1) (1 0)
3267 13:31:06.519635 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3268 13:31:06.523138 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3269 13:31:06.528902 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3270 13:31:06.532074 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3271 13:31:06.535741 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3272 13:31:06.542772 0 12 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3273 13:31:06.545728 0 12 12 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
3274 13:31:06.549456 0 12 16 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
3275 13:31:06.555524 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3276 13:31:06.559159 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3277 13:31:06.562960 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3278 13:31:06.569126 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3279 13:31:06.572436 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3280 13:31:06.576038 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3281 13:31:06.582529 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3282 13:31:06.585834 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3283 13:31:06.589138 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3284 13:31:06.595397 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3285 13:31:06.599184 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3286 13:31:06.602299 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3287 13:31:06.609457 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3288 13:31:06.612399 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3289 13:31:06.615687 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3290 13:31:06.619097 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3291 13:31:06.625658 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3292 13:31:06.628879 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3293 13:31:06.631987 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3294 13:31:06.639153 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3295 13:31:06.642412 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3296 13:31:06.645683 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3297 13:31:06.652694 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3298 13:31:06.655719 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3299 13:31:06.658677 Total UI for P1: 0, mck2ui 16
3300 13:31:06.661992 best dqsien dly found for B0: ( 0, 15, 10)
3301 13:31:06.665271 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3302 13:31:06.668969 Total UI for P1: 0, mck2ui 16
3303 13:31:06.671974 best dqsien dly found for B1: ( 0, 15, 14)
3304 13:31:06.675705 best DQS0 dly(MCK, UI, PI) = (0, 15, 10)
3305 13:31:06.678951 best DQS1 dly(MCK, UI, PI) = (0, 15, 14)
3306 13:31:06.679414
3307 13:31:06.685652 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 10)
3308 13:31:06.689372 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 14)
3309 13:31:06.689728 [Gating] SW calibration Done
3310 13:31:06.692064 ==
3311 13:31:06.695326 Dram Type= 6, Freq= 0, CH_1, rank 1
3312 13:31:06.698828 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3313 13:31:06.699257 ==
3314 13:31:06.699504 RX Vref Scan: 0
3315 13:31:06.699590
3316 13:31:06.702218 RX Vref 0 -> 0, step: 1
3317 13:31:06.702291
3318 13:31:06.705247 RX Delay -40 -> 252, step: 8
3319 13:31:06.709249 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3320 13:31:06.712502 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3321 13:31:06.715988 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3322 13:31:06.722508 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3323 13:31:06.725875 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3324 13:31:06.728971 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3325 13:31:06.732313 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3326 13:31:06.735782 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3327 13:31:06.742202 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3328 13:31:06.746227 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3329 13:31:06.748969 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3330 13:31:06.752091 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3331 13:31:06.756149 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3332 13:31:06.762321 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3333 13:31:06.766388 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3334 13:31:06.769432 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3335 13:31:06.769942 ==
3336 13:31:06.772765 Dram Type= 6, Freq= 0, CH_1, rank 1
3337 13:31:06.776040 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3338 13:31:06.776451 ==
3339 13:31:06.779105 DQS Delay:
3340 13:31:06.779447 DQS0 = 0, DQS1 = 0
3341 13:31:06.779709 DQM Delay:
3342 13:31:06.782455 DQM0 = 117, DQM1 = 106
3343 13:31:06.782911 DQ Delay:
3344 13:31:06.785890 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =119
3345 13:31:06.789308 DQ4 =119, DQ5 =127, DQ6 =123, DQ7 =115
3346 13:31:06.792418 DQ8 =91, DQ9 =91, DQ10 =103, DQ11 =99
3347 13:31:06.799409 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3348 13:31:06.799750
3349 13:31:06.799992
3350 13:31:06.800203 ==
3351 13:31:06.802875 Dram Type= 6, Freq= 0, CH_1, rank 1
3352 13:31:06.806172 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3353 13:31:06.806525 ==
3354 13:31:06.806865
3355 13:31:06.807171
3356 13:31:06.809519 TX Vref Scan disable
3357 13:31:06.809874 == TX Byte 0 ==
3358 13:31:06.816226 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3359 13:31:06.819486 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3360 13:31:06.820002 == TX Byte 1 ==
3361 13:31:06.825846 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3362 13:31:06.829004 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3363 13:31:06.829352 ==
3364 13:31:06.832199 Dram Type= 6, Freq= 0, CH_1, rank 1
3365 13:31:06.835731 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3366 13:31:06.836182 ==
3367 13:31:06.848087 TX Vref=22, minBit 10, minWin=25, winSum=421
3368 13:31:06.851871 TX Vref=24, minBit 9, minWin=25, winSum=426
3369 13:31:06.855078 TX Vref=26, minBit 8, minWin=26, winSum=430
3370 13:31:06.858321 TX Vref=28, minBit 8, minWin=26, winSum=429
3371 13:31:06.861830 TX Vref=30, minBit 8, minWin=26, winSum=432
3372 13:31:06.864731 TX Vref=32, minBit 9, minWin=26, winSum=432
3373 13:31:06.871380 [TxChooseVref] Worse bit 8, Min win 26, Win sum 432, Final Vref 30
3374 13:31:06.871782
3375 13:31:06.875077 Final TX Range 1 Vref 30
3376 13:31:06.875469
3377 13:31:06.875829 ==
3378 13:31:06.878553 Dram Type= 6, Freq= 0, CH_1, rank 1
3379 13:31:06.881778 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3380 13:31:06.882242 ==
3381 13:31:06.884670
3382 13:31:06.885017
3383 13:31:06.885259 TX Vref Scan disable
3384 13:31:06.888305 == TX Byte 0 ==
3385 13:31:06.891392 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3386 13:31:06.894795 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3387 13:31:06.898259 == TX Byte 1 ==
3388 13:31:06.902051 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3389 13:31:06.907891 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3390 13:31:06.908268
3391 13:31:06.908650 [DATLAT]
3392 13:31:06.908946 Freq=1200, CH1 RK1
3393 13:31:06.909255
3394 13:31:06.911162 DATLAT Default: 0xc
3395 13:31:06.911442 0, 0xFFFF, sum = 0
3396 13:31:06.914917 1, 0xFFFF, sum = 0
3397 13:31:06.915294 2, 0xFFFF, sum = 0
3398 13:31:06.918117 3, 0xFFFF, sum = 0
3399 13:31:06.921696 4, 0xFFFF, sum = 0
3400 13:31:06.922174 5, 0xFFFF, sum = 0
3401 13:31:06.924983 6, 0xFFFF, sum = 0
3402 13:31:06.925458 7, 0xFFFF, sum = 0
3403 13:31:06.927844 8, 0xFFFF, sum = 0
3404 13:31:06.928228 9, 0xFFFF, sum = 0
3405 13:31:06.932028 10, 0xFFFF, sum = 0
3406 13:31:06.932588 11, 0x0, sum = 1
3407 13:31:06.935294 12, 0x0, sum = 2
3408 13:31:06.935753 13, 0x0, sum = 3
3409 13:31:06.937869 14, 0x0, sum = 4
3410 13:31:06.938200 best_step = 12
3411 13:31:06.938423
3412 13:31:06.938640 ==
3413 13:31:06.942132 Dram Type= 6, Freq= 0, CH_1, rank 1
3414 13:31:06.945185 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3415 13:31:06.945584 ==
3416 13:31:06.948244 RX Vref Scan: 0
3417 13:31:06.948619
3418 13:31:06.948862 RX Vref 0 -> 0, step: 1
3419 13:31:06.951817
3420 13:31:06.952267 RX Delay -29 -> 252, step: 4
3421 13:31:06.958864 iDelay=199, Bit 0, Center 114 (43 ~ 186) 144
3422 13:31:06.962403 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3423 13:31:06.965895 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3424 13:31:06.968797 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3425 13:31:06.971942 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3426 13:31:06.978526 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3427 13:31:06.982660 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3428 13:31:06.985730 iDelay=199, Bit 7, Center 112 (43 ~ 182) 140
3429 13:31:06.988877 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3430 13:31:06.992158 iDelay=199, Bit 9, Center 90 (23 ~ 158) 136
3431 13:31:06.998657 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3432 13:31:07.002464 iDelay=199, Bit 11, Center 96 (31 ~ 162) 132
3433 13:31:07.005745 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3434 13:31:07.008710 iDelay=199, Bit 13, Center 110 (43 ~ 178) 136
3435 13:31:07.012186 iDelay=199, Bit 14, Center 114 (47 ~ 182) 136
3436 13:31:07.018883 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3437 13:31:07.019435 ==
3438 13:31:07.022495 Dram Type= 6, Freq= 0, CH_1, rank 1
3439 13:31:07.025538 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3440 13:31:07.025957 ==
3441 13:31:07.026228 DQS Delay:
3442 13:31:07.028934 DQS0 = 0, DQS1 = 0
3443 13:31:07.029311 DQM Delay:
3444 13:31:07.032046 DQM0 = 114, DQM1 = 103
3445 13:31:07.032484 DQ Delay:
3446 13:31:07.035137 DQ0 =114, DQ1 =110, DQ2 =108, DQ3 =112
3447 13:31:07.038493 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3448 13:31:07.042334 DQ8 =86, DQ9 =90, DQ10 =106, DQ11 =96
3449 13:31:07.045346 DQ12 =112, DQ13 =110, DQ14 =114, DQ15 =110
3450 13:31:07.045710
3451 13:31:07.045955
3452 13:31:07.055595 [DQSOSCAuto] RK1, (LSB)MR18= 0x707, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
3453 13:31:07.058724 CH1 RK1: MR19=404, MR18=707
3454 13:31:07.062058 CH1_RK1: MR19=0x404, MR18=0x707, DQSOSC=407, MR23=63, INC=39, DEC=26
3455 13:31:07.065776 [RxdqsGatingPostProcess] freq 1200
3456 13:31:07.072164 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3457 13:31:07.075340 Pre-setting of DQS Precalculation
3458 13:31:07.079279 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3459 13:31:07.085971 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3460 13:31:07.095727 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3461 13:31:07.096228
3462 13:31:07.096679
3463 13:31:07.099046 [Calibration Summary] 2400 Mbps
3464 13:31:07.099554 CH 0, Rank 0
3465 13:31:07.102165 SW Impedance : PASS
3466 13:31:07.102603 DUTY Scan : NO K
3467 13:31:07.105354 ZQ Calibration : PASS
3468 13:31:07.108939 Jitter Meter : NO K
3469 13:31:07.109420 CBT Training : PASS
3470 13:31:07.111984 Write leveling : PASS
3471 13:31:07.115852 RX DQS gating : PASS
3472 13:31:07.116387 RX DQ/DQS(RDDQC) : PASS
3473 13:31:07.119063 TX DQ/DQS : PASS
3474 13:31:07.119552 RX DATLAT : PASS
3475 13:31:07.122164 RX DQ/DQS(Engine): PASS
3476 13:31:07.125494 TX OE : NO K
3477 13:31:07.125884 All Pass.
3478 13:31:07.126157
3479 13:31:07.126393 CH 0, Rank 1
3480 13:31:07.128903 SW Impedance : PASS
3481 13:31:07.131827 DUTY Scan : NO K
3482 13:31:07.132201 ZQ Calibration : PASS
3483 13:31:07.135965 Jitter Meter : NO K
3484 13:31:07.138399 CBT Training : PASS
3485 13:31:07.138771 Write leveling : PASS
3486 13:31:07.142224 RX DQS gating : PASS
3487 13:31:07.145749 RX DQ/DQS(RDDQC) : PASS
3488 13:31:07.146092 TX DQ/DQS : PASS
3489 13:31:07.148725 RX DATLAT : PASS
3490 13:31:07.152207 RX DQ/DQS(Engine): PASS
3491 13:31:07.152582 TX OE : NO K
3492 13:31:07.152829 All Pass.
3493 13:31:07.155458
3494 13:31:07.155797 CH 1, Rank 0
3495 13:31:07.159100 SW Impedance : PASS
3496 13:31:07.159555 DUTY Scan : NO K
3497 13:31:07.161849 ZQ Calibration : PASS
3498 13:31:07.162191 Jitter Meter : NO K
3499 13:31:07.165907 CBT Training : PASS
3500 13:31:07.169129 Write leveling : PASS
3501 13:31:07.169590 RX DQS gating : PASS
3502 13:31:07.172250 RX DQ/DQS(RDDQC) : PASS
3503 13:31:07.175557 TX DQ/DQS : PASS
3504 13:31:07.175921 RX DATLAT : PASS
3505 13:31:07.178777 RX DQ/DQS(Engine): PASS
3506 13:31:07.181862 TX OE : NO K
3507 13:31:07.182244 All Pass.
3508 13:31:07.182506
3509 13:31:07.182749 CH 1, Rank 1
3510 13:31:07.185449 SW Impedance : PASS
3511 13:31:07.188630 DUTY Scan : NO K
3512 13:31:07.188972 ZQ Calibration : PASS
3513 13:31:07.191956 Jitter Meter : NO K
3514 13:31:07.195310 CBT Training : PASS
3515 13:31:07.195653 Write leveling : PASS
3516 13:31:07.198863 RX DQS gating : PASS
3517 13:31:07.199317 RX DQ/DQS(RDDQC) : PASS
3518 13:31:07.201819 TX DQ/DQS : PASS
3519 13:31:07.205435 RX DATLAT : PASS
3520 13:31:07.205898 RX DQ/DQS(Engine): PASS
3521 13:31:07.208894 TX OE : NO K
3522 13:31:07.209351 All Pass.
3523 13:31:07.209608
3524 13:31:07.212422 DramC Write-DBI off
3525 13:31:07.215616 PER_BANK_REFRESH: Hybrid Mode
3526 13:31:07.216073 TX_TRACKING: ON
3527 13:31:07.225975 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3528 13:31:07.228560 [FAST_K] Save calibration result to emmc
3529 13:31:07.232202 dramc_set_vcore_voltage set vcore to 650000
3530 13:31:07.235615 Read voltage for 600, 5
3531 13:31:07.236120 Vio18 = 0
3532 13:31:07.238515 Vcore = 650000
3533 13:31:07.238916 Vdram = 0
3534 13:31:07.239189 Vddq = 0
3535 13:31:07.239426 Vmddr = 0
3536 13:31:07.245121 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3537 13:31:07.248957 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3538 13:31:07.252107 MEM_TYPE=3, freq_sel=19
3539 13:31:07.255158 sv_algorithm_assistance_LP4_1600
3540 13:31:07.258760 ============ PULL DRAM RESETB DOWN ============
3541 13:31:07.265540 ========== PULL DRAM RESETB DOWN end =========
3542 13:31:07.268816 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3543 13:31:07.272125 ===================================
3544 13:31:07.275809 LPDDR4 DRAM CONFIGURATION
3545 13:31:07.278320 ===================================
3546 13:31:07.278708 EX_ROW_EN[0] = 0x0
3547 13:31:07.281780 EX_ROW_EN[1] = 0x0
3548 13:31:07.282256 LP4Y_EN = 0x0
3549 13:31:07.284920 WORK_FSP = 0x0
3550 13:31:07.285300 WL = 0x2
3551 13:31:07.289017 RL = 0x2
3552 13:31:07.289497 BL = 0x2
3553 13:31:07.291807 RPST = 0x0
3554 13:31:07.292180 RD_PRE = 0x0
3555 13:31:07.295371 WR_PRE = 0x1
3556 13:31:07.295858 WR_PST = 0x0
3557 13:31:07.298460 DBI_WR = 0x0
3558 13:31:07.301812 DBI_RD = 0x0
3559 13:31:07.302194 OTF = 0x1
3560 13:31:07.305169 ===================================
3561 13:31:07.308588 ===================================
3562 13:31:07.308975 ANA top config
3563 13:31:07.311867 ===================================
3564 13:31:07.314893 DLL_ASYNC_EN = 0
3565 13:31:07.318319 ALL_SLAVE_EN = 1
3566 13:31:07.322182 NEW_RANK_MODE = 1
3567 13:31:07.322663 DLL_IDLE_MODE = 1
3568 13:31:07.325275 LP45_APHY_COMB_EN = 1
3569 13:31:07.328563 TX_ODT_DIS = 1
3570 13:31:07.331696 NEW_8X_MODE = 1
3571 13:31:07.335260 ===================================
3572 13:31:07.338266 ===================================
3573 13:31:07.341839 data_rate = 1200
3574 13:31:07.345112 CKR = 1
3575 13:31:07.345455 DQ_P2S_RATIO = 8
3576 13:31:07.348052 ===================================
3577 13:31:07.351254 CA_P2S_RATIO = 8
3578 13:31:07.354489 DQ_CA_OPEN = 0
3579 13:31:07.358431 DQ_SEMI_OPEN = 0
3580 13:31:07.361634 CA_SEMI_OPEN = 0
3581 13:31:07.364799 CA_FULL_RATE = 0
3582 13:31:07.365144 DQ_CKDIV4_EN = 1
3583 13:31:07.368219 CA_CKDIV4_EN = 1
3584 13:31:07.371098 CA_PREDIV_EN = 0
3585 13:31:07.375111 PH8_DLY = 0
3586 13:31:07.378248 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3587 13:31:07.381595 DQ_AAMCK_DIV = 4
3588 13:31:07.382056 CA_AAMCK_DIV = 4
3589 13:31:07.385097 CA_ADMCK_DIV = 4
3590 13:31:07.388595 DQ_TRACK_CA_EN = 0
3591 13:31:07.391559 CA_PICK = 600
3592 13:31:07.394410 CA_MCKIO = 600
3593 13:31:07.397831 MCKIO_SEMI = 0
3594 13:31:07.401048 PLL_FREQ = 2288
3595 13:31:07.401352 DQ_UI_PI_RATIO = 32
3596 13:31:07.404479 CA_UI_PI_RATIO = 0
3597 13:31:07.407965 ===================================
3598 13:31:07.410961 ===================================
3599 13:31:07.414797 memory_type:LPDDR4
3600 13:31:07.417854 GP_NUM : 10
3601 13:31:07.418320 SRAM_EN : 1
3602 13:31:07.420901 MD32_EN : 0
3603 13:31:07.424790 ===================================
3604 13:31:07.425276 [ANA_INIT] >>>>>>>>>>>>>>
3605 13:31:07.428041 <<<<<< [CONFIGURE PHASE]: ANA_TX
3606 13:31:07.430758 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3607 13:31:07.434112 ===================================
3608 13:31:07.437573 data_rate = 1200,PCW = 0X5800
3609 13:31:07.440833 ===================================
3610 13:31:07.444118 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3611 13:31:07.451304 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3612 13:31:07.457977 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3613 13:31:07.460974 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3614 13:31:07.464483 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3615 13:31:07.467439 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3616 13:31:07.471349 [ANA_INIT] flow start
3617 13:31:07.471884 [ANA_INIT] PLL >>>>>>>>
3618 13:31:07.474322 [ANA_INIT] PLL <<<<<<<<
3619 13:31:07.477547 [ANA_INIT] MIDPI >>>>>>>>
3620 13:31:07.477938 [ANA_INIT] MIDPI <<<<<<<<
3621 13:31:07.480690 [ANA_INIT] DLL >>>>>>>>
3622 13:31:07.484320 [ANA_INIT] flow end
3623 13:31:07.487909 ============ LP4 DIFF to SE enter ============
3624 13:31:07.491160 ============ LP4 DIFF to SE exit ============
3625 13:31:07.494108 [ANA_INIT] <<<<<<<<<<<<<
3626 13:31:07.497362 [Flow] Enable top DCM control >>>>>
3627 13:31:07.501264 [Flow] Enable top DCM control <<<<<
3628 13:31:07.503829 Enable DLL master slave shuffle
3629 13:31:07.507244 ==============================================================
3630 13:31:07.511205 Gating Mode config
3631 13:31:07.517360 ==============================================================
3632 13:31:07.517749 Config description:
3633 13:31:07.527303 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3634 13:31:07.534064 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3635 13:31:07.540080 SELPH_MODE 0: By rank 1: By Phase
3636 13:31:07.543774 ==============================================================
3637 13:31:07.547261 GAT_TRACK_EN = 1
3638 13:31:07.550416 RX_GATING_MODE = 2
3639 13:31:07.553601 RX_GATING_TRACK_MODE = 2
3640 13:31:07.557507 SELPH_MODE = 1
3641 13:31:07.560118 PICG_EARLY_EN = 1
3642 13:31:07.563804 VALID_LAT_VALUE = 1
3643 13:31:07.566967 ==============================================================
3644 13:31:07.570774 Enter into Gating configuration >>>>
3645 13:31:07.573566 Exit from Gating configuration <<<<
3646 13:31:07.576738 Enter into DVFS_PRE_config >>>>>
3647 13:31:07.590432 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3648 13:31:07.594058 Exit from DVFS_PRE_config <<<<<
3649 13:31:07.594561 Enter into PICG configuration >>>>
3650 13:31:07.596706 Exit from PICG configuration <<<<
3651 13:31:07.600175 [RX_INPUT] configuration >>>>>
3652 13:31:07.603257 [RX_INPUT] configuration <<<<<
3653 13:31:07.610460 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3654 13:31:07.613344 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3655 13:31:07.619610 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3656 13:31:07.626911 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3657 13:31:07.633104 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3658 13:31:07.639865 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3659 13:31:07.643428 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3660 13:31:07.646594 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3661 13:31:07.650181 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3662 13:31:07.656411 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3663 13:31:07.659310 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3664 13:31:07.662882 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3665 13:31:07.666079 ===================================
3666 13:31:07.669841 LPDDR4 DRAM CONFIGURATION
3667 13:31:07.672871 ===================================
3668 13:31:07.676395 EX_ROW_EN[0] = 0x0
3669 13:31:07.676738 EX_ROW_EN[1] = 0x0
3670 13:31:07.679298 LP4Y_EN = 0x0
3671 13:31:07.679639 WORK_FSP = 0x0
3672 13:31:07.683351 WL = 0x2
3673 13:31:07.683823 RL = 0x2
3674 13:31:07.685769 BL = 0x2
3675 13:31:07.686117 RPST = 0x0
3676 13:31:07.689496 RD_PRE = 0x0
3677 13:31:07.689889 WR_PRE = 0x1
3678 13:31:07.692891 WR_PST = 0x0
3679 13:31:07.693346 DBI_WR = 0x0
3680 13:31:07.696076 DBI_RD = 0x0
3681 13:31:07.699500 OTF = 0x1
3682 13:31:07.702369 ===================================
3683 13:31:07.705955 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3684 13:31:07.709535 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3685 13:31:07.712551 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3686 13:31:07.715720 ===================================
3687 13:31:07.719208 LPDDR4 DRAM CONFIGURATION
3688 13:31:07.722369 ===================================
3689 13:31:07.726105 EX_ROW_EN[0] = 0x10
3690 13:31:07.726451 EX_ROW_EN[1] = 0x0
3691 13:31:07.729561 LP4Y_EN = 0x0
3692 13:31:07.729906 WORK_FSP = 0x0
3693 13:31:07.732505 WL = 0x2
3694 13:31:07.732799 RL = 0x2
3695 13:31:07.736049 BL = 0x2
3696 13:31:07.736342 RPST = 0x0
3697 13:31:07.738834 RD_PRE = 0x0
3698 13:31:07.739090 WR_PRE = 0x1
3699 13:31:07.742743 WR_PST = 0x0
3700 13:31:07.743230 DBI_WR = 0x0
3701 13:31:07.746014 DBI_RD = 0x0
3702 13:31:07.746381 OTF = 0x1
3703 13:31:07.749122 ===================================
3704 13:31:07.755903 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3705 13:31:07.760564 nWR fixed to 30
3706 13:31:07.763737 [ModeRegInit_LP4] CH0 RK0
3707 13:31:07.764085 [ModeRegInit_LP4] CH0 RK1
3708 13:31:07.767557 [ModeRegInit_LP4] CH1 RK0
3709 13:31:07.770593 [ModeRegInit_LP4] CH1 RK1
3710 13:31:07.771045 match AC timing 16
3711 13:31:07.777667 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3712 13:31:07.780436 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3713 13:31:07.783626 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3714 13:31:07.790589 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3715 13:31:07.793494 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3716 13:31:07.793959 ==
3717 13:31:07.796636 Dram Type= 6, Freq= 0, CH_0, rank 0
3718 13:31:07.800168 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3719 13:31:07.800651 ==
3720 13:31:07.806508 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3721 13:31:07.813671 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3722 13:31:07.816351 [CA 0] Center 35 (5~66) winsize 62
3723 13:31:07.820469 [CA 1] Center 35 (5~66) winsize 62
3724 13:31:07.823199 [CA 2] Center 34 (4~65) winsize 62
3725 13:31:07.826552 [CA 3] Center 34 (4~65) winsize 62
3726 13:31:07.829735 [CA 4] Center 33 (3~64) winsize 62
3727 13:31:07.832642 [CA 5] Center 33 (3~64) winsize 62
3728 13:31:07.832971
3729 13:31:07.836439 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3730 13:31:07.836871
3731 13:31:07.839595 [CATrainingPosCal] consider 1 rank data
3732 13:31:07.843344 u2DelayCellTimex100 = 270/100 ps
3733 13:31:07.846439 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3734 13:31:07.849915 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3735 13:31:07.853070 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3736 13:31:07.856371 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3737 13:31:07.863037 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3738 13:31:07.866322 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3739 13:31:07.866701
3740 13:31:07.869704 CA PerBit enable=1, Macro0, CA PI delay=33
3741 13:31:07.870048
3742 13:31:07.872770 [CBTSetCACLKResult] CA Dly = 33
3743 13:31:07.873122 CS Dly: 4 (0~35)
3744 13:31:07.873368 ==
3745 13:31:07.876512 Dram Type= 6, Freq= 0, CH_0, rank 1
3746 13:31:07.883679 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3747 13:31:07.884305 ==
3748 13:31:07.886030 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3749 13:31:07.893102 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3750 13:31:07.896167 [CA 0] Center 36 (6~66) winsize 61
3751 13:31:07.899294 [CA 1] Center 35 (5~66) winsize 62
3752 13:31:07.902990 [CA 2] Center 34 (4~65) winsize 62
3753 13:31:07.905867 [CA 3] Center 34 (4~65) winsize 62
3754 13:31:07.909259 [CA 4] Center 33 (3~64) winsize 62
3755 13:31:07.912806 [CA 5] Center 33 (3~64) winsize 62
3756 13:31:07.913150
3757 13:31:07.916043 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3758 13:31:07.916411
3759 13:31:07.919218 [CATrainingPosCal] consider 2 rank data
3760 13:31:07.922522 u2DelayCellTimex100 = 270/100 ps
3761 13:31:07.926250 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3762 13:31:07.929571 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3763 13:31:07.935773 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3764 13:31:07.939081 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3765 13:31:07.942153 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3766 13:31:07.946021 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3767 13:31:07.946465
3768 13:31:07.948899 CA PerBit enable=1, Macro0, CA PI delay=33
3769 13:31:07.949265
3770 13:31:07.953167 [CBTSetCACLKResult] CA Dly = 33
3771 13:31:07.953613 CS Dly: 4 (0~36)
3772 13:31:07.953863
3773 13:31:07.955425 ----->DramcWriteLeveling(PI) begin...
3774 13:31:07.958797 ==
3775 13:31:07.962391 Dram Type= 6, Freq= 0, CH_0, rank 0
3776 13:31:07.965329 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3777 13:31:07.965675 ==
3778 13:31:07.968936 Write leveling (Byte 0): 29 => 29
3779 13:31:07.972081 Write leveling (Byte 1): 29 => 29
3780 13:31:07.975538 DramcWriteLeveling(PI) end<-----
3781 13:31:07.975904
3782 13:31:07.976145 ==
3783 13:31:07.978485 Dram Type= 6, Freq= 0, CH_0, rank 0
3784 13:31:07.982096 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3785 13:31:07.982441 ==
3786 13:31:07.985097 [Gating] SW mode calibration
3787 13:31:07.991925 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3788 13:31:07.998412 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3789 13:31:08.001714 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3790 13:31:08.005111 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3791 13:31:08.011612 0 5 8 | B1->B0 | 3333 3232 | 0 1 | (0 1) (0 1)
3792 13:31:08.014906 0 5 12 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (1 0)
3793 13:31:08.018370 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3794 13:31:08.025035 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3795 13:31:08.028409 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3796 13:31:08.031261 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3797 13:31:08.037851 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3798 13:31:08.041563 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3799 13:31:08.044252 0 6 8 | B1->B0 | 2c2c 3434 | 0 0 | (1 1) (0 0)
3800 13:31:08.051049 0 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3801 13:31:08.055062 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3802 13:31:08.058263 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3803 13:31:08.064302 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3804 13:31:08.067712 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3805 13:31:08.071059 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3806 13:31:08.077740 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3807 13:31:08.081399 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3808 13:31:08.084032 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3809 13:31:08.090733 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3810 13:31:08.094517 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3811 13:31:08.097591 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3812 13:31:08.104215 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3813 13:31:08.107619 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3814 13:31:08.111130 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3815 13:31:08.117754 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3816 13:31:08.121115 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3817 13:31:08.124643 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3818 13:31:08.130620 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3819 13:31:08.133472 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3820 13:31:08.137123 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3821 13:31:08.140519 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3822 13:31:08.147092 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3823 13:31:08.150441 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3824 13:31:08.153943 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3825 13:31:08.156908 Total UI for P1: 0, mck2ui 16
3826 13:31:08.160516 best dqsien dly found for B0: ( 0, 9, 8)
3827 13:31:08.163344 Total UI for P1: 0, mck2ui 16
3828 13:31:08.167018 best dqsien dly found for B1: ( 0, 9, 10)
3829 13:31:08.170417 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
3830 13:31:08.176978 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
3831 13:31:08.177466
3832 13:31:08.180313 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
3833 13:31:08.183533 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
3834 13:31:08.186763 [Gating] SW calibration Done
3835 13:31:08.187229 ==
3836 13:31:08.190263 Dram Type= 6, Freq= 0, CH_0, rank 0
3837 13:31:08.193442 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3838 13:31:08.193927 ==
3839 13:31:08.196831 RX Vref Scan: 0
3840 13:31:08.197215
3841 13:31:08.197558 RX Vref 0 -> 0, step: 1
3842 13:31:08.197866
3843 13:31:08.199579 RX Delay -230 -> 252, step: 16
3844 13:31:08.203055 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3845 13:31:08.210249 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3846 13:31:08.213405 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3847 13:31:08.216376 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3848 13:31:08.219851 iDelay=218, Bit 4, Center 41 (-134 ~ 217) 352
3849 13:31:08.226695 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3850 13:31:08.229892 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3851 13:31:08.232754 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3852 13:31:08.236067 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3853 13:31:08.239689 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3854 13:31:08.246051 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3855 13:31:08.249259 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3856 13:31:08.252531 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3857 13:31:08.256165 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3858 13:31:08.262767 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3859 13:31:08.266229 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3860 13:31:08.266635 ==
3861 13:31:08.269109 Dram Type= 6, Freq= 0, CH_0, rank 0
3862 13:31:08.272644 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3863 13:31:08.273103 ==
3864 13:31:08.275820 DQS Delay:
3865 13:31:08.276195 DQS0 = 0, DQS1 = 0
3866 13:31:08.279318 DQM Delay:
3867 13:31:08.279792 DQM0 = 37, DQM1 = 33
3868 13:31:08.280065 DQ Delay:
3869 13:31:08.283016 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3870 13:31:08.286043 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
3871 13:31:08.289216 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3872 13:31:08.292673 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3873 13:31:08.293147
3874 13:31:08.293420
3875 13:31:08.295664 ==
3876 13:31:08.298952 Dram Type= 6, Freq= 0, CH_0, rank 0
3877 13:31:08.302378 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3878 13:31:08.302867 ==
3879 13:31:08.303145
3880 13:31:08.303389
3881 13:31:08.305375 TX Vref Scan disable
3882 13:31:08.305749 == TX Byte 0 ==
3883 13:31:08.308673 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3884 13:31:08.315889 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3885 13:31:08.316419 == TX Byte 1 ==
3886 13:31:08.319036 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3887 13:31:08.325962 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3888 13:31:08.326371 ==
3889 13:31:08.328733 Dram Type= 6, Freq= 0, CH_0, rank 0
3890 13:31:08.332047 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3891 13:31:08.332423 ==
3892 13:31:08.332672
3893 13:31:08.332892
3894 13:31:08.334971 TX Vref Scan disable
3895 13:31:08.338124 == TX Byte 0 ==
3896 13:31:08.341892 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3897 13:31:08.345304 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3898 13:31:08.348676 == TX Byte 1 ==
3899 13:31:08.351622 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3900 13:31:08.355090 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3901 13:31:08.355530
3902 13:31:08.358155 [DATLAT]
3903 13:31:08.358606 Freq=600, CH0 RK0
3904 13:31:08.358877
3905 13:31:08.362069 DATLAT Default: 0x9
3906 13:31:08.362455 0, 0xFFFF, sum = 0
3907 13:31:08.364768 1, 0xFFFF, sum = 0
3908 13:31:08.365119 2, 0xFFFF, sum = 0
3909 13:31:08.368533 3, 0xFFFF, sum = 0
3910 13:31:08.368956 4, 0xFFFF, sum = 0
3911 13:31:08.371444 5, 0xFFFF, sum = 0
3912 13:31:08.371793 6, 0xFFFF, sum = 0
3913 13:31:08.375271 7, 0x0, sum = 1
3914 13:31:08.375695 8, 0x0, sum = 2
3915 13:31:08.378390 9, 0x0, sum = 3
3916 13:31:08.378739 10, 0x0, sum = 4
3917 13:31:08.381701 best_step = 8
3918 13:31:08.382164
3919 13:31:08.382428 ==
3920 13:31:08.384746 Dram Type= 6, Freq= 0, CH_0, rank 0
3921 13:31:08.388588 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3922 13:31:08.389070 ==
3923 13:31:08.391696 RX Vref Scan: 1
3924 13:31:08.392159
3925 13:31:08.392460 RX Vref 0 -> 0, step: 1
3926 13:31:08.392676
3927 13:31:08.394876 RX Delay -195 -> 252, step: 8
3928 13:31:08.395221
3929 13:31:08.398081 Set Vref, RX VrefLevel [Byte0]: 47
3930 13:31:08.401390 [Byte1]: 49
3931 13:31:08.404965
3932 13:31:08.405449 Final RX Vref Byte 0 = 47 to rank0
3933 13:31:08.408484 Final RX Vref Byte 1 = 49 to rank0
3934 13:31:08.411696 Final RX Vref Byte 0 = 47 to rank1
3935 13:31:08.415003 Final RX Vref Byte 1 = 49 to rank1==
3936 13:31:08.418937 Dram Type= 6, Freq= 0, CH_0, rank 0
3937 13:31:08.424938 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3938 13:31:08.425361 ==
3939 13:31:08.425630 DQS Delay:
3940 13:31:08.425869 DQS0 = 0, DQS1 = 0
3941 13:31:08.428661 DQM Delay:
3942 13:31:08.429171 DQM0 = 40, DQM1 = 30
3943 13:31:08.432016 DQ Delay:
3944 13:31:08.435433 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =36
3945 13:31:08.435812 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =48
3946 13:31:08.438973 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
3947 13:31:08.441760 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =40
3948 13:31:08.445751
3949 13:31:08.446094
3950 13:31:08.451742 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b4b, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
3951 13:31:08.455061 CH0 RK0: MR19=808, MR18=4B4B
3952 13:31:08.461959 CH0_RK0: MR19=0x808, MR18=0x4B4B, DQSOSC=395, MR23=63, INC=168, DEC=112
3953 13:31:08.462405
3954 13:31:08.464766 ----->DramcWriteLeveling(PI) begin...
3955 13:31:08.465136 ==
3956 13:31:08.468333 Dram Type= 6, Freq= 0, CH_0, rank 1
3957 13:31:08.471900 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3958 13:31:08.472258 ==
3959 13:31:08.474738 Write leveling (Byte 0): 31 => 31
3960 13:31:08.478265 Write leveling (Byte 1): 29 => 29
3961 13:31:08.481659 DramcWriteLeveling(PI) end<-----
3962 13:31:08.482112
3963 13:31:08.482377 ==
3964 13:31:08.484925 Dram Type= 6, Freq= 0, CH_0, rank 1
3965 13:31:08.488079 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3966 13:31:08.488594 ==
3967 13:31:08.491851 [Gating] SW mode calibration
3968 13:31:08.498166 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3969 13:31:08.504774 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3970 13:31:08.508104 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3971 13:31:08.511565 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3972 13:31:08.518530 0 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
3973 13:31:08.521557 0 5 12 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
3974 13:31:08.524907 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3975 13:31:08.531303 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3976 13:31:08.534474 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3977 13:31:08.538438 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3978 13:31:08.544984 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 13:31:08.547650 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 13:31:08.550984 0 6 8 | B1->B0 | 2b2b 3232 | 1 0 | (0 0) (1 1)
3981 13:31:08.557971 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3982 13:31:08.561134 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3983 13:31:08.564304 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 13:31:08.570826 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3985 13:31:08.575090 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 13:31:08.577736 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 13:31:08.584448 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 13:31:08.587587 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3989 13:31:08.591256 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3990 13:31:08.597601 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 13:31:08.600609 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 13:31:08.604013 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 13:31:08.610627 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 13:31:08.613771 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 13:31:08.617446 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 13:31:08.624185 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 13:31:08.627459 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 13:31:08.630629 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 13:31:08.637128 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 13:31:08.640141 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 13:31:08.643742 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 13:31:08.650368 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 13:31:08.653841 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 13:31:08.657084 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4005 13:31:08.663722 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 13:31:08.664256 Total UI for P1: 0, mck2ui 16
4007 13:31:08.670376 best dqsien dly found for B0: ( 0, 9, 8)
4008 13:31:08.670815 Total UI for P1: 0, mck2ui 16
4009 13:31:08.676682 best dqsien dly found for B1: ( 0, 9, 8)
4010 13:31:08.680244 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4011 13:31:08.683964 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4012 13:31:08.684513
4013 13:31:08.686800 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4014 13:31:08.690437 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4015 13:31:08.693873 [Gating] SW calibration Done
4016 13:31:08.694289 ==
4017 13:31:08.697048 Dram Type= 6, Freq= 0, CH_0, rank 1
4018 13:31:08.700511 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4019 13:31:08.700895 ==
4020 13:31:08.703260 RX Vref Scan: 0
4021 13:31:08.703762
4022 13:31:08.704054 RX Vref 0 -> 0, step: 1
4023 13:31:08.704335
4024 13:31:08.706844 RX Delay -230 -> 252, step: 16
4025 13:31:08.710137 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4026 13:31:08.716240 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4027 13:31:08.719833 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4028 13:31:08.723073 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4029 13:31:08.726392 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4030 13:31:08.732940 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4031 13:31:08.736014 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4032 13:31:08.739651 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4033 13:31:08.743024 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4034 13:31:08.746766 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4035 13:31:08.753653 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4036 13:31:08.756582 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4037 13:31:08.759745 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4038 13:31:08.763124 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4039 13:31:08.769760 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4040 13:31:08.772923 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4041 13:31:08.773385 ==
4042 13:31:08.776261 Dram Type= 6, Freq= 0, CH_0, rank 1
4043 13:31:08.779775 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4044 13:31:08.780117 ==
4045 13:31:08.782786 DQS Delay:
4046 13:31:08.783205 DQS0 = 0, DQS1 = 0
4047 13:31:08.783451 DQM Delay:
4048 13:31:08.786641 DQM0 = 41, DQM1 = 33
4049 13:31:08.786984 DQ Delay:
4050 13:31:08.789710 DQ0 =33, DQ1 =49, DQ2 =33, DQ3 =33
4051 13:31:08.793278 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4052 13:31:08.796137 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4053 13:31:08.799660 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4054 13:31:08.800061
4055 13:31:08.800334
4056 13:31:08.800560 ==
4057 13:31:08.802975 Dram Type= 6, Freq= 0, CH_0, rank 1
4058 13:31:08.809320 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4059 13:31:08.809665 ==
4060 13:31:08.809911
4061 13:31:08.810125
4062 13:31:08.810324 TX Vref Scan disable
4063 13:31:08.813168 == TX Byte 0 ==
4064 13:31:08.816361 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4065 13:31:08.823438 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4066 13:31:08.823850 == TX Byte 1 ==
4067 13:31:08.826580 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4068 13:31:08.833100 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4069 13:31:08.833512 ==
4070 13:31:08.836199 Dram Type= 6, Freq= 0, CH_0, rank 1
4071 13:31:08.839690 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4072 13:31:08.840029 ==
4073 13:31:08.840268
4074 13:31:08.840532
4075 13:31:08.843030 TX Vref Scan disable
4076 13:31:08.846375 == TX Byte 0 ==
4077 13:31:08.850261 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4078 13:31:08.853254 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4079 13:31:08.855995 == TX Byte 1 ==
4080 13:31:08.859796 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4081 13:31:08.862993 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4082 13:31:08.863495
4083 13:31:08.863783 [DATLAT]
4084 13:31:08.866421 Freq=600, CH0 RK1
4085 13:31:08.866802
4086 13:31:08.869261 DATLAT Default: 0x8
4087 13:31:08.869611 0, 0xFFFF, sum = 0
4088 13:31:08.873148 1, 0xFFFF, sum = 0
4089 13:31:08.873602 2, 0xFFFF, sum = 0
4090 13:31:08.876193 3, 0xFFFF, sum = 0
4091 13:31:08.876583 4, 0xFFFF, sum = 0
4092 13:31:08.879197 5, 0xFFFF, sum = 0
4093 13:31:08.879546 6, 0xFFFF, sum = 0
4094 13:31:08.882791 7, 0x0, sum = 1
4095 13:31:08.883160 8, 0x0, sum = 2
4096 13:31:08.883415 9, 0x0, sum = 3
4097 13:31:08.886206 10, 0x0, sum = 4
4098 13:31:08.886553 best_step = 8
4099 13:31:08.886800
4100 13:31:08.889623 ==
4101 13:31:08.889999 Dram Type= 6, Freq= 0, CH_0, rank 1
4102 13:31:08.896098 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4103 13:31:08.896603 ==
4104 13:31:08.896881 RX Vref Scan: 0
4105 13:31:08.897095
4106 13:31:08.899317 RX Vref 0 -> 0, step: 1
4107 13:31:08.899674
4108 13:31:08.903204 RX Delay -195 -> 252, step: 8
4109 13:31:08.909086 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4110 13:31:08.912710 iDelay=205, Bit 1, Center 48 (-107 ~ 204) 312
4111 13:31:08.915739 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4112 13:31:08.919353 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4113 13:31:08.922416 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4114 13:31:08.929304 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4115 13:31:08.932565 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4116 13:31:08.935791 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4117 13:31:08.938871 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4118 13:31:08.946042 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4119 13:31:08.949632 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4120 13:31:08.952318 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4121 13:31:08.955669 iDelay=205, Bit 12, Center 36 (-115 ~ 188) 304
4122 13:31:08.959355 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4123 13:31:08.965642 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4124 13:31:08.968970 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4125 13:31:08.969313 ==
4126 13:31:08.971965 Dram Type= 6, Freq= 0, CH_0, rank 1
4127 13:31:08.975608 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4128 13:31:08.975955 ==
4129 13:31:08.978552 DQS Delay:
4130 13:31:08.978906 DQS0 = 0, DQS1 = 0
4131 13:31:08.981920 DQM Delay:
4132 13:31:08.982354 DQM0 = 42, DQM1 = 32
4133 13:31:08.982622 DQ Delay:
4134 13:31:08.985613 DQ0 =36, DQ1 =48, DQ2 =40, DQ3 =36
4135 13:31:08.988601 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4136 13:31:08.991999 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4137 13:31:08.995525 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =44
4138 13:31:08.995977
4139 13:31:08.996232
4140 13:31:09.005394 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c6c, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4141 13:31:09.008526 CH0 RK1: MR19=808, MR18=6C6C
4142 13:31:09.015671 CH0_RK1: MR19=0x808, MR18=0x6C6C, DQSOSC=389, MR23=63, INC=173, DEC=115
4143 13:31:09.016140 [RxdqsGatingPostProcess] freq 600
4144 13:31:09.021991 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4145 13:31:09.025188 Pre-setting of DQS Precalculation
4146 13:31:09.028603 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4147 13:31:09.031804 ==
4148 13:31:09.035072 Dram Type= 6, Freq= 0, CH_1, rank 0
4149 13:31:09.038402 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4150 13:31:09.038781 ==
4151 13:31:09.041468 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4152 13:31:09.048703 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4153 13:31:09.052045 [CA 0] Center 35 (5~66) winsize 62
4154 13:31:09.055699 [CA 1] Center 35 (5~66) winsize 62
4155 13:31:09.058322 [CA 2] Center 33 (3~64) winsize 62
4156 13:31:09.061841 [CA 3] Center 33 (3~64) winsize 62
4157 13:31:09.065472 [CA 4] Center 33 (2~64) winsize 63
4158 13:31:09.068920 [CA 5] Center 33 (2~64) winsize 63
4159 13:31:09.069281
4160 13:31:09.071854 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4161 13:31:09.072202
4162 13:31:09.075648 [CATrainingPosCal] consider 1 rank data
4163 13:31:09.078678 u2DelayCellTimex100 = 270/100 ps
4164 13:31:09.081951 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4165 13:31:09.085236 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4166 13:31:09.092213 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4167 13:31:09.095596 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4168 13:31:09.098891 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4169 13:31:09.102130 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4170 13:31:09.102596
4171 13:31:09.105318 CA PerBit enable=1, Macro0, CA PI delay=33
4172 13:31:09.105665
4173 13:31:09.108698 [CBTSetCACLKResult] CA Dly = 33
4174 13:31:09.109043 CS Dly: 4 (0~35)
4175 13:31:09.112139 ==
4176 13:31:09.112679 Dram Type= 6, Freq= 0, CH_1, rank 1
4177 13:31:09.118524 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4178 13:31:09.118903 ==
4179 13:31:09.121916 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4180 13:31:09.128222 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4181 13:31:09.131898 [CA 0] Center 35 (5~66) winsize 62
4182 13:31:09.135447 [CA 1] Center 34 (4~65) winsize 62
4183 13:31:09.138719 [CA 2] Center 33 (3~64) winsize 62
4184 13:31:09.142121 [CA 3] Center 33 (3~64) winsize 62
4185 13:31:09.145350 [CA 4] Center 32 (2~63) winsize 62
4186 13:31:09.148523 [CA 5] Center 32 (2~63) winsize 62
4187 13:31:09.148867
4188 13:31:09.151513 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4189 13:31:09.151859
4190 13:31:09.155194 [CATrainingPosCal] consider 2 rank data
4191 13:31:09.158885 u2DelayCellTimex100 = 270/100 ps
4192 13:31:09.161834 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4193 13:31:09.168070 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4194 13:31:09.171632 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4195 13:31:09.175299 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4196 13:31:09.178303 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4197 13:31:09.181665 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4198 13:31:09.182009
4199 13:31:09.184560 CA PerBit enable=1, Macro0, CA PI delay=32
4200 13:31:09.184903
4201 13:31:09.188042 [CBTSetCACLKResult] CA Dly = 32
4202 13:31:09.191459 CS Dly: 4 (0~35)
4203 13:31:09.191802
4204 13:31:09.194674 ----->DramcWriteLeveling(PI) begin...
4205 13:31:09.195030 ==
4206 13:31:09.197776 Dram Type= 6, Freq= 0, CH_1, rank 0
4207 13:31:09.201443 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4208 13:31:09.201786 ==
4209 13:31:09.204709 Write leveling (Byte 0): 29 => 29
4210 13:31:09.208618 Write leveling (Byte 1): 29 => 29
4211 13:31:09.211343 DramcWriteLeveling(PI) end<-----
4212 13:31:09.211976
4213 13:31:09.212418 ==
4214 13:31:09.214714 Dram Type= 6, Freq= 0, CH_1, rank 0
4215 13:31:09.217855 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4216 13:31:09.218203 ==
4217 13:31:09.221211 [Gating] SW mode calibration
4218 13:31:09.228221 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4219 13:31:09.234755 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4220 13:31:09.237418 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4221 13:31:09.240810 0 5 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
4222 13:31:09.247867 0 5 8 | B1->B0 | 2f2f 2525 | 1 0 | (1 1) (1 0)
4223 13:31:09.250721 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 13:31:09.254302 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 13:31:09.260628 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 13:31:09.264361 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 13:31:09.267204 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4228 13:31:09.274147 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 13:31:09.277179 0 6 4 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
4230 13:31:09.280520 0 6 8 | B1->B0 | 3636 4242 | 1 0 | (0 0) (0 0)
4231 13:31:09.287385 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 13:31:09.290518 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 13:31:09.293642 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 13:31:09.300745 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 13:31:09.303891 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 13:31:09.307082 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 13:31:09.313775 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 13:31:09.317757 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4239 13:31:09.320975 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 13:31:09.326882 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 13:31:09.330556 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 13:31:09.333706 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 13:31:09.340170 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 13:31:09.343168 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 13:31:09.347121 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 13:31:09.353647 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 13:31:09.356895 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 13:31:09.359931 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 13:31:09.366508 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 13:31:09.369890 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 13:31:09.373445 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 13:31:09.379752 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 13:31:09.383168 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4254 13:31:09.386960 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4255 13:31:09.393348 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4256 13:31:09.393792 Total UI for P1: 0, mck2ui 16
4257 13:31:09.399699 best dqsien dly found for B0: ( 0, 9, 6)
4258 13:31:09.403455 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4259 13:31:09.406256 Total UI for P1: 0, mck2ui 16
4260 13:31:09.409355 best dqsien dly found for B1: ( 0, 9, 12)
4261 13:31:09.412751 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4262 13:31:09.415957 best DQS1 dly(MCK, UI, PI) = (0, 9, 12)
4263 13:31:09.416335
4264 13:31:09.419276 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4265 13:31:09.423142 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 12)
4266 13:31:09.426148 [Gating] SW calibration Done
4267 13:31:09.426501 ==
4268 13:31:09.430218 Dram Type= 6, Freq= 0, CH_1, rank 0
4269 13:31:09.433054 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4270 13:31:09.433410 ==
4271 13:31:09.436158 RX Vref Scan: 0
4272 13:31:09.436494
4273 13:31:09.439501 RX Vref 0 -> 0, step: 1
4274 13:31:09.439903
4275 13:31:09.440192 RX Delay -230 -> 252, step: 16
4276 13:31:09.445924 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4277 13:31:09.449367 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4278 13:31:09.452503 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4279 13:31:09.455956 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4280 13:31:09.462754 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4281 13:31:09.466038 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4282 13:31:09.469691 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4283 13:31:09.473391 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4284 13:31:09.476114 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4285 13:31:09.482847 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4286 13:31:09.486209 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4287 13:31:09.489495 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4288 13:31:09.493007 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4289 13:31:09.499167 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4290 13:31:09.502595 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4291 13:31:09.505566 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4292 13:31:09.506014 ==
4293 13:31:09.509271 Dram Type= 6, Freq= 0, CH_1, rank 0
4294 13:31:09.515678 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4295 13:31:09.516070 ==
4296 13:31:09.516353 DQS Delay:
4297 13:31:09.516581 DQS0 = 0, DQS1 = 0
4298 13:31:09.518914 DQM Delay:
4299 13:31:09.519257 DQM0 = 39, DQM1 = 32
4300 13:31:09.522396 DQ Delay:
4301 13:31:09.525711 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4302 13:31:09.529142 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4303 13:31:09.531913 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4304 13:31:09.535124 DQ12 =33, DQ13 =49, DQ14 =33, DQ15 =49
4305 13:31:09.535340
4306 13:31:09.535494
4307 13:31:09.535632 ==
4308 13:31:09.539418 Dram Type= 6, Freq= 0, CH_1, rank 0
4309 13:31:09.542239 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4310 13:31:09.542572 ==
4311 13:31:09.542865
4312 13:31:09.543078
4313 13:31:09.546292 TX Vref Scan disable
4314 13:31:09.546655 == TX Byte 0 ==
4315 13:31:09.552116 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4316 13:31:09.555402 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4317 13:31:09.555490 == TX Byte 1 ==
4318 13:31:09.562613 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4319 13:31:09.565323 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4320 13:31:09.565402 ==
4321 13:31:09.569027 Dram Type= 6, Freq= 0, CH_1, rank 0
4322 13:31:09.572182 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4323 13:31:09.572682 ==
4324 13:31:09.572950
4325 13:31:09.573170
4326 13:31:09.575373 TX Vref Scan disable
4327 13:31:09.578645 == TX Byte 0 ==
4328 13:31:09.582221 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4329 13:31:09.589060 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4330 13:31:09.589518 == TX Byte 1 ==
4331 13:31:09.592120 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4332 13:31:09.598522 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4333 13:31:09.598918
4334 13:31:09.599163 [DATLAT]
4335 13:31:09.599434 Freq=600, CH1 RK0
4336 13:31:09.599711
4337 13:31:09.601875 DATLAT Default: 0x9
4338 13:31:09.602451 0, 0xFFFF, sum = 0
4339 13:31:09.605210 1, 0xFFFF, sum = 0
4340 13:31:09.608422 2, 0xFFFF, sum = 0
4341 13:31:09.608873 3, 0xFFFF, sum = 0
4342 13:31:09.612363 4, 0xFFFF, sum = 0
4343 13:31:09.612785 5, 0xFFFF, sum = 0
4344 13:31:09.615138 6, 0xFFFF, sum = 0
4345 13:31:09.615519 7, 0x0, sum = 1
4346 13:31:09.618891 8, 0x0, sum = 2
4347 13:31:09.619362 9, 0x0, sum = 3
4348 13:31:09.619626 10, 0x0, sum = 4
4349 13:31:09.621571 best_step = 8
4350 13:31:09.621937
4351 13:31:09.622181 ==
4352 13:31:09.624911 Dram Type= 6, Freq= 0, CH_1, rank 0
4353 13:31:09.628610 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4354 13:31:09.629066 ==
4355 13:31:09.631487 RX Vref Scan: 1
4356 13:31:09.631941
4357 13:31:09.632195 RX Vref 0 -> 0, step: 1
4358 13:31:09.635127
4359 13:31:09.635471 RX Delay -195 -> 252, step: 8
4360 13:31:09.635716
4361 13:31:09.638070 Set Vref, RX VrefLevel [Byte0]: 53
4362 13:31:09.641444 [Byte1]: 49
4363 13:31:09.646168
4364 13:31:09.646516 Final RX Vref Byte 0 = 53 to rank0
4365 13:31:09.648925 Final RX Vref Byte 1 = 49 to rank0
4366 13:31:09.652688 Final RX Vref Byte 0 = 53 to rank1
4367 13:31:09.656581 Final RX Vref Byte 1 = 49 to rank1==
4368 13:31:09.658909 Dram Type= 6, Freq= 0, CH_1, rank 0
4369 13:31:09.665906 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4370 13:31:09.666409 ==
4371 13:31:09.666681 DQS Delay:
4372 13:31:09.666901 DQS0 = 0, DQS1 = 0
4373 13:31:09.669603 DQM Delay:
4374 13:31:09.670064 DQM0 = 37, DQM1 = 31
4375 13:31:09.672633 DQ Delay:
4376 13:31:09.675869 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4377 13:31:09.676239 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4378 13:31:09.679316 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4379 13:31:09.685568 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4380 13:31:09.685998
4381 13:31:09.686241
4382 13:31:09.692640 [DQSOSCAuto] RK0, (LSB)MR18= 0x7272, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
4383 13:31:09.696055 CH1 RK0: MR19=808, MR18=7272
4384 13:31:09.702191 CH1_RK0: MR19=0x808, MR18=0x7272, DQSOSC=388, MR23=63, INC=174, DEC=116
4385 13:31:09.702630
4386 13:31:09.705585 ----->DramcWriteLeveling(PI) begin...
4387 13:31:09.706016 ==
4388 13:31:09.708694 Dram Type= 6, Freq= 0, CH_1, rank 1
4389 13:31:09.712583 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4390 13:31:09.713101 ==
4391 13:31:09.715251 Write leveling (Byte 0): 26 => 26
4392 13:31:09.718603 Write leveling (Byte 1): 29 => 29
4393 13:31:09.721967 DramcWriteLeveling(PI) end<-----
4394 13:31:09.722361
4395 13:31:09.722614 ==
4396 13:31:09.725646 Dram Type= 6, Freq= 0, CH_1, rank 1
4397 13:31:09.728735 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4398 13:31:09.729241 ==
4399 13:31:09.732006 [Gating] SW mode calibration
4400 13:31:09.738287 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4401 13:31:09.745488 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4402 13:31:09.748168 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4403 13:31:09.755039 0 5 4 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
4404 13:31:09.758516 0 5 8 | B1->B0 | 2f2f 2727 | 0 0 | (1 1) (0 0)
4405 13:31:09.761659 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4406 13:31:09.768187 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4407 13:31:09.771807 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4408 13:31:09.775280 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4409 13:31:09.781734 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4410 13:31:09.785217 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4411 13:31:09.788046 0 6 4 | B1->B0 | 2323 3030 | 1 0 | (0 0) (0 0)
4412 13:31:09.794761 0 6 8 | B1->B0 | 3737 4646 | 0 0 | (1 1) (0 0)
4413 13:31:09.798289 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4414 13:31:09.801385 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4415 13:31:09.805417 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4416 13:31:09.811522 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4417 13:31:09.814678 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4418 13:31:09.818018 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 13:31:09.824568 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4420 13:31:09.827948 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4421 13:31:09.831559 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 13:31:09.838111 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 13:31:09.841324 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 13:31:09.845095 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 13:31:09.851457 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 13:31:09.854342 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 13:31:09.858331 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 13:31:09.864303 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 13:31:09.867749 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 13:31:09.871085 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 13:31:09.878255 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 13:31:09.880983 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 13:31:09.884591 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 13:31:09.890808 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 13:31:09.894389 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4436 13:31:09.898126 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4437 13:31:09.900731 Total UI for P1: 0, mck2ui 16
4438 13:31:09.904449 best dqsien dly found for B0: ( 0, 9, 4)
4439 13:31:09.910818 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 13:31:09.911246 Total UI for P1: 0, mck2ui 16
4441 13:31:09.917468 best dqsien dly found for B1: ( 0, 9, 10)
4442 13:31:09.921411 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4443 13:31:09.924602 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4444 13:31:09.925099
4445 13:31:09.927444 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4446 13:31:09.930937 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4447 13:31:09.934165 [Gating] SW calibration Done
4448 13:31:09.934537 ==
4449 13:31:09.937160 Dram Type= 6, Freq= 0, CH_1, rank 1
4450 13:31:09.940248 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4451 13:31:09.940594 ==
4452 13:31:09.943826 RX Vref Scan: 0
4453 13:31:09.944203
4454 13:31:09.944484 RX Vref 0 -> 0, step: 1
4455 13:31:09.944707
4456 13:31:09.947492 RX Delay -230 -> 252, step: 16
4457 13:31:09.954008 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4458 13:31:09.957111 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4459 13:31:09.960156 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4460 13:31:09.964442 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4461 13:31:09.967566 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4462 13:31:09.973789 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4463 13:31:09.977014 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4464 13:31:09.980372 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4465 13:31:09.983795 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4466 13:31:09.990486 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4467 13:31:09.993911 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4468 13:31:09.997644 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4469 13:31:10.000223 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4470 13:31:10.006778 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4471 13:31:10.010052 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4472 13:31:10.013641 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4473 13:31:10.014103 ==
4474 13:31:10.016567 Dram Type= 6, Freq= 0, CH_1, rank 1
4475 13:31:10.019793 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4476 13:31:10.023152 ==
4477 13:31:10.023565 DQS Delay:
4478 13:31:10.023917 DQS0 = 0, DQS1 = 0
4479 13:31:10.026544 DQM Delay:
4480 13:31:10.026862 DQM0 = 42, DQM1 = 34
4481 13:31:10.030116 DQ Delay:
4482 13:31:10.030596 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4483 13:31:10.033128 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4484 13:31:10.036453 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4485 13:31:10.040208 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4486 13:31:10.040736
4487 13:31:10.042911
4488 13:31:10.043255 ==
4489 13:31:10.046474 Dram Type= 6, Freq= 0, CH_1, rank 1
4490 13:31:10.049411 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4491 13:31:10.049797 ==
4492 13:31:10.050121
4493 13:31:10.050396
4494 13:31:10.052798 TX Vref Scan disable
4495 13:31:10.053165 == TX Byte 0 ==
4496 13:31:10.059633 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4497 13:31:10.062629 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4498 13:31:10.062926 == TX Byte 1 ==
4499 13:31:10.069658 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4500 13:31:10.072971 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4501 13:31:10.073397 ==
4502 13:31:10.076193 Dram Type= 6, Freq= 0, CH_1, rank 1
4503 13:31:10.079286 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4504 13:31:10.079569 ==
4505 13:31:10.079846
4506 13:31:10.080110
4507 13:31:10.083183 TX Vref Scan disable
4508 13:31:10.086516 == TX Byte 0 ==
4509 13:31:10.089858 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4510 13:31:10.093121 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4511 13:31:10.095738 == TX Byte 1 ==
4512 13:31:10.099913 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4513 13:31:10.103009 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4514 13:31:10.106049
4515 13:31:10.106412 [DATLAT]
4516 13:31:10.106789 Freq=600, CH1 RK1
4517 13:31:10.107105
4518 13:31:10.109480 DATLAT Default: 0x8
4519 13:31:10.109865 0, 0xFFFF, sum = 0
4520 13:31:10.112458 1, 0xFFFF, sum = 0
4521 13:31:10.112862 2, 0xFFFF, sum = 0
4522 13:31:10.115990 3, 0xFFFF, sum = 0
4523 13:31:10.119071 4, 0xFFFF, sum = 0
4524 13:31:10.119423 5, 0xFFFF, sum = 0
4525 13:31:10.122385 6, 0xFFFF, sum = 0
4526 13:31:10.122739 7, 0x0, sum = 1
4527 13:31:10.122993 8, 0x0, sum = 2
4528 13:31:10.125854 9, 0x0, sum = 3
4529 13:31:10.126212 10, 0x0, sum = 4
4530 13:31:10.128612 best_step = 8
4531 13:31:10.128960
4532 13:31:10.129208 ==
4533 13:31:10.132031 Dram Type= 6, Freq= 0, CH_1, rank 1
4534 13:31:10.136080 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4535 13:31:10.136592 ==
4536 13:31:10.139126 RX Vref Scan: 0
4537 13:31:10.139559
4538 13:31:10.139847 RX Vref 0 -> 0, step: 1
4539 13:31:10.140069
4540 13:31:10.141894 RX Delay -195 -> 252, step: 8
4541 13:31:10.149409 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4542 13:31:10.152920 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4543 13:31:10.155756 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4544 13:31:10.159355 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4545 13:31:10.166594 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4546 13:31:10.169880 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4547 13:31:10.173049 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4548 13:31:10.176164 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4549 13:31:10.179929 iDelay=205, Bit 8, Center 16 (-139 ~ 172) 312
4550 13:31:10.186503 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4551 13:31:10.189546 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4552 13:31:10.192699 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4553 13:31:10.195894 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4554 13:31:10.202737 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4555 13:31:10.206182 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4556 13:31:10.209066 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4557 13:31:10.209425 ==
4558 13:31:10.212205 Dram Type= 6, Freq= 0, CH_1, rank 1
4559 13:31:10.218869 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4560 13:31:10.219274 ==
4561 13:31:10.219522 DQS Delay:
4562 13:31:10.219742 DQS0 = 0, DQS1 = 0
4563 13:31:10.222478 DQM Delay:
4564 13:31:10.222911 DQM0 = 37, DQM1 = 30
4565 13:31:10.226028 DQ Delay:
4566 13:31:10.228810 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4567 13:31:10.231998 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4568 13:31:10.235569 DQ8 =16, DQ9 =20, DQ10 =28, DQ11 =20
4569 13:31:10.238848 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4570 13:31:10.239201
4571 13:31:10.239511
4572 13:31:10.245379 [DQSOSCAuto] RK1, (LSB)MR18= 0x6060, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4573 13:31:10.248843 CH1 RK1: MR19=808, MR18=6060
4574 13:31:10.255654 CH1_RK1: MR19=0x808, MR18=0x6060, DQSOSC=391, MR23=63, INC=171, DEC=114
4575 13:31:10.258759 [RxdqsGatingPostProcess] freq 600
4576 13:31:10.262148 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4577 13:31:10.265439 Pre-setting of DQS Precalculation
4578 13:31:10.271992 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4579 13:31:10.278466 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4580 13:31:10.285610 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4581 13:31:10.286070
4582 13:31:10.286335
4583 13:31:10.288270 [Calibration Summary] 1200 Mbps
4584 13:31:10.288639 CH 0, Rank 0
4585 13:31:10.291725 SW Impedance : PASS
4586 13:31:10.294825 DUTY Scan : NO K
4587 13:31:10.295194 ZQ Calibration : PASS
4588 13:31:10.298246 Jitter Meter : NO K
4589 13:31:10.301811 CBT Training : PASS
4590 13:31:10.302266 Write leveling : PASS
4591 13:31:10.304954 RX DQS gating : PASS
4592 13:31:10.308445 RX DQ/DQS(RDDQC) : PASS
4593 13:31:10.308911 TX DQ/DQS : PASS
4594 13:31:10.311942 RX DATLAT : PASS
4595 13:31:10.314879 RX DQ/DQS(Engine): PASS
4596 13:31:10.315334 TX OE : NO K
4597 13:31:10.318226 All Pass.
4598 13:31:10.318659
4599 13:31:10.318918 CH 0, Rank 1
4600 13:31:10.321810 SW Impedance : PASS
4601 13:31:10.322244 DUTY Scan : NO K
4602 13:31:10.324541 ZQ Calibration : PASS
4603 13:31:10.327952 Jitter Meter : NO K
4604 13:31:10.328404 CBT Training : PASS
4605 13:31:10.331752 Write leveling : PASS
4606 13:31:10.332158 RX DQS gating : PASS
4607 13:31:10.334514 RX DQ/DQS(RDDQC) : PASS
4608 13:31:10.337923 TX DQ/DQS : PASS
4609 13:31:10.338267 RX DATLAT : PASS
4610 13:31:10.341221 RX DQ/DQS(Engine): PASS
4611 13:31:10.344711 TX OE : NO K
4612 13:31:10.345059 All Pass.
4613 13:31:10.345306
4614 13:31:10.345520 CH 1, Rank 0
4615 13:31:10.348269 SW Impedance : PASS
4616 13:31:10.351118 DUTY Scan : NO K
4617 13:31:10.351464 ZQ Calibration : PASS
4618 13:31:10.354754 Jitter Meter : NO K
4619 13:31:10.358209 CBT Training : PASS
4620 13:31:10.358677 Write leveling : PASS
4621 13:31:10.361344 RX DQS gating : PASS
4622 13:31:10.364667 RX DQ/DQS(RDDQC) : PASS
4623 13:31:10.365159 TX DQ/DQS : PASS
4624 13:31:10.367959 RX DATLAT : PASS
4625 13:31:10.371093 RX DQ/DQS(Engine): PASS
4626 13:31:10.371558 TX OE : NO K
4627 13:31:10.374664 All Pass.
4628 13:31:10.375099
4629 13:31:10.375347 CH 1, Rank 1
4630 13:31:10.377478 SW Impedance : PASS
4631 13:31:10.377824 DUTY Scan : NO K
4632 13:31:10.381307 ZQ Calibration : PASS
4633 13:31:10.384770 Jitter Meter : NO K
4634 13:31:10.385214 CBT Training : PASS
4635 13:31:10.387980 Write leveling : PASS
4636 13:31:10.388429 RX DQS gating : PASS
4637 13:31:10.391376 RX DQ/DQS(RDDQC) : PASS
4638 13:31:10.394726 TX DQ/DQS : PASS
4639 13:31:10.395188 RX DATLAT : PASS
4640 13:31:10.397837 RX DQ/DQS(Engine): PASS
4641 13:31:10.401067 TX OE : NO K
4642 13:31:10.401417 All Pass.
4643 13:31:10.401656
4644 13:31:10.404424 DramC Write-DBI off
4645 13:31:10.404769 PER_BANK_REFRESH: Hybrid Mode
4646 13:31:10.407731 TX_TRACKING: ON
4647 13:31:10.417881 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4648 13:31:10.421195 [FAST_K] Save calibration result to emmc
4649 13:31:10.424146 dramc_set_vcore_voltage set vcore to 662500
4650 13:31:10.424682 Read voltage for 933, 3
4651 13:31:10.427873 Vio18 = 0
4652 13:31:10.428320 Vcore = 662500
4653 13:31:10.428597 Vdram = 0
4654 13:31:10.431263 Vddq = 0
4655 13:31:10.431732 Vmddr = 0
4656 13:31:10.434039 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4657 13:31:10.441017 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4658 13:31:10.444355 MEM_TYPE=3, freq_sel=17
4659 13:31:10.447230 sv_algorithm_assistance_LP4_1600
4660 13:31:10.450641 ============ PULL DRAM RESETB DOWN ============
4661 13:31:10.454448 ========== PULL DRAM RESETB DOWN end =========
4662 13:31:10.460756 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4663 13:31:10.464028 ===================================
4664 13:31:10.464461 LPDDR4 DRAM CONFIGURATION
4665 13:31:10.467052 ===================================
4666 13:31:10.470550 EX_ROW_EN[0] = 0x0
4667 13:31:10.471051 EX_ROW_EN[1] = 0x0
4668 13:31:10.474080 LP4Y_EN = 0x0
4669 13:31:10.477308 WORK_FSP = 0x0
4670 13:31:10.477724 WL = 0x3
4671 13:31:10.480504 RL = 0x3
4672 13:31:10.480882 BL = 0x2
4673 13:31:10.483800 RPST = 0x0
4674 13:31:10.484178 RD_PRE = 0x0
4675 13:31:10.487518 WR_PRE = 0x1
4676 13:31:10.487861 WR_PST = 0x0
4677 13:31:10.490650 DBI_WR = 0x0
4678 13:31:10.491065 DBI_RD = 0x0
4679 13:31:10.493653 OTF = 0x1
4680 13:31:10.497108 ===================================
4681 13:31:10.500735 ===================================
4682 13:31:10.501177 ANA top config
4683 13:31:10.503592 ===================================
4684 13:31:10.506883 DLL_ASYNC_EN = 0
4685 13:31:10.510619 ALL_SLAVE_EN = 1
4686 13:31:10.510964 NEW_RANK_MODE = 1
4687 13:31:10.513740 DLL_IDLE_MODE = 1
4688 13:31:10.516853 LP45_APHY_COMB_EN = 1
4689 13:31:10.520083 TX_ODT_DIS = 1
4690 13:31:10.523728 NEW_8X_MODE = 1
4691 13:31:10.527406 ===================================
4692 13:31:10.530266 ===================================
4693 13:31:10.530617 data_rate = 1866
4694 13:31:10.533402 CKR = 1
4695 13:31:10.536466 DQ_P2S_RATIO = 8
4696 13:31:10.540497 ===================================
4697 13:31:10.543214 CA_P2S_RATIO = 8
4698 13:31:10.546544 DQ_CA_OPEN = 0
4699 13:31:10.549772 DQ_SEMI_OPEN = 0
4700 13:31:10.550125 CA_SEMI_OPEN = 0
4701 13:31:10.553253 CA_FULL_RATE = 0
4702 13:31:10.556926 DQ_CKDIV4_EN = 1
4703 13:31:10.559695 CA_CKDIV4_EN = 1
4704 13:31:10.563368 CA_PREDIV_EN = 0
4705 13:31:10.566859 PH8_DLY = 0
4706 13:31:10.567214 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4707 13:31:10.570087 DQ_AAMCK_DIV = 4
4708 13:31:10.573412 CA_AAMCK_DIV = 4
4709 13:31:10.576156 CA_ADMCK_DIV = 4
4710 13:31:10.579991 DQ_TRACK_CA_EN = 0
4711 13:31:10.583269 CA_PICK = 933
4712 13:31:10.586572 CA_MCKIO = 933
4713 13:31:10.587015 MCKIO_SEMI = 0
4714 13:31:10.589689 PLL_FREQ = 3732
4715 13:31:10.593201 DQ_UI_PI_RATIO = 32
4716 13:31:10.596362 CA_UI_PI_RATIO = 0
4717 13:31:10.599695 ===================================
4718 13:31:10.602828 ===================================
4719 13:31:10.606467 memory_type:LPDDR4
4720 13:31:10.606858 GP_NUM : 10
4721 13:31:10.609237 SRAM_EN : 1
4722 13:31:10.612926 MD32_EN : 0
4723 13:31:10.616556 ===================================
4724 13:31:10.616901 [ANA_INIT] >>>>>>>>>>>>>>
4725 13:31:10.619564 <<<<<< [CONFIGURE PHASE]: ANA_TX
4726 13:31:10.622894 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4727 13:31:10.626149 ===================================
4728 13:31:10.630103 data_rate = 1866,PCW = 0X8f00
4729 13:31:10.633008 ===================================
4730 13:31:10.635737 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4731 13:31:10.642638 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4732 13:31:10.645660 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4733 13:31:10.652377 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4734 13:31:10.655757 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4735 13:31:10.659252 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4736 13:31:10.662444 [ANA_INIT] flow start
4737 13:31:10.662794 [ANA_INIT] PLL >>>>>>>>
4738 13:31:10.665859 [ANA_INIT] PLL <<<<<<<<
4739 13:31:10.668955 [ANA_INIT] MIDPI >>>>>>>>
4740 13:31:10.669317 [ANA_INIT] MIDPI <<<<<<<<
4741 13:31:10.671967 [ANA_INIT] DLL >>>>>>>>
4742 13:31:10.676033 [ANA_INIT] flow end
4743 13:31:10.679134 ============ LP4 DIFF to SE enter ============
4744 13:31:10.682721 ============ LP4 DIFF to SE exit ============
4745 13:31:10.685633 [ANA_INIT] <<<<<<<<<<<<<
4746 13:31:10.689248 [Flow] Enable top DCM control >>>>>
4747 13:31:10.692067 [Flow] Enable top DCM control <<<<<
4748 13:31:10.695526 Enable DLL master slave shuffle
4749 13:31:10.698650 ==============================================================
4750 13:31:10.701968 Gating Mode config
4751 13:31:10.708407 ==============================================================
4752 13:31:10.708846 Config description:
4753 13:31:10.719207 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4754 13:31:10.725343 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4755 13:31:10.728960 SELPH_MODE 0: By rank 1: By Phase
4756 13:31:10.735717 ==============================================================
4757 13:31:10.738365 GAT_TRACK_EN = 1
4758 13:31:10.742005 RX_GATING_MODE = 2
4759 13:31:10.745183 RX_GATING_TRACK_MODE = 2
4760 13:31:10.747943 SELPH_MODE = 1
4761 13:31:10.751335 PICG_EARLY_EN = 1
4762 13:31:10.755159 VALID_LAT_VALUE = 1
4763 13:31:10.758025 ==============================================================
4764 13:31:10.761915 Enter into Gating configuration >>>>
4765 13:31:10.765097 Exit from Gating configuration <<<<
4766 13:31:10.768336 Enter into DVFS_PRE_config >>>>>
4767 13:31:10.781594 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4768 13:31:10.782055 Exit from DVFS_PRE_config <<<<<
4769 13:31:10.784869 Enter into PICG configuration >>>>
4770 13:31:10.788391 Exit from PICG configuration <<<<
4771 13:31:10.791724 [RX_INPUT] configuration >>>>>
4772 13:31:10.795311 [RX_INPUT] configuration <<<<<
4773 13:31:10.801323 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4774 13:31:10.805003 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4775 13:31:10.811264 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4776 13:31:10.818283 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4777 13:31:10.824607 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4778 13:31:10.831627 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4779 13:31:10.834721 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4780 13:31:10.837642 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4781 13:31:10.841933 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4782 13:31:10.847780 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4783 13:31:10.850973 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4784 13:31:10.854345 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4785 13:31:10.857816 ===================================
4786 13:31:10.861222 LPDDR4 DRAM CONFIGURATION
4787 13:31:10.864615 ===================================
4788 13:31:10.864960 EX_ROW_EN[0] = 0x0
4789 13:31:10.868016 EX_ROW_EN[1] = 0x0
4790 13:31:10.871309 LP4Y_EN = 0x0
4791 13:31:10.871657 WORK_FSP = 0x0
4792 13:31:10.874587 WL = 0x3
4793 13:31:10.874929 RL = 0x3
4794 13:31:10.877902 BL = 0x2
4795 13:31:10.878307 RPST = 0x0
4796 13:31:10.880900 RD_PRE = 0x0
4797 13:31:10.881246 WR_PRE = 0x1
4798 13:31:10.884544 WR_PST = 0x0
4799 13:31:10.884886 DBI_WR = 0x0
4800 13:31:10.887488 DBI_RD = 0x0
4801 13:31:10.887757 OTF = 0x1
4802 13:31:10.891400 ===================================
4803 13:31:10.894637 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4804 13:31:10.901102 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4805 13:31:10.904164 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4806 13:31:10.907893 ===================================
4807 13:31:10.910742 LPDDR4 DRAM CONFIGURATION
4808 13:31:10.914587 ===================================
4809 13:31:10.915005 EX_ROW_EN[0] = 0x10
4810 13:31:10.917410 EX_ROW_EN[1] = 0x0
4811 13:31:10.920940 LP4Y_EN = 0x0
4812 13:31:10.921285 WORK_FSP = 0x0
4813 13:31:10.924037 WL = 0x3
4814 13:31:10.924517 RL = 0x3
4815 13:31:10.927531 BL = 0x2
4816 13:31:10.927873 RPST = 0x0
4817 13:31:10.931142 RD_PRE = 0x0
4818 13:31:10.931588 WR_PRE = 0x1
4819 13:31:10.934090 WR_PST = 0x0
4820 13:31:10.934463 DBI_WR = 0x0
4821 13:31:10.936868 DBI_RD = 0x0
4822 13:31:10.937215 OTF = 0x1
4823 13:31:10.941147 ===================================
4824 13:31:10.947233 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4825 13:31:10.951420 nWR fixed to 30
4826 13:31:10.954865 [ModeRegInit_LP4] CH0 RK0
4827 13:31:10.955314 [ModeRegInit_LP4] CH0 RK1
4828 13:31:10.958192 [ModeRegInit_LP4] CH1 RK0
4829 13:31:10.961641 [ModeRegInit_LP4] CH1 RK1
4830 13:31:10.961985 match AC timing 8
4831 13:31:10.967836 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4832 13:31:10.971432 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4833 13:31:10.975080 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4834 13:31:10.981690 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4835 13:31:10.984680 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4836 13:31:10.985027 ==
4837 13:31:10.988083 Dram Type= 6, Freq= 0, CH_0, rank 0
4838 13:31:10.991469 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4839 13:31:10.991962 ==
4840 13:31:10.997954 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4841 13:31:11.004836 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4842 13:31:11.008368 [CA 0] Center 39 (8~70) winsize 63
4843 13:31:11.011539 [CA 1] Center 39 (8~70) winsize 63
4844 13:31:11.014618 [CA 2] Center 36 (6~67) winsize 62
4845 13:31:11.017776 [CA 3] Center 36 (6~67) winsize 62
4846 13:31:11.021005 [CA 4] Center 34 (4~65) winsize 62
4847 13:31:11.024420 [CA 5] Center 34 (4~65) winsize 62
4848 13:31:11.024850
4849 13:31:11.027840 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4850 13:31:11.028350
4851 13:31:11.031207 [CATrainingPosCal] consider 1 rank data
4852 13:31:11.034270 u2DelayCellTimex100 = 270/100 ps
4853 13:31:11.037641 CA0 delay=39 (8~70),Diff = 5 PI (31 cell)
4854 13:31:11.041146 CA1 delay=39 (8~70),Diff = 5 PI (31 cell)
4855 13:31:11.044131 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4856 13:31:11.047472 CA3 delay=36 (6~67),Diff = 2 PI (12 cell)
4857 13:31:11.054342 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4858 13:31:11.057530 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4859 13:31:11.057876
4860 13:31:11.060797 CA PerBit enable=1, Macro0, CA PI delay=34
4861 13:31:11.061149
4862 13:31:11.063962 [CBTSetCACLKResult] CA Dly = 34
4863 13:31:11.064337 CS Dly: 7 (0~38)
4864 13:31:11.064589 ==
4865 13:31:11.067267 Dram Type= 6, Freq= 0, CH_0, rank 1
4866 13:31:11.070625 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4867 13:31:11.074304 ==
4868 13:31:11.077822 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4869 13:31:11.083729 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4870 13:31:11.087557 [CA 0] Center 38 (8~69) winsize 62
4871 13:31:11.090934 [CA 1] Center 38 (8~69) winsize 62
4872 13:31:11.094384 [CA 2] Center 36 (5~67) winsize 63
4873 13:31:11.097449 [CA 3] Center 35 (5~66) winsize 62
4874 13:31:11.100876 [CA 4] Center 34 (4~65) winsize 62
4875 13:31:11.103980 [CA 5] Center 34 (4~65) winsize 62
4876 13:31:11.104479
4877 13:31:11.107477 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4878 13:31:11.107916
4879 13:31:11.110834 [CATrainingPosCal] consider 2 rank data
4880 13:31:11.113874 u2DelayCellTimex100 = 270/100 ps
4881 13:31:11.116940 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4882 13:31:11.120154 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4883 13:31:11.123713 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4884 13:31:11.131080 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4885 13:31:11.133803 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4886 13:31:11.136871 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4887 13:31:11.137244
4888 13:31:11.140034 CA PerBit enable=1, Macro0, CA PI delay=34
4889 13:31:11.140446
4890 13:31:11.143851 [CBTSetCACLKResult] CA Dly = 34
4891 13:31:11.144412 CS Dly: 7 (0~39)
4892 13:31:11.144717
4893 13:31:11.146715 ----->DramcWriteLeveling(PI) begin...
4894 13:31:11.150339 ==
4895 13:31:11.153612 Dram Type= 6, Freq= 0, CH_0, rank 0
4896 13:31:11.156800 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4897 13:31:11.157170 ==
4898 13:31:11.159665 Write leveling (Byte 0): 29 => 29
4899 13:31:11.163595 Write leveling (Byte 1): 29 => 29
4900 13:31:11.166588 DramcWriteLeveling(PI) end<-----
4901 13:31:11.166958
4902 13:31:11.167255 ==
4903 13:31:11.170043 Dram Type= 6, Freq= 0, CH_0, rank 0
4904 13:31:11.173129 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4905 13:31:11.173541 ==
4906 13:31:11.176945 [Gating] SW mode calibration
4907 13:31:11.183026 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4908 13:31:11.190637 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4909 13:31:11.193422 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4910 13:31:11.196383 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4911 13:31:11.199739 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4912 13:31:11.206767 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4913 13:31:11.209751 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4914 13:31:11.213184 0 10 20 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
4915 13:31:11.219871 0 10 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
4916 13:31:11.222874 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4917 13:31:11.226662 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4918 13:31:11.232914 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4919 13:31:11.236259 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4920 13:31:11.239222 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4921 13:31:11.246031 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4922 13:31:11.249274 0 11 20 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
4923 13:31:11.252344 0 11 24 | B1->B0 | 3a3a 4141 | 0 0 | (0 0) (0 0)
4924 13:31:11.259306 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4925 13:31:11.262868 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4926 13:31:11.265805 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4927 13:31:11.272829 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4928 13:31:11.276019 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4929 13:31:11.279293 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4930 13:31:11.285970 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4931 13:31:11.289096 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4932 13:31:11.292154 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4933 13:31:11.298880 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4934 13:31:11.302111 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4935 13:31:11.305485 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4936 13:31:11.311829 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4937 13:31:11.315864 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4938 13:31:11.318629 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4939 13:31:11.325595 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4940 13:31:11.328737 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4941 13:31:11.332138 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4942 13:31:11.338356 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4943 13:31:11.341959 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4944 13:31:11.344664 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4945 13:31:11.351724 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4946 13:31:11.354970 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4947 13:31:11.358422 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4948 13:31:11.364706 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4949 13:31:11.368183 Total UI for P1: 0, mck2ui 16
4950 13:31:11.371833 best dqsien dly found for B0: ( 0, 14, 22)
4951 13:31:11.375027 Total UI for P1: 0, mck2ui 16
4952 13:31:11.378297 best dqsien dly found for B1: ( 0, 14, 22)
4953 13:31:11.381528 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
4954 13:31:11.384897 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
4955 13:31:11.385243
4956 13:31:11.388118 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
4957 13:31:11.391547 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
4958 13:31:11.395192 [Gating] SW calibration Done
4959 13:31:11.395665 ==
4960 13:31:11.398485 Dram Type= 6, Freq= 0, CH_0, rank 0
4961 13:31:11.401691 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4962 13:31:11.402191 ==
4963 13:31:11.404899 RX Vref Scan: 0
4964 13:31:11.405277
4965 13:31:11.408190 RX Vref 0 -> 0, step: 1
4966 13:31:11.408726
4967 13:31:11.408997 RX Delay -80 -> 252, step: 8
4968 13:31:11.414333 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
4969 13:31:11.418099 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
4970 13:31:11.421148 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
4971 13:31:11.424785 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
4972 13:31:11.427855 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
4973 13:31:11.431443 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
4974 13:31:11.437615 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
4975 13:31:11.440881 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
4976 13:31:11.444754 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
4977 13:31:11.447757 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
4978 13:31:11.450798 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
4979 13:31:11.454430 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
4980 13:31:11.460912 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
4981 13:31:11.464803 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
4982 13:31:11.468060 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
4983 13:31:11.470686 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
4984 13:31:11.471095 ==
4985 13:31:11.474054 Dram Type= 6, Freq= 0, CH_0, rank 0
4986 13:31:11.477489 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4987 13:31:11.480616 ==
4988 13:31:11.481010 DQS Delay:
4989 13:31:11.481280 DQS0 = 0, DQS1 = 0
4990 13:31:11.484722 DQM Delay:
4991 13:31:11.485188 DQM0 = 96, DQM1 = 87
4992 13:31:11.487586 DQ Delay:
4993 13:31:11.490560 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =95
4994 13:31:11.490939 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
4995 13:31:11.494301 DQ8 =75, DQ9 =71, DQ10 =91, DQ11 =79
4996 13:31:11.500302 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
4997 13:31:11.500792
4998 13:31:11.501067
4999 13:31:11.501304 ==
5000 13:31:11.503985 Dram Type= 6, Freq= 0, CH_0, rank 0
5001 13:31:11.507640 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5002 13:31:11.508130 ==
5003 13:31:11.508442
5004 13:31:11.508684
5005 13:31:11.510896 TX Vref Scan disable
5006 13:31:11.511291 == TX Byte 0 ==
5007 13:31:11.517310 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5008 13:31:11.520356 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5009 13:31:11.520702 == TX Byte 1 ==
5010 13:31:11.527150 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5011 13:31:11.530854 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5012 13:31:11.531310 ==
5013 13:31:11.533927 Dram Type= 6, Freq= 0, CH_0, rank 0
5014 13:31:11.536698 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5015 13:31:11.537074 ==
5016 13:31:11.537321
5017 13:31:11.540067
5018 13:31:11.540384 TX Vref Scan disable
5019 13:31:11.543802 == TX Byte 0 ==
5020 13:31:11.546916 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5021 13:31:11.550145 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5022 13:31:11.553344 == TX Byte 1 ==
5023 13:31:11.556634 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5024 13:31:11.560115 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5025 13:31:11.563254
5026 13:31:11.563768 [DATLAT]
5027 13:31:11.564087 Freq=933, CH0 RK0
5028 13:31:11.564353
5029 13:31:11.566522 DATLAT Default: 0xd
5030 13:31:11.566873 0, 0xFFFF, sum = 0
5031 13:31:11.569660 1, 0xFFFF, sum = 0
5032 13:31:11.570011 2, 0xFFFF, sum = 0
5033 13:31:11.573244 3, 0xFFFF, sum = 0
5034 13:31:11.573612 4, 0xFFFF, sum = 0
5035 13:31:11.576421 5, 0xFFFF, sum = 0
5036 13:31:11.579894 6, 0xFFFF, sum = 0
5037 13:31:11.580471 7, 0xFFFF, sum = 0
5038 13:31:11.583300 8, 0xFFFF, sum = 0
5039 13:31:11.583679 9, 0xFFFF, sum = 0
5040 13:31:11.586868 10, 0x0, sum = 1
5041 13:31:11.587326 11, 0x0, sum = 2
5042 13:31:11.587584 12, 0x0, sum = 3
5043 13:31:11.589931 13, 0x0, sum = 4
5044 13:31:11.590282 best_step = 11
5045 13:31:11.590525
5046 13:31:11.593370 ==
5047 13:31:11.593715 Dram Type= 6, Freq= 0, CH_0, rank 0
5048 13:31:11.599854 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5049 13:31:11.600356 ==
5050 13:31:11.600645 RX Vref Scan: 1
5051 13:31:11.600867
5052 13:31:11.602907 RX Vref 0 -> 0, step: 1
5053 13:31:11.603258
5054 13:31:11.606745 RX Delay -69 -> 252, step: 4
5055 13:31:11.607157
5056 13:31:11.609650 Set Vref, RX VrefLevel [Byte0]: 47
5057 13:31:11.612915 [Byte1]: 49
5058 13:31:11.613260
5059 13:31:11.616046 Final RX Vref Byte 0 = 47 to rank0
5060 13:31:11.619996 Final RX Vref Byte 1 = 49 to rank0
5061 13:31:11.622722 Final RX Vref Byte 0 = 47 to rank1
5062 13:31:11.626465 Final RX Vref Byte 1 = 49 to rank1==
5063 13:31:11.629553 Dram Type= 6, Freq= 0, CH_0, rank 0
5064 13:31:11.633143 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5065 13:31:11.636009 ==
5066 13:31:11.636388 DQS Delay:
5067 13:31:11.636641 DQS0 = 0, DQS1 = 0
5068 13:31:11.639139 DQM Delay:
5069 13:31:11.639483 DQM0 = 96, DQM1 = 86
5070 13:31:11.643173 DQ Delay:
5071 13:31:11.643651 DQ0 =92, DQ1 =98, DQ2 =94, DQ3 =94
5072 13:31:11.649645 DQ4 =102, DQ5 =86, DQ6 =104, DQ7 =104
5073 13:31:11.650017 DQ8 =76, DQ9 =70, DQ10 =86, DQ11 =78
5074 13:31:11.656087 DQ12 =94, DQ13 =94, DQ14 =98, DQ15 =94
5075 13:31:11.656626
5076 13:31:11.657004
5077 13:31:11.662618 [DQSOSCAuto] RK0, (LSB)MR18= 0x2222, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5078 13:31:11.666110 CH0 RK0: MR19=505, MR18=2222
5079 13:31:11.672251 CH0_RK0: MR19=0x505, MR18=0x2222, DQSOSC=411, MR23=63, INC=64, DEC=42
5080 13:31:11.672637
5081 13:31:11.676057 ----->DramcWriteLeveling(PI) begin...
5082 13:31:11.676428 ==
5083 13:31:11.679057 Dram Type= 6, Freq= 0, CH_0, rank 1
5084 13:31:11.682707 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5085 13:31:11.683174 ==
5086 13:31:11.686005 Write leveling (Byte 0): 28 => 28
5087 13:31:11.689269 Write leveling (Byte 1): 27 => 27
5088 13:31:11.692141 DramcWriteLeveling(PI) end<-----
5089 13:31:11.692566
5090 13:31:11.692816 ==
5091 13:31:11.695776 Dram Type= 6, Freq= 0, CH_0, rank 1
5092 13:31:11.699009 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5093 13:31:11.699358 ==
5094 13:31:11.702334 [Gating] SW mode calibration
5095 13:31:11.709338 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5096 13:31:11.715691 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5097 13:31:11.718660 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5098 13:31:11.725665 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5099 13:31:11.728971 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5100 13:31:11.732356 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5101 13:31:11.738609 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5102 13:31:11.742270 0 10 20 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
5103 13:31:11.745294 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
5104 13:31:11.751754 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5105 13:31:11.755413 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5106 13:31:11.758689 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5107 13:31:11.765104 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5108 13:31:11.768555 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5109 13:31:11.771416 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5110 13:31:11.774947 0 11 20 | B1->B0 | 2a2a 3131 | 0 0 | (0 0) (0 0)
5111 13:31:11.782246 0 11 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5112 13:31:11.785021 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5113 13:31:11.788322 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5114 13:31:11.795243 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5115 13:31:11.798556 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5116 13:31:11.801847 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5117 13:31:11.808186 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5118 13:31:11.811756 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5119 13:31:11.814711 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 13:31:11.822250 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 13:31:11.824630 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 13:31:11.828343 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 13:31:11.834408 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 13:31:11.838474 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 13:31:11.841689 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 13:31:11.847557 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 13:31:11.851466 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 13:31:11.854858 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 13:31:11.861313 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 13:31:11.864809 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 13:31:11.867836 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 13:31:11.873866 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 13:31:11.877708 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 13:31:11.880755 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5135 13:31:11.887993 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5136 13:31:11.888580 Total UI for P1: 0, mck2ui 16
5137 13:31:11.894989 best dqsien dly found for B0: ( 0, 14, 20)
5138 13:31:11.897715 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 13:31:11.901290 Total UI for P1: 0, mck2ui 16
5140 13:31:11.905119 best dqsien dly found for B1: ( 0, 14, 22)
5141 13:31:11.907638 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5142 13:31:11.911401 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5143 13:31:11.911904
5144 13:31:11.914360 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5145 13:31:11.917265 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5146 13:31:11.921260 [Gating] SW calibration Done
5147 13:31:11.921716 ==
5148 13:31:11.924193 Dram Type= 6, Freq= 0, CH_0, rank 1
5149 13:31:11.930769 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5150 13:31:11.931119 ==
5151 13:31:11.931364 RX Vref Scan: 0
5152 13:31:11.931583
5153 13:31:11.934301 RX Vref 0 -> 0, step: 1
5154 13:31:11.934647
5155 13:31:11.937819 RX Delay -80 -> 252, step: 8
5156 13:31:11.940251 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5157 13:31:11.944224 iDelay=208, Bit 1, Center 95 (-8 ~ 199) 208
5158 13:31:11.947459 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5159 13:31:11.950619 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192
5160 13:31:11.957246 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5161 13:31:11.959890 iDelay=208, Bit 5, Center 91 (-8 ~ 191) 200
5162 13:31:11.963634 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5163 13:31:11.967309 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5164 13:31:11.970164 iDelay=208, Bit 8, Center 79 (-8 ~ 167) 176
5165 13:31:11.973330 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5166 13:31:11.980156 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5167 13:31:11.983225 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5168 13:31:11.986927 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5169 13:31:11.989923 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5170 13:31:11.993177 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5171 13:31:11.999615 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5172 13:31:11.999977 ==
5173 13:31:12.003684 Dram Type= 6, Freq= 0, CH_0, rank 1
5174 13:31:12.006518 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5175 13:31:12.006888 ==
5176 13:31:12.007142 DQS Delay:
5177 13:31:12.009965 DQS0 = 0, DQS1 = 0
5178 13:31:12.010437 DQM Delay:
5179 13:31:12.013037 DQM0 = 96, DQM1 = 87
5180 13:31:12.013385 DQ Delay:
5181 13:31:12.016753 DQ0 =91, DQ1 =95, DQ2 =95, DQ3 =87
5182 13:31:12.019971 DQ4 =99, DQ5 =91, DQ6 =103, DQ7 =107
5183 13:31:12.023413 DQ8 =79, DQ9 =67, DQ10 =87, DQ11 =83
5184 13:31:12.026315 DQ12 =99, DQ13 =91, DQ14 =91, DQ15 =99
5185 13:31:12.026710
5186 13:31:12.026976
5187 13:31:12.027211 ==
5188 13:31:12.029766 Dram Type= 6, Freq= 0, CH_0, rank 1
5189 13:31:12.033109 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5190 13:31:12.033580 ==
5191 13:31:12.036151
5192 13:31:12.036555
5193 13:31:12.036823 TX Vref Scan disable
5194 13:31:12.039487 == TX Byte 0 ==
5195 13:31:12.042835 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5196 13:31:12.046042 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5197 13:31:12.049372 == TX Byte 1 ==
5198 13:31:12.052647 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5199 13:31:12.056090 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5200 13:31:12.056476 ==
5201 13:31:12.059254 Dram Type= 6, Freq= 0, CH_0, rank 1
5202 13:31:12.066192 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5203 13:31:12.066546 ==
5204 13:31:12.066787
5205 13:31:12.066999
5206 13:31:12.069566 TX Vref Scan disable
5207 13:31:12.069977 == TX Byte 0 ==
5208 13:31:12.076234 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5209 13:31:12.079422 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5210 13:31:12.079887 == TX Byte 1 ==
5211 13:31:12.085637 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5212 13:31:12.089249 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5213 13:31:12.089705
5214 13:31:12.089963 [DATLAT]
5215 13:31:12.092229 Freq=933, CH0 RK1
5216 13:31:12.092611
5217 13:31:12.092859 DATLAT Default: 0xb
5218 13:31:12.095883 0, 0xFFFF, sum = 0
5219 13:31:12.096373 1, 0xFFFF, sum = 0
5220 13:31:12.099081 2, 0xFFFF, sum = 0
5221 13:31:12.099433 3, 0xFFFF, sum = 0
5222 13:31:12.102341 4, 0xFFFF, sum = 0
5223 13:31:12.102693 5, 0xFFFF, sum = 0
5224 13:31:12.106137 6, 0xFFFF, sum = 0
5225 13:31:12.106609 7, 0xFFFF, sum = 0
5226 13:31:12.109249 8, 0xFFFF, sum = 0
5227 13:31:12.109606 9, 0xFFFF, sum = 0
5228 13:31:12.112342 10, 0x0, sum = 1
5229 13:31:12.112695 11, 0x0, sum = 2
5230 13:31:12.115679 12, 0x0, sum = 3
5231 13:31:12.116034 13, 0x0, sum = 4
5232 13:31:12.119083 best_step = 11
5233 13:31:12.119429
5234 13:31:12.119675 ==
5235 13:31:12.122547 Dram Type= 6, Freq= 0, CH_0, rank 1
5236 13:31:12.125409 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5237 13:31:12.125782 ==
5238 13:31:12.129069 RX Vref Scan: 0
5239 13:31:12.129543
5240 13:31:12.129815 RX Vref 0 -> 0, step: 1
5241 13:31:12.130035
5242 13:31:12.132245 RX Delay -77 -> 252, step: 4
5243 13:31:12.139740 iDelay=199, Bit 0, Center 94 (3 ~ 186) 184
5244 13:31:12.142786 iDelay=199, Bit 1, Center 98 (3 ~ 194) 192
5245 13:31:12.146096 iDelay=199, Bit 2, Center 96 (3 ~ 190) 188
5246 13:31:12.149187 iDelay=199, Bit 3, Center 92 (3 ~ 182) 180
5247 13:31:12.152546 iDelay=199, Bit 4, Center 102 (11 ~ 194) 184
5248 13:31:12.156193 iDelay=199, Bit 5, Center 88 (-5 ~ 182) 188
5249 13:31:12.162759 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5250 13:31:12.166089 iDelay=199, Bit 7, Center 108 (19 ~ 198) 180
5251 13:31:12.169062 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5252 13:31:12.172886 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5253 13:31:12.175818 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5254 13:31:12.182267 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5255 13:31:12.185536 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5256 13:31:12.188780 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5257 13:31:12.192072 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5258 13:31:12.195634 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5259 13:31:12.195734 ==
5260 13:31:12.198706 Dram Type= 6, Freq= 0, CH_0, rank 1
5261 13:31:12.205241 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5262 13:31:12.205364 ==
5263 13:31:12.205433 DQS Delay:
5264 13:31:12.208686 DQS0 = 0, DQS1 = 0
5265 13:31:12.208802 DQM Delay:
5266 13:31:12.211971 DQM0 = 97, DQM1 = 86
5267 13:31:12.212061 DQ Delay:
5268 13:31:12.215185 DQ0 =94, DQ1 =98, DQ2 =96, DQ3 =92
5269 13:31:12.218428 DQ4 =102, DQ5 =88, DQ6 =104, DQ7 =108
5270 13:31:12.221975 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =78
5271 13:31:12.225208 DQ12 =94, DQ13 =90, DQ14 =98, DQ15 =94
5272 13:31:12.225322
5273 13:31:12.225388
5274 13:31:12.231579 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b2b, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5275 13:31:12.235142 CH0 RK1: MR19=505, MR18=2B2B
5276 13:31:12.242317 CH0_RK1: MR19=0x505, MR18=0x2B2B, DQSOSC=408, MR23=63, INC=65, DEC=43
5277 13:31:12.245193 [RxdqsGatingPostProcess] freq 933
5278 13:31:12.251456 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5279 13:31:12.251556 Pre-setting of DQS Precalculation
5280 13:31:12.258352 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5281 13:31:12.258429 ==
5282 13:31:12.261728 Dram Type= 6, Freq= 0, CH_1, rank 0
5283 13:31:12.264989 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5284 13:31:12.265157 ==
5285 13:31:12.271553 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5286 13:31:12.278295 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5287 13:31:12.281750 [CA 0] Center 37 (7~68) winsize 62
5288 13:31:12.284690 [CA 1] Center 37 (6~68) winsize 63
5289 13:31:12.288718 [CA 2] Center 35 (5~65) winsize 61
5290 13:31:12.291637 [CA 3] Center 34 (4~65) winsize 62
5291 13:31:12.295087 [CA 4] Center 33 (2~64) winsize 63
5292 13:31:12.298220 [CA 5] Center 33 (3~63) winsize 61
5293 13:31:12.298313
5294 13:31:12.301491 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5295 13:31:12.301838
5296 13:31:12.305454 [CATrainingPosCal] consider 1 rank data
5297 13:31:12.308610 u2DelayCellTimex100 = 270/100 ps
5298 13:31:12.311532 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5299 13:31:12.314671 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5300 13:31:12.318012 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5301 13:31:12.321531 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5302 13:31:12.324728 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5303 13:31:12.327822 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5304 13:31:12.331459
5305 13:31:12.334753 CA PerBit enable=1, Macro0, CA PI delay=33
5306 13:31:12.335251
5307 13:31:12.338415 [CBTSetCACLKResult] CA Dly = 33
5308 13:31:12.338761 CS Dly: 5 (0~36)
5309 13:31:12.339005 ==
5310 13:31:12.341506 Dram Type= 6, Freq= 0, CH_1, rank 1
5311 13:31:12.344374 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5312 13:31:12.344463 ==
5313 13:31:12.350995 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5314 13:31:12.357680 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5315 13:31:12.360930 [CA 0] Center 37 (6~68) winsize 63
5316 13:31:12.364146 [CA 1] Center 37 (6~68) winsize 63
5317 13:31:12.367699 [CA 2] Center 34 (4~65) winsize 62
5318 13:31:12.370591 [CA 3] Center 34 (4~65) winsize 62
5319 13:31:12.374084 [CA 4] Center 33 (2~64) winsize 63
5320 13:31:12.377463 [CA 5] Center 33 (2~64) winsize 63
5321 13:31:12.377533
5322 13:31:12.380799 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5323 13:31:12.380874
5324 13:31:12.384598 [CATrainingPosCal] consider 2 rank data
5325 13:31:12.387947 u2DelayCellTimex100 = 270/100 ps
5326 13:31:12.391487 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5327 13:31:12.394608 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5328 13:31:12.397866 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5329 13:31:12.400999 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5330 13:31:12.407509 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5331 13:31:12.410975 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5332 13:31:12.411414
5333 13:31:12.414602 CA PerBit enable=1, Macro0, CA PI delay=33
5334 13:31:12.415078
5335 13:31:12.418170 [CBTSetCACLKResult] CA Dly = 33
5336 13:31:12.418630 CS Dly: 5 (0~37)
5337 13:31:12.418990
5338 13:31:12.421399 ----->DramcWriteLeveling(PI) begin...
5339 13:31:12.421875 ==
5340 13:31:12.424221 Dram Type= 6, Freq= 0, CH_1, rank 0
5341 13:31:12.431026 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5342 13:31:12.431482 ==
5343 13:31:12.434375 Write leveling (Byte 0): 24 => 24
5344 13:31:12.434992 Write leveling (Byte 1): 24 => 24
5345 13:31:12.438234 DramcWriteLeveling(PI) end<-----
5346 13:31:12.438579
5347 13:31:12.440895 ==
5348 13:31:12.441280 Dram Type= 6, Freq= 0, CH_1, rank 0
5349 13:31:12.447251 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5350 13:31:12.447696 ==
5351 13:31:12.450862 [Gating] SW mode calibration
5352 13:31:12.457812 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5353 13:31:12.460907 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5354 13:31:12.468075 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5355 13:31:12.470931 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5356 13:31:12.474480 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5357 13:31:12.480649 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5358 13:31:12.483619 0 10 16 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
5359 13:31:12.487673 0 10 20 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
5360 13:31:12.494164 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5361 13:31:12.497260 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 13:31:12.500381 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5363 13:31:12.507341 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5364 13:31:12.510479 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5365 13:31:12.513717 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5366 13:31:12.520591 0 11 16 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
5367 13:31:12.524095 0 11 20 | B1->B0 | 2929 3f3f | 0 1 | (0 0) (0 0)
5368 13:31:12.527186 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 13:31:12.533701 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 13:31:12.537268 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 13:31:12.540150 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 13:31:12.543918 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 13:31:12.549926 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 13:31:12.553434 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5375 13:31:12.556758 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5376 13:31:12.563683 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 13:31:12.566726 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 13:31:12.570731 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 13:31:12.576562 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 13:31:12.579975 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 13:31:12.583847 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 13:31:12.590352 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 13:31:12.593675 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 13:31:12.597053 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 13:31:12.603428 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 13:31:12.606859 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 13:31:12.609984 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 13:31:12.616684 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 13:31:12.620034 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 13:31:12.623459 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5391 13:31:12.630076 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5392 13:31:12.630428 Total UI for P1: 0, mck2ui 16
5393 13:31:12.636905 best dqsien dly found for B0: ( 0, 14, 16)
5394 13:31:12.640066 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5395 13:31:12.643812 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5396 13:31:12.646708 Total UI for P1: 0, mck2ui 16
5397 13:31:12.649867 best dqsien dly found for B1: ( 0, 14, 22)
5398 13:31:12.653236 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5399 13:31:12.655987 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5400 13:31:12.656335
5401 13:31:12.663269 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5402 13:31:12.666288 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5403 13:31:12.669971 [Gating] SW calibration Done
5404 13:31:12.670360 ==
5405 13:31:12.673214 Dram Type= 6, Freq= 0, CH_1, rank 0
5406 13:31:12.676023 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5407 13:31:12.676405 ==
5408 13:31:12.676658 RX Vref Scan: 0
5409 13:31:12.676876
5410 13:31:12.679855 RX Vref 0 -> 0, step: 1
5411 13:31:12.680200
5412 13:31:12.683315 RX Delay -80 -> 252, step: 8
5413 13:31:12.686838 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5414 13:31:12.690053 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5415 13:31:12.692838 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5416 13:31:12.699875 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5417 13:31:12.703130 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5418 13:31:12.706651 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5419 13:31:12.709772 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5420 13:31:12.713241 iDelay=208, Bit 7, Center 95 (-8 ~ 199) 208
5421 13:31:12.716591 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5422 13:31:12.722692 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5423 13:31:12.725867 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5424 13:31:12.729593 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5425 13:31:12.732728 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5426 13:31:12.736323 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5427 13:31:12.742935 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5428 13:31:12.746486 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5429 13:31:12.746955 ==
5430 13:31:12.749324 Dram Type= 6, Freq= 0, CH_1, rank 0
5431 13:31:12.752219 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5432 13:31:12.752572 ==
5433 13:31:12.755882 DQS Delay:
5434 13:31:12.756230 DQS0 = 0, DQS1 = 0
5435 13:31:12.756515 DQM Delay:
5436 13:31:12.759153 DQM0 = 95, DQM1 = 87
5437 13:31:12.759604 DQ Delay:
5438 13:31:12.762607 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5439 13:31:12.766119 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =95
5440 13:31:12.769855 DQ8 =71, DQ9 =75, DQ10 =91, DQ11 =79
5441 13:31:12.772600 DQ12 =95, DQ13 =99, DQ14 =91, DQ15 =99
5442 13:31:12.773032
5443 13:31:12.773286
5444 13:31:12.773514 ==
5445 13:31:12.775750 Dram Type= 6, Freq= 0, CH_1, rank 0
5446 13:31:12.782503 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5447 13:31:12.782952 ==
5448 13:31:12.783226
5449 13:31:12.783463
5450 13:31:12.783683 TX Vref Scan disable
5451 13:31:12.785947 == TX Byte 0 ==
5452 13:31:12.789547 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5453 13:31:12.795897 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5454 13:31:12.796471 == TX Byte 1 ==
5455 13:31:12.799482 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5456 13:31:12.806023 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5457 13:31:12.806501 ==
5458 13:31:12.808832 Dram Type= 6, Freq= 0, CH_1, rank 0
5459 13:31:12.812091 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5460 13:31:12.812610 ==
5461 13:31:12.812900
5462 13:31:12.813141
5463 13:31:12.816072 TX Vref Scan disable
5464 13:31:12.819006 == TX Byte 0 ==
5465 13:31:12.822092 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5466 13:31:12.825520 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5467 13:31:12.828954 == TX Byte 1 ==
5468 13:31:12.831930 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5469 13:31:12.835723 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5470 13:31:12.836222
5471 13:31:12.836556 [DATLAT]
5472 13:31:12.838599 Freq=933, CH1 RK0
5473 13:31:12.838977
5474 13:31:12.839250 DATLAT Default: 0xd
5475 13:31:12.841632 0, 0xFFFF, sum = 0
5476 13:31:12.845307 1, 0xFFFF, sum = 0
5477 13:31:12.845660 2, 0xFFFF, sum = 0
5478 13:31:12.848801 3, 0xFFFF, sum = 0
5479 13:31:12.849187 4, 0xFFFF, sum = 0
5480 13:31:12.851567 5, 0xFFFF, sum = 0
5481 13:31:12.851972 6, 0xFFFF, sum = 0
5482 13:31:12.855526 7, 0xFFFF, sum = 0
5483 13:31:12.856007 8, 0xFFFF, sum = 0
5484 13:31:12.858534 9, 0xFFFF, sum = 0
5485 13:31:12.858891 10, 0x0, sum = 1
5486 13:31:12.861967 11, 0x0, sum = 2
5487 13:31:12.862338 12, 0x0, sum = 3
5488 13:31:12.865438 13, 0x0, sum = 4
5489 13:31:12.865796 best_step = 11
5490 13:31:12.866119
5491 13:31:12.866401 ==
5492 13:31:12.868841 Dram Type= 6, Freq= 0, CH_1, rank 0
5493 13:31:12.871643 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5494 13:31:12.872092 ==
5495 13:31:12.875169 RX Vref Scan: 1
5496 13:31:12.875601
5497 13:31:12.878288 RX Vref 0 -> 0, step: 1
5498 13:31:12.878639
5499 13:31:12.878957 RX Delay -69 -> 252, step: 4
5500 13:31:12.879247
5501 13:31:12.881725 Set Vref, RX VrefLevel [Byte0]: 53
5502 13:31:12.885200 [Byte1]: 49
5503 13:31:12.889875
5504 13:31:12.890337 Final RX Vref Byte 0 = 53 to rank0
5505 13:31:12.893419 Final RX Vref Byte 1 = 49 to rank0
5506 13:31:12.896635 Final RX Vref Byte 0 = 53 to rank1
5507 13:31:12.899862 Final RX Vref Byte 1 = 49 to rank1==
5508 13:31:12.903612 Dram Type= 6, Freq= 0, CH_1, rank 0
5509 13:31:12.910104 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5510 13:31:12.910557 ==
5511 13:31:12.910911 DQS Delay:
5512 13:31:12.912718 DQS0 = 0, DQS1 = 0
5513 13:31:12.913068 DQM Delay:
5514 13:31:12.913393 DQM0 = 94, DQM1 = 88
5515 13:31:12.916634 DQ Delay:
5516 13:31:12.919852 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =92
5517 13:31:12.923683 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =92
5518 13:31:12.926863 DQ8 =72, DQ9 =76, DQ10 =90, DQ11 =80
5519 13:31:12.930111 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =98
5520 13:31:12.930643
5521 13:31:12.931024
5522 13:31:12.936150 [DQSOSCAuto] RK0, (LSB)MR18= 0x3434, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
5523 13:31:12.939754 CH1 RK0: MR19=505, MR18=3434
5524 13:31:12.946259 CH1_RK0: MR19=0x505, MR18=0x3434, DQSOSC=405, MR23=63, INC=66, DEC=44
5525 13:31:12.946624
5526 13:31:12.949823 ----->DramcWriteLeveling(PI) begin...
5527 13:31:12.950183 ==
5528 13:31:12.952712 Dram Type= 6, Freq= 0, CH_1, rank 1
5529 13:31:12.956441 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5530 13:31:12.956877 ==
5531 13:31:12.959550 Write leveling (Byte 0): 23 => 23
5532 13:31:12.962505 Write leveling (Byte 1): 21 => 21
5533 13:31:12.966436 DramcWriteLeveling(PI) end<-----
5534 13:31:12.966789
5535 13:31:12.967108 ==
5536 13:31:12.969988 Dram Type= 6, Freq= 0, CH_1, rank 1
5537 13:31:12.972844 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5538 13:31:12.973207 ==
5539 13:31:12.975852 [Gating] SW mode calibration
5540 13:31:12.983229 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5541 13:31:12.989584 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5542 13:31:12.992891 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5543 13:31:12.999358 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5544 13:31:13.002717 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5545 13:31:13.005999 0 10 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)
5546 13:31:13.012927 0 10 16 | B1->B0 | 3333 2626 | 1 0 | (1 0) (0 1)
5547 13:31:13.015926 0 10 20 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
5548 13:31:13.019241 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5549 13:31:13.026118 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5550 13:31:13.029422 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5551 13:31:13.032908 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5552 13:31:13.039287 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5553 13:31:13.042213 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5554 13:31:13.046109 0 11 16 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
5555 13:31:13.052121 0 11 20 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
5556 13:31:13.055712 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5557 13:31:13.058770 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5558 13:31:13.065226 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5559 13:31:13.068898 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5560 13:31:13.072176 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5561 13:31:13.075174 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5562 13:31:13.082458 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5563 13:31:13.085365 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5564 13:31:13.089474 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5565 13:31:13.095285 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5566 13:31:13.098850 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5567 13:31:13.101946 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5568 13:31:13.108708 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5569 13:31:13.111763 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 13:31:13.115472 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 13:31:13.121922 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 13:31:13.125075 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 13:31:13.127871 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 13:31:13.135174 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 13:31:13.138816 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 13:31:13.141404 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 13:31:13.148456 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5578 13:31:13.151469 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5579 13:31:13.154454 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5580 13:31:13.161355 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 13:31:13.164340 Total UI for P1: 0, mck2ui 16
5582 13:31:13.168152 best dqsien dly found for B0: ( 0, 14, 16)
5583 13:31:13.171776 Total UI for P1: 0, mck2ui 16
5584 13:31:13.174627 best dqsien dly found for B1: ( 0, 14, 20)
5585 13:31:13.177957 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5586 13:31:13.181704 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5587 13:31:13.182047
5588 13:31:13.184931 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5589 13:31:13.187736 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5590 13:31:13.191847 [Gating] SW calibration Done
5591 13:31:13.192398 ==
5592 13:31:13.194463 Dram Type= 6, Freq= 0, CH_1, rank 1
5593 13:31:13.197817 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5594 13:31:13.198208 ==
5595 13:31:13.200935 RX Vref Scan: 0
5596 13:31:13.201277
5597 13:31:13.204603 RX Vref 0 -> 0, step: 1
5598 13:31:13.205063
5599 13:31:13.205369 RX Delay -80 -> 252, step: 8
5600 13:31:13.210935 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5601 13:31:13.214700 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5602 13:31:13.217868 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5603 13:31:13.220985 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5604 13:31:13.224952 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5605 13:31:13.227501 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5606 13:31:13.234455 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5607 13:31:13.237495 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5608 13:31:13.240937 iDelay=208, Bit 8, Center 71 (-32 ~ 175) 208
5609 13:31:13.244406 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5610 13:31:13.247646 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5611 13:31:13.253708 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5612 13:31:13.257602 iDelay=208, Bit 12, Center 95 (-8 ~ 199) 208
5613 13:31:13.261101 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5614 13:31:13.263904 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5615 13:31:13.267437 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5616 13:31:13.267893 ==
5617 13:31:13.270616 Dram Type= 6, Freq= 0, CH_1, rank 1
5618 13:31:13.277262 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5619 13:31:13.277659 ==
5620 13:31:13.277933 DQS Delay:
5621 13:31:13.278167 DQS0 = 0, DQS1 = 0
5622 13:31:13.280457 DQM Delay:
5623 13:31:13.280838 DQM0 = 96, DQM1 = 86
5624 13:31:13.283958 DQ Delay:
5625 13:31:13.287370 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5626 13:31:13.290771 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5627 13:31:13.294133 DQ8 =71, DQ9 =75, DQ10 =87, DQ11 =75
5628 13:31:13.297424 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5629 13:31:13.297779
5630 13:31:13.298026
5631 13:31:13.298243 ==
5632 13:31:13.300246 Dram Type= 6, Freq= 0, CH_1, rank 1
5633 13:31:13.304140 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5634 13:31:13.304658 ==
5635 13:31:13.304937
5636 13:31:13.305159
5637 13:31:13.307558 TX Vref Scan disable
5638 13:31:13.308020 == TX Byte 0 ==
5639 13:31:13.313778 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5640 13:31:13.317489 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5641 13:31:13.317856 == TX Byte 1 ==
5642 13:31:13.323587 Update DQ dly =704 (2 ,5, 32) DQ OEN =(2 ,2)
5643 13:31:13.326751 Update DQM dly =704 (2 ,5, 32) DQM OEN =(2 ,2)
5644 13:31:13.327109 ==
5645 13:31:13.329932 Dram Type= 6, Freq= 0, CH_1, rank 1
5646 13:31:13.333968 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5647 13:31:13.336739 ==
5648 13:31:13.337156
5649 13:31:13.337406
5650 13:31:13.337624 TX Vref Scan disable
5651 13:31:13.340144 == TX Byte 0 ==
5652 13:31:13.344133 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5653 13:31:13.350240 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5654 13:31:13.350609 == TX Byte 1 ==
5655 13:31:13.353270 Update DQ dly =704 (2 ,5, 32) DQ OEN =(2 ,2)
5656 13:31:13.360054 Update DQM dly =704 (2 ,5, 32) DQM OEN =(2 ,2)
5657 13:31:13.360607
5658 13:31:13.360879 [DATLAT]
5659 13:31:13.361097 Freq=933, CH1 RK1
5660 13:31:13.361306
5661 13:31:13.363640 DATLAT Default: 0xb
5662 13:31:13.366930 0, 0xFFFF, sum = 0
5663 13:31:13.367377 1, 0xFFFF, sum = 0
5664 13:31:13.369861 2, 0xFFFF, sum = 0
5665 13:31:13.370219 3, 0xFFFF, sum = 0
5666 13:31:13.373303 4, 0xFFFF, sum = 0
5667 13:31:13.373660 5, 0xFFFF, sum = 0
5668 13:31:13.376502 6, 0xFFFF, sum = 0
5669 13:31:13.376859 7, 0xFFFF, sum = 0
5670 13:31:13.379683 8, 0xFFFF, sum = 0
5671 13:31:13.380104 9, 0xFFFF, sum = 0
5672 13:31:13.383267 10, 0x0, sum = 1
5673 13:31:13.383622 11, 0x0, sum = 2
5674 13:31:13.386267 12, 0x0, sum = 3
5675 13:31:13.386644 13, 0x0, sum = 4
5676 13:31:13.386902 best_step = 11
5677 13:31:13.389816
5678 13:31:13.390163 ==
5679 13:31:13.392743 Dram Type= 6, Freq= 0, CH_1, rank 1
5680 13:31:13.396736 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5681 13:31:13.397151 ==
5682 13:31:13.397400 RX Vref Scan: 0
5683 13:31:13.397678
5684 13:31:13.399878 RX Vref 0 -> 0, step: 1
5685 13:31:13.400229
5686 13:31:13.403053 RX Delay -77 -> 252, step: 4
5687 13:31:13.409746 iDelay=203, Bit 0, Center 98 (7 ~ 190) 184
5688 13:31:13.413009 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5689 13:31:13.416658 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5690 13:31:13.419520 iDelay=203, Bit 3, Center 94 (3 ~ 186) 184
5691 13:31:13.422798 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5692 13:31:13.426402 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5693 13:31:13.433038 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5694 13:31:13.436659 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5695 13:31:13.439417 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5696 13:31:13.442457 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5697 13:31:13.446178 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5698 13:31:13.449408 iDelay=203, Bit 11, Center 82 (-9 ~ 174) 184
5699 13:31:13.455698 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5700 13:31:13.459236 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5701 13:31:13.462791 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5702 13:31:13.466475 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5703 13:31:13.466947 ==
5704 13:31:13.469181 Dram Type= 6, Freq= 0, CH_1, rank 1
5705 13:31:13.472723 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5706 13:31:13.475999 ==
5707 13:31:13.476510 DQS Delay:
5708 13:31:13.476795 DQS0 = 0, DQS1 = 0
5709 13:31:13.479143 DQM Delay:
5710 13:31:13.479614 DQM0 = 96, DQM1 = 87
5711 13:31:13.482744 DQ Delay:
5712 13:31:13.483117 DQ0 =98, DQ1 =90, DQ2 =88, DQ3 =94
5713 13:31:13.486472 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5714 13:31:13.489057 DQ8 =74, DQ9 =74, DQ10 =88, DQ11 =82
5715 13:31:13.492521 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
5716 13:31:13.496491
5717 13:31:13.496738
5718 13:31:13.502453 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
5719 13:31:13.505734 CH1 RK1: MR19=505, MR18=1F1F
5720 13:31:13.512289 CH1_RK1: MR19=0x505, MR18=0x1F1F, DQSOSC=412, MR23=63, INC=63, DEC=42
5721 13:31:13.515502 [RxdqsGatingPostProcess] freq 933
5722 13:31:13.519261 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5723 13:31:13.521937 Pre-setting of DQS Precalculation
5724 13:31:13.528930 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5725 13:31:13.535355 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5726 13:31:13.541886 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5727 13:31:13.541996
5728 13:31:13.542056
5729 13:31:13.545415 [Calibration Summary] 1866 Mbps
5730 13:31:13.545495 CH 0, Rank 0
5731 13:31:13.548871 SW Impedance : PASS
5732 13:31:13.552154 DUTY Scan : NO K
5733 13:31:13.552237 ZQ Calibration : PASS
5734 13:31:13.555421 Jitter Meter : NO K
5735 13:31:13.558732 CBT Training : PASS
5736 13:31:13.558815 Write leveling : PASS
5737 13:31:13.561740 RX DQS gating : PASS
5738 13:31:13.565265 RX DQ/DQS(RDDQC) : PASS
5739 13:31:13.565349 TX DQ/DQS : PASS
5740 13:31:13.568691 RX DATLAT : PASS
5741 13:31:13.568786 RX DQ/DQS(Engine): PASS
5742 13:31:13.572019 TX OE : NO K
5743 13:31:13.572095 All Pass.
5744 13:31:13.572150
5745 13:31:13.575156 CH 0, Rank 1
5746 13:31:13.575242 SW Impedance : PASS
5747 13:31:13.578421 DUTY Scan : NO K
5748 13:31:13.582162 ZQ Calibration : PASS
5749 13:31:13.582241 Jitter Meter : NO K
5750 13:31:13.585505 CBT Training : PASS
5751 13:31:13.588354 Write leveling : PASS
5752 13:31:13.588431 RX DQS gating : PASS
5753 13:31:13.591730 RX DQ/DQS(RDDQC) : PASS
5754 13:31:13.595253 TX DQ/DQS : PASS
5755 13:31:13.595330 RX DATLAT : PASS
5756 13:31:13.598817 RX DQ/DQS(Engine): PASS
5757 13:31:13.602221 TX OE : NO K
5758 13:31:13.602295 All Pass.
5759 13:31:13.602347
5760 13:31:13.602394 CH 1, Rank 0
5761 13:31:13.605009 SW Impedance : PASS
5762 13:31:13.608255 DUTY Scan : NO K
5763 13:31:13.608354 ZQ Calibration : PASS
5764 13:31:13.611585 Jitter Meter : NO K
5765 13:31:13.615482 CBT Training : PASS
5766 13:31:13.615603 Write leveling : PASS
5767 13:31:13.618396 RX DQS gating : PASS
5768 13:31:13.621867 RX DQ/DQS(RDDQC) : PASS
5769 13:31:13.621951 TX DQ/DQS : PASS
5770 13:31:13.625081 RX DATLAT : PASS
5771 13:31:13.625156 RX DQ/DQS(Engine): PASS
5772 13:31:13.628651 TX OE : NO K
5773 13:31:13.628834 All Pass.
5774 13:31:13.628902
5775 13:31:13.631750 CH 1, Rank 1
5776 13:31:13.631918 SW Impedance : PASS
5777 13:31:13.634996 DUTY Scan : NO K
5778 13:31:13.638518 ZQ Calibration : PASS
5779 13:31:13.638678 Jitter Meter : NO K
5780 13:31:13.641686 CBT Training : PASS
5781 13:31:13.645106 Write leveling : PASS
5782 13:31:13.645248 RX DQS gating : PASS
5783 13:31:13.647975 RX DQ/DQS(RDDQC) : PASS
5784 13:31:13.651574 TX DQ/DQS : PASS
5785 13:31:13.651792 RX DATLAT : PASS
5786 13:31:13.655189 RX DQ/DQS(Engine): PASS
5787 13:31:13.658653 TX OE : NO K
5788 13:31:13.659081 All Pass.
5789 13:31:13.659390
5790 13:31:13.661894 DramC Write-DBI off
5791 13:31:13.662356 PER_BANK_REFRESH: Hybrid Mode
5792 13:31:13.665140 TX_TRACKING: ON
5793 13:31:13.671815 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5794 13:31:13.678729 [FAST_K] Save calibration result to emmc
5795 13:31:13.681445 dramc_set_vcore_voltage set vcore to 650000
5796 13:31:13.681821 Read voltage for 400, 6
5797 13:31:13.684732 Vio18 = 0
5798 13:31:13.685123 Vcore = 650000
5799 13:31:13.685374 Vdram = 0
5800 13:31:13.687836 Vddq = 0
5801 13:31:13.688099 Vmddr = 0
5802 13:31:13.691044 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5803 13:31:13.697526 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5804 13:31:13.701522 MEM_TYPE=3, freq_sel=20
5805 13:31:13.704107 sv_algorithm_assistance_LP4_800
5806 13:31:13.707717 ============ PULL DRAM RESETB DOWN ============
5807 13:31:13.711163 ========== PULL DRAM RESETB DOWN end =========
5808 13:31:13.718087 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5809 13:31:13.718248 ===================================
5810 13:31:13.721171 LPDDR4 DRAM CONFIGURATION
5811 13:31:13.724566 ===================================
5812 13:31:13.727893 EX_ROW_EN[0] = 0x0
5813 13:31:13.728119 EX_ROW_EN[1] = 0x0
5814 13:31:13.731373 LP4Y_EN = 0x0
5815 13:31:13.731714 WORK_FSP = 0x0
5816 13:31:13.734426 WL = 0x2
5817 13:31:13.734841 RL = 0x2
5818 13:31:13.737979 BL = 0x2
5819 13:31:13.738432 RPST = 0x0
5820 13:31:13.741298 RD_PRE = 0x0
5821 13:31:13.744339 WR_PRE = 0x1
5822 13:31:13.744780 WR_PST = 0x0
5823 13:31:13.748068 DBI_WR = 0x0
5824 13:31:13.748553 DBI_RD = 0x0
5825 13:31:13.750794 OTF = 0x1
5826 13:31:13.754420 ===================================
5827 13:31:13.758190 ===================================
5828 13:31:13.758677 ANA top config
5829 13:31:13.760964 ===================================
5830 13:31:13.764371 DLL_ASYNC_EN = 0
5831 13:31:13.768031 ALL_SLAVE_EN = 1
5832 13:31:13.768462 NEW_RANK_MODE = 1
5833 13:31:13.771491 DLL_IDLE_MODE = 1
5834 13:31:13.774383 LP45_APHY_COMB_EN = 1
5835 13:31:13.777541 TX_ODT_DIS = 1
5836 13:31:13.777920 NEW_8X_MODE = 1
5837 13:31:13.781577 ===================================
5838 13:31:13.784085 ===================================
5839 13:31:13.787666 data_rate = 800
5840 13:31:13.790816 CKR = 1
5841 13:31:13.794108 DQ_P2S_RATIO = 4
5842 13:31:13.797925 ===================================
5843 13:31:13.800551 CA_P2S_RATIO = 4
5844 13:31:13.804106 DQ_CA_OPEN = 0
5845 13:31:13.807274 DQ_SEMI_OPEN = 1
5846 13:31:13.807654 CA_SEMI_OPEN = 1
5847 13:31:13.810596 CA_FULL_RATE = 0
5848 13:31:13.814195 DQ_CKDIV4_EN = 0
5849 13:31:13.818021 CA_CKDIV4_EN = 1
5850 13:31:13.820920 CA_PREDIV_EN = 0
5851 13:31:13.823743 PH8_DLY = 0
5852 13:31:13.824139 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5853 13:31:13.827994 DQ_AAMCK_DIV = 0
5854 13:31:13.830708 CA_AAMCK_DIV = 0
5855 13:31:13.833697 CA_ADMCK_DIV = 4
5856 13:31:13.836996 DQ_TRACK_CA_EN = 0
5857 13:31:13.840631 CA_PICK = 800
5858 13:31:13.841139 CA_MCKIO = 400
5859 13:31:13.843954 MCKIO_SEMI = 400
5860 13:31:13.847292 PLL_FREQ = 3016
5861 13:31:13.850291 DQ_UI_PI_RATIO = 32
5862 13:31:13.853758 CA_UI_PI_RATIO = 32
5863 13:31:13.857228 ===================================
5864 13:31:13.860028 ===================================
5865 13:31:13.863971 memory_type:LPDDR4
5866 13:31:13.864448 GP_NUM : 10
5867 13:31:13.867167 SRAM_EN : 1
5868 13:31:13.867556 MD32_EN : 0
5869 13:31:13.870579 ===================================
5870 13:31:13.874036 [ANA_INIT] >>>>>>>>>>>>>>
5871 13:31:13.877329 <<<<<< [CONFIGURE PHASE]: ANA_TX
5872 13:31:13.880409 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5873 13:31:13.884356 ===================================
5874 13:31:13.887632 data_rate = 800,PCW = 0X7400
5875 13:31:13.890713 ===================================
5876 13:31:13.893758 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5877 13:31:13.897298 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5878 13:31:13.910631 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5879 13:31:13.913619 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5880 13:31:13.917174 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5881 13:31:13.920255 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5882 13:31:13.923908 [ANA_INIT] flow start
5883 13:31:13.926938 [ANA_INIT] PLL >>>>>>>>
5884 13:31:13.927589 [ANA_INIT] PLL <<<<<<<<
5885 13:31:13.930549 [ANA_INIT] MIDPI >>>>>>>>
5886 13:31:13.934037 [ANA_INIT] MIDPI <<<<<<<<
5887 13:31:13.934476 [ANA_INIT] DLL >>>>>>>>
5888 13:31:13.937043 [ANA_INIT] flow end
5889 13:31:13.940401 ============ LP4 DIFF to SE enter ============
5890 13:31:13.946750 ============ LP4 DIFF to SE exit ============
5891 13:31:13.947145 [ANA_INIT] <<<<<<<<<<<<<
5892 13:31:13.949985 [Flow] Enable top DCM control >>>>>
5893 13:31:13.953307 [Flow] Enable top DCM control <<<<<
5894 13:31:13.956636 Enable DLL master slave shuffle
5895 13:31:13.963049 ==============================================================
5896 13:31:13.963413 Gating Mode config
5897 13:31:13.969853 ==============================================================
5898 13:31:13.973741 Config description:
5899 13:31:13.982816 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5900 13:31:13.989469 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5901 13:31:13.993564 SELPH_MODE 0: By rank 1: By Phase
5902 13:31:13.999526 ==============================================================
5903 13:31:14.003290 GAT_TRACK_EN = 0
5904 13:31:14.003729 RX_GATING_MODE = 2
5905 13:31:14.006488 RX_GATING_TRACK_MODE = 2
5906 13:31:14.009766 SELPH_MODE = 1
5907 13:31:14.012840 PICG_EARLY_EN = 1
5908 13:31:14.016388 VALID_LAT_VALUE = 1
5909 13:31:14.023245 ==============================================================
5910 13:31:14.026342 Enter into Gating configuration >>>>
5911 13:31:14.029657 Exit from Gating configuration <<<<
5912 13:31:14.033263 Enter into DVFS_PRE_config >>>>>
5913 13:31:14.042683 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5914 13:31:14.046413 Exit from DVFS_PRE_config <<<<<
5915 13:31:14.049343 Enter into PICG configuration >>>>
5916 13:31:14.052992 Exit from PICG configuration <<<<
5917 13:31:14.055781 [RX_INPUT] configuration >>>>>
5918 13:31:14.058929 [RX_INPUT] configuration <<<<<
5919 13:31:14.062585 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5920 13:31:14.069144 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5921 13:31:14.075512 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5922 13:31:14.082545 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5923 13:31:14.085306 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5924 13:31:14.091878 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5925 13:31:14.095391 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5926 13:31:14.102421 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5927 13:31:14.105623 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5928 13:31:14.109216 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5929 13:31:14.111999 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5930 13:31:14.118918 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5931 13:31:14.121984 ===================================
5932 13:31:14.125475 LPDDR4 DRAM CONFIGURATION
5933 13:31:14.128347 ===================================
5934 13:31:14.128639 EX_ROW_EN[0] = 0x0
5935 13:31:14.131949 EX_ROW_EN[1] = 0x0
5936 13:31:14.132440 LP4Y_EN = 0x0
5937 13:31:14.135456 WORK_FSP = 0x0
5938 13:31:14.135865 WL = 0x2
5939 13:31:14.139000 RL = 0x2
5940 13:31:14.139352 BL = 0x2
5941 13:31:14.142314 RPST = 0x0
5942 13:31:14.142702 RD_PRE = 0x0
5943 13:31:14.145243 WR_PRE = 0x1
5944 13:31:14.145395 WR_PST = 0x0
5945 13:31:14.148443 DBI_WR = 0x0
5946 13:31:14.148794 DBI_RD = 0x0
5947 13:31:14.152156 OTF = 0x1
5948 13:31:14.155072 ===================================
5949 13:31:14.158326 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5950 13:31:14.161404 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5951 13:31:14.168128 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5952 13:31:14.171630 ===================================
5953 13:31:14.171978 LPDDR4 DRAM CONFIGURATION
5954 13:31:14.174808 ===================================
5955 13:31:14.177876 EX_ROW_EN[0] = 0x10
5956 13:31:14.181648 EX_ROW_EN[1] = 0x0
5957 13:31:14.181728 LP4Y_EN = 0x0
5958 13:31:14.184789 WORK_FSP = 0x0
5959 13:31:14.184864 WL = 0x2
5960 13:31:14.187919 RL = 0x2
5961 13:31:14.187996 BL = 0x2
5962 13:31:14.191530 RPST = 0x0
5963 13:31:14.191616 RD_PRE = 0x0
5964 13:31:14.194838 WR_PRE = 0x1
5965 13:31:14.194915 WR_PST = 0x0
5966 13:31:14.198032 DBI_WR = 0x0
5967 13:31:14.198107 DBI_RD = 0x0
5968 13:31:14.201378 OTF = 0x1
5969 13:31:14.204437 ===================================
5970 13:31:14.211349 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5971 13:31:14.214451 nWR fixed to 30
5972 13:31:14.218013 [ModeRegInit_LP4] CH0 RK0
5973 13:31:14.218476 [ModeRegInit_LP4] CH0 RK1
5974 13:31:14.220897 [ModeRegInit_LP4] CH1 RK0
5975 13:31:14.224380 [ModeRegInit_LP4] CH1 RK1
5976 13:31:14.224728 match AC timing 18
5977 13:31:14.231148 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5978 13:31:14.234441 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5979 13:31:14.238068 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5980 13:31:14.244095 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5981 13:31:14.248077 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5982 13:31:14.248458 ==
5983 13:31:14.251276 Dram Type= 6, Freq= 0, CH_0, rank 0
5984 13:31:14.254414 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5985 13:31:14.254775 ==
5986 13:31:14.261354 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5987 13:31:14.267842 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5988 13:31:14.270987 [CA 0] Center 36 (8~64) winsize 57
5989 13:31:14.274388 [CA 1] Center 36 (8~64) winsize 57
5990 13:31:14.277902 [CA 2] Center 36 (8~64) winsize 57
5991 13:31:14.280691 [CA 3] Center 36 (8~64) winsize 57
5992 13:31:14.281044 [CA 4] Center 36 (8~64) winsize 57
5993 13:31:14.283895 [CA 5] Center 36 (8~64) winsize 57
5994 13:31:14.284268
5995 13:31:14.291350 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5996 13:31:14.291427
5997 13:31:14.294270 [CATrainingPosCal] consider 1 rank data
5998 13:31:14.297393 u2DelayCellTimex100 = 270/100 ps
5999 13:31:14.300728 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6000 13:31:14.304773 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6001 13:31:14.307329 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6002 13:31:14.310876 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6003 13:31:14.313868 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6004 13:31:14.316911 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6005 13:31:14.316997
6006 13:31:14.320687 CA PerBit enable=1, Macro0, CA PI delay=36
6007 13:31:14.321040
6008 13:31:14.324410 [CBTSetCACLKResult] CA Dly = 36
6009 13:31:14.326904 CS Dly: 1 (0~32)
6010 13:31:14.327255 ==
6011 13:31:14.330723 Dram Type= 6, Freq= 0, CH_0, rank 1
6012 13:31:14.334670 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6013 13:31:14.335090 ==
6014 13:31:14.340383 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6015 13:31:14.347320 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6016 13:31:14.347786 [CA 0] Center 36 (8~64) winsize 57
6017 13:31:14.350827 [CA 1] Center 36 (8~64) winsize 57
6018 13:31:14.354609 [CA 2] Center 36 (8~64) winsize 57
6019 13:31:14.357245 [CA 3] Center 36 (8~64) winsize 57
6020 13:31:14.360723 [CA 4] Center 36 (8~64) winsize 57
6021 13:31:14.363619 [CA 5] Center 36 (8~64) winsize 57
6022 13:31:14.363970
6023 13:31:14.367114 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6024 13:31:14.367568
6025 13:31:14.370131 [CATrainingPosCal] consider 2 rank data
6026 13:31:14.373700 u2DelayCellTimex100 = 270/100 ps
6027 13:31:14.376816 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6028 13:31:14.383955 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6029 13:31:14.386921 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6030 13:31:14.390123 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6031 13:31:14.393519 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6032 13:31:14.396815 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6033 13:31:14.397235
6034 13:31:14.400330 CA PerBit enable=1, Macro0, CA PI delay=36
6035 13:31:14.400672
6036 13:31:14.403345 [CBTSetCACLKResult] CA Dly = 36
6037 13:31:14.406659 CS Dly: 1 (0~32)
6038 13:31:14.407001
6039 13:31:14.409430 ----->DramcWriteLeveling(PI) begin...
6040 13:31:14.409511 ==
6041 13:31:14.412943 Dram Type= 6, Freq= 0, CH_0, rank 0
6042 13:31:14.415974 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6043 13:31:14.416048 ==
6044 13:31:14.419390 Write leveling (Byte 0): 32 => 0
6045 13:31:14.422575 Write leveling (Byte 1): 32 => 0
6046 13:31:14.426238 DramcWriteLeveling(PI) end<-----
6047 13:31:14.426314
6048 13:31:14.426367 ==
6049 13:31:14.429433 Dram Type= 6, Freq= 0, CH_0, rank 0
6050 13:31:14.432461 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6051 13:31:14.432555 ==
6052 13:31:14.435645 [Gating] SW mode calibration
6053 13:31:14.442895 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6054 13:31:14.449520 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6055 13:31:14.453003 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6056 13:31:14.456372 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6057 13:31:14.463234 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6058 13:31:14.465991 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6059 13:31:14.469181 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6060 13:31:14.475934 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6061 13:31:14.479050 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6062 13:31:14.482711 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6063 13:31:14.489135 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6064 13:31:14.489584 Total UI for P1: 0, mck2ui 16
6065 13:31:14.495746 best dqsien dly found for B0: ( 0, 10, 16)
6066 13:31:14.496205 Total UI for P1: 0, mck2ui 16
6067 13:31:14.499399 best dqsien dly found for B1: ( 0, 10, 24)
6068 13:31:14.505660 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6069 13:31:14.508930 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6070 13:31:14.509416
6071 13:31:14.512638 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6072 13:31:14.515781 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6073 13:31:14.519108 [Gating] SW calibration Done
6074 13:31:14.519459 ==
6075 13:31:14.522187 Dram Type= 6, Freq= 0, CH_0, rank 0
6076 13:31:14.526034 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6077 13:31:14.526499 ==
6078 13:31:14.528618 RX Vref Scan: 0
6079 13:31:14.528961
6080 13:31:14.529206 RX Vref 0 -> 0, step: 1
6081 13:31:14.529426
6082 13:31:14.532311 RX Delay -410 -> 252, step: 16
6083 13:31:14.538763 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6084 13:31:14.542112 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6085 13:31:14.545269 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6086 13:31:14.548962 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6087 13:31:14.555256 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6088 13:31:14.558878 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6089 13:31:14.561855 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6090 13:31:14.565358 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6091 13:31:14.572193 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6092 13:31:14.575253 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6093 13:31:14.578819 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6094 13:31:14.581762 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6095 13:31:14.588518 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6096 13:31:14.591566 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6097 13:31:14.594698 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6098 13:31:14.601803 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6099 13:31:14.602214 ==
6100 13:31:14.604926 Dram Type= 6, Freq= 0, CH_0, rank 0
6101 13:31:14.607822 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6102 13:31:14.608117 ==
6103 13:31:14.608378 DQS Delay:
6104 13:31:14.611844 DQS0 = 43, DQS1 = 59
6105 13:31:14.612190 DQM Delay:
6106 13:31:14.614707 DQM0 = 5, DQM1 = 15
6107 13:31:14.615123 DQ Delay:
6108 13:31:14.618642 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6109 13:31:14.621127 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6110 13:31:14.624924 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6111 13:31:14.628251 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6112 13:31:14.628748
6113 13:31:14.629049
6114 13:31:14.629272 ==
6115 13:31:14.631386 Dram Type= 6, Freq= 0, CH_0, rank 0
6116 13:31:14.634863 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6117 13:31:14.635359 ==
6118 13:31:14.635675
6119 13:31:14.635896
6120 13:31:14.637947 TX Vref Scan disable
6121 13:31:14.638449 == TX Byte 0 ==
6122 13:31:14.644950 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6123 13:31:14.647928 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6124 13:31:14.648461 == TX Byte 1 ==
6125 13:31:14.654533 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6126 13:31:14.657794 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6127 13:31:14.658185 ==
6128 13:31:14.660738 Dram Type= 6, Freq= 0, CH_0, rank 0
6129 13:31:14.664248 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6130 13:31:14.664761 ==
6131 13:31:14.665040
6132 13:31:14.667435
6133 13:31:14.667841 TX Vref Scan disable
6134 13:31:14.670525 == TX Byte 0 ==
6135 13:31:14.674481 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6136 13:31:14.677933 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6137 13:31:14.681020 == TX Byte 1 ==
6138 13:31:14.684357 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6139 13:31:14.687474 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6140 13:31:14.687821
6141 13:31:14.690735 [DATLAT]
6142 13:31:14.691094 Freq=400, CH0 RK0
6143 13:31:14.691340
6144 13:31:14.693903 DATLAT Default: 0xf
6145 13:31:14.694252 0, 0xFFFF, sum = 0
6146 13:31:14.697891 1, 0xFFFF, sum = 0
6147 13:31:14.698395 2, 0xFFFF, sum = 0
6148 13:31:14.700743 3, 0xFFFF, sum = 0
6149 13:31:14.701220 4, 0xFFFF, sum = 0
6150 13:31:14.703769 5, 0xFFFF, sum = 0
6151 13:31:14.704114 6, 0xFFFF, sum = 0
6152 13:31:14.707465 7, 0xFFFF, sum = 0
6153 13:31:14.707938 8, 0xFFFF, sum = 0
6154 13:31:14.710937 9, 0xFFFF, sum = 0
6155 13:31:14.711399 10, 0xFFFF, sum = 0
6156 13:31:14.713743 11, 0xFFFF, sum = 0
6157 13:31:14.714182 12, 0x0, sum = 1
6158 13:31:14.717102 13, 0x0, sum = 2
6159 13:31:14.717591 14, 0x0, sum = 3
6160 13:31:14.720677 15, 0x0, sum = 4
6161 13:31:14.721136 best_step = 13
6162 13:31:14.721412
6163 13:31:14.721651 ==
6164 13:31:14.723614 Dram Type= 6, Freq= 0, CH_0, rank 0
6165 13:31:14.730469 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6166 13:31:14.730911 ==
6167 13:31:14.731185 RX Vref Scan: 1
6168 13:31:14.731441
6169 13:31:14.734127 RX Vref 0 -> 0, step: 1
6170 13:31:14.734719
6171 13:31:14.737533 RX Delay -359 -> 252, step: 8
6172 13:31:14.738005
6173 13:31:14.740244 Set Vref, RX VrefLevel [Byte0]: 47
6174 13:31:14.743662 [Byte1]: 49
6175 13:31:14.744011
6176 13:31:14.747393 Final RX Vref Byte 0 = 47 to rank0
6177 13:31:14.750332 Final RX Vref Byte 1 = 49 to rank0
6178 13:31:14.754131 Final RX Vref Byte 0 = 47 to rank1
6179 13:31:14.756774 Final RX Vref Byte 1 = 49 to rank1==
6180 13:31:14.760035 Dram Type= 6, Freq= 0, CH_0, rank 0
6181 13:31:14.766567 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6182 13:31:14.767015 ==
6183 13:31:14.767287 DQS Delay:
6184 13:31:14.770529 DQS0 = 52, DQS1 = 68
6185 13:31:14.771000 DQM Delay:
6186 13:31:14.771279 DQM0 = 9, DQM1 = 16
6187 13:31:14.773263 DQ Delay:
6188 13:31:14.776652 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =4
6189 13:31:14.777022 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6190 13:31:14.779896 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6191 13:31:14.783249 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6192 13:31:14.783680
6193 13:31:14.783925
6194 13:31:14.792948 [DQSOSCAuto] RK0, (LSB)MR18= 0x9b9b, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
6195 13:31:14.796232 CH0 RK0: MR19=C0C, MR18=9B9B
6196 13:31:14.803319 CH0_RK0: MR19=0xC0C, MR18=0x9B9B, DQSOSC=390, MR23=63, INC=388, DEC=258
6197 13:31:14.803669 ==
6198 13:31:14.806501 Dram Type= 6, Freq= 0, CH_0, rank 1
6199 13:31:14.810281 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6200 13:31:14.810884 ==
6201 13:31:14.813300 [Gating] SW mode calibration
6202 13:31:14.819835 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6203 13:31:14.826278 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6204 13:31:14.829699 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6205 13:31:14.832666 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6206 13:31:14.839186 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6207 13:31:14.842567 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6208 13:31:14.846149 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6209 13:31:14.852233 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6210 13:31:14.855654 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6211 13:31:14.859541 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6212 13:31:14.865690 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6213 13:31:14.866067 Total UI for P1: 0, mck2ui 16
6214 13:31:14.869051 best dqsien dly found for B0: ( 0, 10, 16)
6215 13:31:14.873077 Total UI for P1: 0, mck2ui 16
6216 13:31:14.875883 best dqsien dly found for B1: ( 0, 10, 24)
6217 13:31:14.882262 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6218 13:31:14.885281 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6219 13:31:14.885628
6220 13:31:14.889010 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6221 13:31:14.892038 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6222 13:31:14.895819 [Gating] SW calibration Done
6223 13:31:14.896260 ==
6224 13:31:14.899091 Dram Type= 6, Freq= 0, CH_0, rank 1
6225 13:31:14.902559 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6226 13:31:14.903022 ==
6227 13:31:14.905596 RX Vref Scan: 0
6228 13:31:14.905944
6229 13:31:14.906190 RX Vref 0 -> 0, step: 1
6230 13:31:14.906411
6231 13:31:14.908492 RX Delay -410 -> 252, step: 16
6232 13:31:14.915505 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6233 13:31:14.918468 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6234 13:31:14.921900 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6235 13:31:14.925397 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6236 13:31:14.931875 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6237 13:31:14.935220 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6238 13:31:14.938271 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6239 13:31:14.942242 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6240 13:31:14.948319 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6241 13:31:14.951506 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6242 13:31:14.954919 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6243 13:31:14.958722 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6244 13:31:14.965132 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6245 13:31:14.968393 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6246 13:31:14.971950 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6247 13:31:14.978742 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6248 13:31:14.979213 ==
6249 13:31:14.981595 Dram Type= 6, Freq= 0, CH_0, rank 1
6250 13:31:14.984466 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6251 13:31:14.984814 ==
6252 13:31:14.985064 DQS Delay:
6253 13:31:14.988135 DQS0 = 43, DQS1 = 59
6254 13:31:14.988665 DQM Delay:
6255 13:31:14.991584 DQM0 = 7, DQM1 = 15
6256 13:31:14.992033 DQ Delay:
6257 13:31:14.995137 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6258 13:31:14.997995 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6259 13:31:15.001668 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6260 13:31:15.004359 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6261 13:31:15.004744
6262 13:31:15.005013
6263 13:31:15.005242 ==
6264 13:31:15.007731 Dram Type= 6, Freq= 0, CH_0, rank 1
6265 13:31:15.012024 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6266 13:31:15.012503 ==
6267 13:31:15.012776
6268 13:31:15.013011
6269 13:31:15.014946 TX Vref Scan disable
6270 13:31:15.015461 == TX Byte 0 ==
6271 13:31:15.021294 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6272 13:31:15.024360 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6273 13:31:15.024777 == TX Byte 1 ==
6274 13:31:15.031075 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6275 13:31:15.034266 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6276 13:31:15.034651 ==
6277 13:31:15.037573 Dram Type= 6, Freq= 0, CH_0, rank 1
6278 13:31:15.041145 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6279 13:31:15.041592 ==
6280 13:31:15.041853
6281 13:31:15.042076
6282 13:31:15.044017 TX Vref Scan disable
6283 13:31:15.044509 == TX Byte 0 ==
6284 13:31:15.050658 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6285 13:31:15.054366 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6286 13:31:15.054715 == TX Byte 1 ==
6287 13:31:15.060888 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6288 13:31:15.063670 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6289 13:31:15.064018
6290 13:31:15.064267 [DATLAT]
6291 13:31:15.067178 Freq=400, CH0 RK1
6292 13:31:15.067527
6293 13:31:15.067775 DATLAT Default: 0xd
6294 13:31:15.071310 0, 0xFFFF, sum = 0
6295 13:31:15.071794 1, 0xFFFF, sum = 0
6296 13:31:15.074037 2, 0xFFFF, sum = 0
6297 13:31:15.074517 3, 0xFFFF, sum = 0
6298 13:31:15.077913 4, 0xFFFF, sum = 0
6299 13:31:15.078262 5, 0xFFFF, sum = 0
6300 13:31:15.080471 6, 0xFFFF, sum = 0
6301 13:31:15.083879 7, 0xFFFF, sum = 0
6302 13:31:15.084349 8, 0xFFFF, sum = 0
6303 13:31:15.087092 9, 0xFFFF, sum = 0
6304 13:31:15.087414 10, 0xFFFF, sum = 0
6305 13:31:15.090583 11, 0xFFFF, sum = 0
6306 13:31:15.090913 12, 0x0, sum = 1
6307 13:31:15.094440 13, 0x0, sum = 2
6308 13:31:15.094831 14, 0x0, sum = 3
6309 13:31:15.097252 15, 0x0, sum = 4
6310 13:31:15.097713 best_step = 13
6311 13:31:15.097984
6312 13:31:15.098208 ==
6313 13:31:15.100711 Dram Type= 6, Freq= 0, CH_0, rank 1
6314 13:31:15.103846 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6315 13:31:15.104396 ==
6316 13:31:15.106709 RX Vref Scan: 0
6317 13:31:15.107056
6318 13:31:15.110384 RX Vref 0 -> 0, step: 1
6319 13:31:15.110813
6320 13:31:15.111086 RX Delay -359 -> 252, step: 8
6321 13:31:15.119044 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6322 13:31:15.122114 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6323 13:31:15.125367 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6324 13:31:15.132205 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6325 13:31:15.135544 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6326 13:31:15.139890 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6327 13:31:15.142714 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6328 13:31:15.145648 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6329 13:31:15.152137 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6330 13:31:15.155939 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6331 13:31:15.159081 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6332 13:31:15.165440 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6333 13:31:15.168699 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6334 13:31:15.172435 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6335 13:31:15.175986 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6336 13:31:15.182701 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6337 13:31:15.183120 ==
6338 13:31:15.185158 Dram Type= 6, Freq= 0, CH_0, rank 1
6339 13:31:15.189110 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6340 13:31:15.189464 ==
6341 13:31:15.189712 DQS Delay:
6342 13:31:15.192163 DQS0 = 52, DQS1 = 64
6343 13:31:15.192552 DQM Delay:
6344 13:31:15.195114 DQM0 = 9, DQM1 = 14
6345 13:31:15.195463 DQ Delay:
6346 13:31:15.198770 DQ0 =4, DQ1 =12, DQ2 =8, DQ3 =4
6347 13:31:15.202046 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6348 13:31:15.205322 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6349 13:31:15.208187 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6350 13:31:15.208596
6351 13:31:15.208849
6352 13:31:15.215045 [DQSOSCAuto] RK1, (LSB)MR18= 0xbaba, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
6353 13:31:15.218632 CH0 RK1: MR19=C0C, MR18=BABA
6354 13:31:15.224734 CH0_RK1: MR19=0xC0C, MR18=0xBABA, DQSOSC=386, MR23=63, INC=396, DEC=264
6355 13:31:15.228098 [RxdqsGatingPostProcess] freq 400
6356 13:31:15.234924 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6357 13:31:15.238301 Pre-setting of DQS Precalculation
6358 13:31:15.241838 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6359 13:31:15.242190 ==
6360 13:31:15.244643 Dram Type= 6, Freq= 0, CH_1, rank 0
6361 13:31:15.248151 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6362 13:31:15.248560 ==
6363 13:31:15.255503 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6364 13:31:15.261467 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6365 13:31:15.264879 [CA 0] Center 36 (8~64) winsize 57
6366 13:31:15.267985 [CA 1] Center 36 (8~64) winsize 57
6367 13:31:15.271410 [CA 2] Center 36 (8~64) winsize 57
6368 13:31:15.274673 [CA 3] Center 36 (8~64) winsize 57
6369 13:31:15.278127 [CA 4] Center 36 (8~64) winsize 57
6370 13:31:15.281002 [CA 5] Center 36 (8~64) winsize 57
6371 13:31:15.281353
6372 13:31:15.284528 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6373 13:31:15.284948
6374 13:31:15.288051 [CATrainingPosCal] consider 1 rank data
6375 13:31:15.291270 u2DelayCellTimex100 = 270/100 ps
6376 13:31:15.294907 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6377 13:31:15.298095 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6378 13:31:15.301838 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6379 13:31:15.304309 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6380 13:31:15.308143 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6381 13:31:15.311749 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6382 13:31:15.312221
6383 13:31:15.314503 CA PerBit enable=1, Macro0, CA PI delay=36
6384 13:31:15.314888
6385 13:31:15.317482 [CBTSetCACLKResult] CA Dly = 36
6386 13:31:15.321350 CS Dly: 1 (0~32)
6387 13:31:15.321830 ==
6388 13:31:15.324348 Dram Type= 6, Freq= 0, CH_1, rank 1
6389 13:31:15.327687 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6390 13:31:15.328149 ==
6391 13:31:15.334363 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6392 13:31:15.341149 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6393 13:31:15.344016 [CA 0] Center 36 (8~64) winsize 57
6394 13:31:15.344536 [CA 1] Center 36 (8~64) winsize 57
6395 13:31:15.347679 [CA 2] Center 36 (8~64) winsize 57
6396 13:31:15.350953 [CA 3] Center 36 (8~64) winsize 57
6397 13:31:15.354477 [CA 4] Center 36 (8~64) winsize 57
6398 13:31:15.357806 [CA 5] Center 36 (8~64) winsize 57
6399 13:31:15.358169
6400 13:31:15.360838 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6401 13:31:15.361328
6402 13:31:15.367371 [CATrainingPosCal] consider 2 rank data
6403 13:31:15.367768 u2DelayCellTimex100 = 270/100 ps
6404 13:31:15.374217 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6405 13:31:15.377448 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6406 13:31:15.381040 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6407 13:31:15.384318 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6408 13:31:15.387219 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6409 13:31:15.390867 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6410 13:31:15.391313
6411 13:31:15.394326 CA PerBit enable=1, Macro0, CA PI delay=36
6412 13:31:15.394783
6413 13:31:15.397214 [CBTSetCACLKResult] CA Dly = 36
6414 13:31:15.400445 CS Dly: 1 (0~32)
6415 13:31:15.400813
6416 13:31:15.403546 ----->DramcWriteLeveling(PI) begin...
6417 13:31:15.403899 ==
6418 13:31:15.407759 Dram Type= 6, Freq= 0, CH_1, rank 0
6419 13:31:15.411291 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6420 13:31:15.411655 ==
6421 13:31:15.414771 Write leveling (Byte 0): 32 => 0
6422 13:31:15.417110 Write leveling (Byte 1): 32 => 0
6423 13:31:15.420195 DramcWriteLeveling(PI) end<-----
6424 13:31:15.420569
6425 13:31:15.420822 ==
6426 13:31:15.423786 Dram Type= 6, Freq= 0, CH_1, rank 0
6427 13:31:15.427141 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6428 13:31:15.427599 ==
6429 13:31:15.430339 [Gating] SW mode calibration
6430 13:31:15.436748 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6431 13:31:15.443480 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6432 13:31:15.446799 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6433 13:31:15.450000 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6434 13:31:15.456545 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6435 13:31:15.460046 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6436 13:31:15.463357 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6437 13:31:15.470238 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6438 13:31:15.473245 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6439 13:31:15.476165 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6440 13:31:15.483041 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6441 13:31:15.483532 Total UI for P1: 0, mck2ui 16
6442 13:31:15.489639 best dqsien dly found for B0: ( 0, 10, 16)
6443 13:31:15.489995 Total UI for P1: 0, mck2ui 16
6444 13:31:15.496728 best dqsien dly found for B1: ( 0, 10, 16)
6445 13:31:15.499664 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6446 13:31:15.502689 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6447 13:31:15.503046
6448 13:31:15.506299 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6449 13:31:15.509887 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6450 13:31:15.512731 [Gating] SW calibration Done
6451 13:31:15.513094 ==
6452 13:31:15.516058 Dram Type= 6, Freq= 0, CH_1, rank 0
6453 13:31:15.519376 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6454 13:31:15.519745 ==
6455 13:31:15.522699 RX Vref Scan: 0
6456 13:31:15.523056
6457 13:31:15.526823 RX Vref 0 -> 0, step: 1
6458 13:31:15.527290
6459 13:31:15.527584 RX Delay -410 -> 252, step: 16
6460 13:31:15.532230 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6461 13:31:15.536212 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6462 13:31:15.539121 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6463 13:31:15.545780 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6464 13:31:15.549034 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6465 13:31:15.552552 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6466 13:31:15.555799 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6467 13:31:15.563023 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6468 13:31:15.565545 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6469 13:31:15.568726 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6470 13:31:15.572038 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6471 13:31:15.578628 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6472 13:31:15.582605 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6473 13:31:15.585323 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6474 13:31:15.588407 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6475 13:31:15.595198 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6476 13:31:15.595553 ==
6477 13:31:15.598949 Dram Type= 6, Freq= 0, CH_1, rank 0
6478 13:31:15.602150 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6479 13:31:15.602606 ==
6480 13:31:15.602876 DQS Delay:
6481 13:31:15.605288 DQS0 = 43, DQS1 = 59
6482 13:31:15.605638 DQM Delay:
6483 13:31:15.609263 DQM0 = 6, DQM1 = 15
6484 13:31:15.609614 DQ Delay:
6485 13:31:15.611896 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6486 13:31:15.615353 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6487 13:31:15.618964 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6488 13:31:15.622360 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6489 13:31:15.622822
6490 13:31:15.623090
6491 13:31:15.623305 ==
6492 13:31:15.625139 Dram Type= 6, Freq= 0, CH_1, rank 0
6493 13:31:15.628743 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6494 13:31:15.629213 ==
6495 13:31:15.629493
6496 13:31:15.631796
6497 13:31:15.632230 TX Vref Scan disable
6498 13:31:15.634785 == TX Byte 0 ==
6499 13:31:15.638294 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6500 13:31:15.641638 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6501 13:31:15.644813 == TX Byte 1 ==
6502 13:31:15.647847 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6503 13:31:15.651455 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6504 13:31:15.651878 ==
6505 13:31:15.654609 Dram Type= 6, Freq= 0, CH_1, rank 0
6506 13:31:15.661707 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6507 13:31:15.662136 ==
6508 13:31:15.662473
6509 13:31:15.662757
6510 13:31:15.663030 TX Vref Scan disable
6511 13:31:15.664324 == TX Byte 0 ==
6512 13:31:15.667783 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6513 13:31:15.671419 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6514 13:31:15.674498 == TX Byte 1 ==
6515 13:31:15.678087 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6516 13:31:15.681260 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6517 13:31:15.681617
6518 13:31:15.684617 [DATLAT]
6519 13:31:15.684967 Freq=400, CH1 RK0
6520 13:31:15.685213
6521 13:31:15.687826 DATLAT Default: 0xf
6522 13:31:15.688099 0, 0xFFFF, sum = 0
6523 13:31:15.691193 1, 0xFFFF, sum = 0
6524 13:31:15.691651 2, 0xFFFF, sum = 0
6525 13:31:15.694560 3, 0xFFFF, sum = 0
6526 13:31:15.694925 4, 0xFFFF, sum = 0
6527 13:31:15.697539 5, 0xFFFF, sum = 0
6528 13:31:15.697921 6, 0xFFFF, sum = 0
6529 13:31:15.701430 7, 0xFFFF, sum = 0
6530 13:31:15.701818 8, 0xFFFF, sum = 0
6531 13:31:15.704630 9, 0xFFFF, sum = 0
6532 13:31:15.705085 10, 0xFFFF, sum = 0
6533 13:31:15.707776 11, 0xFFFF, sum = 0
6534 13:31:15.708132 12, 0x0, sum = 1
6535 13:31:15.711327 13, 0x0, sum = 2
6536 13:31:15.711681 14, 0x0, sum = 3
6537 13:31:15.714502 15, 0x0, sum = 4
6538 13:31:15.714958 best_step = 13
6539 13:31:15.715311
6540 13:31:15.715604 ==
6541 13:31:15.718082 Dram Type= 6, Freq= 0, CH_1, rank 0
6542 13:31:15.724145 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6543 13:31:15.724529 ==
6544 13:31:15.724849 RX Vref Scan: 1
6545 13:31:15.725133
6546 13:31:15.727887 RX Vref 0 -> 0, step: 1
6547 13:31:15.728344
6548 13:31:15.731788 RX Delay -359 -> 252, step: 8
6549 13:31:15.732317
6550 13:31:15.734344 Set Vref, RX VrefLevel [Byte0]: 53
6551 13:31:15.738431 [Byte1]: 49
6552 13:31:15.741105
6553 13:31:15.741604 Final RX Vref Byte 0 = 53 to rank0
6554 13:31:15.744742 Final RX Vref Byte 1 = 49 to rank0
6555 13:31:15.747888 Final RX Vref Byte 0 = 53 to rank1
6556 13:31:15.751138 Final RX Vref Byte 1 = 49 to rank1==
6557 13:31:15.754133 Dram Type= 6, Freq= 0, CH_1, rank 0
6558 13:31:15.760623 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6559 13:31:15.760979 ==
6560 13:31:15.761302 DQS Delay:
6561 13:31:15.764170 DQS0 = 48, DQS1 = 64
6562 13:31:15.764560 DQM Delay:
6563 13:31:15.764879 DQM0 = 7, DQM1 = 15
6564 13:31:15.767427 DQ Delay:
6565 13:31:15.770662 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =4
6566 13:31:15.771121 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =4
6567 13:31:15.774077 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6568 13:31:15.777643 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6569 13:31:15.777996
6570 13:31:15.778317
6571 13:31:15.787216 [DQSOSCAuto] RK0, (LSB)MR18= 0xcbcb, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6572 13:31:15.790765 CH1 RK0: MR19=C0C, MR18=CBCB
6573 13:31:15.797172 CH1_RK0: MR19=0xC0C, MR18=0xCBCB, DQSOSC=384, MR23=63, INC=400, DEC=267
6574 13:31:15.797527 ==
6575 13:31:15.800246 Dram Type= 6, Freq= 0, CH_1, rank 1
6576 13:31:15.803733 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6577 13:31:15.804097 ==
6578 13:31:15.807442 [Gating] SW mode calibration
6579 13:31:15.813960 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6580 13:31:15.820774 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6581 13:31:15.823965 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6582 13:31:15.827288 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6583 13:31:15.833656 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6584 13:31:15.836948 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6585 13:31:15.840032 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6586 13:31:15.846491 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6587 13:31:15.850171 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6588 13:31:15.853320 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6589 13:31:15.859908 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6590 13:31:15.860306 Total UI for P1: 0, mck2ui 16
6591 13:31:15.863678 best dqsien dly found for B0: ( 0, 10, 16)
6592 13:31:15.866498 Total UI for P1: 0, mck2ui 16
6593 13:31:15.870156 best dqsien dly found for B1: ( 0, 10, 16)
6594 13:31:15.873127 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6595 13:31:15.879870 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6596 13:31:15.880316
6597 13:31:15.882872 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6598 13:31:15.887037 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6599 13:31:15.889717 [Gating] SW calibration Done
6600 13:31:15.890065 ==
6601 13:31:15.893380 Dram Type= 6, Freq= 0, CH_1, rank 1
6602 13:31:15.896244 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6603 13:31:15.896629 ==
6604 13:31:15.900356 RX Vref Scan: 0
6605 13:31:15.900839
6606 13:31:15.901119 RX Vref 0 -> 0, step: 1
6607 13:31:15.901348
6608 13:31:15.903639 RX Delay -410 -> 252, step: 16
6609 13:31:15.909692 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6610 13:31:15.913092 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6611 13:31:15.916447 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6612 13:31:15.919759 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6613 13:31:15.926526 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6614 13:31:15.929570 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6615 13:31:15.932815 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6616 13:31:15.936348 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6617 13:31:15.943101 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6618 13:31:15.945903 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6619 13:31:15.949694 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6620 13:31:15.952750 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6621 13:31:15.959438 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6622 13:31:15.962929 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6623 13:31:15.965794 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6624 13:31:15.969633 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6625 13:31:15.972732 ==
6626 13:31:15.973081 Dram Type= 6, Freq= 0, CH_1, rank 1
6627 13:31:15.979103 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6628 13:31:15.979456 ==
6629 13:31:15.979707 DQS Delay:
6630 13:31:15.982426 DQS0 = 43, DQS1 = 59
6631 13:31:15.982695 DQM Delay:
6632 13:31:15.985968 DQM0 = 10, DQM1 = 17
6633 13:31:15.986317 DQ Delay:
6634 13:31:15.989062 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6635 13:31:15.992366 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6636 13:31:15.995743 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6637 13:31:15.999301 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6638 13:31:15.999756
6639 13:31:16.000037
6640 13:31:16.000255 ==
6641 13:31:16.003147 Dram Type= 6, Freq= 0, CH_1, rank 1
6642 13:31:16.005963 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6643 13:31:16.006424 ==
6644 13:31:16.006702
6645 13:31:16.006920
6646 13:31:16.009079 TX Vref Scan disable
6647 13:31:16.009544 == TX Byte 0 ==
6648 13:31:16.015921 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6649 13:31:16.019164 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6650 13:31:16.019547 == TX Byte 1 ==
6651 13:31:16.022244 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6652 13:31:16.029272 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6653 13:31:16.029735 ==
6654 13:31:16.032424 Dram Type= 6, Freq= 0, CH_1, rank 1
6655 13:31:16.035340 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6656 13:31:16.035688 ==
6657 13:31:16.035938
6658 13:31:16.036159
6659 13:31:16.039139 TX Vref Scan disable
6660 13:31:16.039748 == TX Byte 0 ==
6661 13:31:16.045314 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6662 13:31:16.049110 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6663 13:31:16.049459 == TX Byte 1 ==
6664 13:31:16.055146 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6665 13:31:16.059226 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6666 13:31:16.059709
6667 13:31:16.059977 [DATLAT]
6668 13:31:16.062543 Freq=400, CH1 RK1
6669 13:31:16.062984
6670 13:31:16.063260 DATLAT Default: 0xd
6671 13:31:16.065581 0, 0xFFFF, sum = 0
6672 13:31:16.065937 1, 0xFFFF, sum = 0
6673 13:31:16.069359 2, 0xFFFF, sum = 0
6674 13:31:16.069714 3, 0xFFFF, sum = 0
6675 13:31:16.071876 4, 0xFFFF, sum = 0
6676 13:31:16.072157 5, 0xFFFF, sum = 0
6677 13:31:16.075446 6, 0xFFFF, sum = 0
6678 13:31:16.075920 7, 0xFFFF, sum = 0
6679 13:31:16.078852 8, 0xFFFF, sum = 0
6680 13:31:16.079207 9, 0xFFFF, sum = 0
6681 13:31:16.082414 10, 0xFFFF, sum = 0
6682 13:31:16.082780 11, 0xFFFF, sum = 0
6683 13:31:16.086107 12, 0x0, sum = 1
6684 13:31:16.086548 13, 0x0, sum = 2
6685 13:31:16.089160 14, 0x0, sum = 3
6686 13:31:16.089513 15, 0x0, sum = 4
6687 13:31:16.092572 best_step = 13
6688 13:31:16.092920
6689 13:31:16.093168 ==
6690 13:31:16.095341 Dram Type= 6, Freq= 0, CH_1, rank 1
6691 13:31:16.098526 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6692 13:31:16.098876 ==
6693 13:31:16.102365 RX Vref Scan: 0
6694 13:31:16.102847
6695 13:31:16.103121 RX Vref 0 -> 0, step: 1
6696 13:31:16.103344
6697 13:31:16.105342 RX Delay -359 -> 252, step: 8
6698 13:31:16.113744 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6699 13:31:16.116659 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6700 13:31:16.120043 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6701 13:31:16.126552 iDelay=225, Bit 3, Center -44 (-287 ~ 200) 488
6702 13:31:16.129771 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6703 13:31:16.133288 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6704 13:31:16.136307 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6705 13:31:16.139688 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6706 13:31:16.146436 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6707 13:31:16.149784 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504
6708 13:31:16.152978 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6709 13:31:16.159339 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6710 13:31:16.163635 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6711 13:31:16.166428 iDelay=225, Bit 13, Center -36 (-279 ~ 208) 488
6712 13:31:16.169894 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6713 13:31:16.176079 iDelay=225, Bit 15, Center -40 (-287 ~ 208) 496
6714 13:31:16.176467 ==
6715 13:31:16.179318 Dram Type= 6, Freq= 0, CH_1, rank 1
6716 13:31:16.182581 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6717 13:31:16.182934 ==
6718 13:31:16.183180 DQS Delay:
6719 13:31:16.186242 DQS0 = 48, DQS1 = 64
6720 13:31:16.186709 DQM Delay:
6721 13:31:16.189458 DQM0 = 9, DQM1 = 16
6722 13:31:16.189807 DQ Delay:
6723 13:31:16.192858 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6724 13:31:16.196392 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6725 13:31:16.199241 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6726 13:31:16.203018 DQ12 =24, DQ13 =28, DQ14 =24, DQ15 =24
6727 13:31:16.203457
6728 13:31:16.203738
6729 13:31:16.209382 [DQSOSCAuto] RK1, (LSB)MR18= 0xb5b5, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6730 13:31:16.212675 CH1 RK1: MR19=C0C, MR18=B5B5
6731 13:31:16.219362 CH1_RK1: MR19=0xC0C, MR18=0xB5B5, DQSOSC=387, MR23=63, INC=394, DEC=262
6732 13:31:16.222653 [RxdqsGatingPostProcess] freq 400
6733 13:31:16.229594 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6734 13:31:16.230055 Pre-setting of DQS Precalculation
6735 13:31:16.236007 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6736 13:31:16.242925 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6737 13:31:16.249423 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6738 13:31:16.249808
6739 13:31:16.250055
6740 13:31:16.252723 [Calibration Summary] 800 Mbps
6741 13:31:16.255857 CH 0, Rank 0
6742 13:31:16.256217 SW Impedance : PASS
6743 13:31:16.259455 DUTY Scan : NO K
6744 13:31:16.262255 ZQ Calibration : PASS
6745 13:31:16.262605 Jitter Meter : NO K
6746 13:31:16.266401 CBT Training : PASS
6747 13:31:16.269786 Write leveling : PASS
6748 13:31:16.270146 RX DQS gating : PASS
6749 13:31:16.272197 RX DQ/DQS(RDDQC) : PASS
6750 13:31:16.272511 TX DQ/DQS : PASS
6751 13:31:16.275523 RX DATLAT : PASS
6752 13:31:16.279651 RX DQ/DQS(Engine): PASS
6753 13:31:16.280005 TX OE : NO K
6754 13:31:16.282722 All Pass.
6755 13:31:16.283195
6756 13:31:16.283473 CH 0, Rank 1
6757 13:31:16.286103 SW Impedance : PASS
6758 13:31:16.286504 DUTY Scan : NO K
6759 13:31:16.289097 ZQ Calibration : PASS
6760 13:31:16.292336 Jitter Meter : NO K
6761 13:31:16.292686 CBT Training : PASS
6762 13:31:16.295550 Write leveling : NO K
6763 13:31:16.298950 RX DQS gating : PASS
6764 13:31:16.299297 RX DQ/DQS(RDDQC) : PASS
6765 13:31:16.303011 TX DQ/DQS : PASS
6766 13:31:16.306295 RX DATLAT : PASS
6767 13:31:16.306810 RX DQ/DQS(Engine): PASS
6768 13:31:16.308900 TX OE : NO K
6769 13:31:16.309252 All Pass.
6770 13:31:16.309530
6771 13:31:16.311860 CH 1, Rank 0
6772 13:31:16.312208 SW Impedance : PASS
6773 13:31:16.315238 DUTY Scan : NO K
6774 13:31:16.319149 ZQ Calibration : PASS
6775 13:31:16.319496 Jitter Meter : NO K
6776 13:31:16.322321 CBT Training : PASS
6777 13:31:16.325551 Write leveling : PASS
6778 13:31:16.325980 RX DQS gating : PASS
6779 13:31:16.328680 RX DQ/DQS(RDDQC) : PASS
6780 13:31:16.331838 TX DQ/DQS : PASS
6781 13:31:16.332187 RX DATLAT : PASS
6782 13:31:16.335140 RX DQ/DQS(Engine): PASS
6783 13:31:16.335488 TX OE : NO K
6784 13:31:16.338615 All Pass.
6785 13:31:16.338958
6786 13:31:16.339207 CH 1, Rank 1
6787 13:31:16.341677 SW Impedance : PASS
6788 13:31:16.342055 DUTY Scan : NO K
6789 13:31:16.345445 ZQ Calibration : PASS
6790 13:31:16.348468 Jitter Meter : NO K
6791 13:31:16.348820 CBT Training : PASS
6792 13:31:16.351410 Write leveling : NO K
6793 13:31:16.354796 RX DQS gating : PASS
6794 13:31:16.355203 RX DQ/DQS(RDDQC) : PASS
6795 13:31:16.358404 TX DQ/DQS : PASS
6796 13:31:16.361856 RX DATLAT : PASS
6797 13:31:16.362208 RX DQ/DQS(Engine): PASS
6798 13:31:16.364917 TX OE : NO K
6799 13:31:16.365263 All Pass.
6800 13:31:16.365509
6801 13:31:16.367985 DramC Write-DBI off
6802 13:31:16.371417 PER_BANK_REFRESH: Hybrid Mode
6803 13:31:16.371766 TX_TRACKING: ON
6804 13:31:16.381762 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6805 13:31:16.384691 [FAST_K] Save calibration result to emmc
6806 13:31:16.387904 dramc_set_vcore_voltage set vcore to 725000
6807 13:31:16.392155 Read voltage for 1600, 0
6808 13:31:16.392641 Vio18 = 0
6809 13:31:16.392897 Vcore = 725000
6810 13:31:16.394925 Vdram = 0
6811 13:31:16.395273 Vddq = 0
6812 13:31:16.395523 Vmddr = 0
6813 13:31:16.401585 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6814 13:31:16.405341 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6815 13:31:16.408348 MEM_TYPE=3, freq_sel=13
6816 13:31:16.411530 sv_algorithm_assistance_LP4_3733
6817 13:31:16.415263 ============ PULL DRAM RESETB DOWN ============
6818 13:31:16.418419 ========== PULL DRAM RESETB DOWN end =========
6819 13:31:16.424809 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6820 13:31:16.428189 ===================================
6821 13:31:16.431507 LPDDR4 DRAM CONFIGURATION
6822 13:31:16.435004 ===================================
6823 13:31:16.435363 EX_ROW_EN[0] = 0x0
6824 13:31:16.437876 EX_ROW_EN[1] = 0x0
6825 13:31:16.438224 LP4Y_EN = 0x0
6826 13:31:16.441099 WORK_FSP = 0x1
6827 13:31:16.441466 WL = 0x5
6828 13:31:16.444945 RL = 0x5
6829 13:31:16.445396 BL = 0x2
6830 13:31:16.448629 RPST = 0x0
6831 13:31:16.448978 RD_PRE = 0x0
6832 13:31:16.451276 WR_PRE = 0x1
6833 13:31:16.451769 WR_PST = 0x1
6834 13:31:16.453932 DBI_WR = 0x0
6835 13:31:16.457638 DBI_RD = 0x0
6836 13:31:16.457991 OTF = 0x1
6837 13:31:16.461070 ===================================
6838 13:31:16.464311 ===================================
6839 13:31:16.464766 ANA top config
6840 13:31:16.467872 ===================================
6841 13:31:16.471163 DLL_ASYNC_EN = 0
6842 13:31:16.474388 ALL_SLAVE_EN = 0
6843 13:31:16.477335 NEW_RANK_MODE = 1
6844 13:31:16.480343 DLL_IDLE_MODE = 1
6845 13:31:16.480697 LP45_APHY_COMB_EN = 1
6846 13:31:16.483670 TX_ODT_DIS = 0
6847 13:31:16.487095 NEW_8X_MODE = 1
6848 13:31:16.490536 ===================================
6849 13:31:16.493565 ===================================
6850 13:31:16.497074 data_rate = 3200
6851 13:31:16.501029 CKR = 1
6852 13:31:16.504333 DQ_P2S_RATIO = 8
6853 13:31:16.507602 ===================================
6854 13:31:16.508075 CA_P2S_RATIO = 8
6855 13:31:16.510398 DQ_CA_OPEN = 0
6856 13:31:16.514008 DQ_SEMI_OPEN = 0
6857 13:31:16.517008 CA_SEMI_OPEN = 0
6858 13:31:16.520116 CA_FULL_RATE = 0
6859 13:31:16.524014 DQ_CKDIV4_EN = 0
6860 13:31:16.524559 CA_CKDIV4_EN = 0
6861 13:31:16.527030 CA_PREDIV_EN = 0
6862 13:31:16.530379 PH8_DLY = 12
6863 13:31:16.533879 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6864 13:31:16.536597 DQ_AAMCK_DIV = 4
6865 13:31:16.539874 CA_AAMCK_DIV = 4
6866 13:31:16.540265 CA_ADMCK_DIV = 4
6867 13:31:16.544108 DQ_TRACK_CA_EN = 0
6868 13:31:16.546260 CA_PICK = 1600
6869 13:31:16.550192 CA_MCKIO = 1600
6870 13:31:16.553460 MCKIO_SEMI = 0
6871 13:31:16.556029 PLL_FREQ = 3068
6872 13:31:16.559846 DQ_UI_PI_RATIO = 32
6873 13:31:16.562954 CA_UI_PI_RATIO = 0
6874 13:31:16.566343 ===================================
6875 13:31:16.569291 ===================================
6876 13:31:16.569595 memory_type:LPDDR4
6877 13:31:16.573283 GP_NUM : 10
6878 13:31:16.573634 SRAM_EN : 1
6879 13:31:16.576200 MD32_EN : 0
6880 13:31:16.580057 ===================================
6881 13:31:16.583106 [ANA_INIT] >>>>>>>>>>>>>>
6882 13:31:16.586319 <<<<<< [CONFIGURE PHASE]: ANA_TX
6883 13:31:16.589605 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6884 13:31:16.592898 ===================================
6885 13:31:16.595943 data_rate = 3200,PCW = 0X7600
6886 13:31:16.599578 ===================================
6887 13:31:16.602785 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6888 13:31:16.606183 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6889 13:31:16.612763 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6890 13:31:16.616060 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6891 13:31:16.619211 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6892 13:31:16.622577 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6893 13:31:16.625943 [ANA_INIT] flow start
6894 13:31:16.629503 [ANA_INIT] PLL >>>>>>>>
6895 13:31:16.629979 [ANA_INIT] PLL <<<<<<<<
6896 13:31:16.635965 [ANA_INIT] MIDPI >>>>>>>>
6897 13:31:16.636351 [ANA_INIT] MIDPI <<<<<<<<
6898 13:31:16.636694 [ANA_INIT] DLL >>>>>>>>
6899 13:31:16.639044 [ANA_INIT] DLL <<<<<<<<
6900 13:31:16.642601 [ANA_INIT] flow end
6901 13:31:16.645724 ============ LP4 DIFF to SE enter ============
6902 13:31:16.649159 ============ LP4 DIFF to SE exit ============
6903 13:31:16.652372 [ANA_INIT] <<<<<<<<<<<<<
6904 13:31:16.655806 [Flow] Enable top DCM control >>>>>
6905 13:31:16.658860 [Flow] Enable top DCM control <<<<<
6906 13:31:16.662500 Enable DLL master slave shuffle
6907 13:31:16.668770 ==============================================================
6908 13:31:16.669233 Gating Mode config
6909 13:31:16.675694 ==============================================================
6910 13:31:16.676175 Config description:
6911 13:31:16.685276 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6912 13:31:16.692042 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6913 13:31:16.698443 SELPH_MODE 0: By rank 1: By Phase
6914 13:31:16.702494 ==============================================================
6915 13:31:16.705652 GAT_TRACK_EN = 1
6916 13:31:16.708854 RX_GATING_MODE = 2
6917 13:31:16.712338 RX_GATING_TRACK_MODE = 2
6918 13:31:16.715341 SELPH_MODE = 1
6919 13:31:16.718900 PICG_EARLY_EN = 1
6920 13:31:16.722129 VALID_LAT_VALUE = 1
6921 13:31:16.725063 ==============================================================
6922 13:31:16.728567 Enter into Gating configuration >>>>
6923 13:31:16.732093 Exit from Gating configuration <<<<
6924 13:31:16.734746 Enter into DVFS_PRE_config >>>>>
6925 13:31:16.747961 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6926 13:31:16.752063 Exit from DVFS_PRE_config <<<<<
6927 13:31:16.755009 Enter into PICG configuration >>>>
6928 13:31:16.758201 Exit from PICG configuration <<<<
6929 13:31:16.758699 [RX_INPUT] configuration >>>>>
6930 13:31:16.761223 [RX_INPUT] configuration <<<<<
6931 13:31:16.767938 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6932 13:31:16.771003 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6933 13:31:16.777924 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6934 13:31:16.784336 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6935 13:31:16.791076 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6936 13:31:16.797592 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6937 13:31:16.800840 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6938 13:31:16.804697 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6939 13:31:16.811080 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6940 13:31:16.814651 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6941 13:31:16.817584 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6942 13:31:16.824120 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6943 13:31:16.827297 ===================================
6944 13:31:16.827796 LPDDR4 DRAM CONFIGURATION
6945 13:31:16.831074 ===================================
6946 13:31:16.833893 EX_ROW_EN[0] = 0x0
6947 13:31:16.834276 EX_ROW_EN[1] = 0x0
6948 13:31:16.837043 LP4Y_EN = 0x0
6949 13:31:16.840444 WORK_FSP = 0x1
6950 13:31:16.840923 WL = 0x5
6951 13:31:16.843815 RL = 0x5
6952 13:31:16.844328 BL = 0x2
6953 13:31:16.846794 RPST = 0x0
6954 13:31:16.847175 RD_PRE = 0x0
6955 13:31:16.850516 WR_PRE = 0x1
6956 13:31:16.850899 WR_PST = 0x1
6957 13:31:16.853889 DBI_WR = 0x0
6958 13:31:16.854238 DBI_RD = 0x0
6959 13:31:16.856945 OTF = 0x1
6960 13:31:16.860160 ===================================
6961 13:31:16.863524 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6962 13:31:16.867085 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6963 13:31:16.873822 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6964 13:31:16.877124 ===================================
6965 13:31:16.877471 LPDDR4 DRAM CONFIGURATION
6966 13:31:16.879943 ===================================
6967 13:31:16.883734 EX_ROW_EN[0] = 0x10
6968 13:31:16.884352 EX_ROW_EN[1] = 0x0
6969 13:31:16.887177 LP4Y_EN = 0x0
6970 13:31:16.890296 WORK_FSP = 0x1
6971 13:31:16.890664 WL = 0x5
6972 13:31:16.893574 RL = 0x5
6973 13:31:16.893933 BL = 0x2
6974 13:31:16.896983 RPST = 0x0
6975 13:31:16.897331 RD_PRE = 0x0
6976 13:31:16.899961 WR_PRE = 0x1
6977 13:31:16.900344 WR_PST = 0x1
6978 13:31:16.903874 DBI_WR = 0x0
6979 13:31:16.904231 DBI_RD = 0x0
6980 13:31:16.907024 OTF = 0x1
6981 13:31:16.910218 ===================================
6982 13:31:16.916418 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6983 13:31:16.916838 ==
6984 13:31:16.919718 Dram Type= 6, Freq= 0, CH_0, rank 0
6985 13:31:16.923155 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6986 13:31:16.923510 ==
6987 13:31:16.926488 [Duty_Offset_Calibration]
6988 13:31:16.926835 B0:0 B1:2 CA:1
6989 13:31:16.927079
6990 13:31:16.929826 [DutyScan_Calibration_Flow] k_type=0
6991 13:31:16.940370
6992 13:31:16.940843 ==CLK 0==
6993 13:31:16.943924 Final CLK duty delay cell = 0
6994 13:31:16.946640 [0] MAX Duty = 5156%(X100), DQS PI = 24
6995 13:31:16.950493 [0] MIN Duty = 4938%(X100), DQS PI = 38
6996 13:31:16.953292 [0] AVG Duty = 5047%(X100)
6997 13:31:16.953641
6998 13:31:16.956545 CH0 CLK Duty spec in!! Max-Min= 218%
6999 13:31:16.959812 [DutyScan_Calibration_Flow] ====Done====
7000 13:31:16.960321
7001 13:31:16.963337 [DutyScan_Calibration_Flow] k_type=1
7002 13:31:16.980257
7003 13:31:16.980787 ==DQS 0 ==
7004 13:31:16.983345 Final DQS duty delay cell = 0
7005 13:31:16.986986 [0] MAX Duty = 5125%(X100), DQS PI = 34
7006 13:31:16.990084 [0] MIN Duty = 5031%(X100), DQS PI = 8
7007 13:31:16.993270 [0] AVG Duty = 5078%(X100)
7008 13:31:16.993640
7009 13:31:16.993994 ==DQS 1 ==
7010 13:31:16.996605 Final DQS duty delay cell = 0
7011 13:31:17.000025 [0] MAX Duty = 5031%(X100), DQS PI = 6
7012 13:31:17.003545 [0] MIN Duty = 4875%(X100), DQS PI = 18
7013 13:31:17.006586 [0] AVG Duty = 4953%(X100)
7014 13:31:17.007086
7015 13:31:17.010184 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7016 13:31:17.010718
7017 13:31:17.013189 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7018 13:31:17.016648 [DutyScan_Calibration_Flow] ====Done====
7019 13:31:17.017128
7020 13:31:17.019660 [DutyScan_Calibration_Flow] k_type=3
7021 13:31:17.037429
7022 13:31:17.037943 ==DQM 0 ==
7023 13:31:17.040348 Final DQM duty delay cell = 0
7024 13:31:17.043777 [0] MAX Duty = 5187%(X100), DQS PI = 22
7025 13:31:17.046931 [0] MIN Duty = 4907%(X100), DQS PI = 42
7026 13:31:17.050507 [0] AVG Duty = 5047%(X100)
7027 13:31:17.050895
7028 13:31:17.051167 ==DQM 1 ==
7029 13:31:17.053407 Final DQM duty delay cell = 0
7030 13:31:17.056918 [0] MAX Duty = 5031%(X100), DQS PI = 52
7031 13:31:17.060519 [0] MIN Duty = 4782%(X100), DQS PI = 14
7032 13:31:17.063883 [0] AVG Duty = 4906%(X100)
7033 13:31:17.064361
7034 13:31:17.067537 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7035 13:31:17.068019
7036 13:31:17.070879 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7037 13:31:17.073818 [DutyScan_Calibration_Flow] ====Done====
7038 13:31:17.074351
7039 13:31:17.077638 [DutyScan_Calibration_Flow] k_type=2
7040 13:31:17.093584
7041 13:31:17.094278 ==DQ 0 ==
7042 13:31:17.096973 Final DQ duty delay cell = 0
7043 13:31:17.100394 [0] MAX Duty = 5218%(X100), DQS PI = 18
7044 13:31:17.103368 [0] MIN Duty = 4938%(X100), DQS PI = 56
7045 13:31:17.103812 [0] AVG Duty = 5078%(X100)
7046 13:31:17.106724
7047 13:31:17.107194 ==DQ 1 ==
7048 13:31:17.110018 Final DQ duty delay cell = -4
7049 13:31:17.113232 [-4] MAX Duty = 5094%(X100), DQS PI = 6
7050 13:31:17.116666 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7051 13:31:17.120334 [-4] AVG Duty = 4969%(X100)
7052 13:31:17.120788
7053 13:31:17.123699 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7054 13:31:17.124188
7055 13:31:17.126492 CH0 DQ 1 Duty spec in!! Max-Min= 250%
7056 13:31:17.129802 [DutyScan_Calibration_Flow] ====Done====
7057 13:31:17.130166 ==
7058 13:31:17.133435 Dram Type= 6, Freq= 0, CH_1, rank 0
7059 13:31:17.136229 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7060 13:31:17.136633 ==
7061 13:31:17.139724 [Duty_Offset_Calibration]
7062 13:31:17.140204 B0:0 B1:4 CA:-5
7063 13:31:17.140534
7064 13:31:17.143335 [DutyScan_Calibration_Flow] k_type=0
7065 13:31:17.154273
7066 13:31:17.154748 ==CLK 0==
7067 13:31:17.157801 Final CLK duty delay cell = 0
7068 13:31:17.160899 [0] MAX Duty = 5125%(X100), DQS PI = 44
7069 13:31:17.164459 [0] MIN Duty = 4907%(X100), DQS PI = 16
7070 13:31:17.167502 [0] AVG Duty = 5016%(X100)
7071 13:31:17.168007
7072 13:31:17.170741 CH1 CLK Duty spec in!! Max-Min= 218%
7073 13:31:17.174392 [DutyScan_Calibration_Flow] ====Done====
7074 13:31:17.174764
7075 13:31:17.177914 [DutyScan_Calibration_Flow] k_type=1
7076 13:31:17.192965
7077 13:31:17.193442 ==DQS 0 ==
7078 13:31:17.196102 Final DQS duty delay cell = 0
7079 13:31:17.199373 [0] MAX Duty = 5124%(X100), DQS PI = 46
7080 13:31:17.202805 [0] MIN Duty = 4875%(X100), DQS PI = 12
7081 13:31:17.206545 [0] AVG Duty = 4999%(X100)
7082 13:31:17.206993
7083 13:31:17.207263 ==DQS 1 ==
7084 13:31:17.209181 Final DQS duty delay cell = -4
7085 13:31:17.212630 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7086 13:31:17.216202 [-4] MIN Duty = 4875%(X100), DQS PI = 10
7087 13:31:17.219224 [-4] AVG Duty = 4922%(X100)
7088 13:31:17.219695
7089 13:31:17.223342 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7090 13:31:17.223863
7091 13:31:17.226116 CH1 DQS 1 Duty spec in!! Max-Min= 94%
7092 13:31:17.229707 [DutyScan_Calibration_Flow] ====Done====
7093 13:31:17.230210
7094 13:31:17.232674 [DutyScan_Calibration_Flow] k_type=3
7095 13:31:17.249009
7096 13:31:17.249468 ==DQM 0 ==
7097 13:31:17.251902 Final DQM duty delay cell = -4
7098 13:31:17.255297 [-4] MAX Duty = 5031%(X100), DQS PI = 2
7099 13:31:17.258590 [-4] MIN Duty = 4782%(X100), DQS PI = 12
7100 13:31:17.262123 [-4] AVG Duty = 4906%(X100)
7101 13:31:17.262573
7102 13:31:17.262847 ==DQM 1 ==
7103 13:31:17.265026 Final DQM duty delay cell = -4
7104 13:31:17.268719 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7105 13:31:17.271618 [-4] MIN Duty = 4907%(X100), DQS PI = 4
7106 13:31:17.275218 [-4] AVG Duty = 4984%(X100)
7107 13:31:17.275566
7108 13:31:17.278621 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7109 13:31:17.278965
7110 13:31:17.281460 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7111 13:31:17.284863 [DutyScan_Calibration_Flow] ====Done====
7112 13:31:17.285210
7113 13:31:17.288400 [DutyScan_Calibration_Flow] k_type=2
7114 13:31:17.306161
7115 13:31:17.306616 ==DQ 0 ==
7116 13:31:17.309251 Final DQ duty delay cell = 0
7117 13:31:17.312824 [0] MAX Duty = 5093%(X100), DQS PI = 24
7118 13:31:17.315904 [0] MIN Duty = 4969%(X100), DQS PI = 12
7119 13:31:17.316399 [0] AVG Duty = 5031%(X100)
7120 13:31:17.319107
7121 13:31:17.319500 ==DQ 1 ==
7122 13:31:17.322269 Final DQ duty delay cell = 0
7123 13:31:17.326176 [0] MAX Duty = 5062%(X100), DQS PI = 22
7124 13:31:17.328907 [0] MIN Duty = 4844%(X100), DQS PI = 56
7125 13:31:17.329270 [0] AVG Duty = 4953%(X100)
7126 13:31:17.332255
7127 13:31:17.336013 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7128 13:31:17.336474
7129 13:31:17.339000 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7130 13:31:17.342430 [DutyScan_Calibration_Flow] ====Done====
7131 13:31:17.345718 nWR fixed to 30
7132 13:31:17.346175 [ModeRegInit_LP4] CH0 RK0
7133 13:31:17.348757 [ModeRegInit_LP4] CH0 RK1
7134 13:31:17.352764 [ModeRegInit_LP4] CH1 RK0
7135 13:31:17.355621 [ModeRegInit_LP4] CH1 RK1
7136 13:31:17.356080 match AC timing 4
7137 13:31:17.362363 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7138 13:31:17.365995 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7139 13:31:17.369055 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7140 13:31:17.375832 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7141 13:31:17.378529 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7142 13:31:17.378922 [MiockJmeterHQA]
7143 13:31:17.379253
7144 13:31:17.382061 [DramcMiockJmeter] u1RxGatingPI = 0
7145 13:31:17.385311 0 : 4257, 4030
7146 13:31:17.385707 4 : 4258, 4031
7147 13:31:17.388627 8 : 4257, 4030
7148 13:31:17.388984 12 : 4257, 4030
7149 13:31:17.389269 16 : 4368, 4140
7150 13:31:17.392000 20 : 4255, 4027
7151 13:31:17.392458 24 : 4258, 4029
7152 13:31:17.395229 28 : 4368, 4140
7153 13:31:17.395594 32 : 4368, 4140
7154 13:31:17.398902 36 : 4371, 4140
7155 13:31:17.399405 40 : 4255, 4027
7156 13:31:17.402055 44 : 4259, 4031
7157 13:31:17.402526 48 : 4255, 4027
7158 13:31:17.402878 52 : 4255, 4027
7159 13:31:17.405111 56 : 4257, 4029
7160 13:31:17.405484 60 : 4257, 4029
7161 13:31:17.408748 64 : 4255, 4026
7162 13:31:17.409107 68 : 4258, 4029
7163 13:31:17.411696 72 : 4364, 4138
7164 13:31:17.412052 76 : 4255, 4026
7165 13:31:17.415275 80 : 4253, 4027
7166 13:31:17.415633 84 : 4257, 4029
7167 13:31:17.415887 88 : 4255, 4029
7168 13:31:17.418505 92 : 4258, 4029
7169 13:31:17.418863 96 : 4365, 4138
7170 13:31:17.421968 100 : 4253, 2572
7171 13:31:17.422393 104 : 4258, 0
7172 13:31:17.425004 108 : 4363, 0
7173 13:31:17.425360 112 : 4255, 0
7174 13:31:17.425620 116 : 4364, 0
7175 13:31:17.428589 120 : 4252, 0
7176 13:31:17.428952 124 : 4250, 0
7177 13:31:17.432036 128 : 4252, 0
7178 13:31:17.432582 132 : 4360, 0
7179 13:31:17.432950 136 : 4250, 0
7180 13:31:17.434935 140 : 4361, 0
7181 13:31:17.435323 144 : 4360, 0
7182 13:31:17.435649 148 : 4250, 0
7183 13:31:17.438661 152 : 4250, 0
7184 13:31:17.439138 156 : 4361, 0
7185 13:31:17.441731 160 : 4250, 0
7186 13:31:17.442214 164 : 4250, 0
7187 13:31:17.442472 168 : 4361, 0
7188 13:31:17.445120 172 : 4254, 0
7189 13:31:17.445629 176 : 4258, 0
7190 13:31:17.448078 180 : 4250, 0
7191 13:31:17.448515 184 : 4253, 0
7192 13:31:17.448778 188 : 4250, 0
7193 13:31:17.451115 192 : 4250, 0
7194 13:31:17.451474 196 : 4250, 0
7195 13:31:17.454641 200 : 4252, 0
7196 13:31:17.455093 204 : 4250, 0
7197 13:31:17.455360 208 : 4361, 0
7198 13:31:17.457772 212 : 4255, 0
7199 13:31:17.458057 216 : 4250, 0
7200 13:31:17.461449 220 : 4361, 359
7201 13:31:17.461889 224 : 4253, 4011
7202 13:31:17.464743 228 : 4250, 4026
7203 13:31:17.465100 232 : 4252, 4030
7204 13:31:17.465355 236 : 4250, 4027
7205 13:31:17.468193 240 : 4250, 4027
7206 13:31:17.468666 244 : 4250, 4027
7207 13:31:17.471260 248 : 4250, 4027
7208 13:31:17.471632 252 : 4250, 4027
7209 13:31:17.474139 256 : 4361, 4138
7210 13:31:17.474490 260 : 4250, 4027
7211 13:31:17.478350 264 : 4250, 4027
7212 13:31:17.478811 268 : 4361, 4138
7213 13:31:17.480985 272 : 4253, 4029
7214 13:31:17.481334 276 : 4250, 4027
7215 13:31:17.484619 280 : 4250, 4027
7216 13:31:17.484966 284 : 4361, 4138
7217 13:31:17.487634 288 : 4250, 4026
7218 13:31:17.487983 292 : 4250, 4027
7219 13:31:17.491044 296 : 4252, 4029
7220 13:31:17.491584 300 : 4253, 4029
7221 13:31:17.494171 304 : 4253, 4029
7222 13:31:17.494795 308 : 4250, 4027
7223 13:31:17.495269 312 : 4255, 4031
7224 13:31:17.497889 316 : 4250, 4026
7225 13:31:17.498242 320 : 4250, 4027
7226 13:31:17.501090 324 : 4361, 4138
7227 13:31:17.501443 328 : 4252, 4029
7228 13:31:17.504059 332 : 4250, 4026
7229 13:31:17.504439 336 : 4360, 4048
7230 13:31:17.507348 340 : 4250, 1797
7231 13:31:17.507695
7232 13:31:17.507940 MIOCK jitter meter ch=0
7233 13:31:17.508156
7234 13:31:17.511074 1T = (340-104) = 236 dly cells
7235 13:31:17.517724 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7236 13:31:17.518107 ==
7237 13:31:17.520539 Dram Type= 6, Freq= 0, CH_0, rank 0
7238 13:31:17.524040 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7239 13:31:17.524435 ==
7240 13:31:17.530762 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7241 13:31:17.534097 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7242 13:31:17.540649 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7243 13:31:17.543839 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7244 13:31:17.553258 [CA 0] Center 42 (12~73) winsize 62
7245 13:31:17.556753 [CA 1] Center 42 (12~73) winsize 62
7246 13:31:17.560099 [CA 2] Center 39 (9~69) winsize 61
7247 13:31:17.563447 [CA 3] Center 38 (9~68) winsize 60
7248 13:31:17.566996 [CA 4] Center 36 (6~67) winsize 62
7249 13:31:17.570163 [CA 5] Center 36 (6~66) winsize 61
7250 13:31:17.570617
7251 13:31:17.573254 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7252 13:31:17.573702
7253 13:31:17.576169 [CATrainingPosCal] consider 1 rank data
7254 13:31:17.579846 u2DelayCellTimex100 = 275/100 ps
7255 13:31:17.583281 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7256 13:31:17.589896 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7257 13:31:17.592977 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7258 13:31:17.596228 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7259 13:31:17.599738 CA4 delay=36 (6~67),Diff = 0 PI (0 cell)
7260 13:31:17.603201 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7261 13:31:17.603667
7262 13:31:17.606344 CA PerBit enable=1, Macro0, CA PI delay=36
7263 13:31:17.606737
7264 13:31:17.609791 [CBTSetCACLKResult] CA Dly = 36
7265 13:31:17.612781 CS Dly: 10 (0~41)
7266 13:31:17.616330 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7267 13:31:17.620063 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7268 13:31:17.620588 ==
7269 13:31:17.622657 Dram Type= 6, Freq= 0, CH_0, rank 1
7270 13:31:17.629658 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7271 13:31:17.630013 ==
7272 13:31:17.633211 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7273 13:31:17.635928 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7274 13:31:17.643006 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7275 13:31:17.649410 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7276 13:31:17.656323 [CA 0] Center 42 (12~73) winsize 62
7277 13:31:17.659003 [CA 1] Center 42 (12~73) winsize 62
7278 13:31:17.663394 [CA 2] Center 38 (9~68) winsize 60
7279 13:31:17.666318 [CA 3] Center 38 (8~68) winsize 61
7280 13:31:17.669537 [CA 4] Center 36 (6~66) winsize 61
7281 13:31:17.673141 [CA 5] Center 36 (6~66) winsize 61
7282 13:31:17.673637
7283 13:31:17.675965 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7284 13:31:17.676720
7285 13:31:17.679536 [CATrainingPosCal] consider 2 rank data
7286 13:31:17.682855 u2DelayCellTimex100 = 275/100 ps
7287 13:31:17.685632 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7288 13:31:17.692439 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7289 13:31:17.696038 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7290 13:31:17.699176 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7291 13:31:17.702862 CA4 delay=36 (6~66),Diff = 0 PI (0 cell)
7292 13:31:17.705836 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7293 13:31:17.706234
7294 13:31:17.709214 CA PerBit enable=1, Macro0, CA PI delay=36
7295 13:31:17.709599
7296 13:31:17.712580 [CBTSetCACLKResult] CA Dly = 36
7297 13:31:17.715613 CS Dly: 10 (0~42)
7298 13:31:17.719142 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7299 13:31:17.722387 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7300 13:31:17.722801
7301 13:31:17.725488 ----->DramcWriteLeveling(PI) begin...
7302 13:31:17.725768 ==
7303 13:31:17.728936 Dram Type= 6, Freq= 0, CH_0, rank 0
7304 13:31:17.735668 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7305 13:31:17.735943 ==
7306 13:31:17.738811 Write leveling (Byte 0): 29 => 29
7307 13:31:17.739237 Write leveling (Byte 1): 24 => 24
7308 13:31:17.741923 DramcWriteLeveling(PI) end<-----
7309 13:31:17.742245
7310 13:31:17.745818 ==
7311 13:31:17.746199 Dram Type= 6, Freq= 0, CH_0, rank 0
7312 13:31:17.752013 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7313 13:31:17.752234 ==
7314 13:31:17.754816 [Gating] SW mode calibration
7315 13:31:17.761543 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7316 13:31:17.764765 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7317 13:31:17.771538 0 12 0 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
7318 13:31:17.775165 0 12 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
7319 13:31:17.778256 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7320 13:31:17.785080 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7321 13:31:17.787779 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7322 13:31:17.791936 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7323 13:31:17.798369 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7324 13:31:17.802072 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7325 13:31:17.805018 0 13 0 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
7326 13:31:17.811799 0 13 4 | B1->B0 | 3131 2424 | 1 0 | (1 0) (1 0)
7327 13:31:17.815258 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7328 13:31:17.818605 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7329 13:31:17.825327 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7330 13:31:17.828541 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7331 13:31:17.831783 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7332 13:31:17.838088 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7333 13:31:17.841640 0 14 0 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
7334 13:31:17.844798 0 14 4 | B1->B0 | 3333 4545 | 0 0 | (0 0) (0 0)
7335 13:31:17.851252 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7336 13:31:17.854812 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7337 13:31:17.858092 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7338 13:31:17.864602 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7339 13:31:17.868036 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7340 13:31:17.871065 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7341 13:31:17.874344 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7342 13:31:17.881357 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7343 13:31:17.884866 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7344 13:31:17.888065 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7345 13:31:17.895000 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7346 13:31:17.898142 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7347 13:31:17.901527 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7348 13:31:17.907857 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7349 13:31:17.910902 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7350 13:31:17.914324 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7351 13:31:17.920962 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7352 13:31:17.924215 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7353 13:31:17.927525 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7354 13:31:17.934293 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7355 13:31:17.937457 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7356 13:31:17.941001 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7357 13:31:17.947636 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7358 13:31:17.950748 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7359 13:31:17.954240 Total UI for P1: 0, mck2ui 16
7360 13:31:17.957416 best dqsien dly found for B0: ( 1, 0, 30)
7361 13:31:17.960695 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7362 13:31:17.967449 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7363 13:31:17.967884 Total UI for P1: 0, mck2ui 16
7364 13:31:17.974087 best dqsien dly found for B1: ( 1, 1, 6)
7365 13:31:17.976995 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7366 13:31:17.980790 best DQS1 dly(MCK, UI, PI) = (1, 1, 6)
7367 13:31:17.981171
7368 13:31:17.983911 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7369 13:31:17.986843 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 6)
7370 13:31:17.990230 [Gating] SW calibration Done
7371 13:31:17.990577 ==
7372 13:31:17.993932 Dram Type= 6, Freq= 0, CH_0, rank 0
7373 13:31:17.997091 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7374 13:31:17.997451 ==
7375 13:31:18.000243 RX Vref Scan: 0
7376 13:31:18.000631
7377 13:31:18.000878 RX Vref 0 -> 0, step: 1
7378 13:31:18.001093
7379 13:31:18.003737 RX Delay 0 -> 252, step: 8
7380 13:31:18.007681 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7381 13:31:18.013647 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7382 13:31:18.017276 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
7383 13:31:18.020212 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7384 13:31:18.023849 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7385 13:31:18.027003 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7386 13:31:18.033591 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7387 13:31:18.036866 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7388 13:31:18.040925 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7389 13:31:18.043930 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7390 13:31:18.047215 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7391 13:31:18.053842 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7392 13:31:18.056847 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7393 13:31:18.059799 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7394 13:31:18.063722 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7395 13:31:18.066582 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7396 13:31:18.070185 ==
7397 13:31:18.073235 Dram Type= 6, Freq= 0, CH_0, rank 0
7398 13:31:18.076660 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7399 13:31:18.077043 ==
7400 13:31:18.077327 DQS Delay:
7401 13:31:18.079707 DQS0 = 0, DQS1 = 0
7402 13:31:18.080002 DQM Delay:
7403 13:31:18.083029 DQM0 = 130, DQM1 = 124
7404 13:31:18.083374 DQ Delay:
7405 13:31:18.086444 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =127
7406 13:31:18.090153 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7407 13:31:18.092987 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
7408 13:31:18.096313 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7409 13:31:18.096736
7410 13:31:18.096984
7411 13:31:18.097203 ==
7412 13:31:18.099557 Dram Type= 6, Freq= 0, CH_0, rank 0
7413 13:31:18.106534 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7414 13:31:18.106957 ==
7415 13:31:18.107203
7416 13:31:18.107419
7417 13:31:18.110283 TX Vref Scan disable
7418 13:31:18.110741 == TX Byte 0 ==
7419 13:31:18.113055 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7420 13:31:18.119561 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7421 13:31:18.119910 == TX Byte 1 ==
7422 13:31:18.122967 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7423 13:31:18.130213 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7424 13:31:18.130671 ==
7425 13:31:18.132924 Dram Type= 6, Freq= 0, CH_0, rank 0
7426 13:31:18.136185 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7427 13:31:18.136628 ==
7428 13:31:18.149219
7429 13:31:18.152998 TX Vref early break, caculate TX vref
7430 13:31:18.156351 TX Vref=16, minBit 8, minWin=22, winSum=370
7431 13:31:18.160077 TX Vref=18, minBit 8, minWin=22, winSum=376
7432 13:31:18.162849 TX Vref=20, minBit 9, minWin=23, winSum=389
7433 13:31:18.166870 TX Vref=22, minBit 1, minWin=24, winSum=396
7434 13:31:18.169913 TX Vref=24, minBit 8, minWin=24, winSum=413
7435 13:31:18.175816 TX Vref=26, minBit 7, minWin=25, winSum=414
7436 13:31:18.179715 TX Vref=28, minBit 1, minWin=25, winSum=413
7437 13:31:18.182281 TX Vref=30, minBit 6, minWin=24, winSum=409
7438 13:31:18.186649 TX Vref=32, minBit 7, minWin=24, winSum=401
7439 13:31:18.189593 TX Vref=34, minBit 8, minWin=23, winSum=391
7440 13:31:18.195796 [TxChooseVref] Worse bit 7, Min win 25, Win sum 414, Final Vref 26
7441 13:31:18.196183
7442 13:31:18.198946 Final TX Range 0 Vref 26
7443 13:31:18.199288
7444 13:31:18.199525 ==
7445 13:31:18.203032 Dram Type= 6, Freq= 0, CH_0, rank 0
7446 13:31:18.205739 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7447 13:31:18.206172 ==
7448 13:31:18.206444
7449 13:31:18.206664
7450 13:31:18.209006 TX Vref Scan disable
7451 13:31:18.215898 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7452 13:31:18.216260 == TX Byte 0 ==
7453 13:31:18.219170 u2DelayCellOfst[0]=10 cells (3 PI)
7454 13:31:18.222674 u2DelayCellOfst[1]=17 cells (5 PI)
7455 13:31:18.225665 u2DelayCellOfst[2]=10 cells (3 PI)
7456 13:31:18.228782 u2DelayCellOfst[3]=10 cells (3 PI)
7457 13:31:18.232326 u2DelayCellOfst[4]=7 cells (2 PI)
7458 13:31:18.235548 u2DelayCellOfst[5]=0 cells (0 PI)
7459 13:31:18.238592 u2DelayCellOfst[6]=17 cells (5 PI)
7460 13:31:18.242406 u2DelayCellOfst[7]=14 cells (4 PI)
7461 13:31:18.245685 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7462 13:31:18.249025 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7463 13:31:18.251972 == TX Byte 1 ==
7464 13:31:18.255377 u2DelayCellOfst[8]=3 cells (1 PI)
7465 13:31:18.255664 u2DelayCellOfst[9]=0 cells (0 PI)
7466 13:31:18.258554 u2DelayCellOfst[10]=10 cells (3 PI)
7467 13:31:18.262236 u2DelayCellOfst[11]=7 cells (2 PI)
7468 13:31:18.265917 u2DelayCellOfst[12]=14 cells (4 PI)
7469 13:31:18.268855 u2DelayCellOfst[13]=14 cells (4 PI)
7470 13:31:18.271967 u2DelayCellOfst[14]=17 cells (5 PI)
7471 13:31:18.275009 u2DelayCellOfst[15]=14 cells (4 PI)
7472 13:31:18.278057 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
7473 13:31:18.284890 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
7474 13:31:18.285233 DramC Write-DBI on
7475 13:31:18.285476 ==
7476 13:31:18.287995 Dram Type= 6, Freq= 0, CH_0, rank 0
7477 13:31:18.294829 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7478 13:31:18.295284 ==
7479 13:31:18.295557
7480 13:31:18.295774
7481 13:31:18.295979 TX Vref Scan disable
7482 13:31:18.299034 == TX Byte 0 ==
7483 13:31:18.302452 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7484 13:31:18.305725 == TX Byte 1 ==
7485 13:31:18.308904 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
7486 13:31:18.312674 DramC Write-DBI off
7487 13:31:18.313162
7488 13:31:18.313437 [DATLAT]
7489 13:31:18.313670 Freq=1600, CH0 RK0
7490 13:31:18.313900
7491 13:31:18.315275 DATLAT Default: 0xf
7492 13:31:18.315653 0, 0xFFFF, sum = 0
7493 13:31:18.319139 1, 0xFFFF, sum = 0
7494 13:31:18.322119 2, 0xFFFF, sum = 0
7495 13:31:18.322510 3, 0xFFFF, sum = 0
7496 13:31:18.325704 4, 0xFFFF, sum = 0
7497 13:31:18.326187 5, 0xFFFF, sum = 0
7498 13:31:18.328719 6, 0xFFFF, sum = 0
7499 13:31:18.329099 7, 0xFFFF, sum = 0
7500 13:31:18.332226 8, 0xFFFF, sum = 0
7501 13:31:18.332599 9, 0xFFFF, sum = 0
7502 13:31:18.335849 10, 0xFFFF, sum = 0
7503 13:31:18.336340 11, 0xFFFF, sum = 0
7504 13:31:18.338554 12, 0x8FFF, sum = 0
7505 13:31:18.338901 13, 0x0, sum = 1
7506 13:31:18.342402 14, 0x0, sum = 2
7507 13:31:18.342918 15, 0x0, sum = 3
7508 13:31:18.345411 16, 0x0, sum = 4
7509 13:31:18.345766 best_step = 14
7510 13:31:18.346011
7511 13:31:18.346224 ==
7512 13:31:18.348539 Dram Type= 6, Freq= 0, CH_0, rank 0
7513 13:31:18.351801 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7514 13:31:18.355695 ==
7515 13:31:18.356155 RX Vref Scan: 1
7516 13:31:18.356442
7517 13:31:18.358734 Set Vref Range= 24 -> 127
7518 13:31:18.358998
7519 13:31:18.361815 RX Vref 24 -> 127, step: 1
7520 13:31:18.362271
7521 13:31:18.362546 RX Delay 11 -> 252, step: 4
7522 13:31:18.362772
7523 13:31:18.365352 Set Vref, RX VrefLevel [Byte0]: 24
7524 13:31:18.368385 [Byte1]: 24
7525 13:31:18.372452
7526 13:31:18.372934 Set Vref, RX VrefLevel [Byte0]: 25
7527 13:31:18.376015 [Byte1]: 25
7528 13:31:18.380168
7529 13:31:18.380833 Set Vref, RX VrefLevel [Byte0]: 26
7530 13:31:18.383566 [Byte1]: 26
7531 13:31:18.387670
7532 13:31:18.388160 Set Vref, RX VrefLevel [Byte0]: 27
7533 13:31:18.391039 [Byte1]: 27
7534 13:31:18.395439
7535 13:31:18.395927 Set Vref, RX VrefLevel [Byte0]: 28
7536 13:31:18.398543 [Byte1]: 28
7537 13:31:18.402895
7538 13:31:18.403478 Set Vref, RX VrefLevel [Byte0]: 29
7539 13:31:18.405812 [Byte1]: 29
7540 13:31:18.410277
7541 13:31:18.410654 Set Vref, RX VrefLevel [Byte0]: 30
7542 13:31:18.413632 [Byte1]: 30
7543 13:31:18.418528
7544 13:31:18.419027 Set Vref, RX VrefLevel [Byte0]: 31
7545 13:31:18.421039 [Byte1]: 31
7546 13:31:18.425704
7547 13:31:18.426174 Set Vref, RX VrefLevel [Byte0]: 32
7548 13:31:18.428808 [Byte1]: 32
7549 13:31:18.433167
7550 13:31:18.433616 Set Vref, RX VrefLevel [Byte0]: 33
7551 13:31:18.436506 [Byte1]: 33
7552 13:31:18.440791
7553 13:31:18.441135 Set Vref, RX VrefLevel [Byte0]: 34
7554 13:31:18.444233 [Byte1]: 34
7555 13:31:18.448737
7556 13:31:18.449187 Set Vref, RX VrefLevel [Byte0]: 35
7557 13:31:18.451840 [Byte1]: 35
7558 13:31:18.455745
7559 13:31:18.456094 Set Vref, RX VrefLevel [Byte0]: 36
7560 13:31:18.459162 [Byte1]: 36
7561 13:31:18.463758
7562 13:31:18.464211 Set Vref, RX VrefLevel [Byte0]: 37
7563 13:31:18.467325 [Byte1]: 37
7564 13:31:18.471064
7565 13:31:18.471450 Set Vref, RX VrefLevel [Byte0]: 38
7566 13:31:18.474692 [Byte1]: 38
7567 13:31:18.479033
7568 13:31:18.479464 Set Vref, RX VrefLevel [Byte0]: 39
7569 13:31:18.482070 [Byte1]: 39
7570 13:31:18.486820
7571 13:31:18.487277 Set Vref, RX VrefLevel [Byte0]: 40
7572 13:31:18.490154 [Byte1]: 40
7573 13:31:18.494622
7574 13:31:18.495073 Set Vref, RX VrefLevel [Byte0]: 41
7575 13:31:18.497582 [Byte1]: 41
7576 13:31:18.501694
7577 13:31:18.502038 Set Vref, RX VrefLevel [Byte0]: 42
7578 13:31:18.505079 [Byte1]: 42
7579 13:31:18.509685
7580 13:31:18.510175 Set Vref, RX VrefLevel [Byte0]: 43
7581 13:31:18.513551 [Byte1]: 43
7582 13:31:18.517201
7583 13:31:18.517630 Set Vref, RX VrefLevel [Byte0]: 44
7584 13:31:18.520503 [Byte1]: 44
7585 13:31:18.524566
7586 13:31:18.524982 Set Vref, RX VrefLevel [Byte0]: 45
7587 13:31:18.528016 [Byte1]: 45
7588 13:31:18.532073
7589 13:31:18.532608 Set Vref, RX VrefLevel [Byte0]: 46
7590 13:31:18.535749 [Byte1]: 46
7591 13:31:18.539602
7592 13:31:18.539981 Set Vref, RX VrefLevel [Byte0]: 47
7593 13:31:18.543399 [Byte1]: 47
7594 13:31:18.547638
7595 13:31:18.548163 Set Vref, RX VrefLevel [Byte0]: 48
7596 13:31:18.550485 [Byte1]: 48
7597 13:31:18.555148
7598 13:31:18.555633 Set Vref, RX VrefLevel [Byte0]: 49
7599 13:31:18.558376 [Byte1]: 49
7600 13:31:18.562601
7601 13:31:18.563084 Set Vref, RX VrefLevel [Byte0]: 50
7602 13:31:18.566005 [Byte1]: 50
7603 13:31:18.570213
7604 13:31:18.570695 Set Vref, RX VrefLevel [Byte0]: 51
7605 13:31:18.573427 [Byte1]: 51
7606 13:31:18.577915
7607 13:31:18.578404 Set Vref, RX VrefLevel [Byte0]: 52
7608 13:31:18.581026 [Byte1]: 52
7609 13:31:18.585375
7610 13:31:18.585717 Set Vref, RX VrefLevel [Byte0]: 53
7611 13:31:18.588303 [Byte1]: 53
7612 13:31:18.593454
7613 13:31:18.593797 Set Vref, RX VrefLevel [Byte0]: 54
7614 13:31:18.596037 [Byte1]: 54
7615 13:31:18.600815
7616 13:31:18.601261 Set Vref, RX VrefLevel [Byte0]: 55
7617 13:31:18.604398 [Byte1]: 55
7618 13:31:18.608383
7619 13:31:18.608840 Set Vref, RX VrefLevel [Byte0]: 56
7620 13:31:18.611979 [Byte1]: 56
7621 13:31:18.616027
7622 13:31:18.616556 Set Vref, RX VrefLevel [Byte0]: 57
7623 13:31:18.619405 [Byte1]: 57
7624 13:31:18.623503
7625 13:31:18.623988 Set Vref, RX VrefLevel [Byte0]: 58
7626 13:31:18.627043 [Byte1]: 58
7627 13:31:18.631530
7628 13:31:18.632015 Set Vref, RX VrefLevel [Byte0]: 59
7629 13:31:18.635037 [Byte1]: 59
7630 13:31:18.638767
7631 13:31:18.639266 Set Vref, RX VrefLevel [Byte0]: 60
7632 13:31:18.642235 [Byte1]: 60
7633 13:31:18.646346
7634 13:31:18.646803 Set Vref, RX VrefLevel [Byte0]: 61
7635 13:31:18.649551 [Byte1]: 61
7636 13:31:18.654498
7637 13:31:18.654986 Set Vref, RX VrefLevel [Byte0]: 62
7638 13:31:18.657047 [Byte1]: 62
7639 13:31:18.661934
7640 13:31:18.662310 Set Vref, RX VrefLevel [Byte0]: 63
7641 13:31:18.664963 [Byte1]: 63
7642 13:31:18.669595
7643 13:31:18.670079 Set Vref, RX VrefLevel [Byte0]: 64
7644 13:31:18.672890 [Byte1]: 64
7645 13:31:18.676699
7646 13:31:18.677025 Set Vref, RX VrefLevel [Byte0]: 65
7647 13:31:18.680517 [Byte1]: 65
7648 13:31:18.684788
7649 13:31:18.685194 Set Vref, RX VrefLevel [Byte0]: 66
7650 13:31:18.687618 [Byte1]: 66
7651 13:31:18.691751
7652 13:31:18.692210 Set Vref, RX VrefLevel [Byte0]: 67
7653 13:31:18.695148 [Byte1]: 67
7654 13:31:18.699593
7655 13:31:18.700030 Set Vref, RX VrefLevel [Byte0]: 68
7656 13:31:18.703101 [Byte1]: 68
7657 13:31:18.707788
7658 13:31:18.708269 Set Vref, RX VrefLevel [Byte0]: 69
7659 13:31:18.711328 [Byte1]: 69
7660 13:31:18.714782
7661 13:31:18.715279 Set Vref, RX VrefLevel [Byte0]: 70
7662 13:31:18.718144 [Byte1]: 70
7663 13:31:18.722282
7664 13:31:18.722673 Set Vref, RX VrefLevel [Byte0]: 71
7665 13:31:18.725706 [Byte1]: 71
7666 13:31:18.729668
7667 13:31:18.733304 Set Vref, RX VrefLevel [Byte0]: 72
7668 13:31:18.736776 [Byte1]: 72
7669 13:31:18.737275
7670 13:31:18.739614 Final RX Vref Byte 0 = 53 to rank0
7671 13:31:18.743164 Final RX Vref Byte 1 = 57 to rank0
7672 13:31:18.746590 Final RX Vref Byte 0 = 53 to rank1
7673 13:31:18.749599 Final RX Vref Byte 1 = 57 to rank1==
7674 13:31:18.752925 Dram Type= 6, Freq= 0, CH_0, rank 0
7675 13:31:18.756302 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7676 13:31:18.756804 ==
7677 13:31:18.757106 DQS Delay:
7678 13:31:18.759336 DQS0 = 0, DQS1 = 0
7679 13:31:18.759627 DQM Delay:
7680 13:31:18.763128 DQM0 = 126, DQM1 = 120
7681 13:31:18.763616 DQ Delay:
7682 13:31:18.766351 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7683 13:31:18.769608 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7684 13:31:18.772787 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
7685 13:31:18.776704 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =132
7686 13:31:18.777188
7687 13:31:18.779743
7688 13:31:18.780224
7689 13:31:18.780572 [DramC_TX_OE_Calibration] TA2
7690 13:31:18.782507 Original DQ_B0 (3 6) =30, OEN = 27
7691 13:31:18.786134 Original DQ_B1 (3 6) =30, OEN = 27
7692 13:31:18.789656 24, 0x0, End_B0=24 End_B1=24
7693 13:31:18.792744 25, 0x0, End_B0=25 End_B1=25
7694 13:31:18.796172 26, 0x0, End_B0=26 End_B1=26
7695 13:31:18.796658 27, 0x0, End_B0=27 End_B1=27
7696 13:31:18.799121 28, 0x0, End_B0=28 End_B1=28
7697 13:31:18.802487 29, 0x0, End_B0=29 End_B1=29
7698 13:31:18.806181 30, 0x0, End_B0=30 End_B1=30
7699 13:31:18.809572 31, 0x4141, End_B0=30 End_B1=30
7700 13:31:18.809963 Byte0 end_step=30 best_step=27
7701 13:31:18.812966 Byte1 end_step=30 best_step=27
7702 13:31:18.815978 Byte0 TX OE(2T, 0.5T) = (3, 3)
7703 13:31:18.819236 Byte1 TX OE(2T, 0.5T) = (3, 3)
7704 13:31:18.819714
7705 13:31:18.819999
7706 13:31:18.829322 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
7707 13:31:18.829816 CH0 RK0: MR19=303, MR18=1B1B
7708 13:31:18.835883 CH0_RK0: MR19=0x303, MR18=0x1B1B, DQSOSC=396, MR23=63, INC=23, DEC=15
7709 13:31:18.836441
7710 13:31:18.839151 ----->DramcWriteLeveling(PI) begin...
7711 13:31:18.839644 ==
7712 13:31:18.842461 Dram Type= 6, Freq= 0, CH_0, rank 1
7713 13:31:18.849351 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7714 13:31:18.849848 ==
7715 13:31:18.852031 Write leveling (Byte 0): 29 => 29
7716 13:31:18.852418 Write leveling (Byte 1): 26 => 26
7717 13:31:18.855708 DramcWriteLeveling(PI) end<-----
7718 13:31:18.856234
7719 13:31:18.859173 ==
7720 13:31:18.859665 Dram Type= 6, Freq= 0, CH_0, rank 1
7721 13:31:18.865455 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7722 13:31:18.865844 ==
7723 13:31:18.869007 [Gating] SW mode calibration
7724 13:31:18.875473 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7725 13:31:18.878703 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7726 13:31:18.885514 0 12 0 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
7727 13:31:18.888181 0 12 4 | B1->B0 | 2525 3434 | 1 1 | (1 1) (1 1)
7728 13:31:18.891846 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7729 13:31:18.898662 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7730 13:31:18.901862 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7731 13:31:18.905011 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7732 13:31:18.911840 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7733 13:31:18.915130 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7734 13:31:18.918508 0 13 0 | B1->B0 | 3434 2929 | 1 0 | (1 0) (1 0)
7735 13:31:18.925005 0 13 4 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
7736 13:31:18.928461 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7737 13:31:18.931502 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7738 13:31:18.938773 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7739 13:31:18.941360 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7740 13:31:18.944855 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7741 13:31:18.951856 0 13 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7742 13:31:18.954716 0 14 0 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
7743 13:31:18.958259 0 14 4 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
7744 13:31:18.964807 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7745 13:31:18.967618 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7746 13:31:18.971138 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7747 13:31:18.978041 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7748 13:31:18.980801 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7749 13:31:18.983921 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7750 13:31:18.990731 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7751 13:31:18.994354 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7752 13:31:18.997380 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7753 13:31:19.004142 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7754 13:31:19.007830 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7755 13:31:19.011088 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7756 13:31:19.017934 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7757 13:31:19.021067 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7758 13:31:19.023904 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7759 13:31:19.030520 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7760 13:31:19.034200 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7761 13:31:19.037263 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7762 13:31:19.044030 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7763 13:31:19.047798 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7764 13:31:19.050721 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7765 13:31:19.057209 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7766 13:31:19.060625 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7767 13:31:19.063710 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7768 13:31:19.070430 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7769 13:31:19.070924 Total UI for P1: 0, mck2ui 16
7770 13:31:19.073609 best dqsien dly found for B0: ( 1, 1, 0)
7771 13:31:19.076982 Total UI for P1: 0, mck2ui 16
7772 13:31:19.080045 best dqsien dly found for B1: ( 1, 1, 4)
7773 13:31:19.083150 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7774 13:31:19.090216 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7775 13:31:19.090705
7776 13:31:19.093369 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7777 13:31:19.096781 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7778 13:31:19.100093 [Gating] SW calibration Done
7779 13:31:19.100677 ==
7780 13:31:19.103891 Dram Type= 6, Freq= 0, CH_0, rank 1
7781 13:31:19.107031 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7782 13:31:19.107522 ==
7783 13:31:19.107804 RX Vref Scan: 0
7784 13:31:19.110024
7785 13:31:19.110504 RX Vref 0 -> 0, step: 1
7786 13:31:19.110867
7787 13:31:19.113226 RX Delay 0 -> 252, step: 8
7788 13:31:19.116654 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7789 13:31:19.120035 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7790 13:31:19.126630 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7791 13:31:19.129452 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7792 13:31:19.133093 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7793 13:31:19.136234 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7794 13:31:19.139815 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7795 13:31:19.146266 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7796 13:31:19.149392 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7797 13:31:19.152735 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7798 13:31:19.155978 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7799 13:31:19.158973 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
7800 13:31:19.166462 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7801 13:31:19.169551 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7802 13:31:19.172293 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7803 13:31:19.175485 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7804 13:31:19.175605 ==
7805 13:31:19.179000 Dram Type= 6, Freq= 0, CH_0, rank 1
7806 13:31:19.185711 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7807 13:31:19.185874 ==
7808 13:31:19.185951 DQS Delay:
7809 13:31:19.188946 DQS0 = 0, DQS1 = 0
7810 13:31:19.189011 DQM Delay:
7811 13:31:19.192133 DQM0 = 130, DQM1 = 124
7812 13:31:19.192195 DQ Delay:
7813 13:31:19.195713 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =123
7814 13:31:19.198748 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7815 13:31:19.201857 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7816 13:31:19.205316 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7817 13:31:19.205371
7818 13:31:19.205417
7819 13:31:19.205461 ==
7820 13:31:19.208503 Dram Type= 6, Freq= 0, CH_0, rank 1
7821 13:31:19.215028 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7822 13:31:19.215086 ==
7823 13:31:19.215132
7824 13:31:19.215174
7825 13:31:19.215216 TX Vref Scan disable
7826 13:31:19.218622 == TX Byte 0 ==
7827 13:31:19.222228 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7828 13:31:19.228510 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7829 13:31:19.228568 == TX Byte 1 ==
7830 13:31:19.232910 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7831 13:31:19.239307 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7832 13:31:19.239774 ==
7833 13:31:19.242282 Dram Type= 6, Freq= 0, CH_0, rank 1
7834 13:31:19.245752 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7835 13:31:19.246213 ==
7836 13:31:19.259368
7837 13:31:19.262127 TX Vref early break, caculate TX vref
7838 13:31:19.265932 TX Vref=16, minBit 1, minWin=22, winSum=371
7839 13:31:19.269470 TX Vref=18, minBit 1, minWin=23, winSum=383
7840 13:31:19.272947 TX Vref=20, minBit 9, minWin=23, winSum=394
7841 13:31:19.276232 TX Vref=22, minBit 1, minWin=24, winSum=396
7842 13:31:19.279159 TX Vref=24, minBit 8, minWin=24, winSum=402
7843 13:31:19.286162 TX Vref=26, minBit 1, minWin=24, winSum=411
7844 13:31:19.288937 TX Vref=28, minBit 8, minWin=24, winSum=413
7845 13:31:19.292636 TX Vref=30, minBit 8, minWin=24, winSum=410
7846 13:31:19.296000 TX Vref=32, minBit 8, minWin=24, winSum=403
7847 13:31:19.299667 TX Vref=34, minBit 0, minWin=24, winSum=397
7848 13:31:19.302844 TX Vref=36, minBit 8, minWin=22, winSum=387
7849 13:31:19.309087 [TxChooseVref] Worse bit 8, Min win 24, Win sum 413, Final Vref 28
7850 13:31:19.309577
7851 13:31:19.313107 Final TX Range 0 Vref 28
7852 13:31:19.313593
7853 13:31:19.313868 ==
7854 13:31:19.316024 Dram Type= 6, Freq= 0, CH_0, rank 1
7855 13:31:19.319131 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7856 13:31:19.319624 ==
7857 13:31:19.319911
7858 13:31:19.320153
7859 13:31:19.322313 TX Vref Scan disable
7860 13:31:19.328821 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7861 13:31:19.329284 == TX Byte 0 ==
7862 13:31:19.331818 u2DelayCellOfst[0]=14 cells (4 PI)
7863 13:31:19.335555 u2DelayCellOfst[1]=17 cells (5 PI)
7864 13:31:19.338878 u2DelayCellOfst[2]=14 cells (4 PI)
7865 13:31:19.342329 u2DelayCellOfst[3]=14 cells (4 PI)
7866 13:31:19.346222 u2DelayCellOfst[4]=10 cells (3 PI)
7867 13:31:19.348660 u2DelayCellOfst[5]=0 cells (0 PI)
7868 13:31:19.351987 u2DelayCellOfst[6]=17 cells (5 PI)
7869 13:31:19.355259 u2DelayCellOfst[7]=17 cells (5 PI)
7870 13:31:19.358376 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7871 13:31:19.361608 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7872 13:31:19.365127 == TX Byte 1 ==
7873 13:31:19.368648 u2DelayCellOfst[8]=3 cells (1 PI)
7874 13:31:19.371926 u2DelayCellOfst[9]=0 cells (0 PI)
7875 13:31:19.375319 u2DelayCellOfst[10]=14 cells (4 PI)
7876 13:31:19.375593 u2DelayCellOfst[11]=7 cells (2 PI)
7877 13:31:19.378866 u2DelayCellOfst[12]=17 cells (5 PI)
7878 13:31:19.381911 u2DelayCellOfst[13]=17 cells (5 PI)
7879 13:31:19.385651 u2DelayCellOfst[14]=21 cells (6 PI)
7880 13:31:19.388366 u2DelayCellOfst[15]=17 cells (5 PI)
7881 13:31:19.395450 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7882 13:31:19.398598 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7883 13:31:19.398959 DramC Write-DBI on
7884 13:31:19.399206 ==
7885 13:31:19.401914 Dram Type= 6, Freq= 0, CH_0, rank 1
7886 13:31:19.408308 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7887 13:31:19.408664 ==
7888 13:31:19.408908
7889 13:31:19.409122
7890 13:31:19.409326 TX Vref Scan disable
7891 13:31:19.412894 == TX Byte 0 ==
7892 13:31:19.415910 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7893 13:31:19.419461 == TX Byte 1 ==
7894 13:31:19.422805 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7895 13:31:19.425676 DramC Write-DBI off
7896 13:31:19.426036
7897 13:31:19.426281 [DATLAT]
7898 13:31:19.426502 Freq=1600, CH0 RK1
7899 13:31:19.426744
7900 13:31:19.429499 DATLAT Default: 0xe
7901 13:31:19.429959 0, 0xFFFF, sum = 0
7902 13:31:19.432731 1, 0xFFFF, sum = 0
7903 13:31:19.436010 2, 0xFFFF, sum = 0
7904 13:31:19.436542 3, 0xFFFF, sum = 0
7905 13:31:19.439347 4, 0xFFFF, sum = 0
7906 13:31:19.439735 5, 0xFFFF, sum = 0
7907 13:31:19.442384 6, 0xFFFF, sum = 0
7908 13:31:19.442767 7, 0xFFFF, sum = 0
7909 13:31:19.445423 8, 0xFFFF, sum = 0
7910 13:31:19.445797 9, 0xFFFF, sum = 0
7911 13:31:19.449054 10, 0xFFFF, sum = 0
7912 13:31:19.449407 11, 0xFFFF, sum = 0
7913 13:31:19.452165 12, 0x8FFF, sum = 0
7914 13:31:19.452590 13, 0x0, sum = 1
7915 13:31:19.455571 14, 0x0, sum = 2
7916 13:31:19.455985 15, 0x0, sum = 3
7917 13:31:19.459027 16, 0x0, sum = 4
7918 13:31:19.459462 best_step = 14
7919 13:31:19.459731
7920 13:31:19.459954 ==
7921 13:31:19.462362 Dram Type= 6, Freq= 0, CH_0, rank 1
7922 13:31:19.465841 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7923 13:31:19.468727 ==
7924 13:31:19.469075 RX Vref Scan: 0
7925 13:31:19.469320
7926 13:31:19.472810 RX Vref 0 -> 0, step: 1
7927 13:31:19.473272
7928 13:31:19.475152 RX Delay 11 -> 252, step: 4
7929 13:31:19.479361 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7930 13:31:19.482494 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7931 13:31:19.485641 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7932 13:31:19.492171 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
7933 13:31:19.495450 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7934 13:31:19.498656 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
7935 13:31:19.502198 iDelay=195, Bit 6, Center 136 (79 ~ 194) 116
7936 13:31:19.505770 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7937 13:31:19.511953 iDelay=195, Bit 8, Center 106 (51 ~ 162) 112
7938 13:31:19.515473 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7939 13:31:19.518558 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7940 13:31:19.521750 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7941 13:31:19.525516 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7942 13:31:19.531892 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
7943 13:31:19.535093 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
7944 13:31:19.538573 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7945 13:31:19.539064 ==
7946 13:31:19.541907 Dram Type= 6, Freq= 0, CH_0, rank 1
7947 13:31:19.545154 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7948 13:31:19.545643 ==
7949 13:31:19.548483 DQS Delay:
7950 13:31:19.548968 DQS0 = 0, DQS1 = 0
7951 13:31:19.551679 DQM Delay:
7952 13:31:19.552145 DQM0 = 128, DQM1 = 120
7953 13:31:19.555032 DQ Delay:
7954 13:31:19.558557 DQ0 =122, DQ1 =132, DQ2 =126, DQ3 =122
7955 13:31:19.561946 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =138
7956 13:31:19.564782 DQ8 =106, DQ9 =106, DQ10 =122, DQ11 =112
7957 13:31:19.568246 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =130
7958 13:31:19.568929
7959 13:31:19.569232
7960 13:31:19.569472
7961 13:31:19.571741 [DramC_TX_OE_Calibration] TA2
7962 13:31:19.575230 Original DQ_B0 (3 6) =30, OEN = 27
7963 13:31:19.578368 Original DQ_B1 (3 6) =30, OEN = 27
7964 13:31:19.578865 24, 0x0, End_B0=24 End_B1=24
7965 13:31:19.582103 25, 0x0, End_B0=25 End_B1=25
7966 13:31:19.584686 26, 0x0, End_B0=26 End_B1=26
7967 13:31:19.588221 27, 0x0, End_B0=27 End_B1=27
7968 13:31:19.591452 28, 0x0, End_B0=28 End_B1=28
7969 13:31:19.591940 29, 0x0, End_B0=29 End_B1=29
7970 13:31:19.595370 30, 0x0, End_B0=30 End_B1=30
7971 13:31:19.598458 31, 0x4141, End_B0=30 End_B1=30
7972 13:31:19.601521 Byte0 end_step=30 best_step=27
7973 13:31:19.604967 Byte1 end_step=30 best_step=27
7974 13:31:19.608200 Byte0 TX OE(2T, 0.5T) = (3, 3)
7975 13:31:19.608635 Byte1 TX OE(2T, 0.5T) = (3, 3)
7976 13:31:19.608911
7977 13:31:19.609148
7978 13:31:19.617836 [DQSOSCAuto] RK1, (LSB)MR18= 0x2222, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
7979 13:31:19.622041 CH0 RK1: MR19=303, MR18=2222
7980 13:31:19.628093 CH0_RK1: MR19=0x303, MR18=0x2222, DQSOSC=392, MR23=63, INC=24, DEC=16
7981 13:31:19.628601 [RxdqsGatingPostProcess] freq 1600
7982 13:31:19.635171 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7983 13:31:19.638123 Pre-setting of DQS Precalculation
7984 13:31:19.644544 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7985 13:31:19.645011 ==
7986 13:31:19.648206 Dram Type= 6, Freq= 0, CH_1, rank 0
7987 13:31:19.651347 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7988 13:31:19.651833 ==
7989 13:31:19.657717 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7990 13:31:19.661443 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
7991 13:31:19.664427 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
7992 13:31:19.671230 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7993 13:31:19.678807 [CA 0] Center 41 (11~71) winsize 61
7994 13:31:19.681957 [CA 1] Center 40 (10~71) winsize 62
7995 13:31:19.684922 [CA 2] Center 36 (7~66) winsize 60
7996 13:31:19.688260 [CA 3] Center 36 (7~65) winsize 59
7997 13:31:19.691746 [CA 4] Center 33 (4~63) winsize 60
7998 13:31:19.695027 [CA 5] Center 33 (4~63) winsize 60
7999 13:31:19.695414
8000 13:31:19.698486 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8001 13:31:19.698836
8002 13:31:19.701761 [CATrainingPosCal] consider 1 rank data
8003 13:31:19.704913 u2DelayCellTimex100 = 275/100 ps
8004 13:31:19.708528 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8005 13:31:19.714782 CA1 delay=40 (10~71),Diff = 7 PI (24 cell)
8006 13:31:19.718734 CA2 delay=36 (7~66),Diff = 3 PI (10 cell)
8007 13:31:19.721830 CA3 delay=36 (7~65),Diff = 3 PI (10 cell)
8008 13:31:19.725345 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8009 13:31:19.728307 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8010 13:31:19.728775
8011 13:31:19.731630 CA PerBit enable=1, Macro0, CA PI delay=33
8012 13:31:19.732118
8013 13:31:19.735126 [CBTSetCACLKResult] CA Dly = 33
8014 13:31:19.738568 CS Dly: 8 (0~39)
8015 13:31:19.742128 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8016 13:31:19.745105 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8017 13:31:19.745552 ==
8018 13:31:19.748307 Dram Type= 6, Freq= 0, CH_1, rank 1
8019 13:31:19.751771 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8020 13:31:19.754939 ==
8021 13:31:19.758366 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8022 13:31:19.761435 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8023 13:31:19.768332 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8024 13:31:19.775050 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8025 13:31:19.781135 [CA 0] Center 41 (11~71) winsize 61
8026 13:31:19.784432 [CA 1] Center 41 (11~72) winsize 62
8027 13:31:19.787506 [CA 2] Center 36 (7~66) winsize 60
8028 13:31:19.791058 [CA 3] Center 36 (7~65) winsize 59
8029 13:31:19.794361 [CA 4] Center 34 (5~64) winsize 60
8030 13:31:19.798237 [CA 5] Center 34 (4~64) winsize 61
8031 13:31:19.798726
8032 13:31:19.801492 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8033 13:31:19.801890
8034 13:31:19.804518 [CATrainingPosCal] consider 2 rank data
8035 13:31:19.808362 u2DelayCellTimex100 = 275/100 ps
8036 13:31:19.811650 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8037 13:31:19.817626 CA1 delay=41 (11~71),Diff = 8 PI (28 cell)
8038 13:31:19.821101 CA2 delay=36 (7~66),Diff = 3 PI (10 cell)
8039 13:31:19.824338 CA3 delay=36 (7~65),Diff = 3 PI (10 cell)
8040 13:31:19.827922 CA4 delay=34 (5~63),Diff = 1 PI (3 cell)
8041 13:31:19.831029 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8042 13:31:19.831418
8043 13:31:19.834382 CA PerBit enable=1, Macro0, CA PI delay=33
8044 13:31:19.834872
8045 13:31:19.838104 [CBTSetCACLKResult] CA Dly = 33
8046 13:31:19.841089 CS Dly: 9 (0~41)
8047 13:31:19.844821 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8048 13:31:19.847642 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8049 13:31:19.848130
8050 13:31:19.851465 ----->DramcWriteLeveling(PI) begin...
8051 13:31:19.851955 ==
8052 13:31:19.854195 Dram Type= 6, Freq= 0, CH_1, rank 0
8053 13:31:19.861613 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8054 13:31:19.862095 ==
8055 13:31:19.864148 Write leveling (Byte 0): 22 => 22
8056 13:31:19.864558 Write leveling (Byte 1): 21 => 21
8057 13:31:19.867613 DramcWriteLeveling(PI) end<-----
8058 13:31:19.867996
8059 13:31:19.868266 ==
8060 13:31:19.870852 Dram Type= 6, Freq= 0, CH_1, rank 0
8061 13:31:19.877405 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8062 13:31:19.877862 ==
8063 13:31:19.880893 [Gating] SW mode calibration
8064 13:31:19.887093 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8065 13:31:19.890753 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8066 13:31:19.897559 0 12 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8067 13:31:19.900240 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8068 13:31:19.903795 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 13:31:19.910534 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8070 13:31:19.913986 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8071 13:31:19.917310 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8072 13:31:19.923949 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8073 13:31:19.926818 0 12 28 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
8074 13:31:19.930404 0 13 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
8075 13:31:19.937185 0 13 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8076 13:31:19.940392 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8077 13:31:19.943682 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 13:31:19.950518 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8079 13:31:19.953398 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8080 13:31:19.957397 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8081 13:31:19.963634 0 13 28 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
8082 13:31:19.967009 0 14 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
8083 13:31:19.971065 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8084 13:31:19.976832 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 13:31:19.980212 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 13:31:19.983270 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 13:31:19.986630 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 13:31:19.993578 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8089 13:31:19.996260 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8090 13:31:20.000036 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8091 13:31:20.006788 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 13:31:20.010085 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 13:31:20.013036 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 13:31:20.019883 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 13:31:20.022847 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 13:31:20.025672 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 13:31:20.032427 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 13:31:20.036348 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 13:31:20.039716 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 13:31:20.046223 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 13:31:20.049885 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 13:31:20.053282 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 13:31:20.059386 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 13:31:20.063166 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8105 13:31:20.066265 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8106 13:31:20.073094 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8107 13:31:20.076038 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8108 13:31:20.079895 Total UI for P1: 0, mck2ui 16
8109 13:31:20.082740 best dqsien dly found for B0: ( 1, 0, 28)
8110 13:31:20.086119 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8111 13:31:20.089116 Total UI for P1: 0, mck2ui 16
8112 13:31:20.092141 best dqsien dly found for B1: ( 1, 1, 2)
8113 13:31:20.095883 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
8114 13:31:20.100145 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8115 13:31:20.100768
8116 13:31:20.106322 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
8117 13:31:20.109474 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8118 13:31:20.109854 [Gating] SW calibration Done
8119 13:31:20.112553 ==
8120 13:31:20.115740 Dram Type= 6, Freq= 0, CH_1, rank 0
8121 13:31:20.119234 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8122 13:31:20.119697 ==
8123 13:31:20.120020 RX Vref Scan: 0
8124 13:31:20.120402
8125 13:31:20.123052 RX Vref 0 -> 0, step: 1
8126 13:31:20.123506
8127 13:31:20.125916 RX Delay 0 -> 252, step: 8
8128 13:31:20.129081 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8129 13:31:20.132805 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8130 13:31:20.135764 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8131 13:31:20.142110 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8132 13:31:20.145454 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8133 13:31:20.148692 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8134 13:31:20.152165 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8135 13:31:20.155389 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8136 13:31:20.162326 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8137 13:31:20.164953 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8138 13:31:20.168433 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8139 13:31:20.171756 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8140 13:31:20.175116 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8141 13:31:20.181962 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8142 13:31:20.184892 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8143 13:31:20.188252 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8144 13:31:20.188319 ==
8145 13:31:20.191718 Dram Type= 6, Freq= 0, CH_1, rank 0
8146 13:31:20.194784 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8147 13:31:20.198161 ==
8148 13:31:20.198234 DQS Delay:
8149 13:31:20.198286 DQS0 = 0, DQS1 = 0
8150 13:31:20.201566 DQM Delay:
8151 13:31:20.201631 DQM0 = 130, DQM1 = 126
8152 13:31:20.204940 DQ Delay:
8153 13:31:20.208549 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =127
8154 13:31:20.211899 DQ4 =127, DQ5 =143, DQ6 =135, DQ7 =127
8155 13:31:20.215221 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =119
8156 13:31:20.218316 DQ12 =131, DQ13 =139, DQ14 =135, DQ15 =135
8157 13:31:20.218648
8158 13:31:20.218918
8159 13:31:20.219130 ==
8160 13:31:20.222039 Dram Type= 6, Freq= 0, CH_1, rank 0
8161 13:31:20.224789 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8162 13:31:20.224876 ==
8163 13:31:20.228008
8164 13:31:20.228100
8165 13:31:20.228164 TX Vref Scan disable
8166 13:31:20.231315 == TX Byte 0 ==
8167 13:31:20.235256 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8168 13:31:20.238271 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8169 13:31:20.241296 == TX Byte 1 ==
8170 13:31:20.244518 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8171 13:31:20.247853 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8172 13:31:20.247932 ==
8173 13:31:20.251468 Dram Type= 6, Freq= 0, CH_1, rank 0
8174 13:31:20.258288 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8175 13:31:20.258638 ==
8176 13:31:20.269448
8177 13:31:20.272868 TX Vref early break, caculate TX vref
8178 13:31:20.276192 TX Vref=16, minBit 0, minWin=21, winSum=364
8179 13:31:20.279681 TX Vref=18, minBit 0, minWin=22, winSum=377
8180 13:31:20.282846 TX Vref=20, minBit 0, minWin=23, winSum=382
8181 13:31:20.286236 TX Vref=22, minBit 3, minWin=23, winSum=394
8182 13:31:20.289203 TX Vref=24, minBit 0, minWin=24, winSum=404
8183 13:31:20.296710 TX Vref=26, minBit 0, minWin=24, winSum=409
8184 13:31:20.299663 TX Vref=28, minBit 3, minWin=23, winSum=411
8185 13:31:20.302876 TX Vref=30, minBit 0, minWin=25, winSum=407
8186 13:31:20.306225 TX Vref=32, minBit 3, minWin=23, winSum=397
8187 13:31:20.309696 TX Vref=34, minBit 2, minWin=23, winSum=388
8188 13:31:20.315822 [TxChooseVref] Worse bit 0, Min win 25, Win sum 407, Final Vref 30
8189 13:31:20.316350
8190 13:31:20.319189 Final TX Range 0 Vref 30
8191 13:31:20.319568
8192 13:31:20.319831 ==
8193 13:31:20.322562 Dram Type= 6, Freq= 0, CH_1, rank 0
8194 13:31:20.325579 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8195 13:31:20.325966 ==
8196 13:31:20.326215
8197 13:31:20.326434
8198 13:31:20.328950 TX Vref Scan disable
8199 13:31:20.335643 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8200 13:31:20.335994 == TX Byte 0 ==
8201 13:31:20.339334 u2DelayCellOfst[0]=14 cells (4 PI)
8202 13:31:20.342657 u2DelayCellOfst[1]=10 cells (3 PI)
8203 13:31:20.345966 u2DelayCellOfst[2]=0 cells (0 PI)
8204 13:31:20.349248 u2DelayCellOfst[3]=7 cells (2 PI)
8205 13:31:20.352330 u2DelayCellOfst[4]=7 cells (2 PI)
8206 13:31:20.355932 u2DelayCellOfst[5]=14 cells (4 PI)
8207 13:31:20.359494 u2DelayCellOfst[6]=17 cells (5 PI)
8208 13:31:20.359949 u2DelayCellOfst[7]=7 cells (2 PI)
8209 13:31:20.365694 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8210 13:31:20.369257 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8211 13:31:20.369748 == TX Byte 1 ==
8212 13:31:20.372631 u2DelayCellOfst[8]=0 cells (0 PI)
8213 13:31:20.376032 u2DelayCellOfst[9]=7 cells (2 PI)
8214 13:31:20.379526 u2DelayCellOfst[10]=10 cells (3 PI)
8215 13:31:20.382564 u2DelayCellOfst[11]=3 cells (1 PI)
8216 13:31:20.385977 u2DelayCellOfst[12]=17 cells (5 PI)
8217 13:31:20.388931 u2DelayCellOfst[13]=21 cells (6 PI)
8218 13:31:20.392105 u2DelayCellOfst[14]=17 cells (5 PI)
8219 13:31:20.395834 u2DelayCellOfst[15]=21 cells (6 PI)
8220 13:31:20.399378 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8221 13:31:20.406024 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8222 13:31:20.406516 DramC Write-DBI on
8223 13:31:20.406798 ==
8224 13:31:20.409453 Dram Type= 6, Freq= 0, CH_1, rank 0
8225 13:31:20.412395 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8226 13:31:20.412791 ==
8227 13:31:20.415860
8228 13:31:20.416396
8229 13:31:20.416695 TX Vref Scan disable
8230 13:31:20.418787 == TX Byte 0 ==
8231 13:31:20.422379 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8232 13:31:20.425356 == TX Byte 1 ==
8233 13:31:20.428696 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8234 13:31:20.428790 DramC Write-DBI off
8235 13:31:20.432242
8236 13:31:20.432632 [DATLAT]
8237 13:31:20.432950 Freq=1600, CH1 RK0
8238 13:31:20.433231
8239 13:31:20.435574 DATLAT Default: 0xf
8240 13:31:20.436040 0, 0xFFFF, sum = 0
8241 13:31:20.438703 1, 0xFFFF, sum = 0
8242 13:31:20.439059 2, 0xFFFF, sum = 0
8243 13:31:20.442280 3, 0xFFFF, sum = 0
8244 13:31:20.446113 4, 0xFFFF, sum = 0
8245 13:31:20.446577 5, 0xFFFF, sum = 0
8246 13:31:20.448488 6, 0xFFFF, sum = 0
8247 13:31:20.448937 7, 0xFFFF, sum = 0
8248 13:31:20.452214 8, 0xFFFF, sum = 0
8249 13:31:20.452692 9, 0xFFFF, sum = 0
8250 13:31:20.455383 10, 0xFFFF, sum = 0
8251 13:31:20.455843 11, 0xFFFF, sum = 0
8252 13:31:20.458795 12, 0xFFF, sum = 0
8253 13:31:20.459288 13, 0x0, sum = 1
8254 13:31:20.462084 14, 0x0, sum = 2
8255 13:31:20.462580 15, 0x0, sum = 3
8256 13:31:20.465164 16, 0x0, sum = 4
8257 13:31:20.465555 best_step = 14
8258 13:31:20.465827
8259 13:31:20.466180 ==
8260 13:31:20.468639 Dram Type= 6, Freq= 0, CH_1, rank 0
8261 13:31:20.471913 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8262 13:31:20.472448 ==
8263 13:31:20.475111 RX Vref Scan: 1
8264 13:31:20.475501
8265 13:31:20.478788 Set Vref Range= 24 -> 127
8266 13:31:20.479277
8267 13:31:20.479554 RX Vref 24 -> 127, step: 1
8268 13:31:20.479799
8269 13:31:20.481627 RX Delay 3 -> 252, step: 4
8270 13:31:20.482009
8271 13:31:20.485159 Set Vref, RX VrefLevel [Byte0]: 24
8272 13:31:20.488559 [Byte1]: 24
8273 13:31:20.492076
8274 13:31:20.492521 Set Vref, RX VrefLevel [Byte0]: 25
8275 13:31:20.494867 [Byte1]: 25
8276 13:31:20.499664
8277 13:31:20.500120 Set Vref, RX VrefLevel [Byte0]: 26
8278 13:31:20.502925 [Byte1]: 26
8279 13:31:20.507321
8280 13:31:20.507807 Set Vref, RX VrefLevel [Byte0]: 27
8281 13:31:20.510251 [Byte1]: 27
8282 13:31:20.514727
8283 13:31:20.515075 Set Vref, RX VrefLevel [Byte0]: 28
8284 13:31:20.517950 [Byte1]: 28
8285 13:31:20.522627
8286 13:31:20.523117 Set Vref, RX VrefLevel [Byte0]: 29
8287 13:31:20.525445 [Byte1]: 29
8288 13:31:20.530391
8289 13:31:20.530902 Set Vref, RX VrefLevel [Byte0]: 30
8290 13:31:20.533071 [Byte1]: 30
8291 13:31:20.537840
8292 13:31:20.538326 Set Vref, RX VrefLevel [Byte0]: 31
8293 13:31:20.541395 [Byte1]: 31
8294 13:31:20.545759
8295 13:31:20.546241 Set Vref, RX VrefLevel [Byte0]: 32
8296 13:31:20.549074 [Byte1]: 32
8297 13:31:20.553130
8298 13:31:20.553615 Set Vref, RX VrefLevel [Byte0]: 33
8299 13:31:20.556049 [Byte1]: 33
8300 13:31:20.560635
8301 13:31:20.561014 Set Vref, RX VrefLevel [Byte0]: 34
8302 13:31:20.563634 [Byte1]: 34
8303 13:31:20.568067
8304 13:31:20.568401 Set Vref, RX VrefLevel [Byte0]: 35
8305 13:31:20.571540 [Byte1]: 35
8306 13:31:20.576466
8307 13:31:20.576917 Set Vref, RX VrefLevel [Byte0]: 36
8308 13:31:20.579457 [Byte1]: 36
8309 13:31:20.583831
8310 13:31:20.584179 Set Vref, RX VrefLevel [Byte0]: 37
8311 13:31:20.587245 [Byte1]: 37
8312 13:31:20.591076
8313 13:31:20.591191 Set Vref, RX VrefLevel [Byte0]: 38
8314 13:31:20.594350 [Byte1]: 38
8315 13:31:20.598587
8316 13:31:20.598678 Set Vref, RX VrefLevel [Byte0]: 39
8317 13:31:20.601805 [Byte1]: 39
8318 13:31:20.606174
8319 13:31:20.606249 Set Vref, RX VrefLevel [Byte0]: 40
8320 13:31:20.609966 [Byte1]: 40
8321 13:31:20.613924
8322 13:31:20.613999 Set Vref, RX VrefLevel [Byte0]: 41
8323 13:31:20.617705 [Byte1]: 41
8324 13:31:20.621832
8325 13:31:20.621907 Set Vref, RX VrefLevel [Byte0]: 42
8326 13:31:20.624619 [Byte1]: 42
8327 13:31:20.629355
8328 13:31:20.629702 Set Vref, RX VrefLevel [Byte0]: 43
8329 13:31:20.632494 [Byte1]: 43
8330 13:31:20.636770
8331 13:31:20.636842 Set Vref, RX VrefLevel [Byte0]: 44
8332 13:31:20.640022 [Byte1]: 44
8333 13:31:20.644819
8334 13:31:20.644891 Set Vref, RX VrefLevel [Byte0]: 45
8335 13:31:20.647656 [Byte1]: 45
8336 13:31:20.652325
8337 13:31:20.652413 Set Vref, RX VrefLevel [Byte0]: 46
8338 13:31:20.655230 [Byte1]: 46
8339 13:31:20.659828
8340 13:31:20.659902 Set Vref, RX VrefLevel [Byte0]: 47
8341 13:31:20.663586 [Byte1]: 47
8342 13:31:20.667848
8343 13:31:20.668223 Set Vref, RX VrefLevel [Byte0]: 48
8344 13:31:20.670856 [Byte1]: 48
8345 13:31:20.675132
8346 13:31:20.675450 Set Vref, RX VrefLevel [Byte0]: 49
8347 13:31:20.681792 [Byte1]: 49
8348 13:31:20.682110
8349 13:31:20.685035 Set Vref, RX VrefLevel [Byte0]: 50
8350 13:31:20.688095 [Byte1]: 50
8351 13:31:20.688172
8352 13:31:20.691702 Set Vref, RX VrefLevel [Byte0]: 51
8353 13:31:20.695017 [Byte1]: 51
8354 13:31:20.698129
8355 13:31:20.698203 Set Vref, RX VrefLevel [Byte0]: 52
8356 13:31:20.701469 [Byte1]: 52
8357 13:31:20.705910
8358 13:31:20.705986 Set Vref, RX VrefLevel [Byte0]: 53
8359 13:31:20.708741 [Byte1]: 53
8360 13:31:20.713414
8361 13:31:20.713494 Set Vref, RX VrefLevel [Byte0]: 54
8362 13:31:20.716931 [Byte1]: 54
8363 13:31:20.720946
8364 13:31:20.721019 Set Vref, RX VrefLevel [Byte0]: 55
8365 13:31:20.724577 [Byte1]: 55
8366 13:31:20.728584
8367 13:31:20.728660 Set Vref, RX VrefLevel [Byte0]: 56
8368 13:31:20.731893 [Byte1]: 56
8369 13:31:20.736630
8370 13:31:20.736704 Set Vref, RX VrefLevel [Byte0]: 57
8371 13:31:20.739407 [Byte1]: 57
8372 13:31:20.744168
8373 13:31:20.744243 Set Vref, RX VrefLevel [Byte0]: 58
8374 13:31:20.747326 [Byte1]: 58
8375 13:31:20.751582
8376 13:31:20.751658 Set Vref, RX VrefLevel [Byte0]: 59
8377 13:31:20.754837 [Byte1]: 59
8378 13:31:20.759673
8379 13:31:20.759748 Set Vref, RX VrefLevel [Byte0]: 60
8380 13:31:20.762449 [Byte1]: 60
8381 13:31:20.766915
8382 13:31:20.766989 Set Vref, RX VrefLevel [Byte0]: 61
8383 13:31:20.770103 [Byte1]: 61
8384 13:31:20.774504
8385 13:31:20.774591 Set Vref, RX VrefLevel [Byte0]: 62
8386 13:31:20.778054 [Byte1]: 62
8387 13:31:20.782327
8388 13:31:20.782415 Set Vref, RX VrefLevel [Byte0]: 63
8389 13:31:20.785342 [Byte1]: 63
8390 13:31:20.789916
8391 13:31:20.789993 Set Vref, RX VrefLevel [Byte0]: 64
8392 13:31:20.793046 [Byte1]: 64
8393 13:31:20.797302
8394 13:31:20.797381 Set Vref, RX VrefLevel [Byte0]: 65
8395 13:31:20.801027 [Byte1]: 65
8396 13:31:20.805487
8397 13:31:20.805561 Set Vref, RX VrefLevel [Byte0]: 66
8398 13:31:20.808190 [Byte1]: 66
8399 13:31:20.813246
8400 13:31:20.813323 Set Vref, RX VrefLevel [Byte0]: 67
8401 13:31:20.816592 [Byte1]: 67
8402 13:31:20.820136
8403 13:31:20.820212 Set Vref, RX VrefLevel [Byte0]: 68
8404 13:31:20.824486 [Byte1]: 68
8405 13:31:20.828537
8406 13:31:20.828615 Set Vref, RX VrefLevel [Byte0]: 69
8407 13:31:20.831562 [Byte1]: 69
8408 13:31:20.835939
8409 13:31:20.836016 Set Vref, RX VrefLevel [Byte0]: 70
8410 13:31:20.838984 [Byte1]: 70
8411 13:31:20.843015
8412 13:31:20.846532 Final RX Vref Byte 0 = 63 to rank0
8413 13:31:20.846609 Final RX Vref Byte 1 = 55 to rank0
8414 13:31:20.849668 Final RX Vref Byte 0 = 63 to rank1
8415 13:31:20.853229 Final RX Vref Byte 1 = 55 to rank1==
8416 13:31:20.856782 Dram Type= 6, Freq= 0, CH_1, rank 0
8417 13:31:20.863304 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8418 13:31:20.863381 ==
8419 13:31:20.863436 DQS Delay:
8420 13:31:20.866524 DQS0 = 0, DQS1 = 0
8421 13:31:20.866612 DQM Delay:
8422 13:31:20.866678 DQM0 = 128, DQM1 = 124
8423 13:31:20.870098 DQ Delay:
8424 13:31:20.873278 DQ0 =130, DQ1 =122, DQ2 =116, DQ3 =128
8425 13:31:20.876607 DQ4 =128, DQ5 =138, DQ6 =136, DQ7 =126
8426 13:31:20.880004 DQ8 =106, DQ9 =114, DQ10 =126, DQ11 =114
8427 13:31:20.883427 DQ12 =132, DQ13 =134, DQ14 =134, DQ15 =134
8428 13:31:20.883503
8429 13:31:20.883557
8430 13:31:20.883604
8431 13:31:20.886893 [DramC_TX_OE_Calibration] TA2
8432 13:31:20.890036 Original DQ_B0 (3 6) =30, OEN = 27
8433 13:31:20.893132 Original DQ_B1 (3 6) =30, OEN = 27
8434 13:31:20.896447 24, 0x0, End_B0=24 End_B1=24
8435 13:31:20.896521 25, 0x0, End_B0=25 End_B1=25
8436 13:31:20.899784 26, 0x0, End_B0=26 End_B1=26
8437 13:31:20.902999 27, 0x0, End_B0=27 End_B1=27
8438 13:31:20.906268 28, 0x0, End_B0=28 End_B1=28
8439 13:31:20.909895 29, 0x0, End_B0=29 End_B1=29
8440 13:31:20.909970 30, 0x0, End_B0=30 End_B1=30
8441 13:31:20.913084 31, 0x4141, End_B0=30 End_B1=30
8442 13:31:20.916131 Byte0 end_step=30 best_step=27
8443 13:31:20.919428 Byte1 end_step=30 best_step=27
8444 13:31:20.923270 Byte0 TX OE(2T, 0.5T) = (3, 3)
8445 13:31:20.926318 Byte1 TX OE(2T, 0.5T) = (3, 3)
8446 13:31:20.926393
8447 13:31:20.926461
8448 13:31:20.932541 [DQSOSCAuto] RK0, (LSB)MR18= 0x2525, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
8449 13:31:20.936753 CH1 RK0: MR19=303, MR18=2525
8450 13:31:20.942553 CH1_RK0: MR19=0x303, MR18=0x2525, DQSOSC=391, MR23=63, INC=24, DEC=16
8451 13:31:20.942629
8452 13:31:20.945805 ----->DramcWriteLeveling(PI) begin...
8453 13:31:20.945882 ==
8454 13:31:20.949073 Dram Type= 6, Freq= 0, CH_1, rank 1
8455 13:31:20.952547 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8456 13:31:20.952626 ==
8457 13:31:20.955699 Write leveling (Byte 0): 22 => 22
8458 13:31:20.958978 Write leveling (Byte 1): 22 => 22
8459 13:31:20.962215 DramcWriteLeveling(PI) end<-----
8460 13:31:20.962291
8461 13:31:20.962344 ==
8462 13:31:20.966013 Dram Type= 6, Freq= 0, CH_1, rank 1
8463 13:31:20.968894 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8464 13:31:20.968972 ==
8465 13:31:20.972080 [Gating] SW mode calibration
8466 13:31:20.978782 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8467 13:31:20.985434 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8468 13:31:20.988742 0 12 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8469 13:31:20.995615 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8470 13:31:20.998851 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8471 13:31:21.002174 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8472 13:31:21.008546 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8473 13:31:21.012040 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8474 13:31:21.015236 0 12 24 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
8475 13:31:21.021625 0 12 28 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
8476 13:31:21.024989 0 13 0 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
8477 13:31:21.028411 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8478 13:31:21.035023 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8479 13:31:21.038834 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8480 13:31:21.041547 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8481 13:31:21.048419 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8482 13:31:21.051761 0 13 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8483 13:31:21.054890 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8484 13:31:21.061789 0 14 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
8485 13:31:21.064961 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8486 13:31:21.068250 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8487 13:31:21.074825 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8488 13:31:21.078303 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8489 13:31:21.081341 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8490 13:31:21.088103 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8491 13:31:21.091362 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8492 13:31:21.094671 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8493 13:31:21.101337 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8494 13:31:21.104725 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8495 13:31:21.107711 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8496 13:31:21.115155 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8497 13:31:21.117866 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8498 13:31:21.121156 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8499 13:31:21.124351 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8500 13:31:21.131055 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8501 13:31:21.134231 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8502 13:31:21.137579 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8503 13:31:21.144129 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8504 13:31:21.147844 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8505 13:31:21.150826 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8506 13:31:21.157942 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8507 13:31:21.161030 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8508 13:31:21.164377 Total UI for P1: 0, mck2ui 16
8509 13:31:21.167738 best dqsien dly found for B0: ( 1, 0, 24)
8510 13:31:21.171397 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8511 13:31:21.177801 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8512 13:31:21.177914 Total UI for P1: 0, mck2ui 16
8513 13:31:21.184802 best dqsien dly found for B1: ( 1, 1, 0)
8514 13:31:21.187439 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8515 13:31:21.190769 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8516 13:31:21.190835
8517 13:31:21.194498 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8518 13:31:21.197369 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8519 13:31:21.200713 [Gating] SW calibration Done
8520 13:31:21.200792 ==
8521 13:31:21.203761 Dram Type= 6, Freq= 0, CH_1, rank 1
8522 13:31:21.207393 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8523 13:31:21.207470 ==
8524 13:31:21.210935 RX Vref Scan: 0
8525 13:31:21.211012
8526 13:31:21.211067 RX Vref 0 -> 0, step: 1
8527 13:31:21.211114
8528 13:31:21.214293 RX Delay 0 -> 252, step: 8
8529 13:31:21.217089 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8530 13:31:21.223736 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8531 13:31:21.226925 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8532 13:31:21.230800 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8533 13:31:21.234062 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8534 13:31:21.237110 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8535 13:31:21.243707 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8536 13:31:21.247197 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8537 13:31:21.250284 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8538 13:31:21.253601 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8539 13:31:21.257187 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8540 13:31:21.263775 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8541 13:31:21.267239 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8542 13:31:21.270417 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8543 13:31:21.273649 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8544 13:31:21.280426 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8545 13:31:21.280503 ==
8546 13:31:21.283786 Dram Type= 6, Freq= 0, CH_1, rank 1
8547 13:31:21.286997 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8548 13:31:21.287073 ==
8549 13:31:21.287126 DQS Delay:
8550 13:31:21.290040 DQS0 = 0, DQS1 = 0
8551 13:31:21.290126 DQM Delay:
8552 13:31:21.293484 DQM0 = 129, DQM1 = 125
8553 13:31:21.293581 DQ Delay:
8554 13:31:21.296729 DQ0 =131, DQ1 =127, DQ2 =119, DQ3 =127
8555 13:31:21.300097 DQ4 =127, DQ5 =143, DQ6 =135, DQ7 =127
8556 13:31:21.303605 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8557 13:31:21.306802 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8558 13:31:21.306890
8559 13:31:21.306948
8560 13:31:21.310080 ==
8561 13:31:21.310159 Dram Type= 6, Freq= 0, CH_1, rank 1
8562 13:31:21.346788 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8563 13:31:21.347007 ==
8564 13:31:21.347164
8565 13:31:21.347225
8566 13:31:21.347275 TX Vref Scan disable
8567 13:31:21.347337 == TX Byte 0 ==
8568 13:31:21.347387 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8569 13:31:21.347437 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8570 13:31:21.347486 == TX Byte 1 ==
8571 13:31:21.347600 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8572 13:31:21.347651 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8573 13:31:21.347703 ==
8574 13:31:21.347819 Dram Type= 6, Freq= 0, CH_1, rank 1
8575 13:31:21.347870 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8576 13:31:21.347978 ==
8577 13:31:21.359038
8578 13:31:21.362226 TX Vref early break, caculate TX vref
8579 13:31:21.365637 TX Vref=16, minBit 3, minWin=22, winSum=377
8580 13:31:21.368614 TX Vref=18, minBit 0, minWin=23, winSum=384
8581 13:31:21.372045 TX Vref=20, minBit 0, minWin=22, winSum=394
8582 13:31:21.375777 TX Vref=22, minBit 0, minWin=24, winSum=402
8583 13:31:21.378550 TX Vref=24, minBit 0, minWin=24, winSum=405
8584 13:31:21.385499 TX Vref=26, minBit 0, minWin=25, winSum=414
8585 13:31:21.388371 TX Vref=28, minBit 0, minWin=25, winSum=418
8586 13:31:21.391981 TX Vref=30, minBit 0, minWin=25, winSum=415
8587 13:31:21.395127 TX Vref=32, minBit 0, minWin=23, winSum=402
8588 13:31:21.398652 TX Vref=34, minBit 0, minWin=22, winSum=394
8589 13:31:21.405407 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 28
8590 13:31:21.405485
8591 13:31:21.408453 Final TX Range 0 Vref 28
8592 13:31:21.408537
8593 13:31:21.408605 ==
8594 13:31:21.411765 Dram Type= 6, Freq= 0, CH_1, rank 1
8595 13:31:21.414745 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8596 13:31:21.414821 ==
8597 13:31:21.414876
8598 13:31:21.414924
8599 13:31:21.418277 TX Vref Scan disable
8600 13:31:21.425249 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8601 13:31:21.425326 == TX Byte 0 ==
8602 13:31:21.428268 u2DelayCellOfst[0]=17 cells (5 PI)
8603 13:31:21.431647 u2DelayCellOfst[1]=14 cells (4 PI)
8604 13:31:21.434600 u2DelayCellOfst[2]=0 cells (0 PI)
8605 13:31:21.437924 u2DelayCellOfst[3]=10 cells (3 PI)
8606 13:31:21.441520 u2DelayCellOfst[4]=10 cells (3 PI)
8607 13:31:21.445138 u2DelayCellOfst[5]=17 cells (5 PI)
8608 13:31:21.447802 u2DelayCellOfst[6]=17 cells (5 PI)
8609 13:31:21.451204 u2DelayCellOfst[7]=7 cells (2 PI)
8610 13:31:21.454764 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8611 13:31:21.457809 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8612 13:31:21.461024 == TX Byte 1 ==
8613 13:31:21.464415 u2DelayCellOfst[8]=0 cells (0 PI)
8614 13:31:21.467899 u2DelayCellOfst[9]=3 cells (1 PI)
8615 13:31:21.468085 u2DelayCellOfst[10]=10 cells (3 PI)
8616 13:31:21.470927 u2DelayCellOfst[11]=0 cells (0 PI)
8617 13:31:21.474432 u2DelayCellOfst[12]=14 cells (4 PI)
8618 13:31:21.477610 u2DelayCellOfst[13]=17 cells (5 PI)
8619 13:31:21.480958 u2DelayCellOfst[14]=17 cells (5 PI)
8620 13:31:21.484427 u2DelayCellOfst[15]=17 cells (5 PI)
8621 13:31:21.490741 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8622 13:31:21.494097 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8623 13:31:21.494284 DramC Write-DBI on
8624 13:31:21.494407 ==
8625 13:31:21.497422 Dram Type= 6, Freq= 0, CH_1, rank 1
8626 13:31:21.504052 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8627 13:31:21.504243 ==
8628 13:31:21.504338
8629 13:31:21.504410
8630 13:31:21.507294 TX Vref Scan disable
8631 13:31:21.507469 == TX Byte 0 ==
8632 13:31:21.513790 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8633 13:31:21.513957 == TX Byte 1 ==
8634 13:31:21.517477 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8635 13:31:21.520351 DramC Write-DBI off
8636 13:31:21.520410
8637 13:31:21.520460 [DATLAT]
8638 13:31:21.523873 Freq=1600, CH1 RK1
8639 13:31:21.523929
8640 13:31:21.523978 DATLAT Default: 0xe
8641 13:31:21.527497 0, 0xFFFF, sum = 0
8642 13:31:21.527574 1, 0xFFFF, sum = 0
8643 13:31:21.530626 2, 0xFFFF, sum = 0
8644 13:31:21.530705 3, 0xFFFF, sum = 0
8645 13:31:21.533854 4, 0xFFFF, sum = 0
8646 13:31:21.533939 5, 0xFFFF, sum = 0
8647 13:31:21.537025 6, 0xFFFF, sum = 0
8648 13:31:21.537114 7, 0xFFFF, sum = 0
8649 13:31:21.540760 8, 0xFFFF, sum = 0
8650 13:31:21.540849 9, 0xFFFF, sum = 0
8651 13:31:21.543500 10, 0xFFFF, sum = 0
8652 13:31:21.547131 11, 0xFFFF, sum = 0
8653 13:31:21.547211 12, 0xFFF, sum = 0
8654 13:31:21.550634 13, 0x0, sum = 1
8655 13:31:21.550712 14, 0x0, sum = 2
8656 13:31:21.550766 15, 0x0, sum = 3
8657 13:31:21.553599 16, 0x0, sum = 4
8658 13:31:21.553657 best_step = 14
8659 13:31:21.553704
8660 13:31:21.557067 ==
8661 13:31:21.557161 Dram Type= 6, Freq= 0, CH_1, rank 1
8662 13:31:21.563751 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8663 13:31:21.563813 ==
8664 13:31:21.563861 RX Vref Scan: 0
8665 13:31:21.563907
8666 13:31:21.566801 RX Vref 0 -> 0, step: 1
8667 13:31:21.566867
8668 13:31:21.570318 RX Delay 3 -> 252, step: 4
8669 13:31:21.573516 iDelay=195, Bit 0, Center 130 (79 ~ 182) 104
8670 13:31:21.576776 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8671 13:31:21.583638 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8672 13:31:21.587157 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8673 13:31:21.590199 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8674 13:31:21.593600 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8675 13:31:21.597169 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8676 13:31:21.603557 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8677 13:31:21.606502 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8678 13:31:21.610156 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8679 13:31:21.613335 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8680 13:31:21.616575 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8681 13:31:21.623120 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8682 13:31:21.626396 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8683 13:31:21.629685 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8684 13:31:21.633137 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8685 13:31:21.633221 ==
8686 13:31:21.636810 Dram Type= 6, Freq= 0, CH_1, rank 1
8687 13:31:21.642979 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8688 13:31:21.643094 ==
8689 13:31:21.643151 DQS Delay:
8690 13:31:21.646101 DQS0 = 0, DQS1 = 0
8691 13:31:21.646165 DQM Delay:
8692 13:31:21.649195 DQM0 = 128, DQM1 = 122
8693 13:31:21.649262 DQ Delay:
8694 13:31:21.653107 DQ0 =130, DQ1 =124, DQ2 =118, DQ3 =126
8695 13:31:21.656093 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8696 13:31:21.659481 DQ8 =104, DQ9 =110, DQ10 =124, DQ11 =114
8697 13:31:21.662977 DQ12 =132, DQ13 =132, DQ14 =134, DQ15 =132
8698 13:31:21.663114
8699 13:31:21.663172
8700 13:31:21.663223
8701 13:31:21.666467 [DramC_TX_OE_Calibration] TA2
8702 13:31:21.669137 Original DQ_B0 (3 6) =30, OEN = 27
8703 13:31:21.672484 Original DQ_B1 (3 6) =30, OEN = 27
8704 13:31:21.675885 24, 0x0, End_B0=24 End_B1=24
8705 13:31:21.679497 25, 0x0, End_B0=25 End_B1=25
8706 13:31:21.679623 26, 0x0, End_B0=26 End_B1=26
8707 13:31:21.682960 27, 0x0, End_B0=27 End_B1=27
8708 13:31:21.686116 28, 0x0, End_B0=28 End_B1=28
8709 13:31:21.689457 29, 0x0, End_B0=29 End_B1=29
8710 13:31:21.689585 30, 0x0, End_B0=30 End_B1=30
8711 13:31:21.693190 31, 0x4141, End_B0=30 End_B1=30
8712 13:31:21.695993 Byte0 end_step=30 best_step=27
8713 13:31:21.699589 Byte1 end_step=30 best_step=27
8714 13:31:21.702466 Byte0 TX OE(2T, 0.5T) = (3, 3)
8715 13:31:21.705572 Byte1 TX OE(2T, 0.5T) = (3, 3)
8716 13:31:21.705675
8717 13:31:21.705729
8718 13:31:21.712409 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
8719 13:31:21.715568 CH1 RK1: MR19=303, MR18=1B1B
8720 13:31:21.722171 CH1_RK1: MR19=0x303, MR18=0x1B1B, DQSOSC=396, MR23=63, INC=23, DEC=15
8721 13:31:21.725577 [RxdqsGatingPostProcess] freq 1600
8722 13:31:21.729358 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8723 13:31:21.732406 Pre-setting of DQS Precalculation
8724 13:31:21.738849 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8725 13:31:21.745576 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8726 13:31:21.752478 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8727 13:31:21.752553
8728 13:31:21.752621
8729 13:31:21.755387 [Calibration Summary] 3200 Mbps
8730 13:31:21.758342 CH 0, Rank 0
8731 13:31:21.758417 SW Impedance : PASS
8732 13:31:21.762056 DUTY Scan : NO K
8733 13:31:21.765094 ZQ Calibration : PASS
8734 13:31:21.765169 Jitter Meter : NO K
8735 13:31:21.768945 CBT Training : PASS
8736 13:31:21.772375 Write leveling : PASS
8737 13:31:21.772450 RX DQS gating : PASS
8738 13:31:21.775195 RX DQ/DQS(RDDQC) : PASS
8739 13:31:21.778621 TX DQ/DQS : PASS
8740 13:31:21.778704 RX DATLAT : PASS
8741 13:31:21.781695 RX DQ/DQS(Engine): PASS
8742 13:31:21.781770 TX OE : PASS
8743 13:31:21.785561 All Pass.
8744 13:31:21.785640
8745 13:31:21.785706 CH 0, Rank 1
8746 13:31:21.788518 SW Impedance : PASS
8747 13:31:21.788855 DUTY Scan : NO K
8748 13:31:21.792306 ZQ Calibration : PASS
8749 13:31:21.795232 Jitter Meter : NO K
8750 13:31:21.795317 CBT Training : PASS
8751 13:31:21.798085 Write leveling : PASS
8752 13:31:21.801920 RX DQS gating : PASS
8753 13:31:21.801994 RX DQ/DQS(RDDQC) : PASS
8754 13:31:21.805001 TX DQ/DQS : PASS
8755 13:31:21.808394 RX DATLAT : PASS
8756 13:31:21.808482 RX DQ/DQS(Engine): PASS
8757 13:31:21.811346 TX OE : PASS
8758 13:31:21.811408 All Pass.
8759 13:31:21.811457
8760 13:31:21.815027 CH 1, Rank 0
8761 13:31:21.815103 SW Impedance : PASS
8762 13:31:21.818530 DUTY Scan : NO K
8763 13:31:21.821471 ZQ Calibration : PASS
8764 13:31:21.821609 Jitter Meter : NO K
8765 13:31:21.824891 CBT Training : PASS
8766 13:31:21.828028 Write leveling : PASS
8767 13:31:21.828094 RX DQS gating : PASS
8768 13:31:21.831480 RX DQ/DQS(RDDQC) : PASS
8769 13:31:21.834550 TX DQ/DQS : PASS
8770 13:31:21.834638 RX DATLAT : PASS
8771 13:31:21.838006 RX DQ/DQS(Engine): PASS
8772 13:31:21.838096 TX OE : PASS
8773 13:31:21.841714 All Pass.
8774 13:31:21.841796
8775 13:31:21.841854 CH 1, Rank 1
8776 13:31:21.844669 SW Impedance : PASS
8777 13:31:21.844744 DUTY Scan : NO K
8778 13:31:21.848048 ZQ Calibration : PASS
8779 13:31:21.851364 Jitter Meter : NO K
8780 13:31:21.851438 CBT Training : PASS
8781 13:31:21.854642 Write leveling : PASS
8782 13:31:21.857924 RX DQS gating : PASS
8783 13:31:21.858017 RX DQ/DQS(RDDQC) : PASS
8784 13:31:21.861821 TX DQ/DQS : PASS
8785 13:31:21.864696 RX DATLAT : PASS
8786 13:31:21.864774 RX DQ/DQS(Engine): PASS
8787 13:31:21.867743 TX OE : PASS
8788 13:31:21.867835 All Pass.
8789 13:31:21.867900
8790 13:31:21.871354 DramC Write-DBI on
8791 13:31:21.874570 PER_BANK_REFRESH: Hybrid Mode
8792 13:31:21.874660 TX_TRACKING: ON
8793 13:31:21.884572 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8794 13:31:21.890725 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8795 13:31:21.897450 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8796 13:31:21.903977 [FAST_K] Save calibration result to emmc
8797 13:31:21.904037 sync common calibartion params.
8798 13:31:21.907281 sync cbt_mode0:0, 1:0
8799 13:31:21.911232 dram_init: ddr_geometry: 0
8800 13:31:21.911287 dram_init: ddr_geometry: 0
8801 13:31:21.913971 dram_init: ddr_geometry: 0
8802 13:31:21.917251 0:dram_rank_size:80000000
8803 13:31:21.920756 1:dram_rank_size:80000000
8804 13:31:21.924148 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8805 13:31:21.927222 DFS_SHUFFLE_HW_MODE: ON
8806 13:31:21.930813 dramc_set_vcore_voltage set vcore to 725000
8807 13:31:21.933855 Read voltage for 1600, 0
8808 13:31:21.933919 Vio18 = 0
8809 13:31:21.933979 Vcore = 725000
8810 13:31:21.937155 Vdram = 0
8811 13:31:21.937207 Vddq = 0
8812 13:31:21.937284 Vmddr = 0
8813 13:31:21.940968 switch to 3200 Mbps bootup
8814 13:31:21.944242 [DramcRunTimeConfig]
8815 13:31:21.944302 PHYPLL
8816 13:31:21.944349 DPM_CONTROL_AFTERK: ON
8817 13:31:21.947328 PER_BANK_REFRESH: ON
8818 13:31:21.950211 REFRESH_OVERHEAD_REDUCTION: ON
8819 13:31:21.950265 CMD_PICG_NEW_MODE: OFF
8820 13:31:21.953734 XRTWTW_NEW_MODE: ON
8821 13:31:21.957557 XRTRTR_NEW_MODE: ON
8822 13:31:21.957617 TX_TRACKING: ON
8823 13:31:21.960476 RDSEL_TRACKING: OFF
8824 13:31:21.960533 DQS Precalculation for DVFS: ON
8825 13:31:21.963521 RX_TRACKING: OFF
8826 13:31:21.963580 HW_GATING DBG: ON
8827 13:31:21.966943 ZQCS_ENABLE_LP4: ON
8828 13:31:21.967014 RX_PICG_NEW_MODE: ON
8829 13:31:21.970260 TX_PICG_NEW_MODE: ON
8830 13:31:21.973731 ENABLE_RX_DCM_DPHY: ON
8831 13:31:21.977293 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8832 13:31:21.977344 DUMMY_READ_FOR_TRACKING: OFF
8833 13:31:21.980300 !!! SPM_CONTROL_AFTERK: OFF
8834 13:31:21.983479 !!! SPM could not control APHY
8835 13:31:21.986886 IMPEDANCE_TRACKING: ON
8836 13:31:21.986937 TEMP_SENSOR: ON
8837 13:31:21.990169 HW_SAVE_FOR_SR: OFF
8838 13:31:21.990228 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8839 13:31:21.996548 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8840 13:31:21.996629 Read ODT Tracking: ON
8841 13:31:22.000345 Refresh Rate DeBounce: ON
8842 13:31:22.003756 DFS_NO_QUEUE_FLUSH: ON
8843 13:31:22.006571 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8844 13:31:22.006630 ENABLE_DFS_RUNTIME_MRW: OFF
8845 13:31:22.010298 DDR_RESERVE_NEW_MODE: ON
8846 13:31:22.014075 MR_CBT_SWITCH_FREQ: ON
8847 13:31:22.014128 =========================
8848 13:31:22.032722 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8849 13:31:22.036144 dram_init: ddr_geometry: 0
8850 13:31:22.054272 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8851 13:31:22.057710 dram_init: dram init end (result: 0)
8852 13:31:22.064173 DRAM-K: Full calibration passed in 23383 msecs
8853 13:31:22.067509 MRC: failed to locate region type 0.
8854 13:31:22.067568 DRAM rank0 size:0x80000000,
8855 13:31:22.071126 DRAM rank1 size=0x80000000
8856 13:31:22.080934 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8857 13:31:22.087433 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8858 13:31:22.094346 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8859 13:31:22.100562 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8860 13:31:22.103517 DRAM rank0 size:0x80000000,
8861 13:31:22.107089 DRAM rank1 size=0x80000000
8862 13:31:22.107146 CBMEM:
8863 13:31:22.110341 IMD: root @ 0xfffff000 254 entries.
8864 13:31:22.114158 IMD: root @ 0xffffec00 62 entries.
8865 13:31:22.117031 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8866 13:31:22.120089 WARNING: RO_VPD is uninitialized or empty.
8867 13:31:22.126930 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8868 13:31:22.134032 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8869 13:31:22.146673 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8870 13:31:22.157989 BS: romstage times (exec / console): total (unknown) / 22929 ms
8871 13:31:22.158065
8872 13:31:22.158119
8873 13:31:22.167825 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8874 13:31:22.170964 ARM64: Exception handlers installed.
8875 13:31:22.174267 ARM64: Testing exception
8876 13:31:22.178042 ARM64: Done test exception
8877 13:31:22.178166 Enumerating buses...
8878 13:31:22.180997 Show all devs... Before device enumeration.
8879 13:31:22.184550 Root Device: enabled 1
8880 13:31:22.187624 CPU_CLUSTER: 0: enabled 1
8881 13:31:22.187714 CPU: 00: enabled 1
8882 13:31:22.191135 Compare with tree...
8883 13:31:22.191211 Root Device: enabled 1
8884 13:31:22.194234 CPU_CLUSTER: 0: enabled 1
8885 13:31:22.197663 CPU: 00: enabled 1
8886 13:31:22.197743 Root Device scanning...
8887 13:31:22.200735 scan_static_bus for Root Device
8888 13:31:22.204290 CPU_CLUSTER: 0 enabled
8889 13:31:22.207789 scan_static_bus for Root Device done
8890 13:31:22.210726 scan_bus: bus Root Device finished in 8 msecs
8891 13:31:22.210803 done
8892 13:31:22.217474 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8893 13:31:22.220931 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8894 13:31:22.227410 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8895 13:31:22.230630 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8896 13:31:22.233981 Allocating resources...
8897 13:31:22.237630 Reading resources...
8898 13:31:22.240425 Root Device read_resources bus 0 link: 0
8899 13:31:22.240501 DRAM rank0 size:0x80000000,
8900 13:31:22.244682 DRAM rank1 size=0x80000000
8901 13:31:22.247605 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8902 13:31:22.250591 CPU: 00 missing read_resources
8903 13:31:22.253927 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8904 13:31:22.260558 Root Device read_resources bus 0 link: 0 done
8905 13:31:22.260635 Done reading resources.
8906 13:31:22.267036 Show resources in subtree (Root Device)...After reading.
8907 13:31:22.270655 Root Device child on link 0 CPU_CLUSTER: 0
8908 13:31:22.273786 CPU_CLUSTER: 0 child on link 0 CPU: 00
8909 13:31:22.284391 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8910 13:31:22.284482 CPU: 00
8911 13:31:22.286914 Root Device assign_resources, bus 0 link: 0
8912 13:31:22.290498 CPU_CLUSTER: 0 missing set_resources
8913 13:31:22.296983 Root Device assign_resources, bus 0 link: 0 done
8914 13:31:22.297051 Done setting resources.
8915 13:31:22.303298 Show resources in subtree (Root Device)...After assigning values.
8916 13:31:22.306748 Root Device child on link 0 CPU_CLUSTER: 0
8917 13:31:22.310186 CPU_CLUSTER: 0 child on link 0 CPU: 00
8918 13:31:22.320208 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8919 13:31:22.320264 CPU: 00
8920 13:31:22.323590 Done allocating resources.
8921 13:31:22.326853 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8922 13:31:22.330255 Enabling resources...
8923 13:31:22.330339 done.
8924 13:31:22.337060 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8925 13:31:22.337185 Initializing devices...
8926 13:31:22.340361 Root Device init
8927 13:31:22.340461 init hardware done!
8928 13:31:22.343986 0x00000018: ctrlr->caps
8929 13:31:22.346904 52.000 MHz: ctrlr->f_max
8930 13:31:22.346987 0.400 MHz: ctrlr->f_min
8931 13:31:22.350473 0x40ff8080: ctrlr->voltages
8932 13:31:22.350550 sclk: 390625
8933 13:31:22.354117 Bus Width = 1
8934 13:31:22.354192 sclk: 390625
8935 13:31:22.356749 Bus Width = 1
8936 13:31:22.356837 Early init status = 3
8937 13:31:22.363291 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8938 13:31:22.367120 in-header: 03 fc 00 00 01 00 00 00
8939 13:31:22.370013 in-data: 00
8940 13:31:22.373246 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8941 13:31:22.379241 in-header: 03 fd 00 00 00 00 00 00
8942 13:31:22.382381 in-data:
8943 13:31:22.386114 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8944 13:31:22.390616 in-header: 03 fc 00 00 01 00 00 00
8945 13:31:22.393542 in-data: 00
8946 13:31:22.397199 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8947 13:31:22.402460 in-header: 03 fd 00 00 00 00 00 00
8948 13:31:22.405796 in-data:
8949 13:31:22.409392 [SSUSB] Setting up USB HOST controller...
8950 13:31:22.412689 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8951 13:31:22.416232 [SSUSB] phy power-on done.
8952 13:31:22.419160 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8953 13:31:22.425870 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8954 13:31:22.428975 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8955 13:31:22.435928 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8956 13:31:22.442078 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
8957 13:31:22.449352 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8958 13:31:22.455651 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8959 13:31:22.461844 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
8960 13:31:22.465255 SPM: binary array size = 0x9dc
8961 13:31:22.468726 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8962 13:31:22.475209 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8963 13:31:22.481699 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8964 13:31:22.488382 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8965 13:31:22.491530 configure_display: Starting display init
8966 13:31:22.525910 anx7625_power_on_init: Init interface.
8967 13:31:22.529359 anx7625_disable_pd_protocol: Disabled PD feature.
8968 13:31:22.532731 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8969 13:31:22.560365 anx7625_start_dp_work: Secure OCM version=00
8970 13:31:22.563401 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8971 13:31:22.578104 sp_tx_get_edid_block: EDID Block = 1
8972 13:31:22.681144 Extracted contents:
8973 13:31:22.684049 header: 00 ff ff ff ff ff ff 00
8974 13:31:22.687358 serial number: 26 cf 7d 05 00 00 00 00 00 1e
8975 13:31:22.690871 version: 01 04
8976 13:31:22.694137 basic params: 95 1f 11 78 0a
8977 13:31:22.697484 chroma info: 76 90 94 55 54 90 27 21 50 54
8978 13:31:22.700891 established: 00 00 00
8979 13:31:22.707273 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
8980 13:31:22.714090 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
8981 13:31:22.717339 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
8982 13:31:22.723834 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
8983 13:31:22.730308 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
8984 13:31:22.733879 extensions: 00
8985 13:31:22.733944 checksum: fb
8986 13:31:22.734000
8987 13:31:22.740182 Manufacturer: IVO Model 57d Serial Number 0
8988 13:31:22.740240 Made week 0 of 2020
8989 13:31:22.743540 EDID version: 1.4
8990 13:31:22.743594 Digital display
8991 13:31:22.747013 6 bits per primary color channel
8992 13:31:22.747068 DisplayPort interface
8993 13:31:22.750061 Maximum image size: 31 cm x 17 cm
8994 13:31:22.753752 Gamma: 220%
8995 13:31:22.753805 Check DPMS levels
8996 13:31:22.759781 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
8997 13:31:22.763546 First detailed timing is preferred timing
8998 13:31:22.763603 Established timings supported:
8999 13:31:22.767208 Standard timings supported:
9000 13:31:22.769932 Detailed timings
9001 13:31:22.773529 Hex of detail: 383680a07038204018303c0035ae10000019
9002 13:31:22.779887 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9003 13:31:22.782961 0780 0798 07c8 0820 hborder 0
9004 13:31:22.786178 0438 043b 0447 0458 vborder 0
9005 13:31:22.790035 -hsync -vsync
9006 13:31:22.790116 Did detailed timing
9007 13:31:22.796247 Hex of detail: 000000000000000000000000000000000000
9008 13:31:22.799914 Manufacturer-specified data, tag 0
9009 13:31:22.802699 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9010 13:31:22.806487 ASCII string: InfoVision
9011 13:31:22.809931 Hex of detail: 000000fe00523134304e574635205248200a
9012 13:31:22.812958 ASCII string: R140NWF5 RH
9013 13:31:22.813033 Checksum
9014 13:31:22.816424 Checksum: 0xfb (valid)
9015 13:31:22.819637 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9016 13:31:22.822895 DSI data_rate: 832800000 bps
9017 13:31:22.829362 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9018 13:31:22.832888 anx7625_parse_edid: pixelclock(138800).
9019 13:31:22.836044 hactive(1920), hsync(48), hfp(24), hbp(88)
9020 13:31:22.839573 vactive(1080), vsync(12), vfp(3), vbp(17)
9021 13:31:22.842898 anx7625_dsi_config: config dsi.
9022 13:31:22.849458 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9023 13:31:22.863505 anx7625_dsi_config: success to config DSI
9024 13:31:22.866520 anx7625_dp_start: MIPI phy setup OK.
9025 13:31:22.869745 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9026 13:31:22.872785 mtk_ddp_mode_set invalid vrefresh 60
9027 13:31:22.876154 main_disp_path_setup
9028 13:31:22.876229 ovl_layer_smi_id_en
9029 13:31:22.879526 ovl_layer_smi_id_en
9030 13:31:22.879605 ccorr_config
9031 13:31:22.879658 aal_config
9032 13:31:22.883307 gamma_config
9033 13:31:22.883380 postmask_config
9034 13:31:22.886130 dither_config
9035 13:31:22.890100 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9036 13:31:22.895929 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9037 13:31:22.899296 Root Device init finished in 556 msecs
9038 13:31:22.902594 CPU_CLUSTER: 0 init
9039 13:31:22.909417 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9040 13:31:22.912473 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9041 13:31:22.915990 APU_MBOX 0x190000b0 = 0x10001
9042 13:31:22.918988 APU_MBOX 0x190001b0 = 0x10001
9043 13:31:22.922502 APU_MBOX 0x190005b0 = 0x10001
9044 13:31:22.925959 APU_MBOX 0x190006b0 = 0x10001
9045 13:31:22.929099 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9046 13:31:22.942112 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9047 13:31:22.954955 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9048 13:31:22.961373 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9049 13:31:22.972792 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9050 13:31:22.982159 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9051 13:31:22.985476 CPU_CLUSTER: 0 init finished in 81 msecs
9052 13:31:22.988386 Devices initialized
9053 13:31:22.991753 Show all devs... After init.
9054 13:31:22.992067 Root Device: enabled 1
9055 13:31:22.994869 CPU_CLUSTER: 0: enabled 1
9056 13:31:22.998533 CPU: 00: enabled 1
9057 13:31:23.001609 BS: BS_DEV_INIT run times (exec / console): 214 / 447 ms
9058 13:31:23.005182 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9059 13:31:23.008548 ELOG: NV offset 0x57f000 size 0x1000
9060 13:31:23.015241 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9061 13:31:23.021628 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9062 13:31:23.024984 ELOG: Event(17) added with size 13 at 2023-09-08 13:31:22 UTC
9063 13:31:23.031546 out: cmd=0x121: 03 db 21 01 00 00 00 00
9064 13:31:23.034819 in-header: 03 13 00 00 2c 00 00 00
9065 13:31:23.048921 in-data: 50 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9066 13:31:23.051358 ELOG: Event(A1) added with size 10 at 2023-09-08 13:31:22 UTC
9067 13:31:23.057986 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9068 13:31:23.064789 ELOG: Event(A0) added with size 9 at 2023-09-08 13:31:22 UTC
9069 13:31:23.068660 elog_add_boot_reason: Logged dev mode boot
9070 13:31:23.074782 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9071 13:31:23.075139 Finalize devices...
9072 13:31:23.077972 Devices finalized
9073 13:31:23.081357 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9074 13:31:23.084472 Writing coreboot table at 0xffe64000
9075 13:31:23.091175 0. 000000000010a000-0000000000113fff: RAMSTAGE
9076 13:31:23.094317 1. 0000000040000000-00000000400fffff: RAM
9077 13:31:23.097661 2. 0000000040100000-000000004032afff: RAMSTAGE
9078 13:31:23.100743 3. 000000004032b000-00000000545fffff: RAM
9079 13:31:23.104237 4. 0000000054600000-000000005465ffff: BL31
9080 13:31:23.107461 5. 0000000054660000-00000000ffe63fff: RAM
9081 13:31:23.113891 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9082 13:31:23.117569 7. 0000000100000000-000000013fffffff: RAM
9083 13:31:23.120759 Passing 5 GPIOs to payload:
9084 13:31:23.123768 NAME | PORT | POLARITY | VALUE
9085 13:31:23.130460 EC in RW | 0x000000aa | low | undefined
9086 13:31:23.133962 EC interrupt | 0x00000005 | low | undefined
9087 13:31:23.140295 TPM interrupt | 0x000000ab | high | undefined
9088 13:31:23.143891 SD card detect | 0x00000011 | high | undefined
9089 13:31:23.147328 speaker enable | 0x00000093 | high | undefined
9090 13:31:23.150493 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9091 13:31:23.153866 in-header: 03 f8 00 00 02 00 00 00
9092 13:31:23.156945 in-data: 03 00
9093 13:31:23.160465 ADC[4]: Raw value=670063 ID=5
9094 13:31:23.163704 ADC[3]: Raw value=212549 ID=1
9095 13:31:23.163780 RAM Code: 0x51
9096 13:31:23.167304 ADC[6]: Raw value=74410 ID=0
9097 13:31:23.170400 ADC[5]: Raw value=212180 ID=1
9098 13:31:23.170484 SKU Code: 0x1
9099 13:31:23.177363 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 17eb
9100 13:31:23.177440 coreboot table: 964 bytes.
9101 13:31:23.180457 IMD ROOT 0. 0xfffff000 0x00001000
9102 13:31:23.183518 IMD SMALL 1. 0xffffe000 0x00001000
9103 13:31:23.187035 RO MCACHE 2. 0xffffc000 0x00001104
9104 13:31:23.190713 CONSOLE 3. 0xfff7c000 0x00080000
9105 13:31:23.193519 FMAP 4. 0xfff7b000 0x00000452
9106 13:31:23.196585 TIME STAMP 5. 0xfff7a000 0x00000910
9107 13:31:23.200020 VBOOT WORK 6. 0xfff66000 0x00014000
9108 13:31:23.203054 RAMOOPS 7. 0xffe66000 0x00100000
9109 13:31:23.206346 COREBOOT 8. 0xffe64000 0x00002000
9110 13:31:23.209864 IMD small region:
9111 13:31:23.213678 IMD ROOT 0. 0xffffec00 0x00000400
9112 13:31:23.216445 VPD 1. 0xffffeb80 0x0000006c
9113 13:31:23.220149 MMC STATUS 2. 0xffffeb60 0x00000004
9114 13:31:23.226491 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9115 13:31:23.226567 Probing TPM: done!
9116 13:31:23.233636 Connected to device vid:did:rid of 1ae0:0028:00
9117 13:31:23.240042 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9118 13:31:23.243749 Initialized TPM device CR50 revision 0
9119 13:31:23.246754 Checking cr50 for pending updates
9120 13:31:23.251985 Reading cr50 TPM mode
9121 13:31:23.260916 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9122 13:31:23.267227 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9123 13:31:23.307470 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9124 13:31:23.310897 Checking segment from ROM address 0x40100000
9125 13:31:23.314650 Checking segment from ROM address 0x4010001c
9126 13:31:23.321016 Loading segment from ROM address 0x40100000
9127 13:31:23.321361 code (compression=0)
9128 13:31:23.331260 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9129 13:31:23.337287 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9130 13:31:23.337645 it's not compressed!
9131 13:31:23.344721 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9132 13:31:23.350455 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9133 13:31:23.367701 Loading segment from ROM address 0x4010001c
9134 13:31:23.368102 Entry Point 0x80000000
9135 13:31:23.371651 Loaded segments
9136 13:31:23.374831 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9137 13:31:23.381720 Jumping to boot code at 0x80000000(0xffe64000)
9138 13:31:23.387991 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9139 13:31:23.394556 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9140 13:31:23.401826 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9141 13:31:23.406017 Checking segment from ROM address 0x40100000
9142 13:31:23.408611 Checking segment from ROM address 0x4010001c
9143 13:31:23.415404 Loading segment from ROM address 0x40100000
9144 13:31:23.415463 code (compression=1)
9145 13:31:23.422072 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9146 13:31:23.432270 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9147 13:31:23.432365 using LZMA
9148 13:31:23.440469 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9149 13:31:23.447172 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9150 13:31:23.450599 Loading segment from ROM address 0x4010001c
9151 13:31:23.450670 Entry Point 0x54601000
9152 13:31:23.453683 Loaded segments
9153 13:31:23.457176 NOTICE: MT8192 bl31_setup
9154 13:31:23.464347 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9155 13:31:23.467370 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9156 13:31:23.470934 WARNING: region 0:
9157 13:31:23.474029 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9158 13:31:23.474096 WARNING: region 1:
9159 13:31:23.480965 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9160 13:31:23.484210 WARNING: region 2:
9161 13:31:23.487603 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9162 13:31:23.490632 WARNING: region 3:
9163 13:31:23.494472 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9164 13:31:23.497756 WARNING: region 4:
9165 13:31:23.504670 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9166 13:31:23.504998 WARNING: region 5:
9167 13:31:23.508065 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9168 13:31:23.510739 WARNING: region 6:
9169 13:31:23.514422 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9170 13:31:23.518169 WARNING: region 7:
9171 13:31:23.520812 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9172 13:31:23.527344 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9173 13:31:23.530922 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9174 13:31:23.533867 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9175 13:31:23.541097 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9176 13:31:23.543875 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9177 13:31:23.547584 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9178 13:31:23.554077 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9179 13:31:23.557052 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9180 13:31:23.563786 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9181 13:31:23.567255 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9182 13:31:23.570803 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9183 13:31:23.577013 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9184 13:31:23.580947 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9185 13:31:23.584069 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9186 13:31:23.590843 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9187 13:31:23.593962 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9188 13:31:23.600974 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9189 13:31:23.603621 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9190 13:31:23.607083 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9191 13:31:23.613730 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9192 13:31:23.617334 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9193 13:31:23.620741 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9194 13:31:23.627685 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9195 13:31:23.630713 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9196 13:31:23.637720 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9197 13:31:23.640464 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9198 13:31:23.643665 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9199 13:31:23.650577 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9200 13:31:23.653794 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9201 13:31:23.661509 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9202 13:31:23.664039 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9203 13:31:23.667282 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9204 13:31:23.674066 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9205 13:31:23.677003 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9206 13:31:23.680473 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9207 13:31:23.683631 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9208 13:31:23.690223 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9209 13:31:23.693645 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9210 13:31:23.697229 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9211 13:31:23.700505 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9212 13:31:23.706825 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9213 13:31:23.710321 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9214 13:31:23.713906 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9215 13:31:23.716869 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9216 13:31:23.724084 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9217 13:31:23.726992 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9218 13:31:23.730088 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9219 13:31:23.733925 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9220 13:31:23.740468 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9221 13:31:23.743516 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9222 13:31:23.750320 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9223 13:31:23.753452 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9224 13:31:23.760070 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9225 13:31:23.763541 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9226 13:31:23.767039 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9227 13:31:23.773557 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9228 13:31:23.776634 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9229 13:31:23.783438 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9230 13:31:23.787036 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9231 13:31:23.793656 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9232 13:31:23.796707 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9233 13:31:23.800109 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9234 13:31:23.806697 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9235 13:31:23.810587 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9236 13:31:23.817149 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9237 13:31:23.820376 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9238 13:31:23.827230 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9239 13:31:23.830342 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9240 13:31:23.833709 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9241 13:31:23.840389 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9242 13:31:23.843296 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9243 13:31:23.850383 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9244 13:31:23.853670 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9245 13:31:23.860192 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9246 13:31:23.863498 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9247 13:31:23.867011 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9248 13:31:23.873736 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9249 13:31:23.877165 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9250 13:31:23.883434 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9251 13:31:23.886755 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9252 13:31:23.893433 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9253 13:31:23.896834 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9254 13:31:23.903382 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9255 13:31:23.906877 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9256 13:31:23.910242 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9257 13:31:23.917001 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9258 13:31:23.919750 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9259 13:31:23.926853 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9260 13:31:23.929947 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9261 13:31:23.936663 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9262 13:31:23.940649 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9263 13:31:23.943134 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9264 13:31:23.950320 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9265 13:31:23.953316 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9266 13:31:23.960350 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9267 13:31:23.963332 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9268 13:31:23.966600 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9269 13:31:23.973884 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9270 13:31:23.976644 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9271 13:31:23.980107 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9272 13:31:23.983660 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9273 13:31:23.989943 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9274 13:31:23.993237 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9275 13:31:23.999732 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9276 13:31:24.003431 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9277 13:31:24.006494 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9278 13:31:24.013404 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9279 13:31:24.016163 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9280 13:31:24.022910 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9281 13:31:24.026764 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9282 13:31:24.029460 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9283 13:31:24.036427 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9284 13:31:24.040019 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9285 13:31:24.046394 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9286 13:31:24.049652 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9287 13:31:24.052845 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9288 13:31:24.059909 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9289 13:31:24.063220 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9290 13:31:24.067161 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9291 13:31:24.073146 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9292 13:31:24.076301 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9293 13:31:24.079630 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9294 13:31:24.083257 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9295 13:31:24.089960 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9296 13:31:24.093121 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9297 13:31:24.096381 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9298 13:31:24.103273 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9299 13:31:24.106724 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9300 13:31:24.113809 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9301 13:31:24.116479 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9302 13:31:24.119762 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9303 13:31:24.126760 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9304 13:31:24.129809 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9305 13:31:24.133083 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9306 13:31:24.139555 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9307 13:31:24.143355 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9308 13:31:24.149861 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9309 13:31:24.152754 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9310 13:31:24.156531 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9311 13:31:24.162824 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9312 13:31:24.166449 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9313 13:31:24.173048 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9314 13:31:24.176189 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9315 13:31:24.179519 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9316 13:31:24.186288 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9317 13:31:24.189497 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9318 13:31:24.192542 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9319 13:31:24.199259 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9320 13:31:24.202808 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9321 13:31:24.209563 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9322 13:31:24.212727 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9323 13:31:24.216108 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9324 13:31:24.222598 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9325 13:31:24.226237 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9326 13:31:24.232417 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9327 13:31:24.236439 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9328 13:31:24.239579 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9329 13:31:24.245900 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9330 13:31:24.249465 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9331 13:31:24.253031 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9332 13:31:24.259514 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9333 13:31:24.262937 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9334 13:31:24.269431 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9335 13:31:24.272954 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9336 13:31:24.279734 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9337 13:31:24.283194 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9338 13:31:24.286093 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9339 13:31:24.292797 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9340 13:31:24.296538 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9341 13:31:24.299313 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9342 13:31:24.305850 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9343 13:31:24.308893 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9344 13:31:24.315899 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9345 13:31:24.318937 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9346 13:31:24.322378 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9347 13:31:24.329147 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9348 13:31:24.332223 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9349 13:31:24.338926 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9350 13:31:24.342175 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9351 13:31:24.345486 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9352 13:31:24.352329 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9353 13:31:24.355558 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9354 13:31:24.362291 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9355 13:31:24.365806 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9356 13:31:24.368670 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9357 13:31:24.375202 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9358 13:31:24.379036 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9359 13:31:24.385511 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9360 13:31:24.388830 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9361 13:31:24.392209 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9362 13:31:24.398721 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9363 13:31:24.402261 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9364 13:31:24.408770 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9365 13:31:24.412130 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9366 13:31:24.415168 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9367 13:31:24.422170 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9368 13:31:24.425172 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9369 13:31:24.431968 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9370 13:31:24.435275 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9371 13:31:24.441665 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9372 13:31:24.444965 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9373 13:31:24.448103 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9374 13:31:24.454874 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9375 13:31:24.458210 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9376 13:31:24.465253 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9377 13:31:24.468429 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9378 13:31:24.475230 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9379 13:31:24.478372 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9380 13:31:24.481268 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9381 13:31:24.488176 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9382 13:31:24.491727 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9383 13:31:24.497946 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9384 13:31:24.501709 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9385 13:31:24.504936 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9386 13:31:24.511336 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9387 13:31:24.514424 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9388 13:31:24.520946 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9389 13:31:24.525065 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9390 13:31:24.530941 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9391 13:31:24.534347 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9392 13:31:24.537685 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9393 13:31:24.544513 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9394 13:31:24.547718 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9395 13:31:24.554075 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9396 13:31:24.557832 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9397 13:31:24.564018 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9398 13:31:24.567514 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9399 13:31:24.571103 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9400 13:31:24.577405 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9401 13:31:24.580913 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9402 13:31:24.584028 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9403 13:31:24.587176 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9404 13:31:24.594026 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9405 13:31:24.597886 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9406 13:31:24.600442 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9407 13:31:24.607148 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9408 13:31:24.610691 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9409 13:31:24.613879 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9410 13:31:24.621176 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9411 13:31:24.623989 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9412 13:31:24.627641 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9413 13:31:24.633854 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9414 13:31:24.637330 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9415 13:31:24.641058 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9416 13:31:24.647333 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9417 13:31:24.650437 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9418 13:31:24.657156 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9419 13:31:24.660048 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9420 13:31:24.664078 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9421 13:31:24.670395 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9422 13:31:24.673627 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9423 13:31:24.677140 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9424 13:31:24.683603 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9425 13:31:24.687540 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9426 13:31:24.693489 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9427 13:31:24.696910 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9428 13:31:24.700246 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9429 13:31:24.706540 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9430 13:31:24.709879 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9431 13:31:24.713339 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9432 13:31:24.719795 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9433 13:31:24.723129 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9434 13:31:24.729945 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9435 13:31:24.733281 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9436 13:31:24.736451 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9437 13:31:24.743574 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9438 13:31:24.747357 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9439 13:31:24.750036 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9440 13:31:24.756532 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9441 13:31:24.760196 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9442 13:31:24.763289 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9443 13:31:24.766519 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9444 13:31:24.770004 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9445 13:31:24.776444 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9446 13:31:24.779795 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9447 13:31:24.783793 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9448 13:31:24.786448 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9449 13:31:24.792990 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9450 13:31:24.796622 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9451 13:31:24.799819 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9452 13:31:24.806306 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9453 13:31:24.809786 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9454 13:31:24.812923 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9455 13:31:24.819703 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9456 13:31:24.822773 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9457 13:31:24.829513 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9458 13:31:24.833247 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9459 13:31:24.836204 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9460 13:31:24.842708 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9461 13:31:24.846515 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9462 13:31:24.852446 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9463 13:31:24.855791 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9464 13:31:24.859111 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9465 13:31:24.866060 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9466 13:31:24.869277 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9467 13:31:24.875494 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9468 13:31:24.878907 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9469 13:31:24.885670 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9470 13:31:24.889110 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9471 13:31:24.892406 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9472 13:31:24.899080 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9473 13:31:24.902239 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9474 13:31:24.908554 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9475 13:31:24.912154 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9476 13:31:24.918436 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9477 13:31:24.922305 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9478 13:31:24.925576 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9479 13:31:24.932165 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9480 13:31:24.935186 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9481 13:31:24.941646 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9482 13:31:24.945121 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9483 13:31:24.948698 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9484 13:31:24.955401 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9485 13:31:24.958074 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9486 13:31:24.965255 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9487 13:31:24.968204 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9488 13:31:24.971248 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9489 13:31:24.978273 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9490 13:31:24.981768 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9491 13:31:24.988151 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9492 13:31:24.991671 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9493 13:31:24.994774 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9494 13:31:25.001392 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9495 13:31:25.004913 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9496 13:31:25.012268 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9497 13:31:25.014593 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9498 13:31:25.021771 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9499 13:31:25.024988 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9500 13:31:25.027803 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9501 13:31:25.034317 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9502 13:31:25.038014 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9503 13:31:25.044433 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9504 13:31:25.047746 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9505 13:31:25.051373 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9506 13:31:25.057461 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9507 13:31:25.060832 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9508 13:31:25.067530 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9509 13:31:25.071353 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9510 13:31:25.074156 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9511 13:31:25.080973 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9512 13:31:25.085320 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9513 13:31:25.090665 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9514 13:31:25.094111 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9515 13:31:25.100933 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9516 13:31:25.103598 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9517 13:31:25.107177 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9518 13:31:25.113754 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9519 13:31:25.117257 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9520 13:31:25.124241 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9521 13:31:25.127268 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9522 13:31:25.134010 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9523 13:31:25.136973 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9524 13:31:25.140482 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9525 13:31:25.146924 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9526 13:31:25.150126 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9527 13:31:25.156801 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9528 13:31:25.160060 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9529 13:31:25.167171 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9530 13:31:25.170107 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9531 13:31:25.173060 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9532 13:31:25.179931 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9533 13:31:25.183318 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9534 13:31:25.190383 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9535 13:31:25.193295 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9536 13:31:25.199841 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9537 13:31:25.203125 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9538 13:31:25.209469 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9539 13:31:25.212799 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9540 13:31:25.216150 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9541 13:31:25.222881 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9542 13:31:25.226190 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9543 13:31:25.232886 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9544 13:31:25.236345 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9545 13:31:25.242807 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9546 13:31:25.246303 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9547 13:31:25.249534 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9548 13:31:25.255826 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9549 13:31:25.259076 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9550 13:31:25.265710 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9551 13:31:25.269119 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9552 13:31:25.276216 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9553 13:31:25.279450 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9554 13:31:25.282794 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9555 13:31:25.289300 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9556 13:31:25.292820 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9557 13:31:25.299150 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9558 13:31:25.303201 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9559 13:31:25.309149 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9560 13:31:25.312731 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9561 13:31:25.318892 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9562 13:31:25.322380 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9563 13:31:25.325922 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9564 13:31:25.332643 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9565 13:31:25.335714 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9566 13:31:25.342231 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9567 13:31:25.345393 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9568 13:31:25.352376 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9569 13:31:25.355187 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9570 13:31:25.358657 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9571 13:31:25.365169 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9572 13:31:25.368493 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9573 13:31:25.375554 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9574 13:31:25.378406 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9575 13:31:25.381895 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9576 13:31:25.388547 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9577 13:31:25.391823 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9578 13:31:25.398362 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9579 13:31:25.401712 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9580 13:31:25.408650 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9581 13:31:25.412194 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9582 13:31:25.418543 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9583 13:31:25.421531 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9584 13:31:25.428760 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9585 13:31:25.431528 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9586 13:31:25.438587 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9587 13:31:25.441774 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9588 13:31:25.448577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9589 13:31:25.451581 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9590 13:31:25.458570 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9591 13:31:25.461450 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9592 13:31:25.468079 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9593 13:31:25.471256 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9594 13:31:25.478245 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9595 13:31:25.481631 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9596 13:31:25.488020 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9597 13:31:25.491417 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9598 13:31:25.497852 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9599 13:31:25.501214 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9600 13:31:25.507634 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9601 13:31:25.510920 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9602 13:31:25.517352 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9603 13:31:25.521083 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9604 13:31:25.527791 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9605 13:31:25.531078 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9606 13:31:25.534153 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9607 13:31:25.537393 INFO: [APUAPC] vio 0
9608 13:31:25.544221 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9609 13:31:25.547334 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9610 13:31:25.550790 INFO: [APUAPC] D0_APC_0: 0x400510
9611 13:31:25.554232 INFO: [APUAPC] D0_APC_1: 0x0
9612 13:31:25.557350 INFO: [APUAPC] D0_APC_2: 0x1540
9613 13:31:25.560498 INFO: [APUAPC] D0_APC_3: 0x0
9614 13:31:25.563931 INFO: [APUAPC] D1_APC_0: 0xffffffff
9615 13:31:25.567324 INFO: [APUAPC] D1_APC_1: 0xffffffff
9616 13:31:25.570694 INFO: [APUAPC] D1_APC_2: 0x3fffff
9617 13:31:25.574097 INFO: [APUAPC] D1_APC_3: 0x0
9618 13:31:25.577376 INFO: [APUAPC] D2_APC_0: 0xffffffff
9619 13:31:25.580465 INFO: [APUAPC] D2_APC_1: 0xffffffff
9620 13:31:25.584066 INFO: [APUAPC] D2_APC_2: 0x3fffff
9621 13:31:25.587102 INFO: [APUAPC] D2_APC_3: 0x0
9622 13:31:25.590547 INFO: [APUAPC] D3_APC_0: 0xffffffff
9623 13:31:25.593979 INFO: [APUAPC] D3_APC_1: 0xffffffff
9624 13:31:25.597098 INFO: [APUAPC] D3_APC_2: 0x3fffff
9625 13:31:25.597166 INFO: [APUAPC] D3_APC_3: 0x0
9626 13:31:25.603552 INFO: [APUAPC] D4_APC_0: 0xffffffff
9627 13:31:25.607054 INFO: [APUAPC] D4_APC_1: 0xffffffff
9628 13:31:25.610030 INFO: [APUAPC] D4_APC_2: 0x3fffff
9629 13:31:25.610086 INFO: [APUAPC] D4_APC_3: 0x0
9630 13:31:25.614044 INFO: [APUAPC] D5_APC_0: 0xffffffff
9631 13:31:25.620134 INFO: [APUAPC] D5_APC_1: 0xffffffff
9632 13:31:25.623452 INFO: [APUAPC] D5_APC_2: 0x3fffff
9633 13:31:25.623507 INFO: [APUAPC] D5_APC_3: 0x0
9634 13:31:25.626784 INFO: [APUAPC] D6_APC_0: 0xffffffff
9635 13:31:25.630332 INFO: [APUAPC] D6_APC_1: 0xffffffff
9636 13:31:25.633601 INFO: [APUAPC] D6_APC_2: 0x3fffff
9637 13:31:25.637211 INFO: [APUAPC] D6_APC_3: 0x0
9638 13:31:25.640351 INFO: [APUAPC] D7_APC_0: 0xffffffff
9639 13:31:25.643503 INFO: [APUAPC] D7_APC_1: 0xffffffff
9640 13:31:25.646688 INFO: [APUAPC] D7_APC_2: 0x3fffff
9641 13:31:25.649885 INFO: [APUAPC] D7_APC_3: 0x0
9642 13:31:25.653457 INFO: [APUAPC] D8_APC_0: 0xffffffff
9643 13:31:25.656800 INFO: [APUAPC] D8_APC_1: 0xffffffff
9644 13:31:25.660250 INFO: [APUAPC] D8_APC_2: 0x3fffff
9645 13:31:25.663491 INFO: [APUAPC] D8_APC_3: 0x0
9646 13:31:25.666673 INFO: [APUAPC] D9_APC_0: 0xffffffff
9647 13:31:25.670250 INFO: [APUAPC] D9_APC_1: 0xffffffff
9648 13:31:25.673922 INFO: [APUAPC] D9_APC_2: 0x3fffff
9649 13:31:25.677231 INFO: [APUAPC] D9_APC_3: 0x0
9650 13:31:25.679892 INFO: [APUAPC] D10_APC_0: 0xffffffff
9651 13:31:25.683091 INFO: [APUAPC] D10_APC_1: 0xffffffff
9652 13:31:25.686775 INFO: [APUAPC] D10_APC_2: 0x3fffff
9653 13:31:25.689822 INFO: [APUAPC] D10_APC_3: 0x0
9654 13:31:25.693236 INFO: [APUAPC] D11_APC_0: 0xffffffff
9655 13:31:25.696625 INFO: [APUAPC] D11_APC_1: 0xffffffff
9656 13:31:25.699752 INFO: [APUAPC] D11_APC_2: 0x3fffff
9657 13:31:25.703616 INFO: [APUAPC] D11_APC_3: 0x0
9658 13:31:25.706721 INFO: [APUAPC] D12_APC_0: 0xffffffff
9659 13:31:25.709594 INFO: [APUAPC] D12_APC_1: 0xffffffff
9660 13:31:25.713105 INFO: [APUAPC] D12_APC_2: 0x3fffff
9661 13:31:25.716201 INFO: [APUAPC] D12_APC_3: 0x0
9662 13:31:25.720410 INFO: [APUAPC] D13_APC_0: 0xffffffff
9663 13:31:25.722876 INFO: [APUAPC] D13_APC_1: 0xffffffff
9664 13:31:25.726339 INFO: [APUAPC] D13_APC_2: 0x3fffff
9665 13:31:25.729551 INFO: [APUAPC] D13_APC_3: 0x0
9666 13:31:25.733219 INFO: [APUAPC] D14_APC_0: 0xffffffff
9667 13:31:25.736286 INFO: [APUAPC] D14_APC_1: 0xffffffff
9668 13:31:25.739552 INFO: [APUAPC] D14_APC_2: 0x3fffff
9669 13:31:25.742845 INFO: [APUAPC] D14_APC_3: 0x0
9670 13:31:25.746582 INFO: [APUAPC] D15_APC_0: 0xffffffff
9671 13:31:25.749570 INFO: [APUAPC] D15_APC_1: 0xffffffff
9672 13:31:25.752919 INFO: [APUAPC] D15_APC_2: 0x3fffff
9673 13:31:25.755939 INFO: [APUAPC] D15_APC_3: 0x0
9674 13:31:25.759345 INFO: [APUAPC] APC_CON: 0x4
9675 13:31:25.762805 INFO: [NOCDAPC] D0_APC_0: 0x0
9676 13:31:25.765953 INFO: [NOCDAPC] D0_APC_1: 0x0
9677 13:31:25.769244 INFO: [NOCDAPC] D1_APC_0: 0x0
9678 13:31:25.772737 INFO: [NOCDAPC] D1_APC_1: 0xfff
9679 13:31:25.776075 INFO: [NOCDAPC] D2_APC_0: 0x0
9680 13:31:25.776130 INFO: [NOCDAPC] D2_APC_1: 0xfff
9681 13:31:25.779151 INFO: [NOCDAPC] D3_APC_0: 0x0
9682 13:31:25.782613 INFO: [NOCDAPC] D3_APC_1: 0xfff
9683 13:31:25.785892 INFO: [NOCDAPC] D4_APC_0: 0x0
9684 13:31:25.789686 INFO: [NOCDAPC] D4_APC_1: 0xfff
9685 13:31:25.792639 INFO: [NOCDAPC] D5_APC_0: 0x0
9686 13:31:25.795719 INFO: [NOCDAPC] D5_APC_1: 0xfff
9687 13:31:25.799425 INFO: [NOCDAPC] D6_APC_0: 0x0
9688 13:31:25.803288 INFO: [NOCDAPC] D6_APC_1: 0xfff
9689 13:31:25.806052 INFO: [NOCDAPC] D7_APC_0: 0x0
9690 13:31:25.809268 INFO: [NOCDAPC] D7_APC_1: 0xfff
9691 13:31:25.809344 INFO: [NOCDAPC] D8_APC_0: 0x0
9692 13:31:25.812211 INFO: [NOCDAPC] D8_APC_1: 0xfff
9693 13:31:25.815733 INFO: [NOCDAPC] D9_APC_0: 0x0
9694 13:31:25.819101 INFO: [NOCDAPC] D9_APC_1: 0xfff
9695 13:31:25.822349 INFO: [NOCDAPC] D10_APC_0: 0x0
9696 13:31:25.825722 INFO: [NOCDAPC] D10_APC_1: 0xfff
9697 13:31:25.829080 INFO: [NOCDAPC] D11_APC_0: 0x0
9698 13:31:25.832424 INFO: [NOCDAPC] D11_APC_1: 0xfff
9699 13:31:25.835994 INFO: [NOCDAPC] D12_APC_0: 0x0
9700 13:31:25.839114 INFO: [NOCDAPC] D12_APC_1: 0xfff
9701 13:31:25.842265 INFO: [NOCDAPC] D13_APC_0: 0x0
9702 13:31:25.845931 INFO: [NOCDAPC] D13_APC_1: 0xfff
9703 13:31:25.848886 INFO: [NOCDAPC] D14_APC_0: 0x0
9704 13:31:25.852192 INFO: [NOCDAPC] D14_APC_1: 0xfff
9705 13:31:25.855591 INFO: [NOCDAPC] D15_APC_0: 0x0
9706 13:31:25.858958 INFO: [NOCDAPC] D15_APC_1: 0xfff
9707 13:31:25.859015 INFO: [NOCDAPC] APC_CON: 0x4
9708 13:31:25.862126 INFO: [APUAPC] set_apusys_apc done
9709 13:31:25.865275 INFO: [DEVAPC] devapc_init done
9710 13:31:25.871836 INFO: GICv3 without legacy support detected.
9711 13:31:25.875296 INFO: ARM GICv3 driver initialized in EL3
9712 13:31:25.878651 INFO: Maximum SPI INTID supported: 639
9713 13:31:25.882277 INFO: BL31: Initializing runtime services
9714 13:31:25.888348 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9715 13:31:25.891946 INFO: SPM: enable CPC mode
9716 13:31:25.894999 INFO: mcdi ready for mcusys-off-idle and system suspend
9717 13:31:25.901741 INFO: BL31: Preparing for EL3 exit to normal world
9718 13:31:25.904930 INFO: Entry point address = 0x80000000
9719 13:31:25.905014 INFO: SPSR = 0x8
9720 13:31:25.911668
9721 13:31:25.911728
9722 13:31:25.911776
9723 13:31:25.915301 Starting depthcharge on Spherion...
9724 13:31:25.915357
9725 13:31:25.915402 Wipe memory regions:
9726 13:31:25.915447
9727 13:31:25.915941 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9728 13:31:25.916026 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9729 13:31:25.916100 Setting prompt string to ['asurada:']
9730 13:31:25.916162 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9731 13:31:25.918838 [0x00000040000000, 0x00000054600000)
9732 13:31:26.040769
9733 13:31:26.040906 [0x00000054660000, 0x00000080000000)
9734 13:31:26.301725
9735 13:31:26.301872 [0x000000821a7280, 0x000000ffe64000)
9736 13:31:27.046275
9737 13:31:27.046411 [0x00000100000000, 0x00000140000000)
9738 13:31:27.427216
9739 13:31:27.430710 Initializing XHCI USB controller at 0x11200000.
9740 13:31:28.468581
9741 13:31:28.471869 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9742 13:31:28.471946
9743 13:31:28.471997
9744 13:31:28.472043
9745 13:31:28.472304 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9747 13:31:28.572654 asurada: tftpboot 192.168.201.1 11471181/tftp-deploy-gextz524/kernel/image.itb 11471181/tftp-deploy-gextz524/kernel/cmdline
9748 13:31:28.572814 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9749 13:31:28.572891 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9750 13:31:28.577107 tftpboot 192.168.201.1 11471181/tftp-deploy-gextz524/kernel/image.ittp-deploy-gextz524/kernel/cmdline
9751 13:31:28.577183
9752 13:31:28.577237 Waiting for link
9753 13:31:28.737622
9754 13:31:28.737769 R8152: Initializing
9755 13:31:28.737832
9756 13:31:28.740966 Version 9 (ocp_data = 6010)
9757 13:31:28.741045
9758 13:31:28.744212 R8152: Done initializing
9759 13:31:28.744280
9760 13:31:28.744333 Adding net device
9761 13:31:30.630518
9762 13:31:30.630915 done.
9763 13:31:30.631150
9764 13:31:30.631352 MAC: 00:e0:4c:68:03:bd
9765 13:31:30.631547
9766 13:31:30.633704 Sending DHCP discover... done.
9767 13:31:30.634061
9768 13:31:34.100897 Waiting for reply... done.
9769 13:31:34.101054
9770 13:31:34.101115 Sending DHCP request... done.
9771 13:31:34.103838
9772 13:31:34.103898 Waiting for reply... done.
9773 13:31:34.103946
9774 13:31:34.107257 My ip is 192.168.201.16
9775 13:31:34.107325
9776 13:31:34.110516 The DHCP server ip is 192.168.201.1
9777 13:31:34.110587
9778 13:31:34.113915 TFTP server IP predefined by user: 192.168.201.1
9779 13:31:34.113975
9780 13:31:34.120472 Bootfile predefined by user: 11471181/tftp-deploy-gextz524/kernel/image.itb
9781 13:31:34.120550
9782 13:31:34.123957 Sending tftp read request... done.
9783 13:31:34.124014
9784 13:31:34.127658 Waiting for the transfer...
9785 13:31:34.127747
9786 13:31:34.354379 00000000 ################################################################
9787 13:31:34.354523
9788 13:31:34.580936 00080000 ################################################################
9789 13:31:34.581063
9790 13:31:34.808870 00100000 ################################################################
9791 13:31:34.809018
9792 13:31:35.036218 00180000 ################################################################
9793 13:31:35.036370
9794 13:31:35.263331 00200000 ################################################################
9795 13:31:35.263490
9796 13:31:35.492053 00280000 ################################################################
9797 13:31:35.492190
9798 13:31:35.718705 00300000 ################################################################
9799 13:31:35.718848
9800 13:31:35.948366 00380000 ################################################################
9801 13:31:35.948521
9802 13:31:36.174297 00400000 ################################################################
9803 13:31:36.174422
9804 13:31:36.400676 00480000 ################################################################
9805 13:31:36.400817
9806 13:31:36.626961 00500000 ################################################################
9807 13:31:36.627098
9808 13:31:36.853419 00580000 ################################################################
9809 13:31:36.853555
9810 13:31:37.080066 00600000 ################################################################
9811 13:31:37.080213
9812 13:31:37.306973 00680000 ################################################################
9813 13:31:37.307116
9814 13:31:37.532901 00700000 ################################################################
9815 13:31:37.533039
9816 13:31:37.759578 00780000 ################################################################
9817 13:31:37.759705
9818 13:31:37.985505 00800000 ################################################################
9819 13:31:37.985632
9820 13:31:38.212288 00880000 ################################################################
9821 13:31:38.212435
9822 13:31:38.437918 00900000 ################################################################
9823 13:31:38.438054
9824 13:31:38.666957 00980000 ################################################################
9825 13:31:38.667110
9826 13:31:38.896245 00a00000 ################################################################
9827 13:31:38.896388
9828 13:31:39.125499 00a80000 ################################################################
9829 13:31:39.125631
9830 13:31:39.354486 00b00000 ################################################################
9831 13:31:39.354625
9832 13:31:39.583627 00b80000 ################################################################
9833 13:31:39.583749
9834 13:31:39.815077 00c00000 ################################################################
9835 13:31:39.815216
9836 13:31:40.045361 00c80000 ################################################################
9837 13:31:40.045512
9838 13:31:40.273943 00d00000 ################################################################
9839 13:31:40.274082
9840 13:31:40.503923 00d80000 ################################################################
9841 13:31:40.504066
9842 13:31:40.733017 00e00000 ################################################################
9843 13:31:40.733158
9844 13:31:40.962036 00e80000 ################################################################
9845 13:31:40.962200
9846 13:31:41.191348 00f00000 ################################################################
9847 13:31:41.191482
9848 13:31:41.420557 00f80000 ################################################################
9849 13:31:41.420699
9850 13:31:41.649993 01000000 ################################################################
9851 13:31:41.650134
9852 13:31:41.880127 01080000 ################################################################
9853 13:31:41.880272
9854 13:31:42.109339 01100000 ################################################################
9855 13:31:42.109485
9856 13:31:42.338688 01180000 ################################################################
9857 13:31:42.338842
9858 13:31:42.566087 01200000 ################################################################
9859 13:31:42.566228
9860 13:31:42.795527 01280000 ################################################################
9861 13:31:42.795662
9862 13:31:43.024912 01300000 ################################################################
9863 13:31:43.025044
9864 13:31:43.253255 01380000 ################################################################
9865 13:31:43.253382
9866 13:31:43.481679 01400000 ################################################################
9867 13:31:43.481856
9868 13:31:43.710642 01480000 ################################################################
9869 13:31:43.710789
9870 13:31:43.939521 01500000 ################################################################
9871 13:31:43.939661
9872 13:31:44.168980 01580000 ################################################################
9873 13:31:44.169124
9874 13:31:44.396985 01600000 ################################################################
9875 13:31:44.397120
9876 13:31:44.623761 01680000 ################################################################
9877 13:31:44.623890
9878 13:31:44.851978 01700000 ################################################################
9879 13:31:44.852113
9880 13:31:45.079966 01780000 ################################################################
9881 13:31:45.080113
9882 13:31:45.307849 01800000 ################################################################
9883 13:31:45.307975
9884 13:31:45.535515 01880000 ################################################################
9885 13:31:45.535647
9886 13:31:45.762934 01900000 ################################################################
9887 13:31:45.763066
9888 13:31:45.992735 01980000 ################################################################
9889 13:31:45.992876
9890 13:31:46.219827 01a00000 ################################################################
9891 13:31:46.219968
9892 13:31:46.447173 01a80000 ################################################################
9893 13:31:46.447309
9894 13:31:46.675384 01b00000 ################################################################
9895 13:31:46.675520
9896 13:31:46.903012 01b80000 ################################################################
9897 13:31:46.903157
9898 13:31:47.131093 01c00000 ################################################################
9899 13:31:47.131224
9900 13:31:47.357415 01c80000 ################################################################
9901 13:31:47.357536
9902 13:31:47.583321 01d00000 ################################################################
9903 13:31:47.583442
9904 13:31:47.810252 01d80000 ################################################################
9905 13:31:47.810375
9906 13:31:48.037372 01e00000 ################################################################
9907 13:31:48.037507
9908 13:31:48.265537 01e80000 ################################################################
9909 13:31:48.265675
9910 13:31:48.492784 01f00000 ################################################################
9911 13:31:48.492910
9912 13:31:48.720785 01f80000 ################################################################
9913 13:31:48.720910
9914 13:31:48.948594 02000000 ################################################################
9915 13:31:48.948741
9916 13:31:49.178291 02080000 ################################################################
9917 13:31:49.178419
9918 13:31:49.405726 02100000 ################################################################
9919 13:31:49.405861
9920 13:31:49.634019 02180000 ################################################################
9921 13:31:49.634146
9922 13:31:49.862924 02200000 ################################################################
9923 13:31:49.863048
9924 13:31:50.092318 02280000 ################################################################
9925 13:31:50.092449
9926 13:31:50.321773 02300000 ################################################################
9927 13:31:50.321900
9928 13:31:50.549759 02380000 ################################################################
9929 13:31:50.549895
9930 13:31:50.777530 02400000 ################################################################
9931 13:31:50.777661
9932 13:31:51.005142 02480000 ################################################################
9933 13:31:51.005273
9934 13:31:51.236117 02500000 ################################################################
9935 13:31:51.236243
9936 13:31:51.465858 02580000 ################################################################
9937 13:31:51.465989
9938 13:31:51.694933 02600000 ################################################################
9939 13:31:51.695100
9940 13:31:51.923622 02680000 ################################################################
9941 13:31:51.923758
9942 13:31:52.152866 02700000 ################################################################
9943 13:31:52.153003
9944 13:31:52.381044 02780000 ################################################################
9945 13:31:52.381184
9946 13:31:52.608478 02800000 ################################################################
9947 13:31:52.608609
9948 13:31:52.837025 02880000 ################################################################
9949 13:31:52.837172
9950 13:31:53.064879 02900000 ################################################################
9951 13:31:53.065015
9952 13:31:53.292859 02980000 ################################################################
9953 13:31:53.293019
9954 13:31:53.522712 02a00000 ################################################################
9955 13:31:53.522858
9956 13:31:53.751569 02a80000 ################################################################
9957 13:31:53.751707
9958 13:31:53.979000 02b00000 ################################################################
9959 13:31:53.979139
9960 13:31:54.209008 02b80000 ################################################################
9961 13:31:54.209160
9962 13:31:54.437054 02c00000 ################################################################
9963 13:31:54.437199
9964 13:31:54.665412 02c80000 ################################################################
9965 13:31:54.665555
9966 13:31:54.894130 02d00000 ################################################################
9967 13:31:54.894265
9968 13:31:55.122381 02d80000 ################################################################
9969 13:31:55.122511
9970 13:31:55.351147 02e00000 ################################################################
9971 13:31:55.351279
9972 13:31:55.578168 02e80000 ################################################################
9973 13:31:55.578300
9974 13:31:55.805971 02f00000 ################################################################
9975 13:31:55.806116
9976 13:31:56.034031 02f80000 ################################################################
9977 13:31:56.034171
9978 13:31:56.263311 03000000 ################################################################
9979 13:31:56.263447
9980 13:31:56.497457 03080000 ################################################################
9981 13:31:56.497603
9982 13:31:56.729521 03100000 ################################################################
9983 13:31:56.729661
9984 13:31:56.959821 03180000 ################################################################
9985 13:31:56.959961
9986 13:31:57.190729 03200000 ################################################################
9987 13:31:57.190868
9988 13:31:57.418817 03280000 ################################################################
9989 13:31:57.418969
9990 13:31:57.646861 03300000 ################################################################
9991 13:31:57.646987
9992 13:31:57.876076 03380000 ################################################################
9993 13:31:57.876209
9994 13:31:58.106126 03400000 ################################################################
9995 13:31:58.106254
9996 13:31:58.337034 03480000 ################################################################
9997 13:31:58.337174
9998 13:31:58.565162 03500000 ################################################################
9999 13:31:58.565304
10000 13:31:58.794058 03580000 ################################################################
10001 13:31:58.794222
10002 13:31:59.023094 03600000 ################################################################
10003 13:31:59.023236
10004 13:31:59.250390 03680000 ################################################################
10005 13:31:59.250540
10006 13:31:59.477148 03700000 ################################################################
10007 13:31:59.477303
10008 13:31:59.702587 03780000 ################################################################
10009 13:31:59.702733
10010 13:31:59.928889 03800000 ################################################################
10011 13:31:59.929018
10012 13:32:00.155345 03880000 ################################################################
10013 13:32:00.155486
10014 13:32:00.384911 03900000 ################################################################
10015 13:32:00.385039
10016 13:32:00.615667 03980000 ################################################################
10017 13:32:00.615793
10018 13:32:00.847603 03a00000 ################################################################
10019 13:32:00.847740
10020 13:32:01.075879 03a80000 ################################################################
10021 13:32:01.076008
10022 13:32:01.306060 03b00000 ################################################################
10023 13:32:01.306194
10024 13:32:01.537549 03b80000 ################################################################
10025 13:32:01.537707
10026 13:32:01.769586 03c00000 ################################################################
10027 13:32:01.769726
10028 13:32:01.998679 03c80000 ################################################################
10029 13:32:01.998804
10030 13:32:02.227330 03d00000 ################################################################
10031 13:32:02.227468
10032 13:32:02.454913 03d80000 ################################################################
10033 13:32:02.455078
10034 13:32:02.683172 03e00000 ################################################################
10035 13:32:02.683312
10036 13:32:02.912255 03e80000 ################################################################
10037 13:32:02.912401
10038 13:32:03.140834 03f00000 ################################################################
10039 13:32:03.140959
10040 13:32:03.371307 03f80000 ################################################################
10041 13:32:03.371452
10042 13:32:03.600581 04000000 ################################################################
10043 13:32:03.600707
10044 13:32:03.827312 04080000 ################################################################
10045 13:32:03.827440
10046 13:32:04.056602 04100000 ################################################################
10047 13:32:04.056746
10048 13:32:04.283093 04180000 ################################################################
10049 13:32:04.283243
10050 13:32:04.510489 04200000 ################################################################
10051 13:32:04.510633
10052 13:32:04.736317 04280000 ################################################################
10053 13:32:04.736470
10054 13:32:04.963147 04300000 ################################################################
10055 13:32:04.963300
10056 13:32:05.189008 04380000 ################################################################
10057 13:32:05.189154
10058 13:32:05.416900 04400000 ################################################################
10059 13:32:05.417036
10060 13:32:05.644014 04480000 ################################################################
10061 13:32:05.644143
10062 13:32:05.872079 04500000 ################################################################
10063 13:32:05.872216
10064 13:32:06.100122 04580000 ################################################################
10065 13:32:06.100257
10066 13:32:06.328935 04600000 ################################################################
10067 13:32:06.329077
10068 13:32:06.557925 04680000 ################################################################
10069 13:32:06.558051
10070 13:32:06.785016 04700000 ################################################################
10071 13:32:06.785150
10072 13:32:07.012573 04780000 ################################################################
10073 13:32:07.012716
10074 13:32:07.240413 04800000 ################################################################
10075 13:32:07.240555
10076 13:32:07.467283 04880000 ################################################################
10077 13:32:07.467435
10078 13:32:07.694877 04900000 ################################################################
10079 13:32:07.695012
10080 13:32:07.924731 04980000 ################################################################
10081 13:32:07.924877
10082 13:32:08.152647 04a00000 ################################################################
10083 13:32:08.152784
10084 13:32:08.377696 04a80000 ################################################################
10085 13:32:08.377837
10086 13:32:08.604649 04b00000 ################################################################
10087 13:32:08.604795
10088 13:32:08.832059 04b80000 ################################################################
10089 13:32:08.832292
10090 13:32:09.060614 04c00000 ################################################################
10091 13:32:09.060751
10092 13:32:09.289385 04c80000 ################################################################
10093 13:32:09.289535
10094 13:32:09.515430 04d00000 ################################################################
10095 13:32:09.515574
10096 13:32:09.742363 04d80000 ################################################################
10097 13:32:09.742499
10098 13:32:09.970639 04e00000 ################################################################
10099 13:32:09.970778
10100 13:32:10.198138 04e80000 ################################################################
10101 13:32:10.198278
10102 13:32:10.426262 04f00000 ################################################################
10103 13:32:10.426407
10104 13:32:10.654706 04f80000 ################################################################
10105 13:32:10.654852
10106 13:32:10.883189 05000000 ################################################################
10107 13:32:10.883332
10108 13:32:11.111280 05080000 ################################################################
10109 13:32:11.111435
10110 13:32:11.338015 05100000 ################################################################
10111 13:32:11.338157
10112 13:32:11.566620 05180000 ################################################################
10113 13:32:11.566775
10114 13:32:11.794419 05200000 ################################################################
10115 13:32:11.794560
10116 13:32:12.021614 05280000 ################################################################
10117 13:32:12.021753
10118 13:32:12.247058 05300000 ################################################################
10119 13:32:12.247200
10120 13:32:12.472763 05380000 ################################################################
10121 13:32:12.472900
10122 13:32:12.700094 05400000 ################################################################
10123 13:32:12.700229
10124 13:32:12.925523 05480000 ################################################################
10125 13:32:12.925655
10126 13:32:13.151989 05500000 ################################################################
10127 13:32:13.152131
10128 13:32:13.378846 05580000 ################################################################
10129 13:32:13.378996
10130 13:32:13.605620 05600000 ################################################################
10131 13:32:13.605763
10132 13:32:13.833191 05680000 ################################################################
10133 13:32:13.833338
10134 13:32:14.060912 05700000 ################################################################
10135 13:32:14.061050
10136 13:32:14.288699 05780000 ################################################################
10137 13:32:14.288833
10138 13:32:14.515541 05800000 ################################################################
10139 13:32:14.515679
10140 13:32:14.744529 05880000 ################################################################
10141 13:32:14.744673
10142 13:32:14.970089 05900000 ################################################################
10143 13:32:14.970216
10144 13:32:15.196203 05980000 ################################################################
10145 13:32:15.196340
10146 13:32:15.424940 05a00000 ################################################################
10147 13:32:15.425079
10148 13:32:15.652796 05a80000 ################################################################
10149 13:32:15.652927
10150 13:32:15.880768 05b00000 ################################################################
10151 13:32:15.880893
10152 13:32:16.108186 05b80000 ################################################################
10153 13:32:16.108329
10154 13:32:16.335788 05c00000 ################################################################
10155 13:32:16.335924
10156 13:32:16.563627 05c80000 ################################################################
10157 13:32:16.563766
10158 13:32:16.790963 05d00000 ################################################################
10159 13:32:16.791116
10160 13:32:17.019652 05d80000 ################################################################
10161 13:32:17.019792
10162 13:32:17.246181 05e00000 ################################################################
10163 13:32:17.246314
10164 13:32:17.474287 05e80000 ################################################################
10165 13:32:17.474435
10166 13:32:17.702651 05f00000 ################################################################
10167 13:32:17.702804
10168 13:32:17.928206 05f80000 ################################################################
10169 13:32:17.928360
10170 13:32:18.154835 06000000 ################################################################
10171 13:32:18.154977
10172 13:32:18.381568 06080000 ################################################################
10173 13:32:18.381708
10174 13:32:18.608983 06100000 ################################################################
10175 13:32:18.609125
10176 13:32:18.836107 06180000 ################################################################
10177 13:32:18.836243
10178 13:32:19.064494 06200000 ################################################################
10179 13:32:19.064649
10180 13:32:19.294385 06280000 ################################################################
10181 13:32:19.294529
10182 13:32:19.521541 06300000 ################################################################
10183 13:32:19.521679
10184 13:32:19.749698 06380000 ################################################################
10185 13:32:19.749856
10186 13:32:19.978048 06400000 ################################################################
10187 13:32:19.978187
10188 13:32:20.206503 06480000 ################################################################
10189 13:32:20.206663
10190 13:32:20.434647 06500000 ################################################################
10191 13:32:20.434781
10192 13:32:20.662986 06580000 ################################################################
10193 13:32:20.663124
10194 13:32:20.891583 06600000 ################################################################
10195 13:32:20.891731
10196 13:32:21.117980 06680000 ################################################################
10197 13:32:21.118126
10198 13:32:21.348852 06700000 ################################################################
10199 13:32:21.348995
10200 13:32:21.577741 06780000 ################################################################
10201 13:32:21.577895
10202 13:32:21.732404 06800000 ############################################ done.
10203 13:32:21.732546
10204 13:32:21.735646 The bootfile was 109409162 bytes long.
10205 13:32:21.735709
10206 13:32:21.738947 Sending tftp read request... done.
10207 13:32:21.739020
10208 13:32:21.742574 Waiting for the transfer...
10209 13:32:21.742636
10210 13:32:21.745791 00000000 # done.
10211 13:32:21.745868
10212 13:32:21.752760 Command line loaded dynamically from TFTP file: 11471181/tftp-deploy-gextz524/kernel/cmdline
10213 13:32:21.753232
10214 13:32:21.765463 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10215 13:32:21.765935
10216 13:32:21.766198 Loading FIT.
10217 13:32:21.766417
10218 13:32:21.769043 Image ramdisk-1 has 98319756 bytes.
10219 13:32:21.769511
10220 13:32:21.771817 Image fdt-1 has 47278 bytes.
10221 13:32:21.772170
10222 13:32:21.775672 Image kernel-1 has 11040095 bytes.
10223 13:32:21.776137
10224 13:32:21.785634 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10225 13:32:21.786097
10226 13:32:21.801902 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10227 13:32:21.802306
10228 13:32:21.808449 Choosing best match conf-1 for compat google,spherion-rev3.
10229 13:32:21.808907
10230 13:32:21.816318 Connected to device vid:did:rid of 1ae0:0028:00
10231 13:32:21.824611
10232 13:32:21.828107 tpm_get_response: command 0x17b, return code 0x0
10233 13:32:21.828666
10234 13:32:21.834229 ec_init: CrosEC protocol v3 supported (256, 248)
10235 13:32:21.834615
10236 13:32:21.837735 tpm_cleanup: add release locality here.
10237 13:32:21.838188
10238 13:32:21.841318 Shutting down all USB controllers.
10239 13:32:21.841785
10240 13:32:21.844242 Removing current net device
10241 13:32:21.844653
10242 13:32:21.851026 Exiting depthcharge with code 4 at timestamp: 84130755
10243 13:32:21.851526
10244 13:32:21.854733 LZMA decompressing kernel-1 to 0x821a6718
10245 13:32:21.855234
10246 13:32:21.857541 LZMA decompressing kernel-1 to 0x40000000
10247 13:32:23.243903
10248 13:32:23.244443 jumping to kernel
10249 13:32:23.245768 end: 2.2.4 bootloader-commands (duration 00:00:57) [common]
10250 13:32:23.246170 start: 2.2.5 auto-login-action (timeout 00:03:29) [common]
10251 13:32:23.246569 Setting prompt string to ['Linux version [0-9]']
10252 13:32:23.246853 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10253 13:32:23.247125 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10254 13:32:23.293965
10255 13:32:23.297466 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10256 13:32:23.301287 start: 2.2.5.1 login-action (timeout 00:03:29) [common]
10257 13:32:23.301716 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10258 13:32:23.302034 Setting prompt string to []
10259 13:32:23.302346 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10260 13:32:23.302647 Using line separator: #'\n'#
10261 13:32:23.302889 No login prompt set.
10262 13:32:23.303136 Parsing kernel messages
10263 13:32:23.303469 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10264 13:32:23.304033 [login-action] Waiting for messages, (timeout 00:03:29)
10265 13:32:23.320374 [ 0.000000] Linux version 6.1.52-cip5 (KernelCI@build-j38933-arm64-gcc-10-defconfig-arm64-chromebook-kgx6p) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Sep 8 13:10:51 UTC 2023
10266 13:32:23.323802 [ 0.000000] random: crng init done
10267 13:32:23.330526 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10268 13:32:23.333664 [ 0.000000] efi: UEFI not found.
10269 13:32:23.340862 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10270 13:32:23.346802 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10271 13:32:23.357036 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10272 13:32:23.367352 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10273 13:32:23.373490 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10274 13:32:23.380396 [ 0.000000] printk: bootconsole [mtk8250] enabled
10275 13:32:23.386650 [ 0.000000] NUMA: No NUMA configuration found
10276 13:32:23.393346 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10277 13:32:23.396330 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d4a00-0x13f7d6fff]
10278 13:32:23.399777 [ 0.000000] Zone ranges:
10279 13:32:23.406404 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10280 13:32:23.409654 [ 0.000000] DMA32 empty
10281 13:32:23.415947 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10282 13:32:23.419459 [ 0.000000] Movable zone start for each node
10283 13:32:23.423162 [ 0.000000] Early memory node ranges
10284 13:32:23.429396 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10285 13:32:23.436147 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10286 13:32:23.442372 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10287 13:32:23.449207 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10288 13:32:23.455524 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10289 13:32:23.462246 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10290 13:32:23.492181 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10291 13:32:23.498831 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10292 13:32:23.505090 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10293 13:32:23.508821 [ 0.000000] psci: probing for conduit method from DT.
10294 13:32:23.515412 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10295 13:32:23.518733 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10296 13:32:23.525132 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10297 13:32:23.528525 [ 0.000000] psci: SMC Calling Convention v1.2
10298 13:32:23.535474 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10299 13:32:23.538885 [ 0.000000] Detected VIPT I-cache on CPU0
10300 13:32:23.544986 [ 0.000000] CPU features: detected: GIC system register CPU interface
10301 13:32:23.552402 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10302 13:32:23.558455 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10303 13:32:23.565019 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10304 13:32:23.572076 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10305 13:32:23.581756 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10306 13:32:23.584963 [ 0.000000] alternatives: applying boot alternatives
10307 13:32:23.591454 [ 0.000000] Fallback order for Node 0: 0
10308 13:32:23.598250 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10309 13:32:23.601392 [ 0.000000] Policy zone: Normal
10310 13:32:23.614951 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10311 13:32:23.624229 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10312 13:32:23.634779 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10313 13:32:23.644825 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10314 13:32:23.651673 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10315 13:32:23.654719 <6>[ 0.000000] software IO TLB: area num 8.
10316 13:32:23.710699 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10317 13:32:23.790990 <6>[ 0.000000] Memory: 3759068K/4191232K available (17984K kernel code, 4098K rwdata, 17468K rodata, 8384K init, 616K bss, 399396K reserved, 32768K cma-reserved)
10318 13:32:23.797720 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10319 13:32:23.803787 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10320 13:32:23.807306 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10321 13:32:23.813573 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10322 13:32:23.820220 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10323 13:32:23.823705 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10324 13:32:23.833445 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10325 13:32:23.840013 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10326 13:32:23.846793 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10327 13:32:23.853660 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10328 13:32:23.856675 <6>[ 0.000000] GICv3: 608 SPIs implemented
10329 13:32:23.859650 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10330 13:32:23.866561 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10331 13:32:23.870016 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10332 13:32:23.876093 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10333 13:32:23.889820 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10334 13:32:23.902701 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10335 13:32:23.910061 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10336 13:32:23.916688 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10337 13:32:23.930545 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10338 13:32:23.936562 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10339 13:32:23.943635 <6>[ 0.009175] Console: colour dummy device 80x25
10340 13:32:23.953382 <6>[ 0.013931] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10341 13:32:23.959886 <6>[ 0.024373] pid_max: default: 32768 minimum: 301
10342 13:32:23.962942 <6>[ 0.029243] LSM: Security Framework initializing
10343 13:32:23.969955 <6>[ 0.034159] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10344 13:32:23.979825 <6>[ 0.041766] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10345 13:32:23.986445 <6>[ 0.050994] cblist_init_generic: Setting adjustable number of callback queues.
10346 13:32:23.993701 <6>[ 0.058438] cblist_init_generic: Setting shift to 3 and lim to 1.
10347 13:32:24.003263 <6>[ 0.064795] cblist_init_generic: Setting adjustable number of callback queues.
10348 13:32:24.006526 <6>[ 0.072267] cblist_init_generic: Setting shift to 3 and lim to 1.
10349 13:32:24.012670 <6>[ 0.078666] rcu: Hierarchical SRCU implementation.
10350 13:32:24.019782 <6>[ 0.083681] rcu: Max phase no-delay instances is 1000.
10351 13:32:24.026288 <6>[ 0.090707] EFI services will not be available.
10352 13:32:24.029218 <6>[ 0.095659] smp: Bringing up secondary CPUs ...
10353 13:32:24.037431 <6>[ 0.100735] Detected VIPT I-cache on CPU1
10354 13:32:24.043578 <6>[ 0.100805] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10355 13:32:24.050929 <6>[ 0.100835] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10356 13:32:24.053702 <6>[ 0.101164] Detected VIPT I-cache on CPU2
10357 13:32:24.064027 <6>[ 0.101213] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10358 13:32:24.070730 <6>[ 0.101228] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10359 13:32:24.073323 <6>[ 0.101480] Detected VIPT I-cache on CPU3
10360 13:32:24.080374 <6>[ 0.101526] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10361 13:32:24.086887 <6>[ 0.101539] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10362 13:32:24.091120 <6>[ 0.101839] CPU features: detected: Spectre-v4
10363 13:32:24.096815 <6>[ 0.101845] CPU features: detected: Spectre-BHB
10364 13:32:24.099961 <6>[ 0.101849] Detected PIPT I-cache on CPU4
10365 13:32:24.106889 <6>[ 0.101906] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10366 13:32:24.113061 <6>[ 0.101923] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10367 13:32:24.120096 <6>[ 0.102210] Detected PIPT I-cache on CPU5
10368 13:32:24.126613 <6>[ 0.102274] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10369 13:32:24.133186 <6>[ 0.102291] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10370 13:32:24.136108 <6>[ 0.102569] Detected PIPT I-cache on CPU6
10371 13:32:24.143360 <6>[ 0.102631] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10372 13:32:24.149675 <6>[ 0.102647] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10373 13:32:24.156179 <6>[ 0.102946] Detected PIPT I-cache on CPU7
10374 13:32:24.163096 <6>[ 0.103011] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10375 13:32:24.169430 <6>[ 0.103027] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10376 13:32:24.172745 <6>[ 0.103075] smp: Brought up 1 node, 8 CPUs
10377 13:32:24.179365 <6>[ 0.244385] SMP: Total of 8 processors activated.
10378 13:32:24.182486 <6>[ 0.249306] CPU features: detected: 32-bit EL0 Support
10379 13:32:24.192466 <6>[ 0.254668] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10380 13:32:24.198933 <6>[ 0.263469] CPU features: detected: Common not Private translations
10381 13:32:24.205429 <6>[ 0.269944] CPU features: detected: CRC32 instructions
10382 13:32:24.208485 <6>[ 0.275296] CPU features: detected: RCpc load-acquire (LDAPR)
10383 13:32:24.215400 <6>[ 0.281255] CPU features: detected: LSE atomic instructions
10384 13:32:24.222489 <6>[ 0.287037] CPU features: detected: Privileged Access Never
10385 13:32:24.228929 <6>[ 0.292816] CPU features: detected: RAS Extension Support
10386 13:32:24.235655 <6>[ 0.298425] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10387 13:32:24.238784 <6>[ 0.305645] CPU: All CPU(s) started at EL2
10388 13:32:24.244900 <6>[ 0.309961] alternatives: applying system-wide alternatives
10389 13:32:24.253746 <6>[ 0.319863] devtmpfs: initialized
10390 13:32:24.268693 <6>[ 0.328000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10391 13:32:24.275656 <6>[ 0.337962] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10392 13:32:24.282135 <6>[ 0.346198] pinctrl core: initialized pinctrl subsystem
10393 13:32:24.285256 <6>[ 0.352837] DMI not present or invalid.
10394 13:32:24.292084 <6>[ 0.357242] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10395 13:32:24.301718 <6>[ 0.364093] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10396 13:32:24.308217 <6>[ 0.371540] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10397 13:32:24.318367 <6>[ 0.379629] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10398 13:32:24.322018 <6>[ 0.387786] audit: initializing netlink subsys (disabled)
10399 13:32:24.331668 <5>[ 0.393485] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10400 13:32:24.337781 <6>[ 0.394180] thermal_sys: Registered thermal governor 'step_wise'
10401 13:32:24.344847 <6>[ 0.401452] thermal_sys: Registered thermal governor 'power_allocator'
10402 13:32:24.348317 <6>[ 0.407709] cpuidle: using governor menu
10403 13:32:24.354328 <6>[ 0.418667] NET: Registered PF_QIPCRTR protocol family
10404 13:32:24.361699 <6>[ 0.424150] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10405 13:32:24.364215 <6>[ 0.431253] ASID allocator initialised with 32768 entries
10406 13:32:24.372149 <6>[ 0.437790] Serial: AMBA PL011 UART driver
10407 13:32:24.381060 <4>[ 0.446427] Trying to register duplicate clock ID: 134
10408 13:32:24.435001 <6>[ 0.503855] KASLR enabled
10409 13:32:24.448944 <6>[ 0.511536] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10410 13:32:24.456232 <6>[ 0.518549] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10411 13:32:24.462454 <6>[ 0.525038] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10412 13:32:24.469040 <6>[ 0.532043] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10413 13:32:24.475443 <6>[ 0.538532] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10414 13:32:24.482389 <6>[ 0.545533] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10415 13:32:24.488641 <6>[ 0.552021] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10416 13:32:24.495281 <6>[ 0.559025] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10417 13:32:24.498965 <6>[ 0.566526] ACPI: Interpreter disabled.
10418 13:32:24.506987 <6>[ 0.572926] iommu: Default domain type: Translated
10419 13:32:24.514053 <6>[ 0.578039] iommu: DMA domain TLB invalidation policy: strict mode
10420 13:32:24.517325 <5>[ 0.584686] SCSI subsystem initialized
10421 13:32:24.524008 <6>[ 0.588847] usbcore: registered new interface driver usbfs
10422 13:32:24.530641 <6>[ 0.594580] usbcore: registered new interface driver hub
10423 13:32:24.533384 <6>[ 0.600132] usbcore: registered new device driver usb
10424 13:32:24.541475 <6>[ 0.606225] pps_core: LinuxPPS API ver. 1 registered
10425 13:32:24.550204 <6>[ 0.611419] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10426 13:32:24.553445 <6>[ 0.620768] PTP clock support registered
10427 13:32:24.556979 <6>[ 0.625012] EDAC MC: Ver: 3.0.0
10428 13:32:24.564375 <6>[ 0.630154] FPGA manager framework
10429 13:32:24.570973 <6>[ 0.633836] Advanced Linux Sound Architecture Driver Initialized.
10430 13:32:24.574061 <6>[ 0.640606] vgaarb: loaded
10431 13:32:24.580978 <6>[ 0.643702] clocksource: Switched to clocksource arch_sys_counter
10432 13:32:24.584465 <5>[ 0.650137] VFS: Disk quotas dquot_6.6.0
10433 13:32:24.591215 <6>[ 0.654322] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10434 13:32:24.593769 <6>[ 0.661510] pnp: PnP ACPI: disabled
10435 13:32:24.602882 <6>[ 0.668193] NET: Registered PF_INET protocol family
10436 13:32:24.609130 <6>[ 0.673572] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10437 13:32:24.621171 <6>[ 0.683582] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10438 13:32:24.631421 <6>[ 0.692368] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10439 13:32:24.637289 <6>[ 0.700336] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10440 13:32:24.644337 <6>[ 0.708739] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10441 13:32:24.655454 <6>[ 0.717391] TCP: Hash tables configured (established 32768 bind 32768)
10442 13:32:24.661340 <6>[ 0.724250] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10443 13:32:24.668076 <6>[ 0.731270] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10444 13:32:24.674501 <6>[ 0.738790] NET: Registered PF_UNIX/PF_LOCAL protocol family
10445 13:32:24.681524 <6>[ 0.744930] RPC: Registered named UNIX socket transport module.
10446 13:32:24.684826 <6>[ 0.751087] RPC: Registered udp transport module.
10447 13:32:24.691251 <6>[ 0.756017] RPC: Registered tcp transport module.
10448 13:32:24.698162 <6>[ 0.760949] RPC: Registered tcp NFSv4.1 backchannel transport module.
10449 13:32:24.701483 <6>[ 0.767614] PCI: CLS 0 bytes, default 64
10450 13:32:24.703944 <6>[ 0.772003] Unpacking initramfs...
10451 13:32:24.714381 <6>[ 0.775690] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10452 13:32:24.720691 <6>[ 0.784344] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10453 13:32:24.727973 <6>[ 0.793182] kvm [1]: IPA Size Limit: 40 bits
10454 13:32:24.731147 <6>[ 0.797708] kvm [1]: GICv3: no GICV resource entry
10455 13:32:24.737459 <6>[ 0.802729] kvm [1]: disabling GICv2 emulation
10456 13:32:24.744077 <6>[ 0.807413] kvm [1]: GIC system register CPU interface enabled
10457 13:32:24.747409 <6>[ 0.813578] kvm [1]: vgic interrupt IRQ18
10458 13:32:24.753889 <6>[ 0.817951] kvm [1]: VHE mode initialized successfully
10459 13:32:24.757435 <5>[ 0.824378] Initialise system trusted keyrings
10460 13:32:24.764557 <6>[ 0.829173] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10461 13:32:24.773774 <6>[ 0.839121] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10462 13:32:24.780142 <5>[ 0.845491] NFS: Registering the id_resolver key type
10463 13:32:24.783423 <5>[ 0.850787] Key type id_resolver registered
10464 13:32:24.789923 <5>[ 0.855200] Key type id_legacy registered
10465 13:32:24.796620 <6>[ 0.859479] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10466 13:32:24.803141 <6>[ 0.866400] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10467 13:32:24.809471 <6>[ 0.874137] 9p: Installing v9fs 9p2000 file system support
10468 13:32:24.846298 <5>[ 0.911565] Key type asymmetric registered
10469 13:32:24.848937 <5>[ 0.915895] Asymmetric key parser 'x509' registered
10470 13:32:24.859086 <6>[ 0.921043] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10471 13:32:24.862305 <6>[ 0.928656] io scheduler mq-deadline registered
10472 13:32:24.865365 <6>[ 0.933416] io scheduler kyber registered
10473 13:32:24.884860 <6>[ 0.950362] EINJ: ACPI disabled.
10474 13:32:24.916450 <4>[ 0.975743] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10475 13:32:24.926297 <4>[ 0.986359] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10476 13:32:24.941307 <6>[ 1.007143] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10477 13:32:24.949114 <6>[ 1.015188] printk: console [ttyS0] disabled
10478 13:32:24.977611 <6>[ 1.039839] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10479 13:32:24.983922 <6>[ 1.049313] printk: console [ttyS0] enabled
10480 13:32:24.987099 <6>[ 1.049313] printk: console [ttyS0] enabled
10481 13:32:24.993848 <6>[ 1.058208] printk: bootconsole [mtk8250] disabled
10482 13:32:24.997408 <6>[ 1.058208] printk: bootconsole [mtk8250] disabled
10483 13:32:25.004042 <6>[ 1.069459] SuperH (H)SCI(F) driver initialized
10484 13:32:25.007191 <6>[ 1.074740] msm_serial: driver initialized
10485 13:32:25.021337 <6>[ 1.083638] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10486 13:32:25.030951 <6>[ 1.092194] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10487 13:32:25.037814 <6>[ 1.100737] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10488 13:32:25.047570 <6>[ 1.109366] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10489 13:32:25.057691 <6>[ 1.118073] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10490 13:32:25.064506 <6>[ 1.126793] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10491 13:32:25.074627 <6>[ 1.135335] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10492 13:32:25.080906 <6>[ 1.144142] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10493 13:32:25.091108 <6>[ 1.152686] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10494 13:32:25.102615 <6>[ 1.168178] loop: module loaded
10495 13:32:25.108560 <6>[ 1.174166] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10496 13:32:25.130820 <4>[ 1.196883] mtk-pmic-keys: Failed to locate of_node [id: -1]
10497 13:32:25.138349 <6>[ 1.203812] megasas: 07.719.03.00-rc1
10498 13:32:25.147620 <6>[ 1.213535] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10499 13:32:25.157675 <6>[ 1.223099] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10500 13:32:25.174107 <6>[ 1.239714] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10501 13:32:25.230315 <6>[ 1.289362] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10502 13:32:28.715565 <6>[ 4.781942] Freeing initrd memory: 96008K
10503 13:32:28.725904 <6>[ 4.792078] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10504 13:32:28.736579 <6>[ 4.802902] tun: Universal TUN/TAP device driver, 1.6
10505 13:32:28.740349 <6>[ 4.808963] thunder_xcv, ver 1.0
10506 13:32:28.743180 <6>[ 4.812486] thunder_bgx, ver 1.0
10507 13:32:28.746986 <6>[ 4.815980] nicpf, ver 1.0
10508 13:32:28.756738 <6>[ 4.819982] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10509 13:32:28.760423 <6>[ 4.827457] hns3: Copyright (c) 2017 Huawei Corporation.
10510 13:32:28.767024 <6>[ 4.833044] hclge is initializing
10511 13:32:28.770693 <6>[ 4.836624] e1000: Intel(R) PRO/1000 Network Driver
10512 13:32:28.777095 <6>[ 4.841752] e1000: Copyright (c) 1999-2006 Intel Corporation.
10513 13:32:28.780070 <6>[ 4.847765] e1000e: Intel(R) PRO/1000 Network Driver
10514 13:32:28.787046 <6>[ 4.852981] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10515 13:32:28.793960 <6>[ 4.859165] igb: Intel(R) Gigabit Ethernet Network Driver
10516 13:32:28.799939 <6>[ 4.864815] igb: Copyright (c) 2007-2014 Intel Corporation.
10517 13:32:28.806714 <6>[ 4.870652] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10518 13:32:28.813291 <6>[ 4.877169] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10519 13:32:28.816797 <6>[ 4.883625] sky2: driver version 1.30
10520 13:32:28.823027 <6>[ 4.888610] VFIO - User Level meta-driver version: 0.3
10521 13:32:28.830682 <6>[ 4.896836] usbcore: registered new interface driver usb-storage
10522 13:32:28.836839 <6>[ 4.903282] usbcore: registered new device driver onboard-usb-hub
10523 13:32:28.846157 <6>[ 4.912368] mt6397-rtc mt6359-rtc: registered as rtc0
10524 13:32:28.856217 <6>[ 4.917834] mt6397-rtc mt6359-rtc: setting system clock to 2023-09-08T13:32:28 UTC (1694179948)
10525 13:32:28.859495 <6>[ 4.927392] i2c_dev: i2c /dev entries driver
10526 13:32:28.876341 <6>[ 4.939029] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10527 13:32:28.896666 <6>[ 4.963006] cpu cpu0: EM: created perf domain
10528 13:32:28.899749 <6>[ 4.967942] cpu cpu4: EM: created perf domain
10529 13:32:28.907527 <6>[ 4.973466] sdhci: Secure Digital Host Controller Interface driver
10530 13:32:28.913737 <6>[ 4.979898] sdhci: Copyright(c) Pierre Ossman
10531 13:32:28.920483 <6>[ 4.984809] Synopsys Designware Multimedia Card Interface Driver
10532 13:32:28.927078 <6>[ 4.991395] sdhci-pltfm: SDHCI platform and OF driver helper
10533 13:32:28.930331 <6>[ 4.991522] mmc0: CQHCI version 5.10
10534 13:32:28.936544 <6>[ 5.001498] ledtrig-cpu: registered to indicate activity on CPUs
10535 13:32:28.943346 <6>[ 5.008555] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10536 13:32:28.950111 <6>[ 5.015581] usbcore: registered new interface driver usbhid
10537 13:32:28.953270 <6>[ 5.021403] usbhid: USB HID core driver
10538 13:32:28.960402 <6>[ 5.025582] spi_master spi0: will run message pump with realtime priority
10539 13:32:29.003887 <6>[ 5.063797] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10540 13:32:29.023771 <6>[ 5.079976] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10541 13:32:29.030259 <6>[ 5.094595] cros-ec-spi spi0.0: Chrome EC device registered
10542 13:32:29.033872 <6>[ 5.094633] mmc0: Command Queue Engine enabled
10543 13:32:29.040859 <6>[ 5.105197] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10544 13:32:29.046670 <6>[ 5.112490] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10545 13:32:29.059472 <6>[ 5.126091] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10546 13:32:29.069480 <6>[ 5.128905] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10547 13:32:29.076707 <6>[ 5.133179] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10548 13:32:29.079912 <6>[ 5.142221] NET: Registered PF_PACKET protocol family
10549 13:32:29.086131 <6>[ 5.147282] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10550 13:32:29.089523 <6>[ 5.151883] 9pnet: Installing 9P2000 support
10551 13:32:29.096093 <6>[ 5.157740] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10552 13:32:29.102958 <5>[ 5.161608] Key type dns_resolver registered
10553 13:32:29.105934 <6>[ 5.173072] registered taskstats version 1
10554 13:32:29.112599 <5>[ 5.177448] Loading compiled-in X.509 certificates
10555 13:32:29.140117 <4>[ 5.199679] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10556 13:32:29.150113 <4>[ 5.210602] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10557 13:32:29.156553 <3>[ 5.221149] debugfs: File 'uA_load' in directory '/' already present!
10558 13:32:29.163060 <3>[ 5.227911] debugfs: File 'min_uV' in directory '/' already present!
10559 13:32:29.169649 <3>[ 5.234547] debugfs: File 'max_uV' in directory '/' already present!
10560 13:32:29.176668 <3>[ 5.241242] debugfs: File 'constraint_flags' in directory '/' already present!
10561 13:32:29.187986 <3>[ 5.250692] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10562 13:32:29.197126 <6>[ 5.263462] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10563 13:32:29.204030 <6>[ 5.270221] xhci-mtk 11200000.usb: xHCI Host Controller
10564 13:32:29.210932 <6>[ 5.275709] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10565 13:32:29.220902 <6>[ 5.283653] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10566 13:32:29.227613 <6>[ 5.293095] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10567 13:32:29.233721 <6>[ 5.299157] xhci-mtk 11200000.usb: xHCI Host Controller
10568 13:32:29.240577 <6>[ 5.304633] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10569 13:32:29.247025 <6>[ 5.312286] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10570 13:32:29.254224 <6>[ 5.320108] hub 1-0:1.0: USB hub found
10571 13:32:29.257087 <6>[ 5.324128] hub 1-0:1.0: 1 port detected
10572 13:32:29.267264 <6>[ 5.328398] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10573 13:32:29.270382 <6>[ 5.337155] hub 2-0:1.0: USB hub found
10574 13:32:29.274029 <6>[ 5.341178] hub 2-0:1.0: 1 port detected
10575 13:32:29.282185 <6>[ 5.348525] mtk-msdc 11f70000.mmc: Got CD GPIO
10576 13:32:29.292612 <6>[ 5.354830] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10577 13:32:29.299214 <6>[ 5.362855] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10578 13:32:29.308697 <4>[ 5.370744] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10579 13:32:29.318831 <6>[ 5.380260] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10580 13:32:29.325288 <6>[ 5.388337] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10581 13:32:29.332335 <6>[ 5.396445] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10582 13:32:29.341749 <6>[ 5.404370] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10583 13:32:29.348838 <6>[ 5.412186] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10584 13:32:29.358324 <6>[ 5.420002] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10585 13:32:29.368318 <6>[ 5.430468] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10586 13:32:29.375338 <6>[ 5.438852] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10587 13:32:29.385179 <6>[ 5.447193] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10588 13:32:29.391894 <6>[ 5.455531] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10589 13:32:29.401483 <6>[ 5.463868] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10590 13:32:29.407939 <6>[ 5.472208] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10591 13:32:29.418618 <6>[ 5.480554] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10592 13:32:29.425393 <6>[ 5.488892] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10593 13:32:29.434043 <6>[ 5.497229] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10594 13:32:29.441592 <6>[ 5.505566] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10595 13:32:29.450720 <6>[ 5.513904] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10596 13:32:29.457369 <6>[ 5.522241] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10597 13:32:29.468021 <6>[ 5.530579] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10598 13:32:29.477673 <6>[ 5.538917] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10599 13:32:29.484261 <6>[ 5.547256] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10600 13:32:29.491064 <6>[ 5.556046] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10601 13:32:29.497608 <6>[ 5.563216] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10602 13:32:29.504397 <6>[ 5.569961] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10603 13:32:29.510289 <6>[ 5.576704] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10604 13:32:29.517496 <6>[ 5.583617] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10605 13:32:29.527355 <6>[ 5.590460] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10606 13:32:29.537027 <6>[ 5.599590] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10607 13:32:29.547042 <6>[ 5.608709] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10608 13:32:29.556829 <6>[ 5.618003] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10609 13:32:29.566987 <6>[ 5.627470] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10610 13:32:29.573923 <6>[ 5.636937] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10611 13:32:29.583910 <6>[ 5.646070] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10612 13:32:29.593345 <6>[ 5.655536] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10613 13:32:29.603677 <6>[ 5.664654] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10614 13:32:29.613670 <6>[ 5.673949] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10615 13:32:29.623678 <6>[ 5.684108] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10616 13:32:29.632757 <6>[ 5.695635] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10617 13:32:29.665304 <6>[ 5.728064] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10618 13:32:29.692387 <6>[ 5.758484] hub 2-1:1.0: USB hub found
10619 13:32:29.695522 <6>[ 5.762885] hub 2-1:1.0: 3 ports detected
10620 13:32:29.817010 <6>[ 5.879992] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10621 13:32:29.971719 <6>[ 6.037980] hub 1-1:1.0: USB hub found
10622 13:32:29.974881 <6>[ 6.042409] hub 1-1:1.0: 4 ports detected
10623 13:32:30.053306 <6>[ 6.116295] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10624 13:32:30.297159 <6>[ 6.360023] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10625 13:32:30.429633 <6>[ 6.495783] hub 1-1.4:1.0: USB hub found
10626 13:32:30.432828 <6>[ 6.500438] hub 1-1.4:1.0: 2 ports detected
10627 13:32:30.728855 <6>[ 6.791998] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10628 13:32:30.921466 <6>[ 6.983994] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10629 13:32:41.930278 <6>[ 18.001004] ALSA device list:
10630 13:32:41.936764 <6>[ 18.004294] No soundcards found.
10631 13:32:41.944661 <6>[ 18.012078] Freeing unused kernel memory: 8384K
10632 13:32:41.947655 <6>[ 18.017165] Run /init as init process
10633 13:32:41.993166 <6>[ 18.061222] NET: Registered PF_INET6 protocol family
10634 13:32:41.996885 <6>[ 18.067175] Segment Routing with IPv6
10635 13:32:42.003280 <6>[ 18.071130] In-situ OAM (IOAM) with IPv6
10636 13:32:42.037342 <30>[ 18.084918] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10637 13:32:42.040386 <30>[ 18.108837] systemd[1]: Detected architecture arm64.
10638 13:32:42.040888
10639 13:32:42.047215 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10640 13:32:42.047686
10641 13:32:42.060331 <30>[ 18.128001] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10642 13:32:42.195334 <30>[ 18.259494] systemd[1]: Queued start job for default target Graphical Interface.
10643 13:32:42.216903 <30>[ 18.284636] systemd[1]: Created slice system-getty.slice.
10644 13:32:42.223358 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10645 13:32:42.241267 <30>[ 18.308757] systemd[1]: Created slice system-modprobe.slice.
10646 13:32:42.247872 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10647 13:32:42.265536 <30>[ 18.333219] systemd[1]: Created slice system-serial\x2dgetty.slice.
10648 13:32:42.275693 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10649 13:32:42.288655 <30>[ 18.356311] systemd[1]: Created slice User and Session Slice.
10650 13:32:42.295113 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10651 13:32:42.316843 <30>[ 18.380657] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10652 13:32:42.325948 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10653 13:32:42.343842 <30>[ 18.408267] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10654 13:32:42.350281 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10655 13:32:42.370678 <30>[ 18.432073] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10656 13:32:42.377722 <30>[ 18.444236] systemd[1]: Reached target Local Encrypted Volumes.
10657 13:32:42.384087 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10658 13:32:42.400108 <30>[ 18.468477] systemd[1]: Reached target Paths.
10659 13:32:42.407293 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10660 13:32:42.420066 <30>[ 18.488008] systemd[1]: Reached target Remote File Systems.
10661 13:32:42.426415 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10662 13:32:42.444770 <30>[ 18.512344] systemd[1]: Reached target Slices.
10663 13:32:42.450869 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10664 13:32:42.464157 <30>[ 18.532065] systemd[1]: Reached target Swap.
10665 13:32:42.468112 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10666 13:32:42.488345 <30>[ 18.552512] systemd[1]: Listening on initctl Compatibility Named Pipe.
10667 13:32:42.494879 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10668 13:32:42.501357 <30>[ 18.567663] systemd[1]: Listening on Journal Audit Socket.
10669 13:32:42.507620 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10670 13:32:42.521006 <30>[ 18.588501] systemd[1]: Listening on Journal Socket (/dev/log).
10671 13:32:42.527214 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10672 13:32:42.545115 <30>[ 18.613216] systemd[1]: Listening on Journal Socket.
10673 13:32:42.551706 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10674 13:32:42.565045 <30>[ 18.632591] systemd[1]: Listening on udev Control Socket.
10675 13:32:42.571894 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10676 13:32:42.589435 <30>[ 18.656993] systemd[1]: Listening on udev Kernel Socket.
10677 13:32:42.595960 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10678 13:32:42.652638 <30>[ 18.720349] systemd[1]: Mounting Huge Pages File System...
10679 13:32:42.659154 Mounting [0;1;39mHuge Pages File System[0m...
10680 13:32:42.677500 <30>[ 18.741902] systemd[1]: Mounting POSIX Message Queue File System...
10681 13:32:42.680985 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10682 13:32:42.698374 <30>[ 18.765934] systemd[1]: Mounting Kernel Debug File System...
10683 13:32:42.704929 Mounting [0;1;39mKernel Debug File System[0m...
10684 13:32:42.723205 <30>[ 18.788220] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10685 13:32:42.734078 <30>[ 18.799007] systemd[1]: Starting Create list of static device nodes for the current kernel...
10686 13:32:42.740628 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10687 13:32:42.760226 <30>[ 18.828309] systemd[1]: Starting Load Kernel Module configfs...
10688 13:32:42.766311 Starting [0;1;39mLoad Kernel Module configfs[0m...
10689 13:32:42.782771 <30>[ 18.851127] systemd[1]: Starting Load Kernel Module drm...
10690 13:32:42.789130 Starting [0;1;39mLoad Kernel Module drm[0m...
10691 13:32:42.807779 <30>[ 18.872346] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10692 13:32:42.822055 <30>[ 18.889367] systemd[1]: Starting Journal Service...
10693 13:32:42.824453 Starting [0;1;39mJournal Service[0m...
10694 13:32:42.842654 <30>[ 18.910526] systemd[1]: Starting Load Kernel Modules...
10695 13:32:42.849585 Starting [0;1;39mLoad Kernel Modules[0m...
10696 13:32:42.871539 <30>[ 18.935689] systemd[1]: Starting Remount Root and Kernel File Systems...
10697 13:32:42.878020 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10698 13:32:42.895771 <30>[ 18.963264] systemd[1]: Starting Coldplug All udev Devices...
10699 13:32:42.902125 Starting [0;1;39mColdplug All udev Devices[0m...
10700 13:32:42.919025 <30>[ 18.986874] systemd[1]: Started Journal Service.
10701 13:32:42.925722 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10702 13:32:42.946825 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10703 13:32:42.965180 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10704 13:32:42.981435 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10705 13:32:43.001476 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10706 13:32:43.018355 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10707 13:32:43.038757 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10708 13:32:43.062521 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10709 13:32:43.081930 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10710 13:32:43.096312 See 'systemctl status systemd-remount-fs.service' for details.
10711 13:32:43.136481 Mounting [0;1;39mKernel Configuration File System[0m...
10712 13:32:43.156927 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10713 13:32:43.169431 <46>[ 19.233702] systemd-journald[184]: Received client request to flush runtime journal.
10714 13:32:43.179702 Starting [0;1;39mLoad/Save Random Seed[0m...
10715 13:32:43.201676 Starting [0;1;39mApply Kernel Variables[0m...
10716 13:32:43.221122 Starting [0;1;39mCreate System Users[0m...
10717 13:32:43.240160 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10718 13:32:43.257881 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10719 13:32:43.277360 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10720 13:32:43.290696 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10721 13:32:43.309425 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10722 13:32:43.325773 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10723 13:32:43.365452 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10724 13:32:43.384838 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10725 13:32:43.396324 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10726 13:32:43.411969 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10727 13:32:43.449056 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10728 13:32:43.478629 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10729 13:32:43.499160 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10730 13:32:43.518641 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10731 13:32:43.541584 Starting [0;1;39mNetwork Time Synchronization[0m...
10732 13:32:43.563108 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10733 13:32:43.599619 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10734 13:32:43.629361 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10735 13:32:43.654192 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10736 13:32:43.668169 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10737 13:32:43.683899 <6>[ 19.748078] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10738 13:32:43.690216 <6>[ 19.755754] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10739 13:32:43.700007 <6>[ 19.764665] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10740 13:32:43.706201 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10741 13:32:43.717881 <3>[ 19.782037] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10742 13:32:43.724200 <3>[ 19.790229] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10743 13:32:43.733930 <3>[ 19.798341] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10744 13:32:43.740466 <6>[ 19.799286] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10745 13:32:43.744381 <6>[ 19.805794] mc: Linux media interface: v0.10
10746 13:32:43.750750 <6>[ 19.805923] usbcore: registered new interface driver r8152
10747 13:32:43.760718 <3>[ 19.814865] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10748 13:32:43.766643 <4>[ 19.820647] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10749 13:32:43.773667 <3>[ 19.824380] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10750 13:32:43.783276 <4>[ 19.838827] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10751 13:32:43.786479 <6>[ 19.839206] remoteproc remoteproc0: scp is available
10752 13:32:43.793853 <6>[ 19.839296] remoteproc remoteproc0: powering up scp
10753 13:32:43.799873 <6>[ 19.839302] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10754 13:32:43.806821 <6>[ 19.839332] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10755 13:32:43.816629 <3>[ 19.839672] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10756 13:32:43.823084 <6>[ 19.858680] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10757 13:32:43.829772 <6>[ 19.860103] videodev: Linux video capture interface: v2.00
10758 13:32:43.836603 <3>[ 19.861601] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10759 13:32:43.846533 <4>[ 19.885724] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10760 13:32:43.850142 <4>[ 19.885724] Fallback method does not support PEC.
10761 13:32:43.859875 <3>[ 19.888085] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10762 13:32:43.867213 <6>[ 19.897301] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10763 13:32:43.873752 <3>[ 19.901902] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10764 13:32:43.880598 <6>[ 19.909947] pci_bus 0000:00: root bus resource [bus 00-ff]
10765 13:32:43.886912 <3>[ 19.912758] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10766 13:32:43.897303 <6>[ 19.920419] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10767 13:32:43.907497 <6>[ 19.920763] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10768 13:32:43.913641 <3>[ 19.923484] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10769 13:32:43.923940 <6>[ 19.931596] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10770 13:32:43.930927 <3>[ 19.939083] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10771 13:32:43.941153 <6>[ 19.946527] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10772 13:32:43.947868 <3>[ 19.948969] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10773 13:32:43.957717 <3>[ 19.949742] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10774 13:32:43.964449 <6>[ 19.952265] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10775 13:32:43.974722 <3>[ 19.952827] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10776 13:32:43.981794 <3>[ 19.952936] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10777 13:32:43.987929 <3>[ 19.952947] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10778 13:32:43.998886 <3>[ 19.952955] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10779 13:32:44.005621 <3>[ 19.952968] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10780 13:32:44.015235 <3>[ 19.952976] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10781 13:32:44.022513 <3>[ 19.953055] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10782 13:32:44.029749 <6>[ 19.961170] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10783 13:32:44.035908 <6>[ 19.964529] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10784 13:32:44.042954 <6>[ 19.964580] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10785 13:32:44.050116 <6>[ 19.964588] remoteproc remoteproc0: remote processor scp is now up
10786 13:32:44.059894 <6>[ 19.968621] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10787 13:32:44.069829 <4>[ 19.993181] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10788 13:32:44.076240 <6>[ 19.995400] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10789 13:32:44.083332 <6>[ 19.997018] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10790 13:32:44.093745 <6>[ 20.000589] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10791 13:32:44.100437 <4>[ 20.003509] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10792 13:32:44.107141 <6>[ 20.003709] usbcore: registered new interface driver cdc_ether
10793 13:32:44.110456 <6>[ 20.013419] pci 0000:00:00.0: supports D1 D2
10794 13:32:44.120134 <3>[ 20.013582] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10795 13:32:44.127840 <6>[ 20.013973] usbcore: registered new interface driver r8153_ecm
10796 13:32:44.130815 <6>[ 20.014028] Bluetooth: Core ver 2.22
10797 13:32:44.133882 <6>[ 20.014131] NET: Registered PF_BLUETOOTH protocol family
10798 13:32:44.141313 <6>[ 20.014134] Bluetooth: HCI device and connection manager initialized
10799 13:32:44.147581 <6>[ 20.014160] Bluetooth: HCI socket layer initialized
10800 13:32:44.150961 <6>[ 20.014165] Bluetooth: L2CAP socket layer initialized
10801 13:32:44.158012 <6>[ 20.014175] Bluetooth: SCO socket layer initialized
10802 13:32:44.164419 <3>[ 20.046562] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10803 13:32:44.175725 <6>[ 20.054513] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10804 13:32:44.181907 <6>[ 20.056388] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10805 13:32:44.188933 <3>[ 20.062841] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10806 13:32:44.195346 <6>[ 20.070850] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10807 13:32:44.201961 <6>[ 20.072822] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10808 13:32:44.215012 <6>[ 20.073996] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10809 13:32:44.221866 <6>[ 20.074142] usbcore: registered new interface driver uvcvideo
10810 13:32:44.227909 <3>[ 20.075225] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10811 13:32:44.235260 <6>[ 20.087445] usbcore: registered new interface driver btusb
10812 13:32:44.245060 <4>[ 20.088073] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10813 13:32:44.251619 <3>[ 20.088083] Bluetooth: hci0: Failed to load firmware file (-2)
10814 13:32:44.258407 <3>[ 20.088086] Bluetooth: hci0: Failed to set up firmware (-2)
10815 13:32:44.268041 <4>[ 20.088090] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10816 13:32:44.274674 <6>[ 20.095009] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10817 13:32:44.284798 <3>[ 20.099433] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10818 13:32:44.287289 <6>[ 20.101320] r8152 2-1.3:1.0 eth0: v1.12.13
10819 13:32:44.294627 <6>[ 20.101897] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10820 13:32:44.304203 <6>[ 20.108315] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10821 13:32:44.310723 <3>[ 20.120979] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10822 13:32:44.317140 <6>[ 20.123252] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10823 13:32:44.323803 <6>[ 20.124665] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10824 13:32:44.333722 <3>[ 20.152894] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10825 13:32:44.337396 <6>[ 20.157383] pci 0000:01:00.0: supports D1 D2
10826 13:32:44.343992 <6>[ 20.411281] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10827 13:32:44.354304 Startin<6>[ 20.419926] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10828 13:32:44.361131 <6>[ 20.427461] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10829 13:32:44.370873 <6>[ 20.435555] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10830 13:32:44.377582 <6>[ 20.443552] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10831 13:32:44.387843 <6>[ 20.451551] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10832 13:32:44.394092 <6>[ 20.459553] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10833 13:32:44.400919 <6>[ 20.467553] pci 0000:00:00.0: PCI bridge to [bus 01]
10834 13:32:44.407609 <6>[ 20.472768] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10835 13:32:44.413981 g [0;1;39mLoad/<6>[ 20.480906] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10836 13:32:44.423842 Save Screen …o<6>[ 20.489173] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10837 13:32:44.430427 f leds:white:kbd<6>[ 20.496875] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10838 13:32:44.433548 _backlight[0m...
10839 13:32:44.448832 <5>[ 20.513246] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10840 13:32:44.459739 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10841 13:32:44.466379 <5>[ 20.532469] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10842 13:32:44.475958 <4>[ 20.539553] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10843 13:32:44.479761 <6>[ 20.548446] cfg80211: failed to load regulatory.db
10844 13:32:44.486156 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10845 13:32:44.526965 <6>[ 20.591452] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10846 13:32:44.533717 <6>[ 20.598944] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10847 13:32:44.556116 <6>[ 20.623897] mt7921e 0000:01:00.0: ASIC revision: 79610010
10848 13:32:44.643857 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10849 13:32:44.661804 <4>[ 20.723131] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10850 13:32:44.668504 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10851 13:32:44.692454 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10852 13:32:44.707752 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10853 13:32:44.724128 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10854 13:32:44.744066 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10855 13:32:44.759978 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10856 13:32:44.780646 <4>[ 20.842062] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10857 13:32:44.786760 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10858 13:32:44.804235 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10859 13:32:44.849057 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10860 13:32:44.901301 Startin<4>[ 20.963078] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10861 13:32:44.904501 g [0;1;39mUser Login Management[0m...
10862 13:32:44.926825 Starting [0;1;39mPermit User Sessions[0m...
10863 13:32:44.947020 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10864 13:32:44.961065 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10865 13:32:44.976524 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10866 13:32:44.994194 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10867 13:32:45.020267 <4>[ 21.082043] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10868 13:32:45.045383 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10869 13:32:45.064821 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10870 13:32:45.085149 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10871 13:32:45.104837 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10872 13:32:45.138225 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface<4>[ 21.198214] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10873 13:32:45.138747 [0m.
10874 13:32:45.190206 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10875 13:32:45.228899 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10876 13:32:45.257330 <4>[ 21.318868] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10877 13:32:45.290807
10878 13:32:45.291284
10879 13:32:45.294408 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10880 13:32:45.294933
10881 13:32:45.296999 debian-bullseye-arm64 login: root (automatic login)
10882 13:32:45.297386
10883 13:32:45.297660
10884 13:32:45.325159 Linux debian-bullseye-arm64 6.1.52-cip5 #1 SMP PREEMPT Fri Sep 8 13:10:51 UTC 2023 aarch64
10885 13:32:45.325299
10886 13:32:45.332140 The programs included with the Debian GNU/Linux system are free software;
10887 13:32:45.339465 the exact distribution terms for each program are described in the
10888 13:32:45.341879 individual files in /usr/share/doc/*/copyright.
10889 13:32:45.342293
10890 13:32:45.348961 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10891 13:32:45.352073 permitted by applicable law.
10892 13:32:45.353175 Matched prompt #10: / #
10894 13:32:45.354017 Setting prompt string to ['/ #']
10895 13:32:45.354400 end: 2.2.5.1 login-action (duration 00:00:22) [common]
10897 13:32:45.355210 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
10898 13:32:45.355536 start: 2.2.6 expect-shell-connection (timeout 00:03:07) [common]
10899 13:32:45.355796 Setting prompt string to ['/ #']
10900 13:32:45.356013 Forcing a shell prompt, looking for ['/ #']
10902 13:32:45.406634 / #
10903 13:32:45.407192 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10904 13:32:45.407512 Waiting using forced prompt support (timeout 00:02:30)
10905 13:32:45.407887 <4>[ 21.438517] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10906 13:32:45.413139
10907 13:32:45.413958 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10908 13:32:45.414359 start: 2.2.7 export-device-env (timeout 00:03:07) [common]
10909 13:32:45.414731 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10910 13:32:45.415067 end: 2.2 depthcharge-retry (duration 00:01:53) [common]
10911 13:32:45.415393 end: 2 depthcharge-action (duration 00:01:53) [common]
10912 13:32:45.415725 start: 3 lava-test-retry (timeout 00:05:00) [common]
10913 13:32:45.416047 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
10914 13:32:45.416427 Using namespace: common
10916 13:32:45.517606 / # #
10917 13:32:45.518154 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
10918 13:32:45.518610 #<4>[ 21.557975] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10919 13:32:45.524111
10920 13:32:45.524926 Using /lava-11471181
10922 13:32:45.625978 / # export SHELL=/bin/sh
10923 13:32:45.626733 export SHELL=/bin/sh<4>[ 21.673657] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10924 13:32:45.632673
10926 13:32:45.734123 / # . /lava-11471181/environment
10927 13:32:45.734814 . /lava-11471181/environment<4>[ 21.789728] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10928 13:32:45.740320
10930 13:32:45.841795 / # /lava-11471181/bin/lava-test-runner /lava-11471181/0
10931 13:32:45.842365 Test shell timeout: 10s (minimum of the action and connection timeout)
10932 13:32:45.843671 /lava-11471181/bin/lava-test-runner /lava-11471181/0<3>[ 21.903440] mt7921e 0000:01:00.0: hardware init failed
10933 13:32:45.848303
10934 13:32:45.888827 + export TESTRUN_ID=0_sleep
10935 13:32:45.889317 + cd /lava-11471181/0/tests/0_sleep
10936 13:32:45.889595 + cat uuid
10937 13:32:45.889835 + UUID=11471181_1.5.2.3.1
10938 13:32:45.890064 + set +x
10939 13:32:45.890288 <LAVA_SIGNAL_STARTRUN 0_sleep 11471181_1.5.2.3.1>
10940 13:32:45.890512 + ./config/lava/sleep/sleep.sh mem freeze
10941 13:32:45.890995 Received signal: <STARTRUN> 0_sleep 11471181_1.5.2.3.1
10942 13:32:45.891277 Starting test lava.0_sleep (11471181_1.5.2.3.1)
10943 13:32:45.891676 Skipping test definition patterns.
10944 13:32:45.892352 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
10946 13:32:45.893784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
10947 13:32:45.896560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
10948 13:32:45.897174 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
10950 13:32:45.899619 rtcwake: assuming RTC uses UTC ...
10951 13:32:45.906375 rtcwake: wakeup from "mem" usi<6>[ 21.976060] PM: suspend entry (deep)
10952 13:32:45.912813 ng rtc0 at Fri S<6>[ 21.980335] Filesystems sync: 0.000 seconds
10953 13:32:45.916781 ep 8 13:32:51 2023
10954 13:32:45.919431 <6>[ 21.987693] Freezing user space processes
10955 13:32:45.929274 <6>[ 21.994345] Freezing user space processes completed (elapsed 0.001 seconds)
10956 13:32:45.932720 <6>[ 22.001603] OOM killer disabled.
10957 13:32:45.935975 <6>[ 22.005110] Freezing remaining freezable tasks
10958 13:32:45.946678 <6>[ 22.011131] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
10959 13:32:45.952249 <6>[ 22.018829] printk: Suspending console(s) (use no_console_suspend to debug)
10960 13:32:49.332866 <3>[ 25.168075] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
10961 13:32:49.342786 <3>[ 25.168122] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
10962 13:32:49.353070 <3>[ 25.168157] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
10963 13:32:49.359502 <3>[ 25.168193] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
10964 13:32:49.369615 <3>[ 25.168402] PM: Some devices failed to suspend, or early wake event detected
10965 13:32:49.376001 <4>[ 25.184913] typec port0-partner: PM: parent port0 should not be sleeping
10966 13:32:49.379664 <6>[ 25.448538] OOM killer enabled.
10967 13:32:49.390049 <6>[ 25.451950] Restarting tasks ... done.
10968 13:32:49.393183 <5>[ 25.462572] random: crng reseeded on system resumption
10969 13:32:49.396888 <6>[ 25.469128] PM: suspend exit
10970 13:32:49.400696 rtcwake: write error
10971 13:32:49.408415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=fail>
10972 13:32:49.409254 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=fail
10974 13:32:49.411776 rtcwake: assuming RTC uses UTC ...
10975 13:32:49.418667 rtcwake: wakeup from "mem" using rtc0 at Fri Sep 8 13:32:54 2023
10976 13:32:49.432757 <6>[ 25.501293] PM: suspend entry (deep)
10977 13:32:49.435815 <6>[ 25.505217] Filesystems sync: 0.000 seconds
10978 13:32:49.442836 <6>[ 25.510379] Freezing user space processes
10979 13:32:49.449002 <6>[ 25.516497] Freezing user space processes completed (elapsed 0.001 seconds)
10980 13:32:49.453004 <6>[ 25.523738] OOM killer disabled.
10981 13:32:49.459386 <6>[ 25.527217] Freezing remaining freezable tasks
10982 13:32:49.465989 <6>[ 25.533290] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
10983 13:32:49.475750 <6>[ 25.540967] printk: Suspending console(s) (use no_console_suspend to debug)
10984 13:32:52.912815 <3>[ 28.751981] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
10985 13:32:52.922503 <3>[ 28.752005] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
10986 13:32:52.932550 <3>[ 28.752034] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
10987 13:32:52.939306 <3>[ 28.752060] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
10988 13:32:52.945681 <3>[ 28.752440] PM: Some devices failed to suspend, or early wake event detected
10989 13:32:52.952259 <6>[ 29.021456] OOM killer enabled.
10990 13:32:52.955852 <6>[ 29.024873] Restarting tasks ... done.
10991 13:32:52.962867 <5>[ 29.031721] random: crng reseeded on system resumption
10992 13:32:52.966055 <6>[ 29.038472] PM: suspend exit
10993 13:32:52.969347 rtcwake: write error
10994 13:32:52.977711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=fail>
10995 13:32:52.978478 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=fail
10997 13:32:52.981130 rtcwake: assuming RTC uses UTC ...
10998 13:32:52.987704 rtcwake: wakeup from "mem" using rtc0 at Fri Sep 8 13:32:58 2023
10999 13:32:53.002483 <6>[ 29.071236] PM: suspend entry (deep)
11000 13:32:53.005381 <6>[ 29.075132] Filesystems sync: 0.000 seconds
11001 13:32:53.011852 <6>[ 29.080366] Freezing user space processes
11002 13:32:53.019039 <6>[ 29.086508] Freezing user space processes completed (elapsed 0.001 seconds)
11003 13:32:53.021916 <6>[ 29.093732] OOM killer disabled.
11004 13:32:53.029106 <6>[ 29.097220] Freezing remaining freezable tasks
11005 13:32:53.035055 <6>[ 29.103329] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11006 13:32:53.045439 <6>[ 29.111002] printk: Suspending console(s) (use no_console_suspend to debug)
11007 13:32:56.501272 <3>[ 32.336038] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11008 13:32:56.511085 <3>[ 32.336070] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11009 13:32:56.521031 <3>[ 32.336114] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11010 13:32:56.527345 <3>[ 32.336157] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11011 13:32:56.537042 <3>[ 32.336430] PM: Some devices failed to suspend, or early wake event detected
11012 13:32:56.540711 <6>[ 32.610298] OOM killer enabled.
11013 13:32:56.551491 <6>[ 32.613709] Restarting tasks ... done.
11014 13:32:56.554520 <5>[ 32.624595] random: crng reseeded on system resumption
11015 13:32:56.559237 <6>[ 32.631993] PM: suspend exit
11016 13:32:56.562263 rtcwake: write error
11017 13:32:56.570396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=fail>
11018 13:32:56.571171 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=fail
11020 13:32:56.574281 rtcwake: assuming RTC uses UTC ...
11021 13:32:56.580564 rtcwake: wakeup from "mem" using rtc0 at Fri Sep 8 13:33:02 2023
11022 13:32:56.594139 <6>[ 32.663390] PM: suspend entry (deep)
11023 13:32:56.597295 <6>[ 32.667267] Filesystems sync: 0.000 seconds
11024 13:32:56.600137 <6>[ 32.672317] Freezing user space processes
11025 13:32:56.611909 <6>[ 32.678289] Freezing user space processes completed (elapsed 0.001 seconds)
11026 13:32:56.615578 <6>[ 32.685512] OOM killer disabled.
11027 13:32:56.619044 <6>[ 32.688992] Freezing remaining freezable tasks
11028 13:32:56.628980 <6>[ 32.695066] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11029 13:32:56.635899 <6>[ 32.702755] printk: Suspending console(s) (use no_console_suspend to debug)
11030 13:33:00.084377 <3>[ 35.920078] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11031 13:33:00.093911 <3>[ 35.920118] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11032 13:33:00.103389 <3>[ 35.920168] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11033 13:33:00.110937 <3>[ 35.920212] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11034 13:33:00.120451 <3>[ 35.920506] PM: Some devices failed to suspend, or early wake event detected
11035 13:33:00.123827 <6>[ 36.193899] OOM killer enabled.
11036 13:33:00.128005 <6>[ 36.197310] Restarting tasks ... done.
11037 13:33:00.133719 <5>[ 36.203294] random: crng reseeded on system resumption
11038 13:33:00.137267 <6>[ 36.209654] PM: suspend exit
11039 13:33:00.140475 rtcwake: write error
11040 13:33:00.147387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=fail>
11041 13:33:00.148162 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=fail
11043 13:33:00.150762 rtcwake: assuming RTC uses UTC ...
11044 13:33:00.157639 rtcwake: wakeup from "mem" using rtc0 at Fri Sep 8 13:33:05 2023
11045 13:33:00.172238 <6>[ 36.241764] PM: suspend entry (deep)
11046 13:33:00.175415 <6>[ 36.245658] Filesystems sync: 0.000 seconds
11047 13:33:00.178362 <6>[ 36.250795] Freezing user space processes
11048 13:33:00.190338 <6>[ 36.257004] Freezing user space processes completed (elapsed 0.001 seconds)
11049 13:33:00.194254 <6>[ 36.264316] OOM killer disabled.
11050 13:33:00.197064 <6>[ 36.267809] Freezing remaining freezable tasks
11051 13:33:00.207226 <6>[ 36.273879] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11052 13:33:00.213860 <6>[ 36.281565] printk: Suspending console(s) (use no_console_suspend to debug)
11053 13:33:03.663629 <3>[ 39.504071] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11054 13:33:03.673421 <3>[ 39.504109] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11055 13:33:03.683495 <3>[ 39.504153] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11056 13:33:03.689783 <3>[ 39.504195] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11057 13:33:03.700189 <3>[ 39.504477] PM: Some devices failed to suspend, or early wake event detected
11058 13:33:03.703189 <6>[ 39.773707] OOM killer enabled.
11059 13:33:03.706610 <6>[ 39.777120] Restarting tasks ... done.
11060 13:33:03.713629 <5>[ 39.783219] random: crng reseeded on system resumption
11061 13:33:03.717117 <6>[ 39.790564] PM: suspend exit
11062 13:33:03.720195 rtcwake: write error
11063 13:33:03.728465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=fail>
11064 13:33:03.729227 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=fail
11066 13:33:03.731329 rtcwake: assuming RTC uses UTC ...
11067 13:33:03.738178 rtcwake: wakeup from "mem" using rtc0 at Fri Sep 8 13:33:09 2023
11068 13:33:03.750392 <6>[ 39.820748] PM: suspend entry (deep)
11069 13:33:03.754578 <6>[ 39.824636] Filesystems sync: 0.000 seconds
11070 13:33:03.757482 <6>[ 39.829622] Freezing user space processes
11071 13:33:03.768870 <6>[ 39.835583] Freezing user space processes completed (elapsed 0.001 seconds)
11072 13:33:03.772591 <6>[ 39.842836] OOM killer disabled.
11073 13:33:03.775374 <6>[ 39.846316] Freezing remaining freezable tasks
11074 13:33:03.785028 <6>[ 39.852292] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11075 13:33:03.792085 <6>[ 39.859942] printk: Suspending console(s) (use no_console_suspend to debug)
11076 13:33:07.246889 <3>[ 43.088036] mt7921e 0000:01:00.0: Message 00020007 (seq 11) timeout
11077 13:33:07.257099 <3>[ 43.088067] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11078 13:33:07.266781 <3>[ 43.088110] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11079 13:33:07.273258 <3>[ 43.088150] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11080 13:33:07.283660 <3>[ 43.088437] PM: Some devices failed to suspend, or early wake event detected
11081 13:33:07.286537 <6>[ 43.357943] OOM killer enabled.
11082 13:33:07.297624 <6>[ 43.361357] Restarting tasks ... done.
11083 13:33:07.300812 <5>[ 43.372683] random: crng reseeded on system resumption
11084 13:33:07.304457 <6>[ 43.379020] PM: suspend exit
11085 13:33:07.308005 rtcwake: write error
11086 13:33:07.315896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=fail>
11087 13:33:07.316150 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=fail
11089 13:33:07.318803 rtcwake: assuming RTC uses UTC ...
11090 13:33:07.325549 rtcwake: wakeup from "mem" using rtc0 at Fri Sep 8 13:33:12 2023
11091 13:33:07.338422 <6>[ 43.409463] PM: suspend entry (deep)
11092 13:33:07.341494 <6>[ 43.413349] Filesystems sync: 0.000 seconds
11093 13:33:07.345094 <6>[ 43.418319] Freezing user space processes
11094 13:33:07.356095 <6>[ 43.423792] Freezing user space processes completed (elapsed 0.001 seconds)
11095 13:33:07.359356 <6>[ 43.431008] OOM killer disabled.
11096 13:33:07.362482 <6>[ 43.434487] Freezing remaining freezable tasks
11097 13:33:07.372810 <6>[ 43.440348] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11098 13:33:07.379020 <6>[ 43.447998] printk: Suspending console(s) (use no_console_suspend to debug)
11099 13:33:10.831066 <3>[ 46.672042] mt7921e 0000:01:00.0: Message 00020007 (seq 12) timeout
11100 13:33:10.841226 <3>[ 46.672079] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11101 13:33:10.850637 <3>[ 46.672126] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11102 13:33:10.857369 <3>[ 46.672177] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11103 13:33:10.863785 <3>[ 46.672551] PM: Some devices failed to suspend, or early wake event detected
11104 13:33:10.870803 <6>[ 46.941779] OOM killer enabled.
11105 13:33:10.874188 <6>[ 46.945190] Restarting tasks ... done.
11106 13:33:10.880924 <5>[ 46.950968] random: crng reseeded on system resumption
11107 13:33:10.883846 <6>[ 46.957350] PM: suspend exit
11108 13:33:10.887310 rtcwake: write error
11109 13:33:10.894337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=fail>
11110 13:33:10.895123 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=fail
11112 13:33:10.897348 rtcwake: assuming RTC uses UTC ...
11113 13:33:10.904033 rtcwake: wakeup from "mem" using rtc0 at Fri Sep 8 13:33:16 2023
11114 13:33:10.918834 <6>[ 46.989888] PM: suspend entry (deep)
11115 13:33:10.922131 <6>[ 46.993783] Filesystems sync: 0.000 seconds
11116 13:33:10.925292 <6>[ 46.998911] Freezing user space processes
11117 13:33:10.936972 <6>[ 47.004988] Freezing user space processes completed (elapsed 0.001 seconds)
11118 13:33:10.940582 <6>[ 47.012290] OOM killer disabled.
11119 13:33:10.943444 <6>[ 47.015784] Freezing remaining freezable tasks
11120 13:33:10.953362 <6>[ 47.021720] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11121 13:33:10.960047 <6>[ 47.029380] printk: Suspending console(s) (use no_console_suspend to debug)
11122 13:33:14.406507 <6>[ 48.208128] vpu: disabling
11123 13:33:14.410423 <6>[ 48.208261] vproc2: disabling
11124 13:33:14.413262 <6>[ 48.208302] vproc1: disabling
11125 13:33:14.416696 <6>[ 48.208343] vaud18: disabling
11126 13:33:14.419790 <6>[ 48.208535] vsram_others: disabling
11127 13:33:14.423315 <6>[ 48.208690] va09: disabling
11128 13:33:14.426603 <6>[ 48.208749] vsram_md: disabling
11129 13:33:14.429674 <6>[ 48.208852] Vgpu: disabling
11130 13:33:14.436340 <3>[ 50.256007] mt7921e 0000:01:00.0: Message 00020007 (seq 13) timeout
11131 13:33:14.446683 <3>[ 50.256040] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11132 13:33:14.456330 <3>[ 50.256076] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11133 13:33:14.462764 <3>[ 50.256110] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11134 13:33:14.469773 <3>[ 50.256316] PM: Some devices failed to suspend, or early wake event detected
11135 13:33:14.472540 <6>[ 50.547272] OOM killer enabled.
11136 13:33:14.480721 <6>[ 50.550680] Restarting tasks ... done.
11137 13:33:14.487281 <5>[ 50.557372] random: crng reseeded on system resumption
11138 13:33:14.490612 <6>[ 50.564398] PM: suspend exit
11139 13:33:14.494366 rtcwake: write error
11140 13:33:14.500381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=fail>
11141 13:33:14.501026 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=fail
11143 13:33:14.503957 rtcwake: assuming RTC uses UTC ...
11144 13:33:14.510566 rtcwake: wakeup from "mem" using rtc0 at Fri Sep 8 13:33:20 2023
11145 13:33:14.522670 <6>[ 50.594405] PM: suspend entry (deep)
11146 13:33:14.526749 <6>[ 50.598312] Filesystems sync: 0.000 seconds
11147 13:33:14.529379 <6>[ 50.603300] Freezing user space processes
11148 13:33:14.541063 <6>[ 50.609267] Freezing user space processes completed (elapsed 0.001 seconds)
11149 13:33:14.544340 <6>[ 50.616495] OOM killer disabled.
11150 13:33:14.547588 <6>[ 50.619976] Freezing remaining freezable tasks
11151 13:33:14.557971 <6>[ 50.626017] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11152 13:33:14.564315 <6>[ 50.633690] printk: Suspending console(s) (use no_console_suspend to debug)
11153 13:33:17.997680 <3>[ 53.840148] mt7921e 0000:01:00.0: Message 00020007 (seq 14) timeout
11154 13:33:18.008192 <3>[ 53.840245] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11155 13:33:18.018053 <3>[ 53.840314] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11156 13:33:18.024599 <3>[ 53.840355] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11157 13:33:18.031283 <3>[ 53.840555] PM: Some devices failed to suspend, or early wake event detected
11158 13:33:18.038140 <6>[ 54.109935] OOM killer enabled.
11159 13:33:18.041385 <6>[ 54.113345] Restarting tasks ... done.
11160 13:33:18.048814 <5>[ 54.120949] random: crng reseeded on system resumption
11161 13:33:18.053053 <6>[ 54.128570] PM: suspend exit
11162 13:33:18.056451 rtcwake: write error
11163 13:33:18.064131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=fail>
11164 13:33:18.064891 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=fail
11166 13:33:18.067702 rtcwake: assuming RTC uses UTC ...
11167 13:33:18.074434 rtcwake: wakeup from "mem" using rtc0 at Fri Sep 8 13:33:23 2023
11168 13:33:18.087336 <6>[ 54.159041] PM: suspend entry (deep)
11169 13:33:18.090158 <6>[ 54.162924] Filesystems sync: 0.000 seconds
11170 13:33:18.093323 <6>[ 54.167941] Freezing user space processes
11171 13:33:18.105078 <6>[ 54.173820] Freezing user space processes completed (elapsed 0.001 seconds)
11172 13:33:18.108312 <6>[ 54.181054] OOM killer disabled.
11173 13:33:18.111466 <6>[ 54.184535] Freezing remaining freezable tasks
11174 13:33:18.122342 <6>[ 54.190575] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11175 13:33:18.128198 <6>[ 54.198243] printk: Suspending console(s) (use no_console_suspend to debug)
11176 13:33:21.585298 <3>[ 57.423998] mt7921e 0000:01:00.0: Message 00020007 (seq 15) timeout
11177 13:33:21.595833 <3>[ 57.424030] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11178 13:33:21.605149 <3>[ 57.424073] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11179 13:33:21.612183 <3>[ 57.424113] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11180 13:33:21.622188 <3>[ 57.424398] PM: Some devices failed to suspend, or early wake event detected
11181 13:33:21.625249 <6>[ 57.697751] OOM killer enabled.
11182 13:33:21.637395 <6>[ 57.701177] Restarting tasks ... done.
11183 13:33:21.640616 <5>[ 57.713870] random: crng reseeded on system resumption
11184 13:33:21.645231 <6>[ 57.721190] PM: suspend exit
11185 13:33:21.648834 rtcwake: write error
11186 13:33:21.657376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=fail>
11187 13:33:21.658138 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=fail
11189 13:33:21.660422 rtcwake: assuming RTC uses UTC ...
11190 13:33:21.666980 rtcwake: wakeup from "freeze" using rtc0 at Fri Sep 8 13:33:27 2023
11191 13:33:21.682513 <6>[ 57.754459] PM: suspend entry (s2idle)
11192 13:33:21.685454 <6>[ 57.758580] Filesystems sync: 0.000 seconds
11193 13:33:21.688806 <6>[ 57.763543] Freezing user space processes
11194 13:33:21.700105 <6>[ 57.769446] Freezing user space processes completed (elapsed 0.001 seconds)
11195 13:33:21.703693 <6>[ 57.776675] OOM killer disabled.
11196 13:33:21.707135 <6>[ 57.780158] Freezing remaining freezable tasks
11197 13:33:21.717188 <6>[ 57.786184] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11198 13:33:21.724145 <6>[ 57.793857] printk: Suspending console(s) (use no_console_suspend to debug)
11199 13:33:25.165014 <3>[ 61.008127] mt7921e 0000:01:00.0: Message 00020007 (seq 1) timeout
11200 13:33:25.178150 <3>[ 61.008201] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11201 13:33:25.184671 <3>[ 61.008261] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11202 13:33:25.191802 <3>[ 61.008299] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11203 13:33:25.201577 <3>[ 61.008581] PM: Some devices failed to suspend, or early wake event detected
11204 13:33:25.205124 <6>[ 61.277890] OOM killer enabled.
11205 13:33:25.207986 <6>[ 61.281308] Restarting tasks ... done.
11206 13:33:25.215236 <5>[ 61.287216] random: crng reseeded on system resumption
11207 13:33:25.218498 <6>[ 61.293497] PM: suspend exit
11208 13:33:25.221558 rtcwake: write error
11209 13:33:25.227873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail>
11210 13:33:25.228518 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail
11212 13:33:25.231141 rtcwake: assuming RTC uses UTC ...
11213 13:33:25.237958 rtcwake: wakeup from "freeze" using rtc0 at Fri Sep 8 13:33:30 2023
11214 13:33:25.251074 <6>[ 61.323531] PM: suspend entry (s2idle)
11215 13:33:25.254504 <6>[ 61.327593] Filesystems sync: 0.000 seconds
11216 13:33:25.260495 <6>[ 61.332600] Freezing user space processes
11217 13:33:25.266922 <6>[ 61.338559] Freezing user space processes completed (elapsed 0.001 seconds)
11218 13:33:25.270459 <6>[ 61.345790] OOM killer disabled.
11219 13:33:25.277076 <6>[ 61.349270] Freezing remaining freezable tasks
11220 13:33:25.283831 <6>[ 61.355362] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11221 13:33:25.293684 <6>[ 61.363035] printk: Suspending console(s) (use no_console_suspend to debug)
11222 13:33:28.752844 <3>[ 64.592026] mt7921e 0000:01:00.0: Message 00020007 (seq 2) timeout
11223 13:33:28.762484 <3>[ 64.592060] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11224 13:33:28.772627 <3>[ 64.592107] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11225 13:33:28.779334 <3>[ 64.592146] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11226 13:33:28.788774 <3>[ 64.592402] PM: Some devices failed to suspend, or early wake event detected
11227 13:33:28.791925 <6>[ 64.865765] OOM killer enabled.
11228 13:33:28.798962 <6>[ 64.869182] Restarting tasks ... done.
11229 13:33:28.802019 <5>[ 64.876414] random: crng reseeded on system resumption
11230 13:33:28.807447 <6>[ 64.884050] PM: suspend exit
11231 13:33:28.811418 rtcwake: write error
11232 13:33:28.818514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail>
11233 13:33:28.819214 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail
11235 13:33:28.821606 rtcwake: assuming RTC uses UTC ...
11236 13:33:28.828404 rtcwake: wakeup from "freeze" using rtc0 at Fri Sep 8 13:33:34 2023
11237 13:33:28.840848 <6>[ 64.913981] PM: suspend entry (s2idle)
11238 13:33:28.844127 <6>[ 64.918072] Filesystems sync: 0.000 seconds
11239 13:33:28.850632 <6>[ 64.923015] Freezing user space processes
11240 13:33:28.856726 <6>[ 64.928851] Freezing user space processes completed (elapsed 0.001 seconds)
11241 13:33:28.860190 <6>[ 64.936079] OOM killer disabled.
11242 13:33:28.867060 <6>[ 64.939555] Freezing remaining freezable tasks
11243 13:33:28.874020 <6>[ 64.945600] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11244 13:33:28.883569 <6>[ 64.953287] printk: Suspending console(s) (use no_console_suspend to debug)
11245 13:33:32.331983 <3>[ 68.176004] mt7921e 0000:01:00.0: Message 00020007 (seq 3) timeout
11246 13:33:32.342466 <3>[ 68.176035] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11247 13:33:32.352814 <3>[ 68.176078] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11248 13:33:32.358836 <3>[ 68.176118] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11249 13:33:32.368585 <3>[ 68.176412] PM: Some devices failed to suspend, or early wake event detected
11250 13:33:32.371863 <6>[ 68.445906] OOM killer enabled.
11251 13:33:32.381648 <6>[ 68.449316] Restarting tasks ... done.
11252 13:33:32.384552 <5>[ 68.459295] random: crng reseeded on system resumption
11253 13:33:32.389089 <6>[ 68.466054] PM: suspend exit
11254 13:33:32.392270 rtcwake: write error
11255 13:33:32.400390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail>
11256 13:33:32.401090 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail
11258 13:33:32.404153 rtcwake: assuming RTC uses UTC ...
11259 13:33:32.410524 rtcwake: wakeup from "freeze" using rtc0 at Fri Sep 8 13:33:37 2023
11260 13:33:32.423983 <6>[ 68.497467] PM: suspend entry (s2idle)
11261 13:33:32.426950 <6>[ 68.501524] Filesystems sync: 0.000 seconds
11262 13:33:32.430062 <6>[ 68.506498] Freezing user space processes
11263 13:33:32.441570 <6>[ 68.512296] Freezing user space processes completed (elapsed 0.001 seconds)
11264 13:33:32.445450 <6>[ 68.519517] OOM killer disabled.
11265 13:33:32.448438 <6>[ 68.522995] Freezing remaining freezable tasks
11266 13:33:32.458754 <6>[ 68.529043] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11267 13:33:32.464903 <6>[ 68.536708] printk: Suspending console(s) (use no_console_suspend to debug)
11268 13:33:35.916188 <3>[ 71.760033] mt7921e 0000:01:00.0: Message 00020007 (seq 4) timeout
11269 13:33:35.926020 <3>[ 71.760067] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11270 13:33:35.935786 <3>[ 71.760117] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11271 13:33:35.942849 <3>[ 71.760160] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11272 13:33:35.949297 <3>[ 71.760374] PM: Some devices failed to suspend, or early wake event detected
11273 13:33:35.956012 <6>[ 72.029877] OOM killer enabled.
11274 13:33:35.959157 <6>[ 72.033289] Restarting tasks ... done.
11275 13:33:35.965881 <5>[ 72.039097] random: crng reseeded on system resumption
11276 13:33:35.968774 <6>[ 72.045443] PM: suspend exit
11277 13:33:35.971886 rtcwake: write error
11278 13:33:35.978830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail>
11279 13:33:35.979600 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail
11281 13:33:35.982045 rtcwake: assuming RTC uses UTC ...
11282 13:33:35.988767 rtcwake: wakeup from "freeze" using rtc0 at Fri Sep 8 13:33:41 2023
11283 13:33:36.001689 <6>[ 72.076026] PM: suspend entry (s2idle)
11284 13:33:36.005208 <6>[ 72.080070] Filesystems sync: 0.000 seconds
11285 13:33:36.008626 <6>[ 72.085032] Freezing user space processes
11286 13:33:36.020572 <6>[ 72.090867] Freezing user space processes completed (elapsed 0.001 seconds)
11287 13:33:36.023236 <6>[ 72.098098] OOM killer disabled.
11288 13:33:36.026531 <6>[ 72.101579] Freezing remaining freezable tasks
11289 13:33:36.036749 <6>[ 72.107604] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11290 13:33:36.043560 <6>[ 72.115271] printk: Suspending console(s) (use no_console_suspend to debug)
11291 13:33:39.503489 <3>[ 75.344035] mt7921e 0000:01:00.0: Message 00020007 (seq 5) timeout
11292 13:33:39.513511 <3>[ 75.344077] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11293 13:33:39.523397 <3>[ 75.344127] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11294 13:33:39.529874 <3>[ 75.344171] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11295 13:33:39.539796 <3>[ 75.344457] PM: Some devices failed to suspend, or early wake event detected
11296 13:33:39.543089 <6>[ 75.617894] OOM killer enabled.
11297 13:33:39.546746 <6>[ 75.621306] Restarting tasks ... done.
11298 13:33:39.553338 <5>[ 75.627191] random: crng reseeded on system resumption
11299 13:33:39.557431 <6>[ 75.635252] PM: suspend exit
11300 13:33:39.560989 rtcwake: write error
11301 13:33:39.568695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail>
11302 13:33:39.569414 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail
11304 13:33:39.572062 rtcwake: assuming RTC uses UTC ...
11305 13:33:39.578297 rtcwake: wakeup from "freeze" using rtc0 at Fri Sep 8 13:33:45 2023
11306 13:33:39.591331 <6>[ 75.665301] PM: suspend entry (s2idle)
11307 13:33:39.594023 <6>[ 75.669364] Filesystems sync: 0.000 seconds
11308 13:33:39.597733 <6>[ 75.674340] Freezing user space processes
11309 13:33:39.608847 <6>[ 75.679795] Freezing user space processes completed (elapsed 0.001 seconds)
11310 13:33:39.611661 <6>[ 75.687010] OOM killer disabled.
11311 13:33:39.614978 <6>[ 75.690489] Freezing remaining freezable tasks
11312 13:33:39.625190 <6>[ 75.696345] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11313 13:33:39.632126 <6>[ 75.703992] printk: Suspending console(s) (use no_console_suspend to debug)
11314 13:33:43.078513 <3>[ 78.928038] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11315 13:33:43.088461 <3>[ 78.928068] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11316 13:33:43.098246 <3>[ 78.928113] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11317 13:33:43.105441 <3>[ 78.928153] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11318 13:33:43.114832 <3>[ 78.928383] PM: Some devices failed to suspend, or early wake event detected
11319 13:33:43.118198 <6>[ 79.193903] OOM killer enabled.
11320 13:33:43.121486 <6>[ 79.197312] Restarting tasks ... done.
11321 13:33:43.128120 <5>[ 79.203020] random: crng reseeded on system resumption
11322 13:33:43.131264 <6>[ 79.209417] PM: suspend exit
11323 13:33:43.134555 rtcwake: write error
11324 13:33:43.142016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail>
11325 13:33:43.142270 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail
11327 13:33:43.144738 rtcwake: assuming RTC uses UTC ...
11328 13:33:43.151681 rtcwake: wakeup from "freeze" using rtc0 at Fri Sep 8 13:33:48 2023
11329 13:33:43.165684 <6>[ 79.240734] PM: suspend entry (s2idle)
11330 13:33:43.168735 <6>[ 79.244846] Filesystems sync: 0.000 seconds
11331 13:33:43.175432 <6>[ 79.250040] Freezing user space processes
11332 13:33:43.182438 <6>[ 79.255848] Freezing user space processes completed (elapsed 0.001 seconds)
11333 13:33:43.185424 <6>[ 79.263146] OOM killer disabled.
11334 13:33:43.192226 <6>[ 79.266642] Freezing remaining freezable tasks
11335 13:33:43.198551 <6>[ 79.272576] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11336 13:33:43.205241 <6>[ 79.280245] printk: Suspending console(s) (use no_console_suspend to debug)
11337 13:33:46.661945 <3>[ 82.511989] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11338 13:33:46.671648 <3>[ 82.512015] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11339 13:33:46.681647 <3>[ 82.512045] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11340 13:33:46.688190 <3>[ 82.512072] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11341 13:33:46.694730 <3>[ 82.512457] PM: Some devices failed to suspend, or early wake event detected
11342 13:33:46.701209 <6>[ 82.777419] OOM killer enabled.
11343 13:33:46.717563 <6>[ 82.780831] Restarting tasks ... done.
11344 13:33:46.720588 <5>[ 82.797375] random: crng reseeded on system resumption
11345 13:33:46.724524 <6>[ 82.803665] PM: suspend exit
11346 13:33:46.727662 rtcwake: write error
11347 13:33:46.736021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail>
11348 13:33:46.736283 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail
11350 13:33:46.739120 rtcwake: assuming RTC uses UTC ...
11351 13:33:46.745751 rtcwake: wakeup from "freeze" using rtc0 at Fri Sep 8 13:33:52 2023
11352 13:33:46.758686 <6>[ 82.834650] PM: suspend entry (s2idle)
11353 13:33:46.761982 <6>[ 82.838720] Filesystems sync: 0.000 seconds
11354 13:33:46.768752 <6>[ 82.843819] Freezing user space processes
11355 13:33:46.775266 <6>[ 82.849680] Freezing user space processes completed (elapsed 0.001 seconds)
11356 13:33:46.779034 <6>[ 82.856921] OOM killer disabled.
11357 13:33:46.785692 <6>[ 82.860401] Freezing remaining freezable tasks
11358 13:33:46.792178 <6>[ 82.866412] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11359 13:33:46.798748 <6>[ 82.874089] printk: Suspending console(s) (use no_console_suspend to debug)
11360 13:33:50.253556 <3>[ 86.096072] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11361 13:33:50.263598 <3>[ 86.096112] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11362 13:33:50.273553 <3>[ 86.096163] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11363 13:33:50.280544 <3>[ 86.096218] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11364 13:33:50.286955 <3>[ 86.096578] PM: Some devices failed to suspend, or early wake event detected
11365 13:33:50.293457 <6>[ 86.369759] OOM killer enabled.
11366 13:33:50.296793 <6>[ 86.373169] Restarting tasks ... done.
11367 13:33:50.303322 <5>[ 86.378983] random: crng reseeded on system resumption
11368 13:33:50.307174 <6>[ 86.386433] PM: suspend exit
11369 13:33:50.310413 rtcwake: write error
11370 13:33:50.318032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail>
11371 13:33:50.318279 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail
11373 13:33:50.321092 rtcwake: assuming RTC uses UTC ...
11374 13:33:50.327698 rtcwake: wakeup from "freeze" using rtc0 at Fri Sep 8 13:33:55 2023
11375 13:33:50.340164 <6>[ 86.416576] PM: suspend entry (s2idle)
11376 13:33:50.343564 <6>[ 86.420635] Filesystems sync: 0.000 seconds
11377 13:33:50.347129 <6>[ 86.425607] Freezing user space processes
11378 13:33:50.358775 <6>[ 86.431515] Freezing user space processes completed (elapsed 0.001 seconds)
11379 13:33:50.361908 <6>[ 86.438746] OOM killer disabled.
11380 13:33:50.365211 <6>[ 86.442228] Freezing remaining freezable tasks
11381 13:33:50.375299 <6>[ 86.447784] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11382 13:33:50.381768 <6>[ 86.455434] printk: Suspending console(s) (use no_console_suspend to debug)
11383 13:33:53.829595 <3>[ 89.679998] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11384 13:33:53.839110 <3>[ 89.680029] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11385 13:33:53.849291 <3>[ 89.680072] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11386 13:33:53.855849 <3>[ 89.680113] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11387 13:33:53.865840 <3>[ 89.680388] PM: Some devices failed to suspend, or early wake event detected
11388 13:33:53.869276 <6>[ 89.945915] OOM killer enabled.
11389 13:33:53.872319 <6>[ 89.949325] Restarting tasks ... done.
11390 13:33:53.878896 <5>[ 89.955112] random: crng reseeded on system resumption
11391 13:33:53.882146 <6>[ 89.962328] PM: suspend exit
11392 13:33:53.885720 rtcwake: write error
11393 13:33:53.893624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail>
11394 13:33:53.893872 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail
11396 13:33:53.897085 rtcwake: assuming RTC uses UTC ...
11397 13:33:53.903506 rtcwake: wakeup from "freeze" using rtc0 at Fri Sep 8 13:33:59 2023
11398 13:33:53.916121 <6>[ 89.992502] PM: suspend entry (s2idle)
11399 13:33:53.919111 <6>[ 89.996577] Filesystems sync: 0.000 seconds
11400 13:33:53.925769 <6>[ 90.001528] Freezing user space processes
11401 13:33:53.932530 <6>[ 90.007386] Freezing user space processes completed (elapsed 0.001 seconds)
11402 13:33:53.935948 <6>[ 90.014617] OOM killer disabled.
11403 13:33:53.942098 <6>[ 90.018099] Freezing remaining freezable tasks
11404 13:33:53.949129 <6>[ 90.023756] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11405 13:33:53.955466 <6>[ 90.031406] printk: Suspending console(s) (use no_console_suspend to debug)
11406 13:33:57.412722 <3>[ 93.264040] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11407 13:33:57.425892 <3>[ 93.264071] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11408 13:33:57.432342 <3>[ 93.264115] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11409 13:33:57.439034 <3>[ 93.264155] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11410 13:33:57.448689 <3>[ 93.264388] PM: Some devices failed to suspend, or early wake event detected
11411 13:33:57.452181 <6>[ 93.529801] OOM killer enabled.
11412 13:33:57.455707 <6>[ 93.533212] Restarting tasks ... done.
11413 13:33:57.463329 <5>[ 93.540239] random: crng reseeded on system resumption
11414 13:33:57.466339 <6>[ 93.546623] PM: suspend exit
11415 13:33:57.469987 rtcwake: write error
11416 13:33:57.477614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail>
11417 13:33:57.477855 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail
11419 13:33:57.480846 + set +x
11420 13:33:57.484293 <LAVA_SIGNAL_ENDRUN 0_sleep 11471181_1.5.2.3.1>
11421 13:33:57.484382 <LAVA_TEST_RUNNER EXIT>
11422 13:33:57.484617 Received signal: <ENDRUN> 0_sleep 11471181_1.5.2.3.1
11423 13:33:57.484693 Ending use of test pattern.
11424 13:33:57.484742 Ending test lava.0_sleep (11471181_1.5.2.3.1), duration 71.59
11426 13:33:57.484971 ok: lava_test_shell seems to have completed
11427 13:33:57.485124 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-freeze-1: fail
rtcwake-freeze-10: fail
rtcwake-freeze-2: fail
rtcwake-freeze-3: fail
rtcwake-freeze-4: fail
rtcwake-freeze-5: fail
rtcwake-freeze-6: fail
rtcwake-freeze-7: fail
rtcwake-freeze-8: fail
rtcwake-freeze-9: fail
rtcwake-mem-1: fail
rtcwake-mem-10: fail
rtcwake-mem-2: fail
rtcwake-mem-3: fail
rtcwake-mem-4: fail
rtcwake-mem-5: fail
rtcwake-mem-6: fail
rtcwake-mem-7: fail
rtcwake-mem-8: fail
rtcwake-mem-9: fail
11428 13:33:57.485202 end: 3.1 lava-test-shell (duration 00:01:12) [common]
11429 13:33:57.485270 end: 3 lava-test-retry (duration 00:01:12) [common]
11430 13:33:57.485338 start: 4 finalize (timeout 00:06:28) [common]
11431 13:33:57.485406 start: 4.1 power-off (timeout 00:00:30) [common]
11432 13:33:57.485539 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
11433 13:33:57.558075 >> Command sent successfully.
11434 13:33:57.560324 Returned 0 in 0 seconds
11435 13:33:57.660707 end: 4.1 power-off (duration 00:00:00) [common]
11437 13:33:57.660983 start: 4.2 read-feedback (timeout 00:06:28) [common]
11438 13:33:57.661182 Listened to connection for namespace 'common' for up to 1s
11439 13:33:57.661457 Listened to connection for namespace 'common' for up to 1s
11440 13:33:58.662277 Finalising connection for namespace 'common'
11441 13:33:58.662455 Disconnecting from shell: Finalise
11442 13:33:58.662537 / #
11443 13:33:58.762871 end: 4.2 read-feedback (duration 00:00:01) [common]
11444 13:33:58.763032 end: 4 finalize (duration 00:00:01) [common]
11445 13:33:58.763128 Cleaning after the job
11446 13:33:58.763211 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11471181/tftp-deploy-gextz524/ramdisk
11447 13:33:58.771596 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11471181/tftp-deploy-gextz524/kernel
11448 13:33:58.785988 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11471181/tftp-deploy-gextz524/dtb
11449 13:33:58.786174 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11471181/tftp-deploy-gextz524/modules
11450 13:33:58.791435 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11471181
11451 13:33:58.890703 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11471181
11452 13:33:58.890902 Job finished correctly