Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 27
- Boot result: PASS
- Warnings: 1
- Errors: 1
- Kernel Warnings: 19
1 13:28:04.387582 lava-dispatcher, installed at version: 2023.06
2 13:28:04.387763 start: 0 validate
3 13:28:04.387901 Start time: 2023-09-08 13:28:04.387894+00:00 (UTC)
4 13:28:04.388027 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:28:04.388156 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 13:28:04.669412 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:28:04.669609 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.52-cip5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:28:04.934934 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:28:04.935129 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.52-cip5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:28:05.200906 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:28:05.201091 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.52-cip5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 13:28:05.731212 validate duration: 1.34
14 13:28:05.731489 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:28:05.731577 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:28:05.731654 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:28:05.731769 Not decompressing ramdisk as can be used compressed.
18 13:28:05.731849 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/arm64/rootfs.cpio.gz
19 13:28:05.731909 saving as /var/lib/lava/dispatcher/tmp/11471184/tftp-deploy-xgwar0g1/ramdisk/rootfs.cpio.gz
20 13:28:05.731964 total size: 8181372 (7 MB)
21 13:28:05.733149 progress 0 % (0 MB)
22 13:28:05.734804 progress 5 % (0 MB)
23 13:28:05.736247 progress 10 % (0 MB)
24 13:28:05.737839 progress 15 % (1 MB)
25 13:28:05.739276 progress 20 % (1 MB)
26 13:28:05.740853 progress 25 % (1 MB)
27 13:28:05.742370 progress 30 % (2 MB)
28 13:28:05.743936 progress 35 % (2 MB)
29 13:28:05.745496 progress 40 % (3 MB)
30 13:28:05.747058 progress 45 % (3 MB)
31 13:28:05.748549 progress 50 % (3 MB)
32 13:28:05.750145 progress 55 % (4 MB)
33 13:28:05.751569 progress 60 % (4 MB)
34 13:28:05.753139 progress 65 % (5 MB)
35 13:28:05.754531 progress 70 % (5 MB)
36 13:28:05.756028 progress 75 % (5 MB)
37 13:28:05.757430 progress 80 % (6 MB)
38 13:28:05.758967 progress 85 % (6 MB)
39 13:28:05.760391 progress 90 % (7 MB)
40 13:28:05.761889 progress 95 % (7 MB)
41 13:28:05.763329 progress 100 % (7 MB)
42 13:28:05.763507 7 MB downloaded in 0.03 s (247.37 MB/s)
43 13:28:05.763664 end: 1.1.1 http-download (duration 00:00:00) [common]
45 13:28:05.763867 end: 1.1 download-retry (duration 00:00:00) [common]
46 13:28:05.763935 start: 1.2 download-retry (timeout 00:10:00) [common]
47 13:28:05.764000 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 13:28:05.764125 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.52-cip5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 13:28:05.764183 saving as /var/lib/lava/dispatcher/tmp/11471184/tftp-deploy-xgwar0g1/kernel/Image
50 13:28:05.764232 total size: 49220096 (46 MB)
51 13:28:05.764288 No compression specified
52 13:28:05.765448 progress 0 % (0 MB)
53 13:28:05.774272 progress 5 % (2 MB)
54 13:28:05.783186 progress 10 % (4 MB)
55 13:28:05.791872 progress 15 % (7 MB)
56 13:28:05.800642 progress 20 % (9 MB)
57 13:28:05.809408 progress 25 % (11 MB)
58 13:28:05.818156 progress 30 % (14 MB)
59 13:28:05.826875 progress 35 % (16 MB)
60 13:28:05.835446 progress 40 % (18 MB)
61 13:28:05.844139 progress 45 % (21 MB)
62 13:28:05.853017 progress 50 % (23 MB)
63 13:28:05.861618 progress 55 % (25 MB)
64 13:28:05.870297 progress 60 % (28 MB)
65 13:28:05.879160 progress 65 % (30 MB)
66 13:28:05.887956 progress 70 % (32 MB)
67 13:28:05.896633 progress 75 % (35 MB)
68 13:28:05.905475 progress 80 % (37 MB)
69 13:28:05.914382 progress 85 % (39 MB)
70 13:28:05.923189 progress 90 % (42 MB)
71 13:28:05.932006 progress 95 % (44 MB)
72 13:28:05.940632 progress 100 % (46 MB)
73 13:28:05.940769 46 MB downloaded in 0.18 s (265.90 MB/s)
74 13:28:05.940906 end: 1.2.1 http-download (duration 00:00:00) [common]
76 13:28:05.941110 end: 1.2 download-retry (duration 00:00:00) [common]
77 13:28:05.941182 start: 1.3 download-retry (timeout 00:10:00) [common]
78 13:28:05.941249 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 13:28:05.941378 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.52-cip5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 13:28:05.941437 saving as /var/lib/lava/dispatcher/tmp/11471184/tftp-deploy-xgwar0g1/dtb/mt8192-asurada-spherion-r0.dtb
81 13:28:05.941486 total size: 47278 (0 MB)
82 13:28:05.941543 No compression specified
83 13:28:05.942746 progress 69 % (0 MB)
84 13:28:05.942978 progress 100 % (0 MB)
85 13:28:05.943108 0 MB downloaded in 0.00 s (27.86 MB/s)
86 13:28:05.943218 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:28:05.943407 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:28:05.943474 start: 1.4 download-retry (timeout 00:10:00) [common]
90 13:28:05.943538 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 13:28:05.943640 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.52-cip5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 13:28:05.943698 saving as /var/lib/lava/dispatcher/tmp/11471184/tftp-deploy-xgwar0g1/modules/modules.tar
93 13:28:05.943746 total size: 8615576 (8 MB)
94 13:28:05.943808 Using unxz to decompress xz
95 13:28:05.947323 progress 0 % (0 MB)
96 13:28:05.966366 progress 5 % (0 MB)
97 13:28:05.985696 progress 10 % (0 MB)
98 13:28:06.008363 progress 15 % (1 MB)
99 13:28:06.030471 progress 20 % (1 MB)
100 13:28:06.052948 progress 25 % (2 MB)
101 13:28:06.075708 progress 30 % (2 MB)
102 13:28:06.099088 progress 35 % (2 MB)
103 13:28:06.120562 progress 40 % (3 MB)
104 13:28:06.141479 progress 45 % (3 MB)
105 13:28:06.164089 progress 50 % (4 MB)
106 13:28:06.186093 progress 55 % (4 MB)
107 13:28:06.207326 progress 60 % (4 MB)
108 13:28:06.226874 progress 65 % (5 MB)
109 13:28:06.250793 progress 70 % (5 MB)
110 13:28:06.271499 progress 75 % (6 MB)
111 13:28:06.294422 progress 80 % (6 MB)
112 13:28:06.320367 progress 85 % (7 MB)
113 13:28:06.343129 progress 90 % (7 MB)
114 13:28:06.363984 progress 95 % (7 MB)
115 13:28:06.384007 progress 100 % (8 MB)
116 13:28:06.389482 8 MB downloaded in 0.45 s (18.43 MB/s)
117 13:28:06.389747 end: 1.4.1 http-download (duration 00:00:00) [common]
119 13:28:06.390002 end: 1.4 download-retry (duration 00:00:00) [common]
120 13:28:06.390091 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 13:28:06.390181 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 13:28:06.390257 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:28:06.390344 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 13:28:06.390550 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11471184/lava-overlay-9uis2fmb
125 13:28:06.390683 makedir: /var/lib/lava/dispatcher/tmp/11471184/lava-overlay-9uis2fmb/lava-11471184/bin
126 13:28:06.390778 makedir: /var/lib/lava/dispatcher/tmp/11471184/lava-overlay-9uis2fmb/lava-11471184/tests
127 13:28:06.390868 makedir: /var/lib/lava/dispatcher/tmp/11471184/lava-overlay-9uis2fmb/lava-11471184/results
128 13:28:06.390970 Creating /var/lib/lava/dispatcher/tmp/11471184/lava-overlay-9uis2fmb/lava-11471184/bin/lava-add-keys
129 13:28:06.391104 Creating /var/lib/lava/dispatcher/tmp/11471184/lava-overlay-9uis2fmb/lava-11471184/bin/lava-add-sources
130 13:28:06.391221 Creating /var/lib/lava/dispatcher/tmp/11471184/lava-overlay-9uis2fmb/lava-11471184/bin/lava-background-process-start
131 13:28:06.391334 Creating /var/lib/lava/dispatcher/tmp/11471184/lava-overlay-9uis2fmb/lava-11471184/bin/lava-background-process-stop
132 13:28:06.391457 Creating /var/lib/lava/dispatcher/tmp/11471184/lava-overlay-9uis2fmb/lava-11471184/bin/lava-common-functions
133 13:28:06.391572 Creating /var/lib/lava/dispatcher/tmp/11471184/lava-overlay-9uis2fmb/lava-11471184/bin/lava-echo-ipv4
134 13:28:06.391677 Creating /var/lib/lava/dispatcher/tmp/11471184/lava-overlay-9uis2fmb/lava-11471184/bin/lava-install-packages
135 13:28:06.391781 Creating /var/lib/lava/dispatcher/tmp/11471184/lava-overlay-9uis2fmb/lava-11471184/bin/lava-installed-packages
136 13:28:06.391883 Creating /var/lib/lava/dispatcher/tmp/11471184/lava-overlay-9uis2fmb/lava-11471184/bin/lava-os-build
137 13:28:06.391988 Creating /var/lib/lava/dispatcher/tmp/11471184/lava-overlay-9uis2fmb/lava-11471184/bin/lava-probe-channel
138 13:28:06.392092 Creating /var/lib/lava/dispatcher/tmp/11471184/lava-overlay-9uis2fmb/lava-11471184/bin/lava-probe-ip
139 13:28:06.392196 Creating /var/lib/lava/dispatcher/tmp/11471184/lava-overlay-9uis2fmb/lava-11471184/bin/lava-target-ip
140 13:28:06.392313 Creating /var/lib/lava/dispatcher/tmp/11471184/lava-overlay-9uis2fmb/lava-11471184/bin/lava-target-mac
141 13:28:06.392431 Creating /var/lib/lava/dispatcher/tmp/11471184/lava-overlay-9uis2fmb/lava-11471184/bin/lava-target-storage
142 13:28:06.392538 Creating /var/lib/lava/dispatcher/tmp/11471184/lava-overlay-9uis2fmb/lava-11471184/bin/lava-test-case
143 13:28:06.392655 Creating /var/lib/lava/dispatcher/tmp/11471184/lava-overlay-9uis2fmb/lava-11471184/bin/lava-test-event
144 13:28:06.392756 Creating /var/lib/lava/dispatcher/tmp/11471184/lava-overlay-9uis2fmb/lava-11471184/bin/lava-test-feedback
145 13:28:06.392857 Creating /var/lib/lava/dispatcher/tmp/11471184/lava-overlay-9uis2fmb/lava-11471184/bin/lava-test-raise
146 13:28:06.392959 Creating /var/lib/lava/dispatcher/tmp/11471184/lava-overlay-9uis2fmb/lava-11471184/bin/lava-test-reference
147 13:28:06.393062 Creating /var/lib/lava/dispatcher/tmp/11471184/lava-overlay-9uis2fmb/lava-11471184/bin/lava-test-runner
148 13:28:06.393163 Creating /var/lib/lava/dispatcher/tmp/11471184/lava-overlay-9uis2fmb/lava-11471184/bin/lava-test-set
149 13:28:06.393265 Creating /var/lib/lava/dispatcher/tmp/11471184/lava-overlay-9uis2fmb/lava-11471184/bin/lava-test-shell
150 13:28:06.393369 Updating /var/lib/lava/dispatcher/tmp/11471184/lava-overlay-9uis2fmb/lava-11471184/bin/lava-install-packages (oe)
151 13:28:06.393532 Updating /var/lib/lava/dispatcher/tmp/11471184/lava-overlay-9uis2fmb/lava-11471184/bin/lava-installed-packages (oe)
152 13:28:06.393632 Creating /var/lib/lava/dispatcher/tmp/11471184/lava-overlay-9uis2fmb/lava-11471184/environment
153 13:28:06.393718 LAVA metadata
154 13:28:06.393784 - LAVA_JOB_ID=11471184
155 13:28:06.393842 - LAVA_DISPATCHER_IP=192.168.201.1
156 13:28:06.393938 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 13:28:06.393994 skipped lava-vland-overlay
158 13:28:06.394065 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 13:28:06.394137 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 13:28:06.394195 skipped lava-multinode-overlay
161 13:28:06.394266 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 13:28:06.394340 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 13:28:06.394404 Loading test definitions
164 13:28:06.394489 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 13:28:06.394554 Using /lava-11471184 at stage 0
166 13:28:06.394820 uuid=11471184_1.5.2.3.1 testdef=None
167 13:28:06.394894 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 13:28:06.394967 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 13:28:06.395395 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 13:28:06.395591 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 13:28:06.396131 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 13:28:06.396338 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 13:28:06.396870 runner path: /var/lib/lava/dispatcher/tmp/11471184/lava-overlay-9uis2fmb/lava-11471184/0/tests/0_dmesg test_uuid 11471184_1.5.2.3.1
176 13:28:06.396995 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 13:28:06.397188 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:59) [common]
179 13:28:06.397249 Using /lava-11471184 at stage 1
180 13:28:06.397495 uuid=11471184_1.5.2.3.5 testdef=None
181 13:28:06.397584 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 13:28:06.397682 start: 1.5.2.3.6 test-overlay (timeout 00:09:59) [common]
183 13:28:06.398105 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 13:28:06.398272 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:59) [common]
186 13:28:06.399203 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 13:28:06.399403 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
189 13:28:06.399900 runner path: /var/lib/lava/dispatcher/tmp/11471184/lava-overlay-9uis2fmb/lava-11471184/1/tests/1_bootrr test_uuid 11471184_1.5.2.3.5
190 13:28:06.400026 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 13:28:06.400204 Creating lava-test-runner.conf files
193 13:28:06.400254 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11471184/lava-overlay-9uis2fmb/lava-11471184/0 for stage 0
194 13:28:06.400332 - 0_dmesg
195 13:28:06.400409 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11471184/lava-overlay-9uis2fmb/lava-11471184/1 for stage 1
196 13:28:06.400479 - 1_bootrr
197 13:28:06.400552 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 13:28:06.400618 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
199 13:28:06.406796 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 13:28:06.406905 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
201 13:28:06.406979 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 13:28:06.407048 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 13:28:06.407116 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
204 13:28:06.569919 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 13:28:06.570196 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
206 13:28:06.570295 extracting modules file /var/lib/lava/dispatcher/tmp/11471184/tftp-deploy-xgwar0g1/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11471184/extract-overlay-ramdisk-yuoy_ci9/ramdisk
207 13:28:06.707528 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 13:28:06.707693 start: 1.5.5 apply-overlay-tftp (timeout 00:09:59) [common]
209 13:28:06.707783 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11471184/compress-overlay-tt9x79dm/overlay-1.5.2.4.tar.gz to ramdisk
210 13:28:06.707841 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11471184/compress-overlay-tt9x79dm/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11471184/extract-overlay-ramdisk-yuoy_ci9/ramdisk
211 13:28:06.713865 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 13:28:06.713983 start: 1.5.6 configure-preseed-file (timeout 00:09:59) [common]
213 13:28:06.714091 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 13:28:06.714195 start: 1.5.7 compress-ramdisk (timeout 00:09:59) [common]
215 13:28:06.714259 Building ramdisk /var/lib/lava/dispatcher/tmp/11471184/extract-overlay-ramdisk-yuoy_ci9/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11471184/extract-overlay-ramdisk-yuoy_ci9/ramdisk
216 13:28:06.885966 >> 145172 blocks
217 13:28:08.908178 rename /var/lib/lava/dispatcher/tmp/11471184/extract-overlay-ramdisk-yuoy_ci9/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11471184/tftp-deploy-xgwar0g1/ramdisk/ramdisk.cpio.gz
218 13:28:08.908530 end: 1.5.7 compress-ramdisk (duration 00:00:02) [common]
219 13:28:08.908673 start: 1.5.8 prepare-kernel (timeout 00:09:57) [common]
220 13:28:08.908789 start: 1.5.8.1 prepare-fit (timeout 00:09:57) [common]
221 13:28:08.908899 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11471184/tftp-deploy-xgwar0g1/kernel/Image'
222 13:28:21.542172 Returned 0 in 12 seconds
223 13:28:21.642684 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11471184/tftp-deploy-xgwar0g1/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11471184/tftp-deploy-xgwar0g1/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11471184/tftp-deploy-xgwar0g1/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11471184/tftp-deploy-xgwar0g1/kernel/image.itb
224 13:28:21.852278 output: FIT description: Kernel Image image with one or more FDT blobs
225 13:28:21.852562 output: Created: Fri Sep 8 14:28:21 2023
226 13:28:21.852625 output: Image 0 (kernel-1)
227 13:28:21.852693 output: Description:
228 13:28:21.852774 output: Created: Fri Sep 8 14:28:21 2023
229 13:28:21.852857 output: Type: Kernel Image
230 13:28:21.852905 output: Compression: lzma compressed
231 13:28:21.852956 output: Data Size: 11040095 Bytes = 10781.34 KiB = 10.53 MiB
232 13:28:21.853005 output: Architecture: AArch64
233 13:28:21.853051 output: OS: Linux
234 13:28:21.853100 output: Load Address: 0x00000000
235 13:28:21.853152 output: Entry Point: 0x00000000
236 13:28:21.853196 output: Hash algo: crc32
237 13:28:21.853240 output: Hash value: 41c180c9
238 13:28:21.853285 output: Image 1 (fdt-1)
239 13:28:21.853330 output: Description: mt8192-asurada-spherion-r0
240 13:28:21.853375 output: Created: Fri Sep 8 14:28:21 2023
241 13:28:21.853420 output: Type: Flat Device Tree
242 13:28:21.853464 output: Compression: uncompressed
243 13:28:21.853509 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
244 13:28:21.853553 output: Architecture: AArch64
245 13:28:21.853598 output: Hash algo: crc32
246 13:28:21.853643 output: Hash value: cc4352de
247 13:28:21.853687 output: Image 2 (ramdisk-1)
248 13:28:21.853732 output: Description: unavailable
249 13:28:21.853776 output: Created: Fri Sep 8 14:28:21 2023
250 13:28:21.853828 output: Type: RAMDisk Image
251 13:28:21.853876 output: Compression: Unknown Compression
252 13:28:21.853925 output: Data Size: 21386593 Bytes = 20885.34 KiB = 20.40 MiB
253 13:28:21.853971 output: Architecture: AArch64
254 13:28:21.854016 output: OS: Linux
255 13:28:21.854061 output: Load Address: unavailable
256 13:28:21.854105 output: Entry Point: unavailable
257 13:28:21.854150 output: Hash algo: crc32
258 13:28:21.854195 output: Hash value: 0564c8ca
259 13:28:21.854240 output: Default Configuration: 'conf-1'
260 13:28:21.854286 output: Configuration 0 (conf-1)
261 13:28:21.854340 output: Description: mt8192-asurada-spherion-r0
262 13:28:21.854384 output: Kernel: kernel-1
263 13:28:21.854427 output: Init Ramdisk: ramdisk-1
264 13:28:21.854470 output: FDT: fdt-1
265 13:28:21.854514 output: Loadables: kernel-1
266 13:28:21.854558 output:
267 13:28:21.854713 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
268 13:28:21.854794 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
269 13:28:21.854871 end: 1.5 prepare-tftp-overlay (duration 00:00:15) [common]
270 13:28:21.854962 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:44) [common]
271 13:28:21.855026 No LXC device requested
272 13:28:21.855091 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 13:28:21.855160 start: 1.7 deploy-device-env (timeout 00:09:44) [common]
274 13:28:21.855221 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 13:28:21.855279 Checking files for TFTP limit of 4294967296 bytes.
276 13:28:21.855679 end: 1 tftp-deploy (duration 00:00:16) [common]
277 13:28:21.855765 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 13:28:21.855837 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 13:28:21.855944 substitutions:
280 13:28:21.855997 - {DTB}: 11471184/tftp-deploy-xgwar0g1/dtb/mt8192-asurada-spherion-r0.dtb
281 13:28:21.856048 - {INITRD}: 11471184/tftp-deploy-xgwar0g1/ramdisk/ramdisk.cpio.gz
282 13:28:21.856099 - {KERNEL}: 11471184/tftp-deploy-xgwar0g1/kernel/Image
283 13:28:21.856143 - {LAVA_MAC}: None
284 13:28:21.856193 - {PRESEED_CONFIG}: None
285 13:28:21.856237 - {PRESEED_LOCAL}: None
286 13:28:21.856288 - {RAMDISK}: 11471184/tftp-deploy-xgwar0g1/ramdisk/ramdisk.cpio.gz
287 13:28:21.856335 - {ROOT_PART}: None
288 13:28:21.856385 - {ROOT}: None
289 13:28:21.856429 - {SERVER_IP}: 192.168.201.1
290 13:28:21.856478 - {TEE}: None
291 13:28:21.856528 Parsed boot commands:
292 13:28:21.856599 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 13:28:21.856751 Parsed boot commands: tftpboot 192.168.201.1 11471184/tftp-deploy-xgwar0g1/kernel/image.itb 11471184/tftp-deploy-xgwar0g1/kernel/cmdline
294 13:28:21.856826 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 13:28:21.856895 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 13:28:21.856966 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 13:28:21.857033 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 13:28:21.857090 Not connected, no need to disconnect.
299 13:28:21.857149 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 13:28:21.857212 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 13:28:21.857266 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
302 13:28:21.860070 Setting prompt string to ['lava-test: # ']
303 13:28:21.860334 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 13:28:21.860428 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 13:28:21.860513 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 13:28:21.860685 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 13:28:21.860843 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
308 13:28:26.986255 >> Command sent successfully.
309 13:28:26.988612 Returned 0 in 5 seconds
310 13:28:27.088966 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 13:28:27.089284 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 13:28:27.089377 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 13:28:27.089467 Setting prompt string to 'Starting depthcharge on Spherion...'
315 13:28:27.089530 Changing prompt to 'Starting depthcharge on Spherion...'
316 13:28:27.089589 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 13:28:27.089813 [Enter `^Ec?' for help]
318 13:28:27.268429
319 13:28:27.268580
320 13:28:27.268639 F0: 102B 0000
321 13:28:27.268691
322 13:28:27.268738 F3: 1001 0000 [0200]
323 13:28:27.268783
324 13:28:27.272056 F3: 1001 0000
325 13:28:27.272144
326 13:28:27.272203 F7: 102D 0000
327 13:28:27.272256
328 13:28:27.272314 F1: 0000 0000
329 13:28:27.272367
330 13:28:27.275852 V0: 0000 0000 [0001]
331 13:28:27.275930
332 13:28:27.275986 00: 0007 8000
333 13:28:27.276039
334 13:28:27.280292 01: 0000 0000
335 13:28:27.280371
336 13:28:27.280427 BP: 0C00 0209 [0000]
337 13:28:27.280475
338 13:28:27.280522 G0: 1182 0000
339 13:28:27.283260
340 13:28:27.283338 EC: 0000 0021 [4000]
341 13:28:27.283393
342 13:28:27.287063 S7: 0000 0000 [0000]
343 13:28:27.287141
344 13:28:27.287195 CC: 0000 0000 [0001]
345 13:28:27.287242
346 13:28:27.290949 T0: 0000 0040 [010F]
347 13:28:27.291028
348 13:28:27.291082 Jump to BL
349 13:28:27.291130
350 13:28:27.315737
351 13:28:27.315872
352 13:28:27.315933
353 13:28:27.322754 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 13:28:27.326248 ARM64: Exception handlers installed.
355 13:28:27.330129 ARM64: Testing exception
356 13:28:27.333613 ARM64: Done test exception
357 13:28:27.341436 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 13:28:27.349119 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 13:28:27.355696 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 13:28:27.365795 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 13:28:27.372283 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 13:28:27.382633 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 13:28:27.393294 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 13:28:27.399844 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 13:28:27.417707 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 13:28:27.421079 WDT: Last reset was cold boot
367 13:28:27.424377 SPI1(PAD0) initialized at 2873684 Hz
368 13:28:27.427895 SPI5(PAD0) initialized at 992727 Hz
369 13:28:27.431127 VBOOT: Loading verstage.
370 13:28:27.437604 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 13:28:27.440871 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 13:28:27.444191 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 13:28:27.447854 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 13:28:27.455373 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 13:28:27.461596 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 13:28:27.473023 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
377 13:28:27.473097
378 13:28:27.473150
379 13:28:27.482848 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 13:28:27.486236 ARM64: Exception handlers installed.
381 13:28:27.489099 ARM64: Testing exception
382 13:28:27.489172 ARM64: Done test exception
383 13:28:27.496137 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 13:28:27.499294 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 13:28:27.514153 Probing TPM: . done!
386 13:28:27.514250 TPM ready after 0 ms
387 13:28:27.520600 Connected to device vid:did:rid of 1ae0:0028:00
388 13:28:27.527953 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
389 13:28:27.577797 Initialized TPM device CR50 revision 0
390 13:28:27.581246 tlcl_send_startup: Startup return code is 0
391 13:28:27.590004 TPM: setup succeeded
392 13:28:27.600707 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 13:28:27.610435 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 13:28:27.619360 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 13:28:27.628336 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 13:28:27.631973 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 13:28:27.635456 in-header: 03 07 00 00 08 00 00 00
398 13:28:27.638333 in-data: aa e4 47 04 13 02 00 00
399 13:28:27.642136 Chrome EC: UHEPI supported
400 13:28:27.648705 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 13:28:27.652659 in-header: 03 95 00 00 08 00 00 00
402 13:28:27.655923 in-data: 18 20 20 08 00 00 00 00
403 13:28:27.656046 Phase 1
404 13:28:27.659176 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 13:28:27.666929 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 13:28:27.670393 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 13:28:27.673969 Recovery requested (1009000e)
408 13:28:27.683154 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 13:28:27.688528 tlcl_extend: response is 0
410 13:28:27.697865 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 13:28:27.703519 tlcl_extend: response is 0
412 13:28:27.710626 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 13:28:27.730749 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
414 13:28:27.738415 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 13:28:27.738503
416 13:28:27.738558
417 13:28:27.749113 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 13:28:27.749195 ARM64: Exception handlers installed.
419 13:28:27.752685 ARM64: Testing exception
420 13:28:27.756361 ARM64: Done test exception
421 13:28:27.776176 pmic_efuse_setting: Set efuses in 11 msecs
422 13:28:27.779559 pmwrap_interface_init: Select PMIF_VLD_RDY
423 13:28:27.786639 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 13:28:27.789233 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 13:28:27.795926 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 13:28:27.799238 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 13:28:27.805929 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 13:28:27.809290 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 13:28:27.813038 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 13:28:27.819281 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 13:28:27.822940 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 13:28:27.829377 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 13:28:27.832650 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 13:28:27.836496 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 13:28:27.842694 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 13:28:27.849825 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 13:28:27.852768 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 13:28:27.860326 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 13:28:27.864298 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 13:28:27.871108 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 13:28:27.878716 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 13:28:27.882274 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 13:28:27.889420 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 13:28:27.893136 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 13:28:27.900642 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 13:28:27.904185 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 13:28:27.911781 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 13:28:27.914909 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 13:28:27.922420 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 13:28:27.926049 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 13:28:27.929566 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 13:28:27.936793 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 13:28:27.940499 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 13:28:27.944332 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 13:28:27.951577 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 13:28:27.955175 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 13:28:27.958649 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 13:28:27.965905 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 13:28:27.969626 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 13:28:27.976299 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 13:28:27.980074 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 13:28:27.983705 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 13:28:27.987032 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 13:28:27.994497 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 13:28:27.998099 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 13:28:28.001452 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 13:28:28.004979 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 13:28:28.008843 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 13:28:28.015943 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 13:28:28.019421 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 13:28:28.023021 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 13:28:28.026729 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 13:28:28.030393 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 13:28:28.037573 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 13:28:28.048806 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 13:28:28.052462 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 13:28:28.059725 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 13:28:28.066985 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 13:28:28.074532 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 13:28:28.077714 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 13:28:28.081518 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 13:28:28.089513 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x15
483 13:28:28.093311 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 13:28:28.101155 [RTC]rtc_osc_init,62: osc32con val = 0xde70
485 13:28:28.104565 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 13:28:28.113530 [RTC]rtc_get_frequency_meter,154: input=15, output=765
487 13:28:28.123338 [RTC]rtc_get_frequency_meter,154: input=23, output=948
488 13:28:28.132831 [RTC]rtc_get_frequency_meter,154: input=19, output=857
489 13:28:28.142268 [RTC]rtc_get_frequency_meter,154: input=17, output=810
490 13:28:28.151800 [RTC]rtc_get_frequency_meter,154: input=16, output=786
491 13:28:28.161377 [RTC]rtc_get_frequency_meter,154: input=16, output=787
492 13:28:28.171133 [RTC]rtc_get_frequency_meter,154: input=17, output=811
493 13:28:28.175374 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
494 13:28:28.178798 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
495 13:28:28.182422 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
496 13:28:28.189778 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
497 13:28:28.193803 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
498 13:28:28.197490 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
499 13:28:28.201390 ADC[4]: Raw value=670800 ID=5
500 13:28:28.201466 ADC[3]: Raw value=212917 ID=1
501 13:28:28.204900 RAM Code: 0x51
502 13:28:28.208337 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
503 13:28:28.212278 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
504 13:28:28.223187 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
505 13:28:28.227093 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
506 13:28:28.230146 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
507 13:28:28.234016 in-header: 03 07 00 00 08 00 00 00
508 13:28:28.237365 in-data: aa e4 47 04 13 02 00 00
509 13:28:28.241473 Chrome EC: UHEPI supported
510 13:28:28.244694 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
511 13:28:28.248750 in-header: 03 95 00 00 08 00 00 00
512 13:28:28.252566 in-data: 18 20 20 08 00 00 00 00
513 13:28:28.256086 MRC: failed to locate region type 0.
514 13:28:28.263414 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
515 13:28:28.266981 DRAM-K: Running full calibration
516 13:28:28.270502 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
517 13:28:28.274172 header.status = 0x0
518 13:28:28.277963 header.version = 0x6 (expected: 0x6)
519 13:28:28.281324 header.size = 0xd00 (expected: 0xd00)
520 13:28:28.281402 header.flags = 0x0
521 13:28:28.288095 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
522 13:28:28.306085 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
523 13:28:28.313148 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
524 13:28:28.316916 dram_init: ddr_geometry: 0
525 13:28:28.316991 [EMI] MDL number = 0
526 13:28:28.320086 [EMI] Get MDL freq = 0
527 13:28:28.320179 dram_init: ddr_type: 0
528 13:28:28.323912 is_discrete_lpddr4: 1
529 13:28:28.327719 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
530 13:28:28.327809
531 13:28:28.327865
532 13:28:28.331437 [Bian_co] ETT version 0.0.0.1
533 13:28:28.335135 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
534 13:28:28.335215
535 13:28:28.338651 dramc_set_vcore_voltage set vcore to 650000
536 13:28:28.342387 Read voltage for 800, 4
537 13:28:28.342466 Vio18 = 0
538 13:28:28.342521 Vcore = 650000
539 13:28:28.342568 Vdram = 0
540 13:28:28.345824 Vddq = 0
541 13:28:28.345913 Vmddr = 0
542 13:28:28.350060 dram_init: config_dvfs: 1
543 13:28:28.353380 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
544 13:28:28.357233 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
545 13:28:28.361134 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
546 13:28:28.364213 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
547 13:28:28.368330 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
548 13:28:28.375215 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
549 13:28:28.375312 MEM_TYPE=3, freq_sel=18
550 13:28:28.378829 sv_algorithm_assistance_LP4_1600
551 13:28:28.382900 ============ PULL DRAM RESETB DOWN ============
552 13:28:28.385985 ========== PULL DRAM RESETB DOWN end =========
553 13:28:28.393201 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
554 13:28:28.393288 ===================================
555 13:28:28.397270 LPDDR4 DRAM CONFIGURATION
556 13:28:28.400946 ===================================
557 13:28:28.404393 EX_ROW_EN[0] = 0x0
558 13:28:28.404483 EX_ROW_EN[1] = 0x0
559 13:28:28.408240 LP4Y_EN = 0x0
560 13:28:28.408323 WORK_FSP = 0x0
561 13:28:28.408379 WL = 0x2
562 13:28:28.411580 RL = 0x2
563 13:28:28.415524 BL = 0x2
564 13:28:28.415614 RPST = 0x0
565 13:28:28.415678 RD_PRE = 0x0
566 13:28:28.418839 WR_PRE = 0x1
567 13:28:28.418917 WR_PST = 0x0
568 13:28:28.422579 DBI_WR = 0x0
569 13:28:28.422676 DBI_RD = 0x0
570 13:28:28.426419 OTF = 0x1
571 13:28:28.429647 ===================================
572 13:28:28.433643 ===================================
573 13:28:28.433725 ANA top config
574 13:28:28.437519 ===================================
575 13:28:28.440668 DLL_ASYNC_EN = 0
576 13:28:28.440748 ALL_SLAVE_EN = 1
577 13:28:28.444352 NEW_RANK_MODE = 1
578 13:28:28.448035 DLL_IDLE_MODE = 1
579 13:28:28.448115 LP45_APHY_COMB_EN = 1
580 13:28:28.451688 TX_ODT_DIS = 1
581 13:28:28.455587 NEW_8X_MODE = 1
582 13:28:28.458754 ===================================
583 13:28:28.461979 ===================================
584 13:28:28.465353 data_rate = 1600
585 13:28:28.465436 CKR = 1
586 13:28:28.468891 DQ_P2S_RATIO = 8
587 13:28:28.471784 ===================================
588 13:28:28.475851 CA_P2S_RATIO = 8
589 13:28:28.479303 DQ_CA_OPEN = 0
590 13:28:28.482619 DQ_SEMI_OPEN = 0
591 13:28:28.482711 CA_SEMI_OPEN = 0
592 13:28:28.486817 CA_FULL_RATE = 0
593 13:28:28.490146 DQ_CKDIV4_EN = 1
594 13:28:28.493682 CA_CKDIV4_EN = 1
595 13:28:28.493765 CA_PREDIV_EN = 0
596 13:28:28.497235 PH8_DLY = 0
597 13:28:28.500791 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
598 13:28:28.503986 DQ_AAMCK_DIV = 4
599 13:28:28.507694 CA_AAMCK_DIV = 4
600 13:28:28.507773 CA_ADMCK_DIV = 4
601 13:28:28.511197 DQ_TRACK_CA_EN = 0
602 13:28:28.514646 CA_PICK = 800
603 13:28:28.517533 CA_MCKIO = 800
604 13:28:28.521389 MCKIO_SEMI = 0
605 13:28:28.524556 PLL_FREQ = 3068
606 13:28:28.524647 DQ_UI_PI_RATIO = 32
607 13:28:28.528066 CA_UI_PI_RATIO = 0
608 13:28:28.531475 ===================================
609 13:28:28.534588 ===================================
610 13:28:28.538043 memory_type:LPDDR4
611 13:28:28.541600 GP_NUM : 10
612 13:28:28.541680 SRAM_EN : 1
613 13:28:28.545436 MD32_EN : 0
614 13:28:28.545536 ===================================
615 13:28:28.548784 [ANA_INIT] >>>>>>>>>>>>>>
616 13:28:28.552879 <<<<<< [CONFIGURE PHASE]: ANA_TX
617 13:28:28.556535 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
618 13:28:28.559689 ===================================
619 13:28:28.563836 data_rate = 1600,PCW = 0X7600
620 13:28:28.563921 ===================================
621 13:28:28.567706 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
622 13:28:28.574175 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
623 13:28:28.580802 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
624 13:28:28.584362 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
625 13:28:28.587573 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
626 13:28:28.591021 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
627 13:28:28.594688 [ANA_INIT] flow start
628 13:28:28.594779 [ANA_INIT] PLL >>>>>>>>
629 13:28:28.597557 [ANA_INIT] PLL <<<<<<<<
630 13:28:28.601116 [ANA_INIT] MIDPI >>>>>>>>
631 13:28:28.601197 [ANA_INIT] MIDPI <<<<<<<<
632 13:28:28.604606 [ANA_INIT] DLL >>>>>>>>
633 13:28:28.607413 [ANA_INIT] flow end
634 13:28:28.611290 ============ LP4 DIFF to SE enter ============
635 13:28:28.614132 ============ LP4 DIFF to SE exit ============
636 13:28:28.617753 [ANA_INIT] <<<<<<<<<<<<<
637 13:28:28.620809 [Flow] Enable top DCM control >>>>>
638 13:28:28.624406 [Flow] Enable top DCM control <<<<<
639 13:28:28.627332 Enable DLL master slave shuffle
640 13:28:28.631140 ==============================================================
641 13:28:28.634444 Gating Mode config
642 13:28:28.641150 ==============================================================
643 13:28:28.641238 Config description:
644 13:28:28.650711 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
645 13:28:28.657576 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
646 13:28:28.661163 SELPH_MODE 0: By rank 1: By Phase
647 13:28:28.667371 ==============================================================
648 13:28:28.670973 GAT_TRACK_EN = 1
649 13:28:28.674360 RX_GATING_MODE = 2
650 13:28:28.677271 RX_GATING_TRACK_MODE = 2
651 13:28:28.680663 SELPH_MODE = 1
652 13:28:28.684043 PICG_EARLY_EN = 1
653 13:28:28.687437 VALID_LAT_VALUE = 1
654 13:28:28.690763 ==============================================================
655 13:28:28.694120 Enter into Gating configuration >>>>
656 13:28:28.697278 Exit from Gating configuration <<<<
657 13:28:28.700602 Enter into DVFS_PRE_config >>>>>
658 13:28:28.710765 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
659 13:28:28.713902 Exit from DVFS_PRE_config <<<<<
660 13:28:28.717292 Enter into PICG configuration >>>>
661 13:28:28.720548 Exit from PICG configuration <<<<
662 13:28:28.724141 [RX_INPUT] configuration >>>>>
663 13:28:28.728007 [RX_INPUT] configuration <<<<<
664 13:28:28.734266 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
665 13:28:28.737478 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
666 13:28:28.744224 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
667 13:28:28.750755 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
668 13:28:28.757476 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
669 13:28:28.764169 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
670 13:28:28.767606 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
671 13:28:28.770692 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
672 13:28:28.774004 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
673 13:28:28.780548 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
674 13:28:28.784428 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
675 13:28:28.787472 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
676 13:28:28.790493 ===================================
677 13:28:28.794054 LPDDR4 DRAM CONFIGURATION
678 13:28:28.797169 ===================================
679 13:28:28.797249 EX_ROW_EN[0] = 0x0
680 13:28:28.800285 EX_ROW_EN[1] = 0x0
681 13:28:28.800364 LP4Y_EN = 0x0
682 13:28:28.804008 WORK_FSP = 0x0
683 13:28:28.807286 WL = 0x2
684 13:28:28.807360 RL = 0x2
685 13:28:28.810501 BL = 0x2
686 13:28:28.810577 RPST = 0x0
687 13:28:28.813639 RD_PRE = 0x0
688 13:28:28.813718 WR_PRE = 0x1
689 13:28:28.817201 WR_PST = 0x0
690 13:28:28.817275 DBI_WR = 0x0
691 13:28:28.820216 DBI_RD = 0x0
692 13:28:28.820308 OTF = 0x1
693 13:28:28.824161 ===================================
694 13:28:28.827490 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
695 13:28:28.833803 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
696 13:28:28.837324 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 13:28:28.840568 ===================================
698 13:28:28.843652 LPDDR4 DRAM CONFIGURATION
699 13:28:28.847386 ===================================
700 13:28:28.847462 EX_ROW_EN[0] = 0x10
701 13:28:28.850272 EX_ROW_EN[1] = 0x0
702 13:28:28.850348 LP4Y_EN = 0x0
703 13:28:28.853722 WORK_FSP = 0x0
704 13:28:28.853798 WL = 0x2
705 13:28:28.857146 RL = 0x2
706 13:28:28.857220 BL = 0x2
707 13:28:28.860616 RPST = 0x0
708 13:28:28.860754 RD_PRE = 0x0
709 13:28:28.863570 WR_PRE = 0x1
710 13:28:28.867569 WR_PST = 0x0
711 13:28:28.867645 DBI_WR = 0x0
712 13:28:28.870466 DBI_RD = 0x0
713 13:28:28.870540 OTF = 0x1
714 13:28:28.874021 ===================================
715 13:28:28.880175 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
716 13:28:28.883797 nWR fixed to 40
717 13:28:28.887602 [ModeRegInit_LP4] CH0 RK0
718 13:28:28.887677 [ModeRegInit_LP4] CH0 RK1
719 13:28:28.890690 [ModeRegInit_LP4] CH1 RK0
720 13:28:28.893812 [ModeRegInit_LP4] CH1 RK1
721 13:28:28.893887 match AC timing 12
722 13:28:28.900524 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
723 13:28:28.903756 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
724 13:28:28.907273 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
725 13:28:28.913925 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
726 13:28:28.917438 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
727 13:28:28.917512 [EMI DOE] emi_dcm 0
728 13:28:28.924259 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
729 13:28:28.924363 ==
730 13:28:28.927032 Dram Type= 6, Freq= 0, CH_0, rank 0
731 13:28:28.930652 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
732 13:28:28.930728 ==
733 13:28:28.937328 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
734 13:28:28.943593 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
735 13:28:28.951337 [CA 0] Center 37 (7~68) winsize 62
736 13:28:28.955315 [CA 1] Center 37 (7~68) winsize 62
737 13:28:28.957834 [CA 2] Center 35 (5~66) winsize 62
738 13:28:28.961431 [CA 3] Center 35 (5~66) winsize 62
739 13:28:28.964530 [CA 4] Center 34 (4~65) winsize 62
740 13:28:28.967897 [CA 5] Center 33 (3~64) winsize 62
741 13:28:28.967974
742 13:28:28.971500 [CmdBusTrainingLP45] Vref(ca) range 1: 30
743 13:28:28.971577
744 13:28:28.974886 [CATrainingPosCal] consider 1 rank data
745 13:28:28.978120 u2DelayCellTimex100 = 270/100 ps
746 13:28:28.981341 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
747 13:28:28.984775 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
748 13:28:28.991651 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
749 13:28:28.994534 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
750 13:28:28.998144 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
751 13:28:29.001284 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
752 13:28:29.001359
753 13:28:29.004543 CA PerBit enable=1, Macro0, CA PI delay=33
754 13:28:29.004633
755 13:28:29.008021 [CBTSetCACLKResult] CA Dly = 33
756 13:28:29.008097 CS Dly: 5 (0~36)
757 13:28:29.011083 ==
758 13:28:29.011164 Dram Type= 6, Freq= 0, CH_0, rank 1
759 13:28:29.018004 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
760 13:28:29.018079 ==
761 13:28:29.021434 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
762 13:28:29.027944 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
763 13:28:29.037256 [CA 0] Center 37 (7~68) winsize 62
764 13:28:29.040877 [CA 1] Center 37 (7~68) winsize 62
765 13:28:29.043933 [CA 2] Center 35 (5~66) winsize 62
766 13:28:29.047437 [CA 3] Center 35 (4~66) winsize 63
767 13:28:29.051074 [CA 4] Center 34 (4~64) winsize 61
768 13:28:29.054375 [CA 5] Center 34 (3~65) winsize 63
769 13:28:29.054449
770 13:28:29.057476 [CmdBusTrainingLP45] Vref(ca) range 1: 32
771 13:28:29.057553
772 13:28:29.061065 [CATrainingPosCal] consider 2 rank data
773 13:28:29.064111 u2DelayCellTimex100 = 270/100 ps
774 13:28:29.067394 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
775 13:28:29.070704 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
776 13:28:29.074480 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
777 13:28:29.080721 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
778 13:28:29.084462 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
779 13:28:29.087663 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
780 13:28:29.087740
781 13:28:29.091061 CA PerBit enable=1, Macro0, CA PI delay=33
782 13:28:29.091137
783 13:28:29.094228 [CBTSetCACLKResult] CA Dly = 33
784 13:28:29.094317 CS Dly: 5 (0~37)
785 13:28:29.094370
786 13:28:29.097918 ----->DramcWriteLeveling(PI) begin...
787 13:28:29.097994 ==
788 13:28:29.100694 Dram Type= 6, Freq= 0, CH_0, rank 0
789 13:28:29.107453 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
790 13:28:29.107541 ==
791 13:28:29.111294 Write leveling (Byte 0): 28 => 28
792 13:28:29.114146 Write leveling (Byte 1): 31 => 31
793 13:28:29.114230 DramcWriteLeveling(PI) end<-----
794 13:28:29.118205
795 13:28:29.118314 ==
796 13:28:29.121492 Dram Type= 6, Freq= 0, CH_0, rank 0
797 13:28:29.125172 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
798 13:28:29.125251 ==
799 13:28:29.128871 [Gating] SW mode calibration
800 13:28:29.136135 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
801 13:28:29.139144 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
802 13:28:29.142427 0 6 0 | B1->B0 | 3333 3434 | 0 0 | (0 0) (0 1)
803 13:28:29.149412 0 6 4 | B1->B0 | 2424 2424 | 0 0 | (1 1) (0 0)
804 13:28:29.152658 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 13:28:29.156201 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 13:28:29.159120 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 13:28:29.166283 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 13:28:29.169302 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 13:28:29.172476 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 13:28:29.179319 0 7 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
811 13:28:29.182679 0 7 4 | B1->B0 | 4040 3f3f | 0 0 | (0 0) (0 0)
812 13:28:29.186144 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
813 13:28:29.192488 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
814 13:28:29.195701 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
815 13:28:29.199592 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
816 13:28:29.206258 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
817 13:28:29.209266 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
818 13:28:29.212840 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
819 13:28:29.219981 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
820 13:28:29.222681 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
821 13:28:29.225953 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
822 13:28:29.232857 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
823 13:28:29.235762 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
824 13:28:29.239380 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
825 13:28:29.245730 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
826 13:28:29.249469 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
827 13:28:29.252779 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
828 13:28:29.255874 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
829 13:28:29.262685 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
830 13:28:29.266060 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
831 13:28:29.269554 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 13:28:29.276237 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 13:28:29.279097 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 13:28:29.282277 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
835 13:28:29.289108 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 13:28:29.292208 Total UI for P1: 0, mck2ui 16
837 13:28:29.296067 best dqsien dly found for B0: ( 0, 10, 0)
838 13:28:29.298914 Total UI for P1: 0, mck2ui 16
839 13:28:29.302497 best dqsien dly found for B1: ( 0, 10, 0)
840 13:28:29.305730 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
841 13:28:29.309817 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
842 13:28:29.309905
843 13:28:29.312577 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
844 13:28:29.315562 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
845 13:28:29.319262 [Gating] SW calibration Done
846 13:28:29.319331 ==
847 13:28:29.322631 Dram Type= 6, Freq= 0, CH_0, rank 0
848 13:28:29.325753 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
849 13:28:29.325823 ==
850 13:28:29.329208 RX Vref Scan: 0
851 13:28:29.329280
852 13:28:29.329325 RX Vref 0 -> 0, step: 1
853 13:28:29.329379
854 13:28:29.332587 RX Delay -130 -> 252, step: 16
855 13:28:29.335667 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
856 13:28:29.342420 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
857 13:28:29.345534 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
858 13:28:29.348915 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
859 13:28:29.352478 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
860 13:28:29.356029 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
861 13:28:29.362420 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
862 13:28:29.365753 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
863 13:28:29.368838 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
864 13:28:29.372225 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
865 13:28:29.375496 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
866 13:28:29.382313 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
867 13:28:29.385705 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
868 13:28:29.389269 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
869 13:28:29.392111 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
870 13:28:29.399162 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
871 13:28:29.399238 ==
872 13:28:29.402385 Dram Type= 6, Freq= 0, CH_0, rank 0
873 13:28:29.405962 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
874 13:28:29.406050 ==
875 13:28:29.406109 DQS Delay:
876 13:28:29.409177 DQS0 = 0, DQS1 = 0
877 13:28:29.409252 DQM Delay:
878 13:28:29.412061 DQM0 = 83, DQM1 = 75
879 13:28:29.412136 DQ Delay:
880 13:28:29.415770 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
881 13:28:29.418890 DQ4 =77, DQ5 =69, DQ6 =101, DQ7 =101
882 13:28:29.422064 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
883 13:28:29.425413 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
884 13:28:29.425492
885 13:28:29.425548
886 13:28:29.425597 ==
887 13:28:29.428750 Dram Type= 6, Freq= 0, CH_0, rank 0
888 13:28:29.431993 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
889 13:28:29.432069 ==
890 13:28:29.432123
891 13:28:29.435593
892 13:28:29.435669 TX Vref Scan disable
893 13:28:29.438808 == TX Byte 0 ==
894 13:28:29.442251 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
895 13:28:29.445403 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
896 13:28:29.448967 == TX Byte 1 ==
897 13:28:29.452130 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
898 13:28:29.455671 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
899 13:28:29.455747 ==
900 13:28:29.459325 Dram Type= 6, Freq= 0, CH_0, rank 0
901 13:28:29.466027 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
902 13:28:29.466101 ==
903 13:28:29.477038 TX Vref=22, minBit 0, minWin=27, winSum=443
904 13:28:29.480917 TX Vref=24, minBit 2, minWin=27, winSum=448
905 13:28:29.484016 TX Vref=26, minBit 4, minWin=27, winSum=450
906 13:28:29.487377 TX Vref=28, minBit 4, minWin=27, winSum=455
907 13:28:29.490564 TX Vref=30, minBit 0, minWin=28, winSum=455
908 13:28:29.493747 TX Vref=32, minBit 0, minWin=28, winSum=455
909 13:28:29.500198 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 30
910 13:28:29.500283
911 13:28:29.503936 Final TX Range 1 Vref 30
912 13:28:29.504012
913 13:28:29.504065 ==
914 13:28:29.507178 Dram Type= 6, Freq= 0, CH_0, rank 0
915 13:28:29.510531 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
916 13:28:29.510607 ==
917 13:28:29.513821
918 13:28:29.513895
919 13:28:29.513965 TX Vref Scan disable
920 13:28:29.517486 == TX Byte 0 ==
921 13:28:29.520942 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
922 13:28:29.524836 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
923 13:28:29.527951 == TX Byte 1 ==
924 13:28:29.531192 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
925 13:28:29.534151 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
926 13:28:29.534228
927 13:28:29.537841 [DATLAT]
928 13:28:29.537917 Freq=800, CH0 RK0
929 13:28:29.537972
930 13:28:29.541311 DATLAT Default: 0xa
931 13:28:29.541385 0, 0xFFFF, sum = 0
932 13:28:29.544197 1, 0xFFFF, sum = 0
933 13:28:29.544280 2, 0xFFFF, sum = 0
934 13:28:29.547540 3, 0xFFFF, sum = 0
935 13:28:29.547616 4, 0xFFFF, sum = 0
936 13:28:29.550870 5, 0xFFFF, sum = 0
937 13:28:29.550946 6, 0xFFFF, sum = 0
938 13:28:29.554126 7, 0xFFFF, sum = 0
939 13:28:29.554201 8, 0x0, sum = 1
940 13:28:29.557683 9, 0x0, sum = 2
941 13:28:29.557761 10, 0x0, sum = 3
942 13:28:29.560875 11, 0x0, sum = 4
943 13:28:29.560951 best_step = 9
944 13:28:29.561005
945 13:28:29.561065 ==
946 13:28:29.564178 Dram Type= 6, Freq= 0, CH_0, rank 0
947 13:28:29.567859 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
948 13:28:29.570682 ==
949 13:28:29.570757 RX Vref Scan: 1
950 13:28:29.570811
951 13:28:29.574510 Set Vref Range= 32 -> 127
952 13:28:29.574599
953 13:28:29.577372 RX Vref 32 -> 127, step: 1
954 13:28:29.577447
955 13:28:29.577516 RX Delay -111 -> 252, step: 8
956 13:28:29.577594
957 13:28:29.580667 Set Vref, RX VrefLevel [Byte0]: 32
958 13:28:29.584169 [Byte1]: 32
959 13:28:29.587949
960 13:28:29.588022 Set Vref, RX VrefLevel [Byte0]: 33
961 13:28:29.591287 [Byte1]: 33
962 13:28:29.595515
963 13:28:29.595594 Set Vref, RX VrefLevel [Byte0]: 34
964 13:28:29.599302 [Byte1]: 34
965 13:28:29.603453
966 13:28:29.603533 Set Vref, RX VrefLevel [Byte0]: 35
967 13:28:29.606671 [Byte1]: 35
968 13:28:29.611191
969 13:28:29.611333 Set Vref, RX VrefLevel [Byte0]: 36
970 13:28:29.614516 [Byte1]: 36
971 13:28:29.618644
972 13:28:29.618770 Set Vref, RX VrefLevel [Byte0]: 37
973 13:28:29.622277 [Byte1]: 37
974 13:28:29.626493
975 13:28:29.626597 Set Vref, RX VrefLevel [Byte0]: 38
976 13:28:29.629444 [Byte1]: 38
977 13:28:29.633871
978 13:28:29.633952 Set Vref, RX VrefLevel [Byte0]: 39
979 13:28:29.637417 [Byte1]: 39
980 13:28:29.641871
981 13:28:29.641956 Set Vref, RX VrefLevel [Byte0]: 40
982 13:28:29.644767 [Byte1]: 40
983 13:28:29.649493
984 13:28:29.649569 Set Vref, RX VrefLevel [Byte0]: 41
985 13:28:29.652875 [Byte1]: 41
986 13:28:29.656661
987 13:28:29.656739 Set Vref, RX VrefLevel [Byte0]: 42
988 13:28:29.660340 [Byte1]: 42
989 13:28:29.664687
990 13:28:29.664767 Set Vref, RX VrefLevel [Byte0]: 43
991 13:28:29.667916 [Byte1]: 43
992 13:28:29.672417
993 13:28:29.672493 Set Vref, RX VrefLevel [Byte0]: 44
994 13:28:29.675539 [Byte1]: 44
995 13:28:29.679814
996 13:28:29.679889 Set Vref, RX VrefLevel [Byte0]: 45
997 13:28:29.683073 [Byte1]: 45
998 13:28:29.687451
999 13:28:29.687527 Set Vref, RX VrefLevel [Byte0]: 46
1000 13:28:29.690669 [Byte1]: 46
1001 13:28:29.695075
1002 13:28:29.695166 Set Vref, RX VrefLevel [Byte0]: 47
1003 13:28:29.698486 [Byte1]: 47
1004 13:28:29.702956
1005 13:28:29.703031 Set Vref, RX VrefLevel [Byte0]: 48
1006 13:28:29.705916 [Byte1]: 48
1007 13:28:29.710402
1008 13:28:29.710478 Set Vref, RX VrefLevel [Byte0]: 49
1009 13:28:29.713769 [Byte1]: 49
1010 13:28:29.717991
1011 13:28:29.718088 Set Vref, RX VrefLevel [Byte0]: 50
1012 13:28:29.721409 [Byte1]: 50
1013 13:28:29.726478
1014 13:28:29.726567 Set Vref, RX VrefLevel [Byte0]: 51
1015 13:28:29.728839 [Byte1]: 51
1016 13:28:29.733309
1017 13:28:29.733381 Set Vref, RX VrefLevel [Byte0]: 52
1018 13:28:29.736796 [Byte1]: 52
1019 13:28:29.741197
1020 13:28:29.741273 Set Vref, RX VrefLevel [Byte0]: 53
1021 13:28:29.744522 [Byte1]: 53
1022 13:28:29.749120
1023 13:28:29.749201 Set Vref, RX VrefLevel [Byte0]: 54
1024 13:28:29.752182 [Byte1]: 54
1025 13:28:29.756437
1026 13:28:29.756512 Set Vref, RX VrefLevel [Byte0]: 55
1027 13:28:29.760207 [Byte1]: 55
1028 13:28:29.764296
1029 13:28:29.764376 Set Vref, RX VrefLevel [Byte0]: 56
1030 13:28:29.767341 [Byte1]: 56
1031 13:28:29.772034
1032 13:28:29.772108 Set Vref, RX VrefLevel [Byte0]: 57
1033 13:28:29.774958 [Byte1]: 57
1034 13:28:29.779425
1035 13:28:29.779499 Set Vref, RX VrefLevel [Byte0]: 58
1036 13:28:29.783067 [Byte1]: 58
1037 13:28:29.787414
1038 13:28:29.787490 Set Vref, RX VrefLevel [Byte0]: 59
1039 13:28:29.790619 [Byte1]: 59
1040 13:28:29.795492
1041 13:28:29.795564 Set Vref, RX VrefLevel [Byte0]: 60
1042 13:28:29.798681 [Byte1]: 60
1043 13:28:29.802471
1044 13:28:29.802545 Set Vref, RX VrefLevel [Byte0]: 61
1045 13:28:29.806104 [Byte1]: 61
1046 13:28:29.810223
1047 13:28:29.810299 Set Vref, RX VrefLevel [Byte0]: 62
1048 13:28:29.813795 [Byte1]: 62
1049 13:28:29.818122
1050 13:28:29.818199 Set Vref, RX VrefLevel [Byte0]: 63
1051 13:28:29.820982 [Byte1]: 63
1052 13:28:29.825314
1053 13:28:29.825406 Set Vref, RX VrefLevel [Byte0]: 64
1054 13:28:29.828555 [Byte1]: 64
1055 13:28:29.832772
1056 13:28:29.832846 Set Vref, RX VrefLevel [Byte0]: 65
1057 13:28:29.836058 [Byte1]: 65
1058 13:28:29.840543
1059 13:28:29.840616 Set Vref, RX VrefLevel [Byte0]: 66
1060 13:28:29.843846 [Byte1]: 66
1061 13:28:29.848040
1062 13:28:29.848129 Set Vref, RX VrefLevel [Byte0]: 67
1063 13:28:29.851463 [Byte1]: 67
1064 13:28:29.855632
1065 13:28:29.855706 Set Vref, RX VrefLevel [Byte0]: 68
1066 13:28:29.859083 [Byte1]: 68
1067 13:28:29.863326
1068 13:28:29.863399 Set Vref, RX VrefLevel [Byte0]: 69
1069 13:28:29.866940 [Byte1]: 69
1070 13:28:29.870805
1071 13:28:29.870879 Set Vref, RX VrefLevel [Byte0]: 70
1072 13:28:29.874091 [Byte1]: 70
1073 13:28:29.878789
1074 13:28:29.878863 Set Vref, RX VrefLevel [Byte0]: 71
1075 13:28:29.882105 [Byte1]: 71
1076 13:28:29.886065
1077 13:28:29.886143 Set Vref, RX VrefLevel [Byte0]: 72
1078 13:28:29.889485 [Byte1]: 72
1079 13:28:29.894457
1080 13:28:29.894524 Set Vref, RX VrefLevel [Byte0]: 73
1081 13:28:29.897402 [Byte1]: 73
1082 13:28:29.901466
1083 13:28:29.901532 Final RX Vref Byte 0 = 52 to rank0
1084 13:28:29.904594 Final RX Vref Byte 1 = 55 to rank0
1085 13:28:29.908259 Final RX Vref Byte 0 = 52 to rank1
1086 13:28:29.911421 Final RX Vref Byte 1 = 55 to rank1==
1087 13:28:29.914745 Dram Type= 6, Freq= 0, CH_0, rank 0
1088 13:28:29.921328 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1089 13:28:29.921397 ==
1090 13:28:29.921461 DQS Delay:
1091 13:28:29.921511 DQS0 = 0, DQS1 = 0
1092 13:28:29.925339 DQM Delay:
1093 13:28:29.925406 DQM0 = 83, DQM1 = 73
1094 13:28:29.928212 DQ Delay:
1095 13:28:29.931298 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1096 13:28:29.931360 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1097 13:28:29.934972 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =64
1098 13:28:29.941678 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1099 13:28:29.941736
1100 13:28:29.941782
1101 13:28:29.947901 [DQSOSCAuto] RK0, (LSB)MR18= 0x3535, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1102 13:28:29.951908 CH0 RK0: MR19=606, MR18=3535
1103 13:28:29.958367 CH0_RK0: MR19=0x606, MR18=0x3535, DQSOSC=396, MR23=63, INC=94, DEC=62
1104 13:28:29.958443
1105 13:28:29.961749 ----->DramcWriteLeveling(PI) begin...
1106 13:28:29.961823 ==
1107 13:28:29.964661 Dram Type= 6, Freq= 0, CH_0, rank 1
1108 13:28:29.967868 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1109 13:28:29.967950 ==
1110 13:28:29.971236 Write leveling (Byte 0): 28 => 28
1111 13:28:29.974854 Write leveling (Byte 1): 28 => 28
1112 13:28:29.978493 DramcWriteLeveling(PI) end<-----
1113 13:28:29.978567
1114 13:28:29.978619 ==
1115 13:28:29.981630 Dram Type= 6, Freq= 0, CH_0, rank 1
1116 13:28:29.984691 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1117 13:28:29.984764 ==
1118 13:28:29.988030 [Gating] SW mode calibration
1119 13:28:29.994637 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1120 13:28:30.001440 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1121 13:28:30.004685 0 6 0 | B1->B0 | 3333 3030 | 1 0 | (1 0) (0 1)
1122 13:28:30.008183 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1123 13:28:30.014687 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1124 13:28:30.018263 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1125 13:28:30.021265 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1126 13:28:30.027924 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1127 13:28:30.031525 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1128 13:28:30.035047 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1129 13:28:30.041309 0 7 0 | B1->B0 | 2e2e 3535 | 0 0 | (0 0) (0 0)
1130 13:28:30.044981 0 7 4 | B1->B0 | 3f3f 4545 | 0 0 | (0 0) (0 0)
1131 13:28:30.047938 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1132 13:28:30.054507 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1133 13:28:30.058552 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1134 13:28:30.061474 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1135 13:28:30.064861 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1136 13:28:30.071594 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1137 13:28:30.074951 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1138 13:28:30.078229 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1139 13:28:30.084819 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1140 13:28:30.088546 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1141 13:28:30.091808 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1142 13:28:30.098622 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1143 13:28:30.101712 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1144 13:28:30.104776 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1145 13:28:30.111631 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1146 13:28:30.115006 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1147 13:28:30.118227 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1148 13:28:30.124902 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1149 13:28:30.128287 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1150 13:28:30.131390 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1151 13:28:30.138183 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1152 13:28:30.141743 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1153 13:28:30.145041 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1154 13:28:30.151381 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1155 13:28:30.154778 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1156 13:28:30.158308 Total UI for P1: 0, mck2ui 16
1157 13:28:30.161646 best dqsien dly found for B0: ( 0, 10, 2)
1158 13:28:30.165022 Total UI for P1: 0, mck2ui 16
1159 13:28:30.168113 best dqsien dly found for B1: ( 0, 10, 2)
1160 13:28:30.171691 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
1161 13:28:30.174998 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
1162 13:28:30.175098
1163 13:28:30.178220 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
1164 13:28:30.181982 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
1165 13:28:30.184843 [Gating] SW calibration Done
1166 13:28:30.184930 ==
1167 13:28:30.187813 Dram Type= 6, Freq= 0, CH_0, rank 1
1168 13:28:30.191875 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1169 13:28:30.191949 ==
1170 13:28:30.194743 RX Vref Scan: 0
1171 13:28:30.194806
1172 13:28:30.194868 RX Vref 0 -> 0, step: 1
1173 13:28:30.239114
1174 13:28:30.239199 RX Delay -130 -> 252, step: 16
1175 13:28:30.239440 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1176 13:28:30.239508 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1177 13:28:30.239587 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1178 13:28:30.239650 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1179 13:28:30.240185 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1180 13:28:30.240243 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1181 13:28:30.240506 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1182 13:28:30.240570 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1183 13:28:30.240619 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1184 13:28:30.241243 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1185 13:28:30.258880 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1186 13:28:30.259131 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1187 13:28:30.259192 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1188 13:28:30.260144 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1189 13:28:30.262687 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1190 13:28:30.265820 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1191 13:28:30.265893 ==
1192 13:28:30.265962 Dram Type= 6, Freq= 0, CH_0, rank 1
1193 13:28:30.272628 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1194 13:28:30.272706 ==
1195 13:28:30.272759 DQS Delay:
1196 13:28:30.272806 DQS0 = 0, DQS1 = 0
1197 13:28:30.276143 DQM Delay:
1198 13:28:30.276236 DQM0 = 82, DQM1 = 74
1199 13:28:30.279669 DQ Delay:
1200 13:28:30.282566 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
1201 13:28:30.286033 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1202 13:28:30.286117 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1203 13:28:30.292406 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1204 13:28:30.292506
1205 13:28:30.292562
1206 13:28:30.292610 ==
1207 13:28:30.295707 Dram Type= 6, Freq= 0, CH_0, rank 1
1208 13:28:30.299052 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1209 13:28:30.299135 ==
1210 13:28:30.299193
1211 13:28:30.299244
1212 13:28:30.302579 TX Vref Scan disable
1213 13:28:30.302656 == TX Byte 0 ==
1214 13:28:30.309380 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1215 13:28:30.312283 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1216 13:28:30.312374 == TX Byte 1 ==
1217 13:28:30.319321 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1218 13:28:30.322485 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1219 13:28:30.322560 ==
1220 13:28:30.325640 Dram Type= 6, Freq= 0, CH_0, rank 1
1221 13:28:30.329464 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1222 13:28:30.329538 ==
1223 13:28:30.342692 TX Vref=22, minBit 0, minWin=27, winSum=445
1224 13:28:30.345922 TX Vref=24, minBit 0, minWin=28, winSum=452
1225 13:28:30.349620 TX Vref=26, minBit 2, minWin=28, winSum=456
1226 13:28:30.352906 TX Vref=28, minBit 2, minWin=28, winSum=456
1227 13:28:30.356107 TX Vref=30, minBit 2, minWin=28, winSum=459
1228 13:28:30.359908 TX Vref=32, minBit 0, minWin=28, winSum=456
1229 13:28:30.366784 [TxChooseVref] Worse bit 2, Min win 28, Win sum 459, Final Vref 30
1230 13:28:30.366858
1231 13:28:30.370527 Final TX Range 1 Vref 30
1232 13:28:30.370615
1233 13:28:30.370666 ==
1234 13:28:30.373738 Dram Type= 6, Freq= 0, CH_0, rank 1
1235 13:28:30.377613 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1236 13:28:30.377709 ==
1237 13:28:30.377793
1238 13:28:30.377847
1239 13:28:30.381345 TX Vref Scan disable
1240 13:28:30.381419 == TX Byte 0 ==
1241 13:28:30.387666 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1242 13:28:30.391101 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1243 13:28:30.391175 == TX Byte 1 ==
1244 13:28:30.398045 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1245 13:28:30.401642 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1246 13:28:30.401715
1247 13:28:30.401768 [DATLAT]
1248 13:28:30.404945 Freq=800, CH0 RK1
1249 13:28:30.405020
1250 13:28:30.405073 DATLAT Default: 0x9
1251 13:28:30.408119 0, 0xFFFF, sum = 0
1252 13:28:30.408196 1, 0xFFFF, sum = 0
1253 13:28:30.411439 2, 0xFFFF, sum = 0
1254 13:28:30.411517 3, 0xFFFF, sum = 0
1255 13:28:30.414551 4, 0xFFFF, sum = 0
1256 13:28:30.414626 5, 0xFFFF, sum = 0
1257 13:28:30.418247 6, 0xFFFF, sum = 0
1258 13:28:30.418321 7, 0xFFFF, sum = 0
1259 13:28:30.421517 8, 0x0, sum = 1
1260 13:28:30.421591 9, 0x0, sum = 2
1261 13:28:30.424408 10, 0x0, sum = 3
1262 13:28:30.424498 11, 0x0, sum = 4
1263 13:28:30.427972 best_step = 9
1264 13:28:30.428050
1265 13:28:30.428106 ==
1266 13:28:30.431434 Dram Type= 6, Freq= 0, CH_0, rank 1
1267 13:28:30.434699 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1268 13:28:30.434773 ==
1269 13:28:30.434825 RX Vref Scan: 0
1270 13:28:30.437883
1271 13:28:30.437955 RX Vref 0 -> 0, step: 1
1272 13:28:30.438008
1273 13:28:30.441692 RX Delay -111 -> 252, step: 8
1274 13:28:30.448325 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1275 13:28:30.451219 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1276 13:28:30.454805 iDelay=217, Bit 2, Center 84 (-39 ~ 208) 248
1277 13:28:30.458301 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1278 13:28:30.461224 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1279 13:28:30.464574 iDelay=217, Bit 5, Center 72 (-47 ~ 192) 240
1280 13:28:30.471476 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1281 13:28:30.474752 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1282 13:28:30.477747 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1283 13:28:30.481177 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1284 13:28:30.484598 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1285 13:28:30.492056 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1286 13:28:30.494739 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1287 13:28:30.498182 iDelay=217, Bit 13, Center 80 (-39 ~ 200) 240
1288 13:28:30.501598 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1289 13:28:30.508008 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1290 13:28:30.508105 ==
1291 13:28:30.511109 Dram Type= 6, Freq= 0, CH_0, rank 1
1292 13:28:30.514885 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1293 13:28:30.514989 ==
1294 13:28:30.515047 DQS Delay:
1295 13:28:30.517857 DQS0 = 0, DQS1 = 0
1296 13:28:30.517956 DQM Delay:
1297 13:28:30.521541 DQM0 = 85, DQM1 = 73
1298 13:28:30.521667 DQ Delay:
1299 13:28:30.524654 DQ0 =80, DQ1 =88, DQ2 =84, DQ3 =80
1300 13:28:30.527847 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =96
1301 13:28:30.531101 DQ8 =60, DQ9 =60, DQ10 =72, DQ11 =64
1302 13:28:30.534548 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1303 13:28:30.534627
1304 13:28:30.534683
1305 13:28:30.541497 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e3e, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1306 13:28:30.544889 CH0 RK1: MR19=606, MR18=3E3E
1307 13:28:30.551112 CH0_RK1: MR19=0x606, MR18=0x3E3E, DQSOSC=394, MR23=63, INC=95, DEC=63
1308 13:28:30.554961 [RxdqsGatingPostProcess] freq 800
1309 13:28:30.561302 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1310 13:28:30.561390 Pre-setting of DQS Precalculation
1311 13:28:30.568023 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1312 13:28:30.568098 ==
1313 13:28:30.571290 Dram Type= 6, Freq= 0, CH_1, rank 0
1314 13:28:30.574401 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1315 13:28:30.574475 ==
1316 13:28:30.581277 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1317 13:28:30.588064 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1318 13:28:30.595322 [CA 0] Center 37 (6~68) winsize 63
1319 13:28:30.598910 [CA 1] Center 37 (6~68) winsize 63
1320 13:28:30.601921 [CA 2] Center 34 (4~65) winsize 62
1321 13:28:30.605412 [CA 3] Center 34 (4~64) winsize 61
1322 13:28:30.608748 [CA 4] Center 33 (3~64) winsize 62
1323 13:28:30.611959 [CA 5] Center 33 (3~64) winsize 62
1324 13:28:30.612033
1325 13:28:30.615285 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1326 13:28:30.615357
1327 13:28:30.618448 [CATrainingPosCal] consider 1 rank data
1328 13:28:30.621736 u2DelayCellTimex100 = 270/100 ps
1329 13:28:30.625015 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1330 13:28:30.631865 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1331 13:28:30.634825 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1332 13:28:30.638396 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1333 13:28:30.641532 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1334 13:28:30.645225 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1335 13:28:30.645298
1336 13:28:30.648388 CA PerBit enable=1, Macro0, CA PI delay=33
1337 13:28:30.648460
1338 13:28:30.651691 [CBTSetCACLKResult] CA Dly = 33
1339 13:28:30.651765 CS Dly: 4 (0~35)
1340 13:28:30.655075 ==
1341 13:28:30.658307 Dram Type= 6, Freq= 0, CH_1, rank 1
1342 13:28:30.661925 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1343 13:28:30.661999 ==
1344 13:28:30.665013 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1345 13:28:30.671467 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1346 13:28:30.681347 [CA 0] Center 36 (6~67) winsize 62
1347 13:28:30.684225 [CA 1] Center 36 (6~67) winsize 62
1348 13:28:30.688111 [CA 2] Center 34 (4~65) winsize 62
1349 13:28:30.691114 [CA 3] Center 34 (4~65) winsize 62
1350 13:28:30.694702 [CA 4] Center 33 (3~64) winsize 62
1351 13:28:30.697739 [CA 5] Center 33 (3~64) winsize 62
1352 13:28:30.697833
1353 13:28:30.701110 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1354 13:28:30.701184
1355 13:28:30.704464 [CATrainingPosCal] consider 2 rank data
1356 13:28:30.707502 u2DelayCellTimex100 = 270/100 ps
1357 13:28:30.711345 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1358 13:28:30.714624 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1359 13:28:30.721108 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1360 13:28:30.724588 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1361 13:28:30.727757 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1362 13:28:30.731129 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1363 13:28:30.731189
1364 13:28:30.734733 CA PerBit enable=1, Macro0, CA PI delay=33
1365 13:28:30.734789
1366 13:28:30.737922 [CBTSetCACLKResult] CA Dly = 33
1367 13:28:30.737977 CS Dly: 5 (0~37)
1368 13:28:30.738028
1369 13:28:30.741397 ----->DramcWriteLeveling(PI) begin...
1370 13:28:30.744234 ==
1371 13:28:30.747777 Dram Type= 6, Freq= 0, CH_1, rank 0
1372 13:28:30.751435 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1373 13:28:30.751493 ==
1374 13:28:30.754754 Write leveling (Byte 0): 22 => 22
1375 13:28:30.757600 Write leveling (Byte 1): 22 => 22
1376 13:28:30.761232 DramcWriteLeveling(PI) end<-----
1377 13:28:30.761294
1378 13:28:30.761345 ==
1379 13:28:30.764440 Dram Type= 6, Freq= 0, CH_1, rank 0
1380 13:28:30.767688 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1381 13:28:30.767742 ==
1382 13:28:30.771147 [Gating] SW mode calibration
1383 13:28:30.777565 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1384 13:28:30.781133 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1385 13:28:30.787720 0 6 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
1386 13:28:30.791344 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1387 13:28:30.794419 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1388 13:28:30.800984 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1389 13:28:30.804144 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1390 13:28:30.807735 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1391 13:28:30.814564 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1392 13:28:30.817546 0 6 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1393 13:28:30.821052 0 7 0 | B1->B0 | 2c2c 3e3e | 0 0 | (1 1) (0 0)
1394 13:28:30.827666 0 7 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1395 13:28:30.831028 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1396 13:28:30.834639 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1397 13:28:30.841485 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1398 13:28:30.844461 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1399 13:28:30.847969 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1400 13:28:30.851186 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1401 13:28:30.857980 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1402 13:28:30.861480 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1403 13:28:30.864684 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1404 13:28:30.871392 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1405 13:28:30.874303 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1406 13:28:30.878225 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1407 13:28:30.884534 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1408 13:28:30.887690 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1409 13:28:30.890976 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1410 13:28:30.897691 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1411 13:28:30.901387 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1412 13:28:30.904472 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1413 13:28:30.910986 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1414 13:28:30.914316 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1415 13:28:30.917779 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1416 13:28:30.924820 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1417 13:28:30.928096 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1418 13:28:30.931594 Total UI for P1: 0, mck2ui 16
1419 13:28:30.935070 best dqsien dly found for B0: ( 0, 9, 28)
1420 13:28:30.938247 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1421 13:28:30.941313 Total UI for P1: 0, mck2ui 16
1422 13:28:30.944725 best dqsien dly found for B1: ( 0, 9, 30)
1423 13:28:30.947890 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1424 13:28:30.951352 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1425 13:28:30.951432
1426 13:28:30.954629 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1427 13:28:30.961123 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1428 13:28:30.961211 [Gating] SW calibration Done
1429 13:28:30.961273 ==
1430 13:28:30.964795 Dram Type= 6, Freq= 0, CH_1, rank 0
1431 13:28:30.971120 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1432 13:28:30.971196 ==
1433 13:28:30.971250 RX Vref Scan: 0
1434 13:28:30.971299
1435 13:28:30.974575 RX Vref 0 -> 0, step: 1
1436 13:28:30.974651
1437 13:28:30.977888 RX Delay -130 -> 252, step: 16
1438 13:28:30.981815 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1439 13:28:30.984885 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1440 13:28:30.988305 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1441 13:28:30.994779 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1442 13:28:30.998074 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1443 13:28:31.001548 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1444 13:28:31.004793 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1445 13:28:31.008058 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1446 13:28:31.011841 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1447 13:28:31.017893 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1448 13:28:31.021468 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1449 13:28:31.024554 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1450 13:28:31.028685 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1451 13:28:31.031371 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1452 13:28:31.038368 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1453 13:28:31.042211 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1454 13:28:31.042299 ==
1455 13:28:31.045627 Dram Type= 6, Freq= 0, CH_1, rank 0
1456 13:28:31.049182 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1457 13:28:31.049260 ==
1458 13:28:31.049323 DQS Delay:
1459 13:28:31.052738 DQS0 = 0, DQS1 = 0
1460 13:28:31.052816 DQM Delay:
1461 13:28:31.056562 DQM0 = 80, DQM1 = 76
1462 13:28:31.056683 DQ Delay:
1463 13:28:31.060233 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1464 13:28:31.063590 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1465 13:28:31.063677 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
1466 13:28:31.070264 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1467 13:28:31.070344
1468 13:28:31.070414
1469 13:28:31.070475 ==
1470 13:28:31.073446 Dram Type= 6, Freq= 0, CH_1, rank 0
1471 13:28:31.077251 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1472 13:28:31.077316 ==
1473 13:28:31.077380
1474 13:28:31.077438
1475 13:28:31.080119 TX Vref Scan disable
1476 13:28:31.080175 == TX Byte 0 ==
1477 13:28:31.087188 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
1478 13:28:31.090729 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
1479 13:28:31.090843 == TX Byte 1 ==
1480 13:28:31.097185 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
1481 13:28:31.100740 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
1482 13:28:31.100826 ==
1483 13:28:31.104035 Dram Type= 6, Freq= 0, CH_1, rank 0
1484 13:28:31.106869 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1485 13:28:31.106960 ==
1486 13:28:31.120437 TX Vref=22, minBit 3, minWin=27, winSum=445
1487 13:28:31.123735 TX Vref=24, minBit 3, minWin=27, winSum=452
1488 13:28:31.127130 TX Vref=26, minBit 0, minWin=28, winSum=458
1489 13:28:31.130762 TX Vref=28, minBit 0, minWin=28, winSum=459
1490 13:28:31.133638 TX Vref=30, minBit 0, minWin=28, winSum=460
1491 13:28:31.140718 TX Vref=32, minBit 0, minWin=28, winSum=458
1492 13:28:31.143594 [TxChooseVref] Worse bit 0, Min win 28, Win sum 460, Final Vref 30
1493 13:28:31.143672
1494 13:28:31.147362 Final TX Range 1 Vref 30
1495 13:28:31.147450
1496 13:28:31.147523 ==
1497 13:28:31.150543 Dram Type= 6, Freq= 0, CH_1, rank 0
1498 13:28:31.153732 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1499 13:28:31.153810 ==
1500 13:28:31.153864
1501 13:28:31.156965
1502 13:28:31.157040 TX Vref Scan disable
1503 13:28:31.160325 == TX Byte 0 ==
1504 13:28:31.163830 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
1505 13:28:31.167052 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
1506 13:28:31.170912 == TX Byte 1 ==
1507 13:28:31.173454 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
1508 13:28:31.180808 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
1509 13:28:31.180897
1510 13:28:31.180963 [DATLAT]
1511 13:28:31.181021 Freq=800, CH1 RK0
1512 13:28:31.181084
1513 13:28:31.183554 DATLAT Default: 0xa
1514 13:28:31.183629 0, 0xFFFF, sum = 0
1515 13:28:31.187054 1, 0xFFFF, sum = 0
1516 13:28:31.187134 2, 0xFFFF, sum = 0
1517 13:28:31.190546 3, 0xFFFF, sum = 0
1518 13:28:31.190621 4, 0xFFFF, sum = 0
1519 13:28:31.193748 5, 0xFFFF, sum = 0
1520 13:28:31.196991 6, 0xFFFF, sum = 0
1521 13:28:31.197072 7, 0xFFFF, sum = 0
1522 13:28:31.197135 8, 0x0, sum = 1
1523 13:28:31.200192 9, 0x0, sum = 2
1524 13:28:31.200271 10, 0x0, sum = 3
1525 13:28:31.203687 11, 0x0, sum = 4
1526 13:28:31.203763 best_step = 9
1527 13:28:31.203817
1528 13:28:31.203864 ==
1529 13:28:31.206907 Dram Type= 6, Freq= 0, CH_1, rank 0
1530 13:28:31.213444 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1531 13:28:31.213520 ==
1532 13:28:31.213575 RX Vref Scan: 1
1533 13:28:31.213622
1534 13:28:31.216884 Set Vref Range= 32 -> 127
1535 13:28:31.216970
1536 13:28:31.220001 RX Vref 32 -> 127, step: 1
1537 13:28:31.220076
1538 13:28:31.223284 RX Delay -95 -> 252, step: 8
1539 13:28:31.223360
1540 13:28:31.226625 Set Vref, RX VrefLevel [Byte0]: 32
1541 13:28:31.230347 [Byte1]: 32
1542 13:28:31.230423
1543 13:28:31.233402 Set Vref, RX VrefLevel [Byte0]: 33
1544 13:28:31.236862 [Byte1]: 33
1545 13:28:31.236935
1546 13:28:31.239924 Set Vref, RX VrefLevel [Byte0]: 34
1547 13:28:31.243067 [Byte1]: 34
1548 13:28:31.243142
1549 13:28:31.246262 Set Vref, RX VrefLevel [Byte0]: 35
1550 13:28:31.249994 [Byte1]: 35
1551 13:28:31.253930
1552 13:28:31.254003 Set Vref, RX VrefLevel [Byte0]: 36
1553 13:28:31.257441 [Byte1]: 36
1554 13:28:31.261742
1555 13:28:31.261819 Set Vref, RX VrefLevel [Byte0]: 37
1556 13:28:31.264699 [Byte1]: 37
1557 13:28:31.269407
1558 13:28:31.269488 Set Vref, RX VrefLevel [Byte0]: 38
1559 13:28:31.272585 [Byte1]: 38
1560 13:28:31.276738
1561 13:28:31.276821 Set Vref, RX VrefLevel [Byte0]: 39
1562 13:28:31.279797 [Byte1]: 39
1563 13:28:31.284247
1564 13:28:31.284327 Set Vref, RX VrefLevel [Byte0]: 40
1565 13:28:31.287721 [Byte1]: 40
1566 13:28:31.291945
1567 13:28:31.292024 Set Vref, RX VrefLevel [Byte0]: 41
1568 13:28:31.295342 [Byte1]: 41
1569 13:28:31.299539
1570 13:28:31.299633 Set Vref, RX VrefLevel [Byte0]: 42
1571 13:28:31.303172 [Byte1]: 42
1572 13:28:31.307450
1573 13:28:31.307532 Set Vref, RX VrefLevel [Byte0]: 43
1574 13:28:31.310383 [Byte1]: 43
1575 13:28:31.314553
1576 13:28:31.314629 Set Vref, RX VrefLevel [Byte0]: 44
1577 13:28:31.318328 [Byte1]: 44
1578 13:28:31.322474
1579 13:28:31.322549 Set Vref, RX VrefLevel [Byte0]: 45
1580 13:28:31.325524 [Byte1]: 45
1581 13:28:31.330003
1582 13:28:31.330087 Set Vref, RX VrefLevel [Byte0]: 46
1583 13:28:31.333085 [Byte1]: 46
1584 13:28:31.337759
1585 13:28:31.337835 Set Vref, RX VrefLevel [Byte0]: 47
1586 13:28:31.340745 [Byte1]: 47
1587 13:28:31.345439
1588 13:28:31.345516 Set Vref, RX VrefLevel [Byte0]: 48
1589 13:28:31.348573 [Byte1]: 48
1590 13:28:31.352829
1591 13:28:31.352903 Set Vref, RX VrefLevel [Byte0]: 49
1592 13:28:31.355914 [Byte1]: 49
1593 13:28:31.360957
1594 13:28:31.361033 Set Vref, RX VrefLevel [Byte0]: 50
1595 13:28:31.363561 [Byte1]: 50
1596 13:28:31.368019
1597 13:28:31.368094 Set Vref, RX VrefLevel [Byte0]: 51
1598 13:28:31.371414 [Byte1]: 51
1599 13:28:31.375476
1600 13:28:31.375556 Set Vref, RX VrefLevel [Byte0]: 52
1601 13:28:31.381811 [Byte1]: 52
1602 13:28:31.381888
1603 13:28:31.385650 Set Vref, RX VrefLevel [Byte0]: 53
1604 13:28:31.388807 [Byte1]: 53
1605 13:28:31.388891
1606 13:28:31.392168 Set Vref, RX VrefLevel [Byte0]: 54
1607 13:28:31.395347 [Byte1]: 54
1608 13:28:31.395423
1609 13:28:31.398817 Set Vref, RX VrefLevel [Byte0]: 55
1610 13:28:31.401909 [Byte1]: 55
1611 13:28:31.406221
1612 13:28:31.406304 Set Vref, RX VrefLevel [Byte0]: 56
1613 13:28:31.409359 [Byte1]: 56
1614 13:28:31.413584
1615 13:28:31.413658 Set Vref, RX VrefLevel [Byte0]: 57
1616 13:28:31.416850 [Byte1]: 57
1617 13:28:31.421114
1618 13:28:31.421190 Set Vref, RX VrefLevel [Byte0]: 58
1619 13:28:31.424492 [Byte1]: 58
1620 13:28:31.428685
1621 13:28:31.428777 Set Vref, RX VrefLevel [Byte0]: 59
1622 13:28:31.431850 [Byte1]: 59
1623 13:28:31.436089
1624 13:28:31.436173 Set Vref, RX VrefLevel [Byte0]: 60
1625 13:28:31.439565 [Byte1]: 60
1626 13:28:31.443854
1627 13:28:31.443930 Set Vref, RX VrefLevel [Byte0]: 61
1628 13:28:31.447247 [Byte1]: 61
1629 13:28:31.451446
1630 13:28:31.451522 Set Vref, RX VrefLevel [Byte0]: 62
1631 13:28:31.454555 [Byte1]: 62
1632 13:28:31.458827
1633 13:28:31.458903 Set Vref, RX VrefLevel [Byte0]: 63
1634 13:28:31.462366 [Byte1]: 63
1635 13:28:31.467192
1636 13:28:31.467268 Set Vref, RX VrefLevel [Byte0]: 64
1637 13:28:31.470016 [Byte1]: 64
1638 13:28:31.474350
1639 13:28:31.474431 Set Vref, RX VrefLevel [Byte0]: 65
1640 13:28:31.477765 [Byte1]: 65
1641 13:28:31.482360
1642 13:28:31.482444 Set Vref, RX VrefLevel [Byte0]: 66
1643 13:28:31.485513 [Byte1]: 66
1644 13:28:31.489486
1645 13:28:31.489562 Set Vref, RX VrefLevel [Byte0]: 67
1646 13:28:31.492561 [Byte1]: 67
1647 13:28:31.497081
1648 13:28:31.497157 Set Vref, RX VrefLevel [Byte0]: 68
1649 13:28:31.500286 [Byte1]: 68
1650 13:28:31.504619
1651 13:28:31.504700 Set Vref, RX VrefLevel [Byte0]: 69
1652 13:28:31.507743 [Byte1]: 69
1653 13:28:31.512078
1654 13:28:31.512155 Set Vref, RX VrefLevel [Byte0]: 70
1655 13:28:31.515539 [Byte1]: 70
1656 13:28:31.519780
1657 13:28:31.519856 Set Vref, RX VrefLevel [Byte0]: 71
1658 13:28:31.523145 [Byte1]: 71
1659 13:28:31.527727
1660 13:28:31.527813 Set Vref, RX VrefLevel [Byte0]: 72
1661 13:28:31.531364 [Byte1]: 72
1662 13:28:31.535327
1663 13:28:31.535416 Set Vref, RX VrefLevel [Byte0]: 73
1664 13:28:31.538229 [Byte1]: 73
1665 13:28:31.542494
1666 13:28:31.542570 Set Vref, RX VrefLevel [Byte0]: 74
1667 13:28:31.545977 [Byte1]: 74
1668 13:28:31.550324
1669 13:28:31.550407 Set Vref, RX VrefLevel [Byte0]: 75
1670 13:28:31.553422 [Byte1]: 75
1671 13:28:31.557794
1672 13:28:31.557868 Final RX Vref Byte 0 = 59 to rank0
1673 13:28:31.561295 Final RX Vref Byte 1 = 53 to rank0
1674 13:28:31.564546 Final RX Vref Byte 0 = 59 to rank1
1675 13:28:31.567965 Final RX Vref Byte 1 = 53 to rank1==
1676 13:28:31.571210 Dram Type= 6, Freq= 0, CH_1, rank 0
1677 13:28:31.574706 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1678 13:28:31.577950 ==
1679 13:28:31.578030 DQS Delay:
1680 13:28:31.578103 DQS0 = 0, DQS1 = 0
1681 13:28:31.581373 DQM Delay:
1682 13:28:31.581448 DQM0 = 81, DQM1 = 75
1683 13:28:31.584447 DQ Delay:
1684 13:28:31.588091 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1685 13:28:31.588174 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
1686 13:28:31.591114 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
1687 13:28:31.594630 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1688 13:28:31.598520
1689 13:28:31.598595
1690 13:28:31.604652 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a4a, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
1691 13:28:31.608558 CH1 RK0: MR19=606, MR18=4A4A
1692 13:28:31.611961 CH1_RK0: MR19=0x606, MR18=0x4A4A, DQSOSC=391, MR23=63, INC=96, DEC=64
1693 13:28:31.612038
1694 13:28:31.615737 ----->DramcWriteLeveling(PI) begin...
1695 13:28:31.619210 ==
1696 13:28:31.619289 Dram Type= 6, Freq= 0, CH_1, rank 1
1697 13:28:31.625392 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1698 13:28:31.625536 ==
1699 13:28:31.629123 Write leveling (Byte 0): 24 => 24
1700 13:28:31.631925 Write leveling (Byte 1): 24 => 24
1701 13:28:31.632017 DramcWriteLeveling(PI) end<-----
1702 13:28:31.635592
1703 13:28:31.635663 ==
1704 13:28:31.638745 Dram Type= 6, Freq= 0, CH_1, rank 1
1705 13:28:31.642167 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1706 13:28:31.642292 ==
1707 13:28:31.645555 [Gating] SW mode calibration
1708 13:28:31.652191 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1709 13:28:31.655329 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1710 13:28:31.661860 0 6 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (1 0)
1711 13:28:31.665223 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1712 13:28:31.668542 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1713 13:28:31.675351 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1714 13:28:31.678559 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1715 13:28:31.681929 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1716 13:28:31.688741 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1717 13:28:31.692349 0 6 28 | B1->B0 | 2525 2525 | 0 1 | (0 0) (0 0)
1718 13:28:31.695312 0 7 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1719 13:28:31.702192 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1720 13:28:31.705277 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1721 13:28:31.708934 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1722 13:28:31.715147 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1723 13:28:31.718955 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1724 13:28:31.722019 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1725 13:28:31.725540 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1726 13:28:31.732256 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1727 13:28:31.735287 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1728 13:28:31.738603 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1729 13:28:31.745447 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1730 13:28:31.748592 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1731 13:28:31.751905 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1732 13:28:31.758793 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1733 13:28:31.761955 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1734 13:28:31.765403 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1735 13:28:31.772004 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1736 13:28:31.775332 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1737 13:28:31.778637 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1738 13:28:31.785346 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1739 13:28:31.788737 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1740 13:28:31.791911 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1741 13:28:31.798569 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1742 13:28:31.798647 Total UI for P1: 0, mck2ui 16
1743 13:28:31.805452 best dqsien dly found for B0: ( 0, 9, 26)
1744 13:28:31.808802 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1745 13:28:31.812035 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1746 13:28:31.815302 Total UI for P1: 0, mck2ui 16
1747 13:28:31.818502 best dqsien dly found for B1: ( 0, 9, 30)
1748 13:28:31.822126 best DQS0 dly(MCK, UI, PI) = (0, 9, 26)
1749 13:28:31.825434 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1750 13:28:31.825511
1751 13:28:31.828452 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 26)
1752 13:28:31.835348 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1753 13:28:31.835427 [Gating] SW calibration Done
1754 13:28:31.838546 ==
1755 13:28:31.838624 Dram Type= 6, Freq= 0, CH_1, rank 1
1756 13:28:31.845260 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1757 13:28:31.845337 ==
1758 13:28:31.845407 RX Vref Scan: 0
1759 13:28:31.845469
1760 13:28:31.848616 RX Vref 0 -> 0, step: 1
1761 13:28:31.848691
1762 13:28:31.851739 RX Delay -130 -> 252, step: 16
1763 13:28:31.855053 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1764 13:28:31.858322 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1765 13:28:31.861825 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1766 13:28:31.868840 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1767 13:28:31.871894 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1768 13:28:31.875023 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1769 13:28:31.878419 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1770 13:28:31.882101 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1771 13:28:31.888542 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1772 13:28:31.891995 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1773 13:28:31.895625 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1774 13:28:31.898245 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1775 13:28:31.901684 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1776 13:28:31.908541 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1777 13:28:31.911672 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1778 13:28:31.914933 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1779 13:28:31.915009 ==
1780 13:28:31.918477 Dram Type= 6, Freq= 0, CH_1, rank 1
1781 13:28:31.921603 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1782 13:28:31.925504 ==
1783 13:28:31.925580 DQS Delay:
1784 13:28:31.925649 DQS0 = 0, DQS1 = 0
1785 13:28:31.928322 DQM Delay:
1786 13:28:31.928400 DQM0 = 85, DQM1 = 74
1787 13:28:31.931578 DQ Delay:
1788 13:28:31.931636 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1789 13:28:31.934804 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1790 13:28:31.938274 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =69
1791 13:28:31.941708 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1792 13:28:31.941785
1793 13:28:31.945176
1794 13:28:31.945252 ==
1795 13:28:31.948718 Dram Type= 6, Freq= 0, CH_1, rank 1
1796 13:28:31.951994 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1797 13:28:31.952071 ==
1798 13:28:31.952140
1799 13:28:31.952201
1800 13:28:31.955165 TX Vref Scan disable
1801 13:28:31.955240 == TX Byte 0 ==
1802 13:28:31.961982 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1803 13:28:31.965270 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1804 13:28:31.965348 == TX Byte 1 ==
1805 13:28:31.971625 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1806 13:28:31.974772 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1807 13:28:31.974855 ==
1808 13:28:31.978374 Dram Type= 6, Freq= 0, CH_1, rank 1
1809 13:28:31.981712 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1810 13:28:31.981788 ==
1811 13:28:31.995076 TX Vref=22, minBit 4, minWin=27, winSum=449
1812 13:28:31.998427 TX Vref=24, minBit 8, minWin=27, winSum=452
1813 13:28:32.001509 TX Vref=26, minBit 0, minWin=28, winSum=459
1814 13:28:32.004685 TX Vref=28, minBit 9, minWin=27, winSum=458
1815 13:28:32.008125 TX Vref=30, minBit 9, minWin=28, winSum=459
1816 13:28:32.011327 TX Vref=32, minBit 9, minWin=27, winSum=454
1817 13:28:32.018183 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 26
1818 13:28:32.018259
1819 13:28:32.021650 Final TX Range 1 Vref 26
1820 13:28:32.021730
1821 13:28:32.021803 ==
1822 13:28:32.024826 Dram Type= 6, Freq= 0, CH_1, rank 1
1823 13:28:32.028188 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1824 13:28:32.028280 ==
1825 13:28:32.028365
1826 13:28:32.031395
1827 13:28:32.031471 TX Vref Scan disable
1828 13:28:32.034885 == TX Byte 0 ==
1829 13:28:32.038385 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1830 13:28:32.041942 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1831 13:28:32.044826 == TX Byte 1 ==
1832 13:28:32.048137 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1833 13:28:32.051517 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1834 13:28:32.051594
1835 13:28:32.054752 [DATLAT]
1836 13:28:32.054828 Freq=800, CH1 RK1
1837 13:28:32.054900
1838 13:28:32.058040 DATLAT Default: 0x9
1839 13:28:32.058117 0, 0xFFFF, sum = 0
1840 13:28:32.061308 1, 0xFFFF, sum = 0
1841 13:28:32.061385 2, 0xFFFF, sum = 0
1842 13:28:32.064648 3, 0xFFFF, sum = 0
1843 13:28:32.064727 4, 0xFFFF, sum = 0
1844 13:28:32.068203 5, 0xFFFF, sum = 0
1845 13:28:32.068287 6, 0xFFFF, sum = 0
1846 13:28:32.071610 7, 0xFFFF, sum = 0
1847 13:28:32.071688 8, 0x0, sum = 1
1848 13:28:32.074804 9, 0x0, sum = 2
1849 13:28:32.074881 10, 0x0, sum = 3
1850 13:28:32.078375 11, 0x0, sum = 4
1851 13:28:32.078486 best_step = 9
1852 13:28:32.078585
1853 13:28:32.078673 ==
1854 13:28:32.081551 Dram Type= 6, Freq= 0, CH_1, rank 1
1855 13:28:32.088548 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1856 13:28:32.088634 ==
1857 13:28:32.088711 RX Vref Scan: 0
1858 13:28:32.088773
1859 13:28:32.091363 RX Vref 0 -> 0, step: 1
1860 13:28:32.091439
1861 13:28:32.094695 RX Delay -111 -> 252, step: 8
1862 13:28:32.098119 iDelay=217, Bit 0, Center 88 (-23 ~ 200) 224
1863 13:28:32.101431 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1864 13:28:32.108184 iDelay=217, Bit 2, Center 72 (-47 ~ 192) 240
1865 13:28:32.111416 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1866 13:28:32.114735 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1867 13:28:32.118464 iDelay=217, Bit 5, Center 100 (-15 ~ 216) 232
1868 13:28:32.121499 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1869 13:28:32.125196 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1870 13:28:32.131952 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1871 13:28:32.135144 iDelay=217, Bit 9, Center 64 (-55 ~ 184) 240
1872 13:28:32.138224 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1873 13:28:32.141962 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1874 13:28:32.148118 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1875 13:28:32.151387 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1876 13:28:32.154782 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1877 13:28:32.158397 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1878 13:28:32.158472 ==
1879 13:28:32.161757 Dram Type= 6, Freq= 0, CH_1, rank 1
1880 13:28:32.164882 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1881 13:28:32.168061 ==
1882 13:28:32.168138 DQS Delay:
1883 13:28:32.168209 DQS0 = 0, DQS1 = 0
1884 13:28:32.171969 DQM Delay:
1885 13:28:32.172046 DQM0 = 84, DQM1 = 74
1886 13:28:32.174843 DQ Delay:
1887 13:28:32.174919 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =84
1888 13:28:32.178419 DQ4 =84, DQ5 =100, DQ6 =92, DQ7 =80
1889 13:28:32.181330 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1890 13:28:32.184767 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1891 13:28:32.184855
1892 13:28:32.188305
1893 13:28:32.195495 [DQSOSCAuto] RK1, (LSB)MR18= 0x3636, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1894 13:28:32.198301 CH1 RK1: MR19=606, MR18=3636
1895 13:28:32.205084 CH1_RK1: MR19=0x606, MR18=0x3636, DQSOSC=396, MR23=63, INC=94, DEC=62
1896 13:28:32.205163 [RxdqsGatingPostProcess] freq 800
1897 13:28:32.211900 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1898 13:28:32.214901 Pre-setting of DQS Precalculation
1899 13:28:32.218417 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1900 13:28:32.228652 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1901 13:28:32.234773 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1902 13:28:32.234852
1903 13:28:32.234922
1904 13:28:32.238337 [Calibration Summary] 1600 Mbps
1905 13:28:32.238414 CH 0, Rank 0
1906 13:28:32.242195 SW Impedance : PASS
1907 13:28:32.242272 DUTY Scan : NO K
1908 13:28:32.244853 ZQ Calibration : PASS
1909 13:28:32.248688 Jitter Meter : NO K
1910 13:28:32.248764 CBT Training : PASS
1911 13:28:32.251493 Write leveling : PASS
1912 13:28:32.254626 RX DQS gating : PASS
1913 13:28:32.254702 RX DQ/DQS(RDDQC) : PASS
1914 13:28:32.258216 TX DQ/DQS : PASS
1915 13:28:32.261475 RX DATLAT : PASS
1916 13:28:32.261554 RX DQ/DQS(Engine): PASS
1917 13:28:32.264773 TX OE : NO K
1918 13:28:32.264888 All Pass.
1919 13:28:32.264960
1920 13:28:32.268041 CH 0, Rank 1
1921 13:28:32.268120 SW Impedance : PASS
1922 13:28:32.271737 DUTY Scan : NO K
1923 13:28:32.271811 ZQ Calibration : PASS
1924 13:28:32.275140 Jitter Meter : NO K
1925 13:28:32.278540 CBT Training : PASS
1926 13:28:32.278625 Write leveling : PASS
1927 13:28:32.281546 RX DQS gating : PASS
1928 13:28:32.284721 RX DQ/DQS(RDDQC) : PASS
1929 13:28:32.284795 TX DQ/DQS : PASS
1930 13:28:32.288220 RX DATLAT : PASS
1931 13:28:32.291623 RX DQ/DQS(Engine): PASS
1932 13:28:32.291696 TX OE : NO K
1933 13:28:32.294825 All Pass.
1934 13:28:32.294897
1935 13:28:32.294965 CH 1, Rank 0
1936 13:28:32.298066 SW Impedance : PASS
1937 13:28:32.298150 DUTY Scan : NO K
1938 13:28:32.301595 ZQ Calibration : PASS
1939 13:28:32.305060 Jitter Meter : NO K
1940 13:28:32.305133 CBT Training : PASS
1941 13:28:32.308522 Write leveling : PASS
1942 13:28:32.311462 RX DQS gating : PASS
1943 13:28:32.311534 RX DQ/DQS(RDDQC) : PASS
1944 13:28:32.314973 TX DQ/DQS : PASS
1945 13:28:32.315048 RX DATLAT : PASS
1946 13:28:32.318047 RX DQ/DQS(Engine): PASS
1947 13:28:32.321442 TX OE : NO K
1948 13:28:32.321519 All Pass.
1949 13:28:32.321573
1950 13:28:32.321622 CH 1, Rank 1
1951 13:28:32.324898 SW Impedance : PASS
1952 13:28:32.328683 DUTY Scan : NO K
1953 13:28:32.328770 ZQ Calibration : PASS
1954 13:28:32.331814 Jitter Meter : NO K
1955 13:28:32.334765 CBT Training : PASS
1956 13:28:32.334839 Write leveling : PASS
1957 13:28:32.338378 RX DQS gating : PASS
1958 13:28:32.341884 RX DQ/DQS(RDDQC) : PASS
1959 13:28:32.341958 TX DQ/DQS : PASS
1960 13:28:32.344892 RX DATLAT : PASS
1961 13:28:32.347886 RX DQ/DQS(Engine): PASS
1962 13:28:32.347960 TX OE : NO K
1963 13:28:32.351484 All Pass.
1964 13:28:32.351558
1965 13:28:32.351610 DramC Write-DBI off
1966 13:28:32.355167 PER_BANK_REFRESH: Hybrid Mode
1967 13:28:32.355249 TX_TRACKING: ON
1968 13:28:32.358237 [GetDramInforAfterCalByMRR] Vendor 6.
1969 13:28:32.361376 [GetDramInforAfterCalByMRR] Revision 606.
1970 13:28:32.367981 [GetDramInforAfterCalByMRR] Revision 2 0.
1971 13:28:32.368056 MR0 0x3939
1972 13:28:32.368108 MR8 0x1111
1973 13:28:32.371597 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1974 13:28:32.371672
1975 13:28:32.374984 MR0 0x3939
1976 13:28:32.375059 MR8 0x1111
1977 13:28:32.378277 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1978 13:28:32.378356
1979 13:28:32.387977 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1980 13:28:32.391825 [FAST_K] Save calibration result to emmc
1981 13:28:32.395110 [FAST_K] Save calibration result to emmc
1982 13:28:32.398168 dram_init: config_dvfs: 1
1983 13:28:32.401527 dramc_set_vcore_voltage set vcore to 662500
1984 13:28:32.405051 Read voltage for 1200, 2
1985 13:28:32.405126 Vio18 = 0
1986 13:28:32.405180 Vcore = 662500
1987 13:28:32.405226 Vdram = 0
1988 13:28:32.407910 Vddq = 0
1989 13:28:32.407983 Vmddr = 0
1990 13:28:32.414804 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1991 13:28:32.418165 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1992 13:28:32.421495 MEM_TYPE=3, freq_sel=15
1993 13:28:32.424762 sv_algorithm_assistance_LP4_1600
1994 13:28:32.428665 ============ PULL DRAM RESETB DOWN ============
1995 13:28:32.431578 ========== PULL DRAM RESETB DOWN end =========
1996 13:28:32.438243 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1997 13:28:32.441640 ===================================
1998 13:28:32.441714 LPDDR4 DRAM CONFIGURATION
1999 13:28:32.444884 ===================================
2000 13:28:32.447970 EX_ROW_EN[0] = 0x0
2001 13:28:32.448043 EX_ROW_EN[1] = 0x0
2002 13:28:32.451376 LP4Y_EN = 0x0
2003 13:28:32.451450 WORK_FSP = 0x0
2004 13:28:32.454771 WL = 0x4
2005 13:28:32.458401 RL = 0x4
2006 13:28:32.458474 BL = 0x2
2007 13:28:32.461647 RPST = 0x0
2008 13:28:32.461722 RD_PRE = 0x0
2009 13:28:32.464969 WR_PRE = 0x1
2010 13:28:32.465049 WR_PST = 0x0
2011 13:28:32.468450 DBI_WR = 0x0
2012 13:28:32.468523 DBI_RD = 0x0
2013 13:28:32.471306 OTF = 0x1
2014 13:28:32.474542 ===================================
2015 13:28:32.478345 ===================================
2016 13:28:32.478427 ANA top config
2017 13:28:32.481369 ===================================
2018 13:28:32.484801 DLL_ASYNC_EN = 0
2019 13:28:32.488613 ALL_SLAVE_EN = 0
2020 13:28:32.488686 NEW_RANK_MODE = 1
2021 13:28:32.491962 DLL_IDLE_MODE = 1
2022 13:28:32.494836 LP45_APHY_COMB_EN = 1
2023 13:28:32.498199 TX_ODT_DIS = 1
2024 13:28:32.498282 NEW_8X_MODE = 1
2025 13:28:32.501655 ===================================
2026 13:28:32.504843 ===================================
2027 13:28:32.508127 data_rate = 2400
2028 13:28:32.511462 CKR = 1
2029 13:28:32.514685 DQ_P2S_RATIO = 8
2030 13:28:32.518065 ===================================
2031 13:28:32.521415 CA_P2S_RATIO = 8
2032 13:28:32.524911 DQ_CA_OPEN = 0
2033 13:28:32.524985 DQ_SEMI_OPEN = 0
2034 13:28:32.528678 CA_SEMI_OPEN = 0
2035 13:28:32.531252 CA_FULL_RATE = 0
2036 13:28:32.534895 DQ_CKDIV4_EN = 0
2037 13:28:32.537844 CA_CKDIV4_EN = 0
2038 13:28:32.541416 CA_PREDIV_EN = 0
2039 13:28:32.541490 PH8_DLY = 17
2040 13:28:32.544927 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2041 13:28:32.547985 DQ_AAMCK_DIV = 4
2042 13:28:32.551514 CA_AAMCK_DIV = 4
2043 13:28:32.554848 CA_ADMCK_DIV = 4
2044 13:28:32.557915 DQ_TRACK_CA_EN = 0
2045 13:28:32.561399 CA_PICK = 1200
2046 13:28:32.561473 CA_MCKIO = 1200
2047 13:28:32.564781 MCKIO_SEMI = 0
2048 13:28:32.568028 PLL_FREQ = 2366
2049 13:28:32.571099 DQ_UI_PI_RATIO = 32
2050 13:28:32.574802 CA_UI_PI_RATIO = 0
2051 13:28:32.578206 ===================================
2052 13:28:32.581397 ===================================
2053 13:28:32.584830 memory_type:LPDDR4
2054 13:28:32.584905 GP_NUM : 10
2055 13:28:32.587683 SRAM_EN : 1
2056 13:28:32.587757 MD32_EN : 0
2057 13:28:32.591586 ===================================
2058 13:28:32.594845 [ANA_INIT] >>>>>>>>>>>>>>
2059 13:28:32.597893 <<<<<< [CONFIGURE PHASE]: ANA_TX
2060 13:28:32.601681 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2061 13:28:32.604349 ===================================
2062 13:28:32.608010 data_rate = 2400,PCW = 0X5b00
2063 13:28:32.611244 ===================================
2064 13:28:32.614782 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2065 13:28:32.617838 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2066 13:28:32.624930 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2067 13:28:32.627920 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2068 13:28:32.634768 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2069 13:28:32.637957 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2070 13:28:32.638037 [ANA_INIT] flow start
2071 13:28:32.641213 [ANA_INIT] PLL >>>>>>>>
2072 13:28:32.644346 [ANA_INIT] PLL <<<<<<<<
2073 13:28:32.644434 [ANA_INIT] MIDPI >>>>>>>>
2074 13:28:32.648009 [ANA_INIT] MIDPI <<<<<<<<
2075 13:28:32.651237 [ANA_INIT] DLL >>>>>>>>
2076 13:28:32.651324 [ANA_INIT] DLL <<<<<<<<
2077 13:28:32.654453 [ANA_INIT] flow end
2078 13:28:32.657759 ============ LP4 DIFF to SE enter ============
2079 13:28:32.661173 ============ LP4 DIFF to SE exit ============
2080 13:28:32.664578 [ANA_INIT] <<<<<<<<<<<<<
2081 13:28:32.667641 [Flow] Enable top DCM control >>>>>
2082 13:28:32.671232 [Flow] Enable top DCM control <<<<<
2083 13:28:32.674692 Enable DLL master slave shuffle
2084 13:28:32.681007 ==============================================================
2085 13:28:32.681082 Gating Mode config
2086 13:28:32.687855 ==============================================================
2087 13:28:32.687929 Config description:
2088 13:28:32.697588 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2089 13:28:32.704119 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2090 13:28:32.710805 SELPH_MODE 0: By rank 1: By Phase
2091 13:28:32.714026 ==============================================================
2092 13:28:32.717410 GAT_TRACK_EN = 1
2093 13:28:32.720879 RX_GATING_MODE = 2
2094 13:28:32.724025 RX_GATING_TRACK_MODE = 2
2095 13:28:32.727363 SELPH_MODE = 1
2096 13:28:32.730762 PICG_EARLY_EN = 1
2097 13:28:32.734162 VALID_LAT_VALUE = 1
2098 13:28:32.740767 ==============================================================
2099 13:28:32.744307 Enter into Gating configuration >>>>
2100 13:28:32.747139 Exit from Gating configuration <<<<
2101 13:28:32.750821 Enter into DVFS_PRE_config >>>>>
2102 13:28:32.760516 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2103 13:28:32.764052 Exit from DVFS_PRE_config <<<<<
2104 13:28:32.766873 Enter into PICG configuration >>>>
2105 13:28:32.770816 Exit from PICG configuration <<<<
2106 13:28:32.773782 [RX_INPUT] configuration >>>>>
2107 13:28:32.773857 [RX_INPUT] configuration <<<<<
2108 13:28:32.780730 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2109 13:28:32.787010 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2110 13:28:32.790628 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2111 13:28:32.797441 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2112 13:28:32.803777 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2113 13:28:32.810783 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2114 13:28:32.814006 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2115 13:28:32.816979 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2116 13:28:32.823678 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2117 13:28:32.827006 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2118 13:28:32.830816 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2119 13:28:32.834196 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2120 13:28:32.837228 ===================================
2121 13:28:32.840436 LPDDR4 DRAM CONFIGURATION
2122 13:28:32.843835 ===================================
2123 13:28:32.846976 EX_ROW_EN[0] = 0x0
2124 13:28:32.847051 EX_ROW_EN[1] = 0x0
2125 13:28:32.850677 LP4Y_EN = 0x0
2126 13:28:32.850766 WORK_FSP = 0x0
2127 13:28:32.853814 WL = 0x4
2128 13:28:32.853889 RL = 0x4
2129 13:28:32.857448 BL = 0x2
2130 13:28:32.857523 RPST = 0x0
2131 13:28:32.860798 RD_PRE = 0x0
2132 13:28:32.860872 WR_PRE = 0x1
2133 13:28:32.863698 WR_PST = 0x0
2134 13:28:32.863776 DBI_WR = 0x0
2135 13:28:32.867351 DBI_RD = 0x0
2136 13:28:32.867426 OTF = 0x1
2137 13:28:32.870549 ===================================
2138 13:28:32.877222 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2139 13:28:32.880207 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2140 13:28:32.883488 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2141 13:28:32.887280 ===================================
2142 13:28:32.890640 LPDDR4 DRAM CONFIGURATION
2143 13:28:32.893731 ===================================
2144 13:28:32.896990 EX_ROW_EN[0] = 0x10
2145 13:28:32.897085 EX_ROW_EN[1] = 0x0
2146 13:28:32.900649 LP4Y_EN = 0x0
2147 13:28:32.900727 WORK_FSP = 0x0
2148 13:28:32.903747 WL = 0x4
2149 13:28:32.903815 RL = 0x4
2150 13:28:32.906889 BL = 0x2
2151 13:28:32.906946 RPST = 0x0
2152 13:28:32.910882 RD_PRE = 0x0
2153 13:28:32.910964 WR_PRE = 0x1
2154 13:28:32.913723 WR_PST = 0x0
2155 13:28:32.913799 DBI_WR = 0x0
2156 13:28:32.917084 DBI_RD = 0x0
2157 13:28:32.917159 OTF = 0x1
2158 13:28:32.920577 ===================================
2159 13:28:32.927221 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2160 13:28:32.927299 ==
2161 13:28:32.930607 Dram Type= 6, Freq= 0, CH_0, rank 0
2162 13:28:32.933908 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2163 13:28:32.937270 ==
2164 13:28:32.937344 [Duty_Offset_Calibration]
2165 13:28:32.940238 B0:0 B1:2 CA:1
2166 13:28:32.940322
2167 13:28:32.943721 [DutyScan_Calibration_Flow] k_type=0
2168 13:28:32.952250
2169 13:28:32.952332 ==CLK 0==
2170 13:28:32.955641 Final CLK duty delay cell = 0
2171 13:28:32.959259 [0] MAX Duty = 5093%(X100), DQS PI = 12
2172 13:28:32.962253 [0] MIN Duty = 4938%(X100), DQS PI = 52
2173 13:28:32.962330 [0] AVG Duty = 5015%(X100)
2174 13:28:32.965822
2175 13:28:32.969199 CH0 CLK Duty spec in!! Max-Min= 155%
2176 13:28:32.972464 [DutyScan_Calibration_Flow] ====Done====
2177 13:28:32.972539
2178 13:28:32.975491 [DutyScan_Calibration_Flow] k_type=1
2179 13:28:32.991432
2180 13:28:32.991510 ==DQS 0 ==
2181 13:28:32.995094 Final DQS duty delay cell = 0
2182 13:28:32.998411 [0] MAX Duty = 5125%(X100), DQS PI = 30
2183 13:28:33.001373 [0] MIN Duty = 5031%(X100), DQS PI = 4
2184 13:28:33.001463 [0] AVG Duty = 5078%(X100)
2185 13:28:33.005214
2186 13:28:33.005296 ==DQS 1 ==
2187 13:28:33.008319 Final DQS duty delay cell = 0
2188 13:28:33.011515 [0] MAX Duty = 5031%(X100), DQS PI = 54
2189 13:28:33.014879 [0] MIN Duty = 4906%(X100), DQS PI = 18
2190 13:28:33.018501 [0] AVG Duty = 4968%(X100)
2191 13:28:33.018576
2192 13:28:33.021457 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2193 13:28:33.021532
2194 13:28:33.024996 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2195 13:28:33.028399 [DutyScan_Calibration_Flow] ====Done====
2196 13:28:33.028477
2197 13:28:33.031281 [DutyScan_Calibration_Flow] k_type=3
2198 13:28:33.048994
2199 13:28:33.049076 ==DQM 0 ==
2200 13:28:33.051770 Final DQM duty delay cell = 0
2201 13:28:33.055550 [0] MAX Duty = 5124%(X100), DQS PI = 20
2202 13:28:33.058804 [0] MIN Duty = 4969%(X100), DQS PI = 42
2203 13:28:33.062229 [0] AVG Duty = 5046%(X100)
2204 13:28:33.062304
2205 13:28:33.062358 ==DQM 1 ==
2206 13:28:33.065810 Final DQM duty delay cell = 4
2207 13:28:33.068964 [4] MAX Duty = 5187%(X100), DQS PI = 54
2208 13:28:33.072099 [4] MIN Duty = 5000%(X100), DQS PI = 18
2209 13:28:33.075334 [4] AVG Duty = 5093%(X100)
2210 13:28:33.075407
2211 13:28:33.078623 CH0 DQM 0 Duty spec in!! Max-Min= 155%
2212 13:28:33.078702
2213 13:28:33.082192 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2214 13:28:33.085271 [DutyScan_Calibration_Flow] ====Done====
2215 13:28:33.085346
2216 13:28:33.088711 [DutyScan_Calibration_Flow] k_type=2
2217 13:28:33.103987
2218 13:28:33.104434 ==DQ 0 ==
2219 13:28:33.107453 Final DQ duty delay cell = -4
2220 13:28:33.110639 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2221 13:28:33.114083 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2222 13:28:33.117323 [-4] AVG Duty = 4937%(X100)
2223 13:28:33.117666
2224 13:28:33.117913 ==DQ 1 ==
2225 13:28:33.121455 Final DQ duty delay cell = -4
2226 13:28:33.123912 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2227 13:28:33.127289 [-4] MIN Duty = 4876%(X100), DQS PI = 62
2228 13:28:33.130438 [-4] AVG Duty = 4969%(X100)
2229 13:28:33.130782
2230 13:28:33.134314 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2231 13:28:33.134738
2232 13:28:33.137082 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2233 13:28:33.140663 [DutyScan_Calibration_Flow] ====Done====
2234 13:28:33.141007 ==
2235 13:28:33.144115 Dram Type= 6, Freq= 0, CH_1, rank 0
2236 13:28:33.147108 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2237 13:28:33.147561 ==
2238 13:28:33.151011 [Duty_Offset_Calibration]
2239 13:28:33.151445 B0:0 B1:4 CA:-5
2240 13:28:33.151718
2241 13:28:33.154270 [DutyScan_Calibration_Flow] k_type=0
2242 13:28:33.164992
2243 13:28:33.165451 ==CLK 0==
2244 13:28:33.168377 Final CLK duty delay cell = 0
2245 13:28:33.171443 [0] MAX Duty = 5094%(X100), DQS PI = 24
2246 13:28:33.175196 [0] MIN Duty = 4875%(X100), DQS PI = 46
2247 13:28:33.175666 [0] AVG Duty = 4984%(X100)
2248 13:28:33.178158
2249 13:28:33.178545 CH1 CLK Duty spec in!! Max-Min= 219%
2250 13:28:33.185015 [DutyScan_Calibration_Flow] ====Done====
2251 13:28:33.185414
2252 13:28:33.188299 [DutyScan_Calibration_Flow] k_type=1
2253 13:28:33.203399
2254 13:28:33.203849 ==DQS 0 ==
2255 13:28:33.207073 Final DQS duty delay cell = 0
2256 13:28:33.210056 [0] MAX Duty = 5125%(X100), DQS PI = 16
2257 13:28:33.213673 [0] MIN Duty = 4875%(X100), DQS PI = 40
2258 13:28:33.216887 [0] AVG Duty = 5000%(X100)
2259 13:28:33.217373
2260 13:28:33.217642 ==DQS 1 ==
2261 13:28:33.219783 Final DQS duty delay cell = -4
2262 13:28:33.223378 [-4] MAX Duty = 5000%(X100), DQS PI = 4
2263 13:28:33.226631 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2264 13:28:33.229960 [-4] AVG Duty = 4953%(X100)
2265 13:28:33.230361
2266 13:28:33.232762 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2267 13:28:33.233178
2268 13:28:33.236172 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2269 13:28:33.239883 [DutyScan_Calibration_Flow] ====Done====
2270 13:28:33.240421
2271 13:28:33.243377 [DutyScan_Calibration_Flow] k_type=3
2272 13:28:33.258578
2273 13:28:33.259061 ==DQM 0 ==
2274 13:28:33.261758 Final DQM duty delay cell = -4
2275 13:28:33.265179 [-4] MAX Duty = 5093%(X100), DQS PI = 32
2276 13:28:33.268759 [-4] MIN Duty = 4875%(X100), DQS PI = 38
2277 13:28:33.272045 [-4] AVG Duty = 4984%(X100)
2278 13:28:33.272575
2279 13:28:33.272865 ==DQM 1 ==
2280 13:28:33.275220 Final DQM duty delay cell = -4
2281 13:28:33.278227 [-4] MAX Duty = 5062%(X100), DQS PI = 4
2282 13:28:33.281520 [-4] MIN Duty = 4906%(X100), DQS PI = 42
2283 13:28:33.285248 [-4] AVG Duty = 4984%(X100)
2284 13:28:33.285627
2285 13:28:33.288514 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2286 13:28:33.288859
2287 13:28:33.291781 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2288 13:28:33.295317 [DutyScan_Calibration_Flow] ====Done====
2289 13:28:33.295793
2290 13:28:33.298251 [DutyScan_Calibration_Flow] k_type=2
2291 13:28:33.315628
2292 13:28:33.316111 ==DQ 0 ==
2293 13:28:33.318718 Final DQ duty delay cell = 0
2294 13:28:33.322380 [0] MAX Duty = 5062%(X100), DQS PI = 0
2295 13:28:33.325622 [0] MIN Duty = 4938%(X100), DQS PI = 44
2296 13:28:33.326108 [0] AVG Duty = 5000%(X100)
2297 13:28:33.326387
2298 13:28:33.328941 ==DQ 1 ==
2299 13:28:33.331941 Final DQ duty delay cell = 0
2300 13:28:33.335460 [0] MAX Duty = 5031%(X100), DQS PI = 8
2301 13:28:33.338827 [0] MIN Duty = 4875%(X100), DQS PI = 30
2302 13:28:33.339461 [0] AVG Duty = 4953%(X100)
2303 13:28:33.339796
2304 13:28:33.342021 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2305 13:28:33.342367
2306 13:28:33.348481 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2307 13:28:33.352007 [DutyScan_Calibration_Flow] ====Done====
2308 13:28:33.355306 nWR fixed to 30
2309 13:28:33.355660 [ModeRegInit_LP4] CH0 RK0
2310 13:28:33.358446 [ModeRegInit_LP4] CH0 RK1
2311 13:28:33.361618 [ModeRegInit_LP4] CH1 RK0
2312 13:28:33.364999 [ModeRegInit_LP4] CH1 RK1
2313 13:28:33.365308 match AC timing 6
2314 13:28:33.368766 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2315 13:28:33.375420 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2316 13:28:33.378095 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2317 13:28:33.385292 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2318 13:28:33.388675 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2319 13:28:33.389132 ==
2320 13:28:33.391856 Dram Type= 6, Freq= 0, CH_0, rank 0
2321 13:28:33.395056 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2322 13:28:33.395466 ==
2323 13:28:33.401602 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2324 13:28:33.408619 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2325 13:28:33.415456 [CA 0] Center 39 (9~70) winsize 62
2326 13:28:33.418684 [CA 1] Center 39 (9~70) winsize 62
2327 13:28:33.421883 [CA 2] Center 36 (5~67) winsize 63
2328 13:28:33.425324 [CA 3] Center 35 (5~66) winsize 62
2329 13:28:33.428583 [CA 4] Center 34 (3~65) winsize 63
2330 13:28:33.431611 [CA 5] Center 33 (3~64) winsize 62
2331 13:28:33.432062
2332 13:28:33.435500 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2333 13:28:33.435974
2334 13:28:33.438694 [CATrainingPosCal] consider 1 rank data
2335 13:28:33.442050 u2DelayCellTimex100 = 270/100 ps
2336 13:28:33.445156 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2337 13:28:33.448246 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2338 13:28:33.455121 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2339 13:28:33.458730 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2340 13:28:33.461237 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2341 13:28:33.464904 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2342 13:28:33.465381
2343 13:28:33.468226 CA PerBit enable=1, Macro0, CA PI delay=33
2344 13:28:33.468619
2345 13:28:33.471840 [CBTSetCACLKResult] CA Dly = 33
2346 13:28:33.472360 CS Dly: 7 (0~38)
2347 13:28:33.475405 ==
2348 13:28:33.477857 Dram Type= 6, Freq= 0, CH_0, rank 1
2349 13:28:33.481701 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2350 13:28:33.482172 ==
2351 13:28:33.485123 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2352 13:28:33.491944 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2353 13:28:33.500574 [CA 0] Center 39 (9~70) winsize 62
2354 13:28:33.503991 [CA 1] Center 39 (8~70) winsize 63
2355 13:28:33.507238 [CA 2] Center 35 (5~66) winsize 62
2356 13:28:33.510330 [CA 3] Center 35 (4~66) winsize 63
2357 13:28:33.514514 [CA 4] Center 33 (3~64) winsize 62
2358 13:28:33.517291 [CA 5] Center 33 (3~64) winsize 62
2359 13:28:33.517771
2360 13:28:33.520364 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2361 13:28:33.520836
2362 13:28:33.524163 [CATrainingPosCal] consider 2 rank data
2363 13:28:33.527046 u2DelayCellTimex100 = 270/100 ps
2364 13:28:33.530546 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2365 13:28:33.534278 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2366 13:28:33.540513 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2367 13:28:33.544089 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2368 13:28:33.547267 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2369 13:28:33.550614 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2370 13:28:33.551096
2371 13:28:33.553737 CA PerBit enable=1, Macro0, CA PI delay=33
2372 13:28:33.554112
2373 13:28:33.557933 [CBTSetCACLKResult] CA Dly = 33
2374 13:28:33.558420 CS Dly: 7 (0~39)
2375 13:28:33.558698
2376 13:28:33.560739 ----->DramcWriteLeveling(PI) begin...
2377 13:28:33.564591 ==
2378 13:28:33.567016 Dram Type= 6, Freq= 0, CH_0, rank 0
2379 13:28:33.570761 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2380 13:28:33.571238 ==
2381 13:28:33.573991 Write leveling (Byte 0): 26 => 26
2382 13:28:33.577225 Write leveling (Byte 1): 25 => 25
2383 13:28:33.580914 DramcWriteLeveling(PI) end<-----
2384 13:28:33.581396
2385 13:28:33.581674 ==
2386 13:28:33.583765 Dram Type= 6, Freq= 0, CH_0, rank 0
2387 13:28:33.587306 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2388 13:28:33.587764 ==
2389 13:28:33.591243 [Gating] SW mode calibration
2390 13:28:33.597184 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2391 13:28:33.600846 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2392 13:28:33.607552 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2393 13:28:33.610498 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2394 13:28:33.613882 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2395 13:28:33.620602 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2396 13:28:33.624472 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2397 13:28:33.627378 0 11 20 | B1->B0 | 3232 2c2c | 1 0 | (1 0) (0 1)
2398 13:28:33.633895 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2399 13:28:33.637197 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2400 13:28:33.640335 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2401 13:28:33.647383 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2402 13:28:33.650651 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2403 13:28:33.653918 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2404 13:28:33.660916 0 12 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2405 13:28:33.663984 0 12 20 | B1->B0 | 3838 3d3d | 0 0 | (0 0) (1 1)
2406 13:28:33.667388 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2407 13:28:33.673735 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2408 13:28:33.677692 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2409 13:28:33.680635 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2410 13:28:33.687381 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2411 13:28:33.690363 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2412 13:28:33.693915 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2413 13:28:33.697132 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2414 13:28:33.704192 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2415 13:28:33.707103 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2416 13:28:33.710182 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2417 13:28:33.717496 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2418 13:28:33.720429 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2419 13:28:33.724111 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2420 13:28:33.730143 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2421 13:28:33.733625 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2422 13:28:33.737002 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2423 13:28:33.744070 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2424 13:28:33.747249 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2425 13:28:33.750068 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2426 13:28:33.757073 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2427 13:28:33.760920 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2428 13:28:33.764045 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2429 13:28:33.770373 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2430 13:28:33.773785 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2431 13:28:33.776947 Total UI for P1: 0, mck2ui 16
2432 13:28:33.780333 best dqsien dly found for B0: ( 0, 15, 18)
2433 13:28:33.784509 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2434 13:28:33.786909 Total UI for P1: 0, mck2ui 16
2435 13:28:33.790648 best dqsien dly found for B1: ( 0, 15, 20)
2436 13:28:33.793802 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2437 13:28:33.797102 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2438 13:28:33.797548
2439 13:28:33.803665 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2440 13:28:33.807466 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2441 13:28:33.807937 [Gating] SW calibration Done
2442 13:28:33.810161 ==
2443 13:28:33.813624 Dram Type= 6, Freq= 0, CH_0, rank 0
2444 13:28:33.816513 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2445 13:28:33.816859 ==
2446 13:28:33.817107 RX Vref Scan: 0
2447 13:28:33.817324
2448 13:28:33.819854 RX Vref 0 -> 0, step: 1
2449 13:28:33.820197
2450 13:28:33.823905 RX Delay -40 -> 252, step: 8
2451 13:28:33.826777 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2452 13:28:33.830578 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2453 13:28:33.833934 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2454 13:28:33.840058 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2455 13:28:33.843448 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2456 13:28:33.847234 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2457 13:28:33.850375 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2458 13:28:33.853713 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2459 13:28:33.860421 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2460 13:28:33.863443 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2461 13:28:33.866925 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2462 13:28:33.870622 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2463 13:28:33.873278 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2464 13:28:33.880039 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2465 13:28:33.883623 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2466 13:28:33.886965 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2467 13:28:33.887429 ==
2468 13:28:33.890389 Dram Type= 6, Freq= 0, CH_0, rank 0
2469 13:28:33.893982 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2470 13:28:33.894468 ==
2471 13:28:33.896729 DQS Delay:
2472 13:28:33.897207 DQS0 = 0, DQS1 = 0
2473 13:28:33.899920 DQM Delay:
2474 13:28:33.900324 DQM0 = 115, DQM1 = 106
2475 13:28:33.900603 DQ Delay:
2476 13:28:33.906856 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2477 13:28:33.910045 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2478 13:28:33.913041 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2479 13:28:33.917030 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2480 13:28:33.917471
2481 13:28:33.917741
2482 13:28:33.917982 ==
2483 13:28:33.919765 Dram Type= 6, Freq= 0, CH_0, rank 0
2484 13:28:33.923439 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2485 13:28:33.924024 ==
2486 13:28:33.924361
2487 13:28:33.924614
2488 13:28:33.926697 TX Vref Scan disable
2489 13:28:33.930393 == TX Byte 0 ==
2490 13:28:33.933469 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2491 13:28:33.936947 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2492 13:28:33.939810 == TX Byte 1 ==
2493 13:28:33.943128 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2494 13:28:33.946586 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2495 13:28:33.946984 ==
2496 13:28:33.949697 Dram Type= 6, Freq= 0, CH_0, rank 0
2497 13:28:33.953227 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2498 13:28:33.956766 ==
2499 13:28:33.966273 TX Vref=22, minBit 1, minWin=25, winSum=409
2500 13:28:33.969884 TX Vref=24, minBit 10, minWin=25, winSum=416
2501 13:28:33.973177 TX Vref=26, minBit 1, minWin=26, winSum=424
2502 13:28:33.976916 TX Vref=28, minBit 8, minWin=25, winSum=426
2503 13:28:33.979986 TX Vref=30, minBit 4, minWin=26, winSum=428
2504 13:28:33.986553 TX Vref=32, minBit 5, minWin=26, winSum=427
2505 13:28:33.989532 [TxChooseVref] Worse bit 4, Min win 26, Win sum 428, Final Vref 30
2506 13:28:33.990004
2507 13:28:33.993200 Final TX Range 1 Vref 30
2508 13:28:33.993684
2509 13:28:33.993962 ==
2510 13:28:33.996468 Dram Type= 6, Freq= 0, CH_0, rank 0
2511 13:28:33.999978 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2512 13:28:34.000451 ==
2513 13:28:34.003088
2514 13:28:34.003572
2515 13:28:34.003900 TX Vref Scan disable
2516 13:28:34.006156 == TX Byte 0 ==
2517 13:28:34.009478 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2518 13:28:34.013049 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2519 13:28:34.016115 == TX Byte 1 ==
2520 13:28:34.019412 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2521 13:28:34.026311 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2522 13:28:34.026657
2523 13:28:34.026901 [DATLAT]
2524 13:28:34.027122 Freq=1200, CH0 RK0
2525 13:28:34.027335
2526 13:28:34.030038 DATLAT Default: 0xd
2527 13:28:34.030489 0, 0xFFFF, sum = 0
2528 13:28:34.033083 1, 0xFFFF, sum = 0
2529 13:28:34.033465 2, 0xFFFF, sum = 0
2530 13:28:34.036172 3, 0xFFFF, sum = 0
2531 13:28:34.036562 4, 0xFFFF, sum = 0
2532 13:28:34.039550 5, 0xFFFF, sum = 0
2533 13:28:34.043020 6, 0xFFFF, sum = 0
2534 13:28:34.043475 7, 0xFFFF, sum = 0
2535 13:28:34.046427 8, 0xFFFF, sum = 0
2536 13:28:34.046877 9, 0xFFFF, sum = 0
2537 13:28:34.049228 10, 0xFFFF, sum = 0
2538 13:28:34.049579 11, 0x0, sum = 1
2539 13:28:34.053243 12, 0x0, sum = 2
2540 13:28:34.053711 13, 0x0, sum = 3
2541 13:28:34.053986 14, 0x0, sum = 4
2542 13:28:34.056078 best_step = 12
2543 13:28:34.056473
2544 13:28:34.056728 ==
2545 13:28:34.059503 Dram Type= 6, Freq= 0, CH_0, rank 0
2546 13:28:34.062790 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2547 13:28:34.063244 ==
2548 13:28:34.066066 RX Vref Scan: 1
2549 13:28:34.066411
2550 13:28:34.069266 Set Vref Range= 32 -> 127
2551 13:28:34.069722
2552 13:28:34.069979 RX Vref 32 -> 127, step: 1
2553 13:28:34.070200
2554 13:28:34.073141 RX Delay -21 -> 252, step: 4
2555 13:28:34.073596
2556 13:28:34.076091 Set Vref, RX VrefLevel [Byte0]: 32
2557 13:28:34.079270 [Byte1]: 32
2558 13:28:34.082843
2559 13:28:34.083187 Set Vref, RX VrefLevel [Byte0]: 33
2560 13:28:34.086189 [Byte1]: 33
2561 13:28:34.091389
2562 13:28:34.091840 Set Vref, RX VrefLevel [Byte0]: 34
2563 13:28:34.093995 [Byte1]: 34
2564 13:28:34.098876
2565 13:28:34.099325 Set Vref, RX VrefLevel [Byte0]: 35
2566 13:28:34.102110 [Byte1]: 35
2567 13:28:34.106629
2568 13:28:34.107108 Set Vref, RX VrefLevel [Byte0]: 36
2569 13:28:34.109691 [Byte1]: 36
2570 13:28:34.114894
2571 13:28:34.115382 Set Vref, RX VrefLevel [Byte0]: 37
2572 13:28:34.118253 [Byte1]: 37
2573 13:28:34.122838
2574 13:28:34.123322 Set Vref, RX VrefLevel [Byte0]: 38
2575 13:28:34.125800 [Byte1]: 38
2576 13:28:34.130811
2577 13:28:34.131293 Set Vref, RX VrefLevel [Byte0]: 39
2578 13:28:34.133827 [Byte1]: 39
2579 13:28:34.138660
2580 13:28:34.139189 Set Vref, RX VrefLevel [Byte0]: 40
2581 13:28:34.141571 [Byte1]: 40
2582 13:28:34.146630
2583 13:28:34.147089 Set Vref, RX VrefLevel [Byte0]: 41
2584 13:28:34.149784 [Byte1]: 41
2585 13:28:34.154248
2586 13:28:34.154736 Set Vref, RX VrefLevel [Byte0]: 42
2587 13:28:34.157516 [Byte1]: 42
2588 13:28:34.162109
2589 13:28:34.162545 Set Vref, RX VrefLevel [Byte0]: 43
2590 13:28:34.165178 [Byte1]: 43
2591 13:28:34.170531
2592 13:28:34.171016 Set Vref, RX VrefLevel [Byte0]: 44
2593 13:28:34.173729 [Byte1]: 44
2594 13:28:34.178100
2595 13:28:34.178589 Set Vref, RX VrefLevel [Byte0]: 45
2596 13:28:34.181189 [Byte1]: 45
2597 13:28:34.185770
2598 13:28:34.186215 Set Vref, RX VrefLevel [Byte0]: 46
2599 13:28:34.189174 [Byte1]: 46
2600 13:28:34.193998
2601 13:28:34.194451 Set Vref, RX VrefLevel [Byte0]: 47
2602 13:28:34.197492 [Byte1]: 47
2603 13:28:34.201605
2604 13:28:34.202069 Set Vref, RX VrefLevel [Byte0]: 48
2605 13:28:34.205359 [Byte1]: 48
2606 13:28:34.209696
2607 13:28:34.210168 Set Vref, RX VrefLevel [Byte0]: 49
2608 13:28:34.213243 [Byte1]: 49
2609 13:28:34.218067
2610 13:28:34.218547 Set Vref, RX VrefLevel [Byte0]: 50
2611 13:28:34.221033 [Byte1]: 50
2612 13:28:34.225382
2613 13:28:34.225863 Set Vref, RX VrefLevel [Byte0]: 51
2614 13:28:34.229133 [Byte1]: 51
2615 13:28:34.233529
2616 13:28:34.233898 Set Vref, RX VrefLevel [Byte0]: 52
2617 13:28:34.236550 [Byte1]: 52
2618 13:28:34.241536
2619 13:28:34.242025 Set Vref, RX VrefLevel [Byte0]: 53
2620 13:28:34.244377 [Byte1]: 53
2621 13:28:34.249517
2622 13:28:34.249984 Set Vref, RX VrefLevel [Byte0]: 54
2623 13:28:34.252927 [Byte1]: 54
2624 13:28:34.257534
2625 13:28:34.257991 Set Vref, RX VrefLevel [Byte0]: 55
2626 13:28:34.260799 [Byte1]: 55
2627 13:28:34.264921
2628 13:28:34.265382 Set Vref, RX VrefLevel [Byte0]: 56
2629 13:28:34.268187 [Byte1]: 56
2630 13:28:34.273151
2631 13:28:34.273645 Set Vref, RX VrefLevel [Byte0]: 57
2632 13:28:34.276391 [Byte1]: 57
2633 13:28:34.281079
2634 13:28:34.281554 Set Vref, RX VrefLevel [Byte0]: 58
2635 13:28:34.284451 [Byte1]: 58
2636 13:28:34.288901
2637 13:28:34.289279 Set Vref, RX VrefLevel [Byte0]: 59
2638 13:28:34.292062 [Byte1]: 59
2639 13:28:34.297004
2640 13:28:34.297481 Set Vref, RX VrefLevel [Byte0]: 60
2641 13:28:34.300009 [Byte1]: 60
2642 13:28:34.304431
2643 13:28:34.304794 Set Vref, RX VrefLevel [Byte0]: 61
2644 13:28:34.308540 [Byte1]: 61
2645 13:28:34.312650
2646 13:28:34.313047 Set Vref, RX VrefLevel [Byte0]: 62
2647 13:28:34.315966 [Byte1]: 62
2648 13:28:34.320840
2649 13:28:34.321330 Set Vref, RX VrefLevel [Byte0]: 63
2650 13:28:34.323915 [Byte1]: 63
2651 13:28:34.328630
2652 13:28:34.329120 Set Vref, RX VrefLevel [Byte0]: 64
2653 13:28:34.331902 [Byte1]: 64
2654 13:28:34.336024
2655 13:28:34.336476 Set Vref, RX VrefLevel [Byte0]: 65
2656 13:28:34.339518 [Byte1]: 65
2657 13:28:34.344252
2658 13:28:34.344747 Set Vref, RX VrefLevel [Byte0]: 66
2659 13:28:34.347353 [Byte1]: 66
2660 13:28:34.352195
2661 13:28:34.352753 Final RX Vref Byte 0 = 47 to rank0
2662 13:28:34.355494 Final RX Vref Byte 1 = 48 to rank0
2663 13:28:34.359233 Final RX Vref Byte 0 = 47 to rank1
2664 13:28:34.362317 Final RX Vref Byte 1 = 48 to rank1==
2665 13:28:34.365806 Dram Type= 6, Freq= 0, CH_0, rank 0
2666 13:28:34.372643 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2667 13:28:34.373130 ==
2668 13:28:34.373404 DQS Delay:
2669 13:28:34.373643 DQS0 = 0, DQS1 = 0
2670 13:28:34.375550 DQM Delay:
2671 13:28:34.376009 DQM0 = 113, DQM1 = 105
2672 13:28:34.378906 DQ Delay:
2673 13:28:34.382110 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =108
2674 13:28:34.385110 DQ4 =118, DQ5 =104, DQ6 =124, DQ7 =120
2675 13:28:34.388636 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =96
2676 13:28:34.392326 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2677 13:28:34.392787
2678 13:28:34.393059
2679 13:28:34.398920 [DQSOSCAuto] RK0, (LSB)MR18= 0x202, (MSB)MR19= 0x404, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
2680 13:28:34.401903 CH0 RK0: MR19=404, MR18=202
2681 13:28:34.408918 CH0_RK0: MR19=0x404, MR18=0x202, DQSOSC=409, MR23=63, INC=39, DEC=26
2682 13:28:34.409410
2683 13:28:34.411697 ----->DramcWriteLeveling(PI) begin...
2684 13:28:34.412083 ==
2685 13:28:34.415794 Dram Type= 6, Freq= 0, CH_0, rank 1
2686 13:28:34.419017 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2687 13:28:34.419509 ==
2688 13:28:34.422550 Write leveling (Byte 0): 28 => 28
2689 13:28:34.425697 Write leveling (Byte 1): 26 => 26
2690 13:28:34.429764 DramcWriteLeveling(PI) end<-----
2691 13:28:34.430250
2692 13:28:34.430527 ==
2693 13:28:34.432006 Dram Type= 6, Freq= 0, CH_0, rank 1
2694 13:28:34.435506 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2695 13:28:34.438632 ==
2696 13:28:34.439016 [Gating] SW mode calibration
2697 13:28:34.449048 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2698 13:28:34.451696 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2699 13:28:34.455392 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2700 13:28:34.462194 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2701 13:28:34.465076 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2702 13:28:34.468367 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2703 13:28:34.475513 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2704 13:28:34.478531 0 11 20 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
2705 13:28:34.482328 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2706 13:28:34.488623 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2707 13:28:34.492399 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2708 13:28:34.495609 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2709 13:28:34.501422 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2710 13:28:34.505263 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2711 13:28:34.508261 0 12 16 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2712 13:28:34.515257 0 12 20 | B1->B0 | 3737 4444 | 1 1 | (0 0) (0 0)
2713 13:28:34.518383 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2714 13:28:34.521548 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2715 13:28:34.528208 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2716 13:28:34.531988 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2717 13:28:34.534850 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2718 13:28:34.541552 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2719 13:28:34.545090 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2720 13:28:34.548137 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2721 13:28:34.555158 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2722 13:28:34.558262 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2723 13:28:34.561878 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2724 13:28:34.565250 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2725 13:28:34.572071 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2726 13:28:34.575135 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2727 13:28:34.578458 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2728 13:28:34.585209 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2729 13:28:34.588426 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2730 13:28:34.591934 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2731 13:28:34.598605 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2732 13:28:34.602007 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2733 13:28:34.605621 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2734 13:28:34.611522 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2735 13:28:34.614948 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2736 13:28:34.618063 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2737 13:28:34.624871 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2738 13:28:34.625336 Total UI for P1: 0, mck2ui 16
2739 13:28:34.631506 best dqsien dly found for B0: ( 0, 15, 20)
2740 13:28:34.634437 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2741 13:28:34.638134 Total UI for P1: 0, mck2ui 16
2742 13:28:34.641762 best dqsien dly found for B1: ( 0, 15, 22)
2743 13:28:34.644703 best DQS0 dly(MCK, UI, PI) = (0, 15, 20)
2744 13:28:34.648656 best DQS1 dly(MCK, UI, PI) = (0, 15, 22)
2745 13:28:34.649065
2746 13:28:34.651731 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 20)
2747 13:28:34.654854 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 22)
2748 13:28:34.658260 [Gating] SW calibration Done
2749 13:28:34.658669 ==
2750 13:28:34.661677 Dram Type= 6, Freq= 0, CH_0, rank 1
2751 13:28:34.665325 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2752 13:28:34.668164 ==
2753 13:28:34.668601 RX Vref Scan: 0
2754 13:28:34.668970
2755 13:28:34.671578 RX Vref 0 -> 0, step: 1
2756 13:28:34.672068
2757 13:28:34.672492 RX Delay -40 -> 252, step: 8
2758 13:28:34.678533 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2759 13:28:34.681275 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2760 13:28:34.685482 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2761 13:28:34.688615 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2762 13:28:34.691990 iDelay=200, Bit 4, Center 119 (40 ~ 199) 160
2763 13:28:34.698505 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2764 13:28:34.702098 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2765 13:28:34.705128 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2766 13:28:34.708380 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2767 13:28:34.711446 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2768 13:28:34.718634 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2769 13:28:34.721695 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2770 13:28:34.724941 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2771 13:28:34.728308 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2772 13:28:34.731899 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2773 13:28:34.738505 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2774 13:28:34.738977 ==
2775 13:28:34.741369 Dram Type= 6, Freq= 0, CH_0, rank 1
2776 13:28:34.745147 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2777 13:28:34.745541 ==
2778 13:28:34.745870 DQS Delay:
2779 13:28:34.748062 DQS0 = 0, DQS1 = 0
2780 13:28:34.748369 DQM Delay:
2781 13:28:34.751369 DQM0 = 115, DQM1 = 107
2782 13:28:34.751745 DQ Delay:
2783 13:28:34.755028 DQ0 =107, DQ1 =115, DQ2 =115, DQ3 =111
2784 13:28:34.758107 DQ4 =119, DQ5 =107, DQ6 =123, DQ7 =123
2785 13:28:34.761496 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2786 13:28:34.765191 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2787 13:28:34.765693
2788 13:28:34.766077
2789 13:28:34.767682 ==
2790 13:28:34.767975 Dram Type= 6, Freq= 0, CH_0, rank 1
2791 13:28:34.775245 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2792 13:28:34.775740 ==
2793 13:28:34.776123
2794 13:28:34.776472
2795 13:28:34.778479 TX Vref Scan disable
2796 13:28:34.778970 == TX Byte 0 ==
2797 13:28:34.781225 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2798 13:28:34.788143 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2799 13:28:34.788679 == TX Byte 1 ==
2800 13:28:34.791479 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2801 13:28:34.798196 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2802 13:28:34.798682 ==
2803 13:28:34.801280 Dram Type= 6, Freq= 0, CH_0, rank 1
2804 13:28:34.804416 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2805 13:28:34.804806 ==
2806 13:28:34.816763 TX Vref=22, minBit 8, minWin=25, winSum=419
2807 13:28:34.820160 TX Vref=24, minBit 8, minWin=25, winSum=424
2808 13:28:34.823362 TX Vref=26, minBit 8, minWin=26, winSum=426
2809 13:28:34.826633 TX Vref=28, minBit 10, minWin=25, winSum=430
2810 13:28:34.829953 TX Vref=30, minBit 10, minWin=26, winSum=436
2811 13:28:34.836270 TX Vref=32, minBit 10, minWin=25, winSum=435
2812 13:28:34.840187 [TxChooseVref] Worse bit 10, Min win 26, Win sum 436, Final Vref 30
2813 13:28:34.840730
2814 13:28:34.843175 Final TX Range 1 Vref 30
2815 13:28:34.843564
2816 13:28:34.843842 ==
2817 13:28:34.846303 Dram Type= 6, Freq= 0, CH_0, rank 1
2818 13:28:34.850588 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2819 13:28:34.853211 ==
2820 13:28:34.853619
2821 13:28:34.853892
2822 13:28:34.854129 TX Vref Scan disable
2823 13:28:34.856112 == TX Byte 0 ==
2824 13:28:34.860108 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2825 13:28:34.867125 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2826 13:28:34.867577 == TX Byte 1 ==
2827 13:28:34.870101 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2828 13:28:34.876062 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2829 13:28:34.876501
2830 13:28:34.876767 [DATLAT]
2831 13:28:34.877005 Freq=1200, CH0 RK1
2832 13:28:34.877245
2833 13:28:34.879772 DATLAT Default: 0xc
2834 13:28:34.880198 0, 0xFFFF, sum = 0
2835 13:28:34.883200 1, 0xFFFF, sum = 0
2836 13:28:34.883584 2, 0xFFFF, sum = 0
2837 13:28:34.886090 3, 0xFFFF, sum = 0
2838 13:28:34.890007 4, 0xFFFF, sum = 0
2839 13:28:34.890355 5, 0xFFFF, sum = 0
2840 13:28:34.892943 6, 0xFFFF, sum = 0
2841 13:28:34.893290 7, 0xFFFF, sum = 0
2842 13:28:34.896171 8, 0xFFFF, sum = 0
2843 13:28:34.896568 9, 0xFFFF, sum = 0
2844 13:28:34.899890 10, 0xFFFF, sum = 0
2845 13:28:34.900393 11, 0x0, sum = 1
2846 13:28:34.903283 12, 0x0, sum = 2
2847 13:28:34.903743 13, 0x0, sum = 3
2848 13:28:34.906531 14, 0x0, sum = 4
2849 13:28:34.906888 best_step = 12
2850 13:28:34.907138
2851 13:28:34.907360 ==
2852 13:28:34.909752 Dram Type= 6, Freq= 0, CH_0, rank 1
2853 13:28:34.912707 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2854 13:28:34.913055 ==
2855 13:28:34.916618 RX Vref Scan: 0
2856 13:28:34.917072
2857 13:28:34.919731 RX Vref 0 -> 0, step: 1
2858 13:28:34.920075
2859 13:28:34.920355 RX Delay -21 -> 252, step: 4
2860 13:28:34.927258 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2861 13:28:34.930243 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2862 13:28:34.933462 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2863 13:28:34.936563 iDelay=199, Bit 3, Center 108 (39 ~ 178) 140
2864 13:28:34.939985 iDelay=199, Bit 4, Center 118 (47 ~ 190) 144
2865 13:28:34.946801 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2866 13:28:34.950317 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
2867 13:28:34.953302 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2868 13:28:34.957142 iDelay=199, Bit 8, Center 94 (31 ~ 158) 128
2869 13:28:34.960065 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2870 13:28:34.966923 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
2871 13:28:34.970176 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2872 13:28:34.973529 iDelay=199, Bit 12, Center 114 (51 ~ 178) 128
2873 13:28:34.976701 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2874 13:28:34.980073 iDelay=199, Bit 14, Center 116 (51 ~ 182) 132
2875 13:28:34.986898 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2876 13:28:34.987244 ==
2877 13:28:34.990195 Dram Type= 6, Freq= 0, CH_0, rank 1
2878 13:28:34.993460 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2879 13:28:34.993807 ==
2880 13:28:34.994056 DQS Delay:
2881 13:28:34.996944 DQS0 = 0, DQS1 = 0
2882 13:28:34.997289 DQM Delay:
2883 13:28:34.999989 DQM0 = 115, DQM1 = 105
2884 13:28:35.000365 DQ Delay:
2885 13:28:35.003530 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2886 13:28:35.007161 DQ4 =118, DQ5 =108, DQ6 =122, DQ7 =124
2887 13:28:35.010176 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =96
2888 13:28:35.013744 DQ12 =114, DQ13 =112, DQ14 =116, DQ15 =114
2889 13:28:35.014090
2890 13:28:35.014342
2891 13:28:35.023680 [DQSOSCAuto] RK1, (LSB)MR18= 0x1111, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 403 ps
2892 13:28:35.026910 CH0 RK1: MR19=404, MR18=1111
2893 13:28:35.030362 CH0_RK1: MR19=0x404, MR18=0x1111, DQSOSC=403, MR23=63, INC=40, DEC=26
2894 13:28:35.033617 [RxdqsGatingPostProcess] freq 1200
2895 13:28:35.039839 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2896 13:28:35.043586 Pre-setting of DQS Precalculation
2897 13:28:35.046972 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2898 13:28:35.050042 ==
2899 13:28:35.050440 Dram Type= 6, Freq= 0, CH_1, rank 0
2900 13:28:35.057020 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2901 13:28:35.057369 ==
2902 13:28:35.060033 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2903 13:28:35.066622 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2904 13:28:35.075707 [CA 0] Center 37 (7~68) winsize 62
2905 13:28:35.079015 [CA 1] Center 37 (7~68) winsize 62
2906 13:28:35.081904 [CA 2] Center 34 (4~65) winsize 62
2907 13:28:35.085765 [CA 3] Center 33 (3~64) winsize 62
2908 13:28:35.088675 [CA 4] Center 32 (2~63) winsize 62
2909 13:28:35.092142 [CA 5] Center 32 (2~63) winsize 62
2910 13:28:35.092518
2911 13:28:35.095744 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2912 13:28:35.096169
2913 13:28:35.098884 [CATrainingPosCal] consider 1 rank data
2914 13:28:35.102310 u2DelayCellTimex100 = 270/100 ps
2915 13:28:35.105748 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2916 13:28:35.108731 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2917 13:28:35.115710 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2918 13:28:35.118950 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2919 13:28:35.122158 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2920 13:28:35.125738 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2921 13:28:35.126183
2922 13:28:35.129071 CA PerBit enable=1, Macro0, CA PI delay=32
2923 13:28:35.129523
2924 13:28:35.132192 [CBTSetCACLKResult] CA Dly = 32
2925 13:28:35.132654 CS Dly: 6 (0~37)
2926 13:28:35.132915 ==
2927 13:28:35.135934 Dram Type= 6, Freq= 0, CH_1, rank 1
2928 13:28:35.142499 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2929 13:28:35.142848 ==
2930 13:28:35.145581 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2931 13:28:35.152480 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2932 13:28:35.160791 [CA 0] Center 37 (6~68) winsize 63
2933 13:28:35.164604 [CA 1] Center 37 (7~68) winsize 62
2934 13:28:35.167399 [CA 2] Center 34 (3~65) winsize 63
2935 13:28:35.170962 [CA 3] Center 33 (3~64) winsize 62
2936 13:28:35.174179 [CA 4] Center 32 (2~63) winsize 62
2937 13:28:35.177593 [CA 5] Center 32 (2~63) winsize 62
2938 13:28:35.177963
2939 13:28:35.180484 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2940 13:28:35.180829
2941 13:28:35.183828 [CATrainingPosCal] consider 2 rank data
2942 13:28:35.187486 u2DelayCellTimex100 = 270/100 ps
2943 13:28:35.190366 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2944 13:28:35.194568 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2945 13:28:35.201262 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2946 13:28:35.204133 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2947 13:28:35.207680 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2948 13:28:35.210865 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2949 13:28:35.211307
2950 13:28:35.213976 CA PerBit enable=1, Macro0, CA PI delay=32
2951 13:28:35.214356
2952 13:28:35.217627 [CBTSetCACLKResult] CA Dly = 32
2953 13:28:35.218074 CS Dly: 6 (0~38)
2954 13:28:35.218352
2955 13:28:35.221034 ----->DramcWriteLeveling(PI) begin...
2956 13:28:35.224596 ==
2957 13:28:35.227605 Dram Type= 6, Freq= 0, CH_1, rank 0
2958 13:28:35.231098 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2959 13:28:35.231586 ==
2960 13:28:35.234286 Write leveling (Byte 0): 21 => 21
2961 13:28:35.237144 Write leveling (Byte 1): 22 => 22
2962 13:28:35.240251 DramcWriteLeveling(PI) end<-----
2963 13:28:35.240696
2964 13:28:35.240974 ==
2965 13:28:35.244396 Dram Type= 6, Freq= 0, CH_1, rank 0
2966 13:28:35.247311 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2967 13:28:35.247823 ==
2968 13:28:35.250982 [Gating] SW mode calibration
2969 13:28:35.257638 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2970 13:28:35.260857 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2971 13:28:35.267588 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2972 13:28:35.270731 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2973 13:28:35.274641 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2974 13:28:35.280985 0 11 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
2975 13:28:35.283975 0 11 16 | B1->B0 | 3434 2929 | 1 1 | (1 0) (1 0)
2976 13:28:35.287544 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2977 13:28:35.293942 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2978 13:28:35.297447 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2979 13:28:35.300651 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2980 13:28:35.307936 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2981 13:28:35.310507 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2982 13:28:35.313950 0 12 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2983 13:28:35.320044 0 12 16 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
2984 13:28:35.323941 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2985 13:28:35.327668 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2986 13:28:35.333639 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2987 13:28:35.336647 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2988 13:28:35.340456 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2989 13:28:35.347464 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2990 13:28:35.350109 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2991 13:28:35.353703 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2992 13:28:35.360024 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2993 13:28:35.363497 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2994 13:28:35.366863 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2995 13:28:35.373716 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2996 13:28:35.376423 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2997 13:28:35.380168 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2998 13:28:35.386821 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2999 13:28:35.390329 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3000 13:28:35.393574 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3001 13:28:35.400115 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3002 13:28:35.403402 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3003 13:28:35.407276 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3004 13:28:35.410624 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3005 13:28:35.416838 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3006 13:28:35.419885 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3007 13:28:35.423522 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3008 13:28:35.430058 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3009 13:28:35.434025 Total UI for P1: 0, mck2ui 16
3010 13:28:35.436865 best dqsien dly found for B0: ( 0, 15, 16)
3011 13:28:35.439881 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3012 13:28:35.443129 Total UI for P1: 0, mck2ui 16
3013 13:28:35.447100 best dqsien dly found for B1: ( 0, 15, 18)
3014 13:28:35.450391 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3015 13:28:35.453258 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3016 13:28:35.453615
3017 13:28:35.456491 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3018 13:28:35.459792 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3019 13:28:35.463716 [Gating] SW calibration Done
3020 13:28:35.464136 ==
3021 13:28:35.466439 Dram Type= 6, Freq= 0, CH_1, rank 0
3022 13:28:35.473811 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3023 13:28:35.474209 ==
3024 13:28:35.474466 RX Vref Scan: 0
3025 13:28:35.474756
3026 13:28:35.476604 RX Vref 0 -> 0, step: 1
3027 13:28:35.476958
3028 13:28:35.480048 RX Delay -40 -> 252, step: 8
3029 13:28:35.483270 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3030 13:28:35.486441 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3031 13:28:35.490128 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3032 13:28:35.493198 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3033 13:28:35.500020 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3034 13:28:35.503495 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3035 13:28:35.506763 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3036 13:28:35.510002 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3037 13:28:35.513083 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3038 13:28:35.519641 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3039 13:28:35.523757 iDelay=208, Bit 10, Center 107 (32 ~ 183) 152
3040 13:28:35.526879 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3041 13:28:35.530308 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3042 13:28:35.533025 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3043 13:28:35.539866 iDelay=208, Bit 14, Center 115 (48 ~ 183) 136
3044 13:28:35.542852 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3045 13:28:35.543283 ==
3046 13:28:35.546615 Dram Type= 6, Freq= 0, CH_1, rank 0
3047 13:28:35.550145 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3048 13:28:35.550589 ==
3049 13:28:35.553255 DQS Delay:
3050 13:28:35.553611 DQS0 = 0, DQS1 = 0
3051 13:28:35.553861 DQM Delay:
3052 13:28:35.556266 DQM0 = 116, DQM1 = 107
3053 13:28:35.556759 DQ Delay:
3054 13:28:35.560084 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3055 13:28:35.563432 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3056 13:28:35.566404 DQ8 =87, DQ9 =95, DQ10 =107, DQ11 =99
3057 13:28:35.569789 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3058 13:28:35.573532
3059 13:28:35.573984
3060 13:28:35.574247 ==
3061 13:28:35.576224 Dram Type= 6, Freq= 0, CH_1, rank 0
3062 13:28:35.580117 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3063 13:28:35.580601 ==
3064 13:28:35.580861
3065 13:28:35.581083
3066 13:28:35.582872 TX Vref Scan disable
3067 13:28:35.583131 == TX Byte 0 ==
3068 13:28:35.589486 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3069 13:28:35.593271 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3070 13:28:35.593638 == TX Byte 1 ==
3071 13:28:35.599557 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3072 13:28:35.603144 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3073 13:28:35.603502 ==
3074 13:28:35.606545 Dram Type= 6, Freq= 0, CH_1, rank 0
3075 13:28:35.609586 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3076 13:28:35.609943 ==
3077 13:28:35.621813 TX Vref=22, minBit 5, minWin=25, winSum=414
3078 13:28:35.625342 TX Vref=24, minBit 3, minWin=24, winSum=417
3079 13:28:35.628861 TX Vref=26, minBit 0, minWin=26, winSum=423
3080 13:28:35.631705 TX Vref=28, minBit 8, minWin=26, winSum=432
3081 13:28:35.635240 TX Vref=30, minBit 1, minWin=26, winSum=429
3082 13:28:35.641516 TX Vref=32, minBit 9, minWin=26, winSum=430
3083 13:28:35.645513 [TxChooseVref] Worse bit 8, Min win 26, Win sum 432, Final Vref 28
3084 13:28:35.645897
3085 13:28:35.648498 Final TX Range 1 Vref 28
3086 13:28:35.648868
3087 13:28:35.649129 ==
3088 13:28:35.651976 Dram Type= 6, Freq= 0, CH_1, rank 0
3089 13:28:35.655452 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3090 13:28:35.655909 ==
3091 13:28:35.656225
3092 13:28:35.658816
3093 13:28:35.659297 TX Vref Scan disable
3094 13:28:35.662337 == TX Byte 0 ==
3095 13:28:35.665575 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3096 13:28:35.668387 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3097 13:28:35.672059 == TX Byte 1 ==
3098 13:28:35.675446 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3099 13:28:35.678714 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3100 13:28:35.679215
3101 13:28:35.682059 [DATLAT]
3102 13:28:35.682546 Freq=1200, CH1 RK0
3103 13:28:35.682846
3104 13:28:35.685143 DATLAT Default: 0xd
3105 13:28:35.685583 0, 0xFFFF, sum = 0
3106 13:28:35.688830 1, 0xFFFF, sum = 0
3107 13:28:35.689329 2, 0xFFFF, sum = 0
3108 13:28:35.691850 3, 0xFFFF, sum = 0
3109 13:28:35.692240 4, 0xFFFF, sum = 0
3110 13:28:35.695261 5, 0xFFFF, sum = 0
3111 13:28:35.695781 6, 0xFFFF, sum = 0
3112 13:28:35.698378 7, 0xFFFF, sum = 0
3113 13:28:35.701575 8, 0xFFFF, sum = 0
3114 13:28:35.701985 9, 0xFFFF, sum = 0
3115 13:28:35.705017 10, 0xFFFF, sum = 0
3116 13:28:35.705422 11, 0x0, sum = 1
3117 13:28:35.705707 12, 0x0, sum = 2
3118 13:28:35.708784 13, 0x0, sum = 3
3119 13:28:35.709275 14, 0x0, sum = 4
3120 13:28:35.711683 best_step = 12
3121 13:28:35.712025
3122 13:28:35.712333 ==
3123 13:28:35.714837 Dram Type= 6, Freq= 0, CH_1, rank 0
3124 13:28:35.718503 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3125 13:28:35.718881 ==
3126 13:28:35.721783 RX Vref Scan: 1
3127 13:28:35.722145
3128 13:28:35.722405 Set Vref Range= 32 -> 127
3129 13:28:35.724882
3130 13:28:35.725247 RX Vref 32 -> 127, step: 1
3131 13:28:35.725519
3132 13:28:35.728558 RX Delay -29 -> 252, step: 4
3133 13:28:35.729021
3134 13:28:35.731930 Set Vref, RX VrefLevel [Byte0]: 32
3135 13:28:35.735141 [Byte1]: 32
3136 13:28:35.738080
3137 13:28:35.738411 Set Vref, RX VrefLevel [Byte0]: 33
3138 13:28:35.742199 [Byte1]: 33
3139 13:28:35.746268
3140 13:28:35.746686 Set Vref, RX VrefLevel [Byte0]: 34
3141 13:28:35.749498 [Byte1]: 34
3142 13:28:35.754240
3143 13:28:35.754604 Set Vref, RX VrefLevel [Byte0]: 35
3144 13:28:35.757416 [Byte1]: 35
3145 13:28:35.762506
3146 13:28:35.762990 Set Vref, RX VrefLevel [Byte0]: 36
3147 13:28:35.765862 [Byte1]: 36
3148 13:28:35.770474
3149 13:28:35.770873 Set Vref, RX VrefLevel [Byte0]: 37
3150 13:28:35.773799 [Byte1]: 37
3151 13:28:35.777938
3152 13:28:35.778354 Set Vref, RX VrefLevel [Byte0]: 38
3153 13:28:35.781535 [Byte1]: 38
3154 13:28:35.785939
3155 13:28:35.786377 Set Vref, RX VrefLevel [Byte0]: 39
3156 13:28:35.789738 [Byte1]: 39
3157 13:28:35.794090
3158 13:28:35.794438 Set Vref, RX VrefLevel [Byte0]: 40
3159 13:28:35.797219 [Byte1]: 40
3160 13:28:35.802083
3161 13:28:35.802462 Set Vref, RX VrefLevel [Byte0]: 41
3162 13:28:35.805295 [Byte1]: 41
3163 13:28:35.810220
3164 13:28:35.810671 Set Vref, RX VrefLevel [Byte0]: 42
3165 13:28:35.813182 [Byte1]: 42
3166 13:28:35.818042
3167 13:28:35.818457 Set Vref, RX VrefLevel [Byte0]: 43
3168 13:28:35.820947 [Byte1]: 43
3169 13:28:35.826148
3170 13:28:35.826496 Set Vref, RX VrefLevel [Byte0]: 44
3171 13:28:35.829256 [Byte1]: 44
3172 13:28:35.833792
3173 13:28:35.834241 Set Vref, RX VrefLevel [Byte0]: 45
3174 13:28:35.836943 [Byte1]: 45
3175 13:28:35.842180
3176 13:28:35.842655 Set Vref, RX VrefLevel [Byte0]: 46
3177 13:28:35.845248 [Byte1]: 46
3178 13:28:35.849675
3179 13:28:35.850024 Set Vref, RX VrefLevel [Byte0]: 47
3180 13:28:35.853093 [Byte1]: 47
3181 13:28:35.857659
3182 13:28:35.858014 Set Vref, RX VrefLevel [Byte0]: 48
3183 13:28:35.860984 [Byte1]: 48
3184 13:28:35.865694
3185 13:28:35.866043 Set Vref, RX VrefLevel [Byte0]: 49
3186 13:28:35.868851 [Byte1]: 49
3187 13:28:35.874115
3188 13:28:35.874627 Set Vref, RX VrefLevel [Byte0]: 50
3189 13:28:35.876782 [Byte1]: 50
3190 13:28:35.881264
3191 13:28:35.881614 Set Vref, RX VrefLevel [Byte0]: 51
3192 13:28:35.884965 [Byte1]: 51
3193 13:28:35.889984
3194 13:28:35.890438 Set Vref, RX VrefLevel [Byte0]: 52
3195 13:28:35.893101 [Byte1]: 52
3196 13:28:35.897569
3197 13:28:35.898045 Set Vref, RX VrefLevel [Byte0]: 53
3198 13:28:35.900447 [Byte1]: 53
3199 13:28:35.905181
3200 13:28:35.908898 Set Vref, RX VrefLevel [Byte0]: 54
3201 13:28:35.911860 [Byte1]: 54
3202 13:28:35.912359
3203 13:28:35.919819 Set Vref, RX VrefLevel [Byte0]: 55
3204 13:28:35.920177 [Byte1]: 55
3205 13:28:35.920535
3206 13:28:35.921981 Set Vref, RX VrefLevel [Byte0]: 56
3207 13:28:35.924946 [Byte1]: 56
3208 13:28:35.929526
3209 13:28:35.929962 Set Vref, RX VrefLevel [Byte0]: 57
3210 13:28:35.932319 [Byte1]: 57
3211 13:28:35.937523
3212 13:28:35.937943 Set Vref, RX VrefLevel [Byte0]: 58
3213 13:28:35.940179 [Byte1]: 58
3214 13:28:35.945303
3215 13:28:35.945756 Set Vref, RX VrefLevel [Byte0]: 59
3216 13:28:35.948496 [Byte1]: 59
3217 13:28:35.953316
3218 13:28:35.953771 Set Vref, RX VrefLevel [Byte0]: 60
3219 13:28:35.956229 [Byte1]: 60
3220 13:28:35.961132
3221 13:28:35.961569 Set Vref, RX VrefLevel [Byte0]: 61
3222 13:28:35.964680 [Byte1]: 61
3223 13:28:35.969218
3224 13:28:35.969703 Set Vref, RX VrefLevel [Byte0]: 62
3225 13:28:35.972631 [Byte1]: 62
3226 13:28:35.977243
3227 13:28:35.977727 Set Vref, RX VrefLevel [Byte0]: 63
3228 13:28:35.980646 [Byte1]: 63
3229 13:28:35.985345
3230 13:28:35.985825 Set Vref, RX VrefLevel [Byte0]: 64
3231 13:28:35.988562 [Byte1]: 64
3232 13:28:35.993114
3233 13:28:35.993504 Set Vref, RX VrefLevel [Byte0]: 65
3234 13:28:35.996364 [Byte1]: 65
3235 13:28:36.001086
3236 13:28:36.001570 Final RX Vref Byte 0 = 52 to rank0
3237 13:28:36.004190 Final RX Vref Byte 1 = 48 to rank0
3238 13:28:36.007292 Final RX Vref Byte 0 = 52 to rank1
3239 13:28:36.011115 Final RX Vref Byte 1 = 48 to rank1==
3240 13:28:36.013969 Dram Type= 6, Freq= 0, CH_1, rank 0
3241 13:28:36.020758 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3242 13:28:36.021220 ==
3243 13:28:36.021501 DQS Delay:
3244 13:28:36.021743 DQS0 = 0, DQS1 = 0
3245 13:28:36.024204 DQM Delay:
3246 13:28:36.024727 DQM0 = 115, DQM1 = 105
3247 13:28:36.027951 DQ Delay:
3248 13:28:36.030964 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3249 13:28:36.034250 DQ4 =114, DQ5 =126, DQ6 =122, DQ7 =114
3250 13:28:36.037179 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3251 13:28:36.040466 DQ12 =114, DQ13 =116, DQ14 =116, DQ15 =114
3252 13:28:36.040855
3253 13:28:36.041130
3254 13:28:36.050621 [DQSOSCAuto] RK0, (LSB)MR18= 0x1212, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 403 ps
3255 13:28:36.051002 CH1 RK0: MR19=404, MR18=1212
3256 13:28:36.057276 CH1_RK0: MR19=0x404, MR18=0x1212, DQSOSC=403, MR23=63, INC=40, DEC=26
3257 13:28:36.057687
3258 13:28:36.060674 ----->DramcWriteLeveling(PI) begin...
3259 13:28:36.061026 ==
3260 13:28:36.063804 Dram Type= 6, Freq= 0, CH_1, rank 1
3261 13:28:36.067909 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3262 13:28:36.070422 ==
3263 13:28:36.074158 Write leveling (Byte 0): 21 => 21
3264 13:28:36.074629 Write leveling (Byte 1): 21 => 21
3265 13:28:36.077260 DramcWriteLeveling(PI) end<-----
3266 13:28:36.077607
3267 13:28:36.077857 ==
3268 13:28:36.080401 Dram Type= 6, Freq= 0, CH_1, rank 1
3269 13:28:36.087465 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3270 13:28:36.087912 ==
3271 13:28:36.090750 [Gating] SW mode calibration
3272 13:28:36.097622 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3273 13:28:36.100510 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3274 13:28:36.107041 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3275 13:28:36.111030 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3276 13:28:36.114343 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3277 13:28:36.117409 0 11 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 0)
3278 13:28:36.124309 0 11 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
3279 13:28:36.127348 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3280 13:28:36.130495 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3281 13:28:36.136853 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3282 13:28:36.140547 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3283 13:28:36.143376 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3284 13:28:36.150221 0 12 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3285 13:28:36.153996 0 12 12 | B1->B0 | 2323 3a3a | 0 1 | (0 0) (0 0)
3286 13:28:36.157268 0 12 16 | B1->B0 | 3535 4545 | 0 0 | (0 0) (0 0)
3287 13:28:36.164121 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3288 13:28:36.167193 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3289 13:28:36.170451 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3290 13:28:36.176941 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3291 13:28:36.180646 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3292 13:28:36.183708 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3293 13:28:36.190566 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3294 13:28:36.194080 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3295 13:28:36.197218 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3296 13:28:36.203613 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3297 13:28:36.207172 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3298 13:28:36.210240 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3299 13:28:36.216820 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3300 13:28:36.220685 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3301 13:28:36.223863 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3302 13:28:36.230392 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3303 13:28:36.233615 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3304 13:28:36.237246 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3305 13:28:36.240138 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3306 13:28:36.246840 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3307 13:28:36.250146 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3308 13:28:36.253423 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3309 13:28:36.259974 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3310 13:28:36.263223 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3311 13:28:36.266987 Total UI for P1: 0, mck2ui 16
3312 13:28:36.270176 best dqsien dly found for B0: ( 0, 15, 12)
3313 13:28:36.273572 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3314 13:28:36.280515 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3315 13:28:36.280857 Total UI for P1: 0, mck2ui 16
3316 13:28:36.287003 best dqsien dly found for B1: ( 0, 15, 18)
3317 13:28:36.290427 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3318 13:28:36.293290 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3319 13:28:36.293743
3320 13:28:36.296570 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3321 13:28:36.299881 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3322 13:28:36.303393 [Gating] SW calibration Done
3323 13:28:36.303735 ==
3324 13:28:36.306834 Dram Type= 6, Freq= 0, CH_1, rank 1
3325 13:28:36.310187 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3326 13:28:36.310626 ==
3327 13:28:36.313065 RX Vref Scan: 0
3328 13:28:36.313412
3329 13:28:36.313662 RX Vref 0 -> 0, step: 1
3330 13:28:36.313881
3331 13:28:36.317003 RX Delay -40 -> 252, step: 8
3332 13:28:36.320031 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3333 13:28:36.326628 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
3334 13:28:36.330441 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3335 13:28:36.333630 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3336 13:28:36.337372 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3337 13:28:36.340121 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3338 13:28:36.347439 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3339 13:28:36.350435 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3340 13:28:36.353382 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3341 13:28:36.356948 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3342 13:28:36.359661 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
3343 13:28:36.366548 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3344 13:28:36.369957 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3345 13:28:36.373457 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3346 13:28:36.376436 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3347 13:28:36.380325 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3348 13:28:36.380630 ==
3349 13:28:36.383520 Dram Type= 6, Freq= 0, CH_1, rank 1
3350 13:28:36.390595 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3351 13:28:36.391043 ==
3352 13:28:36.391316 DQS Delay:
3353 13:28:36.394091 DQS0 = 0, DQS1 = 0
3354 13:28:36.394507 DQM Delay:
3355 13:28:36.397438 DQM0 = 118, DQM1 = 108
3356 13:28:36.397884 DQ Delay:
3357 13:28:36.400685 DQ0 =119, DQ1 =115, DQ2 =107, DQ3 =119
3358 13:28:36.403585 DQ4 =119, DQ5 =127, DQ6 =123, DQ7 =119
3359 13:28:36.407114 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
3360 13:28:36.410240 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =115
3361 13:28:36.410639
3362 13:28:36.410913
3363 13:28:36.411135 ==
3364 13:28:36.413218 Dram Type= 6, Freq= 0, CH_1, rank 1
3365 13:28:36.416880 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3366 13:28:36.419800 ==
3367 13:28:36.420112
3368 13:28:36.420399
3369 13:28:36.420633 TX Vref Scan disable
3370 13:28:36.423579 == TX Byte 0 ==
3371 13:28:36.426781 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3372 13:28:36.430154 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3373 13:28:36.433299 == TX Byte 1 ==
3374 13:28:36.437150 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3375 13:28:36.439721 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3376 13:28:36.443579 ==
3377 13:28:36.444039 Dram Type= 6, Freq= 0, CH_1, rank 1
3378 13:28:36.449901 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3379 13:28:36.450355 ==
3380 13:28:36.460615 TX Vref=22, minBit 0, minWin=25, winSum=419
3381 13:28:36.464587 TX Vref=24, minBit 9, minWin=25, winSum=424
3382 13:28:36.467696 TX Vref=26, minBit 8, minWin=26, winSum=430
3383 13:28:36.471114 TX Vref=28, minBit 3, minWin=26, winSum=430
3384 13:28:36.474388 TX Vref=30, minBit 9, minWin=26, winSum=434
3385 13:28:36.477690 TX Vref=32, minBit 0, minWin=26, winSum=429
3386 13:28:36.484205 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 30
3387 13:28:36.484726
3388 13:28:36.488131 Final TX Range 1 Vref 30
3389 13:28:36.488668
3390 13:28:36.488984 ==
3391 13:28:36.491439 Dram Type= 6, Freq= 0, CH_1, rank 1
3392 13:28:36.494111 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3393 13:28:36.494497 ==
3394 13:28:36.494766
3395 13:28:36.495004
3396 13:28:36.497897 TX Vref Scan disable
3397 13:28:36.501297 == TX Byte 0 ==
3398 13:28:36.504344 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3399 13:28:36.507705 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3400 13:28:36.510754 == TX Byte 1 ==
3401 13:28:36.514071 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3402 13:28:36.517489 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3403 13:28:36.517867
3404 13:28:36.520936 [DATLAT]
3405 13:28:36.521350 Freq=1200, CH1 RK1
3406 13:28:36.521596
3407 13:28:36.524887 DATLAT Default: 0xc
3408 13:28:36.525453 0, 0xFFFF, sum = 0
3409 13:28:36.527721 1, 0xFFFF, sum = 0
3410 13:28:36.528209 2, 0xFFFF, sum = 0
3411 13:28:36.531114 3, 0xFFFF, sum = 0
3412 13:28:36.531484 4, 0xFFFF, sum = 0
3413 13:28:36.534388 5, 0xFFFF, sum = 0
3414 13:28:36.534878 6, 0xFFFF, sum = 0
3415 13:28:36.537714 7, 0xFFFF, sum = 0
3416 13:28:36.538189 8, 0xFFFF, sum = 0
3417 13:28:36.540938 9, 0xFFFF, sum = 0
3418 13:28:36.541413 10, 0xFFFF, sum = 0
3419 13:28:36.544430 11, 0x0, sum = 1
3420 13:28:36.544839 12, 0x0, sum = 2
3421 13:28:36.547505 13, 0x0, sum = 3
3422 13:28:36.547898 14, 0x0, sum = 4
3423 13:28:36.550933 best_step = 12
3424 13:28:36.551314
3425 13:28:36.551574 ==
3426 13:28:36.554246 Dram Type= 6, Freq= 0, CH_1, rank 1
3427 13:28:36.557897 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3428 13:28:36.558251 ==
3429 13:28:36.560999 RX Vref Scan: 0
3430 13:28:36.561351
3431 13:28:36.561599 RX Vref 0 -> 0, step: 1
3432 13:28:36.561821
3433 13:28:36.564181 RX Delay -21 -> 252, step: 4
3434 13:28:36.570931 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3435 13:28:36.574918 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3436 13:28:36.577859 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3437 13:28:36.580719 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3438 13:28:36.584078 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3439 13:28:36.590729 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3440 13:28:36.594567 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3441 13:28:36.597473 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144
3442 13:28:36.601067 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3443 13:28:36.604165 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3444 13:28:36.610655 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3445 13:28:36.613772 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3446 13:28:36.617701 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3447 13:28:36.621088 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3448 13:28:36.623693 iDelay=199, Bit 14, Center 114 (43 ~ 186) 144
3449 13:28:36.630526 iDelay=199, Bit 15, Center 112 (47 ~ 178) 132
3450 13:28:36.630596 ==
3451 13:28:36.633856 Dram Type= 6, Freq= 0, CH_1, rank 1
3452 13:28:36.637209 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3453 13:28:36.637275 ==
3454 13:28:36.637330 DQS Delay:
3455 13:28:36.640918 DQS0 = 0, DQS1 = 0
3456 13:28:36.640978 DQM Delay:
3457 13:28:36.643795 DQM0 = 115, DQM1 = 104
3458 13:28:36.643853 DQ Delay:
3459 13:28:36.647533 DQ0 =116, DQ1 =110, DQ2 =108, DQ3 =112
3460 13:28:36.650729 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3461 13:28:36.653994 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =98
3462 13:28:36.657343 DQ12 =112, DQ13 =112, DQ14 =114, DQ15 =112
3463 13:28:36.657708
3464 13:28:36.657970
3465 13:28:36.667881 [DQSOSCAuto] RK1, (LSB)MR18= 0x606, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
3466 13:28:36.671123 CH1 RK1: MR19=404, MR18=606
3467 13:28:36.674215 CH1_RK1: MR19=0x404, MR18=0x606, DQSOSC=407, MR23=63, INC=39, DEC=26
3468 13:28:36.677638 [RxdqsGatingPostProcess] freq 1200
3469 13:28:36.684032 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3470 13:28:36.687553 Pre-setting of DQS Precalculation
3471 13:28:36.691423 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3472 13:28:36.697444 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3473 13:28:36.708219 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3474 13:28:36.708728
3475 13:28:36.708999
3476 13:28:36.711032 [Calibration Summary] 2400 Mbps
3477 13:28:36.711388 CH 0, Rank 0
3478 13:28:36.714081 SW Impedance : PASS
3479 13:28:36.714375 DUTY Scan : NO K
3480 13:28:36.717956 ZQ Calibration : PASS
3481 13:28:36.718312 Jitter Meter : NO K
3482 13:28:36.721030 CBT Training : PASS
3483 13:28:36.724216 Write leveling : PASS
3484 13:28:36.724623 RX DQS gating : PASS
3485 13:28:36.727731 RX DQ/DQS(RDDQC) : PASS
3486 13:28:36.731335 TX DQ/DQS : PASS
3487 13:28:36.731755 RX DATLAT : PASS
3488 13:28:36.734563 RX DQ/DQS(Engine): PASS
3489 13:28:36.737866 TX OE : NO K
3490 13:28:36.738321 All Pass.
3491 13:28:36.738584
3492 13:28:36.738906 CH 0, Rank 1
3493 13:28:36.740692 SW Impedance : PASS
3494 13:28:36.743995 DUTY Scan : NO K
3495 13:28:36.744072 ZQ Calibration : PASS
3496 13:28:36.747178 Jitter Meter : NO K
3497 13:28:36.750777 CBT Training : PASS
3498 13:28:36.750890 Write leveling : PASS
3499 13:28:36.754146 RX DQS gating : PASS
3500 13:28:36.757666 RX DQ/DQS(RDDQC) : PASS
3501 13:28:36.757761 TX DQ/DQS : PASS
3502 13:28:36.761016 RX DATLAT : PASS
3503 13:28:36.761368 RX DQ/DQS(Engine): PASS
3504 13:28:36.764825 TX OE : NO K
3505 13:28:36.765176 All Pass.
3506 13:28:36.765434
3507 13:28:36.767958 CH 1, Rank 0
3508 13:28:36.768467 SW Impedance : PASS
3509 13:28:36.771047 DUTY Scan : NO K
3510 13:28:36.774646 ZQ Calibration : PASS
3511 13:28:36.775095 Jitter Meter : NO K
3512 13:28:36.778063 CBT Training : PASS
3513 13:28:36.780936 Write leveling : PASS
3514 13:28:36.781287 RX DQS gating : PASS
3515 13:28:36.784505 RX DQ/DQS(RDDQC) : PASS
3516 13:28:36.787825 TX DQ/DQS : PASS
3517 13:28:36.788190 RX DATLAT : PASS
3518 13:28:36.791356 RX DQ/DQS(Engine): PASS
3519 13:28:36.794632 TX OE : NO K
3520 13:28:36.794993 All Pass.
3521 13:28:36.795247
3522 13:28:36.795463 CH 1, Rank 1
3523 13:28:36.798221 SW Impedance : PASS
3524 13:28:36.801264 DUTY Scan : NO K
3525 13:28:36.801621 ZQ Calibration : PASS
3526 13:28:36.804271 Jitter Meter : NO K
3527 13:28:36.804660 CBT Training : PASS
3528 13:28:36.807788 Write leveling : PASS
3529 13:28:36.811148 RX DQS gating : PASS
3530 13:28:36.811504 RX DQ/DQS(RDDQC) : PASS
3531 13:28:36.814373 TX DQ/DQS : PASS
3532 13:28:36.818258 RX DATLAT : PASS
3533 13:28:36.818746 RX DQ/DQS(Engine): PASS
3534 13:28:36.821146 TX OE : NO K
3535 13:28:36.821504 All Pass.
3536 13:28:36.821852
3537 13:28:36.824597 DramC Write-DBI off
3538 13:28:36.827733 PER_BANK_REFRESH: Hybrid Mode
3539 13:28:36.828095 TX_TRACKING: ON
3540 13:28:36.838186 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3541 13:28:36.841048 [FAST_K] Save calibration result to emmc
3542 13:28:36.844155 dramc_set_vcore_voltage set vcore to 650000
3543 13:28:36.847531 Read voltage for 600, 5
3544 13:28:36.847882 Vio18 = 0
3545 13:28:36.848135 Vcore = 650000
3546 13:28:36.851251 Vdram = 0
3547 13:28:36.851787 Vddq = 0
3548 13:28:36.852061 Vmddr = 0
3549 13:28:36.858196 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3550 13:28:36.861187 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3551 13:28:36.864296 MEM_TYPE=3, freq_sel=19
3552 13:28:36.867855 sv_algorithm_assistance_LP4_1600
3553 13:28:36.871485 ============ PULL DRAM RESETB DOWN ============
3554 13:28:36.874782 ========== PULL DRAM RESETB DOWN end =========
3555 13:28:36.881328 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3556 13:28:36.884826 ===================================
3557 13:28:36.885309 LPDDR4 DRAM CONFIGURATION
3558 13:28:36.887900 ===================================
3559 13:28:36.891346 EX_ROW_EN[0] = 0x0
3560 13:28:36.894593 EX_ROW_EN[1] = 0x0
3561 13:28:36.894989 LP4Y_EN = 0x0
3562 13:28:36.898068 WORK_FSP = 0x0
3563 13:28:36.898483 WL = 0x2
3564 13:28:36.901131 RL = 0x2
3565 13:28:36.901616 BL = 0x2
3566 13:28:36.904632 RPST = 0x0
3567 13:28:36.905065 RD_PRE = 0x0
3568 13:28:36.907821 WR_PRE = 0x1
3569 13:28:36.908335 WR_PST = 0x0
3570 13:28:36.911379 DBI_WR = 0x0
3571 13:28:36.911848 DBI_RD = 0x0
3572 13:28:36.914427 OTF = 0x1
3573 13:28:36.917776 ===================================
3574 13:28:36.920903 ===================================
3575 13:28:36.921372 ANA top config
3576 13:28:36.924325 ===================================
3577 13:28:36.927644 DLL_ASYNC_EN = 0
3578 13:28:36.931327 ALL_SLAVE_EN = 1
3579 13:28:36.934402 NEW_RANK_MODE = 1
3580 13:28:36.934893 DLL_IDLE_MODE = 1
3581 13:28:36.937721 LP45_APHY_COMB_EN = 1
3582 13:28:36.941075 TX_ODT_DIS = 1
3583 13:28:36.944137 NEW_8X_MODE = 1
3584 13:28:36.947310 ===================================
3585 13:28:36.950763 ===================================
3586 13:28:36.954168 data_rate = 1200
3587 13:28:36.954532 CKR = 1
3588 13:28:36.957434 DQ_P2S_RATIO = 8
3589 13:28:36.961298 ===================================
3590 13:28:36.964363 CA_P2S_RATIO = 8
3591 13:28:36.967539 DQ_CA_OPEN = 0
3592 13:28:36.970667 DQ_SEMI_OPEN = 0
3593 13:28:36.973833 CA_SEMI_OPEN = 0
3594 13:28:36.974260 CA_FULL_RATE = 0
3595 13:28:36.977401 DQ_CKDIV4_EN = 1
3596 13:28:36.980679 CA_CKDIV4_EN = 1
3597 13:28:36.983861 CA_PREDIV_EN = 0
3598 13:28:36.987018 PH8_DLY = 0
3599 13:28:36.990515 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3600 13:28:36.990999 DQ_AAMCK_DIV = 4
3601 13:28:36.994099 CA_AAMCK_DIV = 4
3602 13:28:36.997140 CA_ADMCK_DIV = 4
3603 13:28:37.001006 DQ_TRACK_CA_EN = 0
3604 13:28:37.003741 CA_PICK = 600
3605 13:28:37.007315 CA_MCKIO = 600
3606 13:28:37.010429 MCKIO_SEMI = 0
3607 13:28:37.010830 PLL_FREQ = 2288
3608 13:28:37.013477 DQ_UI_PI_RATIO = 32
3609 13:28:37.016765 CA_UI_PI_RATIO = 0
3610 13:28:37.020416 ===================================
3611 13:28:37.023707 ===================================
3612 13:28:37.026743 memory_type:LPDDR4
3613 13:28:37.030736 GP_NUM : 10
3614 13:28:37.031182 SRAM_EN : 1
3615 13:28:37.033639 MD32_EN : 0
3616 13:28:37.036678 ===================================
3617 13:28:37.037092 [ANA_INIT] >>>>>>>>>>>>>>
3618 13:28:37.040259 <<<<<< [CONFIGURE PHASE]: ANA_TX
3619 13:28:37.043334 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3620 13:28:37.046593 ===================================
3621 13:28:37.049800 data_rate = 1200,PCW = 0X5800
3622 13:28:37.053165 ===================================
3623 13:28:37.057035 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3624 13:28:37.063032 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3625 13:28:37.069709 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3626 13:28:37.073355 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3627 13:28:37.077103 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3628 13:28:37.079750 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3629 13:28:37.083289 [ANA_INIT] flow start
3630 13:28:37.083643 [ANA_INIT] PLL >>>>>>>>
3631 13:28:37.086502 [ANA_INIT] PLL <<<<<<<<
3632 13:28:37.090065 [ANA_INIT] MIDPI >>>>>>>>
3633 13:28:37.090420 [ANA_INIT] MIDPI <<<<<<<<
3634 13:28:37.093069 [ANA_INIT] DLL >>>>>>>>
3635 13:28:37.096350 [ANA_INIT] flow end
3636 13:28:37.099521 ============ LP4 DIFF to SE enter ============
3637 13:28:37.103375 ============ LP4 DIFF to SE exit ============
3638 13:28:37.106621 [ANA_INIT] <<<<<<<<<<<<<
3639 13:28:37.109603 [Flow] Enable top DCM control >>>>>
3640 13:28:37.113091 [Flow] Enable top DCM control <<<<<
3641 13:28:37.116541 Enable DLL master slave shuffle
3642 13:28:37.119775 ==============================================================
3643 13:28:37.123026 Gating Mode config
3644 13:28:37.130049 ==============================================================
3645 13:28:37.130480 Config description:
3646 13:28:37.139348 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3647 13:28:37.145940 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3648 13:28:37.149474 SELPH_MODE 0: By rank 1: By Phase
3649 13:28:37.155822 ==============================================================
3650 13:28:37.159718 GAT_TRACK_EN = 1
3651 13:28:37.162694 RX_GATING_MODE = 2
3652 13:28:37.166534 RX_GATING_TRACK_MODE = 2
3653 13:28:37.169226 SELPH_MODE = 1
3654 13:28:37.172678 PICG_EARLY_EN = 1
3655 13:28:37.175629 VALID_LAT_VALUE = 1
3656 13:28:37.179537 ==============================================================
3657 13:28:37.182457 Enter into Gating configuration >>>>
3658 13:28:37.186037 Exit from Gating configuration <<<<
3659 13:28:37.189222 Enter into DVFS_PRE_config >>>>>
3660 13:28:37.202576 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3661 13:28:37.202987 Exit from DVFS_PRE_config <<<<<
3662 13:28:37.205773 Enter into PICG configuration >>>>
3663 13:28:37.209263 Exit from PICG configuration <<<<
3664 13:28:37.212544 [RX_INPUT] configuration >>>>>
3665 13:28:37.215796 [RX_INPUT] configuration <<<<<
3666 13:28:37.222301 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3667 13:28:37.226103 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3668 13:28:37.232383 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3669 13:28:37.239395 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3670 13:28:37.245564 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3671 13:28:37.252079 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3672 13:28:37.255730 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3673 13:28:37.259153 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3674 13:28:37.262589 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3675 13:28:37.269173 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3676 13:28:37.272408 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3677 13:28:37.276153 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3678 13:28:37.279275 ===================================
3679 13:28:37.282408 LPDDR4 DRAM CONFIGURATION
3680 13:28:37.285629 ===================================
3681 13:28:37.286022 EX_ROW_EN[0] = 0x0
3682 13:28:37.289752 EX_ROW_EN[1] = 0x0
3683 13:28:37.292357 LP4Y_EN = 0x0
3684 13:28:37.292867 WORK_FSP = 0x0
3685 13:28:37.295462 WL = 0x2
3686 13:28:37.295847 RL = 0x2
3687 13:28:37.299134 BL = 0x2
3688 13:28:37.299641 RPST = 0x0
3689 13:28:37.302141 RD_PRE = 0x0
3690 13:28:37.302533 WR_PRE = 0x1
3691 13:28:37.305072 WR_PST = 0x0
3692 13:28:37.305338 DBI_WR = 0x0
3693 13:28:37.309058 DBI_RD = 0x0
3694 13:28:37.309522 OTF = 0x1
3695 13:28:37.312349 ===================================
3696 13:28:37.315240 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3697 13:28:37.322025 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3698 13:28:37.325139 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3699 13:28:37.328166 ===================================
3700 13:28:37.331497 LPDDR4 DRAM CONFIGURATION
3701 13:28:37.335289 ===================================
3702 13:28:37.335643 EX_ROW_EN[0] = 0x10
3703 13:28:37.338581 EX_ROW_EN[1] = 0x0
3704 13:28:37.341626 LP4Y_EN = 0x0
3705 13:28:37.341999 WORK_FSP = 0x0
3706 13:28:37.345332 WL = 0x2
3707 13:28:37.345685 RL = 0x2
3708 13:28:37.347916 BL = 0x2
3709 13:28:37.348270 RPST = 0x0
3710 13:28:37.351316 RD_PRE = 0x0
3711 13:28:37.351667 WR_PRE = 0x1
3712 13:28:37.354776 WR_PST = 0x0
3713 13:28:37.355143 DBI_WR = 0x0
3714 13:28:37.358228 DBI_RD = 0x0
3715 13:28:37.358577 OTF = 0x1
3716 13:28:37.361390 ===================================
3717 13:28:37.368266 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3718 13:28:37.372179 nWR fixed to 30
3719 13:28:37.375854 [ModeRegInit_LP4] CH0 RK0
3720 13:28:37.376204 [ModeRegInit_LP4] CH0 RK1
3721 13:28:37.379545 [ModeRegInit_LP4] CH1 RK0
3722 13:28:37.382330 [ModeRegInit_LP4] CH1 RK1
3723 13:28:37.382681 match AC timing 16
3724 13:28:37.389554 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3725 13:28:37.392743 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3726 13:28:37.395578 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3727 13:28:37.402415 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3728 13:28:37.405612 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3729 13:28:37.405970 ==
3730 13:28:37.408941 Dram Type= 6, Freq= 0, CH_0, rank 0
3731 13:28:37.412208 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3732 13:28:37.412763 ==
3733 13:28:37.418754 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3734 13:28:37.425333 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3735 13:28:37.428636 [CA 0] Center 36 (6~66) winsize 61
3736 13:28:37.432246 [CA 1] Center 36 (6~66) winsize 61
3737 13:28:37.435417 [CA 2] Center 34 (4~65) winsize 62
3738 13:28:37.438501 [CA 3] Center 34 (3~65) winsize 63
3739 13:28:37.442205 [CA 4] Center 33 (3~64) winsize 62
3740 13:28:37.445431 [CA 5] Center 33 (3~64) winsize 62
3741 13:28:37.445746
3742 13:28:37.448863 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3743 13:28:37.449209
3744 13:28:37.451740 [CATrainingPosCal] consider 1 rank data
3745 13:28:37.455329 u2DelayCellTimex100 = 270/100 ps
3746 13:28:37.458461 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3747 13:28:37.461868 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3748 13:28:37.465689 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3749 13:28:37.468372 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3750 13:28:37.475029 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3751 13:28:37.478509 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3752 13:28:37.478895
3753 13:28:37.482102 CA PerBit enable=1, Macro0, CA PI delay=33
3754 13:28:37.482569
3755 13:28:37.484848 [CBTSetCACLKResult] CA Dly = 33
3756 13:28:37.485193 CS Dly: 4 (0~35)
3757 13:28:37.485440 ==
3758 13:28:37.488253 Dram Type= 6, Freq= 0, CH_0, rank 1
3759 13:28:37.495362 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3760 13:28:37.495820 ==
3761 13:28:37.498345 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3762 13:28:37.505213 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3763 13:28:37.508126 [CA 0] Center 36 (6~66) winsize 61
3764 13:28:37.511472 [CA 1] Center 35 (5~66) winsize 62
3765 13:28:37.514696 [CA 2] Center 34 (4~65) winsize 62
3766 13:28:37.517953 [CA 3] Center 34 (3~65) winsize 63
3767 13:28:37.521372 [CA 4] Center 33 (3~64) winsize 62
3768 13:28:37.524762 [CA 5] Center 33 (3~64) winsize 62
3769 13:28:37.525108
3770 13:28:37.527947 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3771 13:28:37.528320
3772 13:28:37.531752 [CATrainingPosCal] consider 2 rank data
3773 13:28:37.534535 u2DelayCellTimex100 = 270/100 ps
3774 13:28:37.538454 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3775 13:28:37.541523 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3776 13:28:37.544693 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3777 13:28:37.551089 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3778 13:28:37.554467 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3779 13:28:37.558337 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3780 13:28:37.558680
3781 13:28:37.561520 CA PerBit enable=1, Macro0, CA PI delay=33
3782 13:28:37.561863
3783 13:28:37.564527 [CBTSetCACLKResult] CA Dly = 33
3784 13:28:37.564868 CS Dly: 4 (0~35)
3785 13:28:37.565109
3786 13:28:37.567896 ----->DramcWriteLeveling(PI) begin...
3787 13:28:37.571398 ==
3788 13:28:37.571746 Dram Type= 6, Freq= 0, CH_0, rank 0
3789 13:28:37.578139 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3790 13:28:37.578617 ==
3791 13:28:37.581225 Write leveling (Byte 0): 30 => 30
3792 13:28:37.584724 Write leveling (Byte 1): 29 => 29
3793 13:28:37.587842 DramcWriteLeveling(PI) end<-----
3794 13:28:37.588186
3795 13:28:37.588463 ==
3796 13:28:37.591322 Dram Type= 6, Freq= 0, CH_0, rank 0
3797 13:28:37.594126 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3798 13:28:37.594526 ==
3799 13:28:37.597661 [Gating] SW mode calibration
3800 13:28:37.604244 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3801 13:28:37.607960 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3802 13:28:37.614217 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3803 13:28:37.617439 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3804 13:28:37.620907 0 5 8 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 1)
3805 13:28:37.627817 0 5 12 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
3806 13:28:37.631174 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3807 13:28:37.634200 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3808 13:28:37.641101 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3809 13:28:37.643922 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3810 13:28:37.647256 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3811 13:28:37.654296 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3812 13:28:37.657265 0 6 8 | B1->B0 | 2b2b 2f2f | 0 0 | (0 0) (0 0)
3813 13:28:37.660765 0 6 12 | B1->B0 | 4141 4646 | 0 0 | (1 1) (0 0)
3814 13:28:37.667168 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3815 13:28:37.670861 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3816 13:28:37.673805 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3817 13:28:37.680579 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3818 13:28:37.683969 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3819 13:28:37.686891 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3820 13:28:37.693996 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3821 13:28:37.697338 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3822 13:28:37.700410 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3823 13:28:37.707076 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3824 13:28:37.710437 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3825 13:28:37.713561 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3826 13:28:37.720042 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3827 13:28:37.723790 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3828 13:28:37.726605 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3829 13:28:37.734165 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3830 13:28:37.736910 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3831 13:28:37.740016 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3832 13:28:37.746945 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3833 13:28:37.749993 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3834 13:28:37.753807 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3835 13:28:37.760073 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3836 13:28:37.763321 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3837 13:28:37.766539 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3838 13:28:37.770273 Total UI for P1: 0, mck2ui 16
3839 13:28:37.773401 best dqsien dly found for B0: ( 0, 9, 10)
3840 13:28:37.777218 Total UI for P1: 0, mck2ui 16
3841 13:28:37.780041 best dqsien dly found for B1: ( 0, 9, 10)
3842 13:28:37.783303 best DQS0 dly(MCK, UI, PI) = (0, 9, 10)
3843 13:28:37.786734 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
3844 13:28:37.787159
3845 13:28:37.790245 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10)
3846 13:28:37.796417 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
3847 13:28:37.796766 [Gating] SW calibration Done
3848 13:28:37.799900 ==
3849 13:28:37.800244 Dram Type= 6, Freq= 0, CH_0, rank 0
3850 13:28:37.806504 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3851 13:28:37.806970 ==
3852 13:28:37.807225 RX Vref Scan: 0
3853 13:28:37.807452
3854 13:28:37.809973 RX Vref 0 -> 0, step: 1
3855 13:28:37.810540
3856 13:28:37.813164 RX Delay -230 -> 252, step: 16
3857 13:28:37.816179 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3858 13:28:37.819822 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
3859 13:28:37.826490 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
3860 13:28:37.830244 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3861 13:28:37.833534 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3862 13:28:37.836739 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3863 13:28:37.839922 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3864 13:28:37.845996 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3865 13:28:37.850049 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3866 13:28:37.853544 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
3867 13:28:37.856245 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3868 13:28:37.863229 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3869 13:28:37.866312 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3870 13:28:37.869796 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3871 13:28:37.873293 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3872 13:28:37.879824 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3873 13:28:37.880351 ==
3874 13:28:37.883538 Dram Type= 6, Freq= 0, CH_0, rank 0
3875 13:28:37.886098 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3876 13:28:37.886546 ==
3877 13:28:37.886871 DQS Delay:
3878 13:28:37.889704 DQS0 = 0, DQS1 = 0
3879 13:28:37.890066 DQM Delay:
3880 13:28:37.892918 DQM0 = 40, DQM1 = 34
3881 13:28:37.893268 DQ Delay:
3882 13:28:37.895948 DQ0 =33, DQ1 =41, DQ2 =41, DQ3 =33
3883 13:28:37.899753 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3884 13:28:37.902806 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
3885 13:28:37.906479 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3886 13:28:37.906832
3887 13:28:37.907086
3888 13:28:37.907309 ==
3889 13:28:37.909421 Dram Type= 6, Freq= 0, CH_0, rank 0
3890 13:28:37.912549 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3891 13:28:37.912909 ==
3892 13:28:37.913192
3893 13:28:37.913424
3894 13:28:37.916071 TX Vref Scan disable
3895 13:28:37.919442 == TX Byte 0 ==
3896 13:28:37.922667 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3897 13:28:37.925923 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3898 13:28:37.929681 == TX Byte 1 ==
3899 13:28:37.932805 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3900 13:28:37.935917 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3901 13:28:37.936438 ==
3902 13:28:37.939717 Dram Type= 6, Freq= 0, CH_0, rank 0
3903 13:28:37.946278 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3904 13:28:37.946790 ==
3905 13:28:37.947071
3906 13:28:37.947295
3907 13:28:37.947505 TX Vref Scan disable
3908 13:28:37.950151 == TX Byte 0 ==
3909 13:28:37.953580 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3910 13:28:37.960102 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3911 13:28:37.960490 == TX Byte 1 ==
3912 13:28:37.963712 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3913 13:28:37.969934 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3914 13:28:37.970319
3915 13:28:37.970603 [DATLAT]
3916 13:28:37.970833 Freq=600, CH0 RK0
3917 13:28:37.971047
3918 13:28:37.973432 DATLAT Default: 0x9
3919 13:28:37.973781 0, 0xFFFF, sum = 0
3920 13:28:37.976751 1, 0xFFFF, sum = 0
3921 13:28:37.977179 2, 0xFFFF, sum = 0
3922 13:28:37.979987 3, 0xFFFF, sum = 0
3923 13:28:37.983394 4, 0xFFFF, sum = 0
3924 13:28:37.983747 5, 0xFFFF, sum = 0
3925 13:28:37.986937 6, 0xFFFF, sum = 0
3926 13:28:37.987230 7, 0x0, sum = 1
3927 13:28:37.987458 8, 0x0, sum = 2
3928 13:28:37.990301 9, 0x0, sum = 3
3929 13:28:37.990785 10, 0x0, sum = 4
3930 13:28:37.993707 best_step = 8
3931 13:28:37.994062
3932 13:28:37.994309 ==
3933 13:28:37.996346 Dram Type= 6, Freq= 0, CH_0, rank 0
3934 13:28:38.000137 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3935 13:28:38.000460 ==
3936 13:28:38.003273 RX Vref Scan: 1
3937 13:28:38.003624
3938 13:28:38.003876 RX Vref 0 -> 0, step: 1
3939 13:28:38.004097
3940 13:28:38.006660 RX Delay -179 -> 252, step: 8
3941 13:28:38.007034
3942 13:28:38.010021 Set Vref, RX VrefLevel [Byte0]: 47
3943 13:28:38.013226 [Byte1]: 48
3944 13:28:38.017147
3945 13:28:38.017494 Final RX Vref Byte 0 = 47 to rank0
3946 13:28:38.020829 Final RX Vref Byte 1 = 48 to rank0
3947 13:28:38.023834 Final RX Vref Byte 0 = 47 to rank1
3948 13:28:38.026864 Final RX Vref Byte 1 = 48 to rank1==
3949 13:28:38.030751 Dram Type= 6, Freq= 0, CH_0, rank 0
3950 13:28:38.037561 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3951 13:28:38.038025 ==
3952 13:28:38.038295 DQS Delay:
3953 13:28:38.038517 DQS0 = 0, DQS1 = 0
3954 13:28:38.041113 DQM Delay:
3955 13:28:38.041642 DQM0 = 40, DQM1 = 30
3956 13:28:38.044020 DQ Delay:
3957 13:28:38.047167 DQ0 =36, DQ1 =40, DQ2 =36, DQ3 =36
3958 13:28:38.050641 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =52
3959 13:28:38.053446 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
3960 13:28:38.056986 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
3961 13:28:38.057306
3962 13:28:38.057524
3963 13:28:38.063333 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f4f, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
3964 13:28:38.066733 CH0 RK0: MR19=808, MR18=4F4F
3965 13:28:38.073687 CH0_RK0: MR19=0x808, MR18=0x4F4F, DQSOSC=394, MR23=63, INC=168, DEC=112
3966 13:28:38.074045
3967 13:28:38.077006 ----->DramcWriteLeveling(PI) begin...
3968 13:28:38.077363 ==
3969 13:28:38.079863 Dram Type= 6, Freq= 0, CH_0, rank 1
3970 13:28:38.083666 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3971 13:28:38.084130 ==
3972 13:28:38.086705 Write leveling (Byte 0): 31 => 31
3973 13:28:38.090352 Write leveling (Byte 1): 30 => 30
3974 13:28:38.093347 DramcWriteLeveling(PI) end<-----
3975 13:28:38.093698
3976 13:28:38.093951 ==
3977 13:28:38.096858 Dram Type= 6, Freq= 0, CH_0, rank 1
3978 13:28:38.099963 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3979 13:28:38.100454 ==
3980 13:28:38.103549 [Gating] SW mode calibration
3981 13:28:38.110206 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3982 13:28:38.116617 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3983 13:28:38.120050 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3984 13:28:38.126614 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3985 13:28:38.130601 0 5 8 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (0 0)
3986 13:28:38.133437 0 5 12 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
3987 13:28:38.139697 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 13:28:38.143348 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 13:28:38.146762 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 13:28:38.153567 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 13:28:38.156982 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 13:28:38.159760 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3993 13:28:38.166708 0 6 8 | B1->B0 | 2626 3737 | 0 0 | (0 0) (0 0)
3994 13:28:38.169856 0 6 12 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3995 13:28:38.172810 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 13:28:38.175941 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 13:28:38.183393 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 13:28:38.186703 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 13:28:38.189474 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 13:28:38.196398 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 13:28:38.199717 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4002 13:28:38.203050 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4003 13:28:38.209239 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 13:28:38.212880 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 13:28:38.215752 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 13:28:38.223134 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 13:28:38.225575 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 13:28:38.229807 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 13:28:38.236008 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 13:28:38.239856 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 13:28:38.243151 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 13:28:38.248961 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 13:28:38.252437 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 13:28:38.255975 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 13:28:38.262557 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 13:28:38.265844 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4017 13:28:38.268772 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4018 13:28:38.275627 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4019 13:28:38.275949 Total UI for P1: 0, mck2ui 16
4020 13:28:38.282414 best dqsien dly found for B0: ( 0, 9, 8)
4021 13:28:38.286076 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 13:28:38.288775 Total UI for P1: 0, mck2ui 16
4023 13:28:38.292259 best dqsien dly found for B1: ( 0, 9, 8)
4024 13:28:38.295527 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4025 13:28:38.299045 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4026 13:28:38.299484
4027 13:28:38.302320 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4028 13:28:38.305906 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4029 13:28:38.308564 [Gating] SW calibration Done
4030 13:28:38.308938 ==
4031 13:28:38.312220 Dram Type= 6, Freq= 0, CH_0, rank 1
4032 13:28:38.315610 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4033 13:28:38.315990 ==
4034 13:28:38.318797 RX Vref Scan: 0
4035 13:28:38.319146
4036 13:28:38.322314 RX Vref 0 -> 0, step: 1
4037 13:28:38.322665
4038 13:28:38.322913 RX Delay -230 -> 252, step: 16
4039 13:28:38.329468 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4040 13:28:38.332710 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4041 13:28:38.335710 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4042 13:28:38.339025 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4043 13:28:38.346083 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4044 13:28:38.348937 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4045 13:28:38.352749 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4046 13:28:38.355062 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4047 13:28:38.362464 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4048 13:28:38.365639 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4049 13:28:38.368686 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4050 13:28:38.371691 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4051 13:28:38.378911 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4052 13:28:38.381612 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4053 13:28:38.385446 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4054 13:28:38.388518 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4055 13:28:38.388908 ==
4056 13:28:38.391940 Dram Type= 6, Freq= 0, CH_0, rank 1
4057 13:28:38.398476 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4058 13:28:38.399011 ==
4059 13:28:38.399368 DQS Delay:
4060 13:28:38.401566 DQS0 = 0, DQS1 = 0
4061 13:28:38.401918 DQM Delay:
4062 13:28:38.402172 DQM0 = 41, DQM1 = 33
4063 13:28:38.404990 DQ Delay:
4064 13:28:38.408362 DQ0 =33, DQ1 =49, DQ2 =33, DQ3 =33
4065 13:28:38.411796 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4066 13:28:38.414531 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4067 13:28:38.418083 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4068 13:28:38.418485
4069 13:28:38.418755
4070 13:28:38.419001 ==
4071 13:28:38.421232 Dram Type= 6, Freq= 0, CH_0, rank 1
4072 13:28:38.424778 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4073 13:28:38.425134 ==
4074 13:28:38.425379
4075 13:28:38.425597
4076 13:28:38.428207 TX Vref Scan disable
4077 13:28:38.431086 == TX Byte 0 ==
4078 13:28:38.434754 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4079 13:28:38.437816 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4080 13:28:38.441373 == TX Byte 1 ==
4081 13:28:38.444297 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4082 13:28:38.447843 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4083 13:28:38.448196 ==
4084 13:28:38.451024 Dram Type= 6, Freq= 0, CH_0, rank 1
4085 13:28:38.454694 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4086 13:28:38.457831 ==
4087 13:28:38.458180
4088 13:28:38.458429
4089 13:28:38.458648 TX Vref Scan disable
4090 13:28:38.461885 == TX Byte 0 ==
4091 13:28:38.465037 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4092 13:28:38.471517 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4093 13:28:38.471869 == TX Byte 1 ==
4094 13:28:38.475131 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4095 13:28:38.481288 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4096 13:28:38.481698
4097 13:28:38.481955 [DATLAT]
4098 13:28:38.482176 Freq=600, CH0 RK1
4099 13:28:38.482391
4100 13:28:38.485130 DATLAT Default: 0x8
4101 13:28:38.485477 0, 0xFFFF, sum = 0
4102 13:28:38.487765 1, 0xFFFF, sum = 0
4103 13:28:38.491275 2, 0xFFFF, sum = 0
4104 13:28:38.491643 3, 0xFFFF, sum = 0
4105 13:28:38.494725 4, 0xFFFF, sum = 0
4106 13:28:38.495145 5, 0xFFFF, sum = 0
4107 13:28:38.498306 6, 0xFFFF, sum = 0
4108 13:28:38.498661 7, 0x0, sum = 1
4109 13:28:38.498921 8, 0x0, sum = 2
4110 13:28:38.501257 9, 0x0, sum = 3
4111 13:28:38.501612 10, 0x0, sum = 4
4112 13:28:38.504524 best_step = 8
4113 13:28:38.504871
4114 13:28:38.505125 ==
4115 13:28:38.507888 Dram Type= 6, Freq= 0, CH_0, rank 1
4116 13:28:38.511245 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4117 13:28:38.511702 ==
4118 13:28:38.514893 RX Vref Scan: 0
4119 13:28:38.515243
4120 13:28:38.515492 RX Vref 0 -> 0, step: 1
4121 13:28:38.517818
4122 13:28:38.518166 RX Delay -195 -> 252, step: 8
4123 13:28:38.525170 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4124 13:28:38.528401 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320
4125 13:28:38.532001 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4126 13:28:38.535118 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4127 13:28:38.541912 iDelay=205, Bit 4, Center 48 (-107 ~ 204) 312
4128 13:28:38.544944 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4129 13:28:38.549079 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4130 13:28:38.551559 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4131 13:28:38.554709 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4132 13:28:38.561640 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4133 13:28:38.564606 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4134 13:28:38.568687 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4135 13:28:38.572109 iDelay=205, Bit 12, Center 36 (-115 ~ 188) 304
4136 13:28:38.578236 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4137 13:28:38.581219 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4138 13:28:38.584721 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4139 13:28:38.585075 ==
4140 13:28:38.588361 Dram Type= 6, Freq= 0, CH_0, rank 1
4141 13:28:38.595340 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4142 13:28:38.595827 ==
4143 13:28:38.596125 DQS Delay:
4144 13:28:38.596421 DQS0 = 0, DQS1 = 0
4145 13:28:38.597863 DQM Delay:
4146 13:28:38.598236 DQM0 = 41, DQM1 = 32
4147 13:28:38.601300 DQ Delay:
4148 13:28:38.605037 DQ0 =36, DQ1 =44, DQ2 =40, DQ3 =36
4149 13:28:38.608070 DQ4 =48, DQ5 =32, DQ6 =48, DQ7 =48
4150 13:28:38.610878 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4151 13:28:38.614421 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =44
4152 13:28:38.614771
4153 13:28:38.615058
4154 13:28:38.621538 [DQSOSCAuto] RK1, (LSB)MR18= 0x6d6d, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4155 13:28:38.624599 CH0 RK1: MR19=808, MR18=6D6D
4156 13:28:38.630936 CH0_RK1: MR19=0x808, MR18=0x6D6D, DQSOSC=389, MR23=63, INC=173, DEC=115
4157 13:28:38.634377 [RxdqsGatingPostProcess] freq 600
4158 13:28:38.638038 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4159 13:28:38.641089 Pre-setting of DQS Precalculation
4160 13:28:38.648025 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4161 13:28:38.648576 ==
4162 13:28:38.651312 Dram Type= 6, Freq= 0, CH_1, rank 0
4163 13:28:38.654148 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4164 13:28:38.654536 ==
4165 13:28:38.661015 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4166 13:28:38.667813 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4167 13:28:38.671288 [CA 0] Center 35 (5~66) winsize 62
4168 13:28:38.673994 [CA 1] Center 35 (5~66) winsize 62
4169 13:28:38.677833 [CA 2] Center 33 (3~64) winsize 62
4170 13:28:38.680514 [CA 3] Center 33 (3~64) winsize 62
4171 13:28:38.683750 [CA 4] Center 33 (2~64) winsize 63
4172 13:28:38.687591 [CA 5] Center 33 (2~64) winsize 63
4173 13:28:38.688085
4174 13:28:38.690534 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4175 13:28:38.690887
4176 13:28:38.694721 [CATrainingPosCal] consider 1 rank data
4177 13:28:38.697618 u2DelayCellTimex100 = 270/100 ps
4178 13:28:38.700908 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4179 13:28:38.704400 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4180 13:28:38.707461 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4181 13:28:38.710747 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4182 13:28:38.713881 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4183 13:28:38.716869 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4184 13:28:38.717316
4185 13:28:38.720659 CA PerBit enable=1, Macro0, CA PI delay=33
4186 13:28:38.724096
4187 13:28:38.724634 [CBTSetCACLKResult] CA Dly = 33
4188 13:28:38.727464 CS Dly: 5 (0~36)
4189 13:28:38.727864 ==
4190 13:28:38.730734 Dram Type= 6, Freq= 0, CH_1, rank 1
4191 13:28:38.734006 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4192 13:28:38.734494 ==
4193 13:28:38.740920 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4194 13:28:38.746764 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4195 13:28:38.750123 [CA 0] Center 35 (4~66) winsize 63
4196 13:28:38.753885 [CA 1] Center 34 (4~65) winsize 62
4197 13:28:38.756676 [CA 2] Center 33 (3~64) winsize 62
4198 13:28:38.760190 [CA 3] Center 33 (3~64) winsize 62
4199 13:28:38.763204 [CA 4] Center 32 (2~63) winsize 62
4200 13:28:38.766661 [CA 5] Center 32 (2~63) winsize 62
4201 13:28:38.767012
4202 13:28:38.769822 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4203 13:28:38.770175
4204 13:28:38.773528 [CATrainingPosCal] consider 2 rank data
4205 13:28:38.776617 u2DelayCellTimex100 = 270/100 ps
4206 13:28:38.779819 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4207 13:28:38.783816 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4208 13:28:38.787172 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4209 13:28:38.789920 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4210 13:28:38.793470 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4211 13:28:38.796855 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4212 13:28:38.797313
4213 13:28:38.803204 CA PerBit enable=1, Macro0, CA PI delay=32
4214 13:28:38.803666
4215 13:28:38.806925 [CBTSetCACLKResult] CA Dly = 32
4216 13:28:38.807371 CS Dly: 5 (0~36)
4217 13:28:38.807624
4218 13:28:38.809909 ----->DramcWriteLeveling(PI) begin...
4219 13:28:38.810326 ==
4220 13:28:38.813550 Dram Type= 6, Freq= 0, CH_1, rank 0
4221 13:28:38.816430 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4222 13:28:38.819530 ==
4223 13:28:38.819879 Write leveling (Byte 0): 26 => 26
4224 13:28:38.823118 Write leveling (Byte 1): 26 => 26
4225 13:28:38.826465 DramcWriteLeveling(PI) end<-----
4226 13:28:38.826841
4227 13:28:38.827094 ==
4228 13:28:38.829713 Dram Type= 6, Freq= 0, CH_1, rank 0
4229 13:28:38.836386 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4230 13:28:38.836843 ==
4231 13:28:38.839825 [Gating] SW mode calibration
4232 13:28:38.846342 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4233 13:28:38.849603 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4234 13:28:38.855968 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4235 13:28:38.859448 0 5 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (1 0)
4236 13:28:38.862773 0 5 8 | B1->B0 | 2f2f 2525 | 0 0 | (0 1) (0 0)
4237 13:28:38.869661 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4238 13:28:38.872701 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 13:28:38.875726 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 13:28:38.882531 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 13:28:38.885902 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4242 13:28:38.889263 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4243 13:28:38.892358 0 6 4 | B1->B0 | 2424 2727 | 0 0 | (0 0) (1 1)
4244 13:28:38.899310 0 6 8 | B1->B0 | 3434 3f3f | 0 1 | (0 0) (0 0)
4245 13:28:38.902434 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 13:28:38.905892 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 13:28:38.912622 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 13:28:38.915635 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 13:28:38.918867 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4250 13:28:38.925614 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 13:28:38.928697 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 13:28:38.932323 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4253 13:28:38.938699 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4254 13:28:38.942151 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 13:28:38.945881 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 13:28:38.952169 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 13:28:38.955060 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 13:28:38.958492 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 13:28:38.965596 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 13:28:38.968730 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 13:28:38.971965 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 13:28:38.978676 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 13:28:38.981917 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 13:28:38.985231 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 13:28:38.991756 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 13:28:38.995241 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 13:28:38.998899 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 13:28:39.005645 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4269 13:28:39.008345 Total UI for P1: 0, mck2ui 16
4270 13:28:39.011998 best dqsien dly found for B0: ( 0, 9, 6)
4271 13:28:39.012451 Total UI for P1: 0, mck2ui 16
4272 13:28:39.018274 best dqsien dly found for B1: ( 0, 9, 6)
4273 13:28:39.021509 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4274 13:28:39.024937 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4275 13:28:39.025282
4276 13:28:39.029062 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4277 13:28:39.031633 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4278 13:28:39.034893 [Gating] SW calibration Done
4279 13:28:39.035348 ==
4280 13:28:39.038473 Dram Type= 6, Freq= 0, CH_1, rank 0
4281 13:28:39.041644 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4282 13:28:39.041993 ==
4283 13:28:39.045181 RX Vref Scan: 0
4284 13:28:39.045597
4285 13:28:39.045947 RX Vref 0 -> 0, step: 1
4286 13:28:39.046183
4287 13:28:39.047936 RX Delay -230 -> 252, step: 16
4288 13:28:39.054471 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4289 13:28:39.058166 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4290 13:28:39.061650 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4291 13:28:39.064742 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4292 13:28:39.068320 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4293 13:28:39.074717 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4294 13:28:39.078051 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4295 13:28:39.081373 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4296 13:28:39.084800 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4297 13:28:39.090829 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4298 13:28:39.094640 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4299 13:28:39.097819 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4300 13:28:39.101626 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4301 13:28:39.104359 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4302 13:28:39.111893 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4303 13:28:39.114506 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4304 13:28:39.114977 ==
4305 13:28:39.117314 Dram Type= 6, Freq= 0, CH_1, rank 0
4306 13:28:39.120766 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4307 13:28:39.121168 ==
4308 13:28:39.124454 DQS Delay:
4309 13:28:39.124841 DQS0 = 0, DQS1 = 0
4310 13:28:39.127681 DQM Delay:
4311 13:28:39.128064 DQM0 = 39, DQM1 = 30
4312 13:28:39.128345 DQ Delay:
4313 13:28:39.130892 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4314 13:28:39.134715 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4315 13:28:39.137650 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4316 13:28:39.141021 DQ12 =33, DQ13 =49, DQ14 =33, DQ15 =41
4317 13:28:39.141287
4318 13:28:39.141473
4319 13:28:39.144266 ==
4320 13:28:39.144646 Dram Type= 6, Freq= 0, CH_1, rank 0
4321 13:28:39.151369 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4322 13:28:39.151853 ==
4323 13:28:39.152158
4324 13:28:39.152513
4325 13:28:39.154129 TX Vref Scan disable
4326 13:28:39.154417 == TX Byte 0 ==
4327 13:28:39.157547 Update DQ dly =570 (2 ,1, 26) DQ OEN =(1 ,6)
4328 13:28:39.163868 Update DQM dly =570 (2 ,1, 26) DQM OEN =(1 ,6)
4329 13:28:39.164305 == TX Byte 1 ==
4330 13:28:39.167528 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4331 13:28:39.174324 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4332 13:28:39.174964 ==
4333 13:28:39.177536 Dram Type= 6, Freq= 0, CH_1, rank 0
4334 13:28:39.180653 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4335 13:28:39.180956 ==
4336 13:28:39.181189
4337 13:28:39.181404
4338 13:28:39.183688 TX Vref Scan disable
4339 13:28:39.187233 == TX Byte 0 ==
4340 13:28:39.190786 Update DQ dly =570 (2 ,1, 26) DQ OEN =(1 ,6)
4341 13:28:39.194369 Update DQM dly =570 (2 ,1, 26) DQM OEN =(1 ,6)
4342 13:28:39.197269 == TX Byte 1 ==
4343 13:28:39.201182 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4344 13:28:39.203975 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4345 13:28:39.204368
4346 13:28:39.207294 [DATLAT]
4347 13:28:39.207676 Freq=600, CH1 RK0
4348 13:28:39.207923
4349 13:28:39.210734 DATLAT Default: 0x9
4350 13:28:39.211077 0, 0xFFFF, sum = 0
4351 13:28:39.214475 1, 0xFFFF, sum = 0
4352 13:28:39.214935 2, 0xFFFF, sum = 0
4353 13:28:39.217271 3, 0xFFFF, sum = 0
4354 13:28:39.217619 4, 0xFFFF, sum = 0
4355 13:28:39.220646 5, 0xFFFF, sum = 0
4356 13:28:39.221103 6, 0xFFFF, sum = 0
4357 13:28:39.223977 7, 0x0, sum = 1
4358 13:28:39.224470 8, 0x0, sum = 2
4359 13:28:39.227272 9, 0x0, sum = 3
4360 13:28:39.227616 10, 0x0, sum = 4
4361 13:28:39.230231 best_step = 8
4362 13:28:39.230573
4363 13:28:39.230818 ==
4364 13:28:39.234165 Dram Type= 6, Freq= 0, CH_1, rank 0
4365 13:28:39.237269 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4366 13:28:39.237756 ==
4367 13:28:39.238034 RX Vref Scan: 1
4368 13:28:39.240774
4369 13:28:39.241255 RX Vref 0 -> 0, step: 1
4370 13:28:39.241532
4371 13:28:39.243779 RX Delay -195 -> 252, step: 8
4372 13:28:39.244260
4373 13:28:39.247371 Set Vref, RX VrefLevel [Byte0]: 52
4374 13:28:39.250551 [Byte1]: 48
4375 13:28:39.253469
4376 13:28:39.253850 Final RX Vref Byte 0 = 52 to rank0
4377 13:28:39.256623 Final RX Vref Byte 1 = 48 to rank0
4378 13:28:39.260216 Final RX Vref Byte 0 = 52 to rank1
4379 13:28:39.263583 Final RX Vref Byte 1 = 48 to rank1==
4380 13:28:39.267105 Dram Type= 6, Freq= 0, CH_1, rank 0
4381 13:28:39.273381 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4382 13:28:39.273726 ==
4383 13:28:39.274059 DQS Delay:
4384 13:28:39.276530 DQS0 = 0, DQS1 = 0
4385 13:28:39.276927 DQM Delay:
4386 13:28:39.277184 DQM0 = 37, DQM1 = 30
4387 13:28:39.280405 DQ Delay:
4388 13:28:39.283157 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4389 13:28:39.286645 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4390 13:28:39.289883 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4391 13:28:39.293852 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4392 13:28:39.294216
4393 13:28:39.294461
4394 13:28:39.299992 [DQSOSCAuto] RK0, (LSB)MR18= 0x7a7a, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
4395 13:28:39.303519 CH1 RK0: MR19=808, MR18=7A7A
4396 13:28:39.309916 CH1_RK0: MR19=0x808, MR18=0x7A7A, DQSOSC=387, MR23=63, INC=175, DEC=116
4397 13:28:39.310348
4398 13:28:39.313217 ----->DramcWriteLeveling(PI) begin...
4399 13:28:39.313688 ==
4400 13:28:39.316540 Dram Type= 6, Freq= 0, CH_1, rank 1
4401 13:28:39.319823 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4402 13:28:39.320219 ==
4403 13:28:39.322926 Write leveling (Byte 0): 30 => 30
4404 13:28:39.326511 Write leveling (Byte 1): 26 => 26
4405 13:28:39.329615 DramcWriteLeveling(PI) end<-----
4406 13:28:39.329954
4407 13:28:39.330196 ==
4408 13:28:39.333032 Dram Type= 6, Freq= 0, CH_1, rank 1
4409 13:28:39.336098 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4410 13:28:39.339300 ==
4411 13:28:39.339638 [Gating] SW mode calibration
4412 13:28:39.345992 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4413 13:28:39.352663 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4414 13:28:39.355701 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4415 13:28:39.362404 0 5 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
4416 13:28:39.365830 0 5 8 | B1->B0 | 2f2f 2626 | 1 1 | (1 0) (1 0)
4417 13:28:39.369390 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 13:28:39.376211 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 13:28:39.379377 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 13:28:39.382667 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 13:28:39.388778 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 13:28:39.392139 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 13:28:39.395816 0 6 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
4424 13:28:39.402733 0 6 8 | B1->B0 | 3636 4343 | 1 0 | (0 0) (0 0)
4425 13:28:39.405665 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 13:28:39.409128 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 13:28:39.415501 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 13:28:39.418398 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 13:28:39.421997 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 13:28:39.428641 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 13:28:39.431581 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4432 13:28:39.435548 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4433 13:28:39.441771 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 13:28:39.445747 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 13:28:39.448025 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 13:28:39.455088 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 13:28:39.458338 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 13:28:39.461572 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 13:28:39.468324 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 13:28:39.471593 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 13:28:39.474731 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 13:28:39.482174 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 13:28:39.485194 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 13:28:39.488347 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 13:28:39.494911 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 13:28:39.498220 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 13:28:39.501498 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4448 13:28:39.508029 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4449 13:28:39.508605 Total UI for P1: 0, mck2ui 16
4450 13:28:39.514723 best dqsien dly found for B0: ( 0, 9, 4)
4451 13:28:39.517688 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 13:28:39.521409 Total UI for P1: 0, mck2ui 16
4453 13:28:39.524836 best dqsien dly found for B1: ( 0, 9, 6)
4454 13:28:39.527687 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4455 13:28:39.531152 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4456 13:28:39.531541
4457 13:28:39.534323 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4458 13:28:39.537972 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4459 13:28:39.540901 [Gating] SW calibration Done
4460 13:28:39.541343 ==
4461 13:28:39.543985 Dram Type= 6, Freq= 0, CH_1, rank 1
4462 13:28:39.547380 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4463 13:28:39.547691 ==
4464 13:28:39.551052 RX Vref Scan: 0
4465 13:28:39.551504
4466 13:28:39.554475 RX Vref 0 -> 0, step: 1
4467 13:28:39.555027
4468 13:28:39.555430 RX Delay -230 -> 252, step: 16
4469 13:28:39.560840 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4470 13:28:39.564177 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4471 13:28:39.567632 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4472 13:28:39.570954 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4473 13:28:39.577305 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4474 13:28:39.580697 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4475 13:28:39.584094 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4476 13:28:39.587527 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4477 13:28:39.594194 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4478 13:28:39.597298 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4479 13:28:39.600929 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4480 13:28:39.603791 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4481 13:28:39.610653 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4482 13:28:39.613761 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4483 13:28:39.616789 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4484 13:28:39.620681 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4485 13:28:39.621073 ==
4486 13:28:39.623851 Dram Type= 6, Freq= 0, CH_1, rank 1
4487 13:28:39.630220 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4488 13:28:39.630675 ==
4489 13:28:39.631007 DQS Delay:
4490 13:28:39.633636 DQS0 = 0, DQS1 = 0
4491 13:28:39.634059 DQM Delay:
4492 13:28:39.634392 DQM0 = 40, DQM1 = 34
4493 13:28:39.636890 DQ Delay:
4494 13:28:39.640782 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4495 13:28:39.643701 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33
4496 13:28:39.647091 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4497 13:28:39.650020 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4498 13:28:39.650429
4499 13:28:39.650678
4500 13:28:39.650896 ==
4501 13:28:39.653795 Dram Type= 6, Freq= 0, CH_1, rank 1
4502 13:28:39.657074 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4503 13:28:39.657690 ==
4504 13:28:39.657998
4505 13:28:39.658243
4506 13:28:39.660225 TX Vref Scan disable
4507 13:28:39.663637 == TX Byte 0 ==
4508 13:28:39.666703 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4509 13:28:39.670296 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4510 13:28:39.670724 == TX Byte 1 ==
4511 13:28:39.676685 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4512 13:28:39.679520 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4513 13:28:39.679877 ==
4514 13:28:39.683183 Dram Type= 6, Freq= 0, CH_1, rank 1
4515 13:28:39.687077 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4516 13:28:39.687557 ==
4517 13:28:39.690470
4518 13:28:39.690901
4519 13:28:39.691246 TX Vref Scan disable
4520 13:28:39.693505 == TX Byte 0 ==
4521 13:28:39.697664 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4522 13:28:39.703633 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4523 13:28:39.704149 == TX Byte 1 ==
4524 13:28:39.706850 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4525 13:28:39.713687 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4526 13:28:39.714163
4527 13:28:39.714535 [DATLAT]
4528 13:28:39.714851 Freq=600, CH1 RK1
4529 13:28:39.715158
4530 13:28:39.716431 DATLAT Default: 0x8
4531 13:28:39.716707 0, 0xFFFF, sum = 0
4532 13:28:39.719987 1, 0xFFFF, sum = 0
4533 13:28:39.723326 2, 0xFFFF, sum = 0
4534 13:28:39.723690 3, 0xFFFF, sum = 0
4535 13:28:39.726830 4, 0xFFFF, sum = 0
4536 13:28:39.727190 5, 0xFFFF, sum = 0
4537 13:28:39.730086 6, 0xFFFF, sum = 0
4538 13:28:39.730523 7, 0x0, sum = 1
4539 13:28:39.730837 8, 0x0, sum = 2
4540 13:28:39.733120 9, 0x0, sum = 3
4541 13:28:39.733475 10, 0x0, sum = 4
4542 13:28:39.736793 best_step = 8
4543 13:28:39.737150
4544 13:28:39.737469 ==
4545 13:28:39.740198 Dram Type= 6, Freq= 0, CH_1, rank 1
4546 13:28:39.743605 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4547 13:28:39.744069 ==
4548 13:28:39.746672 RX Vref Scan: 0
4549 13:28:39.747128
4550 13:28:39.747476 RX Vref 0 -> 0, step: 1
4551 13:28:39.747763
4552 13:28:39.749783 RX Delay -195 -> 252, step: 8
4553 13:28:39.757052 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4554 13:28:39.760545 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4555 13:28:39.764047 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4556 13:28:39.767134 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4557 13:28:39.774086 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4558 13:28:39.777108 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4559 13:28:39.780612 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4560 13:28:39.783509 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4561 13:28:39.790214 iDelay=205, Bit 8, Center 16 (-139 ~ 172) 312
4562 13:28:39.793845 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4563 13:28:39.796748 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4564 13:28:39.799946 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4565 13:28:39.806903 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4566 13:28:39.810040 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4567 13:28:39.813722 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4568 13:28:39.816964 iDelay=205, Bit 15, Center 36 (-115 ~ 188) 304
4569 13:28:39.817450 ==
4570 13:28:39.820375 Dram Type= 6, Freq= 0, CH_1, rank 1
4571 13:28:39.826919 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4572 13:28:39.827412 ==
4573 13:28:39.827710 DQS Delay:
4574 13:28:39.827955 DQS0 = 0, DQS1 = 0
4575 13:28:39.829947 DQM Delay:
4576 13:28:39.830407 DQM0 = 37, DQM1 = 29
4577 13:28:39.833960 DQ Delay:
4578 13:28:39.836726 DQ0 =40, DQ1 =32, DQ2 =32, DQ3 =32
4579 13:28:39.840598 DQ4 =40, DQ5 =48, DQ6 =44, DQ7 =32
4580 13:28:39.843447 DQ8 =16, DQ9 =16, DQ10 =32, DQ11 =20
4581 13:28:39.846539 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =36
4582 13:28:39.847027
4583 13:28:39.847308
4584 13:28:39.853340 [DQSOSCAuto] RK1, (LSB)MR18= 0x5555, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4585 13:28:39.856413 CH1 RK1: MR19=808, MR18=5555
4586 13:28:39.863531 CH1_RK1: MR19=0x808, MR18=0x5555, DQSOSC=393, MR23=63, INC=169, DEC=113
4587 13:28:39.866548 [RxdqsGatingPostProcess] freq 600
4588 13:28:39.870187 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4589 13:28:39.873024 Pre-setting of DQS Precalculation
4590 13:28:39.879694 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4591 13:28:39.886568 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4592 13:28:39.893264 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4593 13:28:39.893746
4594 13:28:39.894026
4595 13:28:39.896662 [Calibration Summary] 1200 Mbps
4596 13:28:39.897151 CH 0, Rank 0
4597 13:28:39.899452 SW Impedance : PASS
4598 13:28:39.902781 DUTY Scan : NO K
4599 13:28:39.903172 ZQ Calibration : PASS
4600 13:28:39.906427 Jitter Meter : NO K
4601 13:28:39.909607 CBT Training : PASS
4602 13:28:39.910050 Write leveling : PASS
4603 13:28:39.912692 RX DQS gating : PASS
4604 13:28:39.916362 RX DQ/DQS(RDDQC) : PASS
4605 13:28:39.916843 TX DQ/DQS : PASS
4606 13:28:39.919299 RX DATLAT : PASS
4607 13:28:39.922896 RX DQ/DQS(Engine): PASS
4608 13:28:39.923361 TX OE : NO K
4609 13:28:39.926010 All Pass.
4610 13:28:39.926386
4611 13:28:39.926652 CH 0, Rank 1
4612 13:28:39.929357 SW Impedance : PASS
4613 13:28:39.929732 DUTY Scan : NO K
4614 13:28:39.932593 ZQ Calibration : PASS
4615 13:28:39.936534 Jitter Meter : NO K
4616 13:28:39.937021 CBT Training : PASS
4617 13:28:39.939760 Write leveling : PASS
4618 13:28:39.940264 RX DQS gating : PASS
4619 13:28:39.942815 RX DQ/DQS(RDDQC) : PASS
4620 13:28:39.946149 TX DQ/DQS : PASS
4621 13:28:39.946630 RX DATLAT : PASS
4622 13:28:39.949468 RX DQ/DQS(Engine): PASS
4623 13:28:39.952540 TX OE : NO K
4624 13:28:39.953026 All Pass.
4625 13:28:39.953316
4626 13:28:39.953557 CH 1, Rank 0
4627 13:28:39.955827 SW Impedance : PASS
4628 13:28:39.959147 DUTY Scan : NO K
4629 13:28:39.959578 ZQ Calibration : PASS
4630 13:28:39.962473 Jitter Meter : NO K
4631 13:28:39.966174 CBT Training : PASS
4632 13:28:39.966641 Write leveling : PASS
4633 13:28:39.968918 RX DQS gating : PASS
4634 13:28:39.972326 RX DQ/DQS(RDDQC) : PASS
4635 13:28:39.972619 TX DQ/DQS : PASS
4636 13:28:39.975332 RX DATLAT : PASS
4637 13:28:39.979340 RX DQ/DQS(Engine): PASS
4638 13:28:39.979774 TX OE : NO K
4639 13:28:39.980032 All Pass.
4640 13:28:39.982652
4641 13:28:39.983128 CH 1, Rank 1
4642 13:28:39.985864 SW Impedance : PASS
4643 13:28:39.986294 DUTY Scan : NO K
4644 13:28:39.989065 ZQ Calibration : PASS
4645 13:28:39.989559 Jitter Meter : NO K
4646 13:28:39.992240 CBT Training : PASS
4647 13:28:39.996087 Write leveling : PASS
4648 13:28:39.996687 RX DQS gating : PASS
4649 13:28:39.999080 RX DQ/DQS(RDDQC) : PASS
4650 13:28:40.002442 TX DQ/DQS : PASS
4651 13:28:40.002921 RX DATLAT : PASS
4652 13:28:40.005487 RX DQ/DQS(Engine): PASS
4653 13:28:40.009144 TX OE : NO K
4654 13:28:40.009634 All Pass.
4655 13:28:40.009931
4656 13:28:40.012141 DramC Write-DBI off
4657 13:28:40.012566 PER_BANK_REFRESH: Hybrid Mode
4658 13:28:40.015220 TX_TRACKING: ON
4659 13:28:40.022234 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4660 13:28:40.029196 [FAST_K] Save calibration result to emmc
4661 13:28:40.031973 dramc_set_vcore_voltage set vcore to 662500
4662 13:28:40.032383 Read voltage for 933, 3
4663 13:28:40.035535 Vio18 = 0
4664 13:28:40.036016 Vcore = 662500
4665 13:28:40.036337 Vdram = 0
4666 13:28:40.038889 Vddq = 0
4667 13:28:40.039274 Vmddr = 0
4668 13:28:40.041866 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4669 13:28:40.048879 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4670 13:28:40.052106 MEM_TYPE=3, freq_sel=17
4671 13:28:40.055812 sv_algorithm_assistance_LP4_1600
4672 13:28:40.058483 ============ PULL DRAM RESETB DOWN ============
4673 13:28:40.061834 ========== PULL DRAM RESETB DOWN end =========
4674 13:28:40.068380 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4675 13:28:40.071976 ===================================
4676 13:28:40.072485 LPDDR4 DRAM CONFIGURATION
4677 13:28:40.075170 ===================================
4678 13:28:40.078376 EX_ROW_EN[0] = 0x0
4679 13:28:40.078738 EX_ROW_EN[1] = 0x0
4680 13:28:40.082081 LP4Y_EN = 0x0
4681 13:28:40.082541 WORK_FSP = 0x0
4682 13:28:40.085197 WL = 0x3
4683 13:28:40.085676 RL = 0x3
4684 13:28:40.088445 BL = 0x2
4685 13:28:40.091838 RPST = 0x0
4686 13:28:40.092387 RD_PRE = 0x0
4687 13:28:40.095589 WR_PRE = 0x1
4688 13:28:40.096082 WR_PST = 0x0
4689 13:28:40.098658 DBI_WR = 0x0
4690 13:28:40.099157 DBI_RD = 0x0
4691 13:28:40.101767 OTF = 0x1
4692 13:28:40.105560 ===================================
4693 13:28:40.108594 ===================================
4694 13:28:40.109094 ANA top config
4695 13:28:40.111727 ===================================
4696 13:28:40.114927 DLL_ASYNC_EN = 0
4697 13:28:40.117972 ALL_SLAVE_EN = 1
4698 13:28:40.118447 NEW_RANK_MODE = 1
4699 13:28:40.121844 DLL_IDLE_MODE = 1
4700 13:28:40.124853 LP45_APHY_COMB_EN = 1
4701 13:28:40.127872 TX_ODT_DIS = 1
4702 13:28:40.131040 NEW_8X_MODE = 1
4703 13:28:40.134912 ===================================
4704 13:28:40.138344 ===================================
4705 13:28:40.138839 data_rate = 1866
4706 13:28:40.141407 CKR = 1
4707 13:28:40.144747 DQ_P2S_RATIO = 8
4708 13:28:40.148183 ===================================
4709 13:28:40.151217 CA_P2S_RATIO = 8
4710 13:28:40.154724 DQ_CA_OPEN = 0
4711 13:28:40.157721 DQ_SEMI_OPEN = 0
4712 13:28:40.158100 CA_SEMI_OPEN = 0
4713 13:28:40.160942 CA_FULL_RATE = 0
4714 13:28:40.164563 DQ_CKDIV4_EN = 1
4715 13:28:40.167958 CA_CKDIV4_EN = 1
4716 13:28:40.171120 CA_PREDIV_EN = 0
4717 13:28:40.174292 PH8_DLY = 0
4718 13:28:40.174654 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4719 13:28:40.177549 DQ_AAMCK_DIV = 4
4720 13:28:40.180924 CA_AAMCK_DIV = 4
4721 13:28:40.184563 CA_ADMCK_DIV = 4
4722 13:28:40.187850 DQ_TRACK_CA_EN = 0
4723 13:28:40.191673 CA_PICK = 933
4724 13:28:40.194394 CA_MCKIO = 933
4725 13:28:40.194784 MCKIO_SEMI = 0
4726 13:28:40.197753 PLL_FREQ = 3732
4727 13:28:40.201094 DQ_UI_PI_RATIO = 32
4728 13:28:40.204627 CA_UI_PI_RATIO = 0
4729 13:28:40.207587 ===================================
4730 13:28:40.210839 ===================================
4731 13:28:40.214437 memory_type:LPDDR4
4732 13:28:40.214922 GP_NUM : 10
4733 13:28:40.217371 SRAM_EN : 1
4734 13:28:40.220966 MD32_EN : 0
4735 13:28:40.224170 ===================================
4736 13:28:40.224582 [ANA_INIT] >>>>>>>>>>>>>>
4737 13:28:40.227679 <<<<<< [CONFIGURE PHASE]: ANA_TX
4738 13:28:40.230994 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4739 13:28:40.233942 ===================================
4740 13:28:40.237279 data_rate = 1866,PCW = 0X8f00
4741 13:28:40.240994 ===================================
4742 13:28:40.244058 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4743 13:28:40.250506 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4744 13:28:40.253695 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4745 13:28:40.260267 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4746 13:28:40.263546 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4747 13:28:40.266884 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4748 13:28:40.267376 [ANA_INIT] flow start
4749 13:28:40.270103 [ANA_INIT] PLL >>>>>>>>
4750 13:28:40.273528 [ANA_INIT] PLL <<<<<<<<
4751 13:28:40.273881 [ANA_INIT] MIDPI >>>>>>>>
4752 13:28:40.277275 [ANA_INIT] MIDPI <<<<<<<<
4753 13:28:40.280363 [ANA_INIT] DLL >>>>>>>>
4754 13:28:40.280714 [ANA_INIT] flow end
4755 13:28:40.287078 ============ LP4 DIFF to SE enter ============
4756 13:28:40.290243 ============ LP4 DIFF to SE exit ============
4757 13:28:40.293123 [ANA_INIT] <<<<<<<<<<<<<
4758 13:28:40.296970 [Flow] Enable top DCM control >>>>>
4759 13:28:40.300355 [Flow] Enable top DCM control <<<<<
4760 13:28:40.303740 Enable DLL master slave shuffle
4761 13:28:40.306879 ==============================================================
4762 13:28:40.310373 Gating Mode config
4763 13:28:40.313343 ==============================================================
4764 13:28:40.316993 Config description:
4765 13:28:40.326733 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4766 13:28:40.333482 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4767 13:28:40.336880 SELPH_MODE 0: By rank 1: By Phase
4768 13:28:40.343660 ==============================================================
4769 13:28:40.346988 GAT_TRACK_EN = 1
4770 13:28:40.350247 RX_GATING_MODE = 2
4771 13:28:40.353438 RX_GATING_TRACK_MODE = 2
4772 13:28:40.356628 SELPH_MODE = 1
4773 13:28:40.359768 PICG_EARLY_EN = 1
4774 13:28:40.360304 VALID_LAT_VALUE = 1
4775 13:28:40.366820 ==============================================================
4776 13:28:40.369761 Enter into Gating configuration >>>>
4777 13:28:40.373952 Exit from Gating configuration <<<<
4778 13:28:40.376791 Enter into DVFS_PRE_config >>>>>
4779 13:28:40.386373 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4780 13:28:40.389969 Exit from DVFS_PRE_config <<<<<
4781 13:28:40.392994 Enter into PICG configuration >>>>
4782 13:28:40.396487 Exit from PICG configuration <<<<
4783 13:28:40.399493 [RX_INPUT] configuration >>>>>
4784 13:28:40.403154 [RX_INPUT] configuration <<<<<
4785 13:28:40.409706 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4786 13:28:40.412952 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4787 13:28:40.419505 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4788 13:28:40.426060 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4789 13:28:40.432433 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4790 13:28:40.439088 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4791 13:28:40.442358 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4792 13:28:40.445881 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4793 13:28:40.449081 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4794 13:28:40.455637 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4795 13:28:40.459265 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4796 13:28:40.462193 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4797 13:28:40.465558 ===================================
4798 13:28:40.468804 LPDDR4 DRAM CONFIGURATION
4799 13:28:40.472388 ===================================
4800 13:28:40.475619 EX_ROW_EN[0] = 0x0
4801 13:28:40.476116 EX_ROW_EN[1] = 0x0
4802 13:28:40.478841 LP4Y_EN = 0x0
4803 13:28:40.479232 WORK_FSP = 0x0
4804 13:28:40.482094 WL = 0x3
4805 13:28:40.482558 RL = 0x3
4806 13:28:40.485197 BL = 0x2
4807 13:28:40.485554 RPST = 0x0
4808 13:28:40.488623 RD_PRE = 0x0
4809 13:28:40.489100 WR_PRE = 0x1
4810 13:28:40.492408 WR_PST = 0x0
4811 13:28:40.492890 DBI_WR = 0x0
4812 13:28:40.495786 DBI_RD = 0x0
4813 13:28:40.496418 OTF = 0x1
4814 13:28:40.499088 ===================================
4815 13:28:40.502187 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4816 13:28:40.508559 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4817 13:28:40.512046 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4818 13:28:40.515382 ===================================
4819 13:28:40.518841 LPDDR4 DRAM CONFIGURATION
4820 13:28:40.521981 ===================================
4821 13:28:40.522493 EX_ROW_EN[0] = 0x10
4822 13:28:40.525171 EX_ROW_EN[1] = 0x0
4823 13:28:40.528384 LP4Y_EN = 0x0
4824 13:28:40.528776 WORK_FSP = 0x0
4825 13:28:40.532008 WL = 0x3
4826 13:28:40.532552 RL = 0x3
4827 13:28:40.534936 BL = 0x2
4828 13:28:40.535421 RPST = 0x0
4829 13:28:40.538611 RD_PRE = 0x0
4830 13:28:40.539108 WR_PRE = 0x1
4831 13:28:40.542087 WR_PST = 0x0
4832 13:28:40.542577 DBI_WR = 0x0
4833 13:28:40.545116 DBI_RD = 0x0
4834 13:28:40.545610 OTF = 0x1
4835 13:28:40.548500 ===================================
4836 13:28:40.555324 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4837 13:28:40.559608 nWR fixed to 30
4838 13:28:40.562432 [ModeRegInit_LP4] CH0 RK0
4839 13:28:40.562833 [ModeRegInit_LP4] CH0 RK1
4840 13:28:40.566007 [ModeRegInit_LP4] CH1 RK0
4841 13:28:40.569359 [ModeRegInit_LP4] CH1 RK1
4842 13:28:40.569755 match AC timing 8
4843 13:28:40.576046 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4844 13:28:40.579251 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4845 13:28:40.582580 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4846 13:28:40.589204 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4847 13:28:40.592395 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4848 13:28:40.592891 ==
4849 13:28:40.595819 Dram Type= 6, Freq= 0, CH_0, rank 0
4850 13:28:40.598855 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4851 13:28:40.599352 ==
4852 13:28:40.605956 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4853 13:28:40.612242 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4854 13:28:40.615437 [CA 0] Center 38 (8~69) winsize 62
4855 13:28:40.619229 [CA 1] Center 38 (8~69) winsize 62
4856 13:28:40.622373 [CA 2] Center 36 (6~67) winsize 62
4857 13:28:40.625094 [CA 3] Center 35 (5~66) winsize 62
4858 13:28:40.628988 [CA 4] Center 35 (5~65) winsize 61
4859 13:28:40.631929 [CA 5] Center 34 (4~64) winsize 61
4860 13:28:40.632356
4861 13:28:40.635620 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4862 13:28:40.636118
4863 13:28:40.639210 [CATrainingPosCal] consider 1 rank data
4864 13:28:40.642157 u2DelayCellTimex100 = 270/100 ps
4865 13:28:40.645049 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4866 13:28:40.648866 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4867 13:28:40.652386 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4868 13:28:40.655278 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4869 13:28:40.658518 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
4870 13:28:40.665271 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4871 13:28:40.665760
4872 13:28:40.668618 CA PerBit enable=1, Macro0, CA PI delay=34
4873 13:28:40.668997
4874 13:28:40.671960 [CBTSetCACLKResult] CA Dly = 34
4875 13:28:40.672379 CS Dly: 6 (0~37)
4876 13:28:40.672666 ==
4877 13:28:40.675525 Dram Type= 6, Freq= 0, CH_0, rank 1
4878 13:28:40.678560 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4879 13:28:40.681886 ==
4880 13:28:40.685391 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4881 13:28:40.691637 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4882 13:28:40.694758 [CA 0] Center 38 (8~69) winsize 62
4883 13:28:40.698540 [CA 1] Center 38 (7~69) winsize 63
4884 13:28:40.702194 [CA 2] Center 36 (5~67) winsize 63
4885 13:28:40.705427 [CA 3] Center 35 (5~66) winsize 62
4886 13:28:40.708587 [CA 4] Center 34 (4~65) winsize 62
4887 13:28:40.712239 [CA 5] Center 34 (4~65) winsize 62
4888 13:28:40.712812
4889 13:28:40.715192 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4890 13:28:40.715680
4891 13:28:40.718552 [CATrainingPosCal] consider 2 rank data
4892 13:28:40.721641 u2DelayCellTimex100 = 270/100 ps
4893 13:28:40.724744 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4894 13:28:40.728693 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4895 13:28:40.731775 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4896 13:28:40.735153 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4897 13:28:40.741795 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
4898 13:28:40.744962 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4899 13:28:40.745497
4900 13:28:40.748255 CA PerBit enable=1, Macro0, CA PI delay=34
4901 13:28:40.748750
4902 13:28:40.751575 [CBTSetCACLKResult] CA Dly = 34
4903 13:28:40.751959 CS Dly: 7 (0~39)
4904 13:28:40.752228
4905 13:28:40.755196 ----->DramcWriteLeveling(PI) begin...
4906 13:28:40.755690 ==
4907 13:28:40.757853 Dram Type= 6, Freq= 0, CH_0, rank 0
4908 13:28:40.764969 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4909 13:28:40.765462 ==
4910 13:28:40.767946 Write leveling (Byte 0): 26 => 26
4911 13:28:40.771737 Write leveling (Byte 1): 26 => 26
4912 13:28:40.772141 DramcWriteLeveling(PI) end<-----
4913 13:28:40.772460
4914 13:28:40.775134 ==
4915 13:28:40.778029 Dram Type= 6, Freq= 0, CH_0, rank 0
4916 13:28:40.781101 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4917 13:28:40.781516 ==
4918 13:28:40.784814 [Gating] SW mode calibration
4919 13:28:40.791177 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4920 13:28:40.794370 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4921 13:28:40.801173 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4922 13:28:40.804873 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4923 13:28:40.807824 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4924 13:28:40.814665 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4925 13:28:40.817982 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4926 13:28:40.820737 0 10 20 | B1->B0 | 3434 3131 | 0 1 | (0 1) (1 1)
4927 13:28:40.827540 0 10 24 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4928 13:28:40.831253 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4929 13:28:40.834688 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4930 13:28:40.841472 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4931 13:28:40.844481 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4932 13:28:40.847318 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4933 13:28:40.854328 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4934 13:28:40.857577 0 11 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4935 13:28:40.860644 0 11 24 | B1->B0 | 3737 4141 | 0 1 | (0 0) (0 0)
4936 13:28:40.867826 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4937 13:28:40.870817 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4938 13:28:40.874027 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4939 13:28:40.880315 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4940 13:28:40.884231 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4941 13:28:40.887253 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4942 13:28:40.893829 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4943 13:28:40.897252 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4944 13:28:40.900098 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4945 13:28:40.907274 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4946 13:28:40.910379 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4947 13:28:40.913723 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4948 13:28:40.920375 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4949 13:28:40.923785 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4950 13:28:40.926517 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4951 13:28:40.933693 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4952 13:28:40.936983 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4953 13:28:40.940499 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4954 13:28:40.947088 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4955 13:28:40.950616 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4956 13:28:40.953585 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4957 13:28:40.956926 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4958 13:28:40.963291 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4959 13:28:40.967063 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4960 13:28:40.970744 Total UI for P1: 0, mck2ui 16
4961 13:28:40.973218 best dqsien dly found for B0: ( 0, 14, 20)
4962 13:28:40.976244 Total UI for P1: 0, mck2ui 16
4963 13:28:40.980149 best dqsien dly found for B1: ( 0, 14, 18)
4964 13:28:40.983153 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
4965 13:28:40.986616 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
4966 13:28:40.987077
4967 13:28:40.990505 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
4968 13:28:40.996139 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
4969 13:28:40.996631 [Gating] SW calibration Done
4970 13:28:40.996910 ==
4971 13:28:40.999761 Dram Type= 6, Freq= 0, CH_0, rank 0
4972 13:28:41.006455 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4973 13:28:41.006917 ==
4974 13:28:41.007204 RX Vref Scan: 0
4975 13:28:41.007448
4976 13:28:41.009980 RX Vref 0 -> 0, step: 1
4977 13:28:41.010481
4978 13:28:41.012636 RX Delay -80 -> 252, step: 8
4979 13:28:41.016149 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
4980 13:28:41.020051 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
4981 13:28:41.022868 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
4982 13:28:41.029512 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
4983 13:28:41.032918 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
4984 13:28:41.036389 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
4985 13:28:41.039589 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
4986 13:28:41.043141 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
4987 13:28:41.046505 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
4988 13:28:41.052820 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
4989 13:28:41.056059 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
4990 13:28:41.059798 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
4991 13:28:41.062573 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
4992 13:28:41.066429 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
4993 13:28:41.069430 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
4994 13:28:41.076029 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
4995 13:28:41.076568 ==
4996 13:28:41.079344 Dram Type= 6, Freq= 0, CH_0, rank 0
4997 13:28:41.082530 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4998 13:28:41.083013 ==
4999 13:28:41.083295 DQS Delay:
5000 13:28:41.085891 DQS0 = 0, DQS1 = 0
5001 13:28:41.086376 DQM Delay:
5002 13:28:41.089381 DQM0 = 95, DQM1 = 87
5003 13:28:41.089767 DQ Delay:
5004 13:28:41.093122 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5005 13:28:41.096028 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5006 13:28:41.099690 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5007 13:28:41.102804 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5008 13:28:41.103300
5009 13:28:41.103577
5010 13:28:41.103820 ==
5011 13:28:41.105952 Dram Type= 6, Freq= 0, CH_0, rank 0
5012 13:28:41.109247 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5013 13:28:41.112676 ==
5014 13:28:41.113179
5015 13:28:41.113469
5016 13:28:41.113716 TX Vref Scan disable
5017 13:28:41.116204 == TX Byte 0 ==
5018 13:28:41.119488 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5019 13:28:41.122247 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5020 13:28:41.126501 == TX Byte 1 ==
5021 13:28:41.129503 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5022 13:28:41.132815 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5023 13:28:41.133375 ==
5024 13:28:41.136346 Dram Type= 6, Freq= 0, CH_0, rank 0
5025 13:28:41.142937 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5026 13:28:41.143441 ==
5027 13:28:41.143733
5028 13:28:41.143974
5029 13:28:41.144205 TX Vref Scan disable
5030 13:28:41.146906 == TX Byte 0 ==
5031 13:28:41.150099 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5032 13:28:41.157126 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5033 13:28:41.157655 == TX Byte 1 ==
5034 13:28:41.159997 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5035 13:28:41.166562 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5036 13:28:41.167047
5037 13:28:41.167326 [DATLAT]
5038 13:28:41.167568 Freq=933, CH0 RK0
5039 13:28:41.167800
5040 13:28:41.170049 DATLAT Default: 0xd
5041 13:28:41.170432 0, 0xFFFF, sum = 0
5042 13:28:41.173229 1, 0xFFFF, sum = 0
5043 13:28:41.176710 2, 0xFFFF, sum = 0
5044 13:28:41.177214 3, 0xFFFF, sum = 0
5045 13:28:41.179878 4, 0xFFFF, sum = 0
5046 13:28:41.180436 5, 0xFFFF, sum = 0
5047 13:28:41.183050 6, 0xFFFF, sum = 0
5048 13:28:41.183451 7, 0xFFFF, sum = 0
5049 13:28:41.186501 8, 0xFFFF, sum = 0
5050 13:28:41.186986 9, 0xFFFF, sum = 0
5051 13:28:41.190145 10, 0x0, sum = 1
5052 13:28:41.190641 11, 0x0, sum = 2
5053 13:28:41.192840 12, 0x0, sum = 3
5054 13:28:41.193229 13, 0x0, sum = 4
5055 13:28:41.193507 best_step = 11
5056 13:28:41.193748
5057 13:28:41.196403 ==
5058 13:28:41.199868 Dram Type= 6, Freq= 0, CH_0, rank 0
5059 13:28:41.203057 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5060 13:28:41.203552 ==
5061 13:28:41.203842 RX Vref Scan: 1
5062 13:28:41.204084
5063 13:28:41.206534 RX Vref 0 -> 0, step: 1
5064 13:28:41.207020
5065 13:28:41.210108 RX Delay -77 -> 252, step: 4
5066 13:28:41.210600
5067 13:28:41.212898 Set Vref, RX VrefLevel [Byte0]: 47
5068 13:28:41.217004 [Byte1]: 48
5069 13:28:41.217497
5070 13:28:41.219848 Final RX Vref Byte 0 = 47 to rank0
5071 13:28:41.223291 Final RX Vref Byte 1 = 48 to rank0
5072 13:28:41.226121 Final RX Vref Byte 0 = 47 to rank1
5073 13:28:41.230233 Final RX Vref Byte 1 = 48 to rank1==
5074 13:28:41.232791 Dram Type= 6, Freq= 0, CH_0, rank 0
5075 13:28:41.236069 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5076 13:28:41.239765 ==
5077 13:28:41.240252 DQS Delay:
5078 13:28:41.240571 DQS0 = 0, DQS1 = 0
5079 13:28:41.243193 DQM Delay:
5080 13:28:41.243764 DQM0 = 96, DQM1 = 86
5081 13:28:41.246274 DQ Delay:
5082 13:28:41.249530 DQ0 =94, DQ1 =98, DQ2 =94, DQ3 =92
5083 13:28:41.252958 DQ4 =102, DQ5 =86, DQ6 =104, DQ7 =104
5084 13:28:41.255999 DQ8 =78, DQ9 =70, DQ10 =86, DQ11 =78
5085 13:28:41.259626 DQ12 =94, DQ13 =92, DQ14 =96, DQ15 =96
5086 13:28:41.260116
5087 13:28:41.260449
5088 13:28:41.265877 [DQSOSCAuto] RK0, (LSB)MR18= 0x2020, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5089 13:28:41.269658 CH0 RK0: MR19=505, MR18=2020
5090 13:28:41.276182 CH0_RK0: MR19=0x505, MR18=0x2020, DQSOSC=411, MR23=63, INC=64, DEC=42
5091 13:28:41.276697
5092 13:28:41.279472 ----->DramcWriteLeveling(PI) begin...
5093 13:28:41.279978 ==
5094 13:28:41.282456 Dram Type= 6, Freq= 0, CH_0, rank 1
5095 13:28:41.286233 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5096 13:28:41.286730 ==
5097 13:28:41.289265 Write leveling (Byte 0): 29 => 29
5098 13:28:41.292325 Write leveling (Byte 1): 26 => 26
5099 13:28:41.296072 DramcWriteLeveling(PI) end<-----
5100 13:28:41.296676
5101 13:28:41.296960 ==
5102 13:28:41.299068 Dram Type= 6, Freq= 0, CH_0, rank 1
5103 13:28:41.302225 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5104 13:28:41.302630 ==
5105 13:28:41.306034 [Gating] SW mode calibration
5106 13:28:41.312504 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5107 13:28:41.318921 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5108 13:28:41.322247 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 13:28:41.328580 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 13:28:41.332670 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 13:28:41.335484 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 13:28:41.342303 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 13:28:41.345140 0 10 20 | B1->B0 | 3030 3030 | 0 0 | (0 1) (0 1)
5114 13:28:41.348865 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
5115 13:28:41.355838 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 13:28:41.358872 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 13:28:41.362107 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 13:28:41.369103 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 13:28:41.372177 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 13:28:41.375304 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 13:28:41.378652 0 11 20 | B1->B0 | 2b2b 3232 | 0 0 | (0 0) (1 1)
5122 13:28:41.385141 0 11 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5123 13:28:41.388520 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 13:28:41.391838 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 13:28:41.398857 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 13:28:41.401554 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 13:28:41.405133 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 13:28:41.412127 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 13:28:41.415153 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5130 13:28:41.418194 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5131 13:28:41.425049 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 13:28:41.428202 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 13:28:41.431765 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 13:28:41.438647 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 13:28:41.441856 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 13:28:41.444788 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 13:28:41.451781 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 13:28:41.454704 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 13:28:41.457875 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 13:28:41.464264 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 13:28:41.467633 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 13:28:41.471561 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 13:28:41.478260 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 13:28:41.481252 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 13:28:41.485101 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5146 13:28:41.491249 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5147 13:28:41.491750 Total UI for P1: 0, mck2ui 16
5148 13:28:41.497555 best dqsien dly found for B0: ( 0, 14, 20)
5149 13:28:41.501123 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 13:28:41.504436 Total UI for P1: 0, mck2ui 16
5151 13:28:41.507981 best dqsien dly found for B1: ( 0, 14, 24)
5152 13:28:41.511147 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5153 13:28:41.514922 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
5154 13:28:41.515349
5155 13:28:41.517899 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5156 13:28:41.521178 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 24)
5157 13:28:41.524646 [Gating] SW calibration Done
5158 13:28:41.525142 ==
5159 13:28:41.527877 Dram Type= 6, Freq= 0, CH_0, rank 1
5160 13:28:41.531278 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5161 13:28:41.534577 ==
5162 13:28:41.534962 RX Vref Scan: 0
5163 13:28:41.535238
5164 13:28:41.538202 RX Vref 0 -> 0, step: 1
5165 13:28:41.538696
5166 13:28:41.541484 RX Delay -80 -> 252, step: 8
5167 13:28:41.544854 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5168 13:28:41.547800 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5169 13:28:41.551412 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5170 13:28:41.554482 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192
5171 13:28:41.557813 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5172 13:28:41.564400 iDelay=208, Bit 5, Center 91 (-8 ~ 191) 200
5173 13:28:41.567338 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5174 13:28:41.570802 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5175 13:28:41.574063 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5176 13:28:41.577347 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5177 13:28:41.584553 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5178 13:28:41.587546 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5179 13:28:41.591400 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5180 13:28:41.594612 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5181 13:28:41.597468 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5182 13:28:41.600945 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5183 13:28:41.604132 ==
5184 13:28:41.607756 Dram Type= 6, Freq= 0, CH_0, rank 1
5185 13:28:41.610853 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5186 13:28:41.611347 ==
5187 13:28:41.611638 DQS Delay:
5188 13:28:41.614531 DQS0 = 0, DQS1 = 0
5189 13:28:41.614911 DQM Delay:
5190 13:28:41.617187 DQM0 = 97, DQM1 = 85
5191 13:28:41.617567 DQ Delay:
5192 13:28:41.620420 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =87
5193 13:28:41.623807 DQ4 =103, DQ5 =91, DQ6 =103, DQ7 =107
5194 13:28:41.627131 DQ8 =71, DQ9 =71, DQ10 =87, DQ11 =79
5195 13:28:41.630458 DQ12 =95, DQ13 =91, DQ14 =91, DQ15 =95
5196 13:28:41.630950
5197 13:28:41.631232
5198 13:28:41.631476 ==
5199 13:28:41.633836 Dram Type= 6, Freq= 0, CH_0, rank 1
5200 13:28:41.637183 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5201 13:28:41.637640 ==
5202 13:28:41.637904
5203 13:28:41.640387
5204 13:28:41.640871 TX Vref Scan disable
5205 13:28:41.643733 == TX Byte 0 ==
5206 13:28:41.647177 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5207 13:28:41.650170 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5208 13:28:41.653694 == TX Byte 1 ==
5209 13:28:41.657253 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5210 13:28:41.660315 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5211 13:28:41.660795 ==
5212 13:28:41.663989 Dram Type= 6, Freq= 0, CH_0, rank 1
5213 13:28:41.670533 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5214 13:28:41.671025 ==
5215 13:28:41.671312
5216 13:28:41.671552
5217 13:28:41.671778 TX Vref Scan disable
5218 13:28:41.674571 == TX Byte 0 ==
5219 13:28:41.677906 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5220 13:28:41.683997 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5221 13:28:41.684421 == TX Byte 1 ==
5222 13:28:41.687440 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5223 13:28:41.694235 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5224 13:28:41.694695
5225 13:28:41.694984 [DATLAT]
5226 13:28:41.695224 Freq=933, CH0 RK1
5227 13:28:41.695457
5228 13:28:41.697174 DATLAT Default: 0xb
5229 13:28:41.700939 0, 0xFFFF, sum = 0
5230 13:28:41.701443 1, 0xFFFF, sum = 0
5231 13:28:41.704040 2, 0xFFFF, sum = 0
5232 13:28:41.704479 3, 0xFFFF, sum = 0
5233 13:28:41.707423 4, 0xFFFF, sum = 0
5234 13:28:41.707919 5, 0xFFFF, sum = 0
5235 13:28:41.710819 6, 0xFFFF, sum = 0
5236 13:28:41.711320 7, 0xFFFF, sum = 0
5237 13:28:41.713548 8, 0xFFFF, sum = 0
5238 13:28:41.713937 9, 0xFFFF, sum = 0
5239 13:28:41.717070 10, 0x0, sum = 1
5240 13:28:41.717456 11, 0x0, sum = 2
5241 13:28:41.719967 12, 0x0, sum = 3
5242 13:28:41.720368 13, 0x0, sum = 4
5243 13:28:41.723622 best_step = 11
5244 13:28:41.723715
5245 13:28:41.723777 ==
5246 13:28:41.726472 Dram Type= 6, Freq= 0, CH_0, rank 1
5247 13:28:41.730207 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5248 13:28:41.730298 ==
5249 13:28:41.730362 RX Vref Scan: 0
5250 13:28:41.730419
5251 13:28:41.733168 RX Vref 0 -> 0, step: 1
5252 13:28:41.733246
5253 13:28:41.736248 RX Delay -69 -> 252, step: 4
5254 13:28:41.743262 iDelay=199, Bit 0, Center 94 (3 ~ 186) 184
5255 13:28:41.746280 iDelay=199, Bit 1, Center 100 (7 ~ 194) 188
5256 13:28:41.750120 iDelay=199, Bit 2, Center 94 (3 ~ 186) 184
5257 13:28:41.753038 iDelay=199, Bit 3, Center 92 (3 ~ 182) 180
5258 13:28:41.756738 iDelay=199, Bit 4, Center 102 (11 ~ 194) 184
5259 13:28:41.759650 iDelay=199, Bit 5, Center 90 (-1 ~ 182) 184
5260 13:28:41.766626 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5261 13:28:41.770211 iDelay=199, Bit 7, Center 108 (19 ~ 198) 180
5262 13:28:41.773537 iDelay=199, Bit 8, Center 74 (-13 ~ 162) 176
5263 13:28:41.776899 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5264 13:28:41.779836 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5265 13:28:41.786418 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5266 13:28:41.789708 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5267 13:28:41.793029 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5268 13:28:41.796722 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5269 13:28:41.800079 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5270 13:28:41.800590 ==
5271 13:28:41.803225 Dram Type= 6, Freq= 0, CH_0, rank 1
5272 13:28:41.810069 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5273 13:28:41.810567 ==
5274 13:28:41.810847 DQS Delay:
5275 13:28:41.813049 DQS0 = 0, DQS1 = 0
5276 13:28:41.813548 DQM Delay:
5277 13:28:41.813834 DQM0 = 97, DQM1 = 85
5278 13:28:41.816454 DQ Delay:
5279 13:28:41.819643 DQ0 =94, DQ1 =100, DQ2 =94, DQ3 =92
5280 13:28:41.823002 DQ4 =102, DQ5 =90, DQ6 =102, DQ7 =108
5281 13:28:41.826086 DQ8 =74, DQ9 =72, DQ10 =88, DQ11 =78
5282 13:28:41.829584 DQ12 =92, DQ13 =90, DQ14 =98, DQ15 =94
5283 13:28:41.829967
5284 13:28:41.830242
5285 13:28:41.836037 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e2e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
5286 13:28:41.839410 CH0 RK1: MR19=505, MR18=2E2E
5287 13:28:41.846323 CH0_RK1: MR19=0x505, MR18=0x2E2E, DQSOSC=407, MR23=63, INC=65, DEC=43
5288 13:28:41.849382 [RxdqsGatingPostProcess] freq 933
5289 13:28:41.855949 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5290 13:28:41.856385 Pre-setting of DQS Precalculation
5291 13:28:41.862611 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5292 13:28:41.863049 ==
5293 13:28:41.865607 Dram Type= 6, Freq= 0, CH_1, rank 0
5294 13:28:41.869342 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5295 13:28:41.869696 ==
5296 13:28:41.875752 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5297 13:28:41.882619 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5298 13:28:41.885758 [CA 0] Center 37 (6~68) winsize 63
5299 13:28:41.889456 [CA 1] Center 37 (6~68) winsize 63
5300 13:28:41.892809 [CA 2] Center 34 (4~65) winsize 62
5301 13:28:41.895843 [CA 3] Center 34 (3~65) winsize 63
5302 13:28:41.899022 [CA 4] Center 33 (2~64) winsize 63
5303 13:28:41.902581 [CA 5] Center 33 (2~64) winsize 63
5304 13:28:41.903078
5305 13:28:41.906082 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5306 13:28:41.906576
5307 13:28:41.909080 [CATrainingPosCal] consider 1 rank data
5308 13:28:41.912063 u2DelayCellTimex100 = 270/100 ps
5309 13:28:41.915094 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5310 13:28:41.918447 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5311 13:28:41.922005 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5312 13:28:41.925065 CA3 delay=34 (3~65),Diff = 1 PI (6 cell)
5313 13:28:41.929037 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5314 13:28:41.935667 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5315 13:28:41.936156
5316 13:28:41.938266 CA PerBit enable=1, Macro0, CA PI delay=33
5317 13:28:41.938647
5318 13:28:41.941662 [CBTSetCACLKResult] CA Dly = 33
5319 13:28:41.942011 CS Dly: 5 (0~36)
5320 13:28:41.942258 ==
5321 13:28:41.945201 Dram Type= 6, Freq= 0, CH_1, rank 1
5322 13:28:41.948617 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5323 13:28:41.951402 ==
5324 13:28:41.955363 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5325 13:28:41.961378 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5326 13:28:41.964992 [CA 0] Center 37 (6~68) winsize 63
5327 13:28:41.968081 [CA 1] Center 37 (6~68) winsize 63
5328 13:28:41.971418 [CA 2] Center 34 (4~65) winsize 62
5329 13:28:41.974611 [CA 3] Center 34 (4~64) winsize 61
5330 13:28:41.977962 [CA 4] Center 33 (2~64) winsize 63
5331 13:28:41.981190 [CA 5] Center 32 (2~63) winsize 62
5332 13:28:41.981535
5333 13:28:41.984788 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5334 13:28:41.985132
5335 13:28:41.988221 [CATrainingPosCal] consider 2 rank data
5336 13:28:41.991246 u2DelayCellTimex100 = 270/100 ps
5337 13:28:41.995122 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5338 13:28:41.997947 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5339 13:28:42.001283 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5340 13:28:42.007911 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5341 13:28:42.011650 CA4 delay=33 (2~64),Diff = 1 PI (6 cell)
5342 13:28:42.014338 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5343 13:28:42.014696
5344 13:28:42.018436 CA PerBit enable=1, Macro0, CA PI delay=32
5345 13:28:42.018918
5346 13:28:42.021454 [CBTSetCACLKResult] CA Dly = 32
5347 13:28:42.021911 CS Dly: 5 (0~37)
5348 13:28:42.022205
5349 13:28:42.024844 ----->DramcWriteLeveling(PI) begin...
5350 13:28:42.028329 ==
5351 13:28:42.028777 Dram Type= 6, Freq= 0, CH_1, rank 0
5352 13:28:42.034832 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5353 13:28:42.035318 ==
5354 13:28:42.037827 Write leveling (Byte 0): 28 => 28
5355 13:28:42.041744 Write leveling (Byte 1): 26 => 26
5356 13:28:42.044725 DramcWriteLeveling(PI) end<-----
5357 13:28:42.045112
5358 13:28:42.045382 ==
5359 13:28:42.047891 Dram Type= 6, Freq= 0, CH_1, rank 0
5360 13:28:42.051017 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5361 13:28:42.051496 ==
5362 13:28:42.054060 [Gating] SW mode calibration
5363 13:28:42.061113 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5364 13:28:42.067476 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5365 13:28:42.071277 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5366 13:28:42.073927 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5367 13:28:42.080298 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5368 13:28:42.084370 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5369 13:28:42.087029 0 10 16 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
5370 13:28:42.094363 0 10 20 | B1->B0 | 3333 2323 | 1 0 | (0 0) (0 0)
5371 13:28:42.097249 0 10 24 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
5372 13:28:42.100626 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5373 13:28:42.104139 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5374 13:28:42.110466 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5375 13:28:42.113807 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5376 13:28:42.120384 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5377 13:28:42.123408 0 11 16 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 1)
5378 13:28:42.127087 0 11 20 | B1->B0 | 2727 4242 | 0 0 | (0 0) (0 0)
5379 13:28:42.133835 0 11 24 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
5380 13:28:42.136835 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 13:28:42.140124 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5382 13:28:42.143393 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 13:28:42.149754 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 13:28:42.153321 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5385 13:28:42.159848 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5386 13:28:42.163117 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5387 13:28:42.166380 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 13:28:42.170091 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 13:28:42.176071 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 13:28:42.179679 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 13:28:42.182906 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 13:28:42.189556 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 13:28:42.192896 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 13:28:42.196256 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 13:28:42.202833 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 13:28:42.205818 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 13:28:42.209344 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 13:28:42.216381 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 13:28:42.219383 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 13:28:42.222952 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 13:28:42.229576 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5402 13:28:42.232847 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5403 13:28:42.236621 Total UI for P1: 0, mck2ui 16
5404 13:28:42.239675 best dqsien dly found for B0: ( 0, 14, 16)
5405 13:28:42.242880 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5406 13:28:42.246271 Total UI for P1: 0, mck2ui 16
5407 13:28:42.249493 best dqsien dly found for B1: ( 0, 14, 20)
5408 13:28:42.252637 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5409 13:28:42.259154 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5410 13:28:42.259648
5411 13:28:42.262338 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5412 13:28:42.265487 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5413 13:28:42.268689 [Gating] SW calibration Done
5414 13:28:42.269155 ==
5415 13:28:42.272838 Dram Type= 6, Freq= 0, CH_1, rank 0
5416 13:28:42.275136 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5417 13:28:42.275533 ==
5418 13:28:42.278951 RX Vref Scan: 0
5419 13:28:42.279439
5420 13:28:42.279727 RX Vref 0 -> 0, step: 1
5421 13:28:42.279970
5422 13:28:42.281989 RX Delay -80 -> 252, step: 8
5423 13:28:42.285296 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5424 13:28:42.288512 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5425 13:28:42.295373 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5426 13:28:42.298982 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5427 13:28:42.301655 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5428 13:28:42.305153 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5429 13:28:42.308819 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5430 13:28:42.312079 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5431 13:28:42.318655 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5432 13:28:42.321783 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5433 13:28:42.325425 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5434 13:28:42.328608 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5435 13:28:42.331943 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5436 13:28:42.338732 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5437 13:28:42.341712 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5438 13:28:42.345041 iDelay=208, Bit 15, Center 95 (-8 ~ 199) 208
5439 13:28:42.345520 ==
5440 13:28:42.348847 Dram Type= 6, Freq= 0, CH_1, rank 0
5441 13:28:42.351671 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5442 13:28:42.352154 ==
5443 13:28:42.355345 DQS Delay:
5444 13:28:42.355828 DQS0 = 0, DQS1 = 0
5445 13:28:42.358359 DQM Delay:
5446 13:28:42.358839 DQM0 = 94, DQM1 = 87
5447 13:28:42.359132 DQ Delay:
5448 13:28:42.361540 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5449 13:28:42.364763 DQ4 =91, DQ5 =107, DQ6 =99, DQ7 =91
5450 13:28:42.368250 DQ8 =71, DQ9 =75, DQ10 =91, DQ11 =79
5451 13:28:42.371376 DQ12 =99, DQ13 =99, DQ14 =91, DQ15 =95
5452 13:28:42.371860
5453 13:28:42.372149
5454 13:28:42.374696 ==
5455 13:28:42.378158 Dram Type= 6, Freq= 0, CH_1, rank 0
5456 13:28:42.381504 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5457 13:28:42.381895 ==
5458 13:28:42.382166
5459 13:28:42.382403
5460 13:28:42.384614 TX Vref Scan disable
5461 13:28:42.384989 == TX Byte 0 ==
5462 13:28:42.391102 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5463 13:28:42.394355 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5464 13:28:42.394749 == TX Byte 1 ==
5465 13:28:42.401227 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5466 13:28:42.404746 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5467 13:28:42.405140 ==
5468 13:28:42.408315 Dram Type= 6, Freq= 0, CH_1, rank 0
5469 13:28:42.410980 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5470 13:28:42.411334 ==
5471 13:28:42.411583
5472 13:28:42.411804
5473 13:28:42.414844 TX Vref Scan disable
5474 13:28:42.418243 == TX Byte 0 ==
5475 13:28:42.421016 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5476 13:28:42.424002 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5477 13:28:42.428165 == TX Byte 1 ==
5478 13:28:42.431338 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5479 13:28:42.434498 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5480 13:28:42.434987
5481 13:28:42.437731 [DATLAT]
5482 13:28:42.438190 Freq=933, CH1 RK0
5483 13:28:42.438490
5484 13:28:42.441142 DATLAT Default: 0xd
5485 13:28:42.441719 0, 0xFFFF, sum = 0
5486 13:28:42.443956 1, 0xFFFF, sum = 0
5487 13:28:42.444491 2, 0xFFFF, sum = 0
5488 13:28:42.447576 3, 0xFFFF, sum = 0
5489 13:28:42.448069 4, 0xFFFF, sum = 0
5490 13:28:42.451076 5, 0xFFFF, sum = 0
5491 13:28:42.451528 6, 0xFFFF, sum = 0
5492 13:28:42.453890 7, 0xFFFF, sum = 0
5493 13:28:42.454279 8, 0xFFFF, sum = 0
5494 13:28:42.458122 9, 0xFFFF, sum = 0
5495 13:28:42.458607 10, 0x0, sum = 1
5496 13:28:42.461120 11, 0x0, sum = 2
5497 13:28:42.461610 12, 0x0, sum = 3
5498 13:28:42.463993 13, 0x0, sum = 4
5499 13:28:42.464525 best_step = 11
5500 13:28:42.464817
5501 13:28:42.465058 ==
5502 13:28:42.467183 Dram Type= 6, Freq= 0, CH_1, rank 0
5503 13:28:42.474153 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5504 13:28:42.474579 ==
5505 13:28:42.474873 RX Vref Scan: 1
5506 13:28:42.475108
5507 13:28:42.477124 RX Vref 0 -> 0, step: 1
5508 13:28:42.477476
5509 13:28:42.480339 RX Delay -69 -> 252, step: 4
5510 13:28:42.480692
5511 13:28:42.483768 Set Vref, RX VrefLevel [Byte0]: 52
5512 13:28:42.487382 [Byte1]: 48
5513 13:28:42.487826
5514 13:28:42.490865 Final RX Vref Byte 0 = 52 to rank0
5515 13:28:42.493704 Final RX Vref Byte 1 = 48 to rank0
5516 13:28:42.497015 Final RX Vref Byte 0 = 52 to rank1
5517 13:28:42.500307 Final RX Vref Byte 1 = 48 to rank1==
5518 13:28:42.503427 Dram Type= 6, Freq= 0, CH_1, rank 0
5519 13:28:42.507454 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5520 13:28:42.507916 ==
5521 13:28:42.510303 DQS Delay:
5522 13:28:42.510752 DQS0 = 0, DQS1 = 0
5523 13:28:42.513391 DQM Delay:
5524 13:28:42.513741 DQM0 = 94, DQM1 = 88
5525 13:28:42.513993 DQ Delay:
5526 13:28:42.516998 DQ0 =98, DQ1 =88, DQ2 =86, DQ3 =90
5527 13:28:42.520634 DQ4 =92, DQ5 =104, DQ6 =102, DQ7 =92
5528 13:28:42.523459 DQ8 =70, DQ9 =76, DQ10 =90, DQ11 =80
5529 13:28:42.527270 DQ12 =94, DQ13 =98, DQ14 =98, DQ15 =98
5530 13:28:42.527749
5531 13:28:42.528042
5532 13:28:42.536845 [DQSOSCAuto] RK0, (LSB)MR18= 0x3434, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
5533 13:28:42.540454 CH1 RK0: MR19=505, MR18=3434
5534 13:28:42.547272 CH1_RK0: MR19=0x505, MR18=0x3434, DQSOSC=405, MR23=63, INC=66, DEC=44
5535 13:28:42.547760
5536 13:28:42.549788 ----->DramcWriteLeveling(PI) begin...
5537 13:28:42.550181 ==
5538 13:28:42.553613 Dram Type= 6, Freq= 0, CH_1, rank 1
5539 13:28:42.556957 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5540 13:28:42.557432 ==
5541 13:28:42.559965 Write leveling (Byte 0): 27 => 27
5542 13:28:42.563705 Write leveling (Byte 1): 26 => 26
5543 13:28:42.567034 DramcWriteLeveling(PI) end<-----
5544 13:28:42.567515
5545 13:28:42.567802 ==
5546 13:28:42.569929 Dram Type= 6, Freq= 0, CH_1, rank 1
5547 13:28:42.573107 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5548 13:28:42.573493 ==
5549 13:28:42.576195 [Gating] SW mode calibration
5550 13:28:42.583336 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5551 13:28:42.590048 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5552 13:28:42.592803 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5553 13:28:42.596503 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5554 13:28:42.602807 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5555 13:28:42.606702 0 10 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5556 13:28:42.609586 0 10 16 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 0)
5557 13:28:42.616039 0 10 20 | B1->B0 | 3030 2323 | 1 0 | (1 0) (1 0)
5558 13:28:42.619958 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5559 13:28:42.622828 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5560 13:28:42.629208 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5561 13:28:42.632466 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5562 13:28:42.636419 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5563 13:28:42.642447 0 11 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5564 13:28:42.645771 0 11 16 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
5565 13:28:42.649027 0 11 20 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
5566 13:28:42.656053 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5567 13:28:42.659222 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5568 13:28:42.662400 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5569 13:28:42.669024 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5570 13:28:42.672239 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5571 13:28:42.675518 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5572 13:28:42.682379 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5573 13:28:42.685549 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5574 13:28:42.689127 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 13:28:42.695455 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 13:28:42.698957 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 13:28:42.702033 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 13:28:42.708883 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 13:28:42.711990 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 13:28:42.715152 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 13:28:42.722264 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 13:28:42.725000 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 13:28:42.728265 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 13:28:42.735126 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 13:28:42.738268 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 13:28:42.741526 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 13:28:42.748072 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5588 13:28:42.751758 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5589 13:28:42.755257 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5590 13:28:42.761801 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 13:28:42.762197 Total UI for P1: 0, mck2ui 16
5592 13:28:42.768682 best dqsien dly found for B0: ( 0, 14, 16)
5593 13:28:42.769167 Total UI for P1: 0, mck2ui 16
5594 13:28:42.771503 best dqsien dly found for B1: ( 0, 14, 20)
5595 13:28:42.777932 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5596 13:28:42.781548 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5597 13:28:42.781922
5598 13:28:42.784439 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5599 13:28:42.788348 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5600 13:28:42.791319 [Gating] SW calibration Done
5601 13:28:42.791800 ==
5602 13:28:42.794611 Dram Type= 6, Freq= 0, CH_1, rank 1
5603 13:28:42.797763 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5604 13:28:42.798249 ==
5605 13:28:42.801598 RX Vref Scan: 0
5606 13:28:42.802083
5607 13:28:42.802369 RX Vref 0 -> 0, step: 1
5608 13:28:42.802616
5609 13:28:42.804258 RX Delay -80 -> 252, step: 8
5610 13:28:42.807958 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5611 13:28:42.814395 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5612 13:28:42.817847 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5613 13:28:42.821393 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5614 13:28:42.824171 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5615 13:28:42.827778 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5616 13:28:42.830887 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5617 13:28:42.837563 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5618 13:28:42.841228 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5619 13:28:42.844331 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5620 13:28:42.847332 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5621 13:28:42.850945 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5622 13:28:42.857512 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5623 13:28:42.860487 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5624 13:28:42.864098 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5625 13:28:42.867238 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5626 13:28:42.867644 ==
5627 13:28:42.871160 Dram Type= 6, Freq= 0, CH_1, rank 1
5628 13:28:42.877561 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5629 13:28:42.878054 ==
5630 13:28:42.878343 DQS Delay:
5631 13:28:42.878584 DQS0 = 0, DQS1 = 0
5632 13:28:42.880107 DQM Delay:
5633 13:28:42.880542 DQM0 = 96, DQM1 = 88
5634 13:28:42.884073 DQ Delay:
5635 13:28:42.887305 DQ0 =99, DQ1 =87, DQ2 =87, DQ3 =91
5636 13:28:42.890603 DQ4 =99, DQ5 =107, DQ6 =107, DQ7 =91
5637 13:28:42.894083 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =75
5638 13:28:42.897048 DQ12 =95, DQ13 =103, DQ14 =99, DQ15 =99
5639 13:28:42.897535
5640 13:28:42.897818
5641 13:28:42.898066 ==
5642 13:28:42.900338 Dram Type= 6, Freq= 0, CH_1, rank 1
5643 13:28:42.903919 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5644 13:28:42.904454 ==
5645 13:28:42.904751
5646 13:28:42.904994
5647 13:28:42.907277 TX Vref Scan disable
5648 13:28:42.907763 == TX Byte 0 ==
5649 13:28:42.913666 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5650 13:28:42.916998 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5651 13:28:42.917483 == TX Byte 1 ==
5652 13:28:42.923480 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5653 13:28:42.927098 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5654 13:28:42.927580 ==
5655 13:28:42.930325 Dram Type= 6, Freq= 0, CH_1, rank 1
5656 13:28:42.933568 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5657 13:28:42.934068 ==
5658 13:28:42.934358
5659 13:28:42.936732
5660 13:28:42.937204 TX Vref Scan disable
5661 13:28:42.940535 == TX Byte 0 ==
5662 13:28:42.943645 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5663 13:28:42.947302 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5664 13:28:42.950400 == TX Byte 1 ==
5665 13:28:42.953888 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5666 13:28:42.956717 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5667 13:28:42.957200
5668 13:28:42.959906 [DATLAT]
5669 13:28:42.960441 Freq=933, CH1 RK1
5670 13:28:42.960780
5671 13:28:42.963981 DATLAT Default: 0xb
5672 13:28:42.964544 0, 0xFFFF, sum = 0
5673 13:28:42.966587 1, 0xFFFF, sum = 0
5674 13:28:42.966974 2, 0xFFFF, sum = 0
5675 13:28:42.970314 3, 0xFFFF, sum = 0
5676 13:28:42.970836 4, 0xFFFF, sum = 0
5677 13:28:42.973133 5, 0xFFFF, sum = 0
5678 13:28:42.976350 6, 0xFFFF, sum = 0
5679 13:28:42.976743 7, 0xFFFF, sum = 0
5680 13:28:42.980437 8, 0xFFFF, sum = 0
5681 13:28:42.980900 9, 0xFFFF, sum = 0
5682 13:28:42.983268 10, 0x0, sum = 1
5683 13:28:42.983757 11, 0x0, sum = 2
5684 13:28:42.986227 12, 0x0, sum = 3
5685 13:28:42.986722 13, 0x0, sum = 4
5686 13:28:42.987009 best_step = 11
5687 13:28:42.987248
5688 13:28:42.990017 ==
5689 13:28:42.990544 Dram Type= 6, Freq= 0, CH_1, rank 1
5690 13:28:42.996428 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5691 13:28:42.996905 ==
5692 13:28:42.997190 RX Vref Scan: 0
5693 13:28:42.997433
5694 13:28:42.999538 RX Vref 0 -> 0, step: 1
5695 13:28:42.999919
5696 13:28:43.002906 RX Delay -69 -> 252, step: 4
5697 13:28:43.006508 iDelay=203, Bit 0, Center 96 (7 ~ 186) 180
5698 13:28:43.013087 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5699 13:28:43.016335 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5700 13:28:43.019787 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5701 13:28:43.023086 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5702 13:28:43.026162 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5703 13:28:43.029348 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5704 13:28:43.036406 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5705 13:28:43.039678 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5706 13:28:43.042917 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5707 13:28:43.046052 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5708 13:28:43.049401 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5709 13:28:43.056265 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5710 13:28:43.059609 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5711 13:28:43.062879 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5712 13:28:43.065779 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5713 13:28:43.066102 ==
5714 13:28:43.068977 Dram Type= 6, Freq= 0, CH_1, rank 1
5715 13:28:43.072486 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5716 13:28:43.075997 ==
5717 13:28:43.076518 DQS Delay:
5718 13:28:43.076805 DQS0 = 0, DQS1 = 0
5719 13:28:43.078929 DQM Delay:
5720 13:28:43.079305 DQM0 = 95, DQM1 = 87
5721 13:28:43.082223 DQ Delay:
5722 13:28:43.082600 DQ0 =96, DQ1 =90, DQ2 =88, DQ3 =92
5723 13:28:43.085595 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5724 13:28:43.088704 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =80
5725 13:28:43.092318 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
5726 13:28:43.095621
5727 13:28:43.096141
5728 13:28:43.102328 [DQSOSCAuto] RK1, (LSB)MR18= 0x2222, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5729 13:28:43.105482 CH1 RK1: MR19=505, MR18=2222
5730 13:28:43.112432 CH1_RK1: MR19=0x505, MR18=0x2222, DQSOSC=411, MR23=63, INC=64, DEC=42
5731 13:28:43.115707 [RxdqsGatingPostProcess] freq 933
5732 13:28:43.118908 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5733 13:28:43.122266 Pre-setting of DQS Precalculation
5734 13:28:43.129011 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5735 13:28:43.135687 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5736 13:28:43.142308 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5737 13:28:43.142795
5738 13:28:43.143066
5739 13:28:43.145502 [Calibration Summary] 1866 Mbps
5740 13:28:43.146028 CH 0, Rank 0
5741 13:28:43.148928 SW Impedance : PASS
5742 13:28:43.152091 DUTY Scan : NO K
5743 13:28:43.152511 ZQ Calibration : PASS
5744 13:28:43.155041 Jitter Meter : NO K
5745 13:28:43.158982 CBT Training : PASS
5746 13:28:43.159468 Write leveling : PASS
5747 13:28:43.161617 RX DQS gating : PASS
5748 13:28:43.165325 RX DQ/DQS(RDDQC) : PASS
5749 13:28:43.165807 TX DQ/DQS : PASS
5750 13:28:43.168675 RX DATLAT : PASS
5751 13:28:43.172058 RX DQ/DQS(Engine): PASS
5752 13:28:43.172584 TX OE : NO K
5753 13:28:43.172877 All Pass.
5754 13:28:43.174896
5755 13:28:43.175281 CH 0, Rank 1
5756 13:28:43.178674 SW Impedance : PASS
5757 13:28:43.179152 DUTY Scan : NO K
5758 13:28:43.181576 ZQ Calibration : PASS
5759 13:28:43.181926 Jitter Meter : NO K
5760 13:28:43.184892 CBT Training : PASS
5761 13:28:43.188779 Write leveling : PASS
5762 13:28:43.189230 RX DQS gating : PASS
5763 13:28:43.191349 RX DQ/DQS(RDDQC) : PASS
5764 13:28:43.195072 TX DQ/DQS : PASS
5765 13:28:43.195522 RX DATLAT : PASS
5766 13:28:43.198509 RX DQ/DQS(Engine): PASS
5767 13:28:43.201555 TX OE : NO K
5768 13:28:43.201945 All Pass.
5769 13:28:43.202219
5770 13:28:43.202458 CH 1, Rank 0
5771 13:28:43.204531 SW Impedance : PASS
5772 13:28:43.208432 DUTY Scan : NO K
5773 13:28:43.208915 ZQ Calibration : PASS
5774 13:28:43.211622 Jitter Meter : NO K
5775 13:28:43.214910 CBT Training : PASS
5776 13:28:43.215390 Write leveling : PASS
5777 13:28:43.217908 RX DQS gating : PASS
5778 13:28:43.221624 RX DQ/DQS(RDDQC) : PASS
5779 13:28:43.222105 TX DQ/DQS : PASS
5780 13:28:43.224663 RX DATLAT : PASS
5781 13:28:43.228595 RX DQ/DQS(Engine): PASS
5782 13:28:43.229082 TX OE : NO K
5783 13:28:43.229372 All Pass.
5784 13:28:43.231658
5785 13:28:43.232039 CH 1, Rank 1
5786 13:28:43.234817 SW Impedance : PASS
5787 13:28:43.235302 DUTY Scan : NO K
5788 13:28:43.237858 ZQ Calibration : PASS
5789 13:28:43.241387 Jitter Meter : NO K
5790 13:28:43.241867 CBT Training : PASS
5791 13:28:43.244324 Write leveling : PASS
5792 13:28:43.244706 RX DQS gating : PASS
5793 13:28:43.247853 RX DQ/DQS(RDDQC) : PASS
5794 13:28:43.251287 TX DQ/DQS : PASS
5795 13:28:43.251669 RX DATLAT : PASS
5796 13:28:43.254577 RX DQ/DQS(Engine): PASS
5797 13:28:43.257637 TX OE : NO K
5798 13:28:43.258101 All Pass.
5799 13:28:43.258395
5800 13:28:43.260891 DramC Write-DBI off
5801 13:28:43.261276 PER_BANK_REFRESH: Hybrid Mode
5802 13:28:43.264833 TX_TRACKING: ON
5803 13:28:43.274304 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5804 13:28:43.277508 [FAST_K] Save calibration result to emmc
5805 13:28:43.280968 dramc_set_vcore_voltage set vcore to 650000
5806 13:28:43.281451 Read voltage for 400, 6
5807 13:28:43.284347 Vio18 = 0
5808 13:28:43.284731 Vcore = 650000
5809 13:28:43.285005 Vdram = 0
5810 13:28:43.287722 Vddq = 0
5811 13:28:43.288093 Vmddr = 0
5812 13:28:43.291024 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5813 13:28:43.297786 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5814 13:28:43.300674 MEM_TYPE=3, freq_sel=20
5815 13:28:43.304606 sv_algorithm_assistance_LP4_800
5816 13:28:43.307725 ============ PULL DRAM RESETB DOWN ============
5817 13:28:43.311285 ========== PULL DRAM RESETB DOWN end =========
5818 13:28:43.317645 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5819 13:28:43.321028 ===================================
5820 13:28:43.321515 LPDDR4 DRAM CONFIGURATION
5821 13:28:43.324167 ===================================
5822 13:28:43.327198 EX_ROW_EN[0] = 0x0
5823 13:28:43.327592 EX_ROW_EN[1] = 0x0
5824 13:28:43.330411 LP4Y_EN = 0x0
5825 13:28:43.330683 WORK_FSP = 0x0
5826 13:28:43.333882 WL = 0x2
5827 13:28:43.337877 RL = 0x2
5828 13:28:43.338322 BL = 0x2
5829 13:28:43.341068 RPST = 0x0
5830 13:28:43.341568 RD_PRE = 0x0
5831 13:28:43.344185 WR_PRE = 0x1
5832 13:28:43.344703 WR_PST = 0x0
5833 13:28:43.347716 DBI_WR = 0x0
5834 13:28:43.348193 DBI_RD = 0x0
5835 13:28:43.350668 OTF = 0x1
5836 13:28:43.354100 ===================================
5837 13:28:43.357375 ===================================
5838 13:28:43.357865 ANA top config
5839 13:28:43.361070 ===================================
5840 13:28:43.363867 DLL_ASYNC_EN = 0
5841 13:28:43.367642 ALL_SLAVE_EN = 1
5842 13:28:43.368129 NEW_RANK_MODE = 1
5843 13:28:43.371246 DLL_IDLE_MODE = 1
5844 13:28:43.374068 LP45_APHY_COMB_EN = 1
5845 13:28:43.377530 TX_ODT_DIS = 1
5846 13:28:43.380570 NEW_8X_MODE = 1
5847 13:28:43.383614 ===================================
5848 13:28:43.384051 ===================================
5849 13:28:43.387460 data_rate = 800
5850 13:28:43.390945 CKR = 1
5851 13:28:43.394004 DQ_P2S_RATIO = 4
5852 13:28:43.397168 ===================================
5853 13:28:43.400150 CA_P2S_RATIO = 4
5854 13:28:43.404393 DQ_CA_OPEN = 0
5855 13:28:43.407046 DQ_SEMI_OPEN = 1
5856 13:28:43.407531 CA_SEMI_OPEN = 1
5857 13:28:43.411085 CA_FULL_RATE = 0
5858 13:28:43.413535 DQ_CKDIV4_EN = 0
5859 13:28:43.416931 CA_CKDIV4_EN = 1
5860 13:28:43.420113 CA_PREDIV_EN = 0
5861 13:28:43.423381 PH8_DLY = 0
5862 13:28:43.423862 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5863 13:28:43.426809 DQ_AAMCK_DIV = 0
5864 13:28:43.429729 CA_AAMCK_DIV = 0
5865 13:28:43.433143 CA_ADMCK_DIV = 4
5866 13:28:43.436853 DQ_TRACK_CA_EN = 0
5867 13:28:43.440230 CA_PICK = 800
5868 13:28:43.440757 CA_MCKIO = 400
5869 13:28:43.443383 MCKIO_SEMI = 400
5870 13:28:43.446854 PLL_FREQ = 3016
5871 13:28:43.450085 DQ_UI_PI_RATIO = 32
5872 13:28:43.453689 CA_UI_PI_RATIO = 32
5873 13:28:43.456759 ===================================
5874 13:28:43.460075 ===================================
5875 13:28:43.463917 memory_type:LPDDR4
5876 13:28:43.464507 GP_NUM : 10
5877 13:28:43.466595 SRAM_EN : 1
5878 13:28:43.469910 MD32_EN : 0
5879 13:28:43.473130 ===================================
5880 13:28:43.473525 [ANA_INIT] >>>>>>>>>>>>>>
5881 13:28:43.476374 <<<<<< [CONFIGURE PHASE]: ANA_TX
5882 13:28:43.480269 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5883 13:28:43.483432 ===================================
5884 13:28:43.486628 data_rate = 800,PCW = 0X7400
5885 13:28:43.490052 ===================================
5886 13:28:43.493786 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5887 13:28:43.500183 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5888 13:28:43.509933 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5889 13:28:43.513100 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5890 13:28:43.519505 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5891 13:28:43.523113 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5892 13:28:43.523497 [ANA_INIT] flow start
5893 13:28:43.526226 [ANA_INIT] PLL >>>>>>>>
5894 13:28:43.529770 [ANA_INIT] PLL <<<<<<<<
5895 13:28:43.530137 [ANA_INIT] MIDPI >>>>>>>>
5896 13:28:43.532839 [ANA_INIT] MIDPI <<<<<<<<
5897 13:28:43.536615 [ANA_INIT] DLL >>>>>>>>
5898 13:28:43.537101 [ANA_INIT] flow end
5899 13:28:43.539733 ============ LP4 DIFF to SE enter ============
5900 13:28:43.546506 ============ LP4 DIFF to SE exit ============
5901 13:28:43.547000 [ANA_INIT] <<<<<<<<<<<<<
5902 13:28:43.549640 [Flow] Enable top DCM control >>>>>
5903 13:28:43.553020 [Flow] Enable top DCM control <<<<<
5904 13:28:43.556252 Enable DLL master slave shuffle
5905 13:28:43.562762 ==============================================================
5906 13:28:43.563253 Gating Mode config
5907 13:28:43.570098 ==============================================================
5908 13:28:43.572861 Config description:
5909 13:28:43.582642 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5910 13:28:43.589260 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5911 13:28:43.592634 SELPH_MODE 0: By rank 1: By Phase
5912 13:28:43.599322 ==============================================================
5913 13:28:43.602879 GAT_TRACK_EN = 0
5914 13:28:43.606228 RX_GATING_MODE = 2
5915 13:28:43.606707 RX_GATING_TRACK_MODE = 2
5916 13:28:43.609612 SELPH_MODE = 1
5917 13:28:43.612828 PICG_EARLY_EN = 1
5918 13:28:43.616053 VALID_LAT_VALUE = 1
5919 13:28:43.622652 ==============================================================
5920 13:28:43.625596 Enter into Gating configuration >>>>
5921 13:28:43.629617 Exit from Gating configuration <<<<
5922 13:28:43.632366 Enter into DVFS_PRE_config >>>>>
5923 13:28:43.642880 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5924 13:28:43.645798 Exit from DVFS_PRE_config <<<<<
5925 13:28:43.649092 Enter into PICG configuration >>>>
5926 13:28:43.652682 Exit from PICG configuration <<<<
5927 13:28:43.655882 [RX_INPUT] configuration >>>>>
5928 13:28:43.659019 [RX_INPUT] configuration <<<<<
5929 13:28:43.662472 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5930 13:28:43.669050 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5931 13:28:43.676318 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5932 13:28:43.682399 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5933 13:28:43.685495 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5934 13:28:43.692700 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5935 13:28:43.695462 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5936 13:28:43.702281 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5937 13:28:43.705531 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5938 13:28:43.708907 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5939 13:28:43.711897 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5940 13:28:43.718924 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5941 13:28:43.722239 ===================================
5942 13:28:43.725590 LPDDR4 DRAM CONFIGURATION
5943 13:28:43.726099 ===================================
5944 13:28:43.728897 EX_ROW_EN[0] = 0x0
5945 13:28:43.732045 EX_ROW_EN[1] = 0x0
5946 13:28:43.732545 LP4Y_EN = 0x0
5947 13:28:43.735104 WORK_FSP = 0x0
5948 13:28:43.735489 WL = 0x2
5949 13:28:43.738415 RL = 0x2
5950 13:28:43.738796 BL = 0x2
5951 13:28:43.742228 RPST = 0x0
5952 13:28:43.742735 RD_PRE = 0x0
5953 13:28:43.745078 WR_PRE = 0x1
5954 13:28:43.745564 WR_PST = 0x0
5955 13:28:43.748930 DBI_WR = 0x0
5956 13:28:43.749415 DBI_RD = 0x0
5957 13:28:43.751959 OTF = 0x1
5958 13:28:43.755320 ===================================
5959 13:28:43.758612 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5960 13:28:43.762011 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5961 13:28:43.768444 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5962 13:28:43.771803 ===================================
5963 13:28:43.772323 LPDDR4 DRAM CONFIGURATION
5964 13:28:43.774815 ===================================
5965 13:28:43.778111 EX_ROW_EN[0] = 0x10
5966 13:28:43.781065 EX_ROW_EN[1] = 0x0
5967 13:28:43.781448 LP4Y_EN = 0x0
5968 13:28:43.784935 WORK_FSP = 0x0
5969 13:28:43.785321 WL = 0x2
5970 13:28:43.788421 RL = 0x2
5971 13:28:43.788909 BL = 0x2
5972 13:28:43.791043 RPST = 0x0
5973 13:28:43.791427 RD_PRE = 0x0
5974 13:28:43.794802 WR_PRE = 0x1
5975 13:28:43.795270 WR_PST = 0x0
5976 13:28:43.798023 DBI_WR = 0x0
5977 13:28:43.798374 DBI_RD = 0x0
5978 13:28:43.800734 OTF = 0x1
5979 13:28:43.804549 ===================================
5980 13:28:43.811074 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5981 13:28:43.814378 nWR fixed to 30
5982 13:28:43.817817 [ModeRegInit_LP4] CH0 RK0
5983 13:28:43.818267 [ModeRegInit_LP4] CH0 RK1
5984 13:28:43.821452 [ModeRegInit_LP4] CH1 RK0
5985 13:28:43.824693 [ModeRegInit_LP4] CH1 RK1
5986 13:28:43.825179 match AC timing 18
5987 13:28:43.831798 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5988 13:28:43.834796 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5989 13:28:43.837658 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5990 13:28:43.844266 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5991 13:28:43.847843 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5992 13:28:43.848410 ==
5993 13:28:43.851096 Dram Type= 6, Freq= 0, CH_0, rank 0
5994 13:28:43.854890 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5995 13:28:43.855409 ==
5996 13:28:43.861247 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5997 13:28:43.867553 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5998 13:28:43.871600 [CA 0] Center 36 (8~64) winsize 57
5999 13:28:43.874516 [CA 1] Center 36 (8~64) winsize 57
6000 13:28:43.877350 [CA 2] Center 36 (8~64) winsize 57
6001 13:28:43.877777 [CA 3] Center 36 (8~64) winsize 57
6002 13:28:43.880913 [CA 4] Center 36 (8~64) winsize 57
6003 13:28:43.884009 [CA 5] Center 36 (8~64) winsize 57
6004 13:28:43.884519
6005 13:28:43.887450 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6006 13:28:43.890765
6007 13:28:43.894773 [CATrainingPosCal] consider 1 rank data
6008 13:28:43.895233 u2DelayCellTimex100 = 270/100 ps
6009 13:28:43.900859 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6010 13:28:43.904390 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6011 13:28:43.908141 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6012 13:28:43.911425 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6013 13:28:43.914470 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6014 13:28:43.917837 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6015 13:28:43.918245
6016 13:28:43.921494 CA PerBit enable=1, Macro0, CA PI delay=36
6017 13:28:43.921985
6018 13:28:43.924023 [CBTSetCACLKResult] CA Dly = 36
6019 13:28:43.927603 CS Dly: 1 (0~32)
6020 13:28:43.927967 ==
6021 13:28:43.931150 Dram Type= 6, Freq= 0, CH_0, rank 1
6022 13:28:43.934389 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6023 13:28:43.934872 ==
6024 13:28:43.940870 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6025 13:28:43.943648 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6026 13:28:43.947436 [CA 0] Center 36 (8~64) winsize 57
6027 13:28:43.950768 [CA 1] Center 36 (8~64) winsize 57
6028 13:28:43.954064 [CA 2] Center 36 (8~64) winsize 57
6029 13:28:43.957368 [CA 3] Center 36 (8~64) winsize 57
6030 13:28:43.960373 [CA 4] Center 36 (8~64) winsize 57
6031 13:28:43.964036 [CA 5] Center 36 (8~64) winsize 57
6032 13:28:43.964569
6033 13:28:43.967157 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6034 13:28:43.967536
6035 13:28:43.970585 [CATrainingPosCal] consider 2 rank data
6036 13:28:43.974385 u2DelayCellTimex100 = 270/100 ps
6037 13:28:43.976787 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6038 13:28:43.980310 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6039 13:28:43.986736 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6040 13:28:43.990518 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6041 13:28:43.993315 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6042 13:28:43.996625 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6043 13:28:43.996970
6044 13:28:44.000662 CA PerBit enable=1, Macro0, CA PI delay=36
6045 13:28:44.001154
6046 13:28:44.003441 [CBTSetCACLKResult] CA Dly = 36
6047 13:28:44.003821 CS Dly: 1 (0~32)
6048 13:28:44.004092
6049 13:28:44.006990 ----->DramcWriteLeveling(PI) begin...
6050 13:28:44.010341 ==
6051 13:28:44.010831 Dram Type= 6, Freq= 0, CH_0, rank 0
6052 13:28:44.017246 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6053 13:28:44.017743 ==
6054 13:28:44.019893 Write leveling (Byte 0): 32 => 0
6055 13:28:44.023728 Write leveling (Byte 1): 32 => 0
6056 13:28:44.024112 DramcWriteLeveling(PI) end<-----
6057 13:28:44.026849
6058 13:28:44.027229 ==
6059 13:28:44.030360 Dram Type= 6, Freq= 0, CH_0, rank 0
6060 13:28:44.033191 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6061 13:28:44.033547 ==
6062 13:28:44.036828 [Gating] SW mode calibration
6063 13:28:44.043671 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6064 13:28:44.046163 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6065 13:28:44.053149 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6066 13:28:44.056339 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6067 13:28:44.059550 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6068 13:28:44.066123 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6069 13:28:44.069635 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6070 13:28:44.073019 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6071 13:28:44.079755 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6072 13:28:44.082921 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6073 13:28:44.086301 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6074 13:28:44.089443 Total UI for P1: 0, mck2ui 16
6075 13:28:44.092985 best dqsien dly found for B0: ( 0, 10, 16)
6076 13:28:44.095610 Total UI for P1: 0, mck2ui 16
6077 13:28:44.099085 best dqsien dly found for B1: ( 0, 10, 24)
6078 13:28:44.102054 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6079 13:28:44.109093 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6080 13:28:44.109451
6081 13:28:44.112586 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6082 13:28:44.115565 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6083 13:28:44.118933 [Gating] SW calibration Done
6084 13:28:44.119388 ==
6085 13:28:44.122176 Dram Type= 6, Freq= 0, CH_0, rank 0
6086 13:28:44.125812 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6087 13:28:44.126265 ==
6088 13:28:44.129109 RX Vref Scan: 0
6089 13:28:44.129380
6090 13:28:44.129571 RX Vref 0 -> 0, step: 1
6091 13:28:44.129745
6092 13:28:44.132776 RX Delay -410 -> 252, step: 16
6093 13:28:44.138652 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6094 13:28:44.142353 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6095 13:28:44.145342 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6096 13:28:44.148819 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6097 13:28:44.155586 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6098 13:28:44.158852 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6099 13:28:44.161985 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6100 13:28:44.165163 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6101 13:28:44.171818 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6102 13:28:44.175337 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6103 13:28:44.178879 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6104 13:28:44.182232 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6105 13:28:44.188191 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6106 13:28:44.191589 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6107 13:28:44.195288 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6108 13:28:44.198855 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6109 13:28:44.201755 ==
6110 13:28:44.204705 Dram Type= 6, Freq= 0, CH_0, rank 0
6111 13:28:44.208456 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6112 13:28:44.208950 ==
6113 13:28:44.209247 DQS Delay:
6114 13:28:44.211921 DQS0 = 51, DQS1 = 59
6115 13:28:44.212347 DQM Delay:
6116 13:28:44.215003 DQM0 = 12, DQM1 = 16
6117 13:28:44.215387 DQ Delay:
6118 13:28:44.218493 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6119 13:28:44.221300 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6120 13:28:44.224589 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6121 13:28:44.228705 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6122 13:28:44.229086
6123 13:28:44.229360
6124 13:28:44.229602 ==
6125 13:28:44.231047 Dram Type= 6, Freq= 0, CH_0, rank 0
6126 13:28:44.234433 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6127 13:28:44.234803 ==
6128 13:28:44.235061
6129 13:28:44.235280
6130 13:28:44.237562 TX Vref Scan disable
6131 13:28:44.237914 == TX Byte 0 ==
6132 13:28:44.244435 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6133 13:28:44.247672 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6134 13:28:44.248085 == TX Byte 1 ==
6135 13:28:44.254623 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6136 13:28:44.257739 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6137 13:28:44.258094 ==
6138 13:28:44.260805 Dram Type= 6, Freq= 0, CH_0, rank 0
6139 13:28:44.264602 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6140 13:28:44.265118 ==
6141 13:28:44.265394
6142 13:28:44.267984
6143 13:28:44.268512 TX Vref Scan disable
6144 13:28:44.270926 == TX Byte 0 ==
6145 13:28:44.274262 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6146 13:28:44.277306 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6147 13:28:44.280882 == TX Byte 1 ==
6148 13:28:44.284153 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6149 13:28:44.287622 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6150 13:28:44.288096
6151 13:28:44.290848 [DATLAT]
6152 13:28:44.291302 Freq=400, CH0 RK0
6153 13:28:44.291581
6154 13:28:44.294497 DATLAT Default: 0xf
6155 13:28:44.294974 0, 0xFFFF, sum = 0
6156 13:28:44.297477 1, 0xFFFF, sum = 0
6157 13:28:44.297832 2, 0xFFFF, sum = 0
6158 13:28:44.300229 3, 0xFFFF, sum = 0
6159 13:28:44.300534 4, 0xFFFF, sum = 0
6160 13:28:44.303471 5, 0xFFFF, sum = 0
6161 13:28:44.303846 6, 0xFFFF, sum = 0
6162 13:28:44.307036 7, 0xFFFF, sum = 0
6163 13:28:44.307511 8, 0xFFFF, sum = 0
6164 13:28:44.310485 9, 0xFFFF, sum = 0
6165 13:28:44.310952 10, 0xFFFF, sum = 0
6166 13:28:44.314435 11, 0xFFFF, sum = 0
6167 13:28:44.314883 12, 0x0, sum = 1
6168 13:28:44.317050 13, 0x0, sum = 2
6169 13:28:44.317404 14, 0x0, sum = 3
6170 13:28:44.320507 15, 0x0, sum = 4
6171 13:28:44.320861 best_step = 13
6172 13:28:44.321113
6173 13:28:44.321334 ==
6174 13:28:44.323649 Dram Type= 6, Freq= 0, CH_0, rank 0
6175 13:28:44.331225 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6176 13:28:44.331731 ==
6177 13:28:44.332071 RX Vref Scan: 1
6178 13:28:44.332358
6179 13:28:44.334070 RX Vref 0 -> 0, step: 1
6180 13:28:44.334416
6181 13:28:44.337248 RX Delay -359 -> 252, step: 8
6182 13:28:44.337596
6183 13:28:44.340542 Set Vref, RX VrefLevel [Byte0]: 47
6184 13:28:44.344313 [Byte1]: 48
6185 13:28:44.344780
6186 13:28:44.347668 Final RX Vref Byte 0 = 47 to rank0
6187 13:28:44.350671 Final RX Vref Byte 1 = 48 to rank0
6188 13:28:44.353657 Final RX Vref Byte 0 = 47 to rank1
6189 13:28:44.357475 Final RX Vref Byte 1 = 48 to rank1==
6190 13:28:44.360375 Dram Type= 6, Freq= 0, CH_0, rank 0
6191 13:28:44.363888 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6192 13:28:44.366801 ==
6193 13:28:44.367268 DQS Delay:
6194 13:28:44.367544 DQS0 = 52, DQS1 = 68
6195 13:28:44.370319 DQM Delay:
6196 13:28:44.370673 DQM0 = 9, DQM1 = 16
6197 13:28:44.373663 DQ Delay:
6198 13:28:44.374088 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6199 13:28:44.376653 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6200 13:28:44.380169 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6201 13:28:44.383301 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6202 13:28:44.383713
6203 13:28:44.383979
6204 13:28:44.393562 [DQSOSCAuto] RK0, (LSB)MR18= 0xa0a0, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6205 13:28:44.396849 CH0 RK0: MR19=C0C, MR18=A0A0
6206 13:28:44.403777 CH0_RK0: MR19=0xC0C, MR18=0xA0A0, DQSOSC=389, MR23=63, INC=390, DEC=260
6207 13:28:44.404254 ==
6208 13:28:44.407064 Dram Type= 6, Freq= 0, CH_0, rank 1
6209 13:28:44.410143 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6210 13:28:44.410637 ==
6211 13:28:44.414026 [Gating] SW mode calibration
6212 13:28:44.419986 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6213 13:28:44.423706 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6214 13:28:44.429952 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6215 13:28:44.433286 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6216 13:28:44.436965 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6217 13:28:44.443024 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6218 13:28:44.446811 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6219 13:28:44.450027 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6220 13:28:44.456386 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6221 13:28:44.459463 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6222 13:28:44.463343 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6223 13:28:44.466199 Total UI for P1: 0, mck2ui 16
6224 13:28:44.469729 best dqsien dly found for B0: ( 0, 10, 16)
6225 13:28:44.472722 Total UI for P1: 0, mck2ui 16
6226 13:28:44.476137 best dqsien dly found for B1: ( 0, 10, 24)
6227 13:28:44.479166 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6228 13:28:44.482638 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6229 13:28:44.486229
6230 13:28:44.489212 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6231 13:28:44.492136 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6232 13:28:44.496018 [Gating] SW calibration Done
6233 13:28:44.496503 ==
6234 13:28:44.498943 Dram Type= 6, Freq= 0, CH_0, rank 1
6235 13:28:44.502229 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6236 13:28:44.502581 ==
6237 13:28:44.506331 RX Vref Scan: 0
6238 13:28:44.506734
6239 13:28:44.506984 RX Vref 0 -> 0, step: 1
6240 13:28:44.507209
6241 13:28:44.509246 RX Delay -410 -> 252, step: 16
6242 13:28:44.513037 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6243 13:28:44.519281 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6244 13:28:44.522603 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6245 13:28:44.525525 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6246 13:28:44.532298 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6247 13:28:44.535425 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6248 13:28:44.539267 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6249 13:28:44.542458 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6250 13:28:44.548738 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6251 13:28:44.552241 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6252 13:28:44.555440 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6253 13:28:44.559053 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6254 13:28:44.565201 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6255 13:28:44.568381 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6256 13:28:44.571757 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6257 13:28:44.575068 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6258 13:28:44.578193 ==
6259 13:28:44.581663 Dram Type= 6, Freq= 0, CH_0, rank 1
6260 13:28:44.584787 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6261 13:28:44.585138 ==
6262 13:28:44.585386 DQS Delay:
6263 13:28:44.588308 DQS0 = 43, DQS1 = 59
6264 13:28:44.588659 DQM Delay:
6265 13:28:44.591459 DQM0 = 7, DQM1 = 15
6266 13:28:44.591805 DQ Delay:
6267 13:28:44.595105 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6268 13:28:44.597968 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6269 13:28:44.601923 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6270 13:28:44.604819 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6271 13:28:44.605175
6272 13:28:44.605428
6273 13:28:44.605645 ==
6274 13:28:44.608095 Dram Type= 6, Freq= 0, CH_0, rank 1
6275 13:28:44.611668 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6276 13:28:44.612207 ==
6277 13:28:44.612536
6278 13:28:44.612761
6279 13:28:44.614510 TX Vref Scan disable
6280 13:28:44.614886 == TX Byte 0 ==
6281 13:28:44.621571 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6282 13:28:44.624892 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6283 13:28:44.625346 == TX Byte 1 ==
6284 13:28:44.631532 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6285 13:28:44.634945 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6286 13:28:44.635405 ==
6287 13:28:44.638126 Dram Type= 6, Freq= 0, CH_0, rank 1
6288 13:28:44.641896 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6289 13:28:44.642386 ==
6290 13:28:44.642772
6291 13:28:44.643024
6292 13:28:44.644530 TX Vref Scan disable
6293 13:28:44.644926 == TX Byte 0 ==
6294 13:28:44.651186 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6295 13:28:44.654700 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6296 13:28:44.655196 == TX Byte 1 ==
6297 13:28:44.661121 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6298 13:28:44.664622 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6299 13:28:44.665116
6300 13:28:44.665388 [DATLAT]
6301 13:28:44.667630 Freq=400, CH0 RK1
6302 13:28:44.668017
6303 13:28:44.668318 DATLAT Default: 0xd
6304 13:28:44.670822 0, 0xFFFF, sum = 0
6305 13:28:44.671229 1, 0xFFFF, sum = 0
6306 13:28:44.674296 2, 0xFFFF, sum = 0
6307 13:28:44.674767 3, 0xFFFF, sum = 0
6308 13:28:44.677411 4, 0xFFFF, sum = 0
6309 13:28:44.677790 5, 0xFFFF, sum = 0
6310 13:28:44.680573 6, 0xFFFF, sum = 0
6311 13:28:44.681049 7, 0xFFFF, sum = 0
6312 13:28:44.684259 8, 0xFFFF, sum = 0
6313 13:28:44.687476 9, 0xFFFF, sum = 0
6314 13:28:44.687797 10, 0xFFFF, sum = 0
6315 13:28:44.690420 11, 0xFFFF, sum = 0
6316 13:28:44.690675 12, 0x0, sum = 1
6317 13:28:44.693889 13, 0x0, sum = 2
6318 13:28:44.694169 14, 0x0, sum = 3
6319 13:28:44.694383 15, 0x0, sum = 4
6320 13:28:44.697489 best_step = 13
6321 13:28:44.697835
6322 13:28:44.698087 ==
6323 13:28:44.700546 Dram Type= 6, Freq= 0, CH_0, rank 1
6324 13:28:44.703706 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6325 13:28:44.704078 ==
6326 13:28:44.707209 RX Vref Scan: 0
6327 13:28:44.707677
6328 13:28:44.710496 RX Vref 0 -> 0, step: 1
6329 13:28:44.710869
6330 13:28:44.711228 RX Delay -359 -> 252, step: 8
6331 13:28:44.719021 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6332 13:28:44.722239 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6333 13:28:44.725631 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6334 13:28:44.732006 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6335 13:28:44.735647 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6336 13:28:44.738805 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6337 13:28:44.742648 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6338 13:28:44.748684 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6339 13:28:44.752142 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6340 13:28:44.756148 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6341 13:28:44.758685 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6342 13:28:44.765615 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6343 13:28:44.768874 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6344 13:28:44.772390 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6345 13:28:44.775077 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6346 13:28:44.781876 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6347 13:28:44.782218 ==
6348 13:28:44.785348 Dram Type= 6, Freq= 0, CH_0, rank 1
6349 13:28:44.788625 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6350 13:28:44.788966 ==
6351 13:28:44.789212 DQS Delay:
6352 13:28:44.791661 DQS0 = 52, DQS1 = 64
6353 13:28:44.791932 DQM Delay:
6354 13:28:44.795678 DQM0 = 9, DQM1 = 13
6355 13:28:44.796219 DQ Delay:
6356 13:28:44.798506 DQ0 =4, DQ1 =12, DQ2 =8, DQ3 =4
6357 13:28:44.802045 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6358 13:28:44.805268 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6359 13:28:44.808298 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6360 13:28:44.808601
6361 13:28:44.808828
6362 13:28:44.815455 [DQSOSCAuto] RK1, (LSB)MR18= 0xb7b7, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6363 13:28:44.818456 CH0 RK1: MR19=C0C, MR18=B7B7
6364 13:28:44.825152 CH0_RK1: MR19=0xC0C, MR18=0xB7B7, DQSOSC=387, MR23=63, INC=394, DEC=262
6365 13:28:44.828124 [RxdqsGatingPostProcess] freq 400
6366 13:28:44.835747 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6367 13:28:44.838390 Pre-setting of DQS Precalculation
6368 13:28:44.841436 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6369 13:28:44.841829 ==
6370 13:28:44.844695 Dram Type= 6, Freq= 0, CH_1, rank 0
6371 13:28:44.848205 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6372 13:28:44.848618 ==
6373 13:28:44.855117 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6374 13:28:44.861440 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6375 13:28:44.864600 [CA 0] Center 36 (8~64) winsize 57
6376 13:28:44.867837 [CA 1] Center 36 (8~64) winsize 57
6377 13:28:44.871340 [CA 2] Center 36 (8~64) winsize 57
6378 13:28:44.874927 [CA 3] Center 36 (8~64) winsize 57
6379 13:28:44.877704 [CA 4] Center 36 (8~64) winsize 57
6380 13:28:44.878063 [CA 5] Center 36 (8~64) winsize 57
6381 13:28:44.881396
6382 13:28:44.884649 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6383 13:28:44.885001
6384 13:28:44.887764 [CATrainingPosCal] consider 1 rank data
6385 13:28:44.891224 u2DelayCellTimex100 = 270/100 ps
6386 13:28:44.894810 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6387 13:28:44.898070 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6388 13:28:44.901620 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6389 13:28:44.904440 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6390 13:28:44.908120 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6391 13:28:44.911170 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6392 13:28:44.911644
6393 13:28:44.915000 CA PerBit enable=1, Macro0, CA PI delay=36
6394 13:28:44.915451
6395 13:28:44.917570 [CBTSetCACLKResult] CA Dly = 36
6396 13:28:44.920912 CS Dly: 1 (0~32)
6397 13:28:44.921259 ==
6398 13:28:44.924392 Dram Type= 6, Freq= 0, CH_1, rank 1
6399 13:28:44.928148 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6400 13:28:44.928476 ==
6401 13:28:44.934148 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6402 13:28:44.941011 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6403 13:28:44.944104 [CA 0] Center 36 (8~64) winsize 57
6404 13:28:44.944484 [CA 1] Center 36 (8~64) winsize 57
6405 13:28:44.947491 [CA 2] Center 36 (8~64) winsize 57
6406 13:28:44.951115 [CA 3] Center 36 (8~64) winsize 57
6407 13:28:44.954517 [CA 4] Center 36 (8~64) winsize 57
6408 13:28:44.957383 [CA 5] Center 36 (8~64) winsize 57
6409 13:28:44.957744
6410 13:28:44.961454 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6411 13:28:44.961816
6412 13:28:44.964490 [CATrainingPosCal] consider 2 rank data
6413 13:28:44.967745 u2DelayCellTimex100 = 270/100 ps
6414 13:28:44.971062 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6415 13:28:44.977306 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6416 13:28:44.980406 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6417 13:28:44.983885 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6418 13:28:44.987546 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6419 13:28:44.990456 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6420 13:28:44.990751
6421 13:28:44.994419 CA PerBit enable=1, Macro0, CA PI delay=36
6422 13:28:44.994859
6423 13:28:44.997101 [CBTSetCACLKResult] CA Dly = 36
6424 13:28:45.000741 CS Dly: 1 (0~32)
6425 13:28:45.001086
6426 13:28:45.004475 ----->DramcWriteLeveling(PI) begin...
6427 13:28:45.004884 ==
6428 13:28:45.007646 Dram Type= 6, Freq= 0, CH_1, rank 0
6429 13:28:45.010421 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6430 13:28:45.010870 ==
6431 13:28:45.013815 Write leveling (Byte 0): 32 => 0
6432 13:28:45.017043 Write leveling (Byte 1): 32 => 0
6433 13:28:45.020917 DramcWriteLeveling(PI) end<-----
6434 13:28:45.021354
6435 13:28:45.021632 ==
6436 13:28:45.023993 Dram Type= 6, Freq= 0, CH_1, rank 0
6437 13:28:45.027062 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6438 13:28:45.027406 ==
6439 13:28:45.031190 [Gating] SW mode calibration
6440 13:28:45.037197 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6441 13:28:45.043959 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6442 13:28:45.047588 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6443 13:28:45.050910 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6444 13:28:45.057070 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6445 13:28:45.060706 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6446 13:28:45.063665 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6447 13:28:45.067349 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6448 13:28:45.073893 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6449 13:28:45.077038 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6450 13:28:45.080591 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6451 13:28:45.083252 Total UI for P1: 0, mck2ui 16
6452 13:28:45.087321 best dqsien dly found for B0: ( 0, 10, 16)
6453 13:28:45.090201 Total UI for P1: 0, mck2ui 16
6454 13:28:45.093250 best dqsien dly found for B1: ( 0, 10, 16)
6455 13:28:45.100444 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6456 13:28:45.103320 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6457 13:28:45.103703
6458 13:28:45.106766 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6459 13:28:45.110150 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6460 13:28:45.113184 [Gating] SW calibration Done
6461 13:28:45.113575 ==
6462 13:28:45.116548 Dram Type= 6, Freq= 0, CH_1, rank 0
6463 13:28:45.119593 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6464 13:28:45.119971 ==
6465 13:28:45.123356 RX Vref Scan: 0
6466 13:28:45.123731
6467 13:28:45.123995 RX Vref 0 -> 0, step: 1
6468 13:28:45.124236
6469 13:28:45.126659 RX Delay -410 -> 252, step: 16
6470 13:28:45.133277 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6471 13:28:45.136262 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6472 13:28:45.139673 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6473 13:28:45.142928 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6474 13:28:45.149475 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6475 13:28:45.153108 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6476 13:28:45.156632 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6477 13:28:45.159639 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6478 13:28:45.166461 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6479 13:28:45.169527 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6480 13:28:45.172507 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6481 13:28:45.175946 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6482 13:28:45.182397 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6483 13:28:45.186426 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6484 13:28:45.189291 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6485 13:28:45.195803 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6486 13:28:45.196155 ==
6487 13:28:45.199308 Dram Type= 6, Freq= 0, CH_1, rank 0
6488 13:28:45.202542 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6489 13:28:45.203003 ==
6490 13:28:45.203349 DQS Delay:
6491 13:28:45.205810 DQS0 = 43, DQS1 = 59
6492 13:28:45.206195 DQM Delay:
6493 13:28:45.209034 DQM0 = 6, DQM1 = 15
6494 13:28:45.209382 DQ Delay:
6495 13:28:45.212575 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6496 13:28:45.215298 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6497 13:28:45.218750 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6498 13:28:45.222301 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6499 13:28:45.222692
6500 13:28:45.222940
6501 13:28:45.223151 ==
6502 13:28:45.225460 Dram Type= 6, Freq= 0, CH_1, rank 0
6503 13:28:45.228681 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6504 13:28:45.229034 ==
6505 13:28:45.229283
6506 13:28:45.229502
6507 13:28:45.232458 TX Vref Scan disable
6508 13:28:45.232806 == TX Byte 0 ==
6509 13:28:45.238716 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6510 13:28:45.242693 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6511 13:28:45.243143 == TX Byte 1 ==
6512 13:28:45.248941 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6513 13:28:45.252027 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6514 13:28:45.252430 ==
6515 13:28:45.255784 Dram Type= 6, Freq= 0, CH_1, rank 0
6516 13:28:45.258716 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6517 13:28:45.259062 ==
6518 13:28:45.259313
6519 13:28:45.259531
6520 13:28:45.262273 TX Vref Scan disable
6521 13:28:45.265470 == TX Byte 0 ==
6522 13:28:45.268901 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6523 13:28:45.271970 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6524 13:28:45.275299 == TX Byte 1 ==
6525 13:28:45.278533 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6526 13:28:45.281739 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6527 13:28:45.282116
6528 13:28:45.282362 [DATLAT]
6529 13:28:45.285340 Freq=400, CH1 RK0
6530 13:28:45.285685
6531 13:28:45.288529 DATLAT Default: 0xf
6532 13:28:45.288874 0, 0xFFFF, sum = 0
6533 13:28:45.291507 1, 0xFFFF, sum = 0
6534 13:28:45.291866 2, 0xFFFF, sum = 0
6535 13:28:45.295223 3, 0xFFFF, sum = 0
6536 13:28:45.295568 4, 0xFFFF, sum = 0
6537 13:28:45.298841 5, 0xFFFF, sum = 0
6538 13:28:45.299200 6, 0xFFFF, sum = 0
6539 13:28:45.301940 7, 0xFFFF, sum = 0
6540 13:28:45.302401 8, 0xFFFF, sum = 0
6541 13:28:45.304954 9, 0xFFFF, sum = 0
6542 13:28:45.305423 10, 0xFFFF, sum = 0
6543 13:28:45.308406 11, 0xFFFF, sum = 0
6544 13:28:45.308870 12, 0x0, sum = 1
6545 13:28:45.311766 13, 0x0, sum = 2
6546 13:28:45.312228 14, 0x0, sum = 3
6547 13:28:45.314971 15, 0x0, sum = 4
6548 13:28:45.315432 best_step = 13
6549 13:28:45.315724
6550 13:28:45.315968 ==
6551 13:28:45.318436 Dram Type= 6, Freq= 0, CH_1, rank 0
6552 13:28:45.325098 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6553 13:28:45.325635 ==
6554 13:28:45.325972 RX Vref Scan: 1
6555 13:28:45.326205
6556 13:28:45.328156 RX Vref 0 -> 0, step: 1
6557 13:28:45.328532
6558 13:28:45.331781 RX Delay -359 -> 252, step: 8
6559 13:28:45.332307
6560 13:28:45.334636 Set Vref, RX VrefLevel [Byte0]: 52
6561 13:28:45.338202 [Byte1]: 48
6562 13:28:45.338648
6563 13:28:45.341445 Final RX Vref Byte 0 = 52 to rank0
6564 13:28:45.344883 Final RX Vref Byte 1 = 48 to rank0
6565 13:28:45.348125 Final RX Vref Byte 0 = 52 to rank1
6566 13:28:45.351239 Final RX Vref Byte 1 = 48 to rank1==
6567 13:28:45.354793 Dram Type= 6, Freq= 0, CH_1, rank 0
6568 13:28:45.358030 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6569 13:28:45.361883 ==
6570 13:28:45.362371 DQS Delay:
6571 13:28:45.362652 DQS0 = 48, DQS1 = 64
6572 13:28:45.364373 DQM Delay:
6573 13:28:45.364748 DQM0 = 8, DQM1 = 15
6574 13:28:45.368154 DQ Delay:
6575 13:28:45.368643 DQ0 =8, DQ1 =4, DQ2 =0, DQ3 =8
6576 13:28:45.371320 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6577 13:28:45.374579 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6578 13:28:45.377743 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6579 13:28:45.378086
6580 13:28:45.378415
6581 13:28:45.387734 [DQSOSCAuto] RK0, (LSB)MR18= 0xcdcd, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6582 13:28:45.391100 CH1 RK0: MR19=C0C, MR18=CDCD
6583 13:28:45.397687 CH1_RK0: MR19=0xC0C, MR18=0xCDCD, DQSOSC=384, MR23=63, INC=400, DEC=267
6584 13:28:45.398138 ==
6585 13:28:45.400771 Dram Type= 6, Freq= 0, CH_1, rank 1
6586 13:28:45.404244 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6587 13:28:45.404730 ==
6588 13:28:45.407547 [Gating] SW mode calibration
6589 13:28:45.414368 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6590 13:28:45.417302 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6591 13:28:45.423838 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6592 13:28:45.427204 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6593 13:28:45.430798 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6594 13:28:45.436852 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
6595 13:28:45.440377 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6596 13:28:45.443539 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6597 13:28:45.450877 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6598 13:28:45.453901 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
6599 13:28:45.457070 Total UI for P1: 0, mck2ui 16
6600 13:28:45.459799 best dqsien dly found for B0: ( 0, 10, 8)
6601 13:28:45.463576 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6602 13:28:45.467064 Total UI for P1: 0, mck2ui 16
6603 13:28:45.470031 best dqsien dly found for B1: ( 0, 10, 16)
6604 13:28:45.474009 best DQS0 dly(MCK, UI, PI) = (0, 10, 8)
6605 13:28:45.477008 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6606 13:28:45.480125
6607 13:28:45.483724 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 8)
6608 13:28:45.486620 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6609 13:28:45.490309 [Gating] SW calibration Done
6610 13:28:45.490799 ==
6611 13:28:45.493559 Dram Type= 6, Freq= 0, CH_1, rank 1
6612 13:28:45.496576 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6613 13:28:45.496953 ==
6614 13:28:45.497224 RX Vref Scan: 0
6615 13:28:45.497467
6616 13:28:45.499996 RX Vref 0 -> 0, step: 1
6617 13:28:45.500468
6618 13:28:45.503516 RX Delay -410 -> 252, step: 16
6619 13:28:45.506718 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6620 13:28:45.513672 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6621 13:28:45.516829 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6622 13:28:45.519826 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6623 13:28:45.523789 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6624 13:28:45.530454 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6625 13:28:45.533355 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6626 13:28:45.536521 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6627 13:28:45.539921 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6628 13:28:45.546582 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6629 13:28:45.549994 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6630 13:28:45.553414 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6631 13:28:45.556740 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6632 13:28:45.563055 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6633 13:28:45.566445 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6634 13:28:45.569503 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6635 13:28:45.569963 ==
6636 13:28:45.573076 Dram Type= 6, Freq= 0, CH_1, rank 1
6637 13:28:45.579801 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6638 13:28:45.580245 ==
6639 13:28:45.580558 DQS Delay:
6640 13:28:45.582671 DQS0 = 43, DQS1 = 59
6641 13:28:45.582966 DQM Delay:
6642 13:28:45.583205 DQM0 = 10, DQM1 = 17
6643 13:28:45.585966 DQ Delay:
6644 13:28:45.589368 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6645 13:28:45.589714 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6646 13:28:45.592950 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6647 13:28:45.595682 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6648 13:28:45.596027
6649 13:28:45.599334
6650 13:28:45.599605 ==
6651 13:28:45.602571 Dram Type= 6, Freq= 0, CH_1, rank 1
6652 13:28:45.605857 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6653 13:28:45.606247 ==
6654 13:28:45.606596
6655 13:28:45.606830
6656 13:28:45.609791 TX Vref Scan disable
6657 13:28:45.610137 == TX Byte 0 ==
6658 13:28:45.612816 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6659 13:28:45.619250 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6660 13:28:45.619597 == TX Byte 1 ==
6661 13:28:45.622463 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6662 13:28:45.628998 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6663 13:28:45.629398 ==
6664 13:28:45.632202 Dram Type= 6, Freq= 0, CH_1, rank 1
6665 13:28:45.635914 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6666 13:28:45.636259 ==
6667 13:28:45.636537
6668 13:28:45.636760
6669 13:28:45.638862 TX Vref Scan disable
6670 13:28:45.639206 == TX Byte 0 ==
6671 13:28:45.642281 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6672 13:28:45.648721 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6673 13:28:45.649161 == TX Byte 1 ==
6674 13:28:45.652392 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6675 13:28:45.659015 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6676 13:28:45.659573
6677 13:28:45.659858 [DATLAT]
6678 13:28:45.660082 Freq=400, CH1 RK1
6679 13:28:45.662232
6680 13:28:45.662622 DATLAT Default: 0xd
6681 13:28:45.666383 0, 0xFFFF, sum = 0
6682 13:28:45.666878 1, 0xFFFF, sum = 0
6683 13:28:45.669172 2, 0xFFFF, sum = 0
6684 13:28:45.669613 3, 0xFFFF, sum = 0
6685 13:28:45.672649 4, 0xFFFF, sum = 0
6686 13:28:45.673110 5, 0xFFFF, sum = 0
6687 13:28:45.676037 6, 0xFFFF, sum = 0
6688 13:28:45.676478 7, 0xFFFF, sum = 0
6689 13:28:45.678690 8, 0xFFFF, sum = 0
6690 13:28:45.679136 9, 0xFFFF, sum = 0
6691 13:28:45.682241 10, 0xFFFF, sum = 0
6692 13:28:45.682677 11, 0xFFFF, sum = 0
6693 13:28:45.685291 12, 0x0, sum = 1
6694 13:28:45.685669 13, 0x0, sum = 2
6695 13:28:45.688600 14, 0x0, sum = 3
6696 13:28:45.688951 15, 0x0, sum = 4
6697 13:28:45.691878 best_step = 13
6698 13:28:45.692262
6699 13:28:45.692547 ==
6700 13:28:45.696025 Dram Type= 6, Freq= 0, CH_1, rank 1
6701 13:28:45.698615 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6702 13:28:45.698974 ==
6703 13:28:45.702216 RX Vref Scan: 0
6704 13:28:45.702559
6705 13:28:45.702818 RX Vref 0 -> 0, step: 1
6706 13:28:45.703103
6707 13:28:45.705104 RX Delay -359 -> 252, step: 8
6708 13:28:45.712797 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6709 13:28:45.716247 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6710 13:28:45.719648 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6711 13:28:45.723264 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6712 13:28:45.730059 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6713 13:28:45.732656 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6714 13:28:45.736226 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6715 13:28:45.739701 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6716 13:28:45.746743 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6717 13:28:45.749859 iDelay=217, Bit 9, Center -60 (-311 ~ 192) 504
6718 13:28:45.753048 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6719 13:28:45.759711 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6720 13:28:45.762623 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6721 13:28:45.766275 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6722 13:28:45.769651 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6723 13:28:45.776301 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6724 13:28:45.776683 ==
6725 13:28:45.779702 Dram Type= 6, Freq= 0, CH_1, rank 1
6726 13:28:45.782723 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6727 13:28:45.783147 ==
6728 13:28:45.783449 DQS Delay:
6729 13:28:45.786114 DQS0 = 48, DQS1 = 64
6730 13:28:45.786418 DQM Delay:
6731 13:28:45.789177 DQM0 = 9, DQM1 = 15
6732 13:28:45.789522 DQ Delay:
6733 13:28:45.792831 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6734 13:28:45.795750 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6735 13:28:45.799535 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6736 13:28:45.802995 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =20
6737 13:28:45.803488
6738 13:28:45.803775
6739 13:28:45.808776 [DQSOSCAuto] RK1, (LSB)MR18= 0xb3b3, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6740 13:28:45.812764 CH1 RK1: MR19=C0C, MR18=B3B3
6741 13:28:45.819486 CH1_RK1: MR19=0xC0C, MR18=0xB3B3, DQSOSC=387, MR23=63, INC=394, DEC=262
6742 13:28:45.822475 [RxdqsGatingPostProcess] freq 400
6743 13:28:45.829001 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6744 13:28:45.829452 Pre-setting of DQS Precalculation
6745 13:28:45.835600 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6746 13:28:45.843022 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6747 13:28:45.849080 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6748 13:28:45.849570
6749 13:28:45.849841
6750 13:28:45.852598 [Calibration Summary] 800 Mbps
6751 13:28:45.855618 CH 0, Rank 0
6752 13:28:45.855996 SW Impedance : PASS
6753 13:28:45.859029 DUTY Scan : NO K
6754 13:28:45.862436 ZQ Calibration : PASS
6755 13:28:45.862884 Jitter Meter : NO K
6756 13:28:45.865679 CBT Training : PASS
6757 13:28:45.869214 Write leveling : PASS
6758 13:28:45.869667 RX DQS gating : PASS
6759 13:28:45.872158 RX DQ/DQS(RDDQC) : PASS
6760 13:28:45.872538 TX DQ/DQS : PASS
6761 13:28:45.875924 RX DATLAT : PASS
6762 13:28:45.878644 RX DQ/DQS(Engine): PASS
6763 13:28:45.878922 TX OE : NO K
6764 13:28:45.881912 All Pass.
6765 13:28:45.882256
6766 13:28:45.882511 CH 0, Rank 1
6767 13:28:45.885188 SW Impedance : PASS
6768 13:28:45.885598 DUTY Scan : NO K
6769 13:28:45.889049 ZQ Calibration : PASS
6770 13:28:45.891799 Jitter Meter : NO K
6771 13:28:45.892147 CBT Training : PASS
6772 13:28:45.895274 Write leveling : NO K
6773 13:28:45.898799 RX DQS gating : PASS
6774 13:28:45.899294 RX DQ/DQS(RDDQC) : PASS
6775 13:28:45.901856 TX DQ/DQS : PASS
6776 13:28:45.905026 RX DATLAT : PASS
6777 13:28:45.905409 RX DQ/DQS(Engine): PASS
6778 13:28:45.908641 TX OE : NO K
6779 13:28:45.908991 All Pass.
6780 13:28:45.909244
6781 13:28:45.911845 CH 1, Rank 0
6782 13:28:45.912323 SW Impedance : PASS
6783 13:28:45.915146 DUTY Scan : NO K
6784 13:28:45.922932 ZQ Calibration : PASS
6785 13:28:45.923287 Jitter Meter : NO K
6786 13:28:45.923546 CBT Training : PASS
6787 13:28:45.925268 Write leveling : PASS
6788 13:28:45.925618 RX DQS gating : PASS
6789 13:28:45.928176 RX DQ/DQS(RDDQC) : PASS
6790 13:28:45.928496 TX DQ/DQS : PASS
6791 13:28:45.931489 RX DATLAT : PASS
6792 13:28:45.935247 RX DQ/DQS(Engine): PASS
6793 13:28:45.935667 TX OE : NO K
6794 13:28:45.938381 All Pass.
6795 13:28:45.938838
6796 13:28:45.939102 CH 1, Rank 1
6797 13:28:45.941745 SW Impedance : PASS
6798 13:28:45.942092 DUTY Scan : NO K
6799 13:28:45.945077 ZQ Calibration : PASS
6800 13:28:45.948311 Jitter Meter : NO K
6801 13:28:45.948673 CBT Training : PASS
6802 13:28:45.952134 Write leveling : NO K
6803 13:28:45.955397 RX DQS gating : PASS
6804 13:28:45.955859 RX DQ/DQS(RDDQC) : PASS
6805 13:28:45.958737 TX DQ/DQS : PASS
6806 13:28:45.961786 RX DATLAT : PASS
6807 13:28:45.962320 RX DQ/DQS(Engine): PASS
6808 13:28:45.965528 TX OE : NO K
6809 13:28:45.965988 All Pass.
6810 13:28:45.966247
6811 13:28:45.968117 DramC Write-DBI off
6812 13:28:45.971377 PER_BANK_REFRESH: Hybrid Mode
6813 13:28:45.971721 TX_TRACKING: ON
6814 13:28:45.981537 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6815 13:28:45.984829 [FAST_K] Save calibration result to emmc
6816 13:28:45.988200 dramc_set_vcore_voltage set vcore to 725000
6817 13:28:45.991448 Read voltage for 1600, 0
6818 13:28:45.991797 Vio18 = 0
6819 13:28:45.992047 Vcore = 725000
6820 13:28:45.994527 Vdram = 0
6821 13:28:45.994872 Vddq = 0
6822 13:28:45.995116 Vmddr = 0
6823 13:28:46.001643 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6824 13:28:46.004645 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6825 13:28:46.008060 MEM_TYPE=3, freq_sel=13
6826 13:28:46.011465 sv_algorithm_assistance_LP4_3733
6827 13:28:46.014959 ============ PULL DRAM RESETB DOWN ============
6828 13:28:46.018146 ========== PULL DRAM RESETB DOWN end =========
6829 13:28:46.024882 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6830 13:28:46.027751 ===================================
6831 13:28:46.028113 LPDDR4 DRAM CONFIGURATION
6832 13:28:46.031342 ===================================
6833 13:28:46.034578 EX_ROW_EN[0] = 0x0
6834 13:28:46.037985 EX_ROW_EN[1] = 0x0
6835 13:28:46.038432 LP4Y_EN = 0x0
6836 13:28:46.041155 WORK_FSP = 0x1
6837 13:28:46.041502 WL = 0x5
6838 13:28:46.044816 RL = 0x5
6839 13:28:46.045215 BL = 0x2
6840 13:28:46.047732 RPST = 0x0
6841 13:28:46.048128 RD_PRE = 0x0
6842 13:28:46.051733 WR_PRE = 0x1
6843 13:28:46.052230 WR_PST = 0x1
6844 13:28:46.054832 DBI_WR = 0x0
6845 13:28:46.055497 DBI_RD = 0x0
6846 13:28:46.058152 OTF = 0x1
6847 13:28:46.061582 ===================================
6848 13:28:46.064862 ===================================
6849 13:28:46.065328 ANA top config
6850 13:28:46.067937 ===================================
6851 13:28:46.071041 DLL_ASYNC_EN = 0
6852 13:28:46.074636 ALL_SLAVE_EN = 0
6853 13:28:46.077969 NEW_RANK_MODE = 1
6854 13:28:46.078429 DLL_IDLE_MODE = 1
6855 13:28:46.080799 LP45_APHY_COMB_EN = 1
6856 13:28:46.084623 TX_ODT_DIS = 0
6857 13:28:46.087340 NEW_8X_MODE = 1
6858 13:28:46.090677 ===================================
6859 13:28:46.094202 ===================================
6860 13:28:46.097483 data_rate = 3200
6861 13:28:46.097833 CKR = 1
6862 13:28:46.100657 DQ_P2S_RATIO = 8
6863 13:28:46.104402 ===================================
6864 13:28:46.107211 CA_P2S_RATIO = 8
6865 13:28:46.111266 DQ_CA_OPEN = 0
6866 13:28:46.114205 DQ_SEMI_OPEN = 0
6867 13:28:46.117438 CA_SEMI_OPEN = 0
6868 13:28:46.117899 CA_FULL_RATE = 0
6869 13:28:46.120397 DQ_CKDIV4_EN = 0
6870 13:28:46.123674 CA_CKDIV4_EN = 0
6871 13:28:46.127116 CA_PREDIV_EN = 0
6872 13:28:46.130303 PH8_DLY = 12
6873 13:28:46.133824 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6874 13:28:46.137191 DQ_AAMCK_DIV = 4
6875 13:28:46.137618 CA_AAMCK_DIV = 4
6876 13:28:46.140626 CA_ADMCK_DIV = 4
6877 13:28:46.144100 DQ_TRACK_CA_EN = 0
6878 13:28:46.147052 CA_PICK = 1600
6879 13:28:46.150059 CA_MCKIO = 1600
6880 13:28:46.154225 MCKIO_SEMI = 0
6881 13:28:46.157057 PLL_FREQ = 3068
6882 13:28:46.157437 DQ_UI_PI_RATIO = 32
6883 13:28:46.160265 CA_UI_PI_RATIO = 0
6884 13:28:46.164147 ===================================
6885 13:28:46.166836 ===================================
6886 13:28:46.170009 memory_type:LPDDR4
6887 13:28:46.173835 GP_NUM : 10
6888 13:28:46.174181 SRAM_EN : 1
6889 13:28:46.177194 MD32_EN : 0
6890 13:28:46.180011 ===================================
6891 13:28:46.183365 [ANA_INIT] >>>>>>>>>>>>>>
6892 13:28:46.183713 <<<<<< [CONFIGURE PHASE]: ANA_TX
6893 13:28:46.187012 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6894 13:28:46.190213 ===================================
6895 13:28:46.193626 data_rate = 3200,PCW = 0X7600
6896 13:28:46.196625 ===================================
6897 13:28:46.200099 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6898 13:28:46.206787 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6899 13:28:46.213348 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6900 13:28:46.216802 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6901 13:28:46.220360 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6902 13:28:46.222904 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6903 13:28:46.226692 [ANA_INIT] flow start
6904 13:28:46.227127 [ANA_INIT] PLL >>>>>>>>
6905 13:28:46.230103 [ANA_INIT] PLL <<<<<<<<
6906 13:28:46.233399 [ANA_INIT] MIDPI >>>>>>>>
6907 13:28:46.233748 [ANA_INIT] MIDPI <<<<<<<<
6908 13:28:46.236387 [ANA_INIT] DLL >>>>>>>>
6909 13:28:46.239697 [ANA_INIT] DLL <<<<<<<<
6910 13:28:46.240042 [ANA_INIT] flow end
6911 13:28:46.246929 ============ LP4 DIFF to SE enter ============
6912 13:28:46.250459 ============ LP4 DIFF to SE exit ============
6913 13:28:46.252994 [ANA_INIT] <<<<<<<<<<<<<
6914 13:28:46.257140 [Flow] Enable top DCM control >>>>>
6915 13:28:46.260067 [Flow] Enable top DCM control <<<<<
6916 13:28:46.260499 Enable DLL master slave shuffle
6917 13:28:46.266363 ==============================================================
6918 13:28:46.269919 Gating Mode config
6919 13:28:46.273074 ==============================================================
6920 13:28:46.275987 Config description:
6921 13:28:46.285907 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6922 13:28:46.292912 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6923 13:28:46.295924 SELPH_MODE 0: By rank 1: By Phase
6924 13:28:46.303045 ==============================================================
6925 13:28:46.305932 GAT_TRACK_EN = 1
6926 13:28:46.309235 RX_GATING_MODE = 2
6927 13:28:46.312825 RX_GATING_TRACK_MODE = 2
6928 13:28:46.316431 SELPH_MODE = 1
6929 13:28:46.319166 PICG_EARLY_EN = 1
6930 13:28:46.319539 VALID_LAT_VALUE = 1
6931 13:28:46.325912 ==============================================================
6932 13:28:46.329393 Enter into Gating configuration >>>>
6933 13:28:46.332588 Exit from Gating configuration <<<<
6934 13:28:46.335830 Enter into DVFS_PRE_config >>>>>
6935 13:28:46.345765 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6936 13:28:46.349475 Exit from DVFS_PRE_config <<<<<
6937 13:28:46.352113 Enter into PICG configuration >>>>
6938 13:28:46.355510 Exit from PICG configuration <<<<
6939 13:28:46.359246 [RX_INPUT] configuration >>>>>
6940 13:28:46.362509 [RX_INPUT] configuration <<<<<
6941 13:28:46.369342 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6942 13:28:46.372312 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6943 13:28:46.378981 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6944 13:28:46.385675 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6945 13:28:46.392229 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6946 13:28:46.398547 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6947 13:28:46.402475 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6948 13:28:46.405412 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6949 13:28:46.408853 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6950 13:28:46.415507 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6951 13:28:46.419346 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6952 13:28:46.422235 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6953 13:28:46.425493 ===================================
6954 13:28:46.428582 LPDDR4 DRAM CONFIGURATION
6955 13:28:46.432174 ===================================
6956 13:28:46.432705 EX_ROW_EN[0] = 0x0
6957 13:28:46.435750 EX_ROW_EN[1] = 0x0
6958 13:28:46.436220 LP4Y_EN = 0x0
6959 13:28:46.438745 WORK_FSP = 0x1
6960 13:28:46.442020 WL = 0x5
6961 13:28:46.442399 RL = 0x5
6962 13:28:46.445564 BL = 0x2
6963 13:28:46.446008 RPST = 0x0
6964 13:28:46.448728 RD_PRE = 0x0
6965 13:28:46.449087 WR_PRE = 0x1
6966 13:28:46.452078 WR_PST = 0x1
6967 13:28:46.452636 DBI_WR = 0x0
6968 13:28:46.455830 DBI_RD = 0x0
6969 13:28:46.456396 OTF = 0x1
6970 13:28:46.458268 ===================================
6971 13:28:46.462191 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6972 13:28:46.468546 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6973 13:28:46.471710 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6974 13:28:46.475439 ===================================
6975 13:28:46.478491 LPDDR4 DRAM CONFIGURATION
6976 13:28:46.481733 ===================================
6977 13:28:46.482097 EX_ROW_EN[0] = 0x10
6978 13:28:46.484893 EX_ROW_EN[1] = 0x0
6979 13:28:46.485239 LP4Y_EN = 0x0
6980 13:28:46.488406 WORK_FSP = 0x1
6981 13:28:46.488858 WL = 0x5
6982 13:28:46.491437 RL = 0x5
6983 13:28:46.491783 BL = 0x2
6984 13:28:46.494985 RPST = 0x0
6985 13:28:46.498612 RD_PRE = 0x0
6986 13:28:46.498969 WR_PRE = 0x1
6987 13:28:46.501511 WR_PST = 0x1
6988 13:28:46.501856 DBI_WR = 0x0
6989 13:28:46.504804 DBI_RD = 0x0
6990 13:28:46.505153 OTF = 0x1
6991 13:28:46.507785 ===================================
6992 13:28:46.515261 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6993 13:28:46.515733 ==
6994 13:28:46.518978 Dram Type= 6, Freq= 0, CH_0, rank 0
6995 13:28:46.521743 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6996 13:28:46.522180 ==
6997 13:28:46.524692 [Duty_Offset_Calibration]
6998 13:28:46.528018 B0:0 B1:2 CA:1
6999 13:28:46.528513
7000 13:28:46.532385 [DutyScan_Calibration_Flow] k_type=0
7001 13:28:46.540046
7002 13:28:46.540515 ==CLK 0==
7003 13:28:46.543466 Final CLK duty delay cell = 0
7004 13:28:46.546379 [0] MAX Duty = 5187%(X100), DQS PI = 24
7005 13:28:46.550049 [0] MIN Duty = 4938%(X100), DQS PI = 52
7006 13:28:46.550417 [0] AVG Duty = 5062%(X100)
7007 13:28:46.550746
7008 13:28:46.553636 CH0 CLK Duty spec in!! Max-Min= 249%
7009 13:28:46.560305 [DutyScan_Calibration_Flow] ====Done====
7010 13:28:46.560819
7011 13:28:46.563368 [DutyScan_Calibration_Flow] k_type=1
7012 13:28:46.580305
7013 13:28:46.580864 ==DQS 0 ==
7014 13:28:46.583108 Final DQS duty delay cell = 0
7015 13:28:46.586127 [0] MAX Duty = 5125%(X100), DQS PI = 22
7016 13:28:46.589634 [0] MIN Duty = 5031%(X100), DQS PI = 8
7017 13:28:46.592672 [0] AVG Duty = 5078%(X100)
7018 13:28:46.593034
7019 13:28:46.593286 ==DQS 1 ==
7020 13:28:46.596206 Final DQS duty delay cell = 0
7021 13:28:46.599262 [0] MAX Duty = 5031%(X100), DQS PI = 4
7022 13:28:46.602823 [0] MIN Duty = 4875%(X100), DQS PI = 18
7023 13:28:46.605861 [0] AVG Duty = 4953%(X100)
7024 13:28:46.606247
7025 13:28:46.609746 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7026 13:28:46.610106
7027 13:28:46.612889 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7028 13:28:46.615772 [DutyScan_Calibration_Flow] ====Done====
7029 13:28:46.616121
7030 13:28:46.619277 [DutyScan_Calibration_Flow] k_type=3
7031 13:28:46.637266
7032 13:28:46.637737 ==DQM 0 ==
7033 13:28:46.640179 Final DQM duty delay cell = 0
7034 13:28:46.643439 [0] MAX Duty = 5187%(X100), DQS PI = 22
7035 13:28:46.646815 [0] MIN Duty = 4907%(X100), DQS PI = 42
7036 13:28:46.649984 [0] AVG Duty = 5047%(X100)
7037 13:28:46.650333
7038 13:28:46.650578 ==DQM 1 ==
7039 13:28:46.653635 Final DQM duty delay cell = 0
7040 13:28:46.656737 [0] MAX Duty = 5000%(X100), DQS PI = 2
7041 13:28:46.660132 [0] MIN Duty = 4782%(X100), DQS PI = 12
7042 13:28:46.663214 [0] AVG Duty = 4891%(X100)
7043 13:28:46.663700
7044 13:28:46.666933 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7045 13:28:46.667470
7046 13:28:46.669858 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7047 13:28:46.673444 [DutyScan_Calibration_Flow] ====Done====
7048 13:28:46.674053
7049 13:28:46.676360 [DutyScan_Calibration_Flow] k_type=2
7050 13:28:46.693238
7051 13:28:46.693680 ==DQ 0 ==
7052 13:28:46.696296 Final DQ duty delay cell = 0
7053 13:28:46.699423 [0] MAX Duty = 5218%(X100), DQS PI = 18
7054 13:28:46.702796 [0] MIN Duty = 4969%(X100), DQS PI = 10
7055 13:28:46.703179 [0] AVG Duty = 5093%(X100)
7056 13:28:46.705958
7057 13:28:46.706301 ==DQ 1 ==
7058 13:28:46.710110 Final DQ duty delay cell = -4
7059 13:28:46.713209 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7060 13:28:46.715708 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7061 13:28:46.719143 [-4] AVG Duty = 4937%(X100)
7062 13:28:46.719490
7063 13:28:46.722409 CH0 DQ 0 Duty spec in!! Max-Min= 249%
7064 13:28:46.722761
7065 13:28:46.726222 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7066 13:28:46.729050 [DutyScan_Calibration_Flow] ====Done====
7067 13:28:46.729481 ==
7068 13:28:46.732572 Dram Type= 6, Freq= 0, CH_1, rank 0
7069 13:28:46.736060 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7070 13:28:46.736536 ==
7071 13:28:46.739653 [Duty_Offset_Calibration]
7072 13:28:46.740134 B0:0 B1:4 CA:-5
7073 13:28:46.742372
7074 13:28:46.745487 [DutyScan_Calibration_Flow] k_type=0
7075 13:28:46.753917
7076 13:28:46.754410 ==CLK 0==
7077 13:28:46.757191 Final CLK duty delay cell = 0
7078 13:28:46.760492 [0] MAX Duty = 5156%(X100), DQS PI = 22
7079 13:28:46.763694 [0] MIN Duty = 4875%(X100), DQS PI = 50
7080 13:28:46.767196 [0] AVG Duty = 5015%(X100)
7081 13:28:46.767699
7082 13:28:46.770112 CH1 CLK Duty spec in!! Max-Min= 281%
7083 13:28:46.773504 [DutyScan_Calibration_Flow] ====Done====
7084 13:28:46.773974
7085 13:28:46.776778 [DutyScan_Calibration_Flow] k_type=1
7086 13:28:46.792690
7087 13:28:46.793234 ==DQS 0 ==
7088 13:28:46.795968 Final DQS duty delay cell = 0
7089 13:28:46.798965 [0] MAX Duty = 5156%(X100), DQS PI = 18
7090 13:28:46.802488 [0] MIN Duty = 4876%(X100), DQS PI = 44
7091 13:28:46.805848 [0] AVG Duty = 5016%(X100)
7092 13:28:46.806190
7093 13:28:46.806432 ==DQS 1 ==
7094 13:28:46.809482 Final DQS duty delay cell = -4
7095 13:28:46.812224 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7096 13:28:46.816047 [-4] MIN Duty = 4844%(X100), DQS PI = 40
7097 13:28:46.819060 [-4] AVG Duty = 4922%(X100)
7098 13:28:46.819404
7099 13:28:46.822794 CH1 DQS 0 Duty spec in!! Max-Min= 280%
7100 13:28:46.823274
7101 13:28:46.825984 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7102 13:28:46.828857 [DutyScan_Calibration_Flow] ====Done====
7103 13:28:46.829225
7104 13:28:46.832475 [DutyScan_Calibration_Flow] k_type=3
7105 13:28:46.848375
7106 13:28:46.848943 ==DQM 0 ==
7107 13:28:46.851574 Final DQM duty delay cell = -4
7108 13:28:46.854772 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7109 13:28:46.858217 [-4] MIN Duty = 4782%(X100), DQS PI = 44
7110 13:28:46.861748 [-4] AVG Duty = 4922%(X100)
7111 13:28:46.862125
7112 13:28:46.862388 ==DQM 1 ==
7113 13:28:46.864637 Final DQM duty delay cell = -4
7114 13:28:46.867958 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7115 13:28:46.871369 [-4] MIN Duty = 4907%(X100), DQS PI = 38
7116 13:28:46.875373 [-4] AVG Duty = 4984%(X100)
7117 13:28:46.875831
7118 13:28:46.878364 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7119 13:28:46.878849
7120 13:28:46.881582 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7121 13:28:46.884457 [DutyScan_Calibration_Flow] ====Done====
7122 13:28:46.884839
7123 13:28:46.887620 [DutyScan_Calibration_Flow] k_type=2
7124 13:28:46.905988
7125 13:28:46.906425 ==DQ 0 ==
7126 13:28:46.909520 Final DQ duty delay cell = 0
7127 13:28:46.912775 [0] MAX Duty = 5093%(X100), DQS PI = 20
7128 13:28:46.916256 [0] MIN Duty = 4938%(X100), DQS PI = 46
7129 13:28:46.916806 [0] AVG Duty = 5015%(X100)
7130 13:28:46.919139
7131 13:28:46.919482 ==DQ 1 ==
7132 13:28:46.922499 Final DQ duty delay cell = 0
7133 13:28:46.925872 [0] MAX Duty = 5031%(X100), DQS PI = 4
7134 13:28:46.929201 [0] MIN Duty = 4876%(X100), DQS PI = 28
7135 13:28:46.929548 [0] AVG Duty = 4953%(X100)
7136 13:28:46.929809
7137 13:28:46.932162 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7138 13:28:46.935733
7139 13:28:46.938878 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7140 13:28:46.942131 [DutyScan_Calibration_Flow] ====Done====
7141 13:28:46.946329 nWR fixed to 30
7142 13:28:46.946699 [ModeRegInit_LP4] CH0 RK0
7143 13:28:46.949057 [ModeRegInit_LP4] CH0 RK1
7144 13:28:46.952471 [ModeRegInit_LP4] CH1 RK0
7145 13:28:46.955624 [ModeRegInit_LP4] CH1 RK1
7146 13:28:46.956077 match AC timing 4
7147 13:28:46.959354 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7148 13:28:46.965772 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7149 13:28:46.969097 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7150 13:28:46.975657 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7151 13:28:46.978642 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7152 13:28:46.978991 [MiockJmeterHQA]
7153 13:28:46.979241
7154 13:28:46.981875 [DramcMiockJmeter] u1RxGatingPI = 0
7155 13:28:46.985661 0 : 4252, 4027
7156 13:28:46.986067 4 : 4364, 4137
7157 13:28:46.988658 8 : 4365, 4140
7158 13:28:46.989011 12 : 4253, 4026
7159 13:28:46.989260 16 : 4253, 4026
7160 13:28:46.991656 20 : 4254, 4029
7161 13:28:46.991947 24 : 4363, 4138
7162 13:28:46.995201 28 : 4253, 4026
7163 13:28:46.995561 32 : 4364, 4137
7164 13:28:46.998707 36 : 4252, 4027
7165 13:28:46.999185 40 : 4252, 4027
7166 13:28:46.999552 44 : 4250, 4026
7167 13:28:47.002211 48 : 4360, 4138
7168 13:28:47.002567 52 : 4360, 4137
7169 13:28:47.005249 56 : 4253, 4029
7170 13:28:47.005523 60 : 4251, 4027
7171 13:28:47.008445 64 : 4250, 4026
7172 13:28:47.008799 68 : 4250, 4027
7173 13:28:47.011656 72 : 4252, 4029
7174 13:28:47.012038 76 : 4361, 4137
7175 13:28:47.012320 80 : 4250, 4027
7176 13:28:47.015392 84 : 4250, 4026
7177 13:28:47.015739 88 : 4250, 4027
7178 13:28:47.018768 92 : 4252, 4029
7179 13:28:47.019248 96 : 4250, 4026
7180 13:28:47.021720 100 : 4360, 2413
7181 13:28:47.022072 104 : 4249, 0
7182 13:28:47.025413 108 : 4250, 0
7183 13:28:47.025758 112 : 4252, 0
7184 13:28:47.026006 116 : 4250, 0
7185 13:28:47.028110 120 : 4250, 0
7186 13:28:47.028426 124 : 4250, 0
7187 13:28:47.028652 128 : 4363, 0
7188 13:28:47.031453 132 : 4361, 0
7189 13:28:47.031720 136 : 4250, 0
7190 13:28:47.035133 140 : 4250, 0
7191 13:28:47.035597 144 : 4250, 0
7192 13:28:47.035849 148 : 4250, 0
7193 13:28:47.038702 152 : 4250, 0
7194 13:28:47.039051 156 : 4252, 0
7195 13:28:47.041796 160 : 4250, 0
7196 13:28:47.042144 164 : 4250, 0
7197 13:28:47.042427 168 : 4253, 0
7198 13:28:47.045500 172 : 4360, 0
7199 13:28:47.045957 176 : 4361, 0
7200 13:28:47.046224 180 : 4363, 0
7201 13:28:47.048343 184 : 4250, 0
7202 13:28:47.048692 188 : 4250, 0
7203 13:28:47.051925 192 : 4363, 0
7204 13:28:47.052270 196 : 4250, 0
7205 13:28:47.052563 200 : 4250, 0
7206 13:28:47.055155 204 : 4250, 0
7207 13:28:47.055505 208 : 4252, 0
7208 13:28:47.059139 212 : 4361, 0
7209 13:28:47.059711 216 : 4250, 0
7210 13:28:47.060084 220 : 4251, 355
7211 13:28:47.061934 224 : 4360, 4127
7212 13:28:47.062283 228 : 4250, 4027
7213 13:28:47.064855 232 : 4250, 4027
7214 13:28:47.065205 236 : 4360, 4137
7215 13:28:47.068614 240 : 4250, 4026
7216 13:28:47.069233 244 : 4250, 4027
7217 13:28:47.071811 248 : 4250, 4027
7218 13:28:47.072212 252 : 4252, 4029
7219 13:28:47.075114 256 : 4250, 4026
7220 13:28:47.075744 260 : 4250, 4027
7221 13:28:47.078377 264 : 4360, 4138
7222 13:28:47.079000 268 : 4250, 4027
7223 13:28:47.081565 272 : 4250, 4027
7224 13:28:47.081974 276 : 4361, 4137
7225 13:28:47.082235 280 : 4250, 4027
7226 13:28:47.084941 284 : 4250, 4027
7227 13:28:47.085327 288 : 4361, 4137
7228 13:28:47.087954 292 : 4250, 4026
7229 13:28:47.088362 296 : 4250, 4027
7230 13:28:47.091011 300 : 4250, 4027
7231 13:28:47.091376 304 : 4252, 4029
7232 13:28:47.094686 308 : 4250, 4026
7233 13:28:47.095014 312 : 4250, 4027
7234 13:28:47.097915 316 : 4360, 4138
7235 13:28:47.098258 320 : 4250, 4027
7236 13:28:47.101177 324 : 4250, 4026
7237 13:28:47.101646 328 : 4361, 4137
7238 13:28:47.104572 332 : 4250, 4027
7239 13:28:47.104919 336 : 4250, 3923
7240 13:28:47.107940 340 : 4363, 2314
7241 13:28:47.108445 344 : 4250, 0
7242 13:28:47.108730
7243 13:28:47.110968 MIOCK jitter meter ch=0
7244 13:28:47.111245
7245 13:28:47.114475 1T = (344-104) = 240 dly cells
7246 13:28:47.118089 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7247 13:28:47.118520 ==
7248 13:28:47.121137 Dram Type= 6, Freq= 0, CH_0, rank 0
7249 13:28:47.128243 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7250 13:28:47.128729 ==
7251 13:28:47.130860 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7252 13:28:47.137671 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7253 13:28:47.141140 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7254 13:28:47.147826 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7255 13:28:47.155229 [CA 0] Center 42 (12~73) winsize 62
7256 13:28:47.158220 [CA 1] Center 42 (12~73) winsize 62
7257 13:28:47.160963 [CA 2] Center 39 (9~69) winsize 61
7258 13:28:47.164665 [CA 3] Center 38 (9~68) winsize 60
7259 13:28:47.167840 [CA 4] Center 36 (6~67) winsize 62
7260 13:28:47.171402 [CA 5] Center 36 (6~66) winsize 61
7261 13:28:47.171923
7262 13:28:47.174630 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7263 13:28:47.175116
7264 13:28:47.180687 [CATrainingPosCal] consider 1 rank data
7265 13:28:47.181183 u2DelayCellTimex100 = 271/100 ps
7266 13:28:47.188010 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7267 13:28:47.190392 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7268 13:28:47.194140 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7269 13:28:47.197224 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7270 13:28:47.200634 CA4 delay=36 (6~67),Diff = 0 PI (0 cell)
7271 13:28:47.203974 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7272 13:28:47.204413
7273 13:28:47.207323 CA PerBit enable=1, Macro0, CA PI delay=36
7274 13:28:47.207810
7275 13:28:47.210352 [CBTSetCACLKResult] CA Dly = 36
7276 13:28:47.214070 CS Dly: 10 (0~41)
7277 13:28:47.217079 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7278 13:28:47.220673 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7279 13:28:47.221171 ==
7280 13:28:47.224358 Dram Type= 6, Freq= 0, CH_0, rank 1
7281 13:28:47.230159 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7282 13:28:47.230560 ==
7283 13:28:47.233502 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7284 13:28:47.240098 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7285 13:28:47.243535 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7286 13:28:47.250205 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7287 13:28:47.257495 [CA 0] Center 42 (12~73) winsize 62
7288 13:28:47.260884 [CA 1] Center 42 (12~73) winsize 62
7289 13:28:47.263794 [CA 2] Center 38 (9~68) winsize 60
7290 13:28:47.267498 [CA 3] Center 38 (8~68) winsize 61
7291 13:28:47.270387 [CA 4] Center 36 (6~66) winsize 61
7292 13:28:47.274040 [CA 5] Center 36 (6~66) winsize 61
7293 13:28:47.274423
7294 13:28:47.277059 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7295 13:28:47.277420
7296 13:28:47.280844 [CATrainingPosCal] consider 2 rank data
7297 13:28:47.284172 u2DelayCellTimex100 = 271/100 ps
7298 13:28:47.287396 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7299 13:28:47.293729 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7300 13:28:47.297035 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7301 13:28:47.300439 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7302 13:28:47.303380 CA4 delay=36 (6~66),Diff = 0 PI (0 cell)
7303 13:28:47.306790 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7304 13:28:47.307138
7305 13:28:47.310229 CA PerBit enable=1, Macro0, CA PI delay=36
7306 13:28:47.310576
7307 13:28:47.313780 [CBTSetCACLKResult] CA Dly = 36
7308 13:28:47.316393 CS Dly: 10 (0~42)
7309 13:28:47.320180 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7310 13:28:47.323345 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7311 13:28:47.323688
7312 13:28:47.326917 ----->DramcWriteLeveling(PI) begin...
7313 13:28:47.327267 ==
7314 13:28:47.329820 Dram Type= 6, Freq= 0, CH_0, rank 0
7315 13:28:47.336382 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7316 13:28:47.336696 ==
7317 13:28:47.339753 Write leveling (Byte 0): 29 => 29
7318 13:28:47.342603 Write leveling (Byte 1): 28 => 28
7319 13:28:47.342950 DramcWriteLeveling(PI) end<-----
7320 13:28:47.346263
7321 13:28:47.346605 ==
7322 13:28:47.349212 Dram Type= 6, Freq= 0, CH_0, rank 0
7323 13:28:47.352946 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7324 13:28:47.353291 ==
7325 13:28:47.356239 [Gating] SW mode calibration
7326 13:28:47.362822 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7327 13:28:47.366296 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7328 13:28:47.372551 0 12 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7329 13:28:47.375698 0 12 4 | B1->B0 | 2423 3333 | 1 0 | (0 0) (0 0)
7330 13:28:47.379416 0 12 8 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
7331 13:28:47.385736 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7332 13:28:47.388972 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7333 13:28:47.392878 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7334 13:28:47.399441 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7335 13:28:47.402208 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7336 13:28:47.405789 0 13 0 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 0)
7337 13:28:47.412588 0 13 4 | B1->B0 | 3030 2424 | 1 0 | (1 0) (1 0)
7338 13:28:47.415848 0 13 8 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
7339 13:28:47.419117 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7340 13:28:47.426112 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7341 13:28:47.428858 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7342 13:28:47.431890 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7343 13:28:47.439125 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7344 13:28:47.442593 0 14 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (1 1)
7345 13:28:47.445394 0 14 4 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
7346 13:28:47.451710 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7347 13:28:47.455527 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7348 13:28:47.458383 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7349 13:28:47.465087 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7350 13:28:47.468615 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7351 13:28:47.471713 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7352 13:28:47.478574 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7353 13:28:47.481874 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7354 13:28:47.485344 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7355 13:28:47.492074 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7356 13:28:47.494826 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7357 13:28:47.498418 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7358 13:28:47.504775 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7359 13:28:47.508042 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7360 13:28:47.511158 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7361 13:28:47.518469 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7362 13:28:47.521532 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7363 13:28:47.524603 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7364 13:28:47.531431 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7365 13:28:47.535360 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7366 13:28:47.538237 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7367 13:28:47.544879 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7368 13:28:47.548136 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7369 13:28:47.551318 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7370 13:28:47.554577 Total UI for P1: 0, mck2ui 16
7371 13:28:47.557967 best dqsien dly found for B0: ( 1, 0, 30)
7372 13:28:47.564765 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7373 13:28:47.568047 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7374 13:28:47.571074 Total UI for P1: 0, mck2ui 16
7375 13:28:47.574599 best dqsien dly found for B1: ( 1, 1, 6)
7376 13:28:47.577533 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7377 13:28:47.581005 best DQS1 dly(MCK, UI, PI) = (1, 1, 6)
7378 13:28:47.581350
7379 13:28:47.584164 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7380 13:28:47.587562 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 6)
7381 13:28:47.590833 [Gating] SW calibration Done
7382 13:28:47.591190 ==
7383 13:28:47.593757 Dram Type= 6, Freq= 0, CH_0, rank 0
7384 13:28:47.597787 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7385 13:28:47.600242 ==
7386 13:28:47.600556 RX Vref Scan: 0
7387 13:28:47.600791
7388 13:28:47.603627 RX Vref 0 -> 0, step: 1
7389 13:28:47.603971
7390 13:28:47.604218 RX Delay 0 -> 252, step: 8
7391 13:28:47.610520 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7392 13:28:47.613707 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7393 13:28:47.617541 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
7394 13:28:47.620626 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7395 13:28:47.623574 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7396 13:28:47.630606 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7397 13:28:47.633743 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7398 13:28:47.637463 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7399 13:28:47.640103 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7400 13:28:47.643558 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7401 13:28:47.650719 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7402 13:28:47.653868 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7403 13:28:47.657362 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7404 13:28:47.660324 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7405 13:28:47.667196 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7406 13:28:47.670788 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7407 13:28:47.671168 ==
7408 13:28:47.674038 Dram Type= 6, Freq= 0, CH_0, rank 0
7409 13:28:47.676741 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7410 13:28:47.677084 ==
7411 13:28:47.677330 DQS Delay:
7412 13:28:47.680352 DQS0 = 0, DQS1 = 0
7413 13:28:47.680844 DQM Delay:
7414 13:28:47.683568 DQM0 = 129, DQM1 = 124
7415 13:28:47.683912 DQ Delay:
7416 13:28:47.686719 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =127
7417 13:28:47.690308 DQ4 =135, DQ5 =119, DQ6 =135, DQ7 =139
7418 13:28:47.693317 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7419 13:28:47.700328 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7420 13:28:47.700703
7421 13:28:47.700950
7422 13:28:47.701165 ==
7423 13:28:47.703470 Dram Type= 6, Freq= 0, CH_0, rank 0
7424 13:28:47.707034 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7425 13:28:47.707498 ==
7426 13:28:47.707761
7427 13:28:47.707980
7428 13:28:47.710126 TX Vref Scan disable
7429 13:28:47.710467 == TX Byte 0 ==
7430 13:28:47.716546 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7431 13:28:47.719977 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7432 13:28:47.720483 == TX Byte 1 ==
7433 13:28:47.726432 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7434 13:28:47.729673 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7435 13:28:47.730014 ==
7436 13:28:47.733845 Dram Type= 6, Freq= 0, CH_0, rank 0
7437 13:28:47.736834 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7438 13:28:47.737181 ==
7439 13:28:47.751409
7440 13:28:47.754352 TX Vref early break, caculate TX vref
7441 13:28:47.757500 TX Vref=16, minBit 1, minWin=23, winSum=380
7442 13:28:47.761074 TX Vref=18, minBit 7, minWin=23, winSum=386
7443 13:28:47.764086 TX Vref=20, minBit 8, minWin=23, winSum=392
7444 13:28:47.767592 TX Vref=22, minBit 8, minWin=24, winSum=403
7445 13:28:47.771538 TX Vref=24, minBit 0, minWin=25, winSum=408
7446 13:28:47.777916 TX Vref=26, minBit 7, minWin=25, winSum=417
7447 13:28:47.780768 TX Vref=28, minBit 0, minWin=25, winSum=420
7448 13:28:47.784420 TX Vref=30, minBit 6, minWin=24, winSum=413
7449 13:28:47.787366 TX Vref=32, minBit 6, minWin=24, winSum=406
7450 13:28:47.791222 TX Vref=34, minBit 3, minWin=24, winSum=399
7451 13:28:47.794061 TX Vref=36, minBit 3, minWin=23, winSum=385
7452 13:28:47.800993 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 28
7453 13:28:47.801413
7454 13:28:47.803996 Final TX Range 0 Vref 28
7455 13:28:47.804496
7456 13:28:47.804783 ==
7457 13:28:47.807709 Dram Type= 6, Freq= 0, CH_0, rank 0
7458 13:28:47.810727 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7459 13:28:47.811163 ==
7460 13:28:47.811453
7461 13:28:47.813757
7462 13:28:47.814133 TX Vref Scan disable
7463 13:28:47.820622 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7464 13:28:47.821069 == TX Byte 0 ==
7465 13:28:47.823846 u2DelayCellOfst[0]=14 cells (4 PI)
7466 13:28:47.827362 u2DelayCellOfst[1]=18 cells (5 PI)
7467 13:28:47.830296 u2DelayCellOfst[2]=14 cells (4 PI)
7468 13:28:47.833712 u2DelayCellOfst[3]=10 cells (3 PI)
7469 13:28:47.837495 u2DelayCellOfst[4]=10 cells (3 PI)
7470 13:28:47.840655 u2DelayCellOfst[5]=0 cells (0 PI)
7471 13:28:47.844199 u2DelayCellOfst[6]=18 cells (5 PI)
7472 13:28:47.846935 u2DelayCellOfst[7]=18 cells (5 PI)
7473 13:28:47.850200 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7474 13:28:47.853916 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7475 13:28:47.857012 == TX Byte 1 ==
7476 13:28:47.860733 u2DelayCellOfst[8]=0 cells (0 PI)
7477 13:28:47.863692 u2DelayCellOfst[9]=0 cells (0 PI)
7478 13:28:47.866816 u2DelayCellOfst[10]=7 cells (2 PI)
7479 13:28:47.870047 u2DelayCellOfst[11]=3 cells (1 PI)
7480 13:28:47.870477 u2DelayCellOfst[12]=14 cells (4 PI)
7481 13:28:47.873501 u2DelayCellOfst[13]=14 cells (4 PI)
7482 13:28:47.877024 u2DelayCellOfst[14]=18 cells (5 PI)
7483 13:28:47.880020 u2DelayCellOfst[15]=14 cells (4 PI)
7484 13:28:47.886502 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7485 13:28:47.890427 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7486 13:28:47.890808 DramC Write-DBI on
7487 13:28:47.893107 ==
7488 13:28:47.893450 Dram Type= 6, Freq= 0, CH_0, rank 0
7489 13:28:47.900662 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7490 13:28:47.901126 ==
7491 13:28:47.901393
7492 13:28:47.901611
7493 13:28:47.903114 TX Vref Scan disable
7494 13:28:47.903460 == TX Byte 0 ==
7495 13:28:47.910379 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7496 13:28:47.910831 == TX Byte 1 ==
7497 13:28:47.913260 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7498 13:28:47.916618 DramC Write-DBI off
7499 13:28:47.916960
7500 13:28:47.917205 [DATLAT]
7501 13:28:47.919738 Freq=1600, CH0 RK0
7502 13:28:47.920166
7503 13:28:47.920478 DATLAT Default: 0xf
7504 13:28:47.923220 0, 0xFFFF, sum = 0
7505 13:28:47.923670 1, 0xFFFF, sum = 0
7506 13:28:47.926571 2, 0xFFFF, sum = 0
7507 13:28:47.926919 3, 0xFFFF, sum = 0
7508 13:28:47.929589 4, 0xFFFF, sum = 0
7509 13:28:47.929935 5, 0xFFFF, sum = 0
7510 13:28:47.933072 6, 0xFFFF, sum = 0
7511 13:28:47.933452 7, 0xFFFF, sum = 0
7512 13:28:47.936252 8, 0xFFFF, sum = 0
7513 13:28:47.936725 9, 0xFFFF, sum = 0
7514 13:28:47.939754 10, 0xFFFF, sum = 0
7515 13:28:47.943082 11, 0xFFFF, sum = 0
7516 13:28:47.943470 12, 0xBFF, sum = 0
7517 13:28:47.946412 13, 0x0, sum = 1
7518 13:28:47.946759 14, 0x0, sum = 2
7519 13:28:47.947006 15, 0x0, sum = 3
7520 13:28:47.950045 16, 0x0, sum = 4
7521 13:28:47.950535 best_step = 14
7522 13:28:47.950828
7523 13:28:47.952948 ==
7524 13:28:47.953294 Dram Type= 6, Freq= 0, CH_0, rank 0
7525 13:28:47.959500 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7526 13:28:47.959910 ==
7527 13:28:47.960164 RX Vref Scan: 1
7528 13:28:47.960409
7529 13:28:47.963065 Set Vref Range= 24 -> 127
7530 13:28:47.963521
7531 13:28:47.967204 RX Vref 24 -> 127, step: 1
7532 13:28:47.967625
7533 13:28:47.969260 RX Delay 11 -> 252, step: 4
7534 13:28:47.969603
7535 13:28:47.972598 Set Vref, RX VrefLevel [Byte0]: 24
7536 13:28:47.976217 [Byte1]: 24
7537 13:28:47.976583
7538 13:28:47.979612 Set Vref, RX VrefLevel [Byte0]: 25
7539 13:28:47.982688 [Byte1]: 25
7540 13:28:47.983099
7541 13:28:47.986077 Set Vref, RX VrefLevel [Byte0]: 26
7542 13:28:47.989298 [Byte1]: 26
7543 13:28:47.993157
7544 13:28:47.993584 Set Vref, RX VrefLevel [Byte0]: 27
7545 13:28:47.996000 [Byte1]: 27
7546 13:28:48.000131
7547 13:28:48.000506 Set Vref, RX VrefLevel [Byte0]: 28
7548 13:28:48.003937 [Byte1]: 28
7549 13:28:48.007919
7550 13:28:48.008332 Set Vref, RX VrefLevel [Byte0]: 29
7551 13:28:48.011345 [Byte1]: 29
7552 13:28:48.015665
7553 13:28:48.016139 Set Vref, RX VrefLevel [Byte0]: 30
7554 13:28:48.018928 [Byte1]: 30
7555 13:28:48.023105
7556 13:28:48.023476 Set Vref, RX VrefLevel [Byte0]: 31
7557 13:28:48.029910 [Byte1]: 31
7558 13:28:48.030328
7559 13:28:48.032749 Set Vref, RX VrefLevel [Byte0]: 32
7560 13:28:48.036255 [Byte1]: 32
7561 13:28:48.036716
7562 13:28:48.039230 Set Vref, RX VrefLevel [Byte0]: 33
7563 13:28:48.042995 [Byte1]: 33
7564 13:28:48.045943
7565 13:28:48.046037 Set Vref, RX VrefLevel [Byte0]: 34
7566 13:28:48.049004 [Byte1]: 34
7567 13:28:48.053741
7568 13:28:48.054122 Set Vref, RX VrefLevel [Byte0]: 35
7569 13:28:48.056784 [Byte1]: 35
7570 13:28:48.061950
7571 13:28:48.062409 Set Vref, RX VrefLevel [Byte0]: 36
7572 13:28:48.064301 [Byte1]: 36
7573 13:28:48.068717
7574 13:28:48.069170 Set Vref, RX VrefLevel [Byte0]: 37
7575 13:28:48.072061 [Byte1]: 37
7576 13:28:48.076314
7577 13:28:48.076692 Set Vref, RX VrefLevel [Byte0]: 38
7578 13:28:48.079984 [Byte1]: 38
7579 13:28:48.084121
7580 13:28:48.084534 Set Vref, RX VrefLevel [Byte0]: 39
7581 13:28:48.087478 [Byte1]: 39
7582 13:28:48.091783
7583 13:28:48.092171 Set Vref, RX VrefLevel [Byte0]: 40
7584 13:28:48.094946 [Byte1]: 40
7585 13:28:48.099215
7586 13:28:48.099564 Set Vref, RX VrefLevel [Byte0]: 41
7587 13:28:48.102690 [Byte1]: 41
7588 13:28:48.106869
7589 13:28:48.107302 Set Vref, RX VrefLevel [Byte0]: 42
7590 13:28:48.110313 [Byte1]: 42
7591 13:28:48.114501
7592 13:28:48.114855 Set Vref, RX VrefLevel [Byte0]: 43
7593 13:28:48.118312 [Byte1]: 43
7594 13:28:48.122170
7595 13:28:48.122619 Set Vref, RX VrefLevel [Byte0]: 44
7596 13:28:48.128796 [Byte1]: 44
7597 13:28:48.129148
7598 13:28:48.132315 Set Vref, RX VrefLevel [Byte0]: 45
7599 13:28:48.135456 [Byte1]: 45
7600 13:28:48.135919
7601 13:28:48.138573 Set Vref, RX VrefLevel [Byte0]: 46
7602 13:28:48.142093 [Byte1]: 46
7603 13:28:48.142479
7604 13:28:48.145282 Set Vref, RX VrefLevel [Byte0]: 47
7605 13:28:48.148421 [Byte1]: 47
7606 13:28:48.152627
7607 13:28:48.152981 Set Vref, RX VrefLevel [Byte0]: 48
7608 13:28:48.155817 [Byte1]: 48
7609 13:28:48.160019
7610 13:28:48.160490 Set Vref, RX VrefLevel [Byte0]: 49
7611 13:28:48.163776 [Byte1]: 49
7612 13:28:48.168037
7613 13:28:48.168540 Set Vref, RX VrefLevel [Byte0]: 50
7614 13:28:48.171465 [Byte1]: 50
7615 13:28:48.176004
7616 13:28:48.176439 Set Vref, RX VrefLevel [Byte0]: 51
7617 13:28:48.178693 [Byte1]: 51
7618 13:28:48.183058
7619 13:28:48.183414 Set Vref, RX VrefLevel [Byte0]: 52
7620 13:28:48.186227 [Byte1]: 52
7621 13:28:48.190393
7622 13:28:48.190801 Set Vref, RX VrefLevel [Byte0]: 53
7623 13:28:48.193779 [Byte1]: 53
7624 13:28:48.198228
7625 13:28:48.198619 Set Vref, RX VrefLevel [Byte0]: 54
7626 13:28:48.201479 [Byte1]: 54
7627 13:28:48.206053
7628 13:28:48.206402 Set Vref, RX VrefLevel [Byte0]: 55
7629 13:28:48.209133 [Byte1]: 55
7630 13:28:48.213538
7631 13:28:48.213913 Set Vref, RX VrefLevel [Byte0]: 56
7632 13:28:48.216713 [Byte1]: 56
7633 13:28:48.221490
7634 13:28:48.221989 Set Vref, RX VrefLevel [Byte0]: 57
7635 13:28:48.227654 [Byte1]: 57
7636 13:28:48.228019
7637 13:28:48.231122 Set Vref, RX VrefLevel [Byte0]: 58
7638 13:28:48.234599 [Byte1]: 58
7639 13:28:48.235063
7640 13:28:48.237637 Set Vref, RX VrefLevel [Byte0]: 59
7641 13:28:48.240491 [Byte1]: 59
7642 13:28:48.243800
7643 13:28:48.244148 Set Vref, RX VrefLevel [Byte0]: 60
7644 13:28:48.247579 [Byte1]: 60
7645 13:28:48.251721
7646 13:28:48.252176 Set Vref, RX VrefLevel [Byte0]: 61
7647 13:28:48.255748 [Byte1]: 61
7648 13:28:48.259137
7649 13:28:48.259651 Set Vref, RX VrefLevel [Byte0]: 62
7650 13:28:48.263205 [Byte1]: 62
7651 13:28:48.266952
7652 13:28:48.267396 Set Vref, RX VrefLevel [Byte0]: 63
7653 13:28:48.270056 [Byte1]: 63
7654 13:28:48.274283
7655 13:28:48.274632 Set Vref, RX VrefLevel [Byte0]: 64
7656 13:28:48.278009 [Byte1]: 64
7657 13:28:48.282004
7658 13:28:48.282451 Set Vref, RX VrefLevel [Byte0]: 65
7659 13:28:48.285491 [Byte1]: 65
7660 13:28:48.289271
7661 13:28:48.289621 Set Vref, RX VrefLevel [Byte0]: 66
7662 13:28:48.292946 [Byte1]: 66
7663 13:28:48.297128
7664 13:28:48.297479 Set Vref, RX VrefLevel [Byte0]: 67
7665 13:28:48.300834 [Byte1]: 67
7666 13:28:48.304661
7667 13:28:48.305073 Set Vref, RX VrefLevel [Byte0]: 68
7668 13:28:48.308063 [Byte1]: 68
7669 13:28:48.312333
7670 13:28:48.312685 Set Vref, RX VrefLevel [Byte0]: 69
7671 13:28:48.315626 [Byte1]: 69
7672 13:28:48.319910
7673 13:28:48.320365 Set Vref, RX VrefLevel [Byte0]: 70
7674 13:28:48.323214 [Byte1]: 70
7675 13:28:48.327431
7676 13:28:48.327783 Set Vref, RX VrefLevel [Byte0]: 71
7677 13:28:48.331142 [Byte1]: 71
7678 13:28:48.335388
7679 13:28:48.335758 Set Vref, RX VrefLevel [Byte0]: 72
7680 13:28:48.338514 [Byte1]: 72
7681 13:28:48.343209
7682 13:28:48.343678 Final RX Vref Byte 0 = 53 to rank0
7683 13:28:48.346634 Final RX Vref Byte 1 = 55 to rank0
7684 13:28:48.349927 Final RX Vref Byte 0 = 53 to rank1
7685 13:28:48.352996 Final RX Vref Byte 1 = 55 to rank1==
7686 13:28:48.356156 Dram Type= 6, Freq= 0, CH_0, rank 0
7687 13:28:48.363107 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7688 13:28:48.363562 ==
7689 13:28:48.363843 DQS Delay:
7690 13:28:48.364085 DQS0 = 0, DQS1 = 0
7691 13:28:48.366324 DQM Delay:
7692 13:28:48.366709 DQM0 = 126, DQM1 = 121
7693 13:28:48.369650 DQ Delay:
7694 13:28:48.373056 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7695 13:28:48.376150 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7696 13:28:48.379528 DQ8 =112, DQ9 =104, DQ10 =122, DQ11 =112
7697 13:28:48.383147 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7698 13:28:48.383683
7699 13:28:48.384008
7700 13:28:48.384252
7701 13:28:48.386599 [DramC_TX_OE_Calibration] TA2
7702 13:28:48.389523 Original DQ_B0 (3 6) =30, OEN = 27
7703 13:28:48.393228 Original DQ_B1 (3 6) =30, OEN = 27
7704 13:28:48.395879 24, 0x0, End_B0=24 End_B1=24
7705 13:28:48.396379 25, 0x0, End_B0=25 End_B1=25
7706 13:28:48.399771 26, 0x0, End_B0=26 End_B1=26
7707 13:28:48.402829 27, 0x0, End_B0=27 End_B1=27
7708 13:28:48.405968 28, 0x0, End_B0=28 End_B1=28
7709 13:28:48.409236 29, 0x0, End_B0=29 End_B1=29
7710 13:28:48.409677 30, 0x0, End_B0=30 End_B1=30
7711 13:28:48.412384 31, 0x4141, End_B0=30 End_B1=30
7712 13:28:48.415949 Byte0 end_step=30 best_step=27
7713 13:28:48.419193 Byte1 end_step=30 best_step=27
7714 13:28:48.422472 Byte0 TX OE(2T, 0.5T) = (3, 3)
7715 13:28:48.425639 Byte1 TX OE(2T, 0.5T) = (3, 3)
7716 13:28:48.426000
7717 13:28:48.426336
7718 13:28:48.432190 [DQSOSCAuto] RK0, (LSB)MR18= 0x1717, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
7719 13:28:48.436189 CH0 RK0: MR19=303, MR18=1717
7720 13:28:48.442346 CH0_RK0: MR19=0x303, MR18=0x1717, DQSOSC=398, MR23=63, INC=23, DEC=15
7721 13:28:48.442785
7722 13:28:48.445539 ----->DramcWriteLeveling(PI) begin...
7723 13:28:48.445960 ==
7724 13:28:48.449242 Dram Type= 6, Freq= 0, CH_0, rank 1
7725 13:28:48.452042 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7726 13:28:48.452487 ==
7727 13:28:48.456005 Write leveling (Byte 0): 30 => 30
7728 13:28:48.458915 Write leveling (Byte 1): 27 => 27
7729 13:28:48.462288 DramcWriteLeveling(PI) end<-----
7730 13:28:48.462739
7731 13:28:48.463005 ==
7732 13:28:48.465823 Dram Type= 6, Freq= 0, CH_0, rank 1
7733 13:28:48.469174 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7734 13:28:48.469594 ==
7735 13:28:48.472300 [Gating] SW mode calibration
7736 13:28:48.478689 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7737 13:28:48.486212 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7738 13:28:48.488657 0 12 0 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
7739 13:28:48.494989 0 12 4 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7740 13:28:48.498214 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7741 13:28:48.502495 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7742 13:28:48.508778 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7743 13:28:48.511965 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7744 13:28:48.515054 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7745 13:28:48.521802 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7746 13:28:48.525120 0 13 0 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (0 1)
7747 13:28:48.528693 0 13 4 | B1->B0 | 3030 2323 | 0 0 | (1 0) (0 0)
7748 13:28:48.535160 0 13 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
7749 13:28:48.538196 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7750 13:28:48.541510 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7751 13:28:48.548329 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7752 13:28:48.551931 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7753 13:28:48.554830 0 13 28 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7754 13:28:48.562019 0 14 0 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
7755 13:28:48.564911 0 14 4 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
7756 13:28:48.568321 0 14 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7757 13:28:48.574694 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7758 13:28:48.577876 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7759 13:28:48.581304 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7760 13:28:48.584770 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7761 13:28:48.591178 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7762 13:28:48.594330 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7763 13:28:48.600805 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7764 13:28:48.603960 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7765 13:28:48.607814 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7766 13:28:48.611345 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7767 13:28:48.617972 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7768 13:28:48.620771 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7769 13:28:48.627108 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7770 13:28:48.631103 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7771 13:28:48.634105 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7772 13:28:48.640609 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7773 13:28:48.643800 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7774 13:28:48.647273 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7775 13:28:48.651126 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7776 13:28:48.657151 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7777 13:28:48.660706 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7778 13:28:48.664367 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7779 13:28:48.670555 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7780 13:28:48.673771 Total UI for P1: 0, mck2ui 16
7781 13:28:48.677091 best dqsien dly found for B0: ( 1, 0, 28)
7782 13:28:48.680121 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7783 13:28:48.683871 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7784 13:28:48.686955 Total UI for P1: 0, mck2ui 16
7785 13:28:48.689855 best dqsien dly found for B1: ( 1, 1, 6)
7786 13:28:48.693530 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
7787 13:28:48.699549 best DQS1 dly(MCK, UI, PI) = (1, 1, 6)
7788 13:28:48.699980
7789 13:28:48.703277 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
7790 13:28:48.706422 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 6)
7791 13:28:48.709659 [Gating] SW calibration Done
7792 13:28:48.710012 ==
7793 13:28:48.712779 Dram Type= 6, Freq= 0, CH_0, rank 1
7794 13:28:48.716641 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7795 13:28:48.716997 ==
7796 13:28:48.717251 RX Vref Scan: 0
7797 13:28:48.719827
7798 13:28:48.720179 RX Vref 0 -> 0, step: 1
7799 13:28:48.720502
7800 13:28:48.723670 RX Delay 0 -> 252, step: 8
7801 13:28:48.726290 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7802 13:28:48.730205 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7803 13:28:48.736529 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7804 13:28:48.739816 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7805 13:28:48.742912 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7806 13:28:48.746526 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7807 13:28:48.749368 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7808 13:28:48.756239 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7809 13:28:48.760052 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7810 13:28:48.762701 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7811 13:28:48.766371 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7812 13:28:48.769638 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
7813 13:28:48.775736 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7814 13:28:48.779550 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7815 13:28:48.783180 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7816 13:28:48.786210 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7817 13:28:48.786692 ==
7818 13:28:48.788996 Dram Type= 6, Freq= 0, CH_0, rank 1
7819 13:28:48.796256 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7820 13:28:48.796768 ==
7821 13:28:48.797130 DQS Delay:
7822 13:28:48.798963 DQS0 = 0, DQS1 = 0
7823 13:28:48.799360 DQM Delay:
7824 13:28:48.802745 DQM0 = 131, DQM1 = 124
7825 13:28:48.803193 DQ Delay:
7826 13:28:48.805691 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =127
7827 13:28:48.809301 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =143
7828 13:28:48.812630 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =115
7829 13:28:48.815843 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7830 13:28:48.816229
7831 13:28:48.816521
7832 13:28:48.816745 ==
7833 13:28:48.819155 Dram Type= 6, Freq= 0, CH_0, rank 1
7834 13:28:48.825605 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7835 13:28:48.825964 ==
7836 13:28:48.826214
7837 13:28:48.826432
7838 13:28:48.826641 TX Vref Scan disable
7839 13:28:48.828711 == TX Byte 0 ==
7840 13:28:48.832700 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7841 13:28:48.838981 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7842 13:28:48.839443 == TX Byte 1 ==
7843 13:28:48.841944 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7844 13:28:48.848822 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7845 13:28:48.849262 ==
7846 13:28:48.852321 Dram Type= 6, Freq= 0, CH_0, rank 1
7847 13:28:48.855565 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7848 13:28:48.856032 ==
7849 13:28:48.868019
7850 13:28:48.871285 TX Vref early break, caculate TX vref
7851 13:28:48.874709 TX Vref=16, minBit 1, minWin=23, winSum=379
7852 13:28:48.878017 TX Vref=18, minBit 1, minWin=22, winSum=386
7853 13:28:48.881228 TX Vref=20, minBit 8, minWin=23, winSum=394
7854 13:28:48.884163 TX Vref=22, minBit 1, minWin=23, winSum=398
7855 13:28:48.887669 TX Vref=24, minBit 1, minWin=24, winSum=407
7856 13:28:48.894223 TX Vref=26, minBit 1, minWin=24, winSum=414
7857 13:28:48.897640 TX Vref=28, minBit 8, minWin=25, winSum=417
7858 13:28:48.901224 TX Vref=30, minBit 1, minWin=24, winSum=408
7859 13:28:48.904158 TX Vref=32, minBit 0, minWin=24, winSum=401
7860 13:28:48.907511 TX Vref=34, minBit 8, minWin=23, winSum=393
7861 13:28:48.914219 [TxChooseVref] Worse bit 8, Min win 25, Win sum 417, Final Vref 28
7862 13:28:48.914648
7863 13:28:48.917300 Final TX Range 0 Vref 28
7864 13:28:48.917647
7865 13:28:48.917892 ==
7866 13:28:48.921057 Dram Type= 6, Freq= 0, CH_0, rank 1
7867 13:28:48.924167 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7868 13:28:48.924554 ==
7869 13:28:48.924805
7870 13:28:48.925023
7871 13:28:48.927737 TX Vref Scan disable
7872 13:28:48.934041 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7873 13:28:48.934430 == TX Byte 0 ==
7874 13:28:48.938004 u2DelayCellOfst[0]=10 cells (3 PI)
7875 13:28:48.941029 u2DelayCellOfst[1]=14 cells (4 PI)
7876 13:28:48.944399 u2DelayCellOfst[2]=10 cells (3 PI)
7877 13:28:48.947365 u2DelayCellOfst[3]=10 cells (3 PI)
7878 13:28:48.951114 u2DelayCellOfst[4]=7 cells (2 PI)
7879 13:28:48.954703 u2DelayCellOfst[5]=0 cells (0 PI)
7880 13:28:48.957757 u2DelayCellOfst[6]=14 cells (4 PI)
7881 13:28:48.960973 u2DelayCellOfst[7]=18 cells (5 PI)
7882 13:28:48.964469 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7883 13:28:48.967786 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7884 13:28:48.971202 == TX Byte 1 ==
7885 13:28:48.971658 u2DelayCellOfst[8]=3 cells (1 PI)
7886 13:28:48.973923 u2DelayCellOfst[9]=0 cells (0 PI)
7887 13:28:48.977377 u2DelayCellOfst[10]=10 cells (3 PI)
7888 13:28:48.980889 u2DelayCellOfst[11]=3 cells (1 PI)
7889 13:28:48.983852 u2DelayCellOfst[12]=14 cells (4 PI)
7890 13:28:48.987043 u2DelayCellOfst[13]=14 cells (4 PI)
7891 13:28:48.990482 u2DelayCellOfst[14]=18 cells (5 PI)
7892 13:28:48.994394 u2DelayCellOfst[15]=14 cells (4 PI)
7893 13:28:48.997498 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7894 13:28:49.003667 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7895 13:28:49.004022 DramC Write-DBI on
7896 13:28:49.004364 ==
7897 13:28:49.006830 Dram Type= 6, Freq= 0, CH_0, rank 1
7898 13:28:49.013636 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7899 13:28:49.014026 ==
7900 13:28:49.014360
7901 13:28:49.014655
7902 13:28:49.014927 TX Vref Scan disable
7903 13:28:49.017124 == TX Byte 0 ==
7904 13:28:49.020663 Update DQM dly =730 (2 ,6, 26) DQM OEN =(3 ,3)
7905 13:28:49.024133 == TX Byte 1 ==
7906 13:28:49.027607 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7907 13:28:49.030647 DramC Write-DBI off
7908 13:28:49.031092
7909 13:28:49.031434 [DATLAT]
7910 13:28:49.031716 Freq=1600, CH0 RK1
7911 13:28:49.031987
7912 13:28:49.033686 DATLAT Default: 0xe
7913 13:28:49.037087 0, 0xFFFF, sum = 0
7914 13:28:49.037514 1, 0xFFFF, sum = 0
7915 13:28:49.040760 2, 0xFFFF, sum = 0
7916 13:28:49.041142 3, 0xFFFF, sum = 0
7917 13:28:49.044051 4, 0xFFFF, sum = 0
7918 13:28:49.044453 5, 0xFFFF, sum = 0
7919 13:28:49.047060 6, 0xFFFF, sum = 0
7920 13:28:49.047422 7, 0xFFFF, sum = 0
7921 13:28:49.050514 8, 0xFFFF, sum = 0
7922 13:28:49.050989 9, 0xFFFF, sum = 0
7923 13:28:49.053536 10, 0xFFFF, sum = 0
7924 13:28:49.053902 11, 0xFFFF, sum = 0
7925 13:28:49.056710 12, 0x8FFF, sum = 0
7926 13:28:49.057074 13, 0x0, sum = 1
7927 13:28:49.060368 14, 0x0, sum = 2
7928 13:28:49.060732 15, 0x0, sum = 3
7929 13:28:49.063632 16, 0x0, sum = 4
7930 13:28:49.063993 best_step = 14
7931 13:28:49.064354
7932 13:28:49.064637 ==
7933 13:28:49.066867 Dram Type= 6, Freq= 0, CH_0, rank 1
7934 13:28:49.073640 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7935 13:28:49.074156 ==
7936 13:28:49.074500 RX Vref Scan: 0
7937 13:28:49.074789
7938 13:28:49.077118 RX Vref 0 -> 0, step: 1
7939 13:28:49.077477
7940 13:28:49.080039 RX Delay 11 -> 252, step: 4
7941 13:28:49.083412 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7942 13:28:49.086735 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7943 13:28:49.089905 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7944 13:28:49.096531 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7945 13:28:49.100035 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7946 13:28:49.103025 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
7947 13:28:49.106159 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7948 13:28:49.109441 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7949 13:28:49.115931 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7950 13:28:49.119769 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7951 13:28:49.122578 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7952 13:28:49.125903 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7953 13:28:49.132463 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7954 13:28:49.135701 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
7955 13:28:49.139237 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
7956 13:28:49.142749 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7957 13:28:49.142825 ==
7958 13:28:49.146116 Dram Type= 6, Freq= 0, CH_0, rank 1
7959 13:28:49.152709 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7960 13:28:49.153068 ==
7961 13:28:49.153324 DQS Delay:
7962 13:28:49.153492 DQS0 = 0, DQS1 = 0
7963 13:28:49.155969 DQM Delay:
7964 13:28:49.156044 DQM0 = 128, DQM1 = 120
7965 13:28:49.159232 DQ Delay:
7966 13:28:49.163046 DQ0 =122, DQ1 =132, DQ2 =126, DQ3 =124
7967 13:28:49.165760 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
7968 13:28:49.170097 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
7969 13:28:49.173142 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
7970 13:28:49.173597
7971 13:28:49.173857
7972 13:28:49.174075
7973 13:28:49.176127 [DramC_TX_OE_Calibration] TA2
7974 13:28:49.179682 Original DQ_B0 (3 6) =30, OEN = 27
7975 13:28:49.182783 Original DQ_B1 (3 6) =30, OEN = 27
7976 13:28:49.185683 24, 0x0, End_B0=24 End_B1=24
7977 13:28:49.186119 25, 0x0, End_B0=25 End_B1=25
7978 13:28:49.189408 26, 0x0, End_B0=26 End_B1=26
7979 13:28:49.192880 27, 0x0, End_B0=27 End_B1=27
7980 13:28:49.195519 28, 0x0, End_B0=28 End_B1=28
7981 13:28:49.199225 29, 0x0, End_B0=29 End_B1=29
7982 13:28:49.199746 30, 0x0, End_B0=30 End_B1=30
7983 13:28:49.202763 31, 0x4141, End_B0=30 End_B1=30
7984 13:28:49.205899 Byte0 end_step=30 best_step=27
7985 13:28:49.208950 Byte1 end_step=30 best_step=27
7986 13:28:49.212216 Byte0 TX OE(2T, 0.5T) = (3, 3)
7987 13:28:49.215532 Byte1 TX OE(2T, 0.5T) = (3, 3)
7988 13:28:49.215887
7989 13:28:49.216137
7990 13:28:49.222390 [DQSOSCAuto] RK1, (LSB)MR18= 0x2323, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
7991 13:28:49.225222 CH0 RK1: MR19=303, MR18=2323
7992 13:28:49.232152 CH0_RK1: MR19=0x303, MR18=0x2323, DQSOSC=392, MR23=63, INC=24, DEC=16
7993 13:28:49.236015 [RxdqsGatingPostProcess] freq 1600
7994 13:28:49.238647 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7995 13:28:49.241920 Pre-setting of DQS Precalculation
7996 13:28:49.248528 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7997 13:28:49.249012 ==
7998 13:28:49.251830 Dram Type= 6, Freq= 0, CH_1, rank 0
7999 13:28:49.255243 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8000 13:28:49.255609 ==
8001 13:28:49.262218 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8002 13:28:49.265277 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8003 13:28:49.268159 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8004 13:28:49.275419 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8005 13:28:49.283949 [CA 0] Center 41 (11~72) winsize 62
8006 13:28:49.286931 [CA 1] Center 41 (11~72) winsize 62
8007 13:28:49.289849 [CA 2] Center 37 (8~67) winsize 60
8008 13:28:49.293598 [CA 3] Center 36 (6~66) winsize 61
8009 13:28:49.296752 [CA 4] Center 34 (4~64) winsize 61
8010 13:28:49.300105 [CA 5] Center 34 (5~64) winsize 60
8011 13:28:49.300609
8012 13:28:49.303693 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8013 13:28:49.304214
8014 13:28:49.306694 [CATrainingPosCal] consider 1 rank data
8015 13:28:49.309923 u2DelayCellTimex100 = 271/100 ps
8016 13:28:49.312943 CA0 delay=41 (11~72),Diff = 7 PI (25 cell)
8017 13:28:49.319881 CA1 delay=41 (11~72),Diff = 7 PI (25 cell)
8018 13:28:49.323106 CA2 delay=37 (8~67),Diff = 3 PI (10 cell)
8019 13:28:49.326889 CA3 delay=36 (6~66),Diff = 2 PI (7 cell)
8020 13:28:49.329660 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8021 13:28:49.333084 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
8022 13:28:49.333520
8023 13:28:49.336358 CA PerBit enable=1, Macro0, CA PI delay=34
8024 13:28:49.336741
8025 13:28:49.339780 [CBTSetCACLKResult] CA Dly = 34
8026 13:28:49.342877 CS Dly: 8 (0~39)
8027 13:28:49.346808 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8028 13:28:49.349996 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8029 13:28:49.350474 ==
8030 13:28:49.353045 Dram Type= 6, Freq= 0, CH_1, rank 1
8031 13:28:49.356609 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8032 13:28:49.359853 ==
8033 13:28:49.362502 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8034 13:28:49.366009 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8035 13:28:49.372679 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8036 13:28:49.379105 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8037 13:28:49.385906 [CA 0] Center 40 (10~70) winsize 61
8038 13:28:49.389413 [CA 1] Center 39 (9~70) winsize 62
8039 13:28:49.392687 [CA 2] Center 35 (6~65) winsize 60
8040 13:28:49.395756 [CA 3] Center 35 (6~65) winsize 60
8041 13:28:49.398782 [CA 4] Center 33 (3~63) winsize 61
8042 13:28:49.402208 [CA 5] Center 33 (4~63) winsize 60
8043 13:28:49.402595
8044 13:28:49.405896 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8045 13:28:49.406348
8046 13:28:49.409121 [CATrainingPosCal] consider 2 rank data
8047 13:28:49.412362 u2DelayCellTimex100 = 271/100 ps
8048 13:28:49.415678 CA0 delay=40 (11~70),Diff = 7 PI (25 cell)
8049 13:28:49.422277 CA1 delay=40 (11~70),Diff = 7 PI (25 cell)
8050 13:28:49.425779 CA2 delay=36 (8~65),Diff = 3 PI (10 cell)
8051 13:28:49.429143 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8052 13:28:49.432203 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8053 13:28:49.435308 CA5 delay=34 (5~63),Diff = 1 PI (3 cell)
8054 13:28:49.435704
8055 13:28:49.438834 CA PerBit enable=1, Macro0, CA PI delay=33
8056 13:28:49.439331
8057 13:28:49.442294 [CBTSetCACLKResult] CA Dly = 33
8058 13:28:49.445374 CS Dly: 9 (0~41)
8059 13:28:49.448476 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8060 13:28:49.452050 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8061 13:28:49.452469
8062 13:28:49.455530 ----->DramcWriteLeveling(PI) begin...
8063 13:28:49.455962 ==
8064 13:28:49.458463 Dram Type= 6, Freq= 0, CH_1, rank 0
8065 13:28:49.462367 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8066 13:28:49.465590 ==
8067 13:28:49.468752 Write leveling (Byte 0): 21 => 21
8068 13:28:49.469255 Write leveling (Byte 1): 21 => 21
8069 13:28:49.471885 DramcWriteLeveling(PI) end<-----
8070 13:28:49.472351
8071 13:28:49.472714 ==
8072 13:28:49.475813 Dram Type= 6, Freq= 0, CH_1, rank 0
8073 13:28:49.482103 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8074 13:28:49.482583 ==
8075 13:28:49.485796 [Gating] SW mode calibration
8076 13:28:49.491799 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8077 13:28:49.495171 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8078 13:28:49.501605 0 12 0 | B1->B0 | 2625 3434 | 1 1 | (1 1) (1 1)
8079 13:28:49.505680 0 12 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8080 13:28:49.508194 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8081 13:28:49.515340 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8082 13:28:49.518600 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8083 13:28:49.521667 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8084 13:28:49.528163 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8085 13:28:49.531683 0 12 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
8086 13:28:49.535090 0 13 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
8087 13:28:49.542187 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8088 13:28:49.545274 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8089 13:28:49.548405 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8090 13:28:49.551540 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8091 13:28:49.558508 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8092 13:28:49.561753 0 13 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8093 13:28:49.565058 0 13 28 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
8094 13:28:49.571840 0 14 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
8095 13:28:49.575188 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8096 13:28:49.578296 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8097 13:28:49.585245 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8098 13:28:49.588120 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8099 13:28:49.591651 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8100 13:28:49.598086 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8101 13:28:49.601295 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8102 13:28:49.604963 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8103 13:28:49.611379 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8104 13:28:49.614513 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 13:28:49.618311 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 13:28:49.624587 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 13:28:49.627977 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8108 13:28:49.631411 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8109 13:28:49.638054 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8110 13:28:49.641119 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8111 13:28:49.645180 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8112 13:28:49.651890 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8113 13:28:49.655010 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8114 13:28:49.657845 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8115 13:28:49.664622 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8116 13:28:49.667694 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8117 13:28:49.671346 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8118 13:28:49.677368 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8119 13:28:49.677806 Total UI for P1: 0, mck2ui 16
8120 13:28:49.684753 best dqsien dly found for B0: ( 1, 0, 26)
8121 13:28:49.687616 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8122 13:28:49.690635 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8123 13:28:49.694604 Total UI for P1: 0, mck2ui 16
8124 13:28:49.697919 best dqsien dly found for B1: ( 1, 1, 2)
8125 13:28:49.700547 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8126 13:28:49.703701 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8127 13:28:49.704063
8128 13:28:49.707314 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8129 13:28:49.714138 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8130 13:28:49.714482 [Gating] SW calibration Done
8131 13:28:49.714733 ==
8132 13:28:49.717390 Dram Type= 6, Freq= 0, CH_1, rank 0
8133 13:28:49.723643 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8134 13:28:49.723989 ==
8135 13:28:49.724235 RX Vref Scan: 0
8136 13:28:49.724499
8137 13:28:49.727149 RX Vref 0 -> 0, step: 1
8138 13:28:49.727492
8139 13:28:49.730372 RX Delay 0 -> 252, step: 8
8140 13:28:49.734157 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8141 13:28:49.737538 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8142 13:28:49.740605 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8143 13:28:49.747181 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8144 13:28:49.750377 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8145 13:28:49.753888 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8146 13:28:49.757132 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8147 13:28:49.760247 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8148 13:28:49.767324 iDelay=200, Bit 8, Center 103 (48 ~ 159) 112
8149 13:28:49.770482 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8150 13:28:49.773465 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8151 13:28:49.776678 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8152 13:28:49.779980 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8153 13:28:49.787283 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8154 13:28:49.789873 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8155 13:28:49.793266 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8156 13:28:49.793645 ==
8157 13:28:49.797185 Dram Type= 6, Freq= 0, CH_1, rank 0
8158 13:28:49.800138 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8159 13:28:49.803225 ==
8160 13:28:49.803603 DQS Delay:
8161 13:28:49.803878 DQS0 = 0, DQS1 = 0
8162 13:28:49.806880 DQM Delay:
8163 13:28:49.807397 DQM0 = 129, DQM1 = 126
8164 13:28:49.809967 DQ Delay:
8165 13:28:49.813130 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8166 13:28:49.816738 DQ4 =127, DQ5 =143, DQ6 =135, DQ7 =127
8167 13:28:49.819310 DQ8 =103, DQ9 =115, DQ10 =127, DQ11 =119
8168 13:28:49.822914 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8169 13:28:49.823259
8170 13:28:49.823563
8171 13:28:49.823785 ==
8172 13:28:49.826620 Dram Type= 6, Freq= 0, CH_1, rank 0
8173 13:28:49.829539 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8174 13:28:49.829969 ==
8175 13:28:49.830301
8176 13:28:49.833056
8177 13:28:49.833422 TX Vref Scan disable
8178 13:28:49.836208 == TX Byte 0 ==
8179 13:28:49.839588 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8180 13:28:49.843042 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8181 13:28:49.845904 == TX Byte 1 ==
8182 13:28:49.849864 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8183 13:28:49.853042 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8184 13:28:49.853398 ==
8185 13:28:49.855932 Dram Type= 6, Freq= 0, CH_1, rank 0
8186 13:28:49.863291 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8187 13:28:49.863820 ==
8188 13:28:49.874195
8189 13:28:49.877071 TX Vref early break, caculate TX vref
8190 13:28:49.880687 TX Vref=16, minBit 3, minWin=21, winSum=368
8191 13:28:49.883838 TX Vref=18, minBit 3, minWin=22, winSum=378
8192 13:28:49.887470 TX Vref=20, minBit 0, minWin=23, winSum=384
8193 13:28:49.890371 TX Vref=22, minBit 3, minWin=23, winSum=396
8194 13:28:49.893703 TX Vref=24, minBit 3, minWin=23, winSum=406
8195 13:28:49.900415 TX Vref=26, minBit 1, minWin=24, winSum=412
8196 13:28:49.903516 TX Vref=28, minBit 3, minWin=24, winSum=410
8197 13:28:49.907067 TX Vref=30, minBit 3, minWin=23, winSum=406
8198 13:28:49.910619 TX Vref=32, minBit 3, minWin=23, winSum=397
8199 13:28:49.913482 TX Vref=34, minBit 1, minWin=23, winSum=390
8200 13:28:49.919876 [TxChooseVref] Worse bit 1, Min win 24, Win sum 412, Final Vref 26
8201 13:28:49.920271
8202 13:28:49.923264 Final TX Range 0 Vref 26
8203 13:28:49.923637
8204 13:28:49.923891 ==
8205 13:28:49.927163 Dram Type= 6, Freq= 0, CH_1, rank 0
8206 13:28:49.929990 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8207 13:28:49.930344 ==
8208 13:28:49.930597
8209 13:28:49.930819
8210 13:28:49.933285 TX Vref Scan disable
8211 13:28:49.940126 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8212 13:28:49.940516 == TX Byte 0 ==
8213 13:28:49.944330 u2DelayCellOfst[0]=18 cells (5 PI)
8214 13:28:49.946814 u2DelayCellOfst[1]=10 cells (3 PI)
8215 13:28:49.950492 u2DelayCellOfst[2]=0 cells (0 PI)
8216 13:28:49.953289 u2DelayCellOfst[3]=7 cells (2 PI)
8217 13:28:49.956824 u2DelayCellOfst[4]=10 cells (3 PI)
8218 13:28:49.959909 u2DelayCellOfst[5]=18 cells (5 PI)
8219 13:28:49.963339 u2DelayCellOfst[6]=18 cells (5 PI)
8220 13:28:49.966810 u2DelayCellOfst[7]=7 cells (2 PI)
8221 13:28:49.969862 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8222 13:28:49.973189 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8223 13:28:49.976371 == TX Byte 1 ==
8224 13:28:49.976855 u2DelayCellOfst[8]=0 cells (0 PI)
8225 13:28:49.979873 u2DelayCellOfst[9]=7 cells (2 PI)
8226 13:28:49.983037 u2DelayCellOfst[10]=10 cells (3 PI)
8227 13:28:49.986487 u2DelayCellOfst[11]=7 cells (2 PI)
8228 13:28:49.989577 u2DelayCellOfst[12]=18 cells (5 PI)
8229 13:28:49.992829 u2DelayCellOfst[13]=21 cells (6 PI)
8230 13:28:49.996376 u2DelayCellOfst[14]=21 cells (6 PI)
8231 13:28:49.999253 u2DelayCellOfst[15]=18 cells (5 PI)
8232 13:28:50.002441 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8233 13:28:50.009371 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8234 13:28:50.009804 DramC Write-DBI on
8235 13:28:50.010056 ==
8236 13:28:50.012792 Dram Type= 6, Freq= 0, CH_1, rank 0
8237 13:28:50.019482 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8238 13:28:50.020167 ==
8239 13:28:50.020596
8240 13:28:50.020852
8241 13:28:50.021093 TX Vref Scan disable
8242 13:28:50.023077 == TX Byte 0 ==
8243 13:28:50.026193 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8244 13:28:50.029752 == TX Byte 1 ==
8245 13:28:50.032727 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8246 13:28:50.036063 DramC Write-DBI off
8247 13:28:50.036446
8248 13:28:50.036694 [DATLAT]
8249 13:28:50.036912 Freq=1600, CH1 RK0
8250 13:28:50.037120
8251 13:28:50.039719 DATLAT Default: 0xf
8252 13:28:50.040066 0, 0xFFFF, sum = 0
8253 13:28:50.043351 1, 0xFFFF, sum = 0
8254 13:28:50.046281 2, 0xFFFF, sum = 0
8255 13:28:50.046634 3, 0xFFFF, sum = 0
8256 13:28:50.049323 4, 0xFFFF, sum = 0
8257 13:28:50.049679 5, 0xFFFF, sum = 0
8258 13:28:50.052975 6, 0xFFFF, sum = 0
8259 13:28:50.053440 7, 0xFFFF, sum = 0
8260 13:28:50.056203 8, 0xFFFF, sum = 0
8261 13:28:50.056753 9, 0xFFFF, sum = 0
8262 13:28:50.059777 10, 0xFFFF, sum = 0
8263 13:28:50.060326 11, 0xFFFF, sum = 0
8264 13:28:50.062882 12, 0x8F7F, sum = 0
8265 13:28:50.063448 13, 0x0, sum = 1
8266 13:28:50.066286 14, 0x0, sum = 2
8267 13:28:50.066703 15, 0x0, sum = 3
8268 13:28:50.069579 16, 0x0, sum = 4
8269 13:28:50.070044 best_step = 14
8270 13:28:50.070371
8271 13:28:50.070612 ==
8272 13:28:50.072868 Dram Type= 6, Freq= 0, CH_1, rank 0
8273 13:28:50.075825 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8274 13:28:50.079359 ==
8275 13:28:50.079734 RX Vref Scan: 1
8276 13:28:50.079997
8277 13:28:50.082495 Set Vref Range= 24 -> 127
8278 13:28:50.082938
8279 13:28:50.086333 RX Vref 24 -> 127, step: 1
8280 13:28:50.086749
8281 13:28:50.087013 RX Delay 3 -> 252, step: 4
8282 13:28:50.087247
8283 13:28:50.089068 Set Vref, RX VrefLevel [Byte0]: 24
8284 13:28:50.092658 [Byte1]: 24
8285 13:28:50.096641
8286 13:28:50.096990 Set Vref, RX VrefLevel [Byte0]: 25
8287 13:28:50.099742 [Byte1]: 25
8288 13:28:50.103906
8289 13:28:50.104385 Set Vref, RX VrefLevel [Byte0]: 26
8290 13:28:50.110700 [Byte1]: 26
8291 13:28:50.111134
8292 13:28:50.113819 Set Vref, RX VrefLevel [Byte0]: 27
8293 13:28:50.117227 [Byte1]: 27
8294 13:28:50.117571
8295 13:28:50.120873 Set Vref, RX VrefLevel [Byte0]: 28
8296 13:28:50.123929 [Byte1]: 28
8297 13:28:50.127144
8298 13:28:50.127488 Set Vref, RX VrefLevel [Byte0]: 29
8299 13:28:50.130120 [Byte1]: 29
8300 13:28:50.134932
8301 13:28:50.135370 Set Vref, RX VrefLevel [Byte0]: 30
8302 13:28:50.137832 [Byte1]: 30
8303 13:28:50.142403
8304 13:28:50.142748 Set Vref, RX VrefLevel [Byte0]: 31
8305 13:28:50.145515 [Byte1]: 31
8306 13:28:50.150314
8307 13:28:50.150820 Set Vref, RX VrefLevel [Byte0]: 32
8308 13:28:50.153005 [Byte1]: 32
8309 13:28:50.158062
8310 13:28:50.158417 Set Vref, RX VrefLevel [Byte0]: 33
8311 13:28:50.161009 [Byte1]: 33
8312 13:28:50.164908
8313 13:28:50.165156 Set Vref, RX VrefLevel [Byte0]: 34
8314 13:28:50.168231 [Byte1]: 34
8315 13:28:50.173145
8316 13:28:50.173554 Set Vref, RX VrefLevel [Byte0]: 35
8317 13:28:50.176409 [Byte1]: 35
8318 13:28:50.180325
8319 13:28:50.180687 Set Vref, RX VrefLevel [Byte0]: 36
8320 13:28:50.183998 [Byte1]: 36
8321 13:28:50.188257
8322 13:28:50.188634 Set Vref, RX VrefLevel [Byte0]: 37
8323 13:28:50.191551 [Byte1]: 37
8324 13:28:50.195878
8325 13:28:50.196224 Set Vref, RX VrefLevel [Byte0]: 38
8326 13:28:50.199134 [Byte1]: 38
8327 13:28:50.203552
8328 13:28:50.203918 Set Vref, RX VrefLevel [Byte0]: 39
8329 13:28:50.206831 [Byte1]: 39
8330 13:28:50.211015
8331 13:28:50.211431 Set Vref, RX VrefLevel [Byte0]: 40
8332 13:28:50.214194 [Byte1]: 40
8333 13:28:50.219203
8334 13:28:50.219610 Set Vref, RX VrefLevel [Byte0]: 41
8335 13:28:50.222432 [Byte1]: 41
8336 13:28:50.226567
8337 13:28:50.226917 Set Vref, RX VrefLevel [Byte0]: 42
8338 13:28:50.229669 [Byte1]: 42
8339 13:28:50.234229
8340 13:28:50.234696 Set Vref, RX VrefLevel [Byte0]: 43
8341 13:28:50.237777 [Byte1]: 43
8342 13:28:50.241588
8343 13:28:50.241977 Set Vref, RX VrefLevel [Byte0]: 44
8344 13:28:50.245132 [Byte1]: 44
8345 13:28:50.249187
8346 13:28:50.249530 Set Vref, RX VrefLevel [Byte0]: 45
8347 13:28:50.252385 [Byte1]: 45
8348 13:28:50.257042
8349 13:28:50.257384 Set Vref, RX VrefLevel [Byte0]: 46
8350 13:28:50.260164 [Byte1]: 46
8351 13:28:50.264899
8352 13:28:50.265306 Set Vref, RX VrefLevel [Byte0]: 47
8353 13:28:50.267632 [Byte1]: 47
8354 13:28:50.272660
8355 13:28:50.275375 Set Vref, RX VrefLevel [Byte0]: 48
8356 13:28:50.275863 [Byte1]: 48
8357 13:28:50.280187
8358 13:28:50.280596 Set Vref, RX VrefLevel [Byte0]: 49
8359 13:28:50.283160 [Byte1]: 49
8360 13:28:50.287742
8361 13:28:50.288130 Set Vref, RX VrefLevel [Byte0]: 50
8362 13:28:50.290689 [Byte1]: 50
8363 13:28:50.295314
8364 13:28:50.295734 Set Vref, RX VrefLevel [Byte0]: 51
8365 13:28:50.298733 [Byte1]: 51
8366 13:28:50.303203
8367 13:28:50.303809 Set Vref, RX VrefLevel [Byte0]: 52
8368 13:28:50.306318 [Byte1]: 52
8369 13:28:50.310786
8370 13:28:50.311185 Set Vref, RX VrefLevel [Byte0]: 53
8371 13:28:50.314143 [Byte1]: 53
8372 13:28:50.318571
8373 13:28:50.319082 Set Vref, RX VrefLevel [Byte0]: 54
8374 13:28:50.321694 [Byte1]: 54
8375 13:28:50.325702
8376 13:28:50.326047 Set Vref, RX VrefLevel [Byte0]: 55
8377 13:28:50.329013 [Byte1]: 55
8378 13:28:50.333833
8379 13:28:50.334306 Set Vref, RX VrefLevel [Byte0]: 56
8380 13:28:50.337103 [Byte1]: 56
8381 13:28:50.341299
8382 13:28:50.341642 Set Vref, RX VrefLevel [Byte0]: 57
8383 13:28:50.344241 [Byte1]: 57
8384 13:28:50.348648
8385 13:28:50.348993 Set Vref, RX VrefLevel [Byte0]: 58
8386 13:28:50.352341 [Byte1]: 58
8387 13:28:50.356373
8388 13:28:50.356819 Set Vref, RX VrefLevel [Byte0]: 59
8389 13:28:50.359797 [Byte1]: 59
8390 13:28:50.364258
8391 13:28:50.364692 Set Vref, RX VrefLevel [Byte0]: 60
8392 13:28:50.367156 [Byte1]: 60
8393 13:28:50.371892
8394 13:28:50.372378 Set Vref, RX VrefLevel [Byte0]: 61
8395 13:28:50.375251 [Byte1]: 61
8396 13:28:50.379310
8397 13:28:50.379704 Set Vref, RX VrefLevel [Byte0]: 62
8398 13:28:50.382739 [Byte1]: 62
8399 13:28:50.387012
8400 13:28:50.387364 Set Vref, RX VrefLevel [Byte0]: 63
8401 13:28:50.390301 [Byte1]: 63
8402 13:28:50.394845
8403 13:28:50.395188 Set Vref, RX VrefLevel [Byte0]: 64
8404 13:28:50.398506 [Byte1]: 64
8405 13:28:50.402732
8406 13:28:50.403302 Set Vref, RX VrefLevel [Byte0]: 65
8407 13:28:50.405601 [Byte1]: 65
8408 13:28:50.410053
8409 13:28:50.410394 Set Vref, RX VrefLevel [Byte0]: 66
8410 13:28:50.413772 [Byte1]: 66
8411 13:28:50.417921
8412 13:28:50.418321 Set Vref, RX VrefLevel [Byte0]: 67
8413 13:28:50.421044 [Byte1]: 67
8414 13:28:50.425424
8415 13:28:50.425852 Set Vref, RX VrefLevel [Byte0]: 68
8416 13:28:50.428457 [Byte1]: 68
8417 13:28:50.433490
8418 13:28:50.433942 Set Vref, RX VrefLevel [Byte0]: 69
8419 13:28:50.436494 [Byte1]: 69
8420 13:28:50.441000
8421 13:28:50.441483 Set Vref, RX VrefLevel [Byte0]: 70
8422 13:28:50.444339 [Byte1]: 70
8423 13:28:50.448831
8424 13:28:50.449318 Set Vref, RX VrefLevel [Byte0]: 71
8425 13:28:50.451836 [Byte1]: 71
8426 13:28:50.456203
8427 13:28:50.456712 Set Vref, RX VrefLevel [Byte0]: 72
8428 13:28:50.459207 [Byte1]: 72
8429 13:28:50.464438
8430 13:28:50.464953 Set Vref, RX VrefLevel [Byte0]: 73
8431 13:28:50.467342 [Byte1]: 73
8432 13:28:50.471397
8433 13:28:50.471956 Set Vref, RX VrefLevel [Byte0]: 74
8434 13:28:50.474818 [Byte1]: 74
8435 13:28:50.479134
8436 13:28:50.479607 Final RX Vref Byte 0 = 60 to rank0
8437 13:28:50.482225 Final RX Vref Byte 1 = 56 to rank0
8438 13:28:50.485549 Final RX Vref Byte 0 = 60 to rank1
8439 13:28:50.488601 Final RX Vref Byte 1 = 56 to rank1==
8440 13:28:50.491854 Dram Type= 6, Freq= 0, CH_1, rank 0
8441 13:28:50.498868 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8442 13:28:50.499306 ==
8443 13:28:50.499574 DQS Delay:
8444 13:28:50.501842 DQS0 = 0, DQS1 = 0
8445 13:28:50.502188 DQM Delay:
8446 13:28:50.502433 DQM0 = 128, DQM1 = 124
8447 13:28:50.504964 DQ Delay:
8448 13:28:50.508794 DQ0 =134, DQ1 =124, DQ2 =116, DQ3 =128
8449 13:28:50.511551 DQ4 =130, DQ5 =138, DQ6 =136, DQ7 =124
8450 13:28:50.514966 DQ8 =106, DQ9 =114, DQ10 =128, DQ11 =114
8451 13:28:50.518733 DQ12 =132, DQ13 =134, DQ14 =134, DQ15 =134
8452 13:28:50.519079
8453 13:28:50.519322
8454 13:28:50.519558
8455 13:28:50.522253 [DramC_TX_OE_Calibration] TA2
8456 13:28:50.525207 Original DQ_B0 (3 6) =30, OEN = 27
8457 13:28:50.528493 Original DQ_B1 (3 6) =30, OEN = 27
8458 13:28:50.531999 24, 0x0, End_B0=24 End_B1=24
8459 13:28:50.532524 25, 0x0, End_B0=25 End_B1=25
8460 13:28:50.535009 26, 0x0, End_B0=26 End_B1=26
8461 13:28:50.538666 27, 0x0, End_B0=27 End_B1=27
8462 13:28:50.542008 28, 0x0, End_B0=28 End_B1=28
8463 13:28:50.545370 29, 0x0, End_B0=29 End_B1=29
8464 13:28:50.545872 30, 0x0, End_B0=30 End_B1=30
8465 13:28:50.548384 31, 0x4141, End_B0=30 End_B1=30
8466 13:28:50.551795 Byte0 end_step=30 best_step=27
8467 13:28:50.555151 Byte1 end_step=30 best_step=27
8468 13:28:50.558267 Byte0 TX OE(2T, 0.5T) = (3, 3)
8469 13:28:50.561630 Byte1 TX OE(2T, 0.5T) = (3, 3)
8470 13:28:50.562096
8471 13:28:50.562373
8472 13:28:50.568311 [DQSOSCAuto] RK0, (LSB)MR18= 0x2626, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
8473 13:28:50.571981 CH1 RK0: MR19=303, MR18=2626
8474 13:28:50.578297 CH1_RK0: MR19=0x303, MR18=0x2626, DQSOSC=390, MR23=63, INC=24, DEC=16
8475 13:28:50.578762
8476 13:28:50.581545 ----->DramcWriteLeveling(PI) begin...
8477 13:28:50.581930 ==
8478 13:28:50.584619 Dram Type= 6, Freq= 0, CH_1, rank 1
8479 13:28:50.588458 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8480 13:28:50.588918 ==
8481 13:28:50.591604 Write leveling (Byte 0): 23 => 23
8482 13:28:50.594676 Write leveling (Byte 1): 22 => 22
8483 13:28:50.598075 DramcWriteLeveling(PI) end<-----
8484 13:28:50.598540
8485 13:28:50.598818 ==
8486 13:28:50.601231 Dram Type= 6, Freq= 0, CH_1, rank 1
8487 13:28:50.604464 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8488 13:28:50.604847 ==
8489 13:28:50.607741 [Gating] SW mode calibration
8490 13:28:50.614421 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8491 13:28:50.621125 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8492 13:28:50.624538 0 12 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
8493 13:28:50.631614 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8494 13:28:50.634073 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8495 13:28:50.637746 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8496 13:28:50.644217 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8497 13:28:50.647449 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8498 13:28:50.650992 0 12 24 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
8499 13:28:50.657549 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8500 13:28:50.661025 0 13 0 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
8501 13:28:50.664320 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8502 13:28:50.670929 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8503 13:28:50.674570 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8504 13:28:50.677736 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8505 13:28:50.684458 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8506 13:28:50.687675 0 13 24 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8507 13:28:50.690931 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8508 13:28:50.693958 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8509 13:28:50.700715 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8510 13:28:50.703885 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8511 13:28:50.707154 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8512 13:28:50.713825 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8513 13:28:50.716989 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8514 13:28:50.720676 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8515 13:28:50.727227 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8516 13:28:50.730714 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8517 13:28:50.734095 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8518 13:28:50.740391 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8519 13:28:50.743953 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8520 13:28:50.747866 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8521 13:28:50.753914 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8522 13:28:50.757690 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8523 13:28:50.760404 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8524 13:28:50.767000 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8525 13:28:50.770217 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8526 13:28:50.773520 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8527 13:28:50.779905 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8528 13:28:50.783329 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8529 13:28:50.786799 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8530 13:28:50.793593 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8531 13:28:50.796906 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8532 13:28:50.799921 Total UI for P1: 0, mck2ui 16
8533 13:28:50.803747 best dqsien dly found for B0: ( 1, 0, 24)
8534 13:28:50.806578 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8535 13:28:50.813002 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8536 13:28:50.816615 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8537 13:28:50.819720 Total UI for P1: 0, mck2ui 16
8538 13:28:50.823331 best dqsien dly found for B1: ( 1, 1, 2)
8539 13:28:50.826564 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8540 13:28:50.829472 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8541 13:28:50.829787
8542 13:28:50.833042 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8543 13:28:50.835958 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8544 13:28:50.839594 [Gating] SW calibration Done
8545 13:28:50.840021 ==
8546 13:28:50.843378 Dram Type= 6, Freq= 0, CH_1, rank 1
8547 13:28:50.846316 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8548 13:28:50.849454 ==
8549 13:28:50.849797 RX Vref Scan: 0
8550 13:28:50.850038
8551 13:28:50.852941 RX Vref 0 -> 0, step: 1
8552 13:28:50.853373
8553 13:28:50.853617 RX Delay 0 -> 252, step: 8
8554 13:28:50.859869 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8555 13:28:50.863081 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8556 13:28:50.866458 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8557 13:28:50.869307 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8558 13:28:50.876244 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8559 13:28:50.879609 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8560 13:28:50.882994 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8561 13:28:50.885857 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8562 13:28:50.889497 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8563 13:28:50.895909 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8564 13:28:50.899302 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8565 13:28:50.902277 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8566 13:28:50.905910 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8567 13:28:50.909192 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8568 13:28:50.915829 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8569 13:28:50.919284 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8570 13:28:50.919720 ==
8571 13:28:50.922413 Dram Type= 6, Freq= 0, CH_1, rank 1
8572 13:28:50.926044 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8573 13:28:50.926524 ==
8574 13:28:50.929006 DQS Delay:
8575 13:28:50.929352 DQS0 = 0, DQS1 = 0
8576 13:28:50.929596 DQM Delay:
8577 13:28:50.932167 DQM0 = 131, DQM1 = 125
8578 13:28:50.932693 DQ Delay:
8579 13:28:50.935336 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8580 13:28:50.938597 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8581 13:28:50.945765 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =119
8582 13:28:50.948727 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8583 13:28:50.949095
8584 13:28:50.949334
8585 13:28:50.949552 ==
8586 13:28:50.951897 Dram Type= 6, Freq= 0, CH_1, rank 1
8587 13:28:50.955448 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8588 13:28:50.955917 ==
8589 13:28:50.956198
8590 13:28:50.956490
8591 13:28:50.958785 TX Vref Scan disable
8592 13:28:50.962034 == TX Byte 0 ==
8593 13:28:50.965581 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8594 13:28:50.968826 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8595 13:28:50.972306 == TX Byte 1 ==
8596 13:28:50.975382 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8597 13:28:50.978637 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8598 13:28:50.979108 ==
8599 13:28:50.981757 Dram Type= 6, Freq= 0, CH_1, rank 1
8600 13:28:50.985096 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8601 13:28:50.987997 ==
8602 13:28:51.000360
8603 13:28:51.003502 TX Vref early break, caculate TX vref
8604 13:28:51.006869 TX Vref=16, minBit 0, minWin=22, winSum=372
8605 13:28:51.010148 TX Vref=18, minBit 3, minWin=22, winSum=382
8606 13:28:51.013189 TX Vref=20, minBit 0, minWin=23, winSum=391
8607 13:28:51.016517 TX Vref=22, minBit 0, minWin=23, winSum=402
8608 13:28:51.019881 TX Vref=24, minBit 0, minWin=24, winSum=413
8609 13:28:51.026645 TX Vref=26, minBit 0, minWin=23, winSum=412
8610 13:28:51.029883 TX Vref=28, minBit 0, minWin=24, winSum=415
8611 13:28:51.033370 TX Vref=30, minBit 0, minWin=24, winSum=405
8612 13:28:51.036057 TX Vref=32, minBit 0, minWin=23, winSum=399
8613 13:28:51.039939 TX Vref=34, minBit 0, minWin=22, winSum=395
8614 13:28:51.043182 TX Vref=36, minBit 0, minWin=22, winSum=387
8615 13:28:51.049798 [TxChooseVref] Worse bit 0, Min win 24, Win sum 415, Final Vref 28
8616 13:28:51.050168
8617 13:28:51.053017 Final TX Range 0 Vref 28
8618 13:28:51.053371
8619 13:28:51.053618 ==
8620 13:28:51.056551 Dram Type= 6, Freq= 0, CH_1, rank 1
8621 13:28:51.059817 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8622 13:28:51.060183 ==
8623 13:28:51.060476
8624 13:28:51.062962
8625 13:28:51.063392 TX Vref Scan disable
8626 13:28:51.069383 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8627 13:28:51.069788 == TX Byte 0 ==
8628 13:28:51.073122 u2DelayCellOfst[0]=14 cells (4 PI)
8629 13:28:51.076161 u2DelayCellOfst[1]=10 cells (3 PI)
8630 13:28:51.079745 u2DelayCellOfst[2]=0 cells (0 PI)
8631 13:28:51.082955 u2DelayCellOfst[3]=7 cells (2 PI)
8632 13:28:51.086086 u2DelayCellOfst[4]=7 cells (2 PI)
8633 13:28:51.089723 u2DelayCellOfst[5]=14 cells (4 PI)
8634 13:28:51.093085 u2DelayCellOfst[6]=14 cells (4 PI)
8635 13:28:51.096016 u2DelayCellOfst[7]=3 cells (1 PI)
8636 13:28:51.099645 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8637 13:28:51.102906 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8638 13:28:51.106255 == TX Byte 1 ==
8639 13:28:51.109278 u2DelayCellOfst[8]=0 cells (0 PI)
8640 13:28:51.109740 u2DelayCellOfst[9]=7 cells (2 PI)
8641 13:28:51.112872 u2DelayCellOfst[10]=14 cells (4 PI)
8642 13:28:51.115848 u2DelayCellOfst[11]=7 cells (2 PI)
8643 13:28:51.119031 u2DelayCellOfst[12]=18 cells (5 PI)
8644 13:28:51.122717 u2DelayCellOfst[13]=21 cells (6 PI)
8645 13:28:51.125811 u2DelayCellOfst[14]=21 cells (6 PI)
8646 13:28:51.128822 u2DelayCellOfst[15]=21 cells (6 PI)
8647 13:28:51.135725 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8648 13:28:51.139151 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8649 13:28:51.139600 DramC Write-DBI on
8650 13:28:51.139883 ==
8651 13:28:51.142438 Dram Type= 6, Freq= 0, CH_1, rank 1
8652 13:28:51.148843 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8653 13:28:51.149260 ==
8654 13:28:51.149516
8655 13:28:51.149740
8656 13:28:51.149980 TX Vref Scan disable
8657 13:28:51.153046 == TX Byte 0 ==
8658 13:28:51.156679 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8659 13:28:51.159728 == TX Byte 1 ==
8660 13:28:51.163410 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8661 13:28:51.166444 DramC Write-DBI off
8662 13:28:51.166866
8663 13:28:51.167117 [DATLAT]
8664 13:28:51.167337 Freq=1600, CH1 RK1
8665 13:28:51.167552
8666 13:28:51.169701 DATLAT Default: 0xe
8667 13:28:51.170054 0, 0xFFFF, sum = 0
8668 13:28:51.172972 1, 0xFFFF, sum = 0
8669 13:28:51.176206 2, 0xFFFF, sum = 0
8670 13:28:51.176747 3, 0xFFFF, sum = 0
8671 13:28:51.179459 4, 0xFFFF, sum = 0
8672 13:28:51.179911 5, 0xFFFF, sum = 0
8673 13:28:51.183331 6, 0xFFFF, sum = 0
8674 13:28:51.183801 7, 0xFFFF, sum = 0
8675 13:28:51.186669 8, 0xFFFF, sum = 0
8676 13:28:51.187161 9, 0xFFFF, sum = 0
8677 13:28:51.190219 10, 0xFFFF, sum = 0
8678 13:28:51.190725 11, 0xFFFF, sum = 0
8679 13:28:51.193281 12, 0xF5F, sum = 0
8680 13:28:51.193785 13, 0x0, sum = 1
8681 13:28:51.196315 14, 0x0, sum = 2
8682 13:28:51.196710 15, 0x0, sum = 3
8683 13:28:51.200023 16, 0x0, sum = 4
8684 13:28:51.200585 best_step = 14
8685 13:28:51.200894
8686 13:28:51.201138 ==
8687 13:28:51.202596 Dram Type= 6, Freq= 0, CH_1, rank 1
8688 13:28:51.206059 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8689 13:28:51.209478 ==
8690 13:28:51.210022 RX Vref Scan: 0
8691 13:28:51.210405
8692 13:28:51.212390 RX Vref 0 -> 0, step: 1
8693 13:28:51.212760
8694 13:28:51.213014 RX Delay 3 -> 252, step: 4
8695 13:28:51.219811 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8696 13:28:51.223693 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8697 13:28:51.226597 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8698 13:28:51.230037 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8699 13:28:51.233287 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8700 13:28:51.239922 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8701 13:28:51.243895 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8702 13:28:51.247266 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8703 13:28:51.249982 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8704 13:28:51.253515 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8705 13:28:51.259982 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8706 13:28:51.263091 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8707 13:28:51.266668 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8708 13:28:51.270376 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8709 13:28:51.276947 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8710 13:28:51.279743 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8711 13:28:51.280138 ==
8712 13:28:51.283044 Dram Type= 6, Freq= 0, CH_1, rank 1
8713 13:28:51.286562 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8714 13:28:51.287061 ==
8715 13:28:51.289805 DQS Delay:
8716 13:28:51.290313 DQS0 = 0, DQS1 = 0
8717 13:28:51.290611 DQM Delay:
8718 13:28:51.292771 DQM0 = 127, DQM1 = 123
8719 13:28:51.293154 DQ Delay:
8720 13:28:51.295970 DQ0 =128, DQ1 =122, DQ2 =116, DQ3 =124
8721 13:28:51.299854 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8722 13:28:51.302796 DQ8 =104, DQ9 =112, DQ10 =124, DQ11 =114
8723 13:28:51.309684 DQ12 =132, DQ13 =132, DQ14 =134, DQ15 =132
8724 13:28:51.310193
8725 13:28:51.310459
8726 13:28:51.310681
8727 13:28:51.312591 [DramC_TX_OE_Calibration] TA2
8728 13:28:51.312960 Original DQ_B0 (3 6) =30, OEN = 27
8729 13:28:51.316063 Original DQ_B1 (3 6) =30, OEN = 27
8730 13:28:51.319119 24, 0x0, End_B0=24 End_B1=24
8731 13:28:51.322583 25, 0x0, End_B0=25 End_B1=25
8732 13:28:51.326099 26, 0x0, End_B0=26 End_B1=26
8733 13:28:51.329198 27, 0x0, End_B0=27 End_B1=27
8734 13:28:51.329316 28, 0x0, End_B0=28 End_B1=28
8735 13:28:51.332326 29, 0x0, End_B0=29 End_B1=29
8736 13:28:51.335706 30, 0x0, End_B0=30 End_B1=30
8737 13:28:51.339432 31, 0x4545, End_B0=30 End_B1=30
8738 13:28:51.342323 Byte0 end_step=30 best_step=27
8739 13:28:51.342478 Byte1 end_step=30 best_step=27
8740 13:28:51.345967 Byte0 TX OE(2T, 0.5T) = (3, 3)
8741 13:28:51.348990 Byte1 TX OE(2T, 0.5T) = (3, 3)
8742 13:28:51.349367
8743 13:28:51.349618
8744 13:28:51.359190 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
8745 13:28:51.359670 CH1 RK1: MR19=303, MR18=1F1F
8746 13:28:51.365827 CH1_RK1: MR19=0x303, MR18=0x1F1F, DQSOSC=394, MR23=63, INC=23, DEC=15
8747 13:28:51.368647 [RxdqsGatingPostProcess] freq 1600
8748 13:28:51.375662 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8749 13:28:51.379409 Pre-setting of DQS Precalculation
8750 13:28:51.382438 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8751 13:28:51.392271 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8752 13:28:51.399026 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8753 13:28:51.399441
8754 13:28:51.399682
8755 13:28:51.402225 [Calibration Summary] 3200 Mbps
8756 13:28:51.402634 CH 0, Rank 0
8757 13:28:51.405839 SW Impedance : PASS
8758 13:28:51.406191 DUTY Scan : NO K
8759 13:28:51.408551 ZQ Calibration : PASS
8760 13:28:51.412207 Jitter Meter : NO K
8761 13:28:51.412555 CBT Training : PASS
8762 13:28:51.415544 Write leveling : PASS
8763 13:28:51.418713 RX DQS gating : PASS
8764 13:28:51.419081 RX DQ/DQS(RDDQC) : PASS
8765 13:28:51.422381 TX DQ/DQS : PASS
8766 13:28:51.425689 RX DATLAT : PASS
8767 13:28:51.426036 RX DQ/DQS(Engine): PASS
8768 13:28:51.429098 TX OE : PASS
8769 13:28:51.429465 All Pass.
8770 13:28:51.429778
8771 13:28:51.431893 CH 0, Rank 1
8772 13:28:51.432164 SW Impedance : PASS
8773 13:28:51.435034 DUTY Scan : NO K
8774 13:28:51.435407 ZQ Calibration : PASS
8775 13:28:51.438567 Jitter Meter : NO K
8776 13:28:51.442307 CBT Training : PASS
8777 13:28:51.442380 Write leveling : PASS
8778 13:28:51.444673 RX DQS gating : PASS
8779 13:28:51.448662 RX DQ/DQS(RDDQC) : PASS
8780 13:28:51.448752 TX DQ/DQS : PASS
8781 13:28:51.452088 RX DATLAT : PASS
8782 13:28:51.455708 RX DQ/DQS(Engine): PASS
8783 13:28:51.456177 TX OE : PASS
8784 13:28:51.458915 All Pass.
8785 13:28:51.459385
8786 13:28:51.459654 CH 1, Rank 0
8787 13:28:51.461944 SW Impedance : PASS
8788 13:28:51.462412 DUTY Scan : NO K
8789 13:28:51.465282 ZQ Calibration : PASS
8790 13:28:51.468249 Jitter Meter : NO K
8791 13:28:51.468650 CBT Training : PASS
8792 13:28:51.471803 Write leveling : PASS
8793 13:28:51.474899 RX DQS gating : PASS
8794 13:28:51.475287 RX DQ/DQS(RDDQC) : PASS
8795 13:28:51.478379 TX DQ/DQS : PASS
8796 13:28:51.481645 RX DATLAT : PASS
8797 13:28:51.481995 RX DQ/DQS(Engine): PASS
8798 13:28:51.484988 TX OE : PASS
8799 13:28:51.485428 All Pass.
8800 13:28:51.485683
8801 13:28:51.487981 CH 1, Rank 1
8802 13:28:51.488447 SW Impedance : PASS
8803 13:28:51.491479 DUTY Scan : NO K
8804 13:28:51.494475 ZQ Calibration : PASS
8805 13:28:51.494821 Jitter Meter : NO K
8806 13:28:51.497988 CBT Training : PASS
8807 13:28:51.501381 Write leveling : PASS
8808 13:28:51.501746 RX DQS gating : PASS
8809 13:28:51.504442 RX DQ/DQS(RDDQC) : PASS
8810 13:28:51.504789 TX DQ/DQS : PASS
8811 13:28:51.507918 RX DATLAT : PASS
8812 13:28:51.511014 RX DQ/DQS(Engine): PASS
8813 13:28:51.511361 TX OE : PASS
8814 13:28:51.514368 All Pass.
8815 13:28:51.514713
8816 13:28:51.514965 DramC Write-DBI on
8817 13:28:51.517878 PER_BANK_REFRESH: Hybrid Mode
8818 13:28:51.521238 TX_TRACKING: ON
8819 13:28:51.527869 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8820 13:28:51.538019 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8821 13:28:51.544406 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8822 13:28:51.547770 [FAST_K] Save calibration result to emmc
8823 13:28:51.551150 sync common calibartion params.
8824 13:28:51.551535 sync cbt_mode0:0, 1:0
8825 13:28:51.554181 dram_init: ddr_geometry: 0
8826 13:28:51.558017 dram_init: ddr_geometry: 0
8827 13:28:51.561080 dram_init: ddr_geometry: 0
8828 13:28:51.561442 0:dram_rank_size:80000000
8829 13:28:51.564409 1:dram_rank_size:80000000
8830 13:28:51.571090 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8831 13:28:51.571531 DFS_SHUFFLE_HW_MODE: ON
8832 13:28:51.574256 dramc_set_vcore_voltage set vcore to 725000
8833 13:28:51.577501 Read voltage for 1600, 0
8834 13:28:51.577876 Vio18 = 0
8835 13:28:51.581190 Vcore = 725000
8836 13:28:51.581540 Vdram = 0
8837 13:28:51.581782 Vddq = 0
8838 13:28:51.584138 Vmddr = 0
8839 13:28:51.584534 switch to 3200 Mbps bootup
8840 13:28:51.587819 [DramcRunTimeConfig]
8841 13:28:51.588162 PHYPLL
8842 13:28:51.590928 DPM_CONTROL_AFTERK: ON
8843 13:28:51.591273 PER_BANK_REFRESH: ON
8844 13:28:51.594395 REFRESH_OVERHEAD_REDUCTION: ON
8845 13:28:51.597783 CMD_PICG_NEW_MODE: OFF
8846 13:28:51.598196 XRTWTW_NEW_MODE: ON
8847 13:28:51.601322 XRTRTR_NEW_MODE: ON
8848 13:28:51.601668 TX_TRACKING: ON
8849 13:28:51.604451 RDSEL_TRACKING: OFF
8850 13:28:51.607730 DQS Precalculation for DVFS: ON
8851 13:28:51.608074 RX_TRACKING: OFF
8852 13:28:51.610332 HW_GATING DBG: ON
8853 13:28:51.610675 ZQCS_ENABLE_LP4: ON
8854 13:28:51.614295 RX_PICG_NEW_MODE: ON
8855 13:28:51.614766 TX_PICG_NEW_MODE: ON
8856 13:28:51.617063 ENABLE_RX_DCM_DPHY: ON
8857 13:28:51.620894 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8858 13:28:51.623807 DUMMY_READ_FOR_TRACKING: OFF
8859 13:28:51.624134 !!! SPM_CONTROL_AFTERK: OFF
8860 13:28:51.627507 !!! SPM could not control APHY
8861 13:28:51.630621 IMPEDANCE_TRACKING: ON
8862 13:28:51.630982 TEMP_SENSOR: ON
8863 13:28:51.634219 HW_SAVE_FOR_SR: OFF
8864 13:28:51.637110 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8865 13:28:51.640743 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8866 13:28:51.641180 Read ODT Tracking: ON
8867 13:28:51.644373 Refresh Rate DeBounce: ON
8868 13:28:51.647390 DFS_NO_QUEUE_FLUSH: ON
8869 13:28:51.650536 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8870 13:28:51.653703 ENABLE_DFS_RUNTIME_MRW: OFF
8871 13:28:51.654051 DDR_RESERVE_NEW_MODE: ON
8872 13:28:51.657674 MR_CBT_SWITCH_FREQ: ON
8873 13:28:51.660428 =========================
8874 13:28:51.677657 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8875 13:28:51.680630 dram_init: ddr_geometry: 0
8876 13:28:51.698850 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8877 13:28:51.702595 dram_init: dram init end (result: 0)
8878 13:28:51.708555 DRAM-K: Full calibration passed in 23431 msecs
8879 13:28:51.712550 MRC: failed to locate region type 0.
8880 13:28:51.712932 DRAM rank0 size:0x80000000,
8881 13:28:51.715221 DRAM rank1 size=0x80000000
8882 13:28:51.725542 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8883 13:28:51.731924 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8884 13:28:51.738520 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8885 13:28:51.745172 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8886 13:28:51.748964 DRAM rank0 size:0x80000000,
8887 13:28:51.752224 DRAM rank1 size=0x80000000
8888 13:28:51.752597 CBMEM:
8889 13:28:51.755613 IMD: root @ 0xfffff000 254 entries.
8890 13:28:51.758620 IMD: root @ 0xffffec00 62 entries.
8891 13:28:51.761674 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8892 13:28:51.765299 WARNING: RO_VPD is uninitialized or empty.
8893 13:28:51.771779 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8894 13:28:51.778407 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8895 13:28:51.791304 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8896 13:28:51.802608 BS: romstage times (exec / console): total (unknown) / 22976 ms
8897 13:28:51.803003
8898 13:28:51.803255
8899 13:28:51.812398 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8900 13:28:51.815855 ARM64: Exception handlers installed.
8901 13:28:51.819356 ARM64: Testing exception
8902 13:28:51.822609 ARM64: Done test exception
8903 13:28:51.822962 Enumerating buses...
8904 13:28:51.826021 Show all devs... Before device enumeration.
8905 13:28:51.829428 Root Device: enabled 1
8906 13:28:51.832185 CPU_CLUSTER: 0: enabled 1
8907 13:28:51.832571 CPU: 00: enabled 1
8908 13:28:51.835667 Compare with tree...
8909 13:28:51.836037 Root Device: enabled 1
8910 13:28:51.838871 CPU_CLUSTER: 0: enabled 1
8911 13:28:51.842805 CPU: 00: enabled 1
8912 13:28:51.843217 Root Device scanning...
8913 13:28:51.846028 scan_static_bus for Root Device
8914 13:28:51.849087 CPU_CLUSTER: 0 enabled
8915 13:28:51.852134 scan_static_bus for Root Device done
8916 13:28:51.855532 scan_bus: bus Root Device finished in 8 msecs
8917 13:28:51.855605 done
8918 13:28:51.862587 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8919 13:28:51.866121 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8920 13:28:51.872573 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8921 13:28:51.875459 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8922 13:28:51.879075 Allocating resources...
8923 13:28:51.882153 Reading resources...
8924 13:28:51.885461 Root Device read_resources bus 0 link: 0
8925 13:28:51.885536 DRAM rank0 size:0x80000000,
8926 13:28:51.888951 DRAM rank1 size=0x80000000
8927 13:28:51.892017 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8928 13:28:51.894903 CPU: 00 missing read_resources
8929 13:28:51.898443 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8930 13:28:51.905568 Root Device read_resources bus 0 link: 0 done
8931 13:28:51.905915 Done reading resources.
8932 13:28:51.911854 Show resources in subtree (Root Device)...After reading.
8933 13:28:51.915006 Root Device child on link 0 CPU_CLUSTER: 0
8934 13:28:51.918431 CPU_CLUSTER: 0 child on link 0 CPU: 00
8935 13:28:51.928803 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8936 13:28:51.929121 CPU: 00
8937 13:28:51.931896 Root Device assign_resources, bus 0 link: 0
8938 13:28:51.935366 CPU_CLUSTER: 0 missing set_resources
8939 13:28:51.942191 Root Device assign_resources, bus 0 link: 0 done
8940 13:28:51.942560 Done setting resources.
8941 13:28:51.948222 Show resources in subtree (Root Device)...After assigning values.
8942 13:28:51.951848 Root Device child on link 0 CPU_CLUSTER: 0
8943 13:28:51.955070 CPU_CLUSTER: 0 child on link 0 CPU: 00
8944 13:28:51.964837 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8945 13:28:51.965259 CPU: 00
8946 13:28:51.968494 Done allocating resources.
8947 13:28:51.971429 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8948 13:28:51.974754 Enabling resources...
8949 13:28:51.975067 done.
8950 13:28:51.981425 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8951 13:28:51.981774 Initializing devices...
8952 13:28:51.984913 Root Device init
8953 13:28:51.985357 init hardware done!
8954 13:28:51.988016 0x00000018: ctrlr->caps
8955 13:28:51.991573 52.000 MHz: ctrlr->f_max
8956 13:28:51.991977 0.400 MHz: ctrlr->f_min
8957 13:28:51.994784 0x40ff8080: ctrlr->voltages
8958 13:28:51.995319 sclk: 390625
8959 13:28:51.998128 Bus Width = 1
8960 13:28:51.998643 sclk: 390625
8961 13:28:52.001404 Bus Width = 1
8962 13:28:52.001857 Early init status = 3
8963 13:28:52.007967 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8964 13:28:52.011709 in-header: 03 fc 00 00 01 00 00 00
8965 13:28:52.012125 in-data: 00
8966 13:28:52.018393 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8967 13:28:52.021300 in-header: 03 fd 00 00 00 00 00 00
8968 13:28:52.024939 in-data:
8969 13:28:52.027866 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8970 13:28:52.031760 in-header: 03 fc 00 00 01 00 00 00
8971 13:28:52.035064 in-data: 00
8972 13:28:52.038344 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8973 13:28:52.044493 in-header: 03 fd 00 00 00 00 00 00
8974 13:28:52.047377 in-data:
8975 13:28:52.050658 [SSUSB] Setting up USB HOST controller...
8976 13:28:52.054112 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8977 13:28:52.057791 [SSUSB] phy power-on done.
8978 13:28:52.060546 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8979 13:28:52.067776 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8980 13:28:52.070522 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8981 13:28:52.077323 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8982 13:28:52.084373 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
8983 13:28:52.090696 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8984 13:28:52.097371 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8985 13:28:52.103761 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
8986 13:28:52.106869 SPM: binary array size = 0x9dc
8987 13:28:52.110326 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8988 13:28:52.116731 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8989 13:28:52.123874 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8990 13:28:52.127431 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8991 13:28:52.133673 configure_display: Starting display init
8992 13:28:52.167530 anx7625_power_on_init: Init interface.
8993 13:28:52.170671 anx7625_disable_pd_protocol: Disabled PD feature.
8994 13:28:52.173698 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8995 13:28:52.201777 anx7625_start_dp_work: Secure OCM version=00
8996 13:28:52.205038 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8997 13:28:52.219639 sp_tx_get_edid_block: EDID Block = 1
8998 13:28:52.322545 Extracted contents:
8999 13:28:52.326002 header: 00 ff ff ff ff ff ff 00
9000 13:28:52.329051 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9001 13:28:52.332194 version: 01 04
9002 13:28:52.335832 basic params: 95 1f 11 78 0a
9003 13:28:52.338908 chroma info: 76 90 94 55 54 90 27 21 50 54
9004 13:28:52.342361 established: 00 00 00
9005 13:28:52.348942 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9006 13:28:52.351884 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9007 13:28:52.359264 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9008 13:28:52.365099 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9009 13:28:52.371846 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9010 13:28:52.375353 extensions: 00
9011 13:28:52.375701 checksum: fb
9012 13:28:52.375949
9013 13:28:52.378371 Manufacturer: IVO Model 57d Serial Number 0
9014 13:28:52.381674 Made week 0 of 2020
9015 13:28:52.382021 EDID version: 1.4
9016 13:28:52.385004 Digital display
9017 13:28:52.388737 6 bits per primary color channel
9018 13:28:52.389251 DisplayPort interface
9019 13:28:52.391518 Maximum image size: 31 cm x 17 cm
9020 13:28:52.395105 Gamma: 220%
9021 13:28:52.395449 Check DPMS levels
9022 13:28:52.398652 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9023 13:28:52.405378 First detailed timing is preferred timing
9024 13:28:52.405788 Established timings supported:
9025 13:28:52.408857 Standard timings supported:
9026 13:28:52.412183 Detailed timings
9027 13:28:52.415053 Hex of detail: 383680a07038204018303c0035ae10000019
9028 13:28:52.422155 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9029 13:28:52.424914 0780 0798 07c8 0820 hborder 0
9030 13:28:52.428468 0438 043b 0447 0458 vborder 0
9031 13:28:52.431798 -hsync -vsync
9032 13:28:52.432258 Did detailed timing
9033 13:28:52.437805 Hex of detail: 000000000000000000000000000000000000
9034 13:28:52.441970 Manufacturer-specified data, tag 0
9035 13:28:52.444670 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9036 13:28:52.448022 ASCII string: InfoVision
9037 13:28:52.451133 Hex of detail: 000000fe00523134304e574635205248200a
9038 13:28:52.454978 ASCII string: R140NWF5 RH
9039 13:28:52.455323 Checksum
9040 13:28:52.457740 Checksum: 0xfb (valid)
9041 13:28:52.461662 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9042 13:28:52.464560 DSI data_rate: 832800000 bps
9043 13:28:52.470995 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9044 13:28:52.474592 anx7625_parse_edid: pixelclock(138800).
9045 13:28:52.478090 hactive(1920), hsync(48), hfp(24), hbp(88)
9046 13:28:52.480942 vactive(1080), vsync(12), vfp(3), vbp(17)
9047 13:28:52.484462 anx7625_dsi_config: config dsi.
9048 13:28:52.491228 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9049 13:28:52.504390 anx7625_dsi_config: success to config DSI
9050 13:28:52.507886 anx7625_dp_start: MIPI phy setup OK.
9051 13:28:52.511254 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9052 13:28:52.514379 mtk_ddp_mode_set invalid vrefresh 60
9053 13:28:52.517777 main_disp_path_setup
9054 13:28:52.518196 ovl_layer_smi_id_en
9055 13:28:52.520578 ovl_layer_smi_id_en
9056 13:28:52.521084 ccorr_config
9057 13:28:52.521350 aal_config
9058 13:28:52.523859 gamma_config
9059 13:28:52.524207 postmask_config
9060 13:28:52.527230 dither_config
9061 13:28:52.530861 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9062 13:28:52.537399 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9063 13:28:52.540831 Root Device init finished in 553 msecs
9064 13:28:52.544033 CPU_CLUSTER: 0 init
9065 13:28:52.550781 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9066 13:28:52.557152 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9067 13:28:52.557501 APU_MBOX 0x190000b0 = 0x10001
9068 13:28:52.561087 APU_MBOX 0x190001b0 = 0x10001
9069 13:28:52.563859 APU_MBOX 0x190005b0 = 0x10001
9070 13:28:52.567419 APU_MBOX 0x190006b0 = 0x10001
9071 13:28:52.574098 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9072 13:28:52.583648 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9073 13:28:52.595814 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9074 13:28:52.602229 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9075 13:28:52.614219 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9076 13:28:52.623371 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9077 13:28:52.626692 CPU_CLUSTER: 0 init finished in 81 msecs
9078 13:28:52.630122 Devices initialized
9079 13:28:52.633248 Show all devs... After init.
9080 13:28:52.633615 Root Device: enabled 1
9081 13:28:52.636303 CPU_CLUSTER: 0: enabled 1
9082 13:28:52.640337 CPU: 00: enabled 1
9083 13:28:52.643743 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9084 13:28:52.646815 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9085 13:28:52.649876 ELOG: NV offset 0x57f000 size 0x1000
9086 13:28:52.656206 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9087 13:28:52.663151 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9088 13:28:52.666455 ELOG: Event(17) added with size 13 at 2023-09-08 13:28:52 UTC
9089 13:28:52.669515 out: cmd=0x121: 03 db 21 01 00 00 00 00
9090 13:28:52.674876 in-header: 03 e8 00 00 2c 00 00 00
9091 13:28:52.687728 in-data: 7b 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9092 13:28:52.694517 ELOG: Event(A1) added with size 10 at 2023-09-08 13:28:52 UTC
9093 13:28:52.701414 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9094 13:28:52.707636 ELOG: Event(A0) added with size 9 at 2023-09-08 13:28:52 UTC
9095 13:28:52.711090 elog_add_boot_reason: Logged dev mode boot
9096 13:28:52.713973 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9097 13:28:52.717473 Finalize devices...
9098 13:28:52.717856 Devices finalized
9099 13:28:52.724597 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9100 13:28:52.727374 Writing coreboot table at 0xffe64000
9101 13:28:52.730875 0. 000000000010a000-0000000000113fff: RAMSTAGE
9102 13:28:52.734268 1. 0000000040000000-00000000400fffff: RAM
9103 13:28:52.740932 2. 0000000040100000-000000004032afff: RAMSTAGE
9104 13:28:52.744084 3. 000000004032b000-00000000545fffff: RAM
9105 13:28:52.747698 4. 0000000054600000-000000005465ffff: BL31
9106 13:28:52.750695 5. 0000000054660000-00000000ffe63fff: RAM
9107 13:28:52.757805 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9108 13:28:52.760744 7. 0000000100000000-000000013fffffff: RAM
9109 13:28:52.763917 Passing 5 GPIOs to payload:
9110 13:28:52.767535 NAME | PORT | POLARITY | VALUE
9111 13:28:52.770749 EC in RW | 0x000000aa | low | undefined
9112 13:28:52.777434 EC interrupt | 0x00000005 | low | undefined
9113 13:28:52.781024 TPM interrupt | 0x000000ab | high | undefined
9114 13:28:52.787327 SD card detect | 0x00000011 | high | undefined
9115 13:28:52.790467 speaker enable | 0x00000093 | high | undefined
9116 13:28:52.794240 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9117 13:28:52.797060 in-header: 03 f8 00 00 02 00 00 00
9118 13:28:52.797412 in-data: 03 00
9119 13:28:52.800611 ADC[4]: Raw value=668958 ID=5
9120 13:28:52.803952 ADC[3]: Raw value=212917 ID=1
9121 13:28:52.807426 RAM Code: 0x51
9122 13:28:52.807880 ADC[6]: Raw value=74410 ID=0
9123 13:28:52.810675 ADC[5]: Raw value=211075 ID=1
9124 13:28:52.813571 SKU Code: 0x1
9125 13:28:52.817099 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 17eb
9126 13:28:52.820410 coreboot table: 964 bytes.
9127 13:28:52.823826 IMD ROOT 0. 0xfffff000 0x00001000
9128 13:28:52.827046 IMD SMALL 1. 0xffffe000 0x00001000
9129 13:28:52.830305 RO MCACHE 2. 0xffffc000 0x00001104
9130 13:28:52.833296 CONSOLE 3. 0xfff7c000 0x00080000
9131 13:28:52.836961 FMAP 4. 0xfff7b000 0x00000452
9132 13:28:52.840192 TIME STAMP 5. 0xfff7a000 0x00000910
9133 13:28:52.843287 VBOOT WORK 6. 0xfff66000 0x00014000
9134 13:28:52.846420 RAMOOPS 7. 0xffe66000 0x00100000
9135 13:28:52.850123 COREBOOT 8. 0xffe64000 0x00002000
9136 13:28:52.850477 IMD small region:
9137 13:28:52.853515 IMD ROOT 0. 0xffffec00 0x00000400
9138 13:28:52.859875 VPD 1. 0xffffeb80 0x0000006c
9139 13:28:52.863387 MMC STATUS 2. 0xffffeb60 0x00000004
9140 13:28:52.866846 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9141 13:28:52.870109 Probing TPM: done!
9142 13:28:52.873901 Connected to device vid:did:rid of 1ae0:0028:00
9143 13:28:52.883535 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9144 13:28:52.887131 Initialized TPM device CR50 revision 0
9145 13:28:52.890566 Checking cr50 for pending updates
9146 13:28:52.893909 Reading cr50 TPM mode
9147 13:28:52.902594 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9148 13:28:52.909086 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9149 13:28:52.949146 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9150 13:28:52.952414 Checking segment from ROM address 0x40100000
9151 13:28:52.955646 Checking segment from ROM address 0x4010001c
9152 13:28:52.962704 Loading segment from ROM address 0x40100000
9153 13:28:52.963165 code (compression=0)
9154 13:28:52.972488 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9155 13:28:52.979337 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9156 13:28:52.979809 it's not compressed!
9157 13:28:52.985879 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9158 13:28:52.992266 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9159 13:28:53.009605 Loading segment from ROM address 0x4010001c
9160 13:28:53.010045 Entry Point 0x80000000
9161 13:28:53.013205 Loaded segments
9162 13:28:53.016326 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9163 13:28:53.022770 Jumping to boot code at 0x80000000(0xffe64000)
9164 13:28:53.029432 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9165 13:28:53.035973 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9166 13:28:53.044135 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9167 13:28:53.047752 Checking segment from ROM address 0x40100000
9168 13:28:53.051093 Checking segment from ROM address 0x4010001c
9169 13:28:53.057885 Loading segment from ROM address 0x40100000
9170 13:28:53.058444 code (compression=1)
9171 13:28:53.064146 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9172 13:28:53.074387 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9173 13:28:53.074822 using LZMA
9174 13:28:53.082281 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9175 13:28:53.089422 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9176 13:28:53.093045 Loading segment from ROM address 0x4010001c
9177 13:28:53.093568 Entry Point 0x54601000
9178 13:28:53.095909 Loaded segments
9179 13:28:53.099116 NOTICE: MT8192 bl31_setup
9180 13:28:53.105942 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9181 13:28:53.109213 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9182 13:28:53.112373 WARNING: region 0:
9183 13:28:53.116380 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9184 13:28:53.116747 WARNING: region 1:
9185 13:28:53.122822 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9186 13:28:53.126174 WARNING: region 2:
9187 13:28:53.129608 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9188 13:28:53.132633 WARNING: region 3:
9189 13:28:53.136040 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9190 13:28:53.139325 WARNING: region 4:
9191 13:28:53.146136 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9192 13:28:53.146524 WARNING: region 5:
9193 13:28:53.148955 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9194 13:28:53.152779 WARNING: region 6:
9195 13:28:53.155878 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9196 13:28:53.159232 WARNING: region 7:
9197 13:28:53.163268 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9198 13:28:53.169538 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9199 13:28:53.172967 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9200 13:28:53.176210 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9201 13:28:53.183232 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9202 13:28:53.185798 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9203 13:28:53.189482 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9204 13:28:53.195879 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9205 13:28:53.199531 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9206 13:28:53.205972 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9207 13:28:53.209592 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9208 13:28:53.212798 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9209 13:28:53.219551 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9210 13:28:53.222508 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9211 13:28:53.226108 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9212 13:28:53.232696 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9213 13:28:53.236466 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9214 13:28:53.239686 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9215 13:28:53.245995 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9216 13:28:53.249336 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9217 13:28:53.252521 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9218 13:28:53.259865 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9219 13:28:53.262814 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9220 13:28:53.269073 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9221 13:28:53.273071 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9222 13:28:53.279731 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9223 13:28:53.282656 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9224 13:28:53.286161 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9225 13:28:53.292918 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9226 13:28:53.296229 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9227 13:28:53.302644 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9228 13:28:53.305898 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9229 13:28:53.308924 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9230 13:28:53.315622 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9231 13:28:53.319105 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9232 13:28:53.322097 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9233 13:28:53.325675 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9234 13:28:53.332632 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9235 13:28:53.335592 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9236 13:28:53.339301 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9237 13:28:53.342529 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9238 13:28:53.349157 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9239 13:28:53.352079 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9240 13:28:53.355870 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9241 13:28:53.358753 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9242 13:28:53.365888 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9243 13:28:53.368753 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9244 13:28:53.372249 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9245 13:28:53.375688 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9246 13:28:53.382316 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9247 13:28:53.385776 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9248 13:28:53.392714 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9249 13:28:53.395791 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9250 13:28:53.402276 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9251 13:28:53.405329 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9252 13:28:53.408906 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9253 13:28:53.415872 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9254 13:28:53.418915 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9255 13:28:53.425584 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9256 13:28:53.429342 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9257 13:28:53.435440 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9258 13:28:53.439121 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9259 13:28:53.442251 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9260 13:28:53.449082 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9261 13:28:53.452123 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9262 13:28:53.458843 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9263 13:28:53.462819 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9264 13:28:53.469336 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9265 13:28:53.471971 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9266 13:28:53.475638 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9267 13:28:53.482307 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9268 13:28:53.485924 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9269 13:28:53.492143 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9270 13:28:53.495943 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9271 13:28:53.499080 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9272 13:28:53.505994 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9273 13:28:53.509055 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9274 13:28:53.515923 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9275 13:28:53.519254 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9276 13:28:53.525600 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9277 13:28:53.529035 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9278 13:28:53.535878 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9279 13:28:53.539145 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9280 13:28:53.542480 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9281 13:28:53.549149 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9282 13:28:53.552906 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9283 13:28:53.559310 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9284 13:28:53.562913 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9285 13:28:53.565751 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9286 13:28:53.572814 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9287 13:28:53.576084 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9288 13:28:53.582715 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9289 13:28:53.586129 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9290 13:28:53.593077 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9291 13:28:53.596321 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9292 13:28:53.602578 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9293 13:28:53.606088 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9294 13:28:53.609285 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9295 13:28:53.613070 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9296 13:28:53.619608 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9297 13:28:53.622591 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9298 13:28:53.626134 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9299 13:28:53.632635 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9300 13:28:53.635803 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9301 13:28:53.639300 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9302 13:28:53.646277 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9303 13:28:53.649500 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9304 13:28:53.655928 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9305 13:28:53.659069 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9306 13:28:53.663315 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9307 13:28:53.669468 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9308 13:28:53.673021 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9309 13:28:53.679229 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9310 13:28:53.682744 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9311 13:28:53.686255 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9312 13:28:53.693174 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9313 13:28:53.695995 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9314 13:28:53.699972 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9315 13:28:53.706131 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9316 13:28:53.709563 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9317 13:28:53.712887 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9318 13:28:53.716182 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9319 13:28:53.722507 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9320 13:28:53.726369 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9321 13:28:53.729612 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9322 13:28:53.736044 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9323 13:28:53.739292 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9324 13:28:53.742859 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9325 13:28:53.749438 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9326 13:28:53.752773 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9327 13:28:53.759505 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9328 13:28:53.763109 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9329 13:28:53.765989 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9330 13:28:53.773038 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9331 13:28:53.775916 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9332 13:28:53.780154 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9333 13:28:53.786183 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9334 13:28:53.789580 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9335 13:28:53.796155 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9336 13:28:53.799735 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9337 13:28:53.803318 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9338 13:28:53.809712 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9339 13:28:53.813422 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9340 13:28:53.816313 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9341 13:28:53.822664 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9342 13:28:53.826285 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9343 13:28:53.832894 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9344 13:28:53.836335 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9345 13:28:53.839764 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9346 13:28:53.846735 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9347 13:28:53.849607 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9348 13:28:53.856262 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9349 13:28:53.859701 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9350 13:28:53.863271 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9351 13:28:53.869453 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9352 13:28:53.872861 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9353 13:28:53.879735 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9354 13:28:53.883165 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9355 13:28:53.887091 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9356 13:28:53.893090 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9357 13:28:53.896145 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9358 13:28:53.899710 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9359 13:28:53.905915 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9360 13:28:53.909687 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9361 13:28:53.915978 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9362 13:28:53.919501 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9363 13:28:53.922767 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9364 13:28:53.929589 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9365 13:28:53.932327 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9366 13:28:53.939304 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9367 13:28:53.942315 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9368 13:28:53.946431 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9369 13:28:53.952307 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9370 13:28:53.956246 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9371 13:28:53.962794 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9372 13:28:53.965890 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9373 13:28:53.968980 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9374 13:28:53.975805 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9375 13:28:53.979120 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9376 13:28:53.985427 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9377 13:28:53.989146 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9378 13:28:53.992544 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9379 13:28:53.999223 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9380 13:28:54.002185 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9381 13:28:54.005612 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9382 13:28:54.012269 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9383 13:28:54.016268 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9384 13:28:54.022101 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9385 13:28:54.026231 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9386 13:28:54.029024 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9387 13:28:54.036124 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9388 13:28:54.038978 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9389 13:28:54.045631 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9390 13:28:54.048723 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9391 13:28:54.052473 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9392 13:28:54.059185 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9393 13:28:54.062180 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9394 13:28:54.068359 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9395 13:28:54.071784 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9396 13:28:54.078792 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9397 13:28:54.082437 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9398 13:28:54.085707 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9399 13:28:54.091908 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9400 13:28:54.095352 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9401 13:28:54.101639 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9402 13:28:54.104990 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9403 13:28:54.111427 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9404 13:28:54.114801 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9405 13:28:54.117929 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9406 13:28:54.125152 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9407 13:28:54.128265 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9408 13:28:54.134375 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9409 13:28:54.137714 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9410 13:28:54.144985 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9411 13:28:54.148243 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9412 13:28:54.151248 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9413 13:28:54.158124 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9414 13:28:54.161321 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9415 13:28:54.167951 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9416 13:28:54.171354 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9417 13:28:54.177449 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9418 13:28:54.181032 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9419 13:28:54.184140 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9420 13:28:54.190990 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9421 13:28:54.193958 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9422 13:28:54.200348 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9423 13:28:54.203721 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9424 13:28:54.210564 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9425 13:28:54.214166 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9426 13:28:54.217048 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9427 13:28:54.224227 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9428 13:28:54.226952 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9429 13:28:54.231041 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9430 13:28:54.233935 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9431 13:28:54.237336 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9432 13:28:54.243578 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9433 13:28:54.247016 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9434 13:28:54.253435 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9435 13:28:54.256957 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9436 13:28:54.260205 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9437 13:28:54.267387 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9438 13:28:54.270505 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9439 13:28:54.276776 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9440 13:28:54.280614 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9441 13:28:54.283686 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9442 13:28:54.290247 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9443 13:28:54.293798 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9444 13:28:54.296474 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9445 13:28:54.303364 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9446 13:28:54.306253 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9447 13:28:54.310259 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9448 13:28:54.316374 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9449 13:28:54.320128 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9450 13:28:54.326127 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9451 13:28:54.329850 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9452 13:28:54.332817 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9453 13:28:54.339298 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9454 13:28:54.342539 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9455 13:28:54.346122 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9456 13:28:54.352759 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9457 13:28:54.355883 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9458 13:28:54.362911 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9459 13:28:54.366143 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9460 13:28:54.369294 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9461 13:28:54.375901 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9462 13:28:54.379739 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9463 13:28:54.382713 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9464 13:28:54.389644 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9465 13:28:54.392812 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9466 13:28:54.395725 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9467 13:28:54.402703 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9468 13:28:54.405462 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9469 13:28:54.409014 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9470 13:28:54.412670 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9471 13:28:54.415188 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9472 13:28:54.421852 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9473 13:28:54.425239 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9474 13:28:54.429055 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9475 13:28:54.435245 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9476 13:28:54.438671 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9477 13:28:54.441850 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9478 13:28:54.445528 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9479 13:28:54.452117 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9480 13:28:54.455155 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9481 13:28:54.462200 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9482 13:28:54.465779 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9483 13:28:54.468805 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9484 13:28:54.475234 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9485 13:28:54.478809 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9486 13:28:54.485284 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9487 13:28:54.489096 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9488 13:28:54.492002 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9489 13:28:54.498445 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9490 13:28:54.501694 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9491 13:28:54.508347 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9492 13:28:54.511780 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9493 13:28:54.518627 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9494 13:28:54.521709 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9495 13:28:54.524921 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9496 13:28:54.531239 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9497 13:28:54.534984 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9498 13:28:54.541669 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9499 13:28:54.544662 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9500 13:28:54.548014 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9501 13:28:54.554789 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9502 13:28:54.558261 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9503 13:28:54.564241 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9504 13:28:54.568210 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9505 13:28:54.571554 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9506 13:28:54.578245 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9507 13:28:54.581689 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9508 13:28:54.588111 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9509 13:28:54.591459 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9510 13:28:54.597703 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9511 13:28:54.601208 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9512 13:28:54.604596 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9513 13:28:54.611595 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9514 13:28:54.614858 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9515 13:28:54.621245 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9516 13:28:54.624246 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9517 13:28:54.627946 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9518 13:28:54.634559 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9519 13:28:54.637747 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9520 13:28:54.643867 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9521 13:28:54.647695 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9522 13:28:54.650950 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9523 13:28:54.657783 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9524 13:28:54.660932 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9525 13:28:54.667255 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9526 13:28:54.670856 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9527 13:28:54.674085 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9528 13:28:54.680723 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9529 13:28:54.683667 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9530 13:28:54.690889 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9531 13:28:54.693926 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9532 13:28:54.700432 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9533 13:28:54.704042 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9534 13:28:54.707311 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9535 13:28:54.714417 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9536 13:28:54.717366 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9537 13:28:54.723702 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9538 13:28:54.726848 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9539 13:28:54.730725 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9540 13:28:54.737551 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9541 13:28:54.740270 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9542 13:28:54.747406 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9543 13:28:54.750981 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9544 13:28:54.753811 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9545 13:28:54.760560 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9546 13:28:54.763848 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9547 13:28:54.770376 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9548 13:28:54.773495 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9549 13:28:54.780597 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9550 13:28:54.783285 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9551 13:28:54.786836 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9552 13:28:54.793615 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9553 13:28:54.796832 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9554 13:28:54.803902 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9555 13:28:54.806870 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9556 13:28:54.810494 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9557 13:28:54.816640 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9558 13:28:54.820136 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9559 13:28:54.826521 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9560 13:28:54.830134 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9561 13:28:54.837093 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9562 13:28:54.840113 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9563 13:28:54.846570 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9564 13:28:54.850087 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9565 13:28:54.852880 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9566 13:28:54.859871 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9567 13:28:54.863104 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9568 13:28:54.870395 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9569 13:28:54.873085 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9570 13:28:54.879632 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9571 13:28:54.882816 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9572 13:28:54.886142 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9573 13:28:54.893123 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9574 13:28:54.895835 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9575 13:28:54.902875 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9576 13:28:54.905948 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9577 13:28:54.913079 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9578 13:28:54.916355 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9579 13:28:54.922904 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9580 13:28:54.926007 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9581 13:28:54.929730 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9582 13:28:54.936129 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9583 13:28:54.939405 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9584 13:28:54.945637 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9585 13:28:54.949207 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9586 13:28:54.955797 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9587 13:28:54.958896 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9588 13:28:54.965733 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9589 13:28:54.969729 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9590 13:28:54.972241 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9591 13:28:54.979096 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9592 13:28:54.982194 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9593 13:28:54.988740 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9594 13:28:54.991988 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9595 13:28:54.998993 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9596 13:28:55.002209 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9597 13:28:55.008734 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9598 13:28:55.011772 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9599 13:28:55.014906 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9600 13:28:55.022318 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9601 13:28:55.025047 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9602 13:28:55.031934 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9603 13:28:55.035284 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9604 13:28:55.041887 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9605 13:28:55.044897 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9606 13:28:55.047716 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9607 13:28:55.054803 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9608 13:28:55.058421 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9609 13:28:55.065343 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9610 13:28:55.068194 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9611 13:28:55.074988 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9612 13:28:55.078317 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9613 13:28:55.085002 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9614 13:28:55.088547 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9615 13:28:55.095224 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9616 13:28:55.098047 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9617 13:28:55.104666 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9618 13:28:55.108046 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9619 13:28:55.115762 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9620 13:28:55.117675 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9621 13:28:55.124658 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9622 13:28:55.127457 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9623 13:28:55.134586 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9624 13:28:55.137758 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9625 13:28:55.144047 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9626 13:28:55.147881 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9627 13:28:55.154042 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9628 13:28:55.157807 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9629 13:28:55.164376 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9630 13:28:55.167736 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9631 13:28:55.174414 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9632 13:28:55.177982 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9633 13:28:55.181154 INFO: [APUAPC] vio 0
9634 13:28:55.184381 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9635 13:28:55.190695 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9636 13:28:55.194233 INFO: [APUAPC] D0_APC_0: 0x400510
9637 13:28:55.194703 INFO: [APUAPC] D0_APC_1: 0x0
9638 13:28:55.197507 INFO: [APUAPC] D0_APC_2: 0x1540
9639 13:28:55.200664 INFO: [APUAPC] D0_APC_3: 0x0
9640 13:28:55.203846 INFO: [APUAPC] D1_APC_0: 0xffffffff
9641 13:28:55.207609 INFO: [APUAPC] D1_APC_1: 0xffffffff
9642 13:28:55.210415 INFO: [APUAPC] D1_APC_2: 0x3fffff
9643 13:28:55.213774 INFO: [APUAPC] D1_APC_3: 0x0
9644 13:28:55.217102 INFO: [APUAPC] D2_APC_0: 0xffffffff
9645 13:28:55.221421 INFO: [APUAPC] D2_APC_1: 0xffffffff
9646 13:28:55.223955 INFO: [APUAPC] D2_APC_2: 0x3fffff
9647 13:28:55.227202 INFO: [APUAPC] D2_APC_3: 0x0
9648 13:28:55.230417 INFO: [APUAPC] D3_APC_0: 0xffffffff
9649 13:28:55.233944 INFO: [APUAPC] D3_APC_1: 0xffffffff
9650 13:28:55.237017 INFO: [APUAPC] D3_APC_2: 0x3fffff
9651 13:28:55.240167 INFO: [APUAPC] D3_APC_3: 0x0
9652 13:28:55.243372 INFO: [APUAPC] D4_APC_0: 0xffffffff
9653 13:28:55.246930 INFO: [APUAPC] D4_APC_1: 0xffffffff
9654 13:28:55.250726 INFO: [APUAPC] D4_APC_2: 0x3fffff
9655 13:28:55.253763 INFO: [APUAPC] D4_APC_3: 0x0
9656 13:28:55.257092 INFO: [APUAPC] D5_APC_0: 0xffffffff
9657 13:28:55.260105 INFO: [APUAPC] D5_APC_1: 0xffffffff
9658 13:28:55.263988 INFO: [APUAPC] D5_APC_2: 0x3fffff
9659 13:28:55.267150 INFO: [APUAPC] D5_APC_3: 0x0
9660 13:28:55.270598 INFO: [APUAPC] D6_APC_0: 0xffffffff
9661 13:28:55.273823 INFO: [APUAPC] D6_APC_1: 0xffffffff
9662 13:28:55.277039 INFO: [APUAPC] D6_APC_2: 0x3fffff
9663 13:28:55.280227 INFO: [APUAPC] D6_APC_3: 0x0
9664 13:28:55.283727 INFO: [APUAPC] D7_APC_0: 0xffffffff
9665 13:28:55.286895 INFO: [APUAPC] D7_APC_1: 0xffffffff
9666 13:28:55.290268 INFO: [APUAPC] D7_APC_2: 0x3fffff
9667 13:28:55.293286 INFO: [APUAPC] D7_APC_3: 0x0
9668 13:28:55.296823 INFO: [APUAPC] D8_APC_0: 0xffffffff
9669 13:28:55.300253 INFO: [APUAPC] D8_APC_1: 0xffffffff
9670 13:28:55.303229 INFO: [APUAPC] D8_APC_2: 0x3fffff
9671 13:28:55.306886 INFO: [APUAPC] D8_APC_3: 0x0
9672 13:28:55.310143 INFO: [APUAPC] D9_APC_0: 0xffffffff
9673 13:28:55.313981 INFO: [APUAPC] D9_APC_1: 0xffffffff
9674 13:28:55.316783 INFO: [APUAPC] D9_APC_2: 0x3fffff
9675 13:28:55.319786 INFO: [APUAPC] D9_APC_3: 0x0
9676 13:28:55.322996 INFO: [APUAPC] D10_APC_0: 0xffffffff
9677 13:28:55.326525 INFO: [APUAPC] D10_APC_1: 0xffffffff
9678 13:28:55.329724 INFO: [APUAPC] D10_APC_2: 0x3fffff
9679 13:28:55.333362 INFO: [APUAPC] D10_APC_3: 0x0
9680 13:28:55.336367 INFO: [APUAPC] D11_APC_0: 0xffffffff
9681 13:28:55.339649 INFO: [APUAPC] D11_APC_1: 0xffffffff
9682 13:28:55.342667 INFO: [APUAPC] D11_APC_2: 0x3fffff
9683 13:28:55.346113 INFO: [APUAPC] D11_APC_3: 0x0
9684 13:28:55.350053 INFO: [APUAPC] D12_APC_0: 0xffffffff
9685 13:28:55.353479 INFO: [APUAPC] D12_APC_1: 0xffffffff
9686 13:28:55.355907 INFO: [APUAPC] D12_APC_2: 0x3fffff
9687 13:28:55.359725 INFO: [APUAPC] D12_APC_3: 0x0
9688 13:28:55.363053 INFO: [APUAPC] D13_APC_0: 0xffffffff
9689 13:28:55.366214 INFO: [APUAPC] D13_APC_1: 0xffffffff
9690 13:28:55.369332 INFO: [APUAPC] D13_APC_2: 0x3fffff
9691 13:28:55.372483 INFO: [APUAPC] D13_APC_3: 0x0
9692 13:28:55.375816 INFO: [APUAPC] D14_APC_0: 0xffffffff
9693 13:28:55.379257 INFO: [APUAPC] D14_APC_1: 0xffffffff
9694 13:28:55.382712 INFO: [APUAPC] D14_APC_2: 0x3fffff
9695 13:28:55.386271 INFO: [APUAPC] D14_APC_3: 0x0
9696 13:28:55.389318 INFO: [APUAPC] D15_APC_0: 0xffffffff
9697 13:28:55.392443 INFO: [APUAPC] D15_APC_1: 0xffffffff
9698 13:28:55.396081 INFO: [APUAPC] D15_APC_2: 0x3fffff
9699 13:28:55.399545 INFO: [APUAPC] D15_APC_3: 0x0
9700 13:28:55.402743 INFO: [APUAPC] APC_CON: 0x4
9701 13:28:55.406160 INFO: [NOCDAPC] D0_APC_0: 0x0
9702 13:28:55.406611 INFO: [NOCDAPC] D0_APC_1: 0x0
9703 13:28:55.408995 INFO: [NOCDAPC] D1_APC_0: 0x0
9704 13:28:55.412507 INFO: [NOCDAPC] D1_APC_1: 0xfff
9705 13:28:55.416000 INFO: [NOCDAPC] D2_APC_0: 0x0
9706 13:28:55.419389 INFO: [NOCDAPC] D2_APC_1: 0xfff
9707 13:28:55.422812 INFO: [NOCDAPC] D3_APC_0: 0x0
9708 13:28:55.426031 INFO: [NOCDAPC] D3_APC_1: 0xfff
9709 13:28:55.429174 INFO: [NOCDAPC] D4_APC_0: 0x0
9710 13:28:55.433157 INFO: [NOCDAPC] D4_APC_1: 0xfff
9711 13:28:55.436085 INFO: [NOCDAPC] D5_APC_0: 0x0
9712 13:28:55.436477 INFO: [NOCDAPC] D5_APC_1: 0xfff
9713 13:28:55.439201 INFO: [NOCDAPC] D6_APC_0: 0x0
9714 13:28:55.442493 INFO: [NOCDAPC] D6_APC_1: 0xfff
9715 13:28:55.446004 INFO: [NOCDAPC] D7_APC_0: 0x0
9716 13:28:55.449274 INFO: [NOCDAPC] D7_APC_1: 0xfff
9717 13:28:55.452241 INFO: [NOCDAPC] D8_APC_0: 0x0
9718 13:28:55.455601 INFO: [NOCDAPC] D8_APC_1: 0xfff
9719 13:28:55.458967 INFO: [NOCDAPC] D9_APC_0: 0x0
9720 13:28:55.462415 INFO: [NOCDAPC] D9_APC_1: 0xfff
9721 13:28:55.465969 INFO: [NOCDAPC] D10_APC_0: 0x0
9722 13:28:55.468917 INFO: [NOCDAPC] D10_APC_1: 0xfff
9723 13:28:55.471989 INFO: [NOCDAPC] D11_APC_0: 0x0
9724 13:28:55.475455 INFO: [NOCDAPC] D11_APC_1: 0xfff
9725 13:28:55.475892 INFO: [NOCDAPC] D12_APC_0: 0x0
9726 13:28:55.478784 INFO: [NOCDAPC] D12_APC_1: 0xfff
9727 13:28:55.482839 INFO: [NOCDAPC] D13_APC_0: 0x0
9728 13:28:55.485308 INFO: [NOCDAPC] D13_APC_1: 0xfff
9729 13:28:55.488914 INFO: [NOCDAPC] D14_APC_0: 0x0
9730 13:28:55.492014 INFO: [NOCDAPC] D14_APC_1: 0xfff
9731 13:28:55.495219 INFO: [NOCDAPC] D15_APC_0: 0x0
9732 13:28:55.499309 INFO: [NOCDAPC] D15_APC_1: 0xfff
9733 13:28:55.501645 INFO: [NOCDAPC] APC_CON: 0x4
9734 13:28:55.505255 INFO: [APUAPC] set_apusys_apc done
9735 13:28:55.508681 INFO: [DEVAPC] devapc_init done
9736 13:28:55.512442 INFO: GICv3 without legacy support detected.
9737 13:28:55.515082 INFO: ARM GICv3 driver initialized in EL3
9738 13:28:55.518646 INFO: Maximum SPI INTID supported: 639
9739 13:28:55.525114 INFO: BL31: Initializing runtime services
9740 13:28:55.528189 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9741 13:28:55.531357 INFO: SPM: enable CPC mode
9742 13:28:55.538249 INFO: mcdi ready for mcusys-off-idle and system suspend
9743 13:28:55.541950 INFO: BL31: Preparing for EL3 exit to normal world
9744 13:28:55.545068 INFO: Entry point address = 0x80000000
9745 13:28:55.548084 INFO: SPSR = 0x8
9746 13:28:55.553766
9747 13:28:55.554111
9748 13:28:55.554359
9749 13:28:55.556839 Starting depthcharge on Spherion...
9750 13:28:55.557183
9751 13:28:55.557427 Wipe memory regions:
9752 13:28:55.557645
9753 13:28:55.559146 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9754 13:28:55.559508 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9755 13:28:55.559792 Setting prompt string to ['asurada:']
9756 13:28:55.560065 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9757 13:28:55.560610 [0x00000040000000, 0x00000054600000)
9758 13:28:55.683144
9759 13:28:55.683659 [0x00000054660000, 0x00000080000000)
9760 13:28:55.942844
9761 13:28:55.943292 [0x000000821a7280, 0x000000ffe64000)
9762 13:28:56.686423
9763 13:28:56.686923 [0x00000100000000, 0x00000140000000)
9764 13:28:57.066278
9765 13:28:57.069071 Initializing XHCI USB controller at 0x11200000.
9766 13:28:58.107250
9767 13:28:58.110292 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9768 13:28:58.110745
9769 13:28:58.111023
9770 13:28:58.111257
9771 13:28:58.111864 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9773 13:28:58.212993 asurada: tftpboot 192.168.201.1 11471184/tftp-deploy-xgwar0g1/kernel/image.itb 11471184/tftp-deploy-xgwar0g1/kernel/cmdline
9774 13:28:58.213597 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9775 13:28:58.213993 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9776 13:28:58.218911 tftpboot 192.168.201.1 11471184/tftp-deploy-xgwar0g1/kernel/image.itp-deploy-xgwar0g1/kernel/cmdline
9777 13:28:58.219414
9778 13:28:58.219697 Waiting for link
9779 13:28:58.379209
9780 13:28:58.379692 R8152: Initializing
9781 13:28:58.379987
9782 13:28:58.382645 Version 9 (ocp_data = 6010)
9783 13:28:58.383132
9784 13:28:58.385604 R8152: Done initializing
9785 13:28:58.386092
9786 13:28:58.386381 Adding net device
9787 13:29:00.395202
9788 13:29:00.395691 done.
9789 13:29:00.395980
9790 13:29:00.396224 MAC: 00:e0:4c:68:03:bd
9791 13:29:00.396494
9792 13:29:00.397974 Sending DHCP discover... done.
9793 13:29:00.398350
9794 13:29:04.109536 Waiting for reply... done.
9795 13:29:04.109973
9796 13:29:04.110233 Sending DHCP request... done.
9797 13:29:04.110457
9798 13:29:04.122710 Waiting for reply... done.
9799 13:29:04.123138
9800 13:29:04.123525 My ip is 192.168.201.16
9801 13:29:04.123892
9802 13:29:04.125281 The DHCP server ip is 192.168.201.1
9803 13:29:04.125699
9804 13:29:04.131898 TFTP server IP predefined by user: 192.168.201.1
9805 13:29:04.131976
9806 13:29:04.138497 Bootfile predefined by user: 11471184/tftp-deploy-xgwar0g1/kernel/image.itb
9807 13:29:04.138582
9808 13:29:04.138644 Sending tftp read request... done.
9809 13:29:04.141946
9810 13:29:04.145246 Waiting for the transfer...
9811 13:29:04.145332
9812 13:29:04.375909 00000000 ################################################################
9813 13:29:04.376049
9814 13:29:04.606311 00080000 ################################################################
9815 13:29:04.606461
9816 13:29:04.835681 00100000 ################################################################
9817 13:29:04.835825
9818 13:29:05.065104 00180000 ################################################################
9819 13:29:05.065239
9820 13:29:05.294215 00200000 ################################################################
9821 13:29:05.294348
9822 13:29:05.524171 00280000 ################################################################
9823 13:29:05.524316
9824 13:29:05.755193 00300000 ################################################################
9825 13:29:05.755323
9826 13:29:05.985399 00380000 ################################################################
9827 13:29:05.985570
9828 13:29:06.216386 00400000 ################################################################
9829 13:29:06.216508
9830 13:29:06.447864 00480000 ################################################################
9831 13:29:06.448008
9832 13:29:06.677677 00500000 ################################################################
9833 13:29:06.677824
9834 13:29:06.907734 00580000 ################################################################
9835 13:29:06.907871
9836 13:29:07.139968 00600000 ################################################################
9837 13:29:07.140102
9838 13:29:07.369915 00680000 ################################################################
9839 13:29:07.370055
9840 13:29:07.599715 00700000 ################################################################
9841 13:29:07.599856
9842 13:29:07.828361 00780000 ################################################################
9843 13:29:07.828495
9844 13:29:08.056852 00800000 ################################################################
9845 13:29:08.056997
9846 13:29:08.289000 00880000 ################################################################
9847 13:29:08.289126
9848 13:29:08.519962 00900000 ################################################################
9849 13:29:08.520101
9850 13:29:08.748886 00980000 ################################################################
9851 13:29:08.749022
9852 13:29:08.979479 00a00000 ################################################################
9853 13:29:08.979616
9854 13:29:09.207975 00a80000 ################################################################
9855 13:29:09.208119
9856 13:29:09.438146 00b00000 ################################################################
9857 13:29:09.438280
9858 13:29:09.666881 00b80000 ################################################################
9859 13:29:09.667032
9860 13:29:09.896730 00c00000 ################################################################
9861 13:29:09.896891
9862 13:29:10.128116 00c80000 ################################################################
9863 13:29:10.128263
9864 13:29:10.358182 00d00000 ################################################################
9865 13:29:10.358306
9866 13:29:10.588300 00d80000 ################################################################
9867 13:29:10.588445
9868 13:29:10.818510 00e00000 ################################################################
9869 13:29:10.818686
9870 13:29:11.048107 00e80000 ################################################################
9871 13:29:11.048241
9872 13:29:11.278925 00f00000 ################################################################
9873 13:29:11.279070
9874 13:29:11.507575 00f80000 ################################################################
9875 13:29:11.507717
9876 13:29:11.735870 01000000 ################################################################
9877 13:29:11.736004
9878 13:29:11.965189 01080000 ################################################################
9879 13:29:11.965319
9880 13:29:12.194891 01100000 ################################################################
9881 13:29:12.195029
9882 13:29:12.426142 01180000 ################################################################
9883 13:29:12.426277
9884 13:29:12.656315 01200000 ################################################################
9885 13:29:12.656456
9886 13:29:12.886329 01280000 ################################################################
9887 13:29:12.886471
9888 13:29:13.115474 01300000 ################################################################
9889 13:29:13.115611
9890 13:29:13.344146 01380000 ################################################################
9891 13:29:13.344299
9892 13:29:13.572628 01400000 ################################################################
9893 13:29:13.572755
9894 13:29:13.802715 01480000 ################################################################
9895 13:29:13.802848
9896 13:29:14.033141 01500000 ################################################################
9897 13:29:14.033257
9898 13:29:14.263161 01580000 ################################################################
9899 13:29:14.263304
9900 13:29:14.496469 01600000 ################################################################
9901 13:29:14.496613
9902 13:29:14.726520 01680000 ################################################################
9903 13:29:14.726657
9904 13:29:14.958590 01700000 ################################################################
9905 13:29:14.958733
9906 13:29:15.188932 01780000 ################################################################
9907 13:29:15.189085
9908 13:29:15.416798 01800000 ################################################################
9909 13:29:15.416938
9910 13:29:15.645516 01880000 ################################################################
9911 13:29:15.645637
9912 13:29:15.873432 01900000 ################################################################
9913 13:29:15.873581
9914 13:29:16.102043 01980000 ################################################################
9915 13:29:16.102184
9916 13:29:16.332915 01a00000 ################################################################
9917 13:29:16.333054
9918 13:29:16.563614 01a80000 ################################################################
9919 13:29:16.563756
9920 13:29:16.792793 01b00000 ################################################################
9921 13:29:16.792929
9922 13:29:17.022696 01b80000 ################################################################
9923 13:29:17.022843
9924 13:29:17.253729 01c00000 ################################################################
9925 13:29:17.253859
9926 13:29:17.483451 01c80000 ################################################################
9927 13:29:17.483601
9928 13:29:17.712724 01d00000 ################################################################
9929 13:29:17.712839
9930 13:29:17.942892 01d80000 ################################################################
9931 13:29:17.943029
9932 13:29:18.172334 01e00000 ################################################################
9933 13:29:18.172479
9934 13:29:18.386090 01e80000 ############################################################# done.
9935 13:29:18.386224
9936 13:29:18.389723 The bootfile was 32476002 bytes long.
9937 13:29:18.389792
9938 13:29:18.392705 Sending tftp read request... done.
9939 13:29:18.392772
9940 13:29:18.396171 Waiting for the transfer...
9941 13:29:18.396234
9942 13:29:18.396297 00000000 # done.
9943 13:29:18.396396
9944 13:29:18.406408 Command line loaded dynamically from TFTP file: 11471184/tftp-deploy-xgwar0g1/kernel/cmdline
9945 13:29:18.406469
9946 13:29:18.419444 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
9947 13:29:18.419502
9948 13:29:18.419567 Loading FIT.
9949 13:29:18.419613
9950 13:29:18.422969 Image ramdisk-1 has 21386593 bytes.
9951 13:29:18.423024
9952 13:29:18.426048 Image fdt-1 has 47278 bytes.
9953 13:29:18.426102
9954 13:29:18.429358 Image kernel-1 has 11040095 bytes.
9955 13:29:18.429420
9956 13:29:18.436020 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
9957 13:29:18.439145
9958 13:29:18.455755 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
9959 13:29:18.455818
9960 13:29:18.459162 Choosing best match conf-1 for compat google,spherion-rev3.
9961 13:29:18.464654
9962 13:29:18.468913 Connected to device vid:did:rid of 1ae0:0028:00
9963 13:29:18.475935
9964 13:29:18.479226 tpm_get_response: command 0x17b, return code 0x0
9965 13:29:18.479285
9966 13:29:18.482458 ec_init: CrosEC protocol v3 supported (256, 248)
9967 13:29:18.487918
9968 13:29:18.491208 tpm_cleanup: add release locality here.
9969 13:29:18.491277
9970 13:29:18.491333 Shutting down all USB controllers.
9971 13:29:18.494499
9972 13:29:18.494565 Removing current net device
9973 13:29:18.494629
9974 13:29:18.501024 Exiting depthcharge with code 4 at timestamp: 51182530
9975 13:29:18.501092
9976 13:29:18.504221 LZMA decompressing kernel-1 to 0x821a6718
9977 13:29:18.504285
9978 13:29:18.507747 LZMA decompressing kernel-1 to 0x40000000
9979 13:29:19.894885
9980 13:29:19.895028 jumping to kernel
9981 13:29:19.895404 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
9982 13:29:19.895515 start: 2.2.5 auto-login-action (timeout 00:04:02) [common]
9983 13:29:19.895585 Setting prompt string to ['Linux version [0-9]']
9984 13:29:19.895642 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9985 13:29:19.895697 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
9986 13:29:19.945312
9987 13:29:19.948487 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
9988 13:29:19.952474 start: 2.2.5.1 login-action (timeout 00:04:02) [common]
9989 13:29:19.952548 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
9990 13:29:19.952601 Setting prompt string to []
9991 13:29:19.952662 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
9992 13:29:19.952720 Using line separator: #'\n'#
9993 13:29:19.952766 No login prompt set.
9994 13:29:19.952816 Parsing kernel messages
9995 13:29:19.952860 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
9996 13:29:19.952940 [login-action] Waiting for messages, (timeout 00:04:02)
9997 13:29:19.971712 [ 0.000000] Linux version 6.1.52-cip5 (KernelCI@build-j38933-arm64-gcc-10-defconfig-arm64-chromebook-kgx6p) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Sep 8 13:10:51 UTC 2023
9998 13:29:19.975105 [ 0.000000] random: crng init done
9999 13:29:19.981570 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10000 13:29:19.984891 [ 0.000000] efi: UEFI not found.
10001 13:29:19.991819 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10002 13:29:19.998463 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10003 13:29:20.008350 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10004 13:29:20.018281 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10005 13:29:20.024759 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10006 13:29:20.031398 [ 0.000000] printk: bootconsole [mtk8250] enabled
10007 13:29:20.037799 [ 0.000000] NUMA: No NUMA configuration found
10008 13:29:20.044551 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10009 13:29:20.047833 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d4a00-0x13f7d6fff]
10010 13:29:20.051129 [ 0.000000] Zone ranges:
10011 13:29:20.057867 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10012 13:29:20.061176 [ 0.000000] DMA32 empty
10013 13:29:20.067969 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10014 13:29:20.071103 [ 0.000000] Movable zone start for each node
10015 13:29:20.074715 [ 0.000000] Early memory node ranges
10016 13:29:20.081012 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10017 13:29:20.087939 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10018 13:29:20.094144 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10019 13:29:20.100664 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10020 13:29:20.107350 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10021 13:29:20.113692 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10022 13:29:20.143773 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10023 13:29:20.150113 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10024 13:29:20.156391 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10025 13:29:20.160179 [ 0.000000] psci: probing for conduit method from DT.
10026 13:29:20.167034 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10027 13:29:20.169934 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10028 13:29:20.176462 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10029 13:29:20.179914 [ 0.000000] psci: SMC Calling Convention v1.2
10030 13:29:20.186441 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10031 13:29:20.189528 [ 0.000000] Detected VIPT I-cache on CPU0
10032 13:29:20.196479 [ 0.000000] CPU features: detected: GIC system register CPU interface
10033 13:29:20.203087 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10034 13:29:20.209469 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10035 13:29:20.216359 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10036 13:29:20.226013 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10037 13:29:20.232357 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10038 13:29:20.236357 [ 0.000000] alternatives: applying boot alternatives
10039 13:29:20.242142 [ 0.000000] Fallback order for Node 0: 0
10040 13:29:20.248829 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10041 13:29:20.252563 [ 0.000000] Policy zone: Normal
10042 13:29:20.265687 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10043 13:29:20.275640 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10044 13:29:20.286323 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10045 13:29:20.295862 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10046 13:29:20.302975 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10047 13:29:20.306052 <6>[ 0.000000] software IO TLB: area num 8.
10048 13:29:20.361650 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10049 13:29:20.441312 <6>[ 0.000000] Memory: 3834196K/4191232K available (17984K kernel code, 4098K rwdata, 17468K rodata, 8384K init, 616K bss, 324268K reserved, 32768K cma-reserved)
10050 13:29:20.447910 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10051 13:29:20.454753 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10052 13:29:20.458080 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10053 13:29:20.464659 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10054 13:29:20.470833 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10055 13:29:20.474302 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10056 13:29:20.484772 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10057 13:29:20.490940 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10058 13:29:20.497794 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10059 13:29:20.503999 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10060 13:29:20.507598 <6>[ 0.000000] GICv3: 608 SPIs implemented
10061 13:29:20.510859 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10062 13:29:20.517190 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10063 13:29:20.520836 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10064 13:29:20.527352 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10065 13:29:20.540808 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10066 13:29:20.553530 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10067 13:29:20.560413 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10068 13:29:20.568008 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10069 13:29:20.581487 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10070 13:29:20.588187 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10071 13:29:20.594689 <6>[ 0.009228] Console: colour dummy device 80x25
10072 13:29:20.604948 <6>[ 0.013954] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10073 13:29:20.608015 <6>[ 0.024396] pid_max: default: 32768 minimum: 301
10074 13:29:20.614988 <6>[ 0.029266] LSM: Security Framework initializing
10075 13:29:20.621353 <6>[ 0.034179] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10076 13:29:20.631473 <6>[ 0.041786] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10077 13:29:20.637958 <6>[ 0.051058] cblist_init_generic: Setting adjustable number of callback queues.
10078 13:29:20.644521 <6>[ 0.058502] cblist_init_generic: Setting shift to 3 and lim to 1.
10079 13:29:20.654601 <6>[ 0.064879] cblist_init_generic: Setting adjustable number of callback queues.
10080 13:29:20.657849 <6>[ 0.072351] cblist_init_generic: Setting shift to 3 and lim to 1.
10081 13:29:20.664567 <6>[ 0.078750] rcu: Hierarchical SRCU implementation.
10082 13:29:20.670679 <6>[ 0.083765] rcu: Max phase no-delay instances is 1000.
10083 13:29:20.677745 <6>[ 0.090787] EFI services will not be available.
10084 13:29:20.680643 <6>[ 0.095735] smp: Bringing up secondary CPUs ...
10085 13:29:20.688883 <6>[ 0.100780] Detected VIPT I-cache on CPU1
10086 13:29:20.695299 <6>[ 0.100850] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10087 13:29:20.702156 <6>[ 0.100881] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10088 13:29:20.705247 <6>[ 0.101209] Detected VIPT I-cache on CPU2
10089 13:29:20.715006 <6>[ 0.101257] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10090 13:29:20.721861 <6>[ 0.101272] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10091 13:29:20.724824 <6>[ 0.101527] Detected VIPT I-cache on CPU3
10092 13:29:20.731362 <6>[ 0.101573] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10093 13:29:20.738362 <6>[ 0.101586] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10094 13:29:20.741629 <6>[ 0.101886] CPU features: detected: Spectre-v4
10095 13:29:20.747857 <6>[ 0.101892] CPU features: detected: Spectre-BHB
10096 13:29:20.751515 <6>[ 0.101897] Detected PIPT I-cache on CPU4
10097 13:29:20.758481 <6>[ 0.101955] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10098 13:29:20.764489 <6>[ 0.101971] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10099 13:29:20.771131 <6>[ 0.102259] Detected PIPT I-cache on CPU5
10100 13:29:20.777698 <6>[ 0.102322] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10101 13:29:20.784672 <6>[ 0.102338] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10102 13:29:20.787844 <6>[ 0.102611] Detected PIPT I-cache on CPU6
10103 13:29:20.794017 <6>[ 0.102667] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10104 13:29:20.801106 <6>[ 0.102683] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10105 13:29:20.807394 <6>[ 0.102967] Detected PIPT I-cache on CPU7
10106 13:29:20.814048 <6>[ 0.103031] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10107 13:29:20.820857 <6>[ 0.103048] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10108 13:29:20.824025 <6>[ 0.103094] smp: Brought up 1 node, 8 CPUs
10109 13:29:20.830555 <6>[ 0.244334] SMP: Total of 8 processors activated.
10110 13:29:20.833929 <6>[ 0.249255] CPU features: detected: 32-bit EL0 Support
10111 13:29:20.843864 <6>[ 0.254617] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10112 13:29:20.850662 <6>[ 0.263472] CPU features: detected: Common not Private translations
10113 13:29:20.857177 <6>[ 0.269948] CPU features: detected: CRC32 instructions
10114 13:29:20.860614 <6>[ 0.275333] CPU features: detected: RCpc load-acquire (LDAPR)
10115 13:29:20.866957 <6>[ 0.281292] CPU features: detected: LSE atomic instructions
10116 13:29:20.873617 <6>[ 0.287074] CPU features: detected: Privileged Access Never
10117 13:29:20.880609 <6>[ 0.292853] CPU features: detected: RAS Extension Support
10118 13:29:20.886680 <6>[ 0.298497] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10119 13:29:20.890687 <6>[ 0.305715] CPU: All CPU(s) started at EL2
10120 13:29:20.896974 <6>[ 0.310059] alternatives: applying system-wide alternatives
10121 13:29:20.905402 <6>[ 0.319950] devtmpfs: initialized
10122 13:29:20.920424 <6>[ 0.328161] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10123 13:29:20.927119 <6>[ 0.338125] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10124 13:29:20.933656 <6>[ 0.346360] pinctrl core: initialized pinctrl subsystem
10125 13:29:20.936637 <6>[ 0.352992] DMI not present or invalid.
10126 13:29:20.943234 <6>[ 0.357397] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10127 13:29:20.953490 <6>[ 0.364254] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10128 13:29:20.959851 <6>[ 0.371703] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10129 13:29:20.969841 <6>[ 0.379793] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10130 13:29:20.973263 <6>[ 0.387949] audit: initializing netlink subsys (disabled)
10131 13:29:20.983476 <5>[ 0.393644] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10132 13:29:20.990133 <6>[ 0.394339] thermal_sys: Registered thermal governor 'step_wise'
10133 13:29:20.996300 <6>[ 0.401611] thermal_sys: Registered thermal governor 'power_allocator'
10134 13:29:20.999794 <6>[ 0.407868] cpuidle: using governor menu
10135 13:29:21.006492 <6>[ 0.418829] NET: Registered PF_QIPCRTR protocol family
10136 13:29:21.013216 <6>[ 0.424310] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10137 13:29:21.016130 <6>[ 0.431415] ASID allocator initialised with 32768 entries
10138 13:29:21.023534 <6>[ 0.437950] Serial: AMBA PL011 UART driver
10139 13:29:21.032026 <4>[ 0.446659] Trying to register duplicate clock ID: 134
10140 13:29:21.086419 <6>[ 0.504148] KASLR enabled
10141 13:29:21.100417 <6>[ 0.511842] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10142 13:29:21.107128 <6>[ 0.518856] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10143 13:29:21.114127 <6>[ 0.525345] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10144 13:29:21.120165 <6>[ 0.532348] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10145 13:29:21.127175 <6>[ 0.538835] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10146 13:29:21.133942 <6>[ 0.545839] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10147 13:29:21.140119 <6>[ 0.552325] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10148 13:29:21.146910 <6>[ 0.559333] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10149 13:29:21.149823 <6>[ 0.566835] ACPI: Interpreter disabled.
10150 13:29:21.158971 <6>[ 0.573257] iommu: Default domain type: Translated
10151 13:29:21.165123 <6>[ 0.578369] iommu: DMA domain TLB invalidation policy: strict mode
10152 13:29:21.168406 <5>[ 0.585022] SCSI subsystem initialized
10153 13:29:21.175138 <6>[ 0.589183] usbcore: registered new interface driver usbfs
10154 13:29:21.182091 <6>[ 0.594914] usbcore: registered new interface driver hub
10155 13:29:21.185413 <6>[ 0.600464] usbcore: registered new device driver usb
10156 13:29:21.192446 <6>[ 0.606564] pps_core: LinuxPPS API ver. 1 registered
10157 13:29:21.202567 <6>[ 0.611757] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10158 13:29:21.205201 <6>[ 0.621106] PTP clock support registered
10159 13:29:21.208438 <6>[ 0.625351] EDAC MC: Ver: 3.0.0
10160 13:29:21.216233 <6>[ 0.630499] FPGA manager framework
10161 13:29:21.222798 <6>[ 0.634178] Advanced Linux Sound Architecture Driver Initialized.
10162 13:29:21.226041 <6>[ 0.640950] vgaarb: loaded
10163 13:29:21.232874 <6>[ 0.644107] clocksource: Switched to clocksource arch_sys_counter
10164 13:29:21.235957 <5>[ 0.650539] VFS: Disk quotas dquot_6.6.0
10165 13:29:21.242398 <6>[ 0.654726] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10166 13:29:21.245835 <6>[ 0.661913] pnp: PnP ACPI: disabled
10167 13:29:21.253985 <6>[ 0.668585] NET: Registered PF_INET protocol family
10168 13:29:21.260730 <6>[ 0.673965] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10169 13:29:21.272900 <6>[ 0.683967] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10170 13:29:21.282666 <6>[ 0.692752] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10171 13:29:21.289039 <6>[ 0.700716] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10172 13:29:21.295954 <6>[ 0.709119] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10173 13:29:21.306937 <6>[ 0.717773] TCP: Hash tables configured (established 32768 bind 32768)
10174 13:29:21.312902 <6>[ 0.724631] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10175 13:29:21.319798 <6>[ 0.731652] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10176 13:29:21.326098 <6>[ 0.739168] NET: Registered PF_UNIX/PF_LOCAL protocol family
10177 13:29:21.333163 <6>[ 0.745312] RPC: Registered named UNIX socket transport module.
10178 13:29:21.336224 <6>[ 0.751463] RPC: Registered udp transport module.
10179 13:29:21.342759 <6>[ 0.756396] RPC: Registered tcp transport module.
10180 13:29:21.349219 <6>[ 0.761327] RPC: Registered tcp NFSv4.1 backchannel transport module.
10181 13:29:21.352727 <6>[ 0.767996] PCI: CLS 0 bytes, default 64
10182 13:29:21.356243 <6>[ 0.772288] Unpacking initramfs...
10183 13:29:21.385189 <6>[ 0.796703] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10184 13:29:21.395466 <6>[ 0.805374] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10185 13:29:21.398757 <6>[ 0.814220] kvm [1]: IPA Size Limit: 40 bits
10186 13:29:21.405149 <6>[ 0.818751] kvm [1]: GICv3: no GICV resource entry
10187 13:29:21.408641 <6>[ 0.823774] kvm [1]: disabling GICv2 emulation
10188 13:29:21.414915 <6>[ 0.828462] kvm [1]: GIC system register CPU interface enabled
10189 13:29:21.418294 <6>[ 0.834624] kvm [1]: vgic interrupt IRQ18
10190 13:29:21.425141 <6>[ 0.839001] kvm [1]: VHE mode initialized successfully
10191 13:29:21.431580 <5>[ 0.845479] Initialise system trusted keyrings
10192 13:29:21.438034 <6>[ 0.850280] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10193 13:29:21.445874 <6>[ 0.860307] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10194 13:29:21.453092 <5>[ 0.866712] NFS: Registering the id_resolver key type
10195 13:29:21.455944 <5>[ 0.872017] Key type id_resolver registered
10196 13:29:21.462442 <5>[ 0.876432] Key type id_legacy registered
10197 13:29:21.469028 <6>[ 0.880712] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10198 13:29:21.475607 <6>[ 0.887633] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10199 13:29:21.481850 <6>[ 0.895393] 9p: Installing v9fs 9p2000 file system support
10200 13:29:21.519584 <5>[ 0.933907] Key type asymmetric registered
10201 13:29:21.523360 <5>[ 0.938238] Asymmetric key parser 'x509' registered
10202 13:29:21.533368 <6>[ 0.943404] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10203 13:29:21.536106 <6>[ 0.951037] io scheduler mq-deadline registered
10204 13:29:21.539270 <6>[ 0.955801] io scheduler kyber registered
10205 13:29:21.557978 <6>[ 0.972946] EINJ: ACPI disabled.
10206 13:29:21.591029 <4>[ 0.998614] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10207 13:29:21.600435 <4>[ 1.009252] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10208 13:29:21.615407 <6>[ 1.030084] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10209 13:29:21.623703 <6>[ 1.038165] printk: console [ttyS0] disabled
10210 13:29:21.651552 <6>[ 1.062815] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10211 13:29:21.658534 <6>[ 1.072314] printk: console [ttyS0] enabled
10212 13:29:21.661770 <6>[ 1.072314] printk: console [ttyS0] enabled
10213 13:29:21.668020 <6>[ 1.081211] printk: bootconsole [mtk8250] disabled
10214 13:29:21.671551 <6>[ 1.081211] printk: bootconsole [mtk8250] disabled
10215 13:29:21.678479 <6>[ 1.092372] SuperH (H)SCI(F) driver initialized
10216 13:29:21.681467 <6>[ 1.097637] msm_serial: driver initialized
10217 13:29:21.695856 <6>[ 1.106644] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10218 13:29:21.705408 <6>[ 1.115190] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10219 13:29:21.712028 <6>[ 1.123734] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10220 13:29:21.722135 <6>[ 1.132363] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10221 13:29:21.731740 <6>[ 1.141070] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10222 13:29:21.738379 <6>[ 1.149795] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10223 13:29:21.748840 <6>[ 1.158335] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10224 13:29:21.755141 <6>[ 1.167142] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10225 13:29:21.764579 <6>[ 1.175686] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10226 13:29:21.776555 <6>[ 1.191290] loop: module loaded
10227 13:29:21.783292 <6>[ 1.197236] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10228 13:29:21.806744 <4>[ 1.220530] mtk-pmic-keys: Failed to locate of_node [id: -1]
10229 13:29:21.812839 <6>[ 1.227377] megasas: 07.719.03.00-rc1
10230 13:29:21.822660 <6>[ 1.237072] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10231 13:29:21.832931 <6>[ 1.247490] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10232 13:29:21.850113 <6>[ 1.264008] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10233 13:29:21.906295 <6>[ 1.314093] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10234 13:29:22.259491 <6>[ 1.673994] Freeing initrd memory: 20880K
10235 13:29:22.275231 <6>[ 1.689695] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10236 13:29:22.286304 <6>[ 1.700586] tun: Universal TUN/TAP device driver, 1.6
10237 13:29:22.289858 <6>[ 1.706642] thunder_xcv, ver 1.0
10238 13:29:22.292610 <6>[ 1.710151] thunder_bgx, ver 1.0
10239 13:29:22.295941 <6>[ 1.713646] nicpf, ver 1.0
10240 13:29:22.306682 <6>[ 1.717664] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10241 13:29:22.309633 <6>[ 1.725140] hns3: Copyright (c) 2017 Huawei Corporation.
10242 13:29:22.312972 <6>[ 1.730744] hclge is initializing
10243 13:29:22.320255 <6>[ 1.734319] e1000: Intel(R) PRO/1000 Network Driver
10244 13:29:22.326691 <6>[ 1.739449] e1000: Copyright (c) 1999-2006 Intel Corporation.
10245 13:29:22.330053 <6>[ 1.745463] e1000e: Intel(R) PRO/1000 Network Driver
10246 13:29:22.336531 <6>[ 1.750679] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10247 13:29:22.343041 <6>[ 1.756864] igb: Intel(R) Gigabit Ethernet Network Driver
10248 13:29:22.349626 <6>[ 1.762514] igb: Copyright (c) 2007-2014 Intel Corporation.
10249 13:29:22.356250 <6>[ 1.768369] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10250 13:29:22.362981 <6>[ 1.774887] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10251 13:29:22.366502 <6>[ 1.781348] sky2: driver version 1.30
10252 13:29:22.372959 <6>[ 1.786333] VFIO - User Level meta-driver version: 0.3
10253 13:29:22.380021 <6>[ 1.794585] usbcore: registered new interface driver usb-storage
10254 13:29:22.386497 <6>[ 1.801034] usbcore: registered new device driver onboard-usb-hub
10255 13:29:22.395363 <6>[ 1.810173] mt6397-rtc mt6359-rtc: registered as rtc0
10256 13:29:22.405389 <6>[ 1.815651] mt6397-rtc mt6359-rtc: setting system clock to 2023-09-08T13:29:21 UTC (1694179761)
10257 13:29:22.408685 <6>[ 1.825236] i2c_dev: i2c /dev entries driver
10258 13:29:22.425664 <6>[ 1.836881] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10259 13:29:22.445287 <6>[ 1.859833] cpu cpu0: EM: created perf domain
10260 13:29:22.448371 <6>[ 1.864747] cpu cpu4: EM: created perf domain
10261 13:29:22.455720 <6>[ 1.870266] sdhci: Secure Digital Host Controller Interface driver
10262 13:29:22.462292 <6>[ 1.876699] sdhci: Copyright(c) Pierre Ossman
10263 13:29:22.469164 <6>[ 1.881609] Synopsys Designware Multimedia Card Interface Driver
10264 13:29:22.476045 <6>[ 1.888198] sdhci-pltfm: SDHCI platform and OF driver helper
10265 13:29:22.479117 <6>[ 1.888242] mmc0: CQHCI version 5.10
10266 13:29:22.485815 <6>[ 1.898416] ledtrig-cpu: registered to indicate activity on CPUs
10267 13:29:22.492138 <6>[ 1.905404] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10268 13:29:22.499016 <6>[ 1.912437] usbcore: registered new interface driver usbhid
10269 13:29:22.502161 <6>[ 1.918259] usbhid: USB HID core driver
10270 13:29:22.508796 <6>[ 1.922460] spi_master spi0: will run message pump with realtime priority
10271 13:29:22.554917 <6>[ 1.962813] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10272 13:29:22.574825 <6>[ 1.979024] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10273 13:29:22.577979 <6>[ 1.992621] mmc0: Command Queue Engine enabled
10274 13:29:22.584913 <6>[ 1.994880] cros-ec-spi spi0.0: Chrome EC device registered
10275 13:29:22.591874 <6>[ 1.997366] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10276 13:29:22.594931 <6>[ 2.010586] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10277 13:29:22.605355 <6>[ 2.016881] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10278 13:29:22.612240 <6>[ 2.023356] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10279 13:29:22.618894 <6>[ 2.027166] NET: Registered PF_PACKET protocol family
10280 13:29:22.622373 <6>[ 2.033495] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10281 13:29:22.629329 <6>[ 2.037501] 9pnet: Installing 9P2000 support
10282 13:29:22.632602 <6>[ 2.043249] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10283 13:29:22.638886 <5>[ 2.047184] Key type dns_resolver registered
10284 13:29:22.642591 <6>[ 2.053021] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10285 13:29:22.649206 <6>[ 2.057426] registered taskstats version 1
10286 13:29:22.652112 <5>[ 2.067787] Loading compiled-in X.509 certificates
10287 13:29:22.681066 <4>[ 2.088920] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10288 13:29:22.690984 <4>[ 2.099609] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10289 13:29:22.697272 <3>[ 2.110135] debugfs: File 'uA_load' in directory '/' already present!
10290 13:29:22.704020 <3>[ 2.116834] debugfs: File 'min_uV' in directory '/' already present!
10291 13:29:22.710425 <3>[ 2.123441] debugfs: File 'max_uV' in directory '/' already present!
10292 13:29:22.717336 <3>[ 2.130104] debugfs: File 'constraint_flags' in directory '/' already present!
10293 13:29:22.727892 <3>[ 2.139270] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10294 13:29:22.739202 <6>[ 2.153710] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10295 13:29:22.746338 <6>[ 2.160572] xhci-mtk 11200000.usb: xHCI Host Controller
10296 13:29:22.752818 <6>[ 2.166090] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10297 13:29:22.762735 <6>[ 2.173933] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10298 13:29:22.769425 <6>[ 2.183368] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10299 13:29:22.775900 <6>[ 2.189437] xhci-mtk 11200000.usb: xHCI Host Controller
10300 13:29:22.782999 <6>[ 2.194917] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10301 13:29:22.789321 <6>[ 2.202562] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10302 13:29:22.795690 <6>[ 2.210228] hub 1-0:1.0: USB hub found
10303 13:29:22.799070 <6>[ 2.214235] hub 1-0:1.0: 1 port detected
10304 13:29:22.805885 <6>[ 2.218498] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10305 13:29:22.812127 <6>[ 2.227037] hub 2-0:1.0: USB hub found
10306 13:29:22.815754 <6>[ 2.231039] hub 2-0:1.0: 1 port detected
10307 13:29:22.823713 <6>[ 2.238553] mtk-msdc 11f70000.mmc: Got CD GPIO
10308 13:29:22.835329 <6>[ 2.246566] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10309 13:29:22.842134 <6>[ 2.254596] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10310 13:29:22.851919 <4>[ 2.262481] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10311 13:29:22.861883 <6>[ 2.272007] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10312 13:29:22.868498 <6>[ 2.280084] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10313 13:29:22.875546 <6>[ 2.288290] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10314 13:29:22.885256 <6>[ 2.296229] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10315 13:29:22.891809 <6>[ 2.304076] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10316 13:29:22.901610 <6>[ 2.311896] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10317 13:29:22.911273 <6>[ 2.322331] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10318 13:29:22.917948 <6>[ 2.330693] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10319 13:29:22.927756 <6>[ 2.339059] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10320 13:29:22.934662 <6>[ 2.347398] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10321 13:29:22.944515 <6>[ 2.355746] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10322 13:29:22.954608 <6>[ 2.364084] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10323 13:29:22.960820 <6>[ 2.372435] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10324 13:29:22.970737 <6>[ 2.380773] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10325 13:29:22.977444 <6>[ 2.389120] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10326 13:29:22.987483 <6>[ 2.397458] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10327 13:29:22.994018 <6>[ 2.405805] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10328 13:29:23.003943 <6>[ 2.414142] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10329 13:29:23.010439 <6>[ 2.422480] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10330 13:29:23.020603 <6>[ 2.430818] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10331 13:29:23.027024 <6>[ 2.439155] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10332 13:29:23.034107 <6>[ 2.447987] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10333 13:29:23.040557 <6>[ 2.455273] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10334 13:29:23.047166 <6>[ 2.462068] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10335 13:29:23.057295 <6>[ 2.468814] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10336 13:29:23.064535 <6>[ 2.475720] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10337 13:29:23.070686 <6>[ 2.482487] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10338 13:29:23.080877 <6>[ 2.491614] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10339 13:29:23.090720 <6>[ 2.500736] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10340 13:29:23.100178 <6>[ 2.510032] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10341 13:29:23.110267 <6>[ 2.519524] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10342 13:29:23.116877 <6>[ 2.528997] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10343 13:29:23.127107 <6>[ 2.538116] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10344 13:29:23.136695 <6>[ 2.547585] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10345 13:29:23.146809 <6>[ 2.556705] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10346 13:29:23.156357 <6>[ 2.566000] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10347 13:29:23.166272 <6>[ 2.576160] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10348 13:29:23.177030 <6>[ 2.587690] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10349 13:29:23.205347 <6>[ 2.616571] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10350 13:29:23.233505 <6>[ 2.647768] hub 2-1:1.0: USB hub found
10351 13:29:23.236319 <6>[ 2.652236] hub 2-1:1.0: 3 ports detected
10352 13:29:23.356915 <6>[ 2.768304] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10353 13:29:23.511873 <6>[ 2.926759] hub 1-1:1.0: USB hub found
10354 13:29:23.514914 <6>[ 2.931289] hub 1-1:1.0: 4 ports detected
10355 13:29:23.588937 <6>[ 3.000537] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10356 13:29:23.836774 <6>[ 3.248421] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10357 13:29:23.969728 <6>[ 3.384328] hub 1-1.4:1.0: USB hub found
10358 13:29:23.973093 <6>[ 3.388999] hub 1-1.4:1.0: 2 ports detected
10359 13:29:24.269004 <6>[ 3.680394] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10360 13:29:24.460715 <6>[ 3.872391] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10361 13:29:35.473640 <6>[ 14.893368] ALSA device list:
10362 13:29:35.480340 <6>[ 14.896664] No soundcards found.
10363 13:29:35.488580 <6>[ 14.904420] Freeing unused kernel memory: 8384K
10364 13:29:35.491781 <6>[ 14.909419] Run /init as init process
10365 13:29:35.525819 Starting syslogd: OK
10366 13:29:35.530233 Starting klogd: OK
10367 13:29:35.538988 Running sysctl: OK
10368 13:29:35.546143 Populating /dev using udev: <30>[ 14.962967] udevd[193]: starting version 3.2.9
10369 13:29:35.554788 <27>[ 14.971067] udevd[193]: specified user 'tss' unknown
10370 13:29:35.561944 <27>[ 14.976470] udevd[193]: specified group 'tss' unknown
10371 13:29:35.565118 <30>[ 14.982993] udevd[194]: starting eudev-3.2.9
10372 13:29:35.586661 <27>[ 15.003039] udevd[194]: specified user 'tss' unknown
10373 13:29:35.593284 <27>[ 15.008481] udevd[194]: specified group 'tss' unknown
10374 13:29:35.718368 <6>[ 15.131407] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10375 13:29:35.728382 <6>[ 15.140822] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10376 13:29:35.731692 <6>[ 15.145357] remoteproc remoteproc0: scp is available
10377 13:29:35.741614 <6>[ 15.148506] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10378 13:29:35.745390 <6>[ 15.154048] remoteproc remoteproc0: powering up scp
10379 13:29:35.754827 <6>[ 15.162406] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10380 13:29:35.765516 <6>[ 15.177211] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10381 13:29:35.768077 <6>[ 15.177501] mc: Linux media interface: v0.10
10382 13:29:35.774870 <6>[ 15.178782] usbcore: registered new interface driver r8152
10383 13:29:35.781300 <6>[ 15.185922] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10384 13:29:35.787968 <6>[ 15.196767] usbcore: registered new interface driver cdc_ether
10385 13:29:35.791355 <6>[ 15.206543] videodev: Linux video capture interface: v2.00
10386 13:29:35.800899 <3>[ 15.210073] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10387 13:29:35.812169 <3>[ 15.225085] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10388 13:29:35.818825 <6>[ 15.226219] usbcore: registered new interface driver r8153_ecm
10389 13:29:35.825310 <4>[ 15.232222] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10390 13:29:35.831951 <4>[ 15.232306] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10391 13:29:35.841823 <3>[ 15.244341] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10392 13:29:35.848246 <6>[ 15.250486] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10393 13:29:35.858459 <3>[ 15.259473] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10394 13:29:35.864733 <3>[ 15.278302] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10395 13:29:35.874867 <3>[ 15.286647] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10396 13:29:35.881226 <3>[ 15.294973] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10397 13:29:35.887793 <6>[ 15.297586] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10398 13:29:35.897884 <3>[ 15.303134] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10399 13:29:35.901142 <6>[ 15.310033] pci_bus 0000:00: root bus resource [bus 00-ff]
10400 13:29:35.911195 <3>[ 15.318122] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10401 13:29:35.917724 <6>[ 15.324236] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10402 13:29:35.924055 <6>[ 15.324449] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10403 13:29:35.934521 <6>[ 15.324455] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10404 13:29:35.940812 <6>[ 15.324494] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10405 13:29:35.947877 <6>[ 15.324508] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10406 13:29:35.954456 <6>[ 15.324576] pci 0000:00:00.0: supports D1 D2
10407 13:29:35.961111 <6>[ 15.324578] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10408 13:29:35.967307 <6>[ 15.325480] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10409 13:29:35.974215 <6>[ 15.325564] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10410 13:29:35.983610 <6>[ 15.325588] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10411 13:29:35.990751 <6>[ 15.325603] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10412 13:29:35.997677 <6>[ 15.325618] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10413 13:29:36.001067 <6>[ 15.325721] pci 0000:01:00.0: supports D1 D2
10414 13:29:36.008549 <6>[ 15.325722] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10415 13:29:36.017743 <3>[ 15.331961] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10416 13:29:36.024838 <6>[ 15.340240] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10417 13:29:36.030869 <6>[ 15.340999] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10418 13:29:36.037810 <6>[ 15.346169] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10419 13:29:36.047675 <6>[ 15.346469] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10420 13:29:36.057621 <3>[ 15.346691] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10421 13:29:36.064627 <3>[ 15.346703] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10422 13:29:36.074449 <3>[ 15.346778] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10423 13:29:36.080587 <3>[ 15.346785] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10424 13:29:36.090547 <3>[ 15.346788] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10425 13:29:36.097220 <3>[ 15.346792] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10426 13:29:36.103646 <3>[ 15.346794] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10427 13:29:36.113488 <3>[ 15.346814] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10428 13:29:36.119849 <6>[ 15.356203] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10429 13:29:36.129696 <6>[ 15.357156] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10430 13:29:36.140519 <6>[ 15.357374] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10431 13:29:36.149581 <4>[ 15.359713] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10432 13:29:36.156658 <4>[ 15.359723] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10433 13:29:36.162857 <6>[ 15.362400] remoteproc remoteproc0: remote processor scp is now up
10434 13:29:36.172864 <6>[ 15.370638] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10435 13:29:36.179693 <6>[ 15.374461] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10436 13:29:36.189558 <6>[ 15.374478] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10437 13:29:36.195999 <6>[ 15.374492] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10438 13:29:36.202445 <6>[ 15.374505] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10439 13:29:36.209052 <6>[ 15.374519] pci 0000:00:00.0: PCI bridge to [bus 01]
10440 13:29:36.212866 <6>[ 15.375106] Bluetooth: Core ver 2.22
10441 13:29:36.218990 <6>[ 15.375189] NET: Registered PF_BLUETOOTH protocol family
10442 13:29:36.225757 <6>[ 15.375193] Bluetooth: HCI device and connection manager initialized
10443 13:29:36.228678 <6>[ 15.375220] Bluetooth: HCI socket layer initialized
10444 13:29:36.235420 <6>[ 15.375227] Bluetooth: L2CAP socket layer initialized
10445 13:29:36.242120 <6>[ 15.375236] Bluetooth: SCO socket layer initialized
10446 13:29:36.249133 <6>[ 15.383184] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10447 13:29:36.255261 <6>[ 15.385537] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10448 13:29:36.265237 <6>[ 15.389916] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10449 13:29:36.271854 <4>[ 15.390027] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10450 13:29:36.278667 <4>[ 15.390027] Fallback method does not support PEC.
10451 13:29:36.288810 <6>[ 15.397618] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10452 13:29:36.295318 <6>[ 15.403720] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10453 13:29:36.301653 <6>[ 15.411205] usbcore: registered new interface driver uvcvideo
10454 13:29:36.308415 <6>[ 15.419266] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10455 13:29:36.315179 <6>[ 15.419829] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10456 13:29:36.325026 <3>[ 15.420217] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10457 13:29:36.328160 <6>[ 15.424485] usbcore: registered new interface driver btusb
10458 13:29:36.341312 <4>[ 15.425307] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10459 13:29:36.344773 <3>[ 15.425322] Bluetooth: hci0: Failed to load firmware file (-2)
10460 13:29:36.351497 <3>[ 15.425328] Bluetooth: hci0: Failed to set up firmware (-2)
10461 13:29:36.361212 <4>[ 15.425332] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10462 13:29:36.367762 <6>[ 15.430136] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10463 13:29:36.371053 <6>[ 15.789581] r8152 2-1.3:1.0 eth0: v1.12.13
10464 13:29:36.388062 <5>[ 15.800696] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10465 13:29:36.397871 <3>[ 15.801570] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10466 13:29:36.418327 <5>[ 15.831294] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10467 13:29:36.424926 <4>[ 15.838268] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10468 13:29:36.431643 <6>[ 15.847190] cfg80211: failed to load regulatory.db
10469 13:29:36.485640 <6>[ 15.898414] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10470 13:29:36.492574 <6>[ 15.905926] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10471 13:29:36.516121 <6>[ 15.932707] mt7921e 0000:01:00.0: ASIC revision: 79610010
10472 13:29:36.621990 <4>[ 16.031904] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10473 13:29:36.631132 done
10474 13:29:36.643066 Saving random seed: OK
10475 13:29:36.658211 Starting network: OK
10476 13:29:36.686455 Starting dropbear sshd: <6>[ 16.102434] NET: Registered PF_INET6 protocol family
10477 13:29:36.692886 <6>[ 16.108831] Segment Routing with IPv6
10478 13:29:36.695813 <6>[ 16.112821] In-situ OAM (IOAM) with IPv6
10479 13:29:36.699301 OK
10480 13:29:36.708457 /bin/sh: can't access tty; job control turned off
10481 13:29:36.708773 Matched prompt #10: / #
10483 13:29:36.708961 Setting prompt string to ['/ #']
10484 13:29:36.709042 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10486 13:29:36.709209 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10487 13:29:36.709278 start: 2.2.6 expect-shell-connection (timeout 00:03:45) [common]
10488 13:29:36.709338 Setting prompt string to ['/ #']
10489 13:29:36.709388 Forcing a shell prompt, looking for ['/ #']
10491 13:29:36.759574 / #
10492 13:29:36.759758 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10493 13:29:36.759853 Waiting using forced prompt support (timeout 00:02:30)
10494 13:29:36.759968 <4>[ 16.150688] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10495 13:29:36.764961
10496 13:29:36.765243 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10497 13:29:36.765330 start: 2.2.7 export-device-env (timeout 00:03:45) [common]
10498 13:29:36.765423 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10499 13:29:36.765498 end: 2.2 depthcharge-retry (duration 00:01:15) [common]
10500 13:29:36.765569 end: 2 depthcharge-action (duration 00:01:15) [common]
10501 13:29:36.765652 start: 3 lava-test-retry (timeout 00:01:00) [common]
10502 13:29:36.765722 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10503 13:29:36.765785 Using namespace: common
10505 13:29:36.866095 / # #
10506 13:29:36.866271 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10507 13:29:36.866382 #<4>[ 16.270648] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10508 13:29:36.871591
10509 13:29:36.871858 Using /lava-11471184
10511 13:29:36.972170 / # export SHELL=/bin/sh
10512 13:29:37.016387 export SHELL=/bin/sh<4>[ 16.390729] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10513 13:29:37.016514
10515 13:29:37.117020 / # . /lava-11471184/environment
10516 13:29:37.117217 . /lava-11471184/environment<4>[ 16.510626] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10517 13:29:37.122054
10519 13:29:37.222548 / # /lava-11471184/bin/lava-test-runner /lava-11471184/0
10520 13:29:37.222701 Test shell timeout: 10s (minimum of the action and connection timeout)
10521 13:29:37.223013 /lava-11471184/bin/lava-test-runner /lava-11471184/0<4>[ 16.630284] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10522 13:29:37.227906
10523 13:29:37.268425 + export 'TESTRUN_ID=0_dmesg'
10524 13:29:37.268514 +<8>[ 16.674047] <LAVA_SIGNAL_STARTRUN 0_dmesg 11471184_1.5.2.3.1>
10525 13:29:37.268570 cd /lava-11471184/0/tests/0_dmesg
10526 13:29:37.268625 + cat uuid
10527 13:29:37.268674 + UUID=11471184_1.5.2.3.1
10528 13:29:37.268721 + set +x
10529 13:29:37.268942 Received signal: <STARTRUN> 0_dmesg 11471184_1.5.2.3.1
10530 13:29:37.269005 Starting test lava.0_dmesg (11471184_1.5.2.3.1)
10531 13:29:37.269076 Skipping test definition patterns.
10532 13:29:37.272867 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10533 13:29:37.279324 <8>[ 16.692542] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10534 13:29:37.279570 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10536 13:29:37.302405 <8>[ 16.715604] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10537 13:29:37.302660 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10539 13:29:37.323107 <8>[ 16.736178] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10540 13:29:37.323369 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10542 13:29:37.327811 + set +x
10543 13:29:37.330812 Received signal: <ENDRUN> 0_dmesg 11471184_1.5.2.3.1
10544 13:29:37.330914 Ending use of test pattern.
10545 13:29:37.330978 Ending test lava.0_dmesg (11471184_1.5.2.3.1), duration 0.06
10547 13:29:37.334410 <8>[ 16.747382] <LAVA_SIGNAL_ENDRUN 0_dmesg 11471184_1.5.2.3.1>
10548 13:29:37.343996 <4>[ 16.750603] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10549 13:29:37.347282 <LAVA_TEST_RUNNER EXIT>
10550 13:29:37.347527 ok: lava_test_shell seems to have completed
10551 13:29:37.347618 alert: pass
crit: pass
emerg: pass
10552 13:29:37.347692 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10553 13:29:37.347763 end: 3 lava-test-retry (duration 00:00:01) [common]
10554 13:29:37.347832 start: 4 lava-test-retry (timeout 00:01:00) [common]
10555 13:29:37.347898 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10556 13:29:37.347949 Using namespace: common
10558 13:29:37.448270 / # #
10559 13:29:37.448443 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10560 13:29:37.448551 Using /lava-11471184
10562 13:29:37.548875 export SHELL=/bin/sh
10563 13:29:37.549083 #
10564 13:29:37.549157 / # <4>[ 16.874966] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10566 13:29:37.649647 export SHELL=/bin/sh. /lava-11471184/environment
10567 13:29:37.649854
10568 13:29:37.649940 / # <4>[ 16.994561] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10570 13:29:37.750496 . /lava-11471184/environment/lava-11471184/bin/lava-test-runner /lava-11471184/1
10571 13:29:37.750647 Test shell timeout: 10s (minimum of the action and connection timeout)
10572 13:29:37.750775
10573 13:29:37.750834 / # <4>[ 17.110466] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10574 13:29:37.755797 /lava-11471184/bin/lava-test-runner /lava-11471184/1
10575 13:29:37.796488 + export 'TESTRU<8>[ 17.194589] <LAVA_SIGNAL_STARTRUN 1_bootrr 11471184_1.5.2.3.5>
10576 13:29:37.796638 N_ID=1_bootrr'
10577 13:29:37.796706 + cd /lava-11471184/1/tests/1_bootrr
10578 13:29:37.796761 + cat uuid
10579 13:29:37.796814 + UUID=11471184_1.5.2.3.5
10580 13:29:37.796865 + set +x
10581 13:29:37.797101 Received signal: <STARTRUN> 1_bootrr 11471184_1.5.2.3.5
10582 13:29:37.797168 Starting test lava.1_bootrr (11471184_1.5.2.3.5)
10583 13:29:37.797244 Skipping test definition patterns.
10584 13:29:37.803245 + export 'PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-11471184/1/../bin<8>[ 17.215460] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10585 13:29:37.803524 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10587 13:29:37.806314 :/sbin:/usr/sbin:/bin:/usr/bin'
10588 13:29:37.812872 + cd /opt/bootrr/libexec/bootrr<3>[ 17.227993] mt7921e 0000:01:00.0: hardware init failed
10589 13:29:37.812958
10590 13:29:37.816517 + sh helpers/bootrr-auto
10591 13:29:37.819635 /lava-11471184/1/../bin/lava-test-case
10592 13:29:37.823009 /lava-11471184/1/../bin/lava-test-case
10593 13:29:37.833015 <8>[ 17.244962] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10594 13:29:37.833311 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10596 13:29:37.836970 /usr/bin/tpm2_getcap
10597 13:29:37.866278 /lava-11471184/1/../bin/lava-test-case
10598 13:29:37.873002 <8>[ 17.287922] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
10599 13:29:37.873293 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10601 13:29:37.896516 /lava-11471184/1/../bin/lava-tes<8>[ 17.308885] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10602 13:29:37.896657 t-case
10603 13:29:37.896900 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10605 13:29:37.908409 /lava-11471184/1/../bin/lava-test-case
10606 13:29:37.914800 <8>[ 17.328477] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10607 13:29:37.915071 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10609 13:29:37.925033 /lava-11471184/1/../bin/lava-test-case
10610 13:29:37.931464 <8>[ 17.345516] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10611 13:29:37.931731 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10613 13:29:37.943951 /lava-11471184/1/../bin/lava-test-case
10614 13:29:37.950917 <8>[ 17.363361] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10615 13:29:37.951179 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10617 13:29:37.962315 /lava-11471184/1/../bin/lava-test-case
10618 13:29:37.969424 <8>[ 17.382198] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10619 13:29:37.969695 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10621 13:29:37.978978 /lava-11471184/1/../bin/lava-test-case
10622 13:29:37.985375 <8>[ 17.398277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10623 13:29:37.985680 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10625 13:29:38.004081 /lava-11471184/1/../bin/lava-tes<8>[ 17.416631] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10626 13:29:38.004214 t-case
10627 13:29:38.004451 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10629 13:29:38.012457 /lava-11471184/1/../bin/lava-test-case
10630 13:29:38.019180 <8>[ 17.432008] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10631 13:29:38.019448 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10633 13:29:38.038533 /lava-11471184/1/../bin/lava-tes<8>[ 17.450394] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10634 13:29:38.038665 t-case
10635 13:29:38.038894 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10637 13:29:38.055221 /lava-11471184/1/../bin/lava-tes<8>[ 17.467626] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10638 13:29:38.055364 t-case
10639 13:29:38.055609 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10641 13:29:38.071171 /lava-11471184/1/../bin/lava-test-case
10642 13:29:38.077580 <8>[ 17.490320] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10643 13:29:38.077888 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10645 13:29:38.087513 /lava-11471184/1/../bin/lava-test-case
10646 13:29:38.093898 <8>[ 17.507344] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10647 13:29:38.094172 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10649 13:29:38.104308 /lava-11471184/1/../bin/lava-test-case
10650 13:29:38.110376 <8>[ 17.523772] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
10651 13:29:38.110669 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10653 13:29:38.121310 /lava-11471184/1/../bin/lava-test-case
10654 13:29:38.127395 <8>[ 17.540540] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
10655 13:29:38.127640 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10657 13:29:38.136136 /lava-11471184/1/../bin/lava-test-case
10658 13:29:38.142797 <8>[ 17.556464] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
10659 13:29:38.143084 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10661 13:29:38.153302 /lava-11471184/1/../bin/lava-test-case
10662 13:29:38.160058 <8>[ 17.573082] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
10663 13:29:38.160299 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10665 13:29:38.169141 /lava-11471184/1/../bin/lava-test-case
10666 13:29:38.175531 <8>[ 17.588949] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
10667 13:29:38.175789 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10669 13:29:38.185595 /lava-11471184/1/../bin/lava-test-case
10670 13:29:38.191821 <8>[ 17.605185] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
10671 13:29:38.192100 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10673 13:29:38.199377 /lava-11471184/1/../bin/lava-test-case
10674 13:29:38.205761 <8>[ 17.620475] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
10675 13:29:38.206024 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10677 13:29:38.218935 /lava-11471184/1/../bin/lava-test-case
10678 13:29:38.225067 <8>[ 17.638077] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
10679 13:29:38.225328 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10681 13:29:38.240620 /lava-11471184/1/../bin/lava-tes<8>[ 17.652064] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
10682 13:29:38.240830 t-case
10683 13:29:38.241062 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10685 13:29:38.261389 /lava-11471184/1/../bin/lava-tes<8>[ 17.673963] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
10686 13:29:38.261528 t-case
10687 13:29:38.261771 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
10689 13:29:38.273005 /lava-11471184/1/../bin/lava-test-case
10690 13:29:38.279756 <8>[ 17.693869] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
10691 13:29:38.280019 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
10693 13:29:38.295413 /lava-11471184/1/../bin/lava-tes<8>[ 17.707720] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
10694 13:29:38.295537 t-case
10695 13:29:38.295781 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
10697 13:29:38.309007 /lava-11471184/1/../bin/lava-test-case
10698 13:29:38.315245 <8>[ 17.728048] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
10699 13:29:38.315521 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
10701 13:29:38.323034 /lava-11471184/1/../bin/lava-test-case
10702 13:29:38.329463 <8>[ 17.743605] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
10703 13:29:38.329729 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
10705 13:29:38.341565 /lava-11471184/1/../bin/lava-test-case
10706 13:29:38.348965 <8>[ 17.761566] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
10707 13:29:38.349232 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
10709 13:29:38.359619 /lava-11471184/1/../bin/lava-test-case
10710 13:29:38.366257 <8>[ 17.780528] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
10711 13:29:38.366535 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
10713 13:29:38.379234 /lava-11471184/1/../bin/lava-test-case
10714 13:29:38.386253 <8>[ 17.799131] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
10715 13:29:38.386527 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
10717 13:29:38.395732 /lava-11471184/1/../bin/lava-test-case
10718 13:29:38.402551 <8>[ 17.816667] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
10719 13:29:38.402818 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
10721 13:29:38.413595 /lava-11471184/1/../bin/lava-test-case
10722 13:29:38.420090 <8>[ 17.833258] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
10723 13:29:38.420378 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
10725 13:29:38.430348 /lava-11471184/1/../bin/lava-test-case
10726 13:29:38.437269 <8>[ 17.851995] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
10727 13:29:38.437558 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
10729 13:29:38.448370 /lava-11471184/1/../bin/lava-test-case
10730 13:29:38.454785 <8>[ 17.868731] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
10731 13:29:38.455048 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
10733 13:29:38.463113 /lava-11471184/1/../bin/lava-test-case
10734 13:29:38.470174 <8>[ 17.883388] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
10735 13:29:38.470433 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
10737 13:29:38.481355 /lava-11471184/1/../bin/lava-test-case
10738 13:29:38.488028 <8>[ 17.901109] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
10739 13:29:38.488293 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
10741 13:29:38.502666 /lava-11471184/1/../bin/lava-tes<8>[ 17.914976] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
10742 13:29:38.502796 t-case
10743 13:29:38.503025 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
10745 13:29:38.514025 /lava-11471184/1/../bin/lava-test-case
10746 13:29:38.520597 <8>[ 17.933513] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
10747 13:29:38.520857 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
10749 13:29:38.529782 /lava-11471184/1/../bin/lava-test-case
10750 13:29:38.536102 <8>[ 17.949878] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
10751 13:29:38.536375 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
10753 13:29:38.554868 /lava-11471184/1/../bin/lava-tes<8>[ 17.967346] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
10754 13:29:38.555008 t-case
10755 13:29:38.555243 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
10757 13:29:38.562260 /lava-11471184/1/../bin/lava-test-case
10758 13:29:38.572251 <8>[ 17.983702] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
10759 13:29:38.572539 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
10761 13:29:38.582201 /lava-11471184/1/../bin/lava-test-case
10762 13:29:38.589273 <8>[ 18.001949] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
10763 13:29:38.589528 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
10765 13:29:38.603818 /lava-11471184/1/../bin/lava-tes<8>[ 18.016332] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
10766 13:29:38.603957 t-case
10767 13:29:38.604187 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
10769 13:29:38.623500 /lava-11471184/1/../bin/lava-tes<8>[ 18.035824] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
10770 13:29:38.623642 t-case
10771 13:29:38.623876 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
10773 13:29:38.630534 /lava-11471184/1/../bin/lava-test-case
10774 13:29:38.637538 <8>[ 18.050706] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
10775 13:29:38.637792 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
10777 13:29:38.649243 /lava-11471184/1/../bin/lava-test-case
10778 13:29:38.655872 <8>[ 18.069071] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
10779 13:29:38.656153 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
10781 13:29:38.669756 /lava-11471184/1/../bin/lava-tes<8>[ 18.082348] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
10782 13:29:38.669860 t-case
10783 13:29:38.670083 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
10785 13:29:38.689503 /lava-11471184/1/../bin/lava-tes<8>[ 18.101439] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
10786 13:29:38.689615 t-case
10787 13:29:38.689838 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
10789 13:29:38.697817 /lava-11471184/1/../bin/lava-test-case
10790 13:29:38.704420 <8>[ 18.118358] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
10791 13:29:38.704713 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
10793 13:29:38.713096 /lava-11471184/1/../bin/lava-test-case
10794 13:29:38.719846 <8>[ 18.133406] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
10795 13:29:38.720122 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
10797 13:29:38.737844 /lava-11471184/1/../bin/lava-tes<8>[ 18.150449] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
10798 13:29:38.737968 t-case
10799 13:29:38.738192 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
10801 13:29:38.754241 /lava-11471184/1/../bin/lava-tes<8>[ 18.166453] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
10802 13:29:38.754378 t-case
10803 13:29:38.754617 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
10805 13:29:38.762995 /lava-11471184/1/../bin/lava-test-case
10806 13:29:38.769562 <8>[ 18.183073] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
10807 13:29:38.769838 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
10809 13:29:38.780192 /lava-11471184/1/../bin/lava-test-case
10810 13:29:38.786659 <8>[ 18.199674] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
10811 13:29:38.786921 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
10813 13:29:38.796597 /lava-11471184/1/../bin/lava-test-case
10814 13:29:38.803236 <8>[ 18.215862] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
10815 13:29:38.803528 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
10817 13:29:38.820619 /lava-11471184/1/../bin/lava-tes<8>[ 18.232734] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
10818 13:29:38.820744 t-case
10819 13:29:38.820974 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
10821 13:29:38.837470 /lava-11471184/1/../bin/lava-tes<8>[ 18.249963] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
10822 13:29:38.837597 t-case
10823 13:29:38.837826 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
10825 13:29:38.853748 /lava-11471184/1/../bin/lava-tes<8>[ 18.266491] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
10826 13:29:38.853881 t-case
10827 13:29:38.854117 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
10829 13:29:38.862818 /lava-11471184/1/../bin/lava-test-case
10830 13:29:38.869101 <8>[ 18.282577] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
10831 13:29:38.869364 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
10833 13:29:38.880223 /lava-11471184/1/../bin/lava-test-case
10834 13:29:38.886535 <8>[ 18.300447] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
10835 13:29:38.886812 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
10837 13:29:38.901367 /lava-11471184/1/../bin/lava-tes<8>[ 18.313859] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
10838 13:29:38.901495 t-case
10839 13:29:38.901729 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
10841 13:29:38.911243 /lava-11471184/1/../bin/lava-test-case
10842 13:29:38.917057 <8>[ 18.331240] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
10843 13:29:38.917311 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
10845 13:29:38.932368 /lava-11471184/1/../bin/lava-tes<8>[ 18.344700] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
10846 13:29:38.932501 t-case
10847 13:29:38.932755 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
10849 13:29:38.942756 /lava-11471184/1/../bin/lava-test-case
10850 13:29:38.949347 <8>[ 18.362746] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
10851 13:29:38.949630 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
10853 13:29:38.960993 /lava-11471184/1/../bin/lava-test-case
10854 13:29:38.967433 <8>[ 18.381197] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
10855 13:29:38.967699 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
10857 13:29:38.977813 /lava-11471184/1/../bin/lava-test-case
10858 13:29:38.984621 <8>[ 18.397814] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
10859 13:29:38.984908 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
10861 13:29:38.994148 /lava-11471184/1/../bin/lava-test-case
10862 13:29:39.000143 <8>[ 18.414179] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
10863 13:29:39.000412 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
10865 13:29:39.011195 /lava-11471184/1/../bin/lava-test-case
10866 13:29:39.017956 <8>[ 18.431764] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
10867 13:29:39.018219 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
10869 13:29:39.027714 /lava-11471184/1/../bin/lava-test-case
10870 13:29:39.034427 <8>[ 18.447674] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
10871 13:29:39.034699 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
10873 13:29:39.053689 /lava-11471184/1/../bin/lava-tes<8>[ 18.466215] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
10874 13:29:39.053825 t-case
10875 13:29:39.054065 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
10877 13:29:39.064779 /lava-11471184/1/../bin/lava-test-case
10878 13:29:39.071035 <8>[ 18.485014] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
10879 13:29:39.071302 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
10881 13:29:39.082174 /lava-11471184/1/../bin/lava-test-case
10882 13:29:39.088822 <8>[ 18.501911] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
10883 13:29:39.089093 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
10885 13:29:39.098248 /lava-11471184/1/../bin/lava-test-case
10886 13:29:39.104801 <8>[ 18.518538] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
10887 13:29:39.105076 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
10889 13:29:39.125455 /lava-11471184/1/../bin/lava-tes<8>[ 18.537872] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
10890 13:29:39.125591 t-case
10891 13:29:39.125837 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
10893 13:29:39.136069 /lava-11471184/1/../bin/lava-test-case
10894 13:29:39.142394 <8>[ 18.557536] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
10895 13:29:39.142690 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
10897 13:29:39.153776 /lava-11471184/1/../bin/lava-test-case
10898 13:29:39.159982 <8>[ 18.574188] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
10899 13:29:39.160306 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
10901 13:29:39.170443 /lava-11471184/1/../bin/lava-test-case
10902 13:29:39.177368 <8>[ 18.591029] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
10903 13:29:39.177666 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
10905 13:29:39.186907 /lava-11471184/1/../bin/lava-test-case
10906 13:29:39.193586 <8>[ 18.606823] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
10907 13:29:39.193957 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
10909 13:29:39.202698 /lava-11471184/1/../bin/lava-test-case
10910 13:29:39.209670 <8>[ 18.623341] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
10911 13:29:39.209969 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
10913 13:29:39.219651 /lava-11471184/1/../bin/lava-test-case
10914 13:29:39.225889 <8>[ 18.639203] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
10915 13:29:39.226159 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
10917 13:29:39.241208 /lava-11471184/1/../bin/lava-tes<8>[ 18.653867] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
10918 13:29:39.241341 t-case
10919 13:29:39.241566 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
10921 13:29:39.249882 /lava-11471184/1/../bin/lava-test-case
10922 13:29:39.256424 <8>[ 18.669842] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
10923 13:29:39.256705 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
10925 13:29:39.271857 /lava-11471184/1/../bin/lava-tes<8>[ 18.684019] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
10926 13:29:39.271974 t-case
10927 13:29:39.272196 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
10929 13:29:39.283670 /lava-11471184/1/../bin/lava-test-case
10930 13:29:39.290277 <8>[ 18.704521] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
10931 13:29:39.290550 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
10933 13:29:39.298743 /lava-11471184/1/../bin/lava-test-case
10934 13:29:39.305675 <8>[ 18.718990] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
10935 13:29:39.305945 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
10937 13:29:39.323663 /lava-11471184/1/../bin/lava-tes<8>[ 18.736215] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
10938 13:29:39.323796 t-case
10939 13:29:39.324019 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
10941 13:29:39.339032 /lava-11471184/1/../bin/lava-tes<8>[ 18.751355] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
10942 13:29:39.339157 t-case
10943 13:29:39.339400 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
10945 13:29:39.349772 /lava-11471184/1/../bin/lava-test-case
10946 13:29:39.356042 <8>[ 18.769070] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
10947 13:29:39.356298 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
10949 13:29:39.364013 /lava-11471184/1/../bin/lava-test-case
10950 13:29:39.370730 <8>[ 18.784958] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
10951 13:29:39.370983 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
10953 13:29:39.389348 /lava-11471184/1/../bin/lava-tes<8>[ 18.802176] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
10954 13:29:39.389490 t-case
10955 13:29:39.389745 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
10957 13:29:39.405626 /lava-11471184/1/../bin/lava-tes<8>[ 18.818571] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
10958 13:29:39.405769 t-case
10959 13:29:39.405991 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
10961 13:29:39.423597 /lava-11471184/1/../bin/lava-tes<8>[ 18.835556] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
10962 13:29:39.423722 t-case
10963 13:29:39.423945 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
10965 13:29:39.439302 /lava-11471184/1/../bin/lava-tes<8>[ 18.852004] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
10966 13:29:39.439436 t-case
10967 13:29:39.439658 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
10969 13:29:39.448749 /lava-11471184/1/../bin/lava-test-case
10970 13:29:39.455305 <8>[ 18.870170] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
10971 13:29:39.455583 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
10973 13:29:39.468413 /lava-11471184/1/../bin/lava-test-case
10974 13:29:39.474916 <8>[ 18.888768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
10975 13:29:39.475179 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
10977 13:29:39.485196 /lava-11471184/1/../bin/lava-test-case
10978 13:29:39.491751 <8>[ 18.904765] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
10979 13:29:39.492028 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
10981 13:29:39.501324 /lava-11471184/1/../bin/lava-test-case
10982 13:29:39.507893 <8>[ 18.922508] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
10983 13:29:39.508162 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
10985 13:29:39.518880 /lava-11471184/1/../bin/lava-test-case
10986 13:29:39.524817 <8>[ 18.937592] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
10987 13:29:39.525084 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
10989 13:29:40.539740 /lava-11471184/1/../bin/lava-test-case
10990 13:29:40.546096 <8>[ 19.959420] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
10991 13:29:40.546418 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
10993 13:29:40.556703 /lava-11471184/1/../bin/lava-test-case
10994 13:29:40.562977 <8>[ 19.977567] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
10995 13:29:40.563272 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
10997 13:29:41.579096 /lava-11471184/1/../bin/lava-test-case
10998 13:29:41.585358 <8>[ 20.998526] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
10999 13:29:41.585647 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11001 13:29:41.595661 /lava-11471184/1/../bin/lava-test-case
11002 13:29:41.602019 <8>[ 21.015637] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11003 13:29:41.602351 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11005 13:29:42.616043 /lava-11471184/1/../bin/lava-test-case
11006 13:29:42.622919 <8>[ 22.036838] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11007 13:29:42.623219 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11009 13:29:42.631850 /lava-11471184/1/../bin/lava-test-case
11010 13:29:42.638268 <8>[ 22.051706] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11011 13:29:42.638520 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11013 13:29:43.651298 /lava-11471184/1/../bin/lava-test-case
11014 13:29:43.658204 <8>[ 23.071575] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11015 13:29:43.658503 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11017 13:29:43.667831 /lava-11471184/1/../bin/lava-test-case
11018 13:29:43.674316 <8>[ 23.088291] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11019 13:29:43.674579 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11021 13:29:44.686680 /lava-11471184/1/../bin/lava-test-case
11022 13:29:44.693275 <8>[ 24.108685] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11023 13:29:44.693557 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11025 13:29:44.704429 /lava-11471184/1/../bin/lava-test-case
11026 13:29:44.710779 <8>[ 24.124973] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11027 13:29:44.711031 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11029 13:29:45.726073 /lava-11471184/1/../bin/lava-test-case
11030 13:29:45.732032 <8>[ 25.147560] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11031 13:29:45.732754 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11033 13:29:45.750258 /lava-11471184/1/../bin/lava-tes<8>[ 25.162282] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11034 13:29:45.750748 t-case
11035 13:29:45.751290 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11037 13:29:46.762667 /lava-11471184/1/../bin/lava-test-case
11038 13:29:46.769364 <8>[ 26.183659] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11039 13:29:46.770074 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11041 13:29:46.786391 /lava-11471184/1/../bin/lava-tes<8>[ 26.199393] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11042 13:29:46.786883 t-case
11043 13:29:46.787424 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11045 13:29:46.795660 /lava-11471184/1/../bin/lava-test-case
11046 13:29:46.802900 <8>[ 26.216415] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11047 13:29:46.803578 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11049 13:29:47.816607 /lava-11471184/1/../bin/lava-test-case
11050 13:29:47.823017 <8>[ 27.236739] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11051 13:29:47.823761 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11053 13:29:47.843450 /lava-11471184/1/../bin/lava-tes<8>[ 27.256495] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11054 13:29:47.843945 t-case
11055 13:29:47.844473 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11057 13:29:47.854192 /lava-11471184/1/../bin/lava-test-case
11058 13:29:47.861046 <8>[ 27.276941] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11059 13:29:47.861827 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11061 13:29:47.871847 /lava-11471184/1/../bin/lava-test-case
11062 13:29:47.878232 <8>[ 27.292832] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11063 13:29:47.878931 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11065 13:29:47.897748 /lava-11471184/1/../bin/lava-tes<8>[ 27.310555] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11066 13:29:47.898281 t-case
11067 13:29:47.898816 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11069 13:29:47.908536 /lava-11471184/1/../bin/lava-test-case
11070 13:29:47.915216 <8>[ 27.329794] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11071 13:29:47.916013 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11073 13:29:47.929346 /lava-11471184/1/../bin/lava-test-case
11074 13:29:47.935536 <8>[ 27.349229] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11075 13:29:47.936249 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11077 13:29:47.943867 /lava-11471184/1/../bin/lava-test-case
11078 13:29:47.950216 <8>[ 27.364356] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11079 13:29:47.950958 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11081 13:29:47.969743 /lava-11471184/1/../bin/lava-tes<8>[ 27.383124] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11082 13:29:47.970213 t-case
11083 13:29:47.970841 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11085 13:29:47.985985 /lava-11471184/1/../bin/lava-tes<8>[ 27.399044] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11086 13:29:47.986578 t-case
11087 13:29:47.987123 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11089 13:29:47.993595 /lava-11471184/1/../bin/lava-test-case
11090 13:29:48.003529 <8>[ 27.416350] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11091 13:29:48.004302 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11093 13:29:48.014144 /lava-11471184/1/../bin/lava-test-case
11094 13:29:48.020408 <8>[ 27.434179] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11095 13:29:48.021080 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11097 13:29:48.035715 /lava-11471184/1/../bin/lava-tes<8>[ 27.448247] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11098 13:29:48.036210 t-case
11099 13:29:48.036779 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11101 13:29:48.053141 /lava-11471184/1/../bin/lava-tes<8>[ 27.465770] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11102 13:29:48.053632 t-case
11103 13:29:48.054159 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11105 13:29:48.061520 /lava-11471184/1/../bin/lava-test-case
11106 13:29:48.067825 <8>[ 27.481682] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11107 13:29:48.068603 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11109 13:29:48.085609 /lava-11471184/1/../bin/lava-tes<8>[ 27.498631] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11110 13:29:48.086084 t-case
11111 13:29:48.086596 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11113 13:29:48.101517 /lava-11471184/1/../bin/lava-tes<8>[ 27.514360] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11114 13:29:48.101991 t-case
11115 13:29:48.102508 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11117 13:29:48.121588 /lava-11471184/1/../bin/lava-tes<8>[ 27.534670] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11118 13:29:48.122054 t-case
11119 13:29:48.122563 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11121 13:29:48.129087 /lava-11471184/1/../bin/lava-test-case
11122 13:29:48.135947 <8>[ 27.549325] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11123 13:29:48.136722 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11125 13:29:48.149030 /lava-11471184/1/../bin/lava-test-case
11126 13:29:48.155824 <8>[ 27.569150] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11127 13:29:48.156627 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11129 13:29:48.165222 /lava-11471184/1/../bin/lava-test-case
11130 13:29:48.171661 <8>[ 27.585631] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11131 13:29:48.172600 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11133 13:29:49.188457 /lava-11471184/1/../bin/lava-test-case
11134 13:29:49.191329 <8>[ 28.606447] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11135 13:29:49.191972 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11137 13:29:50.204956 /lava-11471184/1/../bin/lava-test-case
11138 13:29:50.211478 <8>[ 29.626846] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11139 13:29:50.212218 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11141 13:29:50.220487 /lava-11471184/1/../bin/lava-test-case
11142 13:29:50.227009 <8>[ 29.640979] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11143 13:29:50.227747 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11145 13:29:50.247755 /lava-11471184/1/../bin/lava-tes<8>[ 29.660997] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11146 13:29:50.248238 t-case
11147 13:29:50.248828 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11149 13:29:50.256923 /lava-11471184/1/../bin/lava-test-case
11150 13:29:50.263357 <8>[ 29.677935] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11151 13:29:50.264155 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11153 13:29:50.275512 /lava-11471184/1/../bin/lava-test-case
11154 13:29:50.281308 <8>[ 29.696025] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11155 13:29:50.281890 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11157 13:29:50.290660 /lava-11471184/1/../bin/lava-test-case
11158 13:29:50.297772 <8>[ 29.711931] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11159 13:29:50.298447 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11161 13:29:50.307441 /lava-11471184/1/../bin/lava-test-case
11162 13:29:50.314326 <8>[ 29.729461] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11163 13:29:50.314995 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11165 13:29:50.323750 /lava-11471184/1/../bin/lava-test-case
11166 13:29:50.330029 <8>[ 29.744400] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11167 13:29:50.330668 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11169 13:29:50.347515 /lava-11471184/1/../bin/lava-tes<8>[ 29.760666] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11170 13:29:50.347965 t-case
11171 13:29:50.348455 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11173 13:29:50.357524 /lava-11471184/1/../bin/lava-test-case
11174 13:29:50.363869 <8>[ 29.777810] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11175 13:29:50.364670 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11177 13:29:50.374483 /lava-11471184/1/../bin/lava-test-case
11178 13:29:50.380934 <8>[ 29.795579] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11179 13:29:50.381642 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11181 13:29:50.389757 /lava-11471184/1/../bin/lava-test-case
11182 13:29:50.396631 <8>[ 29.810518] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11183 13:29:50.397329 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11185 13:29:50.407821 /lava-11471184/1/../bin/lava-test-case
11186 13:29:50.414747 <8>[ 29.829595] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11187 13:29:50.415454 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11189 13:29:50.425623 /lava-11471184/1/../bin/lava-test-case
11190 13:29:50.432606 <8>[ 29.846036] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11191 13:29:50.433348 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11193 13:29:50.442206 /lava-11471184/1/../bin/lava-test-case
11194 13:29:50.452209 <8>[ 29.866178] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11195 13:29:50.452978 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11197 13:29:50.460050 /lava-11471184/1/../bin/lava-test-case
11198 13:29:50.466431 <8>[ 29.880712] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11199 13:29:50.467060 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11201 13:29:50.482911 /lava-11471184/1/../bin/lava-tes<8>[ 29.899802] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11202 13:29:50.483557 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11204 13:29:50.486499 t-case
11205 13:29:50.493062 /lava-11471184/1/../bin/lava-test-case
11206 13:29:50.500085 <8>[ 29.913942] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11207 13:29:50.500839 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11209 13:29:50.515621 /lava-11471184/1/../bin/lava-tes<8>[ 29.931816] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11210 13:29:50.516369 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11212 13:29:50.518519 t-case
11213 13:29:50.536591 /lava-11471184/1/../bin/lava-tes<8>[ 29.949941] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11214 13:29:50.537040 t-case
11215 13:29:50.537549 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11217 13:29:50.546487 /lava-11471184/1/../bin/lava-test-case
11218 13:29:50.552596 <8>[ 29.967023] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11219 13:29:50.553311 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11221 13:29:51.563321 /lava-11471184/1/../bin/lava-test-case
11222 13:29:51.569787 <8>[ 30.984884] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11223 13:29:51.570039 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11225 13:29:52.587465 /lava-11471184/1/../bin/lava-test-case
11226 13:29:52.593565 <8>[ 32.008999] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11227 13:29:52.594377 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11228 13:29:52.594869 Bad test result: blocked
11229 13:29:52.602700 /lava-11471184/1/../bin/lava-test-case
11230 13:29:52.609494 <8>[ 32.023832] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11231 13:29:52.610181 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11233 13:29:53.624487 /lava-11471184/1/../bin/lava-test-case
11234 13:29:53.631146 <8>[ 33.045716] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11235 13:29:53.631902 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11237 13:29:53.642006 /lava-11471184/1/../bin/lava-test-case
11238 13:29:53.648723 <8>[ 33.064364] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11239 13:29:53.649466 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11241 13:29:53.661957 /lava-11471184/1/../bin/lava-test-case
11242 13:29:53.668181 <8>[ 33.083211] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11243 13:29:53.668962 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11245 13:29:53.679860 /lava-11471184/1/../bin/lava-test-case
11246 13:29:53.686957 <8>[ 33.101137] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11247 13:29:53.687702 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11249 13:29:53.703259 /lava-11471184/1/../bin/lava-tes<8>[ 33.116550] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11250 13:29:53.703752 t-case
11251 13:29:53.704333 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11253 13:29:53.713336 /lava-11471184/1/../bin/lava-test-case
11254 13:29:53.719885 <8>[ 33.134813] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11255 13:29:53.720643 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11257 13:29:53.727944 /lava-11471184/1/../bin/lava-test-case
11258 13:29:53.734401 <8>[ 33.149207] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11259 13:29:53.735117 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11261 13:29:54.749432 /lava-11471184/1/../bin/lava-test-case
11262 13:29:54.755902 <8>[ 34.170661] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11263 13:29:54.756673 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11265 13:29:54.765983 /lava-11471184/1/../bin/lava-test-case
11266 13:29:54.772394 <8>[ 34.187591] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11267 13:29:54.773121 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11269 13:29:55.786092 /lava-11471184/1/../bin/lava-test-case
11270 13:29:55.792806 <8>[ 35.207661] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11271 13:29:55.793066 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11273 13:29:55.802793 /lava-11471184/1/../bin/lava-test-case
11274 13:29:55.808666 <8>[ 35.224583] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11275 13:29:55.808924 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11277 13:29:56.823282 /lava-11471184/1/../bin/lava-test-case
11278 13:29:56.830111 <8>[ 36.245967] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11279 13:29:56.830390 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11281 13:29:56.847635 /lava-11471184/1/../bin/lava-tes<8>[ 36.262563] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11282 13:29:56.847712 t-case
11283 13:29:56.847935 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11285 13:29:57.859926 /lava-11471184/1/../bin/lava-test-case
11286 13:29:57.866860 <8>[ 37.282242] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11287 13:29:57.867114 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11289 13:29:57.878218 /lava-11471184/1/../bin/lava-test-case
11290 13:29:57.884559 <8>[ 37.300584] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11291 13:29:57.884802 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11293 13:29:57.892492 /lava-11471184/1/../bin/lava-test-case
11294 13:29:57.901993 <8>[ 37.317467] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11295 13:29:57.902238 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11297 13:29:57.914295 /lava-11471184/1/../bin/lava-test-case
11298 13:29:57.921046 <8>[ 37.337833] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11299 13:29:57.921296 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11301 13:29:57.930538 /lava-11471184/1/../bin/lava-test-case
11302 13:29:57.937239 <8>[ 37.352525] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11303 13:29:57.937487 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11305 13:29:57.948813 /lava-11471184/1/../bin/lava-test-case
11306 13:29:57.955011 <8>[ 37.370523] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11307 13:29:57.955257 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11309 13:29:57.962877 /lava-11471184/1/../bin/lava-test-case
11310 13:29:57.969203 <8>[ 37.385882] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11311 13:29:57.969446 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11313 13:29:57.980519 /lava-11471184/1/../bin/lava-test-case
11314 13:29:57.986637 <8>[ 37.403453] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11315 13:29:57.986882 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11317 13:29:57.996958 /lava-11471184/1/../bin/lava-test-case
11318 13:29:58.003499 <8>[ 37.419192] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11319 13:29:58.003744 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11321 13:29:58.013705 /lava-11471184/1/../bin/lava-test-case
11322 13:29:58.020821 <8>[ 37.435840] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11323 13:29:58.021066 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11325 13:29:58.024887 + set +x
11326 13:29:58.031133 <8>[ 37.446717] <LAVA_SIGNAL_ENDRUN 1_bootrr 11471184_1.5.2.3.5>
11327 13:29:58.031379 Received signal: <ENDRUN> 1_bootrr 11471184_1.5.2.3.5
11328 13:29:58.031452 Ending use of test pattern.
11329 13:29:58.031502 Ending test lava.1_bootrr (11471184_1.5.2.3.5), duration 20.23
11331 13:29:58.031749 ok: lava_test_shell seems to have completed
11332 13:29:58.032602 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: pass
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11333 13:29:58.032720 end: 4.1 lava-test-shell (duration 00:00:21) [common]
11334 13:29:58.032788 end: 4 lava-test-retry (duration 00:00:21) [common]
11335 13:29:58.032854 start: 5 finalize (timeout 00:08:08) [common]
11336 13:29:58.032923 start: 5.1 power-off (timeout 00:00:30) [common]
11337 13:29:58.033046 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
11338 13:29:58.104481 >> Command sent successfully.
11339 13:29:58.106578 Returned 0 in 0 seconds
11340 13:29:58.206949 end: 5.1 power-off (duration 00:00:00) [common]
11342 13:29:58.207268 start: 5.2 read-feedback (timeout 00:08:08) [common]
11344 13:29:58.207768 Listened to connection for namespace 'common' for up to 1s
11345 13:29:59.208362 Finalising connection for namespace 'common'
11346 13:29:59.208521 Disconnecting from shell: Finalise
11347 13:29:59.208601 / #
11348 13:29:59.308909 end: 5.2 read-feedback (duration 00:00:01) [common]
11349 13:29:59.309061 end: 5 finalize (duration 00:00:01) [common]
11350 13:29:59.309151 Cleaning after the job
11351 13:29:59.309232 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11471184/tftp-deploy-xgwar0g1/ramdisk
11352 13:29:59.311351 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11471184/tftp-deploy-xgwar0g1/kernel
11353 13:29:59.317313 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11471184/tftp-deploy-xgwar0g1/dtb
11354 13:29:59.317497 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11471184/tftp-deploy-xgwar0g1/modules
11355 13:29:59.322342 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11471184
11356 13:29:59.348191 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11471184
11357 13:29:59.348374 Job finished correctly