Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 35
- Boot result: PASS
- Warnings: 1
- Errors: 2
- Kernel Warnings: 65
1 13:31:07.174966 lava-dispatcher, installed at version: 2023.06
2 13:31:07.175271 start: 0 validate
3 13:31:07.175513 Start time: 2023-09-08 13:31:07.175502+00:00 (UTC)
4 13:31:07.175709 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:31:07.175919 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 13:31:07.437194 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:31:07.437405 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.52-cip5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:31:07.695433 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:31:07.695596 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.52-cip5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:31:07.955554 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:31:07.955719 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.52-cip5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 13:31:08.480059 validate duration: 1.30
14 13:31:08.480467 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:31:08.480633 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:31:08.480809 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:31:08.480983 Not decompressing ramdisk as can be used compressed.
18 13:31:08.481131 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 13:31:08.481238 saving as /var/lib/lava/dispatcher/tmp/11471202/tftp-deploy-6wala_bt/ramdisk/rootfs.cpio.gz
20 13:31:08.481338 total size: 26246609 (25 MB)
21 13:31:08.484083 progress 0 % (0 MB)
22 13:31:08.516331 progress 5 % (1 MB)
23 13:31:08.552929 progress 10 % (2 MB)
24 13:31:08.589710 progress 15 % (3 MB)
25 13:31:08.666011 progress 20 % (5 MB)
26 13:31:08.714405 progress 25 % (6 MB)
27 13:31:08.738039 progress 30 % (7 MB)
28 13:31:08.755730 progress 35 % (8 MB)
29 13:31:08.767664 progress 40 % (10 MB)
30 13:31:08.776658 progress 45 % (11 MB)
31 13:31:08.784322 progress 50 % (12 MB)
32 13:31:08.791043 progress 55 % (13 MB)
33 13:31:08.797703 progress 60 % (15 MB)
34 13:31:08.804480 progress 65 % (16 MB)
35 13:31:08.811305 progress 70 % (17 MB)
36 13:31:08.818030 progress 75 % (18 MB)
37 13:31:08.824684 progress 80 % (20 MB)
38 13:31:08.831741 progress 85 % (21 MB)
39 13:31:08.838507 progress 90 % (22 MB)
40 13:31:08.845234 progress 95 % (23 MB)
41 13:31:08.853836 progress 100 % (25 MB)
42 13:31:08.854167 25 MB downloaded in 0.37 s (67.14 MB/s)
43 13:31:08.854339 end: 1.1.1 http-download (duration 00:00:00) [common]
45 13:31:08.854585 end: 1.1 download-retry (duration 00:00:00) [common]
46 13:31:08.854676 start: 1.2 download-retry (timeout 00:10:00) [common]
47 13:31:08.854761 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 13:31:08.854900 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.52-cip5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 13:31:08.854970 saving as /var/lib/lava/dispatcher/tmp/11471202/tftp-deploy-6wala_bt/kernel/Image
50 13:31:08.855030 total size: 49220096 (46 MB)
51 13:31:08.855091 No compression specified
52 13:31:08.856279 progress 0 % (0 MB)
53 13:31:08.869562 progress 5 % (2 MB)
54 13:31:08.883129 progress 10 % (4 MB)
55 13:31:08.896567 progress 15 % (7 MB)
56 13:31:08.909635 progress 20 % (9 MB)
57 13:31:08.922364 progress 25 % (11 MB)
58 13:31:08.935201 progress 30 % (14 MB)
59 13:31:08.948729 progress 35 % (16 MB)
60 13:31:08.962159 progress 40 % (18 MB)
61 13:31:08.975323 progress 45 % (21 MB)
62 13:31:08.988565 progress 50 % (23 MB)
63 13:31:09.001412 progress 55 % (25 MB)
64 13:31:09.014213 progress 60 % (28 MB)
65 13:31:09.027514 progress 65 % (30 MB)
66 13:31:09.040354 progress 70 % (32 MB)
67 13:31:09.053665 progress 75 % (35 MB)
68 13:31:09.066635 progress 80 % (37 MB)
69 13:31:09.079667 progress 85 % (39 MB)
70 13:31:09.092610 progress 90 % (42 MB)
71 13:31:09.105462 progress 95 % (44 MB)
72 13:31:09.118208 progress 100 % (46 MB)
73 13:31:09.118390 46 MB downloaded in 0.26 s (178.24 MB/s)
74 13:31:09.118583 end: 1.2.1 http-download (duration 00:00:00) [common]
76 13:31:09.118813 end: 1.2 download-retry (duration 00:00:00) [common]
77 13:31:09.118905 start: 1.3 download-retry (timeout 00:09:59) [common]
78 13:31:09.119022 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 13:31:09.119170 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.52-cip5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 13:31:09.119241 saving as /var/lib/lava/dispatcher/tmp/11471202/tftp-deploy-6wala_bt/dtb/mt8192-asurada-spherion-r0.dtb
81 13:31:09.119320 total size: 47278 (0 MB)
82 13:31:09.119396 No compression specified
83 13:31:09.120594 progress 69 % (0 MB)
84 13:31:09.120874 progress 100 % (0 MB)
85 13:31:09.121032 0 MB downloaded in 0.00 s (26.36 MB/s)
86 13:31:09.121158 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:31:09.121381 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:31:09.121465 start: 1.4 download-retry (timeout 00:09:59) [common]
90 13:31:09.121547 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 13:31:09.121663 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.52-cip5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 13:31:09.121732 saving as /var/lib/lava/dispatcher/tmp/11471202/tftp-deploy-6wala_bt/modules/modules.tar
93 13:31:09.121792 total size: 8615576 (8 MB)
94 13:31:09.121852 Using unxz to decompress xz
95 13:31:09.125885 progress 0 % (0 MB)
96 13:31:09.148420 progress 5 % (0 MB)
97 13:31:09.171186 progress 10 % (0 MB)
98 13:31:09.198913 progress 15 % (1 MB)
99 13:31:09.226390 progress 20 % (1 MB)
100 13:31:09.253153 progress 25 % (2 MB)
101 13:31:09.280047 progress 30 % (2 MB)
102 13:31:09.307511 progress 35 % (2 MB)
103 13:31:09.333235 progress 40 % (3 MB)
104 13:31:09.358110 progress 45 % (3 MB)
105 13:31:09.384912 progress 50 % (4 MB)
106 13:31:09.410631 progress 55 % (4 MB)
107 13:31:09.435669 progress 60 % (4 MB)
108 13:31:09.458803 progress 65 % (5 MB)
109 13:31:09.486710 progress 70 % (5 MB)
110 13:31:09.511322 progress 75 % (6 MB)
111 13:31:09.537650 progress 80 % (6 MB)
112 13:31:09.568177 progress 85 % (7 MB)
113 13:31:09.595832 progress 90 % (7 MB)
114 13:31:09.620437 progress 95 % (7 MB)
115 13:31:09.644279 progress 100 % (8 MB)
116 13:31:09.651013 8 MB downloaded in 0.53 s (15.53 MB/s)
117 13:31:09.651310 end: 1.4.1 http-download (duration 00:00:01) [common]
119 13:31:09.651623 end: 1.4 download-retry (duration 00:00:01) [common]
120 13:31:09.651717 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 13:31:09.651812 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 13:31:09.651895 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:31:09.651986 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 13:31:09.652215 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11471202/lava-overlay-m1sopmgh
125 13:31:09.652350 makedir: /var/lib/lava/dispatcher/tmp/11471202/lava-overlay-m1sopmgh/lava-11471202/bin
126 13:31:09.652458 makedir: /var/lib/lava/dispatcher/tmp/11471202/lava-overlay-m1sopmgh/lava-11471202/tests
127 13:31:09.652558 makedir: /var/lib/lava/dispatcher/tmp/11471202/lava-overlay-m1sopmgh/lava-11471202/results
128 13:31:09.652676 Creating /var/lib/lava/dispatcher/tmp/11471202/lava-overlay-m1sopmgh/lava-11471202/bin/lava-add-keys
129 13:31:09.652825 Creating /var/lib/lava/dispatcher/tmp/11471202/lava-overlay-m1sopmgh/lava-11471202/bin/lava-add-sources
130 13:31:09.652957 Creating /var/lib/lava/dispatcher/tmp/11471202/lava-overlay-m1sopmgh/lava-11471202/bin/lava-background-process-start
131 13:31:09.653090 Creating /var/lib/lava/dispatcher/tmp/11471202/lava-overlay-m1sopmgh/lava-11471202/bin/lava-background-process-stop
132 13:31:09.653218 Creating /var/lib/lava/dispatcher/tmp/11471202/lava-overlay-m1sopmgh/lava-11471202/bin/lava-common-functions
133 13:31:09.653345 Creating /var/lib/lava/dispatcher/tmp/11471202/lava-overlay-m1sopmgh/lava-11471202/bin/lava-echo-ipv4
134 13:31:09.653473 Creating /var/lib/lava/dispatcher/tmp/11471202/lava-overlay-m1sopmgh/lava-11471202/bin/lava-install-packages
135 13:31:09.653599 Creating /var/lib/lava/dispatcher/tmp/11471202/lava-overlay-m1sopmgh/lava-11471202/bin/lava-installed-packages
136 13:31:09.653738 Creating /var/lib/lava/dispatcher/tmp/11471202/lava-overlay-m1sopmgh/lava-11471202/bin/lava-os-build
137 13:31:09.653903 Creating /var/lib/lava/dispatcher/tmp/11471202/lava-overlay-m1sopmgh/lava-11471202/bin/lava-probe-channel
138 13:31:09.654037 Creating /var/lib/lava/dispatcher/tmp/11471202/lava-overlay-m1sopmgh/lava-11471202/bin/lava-probe-ip
139 13:31:09.654168 Creating /var/lib/lava/dispatcher/tmp/11471202/lava-overlay-m1sopmgh/lava-11471202/bin/lava-target-ip
140 13:31:09.654295 Creating /var/lib/lava/dispatcher/tmp/11471202/lava-overlay-m1sopmgh/lava-11471202/bin/lava-target-mac
141 13:31:09.654422 Creating /var/lib/lava/dispatcher/tmp/11471202/lava-overlay-m1sopmgh/lava-11471202/bin/lava-target-storage
142 13:31:09.654554 Creating /var/lib/lava/dispatcher/tmp/11471202/lava-overlay-m1sopmgh/lava-11471202/bin/lava-test-case
143 13:31:09.654681 Creating /var/lib/lava/dispatcher/tmp/11471202/lava-overlay-m1sopmgh/lava-11471202/bin/lava-test-event
144 13:31:09.654807 Creating /var/lib/lava/dispatcher/tmp/11471202/lava-overlay-m1sopmgh/lava-11471202/bin/lava-test-feedback
145 13:31:09.654932 Creating /var/lib/lava/dispatcher/tmp/11471202/lava-overlay-m1sopmgh/lava-11471202/bin/lava-test-raise
146 13:31:09.655062 Creating /var/lib/lava/dispatcher/tmp/11471202/lava-overlay-m1sopmgh/lava-11471202/bin/lava-test-reference
147 13:31:09.655190 Creating /var/lib/lava/dispatcher/tmp/11471202/lava-overlay-m1sopmgh/lava-11471202/bin/lava-test-runner
148 13:31:09.655315 Creating /var/lib/lava/dispatcher/tmp/11471202/lava-overlay-m1sopmgh/lava-11471202/bin/lava-test-set
149 13:31:09.655490 Creating /var/lib/lava/dispatcher/tmp/11471202/lava-overlay-m1sopmgh/lava-11471202/bin/lava-test-shell
150 13:31:09.655620 Updating /var/lib/lava/dispatcher/tmp/11471202/lava-overlay-m1sopmgh/lava-11471202/bin/lava-install-packages (oe)
151 13:31:09.655780 Updating /var/lib/lava/dispatcher/tmp/11471202/lava-overlay-m1sopmgh/lava-11471202/bin/lava-installed-packages (oe)
152 13:31:09.655905 Creating /var/lib/lava/dispatcher/tmp/11471202/lava-overlay-m1sopmgh/lava-11471202/environment
153 13:31:09.656016 LAVA metadata
154 13:31:09.656091 - LAVA_JOB_ID=11471202
155 13:31:09.656156 - LAVA_DISPATCHER_IP=192.168.201.1
156 13:31:09.656259 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 13:31:09.656328 skipped lava-vland-overlay
158 13:31:09.656402 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 13:31:09.656480 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 13:31:09.656544 skipped lava-multinode-overlay
161 13:31:09.656615 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 13:31:09.656698 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 13:31:09.656772 Loading test definitions
164 13:31:09.656863 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 13:31:09.656938 Using /lava-11471202 at stage 0
166 13:31:09.657254 uuid=11471202_1.5.2.3.1 testdef=None
167 13:31:09.657341 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 13:31:09.657429 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 13:31:09.657962 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 13:31:09.658177 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 13:31:09.658793 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 13:31:09.659019 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 13:31:09.659655 runner path: /var/lib/lava/dispatcher/tmp/11471202/lava-overlay-m1sopmgh/lava-11471202/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 11471202_1.5.2.3.1
176 13:31:09.659811 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 13:31:09.660094 Creating lava-test-runner.conf files
179 13:31:09.660175 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11471202/lava-overlay-m1sopmgh/lava-11471202/0 for stage 0
180 13:31:09.660278 - 0_v4l2-compliance-mtk-vcodec-enc
181 13:31:09.660393 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 13:31:09.660493 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 13:31:09.667409 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 13:31:09.667570 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 13:31:09.667679 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 13:31:09.667782 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 13:31:09.667976 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 13:31:10.422391 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 13:31:10.422774 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 13:31:10.422891 extracting modules file /var/lib/lava/dispatcher/tmp/11471202/tftp-deploy-6wala_bt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11471202/extract-overlay-ramdisk-ffbt6l9n/ramdisk
191 13:31:10.682048 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 13:31:10.682260 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 13:31:10.682395 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11471202/compress-overlay-75_eiba8/overlay-1.5.2.4.tar.gz to ramdisk
194 13:31:10.682503 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11471202/compress-overlay-75_eiba8/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11471202/extract-overlay-ramdisk-ffbt6l9n/ramdisk
195 13:31:10.693599 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 13:31:10.693799 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 13:31:10.693928 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 13:31:10.694053 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 13:31:10.694171 Building ramdisk /var/lib/lava/dispatcher/tmp/11471202/extract-overlay-ramdisk-ffbt6l9n/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11471202/extract-overlay-ramdisk-ffbt6l9n/ramdisk
200 13:31:11.485388 >> 228289 blocks
201 13:31:15.509491 rename /var/lib/lava/dispatcher/tmp/11471202/extract-overlay-ramdisk-ffbt6l9n/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11471202/tftp-deploy-6wala_bt/ramdisk/ramdisk.cpio.gz
202 13:31:15.509981 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 13:31:15.510147 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 13:31:15.510293 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 13:31:15.510444 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11471202/tftp-deploy-6wala_bt/kernel/Image'
206 13:31:29.507863 Returned 0 in 13 seconds
207 13:31:29.608518 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11471202/tftp-deploy-6wala_bt/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11471202/tftp-deploy-6wala_bt/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11471202/tftp-deploy-6wala_bt/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11471202/tftp-deploy-6wala_bt/kernel/image.itb
208 13:31:30.302903 output: FIT description: Kernel Image image with one or more FDT blobs
209 13:31:30.303267 output: Created: Fri Sep 8 14:31:30 2023
210 13:31:30.303339 output: Image 0 (kernel-1)
211 13:31:30.303481 output: Description:
212 13:31:30.303546 output: Created: Fri Sep 8 14:31:30 2023
213 13:31:30.303609 output: Type: Kernel Image
214 13:31:30.303670 output: Compression: lzma compressed
215 13:31:30.303729 output: Data Size: 11040095 Bytes = 10781.34 KiB = 10.53 MiB
216 13:31:30.303788 output: Architecture: AArch64
217 13:31:30.303845 output: OS: Linux
218 13:31:30.303901 output: Load Address: 0x00000000
219 13:31:30.303953 output: Entry Point: 0x00000000
220 13:31:30.304005 output: Hash algo: crc32
221 13:31:30.304057 output: Hash value: 41c180c9
222 13:31:30.304114 output: Image 1 (fdt-1)
223 13:31:30.304167 output: Description: mt8192-asurada-spherion-r0
224 13:31:30.304218 output: Created: Fri Sep 8 14:31:30 2023
225 13:31:30.304270 output: Type: Flat Device Tree
226 13:31:30.304322 output: Compression: uncompressed
227 13:31:30.304374 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 13:31:30.304426 output: Architecture: AArch64
229 13:31:30.304476 output: Hash algo: crc32
230 13:31:30.304528 output: Hash value: cc4352de
231 13:31:30.304579 output: Image 2 (ramdisk-1)
232 13:31:30.304629 output: Description: unavailable
233 13:31:30.304680 output: Created: Fri Sep 8 14:31:30 2023
234 13:31:30.304731 output: Type: RAMDisk Image
235 13:31:30.304782 output: Compression: Unknown Compression
236 13:31:30.304833 output: Data Size: 39338503 Bytes = 38416.51 KiB = 37.52 MiB
237 13:31:30.304885 output: Architecture: AArch64
238 13:31:30.304936 output: OS: Linux
239 13:31:30.304986 output: Load Address: unavailable
240 13:31:30.305037 output: Entry Point: unavailable
241 13:31:30.305088 output: Hash algo: crc32
242 13:31:30.305138 output: Hash value: e7b169ba
243 13:31:30.305189 output: Default Configuration: 'conf-1'
244 13:31:30.305240 output: Configuration 0 (conf-1)
245 13:31:30.305291 output: Description: mt8192-asurada-spherion-r0
246 13:31:30.305342 output: Kernel: kernel-1
247 13:31:30.305392 output: Init Ramdisk: ramdisk-1
248 13:31:30.305443 output: FDT: fdt-1
249 13:31:30.305493 output: Loadables: kernel-1
250 13:31:30.305544 output:
251 13:31:30.305737 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 13:31:30.305833 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 13:31:30.305941 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 13:31:30.306032 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 13:31:30.306150 No LXC device requested
256 13:31:30.306247 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 13:31:30.306335 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 13:31:30.306412 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 13:31:30.306479 Checking files for TFTP limit of 4294967296 bytes.
260 13:31:30.306975 end: 1 tftp-deploy (duration 00:00:22) [common]
261 13:31:30.307076 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 13:31:30.307165 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 13:31:30.307291 substitutions:
264 13:31:30.307357 - {DTB}: 11471202/tftp-deploy-6wala_bt/dtb/mt8192-asurada-spherion-r0.dtb
265 13:31:30.307463 - {INITRD}: 11471202/tftp-deploy-6wala_bt/ramdisk/ramdisk.cpio.gz
266 13:31:30.307522 - {KERNEL}: 11471202/tftp-deploy-6wala_bt/kernel/Image
267 13:31:30.307578 - {LAVA_MAC}: None
268 13:31:30.307634 - {PRESEED_CONFIG}: None
269 13:31:30.307688 - {PRESEED_LOCAL}: None
270 13:31:30.307741 - {RAMDISK}: 11471202/tftp-deploy-6wala_bt/ramdisk/ramdisk.cpio.gz
271 13:31:30.307796 - {ROOT_PART}: None
272 13:31:30.307849 - {ROOT}: None
273 13:31:30.307902 - {SERVER_IP}: 192.168.201.1
274 13:31:30.307954 - {TEE}: None
275 13:31:30.308007 Parsed boot commands:
276 13:31:30.308059 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 13:31:30.308240 Parsed boot commands: tftpboot 192.168.201.1 11471202/tftp-deploy-6wala_bt/kernel/image.itb 11471202/tftp-deploy-6wala_bt/kernel/cmdline
278 13:31:30.308327 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 13:31:30.308409 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 13:31:30.308499 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 13:31:30.308580 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 13:31:30.308650 Not connected, no need to disconnect.
283 13:31:30.308721 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 13:31:30.308800 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 13:31:30.308866 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
286 13:31:30.312734 Setting prompt string to ['lava-test: # ']
287 13:31:30.313137 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 13:31:30.313253 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 13:31:30.313353 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 13:31:30.313448 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 13:31:30.313717 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
292 13:31:35.445056 >> Command sent successfully.
293 13:31:35.448000 Returned 0 in 5 seconds
294 13:31:35.548406 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 13:31:35.548738 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 13:31:35.548867 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 13:31:35.548985 Setting prompt string to 'Starting depthcharge on Spherion...'
299 13:31:35.549060 Changing prompt to 'Starting depthcharge on Spherion...'
300 13:31:35.549128 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 13:31:35.549489 [Enter `^Ec?' for help]
302 13:31:35.720725
303 13:31:35.720879
304 13:31:35.720945 F0: 102B 0000
305 13:31:35.721007
306 13:31:35.721066 F3: 1001 0000 [0200]
307 13:31:35.721124
308 13:31:35.724677 F3: 1001 0000
309 13:31:35.724759
310 13:31:35.724823 F7: 102D 0000
311 13:31:35.724884
312 13:31:35.727921 F1: 0000 0000
313 13:31:35.728003
314 13:31:35.728071 V0: 0000 0000 [0001]
315 13:31:35.728134
316 13:31:35.730975 00: 0007 8000
317 13:31:35.731061
318 13:31:35.731125 01: 0000 0000
319 13:31:35.731186
320 13:31:35.731243 BP: 0C00 0209 [0000]
321 13:31:35.734555
322 13:31:35.734636 G0: 1182 0000
323 13:31:35.734701
324 13:31:35.734761 EC: 0000 0021 [4000]
325 13:31:35.734819
326 13:31:35.737907 S7: 0000 0000 [0000]
327 13:31:35.737988
328 13:31:35.738053 CC: 0000 0000 [0001]
329 13:31:35.740940
330 13:31:35.741053 T0: 0000 0040 [010F]
331 13:31:35.741118
332 13:31:35.741179 Jump to BL
333 13:31:35.741238
334 13:31:35.767783
335 13:31:35.767905
336 13:31:35.767974
337 13:31:35.774723 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 13:31:35.778685 ARM64: Exception handlers installed.
339 13:31:35.781839 ARM64: Testing exception
340 13:31:35.785554 ARM64: Done test exception
341 13:31:35.791784 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 13:31:35.802428 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 13:31:35.808869 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 13:31:35.818735 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 13:31:35.825873 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 13:31:35.832279 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 13:31:35.843982 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 13:31:35.850587 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 13:31:35.870037 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 13:31:35.873671 WDT: Last reset was cold boot
351 13:31:35.876814 SPI1(PAD0) initialized at 2873684 Hz
352 13:31:35.880567 SPI5(PAD0) initialized at 992727 Hz
353 13:31:35.883784 VBOOT: Loading verstage.
354 13:31:35.890000 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 13:31:35.893814 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 13:31:35.896953 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 13:31:35.900156 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 13:31:35.907555 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 13:31:35.914690 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 13:31:35.925079 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 13:31:35.925163
362 13:31:35.925234
363 13:31:35.935178 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 13:31:35.938351 ARM64: Exception handlers installed.
365 13:31:35.942201 ARM64: Testing exception
366 13:31:35.942309 ARM64: Done test exception
367 13:31:35.948396 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 13:31:35.951954 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 13:31:35.966483 Probing TPM: . done!
370 13:31:35.966595 TPM ready after 0 ms
371 13:31:35.973014 Connected to device vid:did:rid of 1ae0:0028:00
372 13:31:35.980270 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 13:31:36.020968 Initialized TPM device CR50 revision 0
374 13:31:36.032585 tlcl_send_startup: Startup return code is 0
375 13:31:36.032684 TPM: setup succeeded
376 13:31:36.044095 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 13:31:36.053125 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 13:31:36.064991 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 13:31:36.073931 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 13:31:36.077916 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 13:31:36.081687 in-header: 03 07 00 00 08 00 00 00
382 13:31:36.084921 in-data: aa e4 47 04 13 02 00 00
383 13:31:36.088610 Chrome EC: UHEPI supported
384 13:31:36.091922 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 13:31:36.097056 in-header: 03 9d 00 00 08 00 00 00
386 13:31:36.100764 in-data: 10 20 20 08 00 00 00 00
387 13:31:36.100851 Phase 1
388 13:31:36.104371 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 13:31:36.111715 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 13:31:36.119532 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 13:31:36.119617 Recovery requested (1009000e)
392 13:31:36.128126 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 13:31:36.133359 tlcl_extend: response is 0
394 13:31:36.141758 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 13:31:36.146998 tlcl_extend: response is 0
396 13:31:36.153362 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 13:31:36.174186 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 13:31:36.182099 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 13:31:36.182216
400 13:31:36.182289
401 13:31:36.188982 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 13:31:36.192938 ARM64: Exception handlers installed.
403 13:31:36.196703 ARM64: Testing exception
404 13:31:36.199908 ARM64: Done test exception
405 13:31:36.219952 pmic_efuse_setting: Set efuses in 11 msecs
406 13:31:36.223451 pmwrap_interface_init: Select PMIF_VLD_RDY
407 13:31:36.230257 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 13:31:36.233896 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 13:31:36.237604 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 13:31:36.245417 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 13:31:36.248777 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 13:31:36.252611 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 13:31:36.256553 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 13:31:36.263096 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 13:31:36.266750 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 13:31:36.272910 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 13:31:36.276844 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 13:31:36.279891 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 13:31:36.286277 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 13:31:36.293306 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 13:31:36.296474 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 13:31:36.303790 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 13:31:36.310129 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 13:31:36.313440 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 13:31:36.319950 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 13:31:36.327347 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 13:31:36.331211 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 13:31:36.338749 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 13:31:36.341821 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 13:31:36.348835 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 13:31:36.352409 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 13:31:36.359043 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 13:31:36.362265 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 13:31:36.369496 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 13:31:36.373220 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 13:31:36.380141 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 13:31:36.383939 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 13:31:36.386953 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 13:31:36.394619 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 13:31:36.398552 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 13:31:36.402376 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 13:31:36.409373 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 13:31:36.412717 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 13:31:36.419154 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 13:31:36.422537 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 13:31:36.425829 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 13:31:36.432352 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 13:31:36.435540 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 13:31:36.439141 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 13:31:36.445823 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 13:31:36.449009 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 13:31:36.452304 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 13:31:36.456009 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 13:31:36.462497 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 13:31:36.466045 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 13:31:36.468967 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 13:31:36.475880 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 13:31:36.482632 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 13:31:36.489037 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 13:31:36.495901 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 13:31:36.502448 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 13:31:36.512564 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 13:31:36.516135 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 13:31:36.522585 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 13:31:36.525782 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 13:31:36.532357 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x20
467 13:31:36.539194 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 13:31:36.542351 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 13:31:36.546007 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 13:31:36.556936 [RTC]rtc_get_frequency_meter,154: input=15, output=793
471 13:31:36.560206 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 13:31:36.566648 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 13:31:36.570337 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
474 13:31:36.573257 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 13:31:36.576371 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
476 13:31:36.579887 ADC[4]: Raw value=899260 ID=7
477 13:31:36.583343 ADC[3]: Raw value=212700 ID=1
478 13:31:36.586343 RAM Code: 0x71
479 13:31:36.589975 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 13:31:36.593146 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 13:31:36.603187 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 13:31:36.610140 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 13:31:36.613995 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 13:31:36.617270 in-header: 03 07 00 00 08 00 00 00
485 13:31:36.620463 in-data: aa e4 47 04 13 02 00 00
486 13:31:36.623654 Chrome EC: UHEPI supported
487 13:31:36.627701 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 13:31:36.631561 in-header: 03 d5 00 00 08 00 00 00
489 13:31:36.635506 in-data: 98 20 60 08 00 00 00 00
490 13:31:36.638843 MRC: failed to locate region type 0.
491 13:31:36.646553 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 13:31:36.649504 DRAM-K: Running full calibration
493 13:31:36.653155 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 13:31:36.657083 header.status = 0x0
495 13:31:36.660421 header.version = 0x6 (expected: 0x6)
496 13:31:36.664290 header.size = 0xd00 (expected: 0xd00)
497 13:31:36.664398 header.flags = 0x0
498 13:31:36.671522 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 13:31:36.689137 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
500 13:31:36.696748 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 13:31:36.700657 dram_init: ddr_geometry: 2
502 13:31:36.700744 [EMI] MDL number = 2
503 13:31:36.704820 [EMI] Get MDL freq = 0
504 13:31:36.704902 dram_init: ddr_type: 0
505 13:31:36.708191 is_discrete_lpddr4: 1
506 13:31:36.712038 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 13:31:36.712121
508 13:31:36.712185
509 13:31:36.712245 [Bian_co] ETT version 0.0.0.1
510 13:31:36.719809 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 13:31:36.719897
512 13:31:36.722970 dramc_set_vcore_voltage set vcore to 650000
513 13:31:36.723053 Read voltage for 800, 4
514 13:31:36.726703 Vio18 = 0
515 13:31:36.726786 Vcore = 650000
516 13:31:36.726852 Vdram = 0
517 13:31:36.726913 Vddq = 0
518 13:31:36.730659 Vmddr = 0
519 13:31:36.730741 dram_init: config_dvfs: 1
520 13:31:36.737823 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 13:31:36.741850 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 13:31:36.745075 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
523 13:31:36.748913 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
524 13:31:36.751947 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
525 13:31:36.755788 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
526 13:31:36.758867 MEM_TYPE=3, freq_sel=18
527 13:31:36.762554 sv_algorithm_assistance_LP4_1600
528 13:31:36.765691 ============ PULL DRAM RESETB DOWN ============
529 13:31:36.768910 ========== PULL DRAM RESETB DOWN end =========
530 13:31:36.776021 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 13:31:36.779164 ===================================
532 13:31:36.782368 LPDDR4 DRAM CONFIGURATION
533 13:31:36.785595 ===================================
534 13:31:36.785678 EX_ROW_EN[0] = 0x0
535 13:31:36.788790 EX_ROW_EN[1] = 0x0
536 13:31:36.788873 LP4Y_EN = 0x0
537 13:31:36.792085 WORK_FSP = 0x0
538 13:31:36.792168 WL = 0x2
539 13:31:36.795441 RL = 0x2
540 13:31:36.795524 BL = 0x2
541 13:31:36.798906 RPST = 0x0
542 13:31:36.798989 RD_PRE = 0x0
543 13:31:36.801938 WR_PRE = 0x1
544 13:31:36.802020 WR_PST = 0x0
545 13:31:36.805512 DBI_WR = 0x0
546 13:31:36.805595 DBI_RD = 0x0
547 13:31:36.808749 OTF = 0x1
548 13:31:36.811979 ===================================
549 13:31:36.815260 ===================================
550 13:31:36.815343 ANA top config
551 13:31:36.818485 ===================================
552 13:31:36.822199 DLL_ASYNC_EN = 0
553 13:31:36.825120 ALL_SLAVE_EN = 1
554 13:31:36.828903 NEW_RANK_MODE = 1
555 13:31:36.828990 DLL_IDLE_MODE = 1
556 13:31:36.832011 LP45_APHY_COMB_EN = 1
557 13:31:36.835527 TX_ODT_DIS = 1
558 13:31:36.838520 NEW_8X_MODE = 1
559 13:31:36.842177 ===================================
560 13:31:36.845426 ===================================
561 13:31:36.848629 data_rate = 1600
562 13:31:36.848711 CKR = 1
563 13:31:36.851872 DQ_P2S_RATIO = 8
564 13:31:36.855701 ===================================
565 13:31:36.858950 CA_P2S_RATIO = 8
566 13:31:36.861994 DQ_CA_OPEN = 0
567 13:31:36.865620 DQ_SEMI_OPEN = 0
568 13:31:36.868801 CA_SEMI_OPEN = 0
569 13:31:36.868882 CA_FULL_RATE = 0
570 13:31:36.872058 DQ_CKDIV4_EN = 1
571 13:31:36.875467 CA_CKDIV4_EN = 1
572 13:31:36.878632 CA_PREDIV_EN = 0
573 13:31:36.881848 PH8_DLY = 0
574 13:31:36.881939 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 13:31:36.885698 DQ_AAMCK_DIV = 4
576 13:31:36.888984 CA_AAMCK_DIV = 4
577 13:31:36.892139 CA_ADMCK_DIV = 4
578 13:31:36.895407 DQ_TRACK_CA_EN = 0
579 13:31:36.898618 CA_PICK = 800
580 13:31:36.901913 CA_MCKIO = 800
581 13:31:36.901995 MCKIO_SEMI = 0
582 13:31:36.905768 PLL_FREQ = 3068
583 13:31:36.908860 DQ_UI_PI_RATIO = 32
584 13:31:36.911943 CA_UI_PI_RATIO = 0
585 13:31:36.915812 ===================================
586 13:31:36.918649 ===================================
587 13:31:36.921833 memory_type:LPDDR4
588 13:31:36.921914 GP_NUM : 10
589 13:31:36.925102 SRAM_EN : 1
590 13:31:36.928308 MD32_EN : 0
591 13:31:36.931796 ===================================
592 13:31:36.931877 [ANA_INIT] >>>>>>>>>>>>>>
593 13:31:36.935410 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 13:31:36.938403 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 13:31:36.942269 ===================================
596 13:31:36.945456 data_rate = 1600,PCW = 0X7600
597 13:31:36.948638 ===================================
598 13:31:36.952082 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 13:31:36.958613 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 13:31:36.961965 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 13:31:36.968638 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 13:31:36.972454 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 13:31:36.975863 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 13:31:36.975942 [ANA_INIT] flow start
605 13:31:36.979092 [ANA_INIT] PLL >>>>>>>>
606 13:31:36.982992 [ANA_INIT] PLL <<<<<<<<
607 13:31:36.983075 [ANA_INIT] MIDPI >>>>>>>>
608 13:31:36.986327 [ANA_INIT] MIDPI <<<<<<<<
609 13:31:36.986410 [ANA_INIT] DLL >>>>>>>>
610 13:31:36.990164 [ANA_INIT] flow end
611 13:31:36.993522 ============ LP4 DIFF to SE enter ============
612 13:31:36.997457 ============ LP4 DIFF to SE exit ============
613 13:31:37.000640 [ANA_INIT] <<<<<<<<<<<<<
614 13:31:37.004583 [Flow] Enable top DCM control >>>>>
615 13:31:37.008428 [Flow] Enable top DCM control <<<<<
616 13:31:37.011599 Enable DLL master slave shuffle
617 13:31:37.014974 ==============================================================
618 13:31:37.018897 Gating Mode config
619 13:31:37.022125 ==============================================================
620 13:31:37.025704 Config description:
621 13:31:37.035756 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 13:31:37.041982 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 13:31:37.045883 SELPH_MODE 0: By rank 1: By Phase
624 13:31:37.052340 ==============================================================
625 13:31:37.055510 GAT_TRACK_EN = 1
626 13:31:37.058663 RX_GATING_MODE = 2
627 13:31:37.058754 RX_GATING_TRACK_MODE = 2
628 13:31:37.062361 SELPH_MODE = 1
629 13:31:37.065266 PICG_EARLY_EN = 1
630 13:31:37.068786 VALID_LAT_VALUE = 1
631 13:31:37.075162 ==============================================================
632 13:31:37.078841 Enter into Gating configuration >>>>
633 13:31:37.082420 Exit from Gating configuration <<<<
634 13:31:37.085321 Enter into DVFS_PRE_config >>>>>
635 13:31:37.095585 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 13:31:37.099587 Exit from DVFS_PRE_config <<<<<
637 13:31:37.103379 Enter into PICG configuration >>>>
638 13:31:37.106544 Exit from PICG configuration <<<<
639 13:31:37.106630 [RX_INPUT] configuration >>>>>
640 13:31:37.110427 [RX_INPUT] configuration <<<<<
641 13:31:37.117653 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 13:31:37.121506 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 13:31:37.128474 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 13:31:37.132216 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 13:31:37.139650 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 13:31:37.146745 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 13:31:37.150635 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 13:31:37.154603 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 13:31:37.157906 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 13:31:37.161856 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 13:31:37.165124 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 13:31:37.169536 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 13:31:37.173165 ===================================
654 13:31:37.176688 LPDDR4 DRAM CONFIGURATION
655 13:31:37.180450 ===================================
656 13:31:37.180537 EX_ROW_EN[0] = 0x0
657 13:31:37.184472 EX_ROW_EN[1] = 0x0
658 13:31:37.184557 LP4Y_EN = 0x0
659 13:31:37.188407 WORK_FSP = 0x0
660 13:31:37.188501 WL = 0x2
661 13:31:37.191607 RL = 0x2
662 13:31:37.191692 BL = 0x2
663 13:31:37.195478 RPST = 0x0
664 13:31:37.195563 RD_PRE = 0x0
665 13:31:37.199945 WR_PRE = 0x1
666 13:31:37.200030 WR_PST = 0x0
667 13:31:37.200097 DBI_WR = 0x0
668 13:31:37.203554 DBI_RD = 0x0
669 13:31:37.203643 OTF = 0x1
670 13:31:37.206571 ===================================
671 13:31:37.210694 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 13:31:37.214002 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 13:31:37.221577 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 13:31:37.224911 ===================================
675 13:31:37.224999 LPDDR4 DRAM CONFIGURATION
676 13:31:37.228863 ===================================
677 13:31:37.232664 EX_ROW_EN[0] = 0x10
678 13:31:37.232751 EX_ROW_EN[1] = 0x0
679 13:31:37.235906 LP4Y_EN = 0x0
680 13:31:37.235991 WORK_FSP = 0x0
681 13:31:37.239776 WL = 0x2
682 13:31:37.239875 RL = 0x2
683 13:31:37.243650 BL = 0x2
684 13:31:37.243734 RPST = 0x0
685 13:31:37.247258 RD_PRE = 0x0
686 13:31:37.247343 WR_PRE = 0x1
687 13:31:37.247422 WR_PST = 0x0
688 13:31:37.250988 DBI_WR = 0x0
689 13:31:37.251072 DBI_RD = 0x0
690 13:31:37.254287 OTF = 0x1
691 13:31:37.258234 ===================================
692 13:31:37.261632 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 13:31:37.267493 nWR fixed to 40
694 13:31:37.271362 [ModeRegInit_LP4] CH0 RK0
695 13:31:37.271483 [ModeRegInit_LP4] CH0 RK1
696 13:31:37.274687 [ModeRegInit_LP4] CH1 RK0
697 13:31:37.274769 [ModeRegInit_LP4] CH1 RK1
698 13:31:37.277964 match AC timing 13
699 13:31:37.281581 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 13:31:37.285609 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 13:31:37.292989 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 13:31:37.296867 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 13:31:37.300157 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 13:31:37.300240 [EMI DOE] emi_dcm 0
705 13:31:37.308439 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 13:31:37.308524 ==
707 13:31:37.311701 Dram Type= 6, Freq= 0, CH_0, rank 0
708 13:31:37.316165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 13:31:37.316249 ==
710 13:31:37.319325 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 13:31:37.326598 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 13:31:37.334962 [CA 0] Center 38 (7~69) winsize 63
713 13:31:37.338476 [CA 1] Center 37 (7~68) winsize 62
714 13:31:37.342589 [CA 2] Center 35 (5~66) winsize 62
715 13:31:37.345720 [CA 3] Center 35 (5~66) winsize 62
716 13:31:37.349551 [CA 4] Center 34 (4~65) winsize 62
717 13:31:37.353410 [CA 5] Center 34 (4~65) winsize 62
718 13:31:37.353494
719 13:31:37.356900 [CmdBusTrainingLP45] Vref(ca) range 1: 32
720 13:31:37.357000
721 13:31:37.360799 [CATrainingPosCal] consider 1 rank data
722 13:31:37.360911 u2DelayCellTimex100 = 270/100 ps
723 13:31:37.364146 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
724 13:31:37.371959 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
725 13:31:37.372070 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
726 13:31:37.375179 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
727 13:31:37.379137 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
728 13:31:37.382431 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
729 13:31:37.386351
730 13:31:37.386434 CA PerBit enable=1, Macro0, CA PI delay=34
731 13:31:37.390602
732 13:31:37.390730 [CBTSetCACLKResult] CA Dly = 34
733 13:31:37.394137 CS Dly: 6 (0~37)
734 13:31:37.394221 ==
735 13:31:37.397850 Dram Type= 6, Freq= 0, CH_0, rank 1
736 13:31:37.401048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 13:31:37.401164 ==
738 13:31:37.404287 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 13:31:37.411260 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 13:31:37.420871 [CA 0] Center 38 (7~69) winsize 63
741 13:31:37.424131 [CA 1] Center 38 (7~69) winsize 63
742 13:31:37.427408 [CA 2] Center 35 (5~66) winsize 62
743 13:31:37.431150 [CA 3] Center 35 (5~66) winsize 62
744 13:31:37.434280 [CA 4] Center 34 (4~65) winsize 62
745 13:31:37.437898 [CA 5] Center 33 (3~64) winsize 62
746 13:31:37.437983
747 13:31:37.441075 [CmdBusTrainingLP45] Vref(ca) range 1: 34
748 13:31:37.441173
749 13:31:37.444311 [CATrainingPosCal] consider 2 rank data
750 13:31:37.447360 u2DelayCellTimex100 = 270/100 ps
751 13:31:37.450989 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
752 13:31:37.454524 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
753 13:31:37.460899 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
754 13:31:37.464428 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
755 13:31:37.467882 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
756 13:31:37.471429 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
757 13:31:37.471512
758 13:31:37.474647 CA PerBit enable=1, Macro0, CA PI delay=34
759 13:31:37.474730
760 13:31:37.477893 [CBTSetCACLKResult] CA Dly = 34
761 13:31:37.477975 CS Dly: 6 (0~37)
762 13:31:37.478042
763 13:31:37.481189 ----->DramcWriteLeveling(PI) begin...
764 13:31:37.481305 ==
765 13:31:37.484571 Dram Type= 6, Freq= 0, CH_0, rank 0
766 13:31:37.490936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 13:31:37.491019 ==
768 13:31:37.494714 Write leveling (Byte 0): 32 => 32
769 13:31:37.497822 Write leveling (Byte 1): 31 => 31
770 13:31:37.497905 DramcWriteLeveling(PI) end<-----
771 13:31:37.500897
772 13:31:37.500980 ==
773 13:31:37.504717 Dram Type= 6, Freq= 0, CH_0, rank 0
774 13:31:37.507527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 13:31:37.507639 ==
776 13:31:37.511338 [Gating] SW mode calibration
777 13:31:37.517582 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 13:31:37.520899 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 13:31:37.527898 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 13:31:37.531068 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
781 13:31:37.534378 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
782 13:31:37.541164 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
783 13:31:37.544301 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 13:31:37.547524 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 13:31:37.554078 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 13:31:37.557394 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 13:31:37.561153 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 13:31:37.564754 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 13:31:37.572033 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 13:31:37.576063 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 13:31:37.579512 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 13:31:37.582713 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 13:31:37.589748 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 13:31:37.593651 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 13:31:37.596886 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 13:31:37.600093 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 13:31:37.606976 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
798 13:31:37.610140 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
799 13:31:37.613843 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 13:31:37.620160 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 13:31:37.623385 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 13:31:37.627135 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 13:31:37.633795 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 13:31:37.636999 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 13:31:37.640229 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
806 13:31:37.646768 0 9 12 | B1->B0 | 2323 3030 | 1 1 | (1 1) (1 1)
807 13:31:37.650575 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 13:31:37.653745 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 13:31:37.660194 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 13:31:37.663513 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 13:31:37.666749 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 13:31:37.670002 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 13:31:37.676872 0 10 8 | B1->B0 | 3434 3131 | 1 0 | (1 0) (1 0)
814 13:31:37.680241 0 10 12 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
815 13:31:37.683411 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 13:31:37.690443 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 13:31:37.693480 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 13:31:37.696853 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 13:31:37.703579 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 13:31:37.707005 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 13:31:37.710068 0 11 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
822 13:31:37.716988 0 11 12 | B1->B0 | 3030 4343 | 0 1 | (0 0) (1 1)
823 13:31:37.720158 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 13:31:37.723284 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 13:31:37.730333 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 13:31:37.733597 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 13:31:37.736877 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 13:31:37.743339 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 13:31:37.747209 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
830 13:31:37.750330 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
831 13:31:37.753399 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 13:31:37.760327 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 13:31:37.763506 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 13:31:37.766794 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 13:31:37.773739 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 13:31:37.777006 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 13:31:37.780179 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 13:31:37.787287 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 13:31:37.790616 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 13:31:37.793867 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 13:31:37.800373 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 13:31:37.803579 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 13:31:37.807157 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 13:31:37.813647 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 13:31:37.817124 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
846 13:31:37.820563 Total UI for P1: 0, mck2ui 16
847 13:31:37.824011 best dqsien dly found for B0: ( 0, 14, 6)
848 13:31:37.827201 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
849 13:31:37.834045 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 13:31:37.834136 Total UI for P1: 0, mck2ui 16
851 13:31:37.836982 best dqsien dly found for B1: ( 0, 14, 10)
852 13:31:37.843241 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
853 13:31:37.846532 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
854 13:31:37.846614
855 13:31:37.850411 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
856 13:31:37.853702 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
857 13:31:37.856832 [Gating] SW calibration Done
858 13:31:37.856914 ==
859 13:31:37.859837 Dram Type= 6, Freq= 0, CH_0, rank 0
860 13:31:37.863517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
861 13:31:37.863615 ==
862 13:31:37.866534 RX Vref Scan: 0
863 13:31:37.866616
864 13:31:37.866681 RX Vref 0 -> 0, step: 1
865 13:31:37.866741
866 13:31:37.869686 RX Delay -130 -> 252, step: 16
867 13:31:37.873582 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
868 13:31:37.879822 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
869 13:31:37.883019 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
870 13:31:37.886788 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
871 13:31:37.889941 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
872 13:31:37.893148 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
873 13:31:37.900158 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
874 13:31:37.903351 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
875 13:31:37.906536 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
876 13:31:37.909669 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
877 13:31:37.913402 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
878 13:31:37.919776 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
879 13:31:37.922958 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
880 13:31:37.926855 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
881 13:31:37.929937 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
882 13:31:37.932989 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
883 13:31:37.936521 ==
884 13:31:37.939892 Dram Type= 6, Freq= 0, CH_0, rank 0
885 13:31:37.943421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
886 13:31:37.943535 ==
887 13:31:37.943601 DQS Delay:
888 13:31:37.946396 DQS0 = 0, DQS1 = 0
889 13:31:37.946477 DQM Delay:
890 13:31:37.949932 DQM0 = 81, DQM1 = 70
891 13:31:37.950014 DQ Delay:
892 13:31:37.953421 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
893 13:31:37.956739 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
894 13:31:37.960011 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
895 13:31:37.963150 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
896 13:31:37.963231
897 13:31:37.963295
898 13:31:37.963354 ==
899 13:31:37.966916 Dram Type= 6, Freq= 0, CH_0, rank 0
900 13:31:37.969981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
901 13:31:37.970066 ==
902 13:31:37.970132
903 13:31:37.970194
904 13:31:37.973934 TX Vref Scan disable
905 13:31:37.974017 == TX Byte 0 ==
906 13:31:37.980329 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
907 13:31:37.983505 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
908 13:31:37.983588 == TX Byte 1 ==
909 13:31:37.989974 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
910 13:31:37.993698 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
911 13:31:37.993797 ==
912 13:31:37.996972 Dram Type= 6, Freq= 0, CH_0, rank 0
913 13:31:38.000228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 13:31:38.000311 ==
915 13:31:38.014376 TX Vref=22, minBit 2, minWin=26, winSum=428
916 13:31:38.017477 TX Vref=24, minBit 14, minWin=26, winSum=439
917 13:31:38.020773 TX Vref=26, minBit 4, minWin=27, winSum=441
918 13:31:38.024579 TX Vref=28, minBit 12, minWin=26, winSum=441
919 13:31:38.027768 TX Vref=30, minBit 12, minWin=26, winSum=440
920 13:31:38.034183 TX Vref=32, minBit 10, minWin=26, winSum=439
921 13:31:38.037472 [TxChooseVref] Worse bit 4, Min win 27, Win sum 441, Final Vref 26
922 13:31:38.037555
923 13:31:38.040624 Final TX Range 1 Vref 26
924 13:31:38.040707
925 13:31:38.040803 ==
926 13:31:38.044360 Dram Type= 6, Freq= 0, CH_0, rank 0
927 13:31:38.047498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 13:31:38.050710 ==
929 13:31:38.050792
930 13:31:38.050856
931 13:31:38.050916 TX Vref Scan disable
932 13:31:38.054608 == TX Byte 0 ==
933 13:31:38.057865 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
934 13:31:38.060868 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
935 13:31:38.064626 == TX Byte 1 ==
936 13:31:38.067613 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
937 13:31:38.074122 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
938 13:31:38.074223
939 13:31:38.074303 [DATLAT]
940 13:31:38.074381 Freq=800, CH0 RK0
941 13:31:38.074501
942 13:31:38.077577 DATLAT Default: 0xa
943 13:31:38.077665 0, 0xFFFF, sum = 0
944 13:31:38.081120 1, 0xFFFF, sum = 0
945 13:31:38.081206 2, 0xFFFF, sum = 0
946 13:31:38.084544 3, 0xFFFF, sum = 0
947 13:31:38.084627 4, 0xFFFF, sum = 0
948 13:31:38.087792 5, 0xFFFF, sum = 0
949 13:31:38.090862 6, 0xFFFF, sum = 0
950 13:31:38.090944 7, 0xFFFF, sum = 0
951 13:31:38.094687 8, 0xFFFF, sum = 0
952 13:31:38.094771 9, 0x0, sum = 1
953 13:31:38.094867 10, 0x0, sum = 2
954 13:31:38.097959 11, 0x0, sum = 3
955 13:31:38.098057 12, 0x0, sum = 4
956 13:31:38.101067 best_step = 10
957 13:31:38.101162
958 13:31:38.101257 ==
959 13:31:38.104244 Dram Type= 6, Freq= 0, CH_0, rank 0
960 13:31:38.107404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
961 13:31:38.107498 ==
962 13:31:38.111269 RX Vref Scan: 1
963 13:31:38.111358
964 13:31:38.111451 Set Vref Range= 32 -> 127
965 13:31:38.111514
966 13:31:38.114452 RX Vref 32 -> 127, step: 1
967 13:31:38.114554
968 13:31:38.117645 RX Delay -111 -> 252, step: 8
969 13:31:38.117724
970 13:31:38.121222 Set Vref, RX VrefLevel [Byte0]: 32
971 13:31:38.124512 [Byte1]: 32
972 13:31:38.124596
973 13:31:38.127605 Set Vref, RX VrefLevel [Byte0]: 33
974 13:31:38.130851 [Byte1]: 33
975 13:31:38.134666
976 13:31:38.134754 Set Vref, RX VrefLevel [Byte0]: 34
977 13:31:38.138500 [Byte1]: 34
978 13:31:38.142388
979 13:31:38.142467 Set Vref, RX VrefLevel [Byte0]: 35
980 13:31:38.146188 [Byte1]: 35
981 13:31:38.150446
982 13:31:38.150532 Set Vref, RX VrefLevel [Byte0]: 36
983 13:31:38.153554 [Byte1]: 36
984 13:31:38.158061
985 13:31:38.158140 Set Vref, RX VrefLevel [Byte0]: 37
986 13:31:38.161270 [Byte1]: 37
987 13:31:38.165614
988 13:31:38.165694 Set Vref, RX VrefLevel [Byte0]: 38
989 13:31:38.168841 [Byte1]: 38
990 13:31:38.173381
991 13:31:38.173464 Set Vref, RX VrefLevel [Byte0]: 39
992 13:31:38.176445 [Byte1]: 39
993 13:31:38.180734
994 13:31:38.180820 Set Vref, RX VrefLevel [Byte0]: 40
995 13:31:38.183936 [Byte1]: 40
996 13:31:38.188672
997 13:31:38.188779 Set Vref, RX VrefLevel [Byte0]: 41
998 13:31:38.191890 [Byte1]: 41
999 13:31:38.196039
1000 13:31:38.196125 Set Vref, RX VrefLevel [Byte0]: 42
1001 13:31:38.199401 [Byte1]: 42
1002 13:31:38.203728
1003 13:31:38.203842 Set Vref, RX VrefLevel [Byte0]: 43
1004 13:31:38.207156 [Byte1]: 43
1005 13:31:38.211434
1006 13:31:38.211518 Set Vref, RX VrefLevel [Byte0]: 44
1007 13:31:38.214620 [Byte1]: 44
1008 13:31:38.219126
1009 13:31:38.219234 Set Vref, RX VrefLevel [Byte0]: 45
1010 13:31:38.222442 [Byte1]: 45
1011 13:31:38.226934
1012 13:31:38.227037 Set Vref, RX VrefLevel [Byte0]: 46
1013 13:31:38.230838 [Byte1]: 46
1014 13:31:38.234553
1015 13:31:38.234631 Set Vref, RX VrefLevel [Byte0]: 47
1016 13:31:38.238368 [Byte1]: 47
1017 13:31:38.242189
1018 13:31:38.242304 Set Vref, RX VrefLevel [Byte0]: 48
1019 13:31:38.245560 [Byte1]: 48
1020 13:31:38.250079
1021 13:31:38.250188 Set Vref, RX VrefLevel [Byte0]: 49
1022 13:31:38.253117 [Byte1]: 49
1023 13:31:38.257228
1024 13:31:38.257330 Set Vref, RX VrefLevel [Byte0]: 50
1025 13:31:38.260547 [Byte1]: 50
1026 13:31:38.264931
1027 13:31:38.265046 Set Vref, RX VrefLevel [Byte0]: 51
1028 13:31:38.268276 [Byte1]: 51
1029 13:31:38.272271
1030 13:31:38.272373 Set Vref, RX VrefLevel [Byte0]: 52
1031 13:31:38.276157 [Byte1]: 52
1032 13:31:38.280000
1033 13:31:38.280108 Set Vref, RX VrefLevel [Byte0]: 53
1034 13:31:38.283877 [Byte1]: 53
1035 13:31:38.287700
1036 13:31:38.287776 Set Vref, RX VrefLevel [Byte0]: 54
1037 13:31:38.291287 [Byte1]: 54
1038 13:31:38.295725
1039 13:31:38.295809 Set Vref, RX VrefLevel [Byte0]: 55
1040 13:31:38.299014 [Byte1]: 55
1041 13:31:38.302900
1042 13:31:38.302972 Set Vref, RX VrefLevel [Byte0]: 56
1043 13:31:38.306676 [Byte1]: 56
1044 13:31:38.310983
1045 13:31:38.311066 Set Vref, RX VrefLevel [Byte0]: 57
1046 13:31:38.313810 [Byte1]: 57
1047 13:31:38.318467
1048 13:31:38.318549 Set Vref, RX VrefLevel [Byte0]: 58
1049 13:31:38.321441 [Byte1]: 58
1050 13:31:38.326270
1051 13:31:38.326352 Set Vref, RX VrefLevel [Byte0]: 59
1052 13:31:38.329157 [Byte1]: 59
1053 13:31:38.333519
1054 13:31:38.333602 Set Vref, RX VrefLevel [Byte0]: 60
1055 13:31:38.337336 [Byte1]: 60
1056 13:31:38.341149
1057 13:31:38.341232 Set Vref, RX VrefLevel [Byte0]: 61
1058 13:31:38.344849 [Byte1]: 61
1059 13:31:38.348736
1060 13:31:38.348819 Set Vref, RX VrefLevel [Byte0]: 62
1061 13:31:38.352597 [Byte1]: 62
1062 13:31:38.356951
1063 13:31:38.357034 Set Vref, RX VrefLevel [Byte0]: 63
1064 13:31:38.360129 [Byte1]: 63
1065 13:31:38.364508
1066 13:31:38.364589 Set Vref, RX VrefLevel [Byte0]: 64
1067 13:31:38.367806 [Byte1]: 64
1068 13:31:38.372271
1069 13:31:38.372355 Set Vref, RX VrefLevel [Byte0]: 65
1070 13:31:38.375572 [Byte1]: 65
1071 13:31:38.379281
1072 13:31:38.379363 Set Vref, RX VrefLevel [Byte0]: 66
1073 13:31:38.383042 [Byte1]: 66
1074 13:31:38.387690
1075 13:31:38.387787 Set Vref, RX VrefLevel [Byte0]: 67
1076 13:31:38.390697 [Byte1]: 67
1077 13:31:38.394536
1078 13:31:38.394690 Set Vref, RX VrefLevel [Byte0]: 68
1079 13:31:38.398361 [Byte1]: 68
1080 13:31:38.402742
1081 13:31:38.402837 Set Vref, RX VrefLevel [Byte0]: 69
1082 13:31:38.405871 [Byte1]: 69
1083 13:31:38.410460
1084 13:31:38.410541 Set Vref, RX VrefLevel [Byte0]: 70
1085 13:31:38.413650 [Byte1]: 70
1086 13:31:38.417979
1087 13:31:38.418074 Set Vref, RX VrefLevel [Byte0]: 71
1088 13:31:38.421068 [Byte1]: 71
1089 13:31:38.425611
1090 13:31:38.425691 Set Vref, RX VrefLevel [Byte0]: 72
1091 13:31:38.428673 [Byte1]: 72
1092 13:31:38.433100
1093 13:31:38.433181 Set Vref, RX VrefLevel [Byte0]: 73
1094 13:31:38.436131 [Byte1]: 73
1095 13:31:38.440685
1096 13:31:38.440770 Set Vref, RX VrefLevel [Byte0]: 74
1097 13:31:38.443973 [Byte1]: 74
1098 13:31:38.448077
1099 13:31:38.448196 Set Vref, RX VrefLevel [Byte0]: 75
1100 13:31:38.451616 [Byte1]: 75
1101 13:31:38.456002
1102 13:31:38.456083 Set Vref, RX VrefLevel [Byte0]: 76
1103 13:31:38.459208 [Byte1]: 76
1104 13:31:38.463340
1105 13:31:38.463443 Set Vref, RX VrefLevel [Byte0]: 77
1106 13:31:38.467177 [Byte1]: 77
1107 13:31:38.471074
1108 13:31:38.471183 Set Vref, RX VrefLevel [Byte0]: 78
1109 13:31:38.474898 [Byte1]: 78
1110 13:31:38.478872
1111 13:31:38.478953 Set Vref, RX VrefLevel [Byte0]: 79
1112 13:31:38.482076 [Byte1]: 79
1113 13:31:38.486747
1114 13:31:38.486830 Final RX Vref Byte 0 = 63 to rank0
1115 13:31:38.489878 Final RX Vref Byte 1 = 57 to rank0
1116 13:31:38.493091 Final RX Vref Byte 0 = 63 to rank1
1117 13:31:38.496168 Final RX Vref Byte 1 = 57 to rank1==
1118 13:31:38.500033 Dram Type= 6, Freq= 0, CH_0, rank 0
1119 13:31:38.506231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1120 13:31:38.506315 ==
1121 13:31:38.506381 DQS Delay:
1122 13:31:38.506442 DQS0 = 0, DQS1 = 0
1123 13:31:38.510126 DQM Delay:
1124 13:31:38.510209 DQM0 = 81, DQM1 = 67
1125 13:31:38.513395 DQ Delay:
1126 13:31:38.516651 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1127 13:31:38.516734 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1128 13:31:38.519747 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1129 13:31:38.526633 DQ12 =72, DQ13 =72, DQ14 =76, DQ15 =76
1130 13:31:38.526731
1131 13:31:38.526835
1132 13:31:38.532991 [DQSOSCAuto] RK0, (LSB)MR18= 0x2726, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1133 13:31:38.536565 CH0 RK0: MR19=606, MR18=2726
1134 13:31:38.543067 CH0_RK0: MR19=0x606, MR18=0x2726, DQSOSC=400, MR23=63, INC=92, DEC=61
1135 13:31:38.543151
1136 13:31:38.546401 ----->DramcWriteLeveling(PI) begin...
1137 13:31:38.546485 ==
1138 13:31:38.549625 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 13:31:38.553137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 13:31:38.553221 ==
1141 13:31:38.556095 Write leveling (Byte 0): 29 => 29
1142 13:31:38.559786 Write leveling (Byte 1): 30 => 30
1143 13:31:38.563194 DramcWriteLeveling(PI) end<-----
1144 13:31:38.563275
1145 13:31:38.563339 ==
1146 13:31:38.566484 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 13:31:38.569740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 13:31:38.569821 ==
1149 13:31:38.572697 [Gating] SW mode calibration
1150 13:31:38.579403 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1151 13:31:38.586250 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1152 13:31:38.589451 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 13:31:38.592760 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1154 13:31:38.599966 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1155 13:31:38.603215 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 13:31:38.606243 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 13:31:38.613134 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 13:31:38.616348 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 13:31:38.619578 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 13:31:38.626568 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 13:31:38.629581 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 13:31:38.633282 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 13:31:38.639708 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 13:31:38.642797 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 13:31:38.686922 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 13:31:38.687269 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 13:31:38.687344 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 13:31:38.687436 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 13:31:38.687496 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 13:31:38.687617 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1171 13:31:38.687691 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1172 13:31:38.687748 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 13:31:38.687803 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 13:31:38.687869 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 13:31:38.709277 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 13:31:38.709737 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 13:31:38.709819 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 13:31:38.709883 0 9 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1179 13:31:38.709944 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1180 13:31:38.712973 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 13:31:38.716235 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 13:31:38.723030 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 13:31:38.726196 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 13:31:38.729510 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 13:31:38.736557 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
1186 13:31:38.739712 0 10 8 | B1->B0 | 3232 2d2d | 1 0 | (1 0) (0 0)
1187 13:31:38.742916 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1188 13:31:38.746245 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 13:31:38.753375 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 13:31:38.756578 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 13:31:38.759908 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 13:31:38.766323 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 13:31:38.769541 0 11 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1194 13:31:38.773433 0 11 8 | B1->B0 | 2b2b 3737 | 0 0 | (1 1) (0 0)
1195 13:31:38.779834 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 13:31:38.782986 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 13:31:38.786229 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 13:31:38.792882 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 13:31:38.796009 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 13:31:38.799816 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 13:31:38.806276 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 13:31:38.809774 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1203 13:31:38.813747 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 13:31:38.817052 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 13:31:38.823957 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 13:31:38.826981 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 13:31:38.831425 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 13:31:38.834579 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 13:31:38.841412 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 13:31:38.844692 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 13:31:38.847903 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 13:31:38.854461 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 13:31:38.857652 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 13:31:38.861345 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 13:31:38.868300 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 13:31:38.871630 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 13:31:38.874297 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 13:31:38.881431 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1219 13:31:38.881513 Total UI for P1: 0, mck2ui 16
1220 13:31:38.887863 best dqsien dly found for B0: ( 0, 14, 6)
1221 13:31:38.891126 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1222 13:31:38.894463 Total UI for P1: 0, mck2ui 16
1223 13:31:38.897655 best dqsien dly found for B1: ( 0, 14, 8)
1224 13:31:38.901213 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1225 13:31:38.904409 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1226 13:31:38.904491
1227 13:31:38.907676 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1228 13:31:38.910877 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1229 13:31:38.914107 [Gating] SW calibration Done
1230 13:31:38.914187 ==
1231 13:31:38.917833 Dram Type= 6, Freq= 0, CH_0, rank 1
1232 13:31:38.920750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1233 13:31:38.920849 ==
1234 13:31:38.924205 RX Vref Scan: 0
1235 13:31:38.924287
1236 13:31:38.927525 RX Vref 0 -> 0, step: 1
1237 13:31:38.927610
1238 13:31:38.927675 RX Delay -130 -> 252, step: 16
1239 13:31:38.934511 iDelay=222, Bit 0, Center 69 (-50 ~ 189) 240
1240 13:31:38.937588 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1241 13:31:38.941051 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1242 13:31:38.944482 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1243 13:31:38.947548 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1244 13:31:38.954552 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1245 13:31:38.957713 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1246 13:31:38.960900 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1247 13:31:38.964108 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1248 13:31:38.967808 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1249 13:31:38.974499 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1250 13:31:38.977702 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1251 13:31:38.980948 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1252 13:31:38.984155 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1253 13:31:38.988038 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1254 13:31:38.994703 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1255 13:31:38.994800 ==
1256 13:31:38.997824 Dram Type= 6, Freq= 0, CH_0, rank 1
1257 13:31:39.001002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1258 13:31:39.001084 ==
1259 13:31:39.001149 DQS Delay:
1260 13:31:39.004179 DQS0 = 0, DQS1 = 0
1261 13:31:39.004260 DQM Delay:
1262 13:31:39.007792 DQM0 = 76, DQM1 = 69
1263 13:31:39.007873 DQ Delay:
1264 13:31:39.010899 DQ0 =69, DQ1 =77, DQ2 =69, DQ3 =69
1265 13:31:39.014078 DQ4 =77, DQ5 =69, DQ6 =85, DQ7 =93
1266 13:31:39.017471 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1267 13:31:39.020753 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1268 13:31:39.020834
1269 13:31:39.020898
1270 13:31:39.020958 ==
1271 13:31:39.024618 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 13:31:39.027851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 13:31:39.027934 ==
1274 13:31:39.030875
1275 13:31:39.030955
1276 13:31:39.031020 TX Vref Scan disable
1277 13:31:39.034005 == TX Byte 0 ==
1278 13:31:39.037739 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1279 13:31:39.040888 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1280 13:31:39.044069 == TX Byte 1 ==
1281 13:31:39.047254 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1282 13:31:39.050977 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1283 13:31:39.051058 ==
1284 13:31:39.053873 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 13:31:39.060882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 13:31:39.061000 ==
1287 13:31:39.072598 TX Vref=22, minBit 1, minWin=26, winSum=434
1288 13:31:39.075600 TX Vref=24, minBit 11, minWin=26, winSum=440
1289 13:31:39.079032 TX Vref=26, minBit 0, minWin=27, winSum=441
1290 13:31:39.082916 TX Vref=28, minBit 9, minWin=27, winSum=445
1291 13:31:39.086163 TX Vref=30, minBit 11, minWin=26, winSum=443
1292 13:31:39.089429 TX Vref=32, minBit 8, minWin=27, winSum=444
1293 13:31:39.095881 [TxChooseVref] Worse bit 9, Min win 27, Win sum 445, Final Vref 28
1294 13:31:39.095969
1295 13:31:39.099107 Final TX Range 1 Vref 28
1296 13:31:39.099189
1297 13:31:39.099254 ==
1298 13:31:39.102379 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 13:31:39.106454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 13:31:39.106535 ==
1301 13:31:39.106632
1302 13:31:39.109556
1303 13:31:39.109637 TX Vref Scan disable
1304 13:31:39.112733 == TX Byte 0 ==
1305 13:31:39.115813 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1306 13:31:39.119419 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1307 13:31:39.122667 == TX Byte 1 ==
1308 13:31:39.125947 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1309 13:31:39.129130 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1310 13:31:39.132370
1311 13:31:39.132449 [DATLAT]
1312 13:31:39.132512 Freq=800, CH0 RK1
1313 13:31:39.132620
1314 13:31:39.135669 DATLAT Default: 0xa
1315 13:31:39.135749 0, 0xFFFF, sum = 0
1316 13:31:39.138931 1, 0xFFFF, sum = 0
1317 13:31:39.139026 2, 0xFFFF, sum = 0
1318 13:31:39.142620 3, 0xFFFF, sum = 0
1319 13:31:39.142708 4, 0xFFFF, sum = 0
1320 13:31:39.145481 5, 0xFFFF, sum = 0
1321 13:31:39.149311 6, 0xFFFF, sum = 0
1322 13:31:39.149392 7, 0xFFFF, sum = 0
1323 13:31:39.152514 8, 0xFFFF, sum = 0
1324 13:31:39.152611 9, 0x0, sum = 1
1325 13:31:39.152698 10, 0x0, sum = 2
1326 13:31:39.155783 11, 0x0, sum = 3
1327 13:31:39.155864 12, 0x0, sum = 4
1328 13:31:39.158949 best_step = 10
1329 13:31:39.159028
1330 13:31:39.159090 ==
1331 13:31:39.162632 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 13:31:39.165676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 13:31:39.165759 ==
1334 13:31:39.168876 RX Vref Scan: 0
1335 13:31:39.168972
1336 13:31:39.169068 RX Vref 0 -> 0, step: 1
1337 13:31:39.169133
1338 13:31:39.172385 RX Delay -111 -> 252, step: 8
1339 13:31:39.179110 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1340 13:31:39.182305 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1341 13:31:39.186108 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1342 13:31:39.189088 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
1343 13:31:39.192658 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1344 13:31:39.199113 iDelay=209, Bit 5, Center 64 (-47 ~ 176) 224
1345 13:31:39.202390 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1346 13:31:39.205717 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1347 13:31:39.209517 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1348 13:31:39.212902 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1349 13:31:39.218976 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1350 13:31:39.222598 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1351 13:31:39.225766 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1352 13:31:39.229034 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1353 13:31:39.235610 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1354 13:31:39.238884 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1355 13:31:39.238972 ==
1356 13:31:39.242160 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 13:31:39.246019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 13:31:39.246105 ==
1359 13:31:39.246172 DQS Delay:
1360 13:31:39.249046 DQS0 = 0, DQS1 = 0
1361 13:31:39.249134 DQM Delay:
1362 13:31:39.252497 DQM0 = 79, DQM1 = 70
1363 13:31:39.252596 DQ Delay:
1364 13:31:39.255967 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =76
1365 13:31:39.258888 DQ4 =76, DQ5 =64, DQ6 =92, DQ7 =92
1366 13:31:39.262733 DQ8 =60, DQ9 =56, DQ10 =72, DQ11 =64
1367 13:31:39.265890 DQ12 =80, DQ13 =76, DQ14 =80, DQ15 =76
1368 13:31:39.265970
1369 13:31:39.266033
1370 13:31:39.275982 [DQSOSCAuto] RK1, (LSB)MR18= 0x421d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
1371 13:31:39.276091 CH0 RK1: MR19=606, MR18=421D
1372 13:31:39.282714 CH0_RK1: MR19=0x606, MR18=0x421D, DQSOSC=393, MR23=63, INC=95, DEC=63
1373 13:31:39.286133 [RxdqsGatingPostProcess] freq 800
1374 13:31:39.292719 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1375 13:31:39.295784 Pre-setting of DQS Precalculation
1376 13:31:39.299418 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1377 13:31:39.299515 ==
1378 13:31:39.302331 Dram Type= 6, Freq= 0, CH_1, rank 0
1379 13:31:39.306180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1380 13:31:39.306264 ==
1381 13:31:39.312598 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1382 13:31:39.319118 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1383 13:31:39.327555 [CA 0] Center 36 (6~66) winsize 61
1384 13:31:39.331138 [CA 1] Center 37 (7~67) winsize 61
1385 13:31:39.334279 [CA 2] Center 34 (4~64) winsize 61
1386 13:31:39.337842 [CA 3] Center 34 (4~64) winsize 61
1387 13:31:39.341120 [CA 4] Center 34 (4~64) winsize 61
1388 13:31:39.344358 [CA 5] Center 34 (4~64) winsize 61
1389 13:31:39.344439
1390 13:31:39.347607 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1391 13:31:39.347687
1392 13:31:39.350853 [CATrainingPosCal] consider 1 rank data
1393 13:31:39.353957 u2DelayCellTimex100 = 270/100 ps
1394 13:31:39.357721 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1395 13:31:39.360761 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1396 13:31:39.367220 CA2 delay=34 (4~64),Diff = 0 PI (0 cell)
1397 13:31:39.370766 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1398 13:31:39.373948 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1399 13:31:39.377165 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1400 13:31:39.377261
1401 13:31:39.380944 CA PerBit enable=1, Macro0, CA PI delay=34
1402 13:31:39.381025
1403 13:31:39.384106 [CBTSetCACLKResult] CA Dly = 34
1404 13:31:39.384187 CS Dly: 5 (0~36)
1405 13:31:39.387286 ==
1406 13:31:39.387368 Dram Type= 6, Freq= 0, CH_1, rank 1
1407 13:31:39.393982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 13:31:39.394063 ==
1409 13:31:39.397361 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1410 13:31:39.404160 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1411 13:31:39.413952 [CA 0] Center 37 (7~67) winsize 61
1412 13:31:39.417325 [CA 1] Center 37 (7~67) winsize 61
1413 13:31:39.420526 [CA 2] Center 34 (4~65) winsize 62
1414 13:31:39.423808 [CA 3] Center 34 (4~64) winsize 61
1415 13:31:39.426965 [CA 4] Center 34 (4~65) winsize 62
1416 13:31:39.430220 [CA 5] Center 33 (3~64) winsize 62
1417 13:31:39.430302
1418 13:31:39.433474 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1419 13:31:39.433555
1420 13:31:39.437283 [CATrainingPosCal] consider 2 rank data
1421 13:31:39.440501 u2DelayCellTimex100 = 270/100 ps
1422 13:31:39.444021 CA0 delay=36 (7~66),Diff = 2 PI (14 cell)
1423 13:31:39.447072 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1424 13:31:39.453467 CA2 delay=34 (4~64),Diff = 0 PI (0 cell)
1425 13:31:39.457479 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1426 13:31:39.460747 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1427 13:31:39.464601 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1428 13:31:39.464682
1429 13:31:39.468012 CA PerBit enable=1, Macro0, CA PI delay=34
1430 13:31:39.468095
1431 13:31:39.471853 [CBTSetCACLKResult] CA Dly = 34
1432 13:31:39.471934 CS Dly: 6 (0~38)
1433 13:31:39.472000
1434 13:31:39.475473 ----->DramcWriteLeveling(PI) begin...
1435 13:31:39.475556 ==
1436 13:31:39.479020 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 13:31:39.482719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 13:31:39.482802 ==
1439 13:31:39.486432 Write leveling (Byte 0): 28 => 28
1440 13:31:39.490217 Write leveling (Byte 1): 27 => 27
1441 13:31:39.493391 DramcWriteLeveling(PI) end<-----
1442 13:31:39.493472
1443 13:31:39.493536 ==
1444 13:31:39.497273 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 13:31:39.500504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 13:31:39.500586 ==
1447 13:31:39.504163 [Gating] SW mode calibration
1448 13:31:39.510626 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1449 13:31:39.513849 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1450 13:31:39.521122 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1451 13:31:39.524044 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1452 13:31:39.527738 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1453 13:31:39.534375 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 13:31:39.537557 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 13:31:39.540679 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 13:31:39.547682 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 13:31:39.550820 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 13:31:39.553849 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 13:31:39.557775 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 13:31:39.564298 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 13:31:39.567547 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 13:31:39.570825 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 13:31:39.577131 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 13:31:39.580788 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 13:31:39.583949 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 13:31:39.590652 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 13:31:39.594350 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1468 13:31:39.597596 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1469 13:31:39.603955 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 13:31:39.607146 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 13:31:39.610964 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 13:31:39.617551 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 13:31:39.620540 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 13:31:39.624420 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 13:31:39.630622 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 13:31:39.633759 0 9 8 | B1->B0 | 2929 2929 | 0 0 | (0 0) (0 0)
1477 13:31:39.637857 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 13:31:39.644199 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 13:31:39.647376 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 13:31:39.650632 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 13:31:39.657542 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 13:31:39.660716 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 13:31:39.663884 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 13:31:39.670332 0 10 8 | B1->B0 | 2e2e 2c2c | 1 1 | (1 1) (1 0)
1485 13:31:39.673550 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 13:31:39.676837 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 13:31:39.680789 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 13:31:39.686904 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 13:31:39.690837 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 13:31:39.693766 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 13:31:39.700430 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 13:31:39.703561 0 11 8 | B1->B0 | 3535 3c3c | 0 0 | (0 0) (1 1)
1493 13:31:39.707441 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 13:31:39.713972 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 13:31:39.717205 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 13:31:39.720459 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 13:31:39.727573 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 13:31:39.730598 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 13:31:39.733784 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1500 13:31:39.740829 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1501 13:31:39.744008 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 13:31:39.747230 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 13:31:39.753976 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 13:31:39.757542 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 13:31:39.760325 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 13:31:39.764031 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 13:31:39.770870 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 13:31:39.774085 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 13:31:39.777311 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 13:31:39.783752 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 13:31:39.787622 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 13:31:39.790654 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 13:31:39.797322 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 13:31:39.800530 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 13:31:39.804255 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1516 13:31:39.810905 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1517 13:31:39.814015 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1518 13:31:39.817229 Total UI for P1: 0, mck2ui 16
1519 13:31:39.820571 best dqsien dly found for B0: ( 0, 14, 8)
1520 13:31:39.823775 Total UI for P1: 0, mck2ui 16
1521 13:31:39.827795 best dqsien dly found for B1: ( 0, 14, 6)
1522 13:31:39.830990 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1523 13:31:39.834117 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1524 13:31:39.834200
1525 13:31:39.837702 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1526 13:31:39.840496 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1527 13:31:39.844093 [Gating] SW calibration Done
1528 13:31:39.844213 ==
1529 13:31:39.847525 Dram Type= 6, Freq= 0, CH_1, rank 0
1530 13:31:39.850768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1531 13:31:39.850872 ==
1532 13:31:39.854015 RX Vref Scan: 0
1533 13:31:39.854120
1534 13:31:39.857581 RX Vref 0 -> 0, step: 1
1535 13:31:39.857686
1536 13:31:39.857787 RX Delay -130 -> 252, step: 16
1537 13:31:39.864110 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1538 13:31:39.867352 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1539 13:31:39.870356 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1540 13:31:39.874042 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1541 13:31:39.877092 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1542 13:31:39.883596 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1543 13:31:39.887063 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1544 13:31:39.890379 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1545 13:31:39.893414 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1546 13:31:39.896836 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1547 13:31:39.903503 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1548 13:31:39.906780 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1549 13:31:39.910495 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1550 13:31:39.913558 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1551 13:31:39.920701 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1552 13:31:39.923922 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1553 13:31:39.924000 ==
1554 13:31:39.927285 Dram Type= 6, Freq= 0, CH_1, rank 0
1555 13:31:39.930555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1556 13:31:39.930657 ==
1557 13:31:39.930751 DQS Delay:
1558 13:31:39.933959 DQS0 = 0, DQS1 = 0
1559 13:31:39.934057 DQM Delay:
1560 13:31:39.937208 DQM0 = 82, DQM1 = 76
1561 13:31:39.937308 DQ Delay:
1562 13:31:39.940378 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1563 13:31:39.943617 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1564 13:31:39.947152 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1565 13:31:39.950144 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1566 13:31:39.950243
1567 13:31:39.950333
1568 13:31:39.950419 ==
1569 13:31:39.953549 Dram Type= 6, Freq= 0, CH_1, rank 0
1570 13:31:39.957122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1571 13:31:39.960211 ==
1572 13:31:39.960318
1573 13:31:39.960411
1574 13:31:39.960500 TX Vref Scan disable
1575 13:31:39.963519 == TX Byte 0 ==
1576 13:31:39.966915 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1577 13:31:39.970254 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1578 13:31:39.973494 == TX Byte 1 ==
1579 13:31:39.977278 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1580 13:31:39.980198 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1581 13:31:39.980300 ==
1582 13:31:39.983668 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 13:31:39.990302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1584 13:31:39.990409 ==
1585 13:31:40.002711 TX Vref=22, minBit 0, minWin=27, winSum=441
1586 13:31:40.005994 TX Vref=24, minBit 1, minWin=27, winSum=445
1587 13:31:40.009305 TX Vref=26, minBit 1, minWin=27, winSum=446
1588 13:31:40.012423 TX Vref=28, minBit 5, minWin=27, winSum=450
1589 13:31:40.015541 TX Vref=30, minBit 5, minWin=27, winSum=449
1590 13:31:40.019189 TX Vref=32, minBit 0, minWin=27, winSum=446
1591 13:31:40.025541 [TxChooseVref] Worse bit 5, Min win 27, Win sum 450, Final Vref 28
1592 13:31:40.025651
1593 13:31:40.028775 Final TX Range 1 Vref 28
1594 13:31:40.028882
1595 13:31:40.028974 ==
1596 13:31:40.032727 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 13:31:40.035976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 13:31:40.036085 ==
1599 13:31:40.036183
1600 13:31:40.039232
1601 13:31:40.039334 TX Vref Scan disable
1602 13:31:40.042495 == TX Byte 0 ==
1603 13:31:40.045952 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1604 13:31:40.049320 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1605 13:31:40.052621 == TX Byte 1 ==
1606 13:31:40.056318 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1607 13:31:40.059308 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1608 13:31:40.059418
1609 13:31:40.062922 [DATLAT]
1610 13:31:40.063022 Freq=800, CH1 RK0
1611 13:31:40.063113
1612 13:31:40.066570 DATLAT Default: 0xa
1613 13:31:40.066672 0, 0xFFFF, sum = 0
1614 13:31:40.069653 1, 0xFFFF, sum = 0
1615 13:31:40.069777 2, 0xFFFF, sum = 0
1616 13:31:40.072787 3, 0xFFFF, sum = 0
1617 13:31:40.072905 4, 0xFFFF, sum = 0
1618 13:31:40.076702 5, 0xFFFF, sum = 0
1619 13:31:40.076786 6, 0xFFFF, sum = 0
1620 13:31:40.079869 7, 0xFFFF, sum = 0
1621 13:31:40.079953 8, 0xFFFF, sum = 0
1622 13:31:40.083089 9, 0x0, sum = 1
1623 13:31:40.083173 10, 0x0, sum = 2
1624 13:31:40.086340 11, 0x0, sum = 3
1625 13:31:40.086424 12, 0x0, sum = 4
1626 13:31:40.089572 best_step = 10
1627 13:31:40.089655
1628 13:31:40.089721 ==
1629 13:31:40.093093 Dram Type= 6, Freq= 0, CH_1, rank 0
1630 13:31:40.095954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1631 13:31:40.096039 ==
1632 13:31:40.096105 RX Vref Scan: 1
1633 13:31:40.099442
1634 13:31:40.099524 Set Vref Range= 32 -> 127
1635 13:31:40.099589
1636 13:31:40.103020 RX Vref 32 -> 127, step: 1
1637 13:31:40.103103
1638 13:31:40.105937 RX Delay -111 -> 252, step: 8
1639 13:31:40.106060
1640 13:31:40.109909 Set Vref, RX VrefLevel [Byte0]: 32
1641 13:31:40.112678 [Byte1]: 32
1642 13:31:40.112789
1643 13:31:40.116436 Set Vref, RX VrefLevel [Byte0]: 33
1644 13:31:40.119584 [Byte1]: 33
1645 13:31:40.122573
1646 13:31:40.122657 Set Vref, RX VrefLevel [Byte0]: 34
1647 13:31:40.125871 [Byte1]: 34
1648 13:31:40.130296
1649 13:31:40.130393 Set Vref, RX VrefLevel [Byte0]: 35
1650 13:31:40.133488 [Byte1]: 35
1651 13:31:40.138037
1652 13:31:40.138138 Set Vref, RX VrefLevel [Byte0]: 36
1653 13:31:40.141368 [Byte1]: 36
1654 13:31:40.145926
1655 13:31:40.146009 Set Vref, RX VrefLevel [Byte0]: 37
1656 13:31:40.149106 [Byte1]: 37
1657 13:31:40.153048
1658 13:31:40.153130 Set Vref, RX VrefLevel [Byte0]: 38
1659 13:31:40.156293 [Byte1]: 38
1660 13:31:40.160913
1661 13:31:40.160995 Set Vref, RX VrefLevel [Byte0]: 39
1662 13:31:40.164021 [Byte1]: 39
1663 13:31:40.168377
1664 13:31:40.168461 Set Vref, RX VrefLevel [Byte0]: 40
1665 13:31:40.172033 [Byte1]: 40
1666 13:31:40.176337
1667 13:31:40.176419 Set Vref, RX VrefLevel [Byte0]: 41
1668 13:31:40.179385 [Byte1]: 41
1669 13:31:40.184117
1670 13:31:40.184199 Set Vref, RX VrefLevel [Byte0]: 42
1671 13:31:40.187452 [Byte1]: 42
1672 13:31:40.191305
1673 13:31:40.191416 Set Vref, RX VrefLevel [Byte0]: 43
1674 13:31:40.194612 [Byte1]: 43
1675 13:31:40.199132
1676 13:31:40.199243 Set Vref, RX VrefLevel [Byte0]: 44
1677 13:31:40.202614 [Byte1]: 44
1678 13:31:40.206979
1679 13:31:40.207062 Set Vref, RX VrefLevel [Byte0]: 45
1680 13:31:40.209930 [Byte1]: 45
1681 13:31:40.214449
1682 13:31:40.214532 Set Vref, RX VrefLevel [Byte0]: 46
1683 13:31:40.217672 [Byte1]: 46
1684 13:31:40.222201
1685 13:31:40.222284 Set Vref, RX VrefLevel [Byte0]: 47
1686 13:31:40.225340 [Byte1]: 47
1687 13:31:40.229827
1688 13:31:40.229908 Set Vref, RX VrefLevel [Byte0]: 48
1689 13:31:40.233219 [Byte1]: 48
1690 13:31:40.237588
1691 13:31:40.237671 Set Vref, RX VrefLevel [Byte0]: 49
1692 13:31:40.240783 [Byte1]: 49
1693 13:31:40.244830
1694 13:31:40.244912 Set Vref, RX VrefLevel [Byte0]: 50
1695 13:31:40.248077 [Byte1]: 50
1696 13:31:40.252560
1697 13:31:40.252642 Set Vref, RX VrefLevel [Byte0]: 51
1698 13:31:40.256382 [Byte1]: 51
1699 13:31:40.260180
1700 13:31:40.260262 Set Vref, RX VrefLevel [Byte0]: 52
1701 13:31:40.263434 [Byte1]: 52
1702 13:31:40.268032
1703 13:31:40.268114 Set Vref, RX VrefLevel [Byte0]: 53
1704 13:31:40.271095 [Byte1]: 53
1705 13:31:40.275410
1706 13:31:40.275494 Set Vref, RX VrefLevel [Byte0]: 54
1707 13:31:40.279064 [Byte1]: 54
1708 13:31:40.282994
1709 13:31:40.283076 Set Vref, RX VrefLevel [Byte0]: 55
1710 13:31:40.286776 [Byte1]: 55
1711 13:31:40.291061
1712 13:31:40.291144 Set Vref, RX VrefLevel [Byte0]: 56
1713 13:31:40.297543 [Byte1]: 56
1714 13:31:40.297629
1715 13:31:40.300922 Set Vref, RX VrefLevel [Byte0]: 57
1716 13:31:40.304178 [Byte1]: 57
1717 13:31:40.304262
1718 13:31:40.307477 Set Vref, RX VrefLevel [Byte0]: 58
1719 13:31:40.310779 [Byte1]: 58
1720 13:31:40.314197
1721 13:31:40.314279 Set Vref, RX VrefLevel [Byte0]: 59
1722 13:31:40.317460 [Byte1]: 59
1723 13:31:40.321648
1724 13:31:40.321730 Set Vref, RX VrefLevel [Byte0]: 60
1725 13:31:40.324602 [Byte1]: 60
1726 13:31:40.329201
1727 13:31:40.329283 Set Vref, RX VrefLevel [Byte0]: 61
1728 13:31:40.332381 [Byte1]: 61
1729 13:31:40.336561
1730 13:31:40.336671 Set Vref, RX VrefLevel [Byte0]: 62
1731 13:31:40.340369 [Byte1]: 62
1732 13:31:40.344280
1733 13:31:40.344362 Set Vref, RX VrefLevel [Byte0]: 63
1734 13:31:40.347644 [Byte1]: 63
1735 13:31:40.352407
1736 13:31:40.352516 Set Vref, RX VrefLevel [Byte0]: 64
1737 13:31:40.355670 [Byte1]: 64
1738 13:31:40.359662
1739 13:31:40.359766 Set Vref, RX VrefLevel [Byte0]: 65
1740 13:31:40.362996 [Byte1]: 65
1741 13:31:40.367661
1742 13:31:40.367762 Set Vref, RX VrefLevel [Byte0]: 66
1743 13:31:40.370372 [Byte1]: 66
1744 13:31:40.374931
1745 13:31:40.375031 Set Vref, RX VrefLevel [Byte0]: 67
1746 13:31:40.378191 [Byte1]: 67
1747 13:31:40.382525
1748 13:31:40.382632 Set Vref, RX VrefLevel [Byte0]: 68
1749 13:31:40.385832 [Byte1]: 68
1750 13:31:40.390495
1751 13:31:40.390602 Set Vref, RX VrefLevel [Byte0]: 69
1752 13:31:40.393718 [Byte1]: 69
1753 13:31:40.398033
1754 13:31:40.398140 Set Vref, RX VrefLevel [Byte0]: 70
1755 13:31:40.401097 [Byte1]: 70
1756 13:31:40.405546
1757 13:31:40.405652 Set Vref, RX VrefLevel [Byte0]: 71
1758 13:31:40.408943 [Byte1]: 71
1759 13:31:40.413439
1760 13:31:40.413521 Set Vref, RX VrefLevel [Byte0]: 72
1761 13:31:40.416644 [Byte1]: 72
1762 13:31:40.421236
1763 13:31:40.421337 Set Vref, RX VrefLevel [Byte0]: 73
1764 13:31:40.424496 [Byte1]: 73
1765 13:31:40.428640
1766 13:31:40.428741 Set Vref, RX VrefLevel [Byte0]: 74
1767 13:31:40.431723 [Byte1]: 74
1768 13:31:40.436432
1769 13:31:40.436537 Final RX Vref Byte 0 = 59 to rank0
1770 13:31:40.439553 Final RX Vref Byte 1 = 57 to rank0
1771 13:31:40.442726 Final RX Vref Byte 0 = 59 to rank1
1772 13:31:40.446454 Final RX Vref Byte 1 = 57 to rank1==
1773 13:31:40.449744 Dram Type= 6, Freq= 0, CH_1, rank 0
1774 13:31:40.456322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1775 13:31:40.456429 ==
1776 13:31:40.456527 DQS Delay:
1777 13:31:40.456623 DQS0 = 0, DQS1 = 0
1778 13:31:40.459454 DQM Delay:
1779 13:31:40.459552 DQM0 = 81, DQM1 = 71
1780 13:31:40.462759 DQ Delay:
1781 13:31:40.466076 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1782 13:31:40.469527 DQ4 =76, DQ5 =92, DQ6 =96, DQ7 =76
1783 13:31:40.472820 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1784 13:31:40.476063 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1785 13:31:40.476162
1786 13:31:40.476253
1787 13:31:40.482559 [DQSOSCAuto] RK0, (LSB)MR18= 0xc16, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 406 ps
1788 13:31:40.485741 CH1 RK0: MR19=606, MR18=C16
1789 13:31:40.492640 CH1_RK0: MR19=0x606, MR18=0xC16, DQSOSC=404, MR23=63, INC=90, DEC=60
1790 13:31:40.492744
1791 13:31:40.495921 ----->DramcWriteLeveling(PI) begin...
1792 13:31:40.495993 ==
1793 13:31:40.499214 Dram Type= 6, Freq= 0, CH_1, rank 1
1794 13:31:40.502365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1795 13:31:40.502448 ==
1796 13:31:40.506093 Write leveling (Byte 0): 27 => 27
1797 13:31:40.509478 Write leveling (Byte 1): 28 => 28
1798 13:31:40.512821 DramcWriteLeveling(PI) end<-----
1799 13:31:40.512896
1800 13:31:40.512962 ==
1801 13:31:40.515862 Dram Type= 6, Freq= 0, CH_1, rank 1
1802 13:31:40.519164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1803 13:31:40.519263 ==
1804 13:31:40.522450 [Gating] SW mode calibration
1805 13:31:40.529104 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1806 13:31:40.536072 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1807 13:31:40.539165 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1808 13:31:40.542380 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1809 13:31:40.549155 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1810 13:31:40.552611 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 13:31:40.556196 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 13:31:40.562627 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 13:31:40.565908 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 13:31:40.569287 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 13:31:40.575738 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 13:31:40.579002 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 13:31:40.582295 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 13:31:40.589538 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 13:31:40.592609 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 13:31:40.595847 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 13:31:40.602432 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 13:31:40.605723 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 13:31:40.609045 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1824 13:31:40.612271 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1825 13:31:40.618689 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1826 13:31:40.622311 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 13:31:40.626113 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 13:31:40.632561 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 13:31:40.635779 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 13:31:40.639082 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 13:31:40.645790 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 13:31:40.648937 0 9 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1833 13:31:40.652348 0 9 8 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
1834 13:31:40.658999 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 13:31:40.662582 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 13:31:40.665689 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 13:31:40.672272 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 13:31:40.675514 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 13:31:40.678825 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1840 13:31:40.685698 0 10 4 | B1->B0 | 3333 2d2d | 0 1 | (0 0) (1 0)
1841 13:31:40.689048 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1842 13:31:40.692377 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 13:31:40.698911 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 13:31:40.702138 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 13:31:40.705679 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 13:31:40.708840 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 13:31:40.715960 0 11 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1848 13:31:40.719274 0 11 4 | B1->B0 | 2424 3636 | 0 0 | (1 1) (0 0)
1849 13:31:40.722401 0 11 8 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
1850 13:31:40.729000 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 13:31:40.732167 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 13:31:40.735892 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 13:31:40.742462 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 13:31:40.745348 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 13:31:40.748884 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 13:31:40.755920 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1857 13:31:40.758813 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1858 13:31:40.762473 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 13:31:40.768821 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 13:31:40.772480 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 13:31:40.775897 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 13:31:40.782215 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 13:31:40.785549 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 13:31:40.788822 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 13:31:40.795412 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 13:31:40.798702 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 13:31:40.802652 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 13:31:40.809083 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 13:31:40.812401 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 13:31:40.815352 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 13:31:40.818678 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 13:31:40.825322 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1873 13:31:40.828564 Total UI for P1: 0, mck2ui 16
1874 13:31:40.832509 best dqsien dly found for B0: ( 0, 14, 2)
1875 13:31:40.835785 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1876 13:31:40.838952 Total UI for P1: 0, mck2ui 16
1877 13:31:40.842342 best dqsien dly found for B1: ( 0, 14, 4)
1878 13:31:40.845637 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1879 13:31:40.848900 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1880 13:31:40.849023
1881 13:31:40.852314 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1882 13:31:40.855301 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1883 13:31:40.858983 [Gating] SW calibration Done
1884 13:31:40.859087 ==
1885 13:31:40.861905 Dram Type= 6, Freq= 0, CH_1, rank 1
1886 13:31:40.868545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1887 13:31:40.868651 ==
1888 13:31:40.868746 RX Vref Scan: 0
1889 13:31:40.868839
1890 13:31:40.871947 RX Vref 0 -> 0, step: 1
1891 13:31:40.872057
1892 13:31:40.875624 RX Delay -130 -> 252, step: 16
1893 13:31:40.878722 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1894 13:31:40.881815 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1895 13:31:40.885354 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1896 13:31:40.888443 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1897 13:31:40.894840 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1898 13:31:40.898853 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1899 13:31:40.902156 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1900 13:31:40.904887 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1901 13:31:40.908843 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1902 13:31:40.914839 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1903 13:31:40.918740 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1904 13:31:40.921907 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1905 13:31:40.924966 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1906 13:31:40.928397 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1907 13:31:40.934852 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1908 13:31:40.938181 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1909 13:31:40.938298 ==
1910 13:31:40.941530 Dram Type= 6, Freq= 0, CH_1, rank 1
1911 13:31:40.944771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1912 13:31:40.944876 ==
1913 13:31:40.948104 DQS Delay:
1914 13:31:40.948206 DQS0 = 0, DQS1 = 0
1915 13:31:40.948306 DQM Delay:
1916 13:31:40.951891 DQM0 = 79, DQM1 = 75
1917 13:31:40.951989 DQ Delay:
1918 13:31:40.955138 DQ0 =85, DQ1 =69, DQ2 =61, DQ3 =77
1919 13:31:40.958319 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1920 13:31:40.961614 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1921 13:31:40.964973 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1922 13:31:40.965059
1923 13:31:40.965125
1924 13:31:40.965187 ==
1925 13:31:40.968845 Dram Type= 6, Freq= 0, CH_1, rank 1
1926 13:31:40.974647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1927 13:31:40.974759 ==
1928 13:31:40.974865
1929 13:31:40.974966
1930 13:31:40.975069 TX Vref Scan disable
1931 13:31:40.978829 == TX Byte 0 ==
1932 13:31:40.982146 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1933 13:31:40.988579 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1934 13:31:40.988698 == TX Byte 1 ==
1935 13:31:40.992077 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1936 13:31:40.998829 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1937 13:31:40.998949 ==
1938 13:31:41.002117 Dram Type= 6, Freq= 0, CH_1, rank 1
1939 13:31:41.005198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1940 13:31:41.005315 ==
1941 13:31:41.017923 TX Vref=22, minBit 0, minWin=28, winSum=452
1942 13:31:41.021164 TX Vref=24, minBit 0, minWin=28, winSum=453
1943 13:31:41.024409 TX Vref=26, minBit 5, minWin=27, winSum=455
1944 13:31:41.027648 TX Vref=28, minBit 1, minWin=28, winSum=460
1945 13:31:41.030742 TX Vref=30, minBit 1, minWin=28, winSum=463
1946 13:31:41.034527 TX Vref=32, minBit 1, minWin=27, winSum=458
1947 13:31:41.041193 [TxChooseVref] Worse bit 1, Min win 28, Win sum 463, Final Vref 30
1948 13:31:41.041310
1949 13:31:41.044566 Final TX Range 1 Vref 30
1950 13:31:41.044677
1951 13:31:41.044776 ==
1952 13:31:41.047738 Dram Type= 6, Freq= 0, CH_1, rank 1
1953 13:31:41.051078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1954 13:31:41.051181 ==
1955 13:31:41.051278
1956 13:31:41.051378
1957 13:31:41.054397 TX Vref Scan disable
1958 13:31:41.057698 == TX Byte 0 ==
1959 13:31:41.060950 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1960 13:31:41.064256 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1961 13:31:41.067591 == TX Byte 1 ==
1962 13:31:41.070888 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1963 13:31:41.074681 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1964 13:31:41.074790
1965 13:31:41.077955 [DATLAT]
1966 13:31:41.078059 Freq=800, CH1 RK1
1967 13:31:41.078155
1968 13:31:41.081233 DATLAT Default: 0xa
1969 13:31:41.081337 0, 0xFFFF, sum = 0
1970 13:31:41.084543 1, 0xFFFF, sum = 0
1971 13:31:41.084645 2, 0xFFFF, sum = 0
1972 13:31:41.087917 3, 0xFFFF, sum = 0
1973 13:31:41.088024 4, 0xFFFF, sum = 0
1974 13:31:41.091206 5, 0xFFFF, sum = 0
1975 13:31:41.091314 6, 0xFFFF, sum = 0
1976 13:31:41.094489 7, 0xFFFF, sum = 0
1977 13:31:41.094604 8, 0x0, sum = 1
1978 13:31:41.097637 9, 0x0, sum = 2
1979 13:31:41.097730 10, 0x0, sum = 3
1980 13:31:41.101390 11, 0x0, sum = 4
1981 13:31:41.101505 best_step = 9
1982 13:31:41.101606
1983 13:31:41.101706 ==
1984 13:31:41.104364 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 13:31:41.111123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 13:31:41.111229 ==
1987 13:31:41.111336 RX Vref Scan: 0
1988 13:31:41.111445
1989 13:31:41.114541 RX Vref 0 -> 0, step: 1
1990 13:31:41.114655
1991 13:31:41.117630 RX Delay -111 -> 252, step: 8
1992 13:31:41.120830 iDelay=209, Bit 0, Center 84 (-39 ~ 208) 248
1993 13:31:41.124190 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
1994 13:31:41.127623 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
1995 13:31:41.134120 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1996 13:31:41.137687 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
1997 13:31:41.140749 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
1998 13:31:41.144560 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1999 13:31:41.148049 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2000 13:31:41.154558 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2001 13:31:41.157888 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2002 13:31:41.161284 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2003 13:31:41.164552 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2004 13:31:41.167925 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2005 13:31:41.174701 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2006 13:31:41.177446 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2007 13:31:41.181175 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2008 13:31:41.181286 ==
2009 13:31:41.184640 Dram Type= 6, Freq= 0, CH_1, rank 1
2010 13:31:41.188371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2011 13:31:41.188457 ==
2012 13:31:41.190954 DQS Delay:
2013 13:31:41.191040 DQS0 = 0, DQS1 = 0
2014 13:31:41.194209 DQM Delay:
2015 13:31:41.194294 DQM0 = 77, DQM1 = 73
2016 13:31:41.194381 DQ Delay:
2017 13:31:41.198014 DQ0 =84, DQ1 =72, DQ2 =64, DQ3 =72
2018 13:31:41.201345 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2019 13:31:41.204464 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
2020 13:31:41.207572 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2021 13:31:41.207658
2022 13:31:41.207745
2023 13:31:41.217824 [DQSOSCAuto] RK1, (LSB)MR18= 0x2239, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2024 13:31:41.221534 CH1 RK1: MR19=606, MR18=2239
2025 13:31:41.224565 CH1_RK1: MR19=0x606, MR18=0x2239, DQSOSC=395, MR23=63, INC=94, DEC=63
2026 13:31:41.227639 [RxdqsGatingPostProcess] freq 800
2027 13:31:41.234605 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2028 13:31:41.238032 Pre-setting of DQS Precalculation
2029 13:31:41.241430 [DualRankRxdatlatCal] RK0: 10, RK1: 9, Final_Datlat 10
2030 13:31:41.251387 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2031 13:31:41.257939 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2032 13:31:41.258052
2033 13:31:41.258164
2034 13:31:41.261248 [Calibration Summary] 1600 Mbps
2035 13:31:41.261365 CH 0, Rank 0
2036 13:31:41.264454 SW Impedance : PASS
2037 13:31:41.264576 DUTY Scan : NO K
2038 13:31:41.267784 ZQ Calibration : PASS
2039 13:31:41.271160 Jitter Meter : NO K
2040 13:31:41.271273 CBT Training : PASS
2041 13:31:41.274545 Write leveling : PASS
2042 13:31:41.277770 RX DQS gating : PASS
2043 13:31:41.277889 RX DQ/DQS(RDDQC) : PASS
2044 13:31:41.281139 TX DQ/DQS : PASS
2045 13:31:41.284400 RX DATLAT : PASS
2046 13:31:41.284485 RX DQ/DQS(Engine): PASS
2047 13:31:41.287622 TX OE : NO K
2048 13:31:41.287703 All Pass.
2049 13:31:41.287783
2050 13:31:41.290838 CH 0, Rank 1
2051 13:31:41.290957 SW Impedance : PASS
2052 13:31:41.294206 DUTY Scan : NO K
2053 13:31:41.294324 ZQ Calibration : PASS
2054 13:31:41.297572 Jitter Meter : NO K
2055 13:31:41.300799 CBT Training : PASS
2056 13:31:41.300922 Write leveling : PASS
2057 13:31:41.304042 RX DQS gating : PASS
2058 13:31:41.307402 RX DQ/DQS(RDDQC) : PASS
2059 13:31:41.307487 TX DQ/DQS : PASS
2060 13:31:41.311212 RX DATLAT : PASS
2061 13:31:41.314356 RX DQ/DQS(Engine): PASS
2062 13:31:41.314473 TX OE : NO K
2063 13:31:41.317594 All Pass.
2064 13:31:41.317695
2065 13:31:41.317798 CH 1, Rank 0
2066 13:31:41.320991 SW Impedance : PASS
2067 13:31:41.321103 DUTY Scan : NO K
2068 13:31:41.324306 ZQ Calibration : PASS
2069 13:31:41.327517 Jitter Meter : NO K
2070 13:31:41.327601 CBT Training : PASS
2071 13:31:41.330839 Write leveling : PASS
2072 13:31:41.334377 RX DQS gating : PASS
2073 13:31:41.334462 RX DQ/DQS(RDDQC) : PASS
2074 13:31:41.337450 TX DQ/DQS : PASS
2075 13:31:41.337530 RX DATLAT : PASS
2076 13:31:41.340900 RX DQ/DQS(Engine): PASS
2077 13:31:41.344366 TX OE : NO K
2078 13:31:41.344490 All Pass.
2079 13:31:41.344586
2080 13:31:41.344699 CH 1, Rank 1
2081 13:31:41.347413 SW Impedance : PASS
2082 13:31:41.350679 DUTY Scan : NO K
2083 13:31:41.350799 ZQ Calibration : PASS
2084 13:31:41.354500 Jitter Meter : NO K
2085 13:31:41.357759 CBT Training : PASS
2086 13:31:41.357866 Write leveling : PASS
2087 13:31:41.360706 RX DQS gating : PASS
2088 13:31:41.364411 RX DQ/DQS(RDDQC) : PASS
2089 13:31:41.364489 TX DQ/DQS : PASS
2090 13:31:41.367691 RX DATLAT : PASS
2091 13:31:41.370815 RX DQ/DQS(Engine): PASS
2092 13:31:41.370925 TX OE : NO K
2093 13:31:41.374220 All Pass.
2094 13:31:41.374302
2095 13:31:41.374367 DramC Write-DBI off
2096 13:31:41.377555 PER_BANK_REFRESH: Hybrid Mode
2097 13:31:41.377638 TX_TRACKING: ON
2098 13:31:41.380762 [GetDramInforAfterCalByMRR] Vendor 6.
2099 13:31:41.387565 [GetDramInforAfterCalByMRR] Revision 606.
2100 13:31:41.390882 [GetDramInforAfterCalByMRR] Revision 2 0.
2101 13:31:41.390997 MR0 0x3b3b
2102 13:31:41.391091 MR8 0x5151
2103 13:31:41.394077 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2104 13:31:41.394177
2105 13:31:41.397279 MR0 0x3b3b
2106 13:31:41.397361 MR8 0x5151
2107 13:31:41.400662 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2108 13:31:41.400746
2109 13:31:41.411311 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2110 13:31:41.414403 [FAST_K] Save calibration result to emmc
2111 13:31:41.417592 [FAST_K] Save calibration result to emmc
2112 13:31:41.420940 dram_init: config_dvfs: 1
2113 13:31:41.424264 dramc_set_vcore_voltage set vcore to 662500
2114 13:31:41.427559 Read voltage for 1200, 2
2115 13:31:41.427642 Vio18 = 0
2116 13:31:41.427707 Vcore = 662500
2117 13:31:41.430953 Vdram = 0
2118 13:31:41.431035 Vddq = 0
2119 13:31:41.431100 Vmddr = 0
2120 13:31:41.437664 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2121 13:31:41.441032 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2122 13:31:41.444361 MEM_TYPE=3, freq_sel=15
2123 13:31:41.447391 sv_algorithm_assistance_LP4_1600
2124 13:31:41.451191 ============ PULL DRAM RESETB DOWN ============
2125 13:31:41.454083 ========== PULL DRAM RESETB DOWN end =========
2126 13:31:41.460922 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2127 13:31:41.464179 ===================================
2128 13:31:41.464261 LPDDR4 DRAM CONFIGURATION
2129 13:31:41.467282 ===================================
2130 13:31:41.470890 EX_ROW_EN[0] = 0x0
2131 13:31:41.473854 EX_ROW_EN[1] = 0x0
2132 13:31:41.473938 LP4Y_EN = 0x0
2133 13:31:41.477266 WORK_FSP = 0x0
2134 13:31:41.477342 WL = 0x4
2135 13:31:41.480947 RL = 0x4
2136 13:31:41.481035 BL = 0x2
2137 13:31:41.484155 RPST = 0x0
2138 13:31:41.484244 RD_PRE = 0x0
2139 13:31:41.487516 WR_PRE = 0x1
2140 13:31:41.487590 WR_PST = 0x0
2141 13:31:41.490900 DBI_WR = 0x0
2142 13:31:41.490978 DBI_RD = 0x0
2143 13:31:41.494276 OTF = 0x1
2144 13:31:41.497530 ===================================
2145 13:31:41.500909 ===================================
2146 13:31:41.500998 ANA top config
2147 13:31:41.503980 ===================================
2148 13:31:41.507141 DLL_ASYNC_EN = 0
2149 13:31:41.510790 ALL_SLAVE_EN = 0
2150 13:31:41.510873 NEW_RANK_MODE = 1
2151 13:31:41.514069 DLL_IDLE_MODE = 1
2152 13:31:41.517370 LP45_APHY_COMB_EN = 1
2153 13:31:41.520565 TX_ODT_DIS = 1
2154 13:31:41.523873 NEW_8X_MODE = 1
2155 13:31:41.527269 ===================================
2156 13:31:41.530524 ===================================
2157 13:31:41.530612 data_rate = 2400
2158 13:31:41.533852 CKR = 1
2159 13:31:41.537166 DQ_P2S_RATIO = 8
2160 13:31:41.540428 ===================================
2161 13:31:41.543839 CA_P2S_RATIO = 8
2162 13:31:41.547176 DQ_CA_OPEN = 0
2163 13:31:41.550442 DQ_SEMI_OPEN = 0
2164 13:31:41.550526 CA_SEMI_OPEN = 0
2165 13:31:41.553729 CA_FULL_RATE = 0
2166 13:31:41.557013 DQ_CKDIV4_EN = 0
2167 13:31:41.560929 CA_CKDIV4_EN = 0
2168 13:31:41.563970 CA_PREDIV_EN = 0
2169 13:31:41.567040 PH8_DLY = 17
2170 13:31:41.567144 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2171 13:31:41.570801 DQ_AAMCK_DIV = 4
2172 13:31:41.574127 CA_AAMCK_DIV = 4
2173 13:31:41.577529 CA_ADMCK_DIV = 4
2174 13:31:41.580620 DQ_TRACK_CA_EN = 0
2175 13:31:41.583819 CA_PICK = 1200
2176 13:31:41.583897 CA_MCKIO = 1200
2177 13:31:41.587336 MCKIO_SEMI = 0
2178 13:31:41.590687 PLL_FREQ = 2366
2179 13:31:41.593939 DQ_UI_PI_RATIO = 32
2180 13:31:41.597610 CA_UI_PI_RATIO = 0
2181 13:31:41.600975 ===================================
2182 13:31:41.603711 ===================================
2183 13:31:41.607567 memory_type:LPDDR4
2184 13:31:41.607661 GP_NUM : 10
2185 13:31:41.610869 SRAM_EN : 1
2186 13:31:41.610955 MD32_EN : 0
2187 13:31:41.613954 ===================================
2188 13:31:41.617301 [ANA_INIT] >>>>>>>>>>>>>>
2189 13:31:41.620698 <<<<<< [CONFIGURE PHASE]: ANA_TX
2190 13:31:41.623850 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2191 13:31:41.627021 ===================================
2192 13:31:41.630396 data_rate = 2400,PCW = 0X5b00
2193 13:31:41.633830 ===================================
2194 13:31:41.637142 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2195 13:31:41.643938 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2196 13:31:41.647278 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2197 13:31:41.653912 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2198 13:31:41.657115 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2199 13:31:41.660370 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2200 13:31:41.660451 [ANA_INIT] flow start
2201 13:31:41.663547 [ANA_INIT] PLL >>>>>>>>
2202 13:31:41.666783 [ANA_INIT] PLL <<<<<<<<
2203 13:31:41.666894 [ANA_INIT] MIDPI >>>>>>>>
2204 13:31:41.670170 [ANA_INIT] MIDPI <<<<<<<<
2205 13:31:41.673918 [ANA_INIT] DLL >>>>>>>>
2206 13:31:41.674001 [ANA_INIT] DLL <<<<<<<<
2207 13:31:41.676831 [ANA_INIT] flow end
2208 13:31:41.680178 ============ LP4 DIFF to SE enter ============
2209 13:31:41.683886 ============ LP4 DIFF to SE exit ============
2210 13:31:41.687238 [ANA_INIT] <<<<<<<<<<<<<
2211 13:31:41.690468 [Flow] Enable top DCM control >>>>>
2212 13:31:41.693677 [Flow] Enable top DCM control <<<<<
2213 13:31:41.696838 Enable DLL master slave shuffle
2214 13:31:41.703314 ==============================================================
2215 13:31:41.703413 Gating Mode config
2216 13:31:41.710322 ==============================================================
2217 13:31:41.713280 Config description:
2218 13:31:41.720043 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2219 13:31:41.726663 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2220 13:31:41.733234 SELPH_MODE 0: By rank 1: By Phase
2221 13:31:41.740231 ==============================================================
2222 13:31:41.740348 GAT_TRACK_EN = 1
2223 13:31:41.742896 RX_GATING_MODE = 2
2224 13:31:41.746218 RX_GATING_TRACK_MODE = 2
2225 13:31:41.749603 SELPH_MODE = 1
2226 13:31:41.752901 PICG_EARLY_EN = 1
2227 13:31:41.756198 VALID_LAT_VALUE = 1
2228 13:31:41.763249 ==============================================================
2229 13:31:41.766438 Enter into Gating configuration >>>>
2230 13:31:41.769757 Exit from Gating configuration <<<<
2231 13:31:41.773068 Enter into DVFS_PRE_config >>>>>
2232 13:31:41.783309 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2233 13:31:41.786457 Exit from DVFS_PRE_config <<<<<
2234 13:31:41.789534 Enter into PICG configuration >>>>
2235 13:31:41.793413 Exit from PICG configuration <<<<
2236 13:31:41.796619 [RX_INPUT] configuration >>>>>
2237 13:31:41.796701 [RX_INPUT] configuration <<<<<
2238 13:31:41.803178 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2239 13:31:41.809527 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2240 13:31:41.813399 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2241 13:31:41.820091 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2242 13:31:41.826198 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2243 13:31:41.833091 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2244 13:31:41.836209 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2245 13:31:41.839738 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2246 13:31:41.846063 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2247 13:31:41.849729 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2248 13:31:41.852966 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2249 13:31:41.856322 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2250 13:31:41.859597 ===================================
2251 13:31:41.863392 LPDDR4 DRAM CONFIGURATION
2252 13:31:41.866512 ===================================
2253 13:31:41.869975 EX_ROW_EN[0] = 0x0
2254 13:31:41.870084 EX_ROW_EN[1] = 0x0
2255 13:31:41.873275 LP4Y_EN = 0x0
2256 13:31:41.873357 WORK_FSP = 0x0
2257 13:31:41.876515 WL = 0x4
2258 13:31:41.876622 RL = 0x4
2259 13:31:41.879860 BL = 0x2
2260 13:31:41.879937 RPST = 0x0
2261 13:31:41.883139 RD_PRE = 0x0
2262 13:31:41.886278 WR_PRE = 0x1
2263 13:31:41.886378 WR_PST = 0x0
2264 13:31:41.889452 DBI_WR = 0x0
2265 13:31:41.889556 DBI_RD = 0x0
2266 13:31:41.892676 OTF = 0x1
2267 13:31:41.896542 ===================================
2268 13:31:41.899959 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2269 13:31:41.903164 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2270 13:31:41.906647 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2271 13:31:41.909266 ===================================
2272 13:31:41.913016 LPDDR4 DRAM CONFIGURATION
2273 13:31:41.916310 ===================================
2274 13:31:41.919570 EX_ROW_EN[0] = 0x10
2275 13:31:41.919657 EX_ROW_EN[1] = 0x0
2276 13:31:41.922989 LP4Y_EN = 0x0
2277 13:31:41.923093 WORK_FSP = 0x0
2278 13:31:41.926269 WL = 0x4
2279 13:31:41.926370 RL = 0x4
2280 13:31:41.929400 BL = 0x2
2281 13:31:41.929492 RPST = 0x0
2282 13:31:41.933154 RD_PRE = 0x0
2283 13:31:41.933258 WR_PRE = 0x1
2284 13:31:41.936464 WR_PST = 0x0
2285 13:31:41.936549 DBI_WR = 0x0
2286 13:31:41.939441 DBI_RD = 0x0
2287 13:31:41.939528 OTF = 0x1
2288 13:31:41.942577 ===================================
2289 13:31:41.949283 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2290 13:31:41.949394 ==
2291 13:31:41.953133 Dram Type= 6, Freq= 0, CH_0, rank 0
2292 13:31:41.959540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2293 13:31:41.959625 ==
2294 13:31:41.959689 [Duty_Offset_Calibration]
2295 13:31:41.962874 B0:2 B1:0 CA:3
2296 13:31:41.962945
2297 13:31:41.966079 [DutyScan_Calibration_Flow] k_type=0
2298 13:31:41.975189
2299 13:31:41.975295 ==CLK 0==
2300 13:31:41.978525 Final CLK duty delay cell = 0
2301 13:31:41.981889 [0] MAX Duty = 5062%(X100), DQS PI = 20
2302 13:31:41.985344 [0] MIN Duty = 4906%(X100), DQS PI = 54
2303 13:31:41.985444 [0] AVG Duty = 4984%(X100)
2304 13:31:41.988603
2305 13:31:41.991885 CH0 CLK Duty spec in!! Max-Min= 156%
2306 13:31:41.995081 [DutyScan_Calibration_Flow] ====Done====
2307 13:31:41.995182
2308 13:31:41.998366 [DutyScan_Calibration_Flow] k_type=1
2309 13:31:42.013562
2310 13:31:42.013659 ==DQS 0 ==
2311 13:31:42.016835 Final DQS duty delay cell = 0
2312 13:31:42.020041 [0] MAX Duty = 5062%(X100), DQS PI = 12
2313 13:31:42.023415 [0] MIN Duty = 4907%(X100), DQS PI = 44
2314 13:31:42.026692 [0] AVG Duty = 4984%(X100)
2315 13:31:42.026763
2316 13:31:42.026824 ==DQS 1 ==
2317 13:31:42.030587 Final DQS duty delay cell = -4
2318 13:31:42.033919 [-4] MAX Duty = 4969%(X100), DQS PI = 24
2319 13:31:42.037097 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2320 13:31:42.040260 [-4] AVG Duty = 4922%(X100)
2321 13:31:42.040337
2322 13:31:42.043303 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2323 13:31:42.043414
2324 13:31:42.047110 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2325 13:31:42.050661 [DutyScan_Calibration_Flow] ====Done====
2326 13:31:42.050735
2327 13:31:42.053721 [DutyScan_Calibration_Flow] k_type=3
2328 13:31:42.071189
2329 13:31:42.071276 ==DQM 0 ==
2330 13:31:42.074617 Final DQM duty delay cell = 0
2331 13:31:42.077796 [0] MAX Duty = 5124%(X100), DQS PI = 28
2332 13:31:42.080753 [0] MIN Duty = 4907%(X100), DQS PI = 0
2333 13:31:42.080859 [0] AVG Duty = 5015%(X100)
2334 13:31:42.084055
2335 13:31:42.084153 ==DQM 1 ==
2336 13:31:42.087484 Final DQM duty delay cell = 4
2337 13:31:42.090777 [4] MAX Duty = 5124%(X100), DQS PI = 50
2338 13:31:42.094554 [4] MIN Duty = 5031%(X100), DQS PI = 12
2339 13:31:42.094636 [4] AVG Duty = 5077%(X100)
2340 13:31:42.097836
2341 13:31:42.101022 CH0 DQM 0 Duty spec in!! Max-Min= 217%
2342 13:31:42.101134
2343 13:31:42.104208 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2344 13:31:42.107383 [DutyScan_Calibration_Flow] ====Done====
2345 13:31:42.107465
2346 13:31:42.111130 [DutyScan_Calibration_Flow] k_type=2
2347 13:31:42.125902
2348 13:31:42.126012 ==DQ 0 ==
2349 13:31:42.129155 Final DQ duty delay cell = -4
2350 13:31:42.132409 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2351 13:31:42.135631 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2352 13:31:42.139671 [-4] AVG Duty = 4969%(X100)
2353 13:31:42.139748
2354 13:31:42.139812 ==DQ 1 ==
2355 13:31:42.142226 Final DQ duty delay cell = -4
2356 13:31:42.146131 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2357 13:31:42.149134 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2358 13:31:42.152227 [-4] AVG Duty = 4938%(X100)
2359 13:31:42.152341
2360 13:31:42.156054 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2361 13:31:42.156162
2362 13:31:42.159248 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2363 13:31:42.162334 [DutyScan_Calibration_Flow] ====Done====
2364 13:31:42.162454 ==
2365 13:31:42.165919 Dram Type= 6, Freq= 0, CH_1, rank 0
2366 13:31:42.168941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2367 13:31:42.169069 ==
2368 13:31:42.172912 [Duty_Offset_Calibration]
2369 13:31:42.172992 B0:1 B1:-2 CA:0
2370 13:31:42.173069
2371 13:31:42.176081 [DutyScan_Calibration_Flow] k_type=0
2372 13:31:42.186538
2373 13:31:42.186630 ==CLK 0==
2374 13:31:42.189418 Final CLK duty delay cell = 0
2375 13:31:42.193338 [0] MAX Duty = 5062%(X100), DQS PI = 30
2376 13:31:42.196382 [0] MIN Duty = 4844%(X100), DQS PI = 58
2377 13:31:42.196496 [0] AVG Duty = 4953%(X100)
2378 13:31:42.199517
2379 13:31:42.199632 CH1 CLK Duty spec in!! Max-Min= 218%
2380 13:31:42.206660 [DutyScan_Calibration_Flow] ====Done====
2381 13:31:42.206768
2382 13:31:42.209816 [DutyScan_Calibration_Flow] k_type=1
2383 13:31:42.225099
2384 13:31:42.225193 ==DQS 0 ==
2385 13:31:42.228064 Final DQS duty delay cell = -4
2386 13:31:42.231262 [-4] MAX Duty = 5000%(X100), DQS PI = 24
2387 13:31:42.234693 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2388 13:31:42.237859 [-4] AVG Duty = 4953%(X100)
2389 13:31:42.237942
2390 13:31:42.238007 ==DQS 1 ==
2391 13:31:42.241676 Final DQS duty delay cell = 0
2392 13:31:42.245010 [0] MAX Duty = 5093%(X100), DQS PI = 0
2393 13:31:42.248233 [0] MIN Duty = 4844%(X100), DQS PI = 26
2394 13:31:42.251451 [0] AVG Duty = 4968%(X100)
2395 13:31:42.251550
2396 13:31:42.254623 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2397 13:31:42.254725
2398 13:31:42.258169 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2399 13:31:42.261199 [DutyScan_Calibration_Flow] ====Done====
2400 13:31:42.261284
2401 13:31:42.264394 [DutyScan_Calibration_Flow] k_type=3
2402 13:31:42.281566
2403 13:31:42.281653 ==DQM 0 ==
2404 13:31:42.284752 Final DQM duty delay cell = 0
2405 13:31:42.287987 [0] MAX Duty = 5000%(X100), DQS PI = 22
2406 13:31:42.291242 [0] MIN Duty = 4844%(X100), DQS PI = 52
2407 13:31:42.294466 [0] AVG Duty = 4922%(X100)
2408 13:31:42.294544
2409 13:31:42.294633 ==DQM 1 ==
2410 13:31:42.298224 Final DQM duty delay cell = 0
2411 13:31:42.301107 [0] MAX Duty = 5031%(X100), DQS PI = 36
2412 13:31:42.304388 [0] MIN Duty = 4907%(X100), DQS PI = 4
2413 13:31:42.307879 [0] AVG Duty = 4969%(X100)
2414 13:31:42.307957
2415 13:31:42.311047 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2416 13:31:42.311126
2417 13:31:42.314276 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2418 13:31:42.318040 [DutyScan_Calibration_Flow] ====Done====
2419 13:31:42.318117
2420 13:31:42.321254 [DutyScan_Calibration_Flow] k_type=2
2421 13:31:42.337774
2422 13:31:42.337879 ==DQ 0 ==
2423 13:31:42.341010 Final DQ duty delay cell = 0
2424 13:31:42.344310 [0] MAX Duty = 5062%(X100), DQS PI = 18
2425 13:31:42.348079 [0] MIN Duty = 4938%(X100), DQS PI = 56
2426 13:31:42.348162 [0] AVG Duty = 5000%(X100)
2427 13:31:42.351283
2428 13:31:42.351401 ==DQ 1 ==
2429 13:31:42.354481 Final DQ duty delay cell = 0
2430 13:31:42.357605 [0] MAX Duty = 5124%(X100), DQS PI = 36
2431 13:31:42.360820 [0] MIN Duty = 4969%(X100), DQS PI = 26
2432 13:31:42.360902 [0] AVG Duty = 5046%(X100)
2433 13:31:42.360967
2434 13:31:42.364889 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2435 13:31:42.367719
2436 13:31:42.370877 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2437 13:31:42.374838 [DutyScan_Calibration_Flow] ====Done====
2438 13:31:42.377925 nWR fixed to 30
2439 13:31:42.378008 [ModeRegInit_LP4] CH0 RK0
2440 13:31:42.381198 [ModeRegInit_LP4] CH0 RK1
2441 13:31:42.384402 [ModeRegInit_LP4] CH1 RK0
2442 13:31:42.384483 [ModeRegInit_LP4] CH1 RK1
2443 13:31:42.387952 match AC timing 7
2444 13:31:42.391128 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2445 13:31:42.394289 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2446 13:31:42.401472 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2447 13:31:42.404622 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2448 13:31:42.411043 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2449 13:31:42.411126 ==
2450 13:31:42.414206 Dram Type= 6, Freq= 0, CH_0, rank 0
2451 13:31:42.417827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2452 13:31:42.417903 ==
2453 13:31:42.424390 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2454 13:31:42.430887 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2455 13:31:42.437849 [CA 0] Center 40 (10~71) winsize 62
2456 13:31:42.441376 [CA 1] Center 39 (9~70) winsize 62
2457 13:31:42.444373 [CA 2] Center 36 (6~66) winsize 61
2458 13:31:42.448110 [CA 3] Center 35 (5~66) winsize 62
2459 13:31:42.451522 [CA 4] Center 34 (4~65) winsize 62
2460 13:31:42.454753 [CA 5] Center 33 (3~63) winsize 61
2461 13:31:42.454836
2462 13:31:42.457842 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2463 13:31:42.457924
2464 13:31:42.461085 [CATrainingPosCal] consider 1 rank data
2465 13:31:42.464381 u2DelayCellTimex100 = 270/100 ps
2466 13:31:42.468181 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2467 13:31:42.474550 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2468 13:31:42.478085 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2469 13:31:42.481424 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2470 13:31:42.484576 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2471 13:31:42.487747 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2472 13:31:42.487847
2473 13:31:42.490923 CA PerBit enable=1, Macro0, CA PI delay=33
2474 13:31:42.491048
2475 13:31:42.494583 [CBTSetCACLKResult] CA Dly = 33
2476 13:31:42.494658 CS Dly: 7 (0~38)
2477 13:31:42.497590 ==
2478 13:31:42.500941 Dram Type= 6, Freq= 0, CH_0, rank 1
2479 13:31:42.504784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2480 13:31:42.504862 ==
2481 13:31:42.508152 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2482 13:31:42.514514 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2483 13:31:42.524184 [CA 0] Center 40 (10~70) winsize 61
2484 13:31:42.527570 [CA 1] Center 39 (9~70) winsize 62
2485 13:31:42.530513 [CA 2] Center 35 (5~66) winsize 62
2486 13:31:42.533836 [CA 3] Center 35 (5~66) winsize 62
2487 13:31:42.537049 [CA 4] Center 34 (4~65) winsize 62
2488 13:31:42.540564 [CA 5] Center 33 (3~64) winsize 62
2489 13:31:42.540675
2490 13:31:42.544152 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2491 13:31:42.544224
2492 13:31:42.547262 [CATrainingPosCal] consider 2 rank data
2493 13:31:42.550385 u2DelayCellTimex100 = 270/100 ps
2494 13:31:42.553952 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2495 13:31:42.560534 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2496 13:31:42.564184 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2497 13:31:42.567381 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2498 13:31:42.570547 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2499 13:31:42.573732 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2500 13:31:42.573840
2501 13:31:42.577523 CA PerBit enable=1, Macro0, CA PI delay=33
2502 13:31:42.577605
2503 13:31:42.580827 [CBTSetCACLKResult] CA Dly = 33
2504 13:31:42.580911 CS Dly: 8 (0~40)
2505 13:31:42.583757
2506 13:31:42.587487 ----->DramcWriteLeveling(PI) begin...
2507 13:31:42.587599 ==
2508 13:31:42.590734 Dram Type= 6, Freq= 0, CH_0, rank 0
2509 13:31:42.593957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2510 13:31:42.594040 ==
2511 13:31:42.597166 Write leveling (Byte 0): 31 => 31
2512 13:31:42.600375 Write leveling (Byte 1): 30 => 30
2513 13:31:42.603945 DramcWriteLeveling(PI) end<-----
2514 13:31:42.604027
2515 13:31:42.604092 ==
2516 13:31:42.607049 Dram Type= 6, Freq= 0, CH_0, rank 0
2517 13:31:42.610356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 13:31:42.610439 ==
2519 13:31:42.613454 [Gating] SW mode calibration
2520 13:31:42.620474 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2521 13:31:42.626876 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2522 13:31:42.630047 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2523 13:31:42.633824 0 15 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
2524 13:31:42.640069 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2525 13:31:42.643362 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2526 13:31:42.646540 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2527 13:31:42.653496 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 13:31:42.656675 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 13:31:42.659881 0 15 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2530 13:31:42.666694 1 0 0 | B1->B0 | 3232 2626 | 1 0 | (1 1) (0 1)
2531 13:31:42.669798 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 13:31:42.673309 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 13:31:42.679772 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 13:31:42.682967 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 13:31:42.686257 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 13:31:42.690078 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 13:31:42.696331 1 0 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2538 13:31:42.700085 1 1 0 | B1->B0 | 2424 3333 | 0 1 | (0 0) (0 0)
2539 13:31:42.703295 1 1 4 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
2540 13:31:42.709594 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 13:31:42.713228 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 13:31:42.716482 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 13:31:42.723262 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 13:31:42.726500 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 13:31:42.729760 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2546 13:31:42.736860 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2547 13:31:42.739979 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 13:31:42.743311 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 13:31:42.749765 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 13:31:42.753538 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 13:31:42.756658 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 13:31:42.762985 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 13:31:42.766761 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 13:31:42.769609 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 13:31:42.776670 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 13:31:42.779766 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 13:31:42.783481 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 13:31:42.789567 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 13:31:42.793023 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 13:31:42.796847 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 13:31:42.799986 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 13:31:42.806840 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2563 13:31:42.810023 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2564 13:31:42.813179 Total UI for P1: 0, mck2ui 16
2565 13:31:42.816249 best dqsien dly found for B0: ( 1, 4, 0)
2566 13:31:42.819934 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2567 13:31:42.822955 Total UI for P1: 0, mck2ui 16
2568 13:31:42.825983 best dqsien dly found for B1: ( 1, 4, 2)
2569 13:31:42.829892 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2570 13:31:42.833089 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2571 13:31:42.833200
2572 13:31:42.839593 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2573 13:31:42.842767 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2574 13:31:42.842877 [Gating] SW calibration Done
2575 13:31:42.846669 ==
2576 13:31:42.849834 Dram Type= 6, Freq= 0, CH_0, rank 0
2577 13:31:42.853198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2578 13:31:42.853307 ==
2579 13:31:42.853413 RX Vref Scan: 0
2580 13:31:42.853516
2581 13:31:42.856795 RX Vref 0 -> 0, step: 1
2582 13:31:42.856903
2583 13:31:42.859858 RX Delay -40 -> 252, step: 8
2584 13:31:42.863104 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2585 13:31:42.866174 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2586 13:31:42.869653 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2587 13:31:42.876497 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2588 13:31:42.879677 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2589 13:31:42.882847 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2590 13:31:42.886077 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2591 13:31:42.889386 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2592 13:31:42.896547 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2593 13:31:42.899605 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2594 13:31:42.902660 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2595 13:31:42.906159 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2596 13:31:42.909625 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2597 13:31:42.916162 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2598 13:31:42.919549 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2599 13:31:42.922760 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2600 13:31:42.922863 ==
2601 13:31:42.926417 Dram Type= 6, Freq= 0, CH_0, rank 0
2602 13:31:42.929545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2603 13:31:42.929651 ==
2604 13:31:42.933136 DQS Delay:
2605 13:31:42.933239 DQS0 = 0, DQS1 = 0
2606 13:31:42.936172 DQM Delay:
2607 13:31:42.936314 DQM0 = 112, DQM1 = 101
2608 13:31:42.936417 DQ Delay:
2609 13:31:42.939328 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2610 13:31:42.943117 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2611 13:31:42.946313 DQ8 =95, DQ9 =83, DQ10 =103, DQ11 =95
2612 13:31:42.952709 DQ12 =107, DQ13 =107, DQ14 =111, DQ15 =111
2613 13:31:42.952830
2614 13:31:42.952930
2615 13:31:42.953028 ==
2616 13:31:42.956472 Dram Type= 6, Freq= 0, CH_0, rank 0
2617 13:31:42.959590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2618 13:31:42.959698 ==
2619 13:31:42.959799
2620 13:31:42.959897
2621 13:31:42.962699 TX Vref Scan disable
2622 13:31:42.962799 == TX Byte 0 ==
2623 13:31:42.969785 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2624 13:31:42.972915 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2625 13:31:42.973022 == TX Byte 1 ==
2626 13:31:42.979856 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2627 13:31:42.983069 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2628 13:31:42.983175 ==
2629 13:31:42.986363 Dram Type= 6, Freq= 0, CH_0, rank 0
2630 13:31:42.989560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2631 13:31:42.989663 ==
2632 13:31:43.001963 TX Vref=22, minBit 11, minWin=25, winSum=416
2633 13:31:43.005764 TX Vref=24, minBit 14, minWin=25, winSum=421
2634 13:31:43.009031 TX Vref=26, minBit 4, minWin=26, winSum=430
2635 13:31:43.012228 TX Vref=28, minBit 13, minWin=26, winSum=432
2636 13:31:43.015472 TX Vref=30, minBit 10, minWin=26, winSum=431
2637 13:31:43.021985 TX Vref=32, minBit 3, minWin=26, winSum=429
2638 13:31:43.025609 [TxChooseVref] Worse bit 13, Min win 26, Win sum 432, Final Vref 28
2639 13:31:43.025714
2640 13:31:43.028626 Final TX Range 1 Vref 28
2641 13:31:43.028733
2642 13:31:43.028832 ==
2643 13:31:43.032019 Dram Type= 6, Freq= 0, CH_0, rank 0
2644 13:31:43.035728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2645 13:31:43.039013 ==
2646 13:31:43.039122
2647 13:31:43.039260
2648 13:31:43.039357 TX Vref Scan disable
2649 13:31:43.042128 == TX Byte 0 ==
2650 13:31:43.045589 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2651 13:31:43.052236 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2652 13:31:43.052345 == TX Byte 1 ==
2653 13:31:43.055364 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2654 13:31:43.062509 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2655 13:31:43.062621
2656 13:31:43.062723 [DATLAT]
2657 13:31:43.062828 Freq=1200, CH0 RK0
2658 13:31:43.062925
2659 13:31:43.065792 DATLAT Default: 0xd
2660 13:31:43.065895 0, 0xFFFF, sum = 0
2661 13:31:43.068842 1, 0xFFFF, sum = 0
2662 13:31:43.068950 2, 0xFFFF, sum = 0
2663 13:31:43.072037 3, 0xFFFF, sum = 0
2664 13:31:43.075856 4, 0xFFFF, sum = 0
2665 13:31:43.075961 5, 0xFFFF, sum = 0
2666 13:31:43.079086 6, 0xFFFF, sum = 0
2667 13:31:43.079192 7, 0xFFFF, sum = 0
2668 13:31:43.082442 8, 0xFFFF, sum = 0
2669 13:31:43.082537 9, 0xFFFF, sum = 0
2670 13:31:43.085698 10, 0xFFFF, sum = 0
2671 13:31:43.085805 11, 0xFFFF, sum = 0
2672 13:31:43.088915 12, 0x0, sum = 1
2673 13:31:43.089022 13, 0x0, sum = 2
2674 13:31:43.092143 14, 0x0, sum = 3
2675 13:31:43.092245 15, 0x0, sum = 4
2676 13:31:43.095423 best_step = 13
2677 13:31:43.095528
2678 13:31:43.095631 ==
2679 13:31:43.098623 Dram Type= 6, Freq= 0, CH_0, rank 0
2680 13:31:43.101780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2681 13:31:43.101892 ==
2682 13:31:43.102000 RX Vref Scan: 1
2683 13:31:43.102100
2684 13:31:43.105081 Set Vref Range= 32 -> 127
2685 13:31:43.105188
2686 13:31:43.108893 RX Vref 32 -> 127, step: 1
2687 13:31:43.109004
2688 13:31:43.112163 RX Delay -37 -> 252, step: 4
2689 13:31:43.112275
2690 13:31:43.115544 Set Vref, RX VrefLevel [Byte0]: 32
2691 13:31:43.118735 [Byte1]: 32
2692 13:31:43.118840
2693 13:31:43.121889 Set Vref, RX VrefLevel [Byte0]: 33
2694 13:31:43.125136 [Byte1]: 33
2695 13:31:43.128972
2696 13:31:43.129080 Set Vref, RX VrefLevel [Byte0]: 34
2697 13:31:43.132258 [Byte1]: 34
2698 13:31:43.136848
2699 13:31:43.136957 Set Vref, RX VrefLevel [Byte0]: 35
2700 13:31:43.140020 [Byte1]: 35
2701 13:31:43.145135
2702 13:31:43.145246 Set Vref, RX VrefLevel [Byte0]: 36
2703 13:31:43.148589 [Byte1]: 36
2704 13:31:43.153180
2705 13:31:43.153283 Set Vref, RX VrefLevel [Byte0]: 37
2706 13:31:43.156370 [Byte1]: 37
2707 13:31:43.161082
2708 13:31:43.161185 Set Vref, RX VrefLevel [Byte0]: 38
2709 13:31:43.164272 [Byte1]: 38
2710 13:31:43.168987
2711 13:31:43.169106 Set Vref, RX VrefLevel [Byte0]: 39
2712 13:31:43.172031 [Byte1]: 39
2713 13:31:43.176955
2714 13:31:43.177089 Set Vref, RX VrefLevel [Byte0]: 40
2715 13:31:43.180485 [Byte1]: 40
2716 13:31:43.185064
2717 13:31:43.185170 Set Vref, RX VrefLevel [Byte0]: 41
2718 13:31:43.188139 [Byte1]: 41
2719 13:31:43.192746
2720 13:31:43.192852 Set Vref, RX VrefLevel [Byte0]: 42
2721 13:31:43.196714 [Byte1]: 42
2722 13:31:43.201248
2723 13:31:43.201353 Set Vref, RX VrefLevel [Byte0]: 43
2724 13:31:43.204416 [Byte1]: 43
2725 13:31:43.208931
2726 13:31:43.209032 Set Vref, RX VrefLevel [Byte0]: 44
2727 13:31:43.212130 [Byte1]: 44
2728 13:31:43.217008
2729 13:31:43.217111 Set Vref, RX VrefLevel [Byte0]: 45
2730 13:31:43.220283 [Byte1]: 45
2731 13:31:43.224852
2732 13:31:43.224953 Set Vref, RX VrefLevel [Byte0]: 46
2733 13:31:43.228630 [Byte1]: 46
2734 13:31:43.233125
2735 13:31:43.233232 Set Vref, RX VrefLevel [Byte0]: 47
2736 13:31:43.236366 [Byte1]: 47
2737 13:31:43.240868
2738 13:31:43.240969 Set Vref, RX VrefLevel [Byte0]: 48
2739 13:31:43.244168 [Byte1]: 48
2740 13:31:43.248841
2741 13:31:43.248944 Set Vref, RX VrefLevel [Byte0]: 49
2742 13:31:43.252657 [Byte1]: 49
2743 13:31:43.257212
2744 13:31:43.257320 Set Vref, RX VrefLevel [Byte0]: 50
2745 13:31:43.260439 [Byte1]: 50
2746 13:31:43.264899
2747 13:31:43.264977 Set Vref, RX VrefLevel [Byte0]: 51
2748 13:31:43.268564 [Byte1]: 51
2749 13:31:43.273034
2750 13:31:43.273137 Set Vref, RX VrefLevel [Byte0]: 52
2751 13:31:43.276034 [Byte1]: 52
2752 13:31:43.281129
2753 13:31:43.281234 Set Vref, RX VrefLevel [Byte0]: 53
2754 13:31:43.284473 [Byte1]: 53
2755 13:31:43.289123
2756 13:31:43.289229 Set Vref, RX VrefLevel [Byte0]: 54
2757 13:31:43.292163 [Byte1]: 54
2758 13:31:43.296673
2759 13:31:43.296754 Set Vref, RX VrefLevel [Byte0]: 55
2760 13:31:43.300386 [Byte1]: 55
2761 13:31:43.304870
2762 13:31:43.304953 Set Vref, RX VrefLevel [Byte0]: 56
2763 13:31:43.308234 [Byte1]: 56
2764 13:31:43.312711
2765 13:31:43.312816 Set Vref, RX VrefLevel [Byte0]: 57
2766 13:31:43.316601 [Byte1]: 57
2767 13:31:43.321083
2768 13:31:43.321166 Set Vref, RX VrefLevel [Byte0]: 58
2769 13:31:43.324331 [Byte1]: 58
2770 13:31:43.328857
2771 13:31:43.328942 Set Vref, RX VrefLevel [Byte0]: 59
2772 13:31:43.332215 [Byte1]: 59
2773 13:31:43.336694
2774 13:31:43.336800 Set Vref, RX VrefLevel [Byte0]: 60
2775 13:31:43.340447 [Byte1]: 60
2776 13:31:43.344921
2777 13:31:43.345027 Set Vref, RX VrefLevel [Byte0]: 61
2778 13:31:43.348114 [Byte1]: 61
2779 13:31:43.352921
2780 13:31:43.353027 Set Vref, RX VrefLevel [Byte0]: 62
2781 13:31:43.356244 [Byte1]: 62
2782 13:31:43.360780
2783 13:31:43.360883 Set Vref, RX VrefLevel [Byte0]: 63
2784 13:31:43.364020 [Byte1]: 63
2785 13:31:43.369290
2786 13:31:43.369391 Set Vref, RX VrefLevel [Byte0]: 64
2787 13:31:43.372403 [Byte1]: 64
2788 13:31:43.376842
2789 13:31:43.376946 Set Vref, RX VrefLevel [Byte0]: 65
2790 13:31:43.380138 [Byte1]: 65
2791 13:31:43.385237
2792 13:31:43.385362 Set Vref, RX VrefLevel [Byte0]: 66
2793 13:31:43.388432 [Byte1]: 66
2794 13:31:43.392888
2795 13:31:43.392988 Set Vref, RX VrefLevel [Byte0]: 67
2796 13:31:43.396083 [Byte1]: 67
2797 13:31:43.401043
2798 13:31:43.401144 Set Vref, RX VrefLevel [Byte0]: 68
2799 13:31:43.404184 [Byte1]: 68
2800 13:31:43.408918
2801 13:31:43.409024 Set Vref, RX VrefLevel [Byte0]: 69
2802 13:31:43.412249 [Byte1]: 69
2803 13:31:43.417103
2804 13:31:43.417203 Set Vref, RX VrefLevel [Byte0]: 70
2805 13:31:43.420024 [Byte1]: 70
2806 13:31:43.425107
2807 13:31:43.425211 Set Vref, RX VrefLevel [Byte0]: 71
2808 13:31:43.428363 [Byte1]: 71
2809 13:31:43.432808
2810 13:31:43.432952 Set Vref, RX VrefLevel [Byte0]: 72
2811 13:31:43.436107 [Byte1]: 72
2812 13:31:43.441103
2813 13:31:43.441221 Set Vref, RX VrefLevel [Byte0]: 73
2814 13:31:43.444197 [Byte1]: 73
2815 13:31:43.448693
2816 13:31:43.448800 Set Vref, RX VrefLevel [Byte0]: 74
2817 13:31:43.452621 [Byte1]: 74
2818 13:31:43.457092
2819 13:31:43.457192 Final RX Vref Byte 0 = 62 to rank0
2820 13:31:43.460321 Final RX Vref Byte 1 = 47 to rank0
2821 13:31:43.463360 Final RX Vref Byte 0 = 62 to rank1
2822 13:31:43.467141 Final RX Vref Byte 1 = 47 to rank1==
2823 13:31:43.470366 Dram Type= 6, Freq= 0, CH_0, rank 0
2824 13:31:43.477276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2825 13:31:43.477385 ==
2826 13:31:43.477481 DQS Delay:
2827 13:31:43.477572 DQS0 = 0, DQS1 = 0
2828 13:31:43.480226 DQM Delay:
2829 13:31:43.480335 DQM0 = 111, DQM1 = 98
2830 13:31:43.483354 DQ Delay:
2831 13:31:43.487219 DQ0 =108, DQ1 =112, DQ2 =112, DQ3 =108
2832 13:31:43.490536 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2833 13:31:43.493811 DQ8 =90, DQ9 =82, DQ10 =100, DQ11 =90
2834 13:31:43.497005 DQ12 =104, DQ13 =104, DQ14 =112, DQ15 =106
2835 13:31:43.497085
2836 13:31:43.497169
2837 13:31:43.503991 [DQSOSCAuto] RK0, (LSB)MR18= 0xfdfd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
2838 13:31:43.507296 CH0 RK0: MR19=303, MR18=FDFD
2839 13:31:43.513711 CH0_RK0: MR19=0x303, MR18=0xFDFD, DQSOSC=411, MR23=63, INC=38, DEC=25
2840 13:31:43.513804
2841 13:31:43.516986 ----->DramcWriteLeveling(PI) begin...
2842 13:31:43.517072 ==
2843 13:31:43.520259 Dram Type= 6, Freq= 0, CH_0, rank 1
2844 13:31:43.523465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2845 13:31:43.523558 ==
2846 13:31:43.526709 Write leveling (Byte 0): 29 => 29
2847 13:31:43.530419 Write leveling (Byte 1): 31 => 31
2848 13:31:43.533575 DramcWriteLeveling(PI) end<-----
2849 13:31:43.533662
2850 13:31:43.533743 ==
2851 13:31:43.536694 Dram Type= 6, Freq= 0, CH_0, rank 1
2852 13:31:43.543595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2853 13:31:43.543677 ==
2854 13:31:43.543742 [Gating] SW mode calibration
2855 13:31:43.553444 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2856 13:31:43.556631 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2857 13:31:43.559949 0 15 0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
2858 13:31:43.566608 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 13:31:43.570336 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 13:31:43.573355 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 13:31:43.579866 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 13:31:43.583131 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 13:31:43.586755 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2864 13:31:43.593132 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
2865 13:31:43.596454 1 0 0 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
2866 13:31:43.600330 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 13:31:43.606773 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 13:31:43.610040 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 13:31:43.613759 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 13:31:43.620409 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 13:31:43.623561 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
2872 13:31:43.626876 1 0 28 | B1->B0 | 2424 4040 | 0 0 | (0 0) (0 0)
2873 13:31:43.633765 1 1 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
2874 13:31:43.636948 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 13:31:43.640016 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 13:31:43.643258 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 13:31:43.650280 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 13:31:43.653487 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 13:31:43.656651 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 13:31:43.663241 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2881 13:31:43.666851 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2882 13:31:43.670497 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 13:31:43.677005 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 13:31:43.680205 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 13:31:43.683363 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 13:31:43.690357 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 13:31:43.693990 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 13:31:43.696748 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 13:31:43.703757 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 13:31:43.706892 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 13:31:43.710121 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 13:31:43.716436 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 13:31:43.720194 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 13:31:43.723341 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 13:31:43.729841 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 13:31:43.733575 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2897 13:31:43.736843 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2898 13:31:43.740014 Total UI for P1: 0, mck2ui 16
2899 13:31:43.743700 best dqsien dly found for B0: ( 1, 3, 28)
2900 13:31:43.746814 Total UI for P1: 0, mck2ui 16
2901 13:31:43.750090 best dqsien dly found for B1: ( 1, 3, 30)
2902 13:31:43.753387 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2903 13:31:43.756681 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2904 13:31:43.756763
2905 13:31:43.759941 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2906 13:31:43.766548 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2907 13:31:43.766629 [Gating] SW calibration Done
2908 13:31:43.766694 ==
2909 13:31:43.770496 Dram Type= 6, Freq= 0, CH_0, rank 1
2910 13:31:43.776923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2911 13:31:43.777006 ==
2912 13:31:43.777071 RX Vref Scan: 0
2913 13:31:43.777131
2914 13:31:43.780031 RX Vref 0 -> 0, step: 1
2915 13:31:43.780112
2916 13:31:43.783223 RX Delay -40 -> 252, step: 8
2917 13:31:43.787049 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2918 13:31:43.790185 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2919 13:31:43.793689 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2920 13:31:43.796992 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2921 13:31:43.803209 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2922 13:31:43.806721 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2923 13:31:43.810223 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2924 13:31:43.813222 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2925 13:31:43.816454 iDelay=200, Bit 8, Center 87 (16 ~ 159) 144
2926 13:31:43.823568 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2927 13:31:43.826520 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2928 13:31:43.830127 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2929 13:31:43.833461 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2930 13:31:43.836747 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2931 13:31:43.843034 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2932 13:31:43.846789 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2933 13:31:43.846900 ==
2934 13:31:43.849871 Dram Type= 6, Freq= 0, CH_0, rank 1
2935 13:31:43.853267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2936 13:31:43.853375 ==
2937 13:31:43.856484 DQS Delay:
2938 13:31:43.856594 DQS0 = 0, DQS1 = 0
2939 13:31:43.856699 DQM Delay:
2940 13:31:43.860393 DQM0 = 112, DQM1 = 100
2941 13:31:43.860498 DQ Delay:
2942 13:31:43.863591 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2943 13:31:43.866784 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =123
2944 13:31:43.870014 DQ8 =87, DQ9 =83, DQ10 =103, DQ11 =95
2945 13:31:43.873275 DQ12 =107, DQ13 =107, DQ14 =111, DQ15 =111
2946 13:31:43.873384
2947 13:31:43.876493
2948 13:31:43.876593 ==
2949 13:31:43.879896 Dram Type= 6, Freq= 0, CH_0, rank 1
2950 13:31:43.883665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2951 13:31:43.883775 ==
2952 13:31:43.883869
2953 13:31:43.883958
2954 13:31:43.886978 TX Vref Scan disable
2955 13:31:43.887080 == TX Byte 0 ==
2956 13:31:43.893451 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2957 13:31:43.896644 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2958 13:31:43.896751 == TX Byte 1 ==
2959 13:31:43.903072 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2960 13:31:43.906636 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2961 13:31:43.906739 ==
2962 13:31:43.909999 Dram Type= 6, Freq= 0, CH_0, rank 1
2963 13:31:43.913284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2964 13:31:43.913390 ==
2965 13:31:43.925435 TX Vref=22, minBit 0, minWin=26, winSum=424
2966 13:31:43.929083 TX Vref=24, minBit 1, minWin=26, winSum=426
2967 13:31:43.932146 TX Vref=26, minBit 1, minWin=26, winSum=435
2968 13:31:43.935250 TX Vref=28, minBit 0, minWin=27, winSum=441
2969 13:31:43.939045 TX Vref=30, minBit 2, minWin=27, winSum=442
2970 13:31:43.942115 TX Vref=32, minBit 2, minWin=26, winSum=438
2971 13:31:43.948802 [TxChooseVref] Worse bit 2, Min win 27, Win sum 442, Final Vref 30
2972 13:31:43.948888
2973 13:31:43.952265 Final TX Range 1 Vref 30
2974 13:31:43.952375
2975 13:31:43.952469 ==
2976 13:31:43.955516 Dram Type= 6, Freq= 0, CH_0, rank 1
2977 13:31:43.958966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2978 13:31:43.959071 ==
2979 13:31:43.959164
2980 13:31:43.959264
2981 13:31:43.962507 TX Vref Scan disable
2982 13:31:43.965786 == TX Byte 0 ==
2983 13:31:43.969042 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2984 13:31:43.972196 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2985 13:31:43.975497 == TX Byte 1 ==
2986 13:31:43.978643 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2987 13:31:43.982510 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2988 13:31:43.982600
2989 13:31:43.985685 [DATLAT]
2990 13:31:43.985792 Freq=1200, CH0 RK1
2991 13:31:43.985887
2992 13:31:43.988890 DATLAT Default: 0xd
2993 13:31:43.988996 0, 0xFFFF, sum = 0
2994 13:31:43.992030 1, 0xFFFF, sum = 0
2995 13:31:43.992138 2, 0xFFFF, sum = 0
2996 13:31:43.995786 3, 0xFFFF, sum = 0
2997 13:31:43.995888 4, 0xFFFF, sum = 0
2998 13:31:43.999012 5, 0xFFFF, sum = 0
2999 13:31:43.999122 6, 0xFFFF, sum = 0
3000 13:31:44.002250 7, 0xFFFF, sum = 0
3001 13:31:44.002353 8, 0xFFFF, sum = 0
3002 13:31:44.005542 9, 0xFFFF, sum = 0
3003 13:31:44.008753 10, 0xFFFF, sum = 0
3004 13:31:44.008857 11, 0xFFFF, sum = 0
3005 13:31:44.012053 12, 0x0, sum = 1
3006 13:31:44.012160 13, 0x0, sum = 2
3007 13:31:44.012254 14, 0x0, sum = 3
3008 13:31:44.015541 15, 0x0, sum = 4
3009 13:31:44.015647 best_step = 13
3010 13:31:44.015742
3011 13:31:44.015833 ==
3012 13:31:44.018882 Dram Type= 6, Freq= 0, CH_0, rank 1
3013 13:31:44.025448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3014 13:31:44.025556 ==
3015 13:31:44.025654 RX Vref Scan: 0
3016 13:31:44.025749
3017 13:31:44.028458 RX Vref 0 -> 0, step: 1
3018 13:31:44.028560
3019 13:31:44.032309 RX Delay -37 -> 252, step: 4
3020 13:31:44.035488 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3021 13:31:44.041949 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3022 13:31:44.045045 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3023 13:31:44.048845 iDelay=195, Bit 3, Center 110 (39 ~ 182) 144
3024 13:31:44.051818 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3025 13:31:44.055547 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3026 13:31:44.058511 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3027 13:31:44.065339 iDelay=195, Bit 7, Center 118 (43 ~ 194) 152
3028 13:31:44.068805 iDelay=195, Bit 8, Center 88 (19 ~ 158) 140
3029 13:31:44.072048 iDelay=195, Bit 9, Center 80 (11 ~ 150) 140
3030 13:31:44.075258 iDelay=195, Bit 10, Center 100 (31 ~ 170) 140
3031 13:31:44.078603 iDelay=195, Bit 11, Center 90 (23 ~ 158) 136
3032 13:31:44.085654 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3033 13:31:44.088939 iDelay=195, Bit 13, Center 106 (35 ~ 178) 144
3034 13:31:44.092034 iDelay=195, Bit 14, Center 112 (47 ~ 178) 132
3035 13:31:44.095871 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3036 13:31:44.095971 ==
3037 13:31:44.098557 Dram Type= 6, Freq= 0, CH_0, rank 1
3038 13:31:44.105800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3039 13:31:44.105907 ==
3040 13:31:44.106001 DQS Delay:
3041 13:31:44.106093 DQS0 = 0, DQS1 = 0
3042 13:31:44.109158 DQM Delay:
3043 13:31:44.109260 DQM0 = 110, DQM1 = 99
3044 13:31:44.112354 DQ Delay:
3045 13:31:44.115512 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =110
3046 13:31:44.118767 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =118
3047 13:31:44.121941 DQ8 =88, DQ9 =80, DQ10 =100, DQ11 =90
3048 13:31:44.125656 DQ12 =108, DQ13 =106, DQ14 =112, DQ15 =108
3049 13:31:44.125758
3050 13:31:44.125851
3051 13:31:44.132157 [DQSOSCAuto] RK1, (LSB)MR18= 0x14fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 402 ps
3052 13:31:44.135772 CH0 RK1: MR19=403, MR18=14FC
3053 13:31:44.141841 CH0_RK1: MR19=0x403, MR18=0x14FC, DQSOSC=402, MR23=63, INC=40, DEC=27
3054 13:31:44.145076 [RxdqsGatingPostProcess] freq 1200
3055 13:31:44.152066 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3056 13:31:44.155217 best DQS0 dly(2T, 0.5T) = (0, 12)
3057 13:31:44.155324 best DQS1 dly(2T, 0.5T) = (0, 12)
3058 13:31:44.158877 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3059 13:31:44.161872 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3060 13:31:44.165192 best DQS0 dly(2T, 0.5T) = (0, 11)
3061 13:31:44.168782 best DQS1 dly(2T, 0.5T) = (0, 11)
3062 13:31:44.171962 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3063 13:31:44.175765 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3064 13:31:44.178637 Pre-setting of DQS Precalculation
3065 13:31:44.182013 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3066 13:31:44.185509 ==
3067 13:31:44.189023 Dram Type= 6, Freq= 0, CH_1, rank 0
3068 13:31:44.192243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3069 13:31:44.192350 ==
3070 13:31:44.195528 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3071 13:31:44.201814 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3072 13:31:44.211468 [CA 0] Center 37 (7~67) winsize 61
3073 13:31:44.214728 [CA 1] Center 37 (7~68) winsize 62
3074 13:31:44.217963 [CA 2] Center 34 (4~64) winsize 61
3075 13:31:44.221285 [CA 3] Center 33 (3~64) winsize 62
3076 13:31:44.224612 [CA 4] Center 34 (4~64) winsize 61
3077 13:31:44.227762 [CA 5] Center 33 (3~63) winsize 61
3078 13:31:44.227868
3079 13:31:44.231518 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3080 13:31:44.231625
3081 13:31:44.234805 [CATrainingPosCal] consider 1 rank data
3082 13:31:44.237828 u2DelayCellTimex100 = 270/100 ps
3083 13:31:44.241421 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3084 13:31:44.244998 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3085 13:31:44.251142 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3086 13:31:44.254549 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3087 13:31:44.257734 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3088 13:31:44.261535 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3089 13:31:44.261640
3090 13:31:44.264802 CA PerBit enable=1, Macro0, CA PI delay=33
3091 13:31:44.264902
3092 13:31:44.268133 [CBTSetCACLKResult] CA Dly = 33
3093 13:31:44.268237 CS Dly: 6 (0~37)
3094 13:31:44.268333 ==
3095 13:31:44.271158 Dram Type= 6, Freq= 0, CH_1, rank 1
3096 13:31:44.277742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3097 13:31:44.277848 ==
3098 13:31:44.281117 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3099 13:31:44.287882 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3100 13:31:44.296774 [CA 0] Center 37 (7~68) winsize 62
3101 13:31:44.300451 [CA 1] Center 37 (7~68) winsize 62
3102 13:31:44.303527 [CA 2] Center 35 (5~65) winsize 61
3103 13:31:44.307076 [CA 3] Center 33 (3~64) winsize 62
3104 13:31:44.310299 [CA 4] Center 34 (4~65) winsize 62
3105 13:31:44.313637 [CA 5] Center 32 (2~63) winsize 62
3106 13:31:44.313741
3107 13:31:44.316768 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3108 13:31:44.316870
3109 13:31:44.319964 [CATrainingPosCal] consider 2 rank data
3110 13:31:44.323843 u2DelayCellTimex100 = 270/100 ps
3111 13:31:44.327153 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3112 13:31:44.330286 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3113 13:31:44.336801 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3114 13:31:44.340124 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3115 13:31:44.343194 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3116 13:31:44.347011 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3117 13:31:44.347117
3118 13:31:44.350027 CA PerBit enable=1, Macro0, CA PI delay=33
3119 13:31:44.350137
3120 13:31:44.353679 [CBTSetCACLKResult] CA Dly = 33
3121 13:31:44.353766 CS Dly: 7 (0~40)
3122 13:31:44.353831
3123 13:31:44.360077 ----->DramcWriteLeveling(PI) begin...
3124 13:31:44.360161 ==
3125 13:31:44.363381 Dram Type= 6, Freq= 0, CH_1, rank 0
3126 13:31:44.366663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3127 13:31:44.366746 ==
3128 13:31:44.370454 Write leveling (Byte 0): 26 => 26
3129 13:31:44.373629 Write leveling (Byte 1): 28 => 28
3130 13:31:44.376902 DramcWriteLeveling(PI) end<-----
3131 13:31:44.376983
3132 13:31:44.377047 ==
3133 13:31:44.380266 Dram Type= 6, Freq= 0, CH_1, rank 0
3134 13:31:44.383504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3135 13:31:44.383585 ==
3136 13:31:44.386929 [Gating] SW mode calibration
3137 13:31:44.393684 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3138 13:31:44.400014 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3139 13:31:44.402981 0 15 0 | B1->B0 | 3333 2c2c | 0 0 | (0 0) (0 0)
3140 13:31:44.406580 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 13:31:44.410075 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 13:31:44.416639 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 13:31:44.419659 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 13:31:44.423355 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 13:31:44.429842 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 13:31:44.433132 0 15 28 | B1->B0 | 2c2c 2f2f | 0 0 | (0 0) (0 1)
3147 13:31:44.436338 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 13:31:44.442913 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 13:31:44.446842 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 13:31:44.449859 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 13:31:44.456727 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 13:31:44.459881 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 13:31:44.463008 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 13:31:44.469822 1 0 28 | B1->B0 | 4141 4242 | 0 0 | (0 0) (0 0)
3155 13:31:44.473010 1 1 0 | B1->B0 | 4646 4343 | 0 1 | (0 0) (0 0)
3156 13:31:44.476201 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 13:31:44.483263 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 13:31:44.487042 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 13:31:44.490300 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 13:31:44.493548 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 13:31:44.500148 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 13:31:44.503109 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 13:31:44.506685 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3164 13:31:44.513510 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 13:31:44.516444 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 13:31:44.519916 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 13:31:44.526768 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 13:31:44.529726 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 13:31:44.533219 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 13:31:44.540015 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 13:31:44.543256 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 13:31:44.546486 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 13:31:44.553304 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 13:31:44.556497 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 13:31:44.559712 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 13:31:44.566256 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 13:31:44.569509 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 13:31:44.573172 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3179 13:31:44.579479 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3180 13:31:44.582851 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3181 13:31:44.586661 Total UI for P1: 0, mck2ui 16
3182 13:31:44.589949 best dqsien dly found for B0: ( 1, 3, 30)
3183 13:31:44.593177 Total UI for P1: 0, mck2ui 16
3184 13:31:44.596461 best dqsien dly found for B1: ( 1, 3, 30)
3185 13:31:44.599776 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3186 13:31:44.603001 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3187 13:31:44.603101
3188 13:31:44.606301 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3189 13:31:44.609532 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3190 13:31:44.613653 [Gating] SW calibration Done
3191 13:31:44.613772 ==
3192 13:31:44.616542 Dram Type= 6, Freq= 0, CH_1, rank 0
3193 13:31:44.619482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3194 13:31:44.619619 ==
3195 13:31:44.623111 RX Vref Scan: 0
3196 13:31:44.623241
3197 13:31:44.626640 RX Vref 0 -> 0, step: 1
3198 13:31:44.626751
3199 13:31:44.626844 RX Delay -40 -> 252, step: 8
3200 13:31:44.632837 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3201 13:31:44.636473 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3202 13:31:44.639527 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3203 13:31:44.643057 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3204 13:31:44.646282 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3205 13:31:44.652885 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3206 13:31:44.656515 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3207 13:31:44.659588 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3208 13:31:44.663271 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3209 13:31:44.666441 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3210 13:31:44.672980 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3211 13:31:44.676287 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3212 13:31:44.679936 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3213 13:31:44.682980 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3214 13:31:44.686253 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3215 13:31:44.692875 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3216 13:31:44.692980 ==
3217 13:31:44.696716 Dram Type= 6, Freq= 0, CH_1, rank 0
3218 13:31:44.699952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3219 13:31:44.700069 ==
3220 13:31:44.700166 DQS Delay:
3221 13:31:44.703274 DQS0 = 0, DQS1 = 0
3222 13:31:44.703390 DQM Delay:
3223 13:31:44.706528 DQM0 = 114, DQM1 = 105
3224 13:31:44.706633 DQ Delay:
3225 13:31:44.709734 DQ0 =115, DQ1 =107, DQ2 =103, DQ3 =115
3226 13:31:44.712992 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3227 13:31:44.716304 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
3228 13:31:44.719488 DQ12 =115, DQ13 =111, DQ14 =111, DQ15 =111
3229 13:31:44.719591
3230 13:31:44.719696
3231 13:31:44.719786 ==
3232 13:31:44.723172 Dram Type= 6, Freq= 0, CH_1, rank 0
3233 13:31:44.729551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3234 13:31:44.729658 ==
3235 13:31:44.729750
3236 13:31:44.729843
3237 13:31:44.729938 TX Vref Scan disable
3238 13:31:44.733564 == TX Byte 0 ==
3239 13:31:44.736515 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3240 13:31:44.740165 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3241 13:31:44.743446 == TX Byte 1 ==
3242 13:31:44.746680 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3243 13:31:44.749814 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3244 13:31:44.753563 ==
3245 13:31:44.756560 Dram Type= 6, Freq= 0, CH_1, rank 0
3246 13:31:44.759917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3247 13:31:44.760027 ==
3248 13:31:44.771158 TX Vref=22, minBit 11, minWin=24, winSum=408
3249 13:31:44.774606 TX Vref=24, minBit 10, minWin=24, winSum=412
3250 13:31:44.778086 TX Vref=26, minBit 8, minWin=25, winSum=419
3251 13:31:44.781251 TX Vref=28, minBit 1, minWin=26, winSum=426
3252 13:31:44.784401 TX Vref=30, minBit 9, minWin=25, winSum=424
3253 13:31:44.791040 TX Vref=32, minBit 9, minWin=25, winSum=420
3254 13:31:44.794288 [TxChooseVref] Worse bit 1, Min win 26, Win sum 426, Final Vref 28
3255 13:31:44.794393
3256 13:31:44.797568 Final TX Range 1 Vref 28
3257 13:31:44.797671
3258 13:31:44.797765 ==
3259 13:31:44.800851 Dram Type= 6, Freq= 0, CH_1, rank 0
3260 13:31:44.804217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3261 13:31:44.804339 ==
3262 13:31:44.807486
3263 13:31:44.807588
3264 13:31:44.807677 TX Vref Scan disable
3265 13:31:44.811356 == TX Byte 0 ==
3266 13:31:44.814611 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3267 13:31:44.817884 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3268 13:31:44.821138 == TX Byte 1 ==
3269 13:31:44.824371 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3270 13:31:44.830880 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3271 13:31:44.830986
3272 13:31:44.831086 [DATLAT]
3273 13:31:44.831177 Freq=1200, CH1 RK0
3274 13:31:44.831269
3275 13:31:44.834351 DATLAT Default: 0xd
3276 13:31:44.834482 0, 0xFFFF, sum = 0
3277 13:31:44.837862 1, 0xFFFF, sum = 0
3278 13:31:44.838002 2, 0xFFFF, sum = 0
3279 13:31:44.841096 3, 0xFFFF, sum = 0
3280 13:31:44.844110 4, 0xFFFF, sum = 0
3281 13:31:44.844216 5, 0xFFFF, sum = 0
3282 13:31:44.847510 6, 0xFFFF, sum = 0
3283 13:31:44.847617 7, 0xFFFF, sum = 0
3284 13:31:44.851182 8, 0xFFFF, sum = 0
3285 13:31:44.851290 9, 0xFFFF, sum = 0
3286 13:31:44.854372 10, 0xFFFF, sum = 0
3287 13:31:44.854479 11, 0xFFFF, sum = 0
3288 13:31:44.857525 12, 0x0, sum = 1
3289 13:31:44.857633 13, 0x0, sum = 2
3290 13:31:44.860787 14, 0x0, sum = 3
3291 13:31:44.860897 15, 0x0, sum = 4
3292 13:31:44.860996 best_step = 13
3293 13:31:44.864190
3294 13:31:44.864288 ==
3295 13:31:44.867990 Dram Type= 6, Freq= 0, CH_1, rank 0
3296 13:31:44.871132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3297 13:31:44.871240 ==
3298 13:31:44.871334 RX Vref Scan: 1
3299 13:31:44.871470
3300 13:31:44.874182 Set Vref Range= 32 -> 127
3301 13:31:44.874291
3302 13:31:44.877781 RX Vref 32 -> 127, step: 1
3303 13:31:44.877886
3304 13:31:44.881178 RX Delay -21 -> 252, step: 4
3305 13:31:44.881284
3306 13:31:44.884058 Set Vref, RX VrefLevel [Byte0]: 32
3307 13:31:44.887565 [Byte1]: 32
3308 13:31:44.887667
3309 13:31:44.890902 Set Vref, RX VrefLevel [Byte0]: 33
3310 13:31:44.894557 [Byte1]: 33
3311 13:31:44.897563
3312 13:31:44.897721 Set Vref, RX VrefLevel [Byte0]: 34
3313 13:31:44.901088 [Byte1]: 34
3314 13:31:44.905582
3315 13:31:44.905698 Set Vref, RX VrefLevel [Byte0]: 35
3316 13:31:44.908727 [Byte1]: 35
3317 13:31:44.913199
3318 13:31:44.913314 Set Vref, RX VrefLevel [Byte0]: 36
3319 13:31:44.916507 [Byte1]: 36
3320 13:31:44.921055
3321 13:31:44.921197 Set Vref, RX VrefLevel [Byte0]: 37
3322 13:31:44.925012 [Byte1]: 37
3323 13:31:44.929591
3324 13:31:44.929709 Set Vref, RX VrefLevel [Byte0]: 38
3325 13:31:44.932589 [Byte1]: 38
3326 13:31:44.937049
3327 13:31:44.937149 Set Vref, RX VrefLevel [Byte0]: 39
3328 13:31:44.940329 [Byte1]: 39
3329 13:31:44.944943
3330 13:31:44.945047 Set Vref, RX VrefLevel [Byte0]: 40
3331 13:31:44.948212 [Byte1]: 40
3332 13:31:44.953076
3333 13:31:44.953177 Set Vref, RX VrefLevel [Byte0]: 41
3334 13:31:44.956147 [Byte1]: 41
3335 13:31:44.960808
3336 13:31:44.960914 Set Vref, RX VrefLevel [Byte0]: 42
3337 13:31:44.964419 [Byte1]: 42
3338 13:31:44.969024
3339 13:31:44.969135 Set Vref, RX VrefLevel [Byte0]: 43
3340 13:31:44.972290 [Byte1]: 43
3341 13:31:44.976768
3342 13:31:44.976887 Set Vref, RX VrefLevel [Byte0]: 44
3343 13:31:44.980093 [Byte1]: 44
3344 13:31:44.984462
3345 13:31:44.984569 Set Vref, RX VrefLevel [Byte0]: 45
3346 13:31:44.988157 [Byte1]: 45
3347 13:31:44.992521
3348 13:31:44.992632 Set Vref, RX VrefLevel [Byte0]: 46
3349 13:31:44.996117 [Byte1]: 46
3350 13:31:45.000546
3351 13:31:45.000654 Set Vref, RX VrefLevel [Byte0]: 47
3352 13:31:45.003784 [Byte1]: 47
3353 13:31:45.008570
3354 13:31:45.008681 Set Vref, RX VrefLevel [Byte0]: 48
3355 13:31:45.011445 [Byte1]: 48
3356 13:31:45.016484
3357 13:31:45.016593 Set Vref, RX VrefLevel [Byte0]: 49
3358 13:31:45.019709 [Byte1]: 49
3359 13:31:45.024360
3360 13:31:45.024462 Set Vref, RX VrefLevel [Byte0]: 50
3361 13:31:45.027530 [Byte1]: 50
3362 13:31:45.032111
3363 13:31:45.032218 Set Vref, RX VrefLevel [Byte0]: 51
3364 13:31:45.035281 [Byte1]: 51
3365 13:31:45.039792
3366 13:31:45.039902 Set Vref, RX VrefLevel [Byte0]: 52
3367 13:31:45.043559 [Byte1]: 52
3368 13:31:45.048012
3369 13:31:45.048120 Set Vref, RX VrefLevel [Byte0]: 53
3370 13:31:45.051289 [Byte1]: 53
3371 13:31:45.055803
3372 13:31:45.055906 Set Vref, RX VrefLevel [Byte0]: 54
3373 13:31:45.059504 [Byte1]: 54
3374 13:31:45.064050
3375 13:31:45.064161 Set Vref, RX VrefLevel [Byte0]: 55
3376 13:31:45.067048 [Byte1]: 55
3377 13:31:45.071734
3378 13:31:45.071837 Set Vref, RX VrefLevel [Byte0]: 56
3379 13:31:45.075319 [Byte1]: 56
3380 13:31:45.079802
3381 13:31:45.079922 Set Vref, RX VrefLevel [Byte0]: 57
3382 13:31:45.083114 [Byte1]: 57
3383 13:31:45.087608
3384 13:31:45.087715 Set Vref, RX VrefLevel [Byte0]: 58
3385 13:31:45.090785 [Byte1]: 58
3386 13:31:45.095252
3387 13:31:45.095356 Set Vref, RX VrefLevel [Byte0]: 59
3388 13:31:45.099021 [Byte1]: 59
3389 13:31:45.103359
3390 13:31:45.103508 Set Vref, RX VrefLevel [Byte0]: 60
3391 13:31:45.106605 [Byte1]: 60
3392 13:31:45.111156
3393 13:31:45.111268 Set Vref, RX VrefLevel [Byte0]: 61
3394 13:31:45.114432 [Byte1]: 61
3395 13:31:45.119458
3396 13:31:45.119562 Set Vref, RX VrefLevel [Byte0]: 62
3397 13:31:45.122445 [Byte1]: 62
3398 13:31:45.127204
3399 13:31:45.127313 Set Vref, RX VrefLevel [Byte0]: 63
3400 13:31:45.130431 [Byte1]: 63
3401 13:31:45.134922
3402 13:31:45.135026 Set Vref, RX VrefLevel [Byte0]: 64
3403 13:31:45.138186 [Byte1]: 64
3404 13:31:45.143357
3405 13:31:45.143502 Set Vref, RX VrefLevel [Byte0]: 65
3406 13:31:45.146596 [Byte1]: 65
3407 13:31:45.150953
3408 13:31:45.151059 Set Vref, RX VrefLevel [Byte0]: 66
3409 13:31:45.154326 [Byte1]: 66
3410 13:31:45.158855
3411 13:31:45.158962 Set Vref, RX VrefLevel [Byte0]: 67
3412 13:31:45.162077 [Byte1]: 67
3413 13:31:45.167073
3414 13:31:45.167178 Set Vref, RX VrefLevel [Byte0]: 68
3415 13:31:45.170275 [Byte1]: 68
3416 13:31:45.175028
3417 13:31:45.175133 Final RX Vref Byte 0 = 59 to rank0
3418 13:31:45.177874 Final RX Vref Byte 1 = 49 to rank0
3419 13:31:45.181512 Final RX Vref Byte 0 = 59 to rank1
3420 13:31:45.185011 Final RX Vref Byte 1 = 49 to rank1==
3421 13:31:45.187991 Dram Type= 6, Freq= 0, CH_1, rank 0
3422 13:31:45.194786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3423 13:31:45.194895 ==
3424 13:31:45.194991 DQS Delay:
3425 13:31:45.195119 DQS0 = 0, DQS1 = 0
3426 13:31:45.198048 DQM Delay:
3427 13:31:45.198151 DQM0 = 114, DQM1 = 105
3428 13:31:45.201837 DQ Delay:
3429 13:31:45.204770 DQ0 =116, DQ1 =110, DQ2 =106, DQ3 =110
3430 13:31:45.208330 DQ4 =112, DQ5 =122, DQ6 =124, DQ7 =112
3431 13:31:45.211358 DQ8 =92, DQ9 =98, DQ10 =104, DQ11 =100
3432 13:31:45.214598 DQ12 =112, DQ13 =112, DQ14 =114, DQ15 =112
3433 13:31:45.214728
3434 13:31:45.214819
3435 13:31:45.221637 [DQSOSCAuto] RK0, (LSB)MR18= 0xedf4, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 417 ps
3436 13:31:45.224928 CH1 RK0: MR19=303, MR18=EDF4
3437 13:31:45.231228 CH1_RK0: MR19=0x303, MR18=0xEDF4, DQSOSC=415, MR23=63, INC=38, DEC=25
3438 13:31:45.231330
3439 13:31:45.234788 ----->DramcWriteLeveling(PI) begin...
3440 13:31:45.234895 ==
3441 13:31:45.238359 Dram Type= 6, Freq= 0, CH_1, rank 1
3442 13:31:45.241502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3443 13:31:45.244713 ==
3444 13:31:45.244815 Write leveling (Byte 0): 27 => 27
3445 13:31:45.247964 Write leveling (Byte 1): 27 => 27
3446 13:31:45.251237 DramcWriteLeveling(PI) end<-----
3447 13:31:45.251337
3448 13:31:45.251471 ==
3449 13:31:45.254933 Dram Type= 6, Freq= 0, CH_1, rank 1
3450 13:31:45.261480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3451 13:31:45.261588 ==
3452 13:31:45.261684 [Gating] SW mode calibration
3453 13:31:45.271299 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3454 13:31:45.274532 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3455 13:31:45.278308 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3456 13:31:45.284660 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3457 13:31:45.287842 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3458 13:31:45.291610 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3459 13:31:45.297757 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3460 13:31:45.301279 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3461 13:31:45.304443 0 15 24 | B1->B0 | 3434 2424 | 0 0 | (0 0) (1 0)
3462 13:31:45.311655 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
3463 13:31:45.314714 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3464 13:31:45.318151 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3465 13:31:45.324605 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3466 13:31:45.327825 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3467 13:31:45.331611 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3468 13:31:45.338097 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3469 13:31:45.341177 1 0 24 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
3470 13:31:45.344821 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3471 13:31:45.351462 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 13:31:45.354588 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 13:31:45.357724 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 13:31:45.364216 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3475 13:31:45.367501 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 13:31:45.371258 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 13:31:45.377656 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3478 13:31:45.380974 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3479 13:31:45.384174 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 13:31:45.390502 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 13:31:45.394303 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 13:31:45.397460 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 13:31:45.403977 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 13:31:45.406971 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 13:31:45.410611 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 13:31:45.417461 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 13:31:45.420606 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 13:31:45.423555 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 13:31:45.430306 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 13:31:45.433596 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 13:31:45.436806 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 13:31:45.443823 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 13:31:45.447004 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3494 13:31:45.450126 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3495 13:31:45.453328 Total UI for P1: 0, mck2ui 16
3496 13:31:45.456549 best dqsien dly found for B0: ( 1, 3, 24)
3497 13:31:45.460310 Total UI for P1: 0, mck2ui 16
3498 13:31:45.463334 best dqsien dly found for B1: ( 1, 3, 26)
3499 13:31:45.466742 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3500 13:31:45.469976 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3501 13:31:45.470080
3502 13:31:45.476316 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3503 13:31:45.479539 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3504 13:31:45.479644 [Gating] SW calibration Done
3505 13:31:45.482719 ==
3506 13:31:45.486626 Dram Type= 6, Freq= 0, CH_1, rank 1
3507 13:31:45.489911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3508 13:31:45.490015 ==
3509 13:31:45.490116 RX Vref Scan: 0
3510 13:31:45.490210
3511 13:31:45.493050 RX Vref 0 -> 0, step: 1
3512 13:31:45.493152
3513 13:31:45.496129 RX Delay -40 -> 252, step: 8
3514 13:31:45.499319 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
3515 13:31:45.503070 iDelay=200, Bit 1, Center 103 (32 ~ 175) 144
3516 13:31:45.506275 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3517 13:31:45.512524 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3518 13:31:45.516101 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3519 13:31:45.519222 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3520 13:31:45.522301 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3521 13:31:45.529254 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3522 13:31:45.532261 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3523 13:31:45.535808 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3524 13:31:45.538981 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3525 13:31:45.542675 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3526 13:31:45.548940 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3527 13:31:45.552846 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3528 13:31:45.556006 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3529 13:31:45.559224 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3530 13:31:45.559329 ==
3531 13:31:45.562499 Dram Type= 6, Freq= 0, CH_1, rank 1
3532 13:31:45.565708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3533 13:31:45.568780 ==
3534 13:31:45.568886 DQS Delay:
3535 13:31:45.568983 DQS0 = 0, DQS1 = 0
3536 13:31:45.571942 DQM Delay:
3537 13:31:45.572044 DQM0 = 110, DQM1 = 109
3538 13:31:45.575623 DQ Delay:
3539 13:31:45.578588 DQ0 =111, DQ1 =103, DQ2 =99, DQ3 =107
3540 13:31:45.582354 DQ4 =107, DQ5 =123, DQ6 =119, DQ7 =111
3541 13:31:45.585563 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3542 13:31:45.588730 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3543 13:31:45.588834
3544 13:31:45.588901
3545 13:31:45.588961 ==
3546 13:31:45.592111 Dram Type= 6, Freq= 0, CH_1, rank 1
3547 13:31:45.595232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3548 13:31:45.598328 ==
3549 13:31:45.598433
3550 13:31:45.598531
3551 13:31:45.598623 TX Vref Scan disable
3552 13:31:45.601542 == TX Byte 0 ==
3553 13:31:45.605306 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3554 13:31:45.608659 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3555 13:31:45.611881 == TX Byte 1 ==
3556 13:31:45.615063 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3557 13:31:45.618286 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3558 13:31:45.621429 ==
3559 13:31:45.621532 Dram Type= 6, Freq= 0, CH_1, rank 1
3560 13:31:45.628280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3561 13:31:45.628359 ==
3562 13:31:45.639332 TX Vref=22, minBit 1, minWin=26, winSum=420
3563 13:31:45.642160 TX Vref=24, minBit 0, minWin=26, winSum=422
3564 13:31:45.646030 TX Vref=26, minBit 1, minWin=26, winSum=426
3565 13:31:45.649207 TX Vref=28, minBit 3, minWin=26, winSum=427
3566 13:31:45.652373 TX Vref=30, minBit 3, minWin=26, winSum=432
3567 13:31:45.658917 TX Vref=32, minBit 1, minWin=25, winSum=430
3568 13:31:45.662046 [TxChooseVref] Worse bit 3, Min win 26, Win sum 432, Final Vref 30
3569 13:31:45.662153
3570 13:31:45.665960 Final TX Range 1 Vref 30
3571 13:31:45.666064
3572 13:31:45.666159 ==
3573 13:31:45.669113 Dram Type= 6, Freq= 0, CH_1, rank 1
3574 13:31:45.672362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3575 13:31:45.672471 ==
3576 13:31:45.675656
3577 13:31:45.675738
3578 13:31:45.675804 TX Vref Scan disable
3579 13:31:45.678885 == TX Byte 0 ==
3580 13:31:45.682032 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3581 13:31:45.688751 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3582 13:31:45.688861 == TX Byte 1 ==
3583 13:31:45.691860 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3584 13:31:45.698411 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3585 13:31:45.698517
3586 13:31:45.698610 [DATLAT]
3587 13:31:45.698703 Freq=1200, CH1 RK1
3588 13:31:45.698796
3589 13:31:45.701621 DATLAT Default: 0xd
3590 13:31:45.705384 0, 0xFFFF, sum = 0
3591 13:31:45.705490 1, 0xFFFF, sum = 0
3592 13:31:45.708582 2, 0xFFFF, sum = 0
3593 13:31:45.708661 3, 0xFFFF, sum = 0
3594 13:31:45.711726 4, 0xFFFF, sum = 0
3595 13:31:45.711833 5, 0xFFFF, sum = 0
3596 13:31:45.714978 6, 0xFFFF, sum = 0
3597 13:31:45.715083 7, 0xFFFF, sum = 0
3598 13:31:45.718156 8, 0xFFFF, sum = 0
3599 13:31:45.718262 9, 0xFFFF, sum = 0
3600 13:31:45.721879 10, 0xFFFF, sum = 0
3601 13:31:45.721985 11, 0xFFFF, sum = 0
3602 13:31:45.725097 12, 0x0, sum = 1
3603 13:31:45.725198 13, 0x0, sum = 2
3604 13:31:45.728296 14, 0x0, sum = 3
3605 13:31:45.728372 15, 0x0, sum = 4
3606 13:31:45.731411 best_step = 13
3607 13:31:45.731511
3608 13:31:45.731607 ==
3609 13:31:45.735050 Dram Type= 6, Freq= 0, CH_1, rank 1
3610 13:31:45.738323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3611 13:31:45.738429 ==
3612 13:31:45.741450 RX Vref Scan: 0
3613 13:31:45.741554
3614 13:31:45.741647 RX Vref 0 -> 0, step: 1
3615 13:31:45.741744
3616 13:31:45.744609 RX Delay -21 -> 252, step: 4
3617 13:31:45.751658 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3618 13:31:45.754892 iDelay=195, Bit 1, Center 108 (43 ~ 174) 132
3619 13:31:45.758159 iDelay=195, Bit 2, Center 102 (31 ~ 174) 144
3620 13:31:45.761481 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3621 13:31:45.764621 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3622 13:31:45.771692 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3623 13:31:45.774873 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3624 13:31:45.778030 iDelay=195, Bit 7, Center 108 (39 ~ 178) 140
3625 13:31:45.781254 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3626 13:31:45.784541 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3627 13:31:45.791619 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3628 13:31:45.794729 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3629 13:31:45.797589 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3630 13:31:45.801164 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3631 13:31:45.804431 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3632 13:31:45.811365 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3633 13:31:45.811452 ==
3634 13:31:45.814408 Dram Type= 6, Freq= 0, CH_1, rank 1
3635 13:31:45.817614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3636 13:31:45.817715 ==
3637 13:31:45.817808 DQS Delay:
3638 13:31:45.820899 DQS0 = 0, DQS1 = 0
3639 13:31:45.820999 DQM Delay:
3640 13:31:45.824115 DQM0 = 111, DQM1 = 110
3641 13:31:45.824215 DQ Delay:
3642 13:31:45.827354 DQ0 =114, DQ1 =108, DQ2 =102, DQ3 =108
3643 13:31:45.831004 DQ4 =108, DQ5 =120, DQ6 =122, DQ7 =108
3644 13:31:45.834337 DQ8 =94, DQ9 =102, DQ10 =110, DQ11 =104
3645 13:31:45.837592 DQ12 =118, DQ13 =116, DQ14 =118, DQ15 =118
3646 13:31:45.837701
3647 13:31:45.840639
3648 13:31:45.847663 [DQSOSCAuto] RK1, (LSB)MR18= 0xf504, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 414 ps
3649 13:31:45.850826 CH1 RK1: MR19=304, MR18=F504
3650 13:31:45.857459 CH1_RK1: MR19=0x304, MR18=0xF504, DQSOSC=408, MR23=63, INC=39, DEC=26
3651 13:31:45.860496 [RxdqsGatingPostProcess] freq 1200
3652 13:31:45.864303 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3653 13:31:45.867450 best DQS0 dly(2T, 0.5T) = (0, 11)
3654 13:31:45.870722 best DQS1 dly(2T, 0.5T) = (0, 11)
3655 13:31:45.874058 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3656 13:31:45.877271 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3657 13:31:45.880442 best DQS0 dly(2T, 0.5T) = (0, 11)
3658 13:31:45.883627 best DQS1 dly(2T, 0.5T) = (0, 11)
3659 13:31:45.886830 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3660 13:31:45.890521 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3661 13:31:45.893785 Pre-setting of DQS Precalculation
3662 13:31:45.897000 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3663 13:31:45.903391 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3664 13:31:45.913564 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3665 13:31:45.913660
3666 13:31:45.913727
3667 13:31:45.916755 [Calibration Summary] 2400 Mbps
3668 13:31:45.916837 CH 0, Rank 0
3669 13:31:45.919899 SW Impedance : PASS
3670 13:31:45.919986 DUTY Scan : NO K
3671 13:31:45.923838 ZQ Calibration : PASS
3672 13:31:45.926487 Jitter Meter : NO K
3673 13:31:45.926568 CBT Training : PASS
3674 13:31:45.930344 Write leveling : PASS
3675 13:31:45.933496 RX DQS gating : PASS
3676 13:31:45.933607 RX DQ/DQS(RDDQC) : PASS
3677 13:31:45.936682 TX DQ/DQS : PASS
3678 13:31:45.936788 RX DATLAT : PASS
3679 13:31:45.939934 RX DQ/DQS(Engine): PASS
3680 13:31:45.943201 TX OE : NO K
3681 13:31:45.943304 All Pass.
3682 13:31:45.943407
3683 13:31:45.946380 CH 0, Rank 1
3684 13:31:45.946490 SW Impedance : PASS
3685 13:31:45.950224 DUTY Scan : NO K
3686 13:31:45.950339 ZQ Calibration : PASS
3687 13:31:45.953369 Jitter Meter : NO K
3688 13:31:45.956557 CBT Training : PASS
3689 13:31:45.956664 Write leveling : PASS
3690 13:31:45.959855 RX DQS gating : PASS
3691 13:31:45.962960 RX DQ/DQS(RDDQC) : PASS
3692 13:31:45.963065 TX DQ/DQS : PASS
3693 13:31:45.966634 RX DATLAT : PASS
3694 13:31:45.969616 RX DQ/DQS(Engine): PASS
3695 13:31:45.969720 TX OE : NO K
3696 13:31:45.973256 All Pass.
3697 13:31:45.973365
3698 13:31:45.973458 CH 1, Rank 0
3699 13:31:45.976481 SW Impedance : PASS
3700 13:31:45.976587 DUTY Scan : NO K
3701 13:31:45.979588 ZQ Calibration : PASS
3702 13:31:45.982876 Jitter Meter : NO K
3703 13:31:45.982977 CBT Training : PASS
3704 13:31:45.986742 Write leveling : PASS
3705 13:31:45.989855 RX DQS gating : PASS
3706 13:31:45.989959 RX DQ/DQS(RDDQC) : PASS
3707 13:31:45.993027 TX DQ/DQS : PASS
3708 13:31:45.996241 RX DATLAT : PASS
3709 13:31:45.996346 RX DQ/DQS(Engine): PASS
3710 13:31:45.999468 TX OE : NO K
3711 13:31:45.999577 All Pass.
3712 13:31:45.999673
3713 13:31:46.002677 CH 1, Rank 1
3714 13:31:46.002779 SW Impedance : PASS
3715 13:31:46.006529 DUTY Scan : NO K
3716 13:31:46.006630 ZQ Calibration : PASS
3717 13:31:46.009577 Jitter Meter : NO K
3718 13:31:46.012846 CBT Training : PASS
3719 13:31:46.012953 Write leveling : PASS
3720 13:31:46.016016 RX DQS gating : PASS
3721 13:31:46.019765 RX DQ/DQS(RDDQC) : PASS
3722 13:31:46.019867 TX DQ/DQS : PASS
3723 13:31:46.022692 RX DATLAT : PASS
3724 13:31:46.026152 RX DQ/DQS(Engine): PASS
3725 13:31:46.026257 TX OE : NO K
3726 13:31:46.029762 All Pass.
3727 13:31:46.029868
3728 13:31:46.029965 DramC Write-DBI off
3729 13:31:46.033049 PER_BANK_REFRESH: Hybrid Mode
3730 13:31:46.033149 TX_TRACKING: ON
3731 13:31:46.042782 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3732 13:31:46.046058 [FAST_K] Save calibration result to emmc
3733 13:31:46.049240 dramc_set_vcore_voltage set vcore to 650000
3734 13:31:46.052846 Read voltage for 600, 5
3735 13:31:46.052952 Vio18 = 0
3736 13:31:46.055943 Vcore = 650000
3737 13:31:46.056045 Vdram = 0
3738 13:31:46.056140 Vddq = 0
3739 13:31:46.059056 Vmddr = 0
3740 13:31:46.062858 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3741 13:31:46.069213 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3742 13:31:46.069320 MEM_TYPE=3, freq_sel=19
3743 13:31:46.072723 sv_algorithm_assistance_LP4_1600
3744 13:31:46.079449 ============ PULL DRAM RESETB DOWN ============
3745 13:31:46.082274 ========== PULL DRAM RESETB DOWN end =========
3746 13:31:46.086087 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3747 13:31:46.089465 ===================================
3748 13:31:46.092653 LPDDR4 DRAM CONFIGURATION
3749 13:31:46.095887 ===================================
3750 13:31:46.095970 EX_ROW_EN[0] = 0x0
3751 13:31:46.099048 EX_ROW_EN[1] = 0x0
3752 13:31:46.102331 LP4Y_EN = 0x0
3753 13:31:46.102413 WORK_FSP = 0x0
3754 13:31:46.105568 WL = 0x2
3755 13:31:46.105650 RL = 0x2
3756 13:31:46.108841 BL = 0x2
3757 13:31:46.108924 RPST = 0x0
3758 13:31:46.112137 RD_PRE = 0x0
3759 13:31:46.112219 WR_PRE = 0x1
3760 13:31:46.115907 WR_PST = 0x0
3761 13:31:46.115988 DBI_WR = 0x0
3762 13:31:46.119127 DBI_RD = 0x0
3763 13:31:46.119209 OTF = 0x1
3764 13:31:46.122358 ===================================
3765 13:31:46.125675 ===================================
3766 13:31:46.128749 ANA top config
3767 13:31:46.132353 ===================================
3768 13:31:46.132435 DLL_ASYNC_EN = 0
3769 13:31:46.135413 ALL_SLAVE_EN = 1
3770 13:31:46.139060 NEW_RANK_MODE = 1
3771 13:31:46.141993 DLL_IDLE_MODE = 1
3772 13:31:46.145105 LP45_APHY_COMB_EN = 1
3773 13:31:46.145187 TX_ODT_DIS = 1
3774 13:31:46.149069 NEW_8X_MODE = 1
3775 13:31:46.152300 ===================================
3776 13:31:46.155548 ===================================
3777 13:31:46.158619 data_rate = 1200
3778 13:31:46.162016 CKR = 1
3779 13:31:46.165138 DQ_P2S_RATIO = 8
3780 13:31:46.168360 ===================================
3781 13:31:46.172064 CA_P2S_RATIO = 8
3782 13:31:46.172165 DQ_CA_OPEN = 0
3783 13:31:46.175226 DQ_SEMI_OPEN = 0
3784 13:31:46.178336 CA_SEMI_OPEN = 0
3785 13:31:46.182056 CA_FULL_RATE = 0
3786 13:31:46.185248 DQ_CKDIV4_EN = 1
3787 13:31:46.188198 CA_CKDIV4_EN = 1
3788 13:31:46.188325 CA_PREDIV_EN = 0
3789 13:31:46.191665 PH8_DLY = 0
3790 13:31:46.195294 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3791 13:31:46.198428 DQ_AAMCK_DIV = 4
3792 13:31:46.201643 CA_AAMCK_DIV = 4
3793 13:31:46.204923 CA_ADMCK_DIV = 4
3794 13:31:46.205034 DQ_TRACK_CA_EN = 0
3795 13:31:46.208088 CA_PICK = 600
3796 13:31:46.211400 CA_MCKIO = 600
3797 13:31:46.214636 MCKIO_SEMI = 0
3798 13:31:46.218340 PLL_FREQ = 2288
3799 13:31:46.221451 DQ_UI_PI_RATIO = 32
3800 13:31:46.224598 CA_UI_PI_RATIO = 0
3801 13:31:46.227874 ===================================
3802 13:31:46.231105 ===================================
3803 13:31:46.231221 memory_type:LPDDR4
3804 13:31:46.234869 GP_NUM : 10
3805 13:31:46.238137 SRAM_EN : 1
3806 13:31:46.238262 MD32_EN : 0
3807 13:31:46.241153 ===================================
3808 13:31:46.244898 [ANA_INIT] >>>>>>>>>>>>>>
3809 13:31:46.247956 <<<<<< [CONFIGURE PHASE]: ANA_TX
3810 13:31:46.251435 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3811 13:31:46.254552 ===================================
3812 13:31:46.257777 data_rate = 1200,PCW = 0X5800
3813 13:31:46.261052 ===================================
3814 13:31:46.264837 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3815 13:31:46.267920 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3816 13:31:46.274769 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3817 13:31:46.277568 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3818 13:31:46.281332 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3819 13:31:46.284525 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3820 13:31:46.287753 [ANA_INIT] flow start
3821 13:31:46.291076 [ANA_INIT] PLL >>>>>>>>
3822 13:31:46.291160 [ANA_INIT] PLL <<<<<<<<
3823 13:31:46.294252 [ANA_INIT] MIDPI >>>>>>>>
3824 13:31:46.297493 [ANA_INIT] MIDPI <<<<<<<<
3825 13:31:46.297577 [ANA_INIT] DLL >>>>>>>>
3826 13:31:46.301267 [ANA_INIT] flow end
3827 13:31:46.304277 ============ LP4 DIFF to SE enter ============
3828 13:31:46.310805 ============ LP4 DIFF to SE exit ============
3829 13:31:46.310897 [ANA_INIT] <<<<<<<<<<<<<
3830 13:31:46.314654 [Flow] Enable top DCM control >>>>>
3831 13:31:46.317945 [Flow] Enable top DCM control <<<<<
3832 13:31:46.321279 Enable DLL master slave shuffle
3833 13:31:46.327376 ==============================================================
3834 13:31:46.327462 Gating Mode config
3835 13:31:46.333853 ==============================================================
3836 13:31:46.337652 Config description:
3837 13:31:46.347165 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3838 13:31:46.354219 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3839 13:31:46.357310 SELPH_MODE 0: By rank 1: By Phase
3840 13:31:46.364062 ==============================================================
3841 13:31:46.367139 GAT_TRACK_EN = 1
3842 13:31:46.370252 RX_GATING_MODE = 2
3843 13:31:46.370335 RX_GATING_TRACK_MODE = 2
3844 13:31:46.373549 SELPH_MODE = 1
3845 13:31:46.377313 PICG_EARLY_EN = 1
3846 13:31:46.380424 VALID_LAT_VALUE = 1
3847 13:31:46.386622 ==============================================================
3848 13:31:46.390519 Enter into Gating configuration >>>>
3849 13:31:46.393727 Exit from Gating configuration <<<<
3850 13:31:46.396346 Enter into DVFS_PRE_config >>>>>
3851 13:31:46.406581 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3852 13:31:46.409758 Exit from DVFS_PRE_config <<<<<
3853 13:31:46.412982 Enter into PICG configuration >>>>
3854 13:31:46.416215 Exit from PICG configuration <<<<
3855 13:31:46.419786 [RX_INPUT] configuration >>>>>
3856 13:31:46.422926 [RX_INPUT] configuration <<<<<
3857 13:31:46.426594 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3858 13:31:46.433080 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3859 13:31:46.439625 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3860 13:31:46.446574 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3861 13:31:46.449847 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3862 13:31:46.456344 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3863 13:31:46.459527 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3864 13:31:46.466223 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3865 13:31:46.469339 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3866 13:31:46.473064 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3867 13:31:46.476074 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3868 13:31:46.482796 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3869 13:31:46.485848 ===================================
3870 13:31:46.489573 LPDDR4 DRAM CONFIGURATION
3871 13:31:46.492742 ===================================
3872 13:31:46.492845 EX_ROW_EN[0] = 0x0
3873 13:31:46.496007 EX_ROW_EN[1] = 0x0
3874 13:31:46.496090 LP4Y_EN = 0x0
3875 13:31:46.499254 WORK_FSP = 0x0
3876 13:31:46.499359 WL = 0x2
3877 13:31:46.502355 RL = 0x2
3878 13:31:46.502457 BL = 0x2
3879 13:31:46.506114 RPST = 0x0
3880 13:31:46.506217 RD_PRE = 0x0
3881 13:31:46.509350 WR_PRE = 0x1
3882 13:31:46.509450 WR_PST = 0x0
3883 13:31:46.512625 DBI_WR = 0x0
3884 13:31:46.512729 DBI_RD = 0x0
3885 13:31:46.515800 OTF = 0x1
3886 13:31:46.519000 ===================================
3887 13:31:46.522276 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3888 13:31:46.525992 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3889 13:31:46.532581 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3890 13:31:46.535576 ===================================
3891 13:31:46.538772 LPDDR4 DRAM CONFIGURATION
3892 13:31:46.542214 ===================================
3893 13:31:46.542299 EX_ROW_EN[0] = 0x10
3894 13:31:46.545750 EX_ROW_EN[1] = 0x0
3895 13:31:46.545835 LP4Y_EN = 0x0
3896 13:31:46.548979 WORK_FSP = 0x0
3897 13:31:46.549063 WL = 0x2
3898 13:31:46.552142 RL = 0x2
3899 13:31:46.552226 BL = 0x2
3900 13:31:46.555348 RPST = 0x0
3901 13:31:46.555441 RD_PRE = 0x0
3902 13:31:46.558550 WR_PRE = 0x1
3903 13:31:46.558634 WR_PST = 0x0
3904 13:31:46.561743 DBI_WR = 0x0
3905 13:31:46.564891 DBI_RD = 0x0
3906 13:31:46.564991 OTF = 0x1
3907 13:31:46.568582 ===================================
3908 13:31:46.575081 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3909 13:31:46.578757 nWR fixed to 30
3910 13:31:46.581873 [ModeRegInit_LP4] CH0 RK0
3911 13:31:46.581955 [ModeRegInit_LP4] CH0 RK1
3912 13:31:46.585521 [ModeRegInit_LP4] CH1 RK0
3913 13:31:46.588705 [ModeRegInit_LP4] CH1 RK1
3914 13:31:46.588787 match AC timing 17
3915 13:31:46.595289 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3916 13:31:46.598442 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3917 13:31:46.601809 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3918 13:31:46.608748 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3919 13:31:46.611962 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3920 13:31:46.612044 ==
3921 13:31:46.615312 Dram Type= 6, Freq= 0, CH_0, rank 0
3922 13:31:46.618475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3923 13:31:46.618557 ==
3924 13:31:46.624940 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3925 13:31:46.631512 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3926 13:31:46.634565 [CA 0] Center 37 (7~67) winsize 61
3927 13:31:46.638292 [CA 1] Center 37 (7~67) winsize 61
3928 13:31:46.641321 [CA 2] Center 35 (5~65) winsize 61
3929 13:31:46.644750 [CA 3] Center 35 (5~65) winsize 61
3930 13:31:46.647869 [CA 4] Center 34 (4~65) winsize 62
3931 13:31:46.651678 [CA 5] Center 33 (3~64) winsize 62
3932 13:31:46.651759
3933 13:31:46.654945 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3934 13:31:46.655026
3935 13:31:46.658095 [CATrainingPosCal] consider 1 rank data
3936 13:31:46.661300 u2DelayCellTimex100 = 270/100 ps
3937 13:31:46.664621 CA0 delay=37 (7~67),Diff = 4 PI (38 cell)
3938 13:31:46.667809 CA1 delay=37 (7~67),Diff = 4 PI (38 cell)
3939 13:31:46.671009 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3940 13:31:46.677644 CA3 delay=35 (5~65),Diff = 2 PI (19 cell)
3941 13:31:46.680928 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
3942 13:31:46.684024 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3943 13:31:46.684134
3944 13:31:46.687815 CA PerBit enable=1, Macro0, CA PI delay=33
3945 13:31:46.687909
3946 13:31:46.691020 [CBTSetCACLKResult] CA Dly = 33
3947 13:31:46.691117 CS Dly: 6 (0~37)
3948 13:31:46.691181 ==
3949 13:31:46.694150 Dram Type= 6, Freq= 0, CH_0, rank 1
3950 13:31:46.700946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3951 13:31:46.701041 ==
3952 13:31:46.703965 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3953 13:31:46.710797 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3954 13:31:46.714027 [CA 0] Center 37 (7~67) winsize 61
3955 13:31:46.717824 [CA 1] Center 37 (7~67) winsize 61
3956 13:31:46.721033 [CA 2] Center 35 (5~65) winsize 61
3957 13:31:46.724323 [CA 3] Center 35 (5~65) winsize 61
3958 13:31:46.727514 [CA 4] Center 34 (3~65) winsize 63
3959 13:31:46.730769 [CA 5] Center 33 (3~64) winsize 62
3960 13:31:46.730849
3961 13:31:46.733951 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3962 13:31:46.734062
3963 13:31:46.737818 [CATrainingPosCal] consider 2 rank data
3964 13:31:46.741021 u2DelayCellTimex100 = 270/100 ps
3965 13:31:46.744165 CA0 delay=37 (7~67),Diff = 4 PI (38 cell)
3966 13:31:46.750488 CA1 delay=37 (7~67),Diff = 4 PI (38 cell)
3967 13:31:46.754212 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3968 13:31:46.757208 CA3 delay=35 (5~65),Diff = 2 PI (19 cell)
3969 13:31:46.760670 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
3970 13:31:46.763839 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3971 13:31:46.763936
3972 13:31:46.767027 CA PerBit enable=1, Macro0, CA PI delay=33
3973 13:31:46.767107
3974 13:31:46.770329 [CBTSetCACLKResult] CA Dly = 33
3975 13:31:46.773565 CS Dly: 5 (0~36)
3976 13:31:46.773685
3977 13:31:46.777451 ----->DramcWriteLeveling(PI) begin...
3978 13:31:46.777532 ==
3979 13:31:46.780683 Dram Type= 6, Freq= 0, CH_0, rank 0
3980 13:31:46.783887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3981 13:31:46.784012 ==
3982 13:31:46.787098 Write leveling (Byte 0): 34 => 34
3983 13:31:46.790222 Write leveling (Byte 1): 32 => 32
3984 13:31:46.794033 DramcWriteLeveling(PI) end<-----
3985 13:31:46.794115
3986 13:31:46.794180 ==
3987 13:31:46.797234 Dram Type= 6, Freq= 0, CH_0, rank 0
3988 13:31:46.800372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3989 13:31:46.800454 ==
3990 13:31:46.803947 [Gating] SW mode calibration
3991 13:31:46.810169 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3992 13:31:46.816713 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3993 13:31:46.820391 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3994 13:31:46.823624 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3995 13:31:46.830573 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3996 13:31:46.833792 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
3997 13:31:46.837123 0 9 16 | B1->B0 | 3333 2828 | 1 1 | (1 0) (1 0)
3998 13:31:46.843537 0 9 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3999 13:31:46.846754 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 13:31:46.850045 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 13:31:46.856571 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4002 13:31:46.859937 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4003 13:31:46.863586 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4004 13:31:46.870044 0 10 12 | B1->B0 | 2424 2a2a | 0 0 | (0 0) (0 0)
4005 13:31:46.873468 0 10 16 | B1->B0 | 2e2e 3d3d | 1 0 | (0 0) (0 0)
4006 13:31:46.876531 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4007 13:31:46.883074 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 13:31:46.886991 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 13:31:46.890123 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 13:31:46.893400 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 13:31:46.899801 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 13:31:46.903601 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4013 13:31:46.906820 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 13:31:46.913151 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 13:31:46.916849 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 13:31:46.919969 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 13:31:46.926579 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 13:31:46.929717 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 13:31:46.933108 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 13:31:46.939522 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 13:31:46.943205 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 13:31:46.946582 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 13:31:46.952978 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 13:31:46.956186 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 13:31:46.959596 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 13:31:46.966037 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 13:31:46.969366 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 13:31:46.972660 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4029 13:31:46.975910 Total UI for P1: 0, mck2ui 16
4030 13:31:46.979711 best dqsien dly found for B0: ( 0, 13, 10)
4031 13:31:46.986143 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4032 13:31:46.989219 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4033 13:31:46.992570 Total UI for P1: 0, mck2ui 16
4034 13:31:46.996070 best dqsien dly found for B1: ( 0, 13, 16)
4035 13:31:46.999019 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4036 13:31:47.002880 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4037 13:31:47.002983
4038 13:31:47.005994 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4039 13:31:47.009087 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4040 13:31:47.012284 [Gating] SW calibration Done
4041 13:31:47.012368 ==
4042 13:31:47.016066 Dram Type= 6, Freq= 0, CH_0, rank 0
4043 13:31:47.022872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4044 13:31:47.022956 ==
4045 13:31:47.023022 RX Vref Scan: 0
4046 13:31:47.023084
4047 13:31:47.026026 RX Vref 0 -> 0, step: 1
4048 13:31:47.026109
4049 13:31:47.029127 RX Delay -230 -> 252, step: 16
4050 13:31:47.032227 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4051 13:31:47.035954 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4052 13:31:47.038945 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4053 13:31:47.045834 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4054 13:31:47.049025 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4055 13:31:47.052204 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4056 13:31:47.055389 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4057 13:31:47.059269 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4058 13:31:47.065812 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4059 13:31:47.069013 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4060 13:31:47.072314 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4061 13:31:47.075538 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4062 13:31:47.082591 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4063 13:31:47.085711 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4064 13:31:47.088945 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4065 13:31:47.092177 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4066 13:31:47.092267 ==
4067 13:31:47.095256 Dram Type= 6, Freq= 0, CH_0, rank 0
4068 13:31:47.102113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4069 13:31:47.102234 ==
4070 13:31:47.102360 DQS Delay:
4071 13:31:47.105185 DQS0 = 0, DQS1 = 0
4072 13:31:47.105304 DQM Delay:
4073 13:31:47.108670 DQM0 = 38, DQM1 = 30
4074 13:31:47.108798 DQ Delay:
4075 13:31:47.112287 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4076 13:31:47.115289 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4077 13:31:47.118519 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4078 13:31:47.122209 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4079 13:31:47.122326
4080 13:31:47.122448
4081 13:31:47.122568 ==
4082 13:31:47.125229 Dram Type= 6, Freq= 0, CH_0, rank 0
4083 13:31:47.128822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4084 13:31:47.128936 ==
4085 13:31:47.129056
4086 13:31:47.129177
4087 13:31:47.131764 TX Vref Scan disable
4088 13:31:47.134873 == TX Byte 0 ==
4089 13:31:47.138188 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4090 13:31:47.141936 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4091 13:31:47.145044 == TX Byte 1 ==
4092 13:31:47.148137 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4093 13:31:47.151941 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4094 13:31:47.152031 ==
4095 13:31:47.155232 Dram Type= 6, Freq= 0, CH_0, rank 0
4096 13:31:47.158394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4097 13:31:47.161595 ==
4098 13:31:47.161706
4099 13:31:47.161803
4100 13:31:47.161894 TX Vref Scan disable
4101 13:31:47.166047 == TX Byte 0 ==
4102 13:31:47.169372 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4103 13:31:47.175867 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4104 13:31:47.175944 == TX Byte 1 ==
4105 13:31:47.179102 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4106 13:31:47.185515 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4107 13:31:47.185621
4108 13:31:47.185713 [DATLAT]
4109 13:31:47.185803 Freq=600, CH0 RK0
4110 13:31:47.185891
4111 13:31:47.188736 DATLAT Default: 0x9
4112 13:31:47.188834 0, 0xFFFF, sum = 0
4113 13:31:47.192506 1, 0xFFFF, sum = 0
4114 13:31:47.195430 2, 0xFFFF, sum = 0
4115 13:31:47.195504 3, 0xFFFF, sum = 0
4116 13:31:47.198603 4, 0xFFFF, sum = 0
4117 13:31:47.198678 5, 0xFFFF, sum = 0
4118 13:31:47.201791 6, 0xFFFF, sum = 0
4119 13:31:47.201893 7, 0xFFFF, sum = 0
4120 13:31:47.205225 8, 0x0, sum = 1
4121 13:31:47.205329 9, 0x0, sum = 2
4122 13:31:47.205420 10, 0x0, sum = 3
4123 13:31:47.208940 11, 0x0, sum = 4
4124 13:31:47.209041 best_step = 9
4125 13:31:47.209129
4126 13:31:47.212126 ==
4127 13:31:47.212227 Dram Type= 6, Freq= 0, CH_0, rank 0
4128 13:31:47.218786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4129 13:31:47.218887 ==
4130 13:31:47.218978 RX Vref Scan: 1
4131 13:31:47.219066
4132 13:31:47.221936 RX Vref 0 -> 0, step: 1
4133 13:31:47.222033
4134 13:31:47.225572 RX Delay -195 -> 252, step: 8
4135 13:31:47.225671
4136 13:31:47.228687 Set Vref, RX VrefLevel [Byte0]: 62
4137 13:31:47.231858 [Byte1]: 47
4138 13:31:47.231938
4139 13:31:47.235484 Final RX Vref Byte 0 = 62 to rank0
4140 13:31:47.238288 Final RX Vref Byte 1 = 47 to rank0
4141 13:31:47.241639 Final RX Vref Byte 0 = 62 to rank1
4142 13:31:47.245266 Final RX Vref Byte 1 = 47 to rank1==
4143 13:31:47.248526 Dram Type= 6, Freq= 0, CH_0, rank 0
4144 13:31:47.251765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4145 13:31:47.251870 ==
4146 13:31:47.254861 DQS Delay:
4147 13:31:47.254978 DQS0 = 0, DQS1 = 0
4148 13:31:47.258615 DQM Delay:
4149 13:31:47.258726 DQM0 = 35, DQM1 = 28
4150 13:31:47.261859 DQ Delay:
4151 13:31:47.261959 DQ0 =36, DQ1 =36, DQ2 =36, DQ3 =28
4152 13:31:47.264998 DQ4 =36, DQ5 =24, DQ6 =44, DQ7 =44
4153 13:31:47.268312 DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =20
4154 13:31:47.271625 DQ12 =32, DQ13 =32, DQ14 =40, DQ15 =36
4155 13:31:47.271724
4156 13:31:47.274781
4157 13:31:47.281238 [DQSOSCAuto] RK0, (LSB)MR18= 0x3a39, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
4158 13:31:47.284456 CH0 RK0: MR19=808, MR18=3A39
4159 13:31:47.291572 CH0_RK0: MR19=0x808, MR18=0x3A39, DQSOSC=398, MR23=63, INC=165, DEC=110
4160 13:31:47.291650
4161 13:31:47.294823 ----->DramcWriteLeveling(PI) begin...
4162 13:31:47.294896 ==
4163 13:31:47.298053 Dram Type= 6, Freq= 0, CH_0, rank 1
4164 13:31:47.301300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4165 13:31:47.301404 ==
4166 13:31:47.304418 Write leveling (Byte 0): 34 => 34
4167 13:31:47.308303 Write leveling (Byte 1): 31 => 31
4168 13:31:47.311483 DramcWriteLeveling(PI) end<-----
4169 13:31:47.311557
4170 13:31:47.311618 ==
4171 13:31:47.314534 Dram Type= 6, Freq= 0, CH_0, rank 1
4172 13:31:47.318192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4173 13:31:47.318294 ==
4174 13:31:47.321412 [Gating] SW mode calibration
4175 13:31:47.327683 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4176 13:31:47.334412 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4177 13:31:47.338050 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4178 13:31:47.341130 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4179 13:31:47.347946 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4180 13:31:47.351256 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
4181 13:31:47.354177 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4182 13:31:47.360955 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 13:31:47.364775 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 13:31:47.367853 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4185 13:31:47.374120 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4186 13:31:47.377346 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4187 13:31:47.381125 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 13:31:47.387517 0 10 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
4189 13:31:47.390794 0 10 16 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
4190 13:31:47.394019 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 13:31:47.400579 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 13:31:47.404417 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 13:31:47.407422 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 13:31:47.413927 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4195 13:31:47.417749 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 13:31:47.420920 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4197 13:31:47.427317 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 13:31:47.430527 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 13:31:47.433742 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 13:31:47.440871 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 13:31:47.443971 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 13:31:47.447069 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 13:31:47.454164 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 13:31:47.457250 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 13:31:47.460876 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 13:31:47.467336 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 13:31:47.470237 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 13:31:47.473701 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 13:31:47.480625 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 13:31:47.483751 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 13:31:47.487014 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4212 13:31:47.490267 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4213 13:31:47.496863 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4214 13:31:47.500009 Total UI for P1: 0, mck2ui 16
4215 13:31:47.503868 best dqsien dly found for B0: ( 0, 13, 10)
4216 13:31:47.507091 Total UI for P1: 0, mck2ui 16
4217 13:31:47.510260 best dqsien dly found for B1: ( 0, 13, 14)
4218 13:31:47.513549 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4219 13:31:47.516817 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4220 13:31:47.516900
4221 13:31:47.520083 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4222 13:31:47.523300 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4223 13:31:47.527092 [Gating] SW calibration Done
4224 13:31:47.527175 ==
4225 13:31:47.530125 Dram Type= 6, Freq= 0, CH_0, rank 1
4226 13:31:47.533328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4227 13:31:47.533411 ==
4228 13:31:47.536542 RX Vref Scan: 0
4229 13:31:47.536624
4230 13:31:47.539870 RX Vref 0 -> 0, step: 1
4231 13:31:47.539952
4232 13:31:47.540036 RX Delay -230 -> 252, step: 16
4233 13:31:47.546790 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4234 13:31:47.549970 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4235 13:31:47.553703 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4236 13:31:47.556827 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4237 13:31:47.563146 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4238 13:31:47.566391 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4239 13:31:47.570166 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4240 13:31:47.573306 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4241 13:31:47.576925 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4242 13:31:47.583550 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4243 13:31:47.586676 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4244 13:31:47.589705 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4245 13:31:47.593439 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4246 13:31:47.599886 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4247 13:31:47.603204 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4248 13:31:47.606402 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4249 13:31:47.606485 ==
4250 13:31:47.609677 Dram Type= 6, Freq= 0, CH_0, rank 1
4251 13:31:47.612847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4252 13:31:47.616581 ==
4253 13:31:47.616678 DQS Delay:
4254 13:31:47.616774 DQS0 = 0, DQS1 = 0
4255 13:31:47.619852 DQM Delay:
4256 13:31:47.619949 DQM0 = 36, DQM1 = 28
4257 13:31:47.623099 DQ Delay:
4258 13:31:47.626379 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4259 13:31:47.626477 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4260 13:31:47.629595 DQ8 =17, DQ9 =9, DQ10 =33, DQ11 =17
4261 13:31:47.632798 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =41
4262 13:31:47.636500
4263 13:31:47.636597
4264 13:31:47.636694 ==
4265 13:31:47.639767 Dram Type= 6, Freq= 0, CH_0, rank 1
4266 13:31:47.643057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4267 13:31:47.643155 ==
4268 13:31:47.643221
4269 13:31:47.643281
4270 13:31:47.646352 TX Vref Scan disable
4271 13:31:47.646449 == TX Byte 0 ==
4272 13:31:47.652480 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4273 13:31:47.656455 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4274 13:31:47.656552 == TX Byte 1 ==
4275 13:31:47.662462 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4276 13:31:47.666028 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4277 13:31:47.666126 ==
4278 13:31:47.669096 Dram Type= 6, Freq= 0, CH_0, rank 1
4279 13:31:47.672611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4280 13:31:47.672709 ==
4281 13:31:47.672806
4282 13:31:47.675871
4283 13:31:47.675968 TX Vref Scan disable
4284 13:31:47.679064 == TX Byte 0 ==
4285 13:31:47.682279 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4286 13:31:47.689277 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4287 13:31:47.689375 == TX Byte 1 ==
4288 13:31:47.692186 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4289 13:31:47.698935 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4290 13:31:47.699044
4291 13:31:47.699138 [DATLAT]
4292 13:31:47.699199 Freq=600, CH0 RK1
4293 13:31:47.699259
4294 13:31:47.702553 DATLAT Default: 0x9
4295 13:31:47.702635 0, 0xFFFF, sum = 0
4296 13:31:47.705790 1, 0xFFFF, sum = 0
4297 13:31:47.709171 2, 0xFFFF, sum = 0
4298 13:31:47.709254 3, 0xFFFF, sum = 0
4299 13:31:47.712476 4, 0xFFFF, sum = 0
4300 13:31:47.712558 5, 0xFFFF, sum = 0
4301 13:31:47.715664 6, 0xFFFF, sum = 0
4302 13:31:47.715746 7, 0xFFFF, sum = 0
4303 13:31:47.718899 8, 0x0, sum = 1
4304 13:31:47.719008 9, 0x0, sum = 2
4305 13:31:47.719101 10, 0x0, sum = 3
4306 13:31:47.722050 11, 0x0, sum = 4
4307 13:31:47.722132 best_step = 9
4308 13:31:47.722219
4309 13:31:47.722352 ==
4310 13:31:47.725327 Dram Type= 6, Freq= 0, CH_0, rank 1
4311 13:31:47.731953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4312 13:31:47.732034 ==
4313 13:31:47.732098 RX Vref Scan: 0
4314 13:31:47.732157
4315 13:31:47.735771 RX Vref 0 -> 0, step: 1
4316 13:31:47.735851
4317 13:31:47.739028 RX Delay -195 -> 252, step: 8
4318 13:31:47.742240 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4319 13:31:47.748650 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4320 13:31:47.751877 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4321 13:31:47.755636 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4322 13:31:47.758819 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4323 13:31:47.765386 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4324 13:31:47.768503 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4325 13:31:47.772269 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4326 13:31:47.775476 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4327 13:31:47.778484 iDelay=205, Bit 9, Center 12 (-139 ~ 164) 304
4328 13:31:47.785377 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4329 13:31:47.788631 iDelay=205, Bit 11, Center 16 (-139 ~ 172) 312
4330 13:31:47.791792 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4331 13:31:47.795425 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4332 13:31:47.801905 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4333 13:31:47.805045 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4334 13:31:47.805129 ==
4335 13:31:47.808099 Dram Type= 6, Freq= 0, CH_0, rank 1
4336 13:31:47.811773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4337 13:31:47.811855 ==
4338 13:31:47.814920 DQS Delay:
4339 13:31:47.815015 DQS0 = 0, DQS1 = 0
4340 13:31:47.818639 DQM Delay:
4341 13:31:47.818719 DQM0 = 33, DQM1 = 27
4342 13:31:47.818821 DQ Delay:
4343 13:31:47.821751 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4344 13:31:47.825115 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4345 13:31:47.828271 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =16
4346 13:31:47.831453 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4347 13:31:47.831548
4348 13:31:47.831626
4349 13:31:47.841521 [DQSOSCAuto] RK1, (LSB)MR18= 0x6634, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
4350 13:31:47.844721 CH0 RK1: MR19=808, MR18=6634
4351 13:31:47.851306 CH0_RK1: MR19=0x808, MR18=0x6634, DQSOSC=390, MR23=63, INC=172, DEC=114
4352 13:31:47.851419 [RxdqsGatingPostProcess] freq 600
4353 13:31:47.857799 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4354 13:31:47.861530 Pre-setting of DQS Precalculation
4355 13:31:47.864843 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4356 13:31:47.868025 ==
4357 13:31:47.868108 Dram Type= 6, Freq= 0, CH_1, rank 0
4358 13:31:47.874420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4359 13:31:47.874505 ==
4360 13:31:47.878167 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4361 13:31:47.884399 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4362 13:31:47.888076 [CA 0] Center 35 (5~66) winsize 62
4363 13:31:47.891801 [CA 1] Center 36 (6~66) winsize 61
4364 13:31:47.895023 [CA 2] Center 34 (4~65) winsize 62
4365 13:31:47.898290 [CA 3] Center 34 (3~65) winsize 63
4366 13:31:47.901368 [CA 4] Center 34 (4~65) winsize 62
4367 13:31:47.904977 [CA 5] Center 33 (3~64) winsize 62
4368 13:31:47.905059
4369 13:31:47.908458 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4370 13:31:47.908542
4371 13:31:47.911639 [CATrainingPosCal] consider 1 rank data
4372 13:31:47.914770 u2DelayCellTimex100 = 270/100 ps
4373 13:31:47.917871 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4374 13:31:47.924676 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4375 13:31:47.927743 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4376 13:31:47.930820 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4377 13:31:47.934089 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4378 13:31:47.937963 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4379 13:31:47.938045
4380 13:31:47.941073 CA PerBit enable=1, Macro0, CA PI delay=33
4381 13:31:47.941156
4382 13:31:47.944312 [CBTSetCACLKResult] CA Dly = 33
4383 13:31:47.947605 CS Dly: 4 (0~35)
4384 13:31:47.947688 ==
4385 13:31:47.950763 Dram Type= 6, Freq= 0, CH_1, rank 1
4386 13:31:47.953897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4387 13:31:47.953979 ==
4388 13:31:47.960726 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4389 13:31:47.964513 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4390 13:31:47.968318 [CA 0] Center 36 (6~66) winsize 61
4391 13:31:47.971648 [CA 1] Center 36 (6~66) winsize 61
4392 13:31:47.974814 [CA 2] Center 34 (4~65) winsize 62
4393 13:31:47.977968 [CA 3] Center 34 (3~65) winsize 63
4394 13:31:47.981802 [CA 4] Center 34 (4~65) winsize 62
4395 13:31:47.985160 [CA 5] Center 33 (3~64) winsize 62
4396 13:31:47.985242
4397 13:31:47.988393 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4398 13:31:47.988475
4399 13:31:47.991486 [CATrainingPosCal] consider 2 rank data
4400 13:31:47.994717 u2DelayCellTimex100 = 270/100 ps
4401 13:31:47.998395 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4402 13:31:48.004707 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4403 13:31:48.007982 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4404 13:31:48.011707 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4405 13:31:48.014609 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4406 13:31:48.018366 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4407 13:31:48.018449
4408 13:31:48.021585 CA PerBit enable=1, Macro0, CA PI delay=33
4409 13:31:48.021667
4410 13:31:48.024549 [CBTSetCACLKResult] CA Dly = 33
4411 13:31:48.024633 CS Dly: 5 (0~37)
4412 13:31:48.027747
4413 13:31:48.031559 ----->DramcWriteLeveling(PI) begin...
4414 13:31:48.031644 ==
4415 13:31:48.034607 Dram Type= 6, Freq= 0, CH_1, rank 0
4416 13:31:48.038205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4417 13:31:48.038330 ==
4418 13:31:48.041353 Write leveling (Byte 0): 27 => 27
4419 13:31:48.044729 Write leveling (Byte 1): 31 => 31
4420 13:31:48.048105 DramcWriteLeveling(PI) end<-----
4421 13:31:48.048220
4422 13:31:48.048316 ==
4423 13:31:48.050855 Dram Type= 6, Freq= 0, CH_1, rank 0
4424 13:31:48.054264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4425 13:31:48.054343 ==
4426 13:31:48.057613 [Gating] SW mode calibration
4427 13:31:48.064374 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4428 13:31:48.071292 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4429 13:31:48.074616 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4430 13:31:48.077831 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4431 13:31:48.084158 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4432 13:31:48.087499 0 9 12 | B1->B0 | 3030 3030 | 1 1 | (1 1) (1 1)
4433 13:31:48.091265 0 9 16 | B1->B0 | 2727 2929 | 1 0 | (1 1) (1 0)
4434 13:31:48.097654 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 13:31:48.100877 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4436 13:31:48.104012 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4437 13:31:48.110900 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4438 13:31:48.114103 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4439 13:31:48.117332 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4440 13:31:48.123848 0 10 12 | B1->B0 | 3030 3030 | 0 0 | (0 0) (0 0)
4441 13:31:48.127703 0 10 16 | B1->B0 | 4242 4646 | 0 0 | (1 1) (0 0)
4442 13:31:48.130960 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 13:31:48.137345 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 13:31:48.140567 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 13:31:48.143722 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 13:31:48.147393 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 13:31:48.153673 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 13:31:48.157023 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4449 13:31:48.160915 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4450 13:31:48.167263 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 13:31:48.170439 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 13:31:48.174035 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 13:31:48.180555 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 13:31:48.183829 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 13:31:48.187037 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 13:31:48.193489 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 13:31:48.197276 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 13:31:48.200420 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 13:31:48.206766 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 13:31:48.210025 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 13:31:48.213297 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 13:31:48.220128 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 13:31:48.223407 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 13:31:48.226554 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 13:31:48.233700 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4466 13:31:48.233786 Total UI for P1: 0, mck2ui 16
4467 13:31:48.240094 best dqsien dly found for B1: ( 0, 13, 14)
4468 13:31:48.242960 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 13:31:48.246629 Total UI for P1: 0, mck2ui 16
4470 13:31:48.249829 best dqsien dly found for B0: ( 0, 13, 16)
4471 13:31:48.253002 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4472 13:31:48.256743 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4473 13:31:48.256829
4474 13:31:48.259844 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4475 13:31:48.263114 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4476 13:31:48.266486 [Gating] SW calibration Done
4477 13:31:48.266571 ==
4478 13:31:48.269597 Dram Type= 6, Freq= 0, CH_1, rank 0
4479 13:31:48.276545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4480 13:31:48.276631 ==
4481 13:31:48.276717 RX Vref Scan: 0
4482 13:31:48.276799
4483 13:31:48.279537 RX Vref 0 -> 0, step: 1
4484 13:31:48.279621
4485 13:31:48.283117 RX Delay -230 -> 252, step: 16
4486 13:31:48.286298 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4487 13:31:48.289541 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4488 13:31:48.292661 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4489 13:31:48.299829 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4490 13:31:48.303068 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4491 13:31:48.306476 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4492 13:31:48.309628 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4493 13:31:48.316144 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4494 13:31:48.319476 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4495 13:31:48.322407 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4496 13:31:48.326371 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4497 13:31:48.329654 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4498 13:31:48.335946 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4499 13:31:48.339508 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4500 13:31:48.342633 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4501 13:31:48.345802 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4502 13:31:48.349064 ==
4503 13:31:48.349144 Dram Type= 6, Freq= 0, CH_1, rank 0
4504 13:31:48.355819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4505 13:31:48.355903 ==
4506 13:31:48.356003 DQS Delay:
4507 13:31:48.359261 DQS0 = 0, DQS1 = 0
4508 13:31:48.359362 DQM Delay:
4509 13:31:48.362522 DQM0 = 38, DQM1 = 28
4510 13:31:48.362607 DQ Delay:
4511 13:31:48.366183 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4512 13:31:48.369348 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4513 13:31:48.372626 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4514 13:31:48.375849 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4515 13:31:48.375933
4516 13:31:48.376019
4517 13:31:48.376099 ==
4518 13:31:48.379064 Dram Type= 6, Freq= 0, CH_1, rank 0
4519 13:31:48.382420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4520 13:31:48.382505 ==
4521 13:31:48.382591
4522 13:31:48.382671
4523 13:31:48.385586 TX Vref Scan disable
4524 13:31:48.389123 == TX Byte 0 ==
4525 13:31:48.392263 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4526 13:31:48.395366 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4527 13:31:48.399321 == TX Byte 1 ==
4528 13:31:48.402550 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4529 13:31:48.405721 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4530 13:31:48.405832 ==
4531 13:31:48.408976 Dram Type= 6, Freq= 0, CH_1, rank 0
4532 13:31:48.415340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4533 13:31:48.415450 ==
4534 13:31:48.415538
4535 13:31:48.415620
4536 13:31:48.415717 TX Vref Scan disable
4537 13:31:48.419768 == TX Byte 0 ==
4538 13:31:48.422902 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4539 13:31:48.429812 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4540 13:31:48.429969 == TX Byte 1 ==
4541 13:31:48.433023 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4542 13:31:48.439462 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4543 13:31:48.439605
4544 13:31:48.439676 [DATLAT]
4545 13:31:48.439747 Freq=600, CH1 RK0
4546 13:31:48.439809
4547 13:31:48.443123 DATLAT Default: 0x9
4548 13:31:48.443227 0, 0xFFFF, sum = 0
4549 13:31:48.446129 1, 0xFFFF, sum = 0
4550 13:31:48.449642 2, 0xFFFF, sum = 0
4551 13:31:48.449748 3, 0xFFFF, sum = 0
4552 13:31:48.452882 4, 0xFFFF, sum = 0
4553 13:31:48.452990 5, 0xFFFF, sum = 0
4554 13:31:48.456133 6, 0xFFFF, sum = 0
4555 13:31:48.456231 7, 0xFFFF, sum = 0
4556 13:31:48.459499 8, 0x0, sum = 1
4557 13:31:48.459599 9, 0x0, sum = 2
4558 13:31:48.459703 10, 0x0, sum = 3
4559 13:31:48.462537 11, 0x0, sum = 4
4560 13:31:48.462624 best_step = 9
4561 13:31:48.462711
4562 13:31:48.466199 ==
4563 13:31:48.466285 Dram Type= 6, Freq= 0, CH_1, rank 0
4564 13:31:48.472890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4565 13:31:48.472981 ==
4566 13:31:48.473069 RX Vref Scan: 1
4567 13:31:48.473152
4568 13:31:48.475868 RX Vref 0 -> 0, step: 1
4569 13:31:48.475956
4570 13:31:48.478904 RX Delay -195 -> 252, step: 8
4571 13:31:48.479014
4572 13:31:48.482256 Set Vref, RX VrefLevel [Byte0]: 59
4573 13:31:48.485555 [Byte1]: 49
4574 13:31:48.485640
4575 13:31:48.489410 Final RX Vref Byte 0 = 59 to rank0
4576 13:31:48.492503 Final RX Vref Byte 1 = 49 to rank0
4577 13:31:48.495485 Final RX Vref Byte 0 = 59 to rank1
4578 13:31:48.498914 Final RX Vref Byte 1 = 49 to rank1==
4579 13:31:48.502522 Dram Type= 6, Freq= 0, CH_1, rank 0
4580 13:31:48.505596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4581 13:31:48.505683 ==
4582 13:31:48.508860 DQS Delay:
4583 13:31:48.508945 DQS0 = 0, DQS1 = 0
4584 13:31:48.512645 DQM Delay:
4585 13:31:48.512732 DQM0 = 38, DQM1 = 28
4586 13:31:48.512819 DQ Delay:
4587 13:31:48.515770 DQ0 =44, DQ1 =36, DQ2 =24, DQ3 =36
4588 13:31:48.519100 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4589 13:31:48.522317 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4590 13:31:48.525572 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4591 13:31:48.525658
4592 13:31:48.528887
4593 13:31:48.535789 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f2d, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
4594 13:31:48.538997 CH1 RK0: MR19=808, MR18=1F2D
4595 13:31:48.545407 CH1_RK0: MR19=0x808, MR18=0x1F2D, DQSOSC=401, MR23=63, INC=163, DEC=108
4596 13:31:48.545502
4597 13:31:48.548720 ----->DramcWriteLeveling(PI) begin...
4598 13:31:48.548802 ==
4599 13:31:48.552473 Dram Type= 6, Freq= 0, CH_1, rank 1
4600 13:31:48.555332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4601 13:31:48.555436 ==
4602 13:31:48.558898 Write leveling (Byte 0): 30 => 30
4603 13:31:48.562073 Write leveling (Byte 1): 30 => 30
4604 13:31:48.565402 DramcWriteLeveling(PI) end<-----
4605 13:31:48.565486
4606 13:31:48.565577 ==
4607 13:31:48.568551 Dram Type= 6, Freq= 0, CH_1, rank 1
4608 13:31:48.571877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4609 13:31:48.571963 ==
4610 13:31:48.575593 [Gating] SW mode calibration
4611 13:31:48.582065 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4612 13:31:48.588857 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4613 13:31:48.592172 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4614 13:31:48.595569 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4615 13:31:48.602120 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4616 13:31:48.604901 0 9 12 | B1->B0 | 3131 2c2c | 1 0 | (1 0) (0 0)
4617 13:31:48.608662 0 9 16 | B1->B0 | 2626 2323 | 1 0 | (0 0) (0 0)
4618 13:31:48.614878 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4619 13:31:48.618650 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4620 13:31:48.621840 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4621 13:31:48.628247 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4622 13:31:48.631452 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4623 13:31:48.634709 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4624 13:31:48.641687 0 10 12 | B1->B0 | 3030 3d3c | 0 1 | (1 1) (0 0)
4625 13:31:48.644759 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4626 13:31:48.647929 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 13:31:48.654459 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 13:31:48.658307 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 13:31:48.661349 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 13:31:48.668033 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 13:31:48.671229 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 13:31:48.674515 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 13:31:48.680972 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4634 13:31:48.684557 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 13:31:48.687864 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 13:31:48.694520 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 13:31:48.697776 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 13:31:48.700992 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 13:31:48.707293 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 13:31:48.710684 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 13:31:48.714236 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 13:31:48.720850 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 13:31:48.724189 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 13:31:48.727051 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 13:31:48.733746 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 13:31:48.737630 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 13:31:48.740788 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 13:31:48.747065 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4649 13:31:48.750288 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4650 13:31:48.753538 Total UI for P1: 0, mck2ui 16
4651 13:31:48.757481 best dqsien dly found for B0: ( 0, 13, 12)
4652 13:31:48.760706 Total UI for P1: 0, mck2ui 16
4653 13:31:48.763928 best dqsien dly found for B1: ( 0, 13, 12)
4654 13:31:48.767243 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4655 13:31:48.770390 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4656 13:31:48.770496
4657 13:31:48.773805 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4658 13:31:48.776775 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4659 13:31:48.780043 [Gating] SW calibration Done
4660 13:31:48.780163 ==
4661 13:31:48.783286 Dram Type= 6, Freq= 0, CH_1, rank 1
4662 13:31:48.787022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4663 13:31:48.790108 ==
4664 13:31:48.790218 RX Vref Scan: 0
4665 13:31:48.790311
4666 13:31:48.793340 RX Vref 0 -> 0, step: 1
4667 13:31:48.793445
4668 13:31:48.796486 RX Delay -230 -> 252, step: 16
4669 13:31:48.800351 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4670 13:31:48.803574 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4671 13:31:48.806772 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4672 13:31:48.813335 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4673 13:31:48.816514 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4674 13:31:48.819848 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4675 13:31:48.823093 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4676 13:31:48.826230 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4677 13:31:48.832870 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4678 13:31:48.836386 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4679 13:31:48.839535 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4680 13:31:48.843107 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4681 13:31:48.849437 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4682 13:31:48.852616 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4683 13:31:48.856454 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4684 13:31:48.859718 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4685 13:31:48.863010 ==
4686 13:31:48.866319 Dram Type= 6, Freq= 0, CH_1, rank 1
4687 13:31:48.869613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4688 13:31:48.869695 ==
4689 13:31:48.869791 DQS Delay:
4690 13:31:48.872896 DQS0 = 0, DQS1 = 0
4691 13:31:48.872986 DQM Delay:
4692 13:31:48.876030 DQM0 = 42, DQM1 = 34
4693 13:31:48.876119 DQ Delay:
4694 13:31:48.879038 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4695 13:31:48.882572 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4696 13:31:48.886234 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =25
4697 13:31:48.889515 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4698 13:31:48.889666
4699 13:31:48.889767
4700 13:31:48.889869 ==
4701 13:31:48.892798 Dram Type= 6, Freq= 0, CH_1, rank 1
4702 13:31:48.895882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4703 13:31:48.895970 ==
4704 13:31:48.896044
4705 13:31:48.896134
4706 13:31:48.898912 TX Vref Scan disable
4707 13:31:48.902563 == TX Byte 0 ==
4708 13:31:48.905760 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4709 13:31:48.908812 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4710 13:31:48.912587 == TX Byte 1 ==
4711 13:31:48.915808 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4712 13:31:48.918983 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4713 13:31:48.919058 ==
4714 13:31:48.922419 Dram Type= 6, Freq= 0, CH_1, rank 1
4715 13:31:48.929034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4716 13:31:48.929117 ==
4717 13:31:48.929209
4718 13:31:48.929272
4719 13:31:48.929331 TX Vref Scan disable
4720 13:31:48.932886 == TX Byte 0 ==
4721 13:31:48.936312 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4722 13:31:48.942907 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4723 13:31:48.943068 == TX Byte 1 ==
4724 13:31:48.946202 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4725 13:31:48.953107 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4726 13:31:48.953221
4727 13:31:48.953333 [DATLAT]
4728 13:31:48.953426 Freq=600, CH1 RK1
4729 13:31:48.953534
4730 13:31:48.956738 DATLAT Default: 0x9
4731 13:31:48.956839 0, 0xFFFF, sum = 0
4732 13:31:48.959623 1, 0xFFFF, sum = 0
4733 13:31:48.963237 2, 0xFFFF, sum = 0
4734 13:31:48.963364 3, 0xFFFF, sum = 0
4735 13:31:48.966432 4, 0xFFFF, sum = 0
4736 13:31:48.966524 5, 0xFFFF, sum = 0
4737 13:31:48.969557 6, 0xFFFF, sum = 0
4738 13:31:48.969671 7, 0xFFFF, sum = 0
4739 13:31:48.972820 8, 0x0, sum = 1
4740 13:31:48.972935 9, 0x0, sum = 2
4741 13:31:48.973048 10, 0x0, sum = 3
4742 13:31:48.975988 11, 0x0, sum = 4
4743 13:31:48.976109 best_step = 9
4744 13:31:48.976227
4745 13:31:48.976344 ==
4746 13:31:48.979254 Dram Type= 6, Freq= 0, CH_1, rank 1
4747 13:31:48.986132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4748 13:31:48.986274 ==
4749 13:31:48.986390 RX Vref Scan: 0
4750 13:31:48.986486
4751 13:31:48.989810 RX Vref 0 -> 0, step: 1
4752 13:31:48.989927
4753 13:31:48.992768 RX Delay -195 -> 252, step: 8
4754 13:31:48.996076 iDelay=205, Bit 0, Center 40 (-123 ~ 204) 328
4755 13:31:49.003098 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4756 13:31:49.006189 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4757 13:31:49.009277 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4758 13:31:49.012957 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4759 13:31:49.019408 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4760 13:31:49.022639 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4761 13:31:49.025916 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4762 13:31:49.029067 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4763 13:31:49.032466 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4764 13:31:49.038837 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4765 13:31:49.042828 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4766 13:31:49.045920 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4767 13:31:49.048911 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4768 13:31:49.055842 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4769 13:31:49.059137 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4770 13:31:49.059246 ==
4771 13:31:49.062510 Dram Type= 6, Freq= 0, CH_1, rank 1
4772 13:31:49.065628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4773 13:31:49.065706 ==
4774 13:31:49.068993 DQS Delay:
4775 13:31:49.069065 DQS0 = 0, DQS1 = 0
4776 13:31:49.071909 DQM Delay:
4777 13:31:49.071979 DQM0 = 35, DQM1 = 29
4778 13:31:49.072046 DQ Delay:
4779 13:31:49.075338 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4780 13:31:49.078936 DQ4 =32, DQ5 =44, DQ6 =44, DQ7 =36
4781 13:31:49.082083 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4782 13:31:49.085502 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4783 13:31:49.085579
4784 13:31:49.085655
4785 13:31:49.095487 [DQSOSCAuto] RK1, (LSB)MR18= 0x3151, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
4786 13:31:49.098542 CH1 RK1: MR19=808, MR18=3151
4787 13:31:49.105109 CH1_RK1: MR19=0x808, MR18=0x3151, DQSOSC=394, MR23=63, INC=168, DEC=112
4788 13:31:49.108065 [RxdqsGatingPostProcess] freq 600
4789 13:31:49.111823 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4790 13:31:49.114918 Pre-setting of DQS Precalculation
4791 13:31:49.118511 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4792 13:31:49.128605 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4793 13:31:49.135191 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4794 13:31:49.135308
4795 13:31:49.135420
4796 13:31:49.138345 [Calibration Summary] 1200 Mbps
4797 13:31:49.138437 CH 0, Rank 0
4798 13:31:49.141513 SW Impedance : PASS
4799 13:31:49.141605 DUTY Scan : NO K
4800 13:31:49.144942 ZQ Calibration : PASS
4801 13:31:49.148096 Jitter Meter : NO K
4802 13:31:49.148179 CBT Training : PASS
4803 13:31:49.152004 Write leveling : PASS
4804 13:31:49.155073 RX DQS gating : PASS
4805 13:31:49.155187 RX DQ/DQS(RDDQC) : PASS
4806 13:31:49.157934 TX DQ/DQS : PASS
4807 13:31:49.161597 RX DATLAT : PASS
4808 13:31:49.161686 RX DQ/DQS(Engine): PASS
4809 13:31:49.164884 TX OE : NO K
4810 13:31:49.164962 All Pass.
4811 13:31:49.165036
4812 13:31:49.168108 CH 0, Rank 1
4813 13:31:49.168184 SW Impedance : PASS
4814 13:31:49.171309 DUTY Scan : NO K
4815 13:31:49.174498 ZQ Calibration : PASS
4816 13:31:49.174576 Jitter Meter : NO K
4817 13:31:49.177798 CBT Training : PASS
4818 13:31:49.181497 Write leveling : PASS
4819 13:31:49.181610 RX DQS gating : PASS
4820 13:31:49.184577 RX DQ/DQS(RDDQC) : PASS
4821 13:31:49.187700 TX DQ/DQS : PASS
4822 13:31:49.187812 RX DATLAT : PASS
4823 13:31:49.191247 RX DQ/DQS(Engine): PASS
4824 13:31:49.194338 TX OE : NO K
4825 13:31:49.194446 All Pass.
4826 13:31:49.194549
4827 13:31:49.194639 CH 1, Rank 0
4828 13:31:49.197688 SW Impedance : PASS
4829 13:31:49.201005 DUTY Scan : NO K
4830 13:31:49.201108 ZQ Calibration : PASS
4831 13:31:49.204321 Jitter Meter : NO K
4832 13:31:49.207974 CBT Training : PASS
4833 13:31:49.208050 Write leveling : PASS
4834 13:31:49.210975 RX DQS gating : PASS
4835 13:31:49.211089 RX DQ/DQS(RDDQC) : PASS
4836 13:31:49.214564 TX DQ/DQS : PASS
4837 13:31:49.217606 RX DATLAT : PASS
4838 13:31:49.217697 RX DQ/DQS(Engine): PASS
4839 13:31:49.221298 TX OE : NO K
4840 13:31:49.221396 All Pass.
4841 13:31:49.221463
4842 13:31:49.224446 CH 1, Rank 1
4843 13:31:49.224553 SW Impedance : PASS
4844 13:31:49.227399 DUTY Scan : NO K
4845 13:31:49.230942 ZQ Calibration : PASS
4846 13:31:49.231036 Jitter Meter : NO K
4847 13:31:49.234086 CBT Training : PASS
4848 13:31:49.237284 Write leveling : PASS
4849 13:31:49.237370 RX DQS gating : PASS
4850 13:31:49.241093 RX DQ/DQS(RDDQC) : PASS
4851 13:31:49.244353 TX DQ/DQS : PASS
4852 13:31:49.244437 RX DATLAT : PASS
4853 13:31:49.247591 RX DQ/DQS(Engine): PASS
4854 13:31:49.250782 TX OE : NO K
4855 13:31:49.250889 All Pass.
4856 13:31:49.250985
4857 13:31:49.251084 DramC Write-DBI off
4858 13:31:49.254095 PER_BANK_REFRESH: Hybrid Mode
4859 13:31:49.257468 TX_TRACKING: ON
4860 13:31:49.264291 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4861 13:31:49.267325 [FAST_K] Save calibration result to emmc
4862 13:31:49.273850 dramc_set_vcore_voltage set vcore to 662500
4863 13:31:49.273966 Read voltage for 933, 3
4864 13:31:49.277073 Vio18 = 0
4865 13:31:49.277185 Vcore = 662500
4866 13:31:49.277277 Vdram = 0
4867 13:31:49.277376 Vddq = 0
4868 13:31:49.280368 Vmddr = 0
4869 13:31:49.283643 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4870 13:31:49.290559 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4871 13:31:49.293655 MEM_TYPE=3, freq_sel=17
4872 13:31:49.293757 sv_algorithm_assistance_LP4_1600
4873 13:31:49.300334 ============ PULL DRAM RESETB DOWN ============
4874 13:31:49.304096 ========== PULL DRAM RESETB DOWN end =========
4875 13:31:49.307262 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4876 13:31:49.310509 ===================================
4877 13:31:49.313704 LPDDR4 DRAM CONFIGURATION
4878 13:31:49.316837 ===================================
4879 13:31:49.320664 EX_ROW_EN[0] = 0x0
4880 13:31:49.320774 EX_ROW_EN[1] = 0x0
4881 13:31:49.323784 LP4Y_EN = 0x0
4882 13:31:49.323866 WORK_FSP = 0x0
4883 13:31:49.326913 WL = 0x3
4884 13:31:49.326995 RL = 0x3
4885 13:31:49.330700 BL = 0x2
4886 13:31:49.330782 RPST = 0x0
4887 13:31:49.333746 RD_PRE = 0x0
4888 13:31:49.333828 WR_PRE = 0x1
4889 13:31:49.336845 WR_PST = 0x0
4890 13:31:49.336926 DBI_WR = 0x0
4891 13:31:49.340580 DBI_RD = 0x0
4892 13:31:49.340701 OTF = 0x1
4893 13:31:49.343700 ===================================
4894 13:31:49.346790 ===================================
4895 13:31:49.350463 ANA top config
4896 13:31:49.353692 ===================================
4897 13:31:49.356870 DLL_ASYNC_EN = 0
4898 13:31:49.356961 ALL_SLAVE_EN = 1
4899 13:31:49.360193 NEW_RANK_MODE = 1
4900 13:31:49.363548 DLL_IDLE_MODE = 1
4901 13:31:49.366873 LP45_APHY_COMB_EN = 1
4902 13:31:49.370002 TX_ODT_DIS = 1
4903 13:31:49.370080 NEW_8X_MODE = 1
4904 13:31:49.373773 ===================================
4905 13:31:49.376777 ===================================
4906 13:31:49.380029 data_rate = 1866
4907 13:31:49.383377 CKR = 1
4908 13:31:49.386609 DQ_P2S_RATIO = 8
4909 13:31:49.389858 ===================================
4910 13:31:49.393088 CA_P2S_RATIO = 8
4911 13:31:49.396441 DQ_CA_OPEN = 0
4912 13:31:49.396517 DQ_SEMI_OPEN = 0
4913 13:31:49.400278 CA_SEMI_OPEN = 0
4914 13:31:49.403528 CA_FULL_RATE = 0
4915 13:31:49.406541 DQ_CKDIV4_EN = 1
4916 13:31:49.410101 CA_CKDIV4_EN = 1
4917 13:31:49.413113 CA_PREDIV_EN = 0
4918 13:31:49.413203 PH8_DLY = 0
4919 13:31:49.416305 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4920 13:31:49.419939 DQ_AAMCK_DIV = 4
4921 13:31:49.423071 CA_AAMCK_DIV = 4
4922 13:31:49.426894 CA_ADMCK_DIV = 4
4923 13:31:49.429990 DQ_TRACK_CA_EN = 0
4924 13:31:49.430092 CA_PICK = 933
4925 13:31:49.433194 CA_MCKIO = 933
4926 13:31:49.436439 MCKIO_SEMI = 0
4927 13:31:49.439465 PLL_FREQ = 3732
4928 13:31:49.443141 DQ_UI_PI_RATIO = 32
4929 13:31:49.446317 CA_UI_PI_RATIO = 0
4930 13:31:49.449602 ===================================
4931 13:31:49.452609 ===================================
4932 13:31:49.452688 memory_type:LPDDR4
4933 13:31:49.456242 GP_NUM : 10
4934 13:31:49.459365 SRAM_EN : 1
4935 13:31:49.459466 MD32_EN : 0
4936 13:31:49.462543 ===================================
4937 13:31:49.465819 [ANA_INIT] >>>>>>>>>>>>>>
4938 13:31:49.469657 <<<<<< [CONFIGURE PHASE]: ANA_TX
4939 13:31:49.472900 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4940 13:31:49.476029 ===================================
4941 13:31:49.479181 data_rate = 1866,PCW = 0X8f00
4942 13:31:49.482667 ===================================
4943 13:31:49.485850 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4944 13:31:49.489065 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4945 13:31:49.495692 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4946 13:31:49.502821 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4947 13:31:49.506086 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4948 13:31:49.509192 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4949 13:31:49.509311 [ANA_INIT] flow start
4950 13:31:49.512530 [ANA_INIT] PLL >>>>>>>>
4951 13:31:49.515694 [ANA_INIT] PLL <<<<<<<<
4952 13:31:49.515784 [ANA_INIT] MIDPI >>>>>>>>
4953 13:31:49.519219 [ANA_INIT] MIDPI <<<<<<<<
4954 13:31:49.522139 [ANA_INIT] DLL >>>>>>>>
4955 13:31:49.522231 [ANA_INIT] flow end
4956 13:31:49.528734 ============ LP4 DIFF to SE enter ============
4957 13:31:49.532423 ============ LP4 DIFF to SE exit ============
4958 13:31:49.535742 [ANA_INIT] <<<<<<<<<<<<<
4959 13:31:49.538848 [Flow] Enable top DCM control >>>>>
4960 13:31:49.542025 [Flow] Enable top DCM control <<<<<
4961 13:31:49.542134 Enable DLL master slave shuffle
4962 13:31:49.549017 ==============================================================
4963 13:31:49.552170 Gating Mode config
4964 13:31:49.555379 ==============================================================
4965 13:31:49.558708 Config description:
4966 13:31:49.568452 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4967 13:31:49.574921 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4968 13:31:49.578288 SELPH_MODE 0: By rank 1: By Phase
4969 13:31:49.585289 ==============================================================
4970 13:31:49.588232 GAT_TRACK_EN = 1
4971 13:31:49.591861 RX_GATING_MODE = 2
4972 13:31:49.595094 RX_GATING_TRACK_MODE = 2
4973 13:31:49.598413 SELPH_MODE = 1
4974 13:31:49.598575 PICG_EARLY_EN = 1
4975 13:31:49.601643 VALID_LAT_VALUE = 1
4976 13:31:49.608147 ==============================================================
4977 13:31:49.611346 Enter into Gating configuration >>>>
4978 13:31:49.615202 Exit from Gating configuration <<<<
4979 13:31:49.618539 Enter into DVFS_PRE_config >>>>>
4980 13:31:49.627917 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4981 13:31:49.631432 Exit from DVFS_PRE_config <<<<<
4982 13:31:49.634441 Enter into PICG configuration >>>>
4983 13:31:49.637916 Exit from PICG configuration <<<<
4984 13:31:49.641465 [RX_INPUT] configuration >>>>>
4985 13:31:49.644364 [RX_INPUT] configuration <<<<<
4986 13:31:49.647944 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4987 13:31:49.654240 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4988 13:31:49.661452 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4989 13:31:49.667924 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4990 13:31:49.674325 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4991 13:31:49.678045 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4992 13:31:49.684334 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4993 13:31:49.687604 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4994 13:31:49.690884 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4995 13:31:49.694006 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4996 13:31:49.700844 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4997 13:31:49.704039 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4998 13:31:49.707884 ===================================
4999 13:31:49.710988 LPDDR4 DRAM CONFIGURATION
5000 13:31:49.714092 ===================================
5001 13:31:49.714212 EX_ROW_EN[0] = 0x0
5002 13:31:49.717364 EX_ROW_EN[1] = 0x0
5003 13:31:49.717474 LP4Y_EN = 0x0
5004 13:31:49.720534 WORK_FSP = 0x0
5005 13:31:49.720644 WL = 0x3
5006 13:31:49.724270 RL = 0x3
5007 13:31:49.727534 BL = 0x2
5008 13:31:49.727641 RPST = 0x0
5009 13:31:49.730638 RD_PRE = 0x0
5010 13:31:49.730742 WR_PRE = 0x1
5011 13:31:49.733859 WR_PST = 0x0
5012 13:31:49.733968 DBI_WR = 0x0
5013 13:31:49.737020 DBI_RD = 0x0
5014 13:31:49.737135 OTF = 0x1
5015 13:31:49.740369 ===================================
5016 13:31:49.743935 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5017 13:31:49.750266 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5018 13:31:49.753505 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5019 13:31:49.757243 ===================================
5020 13:31:49.760312 LPDDR4 DRAM CONFIGURATION
5021 13:31:49.763894 ===================================
5022 13:31:49.763998 EX_ROW_EN[0] = 0x10
5023 13:31:49.766712 EX_ROW_EN[1] = 0x0
5024 13:31:49.766819 LP4Y_EN = 0x0
5025 13:31:49.770157 WORK_FSP = 0x0
5026 13:31:49.770278 WL = 0x3
5027 13:31:49.773673 RL = 0x3
5028 13:31:49.773787 BL = 0x2
5029 13:31:49.777210 RPST = 0x0
5030 13:31:49.780315 RD_PRE = 0x0
5031 13:31:49.780391 WR_PRE = 0x1
5032 13:31:49.783823 WR_PST = 0x0
5033 13:31:49.783923 DBI_WR = 0x0
5034 13:31:49.787108 DBI_RD = 0x0
5035 13:31:49.787206 OTF = 0x1
5036 13:31:49.790404 ===================================
5037 13:31:49.796932 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5038 13:31:49.800773 nWR fixed to 30
5039 13:31:49.803862 [ModeRegInit_LP4] CH0 RK0
5040 13:31:49.803987 [ModeRegInit_LP4] CH0 RK1
5041 13:31:49.807466 [ModeRegInit_LP4] CH1 RK0
5042 13:31:49.810761 [ModeRegInit_LP4] CH1 RK1
5043 13:31:49.810843 match AC timing 9
5044 13:31:49.817085 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5045 13:31:49.820351 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5046 13:31:49.823735 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5047 13:31:49.830794 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5048 13:31:49.834016 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5049 13:31:49.834099 ==
5050 13:31:49.837126 Dram Type= 6, Freq= 0, CH_0, rank 0
5051 13:31:49.840278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5052 13:31:49.840388 ==
5053 13:31:49.847113 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5054 13:31:49.854029 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5055 13:31:49.857205 [CA 0] Center 38 (8~69) winsize 62
5056 13:31:49.860487 [CA 1] Center 38 (7~69) winsize 63
5057 13:31:49.863636 [CA 2] Center 36 (6~66) winsize 61
5058 13:31:49.866988 [CA 3] Center 35 (5~66) winsize 62
5059 13:31:49.870834 [CA 4] Center 34 (4~65) winsize 62
5060 13:31:49.873955 [CA 5] Center 33 (3~64) winsize 62
5061 13:31:49.874038
5062 13:31:49.877517 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5063 13:31:49.877606
5064 13:31:49.880495 [CATrainingPosCal] consider 1 rank data
5065 13:31:49.883858 u2DelayCellTimex100 = 270/100 ps
5066 13:31:49.887295 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5067 13:31:49.890574 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5068 13:31:49.893863 CA2 delay=36 (6~66),Diff = 3 PI (18 cell)
5069 13:31:49.896722 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5070 13:31:49.900115 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5071 13:31:49.907181 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5072 13:31:49.907288
5073 13:31:49.910354 CA PerBit enable=1, Macro0, CA PI delay=33
5074 13:31:49.910459
5075 13:31:49.913411 [CBTSetCACLKResult] CA Dly = 33
5076 13:31:49.913519 CS Dly: 7 (0~38)
5077 13:31:49.913613 ==
5078 13:31:49.916859 Dram Type= 6, Freq= 0, CH_0, rank 1
5079 13:31:49.919932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5080 13:31:49.923810 ==
5081 13:31:49.927123 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5082 13:31:49.933556 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5083 13:31:49.936802 [CA 0] Center 38 (8~69) winsize 62
5084 13:31:49.939899 [CA 1] Center 38 (8~69) winsize 62
5085 13:31:49.943032 [CA 2] Center 35 (5~66) winsize 62
5086 13:31:49.946278 [CA 3] Center 35 (4~66) winsize 63
5087 13:31:49.949981 [CA 4] Center 34 (4~65) winsize 62
5088 13:31:49.953260 [CA 5] Center 33 (3~64) winsize 62
5089 13:31:49.953365
5090 13:31:49.956473 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5091 13:31:49.956601
5092 13:31:49.960109 [CATrainingPosCal] consider 2 rank data
5093 13:31:49.963382 u2DelayCellTimex100 = 270/100 ps
5094 13:31:49.966569 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5095 13:31:49.969836 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5096 13:31:49.973168 CA2 delay=36 (6~66),Diff = 3 PI (18 cell)
5097 13:31:49.979735 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5098 13:31:49.982938 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5099 13:31:49.986249 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5100 13:31:49.986355
5101 13:31:49.989358 CA PerBit enable=1, Macro0, CA PI delay=33
5102 13:31:49.989466
5103 13:31:49.992953 [CBTSetCACLKResult] CA Dly = 33
5104 13:31:49.993058 CS Dly: 7 (0~39)
5105 13:31:49.993161
5106 13:31:49.996072 ----->DramcWriteLeveling(PI) begin...
5107 13:31:49.996181 ==
5108 13:31:49.999944 Dram Type= 6, Freq= 0, CH_0, rank 0
5109 13:31:50.006294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5110 13:31:50.006402 ==
5111 13:31:50.009515 Write leveling (Byte 0): 33 => 33
5112 13:31:50.012933 Write leveling (Byte 1): 31 => 31
5113 13:31:50.013041 DramcWriteLeveling(PI) end<-----
5114 13:31:50.013140
5115 13:31:50.016540 ==
5116 13:31:50.019757 Dram Type= 6, Freq= 0, CH_0, rank 0
5117 13:31:50.022815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5118 13:31:50.022926 ==
5119 13:31:50.026341 [Gating] SW mode calibration
5120 13:31:50.033082 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5121 13:31:50.036525 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5122 13:31:50.042994 0 14 0 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
5123 13:31:50.046290 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5124 13:31:50.049338 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5125 13:31:50.056186 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5126 13:31:50.059332 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5127 13:31:50.063114 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5128 13:31:50.069646 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5129 13:31:50.072832 0 14 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5130 13:31:50.076043 0 15 0 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
5131 13:31:50.082661 0 15 4 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)
5132 13:31:50.085826 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5133 13:31:50.089069 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5134 13:31:50.096194 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5135 13:31:50.099382 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5136 13:31:50.102512 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5137 13:31:50.108874 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5138 13:31:50.112298 1 0 0 | B1->B0 | 2424 3a3a | 0 0 | (0 0) (0 0)
5139 13:31:50.115961 1 0 4 | B1->B0 | 4040 4646 | 0 0 | (1 1) (0 0)
5140 13:31:50.122634 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 13:31:50.125412 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5142 13:31:50.129123 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 13:31:50.135551 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 13:31:50.138982 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 13:31:50.141890 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5146 13:31:50.148553 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5147 13:31:50.152148 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5148 13:31:50.155395 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 13:31:50.162310 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 13:31:50.165344 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 13:31:50.168487 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 13:31:50.174932 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 13:31:50.178912 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 13:31:50.182100 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 13:31:50.188648 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 13:31:50.191905 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 13:31:50.195147 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 13:31:50.201725 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 13:31:50.204880 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 13:31:50.208455 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 13:31:50.215133 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5162 13:31:50.218371 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5163 13:31:50.221620 Total UI for P1: 0, mck2ui 16
5164 13:31:50.224828 best dqsien dly found for B0: ( 1, 2, 28)
5165 13:31:50.227930 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5166 13:31:50.231753 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5167 13:31:50.234575 Total UI for P1: 0, mck2ui 16
5168 13:31:50.238305 best dqsien dly found for B1: ( 1, 3, 4)
5169 13:31:50.241402 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5170 13:31:50.247801 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5171 13:31:50.247884
5172 13:31:50.251748 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5173 13:31:50.254714 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5174 13:31:50.258172 [Gating] SW calibration Done
5175 13:31:50.258256 ==
5176 13:31:50.261419 Dram Type= 6, Freq= 0, CH_0, rank 0
5177 13:31:50.264676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5178 13:31:50.264762 ==
5179 13:31:50.264847 RX Vref Scan: 0
5180 13:31:50.267867
5181 13:31:50.267952 RX Vref 0 -> 0, step: 1
5182 13:31:50.268037
5183 13:31:50.270877 RX Delay -80 -> 252, step: 8
5184 13:31:50.274571 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5185 13:31:50.277689 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5186 13:31:50.284259 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5187 13:31:50.287481 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5188 13:31:50.290641 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5189 13:31:50.294618 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5190 13:31:50.297690 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5191 13:31:50.301093 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5192 13:31:50.307336 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5193 13:31:50.310557 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5194 13:31:50.314300 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5195 13:31:50.317660 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5196 13:31:50.324031 iDelay=208, Bit 12, Center 83 (-16 ~ 183) 200
5197 13:31:50.327246 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5198 13:31:50.330986 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5199 13:31:50.334332 iDelay=208, Bit 15, Center 87 (-16 ~ 191) 208
5200 13:31:50.334417 ==
5201 13:31:50.337456 Dram Type= 6, Freq= 0, CH_0, rank 0
5202 13:31:50.340473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5203 13:31:50.344142 ==
5204 13:31:50.344228 DQS Delay:
5205 13:31:50.344314 DQS0 = 0, DQS1 = 0
5206 13:31:50.347340 DQM Delay:
5207 13:31:50.347441 DQM0 = 94, DQM1 = 81
5208 13:31:50.350493 DQ Delay:
5209 13:31:50.353743 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5210 13:31:50.357021 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5211 13:31:50.357107 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5212 13:31:50.364069 DQ12 =83, DQ13 =87, DQ14 =91, DQ15 =87
5213 13:31:50.364162
5214 13:31:50.364248
5215 13:31:50.364329 ==
5216 13:31:50.367469 Dram Type= 6, Freq= 0, CH_0, rank 0
5217 13:31:50.370386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5218 13:31:50.370478 ==
5219 13:31:50.370564
5220 13:31:50.370645
5221 13:31:50.373631 TX Vref Scan disable
5222 13:31:50.373716 == TX Byte 0 ==
5223 13:31:50.380356 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5224 13:31:50.383568 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5225 13:31:50.383659 == TX Byte 1 ==
5226 13:31:50.390538 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5227 13:31:50.393865 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5228 13:31:50.393979 ==
5229 13:31:50.397285 Dram Type= 6, Freq= 0, CH_0, rank 0
5230 13:31:50.400529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5231 13:31:50.400641 ==
5232 13:31:50.400743
5233 13:31:50.400843
5234 13:31:50.403473 TX Vref Scan disable
5235 13:31:50.406748 == TX Byte 0 ==
5236 13:31:50.410610 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5237 13:31:50.413851 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5238 13:31:50.417063 == TX Byte 1 ==
5239 13:31:50.420335 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5240 13:31:50.423565 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5241 13:31:50.423682
5242 13:31:50.426795 [DATLAT]
5243 13:31:50.426915 Freq=933, CH0 RK0
5244 13:31:50.427018
5245 13:31:50.430063 DATLAT Default: 0xd
5246 13:31:50.430169 0, 0xFFFF, sum = 0
5247 13:31:50.433322 1, 0xFFFF, sum = 0
5248 13:31:50.433438 2, 0xFFFF, sum = 0
5249 13:31:50.436419 3, 0xFFFF, sum = 0
5250 13:31:50.436525 4, 0xFFFF, sum = 0
5251 13:31:50.440315 5, 0xFFFF, sum = 0
5252 13:31:50.440421 6, 0xFFFF, sum = 0
5253 13:31:50.443487 7, 0xFFFF, sum = 0
5254 13:31:50.446737 8, 0xFFFF, sum = 0
5255 13:31:50.446844 9, 0xFFFF, sum = 0
5256 13:31:50.446945 10, 0x0, sum = 1
5257 13:31:50.449669 11, 0x0, sum = 2
5258 13:31:50.449798 12, 0x0, sum = 3
5259 13:31:50.453371 13, 0x0, sum = 4
5260 13:31:50.453455 best_step = 11
5261 13:31:50.453520
5262 13:31:50.453580 ==
5263 13:31:50.456611 Dram Type= 6, Freq= 0, CH_0, rank 0
5264 13:31:50.463088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5265 13:31:50.463196 ==
5266 13:31:50.463293 RX Vref Scan: 1
5267 13:31:50.463390
5268 13:31:50.466341 RX Vref 0 -> 0, step: 1
5269 13:31:50.466450
5270 13:31:50.469752 RX Delay -69 -> 252, step: 4
5271 13:31:50.469837
5272 13:31:50.472947 Set Vref, RX VrefLevel [Byte0]: 62
5273 13:31:50.476719 [Byte1]: 47
5274 13:31:50.476804
5275 13:31:50.479914 Final RX Vref Byte 0 = 62 to rank0
5276 13:31:50.483100 Final RX Vref Byte 1 = 47 to rank0
5277 13:31:50.486436 Final RX Vref Byte 0 = 62 to rank1
5278 13:31:50.489488 Final RX Vref Byte 1 = 47 to rank1==
5279 13:31:50.493263 Dram Type= 6, Freq= 0, CH_0, rank 0
5280 13:31:50.496330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5281 13:31:50.496464 ==
5282 13:31:50.499563 DQS Delay:
5283 13:31:50.499671 DQS0 = 0, DQS1 = 0
5284 13:31:50.503136 DQM Delay:
5285 13:31:50.503242 DQM0 = 95, DQM1 = 82
5286 13:31:50.503335 DQ Delay:
5287 13:31:50.506213 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5288 13:31:50.509713 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =108
5289 13:31:50.513157 DQ8 =72, DQ9 =68, DQ10 =82, DQ11 =76
5290 13:31:50.516373 DQ12 =86, DQ13 =88, DQ14 =94, DQ15 =90
5291 13:31:50.516487
5292 13:31:50.519473
5293 13:31:50.526251 [DQSOSCAuto] RK0, (LSB)MR18= 0x1313, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 415 ps
5294 13:31:50.529309 CH0 RK0: MR19=505, MR18=1313
5295 13:31:50.535872 CH0_RK0: MR19=0x505, MR18=0x1313, DQSOSC=415, MR23=63, INC=62, DEC=41
5296 13:31:50.535982
5297 13:31:50.539192 ----->DramcWriteLeveling(PI) begin...
5298 13:31:50.539281 ==
5299 13:31:50.543105 Dram Type= 6, Freq= 0, CH_0, rank 1
5300 13:31:50.546285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5301 13:31:50.546360 ==
5302 13:31:50.549512 Write leveling (Byte 0): 32 => 32
5303 13:31:50.552692 Write leveling (Byte 1): 30 => 30
5304 13:31:50.556397 DramcWriteLeveling(PI) end<-----
5305 13:31:50.556513
5306 13:31:50.556607 ==
5307 13:31:50.559365 Dram Type= 6, Freq= 0, CH_0, rank 1
5308 13:31:50.562729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5309 13:31:50.562811 ==
5310 13:31:50.565944 [Gating] SW mode calibration
5311 13:31:50.572442 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5312 13:31:50.578788 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5313 13:31:50.582640 0 14 0 | B1->B0 | 2424 3434 | 1 1 | (1 1) (1 1)
5314 13:31:50.585921 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5315 13:31:50.592467 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5316 13:31:50.595700 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5317 13:31:50.598890 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5318 13:31:50.605307 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5319 13:31:50.608607 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5320 13:31:50.612355 0 14 28 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (1 1)
5321 13:31:50.618556 0 15 0 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
5322 13:31:50.622335 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5323 13:31:50.625216 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5324 13:31:50.632282 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5325 13:31:50.635297 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5326 13:31:50.638277 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5327 13:31:50.645312 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5328 13:31:50.648626 0 15 28 | B1->B0 | 2424 3333 | 0 0 | (0 0) (0 0)
5329 13:31:50.651752 1 0 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5330 13:31:50.658671 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 13:31:50.661588 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 13:31:50.665030 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5333 13:31:50.671561 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 13:31:50.674780 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 13:31:50.678046 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5336 13:31:50.685025 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5337 13:31:50.688312 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5338 13:31:50.691653 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 13:31:50.698037 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 13:31:50.701255 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 13:31:50.704484 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 13:31:50.711089 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 13:31:50.714557 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 13:31:50.717689 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 13:31:50.724031 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 13:31:50.727950 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 13:31:50.730984 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 13:31:50.737478 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 13:31:50.740765 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 13:31:50.744480 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 13:31:50.750609 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 13:31:50.754214 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5353 13:31:50.757569 Total UI for P1: 0, mck2ui 16
5354 13:31:50.760906 best dqsien dly found for B0: ( 1, 2, 26)
5355 13:31:50.764020 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5356 13:31:50.770805 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5357 13:31:50.770924 Total UI for P1: 0, mck2ui 16
5358 13:31:50.774016 best dqsien dly found for B1: ( 1, 2, 30)
5359 13:31:50.780506 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5360 13:31:50.783823 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5361 13:31:50.783937
5362 13:31:50.787490 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5363 13:31:50.790705 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5364 13:31:50.793918 [Gating] SW calibration Done
5365 13:31:50.794032 ==
5366 13:31:50.797123 Dram Type= 6, Freq= 0, CH_0, rank 1
5367 13:31:50.800464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5368 13:31:50.800587 ==
5369 13:31:50.804149 RX Vref Scan: 0
5370 13:31:50.804268
5371 13:31:50.804378 RX Vref 0 -> 0, step: 1
5372 13:31:50.804473
5373 13:31:50.807313 RX Delay -80 -> 252, step: 8
5374 13:31:50.810540 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5375 13:31:50.817061 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5376 13:31:50.820189 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5377 13:31:50.824024 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5378 13:31:50.827075 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5379 13:31:50.830440 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5380 13:31:50.836917 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5381 13:31:50.840598 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5382 13:31:50.843688 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5383 13:31:50.846969 iDelay=208, Bit 9, Center 63 (-32 ~ 159) 192
5384 13:31:50.850057 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5385 13:31:50.856612 iDelay=208, Bit 11, Center 71 (-24 ~ 167) 192
5386 13:31:50.859897 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5387 13:31:50.863170 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5388 13:31:50.866781 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5389 13:31:50.869915 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5390 13:31:50.870057 ==
5391 13:31:50.873361 Dram Type= 6, Freq= 0, CH_0, rank 1
5392 13:31:50.879644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5393 13:31:50.879837 ==
5394 13:31:50.879958 DQS Delay:
5395 13:31:50.882978 DQS0 = 0, DQS1 = 0
5396 13:31:50.883070 DQM Delay:
5397 13:31:50.886316 DQM0 = 92, DQM1 = 81
5398 13:31:50.886428 DQ Delay:
5399 13:31:50.889580 DQ0 =91, DQ1 =95, DQ2 =87, DQ3 =87
5400 13:31:50.893285 DQ4 =91, DQ5 =79, DQ6 =103, DQ7 =107
5401 13:31:50.896391 DQ8 =75, DQ9 =63, DQ10 =83, DQ11 =71
5402 13:31:50.899618 DQ12 =87, DQ13 =87, DQ14 =95, DQ15 =87
5403 13:31:50.899703
5404 13:31:50.899769
5405 13:31:50.899838 ==
5406 13:31:50.902921 Dram Type= 6, Freq= 0, CH_0, rank 1
5407 13:31:50.906140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5408 13:31:50.906251 ==
5409 13:31:50.906348
5410 13:31:50.906439
5411 13:31:50.909849 TX Vref Scan disable
5412 13:31:50.913003 == TX Byte 0 ==
5413 13:31:50.916223 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5414 13:31:50.919362 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5415 13:31:50.922559 == TX Byte 1 ==
5416 13:31:50.926364 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5417 13:31:50.929590 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5418 13:31:50.929694 ==
5419 13:31:50.932930 Dram Type= 6, Freq= 0, CH_0, rank 1
5420 13:31:50.936084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5421 13:31:50.939283 ==
5422 13:31:50.939406
5423 13:31:50.939504
5424 13:31:50.939602 TX Vref Scan disable
5425 13:31:50.943093 == TX Byte 0 ==
5426 13:31:50.946087 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5427 13:31:50.953024 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5428 13:31:50.953153 == TX Byte 1 ==
5429 13:31:50.956213 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5430 13:31:50.962772 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5431 13:31:50.962886
5432 13:31:50.962980 [DATLAT]
5433 13:31:50.963072 Freq=933, CH0 RK1
5434 13:31:50.963167
5435 13:31:50.966059 DATLAT Default: 0xb
5436 13:31:50.966160 0, 0xFFFF, sum = 0
5437 13:31:50.969404 1, 0xFFFF, sum = 0
5438 13:31:50.969517 2, 0xFFFF, sum = 0
5439 13:31:50.972553 3, 0xFFFF, sum = 0
5440 13:31:50.976519 4, 0xFFFF, sum = 0
5441 13:31:50.976629 5, 0xFFFF, sum = 0
5442 13:31:50.979644 6, 0xFFFF, sum = 0
5443 13:31:50.979751 7, 0xFFFF, sum = 0
5444 13:31:50.982881 8, 0xFFFF, sum = 0
5445 13:31:50.982979 9, 0xFFFF, sum = 0
5446 13:31:50.986037 10, 0x0, sum = 1
5447 13:31:50.986156 11, 0x0, sum = 2
5448 13:31:50.989264 12, 0x0, sum = 3
5449 13:31:50.989382 13, 0x0, sum = 4
5450 13:31:50.989492 best_step = 11
5451 13:31:50.989598
5452 13:31:50.993001 ==
5453 13:31:50.996259 Dram Type= 6, Freq= 0, CH_0, rank 1
5454 13:31:50.999057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5455 13:31:50.999170 ==
5456 13:31:50.999264 RX Vref Scan: 0
5457 13:31:50.999384
5458 13:31:51.002644 RX Vref 0 -> 0, step: 1
5459 13:31:51.002747
5460 13:31:51.005986 RX Delay -77 -> 252, step: 4
5461 13:31:51.012789 iDelay=199, Bit 0, Center 90 (-1 ~ 182) 184
5462 13:31:51.015819 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5463 13:31:51.019433 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5464 13:31:51.022339 iDelay=199, Bit 3, Center 90 (-5 ~ 186) 192
5465 13:31:51.025824 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5466 13:31:51.028837 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5467 13:31:51.035863 iDelay=199, Bit 6, Center 108 (19 ~ 198) 180
5468 13:31:51.039096 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5469 13:31:51.042358 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5470 13:31:51.045713 iDelay=199, Bit 9, Center 68 (-17 ~ 154) 172
5471 13:31:51.048961 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5472 13:31:51.055618 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5473 13:31:51.058983 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5474 13:31:51.062104 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5475 13:31:51.065321 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5476 13:31:51.069190 iDelay=199, Bit 15, Center 92 (3 ~ 182) 180
5477 13:31:51.069302 ==
5478 13:31:51.072544 Dram Type= 6, Freq= 0, CH_0, rank 1
5479 13:31:51.079033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5480 13:31:51.079144 ==
5481 13:31:51.079238 DQS Delay:
5482 13:31:51.082325 DQS0 = 0, DQS1 = 0
5483 13:31:51.082425 DQM Delay:
5484 13:31:51.082517 DQM0 = 93, DQM1 = 84
5485 13:31:51.085589 DQ Delay:
5486 13:31:51.088840 DQ0 =90, DQ1 =94, DQ2 =88, DQ3 =90
5487 13:31:51.091994 DQ4 =90, DQ5 =80, DQ6 =108, DQ7 =104
5488 13:31:51.095872 DQ8 =76, DQ9 =68, DQ10 =88, DQ11 =76
5489 13:31:51.098994 DQ12 =90, DQ13 =90, DQ14 =96, DQ15 =92
5490 13:31:51.099087
5491 13:31:51.099169
5492 13:31:51.105552 [DQSOSCAuto] RK1, (LSB)MR18= 0x3112, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 406 ps
5493 13:31:51.108793 CH0 RK1: MR19=505, MR18=3112
5494 13:31:51.115203 CH0_RK1: MR19=0x505, MR18=0x3112, DQSOSC=406, MR23=63, INC=65, DEC=43
5495 13:31:51.118872 [RxdqsGatingPostProcess] freq 933
5496 13:31:51.121961 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5497 13:31:51.125601 best DQS0 dly(2T, 0.5T) = (0, 10)
5498 13:31:51.128704 best DQS1 dly(2T, 0.5T) = (0, 11)
5499 13:31:51.131704 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5500 13:31:51.135273 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5501 13:31:51.138615 best DQS0 dly(2T, 0.5T) = (0, 10)
5502 13:31:51.141762 best DQS1 dly(2T, 0.5T) = (0, 10)
5503 13:31:51.145353 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5504 13:31:51.148475 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5505 13:31:51.151758 Pre-setting of DQS Precalculation
5506 13:31:51.155080 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5507 13:31:51.158411 ==
5508 13:31:51.158502 Dram Type= 6, Freq= 0, CH_1, rank 0
5509 13:31:51.165139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5510 13:31:51.165224 ==
5511 13:31:51.168067 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5512 13:31:51.174759 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5513 13:31:51.178701 [CA 0] Center 37 (7~68) winsize 62
5514 13:31:51.182036 [CA 1] Center 37 (7~68) winsize 62
5515 13:31:51.185283 [CA 2] Center 34 (5~64) winsize 60
5516 13:31:51.188485 [CA 3] Center 34 (5~64) winsize 60
5517 13:31:51.191710 [CA 4] Center 34 (5~64) winsize 60
5518 13:31:51.194839 [CA 5] Center 34 (4~64) winsize 61
5519 13:31:51.194948
5520 13:31:51.198070 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5521 13:31:51.198179
5522 13:31:51.201352 [CATrainingPosCal] consider 1 rank data
5523 13:31:51.205130 u2DelayCellTimex100 = 270/100 ps
5524 13:31:51.208437 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5525 13:31:51.214977 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5526 13:31:51.218126 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5527 13:31:51.221431 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5528 13:31:51.225056 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5529 13:31:51.228114 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5530 13:31:51.228236
5531 13:31:51.231304 CA PerBit enable=1, Macro0, CA PI delay=34
5532 13:31:51.231415
5533 13:31:51.234530 [CBTSetCACLKResult] CA Dly = 34
5534 13:31:51.237829 CS Dly: 6 (0~37)
5535 13:31:51.237933 ==
5536 13:31:51.241232 Dram Type= 6, Freq= 0, CH_1, rank 1
5537 13:31:51.244424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5538 13:31:51.244529 ==
5539 13:31:51.251506 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5540 13:31:51.254497 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5541 13:31:51.258389 [CA 0] Center 37 (8~67) winsize 60
5542 13:31:51.261826 [CA 1] Center 37 (7~68) winsize 62
5543 13:31:51.265193 [CA 2] Center 35 (5~65) winsize 61
5544 13:31:51.268055 [CA 3] Center 34 (4~64) winsize 61
5545 13:31:51.271922 [CA 4] Center 35 (5~65) winsize 61
5546 13:31:51.274923 [CA 5] Center 34 (4~64) winsize 61
5547 13:31:51.275005
5548 13:31:51.278391 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5549 13:31:51.278508
5550 13:31:51.281704 [CATrainingPosCal] consider 2 rank data
5551 13:31:51.284909 u2DelayCellTimex100 = 270/100 ps
5552 13:31:51.288069 CA0 delay=37 (8~67),Diff = 3 PI (18 cell)
5553 13:31:51.294933 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5554 13:31:51.298086 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5555 13:31:51.301417 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5556 13:31:51.304568 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5557 13:31:51.308361 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5558 13:31:51.308443
5559 13:31:51.311705 CA PerBit enable=1, Macro0, CA PI delay=34
5560 13:31:51.311786
5561 13:31:51.314931 [CBTSetCACLKResult] CA Dly = 34
5562 13:31:51.315045 CS Dly: 7 (0~39)
5563 13:31:51.318034
5564 13:31:51.321327 ----->DramcWriteLeveling(PI) begin...
5565 13:31:51.321441 ==
5566 13:31:51.324594 Dram Type= 6, Freq= 0, CH_1, rank 0
5567 13:31:51.328365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5568 13:31:51.328446 ==
5569 13:31:51.331463 Write leveling (Byte 0): 23 => 23
5570 13:31:51.334591 Write leveling (Byte 1): 29 => 29
5571 13:31:51.337803 DramcWriteLeveling(PI) end<-----
5572 13:31:51.337887
5573 13:31:51.337973 ==
5574 13:31:51.341135 Dram Type= 6, Freq= 0, CH_1, rank 0
5575 13:31:51.344469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5576 13:31:51.344556 ==
5577 13:31:51.348287 [Gating] SW mode calibration
5578 13:31:51.354667 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5579 13:31:51.361586 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5580 13:31:51.364739 0 14 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (1 1)
5581 13:31:51.368033 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5582 13:31:51.374436 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5583 13:31:51.378033 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5584 13:31:51.380985 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5585 13:31:51.387482 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5586 13:31:51.391235 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5587 13:31:51.394292 0 14 28 | B1->B0 | 3131 3131 | 0 0 | (1 0) (1 0)
5588 13:31:51.401097 0 15 0 | B1->B0 | 2424 2828 | 0 0 | (0 0) (0 0)
5589 13:31:51.404421 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5590 13:31:51.407655 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5591 13:31:51.413974 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5592 13:31:51.417647 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5593 13:31:51.421037 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5594 13:31:51.428017 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5595 13:31:51.430532 0 15 28 | B1->B0 | 3131 3030 | 0 1 | (0 0) (0 0)
5596 13:31:51.434257 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5597 13:31:51.437369 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5598 13:31:51.443873 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5599 13:31:51.447039 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5600 13:31:51.451013 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 13:31:51.457509 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 13:31:51.460620 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 13:31:51.463712 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5604 13:31:51.470693 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 13:31:51.473868 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 13:31:51.477079 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 13:31:51.483506 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 13:31:51.487192 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 13:31:51.490198 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 13:31:51.497322 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 13:31:51.500533 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 13:31:51.503588 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 13:31:51.509967 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 13:31:51.513702 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 13:31:51.516627 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 13:31:51.523709 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 13:31:51.526995 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 13:31:51.529916 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5619 13:31:51.536448 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5620 13:31:51.540086 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 13:31:51.543101 Total UI for P1: 0, mck2ui 16
5622 13:31:51.546385 best dqsien dly found for B0: ( 1, 2, 26)
5623 13:31:51.549654 Total UI for P1: 0, mck2ui 16
5624 13:31:51.553508 best dqsien dly found for B1: ( 1, 2, 28)
5625 13:31:51.556746 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5626 13:31:51.560025 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5627 13:31:51.560113
5628 13:31:51.563248 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5629 13:31:51.566438 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5630 13:31:51.569537 [Gating] SW calibration Done
5631 13:31:51.569622 ==
5632 13:31:51.573341 Dram Type= 6, Freq= 0, CH_1, rank 0
5633 13:31:51.579745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5634 13:31:51.579832 ==
5635 13:31:51.579919 RX Vref Scan: 0
5636 13:31:51.580002
5637 13:31:51.582981 RX Vref 0 -> 0, step: 1
5638 13:31:51.583065
5639 13:31:51.586260 RX Delay -80 -> 252, step: 8
5640 13:31:51.589362 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5641 13:31:51.592415 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5642 13:31:51.595788 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5643 13:31:51.598973 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5644 13:31:51.606139 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5645 13:31:51.609269 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5646 13:31:51.612439 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5647 13:31:51.615641 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5648 13:31:51.618994 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5649 13:31:51.622129 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5650 13:31:51.629107 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5651 13:31:51.632762 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5652 13:31:51.635661 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5653 13:31:51.639366 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5654 13:31:51.642577 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5655 13:31:51.648947 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5656 13:31:51.649051 ==
5657 13:31:51.652159 Dram Type= 6, Freq= 0, CH_1, rank 0
5658 13:31:51.655530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5659 13:31:51.655633 ==
5660 13:31:51.655722 DQS Delay:
5661 13:31:51.659123 DQS0 = 0, DQS1 = 0
5662 13:31:51.659238 DQM Delay:
5663 13:31:51.662558 DQM0 = 96, DQM1 = 88
5664 13:31:51.662646 DQ Delay:
5665 13:31:51.665714 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95
5666 13:31:51.669010 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =95
5667 13:31:51.672340 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5668 13:31:51.675601 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =91
5669 13:31:51.675705
5670 13:31:51.675807
5671 13:31:51.675905 ==
5672 13:31:51.678600 Dram Type= 6, Freq= 0, CH_1, rank 0
5673 13:31:51.681801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5674 13:31:51.681881 ==
5675 13:31:51.685734
5676 13:31:51.685818
5677 13:31:51.685880 TX Vref Scan disable
5678 13:31:51.688923 == TX Byte 0 ==
5679 13:31:51.692131 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5680 13:31:51.695344 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5681 13:31:51.698542 == TX Byte 1 ==
5682 13:31:51.701718 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5683 13:31:51.705194 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5684 13:31:51.708372 ==
5685 13:31:51.711583 Dram Type= 6, Freq= 0, CH_1, rank 0
5686 13:31:51.715326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5687 13:31:51.715447 ==
5688 13:31:51.715516
5689 13:31:51.715576
5690 13:31:51.718531 TX Vref Scan disable
5691 13:31:51.718614 == TX Byte 0 ==
5692 13:31:51.725195 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5693 13:31:51.728180 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5694 13:31:51.728264 == TX Byte 1 ==
5695 13:31:51.735256 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5696 13:31:51.738352 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5697 13:31:51.738437
5698 13:31:51.738503 [DATLAT]
5699 13:31:51.741543 Freq=933, CH1 RK0
5700 13:31:51.741625
5701 13:31:51.741689 DATLAT Default: 0xd
5702 13:31:51.744841 0, 0xFFFF, sum = 0
5703 13:31:51.744952 1, 0xFFFF, sum = 0
5704 13:31:51.748644 2, 0xFFFF, sum = 0
5705 13:31:51.748727 3, 0xFFFF, sum = 0
5706 13:31:51.751862 4, 0xFFFF, sum = 0
5707 13:31:51.751946 5, 0xFFFF, sum = 0
5708 13:31:51.755027 6, 0xFFFF, sum = 0
5709 13:31:51.755143 7, 0xFFFF, sum = 0
5710 13:31:51.758013 8, 0xFFFF, sum = 0
5711 13:31:51.761630 9, 0xFFFF, sum = 0
5712 13:31:51.761743 10, 0x0, sum = 1
5713 13:31:51.761838 11, 0x0, sum = 2
5714 13:31:51.764570 12, 0x0, sum = 3
5715 13:31:51.764643 13, 0x0, sum = 4
5716 13:31:51.768001 best_step = 11
5717 13:31:51.768074
5718 13:31:51.768147 ==
5719 13:31:51.771553 Dram Type= 6, Freq= 0, CH_1, rank 0
5720 13:31:51.774916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5721 13:31:51.775018 ==
5722 13:31:51.778110 RX Vref Scan: 1
5723 13:31:51.778212
5724 13:31:51.778306 RX Vref 0 -> 0, step: 1
5725 13:31:51.778393
5726 13:31:51.781280 RX Delay -61 -> 252, step: 4
5727 13:31:51.781378
5728 13:31:51.784788 Set Vref, RX VrefLevel [Byte0]: 59
5729 13:31:51.787951 [Byte1]: 49
5730 13:31:51.792388
5731 13:31:51.792470 Final RX Vref Byte 0 = 59 to rank0
5732 13:31:51.795530 Final RX Vref Byte 1 = 49 to rank0
5733 13:31:51.798842 Final RX Vref Byte 0 = 59 to rank1
5734 13:31:51.802113 Final RX Vref Byte 1 = 49 to rank1==
5735 13:31:51.805537 Dram Type= 6, Freq= 0, CH_1, rank 0
5736 13:31:51.812516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5737 13:31:51.812595 ==
5738 13:31:51.812677 DQS Delay:
5739 13:31:51.812738 DQS0 = 0, DQS1 = 0
5740 13:31:51.815542 DQM Delay:
5741 13:31:51.815637 DQM0 = 96, DQM1 = 88
5742 13:31:51.818775 DQ Delay:
5743 13:31:51.821880 DQ0 =102, DQ1 =92, DQ2 =84, DQ3 =90
5744 13:31:51.825146 DQ4 =94, DQ5 =108, DQ6 =106, DQ7 =94
5745 13:31:51.829011 DQ8 =76, DQ9 =80, DQ10 =86, DQ11 =80
5746 13:31:51.831963 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
5747 13:31:51.832036
5748 13:31:51.832097
5749 13:31:51.838308 [DQSOSCAuto] RK0, (LSB)MR18= 0xfe07, (MSB)MR19= 0x405, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5750 13:31:51.842062 CH1 RK0: MR19=405, MR18=FE07
5751 13:31:51.848537 CH1_RK0: MR19=0x405, MR18=0xFE07, DQSOSC=419, MR23=63, INC=61, DEC=41
5752 13:31:51.848616
5753 13:31:51.851827 ----->DramcWriteLeveling(PI) begin...
5754 13:31:51.851903 ==
5755 13:31:51.855109 Dram Type= 6, Freq= 0, CH_1, rank 1
5756 13:31:51.858396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5757 13:31:51.858472 ==
5758 13:31:51.861541 Write leveling (Byte 0): 27 => 27
5759 13:31:51.865131 Write leveling (Byte 1): 29 => 29
5760 13:31:51.868226 DramcWriteLeveling(PI) end<-----
5761 13:31:51.868301
5762 13:31:51.868364 ==
5763 13:31:51.871495 Dram Type= 6, Freq= 0, CH_1, rank 1
5764 13:31:51.874957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5765 13:31:51.878405 ==
5766 13:31:51.878479 [Gating] SW mode calibration
5767 13:31:51.885050 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5768 13:31:51.891329 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5769 13:31:51.894646 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5770 13:31:51.901694 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5771 13:31:51.904930 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5772 13:31:51.908356 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5773 13:31:51.914664 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5774 13:31:51.918375 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5775 13:31:51.921259 0 14 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
5776 13:31:51.928124 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
5777 13:31:51.931255 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5778 13:31:51.934493 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5779 13:31:51.941029 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5780 13:31:51.944290 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5781 13:31:51.947953 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5782 13:31:51.954471 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5783 13:31:51.957755 0 15 24 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
5784 13:31:51.961091 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)
5785 13:31:51.967584 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5786 13:31:51.971220 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5787 13:31:51.974350 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5788 13:31:51.981397 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5789 13:31:51.984392 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 13:31:51.987320 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 13:31:51.994001 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5792 13:31:51.997552 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5793 13:31:52.000561 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 13:31:52.004095 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 13:31:52.011199 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 13:31:52.014579 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 13:31:52.017856 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 13:31:52.024233 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 13:31:52.027776 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 13:31:52.030764 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 13:31:52.037302 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 13:31:52.041131 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 13:31:52.044277 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 13:31:52.050648 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 13:31:52.054291 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 13:31:52.057349 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 13:31:52.063860 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5808 13:31:52.067050 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5809 13:31:52.070266 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5810 13:31:52.074121 Total UI for P1: 0, mck2ui 16
5811 13:31:52.077302 best dqsien dly found for B0: ( 1, 2, 26)
5812 13:31:52.080325 Total UI for P1: 0, mck2ui 16
5813 13:31:52.083526 best dqsien dly found for B1: ( 1, 2, 28)
5814 13:31:52.087440 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5815 13:31:52.090091 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5816 13:31:52.090166
5817 13:31:52.096898 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5818 13:31:52.100638 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5819 13:31:52.103784 [Gating] SW calibration Done
5820 13:31:52.103872 ==
5821 13:31:52.106855 Dram Type= 6, Freq= 0, CH_1, rank 1
5822 13:31:52.110449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5823 13:31:52.110533 ==
5824 13:31:52.110599 RX Vref Scan: 0
5825 13:31:52.113775
5826 13:31:52.113857 RX Vref 0 -> 0, step: 1
5827 13:31:52.113924
5828 13:31:52.116752 RX Delay -80 -> 252, step: 8
5829 13:31:52.120001 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5830 13:31:52.123125 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5831 13:31:52.130112 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5832 13:31:52.133250 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5833 13:31:52.136370 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5834 13:31:52.139964 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5835 13:31:52.143102 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5836 13:31:52.149400 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5837 13:31:52.153261 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5838 13:31:52.156453 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5839 13:31:52.159499 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5840 13:31:52.162528 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5841 13:31:52.169732 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5842 13:31:52.172982 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5843 13:31:52.176101 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5844 13:31:52.179276 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5845 13:31:52.179394 ==
5846 13:31:52.182558 Dram Type= 6, Freq= 0, CH_1, rank 1
5847 13:31:52.185816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5848 13:31:52.185900 ==
5849 13:31:52.189448 DQS Delay:
5850 13:31:52.189561 DQS0 = 0, DQS1 = 0
5851 13:31:52.192658 DQM Delay:
5852 13:31:52.192740 DQM0 = 93, DQM1 = 87
5853 13:31:52.192809 DQ Delay:
5854 13:31:52.196044 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =91
5855 13:31:52.199283 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5856 13:31:52.202630 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =79
5857 13:31:52.206118 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5858 13:31:52.209211
5859 13:31:52.209322
5860 13:31:52.209424 ==
5861 13:31:52.212342 Dram Type= 6, Freq= 0, CH_1, rank 1
5862 13:31:52.215671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5863 13:31:52.215791 ==
5864 13:31:52.215887
5865 13:31:52.215976
5866 13:31:52.218743 TX Vref Scan disable
5867 13:31:52.218861 == TX Byte 0 ==
5868 13:31:52.225491 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5869 13:31:52.228951 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5870 13:31:52.229083 == TX Byte 1 ==
5871 13:31:52.235326 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5872 13:31:52.238638 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5873 13:31:52.238721 ==
5874 13:31:52.241818 Dram Type= 6, Freq= 0, CH_1, rank 1
5875 13:31:52.245309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5876 13:31:52.245388 ==
5877 13:31:52.245452
5878 13:31:52.245511
5879 13:31:52.248935 TX Vref Scan disable
5880 13:31:52.251966 == TX Byte 0 ==
5881 13:31:52.255469 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5882 13:31:52.258661 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5883 13:31:52.262043 == TX Byte 1 ==
5884 13:31:52.265139 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5885 13:31:52.268153 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5886 13:31:52.272122
5887 13:31:52.272214 [DATLAT]
5888 13:31:52.272280 Freq=933, CH1 RK1
5889 13:31:52.272341
5890 13:31:52.275449 DATLAT Default: 0xb
5891 13:31:52.275528 0, 0xFFFF, sum = 0
5892 13:31:52.278729 1, 0xFFFF, sum = 0
5893 13:31:52.278809 2, 0xFFFF, sum = 0
5894 13:31:52.282005 3, 0xFFFF, sum = 0
5895 13:31:52.282109 4, 0xFFFF, sum = 0
5896 13:31:52.285242 5, 0xFFFF, sum = 0
5897 13:31:52.285352 6, 0xFFFF, sum = 0
5898 13:31:52.288474 7, 0xFFFF, sum = 0
5899 13:31:52.291824 8, 0xFFFF, sum = 0
5900 13:31:52.291905 9, 0xFFFF, sum = 0
5901 13:31:52.295146 10, 0x0, sum = 1
5902 13:31:52.295250 11, 0x0, sum = 2
5903 13:31:52.295343 12, 0x0, sum = 3
5904 13:31:52.298183 13, 0x0, sum = 4
5905 13:31:52.298298 best_step = 11
5906 13:31:52.298392
5907 13:31:52.298481 ==
5908 13:31:52.301454 Dram Type= 6, Freq= 0, CH_1, rank 1
5909 13:31:52.308430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5910 13:31:52.308531 ==
5911 13:31:52.308598 RX Vref Scan: 0
5912 13:31:52.308660
5913 13:31:52.311495 RX Vref 0 -> 0, step: 1
5914 13:31:52.311583
5915 13:31:52.314566 RX Delay -69 -> 252, step: 4
5916 13:31:52.318356 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5917 13:31:52.324880 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5918 13:31:52.328059 iDelay=203, Bit 2, Center 80 (-17 ~ 178) 196
5919 13:31:52.331287 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5920 13:31:52.334467 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5921 13:31:52.337891 iDelay=203, Bit 5, Center 102 (3 ~ 202) 200
5922 13:31:52.344089 iDelay=203, Bit 6, Center 102 (3 ~ 202) 200
5923 13:31:52.347917 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5924 13:31:52.350914 iDelay=203, Bit 8, Center 80 (-9 ~ 170) 180
5925 13:31:52.354051 iDelay=203, Bit 9, Center 84 (-9 ~ 178) 188
5926 13:31:52.357787 iDelay=203, Bit 10, Center 94 (3 ~ 186) 184
5927 13:31:52.361016 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5928 13:31:52.367307 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5929 13:31:52.370478 iDelay=203, Bit 13, Center 96 (3 ~ 190) 188
5930 13:31:52.374255 iDelay=203, Bit 14, Center 96 (7 ~ 186) 180
5931 13:31:52.377461 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
5932 13:31:52.377553 ==
5933 13:31:52.380684 Dram Type= 6, Freq= 0, CH_1, rank 1
5934 13:31:52.387156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5935 13:31:52.387251 ==
5936 13:31:52.387336 DQS Delay:
5937 13:31:52.387424 DQS0 = 0, DQS1 = 0
5938 13:31:52.390466 DQM Delay:
5939 13:31:52.390548 DQM0 = 91, DQM1 = 91
5940 13:31:52.393908 DQ Delay:
5941 13:31:52.397036 DQ0 =96, DQ1 =86, DQ2 =80, DQ3 =88
5942 13:31:52.400255 DQ4 =90, DQ5 =102, DQ6 =102, DQ7 =88
5943 13:31:52.403302 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =84
5944 13:31:52.407012 DQ12 =98, DQ13 =96, DQ14 =96, DQ15 =96
5945 13:31:52.407100
5946 13:31:52.407164
5947 13:31:52.413447 [DQSOSCAuto] RK1, (LSB)MR18= 0xf22, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 417 ps
5948 13:31:52.417059 CH1 RK1: MR19=505, MR18=F22
5949 13:31:52.423611 CH1_RK1: MR19=0x505, MR18=0xF22, DQSOSC=411, MR23=63, INC=64, DEC=42
5950 13:31:52.426894 [RxdqsGatingPostProcess] freq 933
5951 13:31:52.430002 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5952 13:31:52.433253 best DQS0 dly(2T, 0.5T) = (0, 10)
5953 13:31:52.437096 best DQS1 dly(2T, 0.5T) = (0, 10)
5954 13:31:52.440372 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5955 13:31:52.443493 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5956 13:31:52.446566 best DQS0 dly(2T, 0.5T) = (0, 10)
5957 13:31:52.450368 best DQS1 dly(2T, 0.5T) = (0, 10)
5958 13:31:52.453388 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5959 13:31:52.456449 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5960 13:31:52.460127 Pre-setting of DQS Precalculation
5961 13:31:52.463286 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5962 13:31:52.472896 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5963 13:31:52.479538 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5964 13:31:52.479681
5965 13:31:52.479790
5966 13:31:52.482792 [Calibration Summary] 1866 Mbps
5967 13:31:52.482911 CH 0, Rank 0
5968 13:31:52.485947 SW Impedance : PASS
5969 13:31:52.486061 DUTY Scan : NO K
5970 13:31:52.489839 ZQ Calibration : PASS
5971 13:31:52.493133 Jitter Meter : NO K
5972 13:31:52.493221 CBT Training : PASS
5973 13:31:52.496454 Write leveling : PASS
5974 13:31:52.499635 RX DQS gating : PASS
5975 13:31:52.499771 RX DQ/DQS(RDDQC) : PASS
5976 13:31:52.502911 TX DQ/DQS : PASS
5977 13:31:52.506123 RX DATLAT : PASS
5978 13:31:52.506251 RX DQ/DQS(Engine): PASS
5979 13:31:52.509354 TX OE : NO K
5980 13:31:52.509476 All Pass.
5981 13:31:52.509579
5982 13:31:52.512999 CH 0, Rank 1
5983 13:31:52.513099 SW Impedance : PASS
5984 13:31:52.516104 DUTY Scan : NO K
5985 13:31:52.519272 ZQ Calibration : PASS
5986 13:31:52.519412 Jitter Meter : NO K
5987 13:31:52.522472 CBT Training : PASS
5988 13:31:52.522560 Write leveling : PASS
5989 13:31:52.525915 RX DQS gating : PASS
5990 13:31:52.529105 RX DQ/DQS(RDDQC) : PASS
5991 13:31:52.529210 TX DQ/DQS : PASS
5992 13:31:52.532381 RX DATLAT : PASS
5993 13:31:52.536135 RX DQ/DQS(Engine): PASS
5994 13:31:52.536319 TX OE : NO K
5995 13:31:52.539342 All Pass.
5996 13:31:52.539447
5997 13:31:52.539515 CH 1, Rank 0
5998 13:31:52.542196 SW Impedance : PASS
5999 13:31:52.542279 DUTY Scan : NO K
6000 13:31:52.545876 ZQ Calibration : PASS
6001 13:31:52.549070 Jitter Meter : NO K
6002 13:31:52.549155 CBT Training : PASS
6003 13:31:52.552199 Write leveling : PASS
6004 13:31:52.555477 RX DQS gating : PASS
6005 13:31:52.555572 RX DQ/DQS(RDDQC) : PASS
6006 13:31:52.558512 TX DQ/DQS : PASS
6007 13:31:52.562101 RX DATLAT : PASS
6008 13:31:52.562240 RX DQ/DQS(Engine): PASS
6009 13:31:52.565107 TX OE : NO K
6010 13:31:52.565229 All Pass.
6011 13:31:52.565333
6012 13:31:52.568419 CH 1, Rank 1
6013 13:31:52.568533 SW Impedance : PASS
6014 13:31:52.572220 DUTY Scan : NO K
6015 13:31:52.575312 ZQ Calibration : PASS
6016 13:31:52.575421 Jitter Meter : NO K
6017 13:31:52.578515 CBT Training : PASS
6018 13:31:52.582051 Write leveling : PASS
6019 13:31:52.582143 RX DQS gating : PASS
6020 13:31:52.585179 RX DQ/DQS(RDDQC) : PASS
6021 13:31:52.588732 TX DQ/DQS : PASS
6022 13:31:52.588839 RX DATLAT : PASS
6023 13:31:52.591898 RX DQ/DQS(Engine): PASS
6024 13:31:52.591995 TX OE : NO K
6025 13:31:52.595139 All Pass.
6026 13:31:52.595256
6027 13:31:52.595351 DramC Write-DBI off
6028 13:31:52.598385 PER_BANK_REFRESH: Hybrid Mode
6029 13:31:52.601633 TX_TRACKING: ON
6030 13:31:52.608235 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6031 13:31:52.611408 [FAST_K] Save calibration result to emmc
6032 13:31:52.617965 dramc_set_vcore_voltage set vcore to 650000
6033 13:31:52.618079 Read voltage for 400, 6
6034 13:31:52.621624 Vio18 = 0
6035 13:31:52.621734 Vcore = 650000
6036 13:31:52.621838 Vdram = 0
6037 13:31:52.621946 Vddq = 0
6038 13:31:52.624921 Vmddr = 0
6039 13:31:52.627979 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6040 13:31:52.634928 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6041 13:31:52.638193 MEM_TYPE=3, freq_sel=20
6042 13:31:52.638270 sv_algorithm_assistance_LP4_800
6043 13:31:52.644567 ============ PULL DRAM RESETB DOWN ============
6044 13:31:52.648324 ========== PULL DRAM RESETB DOWN end =========
6045 13:31:52.651485 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6046 13:31:52.654665 ===================================
6047 13:31:52.657890 LPDDR4 DRAM CONFIGURATION
6048 13:31:52.661016 ===================================
6049 13:31:52.664192 EX_ROW_EN[0] = 0x0
6050 13:31:52.664304 EX_ROW_EN[1] = 0x0
6051 13:31:52.667888 LP4Y_EN = 0x0
6052 13:31:52.667989 WORK_FSP = 0x0
6053 13:31:52.671011 WL = 0x2
6054 13:31:52.671091 RL = 0x2
6055 13:31:52.674078 BL = 0x2
6056 13:31:52.674157 RPST = 0x0
6057 13:31:52.677405 RD_PRE = 0x0
6058 13:31:52.677490 WR_PRE = 0x1
6059 13:31:52.680959 WR_PST = 0x0
6060 13:31:52.684167 DBI_WR = 0x0
6061 13:31:52.684248 DBI_RD = 0x0
6062 13:31:52.687303 OTF = 0x1
6063 13:31:52.690896 ===================================
6064 13:31:52.693894 ===================================
6065 13:31:52.694031 ANA top config
6066 13:31:52.697503 ===================================
6067 13:31:52.700714 DLL_ASYNC_EN = 0
6068 13:31:52.703954 ALL_SLAVE_EN = 1
6069 13:31:52.704103 NEW_RANK_MODE = 1
6070 13:31:52.707827 DLL_IDLE_MODE = 1
6071 13:31:52.711010 LP45_APHY_COMB_EN = 1
6072 13:31:52.714321 TX_ODT_DIS = 1
6073 13:31:52.714407 NEW_8X_MODE = 1
6074 13:31:52.717531 ===================================
6075 13:31:52.720702 ===================================
6076 13:31:52.723953 data_rate = 800
6077 13:31:52.727185 CKR = 1
6078 13:31:52.730796 DQ_P2S_RATIO = 4
6079 13:31:52.733913 ===================================
6080 13:31:52.736952 CA_P2S_RATIO = 4
6081 13:31:52.740856 DQ_CA_OPEN = 0
6082 13:31:52.740963 DQ_SEMI_OPEN = 1
6083 13:31:52.744087 CA_SEMI_OPEN = 1
6084 13:31:52.747349 CA_FULL_RATE = 0
6085 13:31:52.750566 DQ_CKDIV4_EN = 0
6086 13:31:52.753643 CA_CKDIV4_EN = 1
6087 13:31:52.756790 CA_PREDIV_EN = 0
6088 13:31:52.760576 PH8_DLY = 0
6089 13:31:52.760660 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6090 13:31:52.763811 DQ_AAMCK_DIV = 0
6091 13:31:52.766467 CA_AAMCK_DIV = 0
6092 13:31:52.770288 CA_ADMCK_DIV = 4
6093 13:31:52.773404 DQ_TRACK_CA_EN = 0
6094 13:31:52.777043 CA_PICK = 800
6095 13:31:52.777126 CA_MCKIO = 400
6096 13:31:52.780211 MCKIO_SEMI = 400
6097 13:31:52.783381 PLL_FREQ = 3016
6098 13:31:52.786555 DQ_UI_PI_RATIO = 32
6099 13:31:52.789859 CA_UI_PI_RATIO = 32
6100 13:31:52.793171 ===================================
6101 13:31:52.796383 ===================================
6102 13:31:52.799528 memory_type:LPDDR4
6103 13:31:52.799613 GP_NUM : 10
6104 13:31:52.803068 SRAM_EN : 1
6105 13:31:52.806138 MD32_EN : 0
6106 13:31:52.809961 ===================================
6107 13:31:52.810045 [ANA_INIT] >>>>>>>>>>>>>>
6108 13:31:52.813096 <<<<<< [CONFIGURE PHASE]: ANA_TX
6109 13:31:52.816348 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6110 13:31:52.819593 ===================================
6111 13:31:52.822861 data_rate = 800,PCW = 0X7400
6112 13:31:52.826124 ===================================
6113 13:31:52.829473 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6114 13:31:52.836384 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6115 13:31:52.846335 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6116 13:31:52.852728 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6117 13:31:52.855833 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6118 13:31:52.859029 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6119 13:31:52.859142 [ANA_INIT] flow start
6120 13:31:52.862851 [ANA_INIT] PLL >>>>>>>>
6121 13:31:52.865968 [ANA_INIT] PLL <<<<<<<<
6122 13:31:52.866072 [ANA_INIT] MIDPI >>>>>>>>
6123 13:31:52.869176 [ANA_INIT] MIDPI <<<<<<<<
6124 13:31:52.872382 [ANA_INIT] DLL >>>>>>>>
6125 13:31:52.872482 [ANA_INIT] flow end
6126 13:31:52.879021 ============ LP4 DIFF to SE enter ============
6127 13:31:52.882121 ============ LP4 DIFF to SE exit ============
6128 13:31:52.885734 [ANA_INIT] <<<<<<<<<<<<<
6129 13:31:52.888929 [Flow] Enable top DCM control >>>>>
6130 13:31:52.892298 [Flow] Enable top DCM control <<<<<
6131 13:31:52.892411 Enable DLL master slave shuffle
6132 13:31:52.898757 ==============================================================
6133 13:31:52.901981 Gating Mode config
6134 13:31:52.905323 ==============================================================
6135 13:31:52.908438 Config description:
6136 13:31:52.918762 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6137 13:31:52.925281 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6138 13:31:52.928620 SELPH_MODE 0: By rank 1: By Phase
6139 13:31:52.935047 ==============================================================
6140 13:31:52.938228 GAT_TRACK_EN = 0
6141 13:31:52.942005 RX_GATING_MODE = 2
6142 13:31:52.945096 RX_GATING_TRACK_MODE = 2
6143 13:31:52.948245 SELPH_MODE = 1
6144 13:31:52.951354 PICG_EARLY_EN = 1
6145 13:31:52.951467 VALID_LAT_VALUE = 1
6146 13:31:52.958270 ==============================================================
6147 13:31:52.961451 Enter into Gating configuration >>>>
6148 13:31:52.964758 Exit from Gating configuration <<<<
6149 13:31:52.967934 Enter into DVFS_PRE_config >>>>>
6150 13:31:52.978373 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6151 13:31:52.981550 Exit from DVFS_PRE_config <<<<<
6152 13:31:52.984770 Enter into PICG configuration >>>>
6153 13:31:52.988314 Exit from PICG configuration <<<<
6154 13:31:52.991305 [RX_INPUT] configuration >>>>>
6155 13:31:52.994717 [RX_INPUT] configuration <<<<<
6156 13:31:52.997823 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6157 13:31:53.004853 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6158 13:31:53.011263 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6159 13:31:53.017839 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6160 13:31:53.024449 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6161 13:31:53.030986 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6162 13:31:53.034267 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6163 13:31:53.037401 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6164 13:31:53.040766 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6165 13:31:53.047242 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6166 13:31:53.050555 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6167 13:31:53.054177 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6168 13:31:53.057386 ===================================
6169 13:31:53.060511 LPDDR4 DRAM CONFIGURATION
6170 13:31:53.063723 ===================================
6171 13:31:53.063808 EX_ROW_EN[0] = 0x0
6172 13:31:53.067158 EX_ROW_EN[1] = 0x0
6173 13:31:53.070577 LP4Y_EN = 0x0
6174 13:31:53.070687 WORK_FSP = 0x0
6175 13:31:53.073806 WL = 0x2
6176 13:31:53.073912 RL = 0x2
6177 13:31:53.077081 BL = 0x2
6178 13:31:53.077188 RPST = 0x0
6179 13:31:53.080279 RD_PRE = 0x0
6180 13:31:53.080382 WR_PRE = 0x1
6181 13:31:53.083495 WR_PST = 0x0
6182 13:31:53.083578 DBI_WR = 0x0
6183 13:31:53.087340 DBI_RD = 0x0
6184 13:31:53.087431 OTF = 0x1
6185 13:31:53.090605 ===================================
6186 13:31:53.093750 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6187 13:31:53.100497 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6188 13:31:53.103607 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6189 13:31:53.107105 ===================================
6190 13:31:53.110381 LPDDR4 DRAM CONFIGURATION
6191 13:31:53.113639 ===================================
6192 13:31:53.113719 EX_ROW_EN[0] = 0x10
6193 13:31:53.116829 EX_ROW_EN[1] = 0x0
6194 13:31:53.120208 LP4Y_EN = 0x0
6195 13:31:53.120316 WORK_FSP = 0x0
6196 13:31:53.123332 WL = 0x2
6197 13:31:53.123423 RL = 0x2
6198 13:31:53.126495 BL = 0x2
6199 13:31:53.126571 RPST = 0x0
6200 13:31:53.130395 RD_PRE = 0x0
6201 13:31:53.130472 WR_PRE = 0x1
6202 13:31:53.133592 WR_PST = 0x0
6203 13:31:53.133693 DBI_WR = 0x0
6204 13:31:53.136751 DBI_RD = 0x0
6205 13:31:53.136851 OTF = 0x1
6206 13:31:53.139746 ===================================
6207 13:31:53.146416 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6208 13:31:53.150899 nWR fixed to 30
6209 13:31:53.154118 [ModeRegInit_LP4] CH0 RK0
6210 13:31:53.154233 [ModeRegInit_LP4] CH0 RK1
6211 13:31:53.157467 [ModeRegInit_LP4] CH1 RK0
6212 13:31:53.161159 [ModeRegInit_LP4] CH1 RK1
6213 13:31:53.161269 match AC timing 19
6214 13:31:53.167569 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6215 13:31:53.170822 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6216 13:31:53.173947 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6217 13:31:53.180850 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6218 13:31:53.183924 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6219 13:31:53.184034 ==
6220 13:31:53.187695 Dram Type= 6, Freq= 0, CH_0, rank 0
6221 13:31:53.190944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6222 13:31:53.191053 ==
6223 13:31:53.197365 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6224 13:31:53.203672 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6225 13:31:53.207434 [CA 0] Center 36 (8~64) winsize 57
6226 13:31:53.210434 [CA 1] Center 36 (8~64) winsize 57
6227 13:31:53.213925 [CA 2] Center 36 (8~64) winsize 57
6228 13:31:53.217192 [CA 3] Center 36 (8~64) winsize 57
6229 13:31:53.220341 [CA 4] Center 36 (8~64) winsize 57
6230 13:31:53.220464 [CA 5] Center 36 (8~64) winsize 57
6231 13:31:53.220563
6232 13:31:53.227498 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6233 13:31:53.227687
6234 13:31:53.230764 [CATrainingPosCal] consider 1 rank data
6235 13:31:53.234002 u2DelayCellTimex100 = 270/100 ps
6236 13:31:53.237109 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 13:31:53.240430 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 13:31:53.243670 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 13:31:53.246896 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 13:31:53.250559 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 13:31:53.253447 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 13:31:53.253557
6243 13:31:53.257026 CA PerBit enable=1, Macro0, CA PI delay=36
6244 13:31:53.257134
6245 13:31:53.260358 [CBTSetCACLKResult] CA Dly = 36
6246 13:31:53.263610 CS Dly: 1 (0~32)
6247 13:31:53.263718 ==
6248 13:31:53.266782 Dram Type= 6, Freq= 0, CH_0, rank 1
6249 13:31:53.270040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6250 13:31:53.270145 ==
6251 13:31:53.276612 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6252 13:31:53.283725 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6253 13:31:53.283849 [CA 0] Center 36 (8~64) winsize 57
6254 13:31:53.286864 [CA 1] Center 36 (8~64) winsize 57
6255 13:31:53.290228 [CA 2] Center 36 (8~64) winsize 57
6256 13:31:53.293595 [CA 3] Center 36 (8~64) winsize 57
6257 13:31:53.296542 [CA 4] Center 36 (8~64) winsize 57
6258 13:31:53.300203 [CA 5] Center 36 (8~64) winsize 57
6259 13:31:53.300302
6260 13:31:53.303347 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6261 13:31:53.303442
6262 13:31:53.306447 [CATrainingPosCal] consider 2 rank data
6263 13:31:53.309674 u2DelayCellTimex100 = 270/100 ps
6264 13:31:53.312970 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 13:31:53.320093 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 13:31:53.323109 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 13:31:53.326528 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 13:31:53.329950 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 13:31:53.333306 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 13:31:53.333420
6271 13:31:53.336555 CA PerBit enable=1, Macro0, CA PI delay=36
6272 13:31:53.336660
6273 13:31:53.339743 [CBTSetCACLKResult] CA Dly = 36
6274 13:31:53.342925 CS Dly: 1 (0~32)
6275 13:31:53.343027
6276 13:31:53.346141 ----->DramcWriteLeveling(PI) begin...
6277 13:31:53.346245 ==
6278 13:31:53.349933 Dram Type= 6, Freq= 0, CH_0, rank 0
6279 13:31:53.353194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6280 13:31:53.353295 ==
6281 13:31:53.356458 Write leveling (Byte 0): 40 => 8
6282 13:31:53.359501 Write leveling (Byte 1): 40 => 8
6283 13:31:53.363082 DramcWriteLeveling(PI) end<-----
6284 13:31:53.363193
6285 13:31:53.363300 ==
6286 13:31:53.366108 Dram Type= 6, Freq= 0, CH_0, rank 0
6287 13:31:53.369504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6288 13:31:53.369609 ==
6289 13:31:53.372879 [Gating] SW mode calibration
6290 13:31:53.379191 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6291 13:31:53.385841 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6292 13:31:53.389022 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6293 13:31:53.392876 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6294 13:31:53.399233 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6295 13:31:53.402269 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6296 13:31:53.405682 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6297 13:31:53.412138 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6298 13:31:53.415752 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6299 13:31:53.418974 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6300 13:31:53.425902 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6301 13:31:53.426012 Total UI for P1: 0, mck2ui 16
6302 13:31:53.432384 best dqsien dly found for B0: ( 0, 14, 24)
6303 13:31:53.432488 Total UI for P1: 0, mck2ui 16
6304 13:31:53.438819 best dqsien dly found for B1: ( 0, 14, 24)
6305 13:31:53.442354 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6306 13:31:53.445669 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6307 13:31:53.445773
6308 13:31:53.448957 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6309 13:31:53.452306 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6310 13:31:53.455565 [Gating] SW calibration Done
6311 13:31:53.455654 ==
6312 13:31:53.458889 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 13:31:53.462111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 13:31:53.462234 ==
6315 13:31:53.465115 RX Vref Scan: 0
6316 13:31:53.465222
6317 13:31:53.465315 RX Vref 0 -> 0, step: 1
6318 13:31:53.465402
6319 13:31:53.468806 RX Delay -410 -> 252, step: 16
6320 13:31:53.475014 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6321 13:31:53.478244 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6322 13:31:53.481559 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6323 13:31:53.484788 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6324 13:31:53.491705 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6325 13:31:53.495298 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6326 13:31:53.498690 iDelay=230, Bit 6, Center -35 (-282 ~ 213) 496
6327 13:31:53.501614 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6328 13:31:53.508137 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6329 13:31:53.511277 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6330 13:31:53.515076 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6331 13:31:53.518610 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6332 13:31:53.525192 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6333 13:31:53.528291 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6334 13:31:53.531512 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6335 13:31:53.537961 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6336 13:31:53.538069 ==
6337 13:31:53.541347 Dram Type= 6, Freq= 0, CH_0, rank 0
6338 13:31:53.545238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6339 13:31:53.545320 ==
6340 13:31:53.545385 DQS Delay:
6341 13:31:53.548321 DQS0 = 59, DQS1 = 59
6342 13:31:53.548402 DQM Delay:
6343 13:31:53.551139 DQM0 = 17, DQM1 = 10
6344 13:31:53.551220 DQ Delay:
6345 13:31:53.554668 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6346 13:31:53.557853 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6347 13:31:53.561067 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6348 13:31:53.564367 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6349 13:31:53.564469
6350 13:31:53.564567
6351 13:31:53.564658 ==
6352 13:31:53.568164 Dram Type= 6, Freq= 0, CH_0, rank 0
6353 13:31:53.571382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6354 13:31:53.571482 ==
6355 13:31:53.571591
6356 13:31:53.571681
6357 13:31:53.574609 TX Vref Scan disable
6358 13:31:53.577564 == TX Byte 0 ==
6359 13:31:53.581139 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6360 13:31:53.584382 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6361 13:31:53.587528 == TX Byte 1 ==
6362 13:31:53.590835 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6363 13:31:53.593958 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6364 13:31:53.594057 ==
6365 13:31:53.597806 Dram Type= 6, Freq= 0, CH_0, rank 0
6366 13:31:53.600981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6367 13:31:53.601081 ==
6368 13:31:53.603902
6369 13:31:53.604010
6370 13:31:53.604107 TX Vref Scan disable
6371 13:31:53.607224 == TX Byte 0 ==
6372 13:31:53.610553 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6373 13:31:53.613855 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6374 13:31:53.616980 == TX Byte 1 ==
6375 13:31:53.620852 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6376 13:31:53.623891 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6377 13:31:53.623973
6378 13:31:53.624036 [DATLAT]
6379 13:31:53.626984 Freq=400, CH0 RK0
6380 13:31:53.627092
6381 13:31:53.630785 DATLAT Default: 0xf
6382 13:31:53.630896 0, 0xFFFF, sum = 0
6383 13:31:53.633750 1, 0xFFFF, sum = 0
6384 13:31:53.633858 2, 0xFFFF, sum = 0
6385 13:31:53.637398 3, 0xFFFF, sum = 0
6386 13:31:53.637515 4, 0xFFFF, sum = 0
6387 13:31:53.640626 5, 0xFFFF, sum = 0
6388 13:31:53.640756 6, 0xFFFF, sum = 0
6389 13:31:53.643767 7, 0xFFFF, sum = 0
6390 13:31:53.643892 8, 0xFFFF, sum = 0
6391 13:31:53.647037 9, 0xFFFF, sum = 0
6392 13:31:53.647146 10, 0xFFFF, sum = 0
6393 13:31:53.650279 11, 0xFFFF, sum = 0
6394 13:31:53.650393 12, 0xFFFF, sum = 0
6395 13:31:53.654261 13, 0x0, sum = 1
6396 13:31:53.654371 14, 0x0, sum = 2
6397 13:31:53.657103 15, 0x0, sum = 3
6398 13:31:53.657217 16, 0x0, sum = 4
6399 13:31:53.660690 best_step = 14
6400 13:31:53.660806
6401 13:31:53.660905 ==
6402 13:31:53.663608 Dram Type= 6, Freq= 0, CH_0, rank 0
6403 13:31:53.666788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6404 13:31:53.666893 ==
6405 13:31:53.670113 RX Vref Scan: 1
6406 13:31:53.670215
6407 13:31:53.670307 RX Vref 0 -> 0, step: 1
6408 13:31:53.670395
6409 13:31:53.673509 RX Delay -359 -> 252, step: 8
6410 13:31:53.673595
6411 13:31:53.677364 Set Vref, RX VrefLevel [Byte0]: 62
6412 13:31:53.680684 [Byte1]: 47
6413 13:31:53.685026
6414 13:31:53.685136 Final RX Vref Byte 0 = 62 to rank0
6415 13:31:53.688175 Final RX Vref Byte 1 = 47 to rank0
6416 13:31:53.691178 Final RX Vref Byte 0 = 62 to rank1
6417 13:31:53.695069 Final RX Vref Byte 1 = 47 to rank1==
6418 13:31:53.698292 Dram Type= 6, Freq= 0, CH_0, rank 0
6419 13:31:53.704948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6420 13:31:53.705068 ==
6421 13:31:53.705168 DQS Delay:
6422 13:31:53.708305 DQS0 = 60, DQS1 = 64
6423 13:31:53.708418 DQM Delay:
6424 13:31:53.708512 DQM0 = 14, DQM1 = 9
6425 13:31:53.711080 DQ Delay:
6426 13:31:53.714365 DQ0 =12, DQ1 =16, DQ2 =12, DQ3 =12
6427 13:31:53.717613 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6428 13:31:53.717717 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6429 13:31:53.720896 DQ12 =16, DQ13 =12, DQ14 =20, DQ15 =16
6430 13:31:53.724647
6431 13:31:53.724757
6432 13:31:53.731051 [DQSOSCAuto] RK0, (LSB)MR18= 0x7e7d, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
6433 13:31:53.734435 CH0 RK0: MR19=C0C, MR18=7E7D
6434 13:31:53.741181 CH0_RK0: MR19=0xC0C, MR18=0x7E7D, DQSOSC=393, MR23=63, INC=382, DEC=254
6435 13:31:53.741288 ==
6436 13:31:53.744139 Dram Type= 6, Freq= 0, CH_0, rank 1
6437 13:31:53.747798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6438 13:31:53.747926 ==
6439 13:31:53.750949 [Gating] SW mode calibration
6440 13:31:53.757473 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6441 13:31:53.764054 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6442 13:31:53.767848 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6443 13:31:53.770848 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6444 13:31:53.777258 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6445 13:31:53.780943 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6446 13:31:53.784059 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6447 13:31:53.790982 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6448 13:31:53.794224 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6449 13:31:53.797375 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6450 13:31:53.803910 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6451 13:31:53.804022 Total UI for P1: 0, mck2ui 16
6452 13:31:53.807111 best dqsien dly found for B0: ( 0, 14, 24)
6453 13:31:53.810926 Total UI for P1: 0, mck2ui 16
6454 13:31:53.814203 best dqsien dly found for B1: ( 0, 14, 24)
6455 13:31:53.820877 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6456 13:31:53.824080 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6457 13:31:53.824198
6458 13:31:53.827280 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6459 13:31:53.830425 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6460 13:31:53.833642 [Gating] SW calibration Done
6461 13:31:53.833751 ==
6462 13:31:53.836952 Dram Type= 6, Freq= 0, CH_0, rank 1
6463 13:31:53.840835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 13:31:53.840940 ==
6465 13:31:53.844015 RX Vref Scan: 0
6466 13:31:53.844121
6467 13:31:53.844212 RX Vref 0 -> 0, step: 1
6468 13:31:53.844303
6469 13:31:53.847186 RX Delay -410 -> 252, step: 16
6470 13:31:53.853794 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6471 13:31:53.856872 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6472 13:31:53.860525 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6473 13:31:53.863807 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6474 13:31:53.870446 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6475 13:31:53.873776 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6476 13:31:53.876872 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6477 13:31:53.880114 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6478 13:31:53.887024 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6479 13:31:53.890383 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6480 13:31:53.893454 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6481 13:31:53.896930 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6482 13:31:53.903203 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6483 13:31:53.906901 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6484 13:31:53.909967 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6485 13:31:53.913350 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6486 13:31:53.916491 ==
6487 13:31:53.916602 Dram Type= 6, Freq= 0, CH_0, rank 1
6488 13:31:53.923060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6489 13:31:53.923176 ==
6490 13:31:53.923287 DQS Delay:
6491 13:31:53.926621 DQS0 = 59, DQS1 = 59
6492 13:31:53.926729 DQM Delay:
6493 13:31:53.930245 DQM0 = 16, DQM1 = 10
6494 13:31:53.930349 DQ Delay:
6495 13:31:53.933300 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6496 13:31:53.936370 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6497 13:31:53.939663 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6498 13:31:53.943549 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6499 13:31:53.943633
6500 13:31:53.943698
6501 13:31:53.943758 ==
6502 13:31:53.946215 Dram Type= 6, Freq= 0, CH_0, rank 1
6503 13:31:53.949999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6504 13:31:53.950082 ==
6505 13:31:53.950147
6506 13:31:53.950207
6507 13:31:53.953345 TX Vref Scan disable
6508 13:31:53.953427 == TX Byte 0 ==
6509 13:31:53.959635 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6510 13:31:53.962716 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6511 13:31:53.962799 == TX Byte 1 ==
6512 13:31:53.969441 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6513 13:31:53.973259 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6514 13:31:53.973342 ==
6515 13:31:53.976465 Dram Type= 6, Freq= 0, CH_0, rank 1
6516 13:31:53.979721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6517 13:31:53.979803 ==
6518 13:31:53.979869
6519 13:31:53.979929
6520 13:31:53.982957 TX Vref Scan disable
6521 13:31:53.983039 == TX Byte 0 ==
6522 13:31:53.989597 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6523 13:31:53.992737 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6524 13:31:53.992833 == TX Byte 1 ==
6525 13:31:53.999321 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6526 13:31:54.002610 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6527 13:31:54.002716
6528 13:31:54.002797 [DATLAT]
6529 13:31:54.006056 Freq=400, CH0 RK1
6530 13:31:54.006201
6531 13:31:54.006265 DATLAT Default: 0xe
6532 13:31:54.009528 0, 0xFFFF, sum = 0
6533 13:31:54.009613 1, 0xFFFF, sum = 0
6534 13:31:54.012563 2, 0xFFFF, sum = 0
6535 13:31:54.012644 3, 0xFFFF, sum = 0
6536 13:31:54.015781 4, 0xFFFF, sum = 0
6537 13:31:54.015863 5, 0xFFFF, sum = 0
6538 13:31:54.019585 6, 0xFFFF, sum = 0
6539 13:31:54.019713 7, 0xFFFF, sum = 0
6540 13:31:54.022679 8, 0xFFFF, sum = 0
6541 13:31:54.025889 9, 0xFFFF, sum = 0
6542 13:31:54.025972 10, 0xFFFF, sum = 0
6543 13:31:54.029077 11, 0xFFFF, sum = 0
6544 13:31:54.029164 12, 0xFFFF, sum = 0
6545 13:31:54.032521 13, 0x0, sum = 1
6546 13:31:54.032631 14, 0x0, sum = 2
6547 13:31:54.035695 15, 0x0, sum = 3
6548 13:31:54.035775 16, 0x0, sum = 4
6549 13:31:54.035840 best_step = 14
6550 13:31:54.039097
6551 13:31:54.039194 ==
6552 13:31:54.042487 Dram Type= 6, Freq= 0, CH_0, rank 1
6553 13:31:54.046016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6554 13:31:54.046100 ==
6555 13:31:54.046165 RX Vref Scan: 0
6556 13:31:54.046225
6557 13:31:54.049336 RX Vref 0 -> 0, step: 1
6558 13:31:54.049417
6559 13:31:54.052591 RX Delay -359 -> 252, step: 8
6560 13:31:54.059704 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6561 13:31:54.063011 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6562 13:31:54.066044 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6563 13:31:54.072844 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6564 13:31:54.075810 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6565 13:31:54.079302 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6566 13:31:54.082575 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6567 13:31:54.085854 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6568 13:31:54.092403 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6569 13:31:54.095747 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6570 13:31:54.099059 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6571 13:31:54.105993 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6572 13:31:54.109491 iDelay=217, Bit 12, Center -48 (-295 ~ 200) 496
6573 13:31:54.112564 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6574 13:31:54.115993 iDelay=217, Bit 14, Center -48 (-295 ~ 200) 496
6575 13:31:54.122520 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6576 13:31:54.122637 ==
6577 13:31:54.125990 Dram Type= 6, Freq= 0, CH_0, rank 1
6578 13:31:54.128973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6579 13:31:54.129073 ==
6580 13:31:54.129164 DQS Delay:
6581 13:31:54.132233 DQS0 = 60, DQS1 = 72
6582 13:31:54.132303 DQM Delay:
6583 13:31:54.136047 DQM0 = 11, DQM1 = 17
6584 13:31:54.136138 DQ Delay:
6585 13:31:54.139300 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6586 13:31:54.142520 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6587 13:31:54.145727 DQ8 =12, DQ9 =0, DQ10 =20, DQ11 =8
6588 13:31:54.148758 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6589 13:31:54.148832
6590 13:31:54.148894
6591 13:31:54.155830 [DQSOSCAuto] RK1, (LSB)MR18= 0xbe73, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps
6592 13:31:54.158801 CH0 RK1: MR19=C0C, MR18=BE73
6593 13:31:54.165896 CH0_RK1: MR19=0xC0C, MR18=0xBE73, DQSOSC=386, MR23=63, INC=396, DEC=264
6594 13:31:54.169131 [RxdqsGatingPostProcess] freq 400
6595 13:31:54.175611 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6596 13:31:54.178863 best DQS0 dly(2T, 0.5T) = (0, 10)
6597 13:31:54.178945 best DQS1 dly(2T, 0.5T) = (0, 10)
6598 13:31:54.182003 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6599 13:31:54.185162 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6600 13:31:54.188734 best DQS0 dly(2T, 0.5T) = (0, 10)
6601 13:31:54.191780 best DQS1 dly(2T, 0.5T) = (0, 10)
6602 13:31:54.195552 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6603 13:31:54.198747 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6604 13:31:54.202027 Pre-setting of DQS Precalculation
6605 13:31:54.208602 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6606 13:31:54.208720 ==
6607 13:31:54.211870 Dram Type= 6, Freq= 0, CH_1, rank 0
6608 13:31:54.214985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6609 13:31:54.215067 ==
6610 13:31:54.222019 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6611 13:31:54.224990 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6612 13:31:54.228558 [CA 0] Center 36 (8~64) winsize 57
6613 13:31:54.231739 [CA 1] Center 36 (8~64) winsize 57
6614 13:31:54.234782 [CA 2] Center 36 (8~64) winsize 57
6615 13:31:54.238200 [CA 3] Center 36 (8~64) winsize 57
6616 13:31:54.241818 [CA 4] Center 36 (8~64) winsize 57
6617 13:31:54.244937 [CA 5] Center 36 (8~64) winsize 57
6618 13:31:54.245010
6619 13:31:54.248242 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6620 13:31:54.248319
6621 13:31:54.251437 [CATrainingPosCal] consider 1 rank data
6622 13:31:54.254618 u2DelayCellTimex100 = 270/100 ps
6623 13:31:54.257925 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 13:31:54.264404 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 13:31:54.267945 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 13:31:54.270969 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 13:31:54.274780 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 13:31:54.277963 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 13:31:54.278061
6630 13:31:54.281150 CA PerBit enable=1, Macro0, CA PI delay=36
6631 13:31:54.281262
6632 13:31:54.284432 [CBTSetCACLKResult] CA Dly = 36
6633 13:31:54.287588 CS Dly: 1 (0~32)
6634 13:31:54.287663 ==
6635 13:31:54.290690 Dram Type= 6, Freq= 0, CH_1, rank 1
6636 13:31:54.294508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6637 13:31:54.294578 ==
6638 13:31:54.301257 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6639 13:31:54.304430 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6640 13:31:54.307627 [CA 0] Center 36 (8~64) winsize 57
6641 13:31:54.310855 [CA 1] Center 36 (8~64) winsize 57
6642 13:31:54.314121 [CA 2] Center 36 (8~64) winsize 57
6643 13:31:54.317414 [CA 3] Center 36 (8~64) winsize 57
6644 13:31:54.320686 [CA 4] Center 36 (8~64) winsize 57
6645 13:31:54.323875 [CA 5] Center 36 (8~64) winsize 57
6646 13:31:54.323959
6647 13:31:54.327076 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6648 13:31:54.327175
6649 13:31:54.330240 [CATrainingPosCal] consider 2 rank data
6650 13:31:54.333854 u2DelayCellTimex100 = 270/100 ps
6651 13:31:54.337013 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 13:31:54.340289 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 13:31:54.347015 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 13:31:54.350075 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 13:31:54.353574 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 13:31:54.356682 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 13:31:54.356767
6658 13:31:54.360065 CA PerBit enable=1, Macro0, CA PI delay=36
6659 13:31:54.360151
6660 13:31:54.363301 [CBTSetCACLKResult] CA Dly = 36
6661 13:31:54.363421 CS Dly: 1 (0~32)
6662 13:31:54.363509
6663 13:31:54.366751 ----->DramcWriteLeveling(PI) begin...
6664 13:31:54.370399 ==
6665 13:31:54.373593 Dram Type= 6, Freq= 0, CH_1, rank 0
6666 13:31:54.377084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6667 13:31:54.377172 ==
6668 13:31:54.379976 Write leveling (Byte 0): 40 => 8
6669 13:31:54.383042 Write leveling (Byte 1): 40 => 8
6670 13:31:54.386270 DramcWriteLeveling(PI) end<-----
6671 13:31:54.386349
6672 13:31:54.386434 ==
6673 13:31:54.389596 Dram Type= 6, Freq= 0, CH_1, rank 0
6674 13:31:54.393428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6675 13:31:54.393514 ==
6676 13:31:54.396579 [Gating] SW mode calibration
6677 13:31:54.402838 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6678 13:31:54.409539 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6679 13:31:54.413246 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6680 13:31:54.416485 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6681 13:31:54.422700 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6682 13:31:54.425960 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6683 13:31:54.429800 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6684 13:31:54.436386 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6685 13:31:54.439221 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6686 13:31:54.442553 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6687 13:31:54.448914 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6688 13:31:54.449002 Total UI for P1: 0, mck2ui 16
6689 13:31:54.455641 best dqsien dly found for B0: ( 0, 14, 24)
6690 13:31:54.455753 Total UI for P1: 0, mck2ui 16
6691 13:31:54.459324 best dqsien dly found for B1: ( 0, 14, 24)
6692 13:31:54.465753 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6693 13:31:54.468875 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6694 13:31:54.468963
6695 13:31:54.472703 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6696 13:31:54.475958 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6697 13:31:54.479202 [Gating] SW calibration Done
6698 13:31:54.479312 ==
6699 13:31:54.482510 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 13:31:54.485510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 13:31:54.485597 ==
6702 13:31:54.488989 RX Vref Scan: 0
6703 13:31:54.489075
6704 13:31:54.489162 RX Vref 0 -> 0, step: 1
6705 13:31:54.489245
6706 13:31:54.492509 RX Delay -410 -> 252, step: 16
6707 13:31:54.498828 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6708 13:31:54.502061 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6709 13:31:54.505335 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6710 13:31:54.508656 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6711 13:31:54.515588 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6712 13:31:54.518640 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6713 13:31:54.521884 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6714 13:31:54.525035 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6715 13:31:54.531896 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6716 13:31:54.535159 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6717 13:31:54.538422 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6718 13:31:54.541617 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6719 13:31:54.548325 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6720 13:31:54.551561 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6721 13:31:54.554728 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6722 13:31:54.561202 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6723 13:31:54.561315 ==
6724 13:31:54.565073 Dram Type= 6, Freq= 0, CH_1, rank 0
6725 13:31:54.568150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6726 13:31:54.568261 ==
6727 13:31:54.568365 DQS Delay:
6728 13:31:54.571133 DQS0 = 51, DQS1 = 67
6729 13:31:54.571234 DQM Delay:
6730 13:31:54.574726 DQM0 = 13, DQM1 = 19
6731 13:31:54.574812 DQ Delay:
6732 13:31:54.577792 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6733 13:31:54.580930 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6734 13:31:54.584820 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6735 13:31:54.588023 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6736 13:31:54.588112
6737 13:31:54.588190
6738 13:31:54.588252 ==
6739 13:31:54.591323 Dram Type= 6, Freq= 0, CH_1, rank 0
6740 13:31:54.594686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6741 13:31:54.594769 ==
6742 13:31:54.594834
6743 13:31:54.594894
6744 13:31:54.597557 TX Vref Scan disable
6745 13:31:54.597639 == TX Byte 0 ==
6746 13:31:54.604585 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6747 13:31:54.607594 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6748 13:31:54.607703 == TX Byte 1 ==
6749 13:31:54.614004 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6750 13:31:54.617301 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6751 13:31:54.617410 ==
6752 13:31:54.621054 Dram Type= 6, Freq= 0, CH_1, rank 0
6753 13:31:54.624172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6754 13:31:54.624256 ==
6755 13:31:54.624321
6756 13:31:54.627686
6757 13:31:54.627768 TX Vref Scan disable
6758 13:31:54.630766 == TX Byte 0 ==
6759 13:31:54.634342 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6760 13:31:54.637373 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6761 13:31:54.640596 == TX Byte 1 ==
6762 13:31:54.643825 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6763 13:31:54.647548 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6764 13:31:54.647656
6765 13:31:54.647752 [DATLAT]
6766 13:31:54.650556 Freq=400, CH1 RK0
6767 13:31:54.650639
6768 13:31:54.653707 DATLAT Default: 0xf
6769 13:31:54.653790 0, 0xFFFF, sum = 0
6770 13:31:54.656971 1, 0xFFFF, sum = 0
6771 13:31:54.657056 2, 0xFFFF, sum = 0
6772 13:31:54.660245 3, 0xFFFF, sum = 0
6773 13:31:54.660330 4, 0xFFFF, sum = 0
6774 13:31:54.664136 5, 0xFFFF, sum = 0
6775 13:31:54.664220 6, 0xFFFF, sum = 0
6776 13:31:54.667302 7, 0xFFFF, sum = 0
6777 13:31:54.667416 8, 0xFFFF, sum = 0
6778 13:31:54.670453 9, 0xFFFF, sum = 0
6779 13:31:54.670537 10, 0xFFFF, sum = 0
6780 13:31:54.673611 11, 0xFFFF, sum = 0
6781 13:31:54.673695 12, 0xFFFF, sum = 0
6782 13:31:54.676789 13, 0x0, sum = 1
6783 13:31:54.676874 14, 0x0, sum = 2
6784 13:31:54.680011 15, 0x0, sum = 3
6785 13:31:54.680095 16, 0x0, sum = 4
6786 13:31:54.683480 best_step = 14
6787 13:31:54.683562
6788 13:31:54.683627 ==
6789 13:31:54.687113 Dram Type= 6, Freq= 0, CH_1, rank 0
6790 13:31:54.690283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6791 13:31:54.690367 ==
6792 13:31:54.693455 RX Vref Scan: 1
6793 13:31:54.693537
6794 13:31:54.693608 RX Vref 0 -> 0, step: 1
6795 13:31:54.693671
6796 13:31:54.696682 RX Delay -375 -> 252, step: 8
6797 13:31:54.696766
6798 13:31:54.700528 Set Vref, RX VrefLevel [Byte0]: 59
6799 13:31:54.703740 [Byte1]: 49
6800 13:31:54.708109
6801 13:31:54.708189 Final RX Vref Byte 0 = 59 to rank0
6802 13:31:54.711219 Final RX Vref Byte 1 = 49 to rank0
6803 13:31:54.714817 Final RX Vref Byte 0 = 59 to rank1
6804 13:31:54.718251 Final RX Vref Byte 1 = 49 to rank1==
6805 13:31:54.721421 Dram Type= 6, Freq= 0, CH_1, rank 0
6806 13:31:54.728000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6807 13:31:54.728088 ==
6808 13:31:54.728154 DQS Delay:
6809 13:31:54.731084 DQS0 = 56, DQS1 = 68
6810 13:31:54.731166 DQM Delay:
6811 13:31:54.731232 DQM0 = 13, DQM1 = 14
6812 13:31:54.734906 DQ Delay:
6813 13:31:54.738003 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6814 13:31:54.738086 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6815 13:31:54.741616 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6816 13:31:54.744583 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6817 13:31:54.744666
6818 13:31:54.747694
6819 13:31:54.754603 [DQSOSCAuto] RK0, (LSB)MR18= 0x5064, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 399 ps
6820 13:31:54.757592 CH1 RK0: MR19=C0C, MR18=5064
6821 13:31:54.764300 CH1_RK0: MR19=0xC0C, MR18=0x5064, DQSOSC=397, MR23=63, INC=374, DEC=249
6822 13:31:54.764388 ==
6823 13:31:54.767590 Dram Type= 6, Freq= 0, CH_1, rank 1
6824 13:31:54.770798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6825 13:31:54.770882 ==
6826 13:31:54.774072 [Gating] SW mode calibration
6827 13:31:54.781099 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6828 13:31:54.787654 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6829 13:31:54.790728 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6830 13:31:54.794141 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6831 13:31:54.801005 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6832 13:31:54.804365 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6833 13:31:54.807722 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6834 13:31:54.813950 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6835 13:31:54.817298 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6836 13:31:54.820570 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6837 13:31:54.826891 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6838 13:31:54.826979 Total UI for P1: 0, mck2ui 16
6839 13:31:54.833550 best dqsien dly found for B0: ( 0, 14, 24)
6840 13:31:54.833638 Total UI for P1: 0, mck2ui 16
6841 13:31:54.837331 best dqsien dly found for B1: ( 0, 14, 24)
6842 13:31:54.843643 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6843 13:31:54.847338 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6844 13:31:54.847432
6845 13:31:54.850479 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6846 13:31:54.853662 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6847 13:31:54.856820 [Gating] SW calibration Done
6848 13:31:54.856904 ==
6849 13:31:54.860495 Dram Type= 6, Freq= 0, CH_1, rank 1
6850 13:31:54.863515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 13:31:54.863599 ==
6852 13:31:54.866727 RX Vref Scan: 0
6853 13:31:54.866809
6854 13:31:54.866873 RX Vref 0 -> 0, step: 1
6855 13:31:54.866933
6856 13:31:54.870020 RX Delay -410 -> 252, step: 16
6857 13:31:54.876593 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6858 13:31:54.879753 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6859 13:31:54.883121 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6860 13:31:54.886449 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6861 13:31:54.893094 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6862 13:31:54.896888 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6863 13:31:54.899926 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6864 13:31:54.903032 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6865 13:31:54.910095 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6866 13:31:54.913292 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6867 13:31:54.916349 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6868 13:31:54.919593 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6869 13:31:54.926673 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6870 13:31:54.929984 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6871 13:31:54.933081 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6872 13:31:54.936166 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6873 13:31:54.939752 ==
6874 13:31:54.943160 Dram Type= 6, Freq= 0, CH_1, rank 1
6875 13:31:54.946124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6876 13:31:54.946208 ==
6877 13:31:54.946273 DQS Delay:
6878 13:31:54.949779 DQS0 = 59, DQS1 = 59
6879 13:31:54.949862 DQM Delay:
6880 13:31:54.952822 DQM0 = 19, DQM1 = 12
6881 13:31:54.952905 DQ Delay:
6882 13:31:54.955921 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6883 13:31:54.959689 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6884 13:31:54.962843 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6885 13:31:54.965937 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6886 13:31:54.966038
6887 13:31:54.966135
6888 13:31:54.966225 ==
6889 13:31:54.969513 Dram Type= 6, Freq= 0, CH_1, rank 1
6890 13:31:54.972755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6891 13:31:54.972858 ==
6892 13:31:54.972952
6893 13:31:54.973039
6894 13:31:54.976005 TX Vref Scan disable
6895 13:31:54.976090 == TX Byte 0 ==
6896 13:31:54.982396 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6897 13:31:54.986292 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6898 13:31:54.986395 == TX Byte 1 ==
6899 13:31:54.992784 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6900 13:31:54.995957 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6901 13:31:54.996038 ==
6902 13:31:54.999314 Dram Type= 6, Freq= 0, CH_1, rank 1
6903 13:31:55.002518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6904 13:31:55.002626 ==
6905 13:31:55.002694
6906 13:31:55.002753
6907 13:31:55.005806 TX Vref Scan disable
6908 13:31:55.009104 == TX Byte 0 ==
6909 13:31:55.012740 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6910 13:31:55.016155 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6911 13:31:55.016258 == TX Byte 1 ==
6912 13:31:55.022647 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6913 13:31:55.025843 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6914 13:31:55.025949
6915 13:31:55.026041 [DATLAT]
6916 13:31:55.029127 Freq=400, CH1 RK1
6917 13:31:55.029210
6918 13:31:55.029275 DATLAT Default: 0xe
6919 13:31:55.032312 0, 0xFFFF, sum = 0
6920 13:31:55.032396 1, 0xFFFF, sum = 0
6921 13:31:55.035506 2, 0xFFFF, sum = 0
6922 13:31:55.035590 3, 0xFFFF, sum = 0
6923 13:31:55.038896 4, 0xFFFF, sum = 0
6924 13:31:55.042175 5, 0xFFFF, sum = 0
6925 13:31:55.042260 6, 0xFFFF, sum = 0
6926 13:31:55.045499 7, 0xFFFF, sum = 0
6927 13:31:55.045583 8, 0xFFFF, sum = 0
6928 13:31:55.049215 9, 0xFFFF, sum = 0
6929 13:31:55.049299 10, 0xFFFF, sum = 0
6930 13:31:55.052193 11, 0xFFFF, sum = 0
6931 13:31:55.052299 12, 0xFFFF, sum = 0
6932 13:31:55.055779 13, 0x0, sum = 1
6933 13:31:55.055863 14, 0x0, sum = 2
6934 13:31:55.059074 15, 0x0, sum = 3
6935 13:31:55.059157 16, 0x0, sum = 4
6936 13:31:55.062142 best_step = 14
6937 13:31:55.062225
6938 13:31:55.062290 ==
6939 13:31:55.065595 Dram Type= 6, Freq= 0, CH_1, rank 1
6940 13:31:55.068661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6941 13:31:55.068745 ==
6942 13:31:55.068811 RX Vref Scan: 0
6943 13:31:55.068872
6944 13:31:55.072131 RX Vref 0 -> 0, step: 1
6945 13:31:55.072214
6946 13:31:55.075611 RX Delay -359 -> 252, step: 8
6947 13:31:55.082581 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6948 13:31:55.085955 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6949 13:31:55.089145 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6950 13:31:55.095861 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6951 13:31:55.099186 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6952 13:31:55.102378 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6953 13:31:55.105662 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6954 13:31:55.112758 iDelay=217, Bit 7, Center -48 (-303 ~ 208) 512
6955 13:31:55.116133 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6956 13:31:55.119256 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6957 13:31:55.122306 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6958 13:31:55.129457 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6959 13:31:55.132527 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6960 13:31:55.135681 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6961 13:31:55.138910 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6962 13:31:55.145448 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6963 13:31:55.145534 ==
6964 13:31:55.148623 Dram Type= 6, Freq= 0, CH_1, rank 1
6965 13:31:55.152509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6966 13:31:55.152595 ==
6967 13:31:55.152685 DQS Delay:
6968 13:31:55.155705 DQS0 = 60, DQS1 = 64
6969 13:31:55.155791 DQM Delay:
6970 13:31:55.158963 DQM0 = 13, DQM1 = 10
6971 13:31:55.159047 DQ Delay:
6972 13:31:55.162259 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6973 13:31:55.165241 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
6974 13:31:55.168376 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6975 13:31:55.172177 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6976 13:31:55.172265
6977 13:31:55.172352
6978 13:31:55.178348 [DQSOSCAuto] RK1, (LSB)MR18= 0x7aa9, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
6979 13:31:55.181723 CH1 RK1: MR19=C0C, MR18=7AA9
6980 13:31:55.188435 CH1_RK1: MR19=0xC0C, MR18=0x7AA9, DQSOSC=388, MR23=63, INC=392, DEC=261
6981 13:31:55.192016 [RxdqsGatingPostProcess] freq 400
6982 13:31:55.198244 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6983 13:31:55.201577 best DQS0 dly(2T, 0.5T) = (0, 10)
6984 13:31:55.204831 best DQS1 dly(2T, 0.5T) = (0, 10)
6985 13:31:55.208155 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6986 13:31:55.211348 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6987 13:31:55.211445 best DQS0 dly(2T, 0.5T) = (0, 10)
6988 13:31:55.215296 best DQS1 dly(2T, 0.5T) = (0, 10)
6989 13:31:55.218532 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6990 13:31:55.221735 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6991 13:31:55.224989 Pre-setting of DQS Precalculation
6992 13:31:55.231348 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6993 13:31:55.237902 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6994 13:31:55.244581 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6995 13:31:55.244670
6996 13:31:55.244760
6997 13:31:55.248343 [Calibration Summary] 800 Mbps
6998 13:31:55.248455 CH 0, Rank 0
6999 13:31:55.251575 SW Impedance : PASS
7000 13:31:55.254852 DUTY Scan : NO K
7001 13:31:55.254926 ZQ Calibration : PASS
7002 13:31:55.258129 Jitter Meter : NO K
7003 13:31:55.261377 CBT Training : PASS
7004 13:31:55.261450 Write leveling : PASS
7005 13:31:55.264613 RX DQS gating : PASS
7006 13:31:55.267842 RX DQ/DQS(RDDQC) : PASS
7007 13:31:55.267915 TX DQ/DQS : PASS
7008 13:31:55.271595 RX DATLAT : PASS
7009 13:31:55.274868 RX DQ/DQS(Engine): PASS
7010 13:31:55.274943 TX OE : NO K
7011 13:31:55.275041 All Pass.
7012 13:31:55.278091
7013 13:31:55.278176 CH 0, Rank 1
7014 13:31:55.281341 SW Impedance : PASS
7015 13:31:55.281426 DUTY Scan : NO K
7016 13:31:55.284460 ZQ Calibration : PASS
7017 13:31:55.284546 Jitter Meter : NO K
7018 13:31:55.288089 CBT Training : PASS
7019 13:31:55.291302 Write leveling : NO K
7020 13:31:55.291416 RX DQS gating : PASS
7021 13:31:55.294797 RX DQ/DQS(RDDQC) : PASS
7022 13:31:55.297690 TX DQ/DQS : PASS
7023 13:31:55.297794 RX DATLAT : PASS
7024 13:31:55.301257 RX DQ/DQS(Engine): PASS
7025 13:31:55.304349 TX OE : NO K
7026 13:31:55.304451 All Pass.
7027 13:31:55.304534
7028 13:31:55.304613 CH 1, Rank 0
7029 13:31:55.307826 SW Impedance : PASS
7030 13:31:55.311238 DUTY Scan : NO K
7031 13:31:55.311348 ZQ Calibration : PASS
7032 13:31:55.314729 Jitter Meter : NO K
7033 13:31:55.317746 CBT Training : PASS
7034 13:31:55.317832 Write leveling : PASS
7035 13:31:55.321075 RX DQS gating : PASS
7036 13:31:55.324321 RX DQ/DQS(RDDQC) : PASS
7037 13:31:55.324407 TX DQ/DQS : PASS
7038 13:31:55.327635 RX DATLAT : PASS
7039 13:31:55.330875 RX DQ/DQS(Engine): PASS
7040 13:31:55.330985 TX OE : NO K
7041 13:31:55.331090 All Pass.
7042 13:31:55.334125
7043 13:31:55.334211 CH 1, Rank 1
7044 13:31:55.337420 SW Impedance : PASS
7045 13:31:55.337505 DUTY Scan : NO K
7046 13:31:55.340622 ZQ Calibration : PASS
7047 13:31:55.344227 Jitter Meter : NO K
7048 13:31:55.344312 CBT Training : PASS
7049 13:31:55.347316 Write leveling : NO K
7050 13:31:55.347426 RX DQS gating : PASS
7051 13:31:55.351096 RX DQ/DQS(RDDQC) : PASS
7052 13:31:55.354053 TX DQ/DQS : PASS
7053 13:31:55.354139 RX DATLAT : PASS
7054 13:31:55.357778 RX DQ/DQS(Engine): PASS
7055 13:31:55.360924 TX OE : NO K
7056 13:31:55.361027 All Pass.
7057 13:31:55.361122
7058 13:31:55.364236 DramC Write-DBI off
7059 13:31:55.364339 PER_BANK_REFRESH: Hybrid Mode
7060 13:31:55.367454 TX_TRACKING: ON
7061 13:31:55.377238 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7062 13:31:55.380366 [FAST_K] Save calibration result to emmc
7063 13:31:55.384257 dramc_set_vcore_voltage set vcore to 725000
7064 13:31:55.384365 Read voltage for 1600, 0
7065 13:31:55.387530 Vio18 = 0
7066 13:31:55.387604 Vcore = 725000
7067 13:31:55.387667 Vdram = 0
7068 13:31:55.390782 Vddq = 0
7069 13:31:55.390862 Vmddr = 0
7070 13:31:55.397007 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7071 13:31:55.400810 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7072 13:31:55.403713 MEM_TYPE=3, freq_sel=13
7073 13:31:55.407045 sv_algorithm_assistance_LP4_3733
7074 13:31:55.410517 ============ PULL DRAM RESETB DOWN ============
7075 13:31:55.414024 ========== PULL DRAM RESETB DOWN end =========
7076 13:31:55.420709 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7077 13:31:55.423718 ===================================
7078 13:31:55.423806 LPDDR4 DRAM CONFIGURATION
7079 13:31:55.427094 ===================================
7080 13:31:55.430225 EX_ROW_EN[0] = 0x0
7081 13:31:55.430338 EX_ROW_EN[1] = 0x0
7082 13:31:55.433414 LP4Y_EN = 0x0
7083 13:31:55.436712 WORK_FSP = 0x1
7084 13:31:55.436825 WL = 0x5
7085 13:31:55.440043 RL = 0x5
7086 13:31:55.440123 BL = 0x2
7087 13:31:55.443985 RPST = 0x0
7088 13:31:55.444091 RD_PRE = 0x0
7089 13:31:55.447229 WR_PRE = 0x1
7090 13:31:55.447334 WR_PST = 0x1
7091 13:31:55.450364 DBI_WR = 0x0
7092 13:31:55.450475 DBI_RD = 0x0
7093 13:31:55.453303 OTF = 0x1
7094 13:31:55.456918 ===================================
7095 13:31:55.460057 ===================================
7096 13:31:55.460137 ANA top config
7097 13:31:55.463790 ===================================
7098 13:31:55.466972 DLL_ASYNC_EN = 0
7099 13:31:55.470320 ALL_SLAVE_EN = 0
7100 13:31:55.470404 NEW_RANK_MODE = 1
7101 13:31:55.473679 DLL_IDLE_MODE = 1
7102 13:31:55.476926 LP45_APHY_COMB_EN = 1
7103 13:31:55.480064 TX_ODT_DIS = 0
7104 13:31:55.483390 NEW_8X_MODE = 1
7105 13:31:55.486682 ===================================
7106 13:31:55.486789 ===================================
7107 13:31:55.489963 data_rate = 3200
7108 13:31:55.493848 CKR = 1
7109 13:31:55.497116 DQ_P2S_RATIO = 8
7110 13:31:55.500319 ===================================
7111 13:31:55.503541 CA_P2S_RATIO = 8
7112 13:31:55.506620 DQ_CA_OPEN = 0
7113 13:31:55.509912 DQ_SEMI_OPEN = 0
7114 13:31:55.510021 CA_SEMI_OPEN = 0
7115 13:31:55.513566 CA_FULL_RATE = 0
7116 13:31:55.516571 DQ_CKDIV4_EN = 0
7117 13:31:55.520038 CA_CKDIV4_EN = 0
7118 13:31:55.523705 CA_PREDIV_EN = 0
7119 13:31:55.526459 PH8_DLY = 12
7120 13:31:55.526573 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7121 13:31:55.530266 DQ_AAMCK_DIV = 4
7122 13:31:55.533633 CA_AAMCK_DIV = 4
7123 13:31:55.536893 CA_ADMCK_DIV = 4
7124 13:31:55.539792 DQ_TRACK_CA_EN = 0
7125 13:31:55.543648 CA_PICK = 1600
7126 13:31:55.546892 CA_MCKIO = 1600
7127 13:31:55.547008 MCKIO_SEMI = 0
7128 13:31:55.550252 PLL_FREQ = 3068
7129 13:31:55.553463 DQ_UI_PI_RATIO = 32
7130 13:31:55.556699 CA_UI_PI_RATIO = 0
7131 13:31:55.559942 ===================================
7132 13:31:55.563028 ===================================
7133 13:31:55.566597 memory_type:LPDDR4
7134 13:31:55.566711 GP_NUM : 10
7135 13:31:55.569778 SRAM_EN : 1
7136 13:31:55.573092 MD32_EN : 0
7137 13:31:55.576414 ===================================
7138 13:31:55.576534 [ANA_INIT] >>>>>>>>>>>>>>
7139 13:31:55.579865 <<<<<< [CONFIGURE PHASE]: ANA_TX
7140 13:31:55.583089 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7141 13:31:55.586447 ===================================
7142 13:31:55.589796 data_rate = 3200,PCW = 0X7600
7143 13:31:55.593089 ===================================
7144 13:31:55.596452 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7145 13:31:55.603048 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7146 13:31:55.606490 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7147 13:31:55.612436 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7148 13:31:55.615737 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7149 13:31:55.619597 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7150 13:31:55.619700 [ANA_INIT] flow start
7151 13:31:55.622793 [ANA_INIT] PLL >>>>>>>>
7152 13:31:55.625860 [ANA_INIT] PLL <<<<<<<<
7153 13:31:55.628998 [ANA_INIT] MIDPI >>>>>>>>
7154 13:31:55.629107 [ANA_INIT] MIDPI <<<<<<<<
7155 13:31:55.632617 [ANA_INIT] DLL >>>>>>>>
7156 13:31:55.635715 [ANA_INIT] DLL <<<<<<<<
7157 13:31:55.635798 [ANA_INIT] flow end
7158 13:31:55.639264 ============ LP4 DIFF to SE enter ============
7159 13:31:55.646060 ============ LP4 DIFF to SE exit ============
7160 13:31:55.646170 [ANA_INIT] <<<<<<<<<<<<<
7161 13:31:55.649112 [Flow] Enable top DCM control >>>>>
7162 13:31:55.652222 [Flow] Enable top DCM control <<<<<
7163 13:31:55.655972 Enable DLL master slave shuffle
7164 13:31:55.662466 ==============================================================
7165 13:31:55.662580 Gating Mode config
7166 13:31:55.668745 ==============================================================
7167 13:31:55.672304 Config description:
7168 13:31:55.682225 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7169 13:31:55.689071 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7170 13:31:55.692320 SELPH_MODE 0: By rank 1: By Phase
7171 13:31:55.698745 ==============================================================
7172 13:31:55.701972 GAT_TRACK_EN = 1
7173 13:31:55.705250 RX_GATING_MODE = 2
7174 13:31:55.708315 RX_GATING_TRACK_MODE = 2
7175 13:31:55.708419 SELPH_MODE = 1
7176 13:31:55.711587 PICG_EARLY_EN = 1
7177 13:31:55.715463 VALID_LAT_VALUE = 1
7178 13:31:55.721907 ==============================================================
7179 13:31:55.725027 Enter into Gating configuration >>>>
7180 13:31:55.728265 Exit from Gating configuration <<<<
7181 13:31:55.731463 Enter into DVFS_PRE_config >>>>>
7182 13:31:55.741399 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7183 13:31:55.745125 Exit from DVFS_PRE_config <<<<<
7184 13:31:55.748112 Enter into PICG configuration >>>>
7185 13:31:55.751700 Exit from PICG configuration <<<<
7186 13:31:55.754819 [RX_INPUT] configuration >>>>>
7187 13:31:55.757910 [RX_INPUT] configuration <<<<<
7188 13:31:55.761637 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7189 13:31:55.768106 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7190 13:31:55.775187 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7191 13:31:55.781628 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7192 13:31:55.787861 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7193 13:31:55.791403 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7194 13:31:55.797852 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7195 13:31:55.801689 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7196 13:31:55.804914 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7197 13:31:55.808145 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7198 13:31:55.814375 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7199 13:31:55.817656 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7200 13:31:55.820999 ===================================
7201 13:31:55.824763 LPDDR4 DRAM CONFIGURATION
7202 13:31:55.827828 ===================================
7203 13:31:55.827941 EX_ROW_EN[0] = 0x0
7204 13:31:55.831065 EX_ROW_EN[1] = 0x0
7205 13:31:55.831173 LP4Y_EN = 0x0
7206 13:31:55.834244 WORK_FSP = 0x1
7207 13:31:55.834327 WL = 0x5
7208 13:31:55.838001 RL = 0x5
7209 13:31:55.838083 BL = 0x2
7210 13:31:55.841204 RPST = 0x0
7211 13:31:55.841286 RD_PRE = 0x0
7212 13:31:55.844392 WR_PRE = 0x1
7213 13:31:55.847328 WR_PST = 0x1
7214 13:31:55.847430 DBI_WR = 0x0
7215 13:31:55.851010 DBI_RD = 0x0
7216 13:31:55.851121 OTF = 0x1
7217 13:31:55.854039 ===================================
7218 13:31:55.857636 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7219 13:31:55.860655 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7220 13:31:55.867552 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7221 13:31:55.870800 ===================================
7222 13:31:55.874018 LPDDR4 DRAM CONFIGURATION
7223 13:31:55.877245 ===================================
7224 13:31:55.877328 EX_ROW_EN[0] = 0x10
7225 13:31:55.881118 EX_ROW_EN[1] = 0x0
7226 13:31:55.881201 LP4Y_EN = 0x0
7227 13:31:55.884292 WORK_FSP = 0x1
7228 13:31:55.884441 WL = 0x5
7229 13:31:55.887243 RL = 0x5
7230 13:31:55.887355 BL = 0x2
7231 13:31:55.890827 RPST = 0x0
7232 13:31:55.890988 RD_PRE = 0x0
7233 13:31:55.894390 WR_PRE = 0x1
7234 13:31:55.894472 WR_PST = 0x1
7235 13:31:55.897569 DBI_WR = 0x0
7236 13:31:55.897650 DBI_RD = 0x0
7237 13:31:55.900724 OTF = 0x1
7238 13:31:55.904472 ===================================
7239 13:31:55.910956 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7240 13:31:55.911042 ==
7241 13:31:55.914128 Dram Type= 6, Freq= 0, CH_0, rank 0
7242 13:31:55.917233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7243 13:31:55.917315 ==
7244 13:31:55.920614 [Duty_Offset_Calibration]
7245 13:31:55.920694 B0:2 B1:0 CA:3
7246 13:31:55.920758
7247 13:31:55.923870 [DutyScan_Calibration_Flow] k_type=0
7248 13:31:55.934781
7249 13:31:55.934863 ==CLK 0==
7250 13:31:55.938059 Final CLK duty delay cell = 0
7251 13:31:55.941808 [0] MAX Duty = 5031%(X100), DQS PI = 12
7252 13:31:55.945074 [0] MIN Duty = 4907%(X100), DQS PI = 6
7253 13:31:55.945158 [0] AVG Duty = 4969%(X100)
7254 13:31:55.948345
7255 13:31:55.951318 CH0 CLK Duty spec in!! Max-Min= 124%
7256 13:31:55.955098 [DutyScan_Calibration_Flow] ====Done====
7257 13:31:55.955181
7258 13:31:55.958348 [DutyScan_Calibration_Flow] k_type=1
7259 13:31:55.975125
7260 13:31:55.975215 ==DQS 0 ==
7261 13:31:55.978176 Final DQS duty delay cell = 0
7262 13:31:55.981361 [0] MAX Duty = 5125%(X100), DQS PI = 30
7263 13:31:55.985163 [0] MIN Duty = 4875%(X100), DQS PI = 48
7264 13:31:55.988446 [0] AVG Duty = 5000%(X100)
7265 13:31:55.988532
7266 13:31:55.988619 ==DQS 1 ==
7267 13:31:55.991684 Final DQS duty delay cell = 0
7268 13:31:55.994898 [0] MAX Duty = 5156%(X100), DQS PI = 32
7269 13:31:55.997906 [0] MIN Duty = 5031%(X100), DQS PI = 12
7270 13:31:56.001380 [0] AVG Duty = 5093%(X100)
7271 13:31:56.001465
7272 13:31:56.005026 CH0 DQS 0 Duty spec in!! Max-Min= 250%
7273 13:31:56.005113
7274 13:31:56.008158 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7275 13:31:56.011134 [DutyScan_Calibration_Flow] ====Done====
7276 13:31:56.011219
7277 13:31:56.014339 [DutyScan_Calibration_Flow] k_type=3
7278 13:31:56.032827
7279 13:31:56.032927 ==DQM 0 ==
7280 13:31:56.036584 Final DQM duty delay cell = 0
7281 13:31:56.039848 [0] MAX Duty = 5156%(X100), DQS PI = 28
7282 13:31:56.042977 [0] MIN Duty = 4844%(X100), DQS PI = 50
7283 13:31:56.046038 [0] AVG Duty = 5000%(X100)
7284 13:31:56.046124
7285 13:31:56.046212 ==DQM 1 ==
7286 13:31:56.049274 Final DQM duty delay cell = 4
7287 13:31:56.052496 [4] MAX Duty = 5187%(X100), DQS PI = 60
7288 13:31:56.055735 [4] MIN Duty = 5031%(X100), DQS PI = 12
7289 13:31:56.059299 [4] AVG Duty = 5109%(X100)
7290 13:31:56.059413
7291 13:31:56.062479 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7292 13:31:56.062561
7293 13:31:56.065709 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7294 13:31:56.068938 [DutyScan_Calibration_Flow] ====Done====
7295 13:31:56.069021
7296 13:31:56.072021 [DutyScan_Calibration_Flow] k_type=2
7297 13:31:56.089850
7298 13:31:56.089943 ==DQ 0 ==
7299 13:31:56.093129 Final DQ duty delay cell = -4
7300 13:31:56.096376 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7301 13:31:56.099591 [-4] MIN Duty = 4876%(X100), DQS PI = 44
7302 13:31:56.102767 [-4] AVG Duty = 4938%(X100)
7303 13:31:56.102849
7304 13:31:56.102914 ==DQ 1 ==
7305 13:31:56.105843 Final DQ duty delay cell = 0
7306 13:31:56.109589 [0] MAX Duty = 5156%(X100), DQS PI = 58
7307 13:31:56.112440 [0] MIN Duty = 5000%(X100), DQS PI = 16
7308 13:31:56.115966 [0] AVG Duty = 5078%(X100)
7309 13:31:56.116048
7310 13:31:56.119032 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7311 13:31:56.119113
7312 13:31:56.122719 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7313 13:31:56.125738 [DutyScan_Calibration_Flow] ====Done====
7314 13:31:56.125820 ==
7315 13:31:56.129399 Dram Type= 6, Freq= 0, CH_1, rank 0
7316 13:31:56.132564 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7317 13:31:56.132676 ==
7318 13:31:56.135889 [Duty_Offset_Calibration]
7319 13:31:56.135970 B0:1 B1:-2 CA:0
7320 13:31:56.136035
7321 13:31:56.139157 [DutyScan_Calibration_Flow] k_type=0
7322 13:31:56.150106
7323 13:31:56.150188 ==CLK 0==
7324 13:31:56.153313 Final CLK duty delay cell = 0
7325 13:31:56.157138 [0] MAX Duty = 5031%(X100), DQS PI = 52
7326 13:31:56.160395 [0] MIN Duty = 4875%(X100), DQS PI = 26
7327 13:31:56.163479 [0] AVG Duty = 4953%(X100)
7328 13:31:56.163562
7329 13:31:56.166555 CH1 CLK Duty spec in!! Max-Min= 156%
7330 13:31:56.169839 [DutyScan_Calibration_Flow] ====Done====
7331 13:31:56.169922
7332 13:31:56.173129 [DutyScan_Calibration_Flow] k_type=1
7333 13:31:56.190161
7334 13:31:56.190247 ==DQS 0 ==
7335 13:31:56.193129 Final DQS duty delay cell = 0
7336 13:31:56.196301 [0] MAX Duty = 5156%(X100), DQS PI = 0
7337 13:31:56.200033 [0] MIN Duty = 5062%(X100), DQS PI = 14
7338 13:31:56.203356 [0] AVG Duty = 5109%(X100)
7339 13:31:56.203450
7340 13:31:56.203515 ==DQS 1 ==
7341 13:31:56.206504 Final DQS duty delay cell = 0
7342 13:31:56.209718 [0] MAX Duty = 5124%(X100), DQS PI = 30
7343 13:31:56.212893 [0] MIN Duty = 4844%(X100), DQS PI = 56
7344 13:31:56.216603 [0] AVG Duty = 4984%(X100)
7345 13:31:56.216685
7346 13:31:56.219696 CH1 DQS 0 Duty spec in!! Max-Min= 94%
7347 13:31:56.219778
7348 13:31:56.222696 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7349 13:31:56.226281 [DutyScan_Calibration_Flow] ====Done====
7350 13:31:56.226364
7351 13:31:56.229387 [DutyScan_Calibration_Flow] k_type=3
7352 13:31:56.246752
7353 13:31:56.246839 ==DQM 0 ==
7354 13:31:56.250008 Final DQM duty delay cell = 0
7355 13:31:56.253177 [0] MAX Duty = 5000%(X100), DQS PI = 0
7356 13:31:56.257003 [0] MIN Duty = 4844%(X100), DQS PI = 22
7357 13:31:56.257086 [0] AVG Duty = 4922%(X100)
7358 13:31:56.260175
7359 13:31:56.260269 ==DQM 1 ==
7360 13:31:56.263451 Final DQM duty delay cell = 0
7361 13:31:56.266653 [0] MAX Duty = 5062%(X100), DQS PI = 4
7362 13:31:56.270338 [0] MIN Duty = 4875%(X100), DQS PI = 36
7363 13:31:56.270439 [0] AVG Duty = 4968%(X100)
7364 13:31:56.270529
7365 13:31:56.276547 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7366 13:31:56.276648
7367 13:31:56.280439 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7368 13:31:56.283425 [DutyScan_Calibration_Flow] ====Done====
7369 13:31:56.283522
7370 13:31:56.286695 [DutyScan_Calibration_Flow] k_type=2
7371 13:31:56.303619
7372 13:31:56.303853 ==DQ 0 ==
7373 13:31:56.306806 Final DQ duty delay cell = 0
7374 13:31:56.309936 [0] MAX Duty = 5062%(X100), DQS PI = 0
7375 13:31:56.313295 [0] MIN Duty = 4938%(X100), DQS PI = 14
7376 13:31:56.313393 [0] AVG Duty = 5000%(X100)
7377 13:31:56.316457
7378 13:31:56.316561 ==DQ 1 ==
7379 13:31:56.320358 Final DQ duty delay cell = 0
7380 13:31:56.323344 [0] MAX Duty = 5156%(X100), DQS PI = 26
7381 13:31:56.326713 [0] MIN Duty = 4938%(X100), DQS PI = 56
7382 13:31:56.326818 [0] AVG Duty = 5047%(X100)
7383 13:31:56.329818
7384 13:31:56.333436 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7385 13:31:56.333535
7386 13:31:56.336484 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7387 13:31:56.339872 [DutyScan_Calibration_Flow] ====Done====
7388 13:31:56.343121 nWR fixed to 30
7389 13:31:56.343217 [ModeRegInit_LP4] CH0 RK0
7390 13:31:56.346805 [ModeRegInit_LP4] CH0 RK1
7391 13:31:56.349950 [ModeRegInit_LP4] CH1 RK0
7392 13:31:56.352910 [ModeRegInit_LP4] CH1 RK1
7393 13:31:56.352992 match AC timing 5
7394 13:31:56.359910 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7395 13:31:56.363133 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7396 13:31:56.366432 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7397 13:31:56.372854 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7398 13:31:56.375880 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7399 13:31:56.375963 [MiockJmeterHQA]
7400 13:31:56.376029
7401 13:31:56.379528 [DramcMiockJmeter] u1RxGatingPI = 0
7402 13:31:56.382698 0 : 4254, 4029
7403 13:31:56.382810 4 : 4253, 4027
7404 13:31:56.386026 8 : 4255, 4030
7405 13:31:56.386111 12 : 4253, 4027
7406 13:31:56.389155 16 : 4250, 4027
7407 13:31:56.389240 20 : 4255, 4029
7408 13:31:56.389306 24 : 4252, 4027
7409 13:31:56.392259 28 : 4365, 4140
7410 13:31:56.392343 32 : 4254, 4029
7411 13:31:56.395591 36 : 4255, 4030
7412 13:31:56.395675 40 : 4252, 4027
7413 13:31:56.398925 44 : 4363, 4137
7414 13:31:56.399013 48 : 4255, 4029
7415 13:31:56.402116 52 : 4360, 4137
7416 13:31:56.402203 56 : 4250, 4027
7417 13:31:56.402271 60 : 4250, 4027
7418 13:31:56.405346 64 : 4250, 4026
7419 13:31:56.405429 68 : 4252, 4030
7420 13:31:56.409089 72 : 4249, 4027
7421 13:31:56.409174 76 : 4250, 4027
7422 13:31:56.412220 80 : 4363, 4140
7423 13:31:56.412305 84 : 4250, 4026
7424 13:31:56.415745 88 : 4252, 4030
7425 13:31:56.415829 92 : 4250, 4027
7426 13:31:56.415896 96 : 4361, 4137
7427 13:31:56.418822 100 : 4250, 4027
7428 13:31:56.418905 104 : 4249, 3845
7429 13:31:56.422152 108 : 4250, 7
7430 13:31:56.422236 112 : 4361, 0
7431 13:31:56.425402 116 : 4250, 0
7432 13:31:56.425490 120 : 4250, 0
7433 13:31:56.425557 124 : 4250, 0
7434 13:31:56.428596 128 : 4250, 0
7435 13:31:56.428684 132 : 4361, 0
7436 13:31:56.428752 136 : 4250, 0
7437 13:31:56.431878 140 : 4250, 0
7438 13:31:56.431962 144 : 4360, 0
7439 13:31:56.435098 148 : 4360, 0
7440 13:31:56.435209 152 : 4363, 0
7441 13:31:56.435308 156 : 4250, 0
7442 13:31:56.438904 160 : 4361, 0
7443 13:31:56.439010 164 : 4250, 0
7444 13:31:56.441920 168 : 4250, 0
7445 13:31:56.442025 172 : 4250, 0
7446 13:31:56.442126 176 : 4249, 0
7447 13:31:56.445028 180 : 4253, 0
7448 13:31:56.445109 184 : 4361, 0
7449 13:31:56.448673 188 : 4251, 0
7450 13:31:56.448761 192 : 4249, 0
7451 13:31:56.448849 196 : 4250, 0
7452 13:31:56.451687 200 : 4360, 0
7453 13:31:56.451774 204 : 4360, 0
7454 13:31:56.454893 208 : 4250, 0
7455 13:31:56.455007 212 : 4250, 0
7456 13:31:56.455112 216 : 4250, 0
7457 13:31:56.458613 220 : 4252, 0
7458 13:31:56.458701 224 : 4250, 0
7459 13:31:56.458788 228 : 4250, 0
7460 13:31:56.461606 232 : 4252, 0
7461 13:31:56.461685 236 : 4361, 1434
7462 13:31:56.465315 240 : 4250, 4027
7463 13:31:56.465404 244 : 4363, 4140
7464 13:31:56.468560 248 : 4361, 4137
7465 13:31:56.468667 252 : 4250, 4026
7466 13:31:56.471560 256 : 4250, 4027
7467 13:31:56.471647 260 : 4252, 4030
7468 13:31:56.474756 264 : 4250, 4026
7469 13:31:56.474844 268 : 4250, 4026
7470 13:31:56.478891 272 : 4361, 4138
7471 13:31:56.479007 276 : 4250, 4027
7472 13:31:56.479116 280 : 4249, 4027
7473 13:31:56.481862 284 : 4361, 4138
7474 13:31:56.481976 288 : 4361, 4137
7475 13:31:56.484794 292 : 4250, 4027
7476 13:31:56.484905 296 : 4363, 4140
7477 13:31:56.488495 300 : 4361, 4138
7478 13:31:56.488600 304 : 4250, 4026
7479 13:31:56.491592 308 : 4250, 4027
7480 13:31:56.491675 312 : 4250, 4027
7481 13:31:56.494808 316 : 4250, 4027
7482 13:31:56.494915 320 : 4250, 4026
7483 13:31:56.497991 324 : 4250, 4027
7484 13:31:56.498106 328 : 4252, 4029
7485 13:31:56.501360 332 : 4250, 4026
7486 13:31:56.501435 336 : 4361, 4137
7487 13:31:56.501499 340 : 4361, 4137
7488 13:31:56.504656 344 : 4250, 4027
7489 13:31:56.504731 348 : 4362, 4140
7490 13:31:56.508554 352 : 4361, 4134
7491 13:31:56.508658 356 : 4250, 3112
7492 13:31:56.511824 360 : 4250, 1
7493 13:31:56.511898
7494 13:31:56.511960 MIOCK jitter meter ch=0
7495 13:31:56.515003
7496 13:31:56.515103 1T = (360-108) = 252 dly cells
7497 13:31:56.521142 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7498 13:31:56.521246 ==
7499 13:31:56.524793 Dram Type= 6, Freq= 0, CH_0, rank 0
7500 13:31:56.527895 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7501 13:31:56.527975 ==
7502 13:31:56.534637 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7503 13:31:56.537769 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7504 13:31:56.544410 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7505 13:31:56.548170 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7506 13:31:56.558438 [CA 0] Center 44 (14~75) winsize 62
7507 13:31:56.561604 [CA 1] Center 43 (13~74) winsize 62
7508 13:31:56.564737 [CA 2] Center 40 (11~69) winsize 59
7509 13:31:56.568365 [CA 3] Center 39 (10~68) winsize 59
7510 13:31:56.571431 [CA 4] Center 37 (8~67) winsize 60
7511 13:31:56.575044 [CA 5] Center 37 (7~67) winsize 61
7512 13:31:56.575156
7513 13:31:56.578404 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7514 13:31:56.578499
7515 13:31:56.581687 [CATrainingPosCal] consider 1 rank data
7516 13:31:56.584978 u2DelayCellTimex100 = 258/100 ps
7517 13:31:56.591639 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7518 13:31:56.594708 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7519 13:31:56.597912 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7520 13:31:56.601783 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7521 13:31:56.605037 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7522 13:31:56.607769 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7523 13:31:56.607845
7524 13:31:56.611068 CA PerBit enable=1, Macro0, CA PI delay=37
7525 13:31:56.611167
7526 13:31:56.614948 [CBTSetCACLKResult] CA Dly = 37
7527 13:31:56.618137 CS Dly: 11 (0~42)
7528 13:31:56.621494 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7529 13:31:56.624704 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7530 13:31:56.624810 ==
7531 13:31:56.627806 Dram Type= 6, Freq= 0, CH_0, rank 1
7532 13:31:56.634415 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7533 13:31:56.634496 ==
7534 13:31:56.638119 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7535 13:31:56.644563 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7536 13:31:56.647696 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7537 13:31:56.654277 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7538 13:31:56.662323 [CA 0] Center 44 (13~75) winsize 63
7539 13:31:56.665336 [CA 1] Center 43 (13~74) winsize 62
7540 13:31:56.668890 [CA 2] Center 39 (10~69) winsize 60
7541 13:31:56.672041 [CA 3] Center 39 (10~68) winsize 59
7542 13:31:56.675847 [CA 4] Center 37 (8~67) winsize 60
7543 13:31:56.678987 [CA 5] Center 36 (7~66) winsize 60
7544 13:31:56.679092
7545 13:31:56.681960 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7546 13:31:56.682063
7547 13:31:56.685674 [CATrainingPosCal] consider 2 rank data
7548 13:31:56.688860 u2DelayCellTimex100 = 258/100 ps
7549 13:31:56.695234 CA0 delay=44 (14~75),Diff = 8 PI (30 cell)
7550 13:31:56.698834 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7551 13:31:56.702124 CA2 delay=40 (11~69),Diff = 4 PI (15 cell)
7552 13:31:56.705218 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7553 13:31:56.708517 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
7554 13:31:56.711891 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7555 13:31:56.711973
7556 13:31:56.715078 CA PerBit enable=1, Macro0, CA PI delay=36
7557 13:31:56.715161
7558 13:31:56.718391 [CBTSetCACLKResult] CA Dly = 36
7559 13:31:56.722186 CS Dly: 11 (0~43)
7560 13:31:56.725346 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7561 13:31:56.728655 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7562 13:31:56.728764
7563 13:31:56.732018 ----->DramcWriteLeveling(PI) begin...
7564 13:31:56.732134 ==
7565 13:31:56.735183 Dram Type= 6, Freq= 0, CH_0, rank 0
7566 13:31:56.741976 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7567 13:31:56.742088 ==
7568 13:31:56.745159 Write leveling (Byte 0): 35 => 35
7569 13:31:56.748364 Write leveling (Byte 1): 30 => 30
7570 13:31:56.748440 DramcWriteLeveling(PI) end<-----
7571 13:31:56.751921
7572 13:31:56.751995 ==
7573 13:31:56.755018 Dram Type= 6, Freq= 0, CH_0, rank 0
7574 13:31:56.758230 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7575 13:31:56.758335 ==
7576 13:31:56.761445 [Gating] SW mode calibration
7577 13:31:56.767903 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7578 13:31:56.771694 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7579 13:31:56.778163 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7580 13:31:56.781313 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7581 13:31:56.784546 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7582 13:31:56.791178 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7583 13:31:56.794323 1 4 16 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
7584 13:31:56.797593 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7585 13:31:56.804631 1 4 24 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
7586 13:31:56.807790 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7587 13:31:56.811191 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7588 13:31:56.817879 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7589 13:31:56.821081 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7590 13:31:56.824280 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7591 13:31:56.830862 1 5 16 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
7592 13:31:56.834196 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7593 13:31:56.837520 1 5 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
7594 13:31:56.844376 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7595 13:31:56.847431 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7596 13:31:56.850675 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7597 13:31:56.857519 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7598 13:31:56.860474 1 6 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7599 13:31:56.864196 1 6 16 | B1->B0 | 2323 3c3b | 0 1 | (0 0) (0 0)
7600 13:31:56.870491 1 6 20 | B1->B0 | 2323 4646 | 1 0 | (0 0) (0 0)
7601 13:31:56.873862 1 6 24 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
7602 13:31:56.877079 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7603 13:31:56.883403 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7604 13:31:56.887042 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7605 13:31:56.890035 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7606 13:31:56.896891 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7607 13:31:56.899821 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7608 13:31:56.903710 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7609 13:31:56.910259 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7610 13:31:56.913514 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 13:31:56.916525 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 13:31:56.922904 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 13:31:56.926598 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 13:31:56.929896 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 13:31:56.936419 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 13:31:56.939759 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 13:31:56.943033 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 13:31:56.949374 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 13:31:56.953048 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 13:31:56.956162 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 13:31:56.963125 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 13:31:56.966429 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 13:31:56.969571 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7624 13:31:56.975974 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7625 13:31:56.979107 Total UI for P1: 0, mck2ui 16
7626 13:31:56.982383 best dqsien dly found for B0: ( 1, 9, 16)
7627 13:31:56.986272 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7628 13:31:56.989417 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7629 13:31:56.992791 Total UI for P1: 0, mck2ui 16
7630 13:31:56.995829 best dqsien dly found for B1: ( 1, 9, 24)
7631 13:31:56.999352 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7632 13:31:57.002287 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7633 13:31:57.002395
7634 13:31:57.008948 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7635 13:31:57.012680 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7636 13:31:57.015913 [Gating] SW calibration Done
7637 13:31:57.016003 ==
7638 13:31:57.019113 Dram Type= 6, Freq= 0, CH_0, rank 0
7639 13:31:57.022378 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7640 13:31:57.022455 ==
7641 13:31:57.022524 RX Vref Scan: 0
7642 13:31:57.025439
7643 13:31:57.025521 RX Vref 0 -> 0, step: 1
7644 13:31:57.025586
7645 13:31:57.029220 RX Delay 0 -> 252, step: 8
7646 13:31:57.032172 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7647 13:31:57.035696 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7648 13:31:57.042139 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7649 13:31:57.045333 iDelay=200, Bit 3, Center 119 (64 ~ 175) 112
7650 13:31:57.049116 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7651 13:31:57.051743 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
7652 13:31:57.055510 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7653 13:31:57.062357 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7654 13:31:57.065607 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7655 13:31:57.068894 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7656 13:31:57.072119 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7657 13:31:57.075487 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
7658 13:31:57.082111 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7659 13:31:57.085158 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7660 13:31:57.088340 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7661 13:31:57.091422 iDelay=200, Bit 15, Center 127 (72 ~ 183) 112
7662 13:31:57.091507 ==
7663 13:31:57.094768 Dram Type= 6, Freq= 0, CH_0, rank 0
7664 13:31:57.101590 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7665 13:31:57.101700 ==
7666 13:31:57.101792 DQS Delay:
7667 13:31:57.105208 DQS0 = 0, DQS1 = 0
7668 13:31:57.105294 DQM Delay:
7669 13:31:57.108321 DQM0 = 127, DQM1 = 123
7670 13:31:57.108404 DQ Delay:
7671 13:31:57.111316 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119
7672 13:31:57.115007 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
7673 13:31:57.118035 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7674 13:31:57.121774 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =127
7675 13:31:57.121857
7676 13:31:57.121923
7677 13:31:57.121984 ==
7678 13:31:57.124990 Dram Type= 6, Freq= 0, CH_0, rank 0
7679 13:31:57.131246 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7680 13:31:57.131361 ==
7681 13:31:57.131462
7682 13:31:57.131545
7683 13:31:57.131626 TX Vref Scan disable
7684 13:31:57.134574 == TX Byte 0 ==
7685 13:31:57.138330 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7686 13:31:57.145043 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7687 13:31:57.145155 == TX Byte 1 ==
7688 13:31:57.148249 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7689 13:31:57.154772 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7690 13:31:57.154861 ==
7691 13:31:57.158019 Dram Type= 6, Freq= 0, CH_0, rank 0
7692 13:31:57.161470 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7693 13:31:57.161562 ==
7694 13:31:57.174147
7695 13:31:57.177462 TX Vref early break, caculate TX vref
7696 13:31:57.180841 TX Vref=16, minBit 0, minWin=22, winSum=365
7697 13:31:57.183938 TX Vref=18, minBit 0, minWin=23, winSum=376
7698 13:31:57.187566 TX Vref=20, minBit 0, minWin=23, winSum=387
7699 13:31:57.190760 TX Vref=22, minBit 4, minWin=24, winSum=398
7700 13:31:57.193888 TX Vref=24, minBit 0, minWin=24, winSum=405
7701 13:31:57.200811 TX Vref=26, minBit 3, minWin=25, winSum=414
7702 13:31:57.204045 TX Vref=28, minBit 4, minWin=25, winSum=413
7703 13:31:57.207316 TX Vref=30, minBit 0, minWin=25, winSum=406
7704 13:31:57.210390 TX Vref=32, minBit 8, minWin=23, winSum=399
7705 13:31:57.214133 TX Vref=34, minBit 9, minWin=23, winSum=390
7706 13:31:57.220291 [TxChooseVref] Worse bit 3, Min win 25, Win sum 414, Final Vref 26
7707 13:31:57.220407
7708 13:31:57.223808 Final TX Range 0 Vref 26
7709 13:31:57.223918
7710 13:31:57.224013 ==
7711 13:31:57.226888 Dram Type= 6, Freq= 0, CH_0, rank 0
7712 13:31:57.230557 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7713 13:31:57.230668 ==
7714 13:31:57.230763
7715 13:31:57.230852
7716 13:31:57.233457 TX Vref Scan disable
7717 13:31:57.240572 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7718 13:31:57.240687 == TX Byte 0 ==
7719 13:31:57.243760 u2DelayCellOfst[0]=15 cells (4 PI)
7720 13:31:57.246956 u2DelayCellOfst[1]=18 cells (5 PI)
7721 13:31:57.250469 u2DelayCellOfst[2]=11 cells (3 PI)
7722 13:31:57.253584 u2DelayCellOfst[3]=11 cells (3 PI)
7723 13:31:57.256859 u2DelayCellOfst[4]=7 cells (2 PI)
7724 13:31:57.260013 u2DelayCellOfst[5]=0 cells (0 PI)
7725 13:31:57.263365 u2DelayCellOfst[6]=18 cells (5 PI)
7726 13:31:57.266484 u2DelayCellOfst[7]=18 cells (5 PI)
7727 13:31:57.270237 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7728 13:31:57.273348 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7729 13:31:57.276741 == TX Byte 1 ==
7730 13:31:57.279951 u2DelayCellOfst[8]=0 cells (0 PI)
7731 13:31:57.280038 u2DelayCellOfst[9]=3 cells (1 PI)
7732 13:31:57.283142 u2DelayCellOfst[10]=7 cells (2 PI)
7733 13:31:57.286399 u2DelayCellOfst[11]=3 cells (1 PI)
7734 13:31:57.290324 u2DelayCellOfst[12]=15 cells (4 PI)
7735 13:31:57.293303 u2DelayCellOfst[13]=11 cells (3 PI)
7736 13:31:57.296698 u2DelayCellOfst[14]=18 cells (5 PI)
7737 13:31:57.299868 u2DelayCellOfst[15]=11 cells (3 PI)
7738 13:31:57.303048 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7739 13:31:57.309909 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7740 13:31:57.310002 DramC Write-DBI on
7741 13:31:57.310091 ==
7742 13:31:57.313144 Dram Type= 6, Freq= 0, CH_0, rank 0
7743 13:31:57.320059 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7744 13:31:57.320147 ==
7745 13:31:57.320235
7746 13:31:57.320317
7747 13:31:57.320398 TX Vref Scan disable
7748 13:31:57.323719 == TX Byte 0 ==
7749 13:31:57.326950 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7750 13:31:57.330040 == TX Byte 1 ==
7751 13:31:57.333748 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7752 13:31:57.336847 DramC Write-DBI off
7753 13:31:57.336933
7754 13:31:57.337036 [DATLAT]
7755 13:31:57.337137 Freq=1600, CH0 RK0
7756 13:31:57.337234
7757 13:31:57.339897 DATLAT Default: 0xf
7758 13:31:57.339983 0, 0xFFFF, sum = 0
7759 13:31:57.343458 1, 0xFFFF, sum = 0
7760 13:31:57.346729 2, 0xFFFF, sum = 0
7761 13:31:57.346835 3, 0xFFFF, sum = 0
7762 13:31:57.349938 4, 0xFFFF, sum = 0
7763 13:31:57.350025 5, 0xFFFF, sum = 0
7764 13:31:57.353640 6, 0xFFFF, sum = 0
7765 13:31:57.353727 7, 0xFFFF, sum = 0
7766 13:31:57.356697 8, 0xFFFF, sum = 0
7767 13:31:57.356797 9, 0xFFFF, sum = 0
7768 13:31:57.360259 10, 0xFFFF, sum = 0
7769 13:31:57.360347 11, 0xFFFF, sum = 0
7770 13:31:57.363394 12, 0xFFFF, sum = 0
7771 13:31:57.363481 13, 0xCFFF, sum = 0
7772 13:31:57.366680 14, 0x0, sum = 1
7773 13:31:57.366768 15, 0x0, sum = 2
7774 13:31:57.369940 16, 0x0, sum = 3
7775 13:31:57.370026 17, 0x0, sum = 4
7776 13:31:57.373161 best_step = 15
7777 13:31:57.373247
7778 13:31:57.373334 ==
7779 13:31:57.376963 Dram Type= 6, Freq= 0, CH_0, rank 0
7780 13:31:57.380060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7781 13:31:57.380147 ==
7782 13:31:57.383021 RX Vref Scan: 1
7783 13:31:57.383108
7784 13:31:57.383196 Set Vref Range= 24 -> 127
7785 13:31:57.383296
7786 13:31:57.386263 RX Vref 24 -> 127, step: 1
7787 13:31:57.386377
7788 13:31:57.389634 RX Delay 11 -> 252, step: 4
7789 13:31:57.389717
7790 13:31:57.393710 Set Vref, RX VrefLevel [Byte0]: 24
7791 13:31:57.396494 [Byte1]: 24
7792 13:31:57.396580
7793 13:31:57.399714 Set Vref, RX VrefLevel [Byte0]: 25
7794 13:31:57.402883 [Byte1]: 25
7795 13:31:57.406173
7796 13:31:57.406258 Set Vref, RX VrefLevel [Byte0]: 26
7797 13:31:57.409478 [Byte1]: 26
7798 13:31:57.413800
7799 13:31:57.413923 Set Vref, RX VrefLevel [Byte0]: 27
7800 13:31:57.417036 [Byte1]: 27
7801 13:31:57.421551
7802 13:31:57.421664 Set Vref, RX VrefLevel [Byte0]: 28
7803 13:31:57.424894 [Byte1]: 28
7804 13:31:57.429440
7805 13:31:57.429554 Set Vref, RX VrefLevel [Byte0]: 29
7806 13:31:57.432599 [Byte1]: 29
7807 13:31:57.437010
7808 13:31:57.437118 Set Vref, RX VrefLevel [Byte0]: 30
7809 13:31:57.440096 [Byte1]: 30
7810 13:31:57.444640
7811 13:31:57.444724 Set Vref, RX VrefLevel [Byte0]: 31
7812 13:31:57.447648 [Byte1]: 31
7813 13:31:57.451814
7814 13:31:57.451898 Set Vref, RX VrefLevel [Byte0]: 32
7815 13:31:57.455700 [Byte1]: 32
7816 13:31:57.459515
7817 13:31:57.459599 Set Vref, RX VrefLevel [Byte0]: 33
7818 13:31:57.463237 [Byte1]: 33
7819 13:31:57.467341
7820 13:31:57.467445 Set Vref, RX VrefLevel [Byte0]: 34
7821 13:31:57.470620 [Byte1]: 34
7822 13:31:57.475119
7823 13:31:57.475203 Set Vref, RX VrefLevel [Byte0]: 35
7824 13:31:57.478369 [Byte1]: 35
7825 13:31:57.482276
7826 13:31:57.482386 Set Vref, RX VrefLevel [Byte0]: 36
7827 13:31:57.485550 [Byte1]: 36
7828 13:31:57.489874
7829 13:31:57.489958 Set Vref, RX VrefLevel [Byte0]: 37
7830 13:31:57.493493 [Byte1]: 37
7831 13:31:57.498070
7832 13:31:57.498154 Set Vref, RX VrefLevel [Byte0]: 38
7833 13:31:57.501149 [Byte1]: 38
7834 13:31:57.505696
7835 13:31:57.505780 Set Vref, RX VrefLevel [Byte0]: 39
7836 13:31:57.508901 [Byte1]: 39
7837 13:31:57.512765
7838 13:31:57.512876 Set Vref, RX VrefLevel [Byte0]: 40
7839 13:31:57.515985 [Byte1]: 40
7840 13:31:57.520469
7841 13:31:57.520553 Set Vref, RX VrefLevel [Byte0]: 41
7842 13:31:57.523629 [Byte1]: 41
7843 13:31:57.528246
7844 13:31:57.528335 Set Vref, RX VrefLevel [Byte0]: 42
7845 13:31:57.531378 [Byte1]: 42
7846 13:31:57.535911
7847 13:31:57.535998 Set Vref, RX VrefLevel [Byte0]: 43
7848 13:31:57.539049 [Byte1]: 43
7849 13:31:57.543270
7850 13:31:57.543394 Set Vref, RX VrefLevel [Byte0]: 44
7851 13:31:57.550134 [Byte1]: 44
7852 13:31:57.550248
7853 13:31:57.553355 Set Vref, RX VrefLevel [Byte0]: 45
7854 13:31:57.556286 [Byte1]: 45
7855 13:31:57.556387
7856 13:31:57.559948 Set Vref, RX VrefLevel [Byte0]: 46
7857 13:31:57.563238 [Byte1]: 46
7858 13:31:57.563342
7859 13:31:57.566536 Set Vref, RX VrefLevel [Byte0]: 47
7860 13:31:57.569813 [Byte1]: 47
7861 13:31:57.573979
7862 13:31:57.574086 Set Vref, RX VrefLevel [Byte0]: 48
7863 13:31:57.577076 [Byte1]: 48
7864 13:31:57.581543
7865 13:31:57.581659 Set Vref, RX VrefLevel [Byte0]: 49
7866 13:31:57.584769 [Byte1]: 49
7867 13:31:57.589161
7868 13:31:57.589269 Set Vref, RX VrefLevel [Byte0]: 50
7869 13:31:57.592426 [Byte1]: 50
7870 13:31:57.596877
7871 13:31:57.596982 Set Vref, RX VrefLevel [Byte0]: 51
7872 13:31:57.599892 [Byte1]: 51
7873 13:31:57.604256
7874 13:31:57.604364 Set Vref, RX VrefLevel [Byte0]: 52
7875 13:31:57.607291 [Byte1]: 52
7876 13:31:57.611785
7877 13:31:57.611861 Set Vref, RX VrefLevel [Byte0]: 53
7878 13:31:57.615501 [Byte1]: 53
7879 13:31:57.619378
7880 13:31:57.619466 Set Vref, RX VrefLevel [Byte0]: 54
7881 13:31:57.622589 [Byte1]: 54
7882 13:31:57.626995
7883 13:31:57.627081 Set Vref, RX VrefLevel [Byte0]: 55
7884 13:31:57.630639 [Byte1]: 55
7885 13:31:57.635048
7886 13:31:57.635167 Set Vref, RX VrefLevel [Byte0]: 56
7887 13:31:57.638320 [Byte1]: 56
7888 13:31:57.642275
7889 13:31:57.642380 Set Vref, RX VrefLevel [Byte0]: 57
7890 13:31:57.645480 [Byte1]: 57
7891 13:31:57.649720
7892 13:31:57.649825 Set Vref, RX VrefLevel [Byte0]: 58
7893 13:31:57.653519 [Byte1]: 58
7894 13:31:57.657290
7895 13:31:57.657396 Set Vref, RX VrefLevel [Byte0]: 59
7896 13:31:57.660969 [Byte1]: 59
7897 13:31:57.665390
7898 13:31:57.665496 Set Vref, RX VrefLevel [Byte0]: 60
7899 13:31:57.668575 [Byte1]: 60
7900 13:31:57.673060
7901 13:31:57.673167 Set Vref, RX VrefLevel [Byte0]: 61
7902 13:31:57.676328 [Byte1]: 61
7903 13:31:57.680607
7904 13:31:57.680711 Set Vref, RX VrefLevel [Byte0]: 62
7905 13:31:57.683589 [Byte1]: 62
7906 13:31:57.688229
7907 13:31:57.688335 Set Vref, RX VrefLevel [Byte0]: 63
7908 13:31:57.691374 [Byte1]: 63
7909 13:31:57.695844
7910 13:31:57.695932 Set Vref, RX VrefLevel [Byte0]: 64
7911 13:31:57.699079 [Byte1]: 64
7912 13:31:57.703533
7913 13:31:57.703609 Set Vref, RX VrefLevel [Byte0]: 65
7914 13:31:57.706570 [Byte1]: 65
7915 13:31:57.710727
7916 13:31:57.710832 Set Vref, RX VrefLevel [Byte0]: 66
7917 13:31:57.714488 [Byte1]: 66
7918 13:31:57.718350
7919 13:31:57.718451 Set Vref, RX VrefLevel [Byte0]: 67
7920 13:31:57.721667 [Byte1]: 67
7921 13:31:57.726073
7922 13:31:57.726157 Set Vref, RX VrefLevel [Byte0]: 68
7923 13:31:57.729221 [Byte1]: 68
7924 13:31:57.733690
7925 13:31:57.733774 Set Vref, RX VrefLevel [Byte0]: 69
7926 13:31:57.737301 [Byte1]: 69
7927 13:31:57.741128
7928 13:31:57.741244 Set Vref, RX VrefLevel [Byte0]: 70
7929 13:31:57.747694 [Byte1]: 70
7930 13:31:57.747791
7931 13:31:57.750949 Set Vref, RX VrefLevel [Byte0]: 71
7932 13:31:57.754565 [Byte1]: 71
7933 13:31:57.754675
7934 13:31:57.757760 Set Vref, RX VrefLevel [Byte0]: 72
7935 13:31:57.761000 [Byte1]: 72
7936 13:31:57.761109
7937 13:31:57.764731 Set Vref, RX VrefLevel [Byte0]: 73
7938 13:31:57.768010 [Byte1]: 73
7939 13:31:57.771743
7940 13:31:57.771856 Set Vref, RX VrefLevel [Byte0]: 74
7941 13:31:57.774824 [Byte1]: 74
7942 13:31:57.779409
7943 13:31:57.779533 Set Vref, RX VrefLevel [Byte0]: 75
7944 13:31:57.782706 [Byte1]: 75
7945 13:31:57.787245
7946 13:31:57.787390 Set Vref, RX VrefLevel [Byte0]: 76
7947 13:31:57.790198 [Byte1]: 76
7948 13:31:57.794381
7949 13:31:57.794491 Set Vref, RX VrefLevel [Byte0]: 77
7950 13:31:57.797696 [Byte1]: 77
7951 13:31:57.802298
7952 13:31:57.802386 Final RX Vref Byte 0 = 63 to rank0
7953 13:31:57.805494 Final RX Vref Byte 1 = 60 to rank0
7954 13:31:57.808715 Final RX Vref Byte 0 = 63 to rank1
7955 13:31:57.811848 Final RX Vref Byte 1 = 60 to rank1==
7956 13:31:57.815596 Dram Type= 6, Freq= 0, CH_0, rank 0
7957 13:31:57.822118 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7958 13:31:57.822204 ==
7959 13:31:57.822271 DQS Delay:
7960 13:31:57.825203 DQS0 = 0, DQS1 = 0
7961 13:31:57.825286 DQM Delay:
7962 13:31:57.825352 DQM0 = 126, DQM1 = 119
7963 13:31:57.828430 DQ Delay:
7964 13:31:57.831776 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7965 13:31:57.835527 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7966 13:31:57.838610 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7967 13:31:57.841841 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
7968 13:31:57.841925
7969 13:31:57.841991
7970 13:31:57.842051
7971 13:31:57.845037 [DramC_TX_OE_Calibration] TA2
7972 13:31:57.848340 Original DQ_B0 (3 6) =30, OEN = 27
7973 13:31:57.851468 Original DQ_B1 (3 6) =30, OEN = 27
7974 13:31:57.855248 24, 0x0, End_B0=24 End_B1=24
7975 13:31:57.855360 25, 0x0, End_B0=25 End_B1=25
7976 13:31:57.858601 26, 0x0, End_B0=26 End_B1=26
7977 13:31:57.861641 27, 0x0, End_B0=27 End_B1=27
7978 13:31:57.864779 28, 0x0, End_B0=28 End_B1=28
7979 13:31:57.868507 29, 0x0, End_B0=29 End_B1=29
7980 13:31:57.868589 30, 0x0, End_B0=30 End_B1=30
7981 13:31:57.871634 31, 0x4141, End_B0=30 End_B1=30
7982 13:31:57.874862 Byte0 end_step=30 best_step=27
7983 13:31:57.878524 Byte1 end_step=30 best_step=27
7984 13:31:57.881677 Byte0 TX OE(2T, 0.5T) = (3, 3)
7985 13:31:57.884861 Byte1 TX OE(2T, 0.5T) = (3, 3)
7986 13:31:57.884970
7987 13:31:57.885069
7988 13:31:57.891447 [DQSOSCAuto] RK0, (LSB)MR18= 0x1111, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
7989 13:31:57.894675 CH0 RK0: MR19=303, MR18=1111
7990 13:31:57.901784 CH0_RK0: MR19=0x303, MR18=0x1111, DQSOSC=401, MR23=63, INC=22, DEC=15
7991 13:31:57.901869
7992 13:31:57.905032 ----->DramcWriteLeveling(PI) begin...
7993 13:31:57.905116 ==
7994 13:31:57.908294 Dram Type= 6, Freq= 0, CH_0, rank 1
7995 13:31:57.911596 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7996 13:31:57.911680 ==
7997 13:31:57.914750 Write leveling (Byte 0): 34 => 34
7998 13:31:57.917944 Write leveling (Byte 1): 28 => 28
7999 13:31:57.921085 DramcWriteLeveling(PI) end<-----
8000 13:31:57.921168
8001 13:31:57.921241 ==
8002 13:31:57.924833 Dram Type= 6, Freq= 0, CH_0, rank 1
8003 13:31:57.927852 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8004 13:31:57.927936 ==
8005 13:31:57.931310 [Gating] SW mode calibration
8006 13:31:57.938042 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8007 13:31:57.944715 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8008 13:31:57.947940 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 13:31:57.954358 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8010 13:31:57.957552 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8011 13:31:57.960781 1 4 12 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
8012 13:31:57.967783 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8013 13:31:57.970909 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
8014 13:31:57.974474 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8015 13:31:57.980950 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8016 13:31:57.984027 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8017 13:31:57.987806 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8018 13:31:57.994316 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8019 13:31:57.997553 1 5 12 | B1->B0 | 3434 2525 | 1 1 | (1 1) (1 0)
8020 13:31:58.000715 1 5 16 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
8021 13:31:58.007143 1 5 20 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8022 13:31:58.010799 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8023 13:31:58.014147 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8024 13:31:58.020839 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8025 13:31:58.024224 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8026 13:31:58.027641 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8027 13:31:58.034028 1 6 12 | B1->B0 | 2323 3f3f | 0 1 | (0 0) (0 0)
8028 13:31:58.038546 1 6 16 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
8029 13:31:58.040555 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8030 13:31:58.046761 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8031 13:31:58.050461 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8032 13:31:58.053573 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8033 13:31:58.056922 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8034 13:31:58.063458 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8035 13:31:58.066798 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8036 13:31:58.070201 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8037 13:31:58.076657 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8038 13:31:58.080475 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 13:31:58.083550 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 13:31:58.090039 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 13:31:58.093404 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 13:31:58.096838 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 13:31:58.103344 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 13:31:58.106690 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 13:31:58.109992 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 13:31:58.116513 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 13:31:58.119668 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 13:31:58.122930 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 13:31:58.129882 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 13:31:58.133251 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 13:31:58.136337 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8052 13:31:58.142909 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8053 13:31:58.146305 Total UI for P1: 0, mck2ui 16
8054 13:31:58.149483 best dqsien dly found for B0: ( 1, 9, 12)
8055 13:31:58.153219 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8056 13:31:58.156501 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8057 13:31:58.159550 Total UI for P1: 0, mck2ui 16
8058 13:31:58.162558 best dqsien dly found for B1: ( 1, 9, 18)
8059 13:31:58.166083 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8060 13:31:58.169233 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8061 13:31:58.172563
8062 13:31:58.175974 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8063 13:31:58.179359 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8064 13:31:58.182807 [Gating] SW calibration Done
8065 13:31:58.182889 ==
8066 13:31:58.186077 Dram Type= 6, Freq= 0, CH_0, rank 1
8067 13:31:58.189138 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8068 13:31:58.189249 ==
8069 13:31:58.189346 RX Vref Scan: 0
8070 13:31:58.192688
8071 13:31:58.192773 RX Vref 0 -> 0, step: 1
8072 13:31:58.192842
8073 13:31:58.195775 RX Delay 0 -> 252, step: 8
8074 13:31:58.198947 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8075 13:31:58.202303 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8076 13:31:58.208997 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8077 13:31:58.212385 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8078 13:31:58.215649 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8079 13:31:58.219038 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8080 13:31:58.222495 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8081 13:31:58.229195 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8082 13:31:58.232283 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8083 13:31:58.235315 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8084 13:31:58.238870 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8085 13:31:58.242287 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8086 13:31:58.248626 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8087 13:31:58.251900 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8088 13:31:58.255174 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8089 13:31:58.258970 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8090 13:31:58.259077 ==
8091 13:31:58.262099 Dram Type= 6, Freq= 0, CH_0, rank 1
8092 13:31:58.268561 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8093 13:31:58.268651 ==
8094 13:31:58.268729 DQS Delay:
8095 13:31:58.272278 DQS0 = 0, DQS1 = 0
8096 13:31:58.272382 DQM Delay:
8097 13:31:58.275430 DQM0 = 128, DQM1 = 122
8098 13:31:58.275508 DQ Delay:
8099 13:31:58.278487 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8100 13:31:58.281691 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8101 13:31:58.285015 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8102 13:31:58.288329 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8103 13:31:58.288410
8104 13:31:58.288476
8105 13:31:58.288536 ==
8106 13:31:58.291606 Dram Type= 6, Freq= 0, CH_0, rank 1
8107 13:31:58.298610 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8108 13:31:58.298688 ==
8109 13:31:58.298753
8110 13:31:58.298840
8111 13:31:58.298900 TX Vref Scan disable
8112 13:31:58.301619 == TX Byte 0 ==
8113 13:31:58.305103 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8114 13:31:58.311588 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8115 13:31:58.311679 == TX Byte 1 ==
8116 13:31:58.314982 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8117 13:31:58.321532 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8118 13:31:58.321642 ==
8119 13:31:58.324882 Dram Type= 6, Freq= 0, CH_0, rank 1
8120 13:31:58.328261 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8121 13:31:58.328348 ==
8122 13:31:58.342408
8123 13:31:58.345669 TX Vref early break, caculate TX vref
8124 13:31:58.349328 TX Vref=16, minBit 0, minWin=22, winSum=369
8125 13:31:58.352216 TX Vref=18, minBit 8, minWin=22, winSum=377
8126 13:31:58.355451 TX Vref=20, minBit 0, minWin=22, winSum=378
8127 13:31:58.358868 TX Vref=22, minBit 0, minWin=24, winSum=390
8128 13:31:58.361987 TX Vref=24, minBit 0, minWin=24, winSum=399
8129 13:31:58.368793 TX Vref=26, minBit 8, minWin=24, winSum=405
8130 13:31:58.372108 TX Vref=28, minBit 8, minWin=24, winSum=405
8131 13:31:58.375253 TX Vref=30, minBit 8, minWin=24, winSum=406
8132 13:31:58.378523 TX Vref=32, minBit 9, minWin=23, winSum=391
8133 13:31:58.382227 TX Vref=34, minBit 8, minWin=22, winSum=387
8134 13:31:58.385387 TX Vref=36, minBit 8, minWin=22, winSum=380
8135 13:31:58.391846 [TxChooseVref] Worse bit 8, Min win 24, Win sum 406, Final Vref 30
8136 13:31:58.391964
8137 13:31:58.395031 Final TX Range 0 Vref 30
8138 13:31:58.395137
8139 13:31:58.395229 ==
8140 13:31:58.398549 Dram Type= 6, Freq= 0, CH_0, rank 1
8141 13:31:58.401912 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8142 13:31:58.402022 ==
8143 13:31:58.402117
8144 13:31:58.405166
8145 13:31:58.405282 TX Vref Scan disable
8146 13:31:58.412095 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8147 13:31:58.412223 == TX Byte 0 ==
8148 13:31:58.415041 u2DelayCellOfst[0]=15 cells (4 PI)
8149 13:31:58.418540 u2DelayCellOfst[1]=18 cells (5 PI)
8150 13:31:58.421731 u2DelayCellOfst[2]=11 cells (3 PI)
8151 13:31:58.424978 u2DelayCellOfst[3]=11 cells (3 PI)
8152 13:31:58.428289 u2DelayCellOfst[4]=7 cells (2 PI)
8153 13:31:58.431580 u2DelayCellOfst[5]=0 cells (0 PI)
8154 13:31:58.434847 u2DelayCellOfst[6]=18 cells (5 PI)
8155 13:31:58.438081 u2DelayCellOfst[7]=18 cells (5 PI)
8156 13:31:58.441501 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8157 13:31:58.444830 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8158 13:31:58.448122 == TX Byte 1 ==
8159 13:31:58.451492 u2DelayCellOfst[8]=0 cells (0 PI)
8160 13:31:58.454748 u2DelayCellOfst[9]=3 cells (1 PI)
8161 13:31:58.458006 u2DelayCellOfst[10]=11 cells (3 PI)
8162 13:31:58.461210 u2DelayCellOfst[11]=7 cells (2 PI)
8163 13:31:58.465004 u2DelayCellOfst[12]=15 cells (4 PI)
8164 13:31:58.465110 u2DelayCellOfst[13]=15 cells (4 PI)
8165 13:31:58.467806 u2DelayCellOfst[14]=18 cells (5 PI)
8166 13:31:58.471237 u2DelayCellOfst[15]=11 cells (3 PI)
8167 13:31:58.477979 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8168 13:31:58.481199 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8169 13:31:58.481308 DramC Write-DBI on
8170 13:31:58.484676 ==
8171 13:31:58.488067 Dram Type= 6, Freq= 0, CH_0, rank 1
8172 13:31:58.491391 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8173 13:31:58.491475 ==
8174 13:31:58.491540
8175 13:31:58.491601
8176 13:31:58.494530 TX Vref Scan disable
8177 13:31:58.494603 == TX Byte 0 ==
8178 13:31:58.500879 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8179 13:31:58.501016 == TX Byte 1 ==
8180 13:31:58.504267 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8181 13:31:58.507526 DramC Write-DBI off
8182 13:31:58.507603
8183 13:31:58.507676 [DATLAT]
8184 13:31:58.510972 Freq=1600, CH0 RK1
8185 13:31:58.511093
8186 13:31:58.511189 DATLAT Default: 0xf
8187 13:31:58.514405 0, 0xFFFF, sum = 0
8188 13:31:58.514511 1, 0xFFFF, sum = 0
8189 13:31:58.517761 2, 0xFFFF, sum = 0
8190 13:31:58.517876 3, 0xFFFF, sum = 0
8191 13:31:58.521073 4, 0xFFFF, sum = 0
8192 13:31:58.521205 5, 0xFFFF, sum = 0
8193 13:31:58.524794 6, 0xFFFF, sum = 0
8194 13:31:58.527707 7, 0xFFFF, sum = 0
8195 13:31:58.527797 8, 0xFFFF, sum = 0
8196 13:31:58.531330 9, 0xFFFF, sum = 0
8197 13:31:58.531441 10, 0xFFFF, sum = 0
8198 13:31:58.534504 11, 0xFFFF, sum = 0
8199 13:31:58.534610 12, 0xFFFF, sum = 0
8200 13:31:58.537825 13, 0xCFFF, sum = 0
8201 13:31:58.537937 14, 0x0, sum = 1
8202 13:31:58.541132 15, 0x0, sum = 2
8203 13:31:58.541216 16, 0x0, sum = 3
8204 13:31:58.544466 17, 0x0, sum = 4
8205 13:31:58.544550 best_step = 15
8206 13:31:58.544620
8207 13:31:58.544682 ==
8208 13:31:58.547837 Dram Type= 6, Freq= 0, CH_0, rank 1
8209 13:31:58.551110 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8210 13:31:58.551192 ==
8211 13:31:58.554457 RX Vref Scan: 0
8212 13:31:58.554540
8213 13:31:58.557700 RX Vref 0 -> 0, step: 1
8214 13:31:58.557782
8215 13:31:58.557847 RX Delay 3 -> 252, step: 4
8216 13:31:58.564453 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8217 13:31:58.567785 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8218 13:31:58.571082 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8219 13:31:58.574376 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8220 13:31:58.577788 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8221 13:31:58.584718 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8222 13:31:58.587658 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8223 13:31:58.591227 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8224 13:31:58.594074 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8225 13:31:58.597824 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8226 13:31:58.604707 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8227 13:31:58.607887 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8228 13:31:58.611127 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8229 13:31:58.614297 iDelay=191, Bit 13, Center 124 (67 ~ 182) 116
8230 13:31:58.620999 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8231 13:31:58.624437 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8232 13:31:58.624519 ==
8233 13:31:58.627953 Dram Type= 6, Freq= 0, CH_0, rank 1
8234 13:31:58.631070 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8235 13:31:58.631167 ==
8236 13:31:58.634326 DQS Delay:
8237 13:31:58.634446 DQS0 = 0, DQS1 = 0
8238 13:31:58.634539 DQM Delay:
8239 13:31:58.637332 DQM0 = 124, DQM1 = 118
8240 13:31:58.637441 DQ Delay:
8241 13:31:58.640879 DQ0 =124, DQ1 =124, DQ2 =122, DQ3 =122
8242 13:31:58.644174 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8243 13:31:58.647490 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
8244 13:31:58.654121 DQ12 =124, DQ13 =124, DQ14 =128, DQ15 =124
8245 13:31:58.654230
8246 13:31:58.654337
8247 13:31:58.654421
8248 13:31:58.657478 [DramC_TX_OE_Calibration] TA2
8249 13:31:58.657596 Original DQ_B0 (3 6) =30, OEN = 27
8250 13:31:58.660767 Original DQ_B1 (3 6) =30, OEN = 27
8251 13:31:58.664231 24, 0x0, End_B0=24 End_B1=24
8252 13:31:58.667647 25, 0x0, End_B0=25 End_B1=25
8253 13:31:58.670907 26, 0x0, End_B0=26 End_B1=26
8254 13:31:58.674202 27, 0x0, End_B0=27 End_B1=27
8255 13:31:58.674315 28, 0x0, End_B0=28 End_B1=28
8256 13:31:58.677358 29, 0x0, End_B0=29 End_B1=29
8257 13:31:58.680675 30, 0x0, End_B0=30 End_B1=30
8258 13:31:58.683986 31, 0x4141, End_B0=30 End_B1=30
8259 13:31:58.687267 Byte0 end_step=30 best_step=27
8260 13:31:58.687379 Byte1 end_step=30 best_step=27
8261 13:31:58.690677 Byte0 TX OE(2T, 0.5T) = (3, 3)
8262 13:31:58.693829 Byte1 TX OE(2T, 0.5T) = (3, 3)
8263 13:31:58.693905
8264 13:31:58.693978
8265 13:31:58.703965 [DQSOSCAuto] RK1, (LSB)MR18= 0x2512, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
8266 13:31:58.704056 CH0 RK1: MR19=303, MR18=2512
8267 13:31:58.710564 CH0_RK1: MR19=0x303, MR18=0x2512, DQSOSC=391, MR23=63, INC=24, DEC=16
8268 13:31:58.713984 [RxdqsGatingPostProcess] freq 1600
8269 13:31:58.720245 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8270 13:31:58.723803 best DQS0 dly(2T, 0.5T) = (1, 1)
8271 13:31:58.727235 best DQS1 dly(2T, 0.5T) = (1, 1)
8272 13:31:58.730470 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8273 13:31:58.733827 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8274 13:31:58.736952 best DQS0 dly(2T, 0.5T) = (1, 1)
8275 13:31:58.737040 best DQS1 dly(2T, 0.5T) = (1, 1)
8276 13:31:58.740237 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8277 13:31:58.743745 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8278 13:31:58.746882 Pre-setting of DQS Precalculation
8279 13:31:58.753734 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8280 13:31:58.753858 ==
8281 13:31:58.756652 Dram Type= 6, Freq= 0, CH_1, rank 0
8282 13:31:58.759910 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8283 13:31:58.760011 ==
8284 13:31:58.766627 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8285 13:31:58.769936 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8286 13:31:58.773283 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8287 13:31:58.779823 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8288 13:31:58.789014 [CA 0] Center 41 (12~70) winsize 59
8289 13:31:58.792254 [CA 1] Center 42 (12~72) winsize 61
8290 13:31:58.795683 [CA 2] Center 37 (8~66) winsize 59
8291 13:31:58.798946 [CA 3] Center 37 (8~66) winsize 59
8292 13:31:58.802140 [CA 4] Center 37 (8~67) winsize 60
8293 13:31:58.805334 [CA 5] Center 36 (7~66) winsize 60
8294 13:31:58.805416
8295 13:31:58.809042 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8296 13:31:58.809124
8297 13:31:58.812343 [CATrainingPosCal] consider 1 rank data
8298 13:31:58.815551 u2DelayCellTimex100 = 258/100 ps
8299 13:31:58.822097 CA0 delay=41 (12~70),Diff = 5 PI (18 cell)
8300 13:31:58.825628 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8301 13:31:58.828842 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8302 13:31:58.832138 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8303 13:31:58.835299 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8304 13:31:58.839042 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8305 13:31:58.839153
8306 13:31:58.842031 CA PerBit enable=1, Macro0, CA PI delay=36
8307 13:31:58.842112
8308 13:31:58.845148 [CBTSetCACLKResult] CA Dly = 36
8309 13:31:58.848709 CS Dly: 9 (0~40)
8310 13:31:58.851873 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8311 13:31:58.855567 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8312 13:31:58.855640 ==
8313 13:31:58.858509 Dram Type= 6, Freq= 0, CH_1, rank 1
8314 13:31:58.862221 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8315 13:31:58.865139 ==
8316 13:31:58.868288 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8317 13:31:58.871585 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8318 13:31:58.878183 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8319 13:31:58.881450 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8320 13:31:58.891994 [CA 0] Center 42 (13~71) winsize 59
8321 13:31:58.895523 [CA 1] Center 41 (11~72) winsize 62
8322 13:31:58.898740 [CA 2] Center 37 (8~67) winsize 60
8323 13:31:58.902102 [CA 3] Center 36 (7~66) winsize 60
8324 13:31:58.905398 [CA 4] Center 37 (8~67) winsize 60
8325 13:31:58.908750 [CA 5] Center 36 (6~66) winsize 61
8326 13:31:58.908836
8327 13:31:58.911880 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8328 13:31:58.911962
8329 13:31:58.915470 [CATrainingPosCal] consider 2 rank data
8330 13:31:58.918522 u2DelayCellTimex100 = 258/100 ps
8331 13:31:58.921811 CA0 delay=41 (13~70),Diff = 5 PI (18 cell)
8332 13:31:58.928510 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8333 13:31:58.931885 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8334 13:31:58.935181 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8335 13:31:58.938489 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8336 13:31:58.941919 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8337 13:31:58.942001
8338 13:31:58.944863 CA PerBit enable=1, Macro0, CA PI delay=36
8339 13:31:58.944944
8340 13:31:58.948103 [CBTSetCACLKResult] CA Dly = 36
8341 13:31:58.951350 CS Dly: 10 (0~43)
8342 13:31:58.955015 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8343 13:31:58.958296 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8344 13:31:58.958378
8345 13:31:58.961600 ----->DramcWriteLeveling(PI) begin...
8346 13:31:58.961684 ==
8347 13:31:58.964895 Dram Type= 6, Freq= 0, CH_1, rank 0
8348 13:31:58.971506 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8349 13:31:58.971595 ==
8350 13:31:58.974790 Write leveling (Byte 0): 25 => 25
8351 13:31:58.974862 Write leveling (Byte 1): 27 => 27
8352 13:31:58.977943 DramcWriteLeveling(PI) end<-----
8353 13:31:58.978026
8354 13:31:58.981102 ==
8355 13:31:58.984663 Dram Type= 6, Freq= 0, CH_1, rank 0
8356 13:31:58.987703 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8357 13:31:58.987791 ==
8358 13:31:58.991283 [Gating] SW mode calibration
8359 13:31:58.997785 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8360 13:31:59.001041 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8361 13:31:59.007752 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 13:31:59.011206 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 13:31:59.014511 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 13:31:59.021145 1 4 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8365 13:31:59.024101 1 4 16 | B1->B0 | 3434 3333 | 0 0 | (0 0) (0 0)
8366 13:31:59.027526 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 13:31:59.033933 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 13:31:59.037332 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 13:31:59.040623 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 13:31:59.047165 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 13:31:59.050918 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 13:31:59.054206 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8373 13:31:59.060438 1 5 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
8374 13:31:59.063763 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8375 13:31:59.067060 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 13:31:59.073715 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 13:31:59.077532 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 13:31:59.080279 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 13:31:59.087039 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 13:31:59.090423 1 6 12 | B1->B0 | 2727 2625 | 0 1 | (0 0) (1 1)
8381 13:31:59.093509 1 6 16 | B1->B0 | 4242 4444 | 0 0 | (0 0) (0 0)
8382 13:31:59.100732 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 13:31:59.104100 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 13:31:59.107115 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 13:31:59.113677 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 13:31:59.116887 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 13:31:59.120248 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 13:31:59.126906 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8389 13:31:59.130195 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8390 13:31:59.133293 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8391 13:31:59.140096 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 13:31:59.143532 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 13:31:59.146941 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 13:31:59.153580 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 13:31:59.156717 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 13:31:59.160116 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 13:31:59.166426 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 13:31:59.169620 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 13:31:59.172903 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 13:31:59.180059 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 13:31:59.183327 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 13:31:59.186525 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 13:31:59.189780 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 13:31:59.196363 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8405 13:31:59.199653 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8406 13:31:59.202808 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 13:31:59.206148 Total UI for P1: 0, mck2ui 16
8408 13:31:59.209434 best dqsien dly found for B0: ( 1, 9, 16)
8409 13:31:59.212813 Total UI for P1: 0, mck2ui 16
8410 13:31:59.216086 best dqsien dly found for B1: ( 1, 9, 14)
8411 13:31:59.219894 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8412 13:31:59.222911 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8413 13:31:59.226027
8414 13:31:59.229758 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8415 13:31:59.233110 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8416 13:31:59.235784 [Gating] SW calibration Done
8417 13:31:59.235893 ==
8418 13:31:59.239689 Dram Type= 6, Freq= 0, CH_1, rank 0
8419 13:31:59.242790 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8420 13:31:59.242863 ==
8421 13:31:59.245910 RX Vref Scan: 0
8422 13:31:59.245992
8423 13:31:59.246057 RX Vref 0 -> 0, step: 1
8424 13:31:59.246119
8425 13:31:59.249091 RX Delay 0 -> 252, step: 8
8426 13:31:59.252521 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8427 13:31:59.255834 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8428 13:31:59.262501 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8429 13:31:59.265555 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8430 13:31:59.269363 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8431 13:31:59.272481 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8432 13:31:59.275524 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8433 13:31:59.282675 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8434 13:31:59.285928 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8435 13:31:59.289097 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8436 13:31:59.292395 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8437 13:31:59.295833 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8438 13:31:59.302328 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8439 13:31:59.305533 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8440 13:31:59.308776 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8441 13:31:59.312193 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8442 13:31:59.312280 ==
8443 13:31:59.315543 Dram Type= 6, Freq= 0, CH_1, rank 0
8444 13:31:59.322248 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8445 13:31:59.322331 ==
8446 13:31:59.322397 DQS Delay:
8447 13:31:59.325561 DQS0 = 0, DQS1 = 0
8448 13:31:59.325643 DQM Delay:
8449 13:31:59.328696 DQM0 = 132, DQM1 = 126
8450 13:31:59.328778 DQ Delay:
8451 13:31:59.331978 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8452 13:31:59.335181 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8453 13:31:59.338960 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8454 13:31:59.342064 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8455 13:31:59.342171
8456 13:31:59.342265
8457 13:31:59.342356 ==
8458 13:31:59.345360 Dram Type= 6, Freq= 0, CH_1, rank 0
8459 13:31:59.351801 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8460 13:31:59.351877 ==
8461 13:31:59.351938
8462 13:31:59.351996
8463 13:31:59.352052 TX Vref Scan disable
8464 13:31:59.355357 == TX Byte 0 ==
8465 13:31:59.358804 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8466 13:31:59.365450 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8467 13:31:59.365563 == TX Byte 1 ==
8468 13:31:59.368524 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8469 13:31:59.375386 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8470 13:31:59.375473 ==
8471 13:31:59.378629 Dram Type= 6, Freq= 0, CH_1, rank 0
8472 13:31:59.381534 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8473 13:31:59.381638 ==
8474 13:31:59.395330
8475 13:31:59.398607 TX Vref early break, caculate TX vref
8476 13:31:59.401905 TX Vref=16, minBit 1, minWin=22, winSum=366
8477 13:31:59.405101 TX Vref=18, minBit 10, minWin=22, winSum=376
8478 13:31:59.408326 TX Vref=20, minBit 5, minWin=23, winSum=386
8479 13:31:59.411504 TX Vref=22, minBit 12, minWin=23, winSum=395
8480 13:31:59.414766 TX Vref=24, minBit 5, minWin=24, winSum=406
8481 13:31:59.421433 TX Vref=26, minBit 1, minWin=25, winSum=414
8482 13:31:59.424741 TX Vref=28, minBit 1, minWin=25, winSum=421
8483 13:31:59.428095 TX Vref=30, minBit 0, minWin=25, winSum=417
8484 13:31:59.431340 TX Vref=32, minBit 0, minWin=24, winSum=408
8485 13:31:59.435215 TX Vref=34, minBit 1, minWin=23, winSum=405
8486 13:31:59.438582 TX Vref=36, minBit 0, minWin=23, winSum=386
8487 13:31:59.444925 [TxChooseVref] Worse bit 1, Min win 25, Win sum 421, Final Vref 28
8488 13:31:59.445003
8489 13:31:59.448168 Final TX Range 0 Vref 28
8490 13:31:59.448250
8491 13:31:59.448313 ==
8492 13:31:59.451840 Dram Type= 6, Freq= 0, CH_1, rank 0
8493 13:31:59.454813 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8494 13:31:59.454888 ==
8495 13:31:59.458281
8496 13:31:59.458355
8497 13:31:59.458417 TX Vref Scan disable
8498 13:31:59.464688 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8499 13:31:59.464772 == TX Byte 0 ==
8500 13:31:59.467841 u2DelayCellOfst[0]=18 cells (5 PI)
8501 13:31:59.471213 u2DelayCellOfst[1]=15 cells (4 PI)
8502 13:31:59.474379 u2DelayCellOfst[2]=0 cells (0 PI)
8503 13:31:59.478202 u2DelayCellOfst[3]=7 cells (2 PI)
8504 13:31:59.481423 u2DelayCellOfst[4]=11 cells (3 PI)
8505 13:31:59.484639 u2DelayCellOfst[5]=22 cells (6 PI)
8506 13:31:59.487764 u2DelayCellOfst[6]=18 cells (5 PI)
8507 13:31:59.491552 u2DelayCellOfst[7]=7 cells (2 PI)
8508 13:31:59.494768 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8509 13:31:59.498098 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8510 13:31:59.500824 == TX Byte 1 ==
8511 13:31:59.504136 u2DelayCellOfst[8]=0 cells (0 PI)
8512 13:31:59.507988 u2DelayCellOfst[9]=3 cells (1 PI)
8513 13:31:59.511137 u2DelayCellOfst[10]=11 cells (3 PI)
8514 13:31:59.514223 u2DelayCellOfst[11]=7 cells (2 PI)
8515 13:31:59.517479 u2DelayCellOfst[12]=15 cells (4 PI)
8516 13:31:59.517565 u2DelayCellOfst[13]=18 cells (5 PI)
8517 13:31:59.520653 u2DelayCellOfst[14]=18 cells (5 PI)
8518 13:31:59.524541 u2DelayCellOfst[15]=18 cells (5 PI)
8519 13:31:59.531182 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8520 13:31:59.534391 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8521 13:31:59.534497 DramC Write-DBI on
8522 13:31:59.537624 ==
8523 13:31:59.540884 Dram Type= 6, Freq= 0, CH_1, rank 0
8524 13:31:59.544182 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8525 13:31:59.544266 ==
8526 13:31:59.544333
8527 13:31:59.544401
8528 13:31:59.547380 TX Vref Scan disable
8529 13:31:59.547452 == TX Byte 0 ==
8530 13:31:59.553854 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8531 13:31:59.553963 == TX Byte 1 ==
8532 13:31:59.557153 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8533 13:31:59.560966 DramC Write-DBI off
8534 13:31:59.561050
8535 13:31:59.561122 [DATLAT]
8536 13:31:59.564205 Freq=1600, CH1 RK0
8537 13:31:59.564289
8538 13:31:59.564355 DATLAT Default: 0xf
8539 13:31:59.567354 0, 0xFFFF, sum = 0
8540 13:31:59.567476 1, 0xFFFF, sum = 0
8541 13:31:59.570878 2, 0xFFFF, sum = 0
8542 13:31:59.570961 3, 0xFFFF, sum = 0
8543 13:31:59.574218 4, 0xFFFF, sum = 0
8544 13:31:59.574307 5, 0xFFFF, sum = 0
8545 13:31:59.577122 6, 0xFFFF, sum = 0
8546 13:31:59.577203 7, 0xFFFF, sum = 0
8547 13:31:59.580491 8, 0xFFFF, sum = 0
8548 13:31:59.583799 9, 0xFFFF, sum = 0
8549 13:31:59.583885 10, 0xFFFF, sum = 0
8550 13:31:59.587468 11, 0xFFFF, sum = 0
8551 13:31:59.587553 12, 0xFFFF, sum = 0
8552 13:31:59.590372 13, 0x8FFF, sum = 0
8553 13:31:59.590455 14, 0x0, sum = 1
8554 13:31:59.593928 15, 0x0, sum = 2
8555 13:31:59.594018 16, 0x0, sum = 3
8556 13:31:59.597361 17, 0x0, sum = 4
8557 13:31:59.597447 best_step = 15
8558 13:31:59.597512
8559 13:31:59.597573 ==
8560 13:31:59.600371 Dram Type= 6, Freq= 0, CH_1, rank 0
8561 13:31:59.603773 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8562 13:31:59.603881 ==
8563 13:31:59.606851 RX Vref Scan: 1
8564 13:31:59.606935
8565 13:31:59.610195 Set Vref Range= 24 -> 127
8566 13:31:59.610278
8567 13:31:59.610343 RX Vref 24 -> 127, step: 1
8568 13:31:59.610403
8569 13:31:59.613984 RX Delay 11 -> 252, step: 4
8570 13:31:59.614067
8571 13:31:59.617198 Set Vref, RX VrefLevel [Byte0]: 24
8572 13:31:59.620476 [Byte1]: 24
8573 13:31:59.623748
8574 13:31:59.627093 Set Vref, RX VrefLevel [Byte0]: 25
8575 13:31:59.627175 [Byte1]: 25
8576 13:31:59.631754
8577 13:31:59.631843 Set Vref, RX VrefLevel [Byte0]: 26
8578 13:31:59.634484 [Byte1]: 26
8579 13:31:59.639209
8580 13:31:59.639293 Set Vref, RX VrefLevel [Byte0]: 27
8581 13:31:59.642518 [Byte1]: 27
8582 13:31:59.646536
8583 13:31:59.646642 Set Vref, RX VrefLevel [Byte0]: 28
8584 13:31:59.649827 [Byte1]: 28
8585 13:31:59.654566
8586 13:31:59.654661 Set Vref, RX VrefLevel [Byte0]: 29
8587 13:31:59.657752 [Byte1]: 29
8588 13:31:59.661729
8589 13:31:59.661809 Set Vref, RX VrefLevel [Byte0]: 30
8590 13:31:59.665251 [Byte1]: 30
8591 13:31:59.669706
8592 13:31:59.669795 Set Vref, RX VrefLevel [Byte0]: 31
8593 13:31:59.673020 [Byte1]: 31
8594 13:31:59.677031
8595 13:31:59.677139 Set Vref, RX VrefLevel [Byte0]: 32
8596 13:31:59.680155 [Byte1]: 32
8597 13:31:59.684416
8598 13:31:59.684529 Set Vref, RX VrefLevel [Byte0]: 33
8599 13:31:59.687791 [Byte1]: 33
8600 13:31:59.692653
8601 13:31:59.692744 Set Vref, RX VrefLevel [Byte0]: 34
8602 13:31:59.695662 [Byte1]: 34
8603 13:31:59.699902
8604 13:31:59.699991 Set Vref, RX VrefLevel [Byte0]: 35
8605 13:31:59.703072 [Byte1]: 35
8606 13:31:59.707838
8607 13:31:59.707924 Set Vref, RX VrefLevel [Byte0]: 36
8608 13:31:59.710859 [Byte1]: 36
8609 13:31:59.715267
8610 13:31:59.715382 Set Vref, RX VrefLevel [Byte0]: 37
8611 13:31:59.718695 [Byte1]: 37
8612 13:31:59.722721
8613 13:31:59.722818 Set Vref, RX VrefLevel [Byte0]: 38
8614 13:31:59.726015 [Byte1]: 38
8615 13:31:59.730365
8616 13:31:59.730480 Set Vref, RX VrefLevel [Byte0]: 39
8617 13:31:59.734032 [Byte1]: 39
8618 13:31:59.737939
8619 13:31:59.738045 Set Vref, RX VrefLevel [Byte0]: 40
8620 13:31:59.741275 [Byte1]: 40
8621 13:31:59.745782
8622 13:31:59.745881 Set Vref, RX VrefLevel [Byte0]: 41
8623 13:31:59.749203 [Byte1]: 41
8624 13:31:59.753097
8625 13:31:59.753200 Set Vref, RX VrefLevel [Byte0]: 42
8626 13:31:59.756462 [Byte1]: 42
8627 13:31:59.761062
8628 13:31:59.761141 Set Vref, RX VrefLevel [Byte0]: 43
8629 13:31:59.764307 [Byte1]: 43
8630 13:31:59.768381
8631 13:31:59.768493 Set Vref, RX VrefLevel [Byte0]: 44
8632 13:31:59.771649 [Byte1]: 44
8633 13:31:59.775747
8634 13:31:59.775825 Set Vref, RX VrefLevel [Byte0]: 45
8635 13:31:59.779064 [Byte1]: 45
8636 13:31:59.783757
8637 13:31:59.783859 Set Vref, RX VrefLevel [Byte0]: 46
8638 13:31:59.786993 [Byte1]: 46
8639 13:31:59.791438
8640 13:31:59.791564 Set Vref, RX VrefLevel [Byte0]: 47
8641 13:31:59.794625 [Byte1]: 47
8642 13:31:59.798869
8643 13:31:59.798950 Set Vref, RX VrefLevel [Byte0]: 48
8644 13:31:59.802092 [Byte1]: 48
8645 13:31:59.806649
8646 13:31:59.806732 Set Vref, RX VrefLevel [Byte0]: 49
8647 13:31:59.809908 [Byte1]: 49
8648 13:31:59.814376
8649 13:31:59.814469 Set Vref, RX VrefLevel [Byte0]: 50
8650 13:31:59.817758 [Byte1]: 50
8651 13:31:59.821732
8652 13:31:59.821817 Set Vref, RX VrefLevel [Byte0]: 51
8653 13:31:59.824786 [Byte1]: 51
8654 13:31:59.829471
8655 13:31:59.829584 Set Vref, RX VrefLevel [Byte0]: 52
8656 13:31:59.832426 [Byte1]: 52
8657 13:31:59.836893
8658 13:31:59.836988 Set Vref, RX VrefLevel [Byte0]: 53
8659 13:31:59.840482 [Byte1]: 53
8660 13:31:59.844329
8661 13:31:59.844406 Set Vref, RX VrefLevel [Byte0]: 54
8662 13:31:59.847653 [Byte1]: 54
8663 13:31:59.852043
8664 13:31:59.852122 Set Vref, RX VrefLevel [Byte0]: 55
8665 13:31:59.855644 [Byte1]: 55
8666 13:31:59.859624
8667 13:31:59.859711 Set Vref, RX VrefLevel [Byte0]: 56
8668 13:31:59.862941 [Byte1]: 56
8669 13:31:59.867477
8670 13:31:59.867563 Set Vref, RX VrefLevel [Byte0]: 57
8671 13:31:59.870901 [Byte1]: 57
8672 13:31:59.874871
8673 13:31:59.874978 Set Vref, RX VrefLevel [Byte0]: 58
8674 13:31:59.878051 [Byte1]: 58
8675 13:31:59.882833
8676 13:31:59.882945 Set Vref, RX VrefLevel [Byte0]: 59
8677 13:31:59.886144 [Byte1]: 59
8678 13:31:59.890076
8679 13:31:59.890185 Set Vref, RX VrefLevel [Byte0]: 60
8680 13:31:59.893219 [Byte1]: 60
8681 13:31:59.897795
8682 13:31:59.897903 Set Vref, RX VrefLevel [Byte0]: 61
8683 13:31:59.901187 [Byte1]: 61
8684 13:31:59.905704
8685 13:31:59.905818 Set Vref, RX VrefLevel [Byte0]: 62
8686 13:31:59.908871 [Byte1]: 62
8687 13:31:59.912762
8688 13:31:59.912848 Set Vref, RX VrefLevel [Byte0]: 63
8689 13:31:59.916669 [Byte1]: 63
8690 13:31:59.920508
8691 13:31:59.920599 Set Vref, RX VrefLevel [Byte0]: 64
8692 13:31:59.923869 [Byte1]: 64
8693 13:31:59.928559
8694 13:31:59.928647 Set Vref, RX VrefLevel [Byte0]: 65
8695 13:31:59.931904 [Byte1]: 65
8696 13:31:59.935991
8697 13:31:59.936072 Set Vref, RX VrefLevel [Byte0]: 66
8698 13:31:59.939610 [Byte1]: 66
8699 13:31:59.943189
8700 13:31:59.943308 Set Vref, RX VrefLevel [Byte0]: 67
8701 13:31:59.947258 [Byte1]: 67
8702 13:31:59.951087
8703 13:31:59.951198 Set Vref, RX VrefLevel [Byte0]: 68
8704 13:31:59.954777 [Byte1]: 68
8705 13:31:59.958445
8706 13:31:59.958549 Set Vref, RX VrefLevel [Byte0]: 69
8707 13:31:59.961806 [Byte1]: 69
8708 13:31:59.966152
8709 13:31:59.966256 Final RX Vref Byte 0 = 57 to rank0
8710 13:31:59.969535 Final RX Vref Byte 1 = 53 to rank0
8711 13:31:59.972812 Final RX Vref Byte 0 = 57 to rank1
8712 13:31:59.976156 Final RX Vref Byte 1 = 53 to rank1==
8713 13:31:59.979538 Dram Type= 6, Freq= 0, CH_1, rank 0
8714 13:31:59.986245 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8715 13:31:59.986352 ==
8716 13:31:59.986446 DQS Delay:
8717 13:31:59.986544 DQS0 = 0, DQS1 = 0
8718 13:31:59.989419 DQM Delay:
8719 13:31:59.989491 DQM0 = 130, DQM1 = 123
8720 13:31:59.992730 DQ Delay:
8721 13:31:59.995955 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =126
8722 13:31:59.999810 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =128
8723 13:32:00.003119 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8724 13:32:00.006374 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =130
8725 13:32:00.006482
8726 13:32:00.006575
8727 13:32:00.006664
8728 13:32:00.009551 [DramC_TX_OE_Calibration] TA2
8729 13:32:00.012837 Original DQ_B0 (3 6) =30, OEN = 27
8730 13:32:00.016060 Original DQ_B1 (3 6) =30, OEN = 27
8731 13:32:00.019367 24, 0x0, End_B0=24 End_B1=24
8732 13:32:00.019465 25, 0x0, End_B0=25 End_B1=25
8733 13:32:00.022517 26, 0x0, End_B0=26 End_B1=26
8734 13:32:00.025660 27, 0x0, End_B0=27 End_B1=27
8735 13:32:00.029056 28, 0x0, End_B0=28 End_B1=28
8736 13:32:00.032423 29, 0x0, End_B0=29 End_B1=29
8737 13:32:00.032501 30, 0x0, End_B0=30 End_B1=30
8738 13:32:00.035789 31, 0x4141, End_B0=30 End_B1=30
8739 13:32:00.039151 Byte0 end_step=30 best_step=27
8740 13:32:00.042357 Byte1 end_step=30 best_step=27
8741 13:32:00.045953 Byte0 TX OE(2T, 0.5T) = (3, 3)
8742 13:32:00.049380 Byte1 TX OE(2T, 0.5T) = (3, 3)
8743 13:32:00.049463
8744 13:32:00.049529
8745 13:32:00.055410 [DQSOSCAuto] RK0, (LSB)MR18= 0xa0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
8746 13:32:00.058785 CH1 RK0: MR19=303, MR18=A0F
8747 13:32:00.065450 CH1_RK0: MR19=0x303, MR18=0xA0F, DQSOSC=402, MR23=63, INC=22, DEC=15
8748 13:32:00.065563
8749 13:32:00.068690 ----->DramcWriteLeveling(PI) begin...
8750 13:32:00.068779 ==
8751 13:32:00.072280 Dram Type= 6, Freq= 0, CH_1, rank 1
8752 13:32:00.075206 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8753 13:32:00.075315 ==
8754 13:32:00.078931 Write leveling (Byte 0): 23 => 23
8755 13:32:00.081990 Write leveling (Byte 1): 29 => 29
8756 13:32:00.085459 DramcWriteLeveling(PI) end<-----
8757 13:32:00.085562
8758 13:32:00.085682 ==
8759 13:32:00.088631 Dram Type= 6, Freq= 0, CH_1, rank 1
8760 13:32:00.091924 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8761 13:32:00.092007 ==
8762 13:32:00.095196 [Gating] SW mode calibration
8763 13:32:00.102229 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8764 13:32:00.108798 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8765 13:32:00.112034 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8766 13:32:00.118443 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 13:32:00.121837 1 4 8 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
8768 13:32:00.125196 1 4 12 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
8769 13:32:00.131707 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8770 13:32:00.135125 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8771 13:32:00.138461 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8772 13:32:00.144918 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8773 13:32:00.148269 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8774 13:32:00.151554 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8775 13:32:00.157717 1 5 8 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
8776 13:32:00.161452 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8777 13:32:00.164803 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 13:32:00.171587 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8779 13:32:00.174799 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8780 13:32:00.178137 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 13:32:00.181341 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 13:32:00.187661 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 13:32:00.191303 1 6 8 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8784 13:32:00.194621 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8785 13:32:00.201373 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8786 13:32:00.204119 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8787 13:32:00.207724 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8788 13:32:00.214402 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 13:32:00.217630 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 13:32:00.220820 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 13:32:00.227089 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8792 13:32:00.230495 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8793 13:32:00.234244 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 13:32:00.240652 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 13:32:00.243848 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 13:32:00.247263 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 13:32:00.254430 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 13:32:00.257108 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 13:32:00.260566 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 13:32:00.267531 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 13:32:00.270676 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 13:32:00.274083 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 13:32:00.280817 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 13:32:00.283556 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 13:32:00.286839 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 13:32:00.293668 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 13:32:00.296974 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8808 13:32:00.300366 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8809 13:32:00.303589 Total UI for P1: 0, mck2ui 16
8810 13:32:00.307098 best dqsien dly found for B0: ( 1, 9, 8)
8811 13:32:00.313223 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8812 13:32:00.313309 Total UI for P1: 0, mck2ui 16
8813 13:32:00.320307 best dqsien dly found for B1: ( 1, 9, 10)
8814 13:32:00.323408 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8815 13:32:00.326403 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8816 13:32:00.326485
8817 13:32:00.329840 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8818 13:32:00.333464 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8819 13:32:00.336747 [Gating] SW calibration Done
8820 13:32:00.336830 ==
8821 13:32:00.340056 Dram Type= 6, Freq= 0, CH_1, rank 1
8822 13:32:00.343240 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8823 13:32:00.343324 ==
8824 13:32:00.346397 RX Vref Scan: 0
8825 13:32:00.346505
8826 13:32:00.346599 RX Vref 0 -> 0, step: 1
8827 13:32:00.349853
8828 13:32:00.349935 RX Delay 0 -> 252, step: 8
8829 13:32:00.353091 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8830 13:32:00.359725 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8831 13:32:00.363071 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8832 13:32:00.366392 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8833 13:32:00.369555 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8834 13:32:00.373313 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8835 13:32:00.379719 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8836 13:32:00.383292 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8837 13:32:00.386421 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8838 13:32:00.389788 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8839 13:32:00.393070 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8840 13:32:00.399894 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8841 13:32:00.403127 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8842 13:32:00.406423 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8843 13:32:00.409485 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8844 13:32:00.416523 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8845 13:32:00.416637 ==
8846 13:32:00.419611 Dram Type= 6, Freq= 0, CH_1, rank 1
8847 13:32:00.422729 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8848 13:32:00.422806 ==
8849 13:32:00.422876 DQS Delay:
8850 13:32:00.425915 DQS0 = 0, DQS1 = 0
8851 13:32:00.426020 DQM Delay:
8852 13:32:00.429125 DQM0 = 132, DQM1 = 128
8853 13:32:00.429224 DQ Delay:
8854 13:32:00.432875 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8855 13:32:00.436210 DQ4 =127, DQ5 =143, DQ6 =139, DQ7 =131
8856 13:32:00.439311 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8857 13:32:00.442415 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =139
8858 13:32:00.442494
8859 13:32:00.442560
8860 13:32:00.446090 ==
8861 13:32:00.449361 Dram Type= 6, Freq= 0, CH_1, rank 1
8862 13:32:00.452578 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8863 13:32:00.452662 ==
8864 13:32:00.452729
8865 13:32:00.452789
8866 13:32:00.455915 TX Vref Scan disable
8867 13:32:00.455997 == TX Byte 0 ==
8868 13:32:00.459063 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8869 13:32:00.465935 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8870 13:32:00.466021 == TX Byte 1 ==
8871 13:32:00.472462 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8872 13:32:00.475845 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8873 13:32:00.475929 ==
8874 13:32:00.479092 Dram Type= 6, Freq= 0, CH_1, rank 1
8875 13:32:00.481997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8876 13:32:00.482098 ==
8877 13:32:00.497489
8878 13:32:00.500275 TX Vref early break, caculate TX vref
8879 13:32:00.503743 TX Vref=16, minBit 0, minWin=21, winSum=374
8880 13:32:00.507088 TX Vref=18, minBit 0, minWin=23, winSum=384
8881 13:32:00.510495 TX Vref=20, minBit 0, minWin=23, winSum=391
8882 13:32:00.513654 TX Vref=22, minBit 3, minWin=24, winSum=402
8883 13:32:00.517134 TX Vref=24, minBit 1, minWin=24, winSum=409
8884 13:32:00.523513 TX Vref=26, minBit 0, minWin=25, winSum=413
8885 13:32:00.527144 TX Vref=28, minBit 1, minWin=24, winSum=416
8886 13:32:00.530307 TX Vref=30, minBit 5, minWin=24, winSum=412
8887 13:32:00.533775 TX Vref=32, minBit 8, minWin=23, winSum=403
8888 13:32:00.536889 TX Vref=34, minBit 8, minWin=23, winSum=397
8889 13:32:00.540014 TX Vref=36, minBit 1, minWin=22, winSum=390
8890 13:32:00.546527 [TxChooseVref] Worse bit 0, Min win 25, Win sum 413, Final Vref 26
8891 13:32:00.546613
8892 13:32:00.550227 Final TX Range 0 Vref 26
8893 13:32:00.550310
8894 13:32:00.550376 ==
8895 13:32:00.553297 Dram Type= 6, Freq= 0, CH_1, rank 1
8896 13:32:00.556674 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8897 13:32:00.556757 ==
8898 13:32:00.556823
8899 13:32:00.560357
8900 13:32:00.560438 TX Vref Scan disable
8901 13:32:00.566598 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8902 13:32:00.566688 == TX Byte 0 ==
8903 13:32:00.569845 u2DelayCellOfst[0]=18 cells (5 PI)
8904 13:32:00.573166 u2DelayCellOfst[1]=11 cells (3 PI)
8905 13:32:00.576462 u2DelayCellOfst[2]=0 cells (0 PI)
8906 13:32:00.579752 u2DelayCellOfst[3]=3 cells (1 PI)
8907 13:32:00.582962 u2DelayCellOfst[4]=7 cells (2 PI)
8908 13:32:00.586855 u2DelayCellOfst[5]=22 cells (6 PI)
8909 13:32:00.589449 u2DelayCellOfst[6]=15 cells (4 PI)
8910 13:32:00.592973 u2DelayCellOfst[7]=3 cells (1 PI)
8911 13:32:00.596651 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8912 13:32:00.599826 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8913 13:32:00.603150 == TX Byte 1 ==
8914 13:32:00.606382 u2DelayCellOfst[8]=0 cells (0 PI)
8915 13:32:00.609628 u2DelayCellOfst[9]=7 cells (2 PI)
8916 13:32:00.612940 u2DelayCellOfst[10]=15 cells (4 PI)
8917 13:32:00.616205 u2DelayCellOfst[11]=7 cells (2 PI)
8918 13:32:00.616317 u2DelayCellOfst[12]=18 cells (5 PI)
8919 13:32:00.619321 u2DelayCellOfst[13]=18 cells (5 PI)
8920 13:32:00.623007 u2DelayCellOfst[14]=18 cells (5 PI)
8921 13:32:00.626223 u2DelayCellOfst[15]=18 cells (5 PI)
8922 13:32:00.632715 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8923 13:32:00.635865 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8924 13:32:00.635976 DramC Write-DBI on
8925 13:32:00.639679 ==
8926 13:32:00.639797 Dram Type= 6, Freq= 0, CH_1, rank 1
8927 13:32:00.646279 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8928 13:32:00.646387 ==
8929 13:32:00.646490
8930 13:32:00.646571
8931 13:32:00.649169 TX Vref Scan disable
8932 13:32:00.649278 == TX Byte 0 ==
8933 13:32:00.656164 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8934 13:32:00.656275 == TX Byte 1 ==
8935 13:32:00.659311 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8936 13:32:00.662336 DramC Write-DBI off
8937 13:32:00.662441
8938 13:32:00.662534 [DATLAT]
8939 13:32:00.666039 Freq=1600, CH1 RK1
8940 13:32:00.666139
8941 13:32:00.666229 DATLAT Default: 0xf
8942 13:32:00.669090 0, 0xFFFF, sum = 0
8943 13:32:00.669187 1, 0xFFFF, sum = 0
8944 13:32:00.672615 2, 0xFFFF, sum = 0
8945 13:32:00.672717 3, 0xFFFF, sum = 0
8946 13:32:00.676253 4, 0xFFFF, sum = 0
8947 13:32:00.676357 5, 0xFFFF, sum = 0
8948 13:32:00.679345 6, 0xFFFF, sum = 0
8949 13:32:00.679433 7, 0xFFFF, sum = 0
8950 13:32:00.682606 8, 0xFFFF, sum = 0
8951 13:32:00.682704 9, 0xFFFF, sum = 0
8952 13:32:00.685815 10, 0xFFFF, sum = 0
8953 13:32:00.689087 11, 0xFFFF, sum = 0
8954 13:32:00.689208 12, 0xFFFF, sum = 0
8955 13:32:00.692425 13, 0x8FFF, sum = 0
8956 13:32:00.692540 14, 0x0, sum = 1
8957 13:32:00.695508 15, 0x0, sum = 2
8958 13:32:00.695618 16, 0x0, sum = 3
8959 13:32:00.698749 17, 0x0, sum = 4
8960 13:32:00.698861 best_step = 15
8961 13:32:00.698973
8962 13:32:00.699078 ==
8963 13:32:00.702287 Dram Type= 6, Freq= 0, CH_1, rank 1
8964 13:32:00.705317 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8965 13:32:00.705428 ==
8966 13:32:00.709089 RX Vref Scan: 0
8967 13:32:00.709200
8968 13:32:00.712318 RX Vref 0 -> 0, step: 1
8969 13:32:00.712424
8970 13:32:00.712530 RX Delay 11 -> 252, step: 4
8971 13:32:00.719339 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8972 13:32:00.722507 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
8973 13:32:00.725671 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8974 13:32:00.729223 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8975 13:32:00.732853 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8976 13:32:00.739144 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
8977 13:32:00.742517 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8978 13:32:00.745599 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
8979 13:32:00.749474 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
8980 13:32:00.752488 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8981 13:32:00.758972 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8982 13:32:00.762002 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8983 13:32:00.765798 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8984 13:32:00.768732 iDelay=195, Bit 13, Center 134 (79 ~ 190) 112
8985 13:32:00.775658 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
8986 13:32:00.778801 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8987 13:32:00.778911 ==
8988 13:32:00.782356 Dram Type= 6, Freq= 0, CH_1, rank 1
8989 13:32:00.785520 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8990 13:32:00.785630 ==
8991 13:32:00.788677 DQS Delay:
8992 13:32:00.788786 DQS0 = 0, DQS1 = 0
8993 13:32:00.788887 DQM Delay:
8994 13:32:00.791913 DQM0 = 129, DQM1 = 125
8995 13:32:00.792022 DQ Delay:
8996 13:32:00.795189 DQ0 =134, DQ1 =128, DQ2 =118, DQ3 =126
8997 13:32:00.798565 DQ4 =126, DQ5 =140, DQ6 =140, DQ7 =126
8998 13:32:00.801767 DQ8 =112, DQ9 =112, DQ10 =128, DQ11 =120
8999 13:32:00.808869 DQ12 =132, DQ13 =134, DQ14 =130, DQ15 =136
9000 13:32:00.808974
9001 13:32:00.809080
9002 13:32:00.809176
9003 13:32:00.811908 [DramC_TX_OE_Calibration] TA2
9004 13:32:00.812014 Original DQ_B0 (3 6) =30, OEN = 27
9005 13:32:00.815574 Original DQ_B1 (3 6) =30, OEN = 27
9006 13:32:00.818484 24, 0x0, End_B0=24 End_B1=24
9007 13:32:00.821705 25, 0x0, End_B0=25 End_B1=25
9008 13:32:00.825507 26, 0x0, End_B0=26 End_B1=26
9009 13:32:00.828767 27, 0x0, End_B0=27 End_B1=27
9010 13:32:00.828875 28, 0x0, End_B0=28 End_B1=28
9011 13:32:00.832089 29, 0x0, End_B0=29 End_B1=29
9012 13:32:00.835286 30, 0x0, End_B0=30 End_B1=30
9013 13:32:00.838280 31, 0x4141, End_B0=30 End_B1=30
9014 13:32:00.841761 Byte0 end_step=30 best_step=27
9015 13:32:00.841870 Byte1 end_step=30 best_step=27
9016 13:32:00.845624 Byte0 TX OE(2T, 0.5T) = (3, 3)
9017 13:32:00.848815 Byte1 TX OE(2T, 0.5T) = (3, 3)
9018 13:32:00.848920
9019 13:32:00.849011
9020 13:32:00.858226 [DQSOSCAuto] RK1, (LSB)MR18= 0xd19, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 403 ps
9021 13:32:00.858333 CH1 RK1: MR19=303, MR18=D19
9022 13:32:00.865242 CH1_RK1: MR19=0x303, MR18=0xD19, DQSOSC=397, MR23=63, INC=23, DEC=15
9023 13:32:00.868341 [RxdqsGatingPostProcess] freq 1600
9024 13:32:00.875126 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9025 13:32:00.878225 best DQS0 dly(2T, 0.5T) = (1, 1)
9026 13:32:00.882017 best DQS1 dly(2T, 0.5T) = (1, 1)
9027 13:32:00.885352 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9028 13:32:00.885469 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9029 13:32:00.888481 best DQS0 dly(2T, 0.5T) = (1, 1)
9030 13:32:00.891653 best DQS1 dly(2T, 0.5T) = (1, 1)
9031 13:32:00.895378 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9032 13:32:00.898606 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9033 13:32:00.901894 Pre-setting of DQS Precalculation
9034 13:32:00.908359 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9035 13:32:00.914893 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9036 13:32:00.921437 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9037 13:32:00.921550
9038 13:32:00.921660
9039 13:32:00.925347 [Calibration Summary] 3200 Mbps
9040 13:32:00.925455 CH 0, Rank 0
9041 13:32:00.928232 SW Impedance : PASS
9042 13:32:00.931514 DUTY Scan : NO K
9043 13:32:00.931621 ZQ Calibration : PASS
9044 13:32:00.934788 Jitter Meter : NO K
9045 13:32:00.938074 CBT Training : PASS
9046 13:32:00.938182 Write leveling : PASS
9047 13:32:00.941333 RX DQS gating : PASS
9048 13:32:00.941433 RX DQ/DQS(RDDQC) : PASS
9049 13:32:00.944534 TX DQ/DQS : PASS
9050 13:32:00.948014 RX DATLAT : PASS
9051 13:32:00.948121 RX DQ/DQS(Engine): PASS
9052 13:32:00.951582 TX OE : PASS
9053 13:32:00.951703 All Pass.
9054 13:32:00.951798
9055 13:32:00.954783 CH 0, Rank 1
9056 13:32:00.954892 SW Impedance : PASS
9057 13:32:00.958287 DUTY Scan : NO K
9058 13:32:00.961445 ZQ Calibration : PASS
9059 13:32:00.961527 Jitter Meter : NO K
9060 13:32:00.964715 CBT Training : PASS
9061 13:32:00.967881 Write leveling : PASS
9062 13:32:00.967960 RX DQS gating : PASS
9063 13:32:00.971098 RX DQ/DQS(RDDQC) : PASS
9064 13:32:00.974246 TX DQ/DQS : PASS
9065 13:32:00.974336 RX DATLAT : PASS
9066 13:32:00.977931 RX DQ/DQS(Engine): PASS
9067 13:32:00.981150 TX OE : PASS
9068 13:32:00.981232 All Pass.
9069 13:32:00.981314
9070 13:32:00.981394 CH 1, Rank 0
9071 13:32:00.984197 SW Impedance : PASS
9072 13:32:00.987877 DUTY Scan : NO K
9073 13:32:00.987970 ZQ Calibration : PASS
9074 13:32:00.991075 Jitter Meter : NO K
9075 13:32:00.994272 CBT Training : PASS
9076 13:32:00.994355 Write leveling : PASS
9077 13:32:00.997409 RX DQS gating : PASS
9078 13:32:01.001280 RX DQ/DQS(RDDQC) : PASS
9079 13:32:01.001362 TX DQ/DQS : PASS
9080 13:32:01.004487 RX DATLAT : PASS
9081 13:32:01.004570 RX DQ/DQS(Engine): PASS
9082 13:32:01.007683 TX OE : PASS
9083 13:32:01.007766 All Pass.
9084 13:32:01.007831
9085 13:32:01.010962 CH 1, Rank 1
9086 13:32:01.011043 SW Impedance : PASS
9087 13:32:01.014247 DUTY Scan : NO K
9088 13:32:01.017494 ZQ Calibration : PASS
9089 13:32:01.017575 Jitter Meter : NO K
9090 13:32:01.020701 CBT Training : PASS
9091 13:32:01.023814 Write leveling : PASS
9092 13:32:01.023908 RX DQS gating : PASS
9093 13:32:01.027058 RX DQ/DQS(RDDQC) : PASS
9094 13:32:01.030356 TX DQ/DQS : PASS
9095 13:32:01.030442 RX DATLAT : PASS
9096 13:32:01.033890 RX DQ/DQS(Engine): PASS
9097 13:32:01.037021 TX OE : PASS
9098 13:32:01.037104 All Pass.
9099 13:32:01.037172
9100 13:32:01.040445 DramC Write-DBI on
9101 13:32:01.040526 PER_BANK_REFRESH: Hybrid Mode
9102 13:32:01.043663 TX_TRACKING: ON
9103 13:32:01.053585 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9104 13:32:01.060333 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9105 13:32:01.066729 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9106 13:32:01.070399 [FAST_K] Save calibration result to emmc
9107 13:32:01.073396 sync common calibartion params.
9108 13:32:01.076585 sync cbt_mode0:1, 1:1
9109 13:32:01.076667 dram_init: ddr_geometry: 2
9110 13:32:01.079884 dram_init: ddr_geometry: 2
9111 13:32:01.083766 dram_init: ddr_geometry: 2
9112 13:32:01.086619 0:dram_rank_size:100000000
9113 13:32:01.086722 1:dram_rank_size:100000000
9114 13:32:01.093123 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9115 13:32:01.096546 DFS_SHUFFLE_HW_MODE: ON
9116 13:32:01.099800 dramc_set_vcore_voltage set vcore to 725000
9117 13:32:01.103339 Read voltage for 1600, 0
9118 13:32:01.103442 Vio18 = 0
9119 13:32:01.103509 Vcore = 725000
9120 13:32:01.103570 Vdram = 0
9121 13:32:01.106467 Vddq = 0
9122 13:32:01.106549 Vmddr = 0
9123 13:32:01.110265 switch to 3200 Mbps bootup
9124 13:32:01.110348 [DramcRunTimeConfig]
9125 13:32:01.113494 PHYPLL
9126 13:32:01.113577 DPM_CONTROL_AFTERK: ON
9127 13:32:01.116758 PER_BANK_REFRESH: ON
9128 13:32:01.120032 REFRESH_OVERHEAD_REDUCTION: ON
9129 13:32:01.120114 CMD_PICG_NEW_MODE: OFF
9130 13:32:01.123287 XRTWTW_NEW_MODE: ON
9131 13:32:01.123368 XRTRTR_NEW_MODE: ON
9132 13:32:01.126463 TX_TRACKING: ON
9133 13:32:01.126545 RDSEL_TRACKING: OFF
9134 13:32:01.129649 DQS Precalculation for DVFS: ON
9135 13:32:01.133506 RX_TRACKING: OFF
9136 13:32:01.133588 HW_GATING DBG: ON
9137 13:32:01.136770 ZQCS_ENABLE_LP4: ON
9138 13:32:01.136851 RX_PICG_NEW_MODE: ON
9139 13:32:01.139920 TX_PICG_NEW_MODE: ON
9140 13:32:01.140025 ENABLE_RX_DCM_DPHY: ON
9141 13:32:01.143067 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9142 13:32:01.146160 DUMMY_READ_FOR_TRACKING: OFF
9143 13:32:01.150003 !!! SPM_CONTROL_AFTERK: OFF
9144 13:32:01.153288 !!! SPM could not control APHY
9145 13:32:01.153370 IMPEDANCE_TRACKING: ON
9146 13:32:01.156487 TEMP_SENSOR: ON
9147 13:32:01.156569 HW_SAVE_FOR_SR: OFF
9148 13:32:01.159654 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9149 13:32:01.162948 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9150 13:32:01.166529 Read ODT Tracking: ON
9151 13:32:01.170063 Refresh Rate DeBounce: ON
9152 13:32:01.170145 DFS_NO_QUEUE_FLUSH: ON
9153 13:32:01.172796 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9154 13:32:01.176353 ENABLE_DFS_RUNTIME_MRW: OFF
9155 13:32:01.179799 DDR_RESERVE_NEW_MODE: ON
9156 13:32:01.179882 MR_CBT_SWITCH_FREQ: ON
9157 13:32:01.182758 =========================
9158 13:32:01.201303 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9159 13:32:01.204994 dram_init: ddr_geometry: 2
9160 13:32:01.223476 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9161 13:32:01.226691 dram_init: dram init end (result: 0)
9162 13:32:01.233069 DRAM-K: Full calibration passed in 24572 msecs
9163 13:32:01.236322 MRC: failed to locate region type 0.
9164 13:32:01.236435 DRAM rank0 size:0x100000000,
9165 13:32:01.239518 DRAM rank1 size=0x100000000
9166 13:32:01.249625 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9167 13:32:01.256523 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9168 13:32:01.263025 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9169 13:32:01.269553 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9170 13:32:01.272703 DRAM rank0 size:0x100000000,
9171 13:32:01.276012 DRAM rank1 size=0x100000000
9172 13:32:01.276098 CBMEM:
9173 13:32:01.279731 IMD: root @ 0xfffff000 254 entries.
9174 13:32:01.282705 IMD: root @ 0xffffec00 62 entries.
9175 13:32:01.286308 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9176 13:32:01.289416 WARNING: RO_VPD is uninitialized or empty.
9177 13:32:01.295868 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9178 13:32:01.303288 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9179 13:32:01.315854 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9180 13:32:01.327588 BS: romstage times (exec / console): total (unknown) / 24036 ms
9181 13:32:01.327676
9182 13:32:01.327742
9183 13:32:01.337154 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9184 13:32:01.341011 ARM64: Exception handlers installed.
9185 13:32:01.344326 ARM64: Testing exception
9186 13:32:01.347506 ARM64: Done test exception
9187 13:32:01.347588 Enumerating buses...
9188 13:32:01.350718 Show all devs... Before device enumeration.
9189 13:32:01.354213 Root Device: enabled 1
9190 13:32:01.357188 CPU_CLUSTER: 0: enabled 1
9191 13:32:01.357271 CPU: 00: enabled 1
9192 13:32:01.360313 Compare with tree...
9193 13:32:01.360394 Root Device: enabled 1
9194 13:32:01.364040 CPU_CLUSTER: 0: enabled 1
9195 13:32:01.367342 CPU: 00: enabled 1
9196 13:32:01.367462 Root Device scanning...
9197 13:32:01.370736 scan_static_bus for Root Device
9198 13:32:01.373948 CPU_CLUSTER: 0 enabled
9199 13:32:01.377256 scan_static_bus for Root Device done
9200 13:32:01.380491 scan_bus: bus Root Device finished in 8 msecs
9201 13:32:01.380572 done
9202 13:32:01.386926 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9203 13:32:01.390076 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9204 13:32:01.396807 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9205 13:32:01.399912 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9206 13:32:01.403428 Allocating resources...
9207 13:32:01.407032 Reading resources...
9208 13:32:01.409889 Root Device read_resources bus 0 link: 0
9209 13:32:01.409990 DRAM rank0 size:0x100000000,
9210 13:32:01.413597 DRAM rank1 size=0x100000000
9211 13:32:01.416829 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9212 13:32:01.420126 CPU: 00 missing read_resources
9213 13:32:01.426485 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9214 13:32:01.430278 Root Device read_resources bus 0 link: 0 done
9215 13:32:01.430379 Done reading resources.
9216 13:32:01.436533 Show resources in subtree (Root Device)...After reading.
9217 13:32:01.439881 Root Device child on link 0 CPU_CLUSTER: 0
9218 13:32:01.443405 CPU_CLUSTER: 0 child on link 0 CPU: 00
9219 13:32:01.453470 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9220 13:32:01.453557 CPU: 00
9221 13:32:01.456709 Root Device assign_resources, bus 0 link: 0
9222 13:32:01.459911 CPU_CLUSTER: 0 missing set_resources
9223 13:32:01.466113 Root Device assign_resources, bus 0 link: 0 done
9224 13:32:01.466195 Done setting resources.
9225 13:32:01.473081 Show resources in subtree (Root Device)...After assigning values.
9226 13:32:01.476355 Root Device child on link 0 CPU_CLUSTER: 0
9227 13:32:01.479562 CPU_CLUSTER: 0 child on link 0 CPU: 00
9228 13:32:01.489272 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9229 13:32:01.489383 CPU: 00
9230 13:32:01.492951 Done allocating resources.
9231 13:32:01.499774 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9232 13:32:01.499854 Enabling resources...
9233 13:32:01.499918 done.
9234 13:32:01.506287 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9235 13:32:01.506389 Initializing devices...
9236 13:32:01.509336 Root Device init
9237 13:32:01.509429 init hardware done!
9238 13:32:01.512529 0x00000018: ctrlr->caps
9239 13:32:01.516318 52.000 MHz: ctrlr->f_max
9240 13:32:01.516391 0.400 MHz: ctrlr->f_min
9241 13:32:01.519586 0x40ff8080: ctrlr->voltages
9242 13:32:01.522579 sclk: 390625
9243 13:32:01.522666 Bus Width = 1
9244 13:32:01.522730 sclk: 390625
9245 13:32:01.526412 Bus Width = 1
9246 13:32:01.526495 Early init status = 3
9247 13:32:01.532808 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9248 13:32:01.536063 in-header: 03 fc 00 00 01 00 00 00
9249 13:32:01.539242 in-data: 00
9250 13:32:01.542500 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9251 13:32:01.548071 in-header: 03 fd 00 00 00 00 00 00
9252 13:32:01.550942 in-data:
9253 13:32:01.554266 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9254 13:32:01.559085 in-header: 03 fc 00 00 01 00 00 00
9255 13:32:01.562151 in-data: 00
9256 13:32:01.565347 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9257 13:32:01.571339 in-header: 03 fd 00 00 00 00 00 00
9258 13:32:01.574295 in-data:
9259 13:32:01.577355 [SSUSB] Setting up USB HOST controller...
9260 13:32:01.581045 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9261 13:32:01.584300 [SSUSB] phy power-on done.
9262 13:32:01.587608 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9263 13:32:01.594010 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9264 13:32:01.597079 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9265 13:32:01.603714 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9266 13:32:01.610655 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9267 13:32:01.617047 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9268 13:32:01.624076 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9269 13:32:01.630592 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9270 13:32:01.633746 SPM: binary array size = 0x9dc
9271 13:32:01.636968 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9272 13:32:01.643565 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9273 13:32:01.650581 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9274 13:32:01.656928 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9275 13:32:01.660087 configure_display: Starting display init
9276 13:32:01.694542 anx7625_power_on_init: Init interface.
9277 13:32:01.697743 anx7625_disable_pd_protocol: Disabled PD feature.
9278 13:32:01.701005 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9279 13:32:01.728314 anx7625_start_dp_work: Secure OCM version=00
9280 13:32:01.731611 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9281 13:32:01.746436 sp_tx_get_edid_block: EDID Block = 1
9282 13:32:01.849332 Extracted contents:
9283 13:32:01.852245 header: 00 ff ff ff ff ff ff 00
9284 13:32:01.856163 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9285 13:32:01.859360 version: 01 04
9286 13:32:01.862683 basic params: 95 1f 11 78 0a
9287 13:32:01.866031 chroma info: 76 90 94 55 54 90 27 21 50 54
9288 13:32:01.869259 established: 00 00 00
9289 13:32:01.875597 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9290 13:32:01.879481 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9291 13:32:01.885964 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9292 13:32:01.892157 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9293 13:32:01.898928 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9294 13:32:01.902129 extensions: 00
9295 13:32:01.902246 checksum: fb
9296 13:32:01.902339
9297 13:32:01.905991 Manufacturer: IVO Model 57d Serial Number 0
9298 13:32:01.908900 Made week 0 of 2020
9299 13:32:01.908999 EDID version: 1.4
9300 13:32:01.912473 Digital display
9301 13:32:01.915589 6 bits per primary color channel
9302 13:32:01.915674 DisplayPort interface
9303 13:32:01.919231 Maximum image size: 31 cm x 17 cm
9304 13:32:01.922292 Gamma: 220%
9305 13:32:01.922403 Check DPMS levels
9306 13:32:01.925746 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9307 13:32:01.929035 First detailed timing is preferred timing
9308 13:32:01.932024 Established timings supported:
9309 13:32:01.935352 Standard timings supported:
9310 13:32:01.938605 Detailed timings
9311 13:32:01.941830 Hex of detail: 383680a07038204018303c0035ae10000019
9312 13:32:01.945719 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9313 13:32:01.951998 0780 0798 07c8 0820 hborder 0
9314 13:32:01.955094 0438 043b 0447 0458 vborder 0
9315 13:32:01.958913 -hsync -vsync
9316 13:32:01.959001 Did detailed timing
9317 13:32:01.965010 Hex of detail: 000000000000000000000000000000000000
9318 13:32:01.965097 Manufacturer-specified data, tag 0
9319 13:32:01.972231 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9320 13:32:01.975339 ASCII string: InfoVision
9321 13:32:01.978709 Hex of detail: 000000fe00523134304e574635205248200a
9322 13:32:01.981782 ASCII string: R140NWF5 RH
9323 13:32:01.981855 Checksum
9324 13:32:01.984912 Checksum: 0xfb (valid)
9325 13:32:01.988124 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9326 13:32:01.992076 DSI data_rate: 832800000 bps
9327 13:32:01.998194 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9328 13:32:02.001513 anx7625_parse_edid: pixelclock(138800).
9329 13:32:02.005316 hactive(1920), hsync(48), hfp(24), hbp(88)
9330 13:32:02.008219 vactive(1080), vsync(12), vfp(3), vbp(17)
9331 13:32:02.011627 anx7625_dsi_config: config dsi.
9332 13:32:02.017902 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9333 13:32:02.031351 anx7625_dsi_config: success to config DSI
9334 13:32:02.034700 anx7625_dp_start: MIPI phy setup OK.
9335 13:32:02.037690 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9336 13:32:02.041259 mtk_ddp_mode_set invalid vrefresh 60
9337 13:32:02.044420 main_disp_path_setup
9338 13:32:02.044499 ovl_layer_smi_id_en
9339 13:32:02.047691 ovl_layer_smi_id_en
9340 13:32:02.047785 ccorr_config
9341 13:32:02.047862 aal_config
9342 13:32:02.050907 gamma_config
9343 13:32:02.050978 postmask_config
9344 13:32:02.054125 dither_config
9345 13:32:02.057414 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9346 13:32:02.064337 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9347 13:32:02.067328 Root Device init finished in 555 msecs
9348 13:32:02.071076 CPU_CLUSTER: 0 init
9349 13:32:02.077449 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9350 13:32:02.084449 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9351 13:32:02.084538 APU_MBOX 0x190000b0 = 0x10001
9352 13:32:02.087614 APU_MBOX 0x190001b0 = 0x10001
9353 13:32:02.090916 APU_MBOX 0x190005b0 = 0x10001
9354 13:32:02.094153 APU_MBOX 0x190006b0 = 0x10001
9355 13:32:02.097522 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9356 13:32:02.110080 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9357 13:32:02.122845 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9358 13:32:02.129255 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9359 13:32:02.140720 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9360 13:32:02.150108 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9361 13:32:02.153601 CPU_CLUSTER: 0 init finished in 81 msecs
9362 13:32:02.156703 Devices initialized
9363 13:32:02.159995 Show all devs... After init.
9364 13:32:02.160111 Root Device: enabled 1
9365 13:32:02.163191 CPU_CLUSTER: 0: enabled 1
9366 13:32:02.166378 CPU: 00: enabled 1
9367 13:32:02.170148 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9368 13:32:02.173353 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9369 13:32:02.176540 ELOG: NV offset 0x57f000 size 0x1000
9370 13:32:02.183044 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9371 13:32:02.189596 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9372 13:32:02.192897 ELOG: Event(17) added with size 13 at 2023-09-08 13:32:05 UTC
9373 13:32:02.199392 out: cmd=0x121: 03 db 21 01 00 00 00 00
9374 13:32:02.203271 in-header: 03 5a 00 00 2c 00 00 00
9375 13:32:02.212717 in-data: 04 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9376 13:32:02.219238 ELOG: Event(A1) added with size 10 at 2023-09-08 13:32:05 UTC
9377 13:32:02.225968 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9378 13:32:02.232567 ELOG: Event(A0) added with size 9 at 2023-09-08 13:32:05 UTC
9379 13:32:02.235797 elog_add_boot_reason: Logged dev mode boot
9380 13:32:02.242513 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9381 13:32:02.242614 Finalize devices...
9382 13:32:02.246071 Devices finalized
9383 13:32:02.249358 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9384 13:32:02.252635 Writing coreboot table at 0xffe64000
9385 13:32:02.255813 0. 000000000010a000-0000000000113fff: RAMSTAGE
9386 13:32:02.259363 1. 0000000040000000-00000000400fffff: RAM
9387 13:32:02.266146 2. 0000000040100000-000000004032afff: RAMSTAGE
9388 13:32:02.269447 3. 000000004032b000-00000000545fffff: RAM
9389 13:32:02.272754 4. 0000000054600000-000000005465ffff: BL31
9390 13:32:02.275724 5. 0000000054660000-00000000ffe63fff: RAM
9391 13:32:02.282282 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9392 13:32:02.286011 7. 0000000100000000-000000023fffffff: RAM
9393 13:32:02.289245 Passing 5 GPIOs to payload:
9394 13:32:02.292431 NAME | PORT | POLARITY | VALUE
9395 13:32:02.295603 EC in RW | 0x000000aa | low | undefined
9396 13:32:02.302733 EC interrupt | 0x00000005 | low | undefined
9397 13:32:02.305959 TPM interrupt | 0x000000ab | high | undefined
9398 13:32:02.312158 SD card detect | 0x00000011 | high | undefined
9399 13:32:02.315357 speaker enable | 0x00000093 | high | undefined
9400 13:32:02.319083 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9401 13:32:02.322255 in-header: 03 f9 00 00 02 00 00 00
9402 13:32:02.325478 in-data: 02 00
9403 13:32:02.328838 ADC[4]: Raw value=896300 ID=7
9404 13:32:02.328918 ADC[3]: Raw value=213070 ID=1
9405 13:32:02.331866 RAM Code: 0x71
9406 13:32:02.335731 ADC[6]: Raw value=74722 ID=0
9407 13:32:02.335822 ADC[5]: Raw value=212330 ID=1
9408 13:32:02.338945 SKU Code: 0x1
9409 13:32:02.342088 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 2dff
9410 13:32:02.345391 coreboot table: 964 bytes.
9411 13:32:02.348418 IMD ROOT 0. 0xfffff000 0x00001000
9412 13:32:02.352034 IMD SMALL 1. 0xffffe000 0x00001000
9413 13:32:02.355276 RO MCACHE 2. 0xffffc000 0x00001104
9414 13:32:02.358508 CONSOLE 3. 0xfff7c000 0x00080000
9415 13:32:02.361637 FMAP 4. 0xfff7b000 0x00000452
9416 13:32:02.365598 TIME STAMP 5. 0xfff7a000 0x00000910
9417 13:32:02.368755 VBOOT WORK 6. 0xfff66000 0x00014000
9418 13:32:02.371905 RAMOOPS 7. 0xffe66000 0x00100000
9419 13:32:02.375162 COREBOOT 8. 0xffe64000 0x00002000
9420 13:32:02.378305 IMD small region:
9421 13:32:02.381998 IMD ROOT 0. 0xffffec00 0x00000400
9422 13:32:02.384894 VPD 1. 0xffffeb80 0x0000006c
9423 13:32:02.388167 MMC STATUS 2. 0xffffeb60 0x00000004
9424 13:32:02.391701 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9425 13:32:02.395234 Probing TPM: done!
9426 13:32:02.398746 Connected to device vid:did:rid of 1ae0:0028:00
9427 13:32:02.408877 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9428 13:32:02.412669 Initialized TPM device CR50 revision 0
9429 13:32:02.416307 Checking cr50 for pending updates
9430 13:32:02.419572 Reading cr50 TPM mode
9431 13:32:02.428560 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9432 13:32:02.434999 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9433 13:32:02.475005 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9434 13:32:02.478614 Checking segment from ROM address 0x40100000
9435 13:32:02.481819 Checking segment from ROM address 0x4010001c
9436 13:32:02.488469 Loading segment from ROM address 0x40100000
9437 13:32:02.488546 code (compression=0)
9438 13:32:02.498318 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9439 13:32:02.505332 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9440 13:32:02.505424 it's not compressed!
9441 13:32:02.511886 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9442 13:32:02.515271 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9443 13:32:02.535303 Loading segment from ROM address 0x4010001c
9444 13:32:02.535442 Entry Point 0x80000000
9445 13:32:02.539208 Loaded segments
9446 13:32:02.542520 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9447 13:32:02.548733 Jumping to boot code at 0x80000000(0xffe64000)
9448 13:32:02.555825 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9449 13:32:02.562358 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9450 13:32:02.570372 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9451 13:32:02.573350 Checking segment from ROM address 0x40100000
9452 13:32:02.576568 Checking segment from ROM address 0x4010001c
9453 13:32:02.583675 Loading segment from ROM address 0x40100000
9454 13:32:02.583772 code (compression=1)
9455 13:32:02.590202 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9456 13:32:02.599819 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9457 13:32:02.599905 using LZMA
9458 13:32:02.608116 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9459 13:32:02.615358 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9460 13:32:02.618486 Loading segment from ROM address 0x4010001c
9461 13:32:02.618567 Entry Point 0x54601000
9462 13:32:02.621698 Loaded segments
9463 13:32:02.624783 NOTICE: MT8192 bl31_setup
9464 13:32:02.632306 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9465 13:32:02.635103 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9466 13:32:02.638862 WARNING: region 0:
9467 13:32:02.642117 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9468 13:32:02.642214 WARNING: region 1:
9469 13:32:02.648903 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9470 13:32:02.652102 WARNING: region 2:
9471 13:32:02.655158 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9472 13:32:02.659056 WARNING: region 3:
9473 13:32:02.662377 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9474 13:32:02.665463 WARNING: region 4:
9475 13:32:02.671822 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9476 13:32:02.671907 WARNING: region 5:
9477 13:32:02.675627 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9478 13:32:02.678756 WARNING: region 6:
9479 13:32:02.682214 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9480 13:32:02.682297 WARNING: region 7:
9481 13:32:02.688614 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9482 13:32:02.695660 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9483 13:32:02.698857 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9484 13:32:02.702275 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9485 13:32:02.709268 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9486 13:32:02.712511 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9487 13:32:02.715637 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9488 13:32:02.722353 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9489 13:32:02.725545 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9490 13:32:02.728838 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9491 13:32:02.735831 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9492 13:32:02.738820 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9493 13:32:02.745429 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9494 13:32:02.748988 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9495 13:32:02.752017 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9496 13:32:02.758899 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9497 13:32:02.762198 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9498 13:32:02.765748 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9499 13:32:02.772160 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9500 13:32:02.775397 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9501 13:32:02.781890 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9502 13:32:02.785131 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9503 13:32:02.788458 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9504 13:32:02.795174 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9505 13:32:02.798515 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9506 13:32:02.805230 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9507 13:32:02.808383 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9508 13:32:02.812127 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9509 13:32:02.818823 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9510 13:32:02.822103 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9511 13:32:02.828868 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9512 13:32:02.831945 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9513 13:32:02.835586 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9514 13:32:02.842132 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9515 13:32:02.845479 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9516 13:32:02.848543 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9517 13:32:02.852124 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9518 13:32:02.855443 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9519 13:32:02.862190 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9520 13:32:02.865300 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9521 13:32:02.869079 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9522 13:32:02.872072 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9523 13:32:02.878765 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9524 13:32:02.882010 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9525 13:32:02.885268 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9526 13:32:02.888494 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9527 13:32:02.895117 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9528 13:32:02.898822 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9529 13:32:02.901826 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9530 13:32:02.908411 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9531 13:32:02.911733 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9532 13:32:02.918745 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9533 13:32:02.921977 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9534 13:32:02.925237 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9535 13:32:02.931649 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9536 13:32:02.934889 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9537 13:32:02.941456 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9538 13:32:02.945295 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9539 13:32:02.951728 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9540 13:32:02.954868 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9541 13:32:02.961725 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9542 13:32:02.964905 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9543 13:32:02.968044 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9544 13:32:02.974879 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9545 13:32:02.977950 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9546 13:32:02.984662 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9547 13:32:02.988162 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9548 13:32:02.994547 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9549 13:32:02.997915 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9550 13:32:03.004917 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9551 13:32:03.008010 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9552 13:32:03.011416 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9553 13:32:03.017970 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9554 13:32:03.021147 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9555 13:32:03.028207 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9556 13:32:03.031367 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9557 13:32:03.037716 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9558 13:32:03.041052 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9559 13:32:03.044827 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9560 13:32:03.051520 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9561 13:32:03.054627 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9562 13:32:03.061104 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9563 13:32:03.064272 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9564 13:32:03.071037 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9565 13:32:03.074406 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9566 13:32:03.078087 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9567 13:32:03.084867 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9568 13:32:03.087877 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9569 13:32:03.094641 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9570 13:32:03.098059 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9571 13:32:03.104361 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9572 13:32:03.107627 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9573 13:32:03.110936 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9574 13:32:03.117740 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9575 13:32:03.120747 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9576 13:32:03.127966 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9577 13:32:03.131187 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9578 13:32:03.137690 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9579 13:32:03.140845 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9580 13:32:03.144750 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9581 13:32:03.148043 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9582 13:32:03.151122 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9583 13:32:03.157735 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9584 13:32:03.160781 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9585 13:32:03.167966 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9586 13:32:03.171107 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9587 13:32:03.174153 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9588 13:32:03.180998 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9589 13:32:03.184271 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9590 13:32:03.191135 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9591 13:32:03.194276 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9592 13:32:03.197593 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9593 13:32:03.204445 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9594 13:32:03.207894 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9595 13:32:03.214740 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9596 13:32:03.217819 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9597 13:32:03.221090 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9598 13:32:03.227507 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9599 13:32:03.231375 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9600 13:32:03.234367 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9601 13:32:03.241010 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9602 13:32:03.244267 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9603 13:32:03.247985 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9604 13:32:03.251303 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9605 13:32:03.257787 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9606 13:32:03.260900 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9607 13:32:03.264476 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9608 13:32:03.271410 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9609 13:32:03.274690 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9610 13:32:03.277877 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9611 13:32:03.284431 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9612 13:32:03.287594 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9613 13:32:03.294621 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9614 13:32:03.297731 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9615 13:32:03.300904 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9616 13:32:03.308022 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9617 13:32:03.311100 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9618 13:32:03.318012 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9619 13:32:03.321428 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9620 13:32:03.324330 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9621 13:32:03.331282 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9622 13:32:03.334562 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9623 13:32:03.337839 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9624 13:32:03.344664 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9625 13:32:03.348068 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9626 13:32:03.354377 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9627 13:32:03.358071 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9628 13:32:03.361382 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9629 13:32:03.367723 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9630 13:32:03.370935 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9631 13:32:03.378040 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9632 13:32:03.381428 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9633 13:32:03.384727 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9634 13:32:03.391390 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9635 13:32:03.394609 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9636 13:32:03.397940 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9637 13:32:03.404292 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9638 13:32:03.407885 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9639 13:32:03.414593 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9640 13:32:03.417813 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9641 13:32:03.421012 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9642 13:32:03.427272 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9643 13:32:03.430880 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9644 13:32:03.437390 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9645 13:32:03.440649 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9646 13:32:03.444613 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9647 13:32:03.451290 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9648 13:32:03.454377 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9649 13:32:03.461004 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9650 13:32:03.464064 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9651 13:32:03.467242 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9652 13:32:03.474117 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9653 13:32:03.477348 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9654 13:32:03.480663 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9655 13:32:03.487740 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9656 13:32:03.490865 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9657 13:32:03.497207 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9658 13:32:03.500886 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9659 13:32:03.507544 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9660 13:32:03.510768 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9661 13:32:03.513921 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9662 13:32:03.520646 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9663 13:32:03.523977 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9664 13:32:03.527172 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9665 13:32:03.533715 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9666 13:32:03.536929 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9667 13:32:03.543710 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9668 13:32:03.547147 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9669 13:32:03.550045 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9670 13:32:03.556699 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9671 13:32:03.559886 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9672 13:32:03.566786 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9673 13:32:03.569816 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9674 13:32:03.576720 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9675 13:32:03.579956 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9676 13:32:03.583038 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9677 13:32:03.590201 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9678 13:32:03.593400 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9679 13:32:03.599848 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9680 13:32:03.603070 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9681 13:32:03.609923 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9682 13:32:03.613079 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9683 13:32:03.616286 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9684 13:32:03.622720 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9685 13:32:03.625827 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9686 13:32:03.632524 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9687 13:32:03.635806 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9688 13:32:03.642346 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9689 13:32:03.645714 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9690 13:32:03.649473 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9691 13:32:03.655859 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9692 13:32:03.659302 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9693 13:32:03.665533 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9694 13:32:03.669136 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9695 13:32:03.675605 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9696 13:32:03.679053 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9697 13:32:03.682600 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9698 13:32:03.689106 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9699 13:32:03.692254 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9700 13:32:03.698678 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9701 13:32:03.702490 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9702 13:32:03.705708 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9703 13:32:03.712027 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9704 13:32:03.715593 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9705 13:32:03.721794 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9706 13:32:03.725198 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9707 13:32:03.731762 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9708 13:32:03.735049 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9709 13:32:03.738221 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9710 13:32:03.745316 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9711 13:32:03.748606 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9712 13:32:03.751708 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9713 13:32:03.754874 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9714 13:32:03.761408 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9715 13:32:03.765275 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9716 13:32:03.768385 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9717 13:32:03.775040 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9718 13:32:03.778383 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9719 13:32:03.784614 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9720 13:32:03.788341 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9721 13:32:03.791466 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9722 13:32:03.798087 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9723 13:32:03.801349 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9724 13:32:03.804808 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9725 13:32:03.811410 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9726 13:32:03.814547 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9727 13:32:03.817906 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9728 13:32:03.824609 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9729 13:32:03.827902 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9730 13:32:03.831088 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9731 13:32:03.837556 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9732 13:32:03.841340 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9733 13:32:03.847726 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9734 13:32:03.850841 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9735 13:32:03.854468 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9736 13:32:03.861136 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9737 13:32:03.864335 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9738 13:32:03.870697 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9739 13:32:03.873975 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9740 13:32:03.877307 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9741 13:32:03.883852 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9742 13:32:03.887542 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9743 13:32:03.890703 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9744 13:32:03.897672 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9745 13:32:03.900870 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9746 13:32:03.903927 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9747 13:32:03.910554 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9748 13:32:03.913891 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9749 13:32:03.920336 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9750 13:32:03.923990 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9751 13:32:03.927073 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9752 13:32:03.930683 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9753 13:32:03.933630 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9754 13:32:03.940317 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9755 13:32:03.943491 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9756 13:32:03.947345 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9757 13:32:03.950680 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9758 13:32:03.957056 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9759 13:32:03.960329 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9760 13:32:03.963562 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9761 13:32:03.967132 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9762 13:32:03.973559 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9763 13:32:03.976682 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9764 13:32:03.983258 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9765 13:32:03.986691 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9766 13:32:03.989906 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9767 13:32:03.996503 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9768 13:32:04.000309 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9769 13:32:04.006364 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9770 13:32:04.009889 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9771 13:32:04.013373 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9772 13:32:04.020036 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9773 13:32:04.023177 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9774 13:32:04.029641 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9775 13:32:04.033124 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9776 13:32:04.039765 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9777 13:32:04.043275 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9778 13:32:04.046531 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9779 13:32:04.052785 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9780 13:32:04.056060 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9781 13:32:04.063083 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9782 13:32:04.065908 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9783 13:32:04.069790 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9784 13:32:04.076209 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9785 13:32:04.079182 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9786 13:32:04.085825 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9787 13:32:04.089541 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9788 13:32:04.092796 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9789 13:32:04.099484 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9790 13:32:04.102732 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9791 13:32:04.109244 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9792 13:32:04.112475 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9793 13:32:04.119461 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9794 13:32:04.122595 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9795 13:32:04.126077 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9796 13:32:04.132473 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9797 13:32:04.136052 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9798 13:32:04.142278 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9799 13:32:04.145855 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9800 13:32:04.149243 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9801 13:32:04.155952 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9802 13:32:04.159006 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9803 13:32:04.165589 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9804 13:32:04.168801 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9805 13:32:04.172175 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9806 13:32:04.178563 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9807 13:32:04.182405 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9808 13:32:04.188912 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9809 13:32:04.192058 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9810 13:32:04.198822 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9811 13:32:04.202000 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9812 13:32:04.205241 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9813 13:32:04.211734 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9814 13:32:04.215017 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9815 13:32:04.222023 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9816 13:32:04.225384 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9817 13:32:04.228487 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9818 13:32:04.234785 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9819 13:32:04.238070 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9820 13:32:04.244718 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9821 13:32:04.248142 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9822 13:32:04.254348 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9823 13:32:04.257861 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9824 13:32:04.260898 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9825 13:32:04.268367 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9826 13:32:04.271276 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9827 13:32:04.277979 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9828 13:32:04.281185 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9829 13:32:04.284538 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9830 13:32:04.290900 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9831 13:32:04.294151 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9832 13:32:04.301231 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9833 13:32:04.304421 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9834 13:32:04.311040 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9835 13:32:04.314099 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9836 13:32:04.317278 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9837 13:32:04.324084 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9838 13:32:04.327338 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9839 13:32:04.334021 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9840 13:32:04.337427 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9841 13:32:04.343918 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9842 13:32:04.347239 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9843 13:32:04.350989 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9844 13:32:04.357641 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9845 13:32:04.360386 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9846 13:32:04.367400 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9847 13:32:04.370571 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9848 13:32:04.376988 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9849 13:32:04.380877 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9850 13:32:04.386937 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9851 13:32:04.390285 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9852 13:32:04.393493 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9853 13:32:04.400008 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9854 13:32:04.403216 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9855 13:32:04.409875 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9856 13:32:04.413766 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9857 13:32:04.420033 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9858 13:32:04.423586 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9859 13:32:04.426669 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9860 13:32:04.433076 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9861 13:32:04.436911 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9862 13:32:04.443328 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9863 13:32:04.446613 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9864 13:32:04.453110 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9865 13:32:04.456363 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9866 13:32:04.463477 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9867 13:32:04.466567 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9868 13:32:04.470040 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9869 13:32:04.476352 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9870 13:32:04.479792 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9871 13:32:04.486495 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9872 13:32:04.489769 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9873 13:32:04.496420 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9874 13:32:04.499303 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9875 13:32:04.502680 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9876 13:32:04.509088 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9877 13:32:04.512967 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9878 13:32:04.519486 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9879 13:32:04.522736 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9880 13:32:04.528994 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9881 13:32:04.532058 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9882 13:32:04.539036 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9883 13:32:04.542355 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9884 13:32:04.545623 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9885 13:32:04.551962 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9886 13:32:04.555253 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9887 13:32:04.561728 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9888 13:32:04.565089 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9889 13:32:04.571648 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9890 13:32:04.575385 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9891 13:32:04.581812 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9892 13:32:04.585007 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9893 13:32:04.591548 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9894 13:32:04.594897 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9895 13:32:04.601248 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9896 13:32:04.604609 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9897 13:32:04.611650 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9898 13:32:04.615034 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9899 13:32:04.621396 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9900 13:32:04.624655 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9901 13:32:04.631256 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9902 13:32:04.634407 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9903 13:32:04.641019 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9904 13:32:04.644875 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9905 13:32:04.651045 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9906 13:32:04.654526 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9907 13:32:04.661086 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9908 13:32:04.664299 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9909 13:32:04.671480 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9910 13:32:04.674754 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9911 13:32:04.681352 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9912 13:32:04.684551 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9913 13:32:04.691074 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9914 13:32:04.694394 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9915 13:32:04.700634 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9916 13:32:04.704088 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9917 13:32:04.707668 INFO: [APUAPC] vio 0
9918 13:32:04.710826 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9919 13:32:04.713983 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9920 13:32:04.717194 INFO: [APUAPC] D0_APC_0: 0x400510
9921 13:32:04.720504 INFO: [APUAPC] D0_APC_1: 0x0
9922 13:32:04.723729 INFO: [APUAPC] D0_APC_2: 0x1540
9923 13:32:04.727333 INFO: [APUAPC] D0_APC_3: 0x0
9924 13:32:04.730492 INFO: [APUAPC] D1_APC_0: 0xffffffff
9925 13:32:04.733758 INFO: [APUAPC] D1_APC_1: 0xffffffff
9926 13:32:04.737499 INFO: [APUAPC] D1_APC_2: 0x3fffff
9927 13:32:04.740191 INFO: [APUAPC] D1_APC_3: 0x0
9928 13:32:04.744055 INFO: [APUAPC] D2_APC_0: 0xffffffff
9929 13:32:04.747251 INFO: [APUAPC] D2_APC_1: 0xffffffff
9930 13:32:04.750431 INFO: [APUAPC] D2_APC_2: 0x3fffff
9931 13:32:04.753816 INFO: [APUAPC] D2_APC_3: 0x0
9932 13:32:04.756997 INFO: [APUAPC] D3_APC_0: 0xffffffff
9933 13:32:04.760682 INFO: [APUAPC] D3_APC_1: 0xffffffff
9934 13:32:04.763979 INFO: [APUAPC] D3_APC_2: 0x3fffff
9935 13:32:04.767111 INFO: [APUAPC] D3_APC_3: 0x0
9936 13:32:04.770103 INFO: [APUAPC] D4_APC_0: 0xffffffff
9937 13:32:04.773199 INFO: [APUAPC] D4_APC_1: 0xffffffff
9938 13:32:04.777069 INFO: [APUAPC] D4_APC_2: 0x3fffff
9939 13:32:04.780294 INFO: [APUAPC] D4_APC_3: 0x0
9940 13:32:04.783557 INFO: [APUAPC] D5_APC_0: 0xffffffff
9941 13:32:04.786597 INFO: [APUAPC] D5_APC_1: 0xffffffff
9942 13:32:04.789985 INFO: [APUAPC] D5_APC_2: 0x3fffff
9943 13:32:04.793246 INFO: [APUAPC] D5_APC_3: 0x0
9944 13:32:04.796448 INFO: [APUAPC] D6_APC_0: 0xffffffff
9945 13:32:04.799702 INFO: [APUAPC] D6_APC_1: 0xffffffff
9946 13:32:04.802974 INFO: [APUAPC] D6_APC_2: 0x3fffff
9947 13:32:04.806299 INFO: [APUAPC] D6_APC_3: 0x0
9948 13:32:04.810051 INFO: [APUAPC] D7_APC_0: 0xffffffff
9949 13:32:04.813299 INFO: [APUAPC] D7_APC_1: 0xffffffff
9950 13:32:04.816565 INFO: [APUAPC] D7_APC_2: 0x3fffff
9951 13:32:04.819623 INFO: [APUAPC] D7_APC_3: 0x0
9952 13:32:04.823063 INFO: [APUAPC] D8_APC_0: 0xffffffff
9953 13:32:04.826552 INFO: [APUAPC] D8_APC_1: 0xffffffff
9954 13:32:04.829748 INFO: [APUAPC] D8_APC_2: 0x3fffff
9955 13:32:04.832855 INFO: [APUAPC] D8_APC_3: 0x0
9956 13:32:04.836360 INFO: [APUAPC] D9_APC_0: 0xffffffff
9957 13:32:04.839541 INFO: [APUAPC] D9_APC_1: 0xffffffff
9958 13:32:04.842883 INFO: [APUAPC] D9_APC_2: 0x3fffff
9959 13:32:04.846075 INFO: [APUAPC] D9_APC_3: 0x0
9960 13:32:04.849842 INFO: [APUAPC] D10_APC_0: 0xffffffff
9961 13:32:04.852865 INFO: [APUAPC] D10_APC_1: 0xffffffff
9962 13:32:04.856214 INFO: [APUAPC] D10_APC_2: 0x3fffff
9963 13:32:04.858949 INFO: [APUAPC] D10_APC_3: 0x0
9964 13:32:04.862520 INFO: [APUAPC] D11_APC_0: 0xffffffff
9965 13:32:04.865680 INFO: [APUAPC] D11_APC_1: 0xffffffff
9966 13:32:04.868859 INFO: [APUAPC] D11_APC_2: 0x3fffff
9967 13:32:04.872228 INFO: [APUAPC] D11_APC_3: 0x0
9968 13:32:04.875407 INFO: [APUAPC] D12_APC_0: 0xffffffff
9969 13:32:04.879112 INFO: [APUAPC] D12_APC_1: 0xffffffff
9970 13:32:04.882007 INFO: [APUAPC] D12_APC_2: 0x3fffff
9971 13:32:04.885444 INFO: [APUAPC] D12_APC_3: 0x0
9972 13:32:04.889097 INFO: [APUAPC] D13_APC_0: 0xffffffff
9973 13:32:04.892257 INFO: [APUAPC] D13_APC_1: 0xffffffff
9974 13:32:04.895418 INFO: [APUAPC] D13_APC_2: 0x3fffff
9975 13:32:04.898686 INFO: [APUAPC] D13_APC_3: 0x0
9976 13:32:04.901948 INFO: [APUAPC] D14_APC_0: 0xffffffff
9977 13:32:04.905130 INFO: [APUAPC] D14_APC_1: 0xffffffff
9978 13:32:04.908457 INFO: [APUAPC] D14_APC_2: 0x3fffff
9979 13:32:04.911640 INFO: [APUAPC] D14_APC_3: 0x0
9980 13:32:04.915548 INFO: [APUAPC] D15_APC_0: 0xffffffff
9981 13:32:04.918678 INFO: [APUAPC] D15_APC_1: 0xffffffff
9982 13:32:04.921955 INFO: [APUAPC] D15_APC_2: 0x3fffff
9983 13:32:04.925312 INFO: [APUAPC] D15_APC_3: 0x0
9984 13:32:04.928444 INFO: [APUAPC] APC_CON: 0x4
9985 13:32:04.931734 INFO: [NOCDAPC] D0_APC_0: 0x0
9986 13:32:04.934885 INFO: [NOCDAPC] D0_APC_1: 0x0
9987 13:32:04.934961 INFO: [NOCDAPC] D1_APC_0: 0x0
9988 13:32:04.938023 INFO: [NOCDAPC] D1_APC_1: 0xfff
9989 13:32:04.941539 INFO: [NOCDAPC] D2_APC_0: 0x0
9990 13:32:04.944901 INFO: [NOCDAPC] D2_APC_1: 0xfff
9991 13:32:04.948126 INFO: [NOCDAPC] D3_APC_0: 0x0
9992 13:32:04.951308 INFO: [NOCDAPC] D3_APC_1: 0xfff
9993 13:32:04.955229 INFO: [NOCDAPC] D4_APC_0: 0x0
9994 13:32:04.958378 INFO: [NOCDAPC] D4_APC_1: 0xfff
9995 13:32:04.961705 INFO: [NOCDAPC] D5_APC_0: 0x0
9996 13:32:04.964749 INFO: [NOCDAPC] D5_APC_1: 0xfff
9997 13:32:04.968429 INFO: [NOCDAPC] D6_APC_0: 0x0
9998 13:32:04.968532 INFO: [NOCDAPC] D6_APC_1: 0xfff
9999 13:32:04.971383 INFO: [NOCDAPC] D7_APC_0: 0x0
10000 13:32:04.974769 INFO: [NOCDAPC] D7_APC_1: 0xfff
10001 13:32:04.977875 INFO: [NOCDAPC] D8_APC_0: 0x0
10002 13:32:04.981427 INFO: [NOCDAPC] D8_APC_1: 0xfff
10003 13:32:04.984636 INFO: [NOCDAPC] D9_APC_0: 0x0
10004 13:32:04.987898 INFO: [NOCDAPC] D9_APC_1: 0xfff
10005 13:32:04.991064 INFO: [NOCDAPC] D10_APC_0: 0x0
10006 13:32:04.994745 INFO: [NOCDAPC] D10_APC_1: 0xfff
10007 13:32:04.998367 INFO: [NOCDAPC] D11_APC_0: 0x0
10008 13:32:05.001211 INFO: [NOCDAPC] D11_APC_1: 0xfff
10009 13:32:05.004589 INFO: [NOCDAPC] D12_APC_0: 0x0
10010 13:32:05.008056 INFO: [NOCDAPC] D12_APC_1: 0xfff
10011 13:32:05.008137 INFO: [NOCDAPC] D13_APC_0: 0x0
10012 13:32:05.011311 INFO: [NOCDAPC] D13_APC_1: 0xfff
10013 13:32:05.014478 INFO: [NOCDAPC] D14_APC_0: 0x0
10014 13:32:05.017710 INFO: [NOCDAPC] D14_APC_1: 0xfff
10015 13:32:05.021027 INFO: [NOCDAPC] D15_APC_0: 0x0
10016 13:32:05.024296 INFO: [NOCDAPC] D15_APC_1: 0xfff
10017 13:32:05.027506 INFO: [NOCDAPC] APC_CON: 0x4
10018 13:32:05.031402 INFO: [APUAPC] set_apusys_apc done
10019 13:32:05.034017 INFO: [DEVAPC] devapc_init done
10020 13:32:05.037311 INFO: GICv3 without legacy support detected.
10021 13:32:05.044312 INFO: ARM GICv3 driver initialized in EL3
10022 13:32:05.047475 INFO: Maximum SPI INTID supported: 639
10023 13:32:05.050552 INFO: BL31: Initializing runtime services
10024 13:32:05.057493 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10025 13:32:05.057580 INFO: SPM: enable CPC mode
10026 13:32:05.063749 INFO: mcdi ready for mcusys-off-idle and system suspend
10027 13:32:05.067268 INFO: BL31: Preparing for EL3 exit to normal world
10028 13:32:05.073857 INFO: Entry point address = 0x80000000
10029 13:32:05.073944 INFO: SPSR = 0x8
10030 13:32:05.079725
10031 13:32:05.079811
10032 13:32:05.079898
10033 13:32:05.083322 Starting depthcharge on Spherion...
10034 13:32:05.083458
10035 13:32:05.083565 Wipe memory regions:
10036 13:32:05.083649
10037 13:32:05.084476 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10038 13:32:05.084612 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10039 13:32:05.084708 Setting prompt string to ['asurada:']
10040 13:32:05.084824 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10041 13:32:05.086561 [0x00000040000000, 0x00000054600000)
10042 13:32:05.209102
10043 13:32:05.209291 [0x00000054660000, 0x00000080000000)
10044 13:32:05.469507
10045 13:32:05.469693 [0x000000821a7280, 0x000000ffe64000)
10046 13:32:06.214377
10047 13:32:06.214535 [0x00000100000000, 0x00000240000000)
10048 13:32:08.105073
10049 13:32:08.108240 Initializing XHCI USB controller at 0x11200000.
10050 13:32:09.145995
10051 13:32:09.149268 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10052 13:32:09.149367
10053 13:32:09.149432
10054 13:32:09.149494
10055 13:32:09.149779 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10057 13:32:09.250162 asurada: tftpboot 192.168.201.1 11471202/tftp-deploy-6wala_bt/kernel/image.itb 11471202/tftp-deploy-6wala_bt/kernel/cmdline
10058 13:32:09.250348 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10059 13:32:09.250455 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10060 13:32:09.254781 tftpboot 192.168.201.1 11471202/tftp-deploy-6wala_bt/kernel/image.ittp-deploy-6wala_bt/kernel/cmdline
10061 13:32:09.254868
10062 13:32:09.254934 Waiting for link
10063 13:32:09.415761
10064 13:32:09.415911 R8152: Initializing
10065 13:32:09.415983
10066 13:32:09.418883 Version 6 (ocp_data = 5c30)
10067 13:32:09.418981
10068 13:32:09.422186 R8152: Done initializing
10069 13:32:09.422267
10070 13:32:09.422333 Adding net device
10071 13:32:11.451065
10072 13:32:11.451245 done.
10073 13:32:11.451338
10074 13:32:11.451452 MAC: 00:24:32:30:78:ff
10075 13:32:11.451513
10076 13:32:11.454232 Sending DHCP discover... done.
10077 13:32:11.454313
10078 13:32:11.458276 Waiting for reply... done.
10079 13:32:11.458357
10080 13:32:11.461308 Sending DHCP request... done.
10081 13:32:11.461388
10082 13:32:11.468290 Waiting for reply... done.
10083 13:32:11.468372
10084 13:32:11.468450 My ip is 192.168.201.21
10085 13:32:11.468525
10086 13:32:11.471321 The DHCP server ip is 192.168.201.1
10087 13:32:11.471441
10088 13:32:11.477998 TFTP server IP predefined by user: 192.168.201.1
10089 13:32:11.478079
10090 13:32:11.484977 Bootfile predefined by user: 11471202/tftp-deploy-6wala_bt/kernel/image.itb
10091 13:32:11.485059
10092 13:32:11.488247 Sending tftp read request... done.
10093 13:32:11.488330
10094 13:32:11.491997 Waiting for the transfer...
10095 13:32:11.492080
10096 13:32:12.142914 00000000 ################################################################
10097 13:32:12.143102
10098 13:32:12.784829 00080000 ################################################################
10099 13:32:12.784977
10100 13:32:13.423769 00100000 ################################################################
10101 13:32:13.423958
10102 13:32:14.074995 00180000 ################################################################
10103 13:32:14.075166
10104 13:32:14.739490 00200000 ################################################################
10105 13:32:14.739641
10106 13:32:15.392739 00280000 ################################################################
10107 13:32:15.392985
10108 13:32:16.055171 00300000 ################################################################
10109 13:32:16.055324
10110 13:32:16.714199 00380000 ################################################################
10111 13:32:16.714361
10112 13:32:17.356547 00400000 ################################################################
10113 13:32:17.356732
10114 13:32:17.983713 00480000 ################################################################
10115 13:32:17.983858
10116 13:32:18.632015 00500000 ################################################################
10117 13:32:18.632165
10118 13:32:19.253455 00580000 ################################################################
10119 13:32:19.253594
10120 13:32:19.798056 00600000 ################################################################
10121 13:32:19.798189
10122 13:32:20.365049 00680000 ################################################################
10123 13:32:20.365181
10124 13:32:20.922613 00700000 ################################################################
10125 13:32:20.922765
10126 13:32:21.539675 00780000 ################################################################
10127 13:32:21.539815
10128 13:32:22.097892 00800000 ################################################################
10129 13:32:22.098051
10130 13:32:22.705246 00880000 ################################################################
10131 13:32:22.705428
10132 13:32:23.360741 00900000 ################################################################
10133 13:32:23.360893
10134 13:32:24.020478 00980000 ################################################################
10135 13:32:24.020649
10136 13:32:24.682097 00a00000 ################################################################
10137 13:32:24.682266
10138 13:32:25.300624 00a80000 ################################################################
10139 13:32:25.300768
10140 13:32:25.891683 00b00000 ################################################################
10141 13:32:25.891824
10142 13:32:26.454260 00b80000 ################################################################
10143 13:32:26.454425
10144 13:32:27.069451 00c00000 ################################################################
10145 13:32:27.069597
10146 13:32:27.648518 00c80000 ################################################################
10147 13:32:27.648681
10148 13:32:28.227251 00d00000 ################################################################
10149 13:32:28.227465
10150 13:32:28.803436 00d80000 ################################################################
10151 13:32:28.803588
10152 13:32:29.391100 00e00000 ################################################################
10153 13:32:29.391284
10154 13:32:29.966847 00e80000 ################################################################
10155 13:32:29.967024
10156 13:32:30.527968 00f00000 ################################################################
10157 13:32:30.528143
10158 13:32:31.083994 00f80000 ################################################################
10159 13:32:31.084167
10160 13:32:31.629288 01000000 ################################################################
10161 13:32:31.629566
10162 13:32:32.210823 01080000 ################################################################
10163 13:32:32.211427
10164 13:32:32.777321 01100000 ################################################################
10165 13:32:32.777500
10166 13:32:33.386848 01180000 ################################################################
10167 13:32:33.386997
10168 13:32:33.946928 01200000 ################################################################
10169 13:32:33.947121
10170 13:32:34.492846 01280000 ################################################################
10171 13:32:34.493003
10172 13:32:35.133718 01300000 ################################################################
10173 13:32:35.134422
10174 13:32:35.786991 01380000 ################################################################
10175 13:32:35.787274
10176 13:32:36.359909 01400000 ################################################################
10177 13:32:36.360075
10178 13:32:36.932260 01480000 ################################################################
10179 13:32:36.932411
10180 13:32:37.472377 01500000 ################################################################
10181 13:32:37.472529
10182 13:32:38.024076 01580000 ################################################################
10183 13:32:38.024221
10184 13:32:38.663586 01600000 ################################################################
10185 13:32:38.664259
10186 13:32:39.236089 01680000 ################################################################
10187 13:32:39.236233
10188 13:32:39.820786 01700000 ################################################################
10189 13:32:39.821558
10190 13:32:40.391128 01780000 ################################################################
10191 13:32:40.391277
10192 13:32:40.952910 01800000 ################################################################
10193 13:32:40.953058
10194 13:32:41.518508 01880000 ################################################################
10195 13:32:41.518660
10196 13:32:42.070040 01900000 ################################################################
10197 13:32:42.070220
10198 13:32:42.623990 01980000 ################################################################
10199 13:32:42.624141
10200 13:32:43.181483 01a00000 ################################################################
10201 13:32:43.181652
10202 13:32:43.829013 01a80000 ################################################################
10203 13:32:43.829520
10204 13:32:44.517437 01b00000 ################################################################
10205 13:32:44.517586
10206 13:32:45.182025 01b80000 ################################################################
10207 13:32:45.182533
10208 13:32:45.865224 01c00000 ################################################################
10209 13:32:45.865737
10210 13:32:46.551277 01c80000 ################################################################
10211 13:32:46.551834
10212 13:32:47.255287 01d00000 ################################################################
10213 13:32:47.255863
10214 13:32:47.858617 01d80000 ################################################################
10215 13:32:47.858757
10216 13:32:48.429242 01e00000 ################################################################
10217 13:32:48.429417
10218 13:32:49.054761 01e80000 ################################################################
10219 13:32:49.055244
10220 13:32:49.660934 01f00000 ################################################################
10221 13:32:49.661094
10222 13:32:50.242265 01f80000 ################################################################
10223 13:32:50.242404
10224 13:32:50.879212 02000000 ################################################################
10225 13:32:50.879751
10226 13:32:51.545088 02080000 ################################################################
10227 13:32:51.545849
10228 13:32:52.124877 02100000 ################################################################
10229 13:32:52.125016
10230 13:32:52.786609 02180000 ################################################################
10231 13:32:52.787257
10232 13:32:53.466802 02200000 ################################################################
10233 13:32:53.466997
10234 13:32:54.110823 02280000 ################################################################
10235 13:32:54.111470
10236 13:32:54.782952 02300000 ################################################################
10237 13:32:54.783490
10238 13:32:55.446581 02380000 ################################################################
10239 13:32:55.447106
10240 13:32:56.050465 02400000 ################################################################
10241 13:32:56.050611
10242 13:32:56.724321 02480000 ################################################################
10243 13:32:56.724508
10244 13:32:57.384062 02500000 ################################################################
10245 13:32:57.384228
10246 13:32:58.039337 02580000 ################################################################
10247 13:32:58.039532
10248 13:32:58.689660 02600000 ################################################################
10249 13:32:58.689826
10250 13:32:59.341718 02680000 ################################################################
10251 13:32:59.341880
10252 13:32:59.985046 02700000 ################################################################
10253 13:32:59.985192
10254 13:33:00.629542 02780000 ################################################################
10255 13:33:00.629690
10256 13:33:01.281915 02800000 ################################################################
10257 13:33:01.282060
10258 13:33:01.923266 02880000 ################################################################
10259 13:33:01.923466
10260 13:33:02.570885 02900000 ################################################################
10261 13:33:02.571038
10262 13:33:03.216954 02980000 ################################################################
10263 13:33:03.217153
10264 13:33:03.884207 02a00000 ################################################################
10265 13:33:03.884385
10266 13:33:04.548974 02a80000 ################################################################
10267 13:33:04.549122
10268 13:33:05.215630 02b00000 ################################################################
10269 13:33:05.215772
10270 13:33:05.870918 02b80000 ################################################################
10271 13:33:05.871069
10272 13:33:06.516168 02c00000 ################################################################
10273 13:33:06.516344
10274 13:33:07.169545 02c80000 ################################################################
10275 13:33:07.169680
10276 13:33:07.839031 02d00000 ################################################################
10277 13:33:07.839182
10278 13:33:08.510009 02d80000 ################################################################
10279 13:33:08.510189
10280 13:33:09.184588 02e00000 ################################################################
10281 13:33:09.184739
10282 13:33:09.831653 02e80000 ################################################################
10283 13:33:09.831834
10284 13:33:10.482005 02f00000 ################################################################
10285 13:33:10.482143
10286 13:33:11.149307 02f80000 ################################################################
10287 13:33:11.149455
10288 13:33:11.273037 03000000 ############ done.
10289 13:33:11.273182
10290 13:33:11.276069 The bootfile was 50427910 bytes long.
10291 13:33:11.276170
10292 13:33:11.279125 Sending tftp read request... done.
10293 13:33:11.279236
10294 13:33:11.279335 Waiting for the transfer...
10295 13:33:11.279436
10296 13:33:11.282634 00000000 # done.
10297 13:33:11.282717
10298 13:33:11.289207 Command line loaded dynamically from TFTP file: 11471202/tftp-deploy-6wala_bt/kernel/cmdline
10299 13:33:11.289358
10300 13:33:11.302660 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10301 13:33:11.302747
10302 13:33:11.306004 Loading FIT.
10303 13:33:11.306083
10304 13:33:11.309260 Image ramdisk-1 has 39338503 bytes.
10305 13:33:11.309339
10306 13:33:11.312494 Image fdt-1 has 47278 bytes.
10307 13:33:11.312574
10308 13:33:11.312638 Image kernel-1 has 11040095 bytes.
10309 13:33:11.315626
10310 13:33:11.322350 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10311 13:33:11.322431
10312 13:33:11.339133 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10313 13:33:11.342399
10314 13:33:11.345469 Choosing best match conf-1 for compat google,spherion-rev2.
10315 13:33:11.349980
10316 13:33:11.354562 Connected to device vid:did:rid of 1ae0:0028:00
10317 13:33:11.361372
10318 13:33:11.364535 tpm_get_response: command 0x17b, return code 0x0
10319 13:33:11.364615
10320 13:33:11.367753 ec_init: CrosEC protocol v3 supported (256, 248)
10321 13:33:11.372329
10322 13:33:11.375676 tpm_cleanup: add release locality here.
10323 13:33:11.375783
10324 13:33:11.375874 Shutting down all USB controllers.
10325 13:33:11.378515
10326 13:33:11.378594 Removing current net device
10327 13:33:11.378657
10328 13:33:11.385352 Exiting depthcharge with code 4 at timestamp: 95614017
10329 13:33:11.385433
10330 13:33:11.388573 LZMA decompressing kernel-1 to 0x821a6718
10331 13:33:11.388653
10332 13:33:11.391747 LZMA decompressing kernel-1 to 0x40000000
10333 13:33:12.779988
10334 13:33:12.780134 jumping to kernel
10335 13:33:12.780555 end: 2.2.4 bootloader-commands (duration 00:01:08) [common]
10336 13:33:12.780656 start: 2.2.5 auto-login-action (timeout 00:03:18) [common]
10337 13:33:12.780731 Setting prompt string to ['Linux version [0-9]']
10338 13:33:12.780799 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10339 13:33:12.780865 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10340 13:33:12.861886
10341 13:33:12.865072 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10342 13:33:12.868512 start: 2.2.5.1 login-action (timeout 00:03:17) [common]
10343 13:33:12.868602 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10344 13:33:12.868672 Setting prompt string to []
10345 13:33:12.868752 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10346 13:33:12.868826 Using line separator: #'\n'#
10347 13:33:12.868885 No login prompt set.
10348 13:33:12.868944 Parsing kernel messages
10349 13:33:12.868999 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10350 13:33:12.869119 [login-action] Waiting for messages, (timeout 00:03:17)
10351 13:33:12.888072 [ 0.000000] Linux version 6.1.52-cip5 (KernelCI@build-j38933-arm64-gcc-10-defconfig-arm64-chromebook-kgx6p) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Sep 8 13:10:51 UTC 2023
10352 13:33:12.891243 [ 0.000000] random: crng init done
10353 13:33:12.897737 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10354 13:33:12.901535 [ 0.000000] efi: UEFI not found.
10355 13:33:12.908155 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10356 13:33:12.914327 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10357 13:33:12.924297 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10358 13:33:12.934274 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10359 13:33:12.940858 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10360 13:33:12.947703 [ 0.000000] printk: bootconsole [mtk8250] enabled
10361 13:33:12.954054 [ 0.000000] NUMA: No NUMA configuration found
10362 13:33:12.960657 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10363 13:33:12.963612 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10364 13:33:12.967358 [ 0.000000] Zone ranges:
10365 13:33:12.973395 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10366 13:33:12.977138 [ 0.000000] DMA32 empty
10367 13:33:12.983282 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10368 13:33:12.987099 [ 0.000000] Movable zone start for each node
10369 13:33:12.990307 [ 0.000000] Early memory node ranges
10370 13:33:12.996785 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10371 13:33:13.003218 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10372 13:33:13.010181 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10373 13:33:13.016630 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10374 13:33:13.022922 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10375 13:33:13.029563 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10376 13:33:13.086141 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10377 13:33:13.092355 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10378 13:33:13.098847 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10379 13:33:13.102069 [ 0.000000] psci: probing for conduit method from DT.
10380 13:33:13.109021 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10381 13:33:13.112148 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10382 13:33:13.118687 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10383 13:33:13.121934 [ 0.000000] psci: SMC Calling Convention v1.2
10384 13:33:13.128450 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10385 13:33:13.131717 [ 0.000000] Detected VIPT I-cache on CPU0
10386 13:33:13.138565 [ 0.000000] CPU features: detected: GIC system register CPU interface
10387 13:33:13.145257 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10388 13:33:13.152129 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10389 13:33:13.158185 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10390 13:33:13.168350 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10391 13:33:13.174511 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10392 13:33:13.178250 [ 0.000000] alternatives: applying boot alternatives
10393 13:33:13.184577 [ 0.000000] Fallback order for Node 0: 0
10394 13:33:13.191015 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10395 13:33:13.194707 [ 0.000000] Policy zone: Normal
10396 13:33:13.207570 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10397 13:33:13.217587 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10398 13:33:13.230505 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10399 13:33:13.240198 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10400 13:33:13.246741 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10401 13:33:13.249849 <6>[ 0.000000] software IO TLB: area num 8.
10402 13:33:13.306818 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10403 13:33:13.455874 <6>[ 0.000000] Memory: 7931076K/8385536K available (17984K kernel code, 4098K rwdata, 17468K rodata, 8384K init, 616K bss, 421692K reserved, 32768K cma-reserved)
10404 13:33:13.462422 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10405 13:33:13.469300 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10406 13:33:13.472360 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10407 13:33:13.478875 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10408 13:33:13.485262 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10409 13:33:13.488948 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10410 13:33:13.498616 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10411 13:33:13.505349 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10412 13:33:13.511773 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10413 13:33:13.518726 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10414 13:33:13.521642 <6>[ 0.000000] GICv3: 608 SPIs implemented
10415 13:33:13.525051 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10416 13:33:13.531784 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10417 13:33:13.535105 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10418 13:33:13.541649 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10419 13:33:13.554784 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10420 13:33:13.565205 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10421 13:33:13.575465 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10422 13:33:13.582470 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10423 13:33:13.595171 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10424 13:33:13.602247 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10425 13:33:13.608998 <6>[ 0.009184] Console: colour dummy device 80x25
10426 13:33:13.618345 <6>[ 0.013911] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10427 13:33:13.625384 <6>[ 0.024353] pid_max: default: 32768 minimum: 301
10428 13:33:13.628338 <6>[ 0.029223] LSM: Security Framework initializing
10429 13:33:13.635553 <6>[ 0.034162] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10430 13:33:13.644839 <6>[ 0.041977] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10431 13:33:13.652013 <6>[ 0.051402] cblist_init_generic: Setting adjustable number of callback queues.
10432 13:33:13.658250 <6>[ 0.058846] cblist_init_generic: Setting shift to 3 and lim to 1.
10433 13:33:13.668574 <6>[ 0.065184] cblist_init_generic: Setting adjustable number of callback queues.
10434 13:33:13.675090 <6>[ 0.072610] cblist_init_generic: Setting shift to 3 and lim to 1.
10435 13:33:13.678341 <6>[ 0.079012] rcu: Hierarchical SRCU implementation.
10436 13:33:13.684849 <6>[ 0.084028] rcu: Max phase no-delay instances is 1000.
10437 13:33:13.691463 <6>[ 0.091059] EFI services will not be available.
10438 13:33:13.694651 <6>[ 0.096017] smp: Bringing up secondary CPUs ...
10439 13:33:13.703192 <6>[ 0.101068] Detected VIPT I-cache on CPU1
10440 13:33:13.709603 <6>[ 0.101135] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10441 13:33:13.715799 <6>[ 0.101167] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10442 13:33:13.719070 <6>[ 0.101503] Detected VIPT I-cache on CPU2
10443 13:33:13.725808 <6>[ 0.101553] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10444 13:33:13.736113 <6>[ 0.101569] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10445 13:33:13.739241 <6>[ 0.101824] Detected VIPT I-cache on CPU3
10446 13:33:13.745564 <6>[ 0.101869] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10447 13:33:13.752239 <6>[ 0.101882] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10448 13:33:13.755811 <6>[ 0.102186] CPU features: detected: Spectre-v4
10449 13:33:13.762076 <6>[ 0.102192] CPU features: detected: Spectre-BHB
10450 13:33:13.765658 <6>[ 0.102197] Detected PIPT I-cache on CPU4
10451 13:33:13.772163 <6>[ 0.102256] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10452 13:33:13.778640 <6>[ 0.102273] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10453 13:33:13.785208 <6>[ 0.102565] Detected PIPT I-cache on CPU5
10454 13:33:13.792211 <6>[ 0.102629] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10455 13:33:13.798285 <6>[ 0.102646] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10456 13:33:13.802181 <6>[ 0.102928] Detected PIPT I-cache on CPU6
10457 13:33:13.808623 <6>[ 0.102994] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10458 13:33:13.814983 <6>[ 0.103010] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10459 13:33:13.821610 <6>[ 0.103306] Detected PIPT I-cache on CPU7
10460 13:33:13.828004 <6>[ 0.103372] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10461 13:33:13.834711 <6>[ 0.103388] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10462 13:33:13.838423 <6>[ 0.103436] smp: Brought up 1 node, 8 CPUs
10463 13:33:13.844831 <6>[ 0.244845] SMP: Total of 8 processors activated.
10464 13:33:13.847973 <6>[ 0.249766] CPU features: detected: 32-bit EL0 Support
10465 13:33:13.857777 <6>[ 0.255128] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10466 13:33:13.864796 <6>[ 0.263983] CPU features: detected: Common not Private translations
10467 13:33:13.871307 <6>[ 0.270459] CPU features: detected: CRC32 instructions
10468 13:33:13.877762 <6>[ 0.275810] CPU features: detected: RCpc load-acquire (LDAPR)
10469 13:33:13.880781 <6>[ 0.281770] CPU features: detected: LSE atomic instructions
10470 13:33:13.887761 <6>[ 0.287552] CPU features: detected: Privileged Access Never
10471 13:33:13.893969 <6>[ 0.293367] CPU features: detected: RAS Extension Support
10472 13:33:13.901076 <6>[ 0.299011] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10473 13:33:13.904233 <6>[ 0.306231] CPU: All CPU(s) started at EL2
10474 13:33:13.910508 <6>[ 0.310575] alternatives: applying system-wide alternatives
10475 13:33:13.920757 <6>[ 0.321229] devtmpfs: initialized
10476 13:33:13.936179 <6>[ 0.330179] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10477 13:33:13.942802 <6>[ 0.340141] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10478 13:33:13.949316 <6>[ 0.348390] pinctrl core: initialized pinctrl subsystem
10479 13:33:13.952506 <6>[ 0.355171] DMI not present or invalid.
10480 13:33:13.959016 <6>[ 0.359588] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10481 13:33:13.969194 <6>[ 0.366473] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10482 13:33:13.975572 <6>[ 0.374056] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10483 13:33:13.985504 <6>[ 0.382282] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10484 13:33:13.988977 <6>[ 0.390523] audit: initializing netlink subsys (disabled)
10485 13:33:13.998754 <5>[ 0.396216] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10486 13:33:14.005742 <6>[ 0.396960] thermal_sys: Registered thermal governor 'step_wise'
10487 13:33:14.011939 <6>[ 0.404184] thermal_sys: Registered thermal governor 'power_allocator'
10488 13:33:14.015014 <6>[ 0.410441] cpuidle: using governor menu
10489 13:33:14.022062 <6>[ 0.421403] NET: Registered PF_QIPCRTR protocol family
10490 13:33:14.028465 <6>[ 0.426884] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10491 13:33:14.035517 <6>[ 0.433987] ASID allocator initialised with 32768 entries
10492 13:33:14.038705 <6>[ 0.440609] Serial: AMBA PL011 UART driver
10493 13:33:14.048763 <4>[ 0.449648] Trying to register duplicate clock ID: 134
10494 13:33:14.105491 <6>[ 0.509607] KASLR enabled
10495 13:33:14.119732 <6>[ 0.517391] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10496 13:33:14.126726 <6>[ 0.524405] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10497 13:33:14.133355 <6>[ 0.530893] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10498 13:33:14.139859 <6>[ 0.537900] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10499 13:33:14.146291 <6>[ 0.544389] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10500 13:33:14.152765 <6>[ 0.551393] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10501 13:33:14.159760 <6>[ 0.557881] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10502 13:33:14.165843 <6>[ 0.564884] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10503 13:33:14.169509 <6>[ 0.572384] ACPI: Interpreter disabled.
10504 13:33:14.178059 <6>[ 0.578860] iommu: Default domain type: Translated
10505 13:33:14.184579 <6>[ 0.583971] iommu: DMA domain TLB invalidation policy: strict mode
10506 13:33:14.187832 <5>[ 0.590623] SCSI subsystem initialized
10507 13:33:14.194903 <6>[ 0.594787] usbcore: registered new interface driver usbfs
10508 13:33:14.201329 <6>[ 0.600521] usbcore: registered new interface driver hub
10509 13:33:14.204623 <6>[ 0.606072] usbcore: registered new device driver usb
10510 13:33:14.211514 <6>[ 0.612201] pps_core: LinuxPPS API ver. 1 registered
10511 13:33:14.221264 <6>[ 0.617395] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10512 13:33:14.224520 <6>[ 0.626742] PTP clock support registered
10513 13:33:14.227793 <6>[ 0.630986] EDAC MC: Ver: 3.0.0
10514 13:33:14.235281 <6>[ 0.636178] FPGA manager framework
10515 13:33:14.242115 <6>[ 0.639858] Advanced Linux Sound Architecture Driver Initialized.
10516 13:33:14.245078 <6>[ 0.646633] vgaarb: loaded
10517 13:33:14.252007 <6>[ 0.649793] clocksource: Switched to clocksource arch_sys_counter
10518 13:33:14.254923 <5>[ 0.656218] VFS: Disk quotas dquot_6.6.0
10519 13:33:14.262064 <6>[ 0.660402] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10520 13:33:14.265227 <6>[ 0.667591] pnp: PnP ACPI: disabled
10521 13:33:14.273403 <6>[ 0.674286] NET: Registered PF_INET protocol family
10522 13:33:14.283293 <6>[ 0.679873] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10523 13:33:14.294954 <6>[ 0.692172] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10524 13:33:14.304720 <6>[ 0.700988] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10525 13:33:14.311335 <6>[ 0.708958] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10526 13:33:14.320706 <6>[ 0.717657] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10527 13:33:14.327429 <6>[ 0.727409] TCP: Hash tables configured (established 65536 bind 65536)
10528 13:33:14.334458 <6>[ 0.734268] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10529 13:33:14.343920 <6>[ 0.741466] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10530 13:33:14.351014 <6>[ 0.749163] NET: Registered PF_UNIX/PF_LOCAL protocol family
10531 13:33:14.357122 <6>[ 0.755343] RPC: Registered named UNIX socket transport module.
10532 13:33:14.360565 <6>[ 0.761496] RPC: Registered udp transport module.
10533 13:33:14.366994 <6>[ 0.766428] RPC: Registered tcp transport module.
10534 13:33:14.374105 <6>[ 0.771362] RPC: Registered tcp NFSv4.1 backchannel transport module.
10535 13:33:14.377216 <6>[ 0.778031] PCI: CLS 0 bytes, default 64
10536 13:33:14.380484 <6>[ 0.782429] Unpacking initramfs...
10537 13:33:14.396746 <6>[ 0.794431] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10538 13:33:14.406996 <6>[ 0.803107] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10539 13:33:14.410307 <6>[ 0.811975] kvm [1]: IPA Size Limit: 40 bits
10540 13:33:14.416881 <6>[ 0.816502] kvm [1]: GICv3: no GICV resource entry
10541 13:33:14.420086 <6>[ 0.821523] kvm [1]: disabling GICv2 emulation
10542 13:33:14.426377 <6>[ 0.826210] kvm [1]: GIC system register CPU interface enabled
10543 13:33:14.429575 <6>[ 0.832382] kvm [1]: vgic interrupt IRQ18
10544 13:33:14.436411 <6>[ 0.836741] kvm [1]: VHE mode initialized successfully
10545 13:33:14.442625 <5>[ 0.843141] Initialise system trusted keyrings
10546 13:33:14.449649 <6>[ 0.847964] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10547 13:33:14.457437 <6>[ 0.857965] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10548 13:33:14.463961 <5>[ 0.864392] NFS: Registering the id_resolver key type
10549 13:33:14.467045 <5>[ 0.869692] Key type id_resolver registered
10550 13:33:14.473540 <5>[ 0.874108] Key type id_legacy registered
10551 13:33:14.480420 <6>[ 0.878385] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10552 13:33:14.486888 <6>[ 0.885309] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10553 13:33:14.493688 <6>[ 0.893041] 9p: Installing v9fs 9p2000 file system support
10554 13:33:14.530243 <5>[ 0.931149] Key type asymmetric registered
10555 13:33:14.533449 <5>[ 0.935482] Asymmetric key parser 'x509' registered
10556 13:33:14.543588 <6>[ 0.940644] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10557 13:33:14.546817 <6>[ 0.948278] io scheduler mq-deadline registered
10558 13:33:14.549912 <6>[ 0.953059] io scheduler kyber registered
10559 13:33:14.569512 <6>[ 0.970590] EINJ: ACPI disabled.
10560 13:33:14.602962 <4>[ 0.996897] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10561 13:33:14.612311 <4>[ 1.007544] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10562 13:33:14.627735 <6>[ 1.028496] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10563 13:33:14.636052 <6>[ 1.036525] printk: console [ttyS0] disabled
10564 13:33:14.663968 <6>[ 1.061198] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10565 13:33:14.670232 <6>[ 1.070671] printk: console [ttyS0] enabled
10566 13:33:14.673365 <6>[ 1.070671] printk: console [ttyS0] enabled
10567 13:33:14.679907 <6>[ 1.079563] printk: bootconsole [mtk8250] disabled
10568 13:33:14.683633 <6>[ 1.079563] printk: bootconsole [mtk8250] disabled
10569 13:33:14.689802 <6>[ 1.090857] SuperH (H)SCI(F) driver initialized
10570 13:33:14.693343 <6>[ 1.096148] msm_serial: driver initialized
10571 13:33:14.707843 <6>[ 1.105239] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10572 13:33:14.717731 <6>[ 1.113789] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10573 13:33:14.724386 <6>[ 1.122331] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10574 13:33:14.734138 <6>[ 1.130962] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10575 13:33:14.740834 <6>[ 1.139674] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10576 13:33:14.751218 <6>[ 1.148394] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10577 13:33:14.760737 <6>[ 1.156935] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10578 13:33:14.767665 <6>[ 1.165737] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10579 13:33:14.777719 <6>[ 1.174281] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10580 13:33:14.789184 <6>[ 1.189969] loop: module loaded
10581 13:33:14.795811 <6>[ 1.196060] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10582 13:33:14.818918 <4>[ 1.219509] mtk-pmic-keys: Failed to locate of_node [id: -1]
10583 13:33:14.825272 <6>[ 1.226389] megasas: 07.719.03.00-rc1
10584 13:33:14.835139 <6>[ 1.236054] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10585 13:33:14.844558 <6>[ 1.245173] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10586 13:33:14.861403 <6>[ 1.261890] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10587 13:33:14.918030 <6>[ 1.312153] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10588 13:33:15.978995 <6>[ 2.379864] Freeing initrd memory: 38412K
10589 13:33:15.989447 <6>[ 2.390224] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10590 13:33:16.000585 <6>[ 2.401169] tun: Universal TUN/TAP device driver, 1.6
10591 13:33:16.003798 <6>[ 2.407259] thunder_xcv, ver 1.0
10592 13:33:16.006903 <6>[ 2.410763] thunder_bgx, ver 1.0
10593 13:33:16.010415 <6>[ 2.414257] nicpf, ver 1.0
10594 13:33:16.020466 <6>[ 2.418299] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10595 13:33:16.024326 <6>[ 2.425775] hns3: Copyright (c) 2017 Huawei Corporation.
10596 13:33:16.030755 <6>[ 2.431364] hclge is initializing
10597 13:33:16.034082 <6>[ 2.434943] e1000: Intel(R) PRO/1000 Network Driver
10598 13:33:16.041024 <6>[ 2.440072] e1000: Copyright (c) 1999-2006 Intel Corporation.
10599 13:33:16.044030 <6>[ 2.446083] e1000e: Intel(R) PRO/1000 Network Driver
10600 13:33:16.050882 <6>[ 2.451299] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10601 13:33:16.057222 <6>[ 2.457485] igb: Intel(R) Gigabit Ethernet Network Driver
10602 13:33:16.063717 <6>[ 2.463135] igb: Copyright (c) 2007-2014 Intel Corporation.
10603 13:33:16.070605 <6>[ 2.468970] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10604 13:33:16.077008 <6>[ 2.475489] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10605 13:33:16.080200 <6>[ 2.481959] sky2: driver version 1.30
10606 13:33:16.087097 <6>[ 2.486981] VFIO - User Level meta-driver version: 0.3
10607 13:33:16.094471 <6>[ 2.495274] usbcore: registered new interface driver usb-storage
10608 13:33:16.101277 <6>[ 2.501720] usbcore: registered new device driver onboard-usb-hub
10609 13:33:16.110320 <6>[ 2.510878] mt6397-rtc mt6359-rtc: registered as rtc0
10610 13:33:16.120060 <6>[ 2.516346] mt6397-rtc mt6359-rtc: setting system clock to 2023-09-08T13:33:19 UTC (1694179999)
10611 13:33:16.123052 <6>[ 2.525939] i2c_dev: i2c /dev entries driver
10612 13:33:16.140319 <6>[ 2.537745] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10613 13:33:16.161060 <6>[ 2.561744] cpu cpu0: EM: created perf domain
10614 13:33:16.164241 <6>[ 2.566678] cpu cpu4: EM: created perf domain
10615 13:33:16.171261 <6>[ 2.572288] sdhci: Secure Digital Host Controller Interface driver
10616 13:33:16.178188 <6>[ 2.578722] sdhci: Copyright(c) Pierre Ossman
10617 13:33:16.184768 <6>[ 2.583681] Synopsys Designware Multimedia Card Interface Driver
10618 13:33:16.191211 <6>[ 2.590323] sdhci-pltfm: SDHCI platform and OF driver helper
10619 13:33:16.194305 <6>[ 2.590393] mmc0: CQHCI version 5.10
10620 13:33:16.201146 <6>[ 2.600701] ledtrig-cpu: registered to indicate activity on CPUs
10621 13:33:16.207875 <6>[ 2.607818] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10622 13:33:16.214328 <6>[ 2.614883] usbcore: registered new interface driver usbhid
10623 13:33:16.218138 <6>[ 2.620705] usbhid: USB HID core driver
10624 13:33:16.224461 <6>[ 2.624900] spi_master spi0: will run message pump with realtime priority
10625 13:33:16.271846 <6>[ 2.666057] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10626 13:33:16.291220 <6>[ 2.681649] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10627 13:33:16.294402 <6>[ 2.696612] mmc0: Command Queue Engine enabled
10628 13:33:16.301476 <6>[ 2.696649] cros-ec-spi spi0.0: Chrome EC device registered
10629 13:33:16.307998 <6>[ 2.701368] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10630 13:33:16.314247 <6>[ 2.714430] mmcblk0: mmc0:0001 DA4128 116 GiB
10631 13:33:16.324127 <6>[ 2.720735] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10632 13:33:16.331174 <6>[ 2.724506] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10633 13:33:16.334358 <6>[ 2.731083] NET: Registered PF_PACKET protocol family
10634 13:33:16.340732 <6>[ 2.737269] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10635 13:33:16.344176 <6>[ 2.741357] 9pnet: Installing 9P2000 support
10636 13:33:16.350623 <6>[ 2.747128] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10637 13:33:16.354497 <5>[ 2.751040] Key type dns_resolver registered
10638 13:33:16.360779 <6>[ 2.756870] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10639 13:33:16.367243 <6>[ 2.761316] registered taskstats version 1
10640 13:33:16.370923 <5>[ 2.771650] Loading compiled-in X.509 certificates
10641 13:33:16.398733 <4>[ 2.792707] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10642 13:33:16.408543 <4>[ 2.803407] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10643 13:33:16.415334 <3>[ 2.813937] debugfs: File 'uA_load' in directory '/' already present!
10644 13:33:16.421691 <3>[ 2.820637] debugfs: File 'min_uV' in directory '/' already present!
10645 13:33:16.428164 <3>[ 2.827243] debugfs: File 'max_uV' in directory '/' already present!
10646 13:33:16.434636 <3>[ 2.833947] debugfs: File 'constraint_flags' in directory '/' already present!
10647 13:33:16.446809 <3>[ 2.844680] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10648 13:33:16.460078 <6>[ 2.860796] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10649 13:33:16.467063 <6>[ 2.867649] xhci-mtk 11200000.usb: xHCI Host Controller
10650 13:33:16.473601 <6>[ 2.873153] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10651 13:33:16.483240 <6>[ 2.881030] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10652 13:33:16.490230 <6>[ 2.890489] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10653 13:33:16.497018 <6>[ 2.896714] xhci-mtk 11200000.usb: xHCI Host Controller
10654 13:33:16.503521 <6>[ 2.902218] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10655 13:33:16.509823 <6>[ 2.909873] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10656 13:33:16.516448 <6>[ 2.917719] hub 1-0:1.0: USB hub found
10657 13:33:16.520089 <6>[ 2.921743] hub 1-0:1.0: 1 port detected
10658 13:33:16.530133 <6>[ 2.926039] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10659 13:33:16.533342 <6>[ 2.934757] hub 2-0:1.0: USB hub found
10660 13:33:16.536483 <6>[ 2.938780] hub 2-0:1.0: 1 port detected
10661 13:33:16.544874 <6>[ 2.945740] mtk-msdc 11f70000.mmc: Got CD GPIO
10662 13:33:16.555766 <6>[ 2.953674] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10663 13:33:16.562649 <6>[ 2.961697] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10664 13:33:16.572585 <4>[ 2.969637] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10665 13:33:16.582305 <6>[ 2.979183] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10666 13:33:16.588795 <6>[ 2.987259] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10667 13:33:16.595905 <6>[ 2.995290] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10668 13:33:16.605713 <6>[ 3.003227] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10669 13:33:16.611901 <6>[ 3.011044] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10670 13:33:16.621983 <6>[ 3.018864] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10671 13:33:16.631797 <6>[ 3.029291] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10672 13:33:16.638571 <6>[ 3.037652] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10673 13:33:16.648279 <6>[ 3.045995] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10674 13:33:16.655227 <6>[ 3.054336] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10675 13:33:16.665050 <6>[ 3.062674] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10676 13:33:16.675318 <6>[ 3.071013] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10677 13:33:16.681157 <6>[ 3.079351] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10678 13:33:16.691012 <6>[ 3.087689] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10679 13:33:16.698124 <6>[ 3.096027] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10680 13:33:16.707853 <6>[ 3.104365] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10681 13:33:16.714176 <6>[ 3.112703] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10682 13:33:16.724115 <6>[ 3.121040] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10683 13:33:16.731143 <6>[ 3.129378] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10684 13:33:16.741066 <6>[ 3.137716] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10685 13:33:16.747391 <6>[ 3.146054] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10686 13:33:16.753748 <6>[ 3.154892] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10687 13:33:16.760960 <6>[ 3.162068] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10688 13:33:16.767521 <6>[ 3.168828] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10689 13:33:16.777803 <6>[ 3.175592] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10690 13:33:16.784431 <6>[ 3.182530] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10691 13:33:16.791477 <6>[ 3.189384] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10692 13:33:16.800772 <6>[ 3.198519] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10693 13:33:16.811079 <6>[ 3.207638] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10694 13:33:16.820893 <6>[ 3.216932] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10695 13:33:16.830856 <6>[ 3.226401] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10696 13:33:16.840499 <6>[ 3.235868] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10697 13:33:16.847045 <6>[ 3.245010] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10698 13:33:16.857103 <6>[ 3.254478] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10699 13:33:16.866900 <6>[ 3.263597] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10700 13:33:16.877149 <6>[ 3.272911] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10701 13:33:16.886862 <6>[ 3.283071] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10702 13:33:16.897099 <6>[ 3.294513] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10703 13:33:16.936542 <6>[ 3.334309] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10704 13:33:16.963565 <6>[ 3.364609] hub 2-1:1.0: USB hub found
10705 13:33:16.966712 <6>[ 3.369023] hub 2-1:1.0: 3 ports detected
10706 13:33:17.088242 <6>[ 3.486056] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10707 13:33:17.243327 <6>[ 3.644104] hub 1-1:1.0: USB hub found
10708 13:33:17.246677 <6>[ 3.648631] hub 1-1:1.0: 4 ports detected
10709 13:33:17.320715 <6>[ 3.718376] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10710 13:33:17.568388 <6>[ 3.966168] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10711 13:33:17.700412 <6>[ 4.101357] hub 1-1.4:1.0: USB hub found
10712 13:33:17.703540 <6>[ 4.105967] hub 1-1.4:1.0: 2 ports detected
10713 13:33:18.000468 <6>[ 4.398077] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10714 13:33:18.188093 <6>[ 4.586077] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10715 13:33:29.193875 <6>[ 15.599072] ALSA device list:
10716 13:33:29.200473 <6>[ 15.602361] No soundcards found.
10717 13:33:29.208188 <6>[ 15.610307] Freeing unused kernel memory: 8384K
10718 13:33:29.211794 <6>[ 15.615324] Run /init as init process
10719 13:33:29.261249 <6>[ 15.663289] NET: Registered PF_INET6 protocol family
10720 13:33:29.267774 <6>[ 15.669526] Segment Routing with IPv6
10721 13:33:29.270920 <6>[ 15.673470] In-situ OAM (IOAM) with IPv6
10722 13:33:29.306243 <30>[ 15.688560] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10723 13:33:29.310031 <30>[ 15.712357] systemd[1]: Detected architecture arm64.
10724 13:33:29.310586
10725 13:33:29.316189 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10726 13:33:29.316636
10727 13:33:29.331865 <30>[ 15.734102] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10728 13:33:29.468883 <30>[ 15.867819] systemd[1]: Queued start job for default target Graphical Interface.
10729 13:33:29.516803 <30>[ 15.919008] systemd[1]: Created slice system-getty.slice.
10730 13:33:29.523553 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10731 13:33:29.540420 <30>[ 15.942649] systemd[1]: Created slice system-modprobe.slice.
10732 13:33:29.546998 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10733 13:33:29.564497 <30>[ 15.966873] systemd[1]: Created slice system-serial\x2dgetty.slice.
10734 13:33:29.574678 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10735 13:33:29.589469 <30>[ 15.991623] systemd[1]: Created slice User and Session Slice.
10736 13:33:29.595907 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10737 13:33:29.615579 <30>[ 16.014373] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10738 13:33:29.624752 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10739 13:33:29.644317 <30>[ 16.042850] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10740 13:33:29.650712 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10741 13:33:29.674692 <30>[ 16.070145] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10742 13:33:29.681552 <30>[ 16.082287] systemd[1]: Reached target Local Encrypted Volumes.
10743 13:33:29.687773 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10744 13:33:29.704359 <30>[ 16.106631] systemd[1]: Reached target Paths.
10745 13:33:29.710820 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10746 13:33:29.724296 <30>[ 16.126065] systemd[1]: Reached target Remote File Systems.
10747 13:33:29.730759 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10748 13:33:29.744293 <30>[ 16.146051] systemd[1]: Reached target Slices.
10749 13:33:29.747480 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10750 13:33:29.764060 <30>[ 16.166097] systemd[1]: Reached target Swap.
10751 13:33:29.767529 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10752 13:33:29.787881 <30>[ 16.186604] systemd[1]: Listening on initctl Compatibility Named Pipe.
10753 13:33:29.794132 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10754 13:33:29.800929 <30>[ 16.201749] systemd[1]: Listening on Journal Audit Socket.
10755 13:33:29.807607 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10756 13:33:29.820928 <30>[ 16.222559] systemd[1]: Listening on Journal Socket (/dev/log).
10757 13:33:29.827350 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10758 13:33:29.845630 <30>[ 16.247315] systemd[1]: Listening on Journal Socket.
10759 13:33:29.852010 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10760 13:33:29.867848 <30>[ 16.266773] systemd[1]: Listening on Network Service Netlink Socket.
10761 13:33:29.874785 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10762 13:33:29.889159 <30>[ 16.291306] systemd[1]: Listening on udev Control Socket.
10763 13:33:29.895621 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10764 13:33:29.913224 <30>[ 16.315164] systemd[1]: Listening on udev Kernel Socket.
10765 13:33:29.919666 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10766 13:33:29.959909 <30>[ 16.362243] systemd[1]: Mounting Huge Pages File System...
10767 13:33:29.966453 Mounting [0;1;39mHuge Pages File System[0m...
10768 13:33:29.982746 <30>[ 16.384598] systemd[1]: Mounting POSIX Message Queue File System...
10769 13:33:29.989461 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10770 13:33:30.040107 <30>[ 16.442195] systemd[1]: Mounting Kernel Debug File System...
10771 13:33:30.046787 Mounting [0;1;39mKernel Debug File System[0m...
10772 13:33:30.063702 <30>[ 16.462579] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10773 13:33:30.076731 <30>[ 16.475532] systemd[1]: Starting Create list of static device nodes for the current kernel...
10774 13:33:30.083232 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10775 13:33:30.119940 <30>[ 16.522329] systemd[1]: Starting Load Kernel Module configfs...
10776 13:33:30.126304 Starting [0;1;39mLoad Kernel Module configfs[0m...
10777 13:33:30.148019 <30>[ 16.550416] systemd[1]: Starting Load Kernel Module drm...
10778 13:33:30.154969 Starting [0;1;39mLoad Kernel Module drm[0m...
10779 13:33:30.175096 <30>[ 16.574458] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10780 13:33:30.189922 <30>[ 16.592217] systemd[1]: Starting Journal Service...
10781 13:33:30.193107 Starting [0;1;39mJournal Service[0m...
10782 13:33:30.224278 <30>[ 16.626652] systemd[1]: Starting Load Kernel Modules...
10783 13:33:30.230859 Starting [0;1;39mLoad Kernel Modules[0m...
10784 13:33:30.255693 <30>[ 16.654417] systemd[1]: Starting Remount Root and Kernel File Systems...
10785 13:33:30.261929 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10786 13:33:30.278727 <30>[ 16.681230] systemd[1]: Starting Coldplug All udev Devices...
10787 13:33:30.285444 Starting [0;1;39mColdplug All udev Devices[0m...
10788 13:33:30.302621 <30>[ 16.704937] systemd[1]: Started Journal Service.
10789 13:33:30.309278 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10790 13:33:30.325522 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10791 13:33:30.340381 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10792 13:33:30.356800 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10793 13:33:30.376955 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10794 13:33:30.394247 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10795 13:33:30.413081 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10796 13:33:30.430003 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10797 13:33:30.450008 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10798 13:33:30.464070 See 'systemctl status systemd-remount-fs.service' for details.
10799 13:33:30.522191 Mounting [0;1;39mKernel Configuration File System[0m...
10800 13:33:30.538993 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10801 13:33:30.552797 <46>[ 16.951419] systemd-journald[185]: Received client request to flush runtime journal.
10802 13:33:30.563460 Starting [0;1;39mLoad/Save Random Seed[0m...
10803 13:33:30.587553 Starting [0;1;39mApply Kernel Variables[0m...
10804 13:33:30.613683 Starting [0;1;39mCreate System Users[0m...
10805 13:33:30.637893 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10806 13:33:30.656914 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10807 13:33:30.677443 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10808 13:33:30.689664 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10809 13:33:30.705638 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10810 13:33:30.721853 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10811 13:33:30.760574 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10812 13:33:30.782947 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10813 13:33:30.796667 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10814 13:33:30.811499 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10815 13:33:30.857361 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10816 13:33:30.881276 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10817 13:33:30.900658 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10818 13:33:30.923750 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10819 13:33:30.984567 Starting [0;1;39mNetwork Service[0m...
10820 13:33:31.007317 Starting [0;1;39mNetwork Time Synchronization[0m...
10821 13:33:31.032951 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10822 13:33:31.081537 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10823 13:33:31.096560 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10824 13:33:31.110545 <3>[ 17.509676] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10825 13:33:31.117393 <6>[ 17.510031] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10826 13:33:31.127598 <3>[ 17.518021] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10827 13:33:31.133885 <6>[ 17.525633] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10828 13:33:31.143507 <3>[ 17.533442] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10829 13:33:31.150580 <6>[ 17.550548] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10830 13:33:31.160053 <3>[ 17.551700] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10831 13:33:31.166868 <3>[ 17.567367] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10832 13:33:31.177092 <6>[ 17.575038] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10833 13:33:31.183573 <3>[ 17.575559] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10834 13:33:31.189802 [[0;32m OK [<6>[ 17.586272] remoteproc remoteproc0: scp is available
10835 13:33:31.196440 <3>[ 17.590901] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10836 13:33:31.203083 0m] Found device<6>[ 17.598319] remoteproc remoteproc0: powering up scp
10837 13:33:31.209700 <6>[ 17.602767] mc: Linux media interface: v0.10
10838 13:33:31.219937 [0;1;39m/dev/t<3>[ 17.605847] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10839 13:33:31.220387 tyS0[0m.
10840 13:33:31.229626 <6>[ 17.612300] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10841 13:33:31.236758 <6>[ 17.614775] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10842 13:33:31.243201 <3>[ 17.620279] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10843 13:33:31.249521 <6>[ 17.625585] videodev: Linux video capture interface: v2.00
10844 13:33:31.255990 <6>[ 17.626313] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10845 13:33:31.262229 <3>[ 17.649506] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10846 13:33:31.272426 <4>[ 17.662760] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10847 13:33:31.275627 <4>[ 17.662760] Fallback method does not support PEC.
10848 13:33:31.285227 <3>[ 17.671009] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10849 13:33:31.292235 <4>[ 17.678458] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10850 13:33:31.299050 <4>[ 17.678779] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10851 13:33:31.306121 <6>[ 17.689284] usbcore: registered new interface driver r8152
10852 13:33:31.312599 <3>[ 17.692753] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10853 13:33:31.323304 <3>[ 17.694307] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10854 13:33:31.329763 <6>[ 17.695569] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10855 13:33:31.336232 <6>[ 17.695583] pci_bus 0000:00: root bus resource [bus 00-ff]
10856 13:33:31.342647 <6>[ 17.695591] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10857 13:33:31.352383 <6>[ 17.695597] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10858 13:33:31.359449 <6>[ 17.695640] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10859 13:33:31.365747 <6>[ 17.695664] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10860 13:33:31.368997 <6>[ 17.695755] pci 0000:00:00.0: supports D1 D2
10861 13:33:31.375947 <6>[ 17.695759] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10862 13:33:31.386312 <3>[ 17.710069] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10863 13:33:31.392686 <6>[ 17.710554] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10864 13:33:31.399945 <6>[ 17.710714] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10865 13:33:31.409408 <6>[ 17.710742] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10866 13:33:31.416001 <6>[ 17.710759] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10867 13:33:31.422718 <6>[ 17.710774] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10868 13:33:31.429588 <6>[ 17.710893] pci 0000:01:00.0: supports D1 D2
10869 13:33:31.436243 <6>[ 17.710896] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10870 13:33:31.443260 <3>[ 17.713245] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10871 13:33:31.449748 <3>[ 17.713262] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10872 13:33:31.459450 <3>[ 17.713279] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10873 13:33:31.466333 <3>[ 17.713283] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10874 13:33:31.476792 <3>[ 17.713404] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10875 13:33:31.483915 <6>[ 17.722177] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10876 13:33:31.493979 <6>[ 17.762291] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10877 13:33:31.500153 <6>[ 17.765816] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10878 13:33:31.510511 <6>[ 17.773572] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10879 13:33:31.516817 <6>[ 17.777668] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10880 13:33:31.526516 <6>[ 17.777679] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10881 13:33:31.533585 <6>[ 17.777692] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10882 13:33:31.539953 <6>[ 17.777705] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10883 13:33:31.549415 <6>[ 17.784613] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10884 13:33:31.555881 <6>[ 17.784653] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10885 13:33:31.562479 <6>[ 17.784663] remoteproc remoteproc0: remote processor scp is now up
10886 13:33:31.569548 <6>[ 17.793337] pci 0000:00:00.0: PCI bridge to [bus 01]
10887 13:33:31.575822 <6>[ 17.793342] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10888 13:33:31.582634 <6>[ 17.793556] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10889 13:33:31.589744 <6>[ 17.801675] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10890 13:33:31.596068 <6>[ 17.808611] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10891 13:33:31.602554 <6>[ 17.809616] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10892 13:33:31.613317 <6>[ 17.811717] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10893 13:33:31.623621 <6>[ 17.812473] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10894 13:33:31.626727 <6>[ 17.832151] usbcore: registered new interface driver cdc_ether
10895 13:33:31.633417 <6>[ 17.835840] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10896 13:33:31.636571 <6>[ 17.836222] Bluetooth: Core ver 2.22
10897 13:33:31.643910 <6>[ 17.836348] NET: Registered PF_BLUETOOTH protocol family
10898 13:33:31.650935 <6>[ 17.836352] Bluetooth: HCI device and connection manager initialized
10899 13:33:31.654212 <6>[ 17.836368] Bluetooth: HCI socket layer initialized
10900 13:33:31.660742 <6>[ 17.836376] Bluetooth: L2CAP socket layer initialized
10901 13:33:31.664044 <6>[ 17.836392] Bluetooth: SCO socket layer initialized
10902 13:33:31.673711 <4>[ 17.849172] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10903 13:33:31.680310 <6>[ 17.867284] usbcore: registered new interface driver r8153_ecm
10904 13:33:31.687099 <5>[ 17.868927] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10905 13:33:31.696913 <4>[ 17.874548] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10906 13:33:31.706581 <3>[ 17.877845] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10907 13:33:31.713456 <5>[ 17.878008] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10908 13:33:31.720112 <4>[ 17.878065] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10909 13:33:31.726459 <6>[ 17.878068] cfg80211: failed to load regulatory.db
10910 13:33:31.733606 <3>[ 17.878626] power_supply sbs-5-000b: driver failed to report `capacity_level' property: -6
10911 13:33:31.742874 <6>[ 17.882930] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10912 13:33:31.746575 <6>[ 17.889184] usbcore: registered new interface driver btusb
10913 13:33:31.756569 <4>[ 17.889572] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10914 13:33:31.770714 <6>[ 17.902214] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10915 13:33:31.777135 <3>[ 17.907707] Bluetooth: hci0: Failed to load firmware file (-2)
10916 13:33:31.783713 <6>[ 17.917022] usbcore: registered new interface driver uvcvideo
10917 13:33:31.790306 <6>[ 17.918196] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10918 13:33:31.793576 <3>[ 17.924882] Bluetooth: hci0: Failed to set up firmware (-2)
10919 13:33:31.800339 <6>[ 17.942201] r8152 2-1.3:1.0 eth0: v1.12.13
10920 13:33:31.810267 <4>[ 17.948744] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10921 13:33:31.816556 <6>[ 17.971865] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10922 13:33:31.823530 <6>[ 17.983899] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10923 13:33:31.833180 <3>[ 17.992859] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10924 13:33:31.836337 <6>[ 17.997550] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10925 13:33:31.846485 <3>[ 18.003998] power_supply sbs-5-000b: driver failed to report `voltage_now' property: -6
10926 13:33:31.856589 <3>[ 18.021708] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 13:33:31.859546 <6>[ 18.029836] mt7921e 0000:01:00.0: ASIC revision: 79610010
10928 13:33:31.869412 <3>[ 18.056941] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 13:33:31.879563 <4>[ 18.149033] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10930 13:33:31.889360 <3>[ 18.170829] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 13:33:31.899630 <4>[ 18.283381] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10932 13:33:31.909942 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10933 13:33:31.919508 <3>[ 18.317693] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10934 13:33:31.951199 <3>[ 18.350500] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 13:33:32.020182 <4>[ 18.416179] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10936 13:33:32.049371 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10937 13:33:32.067733 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10938 13:33:32.087724 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10939 13:33:32.103279 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10940 13:33:32.124754 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10941 13:33:32.134253 <4>[ 18.532376] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10942 13:33:32.184030 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10943 13:33:32.212041 Starting [0;1;39mNetwork Name Resolution[0m...
10944 13:33:32.233626 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10945 13:33:32.256905 [[0;32m OK [<4>[ 18.653711] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10946 13:33:32.263267 0m] Reached target [0;1;39mSystem Initialization[0m.
10947 13:33:32.285321 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10948 13:33:32.302938 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10949 13:33:32.315295 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10950 13:33:32.335304 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10951 13:33:32.347546 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10952 13:33:32.365982 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10953 13:33:32.380326 <4>[ 18.776432] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10954 13:33:32.420767 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10955 13:33:32.453597 Starting [0;1;39mUser Login Management[0m...
10956 13:33:32.472425 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10957 13:33:32.503557 [[0;32m OK [0m] Started [0;<4>[ 18.898142] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10958 13:33:32.506521 1;39mNetwork Name Resolution[0m.
10959 13:33:32.528568 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10960 13:33:32.543999 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10961 13:33:32.562562 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10962 13:33:32.600487 Starting [0;1;39mPermit User Sessions[0m...
10963 13:33:32.628853 [[0;32m OK [<4>[ 19.025644] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10964 13:33:32.635307 0m] Finished [0;1;39mPermit User Sessions[0m.
10965 13:33:32.642933 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10966 13:33:32.655065 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10967 13:33:32.673657 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10968 13:33:32.692553 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10969 13:33:32.707779 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10970 13:33:32.724067 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10971 13:33:32.748296 <4>[ 19.144353] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10972 13:33:32.784840 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10973 13:33:32.823441 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10974 13:33:32.837580
10975 13:33:32.837684
10976 13:33:32.840816 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10977 13:33:32.840896
10978 13:33:32.843954 debian-bullseye-arm64 login: root (automatic login)
10979 13:33:32.844034
10980 13:33:32.844097
10981 13:33:32.868604 Linux debian-bul<4>[ 19.265562] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10982 13:33:32.875845 lseye-arm64 6.1.52-cip5 #1 SMP PREEMPT Fri Sep 8 13:10:51 UTC 2023 aarch64
10983 13:33:32.875929
10984 13:33:32.881846 The programs included with the Debian GNU/Linux system are free software;
10985 13:33:32.889003 the exact distribution terms for each program are described in the
10986 13:33:32.895348 individual files in /usr/share/doc/*/copyright.
10987 13:33:32.895466
10988 13:33:32.898586 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10989 13:33:32.901760 permitted by applicable law.
10990 13:33:32.902097 Matched prompt #10: / #
10992 13:33:32.902295 Setting prompt string to ['/ #']
10993 13:33:32.902384 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10995 13:33:32.902572 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10996 13:33:32.902655 start: 2.2.6 expect-shell-connection (timeout 00:02:57) [common]
10997 13:33:32.902723 Setting prompt string to ['/ #']
10998 13:33:32.902781 Forcing a shell prompt, looking for ['/ #']
11000 13:33:32.952988 / #
11001 13:33:32.953107 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11002 13:33:32.953186 Waiting using forced prompt support (timeout 00:02:30)
11003 13:33:32.958295
11004 13:33:32.958563 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11005 13:33:32.958652 start: 2.2.7 export-device-env (timeout 00:02:57) [common]
11006 13:33:32.958747 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11007 13:33:32.958832 end: 2.2 depthcharge-retry (duration 00:02:03) [common]
11008 13:33:32.958912 end: 2 depthcharge-action (duration 00:02:03) [common]
11009 13:33:32.958996 start: 3 lava-test-retry (timeout 00:07:36) [common]
11010 13:33:32.959080 start: 3.1 lava-test-shell (timeout 00:07:36) [common]
11011 13:33:32.959150 Using namespace: common
11013 13:33:33.059454 / # #
11014 13:33:33.059608 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11015 13:33:33.059745 <3>[ 19.386234] mt7921e 0000:01:00.0: hardware init failed
11016 13:33:33.064655 #
11017 13:33:33.064967 Using /lava-11471202
11019 13:33:33.165325 / # export SHELL=/bin/sh
11020 13:33:33.170506 export SHELL=/bin/sh
11022 13:33:33.271018 / # . /lava-11471202/environment
11023 13:33:33.271223 <6>[ 19.592927] IPv6: ADDRCONF(NETDEV_CHANGE): enx0024323078ff: link becomes ready
11024 13:33:33.271308 <6>[ 19.600971] r8152 2-1.3:1.0 enx0024323078ff: carrier on
11025 13:33:33.276436 . /lava-11471202/environment
11027 13:33:33.377921 / # /lava-11471202/bin/lava-test-runner /lava-11471202/0
11028 13:33:33.378649 Test shell timeout: 10s (minimum of the action and connection timeout)
11029 13:33:33.384441 /lava-11471202/bin/lava-test-runner /lava-11471202/0
11030 13:33:33.405013 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11031 13:33:33.411641 + cd /lava-11471202/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11032 13:33:33.412169 + cat uuid
11033 13:33:33.414824 + UUID=11471202_1.5.2.3.1
11034 13:33:33.415444 + set +x
11035 13:33:33.421610 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 11471202_1.5.2.3.1>
11036 13:33:33.422352 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 11471202_1.5.2.3.1
11037 13:33:33.422728 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (11471202_1.5.2.3.1)
11038 13:33:33.423141 Skipping test definition patterns.
11039 13:33:33.424981 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11040 13:33:33.428695 Received signal: <TESTCASE> TEST_CASE_ID=device-presence<4
11041 13:33:33.429205 Test case results without result (probably a sign of an incorrect parsing pattern being used): {'test_case_id': 'device-presence<4', 'result': 'unknown'}
11042 13:33:33.438400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence<4>[ 19.836658] use of bytesused == 0 is deprecated and will be removed in the future,
11043 13:33:33.441649 <4>[ 19.844644] use the actual size instead.
11044 13:33:33.442077 RESULT=pass>
11045 13:33:33.448175 device: /dev/vide<4>[ 19.850831] ------------[ cut here ]------------
11046 13:33:33.448624 o2
11047 13:33:33.454595 <4>[ 19.856549] get_vaddr_frames() cannot follow VM_IO mapping
11048 13:33:33.467986 <4>[ 19.856685] WARNING: CPU: 5 PID: 315 at drivers/media/common/videobuf2/frame_vector.c:59 get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11049 13:33:33.517821 <4>[ 19.874956] Modules linked in: mt7921e mt7921_common mt76_connac_lib mt76 mac80211 mtk_vcodec_enc mtk_vcodec_common libarc4 mtk_vpu btusb uvcvideo v4l2_mem2mem btintel cfg80211 videobuf2_vmalloc videobuf2_dma_contig btmtk r8153_ecm btrtl btbcm videobuf2_memops videobuf2_v4l2 bluetooth cdc_ether videobuf2_common usbnet cros_ec_rpmsg r8152 elants_i2c crct10dif_ce ecdh_generic videodev ecc mc rfkill elan_i2c sbs_battery cros_ec_chardev mtk_scp hid_google_hammer mtk_rpmsg hid_vivaldi_common cros_ec_typec mtk_scp_ipi pcie_mediatek_gen3 ip_tables x_tables ipv6
11050 13:33:33.524441 <4>[ 19.924305] CPU: 5 PID: 315 Comm: v4l2-compliance Not tainted 6.1.52-cip5 #1
11051 13:33:33.530963 <4>[ 19.931602] Hardware name: Google Spherion (rev0 - 3) (DT)
11052 13:33:33.537530 <4>[ 19.937334] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
11053 13:33:33.544115 <4>[ 19.944543] pc : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11054 13:33:33.550917 <4>[ 19.950629] lr : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11055 13:33:33.554358 <4>[ 19.956716] sp : ffff800009193850
11056 13:33:33.560352 <4>[ 19.960278] x29: ffff800009193850 x28: ffffc4e6261cc000 x27: ffffc4e6261c8238
11057 13:33:33.567483 <4>[ 19.967662] x26: 0000000000000000 x25: ffffc4e67922cbe0 x24: ffff44878e811298
11058 13:33:33.573569 <4>[ 19.975044] x23: ffff44878a089c00 x22: ffff448780d48410 x21: 0000000000000000
11059 13:33:33.583911 <4>[ 19.982427] x20: 00000000fffffff2 x19: ffff44878d9e6180 x18: fffffffffffe9768
11060 13:33:33.590142 <4>[ 19.989810] x17: 0000000000000000 x16: ffffc4e67708bb90 x15: 0000000000000038
11061 13:33:33.596729 <4>[ 19.997193] x14: ffffc4e679b134a8 x13: 000000000000064e x12: 000000000000021a
11062 13:33:33.603801 <4>[ 20.004576] x11: fffffffffffe9768 x10: fffffffffffe9730 x9 : 00000000fffff21a
11063 13:33:33.613192 <4>[ 20.011959] x8 : ffffc4e679b134a8 x7 : ffffc4e679b6b4a8 x6 : 0000000000001938
11064 13:33:33.620050 <4>[ 20.019341] x5 : ffff4488bef7ea18 x4 : 00000000fffff21a x3 : ffff7fa245b2b000
11065 13:33:33.626591 <4>[ 20.026724] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff44878aa62c40
11066 13:33:33.629808 <4>[ 20.034107] Call trace:
11067 13:33:33.636486 <4>[ 20.036802] get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11068 13:33:33.640221 <4>[ 20.042541] vb2_create_framevec+0x50/0xac [videobuf2_memops]
11069 13:33:33.646578 <4>[ 20.048540] vb2_dc_get_userptr+0x9c/0x310 [videobuf2_dma_contig]
11070 13:33:33.652999 <4>[ 20.054887] __prepare_userptr+0x280/0x410 [videobuf2_common]
11071 13:33:33.659998 <4>[ 20.060887] __buf_prepare+0x1a0/0x244 [videobuf2_common]
11072 13:33:33.666277 <4>[ 20.066540] vb2_core_prepare_buf+0x3c/0x140 [videobuf2_common]
11073 13:33:33.669545 <4>[ 20.072713] vb2_prepare_buf+0x68/0xc0 [videobuf2_v4l2]
11074 13:33:33.676151 <4>[ 20.078200] v4l2_m2m_prepare_buf+0x40/0x90 [v4l2_mem2mem]
11075 13:33:33.683104 <4>[ 20.083953] v4l2_m2m_ioctl_prepare_buf+0x18/0x24 [v4l2_mem2mem]
11076 13:33:33.686386 <4>[ 20.090213] v4l_prepare_buf+0x48/0x60 [videodev]
11077 13:33:33.692878 <4>[ 20.095228] __video_do_ioctl+0x184/0x3d0 [videodev]
11078 13:33:33.699655 <4>[ 20.100457] video_usercopy+0x358/0x680 [videodev]
11079 13:33:33.702846 <4>[ 20.105512] video_ioctl2+0x18/0x30 [videodev]
11080 13:33:33.706141 <4>[ 20.110220] v4l2_ioctl+0x40/0x60 [videodev]
11081 13:33:33.712608 <4>[ 20.114755] __arm64_sys_ioctl+0xa8/0xf0
11082 13:33:33.715960 <4>[ 20.118933] invoke_syscall+0x48/0x114
11083 13:33:33.719557 <4>[ 20.122936] el0_svc_common.constprop.0+0x44/0xec
11084 13:33:33.722543 <4>[ 20.127889] do_el0_svc+0x2c/0xd0
11085 13:33:33.725646 <4>[ 20.131453] el0_svc+0x2c/0x84
11086 13:33:33.732260 <4>[ 20.134758] el0t_64_sync_handler+0xb8/0xc0
11087 13:33:33.735557 <4>[ 20.139189] el0t_64_sync+0x18c/0x190
11088 13:33:33.738767 <4>[ 20.143101] ---[ end trace 0000000000000000 ]---
11089 13:33:33.752797 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11090 13:33:33.763142 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
11091 13:33:33.769612
11092 13:33:33.788200 Compliance test for mtk-vcodec-enc device /dev/video2:
11093 13:33:33.795582
11094 13:33:33.805633 Driver Info:
11095 13:33:33.819193 Driver name : mtk-vcodec-enc
11096 13:33:33.832727 Card type : MT8192 video encoder
11097 13:33:33.845245 Bus info : platform:17020000.vcodec
11098 13:33:33.853558 Driver version : 6.1.52
11099 13:33:33.868213 Capabilities : 0x84204000
11100 13:33:33.879874 Video Memory-to-Memory Multiplanar
11101 13:33:33.893022 Streaming
11102 13:33:33.902613 Extended Pix Format
11103 13:33:33.913949 Device Capabilities
11104 13:33:33.928721 Device Caps : 0x04204000
11105 13:33:33.941244 Video Memory-to-Memory Multiplanar
11106 13:33:33.953662 Streaming
11107 13:33:33.967141 Extended Pix Format
11108 13:33:33.977794 Detected Stateful Encoder
11109 13:33:33.992075
11110 13:33:34.003158 Required ioctls:
11111 13:33:34.020671 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11112 13:33:34.021113 test VIDIOC_QUERYCAP: OK
11113 13:33:34.021768 Received signal: <TESTSET> START Required-ioctls
11114 13:33:34.022150 Starting test_set Required-ioctls
11115 13:33:34.045634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11116 13:33:34.046488 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11118 13:33:34.049203 test invalid ioctls: OK
11119 13:33:34.071317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11120 13:33:34.071450
11121 13:33:34.071696 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11123 13:33:34.083079 Allow for multiple opens:
11124 13:33:34.090478 <LAVA_SIGNAL_TESTSET STOP>
11125 13:33:34.090761 Received signal: <TESTSET> STOP
11126 13:33:34.090862 Closing test_set Required-ioctls
11127 13:33:34.099555 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11128 13:33:34.099809 Received signal: <TESTSET> START Allow-for-multiple-opens
11129 13:33:34.099878 Starting test_set Allow-for-multiple-opens
11130 13:33:34.102826 test second /dev/video2 open: OK
11131 13:33:34.124829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11132 13:33:34.125087 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11134 13:33:34.128032 test VIDIOC_QUERYCAP: OK
11135 13:33:34.150061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11136 13:33:34.150378 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11138 13:33:34.153782 test VIDIOC_G/S_PRIORITY: OK
11139 13:33:34.175327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11140 13:33:34.175887 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11142 13:33:34.178832 test for unlimited opens: OK
11143 13:33:34.202683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11144 13:33:34.203271
11145 13:33:34.204124 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11147 13:33:34.213619 Debug ioctls:
11148 13:33:34.221467 <LAVA_SIGNAL_TESTSET STOP>
11149 13:33:34.222262 Received signal: <TESTSET> STOP
11150 13:33:34.222751 Closing test_set Allow-for-multiple-opens
11151 13:33:34.232967 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11152 13:33:34.233772 Received signal: <TESTSET> START Debug-ioctls
11153 13:33:34.234252 Starting test_set Debug-ioctls
11154 13:33:34.239835 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11155 13:33:34.260502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11156 13:33:34.261132 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11158 13:33:34.266947 test VIDIOC_LOG_STATUS: OK (Not Supported)
11159 13:33:34.285232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11160 13:33:34.285613
11161 13:33:34.286156 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11163 13:33:34.294879 Input ioctls:
11164 13:33:34.301956 <LAVA_SIGNAL_TESTSET STOP>
11165 13:33:34.302572 Received signal: <TESTSET> STOP
11166 13:33:34.302888 Closing test_set Debug-ioctls
11167 13:33:34.311603 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11168 13:33:34.312290 Received signal: <TESTSET> START Input-ioctls
11169 13:33:34.312625 Starting test_set Input-ioctls
11170 13:33:34.314855 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11171 13:33:34.340253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11172 13:33:34.341077 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11174 13:33:34.343464 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11175 13:33:34.361843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11176 13:33:34.362605 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11178 13:33:34.368484 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11179 13:33:34.385192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11180 13:33:34.386087 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11182 13:33:34.391923 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11183 13:33:34.411448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11184 13:33:34.412261 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11186 13:33:34.415070 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11187 13:33:34.435969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11188 13:33:34.436851 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11190 13:33:34.439353 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11191 13:33:34.462208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11192 13:33:34.463100 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11194 13:33:34.465468 Inputs: 0 Audio Inputs: 0 Tuners: 0
11195 13:33:34.471656
11196 13:33:34.488555 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11197 13:33:34.509827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11198 13:33:34.510514 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11200 13:33:34.516249 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11201 13:33:34.534689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11202 13:33:34.535426 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11204 13:33:34.540692 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11205 13:33:34.558500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11206 13:33:34.559411 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11208 13:33:34.565069 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11209 13:33:34.588224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11210 13:33:34.589207 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11212 13:33:34.594485 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11213 13:33:34.613006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11214 13:33:34.613644
11215 13:33:34.614469 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11217 13:33:34.634438 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11218 13:33:34.659311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11219 13:33:34.660172 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11221 13:33:34.665829 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11222 13:33:34.686412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11223 13:33:34.687156 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11225 13:33:34.689742 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11226 13:33:34.714202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11227 13:33:34.714883 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11229 13:33:34.717214 test VIDIOC_G/S_EDID: OK (Not Supported)
11230 13:33:34.738637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11231 13:33:34.739197
11232 13:33:34.739961 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11234 13:33:34.749837 Control ioctls:
11235 13:33:34.756502 <LAVA_SIGNAL_TESTSET STOP>
11236 13:33:34.757244 Received signal: <TESTSET> STOP
11237 13:33:34.757734 Closing test_set Input-ioctls
11238 13:33:34.766987 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11239 13:33:34.767972 Received signal: <TESTSET> START Control-ioctls
11240 13:33:34.768473 Starting test_set Control-ioctls
11241 13:33:34.770068 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11242 13:33:34.795797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11243 13:33:34.796262 test VIDIOC_QUERYCTRL: OK
11244 13:33:34.796889 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11246 13:33:34.818306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11247 13:33:34.818996 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11249 13:33:34.821553 test VIDIOC_G/S_CTRL: OK
11250 13:33:34.841596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11251 13:33:34.842286 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11253 13:33:34.844941 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11254 13:33:34.866061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11255 13:33:34.866841 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11257 13:33:34.875709 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11258 13:33:34.879034 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11259 13:33:34.905462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11260 13:33:34.905952 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11262 13:33:34.909050 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11263 13:33:34.926054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11264 13:33:34.926455 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11266 13:33:34.929307 Standard Controls: 16 Private Controls: 0
11267 13:33:34.940012
11268 13:33:34.952241 Format ioctls:
11269 13:33:34.958817 <LAVA_SIGNAL_TESTSET STOP>
11270 13:33:34.959620 Received signal: <TESTSET> STOP
11271 13:33:34.960019 Closing test_set Control-ioctls
11272 13:33:34.967291 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11273 13:33:34.968086 Received signal: <TESTSET> START Format-ioctls
11274 13:33:34.968532 Starting test_set Format-ioctls
11275 13:33:34.970575 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11276 13:33:34.996400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11277 13:33:34.997095 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11279 13:33:34.999834 test VIDIOC_G/S_PARM: OK
11280 13:33:35.017606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11281 13:33:35.018328 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11283 13:33:35.021293 test VIDIOC_G_FBUF: OK (Not Supported)
11284 13:33:35.042229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11285 13:33:35.043119 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11287 13:33:35.045265 test VIDIOC_G_FMT: OK
11288 13:33:35.088507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11289 13:33:35.089088 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11291 13:33:35.091880 test VIDIOC_TRY_FMT: OK
11292 13:33:35.115290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11293 13:33:35.115889 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11295 13:33:35.125000 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11296 13:33:35.128129 test VIDIOC_S_FMT: FAIL
11297 13:33:35.155577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11298 13:33:35.156165 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11300 13:33:35.159023 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11301 13:33:35.183835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11302 13:33:35.184117 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11304 13:33:35.186998 test Cropping: OK
11305 13:33:35.206722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11306 13:33:35.207034 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11308 13:33:35.210119 test Composing: OK (Not Supported)
11309 13:33:35.233014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11310 13:33:35.233340 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11312 13:33:35.236224 test Scaling: OK (Not Supported)
11313 13:33:35.257464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11314 13:33:35.257574
11315 13:33:35.257816 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11317 13:33:35.268665 Codec ioctls:
11318 13:33:35.275042 <LAVA_SIGNAL_TESTSET STOP>
11319 13:33:35.275335 Received signal: <TESTSET> STOP
11320 13:33:35.275443 Closing test_set Format-ioctls
11321 13:33:35.284312 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11322 13:33:35.284600 Received signal: <TESTSET> START Codec-ioctls
11323 13:33:35.284684 Starting test_set Codec-ioctls
11324 13:33:35.287867 test VIDIOC_(TRY_)ENCODER_CMD: OK
11325 13:33:35.309177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11326 13:33:35.309454 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11328 13:33:35.325946 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11329 13:33:35.350649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11330 13:33:35.350948 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11332 13:33:35.356918 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11333 13:33:35.377298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11334 13:33:35.377397
11335 13:33:35.377639 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11337 13:33:35.390071 Buffer ioctls:
11338 13:33:35.399920 <LAVA_SIGNAL_TESTSET STOP>
11339 13:33:35.400190 Received signal: <TESTSET> STOP
11340 13:33:35.400273 Closing test_set Codec-ioctls
11341 13:33:35.410200 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11342 13:33:35.410465 Received signal: <TESTSET> START Buffer-ioctls
11343 13:33:35.410538 Starting test_set Buffer-ioctls
11344 13:33:35.413468 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11345 13:33:35.436517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11346 13:33:35.436645 test VIDIOC_EXPBUF: OK
11347 13:33:35.436921 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11349 13:33:35.458564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11350 13:33:35.458849 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11352 13:33:35.461741 test Requests: OK (Not Supported)
11353 13:33:35.481476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11354 13:33:35.481590
11355 13:33:35.481868 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11357 13:33:35.492133 Test input 0:
11358 13:33:35.502439
11359 13:33:35.513135 Streaming ioctls:
11360 13:33:35.519825 <LAVA_SIGNAL_TESTSET STOP>
11361 13:33:35.520089 Received signal: <TESTSET> STOP
11362 13:33:35.520163 Closing test_set Buffer-ioctls
11363 13:33:35.530008 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11364 13:33:35.530267 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11365 13:33:35.530348 Starting test_set Streaming-ioctls_Test-input-0
11366 13:33:35.533026 test read/write: OK (Not Supported)
11367 13:33:35.554067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11368 13:33:35.554338 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11370 13:33:35.561111 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2798): node->streamon(q.g_type())
11371 13:33:35.571266 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2845): testBlockingDQBuf(node, q)
11372 13:33:35.575594 test blocking wait: FAIL
11373 13:33:35.601262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11374 13:33:35.601545 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11376 13:33:35.611224 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11377 13:33:35.611315 test MMAP (select): FAIL
11378 13:33:35.637650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11379 13:33:35.637924 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11381 13:33:35.644370 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11382 13:33:35.648070 test MMAP (epoll): FAIL
11383 13:33:35.671963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11384 13:33:35.672235 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11386 13:33:35.681349 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11387 13:33:35.691728 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11388 13:33:35.696309 test USERPTR (select): FAIL
11389 13:33:35.721373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11390 13:33:35.721664 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11392 13:33:35.728471 test DMABUF: Cannot test, specify --expbuf-device
11393 13:33:35.734332
11394 13:33:35.755620 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11395 13:33:35.759268 <LAVA_TEST_RUNNER EXIT>
11396 13:33:35.759577 ok: lava_test_shell seems to have completed
11397 13:33:35.759657 Marking unfinished test run as failed
11399 13:33:35.760535 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11400 13:33:35.760691 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11401 13:33:35.760810 end: 3 lava-test-retry (duration 00:00:03) [common]
11402 13:33:35.760912 start: 4 finalize (timeout 00:07:33) [common]
11403 13:33:35.761004 start: 4.1 power-off (timeout 00:00:30) [common]
11404 13:33:35.761157 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11405 13:33:35.844940 >> Command sent successfully.
11406 13:33:35.857760 Returned 0 in 0 seconds
11407 13:33:35.959342 end: 4.1 power-off (duration 00:00:00) [common]
11409 13:33:35.961233 start: 4.2 read-feedback (timeout 00:07:33) [common]
11410 13:33:35.962937 Listened to connection for namespace 'common' for up to 1s
11411 13:33:36.963132 Finalising connection for namespace 'common'
11412 13:33:36.963336 Disconnecting from shell: Finalise
11413 13:33:36.963495 / #
11414 13:33:37.063857 end: 4.2 read-feedback (duration 00:00:01) [common]
11415 13:33:37.064036 end: 4 finalize (duration 00:00:01) [common]
11416 13:33:37.064147 Cleaning after the job
11417 13:33:37.064246 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11471202/tftp-deploy-6wala_bt/ramdisk
11418 13:33:37.069621 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11471202/tftp-deploy-6wala_bt/kernel
11419 13:33:37.078116 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11471202/tftp-deploy-6wala_bt/dtb
11420 13:33:37.078309 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11471202/tftp-deploy-6wala_bt/modules
11421 13:33:37.085581 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11471202
11422 13:33:37.156319 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11471202
11423 13:33:37.156473 Job finished correctly