Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 38
- Kernel Warnings: 27
- Boot result: PASS
- Errors: 1
1 09:56:21.979936 lava-dispatcher, installed at version: 2023.10
2 09:56:21.980158 start: 0 validate
3 09:56:21.980292 Start time: 2023-11-24 09:56:21.980284+00:00 (UTC)
4 09:56:21.980424 Using caching service: 'http://localhost/cache/?uri=%s'
5 09:56:21.980623 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 09:56:22.240793 Using caching service: 'http://localhost/cache/?uri=%s'
7 09:56:22.241196 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 09:56:22.515848 Using caching service: 'http://localhost/cache/?uri=%s'
9 09:56:22.516923 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 09:56:57.731653 Using caching service: 'http://localhost/cache/?uri=%s'
11 09:56:57.732364 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 09:56:58.265430 Using caching service: 'http://localhost/cache/?uri=%s'
13 09:56:58.266155 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 09:56:58.543660 validate duration: 36.56
16 09:56:58.544948 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 09:56:58.545544 start: 1.1 download-retry (timeout 00:10:00) [common]
18 09:56:58.546037 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 09:56:58.546662 Not decompressing ramdisk as can be used compressed.
20 09:56:58.547142 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/initrd.cpio.gz
21 09:56:58.547500 saving as /var/lib/lava/dispatcher/tmp/12073278/tftp-deploy-v4nqla42/ramdisk/initrd.cpio.gz
22 09:56:58.547854 total size: 4665412 (4 MB)
23 09:57:01.246335 progress 0 % (0 MB)
24 09:57:01.250843 progress 5 % (0 MB)
25 09:57:01.252214 progress 10 % (0 MB)
26 09:57:01.253489 progress 15 % (0 MB)
27 09:57:01.254706 progress 20 % (0 MB)
28 09:57:01.255906 progress 25 % (1 MB)
29 09:57:01.257150 progress 30 % (1 MB)
30 09:57:01.258346 progress 35 % (1 MB)
31 09:57:01.259534 progress 40 % (1 MB)
32 09:57:01.260955 progress 45 % (2 MB)
33 09:57:01.262148 progress 50 % (2 MB)
34 09:57:01.263342 progress 55 % (2 MB)
35 09:57:01.264563 progress 60 % (2 MB)
36 09:57:01.265773 progress 65 % (2 MB)
37 09:57:01.266990 progress 70 % (3 MB)
38 09:57:01.268176 progress 75 % (3 MB)
39 09:57:01.269430 progress 80 % (3 MB)
40 09:57:01.270838 progress 85 % (3 MB)
41 09:57:01.272073 progress 90 % (4 MB)
42 09:57:01.273404 progress 95 % (4 MB)
43 09:57:01.274639 progress 100 % (4 MB)
44 09:57:01.274786 4 MB downloaded in 2.73 s (1.63 MB/s)
45 09:57:01.274930 end: 1.1.1 http-download (duration 00:00:03) [common]
47 09:57:01.275162 end: 1.1 download-retry (duration 00:00:03) [common]
48 09:57:01.275245 start: 1.2 download-retry (timeout 00:09:57) [common]
49 09:57:01.275326 start: 1.2.1 http-download (timeout 00:09:57) [common]
50 09:57:01.275457 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 09:57:01.275525 saving as /var/lib/lava/dispatcher/tmp/12073278/tftp-deploy-v4nqla42/kernel/Image
52 09:57:01.275584 total size: 49107456 (46 MB)
53 09:57:01.275642 No compression specified
54 09:57:01.276713 progress 0 % (0 MB)
55 09:57:01.289691 progress 5 % (2 MB)
56 09:57:01.302283 progress 10 % (4 MB)
57 09:57:01.315045 progress 15 % (7 MB)
58 09:57:01.327553 progress 20 % (9 MB)
59 09:57:01.340176 progress 25 % (11 MB)
60 09:57:01.352747 progress 30 % (14 MB)
61 09:57:01.365280 progress 35 % (16 MB)
62 09:57:01.377808 progress 40 % (18 MB)
63 09:57:01.390729 progress 45 % (21 MB)
64 09:57:01.403402 progress 50 % (23 MB)
65 09:57:01.416114 progress 55 % (25 MB)
66 09:57:01.428695 progress 60 % (28 MB)
67 09:57:01.441171 progress 65 % (30 MB)
68 09:57:01.453513 progress 70 % (32 MB)
69 09:57:01.465727 progress 75 % (35 MB)
70 09:57:01.478115 progress 80 % (37 MB)
71 09:57:01.490840 progress 85 % (39 MB)
72 09:57:01.503431 progress 90 % (42 MB)
73 09:57:01.515802 progress 95 % (44 MB)
74 09:57:01.528223 progress 100 % (46 MB)
75 09:57:01.528478 46 MB downloaded in 0.25 s (185.19 MB/s)
76 09:57:01.528646 end: 1.2.1 http-download (duration 00:00:00) [common]
78 09:57:01.528870 end: 1.2 download-retry (duration 00:00:00) [common]
79 09:57:01.528953 start: 1.3 download-retry (timeout 00:09:57) [common]
80 09:57:01.529038 start: 1.3.1 http-download (timeout 00:09:57) [common]
81 09:57:01.529174 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 09:57:01.529241 saving as /var/lib/lava/dispatcher/tmp/12073278/tftp-deploy-v4nqla42/dtb/mt8192-asurada-spherion-r0.dtb
83 09:57:01.529300 total size: 47278 (0 MB)
84 09:57:01.529359 No compression specified
85 09:57:01.530432 progress 69 % (0 MB)
86 09:57:01.530704 progress 100 % (0 MB)
87 09:57:01.530855 0 MB downloaded in 0.00 s (29.04 MB/s)
88 09:57:01.530974 end: 1.3.1 http-download (duration 00:00:00) [common]
90 09:57:01.531192 end: 1.3 download-retry (duration 00:00:00) [common]
91 09:57:01.531273 start: 1.4 download-retry (timeout 00:09:57) [common]
92 09:57:01.531351 start: 1.4.1 http-download (timeout 00:09:57) [common]
93 09:57:01.531461 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/full.rootfs.tar.xz
94 09:57:01.531525 saving as /var/lib/lava/dispatcher/tmp/12073278/tftp-deploy-v4nqla42/nfsrootfs/full.rootfs.tar
95 09:57:01.531582 total size: 125290964 (119 MB)
96 09:57:01.531642 Using unxz to decompress xz
97 09:57:01.535577 progress 0 % (0 MB)
98 09:57:01.857755 progress 5 % (6 MB)
99 09:57:02.185160 progress 10 % (11 MB)
100 09:57:02.513651 progress 15 % (17 MB)
101 09:57:02.695985 progress 20 % (23 MB)
102 09:57:02.877598 progress 25 % (29 MB)
103 09:57:03.230313 progress 30 % (35 MB)
104 09:57:03.578185 progress 35 % (41 MB)
105 09:57:03.957060 progress 40 % (47 MB)
106 09:57:04.326954 progress 45 % (53 MB)
107 09:57:04.706442 progress 50 % (59 MB)
108 09:57:05.050637 progress 55 % (65 MB)
109 09:57:05.407742 progress 60 % (71 MB)
110 09:57:05.752168 progress 65 % (77 MB)
111 09:57:06.128374 progress 70 % (83 MB)
112 09:57:06.510169 progress 75 % (89 MB)
113 09:57:06.936235 progress 80 % (95 MB)
114 09:57:07.373234 progress 85 % (101 MB)
115 09:57:07.629651 progress 90 % (107 MB)
116 09:57:07.966565 progress 95 % (113 MB)
117 09:57:08.337293 progress 100 % (119 MB)
118 09:57:08.342911 119 MB downloaded in 6.81 s (17.54 MB/s)
119 09:57:08.343201 end: 1.4.1 http-download (duration 00:00:07) [common]
121 09:57:08.343518 end: 1.4 download-retry (duration 00:00:07) [common]
122 09:57:08.343608 start: 1.5 download-retry (timeout 00:09:50) [common]
123 09:57:08.343700 start: 1.5.1 http-download (timeout 00:09:50) [common]
124 09:57:08.343866 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 09:57:08.343939 saving as /var/lib/lava/dispatcher/tmp/12073278/tftp-deploy-v4nqla42/modules/modules.tar
126 09:57:08.344000 total size: 8622040 (8 MB)
127 09:57:08.344063 Using unxz to decompress xz
128 09:57:08.348447 progress 0 % (0 MB)
129 09:57:08.369478 progress 5 % (0 MB)
130 09:57:08.393105 progress 10 % (0 MB)
131 09:57:08.416957 progress 15 % (1 MB)
132 09:57:08.440600 progress 20 % (1 MB)
133 09:57:08.464673 progress 25 % (2 MB)
134 09:57:08.490611 progress 30 % (2 MB)
135 09:57:08.517379 progress 35 % (2 MB)
136 09:57:08.540846 progress 40 % (3 MB)
137 09:57:08.565014 progress 45 % (3 MB)
138 09:57:08.590568 progress 50 % (4 MB)
139 09:57:08.615426 progress 55 % (4 MB)
140 09:57:08.640218 progress 60 % (4 MB)
141 09:57:08.667822 progress 65 % (5 MB)
142 09:57:08.692822 progress 70 % (5 MB)
143 09:57:08.716897 progress 75 % (6 MB)
144 09:57:08.743792 progress 80 % (6 MB)
145 09:57:08.769588 progress 85 % (7 MB)
146 09:57:08.794691 progress 90 % (7 MB)
147 09:57:08.824766 progress 95 % (7 MB)
148 09:57:08.854495 progress 100 % (8 MB)
149 09:57:08.859266 8 MB downloaded in 0.52 s (15.96 MB/s)
150 09:57:08.859546 end: 1.5.1 http-download (duration 00:00:01) [common]
152 09:57:08.859813 end: 1.5 download-retry (duration 00:00:01) [common]
153 09:57:08.859905 start: 1.6 prepare-tftp-overlay (timeout 00:09:50) [common]
154 09:57:08.860006 start: 1.6.1 extract-nfsrootfs (timeout 00:09:50) [common]
155 09:57:11.031059 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12073278/extract-nfsrootfs-ycmyc54y
156 09:57:11.031272 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 09:57:11.031371 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 09:57:11.031551 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12073278/lava-overlay-unqo_ilw
159 09:57:11.031689 makedir: /var/lib/lava/dispatcher/tmp/12073278/lava-overlay-unqo_ilw/lava-12073278/bin
160 09:57:11.031792 makedir: /var/lib/lava/dispatcher/tmp/12073278/lava-overlay-unqo_ilw/lava-12073278/tests
161 09:57:11.031892 makedir: /var/lib/lava/dispatcher/tmp/12073278/lava-overlay-unqo_ilw/lava-12073278/results
162 09:57:11.031997 Creating /var/lib/lava/dispatcher/tmp/12073278/lava-overlay-unqo_ilw/lava-12073278/bin/lava-add-keys
163 09:57:11.032144 Creating /var/lib/lava/dispatcher/tmp/12073278/lava-overlay-unqo_ilw/lava-12073278/bin/lava-add-sources
164 09:57:11.032276 Creating /var/lib/lava/dispatcher/tmp/12073278/lava-overlay-unqo_ilw/lava-12073278/bin/lava-background-process-start
165 09:57:11.032407 Creating /var/lib/lava/dispatcher/tmp/12073278/lava-overlay-unqo_ilw/lava-12073278/bin/lava-background-process-stop
166 09:57:11.032567 Creating /var/lib/lava/dispatcher/tmp/12073278/lava-overlay-unqo_ilw/lava-12073278/bin/lava-common-functions
167 09:57:11.032711 Creating /var/lib/lava/dispatcher/tmp/12073278/lava-overlay-unqo_ilw/lava-12073278/bin/lava-echo-ipv4
168 09:57:11.032841 Creating /var/lib/lava/dispatcher/tmp/12073278/lava-overlay-unqo_ilw/lava-12073278/bin/lava-install-packages
169 09:57:11.032967 Creating /var/lib/lava/dispatcher/tmp/12073278/lava-overlay-unqo_ilw/lava-12073278/bin/lava-installed-packages
170 09:57:11.033094 Creating /var/lib/lava/dispatcher/tmp/12073278/lava-overlay-unqo_ilw/lava-12073278/bin/lava-os-build
171 09:57:11.033222 Creating /var/lib/lava/dispatcher/tmp/12073278/lava-overlay-unqo_ilw/lava-12073278/bin/lava-probe-channel
172 09:57:11.033349 Creating /var/lib/lava/dispatcher/tmp/12073278/lava-overlay-unqo_ilw/lava-12073278/bin/lava-probe-ip
173 09:57:11.033475 Creating /var/lib/lava/dispatcher/tmp/12073278/lava-overlay-unqo_ilw/lava-12073278/bin/lava-target-ip
174 09:57:11.033601 Creating /var/lib/lava/dispatcher/tmp/12073278/lava-overlay-unqo_ilw/lava-12073278/bin/lava-target-mac
175 09:57:11.033728 Creating /var/lib/lava/dispatcher/tmp/12073278/lava-overlay-unqo_ilw/lava-12073278/bin/lava-target-storage
176 09:57:11.033856 Creating /var/lib/lava/dispatcher/tmp/12073278/lava-overlay-unqo_ilw/lava-12073278/bin/lava-test-case
177 09:57:11.033985 Creating /var/lib/lava/dispatcher/tmp/12073278/lava-overlay-unqo_ilw/lava-12073278/bin/lava-test-event
178 09:57:11.034111 Creating /var/lib/lava/dispatcher/tmp/12073278/lava-overlay-unqo_ilw/lava-12073278/bin/lava-test-feedback
179 09:57:11.034238 Creating /var/lib/lava/dispatcher/tmp/12073278/lava-overlay-unqo_ilw/lava-12073278/bin/lava-test-raise
180 09:57:11.034364 Creating /var/lib/lava/dispatcher/tmp/12073278/lava-overlay-unqo_ilw/lava-12073278/bin/lava-test-reference
181 09:57:11.034491 Creating /var/lib/lava/dispatcher/tmp/12073278/lava-overlay-unqo_ilw/lava-12073278/bin/lava-test-runner
182 09:57:11.034616 Creating /var/lib/lava/dispatcher/tmp/12073278/lava-overlay-unqo_ilw/lava-12073278/bin/lava-test-set
183 09:57:11.034742 Creating /var/lib/lava/dispatcher/tmp/12073278/lava-overlay-unqo_ilw/lava-12073278/bin/lava-test-shell
184 09:57:11.034870 Updating /var/lib/lava/dispatcher/tmp/12073278/lava-overlay-unqo_ilw/lava-12073278/bin/lava-install-packages (oe)
185 09:57:11.035026 Updating /var/lib/lava/dispatcher/tmp/12073278/lava-overlay-unqo_ilw/lava-12073278/bin/lava-installed-packages (oe)
186 09:57:11.035149 Creating /var/lib/lava/dispatcher/tmp/12073278/lava-overlay-unqo_ilw/lava-12073278/environment
187 09:57:11.035248 LAVA metadata
188 09:57:11.035321 - LAVA_JOB_ID=12073278
189 09:57:11.035385 - LAVA_DISPATCHER_IP=192.168.201.1
190 09:57:11.035489 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
191 09:57:11.035556 skipped lava-vland-overlay
192 09:57:11.035632 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 09:57:11.035711 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
194 09:57:11.035772 skipped lava-multinode-overlay
195 09:57:11.035846 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 09:57:11.035923 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
197 09:57:11.035996 Loading test definitions
198 09:57:11.036085 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
199 09:57:11.036156 Using /lava-12073278 at stage 0
200 09:57:11.036471 uuid=12073278_1.6.2.3.1 testdef=None
201 09:57:11.036567 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 09:57:11.036653 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
203 09:57:11.037173 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 09:57:11.037394 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
206 09:57:11.038032 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 09:57:11.038262 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
209 09:57:11.039161 runner path: /var/lib/lava/dispatcher/tmp/12073278/lava-overlay-unqo_ilw/lava-12073278/0/tests/0_dmesg test_uuid 12073278_1.6.2.3.1
210 09:57:11.039320 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 09:57:11.039545 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:48) [common]
213 09:57:11.039618 Using /lava-12073278 at stage 1
214 09:57:11.039921 uuid=12073278_1.6.2.3.5 testdef=None
215 09:57:11.040012 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 09:57:11.040097 start: 1.6.2.3.6 test-overlay (timeout 00:09:48) [common]
217 09:57:11.040588 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 09:57:11.040807 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:48) [common]
220 09:57:11.041457 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 09:57:11.041684 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:48) [common]
223 09:57:11.042312 runner path: /var/lib/lava/dispatcher/tmp/12073278/lava-overlay-unqo_ilw/lava-12073278/1/tests/1_bootrr test_uuid 12073278_1.6.2.3.5
224 09:57:11.042466 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 09:57:11.042671 Creating lava-test-runner.conf files
227 09:57:11.042734 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12073278/lava-overlay-unqo_ilw/lava-12073278/0 for stage 0
228 09:57:11.042826 - 0_dmesg
229 09:57:11.042906 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12073278/lava-overlay-unqo_ilw/lava-12073278/1 for stage 1
230 09:57:11.042998 - 1_bootrr
231 09:57:11.043094 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 09:57:11.043179 start: 1.6.2.4 compress-overlay (timeout 00:09:48) [common]
233 09:57:11.050617 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 09:57:11.050735 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:47) [common]
235 09:57:11.050822 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 09:57:11.050908 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 09:57:11.050992 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:47) [common]
238 09:57:11.171192 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 09:57:11.171591 start: 1.6.4 extract-modules (timeout 00:09:47) [common]
240 09:57:11.171708 extracting modules file /var/lib/lava/dispatcher/tmp/12073278/tftp-deploy-v4nqla42/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12073278/extract-nfsrootfs-ycmyc54y
241 09:57:11.397280 extracting modules file /var/lib/lava/dispatcher/tmp/12073278/tftp-deploy-v4nqla42/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12073278/extract-overlay-ramdisk-efjdbhuf/ramdisk
242 09:57:11.629256 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 09:57:11.629430 start: 1.6.5 apply-overlay-tftp (timeout 00:09:47) [common]
244 09:57:11.629527 [common] Applying overlay to NFS
245 09:57:11.629599 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12073278/compress-overlay-f7jpkzd_/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12073278/extract-nfsrootfs-ycmyc54y
246 09:57:11.637863 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 09:57:11.638010 start: 1.6.6 configure-preseed-file (timeout 00:09:47) [common]
248 09:57:11.638107 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 09:57:11.638198 start: 1.6.7 compress-ramdisk (timeout 00:09:47) [common]
250 09:57:11.638276 Building ramdisk /var/lib/lava/dispatcher/tmp/12073278/extract-overlay-ramdisk-efjdbhuf/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12073278/extract-overlay-ramdisk-efjdbhuf/ramdisk
251 09:57:11.969069 >> 119398 blocks
252 09:57:13.869061 rename /var/lib/lava/dispatcher/tmp/12073278/extract-overlay-ramdisk-efjdbhuf/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12073278/tftp-deploy-v4nqla42/ramdisk/ramdisk.cpio.gz
253 09:57:13.869541 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 09:57:13.869678 start: 1.6.8 prepare-kernel (timeout 00:09:45) [common]
255 09:57:13.869780 start: 1.6.8.1 prepare-fit (timeout 00:09:45) [common]
256 09:57:13.869890 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12073278/tftp-deploy-v4nqla42/kernel/Image'
257 09:57:25.904246 Returned 0 in 12 seconds
258 09:57:26.005249 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12073278/tftp-deploy-v4nqla42/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12073278/tftp-deploy-v4nqla42/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12073278/tftp-deploy-v4nqla42/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12073278/tftp-deploy-v4nqla42/kernel/image.itb
259 09:57:26.370275 output: FIT description: Kernel Image image with one or more FDT blobs
260 09:57:26.370647 output: Created: Fri Nov 24 09:57:26 2023
261 09:57:26.370721 output: Image 0 (kernel-1)
262 09:57:26.370786 output: Description:
263 09:57:26.370850 output: Created: Fri Nov 24 09:57:26 2023
264 09:57:26.370912 output: Type: Kernel Image
265 09:57:26.370972 output: Compression: lzma compressed
266 09:57:26.371031 output: Data Size: 11047542 Bytes = 10788.62 KiB = 10.54 MiB
267 09:57:26.371092 output: Architecture: AArch64
268 09:57:26.371151 output: OS: Linux
269 09:57:26.371209 output: Load Address: 0x00000000
270 09:57:26.371262 output: Entry Point: 0x00000000
271 09:57:26.371320 output: Hash algo: crc32
272 09:57:26.371376 output: Hash value: 2edffaa3
273 09:57:26.371434 output: Image 1 (fdt-1)
274 09:57:26.371487 output: Description: mt8192-asurada-spherion-r0
275 09:57:26.371540 output: Created: Fri Nov 24 09:57:26 2023
276 09:57:26.371594 output: Type: Flat Device Tree
277 09:57:26.371647 output: Compression: uncompressed
278 09:57:26.371700 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
279 09:57:26.371753 output: Architecture: AArch64
280 09:57:26.371806 output: Hash algo: crc32
281 09:57:26.371859 output: Hash value: cc4352de
282 09:57:26.371912 output: Image 2 (ramdisk-1)
283 09:57:26.371964 output: Description: unavailable
284 09:57:26.372016 output: Created: Fri Nov 24 09:57:26 2023
285 09:57:26.372069 output: Type: RAMDisk Image
286 09:57:26.372122 output: Compression: Unknown Compression
287 09:57:26.372175 output: Data Size: 17800026 Bytes = 17382.84 KiB = 16.98 MiB
288 09:57:26.372228 output: Architecture: AArch64
289 09:57:26.372280 output: OS: Linux
290 09:57:26.372332 output: Load Address: unavailable
291 09:57:26.372384 output: Entry Point: unavailable
292 09:57:26.372437 output: Hash algo: crc32
293 09:57:26.372489 output: Hash value: 0c5bfa20
294 09:57:26.372556 output: Default Configuration: 'conf-1'
295 09:57:26.372610 output: Configuration 0 (conf-1)
296 09:57:26.372663 output: Description: mt8192-asurada-spherion-r0
297 09:57:26.372716 output: Kernel: kernel-1
298 09:57:26.372769 output: Init Ramdisk: ramdisk-1
299 09:57:26.372822 output: FDT: fdt-1
300 09:57:26.372874 output: Loadables: kernel-1
301 09:57:26.372927 output:
302 09:57:26.373135 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
303 09:57:26.373241 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
304 09:57:26.373346 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
305 09:57:26.373441 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:32) [common]
306 09:57:26.373520 No LXC device requested
307 09:57:26.373598 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 09:57:26.373685 start: 1.8 deploy-device-env (timeout 00:09:32) [common]
309 09:57:26.373764 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 09:57:26.373834 Checking files for TFTP limit of 4294967296 bytes.
311 09:57:26.374338 end: 1 tftp-deploy (duration 00:00:28) [common]
312 09:57:26.374444 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 09:57:26.374537 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 09:57:26.374661 substitutions:
315 09:57:26.374727 - {DTB}: 12073278/tftp-deploy-v4nqla42/dtb/mt8192-asurada-spherion-r0.dtb
316 09:57:26.374792 - {INITRD}: 12073278/tftp-deploy-v4nqla42/ramdisk/ramdisk.cpio.gz
317 09:57:26.374851 - {KERNEL}: 12073278/tftp-deploy-v4nqla42/kernel/Image
318 09:57:26.374909 - {LAVA_MAC}: None
319 09:57:26.374965 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12073278/extract-nfsrootfs-ycmyc54y
320 09:57:26.375021 - {NFS_SERVER_IP}: 192.168.201.1
321 09:57:26.375076 - {PRESEED_CONFIG}: None
322 09:57:26.375130 - {PRESEED_LOCAL}: None
323 09:57:26.375185 - {RAMDISK}: 12073278/tftp-deploy-v4nqla42/ramdisk/ramdisk.cpio.gz
324 09:57:26.375239 - {ROOT_PART}: None
325 09:57:26.375293 - {ROOT}: None
326 09:57:26.375347 - {SERVER_IP}: 192.168.201.1
327 09:57:26.375400 - {TEE}: None
328 09:57:26.375453 Parsed boot commands:
329 09:57:26.375506 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 09:57:26.375695 Parsed boot commands: tftpboot 192.168.201.1 12073278/tftp-deploy-v4nqla42/kernel/image.itb 12073278/tftp-deploy-v4nqla42/kernel/cmdline
331 09:57:26.375784 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 09:57:26.375867 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 09:57:26.375964 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 09:57:26.376050 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 09:57:26.376118 Not connected, no need to disconnect.
336 09:57:26.376194 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 09:57:26.376276 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 09:57:26.376346 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
339 09:57:26.380337 Setting prompt string to ['lava-test: # ']
340 09:57:26.380733 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 09:57:26.380845 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 09:57:26.380942 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 09:57:26.381035 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 09:57:26.381230 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
345 09:57:31.526346 >> Command sent successfully.
346 09:57:31.538760 Returned 0 in 5 seconds
347 09:57:31.640213 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 09:57:31.641920 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 09:57:31.642417 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 09:57:31.642922 Setting prompt string to 'Starting depthcharge on Spherion...'
352 09:57:31.643284 Changing prompt to 'Starting depthcharge on Spherion...'
353 09:57:31.643638 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 09:57:31.644840 [Enter `^Ec?' for help]
355 09:57:31.809973
356 09:57:31.810115
357 09:57:31.810183 F0: 102B 0000
358 09:57:31.810249
359 09:57:31.810307 F3: 1001 0000 [0200]
360 09:57:31.810366
361 09:57:31.813576 F3: 1001 0000
362 09:57:31.813658
363 09:57:31.813723 F7: 102D 0000
364 09:57:31.813783
365 09:57:31.813841 F1: 0000 0000
366 09:57:31.817344
367 09:57:31.817425 V0: 0000 0000 [0001]
368 09:57:31.817491
369 09:57:31.817552 00: 0007 8000
370 09:57:31.817615
371 09:57:31.821180 01: 0000 0000
372 09:57:31.821262
373 09:57:31.821326 BP: 0C00 0209 [0000]
374 09:57:31.821386
375 09:57:31.824631 G0: 1182 0000
376 09:57:31.824737
377 09:57:31.824831 EC: 0000 0021 [4000]
378 09:57:31.824920
379 09:57:31.828058 S7: 0000 0000 [0000]
380 09:57:31.828140
381 09:57:31.828205 CC: 0000 0000 [0001]
382 09:57:31.828265
383 09:57:31.831680 T0: 0000 0040 [010F]
384 09:57:31.831765
385 09:57:31.831830 Jump to BL
386 09:57:31.831891
387 09:57:31.856824
388 09:57:31.856908
389 09:57:31.856972
390 09:57:31.863595 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 09:57:31.867268 ARM64: Exception handlers installed.
392 09:57:31.870676 ARM64: Testing exception
393 09:57:31.874294 ARM64: Done test exception
394 09:57:31.881881 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 09:57:31.892589 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 09:57:31.899206 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 09:57:31.909392 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 09:57:31.916098 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 09:57:31.922568 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 09:57:31.933626 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 09:57:31.940613 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 09:57:31.959484 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 09:57:31.963003 WDT: Last reset was cold boot
404 09:57:31.966358 SPI1(PAD0) initialized at 2873684 Hz
405 09:57:31.969542 SPI5(PAD0) initialized at 992727 Hz
406 09:57:31.973002 VBOOT: Loading verstage.
407 09:57:31.979879 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 09:57:31.982859 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 09:57:31.986280 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 09:57:31.989440 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 09:57:31.996928 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 09:57:32.003611 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 09:57:32.014536 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
414 09:57:32.014618
415 09:57:32.014683
416 09:57:32.024681 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 09:57:32.027979 ARM64: Exception handlers installed.
418 09:57:32.030959 ARM64: Testing exception
419 09:57:32.031041 ARM64: Done test exception
420 09:57:32.037709 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 09:57:32.041210 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 09:57:32.055713 Probing TPM: . done!
423 09:57:32.055795 TPM ready after 0 ms
424 09:57:32.062844 Connected to device vid:did:rid of 1ae0:0028:00
425 09:57:32.069869 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
426 09:57:32.118747 Initialized TPM device CR50 revision 0
427 09:57:32.122021 tlcl_send_startup: Startup return code is 0
428 09:57:32.128808 TPM: setup succeeded
429 09:57:32.141518 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 09:57:32.151098 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 09:57:32.160361 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 09:57:32.169259 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 09:57:32.172695 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 09:57:32.175967 in-header: 03 07 00 00 08 00 00 00
435 09:57:32.179288 in-data: aa e4 47 04 13 02 00 00
436 09:57:32.182679 Chrome EC: UHEPI supported
437 09:57:32.189410 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 09:57:32.193203 in-header: 03 95 00 00 08 00 00 00
439 09:57:32.196218 in-data: 18 20 20 08 00 00 00 00
440 09:57:32.196301 Phase 1
441 09:57:32.200077 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 09:57:32.206867 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 09:57:32.214563 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 09:57:32.214646 Recovery requested (1009000e)
445 09:57:32.224274 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 09:57:32.229949 tlcl_extend: response is 0
447 09:57:32.238793 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 09:57:32.244472 tlcl_extend: response is 0
449 09:57:32.251881 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 09:57:32.271811 read SPI 0x210d4 0x2173b: 15145 us, 9047 KB/s, 72.376 Mbps
451 09:57:32.279478 BS: bootblock times (exec / console): total (unknown) / 148 ms
452 09:57:32.279564
453 09:57:32.279630
454 09:57:32.286523 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 09:57:32.290392 ARM64: Exception handlers installed.
456 09:57:32.294209 ARM64: Testing exception
457 09:57:32.297295 ARM64: Done test exception
458 09:57:32.317096 pmic_efuse_setting: Set efuses in 11 msecs
459 09:57:32.320582 pmwrap_interface_init: Select PMIF_VLD_RDY
460 09:57:32.327206 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 09:57:32.330483 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 09:57:32.337377 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 09:57:32.340482 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 09:57:32.347320 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 09:57:32.350405 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 09:57:32.353677 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 09:57:32.360346 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 09:57:32.363800 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 09:57:32.370191 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 09:57:32.373694 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 09:57:32.377095 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 09:57:32.383483 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 09:57:32.390100 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 09:57:32.393792 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 09:57:32.401007 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 09:57:32.408098 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 09:57:32.411793 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 09:57:32.418646 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 09:57:32.422946 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 09:57:32.429662 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 09:57:32.433735 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 09:57:32.440734 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 09:57:32.444348 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 09:57:32.451337 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 09:57:32.455206 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 09:57:32.462605 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 09:57:32.465591 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 09:57:32.469547 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 09:57:32.477138 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 09:57:32.480834 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 09:57:32.488087 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 09:57:32.491441 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 09:57:32.495048 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 09:57:32.502339 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 09:57:32.506223 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 09:57:32.509807 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 09:57:32.517237 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 09:57:32.521134 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 09:57:32.524690 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 09:57:32.528109 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 09:57:32.535553 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 09:57:32.539103 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 09:57:32.542714 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 09:57:32.546554 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 09:57:32.550251 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 09:57:32.553748 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 09:57:32.560900 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 09:57:32.564815 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 09:57:32.568357 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 09:57:32.572244 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 09:57:32.579747 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 09:57:32.586937 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 09:57:32.594216 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 09:57:32.601313 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 09:57:32.609224 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 09:57:32.616356 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 09:57:32.619944 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 09:57:32.622892 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 09:57:32.630136 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x19
520 09:57:32.637518 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 09:57:32.641302 [RTC]rtc_osc_init,62: osc32con val = 0xde70
522 09:57:32.644952 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 09:57:32.655038 [RTC]rtc_get_frequency_meter,154: input=15, output=764
524 09:57:32.664676 [RTC]rtc_get_frequency_meter,154: input=23, output=949
525 09:57:32.673622 [RTC]rtc_get_frequency_meter,154: input=19, output=857
526 09:57:32.682974 [RTC]rtc_get_frequency_meter,154: input=17, output=811
527 09:57:32.692942 [RTC]rtc_get_frequency_meter,154: input=16, output=787
528 09:57:32.702113 [RTC]rtc_get_frequency_meter,154: input=16, output=787
529 09:57:32.711833 [RTC]rtc_get_frequency_meter,154: input=17, output=811
530 09:57:32.715010 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
531 09:57:32.722618 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
532 09:57:32.726618 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
533 09:57:32.729882 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
534 09:57:32.733987 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
535 09:57:32.737340 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
536 09:57:32.741336 ADC[4]: Raw value=670800 ID=5
537 09:57:32.744786 ADC[3]: Raw value=212917 ID=1
538 09:57:32.744886 RAM Code: 0x51
539 09:57:32.748339 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
540 09:57:32.755795 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
541 09:57:32.763278 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
542 09:57:32.766961 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
543 09:57:32.770193 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
544 09:57:32.775288 in-header: 03 07 00 00 08 00 00 00
545 09:57:32.778823 in-data: aa e4 47 04 13 02 00 00
546 09:57:32.781901 Chrome EC: UHEPI supported
547 09:57:32.789559 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
548 09:57:32.793112 in-header: 03 95 00 00 08 00 00 00
549 09:57:32.797126 in-data: 18 20 20 08 00 00 00 00
550 09:57:32.797210 MRC: failed to locate region type 0.
551 09:57:32.804466 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
552 09:57:32.807616 DRAM-K: Running full calibration
553 09:57:32.814721 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
554 09:57:32.814802 header.status = 0x0
555 09:57:32.818047 header.version = 0x6 (expected: 0x6)
556 09:57:32.822017 header.size = 0xd00 (expected: 0xd00)
557 09:57:32.825785 header.flags = 0x0
558 09:57:32.829058 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
559 09:57:32.848401 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps
560 09:57:32.855837 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
561 09:57:32.859439 dram_init: ddr_geometry: 0
562 09:57:32.859532 [EMI] MDL number = 0
563 09:57:32.863256 [EMI] Get MDL freq = 0
564 09:57:32.863335 dram_init: ddr_type: 0
565 09:57:32.867069 is_discrete_lpddr4: 1
566 09:57:32.871131 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
567 09:57:32.871237
568 09:57:32.871305
569 09:57:32.871375 [Bian_co] ETT version 0.0.0.1
570 09:57:32.878358 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
571 09:57:32.878441
572 09:57:32.882008 dramc_set_vcore_voltage set vcore to 650000
573 09:57:32.882087 Read voltage for 800, 4
574 09:57:32.885986 Vio18 = 0
575 09:57:32.886070 Vcore = 650000
576 09:57:32.886136 Vdram = 0
577 09:57:32.886197 Vddq = 0
578 09:57:32.889018 Vmddr = 0
579 09:57:32.889095 dram_init: config_dvfs: 1
580 09:57:32.896427 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
581 09:57:32.900255 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
582 09:57:32.903964 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
583 09:57:32.907470 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
584 09:57:32.911294 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
585 09:57:32.914883 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
586 09:57:32.918586 MEM_TYPE=3, freq_sel=18
587 09:57:32.922525 sv_algorithm_assistance_LP4_1600
588 09:57:32.926041 ============ PULL DRAM RESETB DOWN ============
589 09:57:32.929301 ========== PULL DRAM RESETB DOWN end =========
590 09:57:32.933193 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
591 09:57:32.936500 ===================================
592 09:57:32.940189 LPDDR4 DRAM CONFIGURATION
593 09:57:32.943772 ===================================
594 09:57:32.943852 EX_ROW_EN[0] = 0x0
595 09:57:32.947263 EX_ROW_EN[1] = 0x0
596 09:57:32.947339 LP4Y_EN = 0x0
597 09:57:32.951107 WORK_FSP = 0x0
598 09:57:32.951177 WL = 0x2
599 09:57:32.954895 RL = 0x2
600 09:57:32.954973 BL = 0x2
601 09:57:32.958393 RPST = 0x0
602 09:57:32.958468 RD_PRE = 0x0
603 09:57:32.962234 WR_PRE = 0x1
604 09:57:32.962320 WR_PST = 0x0
605 09:57:32.965895 DBI_WR = 0x0
606 09:57:32.965974 DBI_RD = 0x0
607 09:57:32.969465 OTF = 0x1
608 09:57:32.969551 ===================================
609 09:57:32.973288 ===================================
610 09:57:32.977160 ANA top config
611 09:57:32.980606 ===================================
612 09:57:32.980700 DLL_ASYNC_EN = 0
613 09:57:32.984397 ALL_SLAVE_EN = 1
614 09:57:32.988150 NEW_RANK_MODE = 1
615 09:57:32.988234 DLL_IDLE_MODE = 1
616 09:57:32.991532 LP45_APHY_COMB_EN = 1
617 09:57:32.995377 TX_ODT_DIS = 1
618 09:57:32.995455 NEW_8X_MODE = 1
619 09:57:32.998495 ===================================
620 09:57:33.001804 ===================================
621 09:57:33.005116 data_rate = 1600
622 09:57:33.008819 CKR = 1
623 09:57:33.012319 DQ_P2S_RATIO = 8
624 09:57:33.015916 ===================================
625 09:57:33.019497 CA_P2S_RATIO = 8
626 09:57:33.019580 DQ_CA_OPEN = 0
627 09:57:33.022838 DQ_SEMI_OPEN = 0
628 09:57:33.026504 CA_SEMI_OPEN = 0
629 09:57:33.030257 CA_FULL_RATE = 0
630 09:57:33.030344 DQ_CKDIV4_EN = 1
631 09:57:33.033802 CA_CKDIV4_EN = 1
632 09:57:33.036896 CA_PREDIV_EN = 0
633 09:57:33.039943 PH8_DLY = 0
634 09:57:33.043495 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
635 09:57:33.046692 DQ_AAMCK_DIV = 4
636 09:57:33.046764 CA_AAMCK_DIV = 4
637 09:57:33.050209 CA_ADMCK_DIV = 4
638 09:57:33.053511 DQ_TRACK_CA_EN = 0
639 09:57:33.056978 CA_PICK = 800
640 09:57:33.060625 CA_MCKIO = 800
641 09:57:33.064271 MCKIO_SEMI = 0
642 09:57:33.064340 PLL_FREQ = 3068
643 09:57:33.067709 DQ_UI_PI_RATIO = 32
644 09:57:33.071010 CA_UI_PI_RATIO = 0
645 09:57:33.074432 ===================================
646 09:57:33.078023 ===================================
647 09:57:33.081316 memory_type:LPDDR4
648 09:57:33.081394 GP_NUM : 10
649 09:57:33.084482 SRAM_EN : 1
650 09:57:33.084579 MD32_EN : 0
651 09:57:33.088275 ===================================
652 09:57:33.091833 [ANA_INIT] >>>>>>>>>>>>>>
653 09:57:33.095491 <<<<<< [CONFIGURE PHASE]: ANA_TX
654 09:57:33.099274 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
655 09:57:33.103070 ===================================
656 09:57:33.103150 data_rate = 1600,PCW = 0X7600
657 09:57:33.106495 ===================================
658 09:57:33.110213 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
659 09:57:33.117337 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
660 09:57:33.120850 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
661 09:57:33.127271 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
662 09:57:33.130631 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
663 09:57:33.133877 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
664 09:57:33.133961 [ANA_INIT] flow start
665 09:57:33.137278 [ANA_INIT] PLL >>>>>>>>
666 09:57:33.140477 [ANA_INIT] PLL <<<<<<<<
667 09:57:33.143658 [ANA_INIT] MIDPI >>>>>>>>
668 09:57:33.143740 [ANA_INIT] MIDPI <<<<<<<<
669 09:57:33.146936 [ANA_INIT] DLL >>>>>>>>
670 09:57:33.150250 [ANA_INIT] flow end
671 09:57:33.153762 ============ LP4 DIFF to SE enter ============
672 09:57:33.157218 ============ LP4 DIFF to SE exit ============
673 09:57:33.160227 [ANA_INIT] <<<<<<<<<<<<<
674 09:57:33.163475 [Flow] Enable top DCM control >>>>>
675 09:57:33.166907 [Flow] Enable top DCM control <<<<<
676 09:57:33.170213 Enable DLL master slave shuffle
677 09:57:33.173724 ==============================================================
678 09:57:33.176955 Gating Mode config
679 09:57:33.180254 ==============================================================
680 09:57:33.183710 Config description:
681 09:57:33.193566 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
682 09:57:33.200555 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
683 09:57:33.203643 SELPH_MODE 0: By rank 1: By Phase
684 09:57:33.210264 ==============================================================
685 09:57:33.213626 GAT_TRACK_EN = 1
686 09:57:33.216938 RX_GATING_MODE = 2
687 09:57:33.220154 RX_GATING_TRACK_MODE = 2
688 09:57:33.223762 SELPH_MODE = 1
689 09:57:33.226808 PICG_EARLY_EN = 1
690 09:57:33.226929 VALID_LAT_VALUE = 1
691 09:57:33.233362 ==============================================================
692 09:57:33.236707 Enter into Gating configuration >>>>
693 09:57:33.240125 Exit from Gating configuration <<<<
694 09:57:33.243361 Enter into DVFS_PRE_config >>>>>
695 09:57:33.253374 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
696 09:57:33.256868 Exit from DVFS_PRE_config <<<<<
697 09:57:33.260398 Enter into PICG configuration >>>>
698 09:57:33.263364 Exit from PICG configuration <<<<
699 09:57:33.266932 [RX_INPUT] configuration >>>>>
700 09:57:33.270179 [RX_INPUT] configuration <<<<<
701 09:57:33.273310 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
702 09:57:33.279954 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
703 09:57:33.286979 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
704 09:57:33.293270 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
705 09:57:33.299879 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
706 09:57:33.306636 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
707 09:57:33.310452 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
708 09:57:33.313513 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
709 09:57:33.316731 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
710 09:57:33.320112 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
711 09:57:33.326670 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
712 09:57:33.330294 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
713 09:57:33.333545 ===================================
714 09:57:33.336815 LPDDR4 DRAM CONFIGURATION
715 09:57:33.339854 ===================================
716 09:57:33.339930 EX_ROW_EN[0] = 0x0
717 09:57:33.343342 EX_ROW_EN[1] = 0x0
718 09:57:33.343417 LP4Y_EN = 0x0
719 09:57:33.346735 WORK_FSP = 0x0
720 09:57:33.346809 WL = 0x2
721 09:57:33.350089 RL = 0x2
722 09:57:33.350169 BL = 0x2
723 09:57:33.353304 RPST = 0x0
724 09:57:33.353380 RD_PRE = 0x0
725 09:57:33.356573 WR_PRE = 0x1
726 09:57:33.356651 WR_PST = 0x0
727 09:57:33.360217 DBI_WR = 0x0
728 09:57:33.363297 DBI_RD = 0x0
729 09:57:33.363373 OTF = 0x1
730 09:57:33.366818 ===================================
731 09:57:33.369788 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
732 09:57:33.373178 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
733 09:57:33.380018 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
734 09:57:33.383070 ===================================
735 09:57:33.387148 LPDDR4 DRAM CONFIGURATION
736 09:57:33.387249 ===================================
737 09:57:33.389604 EX_ROW_EN[0] = 0x10
738 09:57:33.393228 EX_ROW_EN[1] = 0x0
739 09:57:33.393306 LP4Y_EN = 0x0
740 09:57:33.396420 WORK_FSP = 0x0
741 09:57:33.396494 WL = 0x2
742 09:57:33.400028 RL = 0x2
743 09:57:33.400111 BL = 0x2
744 09:57:33.403452 RPST = 0x0
745 09:57:33.403534 RD_PRE = 0x0
746 09:57:33.406709 WR_PRE = 0x1
747 09:57:33.406791 WR_PST = 0x0
748 09:57:33.409816 DBI_WR = 0x0
749 09:57:33.409898 DBI_RD = 0x0
750 09:57:33.413220 OTF = 0x1
751 09:57:33.416242 ===================================
752 09:57:33.423045 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
753 09:57:33.426695 nWR fixed to 40
754 09:57:33.429826 [ModeRegInit_LP4] CH0 RK0
755 09:57:33.429909 [ModeRegInit_LP4] CH0 RK1
756 09:57:33.433371 [ModeRegInit_LP4] CH1 RK0
757 09:57:33.436673 [ModeRegInit_LP4] CH1 RK1
758 09:57:33.436755 match AC timing 12
759 09:57:33.443064 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
760 09:57:33.446335 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
761 09:57:33.450056 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
762 09:57:33.456691 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
763 09:57:33.459742 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
764 09:57:33.459824 [EMI DOE] emi_dcm 0
765 09:57:33.466529 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
766 09:57:33.466610 ==
767 09:57:33.469744 Dram Type= 6, Freq= 0, CH_0, rank 0
768 09:57:33.473088 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
769 09:57:33.473178 ==
770 09:57:33.479959 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
771 09:57:33.483142 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
772 09:57:33.493541 [CA 0] Center 37 (7~68) winsize 62
773 09:57:33.496752 [CA 1] Center 37 (7~68) winsize 62
774 09:57:33.499982 [CA 2] Center 35 (5~66) winsize 62
775 09:57:33.503412 [CA 3] Center 35 (4~66) winsize 63
776 09:57:33.507027 [CA 4] Center 34 (4~65) winsize 62
777 09:57:33.510479 [CA 5] Center 33 (3~64) winsize 62
778 09:57:33.510549
779 09:57:33.513463 [CmdBusTrainingLP45] Vref(ca) range 1: 32
780 09:57:33.513531
781 09:57:33.516925 [CATrainingPosCal] consider 1 rank data
782 09:57:33.520177 u2DelayCellTimex100 = 270/100 ps
783 09:57:33.523541 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
784 09:57:33.526872 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
785 09:57:33.533869 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
786 09:57:33.536728 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
787 09:57:33.540365 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
788 09:57:33.543734 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
789 09:57:33.543815
790 09:57:33.546757 CA PerBit enable=1, Macro0, CA PI delay=33
791 09:57:33.546839
792 09:57:33.550102 [CBTSetCACLKResult] CA Dly = 33
793 09:57:33.550184 CS Dly: 5 (0~36)
794 09:57:33.553487 ==
795 09:57:33.553569 Dram Type= 6, Freq= 0, CH_0, rank 1
796 09:57:33.560001 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
797 09:57:33.560084 ==
798 09:57:33.563368 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
799 09:57:33.570155 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
800 09:57:33.579626 [CA 0] Center 37 (7~68) winsize 62
801 09:57:33.583055 [CA 1] Center 37 (6~68) winsize 63
802 09:57:33.586646 [CA 2] Center 35 (4~66) winsize 63
803 09:57:33.589662 [CA 3] Center 34 (4~65) winsize 62
804 09:57:33.593313 [CA 4] Center 33 (3~64) winsize 62
805 09:57:33.596470 [CA 5] Center 33 (3~64) winsize 62
806 09:57:33.596559
807 09:57:33.599777 [CmdBusTrainingLP45] Vref(ca) range 1: 32
808 09:57:33.599858
809 09:57:33.602988 [CATrainingPosCal] consider 2 rank data
810 09:57:33.606341 u2DelayCellTimex100 = 270/100 ps
811 09:57:33.609664 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
812 09:57:33.612937 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
813 09:57:33.619601 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
814 09:57:33.622735 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
815 09:57:33.626094 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
816 09:57:33.629618 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
817 09:57:33.629699
818 09:57:33.632739 CA PerBit enable=1, Macro0, CA PI delay=33
819 09:57:33.632821
820 09:57:33.636263 [CBTSetCACLKResult] CA Dly = 33
821 09:57:33.636345 CS Dly: 6 (0~38)
822 09:57:33.636409
823 09:57:33.639442 ----->DramcWriteLeveling(PI) begin...
824 09:57:33.643024 ==
825 09:57:33.646042 Dram Type= 6, Freq= 0, CH_0, rank 0
826 09:57:33.649203 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
827 09:57:33.649285 ==
828 09:57:33.652711 Write leveling (Byte 0): 29 => 29
829 09:57:33.656300 Write leveling (Byte 1): 30 => 30
830 09:57:33.659905 DramcWriteLeveling(PI) end<-----
831 09:57:33.659986
832 09:57:33.660088 ==
833 09:57:33.663623 Dram Type= 6, Freq= 0, CH_0, rank 0
834 09:57:33.667021 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
835 09:57:33.667142 ==
836 09:57:33.667207 [Gating] SW mode calibration
837 09:57:33.674680 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
838 09:57:33.681294 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
839 09:57:33.684725 0 6 0 | B1->B0 | 3333 3030 | 0 1 | (0 0) (1 0)
840 09:57:33.688474 0 6 4 | B1->B0 | 2c2c 2323 | 1 0 | (0 0) (0 0)
841 09:57:33.695554 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 09:57:33.698329 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 09:57:33.701650 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 09:57:33.708673 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 09:57:33.712220 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 09:57:33.715629 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 09:57:33.721871 0 7 0 | B1->B0 | 2626 2929 | 0 0 | (0 0) (1 1)
848 09:57:33.725335 0 7 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
849 09:57:33.728819 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 09:57:33.735690 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
851 09:57:33.738510 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
852 09:57:33.742178 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 09:57:33.745176 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
854 09:57:33.752002 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
855 09:57:33.755404 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
856 09:57:33.758676 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 09:57:33.765295 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 09:57:33.768630 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 09:57:33.771815 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 09:57:33.778343 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 09:57:33.782004 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 09:57:33.785239 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 09:57:33.791841 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 09:57:33.795140 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
865 09:57:33.798497 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
866 09:57:33.805092 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
867 09:57:33.808837 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
868 09:57:33.811863 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
869 09:57:33.818554 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
870 09:57:33.821732 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
871 09:57:33.825144 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 09:57:33.828707 Total UI for P1: 0, mck2ui 16
873 09:57:33.831914 best dqsien dly found for B0: ( 0, 9, 30)
874 09:57:33.835035 Total UI for P1: 0, mck2ui 16
875 09:57:33.838693 best dqsien dly found for B1: ( 0, 9, 30)
876 09:57:33.841832 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
877 09:57:33.845289 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
878 09:57:33.845362
879 09:57:33.848607 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
880 09:57:33.855182 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
881 09:57:33.855265 [Gating] SW calibration Done
882 09:57:33.855330 ==
883 09:57:33.858518 Dram Type= 6, Freq= 0, CH_0, rank 0
884 09:57:33.865259 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
885 09:57:33.865339 ==
886 09:57:33.865404 RX Vref Scan: 0
887 09:57:33.865487
888 09:57:33.868545 RX Vref 0 -> 0, step: 1
889 09:57:33.868636
890 09:57:33.872161 RX Delay -130 -> 252, step: 16
891 09:57:33.875311 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
892 09:57:33.878593 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
893 09:57:33.882381 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
894 09:57:33.888838 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
895 09:57:33.891904 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
896 09:57:33.895118 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
897 09:57:33.898403 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
898 09:57:33.902041 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
899 09:57:33.908551 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
900 09:57:33.911906 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
901 09:57:33.915116 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
902 09:57:33.918390 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
903 09:57:33.921917 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
904 09:57:33.928485 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
905 09:57:33.931828 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
906 09:57:33.935251 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
907 09:57:33.935332 ==
908 09:57:33.938606 Dram Type= 6, Freq= 0, CH_0, rank 0
909 09:57:33.941941 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
910 09:57:33.942024 ==
911 09:57:33.944972 DQS Delay:
912 09:57:33.945054 DQS0 = 0, DQS1 = 0
913 09:57:33.948554 DQM Delay:
914 09:57:33.948636 DQM0 = 83, DQM1 = 74
915 09:57:33.948701 DQ Delay:
916 09:57:33.951871 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
917 09:57:33.955315 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =101
918 09:57:33.958477 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
919 09:57:33.961790 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
920 09:57:33.961872
921 09:57:33.961936
922 09:57:33.965220 ==
923 09:57:33.965301 Dram Type= 6, Freq= 0, CH_0, rank 0
924 09:57:33.971972 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
925 09:57:33.972054 ==
926 09:57:33.972119
927 09:57:33.972178
928 09:57:33.975086 TX Vref Scan disable
929 09:57:33.975168 == TX Byte 0 ==
930 09:57:33.978342 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
931 09:57:33.984958 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
932 09:57:33.985040 == TX Byte 1 ==
933 09:57:33.988565 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
934 09:57:33.995024 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
935 09:57:33.995106 ==
936 09:57:33.998413 Dram Type= 6, Freq= 0, CH_0, rank 0
937 09:57:34.001897 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
938 09:57:34.001980 ==
939 09:57:34.014726 TX Vref=22, minBit 0, minWin=27, winSum=443
940 09:57:34.017815 TX Vref=24, minBit 0, minWin=27, winSum=445
941 09:57:34.021251 TX Vref=26, minBit 4, minWin=27, winSum=451
942 09:57:34.024695 TX Vref=28, minBit 2, minWin=28, winSum=457
943 09:57:34.027975 TX Vref=30, minBit 0, minWin=28, winSum=455
944 09:57:34.031225 TX Vref=32, minBit 0, minWin=28, winSum=453
945 09:57:34.037935 [TxChooseVref] Worse bit 2, Min win 28, Win sum 457, Final Vref 28
946 09:57:34.038017
947 09:57:34.041342 Final TX Range 1 Vref 28
948 09:57:34.041423
949 09:57:34.041487 ==
950 09:57:34.044540 Dram Type= 6, Freq= 0, CH_0, rank 0
951 09:57:34.047747 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
952 09:57:34.047828 ==
953 09:57:34.047892
954 09:57:34.051044
955 09:57:34.051125 TX Vref Scan disable
956 09:57:34.054406 == TX Byte 0 ==
957 09:57:34.058592 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
958 09:57:34.061867 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
959 09:57:34.065350 == TX Byte 1 ==
960 09:57:34.068487 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
961 09:57:34.072375 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
962 09:57:34.072476
963 09:57:34.075589 [DATLAT]
964 09:57:34.075670 Freq=800, CH0 RK0
965 09:57:34.075735
966 09:57:34.078698 DATLAT Default: 0xa
967 09:57:34.078778 0, 0xFFFF, sum = 0
968 09:57:34.081921 1, 0xFFFF, sum = 0
969 09:57:34.082006 2, 0xFFFF, sum = 0
970 09:57:34.085513 3, 0xFFFF, sum = 0
971 09:57:34.085596 4, 0xFFFF, sum = 0
972 09:57:34.088863 5, 0xFFFF, sum = 0
973 09:57:34.088946 6, 0xFFFF, sum = 0
974 09:57:34.091908 7, 0xFFFF, sum = 0
975 09:57:34.091990 8, 0x0, sum = 1
976 09:57:34.095693 9, 0x0, sum = 2
977 09:57:34.095776 10, 0x0, sum = 3
978 09:57:34.098734 11, 0x0, sum = 4
979 09:57:34.098816 best_step = 9
980 09:57:34.098881
981 09:57:34.098940 ==
982 09:57:34.102236 Dram Type= 6, Freq= 0, CH_0, rank 0
983 09:57:34.105335 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
984 09:57:34.105416 ==
985 09:57:34.108550 RX Vref Scan: 1
986 09:57:34.108633
987 09:57:34.112279 Set Vref Range= 32 -> 127
988 09:57:34.112360
989 09:57:34.112424 RX Vref 32 -> 127, step: 1
990 09:57:34.112484
991 09:57:34.115340 RX Delay -111 -> 252, step: 8
992 09:57:34.115422
993 09:57:34.118873 Set Vref, RX VrefLevel [Byte0]: 32
994 09:57:34.121896 [Byte1]: 32
995 09:57:34.125395
996 09:57:34.125491 Set Vref, RX VrefLevel [Byte0]: 33
997 09:57:34.128766 [Byte1]: 33
998 09:57:34.133003
999 09:57:34.133084 Set Vref, RX VrefLevel [Byte0]: 34
1000 09:57:34.136531 [Byte1]: 34
1001 09:57:34.141254
1002 09:57:34.141335 Set Vref, RX VrefLevel [Byte0]: 35
1003 09:57:34.144065 [Byte1]: 35
1004 09:57:34.148469
1005 09:57:34.148557 Set Vref, RX VrefLevel [Byte0]: 36
1006 09:57:34.152041 [Byte1]: 36
1007 09:57:34.156105
1008 09:57:34.156186 Set Vref, RX VrefLevel [Byte0]: 37
1009 09:57:34.159177 [Byte1]: 37
1010 09:57:34.163649
1011 09:57:34.163731 Set Vref, RX VrefLevel [Byte0]: 38
1012 09:57:34.167011 [Byte1]: 38
1013 09:57:34.171400
1014 09:57:34.171481 Set Vref, RX VrefLevel [Byte0]: 39
1015 09:57:34.174599 [Byte1]: 39
1016 09:57:34.179193
1017 09:57:34.179274 Set Vref, RX VrefLevel [Byte0]: 40
1018 09:57:34.182351 [Byte1]: 40
1019 09:57:34.186536
1020 09:57:34.186617 Set Vref, RX VrefLevel [Byte0]: 41
1021 09:57:34.190182 [Byte1]: 41
1022 09:57:34.194361
1023 09:57:34.194437 Set Vref, RX VrefLevel [Byte0]: 42
1024 09:57:34.197948 [Byte1]: 42
1025 09:57:34.201947
1026 09:57:34.202021 Set Vref, RX VrefLevel [Byte0]: 43
1027 09:57:34.205259 [Byte1]: 43
1028 09:57:34.209523
1029 09:57:34.209599 Set Vref, RX VrefLevel [Byte0]: 44
1030 09:57:34.212990 [Byte1]: 44
1031 09:57:34.217292
1032 09:57:34.217374 Set Vref, RX VrefLevel [Byte0]: 45
1033 09:57:34.220408 [Byte1]: 45
1034 09:57:34.225371
1035 09:57:34.225445 Set Vref, RX VrefLevel [Byte0]: 46
1036 09:57:34.228413 [Byte1]: 46
1037 09:57:34.232790
1038 09:57:34.232870 Set Vref, RX VrefLevel [Byte0]: 47
1039 09:57:34.236028 [Byte1]: 47
1040 09:57:34.240193
1041 09:57:34.240273 Set Vref, RX VrefLevel [Byte0]: 48
1042 09:57:34.243529 [Byte1]: 48
1043 09:57:34.247919
1044 09:57:34.248000 Set Vref, RX VrefLevel [Byte0]: 49
1045 09:57:34.251238 [Byte1]: 49
1046 09:57:34.255533
1047 09:57:34.255608 Set Vref, RX VrefLevel [Byte0]: 50
1048 09:57:34.258699 [Byte1]: 50
1049 09:57:34.263214
1050 09:57:34.263291 Set Vref, RX VrefLevel [Byte0]: 51
1051 09:57:34.266349 [Byte1]: 51
1052 09:57:34.270660
1053 09:57:34.270742 Set Vref, RX VrefLevel [Byte0]: 52
1054 09:57:34.274061 [Byte1]: 52
1055 09:57:34.278307
1056 09:57:34.278381 Set Vref, RX VrefLevel [Byte0]: 53
1057 09:57:34.281908 [Byte1]: 53
1058 09:57:34.285914
1059 09:57:34.286018 Set Vref, RX VrefLevel [Byte0]: 54
1060 09:57:34.289650 [Byte1]: 54
1061 09:57:34.293944
1062 09:57:34.294032 Set Vref, RX VrefLevel [Byte0]: 55
1063 09:57:34.297222 [Byte1]: 55
1064 09:57:34.301301
1065 09:57:34.301378 Set Vref, RX VrefLevel [Byte0]: 56
1066 09:57:34.304722 [Byte1]: 56
1067 09:57:34.308933
1068 09:57:34.309004 Set Vref, RX VrefLevel [Byte0]: 57
1069 09:57:34.312491 [Byte1]: 57
1070 09:57:34.317055
1071 09:57:34.317134 Set Vref, RX VrefLevel [Byte0]: 58
1072 09:57:34.320074 [Byte1]: 58
1073 09:57:34.324793
1074 09:57:34.324873 Set Vref, RX VrefLevel [Byte0]: 59
1075 09:57:34.328085 [Byte1]: 59
1076 09:57:34.332792
1077 09:57:34.332878 Set Vref, RX VrefLevel [Byte0]: 60
1078 09:57:34.335599 [Byte1]: 60
1079 09:57:34.339958
1080 09:57:34.340043 Set Vref, RX VrefLevel [Byte0]: 61
1081 09:57:34.343350 [Byte1]: 61
1082 09:57:34.347780
1083 09:57:34.347858 Set Vref, RX VrefLevel [Byte0]: 62
1084 09:57:34.350657 [Byte1]: 62
1085 09:57:34.354636
1086 09:57:34.358088 Set Vref, RX VrefLevel [Byte0]: 63
1087 09:57:34.358205 [Byte1]: 63
1088 09:57:34.362597
1089 09:57:34.362671 Set Vref, RX VrefLevel [Byte0]: 64
1090 09:57:34.366026 [Byte1]: 64
1091 09:57:34.370019
1092 09:57:34.370092 Set Vref, RX VrefLevel [Byte0]: 65
1093 09:57:34.376514 [Byte1]: 65
1094 09:57:34.376619
1095 09:57:34.380186 Set Vref, RX VrefLevel [Byte0]: 66
1096 09:57:34.383132 [Byte1]: 66
1097 09:57:34.383205
1098 09:57:34.386518 Set Vref, RX VrefLevel [Byte0]: 67
1099 09:57:34.390265 [Byte1]: 67
1100 09:57:34.390336
1101 09:57:34.393306 Set Vref, RX VrefLevel [Byte0]: 68
1102 09:57:34.396730 [Byte1]: 68
1103 09:57:34.400842
1104 09:57:34.400921 Set Vref, RX VrefLevel [Byte0]: 69
1105 09:57:34.403844 [Byte1]: 69
1106 09:57:34.408398
1107 09:57:34.408469 Set Vref, RX VrefLevel [Byte0]: 70
1108 09:57:34.411855 [Byte1]: 70
1109 09:57:34.416006
1110 09:57:34.416081 Set Vref, RX VrefLevel [Byte0]: 71
1111 09:57:34.419275 [Byte1]: 71
1112 09:57:34.423860
1113 09:57:34.423935 Set Vref, RX VrefLevel [Byte0]: 72
1114 09:57:34.426794 [Byte1]: 72
1115 09:57:34.431338
1116 09:57:34.431413 Set Vref, RX VrefLevel [Byte0]: 73
1117 09:57:34.434566 [Byte1]: 73
1118 09:57:34.438955
1119 09:57:34.439028 Set Vref, RX VrefLevel [Byte0]: 74
1120 09:57:34.442588 [Byte1]: 74
1121 09:57:34.446379
1122 09:57:34.446462 Set Vref, RX VrefLevel [Byte0]: 75
1123 09:57:34.450170 [Byte1]: 75
1124 09:57:34.454570
1125 09:57:34.454643 Set Vref, RX VrefLevel [Byte0]: 76
1126 09:57:34.457550 [Byte1]: 76
1127 09:57:34.461862
1128 09:57:34.461947 Final RX Vref Byte 0 = 54 to rank0
1129 09:57:34.465240 Final RX Vref Byte 1 = 50 to rank0
1130 09:57:34.468406 Final RX Vref Byte 0 = 54 to rank1
1131 09:57:34.471877 Final RX Vref Byte 1 = 50 to rank1==
1132 09:57:34.475314 Dram Type= 6, Freq= 0, CH_0, rank 0
1133 09:57:34.481699 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1134 09:57:34.481785 ==
1135 09:57:34.481889 DQS Delay:
1136 09:57:34.481954 DQS0 = 0, DQS1 = 0
1137 09:57:34.485389 DQM Delay:
1138 09:57:34.485498 DQM0 = 83, DQM1 = 73
1139 09:57:34.488503 DQ Delay:
1140 09:57:34.491800 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1141 09:57:34.491879 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1142 09:57:34.495179 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1143 09:57:34.498526 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1144 09:57:34.501687
1145 09:57:34.501782
1146 09:57:34.508512 [DQSOSCAuto] RK0, (LSB)MR18= 0x3838, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1147 09:57:34.511662 CH0 RK0: MR19=606, MR18=3838
1148 09:57:34.518158 CH0_RK0: MR19=0x606, MR18=0x3838, DQSOSC=395, MR23=63, INC=94, DEC=63
1149 09:57:34.518235
1150 09:57:34.521626 ----->DramcWriteLeveling(PI) begin...
1151 09:57:34.521724 ==
1152 09:57:34.525205 Dram Type= 6, Freq= 0, CH_0, rank 1
1153 09:57:34.528445 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1154 09:57:34.528586 ==
1155 09:57:34.531653 Write leveling (Byte 0): 31 => 31
1156 09:57:34.534981 Write leveling (Byte 1): 29 => 29
1157 09:57:34.538208 DramcWriteLeveling(PI) end<-----
1158 09:57:34.538288
1159 09:57:34.538351 ==
1160 09:57:34.541679 Dram Type= 6, Freq= 0, CH_0, rank 1
1161 09:57:34.545056 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1162 09:57:34.545135 ==
1163 09:57:34.548324 [Gating] SW mode calibration
1164 09:57:34.554850 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1165 09:57:34.561353 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1166 09:57:34.564771 0 6 0 | B1->B0 | 3333 2f2f | 0 1 | (0 1) (1 0)
1167 09:57:34.567995 0 6 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1168 09:57:34.574811 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 09:57:34.578463 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 09:57:34.581487 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 09:57:34.588067 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 09:57:34.591311 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 09:57:34.594648 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 09:57:34.601431 0 7 0 | B1->B0 | 2828 3131 | 0 1 | (1 1) (0 0)
1175 09:57:34.604869 0 7 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1176 09:57:34.608412 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1177 09:57:34.614770 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1178 09:57:34.618433 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1179 09:57:34.621313 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1180 09:57:34.628261 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1181 09:57:34.631352 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1182 09:57:34.635165 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1183 09:57:34.641441 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1184 09:57:34.645092 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1185 09:57:34.648271 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1186 09:57:34.654646 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1187 09:57:34.658100 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1188 09:57:34.661469 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1189 09:57:34.664648 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1190 09:57:34.671209 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1191 09:57:34.674518 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1192 09:57:34.678101 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 09:57:34.684844 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 09:57:34.688139 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 09:57:34.691241 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 09:57:34.698235 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 09:57:34.701350 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 09:57:34.704738 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1199 09:57:34.711624 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 09:57:34.711699 Total UI for P1: 0, mck2ui 16
1201 09:57:34.718149 best dqsien dly found for B0: ( 0, 10, 0)
1202 09:57:34.718232 Total UI for P1: 0, mck2ui 16
1203 09:57:34.721892 best dqsien dly found for B1: ( 0, 10, 0)
1204 09:57:34.728109 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1205 09:57:34.731391 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1206 09:57:34.731471
1207 09:57:34.734694 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1208 09:57:34.774601 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1209 09:57:34.774759 [Gating] SW calibration Done
1210 09:57:34.774912 ==
1211 09:57:34.775203 Dram Type= 6, Freq= 0, CH_0, rank 1
1212 09:57:34.775312 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1213 09:57:34.775414 ==
1214 09:57:34.775549 RX Vref Scan: 0
1215 09:57:34.775611
1216 09:57:34.775669 RX Vref 0 -> 0, step: 1
1217 09:57:34.775725
1218 09:57:34.775849 RX Delay -130 -> 252, step: 16
1219 09:57:34.775924 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1220 09:57:34.775979 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1221 09:57:34.776033 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1222 09:57:34.776138 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1223 09:57:34.778948 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1224 09:57:34.779029 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1225 09:57:34.782196 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1226 09:57:34.785686 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1227 09:57:34.792177 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1228 09:57:34.795736 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1229 09:57:34.798913 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1230 09:57:34.802193 iDelay=222, Bit 11, Center 61 (-50 ~ 173) 224
1231 09:57:34.805620 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1232 09:57:34.812172 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1233 09:57:34.815567 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1234 09:57:34.818890 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1235 09:57:34.818964 ==
1236 09:57:34.822710 Dram Type= 6, Freq= 0, CH_0, rank 1
1237 09:57:34.825631 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1238 09:57:34.829001 ==
1239 09:57:34.829087 DQS Delay:
1240 09:57:34.829151 DQS0 = 0, DQS1 = 0
1241 09:57:34.832345 DQM Delay:
1242 09:57:34.832422 DQM0 = 82, DQM1 = 72
1243 09:57:34.835696 DQ Delay:
1244 09:57:34.835785 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
1245 09:57:34.838879 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1246 09:57:34.842094 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1247 09:57:34.845354 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1248 09:57:34.845437
1249 09:57:34.848847
1250 09:57:34.848927 ==
1251 09:57:34.852357 Dram Type= 6, Freq= 0, CH_0, rank 1
1252 09:57:34.855646 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1253 09:57:34.855728 ==
1254 09:57:34.855793
1255 09:57:34.855853
1256 09:57:34.859129 TX Vref Scan disable
1257 09:57:34.859244 == TX Byte 0 ==
1258 09:57:34.865621 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1259 09:57:34.868805 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1260 09:57:34.868887 == TX Byte 1 ==
1261 09:57:34.875474 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1262 09:57:34.878991 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1263 09:57:34.879072 ==
1264 09:57:34.882267 Dram Type= 6, Freq= 0, CH_0, rank 1
1265 09:57:34.885275 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1266 09:57:34.885356 ==
1267 09:57:34.899014 TX Vref=22, minBit 0, minWin=28, winSum=450
1268 09:57:34.902551 TX Vref=24, minBit 0, minWin=28, winSum=451
1269 09:57:34.906430 TX Vref=26, minBit 2, minWin=28, winSum=453
1270 09:57:34.909913 TX Vref=28, minBit 2, minWin=28, winSum=457
1271 09:57:34.913630 TX Vref=30, minBit 3, minWin=28, winSum=458
1272 09:57:34.917333 TX Vref=32, minBit 2, minWin=28, winSum=459
1273 09:57:34.924056 [TxChooseVref] Worse bit 2, Min win 28, Win sum 459, Final Vref 32
1274 09:57:34.924139
1275 09:57:34.924209 Final TX Range 1 Vref 32
1276 09:57:34.924270
1277 09:57:34.927516 ==
1278 09:57:34.931035 Dram Type= 6, Freq= 0, CH_0, rank 1
1279 09:57:34.934594 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1280 09:57:34.934665 ==
1281 09:57:34.934727
1282 09:57:34.934788
1283 09:57:34.934845 TX Vref Scan disable
1284 09:57:34.938866 == TX Byte 0 ==
1285 09:57:34.942541 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1286 09:57:34.945889 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1287 09:57:34.948921 == TX Byte 1 ==
1288 09:57:34.952359 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1289 09:57:34.955447 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1290 09:57:34.958949
1291 09:57:34.959030 [DATLAT]
1292 09:57:34.959094 Freq=800, CH0 RK1
1293 09:57:34.959172
1294 09:57:34.962331 DATLAT Default: 0x9
1295 09:57:34.962410 0, 0xFFFF, sum = 0
1296 09:57:34.965959 1, 0xFFFF, sum = 0
1297 09:57:34.966040 2, 0xFFFF, sum = 0
1298 09:57:34.969063 3, 0xFFFF, sum = 0
1299 09:57:34.969145 4, 0xFFFF, sum = 0
1300 09:57:34.972235 5, 0xFFFF, sum = 0
1301 09:57:34.972316 6, 0xFFFF, sum = 0
1302 09:57:34.975647 7, 0xFFFF, sum = 0
1303 09:57:34.975728 8, 0x0, sum = 1
1304 09:57:34.979146 9, 0x0, sum = 2
1305 09:57:34.979227 10, 0x0, sum = 3
1306 09:57:34.982264 11, 0x0, sum = 4
1307 09:57:34.982345 best_step = 9
1308 09:57:34.982408
1309 09:57:34.982467 ==
1310 09:57:34.985333 Dram Type= 6, Freq= 0, CH_0, rank 1
1311 09:57:34.992114 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1312 09:57:34.992195 ==
1313 09:57:34.992259 RX Vref Scan: 0
1314 09:57:34.992319
1315 09:57:34.995303 RX Vref 0 -> 0, step: 1
1316 09:57:34.995383
1317 09:57:34.998949 RX Delay -111 -> 252, step: 8
1318 09:57:35.002347 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1319 09:57:35.005246 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1320 09:57:35.012268 iDelay=217, Bit 2, Center 88 (-31 ~ 208) 240
1321 09:57:35.015347 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1322 09:57:35.018726 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1323 09:57:35.022145 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1324 09:57:35.025310 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1325 09:57:35.031895 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1326 09:57:35.035407 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1327 09:57:35.039013 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1328 09:57:35.041844 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1329 09:57:35.045511 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1330 09:57:35.051971 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1331 09:57:35.055099 iDelay=217, Bit 13, Center 80 (-31 ~ 192) 224
1332 09:57:35.058723 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1333 09:57:35.062002 iDelay=217, Bit 15, Center 80 (-31 ~ 192) 224
1334 09:57:35.062082 ==
1335 09:57:35.065401 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 09:57:35.072005 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1337 09:57:35.072086 ==
1338 09:57:35.072150 DQS Delay:
1339 09:57:35.072209 DQS0 = 0, DQS1 = 0
1340 09:57:35.075246 DQM Delay:
1341 09:57:35.075326 DQM0 = 87, DQM1 = 74
1342 09:57:35.078626 DQ Delay:
1343 09:57:35.081911 DQ0 =84, DQ1 =88, DQ2 =88, DQ3 =84
1344 09:57:35.081991 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1345 09:57:35.085180 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =64
1346 09:57:35.092098 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =80
1347 09:57:35.092178
1348 09:57:35.092240
1349 09:57:35.098553 [DQSOSCAuto] RK1, (LSB)MR18= 0x4343, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1350 09:57:35.102151 CH0 RK1: MR19=606, MR18=4343
1351 09:57:35.108678 CH0_RK1: MR19=0x606, MR18=0x4343, DQSOSC=393, MR23=63, INC=95, DEC=63
1352 09:57:35.112095 [RxdqsGatingPostProcess] freq 800
1353 09:57:35.115417 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1354 09:57:35.118642 Pre-setting of DQS Precalculation
1355 09:57:35.125245 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1356 09:57:35.125322 ==
1357 09:57:35.128403 Dram Type= 6, Freq= 0, CH_1, rank 0
1358 09:57:35.131919 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1359 09:57:35.131996 ==
1360 09:57:35.138576 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1361 09:57:35.141719 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1362 09:57:35.151540 [CA 0] Center 36 (6~67) winsize 62
1363 09:57:35.154918 [CA 1] Center 36 (6~67) winsize 62
1364 09:57:35.158265 [CA 2] Center 34 (4~65) winsize 62
1365 09:57:35.161848 [CA 3] Center 34 (4~65) winsize 62
1366 09:57:35.165095 [CA 4] Center 33 (2~64) winsize 63
1367 09:57:35.168441 [CA 5] Center 33 (3~63) winsize 61
1368 09:57:35.168536
1369 09:57:35.171808 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1370 09:57:35.171873
1371 09:57:35.174923 [CATrainingPosCal] consider 1 rank data
1372 09:57:35.178245 u2DelayCellTimex100 = 270/100 ps
1373 09:57:35.181767 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1374 09:57:35.185083 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1375 09:57:35.191698 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1376 09:57:35.194965 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1377 09:57:35.198190 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
1378 09:57:35.201541 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
1379 09:57:35.201610
1380 09:57:35.204817 CA PerBit enable=1, Macro0, CA PI delay=33
1381 09:57:35.204885
1382 09:57:35.208323 [CBTSetCACLKResult] CA Dly = 33
1383 09:57:35.208387 CS Dly: 4 (0~35)
1384 09:57:35.208451 ==
1385 09:57:35.211551 Dram Type= 6, Freq= 0, CH_1, rank 1
1386 09:57:35.218218 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1387 09:57:35.218286 ==
1388 09:57:35.221446 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1389 09:57:35.228396 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1390 09:57:35.237760 [CA 0] Center 36 (6~67) winsize 62
1391 09:57:35.240944 [CA 1] Center 36 (5~67) winsize 63
1392 09:57:35.244158 [CA 2] Center 34 (4~65) winsize 62
1393 09:57:35.247652 [CA 3] Center 34 (4~65) winsize 62
1394 09:57:35.250823 [CA 4] Center 33 (3~64) winsize 62
1395 09:57:35.254173 [CA 5] Center 33 (3~64) winsize 62
1396 09:57:35.254243
1397 09:57:35.257718 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1398 09:57:35.257795
1399 09:57:35.261040 [CATrainingPosCal] consider 2 rank data
1400 09:57:35.264279 u2DelayCellTimex100 = 270/100 ps
1401 09:57:35.267695 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1402 09:57:35.270766 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1403 09:57:35.274392 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1404 09:57:35.280945 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1405 09:57:35.284348 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1406 09:57:35.287406 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
1407 09:57:35.287486
1408 09:57:35.290987 CA PerBit enable=1, Macro0, CA PI delay=33
1409 09:57:35.291067
1410 09:57:35.294046 [CBTSetCACLKResult] CA Dly = 33
1411 09:57:35.294126 CS Dly: 4 (0~36)
1412 09:57:35.294190
1413 09:57:35.297522 ----->DramcWriteLeveling(PI) begin...
1414 09:57:35.297603 ==
1415 09:57:35.300928 Dram Type= 6, Freq= 0, CH_1, rank 0
1416 09:57:35.307727 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1417 09:57:35.307810 ==
1418 09:57:35.311074 Write leveling (Byte 0): 26 => 26
1419 09:57:35.314282 Write leveling (Byte 1): 25 => 25
1420 09:57:35.314361 DramcWriteLeveling(PI) end<-----
1421 09:57:35.317386
1422 09:57:35.317465 ==
1423 09:57:35.320918 Dram Type= 6, Freq= 0, CH_1, rank 0
1424 09:57:35.324503 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1425 09:57:35.324603 ==
1426 09:57:35.327578 [Gating] SW mode calibration
1427 09:57:35.334090 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1428 09:57:35.337678 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1429 09:57:35.344106 0 6 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
1430 09:57:35.347430 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1431 09:57:35.350645 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1432 09:57:35.357602 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1433 09:57:35.360748 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1434 09:57:35.364354 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1435 09:57:35.370714 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1436 09:57:35.374151 0 6 28 | B1->B0 | 2525 2b2b | 0 0 | (1 1) (0 0)
1437 09:57:35.377477 0 7 0 | B1->B0 | 3030 3e3e | 0 0 | (0 0) (0 0)
1438 09:57:35.384140 0 7 4 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1439 09:57:35.387570 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1440 09:57:35.390663 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1441 09:57:35.397421 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1442 09:57:35.400755 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1443 09:57:35.404201 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1444 09:57:35.407282 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1445 09:57:35.414347 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1446 09:57:35.417550 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1447 09:57:35.420875 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1448 09:57:35.427597 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1449 09:57:35.431174 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1450 09:57:35.434377 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1451 09:57:35.440857 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1452 09:57:35.444278 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1453 09:57:35.447282 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1454 09:57:35.453998 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1455 09:57:35.457439 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1456 09:57:35.460688 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1457 09:57:35.467448 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1458 09:57:35.470822 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1459 09:57:35.474226 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1460 09:57:35.480880 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1461 09:57:35.484125 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1462 09:57:35.487691 Total UI for P1: 0, mck2ui 16
1463 09:57:35.491003 best dqsien dly found for B0: ( 0, 9, 30)
1464 09:57:35.494291 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1465 09:57:35.497675 Total UI for P1: 0, mck2ui 16
1466 09:57:35.500947 best dqsien dly found for B1: ( 0, 10, 0)
1467 09:57:35.504074 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1468 09:57:35.507495 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1469 09:57:35.507575
1470 09:57:35.510794 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1471 09:57:35.517573 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1472 09:57:35.517654 [Gating] SW calibration Done
1473 09:57:35.517718 ==
1474 09:57:35.520747 Dram Type= 6, Freq= 0, CH_1, rank 0
1475 09:57:35.527514 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1476 09:57:35.527595 ==
1477 09:57:35.527658 RX Vref Scan: 0
1478 09:57:35.527716
1479 09:57:35.531064 RX Vref 0 -> 0, step: 1
1480 09:57:35.531145
1481 09:57:35.534317 RX Delay -130 -> 252, step: 16
1482 09:57:35.537514 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1483 09:57:35.540993 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1484 09:57:35.544282 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1485 09:57:35.547582 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1486 09:57:35.554269 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1487 09:57:35.557723 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1488 09:57:35.561066 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1489 09:57:35.564432 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1490 09:57:35.568235 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1491 09:57:35.575049 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1492 09:57:35.578538 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1493 09:57:35.582405 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1494 09:57:35.585726 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1495 09:57:35.589076 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1496 09:57:35.592802 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1497 09:57:35.596778 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1498 09:57:35.596859 ==
1499 09:57:35.600183 Dram Type= 6, Freq= 0, CH_1, rank 0
1500 09:57:35.604209 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1501 09:57:35.604290 ==
1502 09:57:35.607552 DQS Delay:
1503 09:57:35.607631 DQS0 = 0, DQS1 = 0
1504 09:57:35.610639 DQM Delay:
1505 09:57:35.610718 DQM0 = 80, DQM1 = 70
1506 09:57:35.610781 DQ Delay:
1507 09:57:35.614058 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1508 09:57:35.617492 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1509 09:57:35.620975 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1510 09:57:35.624289 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1511 09:57:35.624370
1512 09:57:35.624433
1513 09:57:35.624492 ==
1514 09:57:35.627601 Dram Type= 6, Freq= 0, CH_1, rank 0
1515 09:57:35.634198 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1516 09:57:35.634280 ==
1517 09:57:35.634344
1518 09:57:35.634404
1519 09:57:35.634461 TX Vref Scan disable
1520 09:57:35.637732 == TX Byte 0 ==
1521 09:57:35.641093 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1522 09:57:35.644610 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1523 09:57:35.647759 == TX Byte 1 ==
1524 09:57:35.651238 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1525 09:57:35.654411 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1526 09:57:35.657917 ==
1527 09:57:35.661310 Dram Type= 6, Freq= 0, CH_1, rank 0
1528 09:57:35.664295 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1529 09:57:35.664376 ==
1530 09:57:35.676989 TX Vref=22, minBit 3, minWin=27, winSum=445
1531 09:57:35.680121 TX Vref=24, minBit 3, minWin=27, winSum=444
1532 09:57:35.683542 TX Vref=26, minBit 3, minWin=27, winSum=454
1533 09:57:35.686929 TX Vref=28, minBit 0, minWin=28, winSum=454
1534 09:57:35.690015 TX Vref=30, minBit 2, minWin=28, winSum=458
1535 09:57:35.693267 TX Vref=32, minBit 2, minWin=28, winSum=453
1536 09:57:35.700057 [TxChooseVref] Worse bit 2, Min win 28, Win sum 458, Final Vref 30
1537 09:57:35.700138
1538 09:57:35.703439 Final TX Range 1 Vref 30
1539 09:57:35.703526
1540 09:57:35.703596 ==
1541 09:57:35.706599 Dram Type= 6, Freq= 0, CH_1, rank 0
1542 09:57:35.709927 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1543 09:57:35.710008 ==
1544 09:57:35.710072
1545 09:57:35.713310
1546 09:57:35.713390 TX Vref Scan disable
1547 09:57:35.716758 == TX Byte 0 ==
1548 09:57:35.720088 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1549 09:57:35.723459 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1550 09:57:35.726896 == TX Byte 1 ==
1551 09:57:35.730036 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1552 09:57:35.733172 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1553 09:57:35.736861
1554 09:57:35.736941 [DATLAT]
1555 09:57:35.737005 Freq=800, CH1 RK0
1556 09:57:35.737065
1557 09:57:35.739795 DATLAT Default: 0xa
1558 09:57:35.739876 0, 0xFFFF, sum = 0
1559 09:57:35.743341 1, 0xFFFF, sum = 0
1560 09:57:35.743423 2, 0xFFFF, sum = 0
1561 09:57:35.746857 3, 0xFFFF, sum = 0
1562 09:57:35.746939 4, 0xFFFF, sum = 0
1563 09:57:35.749879 5, 0xFFFF, sum = 0
1564 09:57:35.749961 6, 0xFFFF, sum = 0
1565 09:57:35.753099 7, 0xFFFF, sum = 0
1566 09:57:35.753181 8, 0x0, sum = 1
1567 09:57:35.756592 9, 0x0, sum = 2
1568 09:57:35.756675 10, 0x0, sum = 3
1569 09:57:35.759791 11, 0x0, sum = 4
1570 09:57:35.759873 best_step = 9
1571 09:57:35.759937
1572 09:57:35.759996 ==
1573 09:57:35.763204 Dram Type= 6, Freq= 0, CH_1, rank 0
1574 09:57:35.769659 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1575 09:57:35.769740 ==
1576 09:57:35.769804 RX Vref Scan: 1
1577 09:57:35.769863
1578 09:57:35.773221 Set Vref Range= 32 -> 127
1579 09:57:35.773301
1580 09:57:35.776767 RX Vref 32 -> 127, step: 1
1581 09:57:35.776848
1582 09:57:35.779628 RX Delay -111 -> 252, step: 8
1583 09:57:35.779709
1584 09:57:35.779773 Set Vref, RX VrefLevel [Byte0]: 32
1585 09:57:35.782999 [Byte1]: 32
1586 09:57:35.787380
1587 09:57:35.787460 Set Vref, RX VrefLevel [Byte0]: 33
1588 09:57:35.790795 [Byte1]: 33
1589 09:57:35.795099
1590 09:57:35.795180 Set Vref, RX VrefLevel [Byte0]: 34
1591 09:57:35.798692 [Byte1]: 34
1592 09:57:35.802895
1593 09:57:35.802975 Set Vref, RX VrefLevel [Byte0]: 35
1594 09:57:35.806151 [Byte1]: 35
1595 09:57:35.810394
1596 09:57:35.810475 Set Vref, RX VrefLevel [Byte0]: 36
1597 09:57:35.813676 [Byte1]: 36
1598 09:57:35.817922
1599 09:57:35.818002 Set Vref, RX VrefLevel [Byte0]: 37
1600 09:57:35.821347 [Byte1]: 37
1601 09:57:35.825863
1602 09:57:35.825944 Set Vref, RX VrefLevel [Byte0]: 38
1603 09:57:35.829066 [Byte1]: 38
1604 09:57:35.833343
1605 09:57:35.833424 Set Vref, RX VrefLevel [Byte0]: 39
1606 09:57:35.836839 [Byte1]: 39
1607 09:57:35.840886
1608 09:57:35.840967 Set Vref, RX VrefLevel [Byte0]: 40
1609 09:57:35.844724 [Byte1]: 40
1610 09:57:35.848890
1611 09:57:35.848970 Set Vref, RX VrefLevel [Byte0]: 41
1612 09:57:35.852059 [Byte1]: 41
1613 09:57:35.856389
1614 09:57:35.856496 Set Vref, RX VrefLevel [Byte0]: 42
1615 09:57:35.859518 [Byte1]: 42
1616 09:57:35.864112
1617 09:57:35.864192 Set Vref, RX VrefLevel [Byte0]: 43
1618 09:57:35.867248 [Byte1]: 43
1619 09:57:35.871507
1620 09:57:35.871588 Set Vref, RX VrefLevel [Byte0]: 44
1621 09:57:35.874737 [Byte1]: 44
1622 09:57:35.879340
1623 09:57:35.879420 Set Vref, RX VrefLevel [Byte0]: 45
1624 09:57:35.882437 [Byte1]: 45
1625 09:57:35.887022
1626 09:57:35.887103 Set Vref, RX VrefLevel [Byte0]: 46
1627 09:57:35.890187 [Byte1]: 46
1628 09:57:35.894531
1629 09:57:35.894612 Set Vref, RX VrefLevel [Byte0]: 47
1630 09:57:35.898124 [Byte1]: 47
1631 09:57:35.902402
1632 09:57:35.902483 Set Vref, RX VrefLevel [Byte0]: 48
1633 09:57:35.905437 [Byte1]: 48
1634 09:57:35.909837
1635 09:57:35.909917 Set Vref, RX VrefLevel [Byte0]: 49
1636 09:57:35.913289 [Byte1]: 49
1637 09:57:35.917509
1638 09:57:35.917590 Set Vref, RX VrefLevel [Byte0]: 50
1639 09:57:35.920615 [Byte1]: 50
1640 09:57:35.924906
1641 09:57:35.924986 Set Vref, RX VrefLevel [Byte0]: 51
1642 09:57:35.928433 [Byte1]: 51
1643 09:57:35.932690
1644 09:57:35.932771 Set Vref, RX VrefLevel [Byte0]: 52
1645 09:57:35.935988 [Byte1]: 52
1646 09:57:35.940354
1647 09:57:35.940460 Set Vref, RX VrefLevel [Byte0]: 53
1648 09:57:35.943992 [Byte1]: 53
1649 09:57:35.947933
1650 09:57:35.948013 Set Vref, RX VrefLevel [Byte0]: 54
1651 09:57:35.951456 [Byte1]: 54
1652 09:57:35.955639
1653 09:57:35.955719 Set Vref, RX VrefLevel [Byte0]: 55
1654 09:57:35.958847 [Byte1]: 55
1655 09:57:35.963461
1656 09:57:35.963540 Set Vref, RX VrefLevel [Byte0]: 56
1657 09:57:35.967004 [Byte1]: 56
1658 09:57:35.971099
1659 09:57:35.971179 Set Vref, RX VrefLevel [Byte0]: 57
1660 09:57:35.974412 [Byte1]: 57
1661 09:57:35.978809
1662 09:57:35.978889 Set Vref, RX VrefLevel [Byte0]: 58
1663 09:57:35.982053 [Byte1]: 58
1664 09:57:35.986484
1665 09:57:35.986569 Set Vref, RX VrefLevel [Byte0]: 59
1666 09:57:35.989650 [Byte1]: 59
1667 09:57:35.993795
1668 09:57:35.993894 Set Vref, RX VrefLevel [Byte0]: 60
1669 09:57:35.997151 [Byte1]: 60
1670 09:57:36.001496
1671 09:57:36.001605 Set Vref, RX VrefLevel [Byte0]: 61
1672 09:57:36.005078 [Byte1]: 61
1673 09:57:36.009326
1674 09:57:36.009458 Set Vref, RX VrefLevel [Byte0]: 62
1675 09:57:36.012318 [Byte1]: 62
1676 09:57:36.017114
1677 09:57:36.017194 Set Vref, RX VrefLevel [Byte0]: 63
1678 09:57:36.020103 [Byte1]: 63
1679 09:57:36.024484
1680 09:57:36.024605 Set Vref, RX VrefLevel [Byte0]: 64
1681 09:57:36.027707 [Byte1]: 64
1682 09:57:36.032136
1683 09:57:36.032219 Set Vref, RX VrefLevel [Byte0]: 65
1684 09:57:36.035333 [Byte1]: 65
1685 09:57:36.039636
1686 09:57:36.039717 Set Vref, RX VrefLevel [Byte0]: 66
1687 09:57:36.043044 [Byte1]: 66
1688 09:57:36.047666
1689 09:57:36.047746 Set Vref, RX VrefLevel [Byte0]: 67
1690 09:57:36.050638 [Byte1]: 67
1691 09:57:36.055350
1692 09:57:36.055430 Set Vref, RX VrefLevel [Byte0]: 68
1693 09:57:36.058641 [Byte1]: 68
1694 09:57:36.062586
1695 09:57:36.062666 Set Vref, RX VrefLevel [Byte0]: 69
1696 09:57:36.065952 [Byte1]: 69
1697 09:57:36.070726
1698 09:57:36.070806 Set Vref, RX VrefLevel [Byte0]: 70
1699 09:57:36.073728 [Byte1]: 70
1700 09:57:36.077849
1701 09:57:36.077929 Set Vref, RX VrefLevel [Byte0]: 71
1702 09:57:36.081280 [Byte1]: 71
1703 09:57:36.085631
1704 09:57:36.085712 Set Vref, RX VrefLevel [Byte0]: 72
1705 09:57:36.089076 [Byte1]: 72
1706 09:57:36.093561
1707 09:57:36.093641 Set Vref, RX VrefLevel [Byte0]: 73
1708 09:57:36.096706 [Byte1]: 73
1709 09:57:36.101101
1710 09:57:36.101182 Set Vref, RX VrefLevel [Byte0]: 74
1711 09:57:36.104169 [Byte1]: 74
1712 09:57:36.108786
1713 09:57:36.108866 Set Vref, RX VrefLevel [Byte0]: 75
1714 09:57:36.111967 [Byte1]: 75
1715 09:57:36.116654
1716 09:57:36.116735 Final RX Vref Byte 0 = 60 to rank0
1717 09:57:36.119783 Final RX Vref Byte 1 = 52 to rank0
1718 09:57:36.122993 Final RX Vref Byte 0 = 60 to rank1
1719 09:57:36.126240 Final RX Vref Byte 1 = 52 to rank1==
1720 09:57:36.129880 Dram Type= 6, Freq= 0, CH_1, rank 0
1721 09:57:36.136045 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1722 09:57:36.136130 ==
1723 09:57:36.136194 DQS Delay:
1724 09:57:36.136253 DQS0 = 0, DQS1 = 0
1725 09:57:36.139631 DQM Delay:
1726 09:57:36.139710 DQM0 = 79, DQM1 = 72
1727 09:57:36.143025 DQ Delay:
1728 09:57:36.146040 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1729 09:57:36.149768 DQ4 =76, DQ5 =92, DQ6 =88, DQ7 =76
1730 09:57:36.149850 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =64
1731 09:57:36.153405 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
1732 09:57:36.153486
1733 09:57:36.153549
1734 09:57:36.163538 [DQSOSCAuto] RK0, (LSB)MR18= 0x5050, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
1735 09:57:36.166804 CH1 RK0: MR19=606, MR18=5050
1736 09:57:36.170311 CH1_RK0: MR19=0x606, MR18=0x5050, DQSOSC=389, MR23=63, INC=97, DEC=65
1737 09:57:36.173792
1738 09:57:36.176549 ----->DramcWriteLeveling(PI) begin...
1739 09:57:36.176632 ==
1740 09:57:36.180036 Dram Type= 6, Freq= 0, CH_1, rank 1
1741 09:57:36.183500 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1742 09:57:36.183581 ==
1743 09:57:36.186640 Write leveling (Byte 0): 23 => 23
1744 09:57:36.190132 Write leveling (Byte 1): 24 => 24
1745 09:57:36.193694 DramcWriteLeveling(PI) end<-----
1746 09:57:36.193774
1747 09:57:36.193837 ==
1748 09:57:36.197078 Dram Type= 6, Freq= 0, CH_1, rank 1
1749 09:57:36.200072 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1750 09:57:36.200153 ==
1751 09:57:36.203497 [Gating] SW mode calibration
1752 09:57:36.210205 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1753 09:57:36.217009 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1754 09:57:36.220138 0 6 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
1755 09:57:36.223540 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1756 09:57:36.227153 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1757 09:57:36.233640 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1758 09:57:36.236763 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1759 09:57:36.240194 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1760 09:57:36.247346 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1761 09:57:36.250043 0 6 28 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
1762 09:57:36.253423 0 7 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
1763 09:57:36.260007 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1764 09:57:36.263383 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1765 09:57:36.266495 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1766 09:57:36.273452 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1767 09:57:36.277124 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1768 09:57:36.280176 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1769 09:57:36.286939 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1770 09:57:36.289982 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1771 09:57:36.293335 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1772 09:57:36.300333 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1773 09:57:36.303464 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1774 09:57:36.306642 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1775 09:57:36.313313 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1776 09:57:36.316677 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1777 09:57:36.319864 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1778 09:57:36.326802 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1779 09:57:36.329954 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1780 09:57:36.333474 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1781 09:57:36.336862 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1782 09:57:36.343201 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1783 09:57:36.346696 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1784 09:57:36.350072 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1785 09:57:36.356486 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1786 09:57:36.359859 Total UI for P1: 0, mck2ui 16
1787 09:57:36.363179 best dqsien dly found for B0: ( 0, 9, 24)
1788 09:57:36.366647 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1789 09:57:36.369897 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1790 09:57:36.373385 Total UI for P1: 0, mck2ui 16
1791 09:57:36.376645 best dqsien dly found for B1: ( 0, 10, 0)
1792 09:57:36.380062 best DQS0 dly(MCK, UI, PI) = (0, 9, 24)
1793 09:57:36.383556 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1794 09:57:36.383637
1795 09:57:36.390121 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 24)
1796 09:57:36.393394 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1797 09:57:36.393475 [Gating] SW calibration Done
1798 09:57:36.396809 ==
1799 09:57:36.400355 Dram Type= 6, Freq= 0, CH_1, rank 1
1800 09:57:36.403604 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1801 09:57:36.403685 ==
1802 09:57:36.403749 RX Vref Scan: 0
1803 09:57:36.403808
1804 09:57:36.406752 RX Vref 0 -> 0, step: 1
1805 09:57:36.406832
1806 09:57:36.410170 RX Delay -130 -> 252, step: 16
1807 09:57:36.413731 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1808 09:57:36.416973 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1809 09:57:36.420263 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1810 09:57:36.426739 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1811 09:57:36.430157 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1812 09:57:36.433260 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1813 09:57:36.436825 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1814 09:57:36.440240 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1815 09:57:36.446801 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1816 09:57:36.449958 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1817 09:57:36.453782 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1818 09:57:36.456661 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1819 09:57:36.460101 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1820 09:57:36.466729 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1821 09:57:36.469999 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1822 09:57:36.473564 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1823 09:57:36.473645 ==
1824 09:57:36.476716 Dram Type= 6, Freq= 0, CH_1, rank 1
1825 09:57:36.480008 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1826 09:57:36.483582 ==
1827 09:57:36.483662 DQS Delay:
1828 09:57:36.483727 DQS0 = 0, DQS1 = 0
1829 09:57:36.486706 DQM Delay:
1830 09:57:36.486786 DQM0 = 80, DQM1 = 71
1831 09:57:36.486850 DQ Delay:
1832 09:57:36.490322 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1833 09:57:36.493490 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1834 09:57:36.496663 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =69
1835 09:57:36.500209 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =77
1836 09:57:36.500289
1837 09:57:36.500353
1838 09:57:36.503663 ==
1839 09:57:36.507015 Dram Type= 6, Freq= 0, CH_1, rank 1
1840 09:57:36.510198 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1841 09:57:36.510278 ==
1842 09:57:36.510343
1843 09:57:36.510401
1844 09:57:36.513651 TX Vref Scan disable
1845 09:57:36.513731 == TX Byte 0 ==
1846 09:57:36.516928 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1847 09:57:36.523354 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1848 09:57:36.523435 == TX Byte 1 ==
1849 09:57:36.526835 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1850 09:57:36.533255 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1851 09:57:36.533336 ==
1852 09:57:36.536447 Dram Type= 6, Freq= 0, CH_1, rank 1
1853 09:57:36.540044 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1854 09:57:36.540125 ==
1855 09:57:36.553101 TX Vref=22, minBit 0, minWin=28, winSum=450
1856 09:57:36.556267 TX Vref=24, minBit 0, minWin=28, winSum=455
1857 09:57:36.559929 TX Vref=26, minBit 3, minWin=28, winSum=458
1858 09:57:36.563320 TX Vref=28, minBit 0, minWin=28, winSum=461
1859 09:57:36.566396 TX Vref=30, minBit 0, minWin=28, winSum=461
1860 09:57:36.572968 TX Vref=32, minBit 0, minWin=28, winSum=456
1861 09:57:36.576716 [TxChooseVref] Worse bit 0, Min win 28, Win sum 461, Final Vref 28
1862 09:57:36.576798
1863 09:57:36.580260 Final TX Range 1 Vref 28
1864 09:57:36.580341
1865 09:57:36.580405 ==
1866 09:57:36.583212 Dram Type= 6, Freq= 0, CH_1, rank 1
1867 09:57:36.586564 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1868 09:57:36.586646 ==
1869 09:57:36.586711
1870 09:57:36.589624
1871 09:57:36.589705 TX Vref Scan disable
1872 09:57:36.592865 == TX Byte 0 ==
1873 09:57:36.596428 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1874 09:57:36.602912 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1875 09:57:36.602993 == TX Byte 1 ==
1876 09:57:36.606290 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1877 09:57:36.609550 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1878 09:57:36.612899
1879 09:57:36.612979 [DATLAT]
1880 09:57:36.613044 Freq=800, CH1 RK1
1881 09:57:36.613104
1882 09:57:36.616469 DATLAT Default: 0x9
1883 09:57:36.616600 0, 0xFFFF, sum = 0
1884 09:57:36.619587 1, 0xFFFF, sum = 0
1885 09:57:36.619668 2, 0xFFFF, sum = 0
1886 09:57:36.622984 3, 0xFFFF, sum = 0
1887 09:57:36.623066 4, 0xFFFF, sum = 0
1888 09:57:36.626133 5, 0xFFFF, sum = 0
1889 09:57:36.629536 6, 0xFFFF, sum = 0
1890 09:57:36.629633 7, 0xFFFF, sum = 0
1891 09:57:36.629700 8, 0x0, sum = 1
1892 09:57:36.632979 9, 0x0, sum = 2
1893 09:57:36.633061 10, 0x0, sum = 3
1894 09:57:36.636464 11, 0x0, sum = 4
1895 09:57:36.636612 best_step = 9
1896 09:57:36.636703
1897 09:57:36.636793 ==
1898 09:57:36.639443 Dram Type= 6, Freq= 0, CH_1, rank 1
1899 09:57:36.646389 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1900 09:57:36.646470 ==
1901 09:57:36.646534 RX Vref Scan: 0
1902 09:57:36.646593
1903 09:57:36.649680 RX Vref 0 -> 0, step: 1
1904 09:57:36.649760
1905 09:57:36.653160 RX Delay -111 -> 252, step: 8
1906 09:57:36.656374 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1907 09:57:36.659787 iDelay=217, Bit 1, Center 80 (-39 ~ 200) 240
1908 09:57:36.666190 iDelay=217, Bit 2, Center 72 (-47 ~ 192) 240
1909 09:57:36.669929 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1910 09:57:36.673004 iDelay=217, Bit 4, Center 80 (-39 ~ 200) 240
1911 09:57:36.676398 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1912 09:57:36.679756 iDelay=217, Bit 6, Center 88 (-31 ~ 208) 240
1913 09:57:36.682951 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1914 09:57:36.689893 iDelay=217, Bit 8, Center 56 (-63 ~ 176) 240
1915 09:57:36.692934 iDelay=217, Bit 9, Center 56 (-63 ~ 176) 240
1916 09:57:36.696197 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1917 09:57:36.699661 iDelay=217, Bit 11, Center 64 (-55 ~ 184) 240
1918 09:57:36.702888 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1919 09:57:36.709679 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1920 09:57:36.712932 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1921 09:57:36.716668 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1922 09:57:36.716750 ==
1923 09:57:36.719636 Dram Type= 6, Freq= 0, CH_1, rank 1
1924 09:57:36.723255 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1925 09:57:36.726246 ==
1926 09:57:36.726352 DQS Delay:
1927 09:57:36.726444 DQS0 = 0, DQS1 = 0
1928 09:57:36.729604 DQM Delay:
1929 09:57:36.729712 DQM0 = 82, DQM1 = 72
1930 09:57:36.729779 DQ Delay:
1931 09:57:36.733840 DQ0 =84, DQ1 =80, DQ2 =72, DQ3 =80
1932 09:57:36.736502 DQ4 =80, DQ5 =96, DQ6 =88, DQ7 =80
1933 09:57:36.739951 DQ8 =56, DQ9 =56, DQ10 =72, DQ11 =64
1934 09:57:36.743101 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1935 09:57:36.743181
1936 09:57:36.743245
1937 09:57:36.753129 [DQSOSCAuto] RK1, (LSB)MR18= 0x4141, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1938 09:57:36.756728 CH1 RK1: MR19=606, MR18=4141
1939 09:57:36.763093 CH1_RK1: MR19=0x606, MR18=0x4141, DQSOSC=393, MR23=63, INC=95, DEC=63
1940 09:57:36.763175 [RxdqsGatingPostProcess] freq 800
1941 09:57:36.770074 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1942 09:57:36.773133 Pre-setting of DQS Precalculation
1943 09:57:36.776406 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1944 09:57:36.786625 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1945 09:57:36.793491 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1946 09:57:36.793573
1947 09:57:36.793637
1948 09:57:36.796721 [Calibration Summary] 1600 Mbps
1949 09:57:36.796802 CH 0, Rank 0
1950 09:57:36.800190 SW Impedance : PASS
1951 09:57:36.800271 DUTY Scan : NO K
1952 09:57:36.803221 ZQ Calibration : PASS
1953 09:57:36.806594 Jitter Meter : NO K
1954 09:57:36.806675 CBT Training : PASS
1955 09:57:36.809940 Write leveling : PASS
1956 09:57:36.813165 RX DQS gating : PASS
1957 09:57:36.813245 RX DQ/DQS(RDDQC) : PASS
1958 09:57:36.816859 TX DQ/DQS : PASS
1959 09:57:36.816940 RX DATLAT : PASS
1960 09:57:36.820048 RX DQ/DQS(Engine): PASS
1961 09:57:36.823198 TX OE : NO K
1962 09:57:36.823278 All Pass.
1963 09:57:36.823342
1964 09:57:36.823401 CH 0, Rank 1
1965 09:57:36.826210 SW Impedance : PASS
1966 09:57:36.829503 DUTY Scan : NO K
1967 09:57:36.829583 ZQ Calibration : PASS
1968 09:57:36.832949 Jitter Meter : NO K
1969 09:57:36.836088 CBT Training : PASS
1970 09:57:36.836169 Write leveling : PASS
1971 09:57:36.839501 RX DQS gating : PASS
1972 09:57:36.843173 RX DQ/DQS(RDDQC) : PASS
1973 09:57:36.843280 TX DQ/DQS : PASS
1974 09:57:36.846487 RX DATLAT : PASS
1975 09:57:36.849627 RX DQ/DQS(Engine): PASS
1976 09:57:36.849708 TX OE : NO K
1977 09:57:36.852885 All Pass.
1978 09:57:36.852966
1979 09:57:36.853030 CH 1, Rank 0
1980 09:57:36.856488 SW Impedance : PASS
1981 09:57:36.856578 DUTY Scan : NO K
1982 09:57:36.859835 ZQ Calibration : PASS
1983 09:57:36.862928 Jitter Meter : NO K
1984 09:57:36.863009 CBT Training : PASS
1985 09:57:36.866406 Write leveling : PASS
1986 09:57:36.866488 RX DQS gating : PASS
1987 09:57:36.869568 RX DQ/DQS(RDDQC) : PASS
1988 09:57:36.873027 TX DQ/DQS : PASS
1989 09:57:36.873108 RX DATLAT : PASS
1990 09:57:36.876449 RX DQ/DQS(Engine): PASS
1991 09:57:36.879729 TX OE : NO K
1992 09:57:36.879810 All Pass.
1993 09:57:36.879873
1994 09:57:36.879932 CH 1, Rank 1
1995 09:57:36.882935 SW Impedance : PASS
1996 09:57:36.886586 DUTY Scan : NO K
1997 09:57:36.886667 ZQ Calibration : PASS
1998 09:57:36.889522 Jitter Meter : NO K
1999 09:57:36.893130 CBT Training : PASS
2000 09:57:36.893210 Write leveling : PASS
2001 09:57:36.896335 RX DQS gating : PASS
2002 09:57:36.899981 RX DQ/DQS(RDDQC) : PASS
2003 09:57:36.900062 TX DQ/DQS : PASS
2004 09:57:36.903026 RX DATLAT : PASS
2005 09:57:36.906401 RX DQ/DQS(Engine): PASS
2006 09:57:36.906481 TX OE : NO K
2007 09:57:36.906546 All Pass.
2008 09:57:36.909650
2009 09:57:36.909730 DramC Write-DBI off
2010 09:57:36.912979 PER_BANK_REFRESH: Hybrid Mode
2011 09:57:36.913059 TX_TRACKING: ON
2012 09:57:36.916354 [GetDramInforAfterCalByMRR] Vendor 6.
2013 09:57:36.919790 [GetDramInforAfterCalByMRR] Revision 606.
2014 09:57:36.926201 [GetDramInforAfterCalByMRR] Revision 2 0.
2015 09:57:36.926283 MR0 0x3939
2016 09:57:36.926348 MR8 0x1111
2017 09:57:36.929663 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2018 09:57:36.929769
2019 09:57:36.932988 MR0 0x3939
2020 09:57:36.933069 MR8 0x1111
2021 09:57:36.936416 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2022 09:57:36.936497
2023 09:57:36.946414 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2024 09:57:36.949611 [FAST_K] Save calibration result to emmc
2025 09:57:36.953130 [FAST_K] Save calibration result to emmc
2026 09:57:36.956293 dram_init: config_dvfs: 1
2027 09:57:36.959782 dramc_set_vcore_voltage set vcore to 662500
2028 09:57:36.959863 Read voltage for 1200, 2
2029 09:57:36.962851 Vio18 = 0
2030 09:57:36.962932 Vcore = 662500
2031 09:57:36.962996 Vdram = 0
2032 09:57:36.966352 Vddq = 0
2033 09:57:36.966433 Vmddr = 0
2034 09:57:36.970029 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2035 09:57:36.976308 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2036 09:57:36.979513 MEM_TYPE=3, freq_sel=15
2037 09:57:36.983324 sv_algorithm_assistance_LP4_1600
2038 09:57:36.986239 ============ PULL DRAM RESETB DOWN ============
2039 09:57:36.989690 ========== PULL DRAM RESETB DOWN end =========
2040 09:57:36.996268 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2041 09:57:36.999954 ===================================
2042 09:57:37.000035 LPDDR4 DRAM CONFIGURATION
2043 09:57:37.003148 ===================================
2044 09:57:37.006776 EX_ROW_EN[0] = 0x0
2045 09:57:37.006856 EX_ROW_EN[1] = 0x0
2046 09:57:37.009642 LP4Y_EN = 0x0
2047 09:57:37.009722 WORK_FSP = 0x0
2048 09:57:37.013189 WL = 0x4
2049 09:57:37.013269 RL = 0x4
2050 09:57:37.016317 BL = 0x2
2051 09:57:37.019536 RPST = 0x0
2052 09:57:37.019616 RD_PRE = 0x0
2053 09:57:37.022790 WR_PRE = 0x1
2054 09:57:37.022870 WR_PST = 0x0
2055 09:57:37.026145 DBI_WR = 0x0
2056 09:57:37.026226 DBI_RD = 0x0
2057 09:57:37.029660 OTF = 0x1
2058 09:57:37.032623 ===================================
2059 09:57:37.036183 ===================================
2060 09:57:37.036286 ANA top config
2061 09:57:37.039637 ===================================
2062 09:57:37.042869 DLL_ASYNC_EN = 0
2063 09:57:37.046331 ALL_SLAVE_EN = 0
2064 09:57:37.046415 NEW_RANK_MODE = 1
2065 09:57:37.049791 DLL_IDLE_MODE = 1
2066 09:57:37.052895 LP45_APHY_COMB_EN = 1
2067 09:57:37.056117 TX_ODT_DIS = 1
2068 09:57:37.056199 NEW_8X_MODE = 1
2069 09:57:37.059392 ===================================
2070 09:57:37.062981 ===================================
2071 09:57:37.066482 data_rate = 2400
2072 09:57:37.069525 CKR = 1
2073 09:57:37.073006 DQ_P2S_RATIO = 8
2074 09:57:37.076258 ===================================
2075 09:57:37.079600 CA_P2S_RATIO = 8
2076 09:57:37.082882 DQ_CA_OPEN = 0
2077 09:57:37.082963 DQ_SEMI_OPEN = 0
2078 09:57:37.086182 CA_SEMI_OPEN = 0
2079 09:57:37.089737 CA_FULL_RATE = 0
2080 09:57:37.092855 DQ_CKDIV4_EN = 0
2081 09:57:37.096290 CA_CKDIV4_EN = 0
2082 09:57:37.099762 CA_PREDIV_EN = 0
2083 09:57:37.099843 PH8_DLY = 17
2084 09:57:37.102706 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2085 09:57:37.106492 DQ_AAMCK_DIV = 4
2086 09:57:37.109670 CA_AAMCK_DIV = 4
2087 09:57:37.112825 CA_ADMCK_DIV = 4
2088 09:57:37.116147 DQ_TRACK_CA_EN = 0
2089 09:57:37.116228 CA_PICK = 1200
2090 09:57:37.119281 CA_MCKIO = 1200
2091 09:57:37.122940 MCKIO_SEMI = 0
2092 09:57:37.126186 PLL_FREQ = 2366
2093 09:57:37.129261 DQ_UI_PI_RATIO = 32
2094 09:57:37.132681 CA_UI_PI_RATIO = 0
2095 09:57:37.136236 ===================================
2096 09:57:37.139534 ===================================
2097 09:57:37.142971 memory_type:LPDDR4
2098 09:57:37.143070 GP_NUM : 10
2099 09:57:37.146230 SRAM_EN : 1
2100 09:57:37.146309 MD32_EN : 0
2101 09:57:37.149294 ===================================
2102 09:57:37.152908 [ANA_INIT] >>>>>>>>>>>>>>
2103 09:57:37.156214 <<<<<< [CONFIGURE PHASE]: ANA_TX
2104 09:57:37.159525 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2105 09:57:37.162700 ===================================
2106 09:57:37.165969 data_rate = 2400,PCW = 0X5b00
2107 09:57:37.169388 ===================================
2108 09:57:37.172833 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2109 09:57:37.175957 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2110 09:57:37.182649 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2111 09:57:37.186134 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2112 09:57:37.192915 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2113 09:57:37.196330 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2114 09:57:37.196411 [ANA_INIT] flow start
2115 09:57:37.199509 [ANA_INIT] PLL >>>>>>>>
2116 09:57:37.202790 [ANA_INIT] PLL <<<<<<<<
2117 09:57:37.202870 [ANA_INIT] MIDPI >>>>>>>>
2118 09:57:37.206400 [ANA_INIT] MIDPI <<<<<<<<
2119 09:57:37.209296 [ANA_INIT] DLL >>>>>>>>
2120 09:57:37.209377 [ANA_INIT] DLL <<<<<<<<
2121 09:57:37.212741 [ANA_INIT] flow end
2122 09:57:37.216028 ============ LP4 DIFF to SE enter ============
2123 09:57:37.219408 ============ LP4 DIFF to SE exit ============
2124 09:57:37.222740 [ANA_INIT] <<<<<<<<<<<<<
2125 09:57:37.225939 [Flow] Enable top DCM control >>>>>
2126 09:57:37.229469 [Flow] Enable top DCM control <<<<<
2127 09:57:37.232909 Enable DLL master slave shuffle
2128 09:57:37.239497 ==============================================================
2129 09:57:37.239579 Gating Mode config
2130 09:57:37.245957 ==============================================================
2131 09:57:37.246038 Config description:
2132 09:57:37.255961 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2133 09:57:37.262408 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2134 09:57:37.269179 SELPH_MODE 0: By rank 1: By Phase
2135 09:57:37.272635 ==============================================================
2136 09:57:37.275826 GAT_TRACK_EN = 1
2137 09:57:37.279301 RX_GATING_MODE = 2
2138 09:57:37.282636 RX_GATING_TRACK_MODE = 2
2139 09:57:37.286020 SELPH_MODE = 1
2140 09:57:37.289308 PICG_EARLY_EN = 1
2141 09:57:37.292627 VALID_LAT_VALUE = 1
2142 09:57:37.295788 ==============================================================
2143 09:57:37.299314 Enter into Gating configuration >>>>
2144 09:57:37.302597 Exit from Gating configuration <<<<
2145 09:57:37.306078 Enter into DVFS_PRE_config >>>>>
2146 09:57:37.319470 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2147 09:57:37.322679 Exit from DVFS_PRE_config <<<<<
2148 09:57:37.322760 Enter into PICG configuration >>>>
2149 09:57:37.326231 Exit from PICG configuration <<<<
2150 09:57:37.329346 [RX_INPUT] configuration >>>>>
2151 09:57:37.332570 [RX_INPUT] configuration <<<<<
2152 09:57:37.339235 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2153 09:57:37.342592 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2154 09:57:37.349189 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2155 09:57:37.356299 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2156 09:57:37.362703 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2157 09:57:37.369303 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2158 09:57:37.372570 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2159 09:57:37.375926 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2160 09:57:37.379106 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2161 09:57:37.385773 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2162 09:57:37.389298 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2163 09:57:37.392870 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2164 09:57:37.395813 ===================================
2165 09:57:37.399263 LPDDR4 DRAM CONFIGURATION
2166 09:57:37.402362 ===================================
2167 09:57:37.402443 EX_ROW_EN[0] = 0x0
2168 09:57:37.405797 EX_ROW_EN[1] = 0x0
2169 09:57:37.409254 LP4Y_EN = 0x0
2170 09:57:37.409335 WORK_FSP = 0x0
2171 09:57:37.412453 WL = 0x4
2172 09:57:37.412557 RL = 0x4
2173 09:57:37.415846 BL = 0x2
2174 09:57:37.415926 RPST = 0x0
2175 09:57:37.419176 RD_PRE = 0x0
2176 09:57:37.419256 WR_PRE = 0x1
2177 09:57:37.422417 WR_PST = 0x0
2178 09:57:37.422497 DBI_WR = 0x0
2179 09:57:37.425734 DBI_RD = 0x0
2180 09:57:37.425815 OTF = 0x1
2181 09:57:37.429180 ===================================
2182 09:57:37.432466 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2183 09:57:37.439010 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2184 09:57:37.442390 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2185 09:57:37.446057 ===================================
2186 09:57:37.449488 LPDDR4 DRAM CONFIGURATION
2187 09:57:37.452501 ===================================
2188 09:57:37.452590 EX_ROW_EN[0] = 0x10
2189 09:57:37.455792 EX_ROW_EN[1] = 0x0
2190 09:57:37.455872 LP4Y_EN = 0x0
2191 09:57:37.459150 WORK_FSP = 0x0
2192 09:57:37.459231 WL = 0x4
2193 09:57:37.462702 RL = 0x4
2194 09:57:37.465776 BL = 0x2
2195 09:57:37.465857 RPST = 0x0
2196 09:57:37.469292 RD_PRE = 0x0
2197 09:57:37.469372 WR_PRE = 0x1
2198 09:57:37.472739 WR_PST = 0x0
2199 09:57:37.472820 DBI_WR = 0x0
2200 09:57:37.475807 DBI_RD = 0x0
2201 09:57:37.475887 OTF = 0x1
2202 09:57:37.479189 ===================================
2203 09:57:37.485862 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2204 09:57:37.485944 ==
2205 09:57:37.489389 Dram Type= 6, Freq= 0, CH_0, rank 0
2206 09:57:37.492480 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2207 09:57:37.492607 ==
2208 09:57:37.495734 [Duty_Offset_Calibration]
2209 09:57:37.499396 B0:0 B1:2 CA:1
2210 09:57:37.499477
2211 09:57:37.502231 [DutyScan_Calibration_Flow] k_type=0
2212 09:57:37.510312
2213 09:57:37.510395 ==CLK 0==
2214 09:57:37.513656 Final CLK duty delay cell = 0
2215 09:57:37.517028 [0] MAX Duty = 5093%(X100), DQS PI = 12
2216 09:57:37.520483 [0] MIN Duty = 4938%(X100), DQS PI = 52
2217 09:57:37.520607 [0] AVG Duty = 5015%(X100)
2218 09:57:37.523688
2219 09:57:37.523769 CH0 CLK Duty spec in!! Max-Min= 155%
2220 09:57:37.530407 [DutyScan_Calibration_Flow] ====Done====
2221 09:57:37.530513
2222 09:57:37.533633 [DutyScan_Calibration_Flow] k_type=1
2223 09:57:37.549533
2224 09:57:37.549614 ==DQS 0 ==
2225 09:57:37.552921 Final DQS duty delay cell = 0
2226 09:57:37.556347 [0] MAX Duty = 5125%(X100), DQS PI = 28
2227 09:57:37.559429 [0] MIN Duty = 5031%(X100), DQS PI = 6
2228 09:57:37.559511 [0] AVG Duty = 5078%(X100)
2229 09:57:37.563033
2230 09:57:37.563114 ==DQS 1 ==
2231 09:57:37.566281 Final DQS duty delay cell = 0
2232 09:57:37.569531 [0] MAX Duty = 5062%(X100), DQS PI = 56
2233 09:57:37.572942 [0] MIN Duty = 4906%(X100), DQS PI = 16
2234 09:57:37.573023 [0] AVG Duty = 4984%(X100)
2235 09:57:37.576145
2236 09:57:37.579509 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2237 09:57:37.579590
2238 09:57:37.583113 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2239 09:57:37.586265 [DutyScan_Calibration_Flow] ====Done====
2240 09:57:37.586346
2241 09:57:37.589632 [DutyScan_Calibration_Flow] k_type=3
2242 09:57:37.606756
2243 09:57:37.606836 ==DQM 0 ==
2244 09:57:37.609938 Final DQM duty delay cell = 0
2245 09:57:37.613610 [0] MAX Duty = 5156%(X100), DQS PI = 22
2246 09:57:37.616709 [0] MIN Duty = 4969%(X100), DQS PI = 40
2247 09:57:37.620077 [0] AVG Duty = 5062%(X100)
2248 09:57:37.620158
2249 09:57:37.620222 ==DQM 1 ==
2250 09:57:37.623363 Final DQM duty delay cell = 4
2251 09:57:37.626705 [4] MAX Duty = 5187%(X100), DQS PI = 54
2252 09:57:37.630455 [4] MIN Duty = 5000%(X100), DQS PI = 18
2253 09:57:37.633399 [4] AVG Duty = 5093%(X100)
2254 09:57:37.633510
2255 09:57:37.636718 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2256 09:57:37.636799
2257 09:57:37.639836 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2258 09:57:37.643449 [DutyScan_Calibration_Flow] ====Done====
2259 09:57:37.643530
2260 09:57:37.646475 [DutyScan_Calibration_Flow] k_type=2
2261 09:57:37.661905
2262 09:57:37.662011 ==DQ 0 ==
2263 09:57:37.664928 Final DQ duty delay cell = -4
2264 09:57:37.668604 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2265 09:57:37.671550 [-4] MIN Duty = 4813%(X100), DQS PI = 54
2266 09:57:37.675463 [-4] AVG Duty = 4937%(X100)
2267 09:57:37.675543
2268 09:57:37.675607 ==DQ 1 ==
2269 09:57:37.678232 Final DQ duty delay cell = -4
2270 09:57:37.681801 [-4] MAX Duty = 5093%(X100), DQS PI = 8
2271 09:57:37.685020 [-4] MIN Duty = 4876%(X100), DQS PI = 62
2272 09:57:37.688283 [-4] AVG Duty = 4984%(X100)
2273 09:57:37.688389
2274 09:57:37.691685 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2275 09:57:37.691766
2276 09:57:37.694861 CH0 DQ 1 Duty spec in!! Max-Min= 217%
2277 09:57:37.698329 [DutyScan_Calibration_Flow] ====Done====
2278 09:57:37.698410 ==
2279 09:57:37.701553 Dram Type= 6, Freq= 0, CH_1, rank 0
2280 09:57:37.705000 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2281 09:57:37.705081 ==
2282 09:57:37.708716 [Duty_Offset_Calibration]
2283 09:57:37.708800 B0:0 B1:4 CA:-5
2284 09:57:37.708870
2285 09:57:37.712028 [DutyScan_Calibration_Flow] k_type=0
2286 09:57:37.722251
2287 09:57:37.722332 ==CLK 0==
2288 09:57:37.725773 Final CLK duty delay cell = 0
2289 09:57:37.728888 [0] MAX Duty = 5094%(X100), DQS PI = 24
2290 09:57:37.732259 [0] MIN Duty = 4907%(X100), DQS PI = 44
2291 09:57:37.732340 [0] AVG Duty = 5000%(X100)
2292 09:57:37.735780
2293 09:57:37.739320 CH1 CLK Duty spec in!! Max-Min= 187%
2294 09:57:37.742354 [DutyScan_Calibration_Flow] ====Done====
2295 09:57:37.742435
2296 09:57:37.745728 [DutyScan_Calibration_Flow] k_type=1
2297 09:57:37.761091
2298 09:57:37.761171 ==DQS 0 ==
2299 09:57:37.764204 Final DQS duty delay cell = 0
2300 09:57:37.767514 [0] MAX Duty = 5125%(X100), DQS PI = 16
2301 09:57:37.770875 [0] MIN Duty = 4875%(X100), DQS PI = 38
2302 09:57:37.774595 [0] AVG Duty = 5000%(X100)
2303 09:57:37.774676
2304 09:57:37.774740 ==DQS 1 ==
2305 09:57:37.777735 Final DQS duty delay cell = -4
2306 09:57:37.780668 [-4] MAX Duty = 5000%(X100), DQS PI = 4
2307 09:57:37.784273 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2308 09:57:37.787769 [-4] AVG Duty = 4953%(X100)
2309 09:57:37.787850
2310 09:57:37.790821 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2311 09:57:37.790901
2312 09:57:37.794219 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2313 09:57:37.797472 [DutyScan_Calibration_Flow] ====Done====
2314 09:57:37.797553
2315 09:57:37.800687 [DutyScan_Calibration_Flow] k_type=3
2316 09:57:37.815743
2317 09:57:37.815823 ==DQM 0 ==
2318 09:57:37.819500 Final DQM duty delay cell = -4
2319 09:57:37.822715 [-4] MAX Duty = 5094%(X100), DQS PI = 30
2320 09:57:37.826049 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2321 09:57:37.829502 [-4] AVG Duty = 4969%(X100)
2322 09:57:37.829583
2323 09:57:37.829646 ==DQM 1 ==
2324 09:57:37.832714 Final DQM duty delay cell = -4
2325 09:57:37.836058 [-4] MAX Duty = 5093%(X100), DQS PI = 20
2326 09:57:37.839551 [-4] MIN Duty = 4907%(X100), DQS PI = 46
2327 09:57:37.843096 [-4] AVG Duty = 5000%(X100)
2328 09:57:37.843177
2329 09:57:37.845813 CH1 DQM 0 Duty spec in!! Max-Min= 250%
2330 09:57:37.845894
2331 09:57:37.849203 CH1 DQM 1 Duty spec in!! Max-Min= 186%
2332 09:57:37.852635 [DutyScan_Calibration_Flow] ====Done====
2333 09:57:37.852715
2334 09:57:37.855741 [DutyScan_Calibration_Flow] k_type=2
2335 09:57:37.873109
2336 09:57:37.873190 ==DQ 0 ==
2337 09:57:37.876331 Final DQ duty delay cell = 0
2338 09:57:37.879686 [0] MAX Duty = 5062%(X100), DQS PI = 0
2339 09:57:37.883146 [0] MIN Duty = 4969%(X100), DQS PI = 42
2340 09:57:37.883227 [0] AVG Duty = 5015%(X100)
2341 09:57:37.883291
2342 09:57:37.886792 ==DQ 1 ==
2343 09:57:37.889869 Final DQ duty delay cell = 0
2344 09:57:37.892948 [0] MAX Duty = 5031%(X100), DQS PI = 6
2345 09:57:37.896211 [0] MIN Duty = 4907%(X100), DQS PI = 0
2346 09:57:37.896291 [0] AVG Duty = 4969%(X100)
2347 09:57:37.896354
2348 09:57:37.899965 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2349 09:57:37.900045
2350 09:57:37.903362 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2351 09:57:37.909940 [DutyScan_Calibration_Flow] ====Done====
2352 09:57:37.912839 nWR fixed to 30
2353 09:57:37.912919 [ModeRegInit_LP4] CH0 RK0
2354 09:57:37.916746 [ModeRegInit_LP4] CH0 RK1
2355 09:57:37.919658 [ModeRegInit_LP4] CH1 RK0
2356 09:57:37.919738 [ModeRegInit_LP4] CH1 RK1
2357 09:57:37.923181 match AC timing 6
2358 09:57:37.926732 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2359 09:57:37.929882 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2360 09:57:37.936304 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2361 09:57:37.939908 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2362 09:57:37.946714 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2363 09:57:37.946795 ==
2364 09:57:37.949667 Dram Type= 6, Freq= 0, CH_0, rank 0
2365 09:57:37.953303 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2366 09:57:37.953383 ==
2367 09:57:37.959802 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2368 09:57:37.962845 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2369 09:57:37.972453 [CA 0] Center 39 (9~70) winsize 62
2370 09:57:37.976096 [CA 1] Center 39 (9~70) winsize 62
2371 09:57:37.979136 [CA 2] Center 36 (5~67) winsize 63
2372 09:57:37.982458 [CA 3] Center 35 (5~66) winsize 62
2373 09:57:37.985856 [CA 4] Center 34 (3~65) winsize 63
2374 09:57:37.989300 [CA 5] Center 33 (3~64) winsize 62
2375 09:57:37.989380
2376 09:57:37.992437 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2377 09:57:37.992547
2378 09:57:37.995665 [CATrainingPosCal] consider 1 rank data
2379 09:57:37.999204 u2DelayCellTimex100 = 270/100 ps
2380 09:57:38.002547 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2381 09:57:38.009140 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2382 09:57:38.012466 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2383 09:57:38.015891 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2384 09:57:38.019156 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2385 09:57:38.022699 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2386 09:57:38.022779
2387 09:57:38.025911 CA PerBit enable=1, Macro0, CA PI delay=33
2388 09:57:38.025992
2389 09:57:38.029458 [CBTSetCACLKResult] CA Dly = 33
2390 09:57:38.029538 CS Dly: 7 (0~38)
2391 09:57:38.032349 ==
2392 09:57:38.036000 Dram Type= 6, Freq= 0, CH_0, rank 1
2393 09:57:38.039218 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2394 09:57:38.039299 ==
2395 09:57:38.042362 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2396 09:57:38.048834 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2397 09:57:38.057932 [CA 0] Center 39 (8~70) winsize 63
2398 09:57:38.061334 [CA 1] Center 39 (8~70) winsize 63
2399 09:57:38.064696 [CA 2] Center 35 (5~66) winsize 62
2400 09:57:38.067879 [CA 3] Center 35 (4~66) winsize 63
2401 09:57:38.071321 [CA 4] Center 33 (3~64) winsize 62
2402 09:57:38.074809 [CA 5] Center 33 (3~64) winsize 62
2403 09:57:38.074889
2404 09:57:38.078178 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2405 09:57:38.078258
2406 09:57:38.081333 [CATrainingPosCal] consider 2 rank data
2407 09:57:38.084476 u2DelayCellTimex100 = 270/100 ps
2408 09:57:38.087889 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2409 09:57:38.091301 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2410 09:57:38.097879 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2411 09:57:38.101353 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2412 09:57:38.104536 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2413 09:57:38.107872 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2414 09:57:38.107951
2415 09:57:38.111118 CA PerBit enable=1, Macro0, CA PI delay=33
2416 09:57:38.111198
2417 09:57:38.114578 [CBTSetCACLKResult] CA Dly = 33
2418 09:57:38.114659 CS Dly: 7 (0~39)
2419 09:57:38.114722
2420 09:57:38.118383 ----->DramcWriteLeveling(PI) begin...
2421 09:57:38.121235 ==
2422 09:57:38.121316 Dram Type= 6, Freq= 0, CH_0, rank 0
2423 09:57:38.127942 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2424 09:57:38.128023 ==
2425 09:57:38.131303 Write leveling (Byte 0): 27 => 27
2426 09:57:38.134755 Write leveling (Byte 1): 27 => 27
2427 09:57:38.137856 DramcWriteLeveling(PI) end<-----
2428 09:57:38.137936
2429 09:57:38.137998 ==
2430 09:57:38.141530 Dram Type= 6, Freq= 0, CH_0, rank 0
2431 09:57:38.144839 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2432 09:57:38.144920 ==
2433 09:57:38.147890 [Gating] SW mode calibration
2434 09:57:38.154359 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2435 09:57:38.161384 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2436 09:57:38.164903 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2437 09:57:38.167924 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2438 09:57:38.171152 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2439 09:57:38.177883 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2440 09:57:38.181358 0 11 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2441 09:57:38.184642 0 11 20 | B1->B0 | 2e2e 2d2d | 1 0 | (1 0) (1 1)
2442 09:57:38.191455 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2443 09:57:38.194407 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2444 09:57:38.197954 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2445 09:57:38.204313 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2446 09:57:38.207751 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2447 09:57:38.211597 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2448 09:57:38.217730 0 12 16 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2449 09:57:38.221085 0 12 20 | B1->B0 | 3d3d 4141 | 0 0 | (0 0) (0 0)
2450 09:57:38.224264 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2451 09:57:38.231125 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2452 09:57:38.234346 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2453 09:57:38.238124 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2454 09:57:38.244307 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2455 09:57:38.247589 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2456 09:57:38.250959 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2457 09:57:38.258024 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2458 09:57:38.260929 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2459 09:57:38.264297 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2460 09:57:38.271104 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2461 09:57:38.274476 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2462 09:57:38.278072 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2463 09:57:38.281153 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2464 09:57:38.287558 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2465 09:57:38.291159 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2466 09:57:38.294420 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2467 09:57:38.301198 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2468 09:57:38.304670 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2469 09:57:38.307690 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2470 09:57:38.314521 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2471 09:57:38.317938 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2472 09:57:38.321340 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2473 09:57:38.327835 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2474 09:57:38.331159 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2475 09:57:38.334429 Total UI for P1: 0, mck2ui 16
2476 09:57:38.337927 best dqsien dly found for B0: ( 0, 15, 16)
2477 09:57:38.341328 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2478 09:57:38.344442 Total UI for P1: 0, mck2ui 16
2479 09:57:38.347920 best dqsien dly found for B1: ( 0, 15, 20)
2480 09:57:38.351485 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2481 09:57:38.354507 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2482 09:57:38.354610
2483 09:57:38.357675 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2484 09:57:38.364437 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2485 09:57:38.364573 [Gating] SW calibration Done
2486 09:57:38.364641 ==
2487 09:57:38.367947 Dram Type= 6, Freq= 0, CH_0, rank 0
2488 09:57:38.374703 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2489 09:57:38.374805 ==
2490 09:57:38.374900 RX Vref Scan: 0
2491 09:57:38.374988
2492 09:57:38.378304 RX Vref 0 -> 0, step: 1
2493 09:57:38.378401
2494 09:57:38.381333 RX Delay -40 -> 252, step: 8
2495 09:57:38.385823 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2496 09:57:38.387988 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2497 09:57:38.391558 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2498 09:57:38.398025 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2499 09:57:38.401588 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2500 09:57:38.404719 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2501 09:57:38.407761 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2502 09:57:38.411222 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2503 09:57:38.414541 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2504 09:57:38.421445 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2505 09:57:38.424615 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2506 09:57:38.427800 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2507 09:57:38.431405 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2508 09:57:38.434685 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2509 09:57:38.441478 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2510 09:57:38.444629 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2511 09:57:38.444710 ==
2512 09:57:38.447825 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 09:57:38.451588 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2514 09:57:38.451672 ==
2515 09:57:38.454860 DQS Delay:
2516 09:57:38.454941 DQS0 = 0, DQS1 = 0
2517 09:57:38.455005 DQM Delay:
2518 09:57:38.458148 DQM0 = 115, DQM1 = 106
2519 09:57:38.458228 DQ Delay:
2520 09:57:38.461321 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2521 09:57:38.464742 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2522 09:57:38.468025 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =99
2523 09:57:38.474692 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2524 09:57:38.474773
2525 09:57:38.474836
2526 09:57:38.474896 ==
2527 09:57:38.478616 Dram Type= 6, Freq= 0, CH_0, rank 0
2528 09:57:38.481596 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2529 09:57:38.481677 ==
2530 09:57:38.481742
2531 09:57:38.481800
2532 09:57:38.484982 TX Vref Scan disable
2533 09:57:38.485062 == TX Byte 0 ==
2534 09:57:38.491594 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2535 09:57:38.494889 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2536 09:57:38.494971 == TX Byte 1 ==
2537 09:57:38.501375 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2538 09:57:38.504789 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2539 09:57:38.504870 ==
2540 09:57:38.508071 Dram Type= 6, Freq= 0, CH_0, rank 0
2541 09:57:38.511109 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2542 09:57:38.511191 ==
2543 09:57:38.523790 TX Vref=22, minBit 9, minWin=25, winSum=419
2544 09:57:38.526834 TX Vref=24, minBit 10, minWin=25, winSum=423
2545 09:57:38.530223 TX Vref=26, minBit 1, minWin=26, winSum=427
2546 09:57:38.533540 TX Vref=28, minBit 8, minWin=25, winSum=429
2547 09:57:38.536952 TX Vref=30, minBit 5, minWin=26, winSum=436
2548 09:57:38.543555 TX Vref=32, minBit 8, minWin=26, winSum=430
2549 09:57:38.546799 [TxChooseVref] Worse bit 5, Min win 26, Win sum 436, Final Vref 30
2550 09:57:38.546880
2551 09:57:38.550144 Final TX Range 1 Vref 30
2552 09:57:38.550225
2553 09:57:38.550289 ==
2554 09:57:38.553770 Dram Type= 6, Freq= 0, CH_0, rank 0
2555 09:57:38.557140 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2556 09:57:38.557222 ==
2557 09:57:38.557286
2558 09:57:38.560805
2559 09:57:38.560885 TX Vref Scan disable
2560 09:57:38.563510 == TX Byte 0 ==
2561 09:57:38.567401 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2562 09:57:38.570278 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2563 09:57:38.573792 == TX Byte 1 ==
2564 09:57:38.577164 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2565 09:57:38.580385 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2566 09:57:38.580491
2567 09:57:38.584002 [DATLAT]
2568 09:57:38.584082 Freq=1200, CH0 RK0
2569 09:57:38.584146
2570 09:57:38.587075 DATLAT Default: 0xd
2571 09:57:38.587156 0, 0xFFFF, sum = 0
2572 09:57:38.590284 1, 0xFFFF, sum = 0
2573 09:57:38.590366 2, 0xFFFF, sum = 0
2574 09:57:38.593569 3, 0xFFFF, sum = 0
2575 09:57:38.593651 4, 0xFFFF, sum = 0
2576 09:57:38.597151 5, 0xFFFF, sum = 0
2577 09:57:38.597233 6, 0xFFFF, sum = 0
2578 09:57:38.600429 7, 0xFFFF, sum = 0
2579 09:57:38.600575 8, 0xFFFF, sum = 0
2580 09:57:38.603792 9, 0xFFFF, sum = 0
2581 09:57:38.603875 10, 0xFFFF, sum = 0
2582 09:57:38.607147 11, 0x0, sum = 1
2583 09:57:38.607229 12, 0x0, sum = 2
2584 09:57:38.610428 13, 0x0, sum = 3
2585 09:57:38.610509 14, 0x0, sum = 4
2586 09:57:38.613750 best_step = 12
2587 09:57:38.613830
2588 09:57:38.613894 ==
2589 09:57:38.617081 Dram Type= 6, Freq= 0, CH_0, rank 0
2590 09:57:38.620306 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2591 09:57:38.620386 ==
2592 09:57:38.623806 RX Vref Scan: 1
2593 09:57:38.623887
2594 09:57:38.623952 Set Vref Range= 32 -> 127
2595 09:57:38.627022
2596 09:57:38.627103 RX Vref 32 -> 127, step: 1
2597 09:57:38.627167
2598 09:57:38.630158 RX Delay -21 -> 252, step: 4
2599 09:57:38.630238
2600 09:57:38.633599 Set Vref, RX VrefLevel [Byte0]: 32
2601 09:57:38.636916 [Byte1]: 32
2602 09:57:38.636998
2603 09:57:38.640415 Set Vref, RX VrefLevel [Byte0]: 33
2604 09:57:38.643631 [Byte1]: 33
2605 09:57:38.648032
2606 09:57:38.648112 Set Vref, RX VrefLevel [Byte0]: 34
2607 09:57:38.651398 [Byte1]: 34
2608 09:57:38.655939
2609 09:57:38.656019 Set Vref, RX VrefLevel [Byte0]: 35
2610 09:57:38.659136 [Byte1]: 35
2611 09:57:38.663694
2612 09:57:38.663815 Set Vref, RX VrefLevel [Byte0]: 36
2613 09:57:38.667003 [Byte1]: 36
2614 09:57:38.671558
2615 09:57:38.671638 Set Vref, RX VrefLevel [Byte0]: 37
2616 09:57:38.674930 [Byte1]: 37
2617 09:57:38.679802
2618 09:57:38.679883 Set Vref, RX VrefLevel [Byte0]: 38
2619 09:57:38.683060 [Byte1]: 38
2620 09:57:38.688119
2621 09:57:38.688200 Set Vref, RX VrefLevel [Byte0]: 39
2622 09:57:38.690999 [Byte1]: 39
2623 09:57:38.695529
2624 09:57:38.695610 Set Vref, RX VrefLevel [Byte0]: 40
2625 09:57:38.698729 [Byte1]: 40
2626 09:57:38.703737
2627 09:57:38.703818 Set Vref, RX VrefLevel [Byte0]: 41
2628 09:57:38.706582 [Byte1]: 41
2629 09:57:38.711256
2630 09:57:38.711336 Set Vref, RX VrefLevel [Byte0]: 42
2631 09:57:38.714705 [Byte1]: 42
2632 09:57:38.719364
2633 09:57:38.719444 Set Vref, RX VrefLevel [Byte0]: 43
2634 09:57:38.722589 [Byte1]: 43
2635 09:57:38.727077
2636 09:57:38.727157 Set Vref, RX VrefLevel [Byte0]: 44
2637 09:57:38.730714 [Byte1]: 44
2638 09:57:38.735577
2639 09:57:38.735666 Set Vref, RX VrefLevel [Byte0]: 45
2640 09:57:38.738387 [Byte1]: 45
2641 09:57:38.743053
2642 09:57:38.743134 Set Vref, RX VrefLevel [Byte0]: 46
2643 09:57:38.746546 [Byte1]: 46
2644 09:57:38.750902
2645 09:57:38.750982 Set Vref, RX VrefLevel [Byte0]: 47
2646 09:57:38.754145 [Byte1]: 47
2647 09:57:38.758757
2648 09:57:38.758837 Set Vref, RX VrefLevel [Byte0]: 48
2649 09:57:38.762138 [Byte1]: 48
2650 09:57:38.766758
2651 09:57:38.766841 Set Vref, RX VrefLevel [Byte0]: 49
2652 09:57:38.769992 [Byte1]: 49
2653 09:57:38.774850
2654 09:57:38.774953 Set Vref, RX VrefLevel [Byte0]: 50
2655 09:57:38.777940 [Byte1]: 50
2656 09:57:38.782724
2657 09:57:38.782804 Set Vref, RX VrefLevel [Byte0]: 51
2658 09:57:38.785890 [Byte1]: 51
2659 09:57:38.790604
2660 09:57:38.790684 Set Vref, RX VrefLevel [Byte0]: 52
2661 09:57:38.793902 [Byte1]: 52
2662 09:57:38.798387
2663 09:57:38.798467 Set Vref, RX VrefLevel [Byte0]: 53
2664 09:57:38.801954 [Byte1]: 53
2665 09:57:38.806360
2666 09:57:38.806441 Set Vref, RX VrefLevel [Byte0]: 54
2667 09:57:38.809926 [Byte1]: 54
2668 09:57:38.814503
2669 09:57:38.814583 Set Vref, RX VrefLevel [Byte0]: 55
2670 09:57:38.817611 [Byte1]: 55
2671 09:57:38.822452
2672 09:57:38.822532 Set Vref, RX VrefLevel [Byte0]: 56
2673 09:57:38.825762 [Byte1]: 56
2674 09:57:38.830139
2675 09:57:38.830219 Set Vref, RX VrefLevel [Byte0]: 57
2676 09:57:38.833656 [Byte1]: 57
2677 09:57:38.838155
2678 09:57:38.838235 Set Vref, RX VrefLevel [Byte0]: 58
2679 09:57:38.841311 [Byte1]: 58
2680 09:57:38.845916
2681 09:57:38.845996 Set Vref, RX VrefLevel [Byte0]: 59
2682 09:57:38.849678 [Byte1]: 59
2683 09:57:38.854043
2684 09:57:38.854124 Set Vref, RX VrefLevel [Byte0]: 60
2685 09:57:38.857324 [Byte1]: 60
2686 09:57:38.861990
2687 09:57:38.862071 Set Vref, RX VrefLevel [Byte0]: 61
2688 09:57:38.865193 [Byte1]: 61
2689 09:57:38.869875
2690 09:57:38.869955 Set Vref, RX VrefLevel [Byte0]: 62
2691 09:57:38.873393 [Byte1]: 62
2692 09:57:38.877566
2693 09:57:38.877647 Set Vref, RX VrefLevel [Byte0]: 63
2694 09:57:38.880999 [Byte1]: 63
2695 09:57:38.885949
2696 09:57:38.886060 Set Vref, RX VrefLevel [Byte0]: 64
2697 09:57:38.888974 [Byte1]: 64
2698 09:57:38.893764
2699 09:57:38.893844 Set Vref, RX VrefLevel [Byte0]: 65
2700 09:57:38.896809 [Byte1]: 65
2701 09:57:38.901658
2702 09:57:38.901739 Set Vref, RX VrefLevel [Byte0]: 66
2703 09:57:38.904798 [Byte1]: 66
2704 09:57:38.909497
2705 09:57:38.909577 Set Vref, RX VrefLevel [Byte0]: 67
2706 09:57:38.912696 [Byte1]: 67
2707 09:57:38.917521
2708 09:57:38.917602 Final RX Vref Byte 0 = 46 to rank0
2709 09:57:38.920693 Final RX Vref Byte 1 = 49 to rank0
2710 09:57:38.923907 Final RX Vref Byte 0 = 46 to rank1
2711 09:57:38.927350 Final RX Vref Byte 1 = 49 to rank1==
2712 09:57:38.930570 Dram Type= 6, Freq= 0, CH_0, rank 0
2713 09:57:38.937289 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2714 09:57:38.937371 ==
2715 09:57:38.937436 DQS Delay:
2716 09:57:38.937496 DQS0 = 0, DQS1 = 0
2717 09:57:38.940737 DQM Delay:
2718 09:57:38.940817 DQM0 = 114, DQM1 = 105
2719 09:57:38.944053 DQ Delay:
2720 09:57:38.947206 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =108
2721 09:57:38.950575 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =120
2722 09:57:38.953746 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2723 09:57:38.957176 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2724 09:57:38.957251
2725 09:57:38.957314
2726 09:57:38.964133 [DQSOSCAuto] RK0, (LSB)MR18= 0x707, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
2727 09:57:38.966949 CH0 RK0: MR19=404, MR18=707
2728 09:57:38.973412 CH0_RK0: MR19=0x404, MR18=0x707, DQSOSC=407, MR23=63, INC=39, DEC=26
2729 09:57:38.973491
2730 09:57:38.976725 ----->DramcWriteLeveling(PI) begin...
2731 09:57:38.976802 ==
2732 09:57:38.980137 Dram Type= 6, Freq= 0, CH_0, rank 1
2733 09:57:38.983568 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2734 09:57:38.986927 ==
2735 09:57:38.987008 Write leveling (Byte 0): 26 => 26
2736 09:57:38.990110 Write leveling (Byte 1): 23 => 23
2737 09:57:38.993490 DramcWriteLeveling(PI) end<-----
2738 09:57:38.993571
2739 09:57:38.993634 ==
2740 09:57:38.996815 Dram Type= 6, Freq= 0, CH_0, rank 1
2741 09:57:39.003421 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2742 09:57:39.003502 ==
2743 09:57:39.003566 [Gating] SW mode calibration
2744 09:57:39.013334 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2745 09:57:39.016897 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2746 09:57:39.020223 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2747 09:57:39.026771 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2748 09:57:39.030131 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2749 09:57:39.033699 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2750 09:57:39.040146 0 11 16 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
2751 09:57:39.043405 0 11 20 | B1->B0 | 2f2f 2727 | 1 0 | (1 0) (1 0)
2752 09:57:39.046733 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2753 09:57:39.053646 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2754 09:57:39.057105 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2755 09:57:39.060182 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2756 09:57:39.066967 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2757 09:57:39.070326 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2758 09:57:39.073504 0 12 16 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2759 09:57:39.080168 0 12 20 | B1->B0 | 3d3d 4545 | 1 0 | (1 1) (0 0)
2760 09:57:39.083748 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2761 09:57:39.086673 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2762 09:57:39.093547 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2763 09:57:39.096729 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2764 09:57:39.100017 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2765 09:57:39.106588 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2766 09:57:39.110135 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2767 09:57:39.113306 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2768 09:57:39.116953 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2769 09:57:39.123717 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2770 09:57:39.127092 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2771 09:57:39.130130 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2772 09:57:39.136991 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2773 09:57:39.140059 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2774 09:57:39.143540 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2775 09:57:39.150352 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2776 09:57:39.153550 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2777 09:57:39.156718 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2778 09:57:39.163425 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2779 09:57:39.166803 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2780 09:57:39.170219 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2781 09:57:39.176927 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2782 09:57:39.180249 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2783 09:57:39.183374 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2784 09:57:39.190001 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2785 09:57:39.190082 Total UI for P1: 0, mck2ui 16
2786 09:57:39.196805 best dqsien dly found for B0: ( 0, 15, 18)
2787 09:57:39.196885 Total UI for P1: 0, mck2ui 16
2788 09:57:39.203772 best dqsien dly found for B1: ( 0, 15, 18)
2789 09:57:39.206550 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2790 09:57:39.209894 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2791 09:57:39.209975
2792 09:57:39.213365 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2793 09:57:39.216707 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2794 09:57:39.220081 [Gating] SW calibration Done
2795 09:57:39.220162 ==
2796 09:57:39.223322 Dram Type= 6, Freq= 0, CH_0, rank 1
2797 09:57:39.226820 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2798 09:57:39.226906 ==
2799 09:57:39.230274 RX Vref Scan: 0
2800 09:57:39.230356
2801 09:57:39.230420 RX Vref 0 -> 0, step: 1
2802 09:57:39.230480
2803 09:57:39.233439 RX Delay -40 -> 252, step: 8
2804 09:57:39.236590 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2805 09:57:39.243301 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2806 09:57:39.246831 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2807 09:57:39.250112 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2808 09:57:39.253501 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2809 09:57:39.256953 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2810 09:57:39.260075 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2811 09:57:39.266835 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2812 09:57:39.270073 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2813 09:57:39.273806 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2814 09:57:39.277027 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2815 09:57:39.280264 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2816 09:57:39.287049 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2817 09:57:39.290501 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2818 09:57:39.294023 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2819 09:57:39.297135 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2820 09:57:39.297217 ==
2821 09:57:39.300326 Dram Type= 6, Freq= 0, CH_0, rank 1
2822 09:57:39.304078 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2823 09:57:39.307352 ==
2824 09:57:39.307433 DQS Delay:
2825 09:57:39.307498 DQS0 = 0, DQS1 = 0
2826 09:57:39.310614 DQM Delay:
2827 09:57:39.310695 DQM0 = 114, DQM1 = 106
2828 09:57:39.313868 DQ Delay:
2829 09:57:39.317420 DQ0 =107, DQ1 =115, DQ2 =115, DQ3 =111
2830 09:57:39.321222 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2831 09:57:39.324146 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
2832 09:57:39.327297 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =115
2833 09:57:39.327381
2834 09:57:39.327446
2835 09:57:39.327506 ==
2836 09:57:39.330689 Dram Type= 6, Freq= 0, CH_0, rank 1
2837 09:57:39.334021 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2838 09:57:39.334103 ==
2839 09:57:39.334168
2840 09:57:39.334227
2841 09:57:39.337442 TX Vref Scan disable
2842 09:57:39.340921 == TX Byte 0 ==
2843 09:57:39.344279 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2844 09:57:39.347536 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2845 09:57:39.350713 == TX Byte 1 ==
2846 09:57:39.354180 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2847 09:57:39.357606 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2848 09:57:39.357686 ==
2849 09:57:39.360947 Dram Type= 6, Freq= 0, CH_0, rank 1
2850 09:57:39.364043 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2851 09:57:39.364124 ==
2852 09:57:39.377412 TX Vref=22, minBit 5, minWin=25, winSum=413
2853 09:57:39.380883 TX Vref=24, minBit 5, minWin=25, winSum=415
2854 09:57:39.383849 TX Vref=26, minBit 8, minWin=25, winSum=421
2855 09:57:39.387344 TX Vref=28, minBit 1, minWin=26, winSum=430
2856 09:57:39.390836 TX Vref=30, minBit 8, minWin=26, winSum=428
2857 09:57:39.393791 TX Vref=32, minBit 3, minWin=26, winSum=428
2858 09:57:39.400454 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 28
2859 09:57:39.400541
2860 09:57:39.403770 Final TX Range 1 Vref 28
2861 09:57:39.403851
2862 09:57:39.403914 ==
2863 09:57:39.407161 Dram Type= 6, Freq= 0, CH_0, rank 1
2864 09:57:39.410494 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2865 09:57:39.410575 ==
2866 09:57:39.410640
2867 09:57:39.414193
2868 09:57:39.414274 TX Vref Scan disable
2869 09:57:39.417323 == TX Byte 0 ==
2870 09:57:39.420456 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2871 09:57:39.424103 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2872 09:57:39.427367 == TX Byte 1 ==
2873 09:57:39.430661 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
2874 09:57:39.433897 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
2875 09:57:39.433978
2876 09:57:39.437859 [DATLAT]
2877 09:57:39.437939 Freq=1200, CH0 RK1
2878 09:57:39.438004
2879 09:57:39.440665 DATLAT Default: 0xc
2880 09:57:39.440750 0, 0xFFFF, sum = 0
2881 09:57:39.444001 1, 0xFFFF, sum = 0
2882 09:57:39.444083 2, 0xFFFF, sum = 0
2883 09:57:39.447417 3, 0xFFFF, sum = 0
2884 09:57:39.447517 4, 0xFFFF, sum = 0
2885 09:57:39.450653 5, 0xFFFF, sum = 0
2886 09:57:39.450735 6, 0xFFFF, sum = 0
2887 09:57:39.454268 7, 0xFFFF, sum = 0
2888 09:57:39.454350 8, 0xFFFF, sum = 0
2889 09:57:39.457280 9, 0xFFFF, sum = 0
2890 09:57:39.460867 10, 0xFFFF, sum = 0
2891 09:57:39.460950 11, 0x0, sum = 1
2892 09:57:39.461016 12, 0x0, sum = 2
2893 09:57:39.464162 13, 0x0, sum = 3
2894 09:57:39.464244 14, 0x0, sum = 4
2895 09:57:39.467419 best_step = 12
2896 09:57:39.467502
2897 09:57:39.467578 ==
2898 09:57:39.471061 Dram Type= 6, Freq= 0, CH_0, rank 1
2899 09:57:39.474298 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2900 09:57:39.474380 ==
2901 09:57:39.477589 RX Vref Scan: 0
2902 09:57:39.477669
2903 09:57:39.477733 RX Vref 0 -> 0, step: 1
2904 09:57:39.477792
2905 09:57:39.480908 RX Delay -21 -> 252, step: 4
2906 09:57:39.487600 iDelay=195, Bit 0, Center 110 (39 ~ 182) 144
2907 09:57:39.490869 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148
2908 09:57:39.494036 iDelay=195, Bit 2, Center 112 (43 ~ 182) 140
2909 09:57:39.497708 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
2910 09:57:39.501133 iDelay=195, Bit 4, Center 118 (47 ~ 190) 144
2911 09:57:39.507617 iDelay=195, Bit 5, Center 106 (35 ~ 178) 144
2912 09:57:39.510991 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
2913 09:57:39.514259 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
2914 09:57:39.517825 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
2915 09:57:39.521188 iDelay=195, Bit 9, Center 90 (27 ~ 154) 128
2916 09:57:39.524184 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
2917 09:57:39.530923 iDelay=195, Bit 11, Center 96 (35 ~ 158) 124
2918 09:57:39.534270 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
2919 09:57:39.537908 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
2920 09:57:39.540821 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
2921 09:57:39.547536 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
2922 09:57:39.547617 ==
2923 09:57:39.551002 Dram Type= 6, Freq= 0, CH_0, rank 1
2924 09:57:39.554625 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2925 09:57:39.554706 ==
2926 09:57:39.554770 DQS Delay:
2927 09:57:39.557474 DQS0 = 0, DQS1 = 0
2928 09:57:39.557554 DQM Delay:
2929 09:57:39.560811 DQM0 = 114, DQM1 = 106
2930 09:57:39.560892 DQ Delay:
2931 09:57:39.564286 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =108
2932 09:57:39.567815 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =124
2933 09:57:39.571195 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =96
2934 09:57:39.574343 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =116
2935 09:57:39.574423
2936 09:57:39.574487
2937 09:57:39.584495 [DQSOSCAuto] RK1, (LSB)MR18= 0x1414, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 402 ps
2938 09:57:39.587756 CH0 RK1: MR19=404, MR18=1414
2939 09:57:39.590962 CH0_RK1: MR19=0x404, MR18=0x1414, DQSOSC=402, MR23=63, INC=40, DEC=27
2940 09:57:39.594516 [RxdqsGatingPostProcess] freq 1200
2941 09:57:39.601003 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2942 09:57:39.604451 Pre-setting of DQS Precalculation
2943 09:57:39.607775 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2944 09:57:39.607856 ==
2945 09:57:39.611037 Dram Type= 6, Freq= 0, CH_1, rank 0
2946 09:57:39.617861 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2947 09:57:39.617942 ==
2948 09:57:39.621248 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2949 09:57:39.627805 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2950 09:57:39.636089 [CA 0] Center 37 (7~68) winsize 62
2951 09:57:39.639523 [CA 1] Center 37 (7~68) winsize 62
2952 09:57:39.642663 [CA 2] Center 34 (4~65) winsize 62
2953 09:57:39.646149 [CA 3] Center 33 (3~64) winsize 62
2954 09:57:39.649524 [CA 4] Center 32 (1~63) winsize 63
2955 09:57:39.652797 [CA 5] Center 32 (2~63) winsize 62
2956 09:57:39.652877
2957 09:57:39.655867 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2958 09:57:39.655948
2959 09:57:39.659649 [CATrainingPosCal] consider 1 rank data
2960 09:57:39.662745 u2DelayCellTimex100 = 270/100 ps
2961 09:57:39.665986 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2962 09:57:39.669289 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2963 09:57:39.675935 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2964 09:57:39.679400 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2965 09:57:39.682691 CA4 delay=32 (1~63),Diff = 0 PI (0 cell)
2966 09:57:39.686155 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2967 09:57:39.686236
2968 09:57:39.689448 CA PerBit enable=1, Macro0, CA PI delay=32
2969 09:57:39.689529
2970 09:57:39.692496 [CBTSetCACLKResult] CA Dly = 32
2971 09:57:39.692616 CS Dly: 6 (0~37)
2972 09:57:39.695990 ==
2973 09:57:39.696071 Dram Type= 6, Freq= 0, CH_1, rank 1
2974 09:57:39.702756 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2975 09:57:39.702837 ==
2976 09:57:39.706402 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2977 09:57:39.712671 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2978 09:57:39.721356 [CA 0] Center 37 (7~68) winsize 62
2979 09:57:39.724692 [CA 1] Center 37 (7~68) winsize 62
2980 09:57:39.728088 [CA 2] Center 33 (3~64) winsize 62
2981 09:57:39.731661 [CA 3] Center 33 (3~64) winsize 62
2982 09:57:39.734676 [CA 4] Center 32 (2~63) winsize 62
2983 09:57:39.738190 [CA 5] Center 32 (1~63) winsize 63
2984 09:57:39.738271
2985 09:57:39.741351 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2986 09:57:39.741431
2987 09:57:39.744494 [CATrainingPosCal] consider 2 rank data
2988 09:57:39.747885 u2DelayCellTimex100 = 270/100 ps
2989 09:57:39.751536 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2990 09:57:39.754581 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2991 09:57:39.761315 CA2 delay=34 (4~64),Diff = 2 PI (9 cell)
2992 09:57:39.764709 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2993 09:57:39.767950 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2994 09:57:39.771581 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2995 09:57:39.771661
2996 09:57:39.774945 CA PerBit enable=1, Macro0, CA PI delay=32
2997 09:57:39.775026
2998 09:57:39.777895 [CBTSetCACLKResult] CA Dly = 32
2999 09:57:39.777976 CS Dly: 6 (0~38)
3000 09:57:39.778040
3001 09:57:39.781157 ----->DramcWriteLeveling(PI) begin...
3002 09:57:39.784808 ==
3003 09:57:39.784888 Dram Type= 6, Freq= 0, CH_1, rank 0
3004 09:57:39.791245 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3005 09:57:39.791326 ==
3006 09:57:39.794612 Write leveling (Byte 0): 20 => 20
3007 09:57:39.797846 Write leveling (Byte 1): 21 => 21
3008 09:57:39.801256 DramcWriteLeveling(PI) end<-----
3009 09:57:39.801337
3010 09:57:39.801400 ==
3011 09:57:39.804757 Dram Type= 6, Freq= 0, CH_1, rank 0
3012 09:57:39.807885 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3013 09:57:39.807973 ==
3014 09:57:39.811262 [Gating] SW mode calibration
3015 09:57:39.817879 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3016 09:57:39.821341 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3017 09:57:39.828124 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3018 09:57:39.831300 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3019 09:57:39.834507 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3020 09:57:39.841240 0 11 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3021 09:57:39.844437 0 11 16 | B1->B0 | 3232 2929 | 0 0 | (0 1) (0 1)
3022 09:57:39.847735 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3023 09:57:39.854702 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3024 09:57:39.857797 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3025 09:57:39.861242 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3026 09:57:39.867900 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3027 09:57:39.871103 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3028 09:57:39.874431 0 12 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
3029 09:57:39.881267 0 12 16 | B1->B0 | 3636 4444 | 1 0 | (0 0) (0 0)
3030 09:57:39.884756 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3031 09:57:39.888202 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3032 09:57:39.894538 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3033 09:57:39.897770 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3034 09:57:39.901118 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3035 09:57:39.907608 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3036 09:57:39.911266 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3037 09:57:39.914581 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3038 09:57:39.918037 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3039 09:57:39.924612 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3040 09:57:39.927795 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3041 09:57:39.931246 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3042 09:57:39.937797 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3043 09:57:39.941433 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3044 09:57:39.944534 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3045 09:57:39.951038 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3046 09:57:39.954363 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3047 09:57:39.957929 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3048 09:57:39.964798 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3049 09:57:39.967786 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3050 09:57:39.971272 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3051 09:57:39.978293 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3052 09:57:39.981302 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3053 09:57:39.984471 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3054 09:57:39.991329 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3055 09:57:39.991410 Total UI for P1: 0, mck2ui 16
3056 09:57:39.994876 best dqsien dly found for B0: ( 0, 15, 16)
3057 09:57:39.997686 Total UI for P1: 0, mck2ui 16
3058 09:57:40.001143 best dqsien dly found for B1: ( 0, 15, 16)
3059 09:57:40.007587 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3060 09:57:40.010952 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3061 09:57:40.011033
3062 09:57:40.014339 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3063 09:57:40.017662 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3064 09:57:40.021175 [Gating] SW calibration Done
3065 09:57:40.021255 ==
3066 09:57:40.024434 Dram Type= 6, Freq= 0, CH_1, rank 0
3067 09:57:40.027713 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3068 09:57:40.027800 ==
3069 09:57:40.031287 RX Vref Scan: 0
3070 09:57:40.031367
3071 09:57:40.031431 RX Vref 0 -> 0, step: 1
3072 09:57:40.031490
3073 09:57:40.034352 RX Delay -40 -> 252, step: 8
3074 09:57:40.037771 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3075 09:57:40.044223 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3076 09:57:40.047961 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3077 09:57:40.050898 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3078 09:57:40.054447 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3079 09:57:40.057509 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3080 09:57:40.064426 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3081 09:57:40.067267 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3082 09:57:40.070621 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3083 09:57:40.074398 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3084 09:57:40.077626 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3085 09:57:40.084080 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3086 09:57:40.087564 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3087 09:57:40.090720 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3088 09:57:40.094162 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3089 09:57:40.097313 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3090 09:57:40.097456 ==
3091 09:57:40.100961 Dram Type= 6, Freq= 0, CH_1, rank 0
3092 09:57:40.107438 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3093 09:57:40.107612 ==
3094 09:57:40.107746 DQS Delay:
3095 09:57:40.110781 DQS0 = 0, DQS1 = 0
3096 09:57:40.110924 DQM Delay:
3097 09:57:40.114123 DQM0 = 116, DQM1 = 109
3098 09:57:40.114259 DQ Delay:
3099 09:57:40.117538 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3100 09:57:40.120741 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3101 09:57:40.124058 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =103
3102 09:57:40.127427 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3103 09:57:40.127539
3104 09:57:40.127631
3105 09:57:40.127719 ==
3106 09:57:40.131029 Dram Type= 6, Freq= 0, CH_1, rank 0
3107 09:57:40.133999 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3108 09:57:40.137534 ==
3109 09:57:40.137616
3110 09:57:40.137681
3111 09:57:40.137740 TX Vref Scan disable
3112 09:57:40.140917 == TX Byte 0 ==
3113 09:57:40.144287 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3114 09:57:40.147762 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3115 09:57:40.151028 == TX Byte 1 ==
3116 09:57:40.154241 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3117 09:57:40.157485 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3118 09:57:40.157567 ==
3119 09:57:40.160849 Dram Type= 6, Freq= 0, CH_1, rank 0
3120 09:57:40.167466 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3121 09:57:40.167574 ==
3122 09:57:40.178396 TX Vref=22, minBit 3, minWin=24, winSum=409
3123 09:57:40.181634 TX Vref=24, minBit 3, minWin=25, winSum=420
3124 09:57:40.184951 TX Vref=26, minBit 9, minWin=25, winSum=420
3125 09:57:40.188146 TX Vref=28, minBit 3, minWin=25, winSum=429
3126 09:57:40.191612 TX Vref=30, minBit 9, minWin=25, winSum=431
3127 09:57:40.194836 TX Vref=32, minBit 3, minWin=26, winSum=429
3128 09:57:40.201571 [TxChooseVref] Worse bit 3, Min win 26, Win sum 429, Final Vref 32
3129 09:57:40.201653
3130 09:57:40.205157 Final TX Range 1 Vref 32
3131 09:57:40.205238
3132 09:57:40.205302 ==
3133 09:57:40.208373 Dram Type= 6, Freq= 0, CH_1, rank 0
3134 09:57:40.211676 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3135 09:57:40.211757 ==
3136 09:57:40.211821
3137 09:57:40.211880
3138 09:57:40.214978 TX Vref Scan disable
3139 09:57:40.218357 == TX Byte 0 ==
3140 09:57:40.221631 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3141 09:57:40.225147 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3142 09:57:40.228308 == TX Byte 1 ==
3143 09:57:40.231538 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3144 09:57:40.235224 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3145 09:57:40.235308
3146 09:57:40.238333 [DATLAT]
3147 09:57:40.238418 Freq=1200, CH1 RK0
3148 09:57:40.238504
3149 09:57:40.241768 DATLAT Default: 0xd
3150 09:57:40.241853 0, 0xFFFF, sum = 0
3151 09:57:40.245035 1, 0xFFFF, sum = 0
3152 09:57:40.245121 2, 0xFFFF, sum = 0
3153 09:57:40.248233 3, 0xFFFF, sum = 0
3154 09:57:40.248319 4, 0xFFFF, sum = 0
3155 09:57:40.251686 5, 0xFFFF, sum = 0
3156 09:57:40.251771 6, 0xFFFF, sum = 0
3157 09:57:40.255306 7, 0xFFFF, sum = 0
3158 09:57:40.255391 8, 0xFFFF, sum = 0
3159 09:57:40.258467 9, 0xFFFF, sum = 0
3160 09:57:40.258553 10, 0xFFFF, sum = 0
3161 09:57:40.261758 11, 0x0, sum = 1
3162 09:57:40.261844 12, 0x0, sum = 2
3163 09:57:40.264975 13, 0x0, sum = 3
3164 09:57:40.265060 14, 0x0, sum = 4
3165 09:57:40.268379 best_step = 12
3166 09:57:40.268487
3167 09:57:40.268615 ==
3168 09:57:40.271684 Dram Type= 6, Freq= 0, CH_1, rank 0
3169 09:57:40.275098 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3170 09:57:40.275183 ==
3171 09:57:40.278785 RX Vref Scan: 1
3172 09:57:40.278869
3173 09:57:40.278955 Set Vref Range= 32 -> 127
3174 09:57:40.279037
3175 09:57:40.281662 RX Vref 32 -> 127, step: 1
3176 09:57:40.281746
3177 09:57:40.285382 RX Delay -29 -> 252, step: 4
3178 09:57:40.285466
3179 09:57:40.288387 Set Vref, RX VrefLevel [Byte0]: 32
3180 09:57:40.291917 [Byte1]: 32
3181 09:57:40.292002
3182 09:57:40.295116 Set Vref, RX VrefLevel [Byte0]: 33
3183 09:57:40.298245 [Byte1]: 33
3184 09:57:40.302621
3185 09:57:40.302716 Set Vref, RX VrefLevel [Byte0]: 34
3186 09:57:40.306180 [Byte1]: 34
3187 09:57:40.310894
3188 09:57:40.310978 Set Vref, RX VrefLevel [Byte0]: 35
3189 09:57:40.313812 [Byte1]: 35
3190 09:57:40.318493
3191 09:57:40.318576 Set Vref, RX VrefLevel [Byte0]: 36
3192 09:57:40.321884 [Byte1]: 36
3193 09:57:40.326570
3194 09:57:40.326661 Set Vref, RX VrefLevel [Byte0]: 37
3195 09:57:40.329920 [Byte1]: 37
3196 09:57:40.334281
3197 09:57:40.334361 Set Vref, RX VrefLevel [Byte0]: 38
3198 09:57:40.337898 [Byte1]: 38
3199 09:57:40.342577
3200 09:57:40.342657 Set Vref, RX VrefLevel [Byte0]: 39
3201 09:57:40.345675 [Byte1]: 39
3202 09:57:40.350339
3203 09:57:40.350420 Set Vref, RX VrefLevel [Byte0]: 40
3204 09:57:40.353598 [Byte1]: 40
3205 09:57:40.358318
3206 09:57:40.358398 Set Vref, RX VrefLevel [Byte0]: 41
3207 09:57:40.361727 [Byte1]: 41
3208 09:57:40.366473
3209 09:57:40.366553 Set Vref, RX VrefLevel [Byte0]: 42
3210 09:57:40.369869 [Byte1]: 42
3211 09:57:40.374271
3212 09:57:40.374352 Set Vref, RX VrefLevel [Byte0]: 43
3213 09:57:40.377435 [Byte1]: 43
3214 09:57:40.382084
3215 09:57:40.382164 Set Vref, RX VrefLevel [Byte0]: 44
3216 09:57:40.385587 [Byte1]: 44
3217 09:57:40.390198
3218 09:57:40.390287 Set Vref, RX VrefLevel [Byte0]: 45
3219 09:57:40.393367 [Byte1]: 45
3220 09:57:40.398120
3221 09:57:40.398201 Set Vref, RX VrefLevel [Byte0]: 46
3222 09:57:40.401391 [Byte1]: 46
3223 09:57:40.406361
3224 09:57:40.406441 Set Vref, RX VrefLevel [Byte0]: 47
3225 09:57:40.409328 [Byte1]: 47
3226 09:57:40.414023
3227 09:57:40.414104 Set Vref, RX VrefLevel [Byte0]: 48
3228 09:57:40.417266 [Byte1]: 48
3229 09:57:40.421916
3230 09:57:40.421996 Set Vref, RX VrefLevel [Byte0]: 49
3231 09:57:40.425342 [Byte1]: 49
3232 09:57:40.430080
3233 09:57:40.430160 Set Vref, RX VrefLevel [Byte0]: 50
3234 09:57:40.433384 [Byte1]: 50
3235 09:57:40.437826
3236 09:57:40.437906 Set Vref, RX VrefLevel [Byte0]: 51
3237 09:57:40.441132 [Byte1]: 51
3238 09:57:40.445895
3239 09:57:40.445975 Set Vref, RX VrefLevel [Byte0]: 52
3240 09:57:40.449009 [Byte1]: 52
3241 09:57:40.454057
3242 09:57:40.454138 Set Vref, RX VrefLevel [Byte0]: 53
3243 09:57:40.457030 [Byte1]: 53
3244 09:57:40.461753
3245 09:57:40.461833 Set Vref, RX VrefLevel [Byte0]: 54
3246 09:57:40.465522 [Byte1]: 54
3247 09:57:40.469723
3248 09:57:40.469805 Set Vref, RX VrefLevel [Byte0]: 55
3249 09:57:40.473136 [Byte1]: 55
3250 09:57:40.477801
3251 09:57:40.477881 Set Vref, RX VrefLevel [Byte0]: 56
3252 09:57:40.481109 [Byte1]: 56
3253 09:57:40.485616
3254 09:57:40.485696 Set Vref, RX VrefLevel [Byte0]: 57
3255 09:57:40.488967 [Byte1]: 57
3256 09:57:40.493506
3257 09:57:40.493587 Set Vref, RX VrefLevel [Byte0]: 58
3258 09:57:40.497072 [Byte1]: 58
3259 09:57:40.501463
3260 09:57:40.501544 Set Vref, RX VrefLevel [Byte0]: 59
3261 09:57:40.504906 [Byte1]: 59
3262 09:57:40.509545
3263 09:57:40.509625 Set Vref, RX VrefLevel [Byte0]: 60
3264 09:57:40.512845 [Byte1]: 60
3265 09:57:40.517535
3266 09:57:40.517616 Set Vref, RX VrefLevel [Byte0]: 61
3267 09:57:40.521044 [Byte1]: 61
3268 09:57:40.525610
3269 09:57:40.525691 Set Vref, RX VrefLevel [Byte0]: 62
3270 09:57:40.528753 [Byte1]: 62
3271 09:57:40.533321
3272 09:57:40.533402 Set Vref, RX VrefLevel [Byte0]: 63
3273 09:57:40.536934 [Byte1]: 63
3274 09:57:40.541402
3275 09:57:40.541483 Set Vref, RX VrefLevel [Byte0]: 64
3276 09:57:40.544438 [Byte1]: 64
3277 09:57:40.549516
3278 09:57:40.549597 Set Vref, RX VrefLevel [Byte0]: 65
3279 09:57:40.552476 [Byte1]: 65
3280 09:57:40.557266
3281 09:57:40.557349 Final RX Vref Byte 0 = 53 to rank0
3282 09:57:40.560701 Final RX Vref Byte 1 = 49 to rank0
3283 09:57:40.564071 Final RX Vref Byte 0 = 53 to rank1
3284 09:57:40.567596 Final RX Vref Byte 1 = 49 to rank1==
3285 09:57:40.570668 Dram Type= 6, Freq= 0, CH_1, rank 0
3286 09:57:40.574208 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3287 09:57:40.577476 ==
3288 09:57:40.577558 DQS Delay:
3289 09:57:40.577622 DQS0 = 0, DQS1 = 0
3290 09:57:40.580759 DQM Delay:
3291 09:57:40.580840 DQM0 = 115, DQM1 = 105
3292 09:57:40.584050 DQ Delay:
3293 09:57:40.587459 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3294 09:57:40.590780 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3295 09:57:40.594268 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3296 09:57:40.597534 DQ12 =112, DQ13 =116, DQ14 =116, DQ15 =116
3297 09:57:40.597615
3298 09:57:40.597679
3299 09:57:40.604316 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a1a, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
3300 09:57:40.607795 CH1 RK0: MR19=404, MR18=1A1A
3301 09:57:40.614094 CH1_RK0: MR19=0x404, MR18=0x1A1A, DQSOSC=400, MR23=63, INC=40, DEC=27
3302 09:57:40.614176
3303 09:57:40.617320 ----->DramcWriteLeveling(PI) begin...
3304 09:57:40.617402 ==
3305 09:57:40.620744 Dram Type= 6, Freq= 0, CH_1, rank 1
3306 09:57:40.624230 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3307 09:57:40.624312 ==
3308 09:57:40.627311 Write leveling (Byte 0): 20 => 20
3309 09:57:40.630881 Write leveling (Byte 1): 24 => 24
3310 09:57:40.634446 DramcWriteLeveling(PI) end<-----
3311 09:57:40.634555
3312 09:57:40.634622 ==
3313 09:57:40.637279 Dram Type= 6, Freq= 0, CH_1, rank 1
3314 09:57:40.640860 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3315 09:57:40.643887 ==
3316 09:57:40.643967 [Gating] SW mode calibration
3317 09:57:40.654046 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3318 09:57:40.657547 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3319 09:57:40.660907 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3320 09:57:40.667171 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3321 09:57:40.670943 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3322 09:57:40.673963 0 11 12 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (1 0)
3323 09:57:40.680663 0 11 16 | B1->B0 | 2f2f 2424 | 1 0 | (1 0) (0 0)
3324 09:57:40.684264 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3325 09:57:40.687154 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3326 09:57:40.693860 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3327 09:57:40.697368 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3328 09:57:40.700617 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3329 09:57:40.707445 0 12 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3330 09:57:40.710752 0 12 12 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
3331 09:57:40.713995 0 12 16 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
3332 09:57:40.717376 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3333 09:57:40.724147 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3334 09:57:40.727838 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3335 09:57:40.730986 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3336 09:57:40.737567 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3337 09:57:40.740831 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3338 09:57:40.744332 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3339 09:57:40.750852 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3340 09:57:40.754122 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3341 09:57:40.757308 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3342 09:57:40.764268 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3343 09:57:40.767395 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3344 09:57:40.770857 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3345 09:57:40.777758 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3346 09:57:40.780923 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3347 09:57:40.784174 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3348 09:57:40.790492 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3349 09:57:40.793923 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3350 09:57:40.797403 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3351 09:57:40.803973 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3352 09:57:40.807431 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3353 09:57:40.810677 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3354 09:57:40.817214 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3355 09:57:40.817295 Total UI for P1: 0, mck2ui 16
3356 09:57:40.820686 best dqsien dly found for B0: ( 0, 15, 10)
3357 09:57:40.827054 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3358 09:57:40.830387 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3359 09:57:40.833746 Total UI for P1: 0, mck2ui 16
3360 09:57:40.836981 best dqsien dly found for B1: ( 0, 15, 14)
3361 09:57:40.840650 best DQS0 dly(MCK, UI, PI) = (0, 15, 10)
3362 09:57:40.843914 best DQS1 dly(MCK, UI, PI) = (0, 15, 14)
3363 09:57:40.843995
3364 09:57:40.847016 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 10)
3365 09:57:40.853769 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 14)
3366 09:57:40.853850 [Gating] SW calibration Done
3367 09:57:40.853914 ==
3368 09:57:40.857210 Dram Type= 6, Freq= 0, CH_1, rank 1
3369 09:57:40.863651 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3370 09:57:40.863733 ==
3371 09:57:40.863797 RX Vref Scan: 0
3372 09:57:40.863857
3373 09:57:40.867184 RX Vref 0 -> 0, step: 1
3374 09:57:40.867265
3375 09:57:40.870445 RX Delay -40 -> 252, step: 8
3376 09:57:40.873589 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3377 09:57:40.876914 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3378 09:57:40.880170 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3379 09:57:40.887405 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3380 09:57:40.890898 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3381 09:57:40.893682 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3382 09:57:40.896994 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3383 09:57:40.900458 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3384 09:57:40.904003 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3385 09:57:40.910387 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3386 09:57:40.913723 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
3387 09:57:40.917046 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3388 09:57:40.920441 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3389 09:57:40.923890 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3390 09:57:40.930524 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3391 09:57:40.933986 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3392 09:57:40.934066 ==
3393 09:57:40.937109 Dram Type= 6, Freq= 0, CH_1, rank 1
3394 09:57:40.940400 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3395 09:57:40.940481 ==
3396 09:57:40.944313 DQS Delay:
3397 09:57:40.944393 DQS0 = 0, DQS1 = 0
3398 09:57:40.944457 DQM Delay:
3399 09:57:40.947255 DQM0 = 115, DQM1 = 106
3400 09:57:40.947335 DQ Delay:
3401 09:57:40.950523 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3402 09:57:40.953769 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3403 09:57:40.957307 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =103
3404 09:57:40.963888 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3405 09:57:40.963974
3406 09:57:40.964037
3407 09:57:40.964095 ==
3408 09:57:40.967332 Dram Type= 6, Freq= 0, CH_1, rank 1
3409 09:57:40.970558 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3410 09:57:40.970642 ==
3411 09:57:40.970706
3412 09:57:40.970764
3413 09:57:40.973654 TX Vref Scan disable
3414 09:57:40.973734 == TX Byte 0 ==
3415 09:57:40.980824 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3416 09:57:40.983790 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3417 09:57:40.983871 == TX Byte 1 ==
3418 09:57:40.990436 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3419 09:57:40.993950 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3420 09:57:40.994031 ==
3421 09:57:40.997300 Dram Type= 6, Freq= 0, CH_1, rank 1
3422 09:57:41.000295 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3423 09:57:41.000376 ==
3424 09:57:41.013159 TX Vref=22, minBit 8, minWin=25, winSum=421
3425 09:57:41.016655 TX Vref=24, minBit 11, minWin=25, winSum=425
3426 09:57:41.019901 TX Vref=26, minBit 4, minWin=26, winSum=428
3427 09:57:41.023400 TX Vref=28, minBit 3, minWin=26, winSum=429
3428 09:57:41.026649 TX Vref=30, minBit 8, minWin=26, winSum=432
3429 09:57:41.033382 TX Vref=32, minBit 3, minWin=26, winSum=428
3430 09:57:41.036643 [TxChooseVref] Worse bit 8, Min win 26, Win sum 432, Final Vref 30
3431 09:57:41.036724
3432 09:57:41.039957 Final TX Range 1 Vref 30
3433 09:57:41.040037
3434 09:57:41.040101 ==
3435 09:57:41.043096 Dram Type= 6, Freq= 0, CH_1, rank 1
3436 09:57:41.046504 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3437 09:57:41.046585 ==
3438 09:57:41.049605
3439 09:57:41.049685
3440 09:57:41.049749 TX Vref Scan disable
3441 09:57:41.052993 == TX Byte 0 ==
3442 09:57:41.056454 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3443 09:57:41.059955 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3444 09:57:41.063051 == TX Byte 1 ==
3445 09:57:41.066562 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3446 09:57:41.069610 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3447 09:57:41.072919
3448 09:57:41.073000 [DATLAT]
3449 09:57:41.073065 Freq=1200, CH1 RK1
3450 09:57:41.073125
3451 09:57:41.076437 DATLAT Default: 0xc
3452 09:57:41.076579 0, 0xFFFF, sum = 0
3453 09:57:41.079916 1, 0xFFFF, sum = 0
3454 09:57:41.079998 2, 0xFFFF, sum = 0
3455 09:57:41.082976 3, 0xFFFF, sum = 0
3456 09:57:41.086159 4, 0xFFFF, sum = 0
3457 09:57:41.086241 5, 0xFFFF, sum = 0
3458 09:57:41.089649 6, 0xFFFF, sum = 0
3459 09:57:41.089730 7, 0xFFFF, sum = 0
3460 09:57:41.093010 8, 0xFFFF, sum = 0
3461 09:57:41.093092 9, 0xFFFF, sum = 0
3462 09:57:41.096490 10, 0xFFFF, sum = 0
3463 09:57:41.096581 11, 0x0, sum = 1
3464 09:57:41.099718 12, 0x0, sum = 2
3465 09:57:41.099800 13, 0x0, sum = 3
3466 09:57:41.102956 14, 0x0, sum = 4
3467 09:57:41.103039 best_step = 12
3468 09:57:41.103104
3469 09:57:41.103163 ==
3470 09:57:41.106479 Dram Type= 6, Freq= 0, CH_1, rank 1
3471 09:57:41.110059 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3472 09:57:41.110141 ==
3473 09:57:41.113144 RX Vref Scan: 0
3474 09:57:41.113225
3475 09:57:41.116264 RX Vref 0 -> 0, step: 1
3476 09:57:41.116345
3477 09:57:41.116409 RX Delay -29 -> 252, step: 4
3478 09:57:41.123993 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3479 09:57:41.126771 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3480 09:57:41.130343 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3481 09:57:41.133924 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3482 09:57:41.136764 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3483 09:57:41.143360 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3484 09:57:41.147344 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3485 09:57:41.150496 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144
3486 09:57:41.153765 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3487 09:57:41.156931 iDelay=199, Bit 9, Center 90 (23 ~ 158) 136
3488 09:57:41.163577 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3489 09:57:41.166793 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3490 09:57:41.170355 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3491 09:57:41.173668 iDelay=199, Bit 13, Center 110 (43 ~ 178) 136
3492 09:57:41.176855 iDelay=199, Bit 14, Center 112 (43 ~ 182) 140
3493 09:57:41.183618 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3494 09:57:41.183699 ==
3495 09:57:41.187066 Dram Type= 6, Freq= 0, CH_1, rank 1
3496 09:57:41.190023 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3497 09:57:41.190104 ==
3498 09:57:41.190170 DQS Delay:
3499 09:57:41.193744 DQS0 = 0, DQS1 = 0
3500 09:57:41.193824 DQM Delay:
3501 09:57:41.196810 DQM0 = 115, DQM1 = 103
3502 09:57:41.196891 DQ Delay:
3503 09:57:41.200217 DQ0 =116, DQ1 =110, DQ2 =108, DQ3 =112
3504 09:57:41.203527 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3505 09:57:41.206933 DQ8 =86, DQ9 =90, DQ10 =106, DQ11 =98
3506 09:57:41.210341 DQ12 =112, DQ13 =110, DQ14 =112, DQ15 =110
3507 09:57:41.210421
3508 09:57:41.210484
3509 09:57:41.220038 [DQSOSCAuto] RK1, (LSB)MR18= 0x909, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
3510 09:57:41.223387 CH1 RK1: MR19=404, MR18=909
3511 09:57:41.226735 CH1_RK1: MR19=0x404, MR18=0x909, DQSOSC=406, MR23=63, INC=39, DEC=26
3512 09:57:41.230112 [RxdqsGatingPostProcess] freq 1200
3513 09:57:41.236693 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3514 09:57:41.240068 Pre-setting of DQS Precalculation
3515 09:57:41.243317 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3516 09:57:41.253368 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3517 09:57:41.260226 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3518 09:57:41.260308
3519 09:57:41.260372
3520 09:57:41.263387 [Calibration Summary] 2400 Mbps
3521 09:57:41.263468 CH 0, Rank 0
3522 09:57:41.266700 SW Impedance : PASS
3523 09:57:41.266781 DUTY Scan : NO K
3524 09:57:41.270355 ZQ Calibration : PASS
3525 09:57:41.273577 Jitter Meter : NO K
3526 09:57:41.273658 CBT Training : PASS
3527 09:57:41.276730 Write leveling : PASS
3528 09:57:41.279972 RX DQS gating : PASS
3529 09:57:41.280053 RX DQ/DQS(RDDQC) : PASS
3530 09:57:41.283658 TX DQ/DQS : PASS
3531 09:57:41.283739 RX DATLAT : PASS
3532 09:57:41.286867 RX DQ/DQS(Engine): PASS
3533 09:57:41.290472 TX OE : NO K
3534 09:57:41.290552 All Pass.
3535 09:57:41.290616
3536 09:57:41.290676 CH 0, Rank 1
3537 09:57:41.293696 SW Impedance : PASS
3538 09:57:41.297030 DUTY Scan : NO K
3539 09:57:41.297110 ZQ Calibration : PASS
3540 09:57:41.300140 Jitter Meter : NO K
3541 09:57:41.303281 CBT Training : PASS
3542 09:57:41.303362 Write leveling : PASS
3543 09:57:41.306942 RX DQS gating : PASS
3544 09:57:41.310116 RX DQ/DQS(RDDQC) : PASS
3545 09:57:41.310196 TX DQ/DQS : PASS
3546 09:57:41.313477 RX DATLAT : PASS
3547 09:57:41.316858 RX DQ/DQS(Engine): PASS
3548 09:57:41.316939 TX OE : NO K
3549 09:57:41.320332 All Pass.
3550 09:57:41.320413
3551 09:57:41.320477 CH 1, Rank 0
3552 09:57:41.323356 SW Impedance : PASS
3553 09:57:41.323436 DUTY Scan : NO K
3554 09:57:41.326652 ZQ Calibration : PASS
3555 09:57:41.330187 Jitter Meter : NO K
3556 09:57:41.330268 CBT Training : PASS
3557 09:57:41.333303 Write leveling : PASS
3558 09:57:41.333383 RX DQS gating : PASS
3559 09:57:41.336434 RX DQ/DQS(RDDQC) : PASS
3560 09:57:41.339914 TX DQ/DQS : PASS
3561 09:57:41.339995 RX DATLAT : PASS
3562 09:57:41.343386 RX DQ/DQS(Engine): PASS
3563 09:57:41.346552 TX OE : NO K
3564 09:57:41.346633 All Pass.
3565 09:57:41.346697
3566 09:57:41.346755 CH 1, Rank 1
3567 09:57:41.349891 SW Impedance : PASS
3568 09:57:41.353393 DUTY Scan : NO K
3569 09:57:41.353474 ZQ Calibration : PASS
3570 09:57:41.356463 Jitter Meter : NO K
3571 09:57:41.360003 CBT Training : PASS
3572 09:57:41.360085 Write leveling : PASS
3573 09:57:41.363244 RX DQS gating : PASS
3574 09:57:41.366530 RX DQ/DQS(RDDQC) : PASS
3575 09:57:41.366611 TX DQ/DQS : PASS
3576 09:57:41.370021 RX DATLAT : PASS
3577 09:57:41.373334 RX DQ/DQS(Engine): PASS
3578 09:57:41.373415 TX OE : NO K
3579 09:57:41.373479 All Pass.
3580 09:57:41.377122
3581 09:57:41.377202 DramC Write-DBI off
3582 09:57:41.379923 PER_BANK_REFRESH: Hybrid Mode
3583 09:57:41.380003 TX_TRACKING: ON
3584 09:57:41.390075 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3585 09:57:41.393371 [FAST_K] Save calibration result to emmc
3586 09:57:41.397005 dramc_set_vcore_voltage set vcore to 650000
3587 09:57:41.400452 Read voltage for 600, 5
3588 09:57:41.400570 Vio18 = 0
3589 09:57:41.403401 Vcore = 650000
3590 09:57:41.403481 Vdram = 0
3591 09:57:41.403546 Vddq = 0
3592 09:57:41.403605 Vmddr = 0
3593 09:57:41.410161 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3594 09:57:41.413349 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3595 09:57:41.416783 MEM_TYPE=3, freq_sel=19
3596 09:57:41.420315 sv_algorithm_assistance_LP4_1600
3597 09:57:41.423590 ============ PULL DRAM RESETB DOWN ============
3598 09:57:41.430340 ========== PULL DRAM RESETB DOWN end =========
3599 09:57:41.433709 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3600 09:57:41.436593 ===================================
3601 09:57:41.439815 LPDDR4 DRAM CONFIGURATION
3602 09:57:41.443233 ===================================
3603 09:57:41.443313 EX_ROW_EN[0] = 0x0
3604 09:57:41.446594 EX_ROW_EN[1] = 0x0
3605 09:57:41.446674 LP4Y_EN = 0x0
3606 09:57:41.450049 WORK_FSP = 0x0
3607 09:57:41.450130 WL = 0x2
3608 09:57:41.453139 RL = 0x2
3609 09:57:41.453220 BL = 0x2
3610 09:57:41.456486 RPST = 0x0
3611 09:57:41.456610 RD_PRE = 0x0
3612 09:57:41.459967 WR_PRE = 0x1
3613 09:57:41.460048 WR_PST = 0x0
3614 09:57:41.463180 DBI_WR = 0x0
3615 09:57:41.466478 DBI_RD = 0x0
3616 09:57:41.466559 OTF = 0x1
3617 09:57:41.469801 ===================================
3618 09:57:41.473035 ===================================
3619 09:57:41.473116 ANA top config
3620 09:57:41.476810 ===================================
3621 09:57:41.479829 DLL_ASYNC_EN = 0
3622 09:57:41.482937 ALL_SLAVE_EN = 1
3623 09:57:41.486286 NEW_RANK_MODE = 1
3624 09:57:41.489695 DLL_IDLE_MODE = 1
3625 09:57:41.489775 LP45_APHY_COMB_EN = 1
3626 09:57:41.492981 TX_ODT_DIS = 1
3627 09:57:41.496228 NEW_8X_MODE = 1
3628 09:57:41.499709 ===================================
3629 09:57:41.503188 ===================================
3630 09:57:41.506496 data_rate = 1200
3631 09:57:41.509431 CKR = 1
3632 09:57:41.509511 DQ_P2S_RATIO = 8
3633 09:57:41.513151 ===================================
3634 09:57:41.516253 CA_P2S_RATIO = 8
3635 09:57:41.519412 DQ_CA_OPEN = 0
3636 09:57:41.523016 DQ_SEMI_OPEN = 0
3637 09:57:41.526076 CA_SEMI_OPEN = 0
3638 09:57:41.529615 CA_FULL_RATE = 0
3639 09:57:41.529695 DQ_CKDIV4_EN = 1
3640 09:57:41.533050 CA_CKDIV4_EN = 1
3641 09:57:41.536303 CA_PREDIV_EN = 0
3642 09:57:41.539549 PH8_DLY = 0
3643 09:57:41.542898 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3644 09:57:41.546164 DQ_AAMCK_DIV = 4
3645 09:57:41.546245 CA_AAMCK_DIV = 4
3646 09:57:41.549500 CA_ADMCK_DIV = 4
3647 09:57:41.552451 DQ_TRACK_CA_EN = 0
3648 09:57:41.556294 CA_PICK = 600
3649 09:57:41.559108 CA_MCKIO = 600
3650 09:57:41.562675 MCKIO_SEMI = 0
3651 09:57:41.566029 PLL_FREQ = 2288
3652 09:57:41.566110 DQ_UI_PI_RATIO = 32
3653 09:57:41.569478 CA_UI_PI_RATIO = 0
3654 09:57:41.572828 ===================================
3655 09:57:41.575727 ===================================
3656 09:57:41.578995 memory_type:LPDDR4
3657 09:57:41.582303 GP_NUM : 10
3658 09:57:41.582384 SRAM_EN : 1
3659 09:57:41.585626 MD32_EN : 0
3660 09:57:41.589194 ===================================
3661 09:57:41.592334 [ANA_INIT] >>>>>>>>>>>>>>
3662 09:57:41.592414 <<<<<< [CONFIGURE PHASE]: ANA_TX
3663 09:57:41.595984 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3664 09:57:41.599028 ===================================
3665 09:57:41.602240 data_rate = 1200,PCW = 0X5800
3666 09:57:41.605688 ===================================
3667 09:57:41.609052 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3668 09:57:41.615353 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3669 09:57:41.622108 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3670 09:57:41.625276 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3671 09:57:41.628889 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3672 09:57:41.632391 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3673 09:57:41.635301 [ANA_INIT] flow start
3674 09:57:41.635382 [ANA_INIT] PLL >>>>>>>>
3675 09:57:41.638963 [ANA_INIT] PLL <<<<<<<<
3676 09:57:41.642119 [ANA_INIT] MIDPI >>>>>>>>
3677 09:57:41.645353 [ANA_INIT] MIDPI <<<<<<<<
3678 09:57:41.645433 [ANA_INIT] DLL >>>>>>>>
3679 09:57:41.648466 [ANA_INIT] flow end
3680 09:57:41.651800 ============ LP4 DIFF to SE enter ============
3681 09:57:41.655075 ============ LP4 DIFF to SE exit ============
3682 09:57:41.658457 [ANA_INIT] <<<<<<<<<<<<<
3683 09:57:41.661786 [Flow] Enable top DCM control >>>>>
3684 09:57:41.665078 [Flow] Enable top DCM control <<<<<
3685 09:57:41.668415 Enable DLL master slave shuffle
3686 09:57:41.674951 ==============================================================
3687 09:57:41.675032 Gating Mode config
3688 09:57:41.681731 ==============================================================
3689 09:57:41.681812 Config description:
3690 09:57:41.691511 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3691 09:57:41.698231 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3692 09:57:41.704906 SELPH_MODE 0: By rank 1: By Phase
3693 09:57:41.708088 ==============================================================
3694 09:57:41.711705 GAT_TRACK_EN = 1
3695 09:57:41.714724 RX_GATING_MODE = 2
3696 09:57:41.718120 RX_GATING_TRACK_MODE = 2
3697 09:57:41.721630 SELPH_MODE = 1
3698 09:57:41.724551 PICG_EARLY_EN = 1
3699 09:57:41.727987 VALID_LAT_VALUE = 1
3700 09:57:41.734686 ==============================================================
3701 09:57:41.737955 Enter into Gating configuration >>>>
3702 09:57:41.741229 Exit from Gating configuration <<<<
3703 09:57:41.741310 Enter into DVFS_PRE_config >>>>>
3704 09:57:41.754638 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3705 09:57:41.758018 Exit from DVFS_PRE_config <<<<<
3706 09:57:41.761161 Enter into PICG configuration >>>>
3707 09:57:41.764768 Exit from PICG configuration <<<<
3708 09:57:41.764849 [RX_INPUT] configuration >>>>>
3709 09:57:41.767823 [RX_INPUT] configuration <<<<<
3710 09:57:41.774396 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3711 09:57:41.777875 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3712 09:57:41.784340 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3713 09:57:41.791046 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3714 09:57:41.797576 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3715 09:57:41.804261 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3716 09:57:41.807677 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3717 09:57:41.810760 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3718 09:57:41.817610 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3719 09:57:41.820611 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3720 09:57:41.824078 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3721 09:57:41.830812 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3722 09:57:41.830894 ===================================
3723 09:57:41.834025 LPDDR4 DRAM CONFIGURATION
3724 09:57:41.837285 ===================================
3725 09:57:41.840652 EX_ROW_EN[0] = 0x0
3726 09:57:41.840732 EX_ROW_EN[1] = 0x0
3727 09:57:41.844226 LP4Y_EN = 0x0
3728 09:57:41.844307 WORK_FSP = 0x0
3729 09:57:41.847169 WL = 0x2
3730 09:57:41.847249 RL = 0x2
3731 09:57:41.850564 BL = 0x2
3732 09:57:41.850664 RPST = 0x0
3733 09:57:41.854176 RD_PRE = 0x0
3734 09:57:41.857272 WR_PRE = 0x1
3735 09:57:41.857352 WR_PST = 0x0
3736 09:57:41.860631 DBI_WR = 0x0
3737 09:57:41.860711 DBI_RD = 0x0
3738 09:57:41.864064 OTF = 0x1
3739 09:57:41.867531 ===================================
3740 09:57:41.870817 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3741 09:57:41.873953 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3742 09:57:41.876999 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3743 09:57:41.880703 ===================================
3744 09:57:41.884262 LPDDR4 DRAM CONFIGURATION
3745 09:57:41.887352 ===================================
3746 09:57:41.890535 EX_ROW_EN[0] = 0x10
3747 09:57:41.890616 EX_ROW_EN[1] = 0x0
3748 09:57:41.893941 LP4Y_EN = 0x0
3749 09:57:41.894021 WORK_FSP = 0x0
3750 09:57:41.897101 WL = 0x2
3751 09:57:41.897183 RL = 0x2
3752 09:57:41.900329 BL = 0x2
3753 09:57:41.900409 RPST = 0x0
3754 09:57:41.903885 RD_PRE = 0x0
3755 09:57:41.903965 WR_PRE = 0x1
3756 09:57:41.907256 WR_PST = 0x0
3757 09:57:41.907336 DBI_WR = 0x0
3758 09:57:41.910460 DBI_RD = 0x0
3759 09:57:41.913992 OTF = 0x1
3760 09:57:41.914074 ===================================
3761 09:57:41.920387 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3762 09:57:41.925436 nWR fixed to 30
3763 09:57:41.929024 [ModeRegInit_LP4] CH0 RK0
3764 09:57:41.929104 [ModeRegInit_LP4] CH0 RK1
3765 09:57:41.932003 [ModeRegInit_LP4] CH1 RK0
3766 09:57:41.935274 [ModeRegInit_LP4] CH1 RK1
3767 09:57:41.935355 match AC timing 16
3768 09:57:41.942024 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3769 09:57:41.945242 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3770 09:57:41.948767 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3771 09:57:41.955692 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3772 09:57:41.958951 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3773 09:57:41.959033 ==
3774 09:57:41.961889 Dram Type= 6, Freq= 0, CH_0, rank 0
3775 09:57:41.965273 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3776 09:57:41.965354 ==
3777 09:57:41.971717 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3778 09:57:41.978382 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3779 09:57:41.981766 [CA 0] Center 35 (5~66) winsize 62
3780 09:57:41.985101 [CA 1] Center 35 (5~66) winsize 62
3781 09:57:41.988630 [CA 2] Center 34 (4~65) winsize 62
3782 09:57:41.991849 [CA 3] Center 34 (3~65) winsize 63
3783 09:57:41.995009 [CA 4] Center 33 (3~64) winsize 62
3784 09:57:41.998241 [CA 5] Center 33 (3~64) winsize 62
3785 09:57:41.998322
3786 09:57:42.001838 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3787 09:57:42.001919
3788 09:57:42.005108 [CATrainingPosCal] consider 1 rank data
3789 09:57:42.008450 u2DelayCellTimex100 = 270/100 ps
3790 09:57:42.011667 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3791 09:57:42.015000 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3792 09:57:42.018761 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3793 09:57:42.021717 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3794 09:57:42.025313 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3795 09:57:42.028596 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3796 09:57:42.028678
3797 09:57:42.035055 CA PerBit enable=1, Macro0, CA PI delay=33
3798 09:57:42.035136
3799 09:57:42.038443 [CBTSetCACLKResult] CA Dly = 33
3800 09:57:42.038571 CS Dly: 4 (0~35)
3801 09:57:42.038641 ==
3802 09:57:42.041769 Dram Type= 6, Freq= 0, CH_0, rank 1
3803 09:57:42.044913 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3804 09:57:42.044995 ==
3805 09:57:42.051679 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3806 09:57:42.058242 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3807 09:57:42.061775 [CA 0] Center 35 (5~66) winsize 62
3808 09:57:42.064768 [CA 1] Center 36 (6~66) winsize 61
3809 09:57:42.068421 [CA 2] Center 34 (4~65) winsize 62
3810 09:57:42.071376 [CA 3] Center 34 (4~65) winsize 62
3811 09:57:42.074828 [CA 4] Center 33 (3~64) winsize 62
3812 09:57:42.078281 [CA 5] Center 33 (3~64) winsize 62
3813 09:57:42.078361
3814 09:57:42.081307 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3815 09:57:42.081388
3816 09:57:42.084851 [CATrainingPosCal] consider 2 rank data
3817 09:57:42.088185 u2DelayCellTimex100 = 270/100 ps
3818 09:57:42.091250 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3819 09:57:42.094852 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3820 09:57:42.098065 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3821 09:57:42.101159 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3822 09:57:42.108051 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3823 09:57:42.111491 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3824 09:57:42.111572
3825 09:57:42.114414 CA PerBit enable=1, Macro0, CA PI delay=33
3826 09:57:42.114495
3827 09:57:42.117779 [CBTSetCACLKResult] CA Dly = 33
3828 09:57:42.117859 CS Dly: 5 (0~37)
3829 09:57:42.117923
3830 09:57:42.121261 ----->DramcWriteLeveling(PI) begin...
3831 09:57:42.121343 ==
3832 09:57:42.124357 Dram Type= 6, Freq= 0, CH_0, rank 0
3833 09:57:42.131119 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3834 09:57:42.131200 ==
3835 09:57:42.134256 Write leveling (Byte 0): 30 => 30
3836 09:57:42.137619 Write leveling (Byte 1): 30 => 30
3837 09:57:42.137699 DramcWriteLeveling(PI) end<-----
3838 09:57:42.137764
3839 09:57:42.141034 ==
3840 09:57:42.141115 Dram Type= 6, Freq= 0, CH_0, rank 0
3841 09:57:42.147671 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3842 09:57:42.147752 ==
3843 09:57:42.151150 [Gating] SW mode calibration
3844 09:57:42.157665 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3845 09:57:42.161058 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3846 09:57:42.167737 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3847 09:57:42.171055 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3848 09:57:42.174505 0 5 8 | B1->B0 | 3434 3131 | 0 0 | (0 0) (0 0)
3849 09:57:42.180773 0 5 12 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
3850 09:57:42.183876 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3851 09:57:42.187674 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3852 09:57:42.193963 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3853 09:57:42.197641 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3854 09:57:42.200693 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3855 09:57:42.207202 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3856 09:57:42.210589 0 6 8 | B1->B0 | 2626 3434 | 0 0 | (0 0) (0 0)
3857 09:57:42.213808 0 6 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
3858 09:57:42.220448 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3859 09:57:42.224121 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3860 09:57:42.227256 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3861 09:57:42.233685 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3862 09:57:42.237296 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3863 09:57:42.240251 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3864 09:57:42.247250 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3865 09:57:42.250324 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3866 09:57:42.253566 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3867 09:57:42.260305 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3868 09:57:42.263514 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3869 09:57:42.266981 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3870 09:57:42.273573 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3871 09:57:42.276821 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3872 09:57:42.280149 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3873 09:57:42.283322 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3874 09:57:42.290285 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3875 09:57:42.293822 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3876 09:57:42.296842 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3877 09:57:42.303516 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3878 09:57:42.306702 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3879 09:57:42.310243 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3880 09:57:42.316925 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3881 09:57:42.320493 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3882 09:57:42.323443 Total UI for P1: 0, mck2ui 16
3883 09:57:42.326708 best dqsien dly found for B0: ( 0, 9, 10)
3884 09:57:42.330172 Total UI for P1: 0, mck2ui 16
3885 09:57:42.333294 best dqsien dly found for B1: ( 0, 9, 10)
3886 09:57:42.336636 best DQS0 dly(MCK, UI, PI) = (0, 9, 10)
3887 09:57:42.339870 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
3888 09:57:42.339951
3889 09:57:42.343246 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10)
3890 09:57:42.346508 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
3891 09:57:42.349926 [Gating] SW calibration Done
3892 09:57:42.350007 ==
3893 09:57:42.353178 Dram Type= 6, Freq= 0, CH_0, rank 0
3894 09:57:42.359874 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3895 09:57:42.359959 ==
3896 09:57:42.360046 RX Vref Scan: 0
3897 09:57:42.360127
3898 09:57:42.363199 RX Vref 0 -> 0, step: 1
3899 09:57:42.363283
3900 09:57:42.366508 RX Delay -230 -> 252, step: 16
3901 09:57:42.369889 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3902 09:57:42.373140 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
3903 09:57:42.376443 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
3904 09:57:42.383205 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3905 09:57:42.386282 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3906 09:57:42.389578 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3907 09:57:42.393171 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3908 09:57:42.396250 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3909 09:57:42.403124 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3910 09:57:42.406350 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3911 09:57:42.409710 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3912 09:57:42.412852 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3913 09:57:42.419788 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3914 09:57:42.422735 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3915 09:57:42.426580 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3916 09:57:42.429757 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3917 09:57:42.432669 ==
3918 09:57:42.432753 Dram Type= 6, Freq= 0, CH_0, rank 0
3919 09:57:42.439421 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3920 09:57:42.439507 ==
3921 09:57:42.439592 DQS Delay:
3922 09:57:42.442704 DQS0 = 0, DQS1 = 0
3923 09:57:42.442789 DQM Delay:
3924 09:57:42.446211 DQM0 = 40, DQM1 = 33
3925 09:57:42.446295 DQ Delay:
3926 09:57:42.449445 DQ0 =33, DQ1 =41, DQ2 =41, DQ3 =33
3927 09:57:42.452774 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3928 09:57:42.455932 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3929 09:57:42.459245 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3930 09:57:42.459330
3931 09:57:42.459415
3932 09:57:42.459496 ==
3933 09:57:42.462670 Dram Type= 6, Freq= 0, CH_0, rank 0
3934 09:57:42.466024 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3935 09:57:42.466108 ==
3936 09:57:42.466194
3937 09:57:42.466274
3938 09:57:42.469499 TX Vref Scan disable
3939 09:57:42.472476 == TX Byte 0 ==
3940 09:57:42.476029 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3941 09:57:42.479264 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3942 09:57:42.482690 == TX Byte 1 ==
3943 09:57:42.486048 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3944 09:57:42.489234 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3945 09:57:42.489319 ==
3946 09:57:42.492355 Dram Type= 6, Freq= 0, CH_0, rank 0
3947 09:57:42.495664 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3948 09:57:42.498912 ==
3949 09:57:42.498996
3950 09:57:42.499081
3951 09:57:42.499162 TX Vref Scan disable
3952 09:57:42.503179 == TX Byte 0 ==
3953 09:57:42.506193 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3954 09:57:42.509700 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3955 09:57:42.513007 == TX Byte 1 ==
3956 09:57:42.516387 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3957 09:57:42.523232 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3958 09:57:42.523317
3959 09:57:42.523403 [DATLAT]
3960 09:57:42.523483 Freq=600, CH0 RK0
3961 09:57:42.523563
3962 09:57:42.526366 DATLAT Default: 0x9
3963 09:57:42.526450 0, 0xFFFF, sum = 0
3964 09:57:42.529552 1, 0xFFFF, sum = 0
3965 09:57:42.529637 2, 0xFFFF, sum = 0
3966 09:57:42.533103 3, 0xFFFF, sum = 0
3967 09:57:42.536495 4, 0xFFFF, sum = 0
3968 09:57:42.536618 5, 0xFFFF, sum = 0
3969 09:57:42.539575 6, 0xFFFF, sum = 0
3970 09:57:42.539661 7, 0x0, sum = 1
3971 09:57:42.539750 8, 0x0, sum = 2
3972 09:57:42.542846 9, 0x0, sum = 3
3973 09:57:42.542931 10, 0x0, sum = 4
3974 09:57:42.546304 best_step = 8
3975 09:57:42.546388
3976 09:57:42.546474 ==
3977 09:57:42.549708 Dram Type= 6, Freq= 0, CH_0, rank 0
3978 09:57:42.552986 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3979 09:57:42.553070 ==
3980 09:57:42.556111 RX Vref Scan: 1
3981 09:57:42.556195
3982 09:57:42.556281 RX Vref 0 -> 0, step: 1
3983 09:57:42.556381
3984 09:57:42.559368 RX Delay -195 -> 252, step: 8
3985 09:57:42.559452
3986 09:57:42.562698 Set Vref, RX VrefLevel [Byte0]: 46
3987 09:57:42.565956 [Byte1]: 49
3988 09:57:42.570068
3989 09:57:42.570152 Final RX Vref Byte 0 = 46 to rank0
3990 09:57:42.573471 Final RX Vref Byte 1 = 49 to rank0
3991 09:57:42.576819 Final RX Vref Byte 0 = 46 to rank1
3992 09:57:42.580259 Final RX Vref Byte 1 = 49 to rank1==
3993 09:57:42.583455 Dram Type= 6, Freq= 0, CH_0, rank 0
3994 09:57:42.590096 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3995 09:57:42.590180 ==
3996 09:57:42.590266 DQS Delay:
3997 09:57:42.590347 DQS0 = 0, DQS1 = 0
3998 09:57:42.593439 DQM Delay:
3999 09:57:42.593523 DQM0 = 39, DQM1 = 30
4000 09:57:42.596384 DQ Delay:
4001 09:57:42.600060 DQ0 =36, DQ1 =40, DQ2 =36, DQ3 =36
4002 09:57:42.603248 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =44
4003 09:57:42.606289 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4004 09:57:42.609679 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4005 09:57:42.609763
4006 09:57:42.609848
4007 09:57:42.616651 [DQSOSCAuto] RK0, (LSB)MR18= 0x5e5e, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
4008 09:57:42.619656 CH0 RK0: MR19=808, MR18=5E5E
4009 09:57:42.626723 CH0_RK0: MR19=0x808, MR18=0x5E5E, DQSOSC=392, MR23=63, INC=170, DEC=113
4010 09:57:42.626808
4011 09:57:42.629544 ----->DramcWriteLeveling(PI) begin...
4012 09:57:42.629672 ==
4013 09:57:42.633056 Dram Type= 6, Freq= 0, CH_0, rank 1
4014 09:57:42.636383 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4015 09:57:42.636515 ==
4016 09:57:42.639727 Write leveling (Byte 0): 32 => 32
4017 09:57:42.643063 Write leveling (Byte 1): 29 => 29
4018 09:57:42.646330 DramcWriteLeveling(PI) end<-----
4019 09:57:42.646411
4020 09:57:42.646474 ==
4021 09:57:42.649643 Dram Type= 6, Freq= 0, CH_0, rank 1
4022 09:57:42.652733 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4023 09:57:42.652815 ==
4024 09:57:42.656475 [Gating] SW mode calibration
4025 09:57:42.663001 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4026 09:57:42.669370 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4027 09:57:42.672977 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4028 09:57:42.679592 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4029 09:57:42.682752 0 5 8 | B1->B0 | 3333 3333 | 0 0 | (0 1) (0 1)
4030 09:57:42.686266 0 5 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4031 09:57:42.692736 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4032 09:57:42.696056 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4033 09:57:42.699507 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4034 09:57:42.705891 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4035 09:57:42.709280 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4036 09:57:42.712472 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 09:57:42.716047 0 6 8 | B1->B0 | 2d2d 3232 | 0 0 | (1 1) (0 0)
4038 09:57:42.722613 0 6 12 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
4039 09:57:42.725954 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 09:57:42.729362 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 09:57:42.735745 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 09:57:42.739264 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 09:57:42.742461 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 09:57:42.749070 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 09:57:42.752734 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4046 09:57:42.755668 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 09:57:42.762232 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 09:57:42.765980 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 09:57:42.769002 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 09:57:42.775533 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 09:57:42.779039 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 09:57:42.782743 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 09:57:42.788706 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 09:57:42.792309 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 09:57:42.795545 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 09:57:42.802260 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 09:57:42.805473 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 09:57:42.808738 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 09:57:42.815480 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 09:57:42.818729 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 09:57:42.821996 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4062 09:57:42.828582 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 09:57:42.828663 Total UI for P1: 0, mck2ui 16
4064 09:57:42.835068 best dqsien dly found for B0: ( 0, 9, 8)
4065 09:57:42.835149 Total UI for P1: 0, mck2ui 16
4066 09:57:42.841770 best dqsien dly found for B1: ( 0, 9, 8)
4067 09:57:42.845198 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4068 09:57:42.848419 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4069 09:57:42.848531
4070 09:57:42.851846 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4071 09:57:42.854874 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4072 09:57:42.858525 [Gating] SW calibration Done
4073 09:57:42.858606 ==
4074 09:57:42.861583 Dram Type= 6, Freq= 0, CH_0, rank 1
4075 09:57:42.865076 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4076 09:57:42.865158 ==
4077 09:57:42.868637 RX Vref Scan: 0
4078 09:57:42.868742
4079 09:57:42.868834 RX Vref 0 -> 0, step: 1
4080 09:57:42.868921
4081 09:57:42.871674 RX Delay -230 -> 252, step: 16
4082 09:57:42.874767 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4083 09:57:42.881521 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4084 09:57:42.884838 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4085 09:57:42.888189 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4086 09:57:42.891527 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4087 09:57:42.897951 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4088 09:57:42.901524 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4089 09:57:42.904985 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4090 09:57:42.908412 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4091 09:57:42.911497 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4092 09:57:42.918245 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4093 09:57:42.921511 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4094 09:57:42.924796 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4095 09:57:42.928307 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4096 09:57:42.934969 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4097 09:57:42.938211 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4098 09:57:42.938318 ==
4099 09:57:42.941659 Dram Type= 6, Freq= 0, CH_0, rank 1
4100 09:57:42.944813 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4101 09:57:42.944895 ==
4102 09:57:42.948063 DQS Delay:
4103 09:57:42.948143 DQS0 = 0, DQS1 = 0
4104 09:57:42.948207 DQM Delay:
4105 09:57:42.951345 DQM0 = 44, DQM1 = 35
4106 09:57:42.951426 DQ Delay:
4107 09:57:42.954633 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4108 09:57:42.957944 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4109 09:57:42.961287 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =33
4110 09:57:42.964523 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4111 09:57:42.964605
4112 09:57:42.964669
4113 09:57:42.964729 ==
4114 09:57:42.967998 Dram Type= 6, Freq= 0, CH_0, rank 1
4115 09:57:42.974674 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4116 09:57:42.974756 ==
4117 09:57:42.974820
4118 09:57:42.974879
4119 09:57:42.974936 TX Vref Scan disable
4120 09:57:42.978426 == TX Byte 0 ==
4121 09:57:42.982183 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4122 09:57:42.988269 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4123 09:57:42.988350 == TX Byte 1 ==
4124 09:57:42.991796 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4125 09:57:42.998118 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4126 09:57:42.998198 ==
4127 09:57:43.001386 Dram Type= 6, Freq= 0, CH_0, rank 1
4128 09:57:43.004717 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4129 09:57:43.004799 ==
4130 09:57:43.004863
4131 09:57:43.004922
4132 09:57:43.008016 TX Vref Scan disable
4133 09:57:43.011704 == TX Byte 0 ==
4134 09:57:43.014813 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4135 09:57:43.018224 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4136 09:57:43.021268 == TX Byte 1 ==
4137 09:57:43.024540 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4138 09:57:43.027876 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4139 09:57:43.027956
4140 09:57:43.028020 [DATLAT]
4141 09:57:43.031321 Freq=600, CH0 RK1
4142 09:57:43.031402
4143 09:57:43.034655 DATLAT Default: 0x8
4144 09:57:43.034736 0, 0xFFFF, sum = 0
4145 09:57:43.037871 1, 0xFFFF, sum = 0
4146 09:57:43.037981 2, 0xFFFF, sum = 0
4147 09:57:43.041338 3, 0xFFFF, sum = 0
4148 09:57:43.041420 4, 0xFFFF, sum = 0
4149 09:57:43.044626 5, 0xFFFF, sum = 0
4150 09:57:43.044708 6, 0xFFFF, sum = 0
4151 09:57:43.047773 7, 0x0, sum = 1
4152 09:57:43.047855 8, 0x0, sum = 2
4153 09:57:43.047920 9, 0x0, sum = 3
4154 09:57:43.051286 10, 0x0, sum = 4
4155 09:57:43.051368 best_step = 8
4156 09:57:43.051432
4157 09:57:43.054616 ==
4158 09:57:43.054697 Dram Type= 6, Freq= 0, CH_0, rank 1
4159 09:57:43.061036 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4160 09:57:43.061118 ==
4161 09:57:43.061182 RX Vref Scan: 0
4162 09:57:43.061242
4163 09:57:43.064268 RX Vref 0 -> 0, step: 1
4164 09:57:43.064348
4165 09:57:43.068017 RX Delay -195 -> 252, step: 8
4166 09:57:43.074647 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4167 09:57:43.077568 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4168 09:57:43.080998 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4169 09:57:43.084564 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4170 09:57:43.087660 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4171 09:57:43.093984 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4172 09:57:43.097444 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4173 09:57:43.100592 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4174 09:57:43.104020 iDelay=205, Bit 8, Center 24 (-123 ~ 172) 296
4175 09:57:43.110669 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4176 09:57:43.113912 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4177 09:57:43.117513 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4178 09:57:43.120730 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4179 09:57:43.127194 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4180 09:57:43.130455 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4181 09:57:43.133837 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4182 09:57:43.133918 ==
4183 09:57:43.136996 Dram Type= 6, Freq= 0, CH_0, rank 1
4184 09:57:43.140616 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4185 09:57:43.140698 ==
4186 09:57:43.143572 DQS Delay:
4187 09:57:43.143652 DQS0 = 0, DQS1 = 0
4188 09:57:43.146817 DQM Delay:
4189 09:57:43.146897 DQM0 = 41, DQM1 = 33
4190 09:57:43.146961 DQ Delay:
4191 09:57:43.150549 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
4192 09:57:43.153582 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4193 09:57:43.156795 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4194 09:57:43.160140 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =44
4195 09:57:43.160221
4196 09:57:43.160284
4197 09:57:43.170238 [DQSOSCAuto] RK1, (LSB)MR18= 0x6464, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4198 09:57:43.173558 CH0 RK1: MR19=808, MR18=6464
4199 09:57:43.180246 CH0_RK1: MR19=0x808, MR18=0x6464, DQSOSC=391, MR23=63, INC=171, DEC=114
4200 09:57:43.180354 [RxdqsGatingPostProcess] freq 600
4201 09:57:43.186757 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4202 09:57:43.190033 Pre-setting of DQS Precalculation
4203 09:57:43.193666 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4204 09:57:43.196532 ==
4205 09:57:43.199967 Dram Type= 6, Freq= 0, CH_1, rank 0
4206 09:57:43.203383 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4207 09:57:43.203464 ==
4208 09:57:43.209950 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4209 09:57:43.213112 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4210 09:57:43.217255 [CA 0] Center 35 (5~66) winsize 62
4211 09:57:43.220412 [CA 1] Center 35 (5~66) winsize 62
4212 09:57:43.223815 [CA 2] Center 33 (3~64) winsize 62
4213 09:57:43.226945 [CA 3] Center 33 (3~64) winsize 62
4214 09:57:43.230296 [CA 4] Center 33 (2~64) winsize 63
4215 09:57:43.233550 [CA 5] Center 33 (2~64) winsize 63
4216 09:57:43.233630
4217 09:57:43.236836 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4218 09:57:43.236917
4219 09:57:43.240463 [CATrainingPosCal] consider 1 rank data
4220 09:57:43.243567 u2DelayCellTimex100 = 270/100 ps
4221 09:57:43.247061 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4222 09:57:43.253518 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4223 09:57:43.256860 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4224 09:57:43.260087 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4225 09:57:43.263489 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4226 09:57:43.266723 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4227 09:57:43.266808
4228 09:57:43.269912 CA PerBit enable=1, Macro0, CA PI delay=33
4229 09:57:43.270018
4230 09:57:43.273347 [CBTSetCACLKResult] CA Dly = 33
4231 09:57:43.276447 CS Dly: 4 (0~35)
4232 09:57:43.276585 ==
4233 09:57:43.279838 Dram Type= 6, Freq= 0, CH_1, rank 1
4234 09:57:43.283206 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4235 09:57:43.283288 ==
4236 09:57:43.289945 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4237 09:57:43.293159 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4238 09:57:43.297417 [CA 0] Center 35 (5~65) winsize 61
4239 09:57:43.300405 [CA 1] Center 34 (4~65) winsize 62
4240 09:57:43.303808 [CA 2] Center 33 (3~64) winsize 62
4241 09:57:43.307152 [CA 3] Center 33 (3~64) winsize 62
4242 09:57:43.310428 [CA 4] Center 32 (2~63) winsize 62
4243 09:57:43.313955 [CA 5] Center 32 (2~63) winsize 62
4244 09:57:43.314036
4245 09:57:43.317154 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4246 09:57:43.317234
4247 09:57:43.320219 [CATrainingPosCal] consider 2 rank data
4248 09:57:43.323705 u2DelayCellTimex100 = 270/100 ps
4249 09:57:43.326969 CA0 delay=35 (5~65),Diff = 3 PI (28 cell)
4250 09:57:43.330656 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4251 09:57:43.336862 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4252 09:57:43.340381 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4253 09:57:43.343631 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4254 09:57:43.346913 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4255 09:57:43.346994
4256 09:57:43.350261 CA PerBit enable=1, Macro0, CA PI delay=32
4257 09:57:43.350342
4258 09:57:43.353604 [CBTSetCACLKResult] CA Dly = 32
4259 09:57:43.353684 CS Dly: 4 (0~36)
4260 09:57:43.353748
4261 09:57:43.360263 ----->DramcWriteLeveling(PI) begin...
4262 09:57:43.360345 ==
4263 09:57:43.363388 Dram Type= 6, Freq= 0, CH_1, rank 0
4264 09:57:43.366719 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4265 09:57:43.366800 ==
4266 09:57:43.370187 Write leveling (Byte 0): 27 => 27
4267 09:57:43.373394 Write leveling (Byte 1): 29 => 29
4268 09:57:43.376791 DramcWriteLeveling(PI) end<-----
4269 09:57:43.376897
4270 09:57:43.376994 ==
4271 09:57:43.380002 Dram Type= 6, Freq= 0, CH_1, rank 0
4272 09:57:43.386496 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4273 09:57:43.386581 ==
4274 09:57:43.386839 [Gating] SW mode calibration
4275 09:57:43.393487 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4276 09:57:43.400063 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4277 09:57:43.403347 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4278 09:57:43.407167 0 5 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
4279 09:57:43.413274 0 5 8 | B1->B0 | 3030 2929 | 0 0 | (0 1) (1 1)
4280 09:57:43.416712 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4281 09:57:43.420180 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4282 09:57:43.423247 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4283 09:57:43.430075 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4284 09:57:43.433506 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4285 09:57:43.436984 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4286 09:57:43.443232 0 6 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
4287 09:57:43.446565 0 6 8 | B1->B0 | 3737 3c3c | 1 0 | (0 0) (0 0)
4288 09:57:43.449983 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4289 09:57:43.456419 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4290 09:57:43.459768 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4291 09:57:43.463199 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4292 09:57:43.469903 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4293 09:57:43.473133 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4294 09:57:43.476754 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4295 09:57:43.482966 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4296 09:57:43.486372 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4297 09:57:43.490046 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4298 09:57:43.496252 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4299 09:57:43.499753 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4300 09:57:43.502941 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4301 09:57:43.509580 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4302 09:57:43.513072 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4303 09:57:43.516393 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4304 09:57:43.522956 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4305 09:57:43.526133 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4306 09:57:43.529407 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4307 09:57:43.536139 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4308 09:57:43.539594 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4309 09:57:43.542643 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4310 09:57:43.549231 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4311 09:57:43.552750 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4312 09:57:43.556133 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4313 09:57:43.559355 Total UI for P1: 0, mck2ui 16
4314 09:57:43.562631 best dqsien dly found for B0: ( 0, 9, 8)
4315 09:57:43.565871 Total UI for P1: 0, mck2ui 16
4316 09:57:43.569081 best dqsien dly found for B1: ( 0, 9, 10)
4317 09:57:43.572542 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4318 09:57:43.575672 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4319 09:57:43.575756
4320 09:57:43.579241 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4321 09:57:43.585514 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4322 09:57:43.585600 [Gating] SW calibration Done
4323 09:57:43.588880 ==
4324 09:57:43.588964 Dram Type= 6, Freq= 0, CH_1, rank 0
4325 09:57:43.595484 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4326 09:57:43.595569 ==
4327 09:57:43.595656 RX Vref Scan: 0
4328 09:57:43.595739
4329 09:57:43.598755 RX Vref 0 -> 0, step: 1
4330 09:57:43.598839
4331 09:57:43.602046 RX Delay -230 -> 252, step: 16
4332 09:57:43.605423 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4333 09:57:43.609015 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4334 09:57:43.615499 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4335 09:57:43.618564 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4336 09:57:43.622063 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4337 09:57:43.625253 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4338 09:57:43.631707 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4339 09:57:43.635320 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4340 09:57:43.638870 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4341 09:57:43.642001 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4342 09:57:43.645139 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4343 09:57:43.651673 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4344 09:57:43.655167 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4345 09:57:43.658281 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4346 09:57:43.661736 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4347 09:57:43.668114 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4348 09:57:43.668195 ==
4349 09:57:43.671420 Dram Type= 6, Freq= 0, CH_1, rank 0
4350 09:57:43.674786 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4351 09:57:43.674869 ==
4352 09:57:43.674934 DQS Delay:
4353 09:57:43.678065 DQS0 = 0, DQS1 = 0
4354 09:57:43.678145 DQM Delay:
4355 09:57:43.681406 DQM0 = 39, DQM1 = 32
4356 09:57:43.681486 DQ Delay:
4357 09:57:43.684768 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4358 09:57:43.688107 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4359 09:57:43.691700 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4360 09:57:43.694910 DQ12 =41, DQ13 =49, DQ14 =33, DQ15 =49
4361 09:57:43.694990
4362 09:57:43.695053
4363 09:57:43.695111 ==
4364 09:57:43.698431 Dram Type= 6, Freq= 0, CH_1, rank 0
4365 09:57:43.701341 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4366 09:57:43.704795 ==
4367 09:57:43.704875
4368 09:57:43.704938
4369 09:57:43.704996 TX Vref Scan disable
4370 09:57:43.708271 == TX Byte 0 ==
4371 09:57:43.711300 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4372 09:57:43.714871 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4373 09:57:43.718010 == TX Byte 1 ==
4374 09:57:43.721451 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4375 09:57:43.724770 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4376 09:57:43.728052 ==
4377 09:57:43.730958 Dram Type= 6, Freq= 0, CH_1, rank 0
4378 09:57:43.734389 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4379 09:57:43.734470 ==
4380 09:57:43.734534
4381 09:57:43.734597
4382 09:57:43.737550 TX Vref Scan disable
4383 09:57:43.740989 == TX Byte 0 ==
4384 09:57:43.744516 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4385 09:57:43.747582 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4386 09:57:43.750887 == TX Byte 1 ==
4387 09:57:43.754168 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4388 09:57:43.757361 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4389 09:57:43.757441
4390 09:57:43.757505 [DATLAT]
4391 09:57:43.761006 Freq=600, CH1 RK0
4392 09:57:43.761086
4393 09:57:43.763975 DATLAT Default: 0x9
4394 09:57:43.764056 0, 0xFFFF, sum = 0
4395 09:57:43.767253 1, 0xFFFF, sum = 0
4396 09:57:43.767335 2, 0xFFFF, sum = 0
4397 09:57:43.770655 3, 0xFFFF, sum = 0
4398 09:57:43.770763 4, 0xFFFF, sum = 0
4399 09:57:43.773773 5, 0xFFFF, sum = 0
4400 09:57:43.773855 6, 0xFFFF, sum = 0
4401 09:57:43.777251 7, 0x0, sum = 1
4402 09:57:43.777332 8, 0x0, sum = 2
4403 09:57:43.780618 9, 0x0, sum = 3
4404 09:57:43.780699 10, 0x0, sum = 4
4405 09:57:43.780764 best_step = 8
4406 09:57:43.780823
4407 09:57:43.783836 ==
4408 09:57:43.787391 Dram Type= 6, Freq= 0, CH_1, rank 0
4409 09:57:43.790660 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4410 09:57:43.790742 ==
4411 09:57:43.790806 RX Vref Scan: 1
4412 09:57:43.790866
4413 09:57:43.793750 RX Vref 0 -> 0, step: 1
4414 09:57:43.793830
4415 09:57:43.797178 RX Delay -195 -> 252, step: 8
4416 09:57:43.797259
4417 09:57:43.800439 Set Vref, RX VrefLevel [Byte0]: 53
4418 09:57:43.803640 [Byte1]: 49
4419 09:57:43.803724
4420 09:57:43.807037 Final RX Vref Byte 0 = 53 to rank0
4421 09:57:43.810430 Final RX Vref Byte 1 = 49 to rank0
4422 09:57:43.813538 Final RX Vref Byte 0 = 53 to rank1
4423 09:57:43.816992 Final RX Vref Byte 1 = 49 to rank1==
4424 09:57:43.820215 Dram Type= 6, Freq= 0, CH_1, rank 0
4425 09:57:43.823721 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4426 09:57:43.826857 ==
4427 09:57:43.826945 DQS Delay:
4428 09:57:43.827010 DQS0 = 0, DQS1 = 0
4429 09:57:43.830064 DQM Delay:
4430 09:57:43.830144 DQM0 = 37, DQM1 = 31
4431 09:57:43.833324 DQ Delay:
4432 09:57:43.833404 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4433 09:57:43.837039 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4434 09:57:43.840049 DQ8 =12, DQ9 =20, DQ10 =36, DQ11 =24
4435 09:57:43.843417 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4436 09:57:43.843497
4437 09:57:43.847165
4438 09:57:43.853670 [DQSOSCAuto] RK0, (LSB)MR18= 0x7373, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
4439 09:57:43.856936 CH1 RK0: MR19=808, MR18=7373
4440 09:57:43.863429 CH1_RK0: MR19=0x808, MR18=0x7373, DQSOSC=388, MR23=63, INC=174, DEC=116
4441 09:57:43.863510
4442 09:57:43.866639 ----->DramcWriteLeveling(PI) begin...
4443 09:57:43.866721 ==
4444 09:57:43.869964 Dram Type= 6, Freq= 0, CH_1, rank 1
4445 09:57:43.873250 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4446 09:57:43.873332 ==
4447 09:57:43.876492 Write leveling (Byte 0): 30 => 30
4448 09:57:43.879937 Write leveling (Byte 1): 29 => 29
4449 09:57:43.883104 DramcWriteLeveling(PI) end<-----
4450 09:57:43.883188
4451 09:57:43.883273 ==
4452 09:57:43.886766 Dram Type= 6, Freq= 0, CH_1, rank 1
4453 09:57:43.890208 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4454 09:57:43.890293 ==
4455 09:57:43.893459 [Gating] SW mode calibration
4456 09:57:43.900090 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4457 09:57:43.906369 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4458 09:57:43.909725 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4459 09:57:43.913084 0 5 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
4460 09:57:43.919613 0 5 8 | B1->B0 | 2f2f 2727 | 0 0 | (0 1) (0 0)
4461 09:57:43.922806 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4462 09:57:43.926244 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4463 09:57:43.932645 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 09:57:43.935871 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 09:57:43.939136 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 09:57:43.945744 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 09:57:43.949074 0 6 4 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)
4468 09:57:43.952900 0 6 8 | B1->B0 | 3737 4646 | 0 0 | (1 1) (0 0)
4469 09:57:43.959061 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 09:57:43.962655 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 09:57:43.965823 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 09:57:43.972079 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 09:57:43.975863 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 09:57:43.978862 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 09:57:43.985556 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 09:57:43.988758 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4477 09:57:43.992244 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 09:57:43.998857 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 09:57:44.001823 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 09:57:44.005366 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 09:57:44.012168 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 09:57:44.015449 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 09:57:44.018589 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 09:57:44.025043 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 09:57:44.028217 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 09:57:44.031965 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 09:57:44.038434 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 09:57:44.041586 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 09:57:44.045198 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 09:57:44.051543 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 09:57:44.054788 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 09:57:44.058660 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 09:57:44.061542 Total UI for P1: 0, mck2ui 16
4494 09:57:44.064936 best dqsien dly found for B0: ( 0, 9, 6)
4495 09:57:44.068018 Total UI for P1: 0, mck2ui 16
4496 09:57:44.071505 best dqsien dly found for B1: ( 0, 9, 6)
4497 09:57:44.074753 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4498 09:57:44.077935 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4499 09:57:44.078016
4500 09:57:44.084808 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4501 09:57:44.087966 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4502 09:57:44.088046 [Gating] SW calibration Done
4503 09:57:44.091256 ==
4504 09:57:44.094589 Dram Type= 6, Freq= 0, CH_1, rank 1
4505 09:57:44.097872 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4506 09:57:44.097953 ==
4507 09:57:44.098017 RX Vref Scan: 0
4508 09:57:44.098077
4509 09:57:44.101136 RX Vref 0 -> 0, step: 1
4510 09:57:44.101217
4511 09:57:44.104633 RX Delay -230 -> 252, step: 16
4512 09:57:44.107854 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4513 09:57:44.111164 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4514 09:57:44.117759 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4515 09:57:44.121053 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4516 09:57:44.124472 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4517 09:57:44.127590 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4518 09:57:44.134023 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4519 09:57:44.137534 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4520 09:57:44.140750 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4521 09:57:44.144194 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4522 09:57:44.151132 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4523 09:57:44.154186 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4524 09:57:44.157628 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4525 09:57:44.160458 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4526 09:57:44.167334 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4527 09:57:44.170788 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4528 09:57:44.170869 ==
4529 09:57:44.173711 Dram Type= 6, Freq= 0, CH_1, rank 1
4530 09:57:44.177418 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4531 09:57:44.177500 ==
4532 09:57:44.177565 DQS Delay:
4533 09:57:44.180458 DQS0 = 0, DQS1 = 0
4534 09:57:44.180593 DQM Delay:
4535 09:57:44.183780 DQM0 = 40, DQM1 = 34
4536 09:57:44.183861 DQ Delay:
4537 09:57:44.187006 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41
4538 09:57:44.190496 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4539 09:57:44.193724 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4540 09:57:44.196836 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4541 09:57:44.196918
4542 09:57:44.196982
4543 09:57:44.197040 ==
4544 09:57:44.200703 Dram Type= 6, Freq= 0, CH_1, rank 1
4545 09:57:44.206896 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4546 09:57:44.206981 ==
4547 09:57:44.207067
4548 09:57:44.207149
4549 09:57:44.207228 TX Vref Scan disable
4550 09:57:44.210384 == TX Byte 0 ==
4551 09:57:44.213797 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4552 09:57:44.220254 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4553 09:57:44.220339 == TX Byte 1 ==
4554 09:57:44.223997 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4555 09:57:44.230168 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4556 09:57:44.230252 ==
4557 09:57:44.233374 Dram Type= 6, Freq= 0, CH_1, rank 1
4558 09:57:44.236862 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4559 09:57:44.236947 ==
4560 09:57:44.237033
4561 09:57:44.237113
4562 09:57:44.240148 TX Vref Scan disable
4563 09:57:44.243429 == TX Byte 0 ==
4564 09:57:44.247094 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4565 09:57:44.250194 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4566 09:57:44.253346 == TX Byte 1 ==
4567 09:57:44.256764 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4568 09:57:44.259793 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4569 09:57:44.259878
4570 09:57:44.259963 [DATLAT]
4571 09:57:44.263288 Freq=600, CH1 RK1
4572 09:57:44.263373
4573 09:57:44.266598 DATLAT Default: 0x8
4574 09:57:44.266682 0, 0xFFFF, sum = 0
4575 09:57:44.269803 1, 0xFFFF, sum = 0
4576 09:57:44.269889 2, 0xFFFF, sum = 0
4577 09:57:44.273127 3, 0xFFFF, sum = 0
4578 09:57:44.273246 4, 0xFFFF, sum = 0
4579 09:57:44.276337 5, 0xFFFF, sum = 0
4580 09:57:44.276447 6, 0xFFFF, sum = 0
4581 09:57:44.279847 7, 0x0, sum = 1
4582 09:57:44.279929 8, 0x0, sum = 2
4583 09:57:44.283063 9, 0x0, sum = 3
4584 09:57:44.283146 10, 0x0, sum = 4
4585 09:57:44.283213 best_step = 8
4586 09:57:44.283278
4587 09:57:44.286372 ==
4588 09:57:44.286454 Dram Type= 6, Freq= 0, CH_1, rank 1
4589 09:57:44.292845 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4590 09:57:44.292931 ==
4591 09:57:44.293017 RX Vref Scan: 0
4592 09:57:44.293098
4593 09:57:44.296216 RX Vref 0 -> 0, step: 1
4594 09:57:44.296300
4595 09:57:44.299646 RX Delay -195 -> 252, step: 8
4596 09:57:44.306316 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4597 09:57:44.309573 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4598 09:57:44.313016 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4599 09:57:44.316053 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4600 09:57:44.319271 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4601 09:57:44.325916 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4602 09:57:44.329292 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4603 09:57:44.332870 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4604 09:57:44.336020 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4605 09:57:44.342510 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4606 09:57:44.346113 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4607 09:57:44.349251 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4608 09:57:44.352488 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4609 09:57:44.359202 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4610 09:57:44.362384 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4611 09:57:44.365984 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4612 09:57:44.366069 ==
4613 09:57:44.369545 Dram Type= 6, Freq= 0, CH_1, rank 1
4614 09:57:44.372348 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4615 09:57:44.372436 ==
4616 09:57:44.375662 DQS Delay:
4617 09:57:44.375743 DQS0 = 0, DQS1 = 0
4618 09:57:44.379339 DQM Delay:
4619 09:57:44.379419 DQM0 = 37, DQM1 = 29
4620 09:57:44.379490 DQ Delay:
4621 09:57:44.382766 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4622 09:57:44.385916 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4623 09:57:44.389158 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4624 09:57:44.392392 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4625 09:57:44.392472
4626 09:57:44.392576
4627 09:57:44.402223 [DQSOSCAuto] RK1, (LSB)MR18= 0x6060, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4628 09:57:44.405400 CH1 RK1: MR19=808, MR18=6060
4629 09:57:44.412328 CH1_RK1: MR19=0x808, MR18=0x6060, DQSOSC=391, MR23=63, INC=171, DEC=114
4630 09:57:44.412436 [RxdqsGatingPostProcess] freq 600
4631 09:57:44.419115 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4632 09:57:44.421980 Pre-setting of DQS Precalculation
4633 09:57:44.428779 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4634 09:57:44.435158 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4635 09:57:44.441701 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4636 09:57:44.441784
4637 09:57:44.441848
4638 09:57:44.445288 [Calibration Summary] 1200 Mbps
4639 09:57:44.445369 CH 0, Rank 0
4640 09:57:44.448742 SW Impedance : PASS
4641 09:57:44.451858 DUTY Scan : NO K
4642 09:57:44.451939 ZQ Calibration : PASS
4643 09:57:44.455384 Jitter Meter : NO K
4644 09:57:44.455465 CBT Training : PASS
4645 09:57:44.458481 Write leveling : PASS
4646 09:57:44.461634 RX DQS gating : PASS
4647 09:57:44.461715 RX DQ/DQS(RDDQC) : PASS
4648 09:57:44.465109 TX DQ/DQS : PASS
4649 09:57:44.468392 RX DATLAT : PASS
4650 09:57:44.468473 RX DQ/DQS(Engine): PASS
4651 09:57:44.471990 TX OE : NO K
4652 09:57:44.472098 All Pass.
4653 09:57:44.472207
4654 09:57:44.475053 CH 0, Rank 1
4655 09:57:44.475134 SW Impedance : PASS
4656 09:57:44.478585 DUTY Scan : NO K
4657 09:57:44.481709 ZQ Calibration : PASS
4658 09:57:44.481790 Jitter Meter : NO K
4659 09:57:44.485075 CBT Training : PASS
4660 09:57:44.488382 Write leveling : PASS
4661 09:57:44.488463 RX DQS gating : PASS
4662 09:57:44.491708 RX DQ/DQS(RDDQC) : PASS
4663 09:57:44.495028 TX DQ/DQS : PASS
4664 09:57:44.495109 RX DATLAT : PASS
4665 09:57:44.498390 RX DQ/DQS(Engine): PASS
4666 09:57:44.501713 TX OE : NO K
4667 09:57:44.501794 All Pass.
4668 09:57:44.501859
4669 09:57:44.501919 CH 1, Rank 0
4670 09:57:44.504958 SW Impedance : PASS
4671 09:57:44.508138 DUTY Scan : NO K
4672 09:57:44.508218 ZQ Calibration : PASS
4673 09:57:44.511655 Jitter Meter : NO K
4674 09:57:44.511736 CBT Training : PASS
4675 09:57:44.514759 Write leveling : PASS
4676 09:57:44.518114 RX DQS gating : PASS
4677 09:57:44.518194 RX DQ/DQS(RDDQC) : PASS
4678 09:57:44.521443 TX DQ/DQS : PASS
4679 09:57:44.524971 RX DATLAT : PASS
4680 09:57:44.525052 RX DQ/DQS(Engine): PASS
4681 09:57:44.528503 TX OE : NO K
4682 09:57:44.528622 All Pass.
4683 09:57:44.528686
4684 09:57:44.531637 CH 1, Rank 1
4685 09:57:44.531717 SW Impedance : PASS
4686 09:57:44.534964 DUTY Scan : NO K
4687 09:57:44.538338 ZQ Calibration : PASS
4688 09:57:44.538424 Jitter Meter : NO K
4689 09:57:44.541382 CBT Training : PASS
4690 09:57:44.544947 Write leveling : PASS
4691 09:57:44.545028 RX DQS gating : PASS
4692 09:57:44.548139 RX DQ/DQS(RDDQC) : PASS
4693 09:57:44.551340 TX DQ/DQS : PASS
4694 09:57:44.551422 RX DATLAT : PASS
4695 09:57:44.554647 RX DQ/DQS(Engine): PASS
4696 09:57:44.554727 TX OE : NO K
4697 09:57:44.557951 All Pass.
4698 09:57:44.558031
4699 09:57:44.558095 DramC Write-DBI off
4700 09:57:44.561178 PER_BANK_REFRESH: Hybrid Mode
4701 09:57:44.564670 TX_TRACKING: ON
4702 09:57:44.571344 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4703 09:57:44.574385 [FAST_K] Save calibration result to emmc
4704 09:57:44.581252 dramc_set_vcore_voltage set vcore to 662500
4705 09:57:44.581333 Read voltage for 933, 3
4706 09:57:44.581398 Vio18 = 0
4707 09:57:44.584489 Vcore = 662500
4708 09:57:44.584609 Vdram = 0
4709 09:57:44.584674 Vddq = 0
4710 09:57:44.587926 Vmddr = 0
4711 09:57:44.591099 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4712 09:57:44.597731 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4713 09:57:44.601258 MEM_TYPE=3, freq_sel=17
4714 09:57:44.601339 sv_algorithm_assistance_LP4_1600
4715 09:57:44.607771 ============ PULL DRAM RESETB DOWN ============
4716 09:57:44.610892 ========== PULL DRAM RESETB DOWN end =========
4717 09:57:44.614439 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4718 09:57:44.617944 ===================================
4719 09:57:44.621062 LPDDR4 DRAM CONFIGURATION
4720 09:57:44.624469 ===================================
4721 09:57:44.627696 EX_ROW_EN[0] = 0x0
4722 09:57:44.627780 EX_ROW_EN[1] = 0x0
4723 09:57:44.630936 LP4Y_EN = 0x0
4724 09:57:44.631017 WORK_FSP = 0x0
4725 09:57:44.634325 WL = 0x3
4726 09:57:44.634405 RL = 0x3
4727 09:57:44.637673 BL = 0x2
4728 09:57:44.637767 RPST = 0x0
4729 09:57:44.640826 RD_PRE = 0x0
4730 09:57:44.640909 WR_PRE = 0x1
4731 09:57:44.644027 WR_PST = 0x0
4732 09:57:44.644108 DBI_WR = 0x0
4733 09:57:44.647375 DBI_RD = 0x0
4734 09:57:44.647457 OTF = 0x1
4735 09:57:44.650885 ===================================
4736 09:57:44.653904 ===================================
4737 09:57:44.657267 ANA top config
4738 09:57:44.660487 ===================================
4739 09:57:44.664102 DLL_ASYNC_EN = 0
4740 09:57:44.664183 ALL_SLAVE_EN = 1
4741 09:57:44.667241 NEW_RANK_MODE = 1
4742 09:57:44.670481 DLL_IDLE_MODE = 1
4743 09:57:44.673771 LP45_APHY_COMB_EN = 1
4744 09:57:44.677091 TX_ODT_DIS = 1
4745 09:57:44.677172 NEW_8X_MODE = 1
4746 09:57:44.680760 ===================================
4747 09:57:44.683857 ===================================
4748 09:57:44.687188 data_rate = 1866
4749 09:57:44.690469 CKR = 1
4750 09:57:44.694004 DQ_P2S_RATIO = 8
4751 09:57:44.697009 ===================================
4752 09:57:44.700490 CA_P2S_RATIO = 8
4753 09:57:44.700581 DQ_CA_OPEN = 0
4754 09:57:44.704056 DQ_SEMI_OPEN = 0
4755 09:57:44.707093 CA_SEMI_OPEN = 0
4756 09:57:44.710450 CA_FULL_RATE = 0
4757 09:57:44.713856 DQ_CKDIV4_EN = 1
4758 09:57:44.717846 CA_CKDIV4_EN = 1
4759 09:57:44.717929 CA_PREDIV_EN = 0
4760 09:57:44.720248 PH8_DLY = 0
4761 09:57:44.723615 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4762 09:57:44.727213 DQ_AAMCK_DIV = 4
4763 09:57:44.730576 CA_AAMCK_DIV = 4
4764 09:57:44.733652 CA_ADMCK_DIV = 4
4765 09:57:44.733736 DQ_TRACK_CA_EN = 0
4766 09:57:44.737014 CA_PICK = 933
4767 09:57:44.740174 CA_MCKIO = 933
4768 09:57:44.743579 MCKIO_SEMI = 0
4769 09:57:44.746819 PLL_FREQ = 3732
4770 09:57:44.750049 DQ_UI_PI_RATIO = 32
4771 09:57:44.753404 CA_UI_PI_RATIO = 0
4772 09:57:44.756726 ===================================
4773 09:57:44.759954 ===================================
4774 09:57:44.760038 memory_type:LPDDR4
4775 09:57:44.763544 GP_NUM : 10
4776 09:57:44.766701 SRAM_EN : 1
4777 09:57:44.766784 MD32_EN : 0
4778 09:57:44.770058 ===================================
4779 09:57:44.773464 [ANA_INIT] >>>>>>>>>>>>>>
4780 09:57:44.776727 <<<<<< [CONFIGURE PHASE]: ANA_TX
4781 09:57:44.779965 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4782 09:57:44.783664 ===================================
4783 09:57:44.786833 data_rate = 1866,PCW = 0X8f00
4784 09:57:44.789909 ===================================
4785 09:57:44.793236 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4786 09:57:44.796530 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4787 09:57:44.803411 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4788 09:57:44.806501 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4789 09:57:44.809644 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4790 09:57:44.816497 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4791 09:57:44.816619 [ANA_INIT] flow start
4792 09:57:44.819684 [ANA_INIT] PLL >>>>>>>>
4793 09:57:44.819784 [ANA_INIT] PLL <<<<<<<<
4794 09:57:44.822919 [ANA_INIT] MIDPI >>>>>>>>
4795 09:57:44.826450 [ANA_INIT] MIDPI <<<<<<<<
4796 09:57:44.829608 [ANA_INIT] DLL >>>>>>>>
4797 09:57:44.829681 [ANA_INIT] flow end
4798 09:57:44.832933 ============ LP4 DIFF to SE enter ============
4799 09:57:44.839782 ============ LP4 DIFF to SE exit ============
4800 09:57:44.839875 [ANA_INIT] <<<<<<<<<<<<<
4801 09:57:44.843079 [Flow] Enable top DCM control >>>>>
4802 09:57:44.846480 [Flow] Enable top DCM control <<<<<
4803 09:57:44.849483 Enable DLL master slave shuffle
4804 09:57:44.856014 ==============================================================
4805 09:57:44.856118 Gating Mode config
4806 09:57:44.862658 ==============================================================
4807 09:57:44.865865 Config description:
4808 09:57:44.875885 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4809 09:57:44.882531 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4810 09:57:44.885959 SELPH_MODE 0: By rank 1: By Phase
4811 09:57:44.892771 ==============================================================
4812 09:57:44.895719 GAT_TRACK_EN = 1
4813 09:57:44.899181 RX_GATING_MODE = 2
4814 09:57:44.899282 RX_GATING_TRACK_MODE = 2
4815 09:57:44.902794 SELPH_MODE = 1
4816 09:57:44.905821 PICG_EARLY_EN = 1
4817 09:57:44.909057 VALID_LAT_VALUE = 1
4818 09:57:44.915691 ==============================================================
4819 09:57:44.919398 Enter into Gating configuration >>>>
4820 09:57:44.922681 Exit from Gating configuration <<<<
4821 09:57:44.925543 Enter into DVFS_PRE_config >>>>>
4822 09:57:44.936024 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4823 09:57:44.938932 Exit from DVFS_PRE_config <<<<<
4824 09:57:44.942373 Enter into PICG configuration >>>>
4825 09:57:44.945585 Exit from PICG configuration <<<<
4826 09:57:44.949048 [RX_INPUT] configuration >>>>>
4827 09:57:44.952245 [RX_INPUT] configuration <<<<<
4828 09:57:44.955736 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4829 09:57:44.962003 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4830 09:57:44.968775 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4831 09:57:44.975342 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4832 09:57:44.978734 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4833 09:57:44.985307 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4834 09:57:44.991753 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4835 09:57:44.995104 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4836 09:57:44.998424 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4837 09:57:45.001849 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4838 09:57:45.005518 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4839 09:57:45.011558 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4840 09:57:45.015083 ===================================
4841 09:57:45.018306 LPDDR4 DRAM CONFIGURATION
4842 09:57:45.021626 ===================================
4843 09:57:45.021708 EX_ROW_EN[0] = 0x0
4844 09:57:45.025143 EX_ROW_EN[1] = 0x0
4845 09:57:45.025224 LP4Y_EN = 0x0
4846 09:57:45.028164 WORK_FSP = 0x0
4847 09:57:45.028246 WL = 0x3
4848 09:57:45.031589 RL = 0x3
4849 09:57:45.031670 BL = 0x2
4850 09:57:45.034777 RPST = 0x0
4851 09:57:45.034858 RD_PRE = 0x0
4852 09:57:45.038143 WR_PRE = 0x1
4853 09:57:45.038224 WR_PST = 0x0
4854 09:57:45.041482 DBI_WR = 0x0
4855 09:57:45.041593 DBI_RD = 0x0
4856 09:57:45.044921 OTF = 0x1
4857 09:57:45.048244 ===================================
4858 09:57:45.051593 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4859 09:57:45.054946 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4860 09:57:45.061406 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4861 09:57:45.064636 ===================================
4862 09:57:45.068157 LPDDR4 DRAM CONFIGURATION
4863 09:57:45.068256 ===================================
4864 09:57:45.071547 EX_ROW_EN[0] = 0x10
4865 09:57:45.074708 EX_ROW_EN[1] = 0x0
4866 09:57:45.074786 LP4Y_EN = 0x0
4867 09:57:45.077838 WORK_FSP = 0x0
4868 09:57:45.077912 WL = 0x3
4869 09:57:45.081362 RL = 0x3
4870 09:57:45.081461 BL = 0x2
4871 09:57:45.084497 RPST = 0x0
4872 09:57:45.084595 RD_PRE = 0x0
4873 09:57:45.087790 WR_PRE = 0x1
4874 09:57:45.087887 WR_PST = 0x0
4875 09:57:45.091184 DBI_WR = 0x0
4876 09:57:45.091264 DBI_RD = 0x0
4877 09:57:45.094494 OTF = 0x1
4878 09:57:45.097910 ===================================
4879 09:57:45.104435 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4880 09:57:45.107699 nWR fixed to 30
4881 09:57:45.111473 [ModeRegInit_LP4] CH0 RK0
4882 09:57:45.111574 [ModeRegInit_LP4] CH0 RK1
4883 09:57:45.114345 [ModeRegInit_LP4] CH1 RK0
4884 09:57:45.117741 [ModeRegInit_LP4] CH1 RK1
4885 09:57:45.117811 match AC timing 8
4886 09:57:45.124402 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4887 09:57:45.127407 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4888 09:57:45.130782 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4889 09:57:45.137462 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4890 09:57:45.140809 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4891 09:57:45.140899 ==
4892 09:57:45.144133 Dram Type= 6, Freq= 0, CH_0, rank 0
4893 09:57:45.147776 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4894 09:57:45.147876 ==
4895 09:57:45.154021 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4896 09:57:45.160742 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4897 09:57:45.164660 [CA 0] Center 38 (8~69) winsize 62
4898 09:57:45.167643 [CA 1] Center 38 (8~69) winsize 62
4899 09:57:45.170938 [CA 2] Center 36 (6~67) winsize 62
4900 09:57:45.174137 [CA 3] Center 35 (5~66) winsize 62
4901 09:57:45.177243 [CA 4] Center 34 (4~65) winsize 62
4902 09:57:45.180440 [CA 5] Center 34 (4~65) winsize 62
4903 09:57:45.180574
4904 09:57:45.184141 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4905 09:57:45.184246
4906 09:57:45.187324 [CATrainingPosCal] consider 1 rank data
4907 09:57:45.190755 u2DelayCellTimex100 = 270/100 ps
4908 09:57:45.193998 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4909 09:57:45.197157 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4910 09:57:45.200624 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4911 09:57:45.203787 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4912 09:57:45.206927 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4913 09:57:45.210428 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4914 09:57:45.214131
4915 09:57:45.217096 CA PerBit enable=1, Macro0, CA PI delay=34
4916 09:57:45.217169
4917 09:57:45.220266 [CBTSetCACLKResult] CA Dly = 34
4918 09:57:45.220363 CS Dly: 7 (0~38)
4919 09:57:45.220452 ==
4920 09:57:45.223659 Dram Type= 6, Freq= 0, CH_0, rank 1
4921 09:57:45.227149 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4922 09:57:45.227250 ==
4923 09:57:45.233685 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4924 09:57:45.240295 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4925 09:57:45.243830 [CA 0] Center 38 (8~69) winsize 62
4926 09:57:45.247123 [CA 1] Center 38 (7~69) winsize 63
4927 09:57:45.250416 [CA 2] Center 36 (5~67) winsize 63
4928 09:57:45.253739 [CA 3] Center 35 (5~66) winsize 62
4929 09:57:45.257042 [CA 4] Center 34 (4~64) winsize 61
4930 09:57:45.260461 [CA 5] Center 34 (4~65) winsize 62
4931 09:57:45.260572
4932 09:57:45.263792 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4933 09:57:45.263889
4934 09:57:45.266798 [CATrainingPosCal] consider 2 rank data
4935 09:57:45.270591 u2DelayCellTimex100 = 270/100 ps
4936 09:57:45.273363 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4937 09:57:45.276690 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4938 09:57:45.280302 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4939 09:57:45.283376 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4940 09:57:45.290154 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
4941 09:57:45.293431 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4942 09:57:45.293539
4943 09:57:45.296919 CA PerBit enable=1, Macro0, CA PI delay=34
4944 09:57:45.296994
4945 09:57:45.300197 [CBTSetCACLKResult] CA Dly = 34
4946 09:57:45.300294 CS Dly: 7 (0~38)
4947 09:57:45.300382
4948 09:57:45.303420 ----->DramcWriteLeveling(PI) begin...
4949 09:57:45.303495 ==
4950 09:57:45.307022 Dram Type= 6, Freq= 0, CH_0, rank 0
4951 09:57:45.313320 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4952 09:57:45.313411 ==
4953 09:57:45.316804 Write leveling (Byte 0): 26 => 26
4954 09:57:45.316903 Write leveling (Byte 1): 26 => 26
4955 09:57:45.319878 DramcWriteLeveling(PI) end<-----
4956 09:57:45.319952
4957 09:57:45.323344 ==
4958 09:57:45.323421 Dram Type= 6, Freq= 0, CH_0, rank 0
4959 09:57:45.330029 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4960 09:57:45.330117 ==
4961 09:57:45.333187 [Gating] SW mode calibration
4962 09:57:45.339793 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4963 09:57:45.343175 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4964 09:57:45.349704 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4965 09:57:45.353197 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4966 09:57:45.356342 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4967 09:57:45.363001 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4968 09:57:45.366519 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4969 09:57:45.369878 0 10 20 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
4970 09:57:45.376248 0 10 24 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
4971 09:57:45.379609 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4972 09:57:45.382894 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4973 09:57:45.389442 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4974 09:57:45.392844 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4975 09:57:45.396216 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4976 09:57:45.402833 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4977 09:57:45.406058 0 11 20 | B1->B0 | 2626 3030 | 0 0 | (0 0) (0 0)
4978 09:57:45.409627 0 11 24 | B1->B0 | 3b3b 4343 | 0 0 | (0 0) (0 0)
4979 09:57:45.416250 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4980 09:57:45.419372 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4981 09:57:45.422810 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4982 09:57:45.426097 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4983 09:57:45.432808 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4984 09:57:45.436030 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4985 09:57:45.439343 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4986 09:57:45.446029 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4987 09:57:45.449202 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4988 09:57:45.452325 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4989 09:57:45.459192 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4990 09:57:45.462353 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4991 09:57:45.465740 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4992 09:57:45.472609 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4993 09:57:45.475541 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4994 09:57:45.478926 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4995 09:57:45.485490 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4996 09:57:45.488815 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4997 09:57:45.492043 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4998 09:57:45.498751 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4999 09:57:45.502254 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5000 09:57:45.505383 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5001 09:57:45.511883 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5002 09:57:45.515199 Total UI for P1: 0, mck2ui 16
5003 09:57:45.518640 best dqsien dly found for B0: ( 0, 14, 18)
5004 09:57:45.522118 Total UI for P1: 0, mck2ui 16
5005 09:57:45.525115 best dqsien dly found for B1: ( 0, 14, 16)
5006 09:57:45.528472 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5007 09:57:45.532355 best DQS1 dly(MCK, UI, PI) = (0, 14, 16)
5008 09:57:45.532437
5009 09:57:45.535158 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5010 09:57:45.538563 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 16)
5011 09:57:45.541609 [Gating] SW calibration Done
5012 09:57:45.541695 ==
5013 09:57:45.545066 Dram Type= 6, Freq= 0, CH_0, rank 0
5014 09:57:45.548450 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5015 09:57:45.548554 ==
5016 09:57:45.551569 RX Vref Scan: 0
5017 09:57:45.551670
5018 09:57:45.554843 RX Vref 0 -> 0, step: 1
5019 09:57:45.554944
5020 09:57:45.555024 RX Delay -80 -> 252, step: 8
5021 09:57:45.561407 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5022 09:57:45.564809 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5023 09:57:45.568472 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5024 09:57:45.571304 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5025 09:57:45.575174 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5026 09:57:45.578063 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5027 09:57:45.584744 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5028 09:57:45.587890 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5029 09:57:45.591312 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5030 09:57:45.594522 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5031 09:57:45.597855 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5032 09:57:45.604484 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5033 09:57:45.607877 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5034 09:57:45.611566 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5035 09:57:45.614530 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5036 09:57:45.617783 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5037 09:57:45.617929 ==
5038 09:57:45.621090 Dram Type= 6, Freq= 0, CH_0, rank 0
5039 09:57:45.627517 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5040 09:57:45.627626 ==
5041 09:57:45.627713 DQS Delay:
5042 09:57:45.631297 DQS0 = 0, DQS1 = 0
5043 09:57:45.631441 DQM Delay:
5044 09:57:45.634448 DQM0 = 96, DQM1 = 84
5045 09:57:45.634548 DQ Delay:
5046 09:57:45.637628 DQ0 =91, DQ1 =95, DQ2 =95, DQ3 =91
5047 09:57:45.640964 DQ4 =99, DQ5 =91, DQ6 =103, DQ7 =103
5048 09:57:45.644343 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =79
5049 09:57:45.647844 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5050 09:57:45.648035
5051 09:57:45.648132
5052 09:57:45.648220 ==
5053 09:57:45.651026 Dram Type= 6, Freq= 0, CH_0, rank 0
5054 09:57:45.654314 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5055 09:57:45.654467 ==
5056 09:57:45.654554
5057 09:57:45.654633
5058 09:57:45.657645 TX Vref Scan disable
5059 09:57:45.660749 == TX Byte 0 ==
5060 09:57:45.664293 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5061 09:57:45.668154 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5062 09:57:45.671484 == TX Byte 1 ==
5063 09:57:45.674465 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5064 09:57:45.678215 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5065 09:57:45.678463 ==
5066 09:57:45.680899 Dram Type= 6, Freq= 0, CH_0, rank 0
5067 09:57:45.684587 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5068 09:57:45.687762 ==
5069 09:57:45.688079
5070 09:57:45.688271
5071 09:57:45.688443 TX Vref Scan disable
5072 09:57:45.691481 == TX Byte 0 ==
5073 09:57:45.694965 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5074 09:57:45.701420 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5075 09:57:45.702130 == TX Byte 1 ==
5076 09:57:45.704763 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5077 09:57:45.711593 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5078 09:57:45.712162
5079 09:57:45.712593 [DATLAT]
5080 09:57:45.712956 Freq=933, CH0 RK0
5081 09:57:45.713296
5082 09:57:45.714699 DATLAT Default: 0xd
5083 09:57:45.715160 0, 0xFFFF, sum = 0
5084 09:57:45.718259 1, 0xFFFF, sum = 0
5085 09:57:45.721271 2, 0xFFFF, sum = 0
5086 09:57:45.721739 3, 0xFFFF, sum = 0
5087 09:57:45.724658 4, 0xFFFF, sum = 0
5088 09:57:45.725255 5, 0xFFFF, sum = 0
5089 09:57:45.727807 6, 0xFFFF, sum = 0
5090 09:57:45.728277 7, 0xFFFF, sum = 0
5091 09:57:45.731045 8, 0xFFFF, sum = 0
5092 09:57:45.731514 9, 0xFFFF, sum = 0
5093 09:57:45.734538 10, 0x0, sum = 1
5094 09:57:45.735010 11, 0x0, sum = 2
5095 09:57:45.737871 12, 0x0, sum = 3
5096 09:57:45.738444 13, 0x0, sum = 4
5097 09:57:45.738818 best_step = 11
5098 09:57:45.740877
5099 09:57:45.741357 ==
5100 09:57:45.744058 Dram Type= 6, Freq= 0, CH_0, rank 0
5101 09:57:45.748062 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5102 09:57:45.748742 ==
5103 09:57:45.749133 RX Vref Scan: 1
5104 09:57:45.749529
5105 09:57:45.750763 RX Vref 0 -> 0, step: 1
5106 09:57:45.751225
5107 09:57:45.754064 RX Delay -69 -> 252, step: 4
5108 09:57:45.754532
5109 09:57:45.757743 Set Vref, RX VrefLevel [Byte0]: 46
5110 09:57:45.761191 [Byte1]: 49
5111 09:57:45.764375
5112 09:57:45.765140 Final RX Vref Byte 0 = 46 to rank0
5113 09:57:45.767688 Final RX Vref Byte 1 = 49 to rank0
5114 09:57:45.770859 Final RX Vref Byte 0 = 46 to rank1
5115 09:57:45.773986 Final RX Vref Byte 1 = 49 to rank1==
5116 09:57:45.777271 Dram Type= 6, Freq= 0, CH_0, rank 0
5117 09:57:45.784247 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5118 09:57:45.784863 ==
5119 09:57:45.785243 DQS Delay:
5120 09:57:45.787677 DQS0 = 0, DQS1 = 0
5121 09:57:45.788237 DQM Delay:
5122 09:57:45.788675 DQM0 = 97, DQM1 = 87
5123 09:57:45.790918 DQ Delay:
5124 09:57:45.794049 DQ0 =94, DQ1 =100, DQ2 =94, DQ3 =94
5125 09:57:45.797152 DQ4 =100, DQ5 =86, DQ6 =104, DQ7 =104
5126 09:57:45.801201 DQ8 =78, DQ9 =72, DQ10 =86, DQ11 =78
5127 09:57:45.803755 DQ12 =94, DQ13 =94, DQ14 =98, DQ15 =98
5128 09:57:45.804218
5129 09:57:45.804641
5130 09:57:45.810672 [DQSOSCAuto] RK0, (LSB)MR18= 0x2424, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5131 09:57:45.814108 CH0 RK0: MR19=505, MR18=2424
5132 09:57:45.820398 CH0_RK0: MR19=0x505, MR18=0x2424, DQSOSC=410, MR23=63, INC=64, DEC=42
5133 09:57:45.821022
5134 09:57:45.824090 ----->DramcWriteLeveling(PI) begin...
5135 09:57:45.824709 ==
5136 09:57:45.827519 Dram Type= 6, Freq= 0, CH_0, rank 1
5137 09:57:45.830781 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5138 09:57:45.831253 ==
5139 09:57:45.833946 Write leveling (Byte 0): 31 => 31
5140 09:57:45.837217 Write leveling (Byte 1): 25 => 25
5141 09:57:45.840225 DramcWriteLeveling(PI) end<-----
5142 09:57:45.840711
5143 09:57:45.841078 ==
5144 09:57:45.843675 Dram Type= 6, Freq= 0, CH_0, rank 1
5145 09:57:45.847380 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5146 09:57:45.847950 ==
5147 09:57:45.850324 [Gating] SW mode calibration
5148 09:57:45.856855 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5149 09:57:45.863760 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5150 09:57:45.866916 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5151 09:57:45.873428 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5152 09:57:45.876767 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 09:57:45.879971 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5154 09:57:45.886784 0 10 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5155 09:57:45.890069 0 10 20 | B1->B0 | 3232 2f2f | 1 0 | (1 0) (0 1)
5156 09:57:45.893531 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5157 09:57:45.900336 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5158 09:57:45.903343 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5159 09:57:45.906987 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5160 09:57:45.913426 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 09:57:45.916683 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 09:57:45.919916 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5163 09:57:45.926930 0 11 20 | B1->B0 | 3030 3f3f | 1 0 | (0 0) (1 1)
5164 09:57:45.930133 0 11 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5165 09:57:45.933015 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5166 09:57:45.939608 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5167 09:57:45.943104 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 09:57:45.946264 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 09:57:45.953383 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 09:57:45.956418 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 09:57:45.959544 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5172 09:57:45.962706 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5173 09:57:45.969511 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 09:57:45.973212 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 09:57:45.976261 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 09:57:45.982899 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 09:57:45.985902 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 09:57:45.989464 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 09:57:45.996033 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 09:57:45.999434 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 09:57:46.002664 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 09:57:46.009379 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 09:57:46.012966 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 09:57:46.016137 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 09:57:46.022409 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 09:57:46.025888 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 09:57:46.028972 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5188 09:57:46.032825 Total UI for P1: 0, mck2ui 16
5189 09:57:46.036109 best dqsien dly found for B0: ( 0, 14, 18)
5190 09:57:46.042335 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 09:57:46.042880 Total UI for P1: 0, mck2ui 16
5192 09:57:46.049087 best dqsien dly found for B1: ( 0, 14, 20)
5193 09:57:46.052385 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5194 09:57:46.055789 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5195 09:57:46.056253
5196 09:57:46.059029 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5197 09:57:46.062427 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5198 09:57:46.065693 [Gating] SW calibration Done
5199 09:57:46.066163 ==
5200 09:57:46.069169 Dram Type= 6, Freq= 0, CH_0, rank 1
5201 09:57:46.072199 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5202 09:57:46.072821 ==
5203 09:57:46.075696 RX Vref Scan: 0
5204 09:57:46.076284
5205 09:57:46.076846 RX Vref 0 -> 0, step: 1
5206 09:57:46.078587
5207 09:57:46.079084 RX Delay -80 -> 252, step: 8
5208 09:57:46.085241 iDelay=200, Bit 0, Center 91 (-8 ~ 191) 200
5209 09:57:46.088933 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5210 09:57:46.092084 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5211 09:57:46.095542 iDelay=200, Bit 3, Center 91 (0 ~ 183) 184
5212 09:57:46.098750 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5213 09:57:46.102043 iDelay=200, Bit 5, Center 87 (-16 ~ 191) 208
5214 09:57:46.108690 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5215 09:57:46.112053 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5216 09:57:46.115572 iDelay=200, Bit 8, Center 71 (-24 ~ 167) 192
5217 09:57:46.118714 iDelay=200, Bit 9, Center 71 (-24 ~ 167) 192
5218 09:57:46.121996 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5219 09:57:46.128876 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5220 09:57:46.131702 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5221 09:57:46.135408 iDelay=200, Bit 13, Center 91 (-8 ~ 191) 200
5222 09:57:46.138321 iDelay=200, Bit 14, Center 91 (-8 ~ 191) 200
5223 09:57:46.141565 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5224 09:57:46.142047 ==
5225 09:57:46.144976 Dram Type= 6, Freq= 0, CH_0, rank 1
5226 09:57:46.151531 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5227 09:57:46.152087 ==
5228 09:57:46.152461 DQS Delay:
5229 09:57:46.155503 DQS0 = 0, DQS1 = 0
5230 09:57:46.156060 DQM Delay:
5231 09:57:46.156431 DQM0 = 96, DQM1 = 85
5232 09:57:46.158334 DQ Delay:
5233 09:57:46.161632 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =91
5234 09:57:46.164965 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5235 09:57:46.168670 DQ8 =71, DQ9 =71, DQ10 =87, DQ11 =79
5236 09:57:46.171567 DQ12 =95, DQ13 =91, DQ14 =91, DQ15 =95
5237 09:57:46.172123
5238 09:57:46.172491
5239 09:57:46.172890 ==
5240 09:57:46.174977 Dram Type= 6, Freq= 0, CH_0, rank 1
5241 09:57:46.178271 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5242 09:57:46.178772 ==
5243 09:57:46.179147
5244 09:57:46.179491
5245 09:57:46.181632 TX Vref Scan disable
5246 09:57:46.182092 == TX Byte 0 ==
5247 09:57:46.188068 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5248 09:57:46.191344 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5249 09:57:46.194666 == TX Byte 1 ==
5250 09:57:46.198091 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5251 09:57:46.201433 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5252 09:57:46.201941 ==
5253 09:57:46.204477 Dram Type= 6, Freq= 0, CH_0, rank 1
5254 09:57:46.207734 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5255 09:57:46.208259 ==
5256 09:57:46.211381
5257 09:57:46.211925
5258 09:57:46.212294 TX Vref Scan disable
5259 09:57:46.214916 == TX Byte 0 ==
5260 09:57:46.217999 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5261 09:57:46.221496 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5262 09:57:46.224727 == TX Byte 1 ==
5263 09:57:46.227927 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5264 09:57:46.234694 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5265 09:57:46.235256
5266 09:57:46.235622 [DATLAT]
5267 09:57:46.235961 Freq=933, CH0 RK1
5268 09:57:46.236290
5269 09:57:46.238086 DATLAT Default: 0xb
5270 09:57:46.238640 0, 0xFFFF, sum = 0
5271 09:57:46.241140 1, 0xFFFF, sum = 0
5272 09:57:46.244267 2, 0xFFFF, sum = 0
5273 09:57:46.244886 3, 0xFFFF, sum = 0
5274 09:57:46.247727 4, 0xFFFF, sum = 0
5275 09:57:46.248289 5, 0xFFFF, sum = 0
5276 09:57:46.251285 6, 0xFFFF, sum = 0
5277 09:57:46.251850 7, 0xFFFF, sum = 0
5278 09:57:46.254486 8, 0xFFFF, sum = 0
5279 09:57:46.255056 9, 0xFFFF, sum = 0
5280 09:57:46.257689 10, 0x0, sum = 1
5281 09:57:46.258255 11, 0x0, sum = 2
5282 09:57:46.261107 12, 0x0, sum = 3
5283 09:57:46.261670 13, 0x0, sum = 4
5284 09:57:46.262047 best_step = 11
5285 09:57:46.264582
5286 09:57:46.265160 ==
5287 09:57:46.267471 Dram Type= 6, Freq= 0, CH_0, rank 1
5288 09:57:46.270995 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5289 09:57:46.271567 ==
5290 09:57:46.271948 RX Vref Scan: 0
5291 09:57:46.272289
5292 09:57:46.273833 RX Vref 0 -> 0, step: 1
5293 09:57:46.274291
5294 09:57:46.277323 RX Delay -69 -> 252, step: 4
5295 09:57:46.283942 iDelay=199, Bit 0, Center 94 (3 ~ 186) 184
5296 09:57:46.287962 iDelay=199, Bit 1, Center 98 (3 ~ 194) 192
5297 09:57:46.290833 iDelay=199, Bit 2, Center 96 (7 ~ 186) 180
5298 09:57:46.294146 iDelay=199, Bit 3, Center 92 (3 ~ 182) 180
5299 09:57:46.297232 iDelay=199, Bit 4, Center 102 (11 ~ 194) 184
5300 09:57:46.300687 iDelay=199, Bit 5, Center 88 (-5 ~ 182) 188
5301 09:57:46.307420 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5302 09:57:46.310380 iDelay=199, Bit 7, Center 108 (19 ~ 198) 180
5303 09:57:46.314015 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5304 09:57:46.317220 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5305 09:57:46.320442 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5306 09:57:46.327272 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5307 09:57:46.330239 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5308 09:57:46.333738 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5309 09:57:46.336744 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5310 09:57:46.340480 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5311 09:57:46.341431 ==
5312 09:57:46.343615 Dram Type= 6, Freq= 0, CH_0, rank 1
5313 09:57:46.350785 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5314 09:57:46.351351 ==
5315 09:57:46.351725 DQS Delay:
5316 09:57:46.352068 DQS0 = 0, DQS1 = 0
5317 09:57:46.353514 DQM Delay:
5318 09:57:46.353980 DQM0 = 97, DQM1 = 86
5319 09:57:46.357098 DQ Delay:
5320 09:57:46.360688 DQ0 =94, DQ1 =98, DQ2 =96, DQ3 =92
5321 09:57:46.364088 DQ4 =102, DQ5 =88, DQ6 =102, DQ7 =108
5322 09:57:46.367219 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =78
5323 09:57:46.370659 DQ12 =94, DQ13 =92, DQ14 =98, DQ15 =96
5324 09:57:46.371216
5325 09:57:46.371585
5326 09:57:46.377092 [DQSOSCAuto] RK1, (LSB)MR18= 0x2929, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5327 09:57:46.380404 CH0 RK1: MR19=505, MR18=2929
5328 09:57:46.387049 CH0_RK1: MR19=0x505, MR18=0x2929, DQSOSC=408, MR23=63, INC=65, DEC=43
5329 09:57:46.390322 [RxdqsGatingPostProcess] freq 933
5330 09:57:46.393878 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5331 09:57:46.396889 Pre-setting of DQS Precalculation
5332 09:57:46.403569 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5333 09:57:46.404126 ==
5334 09:57:46.407102 Dram Type= 6, Freq= 0, CH_1, rank 0
5335 09:57:46.410536 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5336 09:57:46.411091 ==
5337 09:57:46.416947 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5338 09:57:46.423678 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5339 09:57:46.426762 [CA 0] Center 37 (7~68) winsize 62
5340 09:57:46.430290 [CA 1] Center 37 (6~68) winsize 63
5341 09:57:46.433635 [CA 2] Center 34 (4~65) winsize 62
5342 09:57:46.436862 [CA 3] Center 34 (4~65) winsize 62
5343 09:57:46.440193 [CA 4] Center 33 (2~64) winsize 63
5344 09:57:46.440802 [CA 5] Center 33 (2~64) winsize 63
5345 09:57:46.441228
5346 09:57:46.446651 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5347 09:57:46.447111
5348 09:57:46.449639 [CATrainingPosCal] consider 1 rank data
5349 09:57:46.453217 u2DelayCellTimex100 = 270/100 ps
5350 09:57:46.456584 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5351 09:57:46.460262 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5352 09:57:46.463356 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5353 09:57:46.466541 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5354 09:57:46.470310 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5355 09:57:46.473234 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5356 09:57:46.473694
5357 09:57:46.476650 CA PerBit enable=1, Macro0, CA PI delay=33
5358 09:57:46.477150
5359 09:57:46.480097 [CBTSetCACLKResult] CA Dly = 33
5360 09:57:46.483009 CS Dly: 5 (0~36)
5361 09:57:46.483469 ==
5362 09:57:46.486508 Dram Type= 6, Freq= 0, CH_1, rank 1
5363 09:57:46.490421 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5364 09:57:46.490989 ==
5365 09:57:46.496422 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5366 09:57:46.503489 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5367 09:57:46.506251 [CA 0] Center 37 (6~68) winsize 63
5368 09:57:46.509680 [CA 1] Center 37 (6~68) winsize 63
5369 09:57:46.512919 [CA 2] Center 34 (4~65) winsize 62
5370 09:57:46.516114 [CA 3] Center 34 (3~65) winsize 63
5371 09:57:46.519759 [CA 4] Center 33 (2~64) winsize 63
5372 09:57:46.523216 [CA 5] Center 33 (2~64) winsize 63
5373 09:57:46.523776
5374 09:57:46.526408 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5375 09:57:46.526970
5376 09:57:46.529810 [CATrainingPosCal] consider 2 rank data
5377 09:57:46.532787 u2DelayCellTimex100 = 270/100 ps
5378 09:57:46.536477 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5379 09:57:46.539319 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5380 09:57:46.542794 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5381 09:57:46.546084 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5382 09:57:46.549537 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5383 09:57:46.552935 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5384 09:57:46.553498
5385 09:57:46.556391 CA PerBit enable=1, Macro0, CA PI delay=33
5386 09:57:46.559547
5387 09:57:46.560018 [CBTSetCACLKResult] CA Dly = 33
5388 09:57:46.563005 CS Dly: 5 (0~37)
5389 09:57:46.563564
5390 09:57:46.566173 ----->DramcWriteLeveling(PI) begin...
5391 09:57:46.566741 ==
5392 09:57:46.569289 Dram Type= 6, Freq= 0, CH_1, rank 0
5393 09:57:46.572880 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5394 09:57:46.573440 ==
5395 09:57:46.575963 Write leveling (Byte 0): 25 => 25
5396 09:57:46.579250 Write leveling (Byte 1): 25 => 25
5397 09:57:46.582688 DramcWriteLeveling(PI) end<-----
5398 09:57:46.583142
5399 09:57:46.583497 ==
5400 09:57:46.586168 Dram Type= 6, Freq= 0, CH_1, rank 0
5401 09:57:46.589234 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5402 09:57:46.589694 ==
5403 09:57:46.592661 [Gating] SW mode calibration
5404 09:57:46.599375 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5405 09:57:46.605948 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5406 09:57:46.609442 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5407 09:57:46.615827 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5408 09:57:46.619140 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5409 09:57:46.622470 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5410 09:57:46.629215 0 10 16 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 1)
5411 09:57:46.632399 0 10 20 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
5412 09:57:46.635909 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5413 09:57:46.642096 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5414 09:57:46.645384 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5415 09:57:46.648772 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5416 09:57:46.655783 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5417 09:57:46.658767 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5418 09:57:46.662362 0 11 16 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
5419 09:57:46.668768 0 11 20 | B1->B0 | 2a2a 4545 | 0 0 | (1 1) (0 0)
5420 09:57:46.672200 0 11 24 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5421 09:57:46.675648 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5422 09:57:46.682144 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5423 09:57:46.685406 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5424 09:57:46.688788 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5425 09:57:46.695709 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5426 09:57:46.698614 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5427 09:57:46.701897 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5428 09:57:46.705394 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5429 09:57:46.711931 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5430 09:57:46.715435 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5431 09:57:46.718926 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 09:57:46.725398 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 09:57:46.728888 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 09:57:46.732381 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5435 09:57:46.738957 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5436 09:57:46.741970 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5437 09:57:46.745146 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5438 09:57:46.751826 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 09:57:46.755256 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 09:57:46.758020 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 09:57:46.765100 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5442 09:57:46.768167 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5443 09:57:46.771970 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5444 09:57:46.775076 Total UI for P1: 0, mck2ui 16
5445 09:57:46.778208 best dqsien dly found for B0: ( 0, 14, 16)
5446 09:57:46.785302 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5447 09:57:46.785757 Total UI for P1: 0, mck2ui 16
5448 09:57:46.791653 best dqsien dly found for B1: ( 0, 14, 18)
5449 09:57:46.794902 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5450 09:57:46.798038 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5451 09:57:46.798491
5452 09:57:46.801653 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5453 09:57:46.804625 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5454 09:57:46.808016 [Gating] SW calibration Done
5455 09:57:46.808640 ==
5456 09:57:46.811639 Dram Type= 6, Freq= 0, CH_1, rank 0
5457 09:57:46.814483 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5458 09:57:46.815196 ==
5459 09:57:46.818018 RX Vref Scan: 0
5460 09:57:46.818607
5461 09:57:46.819035 RX Vref 0 -> 0, step: 1
5462 09:57:46.821493
5463 09:57:46.821945 RX Delay -80 -> 252, step: 8
5464 09:57:46.827960 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5465 09:57:46.831498 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5466 09:57:46.834595 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5467 09:57:46.837715 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5468 09:57:46.841095 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5469 09:57:46.844545 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5470 09:57:46.851322 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5471 09:57:46.854355 iDelay=208, Bit 7, Center 95 (-8 ~ 199) 208
5472 09:57:46.858044 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5473 09:57:46.861153 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5474 09:57:46.864550 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5475 09:57:46.870703 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5476 09:57:46.874275 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5477 09:57:46.877713 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5478 09:57:46.880634 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5479 09:57:46.884066 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5480 09:57:46.884572 ==
5481 09:57:46.887437 Dram Type= 6, Freq= 0, CH_1, rank 0
5482 09:57:46.893964 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5483 09:57:46.894525 ==
5484 09:57:46.894899 DQS Delay:
5485 09:57:46.895272 DQS0 = 0, DQS1 = 0
5486 09:57:46.897290 DQM Delay:
5487 09:57:46.897750 DQM0 = 94, DQM1 = 88
5488 09:57:46.900568 DQ Delay:
5489 09:57:46.903982 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5490 09:57:46.907594 DQ4 =95, DQ5 =103, DQ6 =99, DQ7 =95
5491 09:57:46.911122 DQ8 =71, DQ9 =79, DQ10 =91, DQ11 =79
5492 09:57:46.913991 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =99
5493 09:57:46.914546
5494 09:57:46.914909
5495 09:57:46.915242 ==
5496 09:57:46.917054 Dram Type= 6, Freq= 0, CH_1, rank 0
5497 09:57:46.920432 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5498 09:57:46.920924 ==
5499 09:57:46.921288
5500 09:57:46.921624
5501 09:57:46.924034 TX Vref Scan disable
5502 09:57:46.924489 == TX Byte 0 ==
5503 09:57:46.930541 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5504 09:57:46.933741 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5505 09:57:46.934302 == TX Byte 1 ==
5506 09:57:46.940011 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5507 09:57:46.943534 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5508 09:57:46.944037 ==
5509 09:57:46.946728 Dram Type= 6, Freq= 0, CH_1, rank 0
5510 09:57:46.950307 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5511 09:57:46.950873 ==
5512 09:57:46.951247
5513 09:57:46.953579
5514 09:57:46.954144 TX Vref Scan disable
5515 09:57:46.956848 == TX Byte 0 ==
5516 09:57:46.960406 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5517 09:57:46.963555 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5518 09:57:46.967163 == TX Byte 1 ==
5519 09:57:46.970189 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5520 09:57:46.976893 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5521 09:57:46.977461
5522 09:57:46.977830 [DATLAT]
5523 09:57:46.978168 Freq=933, CH1 RK0
5524 09:57:46.978496
5525 09:57:46.980041 DATLAT Default: 0xd
5526 09:57:46.980612 0, 0xFFFF, sum = 0
5527 09:57:46.983310 1, 0xFFFF, sum = 0
5528 09:57:46.983780 2, 0xFFFF, sum = 0
5529 09:57:46.986396 3, 0xFFFF, sum = 0
5530 09:57:46.986818 4, 0xFFFF, sum = 0
5531 09:57:46.989787 5, 0xFFFF, sum = 0
5532 09:57:46.993656 6, 0xFFFF, sum = 0
5533 09:57:46.994251 7, 0xFFFF, sum = 0
5534 09:57:46.996334 8, 0xFFFF, sum = 0
5535 09:57:46.996845 9, 0xFFFF, sum = 0
5536 09:57:46.999913 10, 0x0, sum = 1
5537 09:57:47.000384 11, 0x0, sum = 2
5538 09:57:47.002958 12, 0x0, sum = 3
5539 09:57:47.003427 13, 0x0, sum = 4
5540 09:57:47.003809 best_step = 11
5541 09:57:47.004179
5542 09:57:47.006541 ==
5543 09:57:47.009426 Dram Type= 6, Freq= 0, CH_1, rank 0
5544 09:57:47.012995 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5545 09:57:47.013462 ==
5546 09:57:47.013832 RX Vref Scan: 1
5547 09:57:47.014174
5548 09:57:47.016115 RX Vref 0 -> 0, step: 1
5549 09:57:47.016615
5550 09:57:47.019901 RX Delay -69 -> 252, step: 4
5551 09:57:47.020464
5552 09:57:47.023335 Set Vref, RX VrefLevel [Byte0]: 53
5553 09:57:47.026143 [Byte1]: 49
5554 09:57:47.026606
5555 09:57:47.029828 Final RX Vref Byte 0 = 53 to rank0
5556 09:57:47.032954 Final RX Vref Byte 1 = 49 to rank0
5557 09:57:47.036657 Final RX Vref Byte 0 = 53 to rank1
5558 09:57:47.039523 Final RX Vref Byte 1 = 49 to rank1==
5559 09:57:47.042872 Dram Type= 6, Freq= 0, CH_1, rank 0
5560 09:57:47.046072 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5561 09:57:47.049682 ==
5562 09:57:47.050250 DQS Delay:
5563 09:57:47.050622 DQS0 = 0, DQS1 = 0
5564 09:57:47.053026 DQM Delay:
5565 09:57:47.053588 DQM0 = 94, DQM1 = 88
5566 09:57:47.056005 DQ Delay:
5567 09:57:47.056464 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =90
5568 09:57:47.059640 DQ4 =92, DQ5 =104, DQ6 =102, DQ7 =92
5569 09:57:47.063047 DQ8 =72, DQ9 =76, DQ10 =90, DQ11 =80
5570 09:57:47.066091 DQ12 =96, DQ13 =98, DQ14 =98, DQ15 =98
5571 09:57:47.069478
5572 09:57:47.070046
5573 09:57:47.076116 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c3c, (MSB)MR19= 0x505, tDQSOscB0 = 403 ps tDQSOscB1 = 403 ps
5574 09:57:47.079626 CH1 RK0: MR19=505, MR18=3C3C
5575 09:57:47.086193 CH1_RK0: MR19=0x505, MR18=0x3C3C, DQSOSC=403, MR23=63, INC=66, DEC=44
5576 09:57:47.086768
5577 09:57:47.089401 ----->DramcWriteLeveling(PI) begin...
5578 09:57:47.089872 ==
5579 09:57:47.092917 Dram Type= 6, Freq= 0, CH_1, rank 1
5580 09:57:47.096163 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5581 09:57:47.096787 ==
5582 09:57:47.099494 Write leveling (Byte 0): 24 => 24
5583 09:57:47.102729 Write leveling (Byte 1): 25 => 25
5584 09:57:47.106123 DramcWriteLeveling(PI) end<-----
5585 09:57:47.106690
5586 09:57:47.107057 ==
5587 09:57:47.109224 Dram Type= 6, Freq= 0, CH_1, rank 1
5588 09:57:47.112705 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5589 09:57:47.113273 ==
5590 09:57:47.116070 [Gating] SW mode calibration
5591 09:57:47.122844 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5592 09:57:47.129179 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5593 09:57:47.132673 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5594 09:57:47.135692 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5595 09:57:47.142261 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 09:57:47.145645 0 10 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5597 09:57:47.148813 0 10 16 | B1->B0 | 3434 2626 | 1 1 | (1 1) (1 1)
5598 09:57:47.155773 0 10 20 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5599 09:57:47.158782 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5600 09:57:47.162550 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5601 09:57:47.169101 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 09:57:47.172227 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 09:57:47.175742 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 09:57:47.182292 0 11 12 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
5605 09:57:47.185220 0 11 16 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
5606 09:57:47.189017 0 11 20 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
5607 09:57:47.195444 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 09:57:47.198792 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 09:57:47.201770 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 09:57:47.208659 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 09:57:47.211767 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 09:57:47.215414 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 09:57:47.222126 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5614 09:57:47.225241 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 09:57:47.228614 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 09:57:47.234865 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 09:57:47.238515 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 09:57:47.241590 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 09:57:47.248312 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 09:57:47.252003 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 09:57:47.254820 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 09:57:47.261905 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 09:57:47.265037 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 09:57:47.268569 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 09:57:47.274965 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 09:57:47.278184 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 09:57:47.281371 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 09:57:47.287909 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5629 09:57:47.291480 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5630 09:57:47.294997 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 09:57:47.297939 Total UI for P1: 0, mck2ui 16
5632 09:57:47.301204 best dqsien dly found for B0: ( 0, 14, 14)
5633 09:57:47.304782 Total UI for P1: 0, mck2ui 16
5634 09:57:47.308004 best dqsien dly found for B1: ( 0, 14, 18)
5635 09:57:47.311363 best DQS0 dly(MCK, UI, PI) = (0, 14, 14)
5636 09:57:47.314955 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5637 09:57:47.315514
5638 09:57:47.318102 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14)
5639 09:57:47.324889 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5640 09:57:47.325456 [Gating] SW calibration Done
5641 09:57:47.328132 ==
5642 09:57:47.328742 Dram Type= 6, Freq= 0, CH_1, rank 1
5643 09:57:47.335059 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5644 09:57:47.335587 ==
5645 09:57:47.335956 RX Vref Scan: 0
5646 09:57:47.336292
5647 09:57:47.337661 RX Vref 0 -> 0, step: 1
5648 09:57:47.338122
5649 09:57:47.341082 RX Delay -80 -> 252, step: 8
5650 09:57:47.344627 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5651 09:57:47.347676 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5652 09:57:47.351519 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5653 09:57:47.357575 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5654 09:57:47.361480 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5655 09:57:47.364225 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5656 09:57:47.367701 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5657 09:57:47.370939 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5658 09:57:47.374295 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5659 09:57:47.380696 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5660 09:57:47.384095 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5661 09:57:47.387375 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5662 09:57:47.390882 iDelay=208, Bit 12, Center 95 (-8 ~ 199) 208
5663 09:57:47.394141 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5664 09:57:47.400644 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5665 09:57:47.403815 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5666 09:57:47.404279 ==
5667 09:57:47.407325 Dram Type= 6, Freq= 0, CH_1, rank 1
5668 09:57:47.410539 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5669 09:57:47.411006 ==
5670 09:57:47.411374 DQS Delay:
5671 09:57:47.413946 DQS0 = 0, DQS1 = 0
5672 09:57:47.414442 DQM Delay:
5673 09:57:47.417398 DQM0 = 96, DQM1 = 86
5674 09:57:47.417860 DQ Delay:
5675 09:57:47.420674 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5676 09:57:47.423763 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5677 09:57:47.427050 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =75
5678 09:57:47.430471 DQ12 =95, DQ13 =99, DQ14 =91, DQ15 =95
5679 09:57:47.431037
5680 09:57:47.431408
5681 09:57:47.431751 ==
5682 09:57:47.433991 Dram Type= 6, Freq= 0, CH_1, rank 1
5683 09:57:47.440654 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5684 09:57:47.441214 ==
5685 09:57:47.441586
5686 09:57:47.441928
5687 09:57:47.442256 TX Vref Scan disable
5688 09:57:47.443699 == TX Byte 0 ==
5689 09:57:47.447160 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5690 09:57:47.450437 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5691 09:57:47.453921 == TX Byte 1 ==
5692 09:57:47.457075 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5693 09:57:47.460452 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5694 09:57:47.463859 ==
5695 09:57:47.467644 Dram Type= 6, Freq= 0, CH_1, rank 1
5696 09:57:47.470345 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5697 09:57:47.470841 ==
5698 09:57:47.471215
5699 09:57:47.471554
5700 09:57:47.473702 TX Vref Scan disable
5701 09:57:47.474162 == TX Byte 0 ==
5702 09:57:47.480850 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5703 09:57:47.484096 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5704 09:57:47.484601 == TX Byte 1 ==
5705 09:57:47.490714 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5706 09:57:47.494218 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5707 09:57:47.494786
5708 09:57:47.495154 [DATLAT]
5709 09:57:47.497225 Freq=933, CH1 RK1
5710 09:57:47.497688
5711 09:57:47.498055 DATLAT Default: 0xb
5712 09:57:47.500498 0, 0xFFFF, sum = 0
5713 09:57:47.501017 1, 0xFFFF, sum = 0
5714 09:57:47.503669 2, 0xFFFF, sum = 0
5715 09:57:47.504134 3, 0xFFFF, sum = 0
5716 09:57:47.507260 4, 0xFFFF, sum = 0
5717 09:57:47.507728 5, 0xFFFF, sum = 0
5718 09:57:47.510373 6, 0xFFFF, sum = 0
5719 09:57:47.510866 7, 0xFFFF, sum = 0
5720 09:57:47.513495 8, 0xFFFF, sum = 0
5721 09:57:47.516828 9, 0xFFFF, sum = 0
5722 09:57:47.517298 10, 0x0, sum = 1
5723 09:57:47.517672 11, 0x0, sum = 2
5724 09:57:47.520089 12, 0x0, sum = 3
5725 09:57:47.520589 13, 0x0, sum = 4
5726 09:57:47.523687 best_step = 11
5727 09:57:47.524146
5728 09:57:47.524550 ==
5729 09:57:47.526759 Dram Type= 6, Freq= 0, CH_1, rank 1
5730 09:57:47.530470 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5731 09:57:47.530937 ==
5732 09:57:47.533517 RX Vref Scan: 0
5733 09:57:47.533978
5734 09:57:47.534344 RX Vref 0 -> 0, step: 1
5735 09:57:47.534690
5736 09:57:47.536563 RX Delay -69 -> 252, step: 4
5737 09:57:47.543965 iDelay=203, Bit 0, Center 98 (7 ~ 190) 184
5738 09:57:47.547427 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5739 09:57:47.550791 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5740 09:57:47.554216 iDelay=203, Bit 3, Center 92 (3 ~ 182) 180
5741 09:57:47.557427 iDelay=203, Bit 4, Center 94 (-1 ~ 190) 192
5742 09:57:47.560813 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5743 09:57:47.567813 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5744 09:57:47.570481 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5745 09:57:47.573872 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5746 09:57:47.577871 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5747 09:57:47.580715 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5748 09:57:47.587274 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5749 09:57:47.590384 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5750 09:57:47.593914 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5751 09:57:47.597374 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5752 09:57:47.600585 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5753 09:57:47.601051 ==
5754 09:57:47.603817 Dram Type= 6, Freq= 0, CH_1, rank 1
5755 09:57:47.610688 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5756 09:57:47.611156 ==
5757 09:57:47.611526 DQS Delay:
5758 09:57:47.613905 DQS0 = 0, DQS1 = 0
5759 09:57:47.614367 DQM Delay:
5760 09:57:47.614733 DQM0 = 95, DQM1 = 87
5761 09:57:47.617117 DQ Delay:
5762 09:57:47.620460 DQ0 =98, DQ1 =90, DQ2 =88, DQ3 =92
5763 09:57:47.623749 DQ4 =94, DQ5 =106, DQ6 =104, DQ7 =94
5764 09:57:47.627061 DQ8 =74, DQ9 =74, DQ10 =88, DQ11 =80
5765 09:57:47.630188 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =94
5766 09:57:47.630651
5767 09:57:47.631019
5768 09:57:47.637091 [DQSOSCAuto] RK1, (LSB)MR18= 0x2222, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5769 09:57:47.640384 CH1 RK1: MR19=505, MR18=2222
5770 09:57:47.646932 CH1_RK1: MR19=0x505, MR18=0x2222, DQSOSC=411, MR23=63, INC=64, DEC=42
5771 09:57:47.650200 [RxdqsGatingPostProcess] freq 933
5772 09:57:47.653727 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5773 09:57:47.657345 Pre-setting of DQS Precalculation
5774 09:57:47.663971 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5775 09:57:47.670202 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5776 09:57:47.676961 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5777 09:57:47.677527
5778 09:57:47.677902
5779 09:57:47.680344 [Calibration Summary] 1866 Mbps
5780 09:57:47.680959 CH 0, Rank 0
5781 09:57:47.683945 SW Impedance : PASS
5782 09:57:47.686739 DUTY Scan : NO K
5783 09:57:47.687205 ZQ Calibration : PASS
5784 09:57:47.690156 Jitter Meter : NO K
5785 09:57:47.693636 CBT Training : PASS
5786 09:57:47.694196 Write leveling : PASS
5787 09:57:47.696768 RX DQS gating : PASS
5788 09:57:47.700190 RX DQ/DQS(RDDQC) : PASS
5789 09:57:47.700813 TX DQ/DQS : PASS
5790 09:57:47.704058 RX DATLAT : PASS
5791 09:57:47.706933 RX DQ/DQS(Engine): PASS
5792 09:57:47.707488 TX OE : NO K
5793 09:57:47.710105 All Pass.
5794 09:57:47.710571
5795 09:57:47.710961 CH 0, Rank 1
5796 09:57:47.713693 SW Impedance : PASS
5797 09:57:47.714420 DUTY Scan : NO K
5798 09:57:47.716710 ZQ Calibration : PASS
5799 09:57:47.719798 Jitter Meter : NO K
5800 09:57:47.720260 CBT Training : PASS
5801 09:57:47.723237 Write leveling : PASS
5802 09:57:47.726692 RX DQS gating : PASS
5803 09:57:47.727239 RX DQ/DQS(RDDQC) : PASS
5804 09:57:47.729802 TX DQ/DQS : PASS
5805 09:57:47.733198 RX DATLAT : PASS
5806 09:57:47.733732 RX DQ/DQS(Engine): PASS
5807 09:57:47.736369 TX OE : NO K
5808 09:57:47.736886 All Pass.
5809 09:57:47.737258
5810 09:57:47.739818 CH 1, Rank 0
5811 09:57:47.740280 SW Impedance : PASS
5812 09:57:47.743246 DUTY Scan : NO K
5813 09:57:47.743706 ZQ Calibration : PASS
5814 09:57:47.746374 Jitter Meter : NO K
5815 09:57:47.749939 CBT Training : PASS
5816 09:57:47.750405 Write leveling : PASS
5817 09:57:47.753084 RX DQS gating : PASS
5818 09:57:47.756334 RX DQ/DQS(RDDQC) : PASS
5819 09:57:47.756848 TX DQ/DQS : PASS
5820 09:57:47.759689 RX DATLAT : PASS
5821 09:57:47.762633 RX DQ/DQS(Engine): PASS
5822 09:57:47.763095 TX OE : NO K
5823 09:57:47.766594 All Pass.
5824 09:57:47.767145
5825 09:57:47.767519 CH 1, Rank 1
5826 09:57:47.769490 SW Impedance : PASS
5827 09:57:47.769951 DUTY Scan : NO K
5828 09:57:47.772758 ZQ Calibration : PASS
5829 09:57:47.776051 Jitter Meter : NO K
5830 09:57:47.776661 CBT Training : PASS
5831 09:57:47.779689 Write leveling : PASS
5832 09:57:47.782817 RX DQS gating : PASS
5833 09:57:47.783287 RX DQ/DQS(RDDQC) : PASS
5834 09:57:47.786387 TX DQ/DQS : PASS
5835 09:57:47.789753 RX DATLAT : PASS
5836 09:57:47.790323 RX DQ/DQS(Engine): PASS
5837 09:57:47.792715 TX OE : NO K
5838 09:57:47.793174 All Pass.
5839 09:57:47.793535
5840 09:57:47.795655 DramC Write-DBI off
5841 09:57:47.799340 PER_BANK_REFRESH: Hybrid Mode
5842 09:57:47.799894 TX_TRACKING: ON
5843 09:57:47.809013 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5844 09:57:47.812164 [FAST_K] Save calibration result to emmc
5845 09:57:47.815523 dramc_set_vcore_voltage set vcore to 650000
5846 09:57:47.819255 Read voltage for 400, 6
5847 09:57:47.819829 Vio18 = 0
5848 09:57:47.820198 Vcore = 650000
5849 09:57:47.822547 Vdram = 0
5850 09:57:47.823116 Vddq = 0
5851 09:57:47.823489 Vmddr = 0
5852 09:57:47.828604 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5853 09:57:47.832688 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5854 09:57:47.835609 MEM_TYPE=3, freq_sel=20
5855 09:57:47.838826 sv_algorithm_assistance_LP4_800
5856 09:57:47.842134 ============ PULL DRAM RESETB DOWN ============
5857 09:57:47.845459 ========== PULL DRAM RESETB DOWN end =========
5858 09:57:47.852087 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5859 09:57:47.855519 ===================================
5860 09:57:47.856079 LPDDR4 DRAM CONFIGURATION
5861 09:57:47.858622 ===================================
5862 09:57:47.861912 EX_ROW_EN[0] = 0x0
5863 09:57:47.865267 EX_ROW_EN[1] = 0x0
5864 09:57:47.865828 LP4Y_EN = 0x0
5865 09:57:47.868781 WORK_FSP = 0x0
5866 09:57:47.869416 WL = 0x2
5867 09:57:47.871871 RL = 0x2
5868 09:57:47.872445 BL = 0x2
5869 09:57:47.875266 RPST = 0x0
5870 09:57:47.875847 RD_PRE = 0x0
5871 09:57:47.878814 WR_PRE = 0x1
5872 09:57:47.879377 WR_PST = 0x0
5873 09:57:47.881646 DBI_WR = 0x0
5874 09:57:47.882138 DBI_RD = 0x0
5875 09:57:47.885107 OTF = 0x1
5876 09:57:47.888393 ===================================
5877 09:57:47.892157 ===================================
5878 09:57:47.892778 ANA top config
5879 09:57:47.895207 ===================================
5880 09:57:47.898453 DLL_ASYNC_EN = 0
5881 09:57:47.902218 ALL_SLAVE_EN = 1
5882 09:57:47.904887 NEW_RANK_MODE = 1
5883 09:57:47.905371 DLL_IDLE_MODE = 1
5884 09:57:47.908048 LP45_APHY_COMB_EN = 1
5885 09:57:47.911767 TX_ODT_DIS = 1
5886 09:57:47.915222 NEW_8X_MODE = 1
5887 09:57:47.918642 ===================================
5888 09:57:47.921620 ===================================
5889 09:57:47.924714 data_rate = 800
5890 09:57:47.928340 CKR = 1
5891 09:57:47.928994 DQ_P2S_RATIO = 4
5892 09:57:47.931324 ===================================
5893 09:57:47.934464 CA_P2S_RATIO = 4
5894 09:57:47.938011 DQ_CA_OPEN = 0
5895 09:57:47.941377 DQ_SEMI_OPEN = 1
5896 09:57:47.944815 CA_SEMI_OPEN = 1
5897 09:57:47.948043 CA_FULL_RATE = 0
5898 09:57:47.948579 DQ_CKDIV4_EN = 0
5899 09:57:47.951059 CA_CKDIV4_EN = 1
5900 09:57:47.954522 CA_PREDIV_EN = 0
5901 09:57:47.957641 PH8_DLY = 0
5902 09:57:47.961421 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5903 09:57:47.961877 DQ_AAMCK_DIV = 0
5904 09:57:47.964381 CA_AAMCK_DIV = 0
5905 09:57:47.967922 CA_ADMCK_DIV = 4
5906 09:57:47.971197 DQ_TRACK_CA_EN = 0
5907 09:57:47.974432 CA_PICK = 800
5908 09:57:47.977742 CA_MCKIO = 400
5909 09:57:47.981296 MCKIO_SEMI = 400
5910 09:57:47.984358 PLL_FREQ = 3016
5911 09:57:47.984861 DQ_UI_PI_RATIO = 32
5912 09:57:47.987714 CA_UI_PI_RATIO = 32
5913 09:57:47.991457 ===================================
5914 09:57:47.994606 ===================================
5915 09:57:47.998133 memory_type:LPDDR4
5916 09:57:48.000984 GP_NUM : 10
5917 09:57:48.001437 SRAM_EN : 1
5918 09:57:48.004341 MD32_EN : 0
5919 09:57:48.007397 ===================================
5920 09:57:48.010734 [ANA_INIT] >>>>>>>>>>>>>>
5921 09:57:48.011192 <<<<<< [CONFIGURE PHASE]: ANA_TX
5922 09:57:48.014313 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5923 09:57:48.017492 ===================================
5924 09:57:48.020834 data_rate = 800,PCW = 0X7400
5925 09:57:48.024162 ===================================
5926 09:57:48.027292 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5927 09:57:48.033767 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5928 09:57:48.044187 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5929 09:57:48.050678 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5930 09:57:48.053732 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5931 09:57:48.057119 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5932 09:57:48.057576 [ANA_INIT] flow start
5933 09:57:48.060411 [ANA_INIT] PLL >>>>>>>>
5934 09:57:48.063964 [ANA_INIT] PLL <<<<<<<<
5935 09:57:48.067216 [ANA_INIT] MIDPI >>>>>>>>
5936 09:57:48.067767 [ANA_INIT] MIDPI <<<<<<<<
5937 09:57:48.070316 [ANA_INIT] DLL >>>>>>>>
5938 09:57:48.073689 [ANA_INIT] flow end
5939 09:57:48.077279 ============ LP4 DIFF to SE enter ============
5940 09:57:48.080448 ============ LP4 DIFF to SE exit ============
5941 09:57:48.083700 [ANA_INIT] <<<<<<<<<<<<<
5942 09:57:48.087093 [Flow] Enable top DCM control >>>>>
5943 09:57:48.090210 [Flow] Enable top DCM control <<<<<
5944 09:57:48.093744 Enable DLL master slave shuffle
5945 09:57:48.096967 ==============================================================
5946 09:57:48.100210 Gating Mode config
5947 09:57:48.103464 ==============================================================
5948 09:57:48.107406 Config description:
5949 09:57:48.116907 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5950 09:57:48.123252 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5951 09:57:48.126635 SELPH_MODE 0: By rank 1: By Phase
5952 09:57:48.133264 ==============================================================
5953 09:57:48.136451 GAT_TRACK_EN = 0
5954 09:57:48.139875 RX_GATING_MODE = 2
5955 09:57:48.143323 RX_GATING_TRACK_MODE = 2
5956 09:57:48.146580 SELPH_MODE = 1
5957 09:57:48.149811 PICG_EARLY_EN = 1
5958 09:57:48.153523 VALID_LAT_VALUE = 1
5959 09:57:48.156493 ==============================================================
5960 09:57:48.159949 Enter into Gating configuration >>>>
5961 09:57:48.163343 Exit from Gating configuration <<<<
5962 09:57:48.166541 Enter into DVFS_PRE_config >>>>>
5963 09:57:48.176726 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5964 09:57:48.179718 Exit from DVFS_PRE_config <<<<<
5965 09:57:48.182881 Enter into PICG configuration >>>>
5966 09:57:48.186193 Exit from PICG configuration <<<<
5967 09:57:48.189693 [RX_INPUT] configuration >>>>>
5968 09:57:48.192997 [RX_INPUT] configuration <<<<<
5969 09:57:48.199928 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5970 09:57:48.203108 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5971 09:57:48.209431 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5972 09:57:48.216060 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5973 09:57:48.223080 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5974 09:57:48.229278 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5975 09:57:48.233198 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5976 09:57:48.236260 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5977 09:57:48.239800 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5978 09:57:48.246121 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5979 09:57:48.249280 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5980 09:57:48.253000 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5981 09:57:48.256261 ===================================
5982 09:57:48.259784 LPDDR4 DRAM CONFIGURATION
5983 09:57:48.262676 ===================================
5984 09:57:48.263246 EX_ROW_EN[0] = 0x0
5985 09:57:48.265852 EX_ROW_EN[1] = 0x0
5986 09:57:48.269324 LP4Y_EN = 0x0
5987 09:57:48.269837 WORK_FSP = 0x0
5988 09:57:48.272740 WL = 0x2
5989 09:57:48.273217 RL = 0x2
5990 09:57:48.275900 BL = 0x2
5991 09:57:48.276460 RPST = 0x0
5992 09:57:48.279197 RD_PRE = 0x0
5993 09:57:48.279659 WR_PRE = 0x1
5994 09:57:48.282288 WR_PST = 0x0
5995 09:57:48.282753 DBI_WR = 0x0
5996 09:57:48.285556 DBI_RD = 0x0
5997 09:57:48.286022 OTF = 0x1
5998 09:57:48.289005 ===================================
5999 09:57:48.292468 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6000 09:57:48.299063 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6001 09:57:48.302436 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6002 09:57:48.305542 ===================================
6003 09:57:48.309158 LPDDR4 DRAM CONFIGURATION
6004 09:57:48.312330 ===================================
6005 09:57:48.312821 EX_ROW_EN[0] = 0x10
6006 09:57:48.315694 EX_ROW_EN[1] = 0x0
6007 09:57:48.318962 LP4Y_EN = 0x0
6008 09:57:48.319489 WORK_FSP = 0x0
6009 09:57:48.322286 WL = 0x2
6010 09:57:48.322849 RL = 0x2
6011 09:57:48.325387 BL = 0x2
6012 09:57:48.325870 RPST = 0x0
6013 09:57:48.328767 RD_PRE = 0x0
6014 09:57:48.329225 WR_PRE = 0x1
6015 09:57:48.332297 WR_PST = 0x0
6016 09:57:48.332883 DBI_WR = 0x0
6017 09:57:48.335524 DBI_RD = 0x0
6018 09:57:48.336187 OTF = 0x1
6019 09:57:48.339006 ===================================
6020 09:57:48.345589 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6021 09:57:48.349557 nWR fixed to 30
6022 09:57:48.353182 [ModeRegInit_LP4] CH0 RK0
6023 09:57:48.353642 [ModeRegInit_LP4] CH0 RK1
6024 09:57:48.356403 [ModeRegInit_LP4] CH1 RK0
6025 09:57:48.359596 [ModeRegInit_LP4] CH1 RK1
6026 09:57:48.360229 match AC timing 18
6027 09:57:48.366398 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6028 09:57:48.369737 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6029 09:57:48.372708 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6030 09:57:48.379545 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6031 09:57:48.388197 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6032 09:57:48.388746 ==
6033 09:57:48.389510 Dram Type= 6, Freq= 0, CH_0, rank 0
6034 09:57:48.389894 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6035 09:57:48.390241 ==
6036 09:57:48.396340 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6037 09:57:48.402710 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6038 09:57:48.406242 [CA 0] Center 36 (8~64) winsize 57
6039 09:57:48.409335 [CA 1] Center 36 (8~64) winsize 57
6040 09:57:48.412947 [CA 2] Center 36 (8~64) winsize 57
6041 09:57:48.416115 [CA 3] Center 36 (8~64) winsize 57
6042 09:57:48.416789 [CA 4] Center 36 (8~64) winsize 57
6043 09:57:48.419168 [CA 5] Center 36 (8~64) winsize 57
6044 09:57:48.419631
6045 09:57:48.426051 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6046 09:57:48.426611
6047 09:57:48.429387 [CATrainingPosCal] consider 1 rank data
6048 09:57:48.432487 u2DelayCellTimex100 = 270/100 ps
6049 09:57:48.435888 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6050 09:57:48.439440 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6051 09:57:48.442663 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6052 09:57:48.445825 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6053 09:57:48.449105 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6054 09:57:48.452265 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6055 09:57:48.452784
6056 09:57:48.455612 CA PerBit enable=1, Macro0, CA PI delay=36
6057 09:57:48.456165
6058 09:57:48.459114 [CBTSetCACLKResult] CA Dly = 36
6059 09:57:48.462480 CS Dly: 1 (0~32)
6060 09:57:48.463034 ==
6061 09:57:48.465687 Dram Type= 6, Freq= 0, CH_0, rank 1
6062 09:57:48.469069 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6063 09:57:48.469636 ==
6064 09:57:48.475749 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6065 09:57:48.482442 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6066 09:57:48.483017 [CA 0] Center 36 (8~64) winsize 57
6067 09:57:48.485735 [CA 1] Center 36 (8~64) winsize 57
6068 09:57:48.488961 [CA 2] Center 36 (8~64) winsize 57
6069 09:57:48.492317 [CA 3] Center 36 (8~64) winsize 57
6070 09:57:48.496020 [CA 4] Center 36 (8~64) winsize 57
6071 09:57:48.499069 [CA 5] Center 36 (8~64) winsize 57
6072 09:57:48.499630
6073 09:57:48.502503 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6074 09:57:48.503053
6075 09:57:48.505661 [CATrainingPosCal] consider 2 rank data
6076 09:57:48.509007 u2DelayCellTimex100 = 270/100 ps
6077 09:57:48.512392 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6078 09:57:48.515568 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6079 09:57:48.522344 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6080 09:57:48.525277 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6081 09:57:48.528905 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6082 09:57:48.532142 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6083 09:57:48.532761
6084 09:57:48.535423 CA PerBit enable=1, Macro0, CA PI delay=36
6085 09:57:48.535887
6086 09:57:48.538614 [CBTSetCACLKResult] CA Dly = 36
6087 09:57:48.539157 CS Dly: 1 (0~32)
6088 09:57:48.539529
6089 09:57:48.542211 ----->DramcWriteLeveling(PI) begin...
6090 09:57:48.545196 ==
6091 09:57:48.548474 Dram Type= 6, Freq= 0, CH_0, rank 0
6092 09:57:48.551903 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6093 09:57:48.552378 ==
6094 09:57:48.555241 Write leveling (Byte 0): 32 => 0
6095 09:57:48.559418 Write leveling (Byte 1): 32 => 0
6096 09:57:48.561875 DramcWriteLeveling(PI) end<-----
6097 09:57:48.562486
6098 09:57:48.562856 ==
6099 09:57:48.565351 Dram Type= 6, Freq= 0, CH_0, rank 0
6100 09:57:48.568420 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6101 09:57:48.568948 ==
6102 09:57:48.571883 [Gating] SW mode calibration
6103 09:57:48.578312 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6104 09:57:48.584962 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6105 09:57:48.587897 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6106 09:57:48.591343 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6107 09:57:48.598157 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6108 09:57:48.601374 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6109 09:57:48.604567 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6110 09:57:48.611540 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6111 09:57:48.615041 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6112 09:57:48.617981 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6113 09:57:48.621305 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6114 09:57:48.625062 Total UI for P1: 0, mck2ui 16
6115 09:57:48.628010 best dqsien dly found for B0: ( 0, 10, 16)
6116 09:57:48.631335 Total UI for P1: 0, mck2ui 16
6117 09:57:48.634453 best dqsien dly found for B1: ( 0, 10, 16)
6118 09:57:48.640956 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6119 09:57:48.644423 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6120 09:57:48.644937
6121 09:57:48.647601 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6122 09:57:48.650780 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6123 09:57:48.654127 [Gating] SW calibration Done
6124 09:57:48.654590 ==
6125 09:57:48.657643 Dram Type= 6, Freq= 0, CH_0, rank 0
6126 09:57:48.660716 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6127 09:57:48.661256 ==
6128 09:57:48.664224 RX Vref Scan: 0
6129 09:57:48.664814
6130 09:57:48.665180 RX Vref 0 -> 0, step: 1
6131 09:57:48.665551
6132 09:57:48.667480 RX Delay -410 -> 252, step: 16
6133 09:57:48.673838 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6134 09:57:48.677094 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6135 09:57:48.680331 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6136 09:57:48.684385 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6137 09:57:48.690490 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6138 09:57:48.694013 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6139 09:57:48.697327 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6140 09:57:48.700863 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6141 09:57:48.707649 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6142 09:57:48.710382 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6143 09:57:48.713901 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6144 09:57:48.716968 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6145 09:57:48.723723 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6146 09:57:48.727095 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6147 09:57:48.730082 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6148 09:57:48.736880 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6149 09:57:48.737443 ==
6150 09:57:48.740435 Dram Type= 6, Freq= 0, CH_0, rank 0
6151 09:57:48.743445 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6152 09:57:48.743919 ==
6153 09:57:48.744359 DQS Delay:
6154 09:57:48.746652 DQS0 = 43, DQS1 = 59
6155 09:57:48.747118 DQM Delay:
6156 09:57:48.750032 DQM0 = 6, DQM1 = 16
6157 09:57:48.750549 DQ Delay:
6158 09:57:48.753255 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6159 09:57:48.756571 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6160 09:57:48.760213 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6161 09:57:48.763737 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6162 09:57:48.764293
6163 09:57:48.764702
6164 09:57:48.765050 ==
6165 09:57:48.766392 Dram Type= 6, Freq= 0, CH_0, rank 0
6166 09:57:48.769676 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6167 09:57:48.770140 ==
6168 09:57:48.770553
6169 09:57:48.770932
6170 09:57:48.773310 TX Vref Scan disable
6171 09:57:48.773803 == TX Byte 0 ==
6172 09:57:48.780165 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6173 09:57:48.783276 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6174 09:57:48.783745 == TX Byte 1 ==
6175 09:57:48.789658 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6176 09:57:48.793107 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6177 09:57:48.793573 ==
6178 09:57:48.796302 Dram Type= 6, Freq= 0, CH_0, rank 0
6179 09:57:48.799778 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6180 09:57:48.800391 ==
6181 09:57:48.800834
6182 09:57:48.801180
6183 09:57:48.803104 TX Vref Scan disable
6184 09:57:48.806601 == TX Byte 0 ==
6185 09:57:48.809641 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6186 09:57:48.813068 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6187 09:57:48.816046 == TX Byte 1 ==
6188 09:57:48.819514 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6189 09:57:48.823146 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6190 09:57:48.823708
6191 09:57:48.826113 [DATLAT]
6192 09:57:48.826699 Freq=400, CH0 RK0
6193 09:57:48.827136
6194 09:57:48.829357 DATLAT Default: 0xf
6195 09:57:48.829818 0, 0xFFFF, sum = 0
6196 09:57:48.832757 1, 0xFFFF, sum = 0
6197 09:57:48.833333 2, 0xFFFF, sum = 0
6198 09:57:48.836196 3, 0xFFFF, sum = 0
6199 09:57:48.836807 4, 0xFFFF, sum = 0
6200 09:57:48.839488 5, 0xFFFF, sum = 0
6201 09:57:48.840061 6, 0xFFFF, sum = 0
6202 09:57:48.842609 7, 0xFFFF, sum = 0
6203 09:57:48.843081 8, 0xFFFF, sum = 0
6204 09:57:48.845725 9, 0xFFFF, sum = 0
6205 09:57:48.846251 10, 0xFFFF, sum = 0
6206 09:57:48.849176 11, 0xFFFF, sum = 0
6207 09:57:48.849748 12, 0x0, sum = 1
6208 09:57:48.852643 13, 0x0, sum = 2
6209 09:57:48.853131 14, 0x0, sum = 3
6210 09:57:48.855972 15, 0x0, sum = 4
6211 09:57:48.856589 best_step = 13
6212 09:57:48.857076
6213 09:57:48.857429 ==
6214 09:57:48.858978 Dram Type= 6, Freq= 0, CH_0, rank 0
6215 09:57:48.865941 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6216 09:57:48.866517 ==
6217 09:57:48.867002 RX Vref Scan: 1
6218 09:57:48.867360
6219 09:57:48.868871 RX Vref 0 -> 0, step: 1
6220 09:57:48.869347
6221 09:57:48.872216 RX Delay -359 -> 252, step: 8
6222 09:57:48.872745
6223 09:57:48.875739 Set Vref, RX VrefLevel [Byte0]: 46
6224 09:57:48.879192 [Byte1]: 49
6225 09:57:48.879742
6226 09:57:48.882162 Final RX Vref Byte 0 = 46 to rank0
6227 09:57:48.885698 Final RX Vref Byte 1 = 49 to rank0
6228 09:57:48.889184 Final RX Vref Byte 0 = 46 to rank1
6229 09:57:48.892216 Final RX Vref Byte 1 = 49 to rank1==
6230 09:57:48.895390 Dram Type= 6, Freq= 0, CH_0, rank 0
6231 09:57:48.898634 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6232 09:57:48.901949 ==
6233 09:57:48.902555 DQS Delay:
6234 09:57:48.902953 DQS0 = 52, DQS1 = 68
6235 09:57:48.905918 DQM Delay:
6236 09:57:48.906493 DQM0 = 9, DQM1 = 17
6237 09:57:48.908652 DQ Delay:
6238 09:57:48.909119 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6239 09:57:48.912568 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6240 09:57:48.915731 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6241 09:57:48.919171 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6242 09:57:48.919738
6243 09:57:48.920108
6244 09:57:48.928805 [DQSOSCAuto] RK0, (LSB)MR18= 0xa6a6, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6245 09:57:48.931974 CH0 RK0: MR19=C0C, MR18=A6A6
6246 09:57:48.938521 CH0_RK0: MR19=0xC0C, MR18=0xA6A6, DQSOSC=389, MR23=63, INC=390, DEC=260
6247 09:57:48.939105 ==
6248 09:57:48.941738 Dram Type= 6, Freq= 0, CH_0, rank 1
6249 09:57:48.945116 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6250 09:57:48.945586 ==
6251 09:57:48.948394 [Gating] SW mode calibration
6252 09:57:48.955048 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6253 09:57:48.958230 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6254 09:57:48.965128 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6255 09:57:48.968635 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6256 09:57:48.971399 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6257 09:57:48.978209 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6258 09:57:48.981765 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6259 09:57:48.984968 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6260 09:57:48.991315 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6261 09:57:48.994935 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6262 09:57:48.998844 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6263 09:57:49.001635 Total UI for P1: 0, mck2ui 16
6264 09:57:49.005111 best dqsien dly found for B0: ( 0, 10, 16)
6265 09:57:49.008555 Total UI for P1: 0, mck2ui 16
6266 09:57:49.011384 best dqsien dly found for B1: ( 0, 10, 16)
6267 09:57:49.015183 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6268 09:57:49.018189 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6269 09:57:49.021534
6270 09:57:49.024794 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6271 09:57:49.028386 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6272 09:57:49.031251 [Gating] SW calibration Done
6273 09:57:49.031887 ==
6274 09:57:49.034499 Dram Type= 6, Freq= 0, CH_0, rank 1
6275 09:57:49.038048 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6276 09:57:49.038797 ==
6277 09:57:49.039378 RX Vref Scan: 0
6278 09:57:49.041473
6279 09:57:49.042105 RX Vref 0 -> 0, step: 1
6280 09:57:49.042684
6281 09:57:49.044820 RX Delay -410 -> 252, step: 16
6282 09:57:49.047926 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6283 09:57:49.054302 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6284 09:57:49.058243 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6285 09:57:49.061350 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6286 09:57:49.064283 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6287 09:57:49.071119 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6288 09:57:49.074337 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6289 09:57:49.077858 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6290 09:57:49.081000 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6291 09:57:49.087621 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6292 09:57:49.090786 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6293 09:57:49.094022 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6294 09:57:49.097837 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6295 09:57:49.104392 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6296 09:57:49.107939 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6297 09:57:49.110616 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6298 09:57:49.111250 ==
6299 09:57:49.114392 Dram Type= 6, Freq= 0, CH_0, rank 1
6300 09:57:49.121006 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6301 09:57:49.121465 ==
6302 09:57:49.121827 DQS Delay:
6303 09:57:49.124110 DQS0 = 43, DQS1 = 59
6304 09:57:49.124748 DQM Delay:
6305 09:57:49.125121 DQM0 = 7, DQM1 = 15
6306 09:57:49.127452 DQ Delay:
6307 09:57:49.130673 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6308 09:57:49.131269 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6309 09:57:49.134173 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6310 09:57:49.137400 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6311 09:57:49.137858
6312 09:57:49.140631
6313 09:57:49.141241 ==
6314 09:57:49.144139 Dram Type= 6, Freq= 0, CH_0, rank 1
6315 09:57:49.147176 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6316 09:57:49.147634 ==
6317 09:57:49.148010
6318 09:57:49.148346
6319 09:57:49.150468 TX Vref Scan disable
6320 09:57:49.151074 == TX Byte 0 ==
6321 09:57:49.153876 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6322 09:57:49.160623 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6323 09:57:49.161085 == TX Byte 1 ==
6324 09:57:49.163900 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6325 09:57:49.171007 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6326 09:57:49.171573 ==
6327 09:57:49.173890 Dram Type= 6, Freq= 0, CH_0, rank 1
6328 09:57:49.177304 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6329 09:57:49.178083 ==
6330 09:57:49.178497
6331 09:57:49.178839
6332 09:57:49.180561 TX Vref Scan disable
6333 09:57:49.181165 == TX Byte 0 ==
6334 09:57:49.184010 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6335 09:57:49.190593 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6336 09:57:49.191151 == TX Byte 1 ==
6337 09:57:49.193633 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6338 09:57:49.200482 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6339 09:57:49.201102
6340 09:57:49.201492 [DATLAT]
6341 09:57:49.202056 Freq=400, CH0 RK1
6342 09:57:49.202573
6343 09:57:49.203494 DATLAT Default: 0xd
6344 09:57:49.207271 0, 0xFFFF, sum = 0
6345 09:57:49.207832 1, 0xFFFF, sum = 0
6346 09:57:49.210165 2, 0xFFFF, sum = 0
6347 09:57:49.210623 3, 0xFFFF, sum = 0
6348 09:57:49.213517 4, 0xFFFF, sum = 0
6349 09:57:49.213975 5, 0xFFFF, sum = 0
6350 09:57:49.216912 6, 0xFFFF, sum = 0
6351 09:57:49.217394 7, 0xFFFF, sum = 0
6352 09:57:49.220308 8, 0xFFFF, sum = 0
6353 09:57:49.220820 9, 0xFFFF, sum = 0
6354 09:57:49.223877 10, 0xFFFF, sum = 0
6355 09:57:49.224332 11, 0xFFFF, sum = 0
6356 09:57:49.226660 12, 0x0, sum = 1
6357 09:57:49.227147 13, 0x0, sum = 2
6358 09:57:49.230211 14, 0x0, sum = 3
6359 09:57:49.230668 15, 0x0, sum = 4
6360 09:57:49.233413 best_step = 13
6361 09:57:49.233867
6362 09:57:49.234227 ==
6363 09:57:49.236868 Dram Type= 6, Freq= 0, CH_0, rank 1
6364 09:57:49.240221 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6365 09:57:49.240821 ==
6366 09:57:49.241192 RX Vref Scan: 0
6367 09:57:49.243429
6368 09:57:49.243991 RX Vref 0 -> 0, step: 1
6369 09:57:49.244367
6370 09:57:49.246841 RX Delay -359 -> 252, step: 8
6371 09:57:49.254185 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6372 09:57:49.257436 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6373 09:57:49.261098 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6374 09:57:49.264419 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6375 09:57:49.271031 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6376 09:57:49.274023 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6377 09:57:49.277492 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6378 09:57:49.280891 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6379 09:57:49.287619 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6380 09:57:49.290830 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6381 09:57:49.293914 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6382 09:57:49.300937 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6383 09:57:49.304030 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6384 09:57:49.307520 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6385 09:57:49.311047 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6386 09:57:49.317457 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6387 09:57:49.318018 ==
6388 09:57:49.320629 Dram Type= 6, Freq= 0, CH_0, rank 1
6389 09:57:49.323978 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6390 09:57:49.324574 ==
6391 09:57:49.324944 DQS Delay:
6392 09:57:49.327609 DQS0 = 52, DQS1 = 64
6393 09:57:49.328158 DQM Delay:
6394 09:57:49.330813 DQM0 = 10, DQM1 = 14
6395 09:57:49.331369 DQ Delay:
6396 09:57:49.333794 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6397 09:57:49.337379 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6398 09:57:49.340645 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6399 09:57:49.344055 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6400 09:57:49.344685
6401 09:57:49.345070
6402 09:57:49.350294 [DQSOSCAuto] RK1, (LSB)MR18= 0xcccc, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6403 09:57:49.353440 CH0 RK1: MR19=C0C, MR18=CCCC
6404 09:57:49.360552 CH0_RK1: MR19=0xC0C, MR18=0xCCCC, DQSOSC=384, MR23=63, INC=400, DEC=267
6405 09:57:49.363759 [RxdqsGatingPostProcess] freq 400
6406 09:57:49.370576 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6407 09:57:49.373617 Pre-setting of DQS Precalculation
6408 09:57:49.377228 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6409 09:57:49.377777 ==
6410 09:57:49.380309 Dram Type= 6, Freq= 0, CH_1, rank 0
6411 09:57:49.383621 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6412 09:57:49.384175 ==
6413 09:57:49.390276 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6414 09:57:49.396869 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6415 09:57:49.399896 [CA 0] Center 36 (8~64) winsize 57
6416 09:57:49.403656 [CA 1] Center 36 (8~64) winsize 57
6417 09:57:49.406818 [CA 2] Center 36 (8~64) winsize 57
6418 09:57:49.410126 [CA 3] Center 36 (8~64) winsize 57
6419 09:57:49.413204 [CA 4] Center 36 (8~64) winsize 57
6420 09:57:49.413663 [CA 5] Center 36 (8~64) winsize 57
6421 09:57:49.416897
6422 09:57:49.419975 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6423 09:57:49.420554
6424 09:57:49.423111 [CATrainingPosCal] consider 1 rank data
6425 09:57:49.426647 u2DelayCellTimex100 = 270/100 ps
6426 09:57:49.430351 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6427 09:57:49.433266 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6428 09:57:49.437106 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6429 09:57:49.440375 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6430 09:57:49.443449 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6431 09:57:49.446609 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6432 09:57:49.447060
6433 09:57:49.449601 CA PerBit enable=1, Macro0, CA PI delay=36
6434 09:57:49.450054
6435 09:57:49.453076 [CBTSetCACLKResult] CA Dly = 36
6436 09:57:49.456234 CS Dly: 1 (0~32)
6437 09:57:49.456865 ==
6438 09:57:49.459599 Dram Type= 6, Freq= 0, CH_1, rank 1
6439 09:57:49.463605 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6440 09:57:49.464160 ==
6441 09:57:49.469862 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6442 09:57:49.476279 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6443 09:57:49.479774 [CA 0] Center 36 (8~64) winsize 57
6444 09:57:49.480240 [CA 1] Center 36 (8~64) winsize 57
6445 09:57:49.482915 [CA 2] Center 36 (8~64) winsize 57
6446 09:57:49.486234 [CA 3] Center 36 (8~64) winsize 57
6447 09:57:49.489736 [CA 4] Center 36 (8~64) winsize 57
6448 09:57:49.493017 [CA 5] Center 36 (8~64) winsize 57
6449 09:57:49.493560
6450 09:57:49.496148 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6451 09:57:49.496675
6452 09:57:49.499549 [CATrainingPosCal] consider 2 rank data
6453 09:57:49.503120 u2DelayCellTimex100 = 270/100 ps
6454 09:57:49.506343 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6455 09:57:49.512933 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6456 09:57:49.516424 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6457 09:57:49.519975 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6458 09:57:49.522936 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6459 09:57:49.526599 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6460 09:57:49.527061
6461 09:57:49.529760 CA PerBit enable=1, Macro0, CA PI delay=36
6462 09:57:49.530220
6463 09:57:49.532929 [CBTSetCACLKResult] CA Dly = 36
6464 09:57:49.533390 CS Dly: 1 (0~32)
6465 09:57:49.533764
6466 09:57:49.536487 ----->DramcWriteLeveling(PI) begin...
6467 09:57:49.539552 ==
6468 09:57:49.543258 Dram Type= 6, Freq= 0, CH_1, rank 0
6469 09:57:49.546141 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6470 09:57:49.546605 ==
6471 09:57:49.549329 Write leveling (Byte 0): 32 => 0
6472 09:57:49.552423 Write leveling (Byte 1): 32 => 0
6473 09:57:49.556374 DramcWriteLeveling(PI) end<-----
6474 09:57:49.556941
6475 09:57:49.557308 ==
6476 09:57:49.559185 Dram Type= 6, Freq= 0, CH_1, rank 0
6477 09:57:49.562516 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6478 09:57:49.562980 ==
6479 09:57:49.566093 [Gating] SW mode calibration
6480 09:57:49.572587 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6481 09:57:49.579482 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6482 09:57:49.582591 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6483 09:57:49.586143 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6484 09:57:49.592439 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6485 09:57:49.595766 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6486 09:57:49.599242 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6487 09:57:49.602726 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6488 09:57:49.608972 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6489 09:57:49.612429 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6490 09:57:49.615823 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6491 09:57:49.619182 Total UI for P1: 0, mck2ui 16
6492 09:57:49.622445 best dqsien dly found for B0: ( 0, 10, 16)
6493 09:57:49.625844 Total UI for P1: 0, mck2ui 16
6494 09:57:49.628837 best dqsien dly found for B1: ( 0, 10, 16)
6495 09:57:49.632434 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6496 09:57:49.639163 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6497 09:57:49.639703
6498 09:57:49.642174 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6499 09:57:49.645375 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6500 09:57:49.648811 [Gating] SW calibration Done
6501 09:57:49.649266 ==
6502 09:57:49.652113 Dram Type= 6, Freq= 0, CH_1, rank 0
6503 09:57:49.655436 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6504 09:57:49.655890 ==
6505 09:57:49.659037 RX Vref Scan: 0
6506 09:57:49.659587
6507 09:57:49.659952 RX Vref 0 -> 0, step: 1
6508 09:57:49.660289
6509 09:57:49.661990 RX Delay -410 -> 252, step: 16
6510 09:57:49.668754 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6511 09:57:49.672041 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6512 09:57:49.674991 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6513 09:57:49.678783 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6514 09:57:49.684942 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6515 09:57:49.688545 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6516 09:57:49.691400 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6517 09:57:49.695092 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6518 09:57:49.701290 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6519 09:57:49.704911 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6520 09:57:49.708121 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6521 09:57:49.711327 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6522 09:57:49.718403 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6523 09:57:49.721474 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6524 09:57:49.724852 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6525 09:57:49.727763 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6526 09:57:49.731393 ==
6527 09:57:49.734669 Dram Type= 6, Freq= 0, CH_1, rank 0
6528 09:57:49.737753 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6529 09:57:49.738221 ==
6530 09:57:49.738595 DQS Delay:
6531 09:57:49.741193 DQS0 = 43, DQS1 = 59
6532 09:57:49.741657 DQM Delay:
6533 09:57:49.744650 DQM0 = 6, DQM1 = 14
6534 09:57:49.745197 DQ Delay:
6535 09:57:49.748265 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6536 09:57:49.751301 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6537 09:57:49.754573 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6538 09:57:49.758033 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6539 09:57:49.758575
6540 09:57:49.758944
6541 09:57:49.759283 ==
6542 09:57:49.761507 Dram Type= 6, Freq= 0, CH_1, rank 0
6543 09:57:49.764407 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6544 09:57:49.764921 ==
6545 09:57:49.765290
6546 09:57:49.765633
6547 09:57:49.767546 TX Vref Scan disable
6548 09:57:49.768032 == TX Byte 0 ==
6549 09:57:49.774344 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6550 09:57:49.777622 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6551 09:57:49.778170 == TX Byte 1 ==
6552 09:57:49.784299 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6553 09:57:49.787975 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6554 09:57:49.788573 ==
6555 09:57:49.790878 Dram Type= 6, Freq= 0, CH_1, rank 0
6556 09:57:49.794471 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6557 09:57:49.794936 ==
6558 09:57:49.795485
6559 09:57:49.795844
6560 09:57:49.797451 TX Vref Scan disable
6561 09:57:49.800847 == TX Byte 0 ==
6562 09:57:49.804078 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6563 09:57:49.807488 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6564 09:57:49.810872 == TX Byte 1 ==
6565 09:57:49.814328 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6566 09:57:49.817214 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6567 09:57:49.817676
6568 09:57:49.818040 [DATLAT]
6569 09:57:49.820406 Freq=400, CH1 RK0
6570 09:57:49.820920
6571 09:57:49.823792 DATLAT Default: 0xf
6572 09:57:49.824430 0, 0xFFFF, sum = 0
6573 09:57:49.827515 1, 0xFFFF, sum = 0
6574 09:57:49.828018 2, 0xFFFF, sum = 0
6575 09:57:49.830324 3, 0xFFFF, sum = 0
6576 09:57:49.830791 4, 0xFFFF, sum = 0
6577 09:57:49.833836 5, 0xFFFF, sum = 0
6578 09:57:49.834406 6, 0xFFFF, sum = 0
6579 09:57:49.837119 7, 0xFFFF, sum = 0
6580 09:57:49.837604 8, 0xFFFF, sum = 0
6581 09:57:49.840313 9, 0xFFFF, sum = 0
6582 09:57:49.840832 10, 0xFFFF, sum = 0
6583 09:57:49.843736 11, 0xFFFF, sum = 0
6584 09:57:49.844210 12, 0x0, sum = 1
6585 09:57:49.847012 13, 0x0, sum = 2
6586 09:57:49.847477 14, 0x0, sum = 3
6587 09:57:49.850348 15, 0x0, sum = 4
6588 09:57:49.850847 best_step = 13
6589 09:57:49.851210
6590 09:57:49.851560 ==
6591 09:57:49.853568 Dram Type= 6, Freq= 0, CH_1, rank 0
6592 09:57:49.857319 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6593 09:57:49.860148 ==
6594 09:57:49.860687 RX Vref Scan: 1
6595 09:57:49.861026
6596 09:57:49.863581 RX Vref 0 -> 0, step: 1
6597 09:57:49.863998
6598 09:57:49.867030 RX Delay -359 -> 252, step: 8
6599 09:57:49.867448
6600 09:57:49.870457 Set Vref, RX VrefLevel [Byte0]: 53
6601 09:57:49.873505 [Byte1]: 49
6602 09:57:49.873925
6603 09:57:49.876648 Final RX Vref Byte 0 = 53 to rank0
6604 09:57:49.880029 Final RX Vref Byte 1 = 49 to rank0
6605 09:57:49.883555 Final RX Vref Byte 0 = 53 to rank1
6606 09:57:49.886709 Final RX Vref Byte 1 = 49 to rank1==
6607 09:57:49.890016 Dram Type= 6, Freq= 0, CH_1, rank 0
6608 09:57:49.893482 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6609 09:57:49.896395 ==
6610 09:57:49.896916 DQS Delay:
6611 09:57:49.897360 DQS0 = 48, DQS1 = 64
6612 09:57:49.899860 DQM Delay:
6613 09:57:49.900315 DQM0 = 9, DQM1 = 16
6614 09:57:49.903549 DQ Delay:
6615 09:57:49.904080 DQ0 =8, DQ1 =4, DQ2 =0, DQ3 =8
6616 09:57:49.906878 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6617 09:57:49.909907 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6618 09:57:49.913237 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6619 09:57:49.913671
6620 09:57:49.914106
6621 09:57:49.923114 [DQSOSCAuto] RK0, (LSB)MR18= 0xe5e5, (MSB)MR19= 0xc0c, tDQSOscB0 = 381 ps tDQSOscB1 = 381 ps
6622 09:57:49.926611 CH1 RK0: MR19=C0C, MR18=E5E5
6623 09:57:49.929980 CH1_RK0: MR19=0xC0C, MR18=0xE5E5, DQSOSC=381, MR23=63, INC=406, DEC=271
6624 09:57:49.933075 ==
6625 09:57:49.933508 Dram Type= 6, Freq= 0, CH_1, rank 1
6626 09:57:49.939759 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6627 09:57:49.940239 ==
6628 09:57:49.942919 [Gating] SW mode calibration
6629 09:57:49.949521 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6630 09:57:49.952805 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6631 09:57:49.959566 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6632 09:57:49.962796 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6633 09:57:49.966530 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6634 09:57:49.972872 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6635 09:57:49.976038 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6636 09:57:49.979685 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6637 09:57:49.985800 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6638 09:57:49.989534 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6639 09:57:49.992638 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6640 09:57:49.996012 Total UI for P1: 0, mck2ui 16
6641 09:57:49.999372 best dqsien dly found for B0: ( 0, 10, 16)
6642 09:57:50.002463 Total UI for P1: 0, mck2ui 16
6643 09:57:50.005890 best dqsien dly found for B1: ( 0, 10, 16)
6644 09:57:50.009159 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6645 09:57:50.012489 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6646 09:57:50.012980
6647 09:57:50.019171 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6648 09:57:50.022946 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6649 09:57:50.025871 [Gating] SW calibration Done
6650 09:57:50.026413 ==
6651 09:57:50.029655 Dram Type= 6, Freq= 0, CH_1, rank 1
6652 09:57:50.032381 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6653 09:57:50.032906 ==
6654 09:57:50.033346 RX Vref Scan: 0
6655 09:57:50.033761
6656 09:57:50.035567 RX Vref 0 -> 0, step: 1
6657 09:57:50.036092
6658 09:57:50.038752 RX Delay -410 -> 252, step: 16
6659 09:57:50.042360 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6660 09:57:50.049005 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6661 09:57:50.052108 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6662 09:57:50.055290 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6663 09:57:50.058945 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6664 09:57:50.065474 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6665 09:57:50.069025 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6666 09:57:50.071988 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6667 09:57:50.075614 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6668 09:57:50.082139 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6669 09:57:50.085565 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6670 09:57:50.088687 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6671 09:57:50.091951 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6672 09:57:50.098640 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6673 09:57:50.102067 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6674 09:57:50.105196 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6675 09:57:50.105625 ==
6676 09:57:50.108612 Dram Type= 6, Freq= 0, CH_1, rank 1
6677 09:57:50.115182 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6678 09:57:50.115689 ==
6679 09:57:50.116137 DQS Delay:
6680 09:57:50.116701 DQS0 = 35, DQS1 = 59
6681 09:57:50.118512 DQM Delay:
6682 09:57:50.118940 DQM0 = 3, DQM1 = 18
6683 09:57:50.121819 DQ Delay:
6684 09:57:50.122253 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6685 09:57:50.125066 DQ4 =0, DQ5 =16, DQ6 =8, DQ7 =0
6686 09:57:50.128668 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6687 09:57:50.132393 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6688 09:57:50.132975
6689 09:57:50.133422
6690 09:57:50.133835 ==
6691 09:57:50.135075 Dram Type= 6, Freq= 0, CH_1, rank 1
6692 09:57:50.141517 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6693 09:57:50.142055 ==
6694 09:57:50.142504
6695 09:57:50.142915
6696 09:57:50.143317 TX Vref Scan disable
6697 09:57:50.145027 == TX Byte 0 ==
6698 09:57:50.148768 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6699 09:57:50.151758 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6700 09:57:50.154869 == TX Byte 1 ==
6701 09:57:50.158676 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6702 09:57:50.161750 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6703 09:57:50.165147 ==
6704 09:57:50.165793 Dram Type= 6, Freq= 0, CH_1, rank 1
6705 09:57:50.172005 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6706 09:57:50.172498 ==
6707 09:57:50.172893
6708 09:57:50.173212
6709 09:57:50.174752 TX Vref Scan disable
6710 09:57:50.175168 == TX Byte 0 ==
6711 09:57:50.178347 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6712 09:57:50.185190 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6713 09:57:50.185705 == TX Byte 1 ==
6714 09:57:50.188158 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6715 09:57:50.195075 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6716 09:57:50.195624
6717 09:57:50.195961 [DATLAT]
6718 09:57:50.196275 Freq=400, CH1 RK1
6719 09:57:50.196630
6720 09:57:50.197987 DATLAT Default: 0xd
6721 09:57:50.198423 0, 0xFFFF, sum = 0
6722 09:57:50.201277 1, 0xFFFF, sum = 0
6723 09:57:50.201800 2, 0xFFFF, sum = 0
6724 09:57:50.204550 3, 0xFFFF, sum = 0
6725 09:57:50.204992 4, 0xFFFF, sum = 0
6726 09:57:50.207990 5, 0xFFFF, sum = 0
6727 09:57:50.211503 6, 0xFFFF, sum = 0
6728 09:57:50.212047 7, 0xFFFF, sum = 0
6729 09:57:50.214441 8, 0xFFFF, sum = 0
6730 09:57:50.214884 9, 0xFFFF, sum = 0
6731 09:57:50.218188 10, 0xFFFF, sum = 0
6732 09:57:50.218713 11, 0xFFFF, sum = 0
6733 09:57:50.221079 12, 0x0, sum = 1
6734 09:57:50.221516 13, 0x0, sum = 2
6735 09:57:50.224395 14, 0x0, sum = 3
6736 09:57:50.224881 15, 0x0, sum = 4
6737 09:57:50.227770 best_step = 13
6738 09:57:50.228199
6739 09:57:50.228729 ==
6740 09:57:50.230952 Dram Type= 6, Freq= 0, CH_1, rank 1
6741 09:57:50.234543 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6742 09:57:50.235096 ==
6743 09:57:50.235550 RX Vref Scan: 0
6744 09:57:50.235966
6745 09:57:50.237879 RX Vref 0 -> 0, step: 1
6746 09:57:50.238418
6747 09:57:50.240825 RX Delay -359 -> 252, step: 8
6748 09:57:50.248473 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6749 09:57:50.251479 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6750 09:57:50.255166 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6751 09:57:50.258460 iDelay=225, Bit 3, Center -44 (-287 ~ 200) 488
6752 09:57:50.264841 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6753 09:57:50.268664 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6754 09:57:50.271656 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6755 09:57:50.274909 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6756 09:57:50.281332 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6757 09:57:50.284924 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504
6758 09:57:50.288352 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6759 09:57:50.294906 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6760 09:57:50.297922 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6761 09:57:50.301338 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6762 09:57:50.304852 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6763 09:57:50.311602 iDelay=225, Bit 15, Center -40 (-287 ~ 208) 496
6764 09:57:50.312220 ==
6765 09:57:50.315129 Dram Type= 6, Freq= 0, CH_1, rank 1
6766 09:57:50.318027 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6767 09:57:50.318551 ==
6768 09:57:50.318887 DQS Delay:
6769 09:57:50.320982 DQS0 = 48, DQS1 = 64
6770 09:57:50.321398 DQM Delay:
6771 09:57:50.324563 DQM0 = 9, DQM1 = 15
6772 09:57:50.324982 DQ Delay:
6773 09:57:50.328093 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6774 09:57:50.331102 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6775 09:57:50.334704 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6776 09:57:50.337735 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6777 09:57:50.338152
6778 09:57:50.338484
6779 09:57:50.344833 [DQSOSCAuto] RK1, (LSB)MR18= 0xb1b1, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6780 09:57:50.347621 CH1 RK1: MR19=C0C, MR18=B1B1
6781 09:57:50.354267 CH1_RK1: MR19=0xC0C, MR18=0xB1B1, DQSOSC=387, MR23=63, INC=394, DEC=262
6782 09:57:50.357549 [RxdqsGatingPostProcess] freq 400
6783 09:57:50.364572 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6784 09:57:50.364995 Pre-setting of DQS Precalculation
6785 09:57:50.370656 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6786 09:57:50.377538 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6787 09:57:50.384170 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6788 09:57:50.384711
6789 09:57:50.385043
6790 09:57:50.387419 [Calibration Summary] 800 Mbps
6791 09:57:50.390774 CH 0, Rank 0
6792 09:57:50.391186 SW Impedance : PASS
6793 09:57:50.394548 DUTY Scan : NO K
6794 09:57:50.397398 ZQ Calibration : PASS
6795 09:57:50.397817 Jitter Meter : NO K
6796 09:57:50.400667 CBT Training : PASS
6797 09:57:50.403969 Write leveling : PASS
6798 09:57:50.404381 RX DQS gating : PASS
6799 09:57:50.407687 RX DQ/DQS(RDDQC) : PASS
6800 09:57:50.408207 TX DQ/DQS : PASS
6801 09:57:50.410950 RX DATLAT : PASS
6802 09:57:50.413943 RX DQ/DQS(Engine): PASS
6803 09:57:50.414359 TX OE : NO K
6804 09:57:50.417255 All Pass.
6805 09:57:50.417674
6806 09:57:50.418001 CH 0, Rank 1
6807 09:57:50.420654 SW Impedance : PASS
6808 09:57:50.421092 DUTY Scan : NO K
6809 09:57:50.424553 ZQ Calibration : PASS
6810 09:57:50.427304 Jitter Meter : NO K
6811 09:57:50.427720 CBT Training : PASS
6812 09:57:50.430547 Write leveling : NO K
6813 09:57:50.433656 RX DQS gating : PASS
6814 09:57:50.434169 RX DQ/DQS(RDDQC) : PASS
6815 09:57:50.437187 TX DQ/DQS : PASS
6816 09:57:50.440232 RX DATLAT : PASS
6817 09:57:50.440729 RX DQ/DQS(Engine): PASS
6818 09:57:50.443761 TX OE : NO K
6819 09:57:50.444221 All Pass.
6820 09:57:50.444638
6821 09:57:50.447284 CH 1, Rank 0
6822 09:57:50.447741 SW Impedance : PASS
6823 09:57:50.450436 DUTY Scan : NO K
6824 09:57:50.453612 ZQ Calibration : PASS
6825 09:57:50.454286 Jitter Meter : NO K
6826 09:57:50.457040 CBT Training : PASS
6827 09:57:50.460433 Write leveling : PASS
6828 09:57:50.460941 RX DQS gating : PASS
6829 09:57:50.463743 RX DQ/DQS(RDDQC) : PASS
6830 09:57:50.467129 TX DQ/DQS : PASS
6831 09:57:50.467678 RX DATLAT : PASS
6832 09:57:50.470210 RX DQ/DQS(Engine): PASS
6833 09:57:50.470665 TX OE : NO K
6834 09:57:50.473523 All Pass.
6835 09:57:50.474050
6836 09:57:50.474416 CH 1, Rank 1
6837 09:57:50.477118 SW Impedance : PASS
6838 09:57:50.477668 DUTY Scan : NO K
6839 09:57:50.480092 ZQ Calibration : PASS
6840 09:57:50.483589 Jitter Meter : NO K
6841 09:57:50.484121 CBT Training : PASS
6842 09:57:50.486727 Write leveling : NO K
6843 09:57:50.490139 RX DQS gating : PASS
6844 09:57:50.490598 RX DQ/DQS(RDDQC) : PASS
6845 09:57:50.493585 TX DQ/DQS : PASS
6846 09:57:50.496829 RX DATLAT : PASS
6847 09:57:50.497289 RX DQ/DQS(Engine): PASS
6848 09:57:50.499889 TX OE : NO K
6849 09:57:50.500368 All Pass.
6850 09:57:50.500794
6851 09:57:50.503286 DramC Write-DBI off
6852 09:57:50.506881 PER_BANK_REFRESH: Hybrid Mode
6853 09:57:50.507422 TX_TRACKING: ON
6854 09:57:50.516729 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6855 09:57:50.519957 [FAST_K] Save calibration result to emmc
6856 09:57:50.523387 dramc_set_vcore_voltage set vcore to 725000
6857 09:57:50.526986 Read voltage for 1600, 0
6858 09:57:50.527556 Vio18 = 0
6859 09:57:50.527921 Vcore = 725000
6860 09:57:50.529934 Vdram = 0
6861 09:57:50.530496 Vddq = 0
6862 09:57:50.530864 Vmddr = 0
6863 09:57:50.536450 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6864 09:57:50.540152 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6865 09:57:50.542928 MEM_TYPE=3, freq_sel=13
6866 09:57:50.546598 sv_algorithm_assistance_LP4_3733
6867 09:57:50.549769 ============ PULL DRAM RESETB DOWN ============
6868 09:57:50.553042 ========== PULL DRAM RESETB DOWN end =========
6869 09:57:50.559811 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6870 09:57:50.563048 ===================================
6871 09:57:50.566254 LPDDR4 DRAM CONFIGURATION
6872 09:57:50.570058 ===================================
6873 09:57:50.570732 EX_ROW_EN[0] = 0x0
6874 09:57:50.573144 EX_ROW_EN[1] = 0x0
6875 09:57:50.573597 LP4Y_EN = 0x0
6876 09:57:50.576749 WORK_FSP = 0x1
6877 09:57:50.577302 WL = 0x5
6878 09:57:50.579936 RL = 0x5
6879 09:57:50.580391 BL = 0x2
6880 09:57:50.582943 RPST = 0x0
6881 09:57:50.583498 RD_PRE = 0x0
6882 09:57:50.586244 WR_PRE = 0x1
6883 09:57:50.586699 WR_PST = 0x1
6884 09:57:50.589712 DBI_WR = 0x0
6885 09:57:50.590260 DBI_RD = 0x0
6886 09:57:50.592932 OTF = 0x1
6887 09:57:50.596391 ===================================
6888 09:57:50.599471 ===================================
6889 09:57:50.599932 ANA top config
6890 09:57:50.603115 ===================================
6891 09:57:50.606226 DLL_ASYNC_EN = 0
6892 09:57:50.609604 ALL_SLAVE_EN = 0
6893 09:57:50.612888 NEW_RANK_MODE = 1
6894 09:57:50.613462 DLL_IDLE_MODE = 1
6895 09:57:50.616250 LP45_APHY_COMB_EN = 1
6896 09:57:50.619467 TX_ODT_DIS = 0
6897 09:57:50.623130 NEW_8X_MODE = 1
6898 09:57:50.626065 ===================================
6899 09:57:50.629317 ===================================
6900 09:57:50.632631 data_rate = 3200
6901 09:57:50.636263 CKR = 1
6902 09:57:50.636787 DQ_P2S_RATIO = 8
6903 09:57:50.639613 ===================================
6904 09:57:50.642784 CA_P2S_RATIO = 8
6905 09:57:50.646058 DQ_CA_OPEN = 0
6906 09:57:50.649387 DQ_SEMI_OPEN = 0
6907 09:57:50.652373 CA_SEMI_OPEN = 0
6908 09:57:50.652885 CA_FULL_RATE = 0
6909 09:57:50.655626 DQ_CKDIV4_EN = 0
6910 09:57:50.659229 CA_CKDIV4_EN = 0
6911 09:57:50.662617 CA_PREDIV_EN = 0
6912 09:57:50.665833 PH8_DLY = 12
6913 09:57:50.669349 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6914 09:57:50.672358 DQ_AAMCK_DIV = 4
6915 09:57:50.672868 CA_AAMCK_DIV = 4
6916 09:57:50.675694 CA_ADMCK_DIV = 4
6917 09:57:50.679389 DQ_TRACK_CA_EN = 0
6918 09:57:50.682627 CA_PICK = 1600
6919 09:57:50.685880 CA_MCKIO = 1600
6920 09:57:50.689004 MCKIO_SEMI = 0
6921 09:57:50.692360 PLL_FREQ = 3068
6922 09:57:50.692859 DQ_UI_PI_RATIO = 32
6923 09:57:50.695665 CA_UI_PI_RATIO = 0
6924 09:57:50.699243 ===================================
6925 09:57:50.701816 ===================================
6926 09:57:50.705310 memory_type:LPDDR4
6927 09:57:50.708542 GP_NUM : 10
6928 09:57:50.709000 SRAM_EN : 1
6929 09:57:50.712017 MD32_EN : 0
6930 09:57:50.715421 ===================================
6931 09:57:50.718729 [ANA_INIT] >>>>>>>>>>>>>>
6932 09:57:50.722068 <<<<<< [CONFIGURE PHASE]: ANA_TX
6933 09:57:50.725385 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6934 09:57:50.728718 ===================================
6935 09:57:50.729277 data_rate = 3200,PCW = 0X7600
6936 09:57:50.731854 ===================================
6937 09:57:50.735288 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6938 09:57:50.741398 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6939 09:57:50.748468 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6940 09:57:50.751497 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6941 09:57:50.754802 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6942 09:57:50.758095 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6943 09:57:50.761394 [ANA_INIT] flow start
6944 09:57:50.764691 [ANA_INIT] PLL >>>>>>>>
6945 09:57:50.765153 [ANA_INIT] PLL <<<<<<<<
6946 09:57:50.768063 [ANA_INIT] MIDPI >>>>>>>>
6947 09:57:50.771280 [ANA_INIT] MIDPI <<<<<<<<
6948 09:57:50.771837 [ANA_INIT] DLL >>>>>>>>
6949 09:57:50.774768 [ANA_INIT] DLL <<<<<<<<
6950 09:57:50.778062 [ANA_INIT] flow end
6951 09:57:50.781183 ============ LP4 DIFF to SE enter ============
6952 09:57:50.785085 ============ LP4 DIFF to SE exit ============
6953 09:57:50.788144 [ANA_INIT] <<<<<<<<<<<<<
6954 09:57:50.791541 [Flow] Enable top DCM control >>>>>
6955 09:57:50.794824 [Flow] Enable top DCM control <<<<<
6956 09:57:50.798350 Enable DLL master slave shuffle
6957 09:57:50.801685 ==============================================================
6958 09:57:50.804285 Gating Mode config
6959 09:57:50.811253 ==============================================================
6960 09:57:50.811817 Config description:
6961 09:57:50.820904 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6962 09:57:50.827602 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6963 09:57:50.830962 SELPH_MODE 0: By rank 1: By Phase
6964 09:57:50.837517 ==============================================================
6965 09:57:50.840807 GAT_TRACK_EN = 1
6966 09:57:50.844204 RX_GATING_MODE = 2
6967 09:57:50.847678 RX_GATING_TRACK_MODE = 2
6968 09:57:50.850678 SELPH_MODE = 1
6969 09:57:50.854181 PICG_EARLY_EN = 1
6970 09:57:50.857446 VALID_LAT_VALUE = 1
6971 09:57:50.861275 ==============================================================
6972 09:57:50.864314 Enter into Gating configuration >>>>
6973 09:57:50.867188 Exit from Gating configuration <<<<
6974 09:57:50.870602 Enter into DVFS_PRE_config >>>>>
6975 09:57:50.884378 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6976 09:57:50.887470 Exit from DVFS_PRE_config <<<<<
6977 09:57:50.888028 Enter into PICG configuration >>>>
6978 09:57:50.890389 Exit from PICG configuration <<<<
6979 09:57:50.893591 [RX_INPUT] configuration >>>>>
6980 09:57:50.897352 [RX_INPUT] configuration <<<<<
6981 09:57:50.903705 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6982 09:57:50.907264 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6983 09:57:50.914257 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6984 09:57:50.920741 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6985 09:57:50.926825 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6986 09:57:50.933636 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6987 09:57:50.936779 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6988 09:57:50.940091 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6989 09:57:50.943600 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6990 09:57:50.950025 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6991 09:57:50.953125 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6992 09:57:50.956888 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6993 09:57:50.960117 ===================================
6994 09:57:50.963388 LPDDR4 DRAM CONFIGURATION
6995 09:57:50.966464 ===================================
6996 09:57:50.970305 EX_ROW_EN[0] = 0x0
6997 09:57:50.970862 EX_ROW_EN[1] = 0x0
6998 09:57:50.973282 LP4Y_EN = 0x0
6999 09:57:50.973740 WORK_FSP = 0x1
7000 09:57:50.976645 WL = 0x5
7001 09:57:50.977199 RL = 0x5
7002 09:57:50.980099 BL = 0x2
7003 09:57:50.980712 RPST = 0x0
7004 09:57:50.983505 RD_PRE = 0x0
7005 09:57:50.984057 WR_PRE = 0x1
7006 09:57:50.986389 WR_PST = 0x1
7007 09:57:50.986905 DBI_WR = 0x0
7008 09:57:50.989677 DBI_RD = 0x0
7009 09:57:50.990132 OTF = 0x1
7010 09:57:50.993351 ===================================
7011 09:57:50.999707 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7012 09:57:51.002827 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7013 09:57:51.006068 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7014 09:57:51.009228 ===================================
7015 09:57:51.012932 LPDDR4 DRAM CONFIGURATION
7016 09:57:51.016044 ===================================
7017 09:57:51.019552 EX_ROW_EN[0] = 0x10
7018 09:57:51.020107 EX_ROW_EN[1] = 0x0
7019 09:57:51.022965 LP4Y_EN = 0x0
7020 09:57:51.023517 WORK_FSP = 0x1
7021 09:57:51.026029 WL = 0x5
7022 09:57:51.026585 RL = 0x5
7023 09:57:51.029441 BL = 0x2
7024 09:57:51.029997 RPST = 0x0
7025 09:57:51.032534 RD_PRE = 0x0
7026 09:57:51.033101 WR_PRE = 0x1
7027 09:57:51.036110 WR_PST = 0x1
7028 09:57:51.036708 DBI_WR = 0x0
7029 09:57:51.039220 DBI_RD = 0x0
7030 09:57:51.042663 OTF = 0x1
7031 09:57:51.043220 ===================================
7032 09:57:51.049331 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7033 09:57:51.049885 ==
7034 09:57:51.052135 Dram Type= 6, Freq= 0, CH_0, rank 0
7035 09:57:51.059314 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7036 09:57:51.059876 ==
7037 09:57:51.060245 [Duty_Offset_Calibration]
7038 09:57:51.062564 B0:0 B1:2 CA:1
7039 09:57:51.063117
7040 09:57:51.065399 [DutyScan_Calibration_Flow] k_type=0
7041 09:57:51.075053
7042 09:57:51.075604 ==CLK 0==
7043 09:57:51.078563 Final CLK duty delay cell = 0
7044 09:57:51.082068 [0] MAX Duty = 5187%(X100), DQS PI = 24
7045 09:57:51.085293 [0] MIN Duty = 4938%(X100), DQS PI = 52
7046 09:57:51.088334 [0] AVG Duty = 5062%(X100)
7047 09:57:51.088914
7048 09:57:51.091728 CH0 CLK Duty spec in!! Max-Min= 249%
7049 09:57:51.095302 [DutyScan_Calibration_Flow] ====Done====
7050 09:57:51.095879
7051 09:57:51.098463 [DutyScan_Calibration_Flow] k_type=1
7052 09:57:51.114410
7053 09:57:51.114980 ==DQS 0 ==
7054 09:57:51.117683 Final DQS duty delay cell = -4
7055 09:57:51.121066 [-4] MAX Duty = 4969%(X100), DQS PI = 2
7056 09:57:51.124893 [-4] MIN Duty = 4875%(X100), DQS PI = 8
7057 09:57:51.127916 [-4] AVG Duty = 4922%(X100)
7058 09:57:51.128477
7059 09:57:51.128904 ==DQS 1 ==
7060 09:57:51.130973 Final DQS duty delay cell = 0
7061 09:57:51.134344 [0] MAX Duty = 5031%(X100), DQS PI = 0
7062 09:57:51.137985 [0] MIN Duty = 4876%(X100), DQS PI = 18
7063 09:57:51.140930 [0] AVG Duty = 4953%(X100)
7064 09:57:51.141388
7065 09:57:51.144480 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7066 09:57:51.145086
7067 09:57:51.147813 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7068 09:57:51.150941 [DutyScan_Calibration_Flow] ====Done====
7069 09:57:51.151441
7070 09:57:51.154478 [DutyScan_Calibration_Flow] k_type=3
7071 09:57:51.171690
7072 09:57:51.172240 ==DQM 0 ==
7073 09:57:51.174914 Final DQM duty delay cell = 0
7074 09:57:51.178076 [0] MAX Duty = 5187%(X100), DQS PI = 22
7075 09:57:51.181540 [0] MIN Duty = 4907%(X100), DQS PI = 42
7076 09:57:51.184882 [0] AVG Duty = 5047%(X100)
7077 09:57:51.185435
7078 09:57:51.185801 ==DQM 1 ==
7079 09:57:51.188554 Final DQM duty delay cell = 0
7080 09:57:51.191410 [0] MAX Duty = 5031%(X100), DQS PI = 50
7081 09:57:51.194909 [0] MIN Duty = 4782%(X100), DQS PI = 14
7082 09:57:51.198140 [0] AVG Duty = 4906%(X100)
7083 09:57:51.198595
7084 09:57:51.201729 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7085 09:57:51.202308
7086 09:57:51.204687 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7087 09:57:51.207824 [DutyScan_Calibration_Flow] ====Done====
7088 09:57:51.208280
7089 09:57:51.211385 [DutyScan_Calibration_Flow] k_type=2
7090 09:57:51.228000
7091 09:57:51.228592 ==DQ 0 ==
7092 09:57:51.231461 Final DQ duty delay cell = 0
7093 09:57:51.234771 [0] MAX Duty = 5218%(X100), DQS PI = 18
7094 09:57:51.237964 [0] MIN Duty = 4938%(X100), DQS PI = 56
7095 09:57:51.238422 [0] AVG Duty = 5078%(X100)
7096 09:57:51.241467
7097 09:57:51.242022 ==DQ 1 ==
7098 09:57:51.244479 Final DQ duty delay cell = -4
7099 09:57:51.247814 [-4] MAX Duty = 5094%(X100), DQS PI = 4
7100 09:57:51.251208 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7101 09:57:51.254147 [-4] AVG Duty = 4969%(X100)
7102 09:57:51.254605
7103 09:57:51.257545 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7104 09:57:51.258003
7105 09:57:51.261447 CH0 DQ 1 Duty spec in!! Max-Min= 250%
7106 09:57:51.264593 [DutyScan_Calibration_Flow] ====Done====
7107 09:57:51.265153 ==
7108 09:57:51.267949 Dram Type= 6, Freq= 0, CH_1, rank 0
7109 09:57:51.271143 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7110 09:57:51.271705 ==
7111 09:57:51.274468 [Duty_Offset_Calibration]
7112 09:57:51.274923 B0:0 B1:5 CA:-5
7113 09:57:51.275284
7114 09:57:51.277215 [DutyScan_Calibration_Flow] k_type=0
7115 09:57:51.288785
7116 09:57:51.289335 ==CLK 0==
7117 09:57:51.291944 Final CLK duty delay cell = 0
7118 09:57:51.295083 [0] MAX Duty = 5156%(X100), DQS PI = 20
7119 09:57:51.298635 [0] MIN Duty = 4906%(X100), DQS PI = 52
7120 09:57:51.299192 [0] AVG Duty = 5031%(X100)
7121 09:57:51.301662
7122 09:57:51.304939 CH1 CLK Duty spec in!! Max-Min= 250%
7123 09:57:51.308354 [DutyScan_Calibration_Flow] ====Done====
7124 09:57:51.308849
7125 09:57:51.311759 [DutyScan_Calibration_Flow] k_type=1
7126 09:57:51.327671
7127 09:57:51.328241 ==DQS 0 ==
7128 09:57:51.331106 Final DQS duty delay cell = 0
7129 09:57:51.334253 [0] MAX Duty = 5156%(X100), DQS PI = 18
7130 09:57:51.337452 [0] MIN Duty = 4876%(X100), DQS PI = 42
7131 09:57:51.341004 [0] AVG Duty = 5016%(X100)
7132 09:57:51.341564
7133 09:57:51.341931 ==DQS 1 ==
7134 09:57:51.344060 Final DQS duty delay cell = -4
7135 09:57:51.347618 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7136 09:57:51.351095 [-4] MIN Duty = 4844%(X100), DQS PI = 40
7137 09:57:51.353891 [-4] AVG Duty = 4922%(X100)
7138 09:57:51.354347
7139 09:57:51.357094 CH1 DQS 0 Duty spec in!! Max-Min= 280%
7140 09:57:51.357555
7141 09:57:51.360621 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7142 09:57:51.364102 [DutyScan_Calibration_Flow] ====Done====
7143 09:57:51.364698
7144 09:57:51.367288 [DutyScan_Calibration_Flow] k_type=3
7145 09:57:51.383479
7146 09:57:51.384031 ==DQM 0 ==
7147 09:57:51.386517 Final DQM duty delay cell = -4
7148 09:57:51.389897 [-4] MAX Duty = 5093%(X100), DQS PI = 32
7149 09:57:51.393162 [-4] MIN Duty = 4813%(X100), DQS PI = 44
7150 09:57:51.396595 [-4] AVG Duty = 4953%(X100)
7151 09:57:51.397151
7152 09:57:51.397513 ==DQM 1 ==
7153 09:57:51.399800 Final DQM duty delay cell = -4
7154 09:57:51.402870 [-4] MAX Duty = 5062%(X100), DQS PI = 0
7155 09:57:51.406253 [-4] MIN Duty = 4907%(X100), DQS PI = 38
7156 09:57:51.409413 [-4] AVG Duty = 4984%(X100)
7157 09:57:51.409867
7158 09:57:51.412823 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7159 09:57:51.413280
7160 09:57:51.416367 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7161 09:57:51.419846 [DutyScan_Calibration_Flow] ====Done====
7162 09:57:51.420304
7163 09:57:51.422533 [DutyScan_Calibration_Flow] k_type=2
7164 09:57:51.440927
7165 09:57:51.441484 ==DQ 0 ==
7166 09:57:51.443926 Final DQ duty delay cell = 0
7167 09:57:51.447409 [0] MAX Duty = 5093%(X100), DQS PI = 18
7168 09:57:51.450661 [0] MIN Duty = 4938%(X100), DQS PI = 48
7169 09:57:51.451118 [0] AVG Duty = 5015%(X100)
7170 09:57:51.453930
7171 09:57:51.454385 ==DQ 1 ==
7172 09:57:51.457039 Final DQ duty delay cell = 0
7173 09:57:51.460443 [0] MAX Duty = 5031%(X100), DQS PI = 4
7174 09:57:51.464057 [0] MIN Duty = 4907%(X100), DQS PI = 24
7175 09:57:51.464654 [0] AVG Duty = 4969%(X100)
7176 09:57:51.465030
7177 09:57:51.466953 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7178 09:57:51.470233
7179 09:57:51.474013 CH1 DQ 1 Duty spec in!! Max-Min= 124%
7180 09:57:51.476954 [DutyScan_Calibration_Flow] ====Done====
7181 09:57:51.480560 nWR fixed to 30
7182 09:57:51.481121 [ModeRegInit_LP4] CH0 RK0
7183 09:57:51.484030 [ModeRegInit_LP4] CH0 RK1
7184 09:57:51.487148 [ModeRegInit_LP4] CH1 RK0
7185 09:57:51.490470 [ModeRegInit_LP4] CH1 RK1
7186 09:57:51.490936 match AC timing 4
7187 09:57:51.493626 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7188 09:57:51.500181 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7189 09:57:51.503779 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7190 09:57:51.510483 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7191 09:57:51.513768 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7192 09:57:51.514342 [MiockJmeterHQA]
7193 09:57:51.514708
7194 09:57:51.516995 [DramcMiockJmeter] u1RxGatingPI = 0
7195 09:57:51.520498 0 : 4255, 4027
7196 09:57:51.521146 4 : 4363, 4137
7197 09:57:51.521520 8 : 4363, 4138
7198 09:57:51.523551 12 : 4368, 4140
7199 09:57:51.524013 16 : 4368, 4140
7200 09:57:51.526911 20 : 4258, 4029
7201 09:57:51.527476 24 : 4253, 4027
7202 09:57:51.530399 28 : 4253, 4026
7203 09:57:51.530971 32 : 4363, 4137
7204 09:57:51.533971 36 : 4255, 4029
7205 09:57:51.534551 40 : 4253, 4027
7206 09:57:51.534923 44 : 4252, 4027
7207 09:57:51.536589 48 : 4252, 4027
7208 09:57:51.537058 52 : 4252, 4027
7209 09:57:51.540552 56 : 4252, 4027
7210 09:57:51.541125 60 : 4363, 4137
7211 09:57:51.543735 64 : 4366, 4140
7212 09:57:51.544305 68 : 4366, 4139
7213 09:57:51.546765 72 : 4255, 4029
7214 09:57:51.547226 76 : 4252, 4030
7215 09:57:51.547597 80 : 4250, 4026
7216 09:57:51.550043 84 : 4361, 4137
7217 09:57:51.550512 88 : 4252, 4029
7218 09:57:51.553485 92 : 4253, 4029
7219 09:57:51.554007 96 : 4250, 4027
7220 09:57:51.556580 100 : 4250, 2504
7221 09:57:51.557086 104 : 4363, 0
7222 09:57:51.557462 108 : 4363, 0
7223 09:57:51.560406 112 : 4250, 0
7224 09:57:51.561024 116 : 4250, 0
7225 09:57:51.563857 120 : 4366, 0
7226 09:57:51.564421 124 : 4250, 0
7227 09:57:51.564870 128 : 4250, 0
7228 09:57:51.567266 132 : 4250, 0
7229 09:57:51.567826 136 : 4253, 0
7230 09:57:51.568201 140 : 4250, 0
7231 09:57:51.570431 144 : 4360, 0
7232 09:57:51.570991 148 : 4250, 0
7233 09:57:51.573280 152 : 4361, 0
7234 09:57:51.573743 156 : 4361, 0
7235 09:57:51.574113 160 : 4250, 0
7236 09:57:51.576940 164 : 4249, 0
7237 09:57:51.577499 168 : 4250, 0
7238 09:57:51.580006 172 : 4250, 0
7239 09:57:51.580606 176 : 4250, 0
7240 09:57:51.580989 180 : 4250, 0
7241 09:57:51.583611 184 : 4255, 0
7242 09:57:51.584177 188 : 4252, 0
7243 09:57:51.586929 192 : 4250, 0
7244 09:57:51.587518 196 : 4250, 0
7245 09:57:51.587895 200 : 4252, 0
7246 09:57:51.590145 204 : 4363, 0
7247 09:57:51.590607 208 : 4361, 0
7248 09:57:51.593347 212 : 4247, 0
7249 09:57:51.593907 216 : 4251, 0
7250 09:57:51.594280 220 : 4250, 803
7251 09:57:51.596471 224 : 4253, 3976
7252 09:57:51.596971 228 : 4361, 4138
7253 09:57:51.600365 232 : 4252, 4029
7254 09:57:51.600979 236 : 4250, 4026
7255 09:57:51.603380 240 : 4249, 4027
7256 09:57:51.603944 244 : 4361, 4138
7257 09:57:51.606581 248 : 4250, 4026
7258 09:57:51.607276 252 : 4250, 4027
7259 09:57:51.609918 256 : 4361, 4137
7260 09:57:51.610384 260 : 4250, 4027
7261 09:57:51.613290 264 : 4250, 4026
7262 09:57:51.613754 268 : 4250, 4027
7263 09:57:51.614119 272 : 4253, 4029
7264 09:57:51.616335 276 : 4253, 4029
7265 09:57:51.616851 280 : 4250, 4027
7266 09:57:51.620117 284 : 4250, 4026
7267 09:57:51.620734 288 : 4252, 4029
7268 09:57:51.623665 292 : 4249, 4027
7269 09:57:51.624227 296 : 4363, 4139
7270 09:57:51.626920 300 : 4250, 4026
7271 09:57:51.627379 304 : 4250, 4027
7272 09:57:51.630058 308 : 4360, 4138
7273 09:57:51.630623 312 : 4250, 4026
7274 09:57:51.633246 316 : 4250, 4026
7275 09:57:51.633709 320 : 4363, 4140
7276 09:57:51.636565 324 : 4361, 4137
7277 09:57:51.637135 328 : 4250, 4027
7278 09:57:51.637508 332 : 4360, 4137
7279 09:57:51.639579 336 : 4250, 3947
7280 09:57:51.640152 340 : 4250, 1830
7281 09:57:51.640570
7282 09:57:51.643079 MIOCK jitter meter ch=0
7283 09:57:51.643632
7284 09:57:51.646404 1T = (340-104) = 236 dly cells
7285 09:57:51.653059 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7286 09:57:51.653618 ==
7287 09:57:51.656237 Dram Type= 6, Freq= 0, CH_0, rank 0
7288 09:57:51.659798 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7289 09:57:51.660357 ==
7290 09:57:51.666214 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7291 09:57:51.669907 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7292 09:57:51.673380 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7293 09:57:51.679780 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7294 09:57:51.687995 [CA 0] Center 41 (11~72) winsize 62
7295 09:57:51.691193 [CA 1] Center 41 (11~72) winsize 62
7296 09:57:51.694460 [CA 2] Center 37 (7~67) winsize 61
7297 09:57:51.697716 [CA 3] Center 37 (7~67) winsize 61
7298 09:57:51.700795 [CA 4] Center 35 (5~66) winsize 62
7299 09:57:51.704443 [CA 5] Center 35 (5~65) winsize 61
7300 09:57:51.705072
7301 09:57:51.707412 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7302 09:57:51.708020
7303 09:57:51.710876 [CATrainingPosCal] consider 1 rank data
7304 09:57:51.714067 u2DelayCellTimex100 = 275/100 ps
7305 09:57:51.717685 CA0 delay=41 (11~72),Diff = 6 PI (21 cell)
7306 09:57:51.724197 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7307 09:57:51.727511 CA2 delay=37 (7~67),Diff = 2 PI (7 cell)
7308 09:57:51.730987 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7309 09:57:51.734284 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7310 09:57:51.737284 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7311 09:57:51.737902
7312 09:57:51.740636 CA PerBit enable=1, Macro0, CA PI delay=35
7313 09:57:51.741144
7314 09:57:51.744184 [CBTSetCACLKResult] CA Dly = 35
7315 09:57:51.747587 CS Dly: 11 (0~42)
7316 09:57:51.750853 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7317 09:57:51.754094 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7318 09:57:51.754551 ==
7319 09:57:51.757169 Dram Type= 6, Freq= 0, CH_0, rank 1
7320 09:57:51.761124 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7321 09:57:51.764575 ==
7322 09:57:51.767493 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7323 09:57:51.770536 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7324 09:57:51.777319 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7325 09:57:51.783767 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7326 09:57:51.790384 [CA 0] Center 42 (12~73) winsize 62
7327 09:57:51.794099 [CA 1] Center 42 (12~73) winsize 62
7328 09:57:51.796880 [CA 2] Center 38 (9~68) winsize 60
7329 09:57:51.800434 [CA 3] Center 38 (9~67) winsize 59
7330 09:57:51.804021 [CA 4] Center 36 (6~66) winsize 61
7331 09:57:51.806845 [CA 5] Center 36 (6~66) winsize 61
7332 09:57:51.807578
7333 09:57:51.810359 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7334 09:57:51.810818
7335 09:57:51.813794 [CATrainingPosCal] consider 2 rank data
7336 09:57:51.817046 u2DelayCellTimex100 = 275/100 ps
7337 09:57:51.820290 CA0 delay=42 (12~72),Diff = 7 PI (24 cell)
7338 09:57:51.827026 CA1 delay=42 (12~72),Diff = 7 PI (24 cell)
7339 09:57:51.830441 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7340 09:57:51.833562 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7341 09:57:51.837102 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7342 09:57:51.840261 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7343 09:57:51.840951
7344 09:57:51.843352 CA PerBit enable=1, Macro0, CA PI delay=35
7345 09:57:51.843754
7346 09:57:51.846820 [CBTSetCACLKResult] CA Dly = 35
7347 09:57:51.849926 CS Dly: 11 (0~42)
7348 09:57:51.853131 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7349 09:57:51.856613 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7350 09:57:51.857069
7351 09:57:51.859773 ----->DramcWriteLeveling(PI) begin...
7352 09:57:51.860232 ==
7353 09:57:51.863421 Dram Type= 6, Freq= 0, CH_0, rank 0
7354 09:57:51.870122 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7355 09:57:51.870647 ==
7356 09:57:51.873510 Write leveling (Byte 0): 29 => 29
7357 09:57:51.876849 Write leveling (Byte 1): 26 => 26
7358 09:57:51.877264 DramcWriteLeveling(PI) end<-----
7359 09:57:51.877592
7360 09:57:51.879627 ==
7361 09:57:51.883351 Dram Type= 6, Freq= 0, CH_0, rank 0
7362 09:57:51.886343 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7363 09:57:51.886756 ==
7364 09:57:51.890043 [Gating] SW mode calibration
7365 09:57:51.896671 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7366 09:57:51.899898 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7367 09:57:51.906463 0 12 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7368 09:57:51.909544 0 12 4 | B1->B0 | 2424 3434 | 0 1 | (0 0) (0 0)
7369 09:57:51.912940 0 12 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
7370 09:57:51.919758 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7371 09:57:51.923184 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7372 09:57:51.926087 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7373 09:57:51.932908 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7374 09:57:51.936733 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7375 09:57:51.939621 0 13 0 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
7376 09:57:51.946470 0 13 4 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (1 0)
7377 09:57:51.949404 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7378 09:57:51.953059 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7379 09:57:51.959453 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7380 09:57:51.963322 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7381 09:57:51.966534 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7382 09:57:51.969495 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7383 09:57:51.976274 0 14 0 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
7384 09:57:51.979661 0 14 4 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
7385 09:57:51.982966 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7386 09:57:51.989440 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7387 09:57:51.992649 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7388 09:57:51.996217 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7389 09:57:52.002823 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7390 09:57:52.005789 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7391 09:57:52.009231 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7392 09:57:52.016141 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7393 09:57:52.019601 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7394 09:57:52.023022 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7395 09:57:52.029201 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7396 09:57:52.032740 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7397 09:57:52.036243 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7398 09:57:52.042776 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7399 09:57:52.045560 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7400 09:57:52.049241 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7401 09:57:52.055536 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7402 09:57:52.058524 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7403 09:57:52.062440 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7404 09:57:52.069226 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7405 09:57:52.072302 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7406 09:57:52.075735 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7407 09:57:52.082299 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7408 09:57:52.085288 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7409 09:57:52.088778 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7410 09:57:52.092148 Total UI for P1: 0, mck2ui 16
7411 09:57:52.095350 best dqsien dly found for B0: ( 1, 1, 0)
7412 09:57:52.098777 Total UI for P1: 0, mck2ui 16
7413 09:57:52.102083 best dqsien dly found for B1: ( 1, 1, 2)
7414 09:57:52.105340 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7415 09:57:52.108273 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7416 09:57:52.108837
7417 09:57:52.115331 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7418 09:57:52.118441 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7419 09:57:52.118990 [Gating] SW calibration Done
7420 09:57:52.121726 ==
7421 09:57:52.125291 Dram Type= 6, Freq= 0, CH_0, rank 0
7422 09:57:52.128564 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7423 09:57:52.129120 ==
7424 09:57:52.129483 RX Vref Scan: 0
7425 09:57:52.129812
7426 09:57:52.131788 RX Vref 0 -> 0, step: 1
7427 09:57:52.132338
7428 09:57:52.135019 RX Delay 0 -> 252, step: 8
7429 09:57:52.138387 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7430 09:57:52.141800 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7431 09:57:52.145175 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
7432 09:57:52.151506 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7433 09:57:52.154853 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7434 09:57:52.158107 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7435 09:57:52.161661 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7436 09:57:52.164802 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7437 09:57:52.171351 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7438 09:57:52.174609 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7439 09:57:52.177829 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7440 09:57:52.181492 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7441 09:57:52.184729 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7442 09:57:52.191215 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7443 09:57:52.194800 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7444 09:57:52.198038 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7445 09:57:52.198594 ==
7446 09:57:52.201475 Dram Type= 6, Freq= 0, CH_0, rank 0
7447 09:57:52.204398 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7448 09:57:52.207821 ==
7449 09:57:52.208372 DQS Delay:
7450 09:57:52.208806 DQS0 = 0, DQS1 = 0
7451 09:57:52.211284 DQM Delay:
7452 09:57:52.211736 DQM0 = 130, DQM1 = 124
7453 09:57:52.214322 DQ Delay:
7454 09:57:52.217565 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =127
7455 09:57:52.220974 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7456 09:57:52.224691 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7457 09:57:52.227991 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7458 09:57:52.228600
7459 09:57:52.228981
7460 09:57:52.229321 ==
7461 09:57:52.230695 Dram Type= 6, Freq= 0, CH_0, rank 0
7462 09:57:52.234616 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7463 09:57:52.235175 ==
7464 09:57:52.237310
7465 09:57:52.237763
7466 09:57:52.238125 TX Vref Scan disable
7467 09:57:52.241205 == TX Byte 0 ==
7468 09:57:52.244423 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7469 09:57:52.247700 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7470 09:57:52.250818 == TX Byte 1 ==
7471 09:57:52.253763 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7472 09:57:52.257080 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7473 09:57:52.257538 ==
7474 09:57:52.260449 Dram Type= 6, Freq= 0, CH_0, rank 0
7475 09:57:52.267079 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7476 09:57:52.267652 ==
7477 09:57:52.279209
7478 09:57:52.282274 TX Vref early break, caculate TX vref
7479 09:57:52.285641 TX Vref=16, minBit 10, minWin=21, winSum=366
7480 09:57:52.289508 TX Vref=18, minBit 8, minWin=22, winSum=377
7481 09:57:52.292914 TX Vref=20, minBit 8, minWin=23, winSum=385
7482 09:57:52.296042 TX Vref=22, minBit 11, minWin=23, winSum=392
7483 09:57:52.299611 TX Vref=24, minBit 7, minWin=24, winSum=404
7484 09:57:52.305855 TX Vref=26, minBit 7, minWin=24, winSum=405
7485 09:57:52.309156 TX Vref=28, minBit 7, minWin=24, winSum=409
7486 09:57:52.312496 TX Vref=30, minBit 1, minWin=24, winSum=406
7487 09:57:52.315899 TX Vref=32, minBit 0, minWin=24, winSum=399
7488 09:57:52.319201 TX Vref=34, minBit 1, minWin=23, winSum=385
7489 09:57:52.326146 [TxChooseVref] Worse bit 7, Min win 24, Win sum 409, Final Vref 28
7490 09:57:52.326784
7491 09:57:52.328966 Final TX Range 0 Vref 28
7492 09:57:52.329422
7493 09:57:52.329796 ==
7494 09:57:52.332048 Dram Type= 6, Freq= 0, CH_0, rank 0
7495 09:57:52.336002 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7496 09:57:52.336613 ==
7497 09:57:52.336992
7498 09:57:52.337329
7499 09:57:52.338857 TX Vref Scan disable
7500 09:57:52.345618 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7501 09:57:52.346172 == TX Byte 0 ==
7502 09:57:52.348854 u2DelayCellOfst[0]=10 cells (3 PI)
7503 09:57:52.352553 u2DelayCellOfst[1]=17 cells (5 PI)
7504 09:57:52.355593 u2DelayCellOfst[2]=10 cells (3 PI)
7505 09:57:52.358520 u2DelayCellOfst[3]=10 cells (3 PI)
7506 09:57:52.362138 u2DelayCellOfst[4]=7 cells (2 PI)
7507 09:57:52.365440 u2DelayCellOfst[5]=0 cells (0 PI)
7508 09:57:52.368473 u2DelayCellOfst[6]=17 cells (5 PI)
7509 09:57:52.372030 u2DelayCellOfst[7]=14 cells (4 PI)
7510 09:57:52.375493 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7511 09:57:52.378973 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7512 09:57:52.381913 == TX Byte 1 ==
7513 09:57:52.382383 u2DelayCellOfst[8]=3 cells (1 PI)
7514 09:57:52.385088 u2DelayCellOfst[9]=0 cells (0 PI)
7515 09:57:52.388760 u2DelayCellOfst[10]=10 cells (3 PI)
7516 09:57:52.392190 u2DelayCellOfst[11]=3 cells (1 PI)
7517 09:57:52.395428 u2DelayCellOfst[12]=14 cells (4 PI)
7518 09:57:52.398754 u2DelayCellOfst[13]=14 cells (4 PI)
7519 09:57:52.401981 u2DelayCellOfst[14]=21 cells (6 PI)
7520 09:57:52.405394 u2DelayCellOfst[15]=14 cells (4 PI)
7521 09:57:52.408572 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7522 09:57:52.415315 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7523 09:57:52.415875 DramC Write-DBI on
7524 09:57:52.416245 ==
7525 09:57:52.418590 Dram Type= 6, Freq= 0, CH_0, rank 0
7526 09:57:52.425187 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7527 09:57:52.425737 ==
7528 09:57:52.426104
7529 09:57:52.426437
7530 09:57:52.426759 TX Vref Scan disable
7531 09:57:52.428772 == TX Byte 0 ==
7532 09:57:52.432033 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7533 09:57:52.435361 == TX Byte 1 ==
7534 09:57:52.438936 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7535 09:57:52.441964 DramC Write-DBI off
7536 09:57:52.442441
7537 09:57:52.442811 [DATLAT]
7538 09:57:52.443145 Freq=1600, CH0 RK0
7539 09:57:52.443470
7540 09:57:52.445048 DATLAT Default: 0xf
7541 09:57:52.445505 0, 0xFFFF, sum = 0
7542 09:57:52.448381 1, 0xFFFF, sum = 0
7543 09:57:52.452406 2, 0xFFFF, sum = 0
7544 09:57:52.453034 3, 0xFFFF, sum = 0
7545 09:57:52.455291 4, 0xFFFF, sum = 0
7546 09:57:52.455799 5, 0xFFFF, sum = 0
7547 09:57:52.458540 6, 0xFFFF, sum = 0
7548 09:57:52.459106 7, 0xFFFF, sum = 0
7549 09:57:52.462368 8, 0xFFFF, sum = 0
7550 09:57:52.462931 9, 0xFFFF, sum = 0
7551 09:57:52.465519 10, 0xFFFF, sum = 0
7552 09:57:52.466081 11, 0xFFFF, sum = 0
7553 09:57:52.468690 12, 0xBFF, sum = 0
7554 09:57:52.469254 13, 0x0, sum = 1
7555 09:57:52.472037 14, 0x0, sum = 2
7556 09:57:52.472644 15, 0x0, sum = 3
7557 09:57:52.475439 16, 0x0, sum = 4
7558 09:57:52.476013 best_step = 14
7559 09:57:52.476377
7560 09:57:52.476758 ==
7561 09:57:52.478374 Dram Type= 6, Freq= 0, CH_0, rank 0
7562 09:57:52.481928 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7563 09:57:52.485192 ==
7564 09:57:52.485775 RX Vref Scan: 1
7565 09:57:52.486155
7566 09:57:52.488746 Set Vref Range= 24 -> 127
7567 09:57:52.489296
7568 09:57:52.491941 RX Vref 24 -> 127, step: 1
7569 09:57:52.492497
7570 09:57:52.492930 RX Delay 11 -> 252, step: 4
7571 09:57:52.493273
7572 09:57:52.495090 Set Vref, RX VrefLevel [Byte0]: 24
7573 09:57:52.498456 [Byte1]: 24
7574 09:57:52.502203
7575 09:57:52.502752 Set Vref, RX VrefLevel [Byte0]: 25
7576 09:57:52.505408 [Byte1]: 25
7577 09:57:52.509618
7578 09:57:52.510171 Set Vref, RX VrefLevel [Byte0]: 26
7579 09:57:52.513008 [Byte1]: 26
7580 09:57:52.517670
7581 09:57:52.518223 Set Vref, RX VrefLevel [Byte0]: 27
7582 09:57:52.520466 [Byte1]: 27
7583 09:57:52.525119
7584 09:57:52.525671 Set Vref, RX VrefLevel [Byte0]: 28
7585 09:57:52.528294 [Byte1]: 28
7586 09:57:52.532540
7587 09:57:52.533111 Set Vref, RX VrefLevel [Byte0]: 29
7588 09:57:52.536091 [Byte1]: 29
7589 09:57:52.540352
7590 09:57:52.540958 Set Vref, RX VrefLevel [Byte0]: 30
7591 09:57:52.543508 [Byte1]: 30
7592 09:57:52.547761
7593 09:57:52.548315 Set Vref, RX VrefLevel [Byte0]: 31
7594 09:57:52.551271 [Byte1]: 31
7595 09:57:52.555651
7596 09:57:52.556110 Set Vref, RX VrefLevel [Byte0]: 32
7597 09:57:52.558533 [Byte1]: 32
7598 09:57:52.563200
7599 09:57:52.563752 Set Vref, RX VrefLevel [Byte0]: 33
7600 09:57:52.566887 [Byte1]: 33
7601 09:57:52.570942
7602 09:57:52.571495 Set Vref, RX VrefLevel [Byte0]: 34
7603 09:57:52.574242 [Byte1]: 34
7604 09:57:52.578146
7605 09:57:52.578700 Set Vref, RX VrefLevel [Byte0]: 35
7606 09:57:52.581587 [Byte1]: 35
7607 09:57:52.585809
7608 09:57:52.586364 Set Vref, RX VrefLevel [Byte0]: 36
7609 09:57:52.589091 [Byte1]: 36
7610 09:57:52.593493
7611 09:57:52.594061 Set Vref, RX VrefLevel [Byte0]: 37
7612 09:57:52.596480 [Byte1]: 37
7613 09:57:52.601351
7614 09:57:52.601904 Set Vref, RX VrefLevel [Byte0]: 38
7615 09:57:52.604361 [Byte1]: 38
7616 09:57:52.608828
7617 09:57:52.609282 Set Vref, RX VrefLevel [Byte0]: 39
7618 09:57:52.611594 [Byte1]: 39
7619 09:57:52.616447
7620 09:57:52.616941 Set Vref, RX VrefLevel [Byte0]: 40
7621 09:57:52.619487 [Byte1]: 40
7622 09:57:52.624056
7623 09:57:52.624659 Set Vref, RX VrefLevel [Byte0]: 41
7624 09:57:52.627576 [Byte1]: 41
7625 09:57:52.631554
7626 09:57:52.632106 Set Vref, RX VrefLevel [Byte0]: 42
7627 09:57:52.635059 [Byte1]: 42
7628 09:57:52.638999
7629 09:57:52.639550 Set Vref, RX VrefLevel [Byte0]: 43
7630 09:57:52.642216 [Byte1]: 43
7631 09:57:52.646684
7632 09:57:52.647246 Set Vref, RX VrefLevel [Byte0]: 44
7633 09:57:52.649912 [Byte1]: 44
7634 09:57:52.654281
7635 09:57:52.654906 Set Vref, RX VrefLevel [Byte0]: 45
7636 09:57:52.657846 [Byte1]: 45
7637 09:57:52.661810
7638 09:57:52.662266 Set Vref, RX VrefLevel [Byte0]: 46
7639 09:57:52.665064 [Byte1]: 46
7640 09:57:52.669778
7641 09:57:52.670345 Set Vref, RX VrefLevel [Byte0]: 47
7642 09:57:52.672642 [Byte1]: 47
7643 09:57:52.677262
7644 09:57:52.677813 Set Vref, RX VrefLevel [Byte0]: 48
7645 09:57:52.681009 [Byte1]: 48
7646 09:57:52.684462
7647 09:57:52.684966 Set Vref, RX VrefLevel [Byte0]: 49
7648 09:57:52.687970 [Byte1]: 49
7649 09:57:52.692205
7650 09:57:52.692791 Set Vref, RX VrefLevel [Byte0]: 50
7651 09:57:52.695876 [Byte1]: 50
7652 09:57:52.699884
7653 09:57:52.700302 Set Vref, RX VrefLevel [Byte0]: 51
7654 09:57:52.703227 [Byte1]: 51
7655 09:57:52.707722
7656 09:57:52.708279 Set Vref, RX VrefLevel [Byte0]: 52
7657 09:57:52.710662 [Byte1]: 52
7658 09:57:52.714990
7659 09:57:52.715489 Set Vref, RX VrefLevel [Byte0]: 53
7660 09:57:52.718608 [Byte1]: 53
7661 09:57:52.722802
7662 09:57:52.723358 Set Vref, RX VrefLevel [Byte0]: 54
7663 09:57:52.726097 [Byte1]: 54
7664 09:57:52.730588
7665 09:57:52.731142 Set Vref, RX VrefLevel [Byte0]: 55
7666 09:57:52.733819 [Byte1]: 55
7667 09:57:52.738410
7668 09:57:52.738963 Set Vref, RX VrefLevel [Byte0]: 56
7669 09:57:52.741323 [Byte1]: 56
7670 09:57:52.745611
7671 09:57:52.746168 Set Vref, RX VrefLevel [Byte0]: 57
7672 09:57:52.749392 [Byte1]: 57
7673 09:57:52.753294
7674 09:57:52.753891 Set Vref, RX VrefLevel [Byte0]: 58
7675 09:57:52.756583 [Byte1]: 58
7676 09:57:52.760584
7677 09:57:52.761058 Set Vref, RX VrefLevel [Byte0]: 59
7678 09:57:52.764339 [Byte1]: 59
7679 09:57:52.768483
7680 09:57:52.769094 Set Vref, RX VrefLevel [Byte0]: 60
7681 09:57:52.771872 [Byte1]: 60
7682 09:57:52.776063
7683 09:57:52.776539 Set Vref, RX VrefLevel [Byte0]: 61
7684 09:57:52.779487 [Byte1]: 61
7685 09:57:52.783888
7686 09:57:52.784468 Set Vref, RX VrefLevel [Byte0]: 62
7687 09:57:52.787059 [Byte1]: 62
7688 09:57:52.791583
7689 09:57:52.792137 Set Vref, RX VrefLevel [Byte0]: 63
7690 09:57:52.794865 [Byte1]: 63
7691 09:57:52.798972
7692 09:57:52.799527 Set Vref, RX VrefLevel [Byte0]: 64
7693 09:57:52.802350 [Byte1]: 64
7694 09:57:52.806827
7695 09:57:52.807391 Set Vref, RX VrefLevel [Byte0]: 65
7696 09:57:52.809844 [Byte1]: 65
7697 09:57:52.814311
7698 09:57:52.814860 Set Vref, RX VrefLevel [Byte0]: 66
7699 09:57:52.817222 [Byte1]: 66
7700 09:57:52.821861
7701 09:57:52.822416 Set Vref, RX VrefLevel [Byte0]: 67
7702 09:57:52.825101 [Byte1]: 67
7703 09:57:52.829478
7704 09:57:52.830040 Set Vref, RX VrefLevel [Byte0]: 68
7705 09:57:52.833010 [Byte1]: 68
7706 09:57:52.837367
7707 09:57:52.837922 Set Vref, RX VrefLevel [Byte0]: 69
7708 09:57:52.840342 [Byte1]: 69
7709 09:57:52.844763
7710 09:57:52.845320 Set Vref, RX VrefLevel [Byte0]: 70
7711 09:57:52.847867 [Byte1]: 70
7712 09:57:52.852172
7713 09:57:52.852778 Set Vref, RX VrefLevel [Byte0]: 71
7714 09:57:52.855263 [Byte1]: 71
7715 09:57:52.859744
7716 09:57:52.860294 Final RX Vref Byte 0 = 53 to rank0
7717 09:57:52.863232 Final RX Vref Byte 1 = 57 to rank0
7718 09:57:52.866576 Final RX Vref Byte 0 = 53 to rank1
7719 09:57:52.869905 Final RX Vref Byte 1 = 57 to rank1==
7720 09:57:52.873230 Dram Type= 6, Freq= 0, CH_0, rank 0
7721 09:57:52.880031 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7722 09:57:52.880625 ==
7723 09:57:52.880993 DQS Delay:
7724 09:57:52.881327 DQS0 = 0, DQS1 = 0
7725 09:57:52.883303 DQM Delay:
7726 09:57:52.883857 DQM0 = 126, DQM1 = 121
7727 09:57:52.886711 DQ Delay:
7728 09:57:52.889768 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7729 09:57:52.893494 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7730 09:57:52.896545 DQ8 =110, DQ9 =106, DQ10 =122, DQ11 =112
7731 09:57:52.899720 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7732 09:57:52.900271
7733 09:57:52.900695
7734 09:57:52.901043
7735 09:57:52.902824 [DramC_TX_OE_Calibration] TA2
7736 09:57:52.906557 Original DQ_B0 (3 6) =30, OEN = 27
7737 09:57:52.909743 Original DQ_B1 (3 6) =30, OEN = 27
7738 09:57:52.913038 24, 0x0, End_B0=24 End_B1=24
7739 09:57:52.913633 25, 0x0, End_B0=25 End_B1=25
7740 09:57:52.915935 26, 0x0, End_B0=26 End_B1=26
7741 09:57:52.919582 27, 0x0, End_B0=27 End_B1=27
7742 09:57:52.923288 28, 0x0, End_B0=28 End_B1=28
7743 09:57:52.926257 29, 0x0, End_B0=29 End_B1=29
7744 09:57:52.926820 30, 0x0, End_B0=30 End_B1=30
7745 09:57:52.929522 31, 0x5151, End_B0=30 End_B1=30
7746 09:57:52.933010 Byte0 end_step=30 best_step=27
7747 09:57:52.936335 Byte1 end_step=30 best_step=27
7748 09:57:52.939759 Byte0 TX OE(2T, 0.5T) = (3, 3)
7749 09:57:52.942842 Byte1 TX OE(2T, 0.5T) = (3, 3)
7750 09:57:52.943408
7751 09:57:52.943777
7752 09:57:52.949676 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
7753 09:57:52.952921 CH0 RK0: MR19=303, MR18=1B1B
7754 09:57:52.959394 CH0_RK0: MR19=0x303, MR18=0x1B1B, DQSOSC=396, MR23=63, INC=23, DEC=15
7755 09:57:52.959998
7756 09:57:52.962975 ----->DramcWriteLeveling(PI) begin...
7757 09:57:52.963537 ==
7758 09:57:52.966096 Dram Type= 6, Freq= 0, CH_0, rank 1
7759 09:57:52.969328 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7760 09:57:52.969891 ==
7761 09:57:52.972935 Write leveling (Byte 0): 29 => 29
7762 09:57:52.975984 Write leveling (Byte 1): 26 => 26
7763 09:57:52.979300 DramcWriteLeveling(PI) end<-----
7764 09:57:52.979859
7765 09:57:52.980219 ==
7766 09:57:52.982826 Dram Type= 6, Freq= 0, CH_0, rank 1
7767 09:57:52.985956 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7768 09:57:52.986514 ==
7769 09:57:52.989487 [Gating] SW mode calibration
7770 09:57:52.996201 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7771 09:57:53.002277 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7772 09:57:53.005995 0 12 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7773 09:57:53.009128 0 12 4 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
7774 09:57:53.015609 0 12 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7775 09:57:53.019104 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7776 09:57:53.022364 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7777 09:57:53.029151 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7778 09:57:53.032538 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7779 09:57:53.035896 0 12 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7780 09:57:53.042569 0 13 0 | B1->B0 | 3434 2b2b | 1 1 | (1 0) (1 0)
7781 09:57:53.045753 0 13 4 | B1->B0 | 3131 2323 | 0 0 | (1 0) (0 0)
7782 09:57:53.049047 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7783 09:57:53.055941 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7784 09:57:53.058820 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7785 09:57:53.061991 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7786 09:57:53.068763 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7787 09:57:53.072195 0 13 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7788 09:57:53.075981 0 14 0 | B1->B0 | 2323 3f3f | 0 1 | (0 0) (0 0)
7789 09:57:53.082158 0 14 4 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
7790 09:57:53.085407 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7791 09:57:53.089068 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7792 09:57:53.095383 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7793 09:57:53.099492 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7794 09:57:53.102491 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7795 09:57:53.108727 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7796 09:57:53.112084 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7797 09:57:53.115677 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7798 09:57:53.121994 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7799 09:57:53.125235 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7800 09:57:53.128712 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7801 09:57:53.135321 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7802 09:57:53.138682 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7803 09:57:53.142138 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7804 09:57:53.148485 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7805 09:57:53.151864 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7806 09:57:53.155193 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7807 09:57:53.161806 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7808 09:57:53.164967 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7809 09:57:53.168112 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7810 09:57:53.175000 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7811 09:57:53.178126 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7812 09:57:53.181630 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7813 09:57:53.188414 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7814 09:57:53.189021 Total UI for P1: 0, mck2ui 16
7815 09:57:53.192037 best dqsien dly found for B0: ( 1, 0, 30)
7816 09:57:53.198129 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7817 09:57:53.201457 Total UI for P1: 0, mck2ui 16
7818 09:57:53.204783 best dqsien dly found for B1: ( 1, 1, 2)
7819 09:57:53.208243 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7820 09:57:53.211547 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7821 09:57:53.212120
7822 09:57:53.214374 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7823 09:57:53.217670 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7824 09:57:53.221122 [Gating] SW calibration Done
7825 09:57:53.221687 ==
7826 09:57:53.224495 Dram Type= 6, Freq= 0, CH_0, rank 1
7827 09:57:53.227759 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7828 09:57:53.228219 ==
7829 09:57:53.230970 RX Vref Scan: 0
7830 09:57:53.231423
7831 09:57:53.234523 RX Vref 0 -> 0, step: 1
7832 09:57:53.235079
7833 09:57:53.235441 RX Delay 0 -> 252, step: 8
7834 09:57:53.241164 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7835 09:57:53.244595 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7836 09:57:53.247881 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7837 09:57:53.250989 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7838 09:57:53.254323 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7839 09:57:53.260964 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7840 09:57:53.264125 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7841 09:57:53.267853 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7842 09:57:53.270923 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7843 09:57:53.274484 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7844 09:57:53.280792 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7845 09:57:53.284099 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7846 09:57:53.287736 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7847 09:57:53.291002 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7848 09:57:53.294037 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7849 09:57:53.300944 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7850 09:57:53.301507 ==
7851 09:57:53.304012 Dram Type= 6, Freq= 0, CH_0, rank 1
7852 09:57:53.307410 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7853 09:57:53.307973 ==
7854 09:57:53.308345 DQS Delay:
7855 09:57:53.310674 DQS0 = 0, DQS1 = 0
7856 09:57:53.311233 DQM Delay:
7857 09:57:53.313955 DQM0 = 131, DQM1 = 124
7858 09:57:53.314513 DQ Delay:
7859 09:57:53.316966 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =127
7860 09:57:53.320882 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7861 09:57:53.323898 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7862 09:57:53.327173 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7863 09:57:53.327590
7864 09:57:53.330329
7865 09:57:53.330782 ==
7866 09:57:53.333825 Dram Type= 6, Freq= 0, CH_0, rank 1
7867 09:57:53.336824 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7868 09:57:53.337287 ==
7869 09:57:53.337651
7870 09:57:53.337987
7871 09:57:53.340659 TX Vref Scan disable
7872 09:57:53.341218 == TX Byte 0 ==
7873 09:57:53.346927 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7874 09:57:53.350392 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7875 09:57:53.350954 == TX Byte 1 ==
7876 09:57:53.356708 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7877 09:57:53.360253 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7878 09:57:53.360921 ==
7879 09:57:53.363495 Dram Type= 6, Freq= 0, CH_0, rank 1
7880 09:57:53.366601 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7881 09:57:53.367158 ==
7882 09:57:53.381593
7883 09:57:53.386403 TX Vref early break, caculate TX vref
7884 09:57:53.388079 TX Vref=16, minBit 1, minWin=21, winSum=366
7885 09:57:53.391443 TX Vref=18, minBit 1, minWin=22, winSum=375
7886 09:57:53.395103 TX Vref=20, minBit 1, minWin=22, winSum=382
7887 09:57:53.398170 TX Vref=22, minBit 1, minWin=23, winSum=393
7888 09:57:53.401410 TX Vref=24, minBit 1, minWin=23, winSum=397
7889 09:57:53.408213 TX Vref=26, minBit 1, minWin=24, winSum=399
7890 09:57:53.411175 TX Vref=28, minBit 4, minWin=24, winSum=408
7891 09:57:53.414925 TX Vref=30, minBit 0, minWin=25, winSum=406
7892 09:57:53.417800 TX Vref=32, minBit 0, minWin=24, winSum=395
7893 09:57:53.421093 TX Vref=34, minBit 7, minWin=23, winSum=389
7894 09:57:53.424648 TX Vref=36, minBit 7, minWin=22, winSum=380
7895 09:57:53.431187 [TxChooseVref] Worse bit 0, Min win 25, Win sum 406, Final Vref 30
7896 09:57:53.431750
7897 09:57:53.434665 Final TX Range 0 Vref 30
7898 09:57:53.435227
7899 09:57:53.435591 ==
7900 09:57:53.437854 Dram Type= 6, Freq= 0, CH_0, rank 1
7901 09:57:53.440873 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7902 09:57:53.441335 ==
7903 09:57:53.441697
7904 09:57:53.444348
7905 09:57:53.444949 TX Vref Scan disable
7906 09:57:53.451098 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7907 09:57:53.451660 == TX Byte 0 ==
7908 09:57:53.454075 u2DelayCellOfst[0]=14 cells (4 PI)
7909 09:57:53.457316 u2DelayCellOfst[1]=14 cells (4 PI)
7910 09:57:53.461089 u2DelayCellOfst[2]=10 cells (3 PI)
7911 09:57:53.464054 u2DelayCellOfst[3]=10 cells (3 PI)
7912 09:57:53.467424 u2DelayCellOfst[4]=7 cells (2 PI)
7913 09:57:53.470726 u2DelayCellOfst[5]=0 cells (0 PI)
7914 09:57:53.474132 u2DelayCellOfst[6]=17 cells (5 PI)
7915 09:57:53.477393 u2DelayCellOfst[7]=14 cells (4 PI)
7916 09:57:53.480744 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7917 09:57:53.484346 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7918 09:57:53.487526 == TX Byte 1 ==
7919 09:57:53.490916 u2DelayCellOfst[8]=3 cells (1 PI)
7920 09:57:53.494156 u2DelayCellOfst[9]=0 cells (0 PI)
7921 09:57:53.497864 u2DelayCellOfst[10]=14 cells (4 PI)
7922 09:57:53.498442 u2DelayCellOfst[11]=10 cells (3 PI)
7923 09:57:53.501022 u2DelayCellOfst[12]=17 cells (5 PI)
7924 09:57:53.504324 u2DelayCellOfst[13]=17 cells (5 PI)
7925 09:57:53.507633 u2DelayCellOfst[14]=21 cells (6 PI)
7926 09:57:53.511092 u2DelayCellOfst[15]=17 cells (5 PI)
7927 09:57:53.517068 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7928 09:57:53.520583 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7929 09:57:53.521048 DramC Write-DBI on
7930 09:57:53.521412 ==
7931 09:57:53.524022 Dram Type= 6, Freq= 0, CH_0, rank 1
7932 09:57:53.530704 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7933 09:57:53.531264 ==
7934 09:57:53.531633
7935 09:57:53.531967
7936 09:57:53.533832 TX Vref Scan disable
7937 09:57:53.534388 == TX Byte 0 ==
7938 09:57:53.540772 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7939 09:57:53.541331 == TX Byte 1 ==
7940 09:57:53.543974 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7941 09:57:53.547141 DramC Write-DBI off
7942 09:57:53.547705
7943 09:57:53.548072 [DATLAT]
7944 09:57:53.550071 Freq=1600, CH0 RK1
7945 09:57:53.550471
7946 09:57:53.550814 DATLAT Default: 0xe
7947 09:57:53.553469 0, 0xFFFF, sum = 0
7948 09:57:53.553933 1, 0xFFFF, sum = 0
7949 09:57:53.556842 2, 0xFFFF, sum = 0
7950 09:57:53.557332 3, 0xFFFF, sum = 0
7951 09:57:53.560060 4, 0xFFFF, sum = 0
7952 09:57:53.560562 5, 0xFFFF, sum = 0
7953 09:57:53.563290 6, 0xFFFF, sum = 0
7954 09:57:53.563751 7, 0xFFFF, sum = 0
7955 09:57:53.567066 8, 0xFFFF, sum = 0
7956 09:57:53.567630 9, 0xFFFF, sum = 0
7957 09:57:53.570003 10, 0xFFFF, sum = 0
7958 09:57:53.573803 11, 0xFFFF, sum = 0
7959 09:57:53.574363 12, 0x8FFF, sum = 0
7960 09:57:53.577025 13, 0x0, sum = 1
7961 09:57:53.577586 14, 0x0, sum = 2
7962 09:57:53.580099 15, 0x0, sum = 3
7963 09:57:53.580732 16, 0x0, sum = 4
7964 09:57:53.581133 best_step = 14
7965 09:57:53.581469
7966 09:57:53.583429 ==
7967 09:57:53.586780 Dram Type= 6, Freq= 0, CH_0, rank 1
7968 09:57:53.589810 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7969 09:57:53.590268 ==
7970 09:57:53.590633 RX Vref Scan: 0
7971 09:57:53.590971
7972 09:57:53.593467 RX Vref 0 -> 0, step: 1
7973 09:57:53.593994
7974 09:57:53.596892 RX Delay 11 -> 252, step: 4
7975 09:57:53.600224 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7976 09:57:53.603474 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7977 09:57:53.610292 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7978 09:57:53.613420 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7979 09:57:53.616891 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
7980 09:57:53.619933 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
7981 09:57:53.623425 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7982 09:57:53.630115 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7983 09:57:53.633060 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7984 09:57:53.636548 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7985 09:57:53.639973 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7986 09:57:53.643471 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7987 09:57:53.650201 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7988 09:57:53.653304 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
7989 09:57:53.656629 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
7990 09:57:53.660273 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
7991 09:57:53.660896 ==
7992 09:57:53.663098 Dram Type= 6, Freq= 0, CH_0, rank 1
7993 09:57:53.669678 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7994 09:57:53.670240 ==
7995 09:57:53.670609 DQS Delay:
7996 09:57:53.673103 DQS0 = 0, DQS1 = 0
7997 09:57:53.673658 DQM Delay:
7998 09:57:53.676894 DQM0 = 129, DQM1 = 120
7999 09:57:53.677451 DQ Delay:
8000 09:57:53.679846 DQ0 =124, DQ1 =132, DQ2 =126, DQ3 =124
8001 09:57:53.683201 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =138
8002 09:57:53.686405 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
8003 09:57:53.689673 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =132
8004 09:57:53.690232
8005 09:57:53.690595
8006 09:57:53.690927
8007 09:57:53.692860 [DramC_TX_OE_Calibration] TA2
8008 09:57:53.696503 Original DQ_B0 (3 6) =30, OEN = 27
8009 09:57:53.699441 Original DQ_B1 (3 6) =30, OEN = 27
8010 09:57:53.703279 24, 0x0, End_B0=24 End_B1=24
8011 09:57:53.703840 25, 0x0, End_B0=25 End_B1=25
8012 09:57:53.706088 26, 0x0, End_B0=26 End_B1=26
8013 09:57:53.709358 27, 0x0, End_B0=27 End_B1=27
8014 09:57:53.713000 28, 0x0, End_B0=28 End_B1=28
8015 09:57:53.716587 29, 0x0, End_B0=29 End_B1=29
8016 09:57:53.717157 30, 0x0, End_B0=30 End_B1=30
8017 09:57:53.719492 31, 0x4141, End_B0=30 End_B1=30
8018 09:57:53.723107 Byte0 end_step=30 best_step=27
8019 09:57:53.726198 Byte1 end_step=30 best_step=27
8020 09:57:53.729449 Byte0 TX OE(2T, 0.5T) = (3, 3)
8021 09:57:53.732959 Byte1 TX OE(2T, 0.5T) = (3, 3)
8022 09:57:53.733515
8023 09:57:53.733879
8024 09:57:53.739630 [DQSOSCAuto] RK1, (LSB)MR18= 0x2222, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
8025 09:57:53.742685 CH0 RK1: MR19=303, MR18=2222
8026 09:57:53.749336 CH0_RK1: MR19=0x303, MR18=0x2222, DQSOSC=392, MR23=63, INC=24, DEC=16
8027 09:57:53.752663 [RxdqsGatingPostProcess] freq 1600
8028 09:57:53.755919 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8029 09:57:53.759066 Pre-setting of DQS Precalculation
8030 09:57:53.766040 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8031 09:57:53.766597 ==
8032 09:57:53.768899 Dram Type= 6, Freq= 0, CH_1, rank 0
8033 09:57:53.772402 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8034 09:57:53.772993 ==
8035 09:57:53.779244 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8036 09:57:53.782690 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8037 09:57:53.785852 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8038 09:57:53.792331 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8039 09:57:53.801613 [CA 0] Center 41 (11~72) winsize 62
8040 09:57:53.804328 [CA 1] Center 41 (11~72) winsize 62
8041 09:57:53.807908 [CA 2] Center 37 (8~67) winsize 60
8042 09:57:53.811788 [CA 3] Center 36 (7~66) winsize 60
8043 09:57:53.814485 [CA 4] Center 34 (4~64) winsize 61
8044 09:57:53.818160 [CA 5] Center 34 (5~64) winsize 60
8045 09:57:53.818826
8046 09:57:53.820923 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8047 09:57:53.821377
8048 09:57:53.824213 [CATrainingPosCal] consider 1 rank data
8049 09:57:53.827776 u2DelayCellTimex100 = 275/100 ps
8050 09:57:53.831440 CA0 delay=41 (11~72),Diff = 7 PI (24 cell)
8051 09:57:53.837505 CA1 delay=41 (11~72),Diff = 7 PI (24 cell)
8052 09:57:53.841005 CA2 delay=37 (8~67),Diff = 3 PI (10 cell)
8053 09:57:53.844547 CA3 delay=36 (7~66),Diff = 2 PI (7 cell)
8054 09:57:53.847246 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8055 09:57:53.851013 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
8056 09:57:53.851587
8057 09:57:53.854327 CA PerBit enable=1, Macro0, CA PI delay=34
8058 09:57:53.854887
8059 09:57:53.857126 [CBTSetCACLKResult] CA Dly = 34
8060 09:57:53.860584 CS Dly: 8 (0~39)
8061 09:57:53.863915 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8062 09:57:53.867701 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8063 09:57:53.868257 ==
8064 09:57:53.870556 Dram Type= 6, Freq= 0, CH_1, rank 1
8065 09:57:53.874155 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8066 09:57:53.877658 ==
8067 09:57:53.880683 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8068 09:57:53.883949 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8069 09:57:53.890945 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8070 09:57:53.897154 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8071 09:57:53.903484 [CA 0] Center 40 (10~70) winsize 61
8072 09:57:53.906786 [CA 1] Center 39 (9~70) winsize 62
8073 09:57:53.910291 [CA 2] Center 35 (6~65) winsize 60
8074 09:57:53.913724 [CA 3] Center 34 (5~64) winsize 60
8075 09:57:53.916567 [CA 4] Center 33 (3~63) winsize 61
8076 09:57:53.919745 [CA 5] Center 33 (3~63) winsize 61
8077 09:57:53.920201
8078 09:57:53.923185 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8079 09:57:53.923736
8080 09:57:53.926896 [CATrainingPosCal] consider 2 rank data
8081 09:57:53.930043 u2DelayCellTimex100 = 275/100 ps
8082 09:57:53.933078 CA0 delay=40 (11~70),Diff = 7 PI (24 cell)
8083 09:57:53.940151 CA1 delay=40 (11~70),Diff = 7 PI (24 cell)
8084 09:57:53.943049 CA2 delay=36 (8~65),Diff = 3 PI (10 cell)
8085 09:57:53.946493 CA3 delay=35 (7~64),Diff = 2 PI (7 cell)
8086 09:57:53.950062 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8087 09:57:53.953197 CA5 delay=34 (5~63),Diff = 1 PI (3 cell)
8088 09:57:53.953754
8089 09:57:53.956626 CA PerBit enable=1, Macro0, CA PI delay=33
8090 09:57:53.957224
8091 09:57:53.959686 [CBTSetCACLKResult] CA Dly = 33
8092 09:57:53.962913 CS Dly: 9 (0~41)
8093 09:57:53.966318 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8094 09:57:53.969702 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8095 09:57:53.970269
8096 09:57:53.973510 ----->DramcWriteLeveling(PI) begin...
8097 09:57:53.974073 ==
8098 09:57:53.976482 Dram Type= 6, Freq= 0, CH_1, rank 0
8099 09:57:53.979807 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8100 09:57:53.982623 ==
8101 09:57:53.986217 Write leveling (Byte 0): 22 => 22
8102 09:57:53.986676 Write leveling (Byte 1): 20 => 20
8103 09:57:53.989604 DramcWriteLeveling(PI) end<-----
8104 09:57:53.990164
8105 09:57:53.990528 ==
8106 09:57:53.992762 Dram Type= 6, Freq= 0, CH_1, rank 0
8107 09:57:53.999741 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8108 09:57:54.000315 ==
8109 09:57:54.002825 [Gating] SW mode calibration
8110 09:57:54.009344 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8111 09:57:54.012712 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8112 09:57:54.019252 0 12 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
8113 09:57:54.022684 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8114 09:57:54.026158 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8115 09:57:54.032399 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8116 09:57:54.036048 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8117 09:57:54.039424 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8118 09:57:54.045633 0 12 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
8119 09:57:54.049394 0 12 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
8120 09:57:54.052202 0 13 0 | B1->B0 | 3131 2424 | 1 0 | (1 0) (1 0)
8121 09:57:54.058896 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8122 09:57:54.062287 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8123 09:57:54.066066 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8124 09:57:54.069117 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8125 09:57:54.075812 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8126 09:57:54.079007 0 13 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8127 09:57:54.082178 0 13 28 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
8128 09:57:54.089186 0 14 0 | B1->B0 | 3333 4646 | 1 0 | (0 0) (0 0)
8129 09:57:54.092057 0 14 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8130 09:57:54.095558 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8131 09:57:54.102379 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8132 09:57:54.105439 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8133 09:57:54.108879 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8134 09:57:54.115485 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8135 09:57:54.118851 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8136 09:57:54.121839 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8137 09:57:54.128565 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8138 09:57:54.132166 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8139 09:57:54.135422 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8140 09:57:54.141696 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8141 09:57:54.144944 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8142 09:57:54.148229 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8143 09:57:54.155220 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8144 09:57:54.158365 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8145 09:57:54.161401 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8146 09:57:54.168444 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8147 09:57:54.171660 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8148 09:57:54.174625 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8149 09:57:54.181878 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8150 09:57:54.184902 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8151 09:57:54.188316 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8152 09:57:54.194679 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8153 09:57:54.198220 Total UI for P1: 0, mck2ui 16
8154 09:57:54.201096 best dqsien dly found for B0: ( 1, 0, 26)
8155 09:57:54.204626 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8156 09:57:54.208146 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8157 09:57:54.211296 Total UI for P1: 0, mck2ui 16
8158 09:57:54.214880 best dqsien dly found for B1: ( 1, 1, 0)
8159 09:57:54.217951 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8160 09:57:54.221455 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8161 09:57:54.222059
8162 09:57:54.228045 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8163 09:57:54.231161 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8164 09:57:54.231730 [Gating] SW calibration Done
8165 09:57:54.234468 ==
8166 09:57:54.238021 Dram Type= 6, Freq= 0, CH_1, rank 0
8167 09:57:54.241023 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8168 09:57:54.241694 ==
8169 09:57:54.242249 RX Vref Scan: 0
8170 09:57:54.242620
8171 09:57:54.244448 RX Vref 0 -> 0, step: 1
8172 09:57:54.245063
8173 09:57:54.247706 RX Delay 0 -> 252, step: 8
8174 09:57:54.251185 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8175 09:57:54.254508 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8176 09:57:54.258131 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8177 09:57:54.264142 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8178 09:57:54.267789 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8179 09:57:54.271289 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8180 09:57:54.274443 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8181 09:57:54.277575 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8182 09:57:54.284342 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8183 09:57:54.287705 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8184 09:57:54.291143 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8185 09:57:54.294174 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8186 09:57:54.297452 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8187 09:57:54.304022 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8188 09:57:54.307490 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8189 09:57:54.310808 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8190 09:57:54.311384 ==
8191 09:57:54.313876 Dram Type= 6, Freq= 0, CH_1, rank 0
8192 09:57:54.317495 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8193 09:57:54.320787 ==
8194 09:57:54.321405 DQS Delay:
8195 09:57:54.321997 DQS0 = 0, DQS1 = 0
8196 09:57:54.324454 DQM Delay:
8197 09:57:54.324952 DQM0 = 129, DQM1 = 125
8198 09:57:54.327603 DQ Delay:
8199 09:57:54.330666 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8200 09:57:54.334123 DQ4 =127, DQ5 =139, DQ6 =135, DQ7 =127
8201 09:57:54.337397 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8202 09:57:54.340977 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8203 09:57:54.341541
8204 09:57:54.341914
8205 09:57:54.342255 ==
8206 09:57:54.344007 Dram Type= 6, Freq= 0, CH_1, rank 0
8207 09:57:54.347525 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8208 09:57:54.348100 ==
8209 09:57:54.348476
8210 09:57:54.350690
8211 09:57:54.351248 TX Vref Scan disable
8212 09:57:54.354190 == TX Byte 0 ==
8213 09:57:54.357165 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8214 09:57:54.360701 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8215 09:57:54.363434 == TX Byte 1 ==
8216 09:57:54.366969 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8217 09:57:54.370431 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8218 09:57:54.370990 ==
8219 09:57:54.373462 Dram Type= 6, Freq= 0, CH_1, rank 0
8220 09:57:54.380143 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8221 09:57:54.380741 ==
8222 09:57:54.391473
8223 09:57:54.395195 TX Vref early break, caculate TX vref
8224 09:57:54.398535 TX Vref=16, minBit 0, minWin=22, winSum=371
8225 09:57:54.401409 TX Vref=18, minBit 1, minWin=22, winSum=379
8226 09:57:54.405135 TX Vref=20, minBit 1, minWin=23, winSum=390
8227 09:57:54.407997 TX Vref=22, minBit 3, minWin=22, winSum=394
8228 09:57:54.411380 TX Vref=24, minBit 0, minWin=24, winSum=406
8229 09:57:54.417861 TX Vref=26, minBit 3, minWin=23, winSum=411
8230 09:57:54.421221 TX Vref=28, minBit 0, minWin=25, winSum=414
8231 09:57:54.424489 TX Vref=30, minBit 1, minWin=24, winSum=409
8232 09:57:54.427794 TX Vref=32, minBit 3, minWin=23, winSum=398
8233 09:57:54.431485 TX Vref=34, minBit 3, minWin=23, winSum=391
8234 09:57:54.437887 [TxChooseVref] Worse bit 0, Min win 25, Win sum 414, Final Vref 28
8235 09:57:54.438447
8236 09:57:54.441150 Final TX Range 0 Vref 28
8237 09:57:54.441607
8238 09:57:54.441972 ==
8239 09:57:54.444420 Dram Type= 6, Freq= 0, CH_1, rank 0
8240 09:57:54.447753 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8241 09:57:54.448306 ==
8242 09:57:54.448733
8243 09:57:54.449076
8244 09:57:54.450995 TX Vref Scan disable
8245 09:57:54.458204 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8246 09:57:54.458760 == TX Byte 0 ==
8247 09:57:54.461134 u2DelayCellOfst[0]=14 cells (4 PI)
8248 09:57:54.464443 u2DelayCellOfst[1]=7 cells (2 PI)
8249 09:57:54.467886 u2DelayCellOfst[2]=0 cells (0 PI)
8250 09:57:54.471238 u2DelayCellOfst[3]=7 cells (2 PI)
8251 09:57:54.474442 u2DelayCellOfst[4]=7 cells (2 PI)
8252 09:57:54.478285 u2DelayCellOfst[5]=14 cells (4 PI)
8253 09:57:54.480925 u2DelayCellOfst[6]=14 cells (4 PI)
8254 09:57:54.481390 u2DelayCellOfst[7]=3 cells (1 PI)
8255 09:57:54.487554 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8256 09:57:54.491359 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8257 09:57:54.491911 == TX Byte 1 ==
8258 09:57:54.494370 u2DelayCellOfst[8]=0 cells (0 PI)
8259 09:57:54.498055 u2DelayCellOfst[9]=3 cells (1 PI)
8260 09:57:54.501011 u2DelayCellOfst[10]=7 cells (2 PI)
8261 09:57:54.504581 u2DelayCellOfst[11]=3 cells (1 PI)
8262 09:57:54.507746 u2DelayCellOfst[12]=14 cells (4 PI)
8263 09:57:54.510707 u2DelayCellOfst[13]=17 cells (5 PI)
8264 09:57:54.514591 u2DelayCellOfst[14]=14 cells (4 PI)
8265 09:57:54.517674 u2DelayCellOfst[15]=14 cells (4 PI)
8266 09:57:54.521055 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8267 09:57:54.527716 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8268 09:57:54.528274 DramC Write-DBI on
8269 09:57:54.528705 ==
8270 09:57:54.530588 Dram Type= 6, Freq= 0, CH_1, rank 0
8271 09:57:54.533765 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8272 09:57:54.534250 ==
8273 09:57:54.537069
8274 09:57:54.537533
8275 09:57:54.537897 TX Vref Scan disable
8276 09:57:54.540662 == TX Byte 0 ==
8277 09:57:54.544117 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8278 09:57:54.547389 == TX Byte 1 ==
8279 09:57:54.551031 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8280 09:57:54.551586 DramC Write-DBI off
8281 09:57:54.554122
8282 09:57:54.554673 [DATLAT]
8283 09:57:54.555047 Freq=1600, CH1 RK0
8284 09:57:54.555397
8285 09:57:54.557271 DATLAT Default: 0xf
8286 09:57:54.557756 0, 0xFFFF, sum = 0
8287 09:57:54.560667 1, 0xFFFF, sum = 0
8288 09:57:54.561144 2, 0xFFFF, sum = 0
8289 09:57:54.563733 3, 0xFFFF, sum = 0
8290 09:57:54.564198 4, 0xFFFF, sum = 0
8291 09:57:54.567728 5, 0xFFFF, sum = 0
8292 09:57:54.570684 6, 0xFFFF, sum = 0
8293 09:57:54.571244 7, 0xFFFF, sum = 0
8294 09:57:54.573896 8, 0xFFFF, sum = 0
8295 09:57:54.574456 9, 0xFFFF, sum = 0
8296 09:57:54.577062 10, 0xFFFF, sum = 0
8297 09:57:54.577526 11, 0xFFFF, sum = 0
8298 09:57:54.580672 12, 0x8FFF, sum = 0
8299 09:57:54.581231 13, 0x0, sum = 1
8300 09:57:54.583974 14, 0x0, sum = 2
8301 09:57:54.584574 15, 0x0, sum = 3
8302 09:57:54.587029 16, 0x0, sum = 4
8303 09:57:54.587493 best_step = 14
8304 09:57:54.587854
8305 09:57:54.588190 ==
8306 09:57:54.590666 Dram Type= 6, Freq= 0, CH_1, rank 0
8307 09:57:54.594012 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8308 09:57:54.594585 ==
8309 09:57:54.597492 RX Vref Scan: 1
8310 09:57:54.598046
8311 09:57:54.601024 Set Vref Range= 24 -> 127
8312 09:57:54.601581
8313 09:57:54.601944 RX Vref 24 -> 127, step: 1
8314 09:57:54.603911
8315 09:57:54.604461 RX Delay 3 -> 252, step: 4
8316 09:57:54.604875
8317 09:57:54.607212 Set Vref, RX VrefLevel [Byte0]: 24
8318 09:57:54.610567 [Byte1]: 24
8319 09:57:54.613945
8320 09:57:54.614502 Set Vref, RX VrefLevel [Byte0]: 25
8321 09:57:54.617389 [Byte1]: 25
8322 09:57:54.621474
8323 09:57:54.622024 Set Vref, RX VrefLevel [Byte0]: 26
8324 09:57:54.624620 [Byte1]: 26
8325 09:57:54.629086
8326 09:57:54.629637 Set Vref, RX VrefLevel [Byte0]: 27
8327 09:57:54.632693 [Byte1]: 27
8328 09:57:54.636678
8329 09:57:54.637393 Set Vref, RX VrefLevel [Byte0]: 28
8330 09:57:54.640056 [Byte1]: 28
8331 09:57:54.644435
8332 09:57:54.644935 Set Vref, RX VrefLevel [Byte0]: 29
8333 09:57:54.647648 [Byte1]: 29
8334 09:57:54.652156
8335 09:57:54.652756 Set Vref, RX VrefLevel [Byte0]: 30
8336 09:57:54.655803 [Byte1]: 30
8337 09:57:54.659679
8338 09:57:54.660135 Set Vref, RX VrefLevel [Byte0]: 31
8339 09:57:54.663023 [Byte1]: 31
8340 09:57:54.667942
8341 09:57:54.668492 Set Vref, RX VrefLevel [Byte0]: 32
8342 09:57:54.670835 [Byte1]: 32
8343 09:57:54.675169
8344 09:57:54.675726 Set Vref, RX VrefLevel [Byte0]: 33
8345 09:57:54.678339 [Byte1]: 33
8346 09:57:54.682525
8347 09:57:54.682986 Set Vref, RX VrefLevel [Byte0]: 34
8348 09:57:54.686147 [Byte1]: 34
8349 09:57:54.689998
8350 09:57:54.690458 Set Vref, RX VrefLevel [Byte0]: 35
8351 09:57:54.693299 [Byte1]: 35
8352 09:57:54.697652
8353 09:57:54.698111 Set Vref, RX VrefLevel [Byte0]: 36
8354 09:57:54.701130 [Byte1]: 36
8355 09:57:54.705366
8356 09:57:54.705784 Set Vref, RX VrefLevel [Byte0]: 37
8357 09:57:54.709203 [Byte1]: 37
8358 09:57:54.713357
8359 09:57:54.713991 Set Vref, RX VrefLevel [Byte0]: 38
8360 09:57:54.716488 [Byte1]: 38
8361 09:57:54.720885
8362 09:57:54.721519 Set Vref, RX VrefLevel [Byte0]: 39
8363 09:57:54.723912 [Byte1]: 39
8364 09:57:54.728967
8365 09:57:54.729500 Set Vref, RX VrefLevel [Byte0]: 40
8366 09:57:54.734902 [Byte1]: 40
8367 09:57:54.735414
8368 09:57:54.737991 Set Vref, RX VrefLevel [Byte0]: 41
8369 09:57:54.741300 [Byte1]: 41
8370 09:57:54.741735
8371 09:57:54.744653 Set Vref, RX VrefLevel [Byte0]: 42
8372 09:57:54.748240 [Byte1]: 42
8373 09:57:54.751666
8374 09:57:54.752218 Set Vref, RX VrefLevel [Byte0]: 43
8375 09:57:54.754887 [Byte1]: 43
8376 09:57:54.759179
8377 09:57:54.759639 Set Vref, RX VrefLevel [Byte0]: 44
8378 09:57:54.762486 [Byte1]: 44
8379 09:57:54.767149
8380 09:57:54.767700 Set Vref, RX VrefLevel [Byte0]: 45
8381 09:57:54.770560 [Byte1]: 45
8382 09:57:54.774500
8383 09:57:54.775050 Set Vref, RX VrefLevel [Byte0]: 46
8384 09:57:54.778243 [Byte1]: 46
8385 09:57:54.782048
8386 09:57:54.782600 Set Vref, RX VrefLevel [Byte0]: 47
8387 09:57:54.785693 [Byte1]: 47
8388 09:57:54.789787
8389 09:57:54.790246 Set Vref, RX VrefLevel [Byte0]: 48
8390 09:57:54.793430 [Byte1]: 48
8391 09:57:54.797737
8392 09:57:54.798291 Set Vref, RX VrefLevel [Byte0]: 49
8393 09:57:54.801506 [Byte1]: 49
8394 09:57:54.805174
8395 09:57:54.805762 Set Vref, RX VrefLevel [Byte0]: 50
8396 09:57:54.808737 [Byte1]: 50
8397 09:57:54.812714
8398 09:57:54.813261 Set Vref, RX VrefLevel [Byte0]: 51
8399 09:57:54.816150 [Byte1]: 51
8400 09:57:54.820685
8401 09:57:54.821234 Set Vref, RX VrefLevel [Byte0]: 52
8402 09:57:54.823557 [Byte1]: 52
8403 09:57:54.827819
8404 09:57:54.828276 Set Vref, RX VrefLevel [Byte0]: 53
8405 09:57:54.834446 [Byte1]: 53
8406 09:57:54.835001
8407 09:57:54.837924 Set Vref, RX VrefLevel [Byte0]: 54
8408 09:57:54.841199 [Byte1]: 54
8409 09:57:54.841663
8410 09:57:54.844295 Set Vref, RX VrefLevel [Byte0]: 55
8411 09:57:54.847952 [Byte1]: 55
8412 09:57:54.851173
8413 09:57:54.851722 Set Vref, RX VrefLevel [Byte0]: 56
8414 09:57:54.854292 [Byte1]: 56
8415 09:57:54.858808
8416 09:57:54.859417 Set Vref, RX VrefLevel [Byte0]: 57
8417 09:57:54.861843 [Byte1]: 57
8418 09:57:54.866336
8419 09:57:54.866846 Set Vref, RX VrefLevel [Byte0]: 58
8420 09:57:54.869655 [Byte1]: 58
8421 09:57:54.874183
8422 09:57:54.874729 Set Vref, RX VrefLevel [Byte0]: 59
8423 09:57:54.877415 [Byte1]: 59
8424 09:57:54.881808
8425 09:57:54.882355 Set Vref, RX VrefLevel [Byte0]: 60
8426 09:57:54.884961 [Byte1]: 60
8427 09:57:54.889521
8428 09:57:54.890069 Set Vref, RX VrefLevel [Byte0]: 61
8429 09:57:54.892999 [Byte1]: 61
8430 09:57:54.897100
8431 09:57:54.897650 Set Vref, RX VrefLevel [Byte0]: 62
8432 09:57:54.900126 [Byte1]: 62
8433 09:57:54.904641
8434 09:57:54.905196 Set Vref, RX VrefLevel [Byte0]: 63
8435 09:57:54.907970 [Byte1]: 63
8436 09:57:54.912464
8437 09:57:54.913076 Set Vref, RX VrefLevel [Byte0]: 64
8438 09:57:54.915571 [Byte1]: 64
8439 09:57:54.919977
8440 09:57:54.920588 Set Vref, RX VrefLevel [Byte0]: 65
8441 09:57:54.923229 [Byte1]: 65
8442 09:57:54.927306
8443 09:57:54.927767 Set Vref, RX VrefLevel [Byte0]: 66
8444 09:57:54.930823 [Byte1]: 66
8445 09:57:54.935534
8446 09:57:54.936080 Set Vref, RX VrefLevel [Byte0]: 67
8447 09:57:54.938636 [Byte1]: 67
8448 09:57:54.942794
8449 09:57:54.943362 Set Vref, RX VrefLevel [Byte0]: 68
8450 09:57:54.946371 [Byte1]: 68
8451 09:57:54.950491
8452 09:57:54.950951 Set Vref, RX VrefLevel [Byte0]: 69
8453 09:57:54.953710 [Byte1]: 69
8454 09:57:54.958462
8455 09:57:54.959022 Set Vref, RX VrefLevel [Byte0]: 70
8456 09:57:54.961559 [Byte1]: 70
8457 09:57:54.965620
8458 09:57:54.966082 Set Vref, RX VrefLevel [Byte0]: 71
8459 09:57:54.969031 [Byte1]: 71
8460 09:57:54.973386
8461 09:57:54.974065 Set Vref, RX VrefLevel [Byte0]: 72
8462 09:57:54.976741 [Byte1]: 72
8463 09:57:54.980982
8464 09:57:54.981436 Set Vref, RX VrefLevel [Byte0]: 73
8465 09:57:54.984813 [Byte1]: 73
8466 09:57:54.988913
8467 09:57:54.989462 Set Vref, RX VrefLevel [Byte0]: 74
8468 09:57:54.992242 [Byte1]: 74
8469 09:57:54.996569
8470 09:57:54.999832 Final RX Vref Byte 0 = 61 to rank0
8471 09:57:55.000395 Final RX Vref Byte 1 = 55 to rank0
8472 09:57:55.003106 Final RX Vref Byte 0 = 61 to rank1
8473 09:57:55.006066 Final RX Vref Byte 1 = 55 to rank1==
8474 09:57:55.009746 Dram Type= 6, Freq= 0, CH_1, rank 0
8475 09:57:55.016683 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8476 09:57:55.017241 ==
8477 09:57:55.017609 DQS Delay:
8478 09:57:55.019438 DQS0 = 0, DQS1 = 0
8479 09:57:55.019894 DQM Delay:
8480 09:57:55.020257 DQM0 = 128, DQM1 = 124
8481 09:57:55.022976 DQ Delay:
8482 09:57:55.025876 DQ0 =130, DQ1 =124, DQ2 =118, DQ3 =126
8483 09:57:55.029132 DQ4 =130, DQ5 =138, DQ6 =138, DQ7 =124
8484 09:57:55.032498 DQ8 =106, DQ9 =114, DQ10 =128, DQ11 =114
8485 09:57:55.035806 DQ12 =132, DQ13 =134, DQ14 =134, DQ15 =134
8486 09:57:55.036260
8487 09:57:55.036670
8488 09:57:55.037017
8489 09:57:55.039296 [DramC_TX_OE_Calibration] TA2
8490 09:57:55.042857 Original DQ_B0 (3 6) =30, OEN = 27
8491 09:57:55.046355 Original DQ_B1 (3 6) =30, OEN = 27
8492 09:57:55.049210 24, 0x0, End_B0=24 End_B1=24
8493 09:57:55.049673 25, 0x0, End_B0=25 End_B1=25
8494 09:57:55.052632 26, 0x0, End_B0=26 End_B1=26
8495 09:57:55.055839 27, 0x0, End_B0=27 End_B1=27
8496 09:57:55.059521 28, 0x0, End_B0=28 End_B1=28
8497 09:57:55.062759 29, 0x0, End_B0=29 End_B1=29
8498 09:57:55.063326 30, 0x0, End_B0=30 End_B1=30
8499 09:57:55.066034 31, 0x5151, End_B0=30 End_B1=30
8500 09:57:55.069273 Byte0 end_step=30 best_step=27
8501 09:57:55.072829 Byte1 end_step=30 best_step=27
8502 09:57:55.075985 Byte0 TX OE(2T, 0.5T) = (3, 3)
8503 09:57:55.079270 Byte1 TX OE(2T, 0.5T) = (3, 3)
8504 09:57:55.079840
8505 09:57:55.080206
8506 09:57:55.086264 [DQSOSCAuto] RK0, (LSB)MR18= 0x2727, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
8507 09:57:55.089240 CH1 RK0: MR19=303, MR18=2727
8508 09:57:55.095967 CH1_RK0: MR19=0x303, MR18=0x2727, DQSOSC=390, MR23=63, INC=24, DEC=16
8509 09:57:55.096559
8510 09:57:55.099312 ----->DramcWriteLeveling(PI) begin...
8511 09:57:55.099873 ==
8512 09:57:55.102576 Dram Type= 6, Freq= 0, CH_1, rank 1
8513 09:57:55.105960 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8514 09:57:55.106520 ==
8515 09:57:55.108732 Write leveling (Byte 0): 24 => 24
8516 09:57:55.112339 Write leveling (Byte 1): 20 => 20
8517 09:57:55.116042 DramcWriteLeveling(PI) end<-----
8518 09:57:55.116632
8519 09:57:55.117000 ==
8520 09:57:55.118965 Dram Type= 6, Freq= 0, CH_1, rank 1
8521 09:57:55.122393 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8522 09:57:55.122953 ==
8523 09:57:55.125384 [Gating] SW mode calibration
8524 09:57:55.132116 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8525 09:57:55.138932 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8526 09:57:55.142453 0 12 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
8527 09:57:55.148808 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8528 09:57:55.152028 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8529 09:57:55.155791 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8530 09:57:55.161838 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8531 09:57:55.165500 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8532 09:57:55.168833 0 12 24 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
8533 09:57:55.172167 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
8534 09:57:55.178811 0 13 0 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
8535 09:57:55.182263 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8536 09:57:55.185347 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8537 09:57:55.192489 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8538 09:57:55.195325 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8539 09:57:55.198739 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8540 09:57:55.205135 0 13 24 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
8541 09:57:55.209328 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8542 09:57:55.211817 0 14 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8543 09:57:55.218523 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8544 09:57:55.222043 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8545 09:57:55.225434 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8546 09:57:55.231847 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8547 09:57:55.235328 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8548 09:57:55.238703 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8549 09:57:55.244827 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8550 09:57:55.248447 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8551 09:57:55.251678 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8552 09:57:55.258414 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8553 09:57:55.261494 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8554 09:57:55.264705 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8555 09:57:55.271735 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8556 09:57:55.274735 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8557 09:57:55.278313 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8558 09:57:55.284908 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8559 09:57:55.288605 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8560 09:57:55.291735 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8561 09:57:55.298129 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8562 09:57:55.301657 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8563 09:57:55.304503 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8564 09:57:55.311294 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8565 09:57:55.314589 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8566 09:57:55.317812 Total UI for P1: 0, mck2ui 16
8567 09:57:55.321066 best dqsien dly found for B0: ( 1, 0, 22)
8568 09:57:55.324388 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8569 09:57:55.327755 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8570 09:57:55.331259 Total UI for P1: 0, mck2ui 16
8571 09:57:55.334966 best dqsien dly found for B1: ( 1, 0, 30)
8572 09:57:55.338059 best DQS0 dly(MCK, UI, PI) = (1, 0, 22)
8573 09:57:55.344692 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8574 09:57:55.345245
8575 09:57:55.347985 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 22)
8576 09:57:55.351091 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8577 09:57:55.354342 [Gating] SW calibration Done
8578 09:57:55.354902 ==
8579 09:57:55.357556 Dram Type= 6, Freq= 0, CH_1, rank 1
8580 09:57:55.361058 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8581 09:57:55.361517 ==
8582 09:57:55.364455 RX Vref Scan: 0
8583 09:57:55.365062
8584 09:57:55.365575 RX Vref 0 -> 0, step: 1
8585 09:57:55.365948
8586 09:57:55.367443 RX Delay 0 -> 252, step: 8
8587 09:57:55.371113 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8588 09:57:55.374213 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8589 09:57:55.381096 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8590 09:57:55.384680 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8591 09:57:55.387864 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8592 09:57:55.391115 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8593 09:57:55.394229 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8594 09:57:55.400879 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8595 09:57:55.404285 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8596 09:57:55.407935 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8597 09:57:55.410680 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8598 09:57:55.414409 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8599 09:57:55.420670 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8600 09:57:55.424557 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8601 09:57:55.427425 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8602 09:57:55.430512 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8603 09:57:55.430970 ==
8604 09:57:55.434138 Dram Type= 6, Freq= 0, CH_1, rank 1
8605 09:57:55.440673 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8606 09:57:55.441245 ==
8607 09:57:55.441620 DQS Delay:
8608 09:57:55.443746 DQS0 = 0, DQS1 = 0
8609 09:57:55.444205 DQM Delay:
8610 09:57:55.447370 DQM0 = 131, DQM1 = 125
8611 09:57:55.447923 DQ Delay:
8612 09:57:55.450358 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8613 09:57:55.453806 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8614 09:57:55.457236 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8615 09:57:55.460203 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8616 09:57:55.460749
8617 09:57:55.461218
8618 09:57:55.461576 ==
8619 09:57:55.463798 Dram Type= 6, Freq= 0, CH_1, rank 1
8620 09:57:55.470235 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8621 09:57:55.470704 ==
8622 09:57:55.471219
8623 09:57:55.471653
8624 09:57:55.471998 TX Vref Scan disable
8625 09:57:55.473639 == TX Byte 0 ==
8626 09:57:55.477187 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8627 09:57:55.480477 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8628 09:57:55.483737 == TX Byte 1 ==
8629 09:57:55.487070 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8630 09:57:55.493909 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8631 09:57:55.494464 ==
8632 09:57:55.496982 Dram Type= 6, Freq= 0, CH_1, rank 1
8633 09:57:55.500650 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8634 09:57:55.501214 ==
8635 09:57:55.512929
8636 09:57:55.516138 TX Vref early break, caculate TX vref
8637 09:57:55.519398 TX Vref=16, minBit 0, minWin=22, winSum=381
8638 09:57:55.522731 TX Vref=18, minBit 0, minWin=22, winSum=388
8639 09:57:55.526095 TX Vref=20, minBit 0, minWin=23, winSum=394
8640 09:57:55.529027 TX Vref=22, minBit 0, minWin=23, winSum=409
8641 09:57:55.532405 TX Vref=24, minBit 0, minWin=24, winSum=415
8642 09:57:55.539238 TX Vref=26, minBit 0, minWin=24, winSum=419
8643 09:57:55.542382 TX Vref=28, minBit 0, minWin=24, winSum=416
8644 09:57:55.546270 TX Vref=30, minBit 0, minWin=24, winSum=417
8645 09:57:55.549062 TX Vref=32, minBit 0, minWin=23, winSum=409
8646 09:57:55.552587 TX Vref=34, minBit 0, minWin=22, winSum=396
8647 09:57:55.559219 [TxChooseVref] Worse bit 0, Min win 24, Win sum 419, Final Vref 26
8648 09:57:55.559796
8649 09:57:55.562418 Final TX Range 0 Vref 26
8650 09:57:55.562876
8651 09:57:55.563235 ==
8652 09:57:55.565620 Dram Type= 6, Freq= 0, CH_1, rank 1
8653 09:57:55.569103 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8654 09:57:55.569563 ==
8655 09:57:55.569926
8656 09:57:55.570259
8657 09:57:55.572255 TX Vref Scan disable
8658 09:57:55.579117 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8659 09:57:55.579674 == TX Byte 0 ==
8660 09:57:55.582303 u2DelayCellOfst[0]=17 cells (5 PI)
8661 09:57:55.585916 u2DelayCellOfst[1]=10 cells (3 PI)
8662 09:57:55.589103 u2DelayCellOfst[2]=0 cells (0 PI)
8663 09:57:55.592422 u2DelayCellOfst[3]=7 cells (2 PI)
8664 09:57:55.595617 u2DelayCellOfst[4]=7 cells (2 PI)
8665 09:57:55.599057 u2DelayCellOfst[5]=17 cells (5 PI)
8666 09:57:55.602156 u2DelayCellOfst[6]=17 cells (5 PI)
8667 09:57:55.602703 u2DelayCellOfst[7]=3 cells (1 PI)
8668 09:57:55.609211 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8669 09:57:55.612171 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8670 09:57:55.615717 == TX Byte 1 ==
8671 09:57:55.616269 u2DelayCellOfst[8]=0 cells (0 PI)
8672 09:57:55.618705 u2DelayCellOfst[9]=3 cells (1 PI)
8673 09:57:55.622276 u2DelayCellOfst[10]=10 cells (3 PI)
8674 09:57:55.625390 u2DelayCellOfst[11]=3 cells (1 PI)
8675 09:57:55.628712 u2DelayCellOfst[12]=14 cells (4 PI)
8676 09:57:55.631853 u2DelayCellOfst[13]=17 cells (5 PI)
8677 09:57:55.635692 u2DelayCellOfst[14]=17 cells (5 PI)
8678 09:57:55.638469 u2DelayCellOfst[15]=17 cells (5 PI)
8679 09:57:55.642077 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8680 09:57:55.649148 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8681 09:57:55.649738 DramC Write-DBI on
8682 09:57:55.650111 ==
8683 09:57:55.651787 Dram Type= 6, Freq= 0, CH_1, rank 1
8684 09:57:55.655279 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8685 09:57:55.658604 ==
8686 09:57:55.659159
8687 09:57:55.659529
8688 09:57:55.659874 TX Vref Scan disable
8689 09:57:55.661925 == TX Byte 0 ==
8690 09:57:55.665515 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8691 09:57:55.668219 == TX Byte 1 ==
8692 09:57:55.672047 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8693 09:57:55.675234 DramC Write-DBI off
8694 09:57:55.675689
8695 09:57:55.676048 [DATLAT]
8696 09:57:55.676384 Freq=1600, CH1 RK1
8697 09:57:55.676746
8698 09:57:55.678795 DATLAT Default: 0xe
8699 09:57:55.679249 0, 0xFFFF, sum = 0
8700 09:57:55.682433 1, 0xFFFF, sum = 0
8701 09:57:55.685227 2, 0xFFFF, sum = 0
8702 09:57:55.685788 3, 0xFFFF, sum = 0
8703 09:57:55.688814 4, 0xFFFF, sum = 0
8704 09:57:55.689277 5, 0xFFFF, sum = 0
8705 09:57:55.691984 6, 0xFFFF, sum = 0
8706 09:57:55.692591 7, 0xFFFF, sum = 0
8707 09:57:55.695244 8, 0xFFFF, sum = 0
8708 09:57:55.695812 9, 0xFFFF, sum = 0
8709 09:57:55.698349 10, 0xFFFF, sum = 0
8710 09:57:55.698814 11, 0xFFFF, sum = 0
8711 09:57:55.701842 12, 0xF5F, sum = 0
8712 09:57:55.702306 13, 0x0, sum = 1
8713 09:57:55.704966 14, 0x0, sum = 2
8714 09:57:55.705433 15, 0x0, sum = 3
8715 09:57:55.708886 16, 0x0, sum = 4
8716 09:57:55.709585 best_step = 14
8717 09:57:55.710088
8718 09:57:55.710439 ==
8719 09:57:55.711725 Dram Type= 6, Freq= 0, CH_1, rank 1
8720 09:57:55.715373 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8721 09:57:55.715931 ==
8722 09:57:55.718537 RX Vref Scan: 0
8723 09:57:55.719092
8724 09:57:55.721957 RX Vref 0 -> 0, step: 1
8725 09:57:55.722512
8726 09:57:55.722875 RX Delay 3 -> 252, step: 4
8727 09:57:55.728897 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8728 09:57:55.732079 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8729 09:57:55.735486 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8730 09:57:55.738884 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8731 09:57:55.745512 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8732 09:57:55.748892 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8733 09:57:55.752174 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8734 09:57:55.755343 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8735 09:57:55.758747 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
8736 09:57:55.765122 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8737 09:57:55.768598 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8738 09:57:55.772201 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8739 09:57:55.775285 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8740 09:57:55.778477 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8741 09:57:55.785539 iDelay=195, Bit 14, Center 136 (79 ~ 194) 116
8742 09:57:55.788422 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8743 09:57:55.789014 ==
8744 09:57:55.791960 Dram Type= 6, Freq= 0, CH_1, rank 1
8745 09:57:55.795466 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8746 09:57:55.796032 ==
8747 09:57:55.798779 DQS Delay:
8748 09:57:55.799399 DQS0 = 0, DQS1 = 0
8749 09:57:55.799774 DQM Delay:
8750 09:57:55.801550 DQM0 = 127, DQM1 = 123
8751 09:57:55.802003 DQ Delay:
8752 09:57:55.805110 DQ0 =128, DQ1 =124, DQ2 =116, DQ3 =124
8753 09:57:55.807957 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8754 09:57:55.814898 DQ8 =106, DQ9 =110, DQ10 =126, DQ11 =114
8755 09:57:55.817950 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8756 09:57:55.818414
8757 09:57:55.818779
8758 09:57:55.819111
8759 09:57:55.821177 [DramC_TX_OE_Calibration] TA2
8760 09:57:55.824771 Original DQ_B0 (3 6) =30, OEN = 27
8761 09:57:55.828382 Original DQ_B1 (3 6) =30, OEN = 27
8762 09:57:55.828993 24, 0x0, End_B0=24 End_B1=24
8763 09:57:55.831128 25, 0x0, End_B0=25 End_B1=25
8764 09:57:55.834677 26, 0x0, End_B0=26 End_B1=26
8765 09:57:55.838095 27, 0x0, End_B0=27 End_B1=27
8766 09:57:55.838560 28, 0x0, End_B0=28 End_B1=28
8767 09:57:55.841096 29, 0x0, End_B0=29 End_B1=29
8768 09:57:55.844436 30, 0x0, End_B0=30 End_B1=30
8769 09:57:55.847977 31, 0x4141, End_B0=30 End_B1=30
8770 09:57:55.850953 Byte0 end_step=30 best_step=27
8771 09:57:55.854709 Byte1 end_step=30 best_step=27
8772 09:57:55.855268 Byte0 TX OE(2T, 0.5T) = (3, 3)
8773 09:57:55.857857 Byte1 TX OE(2T, 0.5T) = (3, 3)
8774 09:57:55.858415
8775 09:57:55.858781
8776 09:57:55.867932 [DQSOSCAuto] RK1, (LSB)MR18= 0x2121, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
8777 09:57:55.871193 CH1 RK1: MR19=303, MR18=2121
8778 09:57:55.874400 CH1_RK1: MR19=0x303, MR18=0x2121, DQSOSC=393, MR23=63, INC=23, DEC=15
8779 09:57:55.877885 [RxdqsGatingPostProcess] freq 1600
8780 09:57:55.884286 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8781 09:57:55.887943 Pre-setting of DQS Precalculation
8782 09:57:55.890650 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8783 09:57:55.900630 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8784 09:57:55.907500 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8785 09:57:55.908107
8786 09:57:55.908479
8787 09:57:55.910667 [Calibration Summary] 3200 Mbps
8788 09:57:55.911228 CH 0, Rank 0
8789 09:57:55.913895 SW Impedance : PASS
8790 09:57:55.914458 DUTY Scan : NO K
8791 09:57:55.917265 ZQ Calibration : PASS
8792 09:57:55.920853 Jitter Meter : NO K
8793 09:57:55.921409 CBT Training : PASS
8794 09:57:55.923632 Write leveling : PASS
8795 09:57:55.927415 RX DQS gating : PASS
8796 09:57:55.928032 RX DQ/DQS(RDDQC) : PASS
8797 09:57:55.930407 TX DQ/DQS : PASS
8798 09:57:55.933693 RX DATLAT : PASS
8799 09:57:55.934149 RX DQ/DQS(Engine): PASS
8800 09:57:55.937606 TX OE : PASS
8801 09:57:55.938062 All Pass.
8802 09:57:55.938426
8803 09:57:55.940223 CH 0, Rank 1
8804 09:57:55.940724 SW Impedance : PASS
8805 09:57:55.943591 DUTY Scan : NO K
8806 09:57:55.947135 ZQ Calibration : PASS
8807 09:57:55.947690 Jitter Meter : NO K
8808 09:57:55.950205 CBT Training : PASS
8809 09:57:55.954155 Write leveling : PASS
8810 09:57:55.954711 RX DQS gating : PASS
8811 09:57:55.957242 RX DQ/DQS(RDDQC) : PASS
8812 09:57:55.957698 TX DQ/DQS : PASS
8813 09:57:55.960567 RX DATLAT : PASS
8814 09:57:55.963611 RX DQ/DQS(Engine): PASS
8815 09:57:55.964065 TX OE : PASS
8816 09:57:55.966933 All Pass.
8817 09:57:55.967484
8818 09:57:55.967856 CH 1, Rank 0
8819 09:57:55.970454 SW Impedance : PASS
8820 09:57:55.971011 DUTY Scan : NO K
8821 09:57:55.973618 ZQ Calibration : PASS
8822 09:57:55.977467 Jitter Meter : NO K
8823 09:57:55.978025 CBT Training : PASS
8824 09:57:55.980136 Write leveling : PASS
8825 09:57:55.983856 RX DQS gating : PASS
8826 09:57:55.984410 RX DQ/DQS(RDDQC) : PASS
8827 09:57:55.987114 TX DQ/DQS : PASS
8828 09:57:55.990369 RX DATLAT : PASS
8829 09:57:55.990857 RX DQ/DQS(Engine): PASS
8830 09:57:55.993685 TX OE : PASS
8831 09:57:55.994245 All Pass.
8832 09:57:55.994613
8833 09:57:55.996837 CH 1, Rank 1
8834 09:57:55.997291 SW Impedance : PASS
8835 09:57:56.000392 DUTY Scan : NO K
8836 09:57:56.003670 ZQ Calibration : PASS
8837 09:57:56.004224 Jitter Meter : NO K
8838 09:57:56.007070 CBT Training : PASS
8839 09:57:56.010546 Write leveling : PASS
8840 09:57:56.011104 RX DQS gating : PASS
8841 09:57:56.013252 RX DQ/DQS(RDDQC) : PASS
8842 09:57:56.016847 TX DQ/DQS : PASS
8843 09:57:56.017303 RX DATLAT : PASS
8844 09:57:56.020125 RX DQ/DQS(Engine): PASS
8845 09:57:56.020774 TX OE : PASS
8846 09:57:56.023425 All Pass.
8847 09:57:56.023976
8848 09:57:56.024368 DramC Write-DBI on
8849 09:57:56.026603 PER_BANK_REFRESH: Hybrid Mode
8850 09:57:56.030352 TX_TRACKING: ON
8851 09:57:56.036859 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8852 09:57:56.046847 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8853 09:57:56.053127 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8854 09:57:56.056918 [FAST_K] Save calibration result to emmc
8855 09:57:56.059943 sync common calibartion params.
8856 09:57:56.060497 sync cbt_mode0:0, 1:0
8857 09:57:56.062932 dram_init: ddr_geometry: 0
8858 09:57:56.066796 dram_init: ddr_geometry: 0
8859 09:57:56.069721 dram_init: ddr_geometry: 0
8860 09:57:56.070181 0:dram_rank_size:80000000
8861 09:57:56.073213 1:dram_rank_size:80000000
8862 09:57:56.079925 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8863 09:57:56.080489 DFS_SHUFFLE_HW_MODE: ON
8864 09:57:56.083111 dramc_set_vcore_voltage set vcore to 725000
8865 09:57:56.086388 Read voltage for 1600, 0
8866 09:57:56.086946 Vio18 = 0
8867 09:57:56.089859 Vcore = 725000
8868 09:57:56.090416 Vdram = 0
8869 09:57:56.090779 Vddq = 0
8870 09:57:56.092912 Vmddr = 0
8871 09:57:56.093368 switch to 3200 Mbps bootup
8872 09:57:56.096196 [DramcRunTimeConfig]
8873 09:57:56.096805 PHYPLL
8874 09:57:56.099508 DPM_CONTROL_AFTERK: ON
8875 09:57:56.100063 PER_BANK_REFRESH: ON
8876 09:57:56.102927 REFRESH_OVERHEAD_REDUCTION: ON
8877 09:57:56.106131 CMD_PICG_NEW_MODE: OFF
8878 09:57:56.106687 XRTWTW_NEW_MODE: ON
8879 09:57:56.109480 XRTRTR_NEW_MODE: ON
8880 09:57:56.110037 TX_TRACKING: ON
8881 09:57:56.112920 RDSEL_TRACKING: OFF
8882 09:57:56.116064 DQS Precalculation for DVFS: ON
8883 09:57:56.116662 RX_TRACKING: OFF
8884 09:57:56.119027 HW_GATING DBG: ON
8885 09:57:56.119483 ZQCS_ENABLE_LP4: ON
8886 09:57:56.122724 RX_PICG_NEW_MODE: ON
8887 09:57:56.125214 TX_PICG_NEW_MODE: ON
8888 09:57:56.125673 ENABLE_RX_DCM_DPHY: ON
8889 09:57:56.128978 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8890 09:57:56.132403 DUMMY_READ_FOR_TRACKING: OFF
8891 09:57:56.135486 !!! SPM_CONTROL_AFTERK: OFF
8892 09:57:56.136214 !!! SPM could not control APHY
8893 09:57:56.138722 IMPEDANCE_TRACKING: ON
8894 09:57:56.142353 TEMP_SENSOR: ON
8895 09:57:56.142911 HW_SAVE_FOR_SR: OFF
8896 09:57:56.145398 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8897 09:57:56.148850 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8898 09:57:56.152390 Read ODT Tracking: ON
8899 09:57:56.152973 Refresh Rate DeBounce: ON
8900 09:57:56.155582 DFS_NO_QUEUE_FLUSH: ON
8901 09:57:56.158812 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8902 09:57:56.161843 ENABLE_DFS_RUNTIME_MRW: OFF
8903 09:57:56.162299 DDR_RESERVE_NEW_MODE: ON
8904 09:57:56.165819 MR_CBT_SWITCH_FREQ: ON
8905 09:57:56.168569 =========================
8906 09:57:56.186919 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8907 09:57:56.190058 dram_init: ddr_geometry: 0
8908 09:57:56.207927 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8909 09:57:56.211652 dram_init: dram init end (result: 0)
8910 09:57:56.217980 DRAM-K: Full calibration passed in 23397 msecs
8911 09:57:56.221511 MRC: failed to locate region type 0.
8912 09:57:56.222071 DRAM rank0 size:0x80000000,
8913 09:57:56.224987 DRAM rank1 size=0x80000000
8914 09:57:56.234540 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8915 09:57:56.241164 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8916 09:57:56.248046 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8917 09:57:56.254356 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8918 09:57:56.257895 DRAM rank0 size:0x80000000,
8919 09:57:56.261080 DRAM rank1 size=0x80000000
8920 09:57:56.261633 CBMEM:
8921 09:57:56.264186 IMD: root @ 0xfffff000 254 entries.
8922 09:57:56.267401 IMD: root @ 0xffffec00 62 entries.
8923 09:57:56.270697 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8924 09:57:56.274357 WARNING: RO_VPD is uninitialized or empty.
8925 09:57:56.280875 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8926 09:57:56.287919 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8927 09:57:56.300566 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8928 09:57:56.311800 BS: romstage times (exec / console): total (unknown) / 22937 ms
8929 09:57:56.312360
8930 09:57:56.312813
8931 09:57:56.321556 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8932 09:57:56.325055 ARM64: Exception handlers installed.
8933 09:57:56.328168 ARM64: Testing exception
8934 09:57:56.331487 ARM64: Done test exception
8935 09:57:56.332040 Enumerating buses...
8936 09:57:56.334767 Show all devs... Before device enumeration.
8937 09:57:56.338089 Root Device: enabled 1
8938 09:57:56.341790 CPU_CLUSTER: 0: enabled 1
8939 09:57:56.342361 CPU: 00: enabled 1
8940 09:57:56.344634 Compare with tree...
8941 09:57:56.345101 Root Device: enabled 1
8942 09:57:56.348175 CPU_CLUSTER: 0: enabled 1
8943 09:57:56.351562 CPU: 00: enabled 1
8944 09:57:56.352144 Root Device scanning...
8945 09:57:56.354747 scan_static_bus for Root Device
8946 09:57:56.358266 CPU_CLUSTER: 0 enabled
8947 09:57:56.361277 scan_static_bus for Root Device done
8948 09:57:56.364391 scan_bus: bus Root Device finished in 8 msecs
8949 09:57:56.364900 done
8950 09:57:56.371676 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8951 09:57:56.374863 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8952 09:57:56.381184 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8953 09:57:56.384381 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8954 09:57:56.387742 Allocating resources...
8955 09:57:56.390909 Reading resources...
8956 09:57:56.394393 Root Device read_resources bus 0 link: 0
8957 09:57:56.394958 DRAM rank0 size:0x80000000,
8958 09:57:56.397669 DRAM rank1 size=0x80000000
8959 09:57:56.401367 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8960 09:57:56.404332 CPU: 00 missing read_resources
8961 09:57:56.410929 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8962 09:57:56.414255 Root Device read_resources bus 0 link: 0 done
8963 09:57:56.414813 Done reading resources.
8964 09:57:56.421022 Show resources in subtree (Root Device)...After reading.
8965 09:57:56.424278 Root Device child on link 0 CPU_CLUSTER: 0
8966 09:57:56.427626 CPU_CLUSTER: 0 child on link 0 CPU: 00
8967 09:57:56.437379 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8968 09:57:56.438027 CPU: 00
8969 09:57:56.440449 Root Device assign_resources, bus 0 link: 0
8970 09:57:56.443964 CPU_CLUSTER: 0 missing set_resources
8971 09:57:56.450884 Root Device assign_resources, bus 0 link: 0 done
8972 09:57:56.451445 Done setting resources.
8973 09:57:56.457511 Show resources in subtree (Root Device)...After assigning values.
8974 09:57:56.460670 Root Device child on link 0 CPU_CLUSTER: 0
8975 09:57:56.463930 CPU_CLUSTER: 0 child on link 0 CPU: 00
8976 09:57:56.473634 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8977 09:57:56.474197 CPU: 00
8978 09:57:56.477444 Done allocating resources.
8979 09:57:56.483571 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8980 09:57:56.484130 Enabling resources...
8981 09:57:56.484499 done.
8982 09:57:56.490367 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8983 09:57:56.490937 Initializing devices...
8984 09:57:56.493517 Root Device init
8985 09:57:56.494074 init hardware done!
8986 09:57:56.496971 0x00000018: ctrlr->caps
8987 09:57:56.500063 52.000 MHz: ctrlr->f_max
8988 09:57:56.500741 0.400 MHz: ctrlr->f_min
8989 09:57:56.503390 0x40ff8080: ctrlr->voltages
8990 09:57:56.506966 sclk: 390625
8991 09:57:56.507540 Bus Width = 1
8992 09:57:56.507913 sclk: 390625
8993 09:57:56.510082 Bus Width = 1
8994 09:57:56.510634 Early init status = 3
8995 09:57:56.516839 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8996 09:57:56.520234 in-header: 03 fc 00 00 01 00 00 00
8997 09:57:56.523553 in-data: 00
8998 09:57:56.526620 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8999 09:57:56.530373 in-header: 03 fd 00 00 00 00 00 00
9000 09:57:56.533595 in-data:
9001 09:57:56.536692 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9002 09:57:56.540449 in-header: 03 fc 00 00 01 00 00 00
9003 09:57:56.543953 in-data: 00
9004 09:57:56.547390 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9005 09:57:56.551866 in-header: 03 fd 00 00 00 00 00 00
9006 09:57:56.555009 in-data:
9007 09:57:56.558092 [SSUSB] Setting up USB HOST controller...
9008 09:57:56.561788 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9009 09:57:56.565133 [SSUSB] phy power-on done.
9010 09:57:56.568233 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9011 09:57:56.574709 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9012 09:57:56.578085 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9013 09:57:56.585086 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9014 09:57:56.591592 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9015 09:57:56.597835 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9016 09:57:56.604494 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9017 09:57:56.611218 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9018 09:57:56.614818 SPM: binary array size = 0x9dc
9019 09:57:56.617954 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9020 09:57:56.624473 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9021 09:57:56.631240 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9022 09:57:56.637507 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9023 09:57:56.640878 configure_display: Starting display init
9024 09:57:56.675039 anx7625_power_on_init: Init interface.
9025 09:57:56.678024 anx7625_disable_pd_protocol: Disabled PD feature.
9026 09:57:56.681853 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9027 09:57:56.709414 anx7625_start_dp_work: Secure OCM version=00
9028 09:57:56.712741 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9029 09:57:56.727326 sp_tx_get_edid_block: EDID Block = 1
9030 09:57:56.830116 Extracted contents:
9031 09:57:56.833430 header: 00 ff ff ff ff ff ff 00
9032 09:57:56.836473 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9033 09:57:56.839812 version: 01 04
9034 09:57:56.842953 basic params: 95 1f 11 78 0a
9035 09:57:56.846350 chroma info: 76 90 94 55 54 90 27 21 50 54
9036 09:57:56.849445 established: 00 00 00
9037 09:57:56.856057 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9038 09:57:56.859750 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9039 09:57:56.866220 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9040 09:57:56.873148 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9041 09:57:56.879425 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9042 09:57:56.882996 extensions: 00
9043 09:57:56.883550 checksum: fb
9044 09:57:56.883921
9045 09:57:56.885842 Manufacturer: IVO Model 57d Serial Number 0
9046 09:57:56.889399 Made week 0 of 2020
9047 09:57:56.892848 EDID version: 1.4
9048 09:57:56.893406 Digital display
9049 09:57:56.896105 6 bits per primary color channel
9050 09:57:56.896725 DisplayPort interface
9051 09:57:56.899245 Maximum image size: 31 cm x 17 cm
9052 09:57:56.902525 Gamma: 220%
9053 09:57:56.903079 Check DPMS levels
9054 09:57:56.909246 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9055 09:57:56.912735 First detailed timing is preferred timing
9056 09:57:56.913303 Established timings supported:
9057 09:57:56.916077 Standard timings supported:
9058 09:57:56.919101 Detailed timings
9059 09:57:56.922084 Hex of detail: 383680a07038204018303c0035ae10000019
9060 09:57:56.928924 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9061 09:57:56.932043 0780 0798 07c8 0820 hborder 0
9062 09:57:56.935687 0438 043b 0447 0458 vborder 0
9063 09:57:56.938904 -hsync -vsync
9064 09:57:56.939366 Did detailed timing
9065 09:57:56.945151 Hex of detail: 000000000000000000000000000000000000
9066 09:57:56.948592 Manufacturer-specified data, tag 0
9067 09:57:56.952273 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9068 09:57:56.955551 ASCII string: InfoVision
9069 09:57:56.958881 Hex of detail: 000000fe00523134304e574635205248200a
9070 09:57:56.962073 ASCII string: R140NWF5 RH
9071 09:57:56.962745 Checksum
9072 09:57:56.965058 Checksum: 0xfb (valid)
9073 09:57:56.968345 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9074 09:57:56.972022 DSI data_rate: 832800000 bps
9075 09:57:56.978499 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9076 09:57:56.982076 anx7625_parse_edid: pixelclock(138800).
9077 09:57:56.985450 hactive(1920), hsync(48), hfp(24), hbp(88)
9078 09:57:56.988776 vactive(1080), vsync(12), vfp(3), vbp(17)
9079 09:57:56.992247 anx7625_dsi_config: config dsi.
9080 09:57:56.998684 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9081 09:57:57.012217 anx7625_dsi_config: success to config DSI
9082 09:57:57.015720 anx7625_dp_start: MIPI phy setup OK.
9083 09:57:57.019154 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9084 09:57:57.022002 mtk_ddp_mode_set invalid vrefresh 60
9085 09:57:57.025324 main_disp_path_setup
9086 09:57:57.025799 ovl_layer_smi_id_en
9087 09:57:57.028442 ovl_layer_smi_id_en
9088 09:57:57.028931 ccorr_config
9089 09:57:57.029294 aal_config
9090 09:57:57.032212 gamma_config
9091 09:57:57.032808 postmask_config
9092 09:57:57.035289 dither_config
9093 09:57:57.038501 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9094 09:57:57.045039 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9095 09:57:57.048618 Root Device init finished in 551 msecs
9096 09:57:57.049082 CPU_CLUSTER: 0 init
9097 09:57:57.058339 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9098 09:57:57.061663 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9099 09:57:57.065008 APU_MBOX 0x190000b0 = 0x10001
9100 09:57:57.068623 APU_MBOX 0x190001b0 = 0x10001
9101 09:57:57.071762 APU_MBOX 0x190005b0 = 0x10001
9102 09:57:57.075129 APU_MBOX 0x190006b0 = 0x10001
9103 09:57:57.078098 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9104 09:57:57.090868 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9105 09:57:57.103120 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9106 09:57:57.110044 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9107 09:57:57.121626 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9108 09:57:57.130980 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9109 09:57:57.134307 CPU_CLUSTER: 0 init finished in 81 msecs
9110 09:57:57.137443 Devices initialized
9111 09:57:57.140454 Show all devs... After init.
9112 09:57:57.140975 Root Device: enabled 1
9113 09:57:57.144338 CPU_CLUSTER: 0: enabled 1
9114 09:57:57.147312 CPU: 00: enabled 1
9115 09:57:57.150867 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9116 09:57:57.153775 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9117 09:57:57.156963 ELOG: NV offset 0x57f000 size 0x1000
9118 09:57:57.163692 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9119 09:57:57.170593 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9120 09:57:57.173669 ELOG: Event(17) added with size 13 at 2023-11-24 09:57:59 UTC
9121 09:57:57.177335 out: cmd=0x121: 03 db 21 01 00 00 00 00
9122 09:57:57.181228 in-header: 03 0e 00 00 2c 00 00 00
9123 09:57:57.194762 in-data: 55 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9124 09:57:57.201088 ELOG: Event(A1) added with size 10 at 2023-11-24 09:57:59 UTC
9125 09:57:57.207871 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9126 09:57:57.214249 ELOG: Event(A0) added with size 9 at 2023-11-24 09:57:59 UTC
9127 09:57:57.217481 elog_add_boot_reason: Logged dev mode boot
9128 09:57:57.221420 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9129 09:57:57.224347 Finalize devices...
9130 09:57:57.224951 Devices finalized
9131 09:57:57.230976 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9132 09:57:57.234126 Writing coreboot table at 0xffe64000
9133 09:57:57.237489 0. 000000000010a000-0000000000113fff: RAMSTAGE
9134 09:57:57.240924 1. 0000000040000000-00000000400fffff: RAM
9135 09:57:57.247584 2. 0000000040100000-000000004032afff: RAMSTAGE
9136 09:57:57.250951 3. 000000004032b000-00000000545fffff: RAM
9137 09:57:57.253903 4. 0000000054600000-000000005465ffff: BL31
9138 09:57:57.257604 5. 0000000054660000-00000000ffe63fff: RAM
9139 09:57:57.263887 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9140 09:57:57.267448 7. 0000000100000000-000000013fffffff: RAM
9141 09:57:57.270189 Passing 5 GPIOs to payload:
9142 09:57:57.273629 NAME | PORT | POLARITY | VALUE
9143 09:57:57.277468 EC in RW | 0x000000aa | low | undefined
9144 09:57:57.284013 EC interrupt | 0x00000005 | low | undefined
9145 09:57:57.287409 TPM interrupt | 0x000000ab | high | undefined
9146 09:57:57.294117 SD card detect | 0x00000011 | high | undefined
9147 09:57:57.296982 speaker enable | 0x00000093 | high | undefined
9148 09:57:57.300693 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9149 09:57:57.303817 in-header: 03 f4 00 00 02 00 00 00
9150 09:57:57.307169 in-data: 07 00
9151 09:57:57.307725 ADC[4]: Raw value=668590 ID=5
9152 09:57:57.310671 ADC[3]: Raw value=212549 ID=1
9153 09:57:57.313444 RAM Code: 0x51
9154 09:57:57.313911 ADC[6]: Raw value=74410 ID=0
9155 09:57:57.317149 ADC[5]: Raw value=211444 ID=1
9156 09:57:57.320527 SKU Code: 0x1
9157 09:57:57.323556 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7e6
9158 09:57:57.327071 coreboot table: 964 bytes.
9159 09:57:57.330321 IMD ROOT 0. 0xfffff000 0x00001000
9160 09:57:57.333458 IMD SMALL 1. 0xffffe000 0x00001000
9161 09:57:57.336907 RO MCACHE 2. 0xffffc000 0x00001104
9162 09:57:57.339945 CONSOLE 3. 0xfff7c000 0x00080000
9163 09:57:57.343163 FMAP 4. 0xfff7b000 0x00000452
9164 09:57:57.346966 TIME STAMP 5. 0xfff7a000 0x00000910
9165 09:57:57.350077 VBOOT WORK 6. 0xfff66000 0x00014000
9166 09:57:57.353518 RAMOOPS 7. 0xffe66000 0x00100000
9167 09:57:57.356785 COREBOOT 8. 0xffe64000 0x00002000
9168 09:57:57.357243 IMD small region:
9169 09:57:57.360156 IMD ROOT 0. 0xffffec00 0x00000400
9170 09:57:57.363013 VPD 1. 0xffffeb80 0x0000006c
9171 09:57:57.369727 MMC STATUS 2. 0xffffeb60 0x00000004
9172 09:57:57.372850 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9173 09:57:57.376632 Probing TPM: done!
9174 09:57:57.379895 Connected to device vid:did:rid of 1ae0:0028:00
9175 09:57:57.390184 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9176 09:57:57.393118 Initialized TPM device CR50 revision 0
9177 09:57:57.396758 Checking cr50 for pending updates
9178 09:57:57.400445 Reading cr50 TPM mode
9179 09:57:57.409436 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9180 09:57:57.415928 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9181 09:57:57.456136 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9182 09:57:57.459234 Checking segment from ROM address 0x40100000
9183 09:57:57.462861 Checking segment from ROM address 0x4010001c
9184 09:57:57.469094 Loading segment from ROM address 0x40100000
9185 09:57:57.469557 code (compression=0)
9186 09:57:57.476246 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9187 09:57:57.486177 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9188 09:57:57.486745 it's not compressed!
9189 09:57:57.493139 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9190 09:57:57.495772 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9191 09:57:57.516659 Loading segment from ROM address 0x4010001c
9192 09:57:57.517215 Entry Point 0x80000000
9193 09:57:57.519435 Loaded segments
9194 09:57:57.523042 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9195 09:57:57.529846 Jumping to boot code at 0x80000000(0xffe64000)
9196 09:57:57.536115 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9197 09:57:57.542644 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9198 09:57:57.551162 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9199 09:57:57.554052 Checking segment from ROM address 0x40100000
9200 09:57:57.557588 Checking segment from ROM address 0x4010001c
9201 09:57:57.563900 Loading segment from ROM address 0x40100000
9202 09:57:57.564575 code (compression=1)
9203 09:57:57.570888 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9204 09:57:57.581125 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9205 09:57:57.581688 using LZMA
9206 09:57:57.589234 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9207 09:57:57.595842 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9208 09:57:57.599181 Loading segment from ROM address 0x4010001c
9209 09:57:57.599752 Entry Point 0x54601000
9210 09:57:57.602569 Loaded segments
9211 09:57:57.605765 NOTICE: MT8192 bl31_setup
9212 09:57:57.612705 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9213 09:57:57.616207 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9214 09:57:57.619362 WARNING: region 0:
9215 09:57:57.622826 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9216 09:57:57.623384 WARNING: region 1:
9217 09:57:57.629270 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9218 09:57:57.632650 WARNING: region 2:
9219 09:57:57.636203 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9220 09:57:57.639696 WARNING: region 3:
9221 09:57:57.642739 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9222 09:57:57.646115 WARNING: region 4:
9223 09:57:57.649669 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9224 09:57:57.652481 WARNING: region 5:
9225 09:57:57.656108 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9226 09:57:57.659482 WARNING: region 6:
9227 09:57:57.663008 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9228 09:57:57.663587 WARNING: region 7:
9229 09:57:57.669192 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9230 09:57:57.676054 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9231 09:57:57.679185 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9232 09:57:57.682736 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9233 09:57:57.689592 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9234 09:57:57.692738 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9235 09:57:57.696162 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9236 09:57:57.703138 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9237 09:57:57.706044 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9238 09:57:57.712824 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9239 09:57:57.716144 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9240 09:57:57.719996 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9241 09:57:57.726027 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9242 09:57:57.729267 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9243 09:57:57.732919 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9244 09:57:57.739558 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9245 09:57:57.742567 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9246 09:57:57.749270 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9247 09:57:57.752469 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9248 09:57:57.756069 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9249 09:57:57.763082 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9250 09:57:57.765727 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9251 09:57:57.769007 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9252 09:57:57.775523 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9253 09:57:57.779366 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9254 09:57:57.785950 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9255 09:57:57.788928 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9256 09:57:57.792649 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9257 09:57:57.799122 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9258 09:57:57.802573 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9259 09:57:57.808906 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9260 09:57:57.812620 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9261 09:57:57.815765 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9262 09:57:57.822576 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9263 09:57:57.825912 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9264 09:57:57.829355 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9265 09:57:57.832399 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9266 09:57:57.839222 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9267 09:57:57.842506 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9268 09:57:57.845778 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9269 09:57:57.849133 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9270 09:57:57.855649 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9271 09:57:57.859308 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9272 09:57:57.862587 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9273 09:57:57.865999 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9274 09:57:57.872190 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9275 09:57:57.875631 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9276 09:57:57.878914 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9277 09:57:57.882658 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9278 09:57:57.889292 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9279 09:57:57.892389 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9280 09:57:57.899198 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9281 09:57:57.902238 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9282 09:57:57.905993 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9283 09:57:57.912551 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9284 09:57:57.915810 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9285 09:57:57.922720 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9286 09:57:57.925617 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9287 09:57:57.932479 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9288 09:57:57.935713 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9289 09:57:57.942430 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9290 09:57:57.945270 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9291 09:57:57.948992 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9292 09:57:57.955623 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9293 09:57:57.959177 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9294 09:57:57.965208 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9295 09:57:57.969068 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9296 09:57:57.975627 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9297 09:57:57.979074 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9298 09:57:57.982188 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9299 09:57:57.988830 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9300 09:57:57.992097 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9301 09:57:57.998828 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9302 09:57:58.002301 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9303 09:57:58.008367 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9304 09:57:58.011889 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9305 09:57:58.018686 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9306 09:57:58.022324 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9307 09:57:58.025403 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9308 09:57:58.032107 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9309 09:57:58.035679 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9310 09:57:58.041786 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9311 09:57:58.045410 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9312 09:57:58.052223 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9313 09:57:58.055547 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9314 09:57:58.058944 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9315 09:57:58.065321 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9316 09:57:58.068643 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9317 09:57:58.075597 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9318 09:57:58.079202 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9319 09:57:58.085650 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9320 09:57:58.088911 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9321 09:57:58.092436 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9322 09:57:58.099022 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9323 09:57:58.102384 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9324 09:57:58.109121 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9325 09:57:58.112145 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9326 09:57:58.115372 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9327 09:57:58.122055 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9328 09:57:58.125382 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9329 09:57:58.128937 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9330 09:57:58.132105 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9331 09:57:58.138909 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9332 09:57:58.142048 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9333 09:57:58.148822 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9334 09:57:58.152339 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9335 09:57:58.155467 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9336 09:57:58.162163 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9337 09:57:58.165735 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9338 09:57:58.172370 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9339 09:57:58.175709 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9340 09:57:58.179029 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9341 09:57:58.185493 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9342 09:57:58.188979 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9343 09:57:58.195478 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9344 09:57:58.198777 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9345 09:57:58.201821 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9346 09:57:58.208643 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9347 09:57:58.212108 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9348 09:57:58.215234 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9349 09:57:58.218572 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9350 09:57:58.225453 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9351 09:57:58.229037 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9352 09:57:58.232321 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9353 09:57:58.235241 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9354 09:57:58.241855 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9355 09:57:58.245070 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9356 09:57:58.251815 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9357 09:57:58.255369 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9358 09:57:58.258772 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9359 09:57:58.265237 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9360 09:57:58.268816 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9361 09:57:58.275259 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9362 09:57:58.278646 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9363 09:57:58.282014 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9364 09:57:58.288862 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9365 09:57:58.291889 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9366 09:57:58.298557 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9367 09:57:58.302112 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9368 09:57:58.305366 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9369 09:57:58.312356 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9370 09:57:58.315550 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9371 09:57:58.318872 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9372 09:57:58.325389 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9373 09:57:58.329010 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9374 09:57:58.335154 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9375 09:57:58.338981 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9376 09:57:58.341830 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9377 09:57:58.348405 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9378 09:57:58.352185 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9379 09:57:58.358834 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9380 09:57:58.361917 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9381 09:57:58.365307 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9382 09:57:58.371921 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9383 09:57:58.375051 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9384 09:57:58.378443 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9385 09:57:58.386336 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9386 09:57:58.388401 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9387 09:57:58.395372 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9388 09:57:58.398240 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9389 09:57:58.401972 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9390 09:57:58.408371 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9391 09:57:58.411966 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9392 09:57:58.418149 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9393 09:57:58.422026 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9394 09:57:58.424886 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9395 09:57:58.431545 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9396 09:57:58.434710 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9397 09:57:58.441645 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9398 09:57:58.444579 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9399 09:57:58.448040 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9400 09:57:58.454707 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9401 09:57:58.457988 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9402 09:57:58.464784 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9403 09:57:58.467807 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9404 09:57:58.471234 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9405 09:57:58.477675 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9406 09:57:58.481270 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9407 09:57:58.487754 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9408 09:57:58.491195 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9409 09:57:58.494651 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9410 09:57:58.501416 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9411 09:57:58.505016 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9412 09:57:58.508038 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9413 09:57:58.514858 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9414 09:57:58.517800 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9415 09:57:58.524287 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9416 09:57:58.527682 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9417 09:57:58.530775 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9418 09:57:58.537465 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9419 09:57:58.540892 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9420 09:57:58.547310 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9421 09:57:58.551075 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9422 09:57:58.557569 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9423 09:57:58.560786 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9424 09:57:58.564167 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9425 09:57:58.570672 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9426 09:57:58.573963 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9427 09:57:58.580671 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9428 09:57:58.584092 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9429 09:57:58.590796 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9430 09:57:58.593983 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9431 09:57:58.597117 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9432 09:57:58.603842 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9433 09:57:58.607286 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9434 09:57:58.613852 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9435 09:57:58.617387 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9436 09:57:58.620199 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9437 09:57:58.627283 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9438 09:57:58.630575 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9439 09:57:58.637099 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9440 09:57:58.640305 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9441 09:57:58.646607 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9442 09:57:58.650267 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9443 09:57:58.653424 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9444 09:57:58.660194 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9445 09:57:58.663587 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9446 09:57:58.670134 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9447 09:57:58.673501 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9448 09:57:58.676668 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9449 09:57:58.683105 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9450 09:57:58.686940 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9451 09:57:58.693449 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9452 09:57:58.696372 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9453 09:57:58.703267 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9454 09:57:58.706743 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9455 09:57:58.709900 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9456 09:57:58.716622 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9457 09:57:58.719669 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9458 09:57:58.726246 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9459 09:57:58.729892 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9460 09:57:58.733179 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9461 09:57:58.736545 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9462 09:57:58.739738 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9463 09:57:58.746330 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9464 09:57:58.749760 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9465 09:57:58.756239 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9466 09:57:58.759655 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9467 09:57:58.763322 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9468 09:57:58.769416 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9469 09:57:58.772574 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9470 09:57:58.776351 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9471 09:57:58.782661 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9472 09:57:58.786345 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9473 09:57:58.789829 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9474 09:57:58.796084 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9475 09:57:58.799051 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9476 09:57:58.805881 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9477 09:57:58.809224 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9478 09:57:58.812707 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9479 09:57:58.819513 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9480 09:57:58.822514 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9481 09:57:58.825604 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9482 09:57:58.832470 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9483 09:57:58.835738 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9484 09:57:58.842234 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9485 09:57:58.845467 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9486 09:57:58.849096 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9487 09:57:58.855753 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9488 09:57:58.859258 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9489 09:57:58.862511 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9490 09:57:58.868798 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9491 09:57:58.872982 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9492 09:57:58.879198 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9493 09:57:58.882415 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9494 09:57:58.885532 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9495 09:57:58.892276 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9496 09:57:58.895749 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9497 09:57:58.899184 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9498 09:57:58.905521 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9499 09:57:58.908799 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9500 09:57:58.912291 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9501 09:57:58.915314 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9502 09:57:58.918603 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9503 09:57:58.925002 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9504 09:57:58.928551 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9505 09:57:58.931940 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9506 09:57:58.938132 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9507 09:57:58.941614 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9508 09:57:58.944754 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9509 09:57:58.948228 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9510 09:57:58.955066 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9511 09:57:58.958407 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9512 09:57:58.961256 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9513 09:57:58.968360 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9514 09:57:58.971681 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9515 09:57:58.978101 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9516 09:57:58.981453 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9517 09:57:58.985024 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9518 09:57:58.991544 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9519 09:57:58.994783 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9520 09:57:59.001349 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9521 09:57:59.004668 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9522 09:57:59.008022 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9523 09:57:59.014812 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9524 09:57:59.017729 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9525 09:57:59.024545 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9526 09:57:59.027848 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9527 09:57:59.031059 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9528 09:57:59.037923 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9529 09:57:59.041477 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9530 09:57:59.047756 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9531 09:57:59.051300 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9532 09:57:59.057605 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9533 09:57:59.061025 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9534 09:57:59.064418 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9535 09:57:59.071276 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9536 09:57:59.074050 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9537 09:57:59.080874 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9538 09:57:59.084157 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9539 09:57:59.087889 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9540 09:57:59.094261 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9541 09:57:59.097770 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9542 09:57:59.104038 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9543 09:57:59.107550 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9544 09:57:59.110651 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9545 09:57:59.117485 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9546 09:57:59.120902 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9547 09:57:59.127380 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9548 09:57:59.130759 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9549 09:57:59.137618 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9550 09:57:59.141147 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9551 09:57:59.143902 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9552 09:57:59.150684 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9553 09:57:59.153998 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9554 09:57:59.160413 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9555 09:57:59.163830 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9556 09:57:59.166919 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9557 09:57:59.173750 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9558 09:57:59.176912 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9559 09:57:59.183475 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9560 09:57:59.186970 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9561 09:57:59.190293 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9562 09:57:59.196849 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9563 09:57:59.200045 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9564 09:57:59.207003 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9565 09:57:59.210273 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9566 09:57:59.216649 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9567 09:57:59.220045 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9568 09:57:59.223611 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9569 09:57:59.230038 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9570 09:57:59.233419 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9571 09:57:59.239765 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9572 09:57:59.243234 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9573 09:57:59.246359 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9574 09:57:59.253169 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9575 09:57:59.256712 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9576 09:57:59.263204 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9577 09:57:59.266718 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9578 09:57:59.269682 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9579 09:57:59.276446 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9580 09:57:59.279875 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9581 09:57:59.286420 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9582 09:57:59.289449 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9583 09:57:59.292789 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9584 09:57:59.299484 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9585 09:57:59.302709 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9586 09:57:59.309362 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9587 09:57:59.312432 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9588 09:57:59.319460 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9589 09:57:59.322311 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9590 09:57:59.329252 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9591 09:57:59.332676 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9592 09:57:59.335954 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9593 09:57:59.342637 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9594 09:57:59.345974 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9595 09:57:59.352145 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9596 09:57:59.355601 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9597 09:57:59.362102 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9598 09:57:59.365440 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9599 09:57:59.372050 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9600 09:57:59.375109 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9601 09:57:59.381931 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9602 09:57:59.385112 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9603 09:57:59.388863 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9604 09:57:59.395233 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9605 09:57:59.398582 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9606 09:57:59.405496 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9607 09:57:59.408208 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9608 09:57:59.415272 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9609 09:57:59.418690 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9610 09:57:59.421766 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9611 09:57:59.429094 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9612 09:57:59.431581 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9613 09:57:59.438360 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9614 09:57:59.441544 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9615 09:57:59.448232 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9616 09:57:59.451585 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9617 09:57:59.457982 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9618 09:57:59.461577 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9619 09:57:59.464622 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9620 09:57:59.471260 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9621 09:57:59.474341 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9622 09:57:59.481169 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9623 09:57:59.484350 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9624 09:57:59.491159 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9625 09:57:59.494741 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9626 09:57:59.497837 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9627 09:57:59.504546 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9628 09:57:59.507968 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9629 09:57:59.514386 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9630 09:57:59.517452 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9631 09:57:59.524665 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9632 09:57:59.527350 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9633 09:57:59.530426 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9634 09:57:59.537567 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9635 09:57:59.540790 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9636 09:57:59.547105 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9637 09:57:59.550257 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9638 09:57:59.557128 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9639 09:57:59.560620 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9640 09:57:59.567169 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9641 09:57:59.570188 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9642 09:57:59.577161 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9643 09:57:59.580459 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9644 09:57:59.587327 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9645 09:57:59.589952 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9646 09:57:59.597286 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9647 09:57:59.600461 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9648 09:57:59.606871 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9649 09:57:59.609883 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9650 09:57:59.616837 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9651 09:57:59.619892 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9652 09:57:59.626488 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9653 09:57:59.629835 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9654 09:57:59.636433 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9655 09:57:59.640055 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9656 09:57:59.646656 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9657 09:57:59.649581 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9658 09:57:59.656230 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9659 09:57:59.659442 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9660 09:57:59.666260 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9661 09:57:59.669837 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9662 09:57:59.676076 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9663 09:57:59.679214 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9664 09:57:59.685658 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9665 09:57:59.686274 INFO: [APUAPC] vio 0
9666 09:57:59.692692 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9667 09:57:59.695796 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9668 09:57:59.699381 INFO: [APUAPC] D0_APC_0: 0x400510
9669 09:57:59.702462 INFO: [APUAPC] D0_APC_1: 0x0
9670 09:57:59.705725 INFO: [APUAPC] D0_APC_2: 0x1540
9671 09:57:59.709211 INFO: [APUAPC] D0_APC_3: 0x0
9672 09:57:59.712665 INFO: [APUAPC] D1_APC_0: 0xffffffff
9673 09:57:59.715853 INFO: [APUAPC] D1_APC_1: 0xffffffff
9674 09:57:59.718840 INFO: [APUAPC] D1_APC_2: 0x3fffff
9675 09:57:59.721942 INFO: [APUAPC] D1_APC_3: 0x0
9676 09:57:59.725729 INFO: [APUAPC] D2_APC_0: 0xffffffff
9677 09:57:59.728819 INFO: [APUAPC] D2_APC_1: 0xffffffff
9678 09:57:59.732166 INFO: [APUAPC] D2_APC_2: 0x3fffff
9679 09:57:59.735367 INFO: [APUAPC] D2_APC_3: 0x0
9680 09:57:59.738951 INFO: [APUAPC] D3_APC_0: 0xffffffff
9681 09:57:59.742125 INFO: [APUAPC] D3_APC_1: 0xffffffff
9682 09:57:59.745527 INFO: [APUAPC] D3_APC_2: 0x3fffff
9683 09:57:59.748999 INFO: [APUAPC] D3_APC_3: 0x0
9684 09:57:59.751702 INFO: [APUAPC] D4_APC_0: 0xffffffff
9685 09:57:59.755193 INFO: [APUAPC] D4_APC_1: 0xffffffff
9686 09:57:59.758580 INFO: [APUAPC] D4_APC_2: 0x3fffff
9687 09:57:59.762354 INFO: [APUAPC] D4_APC_3: 0x0
9688 09:57:59.765212 INFO: [APUAPC] D5_APC_0: 0xffffffff
9689 09:57:59.768709 INFO: [APUAPC] D5_APC_1: 0xffffffff
9690 09:57:59.772038 INFO: [APUAPC] D5_APC_2: 0x3fffff
9691 09:57:59.772672 INFO: [APUAPC] D5_APC_3: 0x0
9692 09:57:59.778292 INFO: [APUAPC] D6_APC_0: 0xffffffff
9693 09:57:59.781608 INFO: [APUAPC] D6_APC_1: 0xffffffff
9694 09:57:59.785064 INFO: [APUAPC] D6_APC_2: 0x3fffff
9695 09:57:59.785602 INFO: [APUAPC] D6_APC_3: 0x0
9696 09:57:59.788849 INFO: [APUAPC] D7_APC_0: 0xffffffff
9697 09:57:59.795292 INFO: [APUAPC] D7_APC_1: 0xffffffff
9698 09:57:59.795852 INFO: [APUAPC] D7_APC_2: 0x3fffff
9699 09:57:59.798416 INFO: [APUAPC] D7_APC_3: 0x0
9700 09:57:59.802045 INFO: [APUAPC] D8_APC_0: 0xffffffff
9701 09:57:59.804889 INFO: [APUAPC] D8_APC_1: 0xffffffff
9702 09:57:59.808193 INFO: [APUAPC] D8_APC_2: 0x3fffff
9703 09:57:59.811653 INFO: [APUAPC] D8_APC_3: 0x0
9704 09:57:59.815470 INFO: [APUAPC] D9_APC_0: 0xffffffff
9705 09:57:59.818031 INFO: [APUAPC] D9_APC_1: 0xffffffff
9706 09:57:59.821169 INFO: [APUAPC] D9_APC_2: 0x3fffff
9707 09:57:59.824913 INFO: [APUAPC] D9_APC_3: 0x0
9708 09:57:59.828008 INFO: [APUAPC] D10_APC_0: 0xffffffff
9709 09:57:59.831445 INFO: [APUAPC] D10_APC_1: 0xffffffff
9710 09:57:59.834512 INFO: [APUAPC] D10_APC_2: 0x3fffff
9711 09:57:59.838219 INFO: [APUAPC] D10_APC_3: 0x0
9712 09:57:59.841451 INFO: [APUAPC] D11_APC_0: 0xffffffff
9713 09:57:59.844645 INFO: [APUAPC] D11_APC_1: 0xffffffff
9714 09:57:59.848035 INFO: [APUAPC] D11_APC_2: 0x3fffff
9715 09:57:59.851273 INFO: [APUAPC] D11_APC_3: 0x0
9716 09:57:59.854284 INFO: [APUAPC] D12_APC_0: 0xffffffff
9717 09:57:59.857574 INFO: [APUAPC] D12_APC_1: 0xffffffff
9718 09:57:59.864393 INFO: [APUAPC] D12_APC_2: 0x3fffff
9719 09:57:59.865024 INFO: [APUAPC] D12_APC_3: 0x0
9720 09:57:59.867526 INFO: [APUAPC] D13_APC_0: 0xffffffff
9721 09:57:59.874293 INFO: [APUAPC] D13_APC_1: 0xffffffff
9722 09:57:59.877456 INFO: [APUAPC] D13_APC_2: 0x3fffff
9723 09:57:59.877990 INFO: [APUAPC] D13_APC_3: 0x0
9724 09:57:59.884432 INFO: [APUAPC] D14_APC_0: 0xffffffff
9725 09:57:59.887593 INFO: [APUAPC] D14_APC_1: 0xffffffff
9726 09:57:59.890633 INFO: [APUAPC] D14_APC_2: 0x3fffff
9727 09:57:59.891192 INFO: [APUAPC] D14_APC_3: 0x0
9728 09:57:59.897212 INFO: [APUAPC] D15_APC_0: 0xffffffff
9729 09:57:59.900888 INFO: [APUAPC] D15_APC_1: 0xffffffff
9730 09:57:59.903886 INFO: [APUAPC] D15_APC_2: 0x3fffff
9731 09:57:59.907465 INFO: [APUAPC] D15_APC_3: 0x0
9732 09:57:59.908021 INFO: [APUAPC] APC_CON: 0x4
9733 09:57:59.910458 INFO: [NOCDAPC] D0_APC_0: 0x0
9734 09:57:59.913889 INFO: [NOCDAPC] D0_APC_1: 0x0
9735 09:57:59.917037 INFO: [NOCDAPC] D1_APC_0: 0x0
9736 09:57:59.920584 INFO: [NOCDAPC] D1_APC_1: 0xfff
9737 09:57:59.923537 INFO: [NOCDAPC] D2_APC_0: 0x0
9738 09:57:59.927610 INFO: [NOCDAPC] D2_APC_1: 0xfff
9739 09:57:59.930831 INFO: [NOCDAPC] D3_APC_0: 0x0
9740 09:57:59.933836 INFO: [NOCDAPC] D3_APC_1: 0xfff
9741 09:57:59.934411 INFO: [NOCDAPC] D4_APC_0: 0x0
9742 09:57:59.937344 INFO: [NOCDAPC] D4_APC_1: 0xfff
9743 09:57:59.940614 INFO: [NOCDAPC] D5_APC_0: 0x0
9744 09:57:59.943677 INFO: [NOCDAPC] D5_APC_1: 0xfff
9745 09:57:59.947409 INFO: [NOCDAPC] D6_APC_0: 0x0
9746 09:57:59.950436 INFO: [NOCDAPC] D6_APC_1: 0xfff
9747 09:57:59.953795 INFO: [NOCDAPC] D7_APC_0: 0x0
9748 09:57:59.957185 INFO: [NOCDAPC] D7_APC_1: 0xfff
9749 09:57:59.960056 INFO: [NOCDAPC] D8_APC_0: 0x0
9750 09:57:59.963911 INFO: [NOCDAPC] D8_APC_1: 0xfff
9751 09:57:59.967150 INFO: [NOCDAPC] D9_APC_0: 0x0
9752 09:57:59.967711 INFO: [NOCDAPC] D9_APC_1: 0xfff
9753 09:57:59.970420 INFO: [NOCDAPC] D10_APC_0: 0x0
9754 09:57:59.973395 INFO: [NOCDAPC] D10_APC_1: 0xfff
9755 09:57:59.977118 INFO: [NOCDAPC] D11_APC_0: 0x0
9756 09:57:59.980335 INFO: [NOCDAPC] D11_APC_1: 0xfff
9757 09:57:59.984071 INFO: [NOCDAPC] D12_APC_0: 0x0
9758 09:57:59.986610 INFO: [NOCDAPC] D12_APC_1: 0xfff
9759 09:57:59.990392 INFO: [NOCDAPC] D13_APC_0: 0x0
9760 09:57:59.993930 INFO: [NOCDAPC] D13_APC_1: 0xfff
9761 09:57:59.997149 INFO: [NOCDAPC] D14_APC_0: 0x0
9762 09:58:00.000131 INFO: [NOCDAPC] D14_APC_1: 0xfff
9763 09:58:00.003851 INFO: [NOCDAPC] D15_APC_0: 0x0
9764 09:58:00.006894 INFO: [NOCDAPC] D15_APC_1: 0xfff
9765 09:58:00.009972 INFO: [NOCDAPC] APC_CON: 0x4
9766 09:58:00.013648 INFO: [APUAPC] set_apusys_apc done
9767 09:58:00.016627 INFO: [DEVAPC] devapc_init done
9768 09:58:00.019997 INFO: GICv3 without legacy support detected.
9769 09:58:00.023188 INFO: ARM GICv3 driver initialized in EL3
9770 09:58:00.026496 INFO: Maximum SPI INTID supported: 639
9771 09:58:00.029790 INFO: BL31: Initializing runtime services
9772 09:58:00.036423 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9773 09:58:00.039872 INFO: SPM: enable CPC mode
9774 09:58:00.043045 INFO: mcdi ready for mcusys-off-idle and system suspend
9775 09:58:00.049635 INFO: BL31: Preparing for EL3 exit to normal world
9776 09:58:00.053399 INFO: Entry point address = 0x80000000
9777 09:58:00.055859 INFO: SPSR = 0x8
9778 09:58:00.060900
9779 09:58:00.061678
9780 09:58:00.062078
9781 09:58:00.063625 Starting depthcharge on Spherion...
9782 09:58:00.064088
9783 09:58:00.064454 Wipe memory regions:
9784 09:58:00.064862
9785 09:58:00.067394 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9786 09:58:00.067933 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9787 09:58:00.069703 Setting prompt string to ['asurada:']
9788 09:58:00.070244 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9789 09:58:00.070989 [0x00000040000000, 0x00000054600000)
9790 09:58:00.190109
9791 09:58:00.190665 [0x00000054660000, 0x00000080000000)
9792 09:58:00.450376
9793 09:58:00.450931 [0x000000821a7280, 0x000000ffe64000)
9794 09:58:01.194862
9795 09:58:01.195409 [0x00000100000000, 0x00000140000000)
9796 09:58:01.576094
9797 09:58:01.578957 Initializing XHCI USB controller at 0x11200000.
9798 09:58:02.617079
9799 09:58:02.620362 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9800 09:58:02.620971
9801 09:58:02.621343
9802 09:58:02.621683
9803 09:58:02.622477 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9805 09:58:02.723827 asurada: tftpboot 192.168.201.1 12073278/tftp-deploy-v4nqla42/kernel/image.itb 12073278/tftp-deploy-v4nqla42/kernel/cmdline
9806 09:58:02.724477 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9807 09:58:02.725008 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9808 09:58:02.729727 tftpboot 192.168.201.1 12073278/tftp-deploy-v4nqla42/kernel/image.ittp-deploy-v4nqla42/kernel/cmdline
9809 09:58:02.730308
9810 09:58:02.730679 Waiting for link
9811 09:58:02.889987
9812 09:58:02.890546 R8152: Initializing
9813 09:58:02.890920
9814 09:58:02.893004 Version 9 (ocp_data = 6010)
9815 09:58:02.893467
9816 09:58:02.896797 R8152: Done initializing
9817 09:58:02.897356
9818 09:58:02.897732 Adding net device
9819 09:58:04.904814
9820 09:58:04.905363 done.
9821 09:58:04.905730
9822 09:58:04.906071 MAC: 00:e0:4c:68:03:bd
9823 09:58:04.906400
9824 09:58:04.907963 Sending DHCP discover... done.
9825 09:58:04.908419
9826 09:58:15.032799 Waiting for reply... R8152: Bulk read error 0xffffffbf
9827 09:58:15.033432
9828 09:58:15.035679 Receive failed.
9829 09:58:15.036188
9830 09:58:15.036627 done.
9831 09:58:15.036990
9832 09:58:15.038841 Sending DHCP request... done.
9833 09:58:15.039432
9834 09:58:15.045778 Waiting for reply... done.
9835 09:58:15.046239
9836 09:58:15.046601 My ip is 192.168.201.16
9837 09:58:15.046935
9838 09:58:15.049096 The DHCP server ip is 192.168.201.1
9839 09:58:15.049556
9840 09:58:15.055573 TFTP server IP predefined by user: 192.168.201.1
9841 09:58:15.056029
9842 09:58:15.062866 Bootfile predefined by user: 12073278/tftp-deploy-v4nqla42/kernel/image.itb
9843 09:58:15.063429
9844 09:58:15.065611 Sending tftp read request... done.
9845 09:58:15.066065
9846 09:58:15.072343 Waiting for the transfer...
9847 09:58:15.072892
9848 09:58:15.375722 00000000 ################################################################
9849 09:58:15.375868
9850 09:58:15.657257 00080000 ################################################################
9851 09:58:15.657423
9852 09:58:15.937997 00100000 ################################################################
9853 09:58:15.938140
9854 09:58:16.225912 00180000 ################################################################
9855 09:58:16.226057
9856 09:58:16.522741 00200000 ################################################################
9857 09:58:16.523263
9858 09:58:16.838499 00280000 ################################################################
9859 09:58:16.838641
9860 09:58:17.088840 00300000 ################################################################
9861 09:58:17.088975
9862 09:58:17.368495 00380000 ################################################################
9863 09:58:17.368665
9864 09:58:17.618650 00400000 ################################################################
9865 09:58:17.618783
9866 09:58:17.895940 00480000 ################################################################
9867 09:58:17.896072
9868 09:58:18.185434 00500000 ################################################################
9869 09:58:18.185572
9870 09:58:18.551982 00580000 ################################################################
9871 09:58:18.552590
9872 09:58:18.970852 00600000 ################################################################
9873 09:58:18.971388
9874 09:58:19.383837 00680000 ################################################################
9875 09:58:19.384369
9876 09:58:19.767836 00700000 ################################################################
9877 09:58:19.767986
9878 09:58:20.106442 00780000 ################################################################
9879 09:58:20.106956
9880 09:58:20.533958 00800000 ################################################################
9881 09:58:20.534569
9882 09:58:20.954107 00880000 ################################################################
9883 09:58:20.954637
9884 09:58:21.395238 00900000 ################################################################
9885 09:58:21.395802
9886 09:58:21.695358 00980000 ################################################################
9887 09:58:21.695522
9888 09:58:21.951286 00a00000 ################################################################
9889 09:58:21.951432
9890 09:58:22.214472 00a80000 ################################################################
9891 09:58:22.214620
9892 09:58:22.484991 00b00000 ################################################################
9893 09:58:22.485136
9894 09:58:22.737931 00b80000 ################################################################
9895 09:58:22.738082
9896 09:58:23.003136 00c00000 ################################################################
9897 09:58:23.003284
9898 09:58:23.282349 00c80000 ################################################################
9899 09:58:23.282498
9900 09:58:23.562033 00d00000 ################################################################
9901 09:58:23.562181
9902 09:58:23.854316 00d80000 ################################################################
9903 09:58:23.854461
9904 09:58:24.147204 00e00000 ################################################################
9905 09:58:24.147351
9906 09:58:24.431199 00e80000 ################################################################
9907 09:58:24.431348
9908 09:58:24.718204 00f00000 ################################################################
9909 09:58:24.718370
9910 09:58:25.013501 00f80000 ################################################################
9911 09:58:25.013652
9912 09:58:25.301921 01000000 ################################################################
9913 09:58:25.302069
9914 09:58:25.553663 01080000 ################################################################
9915 09:58:25.553808
9916 09:58:25.826808 01100000 ################################################################
9917 09:58:25.826956
9918 09:58:26.123708 01180000 ################################################################
9919 09:58:26.123856
9920 09:58:26.402773 01200000 ################################################################
9921 09:58:26.402950
9922 09:58:26.665662 01280000 ################################################################
9923 09:58:26.665855
9924 09:58:26.929401 01300000 ################################################################
9925 09:58:26.929590
9926 09:58:27.207309 01380000 ################################################################
9927 09:58:27.207495
9928 09:58:27.484414 01400000 ################################################################
9929 09:58:27.484603
9930 09:58:27.736885 01480000 ################################################################
9931 09:58:27.737036
9932 09:58:27.990002 01500000 ################################################################
9933 09:58:27.990153
9934 09:58:28.269787 01580000 ################################################################
9935 09:58:28.269938
9936 09:58:28.568966 01600000 ################################################################
9937 09:58:28.569115
9938 09:58:28.869801 01680000 ################################################################
9939 09:58:28.869949
9940 09:58:29.167769 01700000 ################################################################
9941 09:58:29.167910
9942 09:58:29.449851 01780000 ################################################################
9943 09:58:29.449997
9944 09:58:29.729567 01800000 ################################################################
9945 09:58:29.729712
9946 09:58:30.007370 01880000 ################################################################
9947 09:58:30.007518
9948 09:58:30.289375 01900000 ################################################################
9949 09:58:30.289525
9950 09:58:30.570525 01980000 ################################################################
9951 09:58:30.570672
9952 09:58:30.855112 01a00000 ################################################################
9953 09:58:30.855264
9954 09:58:31.134150 01a80000 ################################################################
9955 09:58:31.134301
9956 09:58:31.423032 01b00000 ################################################################
9957 09:58:31.423181
9958 09:58:31.454038 01b80000 ######## done.
9959 09:58:31.454149
9960 09:58:31.457507 The bootfile was 28896882 bytes long.
9961 09:58:31.457591
9962 09:58:31.460657 Sending tftp read request... done.
9963 09:58:31.460748
9964 09:58:31.464259 Waiting for the transfer...
9965 09:58:31.464343
9966 09:58:31.464408 00000000 # done.
9967 09:58:31.467395
9968 09:58:31.474060 Command line loaded dynamically from TFTP file: 12073278/tftp-deploy-v4nqla42/kernel/cmdline
9969 09:58:31.474144
9970 09:58:31.496742 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12073278/extract-nfsrootfs-ycmyc54y,tcp,hard ip=dhcp tftpserverip=192.168.201.1
9971 09:58:31.496860
9972 09:58:31.496929 Loading FIT.
9973 09:58:31.496991
9974 09:58:31.500251 Image ramdisk-1 has 17800026 bytes.
9975 09:58:31.500334
9976 09:58:31.503409 Image fdt-1 has 47278 bytes.
9977 09:58:31.503492
9978 09:58:31.506833 Image kernel-1 has 11047542 bytes.
9979 09:58:31.506916
9980 09:58:31.513288 Compat preference: google,spherion-rev7-sku1 google,spherion-rev7 google,spherion-sku1 google,spherion
9981 09:58:31.513372
9982 09:58:31.533228 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion (match) mediatek,mt8192
9983 09:58:31.533325
9984 09:58:31.536411 Choosing best match conf-1 for compat google,spherion.
9985 09:58:31.541034
9986 09:58:31.545763 Connected to device vid:did:rid of 1ae0:0028:00
9987 09:58:31.552709
9988 09:58:31.556309 tpm_get_response: command 0x17b, return code 0x0
9989 09:58:31.556391
9990 09:58:31.559461 ec_init: CrosEC protocol v3 supported (256, 248)
9991 09:58:31.564057
9992 09:58:31.567216 tpm_cleanup: add release locality here.
9993 09:58:31.567300
9994 09:58:31.567366 Shutting down all USB controllers.
9995 09:58:31.570473
9996 09:58:31.570554 Removing current net device
9997 09:58:31.570620
9998 09:58:31.577237 Exiting depthcharge with code 4 at timestamp: 59717026
9999 09:58:31.577321
10000 09:58:31.580452 LZMA decompressing kernel-1 to 0x821a6718
10001 09:58:31.580576
10002 09:58:31.583795 LZMA decompressing kernel-1 to 0x40000000
10003 09:58:32.972326
10004 09:58:32.972883 jumping to kernel
10005 09:58:32.974854 end: 2.2.4 bootloader-commands (duration 00:00:33) [common]
10006 09:58:32.975361 start: 2.2.5 auto-login-action (timeout 00:03:53) [common]
10007 09:58:32.975737 Setting prompt string to ['Linux version [0-9]']
10008 09:58:32.976082 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10009 09:58:32.976433 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10010 09:58:33.022435
10011 09:58:33.025775 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10012 09:58:33.029410 start: 2.2.5.1 login-action (timeout 00:03:53) [common]
10013 09:58:33.029886 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10014 09:58:33.030247 Setting prompt string to []
10015 09:58:33.030624 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10016 09:58:33.030978 Using line separator: #'\n'#
10017 09:58:33.031286 No login prompt set.
10018 09:58:33.031597 Parsing kernel messages
10019 09:58:33.031880 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10020 09:58:33.032388 [login-action] Waiting for messages, (timeout 00:03:53)
10021 09:58:33.048904 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j22848-arm64-gcc-10-defconfig-arm64-chromebook-6q8mw) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Nov 24 09:44:51 UTC 2023
10022 09:58:33.052056 [ 0.000000] random: crng init done
10023 09:58:33.058751 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10024 09:58:33.061986 [ 0.000000] efi: UEFI not found.
10025 09:58:33.068525 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10026 09:58:33.075266 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10027 09:58:33.085044 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10028 09:58:33.095153 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10029 09:58:33.101922 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10030 09:58:33.108741 [ 0.000000] printk: bootconsole [mtk8250] enabled
10031 09:58:33.115507 [ 0.000000] NUMA: No NUMA configuration found
10032 09:58:33.121497 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10033 09:58:33.124995 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d4a00-0x13f7d6fff]
10034 09:58:33.128441 [ 0.000000] Zone ranges:
10035 09:58:33.135321 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10036 09:58:33.138370 [ 0.000000] DMA32 empty
10037 09:58:33.144861 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10038 09:58:33.147812 [ 0.000000] Movable zone start for each node
10039 09:58:33.151008 [ 0.000000] Early memory node ranges
10040 09:58:33.157769 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10041 09:58:33.164447 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10042 09:58:33.171108 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10043 09:58:33.177591 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10044 09:58:33.183796 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10045 09:58:33.190821 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10046 09:58:33.220955 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10047 09:58:33.227613 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10048 09:58:33.234463 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10049 09:58:33.237478 [ 0.000000] psci: probing for conduit method from DT.
10050 09:58:33.243893 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10051 09:58:33.247444 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10052 09:58:33.254121 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10053 09:58:33.257090 [ 0.000000] psci: SMC Calling Convention v1.2
10054 09:58:33.264137 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10055 09:58:33.267402 [ 0.000000] Detected VIPT I-cache on CPU0
10056 09:58:33.273899 [ 0.000000] CPU features: detected: GIC system register CPU interface
10057 09:58:33.280341 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10058 09:58:33.286760 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10059 09:58:33.293823 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10060 09:58:33.303801 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10061 09:58:33.310018 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10062 09:58:33.313137 [ 0.000000] alternatives: applying boot alternatives
10063 09:58:33.320045 [ 0.000000] Fallback order for Node 0: 0
10064 09:58:33.326518 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10065 09:58:33.330086 [ 0.000000] Policy zone: Normal
10066 09:58:33.353238 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12073278/extract-nfsrootfs-ycmyc54y,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10067 09:58:33.363119 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10068 09:58:33.373345 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10069 09:58:33.379840 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10070 09:58:33.386406 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10071 09:58:33.393054 <6>[ 0.000000] software IO TLB: area num 8.
10072 09:58:33.448089 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10073 09:58:33.528127 <6>[ 0.000000] Memory: 3837824K/4191232K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 320640K reserved, 32768K cma-reserved)
10074 09:58:33.534644 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10075 09:58:33.541265 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10076 09:58:33.544622 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10077 09:58:33.551066 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10078 09:58:33.557803 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10079 09:58:33.560789 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10080 09:58:33.570861 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10081 09:58:33.577472 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10082 09:58:33.584299 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10083 09:58:33.590581 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10084 09:58:33.593954 <6>[ 0.000000] GICv3: 608 SPIs implemented
10085 09:58:33.597339 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10086 09:58:33.604010 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10087 09:58:33.607264 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10088 09:58:33.613847 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10089 09:58:33.626870 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10090 09:58:33.640331 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10091 09:58:33.646713 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10092 09:58:33.654528 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10093 09:58:33.667532 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10094 09:58:33.673770 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10095 09:58:33.681049 <6>[ 0.009180] Console: colour dummy device 80x25
10096 09:58:33.690748 <6>[ 0.013905] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10097 09:58:33.697271 <6>[ 0.024346] pid_max: default: 32768 minimum: 301
10098 09:58:33.700464 <6>[ 0.029248] LSM: Security Framework initializing
10099 09:58:33.707442 <6>[ 0.034159] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10100 09:58:33.717145 <6>[ 0.041766] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10101 09:58:33.724021 <6>[ 0.050985] cblist_init_generic: Setting adjustable number of callback queues.
10102 09:58:33.730844 <6>[ 0.058428] cblist_init_generic: Setting shift to 3 and lim to 1.
10103 09:58:33.740595 <6>[ 0.064765] cblist_init_generic: Setting adjustable number of callback queues.
10104 09:58:33.743841 <6>[ 0.072192] cblist_init_generic: Setting shift to 3 and lim to 1.
10105 09:58:33.750607 <6>[ 0.078591] rcu: Hierarchical SRCU implementation.
10106 09:58:33.757029 <6>[ 0.083636] rcu: Max phase no-delay instances is 1000.
10107 09:58:33.763583 <6>[ 0.090655] EFI services will not be available.
10108 09:58:33.766955 <6>[ 0.095635] smp: Bringing up secondary CPUs ...
10109 09:58:33.775223 <6>[ 0.100677] Detected VIPT I-cache on CPU1
10110 09:58:33.781425 <6>[ 0.100746] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10111 09:58:33.787727 <6>[ 0.100776] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10112 09:58:33.791230 <6>[ 0.101102] Detected VIPT I-cache on CPU2
10113 09:58:33.800901 <6>[ 0.101151] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10114 09:58:33.807423 <6>[ 0.101168] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10115 09:58:33.811016 <6>[ 0.101423] Detected VIPT I-cache on CPU3
10116 09:58:33.817835 <6>[ 0.101469] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10117 09:58:33.824014 <6>[ 0.101482] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10118 09:58:33.830756 <6>[ 0.101782] CPU features: detected: Spectre-v4
10119 09:58:33.834092 <6>[ 0.101788] CPU features: detected: Spectre-BHB
10120 09:58:33.837272 <6>[ 0.101793] Detected PIPT I-cache on CPU4
10121 09:58:33.844663 <6>[ 0.101850] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10122 09:58:33.850456 <6>[ 0.101867] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10123 09:58:33.857263 <6>[ 0.102158] Detected PIPT I-cache on CPU5
10124 09:58:33.863984 <6>[ 0.102221] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10125 09:58:33.870592 <6>[ 0.102237] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10126 09:58:33.873987 <6>[ 0.102516] Detected PIPT I-cache on CPU6
10127 09:58:33.880413 <6>[ 0.102578] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10128 09:58:33.886930 <6>[ 0.102594] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10129 09:58:33.893555 <6>[ 0.102892] Detected PIPT I-cache on CPU7
10130 09:58:33.900283 <6>[ 0.102956] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10131 09:58:33.906808 <6>[ 0.102972] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10132 09:58:33.910224 <6>[ 0.103019] smp: Brought up 1 node, 8 CPUs
10133 09:58:33.916856 <6>[ 0.244371] SMP: Total of 8 processors activated.
10134 09:58:33.919989 <6>[ 0.249322] CPU features: detected: 32-bit EL0 Support
10135 09:58:33.930038 <6>[ 0.254684] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10136 09:58:33.936907 <6>[ 0.263484] CPU features: detected: Common not Private translations
10137 09:58:33.943009 <6>[ 0.269999] CPU features: detected: CRC32 instructions
10138 09:58:33.946235 <6>[ 0.275351] CPU features: detected: RCpc load-acquire (LDAPR)
10139 09:58:33.953406 <6>[ 0.281310] CPU features: detected: LSE atomic instructions
10140 09:58:33.959885 <6>[ 0.287092] CPU features: detected: Privileged Access Never
10141 09:58:33.966277 <6>[ 0.292871] CPU features: detected: RAS Extension Support
10142 09:58:33.973119 <6>[ 0.298515] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10143 09:58:33.976233 <6>[ 0.305778] CPU: All CPU(s) started at EL2
10144 09:58:33.982959 <6>[ 0.310121] alternatives: applying system-wide alternatives
10145 09:58:33.991516 <6>[ 0.320044] devtmpfs: initialized
10146 09:58:34.006974 <6>[ 0.328296] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10147 09:58:34.012923 <6>[ 0.338252] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10148 09:58:34.019590 <6>[ 0.346465] pinctrl core: initialized pinctrl subsystem
10149 09:58:34.023084 <6>[ 0.353127] DMI not present or invalid.
10150 09:58:34.029311 <6>[ 0.357530] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10151 09:58:34.039680 <6>[ 0.364413] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10152 09:58:34.046087 <6>[ 0.371845] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10153 09:58:34.056234 <6>[ 0.379935] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10154 09:58:34.059584 <6>[ 0.388090] audit: initializing netlink subsys (disabled)
10155 09:58:34.069407 <5>[ 0.393782] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10156 09:58:34.075886 <6>[ 0.394476] thermal_sys: Registered thermal governor 'step_wise'
10157 09:58:34.082314 <6>[ 0.401749] thermal_sys: Registered thermal governor 'power_allocator'
10158 09:58:34.085457 <6>[ 0.408004] cpuidle: using governor menu
10159 09:58:34.091988 <6>[ 0.418963] NET: Registered PF_QIPCRTR protocol family
10160 09:58:34.099111 <6>[ 0.424455] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10161 09:58:34.105166 <6>[ 0.431558] ASID allocator initialised with 32768 entries
10162 09:58:34.108582 <6>[ 0.438105] Serial: AMBA PL011 UART driver
10163 09:58:34.118770 <4>[ 0.446880] Trying to register duplicate clock ID: 134
10164 09:58:34.173065 <6>[ 0.504400] KASLR enabled
10165 09:58:34.187081 <6>[ 0.512085] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10166 09:58:34.193552 <6>[ 0.519101] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10167 09:58:34.200462 <6>[ 0.525593] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10168 09:58:34.207372 <6>[ 0.532599] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10169 09:58:34.213906 <6>[ 0.539086] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10170 09:58:34.220735 <6>[ 0.546089] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10171 09:58:34.227060 <6>[ 0.552578] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10172 09:58:34.233450 <6>[ 0.559582] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10173 09:58:34.236838 <6>[ 0.567070] ACPI: Interpreter disabled.
10174 09:58:34.245456 <6>[ 0.573408] iommu: Default domain type: Translated
10175 09:58:34.251698 <6>[ 0.578521] iommu: DMA domain TLB invalidation policy: strict mode
10176 09:58:34.255224 <5>[ 0.585172] SCSI subsystem initialized
10177 09:58:34.261555 <6>[ 0.589337] usbcore: registered new interface driver usbfs
10178 09:58:34.268343 <6>[ 0.595067] usbcore: registered new interface driver hub
10179 09:58:34.271304 <6>[ 0.600618] usbcore: registered new device driver usb
10180 09:58:34.278177 <6>[ 0.606711] pps_core: LinuxPPS API ver. 1 registered
10181 09:58:34.288348 <6>[ 0.611905] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10182 09:58:34.291426 <6>[ 0.621252] PTP clock support registered
10183 09:58:34.294708 <6>[ 0.625495] EDAC MC: Ver: 3.0.0
10184 09:58:34.302312 <6>[ 0.630638] FPGA manager framework
10185 09:58:34.308714 <6>[ 0.634316] Advanced Linux Sound Architecture Driver Initialized.
10186 09:58:34.312494 <6>[ 0.641079] vgaarb: loaded
10187 09:58:34.319033 <6>[ 0.644255] clocksource: Switched to clocksource arch_sys_counter
10188 09:58:34.322075 <5>[ 0.650681] VFS: Disk quotas dquot_6.6.0
10189 09:58:34.328679 <6>[ 0.654868] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10190 09:58:34.332558 <6>[ 0.662055] pnp: PnP ACPI: disabled
10191 09:58:34.340582 <6>[ 0.668675] NET: Registered PF_INET protocol family
10192 09:58:34.346938 <6>[ 0.674045] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10193 09:58:34.359150 <6>[ 0.684038] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10194 09:58:34.369137 <6>[ 0.692825] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10195 09:58:34.375801 <6>[ 0.700787] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10196 09:58:34.382076 <6>[ 0.709189] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10197 09:58:34.393267 <6>[ 0.717846] TCP: Hash tables configured (established 32768 bind 32768)
10198 09:58:34.399476 <6>[ 0.724690] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10199 09:58:34.405786 <6>[ 0.731710] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10200 09:58:34.412711 <6>[ 0.739219] NET: Registered PF_UNIX/PF_LOCAL protocol family
10201 09:58:34.419228 <6>[ 0.745364] RPC: Registered named UNIX socket transport module.
10202 09:58:34.422541 <6>[ 0.751518] RPC: Registered udp transport module.
10203 09:58:34.428904 <6>[ 0.756449] RPC: Registered tcp transport module.
10204 09:58:34.435899 <6>[ 0.761381] RPC: Registered tcp NFSv4.1 backchannel transport module.
10205 09:58:34.439083 <6>[ 0.768044] PCI: CLS 0 bytes, default 64
10206 09:58:34.442534 <6>[ 0.772426] Unpacking initramfs...
10207 09:58:34.452573 <6>[ 0.776592] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10208 09:58:34.458764 <6>[ 0.785217] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10209 09:58:34.465689 <6>[ 0.794043] kvm [1]: IPA Size Limit: 40 bits
10210 09:58:34.468840 <6>[ 0.798567] kvm [1]: GICv3: no GICV resource entry
10211 09:58:34.475533 <6>[ 0.803588] kvm [1]: disabling GICv2 emulation
10212 09:58:34.482391 <6>[ 0.808273] kvm [1]: GIC system register CPU interface enabled
10213 09:58:34.485609 <6>[ 0.814432] kvm [1]: vgic interrupt IRQ18
10214 09:58:34.492230 <6>[ 0.818802] kvm [1]: VHE mode initialized successfully
10215 09:58:34.495695 <5>[ 0.825045] Initialise system trusted keyrings
10216 09:58:34.502004 <6>[ 0.829841] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10217 09:58:34.511502 <6>[ 0.839783] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10218 09:58:34.518158 <5>[ 0.846179] NFS: Registering the id_resolver key type
10219 09:58:34.521250 <5>[ 0.851478] Key type id_resolver registered
10220 09:58:34.527826 <5>[ 0.855894] Key type id_legacy registered
10221 09:58:34.535043 <6>[ 0.860170] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10222 09:58:34.541396 <6>[ 0.867093] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10223 09:58:34.547812 <6>[ 0.874786] 9p: Installing v9fs 9p2000 file system support
10224 09:58:34.583508 <5>[ 0.911609] Key type asymmetric registered
10225 09:58:34.586418 <5>[ 0.915939] Asymmetric key parser 'x509' registered
10226 09:58:34.596592 <6>[ 0.921088] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10227 09:58:34.599624 <6>[ 0.928705] io scheduler mq-deadline registered
10228 09:58:34.602793 <6>[ 0.933465] io scheduler kyber registered
10229 09:58:34.622010 <6>[ 0.950548] EINJ: ACPI disabled.
10230 09:58:34.654506 <4>[ 0.975911] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10231 09:58:34.664105 <4>[ 0.986553] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10232 09:58:34.678952 <6>[ 1.007406] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10233 09:58:34.687041 <6>[ 1.015452] printk: console [ttyS0] disabled
10234 09:58:34.715236 <6>[ 1.040101] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10235 09:58:34.721909 <6>[ 1.049578] printk: console [ttyS0] enabled
10236 09:58:34.724992 <6>[ 1.049578] printk: console [ttyS0] enabled
10237 09:58:34.731753 <6>[ 1.058476] printk: bootconsole [mtk8250] disabled
10238 09:58:34.734804 <6>[ 1.058476] printk: bootconsole [mtk8250] disabled
10239 09:58:34.741730 <6>[ 1.069512] SuperH (H)SCI(F) driver initialized
10240 09:58:34.745067 <6>[ 1.074786] msm_serial: driver initialized
10241 09:58:34.758798 <6>[ 1.083717] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10242 09:58:34.768827 <6>[ 1.092271] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10243 09:58:34.775303 <6>[ 1.100815] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10244 09:58:34.785211 <6>[ 1.109443] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10245 09:58:34.795017 <6>[ 1.118150] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10246 09:58:34.801989 <6>[ 1.126863] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10247 09:58:34.811952 <6>[ 1.135405] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10248 09:58:34.818249 <6>[ 1.144202] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10249 09:58:34.827965 <6>[ 1.152751] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10250 09:58:34.839755 <6>[ 1.168133] loop: module loaded
10251 09:58:34.846392 <6>[ 1.174074] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10252 09:58:34.868877 <4>[ 1.197166] mtk-pmic-keys: Failed to locate of_node [id: -1]
10253 09:58:34.875679 <6>[ 1.203910] megasas: 07.719.03.00-rc1
10254 09:58:34.885217 <6>[ 1.213572] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10255 09:58:34.895577 <6>[ 1.223636] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10256 09:58:34.911629 <6>[ 1.240158] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10257 09:58:34.968031 <6>[ 1.289555] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10258 09:58:35.181234 <6>[ 1.509505] Freeing initrd memory: 17380K
10259 09:58:35.191856 <6>[ 1.520010] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10260 09:58:35.202381 <6>[ 1.530908] tun: Universal TUN/TAP device driver, 1.6
10261 09:58:35.205915 <6>[ 1.536978] thunder_xcv, ver 1.0
10262 09:58:35.209310 <6>[ 1.540481] thunder_bgx, ver 1.0
10263 09:58:35.212495 <6>[ 1.543971] nicpf, ver 1.0
10264 09:58:35.223600 <6>[ 1.547986] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10265 09:58:35.226223 <6>[ 1.555462] hns3: Copyright (c) 2017 Huawei Corporation.
10266 09:58:35.232744 <6>[ 1.561048] hclge is initializing
10267 09:58:35.236258 <6>[ 1.564627] e1000: Intel(R) PRO/1000 Network Driver
10268 09:58:35.242537 <6>[ 1.569756] e1000: Copyright (c) 1999-2006 Intel Corporation.
10269 09:58:35.245901 <6>[ 1.575767] e1000e: Intel(R) PRO/1000 Network Driver
10270 09:58:35.252595 <6>[ 1.580982] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10271 09:58:35.259198 <6>[ 1.587168] igb: Intel(R) Gigabit Ethernet Network Driver
10272 09:58:35.266169 <6>[ 1.592819] igb: Copyright (c) 2007-2014 Intel Corporation.
10273 09:58:35.272344 <6>[ 1.598654] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10274 09:58:35.279146 <6>[ 1.605172] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10275 09:58:35.282504 <6>[ 1.611634] sky2: driver version 1.30
10276 09:58:35.288944 <6>[ 1.616634] VFIO - User Level meta-driver version: 0.3
10277 09:58:35.296479 <6>[ 1.624870] usbcore: registered new interface driver usb-storage
10278 09:58:35.303206 <6>[ 1.631311] usbcore: registered new device driver onboard-usb-hub
10279 09:58:35.311773 <6>[ 1.640447] mt6397-rtc mt6359-rtc: registered as rtc0
10280 09:58:35.322322 <6>[ 1.645913] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-24T09:58:37 UTC (1700819917)
10281 09:58:35.324981 <6>[ 1.655482] i2c_dev: i2c /dev entries driver
10282 09:58:35.342630 <6>[ 1.667236] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10283 09:58:35.362180 <6>[ 1.690210] cpu cpu0: EM: created perf domain
10284 09:58:35.365409 <6>[ 1.695107] cpu cpu4: EM: created perf domain
10285 09:58:35.372464 <6>[ 1.700637] sdhci: Secure Digital Host Controller Interface driver
10286 09:58:35.379008 <6>[ 1.707066] sdhci: Copyright(c) Pierre Ossman
10287 09:58:35.385668 <6>[ 1.711980] Synopsys Designware Multimedia Card Interface Driver
10288 09:58:35.392199 <6>[ 1.718568] sdhci-pltfm: SDHCI platform and OF driver helper
10289 09:58:35.395321 <6>[ 1.718731] mmc0: CQHCI version 5.10
10290 09:58:35.402254 <6>[ 1.728921] ledtrig-cpu: registered to indicate activity on CPUs
10291 09:58:35.408780 <6>[ 1.735876] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10292 09:58:35.415461 <6>[ 1.742902] usbcore: registered new interface driver usbhid
10293 09:58:35.418839 <6>[ 1.748726] usbhid: USB HID core driver
10294 09:58:35.425185 <6>[ 1.752918] spi_master spi0: will run message pump with realtime priority
10295 09:58:35.468899 <6>[ 1.790613] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10296 09:58:35.488362 <6>[ 1.806444] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10297 09:58:35.495376 <6>[ 1.821140] cros-ec-spi spi0.0: Chrome EC device registered
10298 09:58:35.498959 <6>[ 1.827204] mmc0: Command Queue Engine enabled
10299 09:58:35.505220 <6>[ 1.831947] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10300 09:58:35.511882 <6>[ 1.839412] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10301 09:58:35.521108 <6>[ 1.849432] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10302 09:58:35.531025 <6>[ 1.853719] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10303 09:58:35.537877 <6>[ 1.856418] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10304 09:58:35.541395 <6>[ 1.865643] NET: Registered PF_PACKET protocol family
10305 09:58:35.547806 <6>[ 1.870610] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10306 09:58:35.551129 <6>[ 1.875320] 9pnet: Installing 9P2000 support
10307 09:58:35.557873 <6>[ 1.881146] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10308 09:58:35.564122 <5>[ 1.885046] Key type dns_resolver registered
10309 09:58:35.567960 <6>[ 1.896468] registered taskstats version 1
10310 09:58:35.574071 <5>[ 1.900845] Loading compiled-in X.509 certificates
10311 09:58:35.603176 <4>[ 1.924866] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10312 09:58:35.613150 <4>[ 1.935605] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10313 09:58:35.619513 <3>[ 1.946170] debugfs: File 'uA_load' in directory '/' already present!
10314 09:58:35.626221 <3>[ 1.952939] debugfs: File 'min_uV' in directory '/' already present!
10315 09:58:35.633035 <3>[ 1.959554] debugfs: File 'max_uV' in directory '/' already present!
10316 09:58:35.639480 <3>[ 1.966164] debugfs: File 'constraint_flags' in directory '/' already present!
10317 09:58:35.650607 <3>[ 1.975666] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10318 09:58:35.659700 <6>[ 1.987856] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10319 09:58:35.666702 <6>[ 1.994581] xhci-mtk 11200000.usb: xHCI Host Controller
10320 09:58:35.672834 <6>[ 2.000068] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10321 09:58:35.683102 <6>[ 2.007895] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10322 09:58:35.689750 <6>[ 2.017313] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10323 09:58:35.696014 <6>[ 2.023365] xhci-mtk 11200000.usb: xHCI Host Controller
10324 09:58:35.702491 <6>[ 2.028840] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10325 09:58:35.709152 <6>[ 2.036485] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10326 09:58:35.716016 <6>[ 2.044139] hub 1-0:1.0: USB hub found
10327 09:58:35.719482 <6>[ 2.048170] hub 1-0:1.0: 1 port detected
10328 09:58:35.725808 <6>[ 2.052457] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10329 09:58:35.732549 <6>[ 2.060978] hub 2-0:1.0: USB hub found
10330 09:58:35.735863 <6>[ 2.064999] hub 2-0:1.0: 1 port detected
10331 09:58:35.744173 <6>[ 2.072136] mtk-msdc 11f70000.mmc: Got CD GPIO
10332 09:58:35.753822 <6>[ 2.078793] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10333 09:58:35.760418 <6>[ 2.086825] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10334 09:58:35.770288 <4>[ 2.094724] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10335 09:58:35.780389 <6>[ 2.104252] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10336 09:58:35.786830 <6>[ 2.112328] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10337 09:58:35.793695 <6>[ 2.120390] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10338 09:58:35.803474 <6>[ 2.128324] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10339 09:58:35.810295 <6>[ 2.136143] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10340 09:58:35.820672 <6>[ 2.143961] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10341 09:58:35.830302 <6>[ 2.154292] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10342 09:58:35.836784 <6>[ 2.162665] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10343 09:58:35.846728 <6>[ 2.171003] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10344 09:58:35.853267 <6>[ 2.179342] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10345 09:58:35.863209 <6>[ 2.187679] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10346 09:58:35.870057 <6>[ 2.196025] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10347 09:58:35.879892 <6>[ 2.204364] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10348 09:58:35.886463 <6>[ 2.212701] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10349 09:58:35.896198 <6>[ 2.221038] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10350 09:58:35.903230 <6>[ 2.229375] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10351 09:58:35.912743 <6>[ 2.237713] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10352 09:58:35.919603 <6>[ 2.246052] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10353 09:58:35.929732 <6>[ 2.254394] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10354 09:58:35.936362 <6>[ 2.262737] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10355 09:58:35.946342 <6>[ 2.271075] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10356 09:58:35.952483 <6>[ 2.279807] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10357 09:58:35.959504 <6>[ 2.286947] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10358 09:58:35.965768 <6>[ 2.293703] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10359 09:58:35.972650 <6>[ 2.300456] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10360 09:58:35.979232 <6>[ 2.307404] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10361 09:58:35.989317 <6>[ 2.314263] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10362 09:58:35.998927 <6>[ 2.323391] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10363 09:58:36.008930 <6>[ 2.332508] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10364 09:58:36.018859 <6>[ 2.341801] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10365 09:58:36.028812 <6>[ 2.351271] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10366 09:58:36.035275 <6>[ 2.360739] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10367 09:58:36.045419 <6>[ 2.369858] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10368 09:58:36.055222 <6>[ 2.379341] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10369 09:58:36.065300 <6>[ 2.388460] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10370 09:58:36.075410 <6>[ 2.397752] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10371 09:58:36.084894 <6>[ 2.407916] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10372 09:58:36.094803 <6>[ 2.419314] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10373 09:58:36.101005 <6>[ 2.428839] Trying to probe devices needed for running init ...
10374 09:58:36.151130 <6>[ 2.476518] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10375 09:58:36.306059 <6>[ 2.634472] hub 1-1:1.0: USB hub found
10376 09:58:36.309176 <6>[ 2.638984] hub 1-1:1.0: 4 ports detected
10377 09:58:36.319098 <6>[ 2.647851] hub 1-1:1.0: USB hub found
10378 09:58:36.322475 <6>[ 2.652221] hub 1-1:1.0: 4 ports detected
10379 09:58:36.431668 <6>[ 2.756890] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10380 09:58:36.459184 <6>[ 2.787595] hub 2-1:1.0: USB hub found
10381 09:58:36.462329 <6>[ 2.792153] hub 2-1:1.0: 3 ports detected
10382 09:58:36.472631 <6>[ 2.800737] hub 2-1:1.0: USB hub found
10383 09:58:36.475808 <6>[ 2.805205] hub 2-1:1.0: 3 ports detected
10384 09:58:36.643476 <6>[ 2.968639] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10385 09:58:36.776038 <6>[ 3.104315] hub 1-1.4:1.0: USB hub found
10386 09:58:36.778795 <6>[ 3.108975] hub 1-1.4:1.0: 2 ports detected
10387 09:58:36.787632 <6>[ 3.116305] hub 1-1.4:1.0: USB hub found
10388 09:58:36.791327 <6>[ 3.120888] hub 1-1.4:1.0: 2 ports detected
10389 09:58:36.855587 <6>[ 3.180685] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10390 09:58:37.087275 <6>[ 3.412563] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10391 09:58:37.279249 <6>[ 3.604508] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10392 09:58:48.399774 <6>[ 14.733559] ALSA device list:
10393 09:58:48.406350 <6>[ 14.736851] No soundcards found.
10394 09:58:48.414067 <6>[ 14.744649] Freeing unused kernel memory: 8384K
10395 09:58:48.417363 <6>[ 14.749629] Run /init as init process
10396 09:58:48.428466 Loading, please wait...
10397 09:58:48.448202 Starting version 247.3-7+deb11u2
10398 09:58:48.658630 <6>[ 14.986013] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10399 09:58:48.673437 <6>[ 15.003788] remoteproc remoteproc0: scp is available
10400 09:58:48.680208 <6>[ 15.009797] remoteproc remoteproc0: powering up scp
10401 09:58:48.686895 <6>[ 15.015015] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10402 09:58:48.693287 <6>[ 15.023491] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10403 09:58:48.700118 <6>[ 15.025988] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10404 09:58:48.709744 <3>[ 15.027905] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10405 09:58:48.716480 <3>[ 15.027914] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10406 09:58:48.726287 <3>[ 15.027919] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10407 09:58:48.733006 <3>[ 15.028000] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10408 09:58:48.742949 <3>[ 15.028004] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10409 09:58:48.749548 <3>[ 15.028010] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10410 09:58:48.756107 <3>[ 15.028022] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10411 09:58:48.766295 <3>[ 15.028026] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10412 09:58:48.772683 <3>[ 15.028799] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10413 09:58:48.782827 <3>[ 15.028883] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10414 09:58:48.789140 <3>[ 15.028888] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10415 09:58:48.799193 <3>[ 15.028895] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10416 09:58:48.805711 <3>[ 15.028979] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10417 09:58:48.815733 <3>[ 15.028983] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10418 09:58:48.822352 <3>[ 15.028986] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10419 09:58:48.832277 <3>[ 15.028992] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10420 09:58:48.839069 <3>[ 15.028995] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10421 09:58:48.845803 <3>[ 15.029020] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10422 09:58:48.852681 <4>[ 15.111406] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10423 09:58:48.863087 <6>[ 15.117632] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10424 09:58:48.869838 <6>[ 15.128325] mc: Linux media interface: v0.10
10425 09:58:48.875933 <6>[ 15.128523] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10426 09:58:48.886130 <6>[ 15.133869] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10427 09:58:48.892452 <4>[ 15.143867] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10428 09:58:48.902522 <6>[ 15.155009] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10429 09:58:48.909209 <6>[ 15.155012] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10430 09:58:48.915824 <6>[ 15.155046] remoteproc remoteproc0: remote processor scp is now up
10431 09:58:48.922111 <6>[ 15.158831] videodev: Linux video capture interface: v2.00
10432 09:58:48.925468 <6>[ 15.168340] usbcore: registered new interface driver r8152
10433 09:58:48.935490 <4>[ 15.171927] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10434 09:58:48.938652 <4>[ 15.171927] Fallback method does not support PEC.
10435 09:58:48.948595 <3>[ 15.188802] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10436 09:58:48.955471 <6>[ 15.273796] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10437 09:58:48.962568 <6>[ 15.276960] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10438 09:58:48.972667 <6>[ 15.279640] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10439 09:58:48.982441 <6>[ 15.284133] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10440 09:58:48.989085 <6>[ 15.284475] pci_bus 0000:00: root bus resource [bus 00-ff]
10441 09:58:48.998860 <6>[ 15.284842] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10442 09:58:49.005496 <6>[ 15.294557] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10443 09:58:49.015359 <3>[ 15.297018] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10444 09:58:49.021967 <6>[ 15.299868] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10445 09:58:49.028850 <6>[ 15.309332] usbcore: registered new interface driver cdc_ether
10446 09:58:49.038694 <6>[ 15.319119] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10447 09:58:49.041808 <6>[ 15.319777] Bluetooth: Core ver 2.22
10448 09:58:49.048364 <6>[ 15.319902] NET: Registered PF_BLUETOOTH protocol family
10449 09:58:49.055174 <6>[ 15.319904] Bluetooth: HCI device and connection manager initialized
10450 09:58:49.058332 <6>[ 15.319923] Bluetooth: HCI socket layer initialized
10451 09:58:49.065071 <6>[ 15.319928] Bluetooth: L2CAP socket layer initialized
10452 09:58:49.071687 <6>[ 15.319936] Bluetooth: SCO socket layer initialized
10453 09:58:49.075056 <6>[ 15.334218] usbcore: registered new interface driver r8153_ecm
10454 09:58:49.081668 <6>[ 15.342194] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10455 09:58:49.087994 <6>[ 15.351120] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10456 09:58:49.098181 <6>[ 15.358059] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10457 09:58:49.104936 <6>[ 15.358731] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10458 09:58:49.117860 <6>[ 15.359709] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10459 09:58:49.120975 <6>[ 15.359800] usbcore: registered new interface driver uvcvideo
10460 09:58:49.131088 <4>[ 15.383850] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10461 09:58:49.134398 <6>[ 15.390079] pci 0000:00:00.0: supports D1 D2
10462 09:58:49.140844 <6>[ 15.391058] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10463 09:58:49.150808 <4>[ 15.395153] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10464 09:58:49.157501 <6>[ 15.400450] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10465 09:58:49.163975 <6>[ 15.400856] usbcore: registered new interface driver btusb
10466 09:58:49.174185 <4>[ 15.401571] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10467 09:58:49.180685 <3>[ 15.401577] Bluetooth: hci0: Failed to load firmware file (-2)
10468 09:58:49.187167 <3>[ 15.401580] Bluetooth: hci0: Failed to set up firmware (-2)
10469 09:58:49.197070 <4>[ 15.401584] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10470 09:58:49.200530 <6>[ 15.468578] r8152 2-1.3:1.0 eth0: v1.12.13
10471 09:58:49.206882 <6>[ 15.472331] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10472 09:58:49.213616 <6>[ 15.488627] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10473 09:58:49.220256 <6>[ 15.493038] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10474 09:58:49.226811 <6>[ 15.556446] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10475 09:58:49.236879 <6>[ 15.563931] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10476 09:58:49.243475 <6>[ 15.571412] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10477 09:58:49.246827 <6>[ 15.578984] pci 0000:01:00.0: supports D1 D2
10478 09:58:49.253267 <6>[ 15.583503] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10479 09:58:49.277509 <6>[ 15.604512] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10480 09:58:49.283857 <6>[ 15.611409] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10481 09:58:49.290370 <6>[ 15.619488] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10482 09:58:49.300332 <6>[ 15.627483] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10483 09:58:49.307203 <6>[ 15.635482] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10484 09:58:49.317122 <6>[ 15.643482] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10485 09:58:49.320248 <6>[ 15.651482] pci 0000:00:00.0: PCI bridge to [bus 01]
10486 09:58:49.330551 <6>[ 15.656700] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10487 09:58:49.336855 <6>[ 15.664831] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10488 09:58:49.343501 <6>[ 15.671630] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10489 09:58:49.349828 <6>[ 15.678286] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10490 09:58:49.371075 <5>[ 15.698289] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10491 09:58:49.389381 <5>[ 15.716778] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10492 09:58:49.395994 <4>[ 15.723767] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10493 09:58:49.402839 <6>[ 15.732664] cfg80211: failed to load regulatory.db
10494 09:58:49.463620 <6>[ 15.790941] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10495 09:58:49.470057 <6>[ 15.798523] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10496 09:58:49.494585 <6>[ 15.825346] mt7921e 0000:01:00.0: ASIC revision: 79610010
10497 09:58:49.600499 <4>[ 15.924562] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10498 09:58:49.621943 Begin: Loading essential drivers ... done.
10499 09:58:49.625306 Begin: Running /scripts/init-premount ... done.
10500 09:58:49.632452 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10501 09:58:49.641776 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10502 09:58:49.644861 Device /sys/class/net/enx00e04c6803bd found
10503 09:58:49.644948 done.
10504 09:58:49.693168 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10505 09:58:49.720431 <4>[ 16.044352] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10506 09:58:49.839910 <4>[ 16.164049] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10507 09:58:49.959978 <4>[ 16.283982] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10508 09:58:50.079944 <4>[ 16.404139] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10509 09:58:50.200025 <4>[ 16.523976] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10510 09:58:50.320329 <4>[ 16.644069] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10511 09:58:50.440017 <4>[ 16.763816] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10512 09:58:50.560165 <4>[ 16.884111] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10513 09:58:50.679939 <4>[ 17.003978] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10514 09:58:50.742352 <6>[ 17.073037] r8152 2-1.3:1.0 enx00e04c6803bd: carrier on
10515 09:58:50.791131 <3>[ 17.121806] mt7921e 0000:01:00.0: hardware init failed
10516 09:58:50.815151 IP-Config: no response after 2 secs - giving up
10517 09:58:50.856702 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10518 09:58:51.959334 IP-Config: enx00e04c6803bd complete (dhcp from 192.168.201.1):
10519 09:58:51.965867 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10520 09:58:51.972660 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10521 09:58:51.979154 host : mt8192-asurada-spherion-r0-cbg-4
10522 09:58:51.989186 domain : lava-rack
10523 09:58:51.992222 rootserver: 192.168.201.1 rootpath:
10524 09:58:51.992329 filename :
10525 09:58:52.019416 done.
10526 09:58:52.026495 Begin: Running /scripts/nfs-bottom ... done.
10527 09:58:52.046622 Begin: Running /scripts/init-bottom ... done.
10528 09:58:53.219704 <6>[ 19.550903] NET: Registered PF_INET6 protocol family
10529 09:58:53.227473 <6>[ 19.558457] Segment Routing with IPv6
10530 09:58:53.230748 <6>[ 19.562522] In-situ OAM (IOAM) with IPv6
10531 09:58:53.346130 <30>[ 19.656986] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10532 09:58:53.348968 <30>[ 19.681411] systemd[1]: Detected architecture arm64.
10533 09:58:53.369882
10534 09:58:53.373282 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10535 09:58:53.373378
10536 09:58:53.391628 <30>[ 19.722748] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10537 09:58:54.159037 <30>[ 20.487056] systemd[1]: Queued start job for default target Graphical Interface.
10538 09:58:54.191991 <30>[ 20.523049] systemd[1]: Created slice system-getty.slice.
10539 09:58:54.198416 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10540 09:58:54.215144 <30>[ 20.546072] systemd[1]: Created slice system-modprobe.slice.
10541 09:58:54.221451 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10542 09:58:54.238835 <30>[ 20.569829] systemd[1]: Created slice system-serial\x2dgetty.slice.
10543 09:58:54.248784 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10544 09:58:54.262397 <30>[ 20.593639] systemd[1]: Created slice User and Session Slice.
10545 09:58:54.269092 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10546 09:58:54.289800 <30>[ 20.617376] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10547 09:58:54.299515 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10548 09:58:54.316869 <30>[ 20.644785] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10549 09:58:54.323725 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10550 09:58:54.344021 <30>[ 20.668716] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10551 09:58:54.350689 <30>[ 20.680857] systemd[1]: Reached target Local Encrypted Volumes.
10552 09:58:54.357179 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10553 09:58:54.374099 <30>[ 20.704922] systemd[1]: Reached target Paths.
10554 09:58:54.377302 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10555 09:58:54.393288 <30>[ 20.724543] systemd[1]: Reached target Remote File Systems.
10556 09:58:54.400061 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10557 09:58:54.417813 <30>[ 20.748903] systemd[1]: Reached target Slices.
10558 09:58:54.424260 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10559 09:58:54.437666 <30>[ 20.768567] systemd[1]: Reached target Swap.
10560 09:58:54.440462 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10561 09:58:54.460996 <30>[ 20.789033] systemd[1]: Listening on initctl Compatibility Named Pipe.
10562 09:58:54.467758 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10563 09:58:54.474496 <30>[ 20.805065] systemd[1]: Listening on Journal Audit Socket.
10564 09:58:54.480864 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10565 09:58:54.498944 <30>[ 20.829732] systemd[1]: Listening on Journal Socket (/dev/log).
10566 09:58:54.505237 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10567 09:58:54.522701 <30>[ 20.853775] systemd[1]: Listening on Journal Socket.
10568 09:58:54.529034 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10569 09:58:54.546312 <30>[ 20.874115] systemd[1]: Listening on Network Service Netlink Socket.
10570 09:58:54.552716 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10571 09:58:54.567741 <30>[ 20.898963] systemd[1]: Listening on udev Control Socket.
10572 09:58:54.574589 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10573 09:58:54.589858 <30>[ 20.920976] systemd[1]: Listening on udev Kernel Socket.
10574 09:58:54.596416 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10575 09:58:54.653392 <30>[ 20.984685] systemd[1]: Mounting Huge Pages File System...
10576 09:58:54.659927 Mounting [0;1;39mHuge Pages File System[0m...
10577 09:58:54.677572 <30>[ 21.008848] systemd[1]: Mounting POSIX Message Queue File System...
10578 09:58:54.684282 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10579 09:58:54.708077 <30>[ 21.039340] systemd[1]: Mounting Kernel Debug File System...
10580 09:58:54.714611 Mounting [0;1;39mKernel Debug File System[0m...
10581 09:58:54.732930 <30>[ 21.061007] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10582 09:58:54.756533 <30>[ 21.084512] systemd[1]: Starting Create list of static device nodes for the current kernel...
10583 09:58:54.763072 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10584 09:58:54.786652 <30>[ 21.117483] systemd[1]: Starting Load Kernel Module configfs...
10585 09:58:54.793072 Starting [0;1;39mLoad Kernel Module configfs[0m...
10586 09:58:54.809784 <30>[ 21.141028] systemd[1]: Starting Load Kernel Module drm...
10587 09:58:54.816394 Starting [0;1;39mLoad Kernel Module drm[0m...
10588 09:58:54.834611 <30>[ 21.165537] systemd[1]: Starting Load Kernel Module fuse...
10589 09:58:54.841018 Starting [0;1;39mLoad Kernel Module fuse[0m...
10590 09:58:54.868496 <6>[ 21.199776] fuse: init (API version 7.37)
10591 09:58:54.878344 <30>[ 21.200689] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10592 09:58:54.909965 <30>[ 21.241283] systemd[1]: Starting Journal Service...
10593 09:58:54.916547 Starting [0;1;39mJournal Service[0m...
10594 09:58:54.938908 <30>[ 21.270113] systemd[1]: Starting Load Kernel Modules...
10595 09:58:54.945370 Starting [0;1;39mLoad Kernel Modules[0m...
10596 09:58:54.967950 <30>[ 21.295850] systemd[1]: Starting Remount Root and Kernel File Systems...
10597 09:58:54.974709 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10598 09:58:54.995624 <30>[ 21.326968] systemd[1]: Starting Coldplug All udev Devices...
10599 09:58:55.002291 Starting [0;1;39mColdplug All udev Devices[0m...
10600 09:58:55.028716 <30>[ 21.359615] systemd[1]: Mounted Huge Pages File System.
10601 09:58:55.038865 <3>[ 21.364316] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10602 09:58:55.044988 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10603 09:58:55.058625 <30>[ 21.389006] systemd[1]: Mounted POSIX Message Queue File System.
10604 09:58:55.071705 [[0;32m OK [0m] Mounted [0;<3>[ 21.397087] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10605 09:58:55.075114 1;39mPOSIX Message Queue File System[0m.
10606 09:58:55.089772 <30>[ 21.421169] systemd[1]: Mounted Kernel Debug File System.
10607 09:58:55.096808 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10608 09:58:55.113886 <3>[ 21.441958] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10609 09:58:55.123948 <30>[ 21.451892] systemd[1]: Finished Create list of static device nodes for the current kernel.
10610 09:58:55.134465 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10611 09:58:55.140975 <30>[ 21.471170] systemd[1]: modprobe@configfs.service: Succeeded.
10612 09:58:55.150836 <3>[ 21.472849] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10613 09:58:55.157307 <30>[ 21.478172] systemd[1]: Finished Load Kernel Module configfs.
10614 09:58:55.164055 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10615 09:58:55.179403 <3>[ 21.507402] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10616 09:58:55.186375 <30>[ 21.517565] systemd[1]: modprobe@drm.service: Succeeded.
10617 09:58:55.192892 <30>[ 21.524194] systemd[1]: Finished Load Kernel Module drm.
10618 09:58:55.199890 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10619 09:58:55.209942 <3>[ 21.537797] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10620 09:58:55.217187 <30>[ 21.548467] systemd[1]: modprobe@fuse.service: Succeeded.
10621 09:58:55.224616 <30>[ 21.555633] systemd[1]: Finished Load Kernel Module fuse.
10622 09:58:55.231256 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10623 09:58:55.242637 <3>[ 21.570565] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10624 09:58:55.250125 <30>[ 21.581225] systemd[1]: Finished Load Kernel Modules.
10625 09:58:55.256458 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10626 09:58:55.270927 <3>[ 21.599029] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10627 09:58:55.281847 <30>[ 21.609776] systemd[1]: Finished Remount Root and Kernel File Systems.
10628 09:58:55.288467 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10629 09:58:55.303053 <3>[ 21.631088] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10630 09:58:55.332073 <3>[ 21.660034] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10631 09:58:55.341322 <30>[ 21.672484] systemd[1]: Mounting FUSE Control File System...
10632 09:58:55.347565 Mounting [0;1;39mFUSE Control File System[0m...
10633 09:58:55.367450 <30>[ 21.694984] systemd[1]: Mounting Kernel Configuration File System...
10634 09:58:55.370830 Mounting [0;1;39mKernel Configuration File System[0m...
10635 09:58:55.392783 <30>[ 21.720607] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10636 09:58:55.402538 <30>[ 21.729772] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10637 09:58:55.412280 <30>[ 21.743491] systemd[1]: Starting Load/Save Random Seed...
10638 09:58:55.418748 Starting [0;1;39mLoad/Save Random Seed[0m...
10639 09:58:55.438683 <30>[ 21.770003] systemd[1]: Starting Apply Kernel Variables...
10640 09:58:55.445590 Starting [0;1;39mApply Kernel Variables[0m...
10641 09:58:55.463231 <30>[ 21.794551] systemd[1]: Starting Create System Users...
10642 09:58:55.470014 Starting [0;1;39mCreate System Users[0m...
10643 09:58:55.488845 <30>[ 21.819869] systemd[1]: Started Journal Service.
10644 09:58:55.505358 <4>[ 21.821811] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10645 09:58:55.511790 <3>[ 21.840528] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10646 09:58:55.518268 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10647 09:58:55.543342 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10648 09:58:55.561375 See 'systemctl status systemd-udev-trigger.service' for details.
10649 09:58:55.578201 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10650 09:58:55.594027 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10651 09:58:55.611180 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10652 09:58:55.627149 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10653 09:58:55.643186 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10654 09:58:55.690569 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10655 09:58:55.709587 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10656 09:58:55.756740 <46>[ 22.084367] systemd-journald[293]: Received client request to flush runtime journal.
10657 09:58:55.776034 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10658 09:58:55.790153 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10659 09:58:55.805456 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10660 09:58:55.861939 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10661 09:58:57.155764 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10662 09:58:57.214119 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10663 09:58:57.234440 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10664 09:58:57.255179 Starting [0;1;39mNetwork Service[0m...
10665 09:58:57.637337 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10666 09:58:57.668255 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10667 09:58:57.717485 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10668 09:58:57.917053 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10669 09:58:57.936760 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10670 09:58:57.966276 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10671 09:58:57.986019 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10672 09:58:58.001869 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10673 09:58:58.017924 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10674 09:58:58.042588 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10675 09:58:58.109755 Starting [0;1;39mNetwork Name Resolution[0m...
10676 09:58:58.136382 Starting [0;1;39mNetwork Time Synchronization[0m...
10677 09:58:58.154542 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10678 09:58:58.203635 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10679 09:58:58.330280 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10680 09:58:58.346579 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10681 09:58:58.368718 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10682 09:58:58.385311 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10683 09:58:58.401273 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10684 09:58:58.526402 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10685 09:58:58.561380 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10686 09:58:58.591240 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10687 09:58:58.616178 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10688 09:58:58.633335 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10689 09:58:58.993185 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10690 09:58:59.005097 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10691 09:58:59.020818 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10692 09:58:59.082142 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10693 09:58:59.373264 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10694 09:58:59.763054 Starting [0;1;39mUser Login Management[0m...
10695 09:58:59.784209 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10696 09:58:59.804086 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10697 09:58:59.824970 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10698 09:58:59.870791 Starting [0;1;39mPermit User Sessions[0m...
10699 09:58:59.969624 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10700 09:58:59.988292 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10701 09:59:00.037050 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10702 09:59:00.074078 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10703 09:59:00.089962 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10704 09:59:00.108053 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10705 09:59:00.116991 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10706 09:59:00.134143 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10707 09:59:00.175222 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10708 09:59:00.220823 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10709 09:59:00.307906
10710 09:59:00.308054
10711 09:59:00.311355 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10712 09:59:00.311445
10713 09:59:00.331252 debian-bullseye-arm64 login: root (automatic login)
10714 09:59:00.331388
10715 09:59:00.331456
10716 09:59:00.610599 Linux debian-bullseye-arm64 6.1.62-cip9 #1 SMP PREEMPT Fri Nov 24 09:44:51 UTC 2023 aarch64
10717 09:59:00.610735
10718 09:59:00.617059 The programs included with the Debian GNU/Linux system are free software;
10719 09:59:00.623649 the exact distribution terms for each program are described in the
10720 09:59:00.626968 individual files in /usr/share/doc/*/copyright.
10721 09:59:00.627054
10722 09:59:00.633602 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10723 09:59:00.637111 permitted by applicable law.
10724 09:59:00.705230 Matched prompt #10: / #
10726 09:59:00.705499 Setting prompt string to ['/ #']
10727 09:59:00.705592 end: 2.2.5.1 login-action (duration 00:00:28) [common]
10729 09:59:00.705866 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
10730 09:59:00.705954 start: 2.2.6 expect-shell-connection (timeout 00:03:26) [common]
10731 09:59:00.706023 Setting prompt string to ['/ #']
10732 09:59:00.706083 Forcing a shell prompt, looking for ['/ #']
10734 09:59:00.756305 / #
10735 09:59:00.756446 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10736 09:59:00.756539 Waiting using forced prompt support (timeout 00:02:30)
10737 09:59:00.761713
10738 09:59:00.761994 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10739 09:59:00.762092 start: 2.2.7 export-device-env (timeout 00:03:26) [common]
10741 09:59:00.862459 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12073278/extract-nfsrootfs-ycmyc54y'
10742 09:59:00.868083 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12073278/extract-nfsrootfs-ycmyc54y'
10744 09:59:00.968670 / # export NFS_SERVER_IP='192.168.201.1'
10745 09:59:00.973838 export NFS_SERVER_IP='192.168.201.1'
10746 09:59:00.974168 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10747 09:59:00.974267 end: 2.2 depthcharge-retry (duration 00:01:35) [common]
10748 09:59:00.974357 end: 2 depthcharge-action (duration 00:01:35) [common]
10749 09:59:00.974447 start: 3 lava-test-retry (timeout 00:01:00) [common]
10750 09:59:00.974532 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10751 09:59:00.974608 Using namespace: common
10753 09:59:01.074957 / # #
10754 09:59:01.075119 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10755 09:59:01.079979 #
10756 09:59:01.080292 Using /lava-12073278
10758 09:59:01.180673 / # export SHELL=/bin/sh
10759 09:59:01.185735 export SHELL=/bin/sh
10761 09:59:01.286290 / # . /lava-12073278/environment
10762 09:59:01.291453 . /lava-12073278/environment
10764 09:59:01.396942 / # /lava-12073278/bin/lava-test-runner /lava-12073278/0
10765 09:59:01.397096 Test shell timeout: 10s (minimum of the action and connection timeout)
10766 09:59:01.401990 /lava-12073278/bin/lava-test-runner /lava-12073278/0
10767 09:59:01.596963 + export TESTRUN_ID=0_dmesg
10768 09:59:01.600554 + cd /lava-12073278/0/tests/0_dmesg
10769 09:59:01.603819 + cat uuid
10770 09:59:01.610648 Received signal: <STARTRUN> 0_dmesg 12073278_1.6.2.3.1
10771 09:59:01.610739 Starting test lava.0_dmesg (12073278_1.6.2.3.1)
10772 09:59:01.610827 Skipping test definition patterns.
10773 09:59:01.613572 + UUID=12073278_1.<8>[ 27.941534] <LAVA_SIGNAL_STARTRUN 0_dmesg 12073278_1.6.2.3.1>
10774 09:59:01.613657 6.2.3.1
10775 09:59:01.613733 + set +x
10776 09:59:01.617178 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10777 09:59:01.693789 <8>[ 28.022339] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10778 09:59:01.694102 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10780 09:59:01.749710 <8>[ 28.078240] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10781 09:59:01.750024 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10783 09:59:01.812279 <8>[ 28.141051] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10784 09:59:01.812607 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10786 09:59:01.815771 + set +x
10787 09:59:01.819060 <8>[ 28.150527] <LAVA_SIGNAL_ENDRUN 0_dmesg 12073278_1.6.2.3.1>
10788 09:59:01.819332 Received signal: <ENDRUN> 0_dmesg 12073278_1.6.2.3.1
10789 09:59:01.819414 Ending use of test pattern.
10790 09:59:01.819477 Ending test lava.0_dmesg (12073278_1.6.2.3.1), duration 0.21
10792 09:59:01.824287 <LAVA_TEST_RUNNER EXIT>
10793 09:59:01.824527 ok: lava_test_shell seems to have completed
10794 09:59:01.824670 alert: pass
crit: pass
emerg: pass
10795 09:59:01.824760 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10796 09:59:01.824843 end: 3 lava-test-retry (duration 00:00:01) [common]
10797 09:59:01.824924 start: 4 lava-test-retry (timeout 00:01:00) [common]
10798 09:59:01.825004 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10799 09:59:01.825067 Using namespace: common
10801 09:59:01.925439 / # #
10802 09:59:01.925599 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10803 09:59:01.925739 Using /lava-12073278
10805 09:59:02.026096 export SHELL=/bin/sh
10806 09:59:02.026293 #
10808 09:59:02.126814 / # export SHELL=/bin/sh. /lava-12073278/environment
10809 09:59:02.127010
10811 09:59:02.227565 / # . /lava-12073278/environment/lava-12073278/bin/lava-test-runner /lava-12073278/1
10812 09:59:02.227719 Test shell timeout: 10s (minimum of the action and connection timeout)
10813 09:59:02.227858
10814 09:59:02.232892 / # /lava-12073278/bin/lava-test-runner /lava-12073278/1
10815 09:59:02.331992 + export TESTRUN_ID=1_bootrr
10816 09:59:02.335528 + cd /lava-12073278/1/tests/1_bootrr
10817 09:59:02.338597 + cat uuid
10818 09:59:02.346690 + <8>[ 28.678978] <LAVA_SIGNAL_STARTRUN 1_bootrr 12073278_1.6.2.3.5>
10819 09:59:02.346956 Received signal: <STARTRUN> 1_bootrr 12073278_1.6.2.3.5
10820 09:59:02.347029 Starting test lava.1_bootrr (12073278_1.6.2.3.5)
10821 09:59:02.347112 Skipping test definition patterns.
10822 09:59:02.350167 UUID=12073278_1.6.2.3.5
10823 09:59:02.350251 + set +x
10824 09:59:02.363213 + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-12073278/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
10825 09:59:02.366449 + cd /opt/bootrr/libexec/bootrr
10826 09:59:02.366536 + sh helpers/bootrr-auto
10827 09:59:02.416122 /lava-12073278/1/../bin/lava-test-case
10828 09:59:02.439661 <8>[ 28.768284] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10829 09:59:02.439974 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10831 09:59:02.477806 /lava-12073278/1/../bin/lava-test-case
10832 09:59:02.498640 <8>[ 28.827626] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10833 09:59:02.498948 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10835 09:59:02.520174 /lava-12073278/1/../bin/lava-test-case
10836 09:59:02.541737 <8>[ 28.870585] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>
10837 09:59:02.542029 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
10839 09:59:02.589906 /lava-12073278/1/../bin/lava-test-case
10840 09:59:02.610889 <8>[ 28.939726] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10841 09:59:02.611188 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10843 09:59:02.646864 /lava-12073278/1/../bin/lava-test-case
10844 09:59:02.670332 <8>[ 28.999258] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10845 09:59:02.670685 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10847 09:59:02.697455 /lava-12073278/1/../bin/lava-test-case
10848 09:59:02.721952 <8>[ 29.050903] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10849 09:59:02.722273 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10851 09:59:02.751917 /lava-12073278/1/../bin/lava-test-case
10852 09:59:02.772945 <8>[ 29.101982] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10853 09:59:02.773314 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10855 09:59:02.801245 /lava-12073278/1/../bin/lava-test-case
10856 09:59:02.824814 <8>[ 29.153609] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10857 09:59:02.825191 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10859 09:59:02.843216 /lava-12073278/1/../bin/lava-test-case
10860 09:59:02.865468 <8>[ 29.194449] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10861 09:59:02.865781 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10863 09:59:02.891524 /lava-12073278/1/../bin/lava-test-case
10864 09:59:02.910729 <8>[ 29.239748] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10865 09:59:02.911064 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10867 09:59:02.931054 /lava-12073278/1/../bin/lava-test-case
10868 09:59:02.950244 <8>[ 29.279092] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10869 09:59:02.950557 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10871 09:59:02.988339 /lava-12073278/1/../bin/lava-test-case
10872 09:59:03.008541 <8>[ 29.337615] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10873 09:59:03.008905 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10875 09:59:03.040443 /lava-12073278/1/../bin/lava-test-case
10876 09:59:03.063281 <8>[ 29.392061] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10877 09:59:03.063576 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10879 09:59:03.088288 /lava-12073278/1/../bin/lava-test-case
10880 09:59:03.107445 <8>[ 29.436394] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10881 09:59:03.107733 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10883 09:59:03.133366 /lava-12073278/1/../bin/lava-test-case
10884 09:59:03.152937 <8>[ 29.481470] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10885 09:59:03.153248 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10887 09:59:03.171384 /lava-12073278/1/../bin/lava-test-case
10888 09:59:03.190149 <8>[ 29.519111] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
10889 09:59:03.190446 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10891 09:59:03.220500 /lava-12073278/1/../bin/lava-test-case
10892 09:59:03.242518 <8>[ 29.571424] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
10893 09:59:03.242840 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10895 09:59:03.262102 /lava-12073278/1/../bin/lava-test-case
10896 09:59:03.285306 <8>[ 29.614060] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
10897 09:59:03.285603 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10899 09:59:03.323286 /lava-12073278/1/../bin/lava-test-case
10900 09:59:03.342732 <8>[ 29.671853] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
10901 09:59:03.343006 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10903 09:59:03.360866 /lava-12073278/1/../bin/lava-test-case
10904 09:59:03.379051 <8>[ 29.707972] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
10905 09:59:03.379363 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10907 09:59:03.405283 /lava-12073278/1/../bin/lava-test-case
10908 09:59:03.423812 <8>[ 29.752313] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
10909 09:59:03.424547 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10911 09:59:03.446247 /lava-12073278/1/../bin/lava-test-case
10912 09:59:03.475579 <8>[ 29.804241] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
10913 09:59:03.476272 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10915 09:59:03.505546 /lava-12073278/1/../bin/lava-test-case
10916 09:59:03.528676 <8>[ 29.857739] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
10917 09:59:03.528995 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10919 09:59:03.547894 /lava-12073278/1/../bin/lava-test-case
10920 09:59:03.568229 <8>[ 29.897194] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
10921 09:59:03.568589 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10923 09:59:03.600969 /lava-12073278/1/../bin/lava-test-case
10924 09:59:03.626337 <8>[ 29.955549] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
10925 09:59:03.626651 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
10927 09:59:03.661920 /lava-12073278/1/../bin/lava-test-case
10928 09:59:03.681635 <8>[ 30.010768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
10929 09:59:03.681932 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
10931 09:59:03.701916 /lava-12073278/1/../bin/lava-test-case
10932 09:59:03.724395 <8>[ 30.053381] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
10933 09:59:03.724705 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
10935 09:59:03.755460 /lava-12073278/1/../bin/lava-test-case
10936 09:59:03.779431 <8>[ 30.108333] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
10937 09:59:03.779734 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
10939 09:59:03.800016 /lava-12073278/1/../bin/lava-test-case
10940 09:59:03.820300 <8>[ 30.148859] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
10941 09:59:03.820587 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
10943 09:59:03.848390 /lava-12073278/1/../bin/lava-test-case
10944 09:59:03.871116 <8>[ 30.200188] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
10945 09:59:03.871408 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
10947 09:59:03.898776 /lava-12073278/1/../bin/lava-test-case
10948 09:59:03.921905 <8>[ 30.250939] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
10949 09:59:03.922197 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
10951 09:59:03.950882 /lava-12073278/1/../bin/lava-test-case
10952 09:59:03.968900 <8>[ 30.298055] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
10953 09:59:03.969180 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
10955 09:59:04.010525 /lava-12073278/1/../bin/lava-test-case
10956 09:59:04.036266 <8>[ 30.365391] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
10957 09:59:04.036535 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
10959 09:59:04.056839 /lava-12073278/1/../bin/lava-test-case
10960 09:59:04.078834 <8>[ 30.407976] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
10961 09:59:04.079129 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
10963 09:59:04.104587 /lava-12073278/1/../bin/lava-test-case
10964 09:59:04.122326 <8>[ 30.451469] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
10965 09:59:04.122593 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
10967 09:59:04.148736 /lava-12073278/1/../bin/lava-test-case
10968 09:59:04.167719 <8>[ 30.496978] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
10969 09:59:04.167985 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
10971 09:59:04.185536 /lava-12073278/1/../bin/lava-test-case
10972 09:59:04.208409 <8>[ 30.537255] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
10973 09:59:04.208782 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
10975 09:59:04.239584 /lava-12073278/1/../bin/lava-test-case
10976 09:59:04.265065 <8>[ 30.593866] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
10977 09:59:04.265490 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
10979 09:59:04.288430 /lava-12073278/1/../bin/lava-test-case
10980 09:59:04.319160 <8>[ 30.647467] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
10981 09:59:04.319917 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
10983 09:59:04.364845 /lava-12073278/1/../bin/lava-test-case
10984 09:59:04.397924 <8>[ 30.726431] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
10985 09:59:04.398631 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
10987 09:59:04.422269 /lava-12073278/1/../bin/lava-test-case
10988 09:59:04.451402 <8>[ 30.779885] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
10989 09:59:04.452174 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
10991 09:59:04.489053 /lava-12073278/1/../bin/lava-test-case
10992 09:59:04.518369 <8>[ 30.847209] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
10993 09:59:04.519107 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
10995 09:59:04.542865 /lava-12073278/1/../bin/lava-test-case
10996 09:59:04.566357 <8>[ 30.895330] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
10997 09:59:04.566719 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
10999 09:59:04.599859 /lava-12073278/1/../bin/lava-test-case
11000 09:59:04.624957 <8>[ 30.953755] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11001 09:59:04.625752 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11003 09:59:04.646081 /lava-12073278/1/../bin/lava-test-case
11004 09:59:04.672106 <8>[ 31.000890] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11005 09:59:04.672787 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11007 09:59:04.710803 /lava-12073278/1/../bin/lava-test-case
11008 09:59:04.740214 <8>[ 31.068968] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11009 09:59:04.741021 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11011 09:59:04.764253 /lava-12073278/1/../bin/lava-test-case
11012 09:59:04.792045 <8>[ 31.120790] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11013 09:59:04.792864 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11015 09:59:04.830657 /lava-12073278/1/../bin/lava-test-case
11016 09:59:04.859865 <8>[ 31.188680] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11017 09:59:04.860654 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11019 09:59:04.883909 /lava-12073278/1/../bin/lava-test-case
11020 09:59:04.915923 <8>[ 31.244554] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11021 09:59:04.916611 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11023 09:59:04.954063 /lava-12073278/1/../bin/lava-test-case
11024 09:59:04.985759 <8>[ 31.314562] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11025 09:59:04.986446 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11027 09:59:05.025238 /lava-12073278/1/../bin/lava-test-case
11028 09:59:05.054603 <8>[ 31.383330] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11029 09:59:05.055350 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11031 09:59:05.087107 /lava-12073278/1/../bin/lava-test-case
11032 09:59:05.119802 <8>[ 31.448345] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11033 09:59:05.120616 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11035 09:59:05.160484 /lava-12073278/1/../bin/lava-test-case
11036 09:59:05.192967 <8>[ 31.521755] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11037 09:59:05.193759 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11039 09:59:05.216456 /lava-12073278/1/../bin/lava-test-case
11040 09:59:05.245703 <8>[ 31.574362] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11041 09:59:05.246485 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11043 09:59:05.283348 /lava-12073278/1/../bin/lava-test-case
11044 09:59:05.310548 <8>[ 31.639519] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11045 09:59:05.311334 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11047 09:59:05.349167 /lava-12073278/1/../bin/lava-test-case
11048 09:59:05.383004 <8>[ 31.711900] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11049 09:59:05.384332 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11051 09:59:05.426411 /lava-12073278/1/../bin/lava-test-case
11052 09:59:05.457450 <8>[ 31.786300] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11053 09:59:05.458139 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11055 09:59:05.494760 /lava-12073278/1/../bin/lava-test-case
11056 09:59:05.527426 <8>[ 31.856021] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11057 09:59:05.528146 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11059 09:59:05.562618 /lava-12073278/1/../bin/lava-test-case
11060 09:59:05.590419 <8>[ 31.919383] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11061 09:59:05.591115 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11063 09:59:05.614331 /lava-12073278/1/../bin/lava-test-case
11064 09:59:05.645516 <8>[ 31.974429] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11065 09:59:05.646327 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11067 09:59:05.686100 /lava-12073278/1/../bin/lava-test-case
11068 09:59:05.718276 <8>[ 32.047221] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11069 09:59:05.719039 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11071 09:59:05.759889 /lava-12073278/1/../bin/lava-test-case
11072 09:59:05.786875 <8>[ 32.115791] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11073 09:59:05.787641 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11075 09:59:05.810781 /lava-12073278/1/../bin/lava-test-case
11076 09:59:05.843232 <8>[ 32.171864] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11077 09:59:05.844056 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11079 09:59:05.884084 /lava-12073278/1/../bin/lava-test-case
11080 09:59:05.915984 <8>[ 32.244734] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11081 09:59:05.916687 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11083 09:59:05.938567 /lava-12073278/1/../bin/lava-test-case
11084 09:59:05.966268 <8>[ 32.294850] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11085 09:59:05.967060 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11087 09:59:05.999236 /lava-12073278/1/../bin/lava-test-case
11088 09:59:06.027157 <8>[ 32.355803] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11089 09:59:06.027906 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11091 09:59:06.048273 /lava-12073278/1/../bin/lava-test-case
11092 09:59:06.075626 <8>[ 32.404282] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11093 09:59:06.076285 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11095 09:59:06.115402 /lava-12073278/1/../bin/lava-test-case
11096 09:59:06.143665 <8>[ 32.472536] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11097 09:59:06.144570 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11099 09:59:06.180044 /lava-12073278/1/../bin/lava-test-case
11100 09:59:06.207113 <8>[ 32.535906] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11101 09:59:06.207896 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11103 09:59:06.247418 /lava-12073278/1/../bin/lava-test-case
11104 09:59:06.279018 <8>[ 32.607910] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11105 09:59:06.279832 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11107 09:59:06.317586 /lava-12073278/1/../bin/lava-test-case
11108 09:59:06.348897 <8>[ 32.677633] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11109 09:59:06.349701 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11111 09:59:06.388064 /lava-12073278/1/../bin/lava-test-case
11112 09:59:06.416898 <8>[ 32.745759] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11113 09:59:06.417661 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11115 09:59:06.461253 /lava-12073278/1/../bin/lava-test-case
11116 09:59:06.493589 <8>[ 32.822554] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11117 09:59:06.494323 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11119 09:59:06.531262 /lava-12073278/1/../bin/lava-test-case
11120 09:59:06.560781 <8>[ 32.889798] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11121 09:59:06.561720 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11123 09:59:06.600233 /lava-12073278/1/../bin/lava-test-case
11124 09:59:06.634007 <8>[ 32.962610] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11125 09:59:06.634913 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11127 09:59:06.671180 /lava-12073278/1/../bin/lava-test-case
11128 09:59:06.695642 <8>[ 33.024675] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11129 09:59:06.696007 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11131 09:59:06.729855 /lava-12073278/1/../bin/lava-test-case
11132 09:59:06.760155 <8>[ 33.089089] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11133 09:59:06.760949 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11135 09:59:06.804385 /lava-12073278/1/../bin/lava-test-case
11136 09:59:06.831410 <8>[ 33.160549] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11137 09:59:06.831764 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11139 09:59:06.866787 /lava-12073278/1/../bin/lava-test-case
11140 09:59:06.891287 <8>[ 33.220572] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11141 09:59:06.891572 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11143 09:59:06.923044 /lava-12073278/1/../bin/lava-test-case
11144 09:59:06.950093 <8>[ 33.279253] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11145 09:59:06.950507 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11147 09:59:06.984796 /lava-12073278/1/../bin/lava-test-case
11148 09:59:07.013894 <8>[ 33.342759] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11149 09:59:07.014799 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11151 09:59:07.049474 /lava-12073278/1/../bin/lava-test-case
11152 09:59:07.080926 <8>[ 33.409700] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11153 09:59:07.081634 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11155 09:59:07.103181 /lava-12073278/1/../bin/lava-test-case
11156 09:59:07.127122 <8>[ 33.456385] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11157 09:59:07.127407 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11159 09:59:07.163120 /lava-12073278/1/../bin/lava-test-case
11160 09:59:07.186788 <8>[ 33.515819] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11161 09:59:07.187216 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11163 09:59:07.206245 /lava-12073278/1/../bin/lava-test-case
11164 09:59:07.230605 <8>[ 33.559831] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11165 09:59:07.230958 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11167 09:59:07.259793 /lava-12073278/1/../bin/lava-test-case
11168 09:59:07.285641 <8>[ 33.614563] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11169 09:59:07.286452 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11171 09:59:07.308181 /lava-12073278/1/../bin/lava-test-case
11172 09:59:07.340142 <8>[ 33.669055] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11173 09:59:07.340913 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11175 09:59:07.379358 /lava-12073278/1/../bin/lava-test-case
11176 09:59:07.410307 <8>[ 33.739242] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11177 09:59:07.411068 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11179 09:59:07.435376 /lava-12073278/1/../bin/lava-test-case
11180 09:59:07.465295 <8>[ 33.794398] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11181 09:59:07.465989 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11183 09:59:07.511139 /lava-12073278/1/../bin/lava-test-case
11184 09:59:07.538802 <8>[ 33.867691] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11185 09:59:07.539186 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11187 09:59:07.561010 /lava-12073278/1/../bin/lava-test-case
11188 09:59:07.589727 <8>[ 33.919008] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11189 09:59:07.590421 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11191 09:59:07.629569 /lava-12073278/1/../bin/lava-test-case
11192 09:59:07.660682 <8>[ 33.989719] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11193 09:59:07.661436 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11195 09:59:07.683207 /lava-12073278/1/../bin/lava-test-case
11196 09:59:07.711254 <8>[ 34.040220] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11197 09:59:07.712017 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11199 09:59:07.751262 /lava-12073278/1/../bin/lava-test-case
11200 09:59:07.780649 <8>[ 34.109417] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11201 09:59:07.781408 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11203 09:59:07.817941 /lava-12073278/1/../bin/lava-test-case
11204 09:59:07.848928 <8>[ 34.177752] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11205 09:59:07.849797 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11207 09:59:07.882452 /lava-12073278/1/../bin/lava-test-case
11208 09:59:07.911412 <8>[ 34.240775] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11209 09:59:07.911771 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11211 09:59:07.947335 /lava-12073278/1/../bin/lava-test-case
11212 09:59:07.974240 <8>[ 34.303487] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11213 09:59:07.974627 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11215 09:59:07.995395 /lava-12073278/1/../bin/lava-test-case
11216 09:59:08.020283 <8>[ 34.349086] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11217 09:59:08.021068 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11219 09:59:08.055880 /lava-12073278/1/../bin/lava-test-case
11220 09:59:08.087023 <8>[ 34.416228] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11221 09:59:08.087737 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11223 09:59:08.110392 /lava-12073278/1/../bin/lava-test-case
11224 09:59:08.139494 <8>[ 34.467995] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11225 09:59:08.140277 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11227 09:59:09.196625 /lava-12073278/1/../bin/lava-test-case
11228 09:59:09.226395 <8>[ 35.555602] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11229 09:59:09.226833 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11231 09:59:09.248610 /lava-12073278/1/../bin/lava-test-case
11232 09:59:09.276988 <8>[ 35.606467] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11233 09:59:09.277753 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11235 09:59:10.331338 /lava-12073278/1/../bin/lava-test-case
11236 09:59:10.367056 <8>[ 36.696083] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11237 09:59:10.367866 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11239 09:59:10.390020 /lava-12073278/1/../bin/lava-test-case
11240 09:59:10.418156 <8>[ 36.747395] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11241 09:59:10.418949 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11243 09:59:11.468560 /lava-12073278/1/../bin/lava-test-case
11244 09:59:11.502110 <8>[ 37.831892] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11245 09:59:11.502857 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11247 09:59:11.522258 /lava-12073278/1/../bin/lava-test-case
11248 09:59:11.550108 <8>[ 37.879561] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11249 09:59:11.550842 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11251 09:59:12.596071 /lava-12073278/1/../bin/lava-test-case
11252 09:59:12.630101 <8>[ 38.959387] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11253 09:59:12.630882 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11255 09:59:12.650968 /lava-12073278/1/../bin/lava-test-case
11256 09:59:12.675932 <8>[ 39.005457] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11257 09:59:12.676637 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11259 09:59:13.722091 /lava-12073278/1/../bin/lava-test-case
11260 09:59:13.759108 <8>[ 40.088981] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11261 09:59:13.759830 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11263 09:59:13.781858 /lava-12073278/1/../bin/lava-test-case
11264 09:59:13.809931 <8>[ 40.139559] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11265 09:59:13.810619 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11267 09:59:14.860231 /lava-12073278/1/../bin/lava-test-case
11268 09:59:14.886075 <8>[ 41.216106] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11269 09:59:14.886354 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11271 09:59:14.903095 /lava-12073278/1/../bin/lava-test-case
11272 09:59:14.927427 <8>[ 41.257753] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11273 09:59:14.927695 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11275 09:59:15.963723 /lava-12073278/1/../bin/lava-test-case
11276 09:59:15.988372 <8>[ 42.318348] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11277 09:59:15.988653 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11279 09:59:16.004431 /lava-12073278/1/../bin/lava-test-case
11280 09:59:16.023215 <8>[ 42.353753] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11281 09:59:16.023500 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11283 09:59:16.040661 /lava-12073278/1/../bin/lava-test-case
11284 09:59:16.059837 <8>[ 42.390332] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11285 09:59:16.060123 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11287 09:59:17.091602 /lava-12073278/1/../bin/lava-test-case
11288 09:59:17.117875 <8>[ 43.448542] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11289 09:59:17.118150 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11291 09:59:17.136191 /lava-12073278/1/../bin/lava-test-case
11292 09:59:17.157129 <8>[ 43.487721] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11293 09:59:17.157427 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11295 09:59:17.183057 /lava-12073278/1/../bin/lava-test-case
11296 09:59:17.201664 <8>[ 43.532067] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11297 09:59:17.201960 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11299 09:59:17.217664 /lava-12073278/1/../bin/lava-test-case
11300 09:59:17.236562 <8>[ 43.567317] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11301 09:59:17.236820 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11303 09:59:17.265564 /lava-12073278/1/../bin/lava-test-case
11304 09:59:17.285287 <8>[ 43.615984] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11305 09:59:17.285569 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11307 09:59:17.310243 /lava-12073278/1/../bin/lava-test-case
11308 09:59:17.329160 <8>[ 43.659528] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11309 09:59:17.329450 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11311 09:59:17.353185 /lava-12073278/1/../bin/lava-test-case
11312 09:59:17.373614 <8>[ 43.704331] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11313 09:59:17.373897 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11315 09:59:17.399666 /lava-12073278/1/../bin/lava-test-case
11316 09:59:17.417731 <8>[ 43.748058] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11317 09:59:17.418016 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11319 09:59:17.444640 /lava-12073278/1/../bin/lava-test-case
11320 09:59:17.466974 <8>[ 43.797283] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11321 09:59:17.467260 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11323 09:59:17.496798 /lava-12073278/1/../bin/lava-test-case
11324 09:59:17.516823 <8>[ 43.847546] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11325 09:59:17.517111 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11327 09:59:17.534643 /lava-12073278/1/../bin/lava-test-case
11328 09:59:17.553416 <8>[ 43.884041] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11329 09:59:17.553698 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11331 09:59:17.581561 /lava-12073278/1/../bin/lava-test-case
11332 09:59:17.602363 <8>[ 43.932914] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11333 09:59:17.602621 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11335 09:59:17.623179 /lava-12073278/1/../bin/lava-test-case
11336 09:59:17.643451 <8>[ 43.973970] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11337 09:59:17.643714 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11339 09:59:17.670829 /lava-12073278/1/../bin/lava-test-case
11340 09:59:17.689191 <8>[ 44.019770] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11341 09:59:17.689479 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11343 09:59:17.716129 /lava-12073278/1/../bin/lava-test-case
11344 09:59:17.739097 <8>[ 44.069819] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11345 09:59:17.739363 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11347 09:59:17.769152 /lava-12073278/1/../bin/lava-test-case
11348 09:59:17.789189 <8>[ 44.119789] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11349 09:59:17.789454 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11351 09:59:17.806167 /lava-12073278/1/../bin/lava-test-case
11352 09:59:17.825618 <8>[ 44.156273] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11353 09:59:17.825918 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11355 09:59:17.856042 /lava-12073278/1/../bin/lava-test-case
11356 09:59:17.876141 <8>[ 44.206648] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11357 09:59:17.876426 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11359 09:59:17.893263 /lava-12073278/1/../bin/lava-test-case
11360 09:59:17.915825 <8>[ 44.246349] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11361 09:59:17.916115 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11363 09:59:17.945247 /lava-12073278/1/../bin/lava-test-case
11364 09:59:17.965717 <8>[ 44.296475] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11365 09:59:17.966001 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11367 09:59:17.984476 /lava-12073278/1/../bin/lava-test-case
11368 09:59:18.004061 <8>[ 44.334782] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11369 09:59:18.004359 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11371 09:59:19.047311 /lava-12073278/1/../bin/lava-test-case
11372 09:59:19.072173 <8>[ 45.402994] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11373 09:59:19.072470 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11375 09:59:19.819408 <6>[ 46.156698] vpu: disabling
11376 09:59:19.822809 <6>[ 46.159816] vproc2: disabling
11377 09:59:19.825825 <6>[ 46.163238] vproc1: disabling
11378 09:59:19.829087 <6>[ 46.166547] vaud18: disabling
11379 09:59:19.836381 <6>[ 46.170056] vsram_others: disabling
11380 09:59:19.839563 <6>[ 46.174014] va09: disabling
11381 09:59:19.842602 <6>[ 46.177179] vsram_md: disabling
11382 09:59:19.845806 <6>[ 46.180741] Vgpu: disabling
11383 09:59:20.104795 /lava-12073278/1/../bin/lava-test-case
11384 09:59:20.128871 <8>[ 46.459978] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11385 09:59:20.129180 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11387 09:59:20.157224 /lava-12073278/1/../bin/lava-test-case
11388 09:59:20.178930 <8>[ 46.509907] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11389 09:59:20.179215 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11391 09:59:20.211577 /lava-12073278/1/../bin/lava-test-case
11392 09:59:20.234525 <8>[ 46.565682] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11393 09:59:20.234827 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11395 09:59:20.255842 /lava-12073278/1/../bin/lava-test-case
11396 09:59:20.280938 <8>[ 46.611734] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11397 09:59:20.281242 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11399 09:59:20.312110 /lava-12073278/1/../bin/lava-test-case
11400 09:59:20.332976 <8>[ 46.664110] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11401 09:59:20.333235 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11403 09:59:20.350825 /lava-12073278/1/../bin/lava-test-case
11404 09:59:20.369121 <8>[ 46.700217] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11405 09:59:20.369443 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11407 09:59:20.392342 /lava-12073278/1/../bin/lava-test-case
11408 09:59:20.410904 <8>[ 46.741964] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11409 09:59:20.411199 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11411 09:59:20.426032 /lava-12073278/1/../bin/lava-test-case
11412 09:59:20.445245 <8>[ 46.776107] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11413 09:59:20.445536 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11415 09:59:20.479734 /lava-12073278/1/../bin/lava-test-case
11416 09:59:20.498746 <8>[ 46.829738] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11417 09:59:20.499034 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11419 09:59:20.514467 /lava-12073278/1/../bin/lava-test-case
11420 09:59:20.534798 <8>[ 46.865944] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11421 09:59:20.535091 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11423 09:59:20.557221 /lava-12073278/1/../bin/lava-test-case
11424 09:59:20.576780 <8>[ 46.907624] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11425 09:59:20.577074 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11427 09:59:20.593830 /lava-12073278/1/../bin/lava-test-case
11428 09:59:20.612163 <8>[ 46.943211] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11429 09:59:20.612425 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11431 09:59:20.636622 /lava-12073278/1/../bin/lava-test-case
11432 09:59:20.656979 <8>[ 46.988012] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11433 09:59:20.657273 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11435 09:59:20.673429 /lava-12073278/1/../bin/lava-test-case
11436 09:59:20.694551 <8>[ 47.025668] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11437 09:59:20.694804 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11439 09:59:20.720847 /lava-12073278/1/../bin/lava-test-case
11440 09:59:20.741772 <8>[ 47.072706] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11441 09:59:20.742039 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11443 09:59:20.759760 /lava-12073278/1/../bin/lava-test-case
11444 09:59:20.780981 <8>[ 47.112015] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11445 09:59:20.781238 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11447 09:59:20.817386 /lava-12073278/1/../bin/lava-test-case
11448 09:59:20.837937 <8>[ 47.169114] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11449 09:59:20.838202 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11451 09:59:20.856794 /lava-12073278/1/../bin/lava-test-case
11452 09:59:20.879219 <8>[ 47.210228] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11453 09:59:20.879482 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11455 09:59:20.908854 /lava-12073278/1/../bin/lava-test-case
11456 09:59:20.932970 <8>[ 47.263682] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11457 09:59:20.933232 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11459 09:59:20.950581 /lava-12073278/1/../bin/lava-test-case
11460 09:59:20.972753 <8>[ 47.303887] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11461 09:59:20.973018 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11463 09:59:21.003048 /lava-12073278/1/../bin/lava-test-case
11464 09:59:21.020797 <8>[ 47.351838] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11465 09:59:21.021056 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11467 09:59:22.050671 /lava-12073278/1/../bin/lava-test-case
11468 09:59:22.076787 <8>[ 48.407776] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11469 09:59:22.077059 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11471 09:59:23.103127 /lava-12073278/1/../bin/lava-test-case
11472 09:59:23.125957 <8>[ 49.457200] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11473 09:59:23.126237 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11474 09:59:23.126324 Bad test result: blocked
11475 09:59:23.145180 /lava-12073278/1/../bin/lava-test-case
11476 09:59:23.165676 <8>[ 49.496605] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11477 09:59:23.165966 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11479 09:59:24.204818 /lava-12073278/1/../bin/lava-test-case
11480 09:59:24.230139 <8>[ 50.561735] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11481 09:59:24.230412 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11483 09:59:24.246173 /lava-12073278/1/../bin/lava-test-case
11484 09:59:24.266243 <8>[ 50.597116] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11485 09:59:24.266502 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11487 09:59:24.289556 /lava-12073278/1/../bin/lava-test-case
11488 09:59:24.308024 <8>[ 50.639521] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11489 09:59:24.308313 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11491 09:59:24.331060 /lava-12073278/1/../bin/lava-test-case
11492 09:59:24.349276 <8>[ 50.680792] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11493 09:59:24.349539 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11495 09:59:24.368265 /lava-12073278/1/../bin/lava-test-case
11496 09:59:24.388964 <8>[ 50.720550] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11497 09:59:24.389247 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11499 09:59:24.415472 /lava-12073278/1/../bin/lava-test-case
11500 09:59:24.433689 <8>[ 50.764962] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11501 09:59:24.433986 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11503 09:59:24.450057 /lava-12073278/1/../bin/lava-test-case
11504 09:59:24.472177 <8>[ 50.803522] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11505 09:59:24.472464 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11507 09:59:25.512697 /lava-12073278/1/../bin/lava-test-case
11508 09:59:25.537677 <8>[ 51.869360] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11509 09:59:25.537984 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11511 09:59:25.553640 /lava-12073278/1/../bin/lava-test-case
11512 09:59:25.571434 <8>[ 51.903127] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11513 09:59:25.571719 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11515 09:59:26.601947 /lava-12073278/1/../bin/lava-test-case
11516 09:59:26.625728 <8>[ 52.957623] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11517 09:59:26.626037 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11519 09:59:26.642521 /lava-12073278/1/../bin/lava-test-case
11520 09:59:26.660952 <8>[ 52.992649] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11521 09:59:26.661216 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11523 09:59:27.696526 /lava-12073278/1/../bin/lava-test-case
11524 09:59:27.720783 <8>[ 54.052184] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11525 09:59:27.721066 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11527 09:59:27.737965 /lava-12073278/1/../bin/lava-test-case
11528 09:59:27.757199 <8>[ 54.088725] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11529 09:59:27.757501 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11531 09:59:28.795406 /lava-12073278/1/../bin/lava-test-case
11532 09:59:28.821193 <8>[ 55.153133] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11533 09:59:28.821468 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11535 09:59:28.837909 /lava-12073278/1/../bin/lava-test-case
11536 09:59:28.859594 <8>[ 55.191593] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11537 09:59:28.859854 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11539 09:59:28.882574 /lava-12073278/1/../bin/lava-test-case
11540 09:59:28.903462 <8>[ 55.235422] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11541 09:59:28.903717 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11543 09:59:28.927661 /lava-12073278/1/../bin/lava-test-case
11544 09:59:28.947964 <8>[ 55.280029] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11545 09:59:28.948226 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11547 09:59:28.963853 /lava-12073278/1/../bin/lava-test-case
11548 09:59:28.983151 <8>[ 55.314941] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11549 09:59:28.983413 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11551 09:59:29.009593 /lava-12073278/1/../bin/lava-test-case
11552 09:59:29.029382 <8>[ 55.361375] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11553 09:59:29.029641 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11555 09:59:29.045867 /lava-12073278/1/../bin/lava-test-case
11556 09:59:29.065506 <8>[ 55.397392] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11557 09:59:29.065809 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11559 09:59:29.091683 /lava-12073278/1/../bin/lava-test-case
11560 09:59:29.112486 <8>[ 55.444491] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11561 09:59:29.112791 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11563 09:59:29.139321 /lava-12073278/1/../bin/lava-test-case
11564 09:59:29.157870 <8>[ 55.489693] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11565 09:59:29.158167 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11567 09:59:29.186607 /lava-12073278/1/../bin/lava-test-case
11568 09:59:29.207966 <8>[ 55.539951] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11569 09:59:29.208253 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11571 09:59:29.216490 + <8>[ 55.551711] <LAVA_SIGNAL_ENDRUN 1_bootrr 12073278_1.6.2.3.5>
11572 09:59:29.216806 Received signal: <ENDRUN> 1_bootrr 12073278_1.6.2.3.5
11573 09:59:29.216895 Ending use of test pattern.
11574 09:59:29.216965 Ending test lava.1_bootrr (12073278_1.6.2.3.5), duration 26.87
11576 09:59:29.219625 set +x
11577 09:59:29.223005 <LAVA_TEST_RUNNER EXIT>
11578 09:59:29.223276 ok: lava_test_shell seems to have completed
11579 09:59:29.225308 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: skip
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11580 09:59:29.225494 end: 4.1 lava-test-shell (duration 00:00:27) [common]
11581 09:59:29.225626 end: 4 lava-test-retry (duration 00:00:27) [common]
11582 09:59:29.225750 start: 5 finalize (timeout 00:07:29) [common]
11583 09:59:29.225843 start: 5.1 power-off (timeout 00:00:30) [common]
11584 09:59:29.226011 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
11585 09:59:29.302237 >> Command sent successfully.
11586 09:59:29.305159 Returned 0 in 0 seconds
11587 09:59:29.405544 end: 5.1 power-off (duration 00:00:00) [common]
11589 09:59:29.405855 start: 5.2 read-feedback (timeout 00:07:29) [common]
11590 09:59:29.406120 Listened to connection for namespace 'common' for up to 1s
11591 09:59:30.407034 Finalising connection for namespace 'common'
11592 09:59:30.407205 Disconnecting from shell: Finalise
11593 09:59:30.407282 / #
11594 09:59:30.507600 end: 5.2 read-feedback (duration 00:00:01) [common]
11595 09:59:30.507750 end: 5 finalize (duration 00:00:01) [common]
11596 09:59:30.507862 Cleaning after the job
11597 09:59:30.507962 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073278/tftp-deploy-v4nqla42/ramdisk
11598 09:59:30.510625 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073278/tftp-deploy-v4nqla42/kernel
11599 09:59:30.522840 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073278/tftp-deploy-v4nqla42/dtb
11600 09:59:30.523006 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073278/tftp-deploy-v4nqla42/nfsrootfs
11601 09:59:30.596022 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073278/tftp-deploy-v4nqla42/modules
11602 09:59:30.603300 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12073278
11603 09:59:30.997979 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12073278
11604 09:59:30.998165 Job finished correctly