Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 34
- Kernel Warnings: 16
- Boot result: PASS
- Errors: 1
1 09:57:06.327553 lava-dispatcher, installed at version: 2023.10
2 09:57:06.327749 start: 0 validate
3 09:57:06.327875 Start time: 2023-11-24 09:57:06.327868+00:00 (UTC)
4 09:57:06.327991 Using caching service: 'http://localhost/cache/?uri=%s'
5 09:57:06.328126 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 09:57:06.595089 Using caching service: 'http://localhost/cache/?uri=%s'
7 09:57:06.595353 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 09:57:26.099672 Using caching service: 'http://localhost/cache/?uri=%s'
9 09:57:26.100397 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 09:57:26.377925 Using caching service: 'http://localhost/cache/?uri=%s'
11 09:57:26.378679 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 09:57:34.162666 validate duration: 27.83
14 09:57:34.162929 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 09:57:34.163025 start: 1.1 download-retry (timeout 00:10:00) [common]
16 09:57:34.163113 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 09:57:34.163234 Not decompressing ramdisk as can be used compressed.
18 09:57:34.163317 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230623.0/arm64/rootfs.cpio.gz
19 09:57:34.163382 saving as /var/lib/lava/dispatcher/tmp/12073283/tftp-deploy-xg3kmoi7/ramdisk/rootfs.cpio.gz
20 09:57:34.163447 total size: 34390042 (32 MB)
21 09:57:34.428518 progress 0 % (0 MB)
22 09:57:34.437477 progress 5 % (1 MB)
23 09:57:34.446169 progress 10 % (3 MB)
24 09:57:34.455142 progress 15 % (4 MB)
25 09:57:34.463913 progress 20 % (6 MB)
26 09:57:34.472837 progress 25 % (8 MB)
27 09:57:34.481905 progress 30 % (9 MB)
28 09:57:34.491086 progress 35 % (11 MB)
29 09:57:34.499996 progress 40 % (13 MB)
30 09:57:34.509184 progress 45 % (14 MB)
31 09:57:34.517994 progress 50 % (16 MB)
32 09:57:34.526974 progress 55 % (18 MB)
33 09:57:34.535711 progress 60 % (19 MB)
34 09:57:34.544590 progress 65 % (21 MB)
35 09:57:34.553234 progress 70 % (22 MB)
36 09:57:34.562145 progress 75 % (24 MB)
37 09:57:34.570871 progress 80 % (26 MB)
38 09:57:34.579876 progress 85 % (27 MB)
39 09:57:34.588574 progress 90 % (29 MB)
40 09:57:34.597420 progress 95 % (31 MB)
41 09:57:34.606045 progress 100 % (32 MB)
42 09:57:34.606310 32 MB downloaded in 0.44 s (74.06 MB/s)
43 09:57:34.606548 end: 1.1.1 http-download (duration 00:00:00) [common]
45 09:57:34.606824 end: 1.1 download-retry (duration 00:00:00) [common]
46 09:57:34.606928 start: 1.2 download-retry (timeout 00:10:00) [common]
47 09:57:34.607032 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 09:57:34.607210 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 09:57:34.607315 saving as /var/lib/lava/dispatcher/tmp/12073283/tftp-deploy-xg3kmoi7/kernel/Image
50 09:57:34.607418 total size: 49107456 (46 MB)
51 09:57:34.607520 No compression specified
52 09:57:34.608868 progress 0 % (0 MB)
53 09:57:34.621363 progress 5 % (2 MB)
54 09:57:34.633853 progress 10 % (4 MB)
55 09:57:34.646385 progress 15 % (7 MB)
56 09:57:34.659073 progress 20 % (9 MB)
57 09:57:34.671571 progress 25 % (11 MB)
58 09:57:34.684234 progress 30 % (14 MB)
59 09:57:34.696697 progress 35 % (16 MB)
60 09:57:34.709375 progress 40 % (18 MB)
61 09:57:34.722130 progress 45 % (21 MB)
62 09:57:34.734782 progress 50 % (23 MB)
63 09:57:34.747382 progress 55 % (25 MB)
64 09:57:34.760116 progress 60 % (28 MB)
65 09:57:34.772656 progress 65 % (30 MB)
66 09:57:34.785365 progress 70 % (32 MB)
67 09:57:34.797641 progress 75 % (35 MB)
68 09:57:34.810202 progress 80 % (37 MB)
69 09:57:34.822867 progress 85 % (39 MB)
70 09:57:34.835511 progress 90 % (42 MB)
71 09:57:34.848038 progress 95 % (44 MB)
72 09:57:34.860504 progress 100 % (46 MB)
73 09:57:34.860777 46 MB downloaded in 0.25 s (184.85 MB/s)
74 09:57:34.860955 end: 1.2.1 http-download (duration 00:00:00) [common]
76 09:57:34.861215 end: 1.2 download-retry (duration 00:00:00) [common]
77 09:57:34.861325 start: 1.3 download-retry (timeout 00:09:59) [common]
78 09:57:34.861430 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 09:57:34.861580 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 09:57:34.861683 saving as /var/lib/lava/dispatcher/tmp/12073283/tftp-deploy-xg3kmoi7/dtb/mt8192-asurada-spherion-r0.dtb
81 09:57:34.861786 total size: 47278 (0 MB)
82 09:57:34.861889 No compression specified
83 09:57:34.863624 progress 69 % (0 MB)
84 09:57:34.863929 progress 100 % (0 MB)
85 09:57:34.864101 0 MB downloaded in 0.00 s (19.49 MB/s)
86 09:57:34.864245 end: 1.3.1 http-download (duration 00:00:00) [common]
88 09:57:34.864500 end: 1.3 download-retry (duration 00:00:00) [common]
89 09:57:34.864604 start: 1.4 download-retry (timeout 00:09:59) [common]
90 09:57:34.864706 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 09:57:34.864839 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 09:57:34.864939 saving as /var/lib/lava/dispatcher/tmp/12073283/tftp-deploy-xg3kmoi7/modules/modules.tar
93 09:57:34.865041 total size: 8622040 (8 MB)
94 09:57:34.865144 Using unxz to decompress xz
95 09:57:34.869321 progress 0 % (0 MB)
96 09:57:34.894845 progress 5 % (0 MB)
97 09:57:34.918334 progress 10 % (0 MB)
98 09:57:34.942037 progress 15 % (1 MB)
99 09:57:34.965755 progress 20 % (1 MB)
100 09:57:34.989920 progress 25 % (2 MB)
101 09:57:35.015266 progress 30 % (2 MB)
102 09:57:35.041371 progress 35 % (2 MB)
103 09:57:35.064690 progress 40 % (3 MB)
104 09:57:35.088726 progress 45 % (3 MB)
105 09:57:35.113495 progress 50 % (4 MB)
106 09:57:35.137622 progress 55 % (4 MB)
107 09:57:35.162564 progress 60 % (4 MB)
108 09:57:35.190299 progress 65 % (5 MB)
109 09:57:35.214947 progress 70 % (5 MB)
110 09:57:35.238205 progress 75 % (6 MB)
111 09:57:35.265416 progress 80 % (6 MB)
112 09:57:35.291341 progress 85 % (7 MB)
113 09:57:35.316621 progress 90 % (7 MB)
114 09:57:35.346199 progress 95 % (7 MB)
115 09:57:35.376411 progress 100 % (8 MB)
116 09:57:35.381224 8 MB downloaded in 0.52 s (15.93 MB/s)
117 09:57:35.381479 end: 1.4.1 http-download (duration 00:00:01) [common]
119 09:57:35.381734 end: 1.4 download-retry (duration 00:00:01) [common]
120 09:57:35.381829 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 09:57:35.381926 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 09:57:35.382008 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 09:57:35.382091 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 09:57:35.382319 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12073283/lava-overlay-y323hu64
125 09:57:35.382506 makedir: /var/lib/lava/dispatcher/tmp/12073283/lava-overlay-y323hu64/lava-12073283/bin
126 09:57:35.382609 makedir: /var/lib/lava/dispatcher/tmp/12073283/lava-overlay-y323hu64/lava-12073283/tests
127 09:57:35.382716 makedir: /var/lib/lava/dispatcher/tmp/12073283/lava-overlay-y323hu64/lava-12073283/results
128 09:57:35.382907 Creating /var/lib/lava/dispatcher/tmp/12073283/lava-overlay-y323hu64/lava-12073283/bin/lava-add-keys
129 09:57:35.383070 Creating /var/lib/lava/dispatcher/tmp/12073283/lava-overlay-y323hu64/lava-12073283/bin/lava-add-sources
130 09:57:35.383201 Creating /var/lib/lava/dispatcher/tmp/12073283/lava-overlay-y323hu64/lava-12073283/bin/lava-background-process-start
131 09:57:35.383326 Creating /var/lib/lava/dispatcher/tmp/12073283/lava-overlay-y323hu64/lava-12073283/bin/lava-background-process-stop
132 09:57:35.383447 Creating /var/lib/lava/dispatcher/tmp/12073283/lava-overlay-y323hu64/lava-12073283/bin/lava-common-functions
133 09:57:35.383566 Creating /var/lib/lava/dispatcher/tmp/12073283/lava-overlay-y323hu64/lava-12073283/bin/lava-echo-ipv4
134 09:57:35.383691 Creating /var/lib/lava/dispatcher/tmp/12073283/lava-overlay-y323hu64/lava-12073283/bin/lava-install-packages
135 09:57:35.383809 Creating /var/lib/lava/dispatcher/tmp/12073283/lava-overlay-y323hu64/lava-12073283/bin/lava-installed-packages
136 09:57:35.383926 Creating /var/lib/lava/dispatcher/tmp/12073283/lava-overlay-y323hu64/lava-12073283/bin/lava-os-build
137 09:57:35.384050 Creating /var/lib/lava/dispatcher/tmp/12073283/lava-overlay-y323hu64/lava-12073283/bin/lava-probe-channel
138 09:57:35.384169 Creating /var/lib/lava/dispatcher/tmp/12073283/lava-overlay-y323hu64/lava-12073283/bin/lava-probe-ip
139 09:57:35.384289 Creating /var/lib/lava/dispatcher/tmp/12073283/lava-overlay-y323hu64/lava-12073283/bin/lava-target-ip
140 09:57:35.384409 Creating /var/lib/lava/dispatcher/tmp/12073283/lava-overlay-y323hu64/lava-12073283/bin/lava-target-mac
141 09:57:35.384556 Creating /var/lib/lava/dispatcher/tmp/12073283/lava-overlay-y323hu64/lava-12073283/bin/lava-target-storage
142 09:57:35.384720 Creating /var/lib/lava/dispatcher/tmp/12073283/lava-overlay-y323hu64/lava-12073283/bin/lava-test-case
143 09:57:35.384842 Creating /var/lib/lava/dispatcher/tmp/12073283/lava-overlay-y323hu64/lava-12073283/bin/lava-test-event
144 09:57:35.384965 Creating /var/lib/lava/dispatcher/tmp/12073283/lava-overlay-y323hu64/lava-12073283/bin/lava-test-feedback
145 09:57:35.385084 Creating /var/lib/lava/dispatcher/tmp/12073283/lava-overlay-y323hu64/lava-12073283/bin/lava-test-raise
146 09:57:35.385203 Creating /var/lib/lava/dispatcher/tmp/12073283/lava-overlay-y323hu64/lava-12073283/bin/lava-test-reference
147 09:57:35.385322 Creating /var/lib/lava/dispatcher/tmp/12073283/lava-overlay-y323hu64/lava-12073283/bin/lava-test-runner
148 09:57:35.385444 Creating /var/lib/lava/dispatcher/tmp/12073283/lava-overlay-y323hu64/lava-12073283/bin/lava-test-set
149 09:57:35.385562 Creating /var/lib/lava/dispatcher/tmp/12073283/lava-overlay-y323hu64/lava-12073283/bin/lava-test-shell
150 09:57:35.385684 Updating /var/lib/lava/dispatcher/tmp/12073283/lava-overlay-y323hu64/lava-12073283/bin/lava-install-packages (oe)
151 09:57:35.385833 Updating /var/lib/lava/dispatcher/tmp/12073283/lava-overlay-y323hu64/lava-12073283/bin/lava-installed-packages (oe)
152 09:57:35.385959 Creating /var/lib/lava/dispatcher/tmp/12073283/lava-overlay-y323hu64/lava-12073283/environment
153 09:57:35.386057 LAVA metadata
154 09:57:35.386130 - LAVA_JOB_ID=12073283
155 09:57:35.386200 - LAVA_DISPATCHER_IP=192.168.201.1
156 09:57:35.386312 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 09:57:35.386449 skipped lava-vland-overlay
158 09:57:35.386554 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 09:57:35.386641 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 09:57:35.386711 skipped lava-multinode-overlay
161 09:57:35.386785 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 09:57:35.386875 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 09:57:35.386952 Loading test definitions
164 09:57:35.387042 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 09:57:35.387115 Using /lava-12073283 at stage 0
166 09:57:35.387409 uuid=12073283_1.5.2.3.1 testdef=None
167 09:57:35.387497 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 09:57:35.387582 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 09:57:35.388075 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 09:57:35.388302 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 09:57:35.388985 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 09:57:35.389213 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 09:57:35.389790 runner path: /var/lib/lava/dispatcher/tmp/12073283/lava-overlay-y323hu64/lava-12073283/0/tests/0_cros-ec test_uuid 12073283_1.5.2.3.1
176 09:57:35.389939 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 09:57:35.390145 Creating lava-test-runner.conf files
179 09:57:35.390220 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12073283/lava-overlay-y323hu64/lava-12073283/0 for stage 0
180 09:57:35.390346 - 0_cros-ec
181 09:57:35.390505 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 09:57:35.390593 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 09:57:35.397853 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 09:57:35.397968 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 09:57:35.398059 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 09:57:35.398147 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 09:57:35.398236 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 09:57:36.325060 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 09:57:36.325409 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 09:57:36.325524 extracting modules file /var/lib/lava/dispatcher/tmp/12073283/tftp-deploy-xg3kmoi7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12073283/extract-overlay-ramdisk-c4b6qez_/ramdisk
191 09:57:36.542197 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 09:57:36.542373 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 09:57:36.542504 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12073283/compress-overlay-2h_nwjkn/overlay-1.5.2.4.tar.gz to ramdisk
194 09:57:36.542575 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12073283/compress-overlay-2h_nwjkn/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12073283/extract-overlay-ramdisk-c4b6qez_/ramdisk
195 09:57:36.548918 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 09:57:36.549035 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 09:57:36.549126 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 09:57:36.549211 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 09:57:36.549288 Building ramdisk /var/lib/lava/dispatcher/tmp/12073283/extract-overlay-ramdisk-c4b6qez_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12073283/extract-overlay-ramdisk-c4b6qez_/ramdisk
200 09:57:37.243764 >> 271067 blocks
201 09:57:41.988100 rename /var/lib/lava/dispatcher/tmp/12073283/extract-overlay-ramdisk-c4b6qez_/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12073283/tftp-deploy-xg3kmoi7/ramdisk/ramdisk.cpio.gz
202 09:57:41.988532 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 09:57:41.988662 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
204 09:57:41.988765 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
205 09:57:41.988869 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12073283/tftp-deploy-xg3kmoi7/kernel/Image'
206 09:57:54.375654 Returned 0 in 12 seconds
207 09:57:54.476265 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12073283/tftp-deploy-xg3kmoi7/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12073283/tftp-deploy-xg3kmoi7/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12073283/tftp-deploy-xg3kmoi7/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12073283/tftp-deploy-xg3kmoi7/kernel/image.itb
208 09:57:55.141000 output: FIT description: Kernel Image image with one or more FDT blobs
209 09:57:55.141352 output: Created: Fri Nov 24 09:57:55 2023
210 09:57:55.141435 output: Image 0 (kernel-1)
211 09:57:55.141506 output: Description:
212 09:57:55.141577 output: Created: Fri Nov 24 09:57:55 2023
213 09:57:55.141645 output: Type: Kernel Image
214 09:57:55.141709 output: Compression: lzma compressed
215 09:57:55.141774 output: Data Size: 11047542 Bytes = 10788.62 KiB = 10.54 MiB
216 09:57:55.141835 output: Architecture: AArch64
217 09:57:55.141896 output: OS: Linux
218 09:57:55.141951 output: Load Address: 0x00000000
219 09:57:55.142008 output: Entry Point: 0x00000000
220 09:57:55.142066 output: Hash algo: crc32
221 09:57:55.142128 output: Hash value: 2edffaa3
222 09:57:55.142190 output: Image 1 (fdt-1)
223 09:57:55.142247 output: Description: mt8192-asurada-spherion-r0
224 09:57:55.142303 output: Created: Fri Nov 24 09:57:55 2023
225 09:57:55.142358 output: Type: Flat Device Tree
226 09:57:55.142454 output: Compression: uncompressed
227 09:57:55.142510 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 09:57:55.142565 output: Architecture: AArch64
229 09:57:55.142620 output: Hash algo: crc32
230 09:57:55.142675 output: Hash value: cc4352de
231 09:57:55.142729 output: Image 2 (ramdisk-1)
232 09:57:55.142784 output: Description: unavailable
233 09:57:55.142838 output: Created: Fri Nov 24 09:57:55 2023
234 09:57:55.142893 output: Type: RAMDisk Image
235 09:57:55.142948 output: Compression: Unknown Compression
236 09:57:55.143002 output: Data Size: 47537480 Bytes = 46423.32 KiB = 45.34 MiB
237 09:57:55.143058 output: Architecture: AArch64
238 09:57:55.143112 output: OS: Linux
239 09:57:55.143167 output: Load Address: unavailable
240 09:57:55.143221 output: Entry Point: unavailable
241 09:57:55.143275 output: Hash algo: crc32
242 09:57:55.143329 output: Hash value: 7e3c53e6
243 09:57:55.143383 output: Default Configuration: 'conf-1'
244 09:57:55.143437 output: Configuration 0 (conf-1)
245 09:57:55.143492 output: Description: mt8192-asurada-spherion-r0
246 09:57:55.143547 output: Kernel: kernel-1
247 09:57:55.143601 output: Init Ramdisk: ramdisk-1
248 09:57:55.143655 output: FDT: fdt-1
249 09:57:55.143710 output: Loadables: kernel-1
250 09:57:55.143764 output:
251 09:57:55.143958 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 09:57:55.144060 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 09:57:55.144164 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 09:57:55.144260 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 09:57:55.144342 No LXC device requested
256 09:57:55.144422 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 09:57:55.144507 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 09:57:55.144587 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 09:57:55.144659 Checking files for TFTP limit of 4294967296 bytes.
260 09:57:55.145145 end: 1 tftp-deploy (duration 00:00:21) [common]
261 09:57:55.145253 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 09:57:55.145346 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 09:57:55.145471 substitutions:
264 09:57:55.145540 - {DTB}: 12073283/tftp-deploy-xg3kmoi7/dtb/mt8192-asurada-spherion-r0.dtb
265 09:57:55.145605 - {INITRD}: 12073283/tftp-deploy-xg3kmoi7/ramdisk/ramdisk.cpio.gz
266 09:57:55.145667 - {KERNEL}: 12073283/tftp-deploy-xg3kmoi7/kernel/Image
267 09:57:55.145726 - {LAVA_MAC}: None
268 09:57:55.145785 - {PRESEED_CONFIG}: None
269 09:57:55.145843 - {PRESEED_LOCAL}: None
270 09:57:55.145900 - {RAMDISK}: 12073283/tftp-deploy-xg3kmoi7/ramdisk/ramdisk.cpio.gz
271 09:57:55.145957 - {ROOT_PART}: None
272 09:57:55.146013 - {ROOT}: None
273 09:57:55.146070 - {SERVER_IP}: 192.168.201.1
274 09:57:55.146126 - {TEE}: None
275 09:57:55.146182 Parsed boot commands:
276 09:57:55.146238 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 09:57:55.146415 Parsed boot commands: tftpboot 192.168.201.1 12073283/tftp-deploy-xg3kmoi7/kernel/image.itb 12073283/tftp-deploy-xg3kmoi7/kernel/cmdline
278 09:57:55.146508 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 09:57:55.146596 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 09:57:55.146690 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 09:57:55.146774 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 09:57:55.146846 Not connected, no need to disconnect.
283 09:57:55.146921 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 09:57:55.147010 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 09:57:55.147079 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
286 09:57:55.150360 Setting prompt string to ['lava-test: # ']
287 09:57:55.150693 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 09:57:55.150801 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 09:57:55.150899 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 09:57:55.151030 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 09:57:55.151223 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
292 09:58:00.285095 >> Command sent successfully.
293 09:58:00.288303 Returned 0 in 5 seconds
294 09:58:00.388751 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 09:58:00.389206 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 09:58:00.389348 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 09:58:00.389474 Setting prompt string to 'Starting depthcharge on Spherion...'
299 09:58:00.389577 Changing prompt to 'Starting depthcharge on Spherion...'
300 09:58:00.389686 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 09:58:00.390059 [Enter `^Ec?' for help]
302 09:58:00.564726
303 09:58:00.564892
304 09:58:00.564965 F0: 102B 0000
305 09:58:00.565033
306 09:58:00.565095 F3: 1001 0000 [0200]
307 09:58:00.565156
308 09:58:00.568725 F3: 1001 0000
309 09:58:00.568818
310 09:58:00.568886 F7: 102D 0000
311 09:58:00.568948
312 09:58:00.569007 F1: 0000 0000
313 09:58:00.569067
314 09:58:00.572100 V0: 0000 0000 [0001]
315 09:58:00.572185
316 09:58:00.572252 00: 0007 8000
317 09:58:00.572321
318 09:58:00.576072 01: 0000 0000
319 09:58:00.576158
320 09:58:00.576228 BP: 0C00 0209 [0000]
321 09:58:00.576292
322 09:58:00.576352 G0: 1182 0000
323 09:58:00.579638
324 09:58:00.579772 EC: 0000 0021 [4000]
325 09:58:00.579892
326 09:58:00.583138 S7: 0000 0000 [0000]
327 09:58:00.583230
328 09:58:00.583297 CC: 0000 0000 [0001]
329 09:58:00.583360
330 09:58:00.586653 T0: 0000 0040 [010F]
331 09:58:00.586739
332 09:58:00.586806 Jump to BL
333 09:58:00.586868
334 09:58:00.611226
335 09:58:00.611375
336 09:58:00.611472
337 09:58:00.618554 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 09:58:00.622023 ARM64: Exception handlers installed.
339 09:58:00.625862 ARM64: Testing exception
340 09:58:00.629435 ARM64: Done test exception
341 09:58:00.637000 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 09:58:00.644242 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 09:58:00.651371 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 09:58:00.662035 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 09:58:00.668935 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 09:58:00.678795 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 09:58:00.689427 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 09:58:00.696302 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 09:58:00.714340 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 09:58:00.717513 WDT: Last reset was cold boot
351 09:58:00.720902 SPI1(PAD0) initialized at 2873684 Hz
352 09:58:00.724239 SPI5(PAD0) initialized at 992727 Hz
353 09:58:00.727449 VBOOT: Loading verstage.
354 09:58:00.734270 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 09:58:00.737362 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 09:58:00.740663 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 09:58:00.744407 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 09:58:00.751826 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 09:58:00.758403 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 09:58:00.769103 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 09:58:00.769191
362 09:58:00.769279
363 09:58:00.779226 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 09:58:00.782323 ARM64: Exception handlers installed.
365 09:58:00.785923 ARM64: Testing exception
366 09:58:00.786012 ARM64: Done test exception
367 09:58:00.792122 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 09:58:00.795969 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 09:58:00.810203 Probing TPM: . done!
370 09:58:00.810298 TPM ready after 0 ms
371 09:58:00.816945 Connected to device vid:did:rid of 1ae0:0028:00
372 09:58:00.824442 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 09:58:00.881570 Initialized TPM device CR50 revision 0
374 09:58:00.890815 tlcl_send_startup: Startup return code is 0
375 09:58:00.890907 TPM: setup succeeded
376 09:58:00.902293 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 09:58:00.910953 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 09:58:00.921243 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 09:58:00.930181 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 09:58:00.933493 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 09:58:00.944442 in-header: 03 07 00 00 08 00 00 00
382 09:58:00.947790 in-data: aa e4 47 04 13 02 00 00
383 09:58:00.951766 Chrome EC: UHEPI supported
384 09:58:00.958544 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 09:58:00.962358 in-header: 03 ad 00 00 08 00 00 00
386 09:58:00.966278 in-data: 00 20 20 08 00 00 00 00
387 09:58:00.966368 Phase 1
388 09:58:00.969917 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 09:58:00.976936 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 09:58:00.981426 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 09:58:00.984847 Recovery requested (1009000e)
392 09:58:00.994137 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 09:58:01.000242 tlcl_extend: response is 0
394 09:58:01.008970 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 09:58:01.014714 tlcl_extend: response is 0
396 09:58:01.021259 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 09:58:01.041774 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 09:58:01.049016 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 09:58:01.049117
400 09:58:01.049204
401 09:58:01.059431 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 09:58:01.062405 ARM64: Exception handlers installed.
403 09:58:01.062508 ARM64: Testing exception
404 09:58:01.065932 ARM64: Done test exception
405 09:58:01.086939 pmic_efuse_setting: Set efuses in 11 msecs
406 09:58:01.090318 pmwrap_interface_init: Select PMIF_VLD_RDY
407 09:58:01.097331 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 09:58:01.100874 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 09:58:01.104148 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 09:58:01.111185 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 09:58:01.114606 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 09:58:01.121716 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 09:58:01.125338 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 09:58:01.129579 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 09:58:01.132776 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 09:58:01.140508 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 09:58:01.144194 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 09:58:01.147949 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 09:58:01.151162 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 09:58:01.158337 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 09:58:01.164876 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 09:58:01.172129 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 09:58:01.175795 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 09:58:01.183479 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 09:58:01.187118 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 09:58:01.193558 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 09:58:01.197094 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 09:58:01.204087 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 09:58:01.210914 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 09:58:01.214132 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 09:58:01.220891 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 09:58:01.227624 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 09:58:01.230912 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 09:58:01.237479 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 09:58:01.240848 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 09:58:01.244410 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 09:58:01.250877 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 09:58:01.254297 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 09:58:01.261083 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 09:58:01.264184 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 09:58:01.270944 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 09:58:01.277669 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 09:58:01.281387 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 09:58:01.284407 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 09:58:01.291292 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 09:58:01.294344 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 09:58:01.297835 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 09:58:01.304482 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 09:58:01.308308 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 09:58:01.311916 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 09:58:01.315984 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 09:58:01.322502 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 09:58:01.325604 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 09:58:01.329078 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 09:58:01.332497 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 09:58:01.339063 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 09:58:01.342247 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 09:58:01.348924 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 09:58:01.358979 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 09:58:01.362087 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 09:58:01.371998 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 09:58:01.378882 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 09:58:01.385363 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 09:58:01.389118 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 09:58:01.391925 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 09:58:01.399792 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 09:58:01.406458 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 09:58:01.409501 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 09:58:01.413002 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 09:58:01.423845 [RTC]rtc_get_frequency_meter,154: input=15, output=771
471 09:58:01.434170 [RTC]rtc_get_frequency_meter,154: input=23, output=957
472 09:58:01.444243 [RTC]rtc_get_frequency_meter,154: input=19, output=865
473 09:58:01.453015 [RTC]rtc_get_frequency_meter,154: input=17, output=818
474 09:58:01.463025 [RTC]rtc_get_frequency_meter,154: input=16, output=796
475 09:58:01.466738 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
476 09:58:01.470657 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
477 09:58:01.473935 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
478 09:58:01.481229 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
479 09:58:01.485145 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
480 09:58:01.485235 ADC[4]: Raw value=902876 ID=7
481 09:58:01.488918 ADC[3]: Raw value=212810 ID=1
482 09:58:01.492345 RAM Code: 0x71
483 09:58:01.495598 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
484 09:58:01.499162 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
485 09:58:01.508942 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
486 09:58:01.515596 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
487 09:58:01.518963 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
488 09:58:01.522230 in-header: 03 07 00 00 08 00 00 00
489 09:58:01.525449 in-data: aa e4 47 04 13 02 00 00
490 09:58:01.529123 Chrome EC: UHEPI supported
491 09:58:01.535431 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
492 09:58:01.538946 in-header: 03 ed 00 00 08 00 00 00
493 09:58:01.542360 in-data: 80 20 60 08 00 00 00 00
494 09:58:01.545962 MRC: failed to locate region type 0.
495 09:58:01.548983 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
496 09:58:01.552648 DRAM-K: Running full calibration
497 09:58:01.560361 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
498 09:58:01.563606 header.status = 0x0
499 09:58:01.563693 header.version = 0x6 (expected: 0x6)
500 09:58:01.567274 header.size = 0xd00 (expected: 0xd00)
501 09:58:01.571078 header.flags = 0x0
502 09:58:01.577929 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
503 09:58:01.594159 read SPI 0x72590 0x1c583: 12501 us, 9287 KB/s, 74.296 Mbps
504 09:58:01.600747 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
505 09:58:01.604272 dram_init: ddr_geometry: 2
506 09:58:01.604360 [EMI] MDL number = 2
507 09:58:01.607626 [EMI] Get MDL freq = 0
508 09:58:01.611030 dram_init: ddr_type: 0
509 09:58:01.611119 is_discrete_lpddr4: 1
510 09:58:01.614643 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
511 09:58:01.614730
512 09:58:01.614798
513 09:58:01.617728 [Bian_co] ETT version 0.0.0.1
514 09:58:01.624424 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
515 09:58:01.624513
516 09:58:01.627809 dramc_set_vcore_voltage set vcore to 650000
517 09:58:01.627895 Read voltage for 800, 4
518 09:58:01.631142 Vio18 = 0
519 09:58:01.631228 Vcore = 650000
520 09:58:01.631296 Vdram = 0
521 09:58:01.634627 Vddq = 0
522 09:58:01.634713 Vmddr = 0
523 09:58:01.637860 dram_init: config_dvfs: 1
524 09:58:01.641197 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
525 09:58:01.647980 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
526 09:58:01.650956 [SwImpedanceCal] DRVP=9, DRVN=15, ODTN=9
527 09:58:01.654549 freq_region=0, Reg: DRVP=9, DRVN=15, ODTN=9
528 09:58:01.657764 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
529 09:58:01.660863 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
530 09:58:01.664663 MEM_TYPE=3, freq_sel=18
531 09:58:01.667744 sv_algorithm_assistance_LP4_1600
532 09:58:01.670916 ============ PULL DRAM RESETB DOWN ============
533 09:58:01.674246 ========== PULL DRAM RESETB DOWN end =========
534 09:58:01.681304 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
535 09:58:01.684095 ===================================
536 09:58:01.684181 LPDDR4 DRAM CONFIGURATION
537 09:58:01.687869 ===================================
538 09:58:01.690743 EX_ROW_EN[0] = 0x0
539 09:58:01.694492 EX_ROW_EN[1] = 0x0
540 09:58:01.694577 LP4Y_EN = 0x0
541 09:58:01.697498 WORK_FSP = 0x0
542 09:58:01.697583 WL = 0x2
543 09:58:01.700964 RL = 0x2
544 09:58:01.701049 BL = 0x2
545 09:58:01.704314 RPST = 0x0
546 09:58:01.704400 RD_PRE = 0x0
547 09:58:01.707901 WR_PRE = 0x1
548 09:58:01.707987 WR_PST = 0x0
549 09:58:01.710958 DBI_WR = 0x0
550 09:58:01.711061 DBI_RD = 0x0
551 09:58:01.714182 OTF = 0x1
552 09:58:01.717671 ===================================
553 09:58:01.721173 ===================================
554 09:58:01.721258 ANA top config
555 09:58:01.724407 ===================================
556 09:58:01.727569 DLL_ASYNC_EN = 0
557 09:58:01.731037 ALL_SLAVE_EN = 1
558 09:58:01.734406 NEW_RANK_MODE = 1
559 09:58:01.734506 DLL_IDLE_MODE = 1
560 09:58:01.737521 LP45_APHY_COMB_EN = 1
561 09:58:01.740905 TX_ODT_DIS = 1
562 09:58:01.744278 NEW_8X_MODE = 1
563 09:58:01.748166 ===================================
564 09:58:01.750874 ===================================
565 09:58:01.754066 data_rate = 1600
566 09:58:01.754150 CKR = 1
567 09:58:01.757582 DQ_P2S_RATIO = 8
568 09:58:01.761250 ===================================
569 09:58:01.764076 CA_P2S_RATIO = 8
570 09:58:01.767437 DQ_CA_OPEN = 0
571 09:58:01.771012 DQ_SEMI_OPEN = 0
572 09:58:01.771096 CA_SEMI_OPEN = 0
573 09:58:01.774276 CA_FULL_RATE = 0
574 09:58:01.777564 DQ_CKDIV4_EN = 1
575 09:58:01.780715 CA_CKDIV4_EN = 1
576 09:58:01.784586 CA_PREDIV_EN = 0
577 09:58:01.787792 PH8_DLY = 0
578 09:58:01.787876 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
579 09:58:01.790664 DQ_AAMCK_DIV = 4
580 09:58:01.794263 CA_AAMCK_DIV = 4
581 09:58:01.797869 CA_ADMCK_DIV = 4
582 09:58:01.800964 DQ_TRACK_CA_EN = 0
583 09:58:01.804092 CA_PICK = 800
584 09:58:01.804175 CA_MCKIO = 800
585 09:58:01.807590 MCKIO_SEMI = 0
586 09:58:01.811409 PLL_FREQ = 3068
587 09:58:01.814129 DQ_UI_PI_RATIO = 32
588 09:58:01.817423 CA_UI_PI_RATIO = 0
589 09:58:01.820982 ===================================
590 09:58:01.824378 ===================================
591 09:58:01.827639 memory_type:LPDDR4
592 09:58:01.827751 GP_NUM : 10
593 09:58:01.831085 SRAM_EN : 1
594 09:58:01.831197 MD32_EN : 0
595 09:58:01.834262 ===================================
596 09:58:01.838037 [ANA_INIT] >>>>>>>>>>>>>>
597 09:58:01.841816 <<<<<< [CONFIGURE PHASE]: ANA_TX
598 09:58:01.845355 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
599 09:58:01.849253 ===================================
600 09:58:01.849365 data_rate = 1600,PCW = 0X7600
601 09:58:01.852871 ===================================
602 09:58:01.856908 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
603 09:58:01.864244 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
604 09:58:01.867976 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
605 09:58:01.871629 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
606 09:58:01.875190 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
607 09:58:01.878667 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
608 09:58:01.881910 [ANA_INIT] flow start
609 09:58:01.885079 [ANA_INIT] PLL >>>>>>>>
610 09:58:01.885191 [ANA_INIT] PLL <<<<<<<<
611 09:58:01.888525 [ANA_INIT] MIDPI >>>>>>>>
612 09:58:01.891787 [ANA_INIT] MIDPI <<<<<<<<
613 09:58:01.891896 [ANA_INIT] DLL >>>>>>>>
614 09:58:01.896277 [ANA_INIT] flow end
615 09:58:01.899625 ============ LP4 DIFF to SE enter ============
616 09:58:01.903266 ============ LP4 DIFF to SE exit ============
617 09:58:01.906889 [ANA_INIT] <<<<<<<<<<<<<
618 09:58:01.910776 [Flow] Enable top DCM control >>>>>
619 09:58:01.910928 [Flow] Enable top DCM control <<<<<
620 09:58:01.914305 Enable DLL master slave shuffle
621 09:58:01.921691 ==============================================================
622 09:58:01.921805 Gating Mode config
623 09:58:01.929514 ==============================================================
624 09:58:01.929604 Config description:
625 09:58:01.940216 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
626 09:58:01.947715 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
627 09:58:01.951313 SELPH_MODE 0: By rank 1: By Phase
628 09:58:01.955278 ==============================================================
629 09:58:01.959247 GAT_TRACK_EN = 1
630 09:58:01.963026 RX_GATING_MODE = 2
631 09:58:01.966279 RX_GATING_TRACK_MODE = 2
632 09:58:01.970176 SELPH_MODE = 1
633 09:58:01.970276 PICG_EARLY_EN = 1
634 09:58:01.973944 VALID_LAT_VALUE = 1
635 09:58:01.981256 ==============================================================
636 09:58:01.985163 Enter into Gating configuration >>>>
637 09:58:01.988941 Exit from Gating configuration <<<<
638 09:58:01.989057 Enter into DVFS_PRE_config >>>>>
639 09:58:01.999913 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
640 09:58:02.003467 Exit from DVFS_PRE_config <<<<<
641 09:58:02.007415 Enter into PICG configuration >>>>
642 09:58:02.011321 Exit from PICG configuration <<<<
643 09:58:02.011464 [RX_INPUT] configuration >>>>>
644 09:58:02.015122 [RX_INPUT] configuration <<<<<
645 09:58:02.022676 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
646 09:58:02.026312 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
647 09:58:02.033581 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
648 09:58:02.037948 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
649 09:58:02.044793 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
650 09:58:02.052127 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
651 09:58:02.056117 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
652 09:58:02.059738 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
653 09:58:02.063666 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
654 09:58:02.066933 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
655 09:58:02.070615 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
656 09:58:02.074212 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
657 09:58:02.078261 ===================================
658 09:58:02.081887 LPDDR4 DRAM CONFIGURATION
659 09:58:02.085307 ===================================
660 09:58:02.085416 EX_ROW_EN[0] = 0x0
661 09:58:02.089036 EX_ROW_EN[1] = 0x0
662 09:58:02.089150 LP4Y_EN = 0x0
663 09:58:02.092639 WORK_FSP = 0x0
664 09:58:02.092726 WL = 0x2
665 09:58:02.096470 RL = 0x2
666 09:58:02.096556 BL = 0x2
667 09:58:02.100116 RPST = 0x0
668 09:58:02.100199 RD_PRE = 0x0
669 09:58:02.103665 WR_PRE = 0x1
670 09:58:02.103762 WR_PST = 0x0
671 09:58:02.107961 DBI_WR = 0x0
672 09:58:02.108045 DBI_RD = 0x0
673 09:58:02.108112 OTF = 0x1
674 09:58:02.111553 ===================================
675 09:58:02.115383 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
676 09:58:02.119209 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
677 09:58:02.126782 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
678 09:58:02.130795 ===================================
679 09:58:02.130880 LPDDR4 DRAM CONFIGURATION
680 09:58:02.134280 ===================================
681 09:58:02.138032 EX_ROW_EN[0] = 0x10
682 09:58:02.138116 EX_ROW_EN[1] = 0x0
683 09:58:02.141657 LP4Y_EN = 0x0
684 09:58:02.141758 WORK_FSP = 0x0
685 09:58:02.145546 WL = 0x2
686 09:58:02.145630 RL = 0x2
687 09:58:02.145696 BL = 0x2
688 09:58:02.149124 RPST = 0x0
689 09:58:02.149207 RD_PRE = 0x0
690 09:58:02.153014 WR_PRE = 0x1
691 09:58:02.153098 WR_PST = 0x0
692 09:58:02.156757 DBI_WR = 0x0
693 09:58:02.156841 DBI_RD = 0x0
694 09:58:02.160616 OTF = 0x1
695 09:58:02.160701 ===================================
696 09:58:02.167376 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
697 09:58:02.172725 nWR fixed to 40
698 09:58:02.176361 [ModeRegInit_LP4] CH0 RK0
699 09:58:02.176445 [ModeRegInit_LP4] CH0 RK1
700 09:58:02.179960 [ModeRegInit_LP4] CH1 RK0
701 09:58:02.183397 [ModeRegInit_LP4] CH1 RK1
702 09:58:02.183481 match AC timing 13
703 09:58:02.186818 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
704 09:58:02.190847 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
705 09:58:02.197770 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
706 09:58:02.201541 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
707 09:58:02.204992 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
708 09:58:02.208138 [EMI DOE] emi_dcm 0
709 09:58:02.211503 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
710 09:58:02.211614 ==
711 09:58:02.214743 Dram Type= 6, Freq= 0, CH_0, rank 0
712 09:58:02.218345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
713 09:58:02.218479 ==
714 09:58:02.224931 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
715 09:58:02.231266 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
716 09:58:02.239932 [CA 0] Center 38 (7~69) winsize 63
717 09:58:02.243251 [CA 1] Center 38 (7~69) winsize 63
718 09:58:02.246745 [CA 2] Center 35 (5~66) winsize 62
719 09:58:02.250055 [CA 3] Center 35 (5~66) winsize 62
720 09:58:02.253568 [CA 4] Center 34 (4~65) winsize 62
721 09:58:02.256902 [CA 5] Center 33 (3~64) winsize 62
722 09:58:02.256986
723 09:58:02.260044 [CmdBusTrainingLP45] Vref(ca) range 1: 32
724 09:58:02.260128
725 09:58:02.263495 [CATrainingPosCal] consider 1 rank data
726 09:58:02.266691 u2DelayCellTimex100 = 270/100 ps
727 09:58:02.270318 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
728 09:58:02.273427 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
729 09:58:02.276998 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
730 09:58:02.283434 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
731 09:58:02.287071 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
732 09:58:02.290511 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
733 09:58:02.290595
734 09:58:02.293585 CA PerBit enable=1, Macro0, CA PI delay=33
735 09:58:02.293668
736 09:58:02.297129 [CBTSetCACLKResult] CA Dly = 33
737 09:58:02.297213 CS Dly: 6 (0~37)
738 09:58:02.297279 ==
739 09:58:02.300490 Dram Type= 6, Freq= 0, CH_0, rank 1
740 09:58:02.307070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
741 09:58:02.307154 ==
742 09:58:02.310379 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
743 09:58:02.316785 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
744 09:58:02.326469 [CA 0] Center 38 (7~69) winsize 63
745 09:58:02.330112 [CA 1] Center 38 (7~69) winsize 63
746 09:58:02.333948 [CA 2] Center 36 (5~67) winsize 63
747 09:58:02.336387 [CA 3] Center 35 (5~66) winsize 62
748 09:58:02.339858 [CA 4] Center 34 (4~65) winsize 62
749 09:58:02.343437 [CA 5] Center 34 (4~65) winsize 62
750 09:58:02.343521
751 09:58:02.346371 [CmdBusTrainingLP45] Vref(ca) range 1: 34
752 09:58:02.346479
753 09:58:02.349954 [CATrainingPosCal] consider 2 rank data
754 09:58:02.353337 u2DelayCellTimex100 = 270/100 ps
755 09:58:02.357244 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
756 09:58:02.359675 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
757 09:58:02.366877 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
758 09:58:02.369933 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
759 09:58:02.372922 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
760 09:58:02.376329 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
761 09:58:02.376413
762 09:58:02.379739 CA PerBit enable=1, Macro0, CA PI delay=34
763 09:58:02.379823
764 09:58:02.383164 [CBTSetCACLKResult] CA Dly = 34
765 09:58:02.383248 CS Dly: 6 (0~38)
766 09:58:02.383315
767 09:58:02.386263 ----->DramcWriteLeveling(PI) begin...
768 09:58:02.389490 ==
769 09:58:02.392841 Dram Type= 6, Freq= 0, CH_0, rank 0
770 09:58:02.396444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
771 09:58:02.396528 ==
772 09:58:02.399659 Write leveling (Byte 0): 33 => 33
773 09:58:02.403182 Write leveling (Byte 1): 30 => 30
774 09:58:02.406329 DramcWriteLeveling(PI) end<-----
775 09:58:02.406449
776 09:58:02.406517 ==
777 09:58:02.409548 Dram Type= 6, Freq= 0, CH_0, rank 0
778 09:58:02.413114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 09:58:02.413198 ==
780 09:58:02.416289 [Gating] SW mode calibration
781 09:58:02.423198 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
782 09:58:02.427004 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
783 09:58:02.434628 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
784 09:58:02.438117 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
785 09:58:02.440849 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
786 09:58:02.444253 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
787 09:58:02.451457 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 09:58:02.454875 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 09:58:02.458223 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 09:58:02.461369 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 09:58:02.467966 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 09:58:02.471437 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 09:58:02.474921 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 09:58:02.481473 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 09:58:02.484799 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 09:58:02.488454 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 09:58:02.495092 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 09:58:02.498364 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 09:58:02.501570 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 09:58:02.509177 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
801 09:58:02.511619 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
802 09:58:02.514980 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 09:58:02.518276 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 09:58:02.525064 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 09:58:02.528462 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 09:58:02.532207 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 09:58:02.538242 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 09:58:02.541509 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 09:58:02.544934 0 9 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
810 09:58:02.551805 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
811 09:58:02.555064 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 09:58:02.558233 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 09:58:02.564914 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 09:58:02.568440 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 09:58:02.571820 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
816 09:58:02.578695 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
817 09:58:02.581590 0 10 8 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
818 09:58:02.585023 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
819 09:58:02.591675 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 09:58:02.595086 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 09:58:02.598325 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 09:58:02.605087 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 09:58:02.609016 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 09:58:02.611879 0 11 4 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
825 09:58:02.615179 0 11 8 | B1->B0 | 2626 4545 | 1 0 | (0 0) (0 0)
826 09:58:02.621668 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
827 09:58:02.625153 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 09:58:02.628447 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 09:58:02.635224 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 09:58:02.638521 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 09:58:02.641811 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
832 09:58:02.648377 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
833 09:58:02.651688 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 09:58:02.655260 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 09:58:02.662214 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 09:58:02.665026 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 09:58:02.668397 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 09:58:02.675419 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 09:58:02.678688 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 09:58:02.681722 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 09:58:02.688899 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 09:58:02.692206 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 09:58:02.695255 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 09:58:02.698681 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 09:58:02.705095 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 09:58:02.708722 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 09:58:02.711865 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 09:58:02.718630 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
849 09:58:02.722032 Total UI for P1: 0, mck2ui 16
850 09:58:02.725527 best dqsien dly found for B0: ( 0, 14, 2)
851 09:58:02.728761 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
852 09:58:02.732119 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 09:58:02.735281 Total UI for P1: 0, mck2ui 16
854 09:58:02.738905 best dqsien dly found for B1: ( 0, 14, 8)
855 09:58:02.742216 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
856 09:58:02.745336 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
857 09:58:02.745420
858 09:58:02.748866 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
859 09:58:02.755770 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
860 09:58:02.755864 [Gating] SW calibration Done
861 09:58:02.755932 ==
862 09:58:02.758997 Dram Type= 6, Freq= 0, CH_0, rank 0
863 09:58:02.765494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
864 09:58:02.765579 ==
865 09:58:02.765646 RX Vref Scan: 0
866 09:58:02.765708
867 09:58:02.769325 RX Vref 0 -> 0, step: 1
868 09:58:02.769409
869 09:58:02.772660 RX Delay -130 -> 252, step: 16
870 09:58:02.775569 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
871 09:58:02.779022 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
872 09:58:02.782304 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
873 09:58:02.785868 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
874 09:58:02.792429 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
875 09:58:02.796200 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
876 09:58:02.799041 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
877 09:58:02.802674 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
878 09:58:02.808891 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
879 09:58:02.812466 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
880 09:58:02.815951 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
881 09:58:02.819164 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
882 09:58:02.822749 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
883 09:58:02.829555 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
884 09:58:02.832367 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
885 09:58:02.835962 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
886 09:58:02.836047 ==
887 09:58:02.839214 Dram Type= 6, Freq= 0, CH_0, rank 0
888 09:58:02.842892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
889 09:58:02.842978 ==
890 09:58:02.845722 DQS Delay:
891 09:58:02.845807 DQS0 = 0, DQS1 = 0
892 09:58:02.845875 DQM Delay:
893 09:58:02.849060 DQM0 = 89, DQM1 = 80
894 09:58:02.849146 DQ Delay:
895 09:58:02.852728 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
896 09:58:02.856014 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
897 09:58:02.859203 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
898 09:58:02.862580 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =93
899 09:58:02.862665
900 09:58:02.862732
901 09:58:02.862794 ==
902 09:58:02.865850 Dram Type= 6, Freq= 0, CH_0, rank 0
903 09:58:02.873139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 09:58:02.873224 ==
905 09:58:02.873293
906 09:58:02.873357
907 09:58:02.873418 TX Vref Scan disable
908 09:58:02.876326 == TX Byte 0 ==
909 09:58:02.879947 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
910 09:58:02.882964 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
911 09:58:02.886565 == TX Byte 1 ==
912 09:58:02.889585 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
913 09:58:02.893097 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
914 09:58:02.896553 ==
915 09:58:02.899517 Dram Type= 6, Freq= 0, CH_0, rank 0
916 09:58:02.903158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
917 09:58:02.903243 ==
918 09:58:02.915556 TX Vref=22, minBit 11, minWin=26, winSum=436
919 09:58:02.918868 TX Vref=24, minBit 6, minWin=27, winSum=441
920 09:58:02.922244 TX Vref=26, minBit 10, minWin=27, winSum=447
921 09:58:02.925815 TX Vref=28, minBit 8, minWin=27, winSum=450
922 09:58:02.929332 TX Vref=30, minBit 3, minWin=28, winSum=454
923 09:58:02.932652 TX Vref=32, minBit 10, minWin=27, winSum=452
924 09:58:02.939205 [TxChooseVref] Worse bit 3, Min win 28, Win sum 454, Final Vref 30
925 09:58:02.939291
926 09:58:02.942416 Final TX Range 1 Vref 30
927 09:58:02.942515
928 09:58:02.942584 ==
929 09:58:02.946168 Dram Type= 6, Freq= 0, CH_0, rank 0
930 09:58:02.949664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 09:58:02.949750 ==
932 09:58:02.949819
933 09:58:02.952832
934 09:58:02.952917 TX Vref Scan disable
935 09:58:02.955756 == TX Byte 0 ==
936 09:58:02.959145 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
937 09:58:02.962541 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
938 09:58:02.965678 == TX Byte 1 ==
939 09:58:02.969110 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
940 09:58:02.972828 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
941 09:58:02.976012
942 09:58:02.976097 [DATLAT]
943 09:58:02.976171 Freq=800, CH0 RK0
944 09:58:02.976236
945 09:58:02.979455 DATLAT Default: 0xa
946 09:58:02.979540 0, 0xFFFF, sum = 0
947 09:58:02.982497 1, 0xFFFF, sum = 0
948 09:58:02.982583 2, 0xFFFF, sum = 0
949 09:58:02.985801 3, 0xFFFF, sum = 0
950 09:58:02.985886 4, 0xFFFF, sum = 0
951 09:58:02.989223 5, 0xFFFF, sum = 0
952 09:58:02.992517 6, 0xFFFF, sum = 0
953 09:58:02.992603 7, 0xFFFF, sum = 0
954 09:58:02.995751 8, 0xFFFF, sum = 0
955 09:58:02.995837 9, 0x0, sum = 1
956 09:58:02.995909 10, 0x0, sum = 2
957 09:58:02.999202 11, 0x0, sum = 3
958 09:58:02.999293 12, 0x0, sum = 4
959 09:58:03.002259 best_step = 10
960 09:58:03.002380
961 09:58:03.002476 ==
962 09:58:03.005846 Dram Type= 6, Freq= 0, CH_0, rank 0
963 09:58:03.009424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
964 09:58:03.009522 ==
965 09:58:03.012598 RX Vref Scan: 1
966 09:58:03.012749
967 09:58:03.012881 Set Vref Range= 32 -> 127
968 09:58:03.012988
969 09:58:03.016127 RX Vref 32 -> 127, step: 1
970 09:58:03.016218
971 09:58:03.018968 RX Delay -95 -> 252, step: 8
972 09:58:03.019058
973 09:58:03.022429 Set Vref, RX VrefLevel [Byte0]: 32
974 09:58:03.025970 [Byte1]: 32
975 09:58:03.026073
976 09:58:03.028993 Set Vref, RX VrefLevel [Byte0]: 33
977 09:58:03.032739 [Byte1]: 33
978 09:58:03.036069
979 09:58:03.036210 Set Vref, RX VrefLevel [Byte0]: 34
980 09:58:03.039462 [Byte1]: 34
981 09:58:03.043865
982 09:58:03.043960 Set Vref, RX VrefLevel [Byte0]: 35
983 09:58:03.047009 [Byte1]: 35
984 09:58:03.051253
985 09:58:03.051340 Set Vref, RX VrefLevel [Byte0]: 36
986 09:58:03.054830 [Byte1]: 36
987 09:58:03.058883
988 09:58:03.058993 Set Vref, RX VrefLevel [Byte0]: 37
989 09:58:03.062199 [Byte1]: 37
990 09:58:03.067205
991 09:58:03.067321 Set Vref, RX VrefLevel [Byte0]: 38
992 09:58:03.070563 [Byte1]: 38
993 09:58:03.074182
994 09:58:03.074267 Set Vref, RX VrefLevel [Byte0]: 39
995 09:58:03.077558 [Byte1]: 39
996 09:58:03.081581
997 09:58:03.081666 Set Vref, RX VrefLevel [Byte0]: 40
998 09:58:03.085019 [Byte1]: 40
999 09:58:03.090277
1000 09:58:03.090378 Set Vref, RX VrefLevel [Byte0]: 41
1001 09:58:03.093254 [Byte1]: 41
1002 09:58:03.097133
1003 09:58:03.097218 Set Vref, RX VrefLevel [Byte0]: 42
1004 09:58:03.100358 [Byte1]: 42
1005 09:58:03.104736
1006 09:58:03.104826 Set Vref, RX VrefLevel [Byte0]: 43
1007 09:58:03.108188 [Byte1]: 43
1008 09:58:03.112275
1009 09:58:03.112364 Set Vref, RX VrefLevel [Byte0]: 44
1010 09:58:03.115535 [Byte1]: 44
1011 09:58:03.119959
1012 09:58:03.120045 Set Vref, RX VrefLevel [Byte0]: 45
1013 09:58:03.123404 [Byte1]: 45
1014 09:58:03.127169
1015 09:58:03.127254 Set Vref, RX VrefLevel [Byte0]: 46
1016 09:58:03.130546 [Byte1]: 46
1017 09:58:03.135203
1018 09:58:03.135289 Set Vref, RX VrefLevel [Byte0]: 47
1019 09:58:03.138113 [Byte1]: 47
1020 09:58:03.142585
1021 09:58:03.142670 Set Vref, RX VrefLevel [Byte0]: 48
1022 09:58:03.145956 [Byte1]: 48
1023 09:58:03.150196
1024 09:58:03.150281 Set Vref, RX VrefLevel [Byte0]: 49
1025 09:58:03.153326 [Byte1]: 49
1026 09:58:03.157513
1027 09:58:03.157597 Set Vref, RX VrefLevel [Byte0]: 50
1028 09:58:03.160977 [Byte1]: 50
1029 09:58:03.165383
1030 09:58:03.165467 Set Vref, RX VrefLevel [Byte0]: 51
1031 09:58:03.168631 [Byte1]: 51
1032 09:58:03.172875
1033 09:58:03.172958 Set Vref, RX VrefLevel [Byte0]: 52
1034 09:58:03.176165 [Byte1]: 52
1035 09:58:03.180634
1036 09:58:03.180718 Set Vref, RX VrefLevel [Byte0]: 53
1037 09:58:03.183722 [Byte1]: 53
1038 09:58:03.188355
1039 09:58:03.188438 Set Vref, RX VrefLevel [Byte0]: 54
1040 09:58:03.191498 [Byte1]: 54
1041 09:58:03.195636
1042 09:58:03.195719 Set Vref, RX VrefLevel [Byte0]: 55
1043 09:58:03.199017 [Byte1]: 55
1044 09:58:03.203101
1045 09:58:03.203185 Set Vref, RX VrefLevel [Byte0]: 56
1046 09:58:03.206659 [Byte1]: 56
1047 09:58:03.210846
1048 09:58:03.210956 Set Vref, RX VrefLevel [Byte0]: 57
1049 09:58:03.214133 [Byte1]: 57
1050 09:58:03.218501
1051 09:58:03.218585 Set Vref, RX VrefLevel [Byte0]: 58
1052 09:58:03.221963 [Byte1]: 58
1053 09:58:03.225980
1054 09:58:03.226063 Set Vref, RX VrefLevel [Byte0]: 59
1055 09:58:03.229562 [Byte1]: 59
1056 09:58:03.233588
1057 09:58:03.233672 Set Vref, RX VrefLevel [Byte0]: 60
1058 09:58:03.236881 [Byte1]: 60
1059 09:58:03.242085
1060 09:58:03.242195 Set Vref, RX VrefLevel [Byte0]: 61
1061 09:58:03.244342 [Byte1]: 61
1062 09:58:03.249071
1063 09:58:03.249154 Set Vref, RX VrefLevel [Byte0]: 62
1064 09:58:03.252221 [Byte1]: 62
1065 09:58:03.256474
1066 09:58:03.256557 Set Vref, RX VrefLevel [Byte0]: 63
1067 09:58:03.259898 [Byte1]: 63
1068 09:58:03.264164
1069 09:58:03.264248 Set Vref, RX VrefLevel [Byte0]: 64
1070 09:58:03.267842 [Byte1]: 64
1071 09:58:03.272223
1072 09:58:03.272307 Set Vref, RX VrefLevel [Byte0]: 65
1073 09:58:03.275591 [Byte1]: 65
1074 09:58:03.279103
1075 09:58:03.279186 Set Vref, RX VrefLevel [Byte0]: 66
1076 09:58:03.282516 [Byte1]: 66
1077 09:58:03.286764
1078 09:58:03.286847 Set Vref, RX VrefLevel [Byte0]: 67
1079 09:58:03.290174 [Byte1]: 67
1080 09:58:03.294386
1081 09:58:03.294471 Set Vref, RX VrefLevel [Byte0]: 68
1082 09:58:03.297867 [Byte1]: 68
1083 09:58:03.302113
1084 09:58:03.302196 Set Vref, RX VrefLevel [Byte0]: 69
1085 09:58:03.305174 [Byte1]: 69
1086 09:58:03.309710
1087 09:58:03.309794 Set Vref, RX VrefLevel [Byte0]: 70
1088 09:58:03.313017 [Byte1]: 70
1089 09:58:03.317142
1090 09:58:03.317226 Set Vref, RX VrefLevel [Byte0]: 71
1091 09:58:03.320415 [Byte1]: 71
1092 09:58:03.324916
1093 09:58:03.325013 Set Vref, RX VrefLevel [Byte0]: 72
1094 09:58:03.328100 [Byte1]: 72
1095 09:58:03.332308
1096 09:58:03.332391 Set Vref, RX VrefLevel [Byte0]: 73
1097 09:58:03.336020 [Byte1]: 73
1098 09:58:03.339869
1099 09:58:03.339953 Set Vref, RX VrefLevel [Byte0]: 74
1100 09:58:03.343740 [Byte1]: 74
1101 09:58:03.347946
1102 09:58:03.348030 Set Vref, RX VrefLevel [Byte0]: 75
1103 09:58:03.351121 [Byte1]: 75
1104 09:58:03.355425
1105 09:58:03.355509 Set Vref, RX VrefLevel [Byte0]: 76
1106 09:58:03.358579 [Byte1]: 76
1107 09:58:03.362611
1108 09:58:03.362694 Final RX Vref Byte 0 = 61 to rank0
1109 09:58:03.366198 Final RX Vref Byte 1 = 56 to rank0
1110 09:58:03.369803 Final RX Vref Byte 0 = 61 to rank1
1111 09:58:03.372792 Final RX Vref Byte 1 = 56 to rank1==
1112 09:58:03.376166 Dram Type= 6, Freq= 0, CH_0, rank 0
1113 09:58:03.382991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1114 09:58:03.383076 ==
1115 09:58:03.383143 DQS Delay:
1116 09:58:03.383206 DQS0 = 0, DQS1 = 0
1117 09:58:03.386416 DQM Delay:
1118 09:58:03.386499 DQM0 = 92, DQM1 = 82
1119 09:58:03.389699 DQ Delay:
1120 09:58:03.392799 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1121 09:58:03.396328 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1122 09:58:03.396411 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1123 09:58:03.399852 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =88
1124 09:58:03.403217
1125 09:58:03.403301
1126 09:58:03.409767 [DQSOSCAuto] RK0, (LSB)MR18= 0x3b37, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1127 09:58:03.412926 CH0 RK0: MR19=606, MR18=3B37
1128 09:58:03.419553 CH0_RK0: MR19=0x606, MR18=0x3B37, DQSOSC=394, MR23=63, INC=95, DEC=63
1129 09:58:03.419638
1130 09:58:03.422903 ----->DramcWriteLeveling(PI) begin...
1131 09:58:03.422988 ==
1132 09:58:03.426426 Dram Type= 6, Freq= 0, CH_0, rank 1
1133 09:58:03.430587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1134 09:58:03.430672 ==
1135 09:58:03.433128 Write leveling (Byte 0): 33 => 33
1136 09:58:03.436220 Write leveling (Byte 1): 28 => 28
1137 09:58:03.439652 DramcWriteLeveling(PI) end<-----
1138 09:58:03.439735
1139 09:58:03.439802 ==
1140 09:58:03.443170 Dram Type= 6, Freq= 0, CH_0, rank 1
1141 09:58:03.446403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1142 09:58:03.446517 ==
1143 09:58:03.449722 [Gating] SW mode calibration
1144 09:58:03.456465 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1145 09:58:03.463051 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1146 09:58:03.466870 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1147 09:58:03.469807 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1148 09:58:03.476722 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1149 09:58:03.479811 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 09:58:03.483423 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 09:58:03.530892 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 09:58:03.530985 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 09:58:03.531362 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 09:58:03.531872 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 09:58:03.532137 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 09:58:03.532224 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 09:58:03.532312 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 09:58:03.532557 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 09:58:03.533340 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 09:58:03.533606 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 09:58:03.533679 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 09:58:03.561118 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 09:58:03.561384 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1164 09:58:03.561638 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1165 09:58:03.561915 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 09:58:03.562000 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 09:58:03.562257 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 09:58:03.565270 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 09:58:03.568641 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 09:58:03.571755 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 09:58:03.575755 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 09:58:03.582176 0 9 8 | B1->B0 | 2b2b 3333 | 1 1 | (1 1) (1 1)
1173 09:58:03.585525 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1174 09:58:03.588411 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1175 09:58:03.595346 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 09:58:03.598802 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 09:58:03.601981 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 09:58:03.605594 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 09:58:03.612077 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
1180 09:58:03.615441 0 10 8 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (1 0)
1181 09:58:03.618596 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 09:58:03.625263 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 09:58:03.628613 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 09:58:03.631850 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 09:58:03.638807 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 09:58:03.642100 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 09:58:03.645704 0 11 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1188 09:58:03.652113 0 11 8 | B1->B0 | 3939 4242 | 0 0 | (0 0) (0 0)
1189 09:58:03.655201 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 09:58:03.658655 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 09:58:03.665363 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 09:58:03.669715 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 09:58:03.673081 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 09:58:03.675983 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1195 09:58:03.683190 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1196 09:58:03.687131 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1197 09:58:03.690347 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 09:58:03.693559 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 09:58:03.700681 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 09:58:03.704146 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 09:58:03.707374 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 09:58:03.711054 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 09:58:03.717433 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 09:58:03.720889 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 09:58:03.724098 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 09:58:03.731120 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 09:58:03.734054 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 09:58:03.737297 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 09:58:03.744018 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 09:58:03.747473 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 09:58:03.750938 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1212 09:58:03.757297 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 09:58:03.757429 Total UI for P1: 0, mck2ui 16
1214 09:58:03.764377 best dqsien dly found for B0: ( 0, 14, 4)
1215 09:58:03.764471 Total UI for P1: 0, mck2ui 16
1216 09:58:03.770853 best dqsien dly found for B1: ( 0, 14, 6)
1217 09:58:03.774180 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1218 09:58:03.777714 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1219 09:58:03.777805
1220 09:58:03.780873 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1221 09:58:03.784002 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1222 09:58:03.787642 [Gating] SW calibration Done
1223 09:58:03.787730 ==
1224 09:58:03.790994 Dram Type= 6, Freq= 0, CH_0, rank 1
1225 09:58:03.794302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1226 09:58:03.794407 ==
1227 09:58:03.797583 RX Vref Scan: 0
1228 09:58:03.797666
1229 09:58:03.797733 RX Vref 0 -> 0, step: 1
1230 09:58:03.797796
1231 09:58:03.800867 RX Delay -130 -> 252, step: 16
1232 09:58:03.804103 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1233 09:58:03.811115 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1234 09:58:03.814514 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1235 09:58:03.817446 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1236 09:58:03.820951 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1237 09:58:03.824203 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1238 09:58:03.827564 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1239 09:58:03.834190 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
1240 09:58:03.837629 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1241 09:58:03.841022 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1242 09:58:03.844196 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1243 09:58:03.847676 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1244 09:58:03.854422 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
1245 09:58:03.857468 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
1246 09:58:03.861090 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1247 09:58:03.864235 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1248 09:58:03.864323 ==
1249 09:58:03.867826 Dram Type= 6, Freq= 0, CH_0, rank 1
1250 09:58:03.874269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1251 09:58:03.874364 ==
1252 09:58:03.874443 DQS Delay:
1253 09:58:03.877744 DQS0 = 0, DQS1 = 0
1254 09:58:03.877850 DQM Delay:
1255 09:58:03.877931 DQM0 = 94, DQM1 = 83
1256 09:58:03.881161 DQ Delay:
1257 09:58:03.884312 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1258 09:58:03.887568 DQ4 =93, DQ5 =77, DQ6 =109, DQ7 =109
1259 09:58:03.891046 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =85
1260 09:58:03.894587 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1261 09:58:03.894676
1262 09:58:03.894742
1263 09:58:03.894803 ==
1264 09:58:03.897700 Dram Type= 6, Freq= 0, CH_0, rank 1
1265 09:58:03.900959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1266 09:58:03.901045 ==
1267 09:58:03.901112
1268 09:58:03.901173
1269 09:58:03.904537 TX Vref Scan disable
1270 09:58:03.904623 == TX Byte 0 ==
1271 09:58:03.911389 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1272 09:58:03.914323 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1273 09:58:03.914472 == TX Byte 1 ==
1274 09:58:03.921049 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1275 09:58:03.924641 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1276 09:58:03.924730 ==
1277 09:58:03.927832 Dram Type= 6, Freq= 0, CH_0, rank 1
1278 09:58:03.931276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1279 09:58:03.931364 ==
1280 09:58:03.945908 TX Vref=22, minBit 5, minWin=27, winSum=441
1281 09:58:03.948983 TX Vref=24, minBit 8, minWin=27, winSum=450
1282 09:58:03.952420 TX Vref=26, minBit 8, minWin=27, winSum=451
1283 09:58:03.955739 TX Vref=28, minBit 10, minWin=27, winSum=455
1284 09:58:03.959664 TX Vref=30, minBit 8, minWin=27, winSum=453
1285 09:58:03.962555 TX Vref=32, minBit 4, minWin=28, winSum=457
1286 09:58:03.969360 [TxChooseVref] Worse bit 4, Min win 28, Win sum 457, Final Vref 32
1287 09:58:03.969456
1288 09:58:03.972489 Final TX Range 1 Vref 32
1289 09:58:03.972580
1290 09:58:03.972649 ==
1291 09:58:03.976082 Dram Type= 6, Freq= 0, CH_0, rank 1
1292 09:58:03.979393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1293 09:58:03.979496 ==
1294 09:58:03.979564
1295 09:58:03.979625
1296 09:58:03.982597 TX Vref Scan disable
1297 09:58:03.985861 == TX Byte 0 ==
1298 09:58:03.989468 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1299 09:58:03.992836 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1300 09:58:03.996235 == TX Byte 1 ==
1301 09:58:03.999174 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1302 09:58:04.002646 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1303 09:58:04.002749
1304 09:58:04.006074 [DATLAT]
1305 09:58:04.006165 Freq=800, CH0 RK1
1306 09:58:04.006269
1307 09:58:04.009132 DATLAT Default: 0xa
1308 09:58:04.009216 0, 0xFFFF, sum = 0
1309 09:58:04.012594 1, 0xFFFF, sum = 0
1310 09:58:04.012690 2, 0xFFFF, sum = 0
1311 09:58:04.015920 3, 0xFFFF, sum = 0
1312 09:58:04.016007 4, 0xFFFF, sum = 0
1313 09:58:04.019675 5, 0xFFFF, sum = 0
1314 09:58:04.019760 6, 0xFFFF, sum = 0
1315 09:58:04.022654 7, 0xFFFF, sum = 0
1316 09:58:04.022738 8, 0xFFFF, sum = 0
1317 09:58:04.026009 9, 0x0, sum = 1
1318 09:58:04.026119 10, 0x0, sum = 2
1319 09:58:04.029473 11, 0x0, sum = 3
1320 09:58:04.029558 12, 0x0, sum = 4
1321 09:58:04.033115 best_step = 10
1322 09:58:04.033202
1323 09:58:04.033267 ==
1324 09:58:04.036396 Dram Type= 6, Freq= 0, CH_0, rank 1
1325 09:58:04.039518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1326 09:58:04.039602 ==
1327 09:58:04.042864 RX Vref Scan: 0
1328 09:58:04.042947
1329 09:58:04.043011 RX Vref 0 -> 0, step: 1
1330 09:58:04.043072
1331 09:58:04.045992 RX Delay -79 -> 252, step: 8
1332 09:58:04.052942 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1333 09:58:04.056282 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1334 09:58:04.059681 iDelay=209, Bit 2, Center 92 (-15 ~ 200) 216
1335 09:58:04.063096 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1336 09:58:04.066311 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1337 09:58:04.069831 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1338 09:58:04.076533 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1339 09:58:04.079584 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1340 09:58:04.083326 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1341 09:58:04.086585 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1342 09:58:04.089450 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1343 09:58:04.096517 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1344 09:58:04.099834 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1345 09:58:04.103705 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1346 09:58:04.106784 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1347 09:58:04.109814 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1348 09:58:04.113029 ==
1349 09:58:04.116460 Dram Type= 6, Freq= 0, CH_0, rank 1
1350 09:58:04.120425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1351 09:58:04.120516 ==
1352 09:58:04.120582 DQS Delay:
1353 09:58:04.122787 DQS0 = 0, DQS1 = 0
1354 09:58:04.122869 DQM Delay:
1355 09:58:04.126310 DQM0 = 91, DQM1 = 82
1356 09:58:04.126451 DQ Delay:
1357 09:58:04.129592 DQ0 =88, DQ1 =92, DQ2 =92, DQ3 =84
1358 09:58:04.132980 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1359 09:58:04.136136 DQ8 =76, DQ9 =68, DQ10 =84, DQ11 =80
1360 09:58:04.139598 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =88
1361 09:58:04.139685
1362 09:58:04.139749
1363 09:58:04.146330 [DQSOSCAuto] RK1, (LSB)MR18= 0x421c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
1364 09:58:04.149909 CH0 RK1: MR19=606, MR18=421C
1365 09:58:04.156537 CH0_RK1: MR19=0x606, MR18=0x421C, DQSOSC=393, MR23=63, INC=95, DEC=63
1366 09:58:04.159601 [RxdqsGatingPostProcess] freq 800
1367 09:58:04.163360 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1368 09:58:04.166379 Pre-setting of DQS Precalculation
1369 09:58:04.172967 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1370 09:58:04.173060 ==
1371 09:58:04.176439 Dram Type= 6, Freq= 0, CH_1, rank 0
1372 09:58:04.179624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1373 09:58:04.179709 ==
1374 09:58:04.186183 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1375 09:58:04.192697 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1376 09:58:04.200719 [CA 0] Center 36 (6~67) winsize 62
1377 09:58:04.204113 [CA 1] Center 36 (6~67) winsize 62
1378 09:58:04.207464 [CA 2] Center 34 (4~65) winsize 62
1379 09:58:04.211391 [CA 3] Center 34 (3~65) winsize 63
1380 09:58:04.213980 [CA 4] Center 34 (4~65) winsize 62
1381 09:58:04.217606 [CA 5] Center 33 (3~64) winsize 62
1382 09:58:04.217705
1383 09:58:04.220959 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1384 09:58:04.221046
1385 09:58:04.224294 [CATrainingPosCal] consider 1 rank data
1386 09:58:04.227867 u2DelayCellTimex100 = 270/100 ps
1387 09:58:04.231113 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1388 09:58:04.234193 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1389 09:58:04.240848 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1390 09:58:04.244683 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1391 09:58:04.247925 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1392 09:58:04.250878 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1393 09:58:04.250965
1394 09:58:04.254237 CA PerBit enable=1, Macro0, CA PI delay=33
1395 09:58:04.254325
1396 09:58:04.257773 [CBTSetCACLKResult] CA Dly = 33
1397 09:58:04.257885 CS Dly: 5 (0~36)
1398 09:58:04.257954 ==
1399 09:58:04.261036 Dram Type= 6, Freq= 0, CH_1, rank 1
1400 09:58:04.267460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1401 09:58:04.267561 ==
1402 09:58:04.271059 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1403 09:58:04.277385 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1404 09:58:04.287039 [CA 0] Center 36 (6~67) winsize 62
1405 09:58:04.290166 [CA 1] Center 37 (6~68) winsize 63
1406 09:58:04.293483 [CA 2] Center 35 (5~66) winsize 62
1407 09:58:04.296775 [CA 3] Center 34 (4~65) winsize 62
1408 09:58:04.300616 [CA 4] Center 34 (4~65) winsize 62
1409 09:58:04.303603 [CA 5] Center 34 (3~65) winsize 63
1410 09:58:04.303691
1411 09:58:04.307102 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1412 09:58:04.307190
1413 09:58:04.310147 [CATrainingPosCal] consider 2 rank data
1414 09:58:04.313613 u2DelayCellTimex100 = 270/100 ps
1415 09:58:04.316965 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1416 09:58:04.320326 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1417 09:58:04.327021 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1418 09:58:04.330422 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1419 09:58:04.333888 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1420 09:58:04.337310 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1421 09:58:04.337398
1422 09:58:04.341011 CA PerBit enable=1, Macro0, CA PI delay=33
1423 09:58:04.341100
1424 09:58:04.344907 [CBTSetCACLKResult] CA Dly = 33
1425 09:58:04.344996 CS Dly: 5 (0~37)
1426 09:58:04.345064
1427 09:58:04.348548 ----->DramcWriteLeveling(PI) begin...
1428 09:58:04.348635 ==
1429 09:58:04.352115 Dram Type= 6, Freq= 0, CH_1, rank 0
1430 09:58:04.356003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1431 09:58:04.356107 ==
1432 09:58:04.359731 Write leveling (Byte 0): 27 => 27
1433 09:58:04.363564 Write leveling (Byte 1): 29 => 29
1434 09:58:04.367411 DramcWriteLeveling(PI) end<-----
1435 09:58:04.367509
1436 09:58:04.367579 ==
1437 09:58:04.370967 Dram Type= 6, Freq= 0, CH_1, rank 0
1438 09:58:04.374412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1439 09:58:04.374525 ==
1440 09:58:04.377476 [Gating] SW mode calibration
1441 09:58:04.384163 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1442 09:58:04.387615 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1443 09:58:04.394345 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1444 09:58:04.397767 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1445 09:58:04.400844 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 09:58:04.407501 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 09:58:04.410996 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 09:58:04.414206 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 09:58:04.418571 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 09:58:04.424384 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 09:58:04.427788 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 09:58:04.431235 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 09:58:04.437644 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 09:58:04.440920 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 09:58:04.444290 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 09:58:04.451597 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 09:58:04.454355 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 09:58:04.457891 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1459 09:58:04.464387 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1460 09:58:04.467523 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1461 09:58:04.471003 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 09:58:04.477771 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 09:58:04.481022 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 09:58:04.484790 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 09:58:04.491055 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 09:58:04.494337 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 09:58:04.497895 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 09:58:04.501211 0 9 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1469 09:58:04.507595 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1470 09:58:04.511164 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1471 09:58:04.514459 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1472 09:58:04.521088 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 09:58:04.524518 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 09:58:04.527752 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 09:58:04.534533 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 09:58:04.537893 0 10 4 | B1->B0 | 2f2f 2f2f | 0 0 | (0 1) (1 1)
1477 09:58:04.541269 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 09:58:04.547792 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 09:58:04.551533 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 09:58:04.554990 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 09:58:04.561378 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 09:58:04.564910 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 09:58:04.567939 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 09:58:04.575069 0 11 4 | B1->B0 | 2e2e 3939 | 0 0 | (1 1) (0 0)
1485 09:58:04.577734 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1486 09:58:04.581398 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1487 09:58:04.585025 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1488 09:58:04.591656 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 09:58:04.594595 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 09:58:04.597790 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 09:58:04.605391 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 09:58:04.607774 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1493 09:58:04.611085 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 09:58:04.618055 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 09:58:04.621669 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 09:58:04.624406 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 09:58:04.631180 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 09:58:04.634290 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 09:58:04.637799 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 09:58:04.644513 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 09:58:04.647914 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 09:58:04.651120 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 09:58:04.658091 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 09:58:04.661202 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 09:58:04.665064 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 09:58:04.671136 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 09:58:04.674692 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 09:58:04.678087 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1509 09:58:04.681517 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1510 09:58:04.684569 Total UI for P1: 0, mck2ui 16
1511 09:58:04.688206 best dqsien dly found for B0: ( 0, 14, 4)
1512 09:58:04.694963 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1513 09:58:04.695067 Total UI for P1: 0, mck2ui 16
1514 09:58:04.701637 best dqsien dly found for B1: ( 0, 14, 6)
1515 09:58:04.704875 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1516 09:58:04.708121 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1517 09:58:04.708214
1518 09:58:04.711370 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1519 09:58:04.714869 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1520 09:58:04.718178 [Gating] SW calibration Done
1521 09:58:04.718300 ==
1522 09:58:04.721456 Dram Type= 6, Freq= 0, CH_1, rank 0
1523 09:58:04.724790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1524 09:58:04.724877 ==
1525 09:58:04.728054 RX Vref Scan: 0
1526 09:58:04.728139
1527 09:58:04.728205 RX Vref 0 -> 0, step: 1
1528 09:58:04.728266
1529 09:58:04.731397 RX Delay -130 -> 252, step: 16
1530 09:58:04.734723 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1531 09:58:04.741529 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1532 09:58:04.744751 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1533 09:58:04.748201 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1534 09:58:04.751395 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1535 09:58:04.754856 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1536 09:58:04.761369 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1537 09:58:04.764967 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1538 09:58:04.768030 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1539 09:58:04.771406 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1540 09:58:04.774681 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1541 09:58:04.781668 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1542 09:58:04.784587 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1543 09:58:04.788021 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1544 09:58:04.791448 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1545 09:58:04.794688 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1546 09:58:04.798071 ==
1547 09:58:04.801608 Dram Type= 6, Freq= 0, CH_1, rank 0
1548 09:58:04.804807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1549 09:58:04.804896 ==
1550 09:58:04.804963 DQS Delay:
1551 09:58:04.808163 DQS0 = 0, DQS1 = 0
1552 09:58:04.808247 DQM Delay:
1553 09:58:04.811302 DQM0 = 89, DQM1 = 80
1554 09:58:04.811394 DQ Delay:
1555 09:58:04.815018 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1556 09:58:04.818013 DQ4 =85, DQ5 =93, DQ6 =101, DQ7 =85
1557 09:58:04.821335 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1558 09:58:04.824600 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1559 09:58:04.824689
1560 09:58:04.824754
1561 09:58:04.824813 ==
1562 09:58:04.828066 Dram Type= 6, Freq= 0, CH_1, rank 0
1563 09:58:04.831403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1564 09:58:04.831491 ==
1565 09:58:04.831559
1566 09:58:04.831620
1567 09:58:04.834575 TX Vref Scan disable
1568 09:58:04.838054 == TX Byte 0 ==
1569 09:58:04.841610 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1570 09:58:04.844585 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1571 09:58:04.848049 == TX Byte 1 ==
1572 09:58:04.851299 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1573 09:58:04.854835 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1574 09:58:04.854927 ==
1575 09:58:04.858257 Dram Type= 6, Freq= 0, CH_1, rank 0
1576 09:58:04.861486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1577 09:58:04.865025 ==
1578 09:58:04.876196 TX Vref=22, minBit 8, minWin=27, winSum=447
1579 09:58:04.879394 TX Vref=24, minBit 8, minWin=27, winSum=451
1580 09:58:04.882521 TX Vref=26, minBit 15, minWin=27, winSum=455
1581 09:58:04.885875 TX Vref=28, minBit 15, minWin=27, winSum=457
1582 09:58:04.889601 TX Vref=30, minBit 15, minWin=27, winSum=459
1583 09:58:04.896318 TX Vref=32, minBit 15, minWin=27, winSum=459
1584 09:58:04.899465 [TxChooseVref] Worse bit 15, Min win 27, Win sum 459, Final Vref 30
1585 09:58:04.899556
1586 09:58:04.902805 Final TX Range 1 Vref 30
1587 09:58:04.902893
1588 09:58:04.902962 ==
1589 09:58:04.906089 Dram Type= 6, Freq= 0, CH_1, rank 0
1590 09:58:04.909612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1591 09:58:04.909700 ==
1592 09:58:04.912979
1593 09:58:04.913074
1594 09:58:04.913141 TX Vref Scan disable
1595 09:58:04.916170 == TX Byte 0 ==
1596 09:58:04.919747 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1597 09:58:04.923405 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1598 09:58:04.926948 == TX Byte 1 ==
1599 09:58:04.930060 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1600 09:58:04.933595 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1601 09:58:04.933685
1602 09:58:04.937265 [DATLAT]
1603 09:58:04.937352 Freq=800, CH1 RK0
1604 09:58:04.937420
1605 09:58:04.940212 DATLAT Default: 0xa
1606 09:58:04.940299 0, 0xFFFF, sum = 0
1607 09:58:04.944118 1, 0xFFFF, sum = 0
1608 09:58:04.944207 2, 0xFFFF, sum = 0
1609 09:58:04.947329 3, 0xFFFF, sum = 0
1610 09:58:04.947417 4, 0xFFFF, sum = 0
1611 09:58:04.950519 5, 0xFFFF, sum = 0
1612 09:58:04.950606 6, 0xFFFF, sum = 0
1613 09:58:04.953612 7, 0xFFFF, sum = 0
1614 09:58:04.953701 8, 0xFFFF, sum = 0
1615 09:58:04.957041 9, 0x0, sum = 1
1616 09:58:04.957129 10, 0x0, sum = 2
1617 09:58:04.960706 11, 0x0, sum = 3
1618 09:58:04.960794 12, 0x0, sum = 4
1619 09:58:04.960862 best_step = 10
1620 09:58:04.964114
1621 09:58:04.964201 ==
1622 09:58:04.967079 Dram Type= 6, Freq= 0, CH_1, rank 0
1623 09:58:04.971335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1624 09:58:04.971433 ==
1625 09:58:04.971503 RX Vref Scan: 1
1626 09:58:04.971566
1627 09:58:04.974079 Set Vref Range= 32 -> 127
1628 09:58:04.974165
1629 09:58:04.977556 RX Vref 32 -> 127, step: 1
1630 09:58:04.977643
1631 09:58:04.980590 RX Delay -95 -> 252, step: 8
1632 09:58:04.980676
1633 09:58:04.983969 Set Vref, RX VrefLevel [Byte0]: 32
1634 09:58:04.987595 [Byte1]: 32
1635 09:58:04.987689
1636 09:58:04.990582 Set Vref, RX VrefLevel [Byte0]: 33
1637 09:58:04.993905 [Byte1]: 33
1638 09:58:04.993994
1639 09:58:04.997452 Set Vref, RX VrefLevel [Byte0]: 34
1640 09:58:05.000642 [Byte1]: 34
1641 09:58:05.004714
1642 09:58:05.004807 Set Vref, RX VrefLevel [Byte0]: 35
1643 09:58:05.007355 [Byte1]: 35
1644 09:58:05.011640
1645 09:58:05.011732 Set Vref, RX VrefLevel [Byte0]: 36
1646 09:58:05.014875 [Byte1]: 36
1647 09:58:05.019595
1648 09:58:05.019696 Set Vref, RX VrefLevel [Byte0]: 37
1649 09:58:05.022595 [Byte1]: 37
1650 09:58:05.026855
1651 09:58:05.026948 Set Vref, RX VrefLevel [Byte0]: 38
1652 09:58:05.030161 [Byte1]: 38
1653 09:58:05.034352
1654 09:58:05.034482 Set Vref, RX VrefLevel [Byte0]: 39
1655 09:58:05.037677 [Byte1]: 39
1656 09:58:05.042080
1657 09:58:05.042171 Set Vref, RX VrefLevel [Byte0]: 40
1658 09:58:05.045690 [Byte1]: 40
1659 09:58:05.049586
1660 09:58:05.049678 Set Vref, RX VrefLevel [Byte0]: 41
1661 09:58:05.052948 [Byte1]: 41
1662 09:58:05.057155
1663 09:58:05.057247 Set Vref, RX VrefLevel [Byte0]: 42
1664 09:58:05.060630 [Byte1]: 42
1665 09:58:05.064956
1666 09:58:05.065048 Set Vref, RX VrefLevel [Byte0]: 43
1667 09:58:05.068027 [Byte1]: 43
1668 09:58:05.072355
1669 09:58:05.072447 Set Vref, RX VrefLevel [Byte0]: 44
1670 09:58:05.075532 [Byte1]: 44
1671 09:58:05.080377
1672 09:58:05.083206 Set Vref, RX VrefLevel [Byte0]: 45
1673 09:58:05.086287 [Byte1]: 45
1674 09:58:05.086409
1675 09:58:05.089832 Set Vref, RX VrefLevel [Byte0]: 46
1676 09:58:05.093356 [Byte1]: 46
1677 09:58:05.093491
1678 09:58:05.096439 Set Vref, RX VrefLevel [Byte0]: 47
1679 09:58:05.099988 [Byte1]: 47
1680 09:58:05.100130
1681 09:58:05.103248 Set Vref, RX VrefLevel [Byte0]: 48
1682 09:58:05.106662 [Byte1]: 48
1683 09:58:05.110339
1684 09:58:05.110465 Set Vref, RX VrefLevel [Byte0]: 49
1685 09:58:05.114324 [Byte1]: 49
1686 09:58:05.117911
1687 09:58:05.118005 Set Vref, RX VrefLevel [Byte0]: 50
1688 09:58:05.121431 [Byte1]: 50
1689 09:58:05.125550
1690 09:58:05.125641 Set Vref, RX VrefLevel [Byte0]: 51
1691 09:58:05.128826 [Byte1]: 51
1692 09:58:05.133229
1693 09:58:05.133324 Set Vref, RX VrefLevel [Byte0]: 52
1694 09:58:05.136524 [Byte1]: 52
1695 09:58:05.140768
1696 09:58:05.140858 Set Vref, RX VrefLevel [Byte0]: 53
1697 09:58:05.144387 [Byte1]: 53
1698 09:58:05.148410
1699 09:58:05.148500 Set Vref, RX VrefLevel [Byte0]: 54
1700 09:58:05.151963 [Byte1]: 54
1701 09:58:05.156090
1702 09:58:05.156178 Set Vref, RX VrefLevel [Byte0]: 55
1703 09:58:05.159231 [Byte1]: 55
1704 09:58:05.163505
1705 09:58:05.163595 Set Vref, RX VrefLevel [Byte0]: 56
1706 09:58:05.166807 [Byte1]: 56
1707 09:58:05.171105
1708 09:58:05.171196 Set Vref, RX VrefLevel [Byte0]: 57
1709 09:58:05.174586 [Byte1]: 57
1710 09:58:05.178947
1711 09:58:05.179043 Set Vref, RX VrefLevel [Byte0]: 58
1712 09:58:05.182369 [Byte1]: 58
1713 09:58:05.186262
1714 09:58:05.186352 Set Vref, RX VrefLevel [Byte0]: 59
1715 09:58:05.189669 [Byte1]: 59
1716 09:58:05.193893
1717 09:58:05.193983 Set Vref, RX VrefLevel [Byte0]: 60
1718 09:58:05.197150 [Byte1]: 60
1719 09:58:05.201539
1720 09:58:05.201628 Set Vref, RX VrefLevel [Byte0]: 61
1721 09:58:05.204838 [Byte1]: 61
1722 09:58:05.209037
1723 09:58:05.209130 Set Vref, RX VrefLevel [Byte0]: 62
1724 09:58:05.212463 [Byte1]: 62
1725 09:58:05.216684
1726 09:58:05.216787 Set Vref, RX VrefLevel [Byte0]: 63
1727 09:58:05.220189 [Byte1]: 63
1728 09:58:05.224256
1729 09:58:05.224347 Set Vref, RX VrefLevel [Byte0]: 64
1730 09:58:05.227682 [Byte1]: 64
1731 09:58:05.231892
1732 09:58:05.231983 Set Vref, RX VrefLevel [Byte0]: 65
1733 09:58:05.235474 [Byte1]: 65
1734 09:58:05.240123
1735 09:58:05.240216 Set Vref, RX VrefLevel [Byte0]: 66
1736 09:58:05.242698 [Byte1]: 66
1737 09:58:05.247510
1738 09:58:05.247599 Set Vref, RX VrefLevel [Byte0]: 67
1739 09:58:05.250343 [Byte1]: 67
1740 09:58:05.254651
1741 09:58:05.254741 Set Vref, RX VrefLevel [Byte0]: 68
1742 09:58:05.257882 [Byte1]: 68
1743 09:58:05.262238
1744 09:58:05.262329 Set Vref, RX VrefLevel [Byte0]: 69
1745 09:58:05.266108 [Byte1]: 69
1746 09:58:05.269875
1747 09:58:05.269964 Set Vref, RX VrefLevel [Byte0]: 70
1748 09:58:05.273455 [Byte1]: 70
1749 09:58:05.277783
1750 09:58:05.277879 Set Vref, RX VrefLevel [Byte0]: 71
1751 09:58:05.280635 [Byte1]: 71
1752 09:58:05.284919
1753 09:58:05.285009 Set Vref, RX VrefLevel [Byte0]: 72
1754 09:58:05.288538 [Byte1]: 72
1755 09:58:05.292645
1756 09:58:05.292731 Set Vref, RX VrefLevel [Byte0]: 73
1757 09:58:05.295852 [Byte1]: 73
1758 09:58:05.300467
1759 09:58:05.300556 Set Vref, RX VrefLevel [Byte0]: 74
1760 09:58:05.303663 [Byte1]: 74
1761 09:58:05.307994
1762 09:58:05.308081 Set Vref, RX VrefLevel [Byte0]: 75
1763 09:58:05.311429 [Byte1]: 75
1764 09:58:05.315727
1765 09:58:05.315836 Set Vref, RX VrefLevel [Byte0]: 76
1766 09:58:05.318821 [Byte1]: 76
1767 09:58:05.323127
1768 09:58:05.323215 Final RX Vref Byte 0 = 54 to rank0
1769 09:58:05.326565 Final RX Vref Byte 1 = 62 to rank0
1770 09:58:05.329600 Final RX Vref Byte 0 = 54 to rank1
1771 09:58:05.333167 Final RX Vref Byte 1 = 62 to rank1==
1772 09:58:05.336737 Dram Type= 6, Freq= 0, CH_1, rank 0
1773 09:58:05.343203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1774 09:58:05.343305 ==
1775 09:58:05.343374 DQS Delay:
1776 09:58:05.343435 DQS0 = 0, DQS1 = 0
1777 09:58:05.346657 DQM Delay:
1778 09:58:05.346742 DQM0 = 92, DQM1 = 82
1779 09:58:05.351249 DQ Delay:
1780 09:58:05.353147 DQ0 =96, DQ1 =84, DQ2 =84, DQ3 =92
1781 09:58:05.356412 DQ4 =88, DQ5 =108, DQ6 =100, DQ7 =88
1782 09:58:05.360014 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =80
1783 09:58:05.363184 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1784 09:58:05.363278
1785 09:58:05.363345
1786 09:58:05.369756 [DQSOSCAuto] RK0, (LSB)MR18= 0x3350, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
1787 09:58:05.373174 CH1 RK0: MR19=606, MR18=3350
1788 09:58:05.379731 CH1_RK0: MR19=0x606, MR18=0x3350, DQSOSC=389, MR23=63, INC=97, DEC=65
1789 09:58:05.379846
1790 09:58:05.383371 ----->DramcWriteLeveling(PI) begin...
1791 09:58:05.383461 ==
1792 09:58:05.386325 Dram Type= 6, Freq= 0, CH_1, rank 1
1793 09:58:05.389928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1794 09:58:05.390017 ==
1795 09:58:05.393015 Write leveling (Byte 0): 24 => 24
1796 09:58:05.396425 Write leveling (Byte 1): 31 => 31
1797 09:58:05.399848 DramcWriteLeveling(PI) end<-----
1798 09:58:05.399938
1799 09:58:05.400005 ==
1800 09:58:05.403372 Dram Type= 6, Freq= 0, CH_1, rank 1
1801 09:58:05.406489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1802 09:58:05.406577 ==
1803 09:58:05.410002 [Gating] SW mode calibration
1804 09:58:05.416832 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1805 09:58:05.423449 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1806 09:58:05.426635 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1807 09:58:05.429855 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1808 09:58:05.436961 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 09:58:05.440010 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 09:58:05.443267 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 09:58:05.449917 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 09:58:05.453111 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 09:58:05.456857 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 09:58:05.463296 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 09:58:05.466549 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 09:58:05.469767 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 09:58:05.473223 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 09:58:05.480223 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 09:58:05.483326 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 09:58:05.486834 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 09:58:05.493364 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 09:58:05.496625 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 09:58:05.500081 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1824 09:58:05.506517 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 09:58:05.510020 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 09:58:05.513345 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 09:58:05.520003 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 09:58:05.523264 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 09:58:05.526534 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 09:58:05.533483 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 09:58:05.536970 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1832 09:58:05.539788 0 9 8 | B1->B0 | 3131 3131 | 1 1 | (1 1) (0 0)
1833 09:58:05.546695 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 09:58:05.550317 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 09:58:05.553372 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 09:58:05.560111 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 09:58:05.563301 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 09:58:05.566692 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
1839 09:58:05.569818 0 10 4 | B1->B0 | 3030 3030 | 0 0 | (1 1) (0 1)
1840 09:58:05.576714 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 09:58:05.579933 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 09:58:05.583295 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 09:58:05.589791 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 09:58:05.594303 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 09:58:05.596439 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 09:58:05.603534 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 09:58:05.606892 0 11 4 | B1->B0 | 3333 3434 | 0 0 | (0 0) (0 0)
1848 09:58:05.610146 0 11 8 | B1->B0 | 4444 4545 | 0 0 | (0 0) (0 0)
1849 09:58:05.616619 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 09:58:05.619940 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 09:58:05.623181 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 09:58:05.630301 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 09:58:05.633353 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 09:58:05.636879 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 09:58:05.643801 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 09:58:05.646688 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1857 09:58:05.649876 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 09:58:05.656863 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 09:58:05.660346 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 09:58:05.663400 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 09:58:05.667042 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 09:58:05.673645 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 09:58:05.676604 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 09:58:05.680235 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 09:58:05.686607 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 09:58:05.690527 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 09:58:05.693157 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 09:58:05.700124 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 09:58:05.703255 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 09:58:05.706864 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 09:58:05.713122 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1872 09:58:05.713237 Total UI for P1: 0, mck2ui 16
1873 09:58:05.720076 best dqsien dly found for B1: ( 0, 14, 2)
1874 09:58:05.723385 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1875 09:58:05.726659 Total UI for P1: 0, mck2ui 16
1876 09:58:05.730053 best dqsien dly found for B0: ( 0, 14, 4)
1877 09:58:05.733602 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1878 09:58:05.736704 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1879 09:58:05.736797
1880 09:58:05.740148 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1881 09:58:05.743956 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1882 09:58:05.747019 [Gating] SW calibration Done
1883 09:58:05.747108 ==
1884 09:58:05.750248 Dram Type= 6, Freq= 0, CH_1, rank 1
1885 09:58:05.753655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1886 09:58:05.753766 ==
1887 09:58:05.756769 RX Vref Scan: 0
1888 09:58:05.756858
1889 09:58:05.760180 RX Vref 0 -> 0, step: 1
1890 09:58:05.760267
1891 09:58:05.760334 RX Delay -130 -> 252, step: 16
1892 09:58:05.766915 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1893 09:58:05.770222 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1894 09:58:05.773577 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1895 09:58:05.777281 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1896 09:58:05.780404 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1897 09:58:05.786856 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1898 09:58:05.790109 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1899 09:58:05.793444 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1900 09:58:05.796953 iDelay=206, Bit 8, Center 61 (-50 ~ 173) 224
1901 09:58:05.800107 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1902 09:58:05.806859 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1903 09:58:05.810081 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1904 09:58:05.813425 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1905 09:58:05.816777 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1906 09:58:05.820313 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1907 09:58:05.827101 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1908 09:58:05.827240 ==
1909 09:58:05.830003 Dram Type= 6, Freq= 0, CH_1, rank 1
1910 09:58:05.833815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1911 09:58:05.833907 ==
1912 09:58:05.833975 DQS Delay:
1913 09:58:05.837027 DQS0 = 0, DQS1 = 0
1914 09:58:05.837113 DQM Delay:
1915 09:58:05.840001 DQM0 = 87, DQM1 = 79
1916 09:58:05.840087 DQ Delay:
1917 09:58:05.843577 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1918 09:58:05.846916 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =85
1919 09:58:05.850391 DQ8 =61, DQ9 =69, DQ10 =85, DQ11 =77
1920 09:58:05.854032 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1921 09:58:05.854122
1922 09:58:05.854189
1923 09:58:05.854252 ==
1924 09:58:05.856784 Dram Type= 6, Freq= 0, CH_1, rank 1
1925 09:58:05.860264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1926 09:58:05.860354 ==
1927 09:58:05.860421
1928 09:58:05.860482
1929 09:58:05.863478 TX Vref Scan disable
1930 09:58:05.866690 == TX Byte 0 ==
1931 09:58:05.870091 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1932 09:58:05.873422 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1933 09:58:05.876837 == TX Byte 1 ==
1934 09:58:05.880124 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1935 09:58:05.883374 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1936 09:58:05.883463 ==
1937 09:58:05.886838 Dram Type= 6, Freq= 0, CH_1, rank 1
1938 09:58:05.893362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1939 09:58:05.893458 ==
1940 09:58:05.905505 TX Vref=22, minBit 8, minWin=27, winSum=448
1941 09:58:05.908840 TX Vref=24, minBit 12, minWin=27, winSum=449
1942 09:58:05.912218 TX Vref=26, minBit 1, minWin=28, winSum=457
1943 09:58:05.915568 TX Vref=28, minBit 8, minWin=28, winSum=459
1944 09:58:05.918794 TX Vref=30, minBit 9, minWin=27, winSum=457
1945 09:58:05.925420 TX Vref=32, minBit 8, minWin=27, winSum=456
1946 09:58:05.929080 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 28
1947 09:58:05.929179
1948 09:58:05.932328 Final TX Range 1 Vref 28
1949 09:58:05.932415
1950 09:58:05.932481 ==
1951 09:58:05.935620 Dram Type= 6, Freq= 0, CH_1, rank 1
1952 09:58:05.938935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1953 09:58:05.939025 ==
1954 09:58:05.942233
1955 09:58:05.942319
1956 09:58:05.942410 TX Vref Scan disable
1957 09:58:05.945822 == TX Byte 0 ==
1958 09:58:05.949090 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1959 09:58:05.952476 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1960 09:58:05.955797 == TX Byte 1 ==
1961 09:58:05.959451 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1962 09:58:05.962432 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1963 09:58:05.965859
1964 09:58:05.965949 [DATLAT]
1965 09:58:05.966017 Freq=800, CH1 RK1
1966 09:58:05.966078
1967 09:58:05.969235 DATLAT Default: 0xa
1968 09:58:05.969322 0, 0xFFFF, sum = 0
1969 09:58:05.972703 1, 0xFFFF, sum = 0
1970 09:58:05.972789 2, 0xFFFF, sum = 0
1971 09:58:05.975977 3, 0xFFFF, sum = 0
1972 09:58:05.976065 4, 0xFFFF, sum = 0
1973 09:58:05.979420 5, 0xFFFF, sum = 0
1974 09:58:05.979507 6, 0xFFFF, sum = 0
1975 09:58:05.982420 7, 0xFFFF, sum = 0
1976 09:58:05.986556 8, 0xFFFF, sum = 0
1977 09:58:05.986649 9, 0x0, sum = 1
1978 09:58:05.986717 10, 0x0, sum = 2
1979 09:58:05.989665 11, 0x0, sum = 3
1980 09:58:05.989734 12, 0x0, sum = 4
1981 09:58:05.992764 best_step = 10
1982 09:58:05.992851
1983 09:58:05.992918 ==
1984 09:58:05.996199 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 09:58:05.999240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 09:58:05.999327 ==
1987 09:58:06.002761 RX Vref Scan: 0
1988 09:58:06.002847
1989 09:58:06.002914 RX Vref 0 -> 0, step: 1
1990 09:58:06.002976
1991 09:58:06.005762 RX Delay -95 -> 252, step: 8
1992 09:58:06.012734 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
1993 09:58:06.015741 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
1994 09:58:06.019223 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
1995 09:58:06.022647 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
1996 09:58:06.026576 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1997 09:58:06.032629 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
1998 09:58:06.035968 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
1999 09:58:06.039579 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2000 09:58:06.042601 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2001 09:58:06.045772 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2002 09:58:06.049231 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2003 09:58:06.055723 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2004 09:58:06.059360 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2005 09:58:06.062507 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2006 09:58:06.065990 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2007 09:58:06.072948 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2008 09:58:06.073064 ==
2009 09:58:06.076293 Dram Type= 6, Freq= 0, CH_1, rank 1
2010 09:58:06.079262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2011 09:58:06.079351 ==
2012 09:58:06.079416 DQS Delay:
2013 09:58:06.082778 DQS0 = 0, DQS1 = 0
2014 09:58:06.082862 DQM Delay:
2015 09:58:06.086021 DQM0 = 91, DQM1 = 84
2016 09:58:06.086108 DQ Delay:
2017 09:58:06.089413 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2018 09:58:06.092682 DQ4 =92, DQ5 =100, DQ6 =96, DQ7 =88
2019 09:58:06.096233 DQ8 =68, DQ9 =76, DQ10 =84, DQ11 =80
2020 09:58:06.099263 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =96
2021 09:58:06.099350
2022 09:58:06.099416
2023 09:58:06.105959 [DQSOSCAuto] RK1, (LSB)MR18= 0x390e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
2024 09:58:06.109273 CH1 RK1: MR19=606, MR18=390E
2025 09:58:06.115949 CH1_RK1: MR19=0x606, MR18=0x390E, DQSOSC=395, MR23=63, INC=94, DEC=63
2026 09:58:06.119856 [RxdqsGatingPostProcess] freq 800
2027 09:58:06.126019 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2028 09:58:06.126159 Pre-setting of DQS Precalculation
2029 09:58:06.132496 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2030 09:58:06.139336 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2031 09:58:06.146201 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2032 09:58:06.146329
2033 09:58:06.146469
2034 09:58:06.149690 [Calibration Summary] 1600 Mbps
2035 09:58:06.152628 CH 0, Rank 0
2036 09:58:06.152717 SW Impedance : PASS
2037 09:58:06.155891 DUTY Scan : NO K
2038 09:58:06.159092 ZQ Calibration : PASS
2039 09:58:06.159184 Jitter Meter : NO K
2040 09:58:06.162587 CBT Training : PASS
2041 09:58:06.162676 Write leveling : PASS
2042 09:58:06.165772 RX DQS gating : PASS
2043 09:58:06.169337 RX DQ/DQS(RDDQC) : PASS
2044 09:58:06.169431 TX DQ/DQS : PASS
2045 09:58:06.172575 RX DATLAT : PASS
2046 09:58:06.175995 RX DQ/DQS(Engine): PASS
2047 09:58:06.176087 TX OE : NO K
2048 09:58:06.179370 All Pass.
2049 09:58:06.179459
2050 09:58:06.179545 CH 0, Rank 1
2051 09:58:06.182548 SW Impedance : PASS
2052 09:58:06.182636 DUTY Scan : NO K
2053 09:58:06.185982 ZQ Calibration : PASS
2054 09:58:06.189308 Jitter Meter : NO K
2055 09:58:06.189396 CBT Training : PASS
2056 09:58:06.192532 Write leveling : PASS
2057 09:58:06.196254 RX DQS gating : PASS
2058 09:58:06.196347 RX DQ/DQS(RDDQC) : PASS
2059 09:58:06.199345 TX DQ/DQS : PASS
2060 09:58:06.199432 RX DATLAT : PASS
2061 09:58:06.202640 RX DQ/DQS(Engine): PASS
2062 09:58:06.206671 TX OE : NO K
2063 09:58:06.206762 All Pass.
2064 09:58:06.206849
2065 09:58:06.206929 CH 1, Rank 0
2066 09:58:06.209437 SW Impedance : PASS
2067 09:58:06.212823 DUTY Scan : NO K
2068 09:58:06.212912 ZQ Calibration : PASS
2069 09:58:06.216478 Jitter Meter : NO K
2070 09:58:06.219585 CBT Training : PASS
2071 09:58:06.219679 Write leveling : PASS
2072 09:58:06.222992 RX DQS gating : PASS
2073 09:58:06.226358 RX DQ/DQS(RDDQC) : PASS
2074 09:58:06.226491 TX DQ/DQS : PASS
2075 09:58:06.229499 RX DATLAT : PASS
2076 09:58:06.229586 RX DQ/DQS(Engine): PASS
2077 09:58:06.233008 TX OE : NO K
2078 09:58:06.233095 All Pass.
2079 09:58:06.233181
2080 09:58:06.236183 CH 1, Rank 1
2081 09:58:06.239639 SW Impedance : PASS
2082 09:58:06.239765 DUTY Scan : NO K
2083 09:58:06.243334 ZQ Calibration : PASS
2084 09:58:06.243448 Jitter Meter : NO K
2085 09:58:06.246259 CBT Training : PASS
2086 09:58:06.249994 Write leveling : PASS
2087 09:58:06.250087 RX DQS gating : PASS
2088 09:58:06.253081 RX DQ/DQS(RDDQC) : PASS
2089 09:58:06.256124 TX DQ/DQS : PASS
2090 09:58:06.256214 RX DATLAT : PASS
2091 09:58:06.259453 RX DQ/DQS(Engine): PASS
2092 09:58:06.263122 TX OE : NO K
2093 09:58:06.263214 All Pass.
2094 09:58:06.263302
2095 09:58:06.263384 DramC Write-DBI off
2096 09:58:06.266462 PER_BANK_REFRESH: Hybrid Mode
2097 09:58:06.269750 TX_TRACKING: ON
2098 09:58:06.273217 [GetDramInforAfterCalByMRR] Vendor 6.
2099 09:58:06.277047 [GetDramInforAfterCalByMRR] Revision 606.
2100 09:58:06.279630 [GetDramInforAfterCalByMRR] Revision 2 0.
2101 09:58:06.279721 MR0 0x3b3b
2102 09:58:06.283070 MR8 0x5151
2103 09:58:06.286608 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2104 09:58:06.286699
2105 09:58:06.286787 MR0 0x3b3b
2106 09:58:06.286867 MR8 0x5151
2107 09:58:06.289522 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2108 09:58:06.293391
2109 09:58:06.299630 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2110 09:58:06.302952 [FAST_K] Save calibration result to emmc
2111 09:58:06.306328 [FAST_K] Save calibration result to emmc
2112 09:58:06.309629 dram_init: config_dvfs: 1
2113 09:58:06.312823 dramc_set_vcore_voltage set vcore to 662500
2114 09:58:06.316216 Read voltage for 1200, 2
2115 09:58:06.316328 Vio18 = 0
2116 09:58:06.320017 Vcore = 662500
2117 09:58:06.320112 Vdram = 0
2118 09:58:06.320215 Vddq = 0
2119 09:58:06.320315 Vmddr = 0
2120 09:58:06.326132 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2121 09:58:06.333061 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2122 09:58:06.333166 MEM_TYPE=3, freq_sel=15
2123 09:58:06.336168 sv_algorithm_assistance_LP4_1600
2124 09:58:06.339657 ============ PULL DRAM RESETB DOWN ============
2125 09:58:06.346285 ========== PULL DRAM RESETB DOWN end =========
2126 09:58:06.349942 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2127 09:58:06.352752 ===================================
2128 09:58:06.356403 LPDDR4 DRAM CONFIGURATION
2129 09:58:06.359648 ===================================
2130 09:58:06.359744 EX_ROW_EN[0] = 0x0
2131 09:58:06.363115 EX_ROW_EN[1] = 0x0
2132 09:58:06.363204 LP4Y_EN = 0x0
2133 09:58:06.366817 WORK_FSP = 0x0
2134 09:58:06.366908 WL = 0x4
2135 09:58:06.369749 RL = 0x4
2136 09:58:06.369840 BL = 0x2
2137 09:58:06.372974 RPST = 0x0
2138 09:58:06.373063 RD_PRE = 0x0
2139 09:58:06.376331 WR_PRE = 0x1
2140 09:58:06.376419 WR_PST = 0x0
2141 09:58:06.379902 DBI_WR = 0x0
2142 09:58:06.382913 DBI_RD = 0x0
2143 09:58:06.383003 OTF = 0x1
2144 09:58:06.386238 ===================================
2145 09:58:06.389879 ===================================
2146 09:58:06.389969 ANA top config
2147 09:58:06.393081 ===================================
2148 09:58:06.396297 DLL_ASYNC_EN = 0
2149 09:58:06.399986 ALL_SLAVE_EN = 0
2150 09:58:06.403052 NEW_RANK_MODE = 1
2151 09:58:06.406332 DLL_IDLE_MODE = 1
2152 09:58:06.406475 LP45_APHY_COMB_EN = 1
2153 09:58:06.409816 TX_ODT_DIS = 1
2154 09:58:06.412846 NEW_8X_MODE = 1
2155 09:58:06.416283 ===================================
2156 09:58:06.419723 ===================================
2157 09:58:06.422933 data_rate = 2400
2158 09:58:06.426371 CKR = 1
2159 09:58:06.426503 DQ_P2S_RATIO = 8
2160 09:58:06.429723 ===================================
2161 09:58:06.433020 CA_P2S_RATIO = 8
2162 09:58:06.436344 DQ_CA_OPEN = 0
2163 09:58:06.439618 DQ_SEMI_OPEN = 0
2164 09:58:06.442795 CA_SEMI_OPEN = 0
2165 09:58:06.442885 CA_FULL_RATE = 0
2166 09:58:06.446150 DQ_CKDIV4_EN = 0
2167 09:58:06.449675 CA_CKDIV4_EN = 0
2168 09:58:06.453102 CA_PREDIV_EN = 0
2169 09:58:06.456570 PH8_DLY = 17
2170 09:58:06.460081 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2171 09:58:06.460174 DQ_AAMCK_DIV = 4
2172 09:58:06.462956 CA_AAMCK_DIV = 4
2173 09:58:06.466569 CA_ADMCK_DIV = 4
2174 09:58:06.469995 DQ_TRACK_CA_EN = 0
2175 09:58:06.473217 CA_PICK = 1200
2176 09:58:06.476442 CA_MCKIO = 1200
2177 09:58:06.479658 MCKIO_SEMI = 0
2178 09:58:06.479750 PLL_FREQ = 2366
2179 09:58:06.483170 DQ_UI_PI_RATIO = 32
2180 09:58:06.486829 CA_UI_PI_RATIO = 0
2181 09:58:06.489884 ===================================
2182 09:58:06.493363 ===================================
2183 09:58:06.496510 memory_type:LPDDR4
2184 09:58:06.496599 GP_NUM : 10
2185 09:58:06.500133 SRAM_EN : 1
2186 09:58:06.503503 MD32_EN : 0
2187 09:58:06.506568 ===================================
2188 09:58:06.506659 [ANA_INIT] >>>>>>>>>>>>>>
2189 09:58:06.510054 <<<<<< [CONFIGURE PHASE]: ANA_TX
2190 09:58:06.513391 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2191 09:58:06.517232 ===================================
2192 09:58:06.520603 data_rate = 2400,PCW = 0X5b00
2193 09:58:06.523182 ===================================
2194 09:58:06.527075 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2195 09:58:06.533353 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2196 09:58:06.536434 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2197 09:58:06.544180 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2198 09:58:06.546592 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2199 09:58:06.549795 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2200 09:58:06.549882 [ANA_INIT] flow start
2201 09:58:06.553024 [ANA_INIT] PLL >>>>>>>>
2202 09:58:06.556420 [ANA_INIT] PLL <<<<<<<<
2203 09:58:06.556508 [ANA_INIT] MIDPI >>>>>>>>
2204 09:58:06.560013 [ANA_INIT] MIDPI <<<<<<<<
2205 09:58:06.563955 [ANA_INIT] DLL >>>>>>>>
2206 09:58:06.566726 [ANA_INIT] DLL <<<<<<<<
2207 09:58:06.566817 [ANA_INIT] flow end
2208 09:58:06.570297 ============ LP4 DIFF to SE enter ============
2209 09:58:06.576655 ============ LP4 DIFF to SE exit ============
2210 09:58:06.576776 [ANA_INIT] <<<<<<<<<<<<<
2211 09:58:06.580293 [Flow] Enable top DCM control >>>>>
2212 09:58:06.583372 [Flow] Enable top DCM control <<<<<
2213 09:58:06.586557 Enable DLL master slave shuffle
2214 09:58:06.593220 ==============================================================
2215 09:58:06.593328 Gating Mode config
2216 09:58:06.600033 ==============================================================
2217 09:58:06.603377 Config description:
2218 09:58:06.610272 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2219 09:58:06.617221 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2220 09:58:06.623551 SELPH_MODE 0: By rank 1: By Phase
2221 09:58:06.626736 ==============================================================
2222 09:58:06.630282 GAT_TRACK_EN = 1
2223 09:58:06.633585 RX_GATING_MODE = 2
2224 09:58:06.637050 RX_GATING_TRACK_MODE = 2
2225 09:58:06.640331 SELPH_MODE = 1
2226 09:58:06.643460 PICG_EARLY_EN = 1
2227 09:58:06.646964 VALID_LAT_VALUE = 1
2228 09:58:06.653400 ==============================================================
2229 09:58:06.657282 Enter into Gating configuration >>>>
2230 09:58:06.659970 Exit from Gating configuration <<<<
2231 09:58:06.663346 Enter into DVFS_PRE_config >>>>>
2232 09:58:06.673308 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2233 09:58:06.676758 Exit from DVFS_PRE_config <<<<<
2234 09:58:06.679950 Enter into PICG configuration >>>>
2235 09:58:06.683315 Exit from PICG configuration <<<<
2236 09:58:06.683407 [RX_INPUT] configuration >>>>>
2237 09:58:06.686990 [RX_INPUT] configuration <<<<<
2238 09:58:06.693424 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2239 09:58:06.696949 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2240 09:58:06.703501 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2241 09:58:06.710279 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2242 09:58:06.716601 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2243 09:58:06.723374 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2244 09:58:06.727143 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2245 09:58:06.730342 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2246 09:58:06.736713 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2247 09:58:06.740122 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2248 09:58:06.743557 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2249 09:58:06.746785 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2250 09:58:06.750151 ===================================
2251 09:58:06.753592 LPDDR4 DRAM CONFIGURATION
2252 09:58:06.756951 ===================================
2253 09:58:06.760271 EX_ROW_EN[0] = 0x0
2254 09:58:06.760363 EX_ROW_EN[1] = 0x0
2255 09:58:06.763356 LP4Y_EN = 0x0
2256 09:58:06.763444 WORK_FSP = 0x0
2257 09:58:06.766725 WL = 0x4
2258 09:58:06.766812 RL = 0x4
2259 09:58:06.770179 BL = 0x2
2260 09:58:06.770267 RPST = 0x0
2261 09:58:06.773975 RD_PRE = 0x0
2262 09:58:06.774065 WR_PRE = 0x1
2263 09:58:06.776671 WR_PST = 0x0
2264 09:58:06.776760 DBI_WR = 0x0
2265 09:58:06.780288 DBI_RD = 0x0
2266 09:58:06.780376 OTF = 0x1
2267 09:58:06.783688 ===================================
2268 09:58:06.787103 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2269 09:58:06.793763 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2270 09:58:06.796998 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2271 09:58:06.800158 ===================================
2272 09:58:06.803604 LPDDR4 DRAM CONFIGURATION
2273 09:58:06.806799 ===================================
2274 09:58:06.806895 EX_ROW_EN[0] = 0x10
2275 09:58:06.810335 EX_ROW_EN[1] = 0x0
2276 09:58:06.813726 LP4Y_EN = 0x0
2277 09:58:06.813818 WORK_FSP = 0x0
2278 09:58:06.817115 WL = 0x4
2279 09:58:06.817272 RL = 0x4
2280 09:58:06.820575 BL = 0x2
2281 09:58:06.820667 RPST = 0x0
2282 09:58:06.823755 RD_PRE = 0x0
2283 09:58:06.823842 WR_PRE = 0x1
2284 09:58:06.826932 WR_PST = 0x0
2285 09:58:06.827020 DBI_WR = 0x0
2286 09:58:06.830324 DBI_RD = 0x0
2287 09:58:06.830472 OTF = 0x1
2288 09:58:06.833670 ===================================
2289 09:58:06.840925 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2290 09:58:06.841036 ==
2291 09:58:06.843655 Dram Type= 6, Freq= 0, CH_0, rank 0
2292 09:58:06.847875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2293 09:58:06.847971 ==
2294 09:58:06.850694 [Duty_Offset_Calibration]
2295 09:58:06.854333 B0:2 B1:0 CA:1
2296 09:58:06.854431
2297 09:58:06.857192 [DutyScan_Calibration_Flow] k_type=0
2298 09:58:06.864192
2299 09:58:06.864301 ==CLK 0==
2300 09:58:06.867560 Final CLK duty delay cell = -4
2301 09:58:06.871011 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2302 09:58:06.874208 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2303 09:58:06.877669 [-4] AVG Duty = 4969%(X100)
2304 09:58:06.877760
2305 09:58:06.880881 CH0 CLK Duty spec in!! Max-Min= 124%
2306 09:58:06.884087 [DutyScan_Calibration_Flow] ====Done====
2307 09:58:06.884174
2308 09:58:06.887511 [DutyScan_Calibration_Flow] k_type=1
2309 09:58:06.903119
2310 09:58:06.903255 ==DQS 0 ==
2311 09:58:06.906468 Final DQS duty delay cell = 0
2312 09:58:06.909729 [0] MAX Duty = 5187%(X100), DQS PI = 30
2313 09:58:06.913542 [0] MIN Duty = 4938%(X100), DQS PI = 0
2314 09:58:06.913635 [0] AVG Duty = 5062%(X100)
2315 09:58:06.916754
2316 09:58:06.916843 ==DQS 1 ==
2317 09:58:06.919696 Final DQS duty delay cell = -4
2318 09:58:06.923416 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2319 09:58:06.926878 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2320 09:58:06.929735 [-4] AVG Duty = 5031%(X100)
2321 09:58:06.929825
2322 09:58:06.933432 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2323 09:58:06.933519
2324 09:58:06.936799 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2325 09:58:06.939788 [DutyScan_Calibration_Flow] ====Done====
2326 09:58:06.939873
2327 09:58:06.943233 [DutyScan_Calibration_Flow] k_type=3
2328 09:58:06.960149
2329 09:58:06.960290 ==DQM 0 ==
2330 09:58:06.963480 Final DQM duty delay cell = 0
2331 09:58:06.966450 [0] MAX Duty = 5062%(X100), DQS PI = 24
2332 09:58:06.970266 [0] MIN Duty = 4844%(X100), DQS PI = 0
2333 09:58:06.970356 [0] AVG Duty = 4953%(X100)
2334 09:58:06.973257
2335 09:58:06.973341 ==DQM 1 ==
2336 09:58:06.976492 Final DQM duty delay cell = 0
2337 09:58:06.980079 [0] MAX Duty = 5187%(X100), DQS PI = 48
2338 09:58:06.983188 [0] MIN Duty = 5000%(X100), DQS PI = 22
2339 09:58:06.983277 [0] AVG Duty = 5093%(X100)
2340 09:58:06.986844
2341 09:58:06.989905 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2342 09:58:06.989989
2343 09:58:06.993300 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2344 09:58:06.996686 [DutyScan_Calibration_Flow] ====Done====
2345 09:58:06.996771
2346 09:58:06.999738 [DutyScan_Calibration_Flow] k_type=2
2347 09:58:07.016365
2348 09:58:07.016518 ==DQ 0 ==
2349 09:58:07.019640 Final DQ duty delay cell = -4
2350 09:58:07.022886 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2351 09:58:07.026310 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2352 09:58:07.029662 [-4] AVG Duty = 4984%(X100)
2353 09:58:07.029757
2354 09:58:07.029824 ==DQ 1 ==
2355 09:58:07.033063 Final DQ duty delay cell = 4
2356 09:58:07.036406 [4] MAX Duty = 5093%(X100), DQS PI = 4
2357 09:58:07.039795 [4] MIN Duty = 5031%(X100), DQS PI = 0
2358 09:58:07.039886 [4] AVG Duty = 5062%(X100)
2359 09:58:07.039953
2360 09:58:07.043267 CH0 DQ 0 Duty spec in!! Max-Min= 155%
2361 09:58:07.046340
2362 09:58:07.050503 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2363 09:58:07.053070 [DutyScan_Calibration_Flow] ====Done====
2364 09:58:07.053161 ==
2365 09:58:07.056538 Dram Type= 6, Freq= 0, CH_1, rank 0
2366 09:58:07.059952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2367 09:58:07.060040 ==
2368 09:58:07.063012 [Duty_Offset_Calibration]
2369 09:58:07.063109 B0:0 B1:-1 CA:2
2370 09:58:07.063176
2371 09:58:07.066208 [DutyScan_Calibration_Flow] k_type=0
2372 09:58:07.076374
2373 09:58:07.076498 ==CLK 0==
2374 09:58:07.080033 Final CLK duty delay cell = 0
2375 09:58:07.083212 [0] MAX Duty = 5156%(X100), DQS PI = 8
2376 09:58:07.086487 [0] MIN Duty = 4938%(X100), DQS PI = 44
2377 09:58:07.086577 [0] AVG Duty = 5047%(X100)
2378 09:58:07.086643
2379 09:58:07.089893 CH1 CLK Duty spec in!! Max-Min= 218%
2380 09:58:07.096714 [DutyScan_Calibration_Flow] ====Done====
2381 09:58:07.096819
2382 09:58:07.099908 [DutyScan_Calibration_Flow] k_type=1
2383 09:58:07.115848
2384 09:58:07.115995 ==DQS 0 ==
2385 09:58:07.119074 Final DQS duty delay cell = 0
2386 09:58:07.122604 [0] MAX Duty = 5093%(X100), DQS PI = 24
2387 09:58:07.125773 [0] MIN Duty = 4969%(X100), DQS PI = 0
2388 09:58:07.125868 [0] AVG Duty = 5031%(X100)
2389 09:58:07.129124
2390 09:58:07.129212 ==DQS 1 ==
2391 09:58:07.132627 Final DQS duty delay cell = 0
2392 09:58:07.135965 [0] MAX Duty = 5156%(X100), DQS PI = 0
2393 09:58:07.139223 [0] MIN Duty = 4844%(X100), DQS PI = 36
2394 09:58:07.139371 [0] AVG Duty = 5000%(X100)
2395 09:58:07.139486
2396 09:58:07.145656 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2397 09:58:07.145758
2398 09:58:07.149012 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2399 09:58:07.152508 [DutyScan_Calibration_Flow] ====Done====
2400 09:58:07.152601
2401 09:58:07.155823 [DutyScan_Calibration_Flow] k_type=3
2402 09:58:07.173285
2403 09:58:07.173430 ==DQM 0 ==
2404 09:58:07.176345 Final DQM duty delay cell = 4
2405 09:58:07.179738 [4] MAX Duty = 5093%(X100), DQS PI = 20
2406 09:58:07.182869 [4] MIN Duty = 4938%(X100), DQS PI = 46
2407 09:58:07.182959 [4] AVG Duty = 5015%(X100)
2408 09:58:07.186660
2409 09:58:07.186750 ==DQM 1 ==
2410 09:58:07.190150 Final DQM duty delay cell = 0
2411 09:58:07.192947 [0] MAX Duty = 5249%(X100), DQS PI = 0
2412 09:58:07.196816 [0] MIN Duty = 4875%(X100), DQS PI = 36
2413 09:58:07.196910 [0] AVG Duty = 5062%(X100)
2414 09:58:07.199572
2415 09:58:07.203016 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2416 09:58:07.203104
2417 09:58:07.206555 CH1 DQM 1 Duty spec in!! Max-Min= 374%
2418 09:58:07.210030 [DutyScan_Calibration_Flow] ====Done====
2419 09:58:07.210119
2420 09:58:07.212980 [DutyScan_Calibration_Flow] k_type=2
2421 09:58:07.229818
2422 09:58:07.229970 ==DQ 0 ==
2423 09:58:07.232843 Final DQ duty delay cell = 0
2424 09:58:07.236224 [0] MAX Duty = 5062%(X100), DQS PI = 18
2425 09:58:07.239927 [0] MIN Duty = 4938%(X100), DQS PI = 46
2426 09:58:07.240020 [0] AVG Duty = 5000%(X100)
2427 09:58:07.240085
2428 09:58:07.243300 ==DQ 1 ==
2429 09:58:07.246214 Final DQ duty delay cell = 0
2430 09:58:07.249764 [0] MAX Duty = 5031%(X100), DQS PI = 2
2431 09:58:07.253413 [0] MIN Duty = 4813%(X100), DQS PI = 36
2432 09:58:07.253504 [0] AVG Duty = 4922%(X100)
2433 09:58:07.253573
2434 09:58:07.256313 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2435 09:58:07.256398
2436 09:58:07.259936 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2437 09:58:07.266488 [DutyScan_Calibration_Flow] ====Done====
2438 09:58:07.269694 nWR fixed to 30
2439 09:58:07.269787 [ModeRegInit_LP4] CH0 RK0
2440 09:58:07.273228 [ModeRegInit_LP4] CH0 RK1
2441 09:58:07.276464 [ModeRegInit_LP4] CH1 RK0
2442 09:58:07.276553 [ModeRegInit_LP4] CH1 RK1
2443 09:58:07.279898 match AC timing 7
2444 09:58:07.282975 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2445 09:58:07.286320 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2446 09:58:07.293153 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2447 09:58:07.296569 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2448 09:58:07.303206 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2449 09:58:07.303318 ==
2450 09:58:07.306314 Dram Type= 6, Freq= 0, CH_0, rank 0
2451 09:58:07.309823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2452 09:58:07.309916 ==
2453 09:58:07.316522 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2454 09:58:07.319860 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2455 09:58:07.329532 [CA 0] Center 38 (7~69) winsize 63
2456 09:58:07.332743 [CA 1] Center 38 (7~69) winsize 63
2457 09:58:07.336096 [CA 2] Center 34 (4~65) winsize 62
2458 09:58:07.339477 [CA 3] Center 34 (4~65) winsize 62
2459 09:58:07.342781 [CA 4] Center 33 (3~64) winsize 62
2460 09:58:07.346049 [CA 5] Center 32 (2~63) winsize 62
2461 09:58:07.346145
2462 09:58:07.349611 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2463 09:58:07.349700
2464 09:58:07.352801 [CATrainingPosCal] consider 1 rank data
2465 09:58:07.356274 u2DelayCellTimex100 = 270/100 ps
2466 09:58:07.359594 CA0 delay=38 (7~69),Diff = 6 PI (28 cell)
2467 09:58:07.362818 CA1 delay=38 (7~69),Diff = 6 PI (28 cell)
2468 09:58:07.369880 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2469 09:58:07.373757 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2470 09:58:07.376304 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2471 09:58:07.379853 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2472 09:58:07.379945
2473 09:58:07.383261 CA PerBit enable=1, Macro0, CA PI delay=32
2474 09:58:07.383347
2475 09:58:07.386333 [CBTSetCACLKResult] CA Dly = 32
2476 09:58:07.386425 CS Dly: 6 (0~37)
2477 09:58:07.386492 ==
2478 09:58:07.389470 Dram Type= 6, Freq= 0, CH_0, rank 1
2479 09:58:07.396326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2480 09:58:07.396435 ==
2481 09:58:07.399796 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2482 09:58:07.406168 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2483 09:58:07.415015 [CA 0] Center 38 (7~69) winsize 63
2484 09:58:07.418323 [CA 1] Center 38 (8~69) winsize 62
2485 09:58:07.421619 [CA 2] Center 35 (5~66) winsize 62
2486 09:58:07.424829 [CA 3] Center 35 (5~66) winsize 62
2487 09:58:07.428627 [CA 4] Center 34 (3~65) winsize 63
2488 09:58:07.431387 [CA 5] Center 33 (3~63) winsize 61
2489 09:58:07.431477
2490 09:58:07.434983 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2491 09:58:07.435072
2492 09:58:07.438271 [CATrainingPosCal] consider 2 rank data
2493 09:58:07.441617 u2DelayCellTimex100 = 270/100 ps
2494 09:58:07.444758 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2495 09:58:07.451670 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2496 09:58:07.454886 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
2497 09:58:07.458008 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2498 09:58:07.461495 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2499 09:58:07.464983 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2500 09:58:07.465075
2501 09:58:07.468546 CA PerBit enable=1, Macro0, CA PI delay=33
2502 09:58:07.468633
2503 09:58:07.471751 [CBTSetCACLKResult] CA Dly = 33
2504 09:58:07.471839 CS Dly: 7 (0~39)
2505 09:58:07.471906
2506 09:58:07.474965 ----->DramcWriteLeveling(PI) begin...
2507 09:58:07.478331 ==
2508 09:58:07.481553 Dram Type= 6, Freq= 0, CH_0, rank 0
2509 09:58:07.485478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2510 09:58:07.485567 ==
2511 09:58:07.488179 Write leveling (Byte 0): 33 => 33
2512 09:58:07.491554 Write leveling (Byte 1): 31 => 31
2513 09:58:07.495169 DramcWriteLeveling(PI) end<-----
2514 09:58:07.495259
2515 09:58:07.495327 ==
2516 09:58:07.498309 Dram Type= 6, Freq= 0, CH_0, rank 0
2517 09:58:07.501650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 09:58:07.501739 ==
2519 09:58:07.505341 [Gating] SW mode calibration
2520 09:58:07.511787 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2521 09:58:07.514904 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2522 09:58:07.522203 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2523 09:58:07.524893 0 15 4 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
2524 09:58:07.528751 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2525 09:58:07.534975 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2526 09:58:07.538546 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2527 09:58:07.541937 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 09:58:07.548889 0 15 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
2529 09:58:07.552011 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
2530 09:58:07.555401 1 0 0 | B1->B0 | 2f2f 2323 | 1 0 | (0 1) (0 0)
2531 09:58:07.561844 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 09:58:07.565546 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 09:58:07.568393 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 09:58:07.575327 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 09:58:07.578254 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 09:58:07.581919 1 0 24 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
2537 09:58:07.588497 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2538 09:58:07.591711 1 1 0 | B1->B0 | 3333 4646 | 1 0 | (0 0) (0 0)
2539 09:58:07.595122 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 09:58:07.598599 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 09:58:07.605036 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 09:58:07.608677 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 09:58:07.612023 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 09:58:07.618592 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 09:58:07.621982 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2546 09:58:07.625464 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2547 09:58:07.631868 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 09:58:07.635442 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 09:58:07.638541 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 09:58:07.645215 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 09:58:07.648589 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 09:58:07.651806 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 09:58:07.658592 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 09:58:07.662134 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 09:58:07.665506 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 09:58:07.671917 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 09:58:07.675110 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 09:58:07.678577 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 09:58:07.682039 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 09:58:07.689205 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2561 09:58:07.692019 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2562 09:58:07.695288 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2563 09:58:07.698765 Total UI for P1: 0, mck2ui 16
2564 09:58:07.702234 best dqsien dly found for B0: ( 1, 3, 26)
2565 09:58:07.708656 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2566 09:58:07.708762 Total UI for P1: 0, mck2ui 16
2567 09:58:07.715539 best dqsien dly found for B1: ( 1, 4, 0)
2568 09:58:07.718958 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2569 09:58:07.721821 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2570 09:58:07.721916
2571 09:58:07.725310 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2572 09:58:07.728661 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2573 09:58:07.732091 [Gating] SW calibration Done
2574 09:58:07.732182 ==
2575 09:58:07.735171 Dram Type= 6, Freq= 0, CH_0, rank 0
2576 09:58:07.738670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2577 09:58:07.738761 ==
2578 09:58:07.742116 RX Vref Scan: 0
2579 09:58:07.742203
2580 09:58:07.742268 RX Vref 0 -> 0, step: 1
2581 09:58:07.742329
2582 09:58:07.745216 RX Delay -40 -> 252, step: 8
2583 09:58:07.748444 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
2584 09:58:07.755280 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2585 09:58:07.758638 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2586 09:58:07.761822 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2587 09:58:07.765197 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2588 09:58:07.768321 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2589 09:58:07.775154 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2590 09:58:07.778459 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2591 09:58:07.781738 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2592 09:58:07.785313 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2593 09:58:07.788364 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2594 09:58:07.795469 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
2595 09:58:07.798342 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2596 09:58:07.801789 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2597 09:58:07.804902 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2598 09:58:07.808436 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2599 09:58:07.808527 ==
2600 09:58:07.811791 Dram Type= 6, Freq= 0, CH_0, rank 0
2601 09:58:07.818556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2602 09:58:07.818698 ==
2603 09:58:07.818794 DQS Delay:
2604 09:58:07.822165 DQS0 = 0, DQS1 = 0
2605 09:58:07.822283 DQM Delay:
2606 09:58:07.825187 DQM0 = 122, DQM1 = 110
2607 09:58:07.825272 DQ Delay:
2608 09:58:07.828266 DQ0 =123, DQ1 =119, DQ2 =119, DQ3 =119
2609 09:58:07.832285 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2610 09:58:07.834874 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =111
2611 09:58:07.838645 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2612 09:58:07.838735
2613 09:58:07.838802
2614 09:58:07.838862 ==
2615 09:58:07.841920 Dram Type= 6, Freq= 0, CH_0, rank 0
2616 09:58:07.845155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2617 09:58:07.848186 ==
2618 09:58:07.848273
2619 09:58:07.848338
2620 09:58:07.848398 TX Vref Scan disable
2621 09:58:07.851968 == TX Byte 0 ==
2622 09:58:07.855146 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2623 09:58:07.858517 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2624 09:58:07.861829 == TX Byte 1 ==
2625 09:58:07.865190 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2626 09:58:07.868359 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2627 09:58:07.871756 ==
2628 09:58:07.871848 Dram Type= 6, Freq= 0, CH_0, rank 0
2629 09:58:07.878565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2630 09:58:07.878668 ==
2631 09:58:07.889601 TX Vref=22, minBit 0, minWin=24, winSum=398
2632 09:58:07.892473 TX Vref=24, minBit 7, minWin=23, winSum=404
2633 09:58:07.896168 TX Vref=26, minBit 3, minWin=24, winSum=410
2634 09:58:07.899271 TX Vref=28, minBit 2, minWin=24, winSum=411
2635 09:58:07.902634 TX Vref=30, minBit 7, minWin=24, winSum=415
2636 09:58:07.905887 TX Vref=32, minBit 1, minWin=25, winSum=412
2637 09:58:07.912503 [TxChooseVref] Worse bit 1, Min win 25, Win sum 412, Final Vref 32
2638 09:58:07.912609
2639 09:58:07.916029 Final TX Range 1 Vref 32
2640 09:58:07.916119
2641 09:58:07.916184 ==
2642 09:58:07.920235 Dram Type= 6, Freq= 0, CH_0, rank 0
2643 09:58:07.922373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2644 09:58:07.922500 ==
2645 09:58:07.922567
2646 09:58:07.925841
2647 09:58:07.925926 TX Vref Scan disable
2648 09:58:07.929549 == TX Byte 0 ==
2649 09:58:07.932463 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2650 09:58:07.935868 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2651 09:58:07.939579 == TX Byte 1 ==
2652 09:58:07.942613 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2653 09:58:07.945774 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2654 09:58:07.945861
2655 09:58:07.949156 [DATLAT]
2656 09:58:07.949241 Freq=1200, CH0 RK0
2657 09:58:07.949308
2658 09:58:07.952589 DATLAT Default: 0xd
2659 09:58:07.952672 0, 0xFFFF, sum = 0
2660 09:58:07.955742 1, 0xFFFF, sum = 0
2661 09:58:07.955828 2, 0xFFFF, sum = 0
2662 09:58:07.959494 3, 0xFFFF, sum = 0
2663 09:58:07.959582 4, 0xFFFF, sum = 0
2664 09:58:07.962812 5, 0xFFFF, sum = 0
2665 09:58:07.962900 6, 0xFFFF, sum = 0
2666 09:58:07.966103 7, 0xFFFF, sum = 0
2667 09:58:07.966224 8, 0xFFFF, sum = 0
2668 09:58:07.969366 9, 0xFFFF, sum = 0
2669 09:58:07.972784 10, 0xFFFF, sum = 0
2670 09:58:07.972874 11, 0xFFFF, sum = 0
2671 09:58:07.976359 12, 0x0, sum = 1
2672 09:58:07.976446 13, 0x0, sum = 2
2673 09:58:07.976513 14, 0x0, sum = 3
2674 09:58:07.979617 15, 0x0, sum = 4
2675 09:58:07.979702 best_step = 13
2676 09:58:07.979767
2677 09:58:07.982583 ==
2678 09:58:07.982667 Dram Type= 6, Freq= 0, CH_0, rank 0
2679 09:58:07.989347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2680 09:58:07.989446 ==
2681 09:58:07.989513 RX Vref Scan: 1
2682 09:58:07.989574
2683 09:58:07.992443 Set Vref Range= 32 -> 127
2684 09:58:07.992529
2685 09:58:07.996175 RX Vref 32 -> 127, step: 1
2686 09:58:07.996262
2687 09:58:07.999559 RX Delay -13 -> 252, step: 4
2688 09:58:07.999647
2689 09:58:08.002319 Set Vref, RX VrefLevel [Byte0]: 32
2690 09:58:08.005962 [Byte1]: 32
2691 09:58:08.006049
2692 09:58:08.009169 Set Vref, RX VrefLevel [Byte0]: 33
2693 09:58:08.012373 [Byte1]: 33
2694 09:58:08.012460
2695 09:58:08.015788 Set Vref, RX VrefLevel [Byte0]: 34
2696 09:58:08.019000 [Byte1]: 34
2697 09:58:08.023078
2698 09:58:08.023180 Set Vref, RX VrefLevel [Byte0]: 35
2699 09:58:08.026682 [Byte1]: 35
2700 09:58:08.031548
2701 09:58:08.031647 Set Vref, RX VrefLevel [Byte0]: 36
2702 09:58:08.034704 [Byte1]: 36
2703 09:58:08.039152
2704 09:58:08.039242 Set Vref, RX VrefLevel [Byte0]: 37
2705 09:58:08.042367 [Byte1]: 37
2706 09:58:08.047040
2707 09:58:08.047134 Set Vref, RX VrefLevel [Byte0]: 38
2708 09:58:08.050518 [Byte1]: 38
2709 09:58:08.055251
2710 09:58:08.055342 Set Vref, RX VrefLevel [Byte0]: 39
2711 09:58:08.058209 [Byte1]: 39
2712 09:58:08.062716
2713 09:58:08.062807 Set Vref, RX VrefLevel [Byte0]: 40
2714 09:58:08.066583 [Byte1]: 40
2715 09:58:08.070607
2716 09:58:08.070697 Set Vref, RX VrefLevel [Byte0]: 41
2717 09:58:08.073885 [Byte1]: 41
2718 09:58:08.078604
2719 09:58:08.078696 Set Vref, RX VrefLevel [Byte0]: 42
2720 09:58:08.082053 [Byte1]: 42
2721 09:58:08.086336
2722 09:58:08.086435 Set Vref, RX VrefLevel [Byte0]: 43
2723 09:58:08.089551 [Byte1]: 43
2724 09:58:08.094117
2725 09:58:08.094211 Set Vref, RX VrefLevel [Byte0]: 44
2726 09:58:08.097536 [Byte1]: 44
2727 09:58:08.102102
2728 09:58:08.102198 Set Vref, RX VrefLevel [Byte0]: 45
2729 09:58:08.105903 [Byte1]: 45
2730 09:58:08.109985
2731 09:58:08.110077 Set Vref, RX VrefLevel [Byte0]: 46
2732 09:58:08.113609 [Byte1]: 46
2733 09:58:08.118041
2734 09:58:08.118140 Set Vref, RX VrefLevel [Byte0]: 47
2735 09:58:08.121296 [Byte1]: 47
2736 09:58:08.125908
2737 09:58:08.126003 Set Vref, RX VrefLevel [Byte0]: 48
2738 09:58:08.129044 [Byte1]: 48
2739 09:58:08.133680
2740 09:58:08.133775 Set Vref, RX VrefLevel [Byte0]: 49
2741 09:58:08.137133 [Byte1]: 49
2742 09:58:08.141647
2743 09:58:08.141741 Set Vref, RX VrefLevel [Byte0]: 50
2744 09:58:08.144941 [Byte1]: 50
2745 09:58:08.149373
2746 09:58:08.149465 Set Vref, RX VrefLevel [Byte0]: 51
2747 09:58:08.152645 [Byte1]: 51
2748 09:58:08.157414
2749 09:58:08.157505 Set Vref, RX VrefLevel [Byte0]: 52
2750 09:58:08.160511 [Byte1]: 52
2751 09:58:08.165290
2752 09:58:08.165387 Set Vref, RX VrefLevel [Byte0]: 53
2753 09:58:08.168814 [Byte1]: 53
2754 09:58:08.173132
2755 09:58:08.173255 Set Vref, RX VrefLevel [Byte0]: 54
2756 09:58:08.176359 [Byte1]: 54
2757 09:58:08.181148
2758 09:58:08.181263 Set Vref, RX VrefLevel [Byte0]: 55
2759 09:58:08.184432 [Byte1]: 55
2760 09:58:08.188908
2761 09:58:08.189032 Set Vref, RX VrefLevel [Byte0]: 56
2762 09:58:08.192281 [Byte1]: 56
2763 09:58:08.196736
2764 09:58:08.196830 Set Vref, RX VrefLevel [Byte0]: 57
2765 09:58:08.200694 [Byte1]: 57
2766 09:58:08.204557
2767 09:58:08.204649 Set Vref, RX VrefLevel [Byte0]: 58
2768 09:58:08.207850 [Byte1]: 58
2769 09:58:08.212635
2770 09:58:08.212730 Set Vref, RX VrefLevel [Byte0]: 59
2771 09:58:08.215890 [Byte1]: 59
2772 09:58:08.220636
2773 09:58:08.220764 Set Vref, RX VrefLevel [Byte0]: 60
2774 09:58:08.223844 [Byte1]: 60
2775 09:58:08.228617
2776 09:58:08.228716 Set Vref, RX VrefLevel [Byte0]: 61
2777 09:58:08.231751 [Byte1]: 61
2778 09:58:08.236369
2779 09:58:08.236473 Set Vref, RX VrefLevel [Byte0]: 62
2780 09:58:08.239715 [Byte1]: 62
2781 09:58:08.244480
2782 09:58:08.244579 Set Vref, RX VrefLevel [Byte0]: 63
2783 09:58:08.247366 [Byte1]: 63
2784 09:58:08.251994
2785 09:58:08.252084 Set Vref, RX VrefLevel [Byte0]: 64
2786 09:58:08.255546 [Byte1]: 64
2787 09:58:08.259876
2788 09:58:08.259972 Set Vref, RX VrefLevel [Byte0]: 65
2789 09:58:08.263119 [Byte1]: 65
2790 09:58:08.267903
2791 09:58:08.267998 Set Vref, RX VrefLevel [Byte0]: 66
2792 09:58:08.271098 [Byte1]: 66
2793 09:58:08.275660
2794 09:58:08.275759 Set Vref, RX VrefLevel [Byte0]: 67
2795 09:58:08.279230 [Byte1]: 67
2796 09:58:08.283599
2797 09:58:08.283695 Set Vref, RX VrefLevel [Byte0]: 68
2798 09:58:08.286792 [Byte1]: 68
2799 09:58:08.292091
2800 09:58:08.292187 Set Vref, RX VrefLevel [Byte0]: 69
2801 09:58:08.294993 [Byte1]: 69
2802 09:58:08.299400
2803 09:58:08.299493 Final RX Vref Byte 0 = 58 to rank0
2804 09:58:08.303108 Final RX Vref Byte 1 = 49 to rank0
2805 09:58:08.306058 Final RX Vref Byte 0 = 58 to rank1
2806 09:58:08.309634 Final RX Vref Byte 1 = 49 to rank1==
2807 09:58:08.312688 Dram Type= 6, Freq= 0, CH_0, rank 0
2808 09:58:08.316201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2809 09:58:08.319370 ==
2810 09:58:08.319483 DQS Delay:
2811 09:58:08.319549 DQS0 = 0, DQS1 = 0
2812 09:58:08.322970 DQM Delay:
2813 09:58:08.323063 DQM0 = 122, DQM1 = 109
2814 09:58:08.326184 DQ Delay:
2815 09:58:08.329519 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2816 09:58:08.332750 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2817 09:58:08.336356 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =106
2818 09:58:08.339544 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2819 09:58:08.339639
2820 09:58:08.339707
2821 09:58:08.346286 [DQSOSCAuto] RK0, (LSB)MR18= 0xa07, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 406 ps
2822 09:58:08.349938 CH0 RK0: MR19=404, MR18=A07
2823 09:58:08.356333 CH0_RK0: MR19=0x404, MR18=0xA07, DQSOSC=406, MR23=63, INC=39, DEC=26
2824 09:58:08.356442
2825 09:58:08.359548 ----->DramcWriteLeveling(PI) begin...
2826 09:58:08.359639 ==
2827 09:58:08.362912 Dram Type= 6, Freq= 0, CH_0, rank 1
2828 09:58:08.366066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2829 09:58:08.366156 ==
2830 09:58:08.369867 Write leveling (Byte 0): 36 => 36
2831 09:58:08.373007 Write leveling (Byte 1): 31 => 31
2832 09:58:08.376106 DramcWriteLeveling(PI) end<-----
2833 09:58:08.376197
2834 09:58:08.376263 ==
2835 09:58:08.379514 Dram Type= 6, Freq= 0, CH_0, rank 1
2836 09:58:08.382993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2837 09:58:08.386259 ==
2838 09:58:08.386359 [Gating] SW mode calibration
2839 09:58:08.393037 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2840 09:58:08.399581 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2841 09:58:08.403060 0 15 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
2842 09:58:08.409595 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2843 09:58:08.413148 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2844 09:58:08.416769 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2845 09:58:08.423107 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2846 09:58:08.426428 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2847 09:58:08.430242 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2848 09:58:08.436293 0 15 28 | B1->B0 | 3333 2e2e | 1 1 | (1 1) (1 0)
2849 09:58:08.439890 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2850 09:58:08.442905 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 09:58:08.446174 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2852 09:58:08.452858 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2853 09:58:08.456332 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2854 09:58:08.459546 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2855 09:58:08.466344 1 0 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2856 09:58:08.469897 1 0 28 | B1->B0 | 3939 4444 | 1 1 | (0 0) (0 0)
2857 09:58:08.472950 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 09:58:08.479612 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 09:58:08.483002 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 09:58:08.486342 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2861 09:58:08.492951 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2862 09:58:08.496860 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2863 09:58:08.499849 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2864 09:58:08.506253 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2865 09:58:08.510222 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2866 09:58:08.513739 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 09:58:08.519886 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 09:58:08.523131 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 09:58:08.526907 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 09:58:08.529829 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 09:58:08.536668 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 09:58:08.540462 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 09:58:08.542998 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 09:58:08.549634 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 09:58:08.553052 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 09:58:08.556553 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 09:58:08.563324 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 09:58:08.566451 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 09:58:08.570132 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 09:58:08.576566 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2881 09:58:08.580361 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 09:58:08.583594 Total UI for P1: 0, mck2ui 16
2883 09:58:08.586601 best dqsien dly found for B0: ( 1, 3, 28)
2884 09:58:08.589760 Total UI for P1: 0, mck2ui 16
2885 09:58:08.593194 best dqsien dly found for B1: ( 1, 3, 30)
2886 09:58:08.596509 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2887 09:58:08.600412 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2888 09:58:08.600528
2889 09:58:08.603179 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2890 09:58:08.606722 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2891 09:58:08.610043 [Gating] SW calibration Done
2892 09:58:08.610144 ==
2893 09:58:08.613185 Dram Type= 6, Freq= 0, CH_0, rank 1
2894 09:58:08.616788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2895 09:58:08.616906 ==
2896 09:58:08.620116 RX Vref Scan: 0
2897 09:58:08.620220
2898 09:58:08.623125 RX Vref 0 -> 0, step: 1
2899 09:58:08.623228
2900 09:58:08.623294 RX Delay -40 -> 252, step: 8
2901 09:58:08.629775 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2902 09:58:08.633526 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2903 09:58:08.636636 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2904 09:58:08.639867 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2905 09:58:08.643141 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2906 09:58:08.650238 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2907 09:58:08.652972 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2908 09:58:08.656476 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2909 09:58:08.659990 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2910 09:58:08.663132 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2911 09:58:08.670027 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2912 09:58:08.673125 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2913 09:58:08.676667 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2914 09:58:08.679757 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2915 09:58:08.683099 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2916 09:58:08.689927 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2917 09:58:08.690035 ==
2918 09:58:08.693628 Dram Type= 6, Freq= 0, CH_0, rank 1
2919 09:58:08.696327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2920 09:58:08.696416 ==
2921 09:58:08.696481 DQS Delay:
2922 09:58:08.699746 DQS0 = 0, DQS1 = 0
2923 09:58:08.699832 DQM Delay:
2924 09:58:08.703186 DQM0 = 120, DQM1 = 108
2925 09:58:08.703272 DQ Delay:
2926 09:58:08.706719 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2927 09:58:08.709949 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2928 09:58:08.713551 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2929 09:58:08.716525 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2930 09:58:08.716614
2931 09:58:08.716680
2932 09:58:08.720300 ==
2933 09:58:08.720418 Dram Type= 6, Freq= 0, CH_0, rank 1
2934 09:58:08.726576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2935 09:58:08.726688 ==
2936 09:58:08.726754
2937 09:58:08.726815
2938 09:58:08.729749 TX Vref Scan disable
2939 09:58:08.729835 == TX Byte 0 ==
2940 09:58:08.733409 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2941 09:58:08.739933 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2942 09:58:08.740041 == TX Byte 1 ==
2943 09:58:08.743137 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2944 09:58:08.749944 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2945 09:58:08.750086 ==
2946 09:58:08.753227 Dram Type= 6, Freq= 0, CH_0, rank 1
2947 09:58:08.756380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2948 09:58:08.756488 ==
2949 09:58:08.768567 TX Vref=22, minBit 4, minWin=24, winSum=413
2950 09:58:08.772266 TX Vref=24, minBit 0, minWin=25, winSum=414
2951 09:58:08.775498 TX Vref=26, minBit 3, minWin=25, winSum=420
2952 09:58:08.778642 TX Vref=28, minBit 2, minWin=25, winSum=425
2953 09:58:08.782199 TX Vref=30, minBit 4, minWin=25, winSum=424
2954 09:58:08.785118 TX Vref=32, minBit 2, minWin=26, winSum=425
2955 09:58:08.792522 [TxChooseVref] Worse bit 2, Min win 26, Win sum 425, Final Vref 32
2956 09:58:08.792661
2957 09:58:08.795614 Final TX Range 1 Vref 32
2958 09:58:08.795704
2959 09:58:08.795771 ==
2960 09:58:08.798818 Dram Type= 6, Freq= 0, CH_0, rank 1
2961 09:58:08.801966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2962 09:58:08.802064 ==
2963 09:58:08.802131
2964 09:58:08.802193
2965 09:58:08.805307 TX Vref Scan disable
2966 09:58:08.808852 == TX Byte 0 ==
2967 09:58:08.811930 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2968 09:58:08.815663 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2969 09:58:08.818516 == TX Byte 1 ==
2970 09:58:08.821807 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2971 09:58:08.825237 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2972 09:58:08.825348
2973 09:58:08.828481 [DATLAT]
2974 09:58:08.828577 Freq=1200, CH0 RK1
2975 09:58:08.828646
2976 09:58:08.831863 DATLAT Default: 0xd
2977 09:58:08.831957 0, 0xFFFF, sum = 0
2978 09:58:08.835297 1, 0xFFFF, sum = 0
2979 09:58:08.835394 2, 0xFFFF, sum = 0
2980 09:58:08.838539 3, 0xFFFF, sum = 0
2981 09:58:08.838638 4, 0xFFFF, sum = 0
2982 09:58:08.842152 5, 0xFFFF, sum = 0
2983 09:58:08.842247 6, 0xFFFF, sum = 0
2984 09:58:08.845403 7, 0xFFFF, sum = 0
2985 09:58:08.848774 8, 0xFFFF, sum = 0
2986 09:58:08.848866 9, 0xFFFF, sum = 0
2987 09:58:08.851845 10, 0xFFFF, sum = 0
2988 09:58:08.851939 11, 0xFFFF, sum = 0
2989 09:58:08.855154 12, 0x0, sum = 1
2990 09:58:08.855244 13, 0x0, sum = 2
2991 09:58:08.855312 14, 0x0, sum = 3
2992 09:58:08.858604 15, 0x0, sum = 4
2993 09:58:08.858694 best_step = 13
2994 09:58:08.858759
2995 09:58:08.862097 ==
2996 09:58:08.862184 Dram Type= 6, Freq= 0, CH_0, rank 1
2997 09:58:08.868540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2998 09:58:08.868648 ==
2999 09:58:08.868715 RX Vref Scan: 0
3000 09:58:08.868777
3001 09:58:08.872276 RX Vref 0 -> 0, step: 1
3002 09:58:08.872362
3003 09:58:08.875495 RX Delay -21 -> 252, step: 4
3004 09:58:08.878964 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3005 09:58:08.882119 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3006 09:58:08.888806 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3007 09:58:08.891967 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3008 09:58:08.895416 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3009 09:58:08.899106 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3010 09:58:08.902106 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3011 09:58:08.908915 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3012 09:58:08.912280 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3013 09:58:08.915904 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3014 09:58:08.918911 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3015 09:58:08.922176 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3016 09:58:08.928901 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3017 09:58:08.932406 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3018 09:58:08.935558 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3019 09:58:08.939155 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3020 09:58:08.939248 ==
3021 09:58:08.942365 Dram Type= 6, Freq= 0, CH_0, rank 1
3022 09:58:08.945542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3023 09:58:08.948812 ==
3024 09:58:08.948902 DQS Delay:
3025 09:58:08.948970 DQS0 = 0, DQS1 = 0
3026 09:58:08.952285 DQM Delay:
3027 09:58:08.952372 DQM0 = 119, DQM1 = 108
3028 09:58:08.955570 DQ Delay:
3029 09:58:08.958799 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =112
3030 09:58:08.962636 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3031 09:58:08.965857 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3032 09:58:08.969074 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3033 09:58:08.969167
3034 09:58:08.969233
3035 09:58:08.975835 [DQSOSCAuto] RK1, (LSB)MR18= 0xdf5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 405 ps
3036 09:58:08.979025 CH0 RK1: MR19=403, MR18=DF5
3037 09:58:08.986008 CH0_RK1: MR19=0x403, MR18=0xDF5, DQSOSC=405, MR23=63, INC=39, DEC=26
3038 09:58:08.989251 [RxdqsGatingPostProcess] freq 1200
3039 09:58:08.992308 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3040 09:58:08.995662 best DQS0 dly(2T, 0.5T) = (0, 11)
3041 09:58:08.999169 best DQS1 dly(2T, 0.5T) = (0, 12)
3042 09:58:09.002425 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3043 09:58:09.005840 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3044 09:58:09.009446 best DQS0 dly(2T, 0.5T) = (0, 11)
3045 09:58:09.012500 best DQS1 dly(2T, 0.5T) = (0, 11)
3046 09:58:09.015612 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3047 09:58:09.019569 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3048 09:58:09.022690 Pre-setting of DQS Precalculation
3049 09:58:09.026142 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3050 09:58:09.026238 ==
3051 09:58:09.029321 Dram Type= 6, Freq= 0, CH_1, rank 0
3052 09:58:09.035742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3053 09:58:09.035854 ==
3054 09:58:09.039412 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3055 09:58:09.046316 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3056 09:58:09.055173 [CA 0] Center 37 (7~67) winsize 61
3057 09:58:09.057711 [CA 1] Center 37 (7~68) winsize 62
3058 09:58:09.061757 [CA 2] Center 35 (5~65) winsize 61
3059 09:58:09.064389 [CA 3] Center 33 (3~64) winsize 62
3060 09:58:09.067732 [CA 4] Center 33 (3~64) winsize 62
3061 09:58:09.071130 [CA 5] Center 33 (3~63) winsize 61
3062 09:58:09.071224
3063 09:58:09.075160 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3064 09:58:09.075251
3065 09:58:09.078277 [CATrainingPosCal] consider 1 rank data
3066 09:58:09.081333 u2DelayCellTimex100 = 270/100 ps
3067 09:58:09.084797 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3068 09:58:09.088077 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3069 09:58:09.094500 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3070 09:58:09.097903 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3071 09:58:09.101185 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3072 09:58:09.104600 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3073 09:58:09.104694
3074 09:58:09.107799 CA PerBit enable=1, Macro0, CA PI delay=33
3075 09:58:09.107885
3076 09:58:09.111132 [CBTSetCACLKResult] CA Dly = 33
3077 09:58:09.111217 CS Dly: 5 (0~36)
3078 09:58:09.111283 ==
3079 09:58:09.115045 Dram Type= 6, Freq= 0, CH_1, rank 1
3080 09:58:09.121498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3081 09:58:09.121621 ==
3082 09:58:09.124905 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3083 09:58:09.131215 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3084 09:58:09.140076 [CA 0] Center 38 (8~68) winsize 61
3085 09:58:09.143576 [CA 1] Center 37 (7~68) winsize 62
3086 09:58:09.147720 [CA 2] Center 35 (5~66) winsize 62
3087 09:58:09.150729 [CA 3] Center 34 (4~65) winsize 62
3088 09:58:09.153572 [CA 4] Center 34 (4~64) winsize 61
3089 09:58:09.156768 [CA 5] Center 33 (3~64) winsize 62
3090 09:58:09.156859
3091 09:58:09.160064 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3092 09:58:09.160150
3093 09:58:09.163647 [CATrainingPosCal] consider 2 rank data
3094 09:58:09.166861 u2DelayCellTimex100 = 270/100 ps
3095 09:58:09.170207 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3096 09:58:09.173729 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3097 09:58:09.177123 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3098 09:58:09.183850 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3099 09:58:09.187019 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3100 09:58:09.190130 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3101 09:58:09.190224
3102 09:58:09.193581 CA PerBit enable=1, Macro0, CA PI delay=33
3103 09:58:09.193673
3104 09:58:09.196857 [CBTSetCACLKResult] CA Dly = 33
3105 09:58:09.196952 CS Dly: 6 (0~38)
3106 09:58:09.197039
3107 09:58:09.200752 ----->DramcWriteLeveling(PI) begin...
3108 09:58:09.200847 ==
3109 09:58:09.203519 Dram Type= 6, Freq= 0, CH_1, rank 0
3110 09:58:09.210346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3111 09:58:09.210497 ==
3112 09:58:09.213503 Write leveling (Byte 0): 25 => 25
3113 09:58:09.217323 Write leveling (Byte 1): 27 => 27
3114 09:58:09.217445 DramcWriteLeveling(PI) end<-----
3115 09:58:09.217540
3116 09:58:09.220176 ==
3117 09:58:09.223790 Dram Type= 6, Freq= 0, CH_1, rank 0
3118 09:58:09.226882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3119 09:58:09.226979 ==
3120 09:58:09.230424 [Gating] SW mode calibration
3121 09:58:09.237005 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3122 09:58:09.240707 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3123 09:58:09.247067 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3124 09:58:09.250291 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3125 09:58:09.253963 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3126 09:58:09.261036 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3127 09:58:09.263690 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3128 09:58:09.266961 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3129 09:58:09.273938 0 15 24 | B1->B0 | 2c2c 2525 | 0 0 | (0 1) (0 1)
3130 09:58:09.277484 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3131 09:58:09.280648 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 09:58:09.284160 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 09:58:09.290715 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 09:58:09.294072 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3135 09:58:09.297238 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3136 09:58:09.304041 1 0 20 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
3137 09:58:09.307271 1 0 24 | B1->B0 | 4141 4444 | 0 0 | (0 0) (0 0)
3138 09:58:09.310824 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 09:58:09.317320 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 09:58:09.320361 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 09:58:09.323800 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 09:58:09.330513 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 09:58:09.333866 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3144 09:58:09.337596 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 09:58:09.344051 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3146 09:58:09.346829 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3147 09:58:09.350122 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 09:58:09.357307 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 09:58:09.360247 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 09:58:09.363367 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 09:58:09.370230 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 09:58:09.373701 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 09:58:09.377292 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 09:58:09.383516 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 09:58:09.386840 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 09:58:09.390644 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 09:58:09.396775 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 09:58:09.400161 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 09:58:09.403470 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 09:58:09.406732 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 09:58:09.413396 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3162 09:58:09.416899 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3163 09:58:09.420300 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 09:58:09.423401 Total UI for P1: 0, mck2ui 16
3165 09:58:09.426895 best dqsien dly found for B0: ( 1, 3, 26)
3166 09:58:09.429986 Total UI for P1: 0, mck2ui 16
3167 09:58:09.433326 best dqsien dly found for B1: ( 1, 3, 26)
3168 09:58:09.436939 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3169 09:58:09.440623 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3170 09:58:09.443596
3171 09:58:09.446816 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3172 09:58:09.450578 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3173 09:58:09.453532 [Gating] SW calibration Done
3174 09:58:09.453623 ==
3175 09:58:09.456891 Dram Type= 6, Freq= 0, CH_1, rank 0
3176 09:58:09.459965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3177 09:58:09.460055 ==
3178 09:58:09.460122 RX Vref Scan: 0
3179 09:58:09.460182
3180 09:58:09.463431 RX Vref 0 -> 0, step: 1
3181 09:58:09.463517
3182 09:58:09.466703 RX Delay -40 -> 252, step: 8
3183 09:58:09.470001 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3184 09:58:09.473461 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3185 09:58:09.480528 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3186 09:58:09.483782 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3187 09:58:09.487080 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3188 09:58:09.490265 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3189 09:58:09.493826 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3190 09:58:09.497302 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3191 09:58:09.503826 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3192 09:58:09.507041 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3193 09:58:09.510333 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3194 09:58:09.513918 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3195 09:58:09.517430 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3196 09:58:09.523955 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3197 09:58:09.527271 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3198 09:58:09.530428 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3199 09:58:09.530524 ==
3200 09:58:09.533906 Dram Type= 6, Freq= 0, CH_1, rank 0
3201 09:58:09.537196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3202 09:58:09.537288 ==
3203 09:58:09.540967 DQS Delay:
3204 09:58:09.541056 DQS0 = 0, DQS1 = 0
3205 09:58:09.543922 DQM Delay:
3206 09:58:09.544011 DQM0 = 120, DQM1 = 112
3207 09:58:09.544078 DQ Delay:
3208 09:58:09.547104 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3209 09:58:09.550676 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =123
3210 09:58:09.557415 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3211 09:58:09.560537 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3212 09:58:09.560638
3213 09:58:09.560706
3214 09:58:09.560767 ==
3215 09:58:09.564122 Dram Type= 6, Freq= 0, CH_1, rank 0
3216 09:58:09.567530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3217 09:58:09.567625 ==
3218 09:58:09.567692
3219 09:58:09.567755
3220 09:58:09.570674 TX Vref Scan disable
3221 09:58:09.570760 == TX Byte 0 ==
3222 09:58:09.577442 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3223 09:58:09.581225 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3224 09:58:09.581327 == TX Byte 1 ==
3225 09:58:09.587321 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3226 09:58:09.590823 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3227 09:58:09.590922 ==
3228 09:58:09.594011 Dram Type= 6, Freq= 0, CH_1, rank 0
3229 09:58:09.597290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3230 09:58:09.597387 ==
3231 09:58:09.610311 TX Vref=22, minBit 11, minWin=23, winSum=395
3232 09:58:09.613336 TX Vref=24, minBit 10, minWin=24, winSum=404
3233 09:58:09.616665 TX Vref=26, minBit 11, minWin=24, winSum=407
3234 09:58:09.620126 TX Vref=28, minBit 3, minWin=25, winSum=416
3235 09:58:09.623195 TX Vref=30, minBit 8, minWin=25, winSum=418
3236 09:58:09.629778 TX Vref=32, minBit 9, minWin=24, winSum=414
3237 09:58:09.633325 [TxChooseVref] Worse bit 8, Min win 25, Win sum 418, Final Vref 30
3238 09:58:09.633431
3239 09:58:09.637109 Final TX Range 1 Vref 30
3240 09:58:09.637202
3241 09:58:09.637269 ==
3242 09:58:09.640265 Dram Type= 6, Freq= 0, CH_1, rank 0
3243 09:58:09.643463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3244 09:58:09.643552 ==
3245 09:58:09.643618
3246 09:58:09.647255
3247 09:58:09.647341 TX Vref Scan disable
3248 09:58:09.650366 == TX Byte 0 ==
3249 09:58:09.653509 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3250 09:58:09.657066 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3251 09:58:09.660061 == TX Byte 1 ==
3252 09:58:09.663265 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3253 09:58:09.666739 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3254 09:58:09.666834
3255 09:58:09.670185 [DATLAT]
3256 09:58:09.670272 Freq=1200, CH1 RK0
3257 09:58:09.670339
3258 09:58:09.673558 DATLAT Default: 0xd
3259 09:58:09.673645 0, 0xFFFF, sum = 0
3260 09:58:09.676752 1, 0xFFFF, sum = 0
3261 09:58:09.676841 2, 0xFFFF, sum = 0
3262 09:58:09.680293 3, 0xFFFF, sum = 0
3263 09:58:09.680382 4, 0xFFFF, sum = 0
3264 09:58:09.683518 5, 0xFFFF, sum = 0
3265 09:58:09.683607 6, 0xFFFF, sum = 0
3266 09:58:09.687041 7, 0xFFFF, sum = 0
3267 09:58:09.687128 8, 0xFFFF, sum = 0
3268 09:58:09.690325 9, 0xFFFF, sum = 0
3269 09:58:09.693647 10, 0xFFFF, sum = 0
3270 09:58:09.693740 11, 0xFFFF, sum = 0
3271 09:58:09.697065 12, 0x0, sum = 1
3272 09:58:09.697154 13, 0x0, sum = 2
3273 09:58:09.697222 14, 0x0, sum = 3
3274 09:58:09.700086 15, 0x0, sum = 4
3275 09:58:09.700174 best_step = 13
3276 09:58:09.700239
3277 09:58:09.703574 ==
3278 09:58:09.703660 Dram Type= 6, Freq= 0, CH_1, rank 0
3279 09:58:09.710134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3280 09:58:09.710241 ==
3281 09:58:09.710309 RX Vref Scan: 1
3282 09:58:09.710371
3283 09:58:09.714358 Set Vref Range= 32 -> 127
3284 09:58:09.714494
3285 09:58:09.717150 RX Vref 32 -> 127, step: 1
3286 09:58:09.717238
3287 09:58:09.720849 RX Delay -13 -> 252, step: 4
3288 09:58:09.720950
3289 09:58:09.723580 Set Vref, RX VrefLevel [Byte0]: 32
3290 09:58:09.723676 [Byte1]: 32
3291 09:58:09.728452
3292 09:58:09.728547 Set Vref, RX VrefLevel [Byte0]: 33
3293 09:58:09.731555 [Byte1]: 33
3294 09:58:09.736650
3295 09:58:09.736766 Set Vref, RX VrefLevel [Byte0]: 34
3296 09:58:09.739451 [Byte1]: 34
3297 09:58:09.744148
3298 09:58:09.744252 Set Vref, RX VrefLevel [Byte0]: 35
3299 09:58:09.747598 [Byte1]: 35
3300 09:58:09.751833
3301 09:58:09.751927 Set Vref, RX VrefLevel [Byte0]: 36
3302 09:58:09.755778 [Byte1]: 36
3303 09:58:09.759976
3304 09:58:09.760075 Set Vref, RX VrefLevel [Byte0]: 37
3305 09:58:09.763229 [Byte1]: 37
3306 09:58:09.768059
3307 09:58:09.768170 Set Vref, RX VrefLevel [Byte0]: 38
3308 09:58:09.771092 [Byte1]: 38
3309 09:58:09.775695
3310 09:58:09.775816 Set Vref, RX VrefLevel [Byte0]: 39
3311 09:58:09.779067 [Byte1]: 39
3312 09:58:09.783532
3313 09:58:09.783629 Set Vref, RX VrefLevel [Byte0]: 40
3314 09:58:09.786994 [Byte1]: 40
3315 09:58:09.791500
3316 09:58:09.791598 Set Vref, RX VrefLevel [Byte0]: 41
3317 09:58:09.795559 [Byte1]: 41
3318 09:58:09.799588
3319 09:58:09.799682 Set Vref, RX VrefLevel [Byte0]: 42
3320 09:58:09.802964 [Byte1]: 42
3321 09:58:09.807261
3322 09:58:09.807354 Set Vref, RX VrefLevel [Byte0]: 43
3323 09:58:09.810554 [Byte1]: 43
3324 09:58:09.814930
3325 09:58:09.815024 Set Vref, RX VrefLevel [Byte0]: 44
3326 09:58:09.818298 [Byte1]: 44
3327 09:58:09.822938
3328 09:58:09.823050 Set Vref, RX VrefLevel [Byte0]: 45
3329 09:58:09.826340 [Byte1]: 45
3330 09:58:09.830860
3331 09:58:09.830962 Set Vref, RX VrefLevel [Byte0]: 46
3332 09:58:09.834505 [Byte1]: 46
3333 09:58:09.838998
3334 09:58:09.839137 Set Vref, RX VrefLevel [Byte0]: 47
3335 09:58:09.842141 [Byte1]: 47
3336 09:58:09.847344
3337 09:58:09.847447 Set Vref, RX VrefLevel [Byte0]: 48
3338 09:58:09.849986 [Byte1]: 48
3339 09:58:09.854709
3340 09:58:09.854803 Set Vref, RX VrefLevel [Byte0]: 49
3341 09:58:09.857777 [Byte1]: 49
3342 09:58:09.862587
3343 09:58:09.862684 Set Vref, RX VrefLevel [Byte0]: 50
3344 09:58:09.865654 [Byte1]: 50
3345 09:58:09.870289
3346 09:58:09.870412 Set Vref, RX VrefLevel [Byte0]: 51
3347 09:58:09.873676 [Byte1]: 51
3348 09:58:09.878213
3349 09:58:09.878306 Set Vref, RX VrefLevel [Byte0]: 52
3350 09:58:09.881701 [Byte1]: 52
3351 09:58:09.886016
3352 09:58:09.886113 Set Vref, RX VrefLevel [Byte0]: 53
3353 09:58:09.889607 [Byte1]: 53
3354 09:58:09.894597
3355 09:58:09.894698 Set Vref, RX VrefLevel [Byte0]: 54
3356 09:58:09.897229 [Byte1]: 54
3357 09:58:09.901870
3358 09:58:09.901969 Set Vref, RX VrefLevel [Byte0]: 55
3359 09:58:09.905096 [Byte1]: 55
3360 09:58:09.909716
3361 09:58:09.909810 Set Vref, RX VrefLevel [Byte0]: 56
3362 09:58:09.913038 [Byte1]: 56
3363 09:58:09.917971
3364 09:58:09.918074 Set Vref, RX VrefLevel [Byte0]: 57
3365 09:58:09.920790 [Byte1]: 57
3366 09:58:09.925400
3367 09:58:09.925513 Set Vref, RX VrefLevel [Byte0]: 58
3368 09:58:09.928912 [Byte1]: 58
3369 09:58:09.933358
3370 09:58:09.933463 Set Vref, RX VrefLevel [Byte0]: 59
3371 09:58:09.936701 [Byte1]: 59
3372 09:58:09.941323
3373 09:58:09.941426 Set Vref, RX VrefLevel [Byte0]: 60
3374 09:58:09.944586 [Byte1]: 60
3375 09:58:09.949458
3376 09:58:09.949561 Set Vref, RX VrefLevel [Byte0]: 61
3377 09:58:09.952422 [Byte1]: 61
3378 09:58:09.957032
3379 09:58:09.957132 Set Vref, RX VrefLevel [Byte0]: 62
3380 09:58:09.960418 [Byte1]: 62
3381 09:58:09.964962
3382 09:58:09.965061 Set Vref, RX VrefLevel [Byte0]: 63
3383 09:58:09.971649 [Byte1]: 63
3384 09:58:09.971758
3385 09:58:09.974763 Set Vref, RX VrefLevel [Byte0]: 64
3386 09:58:09.978174 [Byte1]: 64
3387 09:58:09.978266
3388 09:58:09.981945 Set Vref, RX VrefLevel [Byte0]: 65
3389 09:58:09.984755 [Byte1]: 65
3390 09:58:09.988510
3391 09:58:09.988604 Set Vref, RX VrefLevel [Byte0]: 66
3392 09:58:09.991927 [Byte1]: 66
3393 09:58:09.996758
3394 09:58:09.996861 Set Vref, RX VrefLevel [Byte0]: 67
3395 09:58:09.999660 [Byte1]: 67
3396 09:58:10.004422
3397 09:58:10.004520 Final RX Vref Byte 0 = 51 to rank0
3398 09:58:10.007743 Final RX Vref Byte 1 = 50 to rank0
3399 09:58:10.010969 Final RX Vref Byte 0 = 51 to rank1
3400 09:58:10.014498 Final RX Vref Byte 1 = 50 to rank1==
3401 09:58:10.017668 Dram Type= 6, Freq= 0, CH_1, rank 0
3402 09:58:10.024798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3403 09:58:10.024936 ==
3404 09:58:10.025003 DQS Delay:
3405 09:58:10.025065 DQS0 = 0, DQS1 = 0
3406 09:58:10.027903 DQM Delay:
3407 09:58:10.027991 DQM0 = 119, DQM1 = 112
3408 09:58:10.031324 DQ Delay:
3409 09:58:10.034794 DQ0 =120, DQ1 =114, DQ2 =112, DQ3 =118
3410 09:58:10.037952 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =118
3411 09:58:10.041169 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =104
3412 09:58:10.044383 DQ12 =122, DQ13 =118, DQ14 =118, DQ15 =118
3413 09:58:10.044481
3414 09:58:10.044551
3415 09:58:10.051049 [DQSOSCAuto] RK0, (LSB)MR18= 0x317, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3416 09:58:10.054503 CH1 RK0: MR19=404, MR18=317
3417 09:58:10.061039 CH1_RK0: MR19=0x404, MR18=0x317, DQSOSC=401, MR23=63, INC=40, DEC=27
3418 09:58:10.061158
3419 09:58:10.064740 ----->DramcWriteLeveling(PI) begin...
3420 09:58:10.064830 ==
3421 09:58:10.068063 Dram Type= 6, Freq= 0, CH_1, rank 1
3422 09:58:10.071129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3423 09:58:10.071236 ==
3424 09:58:10.074676 Write leveling (Byte 0): 24 => 24
3425 09:58:10.078489 Write leveling (Byte 1): 28 => 28
3426 09:58:10.081421 DramcWriteLeveling(PI) end<-----
3427 09:58:10.081511
3428 09:58:10.081578 ==
3429 09:58:10.084675 Dram Type= 6, Freq= 0, CH_1, rank 1
3430 09:58:10.087898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3431 09:58:10.091295 ==
3432 09:58:10.091384 [Gating] SW mode calibration
3433 09:58:10.098004 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3434 09:58:10.104734 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3435 09:58:10.107855 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3436 09:58:10.115611 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3437 09:58:10.118006 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 09:58:10.121770 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 09:58:10.128423 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 09:58:10.131468 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3441 09:58:10.134794 0 15 24 | B1->B0 | 2727 3333 | 0 1 | (1 0) (1 0)
3442 09:58:10.141235 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3443 09:58:10.144686 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3444 09:58:10.148161 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3445 09:58:10.154750 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 09:58:10.158163 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 09:58:10.161235 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 09:58:10.164622 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 09:58:10.171509 1 0 24 | B1->B0 | 4040 2e2e | 0 1 | (0 0) (0 0)
3450 09:58:10.174575 1 0 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
3451 09:58:10.178276 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3452 09:58:10.184517 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 09:58:10.187825 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 09:58:10.191638 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 09:58:10.198033 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 09:58:10.201185 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 09:58:10.204501 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3458 09:58:10.211602 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3459 09:58:10.214484 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 09:58:10.217863 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 09:58:10.224343 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 09:58:10.227787 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 09:58:10.230975 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 09:58:10.237643 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 09:58:10.241051 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 09:58:10.244230 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 09:58:10.250915 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 09:58:10.254421 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 09:58:10.257604 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 09:58:10.264631 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 09:58:10.267638 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 09:58:10.270835 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3473 09:58:10.277335 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3474 09:58:10.280646 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3475 09:58:10.284407 Total UI for P1: 0, mck2ui 16
3476 09:58:10.287327 best dqsien dly found for B0: ( 1, 3, 22)
3477 09:58:10.290934 Total UI for P1: 0, mck2ui 16
3478 09:58:10.293802 best dqsien dly found for B1: ( 1, 3, 22)
3479 09:58:10.297103 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3480 09:58:10.300644 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3481 09:58:10.300736
3482 09:58:10.304100 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3483 09:58:10.307107 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3484 09:58:10.310599 [Gating] SW calibration Done
3485 09:58:10.310692 ==
3486 09:58:10.313943 Dram Type= 6, Freq= 0, CH_1, rank 1
3487 09:58:10.317183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3488 09:58:10.317275 ==
3489 09:58:10.320493 RX Vref Scan: 0
3490 09:58:10.320579
3491 09:58:10.323694 RX Vref 0 -> 0, step: 1
3492 09:58:10.323789
3493 09:58:10.323856 RX Delay -40 -> 252, step: 8
3494 09:58:10.330860 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3495 09:58:10.334058 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3496 09:58:10.337249 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3497 09:58:10.340584 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3498 09:58:10.344479 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3499 09:58:10.350563 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3500 09:58:10.353903 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3501 09:58:10.357334 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3502 09:58:10.360574 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3503 09:58:10.364127 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3504 09:58:10.370580 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3505 09:58:10.374174 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3506 09:58:10.377147 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3507 09:58:10.380597 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3508 09:58:10.384048 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3509 09:58:10.390485 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3510 09:58:10.390589 ==
3511 09:58:10.394025 Dram Type= 6, Freq= 0, CH_1, rank 1
3512 09:58:10.397104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3513 09:58:10.397191 ==
3514 09:58:10.397256 DQS Delay:
3515 09:58:10.400620 DQS0 = 0, DQS1 = 0
3516 09:58:10.400704 DQM Delay:
3517 09:58:10.403603 DQM0 = 119, DQM1 = 112
3518 09:58:10.403685 DQ Delay:
3519 09:58:10.407539 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =119
3520 09:58:10.410568 DQ4 =119, DQ5 =131, DQ6 =127, DQ7 =115
3521 09:58:10.413771 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3522 09:58:10.416989 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3523 09:58:10.417077
3524 09:58:10.417155
3525 09:58:10.420341 ==
3526 09:58:10.423955 Dram Type= 6, Freq= 0, CH_1, rank 1
3527 09:58:10.427099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3528 09:58:10.427183 ==
3529 09:58:10.427248
3530 09:58:10.427307
3531 09:58:10.430314 TX Vref Scan disable
3532 09:58:10.430418 == TX Byte 0 ==
3533 09:58:10.433939 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3534 09:58:10.440525 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3535 09:58:10.440608 == TX Byte 1 ==
3536 09:58:10.443634 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3537 09:58:10.450251 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3538 09:58:10.450334 ==
3539 09:58:10.453691 Dram Type= 6, Freq= 0, CH_1, rank 1
3540 09:58:10.456751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3541 09:58:10.456834 ==
3542 09:58:10.469087 TX Vref=22, minBit 1, minWin=24, winSum=411
3543 09:58:10.472458 TX Vref=24, minBit 1, minWin=25, winSum=412
3544 09:58:10.476077 TX Vref=26, minBit 1, minWin=25, winSum=417
3545 09:58:10.479240 TX Vref=28, minBit 11, minWin=25, winSum=422
3546 09:58:10.482377 TX Vref=30, minBit 1, minWin=26, winSum=428
3547 09:58:10.486411 TX Vref=32, minBit 0, minWin=26, winSum=424
3548 09:58:10.492410 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 30
3549 09:58:10.492493
3550 09:58:10.496047 Final TX Range 1 Vref 30
3551 09:58:10.496129
3552 09:58:10.496194 ==
3553 09:58:10.499510 Dram Type= 6, Freq= 0, CH_1, rank 1
3554 09:58:10.502644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3555 09:58:10.502726 ==
3556 09:58:10.502791
3557 09:58:10.505743
3558 09:58:10.505824 TX Vref Scan disable
3559 09:58:10.509213 == TX Byte 0 ==
3560 09:58:10.512539 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3561 09:58:10.515994 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3562 09:58:10.519378 == TX Byte 1 ==
3563 09:58:10.522754 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3564 09:58:10.525819 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3565 09:58:10.525904
3566 09:58:10.529418 [DATLAT]
3567 09:58:10.529499 Freq=1200, CH1 RK1
3568 09:58:10.529564
3569 09:58:10.532600 DATLAT Default: 0xd
3570 09:58:10.532682 0, 0xFFFF, sum = 0
3571 09:58:10.535689 1, 0xFFFF, sum = 0
3572 09:58:10.535772 2, 0xFFFF, sum = 0
3573 09:58:10.539622 3, 0xFFFF, sum = 0
3574 09:58:10.539705 4, 0xFFFF, sum = 0
3575 09:58:10.542671 5, 0xFFFF, sum = 0
3576 09:58:10.542755 6, 0xFFFF, sum = 0
3577 09:58:10.545644 7, 0xFFFF, sum = 0
3578 09:58:10.548948 8, 0xFFFF, sum = 0
3579 09:58:10.549030 9, 0xFFFF, sum = 0
3580 09:58:10.552310 10, 0xFFFF, sum = 0
3581 09:58:10.552393 11, 0xFFFF, sum = 0
3582 09:58:10.555905 12, 0x0, sum = 1
3583 09:58:10.555989 13, 0x0, sum = 2
3584 09:58:10.559189 14, 0x0, sum = 3
3585 09:58:10.559272 15, 0x0, sum = 4
3586 09:58:10.559338 best_step = 13
3587 09:58:10.559397
3588 09:58:10.562238 ==
3589 09:58:10.565895 Dram Type= 6, Freq= 0, CH_1, rank 1
3590 09:58:10.568764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3591 09:58:10.568847 ==
3592 09:58:10.568911 RX Vref Scan: 0
3593 09:58:10.568972
3594 09:58:10.572305 RX Vref 0 -> 0, step: 1
3595 09:58:10.572387
3596 09:58:10.575522 RX Delay -13 -> 252, step: 4
3597 09:58:10.579272 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3598 09:58:10.585420 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3599 09:58:10.588654 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3600 09:58:10.592354 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3601 09:58:10.595063 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3602 09:58:10.598292 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3603 09:58:10.605723 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3604 09:58:10.608518 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3605 09:58:10.611805 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3606 09:58:10.615467 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3607 09:58:10.618227 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3608 09:58:10.624806 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3609 09:58:10.628208 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3610 09:58:10.631831 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3611 09:58:10.635167 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3612 09:58:10.641405 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3613 09:58:10.641490 ==
3614 09:58:10.644946 Dram Type= 6, Freq= 0, CH_1, rank 1
3615 09:58:10.647981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3616 09:58:10.648064 ==
3617 09:58:10.648130 DQS Delay:
3618 09:58:10.651558 DQS0 = 0, DQS1 = 0
3619 09:58:10.651640 DQM Delay:
3620 09:58:10.654890 DQM0 = 119, DQM1 = 112
3621 09:58:10.654972 DQ Delay:
3622 09:58:10.658243 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3623 09:58:10.661446 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3624 09:58:10.664889 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =106
3625 09:58:10.668574 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =120
3626 09:58:10.668656
3627 09:58:10.668721
3628 09:58:10.678291 [DQSOSCAuto] RK1, (LSB)MR18= 0xaef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 406 ps
3629 09:58:10.681163 CH1 RK1: MR19=403, MR18=AEF
3630 09:58:10.684917 CH1_RK1: MR19=0x403, MR18=0xAEF, DQSOSC=406, MR23=63, INC=39, DEC=26
3631 09:58:10.687868 [RxdqsGatingPostProcess] freq 1200
3632 09:58:10.694717 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3633 09:58:10.698016 best DQS0 dly(2T, 0.5T) = (0, 11)
3634 09:58:10.701357 best DQS1 dly(2T, 0.5T) = (0, 11)
3635 09:58:10.705019 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3636 09:58:10.708121 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3637 09:58:10.711690 best DQS0 dly(2T, 0.5T) = (0, 11)
3638 09:58:10.714770 best DQS1 dly(2T, 0.5T) = (0, 11)
3639 09:58:10.718273 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3640 09:58:10.721213 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3641 09:58:10.721296 Pre-setting of DQS Precalculation
3642 09:58:10.727754 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3643 09:58:10.734516 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3644 09:58:10.741265 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3645 09:58:10.741348
3646 09:58:10.741413
3647 09:58:10.744336 [Calibration Summary] 2400 Mbps
3648 09:58:10.747902 CH 0, Rank 0
3649 09:58:10.747984 SW Impedance : PASS
3650 09:58:10.751510 DUTY Scan : NO K
3651 09:58:10.754409 ZQ Calibration : PASS
3652 09:58:10.754505 Jitter Meter : NO K
3653 09:58:10.758064 CBT Training : PASS
3654 09:58:10.761621 Write leveling : PASS
3655 09:58:10.761703 RX DQS gating : PASS
3656 09:58:10.764675 RX DQ/DQS(RDDQC) : PASS
3657 09:58:10.764757 TX DQ/DQS : PASS
3658 09:58:10.767826 RX DATLAT : PASS
3659 09:58:10.771070 RX DQ/DQS(Engine): PASS
3660 09:58:10.771151 TX OE : NO K
3661 09:58:10.774428 All Pass.
3662 09:58:10.774509
3663 09:58:10.774575 CH 0, Rank 1
3664 09:58:10.777767 SW Impedance : PASS
3665 09:58:10.777849 DUTY Scan : NO K
3666 09:58:10.781170 ZQ Calibration : PASS
3667 09:58:10.784924 Jitter Meter : NO K
3668 09:58:10.785005 CBT Training : PASS
3669 09:58:10.787534 Write leveling : PASS
3670 09:58:10.791017 RX DQS gating : PASS
3671 09:58:10.791098 RX DQ/DQS(RDDQC) : PASS
3672 09:58:10.794191 TX DQ/DQS : PASS
3673 09:58:10.797798 RX DATLAT : PASS
3674 09:58:10.797879 RX DQ/DQS(Engine): PASS
3675 09:58:10.800995 TX OE : NO K
3676 09:58:10.801076 All Pass.
3677 09:58:10.801141
3678 09:58:10.804304 CH 1, Rank 0
3679 09:58:10.804385 SW Impedance : PASS
3680 09:58:10.807802 DUTY Scan : NO K
3681 09:58:10.811219 ZQ Calibration : PASS
3682 09:58:10.811301 Jitter Meter : NO K
3683 09:58:10.814324 CBT Training : PASS
3684 09:58:10.814443 Write leveling : PASS
3685 09:58:10.817906 RX DQS gating : PASS
3686 09:58:10.820974 RX DQ/DQS(RDDQC) : PASS
3687 09:58:10.821061 TX DQ/DQS : PASS
3688 09:58:10.824512 RX DATLAT : PASS
3689 09:58:10.827624 RX DQ/DQS(Engine): PASS
3690 09:58:10.827707 TX OE : NO K
3691 09:58:10.831207 All Pass.
3692 09:58:10.831289
3693 09:58:10.831354 CH 1, Rank 1
3694 09:58:10.834324 SW Impedance : PASS
3695 09:58:10.834444 DUTY Scan : NO K
3696 09:58:10.837539 ZQ Calibration : PASS
3697 09:58:10.840922 Jitter Meter : NO K
3698 09:58:10.841004 CBT Training : PASS
3699 09:58:10.844239 Write leveling : PASS
3700 09:58:10.847570 RX DQS gating : PASS
3701 09:58:10.847652 RX DQ/DQS(RDDQC) : PASS
3702 09:58:10.851066 TX DQ/DQS : PASS
3703 09:58:10.854230 RX DATLAT : PASS
3704 09:58:10.854311 RX DQ/DQS(Engine): PASS
3705 09:58:10.857372 TX OE : NO K
3706 09:58:10.857454 All Pass.
3707 09:58:10.857518
3708 09:58:10.861128 DramC Write-DBI off
3709 09:58:10.863966 PER_BANK_REFRESH: Hybrid Mode
3710 09:58:10.864048 TX_TRACKING: ON
3711 09:58:10.873982 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3712 09:58:10.877596 [FAST_K] Save calibration result to emmc
3713 09:58:10.880660 dramc_set_vcore_voltage set vcore to 650000
3714 09:58:10.884290 Read voltage for 600, 5
3715 09:58:10.884373 Vio18 = 0
3716 09:58:10.884438 Vcore = 650000
3717 09:58:10.887719 Vdram = 0
3718 09:58:10.887801 Vddq = 0
3719 09:58:10.887866 Vmddr = 0
3720 09:58:10.893983 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3721 09:58:10.897441 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3722 09:58:10.900882 MEM_TYPE=3, freq_sel=19
3723 09:58:10.904066 sv_algorithm_assistance_LP4_1600
3724 09:58:10.907128 ============ PULL DRAM RESETB DOWN ============
3725 09:58:10.910593 ========== PULL DRAM RESETB DOWN end =========
3726 09:58:10.917136 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3727 09:58:10.920399 ===================================
3728 09:58:10.920482 LPDDR4 DRAM CONFIGURATION
3729 09:58:10.923654 ===================================
3730 09:58:10.927328 EX_ROW_EN[0] = 0x0
3731 09:58:10.930653 EX_ROW_EN[1] = 0x0
3732 09:58:10.930735 LP4Y_EN = 0x0
3733 09:58:10.934029 WORK_FSP = 0x0
3734 09:58:10.934111 WL = 0x2
3735 09:58:10.937308 RL = 0x2
3736 09:58:10.937390 BL = 0x2
3737 09:58:10.940393 RPST = 0x0
3738 09:58:10.940474 RD_PRE = 0x0
3739 09:58:10.943593 WR_PRE = 0x1
3740 09:58:10.943676 WR_PST = 0x0
3741 09:58:10.947310 DBI_WR = 0x0
3742 09:58:10.947392 DBI_RD = 0x0
3743 09:58:10.950489 OTF = 0x1
3744 09:58:10.953633 ===================================
3745 09:58:10.957599 ===================================
3746 09:58:10.957681 ANA top config
3747 09:58:10.960385 ===================================
3748 09:58:10.963871 DLL_ASYNC_EN = 0
3749 09:58:10.966905 ALL_SLAVE_EN = 1
3750 09:58:10.970490 NEW_RANK_MODE = 1
3751 09:58:10.970572 DLL_IDLE_MODE = 1
3752 09:58:10.973600 LP45_APHY_COMB_EN = 1
3753 09:58:10.976889 TX_ODT_DIS = 1
3754 09:58:10.980325 NEW_8X_MODE = 1
3755 09:58:10.983984 ===================================
3756 09:58:10.987112 ===================================
3757 09:58:10.987196 data_rate = 1200
3758 09:58:10.990336 CKR = 1
3759 09:58:10.993981 DQ_P2S_RATIO = 8
3760 09:58:10.997023 ===================================
3761 09:58:11.000557 CA_P2S_RATIO = 8
3762 09:58:11.003869 DQ_CA_OPEN = 0
3763 09:58:11.007069 DQ_SEMI_OPEN = 0
3764 09:58:11.007152 CA_SEMI_OPEN = 0
3765 09:58:11.010244 CA_FULL_RATE = 0
3766 09:58:11.013535 DQ_CKDIV4_EN = 1
3767 09:58:11.017010 CA_CKDIV4_EN = 1
3768 09:58:11.020211 CA_PREDIV_EN = 0
3769 09:58:11.023990 PH8_DLY = 0
3770 09:58:11.024075 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3771 09:58:11.026973 DQ_AAMCK_DIV = 4
3772 09:58:11.030175 CA_AAMCK_DIV = 4
3773 09:58:11.033544 CA_ADMCK_DIV = 4
3774 09:58:11.036910 DQ_TRACK_CA_EN = 0
3775 09:58:11.040218 CA_PICK = 600
3776 09:58:11.043533 CA_MCKIO = 600
3777 09:58:11.043616 MCKIO_SEMI = 0
3778 09:58:11.046952 PLL_FREQ = 2288
3779 09:58:11.050708 DQ_UI_PI_RATIO = 32
3780 09:58:11.053634 CA_UI_PI_RATIO = 0
3781 09:58:11.056924 ===================================
3782 09:58:11.060941 ===================================
3783 09:58:11.063660 memory_type:LPDDR4
3784 09:58:11.063743 GP_NUM : 10
3785 09:58:11.066996 SRAM_EN : 1
3786 09:58:11.067078 MD32_EN : 0
3787 09:58:11.070174 ===================================
3788 09:58:11.073748 [ANA_INIT] >>>>>>>>>>>>>>
3789 09:58:11.076923 <<<<<< [CONFIGURE PHASE]: ANA_TX
3790 09:58:11.080555 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3791 09:58:11.084129 ===================================
3792 09:58:11.086827 data_rate = 1200,PCW = 0X5800
3793 09:58:11.090674 ===================================
3794 09:58:11.093582 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3795 09:58:11.100388 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3796 09:58:11.103511 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3797 09:58:11.110072 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3798 09:58:11.113389 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3799 09:58:11.116814 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3800 09:58:11.116900 [ANA_INIT] flow start
3801 09:58:11.119866 [ANA_INIT] PLL >>>>>>>>
3802 09:58:11.123465 [ANA_INIT] PLL <<<<<<<<
3803 09:58:11.123552 [ANA_INIT] MIDPI >>>>>>>>
3804 09:58:11.126547 [ANA_INIT] MIDPI <<<<<<<<
3805 09:58:11.130592 [ANA_INIT] DLL >>>>>>>>
3806 09:58:11.130681 [ANA_INIT] flow end
3807 09:58:11.136583 ============ LP4 DIFF to SE enter ============
3808 09:58:11.140146 ============ LP4 DIFF to SE exit ============
3809 09:58:11.143228 [ANA_INIT] <<<<<<<<<<<<<
3810 09:58:11.146958 [Flow] Enable top DCM control >>>>>
3811 09:58:11.149849 [Flow] Enable top DCM control <<<<<
3812 09:58:11.149934 Enable DLL master slave shuffle
3813 09:58:11.156455 ==============================================================
3814 09:58:11.159760 Gating Mode config
3815 09:58:11.163550 ==============================================================
3816 09:58:11.166546 Config description:
3817 09:58:11.176199 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3818 09:58:11.183094 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3819 09:58:11.186155 SELPH_MODE 0: By rank 1: By Phase
3820 09:58:11.192679 ==============================================================
3821 09:58:11.196177 GAT_TRACK_EN = 1
3822 09:58:11.199578 RX_GATING_MODE = 2
3823 09:58:11.202754 RX_GATING_TRACK_MODE = 2
3824 09:58:11.206079 SELPH_MODE = 1
3825 09:58:11.206163 PICG_EARLY_EN = 1
3826 09:58:11.209453 VALID_LAT_VALUE = 1
3827 09:58:11.216002 ==============================================================
3828 09:58:11.219318 Enter into Gating configuration >>>>
3829 09:58:11.222567 Exit from Gating configuration <<<<
3830 09:58:11.226004 Enter into DVFS_PRE_config >>>>>
3831 09:58:11.235747 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3832 09:58:11.239048 Exit from DVFS_PRE_config <<<<<
3833 09:58:11.242301 Enter into PICG configuration >>>>
3834 09:58:11.246076 Exit from PICG configuration <<<<
3835 09:58:11.249284 [RX_INPUT] configuration >>>>>
3836 09:58:11.252654 [RX_INPUT] configuration <<<<<
3837 09:58:11.255819 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3838 09:58:11.262163 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3839 09:58:11.269021 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3840 09:58:11.275516 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3841 09:58:11.282159 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3842 09:58:11.288519 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3843 09:58:11.291808 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3844 09:58:11.295346 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3845 09:58:11.298512 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3846 09:58:11.305362 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3847 09:58:11.308623 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3848 09:58:11.311803 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3849 09:58:11.315015 ===================================
3850 09:58:11.318682 LPDDR4 DRAM CONFIGURATION
3851 09:58:11.321833 ===================================
3852 09:58:11.321929 EX_ROW_EN[0] = 0x0
3853 09:58:11.325148 EX_ROW_EN[1] = 0x0
3854 09:58:11.325289 LP4Y_EN = 0x0
3855 09:58:11.328602 WORK_FSP = 0x0
3856 09:58:11.331935 WL = 0x2
3857 09:58:11.332038 RL = 0x2
3858 09:58:11.335302 BL = 0x2
3859 09:58:11.335394 RPST = 0x0
3860 09:58:11.338636 RD_PRE = 0x0
3861 09:58:11.338729 WR_PRE = 0x1
3862 09:58:11.341884 WR_PST = 0x0
3863 09:58:11.341976 DBI_WR = 0x0
3864 09:58:11.345372 DBI_RD = 0x0
3865 09:58:11.345482 OTF = 0x1
3866 09:58:11.348745 ===================================
3867 09:58:11.351868 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3868 09:58:11.358632 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3869 09:58:11.361777 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3870 09:58:11.365147 ===================================
3871 09:58:11.368579 LPDDR4 DRAM CONFIGURATION
3872 09:58:11.371861 ===================================
3873 09:58:11.371944 EX_ROW_EN[0] = 0x10
3874 09:58:11.375031 EX_ROW_EN[1] = 0x0
3875 09:58:11.375113 LP4Y_EN = 0x0
3876 09:58:11.378626 WORK_FSP = 0x0
3877 09:58:11.378708 WL = 0x2
3878 09:58:11.381968 RL = 0x2
3879 09:58:11.382051 BL = 0x2
3880 09:58:11.385028 RPST = 0x0
3881 09:58:11.385110 RD_PRE = 0x0
3882 09:58:11.388413 WR_PRE = 0x1
3883 09:58:11.388495 WR_PST = 0x0
3884 09:58:11.392307 DBI_WR = 0x0
3885 09:58:11.395388 DBI_RD = 0x0
3886 09:58:11.395470 OTF = 0x1
3887 09:58:11.398297 ===================================
3888 09:58:11.404951 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3889 09:58:11.408993 nWR fixed to 30
3890 09:58:11.411879 [ModeRegInit_LP4] CH0 RK0
3891 09:58:11.411961 [ModeRegInit_LP4] CH0 RK1
3892 09:58:11.415435 [ModeRegInit_LP4] CH1 RK0
3893 09:58:11.418564 [ModeRegInit_LP4] CH1 RK1
3894 09:58:11.418648 match AC timing 17
3895 09:58:11.425282 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3896 09:58:11.428648 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3897 09:58:11.431970 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3898 09:58:11.438895 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3899 09:58:11.441893 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3900 09:58:11.441979 ==
3901 09:58:11.445264 Dram Type= 6, Freq= 0, CH_0, rank 0
3902 09:58:11.448549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3903 09:58:11.448635 ==
3904 09:58:11.455097 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3905 09:58:11.461732 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3906 09:58:11.465121 [CA 0] Center 36 (6~67) winsize 62
3907 09:58:11.468785 [CA 1] Center 36 (6~67) winsize 62
3908 09:58:11.471540 [CA 2] Center 34 (4~65) winsize 62
3909 09:58:11.475787 [CA 3] Center 34 (4~65) winsize 62
3910 09:58:11.478319 [CA 4] Center 34 (3~65) winsize 63
3911 09:58:11.481569 [CA 5] Center 33 (3~64) winsize 62
3912 09:58:11.481651
3913 09:58:11.485137 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3914 09:58:11.485220
3915 09:58:11.488648 [CATrainingPosCal] consider 1 rank data
3916 09:58:11.491647 u2DelayCellTimex100 = 270/100 ps
3917 09:58:11.495854 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3918 09:58:11.498130 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3919 09:58:11.501712 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3920 09:58:11.504781 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3921 09:58:11.508415 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3922 09:58:11.511496 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3923 09:58:11.515713
3924 09:58:11.518366 CA PerBit enable=1, Macro0, CA PI delay=33
3925 09:58:11.518456
3926 09:58:11.522617 [CBTSetCACLKResult] CA Dly = 33
3927 09:58:11.522699 CS Dly: 5 (0~36)
3928 09:58:11.522764 ==
3929 09:58:11.524995 Dram Type= 6, Freq= 0, CH_0, rank 1
3930 09:58:11.528084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3931 09:58:11.528167 ==
3932 09:58:11.534860 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3933 09:58:11.541428 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3934 09:58:11.544644 [CA 0] Center 36 (6~67) winsize 62
3935 09:58:11.548052 [CA 1] Center 36 (6~67) winsize 62
3936 09:58:11.551431 [CA 2] Center 35 (5~66) winsize 62
3937 09:58:11.554974 [CA 3] Center 34 (4~65) winsize 62
3938 09:58:11.557930 [CA 4] Center 34 (3~65) winsize 63
3939 09:58:11.561357 [CA 5] Center 34 (3~65) winsize 63
3940 09:58:11.561443
3941 09:58:11.564590 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3942 09:58:11.564672
3943 09:58:11.568071 [CATrainingPosCal] consider 2 rank data
3944 09:58:11.571362 u2DelayCellTimex100 = 270/100 ps
3945 09:58:11.574755 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3946 09:58:11.577894 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3947 09:58:11.581171 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3948 09:58:11.584550 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3949 09:58:11.591209 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3950 09:58:11.595014 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3951 09:58:11.595097
3952 09:58:11.598068 CA PerBit enable=1, Macro0, CA PI delay=33
3953 09:58:11.598150
3954 09:58:11.601064 [CBTSetCACLKResult] CA Dly = 33
3955 09:58:11.601146 CS Dly: 5 (0~36)
3956 09:58:11.601210
3957 09:58:11.604499 ----->DramcWriteLeveling(PI) begin...
3958 09:58:11.604582 ==
3959 09:58:11.607874 Dram Type= 6, Freq= 0, CH_0, rank 0
3960 09:58:11.614909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3961 09:58:11.614993 ==
3962 09:58:11.617702 Write leveling (Byte 0): 32 => 32
3963 09:58:11.617785 Write leveling (Byte 1): 32 => 32
3964 09:58:11.621035 DramcWriteLeveling(PI) end<-----
3965 09:58:11.621117
3966 09:58:11.624808 ==
3967 09:58:11.624894 Dram Type= 6, Freq= 0, CH_0, rank 0
3968 09:58:11.630996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3969 09:58:11.631081 ==
3970 09:58:11.634498 [Gating] SW mode calibration
3971 09:58:11.641215 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3972 09:58:11.644402 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3973 09:58:11.651105 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3974 09:58:11.654311 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3975 09:58:11.657518 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3976 09:58:11.664364 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
3977 09:58:11.667708 0 9 16 | B1->B0 | 2c2c 2323 | 1 0 | (1 1) (0 0)
3978 09:58:11.670654 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 09:58:11.677404 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 09:58:11.680792 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 09:58:11.684031 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 09:58:11.690724 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 09:58:11.694186 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 09:58:11.697399 0 10 12 | B1->B0 | 2626 3737 | 0 0 | (0 0) (0 0)
3985 09:58:11.704041 0 10 16 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
3986 09:58:11.707538 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 09:58:11.710414 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 09:58:11.717053 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 09:58:11.720760 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 09:58:11.723782 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 09:58:11.730953 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 09:58:11.733954 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 09:58:11.737170 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3994 09:58:11.740464 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 09:58:11.747062 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 09:58:11.750879 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 09:58:11.753764 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 09:58:11.760546 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 09:58:11.763643 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 09:58:11.767162 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 09:58:11.773580 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 09:58:11.777077 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 09:58:11.780320 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 09:58:11.787315 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 09:58:11.790532 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 09:58:11.793639 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 09:58:11.800467 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 09:58:11.803697 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 09:58:11.806907 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4010 09:58:11.810245 Total UI for P1: 0, mck2ui 16
4011 09:58:11.813722 best dqsien dly found for B0: ( 0, 13, 14)
4012 09:58:11.820064 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 09:58:11.820157 Total UI for P1: 0, mck2ui 16
4014 09:58:11.824140 best dqsien dly found for B1: ( 0, 13, 16)
4015 09:58:11.830281 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4016 09:58:11.833723 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4017 09:58:11.833808
4018 09:58:11.836957 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4019 09:58:11.840117 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4020 09:58:11.844042 [Gating] SW calibration Done
4021 09:58:11.844130 ==
4022 09:58:11.846676 Dram Type= 6, Freq= 0, CH_0, rank 0
4023 09:58:11.850119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4024 09:58:11.850203 ==
4025 09:58:11.853287 RX Vref Scan: 0
4026 09:58:11.853370
4027 09:58:11.853435 RX Vref 0 -> 0, step: 1
4028 09:58:11.853496
4029 09:58:11.857007 RX Delay -230 -> 252, step: 16
4030 09:58:11.863433 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4031 09:58:11.866451 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4032 09:58:11.870106 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4033 09:58:11.873511 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4034 09:58:11.876925 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4035 09:58:11.883263 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4036 09:58:11.886564 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4037 09:58:11.889914 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4038 09:58:11.893356 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4039 09:58:11.899719 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4040 09:58:11.903509 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4041 09:58:11.906487 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4042 09:58:11.909757 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4043 09:58:11.913353 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4044 09:58:11.919987 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4045 09:58:11.923204 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4046 09:58:11.923288 ==
4047 09:58:11.926283 Dram Type= 6, Freq= 0, CH_0, rank 0
4048 09:58:11.929801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4049 09:58:11.929887 ==
4050 09:58:11.933167 DQS Delay:
4051 09:58:11.933249 DQS0 = 0, DQS1 = 0
4052 09:58:11.936200 DQM Delay:
4053 09:58:11.936285 DQM0 = 49, DQM1 = 39
4054 09:58:11.936350 DQ Delay:
4055 09:58:11.939628 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =49
4056 09:58:11.943144 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4057 09:58:11.946544 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4058 09:58:11.949454 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4059 09:58:11.949536
4060 09:58:11.949602
4061 09:58:11.953048 ==
4062 09:58:11.953131 Dram Type= 6, Freq= 0, CH_0, rank 0
4063 09:58:11.959923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4064 09:58:11.960019 ==
4065 09:58:11.960086
4066 09:58:11.960145
4067 09:58:11.962792 TX Vref Scan disable
4068 09:58:11.962875 == TX Byte 0 ==
4069 09:58:11.966500 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4070 09:58:11.972595 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4071 09:58:11.972679 == TX Byte 1 ==
4072 09:58:11.979396 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4073 09:58:11.982810 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4074 09:58:11.982907 ==
4075 09:58:11.986214 Dram Type= 6, Freq= 0, CH_0, rank 0
4076 09:58:11.989425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4077 09:58:11.989537 ==
4078 09:58:11.989608
4079 09:58:11.989670
4080 09:58:11.993225 TX Vref Scan disable
4081 09:58:11.996251 == TX Byte 0 ==
4082 09:58:11.999524 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4083 09:58:12.002609 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4084 09:58:12.005870 == TX Byte 1 ==
4085 09:58:12.009216 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4086 09:58:12.012500 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4087 09:58:12.012617
4088 09:58:12.015928 [DATLAT]
4089 09:58:12.016020 Freq=600, CH0 RK0
4090 09:58:12.016089
4091 09:58:12.019147 DATLAT Default: 0x9
4092 09:58:12.019260 0, 0xFFFF, sum = 0
4093 09:58:12.022645 1, 0xFFFF, sum = 0
4094 09:58:12.022734 2, 0xFFFF, sum = 0
4095 09:58:12.025863 3, 0xFFFF, sum = 0
4096 09:58:12.025959 4, 0xFFFF, sum = 0
4097 09:58:12.029310 5, 0xFFFF, sum = 0
4098 09:58:12.029405 6, 0xFFFF, sum = 0
4099 09:58:12.032308 7, 0xFFFF, sum = 0
4100 09:58:12.032396 8, 0x0, sum = 1
4101 09:58:12.035626 9, 0x0, sum = 2
4102 09:58:12.035716 10, 0x0, sum = 3
4103 09:58:12.038922 11, 0x0, sum = 4
4104 09:58:12.039010 best_step = 9
4105 09:58:12.039077
4106 09:58:12.039137 ==
4107 09:58:12.042322 Dram Type= 6, Freq= 0, CH_0, rank 0
4108 09:58:12.045678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4109 09:58:12.049011 ==
4110 09:58:12.049105 RX Vref Scan: 1
4111 09:58:12.049170
4112 09:58:12.052359 RX Vref 0 -> 0, step: 1
4113 09:58:12.052447
4114 09:58:12.055566 RX Delay -179 -> 252, step: 8
4115 09:58:12.055655
4116 09:58:12.058947 Set Vref, RX VrefLevel [Byte0]: 58
4117 09:58:12.062538 [Byte1]: 49
4118 09:58:12.062636
4119 09:58:12.065472 Final RX Vref Byte 0 = 58 to rank0
4120 09:58:12.069226 Final RX Vref Byte 1 = 49 to rank0
4121 09:58:12.072471 Final RX Vref Byte 0 = 58 to rank1
4122 09:58:12.075517 Final RX Vref Byte 1 = 49 to rank1==
4123 09:58:12.078849 Dram Type= 6, Freq= 0, CH_0, rank 0
4124 09:58:12.082325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4125 09:58:12.082480 ==
4126 09:58:12.082549 DQS Delay:
4127 09:58:12.085679 DQS0 = 0, DQS1 = 0
4128 09:58:12.085763 DQM Delay:
4129 09:58:12.089112 DQM0 = 48, DQM1 = 39
4130 09:58:12.089197 DQ Delay:
4131 09:58:12.092609 DQ0 =44, DQ1 =48, DQ2 =44, DQ3 =44
4132 09:58:12.095429 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =56
4133 09:58:12.098992 DQ8 =36, DQ9 =24, DQ10 =36, DQ11 =36
4134 09:58:12.102654 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =48
4135 09:58:12.102745
4136 09:58:12.102810
4137 09:58:12.112199 [DQSOSCAuto] RK0, (LSB)MR18= 0x5751, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
4138 09:58:12.112320 CH0 RK0: MR19=808, MR18=5751
4139 09:58:12.119238 CH0_RK0: MR19=0x808, MR18=0x5751, DQSOSC=393, MR23=63, INC=169, DEC=113
4140 09:58:12.119363
4141 09:58:12.121989 ----->DramcWriteLeveling(PI) begin...
4142 09:58:12.122076 ==
4143 09:58:12.126184 Dram Type= 6, Freq= 0, CH_0, rank 1
4144 09:58:12.132147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4145 09:58:12.132270 ==
4146 09:58:12.136044 Write leveling (Byte 0): 34 => 34
4147 09:58:12.138824 Write leveling (Byte 1): 30 => 30
4148 09:58:12.138921 DramcWriteLeveling(PI) end<-----
4149 09:58:12.138987
4150 09:58:12.142331 ==
4151 09:58:12.145426 Dram Type= 6, Freq= 0, CH_0, rank 1
4152 09:58:12.149036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 09:58:12.149131 ==
4154 09:58:12.152187 [Gating] SW mode calibration
4155 09:58:12.158809 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4156 09:58:12.162102 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4157 09:58:12.168602 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4158 09:58:12.172222 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4159 09:58:12.175523 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4160 09:58:12.182047 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 0)
4161 09:58:12.185449 0 9 16 | B1->B0 | 2b2b 2525 | 1 0 | (1 0) (0 0)
4162 09:58:12.188896 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4163 09:58:12.195267 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4164 09:58:12.198456 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 09:58:12.201756 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 09:58:12.208661 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 09:58:12.212094 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 09:58:12.215021 0 10 12 | B1->B0 | 3030 3232 | 0 0 | (0 0) (0 0)
4169 09:58:12.221641 0 10 16 | B1->B0 | 3e3e 4444 | 1 0 | (0 0) (0 0)
4170 09:58:12.225343 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4171 09:58:12.228466 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4172 09:58:12.235004 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 09:58:12.238286 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 09:58:12.241544 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 09:58:12.248400 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 09:58:12.251658 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4177 09:58:12.254722 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 09:58:12.258307 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 09:58:12.264821 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 09:58:12.268124 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 09:58:12.271564 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 09:58:12.278095 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 09:58:12.281635 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 09:58:12.285408 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 09:58:12.291656 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 09:58:12.294760 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 09:58:12.298199 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 09:58:12.304624 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 09:58:12.307988 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 09:58:12.311251 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 09:58:12.317949 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 09:58:12.321370 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 09:58:12.324598 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 09:58:12.327966 Total UI for P1: 0, mck2ui 16
4195 09:58:12.331524 best dqsien dly found for B0: ( 0, 13, 14)
4196 09:58:12.334611 Total UI for P1: 0, mck2ui 16
4197 09:58:12.338018 best dqsien dly found for B1: ( 0, 13, 14)
4198 09:58:12.341411 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4199 09:58:12.344970 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4200 09:58:12.345074
4201 09:58:12.351106 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4202 09:58:12.354657 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4203 09:58:12.357790 [Gating] SW calibration Done
4204 09:58:12.357882 ==
4205 09:58:12.361066 Dram Type= 6, Freq= 0, CH_0, rank 1
4206 09:58:12.365051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4207 09:58:12.365145 ==
4208 09:58:12.365214 RX Vref Scan: 0
4209 09:58:12.365275
4210 09:58:12.367693 RX Vref 0 -> 0, step: 1
4211 09:58:12.367780
4212 09:58:12.371417 RX Delay -230 -> 252, step: 16
4213 09:58:12.374538 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4214 09:58:12.378352 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4215 09:58:12.384191 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4216 09:58:12.387668 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4217 09:58:12.391093 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4218 09:58:12.395310 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4219 09:58:12.400902 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4220 09:58:12.404474 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4221 09:58:12.407859 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4222 09:58:12.410832 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4223 09:58:12.414325 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4224 09:58:12.420827 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4225 09:58:12.424357 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4226 09:58:12.427209 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4227 09:58:12.431312 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4228 09:58:12.437476 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4229 09:58:12.437599 ==
4230 09:58:12.440884 Dram Type= 6, Freq= 0, CH_0, rank 1
4231 09:58:12.444702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4232 09:58:12.444806 ==
4233 09:58:12.444875 DQS Delay:
4234 09:58:12.447471 DQS0 = 0, DQS1 = 0
4235 09:58:12.447584 DQM Delay:
4236 09:58:12.450870 DQM0 = 51, DQM1 = 44
4237 09:58:12.450959 DQ Delay:
4238 09:58:12.454232 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4239 09:58:12.457911 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =57
4240 09:58:12.460883 DQ8 =25, DQ9 =25, DQ10 =49, DQ11 =49
4241 09:58:12.463983 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4242 09:58:12.464105
4243 09:58:12.464201
4244 09:58:12.464290 ==
4245 09:58:12.467333 Dram Type= 6, Freq= 0, CH_0, rank 1
4246 09:58:12.470851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4247 09:58:12.473822 ==
4248 09:58:12.473918
4249 09:58:12.473985
4250 09:58:12.474046 TX Vref Scan disable
4251 09:58:12.477305 == TX Byte 0 ==
4252 09:58:12.480466 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4253 09:58:12.484102 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4254 09:58:12.487514 == TX Byte 1 ==
4255 09:58:12.490355 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4256 09:58:12.493911 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4257 09:58:12.497240 ==
4258 09:58:12.500596 Dram Type= 6, Freq= 0, CH_0, rank 1
4259 09:58:12.503931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4260 09:58:12.504027 ==
4261 09:58:12.504094
4262 09:58:12.504154
4263 09:58:12.507171 TX Vref Scan disable
4264 09:58:12.507260 == TX Byte 0 ==
4265 09:58:12.514308 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4266 09:58:12.516930 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4267 09:58:12.520156 == TX Byte 1 ==
4268 09:58:12.523436 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4269 09:58:12.526831 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4270 09:58:12.526990
4271 09:58:12.527092 [DATLAT]
4272 09:58:12.530250 Freq=600, CH0 RK1
4273 09:58:12.530367
4274 09:58:12.530503 DATLAT Default: 0x9
4275 09:58:12.533593 0, 0xFFFF, sum = 0
4276 09:58:12.537231 1, 0xFFFF, sum = 0
4277 09:58:12.537337 2, 0xFFFF, sum = 0
4278 09:58:12.540674 3, 0xFFFF, sum = 0
4279 09:58:12.540780 4, 0xFFFF, sum = 0
4280 09:58:12.543662 5, 0xFFFF, sum = 0
4281 09:58:12.543755 6, 0xFFFF, sum = 0
4282 09:58:12.546993 7, 0xFFFF, sum = 0
4283 09:58:12.547088 8, 0x0, sum = 1
4284 09:58:12.550175 9, 0x0, sum = 2
4285 09:58:12.550295 10, 0x0, sum = 3
4286 09:58:12.550416 11, 0x0, sum = 4
4287 09:58:12.553323 best_step = 9
4288 09:58:12.553414
4289 09:58:12.553481 ==
4290 09:58:12.556790 Dram Type= 6, Freq= 0, CH_0, rank 1
4291 09:58:12.559898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4292 09:58:12.559991 ==
4293 09:58:12.563462 RX Vref Scan: 0
4294 09:58:12.563555
4295 09:58:12.563621 RX Vref 0 -> 0, step: 1
4296 09:58:12.566416
4297 09:58:12.566503 RX Delay -179 -> 252, step: 8
4298 09:58:12.574126 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4299 09:58:12.577930 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4300 09:58:12.580659 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4301 09:58:12.584118 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4302 09:58:12.590584 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4303 09:58:12.594360 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4304 09:58:12.597422 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4305 09:58:12.600748 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4306 09:58:12.604275 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4307 09:58:12.610964 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4308 09:58:12.614112 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4309 09:58:12.617397 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4310 09:58:12.620608 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4311 09:58:12.624063 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4312 09:58:12.631058 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4313 09:58:12.634272 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4314 09:58:12.634435 ==
4315 09:58:12.637375 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 09:58:12.640703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 09:58:12.640807 ==
4318 09:58:12.644076 DQS Delay:
4319 09:58:12.644171 DQS0 = 0, DQS1 = 0
4320 09:58:12.644238 DQM Delay:
4321 09:58:12.647357 DQM0 = 47, DQM1 = 40
4322 09:58:12.647449 DQ Delay:
4323 09:58:12.650649 DQ0 =44, DQ1 =48, DQ2 =44, DQ3 =40
4324 09:58:12.653830 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4325 09:58:12.657562 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4326 09:58:12.660397 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =52
4327 09:58:12.660509
4328 09:58:12.660574
4329 09:58:12.670336 [DQSOSCAuto] RK1, (LSB)MR18= 0x6634, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
4330 09:58:12.673826 CH0 RK1: MR19=808, MR18=6634
4331 09:58:12.677016 CH0_RK1: MR19=0x808, MR18=0x6634, DQSOSC=390, MR23=63, INC=172, DEC=114
4332 09:58:12.680494 [RxdqsGatingPostProcess] freq 600
4333 09:58:12.687211 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4334 09:58:12.690400 Pre-setting of DQS Precalculation
4335 09:58:12.693588 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4336 09:58:12.693705 ==
4337 09:58:12.697537 Dram Type= 6, Freq= 0, CH_1, rank 0
4338 09:58:12.703530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4339 09:58:12.703651 ==
4340 09:58:12.706852 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4341 09:58:12.713664 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4342 09:58:12.716990 [CA 0] Center 35 (5~66) winsize 62
4343 09:58:12.720572 [CA 1] Center 35 (5~66) winsize 62
4344 09:58:12.723710 [CA 2] Center 34 (4~65) winsize 62
4345 09:58:12.727101 [CA 3] Center 33 (3~64) winsize 62
4346 09:58:12.730162 [CA 4] Center 34 (3~65) winsize 63
4347 09:58:12.733991 [CA 5] Center 33 (3~64) winsize 62
4348 09:58:12.734105
4349 09:58:12.737229 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4350 09:58:12.737322
4351 09:58:12.740148 [CATrainingPosCal] consider 1 rank data
4352 09:58:12.743629 u2DelayCellTimex100 = 270/100 ps
4353 09:58:12.746818 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4354 09:58:12.750478 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4355 09:58:12.756767 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4356 09:58:12.759921 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4357 09:58:12.763693 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4358 09:58:12.766895 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4359 09:58:12.766998
4360 09:58:12.770099 CA PerBit enable=1, Macro0, CA PI delay=33
4361 09:58:12.770189
4362 09:58:12.773316 [CBTSetCACLKResult] CA Dly = 33
4363 09:58:12.773405 CS Dly: 4 (0~35)
4364 09:58:12.776940 ==
4365 09:58:12.780347 Dram Type= 6, Freq= 0, CH_1, rank 1
4366 09:58:12.783347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4367 09:58:12.783445 ==
4368 09:58:12.786621 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4369 09:58:12.793537 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4370 09:58:12.797100 [CA 0] Center 36 (6~66) winsize 61
4371 09:58:12.800592 [CA 1] Center 36 (5~67) winsize 63
4372 09:58:12.803755 [CA 2] Center 34 (4~65) winsize 62
4373 09:58:12.807059 [CA 3] Center 34 (4~65) winsize 62
4374 09:58:12.810300 [CA 4] Center 34 (4~65) winsize 62
4375 09:58:12.813731 [CA 5] Center 34 (4~65) winsize 62
4376 09:58:12.813835
4377 09:58:12.817552 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4378 09:58:12.817655
4379 09:58:12.820571 [CATrainingPosCal] consider 2 rank data
4380 09:58:12.823609 u2DelayCellTimex100 = 270/100 ps
4381 09:58:12.827056 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4382 09:58:12.830204 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4383 09:58:12.837455 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4384 09:58:12.840657 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
4385 09:58:12.843656 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4386 09:58:12.847084 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4387 09:58:12.847198
4388 09:58:12.850457 CA PerBit enable=1, Macro0, CA PI delay=34
4389 09:58:12.850560
4390 09:58:12.854533 [CBTSetCACLKResult] CA Dly = 34
4391 09:58:12.854643 CS Dly: 5 (0~37)
4392 09:58:12.854714
4393 09:58:12.856855 ----->DramcWriteLeveling(PI) begin...
4394 09:58:12.860647 ==
4395 09:58:12.863614 Dram Type= 6, Freq= 0, CH_1, rank 0
4396 09:58:12.867263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4397 09:58:12.867377 ==
4398 09:58:12.870170 Write leveling (Byte 0): 29 => 29
4399 09:58:12.873820 Write leveling (Byte 1): 32 => 32
4400 09:58:12.877245 DramcWriteLeveling(PI) end<-----
4401 09:58:12.877355
4402 09:58:12.877422 ==
4403 09:58:12.880856 Dram Type= 6, Freq= 0, CH_1, rank 0
4404 09:58:12.883633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4405 09:58:12.883733 ==
4406 09:58:12.887140 [Gating] SW mode calibration
4407 09:58:12.893845 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4408 09:58:12.897263 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4409 09:58:12.903568 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4410 09:58:12.906954 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4411 09:58:12.910055 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4412 09:58:12.916689 0 9 12 | B1->B0 | 2c2c 2d2d | 1 1 | (1 1) (1 0)
4413 09:58:12.920148 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 09:58:12.923645 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 09:58:12.930335 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 09:58:12.933173 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 09:58:12.936651 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 09:58:12.943296 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 09:58:12.946655 0 10 8 | B1->B0 | 2424 2828 | 0 1 | (0 0) (0 0)
4420 09:58:12.950017 0 10 12 | B1->B0 | 3a3a 3a3a | 0 0 | (0 0) (0 0)
4421 09:58:12.956485 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 09:58:12.959834 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 09:58:12.962927 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 09:58:12.969657 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 09:58:12.972972 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 09:58:12.976456 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 09:58:12.982896 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 09:58:12.986265 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4429 09:58:12.989558 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 09:58:12.996133 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 09:58:12.999809 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 09:58:13.002859 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 09:58:13.009471 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 09:58:13.012782 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 09:58:13.016318 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 09:58:13.022735 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 09:58:13.026157 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 09:58:13.029728 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 09:58:13.035765 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 09:58:13.039171 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 09:58:13.042575 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 09:58:13.049276 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 09:58:13.052272 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 09:58:13.056035 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4445 09:58:13.062716 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 09:58:13.062855 Total UI for P1: 0, mck2ui 16
4447 09:58:13.069288 best dqsien dly found for B0: ( 0, 13, 12)
4448 09:58:13.069416 Total UI for P1: 0, mck2ui 16
4449 09:58:13.072492 best dqsien dly found for B1: ( 0, 13, 14)
4450 09:58:13.078919 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4451 09:58:13.082667 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4452 09:58:13.082773
4453 09:58:13.085918 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4454 09:58:13.089077 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4455 09:58:13.092384 [Gating] SW calibration Done
4456 09:58:13.092479 ==
4457 09:58:13.095731 Dram Type= 6, Freq= 0, CH_1, rank 0
4458 09:58:13.099475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4459 09:58:13.099575 ==
4460 09:58:13.102671 RX Vref Scan: 0
4461 09:58:13.102759
4462 09:58:13.102826 RX Vref 0 -> 0, step: 1
4463 09:58:13.102887
4464 09:58:13.105931 RX Delay -230 -> 252, step: 16
4465 09:58:13.108884 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4466 09:58:13.115703 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4467 09:58:13.119233 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4468 09:58:13.122515 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4469 09:58:13.125590 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4470 09:58:13.129469 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4471 09:58:13.135767 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4472 09:58:13.138894 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4473 09:58:13.142139 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4474 09:58:13.145433 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4475 09:58:13.152649 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4476 09:58:13.155525 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4477 09:58:13.158665 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4478 09:58:13.162214 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4479 09:58:13.168966 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4480 09:58:13.172146 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4481 09:58:13.172256 ==
4482 09:58:13.175404 Dram Type= 6, Freq= 0, CH_1, rank 0
4483 09:58:13.178772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4484 09:58:13.178875 ==
4485 09:58:13.182121 DQS Delay:
4486 09:58:13.182241 DQS0 = 0, DQS1 = 0
4487 09:58:13.182311 DQM Delay:
4488 09:58:13.185249 DQM0 = 52, DQM1 = 41
4489 09:58:13.185339 DQ Delay:
4490 09:58:13.188734 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4491 09:58:13.191934 DQ4 =49, DQ5 =57, DQ6 =65, DQ7 =49
4492 09:58:13.195309 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4493 09:58:13.198640 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =41
4494 09:58:13.198745
4495 09:58:13.198814
4496 09:58:13.198876 ==
4497 09:58:13.202170 Dram Type= 6, Freq= 0, CH_1, rank 0
4498 09:58:13.205540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4499 09:58:13.208661 ==
4500 09:58:13.208763
4501 09:58:13.208831
4502 09:58:13.208894 TX Vref Scan disable
4503 09:58:13.212341 == TX Byte 0 ==
4504 09:58:13.215315 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4505 09:58:13.221925 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4506 09:58:13.222048 == TX Byte 1 ==
4507 09:58:13.225406 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4508 09:58:13.232505 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4509 09:58:13.232642 ==
4510 09:58:13.236226 Dram Type= 6, Freq= 0, CH_1, rank 0
4511 09:58:13.238579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4512 09:58:13.238672 ==
4513 09:58:13.238740
4514 09:58:13.238805
4515 09:58:13.241606 TX Vref Scan disable
4516 09:58:13.245370 == TX Byte 0 ==
4517 09:58:13.248396 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4518 09:58:13.251931 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4519 09:58:13.254982 == TX Byte 1 ==
4520 09:58:13.258372 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4521 09:58:13.261626 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4522 09:58:13.261727
4523 09:58:13.261796 [DATLAT]
4524 09:58:13.264960 Freq=600, CH1 RK0
4525 09:58:13.265052
4526 09:58:13.268576 DATLAT Default: 0x9
4527 09:58:13.268670 0, 0xFFFF, sum = 0
4528 09:58:13.271595 1, 0xFFFF, sum = 0
4529 09:58:13.271686 2, 0xFFFF, sum = 0
4530 09:58:13.274933 3, 0xFFFF, sum = 0
4531 09:58:13.275025 4, 0xFFFF, sum = 0
4532 09:58:13.278230 5, 0xFFFF, sum = 0
4533 09:58:13.278321 6, 0xFFFF, sum = 0
4534 09:58:13.281759 7, 0xFFFF, sum = 0
4535 09:58:13.281850 8, 0x0, sum = 1
4536 09:58:13.285216 9, 0x0, sum = 2
4537 09:58:13.285306 10, 0x0, sum = 3
4538 09:58:13.285374 11, 0x0, sum = 4
4539 09:58:13.288105 best_step = 9
4540 09:58:13.288192
4541 09:58:13.288259 ==
4542 09:58:13.291474 Dram Type= 6, Freq= 0, CH_1, rank 0
4543 09:58:13.294886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4544 09:58:13.294984 ==
4545 09:58:13.298305 RX Vref Scan: 1
4546 09:58:13.298426
4547 09:58:13.298523 RX Vref 0 -> 0, step: 1
4548 09:58:13.301513
4549 09:58:13.301611 RX Delay -179 -> 252, step: 8
4550 09:58:13.301685
4551 09:58:13.304695 Set Vref, RX VrefLevel [Byte0]: 51
4552 09:58:13.308043 [Byte1]: 50
4553 09:58:13.312919
4554 09:58:13.313061 Final RX Vref Byte 0 = 51 to rank0
4555 09:58:13.315774 Final RX Vref Byte 1 = 50 to rank0
4556 09:58:13.319241 Final RX Vref Byte 0 = 51 to rank1
4557 09:58:13.322707 Final RX Vref Byte 1 = 50 to rank1==
4558 09:58:13.326048 Dram Type= 6, Freq= 0, CH_1, rank 0
4559 09:58:13.332475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4560 09:58:13.332602 ==
4561 09:58:13.332670 DQS Delay:
4562 09:58:13.332732 DQS0 = 0, DQS1 = 0
4563 09:58:13.335861 DQM Delay:
4564 09:58:13.335947 DQM0 = 48, DQM1 = 40
4565 09:58:13.339296 DQ Delay:
4566 09:58:13.342525 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4567 09:58:13.342614 DQ4 =48, DQ5 =56, DQ6 =60, DQ7 =44
4568 09:58:13.345743 DQ8 =28, DQ9 =24, DQ10 =48, DQ11 =36
4569 09:58:13.349163 DQ12 =48, DQ13 =48, DQ14 =44, DQ15 =48
4570 09:58:13.352577
4571 09:58:13.352666
4572 09:58:13.359222 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c73, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4573 09:58:13.362292 CH1 RK0: MR19=808, MR18=4C73
4574 09:58:13.368980 CH1_RK0: MR19=0x808, MR18=0x4C73, DQSOSC=388, MR23=63, INC=174, DEC=116
4575 09:58:13.369094
4576 09:58:13.372918 ----->DramcWriteLeveling(PI) begin...
4577 09:58:13.373017 ==
4578 09:58:13.375662 Dram Type= 6, Freq= 0, CH_1, rank 1
4579 09:58:13.378862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4580 09:58:13.378953 ==
4581 09:58:13.382318 Write leveling (Byte 0): 29 => 29
4582 09:58:13.385582 Write leveling (Byte 1): 30 => 30
4583 09:58:13.389054 DramcWriteLeveling(PI) end<-----
4584 09:58:13.389146
4585 09:58:13.389213 ==
4586 09:58:13.392300 Dram Type= 6, Freq= 0, CH_1, rank 1
4587 09:58:13.395477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 09:58:13.395568 ==
4589 09:58:13.398979 [Gating] SW mode calibration
4590 09:58:13.405484 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4591 09:58:13.412093 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4592 09:58:13.415671 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4593 09:58:13.421897 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4594 09:58:13.425340 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4595 09:58:13.428629 0 9 12 | B1->B0 | 2c2c 3131 | 0 0 | (0 0) (0 0)
4596 09:58:13.432073 0 9 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4597 09:58:13.438691 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4598 09:58:13.442147 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 09:58:13.445379 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 09:58:13.452275 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 09:58:13.455431 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 09:58:13.458420 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 09:58:13.465275 0 10 12 | B1->B0 | 3c3c 3030 | 0 0 | (0 0) (0 0)
4604 09:58:13.468633 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4605 09:58:13.471698 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 09:58:13.478290 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 09:58:13.482114 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 09:58:13.485120 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 09:58:13.492028 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 09:58:13.495062 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 09:58:13.498578 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4612 09:58:13.505326 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 09:58:13.508481 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 09:58:13.511666 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 09:58:13.518420 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 09:58:13.521952 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 09:58:13.524932 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 09:58:13.531634 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 09:58:13.535093 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 09:58:13.539001 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 09:58:13.544942 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 09:58:13.548648 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 09:58:13.551590 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 09:58:13.554929 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 09:58:13.561809 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 09:58:13.564962 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4627 09:58:13.568539 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4628 09:58:13.571724 Total UI for P1: 0, mck2ui 16
4629 09:58:13.575016 best dqsien dly found for B1: ( 0, 13, 8)
4630 09:58:13.581547 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 09:58:13.584755 Total UI for P1: 0, mck2ui 16
4632 09:58:13.588364 best dqsien dly found for B0: ( 0, 13, 12)
4633 09:58:13.591626 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4634 09:58:13.594899 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4635 09:58:13.595002
4636 09:58:13.598270 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4637 09:58:13.601597 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4638 09:58:13.604911 [Gating] SW calibration Done
4639 09:58:13.605024 ==
4640 09:58:13.608426 Dram Type= 6, Freq= 0, CH_1, rank 1
4641 09:58:13.611508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4642 09:58:13.611599 ==
4643 09:58:13.615298 RX Vref Scan: 0
4644 09:58:13.615388
4645 09:58:13.615454 RX Vref 0 -> 0, step: 1
4646 09:58:13.618532
4647 09:58:13.618619 RX Delay -230 -> 252, step: 16
4648 09:58:13.625010 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4649 09:58:13.628269 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4650 09:58:13.631097 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4651 09:58:13.634691 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4652 09:58:13.641529 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4653 09:58:13.644718 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4654 09:58:13.647932 iDelay=218, Bit 6, Center 49 (-102 ~ 201) 304
4655 09:58:13.651547 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4656 09:58:13.654573 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4657 09:58:13.661463 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4658 09:58:13.664526 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4659 09:58:13.667668 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4660 09:58:13.671077 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4661 09:58:13.677892 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4662 09:58:13.681307 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4663 09:58:13.684670 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4664 09:58:13.684793 ==
4665 09:58:13.687913 Dram Type= 6, Freq= 0, CH_1, rank 1
4666 09:58:13.691074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4667 09:58:13.691170 ==
4668 09:58:13.694381 DQS Delay:
4669 09:58:13.694494 DQS0 = 0, DQS1 = 0
4670 09:58:13.697834 DQM Delay:
4671 09:58:13.697932 DQM0 = 50, DQM1 = 47
4672 09:58:13.698000 DQ Delay:
4673 09:58:13.701238 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4674 09:58:13.704738 DQ4 =49, DQ5 =57, DQ6 =49, DQ7 =49
4675 09:58:13.708170 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4676 09:58:13.711069 DQ12 =57, DQ13 =49, DQ14 =57, DQ15 =57
4677 09:58:13.711168
4678 09:58:13.711235
4679 09:58:13.714699 ==
4680 09:58:13.714794 Dram Type= 6, Freq= 0, CH_1, rank 1
4681 09:58:13.720897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4682 09:58:13.721027 ==
4683 09:58:13.721100
4684 09:58:13.721196
4685 09:58:13.724121 TX Vref Scan disable
4686 09:58:13.724211 == TX Byte 0 ==
4687 09:58:13.727637 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4688 09:58:13.734133 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4689 09:58:13.734269 == TX Byte 1 ==
4690 09:58:13.737864 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4691 09:58:13.744324 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4692 09:58:13.744448 ==
4693 09:58:13.747946 Dram Type= 6, Freq= 0, CH_1, rank 1
4694 09:58:13.751118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4695 09:58:13.751216 ==
4696 09:58:13.751284
4697 09:58:13.751345
4698 09:58:13.754366 TX Vref Scan disable
4699 09:58:13.757779 == TX Byte 0 ==
4700 09:58:13.761158 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4701 09:58:13.764206 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4702 09:58:13.767590 == TX Byte 1 ==
4703 09:58:13.770954 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4704 09:58:13.774175 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4705 09:58:13.774268
4706 09:58:13.777597 [DATLAT]
4707 09:58:13.777695 Freq=600, CH1 RK1
4708 09:58:13.777762
4709 09:58:13.780886 DATLAT Default: 0x9
4710 09:58:13.780975 0, 0xFFFF, sum = 0
4711 09:58:13.784153 1, 0xFFFF, sum = 0
4712 09:58:13.784241 2, 0xFFFF, sum = 0
4713 09:58:13.787580 3, 0xFFFF, sum = 0
4714 09:58:13.787670 4, 0xFFFF, sum = 0
4715 09:58:13.790964 5, 0xFFFF, sum = 0
4716 09:58:13.791053 6, 0xFFFF, sum = 0
4717 09:58:13.794035 7, 0xFFFF, sum = 0
4718 09:58:13.794121 8, 0x0, sum = 1
4719 09:58:13.797786 9, 0x0, sum = 2
4720 09:58:13.797876 10, 0x0, sum = 3
4721 09:58:13.800909 11, 0x0, sum = 4
4722 09:58:13.800996 best_step = 9
4723 09:58:13.801062
4724 09:58:13.801121 ==
4725 09:58:13.804546 Dram Type= 6, Freq= 0, CH_1, rank 1
4726 09:58:13.808087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4727 09:58:13.810911 ==
4728 09:58:13.811001 RX Vref Scan: 0
4729 09:58:13.811067
4730 09:58:13.814240 RX Vref 0 -> 0, step: 1
4731 09:58:13.814325
4732 09:58:13.817521 RX Delay -163 -> 252, step: 8
4733 09:58:13.820699 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4734 09:58:13.823954 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4735 09:58:13.830856 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4736 09:58:13.834331 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4737 09:58:13.837459 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4738 09:58:13.840762 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4739 09:58:13.843958 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4740 09:58:13.847386 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4741 09:58:13.853873 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4742 09:58:13.857486 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4743 09:58:13.860579 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4744 09:58:13.864366 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4745 09:58:13.870803 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4746 09:58:13.874526 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4747 09:58:13.877396 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4748 09:58:13.880870 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4749 09:58:13.880966 ==
4750 09:58:13.884113 Dram Type= 6, Freq= 0, CH_1, rank 1
4751 09:58:13.890695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4752 09:58:13.890807 ==
4753 09:58:13.890877 DQS Delay:
4754 09:58:13.890939 DQS0 = 0, DQS1 = 0
4755 09:58:13.894056 DQM Delay:
4756 09:58:13.894141 DQM0 = 48, DQM1 = 43
4757 09:58:13.897304 DQ Delay:
4758 09:58:13.900872 DQ0 =56, DQ1 =40, DQ2 =40, DQ3 =44
4759 09:58:13.900963 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =44
4760 09:58:13.904085 DQ8 =32, DQ9 =32, DQ10 =44, DQ11 =36
4761 09:58:13.910378 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =56
4762 09:58:13.910511
4763 09:58:13.910581
4764 09:58:13.917605 [DQSOSCAuto] RK1, (LSB)MR18= 0x5d23, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
4765 09:58:13.920294 CH1 RK1: MR19=808, MR18=5D23
4766 09:58:13.927101 CH1_RK1: MR19=0x808, MR18=0x5D23, DQSOSC=392, MR23=63, INC=170, DEC=113
4767 09:58:13.930346 [RxdqsGatingPostProcess] freq 600
4768 09:58:13.933377 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4769 09:58:13.936858 Pre-setting of DQS Precalculation
4770 09:58:13.943565 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4771 09:58:13.950341 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4772 09:58:13.957331 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4773 09:58:13.957457
4774 09:58:13.957526
4775 09:58:13.960152 [Calibration Summary] 1200 Mbps
4776 09:58:13.960239 CH 0, Rank 0
4777 09:58:13.963225 SW Impedance : PASS
4778 09:58:13.966840 DUTY Scan : NO K
4779 09:58:13.966932 ZQ Calibration : PASS
4780 09:58:13.970127 Jitter Meter : NO K
4781 09:58:13.973437 CBT Training : PASS
4782 09:58:13.973536 Write leveling : PASS
4783 09:58:13.976683 RX DQS gating : PASS
4784 09:58:13.979932 RX DQ/DQS(RDDQC) : PASS
4785 09:58:13.980024 TX DQ/DQS : PASS
4786 09:58:13.983142 RX DATLAT : PASS
4787 09:58:13.986976 RX DQ/DQS(Engine): PASS
4788 09:58:13.987069 TX OE : NO K
4789 09:58:13.987138 All Pass.
4790 09:58:13.990317
4791 09:58:13.990423 CH 0, Rank 1
4792 09:58:13.993357 SW Impedance : PASS
4793 09:58:13.993442 DUTY Scan : NO K
4794 09:58:13.996490 ZQ Calibration : PASS
4795 09:58:13.999923 Jitter Meter : NO K
4796 09:58:14.000010 CBT Training : PASS
4797 09:58:14.003230 Write leveling : PASS
4798 09:58:14.003316 RX DQS gating : PASS
4799 09:58:14.006662 RX DQ/DQS(RDDQC) : PASS
4800 09:58:14.009872 TX DQ/DQS : PASS
4801 09:58:14.009963 RX DATLAT : PASS
4802 09:58:14.012998 RX DQ/DQS(Engine): PASS
4803 09:58:14.016308 TX OE : NO K
4804 09:58:14.016400 All Pass.
4805 09:58:14.016467
4806 09:58:14.016528 CH 1, Rank 0
4807 09:58:14.019734 SW Impedance : PASS
4808 09:58:14.023324 DUTY Scan : NO K
4809 09:58:14.023416 ZQ Calibration : PASS
4810 09:58:14.026280 Jitter Meter : NO K
4811 09:58:14.029680 CBT Training : PASS
4812 09:58:14.029782 Write leveling : PASS
4813 09:58:14.033089 RX DQS gating : PASS
4814 09:58:14.036604 RX DQ/DQS(RDDQC) : PASS
4815 09:58:14.036699 TX DQ/DQS : PASS
4816 09:58:14.039673 RX DATLAT : PASS
4817 09:58:14.043108 RX DQ/DQS(Engine): PASS
4818 09:58:14.043198 TX OE : NO K
4819 09:58:14.043266 All Pass.
4820 09:58:14.046188
4821 09:58:14.046273 CH 1, Rank 1
4822 09:58:14.049520 SW Impedance : PASS
4823 09:58:14.049607 DUTY Scan : NO K
4824 09:58:14.053056 ZQ Calibration : PASS
4825 09:58:14.053146 Jitter Meter : NO K
4826 09:58:14.056216 CBT Training : PASS
4827 09:58:14.059448 Write leveling : PASS
4828 09:58:14.059536 RX DQS gating : PASS
4829 09:58:14.062582 RX DQ/DQS(RDDQC) : PASS
4830 09:58:14.066403 TX DQ/DQS : PASS
4831 09:58:14.066493 RX DATLAT : PASS
4832 09:58:14.069398 RX DQ/DQS(Engine): PASS
4833 09:58:14.072801 TX OE : NO K
4834 09:58:14.072890 All Pass.
4835 09:58:14.072956
4836 09:58:14.076218 DramC Write-DBI off
4837 09:58:14.076317 PER_BANK_REFRESH: Hybrid Mode
4838 09:58:14.079410 TX_TRACKING: ON
4839 09:58:14.086188 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4840 09:58:14.092643 [FAST_K] Save calibration result to emmc
4841 09:58:14.095875 dramc_set_vcore_voltage set vcore to 662500
4842 09:58:14.095975 Read voltage for 933, 3
4843 09:58:14.099280 Vio18 = 0
4844 09:58:14.099368 Vcore = 662500
4845 09:58:14.099434 Vdram = 0
4846 09:58:14.102556 Vddq = 0
4847 09:58:14.102642 Vmddr = 0
4848 09:58:14.105891 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4849 09:58:14.112761 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4850 09:58:14.116432 MEM_TYPE=3, freq_sel=17
4851 09:58:14.119324 sv_algorithm_assistance_LP4_1600
4852 09:58:14.122535 ============ PULL DRAM RESETB DOWN ============
4853 09:58:14.125919 ========== PULL DRAM RESETB DOWN end =========
4854 09:58:14.129268 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4855 09:58:14.132711 ===================================
4856 09:58:14.136212 LPDDR4 DRAM CONFIGURATION
4857 09:58:14.139094 ===================================
4858 09:58:14.142601 EX_ROW_EN[0] = 0x0
4859 09:58:14.142697 EX_ROW_EN[1] = 0x0
4860 09:58:14.145750 LP4Y_EN = 0x0
4861 09:58:14.145869 WORK_FSP = 0x0
4862 09:58:14.149267 WL = 0x3
4863 09:58:14.149356 RL = 0x3
4864 09:58:14.152513 BL = 0x2
4865 09:58:14.152603 RPST = 0x0
4866 09:58:14.155827 RD_PRE = 0x0
4867 09:58:14.155916 WR_PRE = 0x1
4868 09:58:14.159151 WR_PST = 0x0
4869 09:58:14.162355 DBI_WR = 0x0
4870 09:58:14.162485 DBI_RD = 0x0
4871 09:58:14.165812 OTF = 0x1
4872 09:58:14.169116 ===================================
4873 09:58:14.172968 ===================================
4874 09:58:14.173066 ANA top config
4875 09:58:14.175849 ===================================
4876 09:58:14.179029 DLL_ASYNC_EN = 0
4877 09:58:14.179128 ALL_SLAVE_EN = 1
4878 09:58:14.182587 NEW_RANK_MODE = 1
4879 09:58:14.185962 DLL_IDLE_MODE = 1
4880 09:58:14.189317 LP45_APHY_COMB_EN = 1
4881 09:58:14.192681 TX_ODT_DIS = 1
4882 09:58:14.192780 NEW_8X_MODE = 1
4883 09:58:14.196179 ===================================
4884 09:58:14.199395 ===================================
4885 09:58:14.202204 data_rate = 1866
4886 09:58:14.205933 CKR = 1
4887 09:58:14.208880 DQ_P2S_RATIO = 8
4888 09:58:14.212359 ===================================
4889 09:58:14.215459 CA_P2S_RATIO = 8
4890 09:58:14.219164 DQ_CA_OPEN = 0
4891 09:58:14.219260 DQ_SEMI_OPEN = 0
4892 09:58:14.222351 CA_SEMI_OPEN = 0
4893 09:58:14.225406 CA_FULL_RATE = 0
4894 09:58:14.228861 DQ_CKDIV4_EN = 1
4895 09:58:14.231933 CA_CKDIV4_EN = 1
4896 09:58:14.235570 CA_PREDIV_EN = 0
4897 09:58:14.235674 PH8_DLY = 0
4898 09:58:14.239146 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4899 09:58:14.242680 DQ_AAMCK_DIV = 4
4900 09:58:14.245559 CA_AAMCK_DIV = 4
4901 09:58:14.248852 CA_ADMCK_DIV = 4
4902 09:58:14.252108 DQ_TRACK_CA_EN = 0
4903 09:58:14.252208 CA_PICK = 933
4904 09:58:14.255345 CA_MCKIO = 933
4905 09:58:14.258638 MCKIO_SEMI = 0
4906 09:58:14.261883 PLL_FREQ = 3732
4907 09:58:14.265588 DQ_UI_PI_RATIO = 32
4908 09:58:14.268615 CA_UI_PI_RATIO = 0
4909 09:58:14.271920 ===================================
4910 09:58:14.275561 ===================================
4911 09:58:14.275661 memory_type:LPDDR4
4912 09:58:14.278680 GP_NUM : 10
4913 09:58:14.282251 SRAM_EN : 1
4914 09:58:14.282365 MD32_EN : 0
4915 09:58:14.285549 ===================================
4916 09:58:14.288755 [ANA_INIT] >>>>>>>>>>>>>>
4917 09:58:14.291905 <<<<<< [CONFIGURE PHASE]: ANA_TX
4918 09:58:14.295124 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4919 09:58:14.298650 ===================================
4920 09:58:14.301875 data_rate = 1866,PCW = 0X8f00
4921 09:58:14.305136 ===================================
4922 09:58:14.308356 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4923 09:58:14.312108 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4924 09:58:14.318482 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4925 09:58:14.322101 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4926 09:58:14.325385 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4927 09:58:14.332092 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4928 09:58:14.332234 [ANA_INIT] flow start
4929 09:58:14.335119 [ANA_INIT] PLL >>>>>>>>
4930 09:58:14.335244 [ANA_INIT] PLL <<<<<<<<
4931 09:58:14.338321 [ANA_INIT] MIDPI >>>>>>>>
4932 09:58:14.341939 [ANA_INIT] MIDPI <<<<<<<<
4933 09:58:14.345346 [ANA_INIT] DLL >>>>>>>>
4934 09:58:14.345476 [ANA_INIT] flow end
4935 09:58:14.348395 ============ LP4 DIFF to SE enter ============
4936 09:58:14.355352 ============ LP4 DIFF to SE exit ============
4937 09:58:14.355481 [ANA_INIT] <<<<<<<<<<<<<
4938 09:58:14.358423 [Flow] Enable top DCM control >>>>>
4939 09:58:14.361979 [Flow] Enable top DCM control <<<<<
4940 09:58:14.365258 Enable DLL master slave shuffle
4941 09:58:14.371894 ==============================================================
4942 09:58:14.372004 Gating Mode config
4943 09:58:14.378369 ==============================================================
4944 09:58:14.381555 Config description:
4945 09:58:14.391611 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4946 09:58:14.398310 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4947 09:58:14.401841 SELPH_MODE 0: By rank 1: By Phase
4948 09:58:14.408477 ==============================================================
4949 09:58:14.411678 GAT_TRACK_EN = 1
4950 09:58:14.411783 RX_GATING_MODE = 2
4951 09:58:14.415138 RX_GATING_TRACK_MODE = 2
4952 09:58:14.418526 SELPH_MODE = 1
4953 09:58:14.421656 PICG_EARLY_EN = 1
4954 09:58:14.425130 VALID_LAT_VALUE = 1
4955 09:58:14.431648 ==============================================================
4956 09:58:14.434913 Enter into Gating configuration >>>>
4957 09:58:14.438254 Exit from Gating configuration <<<<
4958 09:58:14.441493 Enter into DVFS_PRE_config >>>>>
4959 09:58:14.451415 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4960 09:58:14.454914 Exit from DVFS_PRE_config <<<<<
4961 09:58:14.458286 Enter into PICG configuration >>>>
4962 09:58:14.461547 Exit from PICG configuration <<<<
4963 09:58:14.465220 [RX_INPUT] configuration >>>>>
4964 09:58:14.465315 [RX_INPUT] configuration <<<<<
4965 09:58:14.471707 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4966 09:58:14.478223 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4967 09:58:14.481840 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4968 09:58:14.488395 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4969 09:58:14.494832 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4970 09:58:14.502039 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4971 09:58:14.504749 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4972 09:58:14.508116 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4973 09:58:14.514962 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4974 09:58:14.518020 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4975 09:58:14.521801 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4976 09:58:14.528143 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4977 09:58:14.531399 ===================================
4978 09:58:14.531518 LPDDR4 DRAM CONFIGURATION
4979 09:58:14.534695 ===================================
4980 09:58:14.538212 EX_ROW_EN[0] = 0x0
4981 09:58:14.538307 EX_ROW_EN[1] = 0x0
4982 09:58:14.541558 LP4Y_EN = 0x0
4983 09:58:14.541647 WORK_FSP = 0x0
4984 09:58:14.544483 WL = 0x3
4985 09:58:14.547851 RL = 0x3
4986 09:58:14.547952 BL = 0x2
4987 09:58:14.551253 RPST = 0x0
4988 09:58:14.551346 RD_PRE = 0x0
4989 09:58:14.555005 WR_PRE = 0x1
4990 09:58:14.555098 WR_PST = 0x0
4991 09:58:14.557891 DBI_WR = 0x0
4992 09:58:14.557979 DBI_RD = 0x0
4993 09:58:14.560965 OTF = 0x1
4994 09:58:14.564616 ===================================
4995 09:58:14.568014 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4996 09:58:14.571170 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4997 09:58:14.577634 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4998 09:58:14.581067 ===================================
4999 09:58:14.581177 LPDDR4 DRAM CONFIGURATION
5000 09:58:14.584461 ===================================
5001 09:58:14.587673 EX_ROW_EN[0] = 0x10
5002 09:58:14.587770 EX_ROW_EN[1] = 0x0
5003 09:58:14.591276 LP4Y_EN = 0x0
5004 09:58:14.591366 WORK_FSP = 0x0
5005 09:58:14.594723 WL = 0x3
5006 09:58:14.594813 RL = 0x3
5007 09:58:14.597545 BL = 0x2
5008 09:58:14.601129 RPST = 0x0
5009 09:58:14.601223 RD_PRE = 0x0
5010 09:58:14.604523 WR_PRE = 0x1
5011 09:58:14.604614 WR_PST = 0x0
5012 09:58:14.607581 DBI_WR = 0x0
5013 09:58:14.607671 DBI_RD = 0x0
5014 09:58:14.611514 OTF = 0x1
5015 09:58:14.614281 ===================================
5016 09:58:14.620600 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5017 09:58:14.624401 nWR fixed to 30
5018 09:58:14.624514 [ModeRegInit_LP4] CH0 RK0
5019 09:58:14.627599 [ModeRegInit_LP4] CH0 RK1
5020 09:58:14.630440 [ModeRegInit_LP4] CH1 RK0
5021 09:58:14.630537 [ModeRegInit_LP4] CH1 RK1
5022 09:58:14.634024 match AC timing 9
5023 09:58:14.637458 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5024 09:58:14.640487 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5025 09:58:14.647372 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5026 09:58:14.651205 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5027 09:58:14.657556 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5028 09:58:14.657683 ==
5029 09:58:14.660797 Dram Type= 6, Freq= 0, CH_0, rank 0
5030 09:58:14.663496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5031 09:58:14.663593 ==
5032 09:58:14.670434 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5033 09:58:14.677370 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5034 09:58:14.680217 [CA 0] Center 37 (7~68) winsize 62
5035 09:58:14.683734 [CA 1] Center 38 (8~68) winsize 61
5036 09:58:14.686764 [CA 2] Center 35 (5~66) winsize 62
5037 09:58:14.690008 [CA 3] Center 34 (4~65) winsize 62
5038 09:58:14.693372 [CA 4] Center 34 (4~65) winsize 62
5039 09:58:14.693487 [CA 5] Center 33 (3~64) winsize 62
5040 09:58:14.697073
5041 09:58:14.700204 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5042 09:58:14.700299
5043 09:58:14.703667 [CATrainingPosCal] consider 1 rank data
5044 09:58:14.707072 u2DelayCellTimex100 = 270/100 ps
5045 09:58:14.710026 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5046 09:58:14.713597 CA1 delay=38 (8~68),Diff = 5 PI (31 cell)
5047 09:58:14.716857 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5048 09:58:14.719933 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5049 09:58:14.723190 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5050 09:58:14.726962 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5051 09:58:14.727062
5052 09:58:14.730366 CA PerBit enable=1, Macro0, CA PI delay=33
5053 09:58:14.730489
5054 09:58:14.733255 [CBTSetCACLKResult] CA Dly = 33
5055 09:58:14.736492 CS Dly: 7 (0~38)
5056 09:58:14.736586 ==
5057 09:58:14.739881 Dram Type= 6, Freq= 0, CH_0, rank 1
5058 09:58:14.743213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5059 09:58:14.743307 ==
5060 09:58:14.749923 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5061 09:58:14.756618 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5062 09:58:14.759819 [CA 0] Center 38 (8~69) winsize 62
5063 09:58:14.763165 [CA 1] Center 38 (8~69) winsize 62
5064 09:58:14.766677 [CA 2] Center 36 (6~66) winsize 61
5065 09:58:14.769735 [CA 3] Center 35 (5~66) winsize 62
5066 09:58:14.773106 [CA 4] Center 34 (4~65) winsize 62
5067 09:58:14.776442 [CA 5] Center 33 (3~64) winsize 62
5068 09:58:14.776538
5069 09:58:14.779960 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5070 09:58:14.780054
5071 09:58:14.783072 [CATrainingPosCal] consider 2 rank data
5072 09:58:14.786680 u2DelayCellTimex100 = 270/100 ps
5073 09:58:14.790489 CA0 delay=38 (8~68),Diff = 5 PI (31 cell)
5074 09:58:14.793350 CA1 delay=38 (8~68),Diff = 5 PI (31 cell)
5075 09:58:14.796621 CA2 delay=36 (6~66),Diff = 3 PI (18 cell)
5076 09:58:14.799836 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5077 09:58:14.803285 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5078 09:58:14.806354 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5079 09:58:14.806491
5080 09:58:14.813154 CA PerBit enable=1, Macro0, CA PI delay=33
5081 09:58:14.813265
5082 09:58:14.813336 [CBTSetCACLKResult] CA Dly = 33
5083 09:58:14.816582 CS Dly: 7 (0~39)
5084 09:58:14.816675
5085 09:58:14.819754 ----->DramcWriteLeveling(PI) begin...
5086 09:58:14.819846 ==
5087 09:58:14.823842 Dram Type= 6, Freq= 0, CH_0, rank 0
5088 09:58:14.826706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5089 09:58:14.826798 ==
5090 09:58:14.830130 Write leveling (Byte 0): 32 => 32
5091 09:58:14.833301 Write leveling (Byte 1): 32 => 32
5092 09:58:14.836456 DramcWriteLeveling(PI) end<-----
5093 09:58:14.836554
5094 09:58:14.836621 ==
5095 09:58:14.839696 Dram Type= 6, Freq= 0, CH_0, rank 0
5096 09:58:14.843035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5097 09:58:14.846349 ==
5098 09:58:14.846493 [Gating] SW mode calibration
5099 09:58:14.853103 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5100 09:58:14.859985 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5101 09:58:14.863146 0 14 0 | B1->B0 | 3232 3434 | 0 1 | (1 1) (1 1)
5102 09:58:14.870087 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5103 09:58:14.873116 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 09:58:14.876836 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 09:58:14.882927 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 09:58:14.886357 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 09:58:14.889820 0 14 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
5108 09:58:14.896443 0 14 28 | B1->B0 | 3232 2727 | 0 0 | (1 0) (1 1)
5109 09:58:14.899638 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5110 09:58:14.902996 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 09:58:14.909904 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 09:58:14.912996 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 09:58:14.916613 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 09:58:14.919621 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 09:58:14.926350 0 15 24 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
5116 09:58:14.929526 0 15 28 | B1->B0 | 2828 4545 | 0 0 | (0 0) (0 0)
5117 09:58:14.933463 1 0 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5118 09:58:14.939632 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 09:58:14.942887 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 09:58:14.946348 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 09:58:14.953132 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 09:58:14.956458 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 09:58:14.960244 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 09:58:14.966293 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5125 09:58:14.969882 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5126 09:58:14.973293 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 09:58:14.979559 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 09:58:14.982842 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 09:58:14.986049 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 09:58:14.992792 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 09:58:14.996130 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 09:58:14.999606 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 09:58:15.006104 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 09:58:15.009426 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 09:58:15.012740 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 09:58:15.019830 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 09:58:15.022749 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 09:58:15.026176 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 09:58:15.032842 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5140 09:58:15.036522 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5141 09:58:15.039414 Total UI for P1: 0, mck2ui 16
5142 09:58:15.043082 best dqsien dly found for B0: ( 1, 2, 24)
5143 09:58:15.046502 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5144 09:58:15.049677 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 09:58:15.052756 Total UI for P1: 0, mck2ui 16
5146 09:58:15.055938 best dqsien dly found for B1: ( 1, 2, 30)
5147 09:58:15.059592 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5148 09:58:15.062905 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5149 09:58:15.066111
5150 09:58:15.069590 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5151 09:58:15.072565 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5152 09:58:15.076145 [Gating] SW calibration Done
5153 09:58:15.076246 ==
5154 09:58:15.079496 Dram Type= 6, Freq= 0, CH_0, rank 0
5155 09:58:15.082943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5156 09:58:15.083042 ==
5157 09:58:15.083110 RX Vref Scan: 0
5158 09:58:15.086146
5159 09:58:15.086235 RX Vref 0 -> 0, step: 1
5160 09:58:15.086306
5161 09:58:15.089243 RX Delay -80 -> 252, step: 8
5162 09:58:15.092400 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5163 09:58:15.095982 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5164 09:58:15.102376 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5165 09:58:15.105751 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5166 09:58:15.108992 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5167 09:58:15.112234 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5168 09:58:15.115645 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5169 09:58:15.119056 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5170 09:58:15.125930 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5171 09:58:15.129154 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5172 09:58:15.132308 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5173 09:58:15.136308 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5174 09:58:15.139184 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5175 09:58:15.142222 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5176 09:58:15.148933 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5177 09:58:15.152462 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5178 09:58:15.152568 ==
5179 09:58:15.155463 Dram Type= 6, Freq= 0, CH_0, rank 0
5180 09:58:15.159258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5181 09:58:15.159359 ==
5182 09:58:15.162105 DQS Delay:
5183 09:58:15.162194 DQS0 = 0, DQS1 = 0
5184 09:58:15.162262 DQM Delay:
5185 09:58:15.165579 DQM0 = 105, DQM1 = 90
5186 09:58:15.165666 DQ Delay:
5187 09:58:15.168786 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5188 09:58:15.172028 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5189 09:58:15.175851 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5190 09:58:15.178830 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5191 09:58:15.178923
5192 09:58:15.178992
5193 09:58:15.179054 ==
5194 09:58:15.181986 Dram Type= 6, Freq= 0, CH_0, rank 0
5195 09:58:15.188908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5196 09:58:15.189028 ==
5197 09:58:15.189097
5198 09:58:15.189159
5199 09:58:15.189219 TX Vref Scan disable
5200 09:58:15.192577 == TX Byte 0 ==
5201 09:58:15.195982 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5202 09:58:15.202605 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5203 09:58:15.202727 == TX Byte 1 ==
5204 09:58:15.205998 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5205 09:58:15.212617 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5206 09:58:15.212740 ==
5207 09:58:15.215784 Dram Type= 6, Freq= 0, CH_0, rank 0
5208 09:58:15.219462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5209 09:58:15.219560 ==
5210 09:58:15.219630
5211 09:58:15.219692
5212 09:58:15.222438 TX Vref Scan disable
5213 09:58:15.222527 == TX Byte 0 ==
5214 09:58:15.229012 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5215 09:58:15.232609 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5216 09:58:15.232728 == TX Byte 1 ==
5217 09:58:15.238884 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5218 09:58:15.242340 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5219 09:58:15.242465
5220 09:58:15.242533 [DATLAT]
5221 09:58:15.245638 Freq=933, CH0 RK0
5222 09:58:15.245724
5223 09:58:15.245791 DATLAT Default: 0xd
5224 09:58:15.249257 0, 0xFFFF, sum = 0
5225 09:58:15.249347 1, 0xFFFF, sum = 0
5226 09:58:15.252354 2, 0xFFFF, sum = 0
5227 09:58:15.252442 3, 0xFFFF, sum = 0
5228 09:58:15.255823 4, 0xFFFF, sum = 0
5229 09:58:15.255912 5, 0xFFFF, sum = 0
5230 09:58:15.258942 6, 0xFFFF, sum = 0
5231 09:58:15.262162 7, 0xFFFF, sum = 0
5232 09:58:15.262254 8, 0xFFFF, sum = 0
5233 09:58:15.265622 9, 0xFFFF, sum = 0
5234 09:58:15.265711 10, 0x0, sum = 1
5235 09:58:15.265779 11, 0x0, sum = 2
5236 09:58:15.269066 12, 0x0, sum = 3
5237 09:58:15.269152 13, 0x0, sum = 4
5238 09:58:15.272452 best_step = 11
5239 09:58:15.272539
5240 09:58:15.272604 ==
5241 09:58:15.275563 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 09:58:15.279500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 09:58:15.279591 ==
5244 09:58:15.282292 RX Vref Scan: 1
5245 09:58:15.282408
5246 09:58:15.282477 RX Vref 0 -> 0, step: 1
5247 09:58:15.282539
5248 09:58:15.285880 RX Delay -53 -> 252, step: 4
5249 09:58:15.285966
5250 09:58:15.289029 Set Vref, RX VrefLevel [Byte0]: 58
5251 09:58:15.292393 [Byte1]: 49
5252 09:58:15.296625
5253 09:58:15.296730 Final RX Vref Byte 0 = 58 to rank0
5254 09:58:15.299854 Final RX Vref Byte 1 = 49 to rank0
5255 09:58:15.303163 Final RX Vref Byte 0 = 58 to rank1
5256 09:58:15.306353 Final RX Vref Byte 1 = 49 to rank1==
5257 09:58:15.309707 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 09:58:15.316374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 09:58:15.316497 ==
5260 09:58:15.316566 DQS Delay:
5261 09:58:15.316628 DQS0 = 0, DQS1 = 0
5262 09:58:15.319743 DQM Delay:
5263 09:58:15.319833 DQM0 = 107, DQM1 = 91
5264 09:58:15.323123 DQ Delay:
5265 09:58:15.326311 DQ0 =108, DQ1 =108, DQ2 =104, DQ3 =106
5266 09:58:15.329850 DQ4 =108, DQ5 =98, DQ6 =116, DQ7 =114
5267 09:58:15.333052 DQ8 =84, DQ9 =78, DQ10 =92, DQ11 =90
5268 09:58:15.336460 DQ12 =96, DQ13 =94, DQ14 =102, DQ15 =98
5269 09:58:15.336565
5270 09:58:15.336633
5271 09:58:15.342902 [DQSOSCAuto] RK0, (LSB)MR18= 0x2420, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
5272 09:58:15.346533 CH0 RK0: MR19=505, MR18=2420
5273 09:58:15.352778 CH0_RK0: MR19=0x505, MR18=0x2420, DQSOSC=410, MR23=63, INC=64, DEC=42
5274 09:58:15.352905
5275 09:58:15.356253 ----->DramcWriteLeveling(PI) begin...
5276 09:58:15.356350 ==
5277 09:58:15.359389 Dram Type= 6, Freq= 0, CH_0, rank 1
5278 09:58:15.362879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5279 09:58:15.362975 ==
5280 09:58:15.366090 Write leveling (Byte 0): 33 => 33
5281 09:58:15.369847 Write leveling (Byte 1): 29 => 29
5282 09:58:15.372859 DramcWriteLeveling(PI) end<-----
5283 09:58:15.372971
5284 09:58:15.373091 ==
5285 09:58:15.376087 Dram Type= 6, Freq= 0, CH_0, rank 1
5286 09:58:15.379579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 09:58:15.383169 ==
5288 09:58:15.383265 [Gating] SW mode calibration
5289 09:58:15.392541 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5290 09:58:15.396080 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5291 09:58:15.399263 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5292 09:58:15.406202 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5293 09:58:15.409250 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5294 09:58:15.412664 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 09:58:15.419051 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 09:58:15.422411 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 09:58:15.425635 0 14 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
5298 09:58:15.432383 0 14 28 | B1->B0 | 2d2d 2626 | 0 0 | (0 0) (0 0)
5299 09:58:15.435834 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5300 09:58:15.439188 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5301 09:58:15.445592 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5302 09:58:15.448804 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 09:58:15.452349 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 09:58:15.458796 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 09:58:15.462532 0 15 24 | B1->B0 | 2828 3030 | 0 0 | (0 0) (0 0)
5306 09:58:15.465456 0 15 28 | B1->B0 | 3a3a 4040 | 0 1 | (0 0) (1 1)
5307 09:58:15.472541 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5308 09:58:15.475890 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5309 09:58:15.478670 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 09:58:15.485458 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 09:58:15.488932 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 09:58:15.492276 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 09:58:15.498550 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 09:58:15.501757 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5315 09:58:15.505394 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 09:58:15.511703 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 09:58:15.515392 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 09:58:15.518546 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 09:58:15.525077 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 09:58:15.528615 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 09:58:15.531857 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 09:58:15.535241 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 09:58:15.541926 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 09:58:15.545235 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 09:58:15.548430 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 09:58:15.555082 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 09:58:15.558474 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 09:58:15.561522 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 09:58:15.568647 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 09:58:15.572328 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 09:58:15.574792 Total UI for P1: 0, mck2ui 16
5332 09:58:15.578677 best dqsien dly found for B0: ( 1, 2, 26)
5333 09:58:15.581568 Total UI for P1: 0, mck2ui 16
5334 09:58:15.584762 best dqsien dly found for B1: ( 1, 2, 26)
5335 09:58:15.588164 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5336 09:58:15.591866 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5337 09:58:15.591967
5338 09:58:15.595225 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5339 09:58:15.598167 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5340 09:58:15.601612 [Gating] SW calibration Done
5341 09:58:15.601706 ==
5342 09:58:15.605056 Dram Type= 6, Freq= 0, CH_0, rank 1
5343 09:58:15.611884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5344 09:58:15.612001 ==
5345 09:58:15.612071 RX Vref Scan: 0
5346 09:58:15.612134
5347 09:58:15.614770 RX Vref 0 -> 0, step: 1
5348 09:58:15.614857
5349 09:58:15.618049 RX Delay -80 -> 252, step: 8
5350 09:58:15.621530 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5351 09:58:15.624695 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5352 09:58:15.628274 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5353 09:58:15.631387 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5354 09:58:15.638537 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5355 09:58:15.641370 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5356 09:58:15.645263 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5357 09:58:15.648034 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5358 09:58:15.651569 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5359 09:58:15.654733 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5360 09:58:15.661440 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5361 09:58:15.664801 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5362 09:58:15.668263 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5363 09:58:15.671731 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5364 09:58:15.674594 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5365 09:58:15.678190 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5366 09:58:15.678284 ==
5367 09:58:15.681357 Dram Type= 6, Freq= 0, CH_0, rank 1
5368 09:58:15.687903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5369 09:58:15.688010 ==
5370 09:58:15.688077 DQS Delay:
5371 09:58:15.691410 DQS0 = 0, DQS1 = 0
5372 09:58:15.691497 DQM Delay:
5373 09:58:15.694806 DQM0 = 105, DQM1 = 90
5374 09:58:15.694892 DQ Delay:
5375 09:58:15.697780 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5376 09:58:15.701689 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5377 09:58:15.704671 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5378 09:58:15.707918 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5379 09:58:15.708007
5380 09:58:15.708074
5381 09:58:15.708135 ==
5382 09:58:15.711155 Dram Type= 6, Freq= 0, CH_0, rank 1
5383 09:58:15.714351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5384 09:58:15.714457 ==
5385 09:58:15.714527
5386 09:58:15.717717
5387 09:58:15.717802 TX Vref Scan disable
5388 09:58:15.720909 == TX Byte 0 ==
5389 09:58:15.724413 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5390 09:58:15.727947 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5391 09:58:15.730873 == TX Byte 1 ==
5392 09:58:15.734264 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5393 09:58:15.738044 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5394 09:58:15.738144 ==
5395 09:58:15.741016 Dram Type= 6, Freq= 0, CH_0, rank 1
5396 09:58:15.747604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5397 09:58:15.747715 ==
5398 09:58:15.747782
5399 09:58:15.747844
5400 09:58:15.747902 TX Vref Scan disable
5401 09:58:15.751833 == TX Byte 0 ==
5402 09:58:15.755476 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5403 09:58:15.761666 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5404 09:58:15.761775 == TX Byte 1 ==
5405 09:58:15.764850 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5406 09:58:15.771614 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5407 09:58:15.771723
5408 09:58:15.771790 [DATLAT]
5409 09:58:15.771853 Freq=933, CH0 RK1
5410 09:58:15.771914
5411 09:58:15.774928 DATLAT Default: 0xb
5412 09:58:15.775016 0, 0xFFFF, sum = 0
5413 09:58:15.778432 1, 0xFFFF, sum = 0
5414 09:58:15.778520 2, 0xFFFF, sum = 0
5415 09:58:15.781774 3, 0xFFFF, sum = 0
5416 09:58:15.784733 4, 0xFFFF, sum = 0
5417 09:58:15.784826 5, 0xFFFF, sum = 0
5418 09:58:15.788461 6, 0xFFFF, sum = 0
5419 09:58:15.788552 7, 0xFFFF, sum = 0
5420 09:58:15.791441 8, 0xFFFF, sum = 0
5421 09:58:15.791532 9, 0xFFFF, sum = 0
5422 09:58:15.794732 10, 0x0, sum = 1
5423 09:58:15.794821 11, 0x0, sum = 2
5424 09:58:15.798067 12, 0x0, sum = 3
5425 09:58:15.798154 13, 0x0, sum = 4
5426 09:58:15.798221 best_step = 11
5427 09:58:15.798283
5428 09:58:15.801425 ==
5429 09:58:15.804787 Dram Type= 6, Freq= 0, CH_0, rank 1
5430 09:58:15.808305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5431 09:58:15.808398 ==
5432 09:58:15.808465 RX Vref Scan: 0
5433 09:58:15.808527
5434 09:58:15.811420 RX Vref 0 -> 0, step: 1
5435 09:58:15.811507
5436 09:58:15.814807 RX Delay -53 -> 252, step: 4
5437 09:58:15.818101 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5438 09:58:15.824664 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5439 09:58:15.828035 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5440 09:58:15.831126 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5441 09:58:15.834543 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5442 09:58:15.838122 iDelay=199, Bit 5, Center 98 (15 ~ 182) 168
5443 09:58:15.844532 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5444 09:58:15.848193 iDelay=199, Bit 7, Center 110 (23 ~ 198) 176
5445 09:58:15.851248 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5446 09:58:15.854500 iDelay=199, Bit 9, Center 78 (-5 ~ 162) 168
5447 09:58:15.857930 iDelay=199, Bit 10, Center 92 (7 ~ 178) 172
5448 09:58:15.861717 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5449 09:58:15.867915 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5450 09:58:15.871467 iDelay=199, Bit 13, Center 96 (15 ~ 178) 164
5451 09:58:15.874721 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5452 09:58:15.878006 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5453 09:58:15.878098 ==
5454 09:58:15.881514 Dram Type= 6, Freq= 0, CH_0, rank 1
5455 09:58:15.887828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5456 09:58:15.887941 ==
5457 09:58:15.888008 DQS Delay:
5458 09:58:15.888070 DQS0 = 0, DQS1 = 0
5459 09:58:15.891506 DQM Delay:
5460 09:58:15.891593 DQM0 = 104, DQM1 = 92
5461 09:58:15.894718 DQ Delay:
5462 09:58:15.897835 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =98
5463 09:58:15.901146 DQ4 =104, DQ5 =98, DQ6 =112, DQ7 =110
5464 09:58:15.904996 DQ8 =86, DQ9 =78, DQ10 =92, DQ11 =92
5465 09:58:15.907824 DQ12 =96, DQ13 =96, DQ14 =100, DQ15 =98
5466 09:58:15.907912
5467 09:58:15.907978
5468 09:58:15.914549 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b0b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 408 ps
5469 09:58:15.918041 CH0 RK1: MR19=505, MR18=2B0B
5470 09:58:15.924617 CH0_RK1: MR19=0x505, MR18=0x2B0B, DQSOSC=408, MR23=63, INC=65, DEC=43
5471 09:58:15.927812 [RxdqsGatingPostProcess] freq 933
5472 09:58:15.931083 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5473 09:58:15.934589 best DQS0 dly(2T, 0.5T) = (0, 10)
5474 09:58:15.937927 best DQS1 dly(2T, 0.5T) = (0, 10)
5475 09:58:15.941027 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5476 09:58:15.944553 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5477 09:58:15.947640 best DQS0 dly(2T, 0.5T) = (0, 10)
5478 09:58:15.951138 best DQS1 dly(2T, 0.5T) = (0, 10)
5479 09:58:15.954129 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5480 09:58:15.957858 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5481 09:58:15.961100 Pre-setting of DQS Precalculation
5482 09:58:15.964482 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5483 09:58:15.967728 ==
5484 09:58:15.967822 Dram Type= 6, Freq= 0, CH_1, rank 0
5485 09:58:15.974088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5486 09:58:15.974192 ==
5487 09:58:15.977806 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5488 09:58:15.984246 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5489 09:58:15.987600 [CA 0] Center 37 (7~68) winsize 62
5490 09:58:15.990965 [CA 1] Center 37 (7~68) winsize 62
5491 09:58:15.994248 [CA 2] Center 35 (6~65) winsize 60
5492 09:58:15.997621 [CA 3] Center 35 (5~65) winsize 61
5493 09:58:16.001210 [CA 4] Center 35 (5~65) winsize 61
5494 09:58:16.004226 [CA 5] Center 34 (4~64) winsize 61
5495 09:58:16.004316
5496 09:58:16.007874 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5497 09:58:16.007963
5498 09:58:16.010921 [CATrainingPosCal] consider 1 rank data
5499 09:58:16.014432 u2DelayCellTimex100 = 270/100 ps
5500 09:58:16.017621 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5501 09:58:16.020802 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5502 09:58:16.027754 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5503 09:58:16.030954 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5504 09:58:16.034583 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5505 09:58:16.037763 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5506 09:58:16.037875
5507 09:58:16.041197 CA PerBit enable=1, Macro0, CA PI delay=34
5508 09:58:16.041287
5509 09:58:16.044056 [CBTSetCACLKResult] CA Dly = 34
5510 09:58:16.044141 CS Dly: 6 (0~37)
5511 09:58:16.047489 ==
5512 09:58:16.050943 Dram Type= 6, Freq= 0, CH_1, rank 1
5513 09:58:16.054225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5514 09:58:16.054340 ==
5515 09:58:16.057481 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5516 09:58:16.063955 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5517 09:58:16.067673 [CA 0] Center 38 (8~68) winsize 61
5518 09:58:16.071068 [CA 1] Center 38 (7~69) winsize 63
5519 09:58:16.074235 [CA 2] Center 36 (6~66) winsize 61
5520 09:58:16.077707 [CA 3] Center 35 (5~65) winsize 61
5521 09:58:16.081259 [CA 4] Center 35 (5~65) winsize 61
5522 09:58:16.084341 [CA 5] Center 34 (5~64) winsize 60
5523 09:58:16.084439
5524 09:58:16.087753 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5525 09:58:16.087839
5526 09:58:16.091227 [CATrainingPosCal] consider 2 rank data
5527 09:58:16.094225 u2DelayCellTimex100 = 270/100 ps
5528 09:58:16.097558 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5529 09:58:16.104170 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5530 09:58:16.107865 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5531 09:58:16.111031 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5532 09:58:16.114300 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5533 09:58:16.117809 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5534 09:58:16.117898
5535 09:58:16.121075 CA PerBit enable=1, Macro0, CA PI delay=34
5536 09:58:16.121159
5537 09:58:16.124434 [CBTSetCACLKResult] CA Dly = 34
5538 09:58:16.124521 CS Dly: 7 (0~39)
5539 09:58:16.124586
5540 09:58:16.127691 ----->DramcWriteLeveling(PI) begin...
5541 09:58:16.131051 ==
5542 09:58:16.135054 Dram Type= 6, Freq= 0, CH_1, rank 0
5543 09:58:16.137794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5544 09:58:16.137890 ==
5545 09:58:16.141088 Write leveling (Byte 0): 24 => 24
5546 09:58:16.144236 Write leveling (Byte 1): 30 => 30
5547 09:58:16.147767 DramcWriteLeveling(PI) end<-----
5548 09:58:16.147948
5549 09:58:16.148018 ==
5550 09:58:16.151068 Dram Type= 6, Freq= 0, CH_1, rank 0
5551 09:58:16.154326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5552 09:58:16.154502 ==
5553 09:58:16.157530 [Gating] SW mode calibration
5554 09:58:16.163917 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5555 09:58:16.170949 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5556 09:58:16.174045 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5557 09:58:16.177420 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5558 09:58:16.180881 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5559 09:58:16.187452 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 09:58:16.190522 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 09:58:16.193891 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5562 09:58:16.200677 0 14 24 | B1->B0 | 3333 3030 | 0 0 | (0 0) (0 1)
5563 09:58:16.204428 0 14 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5564 09:58:16.207334 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5565 09:58:16.214184 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5566 09:58:16.217402 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 09:58:16.220824 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 09:58:16.227143 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 09:58:16.230639 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 09:58:16.233969 0 15 24 | B1->B0 | 2727 2f2f | 0 0 | (0 0) (0 0)
5571 09:58:16.240797 0 15 28 | B1->B0 | 3d3d 4242 | 0 1 | (1 1) (0 0)
5572 09:58:16.244092 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5573 09:58:16.247488 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 09:58:16.253939 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 09:58:16.257210 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 09:58:16.260916 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 09:58:16.267156 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 09:58:16.270495 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5579 09:58:16.273780 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 09:58:16.280625 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 09:58:16.283852 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 09:58:16.287200 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 09:58:16.293851 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 09:58:16.297449 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 09:58:16.300536 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 09:58:16.307008 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 09:58:16.310376 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 09:58:16.313843 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 09:58:16.317156 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 09:58:16.323850 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 09:58:16.327200 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 09:58:16.330955 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 09:58:16.337432 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 09:58:16.340430 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5595 09:58:16.343658 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 09:58:16.347161 Total UI for P1: 0, mck2ui 16
5597 09:58:16.350708 best dqsien dly found for B0: ( 1, 2, 24)
5598 09:58:16.353588 Total UI for P1: 0, mck2ui 16
5599 09:58:16.356795 best dqsien dly found for B1: ( 1, 2, 24)
5600 09:58:16.360545 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5601 09:58:16.363720 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5602 09:58:16.363817
5603 09:58:16.370035 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5604 09:58:16.373817 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5605 09:58:16.376904 [Gating] SW calibration Done
5606 09:58:16.376998 ==
5607 09:58:16.380670 Dram Type= 6, Freq= 0, CH_1, rank 0
5608 09:58:16.383728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5609 09:58:16.383824 ==
5610 09:58:16.383893 RX Vref Scan: 0
5611 09:58:16.383955
5612 09:58:16.386663 RX Vref 0 -> 0, step: 1
5613 09:58:16.386751
5614 09:58:16.390317 RX Delay -80 -> 252, step: 8
5615 09:58:16.393497 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5616 09:58:16.396663 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5617 09:58:16.400036 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5618 09:58:16.406420 iDelay=208, Bit 3, Center 107 (24 ~ 191) 168
5619 09:58:16.409787 iDelay=208, Bit 4, Center 107 (24 ~ 191) 168
5620 09:58:16.413391 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5621 09:58:16.417331 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5622 09:58:16.420310 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5623 09:58:16.426630 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5624 09:58:16.430126 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5625 09:58:16.433577 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5626 09:58:16.436843 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5627 09:58:16.439846 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5628 09:58:16.443401 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5629 09:58:16.450654 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5630 09:58:16.453114 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5631 09:58:16.453204 ==
5632 09:58:16.456555 Dram Type= 6, Freq= 0, CH_1, rank 0
5633 09:58:16.460323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5634 09:58:16.460414 ==
5635 09:58:16.463530 DQS Delay:
5636 09:58:16.463616 DQS0 = 0, DQS1 = 0
5637 09:58:16.463682 DQM Delay:
5638 09:58:16.466717 DQM0 = 104, DQM1 = 95
5639 09:58:16.466806 DQ Delay:
5640 09:58:16.470132 DQ0 =111, DQ1 =95, DQ2 =91, DQ3 =107
5641 09:58:16.473470 DQ4 =107, DQ5 =111, DQ6 =115, DQ7 =99
5642 09:58:16.476636 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5643 09:58:16.479826 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5644 09:58:16.480000
5645 09:58:16.480087
5646 09:58:16.483232 ==
5647 09:58:16.483427 Dram Type= 6, Freq= 0, CH_1, rank 0
5648 09:58:16.489761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5649 09:58:16.489942 ==
5650 09:58:16.490063
5651 09:58:16.490171
5652 09:58:16.493274 TX Vref Scan disable
5653 09:58:16.493405 == TX Byte 0 ==
5654 09:58:16.496500 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5655 09:58:16.503292 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5656 09:58:16.503434 == TX Byte 1 ==
5657 09:58:16.506370 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5658 09:58:16.513463 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5659 09:58:16.513584 ==
5660 09:58:16.516444 Dram Type= 6, Freq= 0, CH_1, rank 0
5661 09:58:16.519831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5662 09:58:16.519925 ==
5663 09:58:16.519994
5664 09:58:16.520055
5665 09:58:16.523572 TX Vref Scan disable
5666 09:58:16.526328 == TX Byte 0 ==
5667 09:58:16.529880 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5668 09:58:16.533239 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5669 09:58:16.536383 == TX Byte 1 ==
5670 09:58:16.540246 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5671 09:58:16.542980 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5672 09:58:16.543073
5673 09:58:16.543141 [DATLAT]
5674 09:58:16.546604 Freq=933, CH1 RK0
5675 09:58:16.546694
5676 09:58:16.549897 DATLAT Default: 0xd
5677 09:58:16.549985 0, 0xFFFF, sum = 0
5678 09:58:16.553260 1, 0xFFFF, sum = 0
5679 09:58:16.553349 2, 0xFFFF, sum = 0
5680 09:58:16.556533 3, 0xFFFF, sum = 0
5681 09:58:16.556627 4, 0xFFFF, sum = 0
5682 09:58:16.559744 5, 0xFFFF, sum = 0
5683 09:58:16.559835 6, 0xFFFF, sum = 0
5684 09:58:16.562935 7, 0xFFFF, sum = 0
5685 09:58:16.563025 8, 0xFFFF, sum = 0
5686 09:58:16.566425 9, 0xFFFF, sum = 0
5687 09:58:16.566514 10, 0x0, sum = 1
5688 09:58:16.569596 11, 0x0, sum = 2
5689 09:58:16.569683 12, 0x0, sum = 3
5690 09:58:16.573243 13, 0x0, sum = 4
5691 09:58:16.573332 best_step = 11
5692 09:58:16.573399
5693 09:58:16.573462 ==
5694 09:58:16.576369 Dram Type= 6, Freq= 0, CH_1, rank 0
5695 09:58:16.579856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5696 09:58:16.579946 ==
5697 09:58:16.582906 RX Vref Scan: 1
5698 09:58:16.582993
5699 09:58:16.586153 RX Vref 0 -> 0, step: 1
5700 09:58:16.586241
5701 09:58:16.586309 RX Delay -53 -> 252, step: 4
5702 09:58:16.586372
5703 09:58:16.589470 Set Vref, RX VrefLevel [Byte0]: 51
5704 09:58:16.592989 [Byte1]: 50
5705 09:58:16.597898
5706 09:58:16.597993 Final RX Vref Byte 0 = 51 to rank0
5707 09:58:16.601006 Final RX Vref Byte 1 = 50 to rank0
5708 09:58:16.604969 Final RX Vref Byte 0 = 51 to rank1
5709 09:58:16.607873 Final RX Vref Byte 1 = 50 to rank1==
5710 09:58:16.611322 Dram Type= 6, Freq= 0, CH_1, rank 0
5711 09:58:16.614593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5712 09:58:16.617786 ==
5713 09:58:16.617879 DQS Delay:
5714 09:58:16.617946 DQS0 = 0, DQS1 = 0
5715 09:58:16.621279 DQM Delay:
5716 09:58:16.621368 DQM0 = 104, DQM1 = 97
5717 09:58:16.624766 DQ Delay:
5718 09:58:16.627730 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5719 09:58:16.631353 DQ4 =102, DQ5 =112, DQ6 =114, DQ7 =100
5720 09:58:16.634670 DQ8 =86, DQ9 =86, DQ10 =100, DQ11 =90
5721 09:58:16.638039 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =102
5722 09:58:16.638135
5723 09:58:16.638202
5724 09:58:16.644445 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a33, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 413 ps
5725 09:58:16.647834 CH1 RK0: MR19=505, MR18=1A33
5726 09:58:16.654704 CH1_RK0: MR19=0x505, MR18=0x1A33, DQSOSC=405, MR23=63, INC=66, DEC=44
5727 09:58:16.654815
5728 09:58:16.657807 ----->DramcWriteLeveling(PI) begin...
5729 09:58:16.657895 ==
5730 09:58:16.661268 Dram Type= 6, Freq= 0, CH_1, rank 1
5731 09:58:16.664387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 09:58:16.664478 ==
5733 09:58:16.667979 Write leveling (Byte 0): 23 => 23
5734 09:58:16.671121 Write leveling (Byte 1): 29 => 29
5735 09:58:16.674361 DramcWriteLeveling(PI) end<-----
5736 09:58:16.674492
5737 09:58:16.674560 ==
5738 09:58:16.677861 Dram Type= 6, Freq= 0, CH_1, rank 1
5739 09:58:16.681338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 09:58:16.684783 ==
5741 09:58:16.684873 [Gating] SW mode calibration
5742 09:58:16.694509 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5743 09:58:16.697957 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5744 09:58:16.700991 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5745 09:58:16.707577 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5746 09:58:16.711062 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5747 09:58:16.714347 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5748 09:58:16.720846 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 09:58:16.724320 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5750 09:58:16.727630 0 14 24 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 0)
5751 09:58:16.734213 0 14 28 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
5752 09:58:16.737834 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5753 09:58:16.740826 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5754 09:58:16.747558 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5755 09:58:16.751305 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5756 09:58:16.754320 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5757 09:58:16.760825 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 09:58:16.763973 0 15 24 | B1->B0 | 2828 2525 | 0 1 | (0 0) (0 0)
5759 09:58:16.767384 0 15 28 | B1->B0 | 4040 3939 | 0 0 | (0 0) (0 0)
5760 09:58:16.774418 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5761 09:58:16.777295 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5762 09:58:16.780746 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5763 09:58:16.788033 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 09:58:16.790953 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 09:58:16.794657 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 09:58:16.800523 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5767 09:58:16.803865 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5768 09:58:16.807530 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 09:58:16.810329 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 09:58:16.817348 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 09:58:16.820489 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 09:58:16.823698 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 09:58:16.830374 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 09:58:16.833838 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 09:58:16.837273 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 09:58:16.843524 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 09:58:16.847162 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 09:58:16.850337 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 09:58:16.857329 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 09:58:16.860155 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 09:58:16.863818 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 09:58:16.870252 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5783 09:58:16.873688 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5784 09:58:16.877010 Total UI for P1: 0, mck2ui 16
5785 09:58:16.880318 best dqsien dly found for B1: ( 1, 2, 24)
5786 09:58:16.883549 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5787 09:58:16.886834 Total UI for P1: 0, mck2ui 16
5788 09:58:16.890340 best dqsien dly found for B0: ( 1, 2, 26)
5789 09:58:16.893895 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5790 09:58:16.897164 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5791 09:58:16.897266
5792 09:58:16.903914 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5793 09:58:16.906876 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5794 09:58:16.906964 [Gating] SW calibration Done
5795 09:58:16.910355 ==
5796 09:58:16.913748 Dram Type= 6, Freq= 0, CH_1, rank 1
5797 09:58:16.916820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5798 09:58:16.916907 ==
5799 09:58:16.916973 RX Vref Scan: 0
5800 09:58:16.917033
5801 09:58:16.920206 RX Vref 0 -> 0, step: 1
5802 09:58:16.920292
5803 09:58:16.923680 RX Delay -80 -> 252, step: 8
5804 09:58:16.926979 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
5805 09:58:16.931287 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5806 09:58:16.933375 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5807 09:58:16.940000 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5808 09:58:16.943445 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5809 09:58:16.946641 iDelay=200, Bit 5, Center 115 (32 ~ 199) 168
5810 09:58:16.950251 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5811 09:58:16.953154 iDelay=200, Bit 7, Center 99 (8 ~ 191) 184
5812 09:58:16.956742 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5813 09:58:16.963318 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5814 09:58:16.966949 iDelay=200, Bit 10, Center 95 (8 ~ 183) 176
5815 09:58:16.969826 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5816 09:58:16.973399 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5817 09:58:16.976542 iDelay=200, Bit 13, Center 99 (8 ~ 191) 184
5818 09:58:16.980042 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5819 09:58:16.986722 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5820 09:58:16.986822 ==
5821 09:58:16.989876 Dram Type= 6, Freq= 0, CH_1, rank 1
5822 09:58:16.993708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5823 09:58:16.993798 ==
5824 09:58:16.993864 DQS Delay:
5825 09:58:16.996350 DQS0 = 0, DQS1 = 0
5826 09:58:16.996434 DQM Delay:
5827 09:58:16.999959 DQM0 = 102, DQM1 = 95
5828 09:58:17.000045 DQ Delay:
5829 09:58:17.003041 DQ0 =111, DQ1 =95, DQ2 =87, DQ3 =99
5830 09:58:17.006275 DQ4 =103, DQ5 =115, DQ6 =111, DQ7 =99
5831 09:58:17.010041 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5832 09:58:17.013149 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =103
5833 09:58:17.013236
5834 09:58:17.013302
5835 09:58:17.013363 ==
5836 09:58:17.016369 Dram Type= 6, Freq= 0, CH_1, rank 1
5837 09:58:17.023405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5838 09:58:17.023503 ==
5839 09:58:17.023575
5840 09:58:17.023644
5841 09:58:17.023709 TX Vref Scan disable
5842 09:58:17.026148 == TX Byte 0 ==
5843 09:58:17.029997 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5844 09:58:17.033160 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5845 09:58:17.036343 == TX Byte 1 ==
5846 09:58:17.039555 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5847 09:58:17.042978 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5848 09:58:17.046315 ==
5849 09:58:17.049600 Dram Type= 6, Freq= 0, CH_1, rank 1
5850 09:58:17.052946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5851 09:58:17.053037 ==
5852 09:58:17.053104
5853 09:58:17.053166
5854 09:58:17.057154 TX Vref Scan disable
5855 09:58:17.057242 == TX Byte 0 ==
5856 09:58:17.062898 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5857 09:58:17.066231 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5858 09:58:17.066349 == TX Byte 1 ==
5859 09:58:17.072796 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5860 09:58:17.076121 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5861 09:58:17.076213
5862 09:58:17.076281 [DATLAT]
5863 09:58:17.079607 Freq=933, CH1 RK1
5864 09:58:17.079693
5865 09:58:17.079761 DATLAT Default: 0xb
5866 09:58:17.082705 0, 0xFFFF, sum = 0
5867 09:58:17.082791 1, 0xFFFF, sum = 0
5868 09:58:17.086341 2, 0xFFFF, sum = 0
5869 09:58:17.086445 3, 0xFFFF, sum = 0
5870 09:58:17.089338 4, 0xFFFF, sum = 0
5871 09:58:17.089425 5, 0xFFFF, sum = 0
5872 09:58:17.092726 6, 0xFFFF, sum = 0
5873 09:58:17.096032 7, 0xFFFF, sum = 0
5874 09:58:17.096119 8, 0xFFFF, sum = 0
5875 09:58:17.099440 9, 0xFFFF, sum = 0
5876 09:58:17.099526 10, 0x0, sum = 1
5877 09:58:17.099594 11, 0x0, sum = 2
5878 09:58:17.102641 12, 0x0, sum = 3
5879 09:58:17.102728 13, 0x0, sum = 4
5880 09:58:17.106525 best_step = 11
5881 09:58:17.106609
5882 09:58:17.106675 ==
5883 09:58:17.109584 Dram Type= 6, Freq= 0, CH_1, rank 1
5884 09:58:17.113001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5885 09:58:17.113088 ==
5886 09:58:17.116179 RX Vref Scan: 0
5887 09:58:17.116264
5888 09:58:17.116331 RX Vref 0 -> 0, step: 1
5889 09:58:17.116394
5890 09:58:17.119288 RX Delay -53 -> 252, step: 4
5891 09:58:17.127222 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5892 09:58:17.129886 iDelay=199, Bit 1, Center 100 (23 ~ 178) 156
5893 09:58:17.133126 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5894 09:58:17.136532 iDelay=199, Bit 3, Center 104 (23 ~ 186) 164
5895 09:58:17.139785 iDelay=199, Bit 4, Center 108 (27 ~ 190) 164
5896 09:58:17.146874 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5897 09:58:17.149862 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5898 09:58:17.153357 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5899 09:58:17.156492 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5900 09:58:17.159852 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5901 09:58:17.163194 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5902 09:58:17.169897 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5903 09:58:17.173783 iDelay=199, Bit 12, Center 104 (19 ~ 190) 172
5904 09:58:17.176777 iDelay=199, Bit 13, Center 102 (19 ~ 186) 168
5905 09:58:17.180449 iDelay=199, Bit 14, Center 106 (19 ~ 194) 176
5906 09:58:17.186641 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5907 09:58:17.186746 ==
5908 09:58:17.189589 Dram Type= 6, Freq= 0, CH_1, rank 1
5909 09:58:17.192895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5910 09:58:17.192983 ==
5911 09:58:17.193050 DQS Delay:
5912 09:58:17.196267 DQS0 = 0, DQS1 = 0
5913 09:58:17.196353 DQM Delay:
5914 09:58:17.200059 DQM0 = 105, DQM1 = 97
5915 09:58:17.200146 DQ Delay:
5916 09:58:17.203157 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =104
5917 09:58:17.206096 DQ4 =108, DQ5 =114, DQ6 =112, DQ7 =102
5918 09:58:17.209477 DQ8 =86, DQ9 =86, DQ10 =98, DQ11 =92
5919 09:58:17.212913 DQ12 =104, DQ13 =102, DQ14 =106, DQ15 =106
5920 09:58:17.212998
5921 09:58:17.213066
5922 09:58:17.222769 [DQSOSCAuto] RK1, (LSB)MR18= 0x1efb, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 412 ps
5923 09:58:17.226030 CH1 RK1: MR19=504, MR18=1EFB
5924 09:58:17.229431 CH1_RK1: MR19=0x504, MR18=0x1EFB, DQSOSC=412, MR23=63, INC=63, DEC=42
5925 09:58:17.232790 [RxdqsGatingPostProcess] freq 933
5926 09:58:17.239375 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5927 09:58:17.243140 best DQS0 dly(2T, 0.5T) = (0, 10)
5928 09:58:17.246069 best DQS1 dly(2T, 0.5T) = (0, 10)
5929 09:58:17.249106 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5930 09:58:17.252789 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5931 09:58:17.255821 best DQS0 dly(2T, 0.5T) = (0, 10)
5932 09:58:17.259407 best DQS1 dly(2T, 0.5T) = (0, 10)
5933 09:58:17.262361 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5934 09:58:17.265984 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5935 09:58:17.266073 Pre-setting of DQS Precalculation
5936 09:58:17.272574 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5937 09:58:17.279183 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5938 09:58:17.285953 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5939 09:58:17.286067
5940 09:58:17.286138
5941 09:58:17.289042 [Calibration Summary] 1866 Mbps
5942 09:58:17.292793 CH 0, Rank 0
5943 09:58:17.292881 SW Impedance : PASS
5944 09:58:17.296230 DUTY Scan : NO K
5945 09:58:17.299157 ZQ Calibration : PASS
5946 09:58:17.299244 Jitter Meter : NO K
5947 09:58:17.302464 CBT Training : PASS
5948 09:58:17.305637 Write leveling : PASS
5949 09:58:17.305739 RX DQS gating : PASS
5950 09:58:17.309491 RX DQ/DQS(RDDQC) : PASS
5951 09:58:17.309593 TX DQ/DQS : PASS
5952 09:58:17.312338 RX DATLAT : PASS
5953 09:58:17.315749 RX DQ/DQS(Engine): PASS
5954 09:58:17.315834 TX OE : NO K
5955 09:58:17.319233 All Pass.
5956 09:58:17.319318
5957 09:58:17.319385 CH 0, Rank 1
5958 09:58:17.322758 SW Impedance : PASS
5959 09:58:17.322841 DUTY Scan : NO K
5960 09:58:17.325578 ZQ Calibration : PASS
5961 09:58:17.328990 Jitter Meter : NO K
5962 09:58:17.329078 CBT Training : PASS
5963 09:58:17.332177 Write leveling : PASS
5964 09:58:17.335500 RX DQS gating : PASS
5965 09:58:17.335633 RX DQ/DQS(RDDQC) : PASS
5966 09:58:17.338768 TX DQ/DQS : PASS
5967 09:58:17.342659 RX DATLAT : PASS
5968 09:58:17.342750 RX DQ/DQS(Engine): PASS
5969 09:58:17.345494 TX OE : NO K
5970 09:58:17.345580 All Pass.
5971 09:58:17.345647
5972 09:58:17.348740 CH 1, Rank 0
5973 09:58:17.348826 SW Impedance : PASS
5974 09:58:17.352319 DUTY Scan : NO K
5975 09:58:17.355468 ZQ Calibration : PASS
5976 09:58:17.355553 Jitter Meter : NO K
5977 09:58:17.358706 CBT Training : PASS
5978 09:58:17.362312 Write leveling : PASS
5979 09:58:17.362424 RX DQS gating : PASS
5980 09:58:17.365356 RX DQ/DQS(RDDQC) : PASS
5981 09:58:17.368505 TX DQ/DQS : PASS
5982 09:58:17.368594 RX DATLAT : PASS
5983 09:58:17.371935 RX DQ/DQS(Engine): PASS
5984 09:58:17.372021 TX OE : NO K
5985 09:58:17.375066 All Pass.
5986 09:58:17.375151
5987 09:58:17.375217 CH 1, Rank 1
5988 09:58:17.378521 SW Impedance : PASS
5989 09:58:17.378609 DUTY Scan : NO K
5990 09:58:17.381757 ZQ Calibration : PASS
5991 09:58:17.385676 Jitter Meter : NO K
5992 09:58:17.385766 CBT Training : PASS
5993 09:58:17.388436 Write leveling : PASS
5994 09:58:17.391988 RX DQS gating : PASS
5995 09:58:17.392077 RX DQ/DQS(RDDQC) : PASS
5996 09:58:17.395022 TX DQ/DQS : PASS
5997 09:58:17.398598 RX DATLAT : PASS
5998 09:58:17.398685 RX DQ/DQS(Engine): PASS
5999 09:58:17.402019 TX OE : NO K
6000 09:58:17.402110 All Pass.
6001 09:58:17.402178
6002 09:58:17.404948 DramC Write-DBI off
6003 09:58:17.408337 PER_BANK_REFRESH: Hybrid Mode
6004 09:58:17.408424 TX_TRACKING: ON
6005 09:58:17.418315 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6006 09:58:17.422582 [FAST_K] Save calibration result to emmc
6007 09:58:17.424910 dramc_set_vcore_voltage set vcore to 650000
6008 09:58:17.428188 Read voltage for 400, 6
6009 09:58:17.428307 Vio18 = 0
6010 09:58:17.428404 Vcore = 650000
6011 09:58:17.431623 Vdram = 0
6012 09:58:17.431737 Vddq = 0
6013 09:58:17.431845 Vmddr = 0
6014 09:58:17.438419 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6015 09:58:17.441448 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6016 09:58:17.444916 MEM_TYPE=3, freq_sel=20
6017 09:58:17.448749 sv_algorithm_assistance_LP4_800
6018 09:58:17.451915 ============ PULL DRAM RESETB DOWN ============
6019 09:58:17.454848 ========== PULL DRAM RESETB DOWN end =========
6020 09:58:17.461473 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6021 09:58:17.464764 ===================================
6022 09:58:17.464856 LPDDR4 DRAM CONFIGURATION
6023 09:58:17.467963 ===================================
6024 09:58:17.471278 EX_ROW_EN[0] = 0x0
6025 09:58:17.474589 EX_ROW_EN[1] = 0x0
6026 09:58:17.474677 LP4Y_EN = 0x0
6027 09:58:17.477954 WORK_FSP = 0x0
6028 09:58:17.478041 WL = 0x2
6029 09:58:17.481418 RL = 0x2
6030 09:58:17.481504 BL = 0x2
6031 09:58:17.484783 RPST = 0x0
6032 09:58:17.484869 RD_PRE = 0x0
6033 09:58:17.488040 WR_PRE = 0x1
6034 09:58:17.488127 WR_PST = 0x0
6035 09:58:17.491617 DBI_WR = 0x0
6036 09:58:17.491703 DBI_RD = 0x0
6037 09:58:17.494720 OTF = 0x1
6038 09:58:17.498226 ===================================
6039 09:58:17.501521 ===================================
6040 09:58:17.501610 ANA top config
6041 09:58:17.504506 ===================================
6042 09:58:17.508305 DLL_ASYNC_EN = 0
6043 09:58:17.511117 ALL_SLAVE_EN = 1
6044 09:58:17.514582 NEW_RANK_MODE = 1
6045 09:58:17.514667 DLL_IDLE_MODE = 1
6046 09:58:17.518105 LP45_APHY_COMB_EN = 1
6047 09:58:17.521572 TX_ODT_DIS = 1
6048 09:58:17.524513 NEW_8X_MODE = 1
6049 09:58:17.527660 ===================================
6050 09:58:17.530990 ===================================
6051 09:58:17.534354 data_rate = 800
6052 09:58:17.534485 CKR = 1
6053 09:58:17.537754 DQ_P2S_RATIO = 4
6054 09:58:17.541198 ===================================
6055 09:58:17.544497 CA_P2S_RATIO = 4
6056 09:58:17.547751 DQ_CA_OPEN = 0
6057 09:58:17.551192 DQ_SEMI_OPEN = 1
6058 09:58:17.554673 CA_SEMI_OPEN = 1
6059 09:58:17.554761 CA_FULL_RATE = 0
6060 09:58:17.557608 DQ_CKDIV4_EN = 0
6061 09:58:17.561025 CA_CKDIV4_EN = 1
6062 09:58:17.564692 CA_PREDIV_EN = 0
6063 09:58:17.567745 PH8_DLY = 0
6064 09:58:17.570958 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6065 09:58:17.571046 DQ_AAMCK_DIV = 0
6066 09:58:17.574493 CA_AAMCK_DIV = 0
6067 09:58:17.577795 CA_ADMCK_DIV = 4
6068 09:58:17.580966 DQ_TRACK_CA_EN = 0
6069 09:58:17.584191 CA_PICK = 800
6070 09:58:17.587838 CA_MCKIO = 400
6071 09:58:17.591234 MCKIO_SEMI = 400
6072 09:58:17.591325 PLL_FREQ = 3016
6073 09:58:17.594674 DQ_UI_PI_RATIO = 32
6074 09:58:17.597656 CA_UI_PI_RATIO = 32
6075 09:58:17.600912 ===================================
6076 09:58:17.604410 ===================================
6077 09:58:17.608040 memory_type:LPDDR4
6078 09:58:17.608156 GP_NUM : 10
6079 09:58:17.610822 SRAM_EN : 1
6080 09:58:17.613921 MD32_EN : 0
6081 09:58:17.617309 ===================================
6082 09:58:17.617400 [ANA_INIT] >>>>>>>>>>>>>>
6083 09:58:17.621595 <<<<<< [CONFIGURE PHASE]: ANA_TX
6084 09:58:17.624472 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6085 09:58:17.627946 ===================================
6086 09:58:17.630746 data_rate = 800,PCW = 0X7400
6087 09:58:17.634098 ===================================
6088 09:58:17.637377 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6089 09:58:17.644272 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6090 09:58:17.653904 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6091 09:58:17.661044 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6092 09:58:17.664038 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6093 09:58:17.667565 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6094 09:58:17.667659 [ANA_INIT] flow start
6095 09:58:17.670579 [ANA_INIT] PLL >>>>>>>>
6096 09:58:17.673924 [ANA_INIT] PLL <<<<<<<<
6097 09:58:17.674012 [ANA_INIT] MIDPI >>>>>>>>
6098 09:58:17.677253 [ANA_INIT] MIDPI <<<<<<<<
6099 09:58:17.680555 [ANA_INIT] DLL >>>>>>>>
6100 09:58:17.680644 [ANA_INIT] flow end
6101 09:58:17.687318 ============ LP4 DIFF to SE enter ============
6102 09:58:17.691463 ============ LP4 DIFF to SE exit ============
6103 09:58:17.691561 [ANA_INIT] <<<<<<<<<<<<<
6104 09:58:17.693877 [Flow] Enable top DCM control >>>>>
6105 09:58:17.697198 [Flow] Enable top DCM control <<<<<
6106 09:58:17.700672 Enable DLL master slave shuffle
6107 09:58:17.707160 ==============================================================
6108 09:58:17.710796 Gating Mode config
6109 09:58:17.714032 ==============================================================
6110 09:58:17.717146 Config description:
6111 09:58:17.727679 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6112 09:58:17.734255 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6113 09:58:17.737198 SELPH_MODE 0: By rank 1: By Phase
6114 09:58:17.743912 ==============================================================
6115 09:58:17.747327 GAT_TRACK_EN = 0
6116 09:58:17.750644 RX_GATING_MODE = 2
6117 09:58:17.750739 RX_GATING_TRACK_MODE = 2
6118 09:58:17.754003 SELPH_MODE = 1
6119 09:58:17.757327 PICG_EARLY_EN = 1
6120 09:58:17.760507 VALID_LAT_VALUE = 1
6121 09:58:17.767012 ==============================================================
6122 09:58:17.770300 Enter into Gating configuration >>>>
6123 09:58:17.773991 Exit from Gating configuration <<<<
6124 09:58:17.777202 Enter into DVFS_PRE_config >>>>>
6125 09:58:17.786945 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6126 09:58:17.790539 Exit from DVFS_PRE_config <<<<<
6127 09:58:17.793847 Enter into PICG configuration >>>>
6128 09:58:17.796983 Exit from PICG configuration <<<<
6129 09:58:17.800281 [RX_INPUT] configuration >>>>>
6130 09:58:17.803449 [RX_INPUT] configuration <<<<<
6131 09:58:17.807289 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6132 09:58:17.813282 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6133 09:58:17.819950 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6134 09:58:17.826524 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6135 09:58:17.833343 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6136 09:58:17.836647 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6137 09:58:17.843601 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6138 09:58:17.846594 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6139 09:58:17.849692 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6140 09:58:17.853109 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6141 09:58:17.856399 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6142 09:58:17.863223 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6143 09:58:17.866313 ===================================
6144 09:58:17.869764 LPDDR4 DRAM CONFIGURATION
6145 09:58:17.873169 ===================================
6146 09:58:17.873281 EX_ROW_EN[0] = 0x0
6147 09:58:17.876179 EX_ROW_EN[1] = 0x0
6148 09:58:17.876287 LP4Y_EN = 0x0
6149 09:58:17.879637 WORK_FSP = 0x0
6150 09:58:17.879742 WL = 0x2
6151 09:58:17.882816 RL = 0x2
6152 09:58:17.882921 BL = 0x2
6153 09:58:17.886023 RPST = 0x0
6154 09:58:17.886129 RD_PRE = 0x0
6155 09:58:17.889499 WR_PRE = 0x1
6156 09:58:17.889605 WR_PST = 0x0
6157 09:58:17.892780 DBI_WR = 0x0
6158 09:58:17.892887 DBI_RD = 0x0
6159 09:58:17.896166 OTF = 0x1
6160 09:58:17.899608 ===================================
6161 09:58:17.902743 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6162 09:58:17.906489 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6163 09:58:17.912556 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6164 09:58:17.916182 ===================================
6165 09:58:17.919338 LPDDR4 DRAM CONFIGURATION
6166 09:58:17.922887 ===================================
6167 09:58:17.923016 EX_ROW_EN[0] = 0x10
6168 09:58:17.926006 EX_ROW_EN[1] = 0x0
6169 09:58:17.926112 LP4Y_EN = 0x0
6170 09:58:17.929278 WORK_FSP = 0x0
6171 09:58:17.929386 WL = 0x2
6172 09:58:17.932655 RL = 0x2
6173 09:58:17.932761 BL = 0x2
6174 09:58:17.936140 RPST = 0x0
6175 09:58:17.936251 RD_PRE = 0x0
6176 09:58:17.939565 WR_PRE = 0x1
6177 09:58:17.939679 WR_PST = 0x0
6178 09:58:17.942639 DBI_WR = 0x0
6179 09:58:17.942745 DBI_RD = 0x0
6180 09:58:17.946069 OTF = 0x1
6181 09:58:17.949251 ===================================
6182 09:58:17.955755 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6183 09:58:17.959254 nWR fixed to 30
6184 09:58:17.962670 [ModeRegInit_LP4] CH0 RK0
6185 09:58:17.962779 [ModeRegInit_LP4] CH0 RK1
6186 09:58:17.965735 [ModeRegInit_LP4] CH1 RK0
6187 09:58:17.969178 [ModeRegInit_LP4] CH1 RK1
6188 09:58:17.969286 match AC timing 19
6189 09:58:17.976273 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6190 09:58:17.979340 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6191 09:58:17.982917 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6192 09:58:17.989250 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6193 09:58:17.992481 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6194 09:58:17.992601 ==
6195 09:58:17.995712 Dram Type= 6, Freq= 0, CH_0, rank 0
6196 09:58:17.999209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6197 09:58:17.999323 ==
6198 09:58:18.005901 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6199 09:58:18.012565 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6200 09:58:18.015684 [CA 0] Center 36 (8~64) winsize 57
6201 09:58:18.019422 [CA 1] Center 36 (8~64) winsize 57
6202 09:58:18.019538 [CA 2] Center 36 (8~64) winsize 57
6203 09:58:18.022574 [CA 3] Center 36 (8~64) winsize 57
6204 09:58:18.025808 [CA 4] Center 36 (8~64) winsize 57
6205 09:58:18.029293 [CA 5] Center 36 (8~64) winsize 57
6206 09:58:18.029407
6207 09:58:18.032442 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6208 09:58:18.032550
6209 09:58:18.039170 [CATrainingPosCal] consider 1 rank data
6210 09:58:18.039319 u2DelayCellTimex100 = 270/100 ps
6211 09:58:18.045856 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6212 09:58:18.049244 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6213 09:58:18.052519 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6214 09:58:18.055819 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 09:58:18.058982 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 09:58:18.062469 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 09:58:18.062581
6218 09:58:18.065560 CA PerBit enable=1, Macro0, CA PI delay=36
6219 09:58:18.065669
6220 09:58:18.069467 [CBTSetCACLKResult] CA Dly = 36
6221 09:58:18.072555 CS Dly: 1 (0~32)
6222 09:58:18.072664 ==
6223 09:58:18.075691 Dram Type= 6, Freq= 0, CH_0, rank 1
6224 09:58:18.079005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6225 09:58:18.079116 ==
6226 09:58:18.082281 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6227 09:58:18.089359 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6228 09:58:18.092297 [CA 0] Center 36 (8~64) winsize 57
6229 09:58:18.095935 [CA 1] Center 36 (8~64) winsize 57
6230 09:58:18.099138 [CA 2] Center 36 (8~64) winsize 57
6231 09:58:18.102380 [CA 3] Center 36 (8~64) winsize 57
6232 09:58:18.105726 [CA 4] Center 36 (8~64) winsize 57
6233 09:58:18.108832 [CA 5] Center 36 (8~64) winsize 57
6234 09:58:18.108945
6235 09:58:18.112328 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6236 09:58:18.112437
6237 09:58:18.115724 [CATrainingPosCal] consider 2 rank data
6238 09:58:18.118941 u2DelayCellTimex100 = 270/100 ps
6239 09:58:18.122280 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 09:58:18.125480 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 09:58:18.129107 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 09:58:18.132274 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 09:58:18.139411 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 09:58:18.142211 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 09:58:18.142330
6246 09:58:18.145660 CA PerBit enable=1, Macro0, CA PI delay=36
6247 09:58:18.145770
6248 09:58:18.149034 [CBTSetCACLKResult] CA Dly = 36
6249 09:58:18.149143 CS Dly: 1 (0~32)
6250 09:58:18.149236
6251 09:58:18.152739 ----->DramcWriteLeveling(PI) begin...
6252 09:58:18.152849 ==
6253 09:58:18.155442 Dram Type= 6, Freq= 0, CH_0, rank 0
6254 09:58:18.162149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6255 09:58:18.162275 ==
6256 09:58:18.165517 Write leveling (Byte 0): 40 => 8
6257 09:58:18.165625 Write leveling (Byte 1): 32 => 0
6258 09:58:18.169249 DramcWriteLeveling(PI) end<-----
6259 09:58:18.169357
6260 09:58:18.169449 ==
6261 09:58:18.172125 Dram Type= 6, Freq= 0, CH_0, rank 0
6262 09:58:18.179213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6263 09:58:18.179341 ==
6264 09:58:18.182112 [Gating] SW mode calibration
6265 09:58:18.189741 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6266 09:58:18.192051 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6267 09:58:18.198779 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6268 09:58:18.201965 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6269 09:58:18.205345 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6270 09:58:18.212082 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6271 09:58:18.215402 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6272 09:58:18.218733 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6273 09:58:18.225109 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6274 09:58:18.228452 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6275 09:58:18.231736 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6276 09:58:18.235777 Total UI for P1: 0, mck2ui 16
6277 09:58:18.238838 best dqsien dly found for B0: ( 0, 14, 24)
6278 09:58:18.241744 Total UI for P1: 0, mck2ui 16
6279 09:58:18.245670 best dqsien dly found for B1: ( 0, 14, 24)
6280 09:58:18.248473 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6281 09:58:18.251699 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6282 09:58:18.251813
6283 09:58:18.255452 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6284 09:58:18.261847 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6285 09:58:18.261975 [Gating] SW calibration Done
6286 09:58:18.262071 ==
6287 09:58:18.265318 Dram Type= 6, Freq= 0, CH_0, rank 0
6288 09:58:18.271931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6289 09:58:18.272058 ==
6290 09:58:18.272156 RX Vref Scan: 0
6291 09:58:18.272247
6292 09:58:18.275287 RX Vref 0 -> 0, step: 1
6293 09:58:18.275393
6294 09:58:18.278297 RX Delay -410 -> 252, step: 16
6295 09:58:18.282067 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6296 09:58:18.285168 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6297 09:58:18.291824 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6298 09:58:18.295113 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6299 09:58:18.298689 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6300 09:58:18.301985 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6301 09:58:18.308530 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6302 09:58:18.311835 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6303 09:58:18.315046 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6304 09:58:18.318271 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6305 09:58:18.324986 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6306 09:58:18.328112 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6307 09:58:18.331838 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6308 09:58:18.334857 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6309 09:58:18.341615 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6310 09:58:18.344966 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6311 09:58:18.345064 ==
6312 09:58:18.348233 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 09:58:18.351499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 09:58:18.351588 ==
6315 09:58:18.354981 DQS Delay:
6316 09:58:18.355065 DQS0 = 19, DQS1 = 43
6317 09:58:18.358171 DQM Delay:
6318 09:58:18.358253 DQM0 = 5, DQM1 = 15
6319 09:58:18.358316 DQ Delay:
6320 09:58:18.361580 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6321 09:58:18.364737 DQ4 =8, DQ5 =0, DQ6 =8, DQ7 =16
6322 09:58:18.367864 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6323 09:58:18.371166 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6324 09:58:18.371250
6325 09:58:18.371313
6326 09:58:18.371371 ==
6327 09:58:18.374852 Dram Type= 6, Freq= 0, CH_0, rank 0
6328 09:58:18.378155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6329 09:58:18.381201 ==
6330 09:58:18.381287
6331 09:58:18.381350
6332 09:58:18.381408 TX Vref Scan disable
6333 09:58:18.384429 == TX Byte 0 ==
6334 09:58:18.387647 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6335 09:58:18.391077 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6336 09:58:18.394338 == TX Byte 1 ==
6337 09:58:18.397907 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6338 09:58:18.401072 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6339 09:58:18.401154 ==
6340 09:58:18.404503 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 09:58:18.411312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 09:58:18.411412 ==
6343 09:58:18.411478
6344 09:58:18.411537
6345 09:58:18.411593 TX Vref Scan disable
6346 09:58:18.414304 == TX Byte 0 ==
6347 09:58:18.417535 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6348 09:58:18.420875 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6349 09:58:18.424380 == TX Byte 1 ==
6350 09:58:18.427544 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6351 09:58:18.430904 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6352 09:58:18.430992
6353 09:58:18.434203 [DATLAT]
6354 09:58:18.434287 Freq=400, CH0 RK0
6355 09:58:18.434376
6356 09:58:18.437578 DATLAT Default: 0xf
6357 09:58:18.437667 0, 0xFFFF, sum = 0
6358 09:58:18.441006 1, 0xFFFF, sum = 0
6359 09:58:18.441100 2, 0xFFFF, sum = 0
6360 09:58:18.444306 3, 0xFFFF, sum = 0
6361 09:58:18.444409 4, 0xFFFF, sum = 0
6362 09:58:18.447609 5, 0xFFFF, sum = 0
6363 09:58:18.447755 6, 0xFFFF, sum = 0
6364 09:58:18.450888 7, 0xFFFF, sum = 0
6365 09:58:18.451023 8, 0xFFFF, sum = 0
6366 09:58:18.454010 9, 0xFFFF, sum = 0
6367 09:58:18.457368 10, 0xFFFF, sum = 0
6368 09:58:18.457460 11, 0xFFFF, sum = 0
6369 09:58:18.460692 12, 0xFFFF, sum = 0
6370 09:58:18.460795 13, 0x0, sum = 1
6371 09:58:18.463796 14, 0x0, sum = 2
6372 09:58:18.463919 15, 0x0, sum = 3
6373 09:58:18.467399 16, 0x0, sum = 4
6374 09:58:18.467484 best_step = 14
6375 09:58:18.467553
6376 09:58:18.467672 ==
6377 09:58:18.470683 Dram Type= 6, Freq= 0, CH_0, rank 0
6378 09:58:18.474370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6379 09:58:18.474503 ==
6380 09:58:18.477192 RX Vref Scan: 1
6381 09:58:18.477276
6382 09:58:18.481431 RX Vref 0 -> 0, step: 1
6383 09:58:18.481546
6384 09:58:18.481645 RX Delay -327 -> 252, step: 8
6385 09:58:18.481737
6386 09:58:18.483820 Set Vref, RX VrefLevel [Byte0]: 58
6387 09:58:18.487376 [Byte1]: 49
6388 09:58:18.492557
6389 09:58:18.492659 Final RX Vref Byte 0 = 58 to rank0
6390 09:58:18.495937 Final RX Vref Byte 1 = 49 to rank0
6391 09:58:18.499281 Final RX Vref Byte 0 = 58 to rank1
6392 09:58:18.502822 Final RX Vref Byte 1 = 49 to rank1==
6393 09:58:18.505783 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 09:58:18.512478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 09:58:18.512580 ==
6396 09:58:18.512647 DQS Delay:
6397 09:58:18.516451 DQS0 = 28, DQS1 = 48
6398 09:58:18.516537 DQM Delay:
6399 09:58:18.516602 DQM0 = 12, DQM1 = 16
6400 09:58:18.519090 DQ Delay:
6401 09:58:18.522497 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6402 09:58:18.522585 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6403 09:58:18.525845 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6404 09:58:18.528915 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6405 09:58:18.532774
6406 09:58:18.532866
6407 09:58:18.539018 [DQSOSCAuto] RK0, (LSB)MR18= 0xa59d, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 389 ps
6408 09:58:18.542291 CH0 RK0: MR19=C0C, MR18=A59D
6409 09:58:18.549087 CH0_RK0: MR19=0xC0C, MR18=0xA59D, DQSOSC=389, MR23=63, INC=390, DEC=260
6410 09:58:18.549198 ==
6411 09:58:18.552344 Dram Type= 6, Freq= 0, CH_0, rank 1
6412 09:58:18.555592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6413 09:58:18.555684 ==
6414 09:58:18.559360 [Gating] SW mode calibration
6415 09:58:18.565888 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6416 09:58:18.572260 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6417 09:58:18.575732 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6418 09:58:18.578926 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6419 09:58:18.585651 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6420 09:58:18.589147 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6421 09:58:18.592536 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6422 09:58:18.595607 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6423 09:58:18.602639 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6424 09:58:18.605632 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6425 09:58:18.608888 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6426 09:58:18.612151 Total UI for P1: 0, mck2ui 16
6427 09:58:18.615542 best dqsien dly found for B0: ( 0, 14, 24)
6428 09:58:18.618705 Total UI for P1: 0, mck2ui 16
6429 09:58:18.621986 best dqsien dly found for B1: ( 0, 14, 24)
6430 09:58:18.625596 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6431 09:58:18.632175 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6432 09:58:18.632281
6433 09:58:18.635486 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6434 09:58:18.638516 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6435 09:58:18.641937 [Gating] SW calibration Done
6436 09:58:18.642061 ==
6437 09:58:18.645524 Dram Type= 6, Freq= 0, CH_0, rank 1
6438 09:58:18.648705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6439 09:58:18.648817 ==
6440 09:58:18.651756 RX Vref Scan: 0
6441 09:58:18.651865
6442 09:58:18.651959 RX Vref 0 -> 0, step: 1
6443 09:58:18.652050
6444 09:58:18.655623 RX Delay -410 -> 252, step: 16
6445 09:58:18.662039 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6446 09:58:18.665162 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6447 09:58:18.668519 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6448 09:58:18.671462 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6449 09:58:18.678176 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6450 09:58:18.681472 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6451 09:58:18.684758 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6452 09:58:18.688334 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6453 09:58:18.694731 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6454 09:58:18.698238 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6455 09:58:18.701597 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6456 09:58:18.704550 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6457 09:58:18.711379 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6458 09:58:18.714824 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6459 09:58:18.717821 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6460 09:58:18.721008 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6461 09:58:18.724765 ==
6462 09:58:18.724877 Dram Type= 6, Freq= 0, CH_0, rank 1
6463 09:58:18.731083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 09:58:18.731207 ==
6465 09:58:18.731303 DQS Delay:
6466 09:58:18.734607 DQS0 = 27, DQS1 = 43
6467 09:58:18.734712 DQM Delay:
6468 09:58:18.737719 DQM0 = 9, DQM1 = 16
6469 09:58:18.737826 DQ Delay:
6470 09:58:18.741302 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6471 09:58:18.744433 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6472 09:58:18.744545 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6473 09:58:18.751209 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6474 09:58:18.751331
6475 09:58:18.751427
6476 09:58:18.751516 ==
6477 09:58:18.754636 Dram Type= 6, Freq= 0, CH_0, rank 1
6478 09:58:18.757433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6479 09:58:18.757539 ==
6480 09:58:18.757631
6481 09:58:18.757719
6482 09:58:18.761139 TX Vref Scan disable
6483 09:58:18.761245 == TX Byte 0 ==
6484 09:58:18.767575 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6485 09:58:18.770817 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6486 09:58:18.770950 == TX Byte 1 ==
6487 09:58:18.777602 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6488 09:58:18.780908 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6489 09:58:18.781069 ==
6490 09:58:18.784149 Dram Type= 6, Freq= 0, CH_0, rank 1
6491 09:58:18.787480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 09:58:18.787619 ==
6493 09:58:18.787717
6494 09:58:18.787844
6495 09:58:18.790801 TX Vref Scan disable
6496 09:58:18.790921 == TX Byte 0 ==
6497 09:58:18.797177 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6498 09:58:18.800675 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6499 09:58:18.800802 == TX Byte 1 ==
6500 09:58:18.807188 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6501 09:58:18.810842 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6502 09:58:18.810978
6503 09:58:18.811077 [DATLAT]
6504 09:58:18.814002 Freq=400, CH0 RK1
6505 09:58:18.814111
6506 09:58:18.814203 DATLAT Default: 0xe
6507 09:58:18.817186 0, 0xFFFF, sum = 0
6508 09:58:18.817314 1, 0xFFFF, sum = 0
6509 09:58:18.820236 2, 0xFFFF, sum = 0
6510 09:58:18.820352 3, 0xFFFF, sum = 0
6511 09:58:18.823918 4, 0xFFFF, sum = 0
6512 09:58:18.824032 5, 0xFFFF, sum = 0
6513 09:58:18.826922 6, 0xFFFF, sum = 0
6514 09:58:18.830260 7, 0xFFFF, sum = 0
6515 09:58:18.830381 8, 0xFFFF, sum = 0
6516 09:58:18.833782 9, 0xFFFF, sum = 0
6517 09:58:18.833896 10, 0xFFFF, sum = 0
6518 09:58:18.837259 11, 0xFFFF, sum = 0
6519 09:58:18.837375 12, 0xFFFF, sum = 0
6520 09:58:18.840377 13, 0x0, sum = 1
6521 09:58:18.840514 14, 0x0, sum = 2
6522 09:58:18.843414 15, 0x0, sum = 3
6523 09:58:18.843537 16, 0x0, sum = 4
6524 09:58:18.843636 best_step = 14
6525 09:58:18.846711
6526 09:58:18.846839 ==
6527 09:58:18.850221 Dram Type= 6, Freq= 0, CH_0, rank 1
6528 09:58:18.853399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6529 09:58:18.853533 ==
6530 09:58:18.853636 RX Vref Scan: 0
6531 09:58:18.853727
6532 09:58:18.857060 RX Vref 0 -> 0, step: 1
6533 09:58:18.857185
6534 09:58:18.860290 RX Delay -327 -> 252, step: 8
6535 09:58:18.867269 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6536 09:58:18.870823 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6537 09:58:18.873814 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6538 09:58:18.880465 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6539 09:58:18.883978 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6540 09:58:18.886988 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6541 09:58:18.890315 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6542 09:58:18.894009 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6543 09:58:18.900461 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6544 09:58:18.904371 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6545 09:58:18.907150 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6546 09:58:18.910334 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6547 09:58:18.917099 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6548 09:58:18.920385 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6549 09:58:18.923692 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6550 09:58:18.930166 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6551 09:58:18.930284 ==
6552 09:58:18.933690 Dram Type= 6, Freq= 0, CH_0, rank 1
6553 09:58:18.937435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6554 09:58:18.937556 ==
6555 09:58:18.937652 DQS Delay:
6556 09:58:18.940035 DQS0 = 28, DQS1 = 40
6557 09:58:18.940149 DQM Delay:
6558 09:58:18.943549 DQM0 = 10, DQM1 = 12
6559 09:58:18.943665 DQ Delay:
6560 09:58:18.947228 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6561 09:58:18.950212 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6562 09:58:18.953988 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6563 09:58:18.956865 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6564 09:58:18.956982
6565 09:58:18.957075
6566 09:58:18.963501 [DQSOSCAuto] RK1, (LSB)MR18= 0xb86b, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 386 ps
6567 09:58:18.966916 CH0 RK1: MR19=C0C, MR18=B86B
6568 09:58:18.973487 CH0_RK1: MR19=0xC0C, MR18=0xB86B, DQSOSC=386, MR23=63, INC=396, DEC=264
6569 09:58:18.976777 [RxdqsGatingPostProcess] freq 400
6570 09:58:18.983494 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6571 09:58:18.983610 best DQS0 dly(2T, 0.5T) = (0, 10)
6572 09:58:18.986750 best DQS1 dly(2T, 0.5T) = (0, 10)
6573 09:58:18.990460 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6574 09:58:18.993558 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6575 09:58:18.997083 best DQS0 dly(2T, 0.5T) = (0, 10)
6576 09:58:18.999975 best DQS1 dly(2T, 0.5T) = (0, 10)
6577 09:58:19.003592 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6578 09:58:19.006943 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6579 09:58:19.010472 Pre-setting of DQS Precalculation
6580 09:58:19.013475 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6581 09:58:19.016815 ==
6582 09:58:19.020642 Dram Type= 6, Freq= 0, CH_1, rank 0
6583 09:58:19.023736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6584 09:58:19.023838 ==
6585 09:58:19.027179 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6586 09:58:19.033624 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6587 09:58:19.037361 [CA 0] Center 36 (8~64) winsize 57
6588 09:58:19.040143 [CA 1] Center 36 (8~64) winsize 57
6589 09:58:19.043308 [CA 2] Center 36 (8~64) winsize 57
6590 09:58:19.046934 [CA 3] Center 36 (8~64) winsize 57
6591 09:58:19.050297 [CA 4] Center 36 (8~64) winsize 57
6592 09:58:19.053266 [CA 5] Center 36 (8~64) winsize 57
6593 09:58:19.053406
6594 09:58:19.056838 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6595 09:58:19.056946
6596 09:58:19.059766 [CATrainingPosCal] consider 1 rank data
6597 09:58:19.063295 u2DelayCellTimex100 = 270/100 ps
6598 09:58:19.067339 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6599 09:58:19.070257 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6600 09:58:19.073081 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6601 09:58:19.076750 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 09:58:19.083036 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 09:58:19.086494 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 09:58:19.086609
6605 09:58:19.089770 CA PerBit enable=1, Macro0, CA PI delay=36
6606 09:58:19.089872
6607 09:58:19.093199 [CBTSetCACLKResult] CA Dly = 36
6608 09:58:19.093283 CS Dly: 1 (0~32)
6609 09:58:19.093350 ==
6610 09:58:19.096605 Dram Type= 6, Freq= 0, CH_1, rank 1
6611 09:58:19.099747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6612 09:58:19.103080 ==
6613 09:58:19.106592 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6614 09:58:19.113274 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6615 09:58:19.116743 [CA 0] Center 36 (8~64) winsize 57
6616 09:58:19.119982 [CA 1] Center 36 (8~64) winsize 57
6617 09:58:19.123559 [CA 2] Center 36 (8~64) winsize 57
6618 09:58:19.126541 [CA 3] Center 36 (8~64) winsize 57
6619 09:58:19.130062 [CA 4] Center 36 (8~64) winsize 57
6620 09:58:19.133088 [CA 5] Center 36 (8~64) winsize 57
6621 09:58:19.133177
6622 09:58:19.136399 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6623 09:58:19.136548
6624 09:58:19.139670 [CATrainingPosCal] consider 2 rank data
6625 09:58:19.143241 u2DelayCellTimex100 = 270/100 ps
6626 09:58:19.146540 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 09:58:19.149968 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 09:58:19.153501 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 09:58:19.156603 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 09:58:19.159616 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 09:58:19.162982 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 09:58:19.163067
6633 09:58:19.166266 CA PerBit enable=1, Macro0, CA PI delay=36
6634 09:58:19.166377
6635 09:58:19.169755 [CBTSetCACLKResult] CA Dly = 36
6636 09:58:19.172930 CS Dly: 1 (0~32)
6637 09:58:19.173017
6638 09:58:19.176522 ----->DramcWriteLeveling(PI) begin...
6639 09:58:19.176607 ==
6640 09:58:19.179727 Dram Type= 6, Freq= 0, CH_1, rank 0
6641 09:58:19.182993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6642 09:58:19.183077 ==
6643 09:58:19.186548 Write leveling (Byte 0): 40 => 8
6644 09:58:19.189720 Write leveling (Byte 1): 32 => 0
6645 09:58:19.193222 DramcWriteLeveling(PI) end<-----
6646 09:58:19.193319
6647 09:58:19.193387 ==
6648 09:58:19.196659 Dram Type= 6, Freq= 0, CH_1, rank 0
6649 09:58:19.199865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6650 09:58:19.199950 ==
6651 09:58:19.203031 [Gating] SW mode calibration
6652 09:58:19.210003 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6653 09:58:19.216327 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6654 09:58:19.219870 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6655 09:58:19.226410 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6656 09:58:19.229827 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6657 09:58:19.233030 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6658 09:58:19.236236 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6659 09:58:19.243434 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6660 09:58:19.245978 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6661 09:58:19.249502 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6662 09:58:19.256258 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6663 09:58:19.260011 Total UI for P1: 0, mck2ui 16
6664 09:58:19.262739 best dqsien dly found for B0: ( 0, 14, 24)
6665 09:58:19.266380 Total UI for P1: 0, mck2ui 16
6666 09:58:19.269420 best dqsien dly found for B1: ( 0, 14, 24)
6667 09:58:19.272760 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6668 09:58:19.276245 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6669 09:58:19.276328
6670 09:58:19.279620 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6671 09:58:19.282641 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6672 09:58:19.285881 [Gating] SW calibration Done
6673 09:58:19.285989 ==
6674 09:58:19.289481 Dram Type= 6, Freq= 0, CH_1, rank 0
6675 09:58:19.292699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6676 09:58:19.292782 ==
6677 09:58:19.295868 RX Vref Scan: 0
6678 09:58:19.295953
6679 09:58:19.299254 RX Vref 0 -> 0, step: 1
6680 09:58:19.299341
6681 09:58:19.299406 RX Delay -410 -> 252, step: 16
6682 09:58:19.305891 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6683 09:58:19.309428 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6684 09:58:19.312705 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6685 09:58:19.316144 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6686 09:58:19.322560 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6687 09:58:19.326368 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6688 09:58:19.329588 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6689 09:58:19.332868 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6690 09:58:19.339283 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6691 09:58:19.342566 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6692 09:58:19.345723 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6693 09:58:19.349347 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6694 09:58:19.356069 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6695 09:58:19.359291 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6696 09:58:19.362677 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6697 09:58:19.368961 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6698 09:58:19.369046 ==
6699 09:58:19.372440 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 09:58:19.375697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 09:58:19.375781 ==
6702 09:58:19.375847 DQS Delay:
6703 09:58:19.378930 DQS0 = 27, DQS1 = 43
6704 09:58:19.379013 DQM Delay:
6705 09:58:19.382157 DQM0 = 8, DQM1 = 16
6706 09:58:19.382239 DQ Delay:
6707 09:58:19.385591 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6708 09:58:19.388994 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6709 09:58:19.392357 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6710 09:58:19.395677 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6711 09:58:19.395761
6712 09:58:19.395827
6713 09:58:19.395888 ==
6714 09:58:19.398838 Dram Type= 6, Freq= 0, CH_1, rank 0
6715 09:58:19.402350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6716 09:58:19.402482 ==
6717 09:58:19.402551
6718 09:58:19.402613
6719 09:58:19.405595 TX Vref Scan disable
6720 09:58:19.405680 == TX Byte 0 ==
6721 09:58:19.412208 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6722 09:58:19.415806 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6723 09:58:19.415893 == TX Byte 1 ==
6724 09:58:19.422316 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6725 09:58:19.425450 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6726 09:58:19.425536 ==
6727 09:58:19.428885 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 09:58:19.432031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 09:58:19.432117 ==
6730 09:58:19.432183
6731 09:58:19.432244
6732 09:58:19.435400 TX Vref Scan disable
6733 09:58:19.438972 == TX Byte 0 ==
6734 09:58:19.442035 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6735 09:58:19.445229 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6736 09:58:19.445318 == TX Byte 1 ==
6737 09:58:19.451890 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6738 09:58:19.455467 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6739 09:58:19.455554
6740 09:58:19.455619 [DATLAT]
6741 09:58:19.459061 Freq=400, CH1 RK0
6742 09:58:19.459145
6743 09:58:19.459212 DATLAT Default: 0xf
6744 09:58:19.461857 0, 0xFFFF, sum = 0
6745 09:58:19.461943 1, 0xFFFF, sum = 0
6746 09:58:19.465354 2, 0xFFFF, sum = 0
6747 09:58:19.465439 3, 0xFFFF, sum = 0
6748 09:58:19.468966 4, 0xFFFF, sum = 0
6749 09:58:19.471838 5, 0xFFFF, sum = 0
6750 09:58:19.471925 6, 0xFFFF, sum = 0
6751 09:58:19.475724 7, 0xFFFF, sum = 0
6752 09:58:19.475813 8, 0xFFFF, sum = 0
6753 09:58:19.478855 9, 0xFFFF, sum = 0
6754 09:58:19.478962 10, 0xFFFF, sum = 0
6755 09:58:19.482252 11, 0xFFFF, sum = 0
6756 09:58:19.482421 12, 0xFFFF, sum = 0
6757 09:58:19.485395 13, 0x0, sum = 1
6758 09:58:19.485497 14, 0x0, sum = 2
6759 09:58:19.488600 15, 0x0, sum = 3
6760 09:58:19.488703 16, 0x0, sum = 4
6761 09:58:19.491823 best_step = 14
6762 09:58:19.491912
6763 09:58:19.491979 ==
6764 09:58:19.495286 Dram Type= 6, Freq= 0, CH_1, rank 0
6765 09:58:19.498610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6766 09:58:19.498697 ==
6767 09:58:19.498764 RX Vref Scan: 1
6768 09:58:19.498827
6769 09:58:19.502033 RX Vref 0 -> 0, step: 1
6770 09:58:19.502116
6771 09:58:19.505159 RX Delay -327 -> 252, step: 8
6772 09:58:19.505252
6773 09:58:19.508549 Set Vref, RX VrefLevel [Byte0]: 51
6774 09:58:19.511735 [Byte1]: 50
6775 09:58:19.515646
6776 09:58:19.515728 Final RX Vref Byte 0 = 51 to rank0
6777 09:58:19.519075 Final RX Vref Byte 1 = 50 to rank0
6778 09:58:19.522495 Final RX Vref Byte 0 = 51 to rank1
6779 09:58:19.525811 Final RX Vref Byte 1 = 50 to rank1==
6780 09:58:19.529301 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 09:58:19.535901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 09:58:19.535994 ==
6783 09:58:19.536062 DQS Delay:
6784 09:58:19.539411 DQS0 = 32, DQS1 = 40
6785 09:58:19.539496 DQM Delay:
6786 09:58:19.539562 DQM0 = 11, DQM1 = 13
6787 09:58:19.542217 DQ Delay:
6788 09:58:19.545696 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6789 09:58:19.545782 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6790 09:58:19.549014 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6791 09:58:19.552221 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6792 09:58:19.552310
6793 09:58:19.555782
6794 09:58:19.562329 [DQSOSCAuto] RK0, (LSB)MR18= 0x93ce, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6795 09:58:19.565855 CH1 RK0: MR19=C0C, MR18=93CE
6796 09:58:19.572308 CH1_RK0: MR19=0xC0C, MR18=0x93CE, DQSOSC=384, MR23=63, INC=400, DEC=267
6797 09:58:19.572395 ==
6798 09:58:19.575962 Dram Type= 6, Freq= 0, CH_1, rank 1
6799 09:58:19.578925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6800 09:58:19.579009 ==
6801 09:58:19.582262 [Gating] SW mode calibration
6802 09:58:19.589150 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6803 09:58:19.592303 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6804 09:58:19.599048 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6805 09:58:19.602212 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6806 09:58:19.605602 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6807 09:58:19.612083 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6808 09:58:19.615678 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6809 09:58:19.618817 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6810 09:58:19.625435 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6811 09:58:19.628782 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6812 09:58:19.632091 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6813 09:58:19.635325 Total UI for P1: 0, mck2ui 16
6814 09:58:19.639043 best dqsien dly found for B0: ( 0, 14, 24)
6815 09:58:19.642271 Total UI for P1: 0, mck2ui 16
6816 09:58:19.645614 best dqsien dly found for B1: ( 0, 14, 24)
6817 09:58:19.648616 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6818 09:58:19.652304 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6819 09:58:19.652390
6820 09:58:19.659125 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6821 09:58:19.662174 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6822 09:58:19.665755 [Gating] SW calibration Done
6823 09:58:19.665852 ==
6824 09:58:19.668817 Dram Type= 6, Freq= 0, CH_1, rank 1
6825 09:58:19.672007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6826 09:58:19.672093 ==
6827 09:58:19.672159 RX Vref Scan: 0
6828 09:58:19.672219
6829 09:58:19.675902 RX Vref 0 -> 0, step: 1
6830 09:58:19.675985
6831 09:58:19.678555 RX Delay -410 -> 252, step: 16
6832 09:58:19.682515 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6833 09:58:19.688576 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6834 09:58:19.692085 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6835 09:58:19.695231 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6836 09:58:19.698557 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6837 09:58:19.705473 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6838 09:58:19.708675 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6839 09:58:19.711716 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6840 09:58:19.715724 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6841 09:58:19.721870 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6842 09:58:19.725257 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6843 09:58:19.728518 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6844 09:58:19.731865 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6845 09:58:19.738678 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6846 09:58:19.741913 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6847 09:58:19.744975 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6848 09:58:19.745062 ==
6849 09:58:19.748292 Dram Type= 6, Freq= 0, CH_1, rank 1
6850 09:58:19.751878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 09:58:19.755195 ==
6852 09:58:19.755285 DQS Delay:
6853 09:58:19.755370 DQS0 = 35, DQS1 = 35
6854 09:58:19.759084 DQM Delay:
6855 09:58:19.759174 DQM0 = 16, DQM1 = 13
6856 09:58:19.761529 DQ Delay:
6857 09:58:19.764961 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6858 09:58:19.765052 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6859 09:58:19.768321 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6860 09:58:19.772002 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6861 09:58:19.772100
6862 09:58:19.775109
6863 09:58:19.775199 ==
6864 09:58:19.778098 Dram Type= 6, Freq= 0, CH_1, rank 1
6865 09:58:19.782267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6866 09:58:19.782371 ==
6867 09:58:19.782486
6868 09:58:19.782548
6869 09:58:19.784918 TX Vref Scan disable
6870 09:58:19.785002 == TX Byte 0 ==
6871 09:58:19.788037 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6872 09:58:19.795001 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6873 09:58:19.795143 == TX Byte 1 ==
6874 09:58:19.797926 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6875 09:58:19.804783 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6876 09:58:19.804934 ==
6877 09:58:19.808172 Dram Type= 6, Freq= 0, CH_1, rank 1
6878 09:58:19.811383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 09:58:19.811483 ==
6880 09:58:19.811551
6881 09:58:19.811612
6882 09:58:19.815053 TX Vref Scan disable
6883 09:58:19.815143 == TX Byte 0 ==
6884 09:58:19.821273 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6885 09:58:19.825120 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6886 09:58:19.825222 == TX Byte 1 ==
6887 09:58:19.828123 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6888 09:58:19.834847 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6889 09:58:19.834973
6890 09:58:19.835046 [DATLAT]
6891 09:58:19.838226 Freq=400, CH1 RK1
6892 09:58:19.838347
6893 09:58:19.838489 DATLAT Default: 0xe
6894 09:58:19.841273 0, 0xFFFF, sum = 0
6895 09:58:19.841384 1, 0xFFFF, sum = 0
6896 09:58:19.844790 2, 0xFFFF, sum = 0
6897 09:58:19.844902 3, 0xFFFF, sum = 0
6898 09:58:19.847935 4, 0xFFFF, sum = 0
6899 09:58:19.848022 5, 0xFFFF, sum = 0
6900 09:58:19.851135 6, 0xFFFF, sum = 0
6901 09:58:19.851221 7, 0xFFFF, sum = 0
6902 09:58:19.855142 8, 0xFFFF, sum = 0
6903 09:58:19.855228 9, 0xFFFF, sum = 0
6904 09:58:19.857808 10, 0xFFFF, sum = 0
6905 09:58:19.857894 11, 0xFFFF, sum = 0
6906 09:58:19.861209 12, 0xFFFF, sum = 0
6907 09:58:19.861295 13, 0x0, sum = 1
6908 09:58:19.864631 14, 0x0, sum = 2
6909 09:58:19.864715 15, 0x0, sum = 3
6910 09:58:19.867834 16, 0x0, sum = 4
6911 09:58:19.867919 best_step = 14
6912 09:58:19.867985
6913 09:58:19.868046 ==
6914 09:58:19.870973 Dram Type= 6, Freq= 0, CH_1, rank 1
6915 09:58:19.878081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6916 09:58:19.878168 ==
6917 09:58:19.878234 RX Vref Scan: 0
6918 09:58:19.878297
6919 09:58:19.881123 RX Vref 0 -> 0, step: 1
6920 09:58:19.881206
6921 09:58:19.884594 RX Delay -311 -> 252, step: 8
6922 09:58:19.891123 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6923 09:58:19.894661 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6924 09:58:19.897912 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6925 09:58:19.901081 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6926 09:58:19.907622 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6927 09:58:19.911418 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6928 09:58:19.914255 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6929 09:58:19.917419 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6930 09:58:19.924782 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6931 09:58:19.927995 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6932 09:58:19.931140 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6933 09:58:19.934341 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6934 09:58:19.940839 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6935 09:58:19.944302 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6936 09:58:19.947743 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6937 09:58:19.951050 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6938 09:58:19.954328 ==
6939 09:58:19.954436 Dram Type= 6, Freq= 0, CH_1, rank 1
6940 09:58:19.960900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6941 09:58:19.960984 ==
6942 09:58:19.961051 DQS Delay:
6943 09:58:19.964179 DQS0 = 32, DQS1 = 36
6944 09:58:19.964263 DQM Delay:
6945 09:58:19.968023 DQM0 = 12, DQM1 = 12
6946 09:58:19.968108 DQ Delay:
6947 09:58:19.970885 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6948 09:58:19.974283 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =8
6949 09:58:19.977485 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6950 09:58:19.980875 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
6951 09:58:19.980961
6952 09:58:19.981026
6953 09:58:19.987421 [DQSOSCAuto] RK1, (LSB)MR18= 0xad55, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
6954 09:58:19.991034 CH1 RK1: MR19=C0C, MR18=AD55
6955 09:58:19.997371 CH1_RK1: MR19=0xC0C, MR18=0xAD55, DQSOSC=388, MR23=63, INC=392, DEC=261
6956 09:58:20.000875 [RxdqsGatingPostProcess] freq 400
6957 09:58:20.004029 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6958 09:58:20.008144 best DQS0 dly(2T, 0.5T) = (0, 10)
6959 09:58:20.010675 best DQS1 dly(2T, 0.5T) = (0, 10)
6960 09:58:20.014096 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6961 09:58:20.017616 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6962 09:58:20.020776 best DQS0 dly(2T, 0.5T) = (0, 10)
6963 09:58:20.024314 best DQS1 dly(2T, 0.5T) = (0, 10)
6964 09:58:20.027351 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6965 09:58:20.030850 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6966 09:58:20.034171 Pre-setting of DQS Precalculation
6967 09:58:20.037679 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6968 09:58:20.044111 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6969 09:58:20.054494 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6970 09:58:20.054582
6971 09:58:20.054648
6972 09:58:20.057365 [Calibration Summary] 800 Mbps
6973 09:58:20.057450 CH 0, Rank 0
6974 09:58:20.060710 SW Impedance : PASS
6975 09:58:20.060793 DUTY Scan : NO K
6976 09:58:20.063906 ZQ Calibration : PASS
6977 09:58:20.067404 Jitter Meter : NO K
6978 09:58:20.067487 CBT Training : PASS
6979 09:58:20.070711 Write leveling : PASS
6980 09:58:20.070793 RX DQS gating : PASS
6981 09:58:20.073906 RX DQ/DQS(RDDQC) : PASS
6982 09:58:20.077138 TX DQ/DQS : PASS
6983 09:58:20.077222 RX DATLAT : PASS
6984 09:58:20.080743 RX DQ/DQS(Engine): PASS
6985 09:58:20.084339 TX OE : NO K
6986 09:58:20.084422 All Pass.
6987 09:58:20.084487
6988 09:58:20.084549 CH 0, Rank 1
6989 09:58:20.087030 SW Impedance : PASS
6990 09:58:20.090397 DUTY Scan : NO K
6991 09:58:20.090494 ZQ Calibration : PASS
6992 09:58:20.094276 Jitter Meter : NO K
6993 09:58:20.097024 CBT Training : PASS
6994 09:58:20.097107 Write leveling : NO K
6995 09:58:20.100867 RX DQS gating : PASS
6996 09:58:20.103922 RX DQ/DQS(RDDQC) : PASS
6997 09:58:20.104004 TX DQ/DQS : PASS
6998 09:58:20.107407 RX DATLAT : PASS
6999 09:58:20.110520 RX DQ/DQS(Engine): PASS
7000 09:58:20.110604 TX OE : NO K
7001 09:58:20.113775 All Pass.
7002 09:58:20.113858
7003 09:58:20.113923 CH 1, Rank 0
7004 09:58:20.117067 SW Impedance : PASS
7005 09:58:20.117150 DUTY Scan : NO K
7006 09:58:20.120494 ZQ Calibration : PASS
7007 09:58:20.123967 Jitter Meter : NO K
7008 09:58:20.124051 CBT Training : PASS
7009 09:58:20.127381 Write leveling : PASS
7010 09:58:20.127465 RX DQS gating : PASS
7011 09:58:20.131163 RX DQ/DQS(RDDQC) : PASS
7012 09:58:20.133955 TX DQ/DQS : PASS
7013 09:58:20.134040 RX DATLAT : PASS
7014 09:58:20.137377 RX DQ/DQS(Engine): PASS
7015 09:58:20.140712 TX OE : NO K
7016 09:58:20.140796 All Pass.
7017 09:58:20.140863
7018 09:58:20.140925 CH 1, Rank 1
7019 09:58:20.143651 SW Impedance : PASS
7020 09:58:20.147001 DUTY Scan : NO K
7021 09:58:20.147084 ZQ Calibration : PASS
7022 09:58:20.150566 Jitter Meter : NO K
7023 09:58:20.153711 CBT Training : PASS
7024 09:58:20.153794 Write leveling : NO K
7025 09:58:20.157261 RX DQS gating : PASS
7026 09:58:20.160379 RX DQ/DQS(RDDQC) : PASS
7027 09:58:20.160462 TX DQ/DQS : PASS
7028 09:58:20.163521 RX DATLAT : PASS
7029 09:58:20.166921 RX DQ/DQS(Engine): PASS
7030 09:58:20.167005 TX OE : NO K
7031 09:58:20.167071 All Pass.
7032 09:58:20.170047
7033 09:58:20.170131 DramC Write-DBI off
7034 09:58:20.173737 PER_BANK_REFRESH: Hybrid Mode
7035 09:58:20.173821 TX_TRACKING: ON
7036 09:58:20.183500 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7037 09:58:20.186965 [FAST_K] Save calibration result to emmc
7038 09:58:20.190244 dramc_set_vcore_voltage set vcore to 725000
7039 09:58:20.193478 Read voltage for 1600, 0
7040 09:58:20.193562 Vio18 = 0
7041 09:58:20.196912 Vcore = 725000
7042 09:58:20.196995 Vdram = 0
7043 09:58:20.197062 Vddq = 0
7044 09:58:20.197123 Vmddr = 0
7045 09:58:20.203473 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7046 09:58:20.210069 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7047 09:58:20.210154 MEM_TYPE=3, freq_sel=13
7048 09:58:20.213604 sv_algorithm_assistance_LP4_3733
7049 09:58:20.216825 ============ PULL DRAM RESETB DOWN ============
7050 09:58:20.223501 ========== PULL DRAM RESETB DOWN end =========
7051 09:58:20.226705 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7052 09:58:20.230094 ===================================
7053 09:58:20.233350 LPDDR4 DRAM CONFIGURATION
7054 09:58:20.237050 ===================================
7055 09:58:20.237138 EX_ROW_EN[0] = 0x0
7056 09:58:20.240095 EX_ROW_EN[1] = 0x0
7057 09:58:20.240183 LP4Y_EN = 0x0
7058 09:58:20.243203 WORK_FSP = 0x1
7059 09:58:20.243288 WL = 0x5
7060 09:58:20.246938 RL = 0x5
7061 09:58:20.250440 BL = 0x2
7062 09:58:20.250524 RPST = 0x0
7063 09:58:20.253513 RD_PRE = 0x0
7064 09:58:20.253596 WR_PRE = 0x1
7065 09:58:20.257528 WR_PST = 0x1
7066 09:58:20.257612 DBI_WR = 0x0
7067 09:58:20.260313 DBI_RD = 0x0
7068 09:58:20.260397 OTF = 0x1
7069 09:58:20.263379 ===================================
7070 09:58:20.266660 ===================================
7071 09:58:20.269987 ANA top config
7072 09:58:20.270071 ===================================
7073 09:58:20.273371 DLL_ASYNC_EN = 0
7074 09:58:20.276852 ALL_SLAVE_EN = 0
7075 09:58:20.280233 NEW_RANK_MODE = 1
7076 09:58:20.283359 DLL_IDLE_MODE = 1
7077 09:58:20.283444 LP45_APHY_COMB_EN = 1
7078 09:58:20.286693 TX_ODT_DIS = 0
7079 09:58:20.290022 NEW_8X_MODE = 1
7080 09:58:20.293632 ===================================
7081 09:58:20.296868 ===================================
7082 09:58:20.299945 data_rate = 3200
7083 09:58:20.303770 CKR = 1
7084 09:58:20.303855 DQ_P2S_RATIO = 8
7085 09:58:20.307983 ===================================
7086 09:58:20.309712 CA_P2S_RATIO = 8
7087 09:58:20.313300 DQ_CA_OPEN = 0
7088 09:58:20.316360 DQ_SEMI_OPEN = 0
7089 09:58:20.319996 CA_SEMI_OPEN = 0
7090 09:58:20.323056 CA_FULL_RATE = 0
7091 09:58:20.323139 DQ_CKDIV4_EN = 0
7092 09:58:20.326741 CA_CKDIV4_EN = 0
7093 09:58:20.329583 CA_PREDIV_EN = 0
7094 09:58:20.333057 PH8_DLY = 12
7095 09:58:20.336800 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7096 09:58:20.340032 DQ_AAMCK_DIV = 4
7097 09:58:20.340117 CA_AAMCK_DIV = 4
7098 09:58:20.343378 CA_ADMCK_DIV = 4
7099 09:58:20.346396 DQ_TRACK_CA_EN = 0
7100 09:58:20.349503 CA_PICK = 1600
7101 09:58:20.353127 CA_MCKIO = 1600
7102 09:58:20.356164 MCKIO_SEMI = 0
7103 09:58:20.359802 PLL_FREQ = 3068
7104 09:58:20.363463 DQ_UI_PI_RATIO = 32
7105 09:58:20.363547 CA_UI_PI_RATIO = 0
7106 09:58:20.366341 ===================================
7107 09:58:20.369434 ===================================
7108 09:58:20.373022 memory_type:LPDDR4
7109 09:58:20.376506 GP_NUM : 10
7110 09:58:20.376588 SRAM_EN : 1
7111 09:58:20.379551 MD32_EN : 0
7112 09:58:20.382888 ===================================
7113 09:58:20.386183 [ANA_INIT] >>>>>>>>>>>>>>
7114 09:58:20.386267 <<<<<< [CONFIGURE PHASE]: ANA_TX
7115 09:58:20.393052 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7116 09:58:20.396657 ===================================
7117 09:58:20.396742 data_rate = 3200,PCW = 0X7600
7118 09:58:20.399465 ===================================
7119 09:58:20.403025 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7120 09:58:20.409565 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7121 09:58:20.416061 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7122 09:58:20.419665 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7123 09:58:20.422542 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7124 09:58:20.425998 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7125 09:58:20.429620 [ANA_INIT] flow start
7126 09:58:20.429704 [ANA_INIT] PLL >>>>>>>>
7127 09:58:20.432996 [ANA_INIT] PLL <<<<<<<<
7128 09:58:20.435912 [ANA_INIT] MIDPI >>>>>>>>
7129 09:58:20.439468 [ANA_INIT] MIDPI <<<<<<<<
7130 09:58:20.439552 [ANA_INIT] DLL >>>>>>>>
7131 09:58:20.442963 [ANA_INIT] DLL <<<<<<<<
7132 09:58:20.443049 [ANA_INIT] flow end
7133 09:58:20.449282 ============ LP4 DIFF to SE enter ============
7134 09:58:20.452759 ============ LP4 DIFF to SE exit ============
7135 09:58:20.456005 [ANA_INIT] <<<<<<<<<<<<<
7136 09:58:20.459016 [Flow] Enable top DCM control >>>>>
7137 09:58:20.462691 [Flow] Enable top DCM control <<<<<
7138 09:58:20.466111 Enable DLL master slave shuffle
7139 09:58:20.469134 ==============================================================
7140 09:58:20.472704 Gating Mode config
7141 09:58:20.475579 ==============================================================
7142 09:58:20.479325 Config description:
7143 09:58:20.489069 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7144 09:58:20.495674 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7145 09:58:20.498956 SELPH_MODE 0: By rank 1: By Phase
7146 09:58:20.505656 ==============================================================
7147 09:58:20.508850 GAT_TRACK_EN = 1
7148 09:58:20.512323 RX_GATING_MODE = 2
7149 09:58:20.516219 RX_GATING_TRACK_MODE = 2
7150 09:58:20.519352 SELPH_MODE = 1
7151 09:58:20.522257 PICG_EARLY_EN = 1
7152 09:58:20.522368 VALID_LAT_VALUE = 1
7153 09:58:20.529173 ==============================================================
7154 09:58:20.532176 Enter into Gating configuration >>>>
7155 09:58:20.535537 Exit from Gating configuration <<<<
7156 09:58:20.539046 Enter into DVFS_PRE_config >>>>>
7157 09:58:20.548908 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7158 09:58:20.552157 Exit from DVFS_PRE_config <<<<<
7159 09:58:20.555830 Enter into PICG configuration >>>>
7160 09:58:20.559092 Exit from PICG configuration <<<<
7161 09:58:20.562318 [RX_INPUT] configuration >>>>>
7162 09:58:20.565907 [RX_INPUT] configuration <<<<<
7163 09:58:20.568801 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7164 09:58:20.575714 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7165 09:58:20.582052 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7166 09:58:20.588932 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7167 09:58:20.595473 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7168 09:58:20.599249 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7169 09:58:20.605277 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7170 09:58:20.608813 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7171 09:58:20.612143 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7172 09:58:20.615684 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7173 09:58:20.621866 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7174 09:58:20.625499 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7175 09:58:20.628745 ===================================
7176 09:58:20.631995 LPDDR4 DRAM CONFIGURATION
7177 09:58:20.635347 ===================================
7178 09:58:20.635431 EX_ROW_EN[0] = 0x0
7179 09:58:20.639159 EX_ROW_EN[1] = 0x0
7180 09:58:20.639260 LP4Y_EN = 0x0
7181 09:58:20.641865 WORK_FSP = 0x1
7182 09:58:20.641961 WL = 0x5
7183 09:58:20.645605 RL = 0x5
7184 09:58:20.645691 BL = 0x2
7185 09:58:20.648734 RPST = 0x0
7186 09:58:20.648816 RD_PRE = 0x0
7187 09:58:20.652576 WR_PRE = 0x1
7188 09:58:20.655571 WR_PST = 0x1
7189 09:58:20.655654 DBI_WR = 0x0
7190 09:58:20.658799 DBI_RD = 0x0
7191 09:58:20.658880 OTF = 0x1
7192 09:58:20.662076 ===================================
7193 09:58:20.665881 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7194 09:58:20.668529 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7195 09:58:20.675346 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7196 09:58:20.678833 ===================================
7197 09:58:20.682126 LPDDR4 DRAM CONFIGURATION
7198 09:58:20.685244 ===================================
7199 09:58:20.685325 EX_ROW_EN[0] = 0x10
7200 09:58:20.688586 EX_ROW_EN[1] = 0x0
7201 09:58:20.688666 LP4Y_EN = 0x0
7202 09:58:20.691899 WORK_FSP = 0x1
7203 09:58:20.691981 WL = 0x5
7204 09:58:20.695413 RL = 0x5
7205 09:58:20.695494 BL = 0x2
7206 09:58:20.698578 RPST = 0x0
7207 09:58:20.698658 RD_PRE = 0x0
7208 09:58:20.702058 WR_PRE = 0x1
7209 09:58:20.702140 WR_PST = 0x1
7210 09:58:20.705469 DBI_WR = 0x0
7211 09:58:20.705549 DBI_RD = 0x0
7212 09:58:20.708551 OTF = 0x1
7213 09:58:20.711786 ===================================
7214 09:58:20.718693 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7215 09:58:20.718776 ==
7216 09:58:20.722349 Dram Type= 6, Freq= 0, CH_0, rank 0
7217 09:58:20.725150 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7218 09:58:20.725247 ==
7219 09:58:20.728787 [Duty_Offset_Calibration]
7220 09:58:20.728867 B0:2 B1:0 CA:1
7221 09:58:20.728931
7222 09:58:20.731660 [DutyScan_Calibration_Flow] k_type=0
7223 09:58:20.742096
7224 09:58:20.742224 ==CLK 0==
7225 09:58:20.745452 Final CLK duty delay cell = -4
7226 09:58:20.748718 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7227 09:58:20.752068 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7228 09:58:20.755379 [-4] AVG Duty = 4937%(X100)
7229 09:58:20.755461
7230 09:58:20.758719 CH0 CLK Duty spec in!! Max-Min= 187%
7231 09:58:20.761761 [DutyScan_Calibration_Flow] ====Done====
7232 09:58:20.761843
7233 09:58:20.765003 [DutyScan_Calibration_Flow] k_type=1
7234 09:58:20.781446
7235 09:58:20.781558 ==DQS 0 ==
7236 09:58:20.784696 Final DQS duty delay cell = 0
7237 09:58:20.787976 [0] MAX Duty = 5249%(X100), DQS PI = 32
7238 09:58:20.791236 [0] MIN Duty = 4969%(X100), DQS PI = 0
7239 09:58:20.794746 [0] AVG Duty = 5109%(X100)
7240 09:58:20.794828
7241 09:58:20.794892 ==DQS 1 ==
7242 09:58:20.797795 Final DQS duty delay cell = -4
7243 09:58:20.801308 [-4] MAX Duty = 5125%(X100), DQS PI = 46
7244 09:58:20.804210 [-4] MIN Duty = 4844%(X100), DQS PI = 6
7245 09:58:20.808120 [-4] AVG Duty = 4984%(X100)
7246 09:58:20.808201
7247 09:58:20.810990 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7248 09:58:20.811072
7249 09:58:20.814330 CH0 DQS 1 Duty spec in!! Max-Min= 281%
7250 09:58:20.817779 [DutyScan_Calibration_Flow] ====Done====
7251 09:58:20.817861
7252 09:58:20.821159 [DutyScan_Calibration_Flow] k_type=3
7253 09:58:20.838669
7254 09:58:20.838887 ==DQM 0 ==
7255 09:58:20.842300 Final DQM duty delay cell = 0
7256 09:58:20.845282 [0] MAX Duty = 5124%(X100), DQS PI = 26
7257 09:58:20.849216 [0] MIN Duty = 4844%(X100), DQS PI = 0
7258 09:58:20.849301 [0] AVG Duty = 4984%(X100)
7259 09:58:20.852112
7260 09:58:20.852194 ==DQM 1 ==
7261 09:58:20.855404 Final DQM duty delay cell = 0
7262 09:58:20.858458 [0] MAX Duty = 5249%(X100), DQS PI = 28
7263 09:58:20.862024 [0] MIN Duty = 5031%(X100), DQS PI = 10
7264 09:58:20.865293 [0] AVG Duty = 5140%(X100)
7265 09:58:20.865376
7266 09:58:20.868519 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7267 09:58:20.868601
7268 09:58:20.872110 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7269 09:58:20.875217 [DutyScan_Calibration_Flow] ====Done====
7270 09:58:20.875299
7271 09:58:20.878375 [DutyScan_Calibration_Flow] k_type=2
7272 09:58:20.896084
7273 09:58:20.896185 ==DQ 0 ==
7274 09:58:20.899139 Final DQ duty delay cell = 0
7275 09:58:20.902430 [0] MAX Duty = 5124%(X100), DQS PI = 34
7276 09:58:20.905921 [0] MIN Duty = 5000%(X100), DQS PI = 0
7277 09:58:20.906003 [0] AVG Duty = 5062%(X100)
7278 09:58:20.906068
7279 09:58:20.909215 ==DQ 1 ==
7280 09:58:20.912489 Final DQ duty delay cell = 0
7281 09:58:20.915718 [0] MAX Duty = 4969%(X100), DQS PI = 42
7282 09:58:20.919233 [0] MIN Duty = 4875%(X100), DQS PI = 0
7283 09:58:20.919316 [0] AVG Duty = 4922%(X100)
7284 09:58:20.919381
7285 09:58:20.922677 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7286 09:58:20.926087
7287 09:58:20.926168 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7288 09:58:20.932359 [DutyScan_Calibration_Flow] ====Done====
7289 09:58:20.932444 ==
7290 09:58:20.935820 Dram Type= 6, Freq= 0, CH_1, rank 0
7291 09:58:20.939151 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7292 09:58:20.939237 ==
7293 09:58:20.942083 [Duty_Offset_Calibration]
7294 09:58:20.942167 B0:0 B1:-1 CA:2
7295 09:58:20.942228
7296 09:58:20.945991 [DutyScan_Calibration_Flow] k_type=0
7297 09:58:20.956237
7298 09:58:20.956324 ==CLK 0==
7299 09:58:20.959574 Final CLK duty delay cell = 0
7300 09:58:20.962840 [0] MAX Duty = 5187%(X100), DQS PI = 14
7301 09:58:20.965950 [0] MIN Duty = 4906%(X100), DQS PI = 46
7302 09:58:20.966031 [0] AVG Duty = 5046%(X100)
7303 09:58:20.969261
7304 09:58:20.972766 CH1 CLK Duty spec in!! Max-Min= 281%
7305 09:58:20.975877 [DutyScan_Calibration_Flow] ====Done====
7306 09:58:20.975956
7307 09:58:20.979327 [DutyScan_Calibration_Flow] k_type=1
7308 09:58:20.995622
7309 09:58:20.995761 ==DQS 0 ==
7310 09:58:20.998905 Final DQS duty delay cell = 0
7311 09:58:21.002051 [0] MAX Duty = 5124%(X100), DQS PI = 26
7312 09:58:21.005825 [0] MIN Duty = 4969%(X100), DQS PI = 58
7313 09:58:21.005908 [0] AVG Duty = 5046%(X100)
7314 09:58:21.009003
7315 09:58:21.009083 ==DQS 1 ==
7316 09:58:21.012199 Final DQS duty delay cell = 0
7317 09:58:21.015512 [0] MAX Duty = 5187%(X100), DQS PI = 0
7318 09:58:21.019020 [0] MIN Duty = 4844%(X100), DQS PI = 34
7319 09:58:21.019100 [0] AVG Duty = 5015%(X100)
7320 09:58:21.022337
7321 09:58:21.025663 CH1 DQS 0 Duty spec in!! Max-Min= 155%
7322 09:58:21.025744
7323 09:58:21.028748 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7324 09:58:21.032121 [DutyScan_Calibration_Flow] ====Done====
7325 09:58:21.032203
7326 09:58:21.035424 [DutyScan_Calibration_Flow] k_type=3
7327 09:58:21.053080
7328 09:58:21.053194 ==DQM 0 ==
7329 09:58:21.056577 Final DQM duty delay cell = 4
7330 09:58:21.059659 [4] MAX Duty = 5125%(X100), DQS PI = 6
7331 09:58:21.062986 [4] MIN Duty = 5000%(X100), DQS PI = 34
7332 09:58:21.066881 [4] AVG Duty = 5062%(X100)
7333 09:58:21.066963
7334 09:58:21.067027 ==DQM 1 ==
7335 09:58:21.069706 Final DQM duty delay cell = 0
7336 09:58:21.073131 [0] MAX Duty = 5281%(X100), DQS PI = 60
7337 09:58:21.076366 [0] MIN Duty = 4876%(X100), DQS PI = 34
7338 09:58:21.079887 [0] AVG Duty = 5078%(X100)
7339 09:58:21.079969
7340 09:58:21.083033 CH1 DQM 0 Duty spec in!! Max-Min= 125%
7341 09:58:21.083117
7342 09:58:21.086441 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7343 09:58:21.090024 [DutyScan_Calibration_Flow] ====Done====
7344 09:58:21.090105
7345 09:58:21.093066 [DutyScan_Calibration_Flow] k_type=2
7346 09:58:21.110276
7347 09:58:21.110390 ==DQ 0 ==
7348 09:58:21.113446 Final DQ duty delay cell = 0
7349 09:58:21.117023 [0] MAX Duty = 5093%(X100), DQS PI = 18
7350 09:58:21.120258 [0] MIN Duty = 4969%(X100), DQS PI = 46
7351 09:58:21.120339 [0] AVG Duty = 5031%(X100)
7352 09:58:21.123577
7353 09:58:21.123658 ==DQ 1 ==
7354 09:58:21.126798 Final DQ duty delay cell = 0
7355 09:58:21.130327 [0] MAX Duty = 5062%(X100), DQS PI = 2
7356 09:58:21.133821 [0] MIN Duty = 4813%(X100), DQS PI = 34
7357 09:58:21.133903 [0] AVG Duty = 4937%(X100)
7358 09:58:21.133966
7359 09:58:21.136618 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7360 09:58:21.140595
7361 09:58:21.143438 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7362 09:58:21.146667 [DutyScan_Calibration_Flow] ====Done====
7363 09:58:21.150353 nWR fixed to 30
7364 09:58:21.150491 [ModeRegInit_LP4] CH0 RK0
7365 09:58:21.153114 [ModeRegInit_LP4] CH0 RK1
7366 09:58:21.156497 [ModeRegInit_LP4] CH1 RK0
7367 09:58:21.159667 [ModeRegInit_LP4] CH1 RK1
7368 09:58:21.159750 match AC timing 5
7369 09:58:21.163345 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7370 09:58:21.166779 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7371 09:58:21.172985 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7372 09:58:21.176626 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7373 09:58:21.183156 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7374 09:58:21.183251 [MiockJmeterHQA]
7375 09:58:21.183315
7376 09:58:21.186742 [DramcMiockJmeter] u1RxGatingPI = 0
7377 09:58:21.189865 0 : 4255, 4027
7378 09:58:21.189949 4 : 4257, 4029
7379 09:58:21.190013 8 : 4370, 4142
7380 09:58:21.193303 12 : 4253, 4027
7381 09:58:21.193384 16 : 4258, 4031
7382 09:58:21.196960 20 : 4257, 4029
7383 09:58:21.197043 24 : 4252, 4027
7384 09:58:21.199979 28 : 4253, 4027
7385 09:58:21.200061 32 : 4253, 4026
7386 09:58:21.203241 36 : 4257, 4032
7387 09:58:21.203323 40 : 4252, 4027
7388 09:58:21.203388 44 : 4253, 4026
7389 09:58:21.206772 48 : 4366, 4140
7390 09:58:21.206854 52 : 4255, 4030
7391 09:58:21.209638 56 : 4257, 4032
7392 09:58:21.209719 60 : 4252, 4026
7393 09:58:21.213053 64 : 4361, 4137
7394 09:58:21.213135 68 : 4250, 4027
7395 09:58:21.213199 72 : 4250, 4027
7396 09:58:21.216385 76 : 4250, 4027
7397 09:58:21.216465 80 : 4250, 4027
7398 09:58:21.219948 84 : 4250, 4026
7399 09:58:21.220030 88 : 4252, 3712
7400 09:58:21.222924 92 : 4360, 0
7401 09:58:21.223006 96 : 4363, 0
7402 09:58:21.223070 100 : 4365, 0
7403 09:58:21.226591 104 : 4361, 0
7404 09:58:21.226673 108 : 4361, 0
7405 09:58:21.229804 112 : 4250, 0
7406 09:58:21.229886 116 : 4250, 0
7407 09:58:21.229949 120 : 4250, 0
7408 09:58:21.232955 124 : 4250, 0
7409 09:58:21.233037 128 : 4252, 0
7410 09:58:21.233100 132 : 4250, 0
7411 09:58:21.236404 136 : 4254, 0
7412 09:58:21.236487 140 : 4253, 0
7413 09:58:21.239533 144 : 4361, 0
7414 09:58:21.239616 148 : 4250, 0
7415 09:58:21.239681 152 : 4250, 0
7416 09:58:21.242807 156 : 4250, 0
7417 09:58:21.242889 160 : 4250, 0
7418 09:58:21.246172 164 : 4363, 0
7419 09:58:21.246261 168 : 4250, 0
7420 09:58:21.246325 172 : 4250, 0
7421 09:58:21.249754 176 : 4249, 0
7422 09:58:21.249837 180 : 4253, 0
7423 09:58:21.253032 184 : 4250, 0
7424 09:58:21.253116 188 : 4250, 0
7425 09:58:21.253180 192 : 4252, 0
7426 09:58:21.256319 196 : 4361, 0
7427 09:58:21.256402 200 : 4249, 1
7428 09:58:21.259695 204 : 4361, 2138
7429 09:58:21.259780 208 : 4250, 4027
7430 09:58:21.262761 212 : 4252, 4029
7431 09:58:21.262843 216 : 4250, 4027
7432 09:58:21.262908 220 : 4252, 4029
7433 09:58:21.266428 224 : 4250, 4027
7434 09:58:21.266537 228 : 4361, 4137
7435 09:58:21.269556 232 : 4360, 4138
7436 09:58:21.269638 236 : 4250, 4026
7437 09:58:21.273081 240 : 4250, 4027
7438 09:58:21.273164 244 : 4361, 4138
7439 09:58:21.276039 248 : 4250, 4027
7440 09:58:21.276121 252 : 4250, 4027
7441 09:58:21.279786 256 : 4250, 4027
7442 09:58:21.279869 260 : 4250, 4027
7443 09:58:21.282966 264 : 4250, 4026
7444 09:58:21.283051 268 : 4250, 4027
7445 09:58:21.286564 272 : 4253, 4029
7446 09:58:21.286647 276 : 4250, 4027
7447 09:58:21.286711 280 : 4361, 4137
7448 09:58:21.289689 284 : 4361, 4137
7449 09:58:21.289773 288 : 4250, 4027
7450 09:58:21.292665 292 : 4250, 4027
7451 09:58:21.292748 296 : 4361, 4138
7452 09:58:21.296305 300 : 4250, 4027
7453 09:58:21.296389 304 : 4250, 4027
7454 09:58:21.299243 308 : 4252, 4030
7455 09:58:21.299326 312 : 4250, 4006
7456 09:58:21.302409 316 : 4250, 2322
7457 09:58:21.302542 320 : 4249, 29
7458 09:58:21.302606
7459 09:58:21.306032 MIOCK jitter meter ch=0
7460 09:58:21.306114
7461 09:58:21.309603 1T = (320-92) = 228 dly cells
7462 09:58:21.312482 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7463 09:58:21.312566 ==
7464 09:58:21.315784 Dram Type= 6, Freq= 0, CH_0, rank 0
7465 09:58:21.322992 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7466 09:58:21.323093 ==
7467 09:58:21.326347 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7468 09:58:21.332774 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7469 09:58:21.335955 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7470 09:58:21.342138 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7471 09:58:21.350653 [CA 0] Center 42 (12~72) winsize 61
7472 09:58:21.353629 [CA 1] Center 42 (12~72) winsize 61
7473 09:58:21.356915 [CA 2] Center 37 (7~67) winsize 61
7474 09:58:21.360362 [CA 3] Center 37 (7~67) winsize 61
7475 09:58:21.363427 [CA 4] Center 36 (6~66) winsize 61
7476 09:58:21.366595 [CA 5] Center 35 (5~65) winsize 61
7477 09:58:21.366685
7478 09:58:21.370008 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7479 09:58:21.370095
7480 09:58:21.373421 [CATrainingPosCal] consider 1 rank data
7481 09:58:21.376826 u2DelayCellTimex100 = 285/100 ps
7482 09:58:21.380488 CA0 delay=42 (12~72),Diff = 7 PI (23 cell)
7483 09:58:21.387173 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7484 09:58:21.390161 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7485 09:58:21.393389 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7486 09:58:21.396590 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7487 09:58:21.399922 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7488 09:58:21.400019
7489 09:58:21.403354 CA PerBit enable=1, Macro0, CA PI delay=35
7490 09:58:21.403435
7491 09:58:21.406763 [CBTSetCACLKResult] CA Dly = 35
7492 09:58:21.409885 CS Dly: 10 (0~41)
7493 09:58:21.413214 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7494 09:58:21.417022 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7495 09:58:21.417106 ==
7496 09:58:21.420135 Dram Type= 6, Freq= 0, CH_0, rank 1
7497 09:58:21.423281 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7498 09:58:21.426755 ==
7499 09:58:21.430279 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7500 09:58:21.433195 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7501 09:58:21.440212 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7502 09:58:21.443355 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7503 09:58:21.453793 [CA 0] Center 43 (13~73) winsize 61
7504 09:58:21.457136 [CA 1] Center 43 (13~73) winsize 61
7505 09:58:21.460178 [CA 2] Center 37 (8~67) winsize 60
7506 09:58:21.463396 [CA 3] Center 38 (9~68) winsize 60
7507 09:58:21.467155 [CA 4] Center 36 (6~67) winsize 62
7508 09:58:21.470319 [CA 5] Center 36 (7~66) winsize 60
7509 09:58:21.470443
7510 09:58:21.473530 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7511 09:58:21.473613
7512 09:58:21.476926 [CATrainingPosCal] consider 2 rank data
7513 09:58:21.480209 u2DelayCellTimex100 = 285/100 ps
7514 09:58:21.483818 CA0 delay=42 (13~72),Diff = 6 PI (20 cell)
7515 09:58:21.490656 CA1 delay=42 (13~72),Diff = 6 PI (20 cell)
7516 09:58:21.493672 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
7517 09:58:21.497302 CA3 delay=38 (9~67),Diff = 2 PI (6 cell)
7518 09:58:21.500742 CA4 delay=36 (6~66),Diff = 0 PI (0 cell)
7519 09:58:21.503518 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7520 09:58:21.503600
7521 09:58:21.506852 CA PerBit enable=1, Macro0, CA PI delay=36
7522 09:58:21.506934
7523 09:58:21.510548 [CBTSetCACLKResult] CA Dly = 36
7524 09:58:21.510630 CS Dly: 11 (0~43)
7525 09:58:21.517292 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7526 09:58:21.520141 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7527 09:58:21.520223
7528 09:58:21.523401 ----->DramcWriteLeveling(PI) begin...
7529 09:58:21.523487 ==
7530 09:58:21.527020 Dram Type= 6, Freq= 0, CH_0, rank 0
7531 09:58:21.531050 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7532 09:58:21.533526 ==
7533 09:58:21.533638 Write leveling (Byte 0): 36 => 36
7534 09:58:21.536781 Write leveling (Byte 1): 31 => 31
7535 09:58:21.540208 DramcWriteLeveling(PI) end<-----
7536 09:58:21.540293
7537 09:58:21.540358 ==
7538 09:58:21.543582 Dram Type= 6, Freq= 0, CH_0, rank 0
7539 09:58:21.550299 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7540 09:58:21.550421 ==
7541 09:58:21.550506 [Gating] SW mode calibration
7542 09:58:21.560103 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7543 09:58:21.563801 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7544 09:58:21.566979 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7545 09:58:21.573415 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7546 09:58:21.576857 1 4 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
7547 09:58:21.580141 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7548 09:58:21.587022 1 4 16 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7549 09:58:21.589953 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7550 09:58:21.593411 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7551 09:58:21.599960 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7552 09:58:21.603514 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7553 09:58:21.606945 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7554 09:58:21.613371 1 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
7555 09:58:21.617129 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7556 09:58:21.620136 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7557 09:58:21.626695 1 5 20 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
7558 09:58:21.630746 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7559 09:58:21.633413 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7560 09:58:21.640621 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7561 09:58:21.643288 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7562 09:58:21.646730 1 6 8 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
7563 09:58:21.653576 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7564 09:58:21.656800 1 6 16 | B1->B0 | 2f2f 4646 | 1 0 | (0 0) (0 0)
7565 09:58:21.660514 1 6 20 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
7566 09:58:21.663318 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7567 09:58:21.670050 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7568 09:58:21.673717 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7569 09:58:21.676729 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7570 09:58:21.683309 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7571 09:58:21.686828 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7572 09:58:21.691045 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7573 09:58:21.696527 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7574 09:58:21.699820 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 09:58:21.703367 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 09:58:21.709985 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 09:58:21.713554 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 09:58:21.716871 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 09:58:21.723364 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 09:58:21.726534 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 09:58:21.729548 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 09:58:21.736342 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 09:58:21.739749 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 09:58:21.743310 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 09:58:21.749855 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 09:58:21.753006 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7587 09:58:21.756544 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7588 09:58:21.762794 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7589 09:58:21.766116 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7590 09:58:21.769737 Total UI for P1: 0, mck2ui 16
7591 09:58:21.773332 best dqsien dly found for B0: ( 1, 9, 12)
7592 09:58:21.776252 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7593 09:58:21.779629 Total UI for P1: 0, mck2ui 16
7594 09:58:21.782834 best dqsien dly found for B1: ( 1, 9, 20)
7595 09:58:21.786166 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7596 09:58:21.789412 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7597 09:58:21.789494
7598 09:58:21.796134 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7599 09:58:21.799260 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7600 09:58:21.799343 [Gating] SW calibration Done
7601 09:58:21.802599 ==
7602 09:58:21.805834 Dram Type= 6, Freq= 0, CH_0, rank 0
7603 09:58:21.809251 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7604 09:58:21.809334 ==
7605 09:58:21.809400 RX Vref Scan: 0
7606 09:58:21.809462
7607 09:58:21.812778 RX Vref 0 -> 0, step: 1
7608 09:58:21.812861
7609 09:58:21.815831 RX Delay 0 -> 252, step: 8
7610 09:58:21.819108 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7611 09:58:21.822351 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7612 09:58:21.825741 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7613 09:58:21.832702 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7614 09:58:21.835581 iDelay=200, Bit 4, Center 143 (96 ~ 191) 96
7615 09:58:21.839134 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7616 09:58:21.842634 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7617 09:58:21.845790 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7618 09:58:21.852441 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7619 09:58:21.856398 iDelay=200, Bit 9, Center 111 (64 ~ 159) 96
7620 09:58:21.859450 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7621 09:58:21.862563 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7622 09:58:21.865713 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7623 09:58:21.872195 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7624 09:58:21.875691 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7625 09:58:21.879122 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7626 09:58:21.879244 ==
7627 09:58:21.882244 Dram Type= 6, Freq= 0, CH_0, rank 0
7628 09:58:21.885550 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7629 09:58:21.885658 ==
7630 09:58:21.889052 DQS Delay:
7631 09:58:21.889173 DQS0 = 0, DQS1 = 0
7632 09:58:21.892242 DQM Delay:
7633 09:58:21.892338 DQM0 = 138, DQM1 = 126
7634 09:58:21.892406 DQ Delay:
7635 09:58:21.895715 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7636 09:58:21.898765 DQ4 =143, DQ5 =123, DQ6 =147, DQ7 =147
7637 09:58:21.905542 DQ8 =119, DQ9 =111, DQ10 =123, DQ11 =123
7638 09:58:21.908711 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7639 09:58:21.908798
7640 09:58:21.908864
7641 09:58:21.908925 ==
7642 09:58:21.912419 Dram Type= 6, Freq= 0, CH_0, rank 0
7643 09:58:21.915460 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7644 09:58:21.915544 ==
7645 09:58:21.915610
7646 09:58:21.915670
7647 09:58:21.919227 TX Vref Scan disable
7648 09:58:21.922266 == TX Byte 0 ==
7649 09:58:21.925422 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7650 09:58:21.928809 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7651 09:58:21.932439 == TX Byte 1 ==
7652 09:58:21.935677 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7653 09:58:21.938742 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7654 09:58:21.938826 ==
7655 09:58:21.942059 Dram Type= 6, Freq= 0, CH_0, rank 0
7656 09:58:21.945474 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7657 09:58:21.945591 ==
7658 09:58:21.960362
7659 09:58:21.963131 TX Vref early break, caculate TX vref
7660 09:58:21.966471 TX Vref=16, minBit 7, minWin=22, winSum=377
7661 09:58:21.969695 TX Vref=18, minBit 2, minWin=23, winSum=386
7662 09:58:21.973590 TX Vref=20, minBit 6, minWin=23, winSum=396
7663 09:58:21.976546 TX Vref=22, minBit 2, minWin=24, winSum=411
7664 09:58:21.979787 TX Vref=24, minBit 6, minWin=25, winSum=420
7665 09:58:21.986706 TX Vref=26, minBit 12, minWin=25, winSum=426
7666 09:58:21.989801 TX Vref=28, minBit 0, minWin=25, winSum=425
7667 09:58:21.993029 TX Vref=30, minBit 0, minWin=25, winSum=414
7668 09:58:21.996251 TX Vref=32, minBit 0, minWin=25, winSum=412
7669 09:58:21.999743 TX Vref=34, minBit 8, minWin=24, winSum=401
7670 09:58:22.006606 [TxChooseVref] Worse bit 12, Min win 25, Win sum 426, Final Vref 26
7671 09:58:22.006719
7672 09:58:22.009659 Final TX Range 0 Vref 26
7673 09:58:22.009769
7674 09:58:22.009862 ==
7675 09:58:22.012881 Dram Type= 6, Freq= 0, CH_0, rank 0
7676 09:58:22.016208 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7677 09:58:22.016291 ==
7678 09:58:22.016357
7679 09:58:22.016418
7680 09:58:22.019463 TX Vref Scan disable
7681 09:58:22.026520 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7682 09:58:22.026603 == TX Byte 0 ==
7683 09:58:22.029471 u2DelayCellOfst[0]=13 cells (4 PI)
7684 09:58:22.032632 u2DelayCellOfst[1]=13 cells (4 PI)
7685 09:58:22.037151 u2DelayCellOfst[2]=10 cells (3 PI)
7686 09:58:22.039875 u2DelayCellOfst[3]=10 cells (3 PI)
7687 09:58:22.042727 u2DelayCellOfst[4]=6 cells (2 PI)
7688 09:58:22.046333 u2DelayCellOfst[5]=0 cells (0 PI)
7689 09:58:22.049359 u2DelayCellOfst[6]=17 cells (5 PI)
7690 09:58:22.052780 u2DelayCellOfst[7]=13 cells (4 PI)
7691 09:58:22.056137 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7692 09:58:22.059437 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7693 09:58:22.063175 == TX Byte 1 ==
7694 09:58:22.066107 u2DelayCellOfst[8]=0 cells (0 PI)
7695 09:58:22.066190 u2DelayCellOfst[9]=0 cells (0 PI)
7696 09:58:22.069544 u2DelayCellOfst[10]=6 cells (2 PI)
7697 09:58:22.073016 u2DelayCellOfst[11]=3 cells (1 PI)
7698 09:58:22.075889 u2DelayCellOfst[12]=13 cells (4 PI)
7699 09:58:22.079121 u2DelayCellOfst[13]=13 cells (4 PI)
7700 09:58:22.082860 u2DelayCellOfst[14]=13 cells (4 PI)
7701 09:58:22.086536 u2DelayCellOfst[15]=10 cells (3 PI)
7702 09:58:22.089909 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7703 09:58:22.096146 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7704 09:58:22.096230 DramC Write-DBI on
7705 09:58:22.096296 ==
7706 09:58:22.099470 Dram Type= 6, Freq= 0, CH_0, rank 0
7707 09:58:22.102723 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7708 09:58:22.105797 ==
7709 09:58:22.105880
7710 09:58:22.105945
7711 09:58:22.106005 TX Vref Scan disable
7712 09:58:22.109440 == TX Byte 0 ==
7713 09:58:22.113215 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7714 09:58:22.116312 == TX Byte 1 ==
7715 09:58:22.119833 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7716 09:58:22.122728 DramC Write-DBI off
7717 09:58:22.122893
7718 09:58:22.122973 [DATLAT]
7719 09:58:22.123033 Freq=1600, CH0 RK0
7720 09:58:22.123091
7721 09:58:22.126140 DATLAT Default: 0xf
7722 09:58:22.126221 0, 0xFFFF, sum = 0
7723 09:58:22.129526 1, 0xFFFF, sum = 0
7724 09:58:22.132445 2, 0xFFFF, sum = 0
7725 09:58:22.132584 3, 0xFFFF, sum = 0
7726 09:58:22.135969 4, 0xFFFF, sum = 0
7727 09:58:22.136077 5, 0xFFFF, sum = 0
7728 09:58:22.139336 6, 0xFFFF, sum = 0
7729 09:58:22.139420 7, 0xFFFF, sum = 0
7730 09:58:22.142612 8, 0xFFFF, sum = 0
7731 09:58:22.142722 9, 0xFFFF, sum = 0
7732 09:58:22.146366 10, 0xFFFF, sum = 0
7733 09:58:22.146509 11, 0xFFFF, sum = 0
7734 09:58:22.149381 12, 0xFFFF, sum = 0
7735 09:58:22.149464 13, 0xFFFF, sum = 0
7736 09:58:22.152671 14, 0x0, sum = 1
7737 09:58:22.152754 15, 0x0, sum = 2
7738 09:58:22.156146 16, 0x0, sum = 3
7739 09:58:22.156229 17, 0x0, sum = 4
7740 09:58:22.159334 best_step = 15
7741 09:58:22.159414
7742 09:58:22.159478 ==
7743 09:58:22.162369 Dram Type= 6, Freq= 0, CH_0, rank 0
7744 09:58:22.165949 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7745 09:58:22.166032 ==
7746 09:58:22.169578 RX Vref Scan: 1
7747 09:58:22.169658
7748 09:58:22.169722 Set Vref Range= 24 -> 127
7749 09:58:22.169783
7750 09:58:22.172720 RX Vref 24 -> 127, step: 1
7751 09:58:22.172800
7752 09:58:22.175805 RX Delay 19 -> 252, step: 4
7753 09:58:22.175886
7754 09:58:22.179012 Set Vref, RX VrefLevel [Byte0]: 24
7755 09:58:22.183078 [Byte1]: 24
7756 09:58:22.183159
7757 09:58:22.185916 Set Vref, RX VrefLevel [Byte0]: 25
7758 09:58:22.189604 [Byte1]: 25
7759 09:58:22.189685
7760 09:58:22.193144 Set Vref, RX VrefLevel [Byte0]: 26
7761 09:58:22.196130 [Byte1]: 26
7762 09:58:22.199750
7763 09:58:22.199830 Set Vref, RX VrefLevel [Byte0]: 27
7764 09:58:22.202998 [Byte1]: 27
7765 09:58:22.207260
7766 09:58:22.207340 Set Vref, RX VrefLevel [Byte0]: 28
7767 09:58:22.210917 [Byte1]: 28
7768 09:58:22.214841
7769 09:58:22.214922 Set Vref, RX VrefLevel [Byte0]: 29
7770 09:58:22.218292 [Byte1]: 29
7771 09:58:22.222333
7772 09:58:22.222422 Set Vref, RX VrefLevel [Byte0]: 30
7773 09:58:22.225932 [Byte1]: 30
7774 09:58:22.229984
7775 09:58:22.230084 Set Vref, RX VrefLevel [Byte0]: 31
7776 09:58:22.233486 [Byte1]: 31
7777 09:58:22.238156
7778 09:58:22.238238 Set Vref, RX VrefLevel [Byte0]: 32
7779 09:58:22.240855 [Byte1]: 32
7780 09:58:22.245233
7781 09:58:22.245323 Set Vref, RX VrefLevel [Byte0]: 33
7782 09:58:22.248498 [Byte1]: 33
7783 09:58:22.252893
7784 09:58:22.253038 Set Vref, RX VrefLevel [Byte0]: 34
7785 09:58:22.255861 [Byte1]: 34
7786 09:58:22.260443
7787 09:58:22.260540 Set Vref, RX VrefLevel [Byte0]: 35
7788 09:58:22.263695 [Byte1]: 35
7789 09:58:22.267831
7790 09:58:22.267912 Set Vref, RX VrefLevel [Byte0]: 36
7791 09:58:22.271435 [Byte1]: 36
7792 09:58:22.275842
7793 09:58:22.275928 Set Vref, RX VrefLevel [Byte0]: 37
7794 09:58:22.278753 [Byte1]: 37
7795 09:58:22.283249
7796 09:58:22.283333 Set Vref, RX VrefLevel [Byte0]: 38
7797 09:58:22.286452 [Byte1]: 38
7798 09:58:22.290611
7799 09:58:22.290692 Set Vref, RX VrefLevel [Byte0]: 39
7800 09:58:22.294008 [Byte1]: 39
7801 09:58:22.298201
7802 09:58:22.298283 Set Vref, RX VrefLevel [Byte0]: 40
7803 09:58:22.301853 [Byte1]: 40
7804 09:58:22.306202
7805 09:58:22.306314 Set Vref, RX VrefLevel [Byte0]: 41
7806 09:58:22.309130 [Byte1]: 41
7807 09:58:22.313325
7808 09:58:22.313407 Set Vref, RX VrefLevel [Byte0]: 42
7809 09:58:22.316838 [Byte1]: 42
7810 09:58:22.321370
7811 09:58:22.321452 Set Vref, RX VrefLevel [Byte0]: 43
7812 09:58:22.324311 [Byte1]: 43
7813 09:58:22.328480
7814 09:58:22.328563 Set Vref, RX VrefLevel [Byte0]: 44
7815 09:58:22.331622 [Byte1]: 44
7816 09:58:22.336403
7817 09:58:22.336489 Set Vref, RX VrefLevel [Byte0]: 45
7818 09:58:22.339393 [Byte1]: 45
7819 09:58:22.343694
7820 09:58:22.343779 Set Vref, RX VrefLevel [Byte0]: 46
7821 09:58:22.346828 [Byte1]: 46
7822 09:58:22.351199
7823 09:58:22.351300 Set Vref, RX VrefLevel [Byte0]: 47
7824 09:58:22.354302 [Byte1]: 47
7825 09:58:22.358713
7826 09:58:22.358796 Set Vref, RX VrefLevel [Byte0]: 48
7827 09:58:22.361819 [Byte1]: 48
7828 09:58:22.366240
7829 09:58:22.366323 Set Vref, RX VrefLevel [Byte0]: 49
7830 09:58:22.369649 [Byte1]: 49
7831 09:58:22.373964
7832 09:58:22.374047 Set Vref, RX VrefLevel [Byte0]: 50
7833 09:58:22.377120 [Byte1]: 50
7834 09:58:22.381636
7835 09:58:22.381721 Set Vref, RX VrefLevel [Byte0]: 51
7836 09:58:22.385141 [Byte1]: 51
7837 09:58:22.389032
7838 09:58:22.389115 Set Vref, RX VrefLevel [Byte0]: 52
7839 09:58:22.392571 [Byte1]: 52
7840 09:58:22.396426
7841 09:58:22.396510 Set Vref, RX VrefLevel [Byte0]: 53
7842 09:58:22.399722 [Byte1]: 53
7843 09:58:22.404006
7844 09:58:22.404089 Set Vref, RX VrefLevel [Byte0]: 54
7845 09:58:22.407671 [Byte1]: 54
7846 09:58:22.412269
7847 09:58:22.412352 Set Vref, RX VrefLevel [Byte0]: 55
7848 09:58:22.415113 [Byte1]: 55
7849 09:58:22.419271
7850 09:58:22.419354 Set Vref, RX VrefLevel [Byte0]: 56
7851 09:58:22.422921 [Byte1]: 56
7852 09:58:22.426735
7853 09:58:22.426817 Set Vref, RX VrefLevel [Byte0]: 57
7854 09:58:22.430607 [Byte1]: 57
7855 09:58:22.434729
7856 09:58:22.434815 Set Vref, RX VrefLevel [Byte0]: 58
7857 09:58:22.437920 [Byte1]: 58
7858 09:58:22.442116
7859 09:58:22.442199 Set Vref, RX VrefLevel [Byte0]: 59
7860 09:58:22.445500 [Byte1]: 59
7861 09:58:22.449747
7862 09:58:22.449832 Set Vref, RX VrefLevel [Byte0]: 60
7863 09:58:22.453011 [Byte1]: 60
7864 09:58:22.457450
7865 09:58:22.457534 Set Vref, RX VrefLevel [Byte0]: 61
7866 09:58:22.460481 [Byte1]: 61
7867 09:58:22.465161
7868 09:58:22.465244 Set Vref, RX VrefLevel [Byte0]: 62
7869 09:58:22.467947 [Byte1]: 62
7870 09:58:22.472571
7871 09:58:22.472654 Set Vref, RX VrefLevel [Byte0]: 63
7872 09:58:22.475791 [Byte1]: 63
7873 09:58:22.480090
7874 09:58:22.480174 Set Vref, RX VrefLevel [Byte0]: 64
7875 09:58:22.483149 [Byte1]: 64
7876 09:58:22.487617
7877 09:58:22.487701 Set Vref, RX VrefLevel [Byte0]: 65
7878 09:58:22.490729 [Byte1]: 65
7879 09:58:22.495215
7880 09:58:22.495299 Set Vref, RX VrefLevel [Byte0]: 66
7881 09:58:22.498745 [Byte1]: 66
7882 09:58:22.502929
7883 09:58:22.503012 Set Vref, RX VrefLevel [Byte0]: 67
7884 09:58:22.506375 [Byte1]: 67
7885 09:58:22.510120
7886 09:58:22.510202 Set Vref, RX VrefLevel [Byte0]: 68
7887 09:58:22.513983 [Byte1]: 68
7888 09:58:22.517821
7889 09:58:22.517903 Set Vref, RX VrefLevel [Byte0]: 69
7890 09:58:22.521308 [Byte1]: 69
7891 09:58:22.525586
7892 09:58:22.525669 Set Vref, RX VrefLevel [Byte0]: 70
7893 09:58:22.528808 [Byte1]: 70
7894 09:58:22.532954
7895 09:58:22.533038 Set Vref, RX VrefLevel [Byte0]: 71
7896 09:58:22.536463 [Byte1]: 71
7897 09:58:22.540727
7898 09:58:22.540810 Set Vref, RX VrefLevel [Byte0]: 72
7899 09:58:22.543854 [Byte1]: 72
7900 09:58:22.548332
7901 09:58:22.548420 Set Vref, RX VrefLevel [Byte0]: 73
7902 09:58:22.551515 [Byte1]: 73
7903 09:58:22.555768
7904 09:58:22.555872 Set Vref, RX VrefLevel [Byte0]: 74
7905 09:58:22.558830 [Byte1]: 74
7906 09:58:22.563434
7907 09:58:22.563549 Set Vref, RX VrefLevel [Byte0]: 75
7908 09:58:22.566721 [Byte1]: 75
7909 09:58:22.570739
7910 09:58:22.570825 Set Vref, RX VrefLevel [Byte0]: 76
7911 09:58:22.573987 [Byte1]: 76
7912 09:58:22.578862
7913 09:58:22.578948 Set Vref, RX VrefLevel [Byte0]: 77
7914 09:58:22.581790 [Byte1]: 77
7915 09:58:22.586066
7916 09:58:22.586150 Set Vref, RX VrefLevel [Byte0]: 78
7917 09:58:22.589277 [Byte1]: 78
7918 09:58:22.593976
7919 09:58:22.594063 Set Vref, RX VrefLevel [Byte0]: 79
7920 09:58:22.597306 [Byte1]: 79
7921 09:58:22.601152
7922 09:58:22.601235 Set Vref, RX VrefLevel [Byte0]: 80
7923 09:58:22.604367 [Byte1]: 80
7924 09:58:22.608831
7925 09:58:22.608914 Final RX Vref Byte 0 = 65 to rank0
7926 09:58:22.612235 Final RX Vref Byte 1 = 62 to rank0
7927 09:58:22.615797 Final RX Vref Byte 0 = 65 to rank1
7928 09:58:22.618820 Final RX Vref Byte 1 = 62 to rank1==
7929 09:58:22.621874 Dram Type= 6, Freq= 0, CH_0, rank 0
7930 09:58:22.628400 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7931 09:58:22.628487 ==
7932 09:58:22.628555 DQS Delay:
7933 09:58:22.631737 DQS0 = 0, DQS1 = 0
7934 09:58:22.631821 DQM Delay:
7935 09:58:22.631887 DQM0 = 136, DQM1 = 124
7936 09:58:22.635161 DQ Delay:
7937 09:58:22.638676 DQ0 =136, DQ1 =136, DQ2 =132, DQ3 =134
7938 09:58:22.641884 DQ4 =138, DQ5 =126, DQ6 =144, DQ7 =142
7939 09:58:22.644976 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =118
7940 09:58:22.648387 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =132
7941 09:58:22.648474
7942 09:58:22.648540
7943 09:58:22.648602
7944 09:58:22.651700 [DramC_TX_OE_Calibration] TA2
7945 09:58:22.655149 Original DQ_B0 (3 6) =30, OEN = 27
7946 09:58:22.658222 Original DQ_B1 (3 6) =30, OEN = 27
7947 09:58:22.661667 24, 0x0, End_B0=24 End_B1=24
7948 09:58:22.661753 25, 0x0, End_B0=25 End_B1=25
7949 09:58:22.665154 26, 0x0, End_B0=26 End_B1=26
7950 09:58:22.668068 27, 0x0, End_B0=27 End_B1=27
7951 09:58:22.671685 28, 0x0, End_B0=28 End_B1=28
7952 09:58:22.675108 29, 0x0, End_B0=29 End_B1=29
7953 09:58:22.675194 30, 0x0, End_B0=30 End_B1=30
7954 09:58:22.678289 31, 0x4141, End_B0=30 End_B1=30
7955 09:58:22.682132 Byte0 end_step=30 best_step=27
7956 09:58:22.684895 Byte1 end_step=30 best_step=27
7957 09:58:22.688485 Byte0 TX OE(2T, 0.5T) = (3, 3)
7958 09:58:22.691522 Byte1 TX OE(2T, 0.5T) = (3, 3)
7959 09:58:22.691606
7960 09:58:22.691671
7961 09:58:22.698511 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
7962 09:58:22.701356 CH0 RK0: MR19=303, MR18=1D1B
7963 09:58:22.708393 CH0_RK0: MR19=0x303, MR18=0x1D1B, DQSOSC=395, MR23=63, INC=23, DEC=15
7964 09:58:22.708479
7965 09:58:22.711491 ----->DramcWriteLeveling(PI) begin...
7966 09:58:22.711575 ==
7967 09:58:22.714866 Dram Type= 6, Freq= 0, CH_0, rank 1
7968 09:58:22.718328 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7969 09:58:22.718420 ==
7970 09:58:22.721606 Write leveling (Byte 0): 38 => 38
7971 09:58:22.724955 Write leveling (Byte 1): 27 => 27
7972 09:58:22.728101 DramcWriteLeveling(PI) end<-----
7973 09:58:22.728184
7974 09:58:22.728249 ==
7975 09:58:22.731674 Dram Type= 6, Freq= 0, CH_0, rank 1
7976 09:58:22.734765 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7977 09:58:22.734853 ==
7978 09:58:22.738105 [Gating] SW mode calibration
7979 09:58:22.744660 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7980 09:58:22.751453 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7981 09:58:22.755354 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7982 09:58:22.757892 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7983 09:58:22.764689 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7984 09:58:22.768192 1 4 12 | B1->B0 | 2727 3333 | 1 1 | (1 1) (0 0)
7985 09:58:22.771221 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7986 09:58:22.777937 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7987 09:58:22.781738 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7988 09:58:22.784679 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7989 09:58:22.791815 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7990 09:58:22.795040 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7991 09:58:22.798071 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7992 09:58:22.804532 1 5 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 1)
7993 09:58:22.808186 1 5 16 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
7994 09:58:22.811067 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7995 09:58:22.817699 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7996 09:58:22.821505 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7997 09:58:22.824525 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7998 09:58:22.831386 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7999 09:58:22.834290 1 6 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8000 09:58:22.837901 1 6 12 | B1->B0 | 2828 4141 | 0 0 | (0 0) (0 0)
8001 09:58:22.844263 1 6 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8002 09:58:22.847813 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8003 09:58:22.850890 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8004 09:58:22.857637 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8005 09:58:22.861002 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8006 09:58:22.864486 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8007 09:58:22.870717 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8008 09:58:22.874083 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8009 09:58:22.877191 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8010 09:58:22.883804 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 09:58:22.887406 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 09:58:22.890608 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 09:58:22.897311 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 09:58:22.900539 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 09:58:22.904002 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 09:58:22.910155 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 09:58:22.913469 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 09:58:22.917112 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 09:58:22.923479 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 09:58:22.926735 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 09:58:22.930101 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 09:58:22.936786 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 09:58:22.940672 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8024 09:58:22.943249 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8025 09:58:22.949989 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8026 09:58:22.950085 Total UI for P1: 0, mck2ui 16
8027 09:58:22.953263 best dqsien dly found for B0: ( 1, 9, 10)
8028 09:58:22.960078 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8029 09:58:22.963261 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8030 09:58:22.966829 Total UI for P1: 0, mck2ui 16
8031 09:58:22.969988 best dqsien dly found for B1: ( 1, 9, 16)
8032 09:58:22.973454 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8033 09:58:22.976457 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8034 09:58:22.976544
8035 09:58:22.979708 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8036 09:58:22.986582 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8037 09:58:22.986673 [Gating] SW calibration Done
8038 09:58:22.989876 ==
8039 09:58:22.989962 Dram Type= 6, Freq= 0, CH_0, rank 1
8040 09:58:22.996396 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8041 09:58:22.996485 ==
8042 09:58:22.996572 RX Vref Scan: 0
8043 09:58:22.996655
8044 09:58:22.999857 RX Vref 0 -> 0, step: 1
8045 09:58:22.999944
8046 09:58:23.003362 RX Delay 0 -> 252, step: 8
8047 09:58:23.006100 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8048 09:58:23.009512 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8049 09:58:23.012913 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8050 09:58:23.019540 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8051 09:58:23.022848 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8052 09:58:23.026172 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
8053 09:58:23.029456 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8054 09:58:23.032750 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
8055 09:58:23.039512 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8056 09:58:23.042758 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8057 09:58:23.045968 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8058 09:58:23.049482 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8059 09:58:23.053150 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8060 09:58:23.059333 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8061 09:58:23.062769 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8062 09:58:23.065697 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8063 09:58:23.065785 ==
8064 09:58:23.069576 Dram Type= 6, Freq= 0, CH_0, rank 1
8065 09:58:23.072490 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8066 09:58:23.072577 ==
8067 09:58:23.075621 DQS Delay:
8068 09:58:23.075707 DQS0 = 0, DQS1 = 0
8069 09:58:23.079358 DQM Delay:
8070 09:58:23.079443 DQM0 = 136, DQM1 = 127
8071 09:58:23.082910 DQ Delay:
8072 09:58:23.085828 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8073 09:58:23.089394 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =147
8074 09:58:23.092619 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =123
8075 09:58:23.096069 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8076 09:58:23.096156
8077 09:58:23.096243
8078 09:58:23.096325 ==
8079 09:58:23.099211 Dram Type= 6, Freq= 0, CH_0, rank 1
8080 09:58:23.102649 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8081 09:58:23.102736 ==
8082 09:58:23.102823
8083 09:58:23.102905
8084 09:58:23.105913 TX Vref Scan disable
8085 09:58:23.109183 == TX Byte 0 ==
8086 09:58:23.112331 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8087 09:58:23.116035 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8088 09:58:23.118952 == TX Byte 1 ==
8089 09:58:23.122329 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8090 09:58:23.125907 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8091 09:58:23.125993 ==
8092 09:58:23.129157 Dram Type= 6, Freq= 0, CH_0, rank 1
8093 09:58:23.135783 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8094 09:58:23.135869 ==
8095 09:58:23.148279
8096 09:58:23.151755 TX Vref early break, caculate TX vref
8097 09:58:23.154881 TX Vref=16, minBit 8, minWin=22, winSum=386
8098 09:58:23.158573 TX Vref=18, minBit 8, minWin=24, winSum=402
8099 09:58:23.161487 TX Vref=20, minBit 8, minWin=24, winSum=407
8100 09:58:23.165010 TX Vref=22, minBit 2, minWin=25, winSum=418
8101 09:58:23.168659 TX Vref=24, minBit 0, minWin=26, winSum=425
8102 09:58:23.174892 TX Vref=26, minBit 8, minWin=25, winSum=426
8103 09:58:23.178105 TX Vref=28, minBit 0, minWin=26, winSum=428
8104 09:58:23.181574 TX Vref=30, minBit 8, minWin=25, winSum=421
8105 09:58:23.184900 TX Vref=32, minBit 0, minWin=25, winSum=410
8106 09:58:23.187922 TX Vref=34, minBit 2, minWin=24, winSum=400
8107 09:58:23.194460 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 28
8108 09:58:23.194546
8109 09:58:23.197877 Final TX Range 0 Vref 28
8110 09:58:23.197961
8111 09:58:23.198027 ==
8112 09:58:23.201170 Dram Type= 6, Freq= 0, CH_0, rank 1
8113 09:58:23.204621 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8114 09:58:23.204706 ==
8115 09:58:23.204772
8116 09:58:23.204833
8117 09:58:23.208045 TX Vref Scan disable
8118 09:58:23.214322 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8119 09:58:23.214413 == TX Byte 0 ==
8120 09:58:23.217852 u2DelayCellOfst[0]=10 cells (3 PI)
8121 09:58:23.220986 u2DelayCellOfst[1]=17 cells (5 PI)
8122 09:58:23.224710 u2DelayCellOfst[2]=10 cells (3 PI)
8123 09:58:23.227970 u2DelayCellOfst[3]=10 cells (3 PI)
8124 09:58:23.231473 u2DelayCellOfst[4]=6 cells (2 PI)
8125 09:58:23.234520 u2DelayCellOfst[5]=0 cells (0 PI)
8126 09:58:23.237901 u2DelayCellOfst[6]=17 cells (5 PI)
8127 09:58:23.241360 u2DelayCellOfst[7]=13 cells (4 PI)
8128 09:58:23.244585 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8129 09:58:23.247777 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8130 09:58:23.251224 == TX Byte 1 ==
8131 09:58:23.251310 u2DelayCellOfst[8]=0 cells (0 PI)
8132 09:58:23.254637 u2DelayCellOfst[9]=0 cells (0 PI)
8133 09:58:23.258164 u2DelayCellOfst[10]=3 cells (1 PI)
8134 09:58:23.261073 u2DelayCellOfst[11]=0 cells (0 PI)
8135 09:58:23.264726 u2DelayCellOfst[12]=10 cells (3 PI)
8136 09:58:23.267947 u2DelayCellOfst[13]=6 cells (2 PI)
8137 09:58:23.271332 u2DelayCellOfst[14]=10 cells (3 PI)
8138 09:58:23.274920 u2DelayCellOfst[15]=6 cells (2 PI)
8139 09:58:23.277786 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8140 09:58:23.284401 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8141 09:58:23.284486 DramC Write-DBI on
8142 09:58:23.284553 ==
8143 09:58:23.288128 Dram Type= 6, Freq= 0, CH_0, rank 1
8144 09:58:23.291720 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8145 09:58:23.294377 ==
8146 09:58:23.294468
8147 09:58:23.294533
8148 09:58:23.294593 TX Vref Scan disable
8149 09:58:23.297894 == TX Byte 0 ==
8150 09:58:23.301033 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8151 09:58:23.304644 == TX Byte 1 ==
8152 09:58:23.307782 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8153 09:58:23.310998 DramC Write-DBI off
8154 09:58:23.311080
8155 09:58:23.311146 [DATLAT]
8156 09:58:23.311206 Freq=1600, CH0 RK1
8157 09:58:23.311266
8158 09:58:23.314586 DATLAT Default: 0xf
8159 09:58:23.314668 0, 0xFFFF, sum = 0
8160 09:58:23.317953 1, 0xFFFF, sum = 0
8161 09:58:23.320885 2, 0xFFFF, sum = 0
8162 09:58:23.320968 3, 0xFFFF, sum = 0
8163 09:58:23.324384 4, 0xFFFF, sum = 0
8164 09:58:23.324467 5, 0xFFFF, sum = 0
8165 09:58:23.328029 6, 0xFFFF, sum = 0
8166 09:58:23.328112 7, 0xFFFF, sum = 0
8167 09:58:23.331213 8, 0xFFFF, sum = 0
8168 09:58:23.331297 9, 0xFFFF, sum = 0
8169 09:58:23.334584 10, 0xFFFF, sum = 0
8170 09:58:23.334667 11, 0xFFFF, sum = 0
8171 09:58:23.337688 12, 0xFFFF, sum = 0
8172 09:58:23.337771 13, 0xFFFF, sum = 0
8173 09:58:23.341073 14, 0x0, sum = 1
8174 09:58:23.341155 15, 0x0, sum = 2
8175 09:58:23.344112 16, 0x0, sum = 3
8176 09:58:23.344194 17, 0x0, sum = 4
8177 09:58:23.347927 best_step = 15
8178 09:58:23.348009
8179 09:58:23.348075 ==
8180 09:58:23.350863 Dram Type= 6, Freq= 0, CH_0, rank 1
8181 09:58:23.354323 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8182 09:58:23.354461 ==
8183 09:58:23.357737 RX Vref Scan: 0
8184 09:58:23.357819
8185 09:58:23.357884 RX Vref 0 -> 0, step: 1
8186 09:58:23.357943
8187 09:58:23.360657 RX Delay 11 -> 252, step: 4
8188 09:58:23.364995 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8189 09:58:23.370809 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8190 09:58:23.374595 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8191 09:58:23.377708 iDelay=191, Bit 3, Center 128 (79 ~ 178) 100
8192 09:58:23.380970 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8193 09:58:23.384140 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8194 09:58:23.390895 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8195 09:58:23.394179 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8196 09:58:23.397400 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8197 09:58:23.400753 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8198 09:58:23.404375 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8199 09:58:23.410552 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8200 09:58:23.414198 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8201 09:58:23.417831 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8202 09:58:23.420702 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8203 09:58:23.427291 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8204 09:58:23.427376 ==
8205 09:58:23.430576 Dram Type= 6, Freq= 0, CH_0, rank 1
8206 09:58:23.434211 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8207 09:58:23.434295 ==
8208 09:58:23.434361 DQS Delay:
8209 09:58:23.437368 DQS0 = 0, DQS1 = 0
8210 09:58:23.437450 DQM Delay:
8211 09:58:23.440525 DQM0 = 133, DQM1 = 123
8212 09:58:23.440607 DQ Delay:
8213 09:58:23.443937 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =128
8214 09:58:23.447575 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
8215 09:58:23.450423 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8216 09:58:23.454095 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8217 09:58:23.454206
8218 09:58:23.454300
8219 09:58:23.454395
8220 09:58:23.457126 [DramC_TX_OE_Calibration] TA2
8221 09:58:23.460984 Original DQ_B0 (3 6) =30, OEN = 27
8222 09:58:23.463931 Original DQ_B1 (3 6) =30, OEN = 27
8223 09:58:23.467061 24, 0x0, End_B0=24 End_B1=24
8224 09:58:23.470374 25, 0x0, End_B0=25 End_B1=25
8225 09:58:23.470499 26, 0x0, End_B0=26 End_B1=26
8226 09:58:23.473629 27, 0x0, End_B0=27 End_B1=27
8227 09:58:23.477179 28, 0x0, End_B0=28 End_B1=28
8228 09:58:23.480752 29, 0x0, End_B0=29 End_B1=29
8229 09:58:23.483753 30, 0x0, End_B0=30 End_B1=30
8230 09:58:23.483838 31, 0x5151, End_B0=30 End_B1=30
8231 09:58:23.487293 Byte0 end_step=30 best_step=27
8232 09:58:23.490485 Byte1 end_step=30 best_step=27
8233 09:58:23.493852 Byte0 TX OE(2T, 0.5T) = (3, 3)
8234 09:58:23.497045 Byte1 TX OE(2T, 0.5T) = (3, 3)
8235 09:58:23.497129
8236 09:58:23.497194
8237 09:58:23.504136 [DQSOSCAuto] RK1, (LSB)MR18= 0x200e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8238 09:58:23.507308 CH0 RK1: MR19=303, MR18=200E
8239 09:58:23.513879 CH0_RK1: MR19=0x303, MR18=0x200E, DQSOSC=393, MR23=63, INC=23, DEC=15
8240 09:58:23.517147 [RxdqsGatingPostProcess] freq 1600
8241 09:58:23.523398 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8242 09:58:23.523510 best DQS0 dly(2T, 0.5T) = (1, 1)
8243 09:58:23.526924 best DQS1 dly(2T, 0.5T) = (1, 1)
8244 09:58:23.530096 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8245 09:58:23.533837 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8246 09:58:23.536660 best DQS0 dly(2T, 0.5T) = (1, 1)
8247 09:58:23.540584 best DQS1 dly(2T, 0.5T) = (1, 1)
8248 09:58:23.543413 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8249 09:58:23.546701 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8250 09:58:23.550312 Pre-setting of DQS Precalculation
8251 09:58:23.553804 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8252 09:58:23.553890 ==
8253 09:58:23.557240 Dram Type= 6, Freq= 0, CH_1, rank 0
8254 09:58:23.563393 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8255 09:58:23.563479 ==
8256 09:58:23.566572 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8257 09:58:23.573269 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8258 09:58:23.577033 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8259 09:58:23.583629 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8260 09:58:23.591003 [CA 0] Center 41 (12~71) winsize 60
8261 09:58:23.594070 [CA 1] Center 41 (12~71) winsize 60
8262 09:58:23.597576 [CA 2] Center 37 (8~67) winsize 60
8263 09:58:23.600959 [CA 3] Center 36 (7~66) winsize 60
8264 09:58:23.604314 [CA 4] Center 37 (7~67) winsize 61
8265 09:58:23.607526 [CA 5] Center 36 (7~66) winsize 60
8266 09:58:23.607611
8267 09:58:23.610841 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8268 09:58:23.610926
8269 09:58:23.614142 [CATrainingPosCal] consider 1 rank data
8270 09:58:23.617396 u2DelayCellTimex100 = 285/100 ps
8271 09:58:23.620863 CA0 delay=41 (12~71),Diff = 5 PI (17 cell)
8272 09:58:23.627466 CA1 delay=41 (12~71),Diff = 5 PI (17 cell)
8273 09:58:23.630652 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8274 09:58:23.634064 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8275 09:58:23.637054 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8276 09:58:23.640848 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8277 09:58:23.640932
8278 09:58:23.643929 CA PerBit enable=1, Macro0, CA PI delay=36
8279 09:58:23.644012
8280 09:58:23.647841 [CBTSetCACLKResult] CA Dly = 36
8281 09:58:23.650829 CS Dly: 9 (0~40)
8282 09:58:23.653937 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8283 09:58:23.657371 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8284 09:58:23.657455 ==
8285 09:58:23.660821 Dram Type= 6, Freq= 0, CH_1, rank 1
8286 09:58:23.663848 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8287 09:58:23.667507 ==
8288 09:58:23.670367 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8289 09:58:23.674028 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8290 09:58:23.680298 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8291 09:58:23.683509 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8292 09:58:23.695038 [CA 0] Center 41 (12~71) winsize 60
8293 09:58:23.697448 [CA 1] Center 41 (12~71) winsize 60
8294 09:58:23.700774 [CA 2] Center 37 (8~67) winsize 60
8295 09:58:23.704528 [CA 3] Center 37 (8~67) winsize 60
8296 09:58:23.707192 [CA 4] Center 37 (8~67) winsize 60
8297 09:58:23.711132 [CA 5] Center 37 (7~67) winsize 61
8298 09:58:23.711213
8299 09:58:23.714176 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8300 09:58:23.714257
8301 09:58:23.717516 [CATrainingPosCal] consider 2 rank data
8302 09:58:23.720899 u2DelayCellTimex100 = 285/100 ps
8303 09:58:23.724038 CA0 delay=41 (12~71),Diff = 5 PI (17 cell)
8304 09:58:23.731235 CA1 delay=41 (12~71),Diff = 5 PI (17 cell)
8305 09:58:23.733725 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8306 09:58:23.737187 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8307 09:58:23.740879 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8308 09:58:23.743978 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8309 09:58:23.744064
8310 09:58:23.747185 CA PerBit enable=1, Macro0, CA PI delay=36
8311 09:58:23.747272
8312 09:58:23.750585 [CBTSetCACLKResult] CA Dly = 36
8313 09:58:23.753687 CS Dly: 10 (0~42)
8314 09:58:23.757323 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8315 09:58:23.760391 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8316 09:58:23.760473
8317 09:58:23.763754 ----->DramcWriteLeveling(PI) begin...
8318 09:58:23.763838 ==
8319 09:58:23.767334 Dram Type= 6, Freq= 0, CH_1, rank 0
8320 09:58:23.770335 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8321 09:58:23.773941 ==
8322 09:58:23.774025 Write leveling (Byte 0): 24 => 24
8323 09:58:23.777483 Write leveling (Byte 1): 29 => 29
8324 09:58:23.780906 DramcWriteLeveling(PI) end<-----
8325 09:58:23.780988
8326 09:58:23.781053 ==
8327 09:58:23.783865 Dram Type= 6, Freq= 0, CH_1, rank 0
8328 09:58:23.790534 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8329 09:58:23.790620 ==
8330 09:58:23.790685 [Gating] SW mode calibration
8331 09:58:23.800324 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8332 09:58:23.803779 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8333 09:58:23.810579 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 09:58:23.813939 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8335 09:58:23.817104 1 4 8 | B1->B0 | 2a29 3131 | 1 1 | (1 1) (1 1)
8336 09:58:23.820272 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8337 09:58:23.827072 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8338 09:58:23.830378 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8339 09:58:23.833465 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8340 09:58:23.840131 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8341 09:58:23.843914 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8342 09:58:23.846630 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8343 09:58:23.853720 1 5 8 | B1->B0 | 2626 2424 | 0 0 | (0 0) (1 0)
8344 09:58:23.856990 1 5 12 | B1->B0 | 2424 2424 | 0 0 | (1 0) (0 0)
8345 09:58:23.860099 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 09:58:23.866769 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8347 09:58:23.869858 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8348 09:58:23.873222 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8349 09:58:23.880237 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8350 09:58:23.883945 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8351 09:58:23.886545 1 6 8 | B1->B0 | 3838 4242 | 0 0 | (0 0) (0 0)
8352 09:58:23.893187 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8353 09:58:23.896940 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8354 09:58:23.899894 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8355 09:58:23.906374 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8356 09:58:23.909938 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8357 09:58:23.913577 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8358 09:58:23.920112 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8359 09:58:23.923570 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8360 09:58:23.927038 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8361 09:58:23.933150 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 09:58:23.936439 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 09:58:23.940249 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 09:58:23.946699 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 09:58:23.950029 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 09:58:23.953355 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 09:58:23.956610 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 09:58:23.963323 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 09:58:23.966691 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 09:58:23.969775 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 09:58:23.976357 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 09:58:23.980074 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 09:58:23.983110 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 09:58:23.989942 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 09:58:23.992919 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8376 09:58:23.996548 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8377 09:58:24.000055 Total UI for P1: 0, mck2ui 16
8378 09:58:24.003347 best dqsien dly found for B0: ( 1, 9, 8)
8379 09:58:24.009656 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 09:58:24.009740 Total UI for P1: 0, mck2ui 16
8381 09:58:24.016477 best dqsien dly found for B1: ( 1, 9, 10)
8382 09:58:24.019852 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8383 09:58:24.023215 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8384 09:58:24.023310
8385 09:58:24.026323 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8386 09:58:24.029538 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8387 09:58:24.032802 [Gating] SW calibration Done
8388 09:58:24.032884 ==
8389 09:58:24.036038 Dram Type= 6, Freq= 0, CH_1, rank 0
8390 09:58:24.039747 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8391 09:58:24.039829 ==
8392 09:58:24.042925 RX Vref Scan: 0
8393 09:58:24.043006
8394 09:58:24.043070 RX Vref 0 -> 0, step: 1
8395 09:58:24.043133
8396 09:58:24.046197 RX Delay 0 -> 252, step: 8
8397 09:58:24.049478 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8398 09:58:24.052888 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8399 09:58:24.059906 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8400 09:58:24.063074 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8401 09:58:24.066968 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8402 09:58:24.069940 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8403 09:58:24.072934 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8404 09:58:24.079429 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8405 09:58:24.083021 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8406 09:58:24.086167 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8407 09:58:24.089543 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8408 09:58:24.092924 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8409 09:58:24.099508 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8410 09:58:24.103036 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8411 09:58:24.106126 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8412 09:58:24.109571 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8413 09:58:24.109666 ==
8414 09:58:24.112763 Dram Type= 6, Freq= 0, CH_1, rank 0
8415 09:58:24.119331 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8416 09:58:24.119413 ==
8417 09:58:24.119478 DQS Delay:
8418 09:58:24.123159 DQS0 = 0, DQS1 = 0
8419 09:58:24.123242 DQM Delay:
8420 09:58:24.123307 DQM0 = 136, DQM1 = 131
8421 09:58:24.125859 DQ Delay:
8422 09:58:24.129238 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =135
8423 09:58:24.132758 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8424 09:58:24.136262 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8425 09:58:24.139204 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8426 09:58:24.139287
8427 09:58:24.139354
8428 09:58:24.139414 ==
8429 09:58:24.142752 Dram Type= 6, Freq= 0, CH_1, rank 0
8430 09:58:24.146233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8431 09:58:24.149160 ==
8432 09:58:24.149244
8433 09:58:24.149310
8434 09:58:24.149372 TX Vref Scan disable
8435 09:58:24.152672 == TX Byte 0 ==
8436 09:58:24.156131 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8437 09:58:24.159380 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8438 09:58:24.162905 == TX Byte 1 ==
8439 09:58:24.165800 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8440 09:58:24.169046 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8441 09:58:24.172563 ==
8442 09:58:24.175645 Dram Type= 6, Freq= 0, CH_1, rank 0
8443 09:58:24.178967 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8444 09:58:24.179051 ==
8445 09:58:24.191482
8446 09:58:24.194526 TX Vref early break, caculate TX vref
8447 09:58:24.198504 TX Vref=16, minBit 10, minWin=21, winSum=366
8448 09:58:24.201019 TX Vref=18, minBit 10, minWin=22, winSum=376
8449 09:58:24.204833 TX Vref=20, minBit 9, minWin=23, winSum=389
8450 09:58:24.207808 TX Vref=22, minBit 10, minWin=23, winSum=396
8451 09:58:24.214223 TX Vref=24, minBit 10, minWin=23, winSum=404
8452 09:58:24.217942 TX Vref=26, minBit 9, minWin=25, winSum=415
8453 09:58:24.220996 TX Vref=28, minBit 12, minWin=24, winSum=413
8454 09:58:24.224430 TX Vref=30, minBit 8, minWin=24, winSum=403
8455 09:58:24.227581 TX Vref=32, minBit 8, minWin=23, winSum=394
8456 09:58:24.230724 TX Vref=34, minBit 12, minWin=22, winSum=385
8457 09:58:24.237500 [TxChooseVref] Worse bit 9, Min win 25, Win sum 415, Final Vref 26
8458 09:58:24.237584
8459 09:58:24.240858 Final TX Range 0 Vref 26
8460 09:58:24.240943
8461 09:58:24.241029 ==
8462 09:58:24.244170 Dram Type= 6, Freq= 0, CH_1, rank 0
8463 09:58:24.247585 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8464 09:58:24.247672 ==
8465 09:58:24.247758
8466 09:58:24.250794
8467 09:58:24.250880 TX Vref Scan disable
8468 09:58:24.257878 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8469 09:58:24.257964 == TX Byte 0 ==
8470 09:58:24.260940 u2DelayCellOfst[0]=13 cells (4 PI)
8471 09:58:24.264164 u2DelayCellOfst[1]=10 cells (3 PI)
8472 09:58:24.267229 u2DelayCellOfst[2]=0 cells (0 PI)
8473 09:58:24.270565 u2DelayCellOfst[3]=3 cells (1 PI)
8474 09:58:24.274162 u2DelayCellOfst[4]=6 cells (2 PI)
8475 09:58:24.277403 u2DelayCellOfst[5]=17 cells (5 PI)
8476 09:58:24.280380 u2DelayCellOfst[6]=17 cells (5 PI)
8477 09:58:24.283872 u2DelayCellOfst[7]=6 cells (2 PI)
8478 09:58:24.287112 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8479 09:58:24.290470 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8480 09:58:24.293752 == TX Byte 1 ==
8481 09:58:24.297747 u2DelayCellOfst[8]=0 cells (0 PI)
8482 09:58:24.300320 u2DelayCellOfst[9]=6 cells (2 PI)
8483 09:58:24.303800 u2DelayCellOfst[10]=10 cells (3 PI)
8484 09:58:24.303883 u2DelayCellOfst[11]=6 cells (2 PI)
8485 09:58:24.306953 u2DelayCellOfst[12]=17 cells (5 PI)
8486 09:58:24.310332 u2DelayCellOfst[13]=20 cells (6 PI)
8487 09:58:24.313601 u2DelayCellOfst[14]=20 cells (6 PI)
8488 09:58:24.316853 u2DelayCellOfst[15]=17 cells (5 PI)
8489 09:58:24.323803 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8490 09:58:24.326988 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8491 09:58:24.327079 DramC Write-DBI on
8492 09:58:24.327146 ==
8493 09:58:24.330306 Dram Type= 6, Freq= 0, CH_1, rank 0
8494 09:58:24.337378 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8495 09:58:24.337759 ==
8496 09:58:24.338004
8497 09:58:24.338183
8498 09:58:24.340373 TX Vref Scan disable
8499 09:58:24.340615 == TX Byte 0 ==
8500 09:58:24.346982 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8501 09:58:24.347225 == TX Byte 1 ==
8502 09:58:24.349944 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8503 09:58:24.353633 DramC Write-DBI off
8504 09:58:24.353969
8505 09:58:24.354178 [DATLAT]
8506 09:58:24.356813 Freq=1600, CH1 RK0
8507 09:58:24.357058
8508 09:58:24.357252 DATLAT Default: 0xf
8509 09:58:24.360588 0, 0xFFFF, sum = 0
8510 09:58:24.360928 1, 0xFFFF, sum = 0
8511 09:58:24.363544 2, 0xFFFF, sum = 0
8512 09:58:24.363881 3, 0xFFFF, sum = 0
8513 09:58:24.366866 4, 0xFFFF, sum = 0
8514 09:58:24.367117 5, 0xFFFF, sum = 0
8515 09:58:24.370191 6, 0xFFFF, sum = 0
8516 09:58:24.370671 7, 0xFFFF, sum = 0
8517 09:58:24.373689 8, 0xFFFF, sum = 0
8518 09:58:24.374192 9, 0xFFFF, sum = 0
8519 09:58:24.377023 10, 0xFFFF, sum = 0
8520 09:58:24.380457 11, 0xFFFF, sum = 0
8521 09:58:24.380957 12, 0xFFFF, sum = 0
8522 09:58:24.383890 13, 0xFFFF, sum = 0
8523 09:58:24.384441 14, 0x0, sum = 1
8524 09:58:24.386900 15, 0x0, sum = 2
8525 09:58:24.387347 16, 0x0, sum = 3
8526 09:58:24.390517 17, 0x0, sum = 4
8527 09:58:24.391066 best_step = 15
8528 09:58:24.391417
8529 09:58:24.391734 ==
8530 09:58:24.393827 Dram Type= 6, Freq= 0, CH_1, rank 0
8531 09:58:24.396751 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8532 09:58:24.397191 ==
8533 09:58:24.400029 RX Vref Scan: 1
8534 09:58:24.400421
8535 09:58:24.403930 Set Vref Range= 24 -> 127
8536 09:58:24.404454
8537 09:58:24.404799 RX Vref 24 -> 127, step: 1
8538 09:58:24.405116
8539 09:58:24.406869 RX Delay 19 -> 252, step: 4
8540 09:58:24.407293
8541 09:58:24.409843 Set Vref, RX VrefLevel [Byte0]: 24
8542 09:58:24.413020 [Byte1]: 24
8543 09:58:24.416691
8544 09:58:24.417191 Set Vref, RX VrefLevel [Byte0]: 25
8545 09:58:24.420088 [Byte1]: 25
8546 09:58:24.424116
8547 09:58:24.424636 Set Vref, RX VrefLevel [Byte0]: 26
8548 09:58:24.427510 [Byte1]: 26
8549 09:58:24.431692
8550 09:58:24.432119 Set Vref, RX VrefLevel [Byte0]: 27
8551 09:58:24.434950 [Byte1]: 27
8552 09:58:24.439672
8553 09:58:24.440144 Set Vref, RX VrefLevel [Byte0]: 28
8554 09:58:24.442598 [Byte1]: 28
8555 09:58:24.446758
8556 09:58:24.447281 Set Vref, RX VrefLevel [Byte0]: 29
8557 09:58:24.450365 [Byte1]: 29
8558 09:58:24.454339
8559 09:58:24.454735 Set Vref, RX VrefLevel [Byte0]: 30
8560 09:58:24.457735 [Byte1]: 30
8561 09:58:24.462104
8562 09:58:24.462367 Set Vref, RX VrefLevel [Byte0]: 31
8563 09:58:24.465004 [Byte1]: 31
8564 09:58:24.469053
8565 09:58:24.469212 Set Vref, RX VrefLevel [Byte0]: 32
8566 09:58:24.472545 [Byte1]: 32
8567 09:58:24.477006
8568 09:58:24.477155 Set Vref, RX VrefLevel [Byte0]: 33
8569 09:58:24.479974 [Byte1]: 33
8570 09:58:24.484124
8571 09:58:24.484246 Set Vref, RX VrefLevel [Byte0]: 34
8572 09:58:24.487889 [Byte1]: 34
8573 09:58:24.491821
8574 09:58:24.491917 Set Vref, RX VrefLevel [Byte0]: 35
8575 09:58:24.495438 [Byte1]: 35
8576 09:58:24.499286
8577 09:58:24.499394 Set Vref, RX VrefLevel [Byte0]: 36
8578 09:58:24.502703 [Byte1]: 36
8579 09:58:24.506973
8580 09:58:24.507094 Set Vref, RX VrefLevel [Byte0]: 37
8581 09:58:24.510249 [Byte1]: 37
8582 09:58:24.514704
8583 09:58:24.514787 Set Vref, RX VrefLevel [Byte0]: 38
8584 09:58:24.517913 [Byte1]: 38
8585 09:58:24.522622
8586 09:58:24.522747 Set Vref, RX VrefLevel [Byte0]: 39
8587 09:58:24.525835 [Byte1]: 39
8588 09:58:24.530070
8589 09:58:24.530229 Set Vref, RX VrefLevel [Byte0]: 40
8590 09:58:24.532948 [Byte1]: 40
8591 09:58:24.537659
8592 09:58:24.537810 Set Vref, RX VrefLevel [Byte0]: 41
8593 09:58:24.540741 [Byte1]: 41
8594 09:58:24.544759
8595 09:58:24.544873 Set Vref, RX VrefLevel [Byte0]: 42
8596 09:58:24.548310 [Byte1]: 42
8597 09:58:24.552873
8598 09:58:24.553061 Set Vref, RX VrefLevel [Byte0]: 43
8599 09:58:24.555922 [Byte1]: 43
8600 09:58:24.560025
8601 09:58:24.560213 Set Vref, RX VrefLevel [Byte0]: 44
8602 09:58:24.563396 [Byte1]: 44
8603 09:58:24.567988
8604 09:58:24.568206 Set Vref, RX VrefLevel [Byte0]: 45
8605 09:58:24.571140 [Byte1]: 45
8606 09:58:24.575113
8607 09:58:24.575310 Set Vref, RX VrefLevel [Byte0]: 46
8608 09:58:24.578585 [Byte1]: 46
8609 09:58:24.583002
8610 09:58:24.583272 Set Vref, RX VrefLevel [Byte0]: 47
8611 09:58:24.586712 [Byte1]: 47
8612 09:58:24.590579
8613 09:58:24.590824 Set Vref, RX VrefLevel [Byte0]: 48
8614 09:58:24.593770 [Byte1]: 48
8615 09:58:24.597754
8616 09:58:24.597837 Set Vref, RX VrefLevel [Byte0]: 49
8617 09:58:24.601340 [Byte1]: 49
8618 09:58:24.605367
8619 09:58:24.605452 Set Vref, RX VrefLevel [Byte0]: 50
8620 09:58:24.608708 [Byte1]: 50
8621 09:58:24.613089
8622 09:58:24.613173 Set Vref, RX VrefLevel [Byte0]: 51
8623 09:58:24.616264 [Byte1]: 51
8624 09:58:24.620624
8625 09:58:24.620708 Set Vref, RX VrefLevel [Byte0]: 52
8626 09:58:24.623922 [Byte1]: 52
8627 09:58:24.628544
8628 09:58:24.628627 Set Vref, RX VrefLevel [Byte0]: 53
8629 09:58:24.631424 [Byte1]: 53
8630 09:58:24.635690
8631 09:58:24.635796 Set Vref, RX VrefLevel [Byte0]: 54
8632 09:58:24.638909 [Byte1]: 54
8633 09:58:24.643405
8634 09:58:24.643487 Set Vref, RX VrefLevel [Byte0]: 55
8635 09:58:24.646733 [Byte1]: 55
8636 09:58:24.651054
8637 09:58:24.651140 Set Vref, RX VrefLevel [Byte0]: 56
8638 09:58:24.654943 [Byte1]: 56
8639 09:58:24.658292
8640 09:58:24.658421 Set Vref, RX VrefLevel [Byte0]: 57
8641 09:58:24.661780 [Byte1]: 57
8642 09:58:24.666094
8643 09:58:24.666192 Set Vref, RX VrefLevel [Byte0]: 58
8644 09:58:24.669500 [Byte1]: 58
8645 09:58:24.674020
8646 09:58:24.674102 Set Vref, RX VrefLevel [Byte0]: 59
8647 09:58:24.677253 [Byte1]: 59
8648 09:58:24.681294
8649 09:58:24.681376 Set Vref, RX VrefLevel [Byte0]: 60
8650 09:58:24.684969 [Byte1]: 60
8651 09:58:24.688850
8652 09:58:24.688933 Set Vref, RX VrefLevel [Byte0]: 61
8653 09:58:24.692560 [Byte1]: 61
8654 09:58:24.696145
8655 09:58:24.696231 Set Vref, RX VrefLevel [Byte0]: 62
8656 09:58:24.699547 [Byte1]: 62
8657 09:58:24.703730
8658 09:58:24.703813 Set Vref, RX VrefLevel [Byte0]: 63
8659 09:58:24.707312 [Byte1]: 63
8660 09:58:24.711751
8661 09:58:24.711833 Set Vref, RX VrefLevel [Byte0]: 64
8662 09:58:24.714812 [Byte1]: 64
8663 09:58:24.719142
8664 09:58:24.719226 Set Vref, RX VrefLevel [Byte0]: 65
8665 09:58:24.722569 [Byte1]: 65
8666 09:58:24.726407
8667 09:58:24.729889 Set Vref, RX VrefLevel [Byte0]: 66
8668 09:58:24.732938 [Byte1]: 66
8669 09:58:24.733020
8670 09:58:24.736521 Set Vref, RX VrefLevel [Byte0]: 67
8671 09:58:24.739837 [Byte1]: 67
8672 09:58:24.739920
8673 09:58:24.743031 Set Vref, RX VrefLevel [Byte0]: 68
8674 09:58:24.746065 [Byte1]: 68
8675 09:58:24.746181
8676 09:58:24.749502 Set Vref, RX VrefLevel [Byte0]: 69
8677 09:58:24.752760 [Byte1]: 69
8678 09:58:24.757055
8679 09:58:24.757138 Set Vref, RX VrefLevel [Byte0]: 70
8680 09:58:24.760047 [Byte1]: 70
8681 09:58:24.764326
8682 09:58:24.764408 Set Vref, RX VrefLevel [Byte0]: 71
8683 09:58:24.767798 [Byte1]: 71
8684 09:58:24.771984
8685 09:58:24.772067 Set Vref, RX VrefLevel [Byte0]: 72
8686 09:58:24.775598 [Byte1]: 72
8687 09:58:24.779578
8688 09:58:24.779661 Set Vref, RX VrefLevel [Byte0]: 73
8689 09:58:24.782951 [Byte1]: 73
8690 09:58:24.787393
8691 09:58:24.787508 Set Vref, RX VrefLevel [Byte0]: 74
8692 09:58:24.790323 [Byte1]: 74
8693 09:58:24.795044
8694 09:58:24.795127 Set Vref, RX VrefLevel [Byte0]: 75
8695 09:58:24.797885 [Byte1]: 75
8696 09:58:24.802347
8697 09:58:24.802488 Final RX Vref Byte 0 = 58 to rank0
8698 09:58:24.805757 Final RX Vref Byte 1 = 66 to rank0
8699 09:58:24.809063 Final RX Vref Byte 0 = 58 to rank1
8700 09:58:24.812942 Final RX Vref Byte 1 = 66 to rank1==
8701 09:58:24.815745 Dram Type= 6, Freq= 0, CH_1, rank 0
8702 09:58:24.822114 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8703 09:58:24.822200 ==
8704 09:58:24.822266 DQS Delay:
8705 09:58:24.822329 DQS0 = 0, DQS1 = 0
8706 09:58:24.825305 DQM Delay:
8707 09:58:24.825430 DQM0 = 134, DQM1 = 129
8708 09:58:24.828716 DQ Delay:
8709 09:58:24.832079 DQ0 =136, DQ1 =128, DQ2 =122, DQ3 =132
8710 09:58:24.835797 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =132
8711 09:58:24.838837 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =122
8712 09:58:24.842175 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =134
8713 09:58:24.842259
8714 09:58:24.842324
8715 09:58:24.842409
8716 09:58:24.845476 [DramC_TX_OE_Calibration] TA2
8717 09:58:24.849079 Original DQ_B0 (3 6) =30, OEN = 27
8718 09:58:24.852454 Original DQ_B1 (3 6) =30, OEN = 27
8719 09:58:24.855455 24, 0x0, End_B0=24 End_B1=24
8720 09:58:24.855543 25, 0x0, End_B0=25 End_B1=25
8721 09:58:24.858812 26, 0x0, End_B0=26 End_B1=26
8722 09:58:24.861827 27, 0x0, End_B0=27 End_B1=27
8723 09:58:24.864987 28, 0x0, End_B0=28 End_B1=28
8724 09:58:24.868961 29, 0x0, End_B0=29 End_B1=29
8725 09:58:24.869073 30, 0x0, End_B0=30 End_B1=30
8726 09:58:24.871716 31, 0x4545, End_B0=30 End_B1=30
8727 09:58:24.875054 Byte0 end_step=30 best_step=27
8728 09:58:24.878499 Byte1 end_step=30 best_step=27
8729 09:58:24.881933 Byte0 TX OE(2T, 0.5T) = (3, 3)
8730 09:58:24.885361 Byte1 TX OE(2T, 0.5T) = (3, 3)
8731 09:58:24.885449
8732 09:58:24.885516
8733 09:58:24.891947 [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8734 09:58:24.895665 CH1 RK0: MR19=303, MR18=1826
8735 09:58:24.902090 CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16
8736 09:58:24.902244
8737 09:58:24.905367 ----->DramcWriteLeveling(PI) begin...
8738 09:58:24.905535 ==
8739 09:58:24.908441 Dram Type= 6, Freq= 0, CH_1, rank 1
8740 09:58:24.911780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8741 09:58:24.911929 ==
8742 09:58:24.915069 Write leveling (Byte 0): 25 => 25
8743 09:58:24.918570 Write leveling (Byte 1): 29 => 29
8744 09:58:24.921674 DramcWriteLeveling(PI) end<-----
8745 09:58:24.921812
8746 09:58:24.921895 ==
8747 09:58:24.925504 Dram Type= 6, Freq= 0, CH_1, rank 1
8748 09:58:24.928305 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8749 09:58:24.928430 ==
8750 09:58:24.931558 [Gating] SW mode calibration
8751 09:58:24.938067 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8752 09:58:24.945168 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8753 09:58:24.948346 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8754 09:58:24.955286 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8755 09:58:24.958454 1 4 8 | B1->B0 | 3030 2323 | 1 0 | (1 1) (0 0)
8756 09:58:24.961701 1 4 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 0)
8757 09:58:24.968984 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8758 09:58:24.971702 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8759 09:58:24.974792 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8760 09:58:24.978443 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8761 09:58:24.985054 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8762 09:58:24.988409 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8763 09:58:24.991534 1 5 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 0)
8764 09:58:24.998399 1 5 12 | B1->B0 | 2323 2e2e | 0 0 | (1 0) (0 1)
8765 09:58:25.001992 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8766 09:58:25.005038 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 09:58:25.011832 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 09:58:25.014844 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 09:58:25.018366 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 09:58:25.024880 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 09:58:25.028439 1 6 8 | B1->B0 | 4141 2424 | 1 0 | (0 0) (0 0)
8772 09:58:25.031619 1 6 12 | B1->B0 | 4646 3333 | 0 1 | (0 0) (0 0)
8773 09:58:25.038020 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8774 09:58:25.041546 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8775 09:58:25.044701 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8776 09:58:25.051530 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 09:58:25.054813 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8778 09:58:25.058201 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8779 09:58:25.065193 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8780 09:58:25.068525 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8781 09:58:25.071433 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8782 09:58:25.078101 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 09:58:25.081687 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 09:58:25.085049 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 09:58:25.091339 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 09:58:25.094682 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 09:58:25.098026 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 09:58:25.101268 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 09:58:25.108265 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 09:58:25.111553 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 09:58:25.114949 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 09:58:25.121599 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 09:58:25.124465 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 09:58:25.127837 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 09:58:25.134729 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8796 09:58:25.138062 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8797 09:58:25.141067 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 09:58:25.144258 Total UI for P1: 0, mck2ui 16
8799 09:58:25.147733 best dqsien dly found for B0: ( 1, 9, 10)
8800 09:58:25.150847 Total UI for P1: 0, mck2ui 16
8801 09:58:25.154446 best dqsien dly found for B1: ( 1, 9, 10)
8802 09:58:25.157647 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8803 09:58:25.161445 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8804 09:58:25.164762
8805 09:58:25.167827 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8806 09:58:25.170786 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8807 09:58:25.174180 [Gating] SW calibration Done
8808 09:58:25.174653 ==
8809 09:58:25.177922 Dram Type= 6, Freq= 0, CH_1, rank 1
8810 09:58:25.180975 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8811 09:58:25.181511 ==
8812 09:58:25.181957 RX Vref Scan: 0
8813 09:58:25.184391
8814 09:58:25.184902 RX Vref 0 -> 0, step: 1
8815 09:58:25.185353
8816 09:58:25.187585 RX Delay 0 -> 252, step: 8
8817 09:58:25.190898 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8818 09:58:25.194041 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8819 09:58:25.201273 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8820 09:58:25.204385 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8821 09:58:25.207816 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8822 09:58:25.210948 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8823 09:58:25.214553 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8824 09:58:25.220774 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8825 09:58:25.224360 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8826 09:58:25.227666 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8827 09:58:25.231428 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8828 09:58:25.234087 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8829 09:58:25.240723 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8830 09:58:25.244132 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8831 09:58:25.247356 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8832 09:58:25.250450 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8833 09:58:25.250885 ==
8834 09:58:25.254097 Dram Type= 6, Freq= 0, CH_1, rank 1
8835 09:58:25.260842 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8836 09:58:25.261417 ==
8837 09:58:25.261797 DQS Delay:
8838 09:58:25.262120 DQS0 = 0, DQS1 = 0
8839 09:58:25.263855 DQM Delay:
8840 09:58:25.264274 DQM0 = 137, DQM1 = 132
8841 09:58:25.267244 DQ Delay:
8842 09:58:25.270650 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8843 09:58:25.273939 DQ4 =139, DQ5 =147, DQ6 =139, DQ7 =139
8844 09:58:25.277340 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8845 09:58:25.280743 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143
8846 09:58:25.281283
8847 09:58:25.281640
8848 09:58:25.281987 ==
8849 09:58:25.284110 Dram Type= 6, Freq= 0, CH_1, rank 1
8850 09:58:25.287233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8851 09:58:25.287789 ==
8852 09:58:25.290601
8853 09:58:25.291020
8854 09:58:25.291355 TX Vref Scan disable
8855 09:58:25.294225 == TX Byte 0 ==
8856 09:58:25.297511 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8857 09:58:25.301041 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8858 09:58:25.304358 == TX Byte 1 ==
8859 09:58:25.307783 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8860 09:58:25.310846 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8861 09:58:25.311379 ==
8862 09:58:25.313959 Dram Type= 6, Freq= 0, CH_1, rank 1
8863 09:58:25.320610 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8864 09:58:25.321139 ==
8865 09:58:25.331759
8866 09:58:25.334529 TX Vref early break, caculate TX vref
8867 09:58:25.338044 TX Vref=16, minBit 11, minWin=22, winSum=381
8868 09:58:25.341619 TX Vref=18, minBit 8, minWin=23, winSum=388
8869 09:58:25.344475 TX Vref=20, minBit 9, minWin=23, winSum=396
8870 09:58:25.347771 TX Vref=22, minBit 9, minWin=24, winSum=405
8871 09:58:25.351004 TX Vref=24, minBit 9, minWin=24, winSum=412
8872 09:58:25.358023 TX Vref=26, minBit 9, minWin=25, winSum=417
8873 09:58:25.361079 TX Vref=28, minBit 9, minWin=24, winSum=415
8874 09:58:25.364942 TX Vref=30, minBit 10, minWin=23, winSum=405
8875 09:58:25.367709 TX Vref=32, minBit 9, minWin=22, winSum=394
8876 09:58:25.374483 [TxChooseVref] Worse bit 9, Min win 25, Win sum 417, Final Vref 26
8877 09:58:25.375017
8878 09:58:25.378194 Final TX Range 0 Vref 26
8879 09:58:25.378772
8880 09:58:25.379115 ==
8881 09:58:25.381046 Dram Type= 6, Freq= 0, CH_1, rank 1
8882 09:58:25.384595 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8883 09:58:25.385168 ==
8884 09:58:25.385516
8885 09:58:25.385831
8886 09:58:25.387739 TX Vref Scan disable
8887 09:58:25.391262 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8888 09:58:25.394700 == TX Byte 0 ==
8889 09:58:25.397861 u2DelayCellOfst[0]=17 cells (5 PI)
8890 09:58:25.401522 u2DelayCellOfst[1]=6 cells (2 PI)
8891 09:58:25.404451 u2DelayCellOfst[2]=0 cells (0 PI)
8892 09:58:25.408002 u2DelayCellOfst[3]=3 cells (1 PI)
8893 09:58:25.411312 u2DelayCellOfst[4]=6 cells (2 PI)
8894 09:58:25.411832 u2DelayCellOfst[5]=17 cells (5 PI)
8895 09:58:25.414527 u2DelayCellOfst[6]=17 cells (5 PI)
8896 09:58:25.417736 u2DelayCellOfst[7]=3 cells (1 PI)
8897 09:58:25.424448 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8898 09:58:25.427774 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8899 09:58:25.428298 == TX Byte 1 ==
8900 09:58:25.430974 u2DelayCellOfst[8]=0 cells (0 PI)
8901 09:58:25.434587 u2DelayCellOfst[9]=3 cells (1 PI)
8902 09:58:25.437733 u2DelayCellOfst[10]=6 cells (2 PI)
8903 09:58:25.441107 u2DelayCellOfst[11]=3 cells (1 PI)
8904 09:58:25.444358 u2DelayCellOfst[12]=13 cells (4 PI)
8905 09:58:25.447520 u2DelayCellOfst[13]=17 cells (5 PI)
8906 09:58:25.450657 u2DelayCellOfst[14]=17 cells (5 PI)
8907 09:58:25.454158 u2DelayCellOfst[15]=17 cells (5 PI)
8908 09:58:25.457521 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8909 09:58:25.460907 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8910 09:58:25.464524 DramC Write-DBI on
8911 09:58:25.465047 ==
8912 09:58:25.467233 Dram Type= 6, Freq= 0, CH_1, rank 1
8913 09:58:25.470980 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8914 09:58:25.471530 ==
8915 09:58:25.471890
8916 09:58:25.472201
8917 09:58:25.474077 TX Vref Scan disable
8918 09:58:25.477355 == TX Byte 0 ==
8919 09:58:25.481208 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8920 09:58:25.481744 == TX Byte 1 ==
8921 09:58:25.487503 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8922 09:58:25.488031 DramC Write-DBI off
8923 09:58:25.488373
8924 09:58:25.491070 [DATLAT]
8925 09:58:25.491598 Freq=1600, CH1 RK1
8926 09:58:25.491939
8927 09:58:25.494477 DATLAT Default: 0xf
8928 09:58:25.494999 0, 0xFFFF, sum = 0
8929 09:58:25.497396 1, 0xFFFF, sum = 0
8930 09:58:25.497822 2, 0xFFFF, sum = 0
8931 09:58:25.500887 3, 0xFFFF, sum = 0
8932 09:58:25.501418 4, 0xFFFF, sum = 0
8933 09:58:25.504182 5, 0xFFFF, sum = 0
8934 09:58:25.504710 6, 0xFFFF, sum = 0
8935 09:58:25.507471 7, 0xFFFF, sum = 0
8936 09:58:25.508006 8, 0xFFFF, sum = 0
8937 09:58:25.510741 9, 0xFFFF, sum = 0
8938 09:58:25.511296 10, 0xFFFF, sum = 0
8939 09:58:25.514309 11, 0xFFFF, sum = 0
8940 09:58:25.514883 12, 0xFFFF, sum = 0
8941 09:58:25.517404 13, 0xFFFF, sum = 0
8942 09:58:25.517961 14, 0x0, sum = 1
8943 09:58:25.520944 15, 0x0, sum = 2
8944 09:58:25.521465 16, 0x0, sum = 3
8945 09:58:25.524578 17, 0x0, sum = 4
8946 09:58:25.525102 best_step = 15
8947 09:58:25.525438
8948 09:58:25.525752 ==
8949 09:58:25.527673 Dram Type= 6, Freq= 0, CH_1, rank 1
8950 09:58:25.533979 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8951 09:58:25.534767 ==
8952 09:58:25.535306 RX Vref Scan: 0
8953 09:58:25.535774
8954 09:58:25.537398 RX Vref 0 -> 0, step: 1
8955 09:58:25.537951
8956 09:58:25.541014 RX Delay 19 -> 252, step: 4
8957 09:58:25.543858 iDelay=195, Bit 0, Center 138 (95 ~ 182) 88
8958 09:58:25.547512 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8959 09:58:25.550736 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8960 09:58:25.557453 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8961 09:58:25.561007 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8962 09:58:25.564345 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8963 09:58:25.567465 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8964 09:58:25.570660 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
8965 09:58:25.573903 iDelay=195, Bit 8, Center 114 (67 ~ 162) 96
8966 09:58:25.580413 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8967 09:58:25.584234 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8968 09:58:25.587157 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8969 09:58:25.590435 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8970 09:58:25.597351 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8971 09:58:25.600624 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8972 09:58:25.604228 iDelay=195, Bit 15, Center 142 (91 ~ 194) 104
8973 09:58:25.604767 ==
8974 09:58:25.607211 Dram Type= 6, Freq= 0, CH_1, rank 1
8975 09:58:25.610844 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8976 09:58:25.611403 ==
8977 09:58:25.614285 DQS Delay:
8978 09:58:25.614862 DQS0 = 0, DQS1 = 0
8979 09:58:25.615208 DQM Delay:
8980 09:58:25.617335 DQM0 = 133, DQM1 = 130
8981 09:58:25.617871 DQ Delay:
8982 09:58:25.620594 DQ0 =138, DQ1 =130, DQ2 =120, DQ3 =132
8983 09:58:25.623840 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =130
8984 09:58:25.630622 DQ8 =114, DQ9 =118, DQ10 =132, DQ11 =124
8985 09:58:25.633810 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =142
8986 09:58:25.634240
8987 09:58:25.634658
8988 09:58:25.634990
8989 09:58:25.637021 [DramC_TX_OE_Calibration] TA2
8990 09:58:25.640536 Original DQ_B0 (3 6) =30, OEN = 27
8991 09:58:25.643552 Original DQ_B1 (3 6) =30, OEN = 27
8992 09:58:25.643982 24, 0x0, End_B0=24 End_B1=24
8993 09:58:25.647116 25, 0x0, End_B0=25 End_B1=25
8994 09:58:25.650330 26, 0x0, End_B0=26 End_B1=26
8995 09:58:25.653697 27, 0x0, End_B0=27 End_B1=27
8996 09:58:25.654129 28, 0x0, End_B0=28 End_B1=28
8997 09:58:25.657004 29, 0x0, End_B0=29 End_B1=29
8998 09:58:25.660199 30, 0x0, End_B0=30 End_B1=30
8999 09:58:25.663453 31, 0x4141, End_B0=30 End_B1=30
9000 09:58:25.667045 Byte0 end_step=30 best_step=27
9001 09:58:25.670368 Byte1 end_step=30 best_step=27
9002 09:58:25.670838 Byte0 TX OE(2T, 0.5T) = (3, 3)
9003 09:58:25.673804 Byte1 TX OE(2T, 0.5T) = (3, 3)
9004 09:58:25.674227
9005 09:58:25.674620
9006 09:58:25.683753 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c06, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
9007 09:58:25.684285 CH1 RK1: MR19=303, MR18=1C06
9008 09:58:25.690160 CH1_RK1: MR19=0x303, MR18=0x1C06, DQSOSC=395, MR23=63, INC=23, DEC=15
9009 09:58:25.693641 [RxdqsGatingPostProcess] freq 1600
9010 09:58:25.700608 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9011 09:58:25.703398 best DQS0 dly(2T, 0.5T) = (1, 1)
9012 09:58:25.706856 best DQS1 dly(2T, 0.5T) = (1, 1)
9013 09:58:25.710546 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9014 09:58:25.713595 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9015 09:58:25.717303 best DQS0 dly(2T, 0.5T) = (1, 1)
9016 09:58:25.717837 best DQS1 dly(2T, 0.5T) = (1, 1)
9017 09:58:25.720280 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9018 09:58:25.723817 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9019 09:58:25.727282 Pre-setting of DQS Precalculation
9020 09:58:25.733750 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9021 09:58:25.739910 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9022 09:58:25.746550 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9023 09:58:25.747133
9024 09:58:25.747492
9025 09:58:25.750005 [Calibration Summary] 3200 Mbps
9026 09:58:25.753551 CH 0, Rank 0
9027 09:58:25.754082 SW Impedance : PASS
9028 09:58:25.756297 DUTY Scan : NO K
9029 09:58:25.756730 ZQ Calibration : PASS
9030 09:58:25.760227 Jitter Meter : NO K
9031 09:58:25.763236 CBT Training : PASS
9032 09:58:25.763653 Write leveling : PASS
9033 09:58:25.766336 RX DQS gating : PASS
9034 09:58:25.769722 RX DQ/DQS(RDDQC) : PASS
9035 09:58:25.770141 TX DQ/DQS : PASS
9036 09:58:25.773162 RX DATLAT : PASS
9037 09:58:25.776531 RX DQ/DQS(Engine): PASS
9038 09:58:25.777063 TX OE : PASS
9039 09:58:25.779908 All Pass.
9040 09:58:25.780428
9041 09:58:25.780810 CH 0, Rank 1
9042 09:58:25.783008 SW Impedance : PASS
9043 09:58:25.783429 DUTY Scan : NO K
9044 09:58:25.786157 ZQ Calibration : PASS
9045 09:58:25.789440 Jitter Meter : NO K
9046 09:58:25.789918 CBT Training : PASS
9047 09:58:25.793149 Write leveling : PASS
9048 09:58:25.796429 RX DQS gating : PASS
9049 09:58:25.796951 RX DQ/DQS(RDDQC) : PASS
9050 09:58:25.799205 TX DQ/DQS : PASS
9051 09:58:25.803098 RX DATLAT : PASS
9052 09:58:25.803618 RX DQ/DQS(Engine): PASS
9053 09:58:25.806190 TX OE : PASS
9054 09:58:25.806762 All Pass.
9055 09:58:25.807105
9056 09:58:25.809843 CH 1, Rank 0
9057 09:58:25.810378 SW Impedance : PASS
9058 09:58:25.812999 DUTY Scan : NO K
9059 09:58:25.813449 ZQ Calibration : PASS
9060 09:58:25.816209 Jitter Meter : NO K
9061 09:58:25.819885 CBT Training : PASS
9062 09:58:25.820407 Write leveling : PASS
9063 09:58:25.823034 RX DQS gating : PASS
9064 09:58:25.826619 RX DQ/DQS(RDDQC) : PASS
9065 09:58:25.827137 TX DQ/DQS : PASS
9066 09:58:25.829597 RX DATLAT : PASS
9067 09:58:25.832981 RX DQ/DQS(Engine): PASS
9068 09:58:25.833503 TX OE : PASS
9069 09:58:25.835741 All Pass.
9070 09:58:25.836155
9071 09:58:25.836485 CH 1, Rank 1
9072 09:58:25.839285 SW Impedance : PASS
9073 09:58:25.839701 DUTY Scan : NO K
9074 09:58:25.842931 ZQ Calibration : PASS
9075 09:58:25.845980 Jitter Meter : NO K
9076 09:58:25.846413 CBT Training : PASS
9077 09:58:25.849258 Write leveling : PASS
9078 09:58:25.853160 RX DQS gating : PASS
9079 09:58:25.853727 RX DQ/DQS(RDDQC) : PASS
9080 09:58:25.855706 TX DQ/DQS : PASS
9081 09:58:25.859461 RX DATLAT : PASS
9082 09:58:25.859878 RX DQ/DQS(Engine): PASS
9083 09:58:25.862350 TX OE : PASS
9084 09:58:25.862801 All Pass.
9085 09:58:25.863136
9086 09:58:25.865997 DramC Write-DBI on
9087 09:58:25.869019 PER_BANK_REFRESH: Hybrid Mode
9088 09:58:25.869574 TX_TRACKING: ON
9089 09:58:25.878929 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9090 09:58:25.885873 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9091 09:58:25.892190 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9092 09:58:25.895427 [FAST_K] Save calibration result to emmc
9093 09:58:25.899004 sync common calibartion params.
9094 09:58:25.901947 sync cbt_mode0:1, 1:1
9095 09:58:25.905705 dram_init: ddr_geometry: 2
9096 09:58:25.906001 dram_init: ddr_geometry: 2
9097 09:58:25.908682 dram_init: ddr_geometry: 2
9098 09:58:25.911768 0:dram_rank_size:100000000
9099 09:58:25.911996 1:dram_rank_size:100000000
9100 09:58:25.918565 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9101 09:58:25.921885 DFS_SHUFFLE_HW_MODE: ON
9102 09:58:25.924941 dramc_set_vcore_voltage set vcore to 725000
9103 09:58:25.928619 Read voltage for 1600, 0
9104 09:58:25.928749 Vio18 = 0
9105 09:58:25.928854 Vcore = 725000
9106 09:58:25.931959 Vdram = 0
9107 09:58:25.932073 Vddq = 0
9108 09:58:25.932164 Vmddr = 0
9109 09:58:25.935051 switch to 3200 Mbps bootup
9110 09:58:25.935152 [DramcRunTimeConfig]
9111 09:58:25.938288 PHYPLL
9112 09:58:25.938397 DPM_CONTROL_AFTERK: ON
9113 09:58:25.941367 PER_BANK_REFRESH: ON
9114 09:58:25.945301 REFRESH_OVERHEAD_REDUCTION: ON
9115 09:58:25.945386 CMD_PICG_NEW_MODE: OFF
9116 09:58:25.948529 XRTWTW_NEW_MODE: ON
9117 09:58:25.948616 XRTRTR_NEW_MODE: ON
9118 09:58:25.951544 TX_TRACKING: ON
9119 09:58:25.951627 RDSEL_TRACKING: OFF
9120 09:58:25.954777 DQS Precalculation for DVFS: ON
9121 09:58:25.958632 RX_TRACKING: OFF
9122 09:58:25.958736 HW_GATING DBG: ON
9123 09:58:25.961497 ZQCS_ENABLE_LP4: ON
9124 09:58:25.961580 RX_PICG_NEW_MODE: ON
9125 09:58:25.964940 TX_PICG_NEW_MODE: ON
9126 09:58:25.968237 ENABLE_RX_DCM_DPHY: ON
9127 09:58:25.968318 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9128 09:58:25.971681 DUMMY_READ_FOR_TRACKING: OFF
9129 09:58:25.974694 !!! SPM_CONTROL_AFTERK: OFF
9130 09:58:25.978071 !!! SPM could not control APHY
9131 09:58:25.978159 IMPEDANCE_TRACKING: ON
9132 09:58:25.981234 TEMP_SENSOR: ON
9133 09:58:25.981321 HW_SAVE_FOR_SR: OFF
9134 09:58:25.985452 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9135 09:58:25.988084 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9136 09:58:25.991320 Read ODT Tracking: ON
9137 09:58:25.994576 Refresh Rate DeBounce: ON
9138 09:58:25.994660 DFS_NO_QUEUE_FLUSH: ON
9139 09:58:25.998173 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9140 09:58:26.001328 ENABLE_DFS_RUNTIME_MRW: OFF
9141 09:58:26.004516 DDR_RESERVE_NEW_MODE: ON
9142 09:58:26.004602 MR_CBT_SWITCH_FREQ: ON
9143 09:58:26.008432 =========================
9144 09:58:26.027213 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9145 09:58:26.030410 dram_init: ddr_geometry: 2
9146 09:58:26.048673 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9147 09:58:26.051695 dram_init: dram init end (result: 0)
9148 09:58:26.058739 DRAM-K: Full calibration passed in 24492 msecs
9149 09:58:26.061749 MRC: failed to locate region type 0.
9150 09:58:26.061863 DRAM rank0 size:0x100000000,
9151 09:58:26.065025 DRAM rank1 size=0x100000000
9152 09:58:26.075230 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9153 09:58:26.081638 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9154 09:58:26.088406 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9155 09:58:26.095173 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9156 09:58:26.098209 DRAM rank0 size:0x100000000,
9157 09:58:26.101803 DRAM rank1 size=0x100000000
9158 09:58:26.101902 CBMEM:
9159 09:58:26.105232 IMD: root @ 0xfffff000 254 entries.
9160 09:58:26.108027 IMD: root @ 0xffffec00 62 entries.
9161 09:58:26.111576 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9162 09:58:26.114858 WARNING: RO_VPD is uninitialized or empty.
9163 09:58:26.121409 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9164 09:58:26.128652 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9165 09:58:26.141371 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9166 09:58:26.152651 BS: romstage times (exec / console): total (unknown) / 23992 ms
9167 09:58:26.152791
9168 09:58:26.152859
9169 09:58:26.162754 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9170 09:58:26.166061 ARM64: Exception handlers installed.
9171 09:58:26.169398 ARM64: Testing exception
9172 09:58:26.172792 ARM64: Done test exception
9173 09:58:26.172880 Enumerating buses...
9174 09:58:26.175825 Show all devs... Before device enumeration.
9175 09:58:26.179068 Root Device: enabled 1
9176 09:58:26.182420 CPU_CLUSTER: 0: enabled 1
9177 09:58:26.182523 CPU: 00: enabled 1
9178 09:58:26.186314 Compare with tree...
9179 09:58:26.186449 Root Device: enabled 1
9180 09:58:26.189427 CPU_CLUSTER: 0: enabled 1
9181 09:58:26.192414 CPU: 00: enabled 1
9182 09:58:26.192507 Root Device scanning...
9183 09:58:26.195705 scan_static_bus for Root Device
9184 09:58:26.199288 CPU_CLUSTER: 0 enabled
9185 09:58:26.202274 scan_static_bus for Root Device done
9186 09:58:26.205651 scan_bus: bus Root Device finished in 8 msecs
9187 09:58:26.205745 done
9188 09:58:26.212656 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9189 09:58:26.215633 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9190 09:58:26.222277 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9191 09:58:26.226001 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9192 09:58:26.228912 Allocating resources...
9193 09:58:26.232162 Reading resources...
9194 09:58:26.235497 Root Device read_resources bus 0 link: 0
9195 09:58:26.235581 DRAM rank0 size:0x100000000,
9196 09:58:26.238962 DRAM rank1 size=0x100000000
9197 09:58:26.242163 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9198 09:58:26.245431 CPU: 00 missing read_resources
9199 09:58:26.249234 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9200 09:58:26.255534 Root Device read_resources bus 0 link: 0 done
9201 09:58:26.255621 Done reading resources.
9202 09:58:26.262464 Show resources in subtree (Root Device)...After reading.
9203 09:58:26.265862 Root Device child on link 0 CPU_CLUSTER: 0
9204 09:58:26.269122 CPU_CLUSTER: 0 child on link 0 CPU: 00
9205 09:58:26.279405 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9206 09:58:26.279565 CPU: 00
9207 09:58:26.282294 Root Device assign_resources, bus 0 link: 0
9208 09:58:26.285838 CPU_CLUSTER: 0 missing set_resources
9209 09:58:26.292626 Root Device assign_resources, bus 0 link: 0 done
9210 09:58:26.292801 Done setting resources.
9211 09:58:26.299180 Show resources in subtree (Root Device)...After assigning values.
9212 09:58:26.302240 Root Device child on link 0 CPU_CLUSTER: 0
9213 09:58:26.305562 CPU_CLUSTER: 0 child on link 0 CPU: 00
9214 09:58:26.315701 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9215 09:58:26.315936 CPU: 00
9216 09:58:26.318550 Done allocating resources.
9217 09:58:26.321825 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9218 09:58:26.325659 Enabling resources...
9219 09:58:26.325752 done.
9220 09:58:26.332188 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9221 09:58:26.332291 Initializing devices...
9222 09:58:26.335386 Root Device init
9223 09:58:26.335474 init hardware done!
9224 09:58:26.338325 0x00000018: ctrlr->caps
9225 09:58:26.341590 52.000 MHz: ctrlr->f_max
9226 09:58:26.341677 0.400 MHz: ctrlr->f_min
9227 09:58:26.345106 0x40ff8080: ctrlr->voltages
9228 09:58:26.345190 sclk: 390625
9229 09:58:26.348562 Bus Width = 1
9230 09:58:26.348648 sclk: 390625
9231 09:58:26.351837 Bus Width = 1
9232 09:58:26.351921 Early init status = 3
9233 09:58:26.358375 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9234 09:58:26.362019 in-header: 03 fb 00 00 01 00 00 00
9235 09:58:26.362110 in-data: 01
9236 09:58:26.368278 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9237 09:58:26.371421 in-header: 03 fb 00 00 01 00 00 00
9238 09:58:26.374881 in-data: 01
9239 09:58:26.378233 [SSUSB] Setting up USB HOST controller...
9240 09:58:26.381660 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9241 09:58:26.381745 [SSUSB] phy power-on done.
9242 09:58:26.388231 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9243 09:58:26.391842 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9244 09:58:26.397999 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9245 09:58:26.404860 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9246 09:58:26.411383 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9247 09:58:26.418165 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9248 09:58:26.424736 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9249 09:58:26.427975 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9250 09:58:26.431665 SPM: binary array size = 0x9dc
9251 09:58:26.437891 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9252 09:58:26.444775 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9253 09:58:26.451245 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9254 09:58:26.454739 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9255 09:58:26.457946 configure_display: Starting display init
9256 09:58:26.493918 anx7625_power_on_init: Init interface.
9257 09:58:26.497357 anx7625_disable_pd_protocol: Disabled PD feature.
9258 09:58:26.500569 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9259 09:58:26.528948 anx7625_start_dp_work: Secure OCM version=00
9260 09:58:26.532062 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9261 09:58:26.546770 sp_tx_get_edid_block: EDID Block = 1
9262 09:58:26.649749 Extracted contents:
9263 09:58:26.652812 header: 00 ff ff ff ff ff ff 00
9264 09:58:26.655795 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9265 09:58:26.659294 version: 01 04
9266 09:58:26.662390 basic params: 95 1f 11 78 0a
9267 09:58:26.665875 chroma info: 76 90 94 55 54 90 27 21 50 54
9268 09:58:26.669131 established: 00 00 00
9269 09:58:26.675844 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9270 09:58:26.679240 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9271 09:58:26.685738 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9272 09:58:26.692236 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9273 09:58:26.698952 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9274 09:58:26.702362 extensions: 00
9275 09:58:26.702570 checksum: fb
9276 09:58:26.702725
9277 09:58:26.705601 Manufacturer: IVO Model 57d Serial Number 0
9278 09:58:26.709334 Made week 0 of 2020
9279 09:58:26.709706 EDID version: 1.4
9280 09:58:26.712213 Digital display
9281 09:58:26.715826 6 bits per primary color channel
9282 09:58:26.716299 DisplayPort interface
9283 09:58:26.718834 Maximum image size: 31 cm x 17 cm
9284 09:58:26.722720 Gamma: 220%
9285 09:58:26.723245 Check DPMS levels
9286 09:58:26.725962 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9287 09:58:26.732409 First detailed timing is preferred timing
9288 09:58:26.732940 Established timings supported:
9289 09:58:26.735803 Standard timings supported:
9290 09:58:26.738966 Detailed timings
9291 09:58:26.742368 Hex of detail: 383680a07038204018303c0035ae10000019
9292 09:58:26.745483 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9293 09:58:26.752156 0780 0798 07c8 0820 hborder 0
9294 09:58:26.755231 0438 043b 0447 0458 vborder 0
9295 09:58:26.758617 -hsync -vsync
9296 09:58:26.759247 Did detailed timing
9297 09:58:26.765325 Hex of detail: 000000000000000000000000000000000000
9298 09:58:26.769105 Manufacturer-specified data, tag 0
9299 09:58:26.772159 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9300 09:58:26.775256 ASCII string: InfoVision
9301 09:58:26.778701 Hex of detail: 000000fe00523134304e574635205248200a
9302 09:58:26.781867 ASCII string: R140NWF5 RH
9303 09:58:26.782378 Checksum
9304 09:58:26.785248 Checksum: 0xfb (valid)
9305 09:58:26.788328 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9306 09:58:26.791692 DSI data_rate: 832800000 bps
9307 09:58:26.798287 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9308 09:58:26.801699 anx7625_parse_edid: pixelclock(138800).
9309 09:58:26.805414 hactive(1920), hsync(48), hfp(24), hbp(88)
9310 09:58:26.808452 vactive(1080), vsync(12), vfp(3), vbp(17)
9311 09:58:26.812397 anx7625_dsi_config: config dsi.
9312 09:58:26.818327 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9313 09:58:26.831782 anx7625_dsi_config: success to config DSI
9314 09:58:26.835300 anx7625_dp_start: MIPI phy setup OK.
9315 09:58:26.838710 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9316 09:58:26.841873 mtk_ddp_mode_set invalid vrefresh 60
9317 09:58:26.844604 main_disp_path_setup
9318 09:58:26.845016 ovl_layer_smi_id_en
9319 09:58:26.847901 ovl_layer_smi_id_en
9320 09:58:26.848312 ccorr_config
9321 09:58:26.848666 aal_config
9322 09:58:26.851290 gamma_config
9323 09:58:26.851801 postmask_config
9324 09:58:26.855307 dither_config
9325 09:58:26.858605 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9326 09:58:26.864873 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9327 09:58:26.868053 Root Device init finished in 529 msecs
9328 09:58:26.877762 CPU_CLUSTER: 0 init
9329 09:58:26.878523 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9330 09:58:26.881269 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9331 09:58:26.884618 APU_MBOX 0x190000b0 = 0x10001
9332 09:58:26.887917 APU_MBOX 0x190001b0 = 0x10001
9333 09:58:26.892717 APU_MBOX 0x190005b0 = 0x10001
9334 09:58:26.894704 APU_MBOX 0x190006b0 = 0x10001
9335 09:58:26.898337 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9336 09:58:26.910483 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9337 09:58:26.923073 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9338 09:58:26.929934 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9339 09:58:26.941441 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9340 09:58:26.950646 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9341 09:58:26.953788 CPU_CLUSTER: 0 init finished in 81 msecs
9342 09:58:26.957547 Devices initialized
9343 09:58:26.960207 Show all devs... After init.
9344 09:58:26.960626 Root Device: enabled 1
9345 09:58:26.963391 CPU_CLUSTER: 0: enabled 1
9346 09:58:26.966911 CPU: 00: enabled 1
9347 09:58:26.970378 BS: BS_DEV_INIT run times (exec / console): 206 / 428 ms
9348 09:58:26.973900 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9349 09:58:26.977305 ELOG: NV offset 0x57f000 size 0x1000
9350 09:58:26.983569 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9351 09:58:26.990175 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9352 09:58:26.993636 ELOG: Event(17) added with size 13 at 2023-11-24 09:57:54 UTC
9353 09:58:26.997333 out: cmd=0x121: 03 db 21 01 00 00 00 00
9354 09:58:27.001634 in-header: 03 52 00 00 2c 00 00 00
9355 09:58:27.015866 in-data: 0d 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9356 09:58:27.021384 ELOG: Event(A1) added with size 10 at 2023-11-24 09:57:54 UTC
9357 09:58:27.028103 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9358 09:58:27.035198 ELOG: Event(A0) added with size 9 at 2023-11-24 09:57:54 UTC
9359 09:58:27.038232 elog_add_boot_reason: Logged dev mode boot
9360 09:58:27.041366 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9361 09:58:27.045226 Finalize devices...
9362 09:58:27.045749 Devices finalized
9363 09:58:27.051734 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9364 09:58:27.054823 Writing coreboot table at 0xffe64000
9365 09:58:27.058028 0. 000000000010a000-0000000000113fff: RAMSTAGE
9366 09:58:27.061182 1. 0000000040000000-00000000400fffff: RAM
9367 09:58:27.064935 2. 0000000040100000-000000004032afff: RAMSTAGE
9368 09:58:27.071653 3. 000000004032b000-00000000545fffff: RAM
9369 09:58:27.074497 4. 0000000054600000-000000005465ffff: BL31
9370 09:58:27.078326 5. 0000000054660000-00000000ffe63fff: RAM
9371 09:58:27.081882 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9372 09:58:27.087991 7. 0000000100000000-000000023fffffff: RAM
9373 09:58:27.088517 Passing 5 GPIOs to payload:
9374 09:58:27.095027 NAME | PORT | POLARITY | VALUE
9375 09:58:27.098093 EC in RW | 0x000000aa | low | undefined
9376 09:58:27.104731 EC interrupt | 0x00000005 | low | undefined
9377 09:58:27.108302 TPM interrupt | 0x000000ab | high | undefined
9378 09:58:27.111221 SD card detect | 0x00000011 | high | undefined
9379 09:58:27.117697 speaker enable | 0x00000093 | high | undefined
9380 09:58:27.120814 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9381 09:58:27.124839 in-header: 03 f9 00 00 02 00 00 00
9382 09:58:27.125363 in-data: 02 00
9383 09:58:27.127937 ADC[4]: Raw value=901032 ID=7
9384 09:58:27.131010 ADC[3]: Raw value=213179 ID=1
9385 09:58:27.131550 RAM Code: 0x71
9386 09:58:27.134547 ADC[6]: Raw value=74502 ID=0
9387 09:58:27.137805 ADC[5]: Raw value=212441 ID=1
9388 09:58:27.138224 SKU Code: 0x1
9389 09:58:27.144436 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum f933
9390 09:58:27.147735 coreboot table: 964 bytes.
9391 09:58:27.150892 IMD ROOT 0. 0xfffff000 0x00001000
9392 09:58:27.154103 IMD SMALL 1. 0xffffe000 0x00001000
9393 09:58:27.157603 RO MCACHE 2. 0xffffc000 0x00001104
9394 09:58:27.161337 CONSOLE 3. 0xfff7c000 0x00080000
9395 09:58:27.164562 FMAP 4. 0xfff7b000 0x00000452
9396 09:58:27.168379 TIME STAMP 5. 0xfff7a000 0x00000910
9397 09:58:27.171111 VBOOT WORK 6. 0xfff66000 0x00014000
9398 09:58:27.174324 RAMOOPS 7. 0xffe66000 0x00100000
9399 09:58:27.178067 COREBOOT 8. 0xffe64000 0x00002000
9400 09:58:27.178618 IMD small region:
9401 09:58:27.180921 IMD ROOT 0. 0xffffec00 0x00000400
9402 09:58:27.184474 VPD 1. 0xffffeb80 0x0000006c
9403 09:58:27.187831 MMC STATUS 2. 0xffffeb60 0x00000004
9404 09:58:27.194482 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9405 09:58:27.194905 Probing TPM: done!
9406 09:58:27.200992 Connected to device vid:did:rid of 1ae0:0028:00
9407 09:58:27.207813 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9408 09:58:27.211241 Initialized TPM device CR50 revision 0
9409 09:58:27.215282 Checking cr50 for pending updates
9410 09:58:27.220863 Reading cr50 TPM mode
9411 09:58:27.229590 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9412 09:58:27.236196 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9413 09:58:27.276274 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9414 09:58:27.279926 Checking segment from ROM address 0x40100000
9415 09:58:27.283327 Checking segment from ROM address 0x4010001c
9416 09:58:27.289760 Loading segment from ROM address 0x40100000
9417 09:58:27.290328 code (compression=0)
9418 09:58:27.296996 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9419 09:58:27.306356 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9420 09:58:27.306953 it's not compressed!
9421 09:58:27.313093 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9422 09:58:27.316735 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9423 09:58:27.336417 Loading segment from ROM address 0x4010001c
9424 09:58:27.336594 Entry Point 0x80000000
9425 09:58:27.339701 Loaded segments
9426 09:58:27.342758 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9427 09:58:27.350042 Jumping to boot code at 0x80000000(0xffe64000)
9428 09:58:27.356444 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9429 09:58:27.363125 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9430 09:58:27.371027 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9431 09:58:27.374524 Checking segment from ROM address 0x40100000
9432 09:58:27.377905 Checking segment from ROM address 0x4010001c
9433 09:58:27.384598 Loading segment from ROM address 0x40100000
9434 09:58:27.385074 code (compression=1)
9435 09:58:27.391512 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9436 09:58:27.401285 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9437 09:58:27.401861 using LZMA
9438 09:58:27.409552 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9439 09:58:27.416275 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9440 09:58:27.419451 Loading segment from ROM address 0x4010001c
9441 09:58:27.420019 Entry Point 0x54601000
9442 09:58:27.422897 Loaded segments
9443 09:58:27.426550 NOTICE: MT8192 bl31_setup
9444 09:58:27.433306 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9445 09:58:27.436388 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9446 09:58:27.439644 WARNING: region 0:
9447 09:58:27.443065 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9448 09:58:27.443585 WARNING: region 1:
9449 09:58:27.449483 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9450 09:58:27.452861 WARNING: region 2:
9451 09:58:27.456253 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9452 09:58:27.459342 WARNING: region 3:
9453 09:58:27.463027 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9454 09:58:27.466633 WARNING: region 4:
9455 09:58:27.472952 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9456 09:58:27.473480 WARNING: region 5:
9457 09:58:27.476877 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9458 09:58:27.479789 WARNING: region 6:
9459 09:58:27.482897 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9460 09:58:27.486546 WARNING: region 7:
9461 09:58:27.489579 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9462 09:58:27.496526 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9463 09:58:27.499937 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9464 09:58:27.503255 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9465 09:58:27.509955 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9466 09:58:27.513406 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9467 09:58:27.516494 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9468 09:58:27.523228 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9469 09:58:27.527017 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9470 09:58:27.533256 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9471 09:58:27.536262 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9472 09:58:27.540883 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9473 09:58:27.546465 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9474 09:58:27.549702 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9475 09:58:27.553042 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9476 09:58:27.559649 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9477 09:58:27.563511 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9478 09:58:27.566573 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9479 09:58:27.573607 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9480 09:58:27.577059 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9481 09:58:27.580292 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9482 09:58:27.586438 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9483 09:58:27.590062 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9484 09:58:27.597108 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9485 09:58:27.600065 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9486 09:58:27.606509 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9487 09:58:27.610176 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9488 09:58:27.613374 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9489 09:58:27.619900 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9490 09:58:27.623244 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9491 09:58:27.626725 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9492 09:58:27.633250 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9493 09:58:27.636798 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9494 09:58:27.639785 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9495 09:58:27.646777 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9496 09:58:27.649850 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9497 09:58:27.653272 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9498 09:58:27.656576 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9499 09:58:27.663631 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9500 09:58:27.666342 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9501 09:58:27.669942 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9502 09:58:27.673602 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9503 09:58:27.680014 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9504 09:58:27.683518 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9505 09:58:27.686627 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9506 09:58:27.690221 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9507 09:58:27.696616 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9508 09:58:27.699978 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9509 09:58:27.703176 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9510 09:58:27.710103 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9511 09:58:27.713221 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9512 09:58:27.716972 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9513 09:58:27.723464 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9514 09:58:27.726774 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9515 09:58:27.733607 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9516 09:58:27.737290 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9517 09:58:27.743408 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9518 09:58:27.746706 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9519 09:58:27.750006 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9520 09:58:27.757339 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9521 09:58:27.760221 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9522 09:58:27.766720 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9523 09:58:27.770343 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9524 09:58:27.777289 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9525 09:58:27.780237 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9526 09:58:27.783730 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9527 09:58:27.790523 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9528 09:58:27.793916 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9529 09:58:27.800388 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9530 09:58:27.803801 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9531 09:58:27.810528 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9532 09:58:27.813592 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9533 09:58:27.817069 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9534 09:58:27.824122 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9535 09:58:27.827319 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9536 09:58:27.834206 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9537 09:58:27.837316 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9538 09:58:27.843723 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9539 09:58:27.846883 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9540 09:58:27.850117 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9541 09:58:27.856839 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9542 09:58:27.860388 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9543 09:58:27.867268 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9544 09:58:27.870478 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9545 09:58:27.877234 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9546 09:58:27.880489 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9547 09:58:27.884172 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9548 09:58:27.890621 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9549 09:58:27.894010 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9550 09:58:27.900682 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9551 09:58:27.903950 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9552 09:58:27.911207 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9553 09:58:27.913862 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9554 09:58:27.917226 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9555 09:58:27.924277 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9556 09:58:27.927415 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9557 09:58:27.934124 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9558 09:58:27.937768 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9559 09:58:27.941053 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9560 09:58:27.943788 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9561 09:58:27.950914 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9562 09:58:27.954347 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9563 09:58:27.957590 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9564 09:58:27.964065 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9565 09:58:27.968035 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9566 09:58:27.974451 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9567 09:58:27.977580 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9568 09:58:27.981128 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9569 09:58:27.987385 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9570 09:58:27.990745 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9571 09:58:27.997919 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9572 09:58:28.000887 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9573 09:58:28.004341 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9574 09:58:28.011013 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9575 09:58:28.014517 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9576 09:58:28.021415 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9577 09:58:28.024560 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9578 09:58:28.028176 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9579 09:58:28.031122 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9580 09:58:28.037936 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9581 09:58:28.041414 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9582 09:58:28.044849 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9583 09:58:28.047982 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9584 09:58:28.054844 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9585 09:58:28.058193 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9586 09:58:28.061545 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9587 09:58:28.068040 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9588 09:58:28.070887 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9589 09:58:28.074542 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9590 09:58:28.081301 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9591 09:58:28.084544 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9592 09:58:28.091073 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9593 09:58:28.094504 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9594 09:58:28.097613 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9595 09:58:28.104660 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9596 09:58:28.107813 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9597 09:58:28.114093 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9598 09:58:28.117675 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9599 09:58:28.120739 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9600 09:58:28.127921 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9601 09:58:28.131110 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9602 09:58:28.134529 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9603 09:58:28.141057 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9604 09:58:28.144368 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9605 09:58:28.151403 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9606 09:58:28.154566 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9607 09:58:28.158151 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9608 09:58:28.164870 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9609 09:58:28.167921 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9610 09:58:28.174799 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9611 09:58:28.177651 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9612 09:58:28.181633 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9613 09:58:28.187870 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9614 09:58:28.191088 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9615 09:58:28.194224 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9616 09:58:28.201506 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9617 09:58:28.204684 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9618 09:58:28.211071 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9619 09:58:28.214507 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9620 09:58:28.217814 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9621 09:58:28.224695 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9622 09:58:28.227946 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9623 09:58:28.231465 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9624 09:58:28.237853 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9625 09:58:28.241503 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9626 09:58:28.247765 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9627 09:58:28.251017 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9628 09:58:28.254471 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9629 09:58:28.261056 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9630 09:58:28.264354 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9631 09:58:28.270910 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9632 09:58:28.274563 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9633 09:58:28.278142 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9634 09:58:28.284194 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9635 09:58:28.288057 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9636 09:58:28.294440 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9637 09:58:28.297816 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9638 09:58:28.300896 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9639 09:58:28.307340 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9640 09:58:28.310822 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9641 09:58:28.314206 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9642 09:58:28.321077 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9643 09:58:28.324699 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9644 09:58:28.331130 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9645 09:58:28.334539 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9646 09:58:28.341175 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9647 09:58:28.344272 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9648 09:58:28.347477 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9649 09:58:28.354188 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9650 09:58:28.357276 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9651 09:58:28.364405 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9652 09:58:28.367164 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9653 09:58:28.370834 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9654 09:58:28.377021 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9655 09:58:28.380306 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9656 09:58:28.387431 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9657 09:58:28.390527 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9658 09:58:28.393639 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9659 09:58:28.400579 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9660 09:58:28.404186 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9661 09:58:28.410751 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9662 09:58:28.413762 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9663 09:58:28.417353 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9664 09:58:28.424028 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9665 09:58:28.427326 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9666 09:58:28.433871 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9667 09:58:28.436794 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9668 09:58:28.443748 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9669 09:58:28.447244 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9670 09:58:28.450600 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9671 09:58:28.457210 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9672 09:58:28.460408 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9673 09:58:28.466919 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9674 09:58:28.470583 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9675 09:58:28.473690 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9676 09:58:28.480702 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9677 09:58:28.484033 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9678 09:58:28.490541 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9679 09:58:28.493795 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9680 09:58:28.500195 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9681 09:58:28.503614 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9682 09:58:28.506573 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9683 09:58:28.513437 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9684 09:58:28.516485 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9685 09:58:28.522949 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9686 09:58:28.526773 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9687 09:58:28.533085 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9688 09:58:28.537212 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9689 09:58:28.539939 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9690 09:58:28.546638 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9691 09:58:28.549644 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9692 09:58:28.553241 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9693 09:58:28.556201 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9694 09:58:28.563022 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9695 09:58:28.566294 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9696 09:58:28.569438 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9697 09:58:28.576286 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9698 09:58:28.579572 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9699 09:58:28.583288 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9700 09:58:28.589587 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9701 09:58:28.592437 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9702 09:58:28.599250 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9703 09:58:28.602793 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9704 09:58:28.605603 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9705 09:58:28.612471 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9706 09:58:28.616128 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9707 09:58:28.619328 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9708 09:58:28.625846 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9709 09:58:28.629423 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9710 09:58:28.632627 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9711 09:58:28.639086 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9712 09:58:28.642198 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9713 09:58:28.648849 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9714 09:58:28.652191 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9715 09:58:28.655368 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9716 09:58:28.661983 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9717 09:58:28.665178 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9718 09:58:28.672022 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9719 09:58:28.675297 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9720 09:58:28.678690 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9721 09:58:28.685353 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9722 09:58:28.688820 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9723 09:58:28.691746 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9724 09:58:28.698260 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9725 09:58:28.701738 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9726 09:58:28.705060 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9727 09:58:28.711757 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9728 09:58:28.715142 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9729 09:58:28.721376 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9730 09:58:28.725188 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9731 09:58:28.728142 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9732 09:58:28.731607 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9733 09:58:28.737839 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9734 09:58:28.741205 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9735 09:58:28.744696 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9736 09:58:28.747934 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9737 09:58:28.754149 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9738 09:58:28.757911 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9739 09:58:28.761120 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9740 09:58:28.764232 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9741 09:58:28.771453 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9742 09:58:28.774734 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9743 09:58:28.777786 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9744 09:58:28.784318 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9745 09:58:28.787508 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9746 09:58:28.794034 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9747 09:58:28.797800 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9748 09:58:28.800953 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9749 09:58:28.807320 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9750 09:58:28.811123 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9751 09:58:28.814270 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9752 09:58:28.820776 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9753 09:58:28.823938 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9754 09:58:28.830586 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9755 09:58:28.833867 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9756 09:58:28.840195 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9757 09:58:28.843791 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9758 09:58:28.849996 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9759 09:58:28.853391 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9760 09:58:28.856852 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9761 09:58:28.863241 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9762 09:58:28.866582 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9763 09:58:28.873248 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9764 09:58:28.876639 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9765 09:58:28.880152 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9766 09:58:28.886651 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9767 09:58:28.890109 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9768 09:58:28.896925 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9769 09:58:28.900410 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9770 09:58:28.903308 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9771 09:58:28.910103 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9772 09:58:28.913389 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9773 09:58:28.919924 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9774 09:58:28.923002 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9775 09:58:28.926222 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9776 09:58:28.933164 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9777 09:58:28.936171 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9778 09:58:28.942866 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9779 09:58:28.946293 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9780 09:58:28.952482 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9781 09:58:28.956016 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9782 09:58:28.963013 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9783 09:58:28.965987 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9784 09:58:28.969222 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9785 09:58:28.975775 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9786 09:58:28.979516 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9787 09:58:28.985836 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9788 09:58:28.989286 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9789 09:58:28.992458 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9790 09:58:28.999341 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9791 09:58:29.002356 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9792 09:58:29.009495 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9793 09:58:29.012566 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9794 09:58:29.015489 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9795 09:58:29.022691 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9796 09:58:29.026127 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9797 09:58:29.032305 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9798 09:58:29.036029 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9799 09:58:29.039183 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9800 09:58:29.045622 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9801 09:58:29.048968 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9802 09:58:29.055443 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9803 09:58:29.058803 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9804 09:58:29.065769 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9805 09:58:29.068781 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9806 09:58:29.072188 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9807 09:58:29.078999 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9808 09:58:29.082185 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9809 09:58:29.085443 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9810 09:58:29.092236 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9811 09:58:29.095523 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9812 09:58:29.102453 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9813 09:58:29.105429 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9814 09:58:29.112032 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9815 09:58:29.115319 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9816 09:58:29.118623 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9817 09:58:29.125423 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9818 09:58:29.128555 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9819 09:58:29.135053 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9820 09:58:29.138763 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9821 09:58:29.145130 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9822 09:58:29.148342 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9823 09:58:29.151873 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9824 09:58:29.158479 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9825 09:58:29.161770 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9826 09:58:29.168879 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9827 09:58:29.171972 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9828 09:58:29.178253 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9829 09:58:29.181541 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9830 09:58:29.188101 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9831 09:58:29.191285 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9832 09:58:29.194715 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9833 09:58:29.201832 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9834 09:58:29.204908 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9835 09:58:29.211667 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9836 09:58:29.215184 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9837 09:58:29.221954 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9838 09:58:29.224629 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9839 09:58:29.228353 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9840 09:58:29.234807 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9841 09:58:29.238553 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9842 09:58:29.245075 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9843 09:58:29.248201 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9844 09:58:29.255105 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9845 09:58:29.257939 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9846 09:58:29.261694 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9847 09:58:29.268133 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9848 09:58:29.271130 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9849 09:58:29.278031 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9850 09:58:29.281238 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9851 09:58:29.288119 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9852 09:58:29.291469 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9853 09:58:29.294308 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9854 09:58:29.301395 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9855 09:58:29.304741 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9856 09:58:29.311344 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9857 09:58:29.314860 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9858 09:58:29.320871 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9859 09:58:29.324182 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9860 09:58:29.327568 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9861 09:58:29.335007 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9862 09:58:29.337823 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9863 09:58:29.344481 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9864 09:58:29.347849 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9865 09:58:29.351599 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9866 09:58:29.357735 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9867 09:58:29.360724 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9868 09:58:29.367543 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9869 09:58:29.370776 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9870 09:58:29.377530 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9871 09:58:29.381036 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9872 09:58:29.387147 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9873 09:58:29.391075 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9874 09:58:29.397709 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9875 09:58:29.400507 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9876 09:58:29.407450 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9877 09:58:29.411016 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9878 09:58:29.417196 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9879 09:58:29.420885 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9880 09:58:29.427300 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9881 09:58:29.430495 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9882 09:58:29.437194 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9883 09:58:29.440750 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9884 09:58:29.447010 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9885 09:58:29.450332 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9886 09:58:29.456938 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9887 09:58:29.460312 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9888 09:58:29.466808 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9889 09:58:29.470018 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9890 09:58:29.477093 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9891 09:58:29.479985 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9892 09:58:29.486760 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9893 09:58:29.490043 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9894 09:58:29.496518 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9895 09:58:29.500659 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9896 09:58:29.503788 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9897 09:58:29.506445 INFO: [APUAPC] vio 0
9898 09:58:29.513375 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9899 09:58:29.516745 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9900 09:58:29.519886 INFO: [APUAPC] D0_APC_0: 0x400510
9901 09:58:29.523281 INFO: [APUAPC] D0_APC_1: 0x0
9902 09:58:29.526698 INFO: [APUAPC] D0_APC_2: 0x1540
9903 09:58:29.530203 INFO: [APUAPC] D0_APC_3: 0x0
9904 09:58:29.533492 INFO: [APUAPC] D1_APC_0: 0xffffffff
9905 09:58:29.536707 INFO: [APUAPC] D1_APC_1: 0xffffffff
9906 09:58:29.539817 INFO: [APUAPC] D1_APC_2: 0x3fffff
9907 09:58:29.543293 INFO: [APUAPC] D1_APC_3: 0x0
9908 09:58:29.546424 INFO: [APUAPC] D2_APC_0: 0xffffffff
9909 09:58:29.550077 INFO: [APUAPC] D2_APC_1: 0xffffffff
9910 09:58:29.553168 INFO: [APUAPC] D2_APC_2: 0x3fffff
9911 09:58:29.556266 INFO: [APUAPC] D2_APC_3: 0x0
9912 09:58:29.560153 INFO: [APUAPC] D3_APC_0: 0xffffffff
9913 09:58:29.563634 INFO: [APUAPC] D3_APC_1: 0xffffffff
9914 09:58:29.566548 INFO: [APUAPC] D3_APC_2: 0x3fffff
9915 09:58:29.567120 INFO: [APUAPC] D3_APC_3: 0x0
9916 09:58:29.569732 INFO: [APUAPC] D4_APC_0: 0xffffffff
9917 09:58:29.576462 INFO: [APUAPC] D4_APC_1: 0xffffffff
9918 09:58:29.579615 INFO: [APUAPC] D4_APC_2: 0x3fffff
9919 09:58:29.580231 INFO: [APUAPC] D4_APC_3: 0x0
9920 09:58:29.583146 INFO: [APUAPC] D5_APC_0: 0xffffffff
9921 09:58:29.586518 INFO: [APUAPC] D5_APC_1: 0xffffffff
9922 09:58:29.589580 INFO: [APUAPC] D5_APC_2: 0x3fffff
9923 09:58:29.592906 INFO: [APUAPC] D5_APC_3: 0x0
9924 09:58:29.596267 INFO: [APUAPC] D6_APC_0: 0xffffffff
9925 09:58:29.599676 INFO: [APUAPC] D6_APC_1: 0xffffffff
9926 09:58:29.603007 INFO: [APUAPC] D6_APC_2: 0x3fffff
9927 09:58:29.606654 INFO: [APUAPC] D6_APC_3: 0x0
9928 09:58:29.610425 INFO: [APUAPC] D7_APC_0: 0xffffffff
9929 09:58:29.612980 INFO: [APUAPC] D7_APC_1: 0xffffffff
9930 09:58:29.616425 INFO: [APUAPC] D7_APC_2: 0x3fffff
9931 09:58:29.619862 INFO: [APUAPC] D7_APC_3: 0x0
9932 09:58:29.622892 INFO: [APUAPC] D8_APC_0: 0xffffffff
9933 09:58:29.626532 INFO: [APUAPC] D8_APC_1: 0xffffffff
9934 09:58:29.629790 INFO: [APUAPC] D8_APC_2: 0x3fffff
9935 09:58:29.632953 INFO: [APUAPC] D8_APC_3: 0x0
9936 09:58:29.636416 INFO: [APUAPC] D9_APC_0: 0xffffffff
9937 09:58:29.639467 INFO: [APUAPC] D9_APC_1: 0xffffffff
9938 09:58:29.643081 INFO: [APUAPC] D9_APC_2: 0x3fffff
9939 09:58:29.646098 INFO: [APUAPC] D9_APC_3: 0x0
9940 09:58:29.649562 INFO: [APUAPC] D10_APC_0: 0xffffffff
9941 09:58:29.652807 INFO: [APUAPC] D10_APC_1: 0xffffffff
9942 09:58:29.655954 INFO: [APUAPC] D10_APC_2: 0x3fffff
9943 09:58:29.659731 INFO: [APUAPC] D10_APC_3: 0x0
9944 09:58:29.662580 INFO: [APUAPC] D11_APC_0: 0xffffffff
9945 09:58:29.665867 INFO: [APUAPC] D11_APC_1: 0xffffffff
9946 09:58:29.669540 INFO: [APUAPC] D11_APC_2: 0x3fffff
9947 09:58:29.672879 INFO: [APUAPC] D11_APC_3: 0x0
9948 09:58:29.676072 INFO: [APUAPC] D12_APC_0: 0xffffffff
9949 09:58:29.679049 INFO: [APUAPC] D12_APC_1: 0xffffffff
9950 09:58:29.682602 INFO: [APUAPC] D12_APC_2: 0x3fffff
9951 09:58:29.685832 INFO: [APUAPC] D12_APC_3: 0x0
9952 09:58:29.689198 INFO: [APUAPC] D13_APC_0: 0xffffffff
9953 09:58:29.692499 INFO: [APUAPC] D13_APC_1: 0xffffffff
9954 09:58:29.695822 INFO: [APUAPC] D13_APC_2: 0x3fffff
9955 09:58:29.698990 INFO: [APUAPC] D13_APC_3: 0x0
9956 09:58:29.702587 INFO: [APUAPC] D14_APC_0: 0xffffffff
9957 09:58:29.706095 INFO: [APUAPC] D14_APC_1: 0xffffffff
9958 09:58:29.708938 INFO: [APUAPC] D14_APC_2: 0x3fffff
9959 09:58:29.712450 INFO: [APUAPC] D14_APC_3: 0x0
9960 09:58:29.715689 INFO: [APUAPC] D15_APC_0: 0xffffffff
9961 09:58:29.718968 INFO: [APUAPC] D15_APC_1: 0xffffffff
9962 09:58:29.722342 INFO: [APUAPC] D15_APC_2: 0x3fffff
9963 09:58:29.725961 INFO: [APUAPC] D15_APC_3: 0x0
9964 09:58:29.729172 INFO: [APUAPC] APC_CON: 0x4
9965 09:58:29.732891 INFO: [NOCDAPC] D0_APC_0: 0x0
9966 09:58:29.735791 INFO: [NOCDAPC] D0_APC_1: 0x0
9967 09:58:29.739106 INFO: [NOCDAPC] D1_APC_0: 0x0
9968 09:58:29.742341 INFO: [NOCDAPC] D1_APC_1: 0xfff
9969 09:58:29.742947 INFO: [NOCDAPC] D2_APC_0: 0x0
9970 09:58:29.745223 INFO: [NOCDAPC] D2_APC_1: 0xfff
9971 09:58:29.748728 INFO: [NOCDAPC] D3_APC_0: 0x0
9972 09:58:29.752489 INFO: [NOCDAPC] D3_APC_1: 0xfff
9973 09:58:29.755378 INFO: [NOCDAPC] D4_APC_0: 0x0
9974 09:58:29.759170 INFO: [NOCDAPC] D4_APC_1: 0xfff
9975 09:58:29.762254 INFO: [NOCDAPC] D5_APC_0: 0x0
9976 09:58:29.765591 INFO: [NOCDAPC] D5_APC_1: 0xfff
9977 09:58:29.768695 INFO: [NOCDAPC] D6_APC_0: 0x0
9978 09:58:29.771815 INFO: [NOCDAPC] D6_APC_1: 0xfff
9979 09:58:29.775217 INFO: [NOCDAPC] D7_APC_0: 0x0
9980 09:58:29.778421 INFO: [NOCDAPC] D7_APC_1: 0xfff
9981 09:58:29.778901 INFO: [NOCDAPC] D8_APC_0: 0x0
9982 09:58:29.781703 INFO: [NOCDAPC] D8_APC_1: 0xfff
9983 09:58:29.785131 INFO: [NOCDAPC] D9_APC_0: 0x0
9984 09:58:29.788368 INFO: [NOCDAPC] D9_APC_1: 0xfff
9985 09:58:29.791976 INFO: [NOCDAPC] D10_APC_0: 0x0
9986 09:58:29.794963 INFO: [NOCDAPC] D10_APC_1: 0xfff
9987 09:58:29.798272 INFO: [NOCDAPC] D11_APC_0: 0x0
9988 09:58:29.801640 INFO: [NOCDAPC] D11_APC_1: 0xfff
9989 09:58:29.804947 INFO: [NOCDAPC] D12_APC_0: 0x0
9990 09:58:29.808261 INFO: [NOCDAPC] D12_APC_1: 0xfff
9991 09:58:29.812168 INFO: [NOCDAPC] D13_APC_0: 0x0
9992 09:58:29.815052 INFO: [NOCDAPC] D13_APC_1: 0xfff
9993 09:58:29.818545 INFO: [NOCDAPC] D14_APC_0: 0x0
9994 09:58:29.821182 INFO: [NOCDAPC] D14_APC_1: 0xfff
9995 09:58:29.821615 INFO: [NOCDAPC] D15_APC_0: 0x0
9996 09:58:29.825188 INFO: [NOCDAPC] D15_APC_1: 0xfff
9997 09:58:29.828412 INFO: [NOCDAPC] APC_CON: 0x4
9998 09:58:29.831460 INFO: [APUAPC] set_apusys_apc done
9999 09:58:29.835132 INFO: [DEVAPC] devapc_init done
10000 09:58:29.838830 INFO: GICv3 without legacy support detected.
10001 09:58:29.844896 INFO: ARM GICv3 driver initialized in EL3
10002 09:58:29.848289 INFO: Maximum SPI INTID supported: 639
10003 09:58:29.851451 INFO: BL31: Initializing runtime services
10004 09:58:29.857803 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10005 09:58:29.861409 INFO: SPM: enable CPC mode
10006 09:58:29.864788 INFO: mcdi ready for mcusys-off-idle and system suspend
10007 09:58:29.871318 INFO: BL31: Preparing for EL3 exit to normal world
10008 09:58:29.874717 INFO: Entry point address = 0x80000000
10009 09:58:29.875477 INFO: SPSR = 0x8
10010 09:58:29.881340
10011 09:58:29.881904
10012 09:58:29.882282
10013 09:58:29.884674 Starting depthcharge on Spherion...
10014 09:58:29.885243
10015 09:58:29.885623 Wipe memory regions:
10016 09:58:29.885971
10017 09:58:29.888580 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10018 09:58:29.889136 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10019 09:58:29.889576 Setting prompt string to ['asurada:']
10020 09:58:29.889989 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10021 09:58:29.890740 [0x00000040000000, 0x00000054600000)
10022 09:58:30.009994
10023 09:58:30.010536 [0x00000054660000, 0x00000080000000)
10024 09:58:30.270510
10025 09:58:30.271026 [0x000000821a7280, 0x000000ffe64000)
10026 09:58:31.015906
10027 09:58:31.016473 [0x00000100000000, 0x00000240000000)
10028 09:58:32.906458
10029 09:58:32.909186 Initializing XHCI USB controller at 0x11200000.
10030 09:58:33.947614
10031 09:58:33.950424 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10032 09:58:33.950951
10033 09:58:33.951322
10034 09:58:33.951768
10035 09:58:33.952677 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10037 09:58:34.054329 asurada: tftpboot 192.168.201.1 12073283/tftp-deploy-xg3kmoi7/kernel/image.itb 12073283/tftp-deploy-xg3kmoi7/kernel/cmdline
10038 09:58:34.054706 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10039 09:58:34.054948 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10040 09:58:34.059768 tftpboot 192.168.201.1 12073283/tftp-deploy-xg3kmoi7/kernel/image.itp-deploy-xg3kmoi7/kernel/cmdline
10041 09:58:34.060113
10042 09:58:34.060325 Waiting for link
10043 09:58:34.220170
10044 09:58:34.220771 R8152: Initializing
10045 09:58:34.221154
10046 09:58:34.223323 Version 9 (ocp_data = 6010)
10047 09:58:34.223797
10048 09:58:34.226842 R8152: Done initializing
10049 09:58:34.227316
10050 09:58:34.227693 Adding net device
10051 09:58:36.094681
10052 09:58:36.094840 done.
10053 09:58:36.094917
10054 09:58:36.094983 MAC: 00:e0:4c:72:2d:d6
10055 09:58:36.095054
10056 09:58:36.097985 Sending DHCP discover... done.
10057 09:58:36.098068
10058 09:58:36.101541 Waiting for reply... done.
10059 09:58:36.101643
10060 09:58:36.104548 Sending DHCP request... done.
10061 09:58:36.104646
10062 09:58:36.246566 Waiting for reply... done.
10063 09:58:36.246717
10064 09:58:36.246827 My ip is 192.168.201.21
10065 09:58:36.246925
10066 09:58:36.249734 The DHCP server ip is 192.168.201.1
10067 09:58:36.249818
10068 09:58:36.256433 TFTP server IP predefined by user: 192.168.201.1
10069 09:58:36.256554
10070 09:58:36.262927 Bootfile predefined by user: 12073283/tftp-deploy-xg3kmoi7/kernel/image.itb
10071 09:58:36.263016
10072 09:58:36.263085 Sending tftp read request... done.
10073 09:58:36.266444
10074 09:58:36.266539 Waiting for the transfer...
10075 09:58:36.266625
10076 09:58:36.521033 00000000 ################################################################
10077 09:58:36.521196
10078 09:58:36.776488 00080000 ################################################################
10079 09:58:36.776715
10080 09:58:37.027997 00100000 ################################################################
10081 09:58:37.028181
10082 09:58:37.280654 00180000 ################################################################
10083 09:58:37.280837
10084 09:58:37.528573 00200000 ################################################################
10085 09:58:37.528766
10086 09:58:37.775884 00280000 ################################################################
10087 09:58:37.776033
10088 09:58:38.024860 00300000 ################################################################
10089 09:58:38.025015
10090 09:58:38.272937 00380000 ################################################################
10091 09:58:38.273109
10092 09:58:38.520627 00400000 ################################################################
10093 09:58:38.520805
10094 09:58:38.772120 00480000 ################################################################
10095 09:58:38.772269
10096 09:58:39.019890 00500000 ################################################################
10097 09:58:39.020042
10098 09:58:39.275052 00580000 ################################################################
10099 09:58:39.275204
10100 09:58:39.528636 00600000 ################################################################
10101 09:58:39.528810
10102 09:58:39.782625 00680000 ################################################################
10103 09:58:39.782777
10104 09:58:40.031555 00700000 ################################################################
10105 09:58:40.031709
10106 09:58:40.282308 00780000 ################################################################
10107 09:58:40.282477
10108 09:58:40.532153 00800000 ################################################################
10109 09:58:40.532291
10110 09:58:40.783130 00880000 ################################################################
10111 09:58:40.783291
10112 09:58:41.033875 00900000 ################################################################
10113 09:58:41.034049
10114 09:58:41.280803 00980000 ################################################################
10115 09:58:41.280957
10116 09:58:41.529943 00a00000 ################################################################
10117 09:58:41.530125
10118 09:58:41.780740 00a80000 ################################################################
10119 09:58:41.780894
10120 09:58:42.030860 00b00000 ################################################################
10121 09:58:42.031014
10122 09:58:42.282401 00b80000 ################################################################
10123 09:58:42.282548
10124 09:58:42.536366 00c00000 ################################################################
10125 09:58:42.536508
10126 09:58:42.786392 00c80000 ################################################################
10127 09:58:42.786563
10128 09:58:43.035516 00d00000 ################################################################
10129 09:58:43.035651
10130 09:58:43.286949 00d80000 ################################################################
10131 09:58:43.287088
10132 09:58:43.537299 00e00000 ################################################################
10133 09:58:43.537463
10134 09:58:43.787820 00e80000 ################################################################
10135 09:58:43.787959
10136 09:58:44.038013 00f00000 ################################################################
10137 09:58:44.038178
10138 09:58:44.291135 00f80000 ################################################################
10139 09:58:44.291275
10140 09:58:44.542179 01000000 ################################################################
10141 09:58:44.542344
10142 09:58:44.795483 01080000 ################################################################
10143 09:58:44.795650
10144 09:58:45.047860 01100000 ################################################################
10145 09:58:45.048023
10146 09:58:45.301193 01180000 ################################################################
10147 09:58:45.301339
10148 09:58:45.553119 01200000 ################################################################
10149 09:58:45.553258
10150 09:58:45.807555 01280000 ################################################################
10151 09:58:45.807728
10152 09:58:46.058171 01300000 ################################################################
10153 09:58:46.058316
10154 09:58:46.307075 01380000 ################################################################
10155 09:58:46.307218
10156 09:58:46.558927 01400000 ################################################################
10157 09:58:46.559112
10158 09:58:46.810751 01480000 ################################################################
10159 09:58:46.810890
10160 09:58:47.061878 01500000 ################################################################
10161 09:58:47.062029
10162 09:58:47.324640 01580000 ################################################################
10163 09:58:47.324804
10164 09:58:47.575301 01600000 ################################################################
10165 09:58:47.575433
10166 09:58:47.826498 01680000 ################################################################
10167 09:58:47.826634
10168 09:58:48.075941 01700000 ################################################################
10169 09:58:48.076086
10170 09:58:48.342759 01780000 ################################################################
10171 09:58:48.342899
10172 09:58:48.592864 01800000 ################################################################
10173 09:58:48.593004
10174 09:58:48.865163 01880000 ################################################################
10175 09:58:48.865299
10176 09:58:49.130178 01900000 ################################################################
10177 09:58:49.130317
10178 09:58:49.392196 01980000 ################################################################
10179 09:58:49.392337
10180 09:58:49.647891 01a00000 ################################################################
10181 09:58:49.648064
10182 09:58:49.914375 01a80000 ################################################################
10183 09:58:49.914537
10184 09:58:50.162848 01b00000 ################################################################
10185 09:58:50.162981
10186 09:58:50.412801 01b80000 ################################################################
10187 09:58:50.412941
10188 09:58:50.661161 01c00000 ################################################################
10189 09:58:50.661297
10190 09:58:50.905512 01c80000 ################################################################
10191 09:58:50.905648
10192 09:58:51.153150 01d00000 ################################################################
10193 09:58:51.153284
10194 09:58:51.403979 01d80000 ################################################################
10195 09:58:51.404121
10196 09:58:51.655336 01e00000 ################################################################
10197 09:58:51.655467
10198 09:58:51.903556 01e80000 ################################################################
10199 09:58:51.903690
10200 09:58:52.150901 01f00000 ################################################################
10201 09:58:52.151041
10202 09:58:52.397300 01f80000 ################################################################
10203 09:58:52.397463
10204 09:58:52.643114 02000000 ################################################################
10205 09:58:52.643286
10206 09:58:52.890502 02080000 ################################################################
10207 09:58:52.890652
10208 09:58:53.140286 02100000 ################################################################
10209 09:58:53.140455
10210 09:58:53.389758 02180000 ################################################################
10211 09:58:53.389921
10212 09:58:53.632997 02200000 ################################################################
10213 09:58:53.633171
10214 09:58:53.882439 02280000 ################################################################
10215 09:58:53.882604
10216 09:58:54.130884 02300000 ################################################################
10217 09:58:54.131136
10218 09:58:54.379606 02380000 ################################################################
10219 09:58:54.379762
10220 09:58:54.626058 02400000 ################################################################
10221 09:58:54.626229
10222 09:58:54.886133 02480000 ################################################################
10223 09:58:54.886297
10224 09:58:55.130357 02500000 ################################################################
10225 09:58:55.130518
10226 09:58:55.385923 02580000 ################################################################
10227 09:58:55.386102
10228 09:58:55.632829 02600000 ################################################################
10229 09:58:55.632975
10230 09:58:55.880608 02680000 ################################################################
10231 09:58:55.880749
10232 09:58:56.131901 02700000 ################################################################
10233 09:58:56.132033
10234 09:58:56.375046 02780000 ################################################################
10235 09:58:56.375194
10236 09:58:56.623099 02800000 ################################################################
10237 09:58:56.623240
10238 09:58:56.870015 02880000 ################################################################
10239 09:58:56.870153
10240 09:58:57.124285 02900000 ################################################################
10241 09:58:57.124429
10242 09:58:57.375286 02980000 ################################################################
10243 09:58:57.375438
10244 09:58:57.624176 02a00000 ################################################################
10245 09:58:57.624315
10246 09:58:57.871845 02a80000 ################################################################
10247 09:58:57.871983
10248 09:58:58.119789 02b00000 ################################################################
10249 09:58:58.119927
10250 09:58:58.367614 02b80000 ################################################################
10251 09:58:58.367761
10252 09:58:58.618279 02c00000 ################################################################
10253 09:58:58.618457
10254 09:58:58.865894 02c80000 ################################################################
10255 09:58:58.866056
10256 09:58:59.114016 02d00000 ################################################################
10257 09:58:59.114178
10258 09:58:59.370422 02d80000 ################################################################
10259 09:58:59.370598
10260 09:58:59.625398 02e00000 ################################################################
10261 09:58:59.625567
10262 09:58:59.882259 02e80000 ################################################################
10263 09:58:59.882406
10264 09:59:00.133743 02f00000 ################################################################
10265 09:59:00.133910
10266 09:59:00.384244 02f80000 ################################################################
10267 09:59:00.384379
10268 09:59:00.640958 03000000 ################################################################
10269 09:59:00.641139
10270 09:59:00.884908 03080000 ################################################################
10271 09:59:00.885046
10272 09:59:01.134895 03100000 ################################################################
10273 09:59:01.135034
10274 09:59:01.380116 03180000 ################################################################
10275 09:59:01.380254
10276 09:59:01.646153 03200000 ################################################################
10277 09:59:01.646292
10278 09:59:01.900014 03280000 ################################################################
10279 09:59:01.900196
10280 09:59:02.155617 03300000 ################################################################
10281 09:59:02.155756
10282 09:59:02.402323 03380000 ################################################################
10283 09:59:02.402506
10284 09:59:02.656039 03400000 ################################################################
10285 09:59:02.656179
10286 09:59:02.921693 03480000 ################################################################
10287 09:59:02.921828
10288 09:59:03.180936 03500000 ################################################################
10289 09:59:03.181095
10290 09:59:03.445332 03580000 ################################################################
10291 09:59:03.445504
10292 09:59:03.694341 03600000 ################################################################
10293 09:59:03.694523
10294 09:59:03.952731 03680000 ################################################################
10295 09:59:03.952869
10296 09:59:04.205464 03700000 ################################################################
10297 09:59:04.205627
10298 09:59:04.409638 03780000 ###################################################### done.
10299 09:59:04.409796
10300 09:59:04.412701 The bootfile was 58634334 bytes long.
10301 09:59:04.412788
10302 09:59:04.416179 Sending tftp read request... done.
10303 09:59:04.416263
10304 09:59:04.419372 Waiting for the transfer...
10305 09:59:04.419520
10306 09:59:04.419634 00000000 # done.
10307 09:59:04.419698
10308 09:59:04.429476 Command line loaded dynamically from TFTP file: 12073283/tftp-deploy-xg3kmoi7/kernel/cmdline
10309 09:59:04.429564
10310 09:59:04.442772 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10311 09:59:04.442863
10312 09:59:04.442930 Loading FIT.
10313 09:59:04.442993
10314 09:59:04.445818 Image ramdisk-1 has 47537480 bytes.
10315 09:59:04.445902
10316 09:59:04.449155 Image fdt-1 has 47278 bytes.
10317 09:59:04.449241
10318 09:59:04.452521 Image kernel-1 has 11047542 bytes.
10319 09:59:04.452606
10320 09:59:04.462456 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10321 09:59:04.462559
10322 09:59:04.478915 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10323 09:59:04.479006
10324 09:59:04.485761 Choosing best match conf-1 for compat google,spherion-rev2.
10325 09:59:04.485847
10326 09:59:04.493427 Connected to device vid:did:rid of 1ae0:0028:00
10327 09:59:04.501511
10328 09:59:04.504547 tpm_get_response: command 0x17b, return code 0x0
10329 09:59:04.504632
10330 09:59:04.508028 ec_init: CrosEC protocol v3 supported (256, 248)
10331 09:59:04.511788
10332 09:59:04.515366 tpm_cleanup: add release locality here.
10333 09:59:04.515451
10334 09:59:04.515516 Shutting down all USB controllers.
10335 09:59:04.515594
10336 09:59:04.518817 Removing current net device
10337 09:59:04.518901
10338 09:59:04.525637 Exiting depthcharge with code 4 at timestamp: 63910489
10339 09:59:04.525721
10340 09:59:04.528491 LZMA decompressing kernel-1 to 0x821a6718
10341 09:59:04.528576
10342 09:59:04.531615 LZMA decompressing kernel-1 to 0x40000000
10343 09:59:05.920366
10344 09:59:05.920501 jumping to kernel
10345 09:59:05.921015 end: 2.2.4 bootloader-commands (duration 00:00:36) [common]
10346 09:59:05.921112 start: 2.2.5 auto-login-action (timeout 00:03:49) [common]
10347 09:59:05.921188 Setting prompt string to ['Linux version [0-9]']
10348 09:59:05.921257 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10349 09:59:05.921326 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10350 09:59:06.002845
10351 09:59:06.006174 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10352 09:59:06.009935 start: 2.2.5.1 login-action (timeout 00:03:49) [common]
10353 09:59:06.010027 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10354 09:59:06.010100 Setting prompt string to []
10355 09:59:06.010183 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10356 09:59:06.010260 Using line separator: #'\n'#
10357 09:59:06.010321 No login prompt set.
10358 09:59:06.010388 Parsing kernel messages
10359 09:59:06.010478 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10360 09:59:06.010580 [login-action] Waiting for messages, (timeout 00:03:49)
10361 09:59:06.029586 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j22848-arm64-gcc-10-defconfig-arm64-chromebook-6q8mw) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Nov 24 09:44:51 UTC 2023
10362 09:59:06.033014 [ 0.000000] random: crng init done
10363 09:59:06.036161 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10364 09:59:06.039510 [ 0.000000] efi: UEFI not found.
10365 09:59:06.049326 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10366 09:59:06.056286 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10367 09:59:06.065781 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10368 09:59:06.075929 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10369 09:59:06.082547 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10370 09:59:06.086059 [ 0.000000] printk: bootconsole [mtk8250] enabled
10371 09:59:06.094739 [ 0.000000] NUMA: No NUMA configuration found
10372 09:59:06.101329 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10373 09:59:06.108006 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10374 09:59:06.108105 [ 0.000000] Zone ranges:
10375 09:59:06.114759 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10376 09:59:06.117846 [ 0.000000] DMA32 empty
10377 09:59:06.124589 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10378 09:59:06.128195 [ 0.000000] Movable zone start for each node
10379 09:59:06.131112 [ 0.000000] Early memory node ranges
10380 09:59:06.138115 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10381 09:59:06.144459 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10382 09:59:06.151156 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10383 09:59:06.157712 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10384 09:59:06.164124 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10385 09:59:06.170737 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10386 09:59:06.227160 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10387 09:59:06.233466 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10388 09:59:06.240367 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10389 09:59:06.243681 [ 0.000000] psci: probing for conduit method from DT.
10390 09:59:06.249973 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10391 09:59:06.253939 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10392 09:59:06.260025 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10393 09:59:06.263376 [ 0.000000] psci: SMC Calling Convention v1.2
10394 09:59:06.269994 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10395 09:59:06.273489 [ 0.000000] Detected VIPT I-cache on CPU0
10396 09:59:06.280144 [ 0.000000] CPU features: detected: GIC system register CPU interface
10397 09:59:06.286664 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10398 09:59:06.293368 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10399 09:59:06.299968 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10400 09:59:06.306671 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10401 09:59:06.313192 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10402 09:59:06.319884 [ 0.000000] alternatives: applying boot alternatives
10403 09:59:06.323380 [ 0.000000] Fallback order for Node 0: 0
10404 09:59:06.333183 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10405 09:59:06.333271 [ 0.000000] Policy zone: Normal
10406 09:59:06.349452 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10407 09:59:06.359306 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10408 09:59:06.371339 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10409 09:59:06.381291 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10410 09:59:06.387996 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10411 09:59:06.391507 <6>[ 0.000000] software IO TLB: area num 8.
10412 09:59:06.447015 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10413 09:59:06.596443 <6>[ 0.000000] Memory: 7923196K/8385536K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 429572K reserved, 32768K cma-reserved)
10414 09:59:06.602639 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10415 09:59:06.609429 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10416 09:59:06.613035 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10417 09:59:06.619767 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10418 09:59:06.626255 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10419 09:59:06.629309 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10420 09:59:06.639525 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10421 09:59:06.646214 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10422 09:59:06.652916 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10423 09:59:06.659509 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10424 09:59:06.662625 <6>[ 0.000000] GICv3: 608 SPIs implemented
10425 09:59:06.665965 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10426 09:59:06.672649 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10427 09:59:06.676025 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10428 09:59:06.682674 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10429 09:59:06.695743 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10430 09:59:06.705886 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10431 09:59:06.715823 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10432 09:59:06.722883 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10433 09:59:06.736220 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10434 09:59:06.742569 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10435 09:59:06.749345 <6>[ 0.009235] Console: colour dummy device 80x25
10436 09:59:06.759208 <6>[ 0.013961] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10437 09:59:06.766029 <6>[ 0.024468] pid_max: default: 32768 minimum: 301
10438 09:59:06.769264 <6>[ 0.029371] LSM: Security Framework initializing
10439 09:59:06.776174 <6>[ 0.034307] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10440 09:59:06.785915 <6>[ 0.042120] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10441 09:59:06.792604 <6>[ 0.051528] cblist_init_generic: Setting adjustable number of callback queues.
10442 09:59:06.799209 <6>[ 0.058970] cblist_init_generic: Setting shift to 3 and lim to 1.
10443 09:59:06.809070 <6>[ 0.065308] cblist_init_generic: Setting adjustable number of callback queues.
10444 09:59:06.815669 <6>[ 0.072736] cblist_init_generic: Setting shift to 3 and lim to 1.
10445 09:59:06.819153 <6>[ 0.079136] rcu: Hierarchical SRCU implementation.
10446 09:59:06.825802 <6>[ 0.084150] rcu: Max phase no-delay instances is 1000.
10447 09:59:06.832503 <6>[ 0.091177] EFI services will not be available.
10448 09:59:06.835566 <6>[ 0.096129] smp: Bringing up secondary CPUs ...
10449 09:59:06.843625 <6>[ 0.101203] Detected VIPT I-cache on CPU1
10450 09:59:06.850313 <6>[ 0.101273] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10451 09:59:06.856920 <6>[ 0.101305] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10452 09:59:06.860392 <6>[ 0.101643] Detected VIPT I-cache on CPU2
10453 09:59:06.866642 <6>[ 0.101695] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10454 09:59:06.876788 <6>[ 0.101711] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10455 09:59:06.880180 <6>[ 0.101974] Detected VIPT I-cache on CPU3
10456 09:59:06.886925 <6>[ 0.102020] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10457 09:59:06.893384 <6>[ 0.102034] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10458 09:59:06.896802 <6>[ 0.102335] CPU features: detected: Spectre-v4
10459 09:59:06.903784 <6>[ 0.102342] CPU features: detected: Spectre-BHB
10460 09:59:06.906405 <6>[ 0.102346] Detected PIPT I-cache on CPU4
10461 09:59:06.913269 <6>[ 0.102402] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10462 09:59:06.919936 <6>[ 0.102419] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10463 09:59:06.926621 <6>[ 0.102711] Detected PIPT I-cache on CPU5
10464 09:59:06.933287 <6>[ 0.102774] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10465 09:59:06.939556 <6>[ 0.102790] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10466 09:59:06.943120 <6>[ 0.103072] Detected PIPT I-cache on CPU6
10467 09:59:06.949286 <6>[ 0.103136] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10468 09:59:06.955978 <6>[ 0.103152] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10469 09:59:06.963106 <6>[ 0.103444] Detected PIPT I-cache on CPU7
10470 09:59:06.969531 <6>[ 0.103509] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10471 09:59:06.976284 <6>[ 0.103526] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10472 09:59:06.979596 <6>[ 0.103573] smp: Brought up 1 node, 8 CPUs
10473 09:59:06.985637 <6>[ 0.244948] SMP: Total of 8 processors activated.
10474 09:59:06.989237 <6>[ 0.249869] CPU features: detected: 32-bit EL0 Support
10475 09:59:06.999353 <6>[ 0.255232] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10476 09:59:07.005941 <6>[ 0.264087] CPU features: detected: Common not Private translations
10477 09:59:07.012170 <6>[ 0.270602] CPU features: detected: CRC32 instructions
10478 09:59:07.015632 <6>[ 0.275953] CPU features: detected: RCpc load-acquire (LDAPR)
10479 09:59:07.022576 <6>[ 0.281950] CPU features: detected: LSE atomic instructions
10480 09:59:07.029001 <6>[ 0.287767] CPU features: detected: Privileged Access Never
10481 09:59:07.036087 <6>[ 0.293546] CPU features: detected: RAS Extension Support
10482 09:59:07.042305 <6>[ 0.299189] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10483 09:59:07.045874 <6>[ 0.306403] CPU: All CPU(s) started at EL2
10484 09:59:07.052582 <6>[ 0.310746] alternatives: applying system-wide alternatives
10485 09:59:07.061388 <6>[ 0.321448] devtmpfs: initialized
10486 09:59:07.073996 <6>[ 0.330442] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10487 09:59:07.083783 <6>[ 0.340403] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10488 09:59:07.090317 <6>[ 0.348648] pinctrl core: initialized pinctrl subsystem
10489 09:59:07.093942 <6>[ 0.355317] DMI not present or invalid.
10490 09:59:07.100604 <6>[ 0.359733] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10491 09:59:07.110356 <6>[ 0.366627] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10492 09:59:07.117041 <6>[ 0.374208] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10493 09:59:07.126864 <6>[ 0.382437] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10494 09:59:07.130191 <6>[ 0.390678] audit: initializing netlink subsys (disabled)
10495 09:59:07.139650 <5>[ 0.396371] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10496 09:59:07.146711 <6>[ 0.397073] thermal_sys: Registered thermal governor 'step_wise'
10497 09:59:07.152820 <6>[ 0.404338] thermal_sys: Registered thermal governor 'power_allocator'
10498 09:59:07.156594 <6>[ 0.410597] cpuidle: using governor menu
10499 09:59:07.163302 <6>[ 0.421560] NET: Registered PF_QIPCRTR protocol family
10500 09:59:07.169334 <6>[ 0.427045] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10501 09:59:07.176124 <6>[ 0.434149] ASID allocator initialised with 32768 entries
10502 09:59:07.179192 <6>[ 0.440716] Serial: AMBA PL011 UART driver
10503 09:59:07.189477 <4>[ 0.449541] Trying to register duplicate clock ID: 134
10504 09:59:07.245849 <6>[ 0.509228] KASLR enabled
10505 09:59:07.260298 <6>[ 0.516916] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10506 09:59:07.266915 <6>[ 0.523929] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10507 09:59:07.273349 <6>[ 0.530417] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10508 09:59:07.280168 <6>[ 0.537421] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10509 09:59:07.286839 <6>[ 0.543908] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10510 09:59:07.293344 <6>[ 0.550913] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10511 09:59:07.300266 <6>[ 0.557402] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10512 09:59:07.306529 <6>[ 0.564408] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10513 09:59:07.309990 <6>[ 0.571865] ACPI: Interpreter disabled.
10514 09:59:07.318548 <6>[ 0.578285] iommu: Default domain type: Translated
10515 09:59:07.324843 <6>[ 0.583434] iommu: DMA domain TLB invalidation policy: strict mode
10516 09:59:07.328221 <5>[ 0.590090] SCSI subsystem initialized
10517 09:59:07.335081 <6>[ 0.594336] usbcore: registered new interface driver usbfs
10518 09:59:07.341418 <6>[ 0.600066] usbcore: registered new interface driver hub
10519 09:59:07.344815 <6>[ 0.605620] usbcore: registered new device driver usb
10520 09:59:07.351523 <6>[ 0.611746] pps_core: LinuxPPS API ver. 1 registered
10521 09:59:07.361450 <6>[ 0.616940] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10522 09:59:07.364962 <6>[ 0.626285] PTP clock support registered
10523 09:59:07.368105 <6>[ 0.630525] EDAC MC: Ver: 3.0.0
10524 09:59:07.375880 <6>[ 0.635728] FPGA manager framework
10525 09:59:07.382621 <6>[ 0.639405] Advanced Linux Sound Architecture Driver Initialized.
10526 09:59:07.385774 <6>[ 0.646171] vgaarb: loaded
10527 09:59:07.392367 <6>[ 0.649329] clocksource: Switched to clocksource arch_sys_counter
10528 09:59:07.395270 <5>[ 0.655775] VFS: Disk quotas dquot_6.6.0
10529 09:59:07.402612 <6>[ 0.659963] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10530 09:59:07.405486 <6>[ 0.667152] pnp: PnP ACPI: disabled
10531 09:59:07.413704 <6>[ 0.673808] NET: Registered PF_INET protocol family
10532 09:59:07.423421 <6>[ 0.679393] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10533 09:59:07.434925 <6>[ 0.691691] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10534 09:59:07.444986 <6>[ 0.700505] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10535 09:59:07.451535 <6>[ 0.708470] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10536 09:59:07.458315 <6>[ 0.717170] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10537 09:59:07.470195 <6>[ 0.726884] TCP: Hash tables configured (established 65536 bind 65536)
10538 09:59:07.476806 <6>[ 0.733750] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10539 09:59:07.483336 <6>[ 0.740946] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10540 09:59:07.490014 <6>[ 0.748647] NET: Registered PF_UNIX/PF_LOCAL protocol family
10541 09:59:07.496351 <6>[ 0.754818] RPC: Registered named UNIX socket transport module.
10542 09:59:07.499908 <6>[ 0.760972] RPC: Registered udp transport module.
10543 09:59:07.506745 <6>[ 0.765906] RPC: Registered tcp transport module.
10544 09:59:07.513053 <6>[ 0.770837] RPC: Registered tcp NFSv4.1 backchannel transport module.
10545 09:59:07.516717 <6>[ 0.777502] PCI: CLS 0 bytes, default 64
10546 09:59:07.519747 <6>[ 0.781899] Unpacking initramfs...
10547 09:59:07.544673 <6>[ 0.801450] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10548 09:59:07.554406 <6>[ 0.810097] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10549 09:59:07.558011 <6>[ 0.818980] kvm [1]: IPA Size Limit: 40 bits
10550 09:59:07.564460 <6>[ 0.823512] kvm [1]: GICv3: no GICV resource entry
10551 09:59:07.567761 <6>[ 0.828534] kvm [1]: disabling GICv2 emulation
10552 09:59:07.574511 <6>[ 0.833226] kvm [1]: GIC system register CPU interface enabled
10553 09:59:07.577698 <6>[ 0.839399] kvm [1]: vgic interrupt IRQ18
10554 09:59:07.584622 <6>[ 0.843763] kvm [1]: VHE mode initialized successfully
10555 09:59:07.591262 <5>[ 0.850381] Initialise system trusted keyrings
10556 09:59:07.597537 <6>[ 0.855212] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10557 09:59:07.605063 <6>[ 0.865209] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10558 09:59:07.611817 <5>[ 0.871590] NFS: Registering the id_resolver key type
10559 09:59:07.614795 <5>[ 0.876888] Key type id_resolver registered
10560 09:59:07.621637 <5>[ 0.881302] Key type id_legacy registered
10561 09:59:07.628210 <6>[ 0.885579] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10562 09:59:07.634958 <6>[ 0.892501] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10563 09:59:07.641477 <6>[ 0.900241] 9p: Installing v9fs 9p2000 file system support
10564 09:59:07.678149 <5>[ 0.938112] Key type asymmetric registered
10565 09:59:07.681579 <5>[ 0.942444] Asymmetric key parser 'x509' registered
10566 09:59:07.691639 <6>[ 0.947585] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10567 09:59:07.694754 <6>[ 0.955197] io scheduler mq-deadline registered
10568 09:59:07.698259 <6>[ 0.959959] io scheduler kyber registered
10569 09:59:07.716960 <6>[ 0.977145] EINJ: ACPI disabled.
10570 09:59:07.749783 <4>[ 1.002997] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10571 09:59:07.759359 <4>[ 1.013643] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10572 09:59:07.774604 <6>[ 1.034509] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10573 09:59:07.782206 <6>[ 1.042466] printk: console [ttyS0] disabled
10574 09:59:07.810299 <6>[ 1.067111] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10575 09:59:07.817094 <6>[ 1.076586] printk: console [ttyS0] enabled
10576 09:59:07.820382 <6>[ 1.076586] printk: console [ttyS0] enabled
10577 09:59:07.826906 <6>[ 1.085479] printk: bootconsole [mtk8250] disabled
10578 09:59:07.830287 <6>[ 1.085479] printk: bootconsole [mtk8250] disabled
10579 09:59:07.836727 <6>[ 1.096747] SuperH (H)SCI(F) driver initialized
10580 09:59:07.840248 <6>[ 1.102009] msm_serial: driver initialized
10581 09:59:07.854306 <6>[ 1.111005] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10582 09:59:07.864336 <6>[ 1.119550] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10583 09:59:07.871080 <6>[ 1.128092] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10584 09:59:07.881101 <6>[ 1.136720] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10585 09:59:07.890908 <6>[ 1.145428] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10586 09:59:07.897520 <6>[ 1.154148] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10587 09:59:07.907270 <6>[ 1.162689] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10588 09:59:07.913974 <6>[ 1.171516] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10589 09:59:07.923826 <6>[ 1.180061] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10590 09:59:07.935480 <6>[ 1.195640] loop: module loaded
10591 09:59:07.941976 <6>[ 1.201650] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10592 09:59:07.964750 <4>[ 1.225014] mtk-pmic-keys: Failed to locate of_node [id: -1]
10593 09:59:07.971899 <6>[ 1.231910] megasas: 07.719.03.00-rc1
10594 09:59:07.981384 <6>[ 1.241473] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10595 09:59:07.988722 <6>[ 1.248700] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10596 09:59:08.005879 <6>[ 1.265419] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10597 09:59:08.061673 <6>[ 1.315336] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10598 09:59:09.546876 <6>[ 2.807212] Freeing initrd memory: 46420K
10599 09:59:09.557225 <6>[ 2.817594] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10600 09:59:09.568408 <6>[ 2.828544] tun: Universal TUN/TAP device driver, 1.6
10601 09:59:09.571537 <6>[ 2.834617] thunder_xcv, ver 1.0
10602 09:59:09.575163 <6>[ 2.838119] thunder_bgx, ver 1.0
10603 09:59:09.578055 <6>[ 2.841611] nicpf, ver 1.0
10604 09:59:09.588871 <6>[ 2.845626] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10605 09:59:09.592186 <6>[ 2.853101] hns3: Copyright (c) 2017 Huawei Corporation.
10606 09:59:09.598747 <6>[ 2.858689] hclge is initializing
10607 09:59:09.602122 <6>[ 2.862268] e1000: Intel(R) PRO/1000 Network Driver
10608 09:59:09.608409 <6>[ 2.867396] e1000: Copyright (c) 1999-2006 Intel Corporation.
10609 09:59:09.611768 <6>[ 2.873410] e1000e: Intel(R) PRO/1000 Network Driver
10610 09:59:09.618443 <6>[ 2.878626] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10611 09:59:09.625068 <6>[ 2.884814] igb: Intel(R) Gigabit Ethernet Network Driver
10612 09:59:09.631699 <6>[ 2.890465] igb: Copyright (c) 2007-2014 Intel Corporation.
10613 09:59:09.638316 <6>[ 2.896300] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10614 09:59:09.645088 <6>[ 2.902818] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10615 09:59:09.648450 <6>[ 2.909286] sky2: driver version 1.30
10616 09:59:09.655096 <6>[ 2.914287] VFIO - User Level meta-driver version: 0.3
10617 09:59:09.662255 <6>[ 2.922520] usbcore: registered new interface driver usb-storage
10618 09:59:09.668977 <6>[ 2.928965] usbcore: registered new device driver onboard-usb-hub
10619 09:59:09.678251 <6>[ 2.938112] mt6397-rtc mt6359-rtc: registered as rtc0
10620 09:59:09.687929 <6>[ 2.943598] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-24T09:58:37 UTC (1700819917)
10621 09:59:09.691452 <6>[ 2.953196] i2c_dev: i2c /dev entries driver
10622 09:59:09.707966 <6>[ 2.964952] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10623 09:59:09.727631 <6>[ 2.987910] cpu cpu0: EM: created perf domain
10624 09:59:09.730921 <6>[ 2.992853] cpu cpu4: EM: created perf domain
10625 09:59:09.738184 <6>[ 2.998445] sdhci: Secure Digital Host Controller Interface driver
10626 09:59:09.744831 <6>[ 3.004876] sdhci: Copyright(c) Pierre Ossman
10627 09:59:09.751385 <6>[ 3.009834] Synopsys Designware Multimedia Card Interface Driver
10628 09:59:09.757855 <6>[ 3.016473] sdhci-pltfm: SDHCI platform and OF driver helper
10629 09:59:09.761993 <6>[ 3.016609] mmc0: CQHCI version 5.10
10630 09:59:09.767855 <6>[ 3.026493] ledtrig-cpu: registered to indicate activity on CPUs
10631 09:59:09.774422 <6>[ 3.033557] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10632 09:59:09.781554 <6>[ 3.040609] usbcore: registered new interface driver usbhid
10633 09:59:09.784711 <6>[ 3.046434] usbhid: USB HID core driver
10634 09:59:09.791116 <6>[ 3.050630] spi_master spi0: will run message pump with realtime priority
10635 09:59:09.840564 <6>[ 3.094095] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10636 09:59:09.859446 <6>[ 3.109978] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10637 09:59:09.863408 <6>[ 3.123556] mmc0: Command Queue Engine enabled
10638 09:59:09.870262 <6>[ 3.128314] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10639 09:59:09.876929 <6>[ 3.135442] cros-ec-spi spi0.0: Chrome EC device registered
10640 09:59:09.879929 <6>[ 3.135683] mmcblk0: mmc0:0001 DA4128 116 GiB
10641 09:59:09.892090 <6>[ 3.152565] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10642 09:59:09.900130 <6>[ 3.160267] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10643 09:59:09.906523 <6>[ 3.166335] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10644 09:59:09.912975 <6>[ 3.172304] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10645 09:59:09.923303 <6>[ 3.177502] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10646 09:59:09.929927 <6>[ 3.189453] NET: Registered PF_PACKET protocol family
10647 09:59:09.933274 <6>[ 3.194856] 9pnet: Installing 9P2000 support
10648 09:59:09.939679 <5>[ 3.199422] Key type dns_resolver registered
10649 09:59:09.943302 <6>[ 3.204474] registered taskstats version 1
10650 09:59:09.949460 <5>[ 3.208891] Loading compiled-in X.509 certificates
10651 09:59:09.977882 <4>[ 3.231358] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10652 09:59:09.987468 <4>[ 3.242147] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10653 09:59:09.994700 <3>[ 3.252760] debugfs: File 'uA_load' in directory '/' already present!
10654 09:59:10.000892 <3>[ 3.259473] debugfs: File 'min_uV' in directory '/' already present!
10655 09:59:10.007723 <3>[ 3.266086] debugfs: File 'max_uV' in directory '/' already present!
10656 09:59:10.014353 <3>[ 3.272698] debugfs: File 'constraint_flags' in directory '/' already present!
10657 09:59:10.026493 <3>[ 3.283499] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10658 09:59:10.036251 <6>[ 3.296700] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10659 09:59:10.043580 <6>[ 3.303600] xhci-mtk 11200000.usb: xHCI Host Controller
10660 09:59:10.050107 <6>[ 3.309109] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10661 09:59:10.060160 <6>[ 3.316942] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10662 09:59:10.066894 <6>[ 3.326367] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10663 09:59:10.073688 <6>[ 3.332411] xhci-mtk 11200000.usb: xHCI Host Controller
10664 09:59:10.080107 <6>[ 3.337886] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10665 09:59:10.086839 <6>[ 3.345533] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10666 09:59:10.093552 <6>[ 3.353198] hub 1-0:1.0: USB hub found
10667 09:59:10.096603 <6>[ 3.357209] hub 1-0:1.0: 1 port detected
10668 09:59:10.102837 <6>[ 3.361480] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10669 09:59:10.109878 <6>[ 3.370144] hub 2-0:1.0: USB hub found
10670 09:59:10.113251 <6>[ 3.374160] hub 2-0:1.0: 1 port detected
10671 09:59:10.122632 <6>[ 3.382728] mtk-msdc 11f70000.mmc: Got CD GPIO
10672 09:59:10.132271 <6>[ 3.388376] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10673 09:59:10.138789 <6>[ 3.396410] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10674 09:59:10.148996 <4>[ 3.404308] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10675 09:59:10.155135 <6>[ 3.413833] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10676 09:59:10.165419 <6>[ 3.421910] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10677 09:59:10.172120 <6>[ 3.429931] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10678 09:59:10.181564 <6>[ 3.437850] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10679 09:59:10.188299 <6>[ 3.445667] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10680 09:59:10.198161 <6>[ 3.453485] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10681 09:59:10.208352 <6>[ 3.463939] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10682 09:59:10.214803 <6>[ 3.472301] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10683 09:59:10.224986 <6>[ 3.480644] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10684 09:59:10.231515 <6>[ 3.488989] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10685 09:59:10.241237 <6>[ 3.497328] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10686 09:59:10.248155 <6>[ 3.505668] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10687 09:59:10.258303 <6>[ 3.514009] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10688 09:59:10.264910 <6>[ 3.522347] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10689 09:59:10.274701 <6>[ 3.530685] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10690 09:59:10.281583 <6>[ 3.539024] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10691 09:59:10.291399 <6>[ 3.547363] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10692 09:59:10.297955 <6>[ 3.555714] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10693 09:59:10.307810 <6>[ 3.564054] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10694 09:59:10.314309 <6>[ 3.572393] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10695 09:59:10.324367 <6>[ 3.580731] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10696 09:59:10.330945 <6>[ 3.589537] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10697 09:59:10.337465 <6>[ 3.596680] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10698 09:59:10.344279 <6>[ 3.603445] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10699 09:59:10.350757 <6>[ 3.610201] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10700 09:59:10.357327 <6>[ 3.617130] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10701 09:59:10.367319 <6>[ 3.623973] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10702 09:59:10.377146 <6>[ 3.633101] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10703 09:59:10.387007 <6>[ 3.642219] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10704 09:59:10.397018 <6>[ 3.651512] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10705 09:59:10.406697 <6>[ 3.660986] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10706 09:59:10.413391 <6>[ 3.670455] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10707 09:59:10.423404 <6>[ 3.679577] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10708 09:59:10.433379 <6>[ 3.689045] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10709 09:59:10.443405 <6>[ 3.698166] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10710 09:59:10.453448 <6>[ 3.707460] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10711 09:59:10.463099 <6>[ 3.717620] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10712 09:59:10.472643 <6>[ 3.729230] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10713 09:59:10.528616 <6>[ 3.785602] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10714 09:59:10.683264 <6>[ 3.943397] hub 1-1:1.0: USB hub found
10715 09:59:10.686365 <6>[ 3.947928] hub 1-1:1.0: 4 ports detected
10716 09:59:10.695706 <6>[ 3.955993] hub 1-1:1.0: USB hub found
10717 09:59:10.698719 <6>[ 3.960377] hub 1-1:1.0: 4 ports detected
10718 09:59:10.808914 <6>[ 4.065953] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10719 09:59:10.835458 <6>[ 4.095646] hub 2-1:1.0: USB hub found
10720 09:59:10.838499 <6>[ 4.100156] hub 2-1:1.0: 3 ports detected
10721 09:59:10.848003 <6>[ 4.108437] hub 2-1:1.0: USB hub found
10722 09:59:10.851369 <6>[ 4.112895] hub 2-1:1.0: 3 ports detected
10723 09:59:11.024509 <6>[ 4.281626] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10724 09:59:11.157725 <6>[ 4.418212] hub 1-1.4:1.0: USB hub found
10725 09:59:11.160969 <6>[ 4.422940] hub 1-1.4:1.0: 2 ports detected
10726 09:59:11.171474 <6>[ 4.431824] hub 1-1.4:1.0: USB hub found
10727 09:59:11.175004 <6>[ 4.436483] hub 1-1.4:1.0: 2 ports detected
10728 09:59:11.244891 <6>[ 4.501871] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10729 09:59:11.472374 <6>[ 4.729652] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10730 09:59:11.664249 <6>[ 4.921627] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10731 09:59:22.749959 <6>[ 16.014686] ALSA device list:
10732 09:59:22.756420 <6>[ 16.017982] No soundcards found.
10733 09:59:22.764642 <6>[ 16.026131] Freeing unused kernel memory: 8384K
10734 09:59:22.768284 <6>[ 16.031129] Run /init as init process
10735 09:59:22.821230 <6>[ 16.082824] NET: Registered PF_INET6 protocol family
10736 09:59:22.827708 <6>[ 16.088970] Segment Routing with IPv6
10737 09:59:22.830764 <6>[ 16.092924] In-situ OAM (IOAM) with IPv6
10738 09:59:22.866357 <30>[ 16.108418] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10739 09:59:22.869677 <30>[ 16.132359] systemd[1]: Detected architecture arm64.
10740 09:59:22.873145
10741 09:59:22.876596 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10742 09:59:22.876675
10743 09:59:22.892037 <30>[ 16.153728] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10744 09:59:23.031680 <30>[ 16.289774] systemd[1]: Queued start job for default target Graphical Interface.
10745 09:59:23.061124 <30>[ 16.322575] systemd[1]: Created slice system-getty.slice.
10746 09:59:23.067461 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10747 09:59:23.084643 <30>[ 16.346097] systemd[1]: Created slice system-modprobe.slice.
10748 09:59:23.091417 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10749 09:59:23.109148 <30>[ 16.370160] systemd[1]: Created slice system-serial\x2dgetty.slice.
10750 09:59:23.118267 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10751 09:59:23.132351 <30>[ 16.394205] systemd[1]: Created slice User and Session Slice.
10752 09:59:23.138670 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10753 09:59:23.159675 <30>[ 16.418251] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10754 09:59:23.169726 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10755 09:59:23.188171 <30>[ 16.446189] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10756 09:59:23.194074 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10757 09:59:23.218696 <30>[ 16.474073] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10758 09:59:23.225630 <30>[ 16.486382] systemd[1]: Reached target Local Encrypted Volumes.
10759 09:59:23.232417 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10760 09:59:23.248133 <30>[ 16.510086] systemd[1]: Reached target Paths.
10761 09:59:23.254798 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10762 09:59:23.267706 <30>[ 16.529720] systemd[1]: Reached target Remote File Systems.
10763 09:59:23.274338 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10764 09:59:23.291909 <30>[ 16.553607] systemd[1]: Reached target Slices.
10765 09:59:23.295216 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10766 09:59:23.311825 <30>[ 16.573669] systemd[1]: Reached target Swap.
10767 09:59:23.314919 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10768 09:59:23.335609 <30>[ 16.594181] systemd[1]: Listening on initctl Compatibility Named Pipe.
10769 09:59:23.342129 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10770 09:59:23.348825 <30>[ 16.609508] systemd[1]: Listening on Journal Audit Socket.
10771 09:59:23.355599 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10772 09:59:23.368220 <30>[ 16.630176] systemd[1]: Listening on Journal Socket (/dev/log).
10773 09:59:23.374878 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10774 09:59:23.393024 <30>[ 16.654939] systemd[1]: Listening on Journal Socket.
10775 09:59:23.399749 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10776 09:59:23.415628 <30>[ 16.674424] systemd[1]: Listening on Network Service Netlink Socket.
10777 09:59:23.422598 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10778 09:59:23.437248 <30>[ 16.698917] systemd[1]: Listening on udev Control Socket.
10779 09:59:23.443736 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10780 09:59:23.461149 <30>[ 16.722774] systemd[1]: Listening on udev Kernel Socket.
10781 09:59:23.467788 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10782 09:59:23.520126 <30>[ 16.781861] systemd[1]: Mounting Huge Pages File System...
10783 09:59:23.526343 Mounting [0;1;39mHuge Pages File System[0m...
10784 09:59:23.541543 <30>[ 16.803334] systemd[1]: Mounting POSIX Message Queue File System...
10785 09:59:23.548516 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10786 09:59:23.565631 <30>[ 16.827350] systemd[1]: Mounting Kernel Debug File System...
10787 09:59:23.572164 Mounting [0;1;39mKernel Debug File System[0m...
10788 09:59:23.591307 <30>[ 16.849865] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10789 09:59:23.602854 <30>[ 16.861615] systemd[1]: Starting Create list of static device nodes for the current kernel...
10790 09:59:23.609489 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10791 09:59:23.631679 <30>[ 16.893640] systemd[1]: Starting Load Kernel Module configfs...
10792 09:59:23.638097 Starting [0;1;39mLoad Kernel Module configfs[0m...
10793 09:59:23.656426 <30>[ 16.917882] systemd[1]: Starting Load Kernel Module drm...
10794 09:59:23.662510 Starting [0;1;39mLoad Kernel Module drm[0m...
10795 09:59:23.679491 <30>[ 16.938047] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10796 09:59:23.694880 <30>[ 16.957134] systemd[1]: Starting Journal Service...
10797 09:59:23.701703 Starting [0;1;39mJournal Service[0m...
10798 09:59:23.718597 <30>[ 16.980172] systemd[1]: Starting Load Kernel Modules...
10799 09:59:23.724679 Starting [0;1;39mLoad Kernel Modules[0m...
10800 09:59:23.748517 <30>[ 17.007105] systemd[1]: Starting Remount Root and Kernel File Systems...
10801 09:59:23.755070 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10802 09:59:23.784510 <30>[ 17.046239] systemd[1]: Starting Coldplug All udev Devices...
10803 09:59:23.790815 Starting [0;1;39mColdplug All udev Devices[0m...
10804 09:59:23.806562 <30>[ 17.068617] systemd[1]: Started Journal Service.
10805 09:59:23.813501 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10806 09:59:23.829580 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10807 09:59:23.844846 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10808 09:59:23.860710 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10809 09:59:23.880912 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10810 09:59:23.897655 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10811 09:59:23.923230 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10812 09:59:23.941032 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10813 09:59:23.960730 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10814 09:59:23.976381 See 'systemctl status systemd-remount-fs.service' for details.
10815 09:59:24.025157 Mounting [0;1;39mKernel Configuration File System[0m...
10816 09:59:24.042708 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10817 09:59:24.055617 <46>[ 17.314445] systemd-journald[180]: Received client request to flush runtime journal.
10818 09:59:24.064794 Starting [0;1;39mLoad/Save Random Seed[0m...
10819 09:59:24.083771 Starting [0;1;39mApply Kernel Variables[0m...
10820 09:59:24.108817 Starting [0;1;39mCreate System Users[0m...
10821 09:59:24.131887 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10822 09:59:24.152930 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10823 09:59:24.173120 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10824 09:59:24.190042 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10825 09:59:24.209897 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10826 09:59:24.218222 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10827 09:59:24.264096 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10828 09:59:24.285969 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10829 09:59:24.300030 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10830 09:59:24.315858 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10831 09:59:24.372891 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10832 09:59:24.401066 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10833 09:59:24.424511 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10834 09:59:24.445629 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10835 09:59:24.485031 Starting [0;1;39mNetwork Service[0m...
10836 09:59:24.505353 Starting [0;1;39mNetwork Time Synchronization[0m...
10837 09:59:24.530218 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10838 09:59:24.550944 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10839 09:59:24.640990 Starting [0;1;39mNetwork Name Resolution[0m...
10840 09:59:24.659370 <6>[ 17.918268] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10841 09:59:24.666242 <6>[ 17.926032] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10842 09:59:24.673058 <6>[ 17.928505] usbcore: registered new interface driver r8152
10843 09:59:24.679278 <6>[ 17.928659] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10844 09:59:24.689642 <6>[ 17.934809] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10845 09:59:24.695939 <4>[ 17.943380] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10846 09:59:24.702728 <6>[ 17.944430] remoteproc remoteproc0: scp is available
10847 09:59:24.705896 <6>[ 17.944731] remoteproc remoteproc0: powering up scp
10848 09:59:24.715776 <6>[ 17.944736] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10849 09:59:24.722560 <6>[ 17.944756] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10850 09:59:24.732394 [[0;32m OK [0m] Started [0;<4>[ 17.991092] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10851 09:59:24.735784 1;39mNetwork Time Synchronization[0m.
10852 09:59:24.745928 <3>[ 18.004300] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10853 09:59:24.752377 <3>[ 18.012415] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10854 09:59:24.762187 <3>[ 18.020505] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10855 09:59:24.783847 <3>[ 18.042627] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10856 09:59:24.790364 <3>[ 18.050929] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10857 09:59:24.800088 <3>[ 18.059037] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10858 09:59:24.807264 <3>[ 18.059045] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10859 09:59:24.816891 <3>[ 18.059050] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10860 09:59:24.826752 [[0;32m OK [<3>[ 18.067818] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10861 09:59:24.833507 <6>[ 18.070348] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10862 09:59:24.844173 0m] Finished [0<6>[ 18.070355] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10863 09:59:24.850048 ;1;39mUpdate UTM<6>[ 18.070359] remoteproc remoteproc0: remote processor scp is now up
10864 09:59:24.857145 P about System B<6>[ 18.073210] mc: Linux media interface: v0.10
10865 09:59:24.863623 <6>[ 18.074695] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10866 09:59:24.870238 oot/Shutdown[0m<6>[ 18.074705] pci_bus 0000:00: root bus resource [bus 00-ff]
10867 09:59:24.876977 <6>[ 18.074710] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10868 09:59:24.877086 .
10869 09:59:24.886767 <6>[ 18.074712] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10870 09:59:24.893122 <6>[ 18.074742] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10871 09:59:24.903208 <6>[ 18.074755] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10872 09:59:24.906824 <6>[ 18.074818] pci 0000:00:00.0: supports D1 D2
10873 09:59:24.913390 <6>[ 18.074820] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10874 09:59:24.920129 <6>[ 18.079767] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10875 09:59:24.931012 <3>[ 18.085805] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10876 09:59:24.937207 <6>[ 18.094787] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10877 09:59:24.943858 <3>[ 18.101926] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10878 09:59:24.954352 <3>[ 18.101933] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10879 09:59:24.961759 <6>[ 18.103366] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10880 09:59:24.968655 <3>[ 18.122943] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10881 09:59:24.978771 <6>[ 18.129057] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10882 09:59:24.985384 <3>[ 18.131046] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10883 09:59:24.992095 <6>[ 18.133517] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10884 09:59:25.002039 <6>[ 18.133548] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10885 09:59:25.008728 <6>[ 18.133567] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10886 09:59:25.015305 <6>[ 18.133582] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10887 09:59:25.018752 <6>[ 18.133711] pci 0000:01:00.0: supports D1 D2
10888 09:59:25.028648 <6>[ 18.133713] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10889 09:59:25.038764 <6>[ 18.146815] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10890 09:59:25.045101 <3>[ 18.155517] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10891 09:59:25.051937 <6>[ 18.161175] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10892 09:59:25.061616 <6>[ 18.161219] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10893 09:59:25.068332 <6>[ 18.161223] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10894 09:59:25.075058 <6>[ 18.161233] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10895 09:59:25.085199 <6>[ 18.161246] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10896 09:59:25.092360 <6>[ 18.161259] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10897 09:59:25.098761 <6>[ 18.161271] pci 0000:00:00.0: PCI bridge to [bus 01]
10898 09:59:25.105793 <6>[ 18.161276] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10899 09:59:25.112265 <6>[ 18.161434] videodev: Linux video capture interface: v2.00
10900 09:59:25.118818 <6>[ 18.162925] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10901 09:59:25.126710 <6>[ 18.163006] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10902 09:59:25.136806 <4>[ 18.165189] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10903 09:59:25.140237 <4>[ 18.165189] Fallback method does not support PEC.
10904 09:59:25.147267 <3>[ 18.169182] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10905 09:59:25.157835 <3>[ 18.169193] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10906 09:59:25.164303 <3>[ 18.170071] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10907 09:59:25.171164 <6>[ 18.175197] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10908 09:59:25.177288 <6>[ 18.190077] r8152 2-1.3:1.0: load rtl8153b-2 v1 10/23/19 successfully
10909 09:59:25.184049 <6>[ 18.192609] usbcore: registered new interface driver cdc_ether
10910 09:59:25.194382 <3>[ 18.195071] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10911 09:59:25.197308 <6>[ 18.211793] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10912 09:59:25.207319 <3>[ 18.224961] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 09:59:25.217472 <3>[ 18.245959] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10914 09:59:25.220706 <6>[ 18.254423] Bluetooth: Core ver 2.22
10915 09:59:25.227234 <6>[ 18.254657] usbcore: registered new interface driver r8153_ecm
10916 09:59:25.233718 <6>[ 18.300758] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10917 09:59:25.237052 <6>[ 18.305787] r8152 2-1.3:1.0 eth0: v1.12.13
10918 09:59:25.243848 <6>[ 18.305818] NET: Registered PF_BLUETOOTH protocol family
10919 09:59:25.250209 <6>[ 18.305821] Bluetooth: HCI device and connection manager initialized
10920 09:59:25.253426 <6>[ 18.305849] Bluetooth: HCI socket layer initialized
10921 09:59:25.260262 <6>[ 18.305857] Bluetooth: L2CAP socket layer initialized
10922 09:59:25.263541 <6>[ 18.305886] Bluetooth: SCO socket layer initialized
10923 09:59:25.276852 <6>[ 18.357589] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10924 09:59:25.286673 <6>[ 18.361707] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10925 09:59:25.293497 <6>[ 18.362290] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10926 09:59:25.300181 <5>[ 18.363315] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10927 09:59:25.306820 <6>[ 18.365670] usbcore: registered new interface driver uvcvideo
10928 09:59:25.316447 <3>[ 18.370417] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 09:59:25.323085 <3>[ 18.371581] power_supply sbs-5-000b: driver failed to report `health' property: -6
10930 09:59:25.330073 <6>[ 18.376776] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10931 09:59:25.336451 <6>[ 18.380283] usbcore: registered new interface driver btusb
10932 09:59:25.346265 <4>[ 18.380881] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10933 09:59:25.352849 <3>[ 18.380892] Bluetooth: hci0: Failed to load firmware file (-2)
10934 09:59:25.359451 <3>[ 18.380895] Bluetooth: hci0: Failed to set up firmware (-2)
10935 09:59:25.369563 <4>[ 18.380899] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10936 09:59:25.376123 <6>[ 18.381208] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10937 09:59:25.382874 <5>[ 18.384556] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10938 09:59:25.392343 <3>[ 18.395470] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10939 09:59:25.399158 <3>[ 18.396250] power_supply sbs-5-000b: driver failed to report `voltage_now' property: -6
10940 09:59:25.408894 <3>[ 18.418741] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 09:59:25.422152 [[0;32m OK [0m] Started [0;1;39mNetwork Nam<4>[ 18.678582] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10942 09:59:25.429241 e Resolution[0m<6>[ 18.688809] cfg80211: failed to load regulatory.db
10943 09:59:25.429363 .
10944 09:59:25.439107 <3>[ 18.697233] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10945 09:59:25.449360 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10946 09:59:25.470168 <3>[ 18.728515] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 09:59:25.476469 <6>[ 18.734970] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10948 09:59:25.483125 <6>[ 18.744793] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10949 09:59:25.507291 <6>[ 18.769525] mt7921e 0000:01:00.0: ASIC revision: 79610010
10950 09:59:25.566129 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10951 09:59:25.579373 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10952 09:59:25.596571 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10953 09:59:25.614642 <4>[ 18.869982] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10954 09:59:25.621244 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10955 09:59:25.639946 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10956 09:59:25.655755 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10957 09:59:25.675668 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10958 09:59:25.732750 Starting [0;1;39mLoad/Save Screen …o<4>[ 18.988703] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10959 09:59:25.736151 f leds:white:kbd_backlight[0m...
10960 09:59:25.762179 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10961 09:59:25.780670 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10962 09:59:25.799643 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10963 09:59:25.814962 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10964 09:59:25.827640 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10965 09:59:25.852424 [[0;32m OK [<4>[ 19.108344] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10966 09:59:25.859378 0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10967 09:59:25.876086 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10968 09:59:25.895943 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10969 09:59:25.953249 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10970 09:59:25.973172 <4>[ 19.228595] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10971 09:59:25.999866 Starting [0;1;39mUser Login Management[0m...
10972 09:59:26.020307 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10973 09:59:26.042225 Starting [0;1;39mPermit User Sessions[0m...
10974 09:59:26.057466 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10975 09:59:26.092204 [[0;32m OK [<4>[ 19.348379] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10976 09:59:26.098669 0m] Finished [0;1;39mPermit User Sessions[0m.
10977 09:59:26.128462 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10978 09:59:26.152488 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10979 09:59:26.171891 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10980 09:59:26.193318 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10981 09:59:26.215124 [[0;32m OK [0m] Reached targ<4>[ 19.468529] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10982 09:59:26.217974 et [0;1;39mMulti-User System[0m.
10983 09:59:26.233152 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10984 09:59:26.296399 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10985 09:59:26.333517 <4>[ 19.588772] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10986 09:59:26.339581 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10987 09:59:26.383702
10988 09:59:26.383819
10989 09:59:26.386580 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10990 09:59:26.386661
10991 09:59:26.389878 debian-bullseye-arm64 login: root (automatic login)
10992 09:59:26.389979
10993 09:59:26.390073
10994 09:59:26.408398 Linux debian-bullseye-arm64 6.1.62-cip9 #1 SMP PREEMPT Fri Nov 24 09:44:51 UTC 2023 aarch64
10995 09:59:26.408525
10996 09:59:26.415261 The programs included with the Debian GNU/Linux system are free software;
10997 09:59:26.422028 the exact distribution terms for each program are described in the
10998 09:59:26.425660 individual files in /usr/share/doc/*/copyright.
10999 09:59:26.425743
11000 09:59:26.432003 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11001 09:59:26.435070 permitted by applicable law.
11002 09:59:26.435716 Matched prompt #10: / #
11004 09:59:26.436049 Setting prompt string to ['/ #']
11005 09:59:26.436183 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11007 09:59:26.436498 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11008 09:59:26.436623 start: 2.2.6 expect-shell-connection (timeout 00:03:29) [common]
11009 09:59:26.436725 Setting prompt string to ['/ #']
11010 09:59:26.436823 Forcing a shell prompt, looking for ['/ #']
11012 09:59:26.487094 / #
11013 09:59:26.487270 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11014 09:59:26.487358 Waiting using forced prompt support (timeout 00:02:30)
11015 09:59:26.487464 <4>[ 19.707974] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11016 09:59:26.492423
11017 09:59:26.492718 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11018 09:59:26.492836 start: 2.2.7 export-device-env (timeout 00:03:29) [common]
11019 09:59:26.492961 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11020 09:59:26.493076 end: 2.2 depthcharge-retry (duration 00:01:31) [common]
11021 09:59:26.493194 end: 2 depthcharge-action (duration 00:01:31) [common]
11022 09:59:26.493313 start: 3 lava-test-retry (timeout 00:05:00) [common]
11023 09:59:26.493430 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11024 09:59:26.493540 Using namespace: common
11026 09:59:26.593892 / # #
11027 09:59:26.594097 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11028 09:59:26.594259 #<4>[ 19.828233] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11029 09:59:26.599161
11030 09:59:26.599460 Using /lava-12073283
11032 09:59:26.699852 / # export SHELL=/bin/sh
11033 09:59:26.700081 export SHELL=/bin/sh<4>[ 19.948153] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11034 09:59:26.742524 <6>[ 19.967983] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c722dd6: link becomes ready
11035 09:59:26.742637
11036 09:59:26.742703 <6>[ 19.976178] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
11038 09:59:26.843224 / # . /lava-12073283/environment
11039 09:59:26.843444 . /lava-12073283/environment<3>[ 20.068746] mt7921e 0000:01:00.0: hardware init failed
11040 09:59:26.848286
11042 09:59:26.948824 / # /lava-12073283/bin/lava-test-runner /lava-12073283/0
11043 09:59:26.949002 Test shell timeout: 10s (minimum of the action and connection timeout)
11044 09:59:26.953780 /lava-12073283/bin/lava-test-runner /lava-12073283/0
11045 09:59:26.977104 + export TESTRUN_ID=0_cros-ec
11046 09:59:26.983793 + c<8>[ 20.245107] <LAVA_SIGNAL_STARTRUN 0_cros-ec 12073283_1.5.2.3.1>
11047 09:59:26.984088 Received signal: <STARTRUN> 0_cros-ec 12073283_1.5.2.3.1
11048 09:59:26.984198 Starting test lava.0_cros-ec (12073283_1.5.2.3.1)
11049 09:59:26.984317 Skipping test definition patterns.
11050 09:59:26.987223 d /lava-12073283/0/tests/0_cros-ec
11051 09:59:26.991100 + cat uuid
11052 09:59:26.991213 + UUID=12073283_1.5.2.3.1
11053 09:59:26.991311 + set +x
11054 09:59:26.996952 + python3 -m cros.runners.lava_runner -v
11055 09:59:27.403499 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
11056 09:59:27.409779 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11057 09:59:27.413068
11058 09:59:27.419705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11059 09:59:27.419958 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11061 09:59:27.426095 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
11062 09:59:27.436536 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11063 09:59:27.436645
11064 09:59:27.439921 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_<8
11065 09:59:27.440043 Test case results without result (probably a sign of an incorrect parsing pattern being used): {'test_case_id': 'test_cros_ec_accel_iio_data_is_<8', 'result': 'unknown'}
11066 09:59:27.446272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_<8>[ 20.707958] <LAVA_SIGNAL_ENDRUN 0_cros-ec 12073283_1.5.2.3.1>
11067 09:59:27.446546 Received signal: <ENDRUN> 0_cros-ec 12073283_1.5.2.3.1
11068 09:59:27.446657 Ending use of test pattern.
11069 09:59:27.446753 Ending test lava.0_cros-ec (12073283_1.5.2.3.1), duration 0.46
11071 09:59:27.449453 valid RESULT=skip>
11072 09:59:27.456566 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
11073 09:59:27.462765 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11074 09:59:27.462868
11075 09:59:27.466163 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11077 09:59:27.469320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11078 09:59:27.472854 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11079 09:59:27.479613 Checks the standard ABI for the main Embedded Controller. ... ok
11080 09:59:27.479736
11081 09:59:27.482967 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11083 09:59:27.486212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11084 09:59:27.489199 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
11085 09:59:27.495883 Checks the main Embedded controller character device. ... ok
11086 09:59:27.496014
11087 09:59:27.502449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11088 09:59:27.502740 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11090 09:59:27.505900 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11091 09:59:27.512595 Checks basic comunication with the main Embedded controller. ... ok
11092 09:59:27.512709
11093 09:59:27.519287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11094 09:59:27.519574 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11096 09:59:27.522215 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11097 09:59:27.532407 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11098 09:59:27.532523
11099 09:59:27.535706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11100 09:59:27.535985 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11102 09:59:27.542274 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11103 09:59:27.552501 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11104 09:59:27.552617
11105 09:59:27.555687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11106 09:59:27.555971 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11108 09:59:27.562168 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
11109 09:59:27.568745 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11110 09:59:27.568865
11111 09:59:27.575412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11112 09:59:27.575711 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11114 09:59:27.578804 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11115 09:59:27.588535 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11116 09:59:27.588657
11117 09:59:27.591911 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11119 09:59:27.595100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11120 09:59:27.598327 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11121 09:59:27.608534 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11122 09:59:27.608641
11123 09:59:27.612373 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11125 09:59:27.615141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11126 09:59:27.618421 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11127 09:59:27.624845 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11128 09:59:27.624954
11129 09:59:27.631898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11130 09:59:27.632209 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11132 09:59:27.638154 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11133 09:59:27.644749 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11134 09:59:27.644863
11135 09:59:27.651311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11136 09:59:27.651594 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11138 09:59:27.658742 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
11139 09:59:27.664796 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11140 09:59:27.664881
11141 09:59:27.671401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11142 09:59:27.671659 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11144 09:59:27.677993 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
11145 09:59:27.684570 Check the cros battery ABI. ... skipped 'No BAT found'
11146 09:59:27.684653
11147 09:59:27.691064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11148 09:59:27.691318 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11150 09:59:27.697716 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
11151 09:59:27.704317 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11152 09:59:27.704406
11153 09:59:27.710910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11154 09:59:27.711166 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11156 09:59:27.714480 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
11157 09:59:27.720849 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11158 09:59:27.724199
11159 09:59:27.727710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11160 09:59:27.727965 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11162 09:59:27.733873 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
11163 09:59:27.741052 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11164 09:59:27.741194
11165 09:59:27.747493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11166 09:59:27.747578
11167 09:59:27.747834 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11169 09:59:27.753714 ----------------------------------------------------------------------
11170 09:59:27.756995 Ran 18 tests in 0.007s
11171 09:59:27.757079
11172 09:59:27.757144 OK (skipped=15)
11173 09:59:27.760798 + set +x
11174 09:59:27.760885 <LAVA_TEST_RUNNER EXIT>
11175 09:59:27.761125 ok: lava_test_shell seems to have completed
11176 09:59:27.761298 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11177 09:59:27.761397 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11178 09:59:27.761486 end: 3 lava-test-retry (duration 00:00:01) [common]
11179 09:59:27.761575 start: 4 finalize (timeout 00:08:06) [common]
11180 09:59:27.761664 start: 4.1 power-off (timeout 00:00:30) [common]
11181 09:59:27.761816 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11182 09:59:27.838232 >> Command sent successfully.
11183 09:59:27.840791 Returned 0 in 0 seconds
11184 09:59:27.941263 end: 4.1 power-off (duration 00:00:00) [common]
11186 09:59:27.941613 start: 4.2 read-feedback (timeout 00:08:06) [common]
11187 09:59:27.941886 Listened to connection for namespace 'common' for up to 1s
11188 09:59:28.942481 Finalising connection for namespace 'common'
11189 09:59:28.942661 Disconnecting from shell: Finalise
11190 09:59:28.942745 / #
11191 09:59:29.043060 end: 4.2 read-feedback (duration 00:00:01) [common]
11192 09:59:29.043237 end: 4 finalize (duration 00:00:01) [common]
11193 09:59:29.043387 Cleaning after the job
11194 09:59:29.043502 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073283/tftp-deploy-xg3kmoi7/ramdisk
11195 09:59:29.048714 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073283/tftp-deploy-xg3kmoi7/kernel
11196 09:59:29.055127 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073283/tftp-deploy-xg3kmoi7/dtb
11197 09:59:29.055301 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073283/tftp-deploy-xg3kmoi7/modules
11198 09:59:29.060787 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12073283
11199 09:59:29.161955 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12073283
11200 09:59:29.162151 Job finished correctly