Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 33
- Kernel Warnings: 23
- Boot result: PASS
- Errors: 0
1 10:00:02.731664 lava-dispatcher, installed at version: 2023.10
2 10:00:02.731866 start: 0 validate
3 10:00:02.731994 Start time: 2023-11-24 10:00:02.731986+00:00 (UTC)
4 10:00:02.732111 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:00:02.732237 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 10:00:02.994393 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:00:02.995122 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:00:03.266664 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:00:03.267508 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:00:03.529981 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:00:03.530741 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 10:00:03.807730 validate duration: 1.08
14 10:00:03.809175 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 10:00:03.809706 start: 1.1 download-retry (timeout 00:10:00) [common]
16 10:00:03.810200 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 10:00:03.810823 Not decompressing ramdisk as can be used compressed.
18 10:00:03.811344 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230623.0/arm64/rootfs.cpio.gz
19 10:00:03.811701 saving as /var/lib/lava/dispatcher/tmp/12073309/tftp-deploy-djv8i3is/ramdisk/rootfs.cpio.gz
20 10:00:03.812054 total size: 43284872 (41 MB)
21 10:00:03.817311 progress 0 % (0 MB)
22 10:00:03.851923 progress 5 % (2 MB)
23 10:00:03.867181 progress 10 % (4 MB)
24 10:00:03.878860 progress 15 % (6 MB)
25 10:00:03.889914 progress 20 % (8 MB)
26 10:00:03.901262 progress 25 % (10 MB)
27 10:00:03.912469 progress 30 % (12 MB)
28 10:00:03.923533 progress 35 % (14 MB)
29 10:00:03.934368 progress 40 % (16 MB)
30 10:00:03.945370 progress 45 % (18 MB)
31 10:00:03.956428 progress 50 % (20 MB)
32 10:00:03.967533 progress 55 % (22 MB)
33 10:00:03.978659 progress 60 % (24 MB)
34 10:00:03.989863 progress 65 % (26 MB)
35 10:00:04.000903 progress 70 % (28 MB)
36 10:00:04.012167 progress 75 % (30 MB)
37 10:00:04.023333 progress 80 % (33 MB)
38 10:00:04.034464 progress 85 % (35 MB)
39 10:00:04.045426 progress 90 % (37 MB)
40 10:00:04.056242 progress 95 % (39 MB)
41 10:00:04.067330 progress 100 % (41 MB)
42 10:00:04.067584 41 MB downloaded in 0.26 s (161.53 MB/s)
43 10:00:04.067763 end: 1.1.1 http-download (duration 00:00:00) [common]
45 10:00:04.068005 end: 1.1 download-retry (duration 00:00:00) [common]
46 10:00:04.068089 start: 1.2 download-retry (timeout 00:10:00) [common]
47 10:00:04.068172 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 10:00:04.068308 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 10:00:04.068379 saving as /var/lib/lava/dispatcher/tmp/12073309/tftp-deploy-djv8i3is/kernel/Image
50 10:00:04.068436 total size: 49107456 (46 MB)
51 10:00:04.068494 No compression specified
52 10:00:04.069869 progress 0 % (0 MB)
53 10:00:04.082426 progress 5 % (2 MB)
54 10:00:04.094976 progress 10 % (4 MB)
55 10:00:04.107397 progress 15 % (7 MB)
56 10:00:04.120389 progress 20 % (9 MB)
57 10:00:04.133126 progress 25 % (11 MB)
58 10:00:04.145644 progress 30 % (14 MB)
59 10:00:04.158039 progress 35 % (16 MB)
60 10:00:04.170935 progress 40 % (18 MB)
61 10:00:04.183424 progress 45 % (21 MB)
62 10:00:04.195903 progress 50 % (23 MB)
63 10:00:04.208345 progress 55 % (25 MB)
64 10:00:04.220654 progress 60 % (28 MB)
65 10:00:04.233415 progress 65 % (30 MB)
66 10:00:04.245836 progress 70 % (32 MB)
67 10:00:04.258412 progress 75 % (35 MB)
68 10:00:04.271269 progress 80 % (37 MB)
69 10:00:04.284018 progress 85 % (39 MB)
70 10:00:04.296763 progress 90 % (42 MB)
71 10:00:04.309103 progress 95 % (44 MB)
72 10:00:04.321439 progress 100 % (46 MB)
73 10:00:04.321638 46 MB downloaded in 0.25 s (184.96 MB/s)
74 10:00:04.321785 end: 1.2.1 http-download (duration 00:00:00) [common]
76 10:00:04.322006 end: 1.2 download-retry (duration 00:00:00) [common]
77 10:00:04.322094 start: 1.3 download-retry (timeout 00:09:59) [common]
78 10:00:04.322181 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 10:00:04.322319 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 10:00:04.322386 saving as /var/lib/lava/dispatcher/tmp/12073309/tftp-deploy-djv8i3is/dtb/mt8192-asurada-spherion-r0.dtb
81 10:00:04.322444 total size: 47278 (0 MB)
82 10:00:04.322502 No compression specified
83 10:00:04.323628 progress 69 % (0 MB)
84 10:00:04.323896 progress 100 % (0 MB)
85 10:00:04.324046 0 MB downloaded in 0.00 s (28.18 MB/s)
86 10:00:04.324164 end: 1.3.1 http-download (duration 00:00:00) [common]
88 10:00:04.324380 end: 1.3 download-retry (duration 00:00:00) [common]
89 10:00:04.324462 start: 1.4 download-retry (timeout 00:09:59) [common]
90 10:00:04.324571 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 10:00:04.324700 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 10:00:04.324766 saving as /var/lib/lava/dispatcher/tmp/12073309/tftp-deploy-djv8i3is/modules/modules.tar
93 10:00:04.324824 total size: 8622040 (8 MB)
94 10:00:04.324882 Using unxz to decompress xz
95 10:00:04.328972 progress 0 % (0 MB)
96 10:00:04.349600 progress 5 % (0 MB)
97 10:00:04.373244 progress 10 % (0 MB)
98 10:00:04.396479 progress 15 % (1 MB)
99 10:00:04.419420 progress 20 % (1 MB)
100 10:00:04.443002 progress 25 % (2 MB)
101 10:00:04.468260 progress 30 % (2 MB)
102 10:00:04.494313 progress 35 % (2 MB)
103 10:00:04.517587 progress 40 % (3 MB)
104 10:00:04.541447 progress 45 % (3 MB)
105 10:00:04.566716 progress 50 % (4 MB)
106 10:00:04.590966 progress 55 % (4 MB)
107 10:00:04.615552 progress 60 % (4 MB)
108 10:00:04.642781 progress 65 % (5 MB)
109 10:00:04.667621 progress 70 % (5 MB)
110 10:00:04.691039 progress 75 % (6 MB)
111 10:00:04.717921 progress 80 % (6 MB)
112 10:00:04.743519 progress 85 % (7 MB)
113 10:00:04.768380 progress 90 % (7 MB)
114 10:00:04.797918 progress 95 % (7 MB)
115 10:00:04.827222 progress 100 % (8 MB)
116 10:00:04.831908 8 MB downloaded in 0.51 s (16.22 MB/s)
117 10:00:04.832155 end: 1.4.1 http-download (duration 00:00:01) [common]
119 10:00:04.832412 end: 1.4 download-retry (duration 00:00:01) [common]
120 10:00:04.832511 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 10:00:04.832615 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 10:00:04.832696 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 10:00:04.832779 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 10:00:04.833009 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12073309/lava-overlay-hvpicfei
125 10:00:04.833141 makedir: /var/lib/lava/dispatcher/tmp/12073309/lava-overlay-hvpicfei/lava-12073309/bin
126 10:00:04.833246 makedir: /var/lib/lava/dispatcher/tmp/12073309/lava-overlay-hvpicfei/lava-12073309/tests
127 10:00:04.833361 makedir: /var/lib/lava/dispatcher/tmp/12073309/lava-overlay-hvpicfei/lava-12073309/results
128 10:00:04.833478 Creating /var/lib/lava/dispatcher/tmp/12073309/lava-overlay-hvpicfei/lava-12073309/bin/lava-add-keys
129 10:00:04.833630 Creating /var/lib/lava/dispatcher/tmp/12073309/lava-overlay-hvpicfei/lava-12073309/bin/lava-add-sources
130 10:00:04.833761 Creating /var/lib/lava/dispatcher/tmp/12073309/lava-overlay-hvpicfei/lava-12073309/bin/lava-background-process-start
131 10:00:04.833890 Creating /var/lib/lava/dispatcher/tmp/12073309/lava-overlay-hvpicfei/lava-12073309/bin/lava-background-process-stop
132 10:00:04.834014 Creating /var/lib/lava/dispatcher/tmp/12073309/lava-overlay-hvpicfei/lava-12073309/bin/lava-common-functions
133 10:00:04.834138 Creating /var/lib/lava/dispatcher/tmp/12073309/lava-overlay-hvpicfei/lava-12073309/bin/lava-echo-ipv4
134 10:00:04.834260 Creating /var/lib/lava/dispatcher/tmp/12073309/lava-overlay-hvpicfei/lava-12073309/bin/lava-install-packages
135 10:00:04.834386 Creating /var/lib/lava/dispatcher/tmp/12073309/lava-overlay-hvpicfei/lava-12073309/bin/lava-installed-packages
136 10:00:04.834507 Creating /var/lib/lava/dispatcher/tmp/12073309/lava-overlay-hvpicfei/lava-12073309/bin/lava-os-build
137 10:00:04.834629 Creating /var/lib/lava/dispatcher/tmp/12073309/lava-overlay-hvpicfei/lava-12073309/bin/lava-probe-channel
138 10:00:04.834750 Creating /var/lib/lava/dispatcher/tmp/12073309/lava-overlay-hvpicfei/lava-12073309/bin/lava-probe-ip
139 10:00:04.834871 Creating /var/lib/lava/dispatcher/tmp/12073309/lava-overlay-hvpicfei/lava-12073309/bin/lava-target-ip
140 10:00:04.834993 Creating /var/lib/lava/dispatcher/tmp/12073309/lava-overlay-hvpicfei/lava-12073309/bin/lava-target-mac
141 10:00:04.835115 Creating /var/lib/lava/dispatcher/tmp/12073309/lava-overlay-hvpicfei/lava-12073309/bin/lava-target-storage
142 10:00:04.835243 Creating /var/lib/lava/dispatcher/tmp/12073309/lava-overlay-hvpicfei/lava-12073309/bin/lava-test-case
143 10:00:04.835391 Creating /var/lib/lava/dispatcher/tmp/12073309/lava-overlay-hvpicfei/lava-12073309/bin/lava-test-event
144 10:00:04.835514 Creating /var/lib/lava/dispatcher/tmp/12073309/lava-overlay-hvpicfei/lava-12073309/bin/lava-test-feedback
145 10:00:04.835638 Creating /var/lib/lava/dispatcher/tmp/12073309/lava-overlay-hvpicfei/lava-12073309/bin/lava-test-raise
146 10:00:04.835761 Creating /var/lib/lava/dispatcher/tmp/12073309/lava-overlay-hvpicfei/lava-12073309/bin/lava-test-reference
147 10:00:04.835883 Creating /var/lib/lava/dispatcher/tmp/12073309/lava-overlay-hvpicfei/lava-12073309/bin/lava-test-runner
148 10:00:04.836005 Creating /var/lib/lava/dispatcher/tmp/12073309/lava-overlay-hvpicfei/lava-12073309/bin/lava-test-set
149 10:00:04.836128 Creating /var/lib/lava/dispatcher/tmp/12073309/lava-overlay-hvpicfei/lava-12073309/bin/lava-test-shell
150 10:00:04.836254 Updating /var/lib/lava/dispatcher/tmp/12073309/lava-overlay-hvpicfei/lava-12073309/bin/lava-install-packages (oe)
151 10:00:04.836408 Updating /var/lib/lava/dispatcher/tmp/12073309/lava-overlay-hvpicfei/lava-12073309/bin/lava-installed-packages (oe)
152 10:00:04.836535 Creating /var/lib/lava/dispatcher/tmp/12073309/lava-overlay-hvpicfei/lava-12073309/environment
153 10:00:04.836634 LAVA metadata
154 10:00:04.836705 - LAVA_JOB_ID=12073309
155 10:00:04.836769 - LAVA_DISPATCHER_IP=192.168.201.1
156 10:00:04.836870 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 10:00:04.836936 skipped lava-vland-overlay
158 10:00:04.837008 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 10:00:04.837085 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 10:00:04.837152 skipped lava-multinode-overlay
161 10:00:04.837227 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 10:00:04.837310 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 10:00:04.837383 Loading test definitions
164 10:00:04.837472 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 10:00:04.837543 Using /lava-12073309 at stage 0
166 10:00:04.837853 uuid=12073309_1.5.2.3.1 testdef=None
167 10:00:04.837939 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 10:00:04.838021 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 10:00:04.838537 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 10:00:04.838752 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 10:00:04.839352 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 10:00:04.839574 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 10:00:04.840296 runner path: /var/lib/lava/dispatcher/tmp/12073309/lava-overlay-hvpicfei/lava-12073309/0/tests/0_igt-gpu-panfrost test_uuid 12073309_1.5.2.3.1
176 10:00:04.840451 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 10:00:04.840728 Creating lava-test-runner.conf files
179 10:00:04.840789 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12073309/lava-overlay-hvpicfei/lava-12073309/0 for stage 0
180 10:00:04.840875 - 0_igt-gpu-panfrost
181 10:00:04.840970 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 10:00:04.841051 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 10:00:04.847590 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 10:00:04.847693 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 10:00:04.847781 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 10:00:04.847864 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 10:00:04.847952 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 10:00:06.225710 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 10:00:06.226075 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 10:00:06.226188 extracting modules file /var/lib/lava/dispatcher/tmp/12073309/tftp-deploy-djv8i3is/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12073309/extract-overlay-ramdisk-cbpd53g9/ramdisk
191 10:00:06.454195 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 10:00:06.454350 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 10:00:06.454454 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12073309/compress-overlay-vvu7txv4/overlay-1.5.2.4.tar.gz to ramdisk
194 10:00:06.454527 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12073309/compress-overlay-vvu7txv4/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12073309/extract-overlay-ramdisk-cbpd53g9/ramdisk
195 10:00:06.461264 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 10:00:06.461376 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 10:00:06.461467 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 10:00:06.461554 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 10:00:06.461631 Building ramdisk /var/lib/lava/dispatcher/tmp/12073309/extract-overlay-ramdisk-cbpd53g9/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12073309/extract-overlay-ramdisk-cbpd53g9/ramdisk
200 10:00:07.499335 >> 369976 blocks
201 10:00:13.146457 rename /var/lib/lava/dispatcher/tmp/12073309/extract-overlay-ramdisk-cbpd53g9/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12073309/tftp-deploy-djv8i3is/ramdisk/ramdisk.cpio.gz
202 10:00:13.146899 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 10:00:13.147022 start: 1.5.8 prepare-kernel (timeout 00:09:51) [common]
204 10:00:13.147117 start: 1.5.8.1 prepare-fit (timeout 00:09:51) [common]
205 10:00:13.147221 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12073309/tftp-deploy-djv8i3is/kernel/Image'
206 10:00:25.008501 Returned 0 in 11 seconds
207 10:00:25.109572 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12073309/tftp-deploy-djv8i3is/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12073309/tftp-deploy-djv8i3is/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12073309/tftp-deploy-djv8i3is/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12073309/tftp-deploy-djv8i3is/kernel/image.itb
208 10:00:25.955633 output: FIT description: Kernel Image image with one or more FDT blobs
209 10:00:25.956011 output: Created: Fri Nov 24 10:00:25 2023
210 10:00:25.956087 output: Image 0 (kernel-1)
211 10:00:25.956154 output: Description:
212 10:00:25.956217 output: Created: Fri Nov 24 10:00:25 2023
213 10:00:25.956279 output: Type: Kernel Image
214 10:00:25.956338 output: Compression: lzma compressed
215 10:00:25.956396 output: Data Size: 11047542 Bytes = 10788.62 KiB = 10.54 MiB
216 10:00:25.956450 output: Architecture: AArch64
217 10:00:25.956503 output: OS: Linux
218 10:00:25.956600 output: Load Address: 0x00000000
219 10:00:25.956655 output: Entry Point: 0x00000000
220 10:00:25.956707 output: Hash algo: crc32
221 10:00:25.956760 output: Hash value: 2edffaa3
222 10:00:25.956815 output: Image 1 (fdt-1)
223 10:00:25.956869 output: Description: mt8192-asurada-spherion-r0
224 10:00:25.956920 output: Created: Fri Nov 24 10:00:25 2023
225 10:00:25.956972 output: Type: Flat Device Tree
226 10:00:25.957039 output: Compression: uncompressed
227 10:00:25.957105 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 10:00:25.957158 output: Architecture: AArch64
229 10:00:25.957209 output: Hash algo: crc32
230 10:00:25.957261 output: Hash value: cc4352de
231 10:00:25.957313 output: Image 2 (ramdisk-1)
232 10:00:25.957364 output: Description: unavailable
233 10:00:25.957415 output: Created: Fri Nov 24 10:00:25 2023
234 10:00:25.957466 output: Type: RAMDisk Image
235 10:00:25.957563 output: Compression: Unknown Compression
236 10:00:25.957633 output: Data Size: 56431441 Bytes = 55108.83 KiB = 53.82 MiB
237 10:00:25.957715 output: Architecture: AArch64
238 10:00:25.957795 output: OS: Linux
239 10:00:25.957876 output: Load Address: unavailable
240 10:00:25.957969 output: Entry Point: unavailable
241 10:00:25.958037 output: Hash algo: crc32
242 10:00:25.958089 output: Hash value: 100158cf
243 10:00:25.958141 output: Default Configuration: 'conf-1'
244 10:00:25.958193 output: Configuration 0 (conf-1)
245 10:00:25.958245 output: Description: mt8192-asurada-spherion-r0
246 10:00:25.958298 output: Kernel: kernel-1
247 10:00:25.958350 output: Init Ramdisk: ramdisk-1
248 10:00:25.958403 output: FDT: fdt-1
249 10:00:25.958455 output: Loadables: kernel-1
250 10:00:25.958507 output:
251 10:00:25.958716 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 10:00:25.958813 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 10:00:25.958917 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 10:00:25.959009 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 10:00:25.959084 No LXC device requested
256 10:00:25.959166 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 10:00:25.959248 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 10:00:25.959328 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 10:00:25.959401 Checking files for TFTP limit of 4294967296 bytes.
260 10:00:25.959905 end: 1 tftp-deploy (duration 00:00:22) [common]
261 10:00:25.960010 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 10:00:25.960103 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 10:00:25.960228 substitutions:
264 10:00:25.960348 - {DTB}: 12073309/tftp-deploy-djv8i3is/dtb/mt8192-asurada-spherion-r0.dtb
265 10:00:25.960454 - {INITRD}: 12073309/tftp-deploy-djv8i3is/ramdisk/ramdisk.cpio.gz
266 10:00:25.960555 - {KERNEL}: 12073309/tftp-deploy-djv8i3is/kernel/Image
267 10:00:25.960617 - {LAVA_MAC}: None
268 10:00:25.960703 - {PRESEED_CONFIG}: None
269 10:00:25.960787 - {PRESEED_LOCAL}: None
270 10:00:25.960855 - {RAMDISK}: 12073309/tftp-deploy-djv8i3is/ramdisk/ramdisk.cpio.gz
271 10:00:25.960925 - {ROOT_PART}: None
272 10:00:25.960980 - {ROOT}: None
273 10:00:25.961033 - {SERVER_IP}: 192.168.201.1
274 10:00:25.961087 - {TEE}: None
275 10:00:25.961141 Parsed boot commands:
276 10:00:25.961197 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 10:00:25.961379 Parsed boot commands: tftpboot 192.168.201.1 12073309/tftp-deploy-djv8i3is/kernel/image.itb 12073309/tftp-deploy-djv8i3is/kernel/cmdline
278 10:00:25.961469 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 10:00:25.961557 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 10:00:25.961653 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 10:00:25.961739 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 10:00:25.961813 Not connected, no need to disconnect.
283 10:00:25.961887 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 10:00:25.961969 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 10:00:25.962035 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
286 10:00:25.966086 Setting prompt string to ['lava-test: # ']
287 10:00:25.966447 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 10:00:25.966555 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 10:00:25.966652 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 10:00:25.966790 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 10:00:25.967032 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
292 10:00:31.105072 >> Command sent successfully.
293 10:00:31.117900 Returned 0 in 5 seconds
294 10:00:31.219206 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 10:00:31.220711 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 10:00:31.221262 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 10:00:31.221714 Setting prompt string to 'Starting depthcharge on Spherion...'
299 10:00:31.222158 Changing prompt to 'Starting depthcharge on Spherion...'
300 10:00:31.222555 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 10:00:31.223860 [Enter `^Ec?' for help]
302 10:00:31.387008
303 10:00:31.387706
304 10:00:31.388113 F0: 102B 0000
305 10:00:31.388584
306 10:00:31.388946 F3: 1001 0000 [0200]
307 10:00:31.389276
308 10:00:31.390271 F3: 1001 0000
309 10:00:31.390889
310 10:00:31.391265 F7: 102D 0000
311 10:00:31.391702
312 10:00:31.392047 F1: 0000 0000
313 10:00:31.394420
314 10:00:31.395001 V0: 0000 0000 [0001]
315 10:00:31.395369
316 10:00:31.395704 00: 0007 8000
317 10:00:31.396052
318 10:00:31.398029 01: 0000 0000
319 10:00:31.398497
320 10:00:31.398873 BP: 0C00 0209 [0000]
321 10:00:31.399216
322 10:00:31.399538 G0: 1182 0000
323 10:00:31.402142
324 10:00:31.402715 EC: 0000 0021 [4000]
325 10:00:31.403238
326 10:00:31.405376 S7: 0000 0000 [0000]
327 10:00:31.405838
328 10:00:31.406203 CC: 0000 0000 [0001]
329 10:00:31.406539
330 10:00:31.408689 T0: 0000 0040 [010F]
331 10:00:31.409282
332 10:00:31.409658 Jump to BL
333 10:00:31.410008
334 10:00:31.433773
335 10:00:31.434288
336 10:00:31.434646
337 10:00:31.441345 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 10:00:31.444943 ARM64: Exception handlers installed.
339 10:00:31.448610 ARM64: Testing exception
340 10:00:31.452320 ARM64: Done test exception
341 10:00:31.459705 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 10:00:31.467468 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 10:00:31.474615 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 10:00:31.484633 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 10:00:31.491000 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 10:00:31.501433 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 10:00:31.511797 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 10:00:31.518351 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 10:00:31.536599 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 10:00:31.540152 WDT: Last reset was cold boot
351 10:00:31.543125 SPI1(PAD0) initialized at 2873684 Hz
352 10:00:31.546465 SPI5(PAD0) initialized at 992727 Hz
353 10:00:31.549977 VBOOT: Loading verstage.
354 10:00:31.556211 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 10:00:31.559596 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 10:00:31.563214 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 10:00:31.566327 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 10:00:31.573926 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 10:00:31.580705 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 10:00:31.591625 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 10:00:31.592253
362 10:00:31.592817
363 10:00:31.601377 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 10:00:31.605755 ARM64: Exception handlers installed.
365 10:00:31.606311 ARM64: Testing exception
366 10:00:31.609352 ARM64: Done test exception
367 10:00:31.612327 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 10:00:31.619088 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 10:00:31.632366 Probing TPM: . done!
370 10:00:31.632994 TPM ready after 0 ms
371 10:00:31.640045 Connected to device vid:did:rid of 1ae0:0028:00
372 10:00:31.646664 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
373 10:00:31.693113 Initialized TPM device CR50 revision 0
374 10:00:31.708533 tlcl_send_startup: Startup return code is 0
375 10:00:31.709186 TPM: setup succeeded
376 10:00:31.719181 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 10:00:31.727624 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 10:00:31.737604 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 10:00:31.746474 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 10:00:31.750099 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 10:00:31.753262 in-header: 03 07 00 00 08 00 00 00
382 10:00:31.756482 in-data: aa e4 47 04 13 02 00 00
383 10:00:31.759986 Chrome EC: UHEPI supported
384 10:00:31.766503 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 10:00:31.770607 in-header: 03 95 00 00 08 00 00 00
386 10:00:31.773399 in-data: 18 20 20 08 00 00 00 00
387 10:00:31.773870 Phase 1
388 10:00:31.777109 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 10:00:31.784309 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 10:00:31.788068 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 10:00:31.791719 Recovery requested (1009000e)
392 10:00:31.801162 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 10:00:31.807223 tlcl_extend: response is 0
394 10:00:31.816433 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 10:00:31.821670 tlcl_extend: response is 0
396 10:00:31.828770 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 10:00:31.849693 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 10:00:31.856417 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 10:00:31.856970
400 10:00:31.857416
401 10:00:31.863765 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 10:00:31.867465 ARM64: Exception handlers installed.
403 10:00:31.871217 ARM64: Testing exception
404 10:00:31.874488 ARM64: Done test exception
405 10:00:31.894197 pmic_efuse_setting: Set efuses in 11 msecs
406 10:00:31.897664 pmwrap_interface_init: Select PMIF_VLD_RDY
407 10:00:31.904349 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 10:00:31.907786 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 10:00:31.914137 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 10:00:31.917922 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 10:00:31.924327 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 10:00:31.927841 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 10:00:31.931065 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 10:00:31.937311 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 10:00:31.940888 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 10:00:31.947798 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 10:00:31.950983 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 10:00:31.954288 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 10:00:31.961155 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 10:00:31.967979 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 10:00:31.971333 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 10:00:31.977826 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 10:00:31.984913 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 10:00:31.988705 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 10:00:31.996150 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 10:00:31.999800 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 10:00:32.006674 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 10:00:32.010687 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 10:00:32.017946 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 10:00:32.021276 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 10:00:32.029176 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 10:00:32.033114 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 10:00:32.040242 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 10:00:32.044006 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 10:00:32.047471 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 10:00:32.054862 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 10:00:32.058997 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 10:00:32.062657 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 10:00:32.069894 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 10:00:32.073509 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 10:00:32.077353 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 10:00:32.084875 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 10:00:32.088319 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 10:00:32.092372 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 10:00:32.099807 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 10:00:32.103169 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 10:00:32.106859 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 10:00:32.110516 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 10:00:32.114324 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 10:00:32.121419 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 10:00:32.125205 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 10:00:32.129133 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 10:00:32.132834 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 10:00:32.136385 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 10:00:32.140256 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 10:00:32.143572 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 10:00:32.150847 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 10:00:32.158593 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 10:00:32.165779 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 10:00:32.169356 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 10:00:32.180111 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 10:00:32.187434 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 10:00:32.190998 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 10:00:32.194192 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 10:00:32.201813 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 10:00:32.209105 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x19
467 10:00:32.213072 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 10:00:32.216570 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 10:00:32.220254 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 10:00:32.232005 [RTC]rtc_get_frequency_meter,154: input=15, output=763
471 10:00:32.240899 [RTC]rtc_get_frequency_meter,154: input=23, output=948
472 10:00:32.250825 [RTC]rtc_get_frequency_meter,154: input=19, output=856
473 10:00:32.261149 [RTC]rtc_get_frequency_meter,154: input=17, output=810
474 10:00:32.270418 [RTC]rtc_get_frequency_meter,154: input=16, output=787
475 10:00:32.279475 [RTC]rtc_get_frequency_meter,154: input=16, output=788
476 10:00:32.288864 [RTC]rtc_get_frequency_meter,154: input=17, output=811
477 10:00:32.292170 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 10:00:32.299893 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 10:00:32.303538 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 10:00:32.306756 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 10:00:32.310584 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 10:00:32.313981 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 10:00:32.317924 ADC[4]: Raw value=669695 ID=5
484 10:00:32.321519 ADC[3]: Raw value=212917 ID=1
485 10:00:32.322069 RAM Code: 0x51
486 10:00:32.325258 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 10:00:32.332770 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 10:00:32.339929 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
489 10:00:32.343762 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
490 10:00:32.347363 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 10:00:32.351563 in-header: 03 07 00 00 08 00 00 00
492 10:00:32.354595 in-data: aa e4 47 04 13 02 00 00
493 10:00:32.358586 Chrome EC: UHEPI supported
494 10:00:32.365755 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 10:00:32.369434 in-header: 03 95 00 00 08 00 00 00
496 10:00:32.373431 in-data: 18 20 20 08 00 00 00 00
497 10:00:32.374246 MRC: failed to locate region type 0.
498 10:00:32.380133 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 10:00:32.383911 DRAM-K: Running full calibration
500 10:00:32.391674 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
501 10:00:32.392278 header.status = 0x0
502 10:00:32.395440 header.version = 0x6 (expected: 0x6)
503 10:00:32.398760 header.size = 0xd00 (expected: 0xd00)
504 10:00:32.399232 header.flags = 0x0
505 10:00:32.405882 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 10:00:32.425092 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 10:00:32.432458 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 10:00:32.433010 dram_init: ddr_geometry: 0
509 10:00:32.436306 [EMI] MDL number = 0
510 10:00:32.437152 [EMI] Get MDL freq = 0
511 10:00:32.439786 dram_init: ddr_type: 0
512 10:00:32.443195 is_discrete_lpddr4: 1
513 10:00:32.443840 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 10:00:32.446851
515 10:00:32.447430
516 10:00:32.448047 [Bian_co] ETT version 0.0.0.1
517 10:00:32.454170 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
518 10:00:32.454831
519 10:00:32.458144 dramc_set_vcore_voltage set vcore to 650000
520 10:00:32.458614 Read voltage for 800, 4
521 10:00:32.458980 Vio18 = 0
522 10:00:32.462194 Vcore = 650000
523 10:00:32.462657 Vdram = 0
524 10:00:32.463005 Vddq = 0
525 10:00:32.463307 Vmddr = 0
526 10:00:32.466206 dram_init: config_dvfs: 1
527 10:00:32.469589 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 10:00:32.476996 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 10:00:32.480832 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 10:00:32.484489 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 10:00:32.488175 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 10:00:32.491865 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 10:00:32.495613 MEM_TYPE=3, freq_sel=18
534 10:00:32.496140 sv_algorithm_assistance_LP4_1600
535 10:00:32.503016 ============ PULL DRAM RESETB DOWN ============
536 10:00:32.506502 ========== PULL DRAM RESETB DOWN end =========
537 10:00:32.510128 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 10:00:32.513865 ===================================
539 10:00:32.514286 LPDDR4 DRAM CONFIGURATION
540 10:00:32.517663 ===================================
541 10:00:32.521391 EX_ROW_EN[0] = 0x0
542 10:00:32.521820 EX_ROW_EN[1] = 0x0
543 10:00:32.525280 LP4Y_EN = 0x0
544 10:00:32.525811 WORK_FSP = 0x0
545 10:00:32.528974 WL = 0x2
546 10:00:32.529396 RL = 0x2
547 10:00:32.532474 BL = 0x2
548 10:00:32.532938 RPST = 0x0
549 10:00:32.536743 RD_PRE = 0x0
550 10:00:32.537304 WR_PRE = 0x1
551 10:00:32.540325 WR_PST = 0x0
552 10:00:32.540790 DBI_WR = 0x0
553 10:00:32.541126 DBI_RD = 0x0
554 10:00:32.543580 OTF = 0x1
555 10:00:32.547232 ===================================
556 10:00:32.551015 ===================================
557 10:00:32.551509 ANA top config
558 10:00:32.554721 ===================================
559 10:00:32.558677 DLL_ASYNC_EN = 0
560 10:00:32.559129 ALL_SLAVE_EN = 1
561 10:00:32.561967 NEW_RANK_MODE = 1
562 10:00:32.565357 DLL_IDLE_MODE = 1
563 10:00:32.568728 LP45_APHY_COMB_EN = 1
564 10:00:32.569152 TX_ODT_DIS = 1
565 10:00:32.572086 NEW_8X_MODE = 1
566 10:00:32.575693 ===================================
567 10:00:32.578716 ===================================
568 10:00:32.582564 data_rate = 1600
569 10:00:32.586056 CKR = 1
570 10:00:32.589718 DQ_P2S_RATIO = 8
571 10:00:32.590295 ===================================
572 10:00:32.593073 CA_P2S_RATIO = 8
573 10:00:32.596958 DQ_CA_OPEN = 0
574 10:00:32.600277 DQ_SEMI_OPEN = 0
575 10:00:32.604151 CA_SEMI_OPEN = 0
576 10:00:32.604808 CA_FULL_RATE = 0
577 10:00:32.607465 DQ_CKDIV4_EN = 1
578 10:00:32.610562 CA_CKDIV4_EN = 1
579 10:00:32.614228 CA_PREDIV_EN = 0
580 10:00:32.617450 PH8_DLY = 0
581 10:00:32.618011 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 10:00:32.620640 DQ_AAMCK_DIV = 4
583 10:00:32.624493 CA_AAMCK_DIV = 4
584 10:00:32.628676 CA_ADMCK_DIV = 4
585 10:00:32.629353 DQ_TRACK_CA_EN = 0
586 10:00:32.631512 CA_PICK = 800
587 10:00:32.635386 CA_MCKIO = 800
588 10:00:32.638863 MCKIO_SEMI = 0
589 10:00:32.642131 PLL_FREQ = 3068
590 10:00:32.645439 DQ_UI_PI_RATIO = 32
591 10:00:32.645967 CA_UI_PI_RATIO = 0
592 10:00:32.648713 ===================================
593 10:00:32.652323 ===================================
594 10:00:32.655847 memory_type:LPDDR4
595 10:00:32.659398 GP_NUM : 10
596 10:00:32.659834 SRAM_EN : 1
597 10:00:32.663206 MD32_EN : 0
598 10:00:32.666857 ===================================
599 10:00:32.667331 [ANA_INIT] >>>>>>>>>>>>>>
600 10:00:32.670400 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 10:00:32.673639 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 10:00:32.677473 ===================================
603 10:00:32.681131 data_rate = 1600,PCW = 0X7600
604 10:00:32.684686 ===================================
605 10:00:32.688486 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 10:00:32.691751 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 10:00:32.698675 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 10:00:32.701589 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 10:00:32.705433 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 10:00:32.708766 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 10:00:32.711734 [ANA_INIT] flow start
612 10:00:32.715351 [ANA_INIT] PLL >>>>>>>>
613 10:00:32.715915 [ANA_INIT] PLL <<<<<<<<
614 10:00:32.718382 [ANA_INIT] MIDPI >>>>>>>>
615 10:00:32.722111 [ANA_INIT] MIDPI <<<<<<<<
616 10:00:32.722732 [ANA_INIT] DLL >>>>>>>>
617 10:00:32.725340 [ANA_INIT] flow end
618 10:00:32.728915 ============ LP4 DIFF to SE enter ============
619 10:00:32.731935 ============ LP4 DIFF to SE exit ============
620 10:00:32.735117 [ANA_INIT] <<<<<<<<<<<<<
621 10:00:32.738353 [Flow] Enable top DCM control >>>>>
622 10:00:32.741661 [Flow] Enable top DCM control <<<<<
623 10:00:32.745053 Enable DLL master slave shuffle
624 10:00:32.751631 ==============================================================
625 10:00:32.752245 Gating Mode config
626 10:00:32.758439 ==============================================================
627 10:00:32.758962 Config description:
628 10:00:32.768730 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 10:00:32.775265 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 10:00:32.781586 SELPH_MODE 0: By rank 1: By Phase
631 10:00:32.785254 ==============================================================
632 10:00:32.788402 GAT_TRACK_EN = 1
633 10:00:32.792012 RX_GATING_MODE = 2
634 10:00:32.795243 RX_GATING_TRACK_MODE = 2
635 10:00:32.798928 SELPH_MODE = 1
636 10:00:32.801676 PICG_EARLY_EN = 1
637 10:00:32.805275 VALID_LAT_VALUE = 1
638 10:00:32.808486 ==============================================================
639 10:00:32.811481 Enter into Gating configuration >>>>
640 10:00:32.814901 Exit from Gating configuration <<<<
641 10:00:32.818839 Enter into DVFS_PRE_config >>>>>
642 10:00:32.831923 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 10:00:32.835088 Exit from DVFS_PRE_config <<<<<
644 10:00:32.838367 Enter into PICG configuration >>>>
645 10:00:32.838839 Exit from PICG configuration <<<<
646 10:00:32.841437 [RX_INPUT] configuration >>>>>
647 10:00:32.844679 [RX_INPUT] configuration <<<<<
648 10:00:32.851734 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 10:00:32.855011 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 10:00:32.861649 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 10:00:32.868290 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 10:00:32.874709 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 10:00:32.881224 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 10:00:32.884890 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 10:00:32.888438 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 10:00:32.891579 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 10:00:32.898162 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 10:00:32.901518 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 10:00:32.905048 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 10:00:32.908010 ===================================
661 10:00:32.911460 LPDDR4 DRAM CONFIGURATION
662 10:00:32.914855 ===================================
663 10:00:32.918361 EX_ROW_EN[0] = 0x0
664 10:00:32.918929 EX_ROW_EN[1] = 0x0
665 10:00:32.921546 LP4Y_EN = 0x0
666 10:00:32.922014 WORK_FSP = 0x0
667 10:00:32.925150 WL = 0x2
668 10:00:32.925719 RL = 0x2
669 10:00:32.928676 BL = 0x2
670 10:00:32.929245 RPST = 0x0
671 10:00:32.931596 RD_PRE = 0x0
672 10:00:32.932164 WR_PRE = 0x1
673 10:00:32.934938 WR_PST = 0x0
674 10:00:32.935510 DBI_WR = 0x0
675 10:00:32.938351 DBI_RD = 0x0
676 10:00:32.938921 OTF = 0x1
677 10:00:32.941276 ===================================
678 10:00:32.944688 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 10:00:32.951353 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 10:00:32.954826 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 10:00:32.957943 ===================================
682 10:00:32.961634 LPDDR4 DRAM CONFIGURATION
683 10:00:32.964741 ===================================
684 10:00:32.965209 EX_ROW_EN[0] = 0x10
685 10:00:32.968127 EX_ROW_EN[1] = 0x0
686 10:00:32.971411 LP4Y_EN = 0x0
687 10:00:32.971875 WORK_FSP = 0x0
688 10:00:32.974745 WL = 0x2
689 10:00:32.975209 RL = 0x2
690 10:00:32.978166 BL = 0x2
691 10:00:32.978634 RPST = 0x0
692 10:00:32.981185 RD_PRE = 0x0
693 10:00:32.981646 WR_PRE = 0x1
694 10:00:32.985078 WR_PST = 0x0
695 10:00:32.985646 DBI_WR = 0x0
696 10:00:32.988172 DBI_RD = 0x0
697 10:00:32.988678 OTF = 0x1
698 10:00:32.991300 ===================================
699 10:00:32.998097 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 10:00:33.002220 nWR fixed to 40
701 10:00:33.005368 [ModeRegInit_LP4] CH0 RK0
702 10:00:33.005832 [ModeRegInit_LP4] CH0 RK1
703 10:00:33.008763 [ModeRegInit_LP4] CH1 RK0
704 10:00:33.012241 [ModeRegInit_LP4] CH1 RK1
705 10:00:33.012728 match AC timing 12
706 10:00:33.019024 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
707 10:00:33.021854 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 10:00:33.025388 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 10:00:33.032046 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 10:00:33.035395 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 10:00:33.035863 [EMI DOE] emi_dcm 0
712 10:00:33.042119 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 10:00:33.042676 ==
714 10:00:33.045347 Dram Type= 6, Freq= 0, CH_0, rank 0
715 10:00:33.048767 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
716 10:00:33.049236 ==
717 10:00:33.055649 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 10:00:33.061579 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 10:00:33.069603 [CA 0] Center 37 (7~68) winsize 62
720 10:00:33.072644 [CA 1] Center 37 (7~68) winsize 62
721 10:00:33.076231 [CA 2] Center 35 (5~66) winsize 62
722 10:00:33.079576 [CA 3] Center 35 (5~66) winsize 62
723 10:00:33.082896 [CA 4] Center 34 (4~65) winsize 62
724 10:00:33.086189 [CA 5] Center 33 (3~64) winsize 62
725 10:00:33.086653
726 10:00:33.089194 [CmdBusTrainingLP45] Vref(ca) range 1: 30
727 10:00:33.089659
728 10:00:33.092681 [CATrainingPosCal] consider 1 rank data
729 10:00:33.096145 u2DelayCellTimex100 = 270/100 ps
730 10:00:33.099742 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 10:00:33.102668 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
732 10:00:33.109306 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
733 10:00:33.112547 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
734 10:00:33.115918 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
735 10:00:33.119136 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 10:00:33.119600
737 10:00:33.122972 CA PerBit enable=1, Macro0, CA PI delay=33
738 10:00:33.123535
739 10:00:33.126131 [CBTSetCACLKResult] CA Dly = 33
740 10:00:33.126693 CS Dly: 5 (0~36)
741 10:00:33.129325 ==
742 10:00:33.132961 Dram Type= 6, Freq= 0, CH_0, rank 1
743 10:00:33.135820 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
744 10:00:33.136286 ==
745 10:00:33.139562 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 10:00:33.145782 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 10:00:33.155240 [CA 0] Center 37 (6~68) winsize 63
748 10:00:33.158728 [CA 1] Center 37 (6~68) winsize 63
749 10:00:33.162215 [CA 2] Center 35 (4~66) winsize 63
750 10:00:33.165216 [CA 3] Center 34 (4~65) winsize 62
751 10:00:33.168823 [CA 4] Center 33 (3~64) winsize 62
752 10:00:33.172122 [CA 5] Center 33 (3~64) winsize 62
753 10:00:33.172758
754 10:00:33.175629 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 10:00:33.176195
756 10:00:33.178811 [CATrainingPosCal] consider 2 rank data
757 10:00:33.182417 u2DelayCellTimex100 = 270/100 ps
758 10:00:33.185462 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 10:00:33.188974 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 10:00:33.195585 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
761 10:00:33.198908 CA3 delay=35 (5~65),Diff = 2 PI (14 cell)
762 10:00:33.201961 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
763 10:00:33.205302 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 10:00:33.205883
765 10:00:33.208487 CA PerBit enable=1, Macro0, CA PI delay=33
766 10:00:33.209093
767 10:00:33.211746 [CBTSetCACLKResult] CA Dly = 33
768 10:00:33.212214 CS Dly: 6 (0~38)
769 10:00:33.215290
770 10:00:33.218654 ----->DramcWriteLeveling(PI) begin...
771 10:00:33.219224 ==
772 10:00:33.221926 Dram Type= 6, Freq= 0, CH_0, rank 0
773 10:00:33.225255 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
774 10:00:33.225817 ==
775 10:00:33.228613 Write leveling (Byte 0): 30 => 30
776 10:00:33.232160 Write leveling (Byte 1): 29 => 29
777 10:00:33.235936 DramcWriteLeveling(PI) end<-----
778 10:00:33.236495
779 10:00:33.236909 ==
780 10:00:33.239262 Dram Type= 6, Freq= 0, CH_0, rank 0
781 10:00:33.242853 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
782 10:00:33.243428 ==
783 10:00:33.246505 [Gating] SW mode calibration
784 10:00:33.250394 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 10:00:33.256993 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 10:00:33.260153 0 6 0 | B1->B0 | 3333 3131 | 1 0 | (1 0) (0 1)
787 10:00:33.267231 0 6 4 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
788 10:00:33.270488 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 10:00:33.273938 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 10:00:33.280474 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 10:00:33.283780 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 10:00:33.286964 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 10:00:33.293680 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 10:00:33.297233 0 7 0 | B1->B0 | 2828 2b2b | 0 0 | (0 0) (0 0)
795 10:00:33.300666 0 7 4 | B1->B0 | 3939 3d3d | 1 0 | (0 0) (0 0)
796 10:00:33.303674 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
797 10:00:33.310350 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
798 10:00:33.313603 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
799 10:00:33.316953 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
800 10:00:33.324046 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
801 10:00:33.326974 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
802 10:00:33.330444 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
803 10:00:33.337121 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
804 10:00:33.340577 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
805 10:00:33.343498 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
806 10:00:33.350872 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
807 10:00:33.353705 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
808 10:00:33.357499 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
809 10:00:33.363618 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
810 10:00:33.367109 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
811 10:00:33.370964 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
812 10:00:33.377342 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
813 10:00:33.380459 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
814 10:00:33.383581 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
815 10:00:33.390621 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
816 10:00:33.394102 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
817 10:00:33.397101 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
818 10:00:33.400614 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
819 10:00:33.407138 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
820 10:00:33.410300 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
821 10:00:33.413588 Total UI for P1: 0, mck2ui 16
822 10:00:33.417097 best dqsien dly found for B0: ( 0, 10, 2)
823 10:00:33.420485 Total UI for P1: 0, mck2ui 16
824 10:00:33.423848 best dqsien dly found for B1: ( 0, 10, 2)
825 10:00:33.427250 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
826 10:00:33.430401 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
827 10:00:33.431055
828 10:00:33.434134 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
829 10:00:33.437132 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
830 10:00:33.440401 [Gating] SW calibration Done
831 10:00:33.441004 ==
832 10:00:33.443549 Dram Type= 6, Freq= 0, CH_0, rank 0
833 10:00:33.450602 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
834 10:00:33.451168 ==
835 10:00:33.451542 RX Vref Scan: 0
836 10:00:33.451884
837 10:00:33.453450 RX Vref 0 -> 0, step: 1
838 10:00:33.453916
839 10:00:33.456756 RX Delay -130 -> 252, step: 16
840 10:00:33.460284 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
841 10:00:33.463658 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
842 10:00:33.467171 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
843 10:00:33.470414 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
844 10:00:33.477019 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
845 10:00:33.480458 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
846 10:00:33.483501 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
847 10:00:33.486957 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
848 10:00:33.490410 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
849 10:00:33.496861 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
850 10:00:33.500114 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
851 10:00:33.503612 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
852 10:00:33.507000 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
853 10:00:33.509944 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
854 10:00:33.516826 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
855 10:00:33.520306 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
856 10:00:33.520922 ==
857 10:00:33.523823 Dram Type= 6, Freq= 0, CH_0, rank 0
858 10:00:33.527052 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
859 10:00:33.527622 ==
860 10:00:33.530246 DQS Delay:
861 10:00:33.530836 DQS0 = 0, DQS1 = 0
862 10:00:33.531212 DQM Delay:
863 10:00:33.533607 DQM0 = 82, DQM1 = 71
864 10:00:33.534170 DQ Delay:
865 10:00:33.536872 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
866 10:00:33.540406 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
867 10:00:33.544060 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
868 10:00:33.547142 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
869 10:00:33.547777
870 10:00:33.548157
871 10:00:33.548498 ==
872 10:00:33.550050 Dram Type= 6, Freq= 0, CH_0, rank 0
873 10:00:33.556699 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
874 10:00:33.557174 ==
875 10:00:33.557545
876 10:00:33.557883
877 10:00:33.558212 TX Vref Scan disable
878 10:00:33.560564 == TX Byte 0 ==
879 10:00:33.563417 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
880 10:00:33.570345 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
881 10:00:33.570919 == TX Byte 1 ==
882 10:00:33.573734 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
883 10:00:33.577167 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
884 10:00:33.580719 ==
885 10:00:33.583870 Dram Type= 6, Freq= 0, CH_0, rank 0
886 10:00:33.587008 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
887 10:00:33.587580 ==
888 10:00:33.599491 TX Vref=22, minBit 0, minWin=27, winSum=443
889 10:00:33.602635 TX Vref=24, minBit 3, minWin=27, winSum=449
890 10:00:33.606047 TX Vref=26, minBit 4, minWin=27, winSum=456
891 10:00:33.609484 TX Vref=28, minBit 2, minWin=28, winSum=458
892 10:00:33.612648 TX Vref=30, minBit 0, minWin=28, winSum=457
893 10:00:33.616205 TX Vref=32, minBit 1, minWin=27, winSum=453
894 10:00:33.622703 [TxChooseVref] Worse bit 2, Min win 28, Win sum 458, Final Vref 28
895 10:00:33.623258
896 10:00:33.625754 Final TX Range 1 Vref 28
897 10:00:33.626227
898 10:00:33.626639 ==
899 10:00:33.629154 Dram Type= 6, Freq= 0, CH_0, rank 0
900 10:00:33.632871 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
901 10:00:33.633343 ==
902 10:00:33.633709
903 10:00:33.634047
904 10:00:33.636354 TX Vref Scan disable
905 10:00:33.639870 == TX Byte 0 ==
906 10:00:33.643015 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
907 10:00:33.646463 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
908 10:00:33.649712 == TX Byte 1 ==
909 10:00:33.653048 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
910 10:00:33.656563 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
911 10:00:33.656992
912 10:00:33.659941 [DATLAT]
913 10:00:33.660591 Freq=800, CH0 RK0
914 10:00:33.660953
915 10:00:33.663264 DATLAT Default: 0xa
916 10:00:33.663790 0, 0xFFFF, sum = 0
917 10:00:33.666635 1, 0xFFFF, sum = 0
918 10:00:33.667182 2, 0xFFFF, sum = 0
919 10:00:33.669940 3, 0xFFFF, sum = 0
920 10:00:33.670472 4, 0xFFFF, sum = 0
921 10:00:33.673169 5, 0xFFFF, sum = 0
922 10:00:33.673599 6, 0xFFFF, sum = 0
923 10:00:33.676729 7, 0xFFFF, sum = 0
924 10:00:33.677257 8, 0x0, sum = 1
925 10:00:33.679884 9, 0x0, sum = 2
926 10:00:33.680415 10, 0x0, sum = 3
927 10:00:33.683164 11, 0x0, sum = 4
928 10:00:33.683591 best_step = 9
929 10:00:33.683921
930 10:00:33.684229 ==
931 10:00:33.686803 Dram Type= 6, Freq= 0, CH_0, rank 0
932 10:00:33.690047 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
933 10:00:33.690582 ==
934 10:00:33.693372 RX Vref Scan: 1
935 10:00:33.693902
936 10:00:33.696953 Set Vref Range= 32 -> 127
937 10:00:33.697481
938 10:00:33.697818 RX Vref 32 -> 127, step: 1
939 10:00:33.698127
940 10:00:33.700038 RX Delay -111 -> 252, step: 8
941 10:00:33.700609
942 10:00:33.703397 Set Vref, RX VrefLevel [Byte0]: 32
943 10:00:33.706472 [Byte1]: 32
944 10:00:33.710013
945 10:00:33.710534 Set Vref, RX VrefLevel [Byte0]: 33
946 10:00:33.713193 [Byte1]: 33
947 10:00:33.717749
948 10:00:33.718271 Set Vref, RX VrefLevel [Byte0]: 34
949 10:00:33.721512 [Byte1]: 34
950 10:00:33.725469
951 10:00:33.725992 Set Vref, RX VrefLevel [Byte0]: 35
952 10:00:33.728718 [Byte1]: 35
953 10:00:33.733106
954 10:00:33.733656 Set Vref, RX VrefLevel [Byte0]: 36
955 10:00:33.736290 [Byte1]: 36
956 10:00:33.740707
957 10:00:33.741231 Set Vref, RX VrefLevel [Byte0]: 37
958 10:00:33.744227 [Byte1]: 37
959 10:00:33.748558
960 10:00:33.749086 Set Vref, RX VrefLevel [Byte0]: 38
961 10:00:33.752023 [Byte1]: 38
962 10:00:33.756189
963 10:00:33.756767 Set Vref, RX VrefLevel [Byte0]: 39
964 10:00:33.759259 [Byte1]: 39
965 10:00:33.763780
966 10:00:33.764307 Set Vref, RX VrefLevel [Byte0]: 40
967 10:00:33.767207 [Byte1]: 40
968 10:00:33.771350
969 10:00:33.771872 Set Vref, RX VrefLevel [Byte0]: 41
970 10:00:33.774582 [Byte1]: 41
971 10:00:33.778949
972 10:00:33.779471 Set Vref, RX VrefLevel [Byte0]: 42
973 10:00:33.782079 [Byte1]: 42
974 10:00:33.786516
975 10:00:33.786931 Set Vref, RX VrefLevel [Byte0]: 43
976 10:00:33.789815 [Byte1]: 43
977 10:00:33.794216
978 10:00:33.794739 Set Vref, RX VrefLevel [Byte0]: 44
979 10:00:33.797446 [Byte1]: 44
980 10:00:33.801981
981 10:00:33.802504 Set Vref, RX VrefLevel [Byte0]: 45
982 10:00:33.805128 [Byte1]: 45
983 10:00:33.809460
984 10:00:33.810012 Set Vref, RX VrefLevel [Byte0]: 46
985 10:00:33.812691 [Byte1]: 46
986 10:00:33.817205
987 10:00:33.817667 Set Vref, RX VrefLevel [Byte0]: 47
988 10:00:33.820426 [Byte1]: 47
989 10:00:33.824888
990 10:00:33.825413 Set Vref, RX VrefLevel [Byte0]: 48
991 10:00:33.828188 [Byte1]: 48
992 10:00:33.832460
993 10:00:33.833033 Set Vref, RX VrefLevel [Byte0]: 49
994 10:00:33.836110 [Byte1]: 49
995 10:00:33.840210
996 10:00:33.840782 Set Vref, RX VrefLevel [Byte0]: 50
997 10:00:33.843540 [Byte1]: 50
998 10:00:33.847895
999 10:00:33.848643 Set Vref, RX VrefLevel [Byte0]: 51
1000 10:00:33.851371 [Byte1]: 51
1001 10:00:33.855561
1002 10:00:33.856108 Set Vref, RX VrefLevel [Byte0]: 52
1003 10:00:33.858467 [Byte1]: 52
1004 10:00:33.863119
1005 10:00:33.863636 Set Vref, RX VrefLevel [Byte0]: 53
1006 10:00:33.866113 [Byte1]: 53
1007 10:00:33.870811
1008 10:00:33.871343 Set Vref, RX VrefLevel [Byte0]: 54
1009 10:00:33.873727 [Byte1]: 54
1010 10:00:33.878212
1011 10:00:33.878762 Set Vref, RX VrefLevel [Byte0]: 55
1012 10:00:33.881581 [Byte1]: 55
1013 10:00:33.885634
1014 10:00:33.886051 Set Vref, RX VrefLevel [Byte0]: 56
1015 10:00:33.889424 [Byte1]: 56
1016 10:00:33.893704
1017 10:00:33.894256 Set Vref, RX VrefLevel [Byte0]: 57
1018 10:00:33.897089 [Byte1]: 57
1019 10:00:33.901641
1020 10:00:33.902168 Set Vref, RX VrefLevel [Byte0]: 58
1021 10:00:33.904920 [Byte1]: 58
1022 10:00:33.909545
1023 10:00:33.910057 Set Vref, RX VrefLevel [Byte0]: 59
1024 10:00:33.912607 [Byte1]: 59
1025 10:00:33.916813
1026 10:00:33.917227 Set Vref, RX VrefLevel [Byte0]: 60
1027 10:00:33.919899 [Byte1]: 60
1028 10:00:33.924284
1029 10:00:33.924725 Set Vref, RX VrefLevel [Byte0]: 61
1030 10:00:33.927394 [Byte1]: 61
1031 10:00:33.932100
1032 10:00:33.932639 Set Vref, RX VrefLevel [Byte0]: 62
1033 10:00:33.935592 [Byte1]: 62
1034 10:00:33.939981
1035 10:00:33.940481 Set Vref, RX VrefLevel [Byte0]: 63
1036 10:00:33.942641 [Byte1]: 63
1037 10:00:33.947094
1038 10:00:33.947565 Set Vref, RX VrefLevel [Byte0]: 64
1039 10:00:33.950589 [Byte1]: 64
1040 10:00:33.954867
1041 10:00:33.955433 Set Vref, RX VrefLevel [Byte0]: 65
1042 10:00:33.957774 [Byte1]: 65
1043 10:00:33.962968
1044 10:00:33.963546 Set Vref, RX VrefLevel [Byte0]: 66
1045 10:00:33.965924 [Byte1]: 66
1046 10:00:33.970156
1047 10:00:33.970725 Set Vref, RX VrefLevel [Byte0]: 67
1048 10:00:33.973190 [Byte1]: 67
1049 10:00:33.977882
1050 10:00:33.978452 Set Vref, RX VrefLevel [Byte0]: 68
1051 10:00:33.981145 [Byte1]: 68
1052 10:00:33.985273
1053 10:00:33.985836 Set Vref, RX VrefLevel [Byte0]: 69
1054 10:00:33.988591 [Byte1]: 69
1055 10:00:33.993446
1056 10:00:33.994050 Set Vref, RX VrefLevel [Byte0]: 70
1057 10:00:33.996197 [Byte1]: 70
1058 10:00:34.000778
1059 10:00:34.001370 Set Vref, RX VrefLevel [Byte0]: 71
1060 10:00:34.004011 [Byte1]: 71
1061 10:00:34.008349
1062 10:00:34.008977 Set Vref, RX VrefLevel [Byte0]: 72
1063 10:00:34.011594 [Byte1]: 72
1064 10:00:34.015948
1065 10:00:34.016572 Set Vref, RX VrefLevel [Byte0]: 73
1066 10:00:34.019184 [Byte1]: 73
1067 10:00:34.023878
1068 10:00:34.024446 Set Vref, RX VrefLevel [Byte0]: 74
1069 10:00:34.026968 [Byte1]: 74
1070 10:00:34.031285
1071 10:00:34.031853 Set Vref, RX VrefLevel [Byte0]: 75
1072 10:00:34.034681 [Byte1]: 75
1073 10:00:34.038866
1074 10:00:34.039425 Set Vref, RX VrefLevel [Byte0]: 76
1075 10:00:34.042443 [Byte1]: 76
1076 10:00:34.046595
1077 10:00:34.047364 Final RX Vref Byte 0 = 51 to rank0
1078 10:00:34.049728 Final RX Vref Byte 1 = 50 to rank0
1079 10:00:34.053030 Final RX Vref Byte 0 = 51 to rank1
1080 10:00:34.056630 Final RX Vref Byte 1 = 50 to rank1==
1081 10:00:34.059998 Dram Type= 6, Freq= 0, CH_0, rank 0
1082 10:00:34.066709 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1083 10:00:34.067267 ==
1084 10:00:34.067665 DQS Delay:
1085 10:00:34.068009 DQS0 = 0, DQS1 = 0
1086 10:00:34.069845 DQM Delay:
1087 10:00:34.070301 DQM0 = 83, DQM1 = 73
1088 10:00:34.073354 DQ Delay:
1089 10:00:34.076458 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1090 10:00:34.076962 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1091 10:00:34.080041 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1092 10:00:34.083071 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1093 10:00:34.086937
1094 10:00:34.087492
1095 10:00:34.093298 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c3c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1096 10:00:34.096688 CH0 RK0: MR19=606, MR18=3C3C
1097 10:00:34.103155 CH0_RK0: MR19=0x606, MR18=0x3C3C, DQSOSC=394, MR23=63, INC=95, DEC=63
1098 10:00:34.103701
1099 10:00:34.106760 ----->DramcWriteLeveling(PI) begin...
1100 10:00:34.107320 ==
1101 10:00:34.110075 Dram Type= 6, Freq= 0, CH_0, rank 1
1102 10:00:34.113226 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1103 10:00:34.113839 ==
1104 10:00:34.116647 Write leveling (Byte 0): 31 => 31
1105 10:00:34.119535 Write leveling (Byte 1): 30 => 30
1106 10:00:34.123236 DramcWriteLeveling(PI) end<-----
1107 10:00:34.123795
1108 10:00:34.124154 ==
1109 10:00:34.126333 Dram Type= 6, Freq= 0, CH_0, rank 1
1110 10:00:34.129819 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1111 10:00:34.130375 ==
1112 10:00:34.133203 [Gating] SW mode calibration
1113 10:00:34.139692 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1114 10:00:34.146484 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1115 10:00:34.149705 0 6 0 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
1116 10:00:34.153434 0 6 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1117 10:00:34.159870 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1118 10:00:34.163173 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1119 10:00:34.166480 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1120 10:00:34.173170 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1121 10:00:34.176616 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1122 10:00:34.179784 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1123 10:00:34.186344 0 7 0 | B1->B0 | 2a2a 3333 | 0 1 | (0 0) (1 1)
1124 10:00:34.189811 0 7 4 | B1->B0 | 4646 4545 | 0 0 | (0 0) (1 1)
1125 10:00:34.193060 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1126 10:00:34.199435 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1127 10:00:34.203203 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1128 10:00:34.206624 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1129 10:00:34.213201 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1130 10:00:34.216066 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1131 10:00:34.219504 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1132 10:00:34.223224 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1133 10:00:34.229608 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1134 10:00:34.233138 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1135 10:00:34.236725 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1136 10:00:34.243202 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1137 10:00:34.246201 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1138 10:00:34.249459 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1139 10:00:34.256118 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1140 10:00:34.259403 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1141 10:00:34.262717 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1142 10:00:34.269493 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1143 10:00:34.273154 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1144 10:00:34.276356 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1145 10:00:34.283136 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1146 10:00:34.286336 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1147 10:00:34.289732 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1148 10:00:34.296239 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1149 10:00:34.296844 Total UI for P1: 0, mck2ui 16
1150 10:00:34.299902 best dqsien dly found for B0: ( 0, 10, 0)
1151 10:00:34.303098 Total UI for P1: 0, mck2ui 16
1152 10:00:34.306449 best dqsien dly found for B1: ( 0, 10, 0)
1153 10:00:34.309582 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1154 10:00:34.351969 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1155 10:00:34.352797
1156 10:00:34.353190 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1157 10:00:34.353530 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1158 10:00:34.353857 [Gating] SW calibration Done
1159 10:00:34.354173 ==
1160 10:00:34.354869 Dram Type= 6, Freq= 0, CH_0, rank 1
1161 10:00:34.355248 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1162 10:00:34.355673 ==
1163 10:00:34.356003 RX Vref Scan: 0
1164 10:00:34.356313
1165 10:00:34.356672 RX Vref 0 -> 0, step: 1
1166 10:00:34.356992
1167 10:00:34.357288 RX Delay -130 -> 252, step: 16
1168 10:00:34.357588 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1169 10:00:34.357886 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1170 10:00:34.358255 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1171 10:00:34.359249 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1172 10:00:34.359703 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1173 10:00:34.362608 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1174 10:00:34.369222 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1175 10:00:34.373080 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1176 10:00:34.376321 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1177 10:00:34.379785 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1178 10:00:34.383150 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1179 10:00:34.386270 iDelay=222, Bit 11, Center 61 (-50 ~ 173) 224
1180 10:00:34.393046 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1181 10:00:34.396470 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1182 10:00:34.399630 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1183 10:00:34.402888 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1184 10:00:34.403445 ==
1185 10:00:34.406279 Dram Type= 6, Freq= 0, CH_0, rank 1
1186 10:00:34.412583 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1187 10:00:34.413144 ==
1188 10:00:34.413506 DQS Delay:
1189 10:00:34.415822 DQS0 = 0, DQS1 = 0
1190 10:00:34.416275 DQM Delay:
1191 10:00:34.416685 DQM0 = 82, DQM1 = 72
1192 10:00:34.419280 DQ Delay:
1193 10:00:34.422754 DQ0 =77, DQ1 =85, DQ2 =85, DQ3 =77
1194 10:00:34.426043 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
1195 10:00:34.429471 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1196 10:00:34.432811 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1197 10:00:34.433382
1198 10:00:34.433744
1199 10:00:34.434076 ==
1200 10:00:34.435972 Dram Type= 6, Freq= 0, CH_0, rank 1
1201 10:00:34.439185 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1202 10:00:34.439784 ==
1203 10:00:34.440152
1204 10:00:34.440490
1205 10:00:34.442781 TX Vref Scan disable
1206 10:00:34.445711 == TX Byte 0 ==
1207 10:00:34.448986 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1208 10:00:34.452547 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1209 10:00:34.455935 == TX Byte 1 ==
1210 10:00:34.459136 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1211 10:00:34.462324 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1212 10:00:34.462792 ==
1213 10:00:34.465802 Dram Type= 6, Freq= 0, CH_0, rank 1
1214 10:00:34.469099 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1215 10:00:34.469559 ==
1216 10:00:34.483758 TX Vref=22, minBit 0, minWin=27, winSum=447
1217 10:00:34.487401 TX Vref=24, minBit 0, minWin=28, winSum=452
1218 10:00:34.490891 TX Vref=26, minBit 0, minWin=28, winSum=453
1219 10:00:34.494823 TX Vref=28, minBit 2, minWin=28, winSum=458
1220 10:00:34.498242 TX Vref=30, minBit 4, minWin=28, winSum=461
1221 10:00:34.501132 TX Vref=32, minBit 2, minWin=28, winSum=458
1222 10:00:34.508587 [TxChooseVref] Worse bit 4, Min win 28, Win sum 461, Final Vref 30
1223 10:00:34.509171
1224 10:00:34.509534 Final TX Range 1 Vref 30
1225 10:00:34.512367
1226 10:00:34.513026 ==
1227 10:00:34.513406 Dram Type= 6, Freq= 0, CH_0, rank 1
1228 10:00:34.518628 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1229 10:00:34.519090 ==
1230 10:00:34.519448
1231 10:00:34.519782
1232 10:00:34.522280 TX Vref Scan disable
1233 10:00:34.522839 == TX Byte 0 ==
1234 10:00:34.528938 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1235 10:00:34.532468 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1236 10:00:34.533181 == TX Byte 1 ==
1237 10:00:34.538769 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1238 10:00:34.541996 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1239 10:00:34.542454
1240 10:00:34.542813 [DATLAT]
1241 10:00:34.545200 Freq=800, CH0 RK1
1242 10:00:34.545701
1243 10:00:34.546062 DATLAT Default: 0x9
1244 10:00:34.548565 0, 0xFFFF, sum = 0
1245 10:00:34.549031 1, 0xFFFF, sum = 0
1246 10:00:34.551544 2, 0xFFFF, sum = 0
1247 10:00:34.552093 3, 0xFFFF, sum = 0
1248 10:00:34.554944 4, 0xFFFF, sum = 0
1249 10:00:34.555405 5, 0xFFFF, sum = 0
1250 10:00:34.558238 6, 0xFFFF, sum = 0
1251 10:00:34.558700 7, 0xFFFF, sum = 0
1252 10:00:34.561866 8, 0x0, sum = 1
1253 10:00:34.562405 9, 0x0, sum = 2
1254 10:00:34.565216 10, 0x0, sum = 3
1255 10:00:34.565709 11, 0x0, sum = 4
1256 10:00:34.568598 best_step = 9
1257 10:00:34.569143
1258 10:00:34.569503 ==
1259 10:00:34.572176 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 10:00:34.575127 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1261 10:00:34.575751 ==
1262 10:00:34.578322 RX Vref Scan: 0
1263 10:00:34.579029
1264 10:00:34.579471 RX Vref 0 -> 0, step: 1
1265 10:00:34.580001
1266 10:00:34.581475 RX Delay -111 -> 252, step: 8
1267 10:00:34.588229 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1268 10:00:34.591602 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1269 10:00:34.595234 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1270 10:00:34.598181 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1271 10:00:34.601497 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1272 10:00:34.608127 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1273 10:00:34.611561 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1274 10:00:34.614705 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1275 10:00:34.617998 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1276 10:00:34.621681 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1277 10:00:34.628330 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1278 10:00:34.631717 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1279 10:00:34.635392 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1280 10:00:34.638071 iDelay=217, Bit 13, Center 80 (-31 ~ 192) 224
1281 10:00:34.641628 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1282 10:00:34.648363 iDelay=217, Bit 15, Center 80 (-31 ~ 192) 224
1283 10:00:34.649108 ==
1284 10:00:34.651485 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 10:00:34.654767 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1286 10:00:34.655228 ==
1287 10:00:34.655588 DQS Delay:
1288 10:00:34.658454 DQS0 = 0, DQS1 = 0
1289 10:00:34.659001 DQM Delay:
1290 10:00:34.661452 DQM0 = 86, DQM1 = 74
1291 10:00:34.661908 DQ Delay:
1292 10:00:34.664619 DQ0 =80, DQ1 =88, DQ2 =84, DQ3 =84
1293 10:00:34.668160 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1294 10:00:34.671440 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =64
1295 10:00:34.674724 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =80
1296 10:00:34.675177
1297 10:00:34.675530
1298 10:00:34.681881 [DQSOSCAuto] RK1, (LSB)MR18= 0x4646, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
1299 10:00:34.684704 CH0 RK1: MR19=606, MR18=4646
1300 10:00:34.691550 CH0_RK1: MR19=0x606, MR18=0x4646, DQSOSC=392, MR23=63, INC=96, DEC=64
1301 10:00:34.695052 [RxdqsGatingPostProcess] freq 800
1302 10:00:34.701639 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1303 10:00:34.704861 Pre-setting of DQS Precalculation
1304 10:00:34.708407 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1305 10:00:34.708818 ==
1306 10:00:34.711643 Dram Type= 6, Freq= 0, CH_1, rank 0
1307 10:00:34.714660 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1308 10:00:34.715028 ==
1309 10:00:34.721861 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1310 10:00:34.728457 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1311 10:00:34.736079 [CA 0] Center 37 (6~68) winsize 63
1312 10:00:34.739700 [CA 1] Center 37 (6~68) winsize 63
1313 10:00:34.742886 [CA 2] Center 34 (4~65) winsize 62
1314 10:00:34.745877 [CA 3] Center 34 (4~65) winsize 62
1315 10:00:34.749537 [CA 4] Center 33 (3~64) winsize 62
1316 10:00:34.752719 [CA 5] Center 33 (3~64) winsize 62
1317 10:00:34.753174
1318 10:00:34.756107 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1319 10:00:34.756701
1320 10:00:34.759672 [CATrainingPosCal] consider 1 rank data
1321 10:00:34.762874 u2DelayCellTimex100 = 270/100 ps
1322 10:00:34.766056 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1323 10:00:34.769793 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1324 10:00:34.776378 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1325 10:00:34.779711 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1326 10:00:34.783030 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1327 10:00:34.786011 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1328 10:00:34.786464
1329 10:00:34.789704 CA PerBit enable=1, Macro0, CA PI delay=33
1330 10:00:34.790248
1331 10:00:34.793099 [CBTSetCACLKResult] CA Dly = 33
1332 10:00:34.793658 CS Dly: 4 (0~35)
1333 10:00:34.794018 ==
1334 10:00:34.796347 Dram Type= 6, Freq= 0, CH_1, rank 1
1335 10:00:34.802949 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1336 10:00:34.803496 ==
1337 10:00:34.806357 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1338 10:00:34.813237 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1339 10:00:34.821856 [CA 0] Center 37 (6~68) winsize 63
1340 10:00:34.825390 [CA 1] Center 36 (5~68) winsize 64
1341 10:00:34.828561 [CA 2] Center 34 (4~65) winsize 62
1342 10:00:34.831774 [CA 3] Center 34 (4~65) winsize 62
1343 10:00:34.834834 [CA 4] Center 33 (3~64) winsize 62
1344 10:00:34.838484 [CA 5] Center 33 (2~64) winsize 63
1345 10:00:34.839058
1346 10:00:34.841699 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1347 10:00:34.842244
1348 10:00:34.845125 [CATrainingPosCal] consider 2 rank data
1349 10:00:34.848492 u2DelayCellTimex100 = 270/100 ps
1350 10:00:34.851801 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1351 10:00:34.855096 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1352 10:00:34.862055 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1353 10:00:34.865107 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1354 10:00:34.868113 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1355 10:00:34.871685 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1356 10:00:34.872238
1357 10:00:34.875418 CA PerBit enable=1, Macro0, CA PI delay=33
1358 10:00:34.875964
1359 10:00:34.878569 [CBTSetCACLKResult] CA Dly = 33
1360 10:00:34.879118 CS Dly: 4 (0~36)
1361 10:00:34.879482
1362 10:00:34.882185 ----->DramcWriteLeveling(PI) begin...
1363 10:00:34.885112 ==
1364 10:00:34.888609 Dram Type= 6, Freq= 0, CH_1, rank 0
1365 10:00:34.892096 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1366 10:00:34.892697 ==
1367 10:00:34.895120 Write leveling (Byte 0): 22 => 22
1368 10:00:34.898663 Write leveling (Byte 1): 22 => 22
1369 10:00:34.901678 DramcWriteLeveling(PI) end<-----
1370 10:00:34.902275
1371 10:00:34.902645 ==
1372 10:00:34.905232 Dram Type= 6, Freq= 0, CH_1, rank 0
1373 10:00:34.908195 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1374 10:00:34.908801 ==
1375 10:00:34.911853 [Gating] SW mode calibration
1376 10:00:34.918367 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1377 10:00:34.925222 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1378 10:00:34.928636 0 6 0 | B1->B0 | 2e2e 2525 | 0 0 | (0 0) (0 0)
1379 10:00:34.931888 0 6 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1380 10:00:34.934970 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1381 10:00:34.941358 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1382 10:00:34.944600 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1383 10:00:34.948284 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1384 10:00:34.954856 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1385 10:00:34.958295 0 6 28 | B1->B0 | 2525 2828 | 0 0 | (0 0) (0 0)
1386 10:00:34.961504 0 7 0 | B1->B0 | 3131 4040 | 0 1 | (0 0) (0 0)
1387 10:00:34.967934 0 7 4 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1388 10:00:34.971694 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1389 10:00:34.974513 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1390 10:00:34.981152 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1391 10:00:34.984896 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1392 10:00:34.987906 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1393 10:00:34.994574 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1394 10:00:34.998145 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1395 10:00:35.001093 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1396 10:00:35.007442 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1397 10:00:35.011036 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1398 10:00:35.014278 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1399 10:00:35.020634 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1400 10:00:35.024343 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1401 10:00:35.027707 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1402 10:00:35.034396 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1403 10:00:35.037567 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1404 10:00:35.040932 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1405 10:00:35.047567 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1406 10:00:35.051368 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1407 10:00:35.054119 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1408 10:00:35.061161 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1409 10:00:35.063981 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1410 10:00:35.067462 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1411 10:00:35.071115 Total UI for P1: 0, mck2ui 16
1412 10:00:35.074198 best dqsien dly found for B0: ( 0, 9, 28)
1413 10:00:35.077308 Total UI for P1: 0, mck2ui 16
1414 10:00:35.080602 best dqsien dly found for B1: ( 0, 9, 30)
1415 10:00:35.084095 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1416 10:00:35.087505 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1417 10:00:35.087963
1418 10:00:35.091167 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1419 10:00:35.097310 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1420 10:00:35.097854 [Gating] SW calibration Done
1421 10:00:35.098219 ==
1422 10:00:35.100884 Dram Type= 6, Freq= 0, CH_1, rank 0
1423 10:00:35.107365 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1424 10:00:35.107925 ==
1425 10:00:35.108292 RX Vref Scan: 0
1426 10:00:35.108770
1427 10:00:35.111031 RX Vref 0 -> 0, step: 1
1428 10:00:35.111485
1429 10:00:35.113944 RX Delay -130 -> 252, step: 16
1430 10:00:35.117337 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1431 10:00:35.120881 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1432 10:00:35.123964 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1433 10:00:35.130976 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1434 10:00:35.134211 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1435 10:00:35.137326 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1436 10:00:35.141130 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1437 10:00:35.144651 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1438 10:00:35.148346 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1439 10:00:35.152586 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1440 10:00:35.155664 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1441 10:00:35.162721 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1442 10:00:35.166538 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1443 10:00:35.170353 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1444 10:00:35.173489 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1445 10:00:35.177454 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1446 10:00:35.177955 ==
1447 10:00:35.180807 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 10:00:35.184044 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1449 10:00:35.184458 ==
1450 10:00:35.187700 DQS Delay:
1451 10:00:35.188107 DQS0 = 0, DQS1 = 0
1452 10:00:35.188432 DQM Delay:
1453 10:00:35.191051 DQM0 = 81, DQM1 = 76
1454 10:00:35.191557 DQ Delay:
1455 10:00:35.194499 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1456 10:00:35.197631 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1457 10:00:35.201410 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
1458 10:00:35.204343 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1459 10:00:35.204930
1460 10:00:35.205262
1461 10:00:35.205560 ==
1462 10:00:35.207582 Dram Type= 6, Freq= 0, CH_1, rank 0
1463 10:00:35.214200 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1464 10:00:35.214748 ==
1465 10:00:35.215114
1466 10:00:35.215448
1467 10:00:35.215847 TX Vref Scan disable
1468 10:00:35.217811 == TX Byte 0 ==
1469 10:00:35.221058 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
1470 10:00:35.228045 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
1471 10:00:35.228801 == TX Byte 1 ==
1472 10:00:35.231163 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
1473 10:00:35.237900 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
1474 10:00:35.238449 ==
1475 10:00:35.241320 Dram Type= 6, Freq= 0, CH_1, rank 0
1476 10:00:35.244457 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1477 10:00:35.245056 ==
1478 10:00:35.256627 TX Vref=22, minBit 13, minWin=27, winSum=450
1479 10:00:35.260251 TX Vref=24, minBit 0, minWin=28, winSum=453
1480 10:00:35.263574 TX Vref=26, minBit 1, minWin=28, winSum=454
1481 10:00:35.266814 TX Vref=28, minBit 0, minWin=28, winSum=458
1482 10:00:35.270310 TX Vref=30, minBit 1, minWin=28, winSum=459
1483 10:00:35.276816 TX Vref=32, minBit 1, minWin=28, winSum=456
1484 10:00:35.280290 [TxChooseVref] Worse bit 1, Min win 28, Win sum 459, Final Vref 30
1485 10:00:35.280921
1486 10:00:35.283331 Final TX Range 1 Vref 30
1487 10:00:35.283921
1488 10:00:35.284286 ==
1489 10:00:35.286678 Dram Type= 6, Freq= 0, CH_1, rank 0
1490 10:00:35.290140 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1491 10:00:35.290689 ==
1492 10:00:35.293651
1493 10:00:35.294230
1494 10:00:35.294591 TX Vref Scan disable
1495 10:00:35.296725 == TX Byte 0 ==
1496 10:00:35.300050 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
1497 10:00:35.306605 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
1498 10:00:35.307142 == TX Byte 1 ==
1499 10:00:35.310870 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
1500 10:00:35.313438 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
1501 10:00:35.316962
1502 10:00:35.317409 [DATLAT]
1503 10:00:35.317766 Freq=800, CH1 RK0
1504 10:00:35.318102
1505 10:00:35.320013 DATLAT Default: 0xa
1506 10:00:35.320469 0, 0xFFFF, sum = 0
1507 10:00:35.323440 1, 0xFFFF, sum = 0
1508 10:00:35.323992 2, 0xFFFF, sum = 0
1509 10:00:35.326491 3, 0xFFFF, sum = 0
1510 10:00:35.326952 4, 0xFFFF, sum = 0
1511 10:00:35.330039 5, 0xFFFF, sum = 0
1512 10:00:35.333133 6, 0xFFFF, sum = 0
1513 10:00:35.333597 7, 0xFFFF, sum = 0
1514 10:00:35.336759 8, 0x0, sum = 1
1515 10:00:35.337286 9, 0x0, sum = 2
1516 10:00:35.337625 10, 0x0, sum = 3
1517 10:00:35.340337 11, 0x0, sum = 4
1518 10:00:35.340892 best_step = 9
1519 10:00:35.341225
1520 10:00:35.341528 ==
1521 10:00:35.343276 Dram Type= 6, Freq= 0, CH_1, rank 0
1522 10:00:35.349849 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1523 10:00:35.350361 ==
1524 10:00:35.350692 RX Vref Scan: 1
1525 10:00:35.350997
1526 10:00:35.353228 Set Vref Range= 32 -> 127
1527 10:00:35.353734
1528 10:00:35.356487 RX Vref 32 -> 127, step: 1
1529 10:00:35.356929
1530 10:00:35.359939 RX Delay -95 -> 252, step: 8
1531 10:00:35.360444
1532 10:00:35.363375 Set Vref, RX VrefLevel [Byte0]: 32
1533 10:00:35.366390 [Byte1]: 32
1534 10:00:35.366859
1535 10:00:35.369770 Set Vref, RX VrefLevel [Byte0]: 33
1536 10:00:35.373249 [Byte1]: 33
1537 10:00:35.373761
1538 10:00:35.376497 Set Vref, RX VrefLevel [Byte0]: 34
1539 10:00:35.379922 [Byte1]: 34
1540 10:00:35.380426
1541 10:00:35.383103 Set Vref, RX VrefLevel [Byte0]: 35
1542 10:00:35.386213 [Byte1]: 35
1543 10:00:35.390485
1544 10:00:35.391161 Set Vref, RX VrefLevel [Byte0]: 36
1545 10:00:35.393548 [Byte1]: 36
1546 10:00:35.398100
1547 10:00:35.398619 Set Vref, RX VrefLevel [Byte0]: 37
1548 10:00:35.401232 [Byte1]: 37
1549 10:00:35.405599
1550 10:00:35.406101 Set Vref, RX VrefLevel [Byte0]: 38
1551 10:00:35.408691 [Byte1]: 38
1552 10:00:35.413250
1553 10:00:35.413788 Set Vref, RX VrefLevel [Byte0]: 39
1554 10:00:35.416494 [Byte1]: 39
1555 10:00:35.420732
1556 10:00:35.421137 Set Vref, RX VrefLevel [Byte0]: 40
1557 10:00:35.424316 [Byte1]: 40
1558 10:00:35.428438
1559 10:00:35.428992 Set Vref, RX VrefLevel [Byte0]: 41
1560 10:00:35.431447 [Byte1]: 41
1561 10:00:35.436113
1562 10:00:35.436710 Set Vref, RX VrefLevel [Byte0]: 42
1563 10:00:35.439452 [Byte1]: 42
1564 10:00:35.443545
1565 10:00:35.444268 Set Vref, RX VrefLevel [Byte0]: 43
1566 10:00:35.447200 [Byte1]: 43
1567 10:00:35.451034
1568 10:00:35.451477 Set Vref, RX VrefLevel [Byte0]: 44
1569 10:00:35.454171 [Byte1]: 44
1570 10:00:35.458890
1571 10:00:35.459435 Set Vref, RX VrefLevel [Byte0]: 45
1572 10:00:35.462261 [Byte1]: 45
1573 10:00:35.466161
1574 10:00:35.466609 Set Vref, RX VrefLevel [Byte0]: 46
1575 10:00:35.469472 [Byte1]: 46
1576 10:00:35.474287
1577 10:00:35.474832 Set Vref, RX VrefLevel [Byte0]: 47
1578 10:00:35.477105 [Byte1]: 47
1579 10:00:35.481535
1580 10:00:35.482092 Set Vref, RX VrefLevel [Byte0]: 48
1581 10:00:35.485154 [Byte1]: 48
1582 10:00:35.489241
1583 10:00:35.489785 Set Vref, RX VrefLevel [Byte0]: 49
1584 10:00:35.492766 [Byte1]: 49
1585 10:00:35.496738
1586 10:00:35.497277 Set Vref, RX VrefLevel [Byte0]: 50
1587 10:00:35.500011 [Byte1]: 50
1588 10:00:35.504766
1589 10:00:35.505316 Set Vref, RX VrefLevel [Byte0]: 51
1590 10:00:35.507840 [Byte1]: 51
1591 10:00:35.512031
1592 10:00:35.512626 Set Vref, RX VrefLevel [Byte0]: 52
1593 10:00:35.515227 [Byte1]: 52
1594 10:00:35.519563
1595 10:00:35.520107 Set Vref, RX VrefLevel [Byte0]: 53
1596 10:00:35.522946 [Byte1]: 53
1597 10:00:35.527185
1598 10:00:35.527701 Set Vref, RX VrefLevel [Byte0]: 54
1599 10:00:35.530449 [Byte1]: 54
1600 10:00:35.535011
1601 10:00:35.535583 Set Vref, RX VrefLevel [Byte0]: 55
1602 10:00:35.538364 [Byte1]: 55
1603 10:00:35.542403
1604 10:00:35.542947 Set Vref, RX VrefLevel [Byte0]: 56
1605 10:00:35.545684 [Byte1]: 56
1606 10:00:35.549736
1607 10:00:35.550187 Set Vref, RX VrefLevel [Byte0]: 57
1608 10:00:35.553055 [Byte1]: 57
1609 10:00:35.557223
1610 10:00:35.557812 Set Vref, RX VrefLevel [Byte0]: 58
1611 10:00:35.560561 [Byte1]: 58
1612 10:00:35.565139
1613 10:00:35.565643 Set Vref, RX VrefLevel [Byte0]: 59
1614 10:00:35.568382 [Byte1]: 59
1615 10:00:35.572735
1616 10:00:35.573234 Set Vref, RX VrefLevel [Byte0]: 60
1617 10:00:35.576256 [Byte1]: 60
1618 10:00:35.580431
1619 10:00:35.580980 Set Vref, RX VrefLevel [Byte0]: 61
1620 10:00:35.583552 [Byte1]: 61
1621 10:00:35.587804
1622 10:00:35.588305 Set Vref, RX VrefLevel [Byte0]: 62
1623 10:00:35.591307 [Byte1]: 62
1624 10:00:35.595739
1625 10:00:35.596246 Set Vref, RX VrefLevel [Byte0]: 63
1626 10:00:35.598866 [Byte1]: 63
1627 10:00:35.603284
1628 10:00:35.603690 Set Vref, RX VrefLevel [Byte0]: 64
1629 10:00:35.606163 [Byte1]: 64
1630 10:00:35.610428
1631 10:00:35.610955 Set Vref, RX VrefLevel [Byte0]: 65
1632 10:00:35.613841 [Byte1]: 65
1633 10:00:35.618123
1634 10:00:35.618660 Set Vref, RX VrefLevel [Byte0]: 66
1635 10:00:35.621381 [Byte1]: 66
1636 10:00:35.626176
1637 10:00:35.626693 Set Vref, RX VrefLevel [Byte0]: 67
1638 10:00:35.628934 [Byte1]: 67
1639 10:00:35.633677
1640 10:00:35.634185 Set Vref, RX VrefLevel [Byte0]: 68
1641 10:00:35.636870 [Byte1]: 68
1642 10:00:35.640926
1643 10:00:35.641424 Set Vref, RX VrefLevel [Byte0]: 69
1644 10:00:35.644572 [Byte1]: 69
1645 10:00:35.648834
1646 10:00:35.649337 Set Vref, RX VrefLevel [Byte0]: 70
1647 10:00:35.651872 [Byte1]: 70
1648 10:00:35.656094
1649 10:00:35.656709 Set Vref, RX VrefLevel [Byte0]: 71
1650 10:00:35.659417 [Byte1]: 71
1651 10:00:35.663821
1652 10:00:35.664326 Set Vref, RX VrefLevel [Byte0]: 72
1653 10:00:35.667053 [Byte1]: 72
1654 10:00:35.671431
1655 10:00:35.671977 Set Vref, RX VrefLevel [Byte0]: 73
1656 10:00:35.674682 [Byte1]: 73
1657 10:00:35.679169
1658 10:00:35.679693 Set Vref, RX VrefLevel [Byte0]: 74
1659 10:00:35.682257 [Byte1]: 74
1660 10:00:35.686492
1661 10:00:35.686957 Set Vref, RX VrefLevel [Byte0]: 75
1662 10:00:35.689706 [Byte1]: 75
1663 10:00:35.693986
1664 10:00:35.694393 Set Vref, RX VrefLevel [Byte0]: 76
1665 10:00:35.697657 [Byte1]: 76
1666 10:00:35.701561
1667 10:00:35.701970 Final RX Vref Byte 0 = 60 to rank0
1668 10:00:35.705322 Final RX Vref Byte 1 = 55 to rank0
1669 10:00:35.708446 Final RX Vref Byte 0 = 60 to rank1
1670 10:00:35.711331 Final RX Vref Byte 1 = 55 to rank1==
1671 10:00:35.714891 Dram Type= 6, Freq= 0, CH_1, rank 0
1672 10:00:35.721350 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1673 10:00:35.721575 ==
1674 10:00:35.721737 DQS Delay:
1675 10:00:35.721868 DQS0 = 0, DQS1 = 0
1676 10:00:35.725253 DQM Delay:
1677 10:00:35.725431 DQM0 = 81, DQM1 = 74
1678 10:00:35.725571 DQ Delay:
1679 10:00:35.728724 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =80
1680 10:00:35.732061 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
1681 10:00:35.735683 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
1682 10:00:35.739202 DQ12 =80, DQ13 =84, DQ14 =80, DQ15 =84
1683 10:00:35.739427
1684 10:00:35.739544
1685 10:00:35.749149 [DQSOSCAuto] RK0, (LSB)MR18= 0x5454, (MSB)MR19= 0x606, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
1686 10:00:35.752623 CH1 RK0: MR19=606, MR18=5454
1687 10:00:35.756171 CH1_RK0: MR19=0x606, MR18=0x5454, DQSOSC=388, MR23=63, INC=98, DEC=65
1688 10:00:35.756822
1689 10:00:35.759430 ----->DramcWriteLeveling(PI) begin...
1690 10:00:35.762567 ==
1691 10:00:35.762981 Dram Type= 6, Freq= 0, CH_1, rank 1
1692 10:00:35.769074 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1693 10:00:35.769498 ==
1694 10:00:35.772491 Write leveling (Byte 0): 28 => 28
1695 10:00:35.776074 Write leveling (Byte 1): 23 => 23
1696 10:00:35.779176 DramcWriteLeveling(PI) end<-----
1697 10:00:35.779589
1698 10:00:35.779911 ==
1699 10:00:35.782397 Dram Type= 6, Freq= 0, CH_1, rank 1
1700 10:00:35.785695 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1701 10:00:35.785989 ==
1702 10:00:35.788898 [Gating] SW mode calibration
1703 10:00:35.795563 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1704 10:00:35.798725 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1705 10:00:35.805750 0 6 0 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
1706 10:00:35.808803 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1707 10:00:35.812371 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1708 10:00:35.818888 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1709 10:00:35.822166 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1710 10:00:35.825566 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1711 10:00:35.832598 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1712 10:00:35.835787 0 6 28 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
1713 10:00:35.839017 0 7 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
1714 10:00:35.845598 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1715 10:00:35.848956 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1716 10:00:35.852575 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1717 10:00:35.859135 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1718 10:00:35.862511 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1719 10:00:35.865695 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1720 10:00:35.872403 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1721 10:00:35.876200 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1722 10:00:35.879252 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1723 10:00:35.885953 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1724 10:00:35.889141 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1725 10:00:35.892474 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1726 10:00:35.896018 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1727 10:00:35.902279 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1728 10:00:35.905841 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1729 10:00:35.909374 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1730 10:00:35.915927 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1731 10:00:35.919461 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1732 10:00:35.922378 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1733 10:00:35.929327 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1734 10:00:35.932468 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1735 10:00:35.936018 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1736 10:00:35.942366 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1737 10:00:35.945857 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1738 10:00:35.948965 Total UI for P1: 0, mck2ui 16
1739 10:00:35.952102 best dqsien dly found for B0: ( 0, 9, 28)
1740 10:00:35.955577 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1741 10:00:35.958891 Total UI for P1: 0, mck2ui 16
1742 10:00:35.962101 best dqsien dly found for B1: ( 0, 10, 0)
1743 10:00:35.965400 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1744 10:00:35.968710 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1745 10:00:35.969240
1746 10:00:35.975552 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1747 10:00:35.979176 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1748 10:00:35.982240 [Gating] SW calibration Done
1749 10:00:35.982798 ==
1750 10:00:35.985653 Dram Type= 6, Freq= 0, CH_1, rank 1
1751 10:00:35.988617 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1752 10:00:35.989172 ==
1753 10:00:35.989540 RX Vref Scan: 0
1754 10:00:35.989874
1755 10:00:35.992001 RX Vref 0 -> 0, step: 1
1756 10:00:35.992457
1757 10:00:35.995520 RX Delay -130 -> 252, step: 16
1758 10:00:35.999268 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1759 10:00:36.002618 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1760 10:00:36.008757 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1761 10:00:36.012255 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1762 10:00:36.015322 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1763 10:00:36.018710 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1764 10:00:36.021957 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1765 10:00:36.025655 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1766 10:00:36.032259 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1767 10:00:36.035746 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1768 10:00:36.039050 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1769 10:00:36.042261 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1770 10:00:36.048919 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1771 10:00:36.052246 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1772 10:00:36.055684 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1773 10:00:36.058838 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1774 10:00:36.059296 ==
1775 10:00:36.062322 Dram Type= 6, Freq= 0, CH_1, rank 1
1776 10:00:36.065557 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1777 10:00:36.069082 ==
1778 10:00:36.069635 DQS Delay:
1779 10:00:36.070001 DQS0 = 0, DQS1 = 0
1780 10:00:36.072118 DQM Delay:
1781 10:00:36.072627 DQM0 = 86, DQM1 = 73
1782 10:00:36.075818 DQ Delay:
1783 10:00:36.076369 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1784 10:00:36.079027 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1785 10:00:36.082287 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =69
1786 10:00:36.085632 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1787 10:00:36.086183
1788 10:00:36.089070
1789 10:00:36.089537 ==
1790 10:00:36.092352 Dram Type= 6, Freq= 0, CH_1, rank 1
1791 10:00:36.095901 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1792 10:00:36.096455 ==
1793 10:00:36.096937
1794 10:00:36.097279
1795 10:00:36.099213 TX Vref Scan disable
1796 10:00:36.099760 == TX Byte 0 ==
1797 10:00:36.105889 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1798 10:00:36.109141 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1799 10:00:36.109605 == TX Byte 1 ==
1800 10:00:36.115734 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1801 10:00:36.119012 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1802 10:00:36.119471 ==
1803 10:00:36.122143 Dram Type= 6, Freq= 0, CH_1, rank 1
1804 10:00:36.125770 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1805 10:00:36.126321 ==
1806 10:00:36.140051 TX Vref=22, minBit 0, minWin=27, winSum=445
1807 10:00:36.142970 TX Vref=24, minBit 0, minWin=27, winSum=451
1808 10:00:36.146568 TX Vref=26, minBit 0, minWin=28, winSum=456
1809 10:00:36.149676 TX Vref=28, minBit 0, minWin=28, winSum=457
1810 10:00:36.152928 TX Vref=30, minBit 9, minWin=27, winSum=456
1811 10:00:36.156268 TX Vref=32, minBit 0, minWin=28, winSum=453
1812 10:00:36.163305 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 28
1813 10:00:36.163859
1814 10:00:36.166436 Final TX Range 1 Vref 28
1815 10:00:36.166897
1816 10:00:36.167256 ==
1817 10:00:36.169643 Dram Type= 6, Freq= 0, CH_1, rank 1
1818 10:00:36.172902 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1819 10:00:36.173363 ==
1820 10:00:36.173724
1821 10:00:36.174051
1822 10:00:36.176229 TX Vref Scan disable
1823 10:00:36.179853 == TX Byte 0 ==
1824 10:00:36.182837 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1825 10:00:36.186519 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1826 10:00:36.189622 == TX Byte 1 ==
1827 10:00:36.192978 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1828 10:00:36.199679 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1829 10:00:36.200245
1830 10:00:36.200671 [DATLAT]
1831 10:00:36.201019 Freq=800, CH1 RK1
1832 10:00:36.201346
1833 10:00:36.202771 DATLAT Default: 0x9
1834 10:00:36.203225 0, 0xFFFF, sum = 0
1835 10:00:36.206385 1, 0xFFFF, sum = 0
1836 10:00:36.206942 2, 0xFFFF, sum = 0
1837 10:00:36.209190 3, 0xFFFF, sum = 0
1838 10:00:36.212929 4, 0xFFFF, sum = 0
1839 10:00:36.213480 5, 0xFFFF, sum = 0
1840 10:00:36.216355 6, 0xFFFF, sum = 0
1841 10:00:36.217004 7, 0xFFFF, sum = 0
1842 10:00:36.219354 8, 0x0, sum = 1
1843 10:00:36.219875 9, 0x0, sum = 2
1844 10:00:36.220249 10, 0x0, sum = 3
1845 10:00:36.222616 11, 0x0, sum = 4
1846 10:00:36.223092 best_step = 9
1847 10:00:36.223453
1848 10:00:36.223782 ==
1849 10:00:36.226713 Dram Type= 6, Freq= 0, CH_1, rank 1
1850 10:00:36.232751 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1851 10:00:36.233316 ==
1852 10:00:36.233679 RX Vref Scan: 0
1853 10:00:36.234012
1854 10:00:36.236237 RX Vref 0 -> 0, step: 1
1855 10:00:36.236847
1856 10:00:36.239392 RX Delay -111 -> 252, step: 8
1857 10:00:36.242664 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1858 10:00:36.246266 iDelay=217, Bit 1, Center 80 (-39 ~ 200) 240
1859 10:00:36.253072 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1860 10:00:36.255933 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1861 10:00:36.259208 iDelay=217, Bit 4, Center 80 (-39 ~ 200) 240
1862 10:00:36.262786 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1863 10:00:36.265712 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1864 10:00:36.272612 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1865 10:00:36.275905 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1866 10:00:36.279727 iDelay=217, Bit 9, Center 64 (-55 ~ 184) 240
1867 10:00:36.282777 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1868 10:00:36.286076 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1869 10:00:36.292624 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1870 10:00:36.296033 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1871 10:00:36.299307 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1872 10:00:36.302619 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1873 10:00:36.303085 ==
1874 10:00:36.305865 Dram Type= 6, Freq= 0, CH_1, rank 1
1875 10:00:36.312411 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1876 10:00:36.313026 ==
1877 10:00:36.313395 DQS Delay:
1878 10:00:36.315845 DQS0 = 0, DQS1 = 0
1879 10:00:36.316306 DQM Delay:
1880 10:00:36.316727 DQM0 = 84, DQM1 = 75
1881 10:00:36.318824 DQ Delay:
1882 10:00:36.322280 DQ0 =84, DQ1 =80, DQ2 =76, DQ3 =84
1883 10:00:36.325745 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =80
1884 10:00:36.329220 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
1885 10:00:36.332776 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1886 10:00:36.333350
1887 10:00:36.333719
1888 10:00:36.339419 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e3e, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1889 10:00:36.342437 CH1 RK1: MR19=606, MR18=3E3E
1890 10:00:36.348901 CH1_RK1: MR19=0x606, MR18=0x3E3E, DQSOSC=394, MR23=63, INC=95, DEC=63
1891 10:00:36.352177 [RxdqsGatingPostProcess] freq 800
1892 10:00:36.355760 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1893 10:00:36.358894 Pre-setting of DQS Precalculation
1894 10:00:36.365694 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1895 10:00:36.372308 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1896 10:00:36.379317 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1897 10:00:36.379884
1898 10:00:36.380245
1899 10:00:36.382347 [Calibration Summary] 1600 Mbps
1900 10:00:36.382899 CH 0, Rank 0
1901 10:00:36.385345 SW Impedance : PASS
1902 10:00:36.389017 DUTY Scan : NO K
1903 10:00:36.389572 ZQ Calibration : PASS
1904 10:00:36.392262 Jitter Meter : NO K
1905 10:00:36.395575 CBT Training : PASS
1906 10:00:36.396127 Write leveling : PASS
1907 10:00:36.398965 RX DQS gating : PASS
1908 10:00:36.399514 RX DQ/DQS(RDDQC) : PASS
1909 10:00:36.402195 TX DQ/DQS : PASS
1910 10:00:36.405457 RX DATLAT : PASS
1911 10:00:36.406279 RX DQ/DQS(Engine): PASS
1912 10:00:36.408783 TX OE : NO K
1913 10:00:36.409239 All Pass.
1914 10:00:36.409596
1915 10:00:36.412386 CH 0, Rank 1
1916 10:00:36.412989 SW Impedance : PASS
1917 10:00:36.415597 DUTY Scan : NO K
1918 10:00:36.418802 ZQ Calibration : PASS
1919 10:00:36.419258 Jitter Meter : NO K
1920 10:00:36.422296 CBT Training : PASS
1921 10:00:36.425871 Write leveling : PASS
1922 10:00:36.426420 RX DQS gating : PASS
1923 10:00:36.428700 RX DQ/DQS(RDDQC) : PASS
1924 10:00:36.432096 TX DQ/DQS : PASS
1925 10:00:36.432700 RX DATLAT : PASS
1926 10:00:36.435736 RX DQ/DQS(Engine): PASS
1927 10:00:36.436295 TX OE : NO K
1928 10:00:36.439045 All Pass.
1929 10:00:36.439602
1930 10:00:36.439964 CH 1, Rank 0
1931 10:00:36.442060 SW Impedance : PASS
1932 10:00:36.442517 DUTY Scan : NO K
1933 10:00:36.445392 ZQ Calibration : PASS
1934 10:00:36.448751 Jitter Meter : NO K
1935 10:00:36.449211 CBT Training : PASS
1936 10:00:36.451989 Write leveling : PASS
1937 10:00:36.455769 RX DQS gating : PASS
1938 10:00:36.456327 RX DQ/DQS(RDDQC) : PASS
1939 10:00:36.458759 TX DQ/DQS : PASS
1940 10:00:36.462109 RX DATLAT : PASS
1941 10:00:36.462566 RX DQ/DQS(Engine): PASS
1942 10:00:36.465731 TX OE : NO K
1943 10:00:36.466192 All Pass.
1944 10:00:36.466595
1945 10:00:36.468847 CH 1, Rank 1
1946 10:00:36.469305 SW Impedance : PASS
1947 10:00:36.471966 DUTY Scan : NO K
1948 10:00:36.475691 ZQ Calibration : PASS
1949 10:00:36.476250 Jitter Meter : NO K
1950 10:00:36.478998 CBT Training : PASS
1951 10:00:36.482063 Write leveling : PASS
1952 10:00:36.482523 RX DQS gating : PASS
1953 10:00:36.485188 RX DQ/DQS(RDDQC) : PASS
1954 10:00:36.485643 TX DQ/DQS : PASS
1955 10:00:36.488768 RX DATLAT : PASS
1956 10:00:36.492271 RX DQ/DQS(Engine): PASS
1957 10:00:36.492900 TX OE : NO K
1958 10:00:36.495663 All Pass.
1959 10:00:36.496299
1960 10:00:36.496723 DramC Write-DBI off
1961 10:00:36.499102 PER_BANK_REFRESH: Hybrid Mode
1962 10:00:36.502085 TX_TRACKING: ON
1963 10:00:36.505644 [GetDramInforAfterCalByMRR] Vendor 6.
1964 10:00:36.508631 [GetDramInforAfterCalByMRR] Revision 606.
1965 10:00:36.512139 [GetDramInforAfterCalByMRR] Revision 2 0.
1966 10:00:36.512751 MR0 0x3939
1967 10:00:36.513127 MR8 0x1111
1968 10:00:36.518552 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1969 10:00:36.519131
1970 10:00:36.519552 MR0 0x3939
1971 10:00:36.519899 MR8 0x1111
1972 10:00:36.522256 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1973 10:00:36.522716
1974 10:00:36.532301 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1975 10:00:36.535833 [FAST_K] Save calibration result to emmc
1976 10:00:36.538646 [FAST_K] Save calibration result to emmc
1977 10:00:36.541997 dram_init: config_dvfs: 1
1978 10:00:36.545136 dramc_set_vcore_voltage set vcore to 662500
1979 10:00:36.548953 Read voltage for 1200, 2
1980 10:00:36.549413 Vio18 = 0
1981 10:00:36.549774 Vcore = 662500
1982 10:00:36.551976 Vdram = 0
1983 10:00:36.552430 Vddq = 0
1984 10:00:36.552844 Vmddr = 0
1985 10:00:36.558726 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1986 10:00:36.561972 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1987 10:00:36.565466 MEM_TYPE=3, freq_sel=15
1988 10:00:36.568609 sv_algorithm_assistance_LP4_1600
1989 10:00:36.572213 ============ PULL DRAM RESETB DOWN ============
1990 10:00:36.575436 ========== PULL DRAM RESETB DOWN end =========
1991 10:00:36.581936 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1992 10:00:36.585472 ===================================
1993 10:00:36.588895 LPDDR4 DRAM CONFIGURATION
1994 10:00:36.592057 ===================================
1995 10:00:36.592650 EX_ROW_EN[0] = 0x0
1996 10:00:36.595477 EX_ROW_EN[1] = 0x0
1997 10:00:36.596021 LP4Y_EN = 0x0
1998 10:00:36.598755 WORK_FSP = 0x0
1999 10:00:36.599301 WL = 0x4
2000 10:00:36.601855 RL = 0x4
2001 10:00:36.602309 BL = 0x2
2002 10:00:36.605430 RPST = 0x0
2003 10:00:36.605976 RD_PRE = 0x0
2004 10:00:36.608486 WR_PRE = 0x1
2005 10:00:36.609116 WR_PST = 0x0
2006 10:00:36.611927 DBI_WR = 0x0
2007 10:00:36.612478 DBI_RD = 0x0
2008 10:00:36.615262 OTF = 0x1
2009 10:00:36.618411 ===================================
2010 10:00:36.621777 ===================================
2011 10:00:36.622322 ANA top config
2012 10:00:36.625352 ===================================
2013 10:00:36.628707 DLL_ASYNC_EN = 0
2014 10:00:36.632020 ALL_SLAVE_EN = 0
2015 10:00:36.635373 NEW_RANK_MODE = 1
2016 10:00:36.635927 DLL_IDLE_MODE = 1
2017 10:00:36.638299 LP45_APHY_COMB_EN = 1
2018 10:00:36.641994 TX_ODT_DIS = 1
2019 10:00:36.645275 NEW_8X_MODE = 1
2020 10:00:36.648684 ===================================
2021 10:00:36.651827 ===================================
2022 10:00:36.655016 data_rate = 2400
2023 10:00:36.655476 CKR = 1
2024 10:00:36.658586 DQ_P2S_RATIO = 8
2025 10:00:36.661681 ===================================
2026 10:00:36.665006 CA_P2S_RATIO = 8
2027 10:00:36.668497 DQ_CA_OPEN = 0
2028 10:00:36.671962 DQ_SEMI_OPEN = 0
2029 10:00:36.675276 CA_SEMI_OPEN = 0
2030 10:00:36.676053 CA_FULL_RATE = 0
2031 10:00:36.678343 DQ_CKDIV4_EN = 0
2032 10:00:36.681798 CA_CKDIV4_EN = 0
2033 10:00:36.685069 CA_PREDIV_EN = 0
2034 10:00:36.688383 PH8_DLY = 17
2035 10:00:36.691612 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2036 10:00:36.692070 DQ_AAMCK_DIV = 4
2037 10:00:36.695081 CA_AAMCK_DIV = 4
2038 10:00:36.698394 CA_ADMCK_DIV = 4
2039 10:00:36.701596 DQ_TRACK_CA_EN = 0
2040 10:00:36.705074 CA_PICK = 1200
2041 10:00:36.708258 CA_MCKIO = 1200
2042 10:00:36.711685 MCKIO_SEMI = 0
2043 10:00:36.712099 PLL_FREQ = 2366
2044 10:00:36.715173 DQ_UI_PI_RATIO = 32
2045 10:00:36.718184 CA_UI_PI_RATIO = 0
2046 10:00:36.721801 ===================================
2047 10:00:36.724850 ===================================
2048 10:00:36.728351 memory_type:LPDDR4
2049 10:00:36.728909 GP_NUM : 10
2050 10:00:36.731765 SRAM_EN : 1
2051 10:00:36.735073 MD32_EN : 0
2052 10:00:36.738270 ===================================
2053 10:00:36.738792 [ANA_INIT] >>>>>>>>>>>>>>
2054 10:00:36.741332 <<<<<< [CONFIGURE PHASE]: ANA_TX
2055 10:00:36.744679 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2056 10:00:36.748270 ===================================
2057 10:00:36.751515 data_rate = 2400,PCW = 0X5b00
2058 10:00:36.754934 ===================================
2059 10:00:36.757820 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2060 10:00:36.764644 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2061 10:00:36.767815 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2062 10:00:36.774804 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2063 10:00:36.778235 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2064 10:00:36.781589 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2065 10:00:36.785110 [ANA_INIT] flow start
2066 10:00:36.785657 [ANA_INIT] PLL >>>>>>>>
2067 10:00:36.788101 [ANA_INIT] PLL <<<<<<<<
2068 10:00:36.791020 [ANA_INIT] MIDPI >>>>>>>>
2069 10:00:36.791484 [ANA_INIT] MIDPI <<<<<<<<
2070 10:00:36.794642 [ANA_INIT] DLL >>>>>>>>
2071 10:00:36.797769 [ANA_INIT] DLL <<<<<<<<
2072 10:00:36.798226 [ANA_INIT] flow end
2073 10:00:36.804661 ============ LP4 DIFF to SE enter ============
2074 10:00:36.807876 ============ LP4 DIFF to SE exit ============
2075 10:00:36.808430 [ANA_INIT] <<<<<<<<<<<<<
2076 10:00:36.811247 [Flow] Enable top DCM control >>>>>
2077 10:00:36.814624 [Flow] Enable top DCM control <<<<<
2078 10:00:36.817841 Enable DLL master slave shuffle
2079 10:00:36.824310 ==============================================================
2080 10:00:36.827908 Gating Mode config
2081 10:00:36.831313 ==============================================================
2082 10:00:36.834619 Config description:
2083 10:00:36.844880 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2084 10:00:36.851091 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2085 10:00:36.854396 SELPH_MODE 0: By rank 1: By Phase
2086 10:00:36.861108 ==============================================================
2087 10:00:36.864088 GAT_TRACK_EN = 1
2088 10:00:36.867744 RX_GATING_MODE = 2
2089 10:00:36.868350 RX_GATING_TRACK_MODE = 2
2090 10:00:36.870793 SELPH_MODE = 1
2091 10:00:36.874387 PICG_EARLY_EN = 1
2092 10:00:36.877706 VALID_LAT_VALUE = 1
2093 10:00:36.884469 ==============================================================
2094 10:00:36.887752 Enter into Gating configuration >>>>
2095 10:00:36.891204 Exit from Gating configuration <<<<
2096 10:00:36.894424 Enter into DVFS_PRE_config >>>>>
2097 10:00:36.904619 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2098 10:00:36.907600 Exit from DVFS_PRE_config <<<<<
2099 10:00:36.910995 Enter into PICG configuration >>>>
2100 10:00:36.914350 Exit from PICG configuration <<<<
2101 10:00:36.917219 [RX_INPUT] configuration >>>>>
2102 10:00:36.920632 [RX_INPUT] configuration <<<<<
2103 10:00:36.924200 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2104 10:00:36.930809 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2105 10:00:36.937440 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2106 10:00:36.944145 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2107 10:00:36.947535 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2108 10:00:36.954255 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2109 10:00:36.957895 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2110 10:00:36.964098 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2111 10:00:36.967448 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2112 10:00:36.970996 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2113 10:00:36.974068 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2114 10:00:36.980993 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2115 10:00:36.984118 ===================================
2116 10:00:36.984717 LPDDR4 DRAM CONFIGURATION
2117 10:00:36.987832 ===================================
2118 10:00:36.991101 EX_ROW_EN[0] = 0x0
2119 10:00:36.994397 EX_ROW_EN[1] = 0x0
2120 10:00:36.994961 LP4Y_EN = 0x0
2121 10:00:36.997660 WORK_FSP = 0x0
2122 10:00:36.998115 WL = 0x4
2123 10:00:37.000819 RL = 0x4
2124 10:00:37.001272 BL = 0x2
2125 10:00:37.004405 RPST = 0x0
2126 10:00:37.005009 RD_PRE = 0x0
2127 10:00:37.007601 WR_PRE = 0x1
2128 10:00:37.008153 WR_PST = 0x0
2129 10:00:37.011057 DBI_WR = 0x0
2130 10:00:37.011629 DBI_RD = 0x0
2131 10:00:37.014299 OTF = 0x1
2132 10:00:37.017301 ===================================
2133 10:00:37.020978 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2134 10:00:37.024276 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2135 10:00:37.030982 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2136 10:00:37.034250 ===================================
2137 10:00:37.034813 LPDDR4 DRAM CONFIGURATION
2138 10:00:37.037893 ===================================
2139 10:00:37.040885 EX_ROW_EN[0] = 0x10
2140 10:00:37.041442 EX_ROW_EN[1] = 0x0
2141 10:00:37.044190 LP4Y_EN = 0x0
2142 10:00:37.044799 WORK_FSP = 0x0
2143 10:00:37.047711 WL = 0x4
2144 10:00:37.050984 RL = 0x4
2145 10:00:37.051541 BL = 0x2
2146 10:00:37.054309 RPST = 0x0
2147 10:00:37.054870 RD_PRE = 0x0
2148 10:00:37.058028 WR_PRE = 0x1
2149 10:00:37.058586 WR_PST = 0x0
2150 10:00:37.060775 DBI_WR = 0x0
2151 10:00:37.061234 DBI_RD = 0x0
2152 10:00:37.064059 OTF = 0x1
2153 10:00:37.067307 ===================================
2154 10:00:37.070954 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2155 10:00:37.074125 ==
2156 10:00:37.077384 Dram Type= 6, Freq= 0, CH_0, rank 0
2157 10:00:37.080930 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2158 10:00:37.081537 ==
2159 10:00:37.084163 [Duty_Offset_Calibration]
2160 10:00:37.084780 B0:0 B1:2 CA:1
2161 10:00:37.085148
2162 10:00:37.087633 [DutyScan_Calibration_Flow] k_type=0
2163 10:00:37.096959
2164 10:00:37.097565 ==CLK 0==
2165 10:00:37.100033 Final CLK duty delay cell = 0
2166 10:00:37.103889 [0] MAX Duty = 5093%(X100), DQS PI = 12
2167 10:00:37.107204 [0] MIN Duty = 4938%(X100), DQS PI = 52
2168 10:00:37.107762 [0] AVG Duty = 5015%(X100)
2169 10:00:37.110331
2170 10:00:37.113747 CH0 CLK Duty spec in!! Max-Min= 155%
2171 10:00:37.116935 [DutyScan_Calibration_Flow] ====Done====
2172 10:00:37.117493
2173 10:00:37.119973 [DutyScan_Calibration_Flow] k_type=1
2174 10:00:37.136370
2175 10:00:37.136993 ==DQS 0 ==
2176 10:00:37.139586 Final DQS duty delay cell = 0
2177 10:00:37.142833 [0] MAX Duty = 5125%(X100), DQS PI = 28
2178 10:00:37.146381 [0] MIN Duty = 5031%(X100), DQS PI = 6
2179 10:00:37.146946 [0] AVG Duty = 5078%(X100)
2180 10:00:37.149810
2181 10:00:37.150363 ==DQS 1 ==
2182 10:00:37.152955 Final DQS duty delay cell = 0
2183 10:00:37.156396 [0] MAX Duty = 5062%(X100), DQS PI = 58
2184 10:00:37.159481 [0] MIN Duty = 4906%(X100), DQS PI = 14
2185 10:00:37.162923 [0] AVG Duty = 4984%(X100)
2186 10:00:37.163482
2187 10:00:37.166033 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2188 10:00:37.166492
2189 10:00:37.169349 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2190 10:00:37.172745 [DutyScan_Calibration_Flow] ====Done====
2191 10:00:37.173299
2192 10:00:37.176211 [DutyScan_Calibration_Flow] k_type=3
2193 10:00:37.193238
2194 10:00:37.193793 ==DQM 0 ==
2195 10:00:37.196949 Final DQM duty delay cell = 0
2196 10:00:37.200154 [0] MAX Duty = 5156%(X100), DQS PI = 20
2197 10:00:37.203565 [0] MIN Duty = 4969%(X100), DQS PI = 42
2198 10:00:37.206538 [0] AVG Duty = 5062%(X100)
2199 10:00:37.207083
2200 10:00:37.207445 ==DQM 1 ==
2201 10:00:37.209890 Final DQM duty delay cell = 4
2202 10:00:37.213384 [4] MAX Duty = 5187%(X100), DQS PI = 54
2203 10:00:37.216856 [4] MIN Duty = 5000%(X100), DQS PI = 18
2204 10:00:37.219904 [4] AVG Duty = 5093%(X100)
2205 10:00:37.220362
2206 10:00:37.223508 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2207 10:00:37.224060
2208 10:00:37.226848 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2209 10:00:37.230144 [DutyScan_Calibration_Flow] ====Done====
2210 10:00:37.230694
2211 10:00:37.233466 [DutyScan_Calibration_Flow] k_type=2
2212 10:00:37.248408
2213 10:00:37.249006 ==DQ 0 ==
2214 10:00:37.252073 Final DQ duty delay cell = -4
2215 10:00:37.255025 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2216 10:00:37.258460 [-4] MIN Duty = 4813%(X100), DQS PI = 54
2217 10:00:37.262105 [-4] AVG Duty = 4937%(X100)
2218 10:00:37.262651
2219 10:00:37.263016 ==DQ 1 ==
2220 10:00:37.265147 Final DQ duty delay cell = -4
2221 10:00:37.268405 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2222 10:00:37.271908 [-4] MIN Duty = 4876%(X100), DQS PI = 0
2223 10:00:37.274957 [-4] AVG Duty = 4969%(X100)
2224 10:00:37.275505
2225 10:00:37.278440 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2226 10:00:37.278992
2227 10:00:37.282176 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2228 10:00:37.285047 [DutyScan_Calibration_Flow] ====Done====
2229 10:00:37.285508 ==
2230 10:00:37.288356 Dram Type= 6, Freq= 0, CH_1, rank 0
2231 10:00:37.291868 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2232 10:00:37.292432 ==
2233 10:00:37.295376 [Duty_Offset_Calibration]
2234 10:00:37.295918 B0:0 B1:5 CA:-5
2235 10:00:37.296283
2236 10:00:37.298285 [DutyScan_Calibration_Flow] k_type=0
2237 10:00:37.309206
2238 10:00:37.309748 ==CLK 0==
2239 10:00:37.312198 Final CLK duty delay cell = 0
2240 10:00:37.315702 [0] MAX Duty = 5125%(X100), DQS PI = 16
2241 10:00:37.319212 [0] MIN Duty = 4875%(X100), DQS PI = 46
2242 10:00:37.319719 [0] AVG Duty = 5000%(X100)
2243 10:00:37.322413
2244 10:00:37.325348 CH1 CLK Duty spec in!! Max-Min= 250%
2245 10:00:37.329049 [DutyScan_Calibration_Flow] ====Done====
2246 10:00:37.329594
2247 10:00:37.332330 [DutyScan_Calibration_Flow] k_type=1
2248 10:00:37.347538
2249 10:00:37.348081 ==DQS 0 ==
2250 10:00:37.350812 Final DQS duty delay cell = 0
2251 10:00:37.353994 [0] MAX Duty = 5125%(X100), DQS PI = 16
2252 10:00:37.357410 [0] MIN Duty = 4875%(X100), DQS PI = 40
2253 10:00:37.358049 [0] AVG Duty = 5000%(X100)
2254 10:00:37.360830
2255 10:00:37.361282 ==DQS 1 ==
2256 10:00:37.364437 Final DQS duty delay cell = -4
2257 10:00:37.367445 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2258 10:00:37.370852 [-4] MIN Duty = 4876%(X100), DQS PI = 44
2259 10:00:37.374042 [-4] AVG Duty = 4938%(X100)
2260 10:00:37.374512
2261 10:00:37.377773 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2262 10:00:37.378318
2263 10:00:37.381090 CH1 DQS 1 Duty spec in!! Max-Min= 124%
2264 10:00:37.384343 [DutyScan_Calibration_Flow] ====Done====
2265 10:00:37.384934
2266 10:00:37.387338 [DutyScan_Calibration_Flow] k_type=3
2267 10:00:37.402684
2268 10:00:37.403224 ==DQM 0 ==
2269 10:00:37.406068 Final DQM duty delay cell = -4
2270 10:00:37.409411 [-4] MAX Duty = 5094%(X100), DQS PI = 32
2271 10:00:37.412963 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2272 10:00:37.416072 [-4] AVG Duty = 4969%(X100)
2273 10:00:37.416681
2274 10:00:37.417050 ==DQM 1 ==
2275 10:00:37.419272 Final DQM duty delay cell = -4
2276 10:00:37.422548 [-4] MAX Duty = 5094%(X100), DQS PI = 20
2277 10:00:37.425897 [-4] MIN Duty = 4906%(X100), DQS PI = 42
2278 10:00:37.429415 [-4] AVG Duty = 5000%(X100)
2279 10:00:37.429965
2280 10:00:37.432943 CH1 DQM 0 Duty spec in!! Max-Min= 250%
2281 10:00:37.433489
2282 10:00:37.436479 CH1 DQM 1 Duty spec in!! Max-Min= 188%
2283 10:00:37.439433 [DutyScan_Calibration_Flow] ====Done====
2284 10:00:37.439979
2285 10:00:37.442418 [DutyScan_Calibration_Flow] k_type=2
2286 10:00:37.459977
2287 10:00:37.460569 ==DQ 0 ==
2288 10:00:37.463280 Final DQ duty delay cell = 0
2289 10:00:37.466403 [0] MAX Duty = 5062%(X100), DQS PI = 0
2290 10:00:37.469779 [0] MIN Duty = 4969%(X100), DQS PI = 44
2291 10:00:37.470234 [0] AVG Duty = 5015%(X100)
2292 10:00:37.470592
2293 10:00:37.473279 ==DQ 1 ==
2294 10:00:37.476315 Final DQ duty delay cell = 0
2295 10:00:37.479874 [0] MAX Duty = 5031%(X100), DQS PI = 8
2296 10:00:37.483101 [0] MIN Duty = 4907%(X100), DQS PI = 0
2297 10:00:37.483552 [0] AVG Duty = 4969%(X100)
2298 10:00:37.483904
2299 10:00:37.486434 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2300 10:00:37.486884
2301 10:00:37.489807 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2302 10:00:37.493194 [DutyScan_Calibration_Flow] ====Done====
2303 10:00:37.498457 nWR fixed to 30
2304 10:00:37.502016 [ModeRegInit_LP4] CH0 RK0
2305 10:00:37.502559 [ModeRegInit_LP4] CH0 RK1
2306 10:00:37.505981 [ModeRegInit_LP4] CH1 RK0
2307 10:00:37.508769 [ModeRegInit_LP4] CH1 RK1
2308 10:00:37.509317 match AC timing 6
2309 10:00:37.515514 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2310 10:00:37.518833 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2311 10:00:37.521927 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2312 10:00:37.528996 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2313 10:00:37.532171 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2314 10:00:37.532742 ==
2315 10:00:37.535485 Dram Type= 6, Freq= 0, CH_0, rank 0
2316 10:00:37.538981 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2317 10:00:37.539531 ==
2318 10:00:37.545273 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2319 10:00:37.551974 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2320 10:00:37.559400 [CA 0] Center 39 (9~70) winsize 62
2321 10:00:37.562908 [CA 1] Center 39 (9~70) winsize 62
2322 10:00:37.565782 [CA 2] Center 36 (5~67) winsize 63
2323 10:00:37.569145 [CA 3] Center 35 (5~66) winsize 62
2324 10:00:37.572760 [CA 4] Center 34 (3~65) winsize 63
2325 10:00:37.576154 [CA 5] Center 33 (3~64) winsize 62
2326 10:00:37.576744
2327 10:00:37.579138 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2328 10:00:37.579583
2329 10:00:37.582884 [CATrainingPosCal] consider 1 rank data
2330 10:00:37.585846 u2DelayCellTimex100 = 270/100 ps
2331 10:00:37.589363 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2332 10:00:37.592541 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2333 10:00:37.599395 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2334 10:00:37.602652 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2335 10:00:37.606306 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2336 10:00:37.609215 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2337 10:00:37.609667
2338 10:00:37.612819 CA PerBit enable=1, Macro0, CA PI delay=33
2339 10:00:37.613367
2340 10:00:37.616036 [CBTSetCACLKResult] CA Dly = 33
2341 10:00:37.616643 CS Dly: 7 (0~38)
2342 10:00:37.619442 ==
2343 10:00:37.620012 Dram Type= 6, Freq= 0, CH_0, rank 1
2344 10:00:37.626083 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2345 10:00:37.626636 ==
2346 10:00:37.629428 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2347 10:00:37.636004 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2348 10:00:37.645107 [CA 0] Center 39 (8~70) winsize 63
2349 10:00:37.648460 [CA 1] Center 39 (8~70) winsize 63
2350 10:00:37.651715 [CA 2] Center 36 (5~67) winsize 63
2351 10:00:37.655013 [CA 3] Center 35 (4~66) winsize 63
2352 10:00:37.658272 [CA 4] Center 33 (3~64) winsize 62
2353 10:00:37.661688 [CA 5] Center 33 (3~64) winsize 62
2354 10:00:37.662229
2355 10:00:37.665207 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2356 10:00:37.665753
2357 10:00:37.668424 [CATrainingPosCal] consider 2 rank data
2358 10:00:37.671662 u2DelayCellTimex100 = 270/100 ps
2359 10:00:37.675036 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2360 10:00:37.678261 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2361 10:00:37.684968 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2362 10:00:37.688265 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2363 10:00:37.691483 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2364 10:00:37.694894 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2365 10:00:37.695439
2366 10:00:37.698222 CA PerBit enable=1, Macro0, CA PI delay=33
2367 10:00:37.698820
2368 10:00:37.701343 [CBTSetCACLKResult] CA Dly = 33
2369 10:00:37.701795 CS Dly: 7 (0~39)
2370 10:00:37.702152
2371 10:00:37.704917 ----->DramcWriteLeveling(PI) begin...
2372 10:00:37.708381 ==
2373 10:00:37.711625 Dram Type= 6, Freq= 0, CH_0, rank 0
2374 10:00:37.715047 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2375 10:00:37.715592 ==
2376 10:00:37.717964 Write leveling (Byte 0): 27 => 27
2377 10:00:37.721252 Write leveling (Byte 1): 25 => 25
2378 10:00:37.724849 DramcWriteLeveling(PI) end<-----
2379 10:00:37.725452
2380 10:00:37.725895 ==
2381 10:00:37.728264 Dram Type= 6, Freq= 0, CH_0, rank 0
2382 10:00:37.731430 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2383 10:00:37.731971 ==
2384 10:00:37.734719 [Gating] SW mode calibration
2385 10:00:37.741495 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2386 10:00:37.748113 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2387 10:00:37.751220 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2388 10:00:37.754622 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2389 10:00:37.757970 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2390 10:00:37.764958 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2391 10:00:37.768348 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2392 10:00:37.771091 0 11 20 | B1->B0 | 3030 2d2d | 1 0 | (1 0) (0 1)
2393 10:00:37.777735 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2394 10:00:37.781212 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2395 10:00:37.784445 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2396 10:00:37.791333 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2397 10:00:37.794489 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2398 10:00:37.798254 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2399 10:00:37.804852 0 12 16 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2400 10:00:37.807914 0 12 20 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2401 10:00:37.811366 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2402 10:00:37.817977 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2403 10:00:37.821494 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2404 10:00:37.824637 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2405 10:00:37.831194 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2406 10:00:37.835079 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2407 10:00:37.838195 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2408 10:00:37.844686 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2409 10:00:37.848316 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2410 10:00:37.851702 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2411 10:00:37.854876 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2412 10:00:37.861330 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2413 10:00:37.864785 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2414 10:00:37.868296 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2415 10:00:37.874691 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2416 10:00:37.878140 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2417 10:00:37.881371 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2418 10:00:37.887952 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2419 10:00:37.891502 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2420 10:00:37.894661 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2421 10:00:37.901250 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2422 10:00:37.904681 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2423 10:00:37.908113 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2424 10:00:37.914827 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2425 10:00:37.917810 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2426 10:00:37.921162 Total UI for P1: 0, mck2ui 16
2427 10:00:37.924666 best dqsien dly found for B0: ( 0, 15, 18)
2428 10:00:37.927972 Total UI for P1: 0, mck2ui 16
2429 10:00:37.931352 best dqsien dly found for B1: ( 0, 15, 18)
2430 10:00:37.934445 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2431 10:00:37.937750 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2432 10:00:37.938304
2433 10:00:37.941296 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2434 10:00:37.944343 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2435 10:00:37.947815 [Gating] SW calibration Done
2436 10:00:37.948419 ==
2437 10:00:37.950923 Dram Type= 6, Freq= 0, CH_0, rank 0
2438 10:00:37.957438 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2439 10:00:37.957985 ==
2440 10:00:37.958350 RX Vref Scan: 0
2441 10:00:37.958680
2442 10:00:37.960687 RX Vref 0 -> 0, step: 1
2443 10:00:37.961142
2444 10:00:37.964336 RX Delay -40 -> 252, step: 8
2445 10:00:37.967659 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2446 10:00:37.970811 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2447 10:00:37.974034 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2448 10:00:37.977301 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2449 10:00:37.984166 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2450 10:00:37.987449 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2451 10:00:37.990757 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2452 10:00:37.994149 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2453 10:00:37.997217 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2454 10:00:38.003955 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2455 10:00:38.007339 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2456 10:00:38.010649 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2457 10:00:38.014074 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2458 10:00:38.017466 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2459 10:00:38.024345 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2460 10:00:38.027242 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2461 10:00:38.027698 ==
2462 10:00:38.030789 Dram Type= 6, Freq= 0, CH_0, rank 0
2463 10:00:38.033896 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2464 10:00:38.034355 ==
2465 10:00:38.037632 DQS Delay:
2466 10:00:38.038181 DQS0 = 0, DQS1 = 0
2467 10:00:38.038546 DQM Delay:
2468 10:00:38.040769 DQM0 = 115, DQM1 = 106
2469 10:00:38.041309 DQ Delay:
2470 10:00:38.044338 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2471 10:00:38.047436 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2472 10:00:38.050485 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2473 10:00:38.057468 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2474 10:00:38.058010
2475 10:00:38.058371
2476 10:00:38.058702 ==
2477 10:00:38.061001 Dram Type= 6, Freq= 0, CH_0, rank 0
2478 10:00:38.064368 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2479 10:00:38.064979 ==
2480 10:00:38.065348
2481 10:00:38.065680
2482 10:00:38.067123 TX Vref Scan disable
2483 10:00:38.067579 == TX Byte 0 ==
2484 10:00:38.073977 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2485 10:00:38.077121 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2486 10:00:38.077580 == TX Byte 1 ==
2487 10:00:38.084172 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2488 10:00:38.087321 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2489 10:00:38.087867 ==
2490 10:00:38.090812 Dram Type= 6, Freq= 0, CH_0, rank 0
2491 10:00:38.093813 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2492 10:00:38.094361 ==
2493 10:00:38.106742 TX Vref=22, minBit 9, minWin=25, winSum=417
2494 10:00:38.109930 TX Vref=24, minBit 9, minWin=25, winSum=424
2495 10:00:38.113077 TX Vref=26, minBit 9, minWin=25, winSum=425
2496 10:00:38.116567 TX Vref=28, minBit 9, minWin=25, winSum=429
2497 10:00:38.119980 TX Vref=30, minBit 8, minWin=25, winSum=433
2498 10:00:38.126347 TX Vref=32, minBit 10, minWin=26, winSum=435
2499 10:00:38.129831 [TxChooseVref] Worse bit 10, Min win 26, Win sum 435, Final Vref 32
2500 10:00:38.130379
2501 10:00:38.132857 Final TX Range 1 Vref 32
2502 10:00:38.133311
2503 10:00:38.133671 ==
2504 10:00:38.136660 Dram Type= 6, Freq= 0, CH_0, rank 0
2505 10:00:38.140028 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2506 10:00:38.140627 ==
2507 10:00:38.143115
2508 10:00:38.143658
2509 10:00:38.144017 TX Vref Scan disable
2510 10:00:38.146391 == TX Byte 0 ==
2511 10:00:38.149758 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2512 10:00:38.153462 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2513 10:00:38.156499 == TX Byte 1 ==
2514 10:00:38.159806 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2515 10:00:38.163137 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2516 10:00:38.166476
2517 10:00:38.167022 [DATLAT]
2518 10:00:38.167380 Freq=1200, CH0 RK0
2519 10:00:38.167714
2520 10:00:38.169310 DATLAT Default: 0xd
2521 10:00:38.169758 0, 0xFFFF, sum = 0
2522 10:00:38.172998 1, 0xFFFF, sum = 0
2523 10:00:38.173454 2, 0xFFFF, sum = 0
2524 10:00:38.176362 3, 0xFFFF, sum = 0
2525 10:00:38.179326 4, 0xFFFF, sum = 0
2526 10:00:38.179779 5, 0xFFFF, sum = 0
2527 10:00:38.183152 6, 0xFFFF, sum = 0
2528 10:00:38.183707 7, 0xFFFF, sum = 0
2529 10:00:38.186201 8, 0xFFFF, sum = 0
2530 10:00:38.186754 9, 0xFFFF, sum = 0
2531 10:00:38.189725 10, 0xFFFF, sum = 0
2532 10:00:38.190181 11, 0x0, sum = 1
2533 10:00:38.192694 12, 0x0, sum = 2
2534 10:00:38.193151 13, 0x0, sum = 3
2535 10:00:38.196227 14, 0x0, sum = 4
2536 10:00:38.196834 best_step = 12
2537 10:00:38.197194
2538 10:00:38.197522 ==
2539 10:00:38.199361 Dram Type= 6, Freq= 0, CH_0, rank 0
2540 10:00:38.202888 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2541 10:00:38.203439 ==
2542 10:00:38.206191 RX Vref Scan: 1
2543 10:00:38.206735
2544 10:00:38.209501 Set Vref Range= 32 -> 127
2545 10:00:38.210047
2546 10:00:38.210403 RX Vref 32 -> 127, step: 1
2547 10:00:38.210734
2548 10:00:38.213039 RX Delay -21 -> 252, step: 4
2549 10:00:38.213594
2550 10:00:38.216223 Set Vref, RX VrefLevel [Byte0]: 32
2551 10:00:38.219510 [Byte1]: 32
2552 10:00:38.222883
2553 10:00:38.223339 Set Vref, RX VrefLevel [Byte0]: 33
2554 10:00:38.226252 [Byte1]: 33
2555 10:00:38.231060
2556 10:00:38.231606 Set Vref, RX VrefLevel [Byte0]: 34
2557 10:00:38.234169 [Byte1]: 34
2558 10:00:38.238891
2559 10:00:38.239433 Set Vref, RX VrefLevel [Byte0]: 35
2560 10:00:38.242394 [Byte1]: 35
2561 10:00:38.247114
2562 10:00:38.247674 Set Vref, RX VrefLevel [Byte0]: 36
2563 10:00:38.250317 [Byte1]: 36
2564 10:00:38.254937
2565 10:00:38.255483 Set Vref, RX VrefLevel [Byte0]: 37
2566 10:00:38.257846 [Byte1]: 37
2567 10:00:38.262922
2568 10:00:38.263471 Set Vref, RX VrefLevel [Byte0]: 38
2569 10:00:38.266255 [Byte1]: 38
2570 10:00:38.270528
2571 10:00:38.271385 Set Vref, RX VrefLevel [Byte0]: 39
2572 10:00:38.273969 [Byte1]: 39
2573 10:00:38.278271
2574 10:00:38.278724 Set Vref, RX VrefLevel [Byte0]: 40
2575 10:00:38.282136 [Byte1]: 40
2576 10:00:38.286721
2577 10:00:38.287264 Set Vref, RX VrefLevel [Byte0]: 41
2578 10:00:38.289867 [Byte1]: 41
2579 10:00:38.294358
2580 10:00:38.294977 Set Vref, RX VrefLevel [Byte0]: 42
2581 10:00:38.297649 [Byte1]: 42
2582 10:00:38.302269
2583 10:00:38.303008 Set Vref, RX VrefLevel [Byte0]: 43
2584 10:00:38.305721 [Byte1]: 43
2585 10:00:38.310188
2586 10:00:38.310733 Set Vref, RX VrefLevel [Byte0]: 44
2587 10:00:38.313380 [Byte1]: 44
2588 10:00:38.318455
2589 10:00:38.318998 Set Vref, RX VrefLevel [Byte0]: 45
2590 10:00:38.321513 [Byte1]: 45
2591 10:00:38.325980
2592 10:00:38.326565 Set Vref, RX VrefLevel [Byte0]: 46
2593 10:00:38.329364 [Byte1]: 46
2594 10:00:38.334086
2595 10:00:38.334542 Set Vref, RX VrefLevel [Byte0]: 47
2596 10:00:38.337159 [Byte1]: 47
2597 10:00:38.341733
2598 10:00:38.342276 Set Vref, RX VrefLevel [Byte0]: 48
2599 10:00:38.344951 [Byte1]: 48
2600 10:00:38.349853
2601 10:00:38.350420 Set Vref, RX VrefLevel [Byte0]: 49
2602 10:00:38.353116 [Byte1]: 49
2603 10:00:38.357575
2604 10:00:38.358118 Set Vref, RX VrefLevel [Byte0]: 50
2605 10:00:38.361150 [Byte1]: 50
2606 10:00:38.365702
2607 10:00:38.366254 Set Vref, RX VrefLevel [Byte0]: 51
2608 10:00:38.369076 [Byte1]: 51
2609 10:00:38.373596
2610 10:00:38.374049 Set Vref, RX VrefLevel [Byte0]: 52
2611 10:00:38.380301 [Byte1]: 52
2612 10:00:38.380960
2613 10:00:38.383249 Set Vref, RX VrefLevel [Byte0]: 53
2614 10:00:38.386735 [Byte1]: 53
2615 10:00:38.387318
2616 10:00:38.389901 Set Vref, RX VrefLevel [Byte0]: 54
2617 10:00:38.393256 [Byte1]: 54
2618 10:00:38.397239
2619 10:00:38.397785 Set Vref, RX VrefLevel [Byte0]: 55
2620 10:00:38.400620 [Byte1]: 55
2621 10:00:38.405160
2622 10:00:38.405702 Set Vref, RX VrefLevel [Byte0]: 56
2623 10:00:38.408410 [Byte1]: 56
2624 10:00:38.413264
2625 10:00:38.414016 Set Vref, RX VrefLevel [Byte0]: 57
2626 10:00:38.416758 [Byte1]: 57
2627 10:00:38.420838
2628 10:00:38.421311 Set Vref, RX VrefLevel [Byte0]: 58
2629 10:00:38.424357 [Byte1]: 58
2630 10:00:38.429240
2631 10:00:38.429784 Set Vref, RX VrefLevel [Byte0]: 59
2632 10:00:38.432398 [Byte1]: 59
2633 10:00:38.437106
2634 10:00:38.437648 Set Vref, RX VrefLevel [Byte0]: 60
2635 10:00:38.440548 [Byte1]: 60
2636 10:00:38.444948
2637 10:00:38.445489 Set Vref, RX VrefLevel [Byte0]: 61
2638 10:00:38.448207 [Byte1]: 61
2639 10:00:38.452948
2640 10:00:38.453489 Set Vref, RX VrefLevel [Byte0]: 62
2641 10:00:38.456258 [Byte1]: 62
2642 10:00:38.460761
2643 10:00:38.461328 Set Vref, RX VrefLevel [Byte0]: 63
2644 10:00:38.464158 [Byte1]: 63
2645 10:00:38.468717
2646 10:00:38.469259 Set Vref, RX VrefLevel [Byte0]: 64
2647 10:00:38.471736 [Byte1]: 64
2648 10:00:38.476434
2649 10:00:38.476943 Set Vref, RX VrefLevel [Byte0]: 65
2650 10:00:38.479889 [Byte1]: 65
2651 10:00:38.484580
2652 10:00:38.485035 Set Vref, RX VrefLevel [Byte0]: 66
2653 10:00:38.487729 [Byte1]: 66
2654 10:00:38.492462
2655 10:00:38.493076 Final RX Vref Byte 0 = 49 to rank0
2656 10:00:38.495945 Final RX Vref Byte 1 = 46 to rank0
2657 10:00:38.499044 Final RX Vref Byte 0 = 49 to rank1
2658 10:00:38.502410 Final RX Vref Byte 1 = 46 to rank1==
2659 10:00:38.505830 Dram Type= 6, Freq= 0, CH_0, rank 0
2660 10:00:38.512600 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2661 10:00:38.513146 ==
2662 10:00:38.513505 DQS Delay:
2663 10:00:38.513848 DQS0 = 0, DQS1 = 0
2664 10:00:38.515645 DQM Delay:
2665 10:00:38.516097 DQM0 = 114, DQM1 = 105
2666 10:00:38.519109 DQ Delay:
2667 10:00:38.522242 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =110
2668 10:00:38.525577 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =122
2669 10:00:38.528991 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2670 10:00:38.533008 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =114
2671 10:00:38.533558
2672 10:00:38.533910
2673 10:00:38.538940 [DQSOSCAuto] RK0, (LSB)MR18= 0x909, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
2674 10:00:38.542518 CH0 RK0: MR19=404, MR18=909
2675 10:00:38.549246 CH0_RK0: MR19=0x404, MR18=0x909, DQSOSC=406, MR23=63, INC=39, DEC=26
2676 10:00:38.549792
2677 10:00:38.552794 ----->DramcWriteLeveling(PI) begin...
2678 10:00:38.553352 ==
2679 10:00:38.555861 Dram Type= 6, Freq= 0, CH_0, rank 1
2680 10:00:38.559169 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2681 10:00:38.559715 ==
2682 10:00:38.562475 Write leveling (Byte 0): 27 => 27
2683 10:00:38.565836 Write leveling (Byte 1): 24 => 24
2684 10:00:38.569090 DramcWriteLeveling(PI) end<-----
2685 10:00:38.569541
2686 10:00:38.569893 ==
2687 10:00:38.572480 Dram Type= 6, Freq= 0, CH_0, rank 1
2688 10:00:38.575811 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2689 10:00:38.578918 ==
2690 10:00:38.579458 [Gating] SW mode calibration
2691 10:00:38.589107 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2692 10:00:38.592409 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2693 10:00:38.595871 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2694 10:00:38.602076 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2695 10:00:38.605823 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2696 10:00:38.608737 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2697 10:00:38.615359 0 11 16 | B1->B0 | 3434 3030 | 0 1 | (0 1) (1 0)
2698 10:00:38.618962 0 11 20 | B1->B0 | 2e2e 2424 | 0 0 | (0 1) (1 0)
2699 10:00:38.622048 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2700 10:00:38.628631 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2701 10:00:38.632459 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2702 10:00:38.635546 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2703 10:00:38.642126 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2704 10:00:38.645452 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2705 10:00:38.648560 0 12 16 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
2706 10:00:38.655794 0 12 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2707 10:00:38.658633 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2708 10:00:38.662062 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2709 10:00:38.669006 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2710 10:00:38.672270 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2711 10:00:38.675413 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2712 10:00:38.678415 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2713 10:00:38.685261 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2714 10:00:38.688879 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2715 10:00:38.692253 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2716 10:00:38.698974 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2717 10:00:38.702114 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2718 10:00:38.705432 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2719 10:00:38.712242 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2720 10:00:38.715584 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2721 10:00:38.719002 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2722 10:00:38.725278 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2723 10:00:38.728955 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2724 10:00:38.732108 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2725 10:00:38.738579 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2726 10:00:38.742131 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2727 10:00:38.745441 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2728 10:00:38.751977 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2729 10:00:38.755711 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2730 10:00:38.758528 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2731 10:00:38.761803 Total UI for P1: 0, mck2ui 16
2732 10:00:38.765285 best dqsien dly found for B0: ( 0, 15, 16)
2733 10:00:38.768568 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2734 10:00:38.771777 Total UI for P1: 0, mck2ui 16
2735 10:00:38.775310 best dqsien dly found for B1: ( 0, 15, 18)
2736 10:00:38.778867 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2737 10:00:38.785213 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2738 10:00:38.786091
2739 10:00:38.788492 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2740 10:00:38.791982 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2741 10:00:38.795409 [Gating] SW calibration Done
2742 10:00:38.795960 ==
2743 10:00:38.798612 Dram Type= 6, Freq= 0, CH_0, rank 1
2744 10:00:38.801735 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2745 10:00:38.802191 ==
2746 10:00:38.805359 RX Vref Scan: 0
2747 10:00:38.805905
2748 10:00:38.806259 RX Vref 0 -> 0, step: 1
2749 10:00:38.806590
2750 10:00:38.808779 RX Delay -40 -> 252, step: 8
2751 10:00:38.811971 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2752 10:00:38.818536 iDelay=200, Bit 1, Center 119 (40 ~ 199) 160
2753 10:00:38.821885 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2754 10:00:38.825186 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2755 10:00:38.828409 iDelay=200, Bit 4, Center 119 (40 ~ 199) 160
2756 10:00:38.831604 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2757 10:00:38.835095 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2758 10:00:38.841598 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2759 10:00:38.844979 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2760 10:00:38.848624 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2761 10:00:38.851819 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2762 10:00:38.854945 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2763 10:00:38.861978 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2764 10:00:38.865087 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2765 10:00:38.868302 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2766 10:00:38.871608 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2767 10:00:38.872065 ==
2768 10:00:38.875156 Dram Type= 6, Freq= 0, CH_0, rank 1
2769 10:00:38.882245 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2770 10:00:38.882816 ==
2771 10:00:38.883180 DQS Delay:
2772 10:00:38.884997 DQS0 = 0, DQS1 = 0
2773 10:00:38.885446 DQM Delay:
2774 10:00:38.885799 DQM0 = 116, DQM1 = 106
2775 10:00:38.888214 DQ Delay:
2776 10:00:38.891812 DQ0 =111, DQ1 =119, DQ2 =115, DQ3 =111
2777 10:00:38.895108 DQ4 =119, DQ5 =107, DQ6 =123, DQ7 =123
2778 10:00:38.898554 DQ8 =91, DQ9 =91, DQ10 =111, DQ11 =99
2779 10:00:38.901865 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =115
2780 10:00:38.902322
2781 10:00:38.902675
2782 10:00:38.902999 ==
2783 10:00:38.905170 Dram Type= 6, Freq= 0, CH_0, rank 1
2784 10:00:38.908455 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2785 10:00:38.909057 ==
2786 10:00:38.911840
2787 10:00:38.912380
2788 10:00:38.912797 TX Vref Scan disable
2789 10:00:38.915365 == TX Byte 0 ==
2790 10:00:38.918559 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2791 10:00:38.921866 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2792 10:00:38.924988 == TX Byte 1 ==
2793 10:00:38.928456 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2794 10:00:38.931534 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2795 10:00:38.931986 ==
2796 10:00:38.935113 Dram Type= 6, Freq= 0, CH_0, rank 1
2797 10:00:38.941784 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2798 10:00:38.942367 ==
2799 10:00:38.952499 TX Vref=22, minBit 8, minWin=25, winSum=417
2800 10:00:38.955687 TX Vref=24, minBit 8, minWin=25, winSum=420
2801 10:00:38.959191 TX Vref=26, minBit 9, minWin=25, winSum=425
2802 10:00:38.962668 TX Vref=28, minBit 1, minWin=26, winSum=428
2803 10:00:38.965743 TX Vref=30, minBit 10, minWin=25, winSum=430
2804 10:00:38.972351 TX Vref=32, minBit 8, minWin=26, winSum=432
2805 10:00:38.975424 [TxChooseVref] Worse bit 8, Min win 26, Win sum 432, Final Vref 32
2806 10:00:38.975884
2807 10:00:38.979291 Final TX Range 1 Vref 32
2808 10:00:38.979839
2809 10:00:38.980197 ==
2810 10:00:38.982519 Dram Type= 6, Freq= 0, CH_0, rank 1
2811 10:00:38.985932 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2812 10:00:38.986482 ==
2813 10:00:38.988989
2814 10:00:38.989478
2815 10:00:38.989839 TX Vref Scan disable
2816 10:00:38.992118 == TX Byte 0 ==
2817 10:00:38.995661 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2818 10:00:38.998986 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2819 10:00:39.002343 == TX Byte 1 ==
2820 10:00:39.005526 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2821 10:00:39.008979 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2822 10:00:39.012428
2823 10:00:39.013014 [DATLAT]
2824 10:00:39.013372 Freq=1200, CH0 RK1
2825 10:00:39.013704
2826 10:00:39.015878 DATLAT Default: 0xc
2827 10:00:39.016423 0, 0xFFFF, sum = 0
2828 10:00:39.018817 1, 0xFFFF, sum = 0
2829 10:00:39.019271 2, 0xFFFF, sum = 0
2830 10:00:39.022507 3, 0xFFFF, sum = 0
2831 10:00:39.023128 4, 0xFFFF, sum = 0
2832 10:00:39.025676 5, 0xFFFF, sum = 0
2833 10:00:39.028863 6, 0xFFFF, sum = 0
2834 10:00:39.029320 7, 0xFFFF, sum = 0
2835 10:00:39.032558 8, 0xFFFF, sum = 0
2836 10:00:39.033116 9, 0xFFFF, sum = 0
2837 10:00:39.035658 10, 0xFFFF, sum = 0
2838 10:00:39.036111 11, 0x0, sum = 1
2839 10:00:39.038700 12, 0x0, sum = 2
2840 10:00:39.039157 13, 0x0, sum = 3
2841 10:00:39.039516 14, 0x0, sum = 4
2842 10:00:39.042284 best_step = 12
2843 10:00:39.042866
2844 10:00:39.043230 ==
2845 10:00:39.045742 Dram Type= 6, Freq= 0, CH_0, rank 1
2846 10:00:39.048948 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2847 10:00:39.049507 ==
2848 10:00:39.052001 RX Vref Scan: 0
2849 10:00:39.052448
2850 10:00:39.052847 RX Vref 0 -> 0, step: 1
2851 10:00:39.055304
2852 10:00:39.055747 RX Delay -21 -> 252, step: 4
2853 10:00:39.062633 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2854 10:00:39.065876 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2855 10:00:39.069196 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2856 10:00:39.072980 iDelay=199, Bit 3, Center 108 (39 ~ 178) 140
2857 10:00:39.076020 iDelay=199, Bit 4, Center 116 (43 ~ 190) 148
2858 10:00:39.082845 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2859 10:00:39.086487 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
2860 10:00:39.089234 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2861 10:00:39.092787 iDelay=199, Bit 8, Center 92 (31 ~ 154) 124
2862 10:00:39.095995 iDelay=199, Bit 9, Center 88 (27 ~ 150) 124
2863 10:00:39.102861 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
2864 10:00:39.106300 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2865 10:00:39.109250 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
2866 10:00:39.112909 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2867 10:00:39.116073 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
2868 10:00:39.122760 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2869 10:00:39.123358 ==
2870 10:00:39.126341 Dram Type= 6, Freq= 0, CH_0, rank 1
2871 10:00:39.129252 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2872 10:00:39.129705 ==
2873 10:00:39.130061 DQS Delay:
2874 10:00:39.132732 DQS0 = 0, DQS1 = 0
2875 10:00:39.133280 DQM Delay:
2876 10:00:39.136049 DQM0 = 114, DQM1 = 105
2877 10:00:39.136646 DQ Delay:
2878 10:00:39.139285 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2879 10:00:39.142748 DQ4 =116, DQ5 =108, DQ6 =122, DQ7 =124
2880 10:00:39.146105 DQ8 =92, DQ9 =88, DQ10 =110, DQ11 =96
2881 10:00:39.149456 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
2882 10:00:39.150003
2883 10:00:39.150358
2884 10:00:39.159439 [DQSOSCAuto] RK1, (LSB)MR18= 0x1212, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 403 ps
2885 10:00:39.162733 CH0 RK1: MR19=404, MR18=1212
2886 10:00:39.166057 CH0_RK1: MR19=0x404, MR18=0x1212, DQSOSC=403, MR23=63, INC=40, DEC=26
2887 10:00:39.169221 [RxdqsGatingPostProcess] freq 1200
2888 10:00:39.175718 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2889 10:00:39.179171 Pre-setting of DQS Precalculation
2890 10:00:39.182419 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2891 10:00:39.182871 ==
2892 10:00:39.186070 Dram Type= 6, Freq= 0, CH_1, rank 0
2893 10:00:39.192735 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2894 10:00:39.193189 ==
2895 10:00:39.196187 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2896 10:00:39.202660 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2897 10:00:39.211388 [CA 0] Center 37 (7~68) winsize 62
2898 10:00:39.214540 [CA 1] Center 37 (7~68) winsize 62
2899 10:00:39.217931 [CA 2] Center 34 (4~65) winsize 62
2900 10:00:39.221480 [CA 3] Center 33 (3~64) winsize 62
2901 10:00:39.224816 [CA 4] Center 32 (2~63) winsize 62
2902 10:00:39.228084 [CA 5] Center 32 (2~63) winsize 62
2903 10:00:39.228666
2904 10:00:39.231336 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2905 10:00:39.231882
2906 10:00:39.234432 [CATrainingPosCal] consider 1 rank data
2907 10:00:39.238380 u2DelayCellTimex100 = 270/100 ps
2908 10:00:39.241481 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2909 10:00:39.244806 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2910 10:00:39.251332 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2911 10:00:39.254719 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2912 10:00:39.258206 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2913 10:00:39.261442 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2914 10:00:39.261988
2915 10:00:39.264621 CA PerBit enable=1, Macro0, CA PI delay=32
2916 10:00:39.265168
2917 10:00:39.267959 [CBTSetCACLKResult] CA Dly = 32
2918 10:00:39.268503 CS Dly: 6 (0~37)
2919 10:00:39.268920 ==
2920 10:00:39.271226 Dram Type= 6, Freq= 0, CH_1, rank 1
2921 10:00:39.277859 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2922 10:00:39.278317 ==
2923 10:00:39.281094 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2924 10:00:39.287676 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2925 10:00:39.296653 [CA 0] Center 37 (6~68) winsize 63
2926 10:00:39.299972 [CA 1] Center 37 (7~68) winsize 62
2927 10:00:39.303235 [CA 2] Center 33 (3~64) winsize 62
2928 10:00:39.306607 [CA 3] Center 33 (3~64) winsize 62
2929 10:00:39.310101 [CA 4] Center 32 (2~63) winsize 62
2930 10:00:39.313194 [CA 5] Center 32 (1~63) winsize 63
2931 10:00:39.313744
2932 10:00:39.316835 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2933 10:00:39.317379
2934 10:00:39.319772 [CATrainingPosCal] consider 2 rank data
2935 10:00:39.323129 u2DelayCellTimex100 = 270/100 ps
2936 10:00:39.326527 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2937 10:00:39.329817 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2938 10:00:39.336555 CA2 delay=34 (4~64),Diff = 2 PI (9 cell)
2939 10:00:39.339795 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2940 10:00:39.343175 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2941 10:00:39.346327 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2942 10:00:39.346868
2943 10:00:39.349970 CA PerBit enable=1, Macro0, CA PI delay=32
2944 10:00:39.350507
2945 10:00:39.353329 [CBTSetCACLKResult] CA Dly = 32
2946 10:00:39.353871 CS Dly: 6 (0~38)
2947 10:00:39.354228
2948 10:00:39.356671 ----->DramcWriteLeveling(PI) begin...
2949 10:00:39.359735 ==
2950 10:00:39.363070 Dram Type= 6, Freq= 0, CH_1, rank 0
2951 10:00:39.366316 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2952 10:00:39.366771 ==
2953 10:00:39.369475 Write leveling (Byte 0): 22 => 22
2954 10:00:39.373113 Write leveling (Byte 1): 23 => 23
2955 10:00:39.376141 DramcWriteLeveling(PI) end<-----
2956 10:00:39.376627
2957 10:00:39.376996 ==
2958 10:00:39.379762 Dram Type= 6, Freq= 0, CH_1, rank 0
2959 10:00:39.383147 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2960 10:00:39.383700 ==
2961 10:00:39.386157 [Gating] SW mode calibration
2962 10:00:39.393153 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2963 10:00:39.399965 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2964 10:00:39.403084 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2965 10:00:39.406472 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2966 10:00:39.409727 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2967 10:00:39.416235 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2968 10:00:39.419751 0 11 16 | B1->B0 | 3131 2525 | 1 0 | (1 0) (1 0)
2969 10:00:39.422888 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2970 10:00:39.429598 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2971 10:00:39.433231 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2972 10:00:39.436654 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2973 10:00:39.443023 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2974 10:00:39.446416 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2975 10:00:39.449708 0 12 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2976 10:00:39.456409 0 12 16 | B1->B0 | 3131 3e3d | 0 1 | (0 0) (1 1)
2977 10:00:39.459817 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2978 10:00:39.462855 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2979 10:00:39.469663 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2980 10:00:39.473450 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2981 10:00:39.476375 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2982 10:00:39.482938 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2983 10:00:39.486357 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2984 10:00:39.489440 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2985 10:00:39.496144 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2986 10:00:39.499882 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 10:00:39.503063 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 10:00:39.506406 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2989 10:00:39.512884 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2990 10:00:39.516495 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2991 10:00:39.519727 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2992 10:00:39.526618 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2993 10:00:39.529514 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2994 10:00:39.533116 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2995 10:00:39.539966 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2996 10:00:39.542944 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2997 10:00:39.546179 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2998 10:00:39.552888 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2999 10:00:39.556259 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3000 10:00:39.559638 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3001 10:00:39.566288 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3002 10:00:39.566838 Total UI for P1: 0, mck2ui 16
3003 10:00:39.572866 best dqsien dly found for B0: ( 0, 15, 16)
3004 10:00:39.576113 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3005 10:00:39.579336 Total UI for P1: 0, mck2ui 16
3006 10:00:39.582766 best dqsien dly found for B1: ( 0, 15, 18)
3007 10:00:39.586405 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3008 10:00:39.589230 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3009 10:00:39.589686
3010 10:00:39.592470 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3011 10:00:39.595770 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3012 10:00:39.599137 [Gating] SW calibration Done
3013 10:00:39.599585 ==
3014 10:00:39.602459 Dram Type= 6, Freq= 0, CH_1, rank 0
3015 10:00:39.606043 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3016 10:00:39.609372 ==
3017 10:00:39.609826 RX Vref Scan: 0
3018 10:00:39.610180
3019 10:00:39.612686 RX Vref 0 -> 0, step: 1
3020 10:00:39.613231
3021 10:00:39.615949 RX Delay -40 -> 252, step: 8
3022 10:00:39.619490 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3023 10:00:39.622319 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3024 10:00:39.625657 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3025 10:00:39.629385 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3026 10:00:39.635517 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3027 10:00:39.639240 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3028 10:00:39.642420 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3029 10:00:39.645617 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3030 10:00:39.649252 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3031 10:00:39.655349 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3032 10:00:39.659081 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3033 10:00:39.662508 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3034 10:00:39.665765 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3035 10:00:39.669106 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3036 10:00:39.675388 iDelay=208, Bit 14, Center 115 (48 ~ 183) 136
3037 10:00:39.678898 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3038 10:00:39.679444 ==
3039 10:00:39.682386 Dram Type= 6, Freq= 0, CH_1, rank 0
3040 10:00:39.685791 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3041 10:00:39.686338 ==
3042 10:00:39.688903 DQS Delay:
3043 10:00:39.689351 DQS0 = 0, DQS1 = 0
3044 10:00:39.689707 DQM Delay:
3045 10:00:39.692451 DQM0 = 116, DQM1 = 108
3046 10:00:39.693042 DQ Delay:
3047 10:00:39.695501 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3048 10:00:39.699179 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3049 10:00:39.702399 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =99
3050 10:00:39.705836 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3051 10:00:39.706376
3052 10:00:39.709225
3053 10:00:39.709672 ==
3054 10:00:39.712442 Dram Type= 6, Freq= 0, CH_1, rank 0
3055 10:00:39.715815 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3056 10:00:39.716411 ==
3057 10:00:39.716879
3058 10:00:39.717214
3059 10:00:39.719069 TX Vref Scan disable
3060 10:00:39.719517 == TX Byte 0 ==
3061 10:00:39.725677 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3062 10:00:39.728970 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3063 10:00:39.729611 == TX Byte 1 ==
3064 10:00:39.735531 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3065 10:00:39.739119 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3066 10:00:39.739666 ==
3067 10:00:39.742430 Dram Type= 6, Freq= 0, CH_1, rank 0
3068 10:00:39.745781 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3069 10:00:39.746337 ==
3070 10:00:39.757849 TX Vref=22, minBit 8, minWin=25, winSum=413
3071 10:00:39.761132 TX Vref=24, minBit 0, minWin=25, winSum=423
3072 10:00:39.764634 TX Vref=26, minBit 15, minWin=25, winSum=429
3073 10:00:39.767536 TX Vref=28, minBit 8, minWin=26, winSum=431
3074 10:00:39.771118 TX Vref=30, minBit 8, minWin=26, winSum=432
3075 10:00:39.777553 TX Vref=32, minBit 9, minWin=26, winSum=430
3076 10:00:39.780866 [TxChooseVref] Worse bit 8, Min win 26, Win sum 432, Final Vref 30
3077 10:00:39.781321
3078 10:00:39.784336 Final TX Range 1 Vref 30
3079 10:00:39.784836
3080 10:00:39.785194 ==
3081 10:00:39.787566 Dram Type= 6, Freq= 0, CH_1, rank 0
3082 10:00:39.790751 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3083 10:00:39.791201 ==
3084 10:00:39.794229
3085 10:00:39.794777
3086 10:00:39.795135 TX Vref Scan disable
3087 10:00:39.797297 == TX Byte 0 ==
3088 10:00:39.800433 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3089 10:00:39.807540 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3090 10:00:39.808089 == TX Byte 1 ==
3091 10:00:39.810669 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3092 10:00:39.817240 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3093 10:00:39.817779
3094 10:00:39.818133 [DATLAT]
3095 10:00:39.818461 Freq=1200, CH1 RK0
3096 10:00:39.818780
3097 10:00:39.820813 DATLAT Default: 0xd
3098 10:00:39.821355 0, 0xFFFF, sum = 0
3099 10:00:39.824002 1, 0xFFFF, sum = 0
3100 10:00:39.824566 2, 0xFFFF, sum = 0
3101 10:00:39.827688 3, 0xFFFF, sum = 0
3102 10:00:39.830509 4, 0xFFFF, sum = 0
3103 10:00:39.830966 5, 0xFFFF, sum = 0
3104 10:00:39.833896 6, 0xFFFF, sum = 0
3105 10:00:39.834510 7, 0xFFFF, sum = 0
3106 10:00:39.837657 8, 0xFFFF, sum = 0
3107 10:00:39.838262 9, 0xFFFF, sum = 0
3108 10:00:39.840870 10, 0xFFFF, sum = 0
3109 10:00:39.841426 11, 0x0, sum = 1
3110 10:00:39.844086 12, 0x0, sum = 2
3111 10:00:39.844678 13, 0x0, sum = 3
3112 10:00:39.847201 14, 0x0, sum = 4
3113 10:00:39.847656 best_step = 12
3114 10:00:39.848005
3115 10:00:39.848332 ==
3116 10:00:39.850567 Dram Type= 6, Freq= 0, CH_1, rank 0
3117 10:00:39.854143 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3118 10:00:39.854692 ==
3119 10:00:39.857382 RX Vref Scan: 1
3120 10:00:39.857971
3121 10:00:39.860593 Set Vref Range= 32 -> 127
3122 10:00:39.861134
3123 10:00:39.861491 RX Vref 32 -> 127, step: 1
3124 10:00:39.861820
3125 10:00:39.863991 RX Delay -29 -> 252, step: 4
3126 10:00:39.864585
3127 10:00:39.867208 Set Vref, RX VrefLevel [Byte0]: 32
3128 10:00:39.870488 [Byte1]: 32
3129 10:00:39.874326
3130 10:00:39.874773 Set Vref, RX VrefLevel [Byte0]: 33
3131 10:00:39.877440 [Byte1]: 33
3132 10:00:39.882054
3133 10:00:39.882503 Set Vref, RX VrefLevel [Byte0]: 34
3134 10:00:39.885365 [Byte1]: 34
3135 10:00:39.890135
3136 10:00:39.890680 Set Vref, RX VrefLevel [Byte0]: 35
3137 10:00:39.893622 [Byte1]: 35
3138 10:00:39.897835
3139 10:00:39.898282 Set Vref, RX VrefLevel [Byte0]: 36
3140 10:00:39.901713 [Byte1]: 36
3141 10:00:39.906331
3142 10:00:39.906872 Set Vref, RX VrefLevel [Byte0]: 37
3143 10:00:39.909073 [Byte1]: 37
3144 10:00:39.913960
3145 10:00:39.914510 Set Vref, RX VrefLevel [Byte0]: 38
3146 10:00:39.917208 [Byte1]: 38
3147 10:00:39.921914
3148 10:00:39.922463 Set Vref, RX VrefLevel [Byte0]: 39
3149 10:00:39.924986 [Byte1]: 39
3150 10:00:39.929837
3151 10:00:39.930281 Set Vref, RX VrefLevel [Byte0]: 40
3152 10:00:39.933211 [Byte1]: 40
3153 10:00:39.937969
3154 10:00:39.938510 Set Vref, RX VrefLevel [Byte0]: 41
3155 10:00:39.940902 [Byte1]: 41
3156 10:00:39.945933
3157 10:00:39.946479 Set Vref, RX VrefLevel [Byte0]: 42
3158 10:00:39.949144 [Byte1]: 42
3159 10:00:39.953682
3160 10:00:39.954225 Set Vref, RX VrefLevel [Byte0]: 43
3161 10:00:39.957158 [Byte1]: 43
3162 10:00:39.961704
3163 10:00:39.962252 Set Vref, RX VrefLevel [Byte0]: 44
3164 10:00:39.965432 [Byte1]: 44
3165 10:00:39.969338
3166 10:00:39.969792 Set Vref, RX VrefLevel [Byte0]: 45
3167 10:00:39.973192 [Byte1]: 45
3168 10:00:39.978092
3169 10:00:39.978641 Set Vref, RX VrefLevel [Byte0]: 46
3170 10:00:39.980700 [Byte1]: 46
3171 10:00:39.985591
3172 10:00:39.986169 Set Vref, RX VrefLevel [Byte0]: 47
3173 10:00:39.989109 [Byte1]: 47
3174 10:00:39.993564
3175 10:00:39.994012 Set Vref, RX VrefLevel [Byte0]: 48
3176 10:00:39.996614 [Byte1]: 48
3177 10:00:40.001402
3178 10:00:40.001942 Set Vref, RX VrefLevel [Byte0]: 49
3179 10:00:40.004579 [Byte1]: 49
3180 10:00:40.009360
3181 10:00:40.009902 Set Vref, RX VrefLevel [Byte0]: 50
3182 10:00:40.012842 [Byte1]: 50
3183 10:00:40.017373
3184 10:00:40.017913 Set Vref, RX VrefLevel [Byte0]: 51
3185 10:00:40.021125 [Byte1]: 51
3186 10:00:40.025326
3187 10:00:40.025775 Set Vref, RX VrefLevel [Byte0]: 52
3188 10:00:40.028692 [Byte1]: 52
3189 10:00:40.033445
3190 10:00:40.034047 Set Vref, RX VrefLevel [Byte0]: 53
3191 10:00:40.036726 [Byte1]: 53
3192 10:00:40.041376
3193 10:00:40.041924 Set Vref, RX VrefLevel [Byte0]: 54
3194 10:00:40.044657 [Byte1]: 54
3195 10:00:40.049238
3196 10:00:40.049783 Set Vref, RX VrefLevel [Byte0]: 55
3197 10:00:40.052562 [Byte1]: 55
3198 10:00:40.057342
3199 10:00:40.057884 Set Vref, RX VrefLevel [Byte0]: 56
3200 10:00:40.060381 [Byte1]: 56
3201 10:00:40.065003
3202 10:00:40.065497 Set Vref, RX VrefLevel [Byte0]: 57
3203 10:00:40.068681 [Byte1]: 57
3204 10:00:40.073213
3205 10:00:40.073756 Set Vref, RX VrefLevel [Byte0]: 58
3206 10:00:40.076318 [Byte1]: 58
3207 10:00:40.081271
3208 10:00:40.081822 Set Vref, RX VrefLevel [Byte0]: 59
3209 10:00:40.084418 [Byte1]: 59
3210 10:00:40.089240
3211 10:00:40.089798 Set Vref, RX VrefLevel [Byte0]: 60
3212 10:00:40.092657 [Byte1]: 60
3213 10:00:40.096941
3214 10:00:40.097486 Set Vref, RX VrefLevel [Byte0]: 61
3215 10:00:40.100244 [Byte1]: 61
3216 10:00:40.104763
3217 10:00:40.105237 Set Vref, RX VrefLevel [Byte0]: 62
3218 10:00:40.108367 [Byte1]: 62
3219 10:00:40.113100
3220 10:00:40.113660 Set Vref, RX VrefLevel [Byte0]: 63
3221 10:00:40.116585 [Byte1]: 63
3222 10:00:40.120872
3223 10:00:40.121420 Set Vref, RX VrefLevel [Byte0]: 64
3224 10:00:40.124122 [Byte1]: 64
3225 10:00:40.128737
3226 10:00:40.129275 Set Vref, RX VrefLevel [Byte0]: 65
3227 10:00:40.132055 [Byte1]: 65
3228 10:00:40.136758
3229 10:00:40.137341 Set Vref, RX VrefLevel [Byte0]: 66
3230 10:00:40.140345 [Byte1]: 66
3231 10:00:40.144973
3232 10:00:40.145518 Final RX Vref Byte 0 = 58 to rank0
3233 10:00:40.148144 Final RX Vref Byte 1 = 48 to rank0
3234 10:00:40.151776 Final RX Vref Byte 0 = 58 to rank1
3235 10:00:40.154923 Final RX Vref Byte 1 = 48 to rank1==
3236 10:00:40.158185 Dram Type= 6, Freq= 0, CH_1, rank 0
3237 10:00:40.164823 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3238 10:00:40.165411 ==
3239 10:00:40.165785 DQS Delay:
3240 10:00:40.166163 DQS0 = 0, DQS1 = 0
3241 10:00:40.168121 DQM Delay:
3242 10:00:40.168714 DQM0 = 115, DQM1 = 105
3243 10:00:40.171442 DQ Delay:
3244 10:00:40.174986 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3245 10:00:40.178352 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =114
3246 10:00:40.181397 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =98
3247 10:00:40.184733 DQ12 =112, DQ13 =116, DQ14 =114, DQ15 =114
3248 10:00:40.185190
3249 10:00:40.185544
3250 10:00:40.191512 [DQSOSCAuto] RK0, (LSB)MR18= 0x1515, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
3251 10:00:40.194600 CH1 RK0: MR19=404, MR18=1515
3252 10:00:40.201605 CH1_RK0: MR19=0x404, MR18=0x1515, DQSOSC=401, MR23=63, INC=40, DEC=27
3253 10:00:40.202194
3254 10:00:40.204937 ----->DramcWriteLeveling(PI) begin...
3255 10:00:40.205491 ==
3256 10:00:40.208497 Dram Type= 6, Freq= 0, CH_1, rank 1
3257 10:00:40.211412 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3258 10:00:40.211961 ==
3259 10:00:40.214494 Write leveling (Byte 0): 22 => 22
3260 10:00:40.217934 Write leveling (Byte 1): 22 => 22
3261 10:00:40.221494 DramcWriteLeveling(PI) end<-----
3262 10:00:40.222035
3263 10:00:40.222393 ==
3264 10:00:40.224764 Dram Type= 6, Freq= 0, CH_1, rank 1
3265 10:00:40.231152 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3266 10:00:40.231607 ==
3267 10:00:40.231965 [Gating] SW mode calibration
3268 10:00:40.241466 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3269 10:00:40.244931 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3270 10:00:40.248102 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3271 10:00:40.254643 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3272 10:00:40.258129 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3273 10:00:40.261456 0 11 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 0)
3274 10:00:40.267963 0 11 16 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
3275 10:00:40.271763 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3276 10:00:40.274713 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3277 10:00:40.281259 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3278 10:00:40.284805 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3279 10:00:40.287738 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3280 10:00:40.294525 0 12 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3281 10:00:40.298032 0 12 12 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
3282 10:00:40.301032 0 12 16 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
3283 10:00:40.307908 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3284 10:00:40.311547 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3285 10:00:40.316549 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3286 10:00:40.321046 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3287 10:00:40.324693 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3288 10:00:40.327561 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3289 10:00:40.334374 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3290 10:00:40.337614 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3291 10:00:40.341315 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3292 10:00:40.347494 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3293 10:00:40.350823 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3294 10:00:40.354540 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3295 10:00:40.357553 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3296 10:00:40.364038 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3297 10:00:40.367539 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3298 10:00:40.371313 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3299 10:00:40.377489 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3300 10:00:40.380845 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3301 10:00:40.384119 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3302 10:00:40.390755 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3303 10:00:40.394260 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3304 10:00:40.397350 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3305 10:00:40.404095 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3306 10:00:40.407448 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3307 10:00:40.411079 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3308 10:00:40.414113 Total UI for P1: 0, mck2ui 16
3309 10:00:40.417446 best dqsien dly found for B0: ( 0, 15, 12)
3310 10:00:40.420722 Total UI for P1: 0, mck2ui 16
3311 10:00:40.424308 best dqsien dly found for B1: ( 0, 15, 14)
3312 10:00:40.427379 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3313 10:00:40.430766 best DQS1 dly(MCK, UI, PI) = (0, 15, 14)
3314 10:00:40.431222
3315 10:00:40.437445 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3316 10:00:40.440637 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 14)
3317 10:00:40.444083 [Gating] SW calibration Done
3318 10:00:40.444578 ==
3319 10:00:40.447576 Dram Type= 6, Freq= 0, CH_1, rank 1
3320 10:00:40.450961 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3321 10:00:40.451517 ==
3322 10:00:40.451878 RX Vref Scan: 0
3323 10:00:40.452206
3324 10:00:40.454292 RX Vref 0 -> 0, step: 1
3325 10:00:40.454829
3326 10:00:40.457191 RX Delay -40 -> 252, step: 8
3327 10:00:40.460856 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3328 10:00:40.464324 iDelay=208, Bit 1, Center 115 (40 ~ 191) 152
3329 10:00:40.471100 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3330 10:00:40.474130 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3331 10:00:40.477531 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3332 10:00:40.480709 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3333 10:00:40.484067 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3334 10:00:40.487515 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3335 10:00:40.494467 iDelay=208, Bit 8, Center 91 (16 ~ 167) 152
3336 10:00:40.497268 iDelay=208, Bit 9, Center 91 (16 ~ 167) 152
3337 10:00:40.500835 iDelay=208, Bit 10, Center 107 (32 ~ 183) 152
3338 10:00:40.503992 iDelay=208, Bit 11, Center 99 (24 ~ 175) 152
3339 10:00:40.507388 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3340 10:00:40.514238 iDelay=208, Bit 13, Center 115 (40 ~ 191) 152
3341 10:00:40.517339 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3342 10:00:40.521160 iDelay=208, Bit 15, Center 111 (40 ~ 183) 144
3343 10:00:40.521705 ==
3344 10:00:40.524280 Dram Type= 6, Freq= 0, CH_1, rank 1
3345 10:00:40.527293 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3346 10:00:40.527741 ==
3347 10:00:40.530726 DQS Delay:
3348 10:00:40.531174 DQS0 = 0, DQS1 = 0
3349 10:00:40.534316 DQM Delay:
3350 10:00:40.534858 DQM0 = 117, DQM1 = 105
3351 10:00:40.535210 DQ Delay:
3352 10:00:40.540756 DQ0 =119, DQ1 =115, DQ2 =107, DQ3 =115
3353 10:00:40.544252 DQ4 =115, DQ5 =131, DQ6 =123, DQ7 =115
3354 10:00:40.547777 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
3355 10:00:40.550897 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3356 10:00:40.551593
3357 10:00:40.551965
3358 10:00:40.552297 ==
3359 10:00:40.554203 Dram Type= 6, Freq= 0, CH_1, rank 1
3360 10:00:40.557282 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3361 10:00:40.557734 ==
3362 10:00:40.558088
3363 10:00:40.558410
3364 10:00:40.560785 TX Vref Scan disable
3365 10:00:40.564148 == TX Byte 0 ==
3366 10:00:40.567257 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3367 10:00:40.570908 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3368 10:00:40.573977 == TX Byte 1 ==
3369 10:00:40.577476 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3370 10:00:40.580363 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3371 10:00:40.580789 ==
3372 10:00:40.583910 Dram Type= 6, Freq= 0, CH_1, rank 1
3373 10:00:40.587387 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3374 10:00:40.587929 ==
3375 10:00:40.600397 TX Vref=22, minBit 8, minWin=25, winSum=420
3376 10:00:40.603619 TX Vref=24, minBit 9, minWin=25, winSum=426
3377 10:00:40.607037 TX Vref=26, minBit 9, minWin=25, winSum=427
3378 10:00:40.610531 TX Vref=28, minBit 3, minWin=26, winSum=431
3379 10:00:40.613588 TX Vref=30, minBit 9, minWin=26, winSum=432
3380 10:00:40.616972 TX Vref=32, minBit 0, minWin=26, winSum=430
3381 10:00:40.623349 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 30
3382 10:00:40.623817
3383 10:00:40.626482 Final TX Range 1 Vref 30
3384 10:00:40.626976
3385 10:00:40.627443 ==
3386 10:00:40.629838 Dram Type= 6, Freq= 0, CH_1, rank 1
3387 10:00:40.633210 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3388 10:00:40.633677 ==
3389 10:00:40.636448
3390 10:00:40.636982
3391 10:00:40.637447 TX Vref Scan disable
3392 10:00:40.640127 == TX Byte 0 ==
3393 10:00:40.643437 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3394 10:00:40.646585 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3395 10:00:40.649807 == TX Byte 1 ==
3396 10:00:40.653485 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3397 10:00:40.656447 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3398 10:00:40.659965
3399 10:00:40.660572 [DATLAT]
3400 10:00:40.661058 Freq=1200, CH1 RK1
3401 10:00:40.661507
3402 10:00:40.663712 DATLAT Default: 0xc
3403 10:00:40.664279 0, 0xFFFF, sum = 0
3404 10:00:40.666550 1, 0xFFFF, sum = 0
3405 10:00:40.667123 2, 0xFFFF, sum = 0
3406 10:00:40.669902 3, 0xFFFF, sum = 0
3407 10:00:40.670373 4, 0xFFFF, sum = 0
3408 10:00:40.673173 5, 0xFFFF, sum = 0
3409 10:00:40.676735 6, 0xFFFF, sum = 0
3410 10:00:40.677379 7, 0xFFFF, sum = 0
3411 10:00:40.679873 8, 0xFFFF, sum = 0
3412 10:00:40.680442 9, 0xFFFF, sum = 0
3413 10:00:40.683246 10, 0xFFFF, sum = 0
3414 10:00:40.683820 11, 0x0, sum = 1
3415 10:00:40.686858 12, 0x0, sum = 2
3416 10:00:40.687406 13, 0x0, sum = 3
3417 10:00:40.687770 14, 0x0, sum = 4
3418 10:00:40.690101 best_step = 12
3419 10:00:40.690646
3420 10:00:40.691007 ==
3421 10:00:40.693275 Dram Type= 6, Freq= 0, CH_1, rank 1
3422 10:00:40.696980 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3423 10:00:40.697535 ==
3424 10:00:40.700114 RX Vref Scan: 0
3425 10:00:40.700703
3426 10:00:40.701069 RX Vref 0 -> 0, step: 1
3427 10:00:40.703324
3428 10:00:40.703864 RX Delay -29 -> 252, step: 4
3429 10:00:40.710540 iDelay=199, Bit 0, Center 114 (43 ~ 186) 144
3430 10:00:40.713772 iDelay=199, Bit 1, Center 112 (43 ~ 182) 140
3431 10:00:40.717139 iDelay=199, Bit 2, Center 108 (43 ~ 174) 132
3432 10:00:40.720383 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3433 10:00:40.723762 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3434 10:00:40.730195 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3435 10:00:40.733387 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3436 10:00:40.736844 iDelay=199, Bit 7, Center 112 (43 ~ 182) 140
3437 10:00:40.740276 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3438 10:00:40.743741 iDelay=199, Bit 9, Center 90 (23 ~ 158) 136
3439 10:00:40.750471 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3440 10:00:40.753688 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3441 10:00:40.757350 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3442 10:00:40.760442 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3443 10:00:40.763896 iDelay=199, Bit 14, Center 116 (47 ~ 186) 140
3444 10:00:40.770473 iDelay=199, Bit 15, Center 112 (47 ~ 178) 132
3445 10:00:40.771024 ==
3446 10:00:40.774059 Dram Type= 6, Freq= 0, CH_1, rank 1
3447 10:00:40.777267 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3448 10:00:40.777900 ==
3449 10:00:40.778310 DQS Delay:
3450 10:00:40.780490 DQS0 = 0, DQS1 = 0
3451 10:00:40.781094 DQM Delay:
3452 10:00:40.783814 DQM0 = 114, DQM1 = 104
3453 10:00:40.784365 DQ Delay:
3454 10:00:40.787302 DQ0 =114, DQ1 =112, DQ2 =108, DQ3 =112
3455 10:00:40.790821 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3456 10:00:40.793649 DQ8 =86, DQ9 =90, DQ10 =106, DQ11 =98
3457 10:00:40.796944 DQ12 =112, DQ13 =112, DQ14 =116, DQ15 =112
3458 10:00:40.797389
3459 10:00:40.797738
3460 10:00:40.807313 [DQSOSCAuto] RK1, (LSB)MR18= 0xd0d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
3461 10:00:40.807868 CH1 RK1: MR19=404, MR18=D0D
3462 10:00:40.813783 CH1_RK1: MR19=0x404, MR18=0xD0D, DQSOSC=405, MR23=63, INC=39, DEC=26
3463 10:00:40.817392 [RxdqsGatingPostProcess] freq 1200
3464 10:00:40.823860 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3465 10:00:40.826966 Pre-setting of DQS Precalculation
3466 10:00:40.830238 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3467 10:00:40.837462 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3468 10:00:40.847084 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3469 10:00:40.847635
3470 10:00:40.847991
3471 10:00:40.850428 [Calibration Summary] 2400 Mbps
3472 10:00:40.850974 CH 0, Rank 0
3473 10:00:40.853703 SW Impedance : PASS
3474 10:00:40.854254 DUTY Scan : NO K
3475 10:00:40.857190 ZQ Calibration : PASS
3476 10:00:40.860327 Jitter Meter : NO K
3477 10:00:40.860961 CBT Training : PASS
3478 10:00:40.864006 Write leveling : PASS
3479 10:00:40.864609 RX DQS gating : PASS
3480 10:00:40.867337 RX DQ/DQS(RDDQC) : PASS
3481 10:00:40.870414 TX DQ/DQS : PASS
3482 10:00:40.870882 RX DATLAT : PASS
3483 10:00:40.873480 RX DQ/DQS(Engine): PASS
3484 10:00:40.877372 TX OE : NO K
3485 10:00:40.878033 All Pass.
3486 10:00:40.878522
3487 10:00:40.878962 CH 0, Rank 1
3488 10:00:40.880241 SW Impedance : PASS
3489 10:00:40.883680 DUTY Scan : NO K
3490 10:00:40.884243 ZQ Calibration : PASS
3491 10:00:40.887240 Jitter Meter : NO K
3492 10:00:40.890734 CBT Training : PASS
3493 10:00:40.891294 Write leveling : PASS
3494 10:00:40.893393 RX DQS gating : PASS
3495 10:00:40.896961 RX DQ/DQS(RDDQC) : PASS
3496 10:00:40.897455 TX DQ/DQS : PASS
3497 10:00:40.900679 RX DATLAT : PASS
3498 10:00:40.903767 RX DQ/DQS(Engine): PASS
3499 10:00:40.904233 TX OE : NO K
3500 10:00:40.904787 All Pass.
3501 10:00:40.907086
3502 10:00:40.907859 CH 1, Rank 0
3503 10:00:40.910236 SW Impedance : PASS
3504 10:00:40.910700 DUTY Scan : NO K
3505 10:00:40.913403 ZQ Calibration : PASS
3506 10:00:40.913893 Jitter Meter : NO K
3507 10:00:40.916776 CBT Training : PASS
3508 10:00:40.920425 Write leveling : PASS
3509 10:00:40.921049 RX DQS gating : PASS
3510 10:00:40.923563 RX DQ/DQS(RDDQC) : PASS
3511 10:00:40.926838 TX DQ/DQS : PASS
3512 10:00:40.927291 RX DATLAT : PASS
3513 10:00:40.930305 RX DQ/DQS(Engine): PASS
3514 10:00:40.933919 TX OE : NO K
3515 10:00:40.934539 All Pass.
3516 10:00:40.935019
3517 10:00:40.935466 CH 1, Rank 1
3518 10:00:40.936764 SW Impedance : PASS
3519 10:00:40.940415 DUTY Scan : NO K
3520 10:00:40.941262 ZQ Calibration : PASS
3521 10:00:40.943435 Jitter Meter : NO K
3522 10:00:40.947105 CBT Training : PASS
3523 10:00:40.947669 Write leveling : PASS
3524 10:00:40.950119 RX DQS gating : PASS
3525 10:00:40.953743 RX DQ/DQS(RDDQC) : PASS
3526 10:00:40.954212 TX DQ/DQS : PASS
3527 10:00:40.957417 RX DATLAT : PASS
3528 10:00:40.957980 RX DQ/DQS(Engine): PASS
3529 10:00:40.960667 TX OE : NO K
3530 10:00:40.961249 All Pass.
3531 10:00:40.961728
3532 10:00:40.963909 DramC Write-DBI off
3533 10:00:40.967051 PER_BANK_REFRESH: Hybrid Mode
3534 10:00:40.967621 TX_TRACKING: ON
3535 10:00:40.977351 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3536 10:00:40.980358 [FAST_K] Save calibration result to emmc
3537 10:00:40.983931 dramc_set_vcore_voltage set vcore to 650000
3538 10:00:40.987126 Read voltage for 600, 5
3539 10:00:40.987578 Vio18 = 0
3540 10:00:40.987933 Vcore = 650000
3541 10:00:40.990727 Vdram = 0
3542 10:00:40.991294 Vddq = 0
3543 10:00:40.991775 Vmddr = 0
3544 10:00:40.997615 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3545 10:00:41.000564 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3546 10:00:41.003722 MEM_TYPE=3, freq_sel=19
3547 10:00:41.007263 sv_algorithm_assistance_LP4_1600
3548 10:00:41.010615 ============ PULL DRAM RESETB DOWN ============
3549 10:00:41.014041 ========== PULL DRAM RESETB DOWN end =========
3550 10:00:41.020461 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3551 10:00:41.024030 ===================================
3552 10:00:41.026704 LPDDR4 DRAM CONFIGURATION
3553 10:00:41.030220 ===================================
3554 10:00:41.030687 EX_ROW_EN[0] = 0x0
3555 10:00:41.033437 EX_ROW_EN[1] = 0x0
3556 10:00:41.033903 LP4Y_EN = 0x0
3557 10:00:41.036720 WORK_FSP = 0x0
3558 10:00:41.037182 WL = 0x2
3559 10:00:41.040332 RL = 0x2
3560 10:00:41.040939 BL = 0x2
3561 10:00:41.043590 RPST = 0x0
3562 10:00:41.044171 RD_PRE = 0x0
3563 10:00:41.046911 WR_PRE = 0x1
3564 10:00:41.047491 WR_PST = 0x0
3565 10:00:41.050369 DBI_WR = 0x0
3566 10:00:41.050936 DBI_RD = 0x0
3567 10:00:41.053382 OTF = 0x1
3568 10:00:41.056829 ===================================
3569 10:00:41.059880 ===================================
3570 10:00:41.060346 ANA top config
3571 10:00:41.063335 ===================================
3572 10:00:41.066276 DLL_ASYNC_EN = 0
3573 10:00:41.069698 ALL_SLAVE_EN = 1
3574 10:00:41.072985 NEW_RANK_MODE = 1
3575 10:00:41.076270 DLL_IDLE_MODE = 1
3576 10:00:41.076831 LP45_APHY_COMB_EN = 1
3577 10:00:41.079778 TX_ODT_DIS = 1
3578 10:00:41.082934 NEW_8X_MODE = 1
3579 10:00:41.086328 ===================================
3580 10:00:41.089646 ===================================
3581 10:00:41.092704 data_rate = 1200
3582 10:00:41.096220 CKR = 1
3583 10:00:41.096570 DQ_P2S_RATIO = 8
3584 10:00:41.099400 ===================================
3585 10:00:41.102730 CA_P2S_RATIO = 8
3586 10:00:41.106347 DQ_CA_OPEN = 0
3587 10:00:41.109533 DQ_SEMI_OPEN = 0
3588 10:00:41.112397 CA_SEMI_OPEN = 0
3589 10:00:41.115998 CA_FULL_RATE = 0
3590 10:00:41.116135 DQ_CKDIV4_EN = 1
3591 10:00:41.118979 CA_CKDIV4_EN = 1
3592 10:00:41.122458 CA_PREDIV_EN = 0
3593 10:00:41.125591 PH8_DLY = 0
3594 10:00:41.129045 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3595 10:00:41.132498 DQ_AAMCK_DIV = 4
3596 10:00:41.132623 CA_AAMCK_DIV = 4
3597 10:00:41.135577 CA_ADMCK_DIV = 4
3598 10:00:41.138860 DQ_TRACK_CA_EN = 0
3599 10:00:41.142125 CA_PICK = 600
3600 10:00:41.145656 CA_MCKIO = 600
3601 10:00:41.148887 MCKIO_SEMI = 0
3602 10:00:41.152094 PLL_FREQ = 2288
3603 10:00:41.152213 DQ_UI_PI_RATIO = 32
3604 10:00:41.155421 CA_UI_PI_RATIO = 0
3605 10:00:41.158670 ===================================
3606 10:00:41.162013 ===================================
3607 10:00:41.165319 memory_type:LPDDR4
3608 10:00:41.168813 GP_NUM : 10
3609 10:00:41.168932 SRAM_EN : 1
3610 10:00:41.172015 MD32_EN : 0
3611 10:00:41.175266 ===================================
3612 10:00:41.178529 [ANA_INIT] >>>>>>>>>>>>>>
3613 10:00:41.178693 <<<<<< [CONFIGURE PHASE]: ANA_TX
3614 10:00:41.181984 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3615 10:00:41.185276 ===================================
3616 10:00:41.188641 data_rate = 1200,PCW = 0X5800
3617 10:00:41.192151 ===================================
3618 10:00:41.195190 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3619 10:00:41.201854 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3620 10:00:41.208467 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3621 10:00:41.211799 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3622 10:00:41.215143 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3623 10:00:41.218564 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3624 10:00:41.222173 [ANA_INIT] flow start
3625 10:00:41.222382 [ANA_INIT] PLL >>>>>>>>
3626 10:00:41.225487 [ANA_INIT] PLL <<<<<<<<
3627 10:00:41.228523 [ANA_INIT] MIDPI >>>>>>>>
3628 10:00:41.228755 [ANA_INIT] MIDPI <<<<<<<<
3629 10:00:41.232252 [ANA_INIT] DLL >>>>>>>>
3630 10:00:41.235347 [ANA_INIT] flow end
3631 10:00:41.238734 ============ LP4 DIFF to SE enter ============
3632 10:00:41.242186 ============ LP4 DIFF to SE exit ============
3633 10:00:41.245375 [ANA_INIT] <<<<<<<<<<<<<
3634 10:00:41.248924 [Flow] Enable top DCM control >>>>>
3635 10:00:41.251957 [Flow] Enable top DCM control <<<<<
3636 10:00:41.255775 Enable DLL master slave shuffle
3637 10:00:41.258886 ==============================================================
3638 10:00:41.262026 Gating Mode config
3639 10:00:41.268485 ==============================================================
3640 10:00:41.269074 Config description:
3641 10:00:41.278542 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3642 10:00:41.285254 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3643 10:00:41.292005 SELPH_MODE 0: By rank 1: By Phase
3644 10:00:41.295265 ==============================================================
3645 10:00:41.298204 GAT_TRACK_EN = 1
3646 10:00:41.301962 RX_GATING_MODE = 2
3647 10:00:41.305248 RX_GATING_TRACK_MODE = 2
3648 10:00:41.308611 SELPH_MODE = 1
3649 10:00:41.311942 PICG_EARLY_EN = 1
3650 10:00:41.315024 VALID_LAT_VALUE = 1
3651 10:00:41.318337 ==============================================================
3652 10:00:41.321828 Enter into Gating configuration >>>>
3653 10:00:41.325138 Exit from Gating configuration <<<<
3654 10:00:41.328069 Enter into DVFS_PRE_config >>>>>
3655 10:00:41.341440 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3656 10:00:41.344899 Exit from DVFS_PRE_config <<<<<
3657 10:00:41.348220 Enter into PICG configuration >>>>
3658 10:00:41.351567 Exit from PICG configuration <<<<
3659 10:00:41.352112 [RX_INPUT] configuration >>>>>
3660 10:00:41.354957 [RX_INPUT] configuration <<<<<
3661 10:00:41.361272 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3662 10:00:41.365043 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3663 10:00:41.371228 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3664 10:00:41.377936 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3665 10:00:41.384677 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3666 10:00:41.391255 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3667 10:00:41.394703 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3668 10:00:41.397866 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3669 10:00:41.404565 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3670 10:00:41.408258 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3671 10:00:41.411141 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3672 10:00:41.414610 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3673 10:00:41.417805 ===================================
3674 10:00:41.420896 LPDDR4 DRAM CONFIGURATION
3675 10:00:41.424432 ===================================
3676 10:00:41.427556 EX_ROW_EN[0] = 0x0
3677 10:00:41.428027 EX_ROW_EN[1] = 0x0
3678 10:00:41.431471 LP4Y_EN = 0x0
3679 10:00:41.432038 WORK_FSP = 0x0
3680 10:00:41.434156 WL = 0x2
3681 10:00:41.434619 RL = 0x2
3682 10:00:41.437508 BL = 0x2
3683 10:00:41.437972 RPST = 0x0
3684 10:00:41.441261 RD_PRE = 0x0
3685 10:00:41.441826 WR_PRE = 0x1
3686 10:00:41.444558 WR_PST = 0x0
3687 10:00:41.445125 DBI_WR = 0x0
3688 10:00:41.447715 DBI_RD = 0x0
3689 10:00:41.448314 OTF = 0x1
3690 10:00:41.450936 ===================================
3691 10:00:41.457415 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3692 10:00:41.461151 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3693 10:00:41.464247 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3694 10:00:41.467582 ===================================
3695 10:00:41.470959 LPDDR4 DRAM CONFIGURATION
3696 10:00:41.474171 ===================================
3697 10:00:41.477196 EX_ROW_EN[0] = 0x10
3698 10:00:41.477661 EX_ROW_EN[1] = 0x0
3699 10:00:41.480654 LP4Y_EN = 0x0
3700 10:00:41.481122 WORK_FSP = 0x0
3701 10:00:41.484010 WL = 0x2
3702 10:00:41.484621 RL = 0x2
3703 10:00:41.487202 BL = 0x2
3704 10:00:41.487665 RPST = 0x0
3705 10:00:41.490844 RD_PRE = 0x0
3706 10:00:41.491391 WR_PRE = 0x1
3707 10:00:41.493980 WR_PST = 0x0
3708 10:00:41.494524 DBI_WR = 0x0
3709 10:00:41.497107 DBI_RD = 0x0
3710 10:00:41.497555 OTF = 0x1
3711 10:00:41.500653 ===================================
3712 10:00:41.507144 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3713 10:00:41.512132 nWR fixed to 30
3714 10:00:41.515426 [ModeRegInit_LP4] CH0 RK0
3715 10:00:41.515969 [ModeRegInit_LP4] CH0 RK1
3716 10:00:41.518879 [ModeRegInit_LP4] CH1 RK0
3717 10:00:41.521993 [ModeRegInit_LP4] CH1 RK1
3718 10:00:41.522537 match AC timing 16
3719 10:00:41.528360 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3720 10:00:41.532042 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3721 10:00:41.535505 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3722 10:00:41.542254 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3723 10:00:41.545200 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3724 10:00:41.545745 ==
3725 10:00:41.548794 Dram Type= 6, Freq= 0, CH_0, rank 0
3726 10:00:41.552166 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3727 10:00:41.552852 ==
3728 10:00:41.558640 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3729 10:00:41.565120 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3730 10:00:41.568488 [CA 0] Center 35 (5~66) winsize 62
3731 10:00:41.571756 [CA 1] Center 35 (5~66) winsize 62
3732 10:00:41.574995 [CA 2] Center 34 (4~65) winsize 62
3733 10:00:41.578306 [CA 3] Center 34 (4~65) winsize 62
3734 10:00:41.581299 [CA 4] Center 33 (3~64) winsize 62
3735 10:00:41.584725 [CA 5] Center 33 (3~64) winsize 62
3736 10:00:41.585281
3737 10:00:41.588228 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3738 10:00:41.588947
3739 10:00:41.591600 [CATrainingPosCal] consider 1 rank data
3740 10:00:41.594940 u2DelayCellTimex100 = 270/100 ps
3741 10:00:41.597948 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3742 10:00:41.601405 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3743 10:00:41.604590 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3744 10:00:41.608053 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3745 10:00:41.614607 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3746 10:00:41.617771 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3747 10:00:41.618323
3748 10:00:41.621026 CA PerBit enable=1, Macro0, CA PI delay=33
3749 10:00:41.621477
3750 10:00:41.624323 [CBTSetCACLKResult] CA Dly = 33
3751 10:00:41.624912 CS Dly: 4 (0~35)
3752 10:00:41.625274 ==
3753 10:00:41.627530 Dram Type= 6, Freq= 0, CH_0, rank 1
3754 10:00:41.634628 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3755 10:00:41.635195 ==
3756 10:00:41.637968 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3757 10:00:41.644364 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3758 10:00:41.647345 [CA 0] Center 36 (6~66) winsize 61
3759 10:00:41.650868 [CA 1] Center 35 (5~66) winsize 62
3760 10:00:41.654189 [CA 2] Center 34 (4~65) winsize 62
3761 10:00:41.657204 [CA 3] Center 34 (4~65) winsize 62
3762 10:00:41.660692 [CA 4] Center 33 (3~64) winsize 62
3763 10:00:41.664079 [CA 5] Center 33 (2~64) winsize 63
3764 10:00:41.664675
3765 10:00:41.667446 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3766 10:00:41.668047
3767 10:00:41.670499 [CATrainingPosCal] consider 2 rank data
3768 10:00:41.674207 u2DelayCellTimex100 = 270/100 ps
3769 10:00:41.677432 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3770 10:00:41.680370 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3771 10:00:41.687253 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3772 10:00:41.690350 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3773 10:00:41.693877 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3774 10:00:41.696986 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3775 10:00:41.697512
3776 10:00:41.700530 CA PerBit enable=1, Macro0, CA PI delay=33
3777 10:00:41.701005
3778 10:00:41.703509 [CBTSetCACLKResult] CA Dly = 33
3779 10:00:41.703959 CS Dly: 5 (0~37)
3780 10:00:41.706999
3781 10:00:41.710234 ----->DramcWriteLeveling(PI) begin...
3782 10:00:41.710690 ==
3783 10:00:41.713957 Dram Type= 6, Freq= 0, CH_0, rank 0
3784 10:00:41.716713 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3785 10:00:41.717171 ==
3786 10:00:41.720463 Write leveling (Byte 0): 32 => 32
3787 10:00:41.723616 Write leveling (Byte 1): 31 => 31
3788 10:00:41.727031 DramcWriteLeveling(PI) end<-----
3789 10:00:41.727577
3790 10:00:41.727937 ==
3791 10:00:41.730055 Dram Type= 6, Freq= 0, CH_0, rank 0
3792 10:00:41.733381 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3793 10:00:41.733850 ==
3794 10:00:41.736953 [Gating] SW mode calibration
3795 10:00:41.743674 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3796 10:00:41.749963 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3797 10:00:41.753410 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3798 10:00:41.756795 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3799 10:00:41.763277 0 5 8 | B1->B0 | 3232 3030 | 0 0 | (0 1) (0 0)
3800 10:00:41.766632 0 5 12 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
3801 10:00:41.769557 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3802 10:00:41.776421 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3803 10:00:41.779405 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3804 10:00:41.782878 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3805 10:00:41.789507 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3806 10:00:41.792981 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3807 10:00:41.796266 0 6 8 | B1->B0 | 2a2a 2f2f | 0 0 | (0 0) (0 0)
3808 10:00:41.803043 0 6 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3809 10:00:41.806463 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3810 10:00:41.809955 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3811 10:00:41.813254 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3812 10:00:41.819812 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3813 10:00:41.822955 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3814 10:00:41.826439 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3815 10:00:41.832956 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3816 10:00:41.836346 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3817 10:00:41.839728 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3818 10:00:41.846410 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3819 10:00:41.849696 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3820 10:00:41.853045 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3821 10:00:41.859668 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3822 10:00:41.862573 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3823 10:00:41.866086 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3824 10:00:41.872894 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3825 10:00:41.875894 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3826 10:00:41.879058 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3827 10:00:41.885871 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3828 10:00:41.889548 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3829 10:00:41.892298 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3830 10:00:41.898846 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3831 10:00:41.902714 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3832 10:00:41.905459 Total UI for P1: 0, mck2ui 16
3833 10:00:41.908874 best dqsien dly found for B0: ( 0, 9, 6)
3834 10:00:41.912196 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3835 10:00:41.918841 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3836 10:00:41.922170 Total UI for P1: 0, mck2ui 16
3837 10:00:41.925463 best dqsien dly found for B1: ( 0, 9, 10)
3838 10:00:41.928628 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
3839 10:00:41.932079 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
3840 10:00:41.932682
3841 10:00:41.935116 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
3842 10:00:41.938654 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
3843 10:00:41.942056 [Gating] SW calibration Done
3844 10:00:41.942610 ==
3845 10:00:41.945249 Dram Type= 6, Freq= 0, CH_0, rank 0
3846 10:00:41.948572 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3847 10:00:41.949125 ==
3848 10:00:41.951712 RX Vref Scan: 0
3849 10:00:41.952260
3850 10:00:41.954866 RX Vref 0 -> 0, step: 1
3851 10:00:41.955314
3852 10:00:41.955664 RX Delay -230 -> 252, step: 16
3853 10:00:41.961557 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3854 10:00:41.965070 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3855 10:00:41.968355 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3856 10:00:41.971621 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3857 10:00:41.978001 iDelay=218, Bit 4, Center 41 (-134 ~ 217) 352
3858 10:00:41.981495 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
3859 10:00:41.984615 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3860 10:00:41.987939 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3861 10:00:41.991490 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3862 10:00:41.997999 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3863 10:00:42.001168 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3864 10:00:42.004666 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3865 10:00:42.007901 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3866 10:00:42.014738 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3867 10:00:42.017941 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3868 10:00:42.021121 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3869 10:00:42.021579 ==
3870 10:00:42.024683 Dram Type= 6, Freq= 0, CH_0, rank 0
3871 10:00:42.027900 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3872 10:00:42.030970 ==
3873 10:00:42.031432 DQS Delay:
3874 10:00:42.031903 DQS0 = 0, DQS1 = 0
3875 10:00:42.034242 DQM Delay:
3876 10:00:42.034695 DQM0 = 38, DQM1 = 33
3877 10:00:42.037843 DQ Delay:
3878 10:00:42.041101 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3879 10:00:42.041727 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
3880 10:00:42.044220 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3881 10:00:42.050929 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3882 10:00:42.051382
3883 10:00:42.051735
3884 10:00:42.052063 ==
3885 10:00:42.054304 Dram Type= 6, Freq= 0, CH_0, rank 0
3886 10:00:42.057590 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3887 10:00:42.058098 ==
3888 10:00:42.058463
3889 10:00:42.058792
3890 10:00:42.061155 TX Vref Scan disable
3891 10:00:42.061607 == TX Byte 0 ==
3892 10:00:42.067791 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
3893 10:00:42.070815 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
3894 10:00:42.071270 == TX Byte 1 ==
3895 10:00:42.077159 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
3896 10:00:42.080269 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
3897 10:00:42.080368 ==
3898 10:00:42.083624 Dram Type= 6, Freq= 0, CH_0, rank 0
3899 10:00:42.087133 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3900 10:00:42.087217 ==
3901 10:00:42.087281
3902 10:00:42.087339
3903 10:00:42.090204 TX Vref Scan disable
3904 10:00:42.093742 == TX Byte 0 ==
3905 10:00:42.096873 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
3906 10:00:42.100257 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
3907 10:00:42.103722 == TX Byte 1 ==
3908 10:00:42.107084 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
3909 10:00:42.110198 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
3910 10:00:42.113498
3911 10:00:42.113581 [DATLAT]
3912 10:00:42.113649 Freq=600, CH0 RK0
3913 10:00:42.113723
3914 10:00:42.116922 DATLAT Default: 0x9
3915 10:00:42.117009 0, 0xFFFF, sum = 0
3916 10:00:42.120040 1, 0xFFFF, sum = 0
3917 10:00:42.120122 2, 0xFFFF, sum = 0
3918 10:00:42.123400 3, 0xFFFF, sum = 0
3919 10:00:42.126708 4, 0xFFFF, sum = 0
3920 10:00:42.126789 5, 0xFFFF, sum = 0
3921 10:00:42.130226 6, 0xFFFF, sum = 0
3922 10:00:42.130311 7, 0x0, sum = 1
3923 10:00:42.130375 8, 0x0, sum = 2
3924 10:00:42.133459 9, 0x0, sum = 3
3925 10:00:42.133552 10, 0x0, sum = 4
3926 10:00:42.136630 best_step = 8
3927 10:00:42.136713
3928 10:00:42.136777 ==
3929 10:00:42.139880 Dram Type= 6, Freq= 0, CH_0, rank 0
3930 10:00:42.143261 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3931 10:00:42.143344 ==
3932 10:00:42.146584 RX Vref Scan: 1
3933 10:00:42.146665
3934 10:00:42.146728 RX Vref 0 -> 0, step: 1
3935 10:00:42.146787
3936 10:00:42.150100 RX Delay -195 -> 252, step: 8
3937 10:00:42.150182
3938 10:00:42.153622 Set Vref, RX VrefLevel [Byte0]: 49
3939 10:00:42.156497 [Byte1]: 46
3940 10:00:42.160634
3941 10:00:42.160719 Final RX Vref Byte 0 = 49 to rank0
3942 10:00:42.163746 Final RX Vref Byte 1 = 46 to rank0
3943 10:00:42.167092 Final RX Vref Byte 0 = 49 to rank1
3944 10:00:42.170534 Final RX Vref Byte 1 = 46 to rank1==
3945 10:00:42.173850 Dram Type= 6, Freq= 0, CH_0, rank 0
3946 10:00:42.180240 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3947 10:00:42.180327 ==
3948 10:00:42.180392 DQS Delay:
3949 10:00:42.183597 DQS0 = 0, DQS1 = 0
3950 10:00:42.183680 DQM Delay:
3951 10:00:42.183744 DQM0 = 40, DQM1 = 32
3952 10:00:42.187093 DQ Delay:
3953 10:00:42.190218 DQ0 =32, DQ1 =40, DQ2 =40, DQ3 =36
3954 10:00:42.193768 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
3955 10:00:42.196936 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =24
3956 10:00:42.200355 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =44
3957 10:00:42.200464
3958 10:00:42.200581
3959 10:00:42.207112 [DQSOSCAuto] RK0, (LSB)MR18= 0x5454, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
3960 10:00:42.210363 CH0 RK0: MR19=808, MR18=5454
3961 10:00:42.216960 CH0_RK0: MR19=0x808, MR18=0x5454, DQSOSC=393, MR23=63, INC=169, DEC=113
3962 10:00:42.217076
3963 10:00:42.220167 ----->DramcWriteLeveling(PI) begin...
3964 10:00:42.220257 ==
3965 10:00:42.223476 Dram Type= 6, Freq= 0, CH_0, rank 1
3966 10:00:42.226771 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3967 10:00:42.226854 ==
3968 10:00:42.230200 Write leveling (Byte 0): 31 => 31
3969 10:00:42.233578 Write leveling (Byte 1): 31 => 31
3970 10:00:42.236931 DramcWriteLeveling(PI) end<-----
3971 10:00:42.237014
3972 10:00:42.237091 ==
3973 10:00:42.240282 Dram Type= 6, Freq= 0, CH_0, rank 1
3974 10:00:42.243335 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3975 10:00:42.243425 ==
3976 10:00:42.246745 [Gating] SW mode calibration
3977 10:00:42.253766 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3978 10:00:42.260014 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3979 10:00:42.263227 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3980 10:00:42.269766 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3981 10:00:42.273109 0 5 8 | B1->B0 | 3232 3333 | 1 0 | (1 1) (0 1)
3982 10:00:42.276497 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 10:00:42.283451 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 10:00:42.286970 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 10:00:42.289992 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 10:00:42.296699 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 10:00:42.299753 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 10:00:42.303223 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 10:00:42.306692 0 6 8 | B1->B0 | 2b2b 3131 | 0 1 | (0 0) (0 0)
3990 10:00:42.313266 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 10:00:42.316445 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 10:00:42.319790 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 10:00:42.326496 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 10:00:42.329970 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 10:00:42.332924 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 10:00:42.339557 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 10:00:42.342958 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3998 10:00:42.346399 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 10:00:42.352933 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 10:00:42.356285 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 10:00:42.359665 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 10:00:42.366522 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 10:00:42.369609 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 10:00:42.373214 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 10:00:42.379646 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 10:00:42.383138 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 10:00:42.386217 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 10:00:42.392876 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 10:00:42.396308 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 10:00:42.399702 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 10:00:42.406123 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 10:00:42.409211 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 10:00:42.412614 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4014 10:00:42.416132 Total UI for P1: 0, mck2ui 16
4015 10:00:42.419389 best dqsien dly found for B0: ( 0, 9, 6)
4016 10:00:42.426032 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4017 10:00:42.429329 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 10:00:42.432627 Total UI for P1: 0, mck2ui 16
4019 10:00:42.435930 best dqsien dly found for B1: ( 0, 9, 10)
4020 10:00:42.439032 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4021 10:00:42.442303 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4022 10:00:42.442757
4023 10:00:42.445802 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4024 10:00:42.449061 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4025 10:00:42.452335 [Gating] SW calibration Done
4026 10:00:42.452846 ==
4027 10:00:42.455338 Dram Type= 6, Freq= 0, CH_0, rank 1
4028 10:00:42.462298 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4029 10:00:42.462854 ==
4030 10:00:42.463216 RX Vref Scan: 0
4031 10:00:42.463548
4032 10:00:42.465312 RX Vref 0 -> 0, step: 1
4033 10:00:42.465765
4034 10:00:42.468816 RX Delay -230 -> 252, step: 16
4035 10:00:42.472022 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4036 10:00:42.475148 iDelay=218, Bit 1, Center 41 (-134 ~ 217) 352
4037 10:00:42.478703 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4038 10:00:42.485441 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4039 10:00:42.488750 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4040 10:00:42.491928 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4041 10:00:42.495708 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4042 10:00:42.501733 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4043 10:00:42.505145 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4044 10:00:42.508956 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4045 10:00:42.512275 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4046 10:00:42.515499 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4047 10:00:42.521736 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4048 10:00:42.525172 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4049 10:00:42.528243 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4050 10:00:42.531697 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4051 10:00:42.534817 ==
4052 10:00:42.538679 Dram Type= 6, Freq= 0, CH_0, rank 1
4053 10:00:42.541455 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4054 10:00:42.541914 ==
4055 10:00:42.542274 DQS Delay:
4056 10:00:42.544907 DQS0 = 0, DQS1 = 0
4057 10:00:42.545360 DQM Delay:
4058 10:00:42.548140 DQM0 = 40, DQM1 = 31
4059 10:00:42.548644 DQ Delay:
4060 10:00:42.551612 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4061 10:00:42.554820 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4062 10:00:42.558404 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4063 10:00:42.561430 DQ12 =41, DQ13 =33, DQ14 =41, DQ15 =41
4064 10:00:42.561942
4065 10:00:42.562306
4066 10:00:42.562636 ==
4067 10:00:42.564729 Dram Type= 6, Freq= 0, CH_0, rank 1
4068 10:00:42.568298 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4069 10:00:42.568988 ==
4070 10:00:42.569370
4071 10:00:42.569702
4072 10:00:42.571402 TX Vref Scan disable
4073 10:00:42.575099 == TX Byte 0 ==
4074 10:00:42.578551 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4075 10:00:42.581457 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4076 10:00:42.585156 == TX Byte 1 ==
4077 10:00:42.588137 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4078 10:00:42.591411 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4079 10:00:42.591968 ==
4080 10:00:42.594656 Dram Type= 6, Freq= 0, CH_0, rank 1
4081 10:00:42.601099 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4082 10:00:42.601652 ==
4083 10:00:42.602019
4084 10:00:42.602353
4085 10:00:42.602684 TX Vref Scan disable
4086 10:00:42.605400 == TX Byte 0 ==
4087 10:00:42.608818 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4088 10:00:42.611966 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4089 10:00:42.615630 == TX Byte 1 ==
4090 10:00:42.618821 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4091 10:00:42.622253 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4092 10:00:42.625568
4093 10:00:42.626122 [DATLAT]
4094 10:00:42.626490 Freq=600, CH0 RK1
4095 10:00:42.626828
4096 10:00:42.628568 DATLAT Default: 0x8
4097 10:00:42.629027 0, 0xFFFF, sum = 0
4098 10:00:42.632161 1, 0xFFFF, sum = 0
4099 10:00:42.632785 2, 0xFFFF, sum = 0
4100 10:00:42.635008 3, 0xFFFF, sum = 0
4101 10:00:42.638398 4, 0xFFFF, sum = 0
4102 10:00:42.638857 5, 0xFFFF, sum = 0
4103 10:00:42.641795 6, 0xFFFF, sum = 0
4104 10:00:42.642361 7, 0x0, sum = 1
4105 10:00:42.642732 8, 0x0, sum = 2
4106 10:00:42.645436 9, 0x0, sum = 3
4107 10:00:42.646000 10, 0x0, sum = 4
4108 10:00:42.648681 best_step = 8
4109 10:00:42.649242
4110 10:00:42.649608 ==
4111 10:00:42.652041 Dram Type= 6, Freq= 0, CH_0, rank 1
4112 10:00:42.655075 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4113 10:00:42.655634 ==
4114 10:00:42.658736 RX Vref Scan: 0
4115 10:00:42.659296
4116 10:00:42.659657 RX Vref 0 -> 0, step: 1
4117 10:00:42.659993
4118 10:00:42.661341 RX Delay -195 -> 252, step: 8
4119 10:00:42.668994 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4120 10:00:42.672208 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4121 10:00:42.675556 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4122 10:00:42.678803 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4123 10:00:42.685615 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4124 10:00:42.688483 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4125 10:00:42.691999 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4126 10:00:42.695019 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4127 10:00:42.698703 iDelay=205, Bit 8, Center 24 (-123 ~ 172) 296
4128 10:00:42.705186 iDelay=205, Bit 9, Center 16 (-131 ~ 164) 296
4129 10:00:42.708747 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4130 10:00:42.712398 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4131 10:00:42.715312 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4132 10:00:42.722203 iDelay=205, Bit 13, Center 36 (-115 ~ 188) 304
4133 10:00:42.725178 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4134 10:00:42.728765 iDelay=205, Bit 15, Center 40 (-107 ~ 188) 296
4135 10:00:42.729319 ==
4136 10:00:42.731907 Dram Type= 6, Freq= 0, CH_0, rank 1
4137 10:00:42.735182 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4138 10:00:42.738406 ==
4139 10:00:42.738857 DQS Delay:
4140 10:00:42.739213 DQS0 = 0, DQS1 = 0
4141 10:00:42.741641 DQM Delay:
4142 10:00:42.742092 DQM0 = 41, DQM1 = 32
4143 10:00:42.745363 DQ Delay:
4144 10:00:42.748689 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
4145 10:00:42.749235 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4146 10:00:42.751793 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =24
4147 10:00:42.755119 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =40
4148 10:00:42.758411
4149 10:00:42.758954
4150 10:00:42.765187 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a6a, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4151 10:00:42.768565 CH0 RK1: MR19=808, MR18=6A6A
4152 10:00:42.774919 CH0_RK1: MR19=0x808, MR18=0x6A6A, DQSOSC=389, MR23=63, INC=173, DEC=115
4153 10:00:42.778136 [RxdqsGatingPostProcess] freq 600
4154 10:00:42.781424 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4155 10:00:42.784966 Pre-setting of DQS Precalculation
4156 10:00:42.791422 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4157 10:00:42.791970 ==
4158 10:00:42.794498 Dram Type= 6, Freq= 0, CH_1, rank 0
4159 10:00:42.798175 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4160 10:00:42.798745 ==
4161 10:00:42.804706 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4162 10:00:42.807947 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4163 10:00:42.812470 [CA 0] Center 35 (5~66) winsize 62
4164 10:00:42.815784 [CA 1] Center 35 (4~66) winsize 63
4165 10:00:42.818827 [CA 2] Center 33 (3~64) winsize 62
4166 10:00:42.822394 [CA 3] Center 33 (3~64) winsize 62
4167 10:00:42.825741 [CA 4] Center 33 (2~64) winsize 63
4168 10:00:42.829070 [CA 5] Center 33 (2~64) winsize 63
4169 10:00:42.829620
4170 10:00:42.832055 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4171 10:00:42.832504
4172 10:00:42.835365 [CATrainingPosCal] consider 1 rank data
4173 10:00:42.839029 u2DelayCellTimex100 = 270/100 ps
4174 10:00:42.842701 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4175 10:00:42.849325 CA1 delay=35 (4~66),Diff = 2 PI (19 cell)
4176 10:00:42.852268 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4177 10:00:42.855798 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4178 10:00:42.858733 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4179 10:00:42.862097 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4180 10:00:42.862645
4181 10:00:42.865333 CA PerBit enable=1, Macro0, CA PI delay=33
4182 10:00:42.865780
4183 10:00:42.868872 [CBTSetCACLKResult] CA Dly = 33
4184 10:00:42.869419 CS Dly: 4 (0~35)
4185 10:00:42.872200 ==
4186 10:00:42.875273 Dram Type= 6, Freq= 0, CH_1, rank 1
4187 10:00:42.878560 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4188 10:00:42.879109 ==
4189 10:00:42.881696 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4190 10:00:42.888447 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4191 10:00:42.892342 [CA 0] Center 35 (5~66) winsize 62
4192 10:00:42.895440 [CA 1] Center 34 (4~65) winsize 62
4193 10:00:42.898982 [CA 2] Center 33 (3~64) winsize 62
4194 10:00:42.902615 [CA 3] Center 33 (3~64) winsize 62
4195 10:00:42.905555 [CA 4] Center 33 (2~64) winsize 63
4196 10:00:42.909216 [CA 5] Center 33 (2~64) winsize 63
4197 10:00:42.909767
4198 10:00:42.912199 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4199 10:00:42.912800
4200 10:00:42.915659 [CATrainingPosCal] consider 2 rank data
4201 10:00:42.918901 u2DelayCellTimex100 = 270/100 ps
4202 10:00:42.922341 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4203 10:00:42.928693 CA1 delay=34 (4~65),Diff = 1 PI (9 cell)
4204 10:00:42.932024 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4205 10:00:42.935799 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4206 10:00:42.938751 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4207 10:00:42.942061 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4208 10:00:42.942514
4209 10:00:42.945048 CA PerBit enable=1, Macro0, CA PI delay=33
4210 10:00:42.945498
4211 10:00:42.948603 [CBTSetCACLKResult] CA Dly = 33
4212 10:00:42.949146 CS Dly: 4 (0~36)
4213 10:00:42.951838
4214 10:00:42.955358 ----->DramcWriteLeveling(PI) begin...
4215 10:00:42.955931 ==
4216 10:00:42.958902 Dram Type= 6, Freq= 0, CH_1, rank 0
4217 10:00:42.961998 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4218 10:00:42.962581 ==
4219 10:00:42.965084 Write leveling (Byte 0): 26 => 26
4220 10:00:42.968895 Write leveling (Byte 1): 27 => 27
4221 10:00:42.972037 DramcWriteLeveling(PI) end<-----
4222 10:00:42.972746
4223 10:00:42.973117 ==
4224 10:00:42.975303 Dram Type= 6, Freq= 0, CH_1, rank 0
4225 10:00:42.978881 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4226 10:00:42.979430 ==
4227 10:00:42.981966 [Gating] SW mode calibration
4228 10:00:42.988925 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4229 10:00:42.995043 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4230 10:00:42.998313 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4231 10:00:43.001652 0 5 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (0 0)
4232 10:00:43.008307 0 5 8 | B1->B0 | 2f2f 2c2c | 0 0 | (0 0) (0 0)
4233 10:00:43.011976 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4234 10:00:43.014881 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 10:00:43.021466 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 10:00:43.024880 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4237 10:00:43.028055 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4238 10:00:43.034663 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 10:00:43.038215 0 6 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
4240 10:00:43.041632 0 6 8 | B1->B0 | 3535 4444 | 0 0 | (1 1) (0 0)
4241 10:00:43.044971 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 10:00:43.051553 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 10:00:43.054637 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 10:00:43.058046 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 10:00:43.064900 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 10:00:43.068075 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 10:00:43.071519 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 10:00:43.077917 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4249 10:00:43.080974 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 10:00:43.084644 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 10:00:43.090858 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 10:00:43.094607 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 10:00:43.097430 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 10:00:43.104079 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 10:00:43.107420 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 10:00:43.110943 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 10:00:43.117472 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 10:00:43.120907 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 10:00:43.124159 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 10:00:43.130466 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 10:00:43.133959 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 10:00:43.137091 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 10:00:43.144273 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 10:00:43.147266 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4265 10:00:43.150918 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4266 10:00:43.153590 Total UI for P1: 0, mck2ui 16
4267 10:00:43.157079 best dqsien dly found for B0: ( 0, 9, 8)
4268 10:00:43.160689 Total UI for P1: 0, mck2ui 16
4269 10:00:43.163772 best dqsien dly found for B1: ( 0, 9, 8)
4270 10:00:43.167163 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4271 10:00:43.170557 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4272 10:00:43.171105
4273 10:00:43.177014 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4274 10:00:43.180548 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4275 10:00:43.183478 [Gating] SW calibration Done
4276 10:00:43.183927 ==
4277 10:00:43.186938 Dram Type= 6, Freq= 0, CH_1, rank 0
4278 10:00:43.190150 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4279 10:00:43.190702 ==
4280 10:00:43.191068 RX Vref Scan: 0
4281 10:00:43.191398
4282 10:00:43.193176 RX Vref 0 -> 0, step: 1
4283 10:00:43.193628
4284 10:00:43.196763 RX Delay -230 -> 252, step: 16
4285 10:00:43.200036 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4286 10:00:43.203573 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4287 10:00:43.209927 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4288 10:00:43.213173 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4289 10:00:43.216794 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4290 10:00:43.219993 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4291 10:00:43.226586 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4292 10:00:43.229780 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4293 10:00:43.232796 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4294 10:00:43.236288 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4295 10:00:43.242936 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4296 10:00:43.246294 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4297 10:00:43.249682 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4298 10:00:43.252754 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4299 10:00:43.259613 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4300 10:00:43.263000 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4301 10:00:43.263675 ==
4302 10:00:43.266114 Dram Type= 6, Freq= 0, CH_1, rank 0
4303 10:00:43.269695 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4304 10:00:43.270240 ==
4305 10:00:43.272947 DQS Delay:
4306 10:00:43.273494 DQS0 = 0, DQS1 = 0
4307 10:00:43.273934 DQM Delay:
4308 10:00:43.276076 DQM0 = 39, DQM1 = 30
4309 10:00:43.276672 DQ Delay:
4310 10:00:43.279499 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4311 10:00:43.282525 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4312 10:00:43.285788 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4313 10:00:43.289156 DQ12 =33, DQ13 =49, DQ14 =33, DQ15 =41
4314 10:00:43.289601
4315 10:00:43.289949
4316 10:00:43.290269 ==
4317 10:00:43.292604 Dram Type= 6, Freq= 0, CH_1, rank 0
4318 10:00:43.299027 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4319 10:00:43.299562 ==
4320 10:00:43.299920
4321 10:00:43.300242
4322 10:00:43.300620 TX Vref Scan disable
4323 10:00:43.302527 == TX Byte 0 ==
4324 10:00:43.306581 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4325 10:00:43.312856 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4326 10:00:43.313405 == TX Byte 1 ==
4327 10:00:43.316314 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4328 10:00:43.322794 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4329 10:00:43.323342 ==
4330 10:00:43.325975 Dram Type= 6, Freq= 0, CH_1, rank 0
4331 10:00:43.329122 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4332 10:00:43.329572 ==
4333 10:00:43.329923
4334 10:00:43.330251
4335 10:00:43.332710 TX Vref Scan disable
4336 10:00:43.335933 == TX Byte 0 ==
4337 10:00:43.339333 Update DQ dly =570 (2 ,1, 26) DQ OEN =(1 ,6)
4338 10:00:43.342481 Update DQM dly =570 (2 ,1, 26) DQM OEN =(1 ,6)
4339 10:00:43.345986 == TX Byte 1 ==
4340 10:00:43.349111 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4341 10:00:43.352223 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4342 10:00:43.352698
4343 10:00:43.353049 [DATLAT]
4344 10:00:43.355906 Freq=600, CH1 RK0
4345 10:00:43.356707
4346 10:00:43.357071 DATLAT Default: 0x9
4347 10:00:43.358927 0, 0xFFFF, sum = 0
4348 10:00:43.362102 1, 0xFFFF, sum = 0
4349 10:00:43.362182 2, 0xFFFF, sum = 0
4350 10:00:43.365553 3, 0xFFFF, sum = 0
4351 10:00:43.365711 4, 0xFFFF, sum = 0
4352 10:00:43.369124 5, 0xFFFF, sum = 0
4353 10:00:43.369284 6, 0xFFFF, sum = 0
4354 10:00:43.372281 7, 0x0, sum = 1
4355 10:00:43.372444 8, 0x0, sum = 2
4356 10:00:43.372533 9, 0x0, sum = 3
4357 10:00:43.375536 10, 0x0, sum = 4
4358 10:00:43.375704 best_step = 8
4359 10:00:43.375782
4360 10:00:43.375851 ==
4361 10:00:43.379059 Dram Type= 6, Freq= 0, CH_1, rank 0
4362 10:00:43.385453 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4363 10:00:43.385646 ==
4364 10:00:43.385741 RX Vref Scan: 1
4365 10:00:43.385822
4366 10:00:43.389149 RX Vref 0 -> 0, step: 1
4367 10:00:43.389345
4368 10:00:43.392207 RX Delay -195 -> 252, step: 8
4369 10:00:43.392403
4370 10:00:43.395522 Set Vref, RX VrefLevel [Byte0]: 58
4371 10:00:43.398655 [Byte1]: 48
4372 10:00:43.398886
4373 10:00:43.401940 Final RX Vref Byte 0 = 58 to rank0
4374 10:00:43.405694 Final RX Vref Byte 1 = 48 to rank0
4375 10:00:43.408755 Final RX Vref Byte 0 = 58 to rank1
4376 10:00:43.412160 Final RX Vref Byte 1 = 48 to rank1==
4377 10:00:43.415614 Dram Type= 6, Freq= 0, CH_1, rank 0
4378 10:00:43.418729 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4379 10:00:43.419053 ==
4380 10:00:43.422099 DQS Delay:
4381 10:00:43.422484 DQS0 = 0, DQS1 = 0
4382 10:00:43.425175 DQM Delay:
4383 10:00:43.425462 DQM0 = 37, DQM1 = 30
4384 10:00:43.425746 DQ Delay:
4385 10:00:43.429093 DQ0 =44, DQ1 =28, DQ2 =28, DQ3 =36
4386 10:00:43.431944 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =36
4387 10:00:43.435459 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4388 10:00:43.439103 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4389 10:00:43.439647
4390 10:00:43.440000
4391 10:00:43.448765 [DQSOSCAuto] RK0, (LSB)MR18= 0x7474, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
4392 10:00:43.451921 CH1 RK0: MR19=808, MR18=7474
4393 10:00:43.458860 CH1_RK0: MR19=0x808, MR18=0x7474, DQSOSC=388, MR23=63, INC=174, DEC=116
4394 10:00:43.459405
4395 10:00:43.461603 ----->DramcWriteLeveling(PI) begin...
4396 10:00:43.462055 ==
4397 10:00:43.465497 Dram Type= 6, Freq= 0, CH_1, rank 1
4398 10:00:43.468906 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4399 10:00:43.469455 ==
4400 10:00:43.471708 Write leveling (Byte 0): 28 => 28
4401 10:00:43.475389 Write leveling (Byte 1): 27 => 27
4402 10:00:43.478497 DramcWriteLeveling(PI) end<-----
4403 10:00:43.479041
4404 10:00:43.479390 ==
4405 10:00:43.481822 Dram Type= 6, Freq= 0, CH_1, rank 1
4406 10:00:43.484830 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4407 10:00:43.485281 ==
4408 10:00:43.488164 [Gating] SW mode calibration
4409 10:00:43.494914 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4410 10:00:43.501409 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4411 10:00:43.505153 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4412 10:00:43.508327 0 5 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
4413 10:00:43.514916 0 5 8 | B1->B0 | 2f2f 2323 | 1 0 | (0 0) (0 0)
4414 10:00:43.518374 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 10:00:43.521508 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 10:00:43.528015 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 10:00:43.531095 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 10:00:43.534864 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 10:00:43.541176 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 10:00:43.545129 0 6 4 | B1->B0 | 2525 2c2c | 0 0 | (0 0) (0 0)
4421 10:00:43.547827 0 6 8 | B1->B0 | 3131 4242 | 0 0 | (1 1) (0 0)
4422 10:00:43.554277 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 10:00:43.558105 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 10:00:43.561465 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 10:00:43.567946 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 10:00:43.571123 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 10:00:43.574413 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 10:00:43.580737 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4429 10:00:43.583984 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4430 10:00:43.587441 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 10:00:43.594084 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 10:00:43.597222 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 10:00:43.600867 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 10:00:43.607236 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 10:00:43.610545 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 10:00:43.614334 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 10:00:43.620781 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 10:00:43.623894 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 10:00:43.627404 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 10:00:43.633776 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 10:00:43.637034 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 10:00:43.640496 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 10:00:43.643999 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 10:00:43.650570 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 10:00:43.653956 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 10:00:43.657008 Total UI for P1: 0, mck2ui 16
4447 10:00:43.660317 best dqsien dly found for B0: ( 0, 9, 6)
4448 10:00:43.663362 Total UI for P1: 0, mck2ui 16
4449 10:00:43.666778 best dqsien dly found for B1: ( 0, 9, 6)
4450 10:00:43.670139 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4451 10:00:43.673536 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4452 10:00:43.673728
4453 10:00:43.676873 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4454 10:00:43.680012 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4455 10:00:43.683186 [Gating] SW calibration Done
4456 10:00:43.683322 ==
4457 10:00:43.686471 Dram Type= 6, Freq= 0, CH_1, rank 1
4458 10:00:43.693232 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4459 10:00:43.693339 ==
4460 10:00:43.693447 RX Vref Scan: 0
4461 10:00:43.693547
4462 10:00:43.696394 RX Vref 0 -> 0, step: 1
4463 10:00:43.696500
4464 10:00:43.699868 RX Delay -230 -> 252, step: 16
4465 10:00:43.702875 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4466 10:00:43.706407 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4467 10:00:43.709563 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4468 10:00:43.716122 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4469 10:00:43.719481 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4470 10:00:43.722796 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4471 10:00:43.726095 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4472 10:00:43.732867 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4473 10:00:43.736007 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4474 10:00:43.739474 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4475 10:00:43.742657 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4476 10:00:43.746045 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4477 10:00:43.752856 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4478 10:00:43.756004 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4479 10:00:43.759295 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4480 10:00:43.762509 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4481 10:00:43.766060 ==
4482 10:00:43.769145 Dram Type= 6, Freq= 0, CH_1, rank 1
4483 10:00:43.772742 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4484 10:00:43.772823 ==
4485 10:00:43.772887 DQS Delay:
4486 10:00:43.775776 DQS0 = 0, DQS1 = 0
4487 10:00:43.775855 DQM Delay:
4488 10:00:43.779301 DQM0 = 42, DQM1 = 34
4489 10:00:43.779381 DQ Delay:
4490 10:00:43.782601 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4491 10:00:43.785737 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4492 10:00:43.789082 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4493 10:00:43.792454 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4494 10:00:43.792557
4495 10:00:43.792620
4496 10:00:43.792677 ==
4497 10:00:43.795754 Dram Type= 6, Freq= 0, CH_1, rank 1
4498 10:00:43.799012 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4499 10:00:43.799092 ==
4500 10:00:43.799154
4501 10:00:43.799212
4502 10:00:43.802459 TX Vref Scan disable
4503 10:00:43.805609 == TX Byte 0 ==
4504 10:00:43.808917 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4505 10:00:43.812429 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4506 10:00:43.815668 == TX Byte 1 ==
4507 10:00:43.819065 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4508 10:00:43.822159 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4509 10:00:43.822242 ==
4510 10:00:43.825519 Dram Type= 6, Freq= 0, CH_1, rank 1
4511 10:00:43.832082 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4512 10:00:43.832165 ==
4513 10:00:43.832229
4514 10:00:43.832288
4515 10:00:43.832345 TX Vref Scan disable
4516 10:00:43.836268 == TX Byte 0 ==
4517 10:00:43.839813 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4518 10:00:43.846452 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4519 10:00:43.846538 == TX Byte 1 ==
4520 10:00:43.849630 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4521 10:00:43.853214 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4522 10:00:43.856361
4523 10:00:43.856441 [DATLAT]
4524 10:00:43.856511 Freq=600, CH1 RK1
4525 10:00:43.856574
4526 10:00:43.859754 DATLAT Default: 0x8
4527 10:00:43.859835 0, 0xFFFF, sum = 0
4528 10:00:43.862933 1, 0xFFFF, sum = 0
4529 10:00:43.863016 2, 0xFFFF, sum = 0
4530 10:00:43.866252 3, 0xFFFF, sum = 0
4531 10:00:43.869495 4, 0xFFFF, sum = 0
4532 10:00:43.869581 5, 0xFFFF, sum = 0
4533 10:00:43.872744 6, 0xFFFF, sum = 0
4534 10:00:43.872826 7, 0x0, sum = 1
4535 10:00:43.872891 8, 0x0, sum = 2
4536 10:00:43.876437 9, 0x0, sum = 3
4537 10:00:43.876543 10, 0x0, sum = 4
4538 10:00:43.879523 best_step = 8
4539 10:00:43.879603
4540 10:00:43.879666 ==
4541 10:00:43.882868 Dram Type= 6, Freq= 0, CH_1, rank 1
4542 10:00:43.886121 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4543 10:00:43.886203 ==
4544 10:00:43.889517 RX Vref Scan: 0
4545 10:00:43.889597
4546 10:00:43.889660 RX Vref 0 -> 0, step: 1
4547 10:00:43.889720
4548 10:00:43.892621 RX Delay -195 -> 252, step: 8
4549 10:00:43.900067 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4550 10:00:43.903499 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4551 10:00:43.906770 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4552 10:00:43.909838 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4553 10:00:43.916484 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4554 10:00:43.919810 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4555 10:00:43.923205 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4556 10:00:43.926502 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4557 10:00:43.929768 iDelay=205, Bit 8, Center 16 (-139 ~ 172) 312
4558 10:00:43.936452 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4559 10:00:43.939888 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4560 10:00:43.942955 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4561 10:00:43.946505 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4562 10:00:43.953001 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4563 10:00:43.956519 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4564 10:00:43.959838 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4565 10:00:43.959943 ==
4566 10:00:43.962961 Dram Type= 6, Freq= 0, CH_1, rank 1
4567 10:00:43.969590 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4568 10:00:43.969709 ==
4569 10:00:43.969776 DQS Delay:
4570 10:00:43.969836 DQS0 = 0, DQS1 = 0
4571 10:00:43.972816 DQM Delay:
4572 10:00:43.972897 DQM0 = 37, DQM1 = 30
4573 10:00:43.976181 DQ Delay:
4574 10:00:43.979595 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4575 10:00:43.979676 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4576 10:00:43.982835 DQ8 =16, DQ9 =20, DQ10 =28, DQ11 =20
4577 10:00:43.989428 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4578 10:00:43.989509
4579 10:00:43.989571
4580 10:00:43.996047 [DQSOSCAuto] RK1, (LSB)MR18= 0x5c5c, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
4581 10:00:43.999393 CH1 RK1: MR19=808, MR18=5C5C
4582 10:00:44.005889 CH1_RK1: MR19=0x808, MR18=0x5C5C, DQSOSC=392, MR23=63, INC=170, DEC=113
4583 10:00:44.009328 [RxdqsGatingPostProcess] freq 600
4584 10:00:44.012543 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4585 10:00:44.016016 Pre-setting of DQS Precalculation
4586 10:00:44.022664 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4587 10:00:44.029149 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4588 10:00:44.036016 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4589 10:00:44.036097
4590 10:00:44.036160
4591 10:00:44.039325 [Calibration Summary] 1200 Mbps
4592 10:00:44.039405 CH 0, Rank 0
4593 10:00:44.042585 SW Impedance : PASS
4594 10:00:44.045911 DUTY Scan : NO K
4595 10:00:44.045992 ZQ Calibration : PASS
4596 10:00:44.049310 Jitter Meter : NO K
4597 10:00:44.052560 CBT Training : PASS
4598 10:00:44.052641 Write leveling : PASS
4599 10:00:44.055834 RX DQS gating : PASS
4600 10:00:44.055914 RX DQ/DQS(RDDQC) : PASS
4601 10:00:44.059197 TX DQ/DQS : PASS
4602 10:00:44.062458 RX DATLAT : PASS
4603 10:00:44.062539 RX DQ/DQS(Engine): PASS
4604 10:00:44.065614 TX OE : NO K
4605 10:00:44.065695 All Pass.
4606 10:00:44.065758
4607 10:00:44.069037 CH 0, Rank 1
4608 10:00:44.069118 SW Impedance : PASS
4609 10:00:44.072502 DUTY Scan : NO K
4610 10:00:44.075681 ZQ Calibration : PASS
4611 10:00:44.075761 Jitter Meter : NO K
4612 10:00:44.078903 CBT Training : PASS
4613 10:00:44.082171 Write leveling : PASS
4614 10:00:44.082251 RX DQS gating : PASS
4615 10:00:44.085600 RX DQ/DQS(RDDQC) : PASS
4616 10:00:44.088938 TX DQ/DQS : PASS
4617 10:00:44.089019 RX DATLAT : PASS
4618 10:00:44.092429 RX DQ/DQS(Engine): PASS
4619 10:00:44.095524 TX OE : NO K
4620 10:00:44.095604 All Pass.
4621 10:00:44.095667
4622 10:00:44.095725 CH 1, Rank 0
4623 10:00:44.098843 SW Impedance : PASS
4624 10:00:44.102459 DUTY Scan : NO K
4625 10:00:44.102541 ZQ Calibration : PASS
4626 10:00:44.105635 Jitter Meter : NO K
4627 10:00:44.109165 CBT Training : PASS
4628 10:00:44.109245 Write leveling : PASS
4629 10:00:44.112099 RX DQS gating : PASS
4630 10:00:44.112178 RX DQ/DQS(RDDQC) : PASS
4631 10:00:44.115706 TX DQ/DQS : PASS
4632 10:00:44.118933 RX DATLAT : PASS
4633 10:00:44.119013 RX DQ/DQS(Engine): PASS
4634 10:00:44.122140 TX OE : NO K
4635 10:00:44.122221 All Pass.
4636 10:00:44.122283
4637 10:00:44.125494 CH 1, Rank 1
4638 10:00:44.125575 SW Impedance : PASS
4639 10:00:44.128917 DUTY Scan : NO K
4640 10:00:44.132207 ZQ Calibration : PASS
4641 10:00:44.132318 Jitter Meter : NO K
4642 10:00:44.135434 CBT Training : PASS
4643 10:00:44.138643 Write leveling : PASS
4644 10:00:44.138722 RX DQS gating : PASS
4645 10:00:44.142023 RX DQ/DQS(RDDQC) : PASS
4646 10:00:44.145483 TX DQ/DQS : PASS
4647 10:00:44.145565 RX DATLAT : PASS
4648 10:00:44.148720 RX DQ/DQS(Engine): PASS
4649 10:00:44.151896 TX OE : NO K
4650 10:00:44.151978 All Pass.
4651 10:00:44.152040
4652 10:00:44.152099 DramC Write-DBI off
4653 10:00:44.155495 PER_BANK_REFRESH: Hybrid Mode
4654 10:00:44.158426 TX_TRACKING: ON
4655 10:00:44.165409 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4656 10:00:44.168527 [FAST_K] Save calibration result to emmc
4657 10:00:44.175215 dramc_set_vcore_voltage set vcore to 662500
4658 10:00:44.175296 Read voltage for 933, 3
4659 10:00:44.178345 Vio18 = 0
4660 10:00:44.178426 Vcore = 662500
4661 10:00:44.178489 Vdram = 0
4662 10:00:44.181713 Vddq = 0
4663 10:00:44.181793 Vmddr = 0
4664 10:00:44.185222 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4665 10:00:44.191609 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4666 10:00:44.195093 MEM_TYPE=3, freq_sel=17
4667 10:00:44.198330 sv_algorithm_assistance_LP4_1600
4668 10:00:44.201682 ============ PULL DRAM RESETB DOWN ============
4669 10:00:44.204906 ========== PULL DRAM RESETB DOWN end =========
4670 10:00:44.208392 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4671 10:00:44.211665 ===================================
4672 10:00:44.214932 LPDDR4 DRAM CONFIGURATION
4673 10:00:44.218367 ===================================
4674 10:00:44.221892 EX_ROW_EN[0] = 0x0
4675 10:00:44.221973 EX_ROW_EN[1] = 0x0
4676 10:00:44.225015 LP4Y_EN = 0x0
4677 10:00:44.225096 WORK_FSP = 0x0
4678 10:00:44.228458 WL = 0x3
4679 10:00:44.228590 RL = 0x3
4680 10:00:44.231755 BL = 0x2
4681 10:00:44.231836 RPST = 0x0
4682 10:00:44.234723 RD_PRE = 0x0
4683 10:00:44.234804 WR_PRE = 0x1
4684 10:00:44.238216 WR_PST = 0x0
4685 10:00:44.241396 DBI_WR = 0x0
4686 10:00:44.241477 DBI_RD = 0x0
4687 10:00:44.244758 OTF = 0x1
4688 10:00:44.248072 ===================================
4689 10:00:44.251537 ===================================
4690 10:00:44.251618 ANA top config
4691 10:00:44.254847 ===================================
4692 10:00:44.257990 DLL_ASYNC_EN = 0
4693 10:00:44.258071 ALL_SLAVE_EN = 1
4694 10:00:44.261449 NEW_RANK_MODE = 1
4695 10:00:44.264736 DLL_IDLE_MODE = 1
4696 10:00:44.267990 LP45_APHY_COMB_EN = 1
4697 10:00:44.271519 TX_ODT_DIS = 1
4698 10:00:44.271604 NEW_8X_MODE = 1
4699 10:00:44.274497 ===================================
4700 10:00:44.278213 ===================================
4701 10:00:44.281286 data_rate = 1866
4702 10:00:44.284785 CKR = 1
4703 10:00:44.287906 DQ_P2S_RATIO = 8
4704 10:00:44.291333 ===================================
4705 10:00:44.294526 CA_P2S_RATIO = 8
4706 10:00:44.298025 DQ_CA_OPEN = 0
4707 10:00:44.298106 DQ_SEMI_OPEN = 0
4708 10:00:44.301114 CA_SEMI_OPEN = 0
4709 10:00:44.304481 CA_FULL_RATE = 0
4710 10:00:44.307820 DQ_CKDIV4_EN = 1
4711 10:00:44.310959 CA_CKDIV4_EN = 1
4712 10:00:44.314194 CA_PREDIV_EN = 0
4713 10:00:44.314275 PH8_DLY = 0
4714 10:00:44.317508 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4715 10:00:44.320972 DQ_AAMCK_DIV = 4
4716 10:00:44.324189 CA_AAMCK_DIV = 4
4717 10:00:44.327662 CA_ADMCK_DIV = 4
4718 10:00:44.331364 DQ_TRACK_CA_EN = 0
4719 10:00:44.331445 CA_PICK = 933
4720 10:00:44.334407 CA_MCKIO = 933
4721 10:00:44.337521 MCKIO_SEMI = 0
4722 10:00:44.340845 PLL_FREQ = 3732
4723 10:00:44.344227 DQ_UI_PI_RATIO = 32
4724 10:00:44.347905 CA_UI_PI_RATIO = 0
4725 10:00:44.350769 ===================================
4726 10:00:44.354221 ===================================
4727 10:00:44.354302 memory_type:LPDDR4
4728 10:00:44.357432 GP_NUM : 10
4729 10:00:44.360787 SRAM_EN : 1
4730 10:00:44.360868 MD32_EN : 0
4731 10:00:44.364366 ===================================
4732 10:00:44.367521 [ANA_INIT] >>>>>>>>>>>>>>
4733 10:00:44.370693 <<<<<< [CONFIGURE PHASE]: ANA_TX
4734 10:00:44.374142 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4735 10:00:44.377571 ===================================
4736 10:00:44.380757 data_rate = 1866,PCW = 0X8f00
4737 10:00:44.383921 ===================================
4738 10:00:44.387406 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4739 10:00:44.390592 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4740 10:00:44.397344 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4741 10:00:44.400842 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4742 10:00:44.403863 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4743 10:00:44.410699 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4744 10:00:44.410781 [ANA_INIT] flow start
4745 10:00:44.414089 [ANA_INIT] PLL >>>>>>>>
4746 10:00:44.417087 [ANA_INIT] PLL <<<<<<<<
4747 10:00:44.417168 [ANA_INIT] MIDPI >>>>>>>>
4748 10:00:44.420466 [ANA_INIT] MIDPI <<<<<<<<
4749 10:00:44.423693 [ANA_INIT] DLL >>>>>>>>
4750 10:00:44.423774 [ANA_INIT] flow end
4751 10:00:44.427224 ============ LP4 DIFF to SE enter ============
4752 10:00:44.433879 ============ LP4 DIFF to SE exit ============
4753 10:00:44.433960 [ANA_INIT] <<<<<<<<<<<<<
4754 10:00:44.437487 [Flow] Enable top DCM control >>>>>
4755 10:00:44.440857 [Flow] Enable top DCM control <<<<<
4756 10:00:44.443816 Enable DLL master slave shuffle
4757 10:00:44.450387 ==============================================================
4758 10:00:44.450469 Gating Mode config
4759 10:00:44.457067 ==============================================================
4760 10:00:44.460629 Config description:
4761 10:00:44.470377 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4762 10:00:44.476985 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4763 10:00:44.480319 SELPH_MODE 0: By rank 1: By Phase
4764 10:00:44.486976 ==============================================================
4765 10:00:44.490160 GAT_TRACK_EN = 1
4766 10:00:44.493501 RX_GATING_MODE = 2
4767 10:00:44.493582 RX_GATING_TRACK_MODE = 2
4768 10:00:44.496938 SELPH_MODE = 1
4769 10:00:44.500154 PICG_EARLY_EN = 1
4770 10:00:44.503618 VALID_LAT_VALUE = 1
4771 10:00:44.510116 ==============================================================
4772 10:00:44.513505 Enter into Gating configuration >>>>
4773 10:00:44.516688 Exit from Gating configuration <<<<
4774 10:00:44.520266 Enter into DVFS_PRE_config >>>>>
4775 10:00:44.530021 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4776 10:00:44.533343 Exit from DVFS_PRE_config <<<<<
4777 10:00:44.536644 Enter into PICG configuration >>>>
4778 10:00:44.539997 Exit from PICG configuration <<<<
4779 10:00:44.543231 [RX_INPUT] configuration >>>>>
4780 10:00:44.546571 [RX_INPUT] configuration <<<<<
4781 10:00:44.549946 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4782 10:00:44.556809 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4783 10:00:44.563323 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4784 10:00:44.569863 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4785 10:00:44.573402 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4786 10:00:44.579794 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4787 10:00:44.582992 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4788 10:00:44.589651 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4789 10:00:44.592993 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4790 10:00:44.596414 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4791 10:00:44.599587 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4792 10:00:44.606357 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4793 10:00:44.609642 ===================================
4794 10:00:44.609724 LPDDR4 DRAM CONFIGURATION
4795 10:00:44.612925 ===================================
4796 10:00:44.616348 EX_ROW_EN[0] = 0x0
4797 10:00:44.619639 EX_ROW_EN[1] = 0x0
4798 10:00:44.619720 LP4Y_EN = 0x0
4799 10:00:44.622918 WORK_FSP = 0x0
4800 10:00:44.622998 WL = 0x3
4801 10:00:44.626259 RL = 0x3
4802 10:00:44.626339 BL = 0x2
4803 10:00:44.629501 RPST = 0x0
4804 10:00:44.629581 RD_PRE = 0x0
4805 10:00:44.632741 WR_PRE = 0x1
4806 10:00:44.632822 WR_PST = 0x0
4807 10:00:44.636213 DBI_WR = 0x0
4808 10:00:44.636294 DBI_RD = 0x0
4809 10:00:44.639599 OTF = 0x1
4810 10:00:44.642855 ===================================
4811 10:00:44.646110 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4812 10:00:44.649323 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4813 10:00:44.656454 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4814 10:00:44.659423 ===================================
4815 10:00:44.659505 LPDDR4 DRAM CONFIGURATION
4816 10:00:44.662731 ===================================
4817 10:00:44.666119 EX_ROW_EN[0] = 0x10
4818 10:00:44.669345 EX_ROW_EN[1] = 0x0
4819 10:00:44.669426 LP4Y_EN = 0x0
4820 10:00:44.672444 WORK_FSP = 0x0
4821 10:00:44.672548 WL = 0x3
4822 10:00:44.676087 RL = 0x3
4823 10:00:44.676167 BL = 0x2
4824 10:00:44.679211 RPST = 0x0
4825 10:00:44.679292 RD_PRE = 0x0
4826 10:00:44.682651 WR_PRE = 0x1
4827 10:00:44.682732 WR_PST = 0x0
4828 10:00:44.685943 DBI_WR = 0x0
4829 10:00:44.686029 DBI_RD = 0x0
4830 10:00:44.689196 OTF = 0x1
4831 10:00:44.692435 ===================================
4832 10:00:44.699089 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4833 10:00:44.702344 nWR fixed to 30
4834 10:00:44.702430 [ModeRegInit_LP4] CH0 RK0
4835 10:00:44.706003 [ModeRegInit_LP4] CH0 RK1
4836 10:00:44.708994 [ModeRegInit_LP4] CH1 RK0
4837 10:00:44.712328 [ModeRegInit_LP4] CH1 RK1
4838 10:00:44.712410 match AC timing 8
4839 10:00:44.718881 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4840 10:00:44.722449 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4841 10:00:44.725781 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4842 10:00:44.732197 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4843 10:00:44.735724 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4844 10:00:44.735806 ==
4845 10:00:44.738809 Dram Type= 6, Freq= 0, CH_0, rank 0
4846 10:00:44.742317 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4847 10:00:44.742399 ==
4848 10:00:44.748773 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4849 10:00:44.755409 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4850 10:00:44.758796 [CA 0] Center 38 (8~69) winsize 62
4851 10:00:44.761964 [CA 1] Center 38 (8~69) winsize 62
4852 10:00:44.765638 [CA 2] Center 36 (5~67) winsize 63
4853 10:00:44.768551 [CA 3] Center 36 (6~66) winsize 61
4854 10:00:44.772436 [CA 4] Center 34 (4~65) winsize 62
4855 10:00:44.775203 [CA 5] Center 34 (4~64) winsize 61
4856 10:00:44.775284
4857 10:00:44.778737 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4858 10:00:44.778818
4859 10:00:44.782020 [CATrainingPosCal] consider 1 rank data
4860 10:00:44.785224 u2DelayCellTimex100 = 270/100 ps
4861 10:00:44.788568 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4862 10:00:44.791879 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4863 10:00:44.795371 CA2 delay=36 (5~67),Diff = 2 PI (12 cell)
4864 10:00:44.798421 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4865 10:00:44.802059 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4866 10:00:44.805251 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4867 10:00:44.805334
4868 10:00:44.811782 CA PerBit enable=1, Macro0, CA PI delay=34
4869 10:00:44.811865
4870 10:00:44.814988 [CBTSetCACLKResult] CA Dly = 34
4871 10:00:44.815068 CS Dly: 7 (0~38)
4872 10:00:44.815133 ==
4873 10:00:44.818311 Dram Type= 6, Freq= 0, CH_0, rank 1
4874 10:00:44.821657 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4875 10:00:44.821739 ==
4876 10:00:44.828213 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4877 10:00:44.834819 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4878 10:00:44.838264 [CA 0] Center 38 (8~69) winsize 62
4879 10:00:44.841472 [CA 1] Center 38 (7~69) winsize 63
4880 10:00:44.844740 [CA 2] Center 36 (5~67) winsize 63
4881 10:00:44.848060 [CA 3] Center 35 (5~66) winsize 62
4882 10:00:44.851318 [CA 4] Center 34 (4~65) winsize 62
4883 10:00:44.854633 [CA 5] Center 34 (4~65) winsize 62
4884 10:00:44.854714
4885 10:00:44.858115 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4886 10:00:44.858196
4887 10:00:44.861312 [CATrainingPosCal] consider 2 rank data
4888 10:00:44.864904 u2DelayCellTimex100 = 270/100 ps
4889 10:00:44.868208 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4890 10:00:44.871283 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4891 10:00:44.874746 CA2 delay=36 (5~67),Diff = 2 PI (12 cell)
4892 10:00:44.877925 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4893 10:00:44.884724 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4894 10:00:44.888023 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4895 10:00:44.888104
4896 10:00:44.891345 CA PerBit enable=1, Macro0, CA PI delay=34
4897 10:00:44.891426
4898 10:00:44.894763 [CBTSetCACLKResult] CA Dly = 34
4899 10:00:44.894844 CS Dly: 7 (0~38)
4900 10:00:44.894908
4901 10:00:44.898025 ----->DramcWriteLeveling(PI) begin...
4902 10:00:44.898107 ==
4903 10:00:44.901206 Dram Type= 6, Freq= 0, CH_0, rank 0
4904 10:00:44.907807 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4905 10:00:44.907890 ==
4906 10:00:44.911264 Write leveling (Byte 0): 29 => 29
4907 10:00:44.911346 Write leveling (Byte 1): 27 => 27
4908 10:00:44.914563 DramcWriteLeveling(PI) end<-----
4909 10:00:44.914644
4910 10:00:44.914708 ==
4911 10:00:44.917810 Dram Type= 6, Freq= 0, CH_0, rank 0
4912 10:00:44.924468 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4913 10:00:44.924567 ==
4914 10:00:44.927702 [Gating] SW mode calibration
4915 10:00:44.934557 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4916 10:00:44.937805 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4917 10:00:44.944418 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4918 10:00:44.947632 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4919 10:00:44.950940 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4920 10:00:44.957683 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4921 10:00:44.961223 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4922 10:00:44.964639 0 10 20 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 0)
4923 10:00:44.971238 0 10 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4924 10:00:44.974252 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4925 10:00:44.977610 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4926 10:00:44.984142 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4927 10:00:44.987678 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4928 10:00:44.990768 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4929 10:00:44.997686 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4930 10:00:45.000787 0 11 20 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
4931 10:00:45.004117 0 11 24 | B1->B0 | 3737 3d3d | 1 1 | (0 0) (0 0)
4932 10:00:45.010632 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4933 10:00:45.013897 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4934 10:00:45.017208 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4935 10:00:45.024013 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4936 10:00:45.027111 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4937 10:00:45.030550 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4938 10:00:45.033890 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4939 10:00:45.040630 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4940 10:00:45.043755 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4941 10:00:45.047008 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4942 10:00:45.053662 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4943 10:00:45.056939 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4944 10:00:45.060232 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4945 10:00:45.066960 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4946 10:00:45.070291 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4947 10:00:45.073584 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4948 10:00:45.080141 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4949 10:00:45.083580 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4950 10:00:45.086767 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4951 10:00:45.093436 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4952 10:00:45.096698 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4953 10:00:45.100090 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4954 10:00:45.106892 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4955 10:00:45.109957 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4956 10:00:45.113382 Total UI for P1: 0, mck2ui 16
4957 10:00:45.116733 best dqsien dly found for B0: ( 0, 14, 22)
4958 10:00:45.120189 Total UI for P1: 0, mck2ui 16
4959 10:00:45.123207 best dqsien dly found for B1: ( 0, 14, 22)
4960 10:00:45.126588 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
4961 10:00:45.129836 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
4962 10:00:45.129916
4963 10:00:45.133043 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
4964 10:00:45.136478 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
4965 10:00:45.139710 [Gating] SW calibration Done
4966 10:00:45.139790 ==
4967 10:00:45.143393 Dram Type= 6, Freq= 0, CH_0, rank 0
4968 10:00:45.149799 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4969 10:00:45.149880 ==
4970 10:00:45.149943 RX Vref Scan: 0
4971 10:00:45.150002
4972 10:00:45.153045 RX Vref 0 -> 0, step: 1
4973 10:00:45.153124
4974 10:00:45.156454 RX Delay -80 -> 252, step: 8
4975 10:00:45.159534 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
4976 10:00:45.162904 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
4977 10:00:45.166257 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
4978 10:00:45.169557 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
4979 10:00:45.173032 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
4980 10:00:45.179586 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
4981 10:00:45.182917 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
4982 10:00:45.185965 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
4983 10:00:45.189353 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
4984 10:00:45.192899 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
4985 10:00:45.199512 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
4986 10:00:45.202599 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
4987 10:00:45.205911 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
4988 10:00:45.209270 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
4989 10:00:45.212569 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
4990 10:00:45.215823 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
4991 10:00:45.219243 ==
4992 10:00:45.219325 Dram Type= 6, Freq= 0, CH_0, rank 0
4993 10:00:45.226111 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4994 10:00:45.226193 ==
4995 10:00:45.226258 DQS Delay:
4996 10:00:45.229285 DQS0 = 0, DQS1 = 0
4997 10:00:45.229367 DQM Delay:
4998 10:00:45.232439 DQM0 = 97, DQM1 = 86
4999 10:00:45.232577 DQ Delay:
5000 10:00:45.235799 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =95
5001 10:00:45.239068 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5002 10:00:45.242687 DQ8 =75, DQ9 =67, DQ10 =91, DQ11 =79
5003 10:00:45.245576 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5004 10:00:45.245657
5005 10:00:45.245721
5006 10:00:45.245780 ==
5007 10:00:45.249108 Dram Type= 6, Freq= 0, CH_0, rank 0
5008 10:00:45.252532 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5009 10:00:45.252619 ==
5010 10:00:45.252684
5011 10:00:45.252743
5012 10:00:45.255646 TX Vref Scan disable
5013 10:00:45.258806 == TX Byte 0 ==
5014 10:00:45.262228 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5015 10:00:45.265502 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5016 10:00:45.268814 == TX Byte 1 ==
5017 10:00:45.272247 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5018 10:00:45.275806 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5019 10:00:45.275923 ==
5020 10:00:45.279220 Dram Type= 6, Freq= 0, CH_0, rank 0
5021 10:00:45.285502 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5022 10:00:45.285585 ==
5023 10:00:45.285650
5024 10:00:45.285709
5025 10:00:45.285765 TX Vref Scan disable
5026 10:00:45.289350 == TX Byte 0 ==
5027 10:00:45.292807 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5028 10:00:45.299449 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5029 10:00:45.299531 == TX Byte 1 ==
5030 10:00:45.302551 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5031 10:00:45.309268 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5032 10:00:45.309352
5033 10:00:45.309417 [DATLAT]
5034 10:00:45.309476 Freq=933, CH0 RK0
5035 10:00:45.309536
5036 10:00:45.313074 DATLAT Default: 0xd
5037 10:00:45.313156 0, 0xFFFF, sum = 0
5038 10:00:45.316007 1, 0xFFFF, sum = 0
5039 10:00:45.316090 2, 0xFFFF, sum = 0
5040 10:00:45.319349 3, 0xFFFF, sum = 0
5041 10:00:45.319431 4, 0xFFFF, sum = 0
5042 10:00:45.322929 5, 0xFFFF, sum = 0
5043 10:00:45.325959 6, 0xFFFF, sum = 0
5044 10:00:45.326041 7, 0xFFFF, sum = 0
5045 10:00:45.329383 8, 0xFFFF, sum = 0
5046 10:00:45.329465 9, 0xFFFF, sum = 0
5047 10:00:45.332460 10, 0x0, sum = 1
5048 10:00:45.332568 11, 0x0, sum = 2
5049 10:00:45.335747 12, 0x0, sum = 3
5050 10:00:45.335829 13, 0x0, sum = 4
5051 10:00:45.335895 best_step = 11
5052 10:00:45.335955
5053 10:00:45.339039 ==
5054 10:00:45.342213 Dram Type= 6, Freq= 0, CH_0, rank 0
5055 10:00:45.346017 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5056 10:00:45.346099 ==
5057 10:00:45.346164 RX Vref Scan: 1
5058 10:00:45.346223
5059 10:00:45.349182 RX Vref 0 -> 0, step: 1
5060 10:00:45.349262
5061 10:00:45.352539 RX Delay -77 -> 252, step: 4
5062 10:00:45.352620
5063 10:00:45.355745 Set Vref, RX VrefLevel [Byte0]: 49
5064 10:00:45.358912 [Byte1]: 46
5065 10:00:45.358993
5066 10:00:45.362433 Final RX Vref Byte 0 = 49 to rank0
5067 10:00:45.365682 Final RX Vref Byte 1 = 46 to rank0
5068 10:00:45.369025 Final RX Vref Byte 0 = 49 to rank1
5069 10:00:45.372301 Final RX Vref Byte 1 = 46 to rank1==
5070 10:00:45.375547 Dram Type= 6, Freq= 0, CH_0, rank 0
5071 10:00:45.378930 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5072 10:00:45.382213 ==
5073 10:00:45.382295 DQS Delay:
5074 10:00:45.382360 DQS0 = 0, DQS1 = 0
5075 10:00:45.385538 DQM Delay:
5076 10:00:45.385619 DQM0 = 96, DQM1 = 86
5077 10:00:45.389057 DQ Delay:
5078 10:00:45.389138 DQ0 =92, DQ1 =100, DQ2 =94, DQ3 =94
5079 10:00:45.395528 DQ4 =102, DQ5 =86, DQ6 =104, DQ7 =102
5080 10:00:45.398729 DQ8 =78, DQ9 =70, DQ10 =86, DQ11 =78
5081 10:00:45.402027 DQ12 =96, DQ13 =92, DQ14 =98, DQ15 =96
5082 10:00:45.402108
5083 10:00:45.402172
5084 10:00:45.408795 [DQSOSCAuto] RK0, (LSB)MR18= 0x2323, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5085 10:00:45.411849 CH0 RK0: MR19=505, MR18=2323
5086 10:00:45.418514 CH0_RK0: MR19=0x505, MR18=0x2323, DQSOSC=410, MR23=63, INC=64, DEC=42
5087 10:00:45.418597
5088 10:00:45.422033 ----->DramcWriteLeveling(PI) begin...
5089 10:00:45.422116 ==
5090 10:00:45.425209 Dram Type= 6, Freq= 0, CH_0, rank 1
5091 10:00:45.428485 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5092 10:00:45.428606 ==
5093 10:00:45.431789 Write leveling (Byte 0): 30 => 30
5094 10:00:45.435072 Write leveling (Byte 1): 28 => 28
5095 10:00:45.438575 DramcWriteLeveling(PI) end<-----
5096 10:00:45.438656
5097 10:00:45.438721 ==
5098 10:00:45.441888 Dram Type= 6, Freq= 0, CH_0, rank 1
5099 10:00:45.444848 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5100 10:00:45.444929 ==
5101 10:00:45.448293 [Gating] SW mode calibration
5102 10:00:45.455071 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5103 10:00:45.461480 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5104 10:00:45.464924 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 10:00:45.471477 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 10:00:45.474888 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 10:00:45.477983 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 10:00:45.484670 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5109 10:00:45.487899 0 10 20 | B1->B0 | 3333 2f2f | 0 0 | (1 0) (1 0)
5110 10:00:45.491274 0 10 24 | B1->B0 | 2424 2323 | 1 0 | (1 0) (1 0)
5111 10:00:45.498125 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 10:00:45.501049 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 10:00:45.504342 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 10:00:45.510898 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 10:00:45.514333 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 10:00:45.517776 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 10:00:45.524240 0 11 20 | B1->B0 | 3131 3737 | 0 0 | (1 1) (0 0)
5118 10:00:45.527677 0 11 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5119 10:00:45.531043 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 10:00:45.537365 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 10:00:45.540696 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 10:00:45.544017 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 10:00:45.550645 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 10:00:45.554274 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5125 10:00:45.557218 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 10:00:45.563806 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5127 10:00:45.567202 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 10:00:45.570529 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 10:00:45.577570 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 10:00:45.580483 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 10:00:45.583839 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 10:00:45.590321 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 10:00:45.593704 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 10:00:45.596882 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 10:00:45.603665 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 10:00:45.606932 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 10:00:45.610055 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 10:00:45.613471 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 10:00:45.620106 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 10:00:45.623477 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5141 10:00:45.626840 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5142 10:00:45.633433 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 10:00:45.636731 Total UI for P1: 0, mck2ui 16
5144 10:00:45.639961 best dqsien dly found for B0: ( 0, 14, 18)
5145 10:00:45.643212 Total UI for P1: 0, mck2ui 16
5146 10:00:45.646490 best dqsien dly found for B1: ( 0, 14, 20)
5147 10:00:45.650218 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5148 10:00:45.653123 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5149 10:00:45.653205
5150 10:00:45.656442 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5151 10:00:45.659617 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5152 10:00:45.663111 [Gating] SW calibration Done
5153 10:00:45.663192 ==
5154 10:00:45.666419 Dram Type= 6, Freq= 0, CH_0, rank 1
5155 10:00:45.669751 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5156 10:00:45.669834 ==
5157 10:00:45.673183 RX Vref Scan: 0
5158 10:00:45.673263
5159 10:00:45.676080 RX Vref 0 -> 0, step: 1
5160 10:00:45.676160
5161 10:00:45.676224 RX Delay -80 -> 252, step: 8
5162 10:00:45.683008 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5163 10:00:45.686309 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5164 10:00:45.689559 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5165 10:00:45.692972 iDelay=208, Bit 3, Center 91 (0 ~ 183) 184
5166 10:00:45.696186 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5167 10:00:45.699667 iDelay=208, Bit 5, Center 91 (-8 ~ 191) 200
5168 10:00:45.706335 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5169 10:00:45.709271 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5170 10:00:45.712689 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5171 10:00:45.716008 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5172 10:00:45.719070 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5173 10:00:45.725850 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5174 10:00:45.729374 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5175 10:00:45.732210 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5176 10:00:45.735684 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5177 10:00:45.739015 iDelay=208, Bit 15, Center 91 (0 ~ 183) 184
5178 10:00:45.742118 ==
5179 10:00:45.745629 Dram Type= 6, Freq= 0, CH_0, rank 1
5180 10:00:45.748859 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5181 10:00:45.748941 ==
5182 10:00:45.749005 DQS Delay:
5183 10:00:45.752067 DQS0 = 0, DQS1 = 0
5184 10:00:45.752148 DQM Delay:
5185 10:00:45.755366 DQM0 = 97, DQM1 = 83
5186 10:00:45.755446 DQ Delay:
5187 10:00:45.758896 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =91
5188 10:00:45.761984 DQ4 =99, DQ5 =91, DQ6 =103, DQ7 =107
5189 10:00:45.765229 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5190 10:00:45.768671 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5191 10:00:45.768752
5192 10:00:45.768816
5193 10:00:45.768875 ==
5194 10:00:45.771853 Dram Type= 6, Freq= 0, CH_0, rank 1
5195 10:00:45.775219 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5196 10:00:45.775300 ==
5197 10:00:45.775364
5198 10:00:45.775422
5199 10:00:45.778550 TX Vref Scan disable
5200 10:00:45.781837 == TX Byte 0 ==
5201 10:00:45.785181 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5202 10:00:45.788568 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5203 10:00:45.791935 == TX Byte 1 ==
5204 10:00:45.795184 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5205 10:00:45.798561 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5206 10:00:45.798641 ==
5207 10:00:45.801772 Dram Type= 6, Freq= 0, CH_0, rank 1
5208 10:00:45.808206 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5209 10:00:45.808293 ==
5210 10:00:45.808357
5211 10:00:45.808434
5212 10:00:45.808492 TX Vref Scan disable
5213 10:00:45.812621 == TX Byte 0 ==
5214 10:00:45.815683 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5215 10:00:45.822250 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5216 10:00:45.822332 == TX Byte 1 ==
5217 10:00:45.825664 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5218 10:00:45.832329 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5219 10:00:45.832420
5220 10:00:45.832538 [DATLAT]
5221 10:00:45.832616 Freq=933, CH0 RK1
5222 10:00:45.832674
5223 10:00:45.835664 DATLAT Default: 0xb
5224 10:00:45.835745 0, 0xFFFF, sum = 0
5225 10:00:45.838816 1, 0xFFFF, sum = 0
5226 10:00:45.838898 2, 0xFFFF, sum = 0
5227 10:00:45.842199 3, 0xFFFF, sum = 0
5228 10:00:45.845650 4, 0xFFFF, sum = 0
5229 10:00:45.845732 5, 0xFFFF, sum = 0
5230 10:00:45.848711 6, 0xFFFF, sum = 0
5231 10:00:45.848794 7, 0xFFFF, sum = 0
5232 10:00:45.852099 8, 0xFFFF, sum = 0
5233 10:00:45.852181 9, 0xFFFF, sum = 0
5234 10:00:45.855429 10, 0x0, sum = 1
5235 10:00:45.855511 11, 0x0, sum = 2
5236 10:00:45.858944 12, 0x0, sum = 3
5237 10:00:45.859026 13, 0x0, sum = 4
5238 10:00:45.859090 best_step = 11
5239 10:00:45.859149
5240 10:00:45.862131 ==
5241 10:00:45.865346 Dram Type= 6, Freq= 0, CH_0, rank 1
5242 10:00:45.868843 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5243 10:00:45.868924 ==
5244 10:00:45.868988 RX Vref Scan: 0
5245 10:00:45.869048
5246 10:00:45.872021 RX Vref 0 -> 0, step: 1
5247 10:00:45.872102
5248 10:00:45.875207 RX Delay -69 -> 252, step: 4
5249 10:00:45.878603 iDelay=199, Bit 0, Center 94 (3 ~ 186) 184
5250 10:00:45.885118 iDelay=199, Bit 1, Center 98 (3 ~ 194) 192
5251 10:00:45.888690 iDelay=199, Bit 2, Center 94 (3 ~ 186) 184
5252 10:00:45.891690 iDelay=199, Bit 3, Center 92 (3 ~ 182) 180
5253 10:00:45.895082 iDelay=199, Bit 4, Center 102 (11 ~ 194) 184
5254 10:00:45.898782 iDelay=199, Bit 5, Center 88 (-5 ~ 182) 188
5255 10:00:45.902123 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5256 10:00:45.908549 iDelay=199, Bit 7, Center 106 (15 ~ 198) 184
5257 10:00:45.911766 iDelay=199, Bit 8, Center 74 (-13 ~ 162) 176
5258 10:00:45.914988 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5259 10:00:45.918434 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5260 10:00:45.921806 iDelay=199, Bit 11, Center 76 (-9 ~ 162) 172
5261 10:00:45.928394 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5262 10:00:45.931739 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5263 10:00:45.934840 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5264 10:00:45.938191 iDelay=199, Bit 15, Center 92 (3 ~ 182) 180
5265 10:00:45.938271 ==
5266 10:00:45.941348 Dram Type= 6, Freq= 0, CH_0, rank 1
5267 10:00:45.948146 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5268 10:00:45.948226 ==
5269 10:00:45.948290 DQS Delay:
5270 10:00:45.948348 DQS0 = 0, DQS1 = 0
5271 10:00:45.951630 DQM Delay:
5272 10:00:45.951709 DQM0 = 97, DQM1 = 85
5273 10:00:45.954847 DQ Delay:
5274 10:00:45.957984 DQ0 =94, DQ1 =98, DQ2 =94, DQ3 =92
5275 10:00:45.961255 DQ4 =102, DQ5 =88, DQ6 =102, DQ7 =106
5276 10:00:45.964602 DQ8 =74, DQ9 =72, DQ10 =88, DQ11 =76
5277 10:00:45.968170 DQ12 =94, DQ13 =90, DQ14 =96, DQ15 =92
5278 10:00:45.968249
5279 10:00:45.968311
5280 10:00:45.974706 [DQSOSCAuto] RK1, (LSB)MR18= 0x3131, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
5281 10:00:45.977834 CH0 RK1: MR19=505, MR18=3131
5282 10:00:45.984605 CH0_RK1: MR19=0x505, MR18=0x3131, DQSOSC=406, MR23=63, INC=65, DEC=43
5283 10:00:45.988088 [RxdqsGatingPostProcess] freq 933
5284 10:00:45.991440 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5285 10:00:45.994608 Pre-setting of DQS Precalculation
5286 10:00:46.001380 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5287 10:00:46.001460 ==
5288 10:00:46.004354 Dram Type= 6, Freq= 0, CH_1, rank 0
5289 10:00:46.007795 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5290 10:00:46.007876 ==
5291 10:00:46.014381 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5292 10:00:46.021027 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5293 10:00:46.024395 [CA 0] Center 37 (7~68) winsize 62
5294 10:00:46.027593 [CA 1] Center 37 (6~68) winsize 63
5295 10:00:46.030930 [CA 2] Center 34 (4~65) winsize 62
5296 10:00:46.034325 [CA 3] Center 34 (4~65) winsize 62
5297 10:00:46.037625 [CA 4] Center 32 (2~63) winsize 62
5298 10:00:46.037704 [CA 5] Center 32 (2~63) winsize 62
5299 10:00:46.040956
5300 10:00:46.044148 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5301 10:00:46.044227
5302 10:00:46.047538 [CATrainingPosCal] consider 1 rank data
5303 10:00:46.050830 u2DelayCellTimex100 = 270/100 ps
5304 10:00:46.054108 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5305 10:00:46.057468 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5306 10:00:46.060850 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5307 10:00:46.064101 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5308 10:00:46.067278 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5309 10:00:46.070671 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5310 10:00:46.070751
5311 10:00:46.077291 CA PerBit enable=1, Macro0, CA PI delay=32
5312 10:00:46.077372
5313 10:00:46.077435 [CBTSetCACLKResult] CA Dly = 32
5314 10:00:46.080598 CS Dly: 5 (0~36)
5315 10:00:46.080678 ==
5316 10:00:46.083972 Dram Type= 6, Freq= 0, CH_1, rank 1
5317 10:00:46.087430 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5318 10:00:46.087511 ==
5319 10:00:46.094180 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5320 10:00:46.100605 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5321 10:00:46.104032 [CA 0] Center 37 (6~68) winsize 63
5322 10:00:46.107215 [CA 1] Center 37 (6~68) winsize 63
5323 10:00:46.110409 [CA 2] Center 34 (4~65) winsize 62
5324 10:00:46.113767 [CA 3] Center 34 (4~64) winsize 61
5325 10:00:46.117042 [CA 4] Center 33 (2~64) winsize 63
5326 10:00:46.120494 [CA 5] Center 33 (2~64) winsize 63
5327 10:00:46.120612
5328 10:00:46.123844 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5329 10:00:46.123924
5330 10:00:46.126924 [CATrainingPosCal] consider 2 rank data
5331 10:00:46.130259 u2DelayCellTimex100 = 270/100 ps
5332 10:00:46.133592 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5333 10:00:46.136832 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5334 10:00:46.140095 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5335 10:00:46.143695 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5336 10:00:46.147165 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5337 10:00:46.153463 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5338 10:00:46.153542
5339 10:00:46.156915 CA PerBit enable=1, Macro0, CA PI delay=32
5340 10:00:46.156995
5341 10:00:46.160216 [CBTSetCACLKResult] CA Dly = 32
5342 10:00:46.160296 CS Dly: 5 (0~37)
5343 10:00:46.160359
5344 10:00:46.163334 ----->DramcWriteLeveling(PI) begin...
5345 10:00:46.163415 ==
5346 10:00:46.166762 Dram Type= 6, Freq= 0, CH_1, rank 0
5347 10:00:46.170020 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5348 10:00:46.173406 ==
5349 10:00:46.176563 Write leveling (Byte 0): 26 => 26
5350 10:00:46.176644 Write leveling (Byte 1): 27 => 27
5351 10:00:46.180000 DramcWriteLeveling(PI) end<-----
5352 10:00:46.180080
5353 10:00:46.180144 ==
5354 10:00:46.183270 Dram Type= 6, Freq= 0, CH_1, rank 0
5355 10:00:46.189911 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5356 10:00:46.189992 ==
5357 10:00:46.193241 [Gating] SW mode calibration
5358 10:00:46.199839 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5359 10:00:46.203148 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5360 10:00:46.209902 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5361 10:00:46.213090 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5362 10:00:46.216386 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5363 10:00:46.223031 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5364 10:00:46.226301 0 10 16 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (0 1)
5365 10:00:46.229594 0 10 20 | B1->B0 | 3333 2323 | 1 0 | (1 0) (1 0)
5366 10:00:46.236206 0 10 24 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
5367 10:00:46.239440 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5368 10:00:46.242753 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5369 10:00:46.249460 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5370 10:00:46.252748 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5371 10:00:46.256409 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5372 10:00:46.259652 0 11 16 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
5373 10:00:46.266468 0 11 20 | B1->B0 | 2c2c 4545 | 0 0 | (0 0) (0 0)
5374 10:00:46.269402 0 11 24 | B1->B0 | 3e3e 4646 | 1 0 | (1 1) (0 0)
5375 10:00:46.273087 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 10:00:46.279757 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 10:00:46.282610 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 10:00:46.285849 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 10:00:46.292743 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 10:00:46.295935 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5381 10:00:46.299174 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5382 10:00:46.305868 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 10:00:46.309132 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 10:00:46.312436 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 10:00:46.319159 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 10:00:46.322531 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 10:00:46.325718 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 10:00:46.332497 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 10:00:46.335811 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 10:00:46.339092 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 10:00:46.345934 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 10:00:46.348959 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 10:00:46.352228 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 10:00:46.358824 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 10:00:46.362509 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 10:00:46.365466 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5397 10:00:46.372291 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5398 10:00:46.372374 Total UI for P1: 0, mck2ui 16
5399 10:00:46.378811 best dqsien dly found for B0: ( 0, 14, 16)
5400 10:00:46.382345 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5401 10:00:46.385412 Total UI for P1: 0, mck2ui 16
5402 10:00:46.388683 best dqsien dly found for B1: ( 0, 14, 18)
5403 10:00:46.392093 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5404 10:00:46.395449 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5405 10:00:46.395530
5406 10:00:46.398847 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5407 10:00:46.402212 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5408 10:00:46.405336 [Gating] SW calibration Done
5409 10:00:46.405418 ==
5410 10:00:46.408720 Dram Type= 6, Freq= 0, CH_1, rank 0
5411 10:00:46.411993 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5412 10:00:46.415635 ==
5413 10:00:46.415717 RX Vref Scan: 0
5414 10:00:46.415782
5415 10:00:46.418522 RX Vref 0 -> 0, step: 1
5416 10:00:46.418604
5417 10:00:46.422166 RX Delay -80 -> 252, step: 8
5418 10:00:46.425294 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5419 10:00:46.428650 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5420 10:00:46.431991 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5421 10:00:46.435295 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5422 10:00:46.438402 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5423 10:00:46.445114 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5424 10:00:46.448431 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5425 10:00:46.451756 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5426 10:00:46.455211 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5427 10:00:46.458593 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5428 10:00:46.465140 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5429 10:00:46.468265 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5430 10:00:46.471908 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5431 10:00:46.474828 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5432 10:00:46.478065 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5433 10:00:46.481345 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5434 10:00:46.484758 ==
5435 10:00:46.488230 Dram Type= 6, Freq= 0, CH_1, rank 0
5436 10:00:46.491339 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5437 10:00:46.491452 ==
5438 10:00:46.491520 DQS Delay:
5439 10:00:46.494729 DQS0 = 0, DQS1 = 0
5440 10:00:46.494810 DQM Delay:
5441 10:00:46.498087 DQM0 = 95, DQM1 = 88
5442 10:00:46.498168 DQ Delay:
5443 10:00:46.501449 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5444 10:00:46.504545 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91
5445 10:00:46.507798 DQ8 =71, DQ9 =75, DQ10 =91, DQ11 =79
5446 10:00:46.511367 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =99
5447 10:00:46.511449
5448 10:00:46.511513
5449 10:00:46.511572 ==
5450 10:00:46.514470 Dram Type= 6, Freq= 0, CH_1, rank 0
5451 10:00:46.517676 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5452 10:00:46.517761 ==
5453 10:00:46.517825
5454 10:00:46.517883
5455 10:00:46.521156 TX Vref Scan disable
5456 10:00:46.524783 == TX Byte 0 ==
5457 10:00:46.527609 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5458 10:00:46.530962 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5459 10:00:46.534582 == TX Byte 1 ==
5460 10:00:46.537747 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5461 10:00:46.541238 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5462 10:00:46.541319 ==
5463 10:00:46.544647 Dram Type= 6, Freq= 0, CH_1, rank 0
5464 10:00:46.550956 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5465 10:00:46.551038 ==
5466 10:00:46.551102
5467 10:00:46.551161
5468 10:00:46.551217 TX Vref Scan disable
5469 10:00:46.554957 == TX Byte 0 ==
5470 10:00:46.558313 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5471 10:00:46.564815 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5472 10:00:46.564898 == TX Byte 1 ==
5473 10:00:46.568134 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5474 10:00:46.574732 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5475 10:00:46.574814
5476 10:00:46.574879 [DATLAT]
5477 10:00:46.574938 Freq=933, CH1 RK0
5478 10:00:46.574998
5479 10:00:46.578145 DATLAT Default: 0xd
5480 10:00:46.578226 0, 0xFFFF, sum = 0
5481 10:00:46.581314 1, 0xFFFF, sum = 0
5482 10:00:46.581395 2, 0xFFFF, sum = 0
5483 10:00:46.584758 3, 0xFFFF, sum = 0
5484 10:00:46.588252 4, 0xFFFF, sum = 0
5485 10:00:46.588360 5, 0xFFFF, sum = 0
5486 10:00:46.591344 6, 0xFFFF, sum = 0
5487 10:00:46.591452 7, 0xFFFF, sum = 0
5488 10:00:46.594764 8, 0xFFFF, sum = 0
5489 10:00:46.594846 9, 0xFFFF, sum = 0
5490 10:00:46.598072 10, 0x0, sum = 1
5491 10:00:46.598154 11, 0x0, sum = 2
5492 10:00:46.601657 12, 0x0, sum = 3
5493 10:00:46.601739 13, 0x0, sum = 4
5494 10:00:46.601803 best_step = 11
5495 10:00:46.601862
5496 10:00:46.604725 ==
5497 10:00:46.607953 Dram Type= 6, Freq= 0, CH_1, rank 0
5498 10:00:46.611418 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5499 10:00:46.611500 ==
5500 10:00:46.611564 RX Vref Scan: 1
5501 10:00:46.611623
5502 10:00:46.614638 RX Vref 0 -> 0, step: 1
5503 10:00:46.614719
5504 10:00:46.617977 RX Delay -69 -> 252, step: 4
5505 10:00:46.618058
5506 10:00:46.621422 Set Vref, RX VrefLevel [Byte0]: 58
5507 10:00:46.624824 [Byte1]: 48
5508 10:00:46.624904
5509 10:00:46.628009 Final RX Vref Byte 0 = 58 to rank0
5510 10:00:46.631262 Final RX Vref Byte 1 = 48 to rank0
5511 10:00:46.634735 Final RX Vref Byte 0 = 58 to rank1
5512 10:00:46.638008 Final RX Vref Byte 1 = 48 to rank1==
5513 10:00:46.641042 Dram Type= 6, Freq= 0, CH_1, rank 0
5514 10:00:46.644457 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5515 10:00:46.647970 ==
5516 10:00:46.648051 DQS Delay:
5517 10:00:46.648115 DQS0 = 0, DQS1 = 0
5518 10:00:46.651174 DQM Delay:
5519 10:00:46.651255 DQM0 = 94, DQM1 = 88
5520 10:00:46.654448 DQ Delay:
5521 10:00:46.654529 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =92
5522 10:00:46.657666 DQ4 =94, DQ5 =104, DQ6 =100, DQ7 =94
5523 10:00:46.661255 DQ8 =72, DQ9 =78, DQ10 =90, DQ11 =80
5524 10:00:46.664348 DQ12 =96, DQ13 =98, DQ14 =98, DQ15 =98
5525 10:00:46.667579
5526 10:00:46.667659
5527 10:00:46.674342 [DQSOSCAuto] RK0, (LSB)MR18= 0x3030, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
5528 10:00:46.677548 CH1 RK0: MR19=505, MR18=3030
5529 10:00:46.684237 CH1_RK0: MR19=0x505, MR18=0x3030, DQSOSC=406, MR23=63, INC=65, DEC=43
5530 10:00:46.684318
5531 10:00:46.687681 ----->DramcWriteLeveling(PI) begin...
5532 10:00:46.687763 ==
5533 10:00:46.690850 Dram Type= 6, Freq= 0, CH_1, rank 1
5534 10:00:46.694632 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5535 10:00:46.694714 ==
5536 10:00:46.697499 Write leveling (Byte 0): 22 => 22
5537 10:00:46.700658 Write leveling (Byte 1): 22 => 22
5538 10:00:46.703983 DramcWriteLeveling(PI) end<-----
5539 10:00:46.704063
5540 10:00:46.704126 ==
5541 10:00:46.707317 Dram Type= 6, Freq= 0, CH_1, rank 1
5542 10:00:46.710536 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5543 10:00:46.710618 ==
5544 10:00:46.714207 [Gating] SW mode calibration
5545 10:00:46.720720 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5546 10:00:46.727363 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5547 10:00:46.730627 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5548 10:00:46.733845 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5549 10:00:46.740462 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5550 10:00:46.743769 0 10 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (1 0)
5551 10:00:46.747234 0 10 16 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
5552 10:00:46.753838 0 10 20 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
5553 10:00:46.757315 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5554 10:00:46.760431 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5555 10:00:46.767049 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5556 10:00:46.770556 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5557 10:00:46.773729 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5558 10:00:46.780430 0 11 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5559 10:00:46.783557 0 11 16 | B1->B0 | 2525 3e3e | 0 0 | (0 0) (0 0)
5560 10:00:46.786869 0 11 20 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
5561 10:00:46.793605 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5562 10:00:46.796850 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5563 10:00:46.800210 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5564 10:00:46.807050 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5565 10:00:46.810125 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5566 10:00:46.813398 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5567 10:00:46.820161 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5568 10:00:46.823486 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5569 10:00:46.826542 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 10:00:46.833378 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 10:00:46.836466 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 10:00:46.839816 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 10:00:46.846586 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 10:00:46.849816 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 10:00:46.853093 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 10:00:46.859804 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 10:00:46.863080 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 10:00:46.866657 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 10:00:46.873073 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 10:00:46.876458 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 10:00:46.879554 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 10:00:46.886471 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 10:00:46.889824 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5584 10:00:46.893093 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5585 10:00:46.896184 Total UI for P1: 0, mck2ui 16
5586 10:00:46.899668 best dqsien dly found for B0: ( 0, 14, 16)
5587 10:00:46.906151 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 10:00:46.906237 Total UI for P1: 0, mck2ui 16
5589 10:00:46.909612 best dqsien dly found for B1: ( 0, 14, 18)
5590 10:00:46.916113 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5591 10:00:46.919320 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5592 10:00:46.919401
5593 10:00:46.922647 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5594 10:00:46.926013 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5595 10:00:46.929475 [Gating] SW calibration Done
5596 10:00:46.929556 ==
5597 10:00:46.932447 Dram Type= 6, Freq= 0, CH_1, rank 1
5598 10:00:46.935794 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5599 10:00:46.935893 ==
5600 10:00:46.939333 RX Vref Scan: 0
5601 10:00:46.939414
5602 10:00:46.939478 RX Vref 0 -> 0, step: 1
5603 10:00:46.939538
5604 10:00:46.942603 RX Delay -80 -> 252, step: 8
5605 10:00:46.945726 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5606 10:00:46.952393 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5607 10:00:46.955755 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5608 10:00:46.959007 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5609 10:00:46.962507 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5610 10:00:46.965941 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5611 10:00:46.969072 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5612 10:00:46.975609 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5613 10:00:46.978981 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5614 10:00:46.982217 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5615 10:00:46.985602 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5616 10:00:46.988920 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5617 10:00:46.995580 iDelay=208, Bit 12, Center 95 (-8 ~ 199) 208
5618 10:00:46.998936 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5619 10:00:47.002194 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5620 10:00:47.005532 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5621 10:00:47.005613 ==
5622 10:00:47.008911 Dram Type= 6, Freq= 0, CH_1, rank 1
5623 10:00:47.011983 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5624 10:00:47.015411 ==
5625 10:00:47.015496 DQS Delay:
5626 10:00:47.015581 DQS0 = 0, DQS1 = 0
5627 10:00:47.018614 DQM Delay:
5628 10:00:47.018698 DQM0 = 94, DQM1 = 87
5629 10:00:47.021869 DQ Delay:
5630 10:00:47.025170 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5631 10:00:47.028761 DQ4 =91, DQ5 =107, DQ6 =99, DQ7 =91
5632 10:00:47.028845 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =83
5633 10:00:47.035165 DQ12 =95, DQ13 =95, DQ14 =91, DQ15 =95
5634 10:00:47.035249
5635 10:00:47.035333
5636 10:00:47.035413 ==
5637 10:00:47.038398 Dram Type= 6, Freq= 0, CH_1, rank 1
5638 10:00:47.041602 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5639 10:00:47.041687 ==
5640 10:00:47.041771
5641 10:00:47.041868
5642 10:00:47.044954 TX Vref Scan disable
5643 10:00:47.045038 == TX Byte 0 ==
5644 10:00:47.051595 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5645 10:00:47.054850 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5646 10:00:47.054934 == TX Byte 1 ==
5647 10:00:47.061670 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5648 10:00:47.064815 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5649 10:00:47.064899 ==
5650 10:00:47.068382 Dram Type= 6, Freq= 0, CH_1, rank 1
5651 10:00:47.071517 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5652 10:00:47.071601 ==
5653 10:00:47.071686
5654 10:00:47.071767
5655 10:00:47.074876 TX Vref Scan disable
5656 10:00:47.078280 == TX Byte 0 ==
5657 10:00:47.081323 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5658 10:00:47.084749 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5659 10:00:47.088016 == TX Byte 1 ==
5660 10:00:47.091389 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5661 10:00:47.094647 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5662 10:00:47.094731
5663 10:00:47.097906 [DATLAT]
5664 10:00:47.097989 Freq=933, CH1 RK1
5665 10:00:47.098074
5666 10:00:47.101182 DATLAT Default: 0xb
5667 10:00:47.101266 0, 0xFFFF, sum = 0
5668 10:00:47.104679 1, 0xFFFF, sum = 0
5669 10:00:47.104765 2, 0xFFFF, sum = 0
5670 10:00:47.107947 3, 0xFFFF, sum = 0
5671 10:00:47.108032 4, 0xFFFF, sum = 0
5672 10:00:47.111151 5, 0xFFFF, sum = 0
5673 10:00:47.111236 6, 0xFFFF, sum = 0
5674 10:00:47.114590 7, 0xFFFF, sum = 0
5675 10:00:47.117955 8, 0xFFFF, sum = 0
5676 10:00:47.118040 9, 0xFFFF, sum = 0
5677 10:00:47.118127 10, 0x0, sum = 1
5678 10:00:47.121003 11, 0x0, sum = 2
5679 10:00:47.121087 12, 0x0, sum = 3
5680 10:00:47.124652 13, 0x0, sum = 4
5681 10:00:47.124736 best_step = 11
5682 10:00:47.124822
5683 10:00:47.124902 ==
5684 10:00:47.127880 Dram Type= 6, Freq= 0, CH_1, rank 1
5685 10:00:47.134309 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5686 10:00:47.134418 ==
5687 10:00:47.134504 RX Vref Scan: 0
5688 10:00:47.134585
5689 10:00:47.137644 RX Vref 0 -> 0, step: 1
5690 10:00:47.137751
5691 10:00:47.140980 RX Delay -69 -> 252, step: 4
5692 10:00:47.144281 iDelay=203, Bit 0, Center 98 (7 ~ 190) 184
5693 10:00:47.151060 iDelay=203, Bit 1, Center 92 (-1 ~ 186) 188
5694 10:00:47.154230 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5695 10:00:47.157496 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5696 10:00:47.160865 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5697 10:00:47.164084 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5698 10:00:47.167562 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5699 10:00:47.174105 iDelay=203, Bit 7, Center 94 (-1 ~ 190) 192
5700 10:00:47.177519 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5701 10:00:47.180785 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5702 10:00:47.184326 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5703 10:00:47.187506 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5704 10:00:47.194138 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5705 10:00:47.197339 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5706 10:00:47.200567 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5707 10:00:47.203960 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5708 10:00:47.204044 ==
5709 10:00:47.207223 Dram Type= 6, Freq= 0, CH_1, rank 1
5710 10:00:47.210626 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5711 10:00:47.213887 ==
5712 10:00:47.213971 DQS Delay:
5713 10:00:47.214056 DQS0 = 0, DQS1 = 0
5714 10:00:47.217226 DQM Delay:
5715 10:00:47.217309 DQM0 = 96, DQM1 = 87
5716 10:00:47.220463 DQ Delay:
5717 10:00:47.220593 DQ0 =98, DQ1 =92, DQ2 =88, DQ3 =92
5718 10:00:47.223753 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5719 10:00:47.226997 DQ8 =74, DQ9 =74, DQ10 =88, DQ11 =80
5720 10:00:47.230437 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
5721 10:00:47.233633
5722 10:00:47.233716
5723 10:00:47.240251 [DQSOSCAuto] RK1, (LSB)MR18= 0x2222, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5724 10:00:47.243573 CH1 RK1: MR19=505, MR18=2222
5725 10:00:47.250280 CH1_RK1: MR19=0x505, MR18=0x2222, DQSOSC=411, MR23=63, INC=64, DEC=42
5726 10:00:47.253640 [RxdqsGatingPostProcess] freq 933
5727 10:00:47.256952 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5728 10:00:47.260111 Pre-setting of DQS Precalculation
5729 10:00:47.266670 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5730 10:00:47.273599 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5731 10:00:47.279832 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5732 10:00:47.279917
5733 10:00:47.280001
5734 10:00:47.283339 [Calibration Summary] 1866 Mbps
5735 10:00:47.283424 CH 0, Rank 0
5736 10:00:47.286521 SW Impedance : PASS
5737 10:00:47.289876 DUTY Scan : NO K
5738 10:00:47.289960 ZQ Calibration : PASS
5739 10:00:47.293298 Jitter Meter : NO K
5740 10:00:47.296422 CBT Training : PASS
5741 10:00:47.296568 Write leveling : PASS
5742 10:00:47.299702 RX DQS gating : PASS
5743 10:00:47.303274 RX DQ/DQS(RDDQC) : PASS
5744 10:00:47.303357 TX DQ/DQS : PASS
5745 10:00:47.306486 RX DATLAT : PASS
5746 10:00:47.309674 RX DQ/DQS(Engine): PASS
5747 10:00:47.309755 TX OE : NO K
5748 10:00:47.309820 All Pass.
5749 10:00:47.312977
5750 10:00:47.313057 CH 0, Rank 1
5751 10:00:47.316217 SW Impedance : PASS
5752 10:00:47.316302 DUTY Scan : NO K
5753 10:00:47.319503 ZQ Calibration : PASS
5754 10:00:47.322792 Jitter Meter : NO K
5755 10:00:47.322872 CBT Training : PASS
5756 10:00:47.326089 Write leveling : PASS
5757 10:00:47.326170 RX DQS gating : PASS
5758 10:00:47.329514 RX DQ/DQS(RDDQC) : PASS
5759 10:00:47.332817 TX DQ/DQS : PASS
5760 10:00:47.332898 RX DATLAT : PASS
5761 10:00:47.336056 RX DQ/DQS(Engine): PASS
5762 10:00:47.339805 TX OE : NO K
5763 10:00:47.339886 All Pass.
5764 10:00:47.339950
5765 10:00:47.340009 CH 1, Rank 0
5766 10:00:47.342619 SW Impedance : PASS
5767 10:00:47.345971 DUTY Scan : NO K
5768 10:00:47.346052 ZQ Calibration : PASS
5769 10:00:47.349303 Jitter Meter : NO K
5770 10:00:47.352726 CBT Training : PASS
5771 10:00:47.352806 Write leveling : PASS
5772 10:00:47.355876 RX DQS gating : PASS
5773 10:00:47.359292 RX DQ/DQS(RDDQC) : PASS
5774 10:00:47.359399 TX DQ/DQS : PASS
5775 10:00:47.362924 RX DATLAT : PASS
5776 10:00:47.366088 RX DQ/DQS(Engine): PASS
5777 10:00:47.366167 TX OE : NO K
5778 10:00:47.369236 All Pass.
5779 10:00:47.369316
5780 10:00:47.369379 CH 1, Rank 1
5781 10:00:47.372544 SW Impedance : PASS
5782 10:00:47.372623 DUTY Scan : NO K
5783 10:00:47.375812 ZQ Calibration : PASS
5784 10:00:47.379335 Jitter Meter : NO K
5785 10:00:47.379410 CBT Training : PASS
5786 10:00:47.382600 Write leveling : PASS
5787 10:00:47.382697 RX DQS gating : PASS
5788 10:00:47.385800 RX DQ/DQS(RDDQC) : PASS
5789 10:00:47.389277 TX DQ/DQS : PASS
5790 10:00:47.389375 RX DATLAT : PASS
5791 10:00:47.392348 RX DQ/DQS(Engine): PASS
5792 10:00:47.395711 TX OE : NO K
5793 10:00:47.395784 All Pass.
5794 10:00:47.395847
5795 10:00:47.399019 DramC Write-DBI off
5796 10:00:47.399090 PER_BANK_REFRESH: Hybrid Mode
5797 10:00:47.402471 TX_TRACKING: ON
5798 10:00:47.412212 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5799 10:00:47.415630 [FAST_K] Save calibration result to emmc
5800 10:00:47.418950 dramc_set_vcore_voltage set vcore to 650000
5801 10:00:47.419031 Read voltage for 400, 6
5802 10:00:47.422333 Vio18 = 0
5803 10:00:47.422413 Vcore = 650000
5804 10:00:47.422481 Vdram = 0
5805 10:00:47.425498 Vddq = 0
5806 10:00:47.425604 Vmddr = 0
5807 10:00:47.429184 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5808 10:00:47.435532 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5809 10:00:47.438723 MEM_TYPE=3, freq_sel=20
5810 10:00:47.442192 sv_algorithm_assistance_LP4_800
5811 10:00:47.445549 ============ PULL DRAM RESETB DOWN ============
5812 10:00:47.448896 ========== PULL DRAM RESETB DOWN end =========
5813 10:00:47.455668 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5814 10:00:47.458889 ===================================
5815 10:00:47.458970 LPDDR4 DRAM CONFIGURATION
5816 10:00:47.462195 ===================================
5817 10:00:47.465312 EX_ROW_EN[0] = 0x0
5818 10:00:47.465392 EX_ROW_EN[1] = 0x0
5819 10:00:47.468761 LP4Y_EN = 0x0
5820 10:00:47.468854 WORK_FSP = 0x0
5821 10:00:47.471982 WL = 0x2
5822 10:00:47.475303 RL = 0x2
5823 10:00:47.475404 BL = 0x2
5824 10:00:47.478925 RPST = 0x0
5825 10:00:47.479005 RD_PRE = 0x0
5826 10:00:47.482170 WR_PRE = 0x1
5827 10:00:47.482250 WR_PST = 0x0
5828 10:00:47.485644 DBI_WR = 0x0
5829 10:00:47.485724 DBI_RD = 0x0
5830 10:00:47.488665 OTF = 0x1
5831 10:00:47.491937 ===================================
5832 10:00:47.495441 ===================================
5833 10:00:47.495556 ANA top config
5834 10:00:47.498535 ===================================
5835 10:00:47.502004 DLL_ASYNC_EN = 0
5836 10:00:47.505334 ALL_SLAVE_EN = 1
5837 10:00:47.505418 NEW_RANK_MODE = 1
5838 10:00:47.508848 DLL_IDLE_MODE = 1
5839 10:00:47.511750 LP45_APHY_COMB_EN = 1
5840 10:00:47.515352 TX_ODT_DIS = 1
5841 10:00:47.518377 NEW_8X_MODE = 1
5842 10:00:47.518482 ===================================
5843 10:00:47.521820 ===================================
5844 10:00:47.525093 data_rate = 800
5845 10:00:47.528496 CKR = 1
5846 10:00:47.531623 DQ_P2S_RATIO = 4
5847 10:00:47.535153 ===================================
5848 10:00:47.538368 CA_P2S_RATIO = 4
5849 10:00:47.541690 DQ_CA_OPEN = 0
5850 10:00:47.545174 DQ_SEMI_OPEN = 1
5851 10:00:47.545258 CA_SEMI_OPEN = 1
5852 10:00:47.548211 CA_FULL_RATE = 0
5853 10:00:47.551700 DQ_CKDIV4_EN = 0
5854 10:00:47.554867 CA_CKDIV4_EN = 1
5855 10:00:47.558293 CA_PREDIV_EN = 0
5856 10:00:47.561764 PH8_DLY = 0
5857 10:00:47.561844 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5858 10:00:47.564863 DQ_AAMCK_DIV = 0
5859 10:00:47.568132 CA_AAMCK_DIV = 0
5860 10:00:47.571671 CA_ADMCK_DIV = 4
5861 10:00:47.574830 DQ_TRACK_CA_EN = 0
5862 10:00:47.578302 CA_PICK = 800
5863 10:00:47.578382 CA_MCKIO = 400
5864 10:00:47.581634 MCKIO_SEMI = 400
5865 10:00:47.584872 PLL_FREQ = 3016
5866 10:00:47.588075 DQ_UI_PI_RATIO = 32
5867 10:00:47.591343 CA_UI_PI_RATIO = 32
5868 10:00:47.594769 ===================================
5869 10:00:47.597952 ===================================
5870 10:00:47.601266 memory_type:LPDDR4
5871 10:00:47.601346 GP_NUM : 10
5872 10:00:47.604701 SRAM_EN : 1
5873 10:00:47.608086 MD32_EN : 0
5874 10:00:47.611263 ===================================
5875 10:00:47.611343 [ANA_INIT] >>>>>>>>>>>>>>
5876 10:00:47.614555 <<<<<< [CONFIGURE PHASE]: ANA_TX
5877 10:00:47.617752 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5878 10:00:47.621137 ===================================
5879 10:00:47.624441 data_rate = 800,PCW = 0X7400
5880 10:00:47.627825 ===================================
5881 10:00:47.631055 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5882 10:00:47.637875 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5883 10:00:47.647588 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5884 10:00:47.651171 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5885 10:00:47.657714 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5886 10:00:47.660908 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5887 10:00:47.660989 [ANA_INIT] flow start
5888 10:00:47.664331 [ANA_INIT] PLL >>>>>>>>
5889 10:00:47.667488 [ANA_INIT] PLL <<<<<<<<
5890 10:00:47.667569 [ANA_INIT] MIDPI >>>>>>>>
5891 10:00:47.670767 [ANA_INIT] MIDPI <<<<<<<<
5892 10:00:47.674093 [ANA_INIT] DLL >>>>>>>>
5893 10:00:47.674173 [ANA_INIT] flow end
5894 10:00:47.677433 ============ LP4 DIFF to SE enter ============
5895 10:00:47.684126 ============ LP4 DIFF to SE exit ============
5896 10:00:47.684207 [ANA_INIT] <<<<<<<<<<<<<
5897 10:00:47.687283 [Flow] Enable top DCM control >>>>>
5898 10:00:47.690841 [Flow] Enable top DCM control <<<<<
5899 10:00:47.694134 Enable DLL master slave shuffle
5900 10:00:47.700827 ==============================================================
5901 10:00:47.700909 Gating Mode config
5902 10:00:47.707571 ==============================================================
5903 10:00:47.710683 Config description:
5904 10:00:47.720834 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5905 10:00:47.727198 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5906 10:00:47.730633 SELPH_MODE 0: By rank 1: By Phase
5907 10:00:47.737207 ==============================================================
5908 10:00:47.740648 GAT_TRACK_EN = 0
5909 10:00:47.743750 RX_GATING_MODE = 2
5910 10:00:47.743830 RX_GATING_TRACK_MODE = 2
5911 10:00:47.747078 SELPH_MODE = 1
5912 10:00:47.750635 PICG_EARLY_EN = 1
5913 10:00:47.753959 VALID_LAT_VALUE = 1
5914 10:00:47.760294 ==============================================================
5915 10:00:47.763798 Enter into Gating configuration >>>>
5916 10:00:47.766866 Exit from Gating configuration <<<<
5917 10:00:47.770334 Enter into DVFS_PRE_config >>>>>
5918 10:00:47.780257 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5919 10:00:47.783638 Exit from DVFS_PRE_config <<<<<
5920 10:00:47.786832 Enter into PICG configuration >>>>
5921 10:00:47.790202 Exit from PICG configuration <<<<
5922 10:00:47.793568 [RX_INPUT] configuration >>>>>
5923 10:00:47.796779 [RX_INPUT] configuration <<<<<
5924 10:00:47.800290 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5925 10:00:47.807085 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5926 10:00:47.813572 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5927 10:00:47.820176 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5928 10:00:47.826666 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5929 10:00:47.829754 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5930 10:00:47.836424 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5931 10:00:47.839867 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5932 10:00:47.843086 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5933 10:00:47.846304 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5934 10:00:47.850230 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5935 10:00:47.856651 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5936 10:00:47.859702 ===================================
5937 10:00:47.863181 LPDDR4 DRAM CONFIGURATION
5938 10:00:47.866310 ===================================
5939 10:00:47.866391 EX_ROW_EN[0] = 0x0
5940 10:00:47.869595 EX_ROW_EN[1] = 0x0
5941 10:00:47.869679 LP4Y_EN = 0x0
5942 10:00:47.873013 WORK_FSP = 0x0
5943 10:00:47.873093 WL = 0x2
5944 10:00:47.876229 RL = 0x2
5945 10:00:47.876309 BL = 0x2
5946 10:00:47.879663 RPST = 0x0
5947 10:00:47.879743 RD_PRE = 0x0
5948 10:00:47.882987 WR_PRE = 0x1
5949 10:00:47.883067 WR_PST = 0x0
5950 10:00:47.886270 DBI_WR = 0x0
5951 10:00:47.886349 DBI_RD = 0x0
5952 10:00:47.889689 OTF = 0x1
5953 10:00:47.892948 ===================================
5954 10:00:47.896335 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5955 10:00:47.899541 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5956 10:00:47.906172 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5957 10:00:47.909488 ===================================
5958 10:00:47.909570 LPDDR4 DRAM CONFIGURATION
5959 10:00:47.912856 ===================================
5960 10:00:47.916142 EX_ROW_EN[0] = 0x10
5961 10:00:47.919602 EX_ROW_EN[1] = 0x0
5962 10:00:47.919682 LP4Y_EN = 0x0
5963 10:00:47.922634 WORK_FSP = 0x0
5964 10:00:47.922714 WL = 0x2
5965 10:00:47.925989 RL = 0x2
5966 10:00:47.926068 BL = 0x2
5967 10:00:47.929332 RPST = 0x0
5968 10:00:47.929439 RD_PRE = 0x0
5969 10:00:47.932556 WR_PRE = 0x1
5970 10:00:47.932642 WR_PST = 0x0
5971 10:00:47.936234 DBI_WR = 0x0
5972 10:00:47.936338 DBI_RD = 0x0
5973 10:00:47.939367 OTF = 0x1
5974 10:00:47.942635 ===================================
5975 10:00:47.949209 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5976 10:00:47.952643 nWR fixed to 30
5977 10:00:47.955958 [ModeRegInit_LP4] CH0 RK0
5978 10:00:47.956041 [ModeRegInit_LP4] CH0 RK1
5979 10:00:47.959154 [ModeRegInit_LP4] CH1 RK0
5980 10:00:47.962547 [ModeRegInit_LP4] CH1 RK1
5981 10:00:47.962658 match AC timing 18
5982 10:00:47.969260 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5983 10:00:47.972465 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5984 10:00:47.975977 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5985 10:00:47.982613 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5986 10:00:47.985819 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5987 10:00:47.985900 ==
5988 10:00:47.989026 Dram Type= 6, Freq= 0, CH_0, rank 0
5989 10:00:47.992216 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5990 10:00:47.992296 ==
5991 10:00:47.998933 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5992 10:00:48.005578 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5993 10:00:48.008970 [CA 0] Center 36 (8~64) winsize 57
5994 10:00:48.012163 [CA 1] Center 36 (8~64) winsize 57
5995 10:00:48.015570 [CA 2] Center 36 (8~64) winsize 57
5996 10:00:48.015651 [CA 3] Center 36 (8~64) winsize 57
5997 10:00:48.018881 [CA 4] Center 36 (8~64) winsize 57
5998 10:00:48.022369 [CA 5] Center 36 (8~64) winsize 57
5999 10:00:48.022450
6000 10:00:48.025584 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6001 10:00:48.029248
6002 10:00:48.032235 [CATrainingPosCal] consider 1 rank data
6003 10:00:48.032315 u2DelayCellTimex100 = 270/100 ps
6004 10:00:48.039014 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6005 10:00:48.042394 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6006 10:00:48.045589 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6007 10:00:48.048673 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6008 10:00:48.052155 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6009 10:00:48.055454 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6010 10:00:48.055539
6011 10:00:48.058707 CA PerBit enable=1, Macro0, CA PI delay=36
6012 10:00:48.058793
6013 10:00:48.062276 [CBTSetCACLKResult] CA Dly = 36
6014 10:00:48.065373 CS Dly: 1 (0~32)
6015 10:00:48.065453 ==
6016 10:00:48.068674 Dram Type= 6, Freq= 0, CH_0, rank 1
6017 10:00:48.072154 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6018 10:00:48.072236 ==
6019 10:00:48.078567 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6020 10:00:48.081900 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6021 10:00:48.085327 [CA 0] Center 36 (8~64) winsize 57
6022 10:00:48.088706 [CA 1] Center 36 (8~64) winsize 57
6023 10:00:48.091983 [CA 2] Center 36 (8~64) winsize 57
6024 10:00:48.095541 [CA 3] Center 36 (8~64) winsize 57
6025 10:00:48.098626 [CA 4] Center 36 (8~64) winsize 57
6026 10:00:48.101992 [CA 5] Center 36 (8~64) winsize 57
6027 10:00:48.102073
6028 10:00:48.105072 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6029 10:00:48.105152
6030 10:00:48.108412 [CATrainingPosCal] consider 2 rank data
6031 10:00:48.112122 u2DelayCellTimex100 = 270/100 ps
6032 10:00:48.115205 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6033 10:00:48.118703 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6034 10:00:48.121776 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6035 10:00:48.128451 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6036 10:00:48.131862 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6037 10:00:48.135054 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6038 10:00:48.135134
6039 10:00:48.138413 CA PerBit enable=1, Macro0, CA PI delay=36
6040 10:00:48.138494
6041 10:00:48.141792 [CBTSetCACLKResult] CA Dly = 36
6042 10:00:48.141872 CS Dly: 1 (0~32)
6043 10:00:48.141936
6044 10:00:48.144880 ----->DramcWriteLeveling(PI) begin...
6045 10:00:48.148511 ==
6046 10:00:48.148593 Dram Type= 6, Freq= 0, CH_0, rank 0
6047 10:00:48.154979 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6048 10:00:48.155061 ==
6049 10:00:48.158451 Write leveling (Byte 0): 32 => 0
6050 10:00:48.161517 Write leveling (Byte 1): 32 => 0
6051 10:00:48.161597 DramcWriteLeveling(PI) end<-----
6052 10:00:48.164871
6053 10:00:48.164951 ==
6054 10:00:48.168344 Dram Type= 6, Freq= 0, CH_0, rank 0
6055 10:00:48.171415 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6056 10:00:48.171496 ==
6057 10:00:48.174798 [Gating] SW mode calibration
6058 10:00:48.181382 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6059 10:00:48.184813 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6060 10:00:48.191426 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6061 10:00:48.194507 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6062 10:00:48.197971 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6063 10:00:48.204475 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6064 10:00:48.207826 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6065 10:00:48.211263 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6066 10:00:48.218219 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6067 10:00:48.221080 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6068 10:00:48.224361 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6069 10:00:48.227793 Total UI for P1: 0, mck2ui 16
6070 10:00:48.231036 best dqsien dly found for B0: ( 0, 10, 16)
6071 10:00:48.234681 Total UI for P1: 0, mck2ui 16
6072 10:00:48.237826 best dqsien dly found for B1: ( 0, 10, 16)
6073 10:00:48.240896 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6074 10:00:48.244279 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6075 10:00:48.247514
6076 10:00:48.251015 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6077 10:00:48.254184 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6078 10:00:48.257522 [Gating] SW calibration Done
6079 10:00:48.257671 ==
6080 10:00:48.260875 Dram Type= 6, Freq= 0, CH_0, rank 0
6081 10:00:48.264111 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6082 10:00:48.264191 ==
6083 10:00:48.264255 RX Vref Scan: 0
6084 10:00:48.267321
6085 10:00:48.267400 RX Vref 0 -> 0, step: 1
6086 10:00:48.267463
6087 10:00:48.270743 RX Delay -410 -> 252, step: 16
6088 10:00:48.274171 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6089 10:00:48.280705 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6090 10:00:48.284044 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6091 10:00:48.287702 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6092 10:00:48.290659 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6093 10:00:48.297511 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6094 10:00:48.300495 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6095 10:00:48.303957 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6096 10:00:48.307344 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6097 10:00:48.314010 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6098 10:00:48.317206 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6099 10:00:48.320451 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6100 10:00:48.323809 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6101 10:00:48.330476 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6102 10:00:48.333734 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6103 10:00:48.337127 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6104 10:00:48.337213 ==
6105 10:00:48.340299 Dram Type= 6, Freq= 0, CH_0, rank 0
6106 10:00:48.347003 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6107 10:00:48.347109 ==
6108 10:00:48.347201 DQS Delay:
6109 10:00:48.350309 DQS0 = 51, DQS1 = 59
6110 10:00:48.350390 DQM Delay:
6111 10:00:48.350462 DQM0 = 11, DQM1 = 13
6112 10:00:48.353645 DQ Delay:
6113 10:00:48.357064 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6114 10:00:48.357150 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6115 10:00:48.360483 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6116 10:00:48.363566 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6117 10:00:48.363650
6118 10:00:48.367038
6119 10:00:48.367117 ==
6120 10:00:48.370125 Dram Type= 6, Freq= 0, CH_0, rank 0
6121 10:00:48.373478 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6122 10:00:48.373558 ==
6123 10:00:48.373623
6124 10:00:48.373681
6125 10:00:48.376878 TX Vref Scan disable
6126 10:00:48.376958 == TX Byte 0 ==
6127 10:00:48.380057 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6128 10:00:48.386695 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6129 10:00:48.386776 == TX Byte 1 ==
6130 10:00:48.390155 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6131 10:00:48.396851 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6132 10:00:48.396938 ==
6133 10:00:48.400101 Dram Type= 6, Freq= 0, CH_0, rank 0
6134 10:00:48.403415 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6135 10:00:48.403495 ==
6136 10:00:48.403560
6137 10:00:48.403625
6138 10:00:48.407022 TX Vref Scan disable
6139 10:00:48.407103 == TX Byte 0 ==
6140 10:00:48.413551 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6141 10:00:48.416810 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6142 10:00:48.416895 == TX Byte 1 ==
6143 10:00:48.423524 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6144 10:00:48.426955 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6145 10:00:48.427035
6146 10:00:48.427098 [DATLAT]
6147 10:00:48.430137 Freq=400, CH0 RK0
6148 10:00:48.430216
6149 10:00:48.430279 DATLAT Default: 0xf
6150 10:00:48.433379 0, 0xFFFF, sum = 0
6151 10:00:48.433466 1, 0xFFFF, sum = 0
6152 10:00:48.436491 2, 0xFFFF, sum = 0
6153 10:00:48.436639 3, 0xFFFF, sum = 0
6154 10:00:48.439948 4, 0xFFFF, sum = 0
6155 10:00:48.440054 5, 0xFFFF, sum = 0
6156 10:00:48.443169 6, 0xFFFF, sum = 0
6157 10:00:48.443251 7, 0xFFFF, sum = 0
6158 10:00:48.446946 8, 0xFFFF, sum = 0
6159 10:00:48.447027 9, 0xFFFF, sum = 0
6160 10:00:48.449860 10, 0xFFFF, sum = 0
6161 10:00:48.453156 11, 0xFFFF, sum = 0
6162 10:00:48.453236 12, 0x0, sum = 1
6163 10:00:48.453301 13, 0x0, sum = 2
6164 10:00:48.456398 14, 0x0, sum = 3
6165 10:00:48.456478 15, 0x0, sum = 4
6166 10:00:48.459958 best_step = 13
6167 10:00:48.460044
6168 10:00:48.460108 ==
6169 10:00:48.462934 Dram Type= 6, Freq= 0, CH_0, rank 0
6170 10:00:48.466282 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6171 10:00:48.466362 ==
6172 10:00:48.469613 RX Vref Scan: 1
6173 10:00:48.469700
6174 10:00:48.469763 RX Vref 0 -> 0, step: 1
6175 10:00:48.472783
6176 10:00:48.472862 RX Delay -359 -> 252, step: 8
6177 10:00:48.472926
6178 10:00:48.476166 Set Vref, RX VrefLevel [Byte0]: 49
6179 10:00:48.479430 [Byte1]: 46
6180 10:00:48.484718
6181 10:00:48.484798 Final RX Vref Byte 0 = 49 to rank0
6182 10:00:48.488031 Final RX Vref Byte 1 = 46 to rank0
6183 10:00:48.491697 Final RX Vref Byte 0 = 49 to rank1
6184 10:00:48.494757 Final RX Vref Byte 1 = 46 to rank1==
6185 10:00:48.497937 Dram Type= 6, Freq= 0, CH_0, rank 0
6186 10:00:48.504972 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6187 10:00:48.505079 ==
6188 10:00:48.505171 DQS Delay:
6189 10:00:48.508022 DQS0 = 52, DQS1 = 68
6190 10:00:48.508115 DQM Delay:
6191 10:00:48.508201 DQM0 = 9, DQM1 = 17
6192 10:00:48.511336 DQ Delay:
6193 10:00:48.514706 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =4
6194 10:00:48.514786 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6195 10:00:48.518036 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6196 10:00:48.521588 DQ12 =24, DQ13 =28, DQ14 =28, DQ15 =28
6197 10:00:48.521669
6198 10:00:48.521733
6199 10:00:48.531588 [DQSOSCAuto] RK0, (LSB)MR18= 0xb0b0, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6200 10:00:48.534580 CH0 RK0: MR19=C0C, MR18=B0B0
6201 10:00:48.541434 CH0_RK0: MR19=0xC0C, MR18=0xB0B0, DQSOSC=387, MR23=63, INC=394, DEC=262
6202 10:00:48.541515 ==
6203 10:00:48.544539 Dram Type= 6, Freq= 0, CH_0, rank 1
6204 10:00:48.547781 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6205 10:00:48.547886 ==
6206 10:00:48.551042 [Gating] SW mode calibration
6207 10:00:48.557845 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6208 10:00:48.560925 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6209 10:00:48.567533 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6210 10:00:48.570918 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6211 10:00:48.574128 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6212 10:00:48.580865 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6213 10:00:48.584108 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6214 10:00:48.587557 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6215 10:00:48.594141 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6216 10:00:48.597572 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6217 10:00:48.600800 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6218 10:00:48.604062 Total UI for P1: 0, mck2ui 16
6219 10:00:48.607430 best dqsien dly found for B0: ( 0, 10, 16)
6220 10:00:48.610620 Total UI for P1: 0, mck2ui 16
6221 10:00:48.613987 best dqsien dly found for B1: ( 0, 10, 16)
6222 10:00:48.617311 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6223 10:00:48.623784 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6224 10:00:48.623865
6225 10:00:48.627185 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6226 10:00:48.630559 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6227 10:00:48.633766 [Gating] SW calibration Done
6228 10:00:48.633847 ==
6229 10:00:48.637064 Dram Type= 6, Freq= 0, CH_0, rank 1
6230 10:00:48.640443 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6231 10:00:48.640561 ==
6232 10:00:48.643810 RX Vref Scan: 0
6233 10:00:48.643890
6234 10:00:48.643952 RX Vref 0 -> 0, step: 1
6235 10:00:48.644011
6236 10:00:48.647110 RX Delay -410 -> 252, step: 16
6237 10:00:48.650373 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6238 10:00:48.657410 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6239 10:00:48.660372 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6240 10:00:48.663961 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6241 10:00:48.667079 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6242 10:00:48.673832 iDelay=230, Bit 5, Center -51 (-314 ~ 213) 528
6243 10:00:48.676931 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6244 10:00:48.680440 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6245 10:00:48.683680 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6246 10:00:48.690393 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6247 10:00:48.693742 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6248 10:00:48.696978 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6249 10:00:48.700229 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6250 10:00:48.706902 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6251 10:00:48.710545 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6252 10:00:48.713687 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6253 10:00:48.713769 ==
6254 10:00:48.716827 Dram Type= 6, Freq= 0, CH_0, rank 1
6255 10:00:48.723621 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6256 10:00:48.723715 ==
6257 10:00:48.723810 DQS Delay:
6258 10:00:48.727021 DQS0 = 51, DQS1 = 59
6259 10:00:48.727102 DQM Delay:
6260 10:00:48.727165 DQM0 = 14, DQM1 = 15
6261 10:00:48.730262 DQ Delay:
6262 10:00:48.733494 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6263 10:00:48.733575 DQ4 =24, DQ5 =0, DQ6 =24, DQ7 =24
6264 10:00:48.736925 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6265 10:00:48.740357 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6266 10:00:48.740438
6267 10:00:48.743542
6268 10:00:48.743625 ==
6269 10:00:48.746907 Dram Type= 6, Freq= 0, CH_0, rank 1
6270 10:00:48.750226 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6271 10:00:48.750306 ==
6272 10:00:48.750368
6273 10:00:48.750426
6274 10:00:48.753511 TX Vref Scan disable
6275 10:00:48.753592 == TX Byte 0 ==
6276 10:00:48.756727 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6277 10:00:48.763476 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6278 10:00:48.763561 == TX Byte 1 ==
6279 10:00:48.766739 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6280 10:00:48.773202 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6281 10:00:48.773293 ==
6282 10:00:48.776625 Dram Type= 6, Freq= 0, CH_0, rank 1
6283 10:00:48.779904 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6284 10:00:48.779989 ==
6285 10:00:48.780053
6286 10:00:48.780111
6287 10:00:48.783369 TX Vref Scan disable
6288 10:00:48.783452 == TX Byte 0 ==
6289 10:00:48.786508 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6290 10:00:48.793161 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6291 10:00:48.793242 == TX Byte 1 ==
6292 10:00:48.796447 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6293 10:00:48.803120 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6294 10:00:48.803205
6295 10:00:48.803272 [DATLAT]
6296 10:00:48.803330 Freq=400, CH0 RK1
6297 10:00:48.806497
6298 10:00:48.806581 DATLAT Default: 0xd
6299 10:00:48.809730 0, 0xFFFF, sum = 0
6300 10:00:48.809816 1, 0xFFFF, sum = 0
6301 10:00:48.813011 2, 0xFFFF, sum = 0
6302 10:00:48.813091 3, 0xFFFF, sum = 0
6303 10:00:48.816402 4, 0xFFFF, sum = 0
6304 10:00:48.816515 5, 0xFFFF, sum = 0
6305 10:00:48.819770 6, 0xFFFF, sum = 0
6306 10:00:48.819850 7, 0xFFFF, sum = 0
6307 10:00:48.823053 8, 0xFFFF, sum = 0
6308 10:00:48.823133 9, 0xFFFF, sum = 0
6309 10:00:48.826681 10, 0xFFFF, sum = 0
6310 10:00:48.826764 11, 0xFFFF, sum = 0
6311 10:00:48.829685 12, 0x0, sum = 1
6312 10:00:48.829765 13, 0x0, sum = 2
6313 10:00:48.833118 14, 0x0, sum = 3
6314 10:00:48.833198 15, 0x0, sum = 4
6315 10:00:48.836432 best_step = 13
6316 10:00:48.836557
6317 10:00:48.836622 ==
6318 10:00:48.840007 Dram Type= 6, Freq= 0, CH_0, rank 1
6319 10:00:48.843061 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6320 10:00:48.843142 ==
6321 10:00:48.846546 RX Vref Scan: 0
6322 10:00:48.846625
6323 10:00:48.846689 RX Vref 0 -> 0, step: 1
6324 10:00:48.846748
6325 10:00:48.849541 RX Delay -359 -> 252, step: 8
6326 10:00:48.857540 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6327 10:00:48.860499 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6328 10:00:48.863968 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6329 10:00:48.867435 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6330 10:00:48.873970 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6331 10:00:48.877458 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6332 10:00:48.880452 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6333 10:00:48.883861 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6334 10:00:48.890763 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6335 10:00:48.893778 iDelay=217, Bit 9, Center -64 (-303 ~ 176) 480
6336 10:00:48.897168 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6337 10:00:48.903657 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6338 10:00:48.907239 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6339 10:00:48.910318 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6340 10:00:48.913622 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6341 10:00:48.920352 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6342 10:00:48.920459 ==
6343 10:00:48.923669 Dram Type= 6, Freq= 0, CH_0, rank 1
6344 10:00:48.926966 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6345 10:00:48.927046 ==
6346 10:00:48.927111 DQS Delay:
6347 10:00:48.930267 DQS0 = 52, DQS1 = 64
6348 10:00:48.930348 DQM Delay:
6349 10:00:48.933728 DQM0 = 10, DQM1 = 13
6350 10:00:48.933808 DQ Delay:
6351 10:00:48.936832 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6352 10:00:48.940157 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6353 10:00:48.943481 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6354 10:00:48.946722 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6355 10:00:48.946803
6356 10:00:48.946867
6357 10:00:48.953602 [DQSOSCAuto] RK1, (LSB)MR18= 0xcccc, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6358 10:00:48.956672 CH0 RK1: MR19=C0C, MR18=CCCC
6359 10:00:48.963376 CH0_RK1: MR19=0xC0C, MR18=0xCCCC, DQSOSC=384, MR23=63, INC=400, DEC=267
6360 10:00:48.966911 [RxdqsGatingPostProcess] freq 400
6361 10:00:48.973213 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6362 10:00:48.976886 Pre-setting of DQS Precalculation
6363 10:00:48.980024 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6364 10:00:48.980105 ==
6365 10:00:48.983318 Dram Type= 6, Freq= 0, CH_1, rank 0
6366 10:00:48.986597 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6367 10:00:48.986679 ==
6368 10:00:48.993362 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6369 10:00:48.999862 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6370 10:00:49.003007 [CA 0] Center 36 (8~64) winsize 57
6371 10:00:49.006689 [CA 1] Center 36 (8~64) winsize 57
6372 10:00:49.009803 [CA 2] Center 36 (8~64) winsize 57
6373 10:00:49.013160 [CA 3] Center 36 (8~64) winsize 57
6374 10:00:49.016292 [CA 4] Center 36 (8~64) winsize 57
6375 10:00:49.016373 [CA 5] Center 36 (8~64) winsize 57
6376 10:00:49.019533
6377 10:00:49.022850 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6378 10:00:49.022930
6379 10:00:49.026237 [CATrainingPosCal] consider 1 rank data
6380 10:00:49.029401 u2DelayCellTimex100 = 270/100 ps
6381 10:00:49.032790 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6382 10:00:49.036205 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6383 10:00:49.039563 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6384 10:00:49.042786 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6385 10:00:49.046084 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6386 10:00:49.049397 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6387 10:00:49.049502
6388 10:00:49.052922 CA PerBit enable=1, Macro0, CA PI delay=36
6389 10:00:49.053003
6390 10:00:49.056158 [CBTSetCACLKResult] CA Dly = 36
6391 10:00:49.059536 CS Dly: 1 (0~32)
6392 10:00:49.059616 ==
6393 10:00:49.062909 Dram Type= 6, Freq= 0, CH_1, rank 1
6394 10:00:49.066016 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6395 10:00:49.066106 ==
6396 10:00:49.072883 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6397 10:00:49.079252 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6398 10:00:49.082566 [CA 0] Center 36 (8~64) winsize 57
6399 10:00:49.082667 [CA 1] Center 36 (8~64) winsize 57
6400 10:00:49.085977 [CA 2] Center 36 (8~64) winsize 57
6401 10:00:49.089389 [CA 3] Center 36 (8~64) winsize 57
6402 10:00:49.092865 [CA 4] Center 36 (8~64) winsize 57
6403 10:00:49.095891 [CA 5] Center 36 (8~64) winsize 57
6404 10:00:49.095972
6405 10:00:49.099428 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6406 10:00:49.099510
6407 10:00:49.102604 [CATrainingPosCal] consider 2 rank data
6408 10:00:49.106011 u2DelayCellTimex100 = 270/100 ps
6409 10:00:49.109141 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6410 10:00:49.115796 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6411 10:00:49.119128 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6412 10:00:49.122390 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6413 10:00:49.125708 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6414 10:00:49.129053 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6415 10:00:49.129135
6416 10:00:49.132445 CA PerBit enable=1, Macro0, CA PI delay=36
6417 10:00:49.132564
6418 10:00:49.135674 [CBTSetCACLKResult] CA Dly = 36
6419 10:00:49.139012 CS Dly: 1 (0~32)
6420 10:00:49.139092
6421 10:00:49.142402 ----->DramcWriteLeveling(PI) begin...
6422 10:00:49.142484 ==
6423 10:00:49.145551 Dram Type= 6, Freq= 0, CH_1, rank 0
6424 10:00:49.148911 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6425 10:00:49.148993 ==
6426 10:00:49.152179 Write leveling (Byte 0): 32 => 0
6427 10:00:49.155713 Write leveling (Byte 1): 32 => 0
6428 10:00:49.159204 DramcWriteLeveling(PI) end<-----
6429 10:00:49.159284
6430 10:00:49.159348 ==
6431 10:00:49.162222 Dram Type= 6, Freq= 0, CH_1, rank 0
6432 10:00:49.165370 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6433 10:00:49.165451 ==
6434 10:00:49.168511 [Gating] SW mode calibration
6435 10:00:49.175405 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6436 10:00:49.181947 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6437 10:00:49.185228 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6438 10:00:49.188504 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6439 10:00:49.195105 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6440 10:00:49.198441 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6441 10:00:49.201944 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6442 10:00:49.208479 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6443 10:00:49.211701 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6444 10:00:49.215092 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6445 10:00:49.221601 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6446 10:00:49.221685 Total UI for P1: 0, mck2ui 16
6447 10:00:49.228341 best dqsien dly found for B0: ( 0, 10, 16)
6448 10:00:49.228423 Total UI for P1: 0, mck2ui 16
6449 10:00:49.231691 best dqsien dly found for B1: ( 0, 10, 16)
6450 10:00:49.238103 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6451 10:00:49.241466 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6452 10:00:49.241548
6453 10:00:49.244960 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6454 10:00:49.248330 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6455 10:00:49.251560 [Gating] SW calibration Done
6456 10:00:49.251641 ==
6457 10:00:49.254773 Dram Type= 6, Freq= 0, CH_1, rank 0
6458 10:00:49.258125 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6459 10:00:49.258206 ==
6460 10:00:49.261296 RX Vref Scan: 0
6461 10:00:49.261378
6462 10:00:49.261442 RX Vref 0 -> 0, step: 1
6463 10:00:49.261502
6464 10:00:49.264766 RX Delay -410 -> 252, step: 16
6465 10:00:49.271255 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6466 10:00:49.274583 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6467 10:00:49.277940 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6468 10:00:49.281187 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6469 10:00:49.287778 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6470 10:00:49.291069 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6471 10:00:49.294506 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6472 10:00:49.297907 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6473 10:00:49.304669 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6474 10:00:49.307744 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6475 10:00:49.311226 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6476 10:00:49.314633 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6477 10:00:49.321153 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6478 10:00:49.324909 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6479 10:00:49.327647 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6480 10:00:49.330912 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6481 10:00:49.334298 ==
6482 10:00:49.337549 Dram Type= 6, Freq= 0, CH_1, rank 0
6483 10:00:49.340948 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6484 10:00:49.341031 ==
6485 10:00:49.341095 DQS Delay:
6486 10:00:49.344545 DQS0 = 43, DQS1 = 59
6487 10:00:49.344640 DQM Delay:
6488 10:00:49.347608 DQM0 = 6, DQM1 = 15
6489 10:00:49.347689 DQ Delay:
6490 10:00:49.350864 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6491 10:00:49.354266 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6492 10:00:49.357792 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6493 10:00:49.360904 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6494 10:00:49.360985
6495 10:00:49.361049
6496 10:00:49.361107 ==
6497 10:00:49.364343 Dram Type= 6, Freq= 0, CH_1, rank 0
6498 10:00:49.367694 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6499 10:00:49.367776 ==
6500 10:00:49.367840
6501 10:00:49.367900
6502 10:00:49.371103 TX Vref Scan disable
6503 10:00:49.371184 == TX Byte 0 ==
6504 10:00:49.377688 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6505 10:00:49.380905 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6506 10:00:49.380986 == TX Byte 1 ==
6507 10:00:49.387672 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6508 10:00:49.390698 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6509 10:00:49.390779 ==
6510 10:00:49.393972 Dram Type= 6, Freq= 0, CH_1, rank 0
6511 10:00:49.397488 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6512 10:00:49.397569 ==
6513 10:00:49.397633
6514 10:00:49.397691
6515 10:00:49.400763 TX Vref Scan disable
6516 10:00:49.400844 == TX Byte 0 ==
6517 10:00:49.407424 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6518 10:00:49.410759 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6519 10:00:49.410846 == TX Byte 1 ==
6520 10:00:49.417372 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6521 10:00:49.420644 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6522 10:00:49.420726
6523 10:00:49.420790 [DATLAT]
6524 10:00:49.423997 Freq=400, CH1 RK0
6525 10:00:49.424078
6526 10:00:49.424142 DATLAT Default: 0xf
6527 10:00:49.427194 0, 0xFFFF, sum = 0
6528 10:00:49.427303 1, 0xFFFF, sum = 0
6529 10:00:49.430444 2, 0xFFFF, sum = 0
6530 10:00:49.433722 3, 0xFFFF, sum = 0
6531 10:00:49.433811 4, 0xFFFF, sum = 0
6532 10:00:49.437077 5, 0xFFFF, sum = 0
6533 10:00:49.437161 6, 0xFFFF, sum = 0
6534 10:00:49.440492 7, 0xFFFF, sum = 0
6535 10:00:49.440617 8, 0xFFFF, sum = 0
6536 10:00:49.443976 9, 0xFFFF, sum = 0
6537 10:00:49.444083 10, 0xFFFF, sum = 0
6538 10:00:49.446984 11, 0xFFFF, sum = 0
6539 10:00:49.447067 12, 0x0, sum = 1
6540 10:00:49.450563 13, 0x0, sum = 2
6541 10:00:49.450645 14, 0x0, sum = 3
6542 10:00:49.453629 15, 0x0, sum = 4
6543 10:00:49.453711 best_step = 13
6544 10:00:49.453775
6545 10:00:49.453834 ==
6546 10:00:49.456922 Dram Type= 6, Freq= 0, CH_1, rank 0
6547 10:00:49.460405 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6548 10:00:49.463566 ==
6549 10:00:49.463647 RX Vref Scan: 1
6550 10:00:49.463710
6551 10:00:49.466973 RX Vref 0 -> 0, step: 1
6552 10:00:49.467053
6553 10:00:49.467116 RX Delay -359 -> 252, step: 8
6554 10:00:49.470263
6555 10:00:49.470344 Set Vref, RX VrefLevel [Byte0]: 58
6556 10:00:49.473859 [Byte1]: 48
6557 10:00:49.479364
6558 10:00:49.479444 Final RX Vref Byte 0 = 58 to rank0
6559 10:00:49.482649 Final RX Vref Byte 1 = 48 to rank0
6560 10:00:49.485970 Final RX Vref Byte 0 = 58 to rank1
6561 10:00:49.489222 Final RX Vref Byte 1 = 48 to rank1==
6562 10:00:49.492735 Dram Type= 6, Freq= 0, CH_1, rank 0
6563 10:00:49.499179 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6564 10:00:49.499293 ==
6565 10:00:49.499381 DQS Delay:
6566 10:00:49.502547 DQS0 = 52, DQS1 = 64
6567 10:00:49.502628 DQM Delay:
6568 10:00:49.502692 DQM0 = 10, DQM1 = 16
6569 10:00:49.505850 DQ Delay:
6570 10:00:49.509124 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6571 10:00:49.509230 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6572 10:00:49.512365 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6573 10:00:49.515759 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =28
6574 10:00:49.515845
6575 10:00:49.519041
6576 10:00:49.525652 [DQSOSCAuto] RK0, (LSB)MR18= 0xe4e4, (MSB)MR19= 0xc0c, tDQSOscB0 = 381 ps tDQSOscB1 = 381 ps
6577 10:00:49.528992 CH1 RK0: MR19=C0C, MR18=E4E4
6578 10:00:49.535738 CH1_RK0: MR19=0xC0C, MR18=0xE4E4, DQSOSC=381, MR23=63, INC=406, DEC=271
6579 10:00:49.535821 ==
6580 10:00:49.539023 Dram Type= 6, Freq= 0, CH_1, rank 1
6581 10:00:49.542278 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6582 10:00:49.542351 ==
6583 10:00:49.545603 [Gating] SW mode calibration
6584 10:00:49.552229 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6585 10:00:49.555484 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6586 10:00:49.562200 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6587 10:00:49.565486 0 7 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
6588 10:00:49.568752 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6589 10:00:49.575572 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6590 10:00:49.578750 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6591 10:00:49.582226 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6592 10:00:49.588677 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6593 10:00:49.592218 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6594 10:00:49.595335 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6595 10:00:49.598574 Total UI for P1: 0, mck2ui 16
6596 10:00:49.602013 best dqsien dly found for B0: ( 0, 10, 16)
6597 10:00:49.605070 Total UI for P1: 0, mck2ui 16
6598 10:00:49.608413 best dqsien dly found for B1: ( 0, 10, 16)
6599 10:00:49.611736 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6600 10:00:49.618423 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6601 10:00:49.618505
6602 10:00:49.621636 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6603 10:00:49.624956 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6604 10:00:49.628317 [Gating] SW calibration Done
6605 10:00:49.628398 ==
6606 10:00:49.631668 Dram Type= 6, Freq= 0, CH_1, rank 1
6607 10:00:49.635018 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6608 10:00:49.635099 ==
6609 10:00:49.638155 RX Vref Scan: 0
6610 10:00:49.638236
6611 10:00:49.638301 RX Vref 0 -> 0, step: 1
6612 10:00:49.638361
6613 10:00:49.641497 RX Delay -410 -> 252, step: 16
6614 10:00:49.648235 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6615 10:00:49.651345 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6616 10:00:49.654802 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6617 10:00:49.658004 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6618 10:00:49.664880 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6619 10:00:49.668097 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6620 10:00:49.671449 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6621 10:00:49.674935 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6622 10:00:49.681317 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6623 10:00:49.684756 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6624 10:00:49.688038 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6625 10:00:49.691243 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6626 10:00:49.697759 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6627 10:00:49.701096 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6628 10:00:49.704490 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6629 10:00:49.707632 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6630 10:00:49.710925 ==
6631 10:00:49.714487 Dram Type= 6, Freq= 0, CH_1, rank 1
6632 10:00:49.717884 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6633 10:00:49.717967 ==
6634 10:00:49.718032 DQS Delay:
6635 10:00:49.720942 DQS0 = 43, DQS1 = 59
6636 10:00:49.721023 DQM Delay:
6637 10:00:49.724166 DQM0 = 10, DQM1 = 17
6638 10:00:49.724249 DQ Delay:
6639 10:00:49.727626 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6640 10:00:49.731117 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6641 10:00:49.734250 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6642 10:00:49.737505 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6643 10:00:49.737587
6644 10:00:49.737650
6645 10:00:49.737716 ==
6646 10:00:49.740951 Dram Type= 6, Freq= 0, CH_1, rank 1
6647 10:00:49.744494 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6648 10:00:49.744619 ==
6649 10:00:49.744690
6650 10:00:49.744750
6651 10:00:49.747901 TX Vref Scan disable
6652 10:00:49.747986 == TX Byte 0 ==
6653 10:00:49.753970 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6654 10:00:49.757664 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6655 10:00:49.757745 == TX Byte 1 ==
6656 10:00:49.760900 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6657 10:00:49.767669 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6658 10:00:49.767750 ==
6659 10:00:49.770781 Dram Type= 6, Freq= 0, CH_1, rank 1
6660 10:00:49.774015 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6661 10:00:49.774096 ==
6662 10:00:49.774159
6663 10:00:49.774218
6664 10:00:49.777431 TX Vref Scan disable
6665 10:00:49.777512 == TX Byte 0 ==
6666 10:00:49.784217 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6667 10:00:49.787534 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6668 10:00:49.787615 == TX Byte 1 ==
6669 10:00:49.793950 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6670 10:00:49.797260 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6671 10:00:49.797341
6672 10:00:49.797405 [DATLAT]
6673 10:00:49.800471 Freq=400, CH1 RK1
6674 10:00:49.800595
6675 10:00:49.800659 DATLAT Default: 0xd
6676 10:00:49.803981 0, 0xFFFF, sum = 0
6677 10:00:49.804063 1, 0xFFFF, sum = 0
6678 10:00:49.807302 2, 0xFFFF, sum = 0
6679 10:00:49.807384 3, 0xFFFF, sum = 0
6680 10:00:49.810540 4, 0xFFFF, sum = 0
6681 10:00:49.810623 5, 0xFFFF, sum = 0
6682 10:00:49.813651 6, 0xFFFF, sum = 0
6683 10:00:49.813733 7, 0xFFFF, sum = 0
6684 10:00:49.817262 8, 0xFFFF, sum = 0
6685 10:00:49.817344 9, 0xFFFF, sum = 0
6686 10:00:49.820383 10, 0xFFFF, sum = 0
6687 10:00:49.820465 11, 0xFFFF, sum = 0
6688 10:00:49.823897 12, 0x0, sum = 1
6689 10:00:49.823978 13, 0x0, sum = 2
6690 10:00:49.826943 14, 0x0, sum = 3
6691 10:00:49.827024 15, 0x0, sum = 4
6692 10:00:49.830578 best_step = 13
6693 10:00:49.830659
6694 10:00:49.830722 ==
6695 10:00:49.833756 Dram Type= 6, Freq= 0, CH_1, rank 1
6696 10:00:49.836870 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6697 10:00:49.836951 ==
6698 10:00:49.840275 RX Vref Scan: 0
6699 10:00:49.840355
6700 10:00:49.840418 RX Vref 0 -> 0, step: 1
6701 10:00:49.840477
6702 10:00:49.843627 RX Delay -359 -> 252, step: 8
6703 10:00:49.851695 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6704 10:00:49.855019 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6705 10:00:49.858421 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6706 10:00:49.861779 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6707 10:00:49.868304 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6708 10:00:49.871697 iDelay=217, Bit 5, Center -32 (-279 ~ 216) 496
6709 10:00:49.875062 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6710 10:00:49.878392 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6711 10:00:49.885040 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6712 10:00:49.888315 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6713 10:00:49.892004 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6714 10:00:49.894995 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6715 10:00:49.901495 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6716 10:00:49.904873 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6717 10:00:49.908272 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6718 10:00:49.915017 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6719 10:00:49.915100 ==
6720 10:00:49.918458 Dram Type= 6, Freq= 0, CH_1, rank 1
6721 10:00:49.921515 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6722 10:00:49.921597 ==
6723 10:00:49.921660 DQS Delay:
6724 10:00:49.924832 DQS0 = 48, DQS1 = 64
6725 10:00:49.924913 DQM Delay:
6726 10:00:49.928076 DQM0 = 9, DQM1 = 15
6727 10:00:49.928157 DQ Delay:
6728 10:00:49.931503 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6729 10:00:49.934817 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6730 10:00:49.937983 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6731 10:00:49.941296 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =20
6732 10:00:49.941377
6733 10:00:49.941441
6734 10:00:49.947980 [DQSOSCAuto] RK1, (LSB)MR18= 0xa9a9, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6735 10:00:49.951193 CH1 RK1: MR19=C0C, MR18=A9A9
6736 10:00:49.957871 CH1_RK1: MR19=0xC0C, MR18=0xA9A9, DQSOSC=388, MR23=63, INC=392, DEC=261
6737 10:00:49.961406 [RxdqsGatingPostProcess] freq 400
6738 10:00:49.967745 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6739 10:00:49.967827 Pre-setting of DQS Precalculation
6740 10:00:49.974362 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6741 10:00:49.981087 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6742 10:00:49.987726 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6743 10:00:49.987807
6744 10:00:49.987871
6745 10:00:49.990889 [Calibration Summary] 800 Mbps
6746 10:00:49.994360 CH 0, Rank 0
6747 10:00:49.994441 SW Impedance : PASS
6748 10:00:49.997513 DUTY Scan : NO K
6749 10:00:50.001134 ZQ Calibration : PASS
6750 10:00:50.001215 Jitter Meter : NO K
6751 10:00:50.004250 CBT Training : PASS
6752 10:00:50.007517 Write leveling : PASS
6753 10:00:50.007598 RX DQS gating : PASS
6754 10:00:50.010676 RX DQ/DQS(RDDQC) : PASS
6755 10:00:50.010757 TX DQ/DQS : PASS
6756 10:00:50.013991 RX DATLAT : PASS
6757 10:00:50.017717 RX DQ/DQS(Engine): PASS
6758 10:00:50.017798 TX OE : NO K
6759 10:00:50.020793 All Pass.
6760 10:00:50.020874
6761 10:00:50.020938 CH 0, Rank 1
6762 10:00:50.023927 SW Impedance : PASS
6763 10:00:50.024007 DUTY Scan : NO K
6764 10:00:50.027411 ZQ Calibration : PASS
6765 10:00:50.030914 Jitter Meter : NO K
6766 10:00:50.030995 CBT Training : PASS
6767 10:00:50.034015 Write leveling : NO K
6768 10:00:50.037308 RX DQS gating : PASS
6769 10:00:50.037389 RX DQ/DQS(RDDQC) : PASS
6770 10:00:50.040464 TX DQ/DQS : PASS
6771 10:00:50.043864 RX DATLAT : PASS
6772 10:00:50.043944 RX DQ/DQS(Engine): PASS
6773 10:00:50.047182 TX OE : NO K
6774 10:00:50.047263 All Pass.
6775 10:00:50.047327
6776 10:00:50.050510 CH 1, Rank 0
6777 10:00:50.050590 SW Impedance : PASS
6778 10:00:50.053693 DUTY Scan : NO K
6779 10:00:50.057139 ZQ Calibration : PASS
6780 10:00:50.057220 Jitter Meter : NO K
6781 10:00:50.060382 CBT Training : PASS
6782 10:00:50.063601 Write leveling : PASS
6783 10:00:50.063681 RX DQS gating : PASS
6784 10:00:50.066903 RX DQ/DQS(RDDQC) : PASS
6785 10:00:50.070456 TX DQ/DQS : PASS
6786 10:00:50.070537 RX DATLAT : PASS
6787 10:00:50.073741 RX DQ/DQS(Engine): PASS
6788 10:00:50.073822 TX OE : NO K
6789 10:00:50.077175 All Pass.
6790 10:00:50.077255
6791 10:00:50.077319 CH 1, Rank 1
6792 10:00:50.080386 SW Impedance : PASS
6793 10:00:50.080466 DUTY Scan : NO K
6794 10:00:50.083630 ZQ Calibration : PASS
6795 10:00:50.087172 Jitter Meter : NO K
6796 10:00:50.087252 CBT Training : PASS
6797 10:00:50.090267 Write leveling : NO K
6798 10:00:50.093501 RX DQS gating : PASS
6799 10:00:50.093601 RX DQ/DQS(RDDQC) : PASS
6800 10:00:50.097067 TX DQ/DQS : PASS
6801 10:00:50.100434 RX DATLAT : PASS
6802 10:00:50.100537 RX DQ/DQS(Engine): PASS
6803 10:00:50.103537 TX OE : NO K
6804 10:00:50.103618 All Pass.
6805 10:00:50.103682
6806 10:00:50.106675 DramC Write-DBI off
6807 10:00:50.110105 PER_BANK_REFRESH: Hybrid Mode
6808 10:00:50.110185 TX_TRACKING: ON
6809 10:00:50.119906 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6810 10:00:50.123331 [FAST_K] Save calibration result to emmc
6811 10:00:50.126525 dramc_set_vcore_voltage set vcore to 725000
6812 10:00:50.129975 Read voltage for 1600, 0
6813 10:00:50.130056 Vio18 = 0
6814 10:00:50.130120 Vcore = 725000
6815 10:00:50.133084 Vdram = 0
6816 10:00:50.133165 Vddq = 0
6817 10:00:50.133228 Vmddr = 0
6818 10:00:50.139852 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6819 10:00:50.142901 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6820 10:00:50.146381 MEM_TYPE=3, freq_sel=13
6821 10:00:50.149820 sv_algorithm_assistance_LP4_3733
6822 10:00:50.153169 ============ PULL DRAM RESETB DOWN ============
6823 10:00:50.159562 ========== PULL DRAM RESETB DOWN end =========
6824 10:00:50.162828 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6825 10:00:50.166094 ===================================
6826 10:00:50.169602 LPDDR4 DRAM CONFIGURATION
6827 10:00:50.172781 ===================================
6828 10:00:50.172862 EX_ROW_EN[0] = 0x0
6829 10:00:50.176157 EX_ROW_EN[1] = 0x0
6830 10:00:50.176237 LP4Y_EN = 0x0
6831 10:00:50.179514 WORK_FSP = 0x1
6832 10:00:50.179594 WL = 0x5
6833 10:00:50.182958 RL = 0x5
6834 10:00:50.183038 BL = 0x2
6835 10:00:50.186039 RPST = 0x0
6836 10:00:50.186120 RD_PRE = 0x0
6837 10:00:50.189378 WR_PRE = 0x1
6838 10:00:50.192760 WR_PST = 0x1
6839 10:00:50.192841 DBI_WR = 0x0
6840 10:00:50.195869 DBI_RD = 0x0
6841 10:00:50.195949 OTF = 0x1
6842 10:00:50.199238 ===================================
6843 10:00:50.202628 ===================================
6844 10:00:50.202708 ANA top config
6845 10:00:50.205817 ===================================
6846 10:00:50.209115 DLL_ASYNC_EN = 0
6847 10:00:50.212576 ALL_SLAVE_EN = 0
6848 10:00:50.215718 NEW_RANK_MODE = 1
6849 10:00:50.218973 DLL_IDLE_MODE = 1
6850 10:00:50.219054 LP45_APHY_COMB_EN = 1
6851 10:00:50.222339 TX_ODT_DIS = 0
6852 10:00:50.225607 NEW_8X_MODE = 1
6853 10:00:50.228968 ===================================
6854 10:00:50.232236 ===================================
6855 10:00:50.235574 data_rate = 3200
6856 10:00:50.238850 CKR = 1
6857 10:00:50.242169 DQ_P2S_RATIO = 8
6858 10:00:50.245687 ===================================
6859 10:00:50.245768 CA_P2S_RATIO = 8
6860 10:00:50.248840 DQ_CA_OPEN = 0
6861 10:00:50.252154 DQ_SEMI_OPEN = 0
6862 10:00:50.255458 CA_SEMI_OPEN = 0
6863 10:00:50.259050 CA_FULL_RATE = 0
6864 10:00:50.259131 DQ_CKDIV4_EN = 0
6865 10:00:50.262131 CA_CKDIV4_EN = 0
6866 10:00:50.265921 CA_PREDIV_EN = 0
6867 10:00:50.268700 PH8_DLY = 12
6868 10:00:50.272095 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6869 10:00:50.275377 DQ_AAMCK_DIV = 4
6870 10:00:50.278620 CA_AAMCK_DIV = 4
6871 10:00:50.278700 CA_ADMCK_DIV = 4
6872 10:00:50.282002 DQ_TRACK_CA_EN = 0
6873 10:00:50.285481 CA_PICK = 1600
6874 10:00:50.288441 CA_MCKIO = 1600
6875 10:00:50.291936 MCKIO_SEMI = 0
6876 10:00:50.295328 PLL_FREQ = 3068
6877 10:00:50.298455 DQ_UI_PI_RATIO = 32
6878 10:00:50.298540 CA_UI_PI_RATIO = 0
6879 10:00:50.301843 ===================================
6880 10:00:50.305186 ===================================
6881 10:00:50.308491 memory_type:LPDDR4
6882 10:00:50.311911 GP_NUM : 10
6883 10:00:50.311992 SRAM_EN : 1
6884 10:00:50.314907 MD32_EN : 0
6885 10:00:50.318278 ===================================
6886 10:00:50.321604 [ANA_INIT] >>>>>>>>>>>>>>
6887 10:00:50.325011 <<<<<< [CONFIGURE PHASE]: ANA_TX
6888 10:00:50.328444 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6889 10:00:50.331714 ===================================
6890 10:00:50.331795 data_rate = 3200,PCW = 0X7600
6891 10:00:50.334937 ===================================
6892 10:00:50.338345 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6893 10:00:50.344948 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6894 10:00:50.351409 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6895 10:00:50.355033 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6896 10:00:50.358198 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6897 10:00:50.361884 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6898 10:00:50.364847 [ANA_INIT] flow start
6899 10:00:50.368110 [ANA_INIT] PLL >>>>>>>>
6900 10:00:50.368191 [ANA_INIT] PLL <<<<<<<<
6901 10:00:50.371770 [ANA_INIT] MIDPI >>>>>>>>
6902 10:00:50.374668 [ANA_INIT] MIDPI <<<<<<<<
6903 10:00:50.374748 [ANA_INIT] DLL >>>>>>>>
6904 10:00:50.378132 [ANA_INIT] DLL <<<<<<<<
6905 10:00:50.381237 [ANA_INIT] flow end
6906 10:00:50.384795 ============ LP4 DIFF to SE enter ============
6907 10:00:50.387908 ============ LP4 DIFF to SE exit ============
6908 10:00:50.391285 [ANA_INIT] <<<<<<<<<<<<<
6909 10:00:50.394540 [Flow] Enable top DCM control >>>>>
6910 10:00:50.397881 [Flow] Enable top DCM control <<<<<
6911 10:00:50.401132 Enable DLL master slave shuffle
6912 10:00:50.404558 ==============================================================
6913 10:00:50.407819 Gating Mode config
6914 10:00:50.414672 ==============================================================
6915 10:00:50.414754 Config description:
6916 10:00:50.424414 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6917 10:00:50.431168 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6918 10:00:50.434446 SELPH_MODE 0: By rank 1: By Phase
6919 10:00:50.441340 ==============================================================
6920 10:00:50.444658 GAT_TRACK_EN = 1
6921 10:00:50.447781 RX_GATING_MODE = 2
6922 10:00:50.451145 RX_GATING_TRACK_MODE = 2
6923 10:00:50.454672 SELPH_MODE = 1
6924 10:00:50.457822 PICG_EARLY_EN = 1
6925 10:00:50.461159 VALID_LAT_VALUE = 1
6926 10:00:50.464480 ==============================================================
6927 10:00:50.467636 Enter into Gating configuration >>>>
6928 10:00:50.471053 Exit from Gating configuration <<<<
6929 10:00:50.474294 Enter into DVFS_PRE_config >>>>>
6930 10:00:50.484251 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6931 10:00:50.487683 Exit from DVFS_PRE_config <<<<<
6932 10:00:50.491029 Enter into PICG configuration >>>>
6933 10:00:50.494519 Exit from PICG configuration <<<<
6934 10:00:50.497764 [RX_INPUT] configuration >>>>>
6935 10:00:50.501148 [RX_INPUT] configuration <<<<<
6936 10:00:50.507460 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6937 10:00:50.510680 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6938 10:00:50.517532 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6939 10:00:50.524220 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6940 10:00:50.530677 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6941 10:00:50.537280 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6942 10:00:50.540676 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6943 10:00:50.543773 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6944 10:00:50.547046 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6945 10:00:50.553952 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6946 10:00:50.557050 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6947 10:00:50.560417 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6948 10:00:50.563489 ===================================
6949 10:00:50.567168 LPDDR4 DRAM CONFIGURATION
6950 10:00:50.570168 ===================================
6951 10:00:50.570252 EX_ROW_EN[0] = 0x0
6952 10:00:50.573512 EX_ROW_EN[1] = 0x0
6953 10:00:50.576859 LP4Y_EN = 0x0
6954 10:00:50.576940 WORK_FSP = 0x1
6955 10:00:50.580331 WL = 0x5
6956 10:00:50.580412 RL = 0x5
6957 10:00:50.583545 BL = 0x2
6958 10:00:50.583626 RPST = 0x0
6959 10:00:50.586776 RD_PRE = 0x0
6960 10:00:50.586861 WR_PRE = 0x1
6961 10:00:50.590065 WR_PST = 0x1
6962 10:00:50.590146 DBI_WR = 0x0
6963 10:00:50.593321 DBI_RD = 0x0
6964 10:00:50.593402 OTF = 0x1
6965 10:00:50.596891 ===================================
6966 10:00:50.600034 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6967 10:00:50.606631 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6968 10:00:50.610080 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6969 10:00:50.613224 ===================================
6970 10:00:50.616485 LPDDR4 DRAM CONFIGURATION
6971 10:00:50.619873 ===================================
6972 10:00:50.619954 EX_ROW_EN[0] = 0x10
6973 10:00:50.623113 EX_ROW_EN[1] = 0x0
6974 10:00:50.626851 LP4Y_EN = 0x0
6975 10:00:50.626934 WORK_FSP = 0x1
6976 10:00:50.629844 WL = 0x5
6977 10:00:50.629926 RL = 0x5
6978 10:00:50.633246 BL = 0x2
6979 10:00:50.633327 RPST = 0x0
6980 10:00:50.636419 RD_PRE = 0x0
6981 10:00:50.636501 WR_PRE = 0x1
6982 10:00:50.640040 WR_PST = 0x1
6983 10:00:50.640121 DBI_WR = 0x0
6984 10:00:50.643054 DBI_RD = 0x0
6985 10:00:50.643135 OTF = 0x1
6986 10:00:50.646228 ===================================
6987 10:00:50.652981 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6988 10:00:50.653063 ==
6989 10:00:50.656427 Dram Type= 6, Freq= 0, CH_0, rank 0
6990 10:00:50.659607 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6991 10:00:50.662857 ==
6992 10:00:50.662938 [Duty_Offset_Calibration]
6993 10:00:50.666273 B0:0 B1:2 CA:1
6994 10:00:50.666354
6995 10:00:50.669645 [DutyScan_Calibration_Flow] k_type=0
6996 10:00:50.678660
6997 10:00:50.678803 ==CLK 0==
6998 10:00:50.681815 Final CLK duty delay cell = 0
6999 10:00:50.685110 [0] MAX Duty = 5187%(X100), DQS PI = 24
7000 10:00:50.688363 [0] MIN Duty = 4938%(X100), DQS PI = 54
7001 10:00:50.691843 [0] AVG Duty = 5062%(X100)
7002 10:00:50.691924
7003 10:00:50.695074 CH0 CLK Duty spec in!! Max-Min= 249%
7004 10:00:50.698414 [DutyScan_Calibration_Flow] ====Done====
7005 10:00:50.698495
7006 10:00:50.701544 [DutyScan_Calibration_Flow] k_type=1
7007 10:00:50.718845
7008 10:00:50.718937 ==DQS 0 ==
7009 10:00:50.721782 Final DQS duty delay cell = 0
7010 10:00:50.725194 [0] MAX Duty = 5156%(X100), DQS PI = 32
7011 10:00:50.728438 [0] MIN Duty = 5031%(X100), DQS PI = 10
7012 10:00:50.731898 [0] AVG Duty = 5093%(X100)
7013 10:00:50.731979
7014 10:00:50.732043 ==DQS 1 ==
7015 10:00:50.735182 Final DQS duty delay cell = 0
7016 10:00:50.738821 [0] MAX Duty = 5031%(X100), DQS PI = 4
7017 10:00:50.741789 [0] MIN Duty = 4876%(X100), DQS PI = 18
7018 10:00:50.744971 [0] AVG Duty = 4953%(X100)
7019 10:00:50.745051
7020 10:00:50.748387 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7021 10:00:50.748468
7022 10:00:50.751677 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7023 10:00:50.755103 [DutyScan_Calibration_Flow] ====Done====
7024 10:00:50.755183
7025 10:00:50.758233 [DutyScan_Calibration_Flow] k_type=3
7026 10:00:50.775787
7027 10:00:50.775870 ==DQM 0 ==
7028 10:00:50.778961 Final DQM duty delay cell = 0
7029 10:00:50.782502 [0] MAX Duty = 5187%(X100), DQS PI = 22
7030 10:00:50.785484 [0] MIN Duty = 4907%(X100), DQS PI = 42
7031 10:00:50.788887 [0] AVG Duty = 5047%(X100)
7032 10:00:50.788970
7033 10:00:50.789036 ==DQM 1 ==
7034 10:00:50.792212 Final DQM duty delay cell = 0
7035 10:00:50.795623 [0] MAX Duty = 5031%(X100), DQS PI = 50
7036 10:00:50.799186 [0] MIN Duty = 4782%(X100), DQS PI = 14
7037 10:00:50.802156 [0] AVG Duty = 4906%(X100)
7038 10:00:50.802239
7039 10:00:50.805502 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7040 10:00:50.805584
7041 10:00:50.808907 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7042 10:00:50.812116 [DutyScan_Calibration_Flow] ====Done====
7043 10:00:50.812198
7044 10:00:50.815293 [DutyScan_Calibration_Flow] k_type=2
7045 10:00:50.832569
7046 10:00:50.832685 ==DQ 0 ==
7047 10:00:50.835392 Final DQ duty delay cell = 0
7048 10:00:50.838647 [0] MAX Duty = 5218%(X100), DQS PI = 18
7049 10:00:50.842138 [0] MIN Duty = 4969%(X100), DQS PI = 8
7050 10:00:50.842219 [0] AVG Duty = 5093%(X100)
7051 10:00:50.845421
7052 10:00:50.845501 ==DQ 1 ==
7053 10:00:50.849005 Final DQ duty delay cell = -4
7054 10:00:50.851884 [-4] MAX Duty = 5062%(X100), DQS PI = 2
7055 10:00:50.855200 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7056 10:00:50.858654 [-4] AVG Duty = 4953%(X100)
7057 10:00:50.858736
7058 10:00:50.862177 CH0 DQ 0 Duty spec in!! Max-Min= 249%
7059 10:00:50.862258
7060 10:00:50.865240 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7061 10:00:50.868450 [DutyScan_Calibration_Flow] ====Done====
7062 10:00:50.868570 ==
7063 10:00:50.872194 Dram Type= 6, Freq= 0, CH_1, rank 0
7064 10:00:50.875165 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7065 10:00:50.875249 ==
7066 10:00:50.878578 [Duty_Offset_Calibration]
7067 10:00:50.878662 B0:0 B1:5 CA:-5
7068 10:00:50.878726
7069 10:00:50.881883 [DutyScan_Calibration_Flow] k_type=0
7070 10:00:50.892639
7071 10:00:50.892739 ==CLK 0==
7072 10:00:50.895936 Final CLK duty delay cell = 0
7073 10:00:50.899332 [0] MAX Duty = 5156%(X100), DQS PI = 20
7074 10:00:50.902953 [0] MIN Duty = 4906%(X100), DQS PI = 52
7075 10:00:50.903060 [0] AVG Duty = 5031%(X100)
7076 10:00:50.906035
7077 10:00:50.909233 CH1 CLK Duty spec in!! Max-Min= 250%
7078 10:00:50.912468 [DutyScan_Calibration_Flow] ====Done====
7079 10:00:50.912616
7080 10:00:50.915678 [DutyScan_Calibration_Flow] k_type=1
7081 10:00:50.931435
7082 10:00:50.931524 ==DQS 0 ==
7083 10:00:50.934966 Final DQS duty delay cell = 0
7084 10:00:50.938162 [0] MAX Duty = 5156%(X100), DQS PI = 18
7085 10:00:50.941577 [0] MIN Duty = 4876%(X100), DQS PI = 42
7086 10:00:50.944795 [0] AVG Duty = 5016%(X100)
7087 10:00:50.944876
7088 10:00:50.944940 ==DQS 1 ==
7089 10:00:50.948332 Final DQS duty delay cell = -4
7090 10:00:50.951445 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7091 10:00:50.954698 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7092 10:00:50.958235 [-4] AVG Duty = 4922%(X100)
7093 10:00:50.958316
7094 10:00:50.961335 CH1 DQS 0 Duty spec in!! Max-Min= 280%
7095 10:00:50.961417
7096 10:00:50.964653 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7097 10:00:50.968004 [DutyScan_Calibration_Flow] ====Done====
7098 10:00:50.968085
7099 10:00:50.971075 [DutyScan_Calibration_Flow] k_type=3
7100 10:00:50.987324
7101 10:00:50.987412 ==DQM 0 ==
7102 10:00:50.990849 Final DQM duty delay cell = -4
7103 10:00:50.993958 [-4] MAX Duty = 5093%(X100), DQS PI = 34
7104 10:00:50.997048 [-4] MIN Duty = 4813%(X100), DQS PI = 42
7105 10:00:51.000455 [-4] AVG Duty = 4953%(X100)
7106 10:00:51.000543
7107 10:00:51.000607 ==DQM 1 ==
7108 10:00:51.003694 Final DQM duty delay cell = -4
7109 10:00:51.007156 [-4] MAX Duty = 5062%(X100), DQS PI = 14
7110 10:00:51.010397 [-4] MIN Duty = 4907%(X100), DQS PI = 38
7111 10:00:51.013852 [-4] AVG Duty = 4984%(X100)
7112 10:00:51.013934
7113 10:00:51.016975 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7114 10:00:51.017057
7115 10:00:51.020313 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7116 10:00:51.023594 [DutyScan_Calibration_Flow] ====Done====
7117 10:00:51.023676
7118 10:00:51.026958 [DutyScan_Calibration_Flow] k_type=2
7119 10:00:51.045071
7120 10:00:51.045177 ==DQ 0 ==
7121 10:00:51.048241 Final DQ duty delay cell = 0
7122 10:00:51.051460 [0] MAX Duty = 5093%(X100), DQS PI = 18
7123 10:00:51.054699 [0] MIN Duty = 4938%(X100), DQS PI = 48
7124 10:00:51.054782 [0] AVG Duty = 5015%(X100)
7125 10:00:51.058085
7126 10:00:51.058166 ==DQ 1 ==
7127 10:00:51.061384 Final DQ duty delay cell = 0
7128 10:00:51.064748 [0] MAX Duty = 5031%(X100), DQS PI = 4
7129 10:00:51.067930 [0] MIN Duty = 4875%(X100), DQS PI = 28
7130 10:00:51.068012 [0] AVG Duty = 4953%(X100)
7131 10:00:51.068076
7132 10:00:51.071213 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7133 10:00:51.074565
7134 10:00:51.077948 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7135 10:00:51.081242 [DutyScan_Calibration_Flow] ====Done====
7136 10:00:51.084757 nWR fixed to 30
7137 10:00:51.084839 [ModeRegInit_LP4] CH0 RK0
7138 10:00:51.087738 [ModeRegInit_LP4] CH0 RK1
7139 10:00:51.091027 [ModeRegInit_LP4] CH1 RK0
7140 10:00:51.094190 [ModeRegInit_LP4] CH1 RK1
7141 10:00:51.094271 match AC timing 4
7142 10:00:51.100907 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7143 10:00:51.104102 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7144 10:00:51.107523 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7145 10:00:51.114006 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7146 10:00:51.117694 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7147 10:00:51.117776 [MiockJmeterHQA]
7148 10:00:51.117839
7149 10:00:51.120700 [DramcMiockJmeter] u1RxGatingPI = 0
7150 10:00:51.124298 0 : 4363, 4138
7151 10:00:51.124407 4 : 4253, 4027
7152 10:00:51.127179 8 : 4253, 4027
7153 10:00:51.127262 12 : 4253, 4026
7154 10:00:51.131035 16 : 4252, 4026
7155 10:00:51.131118 20 : 4363, 4137
7156 10:00:51.131183 24 : 4253, 4026
7157 10:00:51.134030 28 : 4363, 4138
7158 10:00:51.134113 32 : 4252, 4027
7159 10:00:51.137201 36 : 4252, 4027
7160 10:00:51.137318 40 : 4253, 4027
7161 10:00:51.140495 44 : 4253, 4026
7162 10:00:51.140617 48 : 4363, 4138
7163 10:00:51.143678 52 : 4250, 4027
7164 10:00:51.143760 56 : 4361, 4137
7165 10:00:51.143826 60 : 4250, 4026
7166 10:00:51.146987 64 : 4250, 4026
7167 10:00:51.147070 68 : 4250, 4027
7168 10:00:51.150525 72 : 4361, 4137
7169 10:00:51.150608 76 : 4250, 4026
7170 10:00:51.153613 80 : 4360, 4138
7171 10:00:51.153695 84 : 4250, 4027
7172 10:00:51.157011 88 : 4250, 4027
7173 10:00:51.157095 92 : 4250, 4027
7174 10:00:51.157160 96 : 4250, 4026
7175 10:00:51.160201 100 : 4360, 2709
7176 10:00:51.160283 104 : 4250, 0
7177 10:00:51.163635 108 : 4250, 0
7178 10:00:51.163717 112 : 4250, 0
7179 10:00:51.163782 116 : 4250, 0
7180 10:00:51.167001 120 : 4360, 0
7181 10:00:51.167083 124 : 4250, 0
7182 10:00:51.170323 128 : 4361, 0
7183 10:00:51.170405 132 : 4361, 0
7184 10:00:51.170469 136 : 4363, 0
7185 10:00:51.173555 140 : 4250, 0
7186 10:00:51.173637 144 : 4250, 0
7187 10:00:51.176794 148 : 4250, 0
7188 10:00:51.176877 152 : 4250, 0
7189 10:00:51.176942 156 : 4250, 0
7190 10:00:51.180021 160 : 4250, 0
7191 10:00:51.180103 164 : 4252, 0
7192 10:00:51.183399 168 : 4252, 0
7193 10:00:51.183481 172 : 4250, 0
7194 10:00:51.183546 176 : 4250, 0
7195 10:00:51.186701 180 : 4361, 0
7196 10:00:51.186783 184 : 4361, 0
7197 10:00:51.186849 188 : 4363, 0
7198 10:00:51.190150 192 : 4250, 0
7199 10:00:51.190232 196 : 4250, 0
7200 10:00:51.193509 200 : 4250, 0
7201 10:00:51.193591 204 : 4250, 0
7202 10:00:51.193656 208 : 4252, 0
7203 10:00:51.197128 212 : 4250, 0
7204 10:00:51.197211 216 : 4252, 0
7205 10:00:51.200143 220 : 4361, 634
7206 10:00:51.200225 224 : 4250, 4012
7207 10:00:51.203499 228 : 4250, 4026
7208 10:00:51.203581 232 : 4250, 4027
7209 10:00:51.203647 236 : 4360, 4138
7210 10:00:51.206795 240 : 4250, 4026
7211 10:00:51.206877 244 : 4250, 4027
7212 10:00:51.210037 248 : 4360, 4138
7213 10:00:51.210119 252 : 4361, 4137
7214 10:00:51.213232 256 : 4248, 4024
7215 10:00:51.213315 260 : 4361, 4137
7216 10:00:51.216747 264 : 4360, 4138
7217 10:00:51.216830 268 : 4250, 4026
7218 10:00:51.219964 272 : 4250, 4027
7219 10:00:51.220046 276 : 4250, 4026
7220 10:00:51.223444 280 : 4250, 4027
7221 10:00:51.223532 284 : 4250, 4027
7222 10:00:51.226894 288 : 4250, 4027
7223 10:00:51.226977 292 : 4250, 4026
7224 10:00:51.229885 296 : 4250, 4027
7225 10:00:51.229968 300 : 4360, 4138
7226 10:00:51.230033 304 : 4361, 4137
7227 10:00:51.233078 308 : 4248, 4024
7228 10:00:51.233160 312 : 4361, 4137
7229 10:00:51.236624 316 : 4360, 4138
7230 10:00:51.236706 320 : 4250, 4026
7231 10:00:51.239742 324 : 4250, 4027
7232 10:00:51.239825 328 : 4250, 4026
7233 10:00:51.243267 332 : 4250, 4027
7234 10:00:51.243349 336 : 4250, 3934
7235 10:00:51.246415 340 : 4250, 1829
7236 10:00:51.246498
7237 10:00:51.246562 MIOCK jitter meter ch=0
7238 10:00:51.246622
7239 10:00:51.249581 1T = (340-104) = 236 dly cells
7240 10:00:51.256432 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7241 10:00:51.256544 ==
7242 10:00:51.259623 Dram Type= 6, Freq= 0, CH_0, rank 0
7243 10:00:51.262860 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7244 10:00:51.262943 ==
7245 10:00:51.269391 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7246 10:00:51.272616 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7247 10:00:51.279472 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7248 10:00:51.282755 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7249 10:00:51.292123 [CA 0] Center 42 (12~72) winsize 61
7250 10:00:51.295424 [CA 1] Center 41 (11~72) winsize 62
7251 10:00:51.298698 [CA 2] Center 37 (7~67) winsize 61
7252 10:00:51.302185 [CA 3] Center 37 (7~67) winsize 61
7253 10:00:51.305992 [CA 4] Center 35 (5~66) winsize 62
7254 10:00:51.308808 [CA 5] Center 35 (5~65) winsize 61
7255 10:00:51.308891
7256 10:00:51.312058 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7257 10:00:51.312139
7258 10:00:51.315572 [CATrainingPosCal] consider 1 rank data
7259 10:00:51.318695 u2DelayCellTimex100 = 275/100 ps
7260 10:00:51.321954 CA0 delay=42 (12~72),Diff = 7 PI (24 cell)
7261 10:00:51.328463 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7262 10:00:51.331859 CA2 delay=37 (7~67),Diff = 2 PI (7 cell)
7263 10:00:51.335296 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7264 10:00:51.338666 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7265 10:00:51.341965 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7266 10:00:51.342048
7267 10:00:51.345091 CA PerBit enable=1, Macro0, CA PI delay=35
7268 10:00:51.345173
7269 10:00:51.348474 [CBTSetCACLKResult] CA Dly = 35
7270 10:00:51.351707 CS Dly: 11 (0~42)
7271 10:00:51.355060 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7272 10:00:51.358252 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7273 10:00:51.358333 ==
7274 10:00:51.361724 Dram Type= 6, Freq= 0, CH_0, rank 1
7275 10:00:51.364990 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7276 10:00:51.368172 ==
7277 10:00:51.371535 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7278 10:00:51.374942 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7279 10:00:51.381488 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7280 10:00:51.387990 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7281 10:00:51.394891 [CA 0] Center 42 (12~73) winsize 62
7282 10:00:51.398095 [CA 1] Center 42 (12~73) winsize 62
7283 10:00:51.401441 [CA 2] Center 38 (9~68) winsize 60
7284 10:00:51.404720 [CA 3] Center 38 (8~68) winsize 61
7285 10:00:51.408122 [CA 4] Center 36 (6~66) winsize 61
7286 10:00:51.411404 [CA 5] Center 36 (6~66) winsize 61
7287 10:00:51.411487
7288 10:00:51.414579 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7289 10:00:51.414661
7290 10:00:51.417928 [CATrainingPosCal] consider 2 rank data
7291 10:00:51.421139 u2DelayCellTimex100 = 275/100 ps
7292 10:00:51.424644 CA0 delay=42 (12~72),Diff = 7 PI (24 cell)
7293 10:00:51.431065 CA1 delay=42 (12~72),Diff = 7 PI (24 cell)
7294 10:00:51.434385 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7295 10:00:51.437958 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7296 10:00:51.441414 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7297 10:00:51.444490 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7298 10:00:51.444607
7299 10:00:51.447955 CA PerBit enable=1, Macro0, CA PI delay=35
7300 10:00:51.448038
7301 10:00:51.451111 [CBTSetCACLKResult] CA Dly = 35
7302 10:00:51.454387 CS Dly: 11 (0~42)
7303 10:00:51.457788 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7304 10:00:51.461002 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7305 10:00:51.461084
7306 10:00:51.464162 ----->DramcWriteLeveling(PI) begin...
7307 10:00:51.464244 ==
7308 10:00:51.467670 Dram Type= 6, Freq= 0, CH_0, rank 0
7309 10:00:51.474440 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7310 10:00:51.474522 ==
7311 10:00:51.477354 Write leveling (Byte 0): 27 => 27
7312 10:00:51.477435 Write leveling (Byte 1): 27 => 27
7313 10:00:51.480831 DramcWriteLeveling(PI) end<-----
7314 10:00:51.480911
7315 10:00:51.484160 ==
7316 10:00:51.484241 Dram Type= 6, Freq= 0, CH_0, rank 0
7317 10:00:51.490536 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7318 10:00:51.490617 ==
7319 10:00:51.493801 [Gating] SW mode calibration
7320 10:00:51.500466 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7321 10:00:51.503870 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7322 10:00:51.510423 0 12 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7323 10:00:51.513916 0 12 4 | B1->B0 | 2525 3434 | 0 0 | (1 1) (0 0)
7324 10:00:51.517156 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7325 10:00:51.523741 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7326 10:00:51.527296 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7327 10:00:51.530591 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7328 10:00:51.536925 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7329 10:00:51.540252 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7330 10:00:51.543601 0 13 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7331 10:00:51.550258 0 13 4 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
7332 10:00:51.553669 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7333 10:00:51.556766 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7334 10:00:51.563371 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7335 10:00:51.566734 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7336 10:00:51.570226 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7337 10:00:51.576613 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7338 10:00:51.579850 0 14 0 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
7339 10:00:51.583277 0 14 4 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
7340 10:00:51.589794 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7341 10:00:51.593106 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7342 10:00:51.596442 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7343 10:00:51.603087 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7344 10:00:51.606665 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7345 10:00:51.609685 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7346 10:00:51.616175 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7347 10:00:51.619642 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7348 10:00:51.623193 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7349 10:00:51.630051 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7350 10:00:51.632817 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7351 10:00:51.636113 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7352 10:00:51.642692 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7353 10:00:51.646046 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7354 10:00:51.649335 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7355 10:00:51.655849 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7356 10:00:51.659339 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7357 10:00:51.662568 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7358 10:00:51.669099 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7359 10:00:51.672428 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7360 10:00:51.675967 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7361 10:00:51.682405 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7362 10:00:51.685886 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7363 10:00:51.688995 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7364 10:00:51.695514 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7365 10:00:51.695604 Total UI for P1: 0, mck2ui 16
7366 10:00:51.698935 best dqsien dly found for B0: ( 1, 1, 0)
7367 10:00:51.702164 Total UI for P1: 0, mck2ui 16
7368 10:00:51.705600 best dqsien dly found for B1: ( 1, 1, 4)
7369 10:00:51.708942 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7370 10:00:51.715857 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7371 10:00:51.715943
7372 10:00:51.718665 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7373 10:00:51.722122 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7374 10:00:51.725410 [Gating] SW calibration Done
7375 10:00:51.725495 ==
7376 10:00:51.728777 Dram Type= 6, Freq= 0, CH_0, rank 0
7377 10:00:51.732071 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7378 10:00:51.732153 ==
7379 10:00:51.732218 RX Vref Scan: 0
7380 10:00:51.732278
7381 10:00:51.735335 RX Vref 0 -> 0, step: 1
7382 10:00:51.735417
7383 10:00:51.738735 RX Delay 0 -> 252, step: 8
7384 10:00:51.742025 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7385 10:00:51.745239 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7386 10:00:51.751828 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7387 10:00:51.754948 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7388 10:00:51.758504 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7389 10:00:51.761607 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
7390 10:00:51.765133 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7391 10:00:51.771610 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7392 10:00:51.775293 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7393 10:00:51.778304 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7394 10:00:51.781754 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7395 10:00:51.784843 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7396 10:00:51.791618 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7397 10:00:51.795169 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7398 10:00:51.798218 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7399 10:00:51.801630 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7400 10:00:51.801712 ==
7401 10:00:51.804884 Dram Type= 6, Freq= 0, CH_0, rank 0
7402 10:00:51.811519 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7403 10:00:51.811601 ==
7404 10:00:51.811665 DQS Delay:
7405 10:00:51.811729 DQS0 = 0, DQS1 = 0
7406 10:00:51.814893 DQM Delay:
7407 10:00:51.815001 DQM0 = 130, DQM1 = 123
7408 10:00:51.818011 DQ Delay:
7409 10:00:51.821511 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7410 10:00:51.825057 DQ4 =135, DQ5 =115, DQ6 =139, DQ7 =139
7411 10:00:51.828424 DQ8 =111, DQ9 =107, DQ10 =119, DQ11 =115
7412 10:00:51.831338 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =131
7413 10:00:51.831418
7414 10:00:51.831480
7415 10:00:51.831538 ==
7416 10:00:51.834636 Dram Type= 6, Freq= 0, CH_0, rank 0
7417 10:00:51.837904 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7418 10:00:51.841387 ==
7419 10:00:51.841468
7420 10:00:51.841532
7421 10:00:51.841591 TX Vref Scan disable
7422 10:00:51.844432 == TX Byte 0 ==
7423 10:00:51.847910 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7424 10:00:51.851196 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7425 10:00:51.854741 == TX Byte 1 ==
7426 10:00:51.858079 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7427 10:00:51.861369 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7428 10:00:51.864722 ==
7429 10:00:51.864802 Dram Type= 6, Freq= 0, CH_0, rank 0
7430 10:00:51.871154 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7431 10:00:51.871235 ==
7432 10:00:51.882914
7433 10:00:51.886121 TX Vref early break, caculate TX vref
7434 10:00:51.889630 TX Vref=16, minBit 8, minWin=22, winSum=375
7435 10:00:51.892878 TX Vref=18, minBit 4, minWin=23, winSum=382
7436 10:00:51.896142 TX Vref=20, minBit 8, minWin=22, winSum=396
7437 10:00:51.899555 TX Vref=22, minBit 9, minWin=23, winSum=397
7438 10:00:51.903022 TX Vref=24, minBit 8, minWin=24, winSum=411
7439 10:00:51.909365 TX Vref=26, minBit 9, minWin=25, winSum=420
7440 10:00:51.912717 TX Vref=28, minBit 8, minWin=25, winSum=420
7441 10:00:51.916051 TX Vref=30, minBit 1, minWin=24, winSum=413
7442 10:00:51.919526 TX Vref=32, minBit 6, minWin=24, winSum=404
7443 10:00:51.922866 TX Vref=34, minBit 8, minWin=23, winSum=395
7444 10:00:51.929551 [TxChooseVref] Worse bit 9, Min win 25, Win sum 420, Final Vref 26
7445 10:00:51.929639
7446 10:00:51.932756 Final TX Range 0 Vref 26
7447 10:00:51.932836
7448 10:00:51.932899 ==
7449 10:00:51.935990 Dram Type= 6, Freq= 0, CH_0, rank 0
7450 10:00:51.939285 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7451 10:00:51.939366 ==
7452 10:00:51.939429
7453 10:00:51.939488
7454 10:00:51.942772 TX Vref Scan disable
7455 10:00:51.949302 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7456 10:00:51.949384 == TX Byte 0 ==
7457 10:00:51.952614 u2DelayCellOfst[0]=10 cells (3 PI)
7458 10:00:51.956074 u2DelayCellOfst[1]=17 cells (5 PI)
7459 10:00:51.959136 u2DelayCellOfst[2]=10 cells (3 PI)
7460 10:00:51.962608 u2DelayCellOfst[3]=10 cells (3 PI)
7461 10:00:51.965878 u2DelayCellOfst[4]=7 cells (2 PI)
7462 10:00:51.969211 u2DelayCellOfst[5]=0 cells (0 PI)
7463 10:00:51.972475 u2DelayCellOfst[6]=17 cells (5 PI)
7464 10:00:51.972574 u2DelayCellOfst[7]=17 cells (5 PI)
7465 10:00:51.978914 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7466 10:00:51.982442 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7467 10:00:51.985740 == TX Byte 1 ==
7468 10:00:51.985819 u2DelayCellOfst[8]=0 cells (0 PI)
7469 10:00:51.988958 u2DelayCellOfst[9]=0 cells (0 PI)
7470 10:00:51.992313 u2DelayCellOfst[10]=7 cells (2 PI)
7471 10:00:51.995674 u2DelayCellOfst[11]=3 cells (1 PI)
7472 10:00:51.998838 u2DelayCellOfst[12]=14 cells (4 PI)
7473 10:00:52.002231 u2DelayCellOfst[13]=10 cells (3 PI)
7474 10:00:52.005543 u2DelayCellOfst[14]=17 cells (5 PI)
7475 10:00:52.008947 u2DelayCellOfst[15]=14 cells (4 PI)
7476 10:00:52.012365 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7477 10:00:52.018910 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7478 10:00:52.018993 DramC Write-DBI on
7479 10:00:52.019057 ==
7480 10:00:52.022051 Dram Type= 6, Freq= 0, CH_0, rank 0
7481 10:00:52.025437 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7482 10:00:52.028760 ==
7483 10:00:52.028840
7484 10:00:52.028902
7485 10:00:52.028961 TX Vref Scan disable
7486 10:00:52.032065 == TX Byte 0 ==
7487 10:00:52.035400 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7488 10:00:52.038593 == TX Byte 1 ==
7489 10:00:52.041902 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7490 10:00:52.045352 DramC Write-DBI off
7491 10:00:52.045432
7492 10:00:52.045495 [DATLAT]
7493 10:00:52.045554 Freq=1600, CH0 RK0
7494 10:00:52.045611
7495 10:00:52.048664 DATLAT Default: 0xf
7496 10:00:52.051909 0, 0xFFFF, sum = 0
7497 10:00:52.051991 1, 0xFFFF, sum = 0
7498 10:00:52.055481 2, 0xFFFF, sum = 0
7499 10:00:52.055562 3, 0xFFFF, sum = 0
7500 10:00:52.058555 4, 0xFFFF, sum = 0
7501 10:00:52.058637 5, 0xFFFF, sum = 0
7502 10:00:52.061768 6, 0xFFFF, sum = 0
7503 10:00:52.061851 7, 0xFFFF, sum = 0
7504 10:00:52.065099 8, 0xFFFF, sum = 0
7505 10:00:52.065181 9, 0xFFFF, sum = 0
7506 10:00:52.068608 10, 0xFFFF, sum = 0
7507 10:00:52.068690 11, 0xFFFF, sum = 0
7508 10:00:52.071984 12, 0xBFF, sum = 0
7509 10:00:52.072066 13, 0x0, sum = 1
7510 10:00:52.075122 14, 0x0, sum = 2
7511 10:00:52.075203 15, 0x0, sum = 3
7512 10:00:52.078761 16, 0x0, sum = 4
7513 10:00:52.079090 best_step = 14
7514 10:00:52.079344
7515 10:00:52.079579 ==
7516 10:00:52.082121 Dram Type= 6, Freq= 0, CH_0, rank 0
7517 10:00:52.085437 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7518 10:00:52.088425 ==
7519 10:00:52.088652 RX Vref Scan: 1
7520 10:00:52.088802
7521 10:00:52.091722 Set Vref Range= 24 -> 127
7522 10:00:52.091907
7523 10:00:52.095014 RX Vref 24 -> 127, step: 1
7524 10:00:52.095168
7525 10:00:52.095291 RX Delay 11 -> 252, step: 4
7526 10:00:52.095404
7527 10:00:52.098465 Set Vref, RX VrefLevel [Byte0]: 24
7528 10:00:52.101655 [Byte1]: 24
7529 10:00:52.105567
7530 10:00:52.105682 Set Vref, RX VrefLevel [Byte0]: 25
7531 10:00:52.108715 [Byte1]: 25
7532 10:00:52.113275
7533 10:00:52.113367 Set Vref, RX VrefLevel [Byte0]: 26
7534 10:00:52.116277 [Byte1]: 26
7535 10:00:52.120674
7536 10:00:52.120757 Set Vref, RX VrefLevel [Byte0]: 27
7537 10:00:52.123978 [Byte1]: 27
7538 10:00:52.128160
7539 10:00:52.128240 Set Vref, RX VrefLevel [Byte0]: 28
7540 10:00:52.131611 [Byte1]: 28
7541 10:00:52.135819
7542 10:00:52.135898 Set Vref, RX VrefLevel [Byte0]: 29
7543 10:00:52.139123 [Byte1]: 29
7544 10:00:52.143680
7545 10:00:52.143760 Set Vref, RX VrefLevel [Byte0]: 30
7546 10:00:52.146972 [Byte1]: 30
7547 10:00:52.150850
7548 10:00:52.154557 Set Vref, RX VrefLevel [Byte0]: 31
7549 10:00:52.157639 [Byte1]: 31
7550 10:00:52.157744
7551 10:00:52.160880 Set Vref, RX VrefLevel [Byte0]: 32
7552 10:00:52.164013 [Byte1]: 32
7553 10:00:52.164093
7554 10:00:52.167387 Set Vref, RX VrefLevel [Byte0]: 33
7555 10:00:52.171005 [Byte1]: 33
7556 10:00:52.174144
7557 10:00:52.174223 Set Vref, RX VrefLevel [Byte0]: 34
7558 10:00:52.177264 [Byte1]: 34
7559 10:00:52.181514
7560 10:00:52.181593 Set Vref, RX VrefLevel [Byte0]: 35
7561 10:00:52.184785 [Byte1]: 35
7562 10:00:52.189033
7563 10:00:52.189113 Set Vref, RX VrefLevel [Byte0]: 36
7564 10:00:52.192458 [Byte1]: 36
7565 10:00:52.196551
7566 10:00:52.196644 Set Vref, RX VrefLevel [Byte0]: 37
7567 10:00:52.200039 [Byte1]: 37
7568 10:00:52.204243
7569 10:00:52.204322 Set Vref, RX VrefLevel [Byte0]: 38
7570 10:00:52.207654 [Byte1]: 38
7571 10:00:52.212129
7572 10:00:52.212209 Set Vref, RX VrefLevel [Byte0]: 39
7573 10:00:52.215167 [Byte1]: 39
7574 10:00:52.219515
7575 10:00:52.219595 Set Vref, RX VrefLevel [Byte0]: 40
7576 10:00:52.222891 [Byte1]: 40
7577 10:00:52.227351
7578 10:00:52.227432 Set Vref, RX VrefLevel [Byte0]: 41
7579 10:00:52.230622 [Byte1]: 41
7580 10:00:52.234944
7581 10:00:52.235050 Set Vref, RX VrefLevel [Byte0]: 42
7582 10:00:52.238071 [Byte1]: 42
7583 10:00:52.242365
7584 10:00:52.242446 Set Vref, RX VrefLevel [Byte0]: 43
7585 10:00:52.245649 [Byte1]: 43
7586 10:00:52.250368
7587 10:00:52.250449 Set Vref, RX VrefLevel [Byte0]: 44
7588 10:00:52.253498 [Byte1]: 44
7589 10:00:52.257559
7590 10:00:52.257639 Set Vref, RX VrefLevel [Byte0]: 45
7591 10:00:52.260974 [Byte1]: 45
7592 10:00:52.265479
7593 10:00:52.265559 Set Vref, RX VrefLevel [Byte0]: 46
7594 10:00:52.268511 [Byte1]: 46
7595 10:00:52.272777
7596 10:00:52.272857 Set Vref, RX VrefLevel [Byte0]: 47
7597 10:00:52.276057 [Byte1]: 47
7598 10:00:52.280444
7599 10:00:52.280550 Set Vref, RX VrefLevel [Byte0]: 48
7600 10:00:52.283728 [Byte1]: 48
7601 10:00:52.288166
7602 10:00:52.288247 Set Vref, RX VrefLevel [Byte0]: 49
7603 10:00:52.291348 [Byte1]: 49
7604 10:00:52.295692
7605 10:00:52.295797 Set Vref, RX VrefLevel [Byte0]: 50
7606 10:00:52.299060 [Byte1]: 50
7607 10:00:52.303246
7608 10:00:52.303325 Set Vref, RX VrefLevel [Byte0]: 51
7609 10:00:52.306483 [Byte1]: 51
7610 10:00:52.310883
7611 10:00:52.310962 Set Vref, RX VrefLevel [Byte0]: 52
7612 10:00:52.314182 [Byte1]: 52
7613 10:00:52.318493
7614 10:00:52.318574 Set Vref, RX VrefLevel [Byte0]: 53
7615 10:00:52.321797 [Byte1]: 53
7616 10:00:52.326140
7617 10:00:52.326221 Set Vref, RX VrefLevel [Byte0]: 54
7618 10:00:52.329554 [Byte1]: 54
7619 10:00:52.333875
7620 10:00:52.333955 Set Vref, RX VrefLevel [Byte0]: 55
7621 10:00:52.336938 [Byte1]: 55
7622 10:00:52.341296
7623 10:00:52.341376 Set Vref, RX VrefLevel [Byte0]: 56
7624 10:00:52.344714 [Byte1]: 56
7625 10:00:52.349579
7626 10:00:52.349659 Set Vref, RX VrefLevel [Byte0]: 57
7627 10:00:52.352333 [Byte1]: 57
7628 10:00:52.356681
7629 10:00:52.356761 Set Vref, RX VrefLevel [Byte0]: 58
7630 10:00:52.360276 [Byte1]: 58
7631 10:00:52.364214
7632 10:00:52.364294 Set Vref, RX VrefLevel [Byte0]: 59
7633 10:00:52.367412 [Byte1]: 59
7634 10:00:52.372143
7635 10:00:52.372223 Set Vref, RX VrefLevel [Byte0]: 60
7636 10:00:52.375094 [Byte1]: 60
7637 10:00:52.379525
7638 10:00:52.379605 Set Vref, RX VrefLevel [Byte0]: 61
7639 10:00:52.382749 [Byte1]: 61
7640 10:00:52.386930
7641 10:00:52.387010 Set Vref, RX VrefLevel [Byte0]: 62
7642 10:00:52.390276 [Byte1]: 62
7643 10:00:52.394662
7644 10:00:52.394743 Set Vref, RX VrefLevel [Byte0]: 63
7645 10:00:52.398144 [Byte1]: 63
7646 10:00:52.402305
7647 10:00:52.402385 Set Vref, RX VrefLevel [Byte0]: 64
7648 10:00:52.405616 [Byte1]: 64
7649 10:00:52.409897
7650 10:00:52.410004 Set Vref, RX VrefLevel [Byte0]: 65
7651 10:00:52.413158 [Byte1]: 65
7652 10:00:52.417519
7653 10:00:52.417599 Set Vref, RX VrefLevel [Byte0]: 66
7654 10:00:52.420828 [Byte1]: 66
7655 10:00:52.425040
7656 10:00:52.425148 Set Vref, RX VrefLevel [Byte0]: 67
7657 10:00:52.428403 [Byte1]: 67
7658 10:00:52.432853
7659 10:00:52.432958 Set Vref, RX VrefLevel [Byte0]: 68
7660 10:00:52.435941 [Byte1]: 68
7661 10:00:52.440428
7662 10:00:52.440570 Set Vref, RX VrefLevel [Byte0]: 69
7663 10:00:52.443426 [Byte1]: 69
7664 10:00:52.448204
7665 10:00:52.448309 Set Vref, RX VrefLevel [Byte0]: 70
7666 10:00:52.451407 [Byte1]: 70
7667 10:00:52.455558
7668 10:00:52.455639 Set Vref, RX VrefLevel [Byte0]: 71
7669 10:00:52.458796 [Byte1]: 71
7670 10:00:52.463339
7671 10:00:52.463418 Final RX Vref Byte 0 = 55 to rank0
7672 10:00:52.466604 Final RX Vref Byte 1 = 54 to rank0
7673 10:00:52.469673 Final RX Vref Byte 0 = 55 to rank1
7674 10:00:52.473125 Final RX Vref Byte 1 = 54 to rank1==
7675 10:00:52.476735 Dram Type= 6, Freq= 0, CH_0, rank 0
7676 10:00:52.483057 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7677 10:00:52.483139 ==
7678 10:00:52.483203 DQS Delay:
7679 10:00:52.483261 DQS0 = 0, DQS1 = 0
7680 10:00:52.486289 DQM Delay:
7681 10:00:52.486368 DQM0 = 126, DQM1 = 120
7682 10:00:52.489835 DQ Delay:
7683 10:00:52.492889 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7684 10:00:52.496382 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7685 10:00:52.499550 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
7686 10:00:52.502843 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =132
7687 10:00:52.502923
7688 10:00:52.502985
7689 10:00:52.503043
7690 10:00:52.506365 [DramC_TX_OE_Calibration] TA2
7691 10:00:52.509483 Original DQ_B0 (3 6) =30, OEN = 27
7692 10:00:52.512828 Original DQ_B1 (3 6) =30, OEN = 27
7693 10:00:52.515919 24, 0x0, End_B0=24 End_B1=24
7694 10:00:52.516027 25, 0x0, End_B0=25 End_B1=25
7695 10:00:52.519359 26, 0x0, End_B0=26 End_B1=26
7696 10:00:52.522626 27, 0x0, End_B0=27 End_B1=27
7697 10:00:52.525919 28, 0x0, End_B0=28 End_B1=28
7698 10:00:52.529257 29, 0x0, End_B0=29 End_B1=29
7699 10:00:52.529338 30, 0x0, End_B0=30 End_B1=30
7700 10:00:52.532717 31, 0x4141, End_B0=30 End_B1=30
7701 10:00:52.535892 Byte0 end_step=30 best_step=27
7702 10:00:52.539272 Byte1 end_step=30 best_step=27
7703 10:00:52.542835 Byte0 TX OE(2T, 0.5T) = (3, 3)
7704 10:00:52.545924 Byte1 TX OE(2T, 0.5T) = (3, 3)
7705 10:00:52.546004
7706 10:00:52.546068
7707 10:00:52.552564 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
7708 10:00:52.555800 CH0 RK0: MR19=303, MR18=1D1D
7709 10:00:52.562443 CH0_RK0: MR19=0x303, MR18=0x1D1D, DQSOSC=395, MR23=63, INC=23, DEC=15
7710 10:00:52.562524
7711 10:00:52.565721 ----->DramcWriteLeveling(PI) begin...
7712 10:00:52.565802 ==
7713 10:00:52.569188 Dram Type= 6, Freq= 0, CH_0, rank 1
7714 10:00:52.572279 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7715 10:00:52.572360 ==
7716 10:00:52.575788 Write leveling (Byte 0): 29 => 29
7717 10:00:52.578951 Write leveling (Byte 1): 25 => 25
7718 10:00:52.582347 DramcWriteLeveling(PI) end<-----
7719 10:00:52.582426
7720 10:00:52.582490 ==
7721 10:00:52.585715 Dram Type= 6, Freq= 0, CH_0, rank 1
7722 10:00:52.588801 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7723 10:00:52.588881 ==
7724 10:00:52.592330 [Gating] SW mode calibration
7725 10:00:52.599058 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7726 10:00:52.605539 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7727 10:00:52.608721 0 12 0 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
7728 10:00:52.615397 0 12 4 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
7729 10:00:52.618811 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7730 10:00:52.621991 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7731 10:00:52.628486 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7732 10:00:52.631893 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7733 10:00:52.635487 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7734 10:00:52.641899 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7735 10:00:52.645219 0 13 0 | B1->B0 | 3434 2828 | 1 1 | (1 0) (1 0)
7736 10:00:52.648669 0 13 4 | B1->B0 | 3232 2323 | 0 0 | (1 0) (0 0)
7737 10:00:52.655002 0 13 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
7738 10:00:52.658413 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7739 10:00:52.661820 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7740 10:00:52.668314 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7741 10:00:52.671488 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7742 10:00:52.674747 0 13 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7743 10:00:52.681290 0 14 0 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
7744 10:00:52.684728 0 14 4 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
7745 10:00:52.687965 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7746 10:00:52.694709 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7747 10:00:52.697919 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7748 10:00:52.701319 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7749 10:00:52.708337 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7750 10:00:52.711234 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7751 10:00:52.714465 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7752 10:00:52.720966 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7753 10:00:52.724436 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7754 10:00:52.727844 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7755 10:00:52.734302 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7756 10:00:52.737503 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7757 10:00:52.741188 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7758 10:00:52.744178 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7759 10:00:52.750832 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7760 10:00:52.754108 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7761 10:00:52.757466 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7762 10:00:52.764284 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7763 10:00:52.767493 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7764 10:00:52.770714 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7765 10:00:52.777585 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7766 10:00:52.780824 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7767 10:00:52.784118 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7768 10:00:52.790733 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7769 10:00:52.793933 Total UI for P1: 0, mck2ui 16
7770 10:00:52.797148 best dqsien dly found for B0: ( 1, 0, 30)
7771 10:00:52.800455 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7772 10:00:52.803879 Total UI for P1: 0, mck2ui 16
7773 10:00:52.807467 best dqsien dly found for B1: ( 1, 1, 2)
7774 10:00:52.810495 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7775 10:00:52.813888 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7776 10:00:52.813999
7777 10:00:52.817046 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7778 10:00:52.820490 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7779 10:00:52.823733 [Gating] SW calibration Done
7780 10:00:52.823846 ==
7781 10:00:52.826966 Dram Type= 6, Freq= 0, CH_0, rank 1
7782 10:00:52.830362 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7783 10:00:52.833795 ==
7784 10:00:52.833907 RX Vref Scan: 0
7785 10:00:52.834009
7786 10:00:52.836971 RX Vref 0 -> 0, step: 1
7787 10:00:52.837090
7788 10:00:52.840351 RX Delay 0 -> 252, step: 8
7789 10:00:52.843665 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7790 10:00:52.847089 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7791 10:00:52.850289 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7792 10:00:52.853883 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7793 10:00:52.860055 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7794 10:00:52.863389 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7795 10:00:52.866692 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7796 10:00:52.870172 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7797 10:00:52.873480 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7798 10:00:52.879987 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7799 10:00:52.883435 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7800 10:00:52.886641 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7801 10:00:52.890075 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7802 10:00:52.893277 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7803 10:00:52.900127 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
7804 10:00:52.903262 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7805 10:00:52.903373 ==
7806 10:00:52.906404 Dram Type= 6, Freq= 0, CH_0, rank 1
7807 10:00:52.909706 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7808 10:00:52.909819 ==
7809 10:00:52.912991 DQS Delay:
7810 10:00:52.913102 DQS0 = 0, DQS1 = 0
7811 10:00:52.913201 DQM Delay:
7812 10:00:52.916274 DQM0 = 130, DQM1 = 123
7813 10:00:52.916395 DQ Delay:
7814 10:00:52.919662 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =123
7815 10:00:52.922892 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7816 10:00:52.929464 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7817 10:00:52.932972 DQ12 =131, DQ13 =131, DQ14 =131, DQ15 =131
7818 10:00:52.933091
7819 10:00:52.933199
7820 10:00:52.933303 ==
7821 10:00:52.936158 Dram Type= 6, Freq= 0, CH_0, rank 1
7822 10:00:52.939495 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7823 10:00:52.939611 ==
7824 10:00:52.939718
7825 10:00:52.939821
7826 10:00:52.942990 TX Vref Scan disable
7827 10:00:52.946255 == TX Byte 0 ==
7828 10:00:52.949582 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7829 10:00:52.952752 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7830 10:00:52.956224 == TX Byte 1 ==
7831 10:00:52.959589 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7832 10:00:52.962606 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7833 10:00:52.962722 ==
7834 10:00:52.965909 Dram Type= 6, Freq= 0, CH_0, rank 1
7835 10:00:52.969380 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7836 10:00:52.972390 ==
7837 10:00:52.983875
7838 10:00:52.987071 TX Vref early break, caculate TX vref
7839 10:00:52.990390 TX Vref=16, minBit 1, minWin=22, winSum=373
7840 10:00:52.993811 TX Vref=18, minBit 9, minWin=22, winSum=380
7841 10:00:52.997144 TX Vref=20, minBit 8, minWin=23, winSum=391
7842 10:00:53.000490 TX Vref=22, minBit 9, minWin=23, winSum=394
7843 10:00:53.004268 TX Vref=24, minBit 8, minWin=24, winSum=406
7844 10:00:53.010372 TX Vref=26, minBit 1, minWin=24, winSum=413
7845 10:00:53.013935 TX Vref=28, minBit 8, minWin=25, winSum=415
7846 10:00:53.017104 TX Vref=30, minBit 1, minWin=24, winSum=409
7847 10:00:53.020463 TX Vref=32, minBit 8, minWin=23, winSum=399
7848 10:00:53.023753 TX Vref=34, minBit 7, minWin=23, winSum=393
7849 10:00:53.030389 [TxChooseVref] Worse bit 8, Min win 25, Win sum 415, Final Vref 28
7850 10:00:53.030507
7851 10:00:53.033811 Final TX Range 0 Vref 28
7852 10:00:53.033927
7853 10:00:53.034033 ==
7854 10:00:53.037093 Dram Type= 6, Freq= 0, CH_0, rank 1
7855 10:00:53.040458 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7856 10:00:53.040615 ==
7857 10:00:53.040723
7858 10:00:53.040827
7859 10:00:53.043583 TX Vref Scan disable
7860 10:00:53.050560 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7861 10:00:53.050679 == TX Byte 0 ==
7862 10:00:53.053582 u2DelayCellOfst[0]=14 cells (4 PI)
7863 10:00:53.057187 u2DelayCellOfst[1]=17 cells (5 PI)
7864 10:00:53.060441 u2DelayCellOfst[2]=10 cells (3 PI)
7865 10:00:53.063614 u2DelayCellOfst[3]=14 cells (4 PI)
7866 10:00:53.066926 u2DelayCellOfst[4]=10 cells (3 PI)
7867 10:00:53.070264 u2DelayCellOfst[5]=0 cells (0 PI)
7868 10:00:53.073486 u2DelayCellOfst[6]=17 cells (5 PI)
7869 10:00:53.076769 u2DelayCellOfst[7]=17 cells (5 PI)
7870 10:00:53.080056 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7871 10:00:53.083678 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7872 10:00:53.086674 == TX Byte 1 ==
7873 10:00:53.086755 u2DelayCellOfst[8]=3 cells (1 PI)
7874 10:00:53.090019 u2DelayCellOfst[9]=0 cells (0 PI)
7875 10:00:53.093374 u2DelayCellOfst[10]=10 cells (3 PI)
7876 10:00:53.096833 u2DelayCellOfst[11]=7 cells (2 PI)
7877 10:00:53.100134 u2DelayCellOfst[12]=17 cells (5 PI)
7878 10:00:53.103405 u2DelayCellOfst[13]=17 cells (5 PI)
7879 10:00:53.106613 u2DelayCellOfst[14]=17 cells (5 PI)
7880 10:00:53.109798 u2DelayCellOfst[15]=14 cells (4 PI)
7881 10:00:53.113301 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
7882 10:00:53.119745 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7883 10:00:53.119827 DramC Write-DBI on
7884 10:00:53.119890 ==
7885 10:00:53.123308 Dram Type= 6, Freq= 0, CH_0, rank 1
7886 10:00:53.129724 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7887 10:00:53.129805 ==
7888 10:00:53.129869
7889 10:00:53.129928
7890 10:00:53.129985 TX Vref Scan disable
7891 10:00:53.133644 == TX Byte 0 ==
7892 10:00:53.136789 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7893 10:00:53.140260 == TX Byte 1 ==
7894 10:00:53.143314 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7895 10:00:53.146608 DramC Write-DBI off
7896 10:00:53.146687
7897 10:00:53.146750 [DATLAT]
7898 10:00:53.146808 Freq=1600, CH0 RK1
7899 10:00:53.146866
7900 10:00:53.150067 DATLAT Default: 0xe
7901 10:00:53.150146 0, 0xFFFF, sum = 0
7902 10:00:53.153349 1, 0xFFFF, sum = 0
7903 10:00:53.156692 2, 0xFFFF, sum = 0
7904 10:00:53.156772 3, 0xFFFF, sum = 0
7905 10:00:53.159865 4, 0xFFFF, sum = 0
7906 10:00:53.159946 5, 0xFFFF, sum = 0
7907 10:00:53.163080 6, 0xFFFF, sum = 0
7908 10:00:53.163159 7, 0xFFFF, sum = 0
7909 10:00:53.166517 8, 0xFFFF, sum = 0
7910 10:00:53.166597 9, 0xFFFF, sum = 0
7911 10:00:53.170235 10, 0xFFFF, sum = 0
7912 10:00:53.170315 11, 0xFFFF, sum = 0
7913 10:00:53.173115 12, 0x8FFF, sum = 0
7914 10:00:53.173195 13, 0x0, sum = 1
7915 10:00:53.176444 14, 0x0, sum = 2
7916 10:00:53.176547 15, 0x0, sum = 3
7917 10:00:53.179854 16, 0x0, sum = 4
7918 10:00:53.179934 best_step = 14
7919 10:00:53.179996
7920 10:00:53.180054 ==
7921 10:00:53.183232 Dram Type= 6, Freq= 0, CH_0, rank 1
7922 10:00:53.186417 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7923 10:00:53.189738 ==
7924 10:00:53.189817 RX Vref Scan: 0
7925 10:00:53.189879
7926 10:00:53.193144 RX Vref 0 -> 0, step: 1
7927 10:00:53.193224
7928 10:00:53.196487 RX Delay 11 -> 252, step: 4
7929 10:00:53.199841 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7930 10:00:53.202925 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7931 10:00:53.206102 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7932 10:00:53.212776 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
7933 10:00:53.216084 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7934 10:00:53.219436 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
7935 10:00:53.222966 iDelay=195, Bit 6, Center 136 (79 ~ 194) 116
7936 10:00:53.226095 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7937 10:00:53.232719 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7938 10:00:53.236027 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7939 10:00:53.239244 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7940 10:00:53.242546 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7941 10:00:53.246193 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7942 10:00:53.252529 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
7943 10:00:53.256193 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
7944 10:00:53.259315 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7945 10:00:53.259395 ==
7946 10:00:53.262681 Dram Type= 6, Freq= 0, CH_0, rank 1
7947 10:00:53.265785 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7948 10:00:53.265865 ==
7949 10:00:53.269092 DQS Delay:
7950 10:00:53.269171 DQS0 = 0, DQS1 = 0
7951 10:00:53.272474 DQM Delay:
7952 10:00:53.272595 DQM0 = 128, DQM1 = 120
7953 10:00:53.275865 DQ Delay:
7954 10:00:53.279157 DQ0 =122, DQ1 =132, DQ2 =126, DQ3 =122
7955 10:00:53.282441 DQ4 =130, DQ5 =120, DQ6 =136, DQ7 =138
7956 10:00:53.285543 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
7957 10:00:53.288843 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =130
7958 10:00:53.288922
7959 10:00:53.288984
7960 10:00:53.289041
7961 10:00:53.292295 [DramC_TX_OE_Calibration] TA2
7962 10:00:53.295522 Original DQ_B0 (3 6) =30, OEN = 27
7963 10:00:53.298837 Original DQ_B1 (3 6) =30, OEN = 27
7964 10:00:53.302439 24, 0x0, End_B0=24 End_B1=24
7965 10:00:53.302519 25, 0x0, End_B0=25 End_B1=25
7966 10:00:53.305536 26, 0x0, End_B0=26 End_B1=26
7967 10:00:53.308757 27, 0x0, End_B0=27 End_B1=27
7968 10:00:53.312194 28, 0x0, End_B0=28 End_B1=28
7969 10:00:53.312274 29, 0x0, End_B0=29 End_B1=29
7970 10:00:53.315497 30, 0x0, End_B0=30 End_B1=30
7971 10:00:53.318749 31, 0x4141, End_B0=30 End_B1=30
7972 10:00:53.322210 Byte0 end_step=30 best_step=27
7973 10:00:53.325368 Byte1 end_step=30 best_step=27
7974 10:00:53.328804 Byte0 TX OE(2T, 0.5T) = (3, 3)
7975 10:00:53.328883 Byte1 TX OE(2T, 0.5T) = (3, 3)
7976 10:00:53.328945
7977 10:00:53.332094
7978 10:00:53.338535 [DQSOSCAuto] RK1, (LSB)MR18= 0x2424, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
7979 10:00:53.342096 CH0 RK1: MR19=303, MR18=2424
7980 10:00:53.348452 CH0_RK1: MR19=0x303, MR18=0x2424, DQSOSC=391, MR23=63, INC=24, DEC=16
7981 10:00:53.351874 [RxdqsGatingPostProcess] freq 1600
7982 10:00:53.355249 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7983 10:00:53.358492 Pre-setting of DQS Precalculation
7984 10:00:53.364909 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7985 10:00:53.364990 ==
7986 10:00:53.368311 Dram Type= 6, Freq= 0, CH_1, rank 0
7987 10:00:53.371681 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7988 10:00:53.371763 ==
7989 10:00:53.378621 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7990 10:00:53.381659 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
7991 10:00:53.384904 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
7992 10:00:53.391580 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7993 10:00:53.399759 [CA 0] Center 41 (11~71) winsize 61
7994 10:00:53.402697 [CA 1] Center 41 (11~72) winsize 62
7995 10:00:53.406284 [CA 2] Center 37 (7~67) winsize 61
7996 10:00:53.409311 [CA 3] Center 36 (7~66) winsize 60
7997 10:00:53.412489 [CA 4] Center 34 (4~64) winsize 61
7998 10:00:53.416099 [CA 5] Center 34 (4~64) winsize 61
7999 10:00:53.416180
8000 10:00:53.419332 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8001 10:00:53.419414
8002 10:00:53.422852 [CATrainingPosCal] consider 1 rank data
8003 10:00:53.426010 u2DelayCellTimex100 = 275/100 ps
8004 10:00:53.429368 CA0 delay=41 (11~71),Diff = 7 PI (24 cell)
8005 10:00:53.435970 CA1 delay=41 (11~72),Diff = 7 PI (24 cell)
8006 10:00:53.439366 CA2 delay=37 (7~67),Diff = 3 PI (10 cell)
8007 10:00:53.442547 CA3 delay=36 (7~66),Diff = 2 PI (7 cell)
8008 10:00:53.445948 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8009 10:00:53.449092 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
8010 10:00:53.449172
8011 10:00:53.452413 CA PerBit enable=1, Macro0, CA PI delay=34
8012 10:00:53.452494
8013 10:00:53.455712 [CBTSetCACLKResult] CA Dly = 34
8014 10:00:53.459033 CS Dly: 8 (0~39)
8015 10:00:53.462566 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8016 10:00:53.465762 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8017 10:00:53.465843 ==
8018 10:00:53.469145 Dram Type= 6, Freq= 0, CH_1, rank 1
8019 10:00:53.472290 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8020 10:00:53.475705 ==
8021 10:00:53.479088 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8022 10:00:53.482371 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8023 10:00:53.488996 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8024 10:00:53.495349 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8025 10:00:53.501840 [CA 0] Center 40 (10~70) winsize 61
8026 10:00:53.505121 [CA 1] Center 39 (9~70) winsize 62
8027 10:00:53.508460 [CA 2] Center 35 (6~65) winsize 60
8028 10:00:53.511663 [CA 3] Center 35 (6~65) winsize 60
8029 10:00:53.514934 [CA 4] Center 33 (4~62) winsize 59
8030 10:00:53.518345 [CA 5] Center 33 (4~63) winsize 60
8031 10:00:53.518426
8032 10:00:53.521688 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8033 10:00:53.521769
8034 10:00:53.525209 [CATrainingPosCal] consider 2 rank data
8035 10:00:53.528231 u2DelayCellTimex100 = 275/100 ps
8036 10:00:53.531604 CA0 delay=40 (11~70),Diff = 7 PI (24 cell)
8037 10:00:53.538008 CA1 delay=40 (11~70),Diff = 7 PI (24 cell)
8038 10:00:53.541338 CA2 delay=36 (7~65),Diff = 3 PI (10 cell)
8039 10:00:53.544904 CA3 delay=36 (7~65),Diff = 3 PI (10 cell)
8040 10:00:53.548034 CA4 delay=33 (4~62),Diff = 0 PI (0 cell)
8041 10:00:53.551519 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8042 10:00:53.551598
8043 10:00:53.554694 CA PerBit enable=1, Macro0, CA PI delay=33
8044 10:00:53.554774
8045 10:00:53.558089 [CBTSetCACLKResult] CA Dly = 33
8046 10:00:53.561381 CS Dly: 9 (0~41)
8047 10:00:53.564798 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8048 10:00:53.568280 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8049 10:00:53.568359
8050 10:00:53.571388 ----->DramcWriteLeveling(PI) begin...
8051 10:00:53.571469 ==
8052 10:00:53.574479 Dram Type= 6, Freq= 0, CH_1, rank 0
8053 10:00:53.581016 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8054 10:00:53.581097 ==
8055 10:00:53.584366 Write leveling (Byte 0): 22 => 22
8056 10:00:53.587897 Write leveling (Byte 1): 22 => 22
8057 10:00:53.587977 DramcWriteLeveling(PI) end<-----
8058 10:00:53.588040
8059 10:00:53.591239 ==
8060 10:00:53.594552 Dram Type= 6, Freq= 0, CH_1, rank 0
8061 10:00:53.597784 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8062 10:00:53.597896 ==
8063 10:00:53.601016 [Gating] SW mode calibration
8064 10:00:53.607587 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8065 10:00:53.610880 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8066 10:00:53.617591 0 12 0 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
8067 10:00:53.620925 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8068 10:00:53.624268 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 10:00:53.631086 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8070 10:00:53.634183 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8071 10:00:53.637467 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8072 10:00:53.644179 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8073 10:00:53.647506 0 12 28 | B1->B0 | 3434 2929 | 1 1 | (1 1) (1 0)
8074 10:00:53.650934 0 13 0 | B1->B0 | 3232 2323 | 0 0 | (0 0) (1 0)
8075 10:00:53.657362 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 10:00:53.660810 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 10:00:53.664064 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 10:00:53.670779 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8079 10:00:53.674085 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8080 10:00:53.677245 0 13 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8081 10:00:53.684347 0 13 28 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (1 1)
8082 10:00:53.687216 0 14 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
8083 10:00:53.690864 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8084 10:00:53.697526 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 10:00:53.700472 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 10:00:53.703866 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 10:00:53.710392 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 10:00:53.713800 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8089 10:00:53.717121 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8090 10:00:53.720771 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8091 10:00:53.727284 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8092 10:00:53.730601 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 10:00:53.733862 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 10:00:53.740362 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 10:00:53.743722 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 10:00:53.747315 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 10:00:53.753822 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 10:00:53.757421 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 10:00:53.760446 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 10:00:53.767100 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 10:00:53.770457 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 10:00:53.773633 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 10:00:53.780108 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 10:00:53.783678 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8105 10:00:53.786804 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8106 10:00:53.793564 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8107 10:00:53.793644 Total UI for P1: 0, mck2ui 16
8108 10:00:53.800163 best dqsien dly found for B0: ( 1, 0, 26)
8109 10:00:53.803422 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8110 10:00:53.807048 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8111 10:00:53.810204 Total UI for P1: 0, mck2ui 16
8112 10:00:53.813383 best dqsien dly found for B1: ( 1, 1, 2)
8113 10:00:53.816631 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8114 10:00:53.819997 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8115 10:00:53.820075
8116 10:00:53.826952 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8117 10:00:53.829785 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8118 10:00:53.829863 [Gating] SW calibration Done
8119 10:00:53.833127 ==
8120 10:00:53.836431 Dram Type= 6, Freq= 0, CH_1, rank 0
8121 10:00:53.839832 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8122 10:00:53.839912 ==
8123 10:00:53.839974 RX Vref Scan: 0
8124 10:00:53.840033
8125 10:00:53.843032 RX Vref 0 -> 0, step: 1
8126 10:00:53.843112
8127 10:00:53.846360 RX Delay 0 -> 252, step: 8
8128 10:00:53.849586 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8129 10:00:53.852935 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8130 10:00:53.856481 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8131 10:00:53.862961 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8132 10:00:53.866339 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8133 10:00:53.869704 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8134 10:00:53.873010 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8135 10:00:53.876220 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8136 10:00:53.882870 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8137 10:00:53.886276 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8138 10:00:53.889544 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8139 10:00:53.892563 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8140 10:00:53.899315 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8141 10:00:53.902557 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8142 10:00:53.905875 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8143 10:00:53.909135 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8144 10:00:53.909216 ==
8145 10:00:53.912682 Dram Type= 6, Freq= 0, CH_1, rank 0
8146 10:00:53.915766 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8147 10:00:53.918998 ==
8148 10:00:53.919078 DQS Delay:
8149 10:00:53.919141 DQS0 = 0, DQS1 = 0
8150 10:00:53.922365 DQM Delay:
8151 10:00:53.922445 DQM0 = 130, DQM1 = 127
8152 10:00:53.925621 DQ Delay:
8153 10:00:53.929109 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =127
8154 10:00:53.932396 DQ4 =131, DQ5 =139, DQ6 =135, DQ7 =127
8155 10:00:53.935735 DQ8 =111, DQ9 =119, DQ10 =127, DQ11 =115
8156 10:00:53.939253 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8157 10:00:53.939333
8158 10:00:53.939395
8159 10:00:53.939452 ==
8160 10:00:53.942246 Dram Type= 6, Freq= 0, CH_1, rank 0
8161 10:00:53.945563 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8162 10:00:53.945643 ==
8163 10:00:53.949069
8164 10:00:53.949147
8165 10:00:53.949210 TX Vref Scan disable
8166 10:00:53.952286 == TX Byte 0 ==
8167 10:00:53.955578 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8168 10:00:53.959104 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8169 10:00:53.962080 == TX Byte 1 ==
8170 10:00:53.965437 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8171 10:00:53.969025 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8172 10:00:53.969105 ==
8173 10:00:53.972385 Dram Type= 6, Freq= 0, CH_1, rank 0
8174 10:00:53.978758 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8175 10:00:53.978838 ==
8176 10:00:53.991011
8177 10:00:53.994399 TX Vref early break, caculate TX vref
8178 10:00:53.997524 TX Vref=16, minBit 1, minWin=21, winSum=365
8179 10:00:54.000955 TX Vref=18, minBit 3, minWin=22, winSum=377
8180 10:00:54.004154 TX Vref=20, minBit 3, minWin=22, winSum=382
8181 10:00:54.007626 TX Vref=22, minBit 1, minWin=23, winSum=391
8182 10:00:54.010687 TX Vref=24, minBit 1, minWin=24, winSum=398
8183 10:00:54.017343 TX Vref=26, minBit 1, minWin=24, winSum=408
8184 10:00:54.020693 TX Vref=28, minBit 3, minWin=23, winSum=409
8185 10:00:54.024077 TX Vref=30, minBit 1, minWin=24, winSum=403
8186 10:00:54.027305 TX Vref=32, minBit 1, minWin=24, winSum=398
8187 10:00:54.030578 TX Vref=34, minBit 2, minWin=23, winSum=388
8188 10:00:54.037129 TX Vref=36, minBit 1, minWin=22, winSum=374
8189 10:00:54.040282 [TxChooseVref] Worse bit 1, Min win 24, Win sum 408, Final Vref 26
8190 10:00:54.040362
8191 10:00:54.043594 Final TX Range 0 Vref 26
8192 10:00:54.043674
8193 10:00:54.043737 ==
8194 10:00:54.047077 Dram Type= 6, Freq= 0, CH_1, rank 0
8195 10:00:54.050398 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8196 10:00:54.050479 ==
8197 10:00:54.053707
8198 10:00:54.053787
8199 10:00:54.053850 TX Vref Scan disable
8200 10:00:54.060461 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8201 10:00:54.060547 == TX Byte 0 ==
8202 10:00:54.063776 u2DelayCellOfst[0]=14 cells (4 PI)
8203 10:00:54.067066 u2DelayCellOfst[1]=7 cells (2 PI)
8204 10:00:54.070316 u2DelayCellOfst[2]=0 cells (0 PI)
8205 10:00:54.073832 u2DelayCellOfst[3]=3 cells (1 PI)
8206 10:00:54.076976 u2DelayCellOfst[4]=7 cells (2 PI)
8207 10:00:54.080322 u2DelayCellOfst[5]=14 cells (4 PI)
8208 10:00:54.083588 u2DelayCellOfst[6]=14 cells (4 PI)
8209 10:00:54.086892 u2DelayCellOfst[7]=3 cells (1 PI)
8210 10:00:54.090259 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8211 10:00:54.093600 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8212 10:00:54.096663 == TX Byte 1 ==
8213 10:00:54.099886 u2DelayCellOfst[8]=0 cells (0 PI)
8214 10:00:54.103227 u2DelayCellOfst[9]=3 cells (1 PI)
8215 10:00:54.106502 u2DelayCellOfst[10]=10 cells (3 PI)
8216 10:00:54.106583 u2DelayCellOfst[11]=3 cells (1 PI)
8217 10:00:54.110051 u2DelayCellOfst[12]=14 cells (4 PI)
8218 10:00:54.113476 u2DelayCellOfst[13]=17 cells (5 PI)
8219 10:00:54.116528 u2DelayCellOfst[14]=17 cells (5 PI)
8220 10:00:54.120132 u2DelayCellOfst[15]=17 cells (5 PI)
8221 10:00:54.126539 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8222 10:00:54.129825 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8223 10:00:54.129908 DramC Write-DBI on
8224 10:00:54.129971 ==
8225 10:00:54.133229 Dram Type= 6, Freq= 0, CH_1, rank 0
8226 10:00:54.139713 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8227 10:00:54.139795 ==
8228 10:00:54.139858
8229 10:00:54.139917
8230 10:00:54.143093 TX Vref Scan disable
8231 10:00:54.143173 == TX Byte 0 ==
8232 10:00:54.149544 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8233 10:00:54.149625 == TX Byte 1 ==
8234 10:00:54.152935 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8235 10:00:54.156295 DramC Write-DBI off
8236 10:00:54.156375
8237 10:00:54.156438 [DATLAT]
8238 10:00:54.159569 Freq=1600, CH1 RK0
8239 10:00:54.159649
8240 10:00:54.159712 DATLAT Default: 0xf
8241 10:00:54.162919 0, 0xFFFF, sum = 0
8242 10:00:54.163001 1, 0xFFFF, sum = 0
8243 10:00:54.166231 2, 0xFFFF, sum = 0
8244 10:00:54.166312 3, 0xFFFF, sum = 0
8245 10:00:54.169453 4, 0xFFFF, sum = 0
8246 10:00:54.169534 5, 0xFFFF, sum = 0
8247 10:00:54.172810 6, 0xFFFF, sum = 0
8248 10:00:54.172891 7, 0xFFFF, sum = 0
8249 10:00:54.176156 8, 0xFFFF, sum = 0
8250 10:00:54.176239 9, 0xFFFF, sum = 0
8251 10:00:54.179287 10, 0xFFFF, sum = 0
8252 10:00:54.182575 11, 0xFFFF, sum = 0
8253 10:00:54.182657 12, 0xF7F, sum = 0
8254 10:00:54.185954 13, 0x0, sum = 1
8255 10:00:54.186036 14, 0x0, sum = 2
8256 10:00:54.186120 15, 0x0, sum = 3
8257 10:00:54.189542 16, 0x0, sum = 4
8258 10:00:54.189623 best_step = 14
8259 10:00:54.189687
8260 10:00:54.189746 ==
8261 10:00:54.192789 Dram Type= 6, Freq= 0, CH_1, rank 0
8262 10:00:54.199340 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8263 10:00:54.199436 ==
8264 10:00:54.199501 RX Vref Scan: 1
8265 10:00:54.199560
8266 10:00:54.202832 Set Vref Range= 24 -> 127
8267 10:00:54.202913
8268 10:00:54.206020 RX Vref 24 -> 127, step: 1
8269 10:00:54.206100
8270 10:00:54.209399 RX Delay 11 -> 252, step: 4
8271 10:00:54.209479
8272 10:00:54.212468 Set Vref, RX VrefLevel [Byte0]: 24
8273 10:00:54.216151 [Byte1]: 24
8274 10:00:54.216233
8275 10:00:54.219320 Set Vref, RX VrefLevel [Byte0]: 25
8276 10:00:54.222413 [Byte1]: 25
8277 10:00:54.222500
8278 10:00:54.225927 Set Vref, RX VrefLevel [Byte0]: 26
8279 10:00:54.228941 [Byte1]: 26
8280 10:00:54.232402
8281 10:00:54.232482 Set Vref, RX VrefLevel [Byte0]: 27
8282 10:00:54.235624 [Byte1]: 27
8283 10:00:54.239992
8284 10:00:54.240073 Set Vref, RX VrefLevel [Byte0]: 28
8285 10:00:54.243482 [Byte1]: 28
8286 10:00:54.247547
8287 10:00:54.247634 Set Vref, RX VrefLevel [Byte0]: 29
8288 10:00:54.251083 [Byte1]: 29
8289 10:00:54.255173
8290 10:00:54.255253 Set Vref, RX VrefLevel [Byte0]: 30
8291 10:00:54.258559 [Byte1]: 30
8292 10:00:54.262744
8293 10:00:54.262824 Set Vref, RX VrefLevel [Byte0]: 31
8294 10:00:54.266341 [Byte1]: 31
8295 10:00:54.270330
8296 10:00:54.270409 Set Vref, RX VrefLevel [Byte0]: 32
8297 10:00:54.273709 [Byte1]: 32
8298 10:00:54.277917
8299 10:00:54.277996 Set Vref, RX VrefLevel [Byte0]: 33
8300 10:00:54.281453 [Byte1]: 33
8301 10:00:54.285547
8302 10:00:54.285626 Set Vref, RX VrefLevel [Byte0]: 34
8303 10:00:54.288899 [Byte1]: 34
8304 10:00:54.293264
8305 10:00:54.293343 Set Vref, RX VrefLevel [Byte0]: 35
8306 10:00:54.296664 [Byte1]: 35
8307 10:00:54.301410
8308 10:00:54.301507 Set Vref, RX VrefLevel [Byte0]: 36
8309 10:00:54.304116 [Byte1]: 36
8310 10:00:54.308598
8311 10:00:54.308677 Set Vref, RX VrefLevel [Byte0]: 37
8312 10:00:54.311754 [Byte1]: 37
8313 10:00:54.316057
8314 10:00:54.316136 Set Vref, RX VrefLevel [Byte0]: 38
8315 10:00:54.319504 [Byte1]: 38
8316 10:00:54.323594
8317 10:00:54.323673 Set Vref, RX VrefLevel [Byte0]: 39
8318 10:00:54.327132 [Byte1]: 39
8319 10:00:54.331365
8320 10:00:54.331444 Set Vref, RX VrefLevel [Byte0]: 40
8321 10:00:54.334664 [Byte1]: 40
8322 10:00:54.338946
8323 10:00:54.339026 Set Vref, RX VrefLevel [Byte0]: 41
8324 10:00:54.342202 [Byte1]: 41
8325 10:00:54.346628
8326 10:00:54.346707 Set Vref, RX VrefLevel [Byte0]: 42
8327 10:00:54.349720 [Byte1]: 42
8328 10:00:54.354209
8329 10:00:54.354287 Set Vref, RX VrefLevel [Byte0]: 43
8330 10:00:54.357356 [Byte1]: 43
8331 10:00:54.362061
8332 10:00:54.362140 Set Vref, RX VrefLevel [Byte0]: 44
8333 10:00:54.365100 [Byte1]: 44
8334 10:00:54.369661
8335 10:00:54.369740 Set Vref, RX VrefLevel [Byte0]: 45
8336 10:00:54.372647 [Byte1]: 45
8337 10:00:54.376913
8338 10:00:54.376992 Set Vref, RX VrefLevel [Byte0]: 46
8339 10:00:54.380466 [Byte1]: 46
8340 10:00:54.384463
8341 10:00:54.384547 Set Vref, RX VrefLevel [Byte0]: 47
8342 10:00:54.387902 [Byte1]: 47
8343 10:00:54.392362
8344 10:00:54.392441 Set Vref, RX VrefLevel [Byte0]: 48
8345 10:00:54.395596 [Byte1]: 48
8346 10:00:54.399977
8347 10:00:54.400056 Set Vref, RX VrefLevel [Byte0]: 49
8348 10:00:54.403221 [Byte1]: 49
8349 10:00:54.407349
8350 10:00:54.407428 Set Vref, RX VrefLevel [Byte0]: 50
8351 10:00:54.410617 [Byte1]: 50
8352 10:00:54.415172
8353 10:00:54.415252 Set Vref, RX VrefLevel [Byte0]: 51
8354 10:00:54.418560 [Byte1]: 51
8355 10:00:54.422698
8356 10:00:54.422782 Set Vref, RX VrefLevel [Byte0]: 52
8357 10:00:54.426041 [Byte1]: 52
8358 10:00:54.430131
8359 10:00:54.433737 Set Vref, RX VrefLevel [Byte0]: 53
8360 10:00:54.436765 [Byte1]: 53
8361 10:00:54.436844
8362 10:00:54.439973 Set Vref, RX VrefLevel [Byte0]: 54
8363 10:00:54.443251 [Byte1]: 54
8364 10:00:54.443328
8365 10:00:54.446531 Set Vref, RX VrefLevel [Byte0]: 55
8366 10:00:54.449829 [Byte1]: 55
8367 10:00:54.453229
8368 10:00:54.453306 Set Vref, RX VrefLevel [Byte0]: 56
8369 10:00:54.456623 [Byte1]: 56
8370 10:00:54.460777
8371 10:00:54.460854 Set Vref, RX VrefLevel [Byte0]: 57
8372 10:00:54.464054 [Byte1]: 57
8373 10:00:54.468617
8374 10:00:54.468695 Set Vref, RX VrefLevel [Byte0]: 58
8375 10:00:54.471782 [Byte1]: 58
8376 10:00:54.475842
8377 10:00:54.475920 Set Vref, RX VrefLevel [Byte0]: 59
8378 10:00:54.479181 [Byte1]: 59
8379 10:00:54.483596
8380 10:00:54.483704 Set Vref, RX VrefLevel [Byte0]: 60
8381 10:00:54.486823 [Byte1]: 60
8382 10:00:54.491507
8383 10:00:54.491585 Set Vref, RX VrefLevel [Byte0]: 61
8384 10:00:54.494350 [Byte1]: 61
8385 10:00:54.498868
8386 10:00:54.498946 Set Vref, RX VrefLevel [Byte0]: 62
8387 10:00:54.502147 [Byte1]: 62
8388 10:00:54.506514
8389 10:00:54.506591 Set Vref, RX VrefLevel [Byte0]: 63
8390 10:00:54.509642 [Byte1]: 63
8391 10:00:54.513937
8392 10:00:54.514014 Set Vref, RX VrefLevel [Byte0]: 64
8393 10:00:54.517208 [Byte1]: 64
8394 10:00:54.521687
8395 10:00:54.521766 Set Vref, RX VrefLevel [Byte0]: 65
8396 10:00:54.525002 [Byte1]: 65
8397 10:00:54.529169
8398 10:00:54.529247 Set Vref, RX VrefLevel [Byte0]: 66
8399 10:00:54.532490 [Byte1]: 66
8400 10:00:54.536830
8401 10:00:54.536907 Set Vref, RX VrefLevel [Byte0]: 67
8402 10:00:54.540209 [Byte1]: 67
8403 10:00:54.544682
8404 10:00:54.544759 Set Vref, RX VrefLevel [Byte0]: 68
8405 10:00:54.547631 [Byte1]: 68
8406 10:00:54.552015
8407 10:00:54.552093 Set Vref, RX VrefLevel [Byte0]: 69
8408 10:00:54.555259 [Byte1]: 69
8409 10:00:54.559761
8410 10:00:54.559838 Set Vref, RX VrefLevel [Byte0]: 70
8411 10:00:54.563105 [Byte1]: 70
8412 10:00:54.567235
8413 10:00:54.567312 Set Vref, RX VrefLevel [Byte0]: 71
8414 10:00:54.570568 [Byte1]: 71
8415 10:00:54.574985
8416 10:00:54.575063 Set Vref, RX VrefLevel [Byte0]: 72
8417 10:00:54.578204 [Byte1]: 72
8418 10:00:54.582564
8419 10:00:54.582642 Set Vref, RX VrefLevel [Byte0]: 73
8420 10:00:54.586016 [Byte1]: 73
8421 10:00:54.590417
8422 10:00:54.590495 Set Vref, RX VrefLevel [Byte0]: 74
8423 10:00:54.593641 [Byte1]: 74
8424 10:00:54.597981
8425 10:00:54.598059 Set Vref, RX VrefLevel [Byte0]: 75
8426 10:00:54.600994 [Byte1]: 75
8427 10:00:54.605240
8428 10:00:54.605318 Set Vref, RX VrefLevel [Byte0]: 76
8429 10:00:54.608635 [Byte1]: 76
8430 10:00:54.613211
8431 10:00:54.613288 Set Vref, RX VrefLevel [Byte0]: 77
8432 10:00:54.616243 [Byte1]: 77
8433 10:00:54.620467
8434 10:00:54.620606 Final RX Vref Byte 0 = 60 to rank0
8435 10:00:54.623784 Final RX Vref Byte 1 = 54 to rank0
8436 10:00:54.627127 Final RX Vref Byte 0 = 60 to rank1
8437 10:00:54.630370 Final RX Vref Byte 1 = 54 to rank1==
8438 10:00:54.633716 Dram Type= 6, Freq= 0, CH_1, rank 0
8439 10:00:54.640333 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8440 10:00:54.640417 ==
8441 10:00:54.640496 DQS Delay:
8442 10:00:54.643841 DQS0 = 0, DQS1 = 0
8443 10:00:54.643920 DQM Delay:
8444 10:00:54.643997 DQM0 = 128, DQM1 = 124
8445 10:00:54.647180 DQ Delay:
8446 10:00:54.650476 DQ0 =132, DQ1 =122, DQ2 =116, DQ3 =128
8447 10:00:54.653805 DQ4 =130, DQ5 =138, DQ6 =138, DQ7 =124
8448 10:00:54.657059 DQ8 =106, DQ9 =114, DQ10 =126, DQ11 =114
8449 10:00:54.660481 DQ12 =132, DQ13 =134, DQ14 =134, DQ15 =134
8450 10:00:54.660567
8451 10:00:54.660629
8452 10:00:54.660686
8453 10:00:54.663692 [DramC_TX_OE_Calibration] TA2
8454 10:00:54.667033 Original DQ_B0 (3 6) =30, OEN = 27
8455 10:00:54.670375 Original DQ_B1 (3 6) =30, OEN = 27
8456 10:00:54.673555 24, 0x0, End_B0=24 End_B1=24
8457 10:00:54.673635 25, 0x0, End_B0=25 End_B1=25
8458 10:00:54.676980 26, 0x0, End_B0=26 End_B1=26
8459 10:00:54.680233 27, 0x0, End_B0=27 End_B1=27
8460 10:00:54.683625 28, 0x0, End_B0=28 End_B1=28
8461 10:00:54.686874 29, 0x0, End_B0=29 End_B1=29
8462 10:00:54.686954 30, 0x0, End_B0=30 End_B1=30
8463 10:00:54.690261 31, 0x4141, End_B0=30 End_B1=30
8464 10:00:54.693602 Byte0 end_step=30 best_step=27
8465 10:00:54.697031 Byte1 end_step=30 best_step=27
8466 10:00:54.700240 Byte0 TX OE(2T, 0.5T) = (3, 3)
8467 10:00:54.703405 Byte1 TX OE(2T, 0.5T) = (3, 3)
8468 10:00:54.703484
8469 10:00:54.703546
8470 10:00:54.710263 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b2b, (MSB)MR19= 0x303, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
8471 10:00:54.713609 CH1 RK0: MR19=303, MR18=2B2B
8472 10:00:54.720037 CH1_RK0: MR19=0x303, MR18=0x2B2B, DQSOSC=388, MR23=63, INC=24, DEC=16
8473 10:00:54.720117
8474 10:00:54.723706 ----->DramcWriteLeveling(PI) begin...
8475 10:00:54.723786 ==
8476 10:00:54.726898 Dram Type= 6, Freq= 0, CH_1, rank 1
8477 10:00:54.730256 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8478 10:00:54.730365 ==
8479 10:00:54.733428 Write leveling (Byte 0): 23 => 23
8480 10:00:54.736764 Write leveling (Byte 1): 20 => 20
8481 10:00:54.740158 DramcWriteLeveling(PI) end<-----
8482 10:00:54.740238
8483 10:00:54.740301 ==
8484 10:00:54.743587 Dram Type= 6, Freq= 0, CH_1, rank 1
8485 10:00:54.746646 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8486 10:00:54.746727 ==
8487 10:00:54.750147 [Gating] SW mode calibration
8488 10:00:54.756602 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8489 10:00:54.763187 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8490 10:00:54.766563 0 12 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8491 10:00:54.773132 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8492 10:00:54.776610 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8493 10:00:54.779664 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8494 10:00:54.782987 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8495 10:00:54.789631 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8496 10:00:54.793192 0 12 24 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 1)
8497 10:00:54.796281 0 12 28 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8498 10:00:54.803011 0 13 0 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8499 10:00:54.806316 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8500 10:00:54.809637 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8501 10:00:54.816292 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8502 10:00:54.819502 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8503 10:00:54.822857 0 13 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8504 10:00:54.829289 0 13 24 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
8505 10:00:54.832670 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8506 10:00:54.836130 0 14 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8507 10:00:54.842701 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8508 10:00:54.845984 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8509 10:00:54.849540 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8510 10:00:54.856202 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8511 10:00:54.859050 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8512 10:00:54.862440 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8513 10:00:54.869035 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8514 10:00:54.872420 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8515 10:00:54.875679 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8516 10:00:54.882470 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8517 10:00:54.885806 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8518 10:00:54.888841 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8519 10:00:54.895295 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8520 10:00:54.898768 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8521 10:00:54.901953 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8522 10:00:54.908516 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8523 10:00:54.911845 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8524 10:00:54.915342 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8525 10:00:54.921829 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8526 10:00:54.924920 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8527 10:00:54.928210 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8528 10:00:54.935041 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8529 10:00:54.938334 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8530 10:00:54.941443 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8531 10:00:54.945110 Total UI for P1: 0, mck2ui 16
8532 10:00:54.948303 best dqsien dly found for B0: ( 1, 0, 26)
8533 10:00:54.954835 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8534 10:00:54.954922 Total UI for P1: 0, mck2ui 16
8535 10:00:54.961249 best dqsien dly found for B1: ( 1, 1, 0)
8536 10:00:54.964608 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8537 10:00:54.967834 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8538 10:00:54.967915
8539 10:00:54.971257 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8540 10:00:54.974426 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8541 10:00:54.977877 [Gating] SW calibration Done
8542 10:00:54.977958 ==
8543 10:00:54.981217 Dram Type= 6, Freq= 0, CH_1, rank 1
8544 10:00:54.984435 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8545 10:00:54.984579 ==
8546 10:00:54.987824 RX Vref Scan: 0
8547 10:00:54.987906
8548 10:00:54.987969 RX Vref 0 -> 0, step: 1
8549 10:00:54.988028
8550 10:00:54.990974 RX Delay 0 -> 252, step: 8
8551 10:00:54.994237 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8552 10:00:55.001000 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8553 10:00:55.004263 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8554 10:00:55.007616 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8555 10:00:55.010936 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8556 10:00:55.014163 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8557 10:00:55.020730 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8558 10:00:55.024089 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8559 10:00:55.027617 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8560 10:00:55.030703 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8561 10:00:55.034080 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8562 10:00:55.040854 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8563 10:00:55.044210 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8564 10:00:55.047386 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8565 10:00:55.050685 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8566 10:00:55.057256 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8567 10:00:55.057349 ==
8568 10:00:55.060611 Dram Type= 6, Freq= 0, CH_1, rank 1
8569 10:00:55.063884 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8570 10:00:55.063966 ==
8571 10:00:55.064030 DQS Delay:
8572 10:00:55.067112 DQS0 = 0, DQS1 = 0
8573 10:00:55.067193 DQM Delay:
8574 10:00:55.070530 DQM0 = 131, DQM1 = 125
8575 10:00:55.070612 DQ Delay:
8576 10:00:55.073705 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8577 10:00:55.077075 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8578 10:00:55.080465 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8579 10:00:55.083660 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8580 10:00:55.083741
8581 10:00:55.083804
8582 10:00:55.087016 ==
8583 10:00:55.090176 Dram Type= 6, Freq= 0, CH_1, rank 1
8584 10:00:55.093606 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8585 10:00:55.093690 ==
8586 10:00:55.093754
8587 10:00:55.093814
8588 10:00:55.096698 TX Vref Scan disable
8589 10:00:55.096799 == TX Byte 0 ==
8590 10:00:55.103629 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8591 10:00:55.106752 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8592 10:00:55.106834 == TX Byte 1 ==
8593 10:00:55.113351 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8594 10:00:55.116715 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8595 10:00:55.116798 ==
8596 10:00:55.119911 Dram Type= 6, Freq= 0, CH_1, rank 1
8597 10:00:55.123058 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8598 10:00:55.123141 ==
8599 10:00:55.136448
8600 10:00:55.139741 TX Vref early break, caculate TX vref
8601 10:00:55.143217 TX Vref=16, minBit 5, minWin=21, winSum=380
8602 10:00:55.146551 TX Vref=18, minBit 5, minWin=22, winSum=384
8603 10:00:55.149607 TX Vref=20, minBit 0, minWin=23, winSum=393
8604 10:00:55.153046 TX Vref=22, minBit 5, minWin=23, winSum=403
8605 10:00:55.156193 TX Vref=24, minBit 4, minWin=23, winSum=409
8606 10:00:55.163148 TX Vref=26, minBit 0, minWin=25, winSum=418
8607 10:00:55.166136 TX Vref=28, minBit 0, minWin=25, winSum=420
8608 10:00:55.169422 TX Vref=30, minBit 0, minWin=23, winSum=415
8609 10:00:55.172917 TX Vref=32, minBit 0, minWin=23, winSum=409
8610 10:00:55.176136 TX Vref=34, minBit 0, minWin=22, winSum=398
8611 10:00:55.182741 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 28
8612 10:00:55.182824
8613 10:00:55.185970 Final TX Range 0 Vref 28
8614 10:00:55.186051
8615 10:00:55.186113 ==
8616 10:00:55.189262 Dram Type= 6, Freq= 0, CH_1, rank 1
8617 10:00:55.192716 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8618 10:00:55.192798 ==
8619 10:00:55.192896
8620 10:00:55.192971
8621 10:00:55.196031 TX Vref Scan disable
8622 10:00:55.202605 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8623 10:00:55.202691 == TX Byte 0 ==
8624 10:00:55.205979 u2DelayCellOfst[0]=14 cells (4 PI)
8625 10:00:55.209008 u2DelayCellOfst[1]=10 cells (3 PI)
8626 10:00:55.212454 u2DelayCellOfst[2]=0 cells (0 PI)
8627 10:00:55.215731 u2DelayCellOfst[3]=7 cells (2 PI)
8628 10:00:55.218906 u2DelayCellOfst[4]=7 cells (2 PI)
8629 10:00:55.222307 u2DelayCellOfst[5]=14 cells (4 PI)
8630 10:00:55.225727 u2DelayCellOfst[6]=14 cells (4 PI)
8631 10:00:55.229038 u2DelayCellOfst[7]=3 cells (1 PI)
8632 10:00:55.232314 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8633 10:00:55.235613 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8634 10:00:55.238800 == TX Byte 1 ==
8635 10:00:55.242323 u2DelayCellOfst[8]=0 cells (0 PI)
8636 10:00:55.242405 u2DelayCellOfst[9]=3 cells (1 PI)
8637 10:00:55.245405 u2DelayCellOfst[10]=7 cells (2 PI)
8638 10:00:55.248819 u2DelayCellOfst[11]=3 cells (1 PI)
8639 10:00:55.251841 u2DelayCellOfst[12]=14 cells (4 PI)
8640 10:00:55.255341 u2DelayCellOfst[13]=17 cells (5 PI)
8641 10:00:55.258706 u2DelayCellOfst[14]=17 cells (5 PI)
8642 10:00:55.261948 u2DelayCellOfst[15]=17 cells (5 PI)
8643 10:00:55.265258 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8644 10:00:55.271921 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8645 10:00:55.272005 DramC Write-DBI on
8646 10:00:55.272069 ==
8647 10:00:55.275266 Dram Type= 6, Freq= 0, CH_1, rank 1
8648 10:00:55.281690 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8649 10:00:55.281773 ==
8650 10:00:55.281836
8651 10:00:55.281895
8652 10:00:55.281950 TX Vref Scan disable
8653 10:00:55.285740 == TX Byte 0 ==
8654 10:00:55.288950 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8655 10:00:55.292254 == TX Byte 1 ==
8656 10:00:55.295508 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8657 10:00:55.298826 DramC Write-DBI off
8658 10:00:55.298906
8659 10:00:55.298972 [DATLAT]
8660 10:00:55.299089 Freq=1600, CH1 RK1
8661 10:00:55.299148
8662 10:00:55.302304 DATLAT Default: 0xe
8663 10:00:55.302384 0, 0xFFFF, sum = 0
8664 10:00:55.305318 1, 0xFFFF, sum = 0
8665 10:00:55.308749 2, 0xFFFF, sum = 0
8666 10:00:55.308830 3, 0xFFFF, sum = 0
8667 10:00:55.312175 4, 0xFFFF, sum = 0
8668 10:00:55.312259 5, 0xFFFF, sum = 0
8669 10:00:55.315381 6, 0xFFFF, sum = 0
8670 10:00:55.315467 7, 0xFFFF, sum = 0
8671 10:00:55.318905 8, 0xFFFF, sum = 0
8672 10:00:55.318992 9, 0xFFFF, sum = 0
8673 10:00:55.321884 10, 0xFFFF, sum = 0
8674 10:00:55.321971 11, 0xFFFF, sum = 0
8675 10:00:55.325313 12, 0xF5F, sum = 0
8676 10:00:55.325399 13, 0x0, sum = 1
8677 10:00:55.328734 14, 0x0, sum = 2
8678 10:00:55.328819 15, 0x0, sum = 3
8679 10:00:55.331933 16, 0x0, sum = 4
8680 10:00:55.332015 best_step = 14
8681 10:00:55.332079
8682 10:00:55.332138 ==
8683 10:00:55.335104 Dram Type= 6, Freq= 0, CH_1, rank 1
8684 10:00:55.338408 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8685 10:00:55.341973 ==
8686 10:00:55.342058 RX Vref Scan: 0
8687 10:00:55.342122
8688 10:00:55.345241 RX Vref 0 -> 0, step: 1
8689 10:00:55.345322
8690 10:00:55.345385 RX Delay 3 -> 252, step: 4
8691 10:00:55.352493 iDelay=195, Bit 0, Center 130 (79 ~ 182) 104
8692 10:00:55.355966 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8693 10:00:55.359157 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8694 10:00:55.362633 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8695 10:00:55.365948 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8696 10:00:55.372526 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8697 10:00:55.376031 iDelay=195, Bit 6, Center 134 (79 ~ 190) 112
8698 10:00:55.379306 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8699 10:00:55.382628 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
8700 10:00:55.385841 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8701 10:00:55.392526 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8702 10:00:55.395826 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8703 10:00:55.399244 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8704 10:00:55.402397 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8705 10:00:55.409125 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8706 10:00:55.412535 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8707 10:00:55.412671 ==
8708 10:00:55.415892 Dram Type= 6, Freq= 0, CH_1, rank 1
8709 10:00:55.419123 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8710 10:00:55.419219 ==
8711 10:00:55.419285 DQS Delay:
8712 10:00:55.422341 DQS0 = 0, DQS1 = 0
8713 10:00:55.422431 DQM Delay:
8714 10:00:55.425661 DQM0 = 127, DQM1 = 122
8715 10:00:55.425749 DQ Delay:
8716 10:00:55.429022 DQ0 =130, DQ1 =124, DQ2 =116, DQ3 =124
8717 10:00:55.432496 DQ4 =126, DQ5 =138, DQ6 =134, DQ7 =126
8718 10:00:55.435713 DQ8 =106, DQ9 =110, DQ10 =124, DQ11 =114
8719 10:00:55.442096 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8720 10:00:55.442196
8721 10:00:55.442263
8722 10:00:55.442320
8723 10:00:55.445396 [DramC_TX_OE_Calibration] TA2
8724 10:00:55.445478 Original DQ_B0 (3 6) =30, OEN = 27
8725 10:00:55.448661 Original DQ_B1 (3 6) =30, OEN = 27
8726 10:00:55.452106 24, 0x0, End_B0=24 End_B1=24
8727 10:00:55.455385 25, 0x0, End_B0=25 End_B1=25
8728 10:00:55.458692 26, 0x0, End_B0=26 End_B1=26
8729 10:00:55.458776 27, 0x0, End_B0=27 End_B1=27
8730 10:00:55.462267 28, 0x0, End_B0=28 End_B1=28
8731 10:00:55.465347 29, 0x0, End_B0=29 End_B1=29
8732 10:00:55.468639 30, 0x0, End_B0=30 End_B1=30
8733 10:00:55.472140 31, 0x4141, End_B0=30 End_B1=30
8734 10:00:55.475318 Byte0 end_step=30 best_step=27
8735 10:00:55.475400 Byte1 end_step=30 best_step=27
8736 10:00:55.478583 Byte0 TX OE(2T, 0.5T) = (3, 3)
8737 10:00:55.481852 Byte1 TX OE(2T, 0.5T) = (3, 3)
8738 10:00:55.481933
8739 10:00:55.481996
8740 10:00:55.491894 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
8741 10:00:55.491999 CH1 RK1: MR19=303, MR18=1C1C
8742 10:00:55.498496 CH1_RK1: MR19=0x303, MR18=0x1C1C, DQSOSC=395, MR23=63, INC=23, DEC=15
8743 10:00:55.501787 [RxdqsGatingPostProcess] freq 1600
8744 10:00:55.508650 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8745 10:00:55.511717 Pre-setting of DQS Precalculation
8746 10:00:55.515323 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8747 10:00:55.521735 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8748 10:00:55.531849 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8749 10:00:55.531947
8750 10:00:55.532012
8751 10:00:55.534994 [Calibration Summary] 3200 Mbps
8752 10:00:55.535074 CH 0, Rank 0
8753 10:00:55.538454 SW Impedance : PASS
8754 10:00:55.538534 DUTY Scan : NO K
8755 10:00:55.541634 ZQ Calibration : PASS
8756 10:00:55.544978 Jitter Meter : NO K
8757 10:00:55.545059 CBT Training : PASS
8758 10:00:55.548349 Write leveling : PASS
8759 10:00:55.548430 RX DQS gating : PASS
8760 10:00:55.551515 RX DQ/DQS(RDDQC) : PASS
8761 10:00:55.554913 TX DQ/DQS : PASS
8762 10:00:55.554994 RX DATLAT : PASS
8763 10:00:55.558342 RX DQ/DQS(Engine): PASS
8764 10:00:55.561682 TX OE : PASS
8765 10:00:55.561764 All Pass.
8766 10:00:55.561827
8767 10:00:55.561886 CH 0, Rank 1
8768 10:00:55.564834 SW Impedance : PASS
8769 10:00:55.568185 DUTY Scan : NO K
8770 10:00:55.568265 ZQ Calibration : PASS
8771 10:00:55.571528 Jitter Meter : NO K
8772 10:00:55.574762 CBT Training : PASS
8773 10:00:55.574843 Write leveling : PASS
8774 10:00:55.578427 RX DQS gating : PASS
8775 10:00:55.581616 RX DQ/DQS(RDDQC) : PASS
8776 10:00:55.581697 TX DQ/DQS : PASS
8777 10:00:55.584802 RX DATLAT : PASS
8778 10:00:55.588214 RX DQ/DQS(Engine): PASS
8779 10:00:55.588295 TX OE : PASS
8780 10:00:55.591275 All Pass.
8781 10:00:55.591355
8782 10:00:55.591418 CH 1, Rank 0
8783 10:00:55.594569 SW Impedance : PASS
8784 10:00:55.594649 DUTY Scan : NO K
8785 10:00:55.597838 ZQ Calibration : PASS
8786 10:00:55.601240 Jitter Meter : NO K
8787 10:00:55.601395 CBT Training : PASS
8788 10:00:55.604705 Write leveling : PASS
8789 10:00:55.607924 RX DQS gating : PASS
8790 10:00:55.608005 RX DQ/DQS(RDDQC) : PASS
8791 10:00:55.611007 TX DQ/DQS : PASS
8792 10:00:55.611087 RX DATLAT : PASS
8793 10:00:55.614326 RX DQ/DQS(Engine): PASS
8794 10:00:55.617650 TX OE : PASS
8795 10:00:55.617738 All Pass.
8796 10:00:55.617803
8797 10:00:55.617861 CH 1, Rank 1
8798 10:00:55.621161 SW Impedance : PASS
8799 10:00:55.624377 DUTY Scan : NO K
8800 10:00:55.624459 ZQ Calibration : PASS
8801 10:00:55.627549 Jitter Meter : NO K
8802 10:00:55.630986 CBT Training : PASS
8803 10:00:55.631071 Write leveling : PASS
8804 10:00:55.634234 RX DQS gating : PASS
8805 10:00:55.637570 RX DQ/DQS(RDDQC) : PASS
8806 10:00:55.637652 TX DQ/DQS : PASS
8807 10:00:55.640744 RX DATLAT : PASS
8808 10:00:55.644394 RX DQ/DQS(Engine): PASS
8809 10:00:55.644476 TX OE : PASS
8810 10:00:55.647480 All Pass.
8811 10:00:55.647595
8812 10:00:55.647658 DramC Write-DBI on
8813 10:00:55.650787 PER_BANK_REFRESH: Hybrid Mode
8814 10:00:55.650870 TX_TRACKING: ON
8815 10:00:55.660786 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8816 10:00:55.670647 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8817 10:00:55.677313 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8818 10:00:55.680727 [FAST_K] Save calibration result to emmc
8819 10:00:55.683756 sync common calibartion params.
8820 10:00:55.683845 sync cbt_mode0:0, 1:0
8821 10:00:55.687186 dram_init: ddr_geometry: 0
8822 10:00:55.690290 dram_init: ddr_geometry: 0
8823 10:00:55.693798 dram_init: ddr_geometry: 0
8824 10:00:55.693889 0:dram_rank_size:80000000
8825 10:00:55.697066 1:dram_rank_size:80000000
8826 10:00:55.703586 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8827 10:00:55.703697 DFS_SHUFFLE_HW_MODE: ON
8828 10:00:55.706913 dramc_set_vcore_voltage set vcore to 725000
8829 10:00:55.710209 Read voltage for 1600, 0
8830 10:00:55.710296 Vio18 = 0
8831 10:00:55.713613 Vcore = 725000
8832 10:00:55.713697 Vdram = 0
8833 10:00:55.713761 Vddq = 0
8834 10:00:55.717220 Vmddr = 0
8835 10:00:55.717304 switch to 3200 Mbps bootup
8836 10:00:55.720526 [DramcRunTimeConfig]
8837 10:00:55.720626 PHYPLL
8838 10:00:55.723591 DPM_CONTROL_AFTERK: ON
8839 10:00:55.723676 PER_BANK_REFRESH: ON
8840 10:00:55.726992 REFRESH_OVERHEAD_REDUCTION: ON
8841 10:00:55.730075 CMD_PICG_NEW_MODE: OFF
8842 10:00:55.730161 XRTWTW_NEW_MODE: ON
8843 10:00:55.733527 XRTRTR_NEW_MODE: ON
8844 10:00:55.733616 TX_TRACKING: ON
8845 10:00:55.736737 RDSEL_TRACKING: OFF
8846 10:00:55.740071 DQS Precalculation for DVFS: ON
8847 10:00:55.740162 RX_TRACKING: OFF
8848 10:00:55.743412 HW_GATING DBG: ON
8849 10:00:55.743494 ZQCS_ENABLE_LP4: ON
8850 10:00:55.746800 RX_PICG_NEW_MODE: ON
8851 10:00:55.746909 TX_PICG_NEW_MODE: ON
8852 10:00:55.749906 ENABLE_RX_DCM_DPHY: ON
8853 10:00:55.753261 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8854 10:00:55.756527 DUMMY_READ_FOR_TRACKING: OFF
8855 10:00:55.756629 !!! SPM_CONTROL_AFTERK: OFF
8856 10:00:55.759759 !!! SPM could not control APHY
8857 10:00:55.763197 IMPEDANCE_TRACKING: ON
8858 10:00:55.763284 TEMP_SENSOR: ON
8859 10:00:55.766508 HW_SAVE_FOR_SR: OFF
8860 10:00:55.769830 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8861 10:00:55.773140 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8862 10:00:55.776709 Read ODT Tracking: ON
8863 10:00:55.776802 Refresh Rate DeBounce: ON
8864 10:00:55.779739 DFS_NO_QUEUE_FLUSH: ON
8865 10:00:55.782949 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8866 10:00:55.786370 ENABLE_DFS_RUNTIME_MRW: OFF
8867 10:00:55.786461 DDR_RESERVE_NEW_MODE: ON
8868 10:00:55.789751 MR_CBT_SWITCH_FREQ: ON
8869 10:00:55.792669 =========================
8870 10:00:55.810314 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8871 10:00:55.813623 dram_init: ddr_geometry: 0
8872 10:00:55.831506 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8873 10:00:55.834839 dram_init: dram init end (result: 0)
8874 10:00:55.841580 DRAM-K: Full calibration passed in 23446 msecs
8875 10:00:55.844955 MRC: failed to locate region type 0.
8876 10:00:55.845036 DRAM rank0 size:0x80000000,
8877 10:00:55.848069 DRAM rank1 size=0x80000000
8878 10:00:55.858055 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8879 10:00:55.864945 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8880 10:00:55.871396 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8881 10:00:55.878207 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8882 10:00:55.881132 DRAM rank0 size:0x80000000,
8883 10:00:55.884562 DRAM rank1 size=0x80000000
8884 10:00:55.884646 CBMEM:
8885 10:00:55.887772 IMD: root @ 0xfffff000 254 entries.
8886 10:00:55.891126 IMD: root @ 0xffffec00 62 entries.
8887 10:00:55.894568 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8888 10:00:55.897812 WARNING: RO_VPD is uninitialized or empty.
8889 10:00:55.904338 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8890 10:00:55.911220 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8891 10:00:55.923776 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
8892 10:00:55.935165 BS: romstage times (exec / console): total (unknown) / 22984 ms
8893 10:00:55.935308
8894 10:00:55.935377
8895 10:00:55.945177 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8896 10:00:55.948722 ARM64: Exception handlers installed.
8897 10:00:55.951938 ARM64: Testing exception
8898 10:00:55.955464 ARM64: Done test exception
8899 10:00:55.955544 Enumerating buses...
8900 10:00:55.958633 Show all devs... Before device enumeration.
8901 10:00:55.961896 Root Device: enabled 1
8902 10:00:55.965147 CPU_CLUSTER: 0: enabled 1
8903 10:00:55.965227 CPU: 00: enabled 1
8904 10:00:55.968482 Compare with tree...
8905 10:00:55.968602 Root Device: enabled 1
8906 10:00:55.971769 CPU_CLUSTER: 0: enabled 1
8907 10:00:55.975068 CPU: 00: enabled 1
8908 10:00:55.975147 Root Device scanning...
8909 10:00:55.978466 scan_static_bus for Root Device
8910 10:00:55.981741 CPU_CLUSTER: 0 enabled
8911 10:00:55.985064 scan_static_bus for Root Device done
8912 10:00:55.988205 scan_bus: bus Root Device finished in 8 msecs
8913 10:00:55.988286 done
8914 10:00:55.995038 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8915 10:00:55.998374 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8916 10:00:56.004951 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8917 10:00:56.008117 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8918 10:00:56.011948 Allocating resources...
8919 10:00:56.015109 Reading resources...
8920 10:00:56.018573 Root Device read_resources bus 0 link: 0
8921 10:00:56.018894 DRAM rank0 size:0x80000000,
8922 10:00:56.021476 DRAM rank1 size=0x80000000
8923 10:00:56.024753 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8924 10:00:56.028005 CPU: 00 missing read_resources
8925 10:00:56.031310 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8926 10:00:56.037724 Root Device read_resources bus 0 link: 0 done
8927 10:00:56.037807 Done reading resources.
8928 10:00:56.044371 Show resources in subtree (Root Device)...After reading.
8929 10:00:56.048025 Root Device child on link 0 CPU_CLUSTER: 0
8930 10:00:56.051079 CPU_CLUSTER: 0 child on link 0 CPU: 00
8931 10:00:56.061182 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8932 10:00:56.061338 CPU: 00
8933 10:00:56.064579 Root Device assign_resources, bus 0 link: 0
8934 10:00:56.067775 CPU_CLUSTER: 0 missing set_resources
8935 10:00:56.074592 Root Device assign_resources, bus 0 link: 0 done
8936 10:00:56.074747 Done setting resources.
8937 10:00:56.080949 Show resources in subtree (Root Device)...After assigning values.
8938 10:00:56.084197 Root Device child on link 0 CPU_CLUSTER: 0
8939 10:00:56.087612 CPU_CLUSTER: 0 child on link 0 CPU: 00
8940 10:00:56.097700 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8941 10:00:56.097892 CPU: 00
8942 10:00:56.100774 Done allocating resources.
8943 10:00:56.107503 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8944 10:00:56.107746 Enabling resources...
8945 10:00:56.107874 done.
8946 10:00:56.114292 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8947 10:00:56.114543 Initializing devices...
8948 10:00:56.117434 Root Device init
8949 10:00:56.117719 init hardware done!
8950 10:00:56.120702 0x00000018: ctrlr->caps
8951 10:00:56.124002 52.000 MHz: ctrlr->f_max
8952 10:00:56.124322 0.400 MHz: ctrlr->f_min
8953 10:00:56.127016 0x40ff8080: ctrlr->voltages
8954 10:00:56.130796 sclk: 390625
8955 10:00:56.131180 Bus Width = 1
8956 10:00:56.131424 sclk: 390625
8957 10:00:56.134216 Bus Width = 1
8958 10:00:56.134724 Early init status = 3
8959 10:00:56.140795 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8960 10:00:56.144309 in-header: 03 fc 00 00 01 00 00 00
8961 10:00:56.147089 in-data: 00
8962 10:00:56.150427 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8963 10:00:56.155005 in-header: 03 fd 00 00 00 00 00 00
8964 10:00:56.158397 in-data:
8965 10:00:56.161610 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8966 10:00:56.165794 in-header: 03 fc 00 00 01 00 00 00
8967 10:00:56.169207 in-data: 00
8968 10:00:56.172678 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8969 10:00:56.178293 in-header: 03 fd 00 00 00 00 00 00
8970 10:00:56.181426 in-data:
8971 10:00:56.184947 [SSUSB] Setting up USB HOST controller...
8972 10:00:56.188274 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8973 10:00:56.191694 [SSUSB] phy power-on done.
8974 10:00:56.194976 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8975 10:00:56.201334 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8976 10:00:56.204654 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8977 10:00:56.211322 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8978 10:00:56.217824 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
8979 10:00:56.224336 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8980 10:00:56.230928 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8981 10:00:56.237898 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
8982 10:00:56.241180 SPM: binary array size = 0x9dc
8983 10:00:56.244198 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8984 10:00:56.250912 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8985 10:00:56.257782 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8986 10:00:56.264323 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8987 10:00:56.267414 configure_display: Starting display init
8988 10:00:56.301323 anx7625_power_on_init: Init interface.
8989 10:00:56.304689 anx7625_disable_pd_protocol: Disabled PD feature.
8990 10:00:56.308270 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8991 10:00:56.335804 anx7625_start_dp_work: Secure OCM version=00
8992 10:00:56.339076 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8993 10:00:56.353756 sp_tx_get_edid_block: EDID Block = 1
8994 10:00:56.456685 Extracted contents:
8995 10:00:56.459795 header: 00 ff ff ff ff ff ff 00
8996 10:00:56.463042 serial number: 26 cf 7d 05 00 00 00 00 00 1e
8997 10:00:56.466516 version: 01 04
8998 10:00:56.469377 basic params: 95 1f 11 78 0a
8999 10:00:56.473088 chroma info: 76 90 94 55 54 90 27 21 50 54
9000 10:00:56.476292 established: 00 00 00
9001 10:00:56.482966 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9002 10:00:56.489251 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9003 10:00:56.492584 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9004 10:00:56.499289 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9005 10:00:56.505649 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9006 10:00:56.509103 extensions: 00
9007 10:00:56.509609 checksum: fb
9008 10:00:56.509940
9009 10:00:56.515886 Manufacturer: IVO Model 57d Serial Number 0
9010 10:00:56.516394 Made week 0 of 2020
9011 10:00:56.518996 EDID version: 1.4
9012 10:00:56.519515 Digital display
9013 10:00:56.522178 6 bits per primary color channel
9014 10:00:56.525538 DisplayPort interface
9015 10:00:56.525954 Maximum image size: 31 cm x 17 cm
9016 10:00:56.528645 Gamma: 220%
9017 10:00:56.529061 Check DPMS levels
9018 10:00:56.535841 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9019 10:00:56.539076 First detailed timing is preferred timing
9020 10:00:56.539622 Established timings supported:
9021 10:00:56.541905 Standard timings supported:
9022 10:00:56.545169 Detailed timings
9023 10:00:56.548591 Hex of detail: 383680a07038204018303c0035ae10000019
9024 10:00:56.555448 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9025 10:00:56.558863 0780 0798 07c8 0820 hborder 0
9026 10:00:56.561822 0438 043b 0447 0458 vborder 0
9027 10:00:56.565193 -hsync -vsync
9028 10:00:56.565605 Did detailed timing
9029 10:00:56.571673 Hex of detail: 000000000000000000000000000000000000
9030 10:00:56.575051 Manufacturer-specified data, tag 0
9031 10:00:56.577998 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9032 10:00:56.581415 ASCII string: InfoVision
9033 10:00:56.584709 Hex of detail: 000000fe00523134304e574635205248200a
9034 10:00:56.588038 ASCII string: R140NWF5 RH
9035 10:00:56.588216 Checksum
9036 10:00:56.591093 Checksum: 0xfb (valid)
9037 10:00:56.595032 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9038 10:00:56.598170 DSI data_rate: 832800000 bps
9039 10:00:56.604649 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9040 10:00:56.608285 anx7625_parse_edid: pixelclock(138800).
9041 10:00:56.611777 hactive(1920), hsync(48), hfp(24), hbp(88)
9042 10:00:56.614860 vactive(1080), vsync(12), vfp(3), vbp(17)
9043 10:00:56.618244 anx7625_dsi_config: config dsi.
9044 10:00:56.624588 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9045 10:00:56.638444 anx7625_dsi_config: success to config DSI
9046 10:00:56.641837 anx7625_dp_start: MIPI phy setup OK.
9047 10:00:56.644865 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9048 10:00:56.648398 mtk_ddp_mode_set invalid vrefresh 60
9049 10:00:56.651574 main_disp_path_setup
9050 10:00:56.651987 ovl_layer_smi_id_en
9051 10:00:56.654795 ovl_layer_smi_id_en
9052 10:00:56.655213 ccorr_config
9053 10:00:56.655538 aal_config
9054 10:00:56.658354 gamma_config
9055 10:00:56.658778 postmask_config
9056 10:00:56.661944 dither_config
9057 10:00:56.664745 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9058 10:00:56.671616 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9059 10:00:56.674536 Root Device init finished in 554 msecs
9060 10:00:56.677907 CPU_CLUSTER: 0 init
9061 10:00:56.684547 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9062 10:00:56.687770 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9063 10:00:56.691051 APU_MBOX 0x190000b0 = 0x10001
9064 10:00:56.694352 APU_MBOX 0x190001b0 = 0x10001
9065 10:00:56.697763 APU_MBOX 0x190005b0 = 0x10001
9066 10:00:56.700797 APU_MBOX 0x190006b0 = 0x10001
9067 10:00:56.704406 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9068 10:00:56.716845 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9069 10:00:56.729435 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9070 10:00:56.736372 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9071 10:00:56.747636 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9072 10:00:56.756848 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9073 10:00:56.760276 CPU_CLUSTER: 0 init finished in 81 msecs
9074 10:00:56.763642 Devices initialized
9075 10:00:56.767476 Show all devs... After init.
9076 10:00:56.767960 Root Device: enabled 1
9077 10:00:56.770190 CPU_CLUSTER: 0: enabled 1
9078 10:00:56.773656 CPU: 00: enabled 1
9079 10:00:56.777200 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9080 10:00:56.780671 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9081 10:00:56.783881 ELOG: NV offset 0x57f000 size 0x1000
9082 10:00:56.790548 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9083 10:00:56.797071 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9084 10:00:56.800385 ELOG: Event(17) added with size 13 at 2023-11-24 10:00:56 UTC
9085 10:00:56.807053 out: cmd=0x121: 03 db 21 01 00 00 00 00
9086 10:00:56.810340 in-header: 03 db 00 00 2c 00 00 00
9087 10:00:56.823426 in-data: 88 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9088 10:00:56.826498 ELOG: Event(A1) added with size 10 at 2023-11-24 10:00:56 UTC
9089 10:00:56.833505 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9090 10:00:56.839552 ELOG: Event(A0) added with size 9 at 2023-11-24 10:00:56 UTC
9091 10:00:56.843250 elog_add_boot_reason: Logged dev mode boot
9092 10:00:56.849611 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9093 10:00:56.850027 Finalize devices...
9094 10:00:56.853036 Devices finalized
9095 10:00:56.856402 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9096 10:00:56.859820 Writing coreboot table at 0xffe64000
9097 10:00:56.866253 0. 000000000010a000-0000000000113fff: RAMSTAGE
9098 10:00:56.869887 1. 0000000040000000-00000000400fffff: RAM
9099 10:00:56.873400 2. 0000000040100000-000000004032afff: RAMSTAGE
9100 10:00:56.876676 3. 000000004032b000-00000000545fffff: RAM
9101 10:00:56.879674 4. 0000000054600000-000000005465ffff: BL31
9102 10:00:56.886564 5. 0000000054660000-00000000ffe63fff: RAM
9103 10:00:56.889383 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9104 10:00:56.893096 7. 0000000100000000-000000013fffffff: RAM
9105 10:00:56.896343 Passing 5 GPIOs to payload:
9106 10:00:56.899917 NAME | PORT | POLARITY | VALUE
9107 10:00:56.906297 EC in RW | 0x000000aa | low | undefined
9108 10:00:56.909268 EC interrupt | 0x00000005 | low | undefined
9109 10:00:56.916010 TPM interrupt | 0x000000ab | high | undefined
9110 10:00:56.919264 SD card detect | 0x00000011 | high | undefined
9111 10:00:56.922509 speaker enable | 0x00000093 | high | undefined
9112 10:00:56.928797 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9113 10:00:56.932308 in-header: 03 f8 00 00 02 00 00 00
9114 10:00:56.932772 in-data: 03 00
9115 10:00:56.935864 ADC[4]: Raw value=668590 ID=5
9116 10:00:56.939388 ADC[3]: Raw value=212549 ID=1
9117 10:00:56.939918 RAM Code: 0x51
9118 10:00:56.942255 ADC[6]: Raw value=74778 ID=0
9119 10:00:56.945863 ADC[5]: Raw value=211444 ID=1
9120 10:00:56.946376 SKU Code: 0x1
9121 10:00:56.952293 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7ea
9122 10:00:56.952789 coreboot table: 964 bytes.
9123 10:00:56.955978 IMD ROOT 0. 0xfffff000 0x00001000
9124 10:00:56.959051 IMD SMALL 1. 0xffffe000 0x00001000
9125 10:00:56.962122 RO MCACHE 2. 0xffffc000 0x00001104
9126 10:00:56.965921 CONSOLE 3. 0xfff7c000 0x00080000
9127 10:00:56.969072 FMAP 4. 0xfff7b000 0x00000452
9128 10:00:56.972588 TIME STAMP 5. 0xfff7a000 0x00000910
9129 10:00:56.975508 VBOOT WORK 6. 0xfff66000 0x00014000
9130 10:00:56.978550 RAMOOPS 7. 0xffe66000 0x00100000
9131 10:00:56.982282 COREBOOT 8. 0xffe64000 0x00002000
9132 10:00:56.985261 IMD small region:
9133 10:00:56.988757 IMD ROOT 0. 0xffffec00 0x00000400
9134 10:00:56.992258 VPD 1. 0xffffeb80 0x0000006c
9135 10:00:56.995158 MMC STATUS 2. 0xffffeb60 0x00000004
9136 10:00:57.002051 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9137 10:00:57.002632 Probing TPM: done!
9138 10:00:57.008568 Connected to device vid:did:rid of 1ae0:0028:00
9139 10:00:57.015288 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9140 10:00:57.018395 Initialized TPM device CR50 revision 0
9141 10:00:57.021763 Checking cr50 for pending updates
9142 10:00:57.027425 Reading cr50 TPM mode
9143 10:00:57.035966 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9144 10:00:57.042804 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9145 10:00:57.082677 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9146 10:00:57.086172 Checking segment from ROM address 0x40100000
9147 10:00:57.089270 Checking segment from ROM address 0x4010001c
9148 10:00:57.096169 Loading segment from ROM address 0x40100000
9149 10:00:57.096761 code (compression=0)
9150 10:00:57.105919 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9151 10:00:57.112870 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9152 10:00:57.113168 it's not compressed!
9153 10:00:57.119487 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9154 10:00:57.122580 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9155 10:00:57.143701 Loading segment from ROM address 0x4010001c
9156 10:00:57.144100 Entry Point 0x80000000
9157 10:00:57.146559 Loaded segments
9158 10:00:57.149612 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9159 10:00:57.156598 Jumping to boot code at 0x80000000(0xffe64000)
9160 10:00:57.162960 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9161 10:00:57.169520 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9162 10:00:57.177530 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9163 10:00:57.180867 Checking segment from ROM address 0x40100000
9164 10:00:57.184125 Checking segment from ROM address 0x4010001c
9165 10:00:57.190813 Loading segment from ROM address 0x40100000
9166 10:00:57.191238 code (compression=1)
9167 10:00:57.197523 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9168 10:00:57.207386 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9169 10:00:57.207811 using LZMA
9170 10:00:57.215986 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9171 10:00:57.222617 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9172 10:00:57.225847 Loading segment from ROM address 0x4010001c
9173 10:00:57.226267 Entry Point 0x54601000
9174 10:00:57.229184 Loaded segments
9175 10:00:57.232595 NOTICE: MT8192 bl31_setup
9176 10:00:57.239873 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9177 10:00:57.243123 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9178 10:00:57.246390 WARNING: region 0:
9179 10:00:57.249364 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9180 10:00:57.249801 WARNING: region 1:
9181 10:00:57.256367 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9182 10:00:57.259596 WARNING: region 2:
9183 10:00:57.263170 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9184 10:00:57.266207 WARNING: region 3:
9185 10:00:57.269456 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9186 10:00:57.272826 WARNING: region 4:
9187 10:00:57.279424 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9188 10:00:57.279842 WARNING: region 5:
9189 10:00:57.282433 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9190 10:00:57.285890 WARNING: region 6:
9191 10:00:57.289175 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9192 10:00:57.292444 WARNING: region 7:
9193 10:00:57.295959 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9194 10:00:57.302740 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9195 10:00:57.306038 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9196 10:00:57.309243 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9197 10:00:57.315969 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9198 10:00:57.319627 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9199 10:00:57.322762 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9200 10:00:57.329160 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9201 10:00:57.332708 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9202 10:00:57.339066 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9203 10:00:57.342682 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9204 10:00:57.346204 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9205 10:00:57.352239 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9206 10:00:57.355632 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9207 10:00:57.358974 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9208 10:00:57.366095 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9209 10:00:57.368848 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9210 10:00:57.375738 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9211 10:00:57.378824 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9212 10:00:57.382627 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9213 10:00:57.389126 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9214 10:00:57.392415 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9215 10:00:57.398975 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9216 10:00:57.402370 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9217 10:00:57.405359 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9218 10:00:57.412293 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9219 10:00:57.415882 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9220 10:00:57.422434 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9221 10:00:57.425933 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9222 10:00:57.428915 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9223 10:00:57.435670 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9224 10:00:57.439104 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9225 10:00:57.442358 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9226 10:00:57.449019 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9227 10:00:57.452413 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9228 10:00:57.455378 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9229 10:00:57.458756 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9230 10:00:57.465347 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9231 10:00:57.468920 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9232 10:00:57.472455 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9233 10:00:57.476053 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9234 10:00:57.482734 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9235 10:00:57.485766 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9236 10:00:57.488998 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9237 10:00:57.492430 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9238 10:00:57.499354 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9239 10:00:57.502578 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9240 10:00:57.505565 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9241 10:00:57.512495 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9242 10:00:57.515723 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9243 10:00:57.518989 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9244 10:00:57.526121 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9245 10:00:57.528864 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9246 10:00:57.535684 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9247 10:00:57.539091 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9248 10:00:57.542646 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9249 10:00:57.548818 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9250 10:00:57.552119 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9251 10:00:57.558830 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9252 10:00:57.562528 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9253 10:00:57.568655 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9254 10:00:57.572199 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9255 10:00:57.579199 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9256 10:00:57.582604 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9257 10:00:57.585483 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9258 10:00:57.592213 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9259 10:00:57.595578 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9260 10:00:57.602020 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9261 10:00:57.605395 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9262 10:00:57.612403 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9263 10:00:57.615384 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9264 10:00:57.619044 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9265 10:00:57.625500 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9266 10:00:57.628900 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9267 10:00:57.635348 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9268 10:00:57.638583 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9269 10:00:57.645588 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9270 10:00:57.648635 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9271 10:00:57.652025 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9272 10:00:57.658645 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9273 10:00:57.661969 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9274 10:00:57.668846 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9275 10:00:57.672264 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9276 10:00:57.678829 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9277 10:00:57.681854 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9278 10:00:57.685490 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9279 10:00:57.692380 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9280 10:00:57.695480 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9281 10:00:57.702016 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9282 10:00:57.705288 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9283 10:00:57.712244 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9284 10:00:57.715386 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9285 10:00:57.718669 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9286 10:00:57.725479 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9287 10:00:57.728484 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9288 10:00:57.735211 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9289 10:00:57.738411 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9290 10:00:57.745383 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9291 10:00:57.748574 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9292 10:00:57.751855 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9293 10:00:57.755220 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9294 10:00:57.761933 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9295 10:00:57.765369 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9296 10:00:57.768625 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9297 10:00:57.775170 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9298 10:00:57.778446 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9299 10:00:57.785123 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9300 10:00:57.788652 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9301 10:00:57.791881 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9302 10:00:57.798508 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9303 10:00:57.801961 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9304 10:00:57.808214 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9305 10:00:57.811989 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9306 10:00:57.815465 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9307 10:00:57.821627 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9308 10:00:57.824931 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9309 10:00:57.828475 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9310 10:00:57.835007 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9311 10:00:57.838449 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9312 10:00:57.841866 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9313 10:00:57.848961 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9314 10:00:57.851593 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9315 10:00:57.855306 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9316 10:00:57.858350 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9317 10:00:57.865129 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9318 10:00:57.868616 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9319 10:00:57.871704 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9320 10:00:57.878634 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9321 10:00:57.881744 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9322 10:00:57.888661 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9323 10:00:57.892207 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9324 10:00:57.895095 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9325 10:00:57.901833 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9326 10:00:57.904885 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9327 10:00:57.911475 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9328 10:00:57.914704 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9329 10:00:57.918140 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9330 10:00:57.925030 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9331 10:00:57.928186 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9332 10:00:57.931323 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9333 10:00:57.938159 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9334 10:00:57.941310 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9335 10:00:57.948367 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9336 10:00:57.951180 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9337 10:00:57.954570 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9338 10:00:57.961352 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9339 10:00:57.964696 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9340 10:00:57.971940 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9341 10:00:57.975018 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9342 10:00:57.978079 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9343 10:00:57.984912 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9344 10:00:57.988263 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9345 10:00:57.991512 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9346 10:00:57.997880 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9347 10:00:58.001150 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9348 10:00:58.008014 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9349 10:00:58.011312 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9350 10:00:58.014756 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9351 10:00:58.021204 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9352 10:00:58.024848 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9353 10:00:58.031596 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9354 10:00:58.034388 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9355 10:00:58.037612 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9356 10:00:58.044587 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9357 10:00:58.048033 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9358 10:00:58.054312 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9359 10:00:58.057637 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9360 10:00:58.061174 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9361 10:00:58.067961 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9362 10:00:58.071021 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9363 10:00:58.077489 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9364 10:00:58.081055 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9365 10:00:58.084163 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9366 10:00:58.090643 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9367 10:00:58.094197 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9368 10:00:58.100497 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9369 10:00:58.103958 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9370 10:00:58.107274 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9371 10:00:58.113789 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9372 10:00:58.117480 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9373 10:00:58.123742 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9374 10:00:58.127267 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9375 10:00:58.130562 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9376 10:00:58.137089 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9377 10:00:58.140177 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9378 10:00:58.147206 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9379 10:00:58.150227 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9380 10:00:58.153597 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9381 10:00:58.160184 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9382 10:00:58.163687 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9383 10:00:58.170421 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9384 10:00:58.173568 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9385 10:00:58.176957 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9386 10:00:58.183503 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9387 10:00:58.187068 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9388 10:00:58.193183 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9389 10:00:58.196400 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9390 10:00:58.203569 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9391 10:00:58.206801 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9392 10:00:58.209863 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9393 10:00:58.216892 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9394 10:00:58.219972 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9395 10:00:58.226610 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9396 10:00:58.229735 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9397 10:00:58.232918 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9398 10:00:58.239738 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9399 10:00:58.243292 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9400 10:00:58.249729 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9401 10:00:58.252935 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9402 10:00:58.259382 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9403 10:00:58.262885 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9404 10:00:58.266112 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9405 10:00:58.272569 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9406 10:00:58.276010 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9407 10:00:58.282207 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9408 10:00:58.285519 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9409 10:00:58.292452 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9410 10:00:58.295645 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9411 10:00:58.298865 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9412 10:00:58.305771 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9413 10:00:58.308867 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9414 10:00:58.315757 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9415 10:00:58.318871 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9416 10:00:58.322429 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9417 10:00:58.328894 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9418 10:00:58.332064 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9419 10:00:58.339161 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9420 10:00:58.341874 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9421 10:00:58.349143 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9422 10:00:58.351731 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9423 10:00:58.355244 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9424 10:00:58.358440 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9425 10:00:58.365109 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9426 10:00:58.368180 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9427 10:00:58.371536 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9428 10:00:58.378470 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9429 10:00:58.381885 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9430 10:00:58.384817 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9431 10:00:58.391830 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9432 10:00:58.395437 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9433 10:00:58.398321 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9434 10:00:58.405304 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9435 10:00:58.408150 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9436 10:00:58.415170 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9437 10:00:58.418620 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9438 10:00:58.421570 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9439 10:00:58.428193 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9440 10:00:58.431570 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9441 10:00:58.434549 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9442 10:00:58.441051 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9443 10:00:58.444589 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9444 10:00:58.451317 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9445 10:00:58.454504 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9446 10:00:58.457640 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9447 10:00:58.464304 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9448 10:00:58.467644 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9449 10:00:58.471037 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9450 10:00:58.477446 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9451 10:00:58.480689 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9452 10:00:58.484189 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9453 10:00:58.491000 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9454 10:00:58.494443 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9455 10:00:58.500905 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9456 10:00:58.504365 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9457 10:00:58.507498 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9458 10:00:58.514346 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9459 10:00:58.517499 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9460 10:00:58.520878 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9461 10:00:58.527880 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9462 10:00:58.530626 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9463 10:00:58.533761 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9464 10:00:58.540471 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9465 10:00:58.543912 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9466 10:00:58.547056 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9467 10:00:58.550285 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9468 10:00:58.553913 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9469 10:00:58.560369 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9470 10:00:58.563414 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9471 10:00:58.567201 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9472 10:00:58.570524 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9473 10:00:58.576969 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9474 10:00:58.580592 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9475 10:00:58.583644 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9476 10:00:58.590317 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9477 10:00:58.593366 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9478 10:00:58.600158 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9479 10:00:58.603599 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9480 10:00:58.610385 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9481 10:00:58.613316 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9482 10:00:58.616629 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9483 10:00:58.622981 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9484 10:00:58.626500 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9485 10:00:58.633501 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9486 10:00:58.636389 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9487 10:00:58.639613 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9488 10:00:58.646379 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9489 10:00:58.649529 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9490 10:00:58.655833 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9491 10:00:58.659298 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9492 10:00:58.662809 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9493 10:00:58.669443 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9494 10:00:58.672728 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9495 10:00:58.679107 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9496 10:00:58.682332 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9497 10:00:58.689062 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9498 10:00:58.692612 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9499 10:00:58.696047 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9500 10:00:58.702323 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9501 10:00:58.705784 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9502 10:00:58.712048 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9503 10:00:58.715720 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9504 10:00:58.722165 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9505 10:00:58.725392 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9506 10:00:58.728467 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9507 10:00:58.735320 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9508 10:00:58.738602 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9509 10:00:58.745186 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9510 10:00:58.748683 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9511 10:00:58.751892 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9512 10:00:58.758448 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9513 10:00:58.761817 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9514 10:00:58.768413 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9515 10:00:58.771992 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9516 10:00:58.775456 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9517 10:00:58.781821 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9518 10:00:58.785301 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9519 10:00:58.791394 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9520 10:00:58.795213 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9521 10:00:58.801359 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9522 10:00:58.804674 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9523 10:00:58.807985 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9524 10:00:58.814443 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9525 10:00:58.817575 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9526 10:00:58.824740 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9527 10:00:58.827842 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9528 10:00:58.833977 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9529 10:00:58.837986 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9530 10:00:58.840948 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9531 10:00:58.847657 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9532 10:00:58.851147 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9533 10:00:58.857256 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9534 10:00:58.860563 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9535 10:00:58.864028 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9536 10:00:58.870794 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9537 10:00:58.874605 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9538 10:00:58.880759 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9539 10:00:58.884116 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9540 10:00:58.887077 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9541 10:00:58.893698 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9542 10:00:58.896942 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9543 10:00:58.903915 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9544 10:00:58.906945 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9545 10:00:58.913582 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9546 10:00:58.917110 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9547 10:00:58.920057 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9548 10:00:58.926850 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9549 10:00:58.930117 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9550 10:00:58.936707 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9551 10:00:58.940084 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9552 10:00:58.946639 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9553 10:00:58.950161 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9554 10:00:58.956560 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9555 10:00:58.959578 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9556 10:00:58.962874 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9557 10:00:58.969794 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9558 10:00:58.973385 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9559 10:00:58.979988 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9560 10:00:58.982816 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9561 10:00:58.989607 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9562 10:00:58.993164 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9563 10:00:58.995883 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9564 10:00:59.002689 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9565 10:00:59.005867 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9566 10:00:59.012572 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9567 10:00:59.016010 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9568 10:00:59.022768 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9569 10:00:59.026128 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9570 10:00:59.032858 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9571 10:00:59.035743 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9572 10:00:59.039071 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9573 10:00:59.045906 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9574 10:00:59.049227 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9575 10:00:59.055854 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9576 10:00:59.058917 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9577 10:00:59.065627 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9578 10:00:59.069024 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9579 10:00:59.072173 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9580 10:00:59.079021 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9581 10:00:59.082364 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9582 10:00:59.088843 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9583 10:00:59.091959 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9584 10:00:59.099073 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9585 10:00:59.101979 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9586 10:00:59.108470 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9587 10:00:59.111906 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9588 10:00:59.115128 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9589 10:00:59.122082 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9590 10:00:59.125090 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9591 10:00:59.132068 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9592 10:00:59.135200 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9593 10:00:59.142045 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9594 10:00:59.145450 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9595 10:00:59.148610 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9596 10:00:59.155036 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9597 10:00:59.158400 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9598 10:00:59.165008 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9599 10:00:59.168088 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9600 10:00:59.174842 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9601 10:00:59.178116 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9602 10:00:59.184576 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9603 10:00:59.187969 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9604 10:00:59.194392 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9605 10:00:59.197783 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9606 10:00:59.204662 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9607 10:00:59.208134 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9608 10:00:59.214339 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9609 10:00:59.218006 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9610 10:00:59.224672 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9611 10:00:59.227896 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9612 10:00:59.234271 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9613 10:00:59.237516 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9614 10:00:59.240878 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9615 10:00:59.247352 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9616 10:00:59.250681 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9617 10:00:59.257652 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9618 10:00:59.260624 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9619 10:00:59.267296 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9620 10:00:59.274134 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9621 10:00:59.277170 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9622 10:00:59.283829 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9623 10:00:59.287006 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9624 10:00:59.294172 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9625 10:00:59.297355 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9626 10:00:59.303710 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9627 10:00:59.307566 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9628 10:00:59.310577 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9629 10:00:59.314135 INFO: [APUAPC] vio 0
9630 10:00:59.317363 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9631 10:00:59.323970 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9632 10:00:59.327387 INFO: [APUAPC] D0_APC_0: 0x400510
9633 10:00:59.330601 INFO: [APUAPC] D0_APC_1: 0x0
9634 10:00:59.334002 INFO: [APUAPC] D0_APC_2: 0x1540
9635 10:00:59.334561 INFO: [APUAPC] D0_APC_3: 0x0
9636 10:00:59.337364 INFO: [APUAPC] D1_APC_0: 0xffffffff
9637 10:00:59.343477 INFO: [APUAPC] D1_APC_1: 0xffffffff
9638 10:00:59.347034 INFO: [APUAPC] D1_APC_2: 0x3fffff
9639 10:00:59.347449 INFO: [APUAPC] D1_APC_3: 0x0
9640 10:00:59.350077 INFO: [APUAPC] D2_APC_0: 0xffffffff
9641 10:00:59.353473 INFO: [APUAPC] D2_APC_1: 0xffffffff
9642 10:00:59.356966 INFO: [APUAPC] D2_APC_2: 0x3fffff
9643 10:00:59.360246 INFO: [APUAPC] D2_APC_3: 0x0
9644 10:00:59.363457 INFO: [APUAPC] D3_APC_0: 0xffffffff
9645 10:00:59.366886 INFO: [APUAPC] D3_APC_1: 0xffffffff
9646 10:00:59.370175 INFO: [APUAPC] D3_APC_2: 0x3fffff
9647 10:00:59.373469 INFO: [APUAPC] D3_APC_3: 0x0
9648 10:00:59.377038 INFO: [APUAPC] D4_APC_0: 0xffffffff
9649 10:00:59.380322 INFO: [APUAPC] D4_APC_1: 0xffffffff
9650 10:00:59.383615 INFO: [APUAPC] D4_APC_2: 0x3fffff
9651 10:00:59.386902 INFO: [APUAPC] D4_APC_3: 0x0
9652 10:00:59.390008 INFO: [APUAPC] D5_APC_0: 0xffffffff
9653 10:00:59.393313 INFO: [APUAPC] D5_APC_1: 0xffffffff
9654 10:00:59.396754 INFO: [APUAPC] D5_APC_2: 0x3fffff
9655 10:00:59.399938 INFO: [APUAPC] D5_APC_3: 0x0
9656 10:00:59.403226 INFO: [APUAPC] D6_APC_0: 0xffffffff
9657 10:00:59.406754 INFO: [APUAPC] D6_APC_1: 0xffffffff
9658 10:00:59.410210 INFO: [APUAPC] D6_APC_2: 0x3fffff
9659 10:00:59.413234 INFO: [APUAPC] D6_APC_3: 0x0
9660 10:00:59.416396 INFO: [APUAPC] D7_APC_0: 0xffffffff
9661 10:00:59.420197 INFO: [APUAPC] D7_APC_1: 0xffffffff
9662 10:00:59.423387 INFO: [APUAPC] D7_APC_2: 0x3fffff
9663 10:00:59.426848 INFO: [APUAPC] D7_APC_3: 0x0
9664 10:00:59.429934 INFO: [APUAPC] D8_APC_0: 0xffffffff
9665 10:00:59.433128 INFO: [APUAPC] D8_APC_1: 0xffffffff
9666 10:00:59.436360 INFO: [APUAPC] D8_APC_2: 0x3fffff
9667 10:00:59.439851 INFO: [APUAPC] D8_APC_3: 0x0
9668 10:00:59.443051 INFO: [APUAPC] D9_APC_0: 0xffffffff
9669 10:00:59.446200 INFO: [APUAPC] D9_APC_1: 0xffffffff
9670 10:00:59.449510 INFO: [APUAPC] D9_APC_2: 0x3fffff
9671 10:00:59.453031 INFO: [APUAPC] D9_APC_3: 0x0
9672 10:00:59.456434 INFO: [APUAPC] D10_APC_0: 0xffffffff
9673 10:00:59.459370 INFO: [APUAPC] D10_APC_1: 0xffffffff
9674 10:00:59.463174 INFO: [APUAPC] D10_APC_2: 0x3fffff
9675 10:00:59.465992 INFO: [APUAPC] D10_APC_3: 0x0
9676 10:00:59.469631 INFO: [APUAPC] D11_APC_0: 0xffffffff
9677 10:00:59.472940 INFO: [APUAPC] D11_APC_1: 0xffffffff
9678 10:00:59.475947 INFO: [APUAPC] D11_APC_2: 0x3fffff
9679 10:00:59.479557 INFO: [APUAPC] D11_APC_3: 0x0
9680 10:00:59.482662 INFO: [APUAPC] D12_APC_0: 0xffffffff
9681 10:00:59.486604 INFO: [APUAPC] D12_APC_1: 0xffffffff
9682 10:00:59.489340 INFO: [APUAPC] D12_APC_2: 0x3fffff
9683 10:00:59.492796 INFO: [APUAPC] D12_APC_3: 0x0
9684 10:00:59.496083 INFO: [APUAPC] D13_APC_0: 0xffffffff
9685 10:00:59.499660 INFO: [APUAPC] D13_APC_1: 0xffffffff
9686 10:00:59.502931 INFO: [APUAPC] D13_APC_2: 0x3fffff
9687 10:00:59.506333 INFO: [APUAPC] D13_APC_3: 0x0
9688 10:00:59.509540 INFO: [APUAPC] D14_APC_0: 0xffffffff
9689 10:00:59.513053 INFO: [APUAPC] D14_APC_1: 0xffffffff
9690 10:00:59.516198 INFO: [APUAPC] D14_APC_2: 0x3fffff
9691 10:00:59.519351 INFO: [APUAPC] D14_APC_3: 0x0
9692 10:00:59.523144 INFO: [APUAPC] D15_APC_0: 0xffffffff
9693 10:00:59.526070 INFO: [APUAPC] D15_APC_1: 0xffffffff
9694 10:00:59.529555 INFO: [APUAPC] D15_APC_2: 0x3fffff
9695 10:00:59.532471 INFO: [APUAPC] D15_APC_3: 0x0
9696 10:00:59.536111 INFO: [APUAPC] APC_CON: 0x4
9697 10:00:59.539492 INFO: [NOCDAPC] D0_APC_0: 0x0
9698 10:00:59.542942 INFO: [NOCDAPC] D0_APC_1: 0x0
9699 10:00:59.543492 INFO: [NOCDAPC] D1_APC_0: 0x0
9700 10:00:59.546162 INFO: [NOCDAPC] D1_APC_1: 0xfff
9701 10:00:59.549120 INFO: [NOCDAPC] D2_APC_0: 0x0
9702 10:00:59.552342 INFO: [NOCDAPC] D2_APC_1: 0xfff
9703 10:00:59.555611 INFO: [NOCDAPC] D3_APC_0: 0x0
9704 10:00:59.558989 INFO: [NOCDAPC] D3_APC_1: 0xfff
9705 10:00:59.562383 INFO: [NOCDAPC] D4_APC_0: 0x0
9706 10:00:59.565466 INFO: [NOCDAPC] D4_APC_1: 0xfff
9707 10:00:59.568923 INFO: [NOCDAPC] D5_APC_0: 0x0
9708 10:00:59.572218 INFO: [NOCDAPC] D5_APC_1: 0xfff
9709 10:00:59.575647 INFO: [NOCDAPC] D6_APC_0: 0x0
9710 10:00:59.576205 INFO: [NOCDAPC] D6_APC_1: 0xfff
9711 10:00:59.578831 INFO: [NOCDAPC] D7_APC_0: 0x0
9712 10:00:59.582349 INFO: [NOCDAPC] D7_APC_1: 0xfff
9713 10:00:59.585752 INFO: [NOCDAPC] D8_APC_0: 0x0
9714 10:00:59.588847 INFO: [NOCDAPC] D8_APC_1: 0xfff
9715 10:00:59.592169 INFO: [NOCDAPC] D9_APC_0: 0x0
9716 10:00:59.595772 INFO: [NOCDAPC] D9_APC_1: 0xfff
9717 10:00:59.599023 INFO: [NOCDAPC] D10_APC_0: 0x0
9718 10:00:59.602337 INFO: [NOCDAPC] D10_APC_1: 0xfff
9719 10:00:59.605462 INFO: [NOCDAPC] D11_APC_0: 0x0
9720 10:00:59.608814 INFO: [NOCDAPC] D11_APC_1: 0xfff
9721 10:00:59.611933 INFO: [NOCDAPC] D12_APC_0: 0x0
9722 10:00:59.615286 INFO: [NOCDAPC] D12_APC_1: 0xfff
9723 10:00:59.615713 INFO: [NOCDAPC] D13_APC_0: 0x0
9724 10:00:59.618606 INFO: [NOCDAPC] D13_APC_1: 0xfff
9725 10:00:59.621890 INFO: [NOCDAPC] D14_APC_0: 0x0
9726 10:00:59.625206 INFO: [NOCDAPC] D14_APC_1: 0xfff
9727 10:00:59.628820 INFO: [NOCDAPC] D15_APC_0: 0x0
9728 10:00:59.631748 INFO: [NOCDAPC] D15_APC_1: 0xfff
9729 10:00:59.635198 INFO: [NOCDAPC] APC_CON: 0x4
9730 10:00:59.638434 INFO: [APUAPC] set_apusys_apc done
9731 10:00:59.641793 INFO: [DEVAPC] devapc_init done
9732 10:00:59.645285 INFO: GICv3 without legacy support detected.
9733 10:00:59.648734 INFO: ARM GICv3 driver initialized in EL3
9734 10:00:59.655010 INFO: Maximum SPI INTID supported: 639
9735 10:00:59.658415 INFO: BL31: Initializing runtime services
9736 10:00:59.665033 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9737 10:00:59.665446 INFO: SPM: enable CPC mode
9738 10:00:59.671973 INFO: mcdi ready for mcusys-off-idle and system suspend
9739 10:00:59.675053 INFO: BL31: Preparing for EL3 exit to normal world
9740 10:00:59.678281 INFO: Entry point address = 0x80000000
9741 10:00:59.681674 INFO: SPSR = 0x8
9742 10:00:59.687452
9743 10:00:59.687856
9744 10:00:59.688175
9745 10:00:59.690536 Starting depthcharge on Spherion...
9746 10:00:59.690942
9747 10:00:59.691262 Wipe memory regions:
9748 10:00:59.691558
9749 10:00:59.693887 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9750 10:00:59.694359 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9751 10:00:59.694765 Setting prompt string to ['asurada:']
9752 10:00:59.695200 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9753 10:00:59.695852 [0x00000040000000, 0x00000054600000)
9754 10:00:59.816457
9755 10:00:59.817003 [0x00000054660000, 0x00000080000000)
9756 10:01:00.076812
9757 10:01:00.077360 [0x000000821a7280, 0x000000ffe64000)
9758 10:01:00.821474
9759 10:01:00.822017 [0x00000100000000, 0x00000140000000)
9760 10:01:01.202507
9761 10:01:01.205568 Initializing XHCI USB controller at 0x11200000.
9762 10:01:02.243456
9763 10:01:02.246559 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9764 10:01:02.247067
9765 10:01:02.247392
9766 10:01:02.247691
9767 10:01:02.248419 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9769 10:01:02.349524 asurada: tftpboot 192.168.201.1 12073309/tftp-deploy-djv8i3is/kernel/image.itb 12073309/tftp-deploy-djv8i3is/kernel/cmdline
9770 10:01:02.350108 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9771 10:01:02.350486 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9772 10:01:02.354617 tftpboot 192.168.201.1 12073309/tftp-deploy-djv8i3is/kernel/image.itp-deploy-djv8i3is/kernel/cmdline
9773 10:01:02.355030
9774 10:01:02.355368 Waiting for link
9775 10:01:02.515174
9776 10:01:02.515700 R8152: Initializing
9777 10:01:02.516204
9778 10:01:02.518328 Version 9 (ocp_data = 6010)
9779 10:01:02.518736
9780 10:01:02.521890 R8152: Done initializing
9781 10:01:02.522294
9782 10:01:02.522614 Adding net device
9783 10:01:04.477252
9784 10:01:04.477832 done.
9785 10:01:04.478304
9786 10:01:04.478617 MAC: 00:e0:4c:68:03:bd
9787 10:01:04.478916
9788 10:01:04.480052 Sending DHCP discover... done.
9789 10:01:04.480454
9790 10:01:04.483211 Waiting for reply... done.
9791 10:01:04.483621
9792 10:01:04.486427 Sending DHCP request... done.
9793 10:01:04.487036
9794 10:01:04.492292 Waiting for reply... done.
9795 10:01:04.492678
9796 10:01:04.492936 My ip is 192.168.201.16
9797 10:01:04.493168
9798 10:01:04.495544 The DHCP server ip is 192.168.201.1
9799 10:01:04.495896
9800 10:01:04.502140 TFTP server IP predefined by user: 192.168.201.1
9801 10:01:04.502427
9802 10:01:04.508900 Bootfile predefined by user: 12073309/tftp-deploy-djv8i3is/kernel/image.itb
9803 10:01:04.509189
9804 10:01:04.511991 Sending tftp read request... done.
9805 10:01:04.512278
9806 10:01:04.517194 Waiting for the transfer...
9807 10:01:04.517494
9808 10:01:04.820048 00000000 ################################################################
9809 10:01:04.820213
9810 10:01:05.119664 00080000 ################################################################
9811 10:01:05.119811
9812 10:01:05.412746 00100000 ################################################################
9813 10:01:05.412897
9814 10:01:05.704008 00180000 ################################################################
9815 10:01:05.704151
9816 10:01:06.003016 00200000 ################################################################
9817 10:01:06.003189
9818 10:01:06.303598 00280000 ################################################################
9819 10:01:06.303745
9820 10:01:06.606420 00300000 ################################################################
9821 10:01:06.606568
9822 10:01:06.907040 00380000 ################################################################
9823 10:01:06.907183
9824 10:01:07.205838 00400000 ################################################################
9825 10:01:07.205985
9826 10:01:07.505786 00480000 ################################################################
9827 10:01:07.505932
9828 10:01:07.806778 00500000 ################################################################
9829 10:01:07.806918
9830 10:01:08.102760 00580000 ################################################################
9831 10:01:08.102900
9832 10:01:08.402184 00600000 ################################################################
9833 10:01:08.402325
9834 10:01:08.704016 00680000 ################################################################
9835 10:01:08.704156
9836 10:01:09.005197 00700000 ################################################################
9837 10:01:09.005336
9838 10:01:09.306039 00780000 ################################################################
9839 10:01:09.306176
9840 10:01:09.604008 00800000 ################################################################
9841 10:01:09.604151
9842 10:01:09.901702 00880000 ################################################################
9843 10:01:09.901845
9844 10:01:10.197543 00900000 ################################################################
9845 10:01:10.197680
9846 10:01:10.497035 00980000 ################################################################
9847 10:01:10.497176
9848 10:01:10.796664 00a00000 ################################################################
9849 10:01:10.796805
9850 10:01:11.089539 00a80000 ################################################################
9851 10:01:11.089677
9852 10:01:11.390375 00b00000 ################################################################
9853 10:01:11.390517
9854 10:01:11.686792 00b80000 ################################################################
9855 10:01:11.686931
9856 10:01:11.974370 00c00000 ################################################################
9857 10:01:11.974513
9858 10:01:12.267630 00c80000 ################################################################
9859 10:01:12.267800
9860 10:01:12.568191 00d00000 ################################################################
9861 10:01:12.568332
9862 10:01:12.867691 00d80000 ################################################################
9863 10:01:12.867833
9864 10:01:13.170978 00e00000 ################################################################
9865 10:01:13.171119
9866 10:01:13.471877 00e80000 ################################################################
9867 10:01:13.472018
9868 10:01:13.774689 00f00000 ################################################################
9869 10:01:13.774844
9870 10:01:14.075937 00f80000 ################################################################
9871 10:01:14.076091
9872 10:01:14.369814 01000000 ################################################################
9873 10:01:14.369960
9874 10:01:14.656921 01080000 ################################################################
9875 10:01:14.657063
9876 10:01:14.954884 01100000 ################################################################
9877 10:01:14.955032
9878 10:01:15.254474 01180000 ################################################################
9879 10:01:15.254623
9880 10:01:15.549200 01200000 ################################################################
9881 10:01:15.549350
9882 10:01:15.837570 01280000 ################################################################
9883 10:01:15.837715
9884 10:01:16.133633 01300000 ################################################################
9885 10:01:16.133803
9886 10:01:16.429159 01380000 ################################################################
9887 10:01:16.429300
9888 10:01:16.719629 01400000 ################################################################
9889 10:01:16.719799
9890 10:01:17.007446 01480000 ################################################################
9891 10:01:17.007615
9892 10:01:17.278588 01500000 ################################################################
9893 10:01:17.278764
9894 10:01:17.536973 01580000 ################################################################
9895 10:01:17.537123
9896 10:01:17.797491 01600000 ################################################################
9897 10:01:17.797643
9898 10:01:18.070064 01680000 ################################################################
9899 10:01:18.070219
9900 10:01:18.365792 01700000 ################################################################
9901 10:01:18.365947
9902 10:01:18.659551 01780000 ################################################################
9903 10:01:18.659702
9904 10:01:18.955103 01800000 ################################################################
9905 10:01:18.955277
9906 10:01:19.249207 01880000 ################################################################
9907 10:01:19.249357
9908 10:01:19.546885 01900000 ################################################################
9909 10:01:19.547035
9910 10:01:19.843026 01980000 ################################################################
9911 10:01:19.843179
9912 10:01:20.136424 01a00000 ################################################################
9913 10:01:20.136613
9914 10:01:20.432520 01a80000 ################################################################
9915 10:01:20.432688
9916 10:01:20.729575 01b00000 ################################################################
9917 10:01:20.729729
9918 10:01:21.025490 01b80000 ################################################################
9919 10:01:21.025642
9920 10:01:21.320242 01c00000 ################################################################
9921 10:01:21.320391
9922 10:01:21.615509 01c80000 ################################################################
9923 10:01:21.615662
9924 10:01:21.911991 01d00000 ################################################################
9925 10:01:21.912146
9926 10:01:22.187804 01d80000 ################################################################
9927 10:01:22.188010
9928 10:01:22.439164 01e00000 ################################################################
9929 10:01:22.439317
9930 10:01:22.694249 01e80000 ################################################################
9931 10:01:22.694419
9932 10:01:22.968694 01f00000 ################################################################
9933 10:01:22.968845
9934 10:01:23.237503 01f80000 ################################################################
9935 10:01:23.237657
9936 10:01:23.501988 02000000 ################################################################
9937 10:01:23.502141
9938 10:01:23.785685 02080000 ################################################################
9939 10:01:23.785839
9940 10:01:24.061231 02100000 ################################################################
9941 10:01:24.061376
9942 10:01:24.321803 02180000 ################################################################
9943 10:01:24.321952
9944 10:01:24.584140 02200000 ################################################################
9945 10:01:24.584287
9946 10:01:24.840859 02280000 ################################################################
9947 10:01:24.841014
9948 10:01:25.097391 02300000 ################################################################
9949 10:01:25.097541
9950 10:01:25.374911 02380000 ################################################################
9951 10:01:25.375059
9952 10:01:25.640939 02400000 ################################################################
9953 10:01:25.641084
9954 10:01:25.897610 02480000 ################################################################
9955 10:01:25.897757
9956 10:01:26.175519 02500000 ################################################################
9957 10:01:26.175666
9958 10:01:26.448019 02580000 ################################################################
9959 10:01:26.448174
9960 10:01:26.705082 02600000 ################################################################
9961 10:01:26.705237
9962 10:01:26.961393 02680000 ################################################################
9963 10:01:26.961543
9964 10:01:27.217167 02700000 ################################################################
9965 10:01:27.217317
9966 10:01:27.486002 02780000 ################################################################
9967 10:01:27.486148
9968 10:01:27.751039 02800000 ################################################################
9969 10:01:27.751185
9970 10:01:28.014787 02880000 ################################################################
9971 10:01:28.014968
9972 10:01:28.258830 02900000 ################################################################
9973 10:01:28.259047
9974 10:01:28.503597 02980000 ################################################################
9975 10:01:28.503743
9976 10:01:28.758874 02a00000 ################################################################
9977 10:01:28.759019
9978 10:01:29.014855 02a80000 ################################################################
9979 10:01:29.015004
9980 10:01:29.283428 02b00000 ################################################################
9981 10:01:29.283580
9982 10:01:29.560058 02b80000 ################################################################
9983 10:01:29.560207
9984 10:01:29.852943 02c00000 ################################################################
9985 10:01:29.853081
9986 10:01:30.147224 02c80000 ################################################################
9987 10:01:30.147399
9988 10:01:30.444454 02d00000 ################################################################
9989 10:01:30.444642
9990 10:01:30.743294 02d80000 ################################################################
9991 10:01:30.743457
9992 10:01:31.110260 02e00000 ################################################################
9993 10:01:31.110401
9994 10:01:31.421226 02e80000 ################################################################
9995 10:01:31.421728
9996 10:01:31.795149 02f00000 ################################################################
9997 10:01:31.795644
9998 10:01:32.175854 02f80000 ################################################################
9999 10:01:32.176375
10000 10:01:32.559822 03000000 ################################################################
10001 10:01:32.560422
10002 10:01:32.945685 03080000 ################################################################
10003 10:01:32.946196
10004 10:01:33.337802 03100000 ################################################################
10005 10:01:33.338339
10006 10:01:33.737982 03180000 ################################################################
10007 10:01:33.738482
10008 10:01:34.139928 03200000 ################################################################
10009 10:01:34.140434
10010 10:01:34.526527 03280000 ################################################################
10011 10:01:34.527169
10012 10:01:34.919160 03300000 ################################################################
10013 10:01:34.919667
10014 10:01:35.318547 03380000 ################################################################
10015 10:01:35.319114
10016 10:01:35.742634 03400000 ################################################################
10017 10:01:35.743174
10018 10:01:36.132184 03480000 ################################################################
10019 10:01:36.132327
10020 10:01:36.483655 03500000 ################################################################
10021 10:01:36.484182
10022 10:01:36.893434 03580000 ################################################################
10023 10:01:36.893920
10024 10:01:37.284292 03600000 ################################################################
10025 10:01:37.284901
10026 10:01:37.642251 03680000 ################################################################
10027 10:01:37.642383
10028 10:01:37.924188 03700000 ################################################################
10029 10:01:37.924322
10030 10:01:38.183172 03780000 ################################################################
10031 10:01:38.183304
10032 10:01:38.464820 03800000 ################################################################
10033 10:01:38.464951
10034 10:01:38.757332 03880000 ################################################################
10035 10:01:38.757468
10036 10:01:39.033048 03900000 ################################################################
10037 10:01:39.033180
10038 10:01:39.306534 03980000 ################################################################
10039 10:01:39.306667
10040 10:01:39.588381 03a00000 ################################################################
10041 10:01:39.588531
10042 10:01:39.880016 03a80000 ################################################################
10043 10:01:39.880148
10044 10:01:40.174366 03b00000 ################################################################
10045 10:01:40.174504
10046 10:01:40.422236 03b80000 ################################################################
10047 10:01:40.422376
10048 10:01:40.709286 03c00000 ################################################################
10049 10:01:40.709454
10050 10:01:40.997238 03c80000 ################################################################
10051 10:01:40.997401
10052 10:01:41.282855 03d00000 ################################################################
10053 10:01:41.283022
10054 10:01:41.571366 03d80000 ################################################################
10055 10:01:41.571515
10056 10:01:41.829196 03e00000 ################################################################
10057 10:01:41.829329
10058 10:01:42.075779 03e80000 ################################################################
10059 10:01:42.075918
10060 10:01:42.323172 03f00000 ################################################################
10061 10:01:42.323328
10062 10:01:42.573969 03f80000 ################################################################
10063 10:01:42.574128
10064 10:01:42.780435 04000000 #################################################### done.
10065 10:01:42.780617
10066 10:01:42.783676 The bootfile was 67528298 bytes long.
10067 10:01:42.783751
10068 10:01:42.787180 Sending tftp read request... done.
10069 10:01:42.787280
10070 10:01:42.790449 Waiting for the transfer...
10071 10:01:42.790552
10072 10:01:42.790643 00000000 # done.
10073 10:01:42.790738
10074 10:01:42.800283 Command line loaded dynamically from TFTP file: 12073309/tftp-deploy-djv8i3is/kernel/cmdline
10075 10:01:42.800384
10076 10:01:42.813373 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10077 10:01:42.813456
10078 10:01:42.813520 Loading FIT.
10079 10:01:42.813580
10080 10:01:42.816580 Image ramdisk-1 has 56431441 bytes.
10081 10:01:42.816658
10082 10:01:42.819757 Image fdt-1 has 47278 bytes.
10083 10:01:42.819856
10084 10:01:42.823153 Image kernel-1 has 11047542 bytes.
10085 10:01:42.823227
10086 10:01:42.829817 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10087 10:01:42.829911
10088 10:01:42.849874 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10089 10:01:42.849957
10090 10:01:42.853069 Choosing best match conf-1 for compat google,spherion-rev3.
10091 10:01:42.858469
10092 10:01:42.862458 Connected to device vid:did:rid of 1ae0:0028:00
10093 10:01:42.869735
10094 10:01:42.872845 tpm_get_response: command 0x17b, return code 0x0
10095 10:01:42.872944
10096 10:01:42.876187 ec_init: CrosEC protocol v3 supported (256, 248)
10097 10:01:42.879347
10098 10:01:42.882560 tpm_cleanup: add release locality here.
10099 10:01:42.882658
10100 10:01:42.886105 Shutting down all USB controllers.
10101 10:01:42.886181
10102 10:01:42.889246 Removing current net device
10103 10:01:42.889320
10104 10:01:42.893064 Exiting depthcharge with code 4 at timestamp: 71458357
10105 10:01:42.893163
10106 10:01:42.896066 LZMA decompressing kernel-1 to 0x821a6718
10107 10:01:42.899179
10108 10:01:42.902721 LZMA decompressing kernel-1 to 0x40000000
10109 10:01:44.290305
10110 10:01:44.290808 jumping to kernel
10111 10:01:44.293398 end: 2.2.4 bootloader-commands (duration 00:00:45) [common]
10112 10:01:44.293924 start: 2.2.5 auto-login-action (timeout 00:03:42) [common]
10113 10:01:44.294320 Setting prompt string to ['Linux version [0-9]']
10114 10:01:44.294683 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10115 10:01:44.295043 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10116 10:01:44.341359
10117 10:01:44.344694 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10118 10:01:44.348800 start: 2.2.5.1 login-action (timeout 00:03:42) [common]
10119 10:01:44.349319 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10120 10:01:44.349781 Setting prompt string to []
10121 10:01:44.350291 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10122 10:01:44.350766 Using line separator: #'\n'#
10123 10:01:44.351302 No login prompt set.
10124 10:01:44.351759 Parsing kernel messages
10125 10:01:44.352159 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10126 10:01:44.352999 [login-action] Waiting for messages, (timeout 00:03:42)
10127 10:01:44.367746 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j22848-arm64-gcc-10-defconfig-arm64-chromebook-6q8mw) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Nov 24 09:44:51 UTC 2023
10128 10:01:44.371175 [ 0.000000] random: crng init done
10129 10:01:44.377611 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10130 10:01:44.380849 [ 0.000000] efi: UEFI not found.
10131 10:01:44.387449 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10132 10:01:44.394176 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10133 10:01:44.404299 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10134 10:01:44.413859 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10135 10:01:44.420400 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10136 10:01:44.426911 [ 0.000000] printk: bootconsole [mtk8250] enabled
10137 10:01:44.433753 [ 0.000000] NUMA: No NUMA configuration found
10138 10:01:44.440745 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10139 10:01:44.443518 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d4a00-0x13f7d6fff]
10140 10:01:44.447221 [ 0.000000] Zone ranges:
10141 10:01:44.453517 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10142 10:01:44.456945 [ 0.000000] DMA32 empty
10143 10:01:44.463294 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10144 10:01:44.466894 [ 0.000000] Movable zone start for each node
10145 10:01:44.469999 [ 0.000000] Early memory node ranges
10146 10:01:44.476545 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10147 10:01:44.483163 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10148 10:01:44.490040 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10149 10:01:44.496763 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10150 10:01:44.502981 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10151 10:01:44.509504 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10152 10:01:44.540177 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10153 10:01:44.546657 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10154 10:01:44.553357 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10155 10:01:44.556798 [ 0.000000] psci: probing for conduit method from DT.
10156 10:01:44.563216 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10157 10:01:44.566369 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10158 10:01:44.572960 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10159 10:01:44.576302 [ 0.000000] psci: SMC Calling Convention v1.2
10160 10:01:44.582939 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10161 10:01:44.586311 [ 0.000000] Detected VIPT I-cache on CPU0
10162 10:01:44.593309 [ 0.000000] CPU features: detected: GIC system register CPU interface
10163 10:01:44.599593 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10164 10:01:44.606215 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10165 10:01:44.612580 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10166 10:01:44.622770 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10167 10:01:44.629424 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10168 10:01:44.632406 [ 0.000000] alternatives: applying boot alternatives
10169 10:01:44.639029 [ 0.000000] Fallback order for Node 0: 0
10170 10:01:44.645701 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10171 10:01:44.648948 [ 0.000000] Policy zone: Normal
10172 10:01:44.662182 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10173 10:01:44.671744 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10174 10:01:44.682219 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10175 10:01:44.692383 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10176 10:01:44.698742 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10177 10:01:44.702117 <6>[ 0.000000] software IO TLB: area num 8.
10178 10:01:44.757764 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10179 10:01:44.838322 <6>[ 0.000000] Memory: 3800096K/4191232K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 358368K reserved, 32768K cma-reserved)
10180 10:01:44.844659 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10181 10:01:44.851199 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10182 10:01:44.854735 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10183 10:01:44.861580 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10184 10:01:44.867585 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10185 10:01:44.871023 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10186 10:01:44.881024 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10187 10:01:44.887699 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10188 10:01:44.894014 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10189 10:01:44.901016 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10190 10:01:44.903762 <6>[ 0.000000] GICv3: 608 SPIs implemented
10191 10:01:44.907204 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10192 10:01:44.913994 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10193 10:01:44.917101 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10194 10:01:44.923695 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10195 10:01:44.937053 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10196 10:01:44.950490 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10197 10:01:44.956531 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10198 10:01:44.964467 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10199 10:01:44.978129 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10200 10:01:44.984403 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10201 10:01:44.991153 <6>[ 0.009174] Console: colour dummy device 80x25
10202 10:01:45.000938 <6>[ 0.013929] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10203 10:01:45.007763 <6>[ 0.024372] pid_max: default: 32768 minimum: 301
10204 10:01:45.011083 <6>[ 0.029274] LSM: Security Framework initializing
10205 10:01:45.017752 <6>[ 0.034216] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10206 10:01:45.027332 <6>[ 0.041823] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10207 10:01:45.034360 <6>[ 0.051044] cblist_init_generic: Setting adjustable number of callback queues.
10208 10:01:45.040910 <6>[ 0.058486] cblist_init_generic: Setting shift to 3 and lim to 1.
10209 10:01:45.050690 <6>[ 0.064864] cblist_init_generic: Setting adjustable number of callback queues.
10210 10:01:45.053988 <6>[ 0.072291] cblist_init_generic: Setting shift to 3 and lim to 1.
10211 10:01:45.060658 <6>[ 0.078690] rcu: Hierarchical SRCU implementation.
10212 10:01:45.067516 <6>[ 0.083704] rcu: Max phase no-delay instances is 1000.
10213 10:01:45.073937 <6>[ 0.090719] EFI services will not be available.
10214 10:01:45.076849 <6>[ 0.095672] smp: Bringing up secondary CPUs ...
10215 10:01:45.084988 <6>[ 0.100715] Detected VIPT I-cache on CPU1
10216 10:01:45.091760 <6>[ 0.100782] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10217 10:01:45.098256 <6>[ 0.100813] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10218 10:01:45.101464 <6>[ 0.101138] Detected VIPT I-cache on CPU2
10219 10:01:45.108584 <6>[ 0.101185] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10220 10:01:45.118006 <6>[ 0.101201] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10221 10:01:45.121320 <6>[ 0.101453] Detected VIPT I-cache on CPU3
10222 10:01:45.128047 <6>[ 0.101498] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10223 10:01:45.134624 <6>[ 0.101511] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10224 10:01:45.137998 <6>[ 0.101811] CPU features: detected: Spectre-v4
10225 10:01:45.144390 <6>[ 0.101818] CPU features: detected: Spectre-BHB
10226 10:01:45.147586 <6>[ 0.101823] Detected PIPT I-cache on CPU4
10227 10:01:45.154224 <6>[ 0.101880] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10228 10:01:45.161117 <6>[ 0.101897] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10229 10:01:45.167648 <6>[ 0.102183] Detected PIPT I-cache on CPU5
10230 10:01:45.174056 <6>[ 0.102245] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10231 10:01:45.180815 <6>[ 0.102261] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10232 10:01:45.184122 <6>[ 0.102538] Detected PIPT I-cache on CPU6
10233 10:01:45.190704 <6>[ 0.102599] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10234 10:01:45.197180 <6>[ 0.102614] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10235 10:01:45.203594 <6>[ 0.102909] Detected PIPT I-cache on CPU7
10236 10:01:45.210119 <6>[ 0.102974] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10237 10:01:45.216614 <6>[ 0.102990] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10238 10:01:45.219885 <6>[ 0.103037] smp: Brought up 1 node, 8 CPUs
10239 10:01:45.226481 <6>[ 0.244411] SMP: Total of 8 processors activated.
10240 10:01:45.229675 <6>[ 0.249332] CPU features: detected: 32-bit EL0 Support
10241 10:01:45.239861 <6>[ 0.254694] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10242 10:01:45.246262 <6>[ 0.263550] CPU features: detected: Common not Private translations
10243 10:01:45.253252 <6>[ 0.270025] CPU features: detected: CRC32 instructions
10244 10:01:45.256389 <6>[ 0.275376] CPU features: detected: RCpc load-acquire (LDAPR)
10245 10:01:45.263169 <6>[ 0.281336] CPU features: detected: LSE atomic instructions
10246 10:01:45.269642 <6>[ 0.287117] CPU features: detected: Privileged Access Never
10247 10:01:45.276079 <6>[ 0.292933] CPU features: detected: RAS Extension Support
10248 10:01:45.283001 <6>[ 0.298542] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10249 10:01:45.286141 <6>[ 0.305760] CPU: All CPU(s) started at EL2
10250 10:01:45.292525 <6>[ 0.310076] alternatives: applying system-wide alternatives
10251 10:01:45.301461 <6>[ 0.319942] devtmpfs: initialized
10252 10:01:45.316503 <6>[ 0.328250] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10253 10:01:45.322935 <6>[ 0.338212] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10254 10:01:45.329497 <6>[ 0.346437] pinctrl core: initialized pinctrl subsystem
10255 10:01:45.332907 <6>[ 0.353106] DMI not present or invalid.
10256 10:01:45.339358 <6>[ 0.357508] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10257 10:01:45.349239 <6>[ 0.364377] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10258 10:01:45.355837 <6>[ 0.371822] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10259 10:01:45.365802 <6>[ 0.379913] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10260 10:01:45.368913 <6>[ 0.388069] audit: initializing netlink subsys (disabled)
10261 10:01:45.378862 <5>[ 0.393765] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10262 10:01:45.385545 <6>[ 0.394461] thermal_sys: Registered thermal governor 'step_wise'
10263 10:01:45.392114 <6>[ 0.401733] thermal_sys: Registered thermal governor 'power_allocator'
10264 10:01:45.395291 <6>[ 0.407991] cpuidle: using governor menu
10265 10:01:45.402008 <6>[ 0.418952] NET: Registered PF_QIPCRTR protocol family
10266 10:01:45.408285 <6>[ 0.424438] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10267 10:01:45.415063 <6>[ 0.431538] ASID allocator initialised with 32768 entries
10268 10:01:45.418051 <6>[ 0.438085] Serial: AMBA PL011 UART driver
10269 10:01:45.428228 <4>[ 0.446848] Trying to register duplicate clock ID: 134
10270 10:01:45.482532 <6>[ 0.504362] KASLR enabled
10271 10:01:45.496974 <6>[ 0.512083] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10272 10:01:45.503248 <6>[ 0.519096] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10273 10:01:45.510299 <6>[ 0.525584] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10274 10:01:45.516694 <6>[ 0.532584] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10275 10:01:45.523273 <6>[ 0.539073] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10276 10:01:45.529653 <6>[ 0.546079] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10277 10:01:45.536720 <6>[ 0.552566] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10278 10:01:45.543269 <6>[ 0.559570] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10279 10:01:45.546298 <6>[ 0.567063] ACPI: Interpreter disabled.
10280 10:01:45.555229 <6>[ 0.573465] iommu: Default domain type: Translated
10281 10:01:45.561574 <6>[ 0.578577] iommu: DMA domain TLB invalidation policy: strict mode
10282 10:01:45.564939 <5>[ 0.585205] SCSI subsystem initialized
10283 10:01:45.571625 <6>[ 0.589369] usbcore: registered new interface driver usbfs
10284 10:01:45.578079 <6>[ 0.595098] usbcore: registered new interface driver hub
10285 10:01:45.581325 <6>[ 0.600649] usbcore: registered new device driver usb
10286 10:01:45.588291 <6>[ 0.606749] pps_core: LinuxPPS API ver. 1 registered
10287 10:01:45.598065 <6>[ 0.611943] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10288 10:01:45.601528 <6>[ 0.621291] PTP clock support registered
10289 10:01:45.604865 <6>[ 0.625534] EDAC MC: Ver: 3.0.0
10290 10:01:45.612140 <6>[ 0.630689] FPGA manager framework
10291 10:01:45.618693 <6>[ 0.634368] Advanced Linux Sound Architecture Driver Initialized.
10292 10:01:45.622157 <6>[ 0.641136] vgaarb: loaded
10293 10:01:45.628891 <6>[ 0.644297] clocksource: Switched to clocksource arch_sys_counter
10294 10:01:45.632052 <5>[ 0.650730] VFS: Disk quotas dquot_6.6.0
10295 10:01:45.638591 <6>[ 0.654914] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10296 10:01:45.641995 <6>[ 0.662099] pnp: PnP ACPI: disabled
10297 10:01:45.650727 <6>[ 0.668769] NET: Registered PF_INET protocol family
10298 10:01:45.656811 <6>[ 0.674162] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10299 10:01:45.668955 <6>[ 0.684188] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10300 10:01:45.678750 <6>[ 0.692977] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10301 10:01:45.685271 <6>[ 0.700940] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10302 10:01:45.691925 <6>[ 0.709340] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10303 10:01:45.702940 <6>[ 0.717989] TCP: Hash tables configured (established 32768 bind 32768)
10304 10:01:45.709554 <6>[ 0.724845] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10305 10:01:45.716112 <6>[ 0.731865] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10306 10:01:45.722751 <6>[ 0.739381] NET: Registered PF_UNIX/PF_LOCAL protocol family
10307 10:01:45.729109 <6>[ 0.745451] RPC: Registered named UNIX socket transport module.
10308 10:01:45.732510 <6>[ 0.751598] RPC: Registered udp transport module.
10309 10:01:45.739221 <6>[ 0.756531] RPC: Registered tcp transport module.
10310 10:01:45.745683 <6>[ 0.761464] RPC: Registered tcp NFSv4.1 backchannel transport module.
10311 10:01:45.748888 <6>[ 0.768128] PCI: CLS 0 bytes, default 64
10312 10:01:45.752106 <6>[ 0.772422] Unpacking initramfs...
10313 10:01:45.777655 <6>[ 0.792935] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10314 10:01:45.787518 <6>[ 0.801608] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10315 10:01:45.790953 <6>[ 0.810452] kvm [1]: IPA Size Limit: 40 bits
10316 10:01:45.797479 <6>[ 0.814978] kvm [1]: GICv3: no GICV resource entry
10317 10:01:45.800828 <6>[ 0.819998] kvm [1]: disabling GICv2 emulation
10318 10:01:45.807516 <6>[ 0.824683] kvm [1]: GIC system register CPU interface enabled
10319 10:01:45.810887 <6>[ 0.830849] kvm [1]: vgic interrupt IRQ18
10320 10:01:45.817697 <6>[ 0.835220] kvm [1]: VHE mode initialized successfully
10321 10:01:45.824223 <5>[ 0.841580] Initialise system trusted keyrings
10322 10:01:45.830542 <6>[ 0.846386] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10323 10:01:45.838042 <6>[ 0.856350] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10324 10:01:45.844550 <5>[ 0.862747] NFS: Registering the id_resolver key type
10325 10:01:45.847867 <5>[ 0.868051] Key type id_resolver registered
10326 10:01:45.854491 <5>[ 0.872466] Key type id_legacy registered
10327 10:01:45.860907 <6>[ 0.876752] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10328 10:01:45.867747 <6>[ 0.883671] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10329 10:01:45.874219 <6>[ 0.891439] 9p: Installing v9fs 9p2000 file system support
10330 10:01:45.910657 <5>[ 0.929134] Key type asymmetric registered
10331 10:01:45.914196 <5>[ 0.933467] Asymmetric key parser 'x509' registered
10332 10:01:45.923956 <6>[ 0.938612] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10333 10:01:45.927291 <6>[ 0.946245] io scheduler mq-deadline registered
10334 10:01:45.930480 <6>[ 0.951008] io scheduler kyber registered
10335 10:01:45.949378 <6>[ 0.968060] EINJ: ACPI disabled.
10336 10:01:45.981776 <4>[ 0.993610] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10337 10:01:45.991594 <4>[ 1.004206] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10338 10:01:46.006669 <6>[ 1.025214] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10339 10:01:46.014865 <6>[ 1.033175] printk: console [ttyS0] disabled
10340 10:01:46.042864 <6>[ 1.057811] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10341 10:01:46.049498 <6>[ 1.067284] printk: console [ttyS0] enabled
10342 10:01:46.052942 <6>[ 1.067284] printk: console [ttyS0] enabled
10343 10:01:46.059416 <6>[ 1.076183] printk: bootconsole [mtk8250] disabled
10344 10:01:46.062722 <6>[ 1.076183] printk: bootconsole [mtk8250] disabled
10345 10:01:46.069393 <6>[ 1.087417] SuperH (H)SCI(F) driver initialized
10346 10:01:46.072782 <6>[ 1.092711] msm_serial: driver initialized
10347 10:01:46.087018 <6>[ 1.101671] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10348 10:01:46.096658 <6>[ 1.110217] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10349 10:01:46.103367 <6>[ 1.118759] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10350 10:01:46.113886 <6>[ 1.127387] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10351 10:01:46.123312 <6>[ 1.136094] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10352 10:01:46.130134 <6>[ 1.144807] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10353 10:01:46.139782 <6>[ 1.153347] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10354 10:01:46.146544 <6>[ 1.162158] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10355 10:01:46.156360 <6>[ 1.170702] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10356 10:01:46.168016 <6>[ 1.186214] loop: module loaded
10357 10:01:46.174595 <6>[ 1.192249] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10358 10:01:46.197712 <4>[ 1.215648] mtk-pmic-keys: Failed to locate of_node [id: -1]
10359 10:01:46.204159 <6>[ 1.222501] megasas: 07.719.03.00-rc1
10360 10:01:46.213932 <6>[ 1.232169] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10361 10:01:46.221659 <6>[ 1.239668] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10362 10:01:46.238297 <6>[ 1.256442] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10363 10:01:46.294910 <6>[ 1.306372] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10364 10:01:48.171728 <6>[ 3.190214] Freeing initrd memory: 55108K
10365 10:01:48.181883 <6>[ 3.200205] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10366 10:01:48.192638 <6>[ 3.211095] tun: Universal TUN/TAP device driver, 1.6
10367 10:01:48.196085 <6>[ 3.217139] thunder_xcv, ver 1.0
10368 10:01:48.199346 <6>[ 3.220644] thunder_bgx, ver 1.0
10369 10:01:48.202757 <6>[ 3.224137] nicpf, ver 1.0
10370 10:01:48.213428 <6>[ 3.228143] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10371 10:01:48.216502 <6>[ 3.235619] hns3: Copyright (c) 2017 Huawei Corporation.
10372 10:01:48.222893 <6>[ 3.241225] hclge is initializing
10373 10:01:48.226425 <6>[ 3.244805] e1000: Intel(R) PRO/1000 Network Driver
10374 10:01:48.232978 <6>[ 3.249934] e1000: Copyright (c) 1999-2006 Intel Corporation.
10375 10:01:48.236180 <6>[ 3.255946] e1000e: Intel(R) PRO/1000 Network Driver
10376 10:01:48.242730 <6>[ 3.261161] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10377 10:01:48.249649 <6>[ 3.267345] igb: Intel(R) Gigabit Ethernet Network Driver
10378 10:01:48.256103 <6>[ 3.272995] igb: Copyright (c) 2007-2014 Intel Corporation.
10379 10:01:48.262899 <6>[ 3.278831] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10380 10:01:48.269291 <6>[ 3.285349] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10381 10:01:48.272650 <6>[ 3.291815] sky2: driver version 1.30
10382 10:01:48.279204 <6>[ 3.296807] VFIO - User Level meta-driver version: 0.3
10383 10:01:48.286743 <6>[ 3.305042] usbcore: registered new interface driver usb-storage
10384 10:01:48.293534 <6>[ 3.311486] usbcore: registered new device driver onboard-usb-hub
10385 10:01:48.302293 <6>[ 3.320614] mt6397-rtc mt6359-rtc: registered as rtc0
10386 10:01:48.312306 <6>[ 3.326081] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-24T10:01:48 UTC (1700820108)
10387 10:01:48.315209 <6>[ 3.335642] i2c_dev: i2c /dev entries driver
10388 10:01:48.332400 <6>[ 3.347400] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10389 10:01:48.352096 <6>[ 3.370374] cpu cpu0: EM: created perf domain
10390 10:01:48.355360 <6>[ 3.375268] cpu cpu4: EM: created perf domain
10391 10:01:48.362557 <6>[ 3.380777] sdhci: Secure Digital Host Controller Interface driver
10392 10:01:48.368788 <6>[ 3.387207] sdhci: Copyright(c) Pierre Ossman
10393 10:01:48.375814 <6>[ 3.392119] Synopsys Designware Multimedia Card Interface Driver
10394 10:01:48.382163 <6>[ 3.398718] sdhci-pltfm: SDHCI platform and OF driver helper
10395 10:01:48.385463 <6>[ 3.398806] mmc0: CQHCI version 5.10
10396 10:01:48.392257 <6>[ 3.408909] ledtrig-cpu: registered to indicate activity on CPUs
10397 10:01:48.398988 <6>[ 3.415943] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10398 10:01:48.405298 <6>[ 3.422974] usbcore: registered new interface driver usbhid
10399 10:01:48.408856 <6>[ 3.428799] usbhid: USB HID core driver
10400 10:01:48.415328 <6>[ 3.432998] spi_master spi0: will run message pump with realtime priority
10401 10:01:48.462607 <6>[ 3.474367] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10402 10:01:48.481812 <6>[ 3.489893] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10403 10:01:48.484982 <6>[ 3.504642] mmc0: Command Queue Engine enabled
10404 10:01:48.491675 <6>[ 3.505168] cros-ec-spi spi0.0: Chrome EC device registered
10405 10:01:48.498341 <6>[ 3.509375] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10406 10:01:48.505388 <6>[ 3.522439] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10407 10:01:48.515058 <6>[ 3.527976] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10408 10:01:48.518298 <6>[ 3.532298] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10409 10:01:48.524838 <6>[ 3.538309] NET: Registered PF_PACKET protocol family
10410 10:01:48.531301 <6>[ 3.544376] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10411 10:01:48.534710 <6>[ 3.548580] 9pnet: Installing 9P2000 support
10412 10:01:48.541439 <6>[ 3.554460] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10413 10:01:48.544880 <5>[ 3.558269] Key type dns_resolver registered
10414 10:01:48.551344 <6>[ 3.564277] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10415 10:01:48.554536 <6>[ 3.568332] registered taskstats version 1
10416 10:01:48.561177 <5>[ 3.578867] Loading compiled-in X.509 certificates
10417 10:01:48.588068 <4>[ 3.599723] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10418 10:01:48.597868 <4>[ 3.610451] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10419 10:01:48.604691 <3>[ 3.620976] debugfs: File 'uA_load' in directory '/' already present!
10420 10:01:48.611180 <3>[ 3.627674] debugfs: File 'min_uV' in directory '/' already present!
10421 10:01:48.617904 <3>[ 3.634280] debugfs: File 'max_uV' in directory '/' already present!
10422 10:01:48.624259 <3>[ 3.640943] debugfs: File 'constraint_flags' in directory '/' already present!
10423 10:01:48.635174 <3>[ 3.650349] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10424 10:01:48.644271 <6>[ 3.662972] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10425 10:01:48.651282 <6>[ 3.669788] xhci-mtk 11200000.usb: xHCI Host Controller
10426 10:01:48.658094 <6>[ 3.675272] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10427 10:01:48.667939 <6>[ 3.683098] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10428 10:01:48.674689 <6>[ 3.692514] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10429 10:01:48.681041 <6>[ 3.698571] xhci-mtk 11200000.usb: xHCI Host Controller
10430 10:01:48.687789 <6>[ 3.704046] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10431 10:01:48.694367 <6>[ 3.711691] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10432 10:01:48.701165 <6>[ 3.719254] hub 1-0:1.0: USB hub found
10433 10:01:48.704249 <6>[ 3.723264] hub 1-0:1.0: 1 port detected
10434 10:01:48.711117 <6>[ 3.727512] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10435 10:01:48.717772 <6>[ 3.736029] hub 2-0:1.0: USB hub found
10436 10:01:48.720889 <6>[ 3.740036] hub 2-0:1.0: 1 port detected
10437 10:01:48.728961 <6>[ 3.747578] mtk-msdc 11f70000.mmc: Got CD GPIO
10438 10:01:48.739174 <6>[ 3.753496] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10439 10:01:48.745844 <6>[ 3.761523] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10440 10:01:48.755549 <4>[ 3.769395] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10441 10:01:48.762445 <6>[ 3.778912] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10442 10:01:48.772126 <6>[ 3.786987] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10443 10:01:48.778691 <6>[ 3.795007] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10444 10:01:48.788495 <6>[ 3.802916] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10445 10:01:48.795109 <6>[ 3.810733] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10446 10:01:48.805262 <6>[ 3.818549] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10447 10:01:48.814919 <6>[ 3.828906] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10448 10:01:48.822000 <6>[ 3.837263] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10449 10:01:48.831675 <6>[ 3.845602] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10450 10:01:48.838300 <6>[ 3.853956] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10451 10:01:48.848184 <6>[ 3.862294] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10452 10:01:48.855041 <6>[ 3.870632] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10453 10:01:48.864659 <6>[ 3.878970] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10454 10:01:48.871191 <6>[ 3.887309] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10455 10:01:48.881217 <6>[ 3.895647] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10456 10:01:48.887912 <6>[ 3.903984] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10457 10:01:48.897596 <6>[ 3.912323] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10458 10:01:48.904161 <6>[ 3.920661] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10459 10:01:48.914228 <6>[ 3.928999] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10460 10:01:48.920650 <6>[ 3.937337] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10461 10:01:48.930553 <6>[ 3.945677] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10462 10:01:48.937281 <6>[ 3.954401] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10463 10:01:48.943911 <6>[ 3.961554] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10464 10:01:48.950208 <6>[ 3.968289] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10465 10:01:48.956834 <6>[ 3.975018] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10466 10:01:48.963716 <6>[ 3.981917] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10467 10:01:48.973494 <6>[ 3.988777] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10468 10:01:48.983515 <6>[ 3.997904] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10469 10:01:48.993486 <6>[ 4.007021] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10470 10:01:49.003332 <6>[ 4.016313] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10471 10:01:49.009848 <6>[ 4.025783] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10472 10:01:49.019912 <6>[ 4.035250] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10473 10:01:49.029990 <6>[ 4.044369] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10474 10:01:49.039939 <6>[ 4.053837] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10475 10:01:49.049920 <6>[ 4.062955] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10476 10:01:49.059777 <6>[ 4.072248] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10477 10:01:49.070029 <6>[ 4.082408] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10478 10:01:49.079475 <6>[ 4.093887] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10479 10:01:49.109686 <6>[ 4.124793] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10480 10:01:49.138041 <6>[ 4.156118] hub 2-1:1.0: USB hub found
10481 10:01:49.140846 <6>[ 4.160583] hub 2-1:1.0: 3 ports detected
10482 10:01:49.149597 <6>[ 4.167795] hub 2-1:1.0: USB hub found
10483 10:01:49.152821 <6>[ 4.172153] hub 2-1:1.0: 3 ports detected
10484 10:01:49.261394 <6>[ 4.276576] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10485 10:01:49.414601 <6>[ 4.432875] hub 1-1:1.0: USB hub found
10486 10:01:49.417553 <6>[ 4.437274] hub 1-1:1.0: 4 ports detected
10487 10:01:49.426070 <6>[ 4.444381] hub 1-1:1.0: USB hub found
10488 10:01:49.429238 <6>[ 4.448902] hub 1-1:1.0: 4 ports detected
10489 10:01:49.493639 <6>[ 4.508638] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10490 10:01:49.749122 <6>[ 4.764587] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10491 10:01:49.881522 <6>[ 4.900083] hub 1-1.4:1.0: USB hub found
10492 10:01:49.884860 <6>[ 4.904740] hub 1-1.4:1.0: 2 ports detected
10493 10:01:49.893974 <6>[ 4.912418] hub 1-1.4:1.0: USB hub found
10494 10:01:49.897647 <6>[ 4.917044] hub 1-1.4:1.0: 2 ports detected
10495 10:01:50.193472 <6>[ 5.208579] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10496 10:01:50.385273 <6>[ 5.400602] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10497 10:02:01.375081 <6>[ 16.397581] ALSA device list:
10498 10:02:01.381260 <6>[ 16.400870] No soundcards found.
10499 10:02:01.389123 <6>[ 16.408686] Freeing unused kernel memory: 8384K
10500 10:02:01.392340 <6>[ 16.413651] Run /init as init process
10501 10:02:01.433635 <6>[ 16.453532] NET: Registered PF_INET6 protocol family
10502 10:02:01.440622 <6>[ 16.459672] Segment Routing with IPv6
10503 10:02:01.443862 <6>[ 16.463620] In-situ OAM (IOAM) with IPv6
10504 10:02:01.477929 <30>[ 16.477713] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10505 10:02:01.481397 <30>[ 16.501645] systemd[1]: Detected architecture arm64.
10506 10:02:01.481862
10507 10:02:01.487881 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10508 10:02:01.488500
10509 10:02:01.501066 <30>[ 16.520591] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10510 10:02:01.625046 <30>[ 16.641731] systemd[1]: Queued start job for default target Graphical Interface.
10511 10:02:01.661577 <30>[ 16.681314] systemd[1]: Created slice system-getty.slice.
10512 10:02:01.668637 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10513 10:02:01.685593 <30>[ 16.705185] systemd[1]: Created slice system-modprobe.slice.
10514 10:02:01.691688 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10515 10:02:01.709646 <30>[ 16.729654] systemd[1]: Created slice system-serial\x2dgetty.slice.
10516 10:02:01.720048 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10517 10:02:01.733280 <30>[ 16.753064] systemd[1]: Created slice User and Session Slice.
10518 10:02:01.740333 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10519 10:02:01.760931 <30>[ 16.777149] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10520 10:02:01.770420 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10521 10:02:01.788650 <30>[ 16.805118] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10522 10:02:01.795486 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10523 10:02:01.820203 <30>[ 16.833002] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10524 10:02:01.826374 <30>[ 16.845261] systemd[1]: Reached target Local Encrypted Volumes.
10525 10:02:01.832821 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10526 10:02:01.849064 <30>[ 16.869032] systemd[1]: Reached target Paths.
10527 10:02:01.855677 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10528 10:02:01.868637 <30>[ 16.888619] systemd[1]: Reached target Remote File Systems.
10529 10:02:01.875632 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10530 10:02:01.893143 <30>[ 16.912562] systemd[1]: Reached target Slices.
10531 10:02:01.899034 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10532 10:02:01.912814 <30>[ 16.932635] systemd[1]: Reached target Swap.
10533 10:02:01.915939 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10534 10:02:01.936399 <30>[ 16.953082] systemd[1]: Listening on initctl Compatibility Named Pipe.
10535 10:02:01.943323 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10536 10:02:01.949837 <30>[ 16.968240] systemd[1]: Listening on Journal Audit Socket.
10537 10:02:01.956355 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10538 10:02:01.969266 <30>[ 16.989077] systemd[1]: Listening on Journal Socket (/dev/log).
10539 10:02:01.975589 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10540 10:02:01.993670 <30>[ 17.013787] systemd[1]: Listening on Journal Socket.
10541 10:02:02.000723 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10542 10:02:02.013051 <30>[ 17.033164] systemd[1]: Listening on udev Control Socket.
10543 10:02:02.020065 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10544 10:02:02.037845 <30>[ 17.057587] systemd[1]: Listening on udev Kernel Socket.
10545 10:02:02.044269 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10546 10:02:02.101229 <30>[ 17.120808] systemd[1]: Mounting Huge Pages File System...
10547 10:02:02.107281 Mounting [0;1;39mHuge Pages File System[0m...
10548 10:02:02.124019 <30>[ 17.143584] systemd[1]: Mounting POSIX Message Queue File System...
10549 10:02:02.130820 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10550 10:02:02.147975 <30>[ 17.168008] systemd[1]: Mounting Kernel Debug File System...
10551 10:02:02.154714 Mounting [0;1;39mKernel Debug File System[0m...
10552 10:02:02.172169 <30>[ 17.188759] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10553 10:02:02.185108 <30>[ 17.201682] systemd[1]: Starting Create list of static device nodes for the current kernel...
10554 10:02:02.191700 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10555 10:02:02.213017 <30>[ 17.233037] systemd[1]: Starting Load Kernel Module configfs...
10556 10:02:02.219694 Starting [0;1;39mLoad Kernel Module configfs[0m...
10557 10:02:02.241155 <30>[ 17.261089] systemd[1]: Starting Load Kernel Module drm...
10558 10:02:02.247694 Starting [0;1;39mLoad Kernel Module drm[0m...
10559 10:02:02.268241 <30>[ 17.284979] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10560 10:02:02.283050 <30>[ 17.302520] systemd[1]: Starting Journal Service...
10561 10:02:02.286046 Starting [0;1;39mJournal Service[0m...
10562 10:02:02.311235 <30>[ 17.331042] systemd[1]: Starting Load Kernel Modules...
10563 10:02:02.318007 Starting [0;1;39mLoad Kernel Modules[0m...
10564 10:02:02.344477 <30>[ 17.360892] systemd[1]: Starting Remount Root and Kernel File Systems...
10565 10:02:02.350740 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10566 10:02:02.368240 <30>[ 17.387711] systemd[1]: Starting Coldplug All udev Devices...
10567 10:02:02.374500 Starting [0;1;39mColdplug All udev Devices[0m...
10568 10:02:02.391856 <30>[ 17.411730] systemd[1]: Started Journal Service.
10569 10:02:02.398586 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10570 10:02:02.415584 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10571 10:02:02.433510 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10572 10:02:02.449220 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10573 10:02:02.470530 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10574 10:02:02.491212 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10575 10:02:02.515803 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10576 10:02:02.534770 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10577 10:02:02.554866 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10578 10:02:02.569066 See 'systemctl status systemd-remount-fs.service' for details.
10579 10:02:02.610964 Mounting [0;1;39mKernel Configuration File System[0m...
10580 10:02:02.632818 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10581 10:02:02.644587 <46>[ 17.661418] systemd-journald[180]: Received client request to flush runtime journal.
10582 10:02:02.654958 Starting [0;1;39mLoad/Save Random Seed[0m...
10583 10:02:02.674418 Starting [0;1;39mApply Kernel Variables[0m...
10584 10:02:02.698356 Starting [0;1;39mCreate System Users[0m...
10585 10:02:02.718112 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10586 10:02:02.737994 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10587 10:02:02.757689 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10588 10:02:02.770854 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10589 10:02:02.786564 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10590 10:02:02.801334 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10591 10:02:02.829705 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10592 10:02:02.853509 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10593 10:02:02.865211 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10594 10:02:02.880553 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10595 10:02:02.921136 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10596 10:02:02.944212 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10597 10:02:02.961976 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10598 10:02:02.985978 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10599 10:02:03.042855 Starting [0;1;39mNetwork Time Synchronization[0m...
10600 10:02:03.066110 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10601 10:02:03.105449 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10602 10:02:03.120571 <6>[ 18.137354] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10603 10:02:03.142494 [[0;32m OK [<6>[ 18.159291] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10604 10:02:03.151821 0m] Finished [0<6>[ 18.167989] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10605 10:02:03.162059 ;1;39mUpdate UTM<6>[ 18.177769] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10606 10:02:03.171724 P about System Boot/Shutdown[0m<6>[ 18.189261] remoteproc remoteproc0: scp is available
10607 10:02:03.172254 .
10608 10:02:03.175038 <6>[ 18.189399] mc: Linux media interface: v0.10
10609 10:02:03.181807 <4>[ 18.191196] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10610 10:02:03.191988 <4>[ 18.194433] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10611 10:02:03.195007 <6>[ 18.196070] remoteproc remoteproc0: powering up scp
10612 10:02:03.204819 <6>[ 18.220481] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10613 10:02:03.208085 <6>[ 18.223893] usbcore: registered new interface driver r8152
10614 10:02:03.218436 [[0;32m OK [<6>[ 18.228991] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10615 10:02:03.228196 0m] Found device<3>[ 18.243068] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10616 10:02:03.234869 [0;1;39m/dev/t<3>[ 18.251526] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10617 10:02:03.237960 tyS0[0m.
10618 10:02:03.244294 <3>[ 18.260985] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10619 10:02:03.254580 <6>[ 18.264314] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10620 10:02:03.257858 <6>[ 18.267607] videodev: Linux video capture interface: v2.00
10621 10:02:03.267542 <3>[ 18.270126] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10622 10:02:03.274935 <3>[ 18.270131] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10623 10:02:03.283972 <3>[ 18.270134] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10624 10:02:03.290843 <3>[ 18.270145] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10625 10:02:03.297472 <3>[ 18.270153] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10626 10:02:03.307228 <3>[ 18.270190] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10627 10:02:03.314147 <3>[ 18.270222] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10628 10:02:03.324149 <3>[ 18.270225] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10629 10:02:03.330648 <3>[ 18.270228] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10630 10:02:03.340898 <3>[ 18.270252] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10631 10:02:03.350685 <6>[ 18.315295] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10632 10:02:03.357157 <3>[ 18.316053] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10633 10:02:03.363753 <6>[ 18.319016] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10634 10:02:03.370124 <6>[ 18.319036] pci_bus 0000:00: root bus resource [bus 00-ff]
10635 10:02:03.376806 <6>[ 18.319051] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10636 10:02:03.386400 <6>[ 18.319056] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10637 10:02:03.393133 <6>[ 18.319108] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10638 10:02:03.402931 <6>[ 18.319138] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10639 10:02:03.406554 <6>[ 18.319260] pci 0000:00:00.0: supports D1 D2
10640 10:02:03.413377 <6>[ 18.319265] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10641 10:02:03.422895 <6>[ 18.325185] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10642 10:02:03.429897 <6>[ 18.327909] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10643 10:02:03.436096 <6>[ 18.330820] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10644 10:02:03.446283 <6>[ 18.330853] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10645 10:02:03.452652 <6>[ 18.330872] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10646 10:02:03.459259 <6>[ 18.330887] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10647 10:02:03.465978 <6>[ 18.331010] pci 0000:01:00.0: supports D1 D2
10648 10:02:03.472662 <6>[ 18.331012] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10649 10:02:03.479265 <3>[ 18.332202] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10650 10:02:03.485745 <6>[ 18.340715] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10651 10:02:03.495568 <3>[ 18.348368] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10652 10:02:03.502050 <3>[ 18.348373] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10653 10:02:03.512415 <3>[ 18.348896] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10654 10:02:03.519002 <6>[ 18.348938] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10655 10:02:03.528707 <6>[ 18.354325] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10656 10:02:03.535298 <6>[ 18.354330] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10657 10:02:03.541871 <6>[ 18.354343] remoteproc remoteproc0: remote processor scp is now up
10658 10:02:03.552211 <4>[ 18.371882] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10659 10:02:03.555360 <4>[ 18.371882] Fallback method does not support PEC.
10660 10:02:03.562457 <6>[ 18.374684] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10661 10:02:03.566041 <6>[ 18.419970] Bluetooth: Core ver 2.22
10662 10:02:03.573010 <6>[ 18.420750] usbcore: registered new interface driver cdc_ether
10663 10:02:03.579962 <6>[ 18.426843] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10664 10:02:03.586501 <6>[ 18.427216] usbcore: registered new interface driver r8153_ecm
10665 10:02:03.596730 <6>[ 18.427840] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10666 10:02:03.603368 <4>[ 18.429544] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10667 10:02:03.614039 <4>[ 18.429551] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10668 10:02:03.620039 <6>[ 18.429816] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10669 10:02:03.626827 <6>[ 18.448046] NET: Registered PF_BLUETOOTH protocol family
10670 10:02:03.633375 <6>[ 18.449094] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10671 10:02:03.644120 <6>[ 18.450486] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10672 10:02:03.650659 <6>[ 18.450654] usbcore: registered new interface driver uvcvideo
10673 10:02:03.660860 <6>[ 18.456345] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10674 10:02:03.667453 <6>[ 18.462493] Bluetooth: HCI device and connection manager initialized
10675 10:02:03.670607 <6>[ 18.462510] Bluetooth: HCI socket layer initialized
10676 10:02:03.677727 <6>[ 18.470042] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10677 10:02:03.684432 <6>[ 18.477446] Bluetooth: L2CAP socket layer initialized
10678 10:02:03.687889 <6>[ 18.477462] Bluetooth: SCO socket layer initialized
10679 10:02:03.697720 <6>[ 18.484960] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10680 10:02:03.701314 <6>[ 18.488577] r8152 2-1.3:1.0 eth0: v1.12.13
10681 10:02:03.707789 <6>[ 18.490781] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10682 10:02:03.717506 <6>[ 18.496354] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10683 10:02:03.720831 <6>[ 18.501406] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10684 10:02:03.728150 <6>[ 18.545371] usbcore: registered new interface driver btusb
10685 10:02:03.738198 <4>[ 18.546215] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10686 10:02:03.744716 <3>[ 18.546228] Bluetooth: hci0: Failed to load firmware file (-2)
10687 10:02:03.751477 <3>[ 18.546233] Bluetooth: hci0: Failed to set up firmware (-2)
10688 10:02:03.761405 <4>[ 18.546238] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10689 10:02:03.768225 <6>[ 18.553462] pci 0000:00:00.0: PCI bridge to [bus 01]
10690 10:02:03.774833 <3>[ 18.590413] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10691 10:02:03.781998 <3>[ 18.591224] power_supply sbs-5-000b: driver failed to report `current_avg' property: -6
10692 10:02:03.791702 <6>[ 18.591326] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10693 10:02:03.801954 <3>[ 18.598621] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10694 10:02:03.805148 <6>[ 18.605679] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10695 10:02:03.815539 <3>[ 18.636942] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10696 10:02:03.825451 <3>[ 18.637906] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10697 10:02:03.831912 <6>[ 18.645742] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10698 10:02:03.838699 <3>[ 18.670454] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10699 10:02:03.845722 <6>[ 18.676781] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10700 10:02:03.852601 <3>[ 18.704244] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10701 10:02:03.862872 <5>[ 18.731967] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10702 10:02:03.869647 <3>[ 18.755454] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10703 10:02:03.877182 <5>[ 18.778450] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10704 10:02:03.886649 <3>[ 18.806983] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10705 10:02:03.893483 <4>[ 18.808718] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10706 10:02:03.903746 <3>[ 18.837742] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10707 10:02:03.910688 <6>[ 18.840561] cfg80211: failed to load regulatory.db
10708 10:02:03.917222 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10709 10:02:03.930793 <6>[ 18.947462] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10710 10:02:03.937187 <6>[ 18.954956] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10711 10:02:03.940628 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10712 10:02:03.960525 <6>[ 18.980541] mt7921e 0000:01:00.0: ASIC revision: 79610010
10713 10:02:03.967057 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10714 10:02:04.016844 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10715 10:02:04.038733 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10716 10:02:04.066795 <4>[ 19.079867] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10717 10:02:04.185919 [[0;32m OK [0m] Reached targ<4>[ 19.198299] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10718 10:02:04.188495 et [0;1;39mBluetooth[0m.
10719 10:02:04.201635 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10720 10:02:04.220387 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10721 10:02:04.236106 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10722 10:02:04.248466 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10723 10:02:04.268396 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10724 10:02:04.284814 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10725 10:02:04.304598 <4>[ 19.318278] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10726 10:02:04.311175 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10727 10:02:04.328555 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10728 10:02:04.373227 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10729 10:02:04.421876 <4>[ 19.435471] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10730 10:02:04.425213 Starting [0;1;39mUser Login Management[0m...
10731 10:02:04.446946 Starting [0;1;39mPermit User Sessions[0m...
10732 10:02:04.473028 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10733 10:02:04.489826 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10734 10:02:04.506657 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10735 10:02:04.524295 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10736 10:02:04.541328 <4>[ 19.554981] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10737 10:02:04.582229 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10738 10:02:04.602519 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10739 10:02:04.609968 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10740 10:02:04.625394 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10741 10:02:04.641437 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10742 10:02:04.664610 <4>[ 19.678410] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10743 10:02:04.697891 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10744 10:02:04.736362 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10745 10:02:04.781469 <4>[ 19.794982] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10746 10:02:04.782004
10747 10:02:04.782361
10748 10:02:04.788002 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10749 10:02:04.788461
10750 10:02:04.791386 debian-bullseye-arm64 login: root (automatic login)
10751 10:02:04.791917
10752 10:02:04.792275
10753 10:02:04.814487 Linux debian-bullseye-arm64 6.1.62-cip9 #1 SMP PREEMPT Fri Nov 24 09:44:51 UTC 2023 aarch64
10754 10:02:04.815012
10755 10:02:04.821471 The programs included with the Debian GNU/Linux system are free software;
10756 10:02:04.827831 the exact distribution terms for each program are described in the
10757 10:02:04.831168 individual files in /usr/share/doc/*/copyright.
10758 10:02:04.831713
10759 10:02:04.837661 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10760 10:02:04.840935 permitted by applicable law.
10761 10:02:04.842432 Matched prompt #10: / #
10763 10:02:04.843555 Setting prompt string to ['/ #']
10764 10:02:04.844256 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10766 10:02:04.845544 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
10767 10:02:04.846230 start: 2.2.6 expect-shell-connection (timeout 00:03:21) [common]
10768 10:02:04.846687 Setting prompt string to ['/ #']
10769 10:02:04.847043 Forcing a shell prompt, looking for ['/ #']
10771 10:02:04.898130 / #
10772 10:02:04.898779 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10773 10:02:04.899217 Waiting using forced prompt support (timeout 00:02:30)
10774 10:02:04.901015 <4>[ 19.914821] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10775 10:02:04.901499
10776 10:02:04.945386 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10777 10:02:04.945998 start: 2.2.7 export-device-env (timeout 00:03:21) [common]
10778 10:02:04.946530 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10779 10:02:04.947014 end: 2.2 depthcharge-retry (duration 00:01:39) [common]
10780 10:02:04.947473 end: 2 depthcharge-action (duration 00:01:39) [common]
10781 10:02:04.947972 start: 3 lava-test-retry (timeout 00:07:59) [common]
10782 10:02:04.948538 start: 3.1 lava-test-shell (timeout 00:07:59) [common]
10783 10:02:04.948976 Using namespace: common
10785 10:02:05.050132 / # #
10786 10:02:05.050745 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10787 10:02:05.051284 #<4>[ 20.039367] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10788 10:02:05.056037
10789 10:02:05.056814 Using /lava-12073309
10791 10:02:05.158172 / # export SHELL=/bin/sh
10792 10:02:05.158942 export SHELL=/bin/sh<4>[ 20.158434] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10793 10:02:05.164265
10795 10:02:05.266392 / # . /lava-12073309/environment
10796 10:02:05.267171 . /lava-12073309/environment<3>[ 20.272734] mt7921e 0000:01:00.0: hardware init failed
10797 10:02:05.272833
10799 10:02:05.374691 / # /lava-12073309/bin/lava-test-runner /lava-12073309/0
10800 10:02:05.375310 Test shell timeout: 10s (minimum of the action and connection timeout)
10801 10:02:05.381326 /lava-12073309/bin/lava-test-runner /lava-12073309/0
10802 10:02:05.406843 + export TESTRUN_ID=0_igt-gpu-pa<8>[ 20.425157] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 12073309_1.5.2.3.1>
10803 10:02:05.407668 Received signal: <STARTRUN> 0_igt-gpu-panfrost 12073309_1.5.2.3.1
10804 10:02:05.408281 Starting test lava.0_igt-gpu-panfrost (12073309_1.5.2.3.1)
10805 10:02:05.409065 Skipping test definition patterns.
10806 10:02:05.410252 nfrost
10807 10:02:05.413155 + cd /lava-12073309/0/tests/0_igt-gpu-panfrost
10808 10:02:05.413631 + cat uuid
10809 10:02:05.416681 + UUID=12073309_1.5.2.3.1
10810 10:02:05.417140 + set +x
10811 10:02:05.429768 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new pan<8>[ 20.448455] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
10812 10:02:05.430768 Received signal: <TESTSET> START panfrost_gem_new
10813 10:02:05.431188 Starting test_set panfrost_gem_new
10814 10:02:05.433070 frost_get_param panfrost_prime panfrost_submit
10815 10:02:05.450117 <14>[ 20.470211] [IGT] panfrost_gem_new: executing
10816 10:02:05.456272 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.477079] [IGT] panfrost_gem_new: exiting, ret=77
10817 10:02:05.459619 rch64) (Linux: 6.1.62-cip9 aarch64)
10818 10:02:05.469531 Test requirement not met in<8>[ 20.487317] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
10819 10:02:05.470353 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
10821 10:02:05.476330 function drm_open_driver, file ../lib/drmtest.c:621:
10822 10:02:05.476956 Test requirement: !(fd<0)
10823 10:02:05.486442 No known gpu found for chipset flags 0x32 (pan<14>[ 20.506784] [IGT] panfrost_gem_new: executing
10824 10:02:05.487076 frost)
10825 10:02:05.496241 Last errno: 2, No such f<14>[ 20.513366] [IGT] panfrost_gem_new: exiting, ret=77
10826 10:02:05.496888 ile or directory
10827 10:02:05.499302 [1mSubtest gem-new-4096: SKIP (0.000s)[0m
10828 10:02:05.506126 I<8>[ 20.525243] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
10829 10:02:05.506854 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
10831 10:02:05.512639 GT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
10832 10:02:05.522397 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:<14>[ 20.544050] [IGT] panfrost_gem_new: executing
10833 10:02:05.526099 621:
10834 10:02:05.526646 Test requirement: !(fd<0)
10835 10:02:05.532396 <14>[ 20.551262] [IGT] panfrost_gem_new: exiting, ret=77
10836 10:02:05.533024
10837 10:02:05.542346 No known gpu found for chipset flags 0x32 (panf<8>[ 20.561506] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
10838 10:02:05.543200 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
10840 10:02:05.545367 rost)
10841 10:02:05.548802 Last errno: 2, No such fi<8>[ 20.570303] <LAVA_SIGNAL_TESTSET STOP>
10842 10:02:05.549547 Received signal: <TESTSET> STOP
10843 10:02:05.549975 Closing test_set panfrost_gem_new
10844 10:02:05.552025 le or directory
10845 10:02:05.555596 [1mSubtest gem-new-0: SKIP (0.000s)[0m
10846 10:02:05.561965 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
10847 10:02:05.572128 Test requirement not met in function drm_open_dr<8>[ 20.590794] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
10848 10:02:05.573057 Received signal: <TESTSET> START panfrost_get_param
10849 10:02:05.573489 Starting test_set panfrost_get_param
10850 10:02:05.575336 iver, file ../lib/drmtest.c:621:
10851 10:02:05.575910 Test requirement: !(fd<0)
10852 10:02:05.582186 No known gpu found for chipset flags 0x32 (panfrost)
10853 10:02:05.588356 Last errno: 2, No such file o<14>[ 20.607883] [IGT] panfrost_get_param: executing
10854 10:02:05.588989 r directory
10855 10:02:05.598237 [1mSubtest gem-new<14>[ 20.616025] [IGT] panfrost_get_param: exiting, ret=77
10856 10:02:05.598820 -zeroed: SKIP (0.000s)[0m
10857 10:02:05.608358 IGT-Version: 1.27.1-g621c2d3 (aarch6<8>[ 20.626622] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
10858 10:02:05.609298 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
10860 10:02:05.611763 4) (Linux: 6.1.62-cip9 aarch64)
10861 10:02:05.618259 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
10862 10:02:05.621147 Test requirement: !(fd<0)
10863 10:02:05.627851 No known gpu found for chipset flags 0x32 (panfrost)
10864 10:02:05.631382 Last errno: 2, No such file or directory
10865 10:02:05.638025 [1mSubtest base-params: SKIP (0.0<14>[ 20.657352] [IGT] panfrost_get_param: executing
10866 10:02:05.638630 00s)[0m
10867 10:02:05.647692 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.666424] [IGT] panfrost_get_param: exiting, ret=77
10868 10:02:05.651125 rch64) (Linux: 6.1.62-cip9 aarch64)
10869 10:02:05.661134 Test requirement not met in function drm_open_driver, file <8>[ 20.679940] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
10870 10:02:05.661998 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
10872 10:02:05.664120 ../lib/drmtest.c:621:
10873 10:02:05.667463 Test requirement: !(fd<0)
10874 10:02:05.671036 No known gpu found for chipset flags 0x32 (panfrost)
10875 10:02:05.674268 Last errno: 2, No such file or directory
10876 10:02:05.681066 [1mSubtest get-bad-param: SKIP (0.000s)[0m
10877 10:02:05.690554 <14>[ 20.710627] [IGT] panfrost_get_param: executing
10878 10:02:05.700961 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 20.718972] [IGT] panfrost_get_param: exiting, ret=77
10879 10:02:05.703837 .1.62-cip9 aarch64)
10880 10:02:05.716717 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c<8>[ 20.732510] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
10881 10:02:05.717300 :621:
10882 10:02:05.717948 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
10884 10:02:05.723384 Test requirement: !(fd<0)<8>[ 20.742778] <LAVA_SIGNAL_TESTSET STOP>
10885 10:02:05.723851
10886 10:02:05.724568 Received signal: <TESTSET> STOP
10887 10:02:05.725022 Closing test_set panfrost_get_param
10888 10:02:05.726807 No known gpu found for chipset flags 0x32 (panfrost)
10889 10:02:05.729905 Last errno: 2, No such file or directory
10890 10:02:05.736605 [1mSubtest get-bad-padding: SKIP (0.000s)[0m
10891 10:02:05.752375 <8>[ 20.772979] <LAVA_SIGNAL_TESTSET START panfrost_prime>
10892 10:02:05.753387 Received signal: <TESTSET> START panfrost_prime
10893 10:02:05.753796 Starting test_set panfrost_prime
10894 10:02:05.783970 <14>[ 20.803956] [IGT] panfrost_prime: executing
10895 10:02:05.790639 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.811470] [IGT] panfrost_prime: exiting, ret=77
10896 10:02:05.793533 rch64) (Linux: 6.1.62-cip9 aarch64)
10897 10:02:05.807126 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c<8>[ 20.825627] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
10898 10:02:05.807985 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
10900 10:02:05.810068 :621:
10901 10:02:05.813881 Received signal: <TESTSET> STOP
10902 10:02:05.814418 Closing test_set panfrost_prime
10903 10:02:05.816934 Test requirement: !(fd<0)<8>[ 20.835606] <LAVA_SIGNAL_TESTSET STOP>
10904 10:02:05.817505
10905 10:02:05.820417 No known gpu found for chipset flags 0x32 (panfrost)
10906 10:02:05.823295 Last errno: 2, No such file or directory
10907 10:02:05.827008 [1mSubtest gem-prime-import: SKIP (0.000s)[0m
10908 10:02:05.845584 <8>[ 20.865745] <LAVA_SIGNAL_TESTSET START panfrost_submit>
10909 10:02:05.846539 Received signal: <TESTSET> START panfrost_submit
10910 10:02:05.846957 Starting test_set panfrost_submit
10911 10:02:05.875539 <14>[ 20.895700] [IGT] panfrost_submit: executing
10912 10:02:05.885574 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 20.903956] [IGT] panfrost_submit: exiting, ret=77
10913 10:02:05.886143 .1.62-cip9 aarch64)
10914 10:02:05.898962 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c<8>[ 20.917186] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
10915 10:02:05.899815 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
10917 10:02:05.901912 :621:
10918 10:02:05.902369 Test requirement: !(fd<0)
10919 10:02:05.908774 No known gpu found for chipset flags 0x32 (panfrost)
10920 10:02:05.911931 Last errno: 2, No such file or directory
10921 10:02:05.918547 [1mSubtest pa<14>[ 20.937103] [IGT] panfrost_submit: executing
10922 10:02:05.919112 n-submit: SKIP (0.000s)[0m
10923 10:02:05.925294 IGT<14>[ 20.944057] [IGT] panfrost_submit: exiting, ret=77
10924 10:02:05.931760 -Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
10925 10:02:05.938478 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
10927 10:02:05.941809 Test requireme<8>[ 20.956782] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
10928 10:02:05.944744 nt not met in function drm_open_driver, file ../lib/drmtest.c:621:
10929 10:02:05.948068 Test requirement: !(fd<0)
10930 10:02:05.951289 No known gpu found for chipset flags 0x32 (panfrost)
10931 10:02:05.958121 Last errno: 2, No such file or directory
10932 10:02:05.961217 [1mSubtest pan-submit-error-no-jc: SKIP (0.000s)[0m
10933 10:02:05.964719 <14>[ 20.986792] [IGT] panfrost_submit: executing
10934 10:02:05.974677 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 20.994662] [IGT] panfrost_submit: exiting, ret=77
10935 10:02:05.978092 .1.62-cip9 aarch64)
10936 10:02:05.984606 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
10937 10:02:05.994741 Test requ<8>[ 21.010132] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
10938 10:02:05.995293 irement: !(fd<0)
10939 10:02:05.995941 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
10941 10:02:06.001431 No known gpu found for chipset flags 0x32 (panfrost)
10942 10:02:06.004864 Last errno: 2, No such file or directory
10943 10:02:06.011347 [1mSubtest pan-submit-error-bad-in-syncs: SKI<14>[ 21.031870] [IGT] panfrost_submit: executing
10944 10:02:06.014797 P (0.000s)[0m
10945 10:02:06.021329 IGT-Version: 1.2<14>[ 21.039336] [IGT] panfrost_submit: exiting, ret=77
10946 10:02:06.024125 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
10947 10:02:06.034219 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
10949 10:02:06.037269 Test requirement not met in<8>[ 21.051961] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
10950 10:02:06.040891 function drm_open_driver, file ../lib/drmtest.c:621:
10951 10:02:06.044060 Test requirement: !(fd<0)
10952 10:02:06.047222 No known gpu found for chipset flags 0x32 (panfrost)
10953 10:02:06.050507 Last errno: 2, No such file or directory
10954 10:02:06.057196 [1mSubtest pan-submit-error-bad-bo-handles: SKIP (0.000s)[0m
10955 10:02:06.063867 <14>[ 21.082969] [IGT] panfrost_submit: executing
10956 10:02:06.070404 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 21.090802] [IGT] panfrost_submit: exiting, ret=77
10957 10:02:06.073985 .1.62-cip9 aarch64)
10958 10:02:06.080247 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
10959 10:02:06.090625 Test requ<8>[ 21.106409] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
10960 10:02:06.091470 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
10962 10:02:06.093431 irement: !(fd<0)
10963 10:02:06.096893 No known gpu found for chipset flags 0x32 (panfrost)
10964 10:02:06.100391 Last errno: 2, No such file or directory
10965 10:02:06.106711 [1mSubtest pan-submit-error-b<14>[ 21.127502] [IGT] panfrost_submit: executing
10966 10:02:06.116767 ad-requirements: SKIP (0.000s)[<14>[ 21.134845] [IGT] panfrost_submit: exiting, ret=77
10967 10:02:06.117317 0m
10968 10:02:06.123031 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
10969 10:02:06.130024 Test re<8>[ 21.147137] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
10970 10:02:06.130870 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
10972 10:02:06.136873 quirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
10973 10:02:06.139899 Test requirement: !(fd<0)
10974 10:02:06.143226 No known gpu found for chipset flags 0x32 (panfrost)
10975 10:02:06.149923 Last errno: 2, No such file or directory
10976 10:02:06.156214 [1mSubtest pan-submit-error-bad-out-sync: SKIP (0.000s)[<14>[ 21.178105] [IGT] panfrost_submit: executing
10977 10:02:06.159436 0m
10978 10:02:06.166493 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 21.186339] [IGT] panfrost_submit: exiting, ret=77
10979 10:02:06.169345 .1.62-cip9 aarch64)
10980 10:02:06.176395 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
10981 10:02:06.183376 Test requ<8>[ 21.202078] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
10982 10:02:06.184216 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
10984 10:02:06.186109 irement: !(fd<0)
10985 10:02:06.189349 No known gpu found for chipset flags 0x32 (panfrost)
10986 10:02:06.192825 Last errno: 2, No such file or directory
10987 10:02:06.199358 [1mSubtest pan-reset: SKIP (0.000s)[0m
10988 10:02:06.211531 <14>[ 21.231889] [IGT] panfrost_submit: executing
10989 10:02:06.218191 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 21.239605] [IGT] panfrost_submit: exiting, ret=77
10990 10:02:06.221500 rch64) (Linux: 6.1.62-cip9 aarch64)
10991 10:02:06.238360 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c<8>[ 21.253727] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
10992 10:02:06.238927 :621:
10993 10:02:06.239577 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
10995 10:02:06.241297 Test requirement: !(fd<0)
10996 10:02:06.245035 No known gpu found for chipset flags 0x32 (panfrost)
10997 10:02:06.248147 Last errno: 2, No such file or directory
10998 10:02:06.251239 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
10999 10:02:06.270012 <14>[ 21.290565] [IGT] panfrost_submit: executing
11000 10:02:06.280585 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 21.298288] [IGT] panfrost_submit: exiting, ret=77
11001 10:02:06.281148 .1.62-cip9 aarch64)
11002 10:02:06.290029 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11003 10:02:06.296564 Test requ<8>[ 21.313680] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11004 10:02:06.297412 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11006 10:02:06.300292 irement: !(fd<0)
11007 10:02:06.303458 No known gpu f<8>[ 21.324039] <LAVA_SIGNAL_TESTSET STOP>
11008 10:02:06.304289 Received signal: <TESTSET> STOP
11009 10:02:06.304777 Closing test_set panfrost_submit
11010 10:02:06.313692 ound for chipset<8>[ 21.330056] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 12073309_1.5.2.3.1>
11011 10:02:06.314238 flags 0x32 (panfrost)
11012 10:02:06.314875 Received signal: <ENDRUN> 0_igt-gpu-panfrost 12073309_1.5.2.3.1
11013 10:02:06.315324 Ending use of test pattern.
11014 10:02:06.315664 Ending test lava.0_igt-gpu-panfrost (12073309_1.5.2.3.1), duration 0.91
11016 10:02:06.317457 Last errno: 2, No such file or directory
11017 10:02:06.322862 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11018 10:02:06.323412 + set +x
11019 10:02:06.326398 <LAVA_TEST_RUNNER EXIT>
11020 10:02:06.327160 ok: lava_test_shell seems to have completed
11021 10:02:06.328925 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11022 10:02:06.329460 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11023 10:02:06.329936 end: 3 lava-test-retry (duration 00:00:01) [common]
11024 10:02:06.330432 start: 4 finalize (timeout 00:07:57) [common]
11025 10:02:06.330939 start: 4.1 power-off (timeout 00:00:30) [common]
11026 10:02:06.331785 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
11027 10:02:06.422582 >> Command sent successfully.
11028 10:02:06.434363 Returned 0 in 0 seconds
11029 10:02:06.536008 end: 4.1 power-off (duration 00:00:00) [common]
11031 10:02:06.537619 start: 4.2 read-feedback (timeout 00:07:57) [common]
11032 10:02:06.538948 Listened to connection for namespace 'common' for up to 1s
11033 10:02:07.539553 Finalising connection for namespace 'common'
11034 10:02:07.540306 Disconnecting from shell: Finalise
11035 10:02:07.540840 / #
11036 10:02:07.641972 end: 4.2 read-feedback (duration 00:00:01) [common]
11037 10:02:07.642728 end: 4 finalize (duration 00:00:01) [common]
11038 10:02:07.643535 Cleaning after the job
11039 10:02:07.644116 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073309/tftp-deploy-djv8i3is/ramdisk
11040 10:02:07.678883 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073309/tftp-deploy-djv8i3is/kernel
11041 10:02:07.695019 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073309/tftp-deploy-djv8i3is/dtb
11042 10:02:07.695318 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073309/tftp-deploy-djv8i3is/modules
11043 10:02:07.704861 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12073309
11044 10:02:07.820980 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12073309
11045 10:02:07.821163 Job finished correctly