Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 34
- Kernel Warnings: 24
- Boot result: PASS
- Errors: 0
1 10:01:06.581484 lava-dispatcher, installed at version: 2023.10
2 10:01:06.581727 start: 0 validate
3 10:01:06.581870 Start time: 2023-11-24 10:01:06.581859+00:00 (UTC)
4 10:01:06.582007 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:01:06.582146 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 10:01:06.850689 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:01:06.850925 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:01:07.117567 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:01:07.117763 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:01:07.383030 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:01:07.383216 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 10:01:07.649700 validate duration: 1.07
14 10:01:07.649988 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 10:01:07.650085 start: 1.1 download-retry (timeout 00:10:00) [common]
16 10:01:07.650176 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 10:01:07.650302 Not decompressing ramdisk as can be used compressed.
18 10:01:07.650387 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230623.0/arm64/rootfs.cpio.gz
19 10:01:07.650451 saving as /var/lib/lava/dispatcher/tmp/12073323/tftp-deploy-3pqnrf9v/ramdisk/rootfs.cpio.gz
20 10:01:07.650515 total size: 43284872 (41 MB)
21 10:01:07.651596 progress 0 % (0 MB)
22 10:01:07.663335 progress 5 % (2 MB)
23 10:01:07.674759 progress 10 % (4 MB)
24 10:01:07.686251 progress 15 % (6 MB)
25 10:01:07.697764 progress 20 % (8 MB)
26 10:01:07.709342 progress 25 % (10 MB)
27 10:01:07.720894 progress 30 % (12 MB)
28 10:01:07.732314 progress 35 % (14 MB)
29 10:01:07.743692 progress 40 % (16 MB)
30 10:01:07.755037 progress 45 % (18 MB)
31 10:01:07.766397 progress 50 % (20 MB)
32 10:01:07.777829 progress 55 % (22 MB)
33 10:01:07.789483 progress 60 % (24 MB)
34 10:01:07.801012 progress 65 % (26 MB)
35 10:01:07.812753 progress 70 % (28 MB)
36 10:01:07.824243 progress 75 % (30 MB)
37 10:01:07.835707 progress 80 % (33 MB)
38 10:01:07.847040 progress 85 % (35 MB)
39 10:01:07.858498 progress 90 % (37 MB)
40 10:01:07.869760 progress 95 % (39 MB)
41 10:01:07.881154 progress 100 % (41 MB)
42 10:01:07.881416 41 MB downloaded in 0.23 s (178.78 MB/s)
43 10:01:07.881613 end: 1.1.1 http-download (duration 00:00:00) [common]
45 10:01:07.881855 end: 1.1 download-retry (duration 00:00:00) [common]
46 10:01:07.881941 start: 1.2 download-retry (timeout 00:10:00) [common]
47 10:01:07.882063 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 10:01:07.882201 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 10:01:07.882275 saving as /var/lib/lava/dispatcher/tmp/12073323/tftp-deploy-3pqnrf9v/kernel/Image
50 10:01:07.882338 total size: 49107456 (46 MB)
51 10:01:07.882400 No compression specified
52 10:01:07.883635 progress 0 % (0 MB)
53 10:01:07.896818 progress 5 % (2 MB)
54 10:01:07.910443 progress 10 % (4 MB)
55 10:01:07.923537 progress 15 % (7 MB)
56 10:01:07.936513 progress 20 % (9 MB)
57 10:01:07.949483 progress 25 % (11 MB)
58 10:01:07.962329 progress 30 % (14 MB)
59 10:01:07.975146 progress 35 % (16 MB)
60 10:01:07.987906 progress 40 % (18 MB)
61 10:01:08.000740 progress 45 % (21 MB)
62 10:01:08.014115 progress 50 % (23 MB)
63 10:01:08.027446 progress 55 % (25 MB)
64 10:01:08.040394 progress 60 % (28 MB)
65 10:01:08.053762 progress 65 % (30 MB)
66 10:01:08.066577 progress 70 % (32 MB)
67 10:01:08.079164 progress 75 % (35 MB)
68 10:01:08.092004 progress 80 % (37 MB)
69 10:01:08.104990 progress 85 % (39 MB)
70 10:01:08.117816 progress 90 % (42 MB)
71 10:01:08.130493 progress 95 % (44 MB)
72 10:01:08.143319 progress 100 % (46 MB)
73 10:01:08.143562 46 MB downloaded in 0.26 s (179.28 MB/s)
74 10:01:08.143717 end: 1.2.1 http-download (duration 00:00:00) [common]
76 10:01:08.143981 end: 1.2 download-retry (duration 00:00:00) [common]
77 10:01:08.144074 start: 1.3 download-retry (timeout 00:10:00) [common]
78 10:01:08.144160 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 10:01:08.144308 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 10:01:08.144398 saving as /var/lib/lava/dispatcher/tmp/12073323/tftp-deploy-3pqnrf9v/dtb/mt8192-asurada-spherion-r0.dtb
81 10:01:08.144476 total size: 47278 (0 MB)
82 10:01:08.144538 No compression specified
83 10:01:08.145688 progress 69 % (0 MB)
84 10:01:08.145996 progress 100 % (0 MB)
85 10:01:08.146154 0 MB downloaded in 0.00 s (26.91 MB/s)
86 10:01:08.146278 end: 1.3.1 http-download (duration 00:00:00) [common]
88 10:01:08.146497 end: 1.3 download-retry (duration 00:00:00) [common]
89 10:01:08.146580 start: 1.4 download-retry (timeout 00:10:00) [common]
90 10:01:08.146662 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 10:01:08.146784 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 10:01:08.146852 saving as /var/lib/lava/dispatcher/tmp/12073323/tftp-deploy-3pqnrf9v/modules/modules.tar
93 10:01:08.146959 total size: 8622040 (8 MB)
94 10:01:08.147020 Using unxz to decompress xz
95 10:01:08.151294 progress 0 % (0 MB)
96 10:01:08.173006 progress 5 % (0 MB)
97 10:01:08.197886 progress 10 % (0 MB)
98 10:01:08.223171 progress 15 % (1 MB)
99 10:01:08.247892 progress 20 % (1 MB)
100 10:01:08.273287 progress 25 % (2 MB)
101 10:01:08.300537 progress 30 % (2 MB)
102 10:01:08.328444 progress 35 % (2 MB)
103 10:01:08.353037 progress 40 % (3 MB)
104 10:01:08.377287 progress 45 % (3 MB)
105 10:01:08.402550 progress 50 % (4 MB)
106 10:01:08.427254 progress 55 % (4 MB)
107 10:01:08.452081 progress 60 % (4 MB)
108 10:01:08.481095 progress 65 % (5 MB)
109 10:01:08.507362 progress 70 % (5 MB)
110 10:01:08.531572 progress 75 % (6 MB)
111 10:01:08.559822 progress 80 % (6 MB)
112 10:01:08.586730 progress 85 % (7 MB)
113 10:01:08.612936 progress 90 % (7 MB)
114 10:01:08.644046 progress 95 % (7 MB)
115 10:01:08.675628 progress 100 % (8 MB)
116 10:01:08.680575 8 MB downloaded in 0.53 s (15.41 MB/s)
117 10:01:08.680825 end: 1.4.1 http-download (duration 00:00:01) [common]
119 10:01:08.681082 end: 1.4 download-retry (duration 00:00:01) [common]
120 10:01:08.681175 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 10:01:08.681268 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 10:01:08.681350 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 10:01:08.681438 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 10:01:08.681670 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12073323/lava-overlay-wkyk4axp
125 10:01:08.681806 makedir: /var/lib/lava/dispatcher/tmp/12073323/lava-overlay-wkyk4axp/lava-12073323/bin
126 10:01:08.681914 makedir: /var/lib/lava/dispatcher/tmp/12073323/lava-overlay-wkyk4axp/lava-12073323/tests
127 10:01:08.682013 makedir: /var/lib/lava/dispatcher/tmp/12073323/lava-overlay-wkyk4axp/lava-12073323/results
128 10:01:08.682133 Creating /var/lib/lava/dispatcher/tmp/12073323/lava-overlay-wkyk4axp/lava-12073323/bin/lava-add-keys
129 10:01:08.682383 Creating /var/lib/lava/dispatcher/tmp/12073323/lava-overlay-wkyk4axp/lava-12073323/bin/lava-add-sources
130 10:01:08.682520 Creating /var/lib/lava/dispatcher/tmp/12073323/lava-overlay-wkyk4axp/lava-12073323/bin/lava-background-process-start
131 10:01:08.682655 Creating /var/lib/lava/dispatcher/tmp/12073323/lava-overlay-wkyk4axp/lava-12073323/bin/lava-background-process-stop
132 10:01:08.682783 Creating /var/lib/lava/dispatcher/tmp/12073323/lava-overlay-wkyk4axp/lava-12073323/bin/lava-common-functions
133 10:01:08.682955 Creating /var/lib/lava/dispatcher/tmp/12073323/lava-overlay-wkyk4axp/lava-12073323/bin/lava-echo-ipv4
134 10:01:08.683086 Creating /var/lib/lava/dispatcher/tmp/12073323/lava-overlay-wkyk4axp/lava-12073323/bin/lava-install-packages
135 10:01:08.683213 Creating /var/lib/lava/dispatcher/tmp/12073323/lava-overlay-wkyk4axp/lava-12073323/bin/lava-installed-packages
136 10:01:08.683341 Creating /var/lib/lava/dispatcher/tmp/12073323/lava-overlay-wkyk4axp/lava-12073323/bin/lava-os-build
137 10:01:08.683467 Creating /var/lib/lava/dispatcher/tmp/12073323/lava-overlay-wkyk4axp/lava-12073323/bin/lava-probe-channel
138 10:01:08.683592 Creating /var/lib/lava/dispatcher/tmp/12073323/lava-overlay-wkyk4axp/lava-12073323/bin/lava-probe-ip
139 10:01:08.683718 Creating /var/lib/lava/dispatcher/tmp/12073323/lava-overlay-wkyk4axp/lava-12073323/bin/lava-target-ip
140 10:01:08.683844 Creating /var/lib/lava/dispatcher/tmp/12073323/lava-overlay-wkyk4axp/lava-12073323/bin/lava-target-mac
141 10:01:08.683970 Creating /var/lib/lava/dispatcher/tmp/12073323/lava-overlay-wkyk4axp/lava-12073323/bin/lava-target-storage
142 10:01:08.684102 Creating /var/lib/lava/dispatcher/tmp/12073323/lava-overlay-wkyk4axp/lava-12073323/bin/lava-test-case
143 10:01:08.684230 Creating /var/lib/lava/dispatcher/tmp/12073323/lava-overlay-wkyk4axp/lava-12073323/bin/lava-test-event
144 10:01:08.684357 Creating /var/lib/lava/dispatcher/tmp/12073323/lava-overlay-wkyk4axp/lava-12073323/bin/lava-test-feedback
145 10:01:08.684484 Creating /var/lib/lava/dispatcher/tmp/12073323/lava-overlay-wkyk4axp/lava-12073323/bin/lava-test-raise
146 10:01:08.684612 Creating /var/lib/lava/dispatcher/tmp/12073323/lava-overlay-wkyk4axp/lava-12073323/bin/lava-test-reference
147 10:01:08.684739 Creating /var/lib/lava/dispatcher/tmp/12073323/lava-overlay-wkyk4axp/lava-12073323/bin/lava-test-runner
148 10:01:08.684866 Creating /var/lib/lava/dispatcher/tmp/12073323/lava-overlay-wkyk4axp/lava-12073323/bin/lava-test-set
149 10:01:08.684994 Creating /var/lib/lava/dispatcher/tmp/12073323/lava-overlay-wkyk4axp/lava-12073323/bin/lava-test-shell
150 10:01:08.685125 Updating /var/lib/lava/dispatcher/tmp/12073323/lava-overlay-wkyk4axp/lava-12073323/bin/lava-install-packages (oe)
151 10:01:08.685281 Updating /var/lib/lava/dispatcher/tmp/12073323/lava-overlay-wkyk4axp/lava-12073323/bin/lava-installed-packages (oe)
152 10:01:08.685406 Creating /var/lib/lava/dispatcher/tmp/12073323/lava-overlay-wkyk4axp/lava-12073323/environment
153 10:01:08.685517 LAVA metadata
154 10:01:08.685592 - LAVA_JOB_ID=12073323
155 10:01:08.685659 - LAVA_DISPATCHER_IP=192.168.201.1
156 10:01:08.685763 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 10:01:08.685834 skipped lava-vland-overlay
158 10:01:08.685909 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 10:01:08.685991 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 10:01:08.686059 skipped lava-multinode-overlay
161 10:01:08.686136 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 10:01:08.686221 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 10:01:08.686297 Loading test definitions
164 10:01:08.686388 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 10:01:08.686461 Using /lava-12073323 at stage 0
166 10:01:08.686767 uuid=12073323_1.5.2.3.1 testdef=None
167 10:01:08.686856 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 10:01:08.686984 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 10:01:08.687519 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 10:01:08.687737 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 10:01:08.688501 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 10:01:08.688739 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 10:01:08.689348 runner path: /var/lib/lava/dispatcher/tmp/12073323/lava-overlay-wkyk4axp/lava-12073323/0/tests/0_igt-kms-mediatek test_uuid 12073323_1.5.2.3.1
176 10:01:08.689510 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 10:01:08.689719 Creating lava-test-runner.conf files
179 10:01:08.689782 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12073323/lava-overlay-wkyk4axp/lava-12073323/0 for stage 0
180 10:01:08.689873 - 0_igt-kms-mediatek
181 10:01:08.689972 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 10:01:08.690056 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 10:01:08.696829 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 10:01:08.696940 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 10:01:08.697028 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 10:01:08.697112 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 10:01:08.697203 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 10:01:10.128494 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 10:01:10.128902 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 10:01:10.129016 extracting modules file /var/lib/lava/dispatcher/tmp/12073323/tftp-deploy-3pqnrf9v/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12073323/extract-overlay-ramdisk-l342nvus/ramdisk
191 10:01:10.386935 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 10:01:10.387111 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 10:01:10.387208 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12073323/compress-overlay-zwcd3dlv/overlay-1.5.2.4.tar.gz to ramdisk
194 10:01:10.387284 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12073323/compress-overlay-zwcd3dlv/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12073323/extract-overlay-ramdisk-l342nvus/ramdisk
195 10:01:10.394020 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 10:01:10.394135 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 10:01:10.394229 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 10:01:10.394319 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 10:01:10.394397 Building ramdisk /var/lib/lava/dispatcher/tmp/12073323/extract-overlay-ramdisk-l342nvus/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12073323/extract-overlay-ramdisk-l342nvus/ramdisk
200 10:01:11.442551 >> 369977 blocks
201 10:01:17.266885 rename /var/lib/lava/dispatcher/tmp/12073323/extract-overlay-ramdisk-l342nvus/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12073323/tftp-deploy-3pqnrf9v/ramdisk/ramdisk.cpio.gz
202 10:01:17.267355 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 10:01:17.267483 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 10:01:17.267584 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 10:01:17.267690 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12073323/tftp-deploy-3pqnrf9v/kernel/Image'
206 10:01:29.682033 Returned 0 in 12 seconds
207 10:01:29.782657 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12073323/tftp-deploy-3pqnrf9v/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12073323/tftp-deploy-3pqnrf9v/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12073323/tftp-deploy-3pqnrf9v/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12073323/tftp-deploy-3pqnrf9v/kernel/image.itb
208 10:01:30.614893 output: FIT description: Kernel Image image with one or more FDT blobs
209 10:01:30.615323 output: Created: Fri Nov 24 10:01:30 2023
210 10:01:30.615407 output: Image 0 (kernel-1)
211 10:01:30.615476 output: Description:
212 10:01:30.615543 output: Created: Fri Nov 24 10:01:30 2023
213 10:01:30.615608 output: Type: Kernel Image
214 10:01:30.615670 output: Compression: lzma compressed
215 10:01:30.615731 output: Data Size: 11047542 Bytes = 10788.62 KiB = 10.54 MiB
216 10:01:30.615790 output: Architecture: AArch64
217 10:01:30.615849 output: OS: Linux
218 10:01:30.615904 output: Load Address: 0x00000000
219 10:01:30.615962 output: Entry Point: 0x00000000
220 10:01:30.616017 output: Hash algo: crc32
221 10:01:30.616074 output: Hash value: 2edffaa3
222 10:01:30.616132 output: Image 1 (fdt-1)
223 10:01:30.616188 output: Description: mt8192-asurada-spherion-r0
224 10:01:30.616242 output: Created: Fri Nov 24 10:01:30 2023
225 10:01:30.616297 output: Type: Flat Device Tree
226 10:01:30.616351 output: Compression: uncompressed
227 10:01:30.616405 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 10:01:30.616459 output: Architecture: AArch64
229 10:01:30.616514 output: Hash algo: crc32
230 10:01:30.616567 output: Hash value: cc4352de
231 10:01:30.616620 output: Image 2 (ramdisk-1)
232 10:01:30.616673 output: Description: unavailable
233 10:01:30.616727 output: Created: Fri Nov 24 10:01:30 2023
234 10:01:30.616781 output: Type: RAMDisk Image
235 10:01:30.616835 output: Compression: Unknown Compression
236 10:01:30.616889 output: Data Size: 56440934 Bytes = 55118.10 KiB = 53.83 MiB
237 10:01:30.616943 output: Architecture: AArch64
238 10:01:30.616997 output: OS: Linux
239 10:01:30.617051 output: Load Address: unavailable
240 10:01:30.617104 output: Entry Point: unavailable
241 10:01:30.617196 output: Hash algo: crc32
242 10:01:30.617255 output: Hash value: 4af98bdf
243 10:01:30.617310 output: Default Configuration: 'conf-1'
244 10:01:30.617365 output: Configuration 0 (conf-1)
245 10:01:30.617426 output: Description: mt8192-asurada-spherion-r0
246 10:01:30.617513 output: Kernel: kernel-1
247 10:01:30.617570 output: Init Ramdisk: ramdisk-1
248 10:01:30.617624 output: FDT: fdt-1
249 10:01:30.617678 output: Loadables: kernel-1
250 10:01:30.617732 output:
251 10:01:30.617935 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 10:01:30.618037 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 10:01:30.618142 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 10:01:30.618238 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
255 10:01:30.618322 No LXC device requested
256 10:01:30.618406 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 10:01:30.618492 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
258 10:01:30.618573 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 10:01:30.618645 Checking files for TFTP limit of 4294967296 bytes.
260 10:01:30.619172 end: 1 tftp-deploy (duration 00:00:23) [common]
261 10:01:30.619300 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 10:01:30.619427 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 10:01:30.619564 substitutions:
264 10:01:30.619633 - {DTB}: 12073323/tftp-deploy-3pqnrf9v/dtb/mt8192-asurada-spherion-r0.dtb
265 10:01:30.619702 - {INITRD}: 12073323/tftp-deploy-3pqnrf9v/ramdisk/ramdisk.cpio.gz
266 10:01:30.619764 - {KERNEL}: 12073323/tftp-deploy-3pqnrf9v/kernel/Image
267 10:01:30.619824 - {LAVA_MAC}: None
268 10:01:30.619882 - {PRESEED_CONFIG}: None
269 10:01:30.619939 - {PRESEED_LOCAL}: None
270 10:01:30.619995 - {RAMDISK}: 12073323/tftp-deploy-3pqnrf9v/ramdisk/ramdisk.cpio.gz
271 10:01:30.620051 - {ROOT_PART}: None
272 10:01:30.620126 - {ROOT}: None
273 10:01:30.620188 - {SERVER_IP}: 192.168.201.1
274 10:01:30.620244 - {TEE}: None
275 10:01:30.620299 Parsed boot commands:
276 10:01:30.620353 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 10:01:30.620539 Parsed boot commands: tftpboot 192.168.201.1 12073323/tftp-deploy-3pqnrf9v/kernel/image.itb 12073323/tftp-deploy-3pqnrf9v/kernel/cmdline
278 10:01:30.620630 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 10:01:30.620720 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 10:01:30.620814 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 10:01:30.620905 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 10:01:30.620977 Not connected, no need to disconnect.
283 10:01:30.621052 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 10:01:30.621133 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 10:01:30.621198 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
286 10:01:30.625316 Setting prompt string to ['lava-test: # ']
287 10:01:30.625691 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 10:01:30.625807 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 10:01:30.625909 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 10:01:30.626008 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 10:01:30.626206 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
292 10:01:35.765759 >> Command sent successfully.
293 10:01:35.768574 Returned 0 in 5 seconds
294 10:01:35.869017 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 10:01:35.869386 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 10:01:35.869504 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 10:01:35.869631 Setting prompt string to 'Starting depthcharge on Spherion...'
299 10:01:35.869712 Changing prompt to 'Starting depthcharge on Spherion...'
300 10:01:35.869831 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 10:01:35.870244 [Enter `^Ec?' for help]
302 10:01:36.043212
303 10:01:36.043375
304 10:01:36.043450 F0: 102B 0000
305 10:01:36.043516
306 10:01:36.043575 F3: 1001 0000 [0200]
307 10:01:36.046625
308 10:01:36.046710 F3: 1001 0000
309 10:01:36.046777
310 10:01:36.046838 F7: 102D 0000
311 10:01:36.046908
312 10:01:36.049706 F1: 0000 0000
313 10:01:36.049797
314 10:01:36.049863 V0: 0000 0000 [0001]
315 10:01:36.049929
316 10:01:36.053194 00: 0007 8000
317 10:01:36.053283
318 10:01:36.053349 01: 0000 0000
319 10:01:36.053412
320 10:01:36.056466 BP: 0C00 0209 [0000]
321 10:01:36.056550
322 10:01:36.056616 G0: 1182 0000
323 10:01:36.056678
324 10:01:36.059777 EC: 0000 0021 [4000]
325 10:01:36.059876
326 10:01:36.059943 S7: 0000 0000 [0000]
327 10:01:36.060022
328 10:01:36.063437 CC: 0000 0000 [0001]
329 10:01:36.063548
330 10:01:36.063614 T0: 0000 0040 [010F]
331 10:01:36.063676
332 10:01:36.063748 Jump to BL
333 10:01:36.066656
334 10:01:36.090223
335 10:01:36.090375
336 10:01:36.090460
337 10:01:36.098231 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 10:01:36.101681 ARM64: Exception handlers installed.
339 10:01:36.105741 ARM64: Testing exception
340 10:01:36.105846 ARM64: Done test exception
341 10:01:36.115628 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 10:01:36.126177 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 10:01:36.132512 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 10:01:36.143145 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 10:01:36.149724 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 10:01:36.156141 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 10:01:36.167124 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 10:01:36.174150 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 10:01:36.192916 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 10:01:36.196442 WDT: Last reset was cold boot
351 10:01:36.200051 SPI1(PAD0) initialized at 2873684 Hz
352 10:01:36.203549 SPI5(PAD0) initialized at 992727 Hz
353 10:01:36.206456 VBOOT: Loading verstage.
354 10:01:36.213280 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 10:01:36.216405 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 10:01:36.220222 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 10:01:36.223288 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 10:01:36.230734 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 10:01:36.237075 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 10:01:36.248182 read SPI 0x96554 0xa1eb: 4596 us, 9018 KB/s, 72.144 Mbps
361 10:01:36.248267
362 10:01:36.248334
363 10:01:36.258156 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 10:01:36.261544 ARM64: Exception handlers installed.
365 10:01:36.264725 ARM64: Testing exception
366 10:01:36.264809 ARM64: Done test exception
367 10:01:36.271879 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 10:01:36.275025 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 10:01:36.289152 Probing TPM: . done!
370 10:01:36.289237 TPM ready after 0 ms
371 10:01:36.295724 Connected to device vid:did:rid of 1ae0:0028:00
372 10:01:36.302879 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 10:01:36.433160 Initialized TPM device CR50 revision 0
374 10:01:36.433348 tlcl_send_startup: Startup return code is 0
375 10:01:36.433421 TPM: setup succeeded
376 10:01:36.433500 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 10:01:36.433576 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 10:01:36.433635 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 10:01:36.433695 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 10:01:36.433769 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 10:01:36.433841 in-header: 03 07 00 00 08 00 00 00
382 10:01:36.433897 in-data: aa e4 47 04 13 02 00 00
383 10:01:36.433953 Chrome EC: UHEPI supported
384 10:01:36.475002 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 10:01:36.475207 in-header: 03 ad 00 00 08 00 00 00
386 10:01:36.475321 in-data: 00 20 20 08 00 00 00 00
387 10:01:36.475429 Phase 1
388 10:01:36.475546 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 10:01:36.475874 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 10:01:36.476007 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 10:01:36.476123 Recovery requested (1009000e)
392 10:01:36.476229 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 10:01:36.519053 tlcl_extend: response is 0
394 10:01:36.519219 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 10:01:36.519292 tlcl_extend: response is 0
396 10:01:36.519355 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 10:01:36.520917 read SPI 0x210d4 0x2173b: 15148 us, 9045 KB/s, 72.360 Mbps
398 10:01:36.527694 BS: bootblock times (exec / console): total (unknown) / 149 ms
399 10:01:36.527780
400 10:01:36.527848
401 10:01:36.539010 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 10:01:36.542119 ARM64: Exception handlers installed.
403 10:01:36.542210 ARM64: Testing exception
404 10:01:36.545498 ARM64: Done test exception
405 10:01:36.566131 pmic_efuse_setting: Set efuses in 11 msecs
406 10:01:36.569797 pmwrap_interface_init: Select PMIF_VLD_RDY
407 10:01:36.576578 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 10:01:36.580370 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 10:01:36.586819 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 10:01:36.590757 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 10:01:36.594089 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 10:01:36.601370 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 10:01:36.604506 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 10:01:36.608489 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 10:01:36.612202 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 10:01:36.620153 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 10:01:36.623701 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 10:01:36.627192 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 10:01:36.630347 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 10:01:36.638360 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 10:01:36.645956 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 10:01:36.649685 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 10:01:36.657616 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 10:01:36.660745 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 10:01:36.668329 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 10:01:36.671701 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 10:01:36.678990 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 10:01:36.682690 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 10:01:36.690009 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 10:01:36.694286 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 10:01:36.701611 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 10:01:36.705765 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 10:01:36.712660 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 10:01:36.716319 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 10:01:36.719815 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 10:01:36.723207 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 10:01:36.731073 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 10:01:36.734637 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 10:01:36.742080 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 10:01:36.745665 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 10:01:36.749396 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 10:01:36.757011 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 10:01:36.761105 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 10:01:36.765126 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 10:01:36.768984 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 10:01:36.776182 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 10:01:36.779621 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 10:01:36.783398 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 10:01:36.786880 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 10:01:36.790743 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 10:01:36.794046 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 10:01:36.801513 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 10:01:36.805373 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 10:01:36.808737 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 10:01:36.813013 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 10:01:36.816602 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 10:01:36.820228 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 10:01:36.828083 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 10:01:36.839064 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 10:01:36.842496 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 10:01:36.850028 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 10:01:36.857291 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 10:01:36.864768 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 10:01:36.868460 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 10:01:36.871712 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 10:01:36.879221 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x26
467 10:01:36.883384 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 10:01:36.891845 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 10:01:36.895282 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 10:01:36.903785 [RTC]rtc_get_frequency_meter,154: input=15, output=790
471 10:01:36.913532 [RTC]rtc_get_frequency_meter,154: input=23, output=979
472 10:01:36.922886 [RTC]rtc_get_frequency_meter,154: input=19, output=885
473 10:01:36.932721 [RTC]rtc_get_frequency_meter,154: input=17, output=837
474 10:01:36.942147 [RTC]rtc_get_frequency_meter,154: input=16, output=813
475 10:01:36.951427 [RTC]rtc_get_frequency_meter,154: input=15, output=789
476 10:01:36.961444 [RTC]rtc_get_frequency_meter,154: input=16, output=813
477 10:01:36.964598 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
478 10:01:36.972114 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
479 10:01:36.975822 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 10:01:36.979521 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 10:01:36.983148 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 10:01:36.986559 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 10:01:36.990588 ADC[4]: Raw value=902066 ID=7
484 10:01:36.994246 ADC[3]: Raw value=213336 ID=1
485 10:01:36.994363 RAM Code: 0x71
486 10:01:36.998319 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 10:01:37.002113 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 10:01:37.012894 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 10:01:37.017146 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 10:01:37.020527 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 10:01:37.024401 in-header: 03 07 00 00 08 00 00 00
492 10:01:37.028038 in-data: aa e4 47 04 13 02 00 00
493 10:01:37.032181 Chrome EC: UHEPI supported
494 10:01:37.039063 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 10:01:37.042835 in-header: 03 ed 00 00 08 00 00 00
496 10:01:37.046887 in-data: 80 20 60 08 00 00 00 00
497 10:01:37.049810 MRC: failed to locate region type 0.
498 10:01:37.053952 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 10:01:37.057397 DRAM-K: Running full calibration
500 10:01:37.064683 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 10:01:37.064852 header.status = 0x0
502 10:01:37.068501 header.version = 0x6 (expected: 0x6)
503 10:01:37.072054 header.size = 0xd00 (expected: 0xd00)
504 10:01:37.076000 header.flags = 0x0
505 10:01:37.079033 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 10:01:37.098416 read SPI 0x72590 0x1c583: 12503 us, 9285 KB/s, 74.280 Mbps
507 10:01:37.106429 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 10:01:37.110180 dram_init: ddr_geometry: 2
509 10:01:37.110282 [EMI] MDL number = 2
510 10:01:37.113751 [EMI] Get MDL freq = 0
511 10:01:37.113865 dram_init: ddr_type: 0
512 10:01:37.117438 is_discrete_lpddr4: 1
513 10:01:37.121444 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 10:01:37.121594
515 10:01:37.121693
516 10:01:37.121785 [Bian_co] ETT version 0.0.0.1
517 10:01:37.128490 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 10:01:37.128696
519 10:01:37.131683 dramc_set_vcore_voltage set vcore to 650000
520 10:01:37.134778 Read voltage for 800, 4
521 10:01:37.134879 Vio18 = 0
522 10:01:37.134954 Vcore = 650000
523 10:01:37.135019 Vdram = 0
524 10:01:37.138513 Vddq = 0
525 10:01:37.138598 Vmddr = 0
526 10:01:37.141855 dram_init: config_dvfs: 1
527 10:01:37.144848 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 10:01:37.151686 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 10:01:37.154830 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
530 10:01:37.158246 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
531 10:01:37.161648 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
532 10:01:37.164697 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
533 10:01:37.168238 MEM_TYPE=3, freq_sel=18
534 10:01:37.171433 sv_algorithm_assistance_LP4_1600
535 10:01:37.175435 ============ PULL DRAM RESETB DOWN ============
536 10:01:37.178620 ========== PULL DRAM RESETB DOWN end =========
537 10:01:37.184886 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 10:01:37.188475 ===================================
539 10:01:37.188560 LPDDR4 DRAM CONFIGURATION
540 10:01:37.191988 ===================================
541 10:01:37.195375 EX_ROW_EN[0] = 0x0
542 10:01:37.198609 EX_ROW_EN[1] = 0x0
543 10:01:37.198693 LP4Y_EN = 0x0
544 10:01:37.202112 WORK_FSP = 0x0
545 10:01:37.202197 WL = 0x2
546 10:01:37.205318 RL = 0x2
547 10:01:37.205403 BL = 0x2
548 10:01:37.208870 RPST = 0x0
549 10:01:37.208955 RD_PRE = 0x0
550 10:01:37.212366 WR_PRE = 0x1
551 10:01:37.212456 WR_PST = 0x0
552 10:01:37.215638 DBI_WR = 0x0
553 10:01:37.215723 DBI_RD = 0x0
554 10:01:37.218709 OTF = 0x1
555 10:01:37.222314 ===================================
556 10:01:37.225353 ===================================
557 10:01:37.225439 ANA top config
558 10:01:37.228640 ===================================
559 10:01:37.232271 DLL_ASYNC_EN = 0
560 10:01:37.235662 ALL_SLAVE_EN = 1
561 10:01:37.235747 NEW_RANK_MODE = 1
562 10:01:37.238982 DLL_IDLE_MODE = 1
563 10:01:37.242492 LP45_APHY_COMB_EN = 1
564 10:01:37.246027 TX_ODT_DIS = 1
565 10:01:37.246112 NEW_8X_MODE = 1
566 10:01:37.248888 ===================================
567 10:01:37.252587 ===================================
568 10:01:37.255534 data_rate = 1600
569 10:01:37.259045 CKR = 1
570 10:01:37.262294 DQ_P2S_RATIO = 8
571 10:01:37.266032 ===================================
572 10:01:37.269163 CA_P2S_RATIO = 8
573 10:01:37.272650 DQ_CA_OPEN = 0
574 10:01:37.272764 DQ_SEMI_OPEN = 0
575 10:01:37.276013 CA_SEMI_OPEN = 0
576 10:01:37.279235 CA_FULL_RATE = 0
577 10:01:37.282769 DQ_CKDIV4_EN = 1
578 10:01:37.286376 CA_CKDIV4_EN = 1
579 10:01:37.289224 CA_PREDIV_EN = 0
580 10:01:37.289310 PH8_DLY = 0
581 10:01:37.292620 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 10:01:37.296236 DQ_AAMCK_DIV = 4
583 10:01:37.299168 CA_AAMCK_DIV = 4
584 10:01:37.302636 CA_ADMCK_DIV = 4
585 10:01:37.302720 DQ_TRACK_CA_EN = 0
586 10:01:37.305978 CA_PICK = 800
587 10:01:37.309630 CA_MCKIO = 800
588 10:01:37.313115 MCKIO_SEMI = 0
589 10:01:37.316885 PLL_FREQ = 3068
590 10:01:37.320166 DQ_UI_PI_RATIO = 32
591 10:01:37.320250 CA_UI_PI_RATIO = 0
592 10:01:37.323836 ===================================
593 10:01:37.327470 ===================================
594 10:01:37.331364 memory_type:LPDDR4
595 10:01:37.331447 GP_NUM : 10
596 10:01:37.334984 SRAM_EN : 1
597 10:01:37.335071 MD32_EN : 0
598 10:01:37.338554 ===================================
599 10:01:37.342885 [ANA_INIT] >>>>>>>>>>>>>>
600 10:01:37.346082 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 10:01:37.349922 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 10:01:37.353229 ===================================
603 10:01:37.353393 data_rate = 1600,PCW = 0X7600
604 10:01:37.356764 ===================================
605 10:01:37.360215 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 10:01:37.366677 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 10:01:37.373944 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 10:01:37.377048 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 10:01:37.380648 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 10:01:37.384037 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 10:01:37.386880 [ANA_INIT] flow start
612 10:01:37.386976 [ANA_INIT] PLL >>>>>>>>
613 10:01:37.391049 [ANA_INIT] PLL <<<<<<<<
614 10:01:37.393594 [ANA_INIT] MIDPI >>>>>>>>
615 10:01:37.393678 [ANA_INIT] MIDPI <<<<<<<<
616 10:01:37.396993 [ANA_INIT] DLL >>>>>>>>
617 10:01:37.400421 [ANA_INIT] flow end
618 10:01:37.403982 ============ LP4 DIFF to SE enter ============
619 10:01:37.407370 ============ LP4 DIFF to SE exit ============
620 10:01:37.410451 [ANA_INIT] <<<<<<<<<<<<<
621 10:01:37.413797 [Flow] Enable top DCM control >>>>>
622 10:01:37.417160 [Flow] Enable top DCM control <<<<<
623 10:01:37.420909 Enable DLL master slave shuffle
624 10:01:37.424535 ==============================================================
625 10:01:37.427729 Gating Mode config
626 10:01:37.430657 ==============================================================
627 10:01:37.434334 Config description:
628 10:01:37.444302 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 10:01:37.451098 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 10:01:37.454337 SELPH_MODE 0: By rank 1: By Phase
631 10:01:37.461258 ==============================================================
632 10:01:37.464329 GAT_TRACK_EN = 1
633 10:01:37.468012 RX_GATING_MODE = 2
634 10:01:37.470878 RX_GATING_TRACK_MODE = 2
635 10:01:37.474293 SELPH_MODE = 1
636 10:01:37.474389 PICG_EARLY_EN = 1
637 10:01:37.477764 VALID_LAT_VALUE = 1
638 10:01:37.484635 ==============================================================
639 10:01:37.487769 Enter into Gating configuration >>>>
640 10:01:37.491107 Exit from Gating configuration <<<<
641 10:01:37.494822 Enter into DVFS_PRE_config >>>>>
642 10:01:37.504305 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 10:01:37.507689 Exit from DVFS_PRE_config <<<<<
644 10:01:37.511296 Enter into PICG configuration >>>>
645 10:01:37.514721 Exit from PICG configuration <<<<
646 10:01:37.517743 [RX_INPUT] configuration >>>>>
647 10:01:37.521178 [RX_INPUT] configuration <<<<<
648 10:01:37.524515 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 10:01:37.531346 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 10:01:37.535249 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 10:01:37.542300 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 10:01:37.548917 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 10:01:37.556067 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 10:01:37.559361 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 10:01:37.562474 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 10:01:37.565942 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 10:01:37.572454 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 10:01:37.575785 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 10:01:37.579386 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 10:01:37.582915 ===================================
661 10:01:37.586074 LPDDR4 DRAM CONFIGURATION
662 10:01:37.589527 ===================================
663 10:01:37.593157 EX_ROW_EN[0] = 0x0
664 10:01:37.593262 EX_ROW_EN[1] = 0x0
665 10:01:37.596130 LP4Y_EN = 0x0
666 10:01:37.596244 WORK_FSP = 0x0
667 10:01:37.599727 WL = 0x2
668 10:01:37.599809 RL = 0x2
669 10:01:37.602755 BL = 0x2
670 10:01:37.602877 RPST = 0x0
671 10:01:37.605891 RD_PRE = 0x0
672 10:01:37.605989 WR_PRE = 0x1
673 10:01:37.609199 WR_PST = 0x0
674 10:01:37.609299 DBI_WR = 0x0
675 10:01:37.612582 DBI_RD = 0x0
676 10:01:37.612655 OTF = 0x1
677 10:01:37.616383 ===================================
678 10:01:37.619581 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 10:01:37.626568 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 10:01:37.629592 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 10:01:37.632955 ===================================
682 10:01:37.636284 LPDDR4 DRAM CONFIGURATION
683 10:01:37.640138 ===================================
684 10:01:37.640221 EX_ROW_EN[0] = 0x10
685 10:01:37.643392 EX_ROW_EN[1] = 0x0
686 10:01:37.643474 LP4Y_EN = 0x0
687 10:01:37.646363 WORK_FSP = 0x0
688 10:01:37.646445 WL = 0x2
689 10:01:37.649554 RL = 0x2
690 10:01:37.649638 BL = 0x2
691 10:01:37.653380 RPST = 0x0
692 10:01:37.656651 RD_PRE = 0x0
693 10:01:37.656733 WR_PRE = 0x1
694 10:01:37.660054 WR_PST = 0x0
695 10:01:37.660137 DBI_WR = 0x0
696 10:01:37.663019 DBI_RD = 0x0
697 10:01:37.663103 OTF = 0x1
698 10:01:37.666248 ===================================
699 10:01:37.672869 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 10:01:37.676498 nWR fixed to 40
701 10:01:37.679864 [ModeRegInit_LP4] CH0 RK0
702 10:01:37.679966 [ModeRegInit_LP4] CH0 RK1
703 10:01:37.683502 [ModeRegInit_LP4] CH1 RK0
704 10:01:37.687016 [ModeRegInit_LP4] CH1 RK1
705 10:01:37.687131 match AC timing 13
706 10:01:37.693709 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 10:01:37.697137 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 10:01:37.700102 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 10:01:37.707088 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 10:01:37.710466 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 10:01:37.710578 [EMI DOE] emi_dcm 0
712 10:01:37.717065 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 10:01:37.717146 ==
714 10:01:37.720571 Dram Type= 6, Freq= 0, CH_0, rank 0
715 10:01:37.723957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 10:01:37.724067 ==
717 10:01:37.730440 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 10:01:37.733894 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 10:01:37.744321 [CA 0] Center 37 (7~68) winsize 62
720 10:01:37.747698 [CA 1] Center 37 (6~68) winsize 63
721 10:01:37.751210 [CA 2] Center 35 (5~66) winsize 62
722 10:01:37.754663 [CA 3] Center 34 (4~65) winsize 62
723 10:01:37.757653 [CA 4] Center 34 (3~65) winsize 63
724 10:01:37.761418 [CA 5] Center 34 (4~64) winsize 61
725 10:01:37.761520
726 10:01:37.764205 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 10:01:37.764333
728 10:01:37.767529 [CATrainingPosCal] consider 1 rank data
729 10:01:37.771107 u2DelayCellTimex100 = 270/100 ps
730 10:01:37.774166 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
731 10:01:37.777540 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
732 10:01:37.781357 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
733 10:01:37.788227 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
734 10:01:37.791110 CA4 delay=34 (3~65),Diff = 0 PI (0 cell)
735 10:01:37.794554 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
736 10:01:37.794657
737 10:01:37.798018 CA PerBit enable=1, Macro0, CA PI delay=34
738 10:01:37.798094
739 10:01:37.800905 [CBTSetCACLKResult] CA Dly = 34
740 10:01:37.800982 CS Dly: 5 (0~36)
741 10:01:37.801050 ==
742 10:01:37.804535 Dram Type= 6, Freq= 0, CH_0, rank 1
743 10:01:37.811431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 10:01:37.811512 ==
745 10:01:37.814620 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 10:01:37.821636 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 10:01:37.830310 [CA 0] Center 37 (6~68) winsize 63
748 10:01:37.833686 [CA 1] Center 37 (6~68) winsize 63
749 10:01:37.836744 [CA 2] Center 35 (5~66) winsize 62
750 10:01:37.840404 [CA 3] Center 35 (4~66) winsize 63
751 10:01:37.844058 [CA 4] Center 34 (3~65) winsize 63
752 10:01:37.847018 [CA 5] Center 33 (3~64) winsize 62
753 10:01:37.847095
754 10:01:37.850392 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 10:01:37.850466
756 10:01:37.853816 [CATrainingPosCal] consider 2 rank data
757 10:01:37.856948 u2DelayCellTimex100 = 270/100 ps
758 10:01:37.860497 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
759 10:01:37.863945 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
760 10:01:37.870174 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
761 10:01:37.873665 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
762 10:01:37.877082 CA4 delay=34 (3~65),Diff = 0 PI (0 cell)
763 10:01:37.880942 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
764 10:01:37.881023
765 10:01:37.883554 CA PerBit enable=1, Macro0, CA PI delay=34
766 10:01:37.883635
767 10:01:37.887204 [CBTSetCACLKResult] CA Dly = 34
768 10:01:37.887305 CS Dly: 6 (0~38)
769 10:01:37.887399
770 10:01:37.890359 ----->DramcWriteLeveling(PI) begin...
771 10:01:37.890476 ==
772 10:01:37.893818 Dram Type= 6, Freq= 0, CH_0, rank 0
773 10:01:37.901481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 10:01:37.901563 ==
775 10:01:37.901632 Write leveling (Byte 0): 30 => 30
776 10:01:37.905381 Write leveling (Byte 1): 29 => 29
777 10:01:37.908684 DramcWriteLeveling(PI) end<-----
778 10:01:37.908762
779 10:01:37.908826 ==
780 10:01:37.912664 Dram Type= 6, Freq= 0, CH_0, rank 0
781 10:01:37.916275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 10:01:37.916351 ==
783 10:01:37.919246 [Gating] SW mode calibration
784 10:01:37.926560 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 10:01:37.930197 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 10:01:37.937139 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 10:01:37.940726 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 10:01:37.943801 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
789 10:01:37.950292 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
790 10:01:37.953757 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 10:01:37.957165 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 10:01:37.963724 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 10:01:37.967211 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 10:01:37.970319 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 10:01:37.973753 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 10:01:37.980838 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 10:01:37.984199 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 10:01:37.987191 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 10:01:37.994352 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 10:01:37.997522 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 10:01:38.001359 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 10:01:38.007660 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 10:01:38.010673 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 10:01:38.013996 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
805 10:01:38.020851 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
806 10:01:38.024346 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 10:01:38.027668 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 10:01:38.034664 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 10:01:38.037942 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 10:01:38.040945 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 10:01:38.044418 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 10:01:38.051268 0 9 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
813 10:01:38.054636 0 9 12 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
814 10:01:38.057750 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 10:01:38.064732 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 10:01:38.068270 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 10:01:38.071205 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 10:01:38.078416 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 10:01:38.081332 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 10:01:38.084799 0 10 8 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
821 10:01:38.091389 0 10 12 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
822 10:01:38.095184 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 10:01:38.098443 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 10:01:38.101382 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 10:01:38.108553 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 10:01:38.111903 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 10:01:38.114869 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 10:01:38.122187 0 11 8 | B1->B0 | 2626 2828 | 0 0 | (0 0) (0 0)
829 10:01:38.125245 0 11 12 | B1->B0 | 3636 4343 | 0 0 | (0 0) (0 0)
830 10:01:38.128511 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 10:01:38.135530 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 10:01:38.138755 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 10:01:38.142075 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 10:01:38.145665 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 10:01:38.152593 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 10:01:38.155642 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
837 10:01:38.159129 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 10:01:38.165863 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 10:01:38.169442 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 10:01:38.172821 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 10:01:38.179200 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 10:01:38.182383 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 10:01:38.186059 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 10:01:38.189649 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 10:01:38.196005 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 10:01:38.199452 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 10:01:38.203283 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 10:01:38.209642 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 10:01:38.212944 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 10:01:38.216064 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 10:01:38.223114 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 10:01:38.226274 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
853 10:01:38.229589 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
854 10:01:38.236441 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
855 10:01:38.236525 Total UI for P1: 0, mck2ui 16
856 10:01:38.243215 best dqsien dly found for B0: ( 0, 14, 8)
857 10:01:38.243299 Total UI for P1: 0, mck2ui 16
858 10:01:38.246202 best dqsien dly found for B1: ( 0, 14, 10)
859 10:01:38.253095 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
860 10:01:38.256478 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
861 10:01:38.256558
862 10:01:38.259608 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 10:01:38.263219 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
864 10:01:38.266602 [Gating] SW calibration Done
865 10:01:38.266703 ==
866 10:01:38.270091 Dram Type= 6, Freq= 0, CH_0, rank 0
867 10:01:38.273419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 10:01:38.273492 ==
869 10:01:38.273559 RX Vref Scan: 0
870 10:01:38.273619
871 10:01:38.276595 RX Vref 0 -> 0, step: 1
872 10:01:38.276666
873 10:01:38.280178 RX Delay -130 -> 252, step: 16
874 10:01:38.283655 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
875 10:01:38.286633 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
876 10:01:38.293905 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
877 10:01:38.297090 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
878 10:01:38.300128 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
879 10:01:38.303693 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
880 10:01:38.306750 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
881 10:01:38.310914 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
882 10:01:38.317523 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
883 10:01:38.320494 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
884 10:01:38.323754 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
885 10:01:38.327157 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
886 10:01:38.330744 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
887 10:01:38.337239 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
888 10:01:38.340731 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
889 10:01:38.343772 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
890 10:01:38.343857 ==
891 10:01:38.347289 Dram Type= 6, Freq= 0, CH_0, rank 0
892 10:01:38.350454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 10:01:38.350564 ==
894 10:01:38.353880 DQS Delay:
895 10:01:38.353982 DQS0 = 0, DQS1 = 0
896 10:01:38.357332 DQM Delay:
897 10:01:38.357415 DQM0 = 85, DQM1 = 78
898 10:01:38.357481 DQ Delay:
899 10:01:38.360640 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
900 10:01:38.363959 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =85
901 10:01:38.367664 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
902 10:01:38.370965 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
903 10:01:38.371048
904 10:01:38.371113
905 10:01:38.371174 ==
906 10:01:38.373962 Dram Type= 6, Freq= 0, CH_0, rank 0
907 10:01:38.380856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 10:01:38.380939 ==
909 10:01:38.381005
910 10:01:38.381065
911 10:01:38.381147 TX Vref Scan disable
912 10:01:38.384735 == TX Byte 0 ==
913 10:01:38.387756 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
914 10:01:38.391411 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
915 10:01:38.394792 == TX Byte 1 ==
916 10:01:38.398348 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
917 10:01:38.401376 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
918 10:01:38.404986 ==
919 10:01:38.408523 Dram Type= 6, Freq= 0, CH_0, rank 0
920 10:01:38.411321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 10:01:38.411405 ==
922 10:01:38.423536 TX Vref=22, minBit 5, minWin=27, winSum=441
923 10:01:38.427043 TX Vref=24, minBit 5, minWin=27, winSum=444
924 10:01:38.430287 TX Vref=26, minBit 5, minWin=27, winSum=445
925 10:01:38.433778 TX Vref=28, minBit 1, minWin=28, winSum=450
926 10:01:38.437165 TX Vref=30, minBit 2, minWin=28, winSum=456
927 10:01:38.443738 TX Vref=32, minBit 12, minWin=27, winSum=450
928 10:01:38.447397 [TxChooseVref] Worse bit 2, Min win 28, Win sum 456, Final Vref 30
929 10:01:38.447481
930 10:01:38.450444 Final TX Range 1 Vref 30
931 10:01:38.450528
932 10:01:38.450594 ==
933 10:01:38.453811 Dram Type= 6, Freq= 0, CH_0, rank 0
934 10:01:38.457396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 10:01:38.457479 ==
936 10:01:38.457545
937 10:01:38.460776
938 10:01:38.460858 TX Vref Scan disable
939 10:01:38.464195 == TX Byte 0 ==
940 10:01:38.467045 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
941 10:01:38.470765 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
942 10:01:38.473862 == TX Byte 1 ==
943 10:01:38.477230 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
944 10:01:38.480749 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
945 10:01:38.480832
946 10:01:38.484345 [DATLAT]
947 10:01:38.484428 Freq=800, CH0 RK0
948 10:01:38.484494
949 10:01:38.487276 DATLAT Default: 0xa
950 10:01:38.487358 0, 0xFFFF, sum = 0
951 10:01:38.490735 1, 0xFFFF, sum = 0
952 10:01:38.490818 2, 0xFFFF, sum = 0
953 10:01:38.494090 3, 0xFFFF, sum = 0
954 10:01:38.494174 4, 0xFFFF, sum = 0
955 10:01:38.497308 5, 0xFFFF, sum = 0
956 10:01:38.497392 6, 0xFFFF, sum = 0
957 10:01:38.500943 7, 0xFFFF, sum = 0
958 10:01:38.501107 8, 0xFFFF, sum = 0
959 10:01:38.504266 9, 0x0, sum = 1
960 10:01:38.504350 10, 0x0, sum = 2
961 10:01:38.507781 11, 0x0, sum = 3
962 10:01:38.507865 12, 0x0, sum = 4
963 10:01:38.510681 best_step = 10
964 10:01:38.510762
965 10:01:38.510827 ==
966 10:01:38.514267 Dram Type= 6, Freq= 0, CH_0, rank 0
967 10:01:38.517825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 10:01:38.517908 ==
969 10:01:38.520795 RX Vref Scan: 1
970 10:01:38.520877
971 10:01:38.520942 Set Vref Range= 32 -> 127
972 10:01:38.521002
973 10:01:38.524344 RX Vref 32 -> 127, step: 1
974 10:01:38.524426
975 10:01:38.528175 RX Delay -95 -> 252, step: 8
976 10:01:38.528257
977 10:01:38.531098 Set Vref, RX VrefLevel [Byte0]: 32
978 10:01:38.534227 [Byte1]: 32
979 10:01:38.534308
980 10:01:38.539099 Set Vref, RX VrefLevel [Byte0]: 33
981 10:01:38.541399 [Byte1]: 33
982 10:01:38.541596
983 10:01:38.545302 Set Vref, RX VrefLevel [Byte0]: 34
984 10:01:38.548081 [Byte1]: 34
985 10:01:38.551657
986 10:01:38.551747 Set Vref, RX VrefLevel [Byte0]: 35
987 10:01:38.554993 [Byte1]: 35
988 10:01:38.559130
989 10:01:38.559203 Set Vref, RX VrefLevel [Byte0]: 36
990 10:01:38.562635 [Byte1]: 36
991 10:01:38.567113
992 10:01:38.567191 Set Vref, RX VrefLevel [Byte0]: 37
993 10:01:38.571179 [Byte1]: 37
994 10:01:38.575166
995 10:01:38.575276 Set Vref, RX VrefLevel [Byte0]: 38
996 10:01:38.578629 [Byte1]: 38
997 10:01:38.582197
998 10:01:38.582309 Set Vref, RX VrefLevel [Byte0]: 39
999 10:01:38.586177 [Byte1]: 39
1000 10:01:38.589974
1001 10:01:38.590101 Set Vref, RX VrefLevel [Byte0]: 40
1002 10:01:38.593454 [Byte1]: 40
1003 10:01:38.597299
1004 10:01:38.597400 Set Vref, RX VrefLevel [Byte0]: 41
1005 10:01:38.600923 [Byte1]: 41
1006 10:01:38.604768
1007 10:01:38.604878 Set Vref, RX VrefLevel [Byte0]: 42
1008 10:01:38.608532 [Byte1]: 42
1009 10:01:38.612334
1010 10:01:38.612409 Set Vref, RX VrefLevel [Byte0]: 43
1011 10:01:38.615651 [Byte1]: 43
1012 10:01:38.620439
1013 10:01:38.620516 Set Vref, RX VrefLevel [Byte0]: 44
1014 10:01:38.623325 [Byte1]: 44
1015 10:01:38.628087
1016 10:01:38.628163 Set Vref, RX VrefLevel [Byte0]: 45
1017 10:01:38.631078 [Byte1]: 45
1018 10:01:38.635553
1019 10:01:38.635625 Set Vref, RX VrefLevel [Byte0]: 46
1020 10:01:38.638799 [Byte1]: 46
1021 10:01:38.642856
1022 10:01:38.642993 Set Vref, RX VrefLevel [Byte0]: 47
1023 10:01:38.646185 [Byte1]: 47
1024 10:01:38.650279
1025 10:01:38.650383 Set Vref, RX VrefLevel [Byte0]: 48
1026 10:01:38.653781 [Byte1]: 48
1027 10:01:38.658133
1028 10:01:38.658231 Set Vref, RX VrefLevel [Byte0]: 49
1029 10:01:38.661556 [Byte1]: 49
1030 10:01:38.665461
1031 10:01:38.665565 Set Vref, RX VrefLevel [Byte0]: 50
1032 10:01:38.669001 [Byte1]: 50
1033 10:01:38.673437
1034 10:01:38.673542 Set Vref, RX VrefLevel [Byte0]: 51
1035 10:01:38.676650 [Byte1]: 51
1036 10:01:38.680954
1037 10:01:38.681056 Set Vref, RX VrefLevel [Byte0]: 52
1038 10:01:38.684035 [Byte1]: 52
1039 10:01:38.688903
1040 10:01:38.689005 Set Vref, RX VrefLevel [Byte0]: 53
1041 10:01:38.691769 [Byte1]: 53
1042 10:01:38.696047
1043 10:01:38.696117 Set Vref, RX VrefLevel [Byte0]: 54
1044 10:01:38.699213 [Byte1]: 54
1045 10:01:38.703731
1046 10:01:38.703807 Set Vref, RX VrefLevel [Byte0]: 55
1047 10:01:38.707096 [Byte1]: 55
1048 10:01:38.711094
1049 10:01:38.711169 Set Vref, RX VrefLevel [Byte0]: 56
1050 10:01:38.714562 [Byte1]: 56
1051 10:01:38.718797
1052 10:01:38.722097 Set Vref, RX VrefLevel [Byte0]: 57
1053 10:01:38.722210 [Byte1]: 57
1054 10:01:38.726225
1055 10:01:38.726298 Set Vref, RX VrefLevel [Byte0]: 58
1056 10:01:38.729740 [Byte1]: 58
1057 10:01:38.733914
1058 10:01:38.734018 Set Vref, RX VrefLevel [Byte0]: 59
1059 10:01:38.737527 [Byte1]: 59
1060 10:01:38.741817
1061 10:01:38.741912 Set Vref, RX VrefLevel [Byte0]: 60
1062 10:01:38.745190 [Byte1]: 60
1063 10:01:38.749199
1064 10:01:38.749271 Set Vref, RX VrefLevel [Byte0]: 61
1065 10:01:38.752694 [Byte1]: 61
1066 10:01:38.756734
1067 10:01:38.756805 Set Vref, RX VrefLevel [Byte0]: 62
1068 10:01:38.760408 [Byte1]: 62
1069 10:01:38.764490
1070 10:01:38.764568 Set Vref, RX VrefLevel [Byte0]: 63
1071 10:01:38.767983 [Byte1]: 63
1072 10:01:38.771750
1073 10:01:38.771832 Set Vref, RX VrefLevel [Byte0]: 64
1074 10:01:38.775304 [Byte1]: 64
1075 10:01:38.779932
1076 10:01:38.780032 Set Vref, RX VrefLevel [Byte0]: 65
1077 10:01:38.782756 [Byte1]: 65
1078 10:01:38.787060
1079 10:01:38.787150 Set Vref, RX VrefLevel [Byte0]: 66
1080 10:01:38.790403 [Byte1]: 66
1081 10:01:38.794943
1082 10:01:38.795057 Set Vref, RX VrefLevel [Byte0]: 67
1083 10:01:38.798286 [Byte1]: 67
1084 10:01:38.802221
1085 10:01:38.802293 Set Vref, RX VrefLevel [Byte0]: 68
1086 10:01:38.805827 [Byte1]: 68
1087 10:01:38.810326
1088 10:01:38.810430 Set Vref, RX VrefLevel [Byte0]: 69
1089 10:01:38.813376 [Byte1]: 69
1090 10:01:38.817906
1091 10:01:38.818003 Set Vref, RX VrefLevel [Byte0]: 70
1092 10:01:38.821080 [Byte1]: 70
1093 10:01:38.825322
1094 10:01:38.825429 Set Vref, RX VrefLevel [Byte0]: 71
1095 10:01:38.828395 [Byte1]: 71
1096 10:01:38.832840
1097 10:01:38.832944 Set Vref, RX VrefLevel [Byte0]: 72
1098 10:01:38.835982 [Byte1]: 72
1099 10:01:38.840337
1100 10:01:38.840410 Set Vref, RX VrefLevel [Byte0]: 73
1101 10:01:38.843450 [Byte1]: 73
1102 10:01:38.848134
1103 10:01:38.848240 Set Vref, RX VrefLevel [Byte0]: 74
1104 10:01:38.854620 [Byte1]: 74
1105 10:01:38.854720
1106 10:01:38.857809 Set Vref, RX VrefLevel [Byte0]: 75
1107 10:01:38.860895 [Byte1]: 75
1108 10:01:38.860991
1109 10:01:38.864295 Set Vref, RX VrefLevel [Byte0]: 76
1110 10:01:38.867885 [Byte1]: 76
1111 10:01:38.867985
1112 10:01:38.871355 Set Vref, RX VrefLevel [Byte0]: 77
1113 10:01:38.874346 [Byte1]: 77
1114 10:01:38.878547
1115 10:01:38.878652 Final RX Vref Byte 0 = 62 to rank0
1116 10:01:38.881778 Final RX Vref Byte 1 = 57 to rank0
1117 10:01:38.885576 Final RX Vref Byte 0 = 62 to rank1
1118 10:01:38.888361 Final RX Vref Byte 1 = 57 to rank1==
1119 10:01:38.892084 Dram Type= 6, Freq= 0, CH_0, rank 0
1120 10:01:38.894795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1121 10:01:38.898242 ==
1122 10:01:38.898324 DQS Delay:
1123 10:01:38.898387 DQS0 = 0, DQS1 = 0
1124 10:01:38.902136 DQM Delay:
1125 10:01:38.902217 DQM0 = 88, DQM1 = 79
1126 10:01:38.904998 DQ Delay:
1127 10:01:38.908601 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1128 10:01:38.908712 DQ4 =92, DQ5 =76, DQ6 =96, DQ7 =92
1129 10:01:38.911985 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1130 10:01:38.915322 DQ12 =84, DQ13 =80, DQ14 =92, DQ15 =88
1131 10:01:38.915394
1132 10:01:38.918803
1133 10:01:38.925537 [DQSOSCAuto] RK0, (LSB)MR18= 0x240c, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
1134 10:01:38.928568 CH0 RK0: MR19=606, MR18=240C
1135 10:01:38.935200 CH0_RK0: MR19=0x606, MR18=0x240C, DQSOSC=400, MR23=63, INC=92, DEC=61
1136 10:01:38.935292
1137 10:01:38.938723 ----->DramcWriteLeveling(PI) begin...
1138 10:01:38.938827 ==
1139 10:01:38.942188 Dram Type= 6, Freq= 0, CH_0, rank 1
1140 10:01:38.945754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1141 10:01:38.945852 ==
1142 10:01:38.948681 Write leveling (Byte 0): 28 => 28
1143 10:01:38.952268 Write leveling (Byte 1): 28 => 28
1144 10:01:38.955337 DramcWriteLeveling(PI) end<-----
1145 10:01:38.955408
1146 10:01:38.955468 ==
1147 10:01:38.958701 Dram Type= 6, Freq= 0, CH_0, rank 1
1148 10:01:38.962256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1149 10:01:38.962352 ==
1150 10:01:38.965971 [Gating] SW mode calibration
1151 10:01:38.972340 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1152 10:01:38.976080 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1153 10:01:39.019894 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1154 10:01:39.020245 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1155 10:01:39.020378 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1156 10:01:39.020842 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 10:01:39.020914 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 10:01:39.021156 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 10:01:39.021224 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 10:01:39.021464 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 10:01:39.021973 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 10:01:39.022040 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 10:01:39.064149 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 10:01:39.064750 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 10:01:39.065037 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 10:01:39.065306 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 10:01:39.065372 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 10:01:39.065633 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 10:01:39.065881 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1170 10:01:39.066344 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1171 10:01:39.066771 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1172 10:01:39.066846 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 10:01:39.075530 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 10:01:39.075817 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 10:01:39.078842 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 10:01:39.082589 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 10:01:39.085385 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 10:01:39.091997 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 10:01:39.095346 0 9 8 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
1180 10:01:39.099066 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1181 10:01:39.105818 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 10:01:39.108953 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 10:01:39.112244 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 10:01:39.119128 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 10:01:39.122273 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1186 10:01:39.125600 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
1187 10:01:39.132775 0 10 8 | B1->B0 | 3232 2727 | 0 0 | (0 1) (0 0)
1188 10:01:39.135688 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1189 10:01:39.139123 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 10:01:39.145822 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 10:01:39.149492 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 10:01:39.153151 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 10:01:39.156953 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 10:01:39.160465 0 11 4 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
1195 10:01:39.168081 0 11 8 | B1->B0 | 2c2c 3d3d | 1 0 | (1 1) (1 1)
1196 10:01:39.171291 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1197 10:01:39.174852 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 10:01:39.178206 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 10:01:39.182469 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 10:01:39.188572 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 10:01:39.192109 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 10:01:39.195423 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1203 10:01:39.202499 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1204 10:01:39.205683 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 10:01:39.208656 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 10:01:39.215720 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 10:01:39.218881 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 10:01:39.222174 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 10:01:39.228983 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 10:01:39.232422 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 10:01:39.235625 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 10:01:39.242268 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 10:01:39.245803 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 10:01:39.249341 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 10:01:39.252727 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 10:01:39.259196 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 10:01:39.262581 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 10:01:39.266022 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1219 10:01:39.269383 Total UI for P1: 0, mck2ui 16
1220 10:01:39.272926 best dqsien dly found for B0: ( 0, 14, 2)
1221 10:01:39.279463 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1222 10:01:39.282813 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1223 10:01:39.286359 Total UI for P1: 0, mck2ui 16
1224 10:01:39.289660 best dqsien dly found for B1: ( 0, 14, 8)
1225 10:01:39.292980 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1226 10:01:39.296147 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1227 10:01:39.296229
1228 10:01:39.299612 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1229 10:01:39.302771 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1230 10:01:39.306316 [Gating] SW calibration Done
1231 10:01:39.306398 ==
1232 10:01:39.309876 Dram Type= 6, Freq= 0, CH_0, rank 1
1233 10:01:39.313471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1234 10:01:39.313553 ==
1235 10:01:39.316331 RX Vref Scan: 0
1236 10:01:39.316411
1237 10:01:39.316475 RX Vref 0 -> 0, step: 1
1238 10:01:39.316535
1239 10:01:39.319935 RX Delay -130 -> 252, step: 16
1240 10:01:39.326600 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1241 10:01:39.330276 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1242 10:01:39.333696 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1243 10:01:39.336607 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1244 10:01:39.340052 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1245 10:01:39.343651 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1246 10:01:39.350231 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1247 10:01:39.353652 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1248 10:01:39.357129 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1249 10:01:39.360535 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1250 10:01:39.363885 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1251 10:01:39.370417 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1252 10:01:39.374079 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1253 10:01:39.377323 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1254 10:01:39.380210 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1255 10:01:39.383722 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1256 10:01:39.383804 ==
1257 10:01:39.387225 Dram Type= 6, Freq= 0, CH_0, rank 1
1258 10:01:39.393655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1259 10:01:39.393737 ==
1260 10:01:39.393802 DQS Delay:
1261 10:01:39.397571 DQS0 = 0, DQS1 = 0
1262 10:01:39.397652 DQM Delay:
1263 10:01:39.397716 DQM0 = 84, DQM1 = 76
1264 10:01:39.400831 DQ Delay:
1265 10:01:39.404065 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1266 10:01:39.407176 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
1267 10:01:39.410494 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1268 10:01:39.413895 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1269 10:01:39.413977
1270 10:01:39.414042
1271 10:01:39.414101 ==
1272 10:01:39.417358 Dram Type= 6, Freq= 0, CH_0, rank 1
1273 10:01:39.420997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1274 10:01:39.421079 ==
1275 10:01:39.421143
1276 10:01:39.421203
1277 10:01:39.423920 TX Vref Scan disable
1278 10:01:39.424001 == TX Byte 0 ==
1279 10:01:39.430774 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1280 10:01:39.433881 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1281 10:01:39.433963 == TX Byte 1 ==
1282 10:01:39.440786 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1283 10:01:39.443977 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1284 10:01:39.444058 ==
1285 10:01:39.447323 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 10:01:39.450632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1287 10:01:39.450714 ==
1288 10:01:39.464467 TX Vref=22, minBit 2, minWin=27, winSum=441
1289 10:01:39.467940 TX Vref=24, minBit 3, minWin=27, winSum=444
1290 10:01:39.471239 TX Vref=26, minBit 4, minWin=27, winSum=448
1291 10:01:39.474350 TX Vref=28, minBit 9, minWin=27, winSum=453
1292 10:01:39.477863 TX Vref=30, minBit 9, minWin=27, winSum=452
1293 10:01:39.481454 TX Vref=32, minBit 0, minWin=28, winSum=450
1294 10:01:39.488428 [TxChooseVref] Worse bit 0, Min win 28, Win sum 450, Final Vref 32
1295 10:01:39.488510
1296 10:01:39.491079 Final TX Range 1 Vref 32
1297 10:01:39.491161
1298 10:01:39.491224 ==
1299 10:01:39.494661 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 10:01:39.498112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 10:01:39.498193 ==
1302 10:01:39.498256
1303 10:01:39.498315
1304 10:01:39.501104 TX Vref Scan disable
1305 10:01:39.504623 == TX Byte 0 ==
1306 10:01:39.507926 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1307 10:01:39.511998 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1308 10:01:39.514791 == TX Byte 1 ==
1309 10:01:39.517963 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1310 10:01:39.521802 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1311 10:01:39.521884
1312 10:01:39.525119 [DATLAT]
1313 10:01:39.525199 Freq=800, CH0 RK1
1314 10:01:39.525263
1315 10:01:39.528049 DATLAT Default: 0xa
1316 10:01:39.528130 0, 0xFFFF, sum = 0
1317 10:01:39.531444 1, 0xFFFF, sum = 0
1318 10:01:39.531526 2, 0xFFFF, sum = 0
1319 10:01:39.534792 3, 0xFFFF, sum = 0
1320 10:01:39.534902 4, 0xFFFF, sum = 0
1321 10:01:39.538989 5, 0xFFFF, sum = 0
1322 10:01:39.539070 6, 0xFFFF, sum = 0
1323 10:01:39.541938 7, 0xFFFF, sum = 0
1324 10:01:39.542047 8, 0xFFFF, sum = 0
1325 10:01:39.545223 9, 0x0, sum = 1
1326 10:01:39.545305 10, 0x0, sum = 2
1327 10:01:39.548346 11, 0x0, sum = 3
1328 10:01:39.548427 12, 0x0, sum = 4
1329 10:01:39.552035 best_step = 10
1330 10:01:39.552115
1331 10:01:39.552179 ==
1332 10:01:39.555382 Dram Type= 6, Freq= 0, CH_0, rank 1
1333 10:01:39.558631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1334 10:01:39.558741 ==
1335 10:01:39.558831 RX Vref Scan: 0
1336 10:01:39.558920
1337 10:01:39.562268 RX Vref 0 -> 0, step: 1
1338 10:01:39.562372
1339 10:01:39.565267 RX Delay -95 -> 252, step: 8
1340 10:01:39.568839 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1341 10:01:39.575319 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1342 10:01:39.578612 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1343 10:01:39.582153 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1344 10:01:39.585455 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1345 10:01:39.588753 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1346 10:01:39.592206 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1347 10:01:39.599120 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1348 10:01:39.602055 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1349 10:01:39.605695 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1350 10:01:39.608670 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1351 10:01:39.612740 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1352 10:01:39.618786 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1353 10:01:39.622642 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1354 10:01:39.625574 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1355 10:01:39.629031 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1356 10:01:39.629112 ==
1357 10:01:39.632499 Dram Type= 6, Freq= 0, CH_0, rank 1
1358 10:01:39.639255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1359 10:01:39.639336 ==
1360 10:01:39.639398 DQS Delay:
1361 10:01:39.642239 DQS0 = 0, DQS1 = 0
1362 10:01:39.642346 DQM Delay:
1363 10:01:39.642443 DQM0 = 87, DQM1 = 78
1364 10:01:39.645626 DQ Delay:
1365 10:01:39.649042 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1366 10:01:39.652353 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1367 10:01:39.652433 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1368 10:01:39.659159 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88
1369 10:01:39.659266
1370 10:01:39.659358
1371 10:01:39.665827 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c17, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
1372 10:01:39.669447 CH0 RK1: MR19=606, MR18=2C17
1373 10:01:39.676231 CH0_RK1: MR19=0x606, MR18=0x2C17, DQSOSC=398, MR23=63, INC=93, DEC=62
1374 10:01:39.679183 [RxdqsGatingPostProcess] freq 800
1375 10:01:39.682807 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1376 10:01:39.686160 Pre-setting of DQS Precalculation
1377 10:01:39.689692 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1378 10:01:39.692923 ==
1379 10:01:39.696418 Dram Type= 6, Freq= 0, CH_1, rank 0
1380 10:01:39.699717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1381 10:01:39.699799 ==
1382 10:01:39.703265 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1383 10:01:39.709436 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1384 10:01:39.719243 [CA 0] Center 36 (6~66) winsize 61
1385 10:01:39.722615 [CA 1] Center 36 (6~66) winsize 61
1386 10:01:39.726028 [CA 2] Center 35 (5~65) winsize 61
1387 10:01:39.729440 [CA 3] Center 33 (3~64) winsize 62
1388 10:01:39.732622 [CA 4] Center 34 (4~65) winsize 62
1389 10:01:39.735858 [CA 5] Center 33 (3~64) winsize 62
1390 10:01:39.735940
1391 10:01:39.739415 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1392 10:01:39.739526
1393 10:01:39.742828 [CATrainingPosCal] consider 1 rank data
1394 10:01:39.745904 u2DelayCellTimex100 = 270/100 ps
1395 10:01:39.749383 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1396 10:01:39.752785 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1397 10:01:39.759359 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1398 10:01:39.762651 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1399 10:01:39.766277 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1400 10:01:39.769343 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1401 10:01:39.769424
1402 10:01:39.773053 CA PerBit enable=1, Macro0, CA PI delay=33
1403 10:01:39.773136
1404 10:01:39.776289 [CBTSetCACLKResult] CA Dly = 33
1405 10:01:39.776370 CS Dly: 4 (0~35)
1406 10:01:39.776435 ==
1407 10:01:39.779890 Dram Type= 6, Freq= 0, CH_1, rank 1
1408 10:01:39.786258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1409 10:01:39.786339 ==
1410 10:01:39.789856 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1411 10:01:39.796308 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1412 10:01:39.805340 [CA 0] Center 36 (6~66) winsize 61
1413 10:01:39.808803 [CA 1] Center 36 (6~66) winsize 61
1414 10:01:39.811983 [CA 2] Center 34 (4~65) winsize 62
1415 10:01:39.815847 [CA 3] Center 33 (3~64) winsize 62
1416 10:01:39.819298 [CA 4] Center 34 (4~65) winsize 62
1417 10:01:39.822673 [CA 5] Center 33 (3~64) winsize 62
1418 10:01:39.822754
1419 10:01:39.826217 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1420 10:01:39.826298
1421 10:01:39.829853 [CATrainingPosCal] consider 2 rank data
1422 10:01:39.833316 u2DelayCellTimex100 = 270/100 ps
1423 10:01:39.836881 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1424 10:01:39.840638 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1425 10:01:39.844445 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1426 10:01:39.848062 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1427 10:01:39.852121 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1428 10:01:39.855477 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1429 10:01:39.855562
1430 10:01:39.858951 CA PerBit enable=1, Macro0, CA PI delay=33
1431 10:01:39.859033
1432 10:01:39.862511 [CBTSetCACLKResult] CA Dly = 33
1433 10:01:39.862592 CS Dly: 5 (0~37)
1434 10:01:39.862656
1435 10:01:39.865479 ----->DramcWriteLeveling(PI) begin...
1436 10:01:39.865554 ==
1437 10:01:39.868783 Dram Type= 6, Freq= 0, CH_1, rank 0
1438 10:01:39.875586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1439 10:01:39.875669 ==
1440 10:01:39.878720 Write leveling (Byte 0): 27 => 27
1441 10:01:39.882367 Write leveling (Byte 1): 27 => 27
1442 10:01:39.882448 DramcWriteLeveling(PI) end<-----
1443 10:01:39.882512
1444 10:01:39.885630 ==
1445 10:01:39.889074 Dram Type= 6, Freq= 0, CH_1, rank 0
1446 10:01:39.892863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 10:01:39.892971 ==
1448 10:01:39.896152 [Gating] SW mode calibration
1449 10:01:39.902527 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1450 10:01:39.906255 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1451 10:01:39.912702 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1452 10:01:39.915978 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1453 10:01:39.919848 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1454 10:01:39.925896 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 10:01:39.929039 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 10:01:39.932605 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 10:01:39.936115 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 10:01:39.942533 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 10:01:39.945866 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 10:01:39.949666 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 10:01:39.956014 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 10:01:39.959425 0 7 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1463 10:01:39.962904 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1464 10:01:39.969755 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 10:01:39.972935 0 7 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1466 10:01:39.976433 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1467 10:01:39.982607 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1468 10:01:39.986335 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1469 10:01:39.989981 0 8 8 | B1->B0 | 2323 2323 | 1 0 | (0 1) (0 1)
1470 10:01:39.993032 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 10:01:39.999729 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 10:01:40.003045 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 10:01:40.006492 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 10:01:40.013347 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 10:01:40.016585 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 10:01:40.020390 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 10:01:40.027049 0 9 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1478 10:01:40.030291 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 10:01:40.033684 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 10:01:40.040284 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 10:01:40.043297 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 10:01:40.047118 0 9 28 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1483 10:01:40.050105 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 10:01:40.056767 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 10:01:40.059912 0 10 8 | B1->B0 | 2c2c 2f2f | 1 1 | (1 0) (1 0)
1486 10:01:40.063379 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 10:01:40.070312 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 10:01:40.073436 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 10:01:40.076850 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 10:01:40.083844 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 10:01:40.087311 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 10:01:40.090609 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1493 10:01:40.097082 0 11 8 | B1->B0 | 3131 3030 | 0 0 | (0 0) (0 0)
1494 10:01:40.100560 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 10:01:40.104018 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 10:01:40.107320 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 10:01:40.114024 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 10:01:40.117173 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 10:01:40.120808 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 10:01:40.127498 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 10:01:40.130980 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1502 10:01:40.134111 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 10:01:40.141312 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 10:01:40.144078 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 10:01:40.147639 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 10:01:40.154553 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 10:01:40.157429 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 10:01:40.160870 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 10:01:40.167682 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 10:01:40.171110 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 10:01:40.174370 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 10:01:40.178130 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 10:01:40.184585 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 10:01:40.187867 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 10:01:40.191476 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 10:01:40.197751 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1517 10:01:40.201170 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1518 10:01:40.204498 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1519 10:01:40.208061 Total UI for P1: 0, mck2ui 16
1520 10:01:40.211418 best dqsien dly found for B0: ( 0, 14, 6)
1521 10:01:40.214528 Total UI for P1: 0, mck2ui 16
1522 10:01:40.218229 best dqsien dly found for B1: ( 0, 14, 6)
1523 10:01:40.221221 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1524 10:01:40.224622 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1525 10:01:40.224703
1526 10:01:40.228093 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1527 10:01:40.231585 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1528 10:01:40.234578 [Gating] SW calibration Done
1529 10:01:40.234660 ==
1530 10:01:40.238274 Dram Type= 6, Freq= 0, CH_1, rank 0
1531 10:01:40.244781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1532 10:01:40.244867 ==
1533 10:01:40.244932 RX Vref Scan: 0
1534 10:01:40.244993
1535 10:01:40.248309 RX Vref 0 -> 0, step: 1
1536 10:01:40.248390
1537 10:01:40.251787 RX Delay -130 -> 252, step: 16
1538 10:01:40.254741 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1539 10:01:40.258358 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1540 10:01:40.261735 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1541 10:01:40.264625 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1542 10:01:40.271643 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1543 10:01:40.275187 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1544 10:01:40.278378 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1545 10:01:40.281622 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1546 10:01:40.285319 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1547 10:01:40.288815 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1548 10:01:40.295530 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1549 10:01:40.298688 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1550 10:01:40.301598 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1551 10:01:40.305047 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1552 10:01:40.312063 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1553 10:01:40.315993 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1554 10:01:40.316137 ==
1555 10:01:40.318849 Dram Type= 6, Freq= 0, CH_1, rank 0
1556 10:01:40.321822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1557 10:01:40.321982 ==
1558 10:01:40.322082 DQS Delay:
1559 10:01:40.325254 DQS0 = 0, DQS1 = 0
1560 10:01:40.325355 DQM Delay:
1561 10:01:40.328808 DQM0 = 81, DQM1 = 75
1562 10:01:40.328890 DQ Delay:
1563 10:01:40.332064 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1564 10:01:40.335591 DQ4 =85, DQ5 =85, DQ6 =93, DQ7 =69
1565 10:01:40.338678 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1566 10:01:40.342394 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =77
1567 10:01:40.342536
1568 10:01:40.342600
1569 10:01:40.342660 ==
1570 10:01:40.345578 Dram Type= 6, Freq= 0, CH_1, rank 0
1571 10:01:40.349048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1572 10:01:40.349130 ==
1573 10:01:40.352016
1574 10:01:40.352096
1575 10:01:40.352161 TX Vref Scan disable
1576 10:01:40.355422 == TX Byte 0 ==
1577 10:01:40.358789 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1578 10:01:40.362331 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1579 10:01:40.365284 == TX Byte 1 ==
1580 10:01:40.369151 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1581 10:01:40.372472 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1582 10:01:40.372553 ==
1583 10:01:40.375494 Dram Type= 6, Freq= 0, CH_1, rank 0
1584 10:01:40.382301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1585 10:01:40.382383 ==
1586 10:01:40.393922 TX Vref=22, minBit 0, minWin=27, winSum=436
1587 10:01:40.397231 TX Vref=24, minBit 4, minWin=27, winSum=440
1588 10:01:40.401449 TX Vref=26, minBit 6, minWin=27, winSum=446
1589 10:01:40.405351 TX Vref=28, minBit 13, minWin=27, winSum=451
1590 10:01:40.408300 TX Vref=30, minBit 15, minWin=27, winSum=453
1591 10:01:40.411794 TX Vref=32, minBit 11, minWin=27, winSum=454
1592 10:01:40.418583 [TxChooseVref] Worse bit 11, Min win 27, Win sum 454, Final Vref 32
1593 10:01:40.418666
1594 10:01:40.421852 Final TX Range 1 Vref 32
1595 10:01:40.421934
1596 10:01:40.421999 ==
1597 10:01:40.425210 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 10:01:40.428809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 10:01:40.428891 ==
1600 10:01:40.428956
1601 10:01:40.429016
1602 10:01:40.432318 TX Vref Scan disable
1603 10:01:40.435741 == TX Byte 0 ==
1604 10:01:40.439089 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1605 10:01:40.442371 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1606 10:01:40.445402 == TX Byte 1 ==
1607 10:01:40.448982 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1608 10:01:40.452445 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1609 10:01:40.452527
1610 10:01:40.452591 [DATLAT]
1611 10:01:40.455823 Freq=800, CH1 RK0
1612 10:01:40.455904
1613 10:01:40.455969 DATLAT Default: 0xa
1614 10:01:40.458995 0, 0xFFFF, sum = 0
1615 10:01:40.462136 1, 0xFFFF, sum = 0
1616 10:01:40.462259 2, 0xFFFF, sum = 0
1617 10:01:40.465931 3, 0xFFFF, sum = 0
1618 10:01:40.466028 4, 0xFFFF, sum = 0
1619 10:01:40.468797 5, 0xFFFF, sum = 0
1620 10:01:40.468884 6, 0xFFFF, sum = 0
1621 10:01:40.472412 7, 0xFFFF, sum = 0
1622 10:01:40.472495 8, 0xFFFF, sum = 0
1623 10:01:40.475767 9, 0x0, sum = 1
1624 10:01:40.475850 10, 0x0, sum = 2
1625 10:01:40.475916 11, 0x0, sum = 3
1626 10:01:40.479332 12, 0x0, sum = 4
1627 10:01:40.479414 best_step = 10
1628 10:01:40.479478
1629 10:01:40.479538 ==
1630 10:01:40.482197 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 10:01:40.489332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 10:01:40.489414 ==
1633 10:01:40.489479 RX Vref Scan: 1
1634 10:01:40.489540
1635 10:01:40.492426 Set Vref Range= 32 -> 127
1636 10:01:40.492507
1637 10:01:40.495961 RX Vref 32 -> 127, step: 1
1638 10:01:40.496041
1639 10:01:40.499116 RX Delay -95 -> 252, step: 8
1640 10:01:40.499213
1641 10:01:40.499291 Set Vref, RX VrefLevel [Byte0]: 32
1642 10:01:40.502772 [Byte1]: 32
1643 10:01:40.506978
1644 10:01:40.507059 Set Vref, RX VrefLevel [Byte0]: 33
1645 10:01:40.510168 [Byte1]: 33
1646 10:01:40.514661
1647 10:01:40.514744 Set Vref, RX VrefLevel [Byte0]: 34
1648 10:01:40.517804 [Byte1]: 34
1649 10:01:40.522074
1650 10:01:40.522155 Set Vref, RX VrefLevel [Byte0]: 35
1651 10:01:40.525444 [Byte1]: 35
1652 10:01:40.529673
1653 10:01:40.529755 Set Vref, RX VrefLevel [Byte0]: 36
1654 10:01:40.532843 [Byte1]: 36
1655 10:01:40.537287
1656 10:01:40.537367 Set Vref, RX VrefLevel [Byte0]: 37
1657 10:01:40.540613 [Byte1]: 37
1658 10:01:40.544976
1659 10:01:40.545083 Set Vref, RX VrefLevel [Byte0]: 38
1660 10:01:40.548209 [Byte1]: 38
1661 10:01:40.552280
1662 10:01:40.552360 Set Vref, RX VrefLevel [Byte0]: 39
1663 10:01:40.556204 [Byte1]: 39
1664 10:01:40.560310
1665 10:01:40.560390 Set Vref, RX VrefLevel [Byte0]: 40
1666 10:01:40.563168 [Byte1]: 40
1667 10:01:40.567784
1668 10:01:40.567866 Set Vref, RX VrefLevel [Byte0]: 41
1669 10:01:40.570984 [Byte1]: 41
1670 10:01:40.575206
1671 10:01:40.575287 Set Vref, RX VrefLevel [Byte0]: 42
1672 10:01:40.578569 [Byte1]: 42
1673 10:01:40.582654
1674 10:01:40.582735 Set Vref, RX VrefLevel [Byte0]: 43
1675 10:01:40.586242 [Byte1]: 43
1676 10:01:40.590335
1677 10:01:40.590417 Set Vref, RX VrefLevel [Byte0]: 44
1678 10:01:40.593917 [Byte1]: 44
1679 10:01:40.597961
1680 10:01:40.598042 Set Vref, RX VrefLevel [Byte0]: 45
1681 10:01:40.601559 [Byte1]: 45
1682 10:01:40.605516
1683 10:01:40.605598 Set Vref, RX VrefLevel [Byte0]: 46
1684 10:01:40.608956 [Byte1]: 46
1685 10:01:40.613413
1686 10:01:40.613495 Set Vref, RX VrefLevel [Byte0]: 47
1687 10:01:40.616482 [Byte1]: 47
1688 10:01:40.620735
1689 10:01:40.620842 Set Vref, RX VrefLevel [Byte0]: 48
1690 10:01:40.624327 [Byte1]: 48
1691 10:01:40.628915
1692 10:01:40.629002 Set Vref, RX VrefLevel [Byte0]: 49
1693 10:01:40.631503 [Byte1]: 49
1694 10:01:40.636210
1695 10:01:40.636291 Set Vref, RX VrefLevel [Byte0]: 50
1696 10:01:40.639706 [Byte1]: 50
1697 10:01:40.643920
1698 10:01:40.644002 Set Vref, RX VrefLevel [Byte0]: 51
1699 10:01:40.647016 [Byte1]: 51
1700 10:01:40.651463
1701 10:01:40.651561 Set Vref, RX VrefLevel [Byte0]: 52
1702 10:01:40.654625 [Byte1]: 52
1703 10:01:40.659105
1704 10:01:40.659186 Set Vref, RX VrefLevel [Byte0]: 53
1705 10:01:40.662255 [Byte1]: 53
1706 10:01:40.666403
1707 10:01:40.670054 Set Vref, RX VrefLevel [Byte0]: 54
1708 10:01:40.670137 [Byte1]: 54
1709 10:01:40.673912
1710 10:01:40.673990 Set Vref, RX VrefLevel [Byte0]: 55
1711 10:01:40.677385 [Byte1]: 55
1712 10:01:40.681782
1713 10:01:40.681864 Set Vref, RX VrefLevel [Byte0]: 56
1714 10:01:40.684772 [Byte1]: 56
1715 10:01:40.689293
1716 10:01:40.689375 Set Vref, RX VrefLevel [Byte0]: 57
1717 10:01:40.692754 [Byte1]: 57
1718 10:01:40.696790
1719 10:01:40.696871 Set Vref, RX VrefLevel [Byte0]: 58
1720 10:01:40.700430 [Byte1]: 58
1721 10:01:40.704936
1722 10:01:40.705017 Set Vref, RX VrefLevel [Byte0]: 59
1723 10:01:40.708291 [Byte1]: 59
1724 10:01:40.711710
1725 10:01:40.711792 Set Vref, RX VrefLevel [Byte0]: 60
1726 10:01:40.715551 [Byte1]: 60
1727 10:01:40.719618
1728 10:01:40.719699 Set Vref, RX VrefLevel [Byte0]: 61
1729 10:01:40.722632 [Byte1]: 61
1730 10:01:40.727160
1731 10:01:40.727241 Set Vref, RX VrefLevel [Byte0]: 62
1732 10:01:40.730661 [Byte1]: 62
1733 10:01:40.734568
1734 10:01:40.734648 Set Vref, RX VrefLevel [Byte0]: 63
1735 10:01:40.737944 [Byte1]: 63
1736 10:01:40.742396
1737 10:01:40.742477 Set Vref, RX VrefLevel [Byte0]: 64
1738 10:01:40.745891 [Byte1]: 64
1739 10:01:40.749747
1740 10:01:40.749827 Set Vref, RX VrefLevel [Byte0]: 65
1741 10:01:40.753517 [Byte1]: 65
1742 10:01:40.757370
1743 10:01:40.757451 Set Vref, RX VrefLevel [Byte0]: 66
1744 10:01:40.760794 [Byte1]: 66
1745 10:01:40.765203
1746 10:01:40.765283 Set Vref, RX VrefLevel [Byte0]: 67
1747 10:01:40.768489 [Byte1]: 67
1748 10:01:40.772925
1749 10:01:40.773009 Set Vref, RX VrefLevel [Byte0]: 68
1750 10:01:40.776090 [Byte1]: 68
1751 10:01:40.780538
1752 10:01:40.780619 Set Vref, RX VrefLevel [Byte0]: 69
1753 10:01:40.784026 [Byte1]: 69
1754 10:01:40.788192
1755 10:01:40.788279 Set Vref, RX VrefLevel [Byte0]: 70
1756 10:01:40.791173 [Byte1]: 70
1757 10:01:40.795480
1758 10:01:40.795561 Set Vref, RX VrefLevel [Byte0]: 71
1759 10:01:40.798523 [Byte1]: 71
1760 10:01:40.803008
1761 10:01:40.803090 Set Vref, RX VrefLevel [Byte0]: 72
1762 10:01:40.806333 [Byte1]: 72
1763 10:01:40.810560
1764 10:01:40.810641 Set Vref, RX VrefLevel [Byte0]: 73
1765 10:01:40.813998 [Byte1]: 73
1766 10:01:40.818128
1767 10:01:40.818210 Set Vref, RX VrefLevel [Byte0]: 74
1768 10:01:40.821745 [Byte1]: 74
1769 10:01:40.826255
1770 10:01:40.826336 Set Vref, RX VrefLevel [Byte0]: 75
1771 10:01:40.829203 [Byte1]: 75
1772 10:01:40.833384
1773 10:01:40.833465 Set Vref, RX VrefLevel [Byte0]: 76
1774 10:01:40.836834 [Byte1]: 76
1775 10:01:40.840859
1776 10:01:40.840939 Set Vref, RX VrefLevel [Byte0]: 77
1777 10:01:40.844456 [Byte1]: 77
1778 10:01:40.848803
1779 10:01:40.848884 Set Vref, RX VrefLevel [Byte0]: 78
1780 10:01:40.852179 [Byte1]: 78
1781 10:01:40.856177
1782 10:01:40.856252 Set Vref, RX VrefLevel [Byte0]: 79
1783 10:01:40.859619 [Byte1]: 79
1784 10:01:40.864308
1785 10:01:40.864390 Final RX Vref Byte 0 = 63 to rank0
1786 10:01:40.867175 Final RX Vref Byte 1 = 55 to rank0
1787 10:01:40.870587 Final RX Vref Byte 0 = 63 to rank1
1788 10:01:40.874236 Final RX Vref Byte 1 = 55 to rank1==
1789 10:01:40.877282 Dram Type= 6, Freq= 0, CH_1, rank 0
1790 10:01:40.880736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1791 10:01:40.883875 ==
1792 10:01:40.883957 DQS Delay:
1793 10:01:40.884022 DQS0 = 0, DQS1 = 0
1794 10:01:40.887584 DQM Delay:
1795 10:01:40.887665 DQM0 = 83, DQM1 = 73
1796 10:01:40.890910 DQ Delay:
1797 10:01:40.894063 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =84
1798 10:01:40.894145 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =76
1799 10:01:40.897575 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =68
1800 10:01:40.900737 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =76
1801 10:01:40.903885
1802 10:01:40.903967
1803 10:01:40.910634 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e03, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
1804 10:01:40.914153 CH1 RK0: MR19=606, MR18=2E03
1805 10:01:40.920525 CH1_RK0: MR19=0x606, MR18=0x2E03, DQSOSC=398, MR23=63, INC=93, DEC=62
1806 10:01:40.920608
1807 10:01:40.924161 ----->DramcWriteLeveling(PI) begin...
1808 10:01:40.924244 ==
1809 10:01:40.927694 Dram Type= 6, Freq= 0, CH_1, rank 1
1810 10:01:40.930594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1811 10:01:40.930676 ==
1812 10:01:40.934085 Write leveling (Byte 0): 27 => 27
1813 10:01:40.937424 Write leveling (Byte 1): 27 => 27
1814 10:01:40.940828 DramcWriteLeveling(PI) end<-----
1815 10:01:40.940911
1816 10:01:40.940976 ==
1817 10:01:40.943968 Dram Type= 6, Freq= 0, CH_1, rank 1
1818 10:01:40.947305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1819 10:01:40.947388 ==
1820 10:01:40.950831 [Gating] SW mode calibration
1821 10:01:40.957745 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1822 10:01:40.964607 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1823 10:01:40.967871 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1824 10:01:40.971400 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1825 10:01:40.974878 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 10:01:40.981202 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 10:01:40.984440 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 10:01:40.988005 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 10:01:40.994797 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 10:01:40.998080 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 10:01:41.001405 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 10:01:41.008091 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 10:01:41.011296 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 10:01:41.014696 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1835 10:01:41.021452 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 10:01:41.024800 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 10:01:41.028053 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1838 10:01:41.031562 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 10:01:41.038521 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1840 10:01:41.041525 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1841 10:01:41.044930 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 10:01:41.051470 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 10:01:41.054984 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 10:01:41.058643 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 10:01:41.065116 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 10:01:41.069043 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 10:01:41.071959 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 10:01:41.078805 0 9 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1849 10:01:41.081767 0 9 8 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
1850 10:01:41.085185 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 10:01:41.088672 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 10:01:41.095718 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 10:01:41.099158 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 10:01:41.102400 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1855 10:01:41.108941 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1856 10:01:41.112440 0 10 4 | B1->B0 | 3232 2d2d | 0 0 | (0 0) (1 1)
1857 10:01:41.115564 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1858 10:01:41.122326 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 10:01:41.125996 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 10:01:41.129068 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 10:01:41.135769 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 10:01:41.139309 0 10 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1863 10:01:41.142771 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1864 10:01:41.145645 0 11 4 | B1->B0 | 2b2b 3c3c | 1 0 | (0 0) (0 0)
1865 10:01:41.152701 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1866 10:01:41.155796 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 10:01:41.159400 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 10:01:41.166236 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 10:01:41.169552 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 10:01:41.172929 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 10:01:41.179211 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1872 10:01:41.182608 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1873 10:01:41.186161 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 10:01:41.192749 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 10:01:41.196011 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 10:01:41.199511 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 10:01:41.202878 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 10:01:41.209597 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 10:01:41.212910 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 10:01:41.216116 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 10:01:41.223250 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 10:01:41.226264 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 10:01:41.229570 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 10:01:41.236853 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 10:01:41.239895 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 10:01:41.243183 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 10:01:41.250092 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 10:01:41.253102 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1889 10:01:41.256919 Total UI for P1: 0, mck2ui 16
1890 10:01:41.259923 best dqsien dly found for B0: ( 0, 14, 2)
1891 10:01:41.263097 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1892 10:01:41.266490 Total UI for P1: 0, mck2ui 16
1893 10:01:41.269955 best dqsien dly found for B1: ( 0, 14, 4)
1894 10:01:41.273313 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1895 10:01:41.276734 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1896 10:01:41.276816
1897 10:01:41.280233 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1898 10:01:41.283217 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1899 10:01:41.286648 [Gating] SW calibration Done
1900 10:01:41.286730 ==
1901 10:01:41.290208 Dram Type= 6, Freq= 0, CH_1, rank 1
1902 10:01:41.296714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1903 10:01:41.296798 ==
1904 10:01:41.296863 RX Vref Scan: 0
1905 10:01:41.296924
1906 10:01:41.300110 RX Vref 0 -> 0, step: 1
1907 10:01:41.300192
1908 10:01:41.303811 RX Delay -130 -> 252, step: 16
1909 10:01:41.306652 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1910 10:01:41.310225 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1911 10:01:41.313794 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1912 10:01:41.316703 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1913 10:01:41.323647 iDelay=206, Bit 4, Center 69 (-50 ~ 189) 240
1914 10:01:41.326974 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1915 10:01:41.330134 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1916 10:01:41.333600 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1917 10:01:41.336908 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1918 10:01:41.340327 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1919 10:01:41.347234 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1920 10:01:41.350563 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1921 10:01:41.353669 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1922 10:01:41.357310 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1923 10:01:41.364448 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1924 10:01:41.367271 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1925 10:01:41.367354 ==
1926 10:01:41.370714 Dram Type= 6, Freq= 0, CH_1, rank 1
1927 10:01:41.374161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1928 10:01:41.374245 ==
1929 10:01:41.374311 DQS Delay:
1930 10:01:41.377277 DQS0 = 0, DQS1 = 0
1931 10:01:41.377359 DQM Delay:
1932 10:01:41.380745 DQM0 = 78, DQM1 = 78
1933 10:01:41.380828 DQ Delay:
1934 10:01:41.384202 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1935 10:01:41.387125 DQ4 =69, DQ5 =93, DQ6 =93, DQ7 =69
1936 10:01:41.390822 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1937 10:01:41.393802 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1938 10:01:41.393884
1939 10:01:41.393949
1940 10:01:41.394008 ==
1941 10:01:41.397188 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 10:01:41.400529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 10:01:41.400612 ==
1944 10:01:41.404024
1945 10:01:41.404105
1946 10:01:41.404169 TX Vref Scan disable
1947 10:01:41.407649 == TX Byte 0 ==
1948 10:01:41.410794 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1949 10:01:41.414049 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1950 10:01:41.417622 == TX Byte 1 ==
1951 10:01:41.420648 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1952 10:01:41.423949 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1953 10:01:41.424033 ==
1954 10:01:41.427270 Dram Type= 6, Freq= 0, CH_1, rank 1
1955 10:01:41.434234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1956 10:01:41.434317 ==
1957 10:01:41.445945 TX Vref=22, minBit 1, minWin=27, winSum=439
1958 10:01:41.449300 TX Vref=24, minBit 1, minWin=27, winSum=442
1959 10:01:41.452229 TX Vref=26, minBit 8, minWin=27, winSum=444
1960 10:01:41.455832 TX Vref=28, minBit 1, minWin=27, winSum=446
1961 10:01:41.459358 TX Vref=30, minBit 15, minWin=27, winSum=448
1962 10:01:41.465513 TX Vref=32, minBit 13, minWin=27, winSum=448
1963 10:01:41.469646 [TxChooseVref] Worse bit 15, Min win 27, Win sum 448, Final Vref 30
1964 10:01:41.469730
1965 10:01:41.472211 Final TX Range 1 Vref 30
1966 10:01:41.472294
1967 10:01:41.472358 ==
1968 10:01:41.475784 Dram Type= 6, Freq= 0, CH_1, rank 1
1969 10:01:41.479157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1970 10:01:41.479240 ==
1971 10:01:41.482589
1972 10:01:41.482670
1973 10:01:41.482735 TX Vref Scan disable
1974 10:01:41.485987 == TX Byte 0 ==
1975 10:01:41.489477 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1976 10:01:41.492313 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1977 10:01:41.495728 == TX Byte 1 ==
1978 10:01:41.499378 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1979 10:01:41.502723 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1980 10:01:41.502805
1981 10:01:41.506079 [DATLAT]
1982 10:01:41.506159 Freq=800, CH1 RK1
1983 10:01:41.506223
1984 10:01:41.509530 DATLAT Default: 0xa
1985 10:01:41.509610 0, 0xFFFF, sum = 0
1986 10:01:41.512509 1, 0xFFFF, sum = 0
1987 10:01:41.512591 2, 0xFFFF, sum = 0
1988 10:01:41.516136 3, 0xFFFF, sum = 0
1989 10:01:41.516219 4, 0xFFFF, sum = 0
1990 10:01:41.519315 5, 0xFFFF, sum = 0
1991 10:01:41.519397 6, 0xFFFF, sum = 0
1992 10:01:41.522805 7, 0xFFFF, sum = 0
1993 10:01:41.522895 8, 0xFFFF, sum = 0
1994 10:01:41.525868 9, 0x0, sum = 1
1995 10:01:41.525950 10, 0x0, sum = 2
1996 10:01:41.529309 11, 0x0, sum = 3
1997 10:01:41.529391 12, 0x0, sum = 4
1998 10:01:41.532784 best_step = 10
1999 10:01:41.532866
2000 10:01:41.532930 ==
2001 10:01:41.536237 Dram Type= 6, Freq= 0, CH_1, rank 1
2002 10:01:41.539877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2003 10:01:41.539959 ==
2004 10:01:41.543177 RX Vref Scan: 0
2005 10:01:41.543258
2006 10:01:41.543322 RX Vref 0 -> 0, step: 1
2007 10:01:41.543382
2008 10:01:41.546246 RX Delay -95 -> 252, step: 8
2009 10:01:41.553008 iDelay=201, Bit 0, Center 84 (-31 ~ 200) 232
2010 10:01:41.556433 iDelay=201, Bit 1, Center 76 (-39 ~ 192) 232
2011 10:01:41.559387 iDelay=201, Bit 2, Center 68 (-47 ~ 184) 232
2012 10:01:41.562791 iDelay=201, Bit 3, Center 76 (-39 ~ 192) 232
2013 10:01:41.566255 iDelay=201, Bit 4, Center 80 (-31 ~ 192) 224
2014 10:01:41.569737 iDelay=201, Bit 5, Center 88 (-23 ~ 200) 224
2015 10:01:41.576204 iDelay=201, Bit 6, Center 88 (-23 ~ 200) 224
2016 10:01:41.579716 iDelay=201, Bit 7, Center 76 (-39 ~ 192) 232
2017 10:01:41.583248 iDelay=201, Bit 8, Center 64 (-55 ~ 184) 240
2018 10:01:41.586566 iDelay=201, Bit 9, Center 64 (-47 ~ 176) 224
2019 10:01:41.589860 iDelay=201, Bit 10, Center 76 (-39 ~ 192) 232
2020 10:01:41.597137 iDelay=201, Bit 11, Center 68 (-47 ~ 184) 232
2021 10:01:41.599697 iDelay=201, Bit 12, Center 80 (-31 ~ 192) 224
2022 10:01:41.603351 iDelay=201, Bit 13, Center 84 (-31 ~ 200) 232
2023 10:01:41.606996 iDelay=201, Bit 14, Center 84 (-31 ~ 200) 232
2024 10:01:41.610152 iDelay=201, Bit 15, Center 84 (-31 ~ 200) 232
2025 10:01:41.610262 ==
2026 10:01:41.613819 Dram Type= 6, Freq= 0, CH_1, rank 1
2027 10:01:41.619957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2028 10:01:41.620039 ==
2029 10:01:41.620105 DQS Delay:
2030 10:01:41.623543 DQS0 = 0, DQS1 = 0
2031 10:01:41.623625 DQM Delay:
2032 10:01:41.623690 DQM0 = 79, DQM1 = 75
2033 10:01:41.626978 DQ Delay:
2034 10:01:41.630015 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2035 10:01:41.633442 DQ4 =80, DQ5 =88, DQ6 =88, DQ7 =76
2036 10:01:41.636855 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2037 10:01:41.640406 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2038 10:01:41.640487
2039 10:01:41.640552
2040 10:01:41.647010 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c27, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 402 ps
2041 10:01:41.650095 CH1 RK1: MR19=606, MR18=1C27
2042 10:01:41.657220 CH1_RK1: MR19=0x606, MR18=0x1C27, DQSOSC=400, MR23=63, INC=92, DEC=61
2043 10:01:41.660347 [RxdqsGatingPostProcess] freq 800
2044 10:01:41.664088 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2045 10:01:41.667207 Pre-setting of DQS Precalculation
2046 10:01:41.673991 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2047 10:01:41.680359 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2048 10:01:41.687449 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2049 10:01:41.687532
2050 10:01:41.687597
2051 10:01:41.690325 [Calibration Summary] 1600 Mbps
2052 10:01:41.690407 CH 0, Rank 0
2053 10:01:41.693869 SW Impedance : PASS
2054 10:01:41.697100 DUTY Scan : NO K
2055 10:01:41.697182 ZQ Calibration : PASS
2056 10:01:41.700477 Jitter Meter : NO K
2057 10:01:41.700559 CBT Training : PASS
2058 10:01:41.703685 Write leveling : PASS
2059 10:01:41.707315 RX DQS gating : PASS
2060 10:01:41.707396 RX DQ/DQS(RDDQC) : PASS
2061 10:01:41.710393 TX DQ/DQS : PASS
2062 10:01:41.714173 RX DATLAT : PASS
2063 10:01:41.714255 RX DQ/DQS(Engine): PASS
2064 10:01:41.717239 TX OE : NO K
2065 10:01:41.717322 All Pass.
2066 10:01:41.717387
2067 10:01:41.720870 CH 0, Rank 1
2068 10:01:41.720952 SW Impedance : PASS
2069 10:01:41.724400 DUTY Scan : NO K
2070 10:01:41.727396 ZQ Calibration : PASS
2071 10:01:41.727477 Jitter Meter : NO K
2072 10:01:41.730767 CBT Training : PASS
2073 10:01:41.730849 Write leveling : PASS
2074 10:01:41.734050 RX DQS gating : PASS
2075 10:01:41.737635 RX DQ/DQS(RDDQC) : PASS
2076 10:01:41.737716 TX DQ/DQS : PASS
2077 10:01:41.741029 RX DATLAT : PASS
2078 10:01:41.744667 RX DQ/DQS(Engine): PASS
2079 10:01:41.744749 TX OE : NO K
2080 10:01:41.747707 All Pass.
2081 10:01:41.747789
2082 10:01:41.747853 CH 1, Rank 0
2083 10:01:41.750814 SW Impedance : PASS
2084 10:01:41.750917 DUTY Scan : NO K
2085 10:01:41.754515 ZQ Calibration : PASS
2086 10:01:41.757987 Jitter Meter : NO K
2087 10:01:41.758068 CBT Training : PASS
2088 10:01:41.761327 Write leveling : PASS
2089 10:01:41.764320 RX DQS gating : PASS
2090 10:01:41.764401 RX DQ/DQS(RDDQC) : PASS
2091 10:01:41.767591 TX DQ/DQS : PASS
2092 10:01:41.767672 RX DATLAT : PASS
2093 10:01:41.771460 RX DQ/DQS(Engine): PASS
2094 10:01:41.774275 TX OE : NO K
2095 10:01:41.774357 All Pass.
2096 10:01:41.774421
2097 10:01:41.774481 CH 1, Rank 1
2098 10:01:41.778442 SW Impedance : PASS
2099 10:01:41.780975 DUTY Scan : NO K
2100 10:01:41.781056 ZQ Calibration : PASS
2101 10:01:41.784497 Jitter Meter : NO K
2102 10:01:41.788304 CBT Training : PASS
2103 10:01:41.788386 Write leveling : PASS
2104 10:01:41.791735 RX DQS gating : PASS
2105 10:01:41.794576 RX DQ/DQS(RDDQC) : PASS
2106 10:01:41.794656 TX DQ/DQS : PASS
2107 10:01:41.798047 RX DATLAT : PASS
2108 10:01:41.798128 RX DQ/DQS(Engine): PASS
2109 10:01:41.801307 TX OE : NO K
2110 10:01:41.801388 All Pass.
2111 10:01:41.801452
2112 10:01:41.804717 DramC Write-DBI off
2113 10:01:41.808111 PER_BANK_REFRESH: Hybrid Mode
2114 10:01:41.808192 TX_TRACKING: ON
2115 10:01:41.811561 [GetDramInforAfterCalByMRR] Vendor 6.
2116 10:01:41.814800 [GetDramInforAfterCalByMRR] Revision 606.
2117 10:01:41.818213 [GetDramInforAfterCalByMRR] Revision 2 0.
2118 10:01:41.821804 MR0 0x3b3b
2119 10:01:41.821884 MR8 0x5151
2120 10:01:41.825085 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2121 10:01:41.825166
2122 10:01:41.828303 MR0 0x3b3b
2123 10:01:41.828384 MR8 0x5151
2124 10:01:41.831347 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2125 10:01:41.831428
2126 10:01:41.841436 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2127 10:01:41.844830 [FAST_K] Save calibration result to emmc
2128 10:01:41.848235 [FAST_K] Save calibration result to emmc
2129 10:01:41.848316 dram_init: config_dvfs: 1
2130 10:01:41.855322 dramc_set_vcore_voltage set vcore to 662500
2131 10:01:41.855404 Read voltage for 1200, 2
2132 10:01:41.858153 Vio18 = 0
2133 10:01:41.858235 Vcore = 662500
2134 10:01:41.858299 Vdram = 0
2135 10:01:41.858358 Vddq = 0
2136 10:01:41.861909 Vmddr = 0
2137 10:01:41.864991 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2138 10:01:41.872144 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2139 10:01:41.875082 MEM_TYPE=3, freq_sel=15
2140 10:01:41.875163 sv_algorithm_assistance_LP4_1600
2141 10:01:41.881722 ============ PULL DRAM RESETB DOWN ============
2142 10:01:41.885524 ========== PULL DRAM RESETB DOWN end =========
2143 10:01:41.888375 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2144 10:01:41.892353 ===================================
2145 10:01:41.895439 LPDDR4 DRAM CONFIGURATION
2146 10:01:41.899237 ===================================
2147 10:01:41.899319 EX_ROW_EN[0] = 0x0
2148 10:01:41.902064 EX_ROW_EN[1] = 0x0
2149 10:01:41.905720 LP4Y_EN = 0x0
2150 10:01:41.905801 WORK_FSP = 0x0
2151 10:01:41.909275 WL = 0x4
2152 10:01:41.909357 RL = 0x4
2153 10:01:41.912390 BL = 0x2
2154 10:01:41.912471 RPST = 0x0
2155 10:01:41.915656 RD_PRE = 0x0
2156 10:01:41.915737 WR_PRE = 0x1
2157 10:01:41.919128 WR_PST = 0x0
2158 10:01:41.919208 DBI_WR = 0x0
2159 10:01:41.922328 DBI_RD = 0x0
2160 10:01:41.922409 OTF = 0x1
2161 10:01:41.925312 ===================================
2162 10:01:41.929098 ===================================
2163 10:01:41.932269 ANA top config
2164 10:01:41.935899 ===================================
2165 10:01:41.935981 DLL_ASYNC_EN = 0
2166 10:01:41.938857 ALL_SLAVE_EN = 0
2167 10:01:41.942407 NEW_RANK_MODE = 1
2168 10:01:41.945817 DLL_IDLE_MODE = 1
2169 10:01:41.945898 LP45_APHY_COMB_EN = 1
2170 10:01:41.949331 TX_ODT_DIS = 1
2171 10:01:41.952268 NEW_8X_MODE = 1
2172 10:01:41.955570 ===================================
2173 10:01:41.959167 ===================================
2174 10:01:41.962368 data_rate = 2400
2175 10:01:41.965757 CKR = 1
2176 10:01:41.969374 DQ_P2S_RATIO = 8
2177 10:01:41.972362 ===================================
2178 10:01:41.972444 CA_P2S_RATIO = 8
2179 10:01:41.975398 DQ_CA_OPEN = 0
2180 10:01:41.978825 DQ_SEMI_OPEN = 0
2181 10:01:41.982492 CA_SEMI_OPEN = 0
2182 10:01:41.985701 CA_FULL_RATE = 0
2183 10:01:41.985787 DQ_CKDIV4_EN = 0
2184 10:01:41.989149 CA_CKDIV4_EN = 0
2185 10:01:41.992690 CA_PREDIV_EN = 0
2186 10:01:41.996105 PH8_DLY = 17
2187 10:01:41.998927 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2188 10:01:42.002921 DQ_AAMCK_DIV = 4
2189 10:01:42.003002 CA_AAMCK_DIV = 4
2190 10:01:42.006121 CA_ADMCK_DIV = 4
2191 10:01:42.009221 DQ_TRACK_CA_EN = 0
2192 10:01:42.012842 CA_PICK = 1200
2193 10:01:42.016228 CA_MCKIO = 1200
2194 10:01:42.019326 MCKIO_SEMI = 0
2195 10:01:42.022552 PLL_FREQ = 2366
2196 10:01:42.022633 DQ_UI_PI_RATIO = 32
2197 10:01:42.026214 CA_UI_PI_RATIO = 0
2198 10:01:42.029753 ===================================
2199 10:01:42.032651 ===================================
2200 10:01:42.036246 memory_type:LPDDR4
2201 10:01:42.039653 GP_NUM : 10
2202 10:01:42.039734 SRAM_EN : 1
2203 10:01:42.043066 MD32_EN : 0
2204 10:01:42.046291 ===================================
2205 10:01:42.046373 [ANA_INIT] >>>>>>>>>>>>>>
2206 10:01:42.049809 <<<<<< [CONFIGURE PHASE]: ANA_TX
2207 10:01:42.053144 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2208 10:01:42.056217 ===================================
2209 10:01:42.059485 data_rate = 2400,PCW = 0X5b00
2210 10:01:42.063321 ===================================
2211 10:01:42.066635 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2212 10:01:42.073170 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2213 10:01:42.076383 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2214 10:01:42.083348 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2215 10:01:42.086273 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2216 10:01:42.089805 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2217 10:01:42.089887 [ANA_INIT] flow start
2218 10:01:42.093069 [ANA_INIT] PLL >>>>>>>>
2219 10:01:42.096727 [ANA_INIT] PLL <<<<<<<<
2220 10:01:42.096808 [ANA_INIT] MIDPI >>>>>>>>
2221 10:01:42.099920 [ANA_INIT] MIDPI <<<<<<<<
2222 10:01:42.102816 [ANA_INIT] DLL >>>>>>>>
2223 10:01:42.106471 [ANA_INIT] DLL <<<<<<<<
2224 10:01:42.106563 [ANA_INIT] flow end
2225 10:01:42.109646 ============ LP4 DIFF to SE enter ============
2226 10:01:42.116625 ============ LP4 DIFF to SE exit ============
2227 10:01:42.116707 [ANA_INIT] <<<<<<<<<<<<<
2228 10:01:42.119976 [Flow] Enable top DCM control >>>>>
2229 10:01:42.122935 [Flow] Enable top DCM control <<<<<
2230 10:01:42.126701 Enable DLL master slave shuffle
2231 10:01:42.133154 ==============================================================
2232 10:01:42.133236 Gating Mode config
2233 10:01:42.139881 ==============================================================
2234 10:01:42.143294 Config description:
2235 10:01:42.149978 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2236 10:01:42.156898 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2237 10:01:42.163966 SELPH_MODE 0: By rank 1: By Phase
2238 10:01:42.167155 ==============================================================
2239 10:01:42.170079 GAT_TRACK_EN = 1
2240 10:01:42.173850 RX_GATING_MODE = 2
2241 10:01:42.177018 RX_GATING_TRACK_MODE = 2
2242 10:01:42.180437 SELPH_MODE = 1
2243 10:01:42.183807 PICG_EARLY_EN = 1
2244 10:01:42.186757 VALID_LAT_VALUE = 1
2245 10:01:42.190206 ==============================================================
2246 10:01:42.193718 Enter into Gating configuration >>>>
2247 10:01:42.197210 Exit from Gating configuration <<<<
2248 10:01:42.200619 Enter into DVFS_PRE_config >>>>>
2249 10:01:42.213989 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2250 10:01:42.217156 Exit from DVFS_PRE_config <<<<<
2251 10:01:42.220573 Enter into PICG configuration >>>>
2252 10:01:42.220655 Exit from PICG configuration <<<<
2253 10:01:42.223950 [RX_INPUT] configuration >>>>>
2254 10:01:42.227216 [RX_INPUT] configuration <<<<<
2255 10:01:42.233708 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2256 10:01:42.237058 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2257 10:01:42.244315 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2258 10:01:42.250510 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2259 10:01:42.257222 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2260 10:01:42.264324 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2261 10:01:42.267835 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2262 10:01:42.270469 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2263 10:01:42.273991 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2264 10:01:42.280797 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2265 10:01:42.284415 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2266 10:01:42.287781 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2267 10:01:42.290633 ===================================
2268 10:01:42.294109 LPDDR4 DRAM CONFIGURATION
2269 10:01:42.297853 ===================================
2270 10:01:42.297934 EX_ROW_EN[0] = 0x0
2271 10:01:42.300879 EX_ROW_EN[1] = 0x0
2272 10:01:42.300960 LP4Y_EN = 0x0
2273 10:01:42.304403 WORK_FSP = 0x0
2274 10:01:42.304484 WL = 0x4
2275 10:01:42.307977 RL = 0x4
2276 10:01:42.308058 BL = 0x2
2277 10:01:42.311140 RPST = 0x0
2278 10:01:42.314410 RD_PRE = 0x0
2279 10:01:42.314492 WR_PRE = 0x1
2280 10:01:42.317817 WR_PST = 0x0
2281 10:01:42.317899 DBI_WR = 0x0
2282 10:01:42.320995 DBI_RD = 0x0
2283 10:01:42.321104 OTF = 0x1
2284 10:01:42.324561 ===================================
2285 10:01:42.327982 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2286 10:01:42.331184 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2287 10:01:42.338178 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2288 10:01:42.341081 ===================================
2289 10:01:42.344583 LPDDR4 DRAM CONFIGURATION
2290 10:01:42.344663 ===================================
2291 10:01:42.347933 EX_ROW_EN[0] = 0x10
2292 10:01:42.351595 EX_ROW_EN[1] = 0x0
2293 10:01:42.351693 LP4Y_EN = 0x0
2294 10:01:42.354762 WORK_FSP = 0x0
2295 10:01:42.354892 WL = 0x4
2296 10:01:42.358241 RL = 0x4
2297 10:01:42.358323 BL = 0x2
2298 10:01:42.361409 RPST = 0x0
2299 10:01:42.361489 RD_PRE = 0x0
2300 10:01:42.364819 WR_PRE = 0x1
2301 10:01:42.364899 WR_PST = 0x0
2302 10:01:42.368390 DBI_WR = 0x0
2303 10:01:42.368471 DBI_RD = 0x0
2304 10:01:42.371307 OTF = 0x1
2305 10:01:42.374713 ===================================
2306 10:01:42.381483 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2307 10:01:42.381566 ==
2308 10:01:42.384898 Dram Type= 6, Freq= 0, CH_0, rank 0
2309 10:01:42.388205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2310 10:01:42.388286 ==
2311 10:01:42.391640 [Duty_Offset_Calibration]
2312 10:01:42.391720 B0:2 B1:-1 CA:1
2313 10:01:42.391784
2314 10:01:42.394609 [DutyScan_Calibration_Flow] k_type=0
2315 10:01:42.404155
2316 10:01:42.404235 ==CLK 0==
2317 10:01:42.407758 Final CLK duty delay cell = -4
2318 10:01:42.411191 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2319 10:01:42.414131 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2320 10:01:42.417988 [-4] AVG Duty = 4953%(X100)
2321 10:01:42.418074
2322 10:01:42.421227 CH0 CLK Duty spec in!! Max-Min= 156%
2323 10:01:42.424767 [DutyScan_Calibration_Flow] ====Done====
2324 10:01:42.424847
2325 10:01:42.427965 [DutyScan_Calibration_Flow] k_type=1
2326 10:01:42.442183
2327 10:01:42.442268 ==DQS 0 ==
2328 10:01:42.445916 Final DQS duty delay cell = -4
2329 10:01:42.449349 [-4] MAX Duty = 5000%(X100), DQS PI = 48
2330 10:01:42.452170 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2331 10:01:42.455969 [-4] AVG Duty = 4938%(X100)
2332 10:01:42.456052
2333 10:01:42.456148 ==DQS 1 ==
2334 10:01:42.458796 Final DQS duty delay cell = -4
2335 10:01:42.462568 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2336 10:01:42.465692 [-4] MIN Duty = 5000%(X100), DQS PI = 44
2337 10:01:42.469238 [-4] AVG Duty = 5062%(X100)
2338 10:01:42.469319
2339 10:01:42.472326 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2340 10:01:42.472408
2341 10:01:42.475782 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2342 10:01:42.478964 [DutyScan_Calibration_Flow] ====Done====
2343 10:01:42.479045
2344 10:01:42.482676 [DutyScan_Calibration_Flow] k_type=3
2345 10:01:42.499467
2346 10:01:42.499574 ==DQM 0 ==
2347 10:01:42.502624 Final DQM duty delay cell = 0
2348 10:01:42.506194 [0] MAX Duty = 5000%(X100), DQS PI = 54
2349 10:01:42.509787 [0] MIN Duty = 4876%(X100), DQS PI = 4
2350 10:01:42.509867 [0] AVG Duty = 4938%(X100)
2351 10:01:42.513219
2352 10:01:42.513298 ==DQM 1 ==
2353 10:01:42.516572 Final DQM duty delay cell = 0
2354 10:01:42.519707 [0] MAX Duty = 5156%(X100), DQS PI = 62
2355 10:01:42.523252 [0] MIN Duty = 5000%(X100), DQS PI = 10
2356 10:01:42.523332 [0] AVG Duty = 5078%(X100)
2357 10:01:42.523396
2358 10:01:42.530030 CH0 DQM 0 Duty spec in!! Max-Min= 124%
2359 10:01:42.530111
2360 10:01:42.533007 CH0 DQM 1 Duty spec in!! Max-Min= 156%
2361 10:01:42.536702 [DutyScan_Calibration_Flow] ====Done====
2362 10:01:42.536783
2363 10:01:42.540301 [DutyScan_Calibration_Flow] k_type=2
2364 10:01:42.555294
2365 10:01:42.555375 ==DQ 0 ==
2366 10:01:42.558278 Final DQ duty delay cell = -4
2367 10:01:42.561704 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2368 10:01:42.565254 [-4] MIN Duty = 4907%(X100), DQS PI = 10
2369 10:01:42.568302 [-4] AVG Duty = 4984%(X100)
2370 10:01:42.568382
2371 10:01:42.568445 ==DQ 1 ==
2372 10:01:42.571608 Final DQ duty delay cell = 0
2373 10:01:42.575506 [0] MAX Duty = 5031%(X100), DQS PI = 18
2374 10:01:42.579051 [0] MIN Duty = 4907%(X100), DQS PI = 46
2375 10:01:42.581629 [0] AVG Duty = 4969%(X100)
2376 10:01:42.581709
2377 10:01:42.585433 CH0 DQ 0 Duty spec in!! Max-Min= 155%
2378 10:01:42.585516
2379 10:01:42.588515 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2380 10:01:42.592329 [DutyScan_Calibration_Flow] ====Done====
2381 10:01:42.592463 ==
2382 10:01:42.595054 Dram Type= 6, Freq= 0, CH_1, rank 0
2383 10:01:42.598631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2384 10:01:42.598712 ==
2385 10:01:42.602143 [Duty_Offset_Calibration]
2386 10:01:42.602277 B0:1 B1:1 CA:2
2387 10:01:42.602355
2388 10:01:42.604985 [DutyScan_Calibration_Flow] k_type=0
2389 10:01:42.615722
2390 10:01:42.615802 ==CLK 0==
2391 10:01:42.619217 Final CLK duty delay cell = 0
2392 10:01:42.622187 [0] MAX Duty = 5187%(X100), DQS PI = 24
2393 10:01:42.625597 [0] MIN Duty = 4938%(X100), DQS PI = 40
2394 10:01:42.625691 [0] AVG Duty = 5062%(X100)
2395 10:01:42.625755
2396 10:01:42.629216 CH1 CLK Duty spec in!! Max-Min= 249%
2397 10:01:42.635635 [DutyScan_Calibration_Flow] ====Done====
2398 10:01:42.635717
2399 10:01:42.638716 [DutyScan_Calibration_Flow] k_type=1
2400 10:01:42.654699
2401 10:01:42.654783 ==DQS 0 ==
2402 10:01:42.658273 Final DQS duty delay cell = 0
2403 10:01:42.661744 [0] MAX Duty = 5031%(X100), DQS PI = 18
2404 10:01:42.665161 [0] MIN Duty = 4813%(X100), DQS PI = 50
2405 10:01:42.665242 [0] AVG Duty = 4922%(X100)
2406 10:01:42.668221
2407 10:01:42.668302 ==DQS 1 ==
2408 10:01:42.671631 Final DQS duty delay cell = 0
2409 10:01:42.675044 [0] MAX Duty = 5062%(X100), DQS PI = 36
2410 10:01:42.678601 [0] MIN Duty = 4907%(X100), DQS PI = 8
2411 10:01:42.678682 [0] AVG Duty = 4984%(X100)
2412 10:01:42.678746
2413 10:01:42.685086 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2414 10:01:42.685169
2415 10:01:42.688576 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2416 10:01:42.691737 [DutyScan_Calibration_Flow] ====Done====
2417 10:01:42.691820
2418 10:01:42.695076 [DutyScan_Calibration_Flow] k_type=3
2419 10:01:42.711441
2420 10:01:42.711525 ==DQM 0 ==
2421 10:01:42.714964 Final DQM duty delay cell = 0
2422 10:01:42.718408 [0] MAX Duty = 5093%(X100), DQS PI = 18
2423 10:01:42.721337 [0] MIN Duty = 4844%(X100), DQS PI = 50
2424 10:01:42.721419 [0] AVG Duty = 4968%(X100)
2425 10:01:42.724937
2426 10:01:42.725018 ==DQM 1 ==
2427 10:01:42.727966 Final DQM duty delay cell = 0
2428 10:01:42.731697 [0] MAX Duty = 5125%(X100), DQS PI = 0
2429 10:01:42.735056 [0] MIN Duty = 4938%(X100), DQS PI = 24
2430 10:01:42.735138 [0] AVG Duty = 5031%(X100)
2431 10:01:42.735202
2432 10:01:42.741722 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2433 10:01:42.741804
2434 10:01:42.744638 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2435 10:01:42.748616 [DutyScan_Calibration_Flow] ====Done====
2436 10:01:42.748697
2437 10:01:42.751247 [DutyScan_Calibration_Flow] k_type=2
2438 10:01:42.767688
2439 10:01:42.767770 ==DQ 0 ==
2440 10:01:42.771217 Final DQ duty delay cell = 0
2441 10:01:42.774743 [0] MAX Duty = 5093%(X100), DQS PI = 18
2442 10:01:42.777840 [0] MIN Duty = 4938%(X100), DQS PI = 50
2443 10:01:42.777922 [0] AVG Duty = 5015%(X100)
2444 10:01:42.777987
2445 10:01:42.781486 ==DQ 1 ==
2446 10:01:42.785041 Final DQ duty delay cell = 0
2447 10:01:42.787983 [0] MAX Duty = 5124%(X100), DQS PI = 58
2448 10:01:42.791476 [0] MIN Duty = 5031%(X100), DQS PI = 2
2449 10:01:42.791591 [0] AVG Duty = 5077%(X100)
2450 10:01:42.791699
2451 10:01:42.795004 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2452 10:01:42.795105
2453 10:01:42.798394 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2454 10:01:42.801564 [DutyScan_Calibration_Flow] ====Done====
2455 10:01:42.807192 nWR fixed to 30
2456 10:01:42.809998 [ModeRegInit_LP4] CH0 RK0
2457 10:01:42.810080 [ModeRegInit_LP4] CH0 RK1
2458 10:01:42.813934 [ModeRegInit_LP4] CH1 RK0
2459 10:01:42.816951 [ModeRegInit_LP4] CH1 RK1
2460 10:01:42.817032 match AC timing 7
2461 10:01:42.823887 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2462 10:01:42.826702 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2463 10:01:42.830340 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2464 10:01:42.837127 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2465 10:01:42.840473 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2466 10:01:42.840555 ==
2467 10:01:42.843957 Dram Type= 6, Freq= 0, CH_0, rank 0
2468 10:01:42.847505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2469 10:01:42.847609 ==
2470 10:01:42.854218 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2471 10:01:42.860790 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2472 10:01:42.867565 [CA 0] Center 40 (10~71) winsize 62
2473 10:01:42.871133 [CA 1] Center 39 (9~70) winsize 62
2474 10:01:42.874402 [CA 2] Center 36 (6~67) winsize 62
2475 10:01:42.877714 [CA 3] Center 36 (5~67) winsize 63
2476 10:01:42.881346 [CA 4] Center 35 (5~65) winsize 61
2477 10:01:42.884289 [CA 5] Center 34 (4~64) winsize 61
2478 10:01:42.884371
2479 10:01:42.887946 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2480 10:01:42.888028
2481 10:01:42.890951 [CATrainingPosCal] consider 1 rank data
2482 10:01:42.894676 u2DelayCellTimex100 = 270/100 ps
2483 10:01:42.898103 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2484 10:01:42.901470 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2485 10:01:42.907860 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2486 10:01:42.911298 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2487 10:01:42.914721 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2488 10:01:42.918273 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2489 10:01:42.918355
2490 10:01:42.921767 CA PerBit enable=1, Macro0, CA PI delay=34
2491 10:01:42.921848
2492 10:01:42.925021 [CBTSetCACLKResult] CA Dly = 34
2493 10:01:42.925103 CS Dly: 7 (0~38)
2494 10:01:42.925169 ==
2495 10:01:42.928018 Dram Type= 6, Freq= 0, CH_0, rank 1
2496 10:01:42.934855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2497 10:01:42.934960 ==
2498 10:01:42.938244 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2499 10:01:42.945049 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2500 10:01:42.953918 [CA 0] Center 39 (9~70) winsize 62
2501 10:01:42.956936 [CA 1] Center 39 (9~70) winsize 62
2502 10:01:42.960434 [CA 2] Center 36 (6~67) winsize 62
2503 10:01:42.963821 [CA 3] Center 35 (5~66) winsize 62
2504 10:01:42.967103 [CA 4] Center 34 (4~65) winsize 62
2505 10:01:42.970725 [CA 5] Center 34 (4~64) winsize 61
2506 10:01:42.970831
2507 10:01:42.974037 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2508 10:01:42.974119
2509 10:01:42.977439 [CATrainingPosCal] consider 2 rank data
2510 10:01:42.980477 u2DelayCellTimex100 = 270/100 ps
2511 10:01:42.983727 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2512 10:01:42.987730 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2513 10:01:42.990581 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2514 10:01:42.997445 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2515 10:01:43.000842 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2516 10:01:43.004154 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2517 10:01:43.004235
2518 10:01:43.007319 CA PerBit enable=1, Macro0, CA PI delay=34
2519 10:01:43.007401
2520 10:01:43.010957 [CBTSetCACLKResult] CA Dly = 34
2521 10:01:43.011065 CS Dly: 8 (0~41)
2522 10:01:43.011157
2523 10:01:43.014271 ----->DramcWriteLeveling(PI) begin...
2524 10:01:43.014353 ==
2525 10:01:43.017585 Dram Type= 6, Freq= 0, CH_0, rank 0
2526 10:01:43.024128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2527 10:01:43.024210 ==
2528 10:01:43.027745 Write leveling (Byte 0): 32 => 32
2529 10:01:43.027830 Write leveling (Byte 1): 30 => 30
2530 10:01:43.031302 DramcWriteLeveling(PI) end<-----
2531 10:01:43.031384
2532 10:01:43.031447 ==
2533 10:01:43.034759 Dram Type= 6, Freq= 0, CH_0, rank 0
2534 10:01:43.041409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2535 10:01:43.041491 ==
2536 10:01:43.044935 [Gating] SW mode calibration
2537 10:01:43.051048 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2538 10:01:43.054528 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2539 10:01:43.061240 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 10:01:43.064789 0 15 4 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
2541 10:01:43.068262 0 15 8 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2542 10:01:43.071161 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 10:01:43.078158 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 10:01:43.081601 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2545 10:01:43.084819 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2546 10:01:43.091336 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2547 10:01:43.094718 1 0 0 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
2548 10:01:43.098237 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2549 10:01:43.105120 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 10:01:43.108508 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 10:01:43.111648 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 10:01:43.118578 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 10:01:43.121681 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2554 10:01:43.124917 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2555 10:01:43.131668 1 1 0 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2556 10:01:43.135268 1 1 4 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
2557 10:01:43.138314 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 10:01:43.141694 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 10:01:43.148357 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 10:01:43.151721 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 10:01:43.155066 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 10:01:43.161780 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2563 10:01:43.164743 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2564 10:01:43.168254 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 10:01:43.174801 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 10:01:43.178310 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 10:01:43.181739 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 10:01:43.188591 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 10:01:43.191951 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 10:01:43.195128 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 10:01:43.201778 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 10:01:43.205296 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 10:01:43.208862 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 10:01:43.211885 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 10:01:43.218702 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 10:01:43.221858 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 10:01:43.225219 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 10:01:43.232001 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 10:01:43.235297 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2580 10:01:43.238727 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2581 10:01:43.245217 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2582 10:01:43.245299 Total UI for P1: 0, mck2ui 16
2583 10:01:43.251965 best dqsien dly found for B0: ( 1, 4, 2)
2584 10:01:43.252059 Total UI for P1: 0, mck2ui 16
2585 10:01:43.258828 best dqsien dly found for B1: ( 1, 4, 2)
2586 10:01:43.262132 best DQS0 dly(MCK, UI, PI) = (1, 4, 2)
2587 10:01:43.265472 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2588 10:01:43.265553
2589 10:01:43.268866 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 2)
2590 10:01:43.271973 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2591 10:01:43.275437 [Gating] SW calibration Done
2592 10:01:43.275518 ==
2593 10:01:43.278777 Dram Type= 6, Freq= 0, CH_0, rank 0
2594 10:01:43.282332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2595 10:01:43.282415 ==
2596 10:01:43.282479 RX Vref Scan: 0
2597 10:01:43.282539
2598 10:01:43.285758 RX Vref 0 -> 0, step: 1
2599 10:01:43.285839
2600 10:01:43.288985 RX Delay -40 -> 252, step: 8
2601 10:01:43.292173 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2602 10:01:43.295450 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2603 10:01:43.302313 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2604 10:01:43.306216 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2605 10:01:43.309509 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2606 10:01:43.312410 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2607 10:01:43.315614 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2608 10:01:43.319429 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2609 10:01:43.326106 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2610 10:01:43.329691 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2611 10:01:43.332864 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2612 10:01:43.336060 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2613 10:01:43.339315 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2614 10:01:43.345839 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2615 10:01:43.349533 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2616 10:01:43.352456 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2617 10:01:43.352537 ==
2618 10:01:43.356190 Dram Type= 6, Freq= 0, CH_0, rank 0
2619 10:01:43.359815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2620 10:01:43.359897 ==
2621 10:01:43.362993 DQS Delay:
2622 10:01:43.363073 DQS0 = 0, DQS1 = 0
2623 10:01:43.366194 DQM Delay:
2624 10:01:43.366275 DQM0 = 116, DQM1 = 107
2625 10:01:43.366339 DQ Delay:
2626 10:01:43.369445 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =111
2627 10:01:43.373028 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2628 10:01:43.376268 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2629 10:01:43.382790 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2630 10:01:43.382916
2631 10:01:43.382983
2632 10:01:43.383044 ==
2633 10:01:43.386320 Dram Type= 6, Freq= 0, CH_0, rank 0
2634 10:01:43.389658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2635 10:01:43.389766 ==
2636 10:01:43.389858
2637 10:01:43.389945
2638 10:01:43.393105 TX Vref Scan disable
2639 10:01:43.393298 == TX Byte 0 ==
2640 10:01:43.399836 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2641 10:01:43.402770 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2642 10:01:43.402900 == TX Byte 1 ==
2643 10:01:43.409651 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2644 10:01:43.412978 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2645 10:01:43.413079 ==
2646 10:01:43.416762 Dram Type= 6, Freq= 0, CH_0, rank 0
2647 10:01:43.419874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2648 10:01:43.419957 ==
2649 10:01:43.432092 TX Vref=22, minBit 0, minWin=25, winSum=414
2650 10:01:43.435554 TX Vref=24, minBit 1, minWin=25, winSum=419
2651 10:01:43.439285 TX Vref=26, minBit 0, minWin=26, winSum=426
2652 10:01:43.442306 TX Vref=28, minBit 0, minWin=26, winSum=427
2653 10:01:43.446042 TX Vref=30, minBit 0, minWin=26, winSum=430
2654 10:01:43.449431 TX Vref=32, minBit 0, minWin=26, winSum=429
2655 10:01:43.455797 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 30
2656 10:01:43.455880
2657 10:01:43.459407 Final TX Range 1 Vref 30
2658 10:01:43.459489
2659 10:01:43.459554 ==
2660 10:01:43.462931 Dram Type= 6, Freq= 0, CH_0, rank 0
2661 10:01:43.466420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2662 10:01:43.466502 ==
2663 10:01:43.466568
2664 10:01:43.466629
2665 10:01:43.469219 TX Vref Scan disable
2666 10:01:43.472657 == TX Byte 0 ==
2667 10:01:43.475999 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2668 10:01:43.479332 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2669 10:01:43.482690 == TX Byte 1 ==
2670 10:01:43.485870 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2671 10:01:43.489380 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2672 10:01:43.489463
2673 10:01:43.492822 [DATLAT]
2674 10:01:43.492904 Freq=1200, CH0 RK0
2675 10:01:43.492970
2676 10:01:43.496396 DATLAT Default: 0xd
2677 10:01:43.496479 0, 0xFFFF, sum = 0
2678 10:01:43.499691 1, 0xFFFF, sum = 0
2679 10:01:43.499775 2, 0xFFFF, sum = 0
2680 10:01:43.503066 3, 0xFFFF, sum = 0
2681 10:01:43.503150 4, 0xFFFF, sum = 0
2682 10:01:43.505956 5, 0xFFFF, sum = 0
2683 10:01:43.506040 6, 0xFFFF, sum = 0
2684 10:01:43.510191 7, 0xFFFF, sum = 0
2685 10:01:43.510274 8, 0xFFFF, sum = 0
2686 10:01:43.513242 9, 0xFFFF, sum = 0
2687 10:01:43.513326 10, 0xFFFF, sum = 0
2688 10:01:43.516205 11, 0xFFFF, sum = 0
2689 10:01:43.516307 12, 0x0, sum = 1
2690 10:01:43.519438 13, 0x0, sum = 2
2691 10:01:43.519537 14, 0x0, sum = 3
2692 10:01:43.523053 15, 0x0, sum = 4
2693 10:01:43.523136 best_step = 13
2694 10:01:43.523201
2695 10:01:43.523261 ==
2696 10:01:43.526374 Dram Type= 6, Freq= 0, CH_0, rank 0
2697 10:01:43.532851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2698 10:01:43.532935 ==
2699 10:01:43.533000 RX Vref Scan: 1
2700 10:01:43.533061
2701 10:01:43.536457 Set Vref Range= 32 -> 127
2702 10:01:43.536540
2703 10:01:43.539363 RX Vref 32 -> 127, step: 1
2704 10:01:43.539446
2705 10:01:43.539511 RX Delay -21 -> 252, step: 4
2706 10:01:43.539572
2707 10:01:43.542825 Set Vref, RX VrefLevel [Byte0]: 32
2708 10:01:43.546359 [Byte1]: 32
2709 10:01:43.550515
2710 10:01:43.550597 Set Vref, RX VrefLevel [Byte0]: 33
2711 10:01:43.553806 [Byte1]: 33
2712 10:01:43.558798
2713 10:01:43.558905 Set Vref, RX VrefLevel [Byte0]: 34
2714 10:01:43.561741 [Byte1]: 34
2715 10:01:43.566383
2716 10:01:43.566464 Set Vref, RX VrefLevel [Byte0]: 35
2717 10:01:43.569854 [Byte1]: 35
2718 10:01:43.574440
2719 10:01:43.574523 Set Vref, RX VrefLevel [Byte0]: 36
2720 10:01:43.577587 [Byte1]: 36
2721 10:01:43.582041
2722 10:01:43.585692 Set Vref, RX VrefLevel [Byte0]: 37
2723 10:01:43.585774 [Byte1]: 37
2724 10:01:43.590142
2725 10:01:43.590224 Set Vref, RX VrefLevel [Byte0]: 38
2726 10:01:43.593534 [Byte1]: 38
2727 10:01:43.598232
2728 10:01:43.598314 Set Vref, RX VrefLevel [Byte0]: 39
2729 10:01:43.601850 [Byte1]: 39
2730 10:01:43.606157
2731 10:01:43.606240 Set Vref, RX VrefLevel [Byte0]: 40
2732 10:01:43.609707 [Byte1]: 40
2733 10:01:43.613719
2734 10:01:43.613801 Set Vref, RX VrefLevel [Byte0]: 41
2735 10:01:43.617073 [Byte1]: 41
2736 10:01:43.621796
2737 10:01:43.621879 Set Vref, RX VrefLevel [Byte0]: 42
2738 10:01:43.625013 [Byte1]: 42
2739 10:01:43.630092
2740 10:01:43.630174 Set Vref, RX VrefLevel [Byte0]: 43
2741 10:01:43.633123 [Byte1]: 43
2742 10:01:43.638194
2743 10:01:43.638276 Set Vref, RX VrefLevel [Byte0]: 44
2744 10:01:43.640875 [Byte1]: 44
2745 10:01:43.645609
2746 10:01:43.645691 Set Vref, RX VrefLevel [Byte0]: 45
2747 10:01:43.649216 [Byte1]: 45
2748 10:01:43.653400
2749 10:01:43.653482 Set Vref, RX VrefLevel [Byte0]: 46
2750 10:01:43.656877 [Byte1]: 46
2751 10:01:43.661848
2752 10:01:43.661930 Set Vref, RX VrefLevel [Byte0]: 47
2753 10:01:43.664954 [Byte1]: 47
2754 10:01:43.669754
2755 10:01:43.669837 Set Vref, RX VrefLevel [Byte0]: 48
2756 10:01:43.672652 [Byte1]: 48
2757 10:01:43.677328
2758 10:01:43.677411 Set Vref, RX VrefLevel [Byte0]: 49
2759 10:01:43.680655 [Byte1]: 49
2760 10:01:43.685846
2761 10:01:43.685928 Set Vref, RX VrefLevel [Byte0]: 50
2762 10:01:43.688885 [Byte1]: 50
2763 10:01:43.693336
2764 10:01:43.693418 Set Vref, RX VrefLevel [Byte0]: 51
2765 10:01:43.696855 [Byte1]: 51
2766 10:01:43.700992
2767 10:01:43.701075 Set Vref, RX VrefLevel [Byte0]: 52
2768 10:01:43.704611 [Byte1]: 52
2769 10:01:43.709001
2770 10:01:43.709087 Set Vref, RX VrefLevel [Byte0]: 53
2771 10:01:43.712169 [Byte1]: 53
2772 10:01:43.717130
2773 10:01:43.717238 Set Vref, RX VrefLevel [Byte0]: 54
2774 10:01:43.720109 [Byte1]: 54
2775 10:01:43.725135
2776 10:01:43.725217 Set Vref, RX VrefLevel [Byte0]: 55
2777 10:01:43.727949 [Byte1]: 55
2778 10:01:43.732691
2779 10:01:43.732773 Set Vref, RX VrefLevel [Byte0]: 56
2780 10:01:43.736278 [Byte1]: 56
2781 10:01:43.740756
2782 10:01:43.740838 Set Vref, RX VrefLevel [Byte0]: 57
2783 10:01:43.744266 [Byte1]: 57
2784 10:01:43.748439
2785 10:01:43.748565 Set Vref, RX VrefLevel [Byte0]: 58
2786 10:01:43.751808 [Byte1]: 58
2787 10:01:43.756550
2788 10:01:43.756632 Set Vref, RX VrefLevel [Byte0]: 59
2789 10:01:43.760156 [Byte1]: 59
2790 10:01:43.764403
2791 10:01:43.764485 Set Vref, RX VrefLevel [Byte0]: 60
2792 10:01:43.767711 [Byte1]: 60
2793 10:01:43.772485
2794 10:01:43.772606 Set Vref, RX VrefLevel [Byte0]: 61
2795 10:01:43.775588 [Byte1]: 61
2796 10:01:43.780858
2797 10:01:43.780941 Set Vref, RX VrefLevel [Byte0]: 62
2798 10:01:43.783756 [Byte1]: 62
2799 10:01:43.788172
2800 10:01:43.788254 Set Vref, RX VrefLevel [Byte0]: 63
2801 10:01:43.791478 [Byte1]: 63
2802 10:01:43.796409
2803 10:01:43.796491 Set Vref, RX VrefLevel [Byte0]: 64
2804 10:01:43.799761 [Byte1]: 64
2805 10:01:43.804173
2806 10:01:43.804254 Set Vref, RX VrefLevel [Byte0]: 65
2807 10:01:43.807843 [Byte1]: 65
2808 10:01:43.812035
2809 10:01:43.812123 Set Vref, RX VrefLevel [Byte0]: 66
2810 10:01:43.815588 [Byte1]: 66
2811 10:01:43.820259
2812 10:01:43.820341 Set Vref, RX VrefLevel [Byte0]: 67
2813 10:01:43.823204 [Byte1]: 67
2814 10:01:43.827774
2815 10:01:43.827856 Set Vref, RX VrefLevel [Byte0]: 68
2816 10:01:43.831243 [Byte1]: 68
2817 10:01:43.835796
2818 10:01:43.835878 Set Vref, RX VrefLevel [Byte0]: 69
2819 10:01:43.839096 [Byte1]: 69
2820 10:01:43.843956
2821 10:01:43.844038 Final RX Vref Byte 0 = 53 to rank0
2822 10:01:43.847392 Final RX Vref Byte 1 = 51 to rank0
2823 10:01:43.850195 Final RX Vref Byte 0 = 53 to rank1
2824 10:01:43.853763 Final RX Vref Byte 1 = 51 to rank1==
2825 10:01:43.857073 Dram Type= 6, Freq= 0, CH_0, rank 0
2826 10:01:43.863974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2827 10:01:43.864058 ==
2828 10:01:43.864123 DQS Delay:
2829 10:01:43.864184 DQS0 = 0, DQS1 = 0
2830 10:01:43.867140 DQM Delay:
2831 10:01:43.867222 DQM0 = 115, DQM1 = 104
2832 10:01:43.870600 DQ Delay:
2833 10:01:43.873631 DQ0 =116, DQ1 =114, DQ2 =112, DQ3 =114
2834 10:01:43.876942 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2835 10:01:43.880515 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2836 10:01:43.883596 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2837 10:01:43.883678
2838 10:01:43.883743
2839 10:01:43.890395 [DQSOSCAuto] RK0, (LSB)MR18= 0xfaea, (MSB)MR19= 0x303, tDQSOscB0 = 419 ps tDQSOscB1 = 412 ps
2840 10:01:43.893824 CH0 RK0: MR19=303, MR18=FAEA
2841 10:01:43.900394 CH0_RK0: MR19=0x303, MR18=0xFAEA, DQSOSC=412, MR23=63, INC=38, DEC=25
2842 10:01:43.900477
2843 10:01:43.903873 ----->DramcWriteLeveling(PI) begin...
2844 10:01:43.903962 ==
2845 10:01:43.907389 Dram Type= 6, Freq= 0, CH_0, rank 1
2846 10:01:43.910972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2847 10:01:43.911055 ==
2848 10:01:43.913733 Write leveling (Byte 0): 32 => 32
2849 10:01:43.917221 Write leveling (Byte 1): 30 => 30
2850 10:01:43.920654 DramcWriteLeveling(PI) end<-----
2851 10:01:43.920736
2852 10:01:43.920800 ==
2853 10:01:43.924371 Dram Type= 6, Freq= 0, CH_0, rank 1
2854 10:01:43.927434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2855 10:01:43.931107 ==
2856 10:01:43.931189 [Gating] SW mode calibration
2857 10:01:43.937494 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2858 10:01:43.944336 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2859 10:01:43.947561 0 15 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2860 10:01:43.954327 0 15 4 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
2861 10:01:43.957639 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 10:01:43.960951 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 10:01:43.967718 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 10:01:43.970733 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 10:01:43.974387 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2866 10:01:43.977618 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
2867 10:01:43.984467 1 0 0 | B1->B0 | 2d2d 2424 | 0 0 | (0 1) (0 0)
2868 10:01:43.987813 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2869 10:01:43.990892 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 10:01:43.998098 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 10:01:44.001381 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 10:01:44.004635 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2873 10:01:44.011675 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2874 10:01:44.015000 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2875 10:01:44.017884 1 1 0 | B1->B0 | 2626 3b3b | 0 0 | (0 0) (0 0)
2876 10:01:44.024879 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 10:01:44.028267 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 10:01:44.031339 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 10:01:44.034845 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 10:01:44.042035 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 10:01:44.044966 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2882 10:01:44.048430 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2883 10:01:44.055183 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2884 10:01:44.058389 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 10:01:44.061839 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 10:01:44.068527 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 10:01:44.072392 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 10:01:44.075461 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 10:01:44.079065 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 10:01:44.085311 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 10:01:44.088721 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 10:01:44.092316 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 10:01:44.098809 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 10:01:44.102556 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 10:01:44.105304 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 10:01:44.112561 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 10:01:44.115485 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 10:01:44.118783 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2899 10:01:44.125624 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2900 10:01:44.125708 Total UI for P1: 0, mck2ui 16
2901 10:01:44.132484 best dqsien dly found for B0: ( 1, 3, 28)
2902 10:01:44.135451 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2903 10:01:44.138982 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2904 10:01:44.142991 Total UI for P1: 0, mck2ui 16
2905 10:01:44.146136 best dqsien dly found for B1: ( 1, 4, 2)
2906 10:01:44.148964 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2907 10:01:44.152583 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2908 10:01:44.152666
2909 10:01:44.156020 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2910 10:01:44.159475 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2911 10:01:44.163056 [Gating] SW calibration Done
2912 10:01:44.163138 ==
2913 10:01:44.165829 Dram Type= 6, Freq= 0, CH_0, rank 1
2914 10:01:44.169776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2915 10:01:44.172295 ==
2916 10:01:44.172401 RX Vref Scan: 0
2917 10:01:44.172498
2918 10:01:44.176271 RX Vref 0 -> 0, step: 1
2919 10:01:44.176389
2920 10:01:44.179334 RX Delay -40 -> 252, step: 8
2921 10:01:44.183134 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2922 10:01:44.186424 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2923 10:01:44.189612 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2924 10:01:44.192924 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2925 10:01:44.196168 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2926 10:01:44.203186 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2927 10:01:44.206650 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2928 10:01:44.209869 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2929 10:01:44.213192 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2930 10:01:44.216472 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2931 10:01:44.223398 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2932 10:01:44.226546 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2933 10:01:44.229942 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2934 10:01:44.233279 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2935 10:01:44.236369 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2936 10:01:44.242898 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2937 10:01:44.242989 ==
2938 10:01:44.246694 Dram Type= 6, Freq= 0, CH_0, rank 1
2939 10:01:44.249622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2940 10:01:44.249729 ==
2941 10:01:44.249822 DQS Delay:
2942 10:01:44.253183 DQS0 = 0, DQS1 = 0
2943 10:01:44.253265 DQM Delay:
2944 10:01:44.256606 DQM0 = 115, DQM1 = 105
2945 10:01:44.256688 DQ Delay:
2946 10:01:44.260039 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2947 10:01:44.263632 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2948 10:01:44.266503 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2949 10:01:44.270054 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2950 10:01:44.270136
2951 10:01:44.270199
2952 10:01:44.270259 ==
2953 10:01:44.273573 Dram Type= 6, Freq= 0, CH_0, rank 1
2954 10:01:44.280055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2955 10:01:44.280138 ==
2956 10:01:44.280203
2957 10:01:44.280263
2958 10:01:44.280320 TX Vref Scan disable
2959 10:01:44.283662 == TX Byte 0 ==
2960 10:01:44.286764 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2961 10:01:44.290554 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2962 10:01:44.294208 == TX Byte 1 ==
2963 10:01:44.296900 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2964 10:01:44.300175 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2965 10:01:44.300257 ==
2966 10:01:44.303824 Dram Type= 6, Freq= 0, CH_0, rank 1
2967 10:01:44.310350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2968 10:01:44.310432 ==
2969 10:01:44.321100 TX Vref=22, minBit 1, minWin=25, winSum=420
2970 10:01:44.324923 TX Vref=24, minBit 0, minWin=26, winSum=430
2971 10:01:44.327809 TX Vref=26, minBit 3, minWin=25, winSum=432
2972 10:01:44.331229 TX Vref=28, minBit 0, minWin=27, winSum=437
2973 10:01:44.334793 TX Vref=30, minBit 5, minWin=26, winSum=436
2974 10:01:44.338051 TX Vref=32, minBit 12, minWin=26, winSum=435
2975 10:01:44.344556 [TxChooseVref] Worse bit 0, Min win 27, Win sum 437, Final Vref 28
2976 10:01:44.344640
2977 10:01:44.348457 Final TX Range 1 Vref 28
2978 10:01:44.348543
2979 10:01:44.348608 ==
2980 10:01:44.351407 Dram Type= 6, Freq= 0, CH_0, rank 1
2981 10:01:44.355036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2982 10:01:44.355118 ==
2983 10:01:44.355183
2984 10:01:44.355243
2985 10:01:44.358047 TX Vref Scan disable
2986 10:01:44.361592 == TX Byte 0 ==
2987 10:01:44.365051 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2988 10:01:44.368500 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2989 10:01:44.371566 == TX Byte 1 ==
2990 10:01:44.374959 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2991 10:01:44.378366 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2992 10:01:44.378449
2993 10:01:44.381832 [DATLAT]
2994 10:01:44.381913 Freq=1200, CH0 RK1
2995 10:01:44.381977
2996 10:01:44.385140 DATLAT Default: 0xd
2997 10:01:44.385221 0, 0xFFFF, sum = 0
2998 10:01:44.388376 1, 0xFFFF, sum = 0
2999 10:01:44.388459 2, 0xFFFF, sum = 0
3000 10:01:44.392062 3, 0xFFFF, sum = 0
3001 10:01:44.392145 4, 0xFFFF, sum = 0
3002 10:01:44.395303 5, 0xFFFF, sum = 0
3003 10:01:44.395387 6, 0xFFFF, sum = 0
3004 10:01:44.398307 7, 0xFFFF, sum = 0
3005 10:01:44.398389 8, 0xFFFF, sum = 0
3006 10:01:44.401638 9, 0xFFFF, sum = 0
3007 10:01:44.401720 10, 0xFFFF, sum = 0
3008 10:01:44.404909 11, 0xFFFF, sum = 0
3009 10:01:44.405030 12, 0x0, sum = 1
3010 10:01:44.408497 13, 0x0, sum = 2
3011 10:01:44.408610 14, 0x0, sum = 3
3012 10:01:44.411565 15, 0x0, sum = 4
3013 10:01:44.411693 best_step = 13
3014 10:01:44.411758
3015 10:01:44.411820 ==
3016 10:01:44.415004 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 10:01:44.421607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 10:01:44.421717 ==
3019 10:01:44.421810 RX Vref Scan: 0
3020 10:01:44.421897
3021 10:01:44.424969 RX Vref 0 -> 0, step: 1
3022 10:01:44.425048
3023 10:01:44.428613 RX Delay -21 -> 252, step: 4
3024 10:01:44.431887 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3025 10:01:44.435240 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3026 10:01:44.438768 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3027 10:01:44.445921 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3028 10:01:44.448661 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3029 10:01:44.452280 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3030 10:01:44.455598 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3031 10:01:44.459122 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3032 10:01:44.465807 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3033 10:01:44.469124 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3034 10:01:44.472114 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3035 10:01:44.475474 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3036 10:01:44.479032 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3037 10:01:44.485458 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3038 10:01:44.488905 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3039 10:01:44.492450 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3040 10:01:44.492532 ==
3041 10:01:44.495596 Dram Type= 6, Freq= 0, CH_0, rank 1
3042 10:01:44.498817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3043 10:01:44.498929 ==
3044 10:01:44.502120 DQS Delay:
3045 10:01:44.502202 DQS0 = 0, DQS1 = 0
3046 10:01:44.502267 DQM Delay:
3047 10:01:44.505469 DQM0 = 114, DQM1 = 104
3048 10:01:44.505577 DQ Delay:
3049 10:01:44.508729 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3050 10:01:44.512986 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3051 10:01:44.515760 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3052 10:01:44.522275 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114
3053 10:01:44.522379
3054 10:01:44.522471
3055 10:01:44.528984 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 408 ps
3056 10:01:44.532339 CH0 RK1: MR19=403, MR18=5F6
3057 10:01:44.539214 CH0_RK1: MR19=0x403, MR18=0x5F6, DQSOSC=408, MR23=63, INC=39, DEC=26
3058 10:01:44.542673 [RxdqsGatingPostProcess] freq 1200
3059 10:01:44.546243 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3060 10:01:44.549302 best DQS0 dly(2T, 0.5T) = (0, 12)
3061 10:01:44.552623 best DQS1 dly(2T, 0.5T) = (0, 12)
3062 10:01:44.555800 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3063 10:01:44.559357 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3064 10:01:44.562957 best DQS0 dly(2T, 0.5T) = (0, 11)
3065 10:01:44.565933 best DQS1 dly(2T, 0.5T) = (0, 12)
3066 10:01:44.569448 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3067 10:01:44.572946 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3068 10:01:44.575906 Pre-setting of DQS Precalculation
3069 10:01:44.579422 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3070 10:01:44.579504 ==
3071 10:01:44.583109 Dram Type= 6, Freq= 0, CH_1, rank 0
3072 10:01:44.586090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3073 10:01:44.586198 ==
3074 10:01:44.592576 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3075 10:01:44.599543 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3076 10:01:44.606857 [CA 0] Center 37 (7~68) winsize 62
3077 10:01:44.610299 [CA 1] Center 38 (9~68) winsize 60
3078 10:01:44.613430 [CA 2] Center 35 (5~65) winsize 61
3079 10:01:44.617155 [CA 3] Center 34 (4~65) winsize 62
3080 10:01:44.619923 [CA 4] Center 34 (4~65) winsize 62
3081 10:01:44.624045 [CA 5] Center 33 (4~63) winsize 60
3082 10:01:44.624127
3083 10:01:44.626782 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3084 10:01:44.626873
3085 10:01:44.630362 [CATrainingPosCal] consider 1 rank data
3086 10:01:44.633464 u2DelayCellTimex100 = 270/100 ps
3087 10:01:44.637143 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3088 10:01:44.640329 CA1 delay=38 (9~68),Diff = 5 PI (24 cell)
3089 10:01:44.643492 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3090 10:01:44.650362 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3091 10:01:44.654207 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3092 10:01:44.657002 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3093 10:01:44.657136
3094 10:01:44.660443 CA PerBit enable=1, Macro0, CA PI delay=33
3095 10:01:44.660550
3096 10:01:44.663808 [CBTSetCACLKResult] CA Dly = 33
3097 10:01:44.663911 CS Dly: 6 (0~37)
3098 10:01:44.664002 ==
3099 10:01:44.667329 Dram Type= 6, Freq= 0, CH_1, rank 1
3100 10:01:44.673757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3101 10:01:44.673872 ==
3102 10:01:44.677317 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3103 10:01:44.683869 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3104 10:01:44.692227 [CA 0] Center 38 (8~68) winsize 61
3105 10:01:44.695720 [CA 1] Center 38 (8~68) winsize 61
3106 10:01:44.699170 [CA 2] Center 34 (4~65) winsize 62
3107 10:01:44.702290 [CA 3] Center 34 (3~65) winsize 63
3108 10:01:44.705936 [CA 4] Center 34 (4~65) winsize 62
3109 10:01:44.709306 [CA 5] Center 33 (3~64) winsize 62
3110 10:01:44.709407
3111 10:01:44.712613 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3112 10:01:44.712717
3113 10:01:44.715715 [CATrainingPosCal] consider 2 rank data
3114 10:01:44.719107 u2DelayCellTimex100 = 270/100 ps
3115 10:01:44.722652 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3116 10:01:44.725674 CA1 delay=38 (9~68),Diff = 5 PI (24 cell)
3117 10:01:44.729338 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3118 10:01:44.736429 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3119 10:01:44.739617 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3120 10:01:44.742716 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3121 10:01:44.742830
3122 10:01:44.746250 CA PerBit enable=1, Macro0, CA PI delay=33
3123 10:01:44.746343
3124 10:01:44.749382 [CBTSetCACLKResult] CA Dly = 33
3125 10:01:44.749478 CS Dly: 7 (0~40)
3126 10:01:44.749592
3127 10:01:44.752946 ----->DramcWriteLeveling(PI) begin...
3128 10:01:44.753054 ==
3129 10:01:44.756333 Dram Type= 6, Freq= 0, CH_1, rank 0
3130 10:01:44.763073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3131 10:01:44.763155 ==
3132 10:01:44.766524 Write leveling (Byte 0): 27 => 27
3133 10:01:44.766629 Write leveling (Byte 1): 29 => 29
3134 10:01:44.769784 DramcWriteLeveling(PI) end<-----
3135 10:01:44.769904
3136 10:01:44.772781 ==
3137 10:01:44.772885 Dram Type= 6, Freq= 0, CH_1, rank 0
3138 10:01:44.779867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3139 10:01:44.780007 ==
3140 10:01:44.783486 [Gating] SW mode calibration
3141 10:01:44.789695 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3142 10:01:44.793120 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3143 10:01:44.799787 0 15 0 | B1->B0 | 2929 2323 | 1 0 | (1 1) (0 0)
3144 10:01:44.803178 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 10:01:44.806815 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 10:01:44.810171 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3147 10:01:44.816890 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 10:01:44.820391 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3149 10:01:44.823784 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3150 10:01:44.830372 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3151 10:01:44.833706 1 0 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3152 10:01:44.836846 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 10:01:44.843660 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 10:01:44.846857 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 10:01:44.850609 1 0 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3156 10:01:44.857208 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3157 10:01:44.860423 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3158 10:01:44.863624 1 0 28 | B1->B0 | 2e2e 2b2b | 0 1 | (0 0) (0 0)
3159 10:01:44.866936 1 1 0 | B1->B0 | 4444 3838 | 0 0 | (0 0) (1 1)
3160 10:01:44.873523 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 10:01:44.877001 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 10:01:44.880609 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 10:01:44.887606 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 10:01:44.890461 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 10:01:44.894090 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 10:01:44.900448 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 10:01:44.903950 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3168 10:01:44.907524 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 10:01:44.913965 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 10:01:44.917492 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 10:01:44.920712 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 10:01:44.927261 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 10:01:44.930533 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 10:01:44.934183 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 10:01:44.937598 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 10:01:44.944564 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 10:01:44.947612 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 10:01:44.950925 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 10:01:44.957991 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 10:01:44.961347 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 10:01:44.964473 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 10:01:44.971165 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3183 10:01:44.974234 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3184 10:01:44.977970 Total UI for P1: 0, mck2ui 16
3185 10:01:44.981378 best dqsien dly found for B1: ( 1, 3, 30)
3186 10:01:44.984786 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3187 10:01:44.987657 Total UI for P1: 0, mck2ui 16
3188 10:01:44.991352 best dqsien dly found for B0: ( 1, 3, 30)
3189 10:01:44.994637 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3190 10:01:44.997673 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3191 10:01:44.997747
3192 10:01:45.001299 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3193 10:01:45.004786 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3194 10:01:45.007931 [Gating] SW calibration Done
3195 10:01:45.008021 ==
3196 10:01:45.011298 Dram Type= 6, Freq= 0, CH_1, rank 0
3197 10:01:45.018107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3198 10:01:45.018203 ==
3199 10:01:45.018268 RX Vref Scan: 0
3200 10:01:45.018327
3201 10:01:45.021671 RX Vref 0 -> 0, step: 1
3202 10:01:45.021775
3203 10:01:45.024714 RX Delay -40 -> 252, step: 8
3204 10:01:45.028107 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3205 10:01:45.031568 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3206 10:01:45.034582 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3207 10:01:45.038156 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3208 10:01:45.044657 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3209 10:01:45.048308 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3210 10:01:45.051974 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3211 10:01:45.054765 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3212 10:01:45.058452 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3213 10:01:45.062033 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3214 10:01:45.068165 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3215 10:01:45.072048 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3216 10:01:45.075329 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3217 10:01:45.078669 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3218 10:01:45.081691 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3219 10:01:45.088419 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3220 10:01:45.088506 ==
3221 10:01:45.092179 Dram Type= 6, Freq= 0, CH_1, rank 0
3222 10:01:45.095055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3223 10:01:45.095137 ==
3224 10:01:45.095202 DQS Delay:
3225 10:01:45.098543 DQS0 = 0, DQS1 = 0
3226 10:01:45.098643 DQM Delay:
3227 10:01:45.102102 DQM0 = 116, DQM1 = 108
3228 10:01:45.102179 DQ Delay:
3229 10:01:45.105905 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3230 10:01:45.108877 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3231 10:01:45.112197 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3232 10:01:45.115449 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111
3233 10:01:45.115533
3234 10:01:45.115598
3235 10:01:45.115658 ==
3236 10:01:45.118761 Dram Type= 6, Freq= 0, CH_1, rank 0
3237 10:01:45.125281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3238 10:01:45.125367 ==
3239 10:01:45.125434
3240 10:01:45.125495
3241 10:01:45.125554 TX Vref Scan disable
3242 10:01:45.129244 == TX Byte 0 ==
3243 10:01:45.132139 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3244 10:01:45.135801 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3245 10:01:45.138784 == TX Byte 1 ==
3246 10:01:45.142351 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3247 10:01:45.145855 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3248 10:01:45.148982 ==
3249 10:01:45.152360 Dram Type= 6, Freq= 0, CH_1, rank 0
3250 10:01:45.156098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3251 10:01:45.156182 ==
3252 10:01:45.166931 TX Vref=22, minBit 1, minWin=25, winSum=415
3253 10:01:45.170399 TX Vref=24, minBit 1, minWin=25, winSum=416
3254 10:01:45.173341 TX Vref=26, minBit 2, minWin=25, winSum=426
3255 10:01:45.177458 TX Vref=28, minBit 0, minWin=26, winSum=425
3256 10:01:45.180307 TX Vref=30, minBit 1, minWin=26, winSum=432
3257 10:01:45.183592 TX Vref=32, minBit 3, minWin=25, winSum=429
3258 10:01:45.190048 [TxChooseVref] Worse bit 1, Min win 26, Win sum 432, Final Vref 30
3259 10:01:45.190145
3260 10:01:45.193879 Final TX Range 1 Vref 30
3261 10:01:45.193993
3262 10:01:45.194087 ==
3263 10:01:45.196945 Dram Type= 6, Freq= 0, CH_1, rank 0
3264 10:01:45.200340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3265 10:01:45.200426 ==
3266 10:01:45.200493
3267 10:01:45.200554
3268 10:01:45.203832 TX Vref Scan disable
3269 10:01:45.207300 == TX Byte 0 ==
3270 10:01:45.210725 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3271 10:01:45.213683 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3272 10:01:45.217430 == TX Byte 1 ==
3273 10:01:45.220897 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3274 10:01:45.223881 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3275 10:01:45.223973
3276 10:01:45.227397 [DATLAT]
3277 10:01:45.227516 Freq=1200, CH1 RK0
3278 10:01:45.227589
3279 10:01:45.231137 DATLAT Default: 0xd
3280 10:01:45.231226 0, 0xFFFF, sum = 0
3281 10:01:45.233871 1, 0xFFFF, sum = 0
3282 10:01:45.233962 2, 0xFFFF, sum = 0
3283 10:01:45.237268 3, 0xFFFF, sum = 0
3284 10:01:45.237358 4, 0xFFFF, sum = 0
3285 10:01:45.240862 5, 0xFFFF, sum = 0
3286 10:01:45.240957 6, 0xFFFF, sum = 0
3287 10:01:45.244321 7, 0xFFFF, sum = 0
3288 10:01:45.244431 8, 0xFFFF, sum = 0
3289 10:01:45.247332 9, 0xFFFF, sum = 0
3290 10:01:45.247419 10, 0xFFFF, sum = 0
3291 10:01:45.250887 11, 0xFFFF, sum = 0
3292 10:01:45.251008 12, 0x0, sum = 1
3293 10:01:45.254292 13, 0x0, sum = 2
3294 10:01:45.254410 14, 0x0, sum = 3
3295 10:01:45.257784 15, 0x0, sum = 4
3296 10:01:45.257911 best_step = 13
3297 10:01:45.258005
3298 10:01:45.258104 ==
3299 10:01:45.260926 Dram Type= 6, Freq= 0, CH_1, rank 0
3300 10:01:45.264306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3301 10:01:45.268398 ==
3302 10:01:45.268487 RX Vref Scan: 1
3303 10:01:45.268554
3304 10:01:45.270684 Set Vref Range= 32 -> 127
3305 10:01:45.270793
3306 10:01:45.274202 RX Vref 32 -> 127, step: 1
3307 10:01:45.274327
3308 10:01:45.274420 RX Delay -21 -> 252, step: 4
3309 10:01:45.274531
3310 10:01:45.277686 Set Vref, RX VrefLevel [Byte0]: 32
3311 10:01:45.280483 [Byte1]: 32
3312 10:01:45.285454
3313 10:01:45.285591 Set Vref, RX VrefLevel [Byte0]: 33
3314 10:01:45.288714 [Byte1]: 33
3315 10:01:45.293121
3316 10:01:45.293225 Set Vref, RX VrefLevel [Byte0]: 34
3317 10:01:45.296390 [Byte1]: 34
3318 10:01:45.300699
3319 10:01:45.300789 Set Vref, RX VrefLevel [Byte0]: 35
3320 10:01:45.304025 [Byte1]: 35
3321 10:01:45.308593
3322 10:01:45.308684 Set Vref, RX VrefLevel [Byte0]: 36
3323 10:01:45.312164 [Byte1]: 36
3324 10:01:45.316654
3325 10:01:45.316745 Set Vref, RX VrefLevel [Byte0]: 37
3326 10:01:45.320102 [Byte1]: 37
3327 10:01:45.324552
3328 10:01:45.324638 Set Vref, RX VrefLevel [Byte0]: 38
3329 10:01:45.328126 [Byte1]: 38
3330 10:01:45.332784
3331 10:01:45.332903 Set Vref, RX VrefLevel [Byte0]: 39
3332 10:01:45.335778 [Byte1]: 39
3333 10:01:45.340253
3334 10:01:45.340340 Set Vref, RX VrefLevel [Byte0]: 40
3335 10:01:45.343750 [Byte1]: 40
3336 10:01:45.348624
3337 10:01:45.348720 Set Vref, RX VrefLevel [Byte0]: 41
3338 10:01:45.351537 [Byte1]: 41
3339 10:01:45.356633
3340 10:01:45.356719 Set Vref, RX VrefLevel [Byte0]: 42
3341 10:01:45.359797 [Byte1]: 42
3342 10:01:45.364025
3343 10:01:45.364103 Set Vref, RX VrefLevel [Byte0]: 43
3344 10:01:45.367738 [Byte1]: 43
3345 10:01:45.372530
3346 10:01:45.372614 Set Vref, RX VrefLevel [Byte0]: 44
3347 10:01:45.375320 [Byte1]: 44
3348 10:01:45.379927
3349 10:01:45.380020 Set Vref, RX VrefLevel [Byte0]: 45
3350 10:01:45.383486 [Byte1]: 45
3351 10:01:45.388158
3352 10:01:45.388244 Set Vref, RX VrefLevel [Byte0]: 46
3353 10:01:45.391285 [Byte1]: 46
3354 10:01:45.395958
3355 10:01:45.396046 Set Vref, RX VrefLevel [Byte0]: 47
3356 10:01:45.399184 [Byte1]: 47
3357 10:01:45.403574
3358 10:01:45.403676 Set Vref, RX VrefLevel [Byte0]: 48
3359 10:01:45.407637 [Byte1]: 48
3360 10:01:45.411680
3361 10:01:45.411802 Set Vref, RX VrefLevel [Byte0]: 49
3362 10:01:45.415125 [Byte1]: 49
3363 10:01:45.419763
3364 10:01:45.419857 Set Vref, RX VrefLevel [Byte0]: 50
3365 10:01:45.423353 [Byte1]: 50
3366 10:01:45.427469
3367 10:01:45.427550 Set Vref, RX VrefLevel [Byte0]: 51
3368 10:01:45.430918 [Byte1]: 51
3369 10:01:45.435535
3370 10:01:45.435634 Set Vref, RX VrefLevel [Byte0]: 52
3371 10:01:45.439062 [Byte1]: 52
3372 10:01:45.443625
3373 10:01:45.443718 Set Vref, RX VrefLevel [Byte0]: 53
3374 10:01:45.446679 [Byte1]: 53
3375 10:01:45.451405
3376 10:01:45.451519 Set Vref, RX VrefLevel [Byte0]: 54
3377 10:01:45.454718 [Byte1]: 54
3378 10:01:45.459468
3379 10:01:45.459560 Set Vref, RX VrefLevel [Byte0]: 55
3380 10:01:45.462422 [Byte1]: 55
3381 10:01:45.467316
3382 10:01:45.467428 Set Vref, RX VrefLevel [Byte0]: 56
3383 10:01:45.470577 [Byte1]: 56
3384 10:01:45.474937
3385 10:01:45.475049 Set Vref, RX VrefLevel [Byte0]: 57
3386 10:01:45.478464 [Byte1]: 57
3387 10:01:45.483168
3388 10:01:45.483274 Set Vref, RX VrefLevel [Byte0]: 58
3389 10:01:45.486483 [Byte1]: 58
3390 10:01:45.491104
3391 10:01:45.491196 Set Vref, RX VrefLevel [Byte0]: 59
3392 10:01:45.494653 [Byte1]: 59
3393 10:01:45.499367
3394 10:01:45.499479 Set Vref, RX VrefLevel [Byte0]: 60
3395 10:01:45.501955 [Byte1]: 60
3396 10:01:45.507009
3397 10:01:45.507092 Set Vref, RX VrefLevel [Byte0]: 61
3398 10:01:45.510848 [Byte1]: 61
3399 10:01:45.514542
3400 10:01:45.514665 Set Vref, RX VrefLevel [Byte0]: 62
3401 10:01:45.517801 [Byte1]: 62
3402 10:01:45.522722
3403 10:01:45.522836 Set Vref, RX VrefLevel [Byte0]: 63
3404 10:01:45.526280 [Byte1]: 63
3405 10:01:45.530468
3406 10:01:45.530607 Set Vref, RX VrefLevel [Byte0]: 64
3407 10:01:45.533729 [Byte1]: 64
3408 10:01:45.538707
3409 10:01:45.538842 Set Vref, RX VrefLevel [Byte0]: 65
3410 10:01:45.541546 [Byte1]: 65
3411 10:01:45.546479
3412 10:01:45.546601 Set Vref, RX VrefLevel [Byte0]: 66
3413 10:01:45.549450 [Byte1]: 66
3414 10:01:45.554427
3415 10:01:45.554563 Set Vref, RX VrefLevel [Byte0]: 67
3416 10:01:45.557858 [Byte1]: 67
3417 10:01:45.562450
3418 10:01:45.562575 Set Vref, RX VrefLevel [Byte0]: 68
3419 10:01:45.565499 [Byte1]: 68
3420 10:01:45.570209
3421 10:01:45.570322 Set Vref, RX VrefLevel [Byte0]: 69
3422 10:01:45.573747 [Byte1]: 69
3423 10:01:45.578444
3424 10:01:45.578574 Set Vref, RX VrefLevel [Byte0]: 70
3425 10:01:45.581211 [Byte1]: 70
3426 10:01:45.585867
3427 10:01:45.585988 Set Vref, RX VrefLevel [Byte0]: 71
3428 10:01:45.589075 [Byte1]: 71
3429 10:01:45.594219
3430 10:01:45.594335 Set Vref, RX VrefLevel [Byte0]: 72
3431 10:01:45.597481 [Byte1]: 72
3432 10:01:45.602182
3433 10:01:45.602316 Set Vref, RX VrefLevel [Byte0]: 73
3434 10:01:45.605288 [Byte1]: 73
3435 10:01:45.609726
3436 10:01:45.609847 Final RX Vref Byte 0 = 58 to rank0
3437 10:01:45.613181 Final RX Vref Byte 1 = 52 to rank0
3438 10:01:45.616512 Final RX Vref Byte 0 = 58 to rank1
3439 10:01:45.620015 Final RX Vref Byte 1 = 52 to rank1==
3440 10:01:45.623156 Dram Type= 6, Freq= 0, CH_1, rank 0
3441 10:01:45.626705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3442 10:01:45.629980 ==
3443 10:01:45.630111 DQS Delay:
3444 10:01:45.630211 DQS0 = 0, DQS1 = 0
3445 10:01:45.633707 DQM Delay:
3446 10:01:45.633817 DQM0 = 116, DQM1 = 109
3447 10:01:45.636686 DQ Delay:
3448 10:01:45.640299 DQ0 =118, DQ1 =108, DQ2 =106, DQ3 =114
3449 10:01:45.643693 DQ4 =116, DQ5 =126, DQ6 =126, DQ7 =114
3450 10:01:45.646938 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =106
3451 10:01:45.650292 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =114
3452 10:01:45.650410
3453 10:01:45.650540
3454 10:01:45.656878 [DQSOSCAuto] RK0, (LSB)MR18= 0xffe4, (MSB)MR19= 0x303, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
3455 10:01:45.659961 CH1 RK0: MR19=303, MR18=FFE4
3456 10:01:45.666887 CH1_RK0: MR19=0x303, MR18=0xFFE4, DQSOSC=410, MR23=63, INC=39, DEC=26
3457 10:01:45.666998
3458 10:01:45.670115 ----->DramcWriteLeveling(PI) begin...
3459 10:01:45.670205 ==
3460 10:01:45.673733 Dram Type= 6, Freq= 0, CH_1, rank 1
3461 10:01:45.677783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3462 10:01:45.677891 ==
3463 10:01:45.680224 Write leveling (Byte 0): 26 => 26
3464 10:01:45.683572 Write leveling (Byte 1): 28 => 28
3465 10:01:45.687563 DramcWriteLeveling(PI) end<-----
3466 10:01:45.687659
3467 10:01:45.687726 ==
3468 10:01:45.690748 Dram Type= 6, Freq= 0, CH_1, rank 1
3469 10:01:45.694001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3470 10:01:45.694083 ==
3471 10:01:45.697107 [Gating] SW mode calibration
3472 10:01:45.704090 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3473 10:01:45.710929 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3474 10:01:45.714342 0 15 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
3475 10:01:45.717327 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3476 10:01:45.724315 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3477 10:01:45.727600 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3478 10:01:45.731111 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3479 10:01:45.737352 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
3480 10:01:45.741151 0 15 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
3481 10:01:45.744219 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3482 10:01:45.750905 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3483 10:01:45.754142 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3484 10:01:45.757455 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3485 10:01:45.763981 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3486 10:01:45.767191 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3487 10:01:45.770811 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3488 10:01:45.777209 1 0 24 | B1->B0 | 2525 3e3e | 0 0 | (0 0) (0 0)
3489 10:01:45.780603 1 0 28 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3490 10:01:45.784339 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3491 10:01:45.790698 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3492 10:01:45.794225 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3493 10:01:45.797731 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3494 10:01:45.804270 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3495 10:01:45.807589 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3496 10:01:45.811170 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3497 10:01:45.814474 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3498 10:01:45.820862 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 10:01:45.824111 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 10:01:45.827714 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 10:01:45.834429 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 10:01:45.837709 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 10:01:45.840571 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 10:01:45.847241 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 10:01:45.850587 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 10:01:45.854449 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 10:01:45.860964 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 10:01:45.864238 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 10:01:45.867840 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 10:01:45.874558 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 10:01:45.877222 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 10:01:45.881030 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3513 10:01:45.887515 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3514 10:01:45.891037 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3515 10:01:45.894228 Total UI for P1: 0, mck2ui 16
3516 10:01:45.897565 best dqsien dly found for B0: ( 1, 3, 26)
3517 10:01:45.901145 Total UI for P1: 0, mck2ui 16
3518 10:01:45.904413 best dqsien dly found for B1: ( 1, 3, 30)
3519 10:01:45.907201 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3520 10:01:45.910621 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3521 10:01:45.910731
3522 10:01:45.913900 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3523 10:01:45.917283 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3524 10:01:45.920910 [Gating] SW calibration Done
3525 10:01:45.921004 ==
3526 10:01:45.924016 Dram Type= 6, Freq= 0, CH_1, rank 1
3527 10:01:45.927604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3528 10:01:45.927733 ==
3529 10:01:45.930493 RX Vref Scan: 0
3530 10:01:45.930626
3531 10:01:45.933796 RX Vref 0 -> 0, step: 1
3532 10:01:45.933901
3533 10:01:45.933993 RX Delay -40 -> 252, step: 8
3534 10:01:45.941026 iDelay=192, Bit 0, Center 115 (40 ~ 191) 152
3535 10:01:45.944019 iDelay=192, Bit 1, Center 111 (40 ~ 183) 144
3536 10:01:45.947613 iDelay=192, Bit 2, Center 103 (32 ~ 175) 144
3537 10:01:45.951073 iDelay=192, Bit 3, Center 111 (40 ~ 183) 144
3538 10:01:45.954316 iDelay=192, Bit 4, Center 111 (40 ~ 183) 144
3539 10:01:45.960828 iDelay=192, Bit 5, Center 123 (56 ~ 191) 136
3540 10:01:45.964310 iDelay=192, Bit 6, Center 119 (48 ~ 191) 144
3541 10:01:45.967658 iDelay=192, Bit 7, Center 107 (40 ~ 175) 136
3542 10:01:45.970792 iDelay=192, Bit 8, Center 103 (32 ~ 175) 144
3543 10:01:45.974264 iDelay=192, Bit 9, Center 95 (24 ~ 167) 144
3544 10:01:45.977529 iDelay=192, Bit 10, Center 111 (40 ~ 183) 144
3545 10:01:45.984183 iDelay=192, Bit 11, Center 103 (32 ~ 175) 144
3546 10:01:45.987344 iDelay=192, Bit 12, Center 115 (48 ~ 183) 136
3547 10:01:45.990769 iDelay=192, Bit 13, Center 119 (48 ~ 191) 144
3548 10:01:45.994374 iDelay=192, Bit 14, Center 119 (48 ~ 191) 144
3549 10:01:46.000746 iDelay=192, Bit 15, Center 119 (48 ~ 191) 144
3550 10:01:46.000861 ==
3551 10:01:46.004410 Dram Type= 6, Freq= 0, CH_1, rank 1
3552 10:01:46.007484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3553 10:01:46.007574 ==
3554 10:01:46.007652 DQS Delay:
3555 10:01:46.010817 DQS0 = 0, DQS1 = 0
3556 10:01:46.010917 DQM Delay:
3557 10:01:46.014169 DQM0 = 112, DQM1 = 110
3558 10:01:46.014265 DQ Delay:
3559 10:01:46.017520 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =111
3560 10:01:46.020982 DQ4 =111, DQ5 =123, DQ6 =119, DQ7 =107
3561 10:01:46.024579 DQ8 =103, DQ9 =95, DQ10 =111, DQ11 =103
3562 10:01:46.027767 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3563 10:01:46.027895
3564 10:01:46.027981
3565 10:01:46.028050 ==
3566 10:01:46.030810 Dram Type= 6, Freq= 0, CH_1, rank 1
3567 10:01:46.038086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3568 10:01:46.038213 ==
3569 10:01:46.038292
3570 10:01:46.038366
3571 10:01:46.038434 TX Vref Scan disable
3572 10:01:46.040802 == TX Byte 0 ==
3573 10:01:46.044510 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3574 10:01:46.051304 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3575 10:01:46.051450 == TX Byte 1 ==
3576 10:01:46.054391 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3577 10:01:46.057688 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3578 10:01:46.061119 ==
3579 10:01:46.064520 Dram Type= 6, Freq= 0, CH_1, rank 1
3580 10:01:46.067639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3581 10:01:46.067765 ==
3582 10:01:46.078838 TX Vref=22, minBit 1, minWin=25, winSum=418
3583 10:01:46.082166 TX Vref=24, minBit 0, minWin=26, winSum=425
3584 10:01:46.085582 TX Vref=26, minBit 0, minWin=26, winSum=429
3585 10:01:46.089045 TX Vref=28, minBit 4, minWin=26, winSum=434
3586 10:01:46.092390 TX Vref=30, minBit 9, minWin=26, winSum=435
3587 10:01:46.095587 TX Vref=32, minBit 0, minWin=26, winSum=430
3588 10:01:46.102205 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 30
3589 10:01:46.102315
3590 10:01:46.105724 Final TX Range 1 Vref 30
3591 10:01:46.105841
3592 10:01:46.105935 ==
3593 10:01:46.109174 Dram Type= 6, Freq= 0, CH_1, rank 1
3594 10:01:46.112399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3595 10:01:46.112492 ==
3596 10:01:46.112560
3597 10:01:46.112625
3598 10:01:46.115812 TX Vref Scan disable
3599 10:01:46.119318 == TX Byte 0 ==
3600 10:01:46.122621 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3601 10:01:46.125543 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3602 10:01:46.129181 == TX Byte 1 ==
3603 10:01:46.132447 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3604 10:01:46.135878 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3605 10:01:46.136004
3606 10:01:46.138802 [DATLAT]
3607 10:01:46.138909 Freq=1200, CH1 RK1
3608 10:01:46.138974
3609 10:01:46.142405 DATLAT Default: 0xd
3610 10:01:46.142532 0, 0xFFFF, sum = 0
3611 10:01:46.145599 1, 0xFFFF, sum = 0
3612 10:01:46.145720 2, 0xFFFF, sum = 0
3613 10:01:46.148969 3, 0xFFFF, sum = 0
3614 10:01:46.149089 4, 0xFFFF, sum = 0
3615 10:01:46.152270 5, 0xFFFF, sum = 0
3616 10:01:46.152400 6, 0xFFFF, sum = 0
3617 10:01:46.156019 7, 0xFFFF, sum = 0
3618 10:01:46.156109 8, 0xFFFF, sum = 0
3619 10:01:46.159458 9, 0xFFFF, sum = 0
3620 10:01:46.159539 10, 0xFFFF, sum = 0
3621 10:01:46.162645 11, 0xFFFF, sum = 0
3622 10:01:46.162754 12, 0x0, sum = 1
3623 10:01:46.165587 13, 0x0, sum = 2
3624 10:01:46.165712 14, 0x0, sum = 3
3625 10:01:46.169090 15, 0x0, sum = 4
3626 10:01:46.169205 best_step = 13
3627 10:01:46.169301
3628 10:01:46.169394 ==
3629 10:01:46.172363 Dram Type= 6, Freq= 0, CH_1, rank 1
3630 10:01:46.178915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3631 10:01:46.179065 ==
3632 10:01:46.179167 RX Vref Scan: 0
3633 10:01:46.179264
3634 10:01:46.182641 RX Vref 0 -> 0, step: 1
3635 10:01:46.182718
3636 10:01:46.185810 RX Delay -21 -> 252, step: 4
3637 10:01:46.189114 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3638 10:01:46.192406 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3639 10:01:46.198874 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3640 10:01:46.202413 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3641 10:01:46.205969 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3642 10:01:46.208964 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3643 10:01:46.212465 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3644 10:01:46.218964 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3645 10:01:46.222700 iDelay=191, Bit 8, Center 96 (31 ~ 162) 132
3646 10:01:46.225717 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3647 10:01:46.229493 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3648 10:01:46.232434 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3649 10:01:46.235925 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3650 10:01:46.242217 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3651 10:01:46.245786 iDelay=191, Bit 14, Center 116 (51 ~ 182) 132
3652 10:01:46.249072 iDelay=191, Bit 15, Center 116 (51 ~ 182) 132
3653 10:01:46.249194 ==
3654 10:01:46.252513 Dram Type= 6, Freq= 0, CH_1, rank 1
3655 10:01:46.256504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3656 10:01:46.259198 ==
3657 10:01:46.259323 DQS Delay:
3658 10:01:46.259418 DQS0 = 0, DQS1 = 0
3659 10:01:46.262426 DQM Delay:
3660 10:01:46.262565 DQM0 = 113, DQM1 = 109
3661 10:01:46.266049 DQ Delay:
3662 10:01:46.269167 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =112
3663 10:01:46.272356 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3664 10:01:46.275896 DQ8 =96, DQ9 =98, DQ10 =110, DQ11 =102
3665 10:01:46.279412 DQ12 =114, DQ13 =120, DQ14 =116, DQ15 =116
3666 10:01:46.279517
3667 10:01:46.279586
3668 10:01:46.286078 [DQSOSCAuto] RK1, (LSB)MR18= 0xf6fd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 414 ps
3669 10:01:46.289483 CH1 RK1: MR19=303, MR18=F6FD
3670 10:01:46.296108 CH1_RK1: MR19=0x303, MR18=0xF6FD, DQSOSC=411, MR23=63, INC=38, DEC=25
3671 10:01:46.299266 [RxdqsGatingPostProcess] freq 1200
3672 10:01:46.305834 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3673 10:01:46.305991 best DQS0 dly(2T, 0.5T) = (0, 11)
3674 10:01:46.309444 best DQS1 dly(2T, 0.5T) = (0, 11)
3675 10:01:46.312203 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3676 10:01:46.315764 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3677 10:01:46.319258 best DQS0 dly(2T, 0.5T) = (0, 11)
3678 10:01:46.322456 best DQS1 dly(2T, 0.5T) = (0, 11)
3679 10:01:46.325865 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3680 10:01:46.329373 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3681 10:01:46.332792 Pre-setting of DQS Precalculation
3682 10:01:46.339385 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3683 10:01:46.345614 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3684 10:01:46.352654 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3685 10:01:46.352806
3686 10:01:46.352912
3687 10:01:46.355968 [Calibration Summary] 2400 Mbps
3688 10:01:46.356064 CH 0, Rank 0
3689 10:01:46.358867 SW Impedance : PASS
3690 10:01:46.358983 DUTY Scan : NO K
3691 10:01:46.362882 ZQ Calibration : PASS
3692 10:01:46.366074 Jitter Meter : NO K
3693 10:01:46.366172 CBT Training : PASS
3694 10:01:46.369501 Write leveling : PASS
3695 10:01:46.372364 RX DQS gating : PASS
3696 10:01:46.372494 RX DQ/DQS(RDDQC) : PASS
3697 10:01:46.375804 TX DQ/DQS : PASS
3698 10:01:46.379411 RX DATLAT : PASS
3699 10:01:46.379523 RX DQ/DQS(Engine): PASS
3700 10:01:46.382909 TX OE : NO K
3701 10:01:46.383003 All Pass.
3702 10:01:46.383070
3703 10:01:46.385791 CH 0, Rank 1
3704 10:01:46.385899 SW Impedance : PASS
3705 10:01:46.389014 DUTY Scan : NO K
3706 10:01:46.392528 ZQ Calibration : PASS
3707 10:01:46.392649 Jitter Meter : NO K
3708 10:01:46.395910 CBT Training : PASS
3709 10:01:46.399396 Write leveling : PASS
3710 10:01:46.399483 RX DQS gating : PASS
3711 10:01:46.402473 RX DQ/DQS(RDDQC) : PASS
3712 10:01:46.402597 TX DQ/DQS : PASS
3713 10:01:46.405687 RX DATLAT : PASS
3714 10:01:46.409252 RX DQ/DQS(Engine): PASS
3715 10:01:46.409382 TX OE : NO K
3716 10:01:46.412564 All Pass.
3717 10:01:46.412683
3718 10:01:46.412790 CH 1, Rank 0
3719 10:01:46.416462 SW Impedance : PASS
3720 10:01:46.416588 DUTY Scan : NO K
3721 10:01:46.419610 ZQ Calibration : PASS
3722 10:01:46.422743 Jitter Meter : NO K
3723 10:01:46.422885 CBT Training : PASS
3724 10:01:46.426016 Write leveling : PASS
3725 10:01:46.429403 RX DQS gating : PASS
3726 10:01:46.429517 RX DQ/DQS(RDDQC) : PASS
3727 10:01:46.432563 TX DQ/DQS : PASS
3728 10:01:46.432680 RX DATLAT : PASS
3729 10:01:46.436094 RX DQ/DQS(Engine): PASS
3730 10:01:46.439579 TX OE : NO K
3731 10:01:46.439701 All Pass.
3732 10:01:46.439815
3733 10:01:46.439909 CH 1, Rank 1
3734 10:01:46.442514 SW Impedance : PASS
3735 10:01:46.445915 DUTY Scan : NO K
3736 10:01:46.446007 ZQ Calibration : PASS
3737 10:01:46.449139 Jitter Meter : NO K
3738 10:01:46.452730 CBT Training : PASS
3739 10:01:46.452854 Write leveling : PASS
3740 10:01:46.456686 RX DQS gating : PASS
3741 10:01:46.459651 RX DQ/DQS(RDDQC) : PASS
3742 10:01:46.459786 TX DQ/DQS : PASS
3743 10:01:46.462562 RX DATLAT : PASS
3744 10:01:46.466388 RX DQ/DQS(Engine): PASS
3745 10:01:46.466514 TX OE : NO K
3746 10:01:46.466617 All Pass.
3747 10:01:46.469659
3748 10:01:46.469784 DramC Write-DBI off
3749 10:01:46.472785 PER_BANK_REFRESH: Hybrid Mode
3750 10:01:46.472895 TX_TRACKING: ON
3751 10:01:46.483335 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3752 10:01:46.486171 [FAST_K] Save calibration result to emmc
3753 10:01:46.489209 dramc_set_vcore_voltage set vcore to 650000
3754 10:01:46.492654 Read voltage for 600, 5
3755 10:01:46.492785 Vio18 = 0
3756 10:01:46.496000 Vcore = 650000
3757 10:01:46.496113 Vdram = 0
3758 10:01:46.496220 Vddq = 0
3759 10:01:46.496310 Vmddr = 0
3760 10:01:46.503096 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3761 10:01:46.509369 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3762 10:01:46.509509 MEM_TYPE=3, freq_sel=19
3763 10:01:46.512705 sv_algorithm_assistance_LP4_1600
3764 10:01:46.515805 ============ PULL DRAM RESETB DOWN ============
3765 10:01:46.522767 ========== PULL DRAM RESETB DOWN end =========
3766 10:01:46.526549 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3767 10:01:46.530148 ===================================
3768 10:01:46.532837 LPDDR4 DRAM CONFIGURATION
3769 10:01:46.536225 ===================================
3770 10:01:46.536315 EX_ROW_EN[0] = 0x0
3771 10:01:46.539665 EX_ROW_EN[1] = 0x0
3772 10:01:46.539747 LP4Y_EN = 0x0
3773 10:01:46.542903 WORK_FSP = 0x0
3774 10:01:46.542992 WL = 0x2
3775 10:01:46.545925 RL = 0x2
3776 10:01:46.546004 BL = 0x2
3777 10:01:46.549168 RPST = 0x0
3778 10:01:46.552669 RD_PRE = 0x0
3779 10:01:46.552764 WR_PRE = 0x1
3780 10:01:46.555836 WR_PST = 0x0
3781 10:01:46.555959 DBI_WR = 0x0
3782 10:01:46.559054 DBI_RD = 0x0
3783 10:01:46.559144 OTF = 0x1
3784 10:01:46.562438 ===================================
3785 10:01:46.566129 ===================================
3786 10:01:46.566221 ANA top config
3787 10:01:46.569215 ===================================
3788 10:01:46.572768 DLL_ASYNC_EN = 0
3789 10:01:46.576136 ALL_SLAVE_EN = 1
3790 10:01:46.579748 NEW_RANK_MODE = 1
3791 10:01:46.582873 DLL_IDLE_MODE = 1
3792 10:01:46.582969 LP45_APHY_COMB_EN = 1
3793 10:01:46.586133 TX_ODT_DIS = 1
3794 10:01:46.589323 NEW_8X_MODE = 1
3795 10:01:46.592667 ===================================
3796 10:01:46.596044 ===================================
3797 10:01:46.599369 data_rate = 1200
3798 10:01:46.602920 CKR = 1
3799 10:01:46.603019 DQ_P2S_RATIO = 8
3800 10:01:46.605816 ===================================
3801 10:01:46.609280 CA_P2S_RATIO = 8
3802 10:01:46.612759 DQ_CA_OPEN = 0
3803 10:01:46.616019 DQ_SEMI_OPEN = 0
3804 10:01:46.619543 CA_SEMI_OPEN = 0
3805 10:01:46.619643 CA_FULL_RATE = 0
3806 10:01:46.622643 DQ_CKDIV4_EN = 1
3807 10:01:46.626190 CA_CKDIV4_EN = 1
3808 10:01:46.629438 CA_PREDIV_EN = 0
3809 10:01:46.632733 PH8_DLY = 0
3810 10:01:46.636221 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3811 10:01:46.636319 DQ_AAMCK_DIV = 4
3812 10:01:46.639392 CA_AAMCK_DIV = 4
3813 10:01:46.642803 CA_ADMCK_DIV = 4
3814 10:01:46.646252 DQ_TRACK_CA_EN = 0
3815 10:01:46.649159 CA_PICK = 600
3816 10:01:46.652685 CA_MCKIO = 600
3817 10:01:46.656093 MCKIO_SEMI = 0
3818 10:01:46.656191 PLL_FREQ = 2288
3819 10:01:46.659611 DQ_UI_PI_RATIO = 32
3820 10:01:46.662666 CA_UI_PI_RATIO = 0
3821 10:01:46.665881 ===================================
3822 10:01:46.669336 ===================================
3823 10:01:46.672835 memory_type:LPDDR4
3824 10:01:46.672939 GP_NUM : 10
3825 10:01:46.676232 SRAM_EN : 1
3826 10:01:46.679717 MD32_EN : 0
3827 10:01:46.682921 ===================================
3828 10:01:46.683047 [ANA_INIT] >>>>>>>>>>>>>>
3829 10:01:46.685975 <<<<<< [CONFIGURE PHASE]: ANA_TX
3830 10:01:46.689216 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3831 10:01:46.692562 ===================================
3832 10:01:46.696050 data_rate = 1200,PCW = 0X5800
3833 10:01:46.699435 ===================================
3834 10:01:46.702660 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3835 10:01:46.709572 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3836 10:01:46.712912 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3837 10:01:46.719272 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3838 10:01:46.722701 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3839 10:01:46.726174 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3840 10:01:46.726266 [ANA_INIT] flow start
3841 10:01:46.729596 [ANA_INIT] PLL >>>>>>>>
3842 10:01:46.733255 [ANA_INIT] PLL <<<<<<<<
3843 10:01:46.733375 [ANA_INIT] MIDPI >>>>>>>>
3844 10:01:46.736212 [ANA_INIT] MIDPI <<<<<<<<
3845 10:01:46.739546 [ANA_INIT] DLL >>>>>>>>
3846 10:01:46.739662 [ANA_INIT] flow end
3847 10:01:46.746103 ============ LP4 DIFF to SE enter ============
3848 10:01:46.749843 ============ LP4 DIFF to SE exit ============
3849 10:01:46.753291 [ANA_INIT] <<<<<<<<<<<<<
3850 10:01:46.756191 [Flow] Enable top DCM control >>>>>
3851 10:01:46.756303 [Flow] Enable top DCM control <<<<<
3852 10:01:46.759714 Enable DLL master slave shuffle
3853 10:01:46.766286 ==============================================================
3854 10:01:46.769853 Gating Mode config
3855 10:01:46.773240 ==============================================================
3856 10:01:46.776382 Config description:
3857 10:01:46.786534 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3858 10:01:46.793497 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3859 10:01:46.796523 SELPH_MODE 0: By rank 1: By Phase
3860 10:01:46.802925 ==============================================================
3861 10:01:46.806238 GAT_TRACK_EN = 1
3862 10:01:46.809875 RX_GATING_MODE = 2
3863 10:01:46.809981 RX_GATING_TRACK_MODE = 2
3864 10:01:46.813327 SELPH_MODE = 1
3865 10:01:46.816326 PICG_EARLY_EN = 1
3866 10:01:46.819706 VALID_LAT_VALUE = 1
3867 10:01:46.826845 ==============================================================
3868 10:01:46.830077 Enter into Gating configuration >>>>
3869 10:01:46.833018 Exit from Gating configuration <<<<
3870 10:01:46.836439 Enter into DVFS_PRE_config >>>>>
3871 10:01:46.847081 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3872 10:01:46.850428 Exit from DVFS_PRE_config <<<<<
3873 10:01:46.853682 Enter into PICG configuration >>>>
3874 10:01:46.856690 Exit from PICG configuration <<<<
3875 10:01:46.860282 [RX_INPUT] configuration >>>>>
3876 10:01:46.860416 [RX_INPUT] configuration <<<<<
3877 10:01:46.867040 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3878 10:01:46.873451 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3879 10:01:46.876873 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3880 10:01:46.883773 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3881 10:01:46.890432 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3882 10:01:46.897101 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3883 10:01:46.900522 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3884 10:01:46.903467 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3885 10:01:46.910145 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3886 10:01:46.913392 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3887 10:01:46.916683 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3888 10:01:46.923566 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3889 10:01:46.927063 ===================================
3890 10:01:46.927187 LPDDR4 DRAM CONFIGURATION
3891 10:01:46.930016 ===================================
3892 10:01:46.933622 EX_ROW_EN[0] = 0x0
3893 10:01:46.933749 EX_ROW_EN[1] = 0x0
3894 10:01:46.936799 LP4Y_EN = 0x0
3895 10:01:46.936895 WORK_FSP = 0x0
3896 10:01:46.940250 WL = 0x2
3897 10:01:46.940342 RL = 0x2
3898 10:01:46.943736 BL = 0x2
3899 10:01:46.946469 RPST = 0x0
3900 10:01:46.946564 RD_PRE = 0x0
3901 10:01:46.949969 WR_PRE = 0x1
3902 10:01:46.950066 WR_PST = 0x0
3903 10:01:46.953842 DBI_WR = 0x0
3904 10:01:46.953941 DBI_RD = 0x0
3905 10:01:46.956840 OTF = 0x1
3906 10:01:46.960038 ===================================
3907 10:01:46.963401 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3908 10:01:46.966439 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3909 10:01:46.970235 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3910 10:01:46.973359 ===================================
3911 10:01:46.977209 LPDDR4 DRAM CONFIGURATION
3912 10:01:46.979881 ===================================
3913 10:01:46.983658 EX_ROW_EN[0] = 0x10
3914 10:01:46.983766 EX_ROW_EN[1] = 0x0
3915 10:01:46.986608 LP4Y_EN = 0x0
3916 10:01:46.986699 WORK_FSP = 0x0
3917 10:01:46.990133 WL = 0x2
3918 10:01:46.990226 RL = 0x2
3919 10:01:46.992985 BL = 0x2
3920 10:01:46.993074 RPST = 0x0
3921 10:01:46.996848 RD_PRE = 0x0
3922 10:01:46.996945 WR_PRE = 0x1
3923 10:01:46.999924 WR_PST = 0x0
3924 10:01:47.000013 DBI_WR = 0x0
3925 10:01:47.003068 DBI_RD = 0x0
3926 10:01:47.006614 OTF = 0x1
3927 10:01:47.006722 ===================================
3928 10:01:47.013512 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3929 10:01:47.018191 nWR fixed to 30
3930 10:01:47.021630 [ModeRegInit_LP4] CH0 RK0
3931 10:01:47.021735 [ModeRegInit_LP4] CH0 RK1
3932 10:01:47.024873 [ModeRegInit_LP4] CH1 RK0
3933 10:01:47.028253 [ModeRegInit_LP4] CH1 RK1
3934 10:01:47.028351 match AC timing 17
3935 10:01:47.035244 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3936 10:01:47.038585 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3937 10:01:47.041526 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3938 10:01:47.048548 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3939 10:01:47.052147 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3940 10:01:47.052250 ==
3941 10:01:47.055115 Dram Type= 6, Freq= 0, CH_0, rank 0
3942 10:01:47.058451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3943 10:01:47.058561 ==
3944 10:01:47.065046 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3945 10:01:47.071821 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3946 10:01:47.075049 [CA 0] Center 36 (6~66) winsize 61
3947 10:01:47.078230 [CA 1] Center 35 (5~66) winsize 62
3948 10:01:47.081986 [CA 2] Center 34 (4~65) winsize 62
3949 10:01:47.085009 [CA 3] Center 34 (4~64) winsize 61
3950 10:01:47.088608 [CA 4] Center 33 (3~64) winsize 62
3951 10:01:47.091927 [CA 5] Center 33 (3~64) winsize 62
3952 10:01:47.092029
3953 10:01:47.094911 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3954 10:01:47.095011
3955 10:01:47.098383 [CATrainingPosCal] consider 1 rank data
3956 10:01:47.102023 u2DelayCellTimex100 = 270/100 ps
3957 10:01:47.105011 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3958 10:01:47.108571 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3959 10:01:47.111655 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3960 10:01:47.114976 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3961 10:01:47.118484 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3962 10:01:47.121586 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3963 10:01:47.121682
3964 10:01:47.125464 CA PerBit enable=1, Macro0, CA PI delay=33
3965 10:01:47.128573
3966 10:01:47.128665 [CBTSetCACLKResult] CA Dly = 33
3967 10:01:47.131754 CS Dly: 5 (0~36)
3968 10:01:47.131844 ==
3969 10:01:47.135213 Dram Type= 6, Freq= 0, CH_0, rank 1
3970 10:01:47.138577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3971 10:01:47.138673 ==
3972 10:01:47.145520 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3973 10:01:47.152173 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3974 10:01:47.155254 [CA 0] Center 35 (5~66) winsize 62
3975 10:01:47.158813 [CA 1] Center 35 (5~66) winsize 62
3976 10:01:47.162168 [CA 2] Center 34 (4~65) winsize 62
3977 10:01:47.165078 [CA 3] Center 34 (4~65) winsize 62
3978 10:01:47.168539 [CA 4] Center 33 (3~64) winsize 62
3979 10:01:47.171746 [CA 5] Center 33 (3~64) winsize 62
3980 10:01:47.171842
3981 10:01:47.175017 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3982 10:01:47.175112
3983 10:01:47.178332 [CATrainingPosCal] consider 2 rank data
3984 10:01:47.181973 u2DelayCellTimex100 = 270/100 ps
3985 10:01:47.184861 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3986 10:01:47.188600 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3987 10:01:47.191857 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3988 10:01:47.194913 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3989 10:01:47.198602 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3990 10:01:47.201729 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3991 10:01:47.201852
3992 10:01:47.208316 CA PerBit enable=1, Macro0, CA PI delay=33
3993 10:01:47.208444
3994 10:01:47.208515 [CBTSetCACLKResult] CA Dly = 33
3995 10:01:47.211820 CS Dly: 4 (0~35)
3996 10:01:47.211914
3997 10:01:47.215280 ----->DramcWriteLeveling(PI) begin...
3998 10:01:47.215375 ==
3999 10:01:47.218687 Dram Type= 6, Freq= 0, CH_0, rank 0
4000 10:01:47.222230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4001 10:01:47.222327 ==
4002 10:01:47.225056 Write leveling (Byte 0): 34 => 34
4003 10:01:47.228499 Write leveling (Byte 1): 30 => 30
4004 10:01:47.232444 DramcWriteLeveling(PI) end<-----
4005 10:01:47.232548
4006 10:01:47.232617 ==
4007 10:01:47.235067 Dram Type= 6, Freq= 0, CH_0, rank 0
4008 10:01:47.238542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4009 10:01:47.241690 ==
4010 10:01:47.241789 [Gating] SW mode calibration
4011 10:01:47.248615 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4012 10:01:47.255103 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4013 10:01:47.258687 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4014 10:01:47.265545 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4015 10:01:47.268857 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4016 10:01:47.271891 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4017 10:01:47.275383 0 9 16 | B1->B0 | 3030 2e2e | 1 0 | (1 1) (1 0)
4018 10:01:47.282296 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4019 10:01:47.285404 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4020 10:01:47.288810 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4021 10:01:47.295369 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4022 10:01:47.298703 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4023 10:01:47.302073 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4024 10:01:47.308733 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4025 10:01:47.312290 0 10 16 | B1->B0 | 2a2a 3a3a | 0 1 | (0 0) (0 0)
4026 10:01:47.315444 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 10:01:47.321934 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 10:01:47.325323 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4029 10:01:47.328956 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 10:01:47.335377 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4031 10:01:47.338795 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4032 10:01:47.341983 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4033 10:01:47.348812 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4034 10:01:47.352174 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 10:01:47.355533 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 10:01:47.362412 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 10:01:47.365468 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 10:01:47.368913 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 10:01:47.372530 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 10:01:47.378990 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 10:01:47.382382 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 10:01:47.385245 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 10:01:47.392220 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 10:01:47.395687 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 10:01:47.398806 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 10:01:47.405548 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 10:01:47.408681 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 10:01:47.411885 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 10:01:47.418697 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4050 10:01:47.422131 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 10:01:47.425513 Total UI for P1: 0, mck2ui 16
4052 10:01:47.428867 best dqsien dly found for B0: ( 0, 13, 16)
4053 10:01:47.432360 Total UI for P1: 0, mck2ui 16
4054 10:01:47.435839 best dqsien dly found for B1: ( 0, 13, 16)
4055 10:01:47.438815 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4056 10:01:47.442344 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4057 10:01:47.442457
4058 10:01:47.445786 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4059 10:01:47.448922 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4060 10:01:47.452318 [Gating] SW calibration Done
4061 10:01:47.452417 ==
4062 10:01:47.455708 Dram Type= 6, Freq= 0, CH_0, rank 0
4063 10:01:47.458674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4064 10:01:47.458817 ==
4065 10:01:47.462224 RX Vref Scan: 0
4066 10:01:47.462335
4067 10:01:47.465708 RX Vref 0 -> 0, step: 1
4068 10:01:47.465817
4069 10:01:47.468932 RX Delay -230 -> 252, step: 16
4070 10:01:47.472124 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4071 10:01:47.475676 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4072 10:01:47.479260 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4073 10:01:47.482040 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4074 10:01:47.489113 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4075 10:01:47.492549 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4076 10:01:47.495500 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4077 10:01:47.498820 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4078 10:01:47.505250 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4079 10:01:47.508680 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4080 10:01:47.511930 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4081 10:01:47.515537 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4082 10:01:47.518965 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4083 10:01:47.525337 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4084 10:01:47.528842 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4085 10:01:47.531981 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4086 10:01:47.532085 ==
4087 10:01:47.535342 Dram Type= 6, Freq= 0, CH_0, rank 0
4088 10:01:47.539123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4089 10:01:47.541998 ==
4090 10:01:47.542107 DQS Delay:
4091 10:01:47.542175 DQS0 = 0, DQS1 = 0
4092 10:01:47.545666 DQM Delay:
4093 10:01:47.545756 DQM0 = 43, DQM1 = 35
4094 10:01:47.549107 DQ Delay:
4095 10:01:47.549221 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4096 10:01:47.552110 DQ4 =41, DQ5 =41, DQ6 =49, DQ7 =49
4097 10:01:47.555630 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =25
4098 10:01:47.558582 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =49
4099 10:01:47.558697
4100 10:01:47.562416
4101 10:01:47.562527 ==
4102 10:01:47.566257 Dram Type= 6, Freq= 0, CH_0, rank 0
4103 10:01:47.568609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4104 10:01:47.568696 ==
4105 10:01:47.568763
4106 10:01:47.568824
4107 10:01:47.572179 TX Vref Scan disable
4108 10:01:47.572255 == TX Byte 0 ==
4109 10:01:47.578982 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4110 10:01:47.582122 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4111 10:01:47.582229 == TX Byte 1 ==
4112 10:01:47.588955 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4113 10:01:47.592395 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4114 10:01:47.592531 ==
4115 10:01:47.595309 Dram Type= 6, Freq= 0, CH_0, rank 0
4116 10:01:47.598729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4117 10:01:47.598844 ==
4118 10:01:47.598953
4119 10:01:47.599046
4120 10:01:47.602264 TX Vref Scan disable
4121 10:01:47.605714 == TX Byte 0 ==
4122 10:01:47.609044 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4123 10:01:47.612252 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4124 10:01:47.615769 == TX Byte 1 ==
4125 10:01:47.618678 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4126 10:01:47.622536 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4127 10:01:47.622674
4128 10:01:47.625881 [DATLAT]
4129 10:01:47.625990 Freq=600, CH0 RK0
4130 10:01:47.626083
4131 10:01:47.629275 DATLAT Default: 0x9
4132 10:01:47.629378 0, 0xFFFF, sum = 0
4133 10:01:47.632155 1, 0xFFFF, sum = 0
4134 10:01:47.632257 2, 0xFFFF, sum = 0
4135 10:01:47.635679 3, 0xFFFF, sum = 0
4136 10:01:47.635792 4, 0xFFFF, sum = 0
4137 10:01:47.639228 5, 0xFFFF, sum = 0
4138 10:01:47.639348 6, 0xFFFF, sum = 0
4139 10:01:47.642631 7, 0xFFFF, sum = 0
4140 10:01:47.642743 8, 0x0, sum = 1
4141 10:01:47.645843 9, 0x0, sum = 2
4142 10:01:47.645938 10, 0x0, sum = 3
4143 10:01:47.648965 11, 0x0, sum = 4
4144 10:01:47.649079 best_step = 9
4145 10:01:47.649179
4146 10:01:47.649268 ==
4147 10:01:47.652523 Dram Type= 6, Freq= 0, CH_0, rank 0
4148 10:01:47.655739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 10:01:47.659284 ==
4150 10:01:47.659415 RX Vref Scan: 1
4151 10:01:47.659510
4152 10:01:47.662075 RX Vref 0 -> 0, step: 1
4153 10:01:47.662157
4154 10:01:47.665635 RX Delay -195 -> 252, step: 8
4155 10:01:47.665743
4156 10:01:47.665842 Set Vref, RX VrefLevel [Byte0]: 53
4157 10:01:47.669137 [Byte1]: 51
4158 10:01:47.673735
4159 10:01:47.673849 Final RX Vref Byte 0 = 53 to rank0
4160 10:01:47.677353 Final RX Vref Byte 1 = 51 to rank0
4161 10:01:47.680780 Final RX Vref Byte 0 = 53 to rank1
4162 10:01:47.683781 Final RX Vref Byte 1 = 51 to rank1==
4163 10:01:47.687477 Dram Type= 6, Freq= 0, CH_0, rank 0
4164 10:01:47.693983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4165 10:01:47.694099 ==
4166 10:01:47.694179 DQS Delay:
4167 10:01:47.694244 DQS0 = 0, DQS1 = 0
4168 10:01:47.697451 DQM Delay:
4169 10:01:47.697573 DQM0 = 42, DQM1 = 33
4170 10:01:47.700397 DQ Delay:
4171 10:01:47.703832 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4172 10:01:47.703948 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4173 10:01:47.707206 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4174 10:01:47.710715 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4175 10:01:47.714292
4176 10:01:47.714414
4177 10:01:47.721086 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c1c, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
4178 10:01:47.723712 CH0 RK0: MR19=808, MR18=3C1C
4179 10:01:47.730471 CH0_RK0: MR19=0x808, MR18=0x3C1C, DQSOSC=398, MR23=63, INC=165, DEC=110
4180 10:01:47.730621
4181 10:01:47.734255 ----->DramcWriteLeveling(PI) begin...
4182 10:01:47.734380 ==
4183 10:01:47.737005 Dram Type= 6, Freq= 0, CH_0, rank 1
4184 10:01:47.740550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4185 10:01:47.740671 ==
4186 10:01:47.743757 Write leveling (Byte 0): 33 => 33
4187 10:01:47.747438 Write leveling (Byte 1): 30 => 30
4188 10:01:47.750591 DramcWriteLeveling(PI) end<-----
4189 10:01:47.750711
4190 10:01:47.750810 ==
4191 10:01:47.754102 Dram Type= 6, Freq= 0, CH_0, rank 1
4192 10:01:47.757450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4193 10:01:47.757540 ==
4194 10:01:47.760694 [Gating] SW mode calibration
4195 10:01:47.767250 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4196 10:01:47.773869 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4197 10:01:47.777337 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4198 10:01:47.780934 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4199 10:01:47.787221 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4200 10:01:47.790997 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
4201 10:01:47.794032 0 9 16 | B1->B0 | 2f2f 2424 | 0 0 | (0 1) (0 0)
4202 10:01:47.801088 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4203 10:01:47.804076 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4204 10:01:47.807556 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4205 10:01:47.811094 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4206 10:01:47.817766 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4207 10:01:47.820738 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4208 10:01:47.824619 0 10 12 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
4209 10:01:47.831091 0 10 16 | B1->B0 | 3b3b 4545 | 0 0 | (0 0) (0 0)
4210 10:01:47.834321 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4211 10:01:47.837931 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4212 10:01:47.844459 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4213 10:01:47.847823 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4214 10:01:47.851132 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4215 10:01:47.857892 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4216 10:01:47.861189 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4217 10:01:47.864732 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4218 10:01:47.870937 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 10:01:47.874305 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 10:01:47.877848 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 10:01:47.884315 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 10:01:47.887494 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 10:01:47.890843 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 10:01:47.897861 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 10:01:47.900724 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 10:01:47.904277 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 10:01:47.907826 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 10:01:47.914563 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 10:01:47.917680 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 10:01:47.920942 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 10:01:47.927349 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4232 10:01:47.930800 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4233 10:01:47.934346 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 10:01:47.937336 Total UI for P1: 0, mck2ui 16
4235 10:01:47.941131 best dqsien dly found for B0: ( 0, 13, 10)
4236 10:01:47.944494 Total UI for P1: 0, mck2ui 16
4237 10:01:47.947904 best dqsien dly found for B1: ( 0, 13, 14)
4238 10:01:47.950983 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4239 10:01:47.954253 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4240 10:01:47.954367
4241 10:01:47.960990 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4242 10:01:47.964411 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4243 10:01:47.967971 [Gating] SW calibration Done
4244 10:01:47.968088 ==
4245 10:01:47.971352 Dram Type= 6, Freq= 0, CH_0, rank 1
4246 10:01:47.974694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4247 10:01:47.974808 ==
4248 10:01:47.974921 RX Vref Scan: 0
4249 10:01:47.974987
4250 10:01:47.977911 RX Vref 0 -> 0, step: 1
4251 10:01:47.977998
4252 10:01:47.980993 RX Delay -230 -> 252, step: 16
4253 10:01:47.984481 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4254 10:01:47.987682 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4255 10:01:47.994343 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4256 10:01:47.997815 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4257 10:01:48.001383 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4258 10:01:48.004269 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4259 10:01:48.010772 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4260 10:01:48.014192 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4261 10:01:48.017544 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4262 10:01:48.021074 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4263 10:01:48.024428 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4264 10:01:48.031193 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4265 10:01:48.035171 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4266 10:01:48.037780 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4267 10:01:48.041142 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4268 10:01:48.047954 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4269 10:01:48.048095 ==
4270 10:01:48.051470 Dram Type= 6, Freq= 0, CH_0, rank 1
4271 10:01:48.054619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4272 10:01:48.054754 ==
4273 10:01:48.054853 DQS Delay:
4274 10:01:48.058384 DQS0 = 0, DQS1 = 0
4275 10:01:48.058503 DQM Delay:
4276 10:01:48.061512 DQM0 = 39, DQM1 = 33
4277 10:01:48.061608 DQ Delay:
4278 10:01:48.064773 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4279 10:01:48.067837 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4280 10:01:48.071697 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4281 10:01:48.074785 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4282 10:01:48.074931
4283 10:01:48.075038
4284 10:01:48.075137 ==
4285 10:01:48.077944 Dram Type= 6, Freq= 0, CH_0, rank 1
4286 10:01:48.081412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4287 10:01:48.081542 ==
4288 10:01:48.081639
4289 10:01:48.081730
4290 10:01:48.085214 TX Vref Scan disable
4291 10:01:48.087968 == TX Byte 0 ==
4292 10:01:48.091364 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4293 10:01:48.094954 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4294 10:01:48.098175 == TX Byte 1 ==
4295 10:01:48.101607 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4296 10:01:48.105082 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4297 10:01:48.105209 ==
4298 10:01:48.108591 Dram Type= 6, Freq= 0, CH_0, rank 1
4299 10:01:48.111395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4300 10:01:48.114929 ==
4301 10:01:48.115051
4302 10:01:48.115141
4303 10:01:48.115205 TX Vref Scan disable
4304 10:01:48.118630 == TX Byte 0 ==
4305 10:01:48.121998 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4306 10:01:48.125279 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4307 10:01:48.128584 == TX Byte 1 ==
4308 10:01:48.132057 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4309 10:01:48.135391 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4310 10:01:48.138798
4311 10:01:48.138939 [DATLAT]
4312 10:01:48.139043 Freq=600, CH0 RK1
4313 10:01:48.139142
4314 10:01:48.141956 DATLAT Default: 0x9
4315 10:01:48.142042 0, 0xFFFF, sum = 0
4316 10:01:48.145614 1, 0xFFFF, sum = 0
4317 10:01:48.145707 2, 0xFFFF, sum = 0
4318 10:01:48.148815 3, 0xFFFF, sum = 0
4319 10:01:48.148908 4, 0xFFFF, sum = 0
4320 10:01:48.152082 5, 0xFFFF, sum = 0
4321 10:01:48.152173 6, 0xFFFF, sum = 0
4322 10:01:48.155524 7, 0xFFFF, sum = 0
4323 10:01:48.155611 8, 0x0, sum = 1
4324 10:01:48.158874 9, 0x0, sum = 2
4325 10:01:48.158961 10, 0x0, sum = 3
4326 10:01:48.162350 11, 0x0, sum = 4
4327 10:01:48.162429 best_step = 9
4328 10:01:48.162495
4329 10:01:48.162556 ==
4330 10:01:48.165669 Dram Type= 6, Freq= 0, CH_0, rank 1
4331 10:01:48.172517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4332 10:01:48.172620 ==
4333 10:01:48.172687 RX Vref Scan: 0
4334 10:01:48.172748
4335 10:01:48.175514 RX Vref 0 -> 0, step: 1
4336 10:01:48.175600
4337 10:01:48.178852 RX Delay -179 -> 252, step: 8
4338 10:01:48.181924 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4339 10:01:48.188681 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4340 10:01:48.191885 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4341 10:01:48.195302 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4342 10:01:48.198834 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4343 10:01:48.202365 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4344 10:01:48.208999 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4345 10:01:48.211986 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4346 10:01:48.215400 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4347 10:01:48.218757 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4348 10:01:48.222303 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4349 10:01:48.228528 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4350 10:01:48.232038 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4351 10:01:48.235112 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4352 10:01:48.238848 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4353 10:01:48.245195 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4354 10:01:48.245301 ==
4355 10:01:48.249013 Dram Type= 6, Freq= 0, CH_0, rank 1
4356 10:01:48.252134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4357 10:01:48.252229 ==
4358 10:01:48.252300 DQS Delay:
4359 10:01:48.255158 DQS0 = 0, DQS1 = 0
4360 10:01:48.255243 DQM Delay:
4361 10:01:48.258708 DQM0 = 39, DQM1 = 33
4362 10:01:48.258798 DQ Delay:
4363 10:01:48.262132 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4364 10:01:48.265740 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =44
4365 10:01:48.268603 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4366 10:01:48.272075 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4367 10:01:48.272196
4368 10:01:48.272294
4369 10:01:48.278600 [DQSOSCAuto] RK1, (LSB)MR18= 0x5032, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 394 ps
4370 10:01:48.282182 CH0 RK1: MR19=808, MR18=5032
4371 10:01:48.288463 CH0_RK1: MR19=0x808, MR18=0x5032, DQSOSC=394, MR23=63, INC=168, DEC=112
4372 10:01:48.292035 [RxdqsGatingPostProcess] freq 600
4373 10:01:48.298504 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4374 10:01:48.301677 Pre-setting of DQS Precalculation
4375 10:01:48.305074 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4376 10:01:48.305185 ==
4377 10:01:48.308508 Dram Type= 6, Freq= 0, CH_1, rank 0
4378 10:01:48.312121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4379 10:01:48.312245 ==
4380 10:01:48.318523 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4381 10:01:48.325436 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4382 10:01:48.328823 [CA 0] Center 35 (5~66) winsize 62
4383 10:01:48.331872 [CA 1] Center 35 (5~65) winsize 61
4384 10:01:48.334951 [CA 2] Center 34 (4~65) winsize 62
4385 10:01:48.338555 [CA 3] Center 33 (3~64) winsize 62
4386 10:01:48.341950 [CA 4] Center 33 (3~64) winsize 62
4387 10:01:48.345488 [CA 5] Center 33 (3~64) winsize 62
4388 10:01:48.345593
4389 10:01:48.348886 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4390 10:01:48.348979
4391 10:01:48.351820 [CATrainingPosCal] consider 1 rank data
4392 10:01:48.355134 u2DelayCellTimex100 = 270/100 ps
4393 10:01:48.358616 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4394 10:01:48.361776 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4395 10:01:48.365367 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4396 10:01:48.368471 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4397 10:01:48.371746 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4398 10:01:48.375099 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4399 10:01:48.378665
4400 10:01:48.381957 CA PerBit enable=1, Macro0, CA PI delay=33
4401 10:01:48.382073
4402 10:01:48.385757 [CBTSetCACLKResult] CA Dly = 33
4403 10:01:48.385875 CS Dly: 3 (0~34)
4404 10:01:48.385970 ==
4405 10:01:48.388968 Dram Type= 6, Freq= 0, CH_1, rank 1
4406 10:01:48.392345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4407 10:01:48.392470 ==
4408 10:01:48.398464 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4409 10:01:48.405478 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4410 10:01:48.408844 [CA 0] Center 35 (5~66) winsize 62
4411 10:01:48.411873 [CA 1] Center 36 (6~66) winsize 61
4412 10:01:48.415708 [CA 2] Center 34 (4~65) winsize 62
4413 10:01:48.418631 [CA 3] Center 34 (3~65) winsize 63
4414 10:01:48.422138 [CA 4] Center 34 (3~65) winsize 63
4415 10:01:48.425685 [CA 5] Center 33 (3~64) winsize 62
4416 10:01:48.425786
4417 10:01:48.428583 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4418 10:01:48.428677
4419 10:01:48.431903 [CATrainingPosCal] consider 2 rank data
4420 10:01:48.435292 u2DelayCellTimex100 = 270/100 ps
4421 10:01:48.438610 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4422 10:01:48.442339 CA1 delay=35 (6~65),Diff = 2 PI (19 cell)
4423 10:01:48.445774 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4424 10:01:48.449250 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4425 10:01:48.452274 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4426 10:01:48.455758 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4427 10:01:48.455848
4428 10:01:48.462487 CA PerBit enable=1, Macro0, CA PI delay=33
4429 10:01:48.462601
4430 10:01:48.465503 [CBTSetCACLKResult] CA Dly = 33
4431 10:01:48.465591 CS Dly: 4 (0~36)
4432 10:01:48.465656
4433 10:01:48.468848 ----->DramcWriteLeveling(PI) begin...
4434 10:01:48.468927 ==
4435 10:01:48.472216 Dram Type= 6, Freq= 0, CH_1, rank 0
4436 10:01:48.475457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4437 10:01:48.475545 ==
4438 10:01:48.478692 Write leveling (Byte 0): 30 => 30
4439 10:01:48.482329 Write leveling (Byte 1): 29 => 29
4440 10:01:48.485679 DramcWriteLeveling(PI) end<-----
4441 10:01:48.485786
4442 10:01:48.485856 ==
4443 10:01:48.489053 Dram Type= 6, Freq= 0, CH_1, rank 0
4444 10:01:48.495503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4445 10:01:48.495614 ==
4446 10:01:48.495684 [Gating] SW mode calibration
4447 10:01:48.505501 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4448 10:01:48.508879 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4449 10:01:48.512175 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4450 10:01:48.518915 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4451 10:01:48.522367 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4452 10:01:48.525291 0 9 12 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 0)
4453 10:01:48.532494 0 9 16 | B1->B0 | 2828 2727 | 0 0 | (0 0) (1 1)
4454 10:01:48.535997 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4455 10:01:48.539290 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4456 10:01:48.545607 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4457 10:01:48.549069 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4458 10:01:48.552348 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4459 10:01:48.558765 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4460 10:01:48.562189 0 10 12 | B1->B0 | 2929 2a2a | 0 0 | (0 0) (0 0)
4461 10:01:48.565782 0 10 16 | B1->B0 | 3d3d 4141 | 0 0 | (0 0) (0 0)
4462 10:01:48.572212 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 10:01:48.575801 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 10:01:48.579059 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4465 10:01:48.582444 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4466 10:01:48.588824 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4467 10:01:48.592391 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4468 10:01:48.595648 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4469 10:01:48.601945 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4470 10:01:48.605498 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 10:01:48.608971 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 10:01:48.615832 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 10:01:48.619015 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 10:01:48.622370 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 10:01:48.628957 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 10:01:48.632504 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 10:01:48.635501 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 10:01:48.642300 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 10:01:48.645711 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 10:01:48.649233 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 10:01:48.656023 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 10:01:48.658933 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 10:01:48.662401 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 10:01:48.665917 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4485 10:01:48.672753 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 10:01:48.676097 Total UI for P1: 0, mck2ui 16
4487 10:01:48.679316 best dqsien dly found for B0: ( 0, 13, 14)
4488 10:01:48.679432 Total UI for P1: 0, mck2ui 16
4489 10:01:48.685748 best dqsien dly found for B1: ( 0, 13, 12)
4490 10:01:48.689354 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4491 10:01:48.692615 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4492 10:01:48.692735
4493 10:01:48.696259 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4494 10:01:48.699081 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4495 10:01:48.702459 [Gating] SW calibration Done
4496 10:01:48.702555 ==
4497 10:01:48.706004 Dram Type= 6, Freq= 0, CH_1, rank 0
4498 10:01:48.709222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4499 10:01:48.709317 ==
4500 10:01:48.712356 RX Vref Scan: 0
4501 10:01:48.712477
4502 10:01:48.712574 RX Vref 0 -> 0, step: 1
4503 10:01:48.712669
4504 10:01:48.716475 RX Delay -230 -> 252, step: 16
4505 10:01:48.722635 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4506 10:01:48.725824 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4507 10:01:48.729440 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4508 10:01:48.732461 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4509 10:01:48.735898 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4510 10:01:48.742610 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4511 10:01:48.745986 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4512 10:01:48.749552 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4513 10:01:48.752438 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4514 10:01:48.759156 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4515 10:01:48.762641 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4516 10:01:48.765662 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4517 10:01:48.769109 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4518 10:01:48.772525 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4519 10:01:48.779449 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4520 10:01:48.782287 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4521 10:01:48.782398 ==
4522 10:01:48.785786 Dram Type= 6, Freq= 0, CH_1, rank 0
4523 10:01:48.789277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4524 10:01:48.789400 ==
4525 10:01:48.792861 DQS Delay:
4526 10:01:48.792981 DQS0 = 0, DQS1 = 0
4527 10:01:48.793083 DQM Delay:
4528 10:01:48.795830 DQM0 = 44, DQM1 = 34
4529 10:01:48.795936 DQ Delay:
4530 10:01:48.799317 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4531 10:01:48.802663 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4532 10:01:48.806186 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4533 10:01:48.809137 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4534 10:01:48.809247
4535 10:01:48.809339
4536 10:01:48.809439 ==
4537 10:01:48.812810 Dram Type= 6, Freq= 0, CH_1, rank 0
4538 10:01:48.819482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4539 10:01:48.819608 ==
4540 10:01:48.819682
4541 10:01:48.819745
4542 10:01:48.819817 TX Vref Scan disable
4543 10:01:48.823113 == TX Byte 0 ==
4544 10:01:48.826240 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4545 10:01:48.833176 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4546 10:01:48.833321 == TX Byte 1 ==
4547 10:01:48.836573 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4548 10:01:48.843207 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4549 10:01:48.843334 ==
4550 10:01:48.846560 Dram Type= 6, Freq= 0, CH_1, rank 0
4551 10:01:48.849839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4552 10:01:48.849958 ==
4553 10:01:48.850027
4554 10:01:48.850088
4555 10:01:48.852772 TX Vref Scan disable
4556 10:01:48.852883 == TX Byte 0 ==
4557 10:01:48.859479 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4558 10:01:48.862795 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4559 10:01:48.862925 == TX Byte 1 ==
4560 10:01:48.869969 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4561 10:01:48.872741 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4562 10:01:48.872877
4563 10:01:48.872965 [DATLAT]
4564 10:01:48.876129 Freq=600, CH1 RK0
4565 10:01:48.876257
4566 10:01:48.876330 DATLAT Default: 0x9
4567 10:01:48.879995 0, 0xFFFF, sum = 0
4568 10:01:48.880120 1, 0xFFFF, sum = 0
4569 10:01:48.883158 2, 0xFFFF, sum = 0
4570 10:01:48.883292 3, 0xFFFF, sum = 0
4571 10:01:48.886207 4, 0xFFFF, sum = 0
4572 10:01:48.886293 5, 0xFFFF, sum = 0
4573 10:01:48.889788 6, 0xFFFF, sum = 0
4574 10:01:48.893209 7, 0xFFFF, sum = 0
4575 10:01:48.893335 8, 0x0, sum = 1
4576 10:01:48.893458 9, 0x0, sum = 2
4577 10:01:48.896143 10, 0x0, sum = 3
4578 10:01:48.896274 11, 0x0, sum = 4
4579 10:01:48.899625 best_step = 9
4580 10:01:48.899721
4581 10:01:48.899787 ==
4582 10:01:48.903250 Dram Type= 6, Freq= 0, CH_1, rank 0
4583 10:01:48.906536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4584 10:01:48.906666 ==
4585 10:01:48.909569 RX Vref Scan: 1
4586 10:01:48.909664
4587 10:01:48.909731 RX Vref 0 -> 0, step: 1
4588 10:01:48.909793
4589 10:01:48.913038 RX Delay -195 -> 252, step: 8
4590 10:01:48.913147
4591 10:01:48.916134 Set Vref, RX VrefLevel [Byte0]: 58
4592 10:01:48.919484 [Byte1]: 52
4593 10:01:48.923359
4594 10:01:48.923465 Final RX Vref Byte 0 = 58 to rank0
4595 10:01:48.927020 Final RX Vref Byte 1 = 52 to rank0
4596 10:01:48.930985 Final RX Vref Byte 0 = 58 to rank1
4597 10:01:48.933519 Final RX Vref Byte 1 = 52 to rank1==
4598 10:01:48.936655 Dram Type= 6, Freq= 0, CH_1, rank 0
4599 10:01:48.943503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4600 10:01:48.943648 ==
4601 10:01:48.943774 DQS Delay:
4602 10:01:48.943842 DQS0 = 0, DQS1 = 0
4603 10:01:48.946952 DQM Delay:
4604 10:01:48.947034 DQM0 = 41, DQM1 = 33
4605 10:01:48.949977 DQ Delay:
4606 10:01:48.953620 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =44
4607 10:01:48.953716 DQ4 =44, DQ5 =48, DQ6 =52, DQ7 =36
4608 10:01:48.956658 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4609 10:01:48.960131 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4610 10:01:48.963624
4611 10:01:48.963746
4612 10:01:48.970451 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e05, (MSB)MR19= 0x808, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
4613 10:01:48.973595 CH1 RK0: MR19=808, MR18=3E05
4614 10:01:48.980295 CH1_RK0: MR19=0x808, MR18=0x3E05, DQSOSC=398, MR23=63, INC=165, DEC=110
4615 10:01:48.980415
4616 10:01:48.983414 ----->DramcWriteLeveling(PI) begin...
4617 10:01:48.983526 ==
4618 10:01:48.986737 Dram Type= 6, Freq= 0, CH_1, rank 1
4619 10:01:48.990291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4620 10:01:48.990416 ==
4621 10:01:48.993185 Write leveling (Byte 0): 32 => 32
4622 10:01:48.996705 Write leveling (Byte 1): 30 => 30
4623 10:01:49.000490 DramcWriteLeveling(PI) end<-----
4624 10:01:49.000590
4625 10:01:49.000658 ==
4626 10:01:49.003489 Dram Type= 6, Freq= 0, CH_1, rank 1
4627 10:01:49.006694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4628 10:01:49.006823 ==
4629 10:01:49.009925 [Gating] SW mode calibration
4630 10:01:49.016458 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4631 10:01:49.023073 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4632 10:01:49.026737 0 9 0 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
4633 10:01:49.029931 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4634 10:01:49.036383 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4635 10:01:49.039938 0 9 12 | B1->B0 | 3030 2b2b | 1 0 | (1 1) (0 0)
4636 10:01:49.042962 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4637 10:01:49.049545 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4638 10:01:49.053632 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4639 10:01:49.056212 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4640 10:01:49.063152 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4641 10:01:49.066198 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4642 10:01:49.069617 0 10 8 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
4643 10:01:49.076675 0 10 12 | B1->B0 | 2f2f 3d3d | 1 1 | (0 0) (0 0)
4644 10:01:49.079810 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4645 10:01:49.083204 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4646 10:01:49.089525 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4647 10:01:49.093026 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4648 10:01:49.096113 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4649 10:01:49.103102 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4650 10:01:49.106109 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4651 10:01:49.109609 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4652 10:01:49.116125 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4653 10:01:49.119462 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 10:01:49.122896 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 10:01:49.126426 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 10:01:49.133075 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 10:01:49.136550 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 10:01:49.140171 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 10:01:49.146271 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 10:01:49.149873 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 10:01:49.153049 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 10:01:49.159903 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 10:01:49.163204 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 10:01:49.166652 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 10:01:49.173011 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 10:01:49.176352 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 10:01:49.179828 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 10:01:49.183234 Total UI for P1: 0, mck2ui 16
4669 10:01:49.186532 best dqsien dly found for B0: ( 0, 13, 10)
4670 10:01:49.189825 Total UI for P1: 0, mck2ui 16
4671 10:01:49.192937 best dqsien dly found for B1: ( 0, 13, 10)
4672 10:01:49.196251 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4673 10:01:49.199761 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4674 10:01:49.199889
4675 10:01:49.206216 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4676 10:01:49.209770 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4677 10:01:49.209873 [Gating] SW calibration Done
4678 10:01:49.213405 ==
4679 10:01:49.216190 Dram Type= 6, Freq= 0, CH_1, rank 1
4680 10:01:49.219768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4681 10:01:49.219869 ==
4682 10:01:49.219936 RX Vref Scan: 0
4683 10:01:49.219998
4684 10:01:49.222757 RX Vref 0 -> 0, step: 1
4685 10:01:49.222880
4686 10:01:49.226105 RX Delay -230 -> 252, step: 16
4687 10:01:49.229520 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4688 10:01:49.232928 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4689 10:01:49.239649 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4690 10:01:49.243157 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4691 10:01:49.246070 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4692 10:01:49.249534 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4693 10:01:49.253207 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4694 10:01:49.259996 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4695 10:01:49.263295 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4696 10:01:49.266175 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4697 10:01:49.269769 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4698 10:01:49.276253 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4699 10:01:49.279598 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4700 10:01:49.282799 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4701 10:01:49.286253 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4702 10:01:49.293019 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4703 10:01:49.293146 ==
4704 10:01:49.296268 Dram Type= 6, Freq= 0, CH_1, rank 1
4705 10:01:49.299655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4706 10:01:49.299760 ==
4707 10:01:49.299830 DQS Delay:
4708 10:01:49.303563 DQS0 = 0, DQS1 = 0
4709 10:01:49.303655 DQM Delay:
4710 10:01:49.306352 DQM0 = 43, DQM1 = 37
4711 10:01:49.306440 DQ Delay:
4712 10:01:49.309491 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4713 10:01:49.313117 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4714 10:01:49.315998 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4715 10:01:49.319526 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4716 10:01:49.319652
4717 10:01:49.319741
4718 10:01:49.319805 ==
4719 10:01:49.323183 Dram Type= 6, Freq= 0, CH_1, rank 1
4720 10:01:49.326223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4721 10:01:49.326318 ==
4722 10:01:49.326387
4723 10:01:49.326450
4724 10:01:49.329719 TX Vref Scan disable
4725 10:01:49.333195 == TX Byte 0 ==
4726 10:01:49.336401 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4727 10:01:49.339969 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4728 10:01:49.342786 == TX Byte 1 ==
4729 10:01:49.346540 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4730 10:01:49.350199 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4731 10:01:49.350322 ==
4732 10:01:49.353117 Dram Type= 6, Freq= 0, CH_1, rank 1
4733 10:01:49.359574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4734 10:01:49.359685 ==
4735 10:01:49.359780
4736 10:01:49.359881
4737 10:01:49.359981 TX Vref Scan disable
4738 10:01:49.363912 == TX Byte 0 ==
4739 10:01:49.366972 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4740 10:01:49.370552 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4741 10:01:49.373828 == TX Byte 1 ==
4742 10:01:49.377279 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4743 10:01:49.380202 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4744 10:01:49.383966
4745 10:01:49.384082 [DATLAT]
4746 10:01:49.384186 Freq=600, CH1 RK1
4747 10:01:49.384297
4748 10:01:49.387115 DATLAT Default: 0x9
4749 10:01:49.387231 0, 0xFFFF, sum = 0
4750 10:01:49.390904 1, 0xFFFF, sum = 0
4751 10:01:49.391026 2, 0xFFFF, sum = 0
4752 10:01:49.393898 3, 0xFFFF, sum = 0
4753 10:01:49.394013 4, 0xFFFF, sum = 0
4754 10:01:49.397201 5, 0xFFFF, sum = 0
4755 10:01:49.400625 6, 0xFFFF, sum = 0
4756 10:01:49.400744 7, 0xFFFF, sum = 0
4757 10:01:49.400850 8, 0x0, sum = 1
4758 10:01:49.403713 9, 0x0, sum = 2
4759 10:01:49.403829 10, 0x0, sum = 3
4760 10:01:49.407308 11, 0x0, sum = 4
4761 10:01:49.407423 best_step = 9
4762 10:01:49.407527
4763 10:01:49.407627 ==
4764 10:01:49.410228 Dram Type= 6, Freq= 0, CH_1, rank 1
4765 10:01:49.417116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4766 10:01:49.417265 ==
4767 10:01:49.417370 RX Vref Scan: 0
4768 10:01:49.417475
4769 10:01:49.420795 RX Vref 0 -> 0, step: 1
4770 10:01:49.420904
4771 10:01:49.423930 RX Delay -179 -> 252, step: 8
4772 10:01:49.427151 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4773 10:01:49.433653 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4774 10:01:49.437263 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4775 10:01:49.440585 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4776 10:01:49.443883 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4777 10:01:49.447177 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4778 10:01:49.454177 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4779 10:01:49.457649 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4780 10:01:49.460595 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4781 10:01:49.463942 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4782 10:01:49.467750 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4783 10:01:49.474160 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4784 10:01:49.477574 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4785 10:01:49.481139 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4786 10:01:49.484217 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4787 10:01:49.490922 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4788 10:01:49.491046 ==
4789 10:01:49.494155 Dram Type= 6, Freq= 0, CH_1, rank 1
4790 10:01:49.497486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4791 10:01:49.497581 ==
4792 10:01:49.497650 DQS Delay:
4793 10:01:49.500643 DQS0 = 0, DQS1 = 0
4794 10:01:49.500733 DQM Delay:
4795 10:01:49.504126 DQM0 = 39, DQM1 = 33
4796 10:01:49.504217 DQ Delay:
4797 10:01:49.507496 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4798 10:01:49.510599 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36
4799 10:01:49.514364 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4800 10:01:49.517692 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4801 10:01:49.517793
4802 10:01:49.517860
4803 10:01:49.523996 [DQSOSCAuto] RK1, (LSB)MR18= 0x3341, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
4804 10:01:49.527673 CH1 RK1: MR19=808, MR18=3341
4805 10:01:49.534089 CH1_RK1: MR19=0x808, MR18=0x3341, DQSOSC=397, MR23=63, INC=166, DEC=110
4806 10:01:49.537525 [RxdqsGatingPostProcess] freq 600
4807 10:01:49.543946 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4808 10:01:49.547572 Pre-setting of DQS Precalculation
4809 10:01:49.550667 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4810 10:01:49.557473 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4811 10:01:49.564047 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4812 10:01:49.564189
4813 10:01:49.564293
4814 10:01:49.567561 [Calibration Summary] 1200 Mbps
4815 10:01:49.570746 CH 0, Rank 0
4816 10:01:49.570834 SW Impedance : PASS
4817 10:01:49.574098 DUTY Scan : NO K
4818 10:01:49.577484 ZQ Calibration : PASS
4819 10:01:49.577577 Jitter Meter : NO K
4820 10:01:49.581326 CBT Training : PASS
4821 10:01:49.581418 Write leveling : PASS
4822 10:01:49.583997 RX DQS gating : PASS
4823 10:01:49.587575 RX DQ/DQS(RDDQC) : PASS
4824 10:01:49.587703 TX DQ/DQS : PASS
4825 10:01:49.590832 RX DATLAT : PASS
4826 10:01:49.594593 RX DQ/DQS(Engine): PASS
4827 10:01:49.594720 TX OE : NO K
4828 10:01:49.597933 All Pass.
4829 10:01:49.598048
4830 10:01:49.598128 CH 0, Rank 1
4831 10:01:49.600693 SW Impedance : PASS
4832 10:01:49.600798 DUTY Scan : NO K
4833 10:01:49.604027 ZQ Calibration : PASS
4834 10:01:49.607270 Jitter Meter : NO K
4835 10:01:49.607358 CBT Training : PASS
4836 10:01:49.611059 Write leveling : PASS
4837 10:01:49.614241 RX DQS gating : PASS
4838 10:01:49.614341 RX DQ/DQS(RDDQC) : PASS
4839 10:01:49.617474 TX DQ/DQS : PASS
4840 10:01:49.617562 RX DATLAT : PASS
4841 10:01:49.620624 RX DQ/DQS(Engine): PASS
4842 10:01:49.623948 TX OE : NO K
4843 10:01:49.624038 All Pass.
4844 10:01:49.624113
4845 10:01:49.624202 CH 1, Rank 0
4846 10:01:49.627262 SW Impedance : PASS
4847 10:01:49.630597 DUTY Scan : NO K
4848 10:01:49.630688 ZQ Calibration : PASS
4849 10:01:49.633903 Jitter Meter : NO K
4850 10:01:49.637318 CBT Training : PASS
4851 10:01:49.637408 Write leveling : PASS
4852 10:01:49.640815 RX DQS gating : PASS
4853 10:01:49.644145 RX DQ/DQS(RDDQC) : PASS
4854 10:01:49.644246 TX DQ/DQS : PASS
4855 10:01:49.647758 RX DATLAT : PASS
4856 10:01:49.650651 RX DQ/DQS(Engine): PASS
4857 10:01:49.650741 TX OE : NO K
4858 10:01:49.650809 All Pass.
4859 10:01:49.654461
4860 10:01:49.654549 CH 1, Rank 1
4861 10:01:49.657854 SW Impedance : PASS
4862 10:01:49.657943 DUTY Scan : NO K
4863 10:01:49.661314 ZQ Calibration : PASS
4864 10:01:49.661405 Jitter Meter : NO K
4865 10:01:49.664359 CBT Training : PASS
4866 10:01:49.667833 Write leveling : PASS
4867 10:01:49.667926 RX DQS gating : PASS
4868 10:01:49.670775 RX DQ/DQS(RDDQC) : PASS
4869 10:01:49.674231 TX DQ/DQS : PASS
4870 10:01:49.674323 RX DATLAT : PASS
4871 10:01:49.677591 RX DQ/DQS(Engine): PASS
4872 10:01:49.680804 TX OE : NO K
4873 10:01:49.680898 All Pass.
4874 10:01:49.680966
4875 10:01:49.684718 DramC Write-DBI off
4876 10:01:49.684817 PER_BANK_REFRESH: Hybrid Mode
4877 10:01:49.687561 TX_TRACKING: ON
4878 10:01:49.694171 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4879 10:01:49.697576 [FAST_K] Save calibration result to emmc
4880 10:01:49.705002 dramc_set_vcore_voltage set vcore to 662500
4881 10:01:49.705128 Read voltage for 933, 3
4882 10:01:49.707906 Vio18 = 0
4883 10:01:49.707997 Vcore = 662500
4884 10:01:49.708063 Vdram = 0
4885 10:01:49.708141 Vddq = 0
4886 10:01:49.710915 Vmddr = 0
4887 10:01:49.714590 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4888 10:01:49.721290 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4889 10:01:49.724611 MEM_TYPE=3, freq_sel=17
4890 10:01:49.724715 sv_algorithm_assistance_LP4_1600
4891 10:01:49.731110 ============ PULL DRAM RESETB DOWN ============
4892 10:01:49.734660 ========== PULL DRAM RESETB DOWN end =========
4893 10:01:49.737907 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4894 10:01:49.741314 ===================================
4895 10:01:49.745158 LPDDR4 DRAM CONFIGURATION
4896 10:01:49.747945 ===================================
4897 10:01:49.751015 EX_ROW_EN[0] = 0x0
4898 10:01:49.751118 EX_ROW_EN[1] = 0x0
4899 10:01:49.754280 LP4Y_EN = 0x0
4900 10:01:49.754383 WORK_FSP = 0x0
4901 10:01:49.757780 WL = 0x3
4902 10:01:49.757868 RL = 0x3
4903 10:01:49.761195 BL = 0x2
4904 10:01:49.761285 RPST = 0x0
4905 10:01:49.764413 RD_PRE = 0x0
4906 10:01:49.764501 WR_PRE = 0x1
4907 10:01:49.768071 WR_PST = 0x0
4908 10:01:49.768160 DBI_WR = 0x0
4909 10:01:49.771557 DBI_RD = 0x0
4910 10:01:49.771645 OTF = 0x1
4911 10:01:49.774458 ===================================
4912 10:01:49.777989 ===================================
4913 10:01:49.781331 ANA top config
4914 10:01:49.784500 ===================================
4915 10:01:49.784611 DLL_ASYNC_EN = 0
4916 10:01:49.788235 ALL_SLAVE_EN = 1
4917 10:01:49.791569 NEW_RANK_MODE = 1
4918 10:01:49.794533 DLL_IDLE_MODE = 1
4919 10:01:49.798028 LP45_APHY_COMB_EN = 1
4920 10:01:49.798125 TX_ODT_DIS = 1
4921 10:01:49.801339 NEW_8X_MODE = 1
4922 10:01:49.804725 ===================================
4923 10:01:49.807884 ===================================
4924 10:01:49.811261 data_rate = 1866
4925 10:01:49.814808 CKR = 1
4926 10:01:49.817763 DQ_P2S_RATIO = 8
4927 10:01:49.821154 ===================================
4928 10:01:49.821252 CA_P2S_RATIO = 8
4929 10:01:49.824321 DQ_CA_OPEN = 0
4930 10:01:49.827765 DQ_SEMI_OPEN = 0
4931 10:01:49.831033 CA_SEMI_OPEN = 0
4932 10:01:49.834557 CA_FULL_RATE = 0
4933 10:01:49.837758 DQ_CKDIV4_EN = 1
4934 10:01:49.837852 CA_CKDIV4_EN = 1
4935 10:01:49.841601 CA_PREDIV_EN = 0
4936 10:01:49.844939 PH8_DLY = 0
4937 10:01:49.847845 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4938 10:01:49.851817 DQ_AAMCK_DIV = 4
4939 10:01:49.854559 CA_AAMCK_DIV = 4
4940 10:01:49.854657 CA_ADMCK_DIV = 4
4941 10:01:49.858143 DQ_TRACK_CA_EN = 0
4942 10:01:49.861708 CA_PICK = 933
4943 10:01:49.864981 CA_MCKIO = 933
4944 10:01:49.867944 MCKIO_SEMI = 0
4945 10:01:49.871329 PLL_FREQ = 3732
4946 10:01:49.871427 DQ_UI_PI_RATIO = 32
4947 10:01:49.874769 CA_UI_PI_RATIO = 0
4948 10:01:49.877869 ===================================
4949 10:01:49.881716 ===================================
4950 10:01:49.884777 memory_type:LPDDR4
4951 10:01:49.888092 GP_NUM : 10
4952 10:01:49.888195 SRAM_EN : 1
4953 10:01:49.891266 MD32_EN : 0
4954 10:01:49.895189 ===================================
4955 10:01:49.898703 [ANA_INIT] >>>>>>>>>>>>>>
4956 10:01:49.898794 <<<<<< [CONFIGURE PHASE]: ANA_TX
4957 10:01:49.901260 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4958 10:01:49.904575 ===================================
4959 10:01:49.907800 data_rate = 1866,PCW = 0X8f00
4960 10:01:49.911147 ===================================
4961 10:01:49.914508 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4962 10:01:49.921362 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4963 10:01:49.928069 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4964 10:01:49.931307 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4965 10:01:49.934424 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4966 10:01:49.938133 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4967 10:01:49.941278 [ANA_INIT] flow start
4968 10:01:49.941368 [ANA_INIT] PLL >>>>>>>>
4969 10:01:49.944489 [ANA_INIT] PLL <<<<<<<<
4970 10:01:49.947929 [ANA_INIT] MIDPI >>>>>>>>
4971 10:01:49.950900 [ANA_INIT] MIDPI <<<<<<<<
4972 10:01:49.951003 [ANA_INIT] DLL >>>>>>>>
4973 10:01:49.954326 [ANA_INIT] flow end
4974 10:01:49.957926 ============ LP4 DIFF to SE enter ============
4975 10:01:49.961231 ============ LP4 DIFF to SE exit ============
4976 10:01:49.964292 [ANA_INIT] <<<<<<<<<<<<<
4977 10:01:49.967569 [Flow] Enable top DCM control >>>>>
4978 10:01:49.971113 [Flow] Enable top DCM control <<<<<
4979 10:01:49.974636 Enable DLL master slave shuffle
4980 10:01:49.981091 ==============================================================
4981 10:01:49.981231 Gating Mode config
4982 10:01:49.987594 ==============================================================
4983 10:01:49.987718 Config description:
4984 10:01:49.997648 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4985 10:01:50.004608 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4986 10:01:50.010612 SELPH_MODE 0: By rank 1: By Phase
4987 10:01:50.014000 ==============================================================
4988 10:01:50.017524 GAT_TRACK_EN = 1
4989 10:01:50.020778 RX_GATING_MODE = 2
4990 10:01:50.024493 RX_GATING_TRACK_MODE = 2
4991 10:01:50.027778 SELPH_MODE = 1
4992 10:01:50.030757 PICG_EARLY_EN = 1
4993 10:01:50.034088 VALID_LAT_VALUE = 1
4994 10:01:50.037407 ==============================================================
4995 10:01:50.040693 Enter into Gating configuration >>>>
4996 10:01:50.044544 Exit from Gating configuration <<<<
4997 10:01:50.047744 Enter into DVFS_PRE_config >>>>>
4998 10:01:50.060663 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4999 10:01:50.064144 Exit from DVFS_PRE_config <<<<<
5000 10:01:50.064241 Enter into PICG configuration >>>>
5001 10:01:50.067499 Exit from PICG configuration <<<<
5002 10:01:50.071148 [RX_INPUT] configuration >>>>>
5003 10:01:50.074539 [RX_INPUT] configuration <<<<<
5004 10:01:50.081079 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5005 10:01:50.084641 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5006 10:01:50.091257 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5007 10:01:50.097850 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5008 10:01:50.104459 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5009 10:01:50.111299 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5010 10:01:50.114398 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5011 10:01:50.117932 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5012 10:01:50.121200 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5013 10:01:50.128129 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5014 10:01:50.131018 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5015 10:01:50.134271 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5016 10:01:50.137790 ===================================
5017 10:01:50.141083 LPDDR4 DRAM CONFIGURATION
5018 10:01:50.144332 ===================================
5019 10:01:50.144430 EX_ROW_EN[0] = 0x0
5020 10:01:50.147775 EX_ROW_EN[1] = 0x0
5021 10:01:50.147865 LP4Y_EN = 0x0
5022 10:01:50.150910 WORK_FSP = 0x0
5023 10:01:50.154308 WL = 0x3
5024 10:01:50.154392 RL = 0x3
5025 10:01:50.157696 BL = 0x2
5026 10:01:50.157783 RPST = 0x0
5027 10:01:50.160933 RD_PRE = 0x0
5028 10:01:50.161019 WR_PRE = 0x1
5029 10:01:50.164450 WR_PST = 0x0
5030 10:01:50.164532 DBI_WR = 0x0
5031 10:01:50.167688 DBI_RD = 0x0
5032 10:01:50.167776 OTF = 0x1
5033 10:01:50.171053 ===================================
5034 10:01:50.174455 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5035 10:01:50.181206 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5036 10:01:50.184693 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5037 10:01:50.187757 ===================================
5038 10:01:50.191275 LPDDR4 DRAM CONFIGURATION
5039 10:01:50.194731 ===================================
5040 10:01:50.194826 EX_ROW_EN[0] = 0x10
5041 10:01:50.197850 EX_ROW_EN[1] = 0x0
5042 10:01:50.197941 LP4Y_EN = 0x0
5043 10:01:50.201370 WORK_FSP = 0x0
5044 10:01:50.201461 WL = 0x3
5045 10:01:50.204779 RL = 0x3
5046 10:01:50.204870 BL = 0x2
5047 10:01:50.207776 RPST = 0x0
5048 10:01:50.207866 RD_PRE = 0x0
5049 10:01:50.211174 WR_PRE = 0x1
5050 10:01:50.211262 WR_PST = 0x0
5051 10:01:50.214604 DBI_WR = 0x0
5052 10:01:50.214694 DBI_RD = 0x0
5053 10:01:50.217524 OTF = 0x1
5054 10:01:50.221254 ===================================
5055 10:01:50.227891 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5056 10:01:50.231130 nWR fixed to 30
5057 10:01:50.234292 [ModeRegInit_LP4] CH0 RK0
5058 10:01:50.234388 [ModeRegInit_LP4] CH0 RK1
5059 10:01:50.237838 [ModeRegInit_LP4] CH1 RK0
5060 10:01:50.241126 [ModeRegInit_LP4] CH1 RK1
5061 10:01:50.241222 match AC timing 9
5062 10:01:50.247600 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5063 10:01:50.251156 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5064 10:01:50.254708 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5065 10:01:50.261736 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5066 10:01:50.265133 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5067 10:01:50.265247 ==
5068 10:01:50.268076 Dram Type= 6, Freq= 0, CH_0, rank 0
5069 10:01:50.271081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5070 10:01:50.271182 ==
5071 10:01:50.278236 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5072 10:01:50.284438 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5073 10:01:50.288000 [CA 0] Center 38 (8~69) winsize 62
5074 10:01:50.291452 [CA 1] Center 38 (7~69) winsize 63
5075 10:01:50.294333 [CA 2] Center 35 (5~66) winsize 62
5076 10:01:50.297893 [CA 3] Center 35 (5~65) winsize 61
5077 10:01:50.301330 [CA 4] Center 34 (4~64) winsize 61
5078 10:01:50.304885 [CA 5] Center 34 (4~64) winsize 61
5079 10:01:50.305012
5080 10:01:50.307989 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5081 10:01:50.308115
5082 10:01:50.310994 [CATrainingPosCal] consider 1 rank data
5083 10:01:50.314318 u2DelayCellTimex100 = 270/100 ps
5084 10:01:50.317722 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5085 10:01:50.321001 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5086 10:01:50.324350 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5087 10:01:50.327769 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5088 10:01:50.331430 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5089 10:01:50.334334 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5090 10:01:50.334449
5091 10:01:50.340943 CA PerBit enable=1, Macro0, CA PI delay=34
5092 10:01:50.341053
5093 10:01:50.341153 [CBTSetCACLKResult] CA Dly = 34
5094 10:01:50.344320 CS Dly: 6 (0~37)
5095 10:01:50.344437 ==
5096 10:01:50.347727 Dram Type= 6, Freq= 0, CH_0, rank 1
5097 10:01:50.350974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5098 10:01:50.351108 ==
5099 10:01:50.357665 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5100 10:01:50.364445 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5101 10:01:50.368227 [CA 0] Center 38 (7~69) winsize 63
5102 10:01:50.371296 [CA 1] Center 38 (7~69) winsize 63
5103 10:01:50.374587 [CA 2] Center 35 (5~66) winsize 62
5104 10:01:50.378015 [CA 3] Center 35 (5~66) winsize 62
5105 10:01:50.381284 [CA 4] Center 33 (3~64) winsize 62
5106 10:01:50.384458 [CA 5] Center 33 (3~64) winsize 62
5107 10:01:50.384592
5108 10:01:50.388271 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5109 10:01:50.388394
5110 10:01:50.391439 [CATrainingPosCal] consider 2 rank data
5111 10:01:50.394640 u2DelayCellTimex100 = 270/100 ps
5112 10:01:50.398203 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5113 10:01:50.401551 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5114 10:01:50.404486 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5115 10:01:50.407929 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5116 10:01:50.411600 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5117 10:01:50.414431 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5118 10:01:50.414541
5119 10:01:50.417995 CA PerBit enable=1, Macro0, CA PI delay=34
5120 10:01:50.421664
5121 10:01:50.421785 [CBTSetCACLKResult] CA Dly = 34
5122 10:01:50.424831 CS Dly: 7 (0~39)
5123 10:01:50.424944
5124 10:01:50.427579 ----->DramcWriteLeveling(PI) begin...
5125 10:01:50.427691 ==
5126 10:01:50.431550 Dram Type= 6, Freq= 0, CH_0, rank 0
5127 10:01:50.434471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5128 10:01:50.434590 ==
5129 10:01:50.438073 Write leveling (Byte 0): 27 => 27
5130 10:01:50.441482 Write leveling (Byte 1): 26 => 26
5131 10:01:50.444720 DramcWriteLeveling(PI) end<-----
5132 10:01:50.444822
5133 10:01:50.444893 ==
5134 10:01:50.447757 Dram Type= 6, Freq= 0, CH_0, rank 0
5135 10:01:50.451169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5136 10:01:50.451261 ==
5137 10:01:50.454655 [Gating] SW mode calibration
5138 10:01:50.461508 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5139 10:01:50.467953 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5140 10:01:50.471267 0 14 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5141 10:01:50.478156 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5142 10:01:50.481093 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5143 10:01:50.484603 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5144 10:01:50.487976 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5145 10:01:50.494987 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5146 10:01:50.498100 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5147 10:01:50.501567 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5148 10:01:50.508037 0 15 0 | B1->B0 | 3030 2e2e | 0 0 | (1 0) (0 1)
5149 10:01:50.511301 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
5150 10:01:50.514706 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5151 10:01:50.521362 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5152 10:01:50.524778 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5153 10:01:50.528318 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5154 10:01:50.534477 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5155 10:01:50.537965 0 15 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
5156 10:01:50.541466 1 0 0 | B1->B0 | 3131 4141 | 1 0 | (0 0) (0 0)
5157 10:01:50.548205 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5158 10:01:50.551459 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5159 10:01:50.554580 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5160 10:01:50.561369 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5161 10:01:50.564889 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 10:01:50.567827 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5163 10:01:50.574459 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5164 10:01:50.577916 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5165 10:01:50.581267 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5166 10:01:50.584912 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 10:01:50.591488 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 10:01:50.594953 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 10:01:50.598154 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 10:01:50.604681 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 10:01:50.607925 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 10:01:50.611504 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 10:01:50.618065 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 10:01:50.621402 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 10:01:50.624753 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 10:01:50.631419 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 10:01:50.635083 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 10:01:50.638360 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 10:01:50.644763 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 10:01:50.648146 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5181 10:01:50.651169 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 10:01:50.654761 Total UI for P1: 0, mck2ui 16
5183 10:01:50.658091 best dqsien dly found for B0: ( 1, 3, 0)
5184 10:01:50.661589 Total UI for P1: 0, mck2ui 16
5185 10:01:50.664863 best dqsien dly found for B1: ( 1, 3, 0)
5186 10:01:50.667974 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5187 10:01:50.671419 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5188 10:01:50.671536
5189 10:01:50.674712 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5190 10:01:50.678113 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5191 10:01:50.681147 [Gating] SW calibration Done
5192 10:01:50.681265 ==
5193 10:01:50.684759 Dram Type= 6, Freq= 0, CH_0, rank 0
5194 10:01:50.691175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5195 10:01:50.691312 ==
5196 10:01:50.691415 RX Vref Scan: 0
5197 10:01:50.691514
5198 10:01:50.694506 RX Vref 0 -> 0, step: 1
5199 10:01:50.694616
5200 10:01:50.698096 RX Delay -80 -> 252, step: 8
5201 10:01:50.701397 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5202 10:01:50.704973 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5203 10:01:50.707784 iDelay=200, Bit 2, Center 91 (-8 ~ 191) 200
5204 10:01:50.711574 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5205 10:01:50.714624 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5206 10:01:50.721532 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5207 10:01:50.724771 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5208 10:01:50.727722 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5209 10:01:50.731174 iDelay=200, Bit 8, Center 75 (-16 ~ 167) 184
5210 10:01:50.734568 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5211 10:01:50.738141 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5212 10:01:50.744881 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5213 10:01:50.747964 iDelay=200, Bit 12, Center 87 (-8 ~ 183) 192
5214 10:01:50.751312 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5215 10:01:50.754676 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5216 10:01:50.758466 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5217 10:01:50.758596 ==
5218 10:01:50.761211 Dram Type= 6, Freq= 0, CH_0, rank 0
5219 10:01:50.768328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5220 10:01:50.768464 ==
5221 10:01:50.768579 DQS Delay:
5222 10:01:50.771347 DQS0 = 0, DQS1 = 0
5223 10:01:50.771462 DQM Delay:
5224 10:01:50.771558 DQM0 = 96, DQM1 = 86
5225 10:01:50.774759 DQ Delay:
5226 10:01:50.778240 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =95
5227 10:01:50.781457 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5228 10:01:50.784827 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5229 10:01:50.788189 DQ12 =87, DQ13 =95, DQ14 =95, DQ15 =95
5230 10:01:50.788317
5231 10:01:50.788418
5232 10:01:50.788510 ==
5233 10:01:50.791555 Dram Type= 6, Freq= 0, CH_0, rank 0
5234 10:01:50.794651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5235 10:01:50.794766 ==
5236 10:01:50.794877
5237 10:01:50.794970
5238 10:01:50.798085 TX Vref Scan disable
5239 10:01:50.798199 == TX Byte 0 ==
5240 10:01:50.805029 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5241 10:01:50.808425 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5242 10:01:50.808548 == TX Byte 1 ==
5243 10:01:50.814659 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5244 10:01:50.818178 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5245 10:01:50.818297 ==
5246 10:01:50.821554 Dram Type= 6, Freq= 0, CH_0, rank 0
5247 10:01:50.825207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5248 10:01:50.825324 ==
5249 10:01:50.825420
5250 10:01:50.825508
5251 10:01:50.828385 TX Vref Scan disable
5252 10:01:50.831645 == TX Byte 0 ==
5253 10:01:50.834939 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5254 10:01:50.838282 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5255 10:01:50.841788 == TX Byte 1 ==
5256 10:01:50.844987 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5257 10:01:50.848285 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5258 10:01:50.848389
5259 10:01:50.851687 [DATLAT]
5260 10:01:50.851804 Freq=933, CH0 RK0
5261 10:01:50.851903
5262 10:01:50.855264 DATLAT Default: 0xd
5263 10:01:50.855366 0, 0xFFFF, sum = 0
5264 10:01:50.858654 1, 0xFFFF, sum = 0
5265 10:01:50.858761 2, 0xFFFF, sum = 0
5266 10:01:50.861657 3, 0xFFFF, sum = 0
5267 10:01:50.861745 4, 0xFFFF, sum = 0
5268 10:01:50.865047 5, 0xFFFF, sum = 0
5269 10:01:50.865153 6, 0xFFFF, sum = 0
5270 10:01:50.868351 7, 0xFFFF, sum = 0
5271 10:01:50.868461 8, 0xFFFF, sum = 0
5272 10:01:50.871555 9, 0xFFFF, sum = 0
5273 10:01:50.871670 10, 0x0, sum = 1
5274 10:01:50.875405 11, 0x0, sum = 2
5275 10:01:50.875529 12, 0x0, sum = 3
5276 10:01:50.878400 13, 0x0, sum = 4
5277 10:01:50.878516 best_step = 11
5278 10:01:50.878618
5279 10:01:50.878718 ==
5280 10:01:50.882584 Dram Type= 6, Freq= 0, CH_0, rank 0
5281 10:01:50.888340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5282 10:01:50.888485 ==
5283 10:01:50.888587 RX Vref Scan: 1
5284 10:01:50.888679
5285 10:01:50.892180 RX Vref 0 -> 0, step: 1
5286 10:01:50.892298
5287 10:01:50.895142 RX Delay -61 -> 252, step: 4
5288 10:01:50.895253
5289 10:01:50.898455 Set Vref, RX VrefLevel [Byte0]: 53
5290 10:01:50.902005 [Byte1]: 51
5291 10:01:50.902110
5292 10:01:50.905222 Final RX Vref Byte 0 = 53 to rank0
5293 10:01:50.908646 Final RX Vref Byte 1 = 51 to rank0
5294 10:01:50.911689 Final RX Vref Byte 0 = 53 to rank1
5295 10:01:50.915151 Final RX Vref Byte 1 = 51 to rank1==
5296 10:01:50.918471 Dram Type= 6, Freq= 0, CH_0, rank 0
5297 10:01:50.921944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5298 10:01:50.922065 ==
5299 10:01:50.925240 DQS Delay:
5300 10:01:50.925350 DQS0 = 0, DQS1 = 0
5301 10:01:50.925443 DQM Delay:
5302 10:01:50.928252 DQM0 = 96, DQM1 = 88
5303 10:01:50.928367 DQ Delay:
5304 10:01:50.932055 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =94
5305 10:01:50.935106 DQ4 =98, DQ5 =86, DQ6 =104, DQ7 =102
5306 10:01:50.938348 DQ8 =78, DQ9 =76, DQ10 =88, DQ11 =82
5307 10:01:50.942053 DQ12 =96, DQ13 =94, DQ14 =98, DQ15 =98
5308 10:01:50.942170
5309 10:01:50.942266
5310 10:01:50.951537 [DQSOSCAuto] RK0, (LSB)MR18= 0x13ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 415 ps
5311 10:01:50.951655 CH0 RK0: MR19=504, MR18=13FF
5312 10:01:50.958347 CH0_RK0: MR19=0x504, MR18=0x13FF, DQSOSC=415, MR23=63, INC=62, DEC=41
5313 10:01:50.958480
5314 10:01:50.962022 ----->DramcWriteLeveling(PI) begin...
5315 10:01:50.962143 ==
5316 10:01:50.965616 Dram Type= 6, Freq= 0, CH_0, rank 1
5317 10:01:50.971852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5318 10:01:50.971965 ==
5319 10:01:50.975495 Write leveling (Byte 0): 29 => 29
5320 10:01:50.978767 Write leveling (Byte 1): 28 => 28
5321 10:01:50.978858 DramcWriteLeveling(PI) end<-----
5322 10:01:50.978937
5323 10:01:50.981733 ==
5324 10:01:50.985543 Dram Type= 6, Freq= 0, CH_0, rank 1
5325 10:01:50.988840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5326 10:01:50.988935 ==
5327 10:01:50.992134 [Gating] SW mode calibration
5328 10:01:50.998439 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5329 10:01:51.001808 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5330 10:01:51.008467 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5331 10:01:51.012073 0 14 4 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
5332 10:01:51.015175 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5333 10:01:51.022078 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5334 10:01:51.025344 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5335 10:01:51.028876 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5336 10:01:51.035249 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5337 10:01:51.038588 0 14 28 | B1->B0 | 3131 2e2e | 0 1 | (0 0) (1 0)
5338 10:01:51.042232 0 15 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
5339 10:01:51.045611 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5340 10:01:51.052314 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5341 10:01:51.055758 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5342 10:01:51.058645 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5343 10:01:51.065766 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5344 10:01:51.069151 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5345 10:01:51.072047 0 15 28 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
5346 10:01:51.078850 1 0 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
5347 10:01:51.082152 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5348 10:01:51.085496 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 10:01:51.092335 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5350 10:01:51.095348 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5351 10:01:51.098721 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5352 10:01:51.105351 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5353 10:01:51.108822 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5354 10:01:51.111918 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5355 10:01:51.118619 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 10:01:51.121994 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 10:01:51.125353 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 10:01:51.131787 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 10:01:51.135366 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 10:01:51.138929 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 10:01:51.141772 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 10:01:51.148563 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 10:01:51.151744 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 10:01:51.155331 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 10:01:51.162214 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 10:01:51.165282 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 10:01:51.168920 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 10:01:51.175180 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 10:01:51.178774 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5370 10:01:51.182150 Total UI for P1: 0, mck2ui 16
5371 10:01:51.185612 best dqsien dly found for B0: ( 1, 2, 26)
5372 10:01:51.189065 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5373 10:01:51.195390 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5374 10:01:51.198582 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 10:01:51.202091 Total UI for P1: 0, mck2ui 16
5376 10:01:51.205319 best dqsien dly found for B1: ( 1, 3, 2)
5377 10:01:51.209355 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5378 10:01:51.211902 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5379 10:01:51.212009
5380 10:01:51.215749 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5381 10:01:51.218854 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5382 10:01:51.222214 [Gating] SW calibration Done
5383 10:01:51.222367 ==
5384 10:01:51.225589 Dram Type= 6, Freq= 0, CH_0, rank 1
5385 10:01:51.228664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5386 10:01:51.228771 ==
5387 10:01:51.232519 RX Vref Scan: 0
5388 10:01:51.232627
5389 10:01:51.232723 RX Vref 0 -> 0, step: 1
5390 10:01:51.235794
5391 10:01:51.235895 RX Delay -80 -> 252, step: 8
5392 10:01:51.239066 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5393 10:01:51.245945 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5394 10:01:51.249146 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5395 10:01:51.252690 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5396 10:01:51.255983 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5397 10:01:51.258797 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5398 10:01:51.262212 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5399 10:01:51.269051 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5400 10:01:51.272090 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5401 10:01:51.275665 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5402 10:01:51.278958 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5403 10:01:51.282474 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5404 10:01:51.286000 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5405 10:01:51.292208 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5406 10:01:51.295773 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5407 10:01:51.299252 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5408 10:01:51.299355 ==
5409 10:01:51.302286 Dram Type= 6, Freq= 0, CH_0, rank 1
5410 10:01:51.305746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5411 10:01:51.305839 ==
5412 10:01:51.309086 DQS Delay:
5413 10:01:51.309185 DQS0 = 0, DQS1 = 0
5414 10:01:51.312337 DQM Delay:
5415 10:01:51.312417 DQM0 = 97, DQM1 = 86
5416 10:01:51.312481 DQ Delay:
5417 10:01:51.315376 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5418 10:01:51.318749 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =103
5419 10:01:51.322627 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =75
5420 10:01:51.325520 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5421 10:01:51.325605
5422 10:01:51.325671
5423 10:01:51.328800 ==
5424 10:01:51.332129 Dram Type= 6, Freq= 0, CH_0, rank 1
5425 10:01:51.335377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5426 10:01:51.335486 ==
5427 10:01:51.335556
5428 10:01:51.335618
5429 10:01:51.338716 TX Vref Scan disable
5430 10:01:51.338838 == TX Byte 0 ==
5431 10:01:51.341742 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5432 10:01:51.349018 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5433 10:01:51.349153 == TX Byte 1 ==
5434 10:01:51.351832 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5435 10:01:51.358545 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5436 10:01:51.358680 ==
5437 10:01:51.361800 Dram Type= 6, Freq= 0, CH_0, rank 1
5438 10:01:51.365243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5439 10:01:51.365343 ==
5440 10:01:51.365411
5441 10:01:51.365473
5442 10:01:51.368584 TX Vref Scan disable
5443 10:01:51.372068 == TX Byte 0 ==
5444 10:01:51.375465 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5445 10:01:51.378450 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5446 10:01:51.382042 == TX Byte 1 ==
5447 10:01:51.385568 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5448 10:01:51.388348 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5449 10:01:51.388456
5450 10:01:51.388529 [DATLAT]
5451 10:01:51.392267 Freq=933, CH0 RK1
5452 10:01:51.392375
5453 10:01:51.395558 DATLAT Default: 0xb
5454 10:01:51.395664 0, 0xFFFF, sum = 0
5455 10:01:51.398688 1, 0xFFFF, sum = 0
5456 10:01:51.398790 2, 0xFFFF, sum = 0
5457 10:01:51.402070 3, 0xFFFF, sum = 0
5458 10:01:51.402146 4, 0xFFFF, sum = 0
5459 10:01:51.404998 5, 0xFFFF, sum = 0
5460 10:01:51.405076 6, 0xFFFF, sum = 0
5461 10:01:51.408424 7, 0xFFFF, sum = 0
5462 10:01:51.408498 8, 0xFFFF, sum = 0
5463 10:01:51.411763 9, 0xFFFF, sum = 0
5464 10:01:51.411882 10, 0x0, sum = 1
5465 10:01:51.415300 11, 0x0, sum = 2
5466 10:01:51.415417 12, 0x0, sum = 3
5467 10:01:51.418315 13, 0x0, sum = 4
5468 10:01:51.418402 best_step = 11
5469 10:01:51.418470
5470 10:01:51.418532 ==
5471 10:01:51.421700 Dram Type= 6, Freq= 0, CH_0, rank 1
5472 10:01:51.425256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5473 10:01:51.425374 ==
5474 10:01:51.428627 RX Vref Scan: 0
5475 10:01:51.428714
5476 10:01:51.431949 RX Vref 0 -> 0, step: 1
5477 10:01:51.432038
5478 10:01:51.432106 RX Delay -61 -> 252, step: 4
5479 10:01:51.439616 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5480 10:01:51.443417 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5481 10:01:51.446289 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5482 10:01:51.449930 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5483 10:01:51.453150 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5484 10:01:51.456491 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5485 10:01:51.462968 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5486 10:01:51.466600 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5487 10:01:51.469811 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5488 10:01:51.473126 iDelay=199, Bit 9, Center 78 (-9 ~ 166) 176
5489 10:01:51.476672 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5490 10:01:51.480119 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5491 10:01:51.486652 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5492 10:01:51.490027 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5493 10:01:51.493601 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5494 10:01:51.496470 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5495 10:01:51.496564 ==
5496 10:01:51.500218 Dram Type= 6, Freq= 0, CH_0, rank 1
5497 10:01:51.503549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5498 10:01:51.506638 ==
5499 10:01:51.506727 DQS Delay:
5500 10:01:51.506823 DQS0 = 0, DQS1 = 0
5501 10:01:51.510261 DQM Delay:
5502 10:01:51.510349 DQM0 = 95, DQM1 = 87
5503 10:01:51.510417 DQ Delay:
5504 10:01:51.513583 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5505 10:01:51.516468 DQ4 =94, DQ5 =84, DQ6 =104, DQ7 =102
5506 10:01:51.520551 DQ8 =80, DQ9 =78, DQ10 =88, DQ11 =80
5507 10:01:51.523614 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =94
5508 10:01:51.523711
5509 10:01:51.526642
5510 10:01:51.533509 [DQSOSCAuto] RK1, (LSB)MR18= 0x1906, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 413 ps
5511 10:01:51.536724 CH0 RK1: MR19=505, MR18=1906
5512 10:01:51.543269 CH0_RK1: MR19=0x505, MR18=0x1906, DQSOSC=413, MR23=63, INC=63, DEC=42
5513 10:01:51.543384 [RxdqsGatingPostProcess] freq 933
5514 10:01:51.550237 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5515 10:01:51.553332 best DQS0 dly(2T, 0.5T) = (0, 11)
5516 10:01:51.556682 best DQS1 dly(2T, 0.5T) = (0, 11)
5517 10:01:51.559927 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5518 10:01:51.563720 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5519 10:01:51.567002 best DQS0 dly(2T, 0.5T) = (0, 10)
5520 10:01:51.570353 best DQS1 dly(2T, 0.5T) = (0, 11)
5521 10:01:51.574147 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5522 10:01:51.576846 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5523 10:01:51.580114 Pre-setting of DQS Precalculation
5524 10:01:51.583662 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5525 10:01:51.583757 ==
5526 10:01:51.587166 Dram Type= 6, Freq= 0, CH_1, rank 0
5527 10:01:51.590543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5528 10:01:51.590662 ==
5529 10:01:51.596958 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5530 10:01:51.603406 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5531 10:01:51.606824 [CA 0] Center 36 (6~67) winsize 62
5532 10:01:51.610368 [CA 1] Center 36 (6~67) winsize 62
5533 10:01:51.613929 [CA 2] Center 34 (4~64) winsize 61
5534 10:01:51.616918 [CA 3] Center 33 (3~64) winsize 62
5535 10:01:51.620358 [CA 4] Center 34 (4~64) winsize 61
5536 10:01:51.623612 [CA 5] Center 33 (3~64) winsize 62
5537 10:01:51.623702
5538 10:01:51.626878 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5539 10:01:51.626995
5540 10:01:51.630803 [CATrainingPosCal] consider 1 rank data
5541 10:01:51.633711 u2DelayCellTimex100 = 270/100 ps
5542 10:01:51.637246 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5543 10:01:51.640862 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5544 10:01:51.643643 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5545 10:01:51.647063 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5546 10:01:51.650838 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5547 10:01:51.654196 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5548 10:01:51.654286
5549 10:01:51.660627 CA PerBit enable=1, Macro0, CA PI delay=33
5550 10:01:51.660729
5551 10:01:51.660796 [CBTSetCACLKResult] CA Dly = 33
5552 10:01:51.663837 CS Dly: 4 (0~35)
5553 10:01:51.663923 ==
5554 10:01:51.666929 Dram Type= 6, Freq= 0, CH_1, rank 1
5555 10:01:51.670187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5556 10:01:51.670275 ==
5557 10:01:51.677500 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5558 10:01:51.684144 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5559 10:01:51.686939 [CA 0] Center 36 (6~67) winsize 62
5560 10:01:51.690515 [CA 1] Center 37 (7~67) winsize 61
5561 10:01:51.693439 [CA 2] Center 33 (3~64) winsize 62
5562 10:01:51.696923 [CA 3] Center 33 (3~64) winsize 62
5563 10:01:51.700719 [CA 4] Center 34 (3~65) winsize 63
5564 10:01:51.703889 [CA 5] Center 33 (2~64) winsize 63
5565 10:01:51.703996
5566 10:01:51.707302 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5567 10:01:51.707386
5568 10:01:51.710575 [CATrainingPosCal] consider 2 rank data
5569 10:01:51.714186 u2DelayCellTimex100 = 270/100 ps
5570 10:01:51.717087 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5571 10:01:51.720891 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5572 10:01:51.724114 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5573 10:01:51.727259 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5574 10:01:51.730442 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5575 10:01:51.734134 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5576 10:01:51.734263
5577 10:01:51.737060 CA PerBit enable=1, Macro0, CA PI delay=33
5578 10:01:51.740503
5579 10:01:51.740634 [CBTSetCACLKResult] CA Dly = 33
5580 10:01:51.743821 CS Dly: 5 (0~37)
5581 10:01:51.743948
5582 10:01:51.747452 ----->DramcWriteLeveling(PI) begin...
5583 10:01:51.747575 ==
5584 10:01:51.750918 Dram Type= 6, Freq= 0, CH_1, rank 0
5585 10:01:51.754245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5586 10:01:51.754366 ==
5587 10:01:51.757467 Write leveling (Byte 0): 29 => 29
5588 10:01:51.760561 Write leveling (Byte 1): 30 => 30
5589 10:01:51.764314 DramcWriteLeveling(PI) end<-----
5590 10:01:51.764430
5591 10:01:51.764523 ==
5592 10:01:51.767243 Dram Type= 6, Freq= 0, CH_1, rank 0
5593 10:01:51.770619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5594 10:01:51.770723 ==
5595 10:01:51.774302 [Gating] SW mode calibration
5596 10:01:51.780565 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5597 10:01:51.787911 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5598 10:01:51.790893 0 14 0 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
5599 10:01:51.797620 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5600 10:01:51.800778 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5601 10:01:51.804105 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5602 10:01:51.807654 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5603 10:01:51.814234 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5604 10:01:51.817219 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5605 10:01:51.820831 0 14 28 | B1->B0 | 2f2f 3030 | 1 1 | (1 0) (1 0)
5606 10:01:51.827243 0 15 0 | B1->B0 | 2727 2c2c | 0 0 | (0 0) (1 1)
5607 10:01:51.830664 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5608 10:01:51.834234 0 15 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5609 10:01:51.840442 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5610 10:01:51.844048 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5611 10:01:51.847308 0 15 20 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
5612 10:01:51.853854 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5613 10:01:51.857364 0 15 28 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (1 1)
5614 10:01:51.860685 1 0 0 | B1->B0 | 4444 4242 | 0 0 | (0 0) (0 0)
5615 10:01:51.867251 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 10:01:51.870553 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5617 10:01:51.873909 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5618 10:01:51.880454 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 10:01:51.883918 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5620 10:01:51.887477 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 10:01:51.894135 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5622 10:01:51.897100 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 10:01:51.900557 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 10:01:51.903894 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 10:01:51.910615 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 10:01:51.914224 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 10:01:51.917466 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 10:01:51.924180 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 10:01:51.927054 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 10:01:51.930674 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 10:01:51.937077 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 10:01:51.940928 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 10:01:51.944102 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 10:01:51.950939 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 10:01:51.953702 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 10:01:51.957473 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 10:01:51.964096 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5638 10:01:51.967183 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 10:01:51.970662 Total UI for P1: 0, mck2ui 16
5640 10:01:51.974377 best dqsien dly found for B0: ( 1, 2, 28)
5641 10:01:51.977278 Total UI for P1: 0, mck2ui 16
5642 10:01:51.980519 best dqsien dly found for B1: ( 1, 2, 30)
5643 10:01:51.984304 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5644 10:01:51.987263 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5645 10:01:51.987394
5646 10:01:51.990784 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5647 10:01:51.994183 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5648 10:01:51.997741 [Gating] SW calibration Done
5649 10:01:51.997859 ==
5650 10:01:52.000927 Dram Type= 6, Freq= 0, CH_1, rank 0
5651 10:01:52.003954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5652 10:01:52.004077 ==
5653 10:01:52.007302 RX Vref Scan: 0
5654 10:01:52.007411
5655 10:01:52.010776 RX Vref 0 -> 0, step: 1
5656 10:01:52.010918
5657 10:01:52.010993 RX Delay -80 -> 252, step: 8
5658 10:01:52.017360 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5659 10:01:52.020473 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5660 10:01:52.024229 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5661 10:01:52.027488 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5662 10:01:52.030476 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5663 10:01:52.034024 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5664 10:01:52.040969 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5665 10:01:52.043808 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5666 10:01:52.047092 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5667 10:01:52.051128 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5668 10:01:52.054132 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5669 10:01:52.057527 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5670 10:01:52.064239 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5671 10:01:52.067059 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5672 10:01:52.070496 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5673 10:01:52.073955 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5674 10:01:52.074075 ==
5675 10:01:52.077517 Dram Type= 6, Freq= 0, CH_1, rank 0
5676 10:01:52.080578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5677 10:01:52.084157 ==
5678 10:01:52.084272 DQS Delay:
5679 10:01:52.084370 DQS0 = 0, DQS1 = 0
5680 10:01:52.087562 DQM Delay:
5681 10:01:52.087694 DQM0 = 95, DQM1 = 89
5682 10:01:52.090669 DQ Delay:
5683 10:01:52.090794 DQ0 =99, DQ1 =87, DQ2 =83, DQ3 =95
5684 10:01:52.094175 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =91
5685 10:01:52.097501 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =87
5686 10:01:52.100488 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5687 10:01:52.104159
5688 10:01:52.104284
5689 10:01:52.104380 ==
5690 10:01:52.107644 Dram Type= 6, Freq= 0, CH_1, rank 0
5691 10:01:52.111058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5692 10:01:52.111149 ==
5693 10:01:52.111230
5694 10:01:52.111293
5695 10:01:52.113838 TX Vref Scan disable
5696 10:01:52.113959 == TX Byte 0 ==
5697 10:01:52.120777 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5698 10:01:52.124168 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5699 10:01:52.124297 == TX Byte 1 ==
5700 10:01:52.130466 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5701 10:01:52.133715 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5702 10:01:52.133845 ==
5703 10:01:52.137237 Dram Type= 6, Freq= 0, CH_1, rank 0
5704 10:01:52.140773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5705 10:01:52.140902 ==
5706 10:01:52.141005
5707 10:01:52.141098
5708 10:01:52.144117 TX Vref Scan disable
5709 10:01:52.147403 == TX Byte 0 ==
5710 10:01:52.151068 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5711 10:01:52.154188 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5712 10:01:52.157472 == TX Byte 1 ==
5713 10:01:52.160859 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5714 10:01:52.163857 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5715 10:01:52.163947
5716 10:01:52.167318 [DATLAT]
5717 10:01:52.167442 Freq=933, CH1 RK0
5718 10:01:52.167541
5719 10:01:52.170736 DATLAT Default: 0xd
5720 10:01:52.170855 0, 0xFFFF, sum = 0
5721 10:01:52.174226 1, 0xFFFF, sum = 0
5722 10:01:52.174355 2, 0xFFFF, sum = 0
5723 10:01:52.177179 3, 0xFFFF, sum = 0
5724 10:01:52.177292 4, 0xFFFF, sum = 0
5725 10:01:52.180571 5, 0xFFFF, sum = 0
5726 10:01:52.180685 6, 0xFFFF, sum = 0
5727 10:01:52.183967 7, 0xFFFF, sum = 0
5728 10:01:52.184081 8, 0xFFFF, sum = 0
5729 10:01:52.187549 9, 0xFFFF, sum = 0
5730 10:01:52.187688 10, 0x0, sum = 1
5731 10:01:52.190506 11, 0x0, sum = 2
5732 10:01:52.190651 12, 0x0, sum = 3
5733 10:01:52.194055 13, 0x0, sum = 4
5734 10:01:52.194144 best_step = 11
5735 10:01:52.194210
5736 10:01:52.194271 ==
5737 10:01:52.197657 Dram Type= 6, Freq= 0, CH_1, rank 0
5738 10:01:52.200705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5739 10:01:52.204259 ==
5740 10:01:52.204372 RX Vref Scan: 1
5741 10:01:52.204467
5742 10:01:52.207572 RX Vref 0 -> 0, step: 1
5743 10:01:52.207676
5744 10:01:52.207769 RX Delay -61 -> 252, step: 4
5745 10:01:52.210738
5746 10:01:52.210846 Set Vref, RX VrefLevel [Byte0]: 58
5747 10:01:52.213803 [Byte1]: 52
5748 10:01:52.219091
5749 10:01:52.219192 Final RX Vref Byte 0 = 58 to rank0
5750 10:01:52.222347 Final RX Vref Byte 1 = 52 to rank0
5751 10:01:52.225852 Final RX Vref Byte 0 = 58 to rank1
5752 10:01:52.229333 Final RX Vref Byte 1 = 52 to rank1==
5753 10:01:52.232626 Dram Type= 6, Freq= 0, CH_1, rank 0
5754 10:01:52.236038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5755 10:01:52.239259 ==
5756 10:01:52.239367 DQS Delay:
5757 10:01:52.239465 DQS0 = 0, DQS1 = 0
5758 10:01:52.242461 DQM Delay:
5759 10:01:52.242545 DQM0 = 98, DQM1 = 90
5760 10:01:52.246157 DQ Delay:
5761 10:01:52.246252 DQ0 =100, DQ1 =92, DQ2 =88, DQ3 =98
5762 10:01:52.248938 DQ4 =96, DQ5 =108, DQ6 =110, DQ7 =96
5763 10:01:52.252701 DQ8 =80, DQ9 =80, DQ10 =90, DQ11 =86
5764 10:01:52.256182 DQ12 =98, DQ13 =98, DQ14 =96, DQ15 =96
5765 10:01:52.259600
5766 10:01:52.259710
5767 10:01:52.266259 [DQSOSCAuto] RK0, (LSB)MR18= 0x15f2, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 415 ps
5768 10:01:52.269251 CH1 RK0: MR19=504, MR18=15F2
5769 10:01:52.276697 CH1_RK0: MR19=0x504, MR18=0x15F2, DQSOSC=415, MR23=63, INC=62, DEC=41
5770 10:01:52.276846
5771 10:01:52.279611 ----->DramcWriteLeveling(PI) begin...
5772 10:01:52.279738 ==
5773 10:01:52.282828 Dram Type= 6, Freq= 0, CH_1, rank 1
5774 10:01:52.286172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5775 10:01:52.286260 ==
5776 10:01:52.289270 Write leveling (Byte 0): 26 => 26
5777 10:01:52.292927 Write leveling (Byte 1): 27 => 27
5778 10:01:52.296438 DramcWriteLeveling(PI) end<-----
5779 10:01:52.296560
5780 10:01:52.296657 ==
5781 10:01:52.299464 Dram Type= 6, Freq= 0, CH_1, rank 1
5782 10:01:52.302813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5783 10:01:52.302905 ==
5784 10:01:52.305995 [Gating] SW mode calibration
5785 10:01:52.312867 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5786 10:01:52.319573 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5787 10:01:52.322822 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5788 10:01:52.326137 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5789 10:01:52.332878 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5790 10:01:52.336480 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5791 10:01:52.339190 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5792 10:01:52.346338 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5793 10:01:52.349560 0 14 24 | B1->B0 | 3232 2e2e | 0 0 | (0 0) (0 1)
5794 10:01:52.352994 0 14 28 | B1->B0 | 2828 2424 | 0 0 | (0 0) (0 0)
5795 10:01:52.359618 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5796 10:01:52.363016 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5797 10:01:52.366492 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5798 10:01:52.369560 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5799 10:01:52.376444 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5800 10:01:52.379420 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5801 10:01:52.382760 0 15 24 | B1->B0 | 2525 3332 | 0 1 | (0 0) (0 0)
5802 10:01:52.389518 0 15 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5803 10:01:52.392581 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 10:01:52.396135 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5805 10:01:52.402762 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5806 10:01:52.406273 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5807 10:01:52.409662 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5808 10:01:52.416120 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5809 10:01:52.419595 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5810 10:01:52.423170 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 10:01:52.429797 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 10:01:52.432936 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 10:01:52.436464 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 10:01:52.443182 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 10:01:52.445994 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 10:01:52.449379 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 10:01:52.452782 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 10:01:52.459535 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 10:01:52.462869 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 10:01:52.465896 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 10:01:52.472651 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 10:01:52.476038 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 10:01:52.479561 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 10:01:52.486107 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 10:01:52.489602 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5826 10:01:52.493093 Total UI for P1: 0, mck2ui 16
5827 10:01:52.496281 best dqsien dly found for B0: ( 1, 2, 22)
5828 10:01:52.499768 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 10:01:52.503124 Total UI for P1: 0, mck2ui 16
5830 10:01:52.506332 best dqsien dly found for B1: ( 1, 2, 24)
5831 10:01:52.509828 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5832 10:01:52.512781 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5833 10:01:52.512887
5834 10:01:52.519271 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5835 10:01:52.522978 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5836 10:01:52.523087 [Gating] SW calibration Done
5837 10:01:52.526502 ==
5838 10:01:52.529486 Dram Type= 6, Freq= 0, CH_1, rank 1
5839 10:01:52.533033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5840 10:01:52.533136 ==
5841 10:01:52.533274 RX Vref Scan: 0
5842 10:01:52.533372
5843 10:01:52.536307 RX Vref 0 -> 0, step: 1
5844 10:01:52.536385
5845 10:01:52.539548 RX Delay -80 -> 252, step: 8
5846 10:01:52.543228 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5847 10:01:52.546087 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5848 10:01:52.549605 iDelay=200, Bit 2, Center 83 (-16 ~ 183) 200
5849 10:01:52.556570 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5850 10:01:52.559293 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5851 10:01:52.562711 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5852 10:01:52.566126 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5853 10:01:52.569525 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5854 10:01:52.572887 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5855 10:01:52.579646 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5856 10:01:52.583007 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5857 10:01:52.586373 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5858 10:01:52.589401 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5859 10:01:52.592854 iDelay=200, Bit 13, Center 99 (0 ~ 199) 200
5860 10:01:52.596301 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5861 10:01:52.602662 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5862 10:01:52.602770 ==
5863 10:01:52.606316 Dram Type= 6, Freq= 0, CH_1, rank 1
5864 10:01:52.609522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5865 10:01:52.609621 ==
5866 10:01:52.609715 DQS Delay:
5867 10:01:52.612744 DQS0 = 0, DQS1 = 0
5868 10:01:52.612815 DQM Delay:
5869 10:01:52.616728 DQM0 = 93, DQM1 = 89
5870 10:01:52.616825 DQ Delay:
5871 10:01:52.619578 DQ0 =95, DQ1 =87, DQ2 =83, DQ3 =95
5872 10:01:52.623114 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5873 10:01:52.626226 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5874 10:01:52.629468 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =95
5875 10:01:52.629546
5876 10:01:52.629649
5877 10:01:52.629709 ==
5878 10:01:52.632908 Dram Type= 6, Freq= 0, CH_1, rank 1
5879 10:01:52.636486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5880 10:01:52.636597 ==
5881 10:01:52.636703
5882 10:01:52.636793
5883 10:01:52.639702 TX Vref Scan disable
5884 10:01:52.643160 == TX Byte 0 ==
5885 10:01:52.646457 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5886 10:01:52.649547 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5887 10:01:52.653229 == TX Byte 1 ==
5888 10:01:52.656436 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5889 10:01:52.659706 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5890 10:01:52.659826 ==
5891 10:01:52.663129 Dram Type= 6, Freq= 0, CH_1, rank 1
5892 10:01:52.666387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5893 10:01:52.669918 ==
5894 10:01:52.670016
5895 10:01:52.670167
5896 10:01:52.670282 TX Vref Scan disable
5897 10:01:52.673163 == TX Byte 0 ==
5898 10:01:52.676678 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5899 10:01:52.680068 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5900 10:01:52.683540 == TX Byte 1 ==
5901 10:01:52.686746 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5902 10:01:52.689939 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5903 10:01:52.693493
5904 10:01:52.693606 [DATLAT]
5905 10:01:52.693706 Freq=933, CH1 RK1
5906 10:01:52.693811
5907 10:01:52.697419 DATLAT Default: 0xb
5908 10:01:52.697527 0, 0xFFFF, sum = 0
5909 10:01:52.700377 1, 0xFFFF, sum = 0
5910 10:01:52.700518 2, 0xFFFF, sum = 0
5911 10:01:52.703195 3, 0xFFFF, sum = 0
5912 10:01:52.703305 4, 0xFFFF, sum = 0
5913 10:01:52.706741 5, 0xFFFF, sum = 0
5914 10:01:52.710169 6, 0xFFFF, sum = 0
5915 10:01:52.710281 7, 0xFFFF, sum = 0
5916 10:01:52.713642 8, 0xFFFF, sum = 0
5917 10:01:52.713771 9, 0xFFFF, sum = 0
5918 10:01:52.716819 10, 0x0, sum = 1
5919 10:01:52.716930 11, 0x0, sum = 2
5920 10:01:52.717038 12, 0x0, sum = 3
5921 10:01:52.719915 13, 0x0, sum = 4
5922 10:01:52.720029 best_step = 11
5923 10:01:52.720131
5924 10:01:52.720227 ==
5925 10:01:52.723263 Dram Type= 6, Freq= 0, CH_1, rank 1
5926 10:01:52.729908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5927 10:01:52.730031 ==
5928 10:01:52.730132 RX Vref Scan: 0
5929 10:01:52.730233
5930 10:01:52.733586 RX Vref 0 -> 0, step: 1
5931 10:01:52.733693
5932 10:01:52.736906 RX Delay -61 -> 252, step: 4
5933 10:01:52.740305 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5934 10:01:52.746771 iDelay=199, Bit 1, Center 88 (-5 ~ 182) 188
5935 10:01:52.750715 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5936 10:01:52.753709 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5937 10:01:52.756784 iDelay=199, Bit 4, Center 94 (-1 ~ 190) 192
5938 10:01:52.760025 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5939 10:01:52.763621 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5940 10:01:52.769914 iDelay=199, Bit 7, Center 90 (-1 ~ 182) 184
5941 10:01:52.773845 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
5942 10:01:52.776824 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5943 10:01:52.780973 iDelay=199, Bit 10, Center 90 (-5 ~ 186) 192
5944 10:01:52.784120 iDelay=199, Bit 11, Center 84 (-5 ~ 174) 180
5945 10:01:52.786731 iDelay=199, Bit 12, Center 96 (7 ~ 186) 180
5946 10:01:52.793680 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
5947 10:01:52.796955 iDelay=199, Bit 14, Center 96 (3 ~ 190) 188
5948 10:01:52.799936 iDelay=199, Bit 15, Center 98 (7 ~ 190) 184
5949 10:01:52.800044 ==
5950 10:01:52.803779 Dram Type= 6, Freq= 0, CH_1, rank 1
5951 10:01:52.807115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5952 10:01:52.807221 ==
5953 10:01:52.810021 DQS Delay:
5954 10:01:52.810103 DQS0 = 0, DQS1 = 0
5955 10:01:52.810186 DQM Delay:
5956 10:01:52.813619 DQM0 = 94, DQM1 = 90
5957 10:01:52.813719 DQ Delay:
5958 10:01:52.817019 DQ0 =98, DQ1 =88, DQ2 =86, DQ3 =92
5959 10:01:52.820104 DQ4 =94, DQ5 =106, DQ6 =102, DQ7 =90
5960 10:01:52.823561 DQ8 =80, DQ9 =80, DQ10 =90, DQ11 =84
5961 10:01:52.827078 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =98
5962 10:01:52.827157
5963 10:01:52.827222
5964 10:01:52.837010 [DQSOSCAuto] RK1, (LSB)MR18= 0xf18, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
5965 10:01:52.837127 CH1 RK1: MR19=505, MR18=F18
5966 10:01:52.843807 CH1_RK1: MR19=0x505, MR18=0xF18, DQSOSC=414, MR23=63, INC=63, DEC=42
5967 10:01:52.846751 [RxdqsGatingPostProcess] freq 933
5968 10:01:52.853898 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5969 10:01:52.857299 best DQS0 dly(2T, 0.5T) = (0, 10)
5970 10:01:52.860535 best DQS1 dly(2T, 0.5T) = (0, 10)
5971 10:01:52.863449 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5972 10:01:52.867006 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5973 10:01:52.870508 best DQS0 dly(2T, 0.5T) = (0, 10)
5974 10:01:52.870638 best DQS1 dly(2T, 0.5T) = (0, 10)
5975 10:01:52.873336 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5976 10:01:52.876973 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5977 10:01:52.880061 Pre-setting of DQS Precalculation
5978 10:01:52.886941 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5979 10:01:52.893621 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5980 10:01:52.900188 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5981 10:01:52.900307
5982 10:01:52.900408
5983 10:01:52.903448 [Calibration Summary] 1866 Mbps
5984 10:01:52.903560 CH 0, Rank 0
5985 10:01:52.906873 SW Impedance : PASS
5986 10:01:52.909825 DUTY Scan : NO K
5987 10:01:52.909936 ZQ Calibration : PASS
5988 10:01:52.913356 Jitter Meter : NO K
5989 10:01:52.916534 CBT Training : PASS
5990 10:01:52.916665 Write leveling : PASS
5991 10:01:52.920185 RX DQS gating : PASS
5992 10:01:52.923117 RX DQ/DQS(RDDQC) : PASS
5993 10:01:52.923240 TX DQ/DQS : PASS
5994 10:01:52.926389 RX DATLAT : PASS
5995 10:01:52.929776 RX DQ/DQS(Engine): PASS
5996 10:01:52.929880 TX OE : NO K
5997 10:01:52.933369 All Pass.
5998 10:01:52.933476
5999 10:01:52.933570 CH 0, Rank 1
6000 10:01:52.936393 SW Impedance : PASS
6001 10:01:52.936507 DUTY Scan : NO K
6002 10:01:52.939783 ZQ Calibration : PASS
6003 10:01:52.943649 Jitter Meter : NO K
6004 10:01:52.943757 CBT Training : PASS
6005 10:01:52.946981 Write leveling : PASS
6006 10:01:52.947093 RX DQS gating : PASS
6007 10:01:52.950194 RX DQ/DQS(RDDQC) : PASS
6008 10:01:52.953716 TX DQ/DQS : PASS
6009 10:01:52.953829 RX DATLAT : PASS
6010 10:01:52.956777 RX DQ/DQS(Engine): PASS
6011 10:01:52.959919 TX OE : NO K
6012 10:01:52.960035 All Pass.
6013 10:01:52.960153
6014 10:01:52.960252 CH 1, Rank 0
6015 10:01:52.963319 SW Impedance : PASS
6016 10:01:52.966593 DUTY Scan : NO K
6017 10:01:52.966701 ZQ Calibration : PASS
6018 10:01:52.970077 Jitter Meter : NO K
6019 10:01:52.973412 CBT Training : PASS
6020 10:01:52.973519 Write leveling : PASS
6021 10:01:52.976359 RX DQS gating : PASS
6022 10:01:52.979976 RX DQ/DQS(RDDQC) : PASS
6023 10:01:52.980079 TX DQ/DQS : PASS
6024 10:01:52.983201 RX DATLAT : PASS
6025 10:01:52.986325 RX DQ/DQS(Engine): PASS
6026 10:01:52.986429 TX OE : NO K
6027 10:01:52.986525 All Pass.
6028 10:01:52.989998
6029 10:01:52.990125 CH 1, Rank 1
6030 10:01:52.993556 SW Impedance : PASS
6031 10:01:52.993662 DUTY Scan : NO K
6032 10:01:52.996623 ZQ Calibration : PASS
6033 10:01:52.996752 Jitter Meter : NO K
6034 10:01:53.000098 CBT Training : PASS
6035 10:01:53.003379 Write leveling : PASS
6036 10:01:53.003486 RX DQS gating : PASS
6037 10:01:53.006576 RX DQ/DQS(RDDQC) : PASS
6038 10:01:53.010088 TX DQ/DQS : PASS
6039 10:01:53.010175 RX DATLAT : PASS
6040 10:01:53.013463 RX DQ/DQS(Engine): PASS
6041 10:01:53.016474 TX OE : NO K
6042 10:01:53.016580 All Pass.
6043 10:01:53.016686
6044 10:01:53.016777 DramC Write-DBI off
6045 10:01:53.020469 PER_BANK_REFRESH: Hybrid Mode
6046 10:01:53.023326 TX_TRACKING: ON
6047 10:01:53.030051 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6048 10:01:53.033567 [FAST_K] Save calibration result to emmc
6049 10:01:53.039990 dramc_set_vcore_voltage set vcore to 650000
6050 10:01:53.040088 Read voltage for 400, 6
6051 10:01:53.043478 Vio18 = 0
6052 10:01:53.043565 Vcore = 650000
6053 10:01:53.043632 Vdram = 0
6054 10:01:53.043693 Vddq = 0
6055 10:01:53.046992 Vmddr = 0
6056 10:01:53.049935 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6057 10:01:53.057094 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6058 10:01:53.059998 MEM_TYPE=3, freq_sel=20
6059 10:01:53.060092 sv_algorithm_assistance_LP4_800
6060 10:01:53.067158 ============ PULL DRAM RESETB DOWN ============
6061 10:01:53.070424 ========== PULL DRAM RESETB DOWN end =========
6062 10:01:53.073338 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6063 10:01:53.076870 ===================================
6064 10:01:53.080399 LPDDR4 DRAM CONFIGURATION
6065 10:01:53.083403 ===================================
6066 10:01:53.086674 EX_ROW_EN[0] = 0x0
6067 10:01:53.086751 EX_ROW_EN[1] = 0x0
6068 10:01:53.090018 LP4Y_EN = 0x0
6069 10:01:53.090107 WORK_FSP = 0x0
6070 10:01:53.093263 WL = 0x2
6071 10:01:53.093347 RL = 0x2
6072 10:01:53.096754 BL = 0x2
6073 10:01:53.096838 RPST = 0x0
6074 10:01:53.100137 RD_PRE = 0x0
6075 10:01:53.100246 WR_PRE = 0x1
6076 10:01:53.103566 WR_PST = 0x0
6077 10:01:53.103669 DBI_WR = 0x0
6078 10:01:53.107574 DBI_RD = 0x0
6079 10:01:53.107696 OTF = 0x1
6080 10:01:53.110201 ===================================
6081 10:01:53.113667 ===================================
6082 10:01:53.117115 ANA top config
6083 10:01:53.119934 ===================================
6084 10:01:53.123400 DLL_ASYNC_EN = 0
6085 10:01:53.123507 ALL_SLAVE_EN = 1
6086 10:01:53.127033 NEW_RANK_MODE = 1
6087 10:01:53.130365 DLL_IDLE_MODE = 1
6088 10:01:53.133144 LP45_APHY_COMB_EN = 1
6089 10:01:53.133223 TX_ODT_DIS = 1
6090 10:01:53.136580 NEW_8X_MODE = 1
6091 10:01:53.140007 ===================================
6092 10:01:53.143531 ===================================
6093 10:01:53.146814 data_rate = 800
6094 10:01:53.149853 CKR = 1
6095 10:01:53.153318 DQ_P2S_RATIO = 4
6096 10:01:53.156883 ===================================
6097 10:01:53.160190 CA_P2S_RATIO = 4
6098 10:01:53.160300 DQ_CA_OPEN = 0
6099 10:01:53.163526 DQ_SEMI_OPEN = 1
6100 10:01:53.167122 CA_SEMI_OPEN = 1
6101 10:01:53.169870 CA_FULL_RATE = 0
6102 10:01:53.173516 DQ_CKDIV4_EN = 0
6103 10:01:53.173675 CA_CKDIV4_EN = 1
6104 10:01:53.176562 CA_PREDIV_EN = 0
6105 10:01:53.180026 PH8_DLY = 0
6106 10:01:53.183243 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6107 10:01:53.186708 DQ_AAMCK_DIV = 0
6108 10:01:53.190330 CA_AAMCK_DIV = 0
6109 10:01:53.190456 CA_ADMCK_DIV = 4
6110 10:01:53.193156 DQ_TRACK_CA_EN = 0
6111 10:01:53.196919 CA_PICK = 800
6112 10:01:53.200179 CA_MCKIO = 400
6113 10:01:53.203157 MCKIO_SEMI = 400
6114 10:01:53.206635 PLL_FREQ = 3016
6115 10:01:53.209973 DQ_UI_PI_RATIO = 32
6116 10:01:53.213458 CA_UI_PI_RATIO = 32
6117 10:01:53.213596 ===================================
6118 10:01:53.216752 ===================================
6119 10:01:53.220389 memory_type:LPDDR4
6120 10:01:53.223855 GP_NUM : 10
6121 10:01:53.223992 SRAM_EN : 1
6122 10:01:53.226674 MD32_EN : 0
6123 10:01:53.230875 ===================================
6124 10:01:53.233905 [ANA_INIT] >>>>>>>>>>>>>>
6125 10:01:53.236783 <<<<<< [CONFIGURE PHASE]: ANA_TX
6126 10:01:53.240108 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6127 10:01:53.243603 ===================================
6128 10:01:53.243715 data_rate = 800,PCW = 0X7400
6129 10:01:53.246956 ===================================
6130 10:01:53.250303 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6131 10:01:53.256648 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6132 10:01:53.267165 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6133 10:01:53.273824 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6134 10:01:53.277247 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6135 10:01:53.280770 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6136 10:01:53.280900 [ANA_INIT] flow start
6137 10:01:53.283756 [ANA_INIT] PLL >>>>>>>>
6138 10:01:53.287142 [ANA_INIT] PLL <<<<<<<<
6139 10:01:53.291046 [ANA_INIT] MIDPI >>>>>>>>
6140 10:01:53.291185 [ANA_INIT] MIDPI <<<<<<<<
6141 10:01:53.294137 [ANA_INIT] DLL >>>>>>>>
6142 10:01:53.294241 [ANA_INIT] flow end
6143 10:01:53.300413 ============ LP4 DIFF to SE enter ============
6144 10:01:53.303611 ============ LP4 DIFF to SE exit ============
6145 10:01:53.307469 [ANA_INIT] <<<<<<<<<<<<<
6146 10:01:53.310384 [Flow] Enable top DCM control >>>>>
6147 10:01:53.313910 [Flow] Enable top DCM control <<<<<
6148 10:01:53.314004 Enable DLL master slave shuffle
6149 10:01:53.320338 ==============================================================
6150 10:01:53.324025 Gating Mode config
6151 10:01:53.327760 ==============================================================
6152 10:01:53.330664 Config description:
6153 10:01:53.340545 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6154 10:01:53.347358 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6155 10:01:53.350636 SELPH_MODE 0: By rank 1: By Phase
6156 10:01:53.357098 ==============================================================
6157 10:01:53.360535 GAT_TRACK_EN = 0
6158 10:01:53.364014 RX_GATING_MODE = 2
6159 10:01:53.367418 RX_GATING_TRACK_MODE = 2
6160 10:01:53.367520 SELPH_MODE = 1
6161 10:01:53.371128 PICG_EARLY_EN = 1
6162 10:01:53.373943 VALID_LAT_VALUE = 1
6163 10:01:53.380801 ==============================================================
6164 10:01:53.384079 Enter into Gating configuration >>>>
6165 10:01:53.387478 Exit from Gating configuration <<<<
6166 10:01:53.391030 Enter into DVFS_PRE_config >>>>>
6167 10:01:53.400544 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6168 10:01:53.404093 Exit from DVFS_PRE_config <<<<<
6169 10:01:53.407344 Enter into PICG configuration >>>>
6170 10:01:53.411243 Exit from PICG configuration <<<<
6171 10:01:53.414454 [RX_INPUT] configuration >>>>>
6172 10:01:53.417976 [RX_INPUT] configuration <<<<<
6173 10:01:53.420899 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6174 10:01:53.427741 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6175 10:01:53.434398 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6176 10:01:53.437841 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6177 10:01:53.444604 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6178 10:01:53.451339 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6179 10:01:53.454433 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6180 10:01:53.457963 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6181 10:01:53.464403 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6182 10:01:53.467881 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6183 10:01:53.470826 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6184 10:01:53.477701 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6185 10:01:53.481233 ===================================
6186 10:01:53.481312 LPDDR4 DRAM CONFIGURATION
6187 10:01:53.484771 ===================================
6188 10:01:53.487578 EX_ROW_EN[0] = 0x0
6189 10:01:53.487685 EX_ROW_EN[1] = 0x0
6190 10:01:53.491432 LP4Y_EN = 0x0
6191 10:01:53.494412 WORK_FSP = 0x0
6192 10:01:53.494489 WL = 0x2
6193 10:01:53.497854 RL = 0x2
6194 10:01:53.497940 BL = 0x2
6195 10:01:53.501684 RPST = 0x0
6196 10:01:53.501784 RD_PRE = 0x0
6197 10:01:53.504261 WR_PRE = 0x1
6198 10:01:53.504340 WR_PST = 0x0
6199 10:01:53.507942 DBI_WR = 0x0
6200 10:01:53.508014 DBI_RD = 0x0
6201 10:01:53.510967 OTF = 0x1
6202 10:01:53.514248 ===================================
6203 10:01:53.517817 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6204 10:01:53.520943 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6205 10:01:53.524248 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6206 10:01:53.527936 ===================================
6207 10:01:53.531063 LPDDR4 DRAM CONFIGURATION
6208 10:01:53.534666 ===================================
6209 10:01:53.537971 EX_ROW_EN[0] = 0x10
6210 10:01:53.538055 EX_ROW_EN[1] = 0x0
6211 10:01:53.541464 LP4Y_EN = 0x0
6212 10:01:53.541575 WORK_FSP = 0x0
6213 10:01:53.544467 WL = 0x2
6214 10:01:53.544580 RL = 0x2
6215 10:01:53.548241 BL = 0x2
6216 10:01:53.548352 RPST = 0x0
6217 10:01:53.551326 RD_PRE = 0x0
6218 10:01:53.551409 WR_PRE = 0x1
6219 10:01:53.554644 WR_PST = 0x0
6220 10:01:53.554726 DBI_WR = 0x0
6221 10:01:53.557584 DBI_RD = 0x0
6222 10:01:53.561193 OTF = 0x1
6223 10:01:53.561278 ===================================
6224 10:01:53.568117 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6225 10:01:53.572999 nWR fixed to 30
6226 10:01:53.576693 [ModeRegInit_LP4] CH0 RK0
6227 10:01:53.576772 [ModeRegInit_LP4] CH0 RK1
6228 10:01:53.579367 [ModeRegInit_LP4] CH1 RK0
6229 10:01:53.582656 [ModeRegInit_LP4] CH1 RK1
6230 10:01:53.582729 match AC timing 19
6231 10:01:53.589669 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6232 10:01:53.593115 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6233 10:01:53.596030 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6234 10:01:53.603253 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6235 10:01:53.606211 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6236 10:01:53.606285 ==
6237 10:01:53.609810 Dram Type= 6, Freq= 0, CH_0, rank 0
6238 10:01:53.613064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6239 10:01:53.613164 ==
6240 10:01:53.619546 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6241 10:01:53.626681 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6242 10:01:53.629631 [CA 0] Center 36 (8~64) winsize 57
6243 10:01:53.633371 [CA 1] Center 36 (8~64) winsize 57
6244 10:01:53.633451 [CA 2] Center 36 (8~64) winsize 57
6245 10:01:53.636575 [CA 3] Center 36 (8~64) winsize 57
6246 10:01:53.639966 [CA 4] Center 36 (8~64) winsize 57
6247 10:01:53.642885 [CA 5] Center 36 (8~64) winsize 57
6248 10:01:53.642974
6249 10:01:53.646242 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6250 10:01:53.646341
6251 10:01:53.653208 [CATrainingPosCal] consider 1 rank data
6252 10:01:53.653284 u2DelayCellTimex100 = 270/100 ps
6253 10:01:53.656712 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 10:01:53.662732 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 10:01:53.666111 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 10:01:53.669775 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 10:01:53.673332 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 10:01:53.676684 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 10:01:53.676756
6260 10:01:53.679804 CA PerBit enable=1, Macro0, CA PI delay=36
6261 10:01:53.679879
6262 10:01:53.682591 [CBTSetCACLKResult] CA Dly = 36
6263 10:01:53.686442 CS Dly: 1 (0~32)
6264 10:01:53.686531 ==
6265 10:01:53.689291 Dram Type= 6, Freq= 0, CH_0, rank 1
6266 10:01:53.693095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6267 10:01:53.693196 ==
6268 10:01:53.696084 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6269 10:01:53.702766 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6270 10:01:53.706431 [CA 0] Center 36 (8~64) winsize 57
6271 10:01:53.709721 [CA 1] Center 36 (8~64) winsize 57
6272 10:01:53.712736 [CA 2] Center 36 (8~64) winsize 57
6273 10:01:53.716287 [CA 3] Center 36 (8~64) winsize 57
6274 10:01:53.719324 [CA 4] Center 36 (8~64) winsize 57
6275 10:01:53.722702 [CA 5] Center 36 (8~64) winsize 57
6276 10:01:53.722802
6277 10:01:53.726079 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6278 10:01:53.726162
6279 10:01:53.729777 [CATrainingPosCal] consider 2 rank data
6280 10:01:53.733005 u2DelayCellTimex100 = 270/100 ps
6281 10:01:53.736205 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 10:01:53.739440 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 10:01:53.743068 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 10:01:53.746164 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 10:01:53.749948 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 10:01:53.756590 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 10:01:53.756679
6288 10:01:53.759951 CA PerBit enable=1, Macro0, CA PI delay=36
6289 10:01:53.760036
6290 10:01:53.762844 [CBTSetCACLKResult] CA Dly = 36
6291 10:01:53.762964 CS Dly: 1 (0~32)
6292 10:01:53.763062
6293 10:01:53.766072 ----->DramcWriteLeveling(PI) begin...
6294 10:01:53.766172 ==
6295 10:01:53.769330 Dram Type= 6, Freq= 0, CH_0, rank 0
6296 10:01:53.773059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6297 10:01:53.776617 ==
6298 10:01:53.776700 Write leveling (Byte 0): 40 => 8
6299 10:01:53.779519 Write leveling (Byte 1): 32 => 0
6300 10:01:53.783009 DramcWriteLeveling(PI) end<-----
6301 10:01:53.783091
6302 10:01:53.783154 ==
6303 10:01:53.786063 Dram Type= 6, Freq= 0, CH_0, rank 0
6304 10:01:53.792883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6305 10:01:53.792980 ==
6306 10:01:53.793060 [Gating] SW mode calibration
6307 10:01:53.803044 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6308 10:01:53.806054 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6309 10:01:53.809579 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6310 10:01:53.816489 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6311 10:01:53.819793 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6312 10:01:53.822875 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6313 10:01:53.830139 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6314 10:01:53.833406 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6315 10:01:53.836414 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6316 10:01:53.843191 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6317 10:01:53.846619 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6318 10:01:53.850114 Total UI for P1: 0, mck2ui 16
6319 10:01:53.853024 best dqsien dly found for B0: ( 0, 14, 24)
6320 10:01:53.856949 Total UI for P1: 0, mck2ui 16
6321 10:01:53.859870 best dqsien dly found for B1: ( 0, 14, 24)
6322 10:01:53.863569 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6323 10:01:53.866704 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6324 10:01:53.866788
6325 10:01:53.870128 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6326 10:01:53.873559 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6327 10:01:53.876876 [Gating] SW calibration Done
6328 10:01:53.876959 ==
6329 10:01:53.880174 Dram Type= 6, Freq= 0, CH_0, rank 0
6330 10:01:53.883975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 10:01:53.884062 ==
6332 10:01:53.886897 RX Vref Scan: 0
6333 10:01:53.886980
6334 10:01:53.889905 RX Vref 0 -> 0, step: 1
6335 10:01:53.890032
6336 10:01:53.890132 RX Delay -410 -> 252, step: 16
6337 10:01:53.896790 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6338 10:01:53.899845 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6339 10:01:53.903552 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6340 10:01:53.906723 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6341 10:01:53.913227 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6342 10:01:53.916444 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6343 10:01:53.920024 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6344 10:01:53.923401 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6345 10:01:53.929846 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6346 10:01:53.933412 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6347 10:01:53.936766 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6348 10:01:53.940193 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6349 10:01:53.946463 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6350 10:01:53.950006 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6351 10:01:53.953535 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6352 10:01:53.960576 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6353 10:01:53.960665 ==
6354 10:01:53.963241 Dram Type= 6, Freq= 0, CH_0, rank 0
6355 10:01:53.966984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6356 10:01:53.967083 ==
6357 10:01:53.967192 DQS Delay:
6358 10:01:53.970305 DQS0 = 35, DQS1 = 51
6359 10:01:53.970391 DQM Delay:
6360 10:01:53.973591 DQM0 = 7, DQM1 = 10
6361 10:01:53.973676 DQ Delay:
6362 10:01:53.976466 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6363 10:01:53.980192 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6364 10:01:53.983244 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6365 10:01:53.986866 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6366 10:01:53.986954
6367 10:01:53.987020
6368 10:01:53.987081 ==
6369 10:01:53.990451 Dram Type= 6, Freq= 0, CH_0, rank 0
6370 10:01:53.993293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6371 10:01:53.993381 ==
6372 10:01:53.993450
6373 10:01:53.993513
6374 10:01:53.996756 TX Vref Scan disable
6375 10:01:53.996838 == TX Byte 0 ==
6376 10:01:54.003202 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6377 10:01:54.006728 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6378 10:01:54.006835 == TX Byte 1 ==
6379 10:01:54.009900 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6380 10:01:54.017725 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6381 10:01:54.017867 ==
6382 10:01:54.020280 Dram Type= 6, Freq= 0, CH_0, rank 0
6383 10:01:54.023942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6384 10:01:54.024099 ==
6385 10:01:54.024166
6386 10:01:54.024227
6387 10:01:54.027217 TX Vref Scan disable
6388 10:01:54.027299 == TX Byte 0 ==
6389 10:01:54.033960 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6390 10:01:54.037106 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6391 10:01:54.037244 == TX Byte 1 ==
6392 10:01:54.040323 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6393 10:01:54.047338 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6394 10:01:54.047445
6395 10:01:54.047526 [DATLAT]
6396 10:01:54.050231 Freq=400, CH0 RK0
6397 10:01:54.050315
6398 10:01:54.050380 DATLAT Default: 0xf
6399 10:01:54.053664 0, 0xFFFF, sum = 0
6400 10:01:54.053780 1, 0xFFFF, sum = 0
6401 10:01:54.057306 2, 0xFFFF, sum = 0
6402 10:01:54.057418 3, 0xFFFF, sum = 0
6403 10:01:54.060565 4, 0xFFFF, sum = 0
6404 10:01:54.060708 5, 0xFFFF, sum = 0
6405 10:01:54.063508 6, 0xFFFF, sum = 0
6406 10:01:54.063623 7, 0xFFFF, sum = 0
6407 10:01:54.067350 8, 0xFFFF, sum = 0
6408 10:01:54.067435 9, 0xFFFF, sum = 0
6409 10:01:54.070688 10, 0xFFFF, sum = 0
6410 10:01:54.070810 11, 0xFFFF, sum = 0
6411 10:01:54.073862 12, 0xFFFF, sum = 0
6412 10:01:54.073965 13, 0x0, sum = 1
6413 10:01:54.077273 14, 0x0, sum = 2
6414 10:01:54.077374 15, 0x0, sum = 3
6415 10:01:54.080336 16, 0x0, sum = 4
6416 10:01:54.080429 best_step = 14
6417 10:01:54.080528
6418 10:01:54.080602 ==
6419 10:01:54.084048 Dram Type= 6, Freq= 0, CH_0, rank 0
6420 10:01:54.090546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6421 10:01:54.090693 ==
6422 10:01:54.090795 RX Vref Scan: 1
6423 10:01:54.090908
6424 10:01:54.093781 RX Vref 0 -> 0, step: 1
6425 10:01:54.093894
6426 10:01:54.097366 RX Delay -343 -> 252, step: 8
6427 10:01:54.097482
6428 10:01:54.101040 Set Vref, RX VrefLevel [Byte0]: 53
6429 10:01:54.103880 [Byte1]: 51
6430 10:01:54.103986
6431 10:01:54.107248 Final RX Vref Byte 0 = 53 to rank0
6432 10:01:54.110697 Final RX Vref Byte 1 = 51 to rank0
6433 10:01:54.113772 Final RX Vref Byte 0 = 53 to rank1
6434 10:01:54.117073 Final RX Vref Byte 1 = 51 to rank1==
6435 10:01:54.120524 Dram Type= 6, Freq= 0, CH_0, rank 0
6436 10:01:54.124491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6437 10:01:54.124606 ==
6438 10:01:54.126845 DQS Delay:
6439 10:01:54.126976 DQS0 = 44, DQS1 = 60
6440 10:01:54.130268 DQM Delay:
6441 10:01:54.130374 DQM0 = 11, DQM1 = 15
6442 10:01:54.133605 DQ Delay:
6443 10:01:54.133707 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6444 10:01:54.137315 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6445 10:01:54.140354 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =12
6446 10:01:54.143581 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =28
6447 10:01:54.143695
6448 10:01:54.143797
6449 10:01:54.153774 [DQSOSCAuto] RK0, (LSB)MR18= 0x8250, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 393 ps
6450 10:01:54.157066 CH0 RK0: MR19=C0C, MR18=8250
6451 10:01:54.160474 CH0_RK0: MR19=0xC0C, MR18=0x8250, DQSOSC=393, MR23=63, INC=382, DEC=254
6452 10:01:54.163911 ==
6453 10:01:54.167406 Dram Type= 6, Freq= 0, CH_0, rank 1
6454 10:01:54.170535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6455 10:01:54.170644 ==
6456 10:01:54.173890 [Gating] SW mode calibration
6457 10:01:54.180169 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6458 10:01:54.183583 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6459 10:01:54.190625 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6460 10:01:54.193741 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6461 10:01:54.197126 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6462 10:01:54.203484 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6463 10:01:54.207045 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6464 10:01:54.210461 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6465 10:01:54.216957 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6466 10:01:54.220490 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6467 10:01:54.223921 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6468 10:01:54.226764 Total UI for P1: 0, mck2ui 16
6469 10:01:54.230628 best dqsien dly found for B0: ( 0, 14, 24)
6470 10:01:54.234100 Total UI for P1: 0, mck2ui 16
6471 10:01:54.236819 best dqsien dly found for B1: ( 0, 14, 24)
6472 10:01:54.240230 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6473 10:01:54.243957 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6474 10:01:54.244086
6475 10:01:54.247211 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6476 10:01:54.253651 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6477 10:01:54.253777 [Gating] SW calibration Done
6478 10:01:54.253913 ==
6479 10:01:54.257247 Dram Type= 6, Freq= 0, CH_0, rank 1
6480 10:01:54.263888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6481 10:01:54.264011 ==
6482 10:01:54.264108 RX Vref Scan: 0
6483 10:01:54.264206
6484 10:01:54.267035 RX Vref 0 -> 0, step: 1
6485 10:01:54.267136
6486 10:01:54.270320 RX Delay -410 -> 252, step: 16
6487 10:01:54.273744 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6488 10:01:54.277311 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6489 10:01:54.283734 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6490 10:01:54.287157 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6491 10:01:54.290480 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6492 10:01:54.294098 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6493 10:01:54.296990 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6494 10:01:54.304550 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6495 10:01:54.307294 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6496 10:01:54.310606 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6497 10:01:54.314091 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6498 10:01:54.320637 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6499 10:01:54.324085 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6500 10:01:54.327339 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6501 10:01:54.334139 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6502 10:01:54.337162 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6503 10:01:54.337266 ==
6504 10:01:54.340724 Dram Type= 6, Freq= 0, CH_0, rank 1
6505 10:01:54.343958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6506 10:01:54.344080 ==
6507 10:01:54.347454 DQS Delay:
6508 10:01:54.347576 DQS0 = 43, DQS1 = 51
6509 10:01:54.347669 DQM Delay:
6510 10:01:54.350503 DQM0 = 11, DQM1 = 10
6511 10:01:54.350619 DQ Delay:
6512 10:01:54.353934 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6513 10:01:54.357550 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6514 10:01:54.360564 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6515 10:01:54.364213 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6516 10:01:54.364341
6517 10:01:54.364449
6518 10:01:54.364542 ==
6519 10:01:54.367117 Dram Type= 6, Freq= 0, CH_0, rank 1
6520 10:01:54.370695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6521 10:01:54.370809 ==
6522 10:01:54.370941
6523 10:01:54.373975
6524 10:01:54.374057 TX Vref Scan disable
6525 10:01:54.377299 == TX Byte 0 ==
6526 10:01:54.380540 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6527 10:01:54.384160 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6528 10:01:54.384265 == TX Byte 1 ==
6529 10:01:54.390825 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6530 10:01:54.394342 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6531 10:01:54.394458 ==
6532 10:01:54.397782 Dram Type= 6, Freq= 0, CH_0, rank 1
6533 10:01:54.400482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6534 10:01:54.400589 ==
6535 10:01:54.400685
6536 10:01:54.400772
6537 10:01:54.404301 TX Vref Scan disable
6538 10:01:54.407221 == TX Byte 0 ==
6539 10:01:54.410661 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6540 10:01:54.413996 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6541 10:01:54.414070 == TX Byte 1 ==
6542 10:01:54.420653 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6543 10:01:54.423926 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6544 10:01:54.424037
6545 10:01:54.424160 [DATLAT]
6546 10:01:54.427096 Freq=400, CH0 RK1
6547 10:01:54.427197
6548 10:01:54.427287 DATLAT Default: 0xe
6549 10:01:54.431018 0, 0xFFFF, sum = 0
6550 10:01:54.431098 1, 0xFFFF, sum = 0
6551 10:01:54.434122 2, 0xFFFF, sum = 0
6552 10:01:54.434258 3, 0xFFFF, sum = 0
6553 10:01:54.437642 4, 0xFFFF, sum = 0
6554 10:01:54.437756 5, 0xFFFF, sum = 0
6555 10:01:54.440616 6, 0xFFFF, sum = 0
6556 10:01:54.440730 7, 0xFFFF, sum = 0
6557 10:01:54.444084 8, 0xFFFF, sum = 0
6558 10:01:54.444197 9, 0xFFFF, sum = 0
6559 10:01:54.447730 10, 0xFFFF, sum = 0
6560 10:01:54.451302 11, 0xFFFF, sum = 0
6561 10:01:54.451406 12, 0xFFFF, sum = 0
6562 10:01:54.454176 13, 0x0, sum = 1
6563 10:01:54.454289 14, 0x0, sum = 2
6564 10:01:54.454385 15, 0x0, sum = 3
6565 10:01:54.457837 16, 0x0, sum = 4
6566 10:01:54.457943 best_step = 14
6567 10:01:54.458040
6568 10:01:54.458134 ==
6569 10:01:54.461067 Dram Type= 6, Freq= 0, CH_0, rank 1
6570 10:01:54.467635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6571 10:01:54.467752 ==
6572 10:01:54.467858 RX Vref Scan: 0
6573 10:01:54.468068
6574 10:01:54.471009 RX Vref 0 -> 0, step: 1
6575 10:01:54.471114
6576 10:01:54.474059 RX Delay -343 -> 252, step: 8
6577 10:01:54.480790 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6578 10:01:54.484234 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6579 10:01:54.487366 iDelay=217, Bit 2, Center -36 (-271 ~ 200) 472
6580 10:01:54.490738 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6581 10:01:54.497697 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6582 10:01:54.500748 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6583 10:01:54.504233 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6584 10:01:54.507519 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6585 10:01:54.514222 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6586 10:01:54.517773 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6587 10:01:54.521109 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6588 10:01:54.524366 iDelay=217, Bit 11, Center -52 (-287 ~ 184) 472
6589 10:01:54.530566 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6590 10:01:54.534265 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6591 10:01:54.537701 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6592 10:01:54.544084 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6593 10:01:54.544197 ==
6594 10:01:54.547185 Dram Type= 6, Freq= 0, CH_0, rank 1
6595 10:01:54.550614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6596 10:01:54.550713 ==
6597 10:01:54.550802 DQS Delay:
6598 10:01:54.554698 DQS0 = 48, DQS1 = 60
6599 10:01:54.554801 DQM Delay:
6600 10:01:54.557338 DQM0 = 13, DQM1 = 14
6601 10:01:54.557435 DQ Delay:
6602 10:01:54.560517 DQ0 =16, DQ1 =16, DQ2 =12, DQ3 =12
6603 10:01:54.564275 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6604 10:01:54.567185 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6605 10:01:54.570724 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6606 10:01:54.570832
6607 10:01:54.570953
6608 10:01:54.577182 [DQSOSCAuto] RK1, (LSB)MR18= 0x9265, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 391 ps
6609 10:01:54.580839 CH0 RK1: MR19=C0C, MR18=9265
6610 10:01:54.587490 CH0_RK1: MR19=0xC0C, MR18=0x9265, DQSOSC=391, MR23=63, INC=386, DEC=257
6611 10:01:54.590881 [RxdqsGatingPostProcess] freq 400
6612 10:01:54.597528 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6613 10:01:54.597731 best DQS0 dly(2T, 0.5T) = (0, 10)
6614 10:01:54.600731 best DQS1 dly(2T, 0.5T) = (0, 10)
6615 10:01:54.604309 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6616 10:01:54.607765 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6617 10:01:54.610766 best DQS0 dly(2T, 0.5T) = (0, 10)
6618 10:01:54.614294 best DQS1 dly(2T, 0.5T) = (0, 10)
6619 10:01:54.617480 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6620 10:01:54.620576 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6621 10:01:54.624047 Pre-setting of DQS Precalculation
6622 10:01:54.627262 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6623 10:01:54.630714 ==
6624 10:01:54.634337 Dram Type= 6, Freq= 0, CH_1, rank 0
6625 10:01:54.638085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6626 10:01:54.638189 ==
6627 10:01:54.640816 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6628 10:01:54.647610 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6629 10:01:54.650691 [CA 0] Center 36 (8~64) winsize 57
6630 10:01:54.654117 [CA 1] Center 36 (8~64) winsize 57
6631 10:01:54.657441 [CA 2] Center 36 (8~64) winsize 57
6632 10:01:54.660704 [CA 3] Center 36 (8~64) winsize 57
6633 10:01:54.663855 [CA 4] Center 36 (8~64) winsize 57
6634 10:01:54.667777 [CA 5] Center 36 (8~64) winsize 57
6635 10:01:54.667868
6636 10:01:54.671280 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6637 10:01:54.671369
6638 10:01:54.674221 [CATrainingPosCal] consider 1 rank data
6639 10:01:54.677729 u2DelayCellTimex100 = 270/100 ps
6640 10:01:54.681318 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 10:01:54.684226 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 10:01:54.687629 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 10:01:54.690914 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 10:01:54.694597 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 10:01:54.697422 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 10:01:54.700990
6647 10:01:54.704294 CA PerBit enable=1, Macro0, CA PI delay=36
6648 10:01:54.704390
6649 10:01:54.707846 [CBTSetCACLKResult] CA Dly = 36
6650 10:01:54.707933 CS Dly: 1 (0~32)
6651 10:01:54.708000 ==
6652 10:01:54.711341 Dram Type= 6, Freq= 0, CH_1, rank 1
6653 10:01:54.714309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6654 10:01:54.714396 ==
6655 10:01:54.721036 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6656 10:01:54.727887 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6657 10:01:54.731720 [CA 0] Center 36 (8~64) winsize 57
6658 10:01:54.734635 [CA 1] Center 36 (8~64) winsize 57
6659 10:01:54.737947 [CA 2] Center 36 (8~64) winsize 57
6660 10:01:54.738040 [CA 3] Center 36 (8~64) winsize 57
6661 10:01:54.741531 [CA 4] Center 36 (8~64) winsize 57
6662 10:01:54.744658 [CA 5] Center 36 (8~64) winsize 57
6663 10:01:54.744750
6664 10:01:54.751190 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6665 10:01:54.751287
6666 10:01:54.754342 [CATrainingPosCal] consider 2 rank data
6667 10:01:54.757702 u2DelayCellTimex100 = 270/100 ps
6668 10:01:54.761076 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 10:01:54.764731 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 10:01:54.767646 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 10:01:54.771005 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 10:01:54.774290 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 10:01:54.777829 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 10:01:54.777914
6675 10:01:54.780948 CA PerBit enable=1, Macro0, CA PI delay=36
6676 10:01:54.781035
6677 10:01:54.784279 [CBTSetCACLKResult] CA Dly = 36
6678 10:01:54.787773 CS Dly: 1 (0~32)
6679 10:01:54.787860
6680 10:01:54.791272 ----->DramcWriteLeveling(PI) begin...
6681 10:01:54.791386 ==
6682 10:01:54.794468 Dram Type= 6, Freq= 0, CH_1, rank 0
6683 10:01:54.797872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6684 10:01:54.797970 ==
6685 10:01:54.800818 Write leveling (Byte 0): 40 => 8
6686 10:01:54.804408 Write leveling (Byte 1): 40 => 8
6687 10:01:54.807729 DramcWriteLeveling(PI) end<-----
6688 10:01:54.807817
6689 10:01:54.807884 ==
6690 10:01:54.811290 Dram Type= 6, Freq= 0, CH_1, rank 0
6691 10:01:54.814577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6692 10:01:54.814691 ==
6693 10:01:54.817762 [Gating] SW mode calibration
6694 10:01:54.824717 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6695 10:01:54.831039 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6696 10:01:54.834250 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6697 10:01:54.838013 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6698 10:01:54.844826 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6699 10:01:54.847810 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6700 10:01:54.851281 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6701 10:01:54.854519 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6702 10:01:54.861591 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6703 10:01:54.864638 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6704 10:01:54.868437 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6705 10:01:54.871348 Total UI for P1: 0, mck2ui 16
6706 10:01:54.874524 best dqsien dly found for B0: ( 0, 14, 24)
6707 10:01:54.878388 Total UI for P1: 0, mck2ui 16
6708 10:01:54.881197 best dqsien dly found for B1: ( 0, 14, 24)
6709 10:01:54.884743 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6710 10:01:54.888287 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6711 10:01:54.888393
6712 10:01:54.894554 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6713 10:01:54.897862 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6714 10:01:54.901825 [Gating] SW calibration Done
6715 10:01:54.901919 ==
6716 10:01:54.904692 Dram Type= 6, Freq= 0, CH_1, rank 0
6717 10:01:54.908322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 10:01:54.908410 ==
6719 10:01:54.908478 RX Vref Scan: 0
6720 10:01:54.908541
6721 10:01:54.911775 RX Vref 0 -> 0, step: 1
6722 10:01:54.911861
6723 10:01:54.914652 RX Delay -410 -> 252, step: 16
6724 10:01:54.918198 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6725 10:01:54.924798 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6726 10:01:54.928259 iDelay=230, Bit 2, Center -43 (-282 ~ 197) 480
6727 10:01:54.931741 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6728 10:01:54.935014 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6729 10:01:54.937837 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6730 10:01:54.944658 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6731 10:01:54.947967 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6732 10:01:54.951304 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6733 10:01:54.954575 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6734 10:01:54.962000 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6735 10:01:54.965010 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6736 10:01:54.968143 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6737 10:01:54.975017 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6738 10:01:54.978370 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6739 10:01:54.981656 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6740 10:01:54.981768 ==
6741 10:01:54.985127 Dram Type= 6, Freq= 0, CH_1, rank 0
6742 10:01:54.987968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6743 10:01:54.988060 ==
6744 10:01:54.991428 DQS Delay:
6745 10:01:54.991513 DQS0 = 43, DQS1 = 59
6746 10:01:54.995075 DQM Delay:
6747 10:01:54.995169 DQM0 = 12, DQM1 = 16
6748 10:01:54.995238 DQ Delay:
6749 10:01:54.998269 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6750 10:01:55.001612 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6751 10:01:55.004828 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6752 10:01:55.008529 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6753 10:01:55.008617
6754 10:01:55.008684
6755 10:01:55.008745 ==
6756 10:01:55.011726 Dram Type= 6, Freq= 0, CH_1, rank 0
6757 10:01:55.018440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6758 10:01:55.018533 ==
6759 10:01:55.018601
6760 10:01:55.018662
6761 10:01:55.018720 TX Vref Scan disable
6762 10:01:55.021566 == TX Byte 0 ==
6763 10:01:55.024903 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6764 10:01:55.028435 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6765 10:01:55.031677 == TX Byte 1 ==
6766 10:01:55.034913 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6767 10:01:55.037951 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6768 10:01:55.038044 ==
6769 10:01:55.041315 Dram Type= 6, Freq= 0, CH_1, rank 0
6770 10:01:55.048128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6771 10:01:55.048221 ==
6772 10:01:55.048289
6773 10:01:55.048351
6774 10:01:55.048409 TX Vref Scan disable
6775 10:01:55.051708 == TX Byte 0 ==
6776 10:01:55.054776 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6777 10:01:55.058488 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6778 10:01:55.061555 == TX Byte 1 ==
6779 10:01:55.064790 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6780 10:01:55.068494 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6781 10:01:55.068584
6782 10:01:55.071688 [DATLAT]
6783 10:01:55.071774 Freq=400, CH1 RK0
6784 10:01:55.071841
6785 10:01:55.074851 DATLAT Default: 0xf
6786 10:01:55.074945 0, 0xFFFF, sum = 0
6787 10:01:55.078376 1, 0xFFFF, sum = 0
6788 10:01:55.078465 2, 0xFFFF, sum = 0
6789 10:01:55.081844 3, 0xFFFF, sum = 0
6790 10:01:55.081932 4, 0xFFFF, sum = 0
6791 10:01:55.085148 5, 0xFFFF, sum = 0
6792 10:01:55.085235 6, 0xFFFF, sum = 0
6793 10:01:55.088658 7, 0xFFFF, sum = 0
6794 10:01:55.088750 8, 0xFFFF, sum = 0
6795 10:01:55.091639 9, 0xFFFF, sum = 0
6796 10:01:55.091753 10, 0xFFFF, sum = 0
6797 10:01:55.094985 11, 0xFFFF, sum = 0
6798 10:01:55.095077 12, 0xFFFF, sum = 0
6799 10:01:55.098275 13, 0x0, sum = 1
6800 10:01:55.098363 14, 0x0, sum = 2
6801 10:01:55.101762 15, 0x0, sum = 3
6802 10:01:55.101849 16, 0x0, sum = 4
6803 10:01:55.105462 best_step = 14
6804 10:01:55.105563
6805 10:01:55.105661 ==
6806 10:01:55.108646 Dram Type= 6, Freq= 0, CH_1, rank 0
6807 10:01:55.112030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6808 10:01:55.112130 ==
6809 10:01:55.114938 RX Vref Scan: 1
6810 10:01:55.115022
6811 10:01:55.115087 RX Vref 0 -> 0, step: 1
6812 10:01:55.115148
6813 10:01:55.118323 RX Delay -359 -> 252, step: 8
6814 10:01:55.118422
6815 10:01:55.121686 Set Vref, RX VrefLevel [Byte0]: 58
6816 10:01:55.125213 [Byte1]: 52
6817 10:01:55.129898
6818 10:01:55.129999 Final RX Vref Byte 0 = 58 to rank0
6819 10:01:55.132902 Final RX Vref Byte 1 = 52 to rank0
6820 10:01:55.136307 Final RX Vref Byte 0 = 58 to rank1
6821 10:01:55.139813 Final RX Vref Byte 1 = 52 to rank1==
6822 10:01:55.142823 Dram Type= 6, Freq= 0, CH_1, rank 0
6823 10:01:55.146253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6824 10:01:55.149761 ==
6825 10:01:55.149878 DQS Delay:
6826 10:01:55.149943 DQS0 = 48, DQS1 = 60
6827 10:01:55.153080 DQM Delay:
6828 10:01:55.153169 DQM0 = 11, DQM1 = 12
6829 10:01:55.156442 DQ Delay:
6830 10:01:55.159746 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6831 10:01:55.159833 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6832 10:01:55.163106 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6833 10:01:55.166605 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6834 10:01:55.166692
6835 10:01:55.166757
6836 10:01:55.176212 [DQSOSCAuto] RK0, (LSB)MR18= 0x8b33, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6837 10:01:55.179521 CH1 RK0: MR19=C0C, MR18=8B33
6838 10:01:55.186528 CH1_RK0: MR19=0xC0C, MR18=0x8B33, DQSOSC=392, MR23=63, INC=384, DEC=256
6839 10:01:55.186623 ==
6840 10:01:55.189612 Dram Type= 6, Freq= 0, CH_1, rank 1
6841 10:01:55.193168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6842 10:01:55.193260 ==
6843 10:01:55.196228 [Gating] SW mode calibration
6844 10:01:55.203570 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6845 10:01:55.206071 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6846 10:01:55.212969 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6847 10:01:55.216548 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6848 10:01:55.219884 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6849 10:01:55.226269 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6850 10:01:55.229416 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6851 10:01:55.233031 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6852 10:01:55.239795 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6853 10:01:55.242655 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6854 10:01:55.246115 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6855 10:01:55.249511 Total UI for P1: 0, mck2ui 16
6856 10:01:55.252974 best dqsien dly found for B0: ( 0, 14, 24)
6857 10:01:55.256206 Total UI for P1: 0, mck2ui 16
6858 10:01:55.259741 best dqsien dly found for B1: ( 0, 14, 24)
6859 10:01:55.263237 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6860 10:01:55.266670 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6861 10:01:55.266748
6862 10:01:55.272874 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6863 10:01:55.276344 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6864 10:01:55.276422 [Gating] SW calibration Done
6865 10:01:55.279656 ==
6866 10:01:55.279733 Dram Type= 6, Freq= 0, CH_1, rank 1
6867 10:01:55.286806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6868 10:01:55.286892 ==
6869 10:01:55.286974 RX Vref Scan: 0
6870 10:01:55.287037
6871 10:01:55.290110 RX Vref 0 -> 0, step: 1
6872 10:01:55.290181
6873 10:01:55.293088 RX Delay -410 -> 252, step: 16
6874 10:01:55.296321 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6875 10:01:55.299625 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6876 10:01:55.306153 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6877 10:01:55.309738 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6878 10:01:55.312748 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6879 10:01:55.316088 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6880 10:01:55.323105 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6881 10:01:55.326567 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6882 10:01:55.329426 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6883 10:01:55.333479 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6884 10:01:55.339666 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6885 10:01:55.343151 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6886 10:01:55.346769 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6887 10:01:55.349667 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6888 10:01:55.356620 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6889 10:01:55.359851 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6890 10:01:55.359954 ==
6891 10:01:55.363345 Dram Type= 6, Freq= 0, CH_1, rank 1
6892 10:01:55.366783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6893 10:01:55.366891 ==
6894 10:01:55.370094 DQS Delay:
6895 10:01:55.370195 DQS0 = 43, DQS1 = 59
6896 10:01:55.372993 DQM Delay:
6897 10:01:55.373068 DQM0 = 9, DQM1 = 20
6898 10:01:55.373131 DQ Delay:
6899 10:01:55.376700 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6900 10:01:55.379953 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6901 10:01:55.383418 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6902 10:01:55.386658 DQ12 =24, DQ13 =32, DQ14 =32, DQ15 =32
6903 10:01:55.386760
6904 10:01:55.386850
6905 10:01:55.386941 ==
6906 10:01:55.389673 Dram Type= 6, Freq= 0, CH_1, rank 1
6907 10:01:55.393346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6908 10:01:55.396518 ==
6909 10:01:55.396598
6910 10:01:55.396661
6911 10:01:55.396721 TX Vref Scan disable
6912 10:01:55.399886 == TX Byte 0 ==
6913 10:01:55.403423 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6914 10:01:55.406302 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6915 10:01:55.409892 == TX Byte 1 ==
6916 10:01:55.413067 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6917 10:01:55.417172 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6918 10:01:55.417255 ==
6919 10:01:55.419772 Dram Type= 6, Freq= 0, CH_1, rank 1
6920 10:01:55.423230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6921 10:01:55.423306 ==
6922 10:01:55.423368
6923 10:01:55.426497
6924 10:01:55.426572 TX Vref Scan disable
6925 10:01:55.429930 == TX Byte 0 ==
6926 10:01:55.433110 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6927 10:01:55.436470 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6928 10:01:55.439703 == TX Byte 1 ==
6929 10:01:55.443288 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6930 10:01:55.446394 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6931 10:01:55.446484
6932 10:01:55.446575 [DATLAT]
6933 10:01:55.449980 Freq=400, CH1 RK1
6934 10:01:55.450052
6935 10:01:55.450113 DATLAT Default: 0xe
6936 10:01:55.453300 0, 0xFFFF, sum = 0
6937 10:01:55.453373 1, 0xFFFF, sum = 0
6938 10:01:55.456730 2, 0xFFFF, sum = 0
6939 10:01:55.456802 3, 0xFFFF, sum = 0
6940 10:01:55.460103 4, 0xFFFF, sum = 0
6941 10:01:55.463575 5, 0xFFFF, sum = 0
6942 10:01:55.463652 6, 0xFFFF, sum = 0
6943 10:01:55.466836 7, 0xFFFF, sum = 0
6944 10:01:55.466923 8, 0xFFFF, sum = 0
6945 10:01:55.470118 9, 0xFFFF, sum = 0
6946 10:01:55.470225 10, 0xFFFF, sum = 0
6947 10:01:55.473422 11, 0xFFFF, sum = 0
6948 10:01:55.473530 12, 0xFFFF, sum = 0
6949 10:01:55.477008 13, 0x0, sum = 1
6950 10:01:55.477081 14, 0x0, sum = 2
6951 10:01:55.480240 15, 0x0, sum = 3
6952 10:01:55.480325 16, 0x0, sum = 4
6953 10:01:55.480388 best_step = 14
6954 10:01:55.483718
6955 10:01:55.483803 ==
6956 10:01:55.487124 Dram Type= 6, Freq= 0, CH_1, rank 1
6957 10:01:55.490392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6958 10:01:55.490467 ==
6959 10:01:55.490530 RX Vref Scan: 0
6960 10:01:55.490589
6961 10:01:55.493604 RX Vref 0 -> 0, step: 1
6962 10:01:55.493710
6963 10:01:55.497048 RX Delay -359 -> 252, step: 8
6964 10:01:55.504024 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6965 10:01:55.507624 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6966 10:01:55.510521 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6967 10:01:55.513818 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6968 10:01:55.520712 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6969 10:01:55.524106 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6970 10:01:55.527619 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6971 10:01:55.530621 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6972 10:01:55.537259 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6973 10:01:55.540475 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6974 10:01:55.543969 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6975 10:01:55.547053 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6976 10:01:55.554257 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6977 10:01:55.557044 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6978 10:01:55.560575 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6979 10:01:55.567452 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6980 10:01:55.567536 ==
6981 10:01:55.570348 Dram Type= 6, Freq= 0, CH_1, rank 1
6982 10:01:55.573942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6983 10:01:55.574045 ==
6984 10:01:55.574145 DQS Delay:
6985 10:01:55.577078 DQS0 = 52, DQS1 = 60
6986 10:01:55.577151 DQM Delay:
6987 10:01:55.580499 DQM0 = 13, DQM1 = 12
6988 10:01:55.580574 DQ Delay:
6989 10:01:55.583928 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6990 10:01:55.586952 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6991 10:01:55.590323 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =4
6992 10:01:55.593735 DQ12 =16, DQ13 =20, DQ14 =20, DQ15 =20
6993 10:01:55.593847
6994 10:01:55.593941
6995 10:01:55.600414 [DQSOSCAuto] RK1, (LSB)MR18= 0x788f, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 394 ps
6996 10:01:55.603853 CH1 RK1: MR19=C0C, MR18=788F
6997 10:01:55.610708 CH1_RK1: MR19=0xC0C, MR18=0x788F, DQSOSC=391, MR23=63, INC=386, DEC=257
6998 10:01:55.613604 [RxdqsGatingPostProcess] freq 400
6999 10:01:55.616994 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7000 10:01:55.620603 best DQS0 dly(2T, 0.5T) = (0, 10)
7001 10:01:55.623734 best DQS1 dly(2T, 0.5T) = (0, 10)
7002 10:01:55.627109 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7003 10:01:55.630488 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7004 10:01:55.633938 best DQS0 dly(2T, 0.5T) = (0, 10)
7005 10:01:55.636918 best DQS1 dly(2T, 0.5T) = (0, 10)
7006 10:01:55.640830 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7007 10:01:55.643779 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7008 10:01:55.647148 Pre-setting of DQS Precalculation
7009 10:01:55.650528 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7010 10:01:55.660245 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7011 10:01:55.667274 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7012 10:01:55.667375
7013 10:01:55.667442
7014 10:01:55.670189 [Calibration Summary] 800 Mbps
7015 10:01:55.670274 CH 0, Rank 0
7016 10:01:55.673482 SW Impedance : PASS
7017 10:01:55.673568 DUTY Scan : NO K
7018 10:01:55.677368 ZQ Calibration : PASS
7019 10:01:55.680697 Jitter Meter : NO K
7020 10:01:55.680784 CBT Training : PASS
7021 10:01:55.684083 Write leveling : PASS
7022 10:01:55.687351 RX DQS gating : PASS
7023 10:01:55.687436 RX DQ/DQS(RDDQC) : PASS
7024 10:01:55.690670 TX DQ/DQS : PASS
7025 10:01:55.693556 RX DATLAT : PASS
7026 10:01:55.693701 RX DQ/DQS(Engine): PASS
7027 10:01:55.697059 TX OE : NO K
7028 10:01:55.697148 All Pass.
7029 10:01:55.697229
7030 10:01:55.700414 CH 0, Rank 1
7031 10:01:55.700493 SW Impedance : PASS
7032 10:01:55.704154 DUTY Scan : NO K
7033 10:01:55.704259 ZQ Calibration : PASS
7034 10:01:55.706769 Jitter Meter : NO K
7035 10:01:55.710301 CBT Training : PASS
7036 10:01:55.710433 Write leveling : NO K
7037 10:01:55.713729 RX DQS gating : PASS
7038 10:01:55.717198 RX DQ/DQS(RDDQC) : PASS
7039 10:01:55.717316 TX DQ/DQS : PASS
7040 10:01:55.720222 RX DATLAT : PASS
7041 10:01:55.723763 RX DQ/DQS(Engine): PASS
7042 10:01:55.723860 TX OE : NO K
7043 10:01:55.727277 All Pass.
7044 10:01:55.727402
7045 10:01:55.727495 CH 1, Rank 0
7046 10:01:55.730474 SW Impedance : PASS
7047 10:01:55.730552 DUTY Scan : NO K
7048 10:01:55.733672 ZQ Calibration : PASS
7049 10:01:55.736879 Jitter Meter : NO K
7050 10:01:55.736959 CBT Training : PASS
7051 10:01:55.740564 Write leveling : PASS
7052 10:01:55.740649 RX DQS gating : PASS
7053 10:01:55.743524 RX DQ/DQS(RDDQC) : PASS
7054 10:01:55.747288 TX DQ/DQS : PASS
7055 10:01:55.747381 RX DATLAT : PASS
7056 10:01:55.750567 RX DQ/DQS(Engine): PASS
7057 10:01:55.753781 TX OE : NO K
7058 10:01:55.753861 All Pass.
7059 10:01:55.753926
7060 10:01:55.754027 CH 1, Rank 1
7061 10:01:55.757372 SW Impedance : PASS
7062 10:01:55.760719 DUTY Scan : NO K
7063 10:01:55.760800 ZQ Calibration : PASS
7064 10:01:55.763928 Jitter Meter : NO K
7065 10:01:55.767255 CBT Training : PASS
7066 10:01:55.767347 Write leveling : NO K
7067 10:01:55.770623 RX DQS gating : PASS
7068 10:01:55.773443 RX DQ/DQS(RDDQC) : PASS
7069 10:01:55.773529 TX DQ/DQS : PASS
7070 10:01:55.776955 RX DATLAT : PASS
7071 10:01:55.780872 RX DQ/DQS(Engine): PASS
7072 10:01:55.780983 TX OE : NO K
7073 10:01:55.781078 All Pass.
7074 10:01:55.781180
7075 10:01:55.783873 DramC Write-DBI off
7076 10:01:55.787284 PER_BANK_REFRESH: Hybrid Mode
7077 10:01:55.787363 TX_TRACKING: ON
7078 10:01:55.797001 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7079 10:01:55.800447 [FAST_K] Save calibration result to emmc
7080 10:01:55.803830 dramc_set_vcore_voltage set vcore to 725000
7081 10:01:55.807640 Read voltage for 1600, 0
7082 10:01:55.807737 Vio18 = 0
7083 10:01:55.810508 Vcore = 725000
7084 10:01:55.810614 Vdram = 0
7085 10:01:55.810716 Vddq = 0
7086 10:01:55.810822 Vmddr = 0
7087 10:01:55.817029 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7088 10:01:55.820547 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7089 10:01:55.824173 MEM_TYPE=3, freq_sel=13
7090 10:01:55.827553 sv_algorithm_assistance_LP4_3733
7091 10:01:55.830986 ============ PULL DRAM RESETB DOWN ============
7092 10:01:55.834447 ========== PULL DRAM RESETB DOWN end =========
7093 10:01:55.840863 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7094 10:01:55.844444 ===================================
7095 10:01:55.847340 LPDDR4 DRAM CONFIGURATION
7096 10:01:55.851030 ===================================
7097 10:01:55.851124 EX_ROW_EN[0] = 0x0
7098 10:01:55.853822 EX_ROW_EN[1] = 0x0
7099 10:01:55.853932 LP4Y_EN = 0x0
7100 10:01:55.857220 WORK_FSP = 0x1
7101 10:01:55.857302 WL = 0x5
7102 10:01:55.860987 RL = 0x5
7103 10:01:55.861076 BL = 0x2
7104 10:01:55.863846 RPST = 0x0
7105 10:01:55.863940 RD_PRE = 0x0
7106 10:01:55.867640 WR_PRE = 0x1
7107 10:01:55.867732 WR_PST = 0x1
7108 10:01:55.871064 DBI_WR = 0x0
7109 10:01:55.871143 DBI_RD = 0x0
7110 10:01:55.873905 OTF = 0x1
7111 10:01:55.877758 ===================================
7112 10:01:55.880902 ===================================
7113 10:01:55.881011 ANA top config
7114 10:01:55.884465 ===================================
7115 10:01:55.887446 DLL_ASYNC_EN = 0
7116 10:01:55.890802 ALL_SLAVE_EN = 0
7117 10:01:55.894264 NEW_RANK_MODE = 1
7118 10:01:55.894401 DLL_IDLE_MODE = 1
7119 10:01:55.897763 LP45_APHY_COMB_EN = 1
7120 10:01:55.900614 TX_ODT_DIS = 0
7121 10:01:55.904543 NEW_8X_MODE = 1
7122 10:01:55.907430 ===================================
7123 10:01:55.911457 ===================================
7124 10:01:55.914160 data_rate = 3200
7125 10:01:55.914236 CKR = 1
7126 10:01:55.917752 DQ_P2S_RATIO = 8
7127 10:01:55.920734 ===================================
7128 10:01:55.924232 CA_P2S_RATIO = 8
7129 10:01:55.927375 DQ_CA_OPEN = 0
7130 10:01:55.931076 DQ_SEMI_OPEN = 0
7131 10:01:55.931158 CA_SEMI_OPEN = 0
7132 10:01:55.934365 CA_FULL_RATE = 0
7133 10:01:55.937941 DQ_CKDIV4_EN = 0
7134 10:01:55.941118 CA_CKDIV4_EN = 0
7135 10:01:55.944275 CA_PREDIV_EN = 0
7136 10:01:55.947689 PH8_DLY = 12
7137 10:01:55.947797 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7138 10:01:55.950845 DQ_AAMCK_DIV = 4
7139 10:01:55.954499 CA_AAMCK_DIV = 4
7140 10:01:55.958039 CA_ADMCK_DIV = 4
7141 10:01:55.961038 DQ_TRACK_CA_EN = 0
7142 10:01:55.964254 CA_PICK = 1600
7143 10:01:55.967772 CA_MCKIO = 1600
7144 10:01:55.967886 MCKIO_SEMI = 0
7145 10:01:55.971521 PLL_FREQ = 3068
7146 10:01:55.974434 DQ_UI_PI_RATIO = 32
7147 10:01:55.977737 CA_UI_PI_RATIO = 0
7148 10:01:55.980858 ===================================
7149 10:01:55.984258 ===================================
7150 10:01:55.987644 memory_type:LPDDR4
7151 10:01:55.987743 GP_NUM : 10
7152 10:01:55.991054 SRAM_EN : 1
7153 10:01:55.991138 MD32_EN : 0
7154 10:01:55.994689 ===================================
7155 10:01:55.997574 [ANA_INIT] >>>>>>>>>>>>>>
7156 10:01:56.001017 <<<<<< [CONFIGURE PHASE]: ANA_TX
7157 10:01:56.004433 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7158 10:01:56.008460 ===================================
7159 10:01:56.011019 data_rate = 3200,PCW = 0X7600
7160 10:01:56.014418 ===================================
7161 10:01:56.017921 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7162 10:01:56.024273 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7163 10:01:56.027854 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7164 10:01:56.034033 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7165 10:01:56.037606 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7166 10:01:56.040707 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7167 10:01:56.040794 [ANA_INIT] flow start
7168 10:01:56.044407 [ANA_INIT] PLL >>>>>>>>
7169 10:01:56.047757 [ANA_INIT] PLL <<<<<<<<
7170 10:01:56.047849 [ANA_INIT] MIDPI >>>>>>>>
7171 10:01:56.051170 [ANA_INIT] MIDPI <<<<<<<<
7172 10:01:56.054015 [ANA_INIT] DLL >>>>>>>>
7173 10:01:56.054099 [ANA_INIT] DLL <<<<<<<<
7174 10:01:56.057379 [ANA_INIT] flow end
7175 10:01:56.061152 ============ LP4 DIFF to SE enter ============
7176 10:01:56.064245 ============ LP4 DIFF to SE exit ============
7177 10:01:56.067807 [ANA_INIT] <<<<<<<<<<<<<
7178 10:01:56.071119 [Flow] Enable top DCM control >>>>>
7179 10:01:56.074267 [Flow] Enable top DCM control <<<<<
7180 10:01:56.077696 Enable DLL master slave shuffle
7181 10:01:56.084418 ==============================================================
7182 10:01:56.084534 Gating Mode config
7183 10:01:56.091259 ==============================================================
7184 10:01:56.091374 Config description:
7185 10:01:56.100854 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7186 10:01:56.107733 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7187 10:01:56.114524 SELPH_MODE 0: By rank 1: By Phase
7188 10:01:56.117742 ==============================================================
7189 10:01:56.121172 GAT_TRACK_EN = 1
7190 10:01:56.124054 RX_GATING_MODE = 2
7191 10:01:56.127514 RX_GATING_TRACK_MODE = 2
7192 10:01:56.130829 SELPH_MODE = 1
7193 10:01:56.134422 PICG_EARLY_EN = 1
7194 10:01:56.137360 VALID_LAT_VALUE = 1
7195 10:01:56.144340 ==============================================================
7196 10:01:56.148030 Enter into Gating configuration >>>>
7197 10:01:56.151031 Exit from Gating configuration <<<<
7198 10:01:56.151110 Enter into DVFS_PRE_config >>>>>
7199 10:01:56.164497 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7200 10:01:56.168118 Exit from DVFS_PRE_config <<<<<
7201 10:01:56.170967 Enter into PICG configuration >>>>
7202 10:01:56.174217 Exit from PICG configuration <<<<
7203 10:01:56.174306 [RX_INPUT] configuration >>>>>
7204 10:01:56.177757 [RX_INPUT] configuration <<<<<
7205 10:01:56.184737 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7206 10:01:56.187898 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7207 10:01:56.194904 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7208 10:01:56.201344 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7209 10:01:56.207988 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7210 10:01:56.214813 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7211 10:01:56.218262 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7212 10:01:56.221665 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7213 10:01:56.224831 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7214 10:01:56.231640 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7215 10:01:56.234661 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7216 10:01:56.238333 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7217 10:01:56.242122 ===================================
7218 10:01:56.245038 LPDDR4 DRAM CONFIGURATION
7219 10:01:56.247986 ===================================
7220 10:01:56.248073 EX_ROW_EN[0] = 0x0
7221 10:01:56.251393 EX_ROW_EN[1] = 0x0
7222 10:01:56.255281 LP4Y_EN = 0x0
7223 10:01:56.255372 WORK_FSP = 0x1
7224 10:01:56.258426 WL = 0x5
7225 10:01:56.258543 RL = 0x5
7226 10:01:56.261742 BL = 0x2
7227 10:01:56.261862 RPST = 0x0
7228 10:01:56.265081 RD_PRE = 0x0
7229 10:01:56.265182 WR_PRE = 0x1
7230 10:01:56.268292 WR_PST = 0x1
7231 10:01:56.268413 DBI_WR = 0x0
7232 10:01:56.271620 DBI_RD = 0x0
7233 10:01:56.271740 OTF = 0x1
7234 10:01:56.274990 ===================================
7235 10:01:56.278343 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7236 10:01:56.284823 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7237 10:01:56.288134 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7238 10:01:56.291421 ===================================
7239 10:01:56.295526 LPDDR4 DRAM CONFIGURATION
7240 10:01:56.298103 ===================================
7241 10:01:56.298187 EX_ROW_EN[0] = 0x10
7242 10:01:56.301505 EX_ROW_EN[1] = 0x0
7243 10:01:56.301621 LP4Y_EN = 0x0
7244 10:01:56.305001 WORK_FSP = 0x1
7245 10:01:56.305112 WL = 0x5
7246 10:01:56.308456 RL = 0x5
7247 10:01:56.308563 BL = 0x2
7248 10:01:56.311509 RPST = 0x0
7249 10:01:56.311613 RD_PRE = 0x0
7250 10:01:56.314738 WR_PRE = 0x1
7251 10:01:56.314845 WR_PST = 0x1
7252 10:01:56.318349 DBI_WR = 0x0
7253 10:01:56.321685 DBI_RD = 0x0
7254 10:01:56.321795 OTF = 0x1
7255 10:01:56.324853 ===================================
7256 10:01:56.331388 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7257 10:01:56.331499 ==
7258 10:01:56.335063 Dram Type= 6, Freq= 0, CH_0, rank 0
7259 10:01:56.337949 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7260 10:01:56.338029 ==
7261 10:01:56.341512 [Duty_Offset_Calibration]
7262 10:01:56.341618 B0:2 B1:-1 CA:1
7263 10:01:56.341710
7264 10:01:56.344981 [DutyScan_Calibration_Flow] k_type=0
7265 10:01:56.355121
7266 10:01:56.355217 ==CLK 0==
7267 10:01:56.358712 Final CLK duty delay cell = -4
7268 10:01:56.362298 [-4] MAX Duty = 5031%(X100), DQS PI = 6
7269 10:01:56.365183 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7270 10:01:56.368710 [-4] AVG Duty = 4937%(X100)
7271 10:01:56.368813
7272 10:01:56.372103 CH0 CLK Duty spec in!! Max-Min= 187%
7273 10:01:56.375305 [DutyScan_Calibration_Flow] ====Done====
7274 10:01:56.375397
7275 10:01:56.378536 [DutyScan_Calibration_Flow] k_type=1
7276 10:01:56.394802
7277 10:01:56.394952 ==DQS 0 ==
7278 10:01:56.398704 Final DQS duty delay cell = 0
7279 10:01:56.401207 [0] MAX Duty = 5125%(X100), DQS PI = 20
7280 10:01:56.404926 [0] MIN Duty = 5000%(X100), DQS PI = 14
7281 10:01:56.407885 [0] AVG Duty = 5062%(X100)
7282 10:01:56.407971
7283 10:01:56.408038 ==DQS 1 ==
7284 10:01:56.411188 Final DQS duty delay cell = -4
7285 10:01:56.414566 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7286 10:01:56.417971 [-4] MIN Duty = 5000%(X100), DQS PI = 42
7287 10:01:56.421456 [-4] AVG Duty = 5046%(X100)
7288 10:01:56.421541
7289 10:01:56.424786 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7290 10:01:56.424872
7291 10:01:56.428481 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7292 10:01:56.431172 [DutyScan_Calibration_Flow] ====Done====
7293 10:01:56.431252
7294 10:01:56.434873 [DutyScan_Calibration_Flow] k_type=3
7295 10:01:56.452117
7296 10:01:56.452265 ==DQM 0 ==
7297 10:01:56.455479 Final DQM duty delay cell = 0
7298 10:01:56.458742 [0] MAX Duty = 5000%(X100), DQS PI = 18
7299 10:01:56.462211 [0] MIN Duty = 4875%(X100), DQS PI = 6
7300 10:01:56.462323 [0] AVG Duty = 4937%(X100)
7301 10:01:56.465171
7302 10:01:56.465280 ==DQM 1 ==
7303 10:01:56.468635 Final DQM duty delay cell = 0
7304 10:01:56.472213 [0] MAX Duty = 5218%(X100), DQS PI = 58
7305 10:01:56.475522 [0] MIN Duty = 4969%(X100), DQS PI = 20
7306 10:01:56.475628 [0] AVG Duty = 5093%(X100)
7307 10:01:56.478744
7308 10:01:56.481997 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7309 10:01:56.482078
7310 10:01:56.485245 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7311 10:01:56.488828 [DutyScan_Calibration_Flow] ====Done====
7312 10:01:56.488938
7313 10:01:56.492098 [DutyScan_Calibration_Flow] k_type=2
7314 10:01:56.508241
7315 10:01:56.508375 ==DQ 0 ==
7316 10:01:56.511678 Final DQ duty delay cell = -4
7317 10:01:56.514823 [-4] MAX Duty = 5000%(X100), DQS PI = 0
7318 10:01:56.518482 [-4] MIN Duty = 4844%(X100), DQS PI = 14
7319 10:01:56.521474 [-4] AVG Duty = 4922%(X100)
7320 10:01:56.521579
7321 10:01:56.521671 ==DQ 1 ==
7322 10:01:56.524882 Final DQ duty delay cell = 0
7323 10:01:56.528409 [0] MAX Duty = 5031%(X100), DQS PI = 30
7324 10:01:56.531551 [0] MIN Duty = 4938%(X100), DQS PI = 2
7325 10:01:56.531636 [0] AVG Duty = 4984%(X100)
7326 10:01:56.535320
7327 10:01:56.538660 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7328 10:01:56.538745
7329 10:01:56.541529 CH0 DQ 1 Duty spec in!! Max-Min= 93%
7330 10:01:56.544975 [DutyScan_Calibration_Flow] ====Done====
7331 10:01:56.545059 ==
7332 10:01:56.548169 Dram Type= 6, Freq= 0, CH_1, rank 0
7333 10:01:56.551651 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7334 10:01:56.551737 ==
7335 10:01:56.554833 [Duty_Offset_Calibration]
7336 10:01:56.554941 B0:1 B1:1 CA:2
7337 10:01:56.555017
7338 10:01:56.558274 [DutyScan_Calibration_Flow] k_type=0
7339 10:01:56.568426
7340 10:01:56.568546 ==CLK 0==
7341 10:01:56.572042 Final CLK duty delay cell = 0
7342 10:01:56.575576 [0] MAX Duty = 5156%(X100), DQS PI = 24
7343 10:01:56.578384 [0] MIN Duty = 4938%(X100), DQS PI = 50
7344 10:01:56.578463 [0] AVG Duty = 5047%(X100)
7345 10:01:56.581947
7346 10:01:56.585616 CH1 CLK Duty spec in!! Max-Min= 218%
7347 10:01:56.588433 [DutyScan_Calibration_Flow] ====Done====
7348 10:01:56.588538
7349 10:01:56.591621 [DutyScan_Calibration_Flow] k_type=1
7350 10:01:56.608185
7351 10:01:56.608330 ==DQS 0 ==
7352 10:01:56.611705 Final DQS duty delay cell = 0
7353 10:01:56.615245 [0] MAX Duty = 5062%(X100), DQS PI = 22
7354 10:01:56.618403 [0] MIN Duty = 4813%(X100), DQS PI = 52
7355 10:01:56.621465 [0] AVG Duty = 4937%(X100)
7356 10:01:56.621550
7357 10:01:56.621615 ==DQS 1 ==
7358 10:01:56.624695 Final DQS duty delay cell = 0
7359 10:01:56.628342 [0] MAX Duty = 5031%(X100), DQS PI = 34
7360 10:01:56.631447 [0] MIN Duty = 4938%(X100), DQS PI = 12
7361 10:01:56.634958 [0] AVG Duty = 4984%(X100)
7362 10:01:56.635045
7363 10:01:56.638402 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7364 10:01:56.638486
7365 10:01:56.641849 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7366 10:01:56.645321 [DutyScan_Calibration_Flow] ====Done====
7367 10:01:56.645407
7368 10:01:56.648204 [DutyScan_Calibration_Flow] k_type=3
7369 10:01:56.665121
7370 10:01:56.665236 ==DQM 0 ==
7371 10:01:56.668721 Final DQM duty delay cell = 0
7372 10:01:56.671673 [0] MAX Duty = 5156%(X100), DQS PI = 20
7373 10:01:56.675205 [0] MIN Duty = 4844%(X100), DQS PI = 50
7374 10:01:56.675291 [0] AVG Duty = 5000%(X100)
7375 10:01:56.678787
7376 10:01:56.678880 ==DQM 1 ==
7377 10:01:56.681624 Final DQM duty delay cell = 0
7378 10:01:56.685640 [0] MAX Duty = 5156%(X100), DQS PI = 60
7379 10:01:56.688399 [0] MIN Duty = 4907%(X100), DQS PI = 20
7380 10:01:56.688482 [0] AVG Duty = 5031%(X100)
7381 10:01:56.692233
7382 10:01:56.695257 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7383 10:01:56.695379
7384 10:01:56.698881 CH1 DQM 1 Duty spec in!! Max-Min= 249%
7385 10:01:56.702113 [DutyScan_Calibration_Flow] ====Done====
7386 10:01:56.702222
7387 10:01:56.705356 [DutyScan_Calibration_Flow] k_type=2
7388 10:01:56.721900
7389 10:01:56.722035 ==DQ 0 ==
7390 10:01:56.725562 Final DQ duty delay cell = 0
7391 10:01:56.728462 [0] MAX Duty = 5156%(X100), DQS PI = 22
7392 10:01:56.731797 [0] MIN Duty = 4907%(X100), DQS PI = 52
7393 10:01:56.731894 [0] AVG Duty = 5031%(X100)
7394 10:01:56.735420
7395 10:01:56.735527 ==DQ 1 ==
7396 10:01:56.738580 Final DQ duty delay cell = 0
7397 10:01:56.741862 [0] MAX Duty = 5093%(X100), DQS PI = 6
7398 10:01:56.745338 [0] MIN Duty = 5031%(X100), DQS PI = 0
7399 10:01:56.745446 [0] AVG Duty = 5062%(X100)
7400 10:01:56.745548
7401 10:01:56.748835 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7402 10:01:56.748939
7403 10:01:56.751795 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7404 10:01:56.758621 [DutyScan_Calibration_Flow] ====Done====
7405 10:01:56.761704 nWR fixed to 30
7406 10:01:56.761814 [ModeRegInit_LP4] CH0 RK0
7407 10:01:56.765233 [ModeRegInit_LP4] CH0 RK1
7408 10:01:56.768507 [ModeRegInit_LP4] CH1 RK0
7409 10:01:56.768601 [ModeRegInit_LP4] CH1 RK1
7410 10:01:56.772269 match AC timing 5
7411 10:01:56.775441 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7412 10:01:56.778333 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7413 10:01:56.785018 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7414 10:01:56.788579 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7415 10:01:56.795037 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7416 10:01:56.795131 [MiockJmeterHQA]
7417 10:01:56.795199
7418 10:01:56.798448 [DramcMiockJmeter] u1RxGatingPI = 0
7419 10:01:56.798541 0 : 4368, 4140
7420 10:01:56.801778 4 : 4363, 4138
7421 10:01:56.801867 8 : 4363, 4138
7422 10:01:56.805489 12 : 4255, 4030
7423 10:01:56.805576 16 : 4252, 4027
7424 10:01:56.808868 20 : 4252, 4027
7425 10:01:56.808954 24 : 4255, 4030
7426 10:01:56.812303 28 : 4363, 4137
7427 10:01:56.812389 32 : 4363, 4138
7428 10:01:56.812458 36 : 4255, 4027
7429 10:01:56.815485 40 : 4258, 4029
7430 10:01:56.815598 44 : 4253, 4026
7431 10:01:56.819217 48 : 4254, 4029
7432 10:01:56.819348 52 : 4253, 4027
7433 10:01:56.821966 56 : 4255, 4029
7434 10:01:56.822053 60 : 4254, 4029
7435 10:01:56.822150 64 : 4252, 4027
7436 10:01:56.825594 68 : 4250, 4027
7437 10:01:56.825679 72 : 4252, 4029
7438 10:01:56.828711 76 : 4254, 4029
7439 10:01:56.828798 80 : 4250, 4027
7440 10:01:56.832055 84 : 4361, 4137
7441 10:01:56.832142 88 : 4249, 4027
7442 10:01:56.835235 92 : 4255, 4029
7443 10:01:56.835322 96 : 4255, 3295
7444 10:01:56.835389 100 : 4254, 0
7445 10:01:56.838623 104 : 4255, 0
7446 10:01:56.838709 108 : 4253, 0
7447 10:01:56.842501 112 : 4255, 0
7448 10:01:56.842649 116 : 4255, 0
7449 10:01:56.842746 120 : 4252, 0
7450 10:01:56.845410 124 : 4250, 0
7451 10:01:56.845497 128 : 4252, 0
7452 10:01:56.845566 132 : 4252, 0
7453 10:01:56.848579 136 : 4255, 0
7454 10:01:56.848664 140 : 4363, 0
7455 10:01:56.851871 144 : 4250, 0
7456 10:01:56.851958 148 : 4250, 0
7457 10:01:56.852026 152 : 4252, 0
7458 10:01:56.855388 156 : 4249, 0
7459 10:01:56.855474 160 : 4250, 0
7460 10:01:56.858832 164 : 4254, 0
7461 10:01:56.858926 168 : 4250, 0
7462 10:01:56.858994 172 : 4361, 0
7463 10:01:56.861894 176 : 4365, 0
7464 10:01:56.861979 180 : 4250, 0
7465 10:01:56.865226 184 : 4250, 0
7466 10:01:56.865312 188 : 4250, 0
7467 10:01:56.865379 192 : 4365, 0
7468 10:01:56.868907 196 : 4250, 0
7469 10:01:56.868993 200 : 4250, 0
7470 10:01:56.869060 204 : 4249, 0
7471 10:01:56.872028 208 : 4255, 0
7472 10:01:56.872123 212 : 4250, 107
7473 10:01:56.875196 216 : 4255, 3723
7474 10:01:56.875279 220 : 4368, 4145
7475 10:01:56.878604 224 : 4250, 4026
7476 10:01:56.878690 228 : 4250, 4027
7477 10:01:56.881883 232 : 4257, 4032
7478 10:01:56.881966 236 : 4253, 4029
7479 10:01:56.885229 240 : 4363, 4140
7480 10:01:56.885312 244 : 4361, 4137
7481 10:01:56.888478 248 : 4250, 4027
7482 10:01:56.888578 252 : 4365, 4142
7483 10:01:56.888645 256 : 4366, 4140
7484 10:01:56.891671 260 : 4361, 4138
7485 10:01:56.891796 264 : 4250, 4027
7486 10:01:56.895582 268 : 4255, 4029
7487 10:01:56.895707 272 : 4253, 4029
7488 10:01:56.899042 276 : 4252, 4029
7489 10:01:56.899129 280 : 4361, 4137
7490 10:01:56.901868 284 : 4361, 4137
7491 10:01:56.901953 288 : 4250, 4026
7492 10:01:56.905453 292 : 4253, 4026
7493 10:01:56.905569 296 : 4360, 4137
7494 10:01:56.908420 300 : 4250, 4027
7495 10:01:56.908523 304 : 4363, 4139
7496 10:01:56.908614 308 : 4253, 4029
7497 10:01:56.911958 312 : 4250, 4027
7498 10:01:56.912058 316 : 4363, 4140
7499 10:01:56.915472 320 : 4250, 4026
7500 10:01:56.915549 324 : 4361, 4137
7501 10:01:56.918832 328 : 4366, 4140
7502 10:01:56.918953 332 : 4250, 2834
7503 10:01:56.922369 336 : 4250, 23
7504 10:01:56.922470
7505 10:01:56.922562 MIOCK jitter meter ch=0
7506 10:01:56.922649
7507 10:01:56.925487 1T = (336-100) = 236 dly cells
7508 10:01:56.932261 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7509 10:01:56.932370 ==
7510 10:01:56.935320 Dram Type= 6, Freq= 0, CH_0, rank 0
7511 10:01:56.938450 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7512 10:01:56.938553 ==
7513 10:01:56.945367 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7514 10:01:56.948724 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7515 10:01:56.952208 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7516 10:01:56.958687 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7517 10:01:56.968508 [CA 0] Center 44 (14~75) winsize 62
7518 10:01:56.971845 [CA 1] Center 44 (14~74) winsize 61
7519 10:01:56.975147 [CA 2] Center 39 (10~68) winsize 59
7520 10:01:56.978423 [CA 3] Center 39 (10~68) winsize 59
7521 10:01:56.981915 [CA 4] Center 37 (7~67) winsize 61
7522 10:01:56.984919 [CA 5] Center 37 (7~67) winsize 61
7523 10:01:56.985019
7524 10:01:56.988512 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7525 10:01:56.988630
7526 10:01:56.991876 [CATrainingPosCal] consider 1 rank data
7527 10:01:56.995246 u2DelayCellTimex100 = 275/100 ps
7528 10:01:56.998595 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7529 10:01:57.005128 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7530 10:01:57.008627 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7531 10:01:57.011645 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7532 10:01:57.015133 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7533 10:01:57.018757 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7534 10:01:57.018842
7535 10:01:57.021522 CA PerBit enable=1, Macro0, CA PI delay=37
7536 10:01:57.021633
7537 10:01:57.025079 [CBTSetCACLKResult] CA Dly = 37
7538 10:01:57.028802 CS Dly: 10 (0~41)
7539 10:01:57.031547 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7540 10:01:57.035156 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7541 10:01:57.035234 ==
7542 10:01:57.038183 Dram Type= 6, Freq= 0, CH_0, rank 1
7543 10:01:57.042029 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7544 10:01:57.044968 ==
7545 10:01:57.048345 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7546 10:01:57.051764 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7547 10:01:57.058597 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7548 10:01:57.062100 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7549 10:01:57.072143 [CA 0] Center 44 (14~75) winsize 62
7550 10:01:57.075481 [CA 1] Center 44 (14~75) winsize 62
7551 10:01:57.078898 [CA 2] Center 40 (11~69) winsize 59
7552 10:01:57.082165 [CA 3] Center 39 (10~69) winsize 60
7553 10:01:57.085707 [CA 4] Center 38 (8~68) winsize 61
7554 10:01:57.089039 [CA 5] Center 37 (7~67) winsize 61
7555 10:01:57.089123
7556 10:01:57.092073 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7557 10:01:57.092157
7558 10:01:57.095550 [CATrainingPosCal] consider 2 rank data
7559 10:01:57.098940 u2DelayCellTimex100 = 275/100 ps
7560 10:01:57.102584 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7561 10:01:57.108728 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7562 10:01:57.112368 CA2 delay=39 (11~68),Diff = 2 PI (7 cell)
7563 10:01:57.115908 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7564 10:01:57.118941 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7565 10:01:57.122503 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7566 10:01:57.122587
7567 10:01:57.125816 CA PerBit enable=1, Macro0, CA PI delay=37
7568 10:01:57.125928
7569 10:01:57.129310 [CBTSetCACLKResult] CA Dly = 37
7570 10:01:57.129421 CS Dly: 11 (0~44)
7571 10:01:57.136308 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7572 10:01:57.139438 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7573 10:01:57.139521
7574 10:01:57.142955 ----->DramcWriteLeveling(PI) begin...
7575 10:01:57.143045 ==
7576 10:01:57.145891 Dram Type= 6, Freq= 0, CH_0, rank 0
7577 10:01:57.149474 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7578 10:01:57.149579 ==
7579 10:01:57.152622 Write leveling (Byte 0): 33 => 33
7580 10:01:57.156256 Write leveling (Byte 1): 30 => 30
7581 10:01:57.159174 DramcWriteLeveling(PI) end<-----
7582 10:01:57.159252
7583 10:01:57.159316 ==
7584 10:01:57.162511 Dram Type= 6, Freq= 0, CH_0, rank 0
7585 10:01:57.166105 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7586 10:01:57.169310 ==
7587 10:01:57.169416 [Gating] SW mode calibration
7588 10:01:57.176226 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7589 10:01:57.183084 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7590 10:01:57.186063 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 10:01:57.192709 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7592 10:01:57.196514 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 10:01:57.199381 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7594 10:01:57.206203 1 4 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7595 10:01:57.209697 1 4 20 | B1->B0 | 2424 3434 | 0 1 | (0 0) (0 0)
7596 10:01:57.213275 1 4 24 | B1->B0 | 2e2e 3434 | 0 1 | (1 1) (1 1)
7597 10:01:57.219894 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7598 10:01:57.222784 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7599 10:01:57.226329 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7600 10:01:57.229939 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7601 10:01:57.236159 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7602 10:01:57.239763 1 5 16 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (0 1)
7603 10:01:57.243082 1 5 20 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
7604 10:01:57.249738 1 5 24 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
7605 10:01:57.253424 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7606 10:01:57.256622 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7607 10:01:57.263039 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7608 10:01:57.266416 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7609 10:01:57.270148 1 6 12 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
7610 10:01:57.276712 1 6 16 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7611 10:01:57.279824 1 6 20 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
7612 10:01:57.283784 1 6 24 | B1->B0 | 3b3a 4646 | 1 0 | (0 0) (0 0)
7613 10:01:57.289651 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7614 10:01:57.293224 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7615 10:01:57.296674 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7616 10:01:57.299673 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7617 10:01:57.306433 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7618 10:01:57.309711 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7619 10:01:57.313294 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7620 10:01:57.319987 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7621 10:01:57.323501 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 10:01:57.326564 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 10:01:57.333001 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 10:01:57.336274 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 10:01:57.339677 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 10:01:57.346518 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 10:01:57.350049 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 10:01:57.352968 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 10:01:57.359969 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 10:01:57.362884 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 10:01:57.366822 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 10:01:57.372994 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 10:01:57.376569 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7634 10:01:57.380025 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7635 10:01:57.386668 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7636 10:01:57.386754 Total UI for P1: 0, mck2ui 16
7637 10:01:57.392855 best dqsien dly found for B0: ( 1, 9, 14)
7638 10:01:57.396181 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7639 10:01:57.399683 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7640 10:01:57.403230 Total UI for P1: 0, mck2ui 16
7641 10:01:57.406230 best dqsien dly found for B1: ( 1, 9, 22)
7642 10:01:57.409945 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7643 10:01:57.413230 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7644 10:01:57.413317
7645 10:01:57.416652 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7646 10:01:57.423086 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7647 10:01:57.423177 [Gating] SW calibration Done
7648 10:01:57.423253 ==
7649 10:01:57.426456 Dram Type= 6, Freq= 0, CH_0, rank 0
7650 10:01:57.432877 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7651 10:01:57.432970 ==
7652 10:01:57.433038 RX Vref Scan: 0
7653 10:01:57.433100
7654 10:01:57.436537 RX Vref 0 -> 0, step: 1
7655 10:01:57.436624
7656 10:01:57.440638 RX Delay 0 -> 252, step: 8
7657 10:01:57.443419 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7658 10:01:57.446510 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7659 10:01:57.449904 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7660 10:01:57.453252 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7661 10:01:57.459979 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7662 10:01:57.462900 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7663 10:01:57.466556 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7664 10:01:57.469947 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7665 10:01:57.473186 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7666 10:01:57.479855 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7667 10:01:57.483319 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7668 10:01:57.486703 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7669 10:01:57.490326 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7670 10:01:57.493380 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7671 10:01:57.499952 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7672 10:01:57.502826 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7673 10:01:57.502960 ==
7674 10:01:57.506755 Dram Type= 6, Freq= 0, CH_0, rank 0
7675 10:01:57.509679 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7676 10:01:57.509792 ==
7677 10:01:57.513366 DQS Delay:
7678 10:01:57.513473 DQS0 = 0, DQS1 = 0
7679 10:01:57.513580 DQM Delay:
7680 10:01:57.516306 DQM0 = 132, DQM1 = 124
7681 10:01:57.516408 DQ Delay:
7682 10:01:57.519769 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7683 10:01:57.523150 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7684 10:01:57.526665 DQ8 =111, DQ9 =111, DQ10 =119, DQ11 =119
7685 10:01:57.532947 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7686 10:01:57.533062
7687 10:01:57.533157
7688 10:01:57.533251 ==
7689 10:01:57.536481 Dram Type= 6, Freq= 0, CH_0, rank 0
7690 10:01:57.539709 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7691 10:01:57.539819 ==
7692 10:01:57.539924
7693 10:01:57.540017
7694 10:01:57.543007 TX Vref Scan disable
7695 10:01:57.543096 == TX Byte 0 ==
7696 10:01:57.549995 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7697 10:01:57.553111 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7698 10:01:57.553199 == TX Byte 1 ==
7699 10:01:57.560153 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7700 10:01:57.563357 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7701 10:01:57.563447 ==
7702 10:01:57.566562 Dram Type= 6, Freq= 0, CH_0, rank 0
7703 10:01:57.570207 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7704 10:01:57.570296 ==
7705 10:01:57.584402
7706 10:01:57.587546 TX Vref early break, caculate TX vref
7707 10:01:57.590290 TX Vref=16, minBit 4, minWin=21, winSum=361
7708 10:01:57.593890 TX Vref=18, minBit 7, minWin=21, winSum=375
7709 10:01:57.597301 TX Vref=20, minBit 0, minWin=23, winSum=384
7710 10:01:57.600758 TX Vref=22, minBit 4, minWin=22, winSum=396
7711 10:01:57.603659 TX Vref=24, minBit 0, minWin=23, winSum=402
7712 10:01:57.610578 TX Vref=26, minBit 4, minWin=24, winSum=416
7713 10:01:57.614208 TX Vref=28, minBit 4, minWin=24, winSum=421
7714 10:01:57.616814 TX Vref=30, minBit 4, minWin=23, winSum=420
7715 10:01:57.620500 TX Vref=32, minBit 0, minWin=24, winSum=411
7716 10:01:57.623779 TX Vref=34, minBit 4, minWin=23, winSum=398
7717 10:01:57.630378 [TxChooseVref] Worse bit 4, Min win 24, Win sum 421, Final Vref 28
7718 10:01:57.630490
7719 10:01:57.633585 Final TX Range 0 Vref 28
7720 10:01:57.633690
7721 10:01:57.633797 ==
7722 10:01:57.636974 Dram Type= 6, Freq= 0, CH_0, rank 0
7723 10:01:57.640236 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7724 10:01:57.640347 ==
7725 10:01:57.640443
7726 10:01:57.640538
7727 10:01:57.643665 TX Vref Scan disable
7728 10:01:57.650545 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7729 10:01:57.650659 == TX Byte 0 ==
7730 10:01:57.653924 u2DelayCellOfst[0]=14 cells (4 PI)
7731 10:01:57.657046 u2DelayCellOfst[1]=17 cells (5 PI)
7732 10:01:57.660269 u2DelayCellOfst[2]=10 cells (3 PI)
7733 10:01:57.663796 u2DelayCellOfst[3]=14 cells (4 PI)
7734 10:01:57.667252 u2DelayCellOfst[4]=7 cells (2 PI)
7735 10:01:57.670242 u2DelayCellOfst[5]=0 cells (0 PI)
7736 10:01:57.670330 u2DelayCellOfst[6]=17 cells (5 PI)
7737 10:01:57.673586 u2DelayCellOfst[7]=17 cells (5 PI)
7738 10:01:57.680214 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7739 10:01:57.683448 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7740 10:01:57.683540 == TX Byte 1 ==
7741 10:01:57.686866 u2DelayCellOfst[8]=0 cells (0 PI)
7742 10:01:57.690386 u2DelayCellOfst[9]=0 cells (0 PI)
7743 10:01:57.693896 u2DelayCellOfst[10]=3 cells (1 PI)
7744 10:01:57.697379 u2DelayCellOfst[11]=0 cells (0 PI)
7745 10:01:57.700239 u2DelayCellOfst[12]=10 cells (3 PI)
7746 10:01:57.703908 u2DelayCellOfst[13]=10 cells (3 PI)
7747 10:01:57.706836 u2DelayCellOfst[14]=14 cells (4 PI)
7748 10:01:57.710385 u2DelayCellOfst[15]=10 cells (3 PI)
7749 10:01:57.713698 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7750 10:01:57.717237 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7751 10:01:57.720375 DramC Write-DBI on
7752 10:01:57.720475 ==
7753 10:01:57.723562 Dram Type= 6, Freq= 0, CH_0, rank 0
7754 10:01:57.727390 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7755 10:01:57.727494 ==
7756 10:01:57.727589
7757 10:01:57.727678
7758 10:01:57.730341 TX Vref Scan disable
7759 10:01:57.733899 == TX Byte 0 ==
7760 10:01:57.737386 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7761 10:01:57.740558 == TX Byte 1 ==
7762 10:01:57.744065 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7763 10:01:57.744154 DramC Write-DBI off
7764 10:01:57.744224
7765 10:01:57.747130 [DATLAT]
7766 10:01:57.747212 Freq=1600, CH0 RK0
7767 10:01:57.747278
7768 10:01:57.750504 DATLAT Default: 0xf
7769 10:01:57.750631 0, 0xFFFF, sum = 0
7770 10:01:57.754141 1, 0xFFFF, sum = 0
7771 10:01:57.754251 2, 0xFFFF, sum = 0
7772 10:01:57.757134 3, 0xFFFF, sum = 0
7773 10:01:57.757218 4, 0xFFFF, sum = 0
7774 10:01:57.760726 5, 0xFFFF, sum = 0
7775 10:01:57.760811 6, 0xFFFF, sum = 0
7776 10:01:57.764083 7, 0xFFFF, sum = 0
7777 10:01:57.764167 8, 0xFFFF, sum = 0
7778 10:01:57.767648 9, 0xFFFF, sum = 0
7779 10:01:57.767733 10, 0xFFFF, sum = 0
7780 10:01:57.770994 11, 0xFFFF, sum = 0
7781 10:01:57.773806 12, 0xFFFF, sum = 0
7782 10:01:57.773891 13, 0xFFFF, sum = 0
7783 10:01:57.777165 14, 0x0, sum = 1
7784 10:01:57.777249 15, 0x0, sum = 2
7785 10:01:57.777315 16, 0x0, sum = 3
7786 10:01:57.780756 17, 0x0, sum = 4
7787 10:01:57.780840 best_step = 15
7788 10:01:57.780905
7789 10:01:57.780966 ==
7790 10:01:57.784040 Dram Type= 6, Freq= 0, CH_0, rank 0
7791 10:01:57.790833 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7792 10:01:57.790967 ==
7793 10:01:57.791033 RX Vref Scan: 1
7794 10:01:57.791095
7795 10:01:57.794017 Set Vref Range= 24 -> 127
7796 10:01:57.794098
7797 10:01:57.797602 RX Vref 24 -> 127, step: 1
7798 10:01:57.797702
7799 10:01:57.800689 RX Delay 11 -> 252, step: 4
7800 10:01:57.800804
7801 10:01:57.800899 Set Vref, RX VrefLevel [Byte0]: 24
7802 10:01:57.803884 [Byte1]: 24
7803 10:01:57.808538
7804 10:01:57.808649 Set Vref, RX VrefLevel [Byte0]: 25
7805 10:01:57.811627 [Byte1]: 25
7806 10:01:57.816080
7807 10:01:57.816183 Set Vref, RX VrefLevel [Byte0]: 26
7808 10:01:57.819097 [Byte1]: 26
7809 10:01:57.823911
7810 10:01:57.824014 Set Vref, RX VrefLevel [Byte0]: 27
7811 10:01:57.827013 [Byte1]: 27
7812 10:01:57.831227
7813 10:01:57.831344 Set Vref, RX VrefLevel [Byte0]: 28
7814 10:01:57.834542 [Byte1]: 28
7815 10:01:57.839231
7816 10:01:57.839343 Set Vref, RX VrefLevel [Byte0]: 29
7817 10:01:57.842150 [Byte1]: 29
7818 10:01:57.846388
7819 10:01:57.846504 Set Vref, RX VrefLevel [Byte0]: 30
7820 10:01:57.849736 [Byte1]: 30
7821 10:01:57.854015
7822 10:01:57.854133 Set Vref, RX VrefLevel [Byte0]: 31
7823 10:01:57.857636 [Byte1]: 31
7824 10:01:57.861603
7825 10:01:57.861713 Set Vref, RX VrefLevel [Byte0]: 32
7826 10:01:57.865184 [Byte1]: 32
7827 10:01:57.869464
7828 10:01:57.869574 Set Vref, RX VrefLevel [Byte0]: 33
7829 10:01:57.872894 [Byte1]: 33
7830 10:01:57.877059
7831 10:01:57.877164 Set Vref, RX VrefLevel [Byte0]: 34
7832 10:01:57.880339 [Byte1]: 34
7833 10:01:57.884402
7834 10:01:57.884509 Set Vref, RX VrefLevel [Byte0]: 35
7835 10:01:57.888015 [Byte1]: 35
7836 10:01:57.892636
7837 10:01:57.892760 Set Vref, RX VrefLevel [Byte0]: 36
7838 10:01:57.895580 [Byte1]: 36
7839 10:01:57.899492
7840 10:01:57.899620 Set Vref, RX VrefLevel [Byte0]: 37
7841 10:01:57.903251 [Byte1]: 37
7842 10:01:57.907081
7843 10:01:57.907164 Set Vref, RX VrefLevel [Byte0]: 38
7844 10:01:57.910407 [Byte1]: 38
7845 10:01:57.915407
7846 10:01:57.915513 Set Vref, RX VrefLevel [Byte0]: 39
7847 10:01:57.918274 [Byte1]: 39
7848 10:01:57.922886
7849 10:01:57.923011 Set Vref, RX VrefLevel [Byte0]: 40
7850 10:01:57.925736 [Byte1]: 40
7851 10:01:57.929995
7852 10:01:57.930102 Set Vref, RX VrefLevel [Byte0]: 41
7853 10:01:57.933292 [Byte1]: 41
7854 10:01:57.937996
7855 10:01:57.938080 Set Vref, RX VrefLevel [Byte0]: 42
7856 10:01:57.941030 [Byte1]: 42
7857 10:01:57.945582
7858 10:01:57.945679 Set Vref, RX VrefLevel [Byte0]: 43
7859 10:01:57.948455 [Byte1]: 43
7860 10:01:57.953195
7861 10:01:57.953307 Set Vref, RX VrefLevel [Byte0]: 44
7862 10:01:57.956416 [Byte1]: 44
7863 10:01:57.960888
7864 10:01:57.960999 Set Vref, RX VrefLevel [Byte0]: 45
7865 10:01:57.963845 [Byte1]: 45
7866 10:01:57.968066
7867 10:01:57.968180 Set Vref, RX VrefLevel [Byte0]: 46
7868 10:01:57.971425 [Byte1]: 46
7869 10:01:57.975628
7870 10:01:57.975730 Set Vref, RX VrefLevel [Byte0]: 47
7871 10:01:57.979102 [Byte1]: 47
7872 10:01:57.983560
7873 10:01:57.983679 Set Vref, RX VrefLevel [Byte0]: 48
7874 10:01:57.986789 [Byte1]: 48
7875 10:01:57.991206
7876 10:01:57.991314 Set Vref, RX VrefLevel [Byte0]: 49
7877 10:01:57.994628 [Byte1]: 49
7878 10:01:57.999410
7879 10:01:57.999566 Set Vref, RX VrefLevel [Byte0]: 50
7880 10:01:58.002433 [Byte1]: 50
7881 10:01:58.006558
7882 10:01:58.006665 Set Vref, RX VrefLevel [Byte0]: 51
7883 10:01:58.009442 [Byte1]: 51
7884 10:01:58.013735
7885 10:01:58.013843 Set Vref, RX VrefLevel [Byte0]: 52
7886 10:01:58.017460 [Byte1]: 52
7887 10:01:58.021401
7888 10:01:58.021503 Set Vref, RX VrefLevel [Byte0]: 53
7889 10:01:58.025363 [Byte1]: 53
7890 10:01:58.029435
7891 10:01:58.029549 Set Vref, RX VrefLevel [Byte0]: 54
7892 10:01:58.032243 [Byte1]: 54
7893 10:01:58.036662
7894 10:01:58.036769 Set Vref, RX VrefLevel [Byte0]: 55
7895 10:01:58.040037 [Byte1]: 55
7896 10:01:58.044243
7897 10:01:58.044347 Set Vref, RX VrefLevel [Byte0]: 56
7898 10:01:58.047671 [Byte1]: 56
7899 10:01:58.051937
7900 10:01:58.052039 Set Vref, RX VrefLevel [Byte0]: 57
7901 10:01:58.055455 [Byte1]: 57
7902 10:01:58.059883
7903 10:01:58.059985 Set Vref, RX VrefLevel [Byte0]: 58
7904 10:01:58.063235 [Byte1]: 58
7905 10:01:58.067290
7906 10:01:58.067368 Set Vref, RX VrefLevel [Byte0]: 59
7907 10:01:58.070702 [Byte1]: 59
7908 10:01:58.074758
7909 10:01:58.074884 Set Vref, RX VrefLevel [Byte0]: 60
7910 10:01:58.078420 [Byte1]: 60
7911 10:01:58.082346
7912 10:01:58.082453 Set Vref, RX VrefLevel [Byte0]: 61
7913 10:01:58.086032 [Byte1]: 61
7914 10:01:58.089749
7915 10:01:58.089855 Set Vref, RX VrefLevel [Byte0]: 62
7916 10:01:58.093507 [Byte1]: 62
7917 10:01:58.097828
7918 10:01:58.097951 Set Vref, RX VrefLevel [Byte0]: 63
7919 10:01:58.101012 [Byte1]: 63
7920 10:01:58.105597
7921 10:01:58.105706 Set Vref, RX VrefLevel [Byte0]: 64
7922 10:01:58.108918 [Byte1]: 64
7923 10:01:58.112923
7924 10:01:58.113158 Set Vref, RX VrefLevel [Byte0]: 65
7925 10:01:58.116514 [Byte1]: 65
7926 10:01:58.120835
7927 10:01:58.121063 Set Vref, RX VrefLevel [Byte0]: 66
7928 10:01:58.123808 [Byte1]: 66
7929 10:01:58.128331
7930 10:01:58.128575 Set Vref, RX VrefLevel [Byte0]: 67
7931 10:01:58.131584 [Byte1]: 67
7932 10:01:58.136105
7933 10:01:58.136296 Set Vref, RX VrefLevel [Byte0]: 68
7934 10:01:58.138939 [Byte1]: 68
7935 10:01:58.143405
7936 10:01:58.143575 Set Vref, RX VrefLevel [Byte0]: 69
7937 10:01:58.146587 [Byte1]: 69
7938 10:01:58.150887
7939 10:01:58.151012 Set Vref, RX VrefLevel [Byte0]: 70
7940 10:01:58.154506 [Byte1]: 70
7941 10:01:58.158365
7942 10:01:58.158475 Set Vref, RX VrefLevel [Byte0]: 71
7943 10:01:58.161670 [Byte1]: 71
7944 10:01:58.166166
7945 10:01:58.166282 Set Vref, RX VrefLevel [Byte0]: 72
7946 10:01:58.169569 [Byte1]: 72
7947 10:01:58.173685
7948 10:01:58.173797 Set Vref, RX VrefLevel [Byte0]: 73
7949 10:01:58.177709 [Byte1]: 73
7950 10:01:58.181486
7951 10:01:58.181597 Set Vref, RX VrefLevel [Byte0]: 74
7952 10:01:58.184591 [Byte1]: 74
7953 10:01:58.189077
7954 10:01:58.189243 Set Vref, RX VrefLevel [Byte0]: 75
7955 10:01:58.192320 [Byte1]: 75
7956 10:01:58.196869
7957 10:01:58.197018 Set Vref, RX VrefLevel [Byte0]: 76
7958 10:01:58.199644 [Byte1]: 76
7959 10:01:58.204052
7960 10:01:58.204153 Final RX Vref Byte 0 = 57 to rank0
7961 10:01:58.207715 Final RX Vref Byte 1 = 61 to rank0
7962 10:01:58.210821 Final RX Vref Byte 0 = 57 to rank1
7963 10:01:58.214104 Final RX Vref Byte 1 = 61 to rank1==
7964 10:01:58.218140 Dram Type= 6, Freq= 0, CH_0, rank 0
7965 10:01:58.221087 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7966 10:01:58.224442 ==
7967 10:01:58.224538 DQS Delay:
7968 10:01:58.224607 DQS0 = 0, DQS1 = 0
7969 10:01:58.227623 DQM Delay:
7970 10:01:58.227713 DQM0 = 129, DQM1 = 121
7971 10:01:58.231115 DQ Delay:
7972 10:01:58.234185 DQ0 =130, DQ1 =132, DQ2 =126, DQ3 =126
7973 10:01:58.237431 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
7974 10:01:58.240989 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =116
7975 10:01:58.244795 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =132
7976 10:01:58.244909
7977 10:01:58.245009
7978 10:01:58.245101
7979 10:01:58.247637 [DramC_TX_OE_Calibration] TA2
7980 10:01:58.251132 Original DQ_B0 (3 6) =30, OEN = 27
7981 10:01:58.254454 Original DQ_B1 (3 6) =30, OEN = 27
7982 10:01:58.257540 24, 0x0, End_B0=24 End_B1=24
7983 10:01:58.257665 25, 0x0, End_B0=25 End_B1=25
7984 10:01:58.260775 26, 0x0, End_B0=26 End_B1=26
7985 10:01:58.264650 27, 0x0, End_B0=27 End_B1=27
7986 10:01:58.267884 28, 0x0, End_B0=28 End_B1=28
7987 10:01:58.268028 29, 0x0, End_B0=29 End_B1=29
7988 10:01:58.270894 30, 0x0, End_B0=30 End_B1=30
7989 10:01:58.274146 31, 0x4141, End_B0=30 End_B1=30
7990 10:01:58.278145 Byte0 end_step=30 best_step=27
7991 10:01:58.280768 Byte1 end_step=30 best_step=27
7992 10:01:58.284716 Byte0 TX OE(2T, 0.5T) = (3, 3)
7993 10:01:58.284858 Byte1 TX OE(2T, 0.5T) = (3, 3)
7994 10:01:58.284956
7995 10:01:58.285063
7996 10:01:58.294738 [DQSOSCAuto] RK0, (LSB)MR18= 0x1408, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
7997 10:01:58.297921 CH0 RK0: MR19=303, MR18=1408
7998 10:01:58.301258 CH0_RK0: MR19=0x303, MR18=0x1408, DQSOSC=399, MR23=63, INC=23, DEC=15
7999 10:01:58.304322
8000 10:01:58.307804 ----->DramcWriteLeveling(PI) begin...
8001 10:01:58.307932 ==
8002 10:01:58.311185 Dram Type= 6, Freq= 0, CH_0, rank 1
8003 10:01:58.314551 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8004 10:01:58.314654 ==
8005 10:01:58.317898 Write leveling (Byte 0): 31 => 31
8006 10:01:58.320847 Write leveling (Byte 1): 28 => 28
8007 10:01:58.324347 DramcWriteLeveling(PI) end<-----
8008 10:01:58.324449
8009 10:01:58.324544 ==
8010 10:01:58.327835 Dram Type= 6, Freq= 0, CH_0, rank 1
8011 10:01:58.331474 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8012 10:01:58.331560 ==
8013 10:01:58.334617 [Gating] SW mode calibration
8014 10:01:58.341118 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8015 10:01:58.347583 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8016 10:01:58.351138 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8017 10:01:58.354664 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8018 10:01:58.361221 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8019 10:01:58.364147 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8020 10:01:58.367552 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8021 10:01:58.371078 1 4 20 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
8022 10:01:58.377678 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8023 10:01:58.381738 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8024 10:01:58.384608 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8025 10:01:58.391183 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8026 10:01:58.394680 1 5 8 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
8027 10:01:58.397662 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 1)
8028 10:01:58.404451 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8029 10:01:58.407816 1 5 20 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
8030 10:01:58.411424 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8031 10:01:58.417805 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8032 10:01:58.421376 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8033 10:01:58.424927 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8034 10:01:58.430947 1 6 8 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
8035 10:01:58.434664 1 6 12 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
8036 10:01:58.437733 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8037 10:01:58.444414 1 6 20 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
8038 10:01:58.448009 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8039 10:01:58.451430 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8040 10:01:58.457568 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8041 10:01:58.461257 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8042 10:01:58.464860 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8043 10:01:58.467651 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8044 10:01:58.474370 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8045 10:01:58.477915 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8046 10:01:58.481276 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8047 10:01:58.487807 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 10:01:58.491183 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 10:01:58.494796 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 10:01:58.501592 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 10:01:58.504826 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 10:01:58.507667 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 10:01:58.514508 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 10:01:58.518141 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 10:01:58.521093 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 10:01:58.527816 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 10:01:58.531495 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8058 10:01:58.534437 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8059 10:01:58.541482 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8060 10:01:58.544461 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8061 10:01:58.547979 Total UI for P1: 0, mck2ui 16
8062 10:01:58.551540 best dqsien dly found for B0: ( 1, 9, 8)
8063 10:01:58.554817 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8064 10:01:58.557776 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8065 10:01:58.561561 Total UI for P1: 0, mck2ui 16
8066 10:01:58.564609 best dqsien dly found for B1: ( 1, 9, 20)
8067 10:01:58.568397 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8068 10:01:58.571564 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8069 10:01:58.571676
8070 10:01:58.578606 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8071 10:01:58.581712 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8072 10:01:58.585041 [Gating] SW calibration Done
8073 10:01:58.585150 ==
8074 10:01:58.588181 Dram Type= 6, Freq= 0, CH_0, rank 1
8075 10:01:58.591763 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8076 10:01:58.591870 ==
8077 10:01:58.591964 RX Vref Scan: 0
8078 10:01:58.592054
8079 10:01:58.594642 RX Vref 0 -> 0, step: 1
8080 10:01:58.594753
8081 10:01:58.598056 RX Delay 0 -> 252, step: 8
8082 10:01:58.601663 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8083 10:01:58.605011 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8084 10:01:58.608043 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
8085 10:01:58.614550 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8086 10:01:58.618155 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8087 10:01:58.621536 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8088 10:01:58.625018 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8089 10:01:58.628745 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8090 10:01:58.634689 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8091 10:01:58.638089 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8092 10:01:58.641707 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8093 10:01:58.645561 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8094 10:01:58.648376 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8095 10:01:58.655031 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8096 10:01:58.658393 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8097 10:01:58.661590 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8098 10:01:58.661692 ==
8099 10:01:58.664990 Dram Type= 6, Freq= 0, CH_0, rank 1
8100 10:01:58.668018 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8101 10:01:58.668127 ==
8102 10:01:58.671597 DQS Delay:
8103 10:01:58.671702 DQS0 = 0, DQS1 = 0
8104 10:01:58.675099 DQM Delay:
8105 10:01:58.675202 DQM0 = 131, DQM1 = 124
8106 10:01:58.675296 DQ Delay:
8107 10:01:58.678583 DQ0 =131, DQ1 =131, DQ2 =131, DQ3 =131
8108 10:01:58.681592 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8109 10:01:58.688235 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8110 10:01:58.691775 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
8111 10:01:58.691885
8112 10:01:58.691977
8113 10:01:58.692065 ==
8114 10:01:58.695483 Dram Type= 6, Freq= 0, CH_0, rank 1
8115 10:01:58.698477 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8116 10:01:58.698580 ==
8117 10:01:58.698672
8118 10:01:58.698767
8119 10:01:58.701820 TX Vref Scan disable
8120 10:01:58.701928 == TX Byte 0 ==
8121 10:01:58.708643 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8122 10:01:58.712182 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8123 10:01:58.712285 == TX Byte 1 ==
8124 10:01:58.718381 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8125 10:01:58.721690 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8126 10:01:58.721793 ==
8127 10:01:58.725305 Dram Type= 6, Freq= 0, CH_0, rank 1
8128 10:01:58.728141 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8129 10:01:58.728245 ==
8130 10:01:58.743666
8131 10:01:58.747260 TX Vref early break, caculate TX vref
8132 10:01:58.750747 TX Vref=16, minBit 1, minWin=21, winSum=371
8133 10:01:58.753646 TX Vref=18, minBit 0, minWin=23, winSum=388
8134 10:01:58.757057 TX Vref=20, minBit 1, minWin=23, winSum=392
8135 10:01:58.760726 TX Vref=22, minBit 1, minWin=24, winSum=396
8136 10:01:58.763612 TX Vref=24, minBit 0, minWin=25, winSum=411
8137 10:01:58.770420 TX Vref=26, minBit 0, minWin=25, winSum=421
8138 10:01:58.773778 TX Vref=28, minBit 1, minWin=25, winSum=420
8139 10:01:58.777258 TX Vref=30, minBit 0, minWin=25, winSum=419
8140 10:01:58.780259 TX Vref=32, minBit 7, minWin=23, winSum=410
8141 10:01:58.783782 TX Vref=34, minBit 1, minWin=23, winSum=400
8142 10:01:58.787003 TX Vref=36, minBit 0, minWin=22, winSum=388
8143 10:01:58.793689 [TxChooseVref] Worse bit 0, Min win 25, Win sum 421, Final Vref 26
8144 10:01:58.793789
8145 10:01:58.797048 Final TX Range 0 Vref 26
8146 10:01:58.797136
8147 10:01:58.797204 ==
8148 10:01:58.800641 Dram Type= 6, Freq= 0, CH_0, rank 1
8149 10:01:58.804214 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8150 10:01:58.804324 ==
8151 10:01:58.804419
8152 10:01:58.804512
8153 10:01:58.807030 TX Vref Scan disable
8154 10:01:58.814111 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8155 10:01:58.814208 == TX Byte 0 ==
8156 10:01:58.817265 u2DelayCellOfst[0]=14 cells (4 PI)
8157 10:01:58.820642 u2DelayCellOfst[1]=21 cells (6 PI)
8158 10:01:58.824197 u2DelayCellOfst[2]=10 cells (3 PI)
8159 10:01:58.827107 u2DelayCellOfst[3]=10 cells (3 PI)
8160 10:01:58.830746 u2DelayCellOfst[4]=10 cells (3 PI)
8161 10:01:58.834278 u2DelayCellOfst[5]=0 cells (0 PI)
8162 10:01:58.837293 u2DelayCellOfst[6]=21 cells (6 PI)
8163 10:01:58.840655 u2DelayCellOfst[7]=17 cells (5 PI)
8164 10:01:58.844057 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8165 10:01:58.847065 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8166 10:01:58.850514 == TX Byte 1 ==
8167 10:01:58.850597 u2DelayCellOfst[8]=0 cells (0 PI)
8168 10:01:58.854058 u2DelayCellOfst[9]=0 cells (0 PI)
8169 10:01:58.857020 u2DelayCellOfst[10]=7 cells (2 PI)
8170 10:01:58.860833 u2DelayCellOfst[11]=3 cells (1 PI)
8171 10:01:58.864000 u2DelayCellOfst[12]=10 cells (3 PI)
8172 10:01:58.867071 u2DelayCellOfst[13]=10 cells (3 PI)
8173 10:01:58.870369 u2DelayCellOfst[14]=17 cells (5 PI)
8174 10:01:58.874046 u2DelayCellOfst[15]=10 cells (3 PI)
8175 10:01:58.877289 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8176 10:01:58.883636 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8177 10:01:58.883723 DramC Write-DBI on
8178 10:01:58.883790 ==
8179 10:01:58.887012 Dram Type= 6, Freq= 0, CH_0, rank 1
8180 10:01:58.890729 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8181 10:01:58.893827 ==
8182 10:01:58.893931
8183 10:01:58.894023
8184 10:01:58.894112 TX Vref Scan disable
8185 10:01:58.897506 == TX Byte 0 ==
8186 10:01:58.900813 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8187 10:01:58.903658 == TX Byte 1 ==
8188 10:01:58.907210 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8189 10:01:58.907290 DramC Write-DBI off
8190 10:01:58.910627
8191 10:01:58.910730 [DATLAT]
8192 10:01:58.910822 Freq=1600, CH0 RK1
8193 10:01:58.910908
8194 10:01:58.914037 DATLAT Default: 0xf
8195 10:01:58.914113 0, 0xFFFF, sum = 0
8196 10:01:58.917139 1, 0xFFFF, sum = 0
8197 10:01:58.920703 2, 0xFFFF, sum = 0
8198 10:01:58.920807 3, 0xFFFF, sum = 0
8199 10:01:58.923927 4, 0xFFFF, sum = 0
8200 10:01:58.924029 5, 0xFFFF, sum = 0
8201 10:01:58.927315 6, 0xFFFF, sum = 0
8202 10:01:58.927418 7, 0xFFFF, sum = 0
8203 10:01:58.930670 8, 0xFFFF, sum = 0
8204 10:01:58.930774 9, 0xFFFF, sum = 0
8205 10:01:58.933714 10, 0xFFFF, sum = 0
8206 10:01:58.933789 11, 0xFFFF, sum = 0
8207 10:01:58.936977 12, 0xFFFF, sum = 0
8208 10:01:58.937063 13, 0xFFFF, sum = 0
8209 10:01:58.940579 14, 0x0, sum = 1
8210 10:01:58.940695 15, 0x0, sum = 2
8211 10:01:58.944082 16, 0x0, sum = 3
8212 10:01:58.944200 17, 0x0, sum = 4
8213 10:01:58.947184 best_step = 15
8214 10:01:58.947260
8215 10:01:58.947323 ==
8216 10:01:58.950715 Dram Type= 6, Freq= 0, CH_0, rank 1
8217 10:01:58.954289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8218 10:01:58.954398 ==
8219 10:01:58.954491 RX Vref Scan: 0
8220 10:01:58.957499
8221 10:01:58.957599 RX Vref 0 -> 0, step: 1
8222 10:01:58.957688
8223 10:01:58.960460 RX Delay 11 -> 252, step: 4
8224 10:01:58.963937 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8225 10:01:58.970420 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8226 10:01:58.974005 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8227 10:01:58.977952 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8228 10:01:58.980925 iDelay=191, Bit 4, Center 126 (75 ~ 178) 104
8229 10:01:58.983861 iDelay=191, Bit 5, Center 114 (59 ~ 170) 112
8230 10:01:58.990822 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8231 10:01:58.993839 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8232 10:01:58.997461 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8233 10:01:59.001030 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8234 10:01:59.003823 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8235 10:01:59.007215 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8236 10:01:59.013862 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8237 10:01:59.017446 iDelay=191, Bit 13, Center 126 (71 ~ 182) 112
8238 10:01:59.020895 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8239 10:01:59.023969 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8240 10:01:59.024054 ==
8241 10:01:59.027568 Dram Type= 6, Freq= 0, CH_0, rank 1
8242 10:01:59.034171 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8243 10:01:59.034273 ==
8244 10:01:59.034339 DQS Delay:
8245 10:01:59.037858 DQS0 = 0, DQS1 = 0
8246 10:01:59.037968 DQM Delay:
8247 10:01:59.038049 DQM0 = 127, DQM1 = 122
8248 10:01:59.040804 DQ Delay:
8249 10:01:59.044362 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8250 10:01:59.047642 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =136
8251 10:01:59.050768 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8252 10:01:59.053996 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =130
8253 10:01:59.054080
8254 10:01:59.054144
8255 10:01:59.054210
8256 10:01:59.057713 [DramC_TX_OE_Calibration] TA2
8257 10:01:59.061290 Original DQ_B0 (3 6) =30, OEN = 27
8258 10:01:59.064237 Original DQ_B1 (3 6) =30, OEN = 27
8259 10:01:59.067686 24, 0x0, End_B0=24 End_B1=24
8260 10:01:59.067799 25, 0x0, End_B0=25 End_B1=25
8261 10:01:59.071390 26, 0x0, End_B0=26 End_B1=26
8262 10:01:59.074606 27, 0x0, End_B0=27 End_B1=27
8263 10:01:59.077446 28, 0x0, End_B0=28 End_B1=28
8264 10:01:59.077550 29, 0x0, End_B0=29 End_B1=29
8265 10:01:59.081038 30, 0x0, End_B0=30 End_B1=30
8266 10:01:59.084472 31, 0x4141, End_B0=30 End_B1=30
8267 10:01:59.087986 Byte0 end_step=30 best_step=27
8268 10:01:59.091347 Byte1 end_step=30 best_step=27
8269 10:01:59.094734 Byte0 TX OE(2T, 0.5T) = (3, 3)
8270 10:01:59.094842 Byte1 TX OE(2T, 0.5T) = (3, 3)
8271 10:01:59.094955
8272 10:01:59.097711
8273 10:01:59.104042 [DQSOSCAuto] RK1, (LSB)MR18= 0x150a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 399 ps
8274 10:01:59.107498 CH0 RK1: MR19=303, MR18=150A
8275 10:01:59.114397 CH0_RK1: MR19=0x303, MR18=0x150A, DQSOSC=399, MR23=63, INC=23, DEC=15
8276 10:01:59.117910 [RxdqsGatingPostProcess] freq 1600
8277 10:01:59.120939 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8278 10:01:59.124059 best DQS0 dly(2T, 0.5T) = (1, 1)
8279 10:01:59.127304 best DQS1 dly(2T, 0.5T) = (1, 1)
8280 10:01:59.130877 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8281 10:01:59.134736 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8282 10:01:59.137942 best DQS0 dly(2T, 0.5T) = (1, 1)
8283 10:01:59.140752 best DQS1 dly(2T, 0.5T) = (1, 1)
8284 10:01:59.144142 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8285 10:01:59.148119 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8286 10:01:59.148223 Pre-setting of DQS Precalculation
8287 10:01:59.154431 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8288 10:01:59.154534 ==
8289 10:01:59.157573 Dram Type= 6, Freq= 0, CH_1, rank 0
8290 10:01:59.161160 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8291 10:01:59.161281 ==
8292 10:01:59.167753 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8293 10:01:59.171176 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8294 10:01:59.174554 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8295 10:01:59.180938 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8296 10:01:59.190304 [CA 0] Center 42 (13~71) winsize 59
8297 10:01:59.193649 [CA 1] Center 42 (13~71) winsize 59
8298 10:01:59.197103 [CA 2] Center 37 (9~66) winsize 58
8299 10:01:59.200651 [CA 3] Center 36 (7~65) winsize 59
8300 10:01:59.203569 [CA 4] Center 37 (8~67) winsize 60
8301 10:01:59.206919 [CA 5] Center 36 (6~66) winsize 61
8302 10:01:59.206999
8303 10:01:59.210372 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8304 10:01:59.210478
8305 10:01:59.213652 [CATrainingPosCal] consider 1 rank data
8306 10:01:59.217116 u2DelayCellTimex100 = 275/100 ps
8307 10:01:59.220863 CA0 delay=42 (13~71),Diff = 6 PI (21 cell)
8308 10:01:59.227381 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8309 10:01:59.230226 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8310 10:01:59.233630 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8311 10:01:59.236999 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8312 10:01:59.240630 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8313 10:01:59.240735
8314 10:01:59.243531 CA PerBit enable=1, Macro0, CA PI delay=36
8315 10:01:59.243636
8316 10:01:59.247136 [CBTSetCACLKResult] CA Dly = 36
8317 10:01:59.247241 CS Dly: 8 (0~39)
8318 10:01:59.254128 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8319 10:01:59.257139 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8320 10:01:59.257247 ==
8321 10:01:59.260274 Dram Type= 6, Freq= 0, CH_1, rank 1
8322 10:01:59.263831 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8323 10:01:59.263942 ==
8324 10:01:59.270411 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8325 10:01:59.273990 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8326 10:01:59.277342 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8327 10:01:59.284120 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8328 10:01:59.293285 [CA 0] Center 42 (14~71) winsize 58
8329 10:01:59.297201 [CA 1] Center 42 (14~71) winsize 58
8330 10:01:59.300072 [CA 2] Center 37 (8~66) winsize 59
8331 10:01:59.303714 [CA 3] Center 36 (7~66) winsize 60
8332 10:01:59.307269 [CA 4] Center 37 (8~67) winsize 60
8333 10:01:59.310011 [CA 5] Center 36 (7~66) winsize 60
8334 10:01:59.310095
8335 10:01:59.313717 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8336 10:01:59.313801
8337 10:01:59.316979 [CATrainingPosCal] consider 2 rank data
8338 10:01:59.320480 u2DelayCellTimex100 = 275/100 ps
8339 10:01:59.323173 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8340 10:01:59.330119 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8341 10:01:59.333643 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8342 10:01:59.336582 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8343 10:01:59.340047 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8344 10:01:59.343560 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8345 10:01:59.343644
8346 10:01:59.346910 CA PerBit enable=1, Macro0, CA PI delay=36
8347 10:01:59.346993
8348 10:01:59.350365 [CBTSetCACLKResult] CA Dly = 36
8349 10:01:59.350448 CS Dly: 11 (0~45)
8350 10:01:59.356729 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8351 10:01:59.360105 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8352 10:01:59.360189
8353 10:01:59.363489 ----->DramcWriteLeveling(PI) begin...
8354 10:01:59.363574 ==
8355 10:01:59.366884 Dram Type= 6, Freq= 0, CH_1, rank 0
8356 10:01:59.370198 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8357 10:01:59.370309 ==
8358 10:01:59.373321 Write leveling (Byte 0): 22 => 22
8359 10:01:59.376794 Write leveling (Byte 1): 29 => 29
8360 10:01:59.380410 DramcWriteLeveling(PI) end<-----
8361 10:01:59.380510
8362 10:01:59.380582 ==
8363 10:01:59.383551 Dram Type= 6, Freq= 0, CH_1, rank 0
8364 10:01:59.386809 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8365 10:01:59.390491 ==
8366 10:01:59.390571 [Gating] SW mode calibration
8367 10:01:59.400366 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8368 10:01:59.403714 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8369 10:01:59.407176 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 10:01:59.414031 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 10:01:59.416940 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 10:01:59.420402 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 10:01:59.427131 1 4 16 | B1->B0 | 3232 2c2c | 1 1 | (1 1) (0 0)
8374 10:01:59.430586 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8375 10:01:59.434048 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 10:01:59.440486 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 10:01:59.444320 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 10:01:59.447419 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 10:01:59.453702 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 10:01:59.457205 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8381 10:01:59.460473 1 5 16 | B1->B0 | 3131 3434 | 1 0 | (1 0) (1 0)
8382 10:01:59.463772 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 10:01:59.470930 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 10:01:59.473763 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 10:01:59.476884 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 10:01:59.483417 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 10:01:59.486881 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 10:01:59.490198 1 6 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8389 10:01:59.497380 1 6 16 | B1->B0 | 3b3b 2d2d | 0 0 | (0 0) (0 0)
8390 10:01:59.501078 1 6 20 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
8391 10:01:59.503703 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 10:01:59.510484 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 10:01:59.513597 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 10:01:59.517281 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 10:01:59.524001 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 10:01:59.527329 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 10:01:59.530733 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8398 10:01:59.537303 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8399 10:01:59.540385 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 10:01:59.543901 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 10:01:59.547461 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 10:01:59.554161 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 10:01:59.556987 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 10:01:59.560540 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 10:01:59.567326 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 10:01:59.570694 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 10:01:59.573739 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 10:01:59.580476 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 10:01:59.583881 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 10:01:59.587196 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 10:01:59.594246 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 10:01:59.597651 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8413 10:01:59.600421 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8414 10:01:59.603785 Total UI for P1: 0, mck2ui 16
8415 10:01:59.607196 best dqsien dly found for B0: ( 1, 9, 12)
8416 10:01:59.614147 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8417 10:01:59.617278 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8418 10:01:59.620856 Total UI for P1: 0, mck2ui 16
8419 10:01:59.623936 best dqsien dly found for B1: ( 1, 9, 18)
8420 10:01:59.627685 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8421 10:01:59.631092 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8422 10:01:59.631195
8423 10:01:59.634354 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8424 10:01:59.637240 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8425 10:01:59.640821 [Gating] SW calibration Done
8426 10:01:59.640925 ==
8427 10:01:59.643942 Dram Type= 6, Freq= 0, CH_1, rank 0
8428 10:01:59.647510 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8429 10:01:59.647629 ==
8430 10:01:59.651204 RX Vref Scan: 0
8431 10:01:59.651309
8432 10:01:59.654176 RX Vref 0 -> 0, step: 1
8433 10:01:59.654282
8434 10:01:59.654380 RX Delay 0 -> 252, step: 8
8435 10:01:59.660897 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8436 10:01:59.664474 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8437 10:01:59.667508 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8438 10:01:59.671003 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8439 10:01:59.674412 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8440 10:01:59.677555 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8441 10:01:59.684293 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8442 10:01:59.687420 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8443 10:01:59.690804 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8444 10:01:59.694456 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8445 10:01:59.697329 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8446 10:01:59.704572 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8447 10:01:59.707750 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8448 10:01:59.710997 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8449 10:01:59.714508 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8450 10:01:59.717819 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8451 10:01:59.721155 ==
8452 10:01:59.721261 Dram Type= 6, Freq= 0, CH_1, rank 0
8453 10:01:59.728088 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8454 10:01:59.728192 ==
8455 10:01:59.728283 DQS Delay:
8456 10:01:59.731085 DQS0 = 0, DQS1 = 0
8457 10:01:59.731185 DQM Delay:
8458 10:01:59.735070 DQM0 = 134, DQM1 = 127
8459 10:01:59.735185 DQ Delay:
8460 10:01:59.737652 DQ0 =139, DQ1 =127, DQ2 =119, DQ3 =135
8461 10:01:59.741222 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =131
8462 10:01:59.744868 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8463 10:01:59.747879 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8464 10:01:59.747975
8465 10:01:59.748067
8466 10:01:59.748157 ==
8467 10:01:59.751559 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 10:01:59.758191 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 10:01:59.758291 ==
8470 10:01:59.758379
8471 10:01:59.758468
8472 10:01:59.758553 TX Vref Scan disable
8473 10:01:59.761285 == TX Byte 0 ==
8474 10:01:59.764270 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8475 10:01:59.767949 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8476 10:01:59.771447 == TX Byte 1 ==
8477 10:01:59.774417 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8478 10:01:59.778254 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8479 10:01:59.781215 ==
8480 10:01:59.781315 Dram Type= 6, Freq= 0, CH_1, rank 0
8481 10:01:59.787899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8482 10:01:59.788002 ==
8483 10:01:59.801952
8484 10:01:59.804869 TX Vref early break, caculate TX vref
8485 10:01:59.808354 TX Vref=16, minBit 8, minWin=20, winSum=360
8486 10:01:59.811755 TX Vref=18, minBit 8, minWin=21, winSum=371
8487 10:01:59.814755 TX Vref=20, minBit 8, minWin=22, winSum=385
8488 10:01:59.818445 TX Vref=22, minBit 8, minWin=23, winSum=396
8489 10:01:59.821590 TX Vref=24, minBit 8, minWin=23, winSum=404
8490 10:01:59.828743 TX Vref=26, minBit 8, minWin=24, winSum=412
8491 10:01:59.831837 TX Vref=28, minBit 8, minWin=24, winSum=418
8492 10:01:59.835132 TX Vref=30, minBit 0, minWin=25, winSum=416
8493 10:01:59.838475 TX Vref=32, minBit 9, minWin=24, winSum=408
8494 10:01:59.841844 TX Vref=34, minBit 11, minWin=23, winSum=397
8495 10:01:59.845239 TX Vref=36, minBit 8, minWin=23, winSum=386
8496 10:01:59.851826 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 30
8497 10:01:59.851934
8498 10:01:59.855483 Final TX Range 0 Vref 30
8499 10:01:59.855587
8500 10:01:59.855682 ==
8501 10:01:59.858505 Dram Type= 6, Freq= 0, CH_1, rank 0
8502 10:01:59.862038 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8503 10:01:59.862148 ==
8504 10:01:59.862242
8505 10:01:59.862334
8506 10:01:59.865685 TX Vref Scan disable
8507 10:01:59.872177 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8508 10:01:59.872287 == TX Byte 0 ==
8509 10:01:59.875255 u2DelayCellOfst[0]=17 cells (5 PI)
8510 10:01:59.878788 u2DelayCellOfst[1]=14 cells (4 PI)
8511 10:01:59.882408 u2DelayCellOfst[2]=0 cells (0 PI)
8512 10:01:59.885240 u2DelayCellOfst[3]=7 cells (2 PI)
8513 10:01:59.888696 u2DelayCellOfst[4]=10 cells (3 PI)
8514 10:01:59.892120 u2DelayCellOfst[5]=21 cells (6 PI)
8515 10:01:59.895158 u2DelayCellOfst[6]=17 cells (5 PI)
8516 10:01:59.895233 u2DelayCellOfst[7]=3 cells (1 PI)
8517 10:01:59.902271 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8518 10:01:59.905484 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8519 10:01:59.905590 == TX Byte 1 ==
8520 10:01:59.909061 u2DelayCellOfst[8]=0 cells (0 PI)
8521 10:01:59.911971 u2DelayCellOfst[9]=7 cells (2 PI)
8522 10:01:59.915720 u2DelayCellOfst[10]=10 cells (3 PI)
8523 10:01:59.918663 u2DelayCellOfst[11]=7 cells (2 PI)
8524 10:01:59.922528 u2DelayCellOfst[12]=14 cells (4 PI)
8525 10:01:59.925735 u2DelayCellOfst[13]=17 cells (5 PI)
8526 10:01:59.928791 u2DelayCellOfst[14]=17 cells (5 PI)
8527 10:01:59.932234 u2DelayCellOfst[15]=17 cells (5 PI)
8528 10:01:59.935569 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8529 10:01:59.938803 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8530 10:01:59.942549 DramC Write-DBI on
8531 10:01:59.942657 ==
8532 10:01:59.945521 Dram Type= 6, Freq= 0, CH_1, rank 0
8533 10:01:59.948993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8534 10:01:59.949102 ==
8535 10:01:59.949198
8536 10:01:59.949291
8537 10:01:59.952194 TX Vref Scan disable
8538 10:01:59.955404 == TX Byte 0 ==
8539 10:01:59.958939 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8540 10:01:59.962488 == TX Byte 1 ==
8541 10:01:59.965540 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8542 10:01:59.965644 DramC Write-DBI off
8543 10:01:59.965738
8544 10:01:59.969087 [DATLAT]
8545 10:01:59.969198 Freq=1600, CH1 RK0
8546 10:01:59.969300
8547 10:01:59.972705 DATLAT Default: 0xf
8548 10:01:59.972810 0, 0xFFFF, sum = 0
8549 10:01:59.975832 1, 0xFFFF, sum = 0
8550 10:01:59.976016 2, 0xFFFF, sum = 0
8551 10:01:59.978972 3, 0xFFFF, sum = 0
8552 10:01:59.979084 4, 0xFFFF, sum = 0
8553 10:01:59.982492 5, 0xFFFF, sum = 0
8554 10:01:59.982603 6, 0xFFFF, sum = 0
8555 10:01:59.985476 7, 0xFFFF, sum = 0
8556 10:01:59.985588 8, 0xFFFF, sum = 0
8557 10:01:59.989081 9, 0xFFFF, sum = 0
8558 10:01:59.989206 10, 0xFFFF, sum = 0
8559 10:01:59.992539 11, 0xFFFF, sum = 0
8560 10:01:59.995962 12, 0xFFFF, sum = 0
8561 10:01:59.996072 13, 0xFFFF, sum = 0
8562 10:01:59.998869 14, 0x0, sum = 1
8563 10:01:59.998981 15, 0x0, sum = 2
8564 10:01:59.999078 16, 0x0, sum = 3
8565 10:02:00.002526 17, 0x0, sum = 4
8566 10:02:00.002639 best_step = 15
8567 10:02:00.002734
8568 10:02:00.002824 ==
8569 10:02:00.006255 Dram Type= 6, Freq= 0, CH_1, rank 0
8570 10:02:00.012650 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8571 10:02:00.012781 ==
8572 10:02:00.012880 RX Vref Scan: 1
8573 10:02:00.012972
8574 10:02:00.015678 Set Vref Range= 24 -> 127
8575 10:02:00.015808
8576 10:02:00.019315 RX Vref 24 -> 127, step: 1
8577 10:02:00.019420
8578 10:02:00.022847 RX Delay 11 -> 252, step: 4
8579 10:02:00.022949
8580 10:02:00.026458 Set Vref, RX VrefLevel [Byte0]: 24
8581 10:02:00.026570 [Byte1]: 24
8582 10:02:00.030434
8583 10:02:00.030560 Set Vref, RX VrefLevel [Byte0]: 25
8584 10:02:00.034074 [Byte1]: 25
8585 10:02:00.037830
8586 10:02:00.037928 Set Vref, RX VrefLevel [Byte0]: 26
8587 10:02:00.041301 [Byte1]: 26
8588 10:02:00.045361
8589 10:02:00.045469 Set Vref, RX VrefLevel [Byte0]: 27
8590 10:02:00.048960 [Byte1]: 27
8591 10:02:00.053268
8592 10:02:00.053379 Set Vref, RX VrefLevel [Byte0]: 28
8593 10:02:00.056230 [Byte1]: 28
8594 10:02:00.060561
8595 10:02:00.060646 Set Vref, RX VrefLevel [Byte0]: 29
8596 10:02:00.063888 [Byte1]: 29
8597 10:02:00.068346
8598 10:02:00.068431 Set Vref, RX VrefLevel [Byte0]: 30
8599 10:02:00.071932 [Byte1]: 30
8600 10:02:00.076002
8601 10:02:00.076087 Set Vref, RX VrefLevel [Byte0]: 31
8602 10:02:00.079162 [Byte1]: 31
8603 10:02:00.083941
8604 10:02:00.084024 Set Vref, RX VrefLevel [Byte0]: 32
8605 10:02:00.086970 [Byte1]: 32
8606 10:02:00.091159
8607 10:02:00.091242 Set Vref, RX VrefLevel [Byte0]: 33
8608 10:02:00.094767 [Byte1]: 33
8609 10:02:00.098796
8610 10:02:00.098888 Set Vref, RX VrefLevel [Byte0]: 34
8611 10:02:00.102095 [Byte1]: 34
8612 10:02:00.106676
8613 10:02:00.106761 Set Vref, RX VrefLevel [Byte0]: 35
8614 10:02:00.109526 [Byte1]: 35
8615 10:02:00.114304
8616 10:02:00.114387 Set Vref, RX VrefLevel [Byte0]: 36
8617 10:02:00.117242 [Byte1]: 36
8618 10:02:00.121440
8619 10:02:00.121524 Set Vref, RX VrefLevel [Byte0]: 37
8620 10:02:00.125074 [Byte1]: 37
8621 10:02:00.129241
8622 10:02:00.129325 Set Vref, RX VrefLevel [Byte0]: 38
8623 10:02:00.132355 [Byte1]: 38
8624 10:02:00.136991
8625 10:02:00.137074 Set Vref, RX VrefLevel [Byte0]: 39
8626 10:02:00.140783 [Byte1]: 39
8627 10:02:00.144688
8628 10:02:00.144771 Set Vref, RX VrefLevel [Byte0]: 40
8629 10:02:00.147938 [Byte1]: 40
8630 10:02:00.152398
8631 10:02:00.152481 Set Vref, RX VrefLevel [Byte0]: 41
8632 10:02:00.155373 [Byte1]: 41
8633 10:02:00.159888
8634 10:02:00.159971 Set Vref, RX VrefLevel [Byte0]: 42
8635 10:02:00.163639 [Byte1]: 42
8636 10:02:00.167442
8637 10:02:00.167530 Set Vref, RX VrefLevel [Byte0]: 43
8638 10:02:00.170632 [Byte1]: 43
8639 10:02:00.175107
8640 10:02:00.175191 Set Vref, RX VrefLevel [Byte0]: 44
8641 10:02:00.178419 [Byte1]: 44
8642 10:02:00.182570
8643 10:02:00.182655 Set Vref, RX VrefLevel [Byte0]: 45
8644 10:02:00.185604 [Byte1]: 45
8645 10:02:00.190381
8646 10:02:00.190465 Set Vref, RX VrefLevel [Byte0]: 46
8647 10:02:00.193421 [Byte1]: 46
8648 10:02:00.197574
8649 10:02:00.197657 Set Vref, RX VrefLevel [Byte0]: 47
8650 10:02:00.201280 [Byte1]: 47
8651 10:02:00.205379
8652 10:02:00.205495 Set Vref, RX VrefLevel [Byte0]: 48
8653 10:02:00.208706 [Byte1]: 48
8654 10:02:00.213076
8655 10:02:00.213159 Set Vref, RX VrefLevel [Byte0]: 49
8656 10:02:00.216452 [Byte1]: 49
8657 10:02:00.220631
8658 10:02:00.220713 Set Vref, RX VrefLevel [Byte0]: 50
8659 10:02:00.223712 [Byte1]: 50
8660 10:02:00.227901
8661 10:02:00.227986 Set Vref, RX VrefLevel [Byte0]: 51
8662 10:02:00.231422 [Byte1]: 51
8663 10:02:00.235719
8664 10:02:00.235800 Set Vref, RX VrefLevel [Byte0]: 52
8665 10:02:00.239286 [Byte1]: 52
8666 10:02:00.243526
8667 10:02:00.243608 Set Vref, RX VrefLevel [Byte0]: 53
8668 10:02:00.246519 [Byte1]: 53
8669 10:02:00.251012
8670 10:02:00.251093 Set Vref, RX VrefLevel [Byte0]: 54
8671 10:02:00.254239 [Byte1]: 54
8672 10:02:00.258744
8673 10:02:00.258826 Set Vref, RX VrefLevel [Byte0]: 55
8674 10:02:00.262265 [Byte1]: 55
8675 10:02:00.266067
8676 10:02:00.266149 Set Vref, RX VrefLevel [Byte0]: 56
8677 10:02:00.269648 [Byte1]: 56
8678 10:02:00.273698
8679 10:02:00.273781 Set Vref, RX VrefLevel [Byte0]: 57
8680 10:02:00.277211 [Byte1]: 57
8681 10:02:00.281692
8682 10:02:00.281774 Set Vref, RX VrefLevel [Byte0]: 58
8683 10:02:00.284735 [Byte1]: 58
8684 10:02:00.289266
8685 10:02:00.289347 Set Vref, RX VrefLevel [Byte0]: 59
8686 10:02:00.292324 [Byte1]: 59
8687 10:02:00.296525
8688 10:02:00.296607 Set Vref, RX VrefLevel [Byte0]: 60
8689 10:02:00.300127 [Byte1]: 60
8690 10:02:00.304278
8691 10:02:00.304362 Set Vref, RX VrefLevel [Byte0]: 61
8692 10:02:00.307868 [Byte1]: 61
8693 10:02:00.312004
8694 10:02:00.312085 Set Vref, RX VrefLevel [Byte0]: 62
8695 10:02:00.315496 [Byte1]: 62
8696 10:02:00.319773
8697 10:02:00.319870 Set Vref, RX VrefLevel [Byte0]: 63
8698 10:02:00.323006 [Byte1]: 63
8699 10:02:00.327239
8700 10:02:00.327324 Set Vref, RX VrefLevel [Byte0]: 64
8701 10:02:00.330363 [Byte1]: 64
8702 10:02:00.334945
8703 10:02:00.335027 Set Vref, RX VrefLevel [Byte0]: 65
8704 10:02:00.341125 [Byte1]: 65
8705 10:02:00.341208
8706 10:02:00.344682 Set Vref, RX VrefLevel [Byte0]: 66
8707 10:02:00.347764 [Byte1]: 66
8708 10:02:00.347880
8709 10:02:00.351417 Set Vref, RX VrefLevel [Byte0]: 67
8710 10:02:00.354484 [Byte1]: 67
8711 10:02:00.354593
8712 10:02:00.358067 Set Vref, RX VrefLevel [Byte0]: 68
8713 10:02:00.361631 [Byte1]: 68
8714 10:02:00.365387
8715 10:02:00.365498 Set Vref, RX VrefLevel [Byte0]: 69
8716 10:02:00.368520 [Byte1]: 69
8717 10:02:00.372865
8718 10:02:00.372966 Set Vref, RX VrefLevel [Byte0]: 70
8719 10:02:00.376278 [Byte1]: 70
8720 10:02:00.380611
8721 10:02:00.380691 Set Vref, RX VrefLevel [Byte0]: 71
8722 10:02:00.383795 [Byte1]: 71
8723 10:02:00.388285
8724 10:02:00.388383 Set Vref, RX VrefLevel [Byte0]: 72
8725 10:02:00.391442 [Byte1]: 72
8726 10:02:00.395697
8727 10:02:00.395794 Set Vref, RX VrefLevel [Byte0]: 73
8728 10:02:00.398888 [Byte1]: 73
8729 10:02:00.403086
8730 10:02:00.403187 Set Vref, RX VrefLevel [Byte0]: 74
8731 10:02:00.406628 [Byte1]: 74
8732 10:02:00.410817
8733 10:02:00.410956 Final RX Vref Byte 0 = 57 to rank0
8734 10:02:00.414408 Final RX Vref Byte 1 = 59 to rank0
8735 10:02:00.417932 Final RX Vref Byte 0 = 57 to rank1
8736 10:02:00.421282 Final RX Vref Byte 1 = 59 to rank1==
8737 10:02:00.424073 Dram Type= 6, Freq= 0, CH_1, rank 0
8738 10:02:00.427995 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8739 10:02:00.431188 ==
8740 10:02:00.431301 DQS Delay:
8741 10:02:00.431397 DQS0 = 0, DQS1 = 0
8742 10:02:00.434129 DQM Delay:
8743 10:02:00.434234 DQM0 = 131, DQM1 = 124
8744 10:02:00.437803 DQ Delay:
8745 10:02:00.440811 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =130
8746 10:02:00.444503 DQ4 =130, DQ5 =142, DQ6 =144, DQ7 =128
8747 10:02:00.447503 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =118
8748 10:02:00.451181 DQ12 =134, DQ13 =132, DQ14 =130, DQ15 =132
8749 10:02:00.451283
8750 10:02:00.451392
8751 10:02:00.451482
8752 10:02:00.454066 [DramC_TX_OE_Calibration] TA2
8753 10:02:00.457692 Original DQ_B0 (3 6) =30, OEN = 27
8754 10:02:00.460762 Original DQ_B1 (3 6) =30, OEN = 27
8755 10:02:00.464442 24, 0x0, End_B0=24 End_B1=24
8756 10:02:00.464547 25, 0x0, End_B0=25 End_B1=25
8757 10:02:00.467376 26, 0x0, End_B0=26 End_B1=26
8758 10:02:00.471195 27, 0x0, End_B0=27 End_B1=27
8759 10:02:00.474560 28, 0x0, End_B0=28 End_B1=28
8760 10:02:00.474660 29, 0x0, End_B0=29 End_B1=29
8761 10:02:00.478083 30, 0x0, End_B0=30 End_B1=30
8762 10:02:00.481290 31, 0x4141, End_B0=30 End_B1=30
8763 10:02:00.484043 Byte0 end_step=30 best_step=27
8764 10:02:00.487962 Byte1 end_step=30 best_step=27
8765 10:02:00.491092 Byte0 TX OE(2T, 0.5T) = (3, 3)
8766 10:02:00.491175 Byte1 TX OE(2T, 0.5T) = (3, 3)
8767 10:02:00.491241
8768 10:02:00.491301
8769 10:02:00.501343 [DQSOSCAuto] RK0, (LSB)MR18= 0x1701, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
8770 10:02:00.504866 CH1 RK0: MR19=303, MR18=1701
8771 10:02:00.507883 CH1_RK0: MR19=0x303, MR18=0x1701, DQSOSC=398, MR23=63, INC=23, DEC=15
8772 10:02:00.511093
8773 10:02:00.514606 ----->DramcWriteLeveling(PI) begin...
8774 10:02:00.514690 ==
8775 10:02:00.517616 Dram Type= 6, Freq= 0, CH_1, rank 1
8776 10:02:00.521193 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8777 10:02:00.521337 ==
8778 10:02:00.524299 Write leveling (Byte 0): 24 => 24
8779 10:02:00.527808 Write leveling (Byte 1): 27 => 27
8780 10:02:00.531332 DramcWriteLeveling(PI) end<-----
8781 10:02:00.531445
8782 10:02:00.531539 ==
8783 10:02:00.534613 Dram Type= 6, Freq= 0, CH_1, rank 1
8784 10:02:00.537807 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8785 10:02:00.537942 ==
8786 10:02:00.540978 [Gating] SW mode calibration
8787 10:02:00.548090 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8788 10:02:00.554717 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8789 10:02:00.557685 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 10:02:00.561516 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8791 10:02:00.567488 1 4 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8792 10:02:00.571059 1 4 12 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
8793 10:02:00.574698 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8794 10:02:00.577663 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8795 10:02:00.584466 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8796 10:02:00.587838 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8797 10:02:00.591186 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8798 10:02:00.597702 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8799 10:02:00.601262 1 5 8 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
8800 10:02:00.604582 1 5 12 | B1->B0 | 2f2f 2424 | 0 0 | (1 0) (0 0)
8801 10:02:00.611644 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8802 10:02:00.614469 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8803 10:02:00.617817 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8804 10:02:00.624574 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8805 10:02:00.628075 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8806 10:02:00.631102 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8807 10:02:00.638218 1 6 8 | B1->B0 | 2727 3535 | 0 0 | (0 0) (0 0)
8808 10:02:00.641617 1 6 12 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
8809 10:02:00.644929 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8810 10:02:00.651158 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8811 10:02:00.654674 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8812 10:02:00.657747 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8813 10:02:00.664375 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8814 10:02:00.667994 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8815 10:02:00.670975 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8816 10:02:00.674532 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8817 10:02:00.681553 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8818 10:02:00.684983 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 10:02:00.687720 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 10:02:00.694237 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 10:02:00.698061 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 10:02:00.701023 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 10:02:00.707703 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 10:02:00.711188 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 10:02:00.714826 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 10:02:00.721293 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 10:02:00.724720 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 10:02:00.728178 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 10:02:00.734400 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 10:02:00.737718 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 10:02:00.741405 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8832 10:02:00.747893 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8833 10:02:00.751387 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8834 10:02:00.754339 Total UI for P1: 0, mck2ui 16
8835 10:02:00.758089 best dqsien dly found for B0: ( 1, 9, 10)
8836 10:02:00.761565 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8837 10:02:00.764638 Total UI for P1: 0, mck2ui 16
8838 10:02:00.768172 best dqsien dly found for B1: ( 1, 9, 14)
8839 10:02:00.771115 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8840 10:02:00.774905 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8841 10:02:00.775002
8842 10:02:00.777925 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8843 10:02:00.784483 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8844 10:02:00.784567 [Gating] SW calibration Done
8845 10:02:00.784631 ==
8846 10:02:00.788033 Dram Type= 6, Freq= 0, CH_1, rank 1
8847 10:02:00.794902 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8848 10:02:00.795000 ==
8849 10:02:00.795066 RX Vref Scan: 0
8850 10:02:00.795126
8851 10:02:00.797980 RX Vref 0 -> 0, step: 1
8852 10:02:00.798061
8853 10:02:00.801227 RX Delay 0 -> 252, step: 8
8854 10:02:00.804533 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8855 10:02:00.807680 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8856 10:02:00.811249 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8857 10:02:00.814560 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8858 10:02:00.821582 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8859 10:02:00.824502 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8860 10:02:00.827860 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8861 10:02:00.831034 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8862 10:02:00.834474 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8863 10:02:00.841313 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8864 10:02:00.844759 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8865 10:02:00.847672 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8866 10:02:00.851140 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8867 10:02:00.854611 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8868 10:02:00.861166 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8869 10:02:00.864491 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8870 10:02:00.864573 ==
8871 10:02:00.867739 Dram Type= 6, Freq= 0, CH_1, rank 1
8872 10:02:00.871242 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8873 10:02:00.871327 ==
8874 10:02:00.874330 DQS Delay:
8875 10:02:00.874444 DQS0 = 0, DQS1 = 0
8876 10:02:00.874508 DQM Delay:
8877 10:02:00.877854 DQM0 = 133, DQM1 = 128
8878 10:02:00.877935 DQ Delay:
8879 10:02:00.881507 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =135
8880 10:02:00.884420 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =127
8881 10:02:00.887990 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8882 10:02:00.894354 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =139
8883 10:02:00.894437
8884 10:02:00.894502
8885 10:02:00.894562 ==
8886 10:02:00.898066 Dram Type= 6, Freq= 0, CH_1, rank 1
8887 10:02:00.901110 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8888 10:02:00.901193 ==
8889 10:02:00.901258
8890 10:02:00.901318
8891 10:02:00.904782 TX Vref Scan disable
8892 10:02:00.904864 == TX Byte 0 ==
8893 10:02:00.911087 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8894 10:02:00.914350 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8895 10:02:00.914433 == TX Byte 1 ==
8896 10:02:00.921148 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8897 10:02:00.924369 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8898 10:02:00.924451 ==
8899 10:02:00.927942 Dram Type= 6, Freq= 0, CH_1, rank 1
8900 10:02:00.930973 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8901 10:02:00.931081 ==
8902 10:02:00.946232
8903 10:02:00.949688 TX Vref early break, caculate TX vref
8904 10:02:00.952901 TX Vref=16, minBit 8, minWin=22, winSum=379
8905 10:02:00.955988 TX Vref=18, minBit 8, minWin=23, winSum=385
8906 10:02:00.959519 TX Vref=20, minBit 8, minWin=23, winSum=395
8907 10:02:00.962523 TX Vref=22, minBit 8, minWin=23, winSum=402
8908 10:02:00.966116 TX Vref=24, minBit 15, minWin=24, winSum=415
8909 10:02:00.972925 TX Vref=26, minBit 0, minWin=26, winSum=425
8910 10:02:00.976202 TX Vref=28, minBit 11, minWin=25, winSum=425
8911 10:02:00.979292 TX Vref=30, minBit 5, minWin=25, winSum=425
8912 10:02:00.982948 TX Vref=32, minBit 0, minWin=24, winSum=416
8913 10:02:00.985911 TX Vref=34, minBit 9, minWin=24, winSum=408
8914 10:02:00.989452 TX Vref=36, minBit 9, minWin=24, winSum=402
8915 10:02:00.995951 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 26
8916 10:02:00.996035
8917 10:02:00.999571 Final TX Range 0 Vref 26
8918 10:02:00.999656
8919 10:02:00.999724 ==
8920 10:02:01.002588 Dram Type= 6, Freq= 0, CH_1, rank 1
8921 10:02:01.006270 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8922 10:02:01.006355 ==
8923 10:02:01.006421
8924 10:02:01.006481
8925 10:02:01.009729 TX Vref Scan disable
8926 10:02:01.016209 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8927 10:02:01.016292 == TX Byte 0 ==
8928 10:02:01.019745 u2DelayCellOfst[0]=14 cells (4 PI)
8929 10:02:01.023099 u2DelayCellOfst[1]=14 cells (4 PI)
8930 10:02:01.026155 u2DelayCellOfst[2]=0 cells (0 PI)
8931 10:02:01.029374 u2DelayCellOfst[3]=7 cells (2 PI)
8932 10:02:01.032946 u2DelayCellOfst[4]=7 cells (2 PI)
8933 10:02:01.036559 u2DelayCellOfst[5]=17 cells (5 PI)
8934 10:02:01.039483 u2DelayCellOfst[6]=17 cells (5 PI)
8935 10:02:01.039567 u2DelayCellOfst[7]=7 cells (2 PI)
8936 10:02:01.046070 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8937 10:02:01.049760 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8938 10:02:01.049845 == TX Byte 1 ==
8939 10:02:01.053205 u2DelayCellOfst[8]=0 cells (0 PI)
8940 10:02:01.056430 u2DelayCellOfst[9]=7 cells (2 PI)
8941 10:02:01.059656 u2DelayCellOfst[10]=14 cells (4 PI)
8942 10:02:01.062937 u2DelayCellOfst[11]=10 cells (3 PI)
8943 10:02:01.066037 u2DelayCellOfst[12]=17 cells (5 PI)
8944 10:02:01.069586 u2DelayCellOfst[13]=17 cells (5 PI)
8945 10:02:01.073284 u2DelayCellOfst[14]=21 cells (6 PI)
8946 10:02:01.076253 u2DelayCellOfst[15]=17 cells (5 PI)
8947 10:02:01.079571 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8948 10:02:01.086370 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8949 10:02:01.086453 DramC Write-DBI on
8950 10:02:01.086517 ==
8951 10:02:01.089929 Dram Type= 6, Freq= 0, CH_1, rank 1
8952 10:02:01.092833 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8953 10:02:01.092941 ==
8954 10:02:01.093033
8955 10:02:01.096515
8956 10:02:01.096596 TX Vref Scan disable
8957 10:02:01.100071 == TX Byte 0 ==
8958 10:02:01.103340 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8959 10:02:01.106491 == TX Byte 1 ==
8960 10:02:01.110012 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8961 10:02:01.110129 DramC Write-DBI off
8962 10:02:01.110247
8963 10:02:01.113094 [DATLAT]
8964 10:02:01.113204 Freq=1600, CH1 RK1
8965 10:02:01.113300
8966 10:02:01.116118 DATLAT Default: 0xf
8967 10:02:01.116220 0, 0xFFFF, sum = 0
8968 10:02:01.119754 1, 0xFFFF, sum = 0
8969 10:02:01.119940 2, 0xFFFF, sum = 0
8970 10:02:01.123503 3, 0xFFFF, sum = 0
8971 10:02:01.123639 4, 0xFFFF, sum = 0
8972 10:02:01.126386 5, 0xFFFF, sum = 0
8973 10:02:01.126471 6, 0xFFFF, sum = 0
8974 10:02:01.129658 7, 0xFFFF, sum = 0
8975 10:02:01.129782 8, 0xFFFF, sum = 0
8976 10:02:01.132997 9, 0xFFFF, sum = 0
8977 10:02:01.136445 10, 0xFFFF, sum = 0
8978 10:02:01.136527 11, 0xFFFF, sum = 0
8979 10:02:01.139721 12, 0xFFFF, sum = 0
8980 10:02:01.139804 13, 0xFFFF, sum = 0
8981 10:02:01.142821 14, 0x0, sum = 1
8982 10:02:01.142951 15, 0x0, sum = 2
8983 10:02:01.146451 16, 0x0, sum = 3
8984 10:02:01.146534 17, 0x0, sum = 4
8985 10:02:01.146662 best_step = 15
8986 10:02:01.149947
8987 10:02:01.150043 ==
8988 10:02:01.153120 Dram Type= 6, Freq= 0, CH_1, rank 1
8989 10:02:01.156444 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8990 10:02:01.156527 ==
8991 10:02:01.156593 RX Vref Scan: 0
8992 10:02:01.156653
8993 10:02:01.159692 RX Vref 0 -> 0, step: 1
8994 10:02:01.159774
8995 10:02:01.163184 RX Delay 11 -> 252, step: 4
8996 10:02:01.166338 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
8997 10:02:01.169658 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8998 10:02:01.176140 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8999 10:02:01.179693 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
9000 10:02:01.183535 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
9001 10:02:01.186191 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
9002 10:02:01.190070 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
9003 10:02:01.196571 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
9004 10:02:01.199578 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
9005 10:02:01.203361 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9006 10:02:01.206698 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9007 10:02:01.209649 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9008 10:02:01.216816 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
9009 10:02:01.219782 iDelay=195, Bit 13, Center 136 (87 ~ 186) 100
9010 10:02:01.223490 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
9011 10:02:01.226529 iDelay=195, Bit 15, Center 134 (83 ~ 186) 104
9012 10:02:01.226613 ==
9013 10:02:01.230158 Dram Type= 6, Freq= 0, CH_1, rank 1
9014 10:02:01.236577 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9015 10:02:01.236663 ==
9016 10:02:01.236730 DQS Delay:
9017 10:02:01.236792 DQS0 = 0, DQS1 = 0
9018 10:02:01.240237 DQM Delay:
9019 10:02:01.240321 DQM0 = 129, DQM1 = 126
9020 10:02:01.243461 DQ Delay:
9021 10:02:01.246570 DQ0 =132, DQ1 =126, DQ2 =116, DQ3 =126
9022 10:02:01.249814 DQ4 =128, DQ5 =144, DQ6 =138, DQ7 =124
9023 10:02:01.253432 DQ8 =112, DQ9 =112, DQ10 =128, DQ11 =120
9024 10:02:01.256396 DQ12 =134, DQ13 =136, DQ14 =136, DQ15 =134
9025 10:02:01.256479
9026 10:02:01.256545
9027 10:02:01.256606
9028 10:02:01.260096 [DramC_TX_OE_Calibration] TA2
9029 10:02:01.263283 Original DQ_B0 (3 6) =30, OEN = 27
9030 10:02:01.266669 Original DQ_B1 (3 6) =30, OEN = 27
9031 10:02:01.269886 24, 0x0, End_B0=24 End_B1=24
9032 10:02:01.269971 25, 0x0, End_B0=25 End_B1=25
9033 10:02:01.273192 26, 0x0, End_B0=26 End_B1=26
9034 10:02:01.276399 27, 0x0, End_B0=27 End_B1=27
9035 10:02:01.280076 28, 0x0, End_B0=28 End_B1=28
9036 10:02:01.280161 29, 0x0, End_B0=29 End_B1=29
9037 10:02:01.283489 30, 0x0, End_B0=30 End_B1=30
9038 10:02:01.286697 31, 0x4141, End_B0=30 End_B1=30
9039 10:02:01.290253 Byte0 end_step=30 best_step=27
9040 10:02:01.293238 Byte1 end_step=30 best_step=27
9041 10:02:01.296597 Byte0 TX OE(2T, 0.5T) = (3, 3)
9042 10:02:01.296679 Byte1 TX OE(2T, 0.5T) = (3, 3)
9043 10:02:01.296744
9044 10:02:01.296857
9045 10:02:01.307066 [DQSOSCAuto] RK1, (LSB)MR18= 0x1016, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
9046 10:02:01.309989 CH1 RK1: MR19=303, MR18=1016
9047 10:02:01.313493 CH1_RK1: MR19=0x303, MR18=0x1016, DQSOSC=398, MR23=63, INC=23, DEC=15
9048 10:02:01.317023 [RxdqsGatingPostProcess] freq 1600
9049 10:02:01.323649 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9050 10:02:01.326714 best DQS0 dly(2T, 0.5T) = (1, 1)
9051 10:02:01.330271 best DQS1 dly(2T, 0.5T) = (1, 1)
9052 10:02:01.333317 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9053 10:02:01.336848 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9054 10:02:01.340174 best DQS0 dly(2T, 0.5T) = (1, 1)
9055 10:02:01.343788 best DQS1 dly(2T, 0.5T) = (1, 1)
9056 10:02:01.343871 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9057 10:02:01.346712 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9058 10:02:01.350088 Pre-setting of DQS Precalculation
9059 10:02:01.357072 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9060 10:02:01.363965 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9061 10:02:01.370069 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9062 10:02:01.370152
9063 10:02:01.370217
9064 10:02:01.373529 [Calibration Summary] 3200 Mbps
9065 10:02:01.373611 CH 0, Rank 0
9066 10:02:01.377186 SW Impedance : PASS
9067 10:02:01.380133 DUTY Scan : NO K
9068 10:02:01.380269 ZQ Calibration : PASS
9069 10:02:01.383479 Jitter Meter : NO K
9070 10:02:01.387457 CBT Training : PASS
9071 10:02:01.387541 Write leveling : PASS
9072 10:02:01.390565 RX DQS gating : PASS
9073 10:02:01.393941 RX DQ/DQS(RDDQC) : PASS
9074 10:02:01.394025 TX DQ/DQS : PASS
9075 10:02:01.397390 RX DATLAT : PASS
9076 10:02:01.400481 RX DQ/DQS(Engine): PASS
9077 10:02:01.400565 TX OE : PASS
9078 10:02:01.400632 All Pass.
9079 10:02:01.400694
9080 10:02:01.403683 CH 0, Rank 1
9081 10:02:01.403770 SW Impedance : PASS
9082 10:02:01.406993 DUTY Scan : NO K
9083 10:02:01.410597 ZQ Calibration : PASS
9084 10:02:01.410711 Jitter Meter : NO K
9085 10:02:01.413681 CBT Training : PASS
9086 10:02:01.417142 Write leveling : PASS
9087 10:02:01.417227 RX DQS gating : PASS
9088 10:02:01.420768 RX DQ/DQS(RDDQC) : PASS
9089 10:02:01.423754 TX DQ/DQS : PASS
9090 10:02:01.423839 RX DATLAT : PASS
9091 10:02:01.427409 RX DQ/DQS(Engine): PASS
9092 10:02:01.430995 TX OE : PASS
9093 10:02:01.431080 All Pass.
9094 10:02:01.431146
9095 10:02:01.431208 CH 1, Rank 0
9096 10:02:01.433951 SW Impedance : PASS
9097 10:02:01.437576 DUTY Scan : NO K
9098 10:02:01.437660 ZQ Calibration : PASS
9099 10:02:01.440531 Jitter Meter : NO K
9100 10:02:01.440645 CBT Training : PASS
9101 10:02:01.443952 Write leveling : PASS
9102 10:02:01.447551 RX DQS gating : PASS
9103 10:02:01.447635 RX DQ/DQS(RDDQC) : PASS
9104 10:02:01.450714 TX DQ/DQS : PASS
9105 10:02:01.454122 RX DATLAT : PASS
9106 10:02:01.454204 RX DQ/DQS(Engine): PASS
9107 10:02:01.457119 TX OE : PASS
9108 10:02:01.457203 All Pass.
9109 10:02:01.457269
9110 10:02:01.460616 CH 1, Rank 1
9111 10:02:01.460700 SW Impedance : PASS
9112 10:02:01.463969 DUTY Scan : NO K
9113 10:02:01.467188 ZQ Calibration : PASS
9114 10:02:01.467271 Jitter Meter : NO K
9115 10:02:01.470739 CBT Training : PASS
9116 10:02:01.473921 Write leveling : PASS
9117 10:02:01.474004 RX DQS gating : PASS
9118 10:02:01.477469 RX DQ/DQS(RDDQC) : PASS
9119 10:02:01.480822 TX DQ/DQS : PASS
9120 10:02:01.480906 RX DATLAT : PASS
9121 10:02:01.483753 RX DQ/DQS(Engine): PASS
9122 10:02:01.483838 TX OE : PASS
9123 10:02:01.487041 All Pass.
9124 10:02:01.487125
9125 10:02:01.487191 DramC Write-DBI on
9126 10:02:01.490699 PER_BANK_REFRESH: Hybrid Mode
9127 10:02:01.503420 TX_TRACKING: ON
9128 10:02:01.503533 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9129 10:02:01.510357 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9130 10:02:01.517177 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9131 10:02:01.520888 [FAST_K] Save calibration result to emmc
9132 10:02:01.524200 sync common calibartion params.
9133 10:02:01.524291 sync cbt_mode0:1, 1:1
9134 10:02:01.527181 dram_init: ddr_geometry: 2
9135 10:02:01.530817 dram_init: ddr_geometry: 2
9136 10:02:01.530910 dram_init: ddr_geometry: 2
9137 10:02:01.533824 0:dram_rank_size:100000000
9138 10:02:01.537487 1:dram_rank_size:100000000
9139 10:02:01.544199 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9140 10:02:01.544300 DFS_SHUFFLE_HW_MODE: ON
9141 10:02:01.547177 dramc_set_vcore_voltage set vcore to 725000
9142 10:02:01.550596 Read voltage for 1600, 0
9143 10:02:01.550670 Vio18 = 0
9144 10:02:01.554277 Vcore = 725000
9145 10:02:01.554351 Vdram = 0
9146 10:02:01.554415 Vddq = 0
9147 10:02:01.557103 Vmddr = 0
9148 10:02:01.557205 switch to 3200 Mbps bootup
9149 10:02:01.560732 [DramcRunTimeConfig]
9150 10:02:01.560813 PHYPLL
9151 10:02:01.564242 DPM_CONTROL_AFTERK: ON
9152 10:02:01.564325 PER_BANK_REFRESH: ON
9153 10:02:01.567213 REFRESH_OVERHEAD_REDUCTION: ON
9154 10:02:01.570616 CMD_PICG_NEW_MODE: OFF
9155 10:02:01.570725 XRTWTW_NEW_MODE: ON
9156 10:02:01.573974 XRTRTR_NEW_MODE: ON
9157 10:02:01.574059 TX_TRACKING: ON
9158 10:02:01.577376 RDSEL_TRACKING: OFF
9159 10:02:01.580443 DQS Precalculation for DVFS: ON
9160 10:02:01.580521 RX_TRACKING: OFF
9161 10:02:01.584004 HW_GATING DBG: ON
9162 10:02:01.584078 ZQCS_ENABLE_LP4: ON
9163 10:02:01.587479 RX_PICG_NEW_MODE: ON
9164 10:02:01.587551 TX_PICG_NEW_MODE: ON
9165 10:02:01.590559 ENABLE_RX_DCM_DPHY: ON
9166 10:02:01.594126 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9167 10:02:01.597172 DUMMY_READ_FOR_TRACKING: OFF
9168 10:02:01.597245 !!! SPM_CONTROL_AFTERK: OFF
9169 10:02:01.600444 !!! SPM could not control APHY
9170 10:02:01.604002 IMPEDANCE_TRACKING: ON
9171 10:02:01.604103 TEMP_SENSOR: ON
9172 10:02:01.607481 HW_SAVE_FOR_SR: OFF
9173 10:02:01.610888 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9174 10:02:01.614309 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9175 10:02:01.614381 Read ODT Tracking: ON
9176 10:02:01.617132 Refresh Rate DeBounce: ON
9177 10:02:01.621003 DFS_NO_QUEUE_FLUSH: ON
9178 10:02:01.623784 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9179 10:02:01.623858 ENABLE_DFS_RUNTIME_MRW: OFF
9180 10:02:01.627574 DDR_RESERVE_NEW_MODE: ON
9181 10:02:01.630710 MR_CBT_SWITCH_FREQ: ON
9182 10:02:01.630808 =========================
9183 10:02:01.651064 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9184 10:02:01.654519 dram_init: ddr_geometry: 2
9185 10:02:01.672490 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9186 10:02:01.676160 dram_init: dram init end (result: 0)
9187 10:02:01.682340 DRAM-K: Full calibration passed in 24612 msecs
9188 10:02:01.686175 MRC: failed to locate region type 0.
9189 10:02:01.686258 DRAM rank0 size:0x100000000,
9190 10:02:01.688971 DRAM rank1 size=0x100000000
9191 10:02:01.699550 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9192 10:02:01.705879 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9193 10:02:01.712818 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9194 10:02:01.719163 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9195 10:02:01.722816 DRAM rank0 size:0x100000000,
9196 10:02:01.725722 DRAM rank1 size=0x100000000
9197 10:02:01.725795 CBMEM:
9198 10:02:01.729652 IMD: root @ 0xfffff000 254 entries.
9199 10:02:01.732476 IMD: root @ 0xffffec00 62 entries.
9200 10:02:01.736182 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9201 10:02:01.739251 WARNING: RO_VPD is uninitialized or empty.
9202 10:02:01.745723 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9203 10:02:01.752336 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9204 10:02:01.765352 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9205 10:02:01.776609 BS: romstage times (exec / console): total (unknown) / 24113 ms
9206 10:02:01.776693
9207 10:02:01.776758
9208 10:02:01.786700 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9209 10:02:01.790125 ARM64: Exception handlers installed.
9210 10:02:01.793390 ARM64: Testing exception
9211 10:02:01.796819 ARM64: Done test exception
9212 10:02:01.796927 Enumerating buses...
9213 10:02:01.799803 Show all devs... Before device enumeration.
9214 10:02:01.803403 Root Device: enabled 1
9215 10:02:01.806481 CPU_CLUSTER: 0: enabled 1
9216 10:02:01.806563 CPU: 00: enabled 1
9217 10:02:01.810115 Compare with tree...
9218 10:02:01.810196 Root Device: enabled 1
9219 10:02:01.813573 CPU_CLUSTER: 0: enabled 1
9220 10:02:01.816889 CPU: 00: enabled 1
9221 10:02:01.816971 Root Device scanning...
9222 10:02:01.819783 scan_static_bus for Root Device
9223 10:02:01.823315 CPU_CLUSTER: 0 enabled
9224 10:02:01.827071 scan_static_bus for Root Device done
9225 10:02:01.830446 scan_bus: bus Root Device finished in 8 msecs
9226 10:02:01.830571 done
9227 10:02:01.836969 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9228 10:02:01.840503 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9229 10:02:01.846964 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9230 10:02:01.850143 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9231 10:02:01.853553 Allocating resources...
9232 10:02:01.853680 Reading resources...
9233 10:02:01.857146 Root Device read_resources bus 0 link: 0
9234 10:02:01.860026 DRAM rank0 size:0x100000000,
9235 10:02:01.863482 DRAM rank1 size=0x100000000
9236 10:02:01.867040 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9237 10:02:01.870004 CPU: 00 missing read_resources
9238 10:02:01.873644 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9239 10:02:01.880106 Root Device read_resources bus 0 link: 0 done
9240 10:02:01.880181 Done reading resources.
9241 10:02:01.886726 Show resources in subtree (Root Device)...After reading.
9242 10:02:01.890435 Root Device child on link 0 CPU_CLUSTER: 0
9243 10:02:01.893448 CPU_CLUSTER: 0 child on link 0 CPU: 00
9244 10:02:01.903550 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9245 10:02:01.903640 CPU: 00
9246 10:02:01.906665 Root Device assign_resources, bus 0 link: 0
9247 10:02:01.910175 CPU_CLUSTER: 0 missing set_resources
9248 10:02:01.913768 Root Device assign_resources, bus 0 link: 0 done
9249 10:02:01.916834 Done setting resources.
9250 10:02:01.923433 Show resources in subtree (Root Device)...After assigning values.
9251 10:02:01.926783 Root Device child on link 0 CPU_CLUSTER: 0
9252 10:02:01.930119 CPU_CLUSTER: 0 child on link 0 CPU: 00
9253 10:02:01.940436 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9254 10:02:01.940514 CPU: 00
9255 10:02:01.943745 Done allocating resources.
9256 10:02:01.946678 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9257 10:02:01.950427 Enabling resources...
9258 10:02:01.950526 done.
9259 10:02:01.953945 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9260 10:02:01.956779 Initializing devices...
9261 10:02:01.960520 Root Device init
9262 10:02:01.960602 init hardware done!
9263 10:02:01.963550 0x00000018: ctrlr->caps
9264 10:02:01.963635 52.000 MHz: ctrlr->f_max
9265 10:02:01.967001 0.400 MHz: ctrlr->f_min
9266 10:02:01.970223 0x40ff8080: ctrlr->voltages
9267 10:02:01.970306 sclk: 390625
9268 10:02:01.973669 Bus Width = 1
9269 10:02:01.973751 sclk: 390625
9270 10:02:01.973815 Bus Width = 1
9271 10:02:01.976883 Early init status = 3
9272 10:02:01.980105 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9273 10:02:01.984220 in-header: 03 fc 00 00 01 00 00 00
9274 10:02:01.987889 in-data: 00
9275 10:02:01.990854 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9276 10:02:01.995739 in-header: 03 fd 00 00 00 00 00 00
9277 10:02:01.998724 in-data:
9278 10:02:02.002341 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9279 10:02:02.005408 in-header: 03 fc 00 00 01 00 00 00
9280 10:02:02.009141 in-data: 00
9281 10:02:02.012630 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9282 10:02:02.017056 in-header: 03 fd 00 00 00 00 00 00
9283 10:02:02.020659 in-data:
9284 10:02:02.023689 [SSUSB] Setting up USB HOST controller...
9285 10:02:02.027290 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9286 10:02:02.030327 [SSUSB] phy power-on done.
9287 10:02:02.033953 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9288 10:02:02.040765 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9289 10:02:02.043890 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9290 10:02:02.050517 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9291 10:02:02.057405 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9292 10:02:02.064321 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9293 10:02:02.070615 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9294 10:02:02.077220 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9295 10:02:02.080168 SPM: binary array size = 0x9dc
9296 10:02:02.083799 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9297 10:02:02.090698 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9298 10:02:02.097556 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9299 10:02:02.100492 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9300 10:02:02.103646 configure_display: Starting display init
9301 10:02:02.140608 anx7625_power_on_init: Init interface.
9302 10:02:02.143624 anx7625_disable_pd_protocol: Disabled PD feature.
9303 10:02:02.147141 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9304 10:02:02.175104 anx7625_start_dp_work: Secure OCM version=00
9305 10:02:02.178076 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9306 10:02:02.192897 sp_tx_get_edid_block: EDID Block = 1
9307 10:02:02.295662 Extracted contents:
9308 10:02:02.298604 header: 00 ff ff ff ff ff ff 00
9309 10:02:02.302118 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9310 10:02:02.305438 version: 01 04
9311 10:02:02.308955 basic params: 95 1f 11 78 0a
9312 10:02:02.312006 chroma info: 76 90 94 55 54 90 27 21 50 54
9313 10:02:02.315511 established: 00 00 00
9314 10:02:02.322213 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9315 10:02:02.325329 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9316 10:02:02.332395 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9317 10:02:02.339022 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9318 10:02:02.345647 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9319 10:02:02.349011 extensions: 00
9320 10:02:02.349098 checksum: fb
9321 10:02:02.349165
9322 10:02:02.351986 Manufacturer: IVO Model 57d Serial Number 0
9323 10:02:02.355610 Made week 0 of 2020
9324 10:02:02.355688 EDID version: 1.4
9325 10:02:02.358565 Digital display
9326 10:02:02.362247 6 bits per primary color channel
9327 10:02:02.362322 DisplayPort interface
9328 10:02:02.365851 Maximum image size: 31 cm x 17 cm
9329 10:02:02.365927 Gamma: 220%
9330 10:02:02.368902 Check DPMS levels
9331 10:02:02.371990 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9332 10:02:02.375543 First detailed timing is preferred timing
9333 10:02:02.378848 Established timings supported:
9334 10:02:02.382407 Standard timings supported:
9335 10:02:02.382481 Detailed timings
9336 10:02:02.388961 Hex of detail: 383680a07038204018303c0035ae10000019
9337 10:02:02.392045 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9338 10:02:02.395426 0780 0798 07c8 0820 hborder 0
9339 10:02:02.401967 0438 043b 0447 0458 vborder 0
9340 10:02:02.402046 -hsync -vsync
9341 10:02:02.405460 Did detailed timing
9342 10:02:02.408880 Hex of detail: 000000000000000000000000000000000000
9343 10:02:02.412099 Manufacturer-specified data, tag 0
9344 10:02:02.418656 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9345 10:02:02.418762 ASCII string: InfoVision
9346 10:02:02.425407 Hex of detail: 000000fe00523134304e574635205248200a
9347 10:02:02.425488 ASCII string: R140NWF5 RH
9348 10:02:02.429073 Checksum
9349 10:02:02.429146 Checksum: 0xfb (valid)
9350 10:02:02.435566 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9351 10:02:02.435643 DSI data_rate: 832800000 bps
9352 10:02:02.442855 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9353 10:02:02.446532 anx7625_parse_edid: pixelclock(138800).
9354 10:02:02.449485 hactive(1920), hsync(48), hfp(24), hbp(88)
9355 10:02:02.453598 vactive(1080), vsync(12), vfp(3), vbp(17)
9356 10:02:02.456617 anx7625_dsi_config: config dsi.
9357 10:02:02.463222 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9358 10:02:02.477592 anx7625_dsi_config: success to config DSI
9359 10:02:02.480601 anx7625_dp_start: MIPI phy setup OK.
9360 10:02:02.484095 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9361 10:02:02.487611 mtk_ddp_mode_set invalid vrefresh 60
9362 10:02:02.490791 main_disp_path_setup
9363 10:02:02.490894 ovl_layer_smi_id_en
9364 10:02:02.494395 ovl_layer_smi_id_en
9365 10:02:02.494464 ccorr_config
9366 10:02:02.494529 aal_config
9367 10:02:02.497657 gamma_config
9368 10:02:02.497729 postmask_config
9369 10:02:02.500972 dither_config
9370 10:02:02.504744 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9371 10:02:02.510845 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9372 10:02:02.514525 Root Device init finished in 551 msecs
9373 10:02:02.514609 CPU_CLUSTER: 0 init
9374 10:02:02.524379 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9375 10:02:02.527486 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9376 10:02:02.530988 APU_MBOX 0x190000b0 = 0x10001
9377 10:02:02.534660 APU_MBOX 0x190001b0 = 0x10001
9378 10:02:02.537597 APU_MBOX 0x190005b0 = 0x10001
9379 10:02:02.540748 APU_MBOX 0x190006b0 = 0x10001
9380 10:02:02.544142 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9381 10:02:02.556741 read SPI 0x539f4 0xe237: 6250 us, 9265 KB/s, 74.120 Mbps
9382 10:02:02.568882 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9383 10:02:02.575856 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9384 10:02:02.587496 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9385 10:02:02.596546 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9386 10:02:02.599880 CPU_CLUSTER: 0 init finished in 81 msecs
9387 10:02:02.602812 Devices initialized
9388 10:02:02.606392 Show all devs... After init.
9389 10:02:02.606492 Root Device: enabled 1
9390 10:02:02.609476 CPU_CLUSTER: 0: enabled 1
9391 10:02:02.612804 CPU: 00: enabled 1
9392 10:02:02.616155 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9393 10:02:02.619468 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9394 10:02:02.623227 ELOG: NV offset 0x57f000 size 0x1000
9395 10:02:02.630063 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9396 10:02:02.636688 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9397 10:02:02.639677 ELOG: Event(17) added with size 13 at 2023-11-24 10:02:02 UTC
9398 10:02:02.643087 out: cmd=0x121: 03 db 21 01 00 00 00 00
9399 10:02:02.647339 in-header: 03 b5 00 00 2c 00 00 00
9400 10:02:02.660084 in-data: aa 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9401 10:02:02.667116 ELOG: Event(A1) added with size 10 at 2023-11-24 10:02:02 UTC
9402 10:02:02.673630 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9403 10:02:02.680175 ELOG: Event(A0) added with size 9 at 2023-11-24 10:02:02 UTC
9404 10:02:02.683669 elog_add_boot_reason: Logged dev mode boot
9405 10:02:02.686699 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9406 10:02:02.690658 Finalize devices...
9407 10:02:02.690775 Devices finalized
9408 10:02:02.696922 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9409 10:02:02.700304 Writing coreboot table at 0xffe64000
9410 10:02:02.703639 0. 000000000010a000-0000000000113fff: RAMSTAGE
9411 10:02:02.706969 1. 0000000040000000-00000000400fffff: RAM
9412 10:02:02.710467 2. 0000000040100000-000000004032afff: RAMSTAGE
9413 10:02:02.716934 3. 000000004032b000-00000000545fffff: RAM
9414 10:02:02.720476 4. 0000000054600000-000000005465ffff: BL31
9415 10:02:02.723466 5. 0000000054660000-00000000ffe63fff: RAM
9416 10:02:02.730056 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9417 10:02:02.733398 7. 0000000100000000-000000023fffffff: RAM
9418 10:02:02.733481 Passing 5 GPIOs to payload:
9419 10:02:02.740385 NAME | PORT | POLARITY | VALUE
9420 10:02:02.743469 EC in RW | 0x000000aa | low | undefined
9421 10:02:02.750148 EC interrupt | 0x00000005 | low | undefined
9422 10:02:02.753649 TPM interrupt | 0x000000ab | high | undefined
9423 10:02:02.757226 SD card detect | 0x00000011 | high | undefined
9424 10:02:02.763309 speaker enable | 0x00000093 | high | undefined
9425 10:02:02.766864 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9426 10:02:02.770461 in-header: 03 f9 00 00 02 00 00 00
9427 10:02:02.770545 in-data: 02 00
9428 10:02:02.773518 ADC[4]: Raw value=900221 ID=7
9429 10:02:02.776981 ADC[3]: Raw value=213336 ID=1
9430 10:02:02.777065 RAM Code: 0x71
9431 10:02:02.780197 ADC[6]: Raw value=74557 ID=0
9432 10:02:02.783905 ADC[5]: Raw value=211860 ID=1
9433 10:02:02.783989 SKU Code: 0x1
9434 10:02:02.790496 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 5bd5
9435 10:02:02.793687 coreboot table: 964 bytes.
9436 10:02:02.796955 IMD ROOT 0. 0xfffff000 0x00001000
9437 10:02:02.800241 IMD SMALL 1. 0xffffe000 0x00001000
9438 10:02:02.804063 RO MCACHE 2. 0xffffc000 0x00001104
9439 10:02:02.807421 CONSOLE 3. 0xfff7c000 0x00080000
9440 10:02:02.810118 FMAP 4. 0xfff7b000 0x00000452
9441 10:02:02.813570 TIME STAMP 5. 0xfff7a000 0x00000910
9442 10:02:02.817058 VBOOT WORK 6. 0xfff66000 0x00014000
9443 10:02:02.820635 RAMOOPS 7. 0xffe66000 0x00100000
9444 10:02:02.824105 COREBOOT 8. 0xffe64000 0x00002000
9445 10:02:02.824188 IMD small region:
9446 10:02:02.827135 IMD ROOT 0. 0xffffec00 0x00000400
9447 10:02:02.830710 VPD 1. 0xffffeb80 0x0000006c
9448 10:02:02.833719 MMC STATUS 2. 0xffffeb60 0x00000004
9449 10:02:02.840423 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9450 10:02:02.840506 Probing TPM: done!
9451 10:02:02.847197 Connected to device vid:did:rid of 1ae0:0028:00
9452 10:02:02.854022 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9453 10:02:02.857272 Initialized TPM device CR50 revision 0
9454 10:02:02.860999 Checking cr50 for pending updates
9455 10:02:02.866255 Reading cr50 TPM mode
9456 10:02:02.875312 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9457 10:02:02.881862 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9458 10:02:02.921920 read SPI 0x3990ec 0x4f1b0: 34859 us, 9295 KB/s, 74.360 Mbps
9459 10:02:02.925320 Checking segment from ROM address 0x40100000
9460 10:02:02.928992 Checking segment from ROM address 0x4010001c
9461 10:02:02.935603 Loading segment from ROM address 0x40100000
9462 10:02:02.935687 code (compression=0)
9463 10:02:02.942106 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9464 10:02:02.952267 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9465 10:02:02.952394 it's not compressed!
9466 10:02:02.958746 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9467 10:02:02.962329 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9468 10:02:02.982548 Loading segment from ROM address 0x4010001c
9469 10:02:02.982642 Entry Point 0x80000000
9470 10:02:02.986144 Loaded segments
9471 10:02:02.989167 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9472 10:02:02.995686 Jumping to boot code at 0x80000000(0xffe64000)
9473 10:02:03.002656 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9474 10:02:03.009024 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9475 10:02:03.016843 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9476 10:02:03.020563 Checking segment from ROM address 0x40100000
9477 10:02:03.023406 Checking segment from ROM address 0x4010001c
9478 10:02:03.026654 Loading segment from ROM address 0x40100000
9479 10:02:03.030102 code (compression=1)
9480 10:02:03.037026 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9481 10:02:03.046654 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9482 10:02:03.046733 using LZMA
9483 10:02:03.054987 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9484 10:02:03.062014 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9485 10:02:03.065113 Loading segment from ROM address 0x4010001c
9486 10:02:03.065198 Entry Point 0x54601000
9487 10:02:03.068726 Loaded segments
9488 10:02:03.071799 NOTICE: MT8192 bl31_setup
9489 10:02:03.078530 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9490 10:02:03.082006 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9491 10:02:03.085284 WARNING: region 0:
9492 10:02:03.089256 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9493 10:02:03.089357 WARNING: region 1:
9494 10:02:03.095669 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9495 10:02:03.095771 WARNING: region 2:
9496 10:02:03.102547 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9497 10:02:03.105528 WARNING: region 3:
9498 10:02:03.108996 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9499 10:02:03.112377 WARNING: region 4:
9500 10:02:03.115799 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9501 10:02:03.119465 WARNING: region 5:
9502 10:02:03.122286 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9503 10:02:03.125948 WARNING: region 6:
9504 10:02:03.128978 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9505 10:02:03.129076 WARNING: region 7:
9506 10:02:03.135748 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9507 10:02:03.139427 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9508 10:02:03.146216 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9509 10:02:03.149196 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9510 10:02:03.152900 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9511 10:02:03.159399 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9512 10:02:03.162523 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9513 10:02:03.169664 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9514 10:02:03.172676 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9515 10:02:03.176254 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9516 10:02:03.182785 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9517 10:02:03.186488 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9518 10:02:03.189529 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9519 10:02:03.196320 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9520 10:02:03.199626 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9521 10:02:03.203112 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9522 10:02:03.210164 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9523 10:02:03.212962 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9524 10:02:03.216576 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9525 10:02:03.223090 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9526 10:02:03.226327 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9527 10:02:03.233106 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9528 10:02:03.236734 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9529 10:02:03.239961 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9530 10:02:03.247035 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9531 10:02:03.250250 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9532 10:02:03.253635 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9533 10:02:03.260444 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9534 10:02:03.263541 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9535 10:02:03.270454 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9536 10:02:03.273397 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9537 10:02:03.277122 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9538 10:02:03.283796 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9539 10:02:03.286881 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9540 10:02:03.290457 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9541 10:02:03.294105 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9542 10:02:03.300677 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9543 10:02:03.303630 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9544 10:02:03.307229 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9545 10:02:03.310712 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9546 10:02:03.317127 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9547 10:02:03.320561 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9548 10:02:03.323706 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9549 10:02:03.327214 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9550 10:02:03.334118 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9551 10:02:03.337650 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9552 10:02:03.340989 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9553 10:02:03.344046 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9554 10:02:03.350648 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9555 10:02:03.354070 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9556 10:02:03.357944 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9557 10:02:03.364407 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9558 10:02:03.367886 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9559 10:02:03.374546 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9560 10:02:03.377804 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9561 10:02:03.381562 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9562 10:02:03.388198 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9563 10:02:03.391857 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9564 10:02:03.397983 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9565 10:02:03.401601 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9566 10:02:03.408238 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9567 10:02:03.411684 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9568 10:02:03.414692 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9569 10:02:03.421722 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9570 10:02:03.424866 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9571 10:02:03.431534 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9572 10:02:03.434936 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9573 10:02:03.441824 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9574 10:02:03.445375 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9575 10:02:03.448297 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9576 10:02:03.455227 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9577 10:02:03.458710 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9578 10:02:03.465233 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9579 10:02:03.469032 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9580 10:02:03.472498 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9581 10:02:03.478662 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9582 10:02:03.482242 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9583 10:02:03.488895 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9584 10:02:03.492475 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9585 10:02:03.499138 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9586 10:02:03.502084 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9587 10:02:03.505789 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9588 10:02:03.512330 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9589 10:02:03.515828 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9590 10:02:03.522388 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9591 10:02:03.525869 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9592 10:02:03.529616 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9593 10:02:03.536262 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9594 10:02:03.539273 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9595 10:02:03.546171 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9596 10:02:03.549585 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9597 10:02:03.555938 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9598 10:02:03.559575 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9599 10:02:03.563026 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9600 10:02:03.569583 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9601 10:02:03.572789 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9602 10:02:03.579424 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9603 10:02:03.583120 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9604 10:02:03.586084 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9605 10:02:03.590031 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9606 10:02:03.596266 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9607 10:02:03.599922 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9608 10:02:03.602997 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9609 10:02:03.609607 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9610 10:02:03.613156 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9611 10:02:03.619748 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9612 10:02:03.623372 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9613 10:02:03.626373 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9614 10:02:03.633495 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9615 10:02:03.636833 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9616 10:02:03.639794 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9617 10:02:03.646669 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9618 10:02:03.650225 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9619 10:02:03.657021 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9620 10:02:03.660604 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9621 10:02:03.663525 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9622 10:02:03.670692 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9623 10:02:03.674128 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9624 10:02:03.677120 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9625 10:02:03.683767 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9626 10:02:03.687146 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9627 10:02:03.690713 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9628 10:02:03.694239 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9629 10:02:03.697149 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9630 10:02:03.704130 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9631 10:02:03.707551 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9632 10:02:03.710792 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9633 10:02:03.717889 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9634 10:02:03.720950 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9635 10:02:03.727519 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9636 10:02:03.731147 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9637 10:02:03.734232 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9638 10:02:03.741262 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9639 10:02:03.744520 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9640 10:02:03.747660 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9641 10:02:03.754754 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9642 10:02:03.757958 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9643 10:02:03.764750 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9644 10:02:03.768209 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9645 10:02:03.771533 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9646 10:02:03.778060 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9647 10:02:03.781554 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9648 10:02:03.785097 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9649 10:02:03.791499 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9650 10:02:03.794938 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9651 10:02:03.798536 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9652 10:02:03.805317 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9653 10:02:03.808539 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9654 10:02:03.814993 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9655 10:02:03.818638 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9656 10:02:03.821855 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9657 10:02:03.828466 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9658 10:02:03.831931 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9659 10:02:03.835494 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9660 10:02:03.842081 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9661 10:02:03.845631 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9662 10:02:03.851846 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9663 10:02:03.855509 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9664 10:02:03.859177 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9665 10:02:03.865248 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9666 10:02:03.868762 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9667 10:02:03.872393 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9668 10:02:03.879084 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9669 10:02:03.882297 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9670 10:02:03.888714 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9671 10:02:03.892069 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9672 10:02:03.895750 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9673 10:02:03.902251 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9674 10:02:03.905372 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9675 10:02:03.912305 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9676 10:02:03.915782 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9677 10:02:03.918888 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9678 10:02:03.925597 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9679 10:02:03.929387 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9680 10:02:03.932253 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9681 10:02:03.938804 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9682 10:02:03.942452 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9683 10:02:03.948779 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9684 10:02:03.952264 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9685 10:02:03.955655 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9686 10:02:03.962253 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9687 10:02:03.965930 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9688 10:02:03.968921 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9689 10:02:03.975569 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9690 10:02:03.979140 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9691 10:02:03.985684 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9692 10:02:03.989156 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9693 10:02:03.992639 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9694 10:02:03.999095 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9695 10:02:04.002306 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9696 10:02:04.009266 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9697 10:02:04.012627 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9698 10:02:04.015974 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9699 10:02:04.022640 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9700 10:02:04.026280 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9701 10:02:04.032871 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9702 10:02:04.035890 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9703 10:02:04.039469 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9704 10:02:04.046088 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9705 10:02:04.049641 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9706 10:02:04.056006 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9707 10:02:04.059406 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9708 10:02:04.062812 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9709 10:02:04.069710 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9710 10:02:04.073000 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9711 10:02:04.079744 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9712 10:02:04.082748 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9713 10:02:04.089454 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9714 10:02:04.093065 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9715 10:02:04.096101 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9716 10:02:04.102906 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9717 10:02:04.106536 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9718 10:02:04.112510 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9719 10:02:04.116415 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9720 10:02:04.119903 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9721 10:02:04.126224 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9722 10:02:04.129490 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9723 10:02:04.136448 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9724 10:02:04.139531 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9725 10:02:04.142571 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9726 10:02:04.149241 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9727 10:02:04.153025 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9728 10:02:04.159507 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9729 10:02:04.162806 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9730 10:02:04.166054 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9731 10:02:04.173023 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9732 10:02:04.176535 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9733 10:02:04.182718 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9734 10:02:04.186330 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9735 10:02:04.192590 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9736 10:02:04.196216 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9737 10:02:04.199250 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9738 10:02:04.202823 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9739 10:02:04.206133 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9740 10:02:04.212954 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9741 10:02:04.216086 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9742 10:02:04.219689 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9743 10:02:04.226376 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9744 10:02:04.229936 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9745 10:02:04.233227 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9746 10:02:04.239236 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9747 10:02:04.242802 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9748 10:02:04.249724 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9749 10:02:04.252810 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9750 10:02:04.256406 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9751 10:02:04.263075 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9752 10:02:04.266121 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9753 10:02:04.269676 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9754 10:02:04.276211 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9755 10:02:04.279868 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9756 10:02:04.282840 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9757 10:02:04.289870 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9758 10:02:04.293165 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9759 10:02:04.296617 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9760 10:02:04.302842 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9761 10:02:04.306459 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9762 10:02:04.313155 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9763 10:02:04.316511 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9764 10:02:04.319892 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9765 10:02:04.326498 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9766 10:02:04.329412 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9767 10:02:04.333125 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9768 10:02:04.339635 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9769 10:02:04.342750 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9770 10:02:04.346294 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9771 10:02:04.352902 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9772 10:02:04.356471 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9773 10:02:04.362991 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9774 10:02:04.365975 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9775 10:02:04.369228 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9776 10:02:04.372800 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9777 10:02:04.379381 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9778 10:02:04.383046 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9779 10:02:04.386056 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9780 10:02:04.389676 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9781 10:02:04.392669 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9782 10:02:04.399848 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9783 10:02:04.403080 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9784 10:02:04.406315 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9785 10:02:04.409673 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9786 10:02:04.416490 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9787 10:02:04.419534 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9788 10:02:04.422849 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9789 10:02:04.429671 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9790 10:02:04.433229 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9791 10:02:04.439942 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9792 10:02:04.442978 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9793 10:02:04.446602 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9794 10:02:04.453235 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9795 10:02:04.456192 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9796 10:02:04.459768 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9797 10:02:04.466420 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9798 10:02:04.470261 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9799 10:02:04.476388 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9800 10:02:04.480091 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9801 10:02:04.486687 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9802 10:02:04.489837 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9803 10:02:04.493396 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9804 10:02:04.500023 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9805 10:02:04.503687 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9806 10:02:04.506610 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9807 10:02:04.513259 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9808 10:02:04.516649 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9809 10:02:04.523691 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9810 10:02:04.526615 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9811 10:02:04.533311 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9812 10:02:04.536954 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9813 10:02:04.539865 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9814 10:02:04.546739 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9815 10:02:04.549820 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9816 10:02:04.556474 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9817 10:02:04.560188 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9818 10:02:04.563230 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9819 10:02:04.569791 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9820 10:02:04.573370 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9821 10:02:04.576872 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9822 10:02:04.583368 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9823 10:02:04.586721 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9824 10:02:04.593222 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9825 10:02:04.596597 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9826 10:02:04.603607 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9827 10:02:04.606683 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9828 10:02:04.610299 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9829 10:02:04.616783 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9830 10:02:04.620162 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9831 10:02:04.626846 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9832 10:02:04.630209 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9833 10:02:04.633516 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9834 10:02:04.640140 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9835 10:02:04.643825 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9836 10:02:04.646922 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9837 10:02:04.653606 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9838 10:02:04.656617 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9839 10:02:04.663341 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9840 10:02:04.667021 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9841 10:02:04.673667 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9842 10:02:04.676713 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9843 10:02:04.679802 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9844 10:02:04.686786 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9845 10:02:04.690171 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9846 10:02:04.696767 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9847 10:02:04.700270 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9848 10:02:04.703445 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9849 10:02:04.710296 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9850 10:02:04.713301 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9851 10:02:04.719846 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9852 10:02:04.723492 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9853 10:02:04.726921 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9854 10:02:04.733282 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9855 10:02:04.736823 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9856 10:02:04.743272 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9857 10:02:04.747047 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9858 10:02:04.749940 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9859 10:02:04.756796 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9860 10:02:04.760274 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9861 10:02:04.766827 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9862 10:02:04.770496 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9863 10:02:04.773532 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9864 10:02:04.780093 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9865 10:02:04.783889 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9866 10:02:04.790461 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9867 10:02:04.793453 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9868 10:02:04.797047 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9869 10:02:04.803749 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9870 10:02:04.806644 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9871 10:02:04.813642 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9872 10:02:04.816653 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9873 10:02:04.823585 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9874 10:02:04.826670 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9875 10:02:04.833812 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9876 10:02:04.837085 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9877 10:02:04.840829 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9878 10:02:04.847303 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9879 10:02:04.850295 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9880 10:02:04.856737 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9881 10:02:04.860248 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9882 10:02:04.866980 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9883 10:02:04.870541 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9884 10:02:04.873580 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9885 10:02:04.880242 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9886 10:02:04.883870 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9887 10:02:04.890738 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9888 10:02:04.894077 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9889 10:02:04.900142 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9890 10:02:04.903848 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9891 10:02:04.907494 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9892 10:02:04.914025 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9893 10:02:04.917493 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9894 10:02:04.924036 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9895 10:02:04.927105 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9896 10:02:04.930595 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9897 10:02:04.937607 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9898 10:02:04.940672 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9899 10:02:04.947528 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9900 10:02:04.950942 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9901 10:02:04.954279 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9902 10:02:04.960645 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9903 10:02:04.964016 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9904 10:02:04.970532 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9905 10:02:04.973975 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9906 10:02:04.980398 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9907 10:02:04.984066 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9908 10:02:04.987111 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9909 10:02:04.993987 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9910 10:02:04.997223 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9911 10:02:05.003927 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9912 10:02:05.006930 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9913 10:02:05.014046 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9914 10:02:05.017026 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9915 10:02:05.023996 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9916 10:02:05.027042 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9917 10:02:05.033708 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9918 10:02:05.037295 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9919 10:02:05.044078 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9920 10:02:05.047382 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9921 10:02:05.053983 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9922 10:02:05.057195 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9923 10:02:05.060508 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9924 10:02:05.067060 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9925 10:02:05.070628 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9926 10:02:05.077066 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9927 10:02:05.080232 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9928 10:02:05.087246 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9929 10:02:05.090309 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9930 10:02:05.096892 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9931 10:02:05.100595 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9932 10:02:05.107182 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9933 10:02:05.110334 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9934 10:02:05.116948 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9935 10:02:05.120380 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9936 10:02:05.127194 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9937 10:02:05.130698 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9938 10:02:05.137369 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9939 10:02:05.140410 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9940 10:02:05.146950 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9941 10:02:05.150497 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9942 10:02:05.153953 INFO: [APUAPC] vio 0
9943 10:02:05.157107 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9944 10:02:05.163716 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9945 10:02:05.167611 INFO: [APUAPC] D0_APC_0: 0x400510
9946 10:02:05.167690 INFO: [APUAPC] D0_APC_1: 0x0
9947 10:02:05.170414 INFO: [APUAPC] D0_APC_2: 0x1540
9948 10:02:05.173740 INFO: [APUAPC] D0_APC_3: 0x0
9949 10:02:05.176981 INFO: [APUAPC] D1_APC_0: 0xffffffff
9950 10:02:05.180883 INFO: [APUAPC] D1_APC_1: 0xffffffff
9951 10:02:05.183853 INFO: [APUAPC] D1_APC_2: 0x3fffff
9952 10:02:05.187669 INFO: [APUAPC] D1_APC_3: 0x0
9953 10:02:05.190886 INFO: [APUAPC] D2_APC_0: 0xffffffff
9954 10:02:05.194111 INFO: [APUAPC] D2_APC_1: 0xffffffff
9955 10:02:05.197765 INFO: [APUAPC] D2_APC_2: 0x3fffff
9956 10:02:05.200950 INFO: [APUAPC] D2_APC_3: 0x0
9957 10:02:05.204065 INFO: [APUAPC] D3_APC_0: 0xffffffff
9958 10:02:05.207674 INFO: [APUAPC] D3_APC_1: 0xffffffff
9959 10:02:05.210722 INFO: [APUAPC] D3_APC_2: 0x3fffff
9960 10:02:05.214302 INFO: [APUAPC] D3_APC_3: 0x0
9961 10:02:05.217294 INFO: [APUAPC] D4_APC_0: 0xffffffff
9962 10:02:05.221080 INFO: [APUAPC] D4_APC_1: 0xffffffff
9963 10:02:05.224013 INFO: [APUAPC] D4_APC_2: 0x3fffff
9964 10:02:05.227561 INFO: [APUAPC] D4_APC_3: 0x0
9965 10:02:05.231050 INFO: [APUAPC] D5_APC_0: 0xffffffff
9966 10:02:05.234051 INFO: [APUAPC] D5_APC_1: 0xffffffff
9967 10:02:05.237695 INFO: [APUAPC] D5_APC_2: 0x3fffff
9968 10:02:05.240845 INFO: [APUAPC] D5_APC_3: 0x0
9969 10:02:05.244210 INFO: [APUAPC] D6_APC_0: 0xffffffff
9970 10:02:05.247764 INFO: [APUAPC] D6_APC_1: 0xffffffff
9971 10:02:05.250736 INFO: [APUAPC] D6_APC_2: 0x3fffff
9972 10:02:05.250835 INFO: [APUAPC] D6_APC_3: 0x0
9973 10:02:05.257840 INFO: [APUAPC] D7_APC_0: 0xffffffff
9974 10:02:05.260910 INFO: [APUAPC] D7_APC_1: 0xffffffff
9975 10:02:05.264786 INFO: [APUAPC] D7_APC_2: 0x3fffff
9976 10:02:05.264867 INFO: [APUAPC] D7_APC_3: 0x0
9977 10:02:05.267626 INFO: [APUAPC] D8_APC_0: 0xffffffff
9978 10:02:05.270791 INFO: [APUAPC] D8_APC_1: 0xffffffff
9979 10:02:05.274257 INFO: [APUAPC] D8_APC_2: 0x3fffff
9980 10:02:05.277236 INFO: [APUAPC] D8_APC_3: 0x0
9981 10:02:05.280565 INFO: [APUAPC] D9_APC_0: 0xffffffff
9982 10:02:05.284245 INFO: [APUAPC] D9_APC_1: 0xffffffff
9983 10:02:05.287166 INFO: [APUAPC] D9_APC_2: 0x3fffff
9984 10:02:05.290756 INFO: [APUAPC] D9_APC_3: 0x0
9985 10:02:05.294343 INFO: [APUAPC] D10_APC_0: 0xffffffff
9986 10:02:05.297338 INFO: [APUAPC] D10_APC_1: 0xffffffff
9987 10:02:05.300801 INFO: [APUAPC] D10_APC_2: 0x3fffff
9988 10:02:05.303948 INFO: [APUAPC] D10_APC_3: 0x0
9989 10:02:05.307627 INFO: [APUAPC] D11_APC_0: 0xffffffff
9990 10:02:05.310935 INFO: [APUAPC] D11_APC_1: 0xffffffff
9991 10:02:05.314220 INFO: [APUAPC] D11_APC_2: 0x3fffff
9992 10:02:05.317141 INFO: [APUAPC] D11_APC_3: 0x0
9993 10:02:05.320840 INFO: [APUAPC] D12_APC_0: 0xffffffff
9994 10:02:05.324572 INFO: [APUAPC] D12_APC_1: 0xffffffff
9995 10:02:05.327649 INFO: [APUAPC] D12_APC_2: 0x3fffff
9996 10:02:05.331009 INFO: [APUAPC] D12_APC_3: 0x0
9997 10:02:05.334594 INFO: [APUAPC] D13_APC_0: 0xffffffff
9998 10:02:05.337434 INFO: [APUAPC] D13_APC_1: 0xffffffff
9999 10:02:05.341176 INFO: [APUAPC] D13_APC_2: 0x3fffff
10000 10:02:05.344150 INFO: [APUAPC] D13_APC_3: 0x0
10001 10:02:05.347705 INFO: [APUAPC] D14_APC_0: 0xffffffff
10002 10:02:05.351239 INFO: [APUAPC] D14_APC_1: 0xffffffff
10003 10:02:05.354176 INFO: [APUAPC] D14_APC_2: 0x3fffff
10004 10:02:05.357915 INFO: [APUAPC] D14_APC_3: 0x0
10005 10:02:05.361306 INFO: [APUAPC] D15_APC_0: 0xffffffff
10006 10:02:05.364463 INFO: [APUAPC] D15_APC_1: 0xffffffff
10007 10:02:05.367425 INFO: [APUAPC] D15_APC_2: 0x3fffff
10008 10:02:05.371064 INFO: [APUAPC] D15_APC_3: 0x0
10009 10:02:05.374277 INFO: [APUAPC] APC_CON: 0x4
10010 10:02:05.377428 INFO: [NOCDAPC] D0_APC_0: 0x0
10011 10:02:05.381052 INFO: [NOCDAPC] D0_APC_1: 0x0
10012 10:02:05.384659 INFO: [NOCDAPC] D1_APC_0: 0x0
10013 10:02:05.387527 INFO: [NOCDAPC] D1_APC_1: 0xfff
10014 10:02:05.387604 INFO: [NOCDAPC] D2_APC_0: 0x0
10015 10:02:05.390879 INFO: [NOCDAPC] D2_APC_1: 0xfff
10016 10:02:05.394749 INFO: [NOCDAPC] D3_APC_0: 0x0
10017 10:02:05.397650 INFO: [NOCDAPC] D3_APC_1: 0xfff
10018 10:02:05.401505 INFO: [NOCDAPC] D4_APC_0: 0x0
10019 10:02:05.404274 INFO: [NOCDAPC] D4_APC_1: 0xfff
10020 10:02:05.408056 INFO: [NOCDAPC] D5_APC_0: 0x0
10021 10:02:05.411055 INFO: [NOCDAPC] D5_APC_1: 0xfff
10022 10:02:05.414337 INFO: [NOCDAPC] D6_APC_0: 0x0
10023 10:02:05.418132 INFO: [NOCDAPC] D6_APC_1: 0xfff
10024 10:02:05.418207 INFO: [NOCDAPC] D7_APC_0: 0x0
10025 10:02:05.421471 INFO: [NOCDAPC] D7_APC_1: 0xfff
10026 10:02:05.424339 INFO: [NOCDAPC] D8_APC_0: 0x0
10027 10:02:05.427924 INFO: [NOCDAPC] D8_APC_1: 0xfff
10028 10:02:05.431087 INFO: [NOCDAPC] D9_APC_0: 0x0
10029 10:02:05.434565 INFO: [NOCDAPC] D9_APC_1: 0xfff
10030 10:02:05.438125 INFO: [NOCDAPC] D10_APC_0: 0x0
10031 10:02:05.440924 INFO: [NOCDAPC] D10_APC_1: 0xfff
10032 10:02:05.444609 INFO: [NOCDAPC] D11_APC_0: 0x0
10033 10:02:05.448180 INFO: [NOCDAPC] D11_APC_1: 0xfff
10034 10:02:05.451100 INFO: [NOCDAPC] D12_APC_0: 0x0
10035 10:02:05.454763 INFO: [NOCDAPC] D12_APC_1: 0xfff
10036 10:02:05.454874 INFO: [NOCDAPC] D13_APC_0: 0x0
10037 10:02:05.457804 INFO: [NOCDAPC] D13_APC_1: 0xfff
10038 10:02:05.461349 INFO: [NOCDAPC] D14_APC_0: 0x0
10039 10:02:05.464808 INFO: [NOCDAPC] D14_APC_1: 0xfff
10040 10:02:05.468362 INFO: [NOCDAPC] D15_APC_0: 0x0
10041 10:02:05.471458 INFO: [NOCDAPC] D15_APC_1: 0xfff
10042 10:02:05.474471 INFO: [NOCDAPC] APC_CON: 0x4
10043 10:02:05.477711 INFO: [APUAPC] set_apusys_apc done
10044 10:02:05.481405 INFO: [DEVAPC] devapc_init done
10045 10:02:05.484600 INFO: GICv3 without legacy support detected.
10046 10:02:05.488156 INFO: ARM GICv3 driver initialized in EL3
10047 10:02:05.494919 INFO: Maximum SPI INTID supported: 639
10048 10:02:05.498174 INFO: BL31: Initializing runtime services
10049 10:02:05.501433 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10050 10:02:05.504632 INFO: SPM: enable CPC mode
10051 10:02:05.511365 INFO: mcdi ready for mcusys-off-idle and system suspend
10052 10:02:05.515091 INFO: BL31: Preparing for EL3 exit to normal world
10053 10:02:05.518167 INFO: Entry point address = 0x80000000
10054 10:02:05.521177 INFO: SPSR = 0x8
10055 10:02:05.526832
10056 10:02:05.526944
10057 10:02:05.527010
10058 10:02:05.529906 Starting depthcharge on Spherion...
10059 10:02:05.529982
10060 10:02:05.530043 Wipe memory regions:
10061 10:02:05.530102
10062 10:02:05.530843 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10063 10:02:05.530979 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10064 10:02:05.531059 Setting prompt string to ['asurada:']
10065 10:02:05.531137 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10066 10:02:05.533303 [0x00000040000000, 0x00000054600000)
10067 10:02:05.655745
10068 10:02:05.655885 [0x00000054660000, 0x00000080000000)
10069 10:02:05.916558
10070 10:02:05.916691 [0x000000821a7280, 0x000000ffe64000)
10071 10:02:06.661365
10072 10:02:06.661504 [0x00000100000000, 0x00000240000000)
10073 10:02:08.551276
10074 10:02:08.554369 Initializing XHCI USB controller at 0x11200000.
10075 10:02:09.592202
10076 10:02:09.595332 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10077 10:02:09.595438
10078 10:02:09.595517
10079 10:02:09.595582
10080 10:02:09.595866 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10082 10:02:09.696243 asurada: tftpboot 192.168.201.1 12073323/tftp-deploy-3pqnrf9v/kernel/image.itb 12073323/tftp-deploy-3pqnrf9v/kernel/cmdline
10083 10:02:09.696417 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10084 10:02:09.696511 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10085 10:02:09.700716 tftpboot 192.168.201.1 12073323/tftp-deploy-3pqnrf9v/kernel/image.ittp-deploy-3pqnrf9v/kernel/cmdline
10086 10:02:09.700830
10087 10:02:09.700924 Waiting for link
10088 10:02:09.861107
10089 10:02:09.861266 R8152: Initializing
10090 10:02:09.861364
10091 10:02:09.864687 Version 6 (ocp_data = 5c30)
10092 10:02:09.864764
10093 10:02:09.867655 R8152: Done initializing
10094 10:02:09.867729
10095 10:02:09.867791 Adding net device
10096 10:02:11.802253
10097 10:02:11.802392 done.
10098 10:02:11.802473
10099 10:02:11.802535 MAC: 00:24:32:30:78:52
10100 10:02:11.802594
10101 10:02:11.805507 Sending DHCP discover... done.
10102 10:02:11.805609
10103 10:02:11.808850 Waiting for reply... done.
10104 10:02:11.808927
10105 10:02:11.812110 Sending DHCP request... done.
10106 10:02:11.812183
10107 10:02:11.815633 Waiting for reply... done.
10108 10:02:11.815705
10109 10:02:11.815764 My ip is 192.168.201.14
10110 10:02:11.815836
10111 10:02:11.819150 The DHCP server ip is 192.168.201.1
10112 10:02:11.819270
10113 10:02:11.825797 TFTP server IP predefined by user: 192.168.201.1
10114 10:02:11.825905
10115 10:02:11.828807 Bootfile predefined by user: 12073323/tftp-deploy-3pqnrf9v/kernel/image.itb
10116 10:02:11.832504
10117 10:02:11.832586 Sending tftp read request... done.
10118 10:02:11.832648
10119 10:02:11.839029 Waiting for the transfer...
10120 10:02:11.839133
10121 10:02:12.377001 00000000 ################################################################
10122 10:02:12.377180
10123 10:02:12.911923 00080000 ################################################################
10124 10:02:12.912059
10125 10:02:13.455102 00100000 ################################################################
10126 10:02:13.455263
10127 10:02:13.982829 00180000 ################################################################
10128 10:02:13.982999
10129 10:02:14.501582 00200000 ################################################################
10130 10:02:14.501733
10131 10:02:15.020451 00280000 ################################################################
10132 10:02:15.020609
10133 10:02:15.546924 00300000 ################################################################
10134 10:02:15.547082
10135 10:02:16.069085 00380000 ################################################################
10136 10:02:16.069224
10137 10:02:16.595377 00400000 ################################################################
10138 10:02:16.595550
10139 10:02:17.111100 00480000 ################################################################
10140 10:02:17.111253
10141 10:02:17.627168 00500000 ################################################################
10142 10:02:17.627348
10143 10:02:18.151537 00580000 ################################################################
10144 10:02:18.151713
10145 10:02:18.677116 00600000 ################################################################
10146 10:02:18.677273
10147 10:02:19.193674 00680000 ################################################################
10148 10:02:19.193838
10149 10:02:19.714626 00700000 ################################################################
10150 10:02:19.714763
10151 10:02:20.254049 00780000 ################################################################
10152 10:02:20.254198
10153 10:02:20.775477 00800000 ################################################################
10154 10:02:20.775637
10155 10:02:21.297513 00880000 ################################################################
10156 10:02:21.297665
10157 10:02:21.821404 00900000 ################################################################
10158 10:02:21.821542
10159 10:02:22.353894 00980000 ################################################################
10160 10:02:22.354055
10161 10:02:22.887485 00a00000 ################################################################
10162 10:02:22.887655
10163 10:02:23.419482 00a80000 ################################################################
10164 10:02:23.419627
10165 10:02:23.946677 00b00000 ################################################################
10166 10:02:23.946841
10167 10:02:24.488252 00b80000 ################################################################
10168 10:02:24.488411
10169 10:02:25.032759 00c00000 ################################################################
10170 10:02:25.032940
10171 10:02:25.591065 00c80000 ################################################################
10172 10:02:25.591198
10173 10:02:26.132868 00d00000 ################################################################
10174 10:02:26.133032
10175 10:02:26.664428 00d80000 ################################################################
10176 10:02:26.664592
10177 10:02:27.199908 00e00000 ################################################################
10178 10:02:27.200042
10179 10:02:27.737424 00e80000 ################################################################
10180 10:02:27.737562
10181 10:02:28.273855 00f00000 ################################################################
10182 10:02:28.273995
10183 10:02:28.797809 00f80000 ################################################################
10184 10:02:28.798028
10185 10:02:29.322590 01000000 ################################################################
10186 10:02:29.322769
10187 10:02:29.847222 01080000 ################################################################
10188 10:02:29.847381
10189 10:02:30.374224 01100000 ################################################################
10190 10:02:30.374386
10191 10:02:30.905222 01180000 ################################################################
10192 10:02:30.905372
10193 10:02:31.431957 01200000 ################################################################
10194 10:02:31.432110
10195 10:02:31.961672 01280000 ################################################################
10196 10:02:31.961833
10197 10:02:32.487253 01300000 ################################################################
10198 10:02:32.487421
10199 10:02:33.016859 01380000 ################################################################
10200 10:02:33.017011
10201 10:02:33.544107 01400000 ################################################################
10202 10:02:33.544267
10203 10:02:34.070060 01480000 ################################################################
10204 10:02:34.070232
10205 10:02:34.593092 01500000 ################################################################
10206 10:02:34.593263
10207 10:02:35.118322 01580000 ################################################################
10208 10:02:35.118464
10209 10:02:35.645012 01600000 ################################################################
10210 10:02:35.645154
10211 10:02:36.170602 01680000 ################################################################
10212 10:02:36.170767
10213 10:02:36.693803 01700000 ################################################################
10214 10:02:36.693965
10215 10:02:37.217981 01780000 ################################################################
10216 10:02:37.218164
10217 10:02:37.743693 01800000 ################################################################
10218 10:02:37.743872
10219 10:02:38.267588 01880000 ################################################################
10220 10:02:38.267778
10221 10:02:38.793378 01900000 ################################################################
10222 10:02:38.793545
10223 10:02:39.321359 01980000 ################################################################
10224 10:02:39.321526
10225 10:02:39.847396 01a00000 ################################################################
10226 10:02:39.847542
10227 10:02:40.375962 01a80000 ################################################################
10228 10:02:40.376109
10229 10:02:40.901661 01b00000 ################################################################
10230 10:02:40.901838
10231 10:02:41.426310 01b80000 ################################################################
10232 10:02:41.426487
10233 10:02:41.950306 01c00000 ################################################################
10234 10:02:41.950488
10235 10:02:42.474623 01c80000 ################################################################
10236 10:02:42.474809
10237 10:02:42.998133 01d00000 ################################################################
10238 10:02:42.998300
10239 10:02:43.523726 01d80000 ################################################################
10240 10:02:43.523916
10241 10:02:44.050812 01e00000 ################################################################
10242 10:02:44.050984
10243 10:02:44.580274 01e80000 ################################################################
10244 10:02:44.580461
10245 10:02:45.104700 01f00000 ################################################################
10246 10:02:45.104879
10247 10:02:45.628783 01f80000 ################################################################
10248 10:02:45.628936
10249 10:02:46.160006 02000000 ################################################################
10250 10:02:46.160173
10251 10:02:46.687865 02080000 ################################################################
10252 10:02:46.688052
10253 10:02:47.212551 02100000 ################################################################
10254 10:02:47.212730
10255 10:02:47.736483 02180000 ################################################################
10256 10:02:47.736662
10257 10:02:48.284982 02200000 ################################################################
10258 10:02:48.285165
10259 10:02:48.838032 02280000 ################################################################
10260 10:02:48.838208
10261 10:02:49.382612 02300000 ################################################################
10262 10:02:49.382790
10263 10:02:49.923606 02380000 ################################################################
10264 10:02:49.923782
10265 10:02:50.470264 02400000 ################################################################
10266 10:02:50.470399
10267 10:02:51.015970 02480000 ################################################################
10268 10:02:51.016123
10269 10:02:51.539432 02500000 ################################################################
10270 10:02:51.539578
10271 10:02:52.078798 02580000 ################################################################
10272 10:02:52.078984
10273 10:02:52.605467 02600000 ################################################################
10274 10:02:52.605640
10275 10:02:53.149331 02680000 ################################################################
10276 10:02:53.149504
10277 10:02:53.695593 02700000 ################################################################
10278 10:02:53.695754
10279 10:02:54.239110 02780000 ################################################################
10280 10:02:54.239258
10281 10:02:54.764992 02800000 ################################################################
10282 10:02:54.765145
10283 10:02:55.294666 02880000 ################################################################
10284 10:02:55.294855
10285 10:02:55.818380 02900000 ################################################################
10286 10:02:55.818527
10287 10:02:56.344949 02980000 ################################################################
10288 10:02:56.345121
10289 10:02:56.872894 02a00000 ################################################################
10290 10:02:56.873064
10291 10:02:57.405069 02a80000 ################################################################
10292 10:02:57.405223
10293 10:02:57.932399 02b00000 ################################################################
10294 10:02:57.932554
10295 10:02:58.456551 02b80000 ################################################################
10296 10:02:58.456726
10297 10:02:58.987283 02c00000 ################################################################
10298 10:02:58.987466
10299 10:02:59.513526 02c80000 ################################################################
10300 10:02:59.513702
10301 10:03:00.038227 02d00000 ################################################################
10302 10:03:00.038417
10303 10:03:00.562182 02d80000 ################################################################
10304 10:03:00.562340
10305 10:03:01.088415 02e00000 ################################################################
10306 10:03:01.088571
10307 10:03:01.611393 02e80000 ################################################################
10308 10:03:01.611535
10309 10:03:02.145305 02f00000 ################################################################
10310 10:03:02.145459
10311 10:03:02.686054 02f80000 ################################################################
10312 10:03:02.686205
10313 10:03:03.212133 03000000 ################################################################
10314 10:03:03.212323
10315 10:03:03.735978 03080000 ################################################################
10316 10:03:03.736128
10317 10:03:04.288079 03100000 ################################################################
10318 10:03:04.288231
10319 10:03:04.843404 03180000 ################################################################
10320 10:03:04.843558
10321 10:03:05.396436 03200000 ################################################################
10322 10:03:05.396584
10323 10:03:05.949225 03280000 ################################################################
10324 10:03:05.949355
10325 10:03:06.499590 03300000 ################################################################
10326 10:03:06.499728
10327 10:03:07.051101 03380000 ################################################################
10328 10:03:07.051240
10329 10:03:07.600396 03400000 ################################################################
10330 10:03:07.600568
10331 10:03:08.155750 03480000 ################################################################
10332 10:03:08.155901
10333 10:03:08.707421 03500000 ################################################################
10334 10:03:08.707596
10335 10:03:09.257905 03580000 ################################################################
10336 10:03:09.258055
10337 10:03:09.807431 03600000 ################################################################
10338 10:03:09.807586
10339 10:03:10.366016 03680000 ################################################################
10340 10:03:10.366153
10341 10:03:10.916888 03700000 ################################################################
10342 10:03:10.917025
10343 10:03:11.468483 03780000 ################################################################
10344 10:03:11.468630
10345 10:03:12.027730 03800000 ################################################################
10346 10:03:12.027903
10347 10:03:12.584258 03880000 ################################################################
10348 10:03:12.584410
10349 10:03:13.135536 03900000 ################################################################
10350 10:03:13.135681
10351 10:03:13.686336 03980000 ################################################################
10352 10:03:13.686488
10353 10:03:14.251617 03a00000 ################################################################
10354 10:03:14.251781
10355 10:03:14.806468 03a80000 ################################################################
10356 10:03:14.806648
10357 10:03:15.378124 03b00000 ################################################################
10358 10:03:15.378268
10359 10:03:15.962326 03b80000 ################################################################
10360 10:03:15.962506
10361 10:03:16.562952 03c00000 ################################################################
10362 10:03:16.563535
10363 10:03:17.255515 03c80000 ################################################################
10364 10:03:17.256111
10365 10:03:17.879939 03d00000 ################################################################
10366 10:03:17.880117
10367 10:03:18.535461 03d80000 ################################################################
10368 10:03:18.536213
10369 10:03:19.144739 03e00000 ################################################################
10370 10:03:19.145484
10371 10:03:19.758810 03e80000 ################################################################
10372 10:03:19.759367
10373 10:03:20.437483 03f00000 ################################################################
10374 10:03:20.438142
10375 10:03:21.131891 03f80000 ################################################################
10376 10:03:21.132450
10377 10:03:21.710804 04000000 ##################################################### done.
10378 10:03:21.711361
10379 10:03:21.713995 The bootfile was 67537790 bytes long.
10380 10:03:21.714414
10381 10:03:21.716950 Sending tftp read request... done.
10382 10:03:21.717372
10383 10:03:21.720790 Waiting for the transfer...
10384 10:03:21.721221
10385 10:03:21.721551 00000000 # done.
10386 10:03:21.721872
10387 10:03:21.727344 Command line loaded dynamically from TFTP file: 12073323/tftp-deploy-3pqnrf9v/kernel/cmdline
10388 10:03:21.727769
10389 10:03:21.741129 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10390 10:03:21.741556
10391 10:03:21.743928 Loading FIT.
10392 10:03:21.744367
10393 10:03:21.747503 Image ramdisk-1 has 56440934 bytes.
10394 10:03:21.747921
10395 10:03:21.750922 Image fdt-1 has 47278 bytes.
10396 10:03:21.751405
10397 10:03:21.751736 Image kernel-1 has 11047542 bytes.
10398 10:03:21.752050
10399 10:03:21.760671 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10400 10:03:21.761094
10401 10:03:21.777124 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10402 10:03:21.780880
10403 10:03:21.784318 Choosing best match conf-1 for compat google,spherion-rev2.
10404 10:03:21.788685
10405 10:03:21.793098 Connected to device vid:did:rid of 1ae0:0028:00
10406 10:03:21.801392
10407 10:03:21.804365 tpm_get_response: command 0x17b, return code 0x0
10408 10:03:21.804777
10409 10:03:21.807777 ec_init: CrosEC protocol v3 supported (256, 248)
10410 10:03:21.811506
10411 10:03:21.815538 tpm_cleanup: add release locality here.
10412 10:03:21.815955
10413 10:03:21.816338 Shutting down all USB controllers.
10414 10:03:21.818655
10415 10:03:21.819123 Removing current net device
10416 10:03:21.819462
10417 10:03:21.825127 Exiting depthcharge with code 4 at timestamp: 105731113
10418 10:03:21.825697
10419 10:03:21.828551 LZMA decompressing kernel-1 to 0x821a6718
10420 10:03:21.828961
10421 10:03:21.832055 LZMA decompressing kernel-1 to 0x40000000
10422 10:03:23.221641
10423 10:03:23.222203 jumping to kernel
10424 10:03:23.224373 end: 2.2.4 bootloader-commands (duration 00:01:18) [common]
10425 10:03:23.224901 start: 2.2.5 auto-login-action (timeout 00:03:07) [common]
10426 10:03:23.225315 Setting prompt string to ['Linux version [0-9]']
10427 10:03:23.225798 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10428 10:03:23.226185 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10429 10:03:23.304062
10430 10:03:23.307302 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10431 10:03:23.310451 start: 2.2.5.1 login-action (timeout 00:03:07) [common]
10432 10:03:23.310940 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10433 10:03:23.311309 Setting prompt string to []
10434 10:03:23.311698 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10435 10:03:23.312071 Using line separator: #'\n'#
10436 10:03:23.312377 No login prompt set.
10437 10:03:23.312697 Parsing kernel messages
10438 10:03:23.312983 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10439 10:03:23.313693 [login-action] Waiting for messages, (timeout 00:03:07)
10440 10:03:23.330060 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j22848-arm64-gcc-10-defconfig-arm64-chromebook-6q8mw) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Nov 24 09:44:51 UTC 2023
10441 10:03:23.333024 [ 0.000000] random: crng init done
10442 10:03:23.339577 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10443 10:03:23.343008 [ 0.000000] efi: UEFI not found.
10444 10:03:23.350053 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10445 10:03:23.356656 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10446 10:03:23.366701 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10447 10:03:23.376660 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10448 10:03:23.383650 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10449 10:03:23.386971 [ 0.000000] printk: bootconsole [mtk8250] enabled
10450 10:03:23.395355 [ 0.000000] NUMA: No NUMA configuration found
10451 10:03:23.401964 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10452 10:03:23.408828 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10453 10:03:23.409373 [ 0.000000] Zone ranges:
10454 10:03:23.415421 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10455 10:03:23.418672 [ 0.000000] DMA32 empty
10456 10:03:23.425824 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10457 10:03:23.429056 [ 0.000000] Movable zone start for each node
10458 10:03:23.432707 [ 0.000000] Early memory node ranges
10459 10:03:23.439021 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10460 10:03:23.445407 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10461 10:03:23.452441 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10462 10:03:23.458764 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10463 10:03:23.465868 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10464 10:03:23.472245 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10465 10:03:23.528600 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10466 10:03:23.535192 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10467 10:03:23.541368 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10468 10:03:23.544629 [ 0.000000] psci: probing for conduit method from DT.
10469 10:03:23.551862 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10470 10:03:23.555081 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10471 10:03:23.561697 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10472 10:03:23.564543 [ 0.000000] psci: SMC Calling Convention v1.2
10473 10:03:23.571446 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10474 10:03:23.575013 [ 0.000000] Detected VIPT I-cache on CPU0
10475 10:03:23.582021 [ 0.000000] CPU features: detected: GIC system register CPU interface
10476 10:03:23.587742 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10477 10:03:23.594726 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10478 10:03:23.601592 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10479 10:03:23.608553 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10480 10:03:23.614420 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10481 10:03:23.621402 [ 0.000000] alternatives: applying boot alternatives
10482 10:03:23.624426 [ 0.000000] Fallback order for Node 0: 0
10483 10:03:23.631129 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10484 10:03:23.634638 [ 0.000000] Policy zone: Normal
10485 10:03:23.651146 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10486 10:03:23.660852 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10487 10:03:23.672677 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10488 10:03:23.682332 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10489 10:03:23.689457 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10490 10:03:23.693253 <6>[ 0.000000] software IO TLB: area num 8.
10491 10:03:23.750292 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10492 10:03:23.899543 <6>[ 0.000000] Memory: 7914496K/8385536K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 438272K reserved, 32768K cma-reserved)
10493 10:03:23.906431 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10494 10:03:23.912835 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10495 10:03:23.916445 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10496 10:03:23.923014 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10497 10:03:23.929535 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10498 10:03:23.932931 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10499 10:03:23.943328 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10500 10:03:23.949923 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10501 10:03:23.953355 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10502 10:03:23.960499 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10503 10:03:23.963935 <6>[ 0.000000] GICv3: 608 SPIs implemented
10504 10:03:23.970601 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10505 10:03:23.973759 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10506 10:03:23.977238 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10507 10:03:23.987267 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10508 10:03:23.997230 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10509 10:03:24.010813 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10510 10:03:24.016875 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10511 10:03:24.026180 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10512 10:03:24.039648 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10513 10:03:24.046306 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10514 10:03:24.053146 <6>[ 0.009180] Console: colour dummy device 80x25
10515 10:03:24.062806 <6>[ 0.013906] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10516 10:03:24.066087 <6>[ 0.024413] pid_max: default: 32768 minimum: 301
10517 10:03:24.072397 <6>[ 0.029285] LSM: Security Framework initializing
10518 10:03:24.079522 <6>[ 0.034222] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10519 10:03:24.089513 <6>[ 0.042067] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10520 10:03:24.096261 <6>[ 0.051475] cblist_init_generic: Setting adjustable number of callback queues.
10521 10:03:24.103088 <6>[ 0.058919] cblist_init_generic: Setting shift to 3 and lim to 1.
10522 10:03:24.109846 <6>[ 0.065258] cblist_init_generic: Setting adjustable number of callback queues.
10523 10:03:24.116810 <6>[ 0.072685] cblist_init_generic: Setting shift to 3 and lim to 1.
10524 10:03:24.122708 <6>[ 0.079124] rcu: Hierarchical SRCU implementation.
10525 10:03:24.129764 <6>[ 0.084140] rcu: Max phase no-delay instances is 1000.
10526 10:03:24.132419 <6>[ 0.091151] EFI services will not be available.
10527 10:03:24.139534 <6>[ 0.096108] smp: Bringing up secondary CPUs ...
10528 10:03:24.147016 <6>[ 0.101152] Detected VIPT I-cache on CPU1
10529 10:03:24.153851 <6>[ 0.101222] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10530 10:03:24.159988 <6>[ 0.101251] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10531 10:03:24.163574 <6>[ 0.101589] Detected VIPT I-cache on CPU2
10532 10:03:24.170591 <6>[ 0.101642] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10533 10:03:24.177342 <6>[ 0.101659] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10534 10:03:24.183465 <6>[ 0.101922] Detected VIPT I-cache on CPU3
10535 10:03:24.190616 <6>[ 0.101968] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10536 10:03:24.197210 <6>[ 0.101982] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10537 10:03:24.199745 <6>[ 0.102282] CPU features: detected: Spectre-v4
10538 10:03:24.207269 <6>[ 0.102288] CPU features: detected: Spectre-BHB
10539 10:03:24.210340 <6>[ 0.102293] Detected PIPT I-cache on CPU4
10540 10:03:24.216919 <6>[ 0.102351] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10541 10:03:24.223754 <6>[ 0.102368] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10542 10:03:24.227079 <6>[ 0.102657] Detected PIPT I-cache on CPU5
10543 10:03:24.236871 <6>[ 0.102722] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10544 10:03:24.243422 <6>[ 0.102739] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10545 10:03:24.246838 <6>[ 0.103019] Detected PIPT I-cache on CPU6
10546 10:03:24.253667 <6>[ 0.103085] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10547 10:03:24.259869 <6>[ 0.103101] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10548 10:03:24.263735 <6>[ 0.103396] Detected PIPT I-cache on CPU7
10549 10:03:24.273208 <6>[ 0.103463] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10550 10:03:24.279950 <6>[ 0.103479] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10551 10:03:24.283440 <6>[ 0.103525] smp: Brought up 1 node, 8 CPUs
10552 10:03:24.286544 <6>[ 0.244749] SMP: Total of 8 processors activated.
10553 10:03:24.293387 <6>[ 0.249670] CPU features: detected: 32-bit EL0 Support
10554 10:03:24.303307 <6>[ 0.255032] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10555 10:03:24.310063 <6>[ 0.263887] CPU features: detected: Common not Private translations
10556 10:03:24.313183 <6>[ 0.270363] CPU features: detected: CRC32 instructions
10557 10:03:24.319687 <6>[ 0.275714] CPU features: detected: RCpc load-acquire (LDAPR)
10558 10:03:24.326563 <6>[ 0.281693] CPU features: detected: LSE atomic instructions
10559 10:03:24.330315 <6>[ 0.287475] CPU features: detected: Privileged Access Never
10560 10:03:24.336888 <6>[ 0.293290] CPU features: detected: RAS Extension Support
10561 10:03:24.343069 <6>[ 0.298933] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10562 10:03:24.350684 <6>[ 0.306197] CPU: All CPU(s) started at EL2
10563 10:03:24.353341 <6>[ 0.310513] alternatives: applying system-wide alternatives
10564 10:03:24.364031 <6>[ 0.321223] devtmpfs: initialized
10565 10:03:24.376782 <6>[ 0.330147] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10566 10:03:24.386813 <6>[ 0.340109] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10567 10:03:24.393567 <6>[ 0.348120] pinctrl core: initialized pinctrl subsystem
10568 10:03:24.396545 <6>[ 0.354913] DMI not present or invalid.
10569 10:03:24.403580 <6>[ 0.359325] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10570 10:03:24.413634 <6>[ 0.366182] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10571 10:03:24.420016 <6>[ 0.373766] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10572 10:03:24.429402 <6>[ 0.381979] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10573 10:03:24.433551 <6>[ 0.390221] audit: initializing netlink subsys (disabled)
10574 10:03:24.443424 <5>[ 0.395911] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10575 10:03:24.450412 <6>[ 0.396660] thermal_sys: Registered thermal governor 'step_wise'
10576 10:03:24.456729 <6>[ 0.403878] thermal_sys: Registered thermal governor 'power_allocator'
10577 10:03:24.460181 <6>[ 0.410133] cpuidle: using governor menu
10578 10:03:24.463272 <6>[ 0.421091] NET: Registered PF_QIPCRTR protocol family
10579 10:03:24.472979 <6>[ 0.426576] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10580 10:03:24.476104 <6>[ 0.433680] ASID allocator initialised with 32768 entries
10581 10:03:24.483548 <6>[ 0.440303] Serial: AMBA PL011 UART driver
10582 10:03:24.492960 <4>[ 0.449476] Trying to register duplicate clock ID: 134
10583 10:03:24.549892 <6>[ 0.509604] KASLR enabled
10584 10:03:24.563734 <6>[ 0.517360] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10585 10:03:24.570719 <6>[ 0.524371] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10586 10:03:24.577434 <6>[ 0.530861] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10587 10:03:24.583949 <6>[ 0.537864] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10588 10:03:24.590676 <6>[ 0.544352] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10589 10:03:24.597547 <6>[ 0.551358] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10590 10:03:24.603614 <6>[ 0.557846] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10591 10:03:24.610519 <6>[ 0.564852] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10592 10:03:24.613858 <6>[ 0.572361] ACPI: Interpreter disabled.
10593 10:03:24.622384 <6>[ 0.578841] iommu: Default domain type: Translated
10594 10:03:24.628724 <6>[ 0.583954] iommu: DMA domain TLB invalidation policy: strict mode
10595 10:03:24.632114 <5>[ 0.590611] SCSI subsystem initialized
10596 10:03:24.638609 <6>[ 0.594776] usbcore: registered new interface driver usbfs
10597 10:03:24.645413 <6>[ 0.600509] usbcore: registered new interface driver hub
10598 10:03:24.648299 <6>[ 0.606062] usbcore: registered new device driver usb
10599 10:03:24.655391 <6>[ 0.612200] pps_core: LinuxPPS API ver. 1 registered
10600 10:03:24.665554 <6>[ 0.617394] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10601 10:03:24.668742 <6>[ 0.626741] PTP clock support registered
10602 10:03:24.672235 <6>[ 0.630987] EDAC MC: Ver: 3.0.0
10603 10:03:24.679478 <6>[ 0.636190] FPGA manager framework
10604 10:03:24.682766 <6>[ 0.639868] Advanced Linux Sound Architecture Driver Initialized.
10605 10:03:24.686960 <6>[ 0.646631] vgaarb: loaded
10606 10:03:24.692783 <6>[ 0.649809] clocksource: Switched to clocksource arch_sys_counter
10607 10:03:24.699651 <5>[ 0.656250] VFS: Disk quotas dquot_6.6.0
10608 10:03:24.706636 <6>[ 0.660431] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10609 10:03:24.709415 <6>[ 0.667620] pnp: PnP ACPI: disabled
10610 10:03:24.717164 <6>[ 0.674276] NET: Registered PF_INET protocol family
10611 10:03:24.727352 <6>[ 0.679860] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10612 10:03:24.738797 <6>[ 0.692157] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10613 10:03:24.748396 <6>[ 0.700972] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10614 10:03:24.755325 <6>[ 0.708944] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10615 10:03:24.761766 <6>[ 0.717643] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10616 10:03:24.773916 <6>[ 0.727358] TCP: Hash tables configured (established 65536 bind 65536)
10617 10:03:24.780265 <6>[ 0.734214] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10618 10:03:24.786993 <6>[ 0.741414] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10619 10:03:24.793630 <6>[ 0.749111] NET: Registered PF_UNIX/PF_LOCAL protocol family
10620 10:03:24.800928 <6>[ 0.755288] RPC: Registered named UNIX socket transport module.
10621 10:03:24.803603 <6>[ 0.761440] RPC: Registered udp transport module.
10622 10:03:24.810387 <6>[ 0.766374] RPC: Registered tcp transport module.
10623 10:03:24.817305 <6>[ 0.771305] RPC: Registered tcp NFSv4.1 backchannel transport module.
10624 10:03:24.820415 <6>[ 0.777975] PCI: CLS 0 bytes, default 64
10625 10:03:24.824016 <6>[ 0.782373] Unpacking initramfs...
10626 10:03:24.848260 <6>[ 0.801930] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10627 10:03:24.858921 <6>[ 0.810552] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10628 10:03:24.861673 <6>[ 0.819432] kvm [1]: IPA Size Limit: 40 bits
10629 10:03:24.868350 <6>[ 0.823960] kvm [1]: GICv3: no GICV resource entry
10630 10:03:24.871868 <6>[ 0.828981] kvm [1]: disabling GICv2 emulation
10631 10:03:24.878469 <6>[ 0.833676] kvm [1]: GIC system register CPU interface enabled
10632 10:03:24.881802 <6>[ 0.839845] kvm [1]: vgic interrupt IRQ18
10633 10:03:24.887967 <6>[ 0.844201] kvm [1]: VHE mode initialized successfully
10634 10:03:24.895067 <5>[ 0.850681] Initialise system trusted keyrings
10635 10:03:24.901711 <6>[ 0.855547] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10636 10:03:24.908766 <6>[ 0.865566] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10637 10:03:24.915682 <5>[ 0.871988] NFS: Registering the id_resolver key type
10638 10:03:24.918337 <5>[ 0.877286] Key type id_resolver registered
10639 10:03:24.925400 <5>[ 0.881704] Key type id_legacy registered
10640 10:03:24.931902 <6>[ 0.885981] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10641 10:03:24.938950 <6>[ 0.892901] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10642 10:03:24.945163 <6>[ 0.900610] 9p: Installing v9fs 9p2000 file system support
10643 10:03:24.981533 <5>[ 0.938430] Key type asymmetric registered
10644 10:03:24.985217 <5>[ 0.942771] Asymmetric key parser 'x509' registered
10645 10:03:24.995112 <6>[ 0.947958] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10646 10:03:24.998394 <6>[ 0.955577] io scheduler mq-deadline registered
10647 10:03:25.001764 <6>[ 0.960344] io scheduler kyber registered
10648 10:03:25.020708 <6>[ 0.977884] EINJ: ACPI disabled.
10649 10:03:25.054097 <4>[ 1.003991] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10650 10:03:25.063630 <4>[ 1.014638] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10651 10:03:25.078527 <6>[ 1.035616] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10652 10:03:25.086858 <6>[ 1.043648] printk: console [ttyS0] disabled
10653 10:03:25.115334 <6>[ 1.068295] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10654 10:03:25.121634 <6>[ 1.077775] printk: console [ttyS0] enabled
10655 10:03:25.125041 <6>[ 1.077775] printk: console [ttyS0] enabled
10656 10:03:25.131489 <6>[ 1.086668] printk: bootconsole [mtk8250] disabled
10657 10:03:25.135007 <6>[ 1.086668] printk: bootconsole [mtk8250] disabled
10658 10:03:25.141514 <6>[ 1.097997] SuperH (H)SCI(F) driver initialized
10659 10:03:25.144271 <6>[ 1.103289] msm_serial: driver initialized
10660 10:03:25.159248 <6>[ 1.112441] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10661 10:03:25.169016 <6>[ 1.120987] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10662 10:03:25.175507 <6>[ 1.129530] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10663 10:03:25.185224 <6>[ 1.138159] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10664 10:03:25.195635 <6>[ 1.146868] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10665 10:03:25.202385 <6>[ 1.155582] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10666 10:03:25.212186 <6>[ 1.164129] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10667 10:03:25.218958 <6>[ 1.172952] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10668 10:03:25.229000 <6>[ 1.181496] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10669 10:03:25.240570 <6>[ 1.197129] loop: module loaded
10670 10:03:25.247219 <6>[ 1.203142] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10671 10:03:25.269597 <4>[ 1.226564] mtk-pmic-keys: Failed to locate of_node [id: -1]
10672 10:03:25.276467 <6>[ 1.233457] megasas: 07.719.03.00-rc1
10673 10:03:25.286590 <6>[ 1.243170] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10674 10:03:25.293277 <6>[ 1.249203] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10675 10:03:25.309396 <6>[ 1.265954] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10676 10:03:25.366055 <6>[ 1.316015] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10677 10:03:27.222190 <6>[ 3.179367] Freeing initrd memory: 55116K
10678 10:03:27.232890 <6>[ 3.189909] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10679 10:03:27.243664 <6>[ 3.200758] tun: Universal TUN/TAP device driver, 1.6
10680 10:03:27.247259 <6>[ 3.206855] thunder_xcv, ver 1.0
10681 10:03:27.250346 <6>[ 3.210360] thunder_bgx, ver 1.0
10682 10:03:27.253406 <6>[ 3.213856] nicpf, ver 1.0
10683 10:03:27.264008 <6>[ 3.217901] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10684 10:03:27.267387 <6>[ 3.225377] hns3: Copyright (c) 2017 Huawei Corporation.
10685 10:03:27.273768 <6>[ 3.230968] hclge is initializing
10686 10:03:27.277385 <6>[ 3.234543] e1000: Intel(R) PRO/1000 Network Driver
10687 10:03:27.283857 <6>[ 3.239672] e1000: Copyright (c) 1999-2006 Intel Corporation.
10688 10:03:27.287563 <6>[ 3.245684] e1000e: Intel(R) PRO/1000 Network Driver
10689 10:03:27.294458 <6>[ 3.250899] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10690 10:03:27.300989 <6>[ 3.257083] igb: Intel(R) Gigabit Ethernet Network Driver
10691 10:03:27.307582 <6>[ 3.262733] igb: Copyright (c) 2007-2014 Intel Corporation.
10692 10:03:27.313839 <6>[ 3.268568] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10693 10:03:27.320402 <6>[ 3.275087] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10694 10:03:27.323720 <6>[ 3.281560] sky2: driver version 1.30
10695 10:03:27.330747 <6>[ 3.286621] VFIO - User Level meta-driver version: 0.3
10696 10:03:27.338091 <6>[ 3.294993] usbcore: registered new interface driver usb-storage
10697 10:03:27.344691 <6>[ 3.301440] usbcore: registered new device driver onboard-usb-hub
10698 10:03:27.353811 <6>[ 3.310665] mt6397-rtc mt6359-rtc: registered as rtc0
10699 10:03:27.363434 <6>[ 3.316162] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-24T10:03:27 UTC (1700820207)
10700 10:03:27.366941 <6>[ 3.325792] i2c_dev: i2c /dev entries driver
10701 10:03:27.383585 <6>[ 3.337715] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10702 10:03:27.403876 <6>[ 3.360732] cpu cpu0: EM: created perf domain
10703 10:03:27.407100 <6>[ 3.365658] cpu cpu4: EM: created perf domain
10704 10:03:27.414355 <6>[ 3.371222] sdhci: Secure Digital Host Controller Interface driver
10705 10:03:27.420973 <6>[ 3.377653] sdhci: Copyright(c) Pierre Ossman
10706 10:03:27.427539 <6>[ 3.382612] Synopsys Designware Multimedia Card Interface Driver
10707 10:03:27.434656 <6>[ 3.389262] sdhci-pltfm: SDHCI platform and OF driver helper
10708 10:03:27.437962 <6>[ 3.389392] mmc0: CQHCI version 5.10
10709 10:03:27.443855 <6>[ 3.399264] ledtrig-cpu: registered to indicate activity on CPUs
10710 10:03:27.451036 <6>[ 3.406192] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10711 10:03:27.457524 <6>[ 3.413248] usbcore: registered new interface driver usbhid
10712 10:03:27.460363 <6>[ 3.419071] usbhid: USB HID core driver
10713 10:03:27.467256 <6>[ 3.423271] spi_master spi0: will run message pump with realtime priority
10714 10:03:27.510670 <6>[ 3.461414] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10715 10:03:27.529041 <6>[ 3.476658] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10716 10:03:27.536240 <6>[ 3.491546] cros-ec-spi spi0.0: Chrome EC device registered
10717 10:03:27.539634 <6>[ 3.497662] mmc0: Command Queue Engine enabled
10718 10:03:27.546607 <6>[ 3.502419] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10719 10:03:27.552948 <6>[ 3.510147] mmcblk0: mmc0:0001 DA4128 116 GiB
10720 10:03:27.562962 <6>[ 3.520887] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10721 10:03:27.570844 <6>[ 3.528679] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10722 10:03:27.581130 <6>[ 3.533036] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10723 10:03:27.584362 <6>[ 3.534632] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10724 10:03:27.590989 <6>[ 3.544635] NET: Registered PF_PACKET protocol family
10725 10:03:27.597544 <6>[ 3.549236] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10726 10:03:27.601342 <6>[ 3.553819] 9pnet: Installing 9P2000 support
10727 10:03:27.607456 <5>[ 3.564824] Key type dns_resolver registered
10728 10:03:27.611017 <6>[ 3.569770] registered taskstats version 1
10729 10:03:27.617477 <5>[ 3.574147] Loading compiled-in X.509 certificates
10730 10:03:27.646062 <4>[ 3.597252] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10731 10:03:27.656580 <4>[ 3.608185] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10732 10:03:27.662717 <3>[ 3.618734] debugfs: File 'uA_load' in directory '/' already present!
10733 10:03:27.669671 <3>[ 3.625489] debugfs: File 'min_uV' in directory '/' already present!
10734 10:03:27.676455 <3>[ 3.632124] debugfs: File 'max_uV' in directory '/' already present!
10735 10:03:27.682845 <3>[ 3.638750] debugfs: File 'constraint_flags' in directory '/' already present!
10736 10:03:27.694091 <3>[ 3.648563] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10737 10:03:27.703172 <6>[ 3.660902] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10738 10:03:27.710618 <6>[ 3.667996] xhci-mtk 11200000.usb: xHCI Host Controller
10739 10:03:27.717020 <6>[ 3.673503] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10740 10:03:27.726900 <6>[ 3.681355] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10741 10:03:27.733821 <6>[ 3.690771] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10742 10:03:27.740221 <6>[ 3.696836] xhci-mtk 11200000.usb: xHCI Host Controller
10743 10:03:27.747130 <6>[ 3.702312] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10744 10:03:27.753746 <6>[ 3.709958] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10745 10:03:27.760255 <6>[ 3.717562] hub 1-0:1.0: USB hub found
10746 10:03:27.763741 <6>[ 3.721572] hub 1-0:1.0: 1 port detected
10747 10:03:27.770395 <6>[ 3.725846] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10748 10:03:27.777338 <6>[ 3.734397] hub 2-0:1.0: USB hub found
10749 10:03:27.780143 <6>[ 3.738399] hub 2-0:1.0: 1 port detected
10750 10:03:27.788652 <6>[ 3.746359] mtk-msdc 11f70000.mmc: Got CD GPIO
10751 10:03:27.798650 <6>[ 3.752608] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10752 10:03:27.805396 <6>[ 3.760637] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10753 10:03:27.815492 <4>[ 3.768531] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10754 10:03:27.822048 <6>[ 3.778054] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10755 10:03:27.832307 <6>[ 3.786135] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10756 10:03:27.838819 <6>[ 3.794154] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10757 10:03:27.848619 <6>[ 3.802076] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10758 10:03:27.855374 <6>[ 3.809892] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10759 10:03:27.865669 <6>[ 3.817713] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10760 10:03:27.871992 <6>[ 3.827895] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10761 10:03:27.881829 <6>[ 3.836257] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10762 10:03:27.889044 <6>[ 3.844602] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10763 10:03:27.898645 <6>[ 3.852942] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10764 10:03:27.908564 <6>[ 3.861279] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10765 10:03:27.915321 <6>[ 3.869628] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10766 10:03:27.925180 <6>[ 3.877968] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10767 10:03:27.932033 <6>[ 3.886335] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10768 10:03:27.941841 <6>[ 3.894678] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10769 10:03:27.948743 <6>[ 3.903019] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10770 10:03:27.958418 <6>[ 3.911358] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10771 10:03:27.964838 <6>[ 3.919696] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10772 10:03:27.975074 <6>[ 3.928036] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10773 10:03:27.981732 <6>[ 3.936376] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10774 10:03:27.991199 <6>[ 3.944714] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10775 10:03:27.997837 <6>[ 3.953484] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10776 10:03:28.004622 <6>[ 3.960689] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10777 10:03:28.011448 <6>[ 3.967602] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10778 10:03:28.018091 <6>[ 3.974481] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10779 10:03:28.024468 <6>[ 3.981488] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10780 10:03:28.034708 <6>[ 3.988344] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10781 10:03:28.044644 <6>[ 3.997472] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10782 10:03:28.054566 <6>[ 4.006592] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10783 10:03:28.060935 <6>[ 4.015887] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10784 10:03:28.071256 <6>[ 4.025358] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10785 10:03:28.080751 <6>[ 4.034826] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10786 10:03:28.091081 <6>[ 4.043965] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10787 10:03:28.101286 <6>[ 4.053435] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10788 10:03:28.107792 <6>[ 4.062553] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10789 10:03:28.117821 <6>[ 4.071847] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10790 10:03:28.131133 <6>[ 4.082013] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10791 10:03:28.137747 <6>[ 4.093451] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10792 10:03:28.187503 <6>[ 4.142082] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10793 10:03:28.342772 <6>[ 4.300162] hub 1-1:1.0: USB hub found
10794 10:03:28.345444 <6>[ 4.304673] hub 1-1:1.0: 4 ports detected
10795 10:03:28.355359 <6>[ 4.313169] hub 1-1:1.0: USB hub found
10796 10:03:28.358464 <6>[ 4.317556] hub 1-1:1.0: 4 ports detected
10797 10:03:28.467999 <6>[ 4.422465] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10798 10:03:28.494061 <6>[ 4.451886] hub 2-1:1.0: USB hub found
10799 10:03:28.497602 <6>[ 4.456405] hub 2-1:1.0: 3 ports detected
10800 10:03:28.506896 <6>[ 4.464700] hub 2-1:1.0: USB hub found
10801 10:03:28.510750 <6>[ 4.469174] hub 2-1:1.0: 3 ports detected
10802 10:03:28.683633 <6>[ 4.638116] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10803 10:03:28.816468 <6>[ 4.773782] hub 1-1.4:1.0: USB hub found
10804 10:03:28.819506 <6>[ 4.778468] hub 1-1.4:1.0: 2 ports detected
10805 10:03:28.828227 <6>[ 4.786009] hub 1-1.4:1.0: USB hub found
10806 10:03:28.831475 <6>[ 4.790613] hub 1-1.4:1.0: 2 ports detected
10807 10:03:28.895661 <6>[ 4.850268] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10808 10:03:29.127822 <6>[ 5.082132] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10809 10:03:29.319595 <6>[ 5.274108] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10810 10:03:40.437460 <6>[ 16.399198] ALSA device list:
10811 10:03:40.443931 <6>[ 16.402496] No soundcards found.
10812 10:03:40.451704 <6>[ 16.410619] Freeing unused kernel memory: 8384K
10813 10:03:40.455242 <6>[ 16.415619] Run /init as init process
10814 10:03:40.508718 <6>[ 16.467156] NET: Registered PF_INET6 protocol family
10815 10:03:40.515387 <6>[ 16.473278] Segment Routing with IPv6
10816 10:03:40.517995 <6>[ 16.477224] In-situ OAM (IOAM) with IPv6
10817 10:03:40.549574 <30>[ 16.491563] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10818 10:03:40.556851 <30>[ 16.515383] systemd[1]: Detected architecture arm64.
10819 10:03:40.557280
10820 10:03:40.563210 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10821 10:03:40.563775
10822 10:03:40.575786 <30>[ 16.534118] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10823 10:03:40.728907 <30>[ 16.683842] systemd[1]: Queued start job for default target Graphical Interface.
10824 10:03:40.760589 <30>[ 16.719042] systemd[1]: Created slice system-getty.slice.
10825 10:03:40.766923 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10826 10:03:40.783798 <30>[ 16.742538] systemd[1]: Created slice system-modprobe.slice.
10827 10:03:40.790768 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10828 10:03:40.807709 <30>[ 16.766390] systemd[1]: Created slice system-serial\x2dgetty.slice.
10829 10:03:40.817503 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10830 10:03:40.832183 <30>[ 16.791004] systemd[1]: Created slice User and Session Slice.
10831 10:03:40.838639 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10832 10:03:40.859302 <30>[ 16.814984] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10833 10:03:40.869372 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10834 10:03:40.887139 <30>[ 16.842588] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10835 10:03:40.893900 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10836 10:03:40.913707 <30>[ 16.866030] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10837 10:03:40.920388 <30>[ 16.878093] systemd[1]: Reached target Local Encrypted Volumes.
10838 10:03:40.927277 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10839 10:03:40.943715 <30>[ 16.902072] systemd[1]: Reached target Paths.
10840 10:03:40.946408 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10841 10:03:40.962996 <30>[ 16.922020] systemd[1]: Reached target Remote File Systems.
10842 10:03:40.969151 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10843 10:03:40.982667 <30>[ 16.942033] systemd[1]: Reached target Slices.
10844 10:03:40.986572 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10845 10:03:41.003243 <30>[ 16.962112] systemd[1]: Reached target Swap.
10846 10:03:41.006103 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10847 10:03:41.027222 <30>[ 16.982526] systemd[1]: Listening on initctl Compatibility Named Pipe.
10848 10:03:41.033950 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10849 10:03:41.048609 <30>[ 17.007614] systemd[1]: Listening on Journal Audit Socket.
10850 10:03:41.055521 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10851 10:03:41.072718 <30>[ 17.031284] systemd[1]: Listening on Journal Socket (/dev/log).
10852 10:03:41.078721 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10853 10:03:41.095933 <30>[ 17.054642] systemd[1]: Listening on Journal Socket.
10854 10:03:41.102281 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10855 10:03:41.115662 <30>[ 17.074689] systemd[1]: Listening on udev Control Socket.
10856 10:03:41.122505 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10857 10:03:41.140144 <30>[ 17.099159] systemd[1]: Listening on udev Kernel Socket.
10858 10:03:41.146612 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10859 10:03:41.199148 <30>[ 17.158337] systemd[1]: Mounting Huge Pages File System...
10860 10:03:41.205852 Mounting [0;1;39mHuge Pages File System[0m...
10861 10:03:41.221310 <30>[ 17.180048] systemd[1]: Mounting POSIX Message Queue File System...
10862 10:03:41.228425 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10863 10:03:41.249578 <30>[ 17.208214] systemd[1]: Mounting Kernel Debug File System...
10864 10:03:41.255757 Mounting [0;1;39mKernel Debug File System[0m...
10865 10:03:41.274930 <30>[ 17.230537] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10866 10:03:41.307022 <30>[ 17.262884] systemd[1]: Starting Create list of static device nodes for the current kernel...
10867 10:03:41.314106 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10868 10:03:41.336507 <30>[ 17.295248] systemd[1]: Starting Load Kernel Module configfs...
10869 10:03:41.342751 Starting [0;1;39mLoad Kernel Module configfs[0m...
10870 10:03:41.364272 <30>[ 17.323305] systemd[1]: Starting Load Kernel Module drm...
10871 10:03:41.370832 Starting [0;1;39mLoad Kernel Module drm[0m...
10872 10:03:41.386982 <30>[ 17.342536] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10873 10:03:41.440214 <30>[ 17.399060] systemd[1]: Starting Journal Service...
10874 10:03:41.443571 Starting [0;1;39mJournal Service[0m...
10875 10:03:41.464551 <30>[ 17.423154] systemd[1]: Starting Load Kernel Modules...
10876 10:03:41.470577 Starting [0;1;39mLoad Kernel Modules[0m...
10877 10:03:41.489902 <30>[ 17.445793] systemd[1]: Starting Remount Root and Kernel File Systems...
10878 10:03:41.496960 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10879 10:03:41.516440 <30>[ 17.475152] systemd[1]: Starting Coldplug All udev Devices...
10880 10:03:41.522673 Starting [0;1;39mColdplug All udev Devices[0m...
10881 10:03:41.546612 <30>[ 17.505625] systemd[1]: Started Journal Service.
10882 10:03:41.553554 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10883 10:03:41.573200 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10884 10:03:41.596358 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10885 10:03:41.616179 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10886 10:03:41.635620 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10887 10:03:41.654749 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10888 10:03:41.672917 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10889 10:03:41.691729 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10890 10:03:41.711541 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10891 10:03:41.727331 See 'systemctl status systemd-remount-fs.service' for details.
10892 10:03:41.763734 Mounting [0;1;39mKernel Configuration File System[0m...
10893 10:03:41.782432 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10894 10:03:41.795544 <46>[ 17.751153] systemd-journald[186]: Received client request to flush runtime journal.
10895 10:03:41.806450 Starting [0;1;39mLoad/Save Random Seed[0m...
10896 10:03:41.829906 Starting [0;1;39mApply Kernel Variables[0m...
10897 10:03:41.848940 Starting [0;1;39mCreate System Users[0m...
10898 10:03:41.873406 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10899 10:03:41.896179 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10900 10:03:41.920420 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10901 10:03:41.936990 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10902 10:03:41.957267 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10903 10:03:41.977326 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10904 10:03:42.015837 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10905 10:03:42.037338 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10906 10:03:42.051129 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10907 10:03:42.067137 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10908 10:03:42.127897 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10909 10:03:42.153568 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10910 10:03:42.178084 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10911 10:03:42.197110 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10912 10:03:42.256394 Starting [0;1;39mNetwork Time Synchronization[0m...
10913 10:03:42.278755 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10914 10:03:42.311419 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10915 10:03:42.348311 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10916 10:03:42.367173 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10917 10:03:42.378010 <6>[ 18.333982] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10918 10:03:42.388506 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10919 10:03:42.395527 <6>[ 18.354423] remoteproc remoteproc0: scp is available
10920 10:03:42.401902 <6>[ 18.355209] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10921 10:03:42.408645 <6>[ 18.359868] remoteproc remoteproc0: powering up scp
10922 10:03:42.418948 <6>[ 18.367521] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10923 10:03:42.425230 <6>[ 18.372460] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10924 10:03:42.432348 <6>[ 18.372496] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10925 10:03:42.438419 <6>[ 18.395449] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10926 10:03:42.448729 [[0;32m OK [<3>[ 18.405345] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10927 10:03:42.458776 0m] Reached targ<3>[ 18.413877] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10928 10:03:42.465216 <4>[ 18.421393] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10929 10:03:42.474933 <3>[ 18.425815] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10930 10:03:42.482104 et [0;1;39mSystem Time Set[0m.<6>[ 18.441109] mc: Linux media interface: v0.10
10931 10:03:42.482531
10932 10:03:42.492769 <3>[ 18.448410] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10933 10:03:42.499496 <4>[ 18.448452] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10934 10:03:42.509384 <3>[ 18.456538] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10935 10:03:42.515998 <3>[ 18.456543] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10936 10:03:42.522381 <3>[ 18.456553] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10937 10:03:42.529472 <6>[ 18.482649] videodev: Linux video capture interface: v2.00
10938 10:03:42.539464 <3>[ 18.488216] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10939 10:03:42.546295 <3>[ 18.489360] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10940 10:03:42.556174 <6>[ 18.494293] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10941 10:03:42.562328 <6>[ 18.494293] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10942 10:03:42.569107 <3>[ 18.503043] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10943 10:03:42.575752 <6>[ 18.510381] remoteproc remoteproc0: remote processor scp is now up
10944 10:03:42.582968 <6>[ 18.537496] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10945 10:03:42.592539 <3>[ 18.540569] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10946 10:03:42.599545 <6>[ 18.543111] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10947 10:03:42.605843 <6>[ 18.543119] pci_bus 0000:00: root bus resource [bus 00-ff]
10948 10:03:42.612263 <6>[ 18.543125] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10949 10:03:42.622149 <6>[ 18.543133] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10950 10:03:42.629150 <6>[ 18.543176] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10951 10:03:42.635756 <6>[ 18.543191] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10952 10:03:42.639468 <6>[ 18.543267] pci 0000:00:00.0: supports D1 D2
10953 10:03:42.645800 <6>[ 18.543269] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10954 10:03:42.653391 <6>[ 18.544400] usbcore: registered new interface driver r8152
10955 10:03:42.660051 <6>[ 18.545349] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10956 10:03:42.666330 <6>[ 18.545607] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10957 10:03:42.676152 <6>[ 18.545637] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10958 10:03:42.682813 <6>[ 18.545659] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10959 10:03:42.689788 <6>[ 18.545674] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10960 10:03:42.693177 <6>[ 18.545788] pci 0000:01:00.0: supports D1 D2
10961 10:03:42.703124 <6>[ 18.545790] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10962 10:03:42.710115 <6>[ 18.557917] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10963 10:03:42.716554 <3>[ 18.563135] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10964 10:03:42.726088 <3>[ 18.563256] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10965 10:03:42.732931 <6>[ 18.569034] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10966 10:03:42.739570 <3>[ 18.576070] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10967 10:03:42.749557 <4>[ 18.585997] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10968 10:03:42.755968 <4>[ 18.585997] Fallback method does not support PEC.
10969 10:03:42.762722 <6>[ 18.586541] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10970 10:03:42.769103 <6>[ 18.586602] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10971 10:03:42.778901 <6>[ 18.586617] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10972 10:03:42.785609 <6>[ 18.586630] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10973 10:03:42.792776 <6>[ 18.586644] pci 0000:00:00.0: PCI bridge to [bus 01]
10974 10:03:42.799232 <6>[ 18.586649] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10975 10:03:42.809837 <6>[ 18.589150] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10976 10:03:42.816439 <6>[ 18.590216] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10977 10:03:42.822968 <3>[ 18.592232] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10978 10:03:42.833743 <6>[ 18.608343] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10979 10:03:42.841270 <3>[ 18.611092] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10980 10:03:42.851408 <3>[ 18.611097] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10981 10:03:42.857534 <3>[ 18.612072] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10982 10:03:42.864735 <6>[ 18.614119] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10983 10:03:42.868486 <6>[ 18.614338] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10984 10:03:42.878718 <3>[ 18.616674] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10985 10:03:42.889171 <6>[ 18.618577] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10986 10:03:42.895913 <6>[ 18.618700] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10987 10:03:42.905867 <6>[ 18.621483] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10988 10:03:42.912638 <6>[ 18.622232] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10989 10:03:42.919155 <4>[ 18.649273] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10990 10:03:42.925928 <6>[ 18.673434] usbcore: registered new interface driver cdc_ether
10991 10:03:42.936670 <4>[ 18.681693] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10992 10:03:42.939627 <6>[ 18.697788] Bluetooth: Core ver 2.22
10993 10:03:42.946201 <5>[ 18.700304] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10994 10:03:42.952938 <6>[ 18.706203] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10995 10:03:42.959810 <5>[ 18.708752] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10996 10:03:42.969750 <4>[ 18.708877] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10997 10:03:42.973364 <6>[ 18.708885] cfg80211: failed to load regulatory.db
10998 10:03:42.979511 <6>[ 18.719001] NET: Registered PF_BLUETOOTH protocol family
10999 10:03:42.986658 <6>[ 18.719892] usbcore: registered new interface driver r8153_ecm
11000 10:03:42.999317 <6>[ 18.728097] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11001 10:03:43.006326 <6>[ 18.734901] Bluetooth: HCI device and connection manager initialized
11002 10:03:43.009600 <6>[ 18.734936] Bluetooth: HCI socket layer initialized
11003 10:03:43.016287 <6>[ 18.743113] usbcore: registered new interface driver uvcvideo
11004 10:03:43.023260 <6>[ 18.750910] Bluetooth: L2CAP socket layer initialized
11005 10:03:43.025906 <6>[ 18.750925] Bluetooth: SCO socket layer initialized
11006 10:03:43.032572 <6>[ 18.751887] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11007 10:03:43.036188 <6>[ 18.753958] r8152 2-1.3:1.0 eth0: v1.12.13
11008 10:03:43.042987 <6>[ 18.768587] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
11009 10:03:43.053383 <3>[ 18.778020] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11010 10:03:43.060548 <3>[ 18.778684] power_supply sbs-5-000b: driver failed to report `temp' property: -6
11011 10:03:43.070705 <3>[ 18.802180] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11012 10:03:43.076988 <3>[ 18.803003] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11013 10:03:43.083670 <6>[ 18.816087] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11014 10:03:43.090236 <6>[ 18.828784] usbcore: registered new interface driver btusb
11015 10:03:43.100486 <4>[ 18.829473] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11016 10:03:43.107348 <3>[ 18.829487] Bluetooth: hci0: Failed to load firmware file (-2)
11017 10:03:43.113624 <3>[ 18.829493] Bluetooth: hci0: Failed to set up firmware (-2)
11018 10:03:43.123547 <4>[ 18.829499] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11019 10:03:43.133752 <3>[ 18.831895] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11020 10:03:43.140106 <6>[ 18.834328] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11021 10:03:43.147081 <3>[ 18.851611] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11022 10:03:43.153384 <6>[ 18.869952] mt7921e 0000:01:00.0: ASIC revision: 79610010
11023 10:03:43.163825 <3>[ 18.896460] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11024 10:03:43.173305 <4>[ 18.988954] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11025 10:03:43.180605 <3>[ 19.011216] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11026 10:03:43.193865 <4>[ 19.123346] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11027 10:03:43.200399 <3>[ 19.147071] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11028 10:03:43.208508 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11029 10:03:43.263376 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11030 10:03:43.284144 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11031 10:03:43.312601 <4>[ 19.264700] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11032 10:03:43.426989 <4>[ 19.379554] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11033 10:03:43.436286 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11034 10:03:43.451219 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11035 10:03:43.470661 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11036 10:03:43.486224 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11037 10:03:43.498794 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11038 10:03:43.519156 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11039 10:03:43.537789 [[0;32m OK [<4>[ 19.491442] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11040 10:03:43.541499 0m] Reached target [0;1;39mSockets[0m.
11041 10:03:43.559366 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11042 10:03:43.579033 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11043 10:03:43.628165 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11044 10:03:43.660490 <4>[ 19.613026] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11045 10:03:43.704270 Starting [0;1;39mUser Login Management[0m...
11046 10:03:43.724182 Starting [0;1;39mPermit User Sessions[0m...
11047 10:03:43.746571 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11048 10:03:43.767179 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11049 10:03:43.784922 <4>[ 19.737235] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11050 10:03:43.795127 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11051 10:03:43.805275 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11052 10:03:43.864679 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11053 10:03:43.899518 [[0;32m OK [<4>[ 19.853374] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11054 10:03:43.906222 0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11055 10:03:43.914205 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11056 10:03:43.928727 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11057 10:03:43.944001 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11058 10:03:44.011887 <4>[ 19.964315] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11059 10:03:44.018191 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11060 10:03:44.061867 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11061 10:03:44.095349
11062 10:03:44.095941
11063 10:03:44.098471 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11064 10:03:44.098942
11065 10:03:44.101971 debian-bullseye-arm64 login: root (automatic login)
11066 10:03:44.102409
11067 10:03:44.102920
11068 10:03:44.129787 <4>[ 20.082391] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11069 10:03:44.137031 Linux debian-bullseye-arm64 6.1.62-cip9 #1 SMP PREEMPT Fri Nov 24 09:44:51 UTC 2023 aarch64
11070 10:03:44.137484
11071 10:03:44.143723 The programs included with the Debian GNU/Linux system are free software;
11072 10:03:44.149878 the exact distribution terms for each program are described in the
11073 10:03:44.157002 individual files in /usr/share/doc/*/copyright.
11074 10:03:44.157443
11075 10:03:44.159771 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11076 10:03:44.163340 permitted by applicable law.
11077 10:03:44.164636 Matched prompt #10: / #
11079 10:03:44.165762 Setting prompt string to ['/ #']
11080 10:03:44.166295 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11082 10:03:44.167543 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11083 10:03:44.168084 start: 2.2.6 expect-shell-connection (timeout 00:02:46) [common]
11084 10:03:44.168482 Setting prompt string to ['/ #']
11085 10:03:44.168882 Forcing a shell prompt, looking for ['/ #']
11087 10:03:44.219870 / #
11088 10:03:44.220457 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11089 10:03:44.220926 Waiting using forced prompt support (timeout 00:02:30)
11090 10:03:44.226227
11091 10:03:44.227063 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11092 10:03:44.227614 start: 2.2.7 export-device-env (timeout 00:02:46) [common]
11093 10:03:44.228157 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11094 10:03:44.228715 end: 2.2 depthcharge-retry (duration 00:02:14) [common]
11095 10:03:44.229343 end: 2 depthcharge-action (duration 00:02:14) [common]
11096 10:03:44.229934 start: 3 lava-test-retry (timeout 00:07:23) [common]
11097 10:03:44.230470 start: 3.1 lava-test-shell (timeout 00:07:23) [common]
11098 10:03:44.230977 Using namespace: common
11100 10:03:44.332149 / # #
11101 10:03:44.332341 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11102 10:03:44.332485 <3>[ 20.206849] mt7921e 0000:01:00.0: hardware init failed
11103 10:03:44.337516 #
11104 10:03:44.337794 Using /lava-12073323
11106 10:03:44.438218 / # export SHELL=/bin/sh
11107 10:03:44.443801 export SHELL=/bin/sh
11109 10:03:44.544520 / # . /lava-12073323/environment
11110 10:03:44.551401 . /lava-12073323/environment
11112 10:03:44.653168 / # /lava-12073323/bin/lava-test-runner /lava-12073323/0
11113 10:03:44.653876 Test shell timeout: 10s (minimum of the action and connection timeout)
11114 10:03:44.660111 /lava-12073323/bin/lava-test-runner /lava-12073323/0
11115 10:03:44.686389 + export TESTRUN_ID=0_igt-kms-me<8>[ 20.645142] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 12073323_1.5.2.3.1>
11116 10:03:44.686655 Received signal: <STARTRUN> 0_igt-kms-mediatek 12073323_1.5.2.3.1
11117 10:03:44.686761 Starting test lava.0_igt-kms-mediatek (12073323_1.5.2.3.1)
11118 10:03:44.686917 Skipping test definition patterns.
11119 10:03:44.689614 diatek
11120 10:03:44.692908 + cd /lava-12073323/0/tests/0_igt-kms-mediatek
11121 10:03:44.693024 + cat uuid
11122 10:03:44.696951 + UUID=12073323_1.5.2.3.1
11123 10:03:44.697053 + set +x
11124 10:03:44.709465 + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getstats core_getversi<8>[ 20.670082] <LAVA_SIGNAL_TESTSET START core_auth>
11125 10:03:44.709755 Received signal: <TESTSET> START core_auth
11126 10:03:44.709854 Starting test_set core_auth
11127 10:03:44.719761 on core_setmaster_vs_auth drm_read kms_addfb_basic kms_atomic kms_flip_event_leak kms_prop_blob kms_setmode kms_vblank
11128 10:03:44.728237 <14>[ 20.687839] [IGT] core_auth: executing
11129 10:03:44.734768 IGT-Version: 1.2<14>[ 20.692214] [IGT] core_auth: starting subtest getclient-simple
11130 10:03:44.744573 7.1-g621c2d3 (aa<14>[ 20.699850] [IGT] core_auth: finished subtest getclient-simple, SUCCESS
11131 10:03:44.748061 rch64) (Linux: 6<14>[ 20.708124] [IGT] core_auth: exiting, ret=0
11132 10:03:44.751538 .1.62-cip9 aarch64)
11133 10:03:44.754805 Starting subtest: getclient-simple
11134 10:03:44.758377 Opened device: /dev/dri/card0
11135 10:03:44.765449 [1mSubt<8>[ 20.721340] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
11136 10:03:44.765707 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
11138 10:03:44.767983 est getclient-simple: SUCCESS (0.000s)[0m
11139 10:03:44.791732 <14>[ 20.751637] [IGT] core_auth: executing
11140 10:03:44.798457 IGT-Version: 1.2<14>[ 20.756243] [IGT] core_auth: starting subtest getclient-master-drop
11141 10:03:44.808668 7.1-g621c2d3 (aa<14>[ 20.764341] [IGT] core_auth: finished subtest getclient-master-drop, SUCCESS
11142 10:03:44.815670 rch64) (Linux: 6<14>[ 20.772992] [IGT] core_auth: exiting, ret=0
11143 10:03:44.815760 .1.62-cip9 aarch64)
11144 10:03:44.818374 Starting subtest: getclient-master-drop
11145 10:03:44.828811 Opened device: /de<8>[ 20.784928] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
11146 10:03:44.828894 v/dri/card0
11147 10:03:44.829131 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
11149 10:03:44.835239 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
11150 10:03:44.845794 <14>[ 20.805746] [IGT] core_auth: executing
11151 10:03:44.852725 IGT-Version: 1.2<14>[ 20.810191] [IGT] core_auth: starting subtest basic-auth
11152 10:03:44.859627 7.1-g621c2d3 (aa<14>[ 20.817250] [IGT] core_auth: finished subtest basic-auth, SUCCESS
11153 10:03:44.866392 rch64) (Linux: 6<14>[ 20.824993] [IGT] core_auth: exiting, ret=0
11154 10:03:44.869206 .1.62-cip9 aarch64)
11155 10:03:44.869331 Opened device: /dev/dri/card0
11156 10:03:44.879448 Starting sub<8>[ 20.835158] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
11157 10:03:44.879962 test: basic-auth
11158 10:03:44.880638 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
11160 10:03:44.883326 [1mSubtest basic-auth: SUCCESS (0.000s)[0m
11161 10:03:44.895812 <14>[ 20.855057] [IGT] core_auth: executing
11162 10:03:44.902457 IGT-Version: 1.2<14>[ 20.859516] [IGT] core_auth: starting subtest many-magics
11163 10:03:44.905822 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11164 10:03:44.915610 Opened device: /dev/dri/car<14>[ 20.873332] [IGT] core_auth: finished subtest many-magics, SUCCESS
11165 10:03:44.916059 d0
11166 10:03:44.922600 Starting sub<14>[ 20.880106] [IGT] core_auth: exiting, ret=0
11167 10:03:44.923138 test: many-magics
11168 10:03:44.926191 Reopening device failed after 1020 opens
11169 10:03:44.932528 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
11171 10:03:44.935513 [1<8>[ 20.890496] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
11172 10:03:44.942029 mSubtest many-magics: SUCCESS (0<8>[ 20.899989] <LAVA_SIGNAL_TESTSET STOP>
11173 10:03:44.942580 .007s)[0m
11174 10:03:44.943373 Received signal: <TESTSET> STOP
11175 10:03:44.943857 Closing test_set core_auth
11176 10:03:44.982295 <14>[ 20.941743] [IGT] core_getclient: executing
11177 10:03:44.989797 IGT-Version: 1.2<14>[ 20.946860] [IGT] core_getclient: exiting, ret=0
11178 10:03:44.992709 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11179 10:03:45.002288 Opened device: /dev/dri/car<8>[ 20.958828] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
11180 10:03:45.002802 d0
11181 10:03:45.003588 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
11183 10:03:45.005768 SUCCESS (0.006s)
11184 10:03:45.032592 <14>[ 20.992160] [IGT] core_getstats: executing
11185 10:03:45.039786 IGT-Version: 1.2<14>[ 20.996918] [IGT] core_getstats: exiting, ret=0
11186 10:03:45.042910 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11187 10:03:45.053130 Opened devi<8>[ 21.008568] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
11188 10:03:45.053781 ce: /dev/dri/card0
11189 10:03:45.054503 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
11191 10:03:45.056378 SUCCESS (0.006s)
11192 10:03:45.081655 <14>[ 21.041130] [IGT] core_getversion: executing
11193 10:03:45.088128 IGT-Version: 1.2<14>[ 21.046243] [IGT] core_getversion: exiting, ret=0
11194 10:03:45.091868 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11195 10:03:45.101742 Opened devi<8>[ 21.057561] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
11196 10:03:45.102169 ce: /dev/dri/card0
11197 10:03:45.102762 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
11199 10:03:45.105095 SUCCESS (0.006s)
11200 10:03:45.148396 <14>[ 21.107770] [IGT] core_setmaster_vs_auth: executing
11201 10:03:45.154980 IGT-Version: 1.2<14>[ 21.113660] [IGT] core_setmaster_vs_auth: exiting, ret=0
11202 10:03:45.161802 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11203 10:03:45.162234 Opened device: /dev/dri/card0
11204 10:03:45.171946 SUCCESS (0.0<8>[ 21.128179] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
11205 10:03:45.172376 07s)
11206 10:03:45.172972 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
11208 10:03:45.196141 <8>[ 21.155404] <LAVA_SIGNAL_TESTSET START drm_read>
11209 10:03:45.196818 Received signal: <TESTSET> START drm_read
11210 10:03:45.197168 Starting test_set drm_read
11211 10:03:45.215360 <14>[ 21.174819] [IGT] drm_read: executing
11212 10:03:45.221708 IGT-Version: 1.2<14>[ 21.179310] [IGT] drm_read: exiting, ret=77
11213 10:03:45.225024 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11214 10:03:45.228982 Opened device: /dev/dri/card0
11215 10:03:45.234920 No KMS drive<8>[ 21.191997] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
11216 10:03:45.235176 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
11218 10:03:45.238517 r or no outputs, pipes: 8, outputs: 0
11219 10:03:45.241577 [1mSubtest invalid-buffer: SKIP (0.000s)[0m
11220 10:03:45.256891 <14>[ 21.216064] [IGT] drm_read: executing
11221 10:03:45.262884 IGT-Version: 1.2<14>[ 21.220515] [IGT] drm_read: exiting, ret=77
11222 10:03:45.266052 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11223 10:03:45.276605 Opened device: /dev/dri/car<8>[ 21.231711] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
11224 10:03:45.276877 d0
11225 10:03:45.277261 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
11227 10:03:45.279486 No KMS driver or no outputs, pipes: 8, outputs: 0
11228 10:03:45.283012 [1mSubtest fault-buffer: SKIP (0.000s)[0m
11229 10:03:45.293279 <14>[ 21.252548] [IGT] drm_read: executing
11230 10:03:45.296666 IGT-Version: 1.2<14>[ 21.257013] [IGT] drm_read: exiting, ret=77
11231 10:03:45.303641 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11232 10:03:45.313860 Opened device: /dev/dri/car<8>[ 21.269381] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
11233 10:03:45.314289 d0
11234 10:03:45.314918 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
11236 10:03:45.316791 No KMS driver or no outputs, pipes: 8, outputs: 0
11237 10:03:45.319749 [1mSubtest empty-block: SKIP (0.000s)[0m
11238 10:03:45.329496 <14>[ 21.288653] [IGT] drm_read: executing
11239 10:03:45.332591 IGT-Version: 1.2<14>[ 21.293097] [IGT] drm_read: exiting, ret=77
11240 10:03:45.339138 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11241 10:03:45.349122 Opened device: /dev/dri/car<8>[ 21.304480] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
11242 10:03:45.349559 d0
11243 10:03:45.350150 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
11245 10:03:45.352340 No KMS driver or no outputs, pipes: 8, outputs: 0
11246 10:03:45.356163 [1mSubtest empty-nonblock: SKIP (0.000s)[0m
11247 10:03:45.365681 <14>[ 21.324997] [IGT] drm_read: executing
11248 10:03:45.372643 IGT-Version: 1.2<14>[ 21.329470] [IGT] drm_read: exiting, ret=77
11249 10:03:45.375881 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11250 10:03:45.385569 Opened device: /dev/dri/car<8>[ 21.340703] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
11251 10:03:45.386002 d0
11252 10:03:45.386598 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
11254 10:03:45.388717 No KMS driver or no outputs, pipes: 8, outputs: 0
11255 10:03:45.395558 [1mSubtest short-buffer-block: SKIP (0.000s)[0m
11256 10:03:45.402393 <14>[ 21.361929] [IGT] drm_read: executing
11257 10:03:45.409067 IGT-Version: 1.2<14>[ 21.366405] [IGT] drm_read: exiting, ret=77
11258 10:03:45.412742 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11259 10:03:45.419398 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11261 10:03:45.422385 Opened devi<8>[ 21.377424] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
11262 10:03:45.422824 ce: /dev/dri/card0
11263 10:03:45.425755 No KMS driver or no outputs, pipes: 8, outputs: 0
11264 10:03:45.432404 [1mSubtest short-buffer-nonblock: SKIP (0.000s)[0m
11265 10:03:45.440230 <14>[ 21.399515] [IGT] drm_read: executing
11266 10:03:45.446741 IGT-Version: 1.2<14>[ 21.404026] [IGT] drm_read: exiting, ret=77
11267 10:03:45.450164 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11268 10:03:45.459932 Opened device: /dev/dri/car<8>[ 21.415555] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
11269 10:03:45.460360 d0
11270 10:03:45.460945 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11272 10:03:45.466807 No KMS driver or no outputs,<8>[ 21.425752] <LAVA_SIGNAL_TESTSET STOP>
11273 10:03:45.467544 Received signal: <TESTSET> STOP
11274 10:03:45.467887 Closing test_set drm_read
11275 10:03:45.469834 pipes: 8, outputs: 0
11276 10:03:45.473082 [1mSubtest short-buffer-wakeup: SKIP (0.000s)[0m
11277 10:03:45.487818 <8>[ 21.447621] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
11278 10:03:45.488498 Received signal: <TESTSET> START kms_addfb_basic
11279 10:03:45.488846 Starting test_set kms_addfb_basic
11280 10:03:45.516463 <14>[ 21.475910] [IGT] kms_addfb_basic: executing
11281 10:03:45.530204 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch<14>[ 21.485483] [IGT] kms_addfb_basic: starting subtest unused-handle
11282 10:03:45.530635 64)
11283 10:03:45.536922 Opened devi<14>[ 21.493043] [IGT] kms_addfb_basic: finished subtest unused-handle, SUCCESS
11284 10:03:45.539656 ce: /dev/dri/card0
11285 10:03:45.542985 Starting subtest: unused-handle
11286 10:03:45.546664 [1mSubtest unused-handle: SUCCESS (0.000s)[0m
11287 10:03:45.553230 Test requirement<14>[ 21.510715] [IGT] kms_addfb_basic: exiting, ret=0
11288 10:03:45.559881 not met in function igt_require_i915, file ../lib/drmtest.c:720:
11289 10:03:45.566500 Test requirem<8>[ 21.523164] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
11290 10:03:45.567358 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11292 10:03:45.569525 ent: is_i915_device(fd)
11293 10:03:45.576478 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11294 10:03:45.580009 Test requirement: is_i915_device(fd)
11295 10:03:45.586638 No KMS driver or no outputs, p<14>[ 21.546096] [IGT] kms_addfb_basic: executing
11296 10:03:45.589442 ipes: 8, outputs: 0
11297 10:03:45.600496 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Lin<14>[ 21.555430] [IGT] kms_addfb_basic: starting subtest unused-pitches
11298 10:03:45.606418 ux: 6.1.62-cip9 <14>[ 21.563184] [IGT] kms_addfb_basic: finished subtest unused-pitches, SUCCESS
11299 10:03:45.609838 aarch64)
11300 10:03:45.610252 Opened device: /dev/dri/card0
11301 10:03:45.612973 Starting subtest: unused-pitches
11302 10:03:45.619865 [1mSubtest unused-pi<14>[ 21.580019] [IGT] kms_addfb_basic: exiting, ret=0
11303 10:03:45.623346 tches: SUCCESS (0.000s)[0m
11304 10:03:45.636708 Test requirement not met in function igt_require_i9<8>[ 21.591459] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
11305 10:03:45.637137 15, file ../lib/drmtest.c:720:
11306 10:03:45.637740 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11308 10:03:45.639644 Test requirement: is_i915_device(fd)
11309 10:03:45.649776 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11310 10:03:45.652528 Test re<14>[ 21.613132] [IGT] kms_addfb_basic: executing
11311 10:03:45.656428 quirement: is_i915_device(fd)
11312 10:03:45.665981 No KMS driver or no outputs, pipe<14>[ 21.622410] [IGT] kms_addfb_basic: starting subtest unused-offsets
11313 10:03:45.672630 s: 8, outputs: 0<14>[ 21.630323] [IGT] kms_addfb_basic: finished subtest unused-offsets, SUCCESS
11314 10:03:45.676260
11315 10:03:45.679429 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11316 10:03:45.689521 Opened device: /dev/dri/c<14>[ 21.647064] [IGT] kms_addfb_basic: exiting, ret=0
11317 10:03:45.689948 ard0
11318 10:03:45.692526 Starting subtest: unused-offsets
11319 10:03:45.702947 [1mSubtest unused-offsets: SUCCESS (0.0<8>[ 21.658305] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
11320 10:03:45.703377 00s)[0m
11321 10:03:45.703992 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11323 10:03:45.709147 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11324 10:03:45.712656 Test requirement: is_i915_device(fd)
11325 10:03:45.719199 Test requirement not met in f<14>[ 21.679684] [IGT] kms_addfb_basic: executing
11326 10:03:45.725921 unction igt_require_i915, file ../lib/drmtest.c:720:
11327 10:03:45.732855 Test requi<14>[ 21.689469] [IGT] kms_addfb_basic: starting subtest unused-modifier
11328 10:03:45.742670 rement: is_i915_<14>[ 21.697462] [IGT] kms_addfb_basic: finished subtest unused-modifier, SUCCESS
11329 10:03:45.743334 device(fd)
11330 10:03:45.745946 No KMS driver or no outputs, pipes: 8, outputs: 0
11331 10:03:45.755721 IGT-Version: 1.27.1-g621c2d3 (aar<14>[ 21.714218] [IGT] kms_addfb_basic: exiting, ret=0
11332 10:03:45.759467 ch64) (Linux: 6.1.62-cip9 aarch64)
11333 10:03:45.762759 Opened device: /dev/dri/card0
11334 10:03:45.769325 Starting subt<8>[ 21.725645] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
11335 10:03:45.770449 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11337 10:03:45.772474 est: unused-modifier
11338 10:03:45.775927 [1mSubtest unused-modifier: SUCCESS (0.000s)[0m
11339 10:03:45.782511 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11340 10:03:45.789181 Test<14>[ 21.747211] [IGT] kms_addfb_basic: executing
11341 10:03:45.793206 requirement: is_i915_device(fd)
11342 10:03:45.799477 Test requirement not met in fu<14>[ 21.756711] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
11343 10:03:45.809225 nction igt_requi<14>[ 21.765041] [IGT] kms_addfb_basic: finished subtest clobberred-modifier, SKIP
11344 10:03:45.812746 re_i915, file ../lib/drmtest.c:720:
11345 10:03:45.815635 Test requirement: is_i915_device(fd)
11346 10:03:45.822575 No KMS driver or no o<14>[ 21.782146] [IGT] kms_addfb_basic: exiting, ret=77
11347 10:03:45.825982 utputs, pipes: 8, outputs: 0
11348 10:03:45.836153 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11350 10:03:45.839414 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1<8>[ 21.793509] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11351 10:03:45.839998 .62-cip9 aarch64)
11352 10:03:45.842288 Opened device: /dev/dri/card0
11353 10:03:45.845604 Starting subtest: clobberred-modifier
11354 10:03:45.855494 Test requirement not met in function igt_require_i915, file ../lib/drmt<14>[ 21.815261] [IGT] kms_addfb_basic: executing
11355 10:03:45.856000 est.c:720:
11356 10:03:45.859002 Test requirement: is_i915_device(fd)
11357 10:03:45.868884 [1mSubtest cl<14>[ 21.824967] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11358 10:03:45.878628 obberred-modifie<14>[ 21.834080] [IGT] kms_addfb_basic: finished subtest invalid-smem-bo-on-discrete, SKIP
11359 10:03:45.882656 r: SKIP (0.000s)[0m
11360 10:03:45.892735 Test requirement not met in function igt_require_i915, file ../lib/drmtest<14>[ 21.851604] [IGT] kms_addfb_basic: exiting, ret=77
11361 10:03:45.893284 .c:720:
11362 10:03:45.895412 Test requirement: is_i915_device(fd)
11363 10:03:45.908767 Test requirement not met in funct<8>[ 21.863521] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11364 10:03:45.909467 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11366 10:03:45.912275 ion igt_require_i915, file ../lib/drmtest.c:720:
11367 10:03:45.915570 Test requirement: is_i915_device(fd)
11368 10:03:45.918771 No KMS driver or no outputs, pipes: 8, outputs: 0
11369 10:03:45.925346 IGT-Version: 1.27.1-g<14>[ 21.886133] [IGT] kms_addfb_basic: executing
11370 10:03:45.932081 621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11371 10:03:45.939065 Opened device: /<14>[ 21.895222] [IGT] kms_addfb_basic: starting subtest legacy-format
11372 10:03:45.939512 dev/dri/card0
11373 10:03:45.945336 Starting subtest: invalid-smem-bo-on-discrete
11374 10:03:45.951820 Test requirement n<14>[ 21.909536] [IGT] kms_addfb_basic: finished subtest legacy-format, SUCCESS
11375 10:03:45.958424 ot met in function igt_require_intel, file ../lib/drmtest.c:715:
11376 10:03:45.965137 Test requirement: is_intel_dev<14>[ 21.925130] [IGT] kms_addfb_basic: exiting, ret=0
11377 10:03:45.968450 ice(fd)
11378 10:03:45.971834 [1mSubtest invalid-smem-bo-on-discrete: SKIP (0.000s)[0m
11379 10:03:45.978821 Test requir<8>[ 21.936522] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11380 10:03:45.979709 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11382 10:03:45.985535 ement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11383 10:03:45.988362 Test requirement: is_i915_device(fd)
11384 10:03:45.998651 Test requirement not met in function igt_require_i<14>[ 21.957386] [IGT] kms_addfb_basic: executing
11385 10:03:46.002260 915, file ../lib/drmtest.c:720:
11386 10:03:46.005688 Test requirement: is_i915_device(fd)
11387 10:03:46.011865 No KMS dr<14>[ 21.969689] [IGT] kms_addfb_basic: starting subtest no-handle
11388 10:03:46.021500 iver or no outpu<14>[ 21.976454] [IGT] kms_addfb_basic: finished subtest no-handle, SUCCESS
11389 10:03:46.021853 ts, pipes: 8, outputs: 0
11390 10:03:46.031747 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-<14>[ 21.990700] [IGT] kms_addfb_basic: exiting, ret=0
11391 10:03:46.034639 cip9 aarch64)
11392 10:03:46.035081 Opened device: /dev/dri/card0
11393 10:03:46.038100 Starting subtest: legacy-format
11394 10:03:46.045209 S<8>[ 22.003185] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11395 10:03:46.045899 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11397 10:03:46.051607 uccessfully fuzzed 10000 {bpp, depth} variations
11398 10:03:46.055112 [1mSubtest legacy-format: SUCCESS (0.006s)[0m
11399 10:03:46.064716 Test requirement not met in function igt_require_i915, file .<14>[ 22.022985] [IGT] kms_addfb_basic: executing
11400 10:03:46.065106 ./lib/drmtest.c:720:
11401 10:03:46.068094 Test requirement: is_i915_device(fd)
11402 10:03:46.078044 Test requirement not<14>[ 22.035561] [IGT] kms_addfb_basic: starting subtest basic
11403 10:03:46.084845 met in function<14>[ 22.041969] [IGT] kms_addfb_basic: finished subtest basic, SUCCESS
11404 10:03:46.088128 igt_require_i915, file ../lib/drmtest.c:720:
11405 10:03:46.098224 Test requirement: is_i915_device(<14>[ 22.055736] [IGT] kms_addfb_basic: exiting, ret=0
11406 10:03:46.098524 fd)
11407 10:03:46.101592 No KMS driver or no outputs, pipes: 8, outputs: 0
11408 10:03:46.111582 IGT-Version: 1.27.1-g621<8>[ 22.068425] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11409 10:03:46.112162 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11411 10:03:46.114613 c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11412 10:03:46.118321 Opened device: /dev/dri/card0
11413 10:03:46.118627 Starting subtest: no-handle
11414 10:03:46.124696 [1mSubtest no-handle: SUCCESS (0.000s)[0m
11415 10:03:46.127968 Test requi<14>[ 22.087822] [IGT] kms_addfb_basic: executing
11416 10:03:46.134847 rement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11417 10:03:46.141803 Test re<14>[ 22.100675] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11418 10:03:46.151735 quirement: is_i9<14>[ 22.107287] [IGT] kms_addfb_basic: finished subtest bad-pitch-0, SUCCESS
11419 10:03:46.152394 15_device(fd)
11420 10:03:46.161535 Test requirement not met in function igt_require_i915, file ../li<14>[ 22.121543] [IGT] kms_addfb_basic: exiting, ret=0
11421 10:03:46.164805 b/drmtest.c:720:
11422 10:03:46.168066 Test requirement: is_i915_device(fd)
11423 10:03:46.178269 No KMS driver or no outp<8>[ 22.133572] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11424 10:03:46.178695 uts, pipes: 8, outputs: 0
11425 10:03:46.179381 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11427 10:03:46.185168 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11428 10:03:46.188408 Opened device: /dev/dri/card0
11429 10:03:46.191457 Starting subtest: basic
11430 10:03:46.194956 [1mSubt<14>[ 22.154402] [IGT] kms_addfb_basic: executing
11431 10:03:46.198252 est basic: SUCCESS (0.000s)[0m
11432 10:03:46.207925 Test requirement not met in function igt_requir<14>[ 22.166771] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11433 10:03:46.218241 e_i915, file ../<14>[ 22.173773] [IGT] kms_addfb_basic: finished subtest bad-pitch-32, SUCCESS
11434 10:03:46.218673 lib/drmtest.c:720:
11435 10:03:46.221327 Test requirement: is_i915_device(fd)
11436 10:03:46.228107 Test requirement not m<14>[ 22.188188] [IGT] kms_addfb_basic: exiting, ret=0
11437 10:03:46.234617 et in function igt_require_i915, file ../lib/drmtest.c:720:
11438 10:03:46.244315 Test requirement: i<8>[ 22.200634] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11439 10:03:46.244600 s_i915_device(fd)
11440 10:03:46.244958 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11442 10:03:46.251029 No KMS driver or no outputs, pipes: 8, outputs: 0
11443 10:03:46.254746 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11444 10:03:46.261106 Opened device: /dev/d<14>[ 22.221055] [IGT] kms_addfb_basic: executing
11445 10:03:46.261292 ri/card0
11446 10:03:46.264817 Starting subtest: bad-pitch-0
11447 10:03:46.275405 [1mSubtest bad-pitch-0: SUCCESS (0.000<14>[ 22.233278] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11448 10:03:46.275836 s)[0m
11449 10:03:46.285001 Test req<14>[ 22.240304] [IGT] kms_addfb_basic: finished subtest bad-pitch-63, SUCCESS
11450 10:03:46.291297 uirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11451 10:03:46.294983 Test <14>[ 22.254693] [IGT] kms_addfb_basic: exiting, ret=0
11452 10:03:46.298028 requirement: is_i915_device(fd)
11453 10:03:46.311393 Test requirement not met in function igt_requir<8>[ 22.267232] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11454 10:03:46.312089 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11456 10:03:46.314493 e_i915, file ../lib/drmtest.c:720:
11457 10:03:46.317951 Test requirement: is_i915_device(fd)
11458 10:03:46.321173 No KMS driver or no outputs, pipes: 8, outputs: 0
11459 10:03:46.327832 IGT-Version: 1.27.1-g621c2d3 (aarch<14>[ 22.287833] [IGT] kms_addfb_basic: executing
11460 10:03:46.331264 64) (Linux: 6.1.62-cip9 aarch64)
11461 10:03:46.334591 Opened device: /dev/dri/card0
11462 10:03:46.341372 Starting subtes<14>[ 22.299759] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11463 10:03:46.344815 t: bad-pitch-32
11464 10:03:46.351039 <14>[ 22.307005] [IGT] kms_addfb_basic: finished subtest bad-pitch-128, SUCCESS
11465 10:03:46.351477
11466 10:03:46.354151 [1mSubtest bad-pitch-32: SUCCESS (0.000s)[0m
11467 10:03:46.364517 Test requirement not met in fun<14>[ 22.321322] [IGT] kms_addfb_basic: exiting, ret=0
11468 10:03:46.367675 ction igt_require_i915, file ../lib/drmtest.c:720:
11469 10:03:46.377825 Test requirement: is_i915_de<8>[ 22.333438] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11470 10:03:46.378258 vice(fd)
11471 10:03:46.378912 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11473 10:03:46.384237 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11474 10:03:46.387681 Test requirement: is_i915_device(fd)
11475 10:03:46.394232 No KMS driver or no outputs, <14>[ 22.355129] [IGT] kms_addfb_basic: executing
11476 10:03:46.397538 pipes: 8, outputs: 0
11477 10:03:46.407354 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9<14>[ 22.366655] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11478 10:03:46.411210 aarch64)
11479 10:03:46.417349 Opene<14>[ 22.373791] [IGT] kms_addfb_basic: finished subtest bad-pitch-256, SUCCESS
11480 10:03:46.420894 d device: /dev/dri/card0
11481 10:03:46.423916 Starting subtest: bad-pitch-63
11482 10:03:46.430633 [1mSubtest bad-pitch-<14>[ 22.388279] [IGT] kms_addfb_basic: exiting, ret=0
11483 10:03:46.431190 63: SUCCESS (0.000s)[0m
11484 10:03:46.444155 Test requirement not met in function igt_require_i915,<8>[ 22.400538] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11485 10:03:46.445036 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11487 10:03:46.447161 file ../lib/drmtest.c:720:
11488 10:03:46.450398 Test requirement: is_i915_device(fd)
11489 10:03:46.457269 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11490 10:03:46.463949 Test requi<14>[ 22.422119] [IGT] kms_addfb_basic: executing
11491 10:03:46.464439 rement: is_i915_device(fd)
11492 10:03:46.470613 No KMS driver or no outputs, pipes: 8, outputs: 0
11493 10:03:46.477108 I<14>[ 22.433415] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11494 10:03:46.483456 GT-Version: 1.27<14>[ 22.440641] [IGT] kms_addfb_basic: finished subtest bad-pitch-1024, SUCCESS
11495 10:03:46.489798 .1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11496 10:03:46.496775 Opened device: /dev/dri/card<14>[ 22.455143] [IGT] kms_addfb_basic: exiting, ret=0
11497 10:03:46.497091 0
11498 10:03:46.500217 Starting subtest: bad-pitch-128
11499 10:03:46.509766 [1mSubtest bad-pitch-128: SUCCESS (0.000s)<8>[ 22.467550] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11500 10:03:46.510074 [0m
11501 10:03:46.510546 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11503 10:03:46.520287 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11504 10:03:46.522969 Test requirement: is_i915_device(fd)
11505 10:03:46.529945 Test requirement not met in functi<14>[ 22.489311] [IGT] kms_addfb_basic: executing
11506 10:03:46.532890 on igt_require_i915, file ../lib/drmtest.c:720:
11507 10:03:46.542830 Test requirement: is_i915_devic<14>[ 22.500452] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11508 10:03:46.543196 e(fd)
11509 10:03:46.553269 No KMS dr<14>[ 22.507664] [IGT] kms_addfb_basic: finished subtest bad-pitch-999, SUCCESS
11510 10:03:46.556578 iver or no outputs, pipes: 8, outputs: 0
11511 10:03:46.562931 IGT-Version: 1.27.1-g621c2d3 (aarch64)<14>[ 22.522057] [IGT] kms_addfb_basic: exiting, ret=0
11512 10:03:46.566464 (Linux: 6.1.62-cip9 aarch64)
11513 10:03:46.569865 Opened device: /dev/dri/card0
11514 10:03:46.576512 Starting subtest: <8>[ 22.534350] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11515 10:03:46.576967 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11517 10:03:46.579377 bad-pitch-256
11518 10:03:46.582679 [1mSubtest bad-pitch-256: SUCCESS (0.000s)[0m
11519 10:03:46.589527 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11520 10:03:46.596174 Test requirem<14>[ 22.555491] [IGT] kms_addfb_basic: executing
11521 10:03:46.599404 ent: is_i915_device(fd)
11522 10:03:46.610105 Test requirement not met in function igt_require_i915, <14>[ 22.567291] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11523 10:03:46.619381 file ../lib/drmt<14>[ 22.574604] [IGT] kms_addfb_basic: finished subtest bad-pitch-65536, SUCCESS
11524 10:03:46.619617 est.c:720:
11525 10:03:46.622892 Test requirement: is_i915_device(fd)
11526 10:03:46.628960 No KMS driver or no outputs, p<14>[ 22.589257] [IGT] kms_addfb_basic: exiting, ret=0
11527 10:03:46.632659 ipes: 8, outputs: 0
11528 10:03:46.645580 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 <8>[ 22.601540] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11529 10:03:46.645766 aarch64)
11530 10:03:46.646064 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11532 10:03:46.648946 Opened device: /dev/dri/card0
11533 10:03:46.652262 Starting subtest: bad-pitch-1024
11534 10:03:46.655884 [1mSubtest bad-pitch-1024: SUCCESS (0.000s)[0m
11535 10:03:46.662297 Test requirement not met in functio<14>[ 22.623156] [IGT] kms_addfb_basic: executing
11536 10:03:46.666045 n igt_require_i915, file ../lib/drmtest.c:720:
11537 10:03:46.669150 Test requirement: is_i915_device(fd)
11538 10:03:46.679131 Test requirement not met i<14>[ 22.636648] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11539 10:03:46.688815 n function igt_r<14>[ 22.645135] [IGT] kms_addfb_basic: finished subtest invalid-get-prop-any, SUCCESS
11540 10:03:46.692200 equire_i915, file ../lib/drmtest.c:720:
11541 10:03:46.698832 Test re<14>[ 22.658362] [IGT] kms_addfb_basic: exiting, ret=0
11542 10:03:46.702321 quirement: is_i915_device(fd)
11543 10:03:46.712433 No KMS driver or no outputs, pipes: 8, outputs: 0<8>[ 22.669772] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11544 10:03:46.712562
11545 10:03:46.712835 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11547 10:03:46.719041 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11548 10:03:46.722396 Opened device: /dev/dri/card0
11549 10:03:46.725779 Starting subtest: bad-pitch-999
11550 10:03:46.732474 [1mSubtest bad-pitch-999<14>[ 22.691453] [IGT] kms_addfb_basic: executing
11551 10:03:46.735840 : SUCCESS (0.000s)[0m
11552 10:03:46.742306 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11553 10:03:46.749038 Test <14>[ 22.705392] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11554 10:03:46.759240 requirement: is_<14>[ 22.713473] [IGT] kms_addfb_basic: finished subtest invalid-get-prop, SUCCESS
11555 10:03:46.759694 i915_device(fd)
11556 10:03:46.765932 Test requirement not met in fun<14>[ 22.726318] [IGT] kms_addfb_basic: exiting, ret=0
11557 10:03:46.772601 ction igt_require_i915, file ../lib/drmtest.c:720:
11558 10:03:46.782187 Test requirement: is_i915_de<8>[ 22.737542] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11559 10:03:46.782616 vice(fd)
11560 10:03:46.783246 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11562 10:03:46.786298 No KMS driver or no outputs, pipes: 8, outputs: 0
11563 10:03:46.792080 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11564 10:03:46.795593 Opened device: /dev/dri/card0
11565 10:03:46.799367 <14>[ 22.759251] [IGT] kms_addfb_basic: executing
11566 10:03:46.799800
11567 10:03:46.802672 Starting subtest: bad-pitch-65536
11568 10:03:46.809243 [1mSubtest bad-pitch-65536: SUCCESS (0.000s)[0m
11569 10:03:46.815952 Test requ<14>[ 22.772879] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11570 10:03:46.825700 irement not met <14>[ 22.780063] [IGT] kms_addfb_basic: finished subtest invalid-set-prop-any, SUCCESS
11571 10:03:46.835837 in function igt_require_i915, file ../lib/drmtes<14>[ 22.793234] [IGT] kms_addfb_basic: exiting, ret=0
11572 10:03:46.836263 t.c:720:
11573 10:03:46.839283 Test requirement: is_i915_device(fd)
11574 10:03:46.848879 Test requirement not met in func<8>[ 22.804645] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11575 10:03:46.849604 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11577 10:03:46.852203 tion igt_require_i915, file ../lib/drmtest.c:720:
11578 10:03:46.855593 Test requirement: is_i915_device(fd)
11579 10:03:46.862328 No KMS driver or no outputs, pipes: 8, outputs: 0
11580 10:03:46.868285 IGT-Version: 1.27.1-<14>[ 22.825937] [IGT] kms_addfb_basic: executing
11581 10:03:46.872055 g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11582 10:03:46.875435 Opened device: /dev/dri/card0
11583 10:03:46.881810 Starting subtest<14>[ 22.840138] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11584 10:03:46.891935 : invalid-get-pr<14>[ 22.847023] [IGT] kms_addfb_basic: finished subtest invalid-set-prop, SUCCESS
11585 10:03:46.892041 op-any
11586 10:03:46.901534 [1mSubtest invalid-get-prop-any: SUCCES<14>[ 22.859952] [IGT] kms_addfb_basic: exiting, ret=0
11587 10:03:46.901629 S (0.000s)[0m
11588 10:03:46.914676 Test requirement not met in function igt_require_i915, file ../l<8>[ 22.871445] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11589 10:03:46.914788 ib/drmtest.c:720:
11590 10:03:46.915098 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11592 10:03:46.918449 Test requirement: is_i915_device(fd)
11593 10:03:46.928274 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11594 10:03:46.931993 Test requirement: is<14>[ 22.892453] [IGT] kms_addfb_basic: executing
11595 10:03:46.935254 _i915_device(fd)
11596 10:03:46.938377 No KMS driver or no outputs, pipes: 8, outputs: 0
11597 10:03:46.951753 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 <14>[ 22.908365] [IGT] kms_addfb_basic: starting subtest master-rmfb
11598 10:03:46.951865 aarch64)
11599 10:03:46.958583 Opened<14>[ 22.915616] [IGT] kms_addfb_basic: finished subtest master-rmfb, SUCCESS
11600 10:03:46.961859 device: /dev/dri/card0
11601 10:03:46.965459 Startin<14>[ 22.926106] [IGT] kms_addfb_basic: exiting, ret=0
11602 10:03:46.968685 g subtest: invalid-get-prop
11603 10:03:46.975445 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
11604 10:03:46.981814 <8>[ 22.937898] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11605 10:03:46.981910
11606 10:03:46.982173 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11608 10:03:46.988535 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11609 10:03:46.991967 Test requirement: is_i915_device(fd)
11610 10:03:46.998781 Test requirement not met in function i<14>[ 22.959284] [IGT] kms_addfb_basic: executing
11611 10:03:47.001550 gt_require_i915, file ../lib/drmtest.c:720:
11612 10:03:47.005241 Test requirement: is_i915_device(fd)
11613 10:03:47.011814 No KMS driver or no outputs, pipes: 8, outputs: 0
11614 10:03:47.018641 IGT-Versio<14>[ 22.976511] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11615 10:03:47.028273 n: 1.27.1-g621c2<14>[ 22.984423] [IGT] kms_addfb_basic: finished subtest addfb25-modifier-no-flag, SUCCESS
11616 10:03:47.035037 d3 (aarch64) (Li<14>[ 22.994109] [IGT] kms_addfb_basic: exiting, ret=0
11617 10:03:47.038363 nux: 6.1.62-cip9 aarch64)
11618 10:03:47.041773 Opened device: /dev/dri/card0
11619 10:03:47.048541 Starti<8>[ 23.005653] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11620 10:03:47.048828 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11622 10:03:47.051483 ng subtest: invalid-set-prop-any
11623 10:03:47.058234 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
11624 10:03:47.065033 Test requirement not met in function igt_require_i915,<14>[ 23.026417] [IGT] kms_addfb_basic: executing
11625 10:03:47.068279 file ../lib/drmtest.c:720:
11626 10:03:47.071737 Test requirement: is_i915_device(fd)
11627 10:03:47.085281 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:<14>[ 23.043488] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11628 10:03:47.085416 720:
11629 10:03:47.088536 Test requirement: is_i915_device(fd)
11630 10:03:47.098047 No KMS driver or no <14>[ 23.056160] [IGT] kms_addfb_basic: finished subtest addfb25-bad-modifier, FAIL
11631 10:03:47.105216 outputs, pipes: <14>[ 23.064425] [IGT] kms_addfb_basic: exiting, ret=98
11632 10:03:47.108057 8, outputs: 0
11633 10:03:47.121462 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch6<8>[ 23.076238] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11634 10:03:47.121557 4)
11635 10:03:47.121800 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11637 10:03:47.124875 Opened device: /dev/dri/card0
11638 10:03:47.124958 Starting subtest: invalid-set-prop
11639 10:03:47.132044 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
11640 10:03:47.138182 Test requirement not met in function <14>[ 23.098238] [IGT] kms_addfb_basic: executing
11641 10:03:47.141493 igt_require_i915, file ../lib/drmtest.c:720:
11642 10:03:47.145050 Test requirement: is_i915_device(fd)
11643 10:03:47.158651 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c<14>[ 23.116368] [IGT] kms_addfb_basic: exiting, ret=77
11644 10:03:47.158740 :720:
11645 10:03:47.161389 Test requirement: is_i915_device(fd)
11646 10:03:47.175006 No KMS driver or no outputs, pipes:<8>[ 23.128678] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11647 10:03:47.175093 8, outputs: 0
11648 10:03:47.175333 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11650 10:03:47.181784 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11651 10:03:47.184988 Opened device: /dev/dri/card0
11652 10:03:47.191185 Starting subtest: master-rmf<14>[ 23.150626] [IGT] kms_addfb_basic: executing
11653 10:03:47.191284 b
11654 10:03:47.194412 [1mSubtest master-rmfb: SUCCESS (0.000s)[0m
11655 10:03:47.201206 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11656 10:03:47.211226 Test requirement: is_i915_d<14>[ 23.168309] [IGT] kms_addfb_basic: exiting, ret=77
11657 10:03:47.211313 evice(fd)
11658 10:03:47.224477 Test requirement not met in function igt_require_i915, file ../lib/dr<8>[ 23.180408] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11659 10:03:47.224563 mtest.c:720:
11660 10:03:47.224802 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11662 10:03:47.228090 Test requirement: is_i915_device(fd)
11663 10:03:47.234600 No KMS driver or no outputs, pipes: 8, outputs: 0
11664 10:03:47.244294 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip<14>[ 23.202231] [IGT] kms_addfb_basic: executing
11665 10:03:47.244378 9 aarch64)
11666 10:03:47.247870 Opened device: /dev/dri/card0
11667 10:03:47.250888 Starting subtest: addfb25-modifier-no-flag
11668 10:03:47.257880 [1mSubtest addfb25-modifier-no-flag: SUCCESS (0.000s)[0m
11669 10:03:47.260585 Test requirem<14>[ 23.220962] [IGT] kms_addfb_basic: exiting, ret=77
11670 10:03:47.267620 ent not met in function igt_require_i915, file ../lib/drmtest.c:720:
11671 10:03:47.277404 Test requi<8>[ 23.232979] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11672 10:03:47.277661 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11674 10:03:47.280802 rement: is_i915_device(fd)
11675 10:03:47.287406 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11676 10:03:47.294229 Test requirement: is_i915_device(<14>[ 23.255260] [IGT] kms_addfb_basic: executing
11677 10:03:47.297273 fd)
11678 10:03:47.300698 No KMS driver or no outputs, pipes: 8, outputs: 0
11679 10:03:47.307682 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11680 10:03:47.314051 Opened device: /dev<14>[ 23.272898] [IGT] kms_addfb_basic: exiting, ret=77
11681 10:03:47.314135 /dri/card0
11682 10:03:47.317240 Starting subtest: addfb25-bad-modifier
11683 10:03:47.327414 (kms_addfb_basic:433) CRITIC<8>[ 23.283863] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11684 10:03:47.327671 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11686 10:03:47.334269 AL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:662:
11687 10:03:47.344034 (kms_addfb_basic:433) CRITICAL: Failed assertion: igt_i<14>[ 23.305113] [IGT] kms_addfb_basic: executing
11688 10:03:47.363789 octl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) <14>[ 23.322431] [IGT] kms_addfb_basic: exiting, ret=77
11689 10:03:47.363882 == -1
11690 10:03:47.367398 (kms_addfb_basic:433) CRITICAL: error: 0 != -1
11691 10:03:47.377656 Stack tra<8>[ 23.333158] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11692 10:03:47.377739 ce:
11693 10:03:47.377977 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11695 10:03:47.380339 #0 ../lib/igt_core.c:1971 __igt_fail_assert()
11696 10:03:47.383627 #1 [<unknown>+0xea4e47e0]
11697 10:03:47.387367 #2 [<unknown>+0xea4e6278]
11698 10:03:47.387447 #3 [<unknown>+0xea4e167c]
11699 10:03:47.390278 #4 [__libc_start_main+0xe8]
11700 10:03:47.394119 #5 [<unknown>+0xea4e16b4]
11701 10:03:47.397288 #6 [<unknown>+0xea4e16b4]
11702 10:03:47.403607 Subtest addfb25-bad-modifi<14>[ 23.363509] [IGT] kms_addfb_basic: executing
11703 10:03:47.403689 er failed.
11704 10:03:47.407453 **** DEBUG ****
11705 10:03:47.414104 (kms_addfb_basic:433) ioctl_wrappers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
11706 10:03:47.423837 (kms_addfb_basic:433) CRITICAL: Test assertion failu<14>[ 23.382239] [IGT] kms_addfb_basic: exiting, ret=77
11707 10:03:47.430487 re function addfb25_tests, file ../tests/kms_addfb_basic.c:662:
11708 10:03:47.440501 (kms_addfb_basic:433) CRITICAL:<8>[ 23.396091] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11709 10:03:47.440755 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11711 10:03:47.457239 Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8))))<14>[ 23.417553] [IGT] kms_addfb_basic: executing
11712 10:03:47.460938 , (&f)) == -1
11713 10:03:47.463990 (kms_addfb_basic:433) CRITICAL: error: 0 != -1
11714 10:03:47.467156 (kms_addfb_basic:433) igt_core-INFO: Stack trace:
11715 10:03:47.477530 (kms_addfb_basic:433) igt_core<14>[ 23.435675] [IGT] kms_addfb_basic: exiting, ret=77
11716 10:03:47.480668 -INFO: #0 ../lib/igt_core.c:1971 __igt_fail_assert()
11717 10:03:47.490465 (kms_addfb_basic:433) ig<8>[ 23.446836] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11718 10:03:47.490723 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11720 10:03:47.493781 t_core-INFO: #1 [<unknown>+0xea4e47e0]
11721 10:03:47.500263 (kms_addfb_basic:433) igt_core-INFO: #2 [<unknown>+0xea4e6278]
11722 10:03:47.507299 (kms_addfb_basic:433) igt_core-INFO:<14>[ 23.467659] [IGT] kms_addfb_basic: executing
11723 10:03:47.510409 #3 [<unknown>+0xea4e167c]
11724 10:03:47.517272 (kms_addfb_basic:433) igt_core-INFO: #4 [__libc_start_main+0xe8]
11725 10:03:47.527118 (kms_addfb_basic:433) igt_core-INFO: #5 [<unknown>+0xea4e16b<14>[ 23.485474] [IGT] kms_addfb_basic: exiting, ret=77
11726 10:03:47.527201 4]
11727 10:03:47.540047 (kms_addfb_basic:433) igt_core-INFO: #6 [<unknown>+0xea4e1<8>[ 23.497509] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11728 10:03:47.540130 6b4]
11729 10:03:47.540195 **** END ****
11730 10:03:47.540428 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11732 10:03:47.547050 [1mSubtest addfb25-bad-modifier: FAIL (0.005s)[0m
11733 10:03:47.553631 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11734 10:03:47.557006 T<14>[ 23.516801] [IGT] kms_addfb_basic: executing
11735 10:03:47.560122 est requirement: is_i915_device(fd)
11736 10:03:47.566702 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11737 10:03:47.577158 Test requirement: is_i91<14>[ 23.535296] [IGT] kms_addfb_basic: exiting, ret=77
11738 10:03:47.577240 5_device(fd)
11739 10:03:47.580341 No KMS driver or no outputs, pipes: 8, outputs: 0
11740 10:03:47.586604 <8>[ 23.546023] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11741 10:03:47.586686
11742 10:03:47.586917 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11744 10:03:47.593349 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11745 10:03:47.596569 Opened device: /dev/dri/card0
11746 10:03:47.606803 Test requirement not met in function igt_re<14>[ 23.565142] [IGT] kms_addfb_basic: executing
11747 10:03:47.609970 quire_i915, file ../lib/drmtest.c:720:
11748 10:03:47.613276 Test requirement: is_i915_device(fd)
11749 10:03:47.616584 [1mSubtest addfb25-x-tiled-mismatch-legacy: SKIP (0.000s)[0m
11750 10:03:47.623301 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11751 10:03:47.626424 Test requirement: is_i915_device(fd)
11752 10:03:47.633183 No KMS driver or no outputs, pipes: 8, outputs: 0
11753 10:03:47.639603 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11754 10:03:47.639685 Opened device: /dev/dri/card0
11755 10:03:47.649604 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11756 10:03:47.652708 Test requirement: is_i915_device(fd)
11757 10:03:47.655949 [1mSubtest addfb25-x-tiled-legacy: SKIP (0.000s)[0m
11758 10:03:47.662701 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11759 10:03:47.665886 Test requirement: is_i915_device(fd)
11760 10:03:47.672582 No KMS driver or no outputs, pipes: 8, outputs: 0
11761 10:03:47.675948 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11762 10:03:47.679159 Opened device: /dev/dri/card0
11763 10:03:47.686185 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11764 10:03:47.689234 Test requirement: is_i915_device(fd)
11765 10:03:47.695874 [1mSubtest addfb25-framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11766 10:03:47.702786 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11767 10:03:47.706031 Test requirement: is_i915_device(fd)
11768 10:03:47.709540 No KMS driver or no outputs, pipes: 8, outputs: 0
11769 10:03:47.716075 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11770 10:03:47.719767 Opened device: /dev/dri/card0
11771 10:03:47.725768 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11772 10:03:47.729151 Test requirement: is_i915_device(fd)
11773 10:03:47.735955 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11774 10:03:47.739158 Test requirement: is_i915_device(fd)
11775 10:03:47.745810 [1mSubtest basic-x-tiled-legacy: SKIP (0.000s)[0m
11776 10:03:47.749406 No KMS driver or no outputs, pipes: 8, outputs: 0
11777 10:03:47.756017 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11778 10:03:47.759505 Opened device: /dev/dri/card0
11779 10:03:47.765819 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11780 10:03:47.769396 Test requirement: is_i915_device(fd)
11781 10:03:47.775865 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11782 10:03:47.779074 Test requirement: is_i915_device(fd)
11783 10:03:47.785909 [1mSubtest framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11784 10:03:47.789048 No KMS driver or no outputs, pipes: 8, outputs: 0
11785 10:03:47.795740 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11786 10:03:47.795823 Opened device: /dev/dri/card0
11787 10:03:47.805955 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11788 10:03:47.808956 Test requirement: is_i915_device(fd)
11789 10:03:47.815891 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11790 10:03:47.819029 Test requirement: is_i915_device(fd)
11791 10:03:47.822803 [1mSubtest tile-pitch-mismatch: SKIP (0.000s)[0m
11792 10:03:47.829123 No KMS driver or no outputs, pipes: 8, outputs: 0
11793 10:03:47.832108 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11794 10:03:47.835722 Opened device: /dev/dri/card0
11795 10:03:47.842461 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11796 10:03:47.845642 Test requirement: is_i915_device(fd)
11797 10:03:47.852085 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11798 10:03:47.855434 Test requirement: is_i915_device(fd)
11799 10:03:47.862195 [1mSubtest basic-y-tiled-legacy: SKIP (0.000s)[0m
11800 10:03:47.865833 No KMS driver or no outputs, pipes: 8, outputs: 0
11801 10:03:47.872573 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11802 10:03:47.875796 Opened device: /dev/dri/card0
11803 10:03:47.882141 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11804 10:03:47.885487 Test requirement: is_i915_device(fd)
11805 10:03:47.892141 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11806 10:03:47.895607 Test requirement: is_i915_device(fd)
11807 10:03:47.898664 No KMS driver or no outputs, pipes: 8, outputs: 0
11808 10:03:47.905168 [1mSubtest size-max: SKIP (0.000s)[0m
11809 10:03:47.908579 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11810 10:03:47.912194 Opened device: /dev/dri/card0
11811 10:03:47.918792 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11812 10:03:47.922353 Test requirement: is_i915_device(fd)
11813 10:03:47.929012 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11814 10:03:47.932331 Test requirement: is_i915_device(fd)
11815 10:03:47.938755 No KMS driver or no outputs, pipes: 8, outputs: 0
11816 10:03:47.941836 [1mSubtest too-wide: SKIP (0.000s)[0m
11817 10:03:47.948907 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11818 10:03:47.949020 Opened device: /dev/dri/card0
11819 10:03:47.955201 Test re<14>[ 23.914734] [IGT] kms_addfb_basic: exiting, ret=77
11820 10:03:47.962077 quirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11821 10:03:47.968469 Test<8>[ 23.927653] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11822 10:03:47.968731 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11824 10:03:47.972197 requirement: is_i915_device(fd)
11825 10:03:47.978398 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11826 10:03:47.981772 Test requirement: is_i915_device(fd)
11827 10:03:47.988613 No KMS driver or no o<14>[ 23.949504] [IGT] kms_addfb_basic: executing
11828 10:03:47.991696 utputs, pipes: 8, outputs: 0
11829 10:03:47.995018 [1mSubtest too-high: SKIP (0.000s)[0m
11830 10:03:48.001800 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11831 10:03:48.008711 Opened device: /dev/<14>[ 23.967086] [IGT] kms_addfb_basic: exiting, ret=77
11832 10:03:48.008815 dri/card0
11833 10:03:48.021939 Test requirement not met in function igt_require_i915, file ../lib/dr<8>[ 23.979342] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11834 10:03:48.022199 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11836 10:03:48.025195 mtest.c:720:
11837 10:03:48.028360 Test requirement: is_i915_device(fd)
11838 10:03:48.035556 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11839 10:03:48.038140 Test requirement: is_i915_device(fd)
11840 10:03:48.041472 No <14>[ 24.002484] [IGT] kms_addfb_basic: executing
11841 10:03:48.048268 KMS driver or no outputs, pipes: 8, outputs: 0
11842 10:03:48.051764 [1mSubtest bo-too-small: SKIP (0.000s)[0m
11843 10:03:48.061577 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)<14>[ 24.020142] [IGT] kms_addfb_basic: exiting, ret=77
11844 10:03:48.061659
11845 10:03:48.064715 Opened device: /dev/dri/card0
11846 10:03:48.074600 Test requirement not met in function igt_requir<8>[ 24.032243] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
11847 10:03:48.074856 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11849 10:03:48.078310 e_i915, file ../lib/drmtest.c:720:
11850 10:03:48.081790 Test requirement: is_i915_device(fd)
11851 10:03:48.091405 Test requirement not met in function igt_require_i915, file ../lib/drm<14>[ 24.052503] [IGT] kms_addfb_basic: executing
11852 10:03:48.094567 test.c:720:
11853 10:03:48.098154 Test requirement: is_i915_device(fd)
11854 10:03:48.102029 No KMS driver or no outputs, pipes: 8, outputs: 0
11855 10:03:48.104474 [1mSubtest small-bo: SKIP (0.000s)[0m
11856 10:03:48.111328 IGT-Version: 1.27<14>[ 24.070110] [IGT] kms_addfb_basic: exiting, ret=77
11857 10:03:48.114703 .1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11858 10:03:48.124266 Opened devic<8>[ 24.081792] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
11859 10:03:48.124521 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11861 10:03:48.127728 e: /dev/dri/card0
11862 10:03:48.134394 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11863 10:03:48.137692 Test requirement: is_i915_device(fd)
11864 10:03:48.141183 Test<14>[ 24.102588] [IGT] kms_addfb_basic: executing
11865 10:03:48.148159 requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11866 10:03:48.150872 Test requirement: is_i915_device(fd)
11867 10:03:48.161618 No KMS driver or no outputs, pipes: 8, outp<14>[ 24.120148] [IGT] kms_addfb_basic: exiting, ret=77
11868 10:03:48.161734 uts: 0
11869 10:03:48.174689 [1mSubtest bo-too-small-due-to-tiling: SKIP (0.000s)[0<8>[ 24.131995] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
11870 10:03:48.174771 m
11871 10:03:48.175008 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11873 10:03:48.181079 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11874 10:03:48.184146 Opened device: /dev/dri/card0
11875 10:03:48.190850 Test requirement not met in function igt_<14>[ 24.152304] [IGT] kms_addfb_basic: executing
11876 10:03:48.194112 require_i915, file ../lib/drmtest.c:720:
11877 10:03:48.197872 Test requirement: is_i915_device(fd)
11878 10:03:48.211012 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720<14>[ 24.169976] [IGT] kms_addfb_basic: exiting, ret=77
11879 10:03:48.211105 :
11880 10:03:48.214080 Test requirement: is_i915_device(fd)
11881 10:03:48.224081 No KMS driver or no out<8>[ 24.181695] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
11882 10:03:48.224336 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
11884 10:03:48.227964 puts, pipes: 8, outputs: 0
11885 10:03:48.230869 [1mSubtest addfb25-y-tiled-legacy: SKIP (0.000s)[0m
11886 10:03:48.240808 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aa<14>[ 24.201119] [IGT] kms_addfb_basic: executing
11887 10:03:48.243910 rch64)
11888 10:03:48.243990 Opened device: /dev/dri/card0
11889 10:03:48.254056 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11890 10:03:48.260581 Test requirement: is_i<14>[ 24.219563] [IGT] kms_addfb_basic: exiting, ret=77
11891 10:03:48.260665 915_device(fd)
11892 10:03:48.273731 Test requirement not met in function igt_require_i915, file ../l<8>[ 24.230385] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
11893 10:03:48.274015 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
11895 10:03:48.277652 ib/drmtest.c:720:
11896 10:03:48.280536 Test requirement: is_i915_device(fd)
11897 10:03:48.283685 No KMS driver or no outputs, pipes: 8, outputs: 0
11898 10:03:48.290805 [1mSubtest addfb25-yf-tiled-legacy:<14>[ 24.252456] [IGT] kms_addfb_basic: executing
11899 10:03:48.293720 SKIP (0.000s)[0m
11900 10:03:48.300711 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11901 10:03:48.303821 Opened device: /dev/dri/card0
11902 10:03:48.310612 Test requirement not met<14>[ 24.269692] [IGT] kms_addfb_basic: exiting, ret=77
11903 10:03:48.313664 in function igt_require_i915, file ../lib/drmtest.c:720:
11904 10:03:48.323588 Test requirement: is_<8>[ 24.280976] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
11905 10:03:48.323842 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
11907 10:03:48.327037 i915_device(fd)
11908 10:03:48.330678 Test requiremen<8>[ 24.290862] <LAVA_SIGNAL_TESTSET STOP>
11909 10:03:48.330903 Received signal: <TESTSET> STOP
11910 10:03:48.330985 Closing test_set kms_addfb_basic
11911 10:03:48.336933 t not met in function igt_require_i915, file ../lib/drmtest.c:720:
11912 10:03:48.340681 Test requirement: is_i915_device(fd)
11913 10:03:48.343799 No KMS driver or no outputs, pipes: 8, outputs: 0
11914 10:03:48.350409 [1mSubtest addfb25-y-tiled-small-legacy: SKIP (0.000s)[0m
11915 10:03:48.357142 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11916 10:03:48.363535 Opened device: /d<8>[ 24.321781] <LAVA_SIGNAL_TESTSET START kms_atomic>
11917 10:03:48.363617 ev/dri/card0
11918 10:03:48.363850 Received signal: <TESTSET> START kms_atomic
11919 10:03:48.363915 Starting test_set kms_atomic
11920 10:03:48.370207 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11921 10:03:48.373688 Test requirement: is_i915_device(fd)
11922 10:03:48.380298 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11923 10:03:48.383527 Test requirement: is_i915_device(fd)
11924 10:03:48.390333 No KMS driver or<14>[ 24.350466] [IGT] kms_atomic: executing
11925 10:03:48.397165 no outputs, pip<14>[ 24.356094] [IGT] kms_atomic: exiting, ret=77
11926 10:03:48.397245 es: 8, outputs: 0
11927 10:03:48.403423 [1mSubtest addfb25-4-tiled: SKIP (0.000s)[0m
11928 10:03:48.410171 IGT-Version: <8>[ 24.367156] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
11929 10:03:48.410423 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
11931 10:03:48.416804 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11932 10:03:48.420287 Opened device: /dev/dri/card0
11933 10:03:48.423589 No KMS driver or no outputs, pipes: 8, outputs: 0
11934 10:03:48.427036 [1mSubtest plane-overlay-legacy: SKIP (0.000s)[0m
11935 10:03:48.433732 <14>[ 24.391756] [IGT] kms_atomic: executing
11936 10:03:48.436771 IGT-Version: 1.2<14>[ 24.397430] [IGT] kms_atomic: exiting, ret=77
11937 10:03:48.443392 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11938 10:03:48.450339 Opened devi<8>[ 24.408788] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
11939 10:03:48.450592 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
11941 10:03:48.453395 ce: /dev/dri/card0
11942 10:03:48.456754 No KMS driver or no outputs, pipes: 8, outputs: 0
11943 10:03:48.463537 [1mSubtest plane-primary-legacy: SKIP (0.000s)[0m
11944 10:03:48.467024 <14>[ 24.428674] [IGT] kms_atomic: executing
11945 10:03:48.473714 IGT-Version: 1.2<14>[ 24.433357] [IGT] kms_atomic: exiting, ret=77
11946 10:03:48.480581 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11947 10:03:48.489852 Opened device: /dev/dri/car<8>[ 24.445718] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
11948 10:03:48.489976 d0
11949 10:03:48.490226 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
11951 10:03:48.493055 No KMS driver or no outputs, pipes: 8, outputs: 0
11952 10:03:48.499864 [1mSubtest plane-primary-overlay-mutable-zpos: SKIP (0.000s)[0m
11953 10:03:48.507266 <14>[ 24.467472] [IGT] kms_atomic: executing
11954 10:03:48.514195 IGT-Version: 1.2<14>[ 24.472143] [IGT] kms_atomic: exiting, ret=77
11955 10:03:48.517429 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11956 10:03:48.527128 Opened device: /dev/dri/car<8>[ 24.483682] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
11957 10:03:48.527210 d0
11958 10:03:48.527445 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
11960 10:03:48.530814 No KMS driver or no outputs, pipes: 8, outputs: 0
11961 10:03:48.537244 [1mSubtest plane-immutable-zpos: SKIP (0.000s)[0m
11962 10:03:48.548025 <14>[ 24.508020] [IGT] kms_atomic: executing
11963 10:03:48.554820 IGT-Version: 1.2<14>[ 24.512615] [IGT] kms_atomic: exiting, ret=77
11964 10:03:48.558081 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11965 10:03:48.564230 Opened devi<8>[ 24.523983] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
11966 10:03:48.564485 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
11968 10:03:48.567543 ce: /dev/dri/card0
11969 10:03:48.570985 No KMS driver or no outputs, pipes: 8, outputs: 0
11970 10:03:48.574293 [1mSubtest test-only: SKIP (0.000s)[0m
11971 10:03:48.585501 <14>[ 24.545818] [IGT] kms_atomic: executing
11972 10:03:48.592292 IGT-Version: 1.2<14>[ 24.550429] [IGT] kms_atomic: exiting, ret=77
11973 10:03:48.595584 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11974 10:03:48.605723 Opened devi<8>[ 24.561686] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
11975 10:03:48.605804 ce: /dev/dri/card0
11976 10:03:48.606039 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
11978 10:03:48.609158 No KMS driver or no outputs, pipes: 8, outputs: 0
11979 10:03:48.615645 [1mSubtest plane-cursor-legacy: SKIP (0.000s)[0m
11980 10:03:48.621963 <14>[ 24.581971] [IGT] kms_atomic: executing
11981 10:03:48.629222 IGT-Version: 1.2<14>[ 24.586565] [IGT] kms_atomic: exiting, ret=77
11982 10:03:48.632057 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11983 10:03:48.642051 Opened device: /dev/dri/car<8>[ 24.598965] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
11984 10:03:48.642133 d0
11985 10:03:48.642366 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
11987 10:03:48.645302 No KMS driver or no outputs, pipes: 8, outputs: 0
11988 10:03:48.651893 [1mSubtest plane-invalid-params: SKIP (0.000s)[0m
11989 10:03:48.661852 <14>[ 24.622089] [IGT] kms_atomic: executing
11990 10:03:48.668917 IGT-Version: 1.2<14>[ 24.626735] [IGT] kms_atomic: exiting, ret=77
11991 10:03:48.671842 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11992 10:03:48.681804 Opened devi<8>[ 24.637947] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
11993 10:03:48.681886 ce: /dev/dri/card0
11994 10:03:48.682126 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
11996 10:03:48.688557 No KMS driver or no outputs, pipes: 8, outputs: 0
11997 10:03:48.691807 [1mSubtest plane-invalid-params-fence: SKIP (0.000s)[0m
11998 10:03:48.698487 <14>[ 24.658204] [IGT] kms_atomic: executing
11999 10:03:48.704916 IGT-Version: 1.2<14>[ 24.662811] [IGT] kms_atomic: exiting, ret=77
12000 10:03:48.708279 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12001 10:03:48.715323 Opened devi<8>[ 24.673832] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
12002 10:03:48.715646 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
12004 10:03:48.718181 ce: /dev/dri/card0
12005 10:03:48.721785 No KMS driver or no outputs, pipes: 8, outputs: 0
12006 10:03:48.728567 [1mSubtest crtc-invalid-params: SKIP (0.000s)[0m
12007 10:03:48.732132 <14>[ 24.694124] [IGT] kms_atomic: executing
12008 10:03:48.738350 IGT-Version: 1.2<14>[ 24.698742] [IGT] kms_atomic: exiting, ret=77
12009 10:03:48.744882 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12010 10:03:48.752578 Opened devi<8>[ 24.709979] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
12011 10:03:48.752835 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
12013 10:03:48.754756 ce: /dev/dri/card0
12014 10:03:48.758318 No KMS driver or no outputs, pipes: 8, outputs: 0
12015 10:03:48.764680 [1mSubtest crtc-invalid-params-fence: SKIP (0.000s)[0m
12016 10:03:48.771531 <14>[ 24.731324] [IGT] kms_atomic: executing
12017 10:03:48.777811 IGT-Version: 1.2<14>[ 24.735924] [IGT] kms_atomic: exiting, ret=77
12018 10:03:48.781266 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12019 10:03:48.791517 Opened device: /dev/dri/car<8>[ 24.748565] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
12020 10:03:48.791620 d0
12021 10:03:48.791862 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
12023 10:03:48.794759 No KMS driver or no outputs, pipes: 8, outputs: 0
12024 10:03:48.801173 [1mSubtest atomic-invalid-params: SKIP (0.000s)[0m
12025 10:03:48.808905 <14>[ 24.768934] [IGT] kms_atomic: executing
12026 10:03:48.815463 IGT-Version: 1.2<14>[ 24.773577] [IGT] kms_atomic: exiting, ret=77
12027 10:03:48.818868 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12028 10:03:48.829034 Opened devi<8>[ 24.784248] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic_plane_damage RESULT=skip>
12029 10:03:48.829118 ce: /dev/dri/card0
12030 10:03:48.829354 Received signal: <TESTCASE> TEST_CASE_ID=atomic_plane_damage RESULT=skip
12032 10:03:48.835277 No KMS drive<8>[ 24.794135] <LAVA_SIGNAL_TESTSET STOP>
12033 10:03:48.835525 Received signal: <TESTSET> STOP
12034 10:03:48.835600 Closing test_set kms_atomic
12035 10:03:48.838617 r or no outputs, pipes: 8, outputs: 0
12036 10:03:48.842073 [1mSubtest atomic_plane_damage: SKIP (0.000s)[0m
12037 10:03:48.854543 <8>[ 24.814560] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
12038 10:03:48.854837 Received signal: <TESTSET> START kms_flip_event_leak
12039 10:03:48.854955 Starting test_set kms_flip_event_leak
12040 10:03:48.872096 <14>[ 24.832168] [IGT] kms_flip_event_leak: executing
12041 10:03:48.878666 IGT-Version: 1.2<14>[ 24.837766] [IGT] kms_flip_event_leak: exiting, ret=77
12042 10:03:48.885465 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12043 10:03:48.891964 Opened devi<8>[ 24.849237] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12044 10:03:48.892101 ce: /dev/dri/card0
12045 10:03:48.892372 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12047 10:03:48.898464 No KMS drive<8>[ 24.857955] <LAVA_SIGNAL_TESTSET STOP>
12048 10:03:48.898750 Received signal: <TESTSET> STOP
12049 10:03:48.898852 Closing test_set kms_flip_event_leak
12050 10:03:48.901740 r or no outputs, pipes: 8, outputs: 0
12051 10:03:48.905177 [1mSubtest basic: SKIP (0.000s)[0m
12052 10:03:48.918352 <8>[ 24.878291] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
12053 10:03:48.918645 Received signal: <TESTSET> START kms_prop_blob
12054 10:03:48.918742 Starting test_set kms_prop_blob
12055 10:03:48.935354 <14>[ 24.895766] [IGT] kms_prop_blob: executing
12056 10:03:48.942190 IGT-Version: 1.2<14>[ 24.900543] [IGT] kms_prop_blob: starting subtest basic
12057 10:03:48.948813 7.1-g621c2d3 (aa<14>[ 24.907410] [IGT] kms_prop_blob: finished subtest basic, SUCCESS
12058 10:03:48.955327 <14>[ 24.915179] [IGT] kms_prop_blob: exiting, ret=0
12059 10:03:48.958747 rch64) (Linux: 6.1.62-cip9 aarch64)
12060 10:03:48.965370 Opened device: /dev/dri/car<8>[ 24.925302] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
12061 10:03:48.965658 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
12063 10:03:48.968781 d0
12064 10:03:48.968892 Starting subtest: basic
12065 10:03:48.971983 [1mSubtest basic: SUCCESS (0.000s)[0m
12066 10:03:48.984082 <14>[ 24.944039] [IGT] kms_prop_blob: executing
12067 10:03:48.990432 IGT-Version: 1.2<14>[ 24.948808] [IGT] kms_prop_blob: starting subtest blob-prop-core
12068 10:03:49.000583 7.1-g621c2d3 (aa<14>[ 24.956443] [IGT] kms_prop_blob: finished subtest blob-prop-core, SUCCESS
12069 10:03:49.007279 rch64) (Linux: 6<14>[ 24.964997] [IGT] kms_prop_blob: exiting, ret=0
12070 10:03:49.007395 .1.62-cip9 aarch64)
12071 10:03:49.010993 Opened device: /dev/dri/card0
12072 10:03:49.017389 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
12074 10:03:49.020547 Starting sub<8>[ 24.976621] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
12075 10:03:49.020622 test: blob-prop-core
12076 10:03:49.023772 [1mSubtest blob-prop-core: SUCCESS (0.000s)[0m
12077 10:03:49.036527 <14>[ 24.996493] [IGT] kms_prop_blob: executing
12078 10:03:49.042762 IGT-Version: 1.2<14>[ 25.001249] [IGT] kms_prop_blob: starting subtest blob-prop-validate
12079 10:03:49.053220 7.1-g621c2d3 (aa<14>[ 25.009341] [IGT] kms_prop_blob: finished subtest blob-prop-validate, SUCCESS
12080 10:03:49.059972 rch64) (Linux: 6<14>[ 25.018154] [IGT] kms_prop_blob: exiting, ret=0
12081 10:03:49.060063 .1.62-cip9 aarch64)
12082 10:03:49.062882 Opened device: /dev/dri/card0
12083 10:03:49.073315 Starting sub<8>[ 25.029723] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
12084 10:03:49.073399 test: blob-prop-validate
12085 10:03:49.073637 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
12087 10:03:49.079840 [1mSubtest blob-prop-validate: SUCCESS (0.000s)[0m
12088 10:03:49.089750 <14>[ 25.049845] [IGT] kms_prop_blob: executing
12089 10:03:49.096482 IGT-Version: 1.2<14>[ 25.054602] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
12090 10:03:49.105864 7.1-g621c2d3 (aa<14>[ 25.062676] [IGT] kms_prop_blob: finished subtest blob-prop-lifetime, SUCCESS
12091 10:03:49.112840 rch64) (Linux: 6<14>[ 25.071541] [IGT] kms_prop_blob: exiting, ret=0
12092 10:03:49.112923 .1.62-cip9 aarch64)
12093 10:03:49.116053 Opened device: /dev/dri/card0
12094 10:03:49.126052 Starting sub<8>[ 25.083089] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
12095 10:03:49.126327 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
12097 10:03:49.129713 test: blob-prop-lifetime
12098 10:03:49.132415 [1mSubtest blob-prop-lifetime: SUCCESS (0.000s)[0m
12099 10:03:49.143070 <14>[ 25.102976] [IGT] kms_prop_blob: executing
12100 10:03:49.149136 IGT-Version: 1.2<14>[ 25.107735] [IGT] kms_prop_blob: starting subtest blob-multiple
12101 10:03:49.159139 7.1-g621c2d3 (aa<14>[ 25.115387] [IGT] kms_prop_blob: finished subtest blob-multiple, SUCCESS
12102 10:03:49.162962 <14>[ 25.123747] [IGT] kms_prop_blob: exiting, ret=0
12103 10:03:49.166238 rch64) (Linux: 6.1.62-cip9 aarch64)
12104 10:03:49.176070 Opened device: /dev/dri/car<8>[ 25.133676] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
12105 10:03:49.176155 d0
12106 10:03:49.176393 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
12108 10:03:49.179221 Starting subtest: blob-multiple
12109 10:03:49.182405 [1mSubtest blob-multiple: SUCCESS (0.000s)[0m
12110 10:03:49.193292 <14>[ 25.153656] [IGT] kms_prop_blob: executing
12111 10:03:49.200275 IGT-Version: 1.2<14>[ 25.158419] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
12112 10:03:49.209997 7.1-g621c2d3 (aa<14>[ 25.166567] [IGT] kms_prop_blob: finished subtest invalid-get-prop-any, SUCCESS
12113 10:03:49.216658 rch64) (Linux: 6<14>[ 25.175644] [IGT] kms_prop_blob: exiting, ret=0
12114 10:03:49.219943 .1.62-cip9 aarch64)
12115 10:03:49.220026 Opened device: /dev/dri/card0
12116 10:03:49.229778 Starting sub<8>[ 25.187172] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
12117 10:03:49.230035 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
12119 10:03:49.233241 test: invalid-get-prop-any
12120 10:03:49.237025 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
12121 10:03:49.247166 <14>[ 25.207609] [IGT] kms_prop_blob: executing
12122 10:03:49.254712 IGT-Version: 1.2<14>[ 25.212377] [IGT] kms_prop_blob: starting subtest invalid-get-prop
12123 10:03:49.263974 7.1-g621c2d3 (aa<14>[ 25.220181] [IGT] kms_prop_blob: finished subtest invalid-get-prop, SUCCESS
12124 10:03:49.270838 rch64) (Linux: 6<14>[ 25.228915] [IGT] kms_prop_blob: exiting, ret=0
12125 10:03:49.270944 .1.62-cip9 aarch64)
12126 10:03:49.274237 Opened device: /dev/dri/card0
12127 10:03:49.283803 Starting sub<8>[ 25.240206] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
12128 10:03:49.283886 test: invalid-get-prop
12129 10:03:49.284125 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
12131 10:03:49.290410 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
12132 10:03:49.300281 <14>[ 25.260464] [IGT] kms_prop_blob: executing
12133 10:03:49.307112 IGT-Version: 1.2<14>[ 25.265235] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
12134 10:03:49.316778 7.1-g621c2d3 (aa<14>[ 25.273376] [IGT] kms_prop_blob: finished subtest invalid-set-prop-any, SUCCESS
12135 10:03:49.323430 rch64) (Linux: 6<14>[ 25.282474] [IGT] kms_prop_blob: exiting, ret=0
12136 10:03:49.326666 .1.62-cip9 aarch64)
12137 10:03:49.326749 Opened device: /dev/dri/card0
12138 10:03:49.336632 Starting sub<8>[ 25.293999] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
12139 10:03:49.336911 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
12141 10:03:49.340296 test: invalid-set-prop-any
12142 10:03:49.343235 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
12143 10:03:49.353948 <14>[ 25.314197] [IGT] kms_prop_blob: executing
12144 10:03:49.360769 IGT-Version: 1.2<14>[ 25.319017] [IGT] kms_prop_blob: starting subtest invalid-set-prop
12145 10:03:49.370514 7.1-g621c2d3 (aa<14>[ 25.326878] [IGT] kms_prop_blob: finished subtest invalid-set-prop, SUCCESS
12146 10:03:49.377451 rch64) (Linux: 6<14>[ 25.335555] [IGT] kms_prop_blob: exiting, ret=0
12147 10:03:49.377533 .1.62-cip9 aarch64)
12148 10:03:49.381269 Opened device: /dev/dri/card0
12149 10:03:49.390503 Starting sub<8>[ 25.347089] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
12150 10:03:49.390585 test: invalid-set-prop
12151 10:03:49.390822 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
12153 10:03:49.397049 [1mSubt<8>[ 25.356256] <LAVA_SIGNAL_TESTSET STOP>
12154 10:03:49.397302 Received signal: <TESTSET> STOP
12155 10:03:49.397371 Closing test_set kms_prop_blob
12156 10:03:49.400602 est invalid-set-prop: SUCCESS (0.000s)[0m
12157 10:03:49.427808 <8>[ 25.388288] <LAVA_SIGNAL_TESTSET START kms_setmode>
12158 10:03:49.428059 Received signal: <TESTSET> START kms_setmode
12159 10:03:49.428126 Starting test_set kms_setmode
12160 10:03:49.452679 <14>[ 25.412650] [IGT] kms_setmode: executing
12161 10:03:49.459453 IGT-Version: 1.2<14>[ 25.417621] [IGT] kms_setmode: starting subtest basic
12162 10:03:49.465697 7.1-g621c2d3 (aa<14>[ 25.424208] [IGT] kms_setmode: finished subtest basic, SKIP
12163 10:03:49.472513 rch64) (Linux: 6<14>[ 25.431512] [IGT] kms_setmode: exiting, ret=77
12164 10:03:49.475947 .1.62-cip9 aarch64)
12165 10:03:49.476048 Opened device: /dev/dri/card0
12166 10:03:49.485773 Starting sub<8>[ 25.443232] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12167 10:03:49.485881 test: basic
12168 10:03:49.486147 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12170 10:03:49.488974 No dynamic tests executed.
12171 10:03:49.492626 [1mSubtest basic: SKIP (0.000s)[0m
12172 10:03:49.502176 <14>[ 25.462469] [IGT] kms_setmode: executing
12173 10:03:49.508993 IGT-Version: 1.2<14>[ 25.467161] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
12174 10:03:49.519164 7.1-g621c2d3 (aa<14>[ 25.475442] [IGT] kms_setmode: finished subtest basic-clone-single-crtc, SKIP
12175 10:03:49.525876 rch64) (Linux: 6<14>[ 25.484280] [IGT] kms_setmode: exiting, ret=77
12176 10:03:49.525958 .1.62-cip9 aarch64)
12177 10:03:49.529150 Opened device: /dev/dri/card0
12178 10:03:49.538812 Starting sub<8>[ 25.494730] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
12179 10:03:49.539075 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
12181 10:03:49.542452 test: basic-clone-single-crtc
12182 10:03:49.545289 No dynamic tests executed.
12183 10:03:49.548813 [1mSubtest basic-clone-single-crtc: SKIP (0.000s)[0m
12184 10:03:49.555667 <14>[ 25.515815] [IGT] kms_setmode: executing
12185 10:03:49.562053 IGT-Version: 1.2<14>[ 25.520443] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
12186 10:03:49.572295 7.1-g621c2d3 (aa<14>[ 25.528902] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc, SKIP
12187 10:03:49.579081 rch64) (Linux: 6<14>[ 25.538035] [IGT] kms_setmode: exiting, ret=77
12188 10:03:49.582086 .1.62-cip9 aarch64)
12189 10:03:49.582166 Opened device: /dev/dri/card0
12190 10:03:49.592331 Starting sub<8>[ 25.549268] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
12191 10:03:49.592585 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
12193 10:03:49.595522 test: invalid-clone-single-crtc
12194 10:03:49.598616 No dynamic tests executed.
12195 10:03:49.602108 [1mSubtest invalid-clone-single-crtc: SKIP (0.000s)[0m
12196 10:03:49.608863 <14>[ 25.569282] [IGT] kms_setmode: executing
12197 10:03:49.615589 IGT-Version: 1.2<14>[ 25.574009] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
12198 10:03:49.625641 7.1-g621c2d3 (aa<14>[ 25.582610] [IGT] kms_setmode: finished subtest invalid-clone-exclusive-crtc, SKIP
12199 10:03:49.632347 <14>[ 25.591881] [IGT] kms_setmode: exiting, ret=77
12200 10:03:49.636082 rch64) (Linux: 6.1.62-cip9 aarch64)
12201 10:03:49.645346 Opened device: /dev/dri/car<8>[ 25.601769] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
12202 10:03:49.645429 d0
12203 10:03:49.645664 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
12205 10:03:49.649733 Starting subtest: invalid-clone-exclusive-crtc
12206 10:03:49.652072 No dynamic tests executed.
12207 10:03:49.659138 [1mSubtest invalid-clone-exclusive-crtc: SKIP (0.000s)[0m
12208 10:03:49.662353 <14>[ 25.622447] [IGT] kms_setmode: executing
12209 10:03:49.669020 IGT-Version: 1.2<14>[ 25.627482] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
12210 10:03:49.678907 7.1-g621c2d3 (aa<14>[ 25.635426] [IGT] kms_setmode: finished subtest clone-exclusive-crtc, SKIP
12211 10:03:49.682000 <14>[ 25.644062] [IGT] kms_setmode: exiting, ret=77
12212 10:03:49.685766 rch64) (Linux: 6.1.62-cip9 aarch64)
12213 10:03:49.695354 Opened device: /dev/dri/car<8>[ 25.654151] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
12214 10:03:49.695689 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
12216 10:03:49.698781 d0
12217 10:03:49.701848 Starting subtest: clone-exclusive-crtc
12218 10:03:49.701929 No dynamic tests executed.
12219 10:03:49.708441 [1mSubtest clone-exclusive-crtc: SKIP (0.000s)[0m
12220 10:03:49.711801 <14>[ 25.673420] [IGT] kms_setmode: executing
12221 10:03:49.722097 IGT-Version: 1.2<14>[ 25.678125] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
12222 10:03:49.732321 7.1-g621c2d3 (aa<14>[ 25.687187] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc-stealing, SKIP
12223 10:03:49.738543 rch64) (Linux: 6<14>[ 25.697063] [IGT] kms_setmode: exiting, ret=77
12224 10:03:49.738625 .1.62-cip9 aarch64)
12225 10:03:49.741913 Opened device: /dev/dri/card0
12226 10:03:49.752270 Starting sub<8>[ 25.708693] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
12227 10:03:49.752524 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12229 10:03:49.758519 test: invalid-clone-single-crtc-<8>[ 25.719268] <LAVA_SIGNAL_TESTSET STOP>
12230 10:03:49.758603 stealing
12231 10:03:49.758838 Received signal: <TESTSET> STOP
12232 10:03:49.758913 Closing test_set kms_setmode
12233 10:03:49.762416 No dynamic tests executed.
12234 10:03:49.768937 [1mSubtest invalid-clone-single-crtc-stealing: SKIP (0.000s)[0m
12235 10:03:49.790052 <8>[ 25.750442] <LAVA_SIGNAL_TESTSET START kms_vblank>
12236 10:03:49.790304 Received signal: <TESTSET> START kms_vblank
12237 10:03:49.790373 Starting test_set kms_vblank
12238 10:03:49.818250 <14>[ 25.778480] [IGT] kms_vblank: executing
12239 10:03:49.825002 IGT-Version: 1.2<14>[ 25.783663] [IGT] kms_vblank: exiting, ret=77
12240 10:03:49.827902 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12241 10:03:49.838199 Opened device: /dev/dri/car<8>[ 25.794812] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
12242 10:03:49.838283 d0
12243 10:03:49.838518 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12245 10:03:49.841730 No KMS driver or no outputs, pipes: 8, outputs: 0
12246 10:03:49.845051 [1mSubtest invalid: SKIP (0.000s)[0m
12247 10:03:49.855044 <14>[ 25.815157] [IGT] kms_vblank: executing
12248 10:03:49.861770 IGT-Version: 1.2<14>[ 25.819871] [IGT] kms_vblank: exiting, ret=77
12249 10:03:49.864677 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12250 10:03:49.874639 Opened device: /dev/dri/car<8>[ 25.831223] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
12251 10:03:49.874724 d0
12252 10:03:49.874963 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12254 10:03:49.877979 No KMS driver or no outputs, pipes: 8, outputs: 0
12255 10:03:49.881292 [1mSubtest crtc-id: SKIP (0.000s)[0m
12256 10:03:49.894066 <14>[ 25.854115] [IGT] kms_vblank: executing
12257 10:03:49.900709 IGT-Version: 1.2<14>[ 25.858987] [IGT] kms_vblank: exiting, ret=77
12258 10:03:49.903860 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12259 10:03:49.914313 Opened device: /dev/dri/car<8>[ 25.870296] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip>
12260 10:03:49.914396 d0
12261 10:03:49.914633 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip
12263 10:03:49.917566 No KMS driver or no outputs, pipes: 8, outputs: 0
12264 10:03:49.923988 [1mSubtest pipe-A-accuracy-idle: SKIP (0.000s)[0m
12265 10:03:49.930895 <14>[ 25.891224] [IGT] kms_vblank: executing
12266 10:03:49.937272 IGT-Version: 1.2<14>[ 25.895986] [IGT] kms_vblank: exiting, ret=77
12267 10:03:49.940567 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12268 10:03:49.950872 Opened device: /dev/dri/car<8>[ 25.907327] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle RESULT=skip>
12269 10:03:49.950969 d0
12270 10:03:49.951204 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle RESULT=skip
12272 10:03:49.954180 No KMS driver or no outputs, pipes: 8, outputs: 0
12273 10:03:49.960774 [1mSubtest pipe-A-query-idle: SKIP (0.000s)[0m
12274 10:03:49.971485 <14>[ 25.931694] [IGT] kms_vblank: executing
12275 10:03:49.978456 IGT-Version: 1.2<14>[ 25.936486] [IGT] kms_vblank: exiting, ret=77
12276 10:03:49.981193 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12277 10:03:49.991428 Opened device: /dev/dri/car<8>[ 25.947815] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip>
12278 10:03:49.991510 d0
12279 10:03:49.991746 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip
12281 10:03:49.997852 No KMS driver or no outputs, pipes: 8, outputs: 0
12282 10:03:50.001096 [1mSubtest pipe-A-query-idle-hang: SKIP (0.000s)[0m
12283 10:03:50.008828 <14>[ 25.968833] [IGT] kms_vblank: executing
12284 10:03:50.014974 IGT-Version: 1.2<14>[ 25.973591] [IGT] kms_vblank: exiting, ret=77
12285 10:03:50.018813 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12286 10:03:50.028331 Opened device: /dev/dri/car<8>[ 25.984900] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked RESULT=skip>
12287 10:03:50.028413 d0
12288 10:03:50.028647 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked RESULT=skip
12290 10:03:50.031783 No KMS driver or no outputs, pipes: 8, outputs: 0
12291 10:03:50.038144 [1mSubtest pipe-A-query-forked: SKIP (0.000s)[0m
12292 10:03:50.046170 <14>[ 26.006508] [IGT] kms_vblank: executing
12293 10:03:50.052853 IGT-Version: 1.2<14>[ 26.011236] [IGT] kms_vblank: exiting, ret=77
12294 10:03:50.056417 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12295 10:03:50.066494 Opened devi<8>[ 26.022439] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip>
12296 10:03:50.066577 ce: /dev/dri/card0
12297 10:03:50.066813 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip
12299 10:03:50.072610 No KMS driver or no outputs, pipes: 8, outputs: 0
12300 10:03:50.075822 [1mSubtest pipe-A-query-forked-hang: SKIP (0.000s)[0m
12301 10:03:50.085717 <14>[ 26.045764] [IGT] kms_vblank: executing
12302 10:03:50.092528 IGT-Version: 1.2<14>[ 26.050514] [IGT] kms_vblank: exiting, ret=77
12303 10:03:50.095924 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12304 10:03:50.102197 Opened devi<8>[ 26.061355] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy RESULT=skip>
12305 10:03:50.102449 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy RESULT=skip
12307 10:03:50.105396 ce: /dev/dri/card0
12308 10:03:50.108912 No KMS driver or no outputs, pipes: 8, outputs: 0
12309 10:03:50.115564 [1mSubtest pipe-A-query-busy: SKIP (0.000s)[0m
12310 10:03:50.118968 <14>[ 26.080778] [IGT] kms_vblank: executing
12311 10:03:50.125367 IGT-Version: 1.2<14>[ 26.085573] [IGT] kms_vblank: exiting, ret=77
12312 10:03:50.132148 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12313 10:03:50.132230 Opened device: /dev/dri/card0
12314 10:03:50.142144 No KMS drive<8>[ 26.098246] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip>
12315 10:03:50.142397 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip
12317 10:03:50.145561 r or no outputs, pipes: 8, outputs: 0
12318 10:03:50.148809 [1mSubtest pipe-A-query-busy-hang: SKIP (0.000s)[0m
12319 10:03:50.159774 <14>[ 26.119794] [IGT] kms_vblank: executing
12320 10:03:50.166429 IGT-Version: 1.2<14>[ 26.124635] [IGT] kms_vblank: exiting, ret=77
12321 10:03:50.169649 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12322 10:03:50.179405 Opened device: /dev/dri/car<8>[ 26.135977] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip>
12323 10:03:50.179488 d0
12324 10:03:50.179723 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip
12326 10:03:50.186512 No KMS driver or no outputs, pipes: 8, outputs: 0
12327 10:03:50.190023 [1mSubtest pipe-A-query-forked-busy: SKIP (0.000s)[0m
12328 10:03:50.196840 <14>[ 26.157389] [IGT] kms_vblank: executing
12329 10:03:50.203732 IGT-Version: 1.2<14>[ 26.162274] [IGT] kms_vblank: exiting, ret=77
12330 10:03:50.207104 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12331 10:03:50.217025 Opened devi<8>[ 26.173243] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip>
12332 10:03:50.217105 ce: /dev/dri/card0
12333 10:03:50.217338 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip
12335 10:03:50.223565 No KMS driver or no outputs, pipes: 8, outputs: 0
12336 10:03:50.227229 [1mSubtest pipe-A-query-forked-busy-hang: SKIP (0.000s)[0m
12337 10:03:50.233789 <14>[ 26.193518] [IGT] kms_vblank: executing
12338 10:03:50.236903 IGT-Version: 1.2<14>[ 26.198327] [IGT] kms_vblank: exiting, ret=77
12339 10:03:50.244226 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12340 10:03:50.250528 Opened devi<8>[ 26.209382] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle RESULT=skip>
12341 10:03:50.250780 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle RESULT=skip
12343 10:03:50.253767 ce: /dev/dri/card0
12344 10:03:50.256659 No KMS driver or no outputs, pipes: 8, outputs: 0
12345 10:03:50.263382 [1mSubtest pipe-A-wait-idle: SKIP (0.000s)[0m
12346 10:03:50.266617 <14>[ 26.228981] [IGT] kms_vblank: executing
12347 10:03:50.274008 IGT-Version: 1.2<14>[ 26.233715] [IGT] kms_vblank: exiting, ret=77
12348 10:03:50.280264 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12349 10:03:50.280345 Opened device: /dev/dri/card0
12350 10:03:50.290071 No KMS drive<8>[ 26.246482] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip>
12351 10:03:50.290323 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip
12353 10:03:50.293679 r or no outputs, pipes: 8, outputs: 0
12354 10:03:50.296608 [1mSubtest pipe-A-wait-idle-hang: SKIP (0.000s)[0m
12355 10:03:50.307298 <14>[ 26.267489] [IGT] kms_vblank: executing
12356 10:03:50.313610 IGT-Version: 1.2<14>[ 26.272208] [IGT] kms_vblank: exiting, ret=77
12357 10:03:50.317097 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12358 10:03:50.327012 Opened devi<8>[ 26.283458] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked RESULT=skip>
12359 10:03:50.327094 ce: /dev/dri/card0
12360 10:03:50.327329 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked RESULT=skip
12362 10:03:50.330522 No KMS driver or no outputs, pipes: 8, outputs: 0
12363 10:03:50.337065 [1mSubtest pipe-A-wait-forked: SKIP (0.000s)[0m
12364 10:03:50.343802 <14>[ 26.303523] [IGT] kms_vblank: executing
12365 10:03:50.347107 IGT-Version: 1.2<14>[ 26.308335] [IGT] kms_vblank: exiting, ret=77
12366 10:03:50.353999 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12367 10:03:50.356871 Opened device: /dev/dri/card0
12368 10:03:50.363708 No KMS drive<8>[ 26.321679] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip>
12369 10:03:50.363962 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip
12371 10:03:50.367140 r or no outputs, pipes: 8, outputs: 0
12372 10:03:50.373759 [1mSubtest pipe-A-wait-forked-hang: SKIP (0.000s)[0m
12373 10:03:50.383177 <14>[ 26.343634] [IGT] kms_vblank: executing
12374 10:03:50.390063 IGT-Version: 1.2<14>[ 26.348409] [IGT] kms_vblank: exiting, ret=77
12375 10:03:50.392976 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12376 10:03:50.399867 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy RESULT=skip
12378 10:03:50.402985 Opened devi<8>[ 26.359489] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy RESULT=skip>
12379 10:03:50.403067 ce: /dev/dri/card0
12380 10:03:50.406202 No KMS driver or no outputs, pipes: 8, outputs: 0
12381 10:03:50.413344 [1mSubtest pipe-A-wait-busy: SKIP (0.000s)[0m
12382 10:03:50.419919 <14>[ 26.379733] [IGT] kms_vblank: executing
12383 10:03:50.423121 IGT-Version: 1.2<14>[ 26.384487] [IGT] kms_vblank: exiting, ret=77
12384 10:03:50.430070 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12385 10:03:50.439662 Opened device: /dev/dri/car<8>[ 26.396312] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip>
12386 10:03:50.439745 d0
12387 10:03:50.439979 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip
12389 10:03:50.443027 No KMS driver or no outputs, pipes: 8, outputs: 0
12390 10:03:50.449818 [1mSubtest pipe-A-wait-busy-hang: SKIP (0.000s)[0m
12391 10:03:50.457617 <14>[ 26.418041] [IGT] kms_vblank: executing
12392 10:03:50.464495 IGT-Version: 1.2<14>[ 26.422773] [IGT] kms_vblank: exiting, ret=77
12393 10:03:50.467521 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12394 10:03:50.477774 Opened device: /dev/dri/car<8>[ 26.435057] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip>
12395 10:03:50.477857 d0
12396 10:03:50.478091 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip
12398 10:03:50.483944 No KMS driver or no outputs, pipes: 8, outputs: 0
12399 10:03:50.487338 [1mSubtest pipe-A-wait-forked-busy: SKIP (0.000s)[0m
12400 10:03:50.495622 <14>[ 26.455866] [IGT] kms_vblank: executing
12401 10:03:50.502214 IGT-Version: 1.2<14>[ 26.460617] [IGT] kms_vblank: exiting, ret=77
12402 10:03:50.505314 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12403 10:03:50.515342 Opened device: /dev/dri/car<8>[ 26.471906] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip>
12404 10:03:50.515425 d0
12405 10:03:50.515660 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip
12407 10:03:50.522616 No KMS driver or no outputs, pipes: 8, outputs: 0
12408 10:03:50.525560 [1mSubtest pipe-A-wait-forked-busy-hang: SKIP (0.000s)[0m
12409 10:03:50.535450 <14>[ 26.495908] [IGT] kms_vblank: executing
12410 10:03:50.542240 IGT-Version: 1.2<14>[ 26.500655] [IGT] kms_vblank: exiting, ret=77
12411 10:03:50.545569 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12412 10:03:50.555629 Opened device: /dev/dri/car<8>[ 26.511927] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip>
12413 10:03:50.555712 d0
12414 10:03:50.555946 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip
12416 10:03:50.562064 No KMS driver or no outputs, pipes: 8, outputs: 0
12417 10:03:50.565645 [1mSubtest pipe-A-ts-continuation-idle: SKIP (0.000s)[0m
12418 10:03:50.573361 <14>[ 26.533653] [IGT] kms_vblank: executing
12419 10:03:50.579867 IGT-Version: 1.2<14>[ 26.538459] [IGT] kms_vblank: exiting, ret=77
12420 10:03:50.583288 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12421 10:03:50.586466 Opened device: /dev/dri/card0
12422 10:03:50.596811 No KMS drive<8>[ 26.551084] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip>
12423 10:03:50.597066 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip
12425 10:03:50.599595 r or no outputs, pipes: 8, outputs: 0
12426 10:03:50.606173 [1mSubtest pipe-A-ts-continuation-idle-hang: SKIP (0.000s)[0m
12427 10:03:50.616375 <14>[ 26.576836] [IGT] kms_vblank: executing
12428 10:03:50.623378 IGT-Version: 1.2<14>[ 26.581587] [IGT] kms_vblank: exiting, ret=77
12429 10:03:50.626801 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12430 10:03:50.636435 Opened device: /dev/dri/car<8>[ 26.592858] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip>
12431 10:03:50.636539 d0
12432 10:03:50.636805 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip
12434 10:03:50.642959 No KMS driver or no outputs, pipes: 8, outputs: 0
12435 10:03:50.646367 [1mSubtest pipe-A-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12436 10:03:50.654217 <14>[ 26.614642] [IGT] kms_vblank: executing
12437 10:03:50.661014 IGT-Version: 1.2<14>[ 26.619418] [IGT] kms_vblank: exiting, ret=77
12438 10:03:50.663977 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12439 10:03:50.674010 Opened devi<8>[ 26.630486] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip>
12440 10:03:50.674267 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip
12442 10:03:50.677282 ce: /dev/dri/card0
12443 10:03:50.681019 No KMS driver or no outputs, pipes: 8, outputs: 0
12444 10:03:50.687304 [1mSubtest pipe-A-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12445 10:03:50.690731 <14>[ 26.651924] [IGT] kms_vblank: executing
12446 10:03:50.697419 IGT-Version: 1.2<14>[ 26.656718] [IGT] kms_vblank: exiting, ret=77
12447 10:03:50.700925 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12448 10:03:50.703805 Opened device: /dev/dri/card0
12449 10:03:50.714058 No KMS drive<8>[ 26.669355] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip>
12450 10:03:50.714310 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip
12452 10:03:50.717140 r or no outputs, pipes: 8, outputs: 0
12453 10:03:50.723500 [1mSubtest pipe-A-ts-continuation-suspend: SKIP (0.000s)[0m
12454 10:03:50.731268 <14>[ 26.691682] [IGT] kms_vblank: executing
12455 10:03:50.738094 IGT-Version: 1.2<14>[ 26.696447] [IGT] kms_vblank: exiting, ret=77
12456 10:03:50.741016 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12457 10:03:50.751061 Opened devi<8>[ 26.707618] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip>
12458 10:03:50.751144 ce: /dev/dri/card0
12459 10:03:50.751381 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip
12461 10:03:50.757787 No KMS driver or no outputs, pipes: 8, outputs: 0
12462 10:03:50.761447 [1mSubtest pipe-A-ts-continuation-modeset: SKIP (0.000s)[0m
12463 10:03:50.771556 <14>[ 26.731785] [IGT] kms_vblank: executing
12464 10:03:50.777983 IGT-Version: 1.2<14>[ 26.736525] [IGT] kms_vblank: exiting, ret=77
12465 10:03:50.781450 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12466 10:03:50.791325 Opened device: /dev/dri/car<8>[ 26.748685] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip>
12467 10:03:50.791579 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip
12469 10:03:50.794672 d0
12470 10:03:50.798338 No KMS driver or no outputs, pipes: 8, outputs: 0
12471 10:03:50.804420 [1mSubtest pipe-A-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12472 10:03:50.807636 <14>[ 26.770487] [IGT] kms_vblank: executing
12473 10:03:50.814516 IGT-Version: 1.2<14>[ 26.775288] [IGT] kms_vblank: exiting, ret=77
12474 10:03:50.821001 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12475 10:03:50.830956 Opened devi<8>[ 26.786282] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip>
12476 10:03:50.831039 ce: /dev/dri/card0
12477 10:03:50.831275 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip
12479 10:03:50.837754 No KMS driver or no outputs, pipes: 8, outputs: 0
12480 10:03:50.841037 [1mSubtest pipe-A-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12481 10:03:50.849623 <14>[ 26.810314] [IGT] kms_vblank: executing
12482 10:03:50.857014 IGT-Version: 1.2<14>[ 26.815067] [IGT] kms_vblank: exiting, ret=77
12483 10:03:50.860222 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12484 10:03:50.870205 Opened devi<8>[ 26.825978] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip>
12485 10:03:50.870288 ce: /dev/dri/card0
12486 10:03:50.870523 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip
12488 10:03:50.873367 No KMS driver or no outputs, pipes: 8, outputs: 0
12489 10:03:50.879648 [1mSubtest pipe-B-accuracy-idle: SKIP (0.000s)[0m
12490 10:03:50.888840 <14>[ 26.849167] [IGT] kms_vblank: executing
12491 10:03:50.895255 IGT-Version: 1.2<14>[ 26.853923] [IGT] kms_vblank: exiting, ret=77
12492 10:03:50.898642 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12493 10:03:50.908788 Opened devi<8>[ 26.865016] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle RESULT=skip>
12494 10:03:50.908902 ce: /dev/dri/card0
12495 10:03:50.909143 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle RESULT=skip
12497 10:03:50.912037 No KMS driver or no outputs, pipes: 8, outputs: 0
12498 10:03:50.918641 [1mSubtest pipe-B-query-idle: SKIP (0.000s)[0m
12499 10:03:50.927009 <14>[ 26.887006] [IGT] kms_vblank: executing
12500 10:03:50.933589 IGT-Version: 1.2<14>[ 26.891827] [IGT] kms_vblank: exiting, ret=77
12501 10:03:50.936697 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12502 10:03:50.946848 Opened devi<8>[ 26.902968] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip>
12503 10:03:50.947011 ce: /dev/dri/card0
12504 10:03:50.947275 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip
12506 10:03:50.953082 No KMS driver or no outputs, pipes: 8, outputs: 0
12507 10:03:50.955970 [1mSubtest pipe-B-query-idle-hang: SKIP (0.000s)[0m
12508 10:03:50.964452 <14>[ 26.924845] [IGT] kms_vblank: executing
12509 10:03:50.970813 IGT-Version: 1.2<14>[ 26.929602] [IGT] kms_vblank: exiting, ret=77
12510 10:03:50.974306 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12511 10:03:50.984166 Opened device: /dev/dri/car<8>[ 26.940893] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked RESULT=skip>
12512 10:03:50.984250 d0
12513 10:03:50.984486 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked RESULT=skip
12515 10:03:50.987954 No KMS driver or no outputs, pipes: 8, outputs: 0
12516 10:03:50.994387 [1mSubtest pipe-B-query-forked: SKIP (0.000s)[0m
12517 10:03:51.001770 <14>[ 26.962181] [IGT] kms_vblank: executing
12518 10:03:51.008420 IGT-Version: 1.2<14>[ 26.966973] [IGT] kms_vblank: exiting, ret=77
12519 10:03:51.012032 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12520 10:03:51.021820 Opened device: /dev/dri/car<8>[ 26.978217] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip>
12521 10:03:51.021906 d0
12522 10:03:51.022141 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip
12524 10:03:51.028358 No KMS driver or no outputs, pipes: 8, outputs: 0
12525 10:03:51.031813 [1mSubtest pipe-B-query-forked-hang: SKIP (0.000s)[0m
12526 10:03:51.039499 <14>[ 26.999949] [IGT] kms_vblank: executing
12527 10:03:51.046220 IGT-Version: 1.2<14>[ 27.004725] [IGT] kms_vblank: exiting, ret=77
12528 10:03:51.049274 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12529 10:03:51.059572 Opened device: /dev/dri/car<8>[ 27.016931] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy RESULT=skip>
12530 10:03:51.059658 d0
12531 10:03:51.059894 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy RESULT=skip
12533 10:03:51.063005 No KMS driver or no outputs, pipes: 8, outputs: 0
12534 10:03:51.069198 [1mSubtest pipe-B-query-busy: SKIP (0.000s)[0m
12535 10:03:51.076534 <14>[ 27.036872] [IGT] kms_vblank: executing
12536 10:03:51.083307 IGT-Version: 1.2<14>[ 27.041610] [IGT] kms_vblank: exiting, ret=77
12537 10:03:51.086272 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12538 10:03:51.096111 Opened device: /dev/dri/car<8>[ 27.052885] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip>
12539 10:03:51.096195 d0
12540 10:03:51.096431 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip
12542 10:03:51.102609 No KMS driver or no outputs, pipes: 8, outputs: 0
12543 10:03:51.106204 [1mSubtest pipe-B-query-busy-hang: SKIP (0.000s)[0m
12544 10:03:51.116057 <14>[ 27.076792] [IGT] kms_vblank: executing
12545 10:03:51.122994 IGT-Version: 1.2<14>[ 27.081568] [IGT] kms_vblank: exiting, ret=77
12546 10:03:51.126007 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12547 10:03:51.136112 Opened device: /dev/dri/car<8>[ 27.093597] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip>
12548 10:03:51.136196 d0
12549 10:03:51.136474 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip
12551 10:03:51.142653 No KMS driver or no outputs, pipes: 8, outputs: 0
12552 10:03:51.145939 [1mSubtest pipe-B-query-forked-busy: SKIP (0.000s)[0m
12553 10:03:51.153838 <14>[ 27.114539] [IGT] kms_vblank: executing
12554 10:03:51.160609 IGT-Version: 1.2<14>[ 27.119292] [IGT] kms_vblank: exiting, ret=77
12555 10:03:51.164267 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12556 10:03:51.174184 Opened device: /dev/dri/car<8>[ 27.131354] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip>
12557 10:03:51.174266 d0
12558 10:03:51.174505 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip
12560 10:03:51.180503 No KMS driver or no outputs, pipes: 8, outputs: 0
12561 10:03:51.184411 [1mSubtest pipe-B-query-forked-busy-hang: SKIP (0.000s)[0m
12562 10:03:51.192177 <14>[ 27.152603] [IGT] kms_vblank: executing
12563 10:03:51.199089 IGT-Version: 1.2<14>[ 27.157343] [IGT] kms_vblank: exiting, ret=77
12564 10:03:51.201932 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12565 10:03:51.208936 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle RESULT=skip
12567 10:03:51.211865 Opened devi<8>[ 27.168312] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle RESULT=skip>
12568 10:03:51.211969 ce: /dev/dri/card0
12569 10:03:51.215459 No KMS driver or no outputs, pipes: 8, outputs: 0
12570 10:03:51.222079 [1mSubtest pipe-B-wait-idle: SKIP (0.000s)[0m
12571 10:03:51.225028 <14>[ 27.188154] [IGT] kms_vblank: executing
12572 10:03:51.232069 IGT-Version: 1.2<14>[ 27.192927] [IGT] kms_vblank: exiting, ret=77
12573 10:03:51.239025 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12574 10:03:51.245362 Opened devi<8>[ 27.204055] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip>
12575 10:03:51.245618 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip
12577 10:03:51.248523 ce: /dev/dri/card0
12578 10:03:51.252124 No KMS driver or no outputs, pipes: 8, outputs: 0
12579 10:03:51.258807 [1mSubtest pipe-B-wait-idle-hang: SKIP (0.000s)[0m
12580 10:03:51.262017 <14>[ 27.224246] [IGT] kms_vblank: executing
12581 10:03:51.268897 IGT-Version: 1.2<14>[ 27.229016] [IGT] kms_vblank: exiting, ret=77
12582 10:03:51.275486 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12583 10:03:51.281794 Opened devi<8>[ 27.240068] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked RESULT=skip>
12584 10:03:51.282048 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked RESULT=skip
12586 10:03:51.285104 ce: /dev/dri/card0
12587 10:03:51.288389 No KMS driver or no outputs, pipes: 8, outputs: 0
12588 10:03:51.291903 [1mSubtest pipe-B-wait-forked: SKIP (0.000s)[0m
12589 10:03:51.299554 <14>[ 27.259978] [IGT] kms_vblank: executing
12590 10:03:51.306259 IGT-Version: 1.2<14>[ 27.264720] [IGT] kms_vblank: exiting, ret=77
12591 10:03:51.308984 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12592 10:03:51.319266 Opened device: /dev/dri/car<8>[ 27.276069] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip>
12593 10:03:51.319351 d0
12594 10:03:51.319588 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip
12596 10:03:51.326051 No KMS driver or no outputs, pipes: 8, outputs: 0
12597 10:03:51.329503 [1mSubtest pipe-B-wait-forked-hang: SKIP (0.000s)[0m
12598 10:03:51.346542 <14>[ 27.307278] [IGT] kms_vblank: executing
12599 10:03:51.353319 IGT-Version: 1.2<14>[ 27.312452] [IGT] kms_vblank: exiting, ret=77
12600 10:03:51.356764 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12601 10:03:51.366803 Opened device: /dev/dri/car<8>[ 27.323546] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy RESULT=skip>
12602 10:03:51.366894 d0
12603 10:03:51.367132 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy RESULT=skip
12605 10:03:51.369649 No KMS driver or no outputs, pipes: 8, outputs: 0
12606 10:03:51.376514 [1mSubtest pipe-B-wait-busy: SKIP (0.000s)[0m
12607 10:03:51.384911 <14>[ 27.345188] [IGT] kms_vblank: executing
12608 10:03:51.391355 IGT-Version: 1.2<14>[ 27.350011] [IGT] kms_vblank: exiting, ret=77
12609 10:03:51.394280 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12610 10:03:51.404332 Opened device: /dev/dri/car<8>[ 27.362161] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip>
12611 10:03:51.404415 d0
12612 10:03:51.404651 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip
12614 10:03:51.411207 No KMS driver or no outputs, pipes: 8, outputs: 0
12615 10:03:51.414531 [1mSubtest pipe-B-wait-busy-hang: SKIP (0.000s)[0m
12616 10:03:51.422095 <14>[ 27.382578] [IGT] kms_vblank: executing
12617 10:03:51.428888 IGT-Version: 1.2<14>[ 27.387321] [IGT] kms_vblank: exiting, ret=77
12618 10:03:51.431730 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12619 10:03:51.441844 Opened devi<8>[ 27.398402] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip>
12620 10:03:51.441927 ce: /dev/dri/card0
12621 10:03:51.442163 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip
12623 10:03:51.448382 No KMS driver or no outputs, pipes: 8, outputs: 0
12624 10:03:51.451766 [1mSubtest pipe-B-wait-forked-busy: SKIP (0.000s)[0m
12625 10:03:51.460926 <14>[ 27.421464] [IGT] kms_vblank: executing
12626 10:03:51.467458 IGT-Version: 1.2<14>[ 27.426317] [IGT] kms_vblank: exiting, ret=77
12627 10:03:51.470907 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12628 10:03:51.481022 Opened devi<8>[ 27.437226] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip>
12629 10:03:51.481105 ce: /dev/dri/card0
12630 10:03:51.481340 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip
12632 10:03:51.487711 No KMS driver or no outputs, pipes: 8, outputs: 0
12633 10:03:51.490603 [1mSubtest pipe-B-wait-forked-busy-hang: SKIP (0.000s)[0m
12634 10:03:51.498042 <14>[ 27.458151] [IGT] kms_vblank: executing
12635 10:03:51.504578 IGT-Version: 1.2<14>[ 27.462893] [IGT] kms_vblank: exiting, ret=77
12636 10:03:51.507515 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12637 10:03:51.517797 Opened device: /dev/dri/car<8>[ 27.474141] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip>
12638 10:03:51.517881 d0
12639 10:03:51.518116 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip
12641 10:03:51.524174 No KMS driver or no outputs, pipes: 8, outputs: 0
12642 10:03:51.527341 [1mSubtest pipe-B-ts-continuation-idle: SKIP (0.000s)[0m
12643 10:03:51.535170 <14>[ 27.495859] [IGT] kms_vblank: executing
12644 10:03:51.541913 IGT-Version: 1.2<14>[ 27.500618] [IGT] kms_vblank: exiting, ret=77
12645 10:03:51.545173 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12646 10:03:51.555461 Opened device: /dev/dri/car<8>[ 27.512002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip>
12647 10:03:51.555544 d0
12648 10:03:51.555780 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip
12650 10:03:51.561851 No KMS driver or no outputs, pipes: 8, outputs: 0
12651 10:03:51.565385 [1mSubtest pipe-B-ts-continuation-idle-hang: SKIP (0.000s)[0m
12652 10:03:51.576083 <14>[ 27.536678] [IGT] kms_vblank: executing
12653 10:03:51.583280 IGT-Version: 1.2<14>[ 27.541412] [IGT] kms_vblank: exiting, ret=77
12654 10:03:51.586106 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12655 10:03:51.596262 Opened devi<8>[ 27.552626] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip>
12656 10:03:51.596345 ce: /dev/dri/card0
12657 10:03:51.596581 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip
12659 10:03:51.603153 No KMS driver or no outputs, pipes: 8, outputs: 0
12660 10:03:51.605817 [1mSubtest pipe-B-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12661 10:03:51.622834 <14>[ 27.583194] [IGT] kms_vblank: executing
12662 10:03:51.629392 IGT-Version: 1.2<14>[ 27.588628] [IGT] kms_vblank: exiting, ret=77
12663 10:03:51.632741 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12664 10:03:51.642674 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip
12666 10:03:51.646074 Opened device: /dev/dri/car<8>[ 27.599866] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip>
12667 10:03:51.646158 d0
12668 10:03:51.649085 No KMS driver or no outputs, pipes: 8, outputs: 0
12669 10:03:51.656345 [1mSubtest pipe-B-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12670 10:03:51.663511 <14>[ 27.623913] [IGT] kms_vblank: executing
12671 10:03:51.669940 IGT-Version: 1.2<14>[ 27.628688] [IGT] kms_vblank: exiting, ret=77
12672 10:03:51.673161 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12673 10:03:51.683141 Opened device: /dev/dri/car<8>[ 27.641030] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip>
12674 10:03:51.683224 d0
12675 10:03:51.683460 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip
12677 10:03:51.689993 No KMS driver or no outputs, pipes: 8, outputs: 0
12678 10:03:51.693333 [1mSubtest pipe-B-ts-continuation-suspend: SKIP (0.000s)[0m
12679 10:03:51.702047 <14>[ 27.662201] [IGT] kms_vblank: executing
12680 10:03:51.708089 IGT-Version: 1.2<14>[ 27.666955] [IGT] kms_vblank: exiting, ret=77
12681 10:03:51.711596 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12682 10:03:51.722079 Opened device: /dev/dri/car<8>[ 27.678200] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip>
12683 10:03:51.722162 d0
12684 10:03:51.722396 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip
12686 10:03:51.728192 No KMS driver or no outputs, pipes: 8, outputs: 0
12687 10:03:51.731326 [1mSubtest pipe-B-ts-continuation-modeset: SKIP (0.000s)[0m
12688 10:03:51.740943 <14>[ 27.701664] [IGT] kms_vblank: executing
12689 10:03:51.747813 IGT-Version: 1.2<14>[ 27.706447] [IGT] kms_vblank: exiting, ret=77
12690 10:03:51.750761 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12691 10:03:51.761133 Opened devi<8>[ 27.717400] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip>
12692 10:03:51.761408 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip
12694 10:03:51.764683 ce: /dev/dri/card0
12695 10:03:51.767608 No KMS driver or no outputs, pipes: 8, outputs: 0
12696 10:03:51.774480 [1mSubtest pipe-B-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12697 10:03:51.777807 <14>[ 27.738903] [IGT] kms_vblank: executing
12698 10:03:51.784516 IGT-Version: 1.2<14>[ 27.743655] [IGT] kms_vblank: exiting, ret=77
12699 10:03:51.787682 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12700 10:03:51.801239 Opened device: /dev/dri/car<8>[ 27.755083] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip>
12701 10:03:51.801323 d0
12702 10:03:51.801559 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip
12704 10:03:51.804562 No KMS driver or no outputs, pipes: 8, outputs: 0
12705 10:03:51.810721 [1mSubtest pipe-B-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12706 10:03:51.819441 <14>[ 27.780109] [IGT] kms_vblank: executing
12707 10:03:51.826267 IGT-Version: 1.2<14>[ 27.784931] [IGT] kms_vblank: exiting, ret=77
12708 10:03:51.829456 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12709 10:03:51.839846 Opened devi<8>[ 27.796161] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip>
12710 10:03:51.839928 ce: /dev/dri/card0
12711 10:03:51.840164 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip
12713 10:03:51.846493 No KMS driver or no outputs, pipes: 8, outputs: 0
12714 10:03:51.849695 [1mSubtest pipe-C-accuracy-idle: SKIP (0.000s)[0m
12715 10:03:51.856061 <14>[ 27.816154] [IGT] kms_vblank: executing
12716 10:03:51.859203 IGT-Version: 1.2<14>[ 27.820918] [IGT] kms_vblank: exiting, ret=77
12717 10:03:51.866196 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12718 10:03:51.875843 Opened device: /dev/dri/car<8>[ 27.832297] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle RESULT=skip>
12719 10:03:51.875925 d0
12720 10:03:51.876161 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle RESULT=skip
12722 10:03:51.879148 No KMS driver or no outputs, pipes: 8, outputs: 0
12723 10:03:51.885777 [1mSubtest pipe-C-query-idle: SKIP (0.000s)[0m
12724 10:03:51.893029 <14>[ 27.853483] [IGT] kms_vblank: executing
12725 10:03:51.899867 IGT-Version: 1.2<14>[ 27.858415] [IGT] kms_vblank: exiting, ret=77
12726 10:03:51.903216 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12727 10:03:51.913233 Opened device: /dev/dri/car<8>[ 27.870578] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip>
12728 10:03:51.913315 d0
12729 10:03:51.913550 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip
12731 10:03:51.919392 No KMS driver or no outputs, pipes: 8, outputs: 0
12732 10:03:51.922881 [1mSubtest pipe-C-query-idle-hang: SKIP (0.000s)[0m
12733 10:03:51.930746 <14>[ 27.891023] [IGT] kms_vblank: executing
12734 10:03:51.936999 IGT-Version: 1.2<14>[ 27.895769] [IGT] kms_vblank: exiting, ret=77
12735 10:03:51.940242 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12736 10:03:51.950407 Opened device: /dev/dri/car<8>[ 27.907357] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked RESULT=skip>
12737 10:03:51.950490 d0
12738 10:03:51.950727 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked RESULT=skip
12740 10:03:51.953852 No KMS driver or no outputs, pipes: 8, outputs: 0
12741 10:03:51.960176 [1mSubtest pipe-C-query-forked: SKIP (0.000s)[0m
12742 10:03:51.970781 <14>[ 27.931301] [IGT] kms_vblank: executing
12743 10:03:51.977377 IGT-Version: 1.2<14>[ 27.936059] [IGT] kms_vblank: exiting, ret=77
12744 10:03:51.980519 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12745 10:03:51.990786 Opened device: /dev/dri/car<8>[ 27.948257] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip>
12746 10:03:51.990881 d0
12747 10:03:51.991135 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip
12749 10:03:51.997376 No KMS driver or no outputs, pipes: 8, outputs: 0
12750 10:03:52.000461 [1mSubtest pipe-C-query-forked-hang: SKIP (0.000s)[0m
12751 10:03:52.009177 <14>[ 27.969488] [IGT] kms_vblank: executing
12752 10:03:52.015350 IGT-Version: 1.2<14>[ 27.974328] [IGT] kms_vblank: exiting, ret=77
12753 10:03:52.018669 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12754 10:03:52.028796 Opened devi<8>[ 27.985379] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy RESULT=skip>
12755 10:03:52.028877 ce: /dev/dri/card0
12756 10:03:52.029114 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy RESULT=skip
12758 10:03:52.032121 No KMS driver or no outputs, pipes: 8, outputs: 0
12759 10:03:52.038651 [1mSubtest pipe-C-query-busy: SKIP (0.000s)[0m
12760 10:03:52.045181 <14>[ 28.005141] [IGT] kms_vblank: executing
12761 10:03:52.048574 IGT-Version: 1.2<14>[ 28.009896] [IGT] kms_vblank: exiting, ret=77
12762 10:03:52.055046 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12763 10:03:52.065513 Opened device: /dev/dri/car<8>[ 28.021166] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip>
12764 10:03:52.065605 d0
12765 10:03:52.065846 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip
12767 10:03:52.068892 No KMS driver or no outputs, pipes: 8, outputs: 0
12768 10:03:52.075483 [1mSubtest pipe-C-query-busy-hang: SKIP (0.000s)[0m
12769 10:03:52.083706 <14>[ 28.044247] [IGT] kms_vblank: executing
12770 10:03:52.090099 IGT-Version: 1.2<14>[ 28.049000] [IGT] kms_vblank: exiting, ret=77
12771 10:03:52.093824 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12772 10:03:52.103443 Opened device: /dev/dri/car<8>[ 28.060362] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip>
12773 10:03:52.103528 d0
12774 10:03:52.103766 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip
12776 10:03:52.110524 No KMS driver or no outputs, pipes: 8, outputs: 0
12777 10:03:52.113509 [1mSubtest pipe-C-query-forked-busy: SKIP (0.000s)[0m
12778 10:03:52.121175 <14>[ 28.081933] [IGT] kms_vblank: executing
12779 10:03:52.128034 IGT-Version: 1.2<14>[ 28.086680] [IGT] kms_vblank: exiting, ret=77
12780 10:03:52.131365 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12781 10:03:52.141350 Opened device: /dev/dri/car<8>[ 28.099058] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip>
12782 10:03:52.141455 d0
12783 10:03:52.141742 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip
12785 10:03:52.147791 No KMS driver or no outputs, pipes: 8, outputs: 0
12786 10:03:52.150902 [1mSubtest pipe-C-query-forked-busy-hang: SKIP (0.000s)[0m
12787 10:03:52.162029 <14>[ 28.122791] [IGT] kms_vblank: executing
12788 10:03:52.169034 IGT-Version: 1.2<14>[ 28.127540] [IGT] kms_vblank: exiting, ret=77
12789 10:03:52.171979 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12790 10:03:52.178850 Opened devi<8>[ 28.138677] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle RESULT=skip>
12791 10:03:52.179148 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle RESULT=skip
12793 10:03:52.182279 ce: /dev/dri/card0
12794 10:03:52.185689 No KMS driver or no outputs, pipes: 8, outputs: 0
12795 10:03:52.192065 [1mSubtest pipe-C-wait-idle: SKIP (0.000s)[0m
12796 10:03:52.200265 <14>[ 28.160975] [IGT] kms_vblank: executing
12797 10:03:52.206902 IGT-Version: 1.2<14>[ 28.165721] [IGT] kms_vblank: exiting, ret=77
12798 10:03:52.210372 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12799 10:03:52.220288 Opened device: /dev/dri/car<8>[ 28.177133] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip>
12800 10:03:52.220372 d0
12801 10:03:52.220610 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip
12803 10:03:52.223540 No KMS driver or no outputs, pipes: 8, outputs: 0
12804 10:03:52.230216 [1mSubtest pipe-C-wait-idle-hang: SKIP (0.000s)[0m
12805 10:03:52.239418 <14>[ 28.200095] [IGT] kms_vblank: executing
12806 10:03:52.246649 IGT-Version: 1.2<14>[ 28.204870] [IGT] kms_vblank: exiting, ret=77
12807 10:03:52.249903 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12808 10:03:52.259224 Opened device: /dev/dri/car<8>[ 28.216253] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked RESULT=skip>
12809 10:03:52.259309 d0
12810 10:03:52.259546 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked RESULT=skip
12812 10:03:52.262642 No KMS driver or no outputs, pipes: 8, outputs: 0
12813 10:03:52.269609 [1mSubtest pipe-C-wait-forked: SKIP (0.000s)[0m
12814 10:03:52.277118 <14>[ 28.237496] [IGT] kms_vblank: executing
12815 10:03:52.283512 IGT-Version: 1.2<14>[ 28.242363] [IGT] kms_vblank: exiting, ret=77
12816 10:03:52.286809 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12817 10:03:52.297165 Opened devi<8>[ 28.253382] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip>
12818 10:03:52.297249 ce: /dev/dri/card0
12819 10:03:52.297486 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip
12821 10:03:52.303576 No KMS driver or no outputs, pipes: 8, outputs: 0
12822 10:03:52.306832 [1mSubtest pipe-C-wait-forked-hang: SKIP (0.000s)[0m
12823 10:03:52.323211 <14>[ 28.283515] [IGT] kms_vblank: executing
12824 10:03:52.329531 IGT-Version: 1.2<14>[ 28.288631] [IGT] kms_vblank: exiting, ret=77
12825 10:03:52.333016 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12826 10:03:52.342951 Opened device: /dev/dri/car<8>[ 28.299748] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy RESULT=skip>
12827 10:03:52.343035 d0
12828 10:03:52.343272 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy RESULT=skip
12830 10:03:52.346408 No KMS driver or no outputs, pipes: 8, outputs: 0
12831 10:03:52.352833 [1mSubtest pipe-C-wait-busy: SKIP (0.000s)[0m
12832 10:03:52.363059 <14>[ 28.323505] [IGT] kms_vblank: executing
12833 10:03:52.369918 IGT-Version: 1.2<14>[ 28.328262] [IGT] kms_vblank: exiting, ret=77
12834 10:03:52.372754 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12835 10:03:52.382716 Opened device: /dev/dri/car<8>[ 28.340152] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip>
12836 10:03:52.382826 d0
12837 10:03:52.383117 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip
12839 10:03:52.385994 No KMS driver or no outputs, pipes: 8, outputs: 0
12840 10:03:52.392670 [1mSubtest pipe-C-wait-busy-hang: SKIP (0.000s)[0m
12841 10:03:52.402370 <14>[ 28.362861] [IGT] kms_vblank: executing
12842 10:03:52.409216 IGT-Version: 1.2<14>[ 28.367664] [IGT] kms_vblank: exiting, ret=77
12843 10:03:52.412453 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12844 10:03:52.421945 Opened device: /dev/dri/car<8>[ 28.379165] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip>
12845 10:03:52.422030 d0
12846 10:03:52.422265 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip
12848 10:03:52.428683 No KMS driver or no outputs, pipes: 8, outputs: 0
12849 10:03:52.432016 [1mSubtest pipe-C-wait-forked-busy: SKIP (0.000s)[0m
12850 10:03:52.442182 <14>[ 28.402570] [IGT] kms_vblank: executing
12851 10:03:52.448628 IGT-Version: 1.2<14>[ 28.407334] [IGT] kms_vblank: exiting, ret=77
12852 10:03:52.451807 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12853 10:03:52.461993 Opened device: /dev/dri/car<8>[ 28.419627] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip>
12854 10:03:52.462078 d0
12855 10:03:52.462315 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip
12857 10:03:52.468937 No KMS driver or no outputs, pipes: 8, outputs: 0
12858 10:03:52.472169 [1mSubtest pipe-C-wait-forked-busy-hang: SKIP (0.000s)[0m
12859 10:03:52.481129 <14>[ 28.441752] [IGT] kms_vblank: executing
12860 10:03:52.487701 IGT-Version: 1.2<14>[ 28.446537] [IGT] kms_vblank: exiting, ret=77
12861 10:03:52.491221 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12862 10:03:52.501472 Opened devi<8>[ 28.457476] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip>
12863 10:03:52.501555 ce: /dev/dri/card0
12864 10:03:52.501791 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip
12866 10:03:52.507978 No KMS driver or no outputs, pipes: 8, outputs: 0
12867 10:03:52.511327 [1mSubtest pipe-C-ts-continuation-idle: SKIP (0.000s)[0m
12868 10:03:52.517932 <14>[ 28.478352] [IGT] kms_vblank: executing
12869 10:03:52.524655 IGT-Version: 1.2<14>[ 28.483152] [IGT] kms_vblank: exiting, ret=77
12870 10:03:52.527844 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12871 10:03:52.538183 Opened device: /dev/dri/car<8>[ 28.495522] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip>
12872 10:03:52.538267 d0
12873 10:03:52.538503 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip
12875 10:03:52.544427 No KMS driver or no outputs, pipes: 8, outputs: 0
12876 10:03:52.547546 [1mSubtest pipe-C-ts-continuation-idle-hang: SKIP (0.000s)[0m
12877 10:03:52.556677 <14>[ 28.517194] [IGT] kms_vblank: executing
12878 10:03:52.563443 IGT-Version: 1.2<14>[ 28.521966] [IGT] kms_vblank: exiting, ret=77
12879 10:03:52.566820 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12880 10:03:52.576746 Opened device: /dev/dri/car<8>[ 28.533933] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip>
12881 10:03:52.576829 d0
12882 10:03:52.577065 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip
12884 10:03:52.582995 No KMS driver or no outputs, pipes: 8, outputs: 0
12885 10:03:52.586485 [1mSubtest pipe-C-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12886 10:03:52.595178 <14>[ 28.555887] [IGT] kms_vblank: executing
12887 10:03:52.601877 IGT-Version: 1.2<14>[ 28.560659] [IGT] kms_vblank: exiting, ret=77
12888 10:03:52.605269 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12889 10:03:52.615317 Opened devi<8>[ 28.571763] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip>
12890 10:03:52.615571 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip
12892 10:03:52.618627 ce: /dev/dri/card0
12893 10:03:52.621811 No KMS driver or no outputs, pipes: 8, outputs: 0
12894 10:03:52.628797 [1mSubtest pipe-C-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12895 10:03:52.631777 <14>[ 28.593194] [IGT] kms_vblank: executing
12896 10:03:52.638417 IGT-Version: 1.2<14>[ 28.597991] [IGT] kms_vblank: exiting, ret=77
12897 10:03:52.642163 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12898 10:03:52.652067 Opened device: /dev/dri/car<8>[ 28.610147] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip>
12899 10:03:52.652321 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip
12901 10:03:52.654986 d0
12902 10:03:52.658633 No KMS driver or no outputs, pipes: 8, outputs: 0
12903 10:03:52.665384 [1mSubtest pipe-C-ts-continuation-suspend: SKIP (0.000s)[0m
12904 10:03:52.668427 <14>[ 28.631396] [IGT] kms_vblank: executing
12905 10:03:52.675297 IGT-Version: 1.2<14>[ 28.636174] [IGT] kms_vblank: exiting, ret=77
12906 10:03:52.681515 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12907 10:03:52.691857 Opened device: /dev/dri/car<8>[ 28.647550] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip>
12908 10:03:52.691941 d0
12909 10:03:52.692177 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip
12911 10:03:52.695048 No KMS driver or no outputs, pipes: 8, outputs: 0
12912 10:03:52.701744 [1mSubtest pipe-C-ts-continuation-modeset: SKIP (0.000s)[0m
12913 10:03:52.711798 <14>[ 28.672403] [IGT] kms_vblank: executing
12914 10:03:52.718214 IGT-Version: 1.2<14>[ 28.677144] [IGT] kms_vblank: exiting, ret=77
12915 10:03:52.721499 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12916 10:03:52.731672 Opened devi<8>[ 28.688249] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip>
12917 10:03:52.731927 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip
12919 10:03:52.735229 ce: /dev/dri/card0
12920 10:03:52.737973 No KMS driver or no outputs, pipes: 8, outputs: 0
12921 10:03:52.744737 [1mSubtest pipe-C-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12922 10:03:52.758737 <14>[ 28.719468] [IGT] kms_vblank: executing
12923 10:03:52.765282 IGT-Version: 1.2<14>[ 28.724699] [IGT] kms_vblank: exiting, ret=77
12924 10:03:52.768770 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12925 10:03:52.779095 Opened device: /dev/dri/car<8>[ 28.735750] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip>
12926 10:03:52.779351 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip
12928 10:03:52.781846 d0
12929 10:03:52.785584 No KMS driver or no outputs, pipes: 8, outputs: 0
12930 10:03:52.791808 [1mSubtest pipe-C-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12931 10:03:52.800653 <14>[ 28.761259] [IGT] kms_vblank: executing
12932 10:03:52.807124 IGT-Version: 1.2<14>[ 28.766152] [IGT] kms_vblank: exiting, ret=77
12933 10:03:52.810583 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12934 10:03:52.820433 Opened devi<8>[ 28.776500] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip>
12935 10:03:52.820517 ce: /dev/dri/card0
12936 10:03:52.820753 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip
12938 10:03:52.827365 No KMS driver or no outputs, pipes: 8, outputs: 0
12939 10:03:52.830772 [1mSubtest pipe-D-accuracy-idle: SKIP (0.000s)[0m
12940 10:03:52.837311 <14>[ 28.797235] [IGT] kms_vblank: executing
12941 10:03:52.840536 IGT-Version: 1.2<14>[ 28.801981] [IGT] kms_vblank: exiting, ret=77
12942 10:03:52.847324 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12943 10:03:52.853968 Opened devi<8>[ 28.812319] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle RESULT=skip>
12944 10:03:52.854222 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle RESULT=skip
12946 10:03:52.857107 ce: /dev/dri/card0
12947 10:03:52.860315 No KMS driver or no outputs, pipes: 8, outputs: 0
12948 10:03:52.867089 [1mSubtest pipe-D-query-idle: SKIP (0.000s)[0m
12949 10:03:52.870758 <14>[ 28.832510] [IGT] kms_vblank: executing
12950 10:03:52.877378 IGT-Version: 1.2<14>[ 28.837231] [IGT] kms_vblank: exiting, ret=77
12951 10:03:52.880305 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12952 10:03:52.890182 Opened devi<8>[ 28.847513] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip>
12953 10:03:52.890437 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip
12955 10:03:52.893632 ce: /dev/dri/card0
12956 10:03:52.897118 No KMS driver or no outputs, pipes: 8, outputs: 0
12957 10:03:52.900325 [1mSubtest pipe-D-query-idle-hang: SKIP (0.000s)[0m
12958 10:03:52.919514 <14>[ 28.879967] [IGT] kms_vblank: executing
12959 10:03:52.925977 IGT-Version: 1.2<14>[ 28.885097] [IGT] kms_vblank: exiting, ret=77
12960 10:03:52.929547 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12961 10:03:52.939474 Opened device: /dev/dri/car<8>[ 28.896379] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked RESULT=skip>
12962 10:03:52.939558 d0
12963 10:03:52.939793 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked RESULT=skip
12965 10:03:52.942779 No KMS driver or no outputs, pipes: 8, outputs: 0
12966 10:03:52.949592 [1mSubtest pipe-D-query-forked: SKIP (0.000s)[0m
12967 10:03:52.956731 <14>[ 28.917507] [IGT] kms_vblank: executing
12968 10:03:52.963196 IGT-Version: 1.2<14>[ 28.922366] [IGT] kms_vblank: exiting, ret=77
12969 10:03:52.966811 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12970 10:03:52.976934 Opened device: /dev/dri/car<8>[ 28.934670] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip>
12971 10:03:52.977018 d0
12972 10:03:52.977253 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip
12974 10:03:52.983349 No KMS driver or no outputs, pipes: 8, outputs: 0
12975 10:03:52.987141 [1mSubtest pipe-D-query-forked-hang: SKIP (0.000s)[0m
12976 10:03:52.994548 <14>[ 28.955185] [IGT] kms_vblank: executing
12977 10:03:53.001158 IGT-Version: 1.2<14>[ 28.959946] [IGT] kms_vblank: exiting, ret=77
12978 10:03:53.004880 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12979 10:03:53.014391 Opened device: /dev/dri/car<8>[ 28.971520] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy RESULT=skip>
12980 10:03:53.014476 d0
12981 10:03:53.014711 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy RESULT=skip
12983 10:03:53.017932 No KMS driver or no outputs, pipes: 8, outputs: 0
12984 10:03:53.024581 [1mSubtest pipe-D-query-busy: SKIP (0.000s)[0m
12985 10:03:53.034498 <14>[ 28.995384] [IGT] kms_vblank: executing
12986 10:03:53.041540 IGT-Version: 1.2<14>[ 29.000131] [IGT] kms_vblank: exiting, ret=77
12987 10:03:53.045524 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12988 10:03:53.054847 Opened device: /dev/dri/car<8>[ 29.011462] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip>
12989 10:03:53.054937 d0
12990 10:03:53.055172 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip
12992 10:03:53.061378 No KMS driver or no outputs, pipes: 8, outputs: 0
12993 10:03:53.064852 [1mSubtest pipe-D-query-busy-hang: SKIP (0.000s)[0m
12994 10:03:53.074292 <14>[ 29.035079] [IGT] kms_vblank: executing
12995 10:03:53.081228 IGT-Version: 1.2<14>[ 29.039821] [IGT] kms_vblank: exiting, ret=77
12996 10:03:53.084108 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12997 10:03:53.094577 Opened device: /dev/dri/car<8>[ 29.051342] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip>
12998 10:03:53.094659 d0
12999 10:03:53.094881 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip
13001 10:03:53.100723 No KMS driver or no outputs, pipes: 8, outputs: 0
13002 10:03:53.104916 [1mSubtest pipe-D-query-forked-busy: SKIP (0.000s)[0m
13003 10:03:53.115180 <14>[ 29.075693] [IGT] kms_vblank: executing
13004 10:03:53.122055 IGT-Version: 1.2<14>[ 29.080419] [IGT] kms_vblank: exiting, ret=77
13005 10:03:53.124967 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13006 10:03:53.134742 Opened device: /dev/dri/car<8>[ 29.091989] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip>
13007 10:03:53.134825 d0
13008 10:03:53.135070 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip
13010 10:03:53.141742 No KMS driver or no outputs, pipes: 8, outputs: 0
13011 10:03:53.145119 [1mSubtest pipe-D-query-forked-busy-hang: SKIP (0.000s)[0m
13012 10:03:53.155026 <14>[ 29.115547] [IGT] kms_vblank: executing
13013 10:03:53.161390 IGT-Version: 1.2<14>[ 29.120280] [IGT] kms_vblank: exiting, ret=77
13014 10:03:53.164772 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13015 10:03:53.175158 Opened device: /dev/dri/car<8>[ 29.131474] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle RESULT=skip>
13016 10:03:53.175242 d0
13017 10:03:53.175477 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle RESULT=skip
13019 10:03:53.178067 No KMS driver or no outputs, pipes: 8, outputs: 0
13020 10:03:53.184879 [1mSubtest pipe-D-wait-idle: SKIP (0.000s)[0m
13021 10:03:53.192173 <14>[ 29.152498] [IGT] kms_vblank: executing
13022 10:03:53.198735 IGT-Version: 1.2<14>[ 29.157435] [IGT] kms_vblank: exiting, ret=77
13023 10:03:53.202027 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13024 10:03:53.211961 Opened device: /dev/dri/car<8>[ 29.169571] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip>
13025 10:03:53.212046 d0
13026 10:03:53.212281 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip
13028 10:03:53.218283 No KMS driver or no outputs, pipes: 8, outputs: 0
13029 10:03:53.221738 [1mSubtest pipe-D-wait-idle-hang: SKIP (0.000s)[0m
13030 10:03:53.229954 <14>[ 29.190457] [IGT] kms_vblank: executing
13031 10:03:53.236519 IGT-Version: 1.2<14>[ 29.195209] [IGT] kms_vblank: exiting, ret=77
13032 10:03:53.239978 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13033 10:03:53.250079 Opened device: /dev/dri/car<8>[ 29.206499] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked RESULT=skip>
13034 10:03:53.250163 d0
13035 10:03:53.250399 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked RESULT=skip
13037 10:03:53.253445 No KMS driver or no outputs, pipes: 8, outputs: 0
13038 10:03:53.259888 [1mSubtest pipe-D-wait-forked: SKIP (0.000s)[0m
13039 10:03:53.268293 <14>[ 29.229095] [IGT] kms_vblank: executing
13040 10:03:53.274759 IGT-Version: 1.2<14>[ 29.233875] [IGT] kms_vblank: exiting, ret=77
13041 10:03:53.278555 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13042 10:03:53.288241 Opened device: /dev/dri/car<8>[ 29.245212] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip>
13043 10:03:53.288324 d0
13044 10:03:53.288559 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip
13046 10:03:53.295052 No KMS driver or no outputs, pipes: 8, outputs: 0
13047 10:03:53.298323 [1mSubtest pipe-D-wait-forked-hang: SKIP (0.000s)[0m
13048 10:03:53.306152 <14>[ 29.266697] [IGT] kms_vblank: executing
13049 10:03:53.312719 IGT-Version: 1.2<14>[ 29.271433] [IGT] kms_vblank: exiting, ret=77
13050 10:03:53.316008 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13051 10:03:53.322857 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy RESULT=skip
13053 10:03:53.326185 Opened devi<8>[ 29.282642] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy RESULT=skip>
13054 10:03:53.326268 ce: /dev/dri/card0
13055 10:03:53.329273 No KMS driver or no outputs, pipes: 8, outputs: 0
13056 10:03:53.335811 [1mSubtest pipe-D-wait-busy: SKIP (0.000s)[0m
13057 10:03:53.344090 <14>[ 29.304819] [IGT] kms_vblank: executing
13058 10:03:53.350689 IGT-Version: 1.2<14>[ 29.309579] [IGT] kms_vblank: exiting, ret=77
13059 10:03:53.354070 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13060 10:03:53.363917 Opened device: /dev/dri/car<8>[ 29.320851] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip>
13061 10:03:53.364009 d0
13062 10:03:53.364246 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip
13064 10:03:53.370727 No KMS driver or no outputs, pipes: 8, outputs: 0
13065 10:03:53.373990 [1mSubtest pipe-D-wait-busy-hang: SKIP (0.000s)[0m
13066 10:03:53.383733 <14>[ 29.344077] [IGT] kms_vblank: executing
13067 10:03:53.389904 IGT-Version: 1.2<14>[ 29.348856] [IGT] kms_vblank: exiting, ret=77
13068 10:03:53.393044 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13069 10:03:53.403454 Opened device: /dev/dri/car<8>[ 29.361232] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip>
13070 10:03:53.403563 d0
13071 10:03:53.403851 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip
13073 10:03:53.409860 No KMS driver or no outputs, pipes: 8, outputs: 0
13074 10:03:53.412942 [1mSubtest pipe-D-wait-forked-busy: SKIP (0.000s)[0m
13075 10:03:53.431804 <14>[ 29.392261] [IGT] kms_vblank: executing
13076 10:03:53.438534 IGT-Version: 1.2<14>[ 29.397396] [IGT] kms_vblank: exiting, ret=77
13077 10:03:53.441299 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13078 10:03:53.444823 Opened device: /dev/dri/card0
13079 10:03:53.454869 No KMS drive<8>[ 29.410778] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip>
13080 10:03:53.455122 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip
13082 10:03:53.458084 r or no outputs, pipes: 8, outputs: 0
13083 10:03:53.461299 [1mSubtest pipe-D-wait-forked-busy-hang: SKIP (0.000s)[0m
13084 10:03:53.472941 <14>[ 29.433374] [IGT] kms_vblank: executing
13085 10:03:53.479740 IGT-Version: 1.2<14>[ 29.438241] [IGT] kms_vblank: exiting, ret=77
13086 10:03:53.482702 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13087 10:03:53.492763 Opened device: /dev/dri/car<8>[ 29.449401] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip>
13088 10:03:53.492848 d0
13089 10:03:53.493083 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip
13091 10:03:53.499217 No KMS driver or no outputs, pipes: 8, outputs: 0
13092 10:03:53.502661 [1mSubtest pipe-D-ts-continuation-idle: SKIP (0.000s)[0m
13093 10:03:53.510671 <14>[ 29.471308] [IGT] kms_vblank: executing
13094 10:03:53.517251 IGT-Version: 1.2<14>[ 29.476074] [IGT] kms_vblank: exiting, ret=77
13095 10:03:53.520379 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13096 10:03:53.530305 Opened device: /dev/dri/car<8>[ 29.487409] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip>
13097 10:03:53.530384 d0
13098 10:03:53.530621 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip
13100 10:03:53.536939 No KMS driver or no outputs, pipes: 8, outputs: 0
13101 10:03:53.543795 [1mSubtest pipe-D-ts-continuation-idle-hang: SKIP (0.000s)[0m
13102 10:03:53.551855 <14>[ 29.512592] [IGT] kms_vblank: executing
13103 10:03:53.558598 IGT-Version: 1.2<14>[ 29.517317] [IGT] kms_vblank: exiting, ret=77
13104 10:03:53.561923 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13105 10:03:53.571467 Opened devi<8>[ 29.528509] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip>
13106 10:03:53.571551 ce: /dev/dri/card0
13107 10:03:53.571788 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip
13109 10:03:53.578420 No KMS driver or no outputs, pipes: 8, outputs: 0
13110 10:03:53.581665 [1mSubtest pipe-D-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13111 10:03:53.588954 <14>[ 29.549418] [IGT] kms_vblank: executing
13112 10:03:53.595355 IGT-Version: 1.2<14>[ 29.554508] [IGT] kms_vblank: exiting, ret=77
13113 10:03:53.598499 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13114 10:03:53.608765 Opened device: /dev/dri/car<8>[ 29.566704] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip>
13115 10:03:53.609020 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip
13117 10:03:53.611934 d0
13118 10:03:53.615201 No KMS driver or no outputs, pipes: 8, outputs: 0
13119 10:03:53.621565 [1mSubtest pipe-D-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13120 10:03:53.624994 <14>[ 29.588231] [IGT] kms_vblank: executing
13121 10:03:53.631565 IGT-Version: 1.2<14>[ 29.592994] [IGT] kms_vblank: exiting, ret=77
13122 10:03:53.638393 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13123 10:03:53.648265 Opened device: /dev/dri/car<8>[ 29.604329] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip>
13124 10:03:53.648349 d0
13125 10:03:53.648585 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip
13127 10:03:53.651833 No KMS driver or no outputs, pipes: 8, outputs: 0
13128 10:03:53.658043 [1mSubtest pipe-D-ts-continuation-suspend: SKIP (0.000s)[0m
13129 10:03:53.665958 <14>[ 29.626430] [IGT] kms_vblank: executing
13130 10:03:53.672781 IGT-Version: 1.2<14>[ 29.631184] [IGT] kms_vblank: exiting, ret=77
13131 10:03:53.675947 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13132 10:03:53.685879 Opened device: /dev/dri/car<8>[ 29.643500] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip>
13133 10:03:53.685961 d0
13134 10:03:53.686233 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip
13136 10:03:53.692966 No KMS driver or no outputs, pipes: 8, outputs: 0
13137 10:03:53.695481 [1mSubtest pipe-D-ts-continuation-modeset: SKIP (0.000s)[0m
13138 10:03:53.705388 <14>[ 29.666135] [IGT] kms_vblank: executing
13139 10:03:53.712247 IGT-Version: 1.2<14>[ 29.670875] [IGT] kms_vblank: exiting, ret=77
13140 10:03:53.715483 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13141 10:03:53.725788 Opened device: /dev/dri/car<8>[ 29.682382] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip>
13142 10:03:53.725871 d0
13143 10:03:53.726114 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip
13145 10:03:53.732141 No KMS driver or no outputs, pipes: 8, outputs: 0
13146 10:03:53.738966 [1mSubtest pipe-D-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13147 10:03:53.747274 <14>[ 29.707802] [IGT] kms_vblank: executing
13148 10:03:53.753766 IGT-Version: 1.2<14>[ 29.712540] [IGT] kms_vblank: exiting, ret=77
13149 10:03:53.757146 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13150 10:03:53.766887 Opened device: /dev/dri/car<8>[ 29.724080] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip>
13151 10:03:53.767159 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip
13153 10:03:53.770404 d0
13154 10:03:53.773920 No KMS driver or no outputs, pipes: 8, outputs: 0
13155 10:03:53.780141 [1mSubtest pipe-D-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13156 10:03:53.783394 <14>[ 29.746046] [IGT] kms_vblank: executing
13157 10:03:53.790078 IGT-Version: 1.2<14>[ 29.750879] [IGT] kms_vblank: exiting, ret=77
13158 10:03:53.796766 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13159 10:03:53.807032 Opened device: /dev/dri/car<8>[ 29.762988] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip>
13160 10:03:53.807116 d0
13161 10:03:53.807353 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip
13163 10:03:53.810106 No KMS driver or no outputs, pipes: 8, outputs: 0
13164 10:03:53.813714 [1mSubtest pipe-E-accuracy-idle: SKIP (0.000s)[0m
13165 10:03:53.822594 <14>[ 29.783466] [IGT] kms_vblank: executing
13166 10:03:53.829538 IGT-Version: 1.2<14>[ 29.788234] [IGT] kms_vblank: exiting, ret=77
13167 10:03:53.832908 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13168 10:03:53.842584 Opened device: /dev/dri/car<8>[ 29.799506] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle RESULT=skip>
13169 10:03:53.842668 d0
13170 10:03:53.842918 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle RESULT=skip
13172 10:03:53.845763 No KMS driver or no outputs, pipes: 8, outputs: 0
13173 10:03:53.852306 [1mSubtest pipe-E-query-idle: SKIP (0.000s)[0m
13174 10:03:53.862181 <14>[ 29.822668] [IGT] kms_vblank: executing
13175 10:03:53.868664 IGT-Version: 1.2<14>[ 29.827411] [IGT] kms_vblank: exiting, ret=77
13176 10:03:53.872213 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13177 10:03:53.881861 Opened device: /dev/dri/car<8>[ 29.838650] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip>
13178 10:03:53.881971 d0
13179 10:03:53.882222 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip
13181 10:03:53.888071 No KMS driver or no outputs, pipes: 8, outputs: 0
13182 10:03:53.891425 [1mSubtest pipe-E-query-idle-hang: SKIP (0.000s)[0m
13183 10:03:53.902566 <14>[ 29.863294] [IGT] kms_vblank: executing
13184 10:03:53.908900 IGT-Version: 1.2<14>[ 29.868009] [IGT] kms_vblank: exiting, ret=77
13185 10:03:53.912949 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13186 10:03:53.922179 Opened device: /dev/dri/car<8>[ 29.879479] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked RESULT=skip>
13187 10:03:53.922259 d0
13188 10:03:53.922496 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked RESULT=skip
13190 10:03:53.925699 No KMS driver or no outputs, pipes: 8, outputs: 0
13191 10:03:53.932331 [1mSubtest pipe-E-query-forked: SKIP (0.000s)[0m
13192 10:03:53.939648 <14>[ 29.900454] [IGT] kms_vblank: executing
13193 10:03:53.946629 IGT-Version: 1.2<14>[ 29.905230] [IGT] kms_vblank: exiting, ret=77
13194 10:03:53.949595 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13195 10:03:53.959392 Opened device: /dev/dri/car<8>[ 29.916514] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip>
13196 10:03:53.959494 d0
13197 10:03:53.959761 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip
13199 10:03:53.966204 No KMS driver or no outputs, pipes: 8, outputs: 0
13200 10:03:53.969495 [1mSubtest pipe-E-query-forked-hang: SKIP (0.000s)[0m
13201 10:03:53.977046 <14>[ 29.937918] [IGT] kms_vblank: executing
13202 10:03:53.983779 IGT-Version: 1.2<14>[ 29.942649] [IGT] kms_vblank: exiting, ret=77
13203 10:03:53.987231 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13204 10:03:53.993633 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy RESULT=skip
13206 10:03:53.996731 Opened devi<8>[ 29.953632] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy RESULT=skip>
13207 10:03:53.996816 ce: /dev/dri/card0
13208 10:03:54.000734 No KMS driver or no outputs, pipes: 8, outputs: 0
13209 10:03:54.006735 [1mSubtest pipe-E-query-busy: SKIP (0.000s)[0m
13210 10:03:54.022552 <14>[ 29.983385] [IGT] kms_vblank: executing
13211 10:03:54.029786 IGT-Version: 1.2<14>[ 29.988482] [IGT] kms_vblank: exiting, ret=77
13212 10:03:54.032804 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13213 10:03:54.042374 Opened device: /dev/dri/car<8>[ 29.999646] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip>
13214 10:03:54.042459 d0
13215 10:03:54.042730 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip
13217 10:03:54.049252 No KMS driver or no outputs, pipes: 8, outputs: 0
13218 10:03:54.052356 [1mSubtest pipe-E-query-busy-hang: SKIP (0.000s)[0m
13219 10:03:54.061060 <14>[ 30.021659] [IGT] kms_vblank: executing
13220 10:03:54.067687 IGT-Version: 1.2<14>[ 30.026571] [IGT] kms_vblank: exiting, ret=77
13221 10:03:54.070735 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13222 10:03:54.080975 Opened device: /dev/dri/car<8>[ 30.038691] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip>
13223 10:03:54.081059 d0
13224 10:03:54.081298 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip
13226 10:03:54.087821 No KMS driver or no outputs, pipes: 8, outputs: 0
13227 10:03:54.090627 [1mSubtest pipe-E-query-forked-busy: SKIP (0.000s)[0m
13228 10:03:54.098568 <14>[ 30.059292] [IGT] kms_vblank: executing
13229 10:03:54.105345 IGT-Version: 1.2<14>[ 30.064063] [IGT] kms_vblank: exiting, ret=77
13230 10:03:54.108765 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13231 10:03:54.118571 Opened device: /dev/dri/car<8>[ 30.076102] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip>
13232 10:03:54.118656 d0
13233 10:03:54.118883 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip
13235 10:03:54.125374 No KMS driver or no outputs, pipes: 8, outputs: 0
13236 10:03:54.128494 [1mSubtest pipe-E-query-forked-busy-hang: SKIP (0.000s)[0m
13237 10:03:54.138514 <14>[ 30.098547] [IGT] kms_vblank: executing
13238 10:03:54.144234 IGT-Version: 1.2<14>[ 30.103300] [IGT] kms_vblank: exiting, ret=77
13239 10:03:54.147670 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13240 10:03:54.157734 Opened device: /dev/dri/car<8>[ 30.115633] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle RESULT=skip>
13241 10:03:54.157817 d0
13242 10:03:54.158052 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle RESULT=skip
13244 10:03:54.160978 No KMS driver or no outputs, pipes: 8, outputs: 0
13245 10:03:54.167577 [1mSubtest pipe-E-wait-idle: SKIP (0.000s)[0m
13246 10:03:54.174995 <14>[ 30.135575] [IGT] kms_vblank: executing
13247 10:03:54.181786 IGT-Version: 1.2<14>[ 30.140356] [IGT] kms_vblank: exiting, ret=77
13248 10:03:54.184742 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13249 10:03:54.194657 Opened device: /dev/dri/car<8>[ 30.151667] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip>
13250 10:03:54.194771 d0
13251 10:03:54.195078 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip
13253 10:03:54.197962 No KMS driver or no outputs, pipes: 8, outputs: 0
13254 10:03:54.204903 [1mSubtest pipe-E-wait-idle-hang: SKIP (0.000s)[0m
13255 10:03:54.212414 <14>[ 30.173245] [IGT] kms_vblank: executing
13256 10:03:54.219096 IGT-Version: 1.2<14>[ 30.178036] [IGT] kms_vblank: exiting, ret=77
13257 10:03:54.222151 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13258 10:03:54.229317 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked RESULT=skip
13260 10:03:54.232545 Opened devi<8>[ 30.188995] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked RESULT=skip>
13261 10:03:54.232631 ce: /dev/dri/card0
13262 10:03:54.235960 No KMS driver or no outputs, pipes: 8, outputs: 0
13263 10:03:54.242403 [1mSubtest pipe-E-wait-forked: SKIP (0.000s)[0m
13264 10:03:54.245761 <14>[ 30.208884] [IGT] kms_vblank: executing
13265 10:03:54.252370 IGT-Version: 1.2<14>[ 30.213672] [IGT] kms_vblank: exiting, ret=77
13266 10:03:54.259659 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13267 10:03:54.269103 Opened device: /dev/dri/car<8>[ 30.225753] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip>
13268 10:03:54.269197 d0
13269 10:03:54.269434 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip
13271 10:03:54.272241 No KMS driver or no outputs, pipes: 8, outputs: 0
13272 10:03:54.279067 [1mSubtest pipe-E-wait-forked-hang: SKIP (0.000s)[0m
13273 10:03:54.285989 <14>[ 30.246452] [IGT] kms_vblank: executing
13274 10:03:54.292179 IGT-Version: 1.2<14>[ 30.251216] [IGT] kms_vblank: exiting, ret=77
13275 10:03:54.295718 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13276 10:03:54.305785 Opened device: /dev/dri/car<8>[ 30.262535] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy RESULT=skip>
13277 10:03:54.305869 d0
13278 10:03:54.306107 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy RESULT=skip
13280 10:03:54.308962 No KMS driver or no outputs, pipes: 8, outputs: 0
13281 10:03:54.315582 [1mSubtest pipe-E-wait-busy: SKIP (0.000s)[0m
13282 10:03:54.322696 <14>[ 30.283420] [IGT] kms_vblank: executing
13283 10:03:54.329666 IGT-Version: 1.2<14>[ 30.288161] [IGT] kms_vblank: exiting, ret=77
13284 10:03:54.332687 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13285 10:03:54.342575 Opened device: /dev/dri/car<8>[ 30.299454] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip>
13286 10:03:54.342685 d0
13287 10:03:54.342979 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip
13289 10:03:54.345889 No KMS driver or no outputs, pipes: 8, outputs: 0
13290 10:03:54.352319 [1mSubtest pipe-E-wait-busy-hang: SKIP (0.000s)[0m
13291 10:03:54.363620 <14>[ 30.324099] [IGT] kms_vblank: executing
13292 10:03:54.370054 IGT-Version: 1.2<14>[ 30.328829] [IGT] kms_vblank: exiting, ret=77
13293 10:03:54.372996 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13294 10:03:54.383152 Opened devi<8>[ 30.339956] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip>
13295 10:03:54.383236 ce: /dev/dri/card0
13296 10:03:54.383476 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip
13298 10:03:54.389754 No KMS driver or no outputs, pipes: 8, outputs: 0
13299 10:03:54.393149 [1mSubtest pipe-E-wait-forked-busy: SKIP (0.000s)[0m
13300 10:03:54.401420 <14>[ 30.362533] [IGT] kms_vblank: executing
13301 10:03:54.408090 IGT-Version: 1.2<14>[ 30.367291] [IGT] kms_vblank: exiting, ret=77
13302 10:03:54.411337 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13303 10:03:54.421731 Opened device: /dev/dri/car<8>[ 30.378555] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip>
13304 10:03:54.421816 d0
13305 10:03:54.422053 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip
13307 10:03:54.428044 No KMS driver or no outputs, pipes: 8, outputs: 0
13308 10:03:54.431063 [1mSubtest pipe-E-wait-forked-busy-hang: SKIP (0.000s)[0m
13309 10:03:54.442897 <14>[ 30.403551] [IGT] kms_vblank: executing
13310 10:03:54.449477 IGT-Version: 1.2<14>[ 30.408274] [IGT] kms_vblank: exiting, ret=77
13311 10:03:54.452676 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13312 10:03:54.462486 Opened device: /dev/dri/car<8>[ 30.419581] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip>
13313 10:03:54.462572 d0
13314 10:03:54.462809 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip
13316 10:03:54.469235 No KMS driver or no outputs, pipes: 8, outputs: 0
13317 10:03:54.472621 [1mSubtest pipe-E-ts-continuation-idle: SKIP (0.000s)[0m
13318 10:03:54.480156 <14>[ 30.440780] [IGT] kms_vblank: executing
13319 10:03:54.486539 IGT-Version: 1.2<14>[ 30.445527] [IGT] kms_vblank: exiting, ret=77
13320 10:03:54.489764 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13321 10:03:54.499880 Opened devi<8>[ 30.456632] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip>
13322 10:03:54.499967 ce: /dev/dri/card0
13323 10:03:54.500205 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip
13325 10:03:54.506982 No KMS driver or no outputs, pipes: 8, outputs: 0
13326 10:03:54.510024 [1mSubtest pipe-E-ts-continuation-idle-hang: SKIP (0.000s)[0m
13327 10:03:54.517023 <14>[ 30.477797] [IGT] kms_vblank: executing
13328 10:03:54.523403 IGT-Version: 1.2<14>[ 30.482560] [IGT] kms_vblank: exiting, ret=77
13329 10:03:54.526838 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13330 10:03:54.537073 Opened devi<8>[ 30.493527] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip>
13331 10:03:54.537157 ce: /dev/dri/card0
13332 10:03:54.537393 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip
13334 10:03:54.543997 No KMS driver or no outputs, pipes: 8, outputs: 0
13335 10:03:54.546996 [1mSubtest pipe-E-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13336 10:03:54.553575 <14>[ 30.514469] [IGT] kms_vblank: executing
13337 10:03:54.560499 IGT-Version: 1.2<14>[ 30.519232] [IGT] kms_vblank: exiting, ret=77
13338 10:03:54.563344 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13339 10:03:54.573746 Opened device: /dev/dri/car<8>[ 30.530562] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip>
13340 10:03:54.574002 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip
13342 10:03:54.577318 d0
13343 10:03:54.579999 No KMS driver or no outputs, pipes: 8, outputs: 0
13344 10:03:54.586846 [1mSubtest pipe-E-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13345 10:03:54.590229 <14>[ 30.553038] [IGT] kms_vblank: executing
13346 10:03:54.596738 IGT-Version: 1.2<14>[ 30.557835] [IGT] kms_vblank: exiting, ret=77
13347 10:03:54.603592 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13348 10:03:54.613900 Opened device: /dev/dri/car<8>[ 30.570263] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip>
13349 10:03:54.613985 d0
13350 10:03:54.614220 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip
13352 10:03:54.616712 No KMS driver or no outputs, pipes: 8, outputs: 0
13353 10:03:54.623683 [1mSubtest pipe-E-ts-continuation-suspend: SKIP (0.000s)[0m
13354 10:03:54.631631 <14>[ 30.592624] [IGT] kms_vblank: executing
13355 10:03:54.638264 IGT-Version: 1.2<14>[ 30.597415] [IGT] kms_vblank: exiting, ret=77
13356 10:03:54.641815 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13357 10:03:54.651543 Opened devi<8>[ 30.608503] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip>
13358 10:03:54.651625 ce: /dev/dri/card0
13359 10:03:54.651860 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip
13361 10:03:54.658472 No KMS driver or no outputs, pipes: 8, outputs: 0
13362 10:03:54.661745 [1mSubtest pipe-E-ts-continuation-modeset: SKIP (0.000s)[0m
13363 10:03:54.668693 <14>[ 30.629387] [IGT] kms_vblank: executing
13364 10:03:54.675359 IGT-Version: 1.2<14>[ 30.634276] [IGT] kms_vblank: exiting, ret=77
13365 10:03:54.678448 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13366 10:03:54.688532 Opened devi<8>[ 30.645366] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip>
13367 10:03:54.688785 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip
13369 10:03:54.691625 ce: /dev/dri/card0
13370 10:03:54.695116 No KMS driver or no outputs, pipes: 8, outputs: 0
13371 10:03:54.701295 [1mSubtest pipe-E-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13372 10:03:54.704970 <14>[ 30.666535] [IGT] kms_vblank: executing
13373 10:03:54.711857 IGT-Version: 1.2<14>[ 30.671296] [IGT] kms_vblank: exiting, ret=77
13374 10:03:54.715190 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13375 10:03:54.727900 Opened device: /dev/dri/car<8>[ 30.683687] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip>
13376 10:03:54.727983 d0
13377 10:03:54.728217 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip
13379 10:03:54.731741 No KMS driver or no outputs, pipes: 8, outputs: 0
13380 10:03:54.739118 [1mSubtest pipe-E-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13381 10:03:54.745106 <14>[ 30.705273] [IGT] kms_vblank: executing
13382 10:03:54.751359 IGT-Version: 1.2<14>[ 30.710062] [IGT] kms_vblank: exiting, ret=77
13383 10:03:54.754800 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13384 10:03:54.761257 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip
13386 10:03:54.764438 Opened devi<8>[ 30.721044] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip>
13387 10:03:54.764521 ce: /dev/dri/card0
13388 10:03:54.767947 No KMS driver or no outputs, pipes: 8, outputs: 0
13389 10:03:54.774535 [1mSubtest pipe-F-accuracy-idle: SKIP (0.000s)[0m
13390 10:03:54.777623 <14>[ 30.741213] [IGT] kms_vblank: executing
13391 10:03:54.784655 IGT-Version: 1.2<14>[ 30.745997] [IGT] kms_vblank: exiting, ret=77
13392 10:03:54.791441 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13393 10:03:54.797835 Opened devi<8>[ 30.756983] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle RESULT=skip>
13394 10:03:54.798089 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle RESULT=skip
13396 10:03:54.801572 ce: /dev/dri/card0
13397 10:03:54.804696 No KMS driver or no outputs, pipes: 8, outputs: 0
13398 10:03:54.807987 [1mSubtest pipe-F-query-idle: SKIP (0.000s)[0m
13399 10:03:54.816250 <14>[ 30.776911] [IGT] kms_vblank: executing
13400 10:03:54.822854 IGT-Version: 1.2<14>[ 30.781647] [IGT] kms_vblank: exiting, ret=77
13401 10:03:54.825741 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13402 10:03:54.836269 Opened device: /dev/dri/car<8>[ 30.792888] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip>
13403 10:03:54.836357 d0
13404 10:03:54.836598 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip
13406 10:03:54.842849 No KMS driver or no outputs, pipes: 8, outputs: 0
13407 10:03:54.846068 [1mSubtest pipe-F-query-idle-hang: SKIP (0.000s)[0m
13408 10:03:54.853911 <14>[ 30.814349] [IGT] kms_vblank: executing
13409 10:03:54.860659 IGT-Version: 1.2<14>[ 30.819086] [IGT] kms_vblank: exiting, ret=77
13410 10:03:54.864019 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13411 10:03:54.873733 Opened device: /dev/dri/car<8>[ 30.831385] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked RESULT=skip>
13412 10:03:54.873850 d0
13413 10:03:54.874117 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked RESULT=skip
13415 10:03:54.877190 No KMS driver or no outputs, pipes: 8, outputs: 0
13416 10:03:54.884102 [1mSubtest pipe-F-query-forked: SKIP (0.000s)[0m
13417 10:03:54.890662 <14>[ 30.851471] [IGT] kms_vblank: executing
13418 10:03:54.896969 IGT-Version: 1.2<14>[ 30.856229] [IGT] kms_vblank: exiting, ret=77
13419 10:03:54.900688 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13420 10:03:54.910245 Opened device: /dev/dri/car<8>[ 30.867724] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip>
13421 10:03:54.910329 d0
13422 10:03:54.910565 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip
13424 10:03:54.916975 No KMS driver or no outputs, pipes: 8, outputs: 0
13425 10:03:54.920216 [1mSubtest pipe-F-query-forked-hang: SKIP (0.000s)[0m
13426 10:03:54.931149 <14>[ 30.892266] [IGT] kms_vblank: executing
13427 10:03:54.938128 IGT-Version: 1.2<14>[ 30.897150] [IGT] kms_vblank: exiting, ret=77
13428 10:03:54.941349 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13429 10:03:54.951344 Opened device: /dev/dri/car<8>[ 30.908497] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy RESULT=skip>
13430 10:03:54.951427 d0
13431 10:03:54.951670 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy RESULT=skip
13433 10:03:54.954595 No KMS driver or no outputs, pipes: 8, outputs: 0
13434 10:03:54.961057 [1mSubtest pipe-F-query-busy: SKIP (0.000s)[0m
13435 10:03:54.970763 <14>[ 30.931441] [IGT] kms_vblank: executing
13436 10:03:54.977274 IGT-Version: 1.2<14>[ 30.936193] [IGT] kms_vblank: exiting, ret=77
13437 10:03:54.980740 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13438 10:03:54.990247 Opened device: /dev/dri/car<8>[ 30.947584] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip>
13439 10:03:54.990332 d0
13440 10:03:54.990570 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip
13442 10:03:54.996989 No KMS driver or no outputs, pipes: 8, outputs: 0
13443 10:03:55.000695 [1mSubtest pipe-F-query-busy-hang: SKIP (0.000s)[0m
13444 10:03:55.010954 <14>[ 30.971888] [IGT] kms_vblank: executing
13445 10:03:55.017600 IGT-Version: 1.2<14>[ 30.976607] [IGT] kms_vblank: exiting, ret=77
13446 10:03:55.021080 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13447 10:03:55.030609 Opened devi<8>[ 30.987812] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip>
13448 10:03:55.030721 ce: /dev/dri/card0
13449 10:03:55.030985 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip
13451 10:03:55.037572 No KMS driver or no outputs, pipes: 8, outputs: 0
13452 10:03:55.040898 [1mSubtest pipe-F-query-forked-busy: SKIP (0.000s)[0m
13453 10:03:55.049778 <14>[ 31.010583] [IGT] kms_vblank: executing
13454 10:03:55.056344 IGT-Version: 1.2<14>[ 31.015349] [IGT] kms_vblank: exiting, ret=77
13455 10:03:55.059566 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13456 10:03:55.069837 Opened device: /dev/dri/car<8>[ 31.026663] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip>
13457 10:03:55.069923 d0
13458 10:03:55.070159 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip
13460 10:03:55.076152 No KMS driver or no outputs, pipes: 8, outputs: 0
13461 10:03:55.079808 [1mSubtest pipe-F-query-forked-busy-hang: SKIP (0.000s)[0m
13462 10:03:55.090649 <14>[ 31.051656] [IGT] kms_vblank: executing
13463 10:03:55.097273 IGT-Version: 1.2<14>[ 31.056373] [IGT] kms_vblank: exiting, ret=77
13464 10:03:55.100672 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13465 10:03:55.107544 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle RESULT=skip
13467 10:03:55.110589 Opened devi<8>[ 31.067624] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle RESULT=skip>
13468 10:03:55.110674 ce: /dev/dri/card0
13469 10:03:55.113832 No KMS driver or no outputs, pipes: 8, outputs: 0
13470 10:03:55.120353 [1mSubtest pipe-F-wait-idle: SKIP (0.000s)[0m
13471 10:03:55.124223 <14>[ 31.087217] [IGT] kms_vblank: executing
13472 10:03:55.130793 IGT-Version: 1.2<14>[ 31.091969] [IGT] kms_vblank: exiting, ret=77
13473 10:03:55.137463 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13474 10:03:55.147513 Opened device: /dev/dri/car<8>[ 31.103539] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip>
13475 10:03:55.147597 d0
13476 10:03:55.147834 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip
13478 10:03:55.150637 No KMS driver or no outputs, pipes: 8, outputs: 0
13479 10:03:55.157451 [1mSubtest pipe-F-wait-idle-hang: SKIP (0.000s)[0m
13480 10:03:55.164205 <14>[ 31.124824] [IGT] kms_vblank: executing
13481 10:03:55.170682 IGT-Version: 1.2<14>[ 31.129581] [IGT] kms_vblank: exiting, ret=77
13482 10:03:55.174075 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13483 10:03:55.180864 Opened devi<8>[ 31.140751] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked RESULT=skip>
13484 10:03:55.181119 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked RESULT=skip
13486 10:03:55.184158 ce: /dev/dri/card0
13487 10:03:55.187697 No KMS driver or no outputs, pipes: 8, outputs: 0
13488 10:03:55.194277 [1mSubtest pipe-F-wait-forked: SKIP (0.000s)[0m
13489 10:03:55.197657 <14>[ 31.160822] [IGT] kms_vblank: executing
13490 10:03:55.204100 IGT-Version: 1.2<14>[ 31.165540] [IGT] kms_vblank: exiting, ret=77
13491 10:03:55.210661 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13492 10:03:55.220718 Opened device: /dev/dri/car<8>[ 31.177690] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip>
13493 10:03:55.220802 d0
13494 10:03:55.221038 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip
13496 10:03:55.224239 No KMS driver or no outputs, pipes: 8, outputs: 0
13497 10:03:55.231177 [1mSubtest pipe-F-wait-forked-hang: SKIP (0.000s)[0m
13498 10:03:55.237455 <14>[ 31.198441] [IGT] kms_vblank: executing
13499 10:03:55.244055 IGT-Version: 1.2<14>[ 31.203179] [IGT] kms_vblank: exiting, ret=77
13500 10:03:55.247827 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13501 10:03:55.257234 Opened device: /dev/dri/car<8>[ 31.214445] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy RESULT=skip>
13502 10:03:55.257318 d0
13503 10:03:55.257555 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy RESULT=skip
13505 10:03:55.261005 No KMS driver or no outputs, pipes: 8, outputs: 0
13506 10:03:55.267673 [1mSubtest pipe-F-wait-busy: SKIP (0.000s)[0m
13507 10:03:55.276256 <14>[ 31.236954] [IGT] kms_vblank: executing
13508 10:03:55.282750 IGT-Version: 1.2<14>[ 31.241685] [IGT] kms_vblank: exiting, ret=77
13509 10:03:55.286021 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13510 10:03:55.295939 Opened device: /dev/dri/car<8>[ 31.252968] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip>
13511 10:03:55.296047 d0
13512 10:03:55.296286 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip
13514 10:03:55.299151 No KMS driver or no outputs, pipes: 8, outputs: 0
13515 10:03:55.306328 [1mSubtest pipe-F-wait-busy-hang: SKIP (0.000s)[0m
13516 10:03:55.313488 <14>[ 31.274449] [IGT] kms_vblank: executing
13517 10:03:55.320113 IGT-Version: 1.2<14>[ 31.279196] [IGT] kms_vblank: exiting, ret=77
13518 10:03:55.323497 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13519 10:03:55.333444 Opened device: /dev/dri/car<8>[ 31.290572] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip>
13520 10:03:55.333530 d0
13521 10:03:55.333769 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip
13523 10:03:55.340294 No KMS driver or no outputs, pipes: 8, outputs: 0
13524 10:03:55.343404 [1mSubtest pipe-F-wait-forked-busy: SKIP (0.000s)[0m
13525 10:03:55.350821 <14>[ 31.311987] [IGT] kms_vblank: executing
13526 10:03:55.357830 IGT-Version: 1.2<14>[ 31.316730] [IGT] kms_vblank: exiting, ret=77
13527 10:03:55.360814 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13528 10:03:55.370974 Opened device: /dev/dri/car<8>[ 31.328010] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip>
13529 10:03:55.371065 d0
13530 10:03:55.371305 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip
13532 10:03:55.377522 No KMS driver or no outputs, pipes: 8, outputs: 0
13533 10:03:55.380867 [1mSubtest pipe-F-wait-forked-busy-hang: SKIP (0.000s)[0m
13534 10:03:55.392382 <14>[ 31.352745] [IGT] kms_vblank: executing
13535 10:03:55.398797 IGT-Version: 1.2<14>[ 31.357483] [IGT] kms_vblank: exiting, ret=77
13536 10:03:55.401966 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13537 10:03:55.411613 Opened devi<8>[ 31.368649] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip>
13538 10:03:55.411708 ce: /dev/dri/card0
13539 10:03:55.411950 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip
13541 10:03:55.418336 No KMS driver or no outputs, pipes: 8, outputs: 0
13542 10:03:55.421764 [1mSubtest pipe-F-ts-continuation-idle: SKIP (0.000s)[0m
13543 10:03:55.428684 <14>[ 31.389400] [IGT] kms_vblank: executing
13544 10:03:55.435138 IGT-Version: 1.2<14>[ 31.394283] [IGT] kms_vblank: exiting, ret=77
13545 10:03:55.438388 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13546 10:03:55.448466 Opened device: /dev/dri/car<8>[ 31.406400] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip>
13547 10:03:55.448557 d0
13548 10:03:55.448798 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip
13550 10:03:55.455225 No KMS driver or no outputs, pipes: 8, outputs: 0
13551 10:03:55.458189 [1mSubtest pipe-F-ts-continuation-idle-hang: SKIP (0.000s)[0m
13552 10:03:55.469501 <14>[ 31.430186] [IGT] kms_vblank: executing
13553 10:03:55.475782 IGT-Version: 1.2<14>[ 31.434984] [IGT] kms_vblank: exiting, ret=77
13554 10:03:55.479634 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13555 10:03:55.489117 Opened device: /dev/dri/car<8>[ 31.447217] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip>
13556 10:03:55.489208 d0
13557 10:03:55.489450 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip
13559 10:03:55.495762 No KMS driver or no outputs, pipes: 8, outputs: 0
13560 10:03:55.499215 [1mSubtest pipe-F-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13561 10:03:55.507737 <14>[ 31.468597] [IGT] kms_vblank: executing
13562 10:03:55.514274 IGT-Version: 1.2<14>[ 31.473382] [IGT] kms_vblank: exiting, ret=77
13563 10:03:55.517455 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13564 10:03:55.527494 Opened devi<8>[ 31.484543] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip>
13565 10:03:55.527753 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip
13567 10:03:55.530902 ce: /dev/dri/card0
13568 10:03:55.534428 No KMS driver or no outputs, pipes: 8, outputs: 0
13569 10:03:55.540842 [1mSubtest pipe-F-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13570 10:03:55.544288 <14>[ 31.506062] [IGT] kms_vblank: executing
13571 10:03:55.550625 IGT-Version: 1.2<14>[ 31.510829] [IGT] kms_vblank: exiting, ret=77
13572 10:03:55.554272 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13573 10:03:55.564216 Opened devi<8>[ 31.521735] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip>
13574 10:03:55.564484 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip
13576 10:03:55.567455 ce: /dev/dri/card0
13577 10:03:55.570781 No KMS driver or no outputs, pipes: 8, outputs: 0
13578 10:03:55.577502 [1mSubtest pipe-F-ts-continuation-suspend: SKIP (0.000s)[0m
13579 10:03:55.580842 <14>[ 31.542653] [IGT] kms_vblank: executing
13580 10:03:55.587330 IGT-Version: 1.2<14>[ 31.547436] [IGT] kms_vblank: exiting, ret=77
13581 10:03:55.590549 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13582 10:03:55.603977 Opened device: /dev/dri/car<8>[ 31.559765] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip>
13583 10:03:55.604065 d0
13584 10:03:55.604304 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip
13586 10:03:55.607470 No KMS driver or no outputs, pipes: 8, outputs: 0
13587 10:03:55.613746 [1mSubtest pipe-F-ts-continuation-modeset: SKIP (0.000s)[0m
13588 10:03:55.623304 <14>[ 31.583853] [IGT] kms_vblank: executing
13589 10:03:55.629282 IGT-Version: 1.2<14>[ 31.588586] [IGT] kms_vblank: exiting, ret=77
13590 10:03:55.632559 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13591 10:03:55.642447 Opened device: /dev/dri/car<8>[ 31.599865] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip>
13592 10:03:55.642745 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip
13594 10:03:55.645995 d0
13595 10:03:55.649582 No KMS driver or no outputs, pipes: 8, outputs: 0
13596 10:03:55.655901 [1mSubtest pipe-F-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13597 10:03:55.663058 <14>[ 31.624145] [IGT] kms_vblank: executing
13598 10:03:55.670317 IGT-Version: 1.2<14>[ 31.628866] [IGT] kms_vblank: exiting, ret=77
13599 10:03:55.673408 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13600 10:03:55.683020 Opened devi<8>[ 31.639865] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip>
13601 10:03:55.683282 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip
13603 10:03:55.686384 ce: /dev/dri/card0
13604 10:03:55.689463 No KMS driver or no outputs, pipes: 8, outputs: 0
13605 10:03:55.696137 [1mSubtest pipe-F-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13606 10:03:55.699594 <14>[ 31.661269] [IGT] kms_vblank: executing
13607 10:03:55.706208 IGT-Version: 1.2<14>[ 31.666050] [IGT] kms_vblank: exiting, ret=77
13608 10:03:55.709584 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13609 10:03:55.719446 Opened devi<8>[ 31.677135] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip>
13610 10:03:55.719533 ce: /dev/dri/card0
13611 10:03:55.719772 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip
13613 10:03:55.726178 No KMS driver or no outputs, pipes: 8, outputs: 0
13614 10:03:55.730002 [1mSubtest pipe-G-accuracy-idle: SKIP (0.000s)[0m
13615 10:03:55.736796 <14>[ 31.697561] [IGT] kms_vblank: executing
13616 10:03:55.743641 IGT-Version: 1.2<14>[ 31.702602] [IGT] kms_vblank: exiting, ret=77
13617 10:03:55.746359 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13618 10:03:55.756870 Opened devi<8>[ 31.713725] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle RESULT=skip>
13619 10:03:55.756955 ce: /dev/dri/card0
13620 10:03:55.757194 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle RESULT=skip
13622 10:03:55.759960 No KMS driver or no outputs, pipes: 8, outputs: 0
13623 10:03:55.766322 [1mSubtest pipe-G-query-idle: SKIP (0.000s)[0m
13624 10:03:55.773561 <14>[ 31.733527] [IGT] kms_vblank: executing
13625 10:03:55.776535 IGT-Version: 1.2<14>[ 31.738446] [IGT] kms_vblank: exiting, ret=77
13626 10:03:55.783184 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13627 10:03:55.793280 Opened device: /dev/dri/car<8>[ 31.750554] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip>
13628 10:03:55.793367 d0
13629 10:03:55.793606 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip
13631 10:03:55.796226 No KMS driver or no outputs, pipes: 8, outputs: 0
13632 10:03:55.803121 [1mSubtest pipe-G-query-idle-hang: SKIP (0.000s)[0m
13633 10:03:55.811691 <14>[ 31.772833] [IGT] kms_vblank: executing
13634 10:03:55.818364 IGT-Version: 1.2<14>[ 31.777595] [IGT] kms_vblank: exiting, ret=77
13635 10:03:55.821649 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13636 10:03:55.831934 Opened devi<8>[ 31.788736] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked RESULT=skip>
13637 10:03:55.832022 ce: /dev/dri/card0
13638 10:03:55.832262 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked RESULT=skip
13640 10:03:55.835394 No KMS driver or no outputs, pipes: 8, outputs: 0
13641 10:03:55.841736 [1mSubtest pipe-G-query-forked: SKIP (0.000s)[0m
13642 10:03:55.848429 <14>[ 31.808607] [IGT] kms_vblank: executing
13643 10:03:55.851502 IGT-Version: 1.2<14>[ 31.813367] [IGT] kms_vblank: exiting, ret=77
13644 10:03:55.858147 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13645 10:03:55.868394 Opened device: /dev/dri/car<8>[ 31.824780] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip>
13646 10:03:55.868490 d0
13647 10:03:55.868731 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip
13649 10:03:55.871973 No KMS driver or no outputs, pipes: 8, outputs: 0
13650 10:03:55.877868 [1mSubtest pipe-G-query-forked-hang: SKIP (0.000s)[0m
13651 10:03:55.885430 <14>[ 31.846254] [IGT] kms_vblank: executing
13652 10:03:55.891749 IGT-Version: 1.2<14>[ 31.850981] [IGT] kms_vblank: exiting, ret=77
13653 10:03:55.895389 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13654 10:03:55.905067 Opened device: /dev/dri/car<8>[ 31.863246] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy RESULT=skip>
13655 10:03:55.905157 d0
13656 10:03:55.905398 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy RESULT=skip
13658 10:03:55.908393 No KMS driver or no outputs, pipes: 8, outputs: 0
13659 10:03:55.915164 [1mSubtest pipe-G-query-busy: SKIP (0.000s)[0m
13660 10:03:55.922575 <14>[ 31.883318] [IGT] kms_vblank: executing
13661 10:03:55.929078 IGT-Version: 1.2<14>[ 31.888057] [IGT] kms_vblank: exiting, ret=77
13662 10:03:55.932139 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13663 10:03:55.942494 Opened device: /dev/dri/car<8>[ 31.899745] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip>
13664 10:03:55.942581 d0
13665 10:03:55.942821 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip
13667 10:03:55.948835 No KMS driver or no outputs, pipes: 8, outputs: 0
13668 10:03:55.952422 [1mSubtest pipe-G-query-busy-hang: SKIP (0.000s)[0m
13669 10:03:55.963438 <14>[ 31.923967] [IGT] kms_vblank: executing
13670 10:03:55.969638 IGT-Version: 1.2<14>[ 31.928808] [IGT] kms_vblank: exiting, ret=77
13671 10:03:55.973099 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13672 10:03:55.983507 Opened devi<8>[ 31.939817] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip>
13673 10:03:55.983755 ce: /dev/dri/card0
13674 10:03:55.984164 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip
13676 10:03:55.989546 No KMS driver or no outputs, pipes: 8, outputs: 0
13677 10:03:55.992788 [1mSubtest pipe-G-query-forked-busy: SKIP (0.000s)[0m
13678 10:03:55.999646 <14>[ 31.960462] [IGT] kms_vblank: executing
13679 10:03:56.005863 IGT-Version: 1.2<14>[ 31.965196] [IGT] kms_vblank: exiting, ret=77
13680 10:03:56.009436 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13681 10:03:56.019424 Opened device: /dev/dri/car<8>[ 31.976654] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip>
13682 10:03:56.019509 d0
13683 10:03:56.019747 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip
13685 10:03:56.026172 No KMS driver or no outputs, pipes: 8, outputs: 0
13686 10:03:56.029282 [1mSubtest pipe-G-query-forked-busy-hang: SKIP (0.000s)[0m
13687 10:03:56.040290 <14>[ 32.001228] [IGT] kms_vblank: executing
13688 10:03:56.046984 IGT-Version: 1.2<14>[ 32.006047] [IGT] kms_vblank: exiting, ret=77
13689 10:03:56.050466 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13690 10:03:56.056780 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle RESULT=skip
13692 10:03:56.060033 Opened devi<8>[ 32.017034] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle RESULT=skip>
13693 10:03:56.060117 ce: /dev/dri/card0
13694 10:03:56.063702 No KMS driver or no outputs, pipes: 8, outputs: 0
13695 10:03:56.070192 [1mSubtest pipe-G-wait-idle: SKIP (0.000s)[0m
13696 10:03:56.073447 <14>[ 32.036781] [IGT] kms_vblank: executing
13697 10:03:56.080307 IGT-Version: 1.2<14>[ 32.041512] [IGT] kms_vblank: exiting, ret=77
13698 10:03:56.087096 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13699 10:03:56.096630 Opened device: /dev/dri/car<8>[ 32.052821] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip>
13700 10:03:56.096714 d0
13701 10:03:56.096952 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip
13703 10:03:56.100578 No KMS driver or no outputs, pipes: 8, outputs: 0
13704 10:03:56.106841 [1mSubtest pipe-G-wait-idle-hang: SKIP (0.000s)[0m
13705 10:03:56.113122 <14>[ 32.073837] [IGT] kms_vblank: executing
13706 10:03:56.119805 IGT-Version: 1.2<14>[ 32.078764] [IGT] kms_vblank: exiting, ret=77
13707 10:03:56.123158 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13708 10:03:56.130174 Opened devi<8>[ 32.089130] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked RESULT=skip>
13709 10:03:56.130430 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked RESULT=skip
13711 10:03:56.133125 ce: /dev/dri/card0
13712 10:03:56.136489 No KMS driver or no outputs, pipes: 8, outputs: 0
13713 10:03:56.143144 [1mSubtest pipe-G-wait-forked: SKIP (0.000s)[0m
13714 10:03:56.146146 <14>[ 32.109791] [IGT] kms_vblank: executing
13715 10:03:56.152853 IGT-Version: 1.2<14>[ 32.114518] [IGT] kms_vblank: exiting, ret=77
13716 10:03:56.159818 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13717 10:03:56.166089 Opened devi<8>[ 32.124958] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip>
13718 10:03:56.166348 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip
13720 10:03:56.170043 ce: /dev/dri/card0
13721 10:03:56.173180 No KMS driver or no outputs, pipes: 8, outputs: 0
13722 10:03:56.179730 [1mSubtest pipe-G-wait-forked-hang: SKIP (0.000s)[0m
13723 10:03:56.183181 <14>[ 32.145404] [IGT] kms_vblank: executing
13724 10:03:56.189575 IGT-Version: 1.2<14>[ 32.150307] [IGT] kms_vblank: exiting, ret=77
13725 10:03:56.193030 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13726 10:03:56.202779 Opened devi<8>[ 32.160617] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy RESULT=skip>
13727 10:03:56.202924 ce: /dev/dri/card0
13728 10:03:56.203163 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy RESULT=skip
13730 10:03:56.209367 No KMS driver or no outputs, pipes: 8, outputs: 0
13731 10:03:56.213029 [1mSubtest pipe-G-wait-busy: SKIP (0.000s)[0m
13732 10:03:56.230904 <14>[ 32.191778] [IGT] kms_vblank: executing
13733 10:03:56.237392 IGT-Version: 1.2<14>[ 32.196927] [IGT] kms_vblank: exiting, ret=77
13734 10:03:56.240773 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13735 10:03:56.250428 Opened device: /dev/dri/car<8>[ 32.207940] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip>
13736 10:03:56.250512 d0
13737 10:03:56.250749 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip
13739 10:03:56.257382 No KMS driver or no outputs, pipes: 8, outputs: 0
13740 10:03:56.260797 [1mSubtest pipe-G-wait-busy-hang: SKIP (0.000s)[0m
13741 10:03:56.271497 <14>[ 32.232476] [IGT] kms_vblank: executing
13742 10:03:56.278199 IGT-Version: 1.2<14>[ 32.237215] [IGT] kms_vblank: exiting, ret=77
13743 10:03:56.281415 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13744 10:03:56.291546 Opened device: /dev/dri/car<8>[ 32.248515] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip>
13745 10:03:56.291630 d0
13746 10:03:56.291866 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip
13748 10:03:56.297823 No KMS driver or no outputs, pipes: 8, outputs: 0
13749 10:03:56.301188 [1mSubtest pipe-G-wait-forked-busy: SKIP (0.000s)[0m
13750 10:03:56.308481 <14>[ 32.269622] [IGT] kms_vblank: executing
13751 10:03:56.315360 IGT-Version: 1.2<14>[ 32.274453] [IGT] kms_vblank: exiting, ret=77
13752 10:03:56.318780 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13753 10:03:56.328802 Opened devi<8>[ 32.285590] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip>
13754 10:03:56.328886 ce: /dev/dri/card0
13755 10:03:56.329123 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip
13757 10:03:56.335153 No KMS driver or no outputs, pipes: 8, outputs: 0
13758 10:03:56.338526 [1mSubtest pipe-G-wait-forked-busy-hang: SKIP (0.000s)[0m
13759 10:03:56.345243 <14>[ 32.306325] [IGT] kms_vblank: executing
13760 10:03:56.352271 IGT-Version: 1.2<14>[ 32.311068] [IGT] kms_vblank: exiting, ret=77
13761 10:03:56.355131 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13762 10:03:56.365009 Opened devi<8>[ 32.321987] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip>
13763 10:03:56.365093 ce: /dev/dri/card0
13764 10:03:56.365330 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip
13766 10:03:56.371974 No KMS driver or no outputs, pipes: 8, outputs: 0
13767 10:03:56.374855 [1mSubtest pipe-G-ts-continuation-idle: SKIP (0.000s)[0m
13768 10:03:56.382087 <14>[ 32.342911] [IGT] kms_vblank: executing
13769 10:03:56.388758 IGT-Version: 1.2<14>[ 32.347670] [IGT] kms_vblank: exiting, ret=77
13770 10:03:56.392095 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13771 10:03:56.401962 Opened device: /dev/dri/car<8>[ 32.358916] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip>
13772 10:03:56.402048 d0
13773 10:03:56.402285 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip
13775 10:03:56.408254 No KMS driver or no outputs, pipes: 8, outputs: 0
13776 10:03:56.414819 [1mSubtest pipe-G-ts-continuation-idle-hang: SKIP (0.000s)[0m
13777 10:03:56.422477 <14>[ 32.383386] [IGT] kms_vblank: executing
13778 10:03:56.429043 IGT-Version: 1.2<14>[ 32.388170] [IGT] kms_vblank: exiting, ret=77
13779 10:03:56.432615 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13780 10:03:56.442516 Opened device: /dev/dri/car<8>[ 32.400680] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip>
13781 10:03:56.442602 d0
13782 10:03:56.442840 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip
13784 10:03:56.448915 No KMS driver or no outputs, pipes: 8, outputs: 0
13785 10:03:56.452123 [1mSubtest pipe-G-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13786 10:03:56.463539 <14>[ 32.424480] [IGT] kms_vblank: executing
13787 10:03:56.469885 IGT-Version: 1.2<14>[ 32.429305] [IGT] kms_vblank: exiting, ret=77
13788 10:03:56.473527 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13789 10:03:56.483780 Opened devi<8>[ 32.440530] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip>
13790 10:03:56.484037 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip
13792 10:03:56.486620 ce: /dev/dri/card0
13793 10:03:56.490142 No KMS driver or no outputs, pipes: 8, outputs: 0
13794 10:03:56.496844 [1mSubtest pipe-G-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13795 10:03:56.500163 <14>[ 32.461721] [IGT] kms_vblank: executing
13796 10:03:56.506650 IGT-Version: 1.2<14>[ 32.466517] [IGT] kms_vblank: exiting, ret=77
13797 10:03:56.509803 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13798 10:03:56.520175 Opened device: /dev/dri/car<8>[ 32.478710] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip>
13799 10:03:56.520431 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip
13801 10:03:56.523184 d0
13802 10:03:56.527018 No KMS driver or no outputs, pipes: 8, outputs: 0
13803 10:03:56.533104 [1mSubtest pipe-G-ts-continuation-suspend: SKIP (0.000s)[0m
13804 10:03:56.536725 <14>[ 32.499835] [IGT] kms_vblank: executing
13805 10:03:56.543284 IGT-Version: 1.2<14>[ 32.504615] [IGT] kms_vblank: exiting, ret=77
13806 10:03:56.549739 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13807 10:03:56.559715 Opened device: /dev/dri/car<8>[ 32.515961] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip>
13808 10:03:56.559800 d0
13809 10:03:56.560036 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip
13811 10:03:56.562904 No KMS driver or no outputs, pipes: 8, outputs: 0
13812 10:03:56.569819 [1mSubtest pipe-G-ts-continuation-modeset: SKIP (0.000s)[0m
13813 10:03:56.577024 <14>[ 32.537985] [IGT] kms_vblank: executing
13814 10:03:56.583597 IGT-Version: 1.2<14>[ 32.542712] [IGT] kms_vblank: exiting, ret=77
13815 10:03:56.586755 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13816 10:03:56.596990 Opened devi<8>[ 32.553794] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip>
13817 10:03:56.597246 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip
13819 10:03:56.600243 ce: /dev/dri/card0
13820 10:03:56.603567 No KMS driver or no outputs, pipes: 8, outputs: 0
13821 10:03:56.610417 [1mSubtest pipe-G-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13822 10:03:56.613512 <14>[ 32.575002] [IGT] kms_vblank: executing
13823 10:03:56.620578 IGT-Version: 1.2<14>[ 32.579885] [IGT] kms_vblank: exiting, ret=77
13824 10:03:56.623670 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13825 10:03:56.627204 Opened device: /dev/dri/card0
13826 10:03:56.637145 No KMS drive<8>[ 32.592665] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip>
13827 10:03:56.637446 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip
13829 10:03:56.640041 r or no outputs, pipes: 8, outputs: 0
13830 10:03:56.646994 [1mSubtest pipe-G-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13831 10:03:56.654694 <14>[ 32.615452] [IGT] kms_vblank: executing
13832 10:03:56.661660 IGT-Version: 1.2<14>[ 32.620182] [IGT] kms_vblank: exiting, ret=77
13833 10:03:56.664472 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13834 10:03:56.674508 Opened device: /dev/dri/car<8>[ 32.632455] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip>
13835 10:03:56.674763 d0
13836 10:03:56.675201 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip
13838 10:03:56.678028 No KMS driver or no outputs, pipes: 8, outputs: 0
13839 10:03:56.684531 [1mSubtest pipe-H-accuracy-idle: SKIP (0.000s)[0m
13840 10:03:56.694460 <14>[ 32.655091] [IGT] kms_vblank: executing
13841 10:03:56.701226 IGT-Version: 1.2<14>[ 32.659826] [IGT] kms_vblank: exiting, ret=77
13842 10:03:56.704069 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13843 10:03:56.714227 Opened device: /dev/dri/car<8>[ 32.671084] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle RESULT=skip>
13844 10:03:56.714613 d0
13845 10:03:56.715304 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle RESULT=skip
13847 10:03:56.717784 No KMS driver or no outputs, pipes: 8, outputs: 0
13848 10:03:56.724160 [1mSubtest pipe-H-query-idle: SKIP (0.000s)[0m
13849 10:03:56.735141 <14>[ 32.695555] [IGT] kms_vblank: executing
13850 10:03:56.741581 IGT-Version: 1.2<14>[ 32.700286] [IGT] kms_vblank: exiting, ret=77
13851 10:03:56.745175 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13852 10:03:56.754592 Opened device: /dev/dri/car<8>[ 32.711682] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip>
13853 10:03:56.755270 d0
13854 10:03:56.755914 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip
13856 10:03:56.761318 No KMS driver or no outputs, pipes: 8, outputs: 0
13857 10:03:56.764534 [1mSubtest pipe-H-query-idle-hang: SKIP (0.000s)[0m
13858 10:03:56.774711 <14>[ 32.735119] [IGT] kms_vblank: executing
13859 10:03:56.780990 IGT-Version: 1.2<14>[ 32.739898] [IGT] kms_vblank: exiting, ret=77
13860 10:03:56.784568 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13861 10:03:56.794344 Opened device: /dev/dri/car<8>[ 32.752225] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked RESULT=skip>
13862 10:03:56.794909 d0
13863 10:03:56.795592 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked RESULT=skip
13865 10:03:56.797799 No KMS driver or no outputs, pipes: 8, outputs: 0
13866 10:03:56.804299 [1mSubtest pipe-H-query-forked: SKIP (0.000s)[0m
13867 10:03:56.811830 <14>[ 32.772411] [IGT] kms_vblank: executing
13868 10:03:56.818067 IGT-Version: 1.2<14>[ 32.777144] [IGT] kms_vblank: exiting, ret=77
13869 10:03:56.821505 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13870 10:03:56.831583 Opened devi<8>[ 32.788257] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip>
13871 10:03:56.832093 ce: /dev/dri/card0
13872 10:03:56.832673 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip
13874 10:03:56.838283 No KMS driver or no outputs, pipes: 8, outputs: 0
13875 10:03:56.841854 [1mSubtest pipe-H-query-forked-hang: SKIP (0.000s)[0m
13876 10:03:56.850274 <14>[ 32.810905] [IGT] kms_vblank: executing
13877 10:03:56.856993 IGT-Version: 1.2<14>[ 32.815650] [IGT] kms_vblank: exiting, ret=77
13878 10:03:56.859872 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13879 10:03:56.870975 Opened device: /dev/dri/car<8>[ 32.826884] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy RESULT=skip>
13880 10:03:56.871625 d0
13881 10:03:56.872218 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy RESULT=skip
13883 10:03:56.873191 No KMS driver or no outputs, pipes: 8, outputs: 0
13884 10:03:56.880160 [1mSubtest pipe-H-query-busy: SKIP (0.000s)[0m
13885 10:03:56.890845 <14>[ 32.851323] [IGT] kms_vblank: executing
13886 10:03:56.897444 IGT-Version: 1.2<14>[ 32.856100] [IGT] kms_vblank: exiting, ret=77
13887 10:03:56.901007 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13888 10:03:56.910687 Opened devi<8>[ 32.867193] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip>
13889 10:03:56.911332 ce: /dev/dri/card0
13890 10:03:56.912062 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip
13892 10:03:56.917338 No KMS driver or no outputs, pipes: 8, outputs: 0
13893 10:03:56.920321 [1mSubtest pipe-H-query-busy-hang: SKIP (0.000s)[0m
13894 10:03:56.930025 <14>[ 32.890327] [IGT] kms_vblank: executing
13895 10:03:56.936545 IGT-Version: 1.2<14>[ 32.895051] [IGT] kms_vblank: exiting, ret=77
13896 10:03:56.939745 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13897 10:03:56.950214 Opened device: /dev/dri/car<8>[ 32.906311] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip>
13898 10:03:56.950709 d0
13899 10:03:56.951468 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip
13901 10:03:56.956522 No KMS driver or no outputs, pipes: 8, outputs: 0
13902 10:03:56.959308 [1mSubtest pipe-H-query-forked-busy: SKIP (0.000s)[0m
13903 10:03:56.967413 <14>[ 32.928150] [IGT] kms_vblank: executing
13904 10:03:56.974042 IGT-Version: 1.2<14>[ 32.932884] [IGT] kms_vblank: exiting, ret=77
13905 10:03:56.977359 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13906 10:03:56.987308 Opened devi<8>[ 32.943953] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip>
13907 10:03:56.987676 ce: /dev/dri/card0
13908 10:03:56.988210 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip
13910 10:03:56.994101 No KMS driver or no outputs, pipes: 8, outputs: 0
13911 10:03:56.997483 [1mSubtest pipe-H-query-forked-busy-hang: SKIP (0.000s)[0m
13912 10:03:57.004386 <14>[ 32.964947] [IGT] kms_vblank: executing
13913 10:03:57.011178 IGT-Version: 1.2<14>[ 32.969661] [IGT] kms_vblank: exiting, ret=77
13914 10:03:57.014525 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13915 10:03:57.020832 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle RESULT=skip
13917 10:03:57.024226 Opened devi<8>[ 32.980857] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle RESULT=skip>
13918 10:03:57.024685 ce: /dev/dri/card0
13919 10:03:57.027533 No KMS driver or no outputs, pipes: 8, outputs: 0
13920 10:03:57.034125 [1mSubtest pipe-H-wait-idle: SKIP (0.000s)[0m
13921 10:03:57.040831 <14>[ 33.000742] [IGT] kms_vblank: executing
13922 10:03:57.044118 IGT-Version: 1.2<14>[ 33.005502] [IGT] kms_vblank: exiting, ret=77
13923 10:03:57.050952 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13924 10:03:57.057794 Opened devi<8>[ 33.015766] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip>
13925 10:03:57.058715 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip
13927 10:03:57.060472 ce: /dev/dri/card0
13928 10:03:57.064317 No KMS driver or no outputs, pipes: 8, outputs: 0
13929 10:03:57.070907 [1mSubtest pipe-H-wait-idle-hang: SKIP (0.000s)[0m
13930 10:03:57.087414 <14>[ 33.047919] [IGT] kms_vblank: executing
13931 10:03:57.094482 IGT-Version: 1.2<14>[ 33.053043] [IGT] kms_vblank: exiting, ret=77
13932 10:03:57.097366 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13933 10:03:57.100714 Opened device: /dev/dri/card0
13934 10:03:57.107299 No KMS drive<8>[ 33.066237] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked RESULT=skip>
13935 10:03:57.108031 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked RESULT=skip
13937 10:03:57.111116 r or no outputs, pipes: 8, outputs: 0
13938 10:03:57.117438 [1mSubtest pipe-H-wait-forked: SKIP (0.000s)[0m
13939 10:03:57.127730 <14>[ 33.088469] [IGT] kms_vblank: executing
13940 10:03:57.134226 IGT-Version: 1.2<14>[ 33.093237] [IGT] kms_vblank: exiting, ret=77
13941 10:03:57.137746 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13942 10:03:57.148144 Opened devi<8>[ 33.104178] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip>
13943 10:03:57.148683 ce: /dev/dri/card0
13944 10:03:57.149298 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip
13946 10:03:57.154641 No KMS driver or no outputs, pipes: 8, outputs: 0
13947 10:03:57.158096 [1mSubtest pipe-H-wait-forked-hang: SKIP (0.000s)[0m
13948 10:03:57.164879 <14>[ 33.124815] [IGT] kms_vblank: executing
13949 10:03:57.167924 IGT-Version: 1.2<14>[ 33.129576] [IGT] kms_vblank: exiting, ret=77
13950 10:03:57.174443 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13951 10:03:57.177873 Opened device: /dev/dri/card0
13952 10:03:57.184051 No KMS drive<8>[ 33.142194] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy RESULT=skip>
13953 10:03:57.184752 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy RESULT=skip
13955 10:03:57.187645 r or no outputs, pipes: 8, outputs: 0
13956 10:03:57.194797 [1mSubtest pipe-H-wait-busy: SKIP (0.000s)[0m
13957 10:03:57.202619 <14>[ 33.163092] [IGT] kms_vblank: executing
13958 10:03:57.209030 IGT-Version: 1.2<14>[ 33.168043] [IGT] kms_vblank: exiting, ret=77
13959 10:03:57.212385 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13960 10:03:57.222003 Opened devi<8>[ 33.179167] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip>
13961 10:03:57.222492 ce: /dev/dri/card0
13962 10:03:57.223102 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip
13964 10:03:57.229161 No KMS driver or no outputs, pipes: 8, outputs: 0
13965 10:03:57.231980 [1mSubtest pipe-H-wait-busy-hang: SKIP (0.000s)[0m
13966 10:03:57.238699 <14>[ 33.199350] [IGT] kms_vblank: executing
13967 10:03:57.245772 IGT-Version: 1.2<14>[ 33.204119] [IGT] kms_vblank: exiting, ret=77
13968 10:03:57.249221 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13969 10:03:57.258856 Opened devi<8>[ 33.215337] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip>
13970 10:03:57.259296 ce: /dev/dri/card0
13971 10:03:57.259865 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip
13973 10:03:57.261791 No KMS driver or no outputs, pipes: 8, outputs: 0
13974 10:03:57.269159 [1mSubtest pipe-H-wait-forked-busy: SKIP (0.000s)[0m
13975 10:03:57.275239 <14>[ 33.235619] [IGT] kms_vblank: executing
13976 10:03:57.279128 IGT-Version: 1.2<14>[ 33.240369] [IGT] kms_vblank: exiting, ret=77
13977 10:03:57.285381 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13978 10:03:57.295312 Opened device: /dev/dri/car<8>[ 33.251798] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip>
13979 10:03:57.295757 d0
13980 10:03:57.296324 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip
13982 10:03:57.301975 No KMS driver or no outputs, pipes: 8, outputs: 0
13983 10:03:57.305383 [1mSubtest pipe-H-wait-forked-busy-hang: SKIP (0.000s)[0m
13984 10:03:57.322893 <14>[ 33.283549] [IGT] kms_vblank: executing
13985 10:03:57.329443 IGT-Version: 1.2<14>[ 33.288645] [IGT] kms_vblank: exiting, ret=77
13986 10:03:57.332555 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13987 10:03:57.343059 Opened devi<8>[ 33.299631] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip>
13988 10:03:57.343572 ce: /dev/dri/card0
13989 10:03:57.344154 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip
13991 10:03:57.349650 No KMS driver or no outputs, pipes: 8, outputs: 0
13992 10:03:57.352602 [1mSubtest pipe-H-ts-continuation-idle: SKIP (0.000s)[0m
13993 10:03:57.361142 <14>[ 33.321405] [IGT] kms_vblank: executing
13994 10:03:57.367504 IGT-Version: 1.2<14>[ 33.326285] [IGT] kms_vblank: exiting, ret=77
13995 10:03:57.370816 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13996 10:03:57.380401 Opened devi<8>[ 33.337180] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip>
13997 10:03:57.380799 ce: /dev/dri/card0
13998 10:03:57.381371 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip
14000 10:03:57.387472 No KMS driver or no outputs, pipes: 8, outputs: 0
14001 10:03:57.390324 [1mSubtest pipe-H-ts-continuation-idle-hang: SKIP (0.000s)[0m
14002 10:03:57.398109 <14>[ 33.358583] [IGT] kms_vblank: executing
14003 10:03:57.404791 IGT-Version: 1.2<14>[ 33.363347] [IGT] kms_vblank: exiting, ret=77
14004 10:03:57.407446 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
14005 10:03:57.417445 Opened device: /dev/dri/car<8>[ 33.374714] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip>
14006 10:03:57.417941 d0
14007 10:03:57.418575 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip
14009 10:03:57.424369 No KMS driver or no outputs, pipes: 8, outputs: 0
14010 10:03:57.427331 [1mSubtest pipe-H-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
14011 10:03:57.439373 <14>[ 33.399981] [IGT] kms_vblank: executing
14012 10:03:57.445958 IGT-Version: 1.2<14>[ 33.404715] [IGT] kms_vblank: exiting, ret=77
14013 10:03:57.449333 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
14014 10:03:57.458926 Opened devi<8>[ 33.415861] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip>
14015 10:03:57.459690 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip
14017 10:03:57.462423 ce: /dev/dri/card0
14018 10:03:57.466061 No KMS driver or no outputs, pipes: 8, outputs: 0
14019 10:03:57.472376 [1mSubtest pipe-H-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
14020 10:03:57.475742 <14>[ 33.437263] [IGT] kms_vblank: executing
14021 10:03:57.482418 IGT-Version: 1.2<14>[ 33.442062] [IGT] kms_vblank: exiting, ret=77
14022 10:03:57.485944 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
14023 10:03:57.495307 Opened devi<8>[ 33.453184] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip>
14024 10:03:57.495962 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip
14026 10:03:57.498765 ce: /dev/dri/card0
14027 10:03:57.502396 No KMS driver or no outputs, pipes: 8, outputs: 0
14028 10:03:57.508989 [1mSubtest pipe-H-ts-continuation-suspend: SKIP (0.000s)[0m
14029 10:03:57.516074 <14>[ 33.476807] [IGT] kms_vblank: executing
14030 10:03:57.522506 IGT-Version: 1.2<14>[ 33.481557] [IGT] kms_vblank: exiting, ret=77
14031 10:03:57.526099 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
14032 10:03:57.536120 Opened device: /dev/dri/car<8>[ 33.492987] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip>
14033 10:03:57.536518 d0
14034 10:03:57.537076 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip
14036 10:03:57.542355 No KMS driver or no outputs, pipes: 8, outputs: 0
14037 10:03:57.546182 [1mSubtest pipe-H-ts-continuation-modeset: SKIP (0.000s)[0m
14038 10:03:57.553848 <14>[ 33.514663] [IGT] kms_vblank: executing
14039 10:03:57.560829 IGT-Version: 1.2<14>[ 33.519447] [IGT] kms_vblank: exiting, ret=77
14040 10:03:57.563626 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
14041 10:03:57.573989 Opened device: /dev/dri/car<8>[ 33.530837] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip>
14042 10:03:57.574694 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip
14044 10:03:57.577486 d0
14045 10:03:57.580378 No KMS driver or no outputs, pipes: 8, outputs: 0
14046 10:03:57.587062 [1mSubtest pipe-H-ts-continuation-modeset-hang: SKIP (0.000s)[0m
14047 10:03:57.590382 <14>[ 33.553712] [IGT] kms_vblank: executing
14048 10:03:57.597252 IGT-Version: 1.2<14>[ 33.558573] [IGT] kms_vblank: exiting, ret=77
14049 10:03:57.604168 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
14050 10:03:57.613605 Opened device: /dev/dri/car<8>[ 33.570782] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip>
14051 10:03:57.614003 d0
14052 10:03:57.614565 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip
14054 10:03:57.620714 No KMS driver or no outputs,<8>[ 33.581480] <LAVA_SIGNAL_TESTSET STOP>
14055 10:03:57.621374 Received signal: <TESTSET> STOP
14056 10:03:57.621706 Closing test_set kms_vblank
14057 10:03:57.630784 pipes: 8, outpu<8>[ 33.587700] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 12073323_1.5.2.3.1>
14058 10:03:57.631360 ts: 0
14059 10:03:57.631942 Received signal: <ENDRUN> 0_igt-kms-mediatek 12073323_1.5.2.3.1
14060 10:03:57.632355 Ending use of test pattern.
14061 10:03:57.632664 Ending test lava.0_igt-kms-mediatek (12073323_1.5.2.3.1), duration 12.95
14063 10:03:57.637324 [1mSubtest pipe-H-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
14064 10:03:57.637725 + set +x
14065 10:03:57.638038 <LAVA_TEST_RUNNER EXIT>
14066 10:03:57.638576 ok: lava_test_shell seems to have completed
14067 10:03:57.656085 addfb25-4-tiled:
result: skip
set: kms_addfb_basic
addfb25-bad-modifier:
result: fail
set: kms_addfb_basic
addfb25-framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
addfb25-modifier-no-flag:
result: pass
set: kms_addfb_basic
addfb25-x-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-x-tiled-mismatch-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-small-legacy:
result: skip
set: kms_addfb_basic
addfb25-yf-tiled-legacy:
result: skip
set: kms_addfb_basic
atomic-invalid-params:
result: skip
set: kms_atomic
atomic_plane_damage:
result: skip
set: kms_atomic
bad-pitch-0:
result: pass
set: kms_addfb_basic
bad-pitch-1024:
result: pass
set: kms_addfb_basic
bad-pitch-128:
result: pass
set: kms_addfb_basic
bad-pitch-256:
result: pass
set: kms_addfb_basic
bad-pitch-32:
result: pass
set: kms_addfb_basic
bad-pitch-63:
result: pass
set: kms_addfb_basic
bad-pitch-65536:
result: pass
set: kms_addfb_basic
bad-pitch-999:
result: pass
set: kms_addfb_basic
basic:
result: skip
set: kms_setmode
basic-auth:
result: pass
set: core_auth
basic-clone-single-crtc:
result: skip
set: kms_setmode
basic-x-tiled-legacy:
result: skip
set: kms_addfb_basic
basic-y-tiled-legacy:
result: skip
set: kms_addfb_basic
blob-multiple:
result: pass
set: kms_prop_blob
blob-prop-core:
result: pass
set: kms_prop_blob
blob-prop-lifetime:
result: pass
set: kms_prop_blob
blob-prop-validate:
result: pass
set: kms_prop_blob
bo-too-small:
result: skip
set: kms_addfb_basic
bo-too-small-due-to-tiling:
result: skip
set: kms_addfb_basic
clobberred-modifier:
result: skip
set: kms_addfb_basic
clone-exclusive-crtc:
result: skip
set: kms_setmode
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
crtc-id:
result: skip
set: kms_vblank
crtc-invalid-params:
result: skip
set: kms_atomic
crtc-invalid-params-fence:
result: skip
set: kms_atomic
empty-block:
result: skip
set: drm_read
empty-nonblock:
result: skip
set: drm_read
fault-buffer:
result: skip
set: drm_read
framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
getclient-master-drop:
result: pass
set: core_auth
getclient-simple:
result: pass
set: core_auth
invalid:
result: skip
set: kms_vblank
invalid-buffer:
result: skip
set: drm_read
invalid-clone-exclusive-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc-stealing:
result: skip
set: kms_setmode
invalid-get-prop:
result: pass
set: kms_prop_blob
invalid-get-prop-any:
result: pass
set: kms_prop_blob
invalid-set-prop:
result: pass
set: kms_prop_blob
invalid-set-prop-any:
result: pass
set: kms_prop_blob
invalid-smem-bo-on-discrete:
result: skip
set: kms_addfb_basic
legacy-format:
result: pass
set: kms_addfb_basic
many-magics:
result: pass
set: core_auth
master-rmfb:
result: pass
set: kms_addfb_basic
no-handle:
result: pass
set: kms_addfb_basic
pipe-A-accuracy-idle:
result: skip
set: kms_vblank
pipe-A-query-busy:
result: skip
set: kms_vblank
pipe-A-query-busy-hang:
result: skip
set: kms_vblank
pipe-A-query-forked:
result: skip
set: kms_vblank
pipe-A-query-forked-busy:
result: skip
set: kms_vblank
pipe-A-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-A-query-forked-hang:
result: skip
set: kms_vblank
pipe-A-query-idle:
result: skip
set: kms_vblank
pipe-A-query-idle-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-A-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-A-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-A-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-A-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-A-wait-busy:
result: skip
set: kms_vblank
pipe-A-wait-busy-hang:
result: skip
set: kms_vblank
pipe-A-wait-forked:
result: skip
set: kms_vblank
pipe-A-wait-forked-busy:
result: skip
set: kms_vblank
pipe-A-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-A-wait-forked-hang:
result: skip
set: kms_vblank
pipe-A-wait-idle:
result: skip
set: kms_vblank
pipe-A-wait-idle-hang:
result: skip
set: kms_vblank
pipe-B-accuracy-idle:
result: skip
set: kms_vblank
pipe-B-query-busy:
result: skip
set: kms_vblank
pipe-B-query-busy-hang:
result: skip
set: kms_vblank
pipe-B-query-forked:
result: skip
set: kms_vblank
pipe-B-query-forked-busy:
result: skip
set: kms_vblank
pipe-B-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-B-query-forked-hang:
result: skip
set: kms_vblank
pipe-B-query-idle:
result: skip
set: kms_vblank
pipe-B-query-idle-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-B-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-B-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-B-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-B-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-B-wait-busy:
result: skip
set: kms_vblank
pipe-B-wait-busy-hang:
result: skip
set: kms_vblank
pipe-B-wait-forked:
result: skip
set: kms_vblank
pipe-B-wait-forked-busy:
result: skip
set: kms_vblank
pipe-B-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-B-wait-forked-hang:
result: skip
set: kms_vblank
pipe-B-wait-idle:
result: skip
set: kms_vblank
pipe-B-wait-idle-hang:
result: skip
set: kms_vblank
pipe-C-accuracy-idle:
result: skip
set: kms_vblank
pipe-C-query-busy:
result: skip
set: kms_vblank
pipe-C-query-busy-hang:
result: skip
set: kms_vblank
pipe-C-query-forked:
result: skip
set: kms_vblank
pipe-C-query-forked-busy:
result: skip
set: kms_vblank
pipe-C-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-C-query-forked-hang:
result: skip
set: kms_vblank
pipe-C-query-idle:
result: skip
set: kms_vblank
pipe-C-query-idle-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-C-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-C-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-C-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-C-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-C-wait-busy:
result: skip
set: kms_vblank
pipe-C-wait-busy-hang:
result: skip
set: kms_vblank
pipe-C-wait-forked:
result: skip
set: kms_vblank
pipe-C-wait-forked-busy:
result: skip
set: kms_vblank
pipe-C-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-C-wait-forked-hang:
result: skip
set: kms_vblank
pipe-C-wait-idle:
result: skip
set: kms_vblank
pipe-C-wait-idle-hang:
result: skip
set: kms_vblank
pipe-D-accuracy-idle:
result: skip
set: kms_vblank
pipe-D-query-busy:
result: skip
set: kms_vblank
pipe-D-query-busy-hang:
result: skip
set: kms_vblank
pipe-D-query-forked:
result: skip
set: kms_vblank
pipe-D-query-forked-busy:
result: skip
set: kms_vblank
pipe-D-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-D-query-forked-hang:
result: skip
set: kms_vblank
pipe-D-query-idle:
result: skip
set: kms_vblank
pipe-D-query-idle-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-D-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-D-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-D-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-D-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-D-wait-busy:
result: skip
set: kms_vblank
pipe-D-wait-busy-hang:
result: skip
set: kms_vblank
pipe-D-wait-forked:
result: skip
set: kms_vblank
pipe-D-wait-forked-busy:
result: skip
set: kms_vblank
pipe-D-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-D-wait-forked-hang:
result: skip
set: kms_vblank
pipe-D-wait-idle:
result: skip
set: kms_vblank
pipe-D-wait-idle-hang:
result: skip
set: kms_vblank
pipe-E-accuracy-idle:
result: skip
set: kms_vblank
pipe-E-query-busy:
result: skip
set: kms_vblank
pipe-E-query-busy-hang:
result: skip
set: kms_vblank
pipe-E-query-forked:
result: skip
set: kms_vblank
pipe-E-query-forked-busy:
result: skip
set: kms_vblank
pipe-E-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-E-query-forked-hang:
result: skip
set: kms_vblank
pipe-E-query-idle:
result: skip
set: kms_vblank
pipe-E-query-idle-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-E-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-E-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-E-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-E-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-E-wait-busy:
result: skip
set: kms_vblank
pipe-E-wait-busy-hang:
result: skip
set: kms_vblank
pipe-E-wait-forked:
result: skip
set: kms_vblank
pipe-E-wait-forked-busy:
result: skip
set: kms_vblank
pipe-E-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-E-wait-forked-hang:
result: skip
set: kms_vblank
pipe-E-wait-idle:
result: skip
set: kms_vblank
pipe-E-wait-idle-hang:
result: skip
set: kms_vblank
pipe-F-accuracy-idle:
result: skip
set: kms_vblank
pipe-F-query-busy:
result: skip
set: kms_vblank
pipe-F-query-busy-hang:
result: skip
set: kms_vblank
pipe-F-query-forked:
result: skip
set: kms_vblank
pipe-F-query-forked-busy:
result: skip
set: kms_vblank
pipe-F-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-F-query-forked-hang:
result: skip
set: kms_vblank
pipe-F-query-idle:
result: skip
set: kms_vblank
pipe-F-query-idle-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-F-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-F-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-F-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-F-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-F-wait-busy:
result: skip
set: kms_vblank
pipe-F-wait-busy-hang:
result: skip
set: kms_vblank
pipe-F-wait-forked:
result: skip
set: kms_vblank
pipe-F-wait-forked-busy:
result: skip
set: kms_vblank
pipe-F-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-F-wait-forked-hang:
result: skip
set: kms_vblank
pipe-F-wait-idle:
result: skip
set: kms_vblank
pipe-F-wait-idle-hang:
result: skip
set: kms_vblank
pipe-G-accuracy-idle:
result: skip
set: kms_vblank
pipe-G-query-busy:
result: skip
set: kms_vblank
pipe-G-query-busy-hang:
result: skip
set: kms_vblank
pipe-G-query-forked:
result: skip
set: kms_vblank
pipe-G-query-forked-busy:
result: skip
set: kms_vblank
pipe-G-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-G-query-forked-hang:
result: skip
set: kms_vblank
pipe-G-query-idle:
result: skip
set: kms_vblank
pipe-G-query-idle-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-G-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-G-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-G-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-G-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-G-wait-busy:
result: skip
set: kms_vblank
pipe-G-wait-busy-hang:
result: skip
set: kms_vblank
pipe-G-wait-forked:
result: skip
set: kms_vblank
pipe-G-wait-forked-busy:
result: skip
set: kms_vblank
pipe-G-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-G-wait-forked-hang:
result: skip
set: kms_vblank
pipe-G-wait-idle:
result: skip
set: kms_vblank
pipe-G-wait-idle-hang:
result: skip
set: kms_vblank
pipe-H-accuracy-idle:
result: skip
set: kms_vblank
pipe-H-query-busy:
result: skip
set: kms_vblank
pipe-H-query-busy-hang:
result: skip
set: kms_vblank
pipe-H-query-forked:
result: skip
set: kms_vblank
pipe-H-query-forked-busy:
result: skip
set: kms_vblank
pipe-H-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-H-query-forked-hang:
result: skip
set: kms_vblank
pipe-H-query-idle:
result: skip
set: kms_vblank
pipe-H-query-idle-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-H-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-H-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-H-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-H-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-H-wait-busy:
result: skip
set: kms_vblank
pipe-H-wait-busy-hang:
result: skip
set: kms_vblank
pipe-H-wait-forked:
result: skip
set: kms_vblank
pipe-H-wait-forked-busy:
result: skip
set: kms_vblank
pipe-H-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-H-wait-forked-hang:
result: skip
set: kms_vblank
pipe-H-wait-idle:
result: skip
set: kms_vblank
pipe-H-wait-idle-hang:
result: skip
set: kms_vblank
plane-cursor-legacy:
result: skip
set: kms_atomic
plane-immutable-zpos:
result: skip
set: kms_atomic
plane-invalid-params:
result: skip
set: kms_atomic
plane-invalid-params-fence:
result: skip
set: kms_atomic
plane-overlay-legacy:
result: skip
set: kms_atomic
plane-primary-legacy:
result: skip
set: kms_atomic
plane-primary-overlay-mutable-zpos:
result: skip
set: kms_atomic
short-buffer-block:
result: skip
set: drm_read
short-buffer-nonblock:
result: skip
set: drm_read
short-buffer-wakeup:
result: skip
set: drm_read
size-max:
result: skip
set: kms_addfb_basic
small-bo:
result: skip
set: kms_addfb_basic
test-only:
result: skip
set: kms_atomic
tile-pitch-mismatch:
result: skip
set: kms_addfb_basic
too-high:
result: skip
set: kms_addfb_basic
too-wide:
result: skip
set: kms_addfb_basic
unused-handle:
result: pass
set: kms_addfb_basic
unused-modifier:
result: pass
set: kms_addfb_basic
unused-offsets:
result: pass
set: kms_addfb_basic
unused-pitches:
result: pass
set: kms_addfb_basic
14068 10:03:57.657146 end: 3.1 lava-test-shell (duration 00:00:13) [common]
14069 10:03:57.657560 end: 3 lava-test-retry (duration 00:00:13) [common]
14070 10:03:57.657968 start: 4 finalize (timeout 00:07:10) [common]
14071 10:03:57.658393 start: 4.1 power-off (timeout 00:00:30) [common]
14072 10:03:57.659064 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
14073 10:03:57.766091 >> Command sent successfully.
14074 10:03:57.776597 Returned 0 in 0 seconds
14075 10:03:57.877916 end: 4.1 power-off (duration 00:00:00) [common]
14077 10:03:57.879420 start: 4.2 read-feedback (timeout 00:07:10) [common]
14078 10:03:57.880670 Listened to connection for namespace 'common' for up to 1s
14079 10:03:57.881493 Listened to connection for namespace 'common' for up to 1s
14080 10:03:58.881299 Finalising connection for namespace 'common'
14081 10:03:58.881942 Disconnecting from shell: Finalise
14082 10:03:58.882313 / #
14083 10:03:58.983308 end: 4.2 read-feedback (duration 00:00:01) [common]
14084 10:03:58.983991 end: 4 finalize (duration 00:00:01) [common]
14085 10:03:58.984555 Cleaning after the job
14086 10:03:58.985043 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073323/tftp-deploy-3pqnrf9v/ramdisk
14087 10:03:59.017591 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073323/tftp-deploy-3pqnrf9v/kernel
14088 10:03:59.034473 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073323/tftp-deploy-3pqnrf9v/dtb
14089 10:03:59.034742 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073323/tftp-deploy-3pqnrf9v/modules
14090 10:03:59.044631 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12073323
14091 10:03:59.162418 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12073323
14092 10:03:59.162602 Job finished correctly