Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 42
- Kernel Warnings: 31
- Boot result: PASS
- Errors: 0
1 10:00:29.528329 lava-dispatcher, installed at version: 2023.10
2 10:00:29.528572 start: 0 validate
3 10:00:29.528715 Start time: 2023-11-24 10:00:29.528706+00:00 (UTC)
4 10:00:29.528846 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:00:29.528981 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 10:00:29.803057 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:00:29.803235 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:00:30.069872 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:00:30.070073 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:00:30.336780 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:00:30.336966 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 10:00:30.594842 Using caching service: 'http://localhost/cache/?uri=%s'
13 10:00:30.595032 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 10:00:30.862159 validate duration: 1.33
16 10:00:30.862465 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 10:00:30.862592 start: 1.1 download-retry (timeout 00:10:00) [common]
18 10:00:30.862709 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 10:00:30.862885 Not decompressing ramdisk as can be used compressed.
20 10:00:30.862993 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230623.0/arm64/initrd.cpio.gz
21 10:00:30.863086 saving as /var/lib/lava/dispatcher/tmp/12073315/tftp-deploy-ahuft4sa/ramdisk/initrd.cpio.gz
22 10:00:30.863155 total size: 5625687 (5 MB)
23 10:00:30.867487 progress 0 % (0 MB)
24 10:00:30.868962 progress 5 % (0 MB)
25 10:00:30.870673 progress 10 % (0 MB)
26 10:00:30.872083 progress 15 % (0 MB)
27 10:00:30.873717 progress 20 % (1 MB)
28 10:00:30.875119 progress 25 % (1 MB)
29 10:00:30.876726 progress 30 % (1 MB)
30 10:00:30.878345 progress 35 % (1 MB)
31 10:00:30.879752 progress 40 % (2 MB)
32 10:00:30.881322 progress 45 % (2 MB)
33 10:00:30.882795 progress 50 % (2 MB)
34 10:00:30.884371 progress 55 % (2 MB)
35 10:00:30.886033 progress 60 % (3 MB)
36 10:00:30.887468 progress 65 % (3 MB)
37 10:00:30.889047 progress 70 % (3 MB)
38 10:00:30.890558 progress 75 % (4 MB)
39 10:00:30.892142 progress 80 % (4 MB)
40 10:00:30.893718 progress 85 % (4 MB)
41 10:00:30.895371 progress 90 % (4 MB)
42 10:00:30.896942 progress 95 % (5 MB)
43 10:00:30.898457 progress 100 % (5 MB)
44 10:00:30.898711 5 MB downloaded in 0.04 s (150.95 MB/s)
45 10:00:30.898893 end: 1.1.1 http-download (duration 00:00:00) [common]
47 10:00:30.899182 end: 1.1 download-retry (duration 00:00:00) [common]
48 10:00:30.899297 start: 1.2 download-retry (timeout 00:10:00) [common]
49 10:00:30.899407 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 10:00:30.899584 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 10:00:30.899671 saving as /var/lib/lava/dispatcher/tmp/12073315/tftp-deploy-ahuft4sa/kernel/Image
52 10:00:30.899733 total size: 49107456 (46 MB)
53 10:00:30.899824 No compression specified
54 10:00:30.900941 progress 0 % (0 MB)
55 10:00:30.913739 progress 5 % (2 MB)
56 10:00:30.926794 progress 10 % (4 MB)
57 10:00:30.939888 progress 15 % (7 MB)
58 10:00:30.953103 progress 20 % (9 MB)
59 10:00:30.966235 progress 25 % (11 MB)
60 10:00:30.979105 progress 30 % (14 MB)
61 10:00:30.991957 progress 35 % (16 MB)
62 10:00:31.004828 progress 40 % (18 MB)
63 10:00:31.017608 progress 45 % (21 MB)
64 10:00:31.030487 progress 50 % (23 MB)
65 10:00:31.043398 progress 55 % (25 MB)
66 10:00:31.056270 progress 60 % (28 MB)
67 10:00:31.069304 progress 65 % (30 MB)
68 10:00:31.082348 progress 70 % (32 MB)
69 10:00:31.095011 progress 75 % (35 MB)
70 10:00:31.107808 progress 80 % (37 MB)
71 10:00:31.120481 progress 85 % (39 MB)
72 10:00:31.133256 progress 90 % (42 MB)
73 10:00:31.145815 progress 95 % (44 MB)
74 10:00:31.158478 progress 100 % (46 MB)
75 10:00:31.158719 46 MB downloaded in 0.26 s (180.83 MB/s)
76 10:00:31.158874 end: 1.2.1 http-download (duration 00:00:00) [common]
78 10:00:31.159104 end: 1.2 download-retry (duration 00:00:00) [common]
79 10:00:31.159195 start: 1.3 download-retry (timeout 00:10:00) [common]
80 10:00:31.159281 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 10:00:31.159423 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 10:00:31.159492 saving as /var/lib/lava/dispatcher/tmp/12073315/tftp-deploy-ahuft4sa/dtb/mt8192-asurada-spherion-r0.dtb
83 10:00:31.159552 total size: 47278 (0 MB)
84 10:00:31.159614 No compression specified
85 10:00:31.160765 progress 69 % (0 MB)
86 10:00:31.161044 progress 100 % (0 MB)
87 10:00:31.161246 0 MB downloaded in 0.00 s (26.66 MB/s)
88 10:00:31.161367 end: 1.3.1 http-download (duration 00:00:00) [common]
90 10:00:31.161669 end: 1.3 download-retry (duration 00:00:00) [common]
91 10:00:31.161758 start: 1.4 download-retry (timeout 00:10:00) [common]
92 10:00:31.161842 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 10:00:31.161957 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 10:00:31.162024 saving as /var/lib/lava/dispatcher/tmp/12073315/tftp-deploy-ahuft4sa/nfsrootfs/full.rootfs.tar
95 10:00:31.162084 total size: 195204440 (186 MB)
96 10:00:31.162146 Using unxz to decompress xz
97 10:00:31.169803 progress 0 % (0 MB)
98 10:00:31.722908 progress 5 % (9 MB)
99 10:00:32.215959 progress 10 % (18 MB)
100 10:00:32.802618 progress 15 % (27 MB)
101 10:00:33.079433 progress 20 % (37 MB)
102 10:00:33.534718 progress 25 % (46 MB)
103 10:00:34.098850 progress 30 % (55 MB)
104 10:00:34.650980 progress 35 % (65 MB)
105 10:00:35.226491 progress 40 % (74 MB)
106 10:00:35.790803 progress 45 % (83 MB)
107 10:00:36.389966 progress 50 % (93 MB)
108 10:00:36.988599 progress 55 % (102 MB)
109 10:00:37.637647 progress 60 % (111 MB)
110 10:00:38.022226 progress 65 % (121 MB)
111 10:00:38.104680 progress 70 % (130 MB)
112 10:00:38.246487 progress 75 % (139 MB)
113 10:00:38.326842 progress 80 % (148 MB)
114 10:00:38.372976 progress 85 % (158 MB)
115 10:00:38.463988 progress 90 % (167 MB)
116 10:00:38.842877 progress 95 % (176 MB)
117 10:00:39.414614 progress 100 % (186 MB)
118 10:00:39.419612 186 MB downloaded in 8.26 s (22.54 MB/s)
119 10:00:39.419872 end: 1.4.1 http-download (duration 00:00:08) [common]
121 10:00:39.420139 end: 1.4 download-retry (duration 00:00:08) [common]
122 10:00:39.420228 start: 1.5 download-retry (timeout 00:09:51) [common]
123 10:00:39.420316 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 10:00:39.420481 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 10:00:39.420557 saving as /var/lib/lava/dispatcher/tmp/12073315/tftp-deploy-ahuft4sa/modules/modules.tar
126 10:00:39.420639 total size: 8622040 (8 MB)
127 10:00:39.420745 Using unxz to decompress xz
128 10:00:39.424802 progress 0 % (0 MB)
129 10:00:39.445876 progress 5 % (0 MB)
130 10:00:39.469461 progress 10 % (0 MB)
131 10:00:39.492824 progress 15 % (1 MB)
132 10:00:39.516006 progress 20 % (1 MB)
133 10:00:39.539705 progress 25 % (2 MB)
134 10:00:39.565687 progress 30 % (2 MB)
135 10:00:39.591853 progress 35 % (2 MB)
136 10:00:39.614907 progress 40 % (3 MB)
137 10:00:39.638934 progress 45 % (3 MB)
138 10:00:39.664167 progress 50 % (4 MB)
139 10:00:39.688778 progress 55 % (4 MB)
140 10:00:39.713593 progress 60 % (4 MB)
141 10:00:39.740658 progress 65 % (5 MB)
142 10:00:39.765304 progress 70 % (5 MB)
143 10:00:39.788512 progress 75 % (6 MB)
144 10:00:39.815460 progress 80 % (6 MB)
145 10:00:39.840671 progress 85 % (7 MB)
146 10:00:39.865720 progress 90 % (7 MB)
147 10:00:39.896086 progress 95 % (7 MB)
148 10:00:39.925840 progress 100 % (8 MB)
149 10:00:39.930593 8 MB downloaded in 0.51 s (16.12 MB/s)
150 10:00:39.930854 end: 1.5.1 http-download (duration 00:00:01) [common]
152 10:00:39.931148 end: 1.5 download-retry (duration 00:00:01) [common]
153 10:00:39.931257 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 10:00:39.931370 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 10:00:43.632543 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12073315/extract-nfsrootfs-ykqohhck
156 10:00:43.632768 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 10:00:43.632869 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 10:00:43.633050 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a
159 10:00:43.633187 makedir: /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a/lava-12073315/bin
160 10:00:43.633290 makedir: /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a/lava-12073315/tests
161 10:00:43.633390 makedir: /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a/lava-12073315/results
162 10:00:43.633501 Creating /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a/lava-12073315/bin/lava-add-keys
163 10:00:43.633653 Creating /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a/lava-12073315/bin/lava-add-sources
164 10:00:43.633784 Creating /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a/lava-12073315/bin/lava-background-process-start
165 10:00:43.633916 Creating /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a/lava-12073315/bin/lava-background-process-stop
166 10:00:43.634046 Creating /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a/lava-12073315/bin/lava-common-functions
167 10:00:43.634173 Creating /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a/lava-12073315/bin/lava-echo-ipv4
168 10:00:43.634300 Creating /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a/lava-12073315/bin/lava-install-packages
169 10:00:43.634427 Creating /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a/lava-12073315/bin/lava-installed-packages
170 10:00:43.634553 Creating /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a/lava-12073315/bin/lava-os-build
171 10:00:43.634680 Creating /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a/lava-12073315/bin/lava-probe-channel
172 10:00:43.634807 Creating /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a/lava-12073315/bin/lava-probe-ip
173 10:00:43.634933 Creating /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a/lava-12073315/bin/lava-target-ip
174 10:00:43.635059 Creating /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a/lava-12073315/bin/lava-target-mac
175 10:00:43.635186 Creating /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a/lava-12073315/bin/lava-target-storage
176 10:00:43.635315 Creating /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a/lava-12073315/bin/lava-test-case
177 10:00:43.635447 Creating /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a/lava-12073315/bin/lava-test-event
178 10:00:43.635574 Creating /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a/lava-12073315/bin/lava-test-feedback
179 10:00:43.635700 Creating /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a/lava-12073315/bin/lava-test-raise
180 10:00:43.635825 Creating /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a/lava-12073315/bin/lava-test-reference
181 10:00:43.635952 Creating /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a/lava-12073315/bin/lava-test-runner
182 10:00:43.636080 Creating /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a/lava-12073315/bin/lava-test-set
183 10:00:43.636213 Creating /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a/lava-12073315/bin/lava-test-shell
184 10:00:43.636341 Updating /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a/lava-12073315/bin/lava-add-keys (debian)
185 10:00:43.645518 Updating /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a/lava-12073315/bin/lava-add-sources (debian)
186 10:00:43.645736 Updating /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a/lava-12073315/bin/lava-install-packages (debian)
187 10:00:43.645888 Updating /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a/lava-12073315/bin/lava-installed-packages (debian)
188 10:00:43.646033 Updating /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a/lava-12073315/bin/lava-os-build (debian)
189 10:00:43.646160 Creating /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a/lava-12073315/environment
190 10:00:43.646274 LAVA metadata
191 10:00:43.646351 - LAVA_JOB_ID=12073315
192 10:00:43.646418 - LAVA_DISPATCHER_IP=192.168.201.1
193 10:00:43.646540 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 10:00:43.646609 skipped lava-vland-overlay
195 10:00:43.646687 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 10:00:43.646768 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 10:00:43.646829 skipped lava-multinode-overlay
198 10:00:43.646901 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 10:00:43.646981 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 10:00:43.647061 Loading test definitions
201 10:00:43.647150 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 10:00:43.647224 Using /lava-12073315 at stage 0
203 10:00:43.647514 uuid=12073315_1.6.2.3.1 testdef=None
204 10:00:43.647603 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 10:00:43.647689 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 10:00:43.648154 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 10:00:43.648435 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 10:00:43.648996 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 10:00:43.649228 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 10:00:43.675048 runner path: /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a/lava-12073315/0/tests/0_timesync-off test_uuid 12073315_1.6.2.3.1
213 10:00:43.675276 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 10:00:43.675512 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 10:00:43.675587 Using /lava-12073315 at stage 0
217 10:00:43.675692 Fetching tests from https://github.com/kernelci/test-definitions.git
218 10:00:43.675772 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a/lava-12073315/0/tests/1_kselftest-alsa'
219 10:00:50.086094 Running '/usr/bin/git checkout kernelci.org
220 10:00:50.165800 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a/lava-12073315/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 10:00:50.166587 uuid=12073315_1.6.2.3.5 testdef=None
222 10:00:50.166746 end: 1.6.2.3.5 git-repo-action (duration 00:00:06) [common]
224 10:00:50.167004 start: 1.6.2.3.6 test-overlay (timeout 00:09:41) [common]
225 10:00:50.167772 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 10:00:50.168002 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:41) [common]
228 10:00:50.168983 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 10:00:50.169217 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:41) [common]
231 10:00:50.170199 runner path: /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a/lava-12073315/0/tests/1_kselftest-alsa test_uuid 12073315_1.6.2.3.5
232 10:00:50.170293 BOARD='mt8192-asurada-spherion-r0'
233 10:00:50.170359 BRANCH='cip'
234 10:00:50.170419 SKIPFILE='/dev/null'
235 10:00:50.170477 SKIP_INSTALL='True'
236 10:00:50.170533 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 10:00:50.170591 TST_CASENAME=''
238 10:00:50.170645 TST_CMDFILES='alsa'
239 10:00:50.170788 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 10:00:50.170990 Creating lava-test-runner.conf files
242 10:00:50.171053 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12073315/lava-overlay-cl_vwc5a/lava-12073315/0 for stage 0
243 10:00:50.171146 - 0_timesync-off
244 10:00:50.171214 - 1_kselftest-alsa
245 10:00:50.171308 end: 1.6.2.3 test-definition (duration 00:00:07) [common]
246 10:00:50.171398 start: 1.6.2.4 compress-overlay (timeout 00:09:41) [common]
247 10:00:57.754685 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 10:00:57.754865 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:33) [common]
249 10:00:57.754956 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 10:00:57.755060 end: 1.6.2 lava-overlay (duration 00:00:14) [common]
251 10:00:57.755149 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:33) [common]
252 10:00:57.924606 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 10:00:57.924996 start: 1.6.4 extract-modules (timeout 00:09:33) [common]
254 10:00:57.925111 extracting modules file /var/lib/lava/dispatcher/tmp/12073315/tftp-deploy-ahuft4sa/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12073315/extract-nfsrootfs-ykqohhck
255 10:00:58.152416 extracting modules file /var/lib/lava/dispatcher/tmp/12073315/tftp-deploy-ahuft4sa/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12073315/extract-overlay-ramdisk-irj41_k4/ramdisk
256 10:00:58.385064 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 10:00:58.385219 start: 1.6.5 apply-overlay-tftp (timeout 00:09:32) [common]
258 10:00:58.385316 [common] Applying overlay to NFS
259 10:00:58.385387 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12073315/compress-overlay-zyz1925r/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12073315/extract-nfsrootfs-ykqohhck
260 10:00:59.315946 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 10:00:59.316116 start: 1.6.6 configure-preseed-file (timeout 00:09:32) [common]
262 10:00:59.316207 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 10:00:59.316295 start: 1.6.7 compress-ramdisk (timeout 00:09:32) [common]
264 10:00:59.316376 Building ramdisk /var/lib/lava/dispatcher/tmp/12073315/extract-overlay-ramdisk-irj41_k4/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12073315/extract-overlay-ramdisk-irj41_k4/ramdisk
265 10:00:59.665751 >> 130520 blocks
266 10:01:01.713292 rename /var/lib/lava/dispatcher/tmp/12073315/extract-overlay-ramdisk-irj41_k4/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12073315/tftp-deploy-ahuft4sa/ramdisk/ramdisk.cpio.gz
267 10:01:01.713783 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 10:01:01.713922 start: 1.6.8 prepare-kernel (timeout 00:09:29) [common]
269 10:01:01.714028 start: 1.6.8.1 prepare-fit (timeout 00:09:29) [common]
270 10:01:01.714158 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12073315/tftp-deploy-ahuft4sa/kernel/Image'
271 10:01:14.050668 Returned 0 in 12 seconds
272 10:01:14.151307 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12073315/tftp-deploy-ahuft4sa/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12073315/tftp-deploy-ahuft4sa/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12073315/tftp-deploy-ahuft4sa/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12073315/tftp-deploy-ahuft4sa/kernel/image.itb
273 10:01:14.515063 output: FIT description: Kernel Image image with one or more FDT blobs
274 10:01:14.515447 output: Created: Fri Nov 24 10:01:14 2023
275 10:01:14.515527 output: Image 0 (kernel-1)
276 10:01:14.515595 output: Description:
277 10:01:14.515659 output: Created: Fri Nov 24 10:01:14 2023
278 10:01:14.515718 output: Type: Kernel Image
279 10:01:14.515774 output: Compression: lzma compressed
280 10:01:14.515833 output: Data Size: 11047542 Bytes = 10788.62 KiB = 10.54 MiB
281 10:01:14.515889 output: Architecture: AArch64
282 10:01:14.515946 output: OS: Linux
283 10:01:14.516005 output: Load Address: 0x00000000
284 10:01:14.516065 output: Entry Point: 0x00000000
285 10:01:14.516124 output: Hash algo: crc32
286 10:01:14.516182 output: Hash value: 2edffaa3
287 10:01:14.516243 output: Image 1 (fdt-1)
288 10:01:14.516296 output: Description: mt8192-asurada-spherion-r0
289 10:01:14.516350 output: Created: Fri Nov 24 10:01:14 2023
290 10:01:14.516404 output: Type: Flat Device Tree
291 10:01:14.516457 output: Compression: uncompressed
292 10:01:14.516510 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 10:01:14.516563 output: Architecture: AArch64
294 10:01:14.516616 output: Hash algo: crc32
295 10:01:14.516669 output: Hash value: cc4352de
296 10:01:14.516724 output: Image 2 (ramdisk-1)
297 10:01:14.516791 output: Description: unavailable
298 10:01:14.516845 output: Created: Fri Nov 24 10:01:14 2023
299 10:01:14.516899 output: Type: RAMDisk Image
300 10:01:14.516952 output: Compression: Unknown Compression
301 10:01:14.517004 output: Data Size: 18762476 Bytes = 18322.73 KiB = 17.89 MiB
302 10:01:14.517058 output: Architecture: AArch64
303 10:01:14.517111 output: OS: Linux
304 10:01:14.517164 output: Load Address: unavailable
305 10:01:14.517237 output: Entry Point: unavailable
306 10:01:14.517321 output: Hash algo: crc32
307 10:01:14.517375 output: Hash value: 2a3172a1
308 10:01:14.517435 output: Default Configuration: 'conf-1'
309 10:01:14.517491 output: Configuration 0 (conf-1)
310 10:01:14.517559 output: Description: mt8192-asurada-spherion-r0
311 10:01:14.517612 output: Kernel: kernel-1
312 10:01:14.517664 output: Init Ramdisk: ramdisk-1
313 10:01:14.517717 output: FDT: fdt-1
314 10:01:14.517770 output: Loadables: kernel-1
315 10:01:14.517823 output:
316 10:01:14.518023 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 10:01:14.518120 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 10:01:14.518221 end: 1.6 prepare-tftp-overlay (duration 00:00:35) [common]
319 10:01:14.518317 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:16) [common]
320 10:01:14.518398 No LXC device requested
321 10:01:14.518476 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 10:01:14.518560 start: 1.8 deploy-device-env (timeout 00:09:16) [common]
323 10:01:14.518638 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 10:01:14.518711 Checking files for TFTP limit of 4294967296 bytes.
325 10:01:14.519207 end: 1 tftp-deploy (duration 00:00:44) [common]
326 10:01:14.519314 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 10:01:14.519407 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 10:01:14.519555 substitutions:
329 10:01:14.519640 - {DTB}: 12073315/tftp-deploy-ahuft4sa/dtb/mt8192-asurada-spherion-r0.dtb
330 10:01:14.519706 - {INITRD}: 12073315/tftp-deploy-ahuft4sa/ramdisk/ramdisk.cpio.gz
331 10:01:14.519766 - {KERNEL}: 12073315/tftp-deploy-ahuft4sa/kernel/Image
332 10:01:14.519823 - {LAVA_MAC}: None
333 10:01:14.519881 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12073315/extract-nfsrootfs-ykqohhck
334 10:01:14.519936 - {NFS_SERVER_IP}: 192.168.201.1
335 10:01:14.519991 - {PRESEED_CONFIG}: None
336 10:01:14.520047 - {PRESEED_LOCAL}: None
337 10:01:14.520102 - {RAMDISK}: 12073315/tftp-deploy-ahuft4sa/ramdisk/ramdisk.cpio.gz
338 10:01:14.520158 - {ROOT_PART}: None
339 10:01:14.520212 - {ROOT}: None
340 10:01:14.520266 - {SERVER_IP}: 192.168.201.1
341 10:01:14.520320 - {TEE}: None
342 10:01:14.520374 Parsed boot commands:
343 10:01:14.520427 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 10:01:14.520681 Parsed boot commands: tftpboot 192.168.201.1 12073315/tftp-deploy-ahuft4sa/kernel/image.itb 12073315/tftp-deploy-ahuft4sa/kernel/cmdline
345 10:01:14.520774 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 10:01:14.520897 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 10:01:14.521013 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 10:01:14.521106 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 10:01:14.521183 Not connected, no need to disconnect.
350 10:01:14.521274 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 10:01:14.521359 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 10:01:14.521450 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
353 10:01:14.525363 Setting prompt string to ['lava-test: # ']
354 10:01:14.525779 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 10:01:14.525891 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 10:01:14.525993 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 10:01:14.526094 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 10:01:14.526299 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
359 10:01:19.673383 >> Command sent successfully.
360 10:01:19.684139 Returned 0 in 5 seconds
361 10:01:19.785070 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 10:01:19.785540 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 10:01:19.785701 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 10:01:19.785837 Setting prompt string to 'Starting depthcharge on Spherion...'
366 10:01:19.785938 Changing prompt to 'Starting depthcharge on Spherion...'
367 10:01:19.786041 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 10:01:19.786434 [Enter `^Ec?' for help]
369 10:01:19.953658
370 10:01:19.954245
371 10:01:19.954665 F0: 102B 0000
372 10:01:19.955047
373 10:01:19.955387 F3: 1001 0000 [0200]
374 10:01:19.955793
375 10:01:19.957552 F3: 1001 0000
376 10:01:19.958003
377 10:01:19.958392 F7: 102D 0000
378 10:01:19.958718
379 10:01:19.959025 F1: 0000 0000
380 10:01:19.960614
381 10:01:19.961041 V0: 0000 0000 [0001]
382 10:01:19.961383
383 10:01:19.961770 00: 0007 8000
384 10:01:19.962103
385 10:01:19.963966 01: 0000 0000
386 10:01:19.964398
387 10:01:19.964738 BP: 0C00 0209 [0000]
388 10:01:19.965052
389 10:01:19.967456 G0: 1182 0000
390 10:01:19.967883
391 10:01:19.968223 EC: 0000 0021 [4000]
392 10:01:19.968540
393 10:01:19.970710 S7: 0000 0000 [0000]
394 10:01:19.971138
395 10:01:19.971478 CC: 0000 0000 [0001]
396 10:01:19.974343
397 10:01:19.974769 T0: 0000 0040 [010F]
398 10:01:19.975109
399 10:01:19.975425 Jump to BL
400 10:01:19.975730
401 10:01:20.000317
402 10:01:20.000849
403 10:01:20.001191
404 10:01:20.008068 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 10:01:20.011001 ARM64: Exception handlers installed.
406 10:01:20.014455 ARM64: Testing exception
407 10:01:20.018191 ARM64: Done test exception
408 10:01:20.025384 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 10:01:20.035109 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 10:01:20.042615 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 10:01:20.051863 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 10:01:20.059013 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 10:01:20.065203 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 10:01:20.077178 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 10:01:20.083683 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 10:01:20.103672 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 10:01:20.106964 WDT: Last reset was cold boot
418 10:01:20.109692 SPI1(PAD0) initialized at 2873684 Hz
419 10:01:20.113230 SPI5(PAD0) initialized at 992727 Hz
420 10:01:20.116642 VBOOT: Loading verstage.
421 10:01:20.123008 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 10:01:20.126330 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 10:01:20.130060 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 10:01:20.133103 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 10:01:20.141663 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 10:01:20.147170 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 10:01:20.158323 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 10:01:20.158811
429 10:01:20.159184
430 10:01:20.168470 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 10:01:20.171663 ARM64: Exception handlers installed.
432 10:01:20.175556 ARM64: Testing exception
433 10:01:20.176145 ARM64: Done test exception
434 10:01:20.181767 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 10:01:20.185200 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 10:01:20.199205 Probing TPM: . done!
437 10:01:20.199773 TPM ready after 0 ms
438 10:01:20.206009 Connected to device vid:did:rid of 1ae0:0028:00
439 10:01:20.216158 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 10:01:20.254789 Initialized TPM device CR50 revision 0
441 10:01:20.265921 tlcl_send_startup: Startup return code is 0
442 10:01:20.266613 TPM: setup succeeded
443 10:01:20.277469 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 10:01:20.286137 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 10:01:20.296691 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 10:01:20.304815 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 10:01:20.308975 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 10:01:20.311681 in-header: 03 07 00 00 08 00 00 00
449 10:01:20.315194 in-data: aa e4 47 04 13 02 00 00
450 10:01:20.318463 Chrome EC: UHEPI supported
451 10:01:20.325322 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 10:01:20.328439 in-header: 03 ad 00 00 08 00 00 00
453 10:01:20.331724 in-data: 00 20 20 08 00 00 00 00
454 10:01:20.332292 Phase 1
455 10:01:20.334862 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 10:01:20.341255 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 10:01:20.348585 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 10:01:20.351187 Recovery requested (1009000e)
459 10:01:20.355836 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 10:01:20.364109 tlcl_extend: response is 0
461 10:01:20.374238 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 10:01:20.377276 tlcl_extend: response is 0
463 10:01:20.384202 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 10:01:20.405397 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 10:01:20.411446 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 10:01:20.412014
467 10:01:20.412386
468 10:01:20.422305 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 10:01:20.425738 ARM64: Exception handlers installed.
470 10:01:20.426359 ARM64: Testing exception
471 10:01:20.428655 ARM64: Done test exception
472 10:01:20.450396 pmic_efuse_setting: Set efuses in 11 msecs
473 10:01:20.454323 pmwrap_interface_init: Select PMIF_VLD_RDY
474 10:01:20.457682 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 10:01:20.464143 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 10:01:20.467381 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 10:01:20.474300 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 10:01:20.478001 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 10:01:20.485094 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 10:01:20.488066 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 10:01:20.491310 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 10:01:20.498174 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 10:01:20.501877 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 10:01:20.508047 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 10:01:20.511312 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 10:01:20.514852 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 10:01:20.521495 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 10:01:20.528276 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 10:01:20.534790 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 10:01:20.538737 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 10:01:20.544578 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 10:01:20.551357 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 10:01:20.557891 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 10:01:20.561189 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 10:01:20.569103 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 10:01:20.572107 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 10:01:20.579815 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 10:01:20.583299 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 10:01:20.589641 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 10:01:20.592953 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 10:01:20.600036 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 10:01:20.603664 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 10:01:20.610659 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 10:01:20.613672 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 10:01:20.617460 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 10:01:20.623680 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 10:01:20.630634 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 10:01:20.634193 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 10:01:20.640580 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 10:01:20.644748 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 10:01:20.648142 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 10:01:20.655416 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 10:01:20.658668 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 10:01:20.661952 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 10:01:20.665273 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 10:01:20.672014 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 10:01:20.675741 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 10:01:20.678336 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 10:01:20.685043 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 10:01:20.688588 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 10:01:20.691344 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 10:01:20.698370 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 10:01:20.701924 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 10:01:20.705380 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 10:01:20.711452 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 10:01:20.721700 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 10:01:20.725062 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 10:01:20.735141 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 10:01:20.741202 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 10:01:20.748097 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 10:01:20.752526 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 10:01:20.754737 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 10:01:20.763104 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x0
534 10:01:20.769506 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 10:01:20.773320 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
536 10:01:20.776658 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 10:01:20.787235 [RTC]rtc_get_frequency_meter,154: input=15, output=836
538 10:01:20.797190 [RTC]rtc_get_frequency_meter,154: input=7, output=709
539 10:01:20.806225 [RTC]rtc_get_frequency_meter,154: input=11, output=771
540 10:01:20.816147 [RTC]rtc_get_frequency_meter,154: input=13, output=803
541 10:01:20.825360 [RTC]rtc_get_frequency_meter,154: input=12, output=786
542 10:01:20.835132 [RTC]rtc_get_frequency_meter,154: input=12, output=788
543 10:01:20.843937 [RTC]rtc_get_frequency_meter,154: input=13, output=803
544 10:01:20.847490 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
545 10:01:20.854825 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
546 10:01:20.857748 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 10:01:20.861126 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 10:01:20.868385 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 10:01:20.871428 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 10:01:20.874135 ADC[4]: Raw value=905988 ID=7
551 10:01:20.874564 ADC[3]: Raw value=214021 ID=1
552 10:01:20.877989 RAM Code: 0x71
553 10:01:20.880855 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 10:01:20.887483 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 10:01:20.894082 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 10:01:20.901267 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 10:01:20.904266 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 10:01:20.908370 in-header: 03 07 00 00 08 00 00 00
559 10:01:20.912040 in-data: aa e4 47 04 13 02 00 00
560 10:01:20.914231 Chrome EC: UHEPI supported
561 10:01:20.921051 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 10:01:20.924444 in-header: 03 dd 00 00 08 00 00 00
563 10:01:20.927634 in-data: 90 20 60 08 00 00 00 00
564 10:01:20.931062 MRC: failed to locate region type 0.
565 10:01:20.937867 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 10:01:20.941302 DRAM-K: Running full calibration
567 10:01:20.947846 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 10:01:20.948435 header.status = 0x0
569 10:01:20.951011 header.version = 0x6 (expected: 0x6)
570 10:01:20.954090 header.size = 0xd00 (expected: 0xd00)
571 10:01:20.957702 header.flags = 0x0
572 10:01:20.964354 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 10:01:20.981001 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 10:01:20.987829 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 10:01:20.991784 dram_init: ddr_geometry: 2
576 10:01:20.994141 [EMI] MDL number = 2
577 10:01:20.994607 [EMI] Get MDL freq = 0
578 10:01:20.997388 dram_init: ddr_type: 0
579 10:01:20.997885 is_discrete_lpddr4: 1
580 10:01:21.001084 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 10:01:21.001703
582 10:01:21.004298
583 10:01:21.004863 [Bian_co] ETT version 0.0.0.1
584 10:01:21.010460 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 10:01:21.010927
586 10:01:21.013995 dramc_set_vcore_voltage set vcore to 650000
587 10:01:21.017551 Read voltage for 800, 4
588 10:01:21.018124 Vio18 = 0
589 10:01:21.018575 Vcore = 650000
590 10:01:21.020829 Vdram = 0
591 10:01:21.021395 Vddq = 0
592 10:01:21.021838 Vmddr = 0
593 10:01:21.023853 dram_init: config_dvfs: 1
594 10:01:21.028108 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 10:01:21.033988 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 10:01:21.037762 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
597 10:01:21.040238 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
598 10:01:21.043822 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
599 10:01:21.050263 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
600 10:01:21.050690 MEM_TYPE=3, freq_sel=18
601 10:01:21.053435 sv_algorithm_assistance_LP4_1600
602 10:01:21.056906 ============ PULL DRAM RESETB DOWN ============
603 10:01:21.064005 ========== PULL DRAM RESETB DOWN end =========
604 10:01:21.067319 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 10:01:21.070336 ===================================
606 10:01:21.074346 LPDDR4 DRAM CONFIGURATION
607 10:01:21.077139 ===================================
608 10:01:21.077603 EX_ROW_EN[0] = 0x0
609 10:01:21.080288 EX_ROW_EN[1] = 0x0
610 10:01:21.080709 LP4Y_EN = 0x0
611 10:01:21.083506 WORK_FSP = 0x0
612 10:01:21.084030 WL = 0x2
613 10:01:21.086840 RL = 0x2
614 10:01:21.087262 BL = 0x2
615 10:01:21.090873 RPST = 0x0
616 10:01:21.093296 RD_PRE = 0x0
617 10:01:21.093792 WR_PRE = 0x1
618 10:01:21.097359 WR_PST = 0x0
619 10:01:21.097816 DBI_WR = 0x0
620 10:01:21.099901 DBI_RD = 0x0
621 10:01:21.100321 OTF = 0x1
622 10:01:21.104123 ===================================
623 10:01:21.107088 ===================================
624 10:01:21.110054 ANA top config
625 10:01:21.113794 ===================================
626 10:01:21.114321 DLL_ASYNC_EN = 0
627 10:01:21.117952 ALL_SLAVE_EN = 1
628 10:01:21.120647 NEW_RANK_MODE = 1
629 10:01:21.123651 DLL_IDLE_MODE = 1
630 10:01:21.124076 LP45_APHY_COMB_EN = 1
631 10:01:21.127000 TX_ODT_DIS = 1
632 10:01:21.130153 NEW_8X_MODE = 1
633 10:01:21.134032 ===================================
634 10:01:21.137312 ===================================
635 10:01:21.140488 data_rate = 1600
636 10:01:21.144191 CKR = 1
637 10:01:21.144721 DQ_P2S_RATIO = 8
638 10:01:21.146695 ===================================
639 10:01:21.150541 CA_P2S_RATIO = 8
640 10:01:21.153557 DQ_CA_OPEN = 0
641 10:01:21.156669 DQ_SEMI_OPEN = 0
642 10:01:21.159949 CA_SEMI_OPEN = 0
643 10:01:21.163506 CA_FULL_RATE = 0
644 10:01:21.163929 DQ_CKDIV4_EN = 1
645 10:01:21.166816 CA_CKDIV4_EN = 1
646 10:01:21.170467 CA_PREDIV_EN = 0
647 10:01:21.173259 PH8_DLY = 0
648 10:01:21.177287 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 10:01:21.180467 DQ_AAMCK_DIV = 4
650 10:01:21.181002 CA_AAMCK_DIV = 4
651 10:01:21.184000 CA_ADMCK_DIV = 4
652 10:01:21.187188 DQ_TRACK_CA_EN = 0
653 10:01:21.189903 CA_PICK = 800
654 10:01:21.193157 CA_MCKIO = 800
655 10:01:21.196791 MCKIO_SEMI = 0
656 10:01:21.199915 PLL_FREQ = 3068
657 10:01:21.200442 DQ_UI_PI_RATIO = 32
658 10:01:21.203189 CA_UI_PI_RATIO = 0
659 10:01:21.206556 ===================================
660 10:01:21.210249 ===================================
661 10:01:21.213580 memory_type:LPDDR4
662 10:01:21.217221 GP_NUM : 10
663 10:01:21.217838 SRAM_EN : 1
664 10:01:21.220240 MD32_EN : 0
665 10:01:21.223303 ===================================
666 10:01:21.223729 [ANA_INIT] >>>>>>>>>>>>>>
667 10:01:21.226424 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 10:01:21.230014 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 10:01:21.233598 ===================================
670 10:01:21.236547 data_rate = 1600,PCW = 0X7600
671 10:01:21.241116 ===================================
672 10:01:21.243344 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 10:01:21.250154 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 10:01:21.253627 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 10:01:21.259954 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 10:01:21.263668 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 10:01:21.266299 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 10:01:21.269937 [ANA_INIT] flow start
679 10:01:21.270365 [ANA_INIT] PLL >>>>>>>>
680 10:01:21.273274 [ANA_INIT] PLL <<<<<<<<
681 10:01:21.276715 [ANA_INIT] MIDPI >>>>>>>>
682 10:01:21.277270 [ANA_INIT] MIDPI <<<<<<<<
683 10:01:21.279975 [ANA_INIT] DLL >>>>>>>>
684 10:01:21.283177 [ANA_INIT] flow end
685 10:01:21.287040 ============ LP4 DIFF to SE enter ============
686 10:01:21.289855 ============ LP4 DIFF to SE exit ============
687 10:01:21.292894 [ANA_INIT] <<<<<<<<<<<<<
688 10:01:21.296292 [Flow] Enable top DCM control >>>>>
689 10:01:21.300053 [Flow] Enable top DCM control <<<<<
690 10:01:21.303014 Enable DLL master slave shuffle
691 10:01:21.306318 ==============================================================
692 10:01:21.309488 Gating Mode config
693 10:01:21.316503 ==============================================================
694 10:01:21.317032 Config description:
695 10:01:21.326034 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 10:01:21.332896 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 10:01:21.339902 SELPH_MODE 0: By rank 1: By Phase
698 10:01:21.342816 ==============================================================
699 10:01:21.346144 GAT_TRACK_EN = 1
700 10:01:21.349528 RX_GATING_MODE = 2
701 10:01:21.353292 RX_GATING_TRACK_MODE = 2
702 10:01:21.355976 SELPH_MODE = 1
703 10:01:21.359699 PICG_EARLY_EN = 1
704 10:01:21.362779 VALID_LAT_VALUE = 1
705 10:01:21.366058 ==============================================================
706 10:01:21.369971 Enter into Gating configuration >>>>
707 10:01:21.373100 Exit from Gating configuration <<<<
708 10:01:21.375837 Enter into DVFS_PRE_config >>>>>
709 10:01:21.385637 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 10:01:21.389630 Exit from DVFS_PRE_config <<<<<
711 10:01:21.392561 Enter into PICG configuration >>>>
712 10:01:21.395831 Exit from PICG configuration <<<<
713 10:01:21.399414 [RX_INPUT] configuration >>>>>
714 10:01:21.402459 [RX_INPUT] configuration <<<<<
715 10:01:21.409691 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 10:01:21.413280 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 10:01:21.420312 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 10:01:21.427189 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 10:01:21.430994 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 10:01:21.437604 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 10:01:21.441524 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 10:01:21.445073 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 10:01:21.448577 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 10:01:21.456257 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 10:01:21.459558 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 10:01:21.463825 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 10:01:21.467958 ===================================
728 10:01:21.468238 LPDDR4 DRAM CONFIGURATION
729 10:01:21.470986 ===================================
730 10:01:21.474228 EX_ROW_EN[0] = 0x0
731 10:01:21.474489 EX_ROW_EN[1] = 0x0
732 10:01:21.477907 LP4Y_EN = 0x0
733 10:01:21.478155 WORK_FSP = 0x0
734 10:01:21.481445 WL = 0x2
735 10:01:21.481751 RL = 0x2
736 10:01:21.486048 BL = 0x2
737 10:01:21.486581 RPST = 0x0
738 10:01:21.489268 RD_PRE = 0x0
739 10:01:21.489759 WR_PRE = 0x1
740 10:01:21.492570 WR_PST = 0x0
741 10:01:21.492999 DBI_WR = 0x0
742 10:01:21.496432 DBI_RD = 0x0
743 10:01:21.496863 OTF = 0x1
744 10:01:21.501047 ===================================
745 10:01:21.503697 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 10:01:21.507734 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 10:01:21.511612 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 10:01:21.514621 ===================================
749 10:01:21.518103 LPDDR4 DRAM CONFIGURATION
750 10:01:21.521880 ===================================
751 10:01:21.522459 EX_ROW_EN[0] = 0x10
752 10:01:21.525533 EX_ROW_EN[1] = 0x0
753 10:01:21.525964 LP4Y_EN = 0x0
754 10:01:21.529579 WORK_FSP = 0x0
755 10:01:21.530164 WL = 0x2
756 10:01:21.532792 RL = 0x2
757 10:01:21.533356 BL = 0x2
758 10:01:21.536704 RPST = 0x0
759 10:01:21.537148 RD_PRE = 0x0
760 10:01:21.540355 WR_PRE = 0x1
761 10:01:21.540800 WR_PST = 0x0
762 10:01:21.543868 DBI_WR = 0x0
763 10:01:21.544299 DBI_RD = 0x0
764 10:01:21.547290 OTF = 0x1
765 10:01:21.551590 ===================================
766 10:01:21.554869 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 10:01:21.559552 nWR fixed to 40
768 10:01:21.559986 [ModeRegInit_LP4] CH0 RK0
769 10:01:21.563549 [ModeRegInit_LP4] CH0 RK1
770 10:01:21.567040 [ModeRegInit_LP4] CH1 RK0
771 10:01:21.567582 [ModeRegInit_LP4] CH1 RK1
772 10:01:21.570353 match AC timing 13
773 10:01:21.574150 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 10:01:21.577529 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 10:01:21.583981 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 10:01:21.587975 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 10:01:21.591270 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 10:01:21.594882 [EMI DOE] emi_dcm 0
779 10:01:21.598282 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 10:01:21.598713 ==
781 10:01:21.601254 Dram Type= 6, Freq= 0, CH_0, rank 0
782 10:01:21.604878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 10:01:21.608252 ==
784 10:01:21.611307 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 10:01:21.617661 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 10:01:21.627172 [CA 0] Center 37 (7~68) winsize 62
787 10:01:21.629796 [CA 1] Center 37 (6~68) winsize 63
788 10:01:21.633820 [CA 2] Center 34 (4~65) winsize 62
789 10:01:21.637259 [CA 3] Center 34 (4~65) winsize 62
790 10:01:21.639989 [CA 4] Center 33 (3~64) winsize 62
791 10:01:21.643830 [CA 5] Center 33 (3~64) winsize 62
792 10:01:21.644430
793 10:01:21.647042 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 10:01:21.647477
795 10:01:21.650540 [CATrainingPosCal] consider 1 rank data
796 10:01:21.653697 u2DelayCellTimex100 = 270/100 ps
797 10:01:21.656975 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 10:01:21.660314 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 10:01:21.663732 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 10:01:21.670229 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 10:01:21.673717 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 10:01:21.676968 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 10:01:21.677596
804 10:01:21.680242 CA PerBit enable=1, Macro0, CA PI delay=33
805 10:01:21.680802
806 10:01:21.684455 [CBTSetCACLKResult] CA Dly = 33
807 10:01:21.684888 CS Dly: 7 (0~38)
808 10:01:21.685406 ==
809 10:01:21.686735 Dram Type= 6, Freq= 0, CH_0, rank 1
810 10:01:21.693442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 10:01:21.693890 ==
812 10:01:21.696453 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 10:01:21.703575 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 10:01:21.712950 [CA 0] Center 37 (6~68) winsize 63
815 10:01:21.716351 [CA 1] Center 37 (7~68) winsize 62
816 10:01:21.719478 [CA 2] Center 34 (4~65) winsize 62
817 10:01:21.722771 [CA 3] Center 34 (4~65) winsize 62
818 10:01:21.725975 [CA 4] Center 33 (3~64) winsize 62
819 10:01:21.729478 [CA 5] Center 33 (2~64) winsize 63
820 10:01:21.729929
821 10:01:21.732933 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 10:01:21.733575
823 10:01:21.736089 [CATrainingPosCal] consider 2 rank data
824 10:01:21.739527 u2DelayCellTimex100 = 270/100 ps
825 10:01:21.742743 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 10:01:21.749312 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 10:01:21.753058 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 10:01:21.756344 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 10:01:21.760296 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 10:01:21.764655 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 10:01:21.765077
832 10:01:21.767511 CA PerBit enable=1, Macro0, CA PI delay=33
833 10:01:21.767945
834 10:01:21.771757 [CBTSetCACLKResult] CA Dly = 33
835 10:01:21.772220 CS Dly: 7 (0~39)
836 10:01:21.772606
837 10:01:21.774725 ----->DramcWriteLeveling(PI) begin...
838 10:01:21.775172 ==
839 10:01:21.778365 Dram Type= 6, Freq= 0, CH_0, rank 0
840 10:01:21.781777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 10:01:21.782392 ==
842 10:01:21.785204 Write leveling (Byte 0): 32 => 32
843 10:01:21.788370 Write leveling (Byte 1): 32 => 32
844 10:01:21.792400 DramcWriteLeveling(PI) end<-----
845 10:01:21.792497
846 10:01:21.792567 ==
847 10:01:21.794981 Dram Type= 6, Freq= 0, CH_0, rank 0
848 10:01:21.798523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 10:01:21.798606 ==
850 10:01:21.801750 [Gating] SW mode calibration
851 10:01:21.807943 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 10:01:21.814861 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 10:01:21.817859 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 10:01:21.821790 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
855 10:01:21.828138 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
856 10:01:21.831383 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 10:01:21.834687 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 10:01:21.841672 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 10:01:21.845475 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 10:01:21.848328 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 10:01:21.854745 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 10:01:21.858252 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 10:01:21.861806 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 10:01:21.868554 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 10:01:21.871391 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 10:01:21.874645 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 10:01:21.881474 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 10:01:21.884584 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 10:01:21.887880 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 10:01:21.891230 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 10:01:21.898210 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
872 10:01:21.901524 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 10:01:21.905079 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 10:01:21.911236 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 10:01:21.915019 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 10:01:21.918322 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 10:01:21.924394 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 10:01:21.928111 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 10:01:21.931383 0 9 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
880 10:01:21.938292 0 9 12 | B1->B0 | 2e2d 3434 | 1 1 | (1 1) (1 1)
881 10:01:21.941131 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 10:01:21.945229 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 10:01:21.951823 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 10:01:21.954809 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 10:01:21.958255 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 10:01:21.964935 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
887 10:01:21.968207 0 10 8 | B1->B0 | 3333 2828 | 0 0 | (0 0) (1 0)
888 10:01:21.972079 0 10 12 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)
889 10:01:21.978003 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 10:01:21.982216 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 10:01:21.984828 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 10:01:21.991492 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 10:01:21.994994 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 10:01:21.997992 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
895 10:01:22.005185 0 11 8 | B1->B0 | 2525 3c3c | 0 0 | (0 0) (0 0)
896 10:01:22.007817 0 11 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
897 10:01:22.011535 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 10:01:22.017819 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 10:01:22.021079 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 10:01:22.025005 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 10:01:22.031085 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 10:01:22.034888 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 10:01:22.037785 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
904 10:01:22.044351 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
905 10:01:22.047574 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 10:01:22.051282 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 10:01:22.054645 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 10:01:22.060946 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 10:01:22.063984 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 10:01:22.067423 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 10:01:22.074764 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 10:01:22.077577 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 10:01:22.081698 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 10:01:22.088588 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 10:01:22.092001 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 10:01:22.096203 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 10:01:22.099567 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 10:01:22.103440 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 10:01:22.110921 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
920 10:01:22.111351 Total UI for P1: 0, mck2ui 16
921 10:01:22.114614 best dqsien dly found for B0: ( 0, 14, 6)
922 10:01:22.118419 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
923 10:01:22.126293 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
924 10:01:22.126730 Total UI for P1: 0, mck2ui 16
925 10:01:22.129724 best dqsien dly found for B1: ( 0, 14, 12)
926 10:01:22.132821 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
927 10:01:22.136437 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
928 10:01:22.136905
929 10:01:22.143276 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
930 10:01:22.147715 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
931 10:01:22.148146 [Gating] SW calibration Done
932 10:01:22.148486 ==
933 10:01:22.150327 Dram Type= 6, Freq= 0, CH_0, rank 0
934 10:01:22.157351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 10:01:22.157857 ==
936 10:01:22.158261 RX Vref Scan: 0
937 10:01:22.158608
938 10:01:22.159788 RX Vref 0 -> 0, step: 1
939 10:01:22.160099
940 10:01:22.163366 RX Delay -130 -> 252, step: 16
941 10:01:22.167240 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
942 10:01:22.169522 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
943 10:01:22.173042 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
944 10:01:22.179943 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
945 10:01:22.183119 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
946 10:01:22.186324 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
947 10:01:22.190787 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
948 10:01:22.194205 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
949 10:01:22.198245 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
950 10:01:22.201366 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
951 10:01:22.204706 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
952 10:01:22.208699 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
953 10:01:22.215612 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
954 10:01:22.219057 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
955 10:01:22.222280 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
956 10:01:22.225703 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
957 10:01:22.225858 ==
958 10:01:22.228600 Dram Type= 6, Freq= 0, CH_0, rank 0
959 10:01:22.235044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 10:01:22.235201 ==
961 10:01:22.235323 DQS Delay:
962 10:01:22.238745 DQS0 = 0, DQS1 = 0
963 10:01:22.238828 DQM Delay:
964 10:01:22.238895 DQM0 = 85, DQM1 = 71
965 10:01:22.241909 DQ Delay:
966 10:01:22.245323 DQ0 =85, DQ1 =93, DQ2 =77, DQ3 =77
967 10:01:22.248524 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =101
968 10:01:22.251684 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
969 10:01:22.254815 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
970 10:01:22.254898
971 10:01:22.254965
972 10:01:22.255026 ==
973 10:01:22.258387 Dram Type= 6, Freq= 0, CH_0, rank 0
974 10:01:22.261887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
975 10:01:22.261965 ==
976 10:01:22.262030
977 10:01:22.262090
978 10:01:22.265648 TX Vref Scan disable
979 10:01:22.265750 == TX Byte 0 ==
980 10:01:22.271554 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
981 10:01:22.275138 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
982 10:01:22.275227 == TX Byte 1 ==
983 10:01:22.281511 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
984 10:01:22.284647 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
985 10:01:22.284768 ==
986 10:01:22.288595 Dram Type= 6, Freq= 0, CH_0, rank 0
987 10:01:22.291466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 10:01:22.291590 ==
989 10:01:22.305693 TX Vref=22, minBit 4, minWin=27, winSum=443
990 10:01:22.309297 TX Vref=24, minBit 5, minWin=27, winSum=446
991 10:01:22.312402 TX Vref=26, minBit 5, minWin=27, winSum=446
992 10:01:22.315593 TX Vref=28, minBit 8, minWin=27, winSum=448
993 10:01:22.319185 TX Vref=30, minBit 8, minWin=27, winSum=445
994 10:01:22.322577 TX Vref=32, minBit 4, minWin=27, winSum=444
995 10:01:22.329129 [TxChooseVref] Worse bit 8, Min win 27, Win sum 448, Final Vref 28
996 10:01:22.329467
997 10:01:22.332452 Final TX Range 1 Vref 28
998 10:01:22.332754
999 10:01:22.332993 ==
1000 10:01:22.335467 Dram Type= 6, Freq= 0, CH_0, rank 0
1001 10:01:22.338672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1002 10:01:22.338978 ==
1003 10:01:22.339220
1004 10:01:22.341848
1005 10:01:22.341929 TX Vref Scan disable
1006 10:01:22.345251 == TX Byte 0 ==
1007 10:01:22.348444 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1008 10:01:22.355012 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1009 10:01:22.355095 == TX Byte 1 ==
1010 10:01:22.358870 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1011 10:01:22.365257 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1012 10:01:22.365341
1013 10:01:22.365450 [DATLAT]
1014 10:01:22.365514 Freq=800, CH0 RK0
1015 10:01:22.365575
1016 10:01:22.368934 DATLAT Default: 0xa
1017 10:01:22.369016 0, 0xFFFF, sum = 0
1018 10:01:22.372491 1, 0xFFFF, sum = 0
1019 10:01:22.372577 2, 0xFFFF, sum = 0
1020 10:01:22.375913 3, 0xFFFF, sum = 0
1021 10:01:22.375996 4, 0xFFFF, sum = 0
1022 10:01:22.378866 5, 0xFFFF, sum = 0
1023 10:01:22.381869 6, 0xFFFF, sum = 0
1024 10:01:22.381953 7, 0xFFFF, sum = 0
1025 10:01:22.385021 8, 0xFFFF, sum = 0
1026 10:01:22.385106 9, 0x0, sum = 1
1027 10:01:22.385172 10, 0x0, sum = 2
1028 10:01:22.388434 11, 0x0, sum = 3
1029 10:01:22.388516 12, 0x0, sum = 4
1030 10:01:22.392046 best_step = 10
1031 10:01:22.392132
1032 10:01:22.392201 ==
1033 10:01:22.395467 Dram Type= 6, Freq= 0, CH_0, rank 0
1034 10:01:22.398460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1035 10:01:22.398557 ==
1036 10:01:22.402039 RX Vref Scan: 1
1037 10:01:22.402140
1038 10:01:22.402220 Set Vref Range= 32 -> 127
1039 10:01:22.405100
1040 10:01:22.405209 RX Vref 32 -> 127, step: 1
1041 10:01:22.405297
1042 10:01:22.409018 RX Delay -111 -> 252, step: 8
1043 10:01:22.409162
1044 10:01:22.412072 Set Vref, RX VrefLevel [Byte0]: 32
1045 10:01:22.415132 [Byte1]: 32
1046 10:01:22.415266
1047 10:01:22.418331 Set Vref, RX VrefLevel [Byte0]: 33
1048 10:01:22.422091 [Byte1]: 33
1049 10:01:22.426872
1050 10:01:22.427022 Set Vref, RX VrefLevel [Byte0]: 34
1051 10:01:22.429393 [Byte1]: 34
1052 10:01:22.433799
1053 10:01:22.433949 Set Vref, RX VrefLevel [Byte0]: 35
1054 10:01:22.436943 [Byte1]: 35
1055 10:01:22.440881
1056 10:01:22.440961 Set Vref, RX VrefLevel [Byte0]: 36
1057 10:01:22.445024 [Byte1]: 36
1058 10:01:22.448917
1059 10:01:22.452342 Set Vref, RX VrefLevel [Byte0]: 37
1060 10:01:22.455571 [Byte1]: 37
1061 10:01:22.455652
1062 10:01:22.458373 Set Vref, RX VrefLevel [Byte0]: 38
1063 10:01:22.461722 [Byte1]: 38
1064 10:01:22.461803
1065 10:01:22.465348 Set Vref, RX VrefLevel [Byte0]: 39
1066 10:01:22.468578 [Byte1]: 39
1067 10:01:22.471485
1068 10:01:22.471559 Set Vref, RX VrefLevel [Byte0]: 40
1069 10:01:22.474818 [Byte1]: 40
1070 10:01:22.479503
1071 10:01:22.479585 Set Vref, RX VrefLevel [Byte0]: 41
1072 10:01:22.482933 [Byte1]: 41
1073 10:01:22.486795
1074 10:01:22.486876 Set Vref, RX VrefLevel [Byte0]: 42
1075 10:01:22.490871 [Byte1]: 42
1076 10:01:22.494625
1077 10:01:22.494706 Set Vref, RX VrefLevel [Byte0]: 43
1078 10:01:22.497954 [Byte1]: 43
1079 10:01:22.502496
1080 10:01:22.502583 Set Vref, RX VrefLevel [Byte0]: 44
1081 10:01:22.505767 [Byte1]: 44
1082 10:01:22.510280
1083 10:01:22.513718 Set Vref, RX VrefLevel [Byte0]: 45
1084 10:01:22.516748 [Byte1]: 45
1085 10:01:22.517163
1086 10:01:22.520645 Set Vref, RX VrefLevel [Byte0]: 46
1087 10:01:22.523212 [Byte1]: 46
1088 10:01:22.523627
1089 10:01:22.526667 Set Vref, RX VrefLevel [Byte0]: 47
1090 10:01:22.530069 [Byte1]: 47
1091 10:01:22.533716
1092 10:01:22.534152 Set Vref, RX VrefLevel [Byte0]: 48
1093 10:01:22.536497 [Byte1]: 48
1094 10:01:22.541044
1095 10:01:22.541558 Set Vref, RX VrefLevel [Byte0]: 49
1096 10:01:22.544228 [Byte1]: 49
1097 10:01:22.548723
1098 10:01:22.549192 Set Vref, RX VrefLevel [Byte0]: 50
1099 10:01:22.551732 [Byte1]: 50
1100 10:01:22.556195
1101 10:01:22.556606 Set Vref, RX VrefLevel [Byte0]: 51
1102 10:01:22.559593 [Byte1]: 51
1103 10:01:22.563846
1104 10:01:22.564343 Set Vref, RX VrefLevel [Byte0]: 52
1105 10:01:22.567173 [Byte1]: 52
1106 10:01:22.571322
1107 10:01:22.571751 Set Vref, RX VrefLevel [Byte0]: 53
1108 10:01:22.574893 [Byte1]: 53
1109 10:01:22.579317
1110 10:01:22.579810 Set Vref, RX VrefLevel [Byte0]: 54
1111 10:01:22.582393 [Byte1]: 54
1112 10:01:22.586667
1113 10:01:22.587032 Set Vref, RX VrefLevel [Byte0]: 55
1114 10:01:22.589680 [Byte1]: 55
1115 10:01:22.594088
1116 10:01:22.594427 Set Vref, RX VrefLevel [Byte0]: 56
1117 10:01:22.598084 [Byte1]: 56
1118 10:01:22.601830
1119 10:01:22.602089 Set Vref, RX VrefLevel [Byte0]: 57
1120 10:01:22.605689 [Byte1]: 57
1121 10:01:22.609720
1122 10:01:22.609973 Set Vref, RX VrefLevel [Byte0]: 58
1123 10:01:22.613266 [Byte1]: 58
1124 10:01:22.617470
1125 10:01:22.617711 Set Vref, RX VrefLevel [Byte0]: 59
1126 10:01:22.620977 [Byte1]: 59
1127 10:01:22.625714
1128 10:01:22.625933 Set Vref, RX VrefLevel [Byte0]: 60
1129 10:01:22.628319 [Byte1]: 60
1130 10:01:22.632741
1131 10:01:22.632962 Set Vref, RX VrefLevel [Byte0]: 61
1132 10:01:22.635969 [Byte1]: 61
1133 10:01:22.639861
1134 10:01:22.640175 Set Vref, RX VrefLevel [Byte0]: 62
1135 10:01:22.644075 [Byte1]: 62
1136 10:01:22.647437
1137 10:01:22.647740 Set Vref, RX VrefLevel [Byte0]: 63
1138 10:01:22.651044 [Byte1]: 63
1139 10:01:22.655780
1140 10:01:22.656028 Set Vref, RX VrefLevel [Byte0]: 64
1141 10:01:22.659493 [Byte1]: 64
1142 10:01:22.664355
1143 10:01:22.664674 Set Vref, RX VrefLevel [Byte0]: 65
1144 10:01:22.666961 [Byte1]: 65
1145 10:01:22.670761
1146 10:01:22.671124 Set Vref, RX VrefLevel [Byte0]: 66
1147 10:01:22.675184 [Byte1]: 66
1148 10:01:22.678082
1149 10:01:22.681724 Set Vref, RX VrefLevel [Byte0]: 67
1150 10:01:22.681827 [Byte1]: 67
1151 10:01:22.685765
1152 10:01:22.685874 Set Vref, RX VrefLevel [Byte0]: 68
1153 10:01:22.689752 [Byte1]: 68
1154 10:01:22.694443
1155 10:01:22.694555 Set Vref, RX VrefLevel [Byte0]: 69
1156 10:01:22.697253 [Byte1]: 69
1157 10:01:22.701818
1158 10:01:22.701931 Set Vref, RX VrefLevel [Byte0]: 70
1159 10:01:22.704193 [Byte1]: 70
1160 10:01:22.709012
1161 10:01:22.709086 Set Vref, RX VrefLevel [Byte0]: 71
1162 10:01:22.712232 [Byte1]: 71
1163 10:01:22.717141
1164 10:01:22.717213 Set Vref, RX VrefLevel [Byte0]: 72
1165 10:01:22.720099 [Byte1]: 72
1166 10:01:22.724322
1167 10:01:22.724424 Set Vref, RX VrefLevel [Byte0]: 73
1168 10:01:22.728211 [Byte1]: 73
1169 10:01:22.731705
1170 10:01:22.731821 Set Vref, RX VrefLevel [Byte0]: 74
1171 10:01:22.735588 [Byte1]: 74
1172 10:01:22.739503
1173 10:01:22.739605 Set Vref, RX VrefLevel [Byte0]: 75
1174 10:01:22.742582 [Byte1]: 75
1175 10:01:22.747065
1176 10:01:22.747177 Set Vref, RX VrefLevel [Byte0]: 76
1177 10:01:22.751007 [Byte1]: 76
1178 10:01:22.754657
1179 10:01:22.754737 Set Vref, RX VrefLevel [Byte0]: 77
1180 10:01:22.758606 [Byte1]: 77
1181 10:01:22.762460
1182 10:01:22.762568 Set Vref, RX VrefLevel [Byte0]: 78
1183 10:01:22.765890 [Byte1]: 78
1184 10:01:22.770553
1185 10:01:22.770649 Set Vref, RX VrefLevel [Byte0]: 79
1186 10:01:22.773661 [Byte1]: 79
1187 10:01:22.777923
1188 10:01:22.778003 Set Vref, RX VrefLevel [Byte0]: 80
1189 10:01:22.781102 [Byte1]: 80
1190 10:01:22.785697
1191 10:01:22.785819 Set Vref, RX VrefLevel [Byte0]: 81
1192 10:01:22.788641 [Byte1]: 81
1193 10:01:22.792811
1194 10:01:22.792926 Set Vref, RX VrefLevel [Byte0]: 82
1195 10:01:22.796637 [Byte1]: 82
1196 10:01:22.801218
1197 10:01:22.801339 Set Vref, RX VrefLevel [Byte0]: 83
1198 10:01:22.804245 [Byte1]: 83
1199 10:01:22.808739
1200 10:01:22.808821 Final RX Vref Byte 0 = 67 to rank0
1201 10:01:22.811942 Final RX Vref Byte 1 = 58 to rank0
1202 10:01:22.815721 Final RX Vref Byte 0 = 67 to rank1
1203 10:01:22.819001 Final RX Vref Byte 1 = 58 to rank1==
1204 10:01:22.822858 Dram Type= 6, Freq= 0, CH_0, rank 0
1205 10:01:22.825544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1206 10:01:22.825635 ==
1207 10:01:22.829122 DQS Delay:
1208 10:01:22.829242 DQS0 = 0, DQS1 = 0
1209 10:01:22.829341 DQM Delay:
1210 10:01:22.832754 DQM0 = 86, DQM1 = 75
1211 10:01:22.832857 DQ Delay:
1212 10:01:22.837058 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =80
1213 10:01:22.840159 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1214 10:01:22.844031 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =68
1215 10:01:22.847527 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1216 10:01:22.847666
1217 10:01:22.847775
1218 10:01:22.855179 [DQSOSCAuto] RK0, (LSB)MR18= 0x4729, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 392 ps
1219 10:01:22.858793 CH0 RK0: MR19=606, MR18=4729
1220 10:01:22.862748 CH0_RK0: MR19=0x606, MR18=0x4729, DQSOSC=392, MR23=63, INC=96, DEC=64
1221 10:01:22.862941
1222 10:01:22.866569 ----->DramcWriteLeveling(PI) begin...
1223 10:01:22.866729 ==
1224 10:01:22.869703 Dram Type= 6, Freq= 0, CH_0, rank 1
1225 10:01:22.874325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1226 10:01:22.874466 ==
1227 10:01:22.918103 Write leveling (Byte 0): 32 => 32
1228 10:01:22.918735 Write leveling (Byte 1): 31 => 31
1229 10:01:22.919056 DramcWriteLeveling(PI) end<-----
1230 10:01:22.919363
1231 10:01:22.919659 ==
1232 10:01:22.920000 Dram Type= 6, Freq= 0, CH_0, rank 1
1233 10:01:22.920355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1234 10:01:22.920656 ==
1235 10:01:22.920950 [Gating] SW mode calibration
1236 10:01:22.921291 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1237 10:01:22.921612 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1238 10:01:22.921962 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1239 10:01:22.922260 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1240 10:01:22.962620 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1241 10:01:22.963158 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 10:01:22.963873 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 10:01:22.964269 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 10:01:22.964668 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 10:01:22.965043 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 10:01:22.965442 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 10:01:22.965837 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 10:01:22.966260 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 10:01:22.966677 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 10:01:23.006391 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 10:01:23.006732 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 10:01:23.007289 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 10:01:23.007663 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 10:01:23.007924 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 10:01:23.008211 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1256 10:01:23.008525 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1257 10:01:23.008764 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1258 10:01:23.009042 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 10:01:23.009277 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 10:01:23.050196 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 10:01:23.050810 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 10:01:23.051322 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 10:01:23.052210 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1264 10:01:23.052774 0 9 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1265 10:01:23.053256 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1266 10:01:23.053882 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1267 10:01:23.054360 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1268 10:01:23.054868 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1269 10:01:23.055397 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1270 10:01:23.094634 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1271 10:01:23.095262 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
1272 10:01:23.096186 0 10 8 | B1->B0 | 3030 2a2a | 0 0 | (0 0) (0 0)
1273 10:01:23.096726 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1274 10:01:23.097251 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1275 10:01:23.097767 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1276 10:01:23.098305 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1277 10:01:23.098856 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1278 10:01:23.099353 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1279 10:01:23.099846 0 11 4 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
1280 10:01:23.112114 0 11 8 | B1->B0 | 3131 4242 | 0 0 | (0 0) (0 0)
1281 10:01:23.112516 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1282 10:01:23.112886 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1283 10:01:23.113576 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1284 10:01:23.115541 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1285 10:01:23.118862 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1286 10:01:23.121692 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1287 10:01:23.125186 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1288 10:01:23.132051 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1289 10:01:23.134939 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 10:01:23.138440 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 10:01:23.144920 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1292 10:01:23.148701 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1293 10:01:23.151725 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1294 10:01:23.158218 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1295 10:01:23.162205 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1296 10:01:23.164870 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1297 10:01:23.171441 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1298 10:01:23.175503 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1299 10:01:23.178254 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1300 10:01:23.185277 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1301 10:01:23.189347 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1302 10:01:23.191817 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1303 10:01:23.198147 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1304 10:01:23.201746 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1305 10:01:23.205000 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1306 10:01:23.208276 Total UI for P1: 0, mck2ui 16
1307 10:01:23.212177 best dqsien dly found for B0: ( 0, 14, 8)
1308 10:01:23.219278 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1309 10:01:23.219718 Total UI for P1: 0, mck2ui 16
1310 10:01:23.225184 best dqsien dly found for B1: ( 0, 14, 10)
1311 10:01:23.228838 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1312 10:01:23.231493 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1313 10:01:23.232040
1314 10:01:23.235160 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1315 10:01:23.238628 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1316 10:01:23.242105 [Gating] SW calibration Done
1317 10:01:23.242521 ==
1318 10:01:23.244938 Dram Type= 6, Freq= 0, CH_0, rank 1
1319 10:01:23.248900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1320 10:01:23.249461 ==
1321 10:01:23.251983 RX Vref Scan: 0
1322 10:01:23.252497
1323 10:01:23.252829 RX Vref 0 -> 0, step: 1
1324 10:01:23.253142
1325 10:01:23.254629 RX Delay -130 -> 252, step: 16
1326 10:01:23.258466 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1327 10:01:23.265015 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1328 10:01:23.268531 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1329 10:01:23.272106 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1330 10:01:23.274943 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1331 10:01:23.281487 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1332 10:01:23.284649 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1333 10:01:23.288247 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1334 10:01:23.291029 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1335 10:01:23.294746 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1336 10:01:23.298457 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1337 10:01:23.305037 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1338 10:01:23.308141 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1339 10:01:23.311096 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1340 10:01:23.315190 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1341 10:01:23.321532 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1342 10:01:23.322165 ==
1343 10:01:23.324322 Dram Type= 6, Freq= 0, CH_0, rank 1
1344 10:01:23.328774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1345 10:01:23.329344 ==
1346 10:01:23.329767 DQS Delay:
1347 10:01:23.331263 DQS0 = 0, DQS1 = 0
1348 10:01:23.331726 DQM Delay:
1349 10:01:23.334307 DQM0 = 84, DQM1 = 76
1350 10:01:23.334773 DQ Delay:
1351 10:01:23.337492 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1352 10:01:23.341054 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1353 10:01:23.344188 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1354 10:01:23.348018 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1355 10:01:23.348543
1356 10:01:23.348876
1357 10:01:23.349182 ==
1358 10:01:23.350847 Dram Type= 6, Freq= 0, CH_0, rank 1
1359 10:01:23.353935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1360 10:01:23.354357 ==
1361 10:01:23.357401
1362 10:01:23.357863
1363 10:01:23.358193 TX Vref Scan disable
1364 10:01:23.360827 == TX Byte 0 ==
1365 10:01:23.363999 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1366 10:01:23.367489 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1367 10:01:23.370675 == TX Byte 1 ==
1368 10:01:23.373971 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1369 10:01:23.377763 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1370 10:01:23.378178 ==
1371 10:01:23.380350 Dram Type= 6, Freq= 0, CH_0, rank 1
1372 10:01:23.387445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1373 10:01:23.387840 ==
1374 10:01:23.399160 TX Vref=22, minBit 3, minWin=27, winSum=445
1375 10:01:23.402367 TX Vref=24, minBit 9, minWin=27, winSum=444
1376 10:01:23.406443 TX Vref=26, minBit 9, minWin=27, winSum=446
1377 10:01:23.409232 TX Vref=28, minBit 9, minWin=27, winSum=447
1378 10:01:23.412733 TX Vref=30, minBit 8, minWin=27, winSum=443
1379 10:01:23.418946 TX Vref=32, minBit 9, minWin=27, winSum=443
1380 10:01:23.422279 [TxChooseVref] Worse bit 9, Min win 27, Win sum 447, Final Vref 28
1381 10:01:23.422700
1382 10:01:23.425791 Final TX Range 1 Vref 28
1383 10:01:23.426210
1384 10:01:23.426540 ==
1385 10:01:23.428913 Dram Type= 6, Freq= 0, CH_0, rank 1
1386 10:01:23.432279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1387 10:01:23.432882 ==
1388 10:01:23.435557
1389 10:01:23.436144
1390 10:01:23.436658 TX Vref Scan disable
1391 10:01:23.438925 == TX Byte 0 ==
1392 10:01:23.442164 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1393 10:01:23.448838 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1394 10:01:23.449463 == TX Byte 1 ==
1395 10:01:23.452400 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1396 10:01:23.459243 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1397 10:01:23.459784
1398 10:01:23.460124 [DATLAT]
1399 10:01:23.460432 Freq=800, CH0 RK1
1400 10:01:23.460733
1401 10:01:23.462333 DATLAT Default: 0xa
1402 10:01:23.462744 0, 0xFFFF, sum = 0
1403 10:01:23.465687 1, 0xFFFF, sum = 0
1404 10:01:23.466104 2, 0xFFFF, sum = 0
1405 10:01:23.468989 3, 0xFFFF, sum = 0
1406 10:01:23.469436 4, 0xFFFF, sum = 0
1407 10:01:23.471933 5, 0xFFFF, sum = 0
1408 10:01:23.475069 6, 0xFFFF, sum = 0
1409 10:01:23.475293 7, 0xFFFF, sum = 0
1410 10:01:23.478814 8, 0xFFFF, sum = 0
1411 10:01:23.479038 9, 0x0, sum = 1
1412 10:01:23.479215 10, 0x0, sum = 2
1413 10:01:23.481738 11, 0x0, sum = 3
1414 10:01:23.481917 12, 0x0, sum = 4
1415 10:01:23.485112 best_step = 10
1416 10:01:23.485342
1417 10:01:23.485529 ==
1418 10:01:23.488963 Dram Type= 6, Freq= 0, CH_0, rank 1
1419 10:01:23.491927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1420 10:01:23.492105 ==
1421 10:01:23.495639 RX Vref Scan: 0
1422 10:01:23.495816
1423 10:01:23.495956 RX Vref 0 -> 0, step: 1
1424 10:01:23.498765
1425 10:01:23.498940 RX Delay -111 -> 252, step: 8
1426 10:01:23.505354 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1427 10:01:23.509067 iDelay=217, Bit 1, Center 92 (-23 ~ 208) 232
1428 10:01:23.512099 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
1429 10:01:23.515257 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1430 10:01:23.518935 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1431 10:01:23.525540 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1432 10:01:23.529112 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1433 10:01:23.532056 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1434 10:01:23.535507 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1435 10:01:23.538752 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1436 10:01:23.545551 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
1437 10:01:23.548596 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1438 10:01:23.552579 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1439 10:01:23.555158 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1440 10:01:23.561739 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1441 10:01:23.565128 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1442 10:01:23.565363 ==
1443 10:01:23.568680 Dram Type= 6, Freq= 0, CH_0, rank 1
1444 10:01:23.571888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1445 10:01:23.572068 ==
1446 10:01:23.574980 DQS Delay:
1447 10:01:23.575157 DQS0 = 0, DQS1 = 0
1448 10:01:23.575299 DQM Delay:
1449 10:01:23.578318 DQM0 = 86, DQM1 = 77
1450 10:01:23.578495 DQ Delay:
1451 10:01:23.582283 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =84
1452 10:01:23.585369 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96
1453 10:01:23.588176 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =68
1454 10:01:23.591980 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1455 10:01:23.592157
1456 10:01:23.592297
1457 10:01:23.601787 [DQSOSCAuto] RK1, (LSB)MR18= 0x4005, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
1458 10:01:23.601966 CH0 RK1: MR19=606, MR18=4005
1459 10:01:23.608897 CH0_RK1: MR19=0x606, MR18=0x4005, DQSOSC=393, MR23=63, INC=95, DEC=63
1460 10:01:23.612040 [RxdqsGatingPostProcess] freq 800
1461 10:01:23.618617 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1462 10:01:23.621845 Pre-setting of DQS Precalculation
1463 10:01:23.625655 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1464 10:01:23.626093 ==
1465 10:01:23.628545 Dram Type= 6, Freq= 0, CH_1, rank 0
1466 10:01:23.635708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1467 10:01:23.636263 ==
1468 10:01:23.639088 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1469 10:01:23.645696 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1470 10:01:23.654435 [CA 0] Center 36 (6~67) winsize 62
1471 10:01:23.658271 [CA 1] Center 36 (6~67) winsize 62
1472 10:01:23.660720 [CA 2] Center 34 (4~65) winsize 62
1473 10:01:23.664441 [CA 3] Center 34 (3~65) winsize 63
1474 10:01:23.667867 [CA 4] Center 34 (4~65) winsize 62
1475 10:01:23.670759 [CA 5] Center 34 (4~65) winsize 62
1476 10:01:23.671379
1477 10:01:23.674239 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1478 10:01:23.674860
1479 10:01:23.677258 [CATrainingPosCal] consider 1 rank data
1480 10:01:23.681164 u2DelayCellTimex100 = 270/100 ps
1481 10:01:23.683858 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1482 10:01:23.690479 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1483 10:01:23.693664 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1484 10:01:23.697399 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1485 10:01:23.700352 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1486 10:01:23.703615 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1487 10:01:23.704033
1488 10:01:23.707053 CA PerBit enable=1, Macro0, CA PI delay=34
1489 10:01:23.707520
1490 10:01:23.710716 [CBTSetCACLKResult] CA Dly = 34
1491 10:01:23.713879 CS Dly: 5 (0~36)
1492 10:01:23.714305 ==
1493 10:01:23.716836 Dram Type= 6, Freq= 0, CH_1, rank 1
1494 10:01:23.720559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1495 10:01:23.720994 ==
1496 10:01:23.727005 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1497 10:01:23.730209 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1498 10:01:23.740343 [CA 0] Center 36 (6~67) winsize 62
1499 10:01:23.743451 [CA 1] Center 36 (6~67) winsize 62
1500 10:01:23.746893 [CA 2] Center 34 (4~65) winsize 62
1501 10:01:23.750296 [CA 3] Center 34 (3~65) winsize 63
1502 10:01:23.753764 [CA 4] Center 34 (4~65) winsize 62
1503 10:01:23.756719 [CA 5] Center 34 (3~65) winsize 63
1504 10:01:23.756847
1505 10:01:23.759853 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1506 10:01:23.759983
1507 10:01:23.763509 [CATrainingPosCal] consider 2 rank data
1508 10:01:23.766537 u2DelayCellTimex100 = 270/100 ps
1509 10:01:23.770157 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1510 10:01:23.776571 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1511 10:01:23.779979 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1512 10:01:23.783247 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1513 10:01:23.786450 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1514 10:01:23.789363 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1515 10:01:23.789541
1516 10:01:23.792926 CA PerBit enable=1, Macro0, CA PI delay=34
1517 10:01:23.793117
1518 10:01:23.796660 [CBTSetCACLKResult] CA Dly = 34
1519 10:01:23.796808 CS Dly: 5 (0~37)
1520 10:01:23.800083
1521 10:01:23.803182 ----->DramcWriteLeveling(PI) begin...
1522 10:01:23.803330 ==
1523 10:01:23.806112 Dram Type= 6, Freq= 0, CH_1, rank 0
1524 10:01:23.809431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1525 10:01:23.809577 ==
1526 10:01:23.812761 Write leveling (Byte 0): 26 => 26
1527 10:01:23.816173 Write leveling (Byte 1): 27 => 27
1528 10:01:23.819885 DramcWriteLeveling(PI) end<-----
1529 10:01:23.820041
1530 10:01:23.820159 ==
1531 10:01:23.822845 Dram Type= 6, Freq= 0, CH_1, rank 0
1532 10:01:23.826216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1533 10:01:23.826373 ==
1534 10:01:23.829735 [Gating] SW mode calibration
1535 10:01:23.836109 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1536 10:01:23.843343 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1537 10:01:23.846641 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1538 10:01:23.849229 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1539 10:01:23.856112 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 10:01:23.860019 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 10:01:23.862963 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 10:01:23.869271 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 10:01:23.872873 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 10:01:23.876498 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 10:01:23.882924 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 10:01:23.886111 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 10:01:23.889515 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 10:01:23.896173 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 10:01:23.899849 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 10:01:23.902603 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 10:01:23.909393 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 10:01:23.913190 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 10:01:23.916025 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1554 10:01:23.922441 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1555 10:01:23.925625 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1556 10:01:23.929005 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 10:01:23.936477 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 10:01:23.938885 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 10:01:23.942440 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 10:01:23.945773 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 10:01:23.952176 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1562 10:01:23.955632 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1563 10:01:23.958941 0 9 8 | B1->B0 | 2f2f 3434 | 0 0 | (0 0) (0 0)
1564 10:01:23.968477 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1565 10:01:23.969233 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1566 10:01:23.971877 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1567 10:01:23.978472 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1568 10:01:23.982122 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1569 10:01:23.985122 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1570 10:01:23.991662 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
1571 10:01:23.995027 0 10 8 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
1572 10:01:23.998518 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1573 10:01:24.004856 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1574 10:01:24.008442 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1575 10:01:24.011639 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1576 10:01:24.018449 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1577 10:01:24.021751 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1578 10:01:24.025521 0 11 4 | B1->B0 | 2727 2626 | 0 0 | (0 0) (1 1)
1579 10:01:24.031718 0 11 8 | B1->B0 | 3a3a 4141 | 0 0 | (0 0) (0 0)
1580 10:01:24.035252 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1581 10:01:24.038239 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1582 10:01:24.044966 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1583 10:01:24.048329 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1584 10:01:24.052054 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1585 10:01:24.058393 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1586 10:01:24.061126 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1587 10:01:24.064698 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 10:01:24.071632 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1589 10:01:24.074334 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1590 10:01:24.078031 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1591 10:01:24.084682 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1592 10:01:24.087907 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1593 10:01:24.091287 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1594 10:01:24.097777 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1595 10:01:24.101067 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1596 10:01:24.104580 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1597 10:01:24.111047 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1598 10:01:24.114710 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1599 10:01:24.117617 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1600 10:01:24.124423 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1601 10:01:24.127449 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1602 10:01:24.130810 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1603 10:01:24.137356 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1604 10:01:24.137884 Total UI for P1: 0, mck2ui 16
1605 10:01:24.144163 best dqsien dly found for B0: ( 0, 14, 4)
1606 10:01:24.144730 Total UI for P1: 0, mck2ui 16
1607 10:01:24.147513 best dqsien dly found for B1: ( 0, 14, 4)
1608 10:01:24.154874 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1609 10:01:24.157548 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1610 10:01:24.158117
1611 10:01:24.160608 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1612 10:01:24.163788 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1613 10:01:24.167870 [Gating] SW calibration Done
1614 10:01:24.168352 ==
1615 10:01:24.170421 Dram Type= 6, Freq= 0, CH_1, rank 0
1616 10:01:24.174386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1617 10:01:24.174761 ==
1618 10:01:24.174942 RX Vref Scan: 0
1619 10:01:24.177068
1620 10:01:24.177262 RX Vref 0 -> 0, step: 1
1621 10:01:24.177462
1622 10:01:24.180756 RX Delay -130 -> 252, step: 16
1623 10:01:24.183623 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1624 10:01:24.190487 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1625 10:01:24.194069 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1626 10:01:24.197241 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1627 10:01:24.200772 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1628 10:01:24.204013 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1629 10:01:24.210678 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1630 10:01:24.214293 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1631 10:01:24.217460 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1632 10:01:24.220585 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1633 10:01:24.224183 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1634 10:01:24.230794 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1635 10:01:24.234167 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1636 10:01:24.236859 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1637 10:01:24.240898 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1638 10:01:24.244120 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1639 10:01:24.247977 ==
1640 10:01:24.248498 Dram Type= 6, Freq= 0, CH_1, rank 0
1641 10:01:24.253825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1642 10:01:24.254339 ==
1643 10:01:24.254673 DQS Delay:
1644 10:01:24.256798 DQS0 = 0, DQS1 = 0
1645 10:01:24.257269 DQM Delay:
1646 10:01:24.260352 DQM0 = 89, DQM1 = 80
1647 10:01:24.260808 DQ Delay:
1648 10:01:24.263908 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1649 10:01:24.266900 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1650 10:01:24.270323 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1651 10:01:24.273538 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =93
1652 10:01:24.273996
1653 10:01:24.274357
1654 10:01:24.274692 ==
1655 10:01:24.276888 Dram Type= 6, Freq= 0, CH_1, rank 0
1656 10:01:24.280196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1657 10:01:24.280656 ==
1658 10:01:24.281018
1659 10:01:24.281350
1660 10:01:24.284154 TX Vref Scan disable
1661 10:01:24.287030 == TX Byte 0 ==
1662 10:01:24.290761 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1663 10:01:24.293671 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1664 10:01:24.296762 == TX Byte 1 ==
1665 10:01:24.300583 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1666 10:01:24.303267 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1667 10:01:24.303686 ==
1668 10:01:24.306653 Dram Type= 6, Freq= 0, CH_1, rank 0
1669 10:01:24.313570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1670 10:01:24.314091 ==
1671 10:01:24.325366 TX Vref=22, minBit 8, minWin=27, winSum=444
1672 10:01:24.328345 TX Vref=24, minBit 9, minWin=27, winSum=447
1673 10:01:24.331686 TX Vref=26, minBit 10, minWin=27, winSum=449
1674 10:01:24.334684 TX Vref=28, minBit 13, minWin=27, winSum=449
1675 10:01:24.338145 TX Vref=30, minBit 8, minWin=27, winSum=450
1676 10:01:24.344558 TX Vref=32, minBit 0, minWin=27, winSum=445
1677 10:01:24.348570 [TxChooseVref] Worse bit 8, Min win 27, Win sum 450, Final Vref 30
1678 10:01:24.348988
1679 10:01:24.351812 Final TX Range 1 Vref 30
1680 10:01:24.352226
1681 10:01:24.352552 ==
1682 10:01:24.355077 Dram Type= 6, Freq= 0, CH_1, rank 0
1683 10:01:24.358165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1684 10:01:24.362030 ==
1685 10:01:24.362439
1686 10:01:24.362762
1687 10:01:24.363064 TX Vref Scan disable
1688 10:01:24.365304 == TX Byte 0 ==
1689 10:01:24.368269 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1690 10:01:24.374937 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1691 10:01:24.375439 == TX Byte 1 ==
1692 10:01:24.378495 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1693 10:01:24.384799 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1694 10:01:24.385284
1695 10:01:24.385661 [DATLAT]
1696 10:01:24.385972 Freq=800, CH1 RK0
1697 10:01:24.386271
1698 10:01:24.388048 DATLAT Default: 0xa
1699 10:01:24.388461 0, 0xFFFF, sum = 0
1700 10:01:24.391754 1, 0xFFFF, sum = 0
1701 10:01:24.392173 2, 0xFFFF, sum = 0
1702 10:01:24.394648 3, 0xFFFF, sum = 0
1703 10:01:24.398253 4, 0xFFFF, sum = 0
1704 10:01:24.398671 5, 0xFFFF, sum = 0
1705 10:01:24.401379 6, 0xFFFF, sum = 0
1706 10:01:24.401939 7, 0xFFFF, sum = 0
1707 10:01:24.404648 8, 0xFFFF, sum = 0
1708 10:01:24.405089 9, 0x0, sum = 1
1709 10:01:24.407901 10, 0x0, sum = 2
1710 10:01:24.408338 11, 0x0, sum = 3
1711 10:01:24.408722 12, 0x0, sum = 4
1712 10:01:24.411239 best_step = 10
1713 10:01:24.411766
1714 10:01:24.412223 ==
1715 10:01:24.414973 Dram Type= 6, Freq= 0, CH_1, rank 0
1716 10:01:24.417840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1717 10:01:24.418414 ==
1718 10:01:24.421162 RX Vref Scan: 1
1719 10:01:24.421646
1720 10:01:24.424272 Set Vref Range= 32 -> 127
1721 10:01:24.424832
1722 10:01:24.425335 RX Vref 32 -> 127, step: 1
1723 10:01:24.425815
1724 10:01:24.427880 RX Delay -95 -> 252, step: 8
1725 10:01:24.428296
1726 10:01:24.431726 Set Vref, RX VrefLevel [Byte0]: 32
1727 10:01:24.435107 [Byte1]: 32
1728 10:01:24.435526
1729 10:01:24.438188 Set Vref, RX VrefLevel [Byte0]: 33
1730 10:01:24.440910 [Byte1]: 33
1731 10:01:24.445749
1732 10:01:24.446327 Set Vref, RX VrefLevel [Byte0]: 34
1733 10:01:24.448712 [Byte1]: 34
1734 10:01:24.452722
1735 10:01:24.453267 Set Vref, RX VrefLevel [Byte0]: 35
1736 10:01:24.456445 [Byte1]: 35
1737 10:01:24.460154
1738 10:01:24.460449 Set Vref, RX VrefLevel [Byte0]: 36
1739 10:01:24.463881 [Byte1]: 36
1740 10:01:24.467834
1741 10:01:24.468135 Set Vref, RX VrefLevel [Byte0]: 37
1742 10:01:24.471339 [Byte1]: 37
1743 10:01:24.475763
1744 10:01:24.476057 Set Vref, RX VrefLevel [Byte0]: 38
1745 10:01:24.478669 [Byte1]: 38
1746 10:01:24.483251
1747 10:01:24.483547 Set Vref, RX VrefLevel [Byte0]: 39
1748 10:01:24.486262 [Byte1]: 39
1749 10:01:24.490712
1750 10:01:24.490891 Set Vref, RX VrefLevel [Byte0]: 40
1751 10:01:24.494019 [Byte1]: 40
1752 10:01:24.498530
1753 10:01:24.498680 Set Vref, RX VrefLevel [Byte0]: 41
1754 10:01:24.501629 [Byte1]: 41
1755 10:01:24.505654
1756 10:01:24.505783 Set Vref, RX VrefLevel [Byte0]: 42
1757 10:01:24.509307 [Byte1]: 42
1758 10:01:24.513447
1759 10:01:24.513667 Set Vref, RX VrefLevel [Byte0]: 43
1760 10:01:24.516426 [Byte1]: 43
1761 10:01:24.520771
1762 10:01:24.520902 Set Vref, RX VrefLevel [Byte0]: 44
1763 10:01:24.524254 [Byte1]: 44
1764 10:01:24.528317
1765 10:01:24.528448 Set Vref, RX VrefLevel [Byte0]: 45
1766 10:01:24.531732 [Byte1]: 45
1767 10:01:24.535944
1768 10:01:24.536074 Set Vref, RX VrefLevel [Byte0]: 46
1769 10:01:24.539639 [Byte1]: 46
1770 10:01:24.543450
1771 10:01:24.543531 Set Vref, RX VrefLevel [Byte0]: 47
1772 10:01:24.546819 [Byte1]: 47
1773 10:01:24.551446
1774 10:01:24.551526 Set Vref, RX VrefLevel [Byte0]: 48
1775 10:01:24.554837 [Byte1]: 48
1776 10:01:24.558582
1777 10:01:24.558663 Set Vref, RX VrefLevel [Byte0]: 49
1778 10:01:24.561918 [Byte1]: 49
1779 10:01:24.566160
1780 10:01:24.566241 Set Vref, RX VrefLevel [Byte0]: 50
1781 10:01:24.569967 [Byte1]: 50
1782 10:01:24.573966
1783 10:01:24.574073 Set Vref, RX VrefLevel [Byte0]: 51
1784 10:01:24.577015 [Byte1]: 51
1785 10:01:24.581470
1786 10:01:24.581551 Set Vref, RX VrefLevel [Byte0]: 52
1787 10:01:24.584795 [Byte1]: 52
1788 10:01:24.589561
1789 10:01:24.589644 Set Vref, RX VrefLevel [Byte0]: 53
1790 10:01:24.592342 [Byte1]: 53
1791 10:01:24.596967
1792 10:01:24.597048 Set Vref, RX VrefLevel [Byte0]: 54
1793 10:01:24.600100 [Byte1]: 54
1794 10:01:24.604908
1795 10:01:24.604989 Set Vref, RX VrefLevel [Byte0]: 55
1796 10:01:24.607574 [Byte1]: 55
1797 10:01:24.612075
1798 10:01:24.612156 Set Vref, RX VrefLevel [Byte0]: 56
1799 10:01:24.615814 [Byte1]: 56
1800 10:01:24.619480
1801 10:01:24.619561 Set Vref, RX VrefLevel [Byte0]: 57
1802 10:01:24.622635 [Byte1]: 57
1803 10:01:24.627744
1804 10:01:24.627825 Set Vref, RX VrefLevel [Byte0]: 58
1805 10:01:24.630250 [Byte1]: 58
1806 10:01:24.635738
1807 10:01:24.635819 Set Vref, RX VrefLevel [Byte0]: 59
1808 10:01:24.637976 [Byte1]: 59
1809 10:01:24.642531
1810 10:01:24.642612 Set Vref, RX VrefLevel [Byte0]: 60
1811 10:01:24.645911 [Byte1]: 60
1812 10:01:24.650242
1813 10:01:24.650335 Set Vref, RX VrefLevel [Byte0]: 61
1814 10:01:24.653141 [Byte1]: 61
1815 10:01:24.657667
1816 10:01:24.657767 Set Vref, RX VrefLevel [Byte0]: 62
1817 10:01:24.661026 [Byte1]: 62
1818 10:01:24.665320
1819 10:01:24.665452 Set Vref, RX VrefLevel [Byte0]: 63
1820 10:01:24.668935 [Byte1]: 63
1821 10:01:24.672860
1822 10:01:24.673076 Set Vref, RX VrefLevel [Byte0]: 64
1823 10:01:24.676645 [Byte1]: 64
1824 10:01:24.680725
1825 10:01:24.680986 Set Vref, RX VrefLevel [Byte0]: 65
1826 10:01:24.683896 [Byte1]: 65
1827 10:01:24.688455
1828 10:01:24.688747 Set Vref, RX VrefLevel [Byte0]: 66
1829 10:01:24.691987 [Byte1]: 66
1830 10:01:24.695955
1831 10:01:24.696249 Set Vref, RX VrefLevel [Byte0]: 67
1832 10:01:24.699092 [Byte1]: 67
1833 10:01:24.703359
1834 10:01:24.703739 Set Vref, RX VrefLevel [Byte0]: 68
1835 10:01:24.707167 [Byte1]: 68
1836 10:01:24.711213
1837 10:01:24.711895 Set Vref, RX VrefLevel [Byte0]: 69
1838 10:01:24.714377 [Byte1]: 69
1839 10:01:24.718577
1840 10:01:24.718997 Set Vref, RX VrefLevel [Byte0]: 70
1841 10:01:24.721993 [Byte1]: 70
1842 10:01:24.726289
1843 10:01:24.726811 Set Vref, RX VrefLevel [Byte0]: 71
1844 10:01:24.729459 [Byte1]: 71
1845 10:01:24.733878
1846 10:01:24.734293 Set Vref, RX VrefLevel [Byte0]: 72
1847 10:01:24.736962 [Byte1]: 72
1848 10:01:24.741389
1849 10:01:24.741929 Set Vref, RX VrefLevel [Byte0]: 73
1850 10:01:24.744609 [Byte1]: 73
1851 10:01:24.749163
1852 10:01:24.749841 Set Vref, RX VrefLevel [Byte0]: 74
1853 10:01:24.752199 [Byte1]: 74
1854 10:01:24.756432
1855 10:01:24.757051 Set Vref, RX VrefLevel [Byte0]: 75
1856 10:01:24.759985 [Byte1]: 75
1857 10:01:24.764104
1858 10:01:24.764674 Set Vref, RX VrefLevel [Byte0]: 76
1859 10:01:24.767164 [Byte1]: 76
1860 10:01:24.771902
1861 10:01:24.772454 Final RX Vref Byte 0 = 56 to rank0
1862 10:01:24.775140 Final RX Vref Byte 1 = 66 to rank0
1863 10:01:24.778479 Final RX Vref Byte 0 = 56 to rank1
1864 10:01:24.781701 Final RX Vref Byte 1 = 66 to rank1==
1865 10:01:24.785230 Dram Type= 6, Freq= 0, CH_1, rank 0
1866 10:01:24.791714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1867 10:01:24.791938 ==
1868 10:01:24.792117 DQS Delay:
1869 10:01:24.792281 DQS0 = 0, DQS1 = 0
1870 10:01:24.795417 DQM Delay:
1871 10:01:24.795637 DQM0 = 87, DQM1 = 78
1872 10:01:24.798478 DQ Delay:
1873 10:01:24.801434 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1874 10:01:24.804861 DQ4 =84, DQ5 =100, DQ6 =100, DQ7 =80
1875 10:01:24.808515 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1876 10:01:24.811970 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
1877 10:01:24.812192
1878 10:01:24.812369
1879 10:01:24.818581 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e1b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
1880 10:01:24.821445 CH1 RK0: MR19=606, MR18=2E1B
1881 10:01:24.828300 CH1_RK0: MR19=0x606, MR18=0x2E1B, DQSOSC=398, MR23=63, INC=93, DEC=62
1882 10:01:24.828539
1883 10:01:24.831746 ----->DramcWriteLeveling(PI) begin...
1884 10:01:24.831971 ==
1885 10:01:24.835160 Dram Type= 6, Freq= 0, CH_1, rank 1
1886 10:01:24.838381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1887 10:01:24.838604 ==
1888 10:01:24.841591 Write leveling (Byte 0): 27 => 27
1889 10:01:24.844539 Write leveling (Byte 1): 28 => 28
1890 10:01:24.848327 DramcWriteLeveling(PI) end<-----
1891 10:01:24.848547
1892 10:01:24.848722 ==
1893 10:01:24.851348 Dram Type= 6, Freq= 0, CH_1, rank 1
1894 10:01:24.854623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1895 10:01:24.854848 ==
1896 10:01:24.858316 [Gating] SW mode calibration
1897 10:01:24.864708 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1898 10:01:24.871507 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1899 10:01:24.874321 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1900 10:01:24.878305 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1901 10:01:24.884954 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 10:01:24.888002 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 10:01:24.891636 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 10:01:24.897843 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 10:01:24.901642 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 10:01:24.904221 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 10:01:24.911391 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 10:01:24.914653 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 10:01:24.917634 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 10:01:24.924206 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 10:01:24.927426 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 10:01:24.931303 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 10:01:24.937937 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 10:01:24.940888 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 10:01:24.944974 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1916 10:01:24.951145 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1917 10:01:24.954639 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1918 10:01:24.957745 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 10:01:24.964142 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 10:01:24.967869 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 10:01:24.971197 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 10:01:24.977490 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 10:01:24.980852 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1924 10:01:24.984389 0 9 4 | B1->B0 | 2323 2323 | 1 0 | (1 1) (0 0)
1925 10:01:24.991178 0 9 8 | B1->B0 | 2f2f 2727 | 1 1 | (0 0) (1 1)
1926 10:01:24.994081 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1927 10:01:24.997798 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1928 10:01:25.004654 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1929 10:01:25.007981 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1930 10:01:25.010956 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1931 10:01:25.017480 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1932 10:01:25.020950 0 10 4 | B1->B0 | 3232 3434 | 1 1 | (1 0) (1 0)
1933 10:01:25.024074 0 10 8 | B1->B0 | 2828 2d2d | 0 0 | (0 0) (1 0)
1934 10:01:25.030854 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1935 10:01:25.034109 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1936 10:01:25.037563 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1937 10:01:25.044184 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1938 10:01:25.048076 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1939 10:01:25.050633 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1940 10:01:25.056988 0 11 4 | B1->B0 | 2b2b 2626 | 0 0 | (0 0) (0 0)
1941 10:01:25.060953 0 11 8 | B1->B0 | 4242 3a3a | 0 0 | (0 0) (0 0)
1942 10:01:25.063847 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1943 10:01:25.070276 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1944 10:01:25.073925 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1945 10:01:25.077341 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1946 10:01:25.084142 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1947 10:01:25.087185 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1948 10:01:25.090081 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1949 10:01:25.097283 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1950 10:01:25.099826 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 10:01:25.103525 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1952 10:01:25.107467 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1953 10:01:25.113475 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1954 10:01:25.116927 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1955 10:01:25.120156 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1956 10:01:25.126803 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1957 10:01:25.130833 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1958 10:01:25.133202 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1959 10:01:25.140006 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1960 10:01:25.143183 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1961 10:01:25.146739 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1962 10:01:25.153102 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1963 10:01:25.156572 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1964 10:01:25.160130 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1965 10:01:25.166269 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1966 10:01:25.169655 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1967 10:01:25.173463 Total UI for P1: 0, mck2ui 16
1968 10:01:25.176371 best dqsien dly found for B0: ( 0, 14, 8)
1969 10:01:25.180281 Total UI for P1: 0, mck2ui 16
1970 10:01:25.183527 best dqsien dly found for B1: ( 0, 14, 8)
1971 10:01:25.186005 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1972 10:01:25.189268 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1973 10:01:25.189758
1974 10:01:25.193025 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1975 10:01:25.196047 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1976 10:01:25.199091 [Gating] SW calibration Done
1977 10:01:25.199603 ==
1978 10:01:25.202467 Dram Type= 6, Freq= 0, CH_1, rank 1
1979 10:01:25.209301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1980 10:01:25.209928 ==
1981 10:01:25.210298 RX Vref Scan: 0
1982 10:01:25.210639
1983 10:01:25.213278 RX Vref 0 -> 0, step: 1
1984 10:01:25.213825
1985 10:01:25.215923 RX Delay -130 -> 252, step: 16
1986 10:01:25.219111 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1987 10:01:25.222390 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1988 10:01:25.225759 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1989 10:01:25.232570 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1990 10:01:25.235992 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1991 10:01:25.239002 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1992 10:01:25.242452 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1993 10:01:25.245635 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1994 10:01:25.249513 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1995 10:01:25.255540 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1996 10:01:25.258918 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1997 10:01:25.262202 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1998 10:01:25.265375 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1999 10:01:25.272275 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
2000 10:01:25.275689 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
2001 10:01:25.279408 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
2002 10:01:25.279823 ==
2003 10:01:25.282210 Dram Type= 6, Freq= 0, CH_1, rank 1
2004 10:01:25.285692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2005 10:01:25.286110 ==
2006 10:01:25.289020 DQS Delay:
2007 10:01:25.289450 DQS0 = 0, DQS1 = 0
2008 10:01:25.292275 DQM Delay:
2009 10:01:25.292782 DQM0 = 87, DQM1 = 78
2010 10:01:25.293115 DQ Delay:
2011 10:01:25.295977 DQ0 =93, DQ1 =77, DQ2 =69, DQ3 =85
2012 10:01:25.299060 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
2013 10:01:25.301738 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =61
2014 10:01:25.305277 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =85
2015 10:01:25.305747
2016 10:01:25.308856
2017 10:01:25.309280 ==
2018 10:01:25.312128 Dram Type= 6, Freq= 0, CH_1, rank 1
2019 10:01:25.315299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2020 10:01:25.315825 ==
2021 10:01:25.316161
2022 10:01:25.316465
2023 10:01:25.319081 TX Vref Scan disable
2024 10:01:25.319496 == TX Byte 0 ==
2025 10:01:25.325399 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2026 10:01:25.328645 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2027 10:01:25.329095 == TX Byte 1 ==
2028 10:01:25.335533 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2029 10:01:25.338904 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2030 10:01:25.339431 ==
2031 10:01:25.341563 Dram Type= 6, Freq= 0, CH_1, rank 1
2032 10:01:25.345269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2033 10:01:25.345796 ==
2034 10:01:25.358659 TX Vref=22, minBit 1, minWin=27, winSum=448
2035 10:01:25.362068 TX Vref=24, minBit 8, minWin=27, winSum=446
2036 10:01:25.365984 TX Vref=26, minBit 9, minWin=27, winSum=451
2037 10:01:25.369210 TX Vref=28, minBit 8, minWin=27, winSum=450
2038 10:01:25.372790 TX Vref=30, minBit 13, minWin=27, winSum=448
2039 10:01:25.379644 TX Vref=32, minBit 8, minWin=27, winSum=450
2040 10:01:25.381902 [TxChooseVref] Worse bit 9, Min win 27, Win sum 451, Final Vref 26
2041 10:01:25.382429
2042 10:01:25.385499 Final TX Range 1 Vref 26
2043 10:01:25.386067
2044 10:01:25.386439 ==
2045 10:01:25.388433 Dram Type= 6, Freq= 0, CH_1, rank 1
2046 10:01:25.392386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2047 10:01:25.395494 ==
2048 10:01:25.396049
2049 10:01:25.396411
2050 10:01:25.396746 TX Vref Scan disable
2051 10:01:25.398826 == TX Byte 0 ==
2052 10:01:25.402276 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2053 10:01:25.408845 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2054 10:01:25.409449 == TX Byte 1 ==
2055 10:01:25.412241 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2056 10:01:25.419206 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2057 10:01:25.419761
2058 10:01:25.420125 [DATLAT]
2059 10:01:25.420462 Freq=800, CH1 RK1
2060 10:01:25.420791
2061 10:01:25.422305 DATLAT Default: 0xa
2062 10:01:25.422815 0, 0xFFFF, sum = 0
2063 10:01:25.425582 1, 0xFFFF, sum = 0
2064 10:01:25.428644 2, 0xFFFF, sum = 0
2065 10:01:25.429107 3, 0xFFFF, sum = 0
2066 10:01:25.432163 4, 0xFFFF, sum = 0
2067 10:01:25.432726 5, 0xFFFF, sum = 0
2068 10:01:25.435918 6, 0xFFFF, sum = 0
2069 10:01:25.436476 7, 0xFFFF, sum = 0
2070 10:01:25.438727 8, 0xFFFF, sum = 0
2071 10:01:25.439291 9, 0x0, sum = 1
2072 10:01:25.441864 10, 0x0, sum = 2
2073 10:01:25.442327 11, 0x0, sum = 3
2074 10:01:25.442698 12, 0x0, sum = 4
2075 10:01:25.445924 best_step = 10
2076 10:01:25.446378
2077 10:01:25.446743 ==
2078 10:01:25.448792 Dram Type= 6, Freq= 0, CH_1, rank 1
2079 10:01:25.451685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2080 10:01:25.452149 ==
2081 10:01:25.455249 RX Vref Scan: 0
2082 10:01:25.455815
2083 10:01:25.456181 RX Vref 0 -> 0, step: 1
2084 10:01:25.458760
2085 10:01:25.459214 RX Delay -111 -> 252, step: 8
2086 10:01:25.465402 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2087 10:01:25.468997 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2088 10:01:25.472282 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2089 10:01:25.475537 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2090 10:01:25.478827 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2091 10:01:25.485767 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2092 10:01:25.488696 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2093 10:01:25.491947 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2094 10:01:25.495339 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2095 10:01:25.498898 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2096 10:01:25.505379 iDelay=217, Bit 10, Center 84 (-31 ~ 200) 232
2097 10:01:25.509184 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2098 10:01:25.512272 iDelay=217, Bit 12, Center 88 (-23 ~ 200) 224
2099 10:01:25.515381 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2100 10:01:25.522189 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
2101 10:01:25.525515 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2102 10:01:25.525933 ==
2103 10:01:25.528798 Dram Type= 6, Freq= 0, CH_1, rank 1
2104 10:01:25.531868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2105 10:01:25.532283 ==
2106 10:01:25.532614 DQS Delay:
2107 10:01:25.535154 DQS0 = 0, DQS1 = 0
2108 10:01:25.535565 DQM Delay:
2109 10:01:25.539162 DQM0 = 87, DQM1 = 79
2110 10:01:25.539677 DQ Delay:
2111 10:01:25.542981 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2112 10:01:25.545911 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2113 10:01:25.548931 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68
2114 10:01:25.552368 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
2115 10:01:25.552889
2116 10:01:25.553218
2117 10:01:25.562299 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b14, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 403 ps
2118 10:01:25.562834 CH1 RK1: MR19=606, MR18=1B14
2119 10:01:25.568754 CH1_RK1: MR19=0x606, MR18=0x1B14, DQSOSC=403, MR23=63, INC=90, DEC=60
2120 10:01:25.572252 [RxdqsGatingPostProcess] freq 800
2121 10:01:25.578371 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2122 10:01:25.582022 Pre-setting of DQS Precalculation
2123 10:01:25.585329 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2124 10:01:25.591677 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2125 10:01:25.601673 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2126 10:01:25.602191
2127 10:01:25.602563
2128 10:01:25.605201 [Calibration Summary] 1600 Mbps
2129 10:01:25.605754 CH 0, Rank 0
2130 10:01:25.608787 SW Impedance : PASS
2131 10:01:25.609297 DUTY Scan : NO K
2132 10:01:25.611863 ZQ Calibration : PASS
2133 10:01:25.615333 Jitter Meter : NO K
2134 10:01:25.615849 CBT Training : PASS
2135 10:01:25.618597 Write leveling : PASS
2136 10:01:25.619250 RX DQS gating : PASS
2137 10:01:25.621742 RX DQ/DQS(RDDQC) : PASS
2138 10:01:25.624667 TX DQ/DQS : PASS
2139 10:01:25.625080 RX DATLAT : PASS
2140 10:01:25.628690 RX DQ/DQS(Engine): PASS
2141 10:01:25.631628 TX OE : NO K
2142 10:01:25.632042 All Pass.
2143 10:01:25.632374
2144 10:01:25.632678 CH 0, Rank 1
2145 10:01:25.635072 SW Impedance : PASS
2146 10:01:25.638552 DUTY Scan : NO K
2147 10:01:25.639111 ZQ Calibration : PASS
2148 10:01:25.641328 Jitter Meter : NO K
2149 10:01:25.644857 CBT Training : PASS
2150 10:01:25.645313 Write leveling : PASS
2151 10:01:25.648095 RX DQS gating : PASS
2152 10:01:25.651856 RX DQ/DQS(RDDQC) : PASS
2153 10:01:25.652411 TX DQ/DQS : PASS
2154 10:01:25.655287 RX DATLAT : PASS
2155 10:01:25.658155 RX DQ/DQS(Engine): PASS
2156 10:01:25.658711 TX OE : NO K
2157 10:01:25.661477 All Pass.
2158 10:01:25.662033
2159 10:01:25.662392 CH 1, Rank 0
2160 10:01:25.664883 SW Impedance : PASS
2161 10:01:25.665510 DUTY Scan : NO K
2162 10:01:25.668117 ZQ Calibration : PASS
2163 10:01:25.671199 Jitter Meter : NO K
2164 10:01:25.671659 CBT Training : PASS
2165 10:01:25.675082 Write leveling : PASS
2166 10:01:25.675637 RX DQS gating : PASS
2167 10:01:25.677869 RX DQ/DQS(RDDQC) : PASS
2168 10:01:25.681391 TX DQ/DQS : PASS
2169 10:01:25.681986 RX DATLAT : PASS
2170 10:01:25.684955 RX DQ/DQS(Engine): PASS
2171 10:01:25.688412 TX OE : NO K
2172 10:01:25.688968 All Pass.
2173 10:01:25.689333
2174 10:01:25.689714 CH 1, Rank 1
2175 10:01:25.691060 SW Impedance : PASS
2176 10:01:25.694429 DUTY Scan : NO K
2177 10:01:25.694885 ZQ Calibration : PASS
2178 10:01:25.697739 Jitter Meter : NO K
2179 10:01:25.701094 CBT Training : PASS
2180 10:01:25.701641 Write leveling : PASS
2181 10:01:25.704558 RX DQS gating : PASS
2182 10:01:25.707890 RX DQ/DQS(RDDQC) : PASS
2183 10:01:25.708345 TX DQ/DQS : PASS
2184 10:01:25.711082 RX DATLAT : PASS
2185 10:01:25.714439 RX DQ/DQS(Engine): PASS
2186 10:01:25.714889 TX OE : NO K
2187 10:01:25.715230 All Pass.
2188 10:01:25.717497
2189 10:01:25.717910 DramC Write-DBI off
2190 10:01:25.721514 PER_BANK_REFRESH: Hybrid Mode
2191 10:01:25.722029 TX_TRACKING: ON
2192 10:01:25.724504 [GetDramInforAfterCalByMRR] Vendor 6.
2193 10:01:25.727394 [GetDramInforAfterCalByMRR] Revision 606.
2194 10:01:25.734768 [GetDramInforAfterCalByMRR] Revision 2 0.
2195 10:01:25.735283 MR0 0x3b3b
2196 10:01:25.735614 MR8 0x5151
2197 10:01:25.738059 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2198 10:01:25.738577
2199 10:01:25.740746 MR0 0x3b3b
2200 10:01:25.741157 MR8 0x5151
2201 10:01:25.744241 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2202 10:01:25.744657
2203 10:01:25.755084 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2204 10:01:25.757504 [FAST_K] Save calibration result to emmc
2205 10:01:25.761054 [FAST_K] Save calibration result to emmc
2206 10:01:25.764667 dram_init: config_dvfs: 1
2207 10:01:25.768006 dramc_set_vcore_voltage set vcore to 662500
2208 10:01:25.771221 Read voltage for 1200, 2
2209 10:01:25.771639 Vio18 = 0
2210 10:01:25.771974 Vcore = 662500
2211 10:01:25.772277 Vdram = 0
2212 10:01:25.774180 Vddq = 0
2213 10:01:25.774592 Vmddr = 0
2214 10:01:25.780987 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2215 10:01:25.784779 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2216 10:01:25.788237 MEM_TYPE=3, freq_sel=15
2217 10:01:25.790712 sv_algorithm_assistance_LP4_1600
2218 10:01:25.794389 ============ PULL DRAM RESETB DOWN ============
2219 10:01:25.798078 ========== PULL DRAM RESETB DOWN end =========
2220 10:01:25.804096 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2221 10:01:25.807991 ===================================
2222 10:01:25.808502 LPDDR4 DRAM CONFIGURATION
2223 10:01:25.811924 ===================================
2224 10:01:25.814433 EX_ROW_EN[0] = 0x0
2225 10:01:25.817757 EX_ROW_EN[1] = 0x0
2226 10:01:25.818273 LP4Y_EN = 0x0
2227 10:01:25.820706 WORK_FSP = 0x0
2228 10:01:25.821118 WL = 0x4
2229 10:01:25.824114 RL = 0x4
2230 10:01:25.824694 BL = 0x2
2231 10:01:25.827700 RPST = 0x0
2232 10:01:25.828269 RD_PRE = 0x0
2233 10:01:25.831064 WR_PRE = 0x1
2234 10:01:25.831578 WR_PST = 0x0
2235 10:01:25.834270 DBI_WR = 0x0
2236 10:01:25.834789 DBI_RD = 0x0
2237 10:01:25.837568 OTF = 0x1
2238 10:01:25.840896 ===================================
2239 10:01:25.844118 ===================================
2240 10:01:25.844535 ANA top config
2241 10:01:25.847338 ===================================
2242 10:01:25.850190 DLL_ASYNC_EN = 0
2243 10:01:25.853479 ALL_SLAVE_EN = 0
2244 10:01:25.857075 NEW_RANK_MODE = 1
2245 10:01:25.857641 DLL_IDLE_MODE = 1
2246 10:01:25.860213 LP45_APHY_COMB_EN = 1
2247 10:01:25.863774 TX_ODT_DIS = 1
2248 10:01:25.866712 NEW_8X_MODE = 1
2249 10:01:25.870834 ===================================
2250 10:01:25.873854 ===================================
2251 10:01:25.877575 data_rate = 2400
2252 10:01:25.878092 CKR = 1
2253 10:01:25.880662 DQ_P2S_RATIO = 8
2254 10:01:25.883481 ===================================
2255 10:01:25.887556 CA_P2S_RATIO = 8
2256 10:01:25.890335 DQ_CA_OPEN = 0
2257 10:01:25.894027 DQ_SEMI_OPEN = 0
2258 10:01:25.897013 CA_SEMI_OPEN = 0
2259 10:01:25.897453 CA_FULL_RATE = 0
2260 10:01:25.899889 DQ_CKDIV4_EN = 0
2261 10:01:25.903475 CA_CKDIV4_EN = 0
2262 10:01:25.907005 CA_PREDIV_EN = 0
2263 10:01:25.910285 PH8_DLY = 17
2264 10:01:25.910701 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2265 10:01:25.913600 DQ_AAMCK_DIV = 4
2266 10:01:25.916901 CA_AAMCK_DIV = 4
2267 10:01:25.920545 CA_ADMCK_DIV = 4
2268 10:01:25.923654 DQ_TRACK_CA_EN = 0
2269 10:01:25.926629 CA_PICK = 1200
2270 10:01:25.930600 CA_MCKIO = 1200
2271 10:01:25.931125 MCKIO_SEMI = 0
2272 10:01:25.933851 PLL_FREQ = 2366
2273 10:01:25.936888 DQ_UI_PI_RATIO = 32
2274 10:01:25.940101 CA_UI_PI_RATIO = 0
2275 10:01:25.943366 ===================================
2276 10:01:25.946932 ===================================
2277 10:01:25.949933 memory_type:LPDDR4
2278 10:01:25.950449 GP_NUM : 10
2279 10:01:25.953096 SRAM_EN : 1
2280 10:01:25.956302 MD32_EN : 0
2281 10:01:25.959688 ===================================
2282 10:01:25.960103 [ANA_INIT] >>>>>>>>>>>>>>
2283 10:01:25.963976 <<<<<< [CONFIGURE PHASE]: ANA_TX
2284 10:01:25.966077 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2285 10:01:25.969784 ===================================
2286 10:01:25.972966 data_rate = 2400,PCW = 0X5b00
2287 10:01:25.976782 ===================================
2288 10:01:25.979684 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2289 10:01:25.986841 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2290 10:01:25.990018 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2291 10:01:25.996274 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2292 10:01:25.999395 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2293 10:01:26.002655 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2294 10:01:26.006617 [ANA_INIT] flow start
2295 10:01:26.007225 [ANA_INIT] PLL >>>>>>>>
2296 10:01:26.009393 [ANA_INIT] PLL <<<<<<<<
2297 10:01:26.013210 [ANA_INIT] MIDPI >>>>>>>>
2298 10:01:26.013771 [ANA_INIT] MIDPI <<<<<<<<
2299 10:01:26.016177 [ANA_INIT] DLL >>>>>>>>
2300 10:01:26.019363 [ANA_INIT] DLL <<<<<<<<
2301 10:01:26.019777 [ANA_INIT] flow end
2302 10:01:26.023431 ============ LP4 DIFF to SE enter ============
2303 10:01:26.029579 ============ LP4 DIFF to SE exit ============
2304 10:01:26.030113 [ANA_INIT] <<<<<<<<<<<<<
2305 10:01:26.033124 [Flow] Enable top DCM control >>>>>
2306 10:01:26.037502 [Flow] Enable top DCM control <<<<<
2307 10:01:26.039493 Enable DLL master slave shuffle
2308 10:01:26.046873 ==============================================================
2309 10:01:26.047394 Gating Mode config
2310 10:01:26.053252 ==============================================================
2311 10:01:26.056286 Config description:
2312 10:01:26.066264 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2313 10:01:26.072748 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2314 10:01:26.075851 SELPH_MODE 0: By rank 1: By Phase
2315 10:01:26.082655 ==============================================================
2316 10:01:26.085731 GAT_TRACK_EN = 1
2317 10:01:26.088648 RX_GATING_MODE = 2
2318 10:01:26.092730 RX_GATING_TRACK_MODE = 2
2319 10:01:26.093143 SELPH_MODE = 1
2320 10:01:26.095606 PICG_EARLY_EN = 1
2321 10:01:26.098791 VALID_LAT_VALUE = 1
2322 10:01:26.105557 ==============================================================
2323 10:01:26.109229 Enter into Gating configuration >>>>
2324 10:01:26.112202 Exit from Gating configuration <<<<
2325 10:01:26.115379 Enter into DVFS_PRE_config >>>>>
2326 10:01:26.125347 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2327 10:01:26.128605 Exit from DVFS_PRE_config <<<<<
2328 10:01:26.132385 Enter into PICG configuration >>>>
2329 10:01:26.135268 Exit from PICG configuration <<<<
2330 10:01:26.139091 [RX_INPUT] configuration >>>>>
2331 10:01:26.142417 [RX_INPUT] configuration <<<<<
2332 10:01:26.145002 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2333 10:01:26.152213 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2334 10:01:26.158578 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2335 10:01:26.165341 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2336 10:01:26.171468 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2337 10:01:26.175406 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2338 10:01:26.181519 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2339 10:01:26.184918 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2340 10:01:26.188455 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2341 10:01:26.192584 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2342 10:01:26.198557 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2343 10:01:26.201565 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2344 10:01:26.204788 ===================================
2345 10:01:26.208165 LPDDR4 DRAM CONFIGURATION
2346 10:01:26.211422 ===================================
2347 10:01:26.211883 EX_ROW_EN[0] = 0x0
2348 10:01:26.214765 EX_ROW_EN[1] = 0x0
2349 10:01:26.215220 LP4Y_EN = 0x0
2350 10:01:26.218001 WORK_FSP = 0x0
2351 10:01:26.218455 WL = 0x4
2352 10:01:26.221362 RL = 0x4
2353 10:01:26.221866 BL = 0x2
2354 10:01:26.225126 RPST = 0x0
2355 10:01:26.225741 RD_PRE = 0x0
2356 10:01:26.228304 WR_PRE = 0x1
2357 10:01:26.231213 WR_PST = 0x0
2358 10:01:26.231795 DBI_WR = 0x0
2359 10:01:26.234784 DBI_RD = 0x0
2360 10:01:26.235267 OTF = 0x1
2361 10:01:26.238031 ===================================
2362 10:01:26.241568 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2363 10:01:26.244836 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2364 10:01:26.251201 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2365 10:01:26.254639 ===================================
2366 10:01:26.257712 LPDDR4 DRAM CONFIGURATION
2367 10:01:26.261372 ===================================
2368 10:01:26.261941 EX_ROW_EN[0] = 0x10
2369 10:01:26.264798 EX_ROW_EN[1] = 0x0
2370 10:01:26.265348 LP4Y_EN = 0x0
2371 10:01:26.267828 WORK_FSP = 0x0
2372 10:01:26.268392 WL = 0x4
2373 10:01:26.271079 RL = 0x4
2374 10:01:26.271578 BL = 0x2
2375 10:01:26.274060 RPST = 0x0
2376 10:01:26.274468 RD_PRE = 0x0
2377 10:01:26.277982 WR_PRE = 0x1
2378 10:01:26.278491 WR_PST = 0x0
2379 10:01:26.281171 DBI_WR = 0x0
2380 10:01:26.284826 DBI_RD = 0x0
2381 10:01:26.285336 OTF = 0x1
2382 10:01:26.288653 ===================================
2383 10:01:26.294821 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2384 10:01:26.295344 ==
2385 10:01:26.297996 Dram Type= 6, Freq= 0, CH_0, rank 0
2386 10:01:26.301163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2387 10:01:26.301729 ==
2388 10:01:26.303985 [Duty_Offset_Calibration]
2389 10:01:26.304405 B0:1 B1:-1 CA:0
2390 10:01:26.307277
2391 10:01:26.310912 [DutyScan_Calibration_Flow] k_type=0
2392 10:01:26.318784
2393 10:01:26.319251 ==CLK 0==
2394 10:01:26.321845 Final CLK duty delay cell = 0
2395 10:01:26.324895 [0] MAX Duty = 5094%(X100), DQS PI = 16
2396 10:01:26.328902 [0] MIN Duty = 4875%(X100), DQS PI = 8
2397 10:01:26.329496 [0] AVG Duty = 4984%(X100)
2398 10:01:26.332195
2399 10:01:26.335347 CH0 CLK Duty spec in!! Max-Min= 219%
2400 10:01:26.338576 [DutyScan_Calibration_Flow] ====Done====
2401 10:01:26.338987
2402 10:01:26.342058 [DutyScan_Calibration_Flow] k_type=1
2403 10:01:26.356648
2404 10:01:26.357160 ==DQS 0 ==
2405 10:01:26.359965 Final DQS duty delay cell = -4
2406 10:01:26.363412 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2407 10:01:26.366255 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2408 10:01:26.370207 [-4] AVG Duty = 4968%(X100)
2409 10:01:26.370614
2410 10:01:26.371001 ==DQS 1 ==
2411 10:01:26.373011 Final DQS duty delay cell = -4
2412 10:01:26.376815 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2413 10:01:26.379485 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2414 10:01:26.382843 [-4] AVG Duty = 4938%(X100)
2415 10:01:26.383257
2416 10:01:26.386888 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2417 10:01:26.387345
2418 10:01:26.389561 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2419 10:01:26.392765 [DutyScan_Calibration_Flow] ====Done====
2420 10:01:26.393371
2421 10:01:26.396811 [DutyScan_Calibration_Flow] k_type=3
2422 10:01:26.414988
2423 10:01:26.415511 ==DQM 0 ==
2424 10:01:26.417529 Final DQM duty delay cell = 0
2425 10:01:26.421076 [0] MAX Duty = 5062%(X100), DQS PI = 18
2426 10:01:26.424441 [0] MIN Duty = 4875%(X100), DQS PI = 8
2427 10:01:26.427711 [0] AVG Duty = 4968%(X100)
2428 10:01:26.428270
2429 10:01:26.428630 ==DQM 1 ==
2430 10:01:26.430803 Final DQM duty delay cell = 4
2431 10:01:26.433757 [4] MAX Duty = 5187%(X100), DQS PI = 16
2432 10:01:26.437544 [4] MIN Duty = 5000%(X100), DQS PI = 24
2433 10:01:26.440865 [4] AVG Duty = 5093%(X100)
2434 10:01:26.441377
2435 10:01:26.444140 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2436 10:01:26.444548
2437 10:01:26.446909 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2438 10:01:26.450820 [DutyScan_Calibration_Flow] ====Done====
2439 10:01:26.451329
2440 10:01:26.453564 [DutyScan_Calibration_Flow] k_type=2
2441 10:01:26.470219
2442 10:01:26.470771 ==DQ 0 ==
2443 10:01:26.473382 Final DQ duty delay cell = -4
2444 10:01:26.476710 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2445 10:01:26.480111 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2446 10:01:26.483058 [-4] AVG Duty = 4953%(X100)
2447 10:01:26.483633
2448 10:01:26.483997 ==DQ 1 ==
2449 10:01:26.486277 Final DQ duty delay cell = 0
2450 10:01:26.489526 [0] MAX Duty = 5093%(X100), DQS PI = 4
2451 10:01:26.492989 [0] MIN Duty = 4969%(X100), DQS PI = 40
2452 10:01:26.496785 [0] AVG Duty = 5031%(X100)
2453 10:01:26.497236
2454 10:01:26.499693 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2455 10:01:26.500144
2456 10:01:26.503458 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2457 10:01:26.507088 [DutyScan_Calibration_Flow] ====Done====
2458 10:01:26.507497 ==
2459 10:01:26.509994 Dram Type= 6, Freq= 0, CH_1, rank 0
2460 10:01:26.513340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2461 10:01:26.513781 ==
2462 10:01:26.516486 [Duty_Offset_Calibration]
2463 10:01:26.516847 B0:-1 B1:1 CA:2
2464 10:01:26.517157
2465 10:01:26.519899 [DutyScan_Calibration_Flow] k_type=0
2466 10:01:26.530036
2467 10:01:26.530575 ==CLK 0==
2468 10:01:26.534249 Final CLK duty delay cell = 0
2469 10:01:26.536741 [0] MAX Duty = 5156%(X100), DQS PI = 22
2470 10:01:26.540402 [0] MIN Duty = 4969%(X100), DQS PI = 62
2471 10:01:26.540812 [0] AVG Duty = 5062%(X100)
2472 10:01:26.543529
2473 10:01:26.546582 CH1 CLK Duty spec in!! Max-Min= 187%
2474 10:01:26.550150 [DutyScan_Calibration_Flow] ====Done====
2475 10:01:26.550663
2476 10:01:26.553805 [DutyScan_Calibration_Flow] k_type=1
2477 10:01:26.569571
2478 10:01:26.570184 ==DQS 0 ==
2479 10:01:26.573222 Final DQS duty delay cell = 0
2480 10:01:26.576787 [0] MAX Duty = 5125%(X100), DQS PI = 48
2481 10:01:26.579148 [0] MIN Duty = 4875%(X100), DQS PI = 8
2482 10:01:26.582774 [0] AVG Duty = 5000%(X100)
2483 10:01:26.583225
2484 10:01:26.583580 ==DQS 1 ==
2485 10:01:26.586557 Final DQS duty delay cell = 0
2486 10:01:26.589571 [0] MAX Duty = 5094%(X100), DQS PI = 12
2487 10:01:26.592707 [0] MIN Duty = 4969%(X100), DQS PI = 58
2488 10:01:26.595772 [0] AVG Duty = 5031%(X100)
2489 10:01:26.596227
2490 10:01:26.598946 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2491 10:01:26.599421
2492 10:01:26.602599 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2493 10:01:26.605982 [DutyScan_Calibration_Flow] ====Done====
2494 10:01:26.606551
2495 10:01:26.609086 [DutyScan_Calibration_Flow] k_type=3
2496 10:01:26.625574
2497 10:01:26.626216 ==DQM 0 ==
2498 10:01:26.628600 Final DQM duty delay cell = -4
2499 10:01:26.632493 [-4] MAX Duty = 5031%(X100), DQS PI = 16
2500 10:01:26.635530 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2501 10:01:26.639156 [-4] AVG Duty = 4937%(X100)
2502 10:01:26.639715
2503 10:01:26.640077 ==DQM 1 ==
2504 10:01:26.641528 Final DQM duty delay cell = 0
2505 10:01:26.645463 [0] MAX Duty = 5187%(X100), DQS PI = 6
2506 10:01:26.648361 [0] MIN Duty = 5000%(X100), DQS PI = 28
2507 10:01:26.652485 [0] AVG Duty = 5093%(X100)
2508 10:01:26.653038
2509 10:01:26.655397 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2510 10:01:26.655952
2511 10:01:26.658582 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2512 10:01:26.661668 [DutyScan_Calibration_Flow] ====Done====
2513 10:01:26.662124
2514 10:01:26.664922 [DutyScan_Calibration_Flow] k_type=2
2515 10:01:26.682168
2516 10:01:26.682721 ==DQ 0 ==
2517 10:01:26.685333 Final DQ duty delay cell = 0
2518 10:01:26.688787 [0] MAX Duty = 5156%(X100), DQS PI = 28
2519 10:01:26.692024 [0] MIN Duty = 4876%(X100), DQS PI = 8
2520 10:01:26.692589 [0] AVG Duty = 5016%(X100)
2521 10:01:26.692958
2522 10:01:26.695646 ==DQ 1 ==
2523 10:01:26.698656 Final DQ duty delay cell = 0
2524 10:01:26.701744 [0] MAX Duty = 5124%(X100), DQS PI = 10
2525 10:01:26.704854 [0] MIN Duty = 4969%(X100), DQS PI = 0
2526 10:01:26.705313 [0] AVG Duty = 5046%(X100)
2527 10:01:26.705784
2528 10:01:26.708604 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2529 10:01:26.711582
2530 10:01:26.714802 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2531 10:01:26.718073 [DutyScan_Calibration_Flow] ====Done====
2532 10:01:26.722036 nWR fixed to 30
2533 10:01:26.722595 [ModeRegInit_LP4] CH0 RK0
2534 10:01:26.725083 [ModeRegInit_LP4] CH0 RK1
2535 10:01:26.728411 [ModeRegInit_LP4] CH1 RK0
2536 10:01:26.731663 [ModeRegInit_LP4] CH1 RK1
2537 10:01:26.732224 match AC timing 7
2538 10:01:26.735267 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2539 10:01:26.741572 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2540 10:01:26.744779 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2541 10:01:26.751362 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2542 10:01:26.754690 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2543 10:01:26.755252 ==
2544 10:01:26.758131 Dram Type= 6, Freq= 0, CH_0, rank 0
2545 10:01:26.761608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2546 10:01:26.762165 ==
2547 10:01:26.768049 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2548 10:01:26.774890 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2549 10:01:26.781927 [CA 0] Center 39 (9~70) winsize 62
2550 10:01:26.785713 [CA 1] Center 39 (9~70) winsize 62
2551 10:01:26.788728 [CA 2] Center 35 (5~66) winsize 62
2552 10:01:26.791650 [CA 3] Center 35 (5~65) winsize 61
2553 10:01:26.795331 [CA 4] Center 33 (3~64) winsize 62
2554 10:01:26.798139 [CA 5] Center 33 (4~63) winsize 60
2555 10:01:26.798596
2556 10:01:26.801588 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2557 10:01:26.802146
2558 10:01:26.804873 [CATrainingPosCal] consider 1 rank data
2559 10:01:26.808448 u2DelayCellTimex100 = 270/100 ps
2560 10:01:26.811781 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2561 10:01:26.815133 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2562 10:01:26.821918 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2563 10:01:26.825093 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2564 10:01:26.828752 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2565 10:01:26.831681 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2566 10:01:26.832251
2567 10:01:26.835505 CA PerBit enable=1, Macro0, CA PI delay=33
2568 10:01:26.836062
2569 10:01:26.838229 [CBTSetCACLKResult] CA Dly = 33
2570 10:01:26.838687 CS Dly: 8 (0~39)
2571 10:01:26.841777 ==
2572 10:01:26.842332 Dram Type= 6, Freq= 0, CH_0, rank 1
2573 10:01:26.848529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2574 10:01:26.849130 ==
2575 10:01:26.851390 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2576 10:01:26.858792 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2577 10:01:26.867419 [CA 0] Center 39 (9~70) winsize 62
2578 10:01:26.871095 [CA 1] Center 39 (9~70) winsize 62
2579 10:01:26.874713 [CA 2] Center 35 (5~66) winsize 62
2580 10:01:26.877824 [CA 3] Center 34 (4~65) winsize 62
2581 10:01:26.880741 [CA 4] Center 33 (3~64) winsize 62
2582 10:01:26.884090 [CA 5] Center 33 (3~63) winsize 61
2583 10:01:26.884648
2584 10:01:26.887279 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2585 10:01:26.887836
2586 10:01:26.891011 [CATrainingPosCal] consider 2 rank data
2587 10:01:26.894057 u2DelayCellTimex100 = 270/100 ps
2588 10:01:26.897296 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2589 10:01:26.903911 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2590 10:01:26.907649 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2591 10:01:26.911524 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2592 10:01:26.913850 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2593 10:01:26.916966 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2594 10:01:26.917628
2595 10:01:26.920344 CA PerBit enable=1, Macro0, CA PI delay=33
2596 10:01:26.920901
2597 10:01:26.923730 [CBTSetCACLKResult] CA Dly = 33
2598 10:01:26.926931 CS Dly: 9 (0~41)
2599 10:01:26.927576
2600 10:01:26.930302 ----->DramcWriteLeveling(PI) begin...
2601 10:01:26.930763 ==
2602 10:01:26.933662 Dram Type= 6, Freq= 0, CH_0, rank 0
2603 10:01:26.938163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2604 10:01:26.938718 ==
2605 10:01:26.942189 Write leveling (Byte 0): 34 => 34
2606 10:01:26.943383 Write leveling (Byte 1): 30 => 30
2607 10:01:26.946803 DramcWriteLeveling(PI) end<-----
2608 10:01:26.947258
2609 10:01:26.947617 ==
2610 10:01:26.950021 Dram Type= 6, Freq= 0, CH_0, rank 0
2611 10:01:26.954226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2612 10:01:26.954686 ==
2613 10:01:26.957585 [Gating] SW mode calibration
2614 10:01:26.963765 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2615 10:01:26.970134 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2616 10:01:26.973568 0 15 0 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
2617 10:01:26.977036 0 15 4 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
2618 10:01:26.983703 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2619 10:01:26.987021 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2620 10:01:26.989888 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2621 10:01:26.997001 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2622 10:01:27.000380 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2623 10:01:27.003622 0 15 28 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
2624 10:01:27.010487 1 0 0 | B1->B0 | 3131 2323 | 0 0 | (0 1) (1 0)
2625 10:01:27.013453 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2626 10:01:27.017049 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2627 10:01:27.024105 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2628 10:01:27.026780 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2629 10:01:27.030566 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2630 10:01:27.033460 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2631 10:01:27.040109 1 0 28 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
2632 10:01:27.043725 1 1 0 | B1->B0 | 2b2a 4646 | 1 0 | (0 0) (0 0)
2633 10:01:27.046809 1 1 4 | B1->B0 | 3c3c 4646 | 1 0 | (1 1) (0 0)
2634 10:01:27.054001 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2635 10:01:27.057338 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2636 10:01:27.060106 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2637 10:01:27.066897 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2638 10:01:27.070284 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2639 10:01:27.073464 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2640 10:01:27.079862 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2641 10:01:27.083265 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2642 10:01:27.086586 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2643 10:01:27.093074 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2644 10:01:27.096812 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2645 10:01:27.099747 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2646 10:01:27.106468 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2647 10:01:27.110016 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2648 10:01:27.113783 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2649 10:01:27.120221 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2650 10:01:27.122954 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2651 10:01:27.126331 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2652 10:01:27.133920 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2653 10:01:27.136107 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2654 10:01:27.139899 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2655 10:01:27.146551 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2656 10:01:27.147112 Total UI for P1: 0, mck2ui 16
2657 10:01:27.152971 best dqsien dly found for B0: ( 1, 3, 24)
2658 10:01:27.156191 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2659 10:01:27.159755 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2660 10:01:27.162966 Total UI for P1: 0, mck2ui 16
2661 10:01:27.166165 best dqsien dly found for B1: ( 1, 3, 30)
2662 10:01:27.169674 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2663 10:01:27.172614 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2664 10:01:27.173305
2665 10:01:27.175840 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2666 10:01:27.182979 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2667 10:01:27.183442 [Gating] SW calibration Done
2668 10:01:27.183806 ==
2669 10:01:27.186257 Dram Type= 6, Freq= 0, CH_0, rank 0
2670 10:01:27.192619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2671 10:01:27.193234 ==
2672 10:01:27.193712 RX Vref Scan: 0
2673 10:01:27.194059
2674 10:01:27.196238 RX Vref 0 -> 0, step: 1
2675 10:01:27.196817
2676 10:01:27.199304 RX Delay -40 -> 252, step: 8
2677 10:01:27.202387 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2678 10:01:27.206111 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2679 10:01:27.209219 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2680 10:01:27.216189 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2681 10:01:27.219489 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2682 10:01:27.222637 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2683 10:01:27.226147 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2684 10:01:27.229677 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2685 10:01:27.236538 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2686 10:01:27.238869 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2687 10:01:27.242800 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2688 10:01:27.245800 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2689 10:01:27.248794 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2690 10:01:27.255958 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2691 10:01:27.259203 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2692 10:01:27.261976 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2693 10:01:27.262434 ==
2694 10:01:27.266220 Dram Type= 6, Freq= 0, CH_0, rank 0
2695 10:01:27.268894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2696 10:01:27.269357 ==
2697 10:01:27.272216 DQS Delay:
2698 10:01:27.272797 DQS0 = 0, DQS1 = 0
2699 10:01:27.275297 DQM Delay:
2700 10:01:27.275752 DQM0 = 119, DQM1 = 107
2701 10:01:27.278905 DQ Delay:
2702 10:01:27.282170 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2703 10:01:27.285289 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =127
2704 10:01:27.288792 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2705 10:01:27.291777 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2706 10:01:27.292366
2707 10:01:27.292753
2708 10:01:27.293090 ==
2709 10:01:27.295330 Dram Type= 6, Freq= 0, CH_0, rank 0
2710 10:01:27.298627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2711 10:01:27.299088 ==
2712 10:01:27.299450
2713 10:01:27.299879
2714 10:01:27.302487 TX Vref Scan disable
2715 10:01:27.305119 == TX Byte 0 ==
2716 10:01:27.308311 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2717 10:01:27.312284 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2718 10:01:27.315496 == TX Byte 1 ==
2719 10:01:27.318666 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2720 10:01:27.322423 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2721 10:01:27.322987 ==
2722 10:01:27.325140 Dram Type= 6, Freq= 0, CH_0, rank 0
2723 10:01:27.328703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2724 10:01:27.331791 ==
2725 10:01:27.342369 TX Vref=22, minBit 5, minWin=25, winSum=421
2726 10:01:27.345313 TX Vref=24, minBit 1, minWin=26, winSum=428
2727 10:01:27.348711 TX Vref=26, minBit 13, minWin=25, winSum=432
2728 10:01:27.351865 TX Vref=28, minBit 11, minWin=26, winSum=436
2729 10:01:27.355575 TX Vref=30, minBit 10, minWin=26, winSum=437
2730 10:01:27.361980 TX Vref=32, minBit 4, minWin=26, winSum=433
2731 10:01:27.365678 [TxChooseVref] Worse bit 10, Min win 26, Win sum 437, Final Vref 30
2732 10:01:27.366247
2733 10:01:27.368654 Final TX Range 1 Vref 30
2734 10:01:27.369114
2735 10:01:27.369533 ==
2736 10:01:27.371916 Dram Type= 6, Freq= 0, CH_0, rank 0
2737 10:01:27.378007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2738 10:01:27.378476 ==
2739 10:01:27.378863
2740 10:01:27.379201
2741 10:01:27.379526 TX Vref Scan disable
2742 10:01:27.382040 == TX Byte 0 ==
2743 10:01:27.385484 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2744 10:01:27.392515 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2745 10:01:27.393082 == TX Byte 1 ==
2746 10:01:27.395871 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2747 10:01:27.402092 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2748 10:01:27.402573
2749 10:01:27.402939 [DATLAT]
2750 10:01:27.403279 Freq=1200, CH0 RK0
2751 10:01:27.403606
2752 10:01:27.405591 DATLAT Default: 0xd
2753 10:01:27.406049 0, 0xFFFF, sum = 0
2754 10:01:27.408938 1, 0xFFFF, sum = 0
2755 10:01:27.412488 2, 0xFFFF, sum = 0
2756 10:01:27.413261 3, 0xFFFF, sum = 0
2757 10:01:27.415883 4, 0xFFFF, sum = 0
2758 10:01:27.416348 5, 0xFFFF, sum = 0
2759 10:01:27.418582 6, 0xFFFF, sum = 0
2760 10:01:27.419050 7, 0xFFFF, sum = 0
2761 10:01:27.421918 8, 0xFFFF, sum = 0
2762 10:01:27.422343 9, 0xFFFF, sum = 0
2763 10:01:27.425346 10, 0xFFFF, sum = 0
2764 10:01:27.425815 11, 0xFFFF, sum = 0
2765 10:01:27.428508 12, 0x0, sum = 1
2766 10:01:27.428930 13, 0x0, sum = 2
2767 10:01:27.432009 14, 0x0, sum = 3
2768 10:01:27.432535 15, 0x0, sum = 4
2769 10:01:27.435411 best_step = 13
2770 10:01:27.435958
2771 10:01:27.436293 ==
2772 10:01:27.438381 Dram Type= 6, Freq= 0, CH_0, rank 0
2773 10:01:27.441811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2774 10:01:27.442230 ==
2775 10:01:27.442563 RX Vref Scan: 1
2776 10:01:27.445000
2777 10:01:27.445445 Set Vref Range= 32 -> 127
2778 10:01:27.445785
2779 10:01:27.449120 RX Vref 32 -> 127, step: 1
2780 10:01:27.449570
2781 10:01:27.451535 RX Delay -21 -> 252, step: 4
2782 10:01:27.451952
2783 10:01:27.455347 Set Vref, RX VrefLevel [Byte0]: 32
2784 10:01:27.458809 [Byte1]: 32
2785 10:01:27.459332
2786 10:01:27.461863 Set Vref, RX VrefLevel [Byte0]: 33
2787 10:01:27.464871 [Byte1]: 33
2788 10:01:27.468912
2789 10:01:27.469485 Set Vref, RX VrefLevel [Byte0]: 34
2790 10:01:27.471943 [Byte1]: 34
2791 10:01:27.476543
2792 10:01:27.476957 Set Vref, RX VrefLevel [Byte0]: 35
2793 10:01:27.479912 [Byte1]: 35
2794 10:01:27.484552
2795 10:01:27.485004 Set Vref, RX VrefLevel [Byte0]: 36
2796 10:01:27.488093 [Byte1]: 36
2797 10:01:27.492530
2798 10:01:27.492942 Set Vref, RX VrefLevel [Byte0]: 37
2799 10:01:27.496372 [Byte1]: 37
2800 10:01:27.500612
2801 10:01:27.501130 Set Vref, RX VrefLevel [Byte0]: 38
2802 10:01:27.503546 [Byte1]: 38
2803 10:01:27.508208
2804 10:01:27.508722 Set Vref, RX VrefLevel [Byte0]: 39
2805 10:01:27.511648 [Byte1]: 39
2806 10:01:27.516356
2807 10:01:27.516922 Set Vref, RX VrefLevel [Byte0]: 40
2808 10:01:27.519642 [Byte1]: 40
2809 10:01:27.524244
2810 10:01:27.524802 Set Vref, RX VrefLevel [Byte0]: 41
2811 10:01:27.527667 [Byte1]: 41
2812 10:01:27.531910
2813 10:01:27.532393 Set Vref, RX VrefLevel [Byte0]: 42
2814 10:01:27.535683 [Byte1]: 42
2815 10:01:27.540215
2816 10:01:27.540768 Set Vref, RX VrefLevel [Byte0]: 43
2817 10:01:27.543431 [Byte1]: 43
2818 10:01:27.548104
2819 10:01:27.548559 Set Vref, RX VrefLevel [Byte0]: 44
2820 10:01:27.551131 [Byte1]: 44
2821 10:01:27.556245
2822 10:01:27.556773 Set Vref, RX VrefLevel [Byte0]: 45
2823 10:01:27.559124 [Byte1]: 45
2824 10:01:27.563759
2825 10:01:27.564247 Set Vref, RX VrefLevel [Byte0]: 46
2826 10:01:27.566987 [Byte1]: 46
2827 10:01:27.571512
2828 10:01:27.571924 Set Vref, RX VrefLevel [Byte0]: 47
2829 10:01:27.575263 [Byte1]: 47
2830 10:01:27.579801
2831 10:01:27.580210 Set Vref, RX VrefLevel [Byte0]: 48
2832 10:01:27.582637 [Byte1]: 48
2833 10:01:27.587760
2834 10:01:27.588172 Set Vref, RX VrefLevel [Byte0]: 49
2835 10:01:27.590535 [Byte1]: 49
2836 10:01:27.595596
2837 10:01:27.595823 Set Vref, RX VrefLevel [Byte0]: 50
2838 10:01:27.598413 [Byte1]: 50
2839 10:01:27.603374
2840 10:01:27.603550 Set Vref, RX VrefLevel [Byte0]: 51
2841 10:01:27.606046 [Byte1]: 51
2842 10:01:27.610767
2843 10:01:27.610894 Set Vref, RX VrefLevel [Byte0]: 52
2844 10:01:27.614822 [Byte1]: 52
2845 10:01:27.618860
2846 10:01:27.618972 Set Vref, RX VrefLevel [Byte0]: 53
2847 10:01:27.622594 [Byte1]: 53
2848 10:01:27.626678
2849 10:01:27.626768 Set Vref, RX VrefLevel [Byte0]: 54
2850 10:01:27.629952 [Byte1]: 54
2851 10:01:27.634780
2852 10:01:27.634860 Set Vref, RX VrefLevel [Byte0]: 55
2853 10:01:27.638046 [Byte1]: 55
2854 10:01:27.642571
2855 10:01:27.642651 Set Vref, RX VrefLevel [Byte0]: 56
2856 10:01:27.646378 [Byte1]: 56
2857 10:01:27.651106
2858 10:01:27.651304 Set Vref, RX VrefLevel [Byte0]: 57
2859 10:01:27.654420 [Byte1]: 57
2860 10:01:27.658874
2861 10:01:27.659032 Set Vref, RX VrefLevel [Byte0]: 58
2862 10:01:27.662246 [Byte1]: 58
2863 10:01:27.666430
2864 10:01:27.666570 Set Vref, RX VrefLevel [Byte0]: 59
2865 10:01:27.670417 [Byte1]: 59
2866 10:01:27.674362
2867 10:01:27.674449 Set Vref, RX VrefLevel [Byte0]: 60
2868 10:01:27.677858 [Byte1]: 60
2869 10:01:27.682785
2870 10:01:27.682944 Set Vref, RX VrefLevel [Byte0]: 61
2871 10:01:27.685509 [Byte1]: 61
2872 10:01:27.690340
2873 10:01:27.690754 Set Vref, RX VrefLevel [Byte0]: 62
2874 10:01:27.694110 [Byte1]: 62
2875 10:01:27.698755
2876 10:01:27.699324 Set Vref, RX VrefLevel [Byte0]: 63
2877 10:01:27.702319 [Byte1]: 63
2878 10:01:27.706502
2879 10:01:27.706915 Set Vref, RX VrefLevel [Byte0]: 64
2880 10:01:27.710195 [Byte1]: 64
2881 10:01:27.714620
2882 10:01:27.715037 Set Vref, RX VrefLevel [Byte0]: 65
2883 10:01:27.717471 [Byte1]: 65
2884 10:01:27.722660
2885 10:01:27.723182 Set Vref, RX VrefLevel [Byte0]: 66
2886 10:01:27.725524 [Byte1]: 66
2887 10:01:27.730878
2888 10:01:27.731400 Set Vref, RX VrefLevel [Byte0]: 67
2889 10:01:27.734001 [Byte1]: 67
2890 10:01:27.738140
2891 10:01:27.741361 Set Vref, RX VrefLevel [Byte0]: 68
2892 10:01:27.744500 [Byte1]: 68
2893 10:01:27.745060
2894 10:01:27.747741 Set Vref, RX VrefLevel [Byte0]: 69
2895 10:01:27.751438 [Byte1]: 69
2896 10:01:27.752001
2897 10:01:27.754498 Set Vref, RX VrefLevel [Byte0]: 70
2898 10:01:27.758295 [Byte1]: 70
2899 10:01:27.762428
2900 10:01:27.762990 Set Vref, RX VrefLevel [Byte0]: 71
2901 10:01:27.765317 [Byte1]: 71
2902 10:01:27.770375
2903 10:01:27.770833 Set Vref, RX VrefLevel [Byte0]: 72
2904 10:01:27.772998 [Byte1]: 72
2905 10:01:27.777900
2906 10:01:27.778504 Set Vref, RX VrefLevel [Byte0]: 73
2907 10:01:27.781929 [Byte1]: 73
2908 10:01:27.785930
2909 10:01:27.786392 Set Vref, RX VrefLevel [Byte0]: 74
2910 10:01:27.788616 [Byte1]: 74
2911 10:01:27.793402
2912 10:01:27.793856 Set Vref, RX VrefLevel [Byte0]: 75
2913 10:01:27.796984 [Byte1]: 75
2914 10:01:27.801872
2915 10:01:27.802336 Set Vref, RX VrefLevel [Byte0]: 76
2916 10:01:27.804875 [Byte1]: 76
2917 10:01:27.809898
2918 10:01:27.810311 Set Vref, RX VrefLevel [Byte0]: 77
2919 10:01:27.812768 [Byte1]: 77
2920 10:01:27.817648
2921 10:01:27.818061 Final RX Vref Byte 0 = 60 to rank0
2922 10:01:27.820599 Final RX Vref Byte 1 = 48 to rank0
2923 10:01:27.824217 Final RX Vref Byte 0 = 60 to rank1
2924 10:01:27.827418 Final RX Vref Byte 1 = 48 to rank1==
2925 10:01:27.831163 Dram Type= 6, Freq= 0, CH_0, rank 0
2926 10:01:27.837730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2927 10:01:27.838192 ==
2928 10:01:27.838557 DQS Delay:
2929 10:01:27.838898 DQS0 = 0, DQS1 = 0
2930 10:01:27.840477 DQM Delay:
2931 10:01:27.840954 DQM0 = 119, DQM1 = 105
2932 10:01:27.844131 DQ Delay:
2933 10:01:27.847518 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2934 10:01:27.850425 DQ4 =120, DQ5 =114, DQ6 =124, DQ7 =126
2935 10:01:27.853886 DQ8 =96, DQ9 =92, DQ10 =108, DQ11 =100
2936 10:01:27.857483 DQ12 =110, DQ13 =108, DQ14 =118, DQ15 =114
2937 10:01:27.857902
2938 10:01:27.858233
2939 10:01:27.863773 [DQSOSCAuto] RK0, (LSB)MR18= 0x12fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 403 ps
2940 10:01:27.866879 CH0 RK0: MR19=403, MR18=12FE
2941 10:01:27.874228 CH0_RK0: MR19=0x403, MR18=0x12FE, DQSOSC=403, MR23=63, INC=40, DEC=26
2942 10:01:27.874628
2943 10:01:27.876741 ----->DramcWriteLeveling(PI) begin...
2944 10:01:27.877144 ==
2945 10:01:27.880206 Dram Type= 6, Freq= 0, CH_0, rank 1
2946 10:01:27.887143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2947 10:01:27.887564 ==
2948 10:01:27.890120 Write leveling (Byte 0): 32 => 32
2949 10:01:27.890547 Write leveling (Byte 1): 30 => 30
2950 10:01:27.893275 DramcWriteLeveling(PI) end<-----
2951 10:01:27.893816
2952 10:01:27.897121 ==
2953 10:01:27.897587 Dram Type= 6, Freq= 0, CH_0, rank 1
2954 10:01:27.903337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2955 10:01:27.903754 ==
2956 10:01:27.906852 [Gating] SW mode calibration
2957 10:01:27.913308 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2958 10:01:27.916627 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2959 10:01:27.923567 0 15 0 | B1->B0 | 2323 3131 | 1 0 | (1 1) (0 0)
2960 10:01:27.926635 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
2961 10:01:27.929681 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2962 10:01:27.936352 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2963 10:01:27.939797 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2964 10:01:27.943120 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2965 10:01:27.949833 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2966 10:01:27.953461 0 15 28 | B1->B0 | 3434 3232 | 1 0 | (1 1) (1 0)
2967 10:01:27.956249 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
2968 10:01:27.962890 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2969 10:01:27.966493 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2970 10:01:27.970007 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2971 10:01:27.976486 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2972 10:01:27.979726 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2973 10:01:27.982995 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2974 10:01:27.986397 1 0 28 | B1->B0 | 2525 3232 | 1 1 | (0 0) (0 0)
2975 10:01:27.993009 1 1 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
2976 10:01:27.996408 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2977 10:01:27.999942 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2978 10:01:28.006481 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2979 10:01:28.009212 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2980 10:01:28.013025 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2981 10:01:28.019381 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2982 10:01:28.022876 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2983 10:01:28.026047 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2984 10:01:28.032725 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 10:01:28.036116 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 10:01:28.039819 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 10:01:28.046964 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 10:01:28.049911 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2989 10:01:28.054990 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2990 10:01:28.059604 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2991 10:01:28.062867 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2992 10:01:28.066542 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2993 10:01:28.072833 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2994 10:01:28.075839 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2995 10:01:28.079831 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2996 10:01:28.085966 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2997 10:01:28.089514 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2998 10:01:28.092593 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2999 10:01:28.099185 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3000 10:01:28.099603 Total UI for P1: 0, mck2ui 16
3001 10:01:28.106755 best dqsien dly found for B0: ( 1, 3, 26)
3002 10:01:28.109329 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3003 10:01:28.112553 Total UI for P1: 0, mck2ui 16
3004 10:01:28.116041 best dqsien dly found for B1: ( 1, 3, 30)
3005 10:01:28.119096 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3006 10:01:28.122562 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3007 10:01:28.123074
3008 10:01:28.125959 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3009 10:01:28.129104 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3010 10:01:28.132775 [Gating] SW calibration Done
3011 10:01:28.133262 ==
3012 10:01:28.135446 Dram Type= 6, Freq= 0, CH_0, rank 1
3013 10:01:28.139171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3014 10:01:28.139596 ==
3015 10:01:28.142580 RX Vref Scan: 0
3016 10:01:28.142997
3017 10:01:28.145521 RX Vref 0 -> 0, step: 1
3018 10:01:28.145938
3019 10:01:28.146266 RX Delay -40 -> 252, step: 8
3020 10:01:28.152992 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
3021 10:01:28.155827 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3022 10:01:28.159277 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3023 10:01:28.162144 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3024 10:01:28.166102 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3025 10:01:28.172020 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3026 10:01:28.175727 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3027 10:01:28.178942 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3028 10:01:28.182366 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3029 10:01:28.185394 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3030 10:01:28.192222 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3031 10:01:28.195465 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3032 10:01:28.198726 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3033 10:01:28.201987 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3034 10:01:28.208772 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3035 10:01:28.212278 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3036 10:01:28.212776 ==
3037 10:01:28.215647 Dram Type= 6, Freq= 0, CH_0, rank 1
3038 10:01:28.218559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3039 10:01:28.218986 ==
3040 10:01:28.219358 DQS Delay:
3041 10:01:28.222143 DQS0 = 0, DQS1 = 0
3042 10:01:28.222539 DQM Delay:
3043 10:01:28.225360 DQM0 = 116, DQM1 = 108
3044 10:01:28.225821 DQ Delay:
3045 10:01:28.228610 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
3046 10:01:28.231942 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
3047 10:01:28.235294 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3048 10:01:28.238787 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =111
3049 10:01:28.241854
3050 10:01:28.242243
3051 10:01:28.242587 ==
3052 10:01:28.245284 Dram Type= 6, Freq= 0, CH_0, rank 1
3053 10:01:28.248353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3054 10:01:28.248750 ==
3055 10:01:28.249129
3056 10:01:28.249492
3057 10:01:28.252235 TX Vref Scan disable
3058 10:01:28.252577 == TX Byte 0 ==
3059 10:01:28.258462 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3060 10:01:28.261820 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3061 10:01:28.262292 == TX Byte 1 ==
3062 10:01:28.268535 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3063 10:01:28.272152 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3064 10:01:28.272622 ==
3065 10:01:28.275264 Dram Type= 6, Freq= 0, CH_0, rank 1
3066 10:01:28.278360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3067 10:01:28.279083 ==
3068 10:01:28.291064 TX Vref=22, minBit 1, minWin=25, winSum=418
3069 10:01:28.294042 TX Vref=24, minBit 1, minWin=26, winSum=422
3070 10:01:28.298137 TX Vref=26, minBit 10, minWin=26, winSum=427
3071 10:01:28.300856 TX Vref=28, minBit 8, minWin=26, winSum=426
3072 10:01:28.304084 TX Vref=30, minBit 9, minWin=26, winSum=428
3073 10:01:28.310720 TX Vref=32, minBit 12, minWin=25, winSum=425
3074 10:01:28.313962 [TxChooseVref] Worse bit 9, Min win 26, Win sum 428, Final Vref 30
3075 10:01:28.314437
3076 10:01:28.317574 Final TX Range 1 Vref 30
3077 10:01:28.317995
3078 10:01:28.318326 ==
3079 10:01:28.320946 Dram Type= 6, Freq= 0, CH_0, rank 1
3080 10:01:28.324312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3081 10:01:28.324729 ==
3082 10:01:28.327327
3083 10:01:28.327772
3084 10:01:28.328104 TX Vref Scan disable
3085 10:01:28.330529 == TX Byte 0 ==
3086 10:01:28.333827 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3087 10:01:28.341034 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3088 10:01:28.341757 == TX Byte 1 ==
3089 10:01:28.343733 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3090 10:01:28.350443 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3091 10:01:28.350916
3092 10:01:28.351285 [DATLAT]
3093 10:01:28.351731 Freq=1200, CH0 RK1
3094 10:01:28.352091
3095 10:01:28.354354 DATLAT Default: 0xd
3096 10:01:28.354813 0, 0xFFFF, sum = 0
3097 10:01:28.357343 1, 0xFFFF, sum = 0
3098 10:01:28.360401 2, 0xFFFF, sum = 0
3099 10:01:28.360832 3, 0xFFFF, sum = 0
3100 10:01:28.364261 4, 0xFFFF, sum = 0
3101 10:01:28.364731 5, 0xFFFF, sum = 0
3102 10:01:28.367521 6, 0xFFFF, sum = 0
3103 10:01:28.367973 7, 0xFFFF, sum = 0
3104 10:01:28.371157 8, 0xFFFF, sum = 0
3105 10:01:28.371619 9, 0xFFFF, sum = 0
3106 10:01:28.373782 10, 0xFFFF, sum = 0
3107 10:01:28.374324 11, 0xFFFF, sum = 0
3108 10:01:28.377607 12, 0x0, sum = 1
3109 10:01:28.378193 13, 0x0, sum = 2
3110 10:01:28.380664 14, 0x0, sum = 3
3111 10:01:28.381102 15, 0x0, sum = 4
3112 10:01:28.384027 best_step = 13
3113 10:01:28.384468
3114 10:01:28.384798 ==
3115 10:01:28.387089 Dram Type= 6, Freq= 0, CH_0, rank 1
3116 10:01:28.390529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3117 10:01:28.391017 ==
3118 10:01:28.391380 RX Vref Scan: 0
3119 10:01:28.391743
3120 10:01:28.393762 RX Vref 0 -> 0, step: 1
3121 10:01:28.394476
3122 10:01:28.397261 RX Delay -21 -> 252, step: 4
3123 10:01:28.403768 iDelay=199, Bit 0, Center 112 (47 ~ 178) 132
3124 10:01:28.407188 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3125 10:01:28.410476 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3126 10:01:28.413779 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3127 10:01:28.417355 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3128 10:01:28.420390 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3129 10:01:28.427122 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3130 10:01:28.430235 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3131 10:01:28.433552 iDelay=199, Bit 8, Center 96 (27 ~ 166) 140
3132 10:01:28.436867 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3133 10:01:28.439901 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3134 10:01:28.446629 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3135 10:01:28.449946 iDelay=199, Bit 12, Center 114 (47 ~ 182) 136
3136 10:01:28.453866 iDelay=199, Bit 13, Center 114 (47 ~ 182) 136
3137 10:01:28.456478 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3138 10:01:28.463280 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3139 10:01:28.463758 ==
3140 10:01:28.466756 Dram Type= 6, Freq= 0, CH_0, rank 1
3141 10:01:28.470010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3142 10:01:28.470524 ==
3143 10:01:28.470861 DQS Delay:
3144 10:01:28.474004 DQS0 = 0, DQS1 = 0
3145 10:01:28.474418 DQM Delay:
3146 10:01:28.476742 DQM0 = 116, DQM1 = 107
3147 10:01:28.477153 DQ Delay:
3148 10:01:28.479731 DQ0 =112, DQ1 =118, DQ2 =110, DQ3 =114
3149 10:01:28.483122 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3150 10:01:28.486453 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3151 10:01:28.490356 DQ12 =114, DQ13 =114, DQ14 =118, DQ15 =116
3152 10:01:28.490771
3153 10:01:28.491096
3154 10:01:28.499899 [DQSOSCAuto] RK1, (LSB)MR18= 0xbe6, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 405 ps
3155 10:01:28.503071 CH0 RK1: MR19=403, MR18=BE6
3156 10:01:28.506385 CH0_RK1: MR19=0x403, MR18=0xBE6, DQSOSC=405, MR23=63, INC=39, DEC=26
3157 10:01:28.509510 [RxdqsGatingPostProcess] freq 1200
3158 10:01:28.516754 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3159 10:01:28.520169 best DQS0 dly(2T, 0.5T) = (0, 11)
3160 10:01:28.523216 best DQS1 dly(2T, 0.5T) = (0, 11)
3161 10:01:28.526834 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3162 10:01:28.529733 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3163 10:01:28.533042 best DQS0 dly(2T, 0.5T) = (0, 11)
3164 10:01:28.536131 best DQS1 dly(2T, 0.5T) = (0, 11)
3165 10:01:28.539763 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3166 10:01:28.543023 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3167 10:01:28.543746 Pre-setting of DQS Precalculation
3168 10:01:28.549981 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3169 10:01:28.550537 ==
3170 10:01:28.552772 Dram Type= 6, Freq= 0, CH_1, rank 0
3171 10:01:28.555997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3172 10:01:28.556509 ==
3173 10:01:28.562678 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3174 10:01:28.569594 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3175 10:01:28.577330 [CA 0] Center 37 (7~67) winsize 61
3176 10:01:28.580276 [CA 1] Center 37 (7~68) winsize 62
3177 10:01:28.583696 [CA 2] Center 34 (4~64) winsize 61
3178 10:01:28.587210 [CA 3] Center 33 (3~64) winsize 62
3179 10:01:28.590275 [CA 4] Center 34 (4~64) winsize 61
3180 10:01:28.593754 [CA 5] Center 33 (3~64) winsize 62
3181 10:01:28.594173
3182 10:01:28.597318 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3183 10:01:28.597803
3184 10:01:28.600247 [CATrainingPosCal] consider 1 rank data
3185 10:01:28.603524 u2DelayCellTimex100 = 270/100 ps
3186 10:01:28.606719 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3187 10:01:28.614183 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3188 10:01:28.616777 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3189 10:01:28.620752 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3190 10:01:28.623985 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3191 10:01:28.626673 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3192 10:01:28.627094
3193 10:01:28.629871 CA PerBit enable=1, Macro0, CA PI delay=33
3194 10:01:28.630288
3195 10:01:28.633347 [CBTSetCACLKResult] CA Dly = 33
3196 10:01:28.637041 CS Dly: 6 (0~37)
3197 10:01:28.637506 ==
3198 10:01:28.640135 Dram Type= 6, Freq= 0, CH_1, rank 1
3199 10:01:28.643155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3200 10:01:28.643576 ==
3201 10:01:28.650032 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3202 10:01:28.652735 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3203 10:01:28.662282 [CA 0] Center 37 (7~68) winsize 62
3204 10:01:28.665427 [CA 1] Center 38 (8~68) winsize 61
3205 10:01:28.668782 [CA 2] Center 34 (4~65) winsize 62
3206 10:01:28.671803 [CA 3] Center 33 (3~64) winsize 62
3207 10:01:28.675432 [CA 4] Center 34 (4~65) winsize 62
3208 10:01:28.678889 [CA 5] Center 33 (3~64) winsize 62
3209 10:01:28.678970
3210 10:01:28.682095 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3211 10:01:28.682176
3212 10:01:28.685372 [CATrainingPosCal] consider 2 rank data
3213 10:01:28.689105 u2DelayCellTimex100 = 270/100 ps
3214 10:01:28.692628 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3215 10:01:28.699143 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3216 10:01:28.702018 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3217 10:01:28.705893 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3218 10:01:28.708657 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3219 10:01:28.711963 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3220 10:01:28.712044
3221 10:01:28.715216 CA PerBit enable=1, Macro0, CA PI delay=33
3222 10:01:28.715297
3223 10:01:28.718569 [CBTSetCACLKResult] CA Dly = 33
3224 10:01:28.718650 CS Dly: 7 (0~40)
3225 10:01:28.722391
3226 10:01:28.725267 ----->DramcWriteLeveling(PI) begin...
3227 10:01:28.725349 ==
3228 10:01:28.728184 Dram Type= 6, Freq= 0, CH_1, rank 0
3229 10:01:28.732091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3230 10:01:28.732173 ==
3231 10:01:28.735049 Write leveling (Byte 0): 26 => 26
3232 10:01:28.738220 Write leveling (Byte 1): 27 => 27
3233 10:01:28.742286 DramcWriteLeveling(PI) end<-----
3234 10:01:28.742366
3235 10:01:28.742430 ==
3236 10:01:28.744806 Dram Type= 6, Freq= 0, CH_1, rank 0
3237 10:01:28.748827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3238 10:01:28.748908 ==
3239 10:01:28.751516 [Gating] SW mode calibration
3240 10:01:28.758064 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3241 10:01:28.765087 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3242 10:01:28.768556 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (1 1) (1 1)
3243 10:01:28.771306 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3244 10:01:28.777913 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3245 10:01:28.781231 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3246 10:01:28.784734 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3247 10:01:28.791201 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3248 10:01:28.794827 0 15 24 | B1->B0 | 3434 2828 | 0 0 | (0 0) (0 0)
3249 10:01:28.798171 0 15 28 | B1->B0 | 2323 2323 | 1 0 | (1 0) (1 0)
3250 10:01:28.804273 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3251 10:01:28.807818 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3252 10:01:28.811177 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3253 10:01:28.817917 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3254 10:01:28.820953 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3255 10:01:28.824080 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3256 10:01:28.830555 1 0 24 | B1->B0 | 2b2b 4040 | 0 0 | (0 0) (0 0)
3257 10:01:28.834396 1 0 28 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
3258 10:01:28.837135 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3259 10:01:28.844623 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3260 10:01:28.847156 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3261 10:01:28.851524 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3262 10:01:28.857044 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3263 10:01:28.860714 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3264 10:01:28.863878 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3265 10:01:28.870356 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3266 10:01:28.873863 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3267 10:01:28.876977 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3268 10:01:28.883886 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3269 10:01:28.887473 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3270 10:01:28.890617 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3271 10:01:28.897202 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3272 10:01:28.900545 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3273 10:01:28.903436 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3274 10:01:28.907108 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3275 10:01:28.913946 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3276 10:01:28.917502 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3277 10:01:28.920732 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3278 10:01:28.927288 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3279 10:01:28.930432 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3280 10:01:28.934130 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3281 10:01:28.940272 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3282 10:01:28.943498 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3283 10:01:28.947347 Total UI for P1: 0, mck2ui 16
3284 10:01:28.950754 best dqsien dly found for B0: ( 1, 3, 26)
3285 10:01:28.953894 Total UI for P1: 0, mck2ui 16
3286 10:01:28.956929 best dqsien dly found for B1: ( 1, 3, 28)
3287 10:01:28.960391 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3288 10:01:28.963983 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3289 10:01:28.964184
3290 10:01:28.967429 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3291 10:01:28.971105 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3292 10:01:28.973483 [Gating] SW calibration Done
3293 10:01:28.973679 ==
3294 10:01:28.976958 Dram Type= 6, Freq= 0, CH_1, rank 0
3295 10:01:28.983894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3296 10:01:28.984180 ==
3297 10:01:28.984355 RX Vref Scan: 0
3298 10:01:28.984561
3299 10:01:28.986823 RX Vref 0 -> 0, step: 1
3300 10:01:28.987054
3301 10:01:28.990255 RX Delay -40 -> 252, step: 8
3302 10:01:28.993718 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3303 10:01:28.996836 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3304 10:01:29.000739 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3305 10:01:29.003983 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3306 10:01:29.010108 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3307 10:01:29.013573 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3308 10:01:29.017263 iDelay=208, Bit 6, Center 127 (56 ~ 199) 144
3309 10:01:29.020306 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3310 10:01:29.023650 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3311 10:01:29.030446 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3312 10:01:29.034297 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3313 10:01:29.037075 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3314 10:01:29.040471 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3315 10:01:29.043427 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3316 10:01:29.050092 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3317 10:01:29.053447 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3318 10:01:29.053936 ==
3319 10:01:29.057268 Dram Type= 6, Freq= 0, CH_1, rank 0
3320 10:01:29.060152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3321 10:01:29.060612 ==
3322 10:01:29.063838 DQS Delay:
3323 10:01:29.064291 DQS0 = 0, DQS1 = 0
3324 10:01:29.064626 DQM Delay:
3325 10:01:29.067023 DQM0 = 118, DQM1 = 108
3326 10:01:29.067437 DQ Delay:
3327 10:01:29.070209 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3328 10:01:29.073600 DQ4 =111, DQ5 =131, DQ6 =127, DQ7 =115
3329 10:01:29.077009 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3330 10:01:29.083157 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =119
3331 10:01:29.083569
3332 10:01:29.083899
3333 10:01:29.084201 ==
3334 10:01:29.086588 Dram Type= 6, Freq= 0, CH_1, rank 0
3335 10:01:29.090152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3336 10:01:29.090569 ==
3337 10:01:29.090902
3338 10:01:29.091207
3339 10:01:29.093327 TX Vref Scan disable
3340 10:01:29.093788 == TX Byte 0 ==
3341 10:01:29.099828 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3342 10:01:29.102784 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3343 10:01:29.103200 == TX Byte 1 ==
3344 10:01:29.109505 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3345 10:01:29.113050 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3346 10:01:29.113515 ==
3347 10:01:29.116483 Dram Type= 6, Freq= 0, CH_1, rank 0
3348 10:01:29.120009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3349 10:01:29.120529 ==
3350 10:01:29.132423 TX Vref=22, minBit 10, minWin=25, winSum=418
3351 10:01:29.135577 TX Vref=24, minBit 9, minWin=25, winSum=419
3352 10:01:29.139087 TX Vref=26, minBit 9, minWin=25, winSum=425
3353 10:01:29.142343 TX Vref=28, minBit 9, minWin=25, winSum=431
3354 10:01:29.145582 TX Vref=30, minBit 11, minWin=25, winSum=430
3355 10:01:29.153246 TX Vref=32, minBit 9, minWin=25, winSum=424
3356 10:01:29.156176 [TxChooseVref] Worse bit 9, Min win 25, Win sum 431, Final Vref 28
3357 10:01:29.156592
3358 10:01:29.159265 Final TX Range 1 Vref 28
3359 10:01:29.159687
3360 10:01:29.160020 ==
3361 10:01:29.162250 Dram Type= 6, Freq= 0, CH_1, rank 0
3362 10:01:29.165268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3363 10:01:29.168705 ==
3364 10:01:29.169113
3365 10:01:29.169588
3366 10:01:29.169915 TX Vref Scan disable
3367 10:01:29.172429 == TX Byte 0 ==
3368 10:01:29.175981 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3369 10:01:29.182328 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3370 10:01:29.182742 == TX Byte 1 ==
3371 10:01:29.185570 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3372 10:01:29.192450 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3373 10:01:29.192859
3374 10:01:29.193231 [DATLAT]
3375 10:01:29.193643 Freq=1200, CH1 RK0
3376 10:01:29.193950
3377 10:01:29.195460 DATLAT Default: 0xd
3378 10:01:29.195831 0, 0xFFFF, sum = 0
3379 10:01:29.198526 1, 0xFFFF, sum = 0
3380 10:01:29.202198 2, 0xFFFF, sum = 0
3381 10:01:29.202718 3, 0xFFFF, sum = 0
3382 10:01:29.205470 4, 0xFFFF, sum = 0
3383 10:01:29.205890 5, 0xFFFF, sum = 0
3384 10:01:29.208616 6, 0xFFFF, sum = 0
3385 10:01:29.209034 7, 0xFFFF, sum = 0
3386 10:01:29.211766 8, 0xFFFF, sum = 0
3387 10:01:29.212185 9, 0xFFFF, sum = 0
3388 10:01:29.215467 10, 0xFFFF, sum = 0
3389 10:01:29.215883 11, 0xFFFF, sum = 0
3390 10:01:29.218678 12, 0x0, sum = 1
3391 10:01:29.219096 13, 0x0, sum = 2
3392 10:01:29.222011 14, 0x0, sum = 3
3393 10:01:29.222444 15, 0x0, sum = 4
3394 10:01:29.225217 best_step = 13
3395 10:01:29.225764
3396 10:01:29.226095 ==
3397 10:01:29.228737 Dram Type= 6, Freq= 0, CH_1, rank 0
3398 10:01:29.232787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3399 10:01:29.233303 ==
3400 10:01:29.233711 RX Vref Scan: 1
3401 10:01:29.235026
3402 10:01:29.235435 Set Vref Range= 32 -> 127
3403 10:01:29.235762
3404 10:01:29.239048 RX Vref 32 -> 127, step: 1
3405 10:01:29.239462
3406 10:01:29.241924 RX Delay -21 -> 252, step: 4
3407 10:01:29.242336
3408 10:01:29.245151 Set Vref, RX VrefLevel [Byte0]: 32
3409 10:01:29.248948 [Byte1]: 32
3410 10:01:29.249533
3411 10:01:29.251736 Set Vref, RX VrefLevel [Byte0]: 33
3412 10:01:29.255614 [Byte1]: 33
3413 10:01:29.259053
3414 10:01:29.259596 Set Vref, RX VrefLevel [Byte0]: 34
3415 10:01:29.262219 [Byte1]: 34
3416 10:01:29.267203
3417 10:01:29.267717 Set Vref, RX VrefLevel [Byte0]: 35
3418 10:01:29.269869 [Byte1]: 35
3419 10:01:29.274781
3420 10:01:29.275293 Set Vref, RX VrefLevel [Byte0]: 36
3421 10:01:29.278110 [Byte1]: 36
3422 10:01:29.282805
3423 10:01:29.283316 Set Vref, RX VrefLevel [Byte0]: 37
3424 10:01:29.286065 [Byte1]: 37
3425 10:01:29.290124
3426 10:01:29.290535 Set Vref, RX VrefLevel [Byte0]: 38
3427 10:01:29.293661 [Byte1]: 38
3428 10:01:29.297977
3429 10:01:29.298597 Set Vref, RX VrefLevel [Byte0]: 39
3430 10:01:29.301783 [Byte1]: 39
3431 10:01:29.306814
3432 10:01:29.307525 Set Vref, RX VrefLevel [Byte0]: 40
3433 10:01:29.309524 [Byte1]: 40
3434 10:01:29.314033
3435 10:01:29.314671 Set Vref, RX VrefLevel [Byte0]: 41
3436 10:01:29.317184 [Byte1]: 41
3437 10:01:29.321880
3438 10:01:29.322501 Set Vref, RX VrefLevel [Byte0]: 42
3439 10:01:29.325358 [Byte1]: 42
3440 10:01:29.330123
3441 10:01:29.330793 Set Vref, RX VrefLevel [Byte0]: 43
3442 10:01:29.333638 [Byte1]: 43
3443 10:01:29.337685
3444 10:01:29.338198 Set Vref, RX VrefLevel [Byte0]: 44
3445 10:01:29.340884 [Byte1]: 44
3446 10:01:29.345524
3447 10:01:29.345985 Set Vref, RX VrefLevel [Byte0]: 45
3448 10:01:29.348995 [Byte1]: 45
3449 10:01:29.353708
3450 10:01:29.354124 Set Vref, RX VrefLevel [Byte0]: 46
3451 10:01:29.356912 [Byte1]: 46
3452 10:01:29.361440
3453 10:01:29.361859 Set Vref, RX VrefLevel [Byte0]: 47
3454 10:01:29.365243 [Byte1]: 47
3455 10:01:29.369765
3456 10:01:29.370178 Set Vref, RX VrefLevel [Byte0]: 48
3457 10:01:29.372556 [Byte1]: 48
3458 10:01:29.377842
3459 10:01:29.378259 Set Vref, RX VrefLevel [Byte0]: 49
3460 10:01:29.380549 [Byte1]: 49
3461 10:01:29.385333
3462 10:01:29.385797 Set Vref, RX VrefLevel [Byte0]: 50
3463 10:01:29.388652 [Byte1]: 50
3464 10:01:29.393521
3465 10:01:29.393940 Set Vref, RX VrefLevel [Byte0]: 51
3466 10:01:29.396686 [Byte1]: 51
3467 10:01:29.401091
3468 10:01:29.401545 Set Vref, RX VrefLevel [Byte0]: 52
3469 10:01:29.404376 [Byte1]: 52
3470 10:01:29.408943
3471 10:01:29.409354 Set Vref, RX VrefLevel [Byte0]: 53
3472 10:01:29.412262 [Byte1]: 53
3473 10:01:29.416861
3474 10:01:29.417274 Set Vref, RX VrefLevel [Byte0]: 54
3475 10:01:29.420226 [Byte1]: 54
3476 10:01:29.425712
3477 10:01:29.426227 Set Vref, RX VrefLevel [Byte0]: 55
3478 10:01:29.428682 [Byte1]: 55
3479 10:01:29.433548
3480 10:01:29.434065 Set Vref, RX VrefLevel [Byte0]: 56
3481 10:01:29.436761 [Byte1]: 56
3482 10:01:29.440670
3483 10:01:29.441083 Set Vref, RX VrefLevel [Byte0]: 57
3484 10:01:29.444081 [Byte1]: 57
3485 10:01:29.448844
3486 10:01:29.449376 Set Vref, RX VrefLevel [Byte0]: 58
3487 10:01:29.452072 [Byte1]: 58
3488 10:01:29.456536
3489 10:01:29.456954 Set Vref, RX VrefLevel [Byte0]: 59
3490 10:01:29.459758 [Byte1]: 59
3491 10:01:29.465182
3492 10:01:29.465676 Set Vref, RX VrefLevel [Byte0]: 60
3493 10:01:29.468273 [Byte1]: 60
3494 10:01:29.473290
3495 10:01:29.473873 Set Vref, RX VrefLevel [Byte0]: 61
3496 10:01:29.475932 [Byte1]: 61
3497 10:01:29.480375
3498 10:01:29.480794 Set Vref, RX VrefLevel [Byte0]: 62
3499 10:01:29.483656 [Byte1]: 62
3500 10:01:29.489507
3501 10:01:29.489923 Set Vref, RX VrefLevel [Byte0]: 63
3502 10:01:29.491735 [Byte1]: 63
3503 10:01:29.496105
3504 10:01:29.496537 Set Vref, RX VrefLevel [Byte0]: 64
3505 10:01:29.499583 [Byte1]: 64
3506 10:01:29.504766
3507 10:01:29.505363 Set Vref, RX VrefLevel [Byte0]: 65
3508 10:01:29.508487 [Byte1]: 65
3509 10:01:29.512103
3510 10:01:29.512533 Set Vref, RX VrefLevel [Byte0]: 66
3511 10:01:29.515988 [Byte1]: 66
3512 10:01:29.520329
3513 10:01:29.520747 Set Vref, RX VrefLevel [Byte0]: 67
3514 10:01:29.524050 [Byte1]: 67
3515 10:01:29.528315
3516 10:01:29.528738 Set Vref, RX VrefLevel [Byte0]: 68
3517 10:01:29.531149 [Byte1]: 68
3518 10:01:29.535963
3519 10:01:29.536380 Set Vref, RX VrefLevel [Byte0]: 69
3520 10:01:29.539051 [Byte1]: 69
3521 10:01:29.544046
3522 10:01:29.544466 Set Vref, RX VrefLevel [Byte0]: 70
3523 10:01:29.547244 [Byte1]: 70
3524 10:01:29.552122
3525 10:01:29.552539 Final RX Vref Byte 0 = 53 to rank0
3526 10:01:29.554937 Final RX Vref Byte 1 = 51 to rank0
3527 10:01:29.559714 Final RX Vref Byte 0 = 53 to rank1
3528 10:01:29.561641 Final RX Vref Byte 1 = 51 to rank1==
3529 10:01:29.565280 Dram Type= 6, Freq= 0, CH_1, rank 0
3530 10:01:29.572106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3531 10:01:29.572572 ==
3532 10:01:29.572914 DQS Delay:
3533 10:01:29.573227 DQS0 = 0, DQS1 = 0
3534 10:01:29.575195 DQM Delay:
3535 10:01:29.575614 DQM0 = 116, DQM1 = 110
3536 10:01:29.578246 DQ Delay:
3537 10:01:29.581787 DQ0 =120, DQ1 =110, DQ2 =110, DQ3 =114
3538 10:01:29.585904 DQ4 =114, DQ5 =128, DQ6 =124, DQ7 =112
3539 10:01:29.587998 DQ8 =96, DQ9 =102, DQ10 =112, DQ11 =100
3540 10:01:29.591385 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =118
3541 10:01:29.591803
3542 10:01:29.592134
3543 10:01:29.601193 [DQSOSCAuto] RK0, (LSB)MR18= 0x7fa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 407 ps
3544 10:01:29.601669 CH1 RK0: MR19=403, MR18=7FA
3545 10:01:29.607994 CH1_RK0: MR19=0x403, MR18=0x7FA, DQSOSC=407, MR23=63, INC=39, DEC=26
3546 10:01:29.608413
3547 10:01:29.611502 ----->DramcWriteLeveling(PI) begin...
3548 10:01:29.612068 ==
3549 10:01:29.614540 Dram Type= 6, Freq= 0, CH_1, rank 1
3550 10:01:29.618208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3551 10:01:29.621028 ==
3552 10:01:29.621470 Write leveling (Byte 0): 24 => 24
3553 10:01:29.624652 Write leveling (Byte 1): 27 => 27
3554 10:01:29.627553 DramcWriteLeveling(PI) end<-----
3555 10:01:29.627969
3556 10:01:29.628300 ==
3557 10:01:29.630942 Dram Type= 6, Freq= 0, CH_1, rank 1
3558 10:01:29.637684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3559 10:01:29.638105 ==
3560 10:01:29.640915 [Gating] SW mode calibration
3561 10:01:29.647476 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3562 10:01:29.651849 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3563 10:01:29.658076 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3564 10:01:29.661023 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3565 10:01:29.664228 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3566 10:01:29.670731 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3567 10:01:29.673755 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3568 10:01:29.677220 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3569 10:01:29.683895 0 15 24 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 0)
3570 10:01:29.686928 0 15 28 | B1->B0 | 2525 2828 | 0 0 | (0 0) (1 0)
3571 10:01:29.690557 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3572 10:01:29.696825 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3573 10:01:29.699888 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3574 10:01:29.704007 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3575 10:01:29.710096 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3576 10:01:29.713399 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3577 10:01:29.717033 1 0 24 | B1->B0 | 3535 2424 | 1 0 | (0 0) (0 0)
3578 10:01:29.723563 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3579 10:01:29.726694 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3580 10:01:29.730360 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3581 10:01:29.736760 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3582 10:01:29.739506 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3583 10:01:29.743175 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3584 10:01:29.749735 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3585 10:01:29.752892 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3586 10:01:29.756242 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3587 10:01:29.763479 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3588 10:01:29.766393 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3589 10:01:29.769853 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3590 10:01:29.776669 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3591 10:01:29.779692 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3592 10:01:29.783050 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3593 10:01:29.789472 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3594 10:01:29.792668 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3595 10:01:29.795952 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3596 10:01:29.802650 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3597 10:01:29.806167 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3598 10:01:29.809393 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3599 10:01:29.815922 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3600 10:01:29.819622 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3601 10:01:29.822439 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3602 10:01:29.829149 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3603 10:01:29.829604 Total UI for P1: 0, mck2ui 16
3604 10:01:29.832803 best dqsien dly found for B1: ( 1, 3, 24)
3605 10:01:29.840526 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3606 10:01:29.842330 Total UI for P1: 0, mck2ui 16
3607 10:01:29.845782 best dqsien dly found for B0: ( 1, 3, 26)
3608 10:01:29.849700 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3609 10:01:29.852725 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3610 10:01:29.853187
3611 10:01:29.855734 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3612 10:01:29.858870 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3613 10:01:29.862237 [Gating] SW calibration Done
3614 10:01:29.862655 ==
3615 10:01:29.865458 Dram Type= 6, Freq= 0, CH_1, rank 1
3616 10:01:29.868634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3617 10:01:29.869053 ==
3618 10:01:29.872510 RX Vref Scan: 0
3619 10:01:29.873039
3620 10:01:29.875615 RX Vref 0 -> 0, step: 1
3621 10:01:29.876031
3622 10:01:29.876358 RX Delay -40 -> 252, step: 8
3623 10:01:29.882069 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3624 10:01:29.885236 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3625 10:01:29.888699 iDelay=208, Bit 2, Center 107 (40 ~ 175) 136
3626 10:01:29.891895 iDelay=208, Bit 3, Center 111 (40 ~ 183) 144
3627 10:01:29.895287 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3628 10:01:29.901744 iDelay=208, Bit 5, Center 127 (56 ~ 199) 144
3629 10:01:29.904957 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3630 10:01:29.908542 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3631 10:01:29.911749 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3632 10:01:29.915395 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3633 10:01:29.921742 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3634 10:01:29.924982 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3635 10:01:29.928397 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3636 10:01:29.931318 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3637 10:01:29.938148 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3638 10:01:29.941803 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3639 10:01:29.942293 ==
3640 10:01:29.945167 Dram Type= 6, Freq= 0, CH_1, rank 1
3641 10:01:29.948321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3642 10:01:29.948741 ==
3643 10:01:29.951205 DQS Delay:
3644 10:01:29.951624 DQS0 = 0, DQS1 = 0
3645 10:01:29.951958 DQM Delay:
3646 10:01:29.954735 DQM0 = 117, DQM1 = 109
3647 10:01:29.955155 DQ Delay:
3648 10:01:29.957901 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =111
3649 10:01:29.961108 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =115
3650 10:01:29.964575 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =99
3651 10:01:29.971159 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3652 10:01:29.971579
3653 10:01:29.971909
3654 10:01:29.972217 ==
3655 10:01:29.974611 Dram Type= 6, Freq= 0, CH_1, rank 1
3656 10:01:29.977758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3657 10:01:29.978178 ==
3658 10:01:29.978512
3659 10:01:29.978817
3660 10:01:29.980906 TX Vref Scan disable
3661 10:01:29.981341 == TX Byte 0 ==
3662 10:01:29.987812 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3663 10:01:29.991421 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3664 10:01:29.991858 == TX Byte 1 ==
3665 10:01:29.997987 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3666 10:01:30.000767 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3667 10:01:30.001188 ==
3668 10:01:30.005104 Dram Type= 6, Freq= 0, CH_1, rank 1
3669 10:01:30.007424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3670 10:01:30.007846 ==
3671 10:01:30.020555 TX Vref=22, minBit 1, minWin=26, winSum=427
3672 10:01:30.023645 TX Vref=24, minBit 3, minWin=26, winSum=431
3673 10:01:30.026926 TX Vref=26, minBit 9, minWin=26, winSum=433
3674 10:01:30.030610 TX Vref=28, minBit 9, minWin=26, winSum=435
3675 10:01:30.033773 TX Vref=30, minBit 9, minWin=26, winSum=437
3676 10:01:30.039985 TX Vref=32, minBit 9, minWin=25, winSum=432
3677 10:01:30.043134 [TxChooseVref] Worse bit 9, Min win 26, Win sum 437, Final Vref 30
3678 10:01:30.043558
3679 10:01:30.046767 Final TX Range 1 Vref 30
3680 10:01:30.047331
3681 10:01:30.047680 ==
3682 10:01:30.050001 Dram Type= 6, Freq= 0, CH_1, rank 1
3683 10:01:30.053078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3684 10:01:30.056879 ==
3685 10:01:30.057298
3686 10:01:30.057671
3687 10:01:30.057983 TX Vref Scan disable
3688 10:01:30.060481 == TX Byte 0 ==
3689 10:01:30.064107 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3690 10:01:30.070777 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3691 10:01:30.071200 == TX Byte 1 ==
3692 10:01:30.073323 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3693 10:01:30.079708 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3694 10:01:30.080146
3695 10:01:30.080481 [DATLAT]
3696 10:01:30.080791 Freq=1200, CH1 RK1
3697 10:01:30.081092
3698 10:01:30.083256 DATLAT Default: 0xd
3699 10:01:30.085976 0, 0xFFFF, sum = 0
3700 10:01:30.086416 1, 0xFFFF, sum = 0
3701 10:01:30.089937 2, 0xFFFF, sum = 0
3702 10:01:30.090361 3, 0xFFFF, sum = 0
3703 10:01:30.092947 4, 0xFFFF, sum = 0
3704 10:01:30.093370 5, 0xFFFF, sum = 0
3705 10:01:30.096309 6, 0xFFFF, sum = 0
3706 10:01:30.096736 7, 0xFFFF, sum = 0
3707 10:01:30.099602 8, 0xFFFF, sum = 0
3708 10:01:30.100027 9, 0xFFFF, sum = 0
3709 10:01:30.102968 10, 0xFFFF, sum = 0
3710 10:01:30.103398 11, 0xFFFF, sum = 0
3711 10:01:30.106427 12, 0x0, sum = 1
3712 10:01:30.106856 13, 0x0, sum = 2
3713 10:01:30.109550 14, 0x0, sum = 3
3714 10:01:30.109980 15, 0x0, sum = 4
3715 10:01:30.112909 best_step = 13
3716 10:01:30.113330
3717 10:01:30.113710 ==
3718 10:01:30.116070 Dram Type= 6, Freq= 0, CH_1, rank 1
3719 10:01:30.119603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3720 10:01:30.120026 ==
3721 10:01:30.122990 RX Vref Scan: 0
3722 10:01:30.123457
3723 10:01:30.123795 RX Vref 0 -> 0, step: 1
3724 10:01:30.124106
3725 10:01:30.126192 RX Delay -21 -> 252, step: 4
3726 10:01:30.132992 iDelay=199, Bit 0, Center 120 (51 ~ 190) 140
3727 10:01:30.135765 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3728 10:01:30.139015 iDelay=199, Bit 2, Center 108 (43 ~ 174) 132
3729 10:01:30.142500 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3730 10:01:30.146117 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3731 10:01:30.152199 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3732 10:01:30.155736 iDelay=199, Bit 6, Center 128 (59 ~ 198) 140
3733 10:01:30.159142 iDelay=199, Bit 7, Center 114 (47 ~ 182) 136
3734 10:01:30.162347 iDelay=199, Bit 8, Center 96 (31 ~ 162) 132
3735 10:01:30.165555 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3736 10:01:30.172077 iDelay=199, Bit 10, Center 108 (39 ~ 178) 140
3737 10:01:30.175454 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3738 10:01:30.179097 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3739 10:01:30.182254 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3740 10:01:30.189079 iDelay=199, Bit 14, Center 116 (51 ~ 182) 132
3741 10:01:30.191943 iDelay=199, Bit 15, Center 116 (47 ~ 186) 140
3742 10:01:30.192361 ==
3743 10:01:30.195203 Dram Type= 6, Freq= 0, CH_1, rank 1
3744 10:01:30.198812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3745 10:01:30.199234 ==
3746 10:01:30.202414 DQS Delay:
3747 10:01:30.202832 DQS0 = 0, DQS1 = 0
3748 10:01:30.203162 DQM Delay:
3749 10:01:30.204988 DQM0 = 116, DQM1 = 109
3750 10:01:30.205405 DQ Delay:
3751 10:01:30.208444 DQ0 =120, DQ1 =110, DQ2 =108, DQ3 =112
3752 10:01:30.211959 DQ4 =116, DQ5 =126, DQ6 =128, DQ7 =114
3753 10:01:30.215212 DQ8 =96, DQ9 =100, DQ10 =108, DQ11 =100
3754 10:01:30.221778 DQ12 =118, DQ13 =118, DQ14 =116, DQ15 =116
3755 10:01:30.222196
3756 10:01:30.222522
3757 10:01:30.228287 [DQSOSCAuto] RK1, (LSB)MR18= 0xf4ef, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
3758 10:01:30.231956 CH1 RK1: MR19=303, MR18=F4EF
3759 10:01:30.238190 CH1_RK1: MR19=0x303, MR18=0xF4EF, DQSOSC=415, MR23=63, INC=38, DEC=25
3760 10:01:30.241551 [RxdqsGatingPostProcess] freq 1200
3761 10:01:30.244438 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3762 10:01:30.248217 best DQS0 dly(2T, 0.5T) = (0, 11)
3763 10:01:30.251487 best DQS1 dly(2T, 0.5T) = (0, 11)
3764 10:01:30.254443 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3765 10:01:30.258263 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3766 10:01:30.261302 best DQS0 dly(2T, 0.5T) = (0, 11)
3767 10:01:30.265025 best DQS1 dly(2T, 0.5T) = (0, 11)
3768 10:01:30.267863 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3769 10:01:30.271245 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3770 10:01:30.274833 Pre-setting of DQS Precalculation
3771 10:01:30.277848 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3772 10:01:30.287462 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3773 10:01:30.294017 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3774 10:01:30.294440
3775 10:01:30.294773
3776 10:01:30.297619 [Calibration Summary] 2400 Mbps
3777 10:01:30.298064 CH 0, Rank 0
3778 10:01:30.300790 SW Impedance : PASS
3779 10:01:30.303986 DUTY Scan : NO K
3780 10:01:30.304408 ZQ Calibration : PASS
3781 10:01:30.307319 Jitter Meter : NO K
3782 10:01:30.307741 CBT Training : PASS
3783 10:01:30.310631 Write leveling : PASS
3784 10:01:30.313821 RX DQS gating : PASS
3785 10:01:30.314334 RX DQ/DQS(RDDQC) : PASS
3786 10:01:30.317275 TX DQ/DQS : PASS
3787 10:01:30.320763 RX DATLAT : PASS
3788 10:01:30.321182 RX DQ/DQS(Engine): PASS
3789 10:01:30.323902 TX OE : NO K
3790 10:01:30.324323 All Pass.
3791 10:01:30.324655
3792 10:01:30.327945 CH 0, Rank 1
3793 10:01:30.328455 SW Impedance : PASS
3794 10:01:30.330662 DUTY Scan : NO K
3795 10:01:30.334290 ZQ Calibration : PASS
3796 10:01:30.334815 Jitter Meter : NO K
3797 10:01:30.337051 CBT Training : PASS
3798 10:01:30.340283 Write leveling : PASS
3799 10:01:30.340806 RX DQS gating : PASS
3800 10:01:30.343410 RX DQ/DQS(RDDQC) : PASS
3801 10:01:30.347162 TX DQ/DQS : PASS
3802 10:01:30.347680 RX DATLAT : PASS
3803 10:01:30.350275 RX DQ/DQS(Engine): PASS
3804 10:01:30.353376 TX OE : NO K
3805 10:01:30.353845 All Pass.
3806 10:01:30.354183
3807 10:01:30.354494 CH 1, Rank 0
3808 10:01:30.356563 SW Impedance : PASS
3809 10:01:30.360451 DUTY Scan : NO K
3810 10:01:30.360874 ZQ Calibration : PASS
3811 10:01:30.363730 Jitter Meter : NO K
3812 10:01:30.366439 CBT Training : PASS
3813 10:01:30.366861 Write leveling : PASS
3814 10:01:30.369774 RX DQS gating : PASS
3815 10:01:30.373548 RX DQ/DQS(RDDQC) : PASS
3816 10:01:30.374060 TX DQ/DQS : PASS
3817 10:01:30.376892 RX DATLAT : PASS
3818 10:01:30.379416 RX DQ/DQS(Engine): PASS
3819 10:01:30.379834 TX OE : NO K
3820 10:01:30.380171 All Pass.
3821 10:01:30.382835
3822 10:01:30.383252 CH 1, Rank 1
3823 10:01:30.386206 SW Impedance : PASS
3824 10:01:30.386723 DUTY Scan : NO K
3825 10:01:30.389513 ZQ Calibration : PASS
3826 10:01:30.393513 Jitter Meter : NO K
3827 10:01:30.394037 CBT Training : PASS
3828 10:01:30.396453 Write leveling : PASS
3829 10:01:30.396871 RX DQS gating : PASS
3830 10:01:30.400610 RX DQ/DQS(RDDQC) : PASS
3831 10:01:30.402707 TX DQ/DQS : PASS
3832 10:01:30.403146 RX DATLAT : PASS
3833 10:01:30.406291 RX DQ/DQS(Engine): PASS
3834 10:01:30.409737 TX OE : NO K
3835 10:01:30.410232 All Pass.
3836 10:01:30.410565
3837 10:01:30.412761 DramC Write-DBI off
3838 10:01:30.413182 PER_BANK_REFRESH: Hybrid Mode
3839 10:01:30.416302 TX_TRACKING: ON
3840 10:01:30.426000 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3841 10:01:30.429159 [FAST_K] Save calibration result to emmc
3842 10:01:30.433067 dramc_set_vcore_voltage set vcore to 650000
3843 10:01:30.433718 Read voltage for 600, 5
3844 10:01:30.435949 Vio18 = 0
3845 10:01:30.436368 Vcore = 650000
3846 10:01:30.436700 Vdram = 0
3847 10:01:30.439617 Vddq = 0
3848 10:01:30.440135 Vmddr = 0
3849 10:01:30.446100 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3850 10:01:30.448997 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3851 10:01:30.452283 MEM_TYPE=3, freq_sel=19
3852 10:01:30.455548 sv_algorithm_assistance_LP4_1600
3853 10:01:30.459124 ============ PULL DRAM RESETB DOWN ============
3854 10:01:30.461860 ========== PULL DRAM RESETB DOWN end =========
3855 10:01:30.469203 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3856 10:01:30.472301 ===================================
3857 10:01:30.472913 LPDDR4 DRAM CONFIGURATION
3858 10:01:30.475404 ===================================
3859 10:01:30.478950 EX_ROW_EN[0] = 0x0
3860 10:01:30.482134 EX_ROW_EN[1] = 0x0
3861 10:01:30.482598 LP4Y_EN = 0x0
3862 10:01:30.485041 WORK_FSP = 0x0
3863 10:01:30.485676 WL = 0x2
3864 10:01:30.488566 RL = 0x2
3865 10:01:30.489021 BL = 0x2
3866 10:01:30.491933 RPST = 0x0
3867 10:01:30.492485 RD_PRE = 0x0
3868 10:01:30.495560 WR_PRE = 0x1
3869 10:01:30.495980 WR_PST = 0x0
3870 10:01:30.499110 DBI_WR = 0x0
3871 10:01:30.499650 DBI_RD = 0x0
3872 10:01:30.502105 OTF = 0x1
3873 10:01:30.505514 ===================================
3874 10:01:30.508668 ===================================
3875 10:01:30.509091 ANA top config
3876 10:01:30.511968 ===================================
3877 10:01:30.515056 DLL_ASYNC_EN = 0
3878 10:01:30.518347 ALL_SLAVE_EN = 1
3879 10:01:30.521824 NEW_RANK_MODE = 1
3880 10:01:30.522343 DLL_IDLE_MODE = 1
3881 10:01:30.524910 LP45_APHY_COMB_EN = 1
3882 10:01:30.528162 TX_ODT_DIS = 1
3883 10:01:30.531844 NEW_8X_MODE = 1
3884 10:01:30.535195 ===================================
3885 10:01:30.538129 ===================================
3886 10:01:30.542116 data_rate = 1200
3887 10:01:30.542607 CKR = 1
3888 10:01:30.544745 DQ_P2S_RATIO = 8
3889 10:01:30.548136 ===================================
3890 10:01:30.551548 CA_P2S_RATIO = 8
3891 10:01:30.554440 DQ_CA_OPEN = 0
3892 10:01:30.557510 DQ_SEMI_OPEN = 0
3893 10:01:30.560904 CA_SEMI_OPEN = 0
3894 10:01:30.564465 CA_FULL_RATE = 0
3895 10:01:30.564952 DQ_CKDIV4_EN = 1
3896 10:01:30.567421 CA_CKDIV4_EN = 1
3897 10:01:30.570760 CA_PREDIV_EN = 0
3898 10:01:30.574604 PH8_DLY = 0
3899 10:01:30.577593 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3900 10:01:30.581375 DQ_AAMCK_DIV = 4
3901 10:01:30.581833 CA_AAMCK_DIV = 4
3902 10:01:30.584049 CA_ADMCK_DIV = 4
3903 10:01:30.587511 DQ_TRACK_CA_EN = 0
3904 10:01:30.591288 CA_PICK = 600
3905 10:01:30.593827 CA_MCKIO = 600
3906 10:01:30.597940 MCKIO_SEMI = 0
3907 10:01:30.601087 PLL_FREQ = 2288
3908 10:01:30.601656 DQ_UI_PI_RATIO = 32
3909 10:01:30.604166 CA_UI_PI_RATIO = 0
3910 10:01:30.607505 ===================================
3911 10:01:30.610226 ===================================
3912 10:01:30.614649 memory_type:LPDDR4
3913 10:01:30.617051 GP_NUM : 10
3914 10:01:30.617537 SRAM_EN : 1
3915 10:01:30.620242 MD32_EN : 0
3916 10:01:30.623928 ===================================
3917 10:01:30.627237 [ANA_INIT] >>>>>>>>>>>>>>
3918 10:01:30.627752 <<<<<< [CONFIGURE PHASE]: ANA_TX
3919 10:01:30.634397 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3920 10:01:30.634926 ===================================
3921 10:01:30.636482 data_rate = 1200,PCW = 0X5800
3922 10:01:30.640639 ===================================
3923 10:01:30.643781 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3924 10:01:30.650082 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3925 10:01:30.657119 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3926 10:01:30.659670 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3927 10:01:30.663342 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3928 10:01:30.666699 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3929 10:01:30.669453 [ANA_INIT] flow start
3930 10:01:30.673077 [ANA_INIT] PLL >>>>>>>>
3931 10:01:30.673529 [ANA_INIT] PLL <<<<<<<<
3932 10:01:30.676191 [ANA_INIT] MIDPI >>>>>>>>
3933 10:01:30.679188 [ANA_INIT] MIDPI <<<<<<<<
3934 10:01:30.679783 [ANA_INIT] DLL >>>>>>>>
3935 10:01:30.682422 [ANA_INIT] flow end
3936 10:01:30.685657 ============ LP4 DIFF to SE enter ============
3937 10:01:30.689232 ============ LP4 DIFF to SE exit ============
3938 10:01:30.692803 [ANA_INIT] <<<<<<<<<<<<<
3939 10:01:30.696075 [Flow] Enable top DCM control >>>>>
3940 10:01:30.699204 [Flow] Enable top DCM control <<<<<
3941 10:01:30.702427 Enable DLL master slave shuffle
3942 10:01:30.709008 ==============================================================
3943 10:01:30.709603 Gating Mode config
3944 10:01:30.715947 ==============================================================
3945 10:01:30.719341 Config description:
3946 10:01:30.725878 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3947 10:01:30.732087 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3948 10:01:30.739150 SELPH_MODE 0: By rank 1: By Phase
3949 10:01:30.745515 ==============================================================
3950 10:01:30.746156 GAT_TRACK_EN = 1
3951 10:01:30.748652 RX_GATING_MODE = 2
3952 10:01:30.751930 RX_GATING_TRACK_MODE = 2
3953 10:01:30.755678 SELPH_MODE = 1
3954 10:01:30.758936 PICG_EARLY_EN = 1
3955 10:01:30.762731 VALID_LAT_VALUE = 1
3956 10:01:30.768437 ==============================================================
3957 10:01:30.772199 Enter into Gating configuration >>>>
3958 10:01:30.775622 Exit from Gating configuration <<<<
3959 10:01:30.778361 Enter into DVFS_PRE_config >>>>>
3960 10:01:30.788765 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3961 10:01:30.791881 Exit from DVFS_PRE_config <<<<<
3962 10:01:30.795450 Enter into PICG configuration >>>>
3963 10:01:30.798434 Exit from PICG configuration <<<<
3964 10:01:30.802367 [RX_INPUT] configuration >>>>>
3965 10:01:30.802834 [RX_INPUT] configuration <<<<<
3966 10:01:30.808657 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3967 10:01:30.815016 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3968 10:01:30.821395 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3969 10:01:30.824871 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3970 10:01:30.831470 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3971 10:01:30.837985 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3972 10:01:30.841512 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3973 10:01:30.844876 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3974 10:01:30.850940 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3975 10:01:30.854710 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3976 10:01:30.858230 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3977 10:01:30.864297 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3978 10:01:30.867721 ===================================
3979 10:01:30.868340 LPDDR4 DRAM CONFIGURATION
3980 10:01:30.871706 ===================================
3981 10:01:30.874298 EX_ROW_EN[0] = 0x0
3982 10:01:30.877623 EX_ROW_EN[1] = 0x0
3983 10:01:30.878072 LP4Y_EN = 0x0
3984 10:01:30.881213 WORK_FSP = 0x0
3985 10:01:30.881782 WL = 0x2
3986 10:01:30.884184 RL = 0x2
3987 10:01:30.884606 BL = 0x2
3988 10:01:30.887832 RPST = 0x0
3989 10:01:30.888251 RD_PRE = 0x0
3990 10:01:30.891136 WR_PRE = 0x1
3991 10:01:30.891550 WR_PST = 0x0
3992 10:01:30.894341 DBI_WR = 0x0
3993 10:01:30.894756 DBI_RD = 0x0
3994 10:01:30.897386 OTF = 0x1
3995 10:01:30.901498 ===================================
3996 10:01:30.904241 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3997 10:01:30.907548 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3998 10:01:30.914067 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3999 10:01:30.917358 ===================================
4000 10:01:30.917814 LPDDR4 DRAM CONFIGURATION
4001 10:01:30.920618 ===================================
4002 10:01:30.924073 EX_ROW_EN[0] = 0x10
4003 10:01:30.927901 EX_ROW_EN[1] = 0x0
4004 10:01:30.928318 LP4Y_EN = 0x0
4005 10:01:30.930858 WORK_FSP = 0x0
4006 10:01:30.931310 WL = 0x2
4007 10:01:30.933586 RL = 0x2
4008 10:01:30.934027 BL = 0x2
4009 10:01:30.937263 RPST = 0x0
4010 10:01:30.937759 RD_PRE = 0x0
4011 10:01:30.940147 WR_PRE = 0x1
4012 10:01:30.940563 WR_PST = 0x0
4013 10:01:30.943685 DBI_WR = 0x0
4014 10:01:30.944099 DBI_RD = 0x0
4015 10:01:30.947012 OTF = 0x1
4016 10:01:30.950417 ===================================
4017 10:01:30.957095 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4018 10:01:30.959999 nWR fixed to 30
4019 10:01:30.963374 [ModeRegInit_LP4] CH0 RK0
4020 10:01:30.963937 [ModeRegInit_LP4] CH0 RK1
4021 10:01:30.966460 [ModeRegInit_LP4] CH1 RK0
4022 10:01:30.969805 [ModeRegInit_LP4] CH1 RK1
4023 10:01:30.970220 match AC timing 17
4024 10:01:30.976513 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4025 10:01:30.980051 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4026 10:01:30.983198 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4027 10:01:30.989896 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4028 10:01:30.993035 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4029 10:01:30.993496 ==
4030 10:01:30.996288 Dram Type= 6, Freq= 0, CH_0, rank 0
4031 10:01:31.000160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4032 10:01:31.000579 ==
4033 10:01:31.006627 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4034 10:01:31.012834 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4035 10:01:31.016886 [CA 0] Center 36 (6~66) winsize 61
4036 10:01:31.019497 [CA 1] Center 36 (6~66) winsize 61
4037 10:01:31.022613 [CA 2] Center 34 (4~64) winsize 61
4038 10:01:31.025939 [CA 3] Center 34 (4~64) winsize 61
4039 10:01:31.029746 [CA 4] Center 33 (3~64) winsize 62
4040 10:01:31.032925 [CA 5] Center 33 (2~64) winsize 63
4041 10:01:31.033343
4042 10:01:31.036690 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4043 10:01:31.037198
4044 10:01:31.039206 [CATrainingPosCal] consider 1 rank data
4045 10:01:31.043599 u2DelayCellTimex100 = 270/100 ps
4046 10:01:31.046246 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4047 10:01:31.049582 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4048 10:01:31.052679 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4049 10:01:31.056204 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4050 10:01:31.062358 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4051 10:01:31.065339 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4052 10:01:31.065827
4053 10:01:31.069536 CA PerBit enable=1, Macro0, CA PI delay=33
4054 10:01:31.069956
4055 10:01:31.072433 [CBTSetCACLKResult] CA Dly = 33
4056 10:01:31.072848 CS Dly: 6 (0~37)
4057 10:01:31.073361 ==
4058 10:01:31.075521 Dram Type= 6, Freq= 0, CH_0, rank 1
4059 10:01:31.081937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4060 10:01:31.082377 ==
4061 10:01:31.085470 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4062 10:01:31.091887 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4063 10:01:31.095298 [CA 0] Center 35 (5~66) winsize 62
4064 10:01:31.098702 [CA 1] Center 36 (6~66) winsize 61
4065 10:01:31.101940 [CA 2] Center 33 (3~64) winsize 62
4066 10:01:31.105030 [CA 3] Center 33 (3~64) winsize 62
4067 10:01:31.108456 [CA 4] Center 33 (2~64) winsize 63
4068 10:01:31.112156 [CA 5] Center 33 (2~64) winsize 63
4069 10:01:31.112571
4070 10:01:31.115067 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4071 10:01:31.115481
4072 10:01:31.118495 [CATrainingPosCal] consider 2 rank data
4073 10:01:31.121837 u2DelayCellTimex100 = 270/100 ps
4074 10:01:31.125008 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4075 10:01:31.131738 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4076 10:01:31.134821 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4077 10:01:31.137715 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4078 10:01:31.141294 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4079 10:01:31.144770 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4080 10:01:31.144851
4081 10:01:31.147321 CA PerBit enable=1, Macro0, CA PI delay=33
4082 10:01:31.147402
4083 10:01:31.151084 [CBTSetCACLKResult] CA Dly = 33
4084 10:01:31.154421 CS Dly: 6 (0~38)
4085 10:01:31.154502
4086 10:01:31.157366 ----->DramcWriteLeveling(PI) begin...
4087 10:01:31.157467 ==
4088 10:01:31.160761 Dram Type= 6, Freq= 0, CH_0, rank 0
4089 10:01:31.164144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4090 10:01:31.164226 ==
4091 10:01:31.167764 Write leveling (Byte 0): 34 => 34
4092 10:01:31.170823 Write leveling (Byte 1): 30 => 30
4093 10:01:31.174675 DramcWriteLeveling(PI) end<-----
4094 10:01:31.174829
4095 10:01:31.174920 ==
4096 10:01:31.177377 Dram Type= 6, Freq= 0, CH_0, rank 0
4097 10:01:31.180744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4098 10:01:31.180826 ==
4099 10:01:31.184045 [Gating] SW mode calibration
4100 10:01:31.190681 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4101 10:01:31.197213 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4102 10:01:31.200460 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4103 10:01:31.204001 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4104 10:01:31.210387 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4105 10:01:31.213512 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4106 10:01:31.216935 0 9 16 | B1->B0 | 2d2d 2727 | 1 0 | (1 0) (0 0)
4107 10:01:31.223858 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4108 10:01:31.226723 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4109 10:01:31.229956 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4110 10:01:31.236906 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4111 10:01:31.240507 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4112 10:01:31.244035 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4113 10:01:31.250346 0 10 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4114 10:01:31.253974 0 10 16 | B1->B0 | 3434 4343 | 0 0 | (0 0) (0 0)
4115 10:01:31.256687 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4116 10:01:31.263633 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4117 10:01:31.267724 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4118 10:01:31.270103 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4119 10:01:31.277006 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4120 10:01:31.279971 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4121 10:01:31.284011 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4122 10:01:31.290142 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4123 10:01:31.293651 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4124 10:01:31.296599 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4125 10:01:31.303681 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4126 10:01:31.306949 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4127 10:01:31.310148 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4128 10:01:31.316748 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4129 10:01:31.319644 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4130 10:01:31.323791 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4131 10:01:31.329949 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4132 10:01:31.332941 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4133 10:01:31.336393 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4134 10:01:31.342619 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4135 10:01:31.345933 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4136 10:01:31.349312 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4137 10:01:31.355533 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4138 10:01:31.358799 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4139 10:01:31.362818 Total UI for P1: 0, mck2ui 16
4140 10:01:31.365664 best dqsien dly found for B0: ( 0, 13, 12)
4141 10:01:31.368584 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4142 10:01:31.372301 Total UI for P1: 0, mck2ui 16
4143 10:01:31.375252 best dqsien dly found for B1: ( 0, 13, 18)
4144 10:01:31.378564 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4145 10:01:31.385010 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4146 10:01:31.385471
4147 10:01:31.388543 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4148 10:01:31.391667 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4149 10:01:31.395549 [Gating] SW calibration Done
4150 10:01:31.395964 ==
4151 10:01:31.398432 Dram Type= 6, Freq= 0, CH_0, rank 0
4152 10:01:31.401668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 10:01:31.402090 ==
4154 10:01:31.404894 RX Vref Scan: 0
4155 10:01:31.405310
4156 10:01:31.405691 RX Vref 0 -> 0, step: 1
4157 10:01:31.406167
4158 10:01:31.408153 RX Delay -230 -> 252, step: 16
4159 10:01:31.411657 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4160 10:01:31.418240 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4161 10:01:31.421620 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4162 10:01:31.424888 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4163 10:01:31.428015 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4164 10:01:31.434843 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4165 10:01:31.437933 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4166 10:01:31.441360 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4167 10:01:31.444675 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4168 10:01:31.451543 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4169 10:01:31.454333 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4170 10:01:31.457896 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4171 10:01:31.460691 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4172 10:01:31.467692 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4173 10:01:31.471051 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4174 10:01:31.473989 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4175 10:01:31.474438 ==
4176 10:01:31.477461 Dram Type= 6, Freq= 0, CH_0, rank 0
4177 10:01:31.480535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4178 10:01:31.484337 ==
4179 10:01:31.484750 DQS Delay:
4180 10:01:31.485083 DQS0 = 0, DQS1 = 0
4181 10:01:31.487292 DQM Delay:
4182 10:01:31.487705 DQM0 = 43, DQM1 = 35
4183 10:01:31.490616 DQ Delay:
4184 10:01:31.491030 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4185 10:01:31.493844 DQ4 =41, DQ5 =41, DQ6 =49, DQ7 =49
4186 10:01:31.497402 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =33
4187 10:01:31.500196 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4188 10:01:31.503502
4189 10:01:31.503913
4190 10:01:31.504245 ==
4191 10:01:31.507343 Dram Type= 6, Freq= 0, CH_0, rank 0
4192 10:01:31.510170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4193 10:01:31.510721 ==
4194 10:01:31.511186
4195 10:01:31.511668
4196 10:01:31.513473 TX Vref Scan disable
4197 10:01:31.513892 == TX Byte 0 ==
4198 10:01:31.520106 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4199 10:01:31.523863 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4200 10:01:31.524380 == TX Byte 1 ==
4201 10:01:31.529849 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4202 10:01:31.533178 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4203 10:01:31.533680 ==
4204 10:01:31.537166 Dram Type= 6, Freq= 0, CH_0, rank 0
4205 10:01:31.540206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4206 10:01:31.540623 ==
4207 10:01:31.540954
4208 10:01:31.543311
4209 10:01:31.543726 TX Vref Scan disable
4210 10:01:31.546838 == TX Byte 0 ==
4211 10:01:31.550107 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4212 10:01:31.557201 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4213 10:01:31.557666 == TX Byte 1 ==
4214 10:01:31.559893 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4215 10:01:31.566410 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4216 10:01:31.566828
4217 10:01:31.567159 [DATLAT]
4218 10:01:31.567465 Freq=600, CH0 RK0
4219 10:01:31.567792
4220 10:01:31.569661 DATLAT Default: 0x9
4221 10:01:31.570076 0, 0xFFFF, sum = 0
4222 10:01:31.573118 1, 0xFFFF, sum = 0
4223 10:01:31.576513 2, 0xFFFF, sum = 0
4224 10:01:31.576944 3, 0xFFFF, sum = 0
4225 10:01:31.580416 4, 0xFFFF, sum = 0
4226 10:01:31.580838 5, 0xFFFF, sum = 0
4227 10:01:31.582882 6, 0xFFFF, sum = 0
4228 10:01:31.583302 7, 0xFFFF, sum = 0
4229 10:01:31.586452 8, 0x0, sum = 1
4230 10:01:31.586873 9, 0x0, sum = 2
4231 10:01:31.589517 10, 0x0, sum = 3
4232 10:01:31.590109 11, 0x0, sum = 4
4233 10:01:31.590464 best_step = 9
4234 10:01:31.590774
4235 10:01:31.593210 ==
4236 10:01:31.593689 Dram Type= 6, Freq= 0, CH_0, rank 0
4237 10:01:31.599348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4238 10:01:31.599850 ==
4239 10:01:31.600324 RX Vref Scan: 1
4240 10:01:31.600653
4241 10:01:31.602934 RX Vref 0 -> 0, step: 1
4242 10:01:31.603349
4243 10:01:31.606205 RX Delay -195 -> 252, step: 8
4244 10:01:31.606620
4245 10:01:31.609776 Set Vref, RX VrefLevel [Byte0]: 60
4246 10:01:31.612579 [Byte1]: 48
4247 10:01:31.612995
4248 10:01:31.615849 Final RX Vref Byte 0 = 60 to rank0
4249 10:01:31.619437 Final RX Vref Byte 1 = 48 to rank0
4250 10:01:31.622727 Final RX Vref Byte 0 = 60 to rank1
4251 10:01:31.625766 Final RX Vref Byte 1 = 48 to rank1==
4252 10:01:31.629238 Dram Type= 6, Freq= 0, CH_0, rank 0
4253 10:01:31.633122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4254 10:01:31.635868 ==
4255 10:01:31.636282 DQS Delay:
4256 10:01:31.636685 DQS0 = 0, DQS1 = 0
4257 10:01:31.639004 DQM Delay:
4258 10:01:31.639446 DQM0 = 43, DQM1 = 32
4259 10:01:31.642131 DQ Delay:
4260 10:01:31.642457 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4261 10:01:31.646035 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4262 10:01:31.648805 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4263 10:01:31.651974 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4264 10:01:31.655264
4265 10:01:31.655652
4266 10:01:31.661880 [DQSOSCAuto] RK0, (LSB)MR18= 0x683f, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 390 ps
4267 10:01:31.665284 CH0 RK0: MR19=808, MR18=683F
4268 10:01:31.672226 CH0_RK0: MR19=0x808, MR18=0x683F, DQSOSC=390, MR23=63, INC=172, DEC=114
4269 10:01:31.672386
4270 10:01:31.674906 ----->DramcWriteLeveling(PI) begin...
4271 10:01:31.675064 ==
4272 10:01:31.678169 Dram Type= 6, Freq= 0, CH_0, rank 1
4273 10:01:31.681445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4274 10:01:31.681592 ==
4275 10:01:31.685132 Write leveling (Byte 0): 32 => 32
4276 10:01:31.687860 Write leveling (Byte 1): 30 => 30
4277 10:01:31.691371 DramcWriteLeveling(PI) end<-----
4278 10:01:31.691501
4279 10:01:31.691602 ==
4280 10:01:31.694802 Dram Type= 6, Freq= 0, CH_0, rank 1
4281 10:01:31.697920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4282 10:01:31.698102 ==
4283 10:01:31.701327 [Gating] SW mode calibration
4284 10:01:31.708220 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4285 10:01:31.714517 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4286 10:01:31.718018 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4287 10:01:31.724560 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4288 10:01:31.727610 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4289 10:01:31.731242 0 9 12 | B1->B0 | 3434 3333 | 0 1 | (0 1) (0 1)
4290 10:01:31.737907 0 9 16 | B1->B0 | 2e2e 2626 | 0 0 | (0 0) (0 0)
4291 10:01:31.741213 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4292 10:01:31.744399 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4293 10:01:31.750896 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4294 10:01:31.753952 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4295 10:01:31.757146 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4296 10:01:31.764008 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4297 10:01:31.767127 0 10 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4298 10:01:31.771102 0 10 16 | B1->B0 | 3c3c 4242 | 0 0 | (0 0) (0 0)
4299 10:01:31.777033 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4300 10:01:31.781050 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4301 10:01:31.784022 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4302 10:01:31.790441 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4303 10:01:31.793785 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4304 10:01:31.797253 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4305 10:01:31.803915 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4306 10:01:31.807502 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4307 10:01:31.810728 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4308 10:01:31.813819 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4309 10:01:31.820503 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4310 10:01:31.823963 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4311 10:01:31.826932 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4312 10:01:31.834173 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4313 10:01:31.837301 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4314 10:01:31.841002 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4315 10:01:31.847164 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4316 10:01:31.850808 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4317 10:01:31.853535 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4318 10:01:31.860416 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4319 10:01:31.863542 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4320 10:01:31.867178 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4321 10:01:31.873519 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4322 10:01:31.877121 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4323 10:01:31.880888 Total UI for P1: 0, mck2ui 16
4324 10:01:31.883806 best dqsien dly found for B0: ( 0, 13, 12)
4325 10:01:31.886734 Total UI for P1: 0, mck2ui 16
4326 10:01:31.890726 best dqsien dly found for B1: ( 0, 13, 14)
4327 10:01:31.893375 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4328 10:01:31.896855 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4329 10:01:31.897272
4330 10:01:31.900196 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4331 10:01:31.906708 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4332 10:01:31.907132 [Gating] SW calibration Done
4333 10:01:31.907470 ==
4334 10:01:31.909754 Dram Type= 6, Freq= 0, CH_0, rank 1
4335 10:01:31.916721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4336 10:01:31.917146 ==
4337 10:01:31.917518 RX Vref Scan: 0
4338 10:01:31.917834
4339 10:01:31.919931 RX Vref 0 -> 0, step: 1
4340 10:01:31.920349
4341 10:01:31.923102 RX Delay -230 -> 252, step: 16
4342 10:01:31.926565 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4343 10:01:31.930397 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4344 10:01:31.933771 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4345 10:01:31.939842 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4346 10:01:31.942930 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4347 10:01:31.946052 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4348 10:01:31.949179 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4349 10:01:31.956099 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4350 10:01:31.959040 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4351 10:01:31.962745 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4352 10:01:31.966227 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4353 10:01:31.972759 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4354 10:01:31.975907 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4355 10:01:31.979073 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4356 10:01:31.982839 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4357 10:01:31.989230 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4358 10:01:31.989428 ==
4359 10:01:31.992131 Dram Type= 6, Freq= 0, CH_0, rank 1
4360 10:01:31.995404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4361 10:01:31.995662 ==
4362 10:01:31.995883 DQS Delay:
4363 10:01:31.999118 DQS0 = 0, DQS1 = 0
4364 10:01:31.999374 DQM Delay:
4365 10:01:32.002022 DQM0 = 47, DQM1 = 42
4366 10:01:32.002278 DQ Delay:
4367 10:01:32.005318 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4368 10:01:32.008915 DQ4 =41, DQ5 =41, DQ6 =57, DQ7 =57
4369 10:01:32.012016 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4370 10:01:32.015560 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4371 10:01:32.015940
4372 10:01:32.016281
4373 10:01:32.016612 ==
4374 10:01:32.018446 Dram Type= 6, Freq= 0, CH_0, rank 1
4375 10:01:32.021744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4376 10:01:32.025338 ==
4377 10:01:32.025746
4378 10:01:32.026100
4379 10:01:32.026442 TX Vref Scan disable
4380 10:01:32.028737 == TX Byte 0 ==
4381 10:01:32.031835 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4382 10:01:32.034902 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4383 10:01:32.038244 == TX Byte 1 ==
4384 10:01:32.042033 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4385 10:01:32.045082 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4386 10:01:32.048593 ==
4387 10:01:32.051699 Dram Type= 6, Freq= 0, CH_0, rank 1
4388 10:01:32.055103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4389 10:01:32.055456 ==
4390 10:01:32.055768
4391 10:01:32.056065
4392 10:01:32.058162 TX Vref Scan disable
4393 10:01:32.058518 == TX Byte 0 ==
4394 10:01:32.065137 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4395 10:01:32.068271 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4396 10:01:32.071166 == TX Byte 1 ==
4397 10:01:32.074620 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4398 10:01:32.077784 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4399 10:01:32.078036
4400 10:01:32.078235 [DATLAT]
4401 10:01:32.081631 Freq=600, CH0 RK1
4402 10:01:32.081883
4403 10:01:32.084972 DATLAT Default: 0x9
4404 10:01:32.085224 0, 0xFFFF, sum = 0
4405 10:01:32.087847 1, 0xFFFF, sum = 0
4406 10:01:32.088102 2, 0xFFFF, sum = 0
4407 10:01:32.091799 3, 0xFFFF, sum = 0
4408 10:01:32.092059 4, 0xFFFF, sum = 0
4409 10:01:32.094535 5, 0xFFFF, sum = 0
4410 10:01:32.094893 6, 0xFFFF, sum = 0
4411 10:01:32.098031 7, 0xFFFF, sum = 0
4412 10:01:32.098412 8, 0x0, sum = 1
4413 10:01:32.101267 9, 0x0, sum = 2
4414 10:01:32.101701 10, 0x0, sum = 3
4415 10:01:32.104583 11, 0x0, sum = 4
4416 10:01:32.104926 best_step = 9
4417 10:01:32.105286
4418 10:01:32.105652 ==
4419 10:01:32.107828 Dram Type= 6, Freq= 0, CH_0, rank 1
4420 10:01:32.110905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4421 10:01:32.111274 ==
4422 10:01:32.114163 RX Vref Scan: 0
4423 10:01:32.114520
4424 10:01:32.117755 RX Vref 0 -> 0, step: 1
4425 10:01:32.118123
4426 10:01:32.118458 RX Delay -179 -> 252, step: 8
4427 10:01:32.125260 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4428 10:01:32.128695 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4429 10:01:32.131630 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4430 10:01:32.135147 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4431 10:01:32.142047 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4432 10:01:32.145153 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4433 10:01:32.148724 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4434 10:01:32.152240 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4435 10:01:32.158426 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4436 10:01:32.161986 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4437 10:01:32.164899 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4438 10:01:32.168451 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4439 10:01:32.175000 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4440 10:01:32.178362 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4441 10:01:32.181525 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4442 10:01:32.184938 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4443 10:01:32.185034 ==
4444 10:01:32.187695 Dram Type= 6, Freq= 0, CH_0, rank 1
4445 10:01:32.194520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4446 10:01:32.194603 ==
4447 10:01:32.194668 DQS Delay:
4448 10:01:32.197868 DQS0 = 0, DQS1 = 0
4449 10:01:32.197950 DQM Delay:
4450 10:01:32.198015 DQM0 = 41, DQM1 = 37
4451 10:01:32.200951 DQ Delay:
4452 10:01:32.204316 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4453 10:01:32.207468 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4454 10:01:32.211024 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4455 10:01:32.214309 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4456 10:01:32.214390
4457 10:01:32.214454
4458 10:01:32.220694 [DQSOSCAuto] RK1, (LSB)MR18= 0x6619, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 390 ps
4459 10:01:32.224212 CH0 RK1: MR19=808, MR18=6619
4460 10:01:32.230812 CH0_RK1: MR19=0x808, MR18=0x6619, DQSOSC=390, MR23=63, INC=172, DEC=114
4461 10:01:32.234069 [RxdqsGatingPostProcess] freq 600
4462 10:01:32.237367 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4463 10:01:32.241094 Pre-setting of DQS Precalculation
4464 10:01:32.247396 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4465 10:01:32.247478 ==
4466 10:01:32.250578 Dram Type= 6, Freq= 0, CH_1, rank 0
4467 10:01:32.253820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4468 10:01:32.253902 ==
4469 10:01:32.260564 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4470 10:01:32.267133 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4471 10:01:32.270483 [CA 0] Center 35 (5~66) winsize 62
4472 10:01:32.274210 [CA 1] Center 35 (5~66) winsize 62
4473 10:01:32.276859 [CA 2] Center 34 (4~65) winsize 62
4474 10:01:32.280139 [CA 3] Center 33 (3~64) winsize 62
4475 10:01:32.283618 [CA 4] Center 34 (4~65) winsize 62
4476 10:01:32.286966 [CA 5] Center 33 (3~64) winsize 62
4477 10:01:32.287048
4478 10:01:32.290399 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4479 10:01:32.290480
4480 10:01:32.293540 [CATrainingPosCal] consider 1 rank data
4481 10:01:32.296559 u2DelayCellTimex100 = 270/100 ps
4482 10:01:32.299815 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4483 10:01:32.303358 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4484 10:01:32.306610 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4485 10:01:32.309625 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4486 10:01:32.313443 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4487 10:01:32.316593 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4488 10:01:32.320117
4489 10:01:32.323058 CA PerBit enable=1, Macro0, CA PI delay=33
4490 10:01:32.323141
4491 10:01:32.326248 [CBTSetCACLKResult] CA Dly = 33
4492 10:01:32.326318 CS Dly: 4 (0~35)
4493 10:01:32.326386 ==
4494 10:01:32.329575 Dram Type= 6, Freq= 0, CH_1, rank 1
4495 10:01:32.332705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4496 10:01:32.336386 ==
4497 10:01:32.339306 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4498 10:01:32.345925 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4499 10:01:32.349106 [CA 0] Center 35 (5~66) winsize 62
4500 10:01:32.352629 [CA 1] Center 36 (6~66) winsize 61
4501 10:01:32.356013 [CA 2] Center 34 (4~65) winsize 62
4502 10:01:32.359053 [CA 3] Center 34 (3~65) winsize 63
4503 10:01:32.362538 [CA 4] Center 34 (3~65) winsize 63
4504 10:01:32.366336 [CA 5] Center 34 (3~65) winsize 63
4505 10:01:32.366410
4506 10:01:32.369687 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4507 10:01:32.369756
4508 10:01:32.372620 [CATrainingPosCal] consider 2 rank data
4509 10:01:32.376011 u2DelayCellTimex100 = 270/100 ps
4510 10:01:32.379286 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4511 10:01:32.382465 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4512 10:01:32.385885 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4513 10:01:32.392205 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4514 10:01:32.395757 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4515 10:01:32.399092 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4516 10:01:32.399174
4517 10:01:32.402591 CA PerBit enable=1, Macro0, CA PI delay=33
4518 10:01:32.402673
4519 10:01:32.405704 [CBTSetCACLKResult] CA Dly = 33
4520 10:01:32.405786 CS Dly: 4 (0~36)
4521 10:01:32.405850
4522 10:01:32.409288 ----->DramcWriteLeveling(PI) begin...
4523 10:01:32.411861 ==
4524 10:01:32.411943 Dram Type= 6, Freq= 0, CH_1, rank 0
4525 10:01:32.419250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4526 10:01:32.419332 ==
4527 10:01:32.422204 Write leveling (Byte 0): 29 => 29
4528 10:01:32.425304 Write leveling (Byte 1): 33 => 33
4529 10:01:32.428556 DramcWriteLeveling(PI) end<-----
4530 10:01:32.428638
4531 10:01:32.428702 ==
4532 10:01:32.431996 Dram Type= 6, Freq= 0, CH_1, rank 0
4533 10:01:32.435655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4534 10:01:32.435736 ==
4535 10:01:32.438991 [Gating] SW mode calibration
4536 10:01:32.444875 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4537 10:01:32.451482 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4538 10:01:32.455422 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4539 10:01:32.458839 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4540 10:01:32.464731 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4541 10:01:32.467893 0 9 12 | B1->B0 | 3030 2f2f | 0 1 | (0 1) (0 0)
4542 10:01:32.471741 0 9 16 | B1->B0 | 2828 2323 | 1 0 | (1 0) (1 0)
4543 10:01:32.478268 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4544 10:01:32.481362 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4545 10:01:32.485525 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4546 10:01:32.491303 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4547 10:01:32.494617 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4548 10:01:32.497887 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4549 10:01:32.504668 0 10 12 | B1->B0 | 3231 3636 | 1 0 | (0 0) (0 0)
4550 10:01:32.507909 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4551 10:01:32.511383 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4552 10:01:32.517819 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4553 10:01:32.521136 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4554 10:01:32.524685 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4555 10:01:32.531413 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4556 10:01:32.535312 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4557 10:01:32.537795 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4558 10:01:32.544184 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4559 10:01:32.547347 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4560 10:01:32.550488 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4561 10:01:32.557553 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4562 10:01:32.560417 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4563 10:01:32.563779 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4564 10:01:32.570829 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4565 10:01:32.573545 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4566 10:01:32.577165 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4567 10:01:32.583672 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4568 10:01:32.586726 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4569 10:01:32.589878 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4570 10:01:32.596651 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4571 10:01:32.599937 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4572 10:01:32.603378 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4573 10:01:32.609684 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4574 10:01:32.613128 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4575 10:01:32.616351 Total UI for P1: 0, mck2ui 16
4576 10:01:32.619673 best dqsien dly found for B0: ( 0, 13, 10)
4577 10:01:32.623052 Total UI for P1: 0, mck2ui 16
4578 10:01:32.626596 best dqsien dly found for B1: ( 0, 13, 12)
4579 10:01:32.629760 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4580 10:01:32.633222 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4581 10:01:32.633303
4582 10:01:32.636093 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4583 10:01:32.639816 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4584 10:01:32.643331 [Gating] SW calibration Done
4585 10:01:32.643412 ==
4586 10:01:32.646214 Dram Type= 6, Freq= 0, CH_1, rank 0
4587 10:01:32.649895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 10:01:32.652685 ==
4589 10:01:32.652766 RX Vref Scan: 0
4590 10:01:32.652831
4591 10:01:32.656141 RX Vref 0 -> 0, step: 1
4592 10:01:32.656222
4593 10:01:32.659173 RX Delay -230 -> 252, step: 16
4594 10:01:32.663380 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4595 10:01:32.665945 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4596 10:01:32.669818 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4597 10:01:32.676124 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4598 10:01:32.679378 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4599 10:01:32.682700 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4600 10:01:32.685591 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4601 10:01:32.689029 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4602 10:01:32.695461 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4603 10:01:32.698927 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4604 10:01:32.702188 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4605 10:01:32.705699 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4606 10:01:32.712631 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4607 10:01:32.715515 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4608 10:01:32.718808 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4609 10:01:32.721888 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4610 10:01:32.725139 ==
4611 10:01:32.728928 Dram Type= 6, Freq= 0, CH_1, rank 0
4612 10:01:32.732249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4613 10:01:32.732330 ==
4614 10:01:32.732395 DQS Delay:
4615 10:01:32.735263 DQS0 = 0, DQS1 = 0
4616 10:01:32.735345 DQM Delay:
4617 10:01:32.738490 DQM0 = 46, DQM1 = 38
4618 10:01:32.738571 DQ Delay:
4619 10:01:32.741935 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =41
4620 10:01:32.745310 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4621 10:01:32.748211 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4622 10:01:32.751727 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4623 10:01:32.751809
4624 10:01:32.751873
4625 10:01:32.751933 ==
4626 10:01:32.755782 Dram Type= 6, Freq= 0, CH_1, rank 0
4627 10:01:32.758553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4628 10:01:32.758635 ==
4629 10:01:32.758699
4630 10:01:32.758758
4631 10:01:32.761727 TX Vref Scan disable
4632 10:01:32.764876 == TX Byte 0 ==
4633 10:01:32.768427 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4634 10:01:32.771896 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4635 10:01:32.775237 == TX Byte 1 ==
4636 10:01:32.778713 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4637 10:01:32.782447 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4638 10:01:32.782869 ==
4639 10:01:32.785442 Dram Type= 6, Freq= 0, CH_1, rank 0
4640 10:01:32.791698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4641 10:01:32.792116 ==
4642 10:01:32.792447
4643 10:01:32.792748
4644 10:01:32.793035 TX Vref Scan disable
4645 10:01:32.796306 == TX Byte 0 ==
4646 10:01:32.799362 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4647 10:01:32.806130 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4648 10:01:32.806563 == TX Byte 1 ==
4649 10:01:32.809371 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4650 10:01:32.816806 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4651 10:01:32.817218
4652 10:01:32.817590 [DATLAT]
4653 10:01:32.817901 Freq=600, CH1 RK0
4654 10:01:32.818203
4655 10:01:32.819122 DATLAT Default: 0x9
4656 10:01:32.822561 0, 0xFFFF, sum = 0
4657 10:01:32.822979 1, 0xFFFF, sum = 0
4658 10:01:32.826199 2, 0xFFFF, sum = 0
4659 10:01:32.826616 3, 0xFFFF, sum = 0
4660 10:01:32.829213 4, 0xFFFF, sum = 0
4661 10:01:32.829663 5, 0xFFFF, sum = 0
4662 10:01:32.832326 6, 0xFFFF, sum = 0
4663 10:01:32.832741 7, 0xFFFF, sum = 0
4664 10:01:32.835751 8, 0x0, sum = 1
4665 10:01:32.836219 9, 0x0, sum = 2
4666 10:01:32.838907 10, 0x0, sum = 3
4667 10:01:32.839376 11, 0x0, sum = 4
4668 10:01:32.839747 best_step = 9
4669 10:01:32.840097
4670 10:01:32.842316 ==
4671 10:01:32.846007 Dram Type= 6, Freq= 0, CH_1, rank 0
4672 10:01:32.848706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4673 10:01:32.849128 ==
4674 10:01:32.849481 RX Vref Scan: 1
4675 10:01:32.849997
4676 10:01:32.852510 RX Vref 0 -> 0, step: 1
4677 10:01:32.852963
4678 10:01:32.855545 RX Delay -179 -> 252, step: 8
4679 10:01:32.855966
4680 10:01:32.858982 Set Vref, RX VrefLevel [Byte0]: 53
4681 10:01:32.861921 [Byte1]: 51
4682 10:01:32.862345
4683 10:01:32.865486 Final RX Vref Byte 0 = 53 to rank0
4684 10:01:32.868325 Final RX Vref Byte 1 = 51 to rank0
4685 10:01:32.871766 Final RX Vref Byte 0 = 53 to rank1
4686 10:01:32.875476 Final RX Vref Byte 1 = 51 to rank1==
4687 10:01:32.878885 Dram Type= 6, Freq= 0, CH_1, rank 0
4688 10:01:32.881484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4689 10:01:32.884911 ==
4690 10:01:32.885330 DQS Delay:
4691 10:01:32.885823 DQS0 = 0, DQS1 = 0
4692 10:01:32.888065 DQM Delay:
4693 10:01:32.888482 DQM0 = 47, DQM1 = 37
4694 10:01:32.891689 DQ Delay:
4695 10:01:32.894692 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =48
4696 10:01:32.898705 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4697 10:01:32.901566 DQ8 =28, DQ9 =28, DQ10 =40, DQ11 =28
4698 10:01:32.904546 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4699 10:01:32.905043
4700 10:01:32.905530
4701 10:01:32.911779 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c31, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4702 10:01:32.914658 CH1 RK0: MR19=808, MR18=4C31
4703 10:01:32.921658 CH1_RK0: MR19=0x808, MR18=0x4C31, DQSOSC=395, MR23=63, INC=168, DEC=112
4704 10:01:32.922131
4705 10:01:32.924567 ----->DramcWriteLeveling(PI) begin...
4706 10:01:32.924991 ==
4707 10:01:32.927813 Dram Type= 6, Freq= 0, CH_1, rank 1
4708 10:01:32.930851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4709 10:01:32.931276 ==
4710 10:01:32.934350 Write leveling (Byte 0): 29 => 29
4711 10:01:32.937724 Write leveling (Byte 1): 30 => 30
4712 10:01:32.941525 DramcWriteLeveling(PI) end<-----
4713 10:01:32.941947
4714 10:01:32.942276 ==
4715 10:01:32.943980 Dram Type= 6, Freq= 0, CH_1, rank 1
4716 10:01:32.948050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4717 10:01:32.950854 ==
4718 10:01:32.951278 [Gating] SW mode calibration
4719 10:01:32.960351 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4720 10:01:32.964013 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4721 10:01:32.967501 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4722 10:01:32.973709 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4723 10:01:32.976938 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4724 10:01:32.980235 0 9 12 | B1->B0 | 2f2f 3333 | 1 1 | (0 0) (1 0)
4725 10:01:32.986698 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4726 10:01:32.990175 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4727 10:01:32.993369 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4728 10:01:33.000205 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4729 10:01:33.003469 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4730 10:01:33.006624 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4731 10:01:33.013393 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4732 10:01:33.017870 0 10 12 | B1->B0 | 3a3a 2e2e | 1 0 | (0 0) (0 0)
4733 10:01:33.019986 0 10 16 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
4734 10:01:33.026485 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4735 10:01:33.029879 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4736 10:01:33.033237 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4737 10:01:33.040237 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4738 10:01:33.043021 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4739 10:01:33.046317 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4740 10:01:33.053216 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4741 10:01:33.056604 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4742 10:01:33.059477 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4743 10:01:33.066360 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4744 10:01:33.069523 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4745 10:01:33.073115 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4746 10:01:33.079144 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4747 10:01:33.082562 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4748 10:01:33.085964 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4749 10:01:33.092741 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4750 10:01:33.095783 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4751 10:01:33.098998 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4752 10:01:33.106286 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4753 10:01:33.109165 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4754 10:01:33.112638 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4755 10:01:33.118904 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4756 10:01:33.122286 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4757 10:01:33.125548 Total UI for P1: 0, mck2ui 16
4758 10:01:33.128743 best dqsien dly found for B1: ( 0, 13, 10)
4759 10:01:33.132241 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4760 10:01:33.135406 Total UI for P1: 0, mck2ui 16
4761 10:01:33.139436 best dqsien dly found for B0: ( 0, 13, 12)
4762 10:01:33.142485 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4763 10:01:33.145691 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4764 10:01:33.149101
4765 10:01:33.152507 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4766 10:01:33.155480 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4767 10:01:33.158338 [Gating] SW calibration Done
4768 10:01:33.158802 ==
4769 10:01:33.162003 Dram Type= 6, Freq= 0, CH_1, rank 1
4770 10:01:33.165948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4771 10:01:33.166505 ==
4772 10:01:33.166878 RX Vref Scan: 0
4773 10:01:33.168715
4774 10:01:33.169179 RX Vref 0 -> 0, step: 1
4775 10:01:33.169611
4776 10:01:33.171508 RX Delay -230 -> 252, step: 16
4777 10:01:33.175360 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4778 10:01:33.182407 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4779 10:01:33.185495 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4780 10:01:33.188485 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4781 10:01:33.191979 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4782 10:01:33.195230 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4783 10:01:33.201301 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4784 10:01:33.204920 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4785 10:01:33.208039 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4786 10:01:33.211240 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4787 10:01:33.218060 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4788 10:01:33.221089 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4789 10:01:33.224635 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4790 10:01:33.228325 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4791 10:01:33.235371 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4792 10:01:33.237720 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4793 10:01:33.238222 ==
4794 10:01:33.241263 Dram Type= 6, Freq= 0, CH_1, rank 1
4795 10:01:33.244456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4796 10:01:33.244903 ==
4797 10:01:33.247821 DQS Delay:
4798 10:01:33.248238 DQS0 = 0, DQS1 = 0
4799 10:01:33.248569 DQM Delay:
4800 10:01:33.251297 DQM0 = 43, DQM1 = 35
4801 10:01:33.251717 DQ Delay:
4802 10:01:33.254136 DQ0 =57, DQ1 =41, DQ2 =25, DQ3 =41
4803 10:01:33.257796 DQ4 =33, DQ5 =57, DQ6 =57, DQ7 =33
4804 10:01:33.261048 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4805 10:01:33.264096 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4806 10:01:33.264514
4807 10:01:33.264842
4808 10:01:33.265151 ==
4809 10:01:33.267346 Dram Type= 6, Freq= 0, CH_1, rank 1
4810 10:01:33.274170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4811 10:01:33.274593 ==
4812 10:01:33.274933
4813 10:01:33.275242
4814 10:01:33.275541 TX Vref Scan disable
4815 10:01:33.278191 == TX Byte 0 ==
4816 10:01:33.281440 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4817 10:01:33.287843 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4818 10:01:33.288267 == TX Byte 1 ==
4819 10:01:33.291081 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4820 10:01:33.297883 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4821 10:01:33.298304 ==
4822 10:01:33.300873 Dram Type= 6, Freq= 0, CH_1, rank 1
4823 10:01:33.304364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4824 10:01:33.304787 ==
4825 10:01:33.305122
4826 10:01:33.305470
4827 10:01:33.307624 TX Vref Scan disable
4828 10:01:33.310938 == TX Byte 0 ==
4829 10:01:33.314469 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4830 10:01:33.317754 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4831 10:01:33.320699 == TX Byte 1 ==
4832 10:01:33.324780 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4833 10:01:33.327369 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4834 10:01:33.327858
4835 10:01:33.331722 [DATLAT]
4836 10:01:33.332275 Freq=600, CH1 RK1
4837 10:01:33.332639
4838 10:01:33.333976 DATLAT Default: 0x9
4839 10:01:33.334461 0, 0xFFFF, sum = 0
4840 10:01:33.337609 1, 0xFFFF, sum = 0
4841 10:01:33.338127 2, 0xFFFF, sum = 0
4842 10:01:33.341199 3, 0xFFFF, sum = 0
4843 10:01:33.341862 4, 0xFFFF, sum = 0
4844 10:01:33.343845 5, 0xFFFF, sum = 0
4845 10:01:33.344318 6, 0xFFFF, sum = 0
4846 10:01:33.347182 7, 0xFFFF, sum = 0
4847 10:01:33.347747 8, 0x0, sum = 1
4848 10:01:33.350340 9, 0x0, sum = 2
4849 10:01:33.350827 10, 0x0, sum = 3
4850 10:01:33.353612 11, 0x0, sum = 4
4851 10:01:33.354083 best_step = 9
4852 10:01:33.354452
4853 10:01:33.354789 ==
4854 10:01:33.357551 Dram Type= 6, Freq= 0, CH_1, rank 1
4855 10:01:33.360464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4856 10:01:33.361097 ==
4857 10:01:33.363910 RX Vref Scan: 0
4858 10:01:33.364468
4859 10:01:33.366745 RX Vref 0 -> 0, step: 1
4860 10:01:33.367212
4861 10:01:33.370355 RX Delay -195 -> 252, step: 8
4862 10:01:33.373993 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4863 10:01:33.377038 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4864 10:01:33.383406 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4865 10:01:33.386598 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4866 10:01:33.389624 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4867 10:01:33.394198 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4868 10:01:33.399677 iDelay=213, Bit 6, Center 56 (-99 ~ 212) 312
4869 10:01:33.403281 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4870 10:01:33.406344 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4871 10:01:33.409314 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4872 10:01:33.415897 iDelay=213, Bit 10, Center 36 (-115 ~ 188) 304
4873 10:01:33.419500 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4874 10:01:33.422707 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4875 10:01:33.425798 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4876 10:01:33.432735 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4877 10:01:33.436310 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4878 10:01:33.436777 ==
4879 10:01:33.439116 Dram Type= 6, Freq= 0, CH_1, rank 1
4880 10:01:33.443072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4881 10:01:33.443489 ==
4882 10:01:33.443821 DQS Delay:
4883 10:01:33.446152 DQS0 = 0, DQS1 = 0
4884 10:01:33.446567 DQM Delay:
4885 10:01:33.449194 DQM0 = 45, DQM1 = 37
4886 10:01:33.449641 DQ Delay:
4887 10:01:33.452581 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4888 10:01:33.455819 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4889 10:01:33.459671 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4890 10:01:33.462169 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4891 10:01:33.462587
4892 10:01:33.462916
4893 10:01:33.472467 [DQSOSCAuto] RK1, (LSB)MR18= 0x3529, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 399 ps
4894 10:01:33.472890 CH1 RK1: MR19=808, MR18=3529
4895 10:01:33.479213 CH1_RK1: MR19=0x808, MR18=0x3529, DQSOSC=399, MR23=63, INC=164, DEC=109
4896 10:01:33.482275 [RxdqsGatingPostProcess] freq 600
4897 10:01:33.488890 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4898 10:01:33.492441 Pre-setting of DQS Precalculation
4899 10:01:33.495892 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4900 10:01:33.501856 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4901 10:01:33.512036 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4902 10:01:33.512460
4903 10:01:33.512789
4904 10:01:33.515244 [Calibration Summary] 1200 Mbps
4905 10:01:33.515667 CH 0, Rank 0
4906 10:01:33.518775 SW Impedance : PASS
4907 10:01:33.519195 DUTY Scan : NO K
4908 10:01:33.522152 ZQ Calibration : PASS
4909 10:01:33.525152 Jitter Meter : NO K
4910 10:01:33.525616 CBT Training : PASS
4911 10:01:33.528804 Write leveling : PASS
4912 10:01:33.529222 RX DQS gating : PASS
4913 10:01:33.532020 RX DQ/DQS(RDDQC) : PASS
4914 10:01:33.535776 TX DQ/DQS : PASS
4915 10:01:33.536198 RX DATLAT : PASS
4916 10:01:33.538463 RX DQ/DQS(Engine): PASS
4917 10:01:33.541958 TX OE : NO K
4918 10:01:33.542379 All Pass.
4919 10:01:33.542733
4920 10:01:33.543077 CH 0, Rank 1
4921 10:01:33.544793 SW Impedance : PASS
4922 10:01:33.548352 DUTY Scan : NO K
4923 10:01:33.548769 ZQ Calibration : PASS
4924 10:01:33.551749 Jitter Meter : NO K
4925 10:01:33.554877 CBT Training : PASS
4926 10:01:33.555296 Write leveling : PASS
4927 10:01:33.558272 RX DQS gating : PASS
4928 10:01:33.561825 RX DQ/DQS(RDDQC) : PASS
4929 10:01:33.562242 TX DQ/DQS : PASS
4930 10:01:33.564563 RX DATLAT : PASS
4931 10:01:33.567795 RX DQ/DQS(Engine): PASS
4932 10:01:33.568215 TX OE : NO K
4933 10:01:33.571561 All Pass.
4934 10:01:33.572038
4935 10:01:33.572379 CH 1, Rank 0
4936 10:01:33.574697 SW Impedance : PASS
4937 10:01:33.575237 DUTY Scan : NO K
4938 10:01:33.577863 ZQ Calibration : PASS
4939 10:01:33.581094 Jitter Meter : NO K
4940 10:01:33.581556 CBT Training : PASS
4941 10:01:33.584748 Write leveling : PASS
4942 10:01:33.587532 RX DQS gating : PASS
4943 10:01:33.587952 RX DQ/DQS(RDDQC) : PASS
4944 10:01:33.591169 TX DQ/DQS : PASS
4945 10:01:33.594481 RX DATLAT : PASS
4946 10:01:33.594900 RX DQ/DQS(Engine): PASS
4947 10:01:33.597613 TX OE : NO K
4948 10:01:33.598033 All Pass.
4949 10:01:33.598367
4950 10:01:33.601247 CH 1, Rank 1
4951 10:01:33.601710 SW Impedance : PASS
4952 10:01:33.604783 DUTY Scan : NO K
4953 10:01:33.607483 ZQ Calibration : PASS
4954 10:01:33.607903 Jitter Meter : NO K
4955 10:01:33.610611 CBT Training : PASS
4956 10:01:33.614222 Write leveling : PASS
4957 10:01:33.614674 RX DQS gating : PASS
4958 10:01:33.617891 RX DQ/DQS(RDDQC) : PASS
4959 10:01:33.618339 TX DQ/DQS : PASS
4960 10:01:33.620572 RX DATLAT : PASS
4961 10:01:33.624324 RX DQ/DQS(Engine): PASS
4962 10:01:33.624778 TX OE : NO K
4963 10:01:33.627313 All Pass.
4964 10:01:33.627789
4965 10:01:33.628269 DramC Write-DBI off
4966 10:01:33.630780 PER_BANK_REFRESH: Hybrid Mode
4967 10:01:33.634266 TX_TRACKING: ON
4968 10:01:33.640292 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4969 10:01:33.643784 [FAST_K] Save calibration result to emmc
4970 10:01:33.647032 dramc_set_vcore_voltage set vcore to 662500
4971 10:01:33.650173 Read voltage for 933, 3
4972 10:01:33.650597 Vio18 = 0
4973 10:01:33.653748 Vcore = 662500
4974 10:01:33.654229 Vdram = 0
4975 10:01:33.654698 Vddq = 0
4976 10:01:33.656914 Vmddr = 0
4977 10:01:33.660438 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4978 10:01:33.666710 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4979 10:01:33.670204 MEM_TYPE=3, freq_sel=17
4980 10:01:33.670625 sv_algorithm_assistance_LP4_1600
4981 10:01:33.677083 ============ PULL DRAM RESETB DOWN ============
4982 10:01:33.679683 ========== PULL DRAM RESETB DOWN end =========
4983 10:01:33.683318 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4984 10:01:33.686831 ===================================
4985 10:01:33.690008 LPDDR4 DRAM CONFIGURATION
4986 10:01:33.694333 ===================================
4987 10:01:33.697107 EX_ROW_EN[0] = 0x0
4988 10:01:33.697568 EX_ROW_EN[1] = 0x0
4989 10:01:33.699814 LP4Y_EN = 0x0
4990 10:01:33.700234 WORK_FSP = 0x0
4991 10:01:33.703657 WL = 0x3
4992 10:01:33.704077 RL = 0x3
4993 10:01:33.706431 BL = 0x2
4994 10:01:33.706850 RPST = 0x0
4995 10:01:33.709537 RD_PRE = 0x0
4996 10:01:33.709958 WR_PRE = 0x1
4997 10:01:33.712825 WR_PST = 0x0
4998 10:01:33.716134 DBI_WR = 0x0
4999 10:01:33.716546 DBI_RD = 0x0
5000 10:01:33.719865 OTF = 0x1
5001 10:01:33.722996 ===================================
5002 10:01:33.726471 ===================================
5003 10:01:33.726882 ANA top config
5004 10:01:33.729791 ===================================
5005 10:01:33.732906 DLL_ASYNC_EN = 0
5006 10:01:33.735906 ALL_SLAVE_EN = 1
5007 10:01:33.736326 NEW_RANK_MODE = 1
5008 10:01:33.739203 DLL_IDLE_MODE = 1
5009 10:01:33.742775 LP45_APHY_COMB_EN = 1
5010 10:01:33.745958 TX_ODT_DIS = 1
5011 10:01:33.746384 NEW_8X_MODE = 1
5012 10:01:33.749267 ===================================
5013 10:01:33.752516 ===================================
5014 10:01:33.756057 data_rate = 1866
5015 10:01:33.759555 CKR = 1
5016 10:01:33.762470 DQ_P2S_RATIO = 8
5017 10:01:33.765775 ===================================
5018 10:01:33.769467 CA_P2S_RATIO = 8
5019 10:01:33.772298 DQ_CA_OPEN = 0
5020 10:01:33.772721 DQ_SEMI_OPEN = 0
5021 10:01:33.775843 CA_SEMI_OPEN = 0
5022 10:01:33.778734 CA_FULL_RATE = 0
5023 10:01:33.783053 DQ_CKDIV4_EN = 1
5024 10:01:33.785395 CA_CKDIV4_EN = 1
5025 10:01:33.788508 CA_PREDIV_EN = 0
5026 10:01:33.788590 PH8_DLY = 0
5027 10:01:33.792386 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5028 10:01:33.795736 DQ_AAMCK_DIV = 4
5029 10:01:33.798994 CA_AAMCK_DIV = 4
5030 10:01:33.801914 CA_ADMCK_DIV = 4
5031 10:01:33.805477 DQ_TRACK_CA_EN = 0
5032 10:01:33.808551 CA_PICK = 933
5033 10:01:33.808632 CA_MCKIO = 933
5034 10:01:33.812170 MCKIO_SEMI = 0
5035 10:01:33.814941 PLL_FREQ = 3732
5036 10:01:33.818036 DQ_UI_PI_RATIO = 32
5037 10:01:33.821451 CA_UI_PI_RATIO = 0
5038 10:01:33.824992 ===================================
5039 10:01:33.828305 ===================================
5040 10:01:33.831515 memory_type:LPDDR4
5041 10:01:33.831596 GP_NUM : 10
5042 10:01:33.834606 SRAM_EN : 1
5043 10:01:33.834688 MD32_EN : 0
5044 10:01:33.837957 ===================================
5045 10:01:33.841480 [ANA_INIT] >>>>>>>>>>>>>>
5046 10:01:33.844663 <<<<<< [CONFIGURE PHASE]: ANA_TX
5047 10:01:33.848681 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5048 10:01:33.851182 ===================================
5049 10:01:33.854786 data_rate = 1866,PCW = 0X8f00
5050 10:01:33.858239 ===================================
5051 10:01:33.861060 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5052 10:01:33.867902 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5053 10:01:33.870770 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5054 10:01:33.877628 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5055 10:01:33.881180 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5056 10:01:33.884225 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5057 10:01:33.884306 [ANA_INIT] flow start
5058 10:01:33.887970 [ANA_INIT] PLL >>>>>>>>
5059 10:01:33.890763 [ANA_INIT] PLL <<<<<<<<
5060 10:01:33.890843 [ANA_INIT] MIDPI >>>>>>>>
5061 10:01:33.893987 [ANA_INIT] MIDPI <<<<<<<<
5062 10:01:33.897300 [ANA_INIT] DLL >>>>>>>>
5063 10:01:33.897380 [ANA_INIT] flow end
5064 10:01:33.903881 ============ LP4 DIFF to SE enter ============
5065 10:01:33.907486 ============ LP4 DIFF to SE exit ============
5066 10:01:33.910703 [ANA_INIT] <<<<<<<<<<<<<
5067 10:01:33.914346 [Flow] Enable top DCM control >>>>>
5068 10:01:33.917763 [Flow] Enable top DCM control <<<<<
5069 10:01:33.920700 Enable DLL master slave shuffle
5070 10:01:33.923752 ==============================================================
5071 10:01:33.927545 Gating Mode config
5072 10:01:33.930558 ==============================================================
5073 10:01:33.933858 Config description:
5074 10:01:33.943484 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5075 10:01:33.950499 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5076 10:01:33.954352 SELPH_MODE 0: By rank 1: By Phase
5077 10:01:33.959983 ==============================================================
5078 10:01:33.963489 GAT_TRACK_EN = 1
5079 10:01:33.966616 RX_GATING_MODE = 2
5080 10:01:33.970039 RX_GATING_TRACK_MODE = 2
5081 10:01:33.973863 SELPH_MODE = 1
5082 10:01:33.976387 PICG_EARLY_EN = 1
5083 10:01:33.979637 VALID_LAT_VALUE = 1
5084 10:01:33.983378 ==============================================================
5085 10:01:33.986638 Enter into Gating configuration >>>>
5086 10:01:33.990207 Exit from Gating configuration <<<<
5087 10:01:33.993127 Enter into DVFS_PRE_config >>>>>
5088 10:01:34.006390 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5089 10:01:34.009902 Exit from DVFS_PRE_config <<<<<
5090 10:01:34.009983 Enter into PICG configuration >>>>
5091 10:01:34.012921 Exit from PICG configuration <<<<
5092 10:01:34.016574 [RX_INPUT] configuration >>>>>
5093 10:01:34.019322 [RX_INPUT] configuration <<<<<
5094 10:01:34.026186 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5095 10:01:34.029381 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5096 10:01:34.035976 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5097 10:01:34.043348 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5098 10:01:34.049270 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5099 10:01:34.055723 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5100 10:01:34.059401 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5101 10:01:34.062290 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5102 10:01:34.068848 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5103 10:01:34.072150 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5104 10:01:34.075493 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5105 10:01:34.078879 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5106 10:01:34.081646 ===================================
5107 10:01:34.085571 LPDDR4 DRAM CONFIGURATION
5108 10:01:34.088593 ===================================
5109 10:01:34.092003 EX_ROW_EN[0] = 0x0
5110 10:01:34.092084 EX_ROW_EN[1] = 0x0
5111 10:01:34.095069 LP4Y_EN = 0x0
5112 10:01:34.095149 WORK_FSP = 0x0
5113 10:01:34.098284 WL = 0x3
5114 10:01:34.098364 RL = 0x3
5115 10:01:34.101630 BL = 0x2
5116 10:01:34.101710 RPST = 0x0
5117 10:01:34.105167 RD_PRE = 0x0
5118 10:01:34.105247 WR_PRE = 0x1
5119 10:01:34.108299 WR_PST = 0x0
5120 10:01:34.111765 DBI_WR = 0x0
5121 10:01:34.111845 DBI_RD = 0x0
5122 10:01:34.115290 OTF = 0x1
5123 10:01:34.118439 ===================================
5124 10:01:34.121291 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5125 10:01:34.125307 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5126 10:01:34.127975 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5127 10:01:34.131300 ===================================
5128 10:01:34.134643 LPDDR4 DRAM CONFIGURATION
5129 10:01:34.137913 ===================================
5130 10:01:34.141228 EX_ROW_EN[0] = 0x10
5131 10:01:34.141336 EX_ROW_EN[1] = 0x0
5132 10:01:34.145042 LP4Y_EN = 0x0
5133 10:01:34.145126 WORK_FSP = 0x0
5134 10:01:34.147984 WL = 0x3
5135 10:01:34.148065 RL = 0x3
5136 10:01:34.151408 BL = 0x2
5137 10:01:34.151489 RPST = 0x0
5138 10:01:34.154473 RD_PRE = 0x0
5139 10:01:34.154552 WR_PRE = 0x1
5140 10:01:34.158011 WR_PST = 0x0
5141 10:01:34.161598 DBI_WR = 0x0
5142 10:01:34.161679 DBI_RD = 0x0
5143 10:01:34.164468 OTF = 0x1
5144 10:01:34.168043 ===================================
5145 10:01:34.171375 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5146 10:01:34.176355 nWR fixed to 30
5147 10:01:34.179916 [ModeRegInit_LP4] CH0 RK0
5148 10:01:34.179997 [ModeRegInit_LP4] CH0 RK1
5149 10:01:34.182804 [ModeRegInit_LP4] CH1 RK0
5150 10:01:34.186383 [ModeRegInit_LP4] CH1 RK1
5151 10:01:34.186465 match AC timing 9
5152 10:01:34.193024 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5153 10:01:34.195996 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5154 10:01:34.199626 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5155 10:01:34.206282 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5156 10:01:34.209029 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5157 10:01:34.209111 ==
5158 10:01:34.212694 Dram Type= 6, Freq= 0, CH_0, rank 0
5159 10:01:34.215932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5160 10:01:34.216013 ==
5161 10:01:34.222413 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5162 10:01:34.229150 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5163 10:01:34.232192 [CA 0] Center 37 (7~68) winsize 62
5164 10:01:34.235575 [CA 1] Center 37 (7~68) winsize 62
5165 10:01:34.238762 [CA 2] Center 34 (4~65) winsize 62
5166 10:01:34.242339 [CA 3] Center 34 (4~65) winsize 62
5167 10:01:34.245455 [CA 4] Center 33 (3~64) winsize 62
5168 10:01:34.248637 [CA 5] Center 33 (4~63) winsize 60
5169 10:01:34.248717
5170 10:01:34.252117 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5171 10:01:34.252199
5172 10:01:34.255685 [CATrainingPosCal] consider 1 rank data
5173 10:01:34.258838 u2DelayCellTimex100 = 270/100 ps
5174 10:01:34.261872 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5175 10:01:34.265751 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5176 10:01:34.268571 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5177 10:01:34.275195 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5178 10:01:34.278548 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5179 10:01:34.281798 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5180 10:01:34.281881
5181 10:01:34.284882 CA PerBit enable=1, Macro0, CA PI delay=33
5182 10:01:34.284963
5183 10:01:34.288346 [CBTSetCACLKResult] CA Dly = 33
5184 10:01:34.288427 CS Dly: 7 (0~38)
5185 10:01:34.288493 ==
5186 10:01:34.291580 Dram Type= 6, Freq= 0, CH_0, rank 1
5187 10:01:34.298373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5188 10:01:34.298455 ==
5189 10:01:34.301542 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5190 10:01:34.308134 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5191 10:01:34.311506 [CA 0] Center 37 (7~68) winsize 62
5192 10:01:34.315180 [CA 1] Center 37 (7~68) winsize 62
5193 10:01:34.318586 [CA 2] Center 34 (4~65) winsize 62
5194 10:01:34.321956 [CA 3] Center 34 (4~65) winsize 62
5195 10:01:34.324780 [CA 4] Center 33 (3~64) winsize 62
5196 10:01:34.328117 [CA 5] Center 33 (3~63) winsize 61
5197 10:01:34.328238
5198 10:01:34.331478 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5199 10:01:34.331613
5200 10:01:34.334872 [CATrainingPosCal] consider 2 rank data
5201 10:01:34.338601 u2DelayCellTimex100 = 270/100 ps
5202 10:01:34.341389 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5203 10:01:34.345481 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5204 10:01:34.352272 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5205 10:01:34.355155 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5206 10:01:34.358304 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5207 10:01:34.361684 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5208 10:01:34.362069
5209 10:01:34.364963 CA PerBit enable=1, Macro0, CA PI delay=33
5210 10:01:34.365355
5211 10:01:34.368498 [CBTSetCACLKResult] CA Dly = 33
5212 10:01:34.369071 CS Dly: 7 (0~39)
5213 10:01:34.369474
5214 10:01:34.371440 ----->DramcWriteLeveling(PI) begin...
5215 10:01:34.374819 ==
5216 10:01:34.378383 Dram Type= 6, Freq= 0, CH_0, rank 0
5217 10:01:34.381516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5218 10:01:34.381930 ==
5219 10:01:34.384914 Write leveling (Byte 0): 30 => 30
5220 10:01:34.388083 Write leveling (Byte 1): 29 => 29
5221 10:01:34.391609 DramcWriteLeveling(PI) end<-----
5222 10:01:34.392021
5223 10:01:34.392396 ==
5224 10:01:34.394860 Dram Type= 6, Freq= 0, CH_0, rank 0
5225 10:01:34.398137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5226 10:01:34.398552 ==
5227 10:01:34.401280 [Gating] SW mode calibration
5228 10:01:34.408208 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5229 10:01:34.414388 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5230 10:01:34.417815 0 14 0 | B1->B0 | 2424 3434 | 1 1 | (0 0) (1 1)
5231 10:01:34.421493 0 14 4 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
5232 10:01:34.428171 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5233 10:01:34.431228 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5234 10:01:34.434412 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5235 10:01:34.441087 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5236 10:01:34.444263 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5237 10:01:34.447860 0 14 28 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
5238 10:01:34.454286 0 15 0 | B1->B0 | 3131 2525 | 0 0 | (0 1) (0 0)
5239 10:01:34.457780 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5240 10:01:34.460598 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5241 10:01:34.467155 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5242 10:01:34.470709 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5243 10:01:34.473882 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5244 10:01:34.480295 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5245 10:01:34.484017 0 15 28 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5246 10:01:34.486840 1 0 0 | B1->B0 | 3232 4545 | 0 0 | (0 0) (0 0)
5247 10:01:34.493899 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5248 10:01:34.497227 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5249 10:01:34.500389 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5250 10:01:34.506748 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5251 10:01:34.509939 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5252 10:01:34.513082 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5253 10:01:34.519907 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5254 10:01:34.523500 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5255 10:01:34.527108 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5256 10:01:34.533008 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5257 10:01:34.536001 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5258 10:01:34.539924 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5259 10:01:34.546570 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5260 10:01:34.549619 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5261 10:01:34.553116 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5262 10:01:34.559999 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5263 10:01:34.562748 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5264 10:01:34.566290 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5265 10:01:34.572444 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5266 10:01:34.575801 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5267 10:01:34.579062 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5268 10:01:34.585934 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5269 10:01:34.589259 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5270 10:01:34.592741 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5271 10:01:34.595394 Total UI for P1: 0, mck2ui 16
5272 10:01:34.598950 best dqsien dly found for B0: ( 1, 2, 28)
5273 10:01:34.605328 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5274 10:01:34.605777 Total UI for P1: 0, mck2ui 16
5275 10:01:34.612273 best dqsien dly found for B1: ( 1, 3, 0)
5276 10:01:34.615438 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5277 10:01:34.618353 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5278 10:01:34.618810
5279 10:01:34.622134 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5280 10:01:34.625208 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5281 10:01:34.628657 [Gating] SW calibration Done
5282 10:01:34.629068 ==
5283 10:01:34.631639 Dram Type= 6, Freq= 0, CH_0, rank 0
5284 10:01:34.635432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 10:01:34.635846 ==
5286 10:01:34.638340 RX Vref Scan: 0
5287 10:01:34.638749
5288 10:01:34.639073 RX Vref 0 -> 0, step: 1
5289 10:01:34.639379
5290 10:01:34.641528 RX Delay -80 -> 252, step: 8
5291 10:01:34.645513 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5292 10:01:34.651562 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5293 10:01:34.655290 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5294 10:01:34.657941 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5295 10:01:34.661479 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5296 10:01:34.664873 iDelay=208, Bit 5, Center 87 (-16 ~ 191) 208
5297 10:01:34.668693 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5298 10:01:34.675306 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5299 10:01:34.678392 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5300 10:01:34.681490 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5301 10:01:34.685042 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5302 10:01:34.691791 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5303 10:01:34.694339 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5304 10:01:34.697993 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5305 10:01:34.701453 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5306 10:01:34.704257 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5307 10:01:34.704807 ==
5308 10:01:34.707729 Dram Type= 6, Freq= 0, CH_0, rank 0
5309 10:01:34.714027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5310 10:01:34.714109 ==
5311 10:01:34.714173 DQS Delay:
5312 10:01:34.717557 DQS0 = 0, DQS1 = 0
5313 10:01:34.717966 DQM Delay:
5314 10:01:34.718293 DQM0 = 97, DQM1 = 85
5315 10:01:34.721504 DQ Delay:
5316 10:01:34.725091 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5317 10:01:34.727779 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5318 10:01:34.731228 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5319 10:01:34.734142 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5320 10:01:34.734556
5321 10:01:34.734883
5322 10:01:34.735189 ==
5323 10:01:34.737354 Dram Type= 6, Freq= 0, CH_0, rank 0
5324 10:01:34.740895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5325 10:01:34.741306 ==
5326 10:01:34.741686
5327 10:01:34.741996
5328 10:01:34.744253 TX Vref Scan disable
5329 10:01:34.747750 == TX Byte 0 ==
5330 10:01:34.750653 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5331 10:01:34.754233 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5332 10:01:34.757006 == TX Byte 1 ==
5333 10:01:34.760612 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5334 10:01:34.763924 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5335 10:01:34.764348 ==
5336 10:01:34.767370 Dram Type= 6, Freq= 0, CH_0, rank 0
5337 10:01:34.773341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5338 10:01:34.773808 ==
5339 10:01:34.774140
5340 10:01:34.774447
5341 10:01:34.774745 TX Vref Scan disable
5342 10:01:34.777538 == TX Byte 0 ==
5343 10:01:34.780900 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5344 10:01:34.787432 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5345 10:01:34.787855 == TX Byte 1 ==
5346 10:01:34.790382 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5347 10:01:34.797519 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5348 10:01:34.797941
5349 10:01:34.798276 [DATLAT]
5350 10:01:34.798584 Freq=933, CH0 RK0
5351 10:01:34.798887
5352 10:01:34.800470 DATLAT Default: 0xd
5353 10:01:34.800885 0, 0xFFFF, sum = 0
5354 10:01:34.803706 1, 0xFFFF, sum = 0
5355 10:01:34.807032 2, 0xFFFF, sum = 0
5356 10:01:34.807527 3, 0xFFFF, sum = 0
5357 10:01:34.810354 4, 0xFFFF, sum = 0
5358 10:01:34.810781 5, 0xFFFF, sum = 0
5359 10:01:34.814154 6, 0xFFFF, sum = 0
5360 10:01:34.814579 7, 0xFFFF, sum = 0
5361 10:01:34.816798 8, 0xFFFF, sum = 0
5362 10:01:34.817315 9, 0xFFFF, sum = 0
5363 10:01:34.819958 10, 0x0, sum = 1
5364 10:01:34.820383 11, 0x0, sum = 2
5365 10:01:34.823233 12, 0x0, sum = 3
5366 10:01:34.823653 13, 0x0, sum = 4
5367 10:01:34.827111 best_step = 11
5368 10:01:34.827524
5369 10:01:34.827846 ==
5370 10:01:34.829944 Dram Type= 6, Freq= 0, CH_0, rank 0
5371 10:01:34.833816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5372 10:01:34.834131 ==
5373 10:01:34.834375 RX Vref Scan: 1
5374 10:01:34.834599
5375 10:01:34.836678 RX Vref 0 -> 0, step: 1
5376 10:01:34.836901
5377 10:01:34.840221 RX Delay -61 -> 252, step: 4
5378 10:01:34.840445
5379 10:01:34.843177 Set Vref, RX VrefLevel [Byte0]: 60
5380 10:01:34.846624 [Byte1]: 48
5381 10:01:34.846704
5382 10:01:34.850240 Final RX Vref Byte 0 = 60 to rank0
5383 10:01:34.853054 Final RX Vref Byte 1 = 48 to rank0
5384 10:01:34.856433 Final RX Vref Byte 0 = 60 to rank1
5385 10:01:34.859430 Final RX Vref Byte 1 = 48 to rank1==
5386 10:01:34.862783 Dram Type= 6, Freq= 0, CH_0, rank 0
5387 10:01:34.869568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5388 10:01:34.869649 ==
5389 10:01:34.869712 DQS Delay:
5390 10:01:34.869772 DQS0 = 0, DQS1 = 0
5391 10:01:34.872879 DQM Delay:
5392 10:01:34.872959 DQM0 = 97, DQM1 = 85
5393 10:01:34.876065 DQ Delay:
5394 10:01:34.879478 DQ0 =94, DQ1 =100, DQ2 =94, DQ3 =92
5395 10:01:34.883277 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =106
5396 10:01:34.886268 DQ8 =76, DQ9 =74, DQ10 =86, DQ11 =80
5397 10:01:34.889545 DQ12 =90, DQ13 =88, DQ14 =94, DQ15 =94
5398 10:01:34.889626
5399 10:01:34.889689
5400 10:01:34.895898 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f16, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 407 ps
5401 10:01:34.899139 CH0 RK0: MR19=505, MR18=2F16
5402 10:01:34.905825 CH0_RK0: MR19=0x505, MR18=0x2F16, DQSOSC=407, MR23=63, INC=65, DEC=43
5403 10:01:34.905908
5404 10:01:34.909018 ----->DramcWriteLeveling(PI) begin...
5405 10:01:34.909099 ==
5406 10:01:34.912094 Dram Type= 6, Freq= 0, CH_0, rank 1
5407 10:01:34.915606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5408 10:01:34.915687 ==
5409 10:01:34.918795 Write leveling (Byte 0): 36 => 36
5410 10:01:34.922325 Write leveling (Byte 1): 33 => 33
5411 10:01:34.925857 DramcWriteLeveling(PI) end<-----
5412 10:01:34.925938
5413 10:01:34.926001 ==
5414 10:01:34.929058 Dram Type= 6, Freq= 0, CH_0, rank 1
5415 10:01:34.932331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5416 10:01:34.935716 ==
5417 10:01:34.935796 [Gating] SW mode calibration
5418 10:01:34.945268 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5419 10:01:34.948396 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5420 10:01:34.952301 0 14 0 | B1->B0 | 2626 3030 | 1 1 | (1 1) (1 1)
5421 10:01:34.959103 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5422 10:01:34.961755 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5423 10:01:34.965154 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5424 10:01:34.972098 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5425 10:01:34.975079 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5426 10:01:34.978436 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5427 10:01:34.985629 0 14 28 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
5428 10:01:34.988594 0 15 0 | B1->B0 | 2e2e 2424 | 0 0 | (1 0) (0 0)
5429 10:01:34.991278 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5430 10:01:34.998223 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5431 10:01:35.001108 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5432 10:01:35.004438 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5433 10:01:35.011074 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5434 10:01:35.014359 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5435 10:01:35.017480 0 15 28 | B1->B0 | 2828 3636 | 0 0 | (0 0) (0 0)
5436 10:01:35.024491 1 0 0 | B1->B0 | 3c3c 4242 | 0 0 | (0 0) (0 0)
5437 10:01:35.028291 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5438 10:01:35.030937 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5439 10:01:35.037594 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5440 10:01:35.040726 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5441 10:01:35.043844 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5442 10:01:35.050612 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5443 10:01:35.054553 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5444 10:01:35.060163 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5445 10:01:35.063877 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5446 10:01:35.067020 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5447 10:01:35.070304 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5448 10:01:35.076663 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5449 10:01:35.080613 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5450 10:01:35.083392 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5451 10:01:35.090136 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5452 10:01:35.093314 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5453 10:01:35.096531 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5454 10:01:35.103813 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5455 10:01:35.106654 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5456 10:01:35.110524 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5457 10:01:35.116825 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5458 10:01:35.120216 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5459 10:01:35.123468 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5460 10:01:35.130038 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5461 10:01:35.133448 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5462 10:01:35.137031 Total UI for P1: 0, mck2ui 16
5463 10:01:35.140031 best dqsien dly found for B0: ( 1, 2, 30)
5464 10:01:35.142946 Total UI for P1: 0, mck2ui 16
5465 10:01:35.146374 best dqsien dly found for B1: ( 1, 3, 0)
5466 10:01:35.150243 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5467 10:01:35.153273 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5468 10:01:35.153381
5469 10:01:35.155889 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5470 10:01:35.159878 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5471 10:01:35.162735 [Gating] SW calibration Done
5472 10:01:35.162817 ==
5473 10:01:35.165983 Dram Type= 6, Freq= 0, CH_0, rank 1
5474 10:01:35.172501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5475 10:01:35.172583 ==
5476 10:01:35.172648 RX Vref Scan: 0
5477 10:01:35.172709
5478 10:01:35.175768 RX Vref 0 -> 0, step: 1
5479 10:01:35.175849
5480 10:01:35.179100 RX Delay -80 -> 252, step: 8
5481 10:01:35.182843 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5482 10:01:35.186269 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5483 10:01:35.189417 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5484 10:01:35.192323 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5485 10:01:35.199084 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5486 10:01:35.202092 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5487 10:01:35.205533 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5488 10:01:35.209635 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5489 10:01:35.212115 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5490 10:01:35.218580 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5491 10:01:35.222168 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5492 10:01:35.225310 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5493 10:01:35.228900 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5494 10:01:35.231936 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5495 10:01:35.238442 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5496 10:01:35.241769 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5497 10:01:35.241849 ==
5498 10:01:35.245220 Dram Type= 6, Freq= 0, CH_0, rank 1
5499 10:01:35.248348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5500 10:01:35.248430 ==
5501 10:01:35.251576 DQS Delay:
5502 10:01:35.251655 DQS0 = 0, DQS1 = 0
5503 10:01:35.251719 DQM Delay:
5504 10:01:35.255133 DQM0 = 96, DQM1 = 87
5505 10:01:35.255214 DQ Delay:
5506 10:01:35.258436 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5507 10:01:35.261843 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5508 10:01:35.264994 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5509 10:01:35.268318 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5510 10:01:35.268398
5511 10:01:35.268461
5512 10:01:35.268520 ==
5513 10:01:35.271631 Dram Type= 6, Freq= 0, CH_0, rank 1
5514 10:01:35.278315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5515 10:01:35.278395 ==
5516 10:01:35.278458
5517 10:01:35.278516
5518 10:01:35.278573 TX Vref Scan disable
5519 10:01:35.281630 == TX Byte 0 ==
5520 10:01:35.285220 Update DQ dly =720 (2 ,6, 16) DQ OEN =(2 ,3)
5521 10:01:35.291731 Update DQM dly =720 (2 ,6, 16) DQM OEN =(2 ,3)
5522 10:01:35.291812 == TX Byte 1 ==
5523 10:01:35.294614 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5524 10:01:35.301634 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5525 10:01:35.301717 ==
5526 10:01:35.304720 Dram Type= 6, Freq= 0, CH_0, rank 1
5527 10:01:35.307902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5528 10:01:35.307984 ==
5529 10:01:35.308048
5530 10:01:35.308106
5531 10:01:35.311370 TX Vref Scan disable
5532 10:01:35.311450 == TX Byte 0 ==
5533 10:01:35.318002 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5534 10:01:35.321107 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5535 10:01:35.324607 == TX Byte 1 ==
5536 10:01:35.327560 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5537 10:01:35.330773 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5538 10:01:35.330854
5539 10:01:35.330917 [DATLAT]
5540 10:01:35.334167 Freq=933, CH0 RK1
5541 10:01:35.334247
5542 10:01:35.337482 DATLAT Default: 0xb
5543 10:01:35.337561 0, 0xFFFF, sum = 0
5544 10:01:35.340896 1, 0xFFFF, sum = 0
5545 10:01:35.340978 2, 0xFFFF, sum = 0
5546 10:01:35.344279 3, 0xFFFF, sum = 0
5547 10:01:35.344361 4, 0xFFFF, sum = 0
5548 10:01:35.347614 5, 0xFFFF, sum = 0
5549 10:01:35.347695 6, 0xFFFF, sum = 0
5550 10:01:35.351016 7, 0xFFFF, sum = 0
5551 10:01:35.351098 8, 0xFFFF, sum = 0
5552 10:01:35.354013 9, 0xFFFF, sum = 0
5553 10:01:35.354094 10, 0x0, sum = 1
5554 10:01:35.358089 11, 0x0, sum = 2
5555 10:01:35.358170 12, 0x0, sum = 3
5556 10:01:35.360772 13, 0x0, sum = 4
5557 10:01:35.360853 best_step = 11
5558 10:01:35.360915
5559 10:01:35.360973 ==
5560 10:01:35.364390 Dram Type= 6, Freq= 0, CH_0, rank 1
5561 10:01:35.367927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5562 10:01:35.368007 ==
5563 10:01:35.371222 RX Vref Scan: 0
5564 10:01:35.371301
5565 10:01:35.374451 RX Vref 0 -> 0, step: 1
5566 10:01:35.374531
5567 10:01:35.374594 RX Delay -61 -> 252, step: 4
5568 10:01:35.381897 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5569 10:01:35.385925 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5570 10:01:35.389437 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5571 10:01:35.392255 iDelay=203, Bit 3, Center 92 (-5 ~ 190) 196
5572 10:01:35.395280 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5573 10:01:35.398568 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5574 10:01:35.405205 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5575 10:01:35.408742 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5576 10:01:35.412631 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5577 10:01:35.415142 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5578 10:01:35.418375 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5579 10:01:35.425120 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5580 10:01:35.428548 iDelay=203, Bit 12, Center 94 (3 ~ 186) 184
5581 10:01:35.431377 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5582 10:01:35.434687 iDelay=203, Bit 14, Center 94 (3 ~ 186) 184
5583 10:01:35.438505 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5584 10:01:35.441560 ==
5585 10:01:35.444694 Dram Type= 6, Freq= 0, CH_0, rank 1
5586 10:01:35.448238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5587 10:01:35.448319 ==
5588 10:01:35.448383 DQS Delay:
5589 10:01:35.451552 DQS0 = 0, DQS1 = 0
5590 10:01:35.451660 DQM Delay:
5591 10:01:35.454656 DQM0 = 95, DQM1 = 85
5592 10:01:35.454735 DQ Delay:
5593 10:01:35.457929 DQ0 =92, DQ1 =98, DQ2 =88, DQ3 =92
5594 10:01:35.461816 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5595 10:01:35.464863 DQ8 =76, DQ9 =74, DQ10 =86, DQ11 =78
5596 10:01:35.467929 DQ12 =94, DQ13 =92, DQ14 =94, DQ15 =92
5597 10:01:35.468009
5598 10:01:35.468070
5599 10:01:35.474385 [DQSOSCAuto] RK1, (LSB)MR18= 0x27f8, (MSB)MR19= 0x504, tDQSOscB0 = 424 ps tDQSOscB1 = 409 ps
5600 10:01:35.478319 CH0 RK1: MR19=504, MR18=27F8
5601 10:01:35.484706 CH0_RK1: MR19=0x504, MR18=0x27F8, DQSOSC=409, MR23=63, INC=64, DEC=43
5602 10:01:35.487538 [RxdqsGatingPostProcess] freq 933
5603 10:01:35.494541 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5604 10:01:35.497589 best DQS0 dly(2T, 0.5T) = (0, 10)
5605 10:01:35.497669 best DQS1 dly(2T, 0.5T) = (0, 11)
5606 10:01:35.501033 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5607 10:01:35.503858 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5608 10:01:35.507432 best DQS0 dly(2T, 0.5T) = (0, 10)
5609 10:01:35.510871 best DQS1 dly(2T, 0.5T) = (0, 11)
5610 10:01:35.513996 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5611 10:01:35.517793 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5612 10:01:35.520360 Pre-setting of DQS Precalculation
5613 10:01:35.527804 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5614 10:01:35.527885 ==
5615 10:01:35.530214 Dram Type= 6, Freq= 0, CH_1, rank 0
5616 10:01:35.533823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5617 10:01:35.533904 ==
5618 10:01:35.540412 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5619 10:01:35.546910 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5620 10:01:35.550082 [CA 0] Center 36 (6~67) winsize 62
5621 10:01:35.554076 [CA 1] Center 36 (6~67) winsize 62
5622 10:01:35.556753 [CA 2] Center 34 (4~64) winsize 61
5623 10:01:35.560099 [CA 3] Center 33 (3~64) winsize 62
5624 10:01:35.563420 [CA 4] Center 34 (4~64) winsize 61
5625 10:01:35.567305 [CA 5] Center 33 (3~64) winsize 62
5626 10:01:35.567386
5627 10:01:35.570755 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5628 10:01:35.570841
5629 10:01:35.573633 [CATrainingPosCal] consider 1 rank data
5630 10:01:35.576472 u2DelayCellTimex100 = 270/100 ps
5631 10:01:35.579863 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5632 10:01:35.583279 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5633 10:01:35.586560 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5634 10:01:35.590059 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5635 10:01:35.593118 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5636 10:01:35.596325 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5637 10:01:35.596405
5638 10:01:35.603531 CA PerBit enable=1, Macro0, CA PI delay=33
5639 10:01:35.603612
5640 10:01:35.603691 [CBTSetCACLKResult] CA Dly = 33
5641 10:01:35.606518 CS Dly: 6 (0~37)
5642 10:01:35.606597 ==
5643 10:01:35.609714 Dram Type= 6, Freq= 0, CH_1, rank 1
5644 10:01:35.613449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5645 10:01:35.613543 ==
5646 10:01:35.619366 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5647 10:01:35.626381 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5648 10:01:35.629991 [CA 0] Center 36 (6~67) winsize 62
5649 10:01:35.632677 [CA 1] Center 37 (7~67) winsize 61
5650 10:01:35.636100 [CA 2] Center 34 (3~65) winsize 63
5651 10:01:35.639152 [CA 3] Center 33 (3~64) winsize 62
5652 10:01:35.642906 [CA 4] Center 34 (3~65) winsize 63
5653 10:01:35.645886 [CA 5] Center 33 (3~64) winsize 62
5654 10:01:35.646002
5655 10:01:35.649006 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5656 10:01:35.649086
5657 10:01:35.652474 [CATrainingPosCal] consider 2 rank data
5658 10:01:35.655604 u2DelayCellTimex100 = 270/100 ps
5659 10:01:35.658990 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5660 10:01:35.662009 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5661 10:01:35.665453 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5662 10:01:35.668646 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5663 10:01:35.675626 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5664 10:01:35.678687 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5665 10:01:35.678770
5666 10:01:35.681909 CA PerBit enable=1, Macro0, CA PI delay=33
5667 10:01:35.681991
5668 10:01:35.685124 [CBTSetCACLKResult] CA Dly = 33
5669 10:01:35.685205 CS Dly: 7 (0~39)
5670 10:01:35.685270
5671 10:01:35.688470 ----->DramcWriteLeveling(PI) begin...
5672 10:01:35.688553 ==
5673 10:01:35.692427 Dram Type= 6, Freq= 0, CH_1, rank 0
5674 10:01:35.698612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5675 10:01:35.698695 ==
5676 10:01:35.702040 Write leveling (Byte 0): 23 => 23
5677 10:01:35.704996 Write leveling (Byte 1): 26 => 26
5678 10:01:35.705077 DramcWriteLeveling(PI) end<-----
5679 10:01:35.705142
5680 10:01:35.708582 ==
5681 10:01:35.712189 Dram Type= 6, Freq= 0, CH_1, rank 0
5682 10:01:35.714864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5683 10:01:35.714945 ==
5684 10:01:35.718131 [Gating] SW mode calibration
5685 10:01:35.725241 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5686 10:01:35.728108 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5687 10:01:35.735512 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5688 10:01:35.738727 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5689 10:01:35.741710 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5690 10:01:35.748418 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5691 10:01:35.751040 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5692 10:01:35.754719 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5693 10:01:35.761109 0 14 24 | B1->B0 | 3434 3333 | 0 0 | (0 1) (1 0)
5694 10:01:35.764741 0 14 28 | B1->B0 | 2d2d 2828 | 0 0 | (1 1) (0 0)
5695 10:01:35.768027 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5696 10:01:35.774981 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5697 10:01:35.777974 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5698 10:01:35.781018 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5699 10:01:35.787625 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5700 10:01:35.791252 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5701 10:01:35.794617 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5702 10:01:35.800755 0 15 28 | B1->B0 | 3535 3c3c | 0 0 | (0 0) (0 0)
5703 10:01:35.804001 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5704 10:01:35.807425 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5705 10:01:35.813647 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5706 10:01:35.816982 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5707 10:01:35.820515 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5708 10:01:35.827359 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5709 10:01:35.830417 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5710 10:01:35.833860 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5711 10:01:35.840531 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5712 10:01:35.843519 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5713 10:01:35.847565 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5714 10:01:35.853321 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5715 10:01:35.856802 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5716 10:01:35.859973 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5717 10:01:35.866766 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5718 10:01:35.869944 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5719 10:01:35.872997 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5720 10:01:35.879655 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5721 10:01:35.883318 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5722 10:01:35.886816 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5723 10:01:35.893302 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5724 10:01:35.896291 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5725 10:01:35.899421 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5726 10:01:35.906453 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5727 10:01:35.909340 Total UI for P1: 0, mck2ui 16
5728 10:01:35.913375 best dqsien dly found for B0: ( 1, 2, 24)
5729 10:01:35.916289 Total UI for P1: 0, mck2ui 16
5730 10:01:35.919295 best dqsien dly found for B1: ( 1, 2, 24)
5731 10:01:35.922534 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5732 10:01:35.926081 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5733 10:01:35.926163
5734 10:01:35.929162 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5735 10:01:35.932571 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5736 10:01:35.935973 [Gating] SW calibration Done
5737 10:01:35.936055 ==
5738 10:01:35.939394 Dram Type= 6, Freq= 0, CH_1, rank 0
5739 10:01:35.942936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 10:01:35.943019 ==
5741 10:01:35.945862 RX Vref Scan: 0
5742 10:01:35.945943
5743 10:01:35.949130 RX Vref 0 -> 0, step: 1
5744 10:01:35.949211
5745 10:01:35.949275 RX Delay -80 -> 252, step: 8
5746 10:01:35.955689 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5747 10:01:35.959481 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5748 10:01:35.962812 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5749 10:01:35.965746 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5750 10:01:35.969147 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5751 10:01:35.972148 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5752 10:01:35.979034 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5753 10:01:35.982107 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5754 10:01:35.985984 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5755 10:01:35.988897 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5756 10:01:35.992198 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5757 10:01:35.999201 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5758 10:01:36.002299 iDelay=208, Bit 12, Center 95 (-8 ~ 199) 208
5759 10:01:36.005220 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5760 10:01:36.008636 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5761 10:01:36.012363 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5762 10:01:36.012443 ==
5763 10:01:36.015068 Dram Type= 6, Freq= 0, CH_1, rank 0
5764 10:01:36.021696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5765 10:01:36.021777 ==
5766 10:01:36.021841 DQS Delay:
5767 10:01:36.025136 DQS0 = 0, DQS1 = 0
5768 10:01:36.025216 DQM Delay:
5769 10:01:36.025279 DQM0 = 102, DQM1 = 90
5770 10:01:36.028550 DQ Delay:
5771 10:01:36.031838 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =99
5772 10:01:36.034872 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5773 10:01:36.038340 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =83
5774 10:01:36.041858 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =99
5775 10:01:36.041938
5776 10:01:36.042001
5777 10:01:36.042058 ==
5778 10:01:36.044759 Dram Type= 6, Freq= 0, CH_1, rank 0
5779 10:01:36.048629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5780 10:01:36.048710 ==
5781 10:01:36.048773
5782 10:01:36.048831
5783 10:01:36.051607 TX Vref Scan disable
5784 10:01:36.055314 == TX Byte 0 ==
5785 10:01:36.058135 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5786 10:01:36.061851 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5787 10:01:36.064443 == TX Byte 1 ==
5788 10:01:36.067820 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5789 10:01:36.071499 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5790 10:01:36.071579 ==
5791 10:01:36.074567 Dram Type= 6, Freq= 0, CH_1, rank 0
5792 10:01:36.081231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5793 10:01:36.081312 ==
5794 10:01:36.081375
5795 10:01:36.081439
5796 10:01:36.081495 TX Vref Scan disable
5797 10:01:36.085141 == TX Byte 0 ==
5798 10:01:36.088387 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5799 10:01:36.095279 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5800 10:01:36.095359 == TX Byte 1 ==
5801 10:01:36.098353 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5802 10:01:36.104886 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5803 10:01:36.104966
5804 10:01:36.105029 [DATLAT]
5805 10:01:36.105088 Freq=933, CH1 RK0
5806 10:01:36.105145
5807 10:01:36.108088 DATLAT Default: 0xd
5808 10:01:36.108167 0, 0xFFFF, sum = 0
5809 10:01:36.111573 1, 0xFFFF, sum = 0
5810 10:01:36.115275 2, 0xFFFF, sum = 0
5811 10:01:36.115357 3, 0xFFFF, sum = 0
5812 10:01:36.118268 4, 0xFFFF, sum = 0
5813 10:01:36.118349 5, 0xFFFF, sum = 0
5814 10:01:36.121588 6, 0xFFFF, sum = 0
5815 10:01:36.121669 7, 0xFFFF, sum = 0
5816 10:01:36.124655 8, 0xFFFF, sum = 0
5817 10:01:36.124736 9, 0xFFFF, sum = 0
5818 10:01:36.128042 10, 0x0, sum = 1
5819 10:01:36.128122 11, 0x0, sum = 2
5820 10:01:36.131583 12, 0x0, sum = 3
5821 10:01:36.131664 13, 0x0, sum = 4
5822 10:01:36.131729 best_step = 11
5823 10:01:36.135142
5824 10:01:36.135222 ==
5825 10:01:36.137799 Dram Type= 6, Freq= 0, CH_1, rank 0
5826 10:01:36.141558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5827 10:01:36.141640 ==
5828 10:01:36.141703 RX Vref Scan: 1
5829 10:01:36.141762
5830 10:01:36.144843 RX Vref 0 -> 0, step: 1
5831 10:01:36.144924
5832 10:01:36.148109 RX Delay -69 -> 252, step: 4
5833 10:01:36.148204
5834 10:01:36.150985 Set Vref, RX VrefLevel [Byte0]: 53
5835 10:01:36.154429 [Byte1]: 51
5836 10:01:36.157687
5837 10:01:36.157767 Final RX Vref Byte 0 = 53 to rank0
5838 10:01:36.161240 Final RX Vref Byte 1 = 51 to rank0
5839 10:01:36.164523 Final RX Vref Byte 0 = 53 to rank1
5840 10:01:36.167321 Final RX Vref Byte 1 = 51 to rank1==
5841 10:01:36.171689 Dram Type= 6, Freq= 0, CH_1, rank 0
5842 10:01:36.178051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5843 10:01:36.178131 ==
5844 10:01:36.178194 DQS Delay:
5845 10:01:36.178253 DQS0 = 0, DQS1 = 0
5846 10:01:36.180750 DQM Delay:
5847 10:01:36.180829 DQM0 = 100, DQM1 = 94
5848 10:01:36.183875 DQ Delay:
5849 10:01:36.187640 DQ0 =104, DQ1 =96, DQ2 =92, DQ3 =98
5850 10:01:36.190733 DQ4 =98, DQ5 =110, DQ6 =110, DQ7 =96
5851 10:01:36.193751 DQ8 =82, DQ9 =84, DQ10 =96, DQ11 =84
5852 10:01:36.197563 DQ12 =102, DQ13 =100, DQ14 =102, DQ15 =102
5853 10:01:36.197642
5854 10:01:36.197705
5855 10:01:36.204116 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a0a, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 413 ps
5856 10:01:36.207413 CH1 RK0: MR19=505, MR18=1A0A
5857 10:01:36.213741 CH1_RK0: MR19=0x505, MR18=0x1A0A, DQSOSC=413, MR23=63, INC=63, DEC=42
5858 10:01:36.213823
5859 10:01:36.217282 ----->DramcWriteLeveling(PI) begin...
5860 10:01:36.217363 ==
5861 10:01:36.220293 Dram Type= 6, Freq= 0, CH_1, rank 1
5862 10:01:36.223963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5863 10:01:36.224043 ==
5864 10:01:36.227471 Write leveling (Byte 0): 25 => 25
5865 10:01:36.230369 Write leveling (Byte 1): 26 => 26
5866 10:01:36.234339 DramcWriteLeveling(PI) end<-----
5867 10:01:36.234419
5868 10:01:36.234482 ==
5869 10:01:36.236810 Dram Type= 6, Freq= 0, CH_1, rank 1
5870 10:01:36.243538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5871 10:01:36.243618 ==
5872 10:01:36.243682 [Gating] SW mode calibration
5873 10:01:36.253764 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5874 10:01:36.256583 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5875 10:01:36.263672 0 14 0 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
5876 10:01:36.267004 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5877 10:01:36.269849 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5878 10:01:36.276609 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5879 10:01:36.280188 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5880 10:01:36.283267 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5881 10:01:36.290485 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5882 10:01:36.293090 0 14 28 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 0)
5883 10:01:36.296561 0 15 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 0)
5884 10:01:36.300024 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5885 10:01:36.306100 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5886 10:01:36.310014 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5887 10:01:36.312961 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5888 10:01:36.319497 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5889 10:01:36.323114 0 15 24 | B1->B0 | 2a2a 2424 | 0 0 | (0 0) (0 0)
5890 10:01:36.326060 0 15 28 | B1->B0 | 4343 3636 | 0 0 | (0 0) (0 0)
5891 10:01:36.333380 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5892 10:01:36.336058 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5893 10:01:36.339735 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5894 10:01:36.346911 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5895 10:01:36.349229 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5896 10:01:36.352448 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5897 10:01:36.359830 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5898 10:01:36.362264 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5899 10:01:36.366050 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5900 10:01:36.372424 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5901 10:01:36.376029 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5902 10:01:36.379162 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5903 10:01:36.386094 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5904 10:01:36.389933 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5905 10:01:36.392572 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5906 10:01:36.399288 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5907 10:01:36.402294 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5908 10:01:36.405609 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5909 10:01:36.412144 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5910 10:01:36.415804 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5911 10:01:36.418960 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5912 10:01:36.425951 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5913 10:01:36.428867 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5914 10:01:36.432397 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5915 10:01:36.439003 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5916 10:01:36.442352 Total UI for P1: 0, mck2ui 16
5917 10:01:36.445340 best dqsien dly found for B1: ( 1, 2, 26)
5918 10:01:36.448923 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5919 10:01:36.451799 Total UI for P1: 0, mck2ui 16
5920 10:01:36.454805 best dqsien dly found for B0: ( 1, 2, 30)
5921 10:01:36.458525 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5922 10:01:36.462120 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5923 10:01:36.462558
5924 10:01:36.464873 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5925 10:01:36.471418 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5926 10:01:36.471833 [Gating] SW calibration Done
5927 10:01:36.472164 ==
5928 10:01:36.475226 Dram Type= 6, Freq= 0, CH_1, rank 1
5929 10:01:36.481848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5930 10:01:36.482261 ==
5931 10:01:36.482588 RX Vref Scan: 0
5932 10:01:36.482892
5933 10:01:36.485096 RX Vref 0 -> 0, step: 1
5934 10:01:36.485546
5935 10:01:36.488480 RX Delay -80 -> 252, step: 8
5936 10:01:36.491080 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5937 10:01:36.494963 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5938 10:01:36.497846 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5939 10:01:36.501811 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5940 10:01:36.507848 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5941 10:01:36.511270 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5942 10:01:36.514387 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5943 10:01:36.518267 iDelay=208, Bit 7, Center 99 (0 ~ 199) 200
5944 10:01:36.520891 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5945 10:01:36.527799 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5946 10:01:36.530762 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5947 10:01:36.534069 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5948 10:01:36.537943 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5949 10:01:36.541615 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5950 10:01:36.544491 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5951 10:01:36.551037 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5952 10:01:36.551459 ==
5953 10:01:36.554219 Dram Type= 6, Freq= 0, CH_1, rank 1
5954 10:01:36.557400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5955 10:01:36.557898 ==
5956 10:01:36.558235 DQS Delay:
5957 10:01:36.561069 DQS0 = 0, DQS1 = 0
5958 10:01:36.561531 DQM Delay:
5959 10:01:36.564440 DQM0 = 100, DQM1 = 90
5960 10:01:36.564858 DQ Delay:
5961 10:01:36.567674 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =95
5962 10:01:36.570926 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5963 10:01:36.574197 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5964 10:01:36.577222 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =103
5965 10:01:36.577805
5966 10:01:36.578149
5967 10:01:36.578456 ==
5968 10:01:36.580820 Dram Type= 6, Freq= 0, CH_1, rank 1
5969 10:01:36.586992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5970 10:01:36.587415 ==
5971 10:01:36.587749
5972 10:01:36.588057
5973 10:01:36.588352 TX Vref Scan disable
5974 10:01:36.590938 == TX Byte 0 ==
5975 10:01:36.593789 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5976 10:01:36.600676 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5977 10:01:36.601112 == TX Byte 1 ==
5978 10:01:36.603509 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5979 10:01:36.610463 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5980 10:01:36.610896 ==
5981 10:01:36.613927 Dram Type= 6, Freq= 0, CH_1, rank 1
5982 10:01:36.617853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5983 10:01:36.618269 ==
5984 10:01:36.618595
5985 10:01:36.618895
5986 10:01:36.620332 TX Vref Scan disable
5987 10:01:36.620741 == TX Byte 0 ==
5988 10:01:36.627111 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5989 10:01:36.630409 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5990 10:01:36.630997 == TX Byte 1 ==
5991 10:01:36.637470 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5992 10:01:36.640476 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5993 10:01:36.640885
5994 10:01:36.641209 [DATLAT]
5995 10:01:36.643550 Freq=933, CH1 RK1
5996 10:01:36.644114
5997 10:01:36.644631 DATLAT Default: 0xb
5998 10:01:36.647275 0, 0xFFFF, sum = 0
5999 10:01:36.647758 1, 0xFFFF, sum = 0
6000 10:01:36.650175 2, 0xFFFF, sum = 0
6001 10:01:36.653511 3, 0xFFFF, sum = 0
6002 10:01:36.653935 4, 0xFFFF, sum = 0
6003 10:01:36.656840 5, 0xFFFF, sum = 0
6004 10:01:36.657257 6, 0xFFFF, sum = 0
6005 10:01:36.660265 7, 0xFFFF, sum = 0
6006 10:01:36.660692 8, 0xFFFF, sum = 0
6007 10:01:36.663262 9, 0xFFFF, sum = 0
6008 10:01:36.663688 10, 0x0, sum = 1
6009 10:01:36.666557 11, 0x0, sum = 2
6010 10:01:36.667023 12, 0x0, sum = 3
6011 10:01:36.669785 13, 0x0, sum = 4
6012 10:01:36.670211 best_step = 11
6013 10:01:36.670576
6014 10:01:36.670888 ==
6015 10:01:36.673269 Dram Type= 6, Freq= 0, CH_1, rank 1
6016 10:01:36.676640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6017 10:01:36.677061 ==
6018 10:01:36.679864 RX Vref Scan: 0
6019 10:01:36.680379
6020 10:01:36.683049 RX Vref 0 -> 0, step: 1
6021 10:01:36.683469
6022 10:01:36.683800 RX Delay -61 -> 252, step: 4
6023 10:01:36.690814 iDelay=207, Bit 0, Center 106 (15 ~ 198) 184
6024 10:01:36.694715 iDelay=207, Bit 1, Center 96 (7 ~ 186) 180
6025 10:01:36.698052 iDelay=207, Bit 2, Center 88 (-1 ~ 178) 180
6026 10:01:36.701151 iDelay=207, Bit 3, Center 98 (11 ~ 186) 176
6027 10:01:36.704660 iDelay=207, Bit 4, Center 100 (7 ~ 194) 188
6028 10:01:36.710925 iDelay=207, Bit 5, Center 112 (23 ~ 202) 180
6029 10:01:36.714435 iDelay=207, Bit 6, Center 112 (19 ~ 206) 188
6030 10:01:36.717194 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
6031 10:01:36.720562 iDelay=207, Bit 8, Center 80 (-9 ~ 170) 180
6032 10:01:36.723841 iDelay=207, Bit 9, Center 82 (-9 ~ 174) 184
6033 10:01:36.730682 iDelay=207, Bit 10, Center 90 (-1 ~ 182) 184
6034 10:01:36.733522 iDelay=207, Bit 11, Center 82 (-9 ~ 174) 184
6035 10:01:36.737361 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
6036 10:01:36.740365 iDelay=207, Bit 13, Center 100 (7 ~ 194) 188
6037 10:01:36.744049 iDelay=207, Bit 14, Center 98 (7 ~ 190) 184
6038 10:01:36.750168 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
6039 10:01:36.750580 ==
6040 10:01:36.753564 Dram Type= 6, Freq= 0, CH_1, rank 1
6041 10:01:36.756919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6042 10:01:36.757333 ==
6043 10:01:36.757714 DQS Delay:
6044 10:01:36.759959 DQS0 = 0, DQS1 = 0
6045 10:01:36.760369 DQM Delay:
6046 10:01:36.763574 DQM0 = 101, DQM1 = 92
6047 10:01:36.763988 DQ Delay:
6048 10:01:36.766779 DQ0 =106, DQ1 =96, DQ2 =88, DQ3 =98
6049 10:01:36.770160 DQ4 =100, DQ5 =112, DQ6 =112, DQ7 =98
6050 10:01:36.773789 DQ8 =80, DQ9 =82, DQ10 =90, DQ11 =82
6051 10:01:36.776736 DQ12 =102, DQ13 =100, DQ14 =98, DQ15 =102
6052 10:01:36.777147
6053 10:01:36.777513
6054 10:01:36.786513 [DQSOSCAuto] RK1, (LSB)MR18= 0x600, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 420 ps
6055 10:01:36.787035 CH1 RK1: MR19=505, MR18=600
6056 10:01:36.793119 CH1_RK1: MR19=0x505, MR18=0x600, DQSOSC=420, MR23=63, INC=61, DEC=40
6057 10:01:36.796980 [RxdqsGatingPostProcess] freq 933
6058 10:01:36.802911 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6059 10:01:36.806622 best DQS0 dly(2T, 0.5T) = (0, 10)
6060 10:01:36.809887 best DQS1 dly(2T, 0.5T) = (0, 10)
6061 10:01:36.813109 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6062 10:01:36.817136 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6063 10:01:36.819570 best DQS0 dly(2T, 0.5T) = (0, 10)
6064 10:01:36.820030 best DQS1 dly(2T, 0.5T) = (0, 10)
6065 10:01:36.823239 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6066 10:01:36.826298 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6067 10:01:36.830215 Pre-setting of DQS Precalculation
6068 10:01:36.837113 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6069 10:01:36.843170 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6070 10:01:36.850375 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6071 10:01:36.851023
6072 10:01:36.851393
6073 10:01:36.853309 [Calibration Summary] 1866 Mbps
6074 10:01:36.856136 CH 0, Rank 0
6075 10:01:36.856691 SW Impedance : PASS
6076 10:01:36.859842 DUTY Scan : NO K
6077 10:01:36.860463 ZQ Calibration : PASS
6078 10:01:36.863212 Jitter Meter : NO K
6079 10:01:36.866101 CBT Training : PASS
6080 10:01:36.866712 Write leveling : PASS
6081 10:01:36.869044 RX DQS gating : PASS
6082 10:01:36.872875 RX DQ/DQS(RDDQC) : PASS
6083 10:01:36.873465 TX DQ/DQS : PASS
6084 10:01:36.875982 RX DATLAT : PASS
6085 10:01:36.879405 RX DQ/DQS(Engine): PASS
6086 10:01:36.879965 TX OE : NO K
6087 10:01:36.882896 All Pass.
6088 10:01:36.883350
6089 10:01:36.883705 CH 0, Rank 1
6090 10:01:36.885807 SW Impedance : PASS
6091 10:01:36.886262 DUTY Scan : NO K
6092 10:01:36.889835 ZQ Calibration : PASS
6093 10:01:36.892897 Jitter Meter : NO K
6094 10:01:36.893450 CBT Training : PASS
6095 10:01:36.896053 Write leveling : PASS
6096 10:01:36.899821 RX DQS gating : PASS
6097 10:01:36.900277 RX DQ/DQS(RDDQC) : PASS
6098 10:01:36.902512 TX DQ/DQS : PASS
6099 10:01:36.905661 RX DATLAT : PASS
6100 10:01:36.906216 RX DQ/DQS(Engine): PASS
6101 10:01:36.909333 TX OE : NO K
6102 10:01:36.909834 All Pass.
6103 10:01:36.910193
6104 10:01:36.912192 CH 1, Rank 0
6105 10:01:36.912643 SW Impedance : PASS
6106 10:01:36.915620 DUTY Scan : NO K
6107 10:01:36.918620 ZQ Calibration : PASS
6108 10:01:36.919099 Jitter Meter : NO K
6109 10:01:36.922492 CBT Training : PASS
6110 10:01:36.925139 Write leveling : PASS
6111 10:01:36.925629 RX DQS gating : PASS
6112 10:01:36.928478 RX DQ/DQS(RDDQC) : PASS
6113 10:01:36.928932 TX DQ/DQS : PASS
6114 10:01:36.932368 RX DATLAT : PASS
6115 10:01:36.935219 RX DQ/DQS(Engine): PASS
6116 10:01:36.935675 TX OE : NO K
6117 10:01:36.938676 All Pass.
6118 10:01:36.939084
6119 10:01:36.939411 CH 1, Rank 1
6120 10:01:36.941939 SW Impedance : PASS
6121 10:01:36.942348 DUTY Scan : NO K
6122 10:01:36.946080 ZQ Calibration : PASS
6123 10:01:36.948851 Jitter Meter : NO K
6124 10:01:36.949263 CBT Training : PASS
6125 10:01:36.952531 Write leveling : PASS
6126 10:01:36.954968 RX DQS gating : PASS
6127 10:01:36.955383 RX DQ/DQS(RDDQC) : PASS
6128 10:01:36.958573 TX DQ/DQS : PASS
6129 10:01:36.961784 RX DATLAT : PASS
6130 10:01:36.962197 RX DQ/DQS(Engine): PASS
6131 10:01:36.964813 TX OE : NO K
6132 10:01:36.965320 All Pass.
6133 10:01:36.965711
6134 10:01:36.968273 DramC Write-DBI off
6135 10:01:36.971814 PER_BANK_REFRESH: Hybrid Mode
6136 10:01:36.972332 TX_TRACKING: ON
6137 10:01:36.981658 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6138 10:01:36.984817 [FAST_K] Save calibration result to emmc
6139 10:01:36.988119 dramc_set_vcore_voltage set vcore to 650000
6140 10:01:36.990992 Read voltage for 400, 6
6141 10:01:36.991406 Vio18 = 0
6142 10:01:36.991736 Vcore = 650000
6143 10:01:36.994415 Vdram = 0
6144 10:01:36.994825 Vddq = 0
6145 10:01:36.995153 Vmddr = 0
6146 10:01:37.001484 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6147 10:01:37.004637 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6148 10:01:37.008427 MEM_TYPE=3, freq_sel=20
6149 10:01:37.011068 sv_algorithm_assistance_LP4_800
6150 10:01:37.014385 ============ PULL DRAM RESETB DOWN ============
6151 10:01:37.020989 ========== PULL DRAM RESETB DOWN end =========
6152 10:01:37.024421 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6153 10:01:37.027393 ===================================
6154 10:01:37.030952 LPDDR4 DRAM CONFIGURATION
6155 10:01:37.034516 ===================================
6156 10:01:37.034954 EX_ROW_EN[0] = 0x0
6157 10:01:37.037624 EX_ROW_EN[1] = 0x0
6158 10:01:37.038034 LP4Y_EN = 0x0
6159 10:01:37.040891 WORK_FSP = 0x0
6160 10:01:37.041302 WL = 0x2
6161 10:01:37.044244 RL = 0x2
6162 10:01:37.044656 BL = 0x2
6163 10:01:37.047284 RPST = 0x0
6164 10:01:37.047694 RD_PRE = 0x0
6165 10:01:37.050767 WR_PRE = 0x1
6166 10:01:37.051179 WR_PST = 0x0
6167 10:01:37.054621 DBI_WR = 0x0
6168 10:01:37.057709 DBI_RD = 0x0
6169 10:01:37.058118 OTF = 0x1
6170 10:01:37.060610 ===================================
6171 10:01:37.064365 ===================================
6172 10:01:37.064885 ANA top config
6173 10:01:37.067270 ===================================
6174 10:01:37.071100 DLL_ASYNC_EN = 0
6175 10:01:37.074877 ALL_SLAVE_EN = 1
6176 10:01:37.077699 NEW_RANK_MODE = 1
6177 10:01:37.080989 DLL_IDLE_MODE = 1
6178 10:01:37.081533 LP45_APHY_COMB_EN = 1
6179 10:01:37.083994 TX_ODT_DIS = 1
6180 10:01:37.087493 NEW_8X_MODE = 1
6181 10:01:37.090720 ===================================
6182 10:01:37.093959 ===================================
6183 10:01:37.097286 data_rate = 800
6184 10:01:37.100530 CKR = 1
6185 10:01:37.100940 DQ_P2S_RATIO = 4
6186 10:01:37.103804 ===================================
6187 10:01:37.107142 CA_P2S_RATIO = 4
6188 10:01:37.110159 DQ_CA_OPEN = 0
6189 10:01:37.113485 DQ_SEMI_OPEN = 1
6190 10:01:37.116683 CA_SEMI_OPEN = 1
6191 10:01:37.119889 CA_FULL_RATE = 0
6192 10:01:37.120305 DQ_CKDIV4_EN = 0
6193 10:01:37.123512 CA_CKDIV4_EN = 1
6194 10:01:37.126851 CA_PREDIV_EN = 0
6195 10:01:37.129803 PH8_DLY = 0
6196 10:01:37.133132 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6197 10:01:37.136480 DQ_AAMCK_DIV = 0
6198 10:01:37.140096 CA_AAMCK_DIV = 0
6199 10:01:37.140506 CA_ADMCK_DIV = 4
6200 10:01:37.143468 DQ_TRACK_CA_EN = 0
6201 10:01:37.146757 CA_PICK = 800
6202 10:01:37.149510 CA_MCKIO = 400
6203 10:01:37.153113 MCKIO_SEMI = 400
6204 10:01:37.156461 PLL_FREQ = 3016
6205 10:01:37.159320 DQ_UI_PI_RATIO = 32
6206 10:01:37.162990 CA_UI_PI_RATIO = 32
6207 10:01:37.166108 ===================================
6208 10:01:37.169272 ===================================
6209 10:01:37.169709 memory_type:LPDDR4
6210 10:01:37.173002 GP_NUM : 10
6211 10:01:37.173438 SRAM_EN : 1
6212 10:01:37.176187 MD32_EN : 0
6213 10:01:37.179194 ===================================
6214 10:01:37.182590 [ANA_INIT] >>>>>>>>>>>>>>
6215 10:01:37.185678 <<<<<< [CONFIGURE PHASE]: ANA_TX
6216 10:01:37.189093 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6217 10:01:37.192222 ===================================
6218 10:01:37.195944 data_rate = 800,PCW = 0X7400
6219 10:01:37.199640 ===================================
6220 10:01:37.202329 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6221 10:01:37.205639 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6222 10:01:37.218865 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6223 10:01:37.222656 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6224 10:01:37.225492 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6225 10:01:37.228854 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6226 10:01:37.231881 [ANA_INIT] flow start
6227 10:01:37.235369 [ANA_INIT] PLL >>>>>>>>
6228 10:01:37.235785 [ANA_INIT] PLL <<<<<<<<
6229 10:01:37.238561 [ANA_INIT] MIDPI >>>>>>>>
6230 10:01:37.242430 [ANA_INIT] MIDPI <<<<<<<<
6231 10:01:37.242881 [ANA_INIT] DLL >>>>>>>>
6232 10:01:37.245879 [ANA_INIT] flow end
6233 10:01:37.248345 ============ LP4 DIFF to SE enter ============
6234 10:01:37.251927 ============ LP4 DIFF to SE exit ============
6235 10:01:37.254948 [ANA_INIT] <<<<<<<<<<<<<
6236 10:01:37.258442 [Flow] Enable top DCM control >>>>>
6237 10:01:37.261651 [Flow] Enable top DCM control <<<<<
6238 10:01:37.265162 Enable DLL master slave shuffle
6239 10:01:37.271861 ==============================================================
6240 10:01:37.272296 Gating Mode config
6241 10:01:37.278318 ==============================================================
6242 10:01:37.278836 Config description:
6243 10:01:37.288037 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6244 10:01:37.295386 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6245 10:01:37.301531 SELPH_MODE 0: By rank 1: By Phase
6246 10:01:37.308096 ==============================================================
6247 10:01:37.308521 GAT_TRACK_EN = 0
6248 10:01:37.311306 RX_GATING_MODE = 2
6249 10:01:37.314488 RX_GATING_TRACK_MODE = 2
6250 10:01:37.317961 SELPH_MODE = 1
6251 10:01:37.322284 PICG_EARLY_EN = 1
6252 10:01:37.324555 VALID_LAT_VALUE = 1
6253 10:01:37.331782 ==============================================================
6254 10:01:37.334431 Enter into Gating configuration >>>>
6255 10:01:37.338134 Exit from Gating configuration <<<<
6256 10:01:37.341039 Enter into DVFS_PRE_config >>>>>
6257 10:01:37.350749 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6258 10:01:37.354587 Exit from DVFS_PRE_config <<<<<
6259 10:01:37.357359 Enter into PICG configuration >>>>
6260 10:01:37.360826 Exit from PICG configuration <<<<
6261 10:01:37.364288 [RX_INPUT] configuration >>>>>
6262 10:01:37.367777 [RX_INPUT] configuration <<<<<
6263 10:01:37.370811 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6264 10:01:37.377199 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6265 10:01:37.384159 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6266 10:01:37.387320 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6267 10:01:37.393622 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6268 10:01:37.400218 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6269 10:01:37.403738 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6270 10:01:37.410360 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6271 10:01:37.413823 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6272 10:01:37.416660 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6273 10:01:37.420284 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6274 10:01:37.426527 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6275 10:01:37.430334 ===================================
6276 10:01:37.433201 LPDDR4 DRAM CONFIGURATION
6277 10:01:37.436564 ===================================
6278 10:01:37.436986 EX_ROW_EN[0] = 0x0
6279 10:01:37.440567 EX_ROW_EN[1] = 0x0
6280 10:01:37.441003 LP4Y_EN = 0x0
6281 10:01:37.443270 WORK_FSP = 0x0
6282 10:01:37.443690 WL = 0x2
6283 10:01:37.446858 RL = 0x2
6284 10:01:37.447277 BL = 0x2
6285 10:01:37.449490 RPST = 0x0
6286 10:01:37.449910 RD_PRE = 0x0
6287 10:01:37.452921 WR_PRE = 0x1
6288 10:01:37.453338 WR_PST = 0x0
6289 10:01:37.457117 DBI_WR = 0x0
6290 10:01:37.457578 DBI_RD = 0x0
6291 10:01:37.459784 OTF = 0x1
6292 10:01:37.463116 ===================================
6293 10:01:37.466105 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6294 10:01:37.469617 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6295 10:01:37.476691 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6296 10:01:37.480174 ===================================
6297 10:01:37.482765 LPDDR4 DRAM CONFIGURATION
6298 10:01:37.483184 ===================================
6299 10:01:37.485984 EX_ROW_EN[0] = 0x10
6300 10:01:37.489353 EX_ROW_EN[1] = 0x0
6301 10:01:37.489819 LP4Y_EN = 0x0
6302 10:01:37.492708 WORK_FSP = 0x0
6303 10:01:37.493128 WL = 0x2
6304 10:01:37.495753 RL = 0x2
6305 10:01:37.496173 BL = 0x2
6306 10:01:37.499908 RPST = 0x0
6307 10:01:37.500326 RD_PRE = 0x0
6308 10:01:37.502403 WR_PRE = 0x1
6309 10:01:37.502820 WR_PST = 0x0
6310 10:01:37.506009 DBI_WR = 0x0
6311 10:01:37.506446 DBI_RD = 0x0
6312 10:01:37.508865 OTF = 0x1
6313 10:01:37.512893 ===================================
6314 10:01:37.518942 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6315 10:01:37.522632 nWR fixed to 30
6316 10:01:37.526164 [ModeRegInit_LP4] CH0 RK0
6317 10:01:37.526607 [ModeRegInit_LP4] CH0 RK1
6318 10:01:37.528798 [ModeRegInit_LP4] CH1 RK0
6319 10:01:37.532095 [ModeRegInit_LP4] CH1 RK1
6320 10:01:37.532512 match AC timing 19
6321 10:01:37.540153 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6322 10:01:37.542204 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6323 10:01:37.545925 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6324 10:01:37.552262 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6325 10:01:37.555346 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6326 10:01:37.555769 ==
6327 10:01:37.558984 Dram Type= 6, Freq= 0, CH_0, rank 0
6328 10:01:37.562098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6329 10:01:37.562519 ==
6330 10:01:37.568349 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6331 10:01:37.575089 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6332 10:01:37.578078 [CA 0] Center 36 (8~64) winsize 57
6333 10:01:37.581830 [CA 1] Center 36 (8~64) winsize 57
6334 10:01:37.584862 [CA 2] Center 36 (8~64) winsize 57
6335 10:01:37.587920 [CA 3] Center 36 (8~64) winsize 57
6336 10:01:37.591765 [CA 4] Center 36 (8~64) winsize 57
6337 10:01:37.594900 [CA 5] Center 36 (8~64) winsize 57
6338 10:01:37.595322
6339 10:01:37.598355 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6340 10:01:37.598776
6341 10:01:37.601461 [CATrainingPosCal] consider 1 rank data
6342 10:01:37.604758 u2DelayCellTimex100 = 270/100 ps
6343 10:01:37.608026 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6344 10:01:37.611225 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6345 10:01:37.615085 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6346 10:01:37.617787 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6347 10:01:37.621054 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6348 10:01:37.624522 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6349 10:01:37.625070
6350 10:01:37.631008 CA PerBit enable=1, Macro0, CA PI delay=36
6351 10:01:37.631448
6352 10:01:37.631809 [CBTSetCACLKResult] CA Dly = 36
6353 10:01:37.634371 CS Dly: 1 (0~32)
6354 10:01:37.634791 ==
6355 10:01:37.637486 Dram Type= 6, Freq= 0, CH_0, rank 1
6356 10:01:37.640850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6357 10:01:37.641496 ==
6358 10:01:37.647197 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6359 10:01:37.654488 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6360 10:01:37.657148 [CA 0] Center 36 (8~64) winsize 57
6361 10:01:37.660474 [CA 1] Center 36 (8~64) winsize 57
6362 10:01:37.664206 [CA 2] Center 36 (8~64) winsize 57
6363 10:01:37.667138 [CA 3] Center 36 (8~64) winsize 57
6364 10:01:37.667557 [CA 4] Center 36 (8~64) winsize 57
6365 10:01:37.671004 [CA 5] Center 36 (8~64) winsize 57
6366 10:01:37.671420
6367 10:01:37.677277 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6368 10:01:37.677743
6369 10:01:37.680684 [CATrainingPosCal] consider 2 rank data
6370 10:01:37.683844 u2DelayCellTimex100 = 270/100 ps
6371 10:01:37.686998 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6372 10:01:37.690385 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6373 10:01:37.693889 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6374 10:01:37.697206 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6375 10:01:37.700483 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6376 10:01:37.703643 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6377 10:01:37.704060
6378 10:01:37.707472 CA PerBit enable=1, Macro0, CA PI delay=36
6379 10:01:37.707887
6380 10:01:37.710556 [CBTSetCACLKResult] CA Dly = 36
6381 10:01:37.713772 CS Dly: 1 (0~32)
6382 10:01:37.714293
6383 10:01:37.716968 ----->DramcWriteLeveling(PI) begin...
6384 10:01:37.717465 ==
6385 10:01:37.720476 Dram Type= 6, Freq= 0, CH_0, rank 0
6386 10:01:37.723420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6387 10:01:37.723838 ==
6388 10:01:37.726787 Write leveling (Byte 0): 40 => 8
6389 10:01:37.730156 Write leveling (Byte 1): 32 => 0
6390 10:01:37.733386 DramcWriteLeveling(PI) end<-----
6391 10:01:37.733844
6392 10:01:37.734173 ==
6393 10:01:37.737042 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 10:01:37.740065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 10:01:37.740583 ==
6396 10:01:37.743854 [Gating] SW mode calibration
6397 10:01:37.749793 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6398 10:01:37.756952 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6399 10:01:37.760392 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6400 10:01:37.766523 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6401 10:01:37.769837 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6402 10:01:37.773556 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6403 10:01:37.779511 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6404 10:01:37.782602 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6405 10:01:37.786500 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6406 10:01:37.792524 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6407 10:01:37.796399 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6408 10:01:37.799778 Total UI for P1: 0, mck2ui 16
6409 10:01:37.803058 best dqsien dly found for B0: ( 0, 14, 24)
6410 10:01:37.805976 Total UI for P1: 0, mck2ui 16
6411 10:01:37.809081 best dqsien dly found for B1: ( 0, 14, 24)
6412 10:01:37.812658 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6413 10:01:37.815901 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6414 10:01:37.816313
6415 10:01:37.818941 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6416 10:01:37.822930 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6417 10:01:37.825823 [Gating] SW calibration Done
6418 10:01:37.826236 ==
6419 10:01:37.829039 Dram Type= 6, Freq= 0, CH_0, rank 0
6420 10:01:37.832605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6421 10:01:37.835735 ==
6422 10:01:37.836304 RX Vref Scan: 0
6423 10:01:37.836639
6424 10:01:37.839168 RX Vref 0 -> 0, step: 1
6425 10:01:37.839728
6426 10:01:37.842738 RX Delay -410 -> 252, step: 16
6427 10:01:37.846244 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6428 10:01:37.849542 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6429 10:01:37.852469 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6430 10:01:37.858882 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6431 10:01:37.862360 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6432 10:01:37.865189 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6433 10:01:37.869045 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6434 10:01:37.875377 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6435 10:01:37.878644 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6436 10:01:37.881852 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6437 10:01:37.888488 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6438 10:01:37.891894 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6439 10:01:37.894902 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6440 10:01:37.898048 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6441 10:01:37.905200 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6442 10:01:37.908243 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6443 10:01:37.908731 ==
6444 10:01:37.911503 Dram Type= 6, Freq= 0, CH_0, rank 0
6445 10:01:37.914912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6446 10:01:37.915377 ==
6447 10:01:37.918047 DQS Delay:
6448 10:01:37.918507 DQS0 = 43, DQS1 = 59
6449 10:01:37.921523 DQM Delay:
6450 10:01:37.921986 DQM0 = 10, DQM1 = 12
6451 10:01:37.922354 DQ Delay:
6452 10:01:37.924571 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6453 10:01:37.927914 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6454 10:01:37.931287 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6455 10:01:37.934749 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6456 10:01:37.935272
6457 10:01:37.935612
6458 10:01:37.935922 ==
6459 10:01:37.937921 Dram Type= 6, Freq= 0, CH_0, rank 0
6460 10:01:37.944918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6461 10:01:37.945358 ==
6462 10:01:37.945826
6463 10:01:37.946147
6464 10:01:37.946485 TX Vref Scan disable
6465 10:01:37.947542 == TX Byte 0 ==
6466 10:01:37.950761 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6467 10:01:37.954721 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6468 10:01:37.958263 == TX Byte 1 ==
6469 10:01:37.960711 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6470 10:01:37.964009 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6471 10:01:37.967569 ==
6472 10:01:37.967991 Dram Type= 6, Freq= 0, CH_0, rank 0
6473 10:01:37.974542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6474 10:01:37.974994 ==
6475 10:01:37.975332
6476 10:01:37.975683
6477 10:01:37.977524 TX Vref Scan disable
6478 10:01:37.977977 == TX Byte 0 ==
6479 10:01:37.980938 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6480 10:01:37.987220 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6481 10:01:37.987787 == TX Byte 1 ==
6482 10:01:37.990907 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6483 10:01:37.997487 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6484 10:01:37.997913
6485 10:01:37.998252 [DATLAT]
6486 10:01:37.998562 Freq=400, CH0 RK0
6487 10:01:37.998863
6488 10:01:38.000392 DATLAT Default: 0xf
6489 10:01:38.003621 0, 0xFFFF, sum = 0
6490 10:01:38.004065 1, 0xFFFF, sum = 0
6491 10:01:38.007814 2, 0xFFFF, sum = 0
6492 10:01:38.008346 3, 0xFFFF, sum = 0
6493 10:01:38.010740 4, 0xFFFF, sum = 0
6494 10:01:38.011273 5, 0xFFFF, sum = 0
6495 10:01:38.013798 6, 0xFFFF, sum = 0
6496 10:01:38.014254 7, 0xFFFF, sum = 0
6497 10:01:38.016687 8, 0xFFFF, sum = 0
6498 10:01:38.017272 9, 0xFFFF, sum = 0
6499 10:01:38.020328 10, 0xFFFF, sum = 0
6500 10:01:38.020901 11, 0xFFFF, sum = 0
6501 10:01:38.023707 12, 0xFFFF, sum = 0
6502 10:01:38.024136 13, 0x0, sum = 1
6503 10:01:38.026767 14, 0x0, sum = 2
6504 10:01:38.027215 15, 0x0, sum = 3
6505 10:01:38.030210 16, 0x0, sum = 4
6506 10:01:38.030634 best_step = 14
6507 10:01:38.030969
6508 10:01:38.031279 ==
6509 10:01:38.033404 Dram Type= 6, Freq= 0, CH_0, rank 0
6510 10:01:38.039787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6511 10:01:38.040211 ==
6512 10:01:38.040545 RX Vref Scan: 1
6513 10:01:38.040923
6514 10:01:38.043065 RX Vref 0 -> 0, step: 1
6515 10:01:38.043482
6516 10:01:38.046408 RX Delay -359 -> 252, step: 8
6517 10:01:38.046828
6518 10:01:38.049935 Set Vref, RX VrefLevel [Byte0]: 60
6519 10:01:38.053066 [Byte1]: 48
6520 10:01:38.056645
6521 10:01:38.057166 Final RX Vref Byte 0 = 60 to rank0
6522 10:01:38.059974 Final RX Vref Byte 1 = 48 to rank0
6523 10:01:38.063612 Final RX Vref Byte 0 = 60 to rank1
6524 10:01:38.066165 Final RX Vref Byte 1 = 48 to rank1==
6525 10:01:38.069785 Dram Type= 6, Freq= 0, CH_0, rank 0
6526 10:01:38.076560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6527 10:01:38.077088 ==
6528 10:01:38.077474 DQS Delay:
6529 10:01:38.080090 DQS0 = 48, DQS1 = 60
6530 10:01:38.080622 DQM Delay:
6531 10:01:38.080956 DQM0 = 12, DQM1 = 12
6532 10:01:38.082703 DQ Delay:
6533 10:01:38.085816 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6534 10:01:38.089573 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6535 10:01:38.090104 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6536 10:01:38.095881 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6537 10:01:38.096391
6538 10:01:38.096728
6539 10:01:38.102395 [DQSOSCAuto] RK0, (LSB)MR18= 0xbe82, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6540 10:01:38.105514 CH0 RK0: MR19=C0C, MR18=BE82
6541 10:01:38.112568 CH0_RK0: MR19=0xC0C, MR18=0xBE82, DQSOSC=386, MR23=63, INC=396, DEC=264
6542 10:01:38.113159 ==
6543 10:01:38.115833 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 10:01:38.118718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 10:01:38.119186 ==
6546 10:01:38.122016 [Gating] SW mode calibration
6547 10:01:38.129150 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6548 10:01:38.135775 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6549 10:01:38.139014 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6550 10:01:38.142944 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6551 10:01:38.148481 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6552 10:01:38.151757 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6553 10:01:38.155060 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6554 10:01:38.161897 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6555 10:01:38.164991 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6556 10:01:38.168190 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6557 10:01:38.174810 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6558 10:01:38.178029 Total UI for P1: 0, mck2ui 16
6559 10:01:38.181963 best dqsien dly found for B0: ( 0, 14, 24)
6560 10:01:38.185186 Total UI for P1: 0, mck2ui 16
6561 10:01:38.188298 best dqsien dly found for B1: ( 0, 14, 24)
6562 10:01:38.191331 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6563 10:01:38.194309 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6564 10:01:38.194775
6565 10:01:38.198214 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6566 10:01:38.201227 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6567 10:01:38.204783 [Gating] SW calibration Done
6568 10:01:38.205265 ==
6569 10:01:38.207708 Dram Type= 6, Freq= 0, CH_0, rank 1
6570 10:01:38.211176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6571 10:01:38.211598 ==
6572 10:01:38.214354 RX Vref Scan: 0
6573 10:01:38.214780
6574 10:01:38.217516 RX Vref 0 -> 0, step: 1
6575 10:01:38.217935
6576 10:01:38.218303 RX Delay -410 -> 252, step: 16
6577 10:01:38.224594 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6578 10:01:38.228356 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6579 10:01:38.231019 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6580 10:01:38.238013 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6581 10:01:38.241282 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6582 10:01:38.244297 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6583 10:01:38.247843 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6584 10:01:38.254845 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6585 10:01:38.257475 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6586 10:01:38.260977 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6587 10:01:38.263842 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6588 10:01:38.270972 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6589 10:01:38.274239 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6590 10:01:38.277655 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6591 10:01:38.281018 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6592 10:01:38.288202 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6593 10:01:38.288755 ==
6594 10:01:38.290553 Dram Type= 6, Freq= 0, CH_0, rank 1
6595 10:01:38.294283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6596 10:01:38.294750 ==
6597 10:01:38.295119 DQS Delay:
6598 10:01:38.297055 DQS0 = 43, DQS1 = 59
6599 10:01:38.297548 DQM Delay:
6600 10:01:38.300336 DQM0 = 11, DQM1 = 16
6601 10:01:38.300795 DQ Delay:
6602 10:01:38.303496 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6603 10:01:38.307013 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6604 10:01:38.310276 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6605 10:01:38.313504 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6606 10:01:38.314115
6607 10:01:38.314515
6608 10:01:38.314942 ==
6609 10:01:38.316782 Dram Type= 6, Freq= 0, CH_0, rank 1
6610 10:01:38.319908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6611 10:01:38.320329 ==
6612 10:01:38.320693
6613 10:01:38.323648
6614 10:01:38.324066 TX Vref Scan disable
6615 10:01:38.327103 == TX Byte 0 ==
6616 10:01:38.330360 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6617 10:01:38.333085 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6618 10:01:38.336878 == TX Byte 1 ==
6619 10:01:38.340345 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6620 10:01:38.343886 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6621 10:01:38.344336 ==
6622 10:01:38.346430 Dram Type= 6, Freq= 0, CH_0, rank 1
6623 10:01:38.349832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6624 10:01:38.352826 ==
6625 10:01:38.353254
6626 10:01:38.353641
6627 10:01:38.354003 TX Vref Scan disable
6628 10:01:38.356418 == TX Byte 0 ==
6629 10:01:38.360161 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6630 10:01:38.363105 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6631 10:01:38.367089 == TX Byte 1 ==
6632 10:01:38.369390 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6633 10:01:38.373146 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6634 10:01:38.373598
6635 10:01:38.373933 [DATLAT]
6636 10:01:38.376389 Freq=400, CH0 RK1
6637 10:01:38.376807
6638 10:01:38.380406 DATLAT Default: 0xe
6639 10:01:38.380931 0, 0xFFFF, sum = 0
6640 10:01:38.383189 1, 0xFFFF, sum = 0
6641 10:01:38.383721 2, 0xFFFF, sum = 0
6642 10:01:38.386449 3, 0xFFFF, sum = 0
6643 10:01:38.386981 4, 0xFFFF, sum = 0
6644 10:01:38.389551 5, 0xFFFF, sum = 0
6645 10:01:38.390092 6, 0xFFFF, sum = 0
6646 10:01:38.392559 7, 0xFFFF, sum = 0
6647 10:01:38.393137 8, 0xFFFF, sum = 0
6648 10:01:38.396696 9, 0xFFFF, sum = 0
6649 10:01:38.397179 10, 0xFFFF, sum = 0
6650 10:01:38.400403 11, 0xFFFF, sum = 0
6651 10:01:38.400827 12, 0xFFFF, sum = 0
6652 10:01:38.402492 13, 0x0, sum = 1
6653 10:01:38.402926 14, 0x0, sum = 2
6654 10:01:38.406367 15, 0x0, sum = 3
6655 10:01:38.406810 16, 0x0, sum = 4
6656 10:01:38.409255 best_step = 14
6657 10:01:38.409733
6658 10:01:38.410074 ==
6659 10:01:38.412648 Dram Type= 6, Freq= 0, CH_0, rank 1
6660 10:01:38.415996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6661 10:01:38.416419 ==
6662 10:01:38.419313 RX Vref Scan: 0
6663 10:01:38.419730
6664 10:01:38.420063 RX Vref 0 -> 0, step: 1
6665 10:01:38.420446
6666 10:01:38.422494 RX Delay -359 -> 252, step: 8
6667 10:01:38.430642 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6668 10:01:38.434257 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6669 10:01:38.437447 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6670 10:01:38.443752 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6671 10:01:38.446926 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6672 10:01:38.451549 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6673 10:01:38.454118 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6674 10:01:38.460098 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6675 10:01:38.464131 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6676 10:01:38.467377 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6677 10:01:38.470566 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6678 10:01:38.476834 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6679 10:01:38.480134 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6680 10:01:38.483573 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6681 10:01:38.486640 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6682 10:01:38.493779 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6683 10:01:38.494347 ==
6684 10:01:38.496686 Dram Type= 6, Freq= 0, CH_0, rank 1
6685 10:01:38.499832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6686 10:01:38.500308 ==
6687 10:01:38.500788 DQS Delay:
6688 10:01:38.504739 DQS0 = 44, DQS1 = 60
6689 10:01:38.505209 DQM Delay:
6690 10:01:38.507013 DQM0 = 7, DQM1 = 15
6691 10:01:38.507482 DQ Delay:
6692 10:01:38.510012 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6693 10:01:38.512985 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6694 10:01:38.516586 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6695 10:01:38.519804 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6696 10:01:38.520275
6697 10:01:38.520756
6698 10:01:38.526227 [DQSOSCAuto] RK1, (LSB)MR18= 0xba46, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 386 ps
6699 10:01:38.529623 CH0 RK1: MR19=C0C, MR18=BA46
6700 10:01:38.536438 CH0_RK1: MR19=0xC0C, MR18=0xBA46, DQSOSC=386, MR23=63, INC=396, DEC=264
6701 10:01:38.539659 [RxdqsGatingPostProcess] freq 400
6702 10:01:38.546399 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6703 10:01:38.549593 best DQS0 dly(2T, 0.5T) = (0, 10)
6704 10:01:38.553322 best DQS1 dly(2T, 0.5T) = (0, 10)
6705 10:01:38.556525 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6706 10:01:38.557077 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6707 10:01:38.560314 best DQS0 dly(2T, 0.5T) = (0, 10)
6708 10:01:38.563156 best DQS1 dly(2T, 0.5T) = (0, 10)
6709 10:01:38.565982 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6710 10:01:38.569586 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6711 10:01:38.572904 Pre-setting of DQS Precalculation
6712 10:01:38.579683 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6713 10:01:38.580150 ==
6714 10:01:38.582733 Dram Type= 6, Freq= 0, CH_1, rank 0
6715 10:01:38.585880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6716 10:01:38.586345 ==
6717 10:01:38.592478 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6718 10:01:38.598966 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6719 10:01:38.602164 [CA 0] Center 36 (8~64) winsize 57
6720 10:01:38.602584 [CA 1] Center 36 (8~64) winsize 57
6721 10:01:38.605387 [CA 2] Center 36 (8~64) winsize 57
6722 10:01:38.609199 [CA 3] Center 36 (8~64) winsize 57
6723 10:01:38.612169 [CA 4] Center 36 (8~64) winsize 57
6724 10:01:38.615286 [CA 5] Center 36 (8~64) winsize 57
6725 10:01:38.615741
6726 10:01:38.618963 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6727 10:01:38.619380
6728 10:01:38.623094 [CATrainingPosCal] consider 1 rank data
6729 10:01:38.625653 u2DelayCellTimex100 = 270/100 ps
6730 10:01:38.628920 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6731 10:01:38.635488 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6732 10:01:38.638922 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6733 10:01:38.642275 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6734 10:01:38.645356 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6735 10:01:38.648754 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6736 10:01:38.649171
6737 10:01:38.652092 CA PerBit enable=1, Macro0, CA PI delay=36
6738 10:01:38.652514
6739 10:01:38.655437 [CBTSetCACLKResult] CA Dly = 36
6740 10:01:38.655858 CS Dly: 1 (0~32)
6741 10:01:38.658464 ==
6742 10:01:38.661853 Dram Type= 6, Freq= 0, CH_1, rank 1
6743 10:01:38.665513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6744 10:01:38.665938 ==
6745 10:01:38.671576 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6746 10:01:38.675051 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6747 10:01:38.678348 [CA 0] Center 36 (8~64) winsize 57
6748 10:01:38.681779 [CA 1] Center 36 (8~64) winsize 57
6749 10:01:38.684648 [CA 2] Center 36 (8~64) winsize 57
6750 10:01:38.687639 [CA 3] Center 36 (8~64) winsize 57
6751 10:01:38.691379 [CA 4] Center 36 (8~64) winsize 57
6752 10:01:38.694361 [CA 5] Center 36 (8~64) winsize 57
6753 10:01:38.694442
6754 10:01:38.697869 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6755 10:01:38.697951
6756 10:01:38.701295 [CATrainingPosCal] consider 2 rank data
6757 10:01:38.704735 u2DelayCellTimex100 = 270/100 ps
6758 10:01:38.707694 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6759 10:01:38.711293 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6760 10:01:38.714824 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6761 10:01:38.721223 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6762 10:01:38.725269 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6763 10:01:38.727875 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6764 10:01:38.728372
6765 10:01:38.731437 CA PerBit enable=1, Macro0, CA PI delay=36
6766 10:01:38.731992
6767 10:01:38.734726 [CBTSetCACLKResult] CA Dly = 36
6768 10:01:38.735283 CS Dly: 1 (0~32)
6769 10:01:38.735656
6770 10:01:38.738411 ----->DramcWriteLeveling(PI) begin...
6771 10:01:38.741503 ==
6772 10:01:38.741970 Dram Type= 6, Freq= 0, CH_1, rank 0
6773 10:01:38.748304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6774 10:01:38.748859 ==
6775 10:01:38.751120 Write leveling (Byte 0): 40 => 8
6776 10:01:38.754764 Write leveling (Byte 1): 32 => 0
6777 10:01:38.757854 DramcWriteLeveling(PI) end<-----
6778 10:01:38.758317
6779 10:01:38.758683 ==
6780 10:01:38.760964 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 10:01:38.764427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 10:01:38.764893 ==
6783 10:01:38.767587 [Gating] SW mode calibration
6784 10:01:38.774392 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6785 10:01:38.777780 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6786 10:01:38.784556 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6787 10:01:38.787281 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6788 10:01:38.791131 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6789 10:01:38.797294 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6790 10:01:38.800998 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6791 10:01:38.803854 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6792 10:01:38.810323 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6793 10:01:38.814736 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6794 10:01:38.817471 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6795 10:01:38.820779 Total UI for P1: 0, mck2ui 16
6796 10:01:38.823770 best dqsien dly found for B0: ( 0, 14, 24)
6797 10:01:38.827075 Total UI for P1: 0, mck2ui 16
6798 10:01:38.830535 best dqsien dly found for B1: ( 0, 14, 24)
6799 10:01:38.836761 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6800 10:01:38.840403 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6801 10:01:38.840912
6802 10:01:38.843229 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6803 10:01:38.847060 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6804 10:01:38.849782 [Gating] SW calibration Done
6805 10:01:38.850083 ==
6806 10:01:38.853341 Dram Type= 6, Freq= 0, CH_1, rank 0
6807 10:01:38.856567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6808 10:01:38.856797 ==
6809 10:01:38.859749 RX Vref Scan: 0
6810 10:01:38.859977
6811 10:01:38.860210 RX Vref 0 -> 0, step: 1
6812 10:01:38.860430
6813 10:01:38.862648 RX Delay -410 -> 252, step: 16
6814 10:01:38.869432 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6815 10:01:38.872809 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6816 10:01:38.876492 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6817 10:01:38.880030 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6818 10:01:38.885872 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6819 10:01:38.890015 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6820 10:01:38.892953 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6821 10:01:38.895820 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6822 10:01:38.902337 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6823 10:01:38.905599 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6824 10:01:38.908884 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6825 10:01:38.912164 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6826 10:01:38.919023 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6827 10:01:38.922672 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6828 10:01:38.925569 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6829 10:01:38.929524 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6830 10:01:38.932341 ==
6831 10:01:38.935480 Dram Type= 6, Freq= 0, CH_1, rank 0
6832 10:01:38.938886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6833 10:01:38.938993 ==
6834 10:01:38.939083 DQS Delay:
6835 10:01:38.942226 DQS0 = 43, DQS1 = 51
6836 10:01:38.942321 DQM Delay:
6837 10:01:38.945338 DQM0 = 12, DQM1 = 14
6838 10:01:38.945442 DQ Delay:
6839 10:01:38.948599 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6840 10:01:38.952467 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6841 10:01:38.955573 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6842 10:01:38.958918 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6843 10:01:38.959041
6844 10:01:38.959166
6845 10:01:38.959284 ==
6846 10:01:38.962475 Dram Type= 6, Freq= 0, CH_1, rank 0
6847 10:01:38.965547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6848 10:01:38.965685 ==
6849 10:01:38.965826
6850 10:01:38.965959
6851 10:01:38.968832 TX Vref Scan disable
6852 10:01:38.968969 == TX Byte 0 ==
6853 10:01:38.975217 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6854 10:01:38.978793 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6855 10:01:38.979223 == TX Byte 1 ==
6856 10:01:38.985836 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6857 10:01:38.989116 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6858 10:01:38.989575 ==
6859 10:01:38.993154 Dram Type= 6, Freq= 0, CH_1, rank 0
6860 10:01:38.996081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6861 10:01:38.996627 ==
6862 10:01:38.997069
6863 10:01:38.997522
6864 10:01:38.998746 TX Vref Scan disable
6865 10:01:39.001974 == TX Byte 0 ==
6866 10:01:39.005394 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6867 10:01:39.008869 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6868 10:01:39.011651 == TX Byte 1 ==
6869 10:01:39.015316 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6870 10:01:39.018958 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6871 10:01:39.019398
6872 10:01:39.019837 [DATLAT]
6873 10:01:39.021659 Freq=400, CH1 RK0
6874 10:01:39.022115
6875 10:01:39.022644 DATLAT Default: 0xf
6876 10:01:39.025065 0, 0xFFFF, sum = 0
6877 10:01:39.027798 1, 0xFFFF, sum = 0
6878 10:01:39.027882 2, 0xFFFF, sum = 0
6879 10:01:39.031330 3, 0xFFFF, sum = 0
6880 10:01:39.031414 4, 0xFFFF, sum = 0
6881 10:01:39.035008 5, 0xFFFF, sum = 0
6882 10:01:39.035099 6, 0xFFFF, sum = 0
6883 10:01:39.037971 7, 0xFFFF, sum = 0
6884 10:01:39.038063 8, 0xFFFF, sum = 0
6885 10:01:39.041577 9, 0xFFFF, sum = 0
6886 10:01:39.041662 10, 0xFFFF, sum = 0
6887 10:01:39.044547 11, 0xFFFF, sum = 0
6888 10:01:39.044630 12, 0xFFFF, sum = 0
6889 10:01:39.047811 13, 0x0, sum = 1
6890 10:01:39.047895 14, 0x0, sum = 2
6891 10:01:39.050945 15, 0x0, sum = 3
6892 10:01:39.051029 16, 0x0, sum = 4
6893 10:01:39.054699 best_step = 14
6894 10:01:39.054781
6895 10:01:39.054865 ==
6896 10:01:39.058210 Dram Type= 6, Freq= 0, CH_1, rank 0
6897 10:01:39.061359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6898 10:01:39.061475 ==
6899 10:01:39.064391 RX Vref Scan: 1
6900 10:01:39.064479
6901 10:01:39.064567 RX Vref 0 -> 0, step: 1
6902 10:01:39.064652
6903 10:01:39.067962 RX Delay -343 -> 252, step: 8
6904 10:01:39.068057
6905 10:01:39.071175 Set Vref, RX VrefLevel [Byte0]: 53
6906 10:01:39.074221 [Byte1]: 51
6907 10:01:39.078844
6908 10:01:39.078955 Final RX Vref Byte 0 = 53 to rank0
6909 10:01:39.082368 Final RX Vref Byte 1 = 51 to rank0
6910 10:01:39.085438 Final RX Vref Byte 0 = 53 to rank1
6911 10:01:39.088799 Final RX Vref Byte 1 = 51 to rank1==
6912 10:01:39.091756 Dram Type= 6, Freq= 0, CH_1, rank 0
6913 10:01:39.098220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6914 10:01:39.098313 ==
6915 10:01:39.098403 DQS Delay:
6916 10:01:39.101428 DQS0 = 48, DQS1 = 56
6917 10:01:39.101514 DQM Delay:
6918 10:01:39.101574 DQM0 = 11, DQM1 = 12
6919 10:01:39.105356 DQ Delay:
6920 10:01:39.108663 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =12
6921 10:01:39.111357 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =4
6922 10:01:39.111437 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6923 10:01:39.118002 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =20
6924 10:01:39.118083
6925 10:01:39.118147
6926 10:01:39.124698 [DQSOSCAuto] RK0, (LSB)MR18= 0x9b72, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6927 10:01:39.128641 CH1 RK0: MR19=C0C, MR18=9B72
6928 10:01:39.135396 CH1_RK0: MR19=0xC0C, MR18=0x9B72, DQSOSC=390, MR23=63, INC=388, DEC=258
6929 10:01:39.135809 ==
6930 10:01:39.138606 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 10:01:39.142003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 10:01:39.142501 ==
6933 10:01:39.146188 [Gating] SW mode calibration
6934 10:01:39.151376 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6935 10:01:39.157885 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6936 10:01:39.161223 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6937 10:01:39.164849 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6938 10:01:39.171306 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6939 10:01:39.174716 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6940 10:01:39.177851 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6941 10:01:39.184512 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6942 10:01:39.187465 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6943 10:01:39.191134 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6944 10:01:39.197744 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6945 10:01:39.200778 Total UI for P1: 0, mck2ui 16
6946 10:01:39.204453 best dqsien dly found for B0: ( 0, 14, 24)
6947 10:01:39.204901 Total UI for P1: 0, mck2ui 16
6948 10:01:39.210974 best dqsien dly found for B1: ( 0, 14, 24)
6949 10:01:39.214429 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6950 10:01:39.217445 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6951 10:01:39.217936
6952 10:01:39.220907 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6953 10:01:39.224133 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6954 10:01:39.227357 [Gating] SW calibration Done
6955 10:01:39.227777 ==
6956 10:01:39.231387 Dram Type= 6, Freq= 0, CH_1, rank 1
6957 10:01:39.234227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6958 10:01:39.234650 ==
6959 10:01:39.237578 RX Vref Scan: 0
6960 10:01:39.238035
6961 10:01:39.240978 RX Vref 0 -> 0, step: 1
6962 10:01:39.241520
6963 10:01:39.241850 RX Delay -410 -> 252, step: 16
6964 10:01:39.247527 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6965 10:01:39.250794 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6966 10:01:39.253588 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6967 10:01:39.260832 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6968 10:01:39.264593 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6969 10:01:39.267074 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6970 10:01:39.270174 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6971 10:01:39.277283 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6972 10:01:39.280526 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6973 10:01:39.283748 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6974 10:01:39.287445 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6975 10:01:39.293274 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6976 10:01:39.296939 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6977 10:01:39.300134 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6978 10:01:39.303242 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6979 10:01:39.309980 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6980 10:01:39.310402 ==
6981 10:01:39.313970 Dram Type= 6, Freq= 0, CH_1, rank 1
6982 10:01:39.316656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6983 10:01:39.317156 ==
6984 10:01:39.317537 DQS Delay:
6985 10:01:39.319730 DQS0 = 43, DQS1 = 51
6986 10:01:39.320148 DQM Delay:
6987 10:01:39.323060 DQM0 = 12, DQM1 = 13
6988 10:01:39.323492 DQ Delay:
6989 10:01:39.326851 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6990 10:01:39.329865 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6991 10:01:39.333043 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6992 10:01:39.336762 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6993 10:01:39.337472
6994 10:01:39.337965
6995 10:01:39.338298 ==
6996 10:01:39.339631 Dram Type= 6, Freq= 0, CH_1, rank 1
6997 10:01:39.343005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6998 10:01:39.343431 ==
6999 10:01:39.343765
7000 10:01:39.346145
7001 10:01:39.346563 TX Vref Scan disable
7002 10:01:39.349317 == TX Byte 0 ==
7003 10:01:39.353108 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
7004 10:01:39.356475 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
7005 10:01:39.359638 == TX Byte 1 ==
7006 10:01:39.363175 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
7007 10:01:39.366817 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
7008 10:01:39.367334 ==
7009 10:01:39.369689 Dram Type= 6, Freq= 0, CH_1, rank 1
7010 10:01:39.372313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7011 10:01:39.375867 ==
7012 10:01:39.376336
7013 10:01:39.376677
7014 10:01:39.377028 TX Vref Scan disable
7015 10:01:39.379447 == TX Byte 0 ==
7016 10:01:39.382646 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
7017 10:01:39.385712 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
7018 10:01:39.388966 == TX Byte 1 ==
7019 10:01:39.392544 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
7020 10:01:39.395640 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
7021 10:01:39.396057
7022 10:01:39.398732 [DATLAT]
7023 10:01:39.399298 Freq=400, CH1 RK1
7024 10:01:39.399798
7025 10:01:39.402598 DATLAT Default: 0xe
7026 10:01:39.403019 0, 0xFFFF, sum = 0
7027 10:01:39.405602 1, 0xFFFF, sum = 0
7028 10:01:39.406204 2, 0xFFFF, sum = 0
7029 10:01:39.409090 3, 0xFFFF, sum = 0
7030 10:01:39.409651 4, 0xFFFF, sum = 0
7031 10:01:39.412145 5, 0xFFFF, sum = 0
7032 10:01:39.412751 6, 0xFFFF, sum = 0
7033 10:01:39.415757 7, 0xFFFF, sum = 0
7034 10:01:39.416337 8, 0xFFFF, sum = 0
7035 10:01:39.419259 9, 0xFFFF, sum = 0
7036 10:01:39.419685 10, 0xFFFF, sum = 0
7037 10:01:39.421941 11, 0xFFFF, sum = 0
7038 10:01:39.422395 12, 0xFFFF, sum = 0
7039 10:01:39.425222 13, 0x0, sum = 1
7040 10:01:39.425764 14, 0x0, sum = 2
7041 10:01:39.429141 15, 0x0, sum = 3
7042 10:01:39.429610 16, 0x0, sum = 4
7043 10:01:39.432400 best_step = 14
7044 10:01:39.432818
7045 10:01:39.433149 ==
7046 10:01:39.435714 Dram Type= 6, Freq= 0, CH_1, rank 1
7047 10:01:39.438675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7048 10:01:39.439098 ==
7049 10:01:39.442127 RX Vref Scan: 0
7050 10:01:39.442545
7051 10:01:39.442876 RX Vref 0 -> 0, step: 1
7052 10:01:39.443186
7053 10:01:39.445299 RX Delay -343 -> 252, step: 8
7054 10:01:39.453053 iDelay=225, Bit 0, Center -32 (-279 ~ 216) 496
7055 10:01:39.456648 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
7056 10:01:39.459859 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
7057 10:01:39.466453 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7058 10:01:39.469880 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
7059 10:01:39.473275 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
7060 10:01:39.476638 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7061 10:01:39.482748 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
7062 10:01:39.486718 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7063 10:01:39.489667 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7064 10:01:39.492897 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
7065 10:01:39.499255 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7066 10:01:39.503182 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7067 10:01:39.506066 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7068 10:01:39.509247 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7069 10:01:39.515740 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7070 10:01:39.516286 ==
7071 10:01:39.519426 Dram Type= 6, Freq= 0, CH_1, rank 1
7072 10:01:39.522657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7073 10:01:39.523171 ==
7074 10:01:39.525574 DQS Delay:
7075 10:01:39.526037 DQS0 = 48, DQS1 = 56
7076 10:01:39.526405 DQM Delay:
7077 10:01:39.529648 DQM0 = 11, DQM1 = 10
7078 10:01:39.530212 DQ Delay:
7079 10:01:39.532509 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
7080 10:01:39.535827 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
7081 10:01:39.538747 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
7082 10:01:39.542284 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7083 10:01:39.542798
7084 10:01:39.543167
7085 10:01:39.549052 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a5a, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7086 10:01:39.552093 CH1 RK1: MR19=C0C, MR18=6A5A
7087 10:01:39.559290 CH1_RK1: MR19=0xC0C, MR18=0x6A5A, DQSOSC=396, MR23=63, INC=376, DEC=251
7088 10:01:39.561935 [RxdqsGatingPostProcess] freq 400
7089 10:01:39.568969 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7090 10:01:39.572143 best DQS0 dly(2T, 0.5T) = (0, 10)
7091 10:01:39.575861 best DQS1 dly(2T, 0.5T) = (0, 10)
7092 10:01:39.578411 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7093 10:01:39.581916 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7094 10:01:39.582475 best DQS0 dly(2T, 0.5T) = (0, 10)
7095 10:01:39.585570 best DQS1 dly(2T, 0.5T) = (0, 10)
7096 10:01:39.588389 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7097 10:01:39.591971 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7098 10:01:39.594875 Pre-setting of DQS Precalculation
7099 10:01:39.601522 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7100 10:01:39.608195 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7101 10:01:39.615463 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7102 10:01:39.616022
7103 10:01:39.616390
7104 10:01:39.618547 [Calibration Summary] 800 Mbps
7105 10:01:39.619012 CH 0, Rank 0
7106 10:01:39.622136 SW Impedance : PASS
7107 10:01:39.624870 DUTY Scan : NO K
7108 10:01:39.625666 ZQ Calibration : PASS
7109 10:01:39.628123 Jitter Meter : NO K
7110 10:01:39.631710 CBT Training : PASS
7111 10:01:39.632224 Write leveling : PASS
7112 10:01:39.634773 RX DQS gating : PASS
7113 10:01:39.637985 RX DQ/DQS(RDDQC) : PASS
7114 10:01:39.638446 TX DQ/DQS : PASS
7115 10:01:39.641403 RX DATLAT : PASS
7116 10:01:39.644886 RX DQ/DQS(Engine): PASS
7117 10:01:39.645349 TX OE : NO K
7118 10:01:39.647853 All Pass.
7119 10:01:39.648313
7120 10:01:39.648679 CH 0, Rank 1
7121 10:01:39.651415 SW Impedance : PASS
7122 10:01:39.651893 DUTY Scan : NO K
7123 10:01:39.654452 ZQ Calibration : PASS
7124 10:01:39.657881 Jitter Meter : NO K
7125 10:01:39.658345 CBT Training : PASS
7126 10:01:39.661362 Write leveling : NO K
7127 10:01:39.664810 RX DQS gating : PASS
7128 10:01:39.665276 RX DQ/DQS(RDDQC) : PASS
7129 10:01:39.668161 TX DQ/DQS : PASS
7130 10:01:39.668582 RX DATLAT : PASS
7131 10:01:39.671733 RX DQ/DQS(Engine): PASS
7132 10:01:39.674492 TX OE : NO K
7133 10:01:39.674912 All Pass.
7134 10:01:39.675245
7135 10:01:39.677925 CH 1, Rank 0
7136 10:01:39.678346 SW Impedance : PASS
7137 10:01:39.680975 DUTY Scan : NO K
7138 10:01:39.681405 ZQ Calibration : PASS
7139 10:01:39.684582 Jitter Meter : NO K
7140 10:01:39.687582 CBT Training : PASS
7141 10:01:39.688001 Write leveling : PASS
7142 10:01:39.690627 RX DQS gating : PASS
7143 10:01:39.693838 RX DQ/DQS(RDDQC) : PASS
7144 10:01:39.694259 TX DQ/DQS : PASS
7145 10:01:39.697104 RX DATLAT : PASS
7146 10:01:39.700547 RX DQ/DQS(Engine): PASS
7147 10:01:39.701134 TX OE : NO K
7148 10:01:39.703729 All Pass.
7149 10:01:39.704160
7150 10:01:39.704501 CH 1, Rank 1
7151 10:01:39.707131 SW Impedance : PASS
7152 10:01:39.707741 DUTY Scan : NO K
7153 10:01:39.710946 ZQ Calibration : PASS
7154 10:01:39.713571 Jitter Meter : NO K
7155 10:01:39.713993 CBT Training : PASS
7156 10:01:39.717087 Write leveling : NO K
7157 10:01:39.720461 RX DQS gating : PASS
7158 10:01:39.720881 RX DQ/DQS(RDDQC) : PASS
7159 10:01:39.724137 TX DQ/DQS : PASS
7160 10:01:39.727251 RX DATLAT : PASS
7161 10:01:39.727672 RX DQ/DQS(Engine): PASS
7162 10:01:39.730692 TX OE : NO K
7163 10:01:39.731112 All Pass.
7164 10:01:39.731443
7165 10:01:39.733968 DramC Write-DBI off
7166 10:01:39.737066 PER_BANK_REFRESH: Hybrid Mode
7167 10:01:39.737526 TX_TRACKING: ON
7168 10:01:39.747038 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7169 10:01:39.750467 [FAST_K] Save calibration result to emmc
7170 10:01:39.753592 dramc_set_vcore_voltage set vcore to 725000
7171 10:01:39.756891 Read voltage for 1600, 0
7172 10:01:39.757443 Vio18 = 0
7173 10:01:39.757822 Vcore = 725000
7174 10:01:39.760431 Vdram = 0
7175 10:01:39.760849 Vddq = 0
7176 10:01:39.761184 Vmddr = 0
7177 10:01:39.766927 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7178 10:01:39.770193 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7179 10:01:39.773252 MEM_TYPE=3, freq_sel=13
7180 10:01:39.777053 sv_algorithm_assistance_LP4_3733
7181 10:01:39.779974 ============ PULL DRAM RESETB DOWN ============
7182 10:01:39.783154 ========== PULL DRAM RESETB DOWN end =========
7183 10:01:39.790181 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7184 10:01:39.793721 ===================================
7185 10:01:39.796509 LPDDR4 DRAM CONFIGURATION
7186 10:01:39.799714 ===================================
7187 10:01:39.800147 EX_ROW_EN[0] = 0x0
7188 10:01:39.803085 EX_ROW_EN[1] = 0x0
7189 10:01:39.803531 LP4Y_EN = 0x0
7190 10:01:39.806491 WORK_FSP = 0x1
7191 10:01:39.806907 WL = 0x5
7192 10:01:39.809807 RL = 0x5
7193 10:01:39.810220 BL = 0x2
7194 10:01:39.813136 RPST = 0x0
7195 10:01:39.813591 RD_PRE = 0x0
7196 10:01:39.816493 WR_PRE = 0x1
7197 10:01:39.816907 WR_PST = 0x1
7198 10:01:39.819609 DBI_WR = 0x0
7199 10:01:39.820035 DBI_RD = 0x0
7200 10:01:39.822903 OTF = 0x1
7201 10:01:39.826212 ===================================
7202 10:01:39.829657 ===================================
7203 10:01:39.830076 ANA top config
7204 10:01:39.832951 ===================================
7205 10:01:39.836170 DLL_ASYNC_EN = 0
7206 10:01:39.839281 ALL_SLAVE_EN = 0
7207 10:01:39.842867 NEW_RANK_MODE = 1
7208 10:01:39.845941 DLL_IDLE_MODE = 1
7209 10:01:39.846356 LP45_APHY_COMB_EN = 1
7210 10:01:39.849843 TX_ODT_DIS = 0
7211 10:01:39.852545 NEW_8X_MODE = 1
7212 10:01:39.855768 ===================================
7213 10:01:39.859628 ===================================
7214 10:01:39.862483 data_rate = 3200
7215 10:01:39.865777 CKR = 1
7216 10:01:39.866190 DQ_P2S_RATIO = 8
7217 10:01:39.869561 ===================================
7218 10:01:39.872763 CA_P2S_RATIO = 8
7219 10:01:39.876260 DQ_CA_OPEN = 0
7220 10:01:39.879258 DQ_SEMI_OPEN = 0
7221 10:01:39.882719 CA_SEMI_OPEN = 0
7222 10:01:39.885601 CA_FULL_RATE = 0
7223 10:01:39.886012 DQ_CKDIV4_EN = 0
7224 10:01:39.888922 CA_CKDIV4_EN = 0
7225 10:01:39.892424 CA_PREDIV_EN = 0
7226 10:01:39.895596 PH8_DLY = 12
7227 10:01:39.899394 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7228 10:01:39.902386 DQ_AAMCK_DIV = 4
7229 10:01:39.902814 CA_AAMCK_DIV = 4
7230 10:01:39.905756 CA_ADMCK_DIV = 4
7231 10:01:39.909323 DQ_TRACK_CA_EN = 0
7232 10:01:39.912436 CA_PICK = 1600
7233 10:01:39.916063 CA_MCKIO = 1600
7234 10:01:39.918741 MCKIO_SEMI = 0
7235 10:01:39.922417 PLL_FREQ = 3068
7236 10:01:39.925582 DQ_UI_PI_RATIO = 32
7237 10:01:39.926008 CA_UI_PI_RATIO = 0
7238 10:01:39.928640 ===================================
7239 10:01:39.931929 ===================================
7240 10:01:39.936002 memory_type:LPDDR4
7241 10:01:39.938753 GP_NUM : 10
7242 10:01:39.939183 SRAM_EN : 1
7243 10:01:39.942442 MD32_EN : 0
7244 10:01:39.945859 ===================================
7245 10:01:39.948618 [ANA_INIT] >>>>>>>>>>>>>>
7246 10:01:39.951855 <<<<<< [CONFIGURE PHASE]: ANA_TX
7247 10:01:39.955472 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7248 10:01:39.958618 ===================================
7249 10:01:39.959043 data_rate = 3200,PCW = 0X7600
7250 10:01:39.961719 ===================================
7251 10:01:39.965172 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7252 10:01:39.971729 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7253 10:01:39.979546 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7254 10:01:39.981901 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7255 10:01:39.985223 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7256 10:01:39.988025 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7257 10:01:39.991868 [ANA_INIT] flow start
7258 10:01:39.994811 [ANA_INIT] PLL >>>>>>>>
7259 10:01:39.995195 [ANA_INIT] PLL <<<<<<<<
7260 10:01:39.998139 [ANA_INIT] MIDPI >>>>>>>>
7261 10:01:40.001656 [ANA_INIT] MIDPI <<<<<<<<
7262 10:01:40.002161 [ANA_INIT] DLL >>>>>>>>
7263 10:01:40.004662 [ANA_INIT] DLL <<<<<<<<
7264 10:01:40.008230 [ANA_INIT] flow end
7265 10:01:40.011791 ============ LP4 DIFF to SE enter ============
7266 10:01:40.015230 ============ LP4 DIFF to SE exit ============
7267 10:01:40.017959 [ANA_INIT] <<<<<<<<<<<<<
7268 10:01:40.021287 [Flow] Enable top DCM control >>>>>
7269 10:01:40.024882 [Flow] Enable top DCM control <<<<<
7270 10:01:40.027597 Enable DLL master slave shuffle
7271 10:01:40.031350 ==============================================================
7272 10:01:40.034662 Gating Mode config
7273 10:01:40.040957 ==============================================================
7274 10:01:40.041385 Config description:
7275 10:01:40.050928 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7276 10:01:40.057964 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7277 10:01:40.061086 SELPH_MODE 0: By rank 1: By Phase
7278 10:01:40.068548 ==============================================================
7279 10:01:40.071513 GAT_TRACK_EN = 1
7280 10:01:40.074519 RX_GATING_MODE = 2
7281 10:01:40.077486 RX_GATING_TRACK_MODE = 2
7282 10:01:40.080955 SELPH_MODE = 1
7283 10:01:40.084420 PICG_EARLY_EN = 1
7284 10:01:40.087568 VALID_LAT_VALUE = 1
7285 10:01:40.091031 ==============================================================
7286 10:01:40.094717 Enter into Gating configuration >>>>
7287 10:01:40.097467 Exit from Gating configuration <<<<
7288 10:01:40.101317 Enter into DVFS_PRE_config >>>>>
7289 10:01:40.114204 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7290 10:01:40.114624 Exit from DVFS_PRE_config <<<<<
7291 10:01:40.117128 Enter into PICG configuration >>>>
7292 10:01:40.120437 Exit from PICG configuration <<<<
7293 10:01:40.123846 [RX_INPUT] configuration >>>>>
7294 10:01:40.127383 [RX_INPUT] configuration <<<<<
7295 10:01:40.133738 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7296 10:01:40.137658 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7297 10:01:40.143966 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7298 10:01:40.150585 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7299 10:01:40.156885 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7300 10:01:40.163986 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7301 10:01:40.167006 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7302 10:01:40.170076 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7303 10:01:40.173344 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7304 10:01:40.180156 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7305 10:01:40.183309 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7306 10:01:40.186464 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7307 10:01:40.189944 ===================================
7308 10:01:40.193224 LPDDR4 DRAM CONFIGURATION
7309 10:01:40.196873 ===================================
7310 10:01:40.200478 EX_ROW_EN[0] = 0x0
7311 10:01:40.200889 EX_ROW_EN[1] = 0x0
7312 10:01:40.203135 LP4Y_EN = 0x0
7313 10:01:40.203546 WORK_FSP = 0x1
7314 10:01:40.206669 WL = 0x5
7315 10:01:40.207080 RL = 0x5
7316 10:01:40.209912 BL = 0x2
7317 10:01:40.210347 RPST = 0x0
7318 10:01:40.213433 RD_PRE = 0x0
7319 10:01:40.213851 WR_PRE = 0x1
7320 10:01:40.217000 WR_PST = 0x1
7321 10:01:40.217443 DBI_WR = 0x0
7322 10:01:40.220156 DBI_RD = 0x0
7323 10:01:40.220582 OTF = 0x1
7324 10:01:40.223169 ===================================
7325 10:01:40.229737 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7326 10:01:40.232838 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7327 10:01:40.236113 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7328 10:01:40.239427 ===================================
7329 10:01:40.243026 LPDDR4 DRAM CONFIGURATION
7330 10:01:40.246023 ===================================
7331 10:01:40.249276 EX_ROW_EN[0] = 0x10
7332 10:01:40.249750 EX_ROW_EN[1] = 0x0
7333 10:01:40.252750 LP4Y_EN = 0x0
7334 10:01:40.253187 WORK_FSP = 0x1
7335 10:01:40.255690 WL = 0x5
7336 10:01:40.256118 RL = 0x5
7337 10:01:40.259261 BL = 0x2
7338 10:01:40.259671 RPST = 0x0
7339 10:01:40.262224 RD_PRE = 0x0
7340 10:01:40.262693 WR_PRE = 0x1
7341 10:01:40.265701 WR_PST = 0x1
7342 10:01:40.266162 DBI_WR = 0x0
7343 10:01:40.269708 DBI_RD = 0x0
7344 10:01:40.272182 OTF = 0x1
7345 10:01:40.275522 ===================================
7346 10:01:40.278891 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7347 10:01:40.279304 ==
7348 10:01:40.282561 Dram Type= 6, Freq= 0, CH_0, rank 0
7349 10:01:40.289044 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7350 10:01:40.289500 ==
7351 10:01:40.289870 [Duty_Offset_Calibration]
7352 10:01:40.292410 B0:1 B1:-1 CA:0
7353 10:01:40.292857
7354 10:01:40.295780 [DutyScan_Calibration_Flow] k_type=0
7355 10:01:40.305230
7356 10:01:40.305714 ==CLK 0==
7357 10:01:40.308595 Final CLK duty delay cell = 0
7358 10:01:40.312200 [0] MAX Duty = 5125%(X100), DQS PI = 20
7359 10:01:40.315279 [0] MIN Duty = 4907%(X100), DQS PI = 6
7360 10:01:40.315731 [0] AVG Duty = 5016%(X100)
7361 10:01:40.318775
7362 10:01:40.321753 CH0 CLK Duty spec in!! Max-Min= 218%
7363 10:01:40.325168 [DutyScan_Calibration_Flow] ====Done====
7364 10:01:40.325619
7365 10:01:40.328449 [DutyScan_Calibration_Flow] k_type=1
7366 10:01:40.344348
7367 10:01:40.344764 ==DQS 0 ==
7368 10:01:40.348403 Final DQS duty delay cell = -4
7369 10:01:40.351001 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7370 10:01:40.354380 [-4] MIN Duty = 4844%(X100), DQS PI = 54
7371 10:01:40.357744 [-4] AVG Duty = 4922%(X100)
7372 10:01:40.358379
7373 10:01:40.358869 ==DQS 1 ==
7374 10:01:40.360752 Final DQS duty delay cell = 0
7375 10:01:40.364353 [0] MAX Duty = 5156%(X100), DQS PI = 0
7376 10:01:40.367366 [0] MIN Duty = 5000%(X100), DQS PI = 20
7377 10:01:40.370828 [0] AVG Duty = 5078%(X100)
7378 10:01:40.371238
7379 10:01:40.373877 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7380 10:01:40.374286
7381 10:01:40.377237 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7382 10:01:40.380829 [DutyScan_Calibration_Flow] ====Done====
7383 10:01:40.381532
7384 10:01:40.384302 [DutyScan_Calibration_Flow] k_type=3
7385 10:01:40.402095
7386 10:01:40.402594 ==DQM 0 ==
7387 10:01:40.405443 Final DQM duty delay cell = 0
7388 10:01:40.408309 [0] MAX Duty = 5124%(X100), DQS PI = 24
7389 10:01:40.412185 [0] MIN Duty = 4907%(X100), DQS PI = 10
7390 10:01:40.415507 [0] AVG Duty = 5015%(X100)
7391 10:01:40.415941
7392 10:01:40.416304 ==DQM 1 ==
7393 10:01:40.418229 Final DQM duty delay cell = 0
7394 10:01:40.421322 [0] MAX Duty = 5000%(X100), DQS PI = 6
7395 10:01:40.424983 [0] MIN Duty = 4813%(X100), DQS PI = 20
7396 10:01:40.428304 [0] AVG Duty = 4906%(X100)
7397 10:01:40.428713
7398 10:01:40.431653 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7399 10:01:40.432062
7400 10:01:40.435389 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7401 10:01:40.438003 [DutyScan_Calibration_Flow] ====Done====
7402 10:01:40.438608
7403 10:01:40.441127 [DutyScan_Calibration_Flow] k_type=2
7404 10:01:40.458786
7405 10:01:40.459228 ==DQ 0 ==
7406 10:01:40.461495 Final DQ duty delay cell = -4
7407 10:01:40.464763 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7408 10:01:40.468171 [-4] MIN Duty = 4876%(X100), DQS PI = 50
7409 10:01:40.471262 [-4] AVG Duty = 4953%(X100)
7410 10:01:40.471675
7411 10:01:40.472000 ==DQ 1 ==
7412 10:01:40.474762 Final DQ duty delay cell = 0
7413 10:01:40.477972 [0] MAX Duty = 5125%(X100), DQS PI = 48
7414 10:01:40.481515 [0] MIN Duty = 4969%(X100), DQS PI = 38
7415 10:01:40.484808 [0] AVG Duty = 5047%(X100)
7416 10:01:40.485338
7417 10:01:40.488007 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7418 10:01:40.488418
7419 10:01:40.490958 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7420 10:01:40.494335 [DutyScan_Calibration_Flow] ====Done====
7421 10:01:40.494748 ==
7422 10:01:40.498249 Dram Type= 6, Freq= 0, CH_1, rank 0
7423 10:01:40.501517 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7424 10:01:40.501940 ==
7425 10:01:40.504305 [Duty_Offset_Calibration]
7426 10:01:40.504678 B0:-1 B1:1 CA:2
7427 10:01:40.507631
7428 10:01:40.510986 [DutyScan_Calibration_Flow] k_type=0
7429 10:01:40.519512
7430 10:01:40.519941 ==CLK 0==
7431 10:01:40.522069 Final CLK duty delay cell = 0
7432 10:01:40.525943 [0] MAX Duty = 5187%(X100), DQS PI = 24
7433 10:01:40.529208 [0] MIN Duty = 4969%(X100), DQS PI = 0
7434 10:01:40.529860 [0] AVG Duty = 5078%(X100)
7435 10:01:40.532213
7436 10:01:40.535866 CH1 CLK Duty spec in!! Max-Min= 218%
7437 10:01:40.538770 [DutyScan_Calibration_Flow] ====Done====
7438 10:01:40.539189
7439 10:01:40.543575 [DutyScan_Calibration_Flow] k_type=1
7440 10:01:40.558795
7441 10:01:40.559208 ==DQS 0 ==
7442 10:01:40.561867 Final DQS duty delay cell = 0
7443 10:01:40.565477 [0] MAX Duty = 5156%(X100), DQS PI = 20
7444 10:01:40.568787 [0] MIN Duty = 4907%(X100), DQS PI = 8
7445 10:01:40.569461 [0] AVG Duty = 5031%(X100)
7446 10:01:40.571873
7447 10:01:40.572387 ==DQS 1 ==
7448 10:01:40.575322 Final DQS duty delay cell = 0
7449 10:01:40.578949 [0] MAX Duty = 5093%(X100), DQS PI = 22
7450 10:01:40.582212 [0] MIN Duty = 4969%(X100), DQS PI = 56
7451 10:01:40.585794 [0] AVG Duty = 5031%(X100)
7452 10:01:40.586308
7453 10:01:40.588665 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7454 10:01:40.589149
7455 10:01:40.591800 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7456 10:01:40.594988 [DutyScan_Calibration_Flow] ====Done====
7457 10:01:40.595406
7458 10:01:40.598974 [DutyScan_Calibration_Flow] k_type=3
7459 10:01:40.614929
7460 10:01:40.615487 ==DQM 0 ==
7461 10:01:40.617907 Final DQM duty delay cell = -4
7462 10:01:40.621228 [-4] MAX Duty = 5062%(X100), DQS PI = 36
7463 10:01:40.624898 [-4] MIN Duty = 4782%(X100), DQS PI = 10
7464 10:01:40.628073 [-4] AVG Duty = 4922%(X100)
7465 10:01:40.628650
7466 10:01:40.629036 ==DQM 1 ==
7467 10:01:40.631045 Final DQM duty delay cell = 0
7468 10:01:40.634778 [0] MAX Duty = 5125%(X100), DQS PI = 0
7469 10:01:40.637877 [0] MIN Duty = 4969%(X100), DQS PI = 34
7470 10:01:40.640824 [0] AVG Duty = 5047%(X100)
7471 10:01:40.641277
7472 10:01:40.644802 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7473 10:01:40.645355
7474 10:01:40.648248 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7475 10:01:40.651205 [DutyScan_Calibration_Flow] ====Done====
7476 10:01:40.651763
7477 10:01:40.654891 [DutyScan_Calibration_Flow] k_type=2
7478 10:01:40.671843
7479 10:01:40.672254 ==DQ 0 ==
7480 10:01:40.675529 Final DQ duty delay cell = 0
7481 10:01:40.678632 [0] MAX Duty = 5156%(X100), DQS PI = 30
7482 10:01:40.682131 [0] MIN Duty = 4906%(X100), DQS PI = 10
7483 10:01:40.682588 [0] AVG Duty = 5031%(X100)
7484 10:01:40.685248
7485 10:01:40.685787 ==DQ 1 ==
7486 10:01:40.688626 Final DQ duty delay cell = 0
7487 10:01:40.691634 [0] MAX Duty = 5156%(X100), DQS PI = 8
7488 10:01:40.695058 [0] MIN Duty = 4969%(X100), DQS PI = 56
7489 10:01:40.695514 [0] AVG Duty = 5062%(X100)
7490 10:01:40.695877
7491 10:01:40.702216 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7492 10:01:40.702763
7493 10:01:40.705348 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7494 10:01:40.708909 [DutyScan_Calibration_Flow] ====Done====
7495 10:01:40.711507 nWR fixed to 30
7496 10:01:40.711964 [ModeRegInit_LP4] CH0 RK0
7497 10:01:40.714982 [ModeRegInit_LP4] CH0 RK1
7498 10:01:40.718617 [ModeRegInit_LP4] CH1 RK0
7499 10:01:40.721597 [ModeRegInit_LP4] CH1 RK1
7500 10:01:40.722056 match AC timing 5
7501 10:01:40.728479 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7502 10:01:40.731159 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7503 10:01:40.734994 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7504 10:01:40.741795 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7505 10:01:40.744740 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7506 10:01:40.745310 [MiockJmeterHQA]
7507 10:01:40.745751
7508 10:01:40.748235 [DramcMiockJmeter] u1RxGatingPI = 0
7509 10:01:40.751632 0 : 4255, 4029
7510 10:01:40.752202 4 : 4252, 4027
7511 10:01:40.754872 8 : 4252, 4027
7512 10:01:40.755350 12 : 4252, 4027
7513 10:01:40.755716 16 : 4255, 4030
7514 10:01:40.757881 20 : 4252, 4027
7515 10:01:40.758345 24 : 4255, 4029
7516 10:01:40.761299 28 : 4363, 4137
7517 10:01:40.761933 32 : 4252, 4027
7518 10:01:40.765178 36 : 4253, 4027
7519 10:01:40.765809 40 : 4252, 4027
7520 10:01:40.768093 44 : 4255, 4029
7521 10:01:40.768650 48 : 4253, 4027
7522 10:01:40.769018 52 : 4363, 4137
7523 10:01:40.771439 56 : 4363, 4137
7524 10:01:40.772000 60 : 4252, 4027
7525 10:01:40.774547 64 : 4252, 4030
7526 10:01:40.775010 68 : 4253, 4027
7527 10:01:40.778123 72 : 4252, 4029
7528 10:01:40.778585 76 : 4252, 4029
7529 10:01:40.780876 80 : 4360, 4138
7530 10:01:40.781497 84 : 4252, 4030
7531 10:01:40.781884 88 : 4250, 4027
7532 10:01:40.784522 92 : 4250, 662
7533 10:01:40.785084 96 : 4360, 0
7534 10:01:40.787830 100 : 4252, 0
7535 10:01:40.788423 104 : 4253, 0
7536 10:01:40.788801 108 : 4250, 0
7537 10:01:40.790678 112 : 4253, 0
7538 10:01:40.791142 116 : 4249, 0
7539 10:01:40.794118 120 : 4255, 0
7540 10:01:40.794584 124 : 4249, 0
7541 10:01:40.794951 128 : 4252, 0
7542 10:01:40.797271 132 : 4363, 0
7543 10:01:40.797777 136 : 4250, 0
7544 10:01:40.800880 140 : 4250, 0
7545 10:01:40.801496 144 : 4252, 0
7546 10:01:40.801894 148 : 4250, 0
7547 10:01:40.804417 152 : 4252, 0
7548 10:01:40.805063 156 : 4252, 0
7549 10:01:40.807142 160 : 4252, 0
7550 10:01:40.807606 164 : 4250, 0
7551 10:01:40.807975 168 : 4361, 0
7552 10:01:40.810672 172 : 4252, 0
7553 10:01:40.811174 176 : 4360, 0
7554 10:01:40.811554 180 : 4249, 0
7555 10:01:40.813890 184 : 4250, 0
7556 10:01:40.814356 188 : 4249, 0
7557 10:01:40.817019 192 : 4250, 0
7558 10:01:40.817533 196 : 4250, 0
7559 10:01:40.817916 200 : 4250, 0
7560 10:01:40.820839 204 : 4252, 0
7561 10:01:40.821303 208 : 4250, 0
7562 10:01:40.823568 212 : 4253, 0
7563 10:01:40.823990 216 : 4252, 0
7564 10:01:40.824329 220 : 4363, 0
7565 10:01:40.827886 224 : 4361, 388
7566 10:01:40.828349 228 : 4250, 3341
7567 10:01:40.830335 232 : 4250, 4027
7568 10:01:40.830774 236 : 4250, 4026
7569 10:01:40.833587 240 : 4250, 4027
7570 10:01:40.834010 244 : 4361, 4138
7571 10:01:40.837114 248 : 4250, 4027
7572 10:01:40.837696 252 : 4250, 4027
7573 10:01:40.840697 256 : 4361, 4137
7574 10:01:40.841116 260 : 4250, 4027
7575 10:01:40.844461 264 : 4249, 4027
7576 10:01:40.844884 268 : 4363, 4140
7577 10:01:40.845219 272 : 4250, 4027
7578 10:01:40.846914 276 : 4250, 4027
7579 10:01:40.847334 280 : 4250, 4027
7580 10:01:40.850790 284 : 4252, 4029
7581 10:01:40.851313 288 : 4250, 4027
7582 10:01:40.853661 292 : 4250, 4027
7583 10:01:40.854084 296 : 4360, 4138
7584 10:01:40.856783 300 : 4250, 4027
7585 10:01:40.857226 304 : 4250, 4026
7586 10:01:40.860422 308 : 4361, 4137
7587 10:01:40.861105 312 : 4250, 4027
7588 10:01:40.863818 316 : 4249, 4027
7589 10:01:40.864392 320 : 4363, 4140
7590 10:01:40.867289 324 : 4250, 4026
7591 10:01:40.867833 328 : 4250, 4027
7592 10:01:40.868175 332 : 4249, 4027
7593 10:01:40.870648 336 : 4252, 3853
7594 10:01:40.871065 340 : 4250, 2027
7595 10:01:40.871398
7596 10:01:40.874050 MIOCK jitter meter ch=0
7597 10:01:40.874565
7598 10:01:40.877369 1T = (340-92) = 248 dly cells
7599 10:01:40.883854 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7600 10:01:40.884414 ==
7601 10:01:40.886913 Dram Type= 6, Freq= 0, CH_0, rank 0
7602 10:01:40.890479 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7603 10:01:40.891041 ==
7604 10:01:40.896877 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7605 10:01:40.899905 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7606 10:01:40.902949 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7607 10:01:40.910062 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7608 10:01:40.919267 [CA 0] Center 43 (12~74) winsize 63
7609 10:01:40.922493 [CA 1] Center 43 (13~73) winsize 61
7610 10:01:40.925781 [CA 2] Center 38 (9~68) winsize 60
7611 10:01:40.929532 [CA 3] Center 38 (8~68) winsize 61
7612 10:01:40.932170 [CA 4] Center 36 (7~66) winsize 60
7613 10:01:40.935851 [CA 5] Center 35 (6~65) winsize 60
7614 10:01:40.936405
7615 10:01:40.938663 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7616 10:01:40.939121
7617 10:01:40.942739 [CATrainingPosCal] consider 1 rank data
7618 10:01:40.945332 u2DelayCellTimex100 = 262/100 ps
7619 10:01:40.952866 CA0 delay=43 (12~74),Diff = 8 PI (29 cell)
7620 10:01:40.955594 CA1 delay=43 (13~73),Diff = 8 PI (29 cell)
7621 10:01:40.958718 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7622 10:01:40.962250 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7623 10:01:40.965890 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7624 10:01:40.968869 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7625 10:01:40.969464
7626 10:01:40.971980 CA PerBit enable=1, Macro0, CA PI delay=35
7627 10:01:40.972536
7628 10:01:40.974849 [CBTSetCACLKResult] CA Dly = 35
7629 10:01:40.978274 CS Dly: 12 (0~43)
7630 10:01:40.982056 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7631 10:01:40.985317 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7632 10:01:40.985929 ==
7633 10:01:40.988115 Dram Type= 6, Freq= 0, CH_0, rank 1
7634 10:01:40.994893 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7635 10:01:40.995354 ==
7636 10:01:40.998691 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7637 10:01:41.004758 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7638 10:01:41.007986 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7639 10:01:41.014523 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7640 10:01:41.023019 [CA 0] Center 43 (13~74) winsize 62
7641 10:01:41.026116 [CA 1] Center 44 (14~74) winsize 61
7642 10:01:41.029269 [CA 2] Center 38 (9~68) winsize 60
7643 10:01:41.032692 [CA 3] Center 38 (9~68) winsize 60
7644 10:01:41.035601 [CA 4] Center 36 (7~66) winsize 60
7645 10:01:41.039209 [CA 5] Center 36 (7~66) winsize 60
7646 10:01:41.039664
7647 10:01:41.042345 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7648 10:01:41.042801
7649 10:01:41.049194 [CATrainingPosCal] consider 2 rank data
7650 10:01:41.049819 u2DelayCellTimex100 = 262/100 ps
7651 10:01:41.055901 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7652 10:01:41.058505 CA1 delay=43 (14~73),Diff = 7 PI (26 cell)
7653 10:01:41.062934 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7654 10:01:41.065082 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7655 10:01:41.068973 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7656 10:01:41.072201 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7657 10:01:41.072760
7658 10:01:41.075327 CA PerBit enable=1, Macro0, CA PI delay=36
7659 10:01:41.075782
7660 10:01:41.078794 [CBTSetCACLKResult] CA Dly = 36
7661 10:01:41.082199 CS Dly: 12 (0~44)
7662 10:01:41.085134 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7663 10:01:41.088790 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7664 10:01:41.089343
7665 10:01:41.091840 ----->DramcWriteLeveling(PI) begin...
7666 10:01:41.092403 ==
7667 10:01:41.095281 Dram Type= 6, Freq= 0, CH_0, rank 0
7668 10:01:41.102274 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7669 10:01:41.103016 ==
7670 10:01:41.105224 Write leveling (Byte 0): 36 => 36
7671 10:01:41.108122 Write leveling (Byte 1): 25 => 25
7672 10:01:41.108586 DramcWriteLeveling(PI) end<-----
7673 10:01:41.111983
7674 10:01:41.112440 ==
7675 10:01:41.115148 Dram Type= 6, Freq= 0, CH_0, rank 0
7676 10:01:41.118121 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7677 10:01:41.118613 ==
7678 10:01:41.121613 [Gating] SW mode calibration
7679 10:01:41.127995 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7680 10:01:41.131359 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7681 10:01:41.138121 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7682 10:01:41.141287 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7683 10:01:41.147451 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7684 10:01:41.151353 1 4 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
7685 10:01:41.154055 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7686 10:01:41.160496 1 4 20 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
7687 10:01:41.163783 1 4 24 | B1->B0 | 2c2b 3434 | 1 1 | (0 0) (1 1)
7688 10:01:41.167255 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7689 10:01:41.173568 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7690 10:01:41.177465 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7691 10:01:41.180462 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7692 10:01:41.186770 1 5 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
7693 10:01:41.189958 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7694 10:01:41.193503 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7695 10:01:41.199875 1 5 24 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
7696 10:01:41.203132 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7697 10:01:41.206300 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7698 10:01:41.212872 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7699 10:01:41.216226 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7700 10:01:41.219529 1 6 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
7701 10:01:41.225872 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7702 10:01:41.229521 1 6 20 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
7703 10:01:41.232849 1 6 24 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7704 10:01:41.239256 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7705 10:01:41.242607 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7706 10:01:41.246211 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7707 10:01:41.252714 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7708 10:01:41.255990 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7709 10:01:41.259464 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7710 10:01:41.266076 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7711 10:01:41.269375 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7712 10:01:41.272945 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7713 10:01:41.279243 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7714 10:01:41.282853 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7715 10:01:41.285680 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7716 10:01:41.292774 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7717 10:01:41.295804 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7718 10:01:41.299621 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7719 10:01:41.306075 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7720 10:01:41.309183 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7721 10:01:41.312332 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7722 10:01:41.319150 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7723 10:01:41.322055 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7724 10:01:41.326389 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7725 10:01:41.331820 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7726 10:01:41.332387 Total UI for P1: 0, mck2ui 16
7727 10:01:41.338340 best dqsien dly found for B0: ( 1, 9, 12)
7728 10:01:41.341806 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7729 10:01:41.345200 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7730 10:01:41.349195 Total UI for P1: 0, mck2ui 16
7731 10:01:41.351965 best dqsien dly found for B1: ( 1, 9, 18)
7732 10:01:41.355140 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7733 10:01:41.358847 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7734 10:01:41.359306
7735 10:01:41.364989 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7736 10:01:41.368470 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7737 10:01:41.371380 [Gating] SW calibration Done
7738 10:01:41.371835 ==
7739 10:01:41.374869 Dram Type= 6, Freq= 0, CH_0, rank 0
7740 10:01:41.378174 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7741 10:01:41.378731 ==
7742 10:01:41.379127 RX Vref Scan: 0
7743 10:01:41.381296
7744 10:01:41.381788 RX Vref 0 -> 0, step: 1
7745 10:01:41.382154
7746 10:01:41.384318 RX Delay 0 -> 252, step: 8
7747 10:01:41.387922 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7748 10:01:41.391168 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7749 10:01:41.397759 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7750 10:01:41.400804 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7751 10:01:41.404646 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7752 10:01:41.407859 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7753 10:01:41.411091 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7754 10:01:41.417548 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7755 10:01:41.421059 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7756 10:01:41.424222 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7757 10:01:41.428276 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7758 10:01:41.430702 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7759 10:01:41.437093 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7760 10:01:41.440549 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7761 10:01:41.444035 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7762 10:01:41.446815 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7763 10:01:41.447358 ==
7764 10:01:41.450406 Dram Type= 6, Freq= 0, CH_0, rank 0
7765 10:01:41.456646 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7766 10:01:41.457069 ==
7767 10:01:41.457566 DQS Delay:
7768 10:01:41.460136 DQS0 = 0, DQS1 = 0
7769 10:01:41.460678 DQM Delay:
7770 10:01:41.463503 DQM0 = 135, DQM1 = 126
7771 10:01:41.463912 DQ Delay:
7772 10:01:41.467047 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7773 10:01:41.470658 DQ4 =139, DQ5 =119, DQ6 =139, DQ7 =147
7774 10:01:41.473539 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7775 10:01:41.476549 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =131
7776 10:01:41.476980
7777 10:01:41.477499
7778 10:01:41.477862 ==
7779 10:01:41.480760 Dram Type= 6, Freq= 0, CH_0, rank 0
7780 10:01:41.486572 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7781 10:01:41.487145 ==
7782 10:01:41.487522
7783 10:01:41.487993
7784 10:01:41.488306 TX Vref Scan disable
7785 10:01:41.490489 == TX Byte 0 ==
7786 10:01:41.493712 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7787 10:01:41.501465 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7788 10:01:41.501921 == TX Byte 1 ==
7789 10:01:41.503661 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7790 10:01:41.510232 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7791 10:01:41.510701 ==
7792 10:01:41.513918 Dram Type= 6, Freq= 0, CH_0, rank 0
7793 10:01:41.516848 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7794 10:01:41.517266 ==
7795 10:01:41.529966
7796 10:01:41.532958 TX Vref early break, caculate TX vref
7797 10:01:41.536789 TX Vref=16, minBit 4, minWin=22, winSum=369
7798 10:01:41.540183 TX Vref=18, minBit 1, minWin=23, winSum=379
7799 10:01:41.543258 TX Vref=20, minBit 0, minWin=23, winSum=382
7800 10:01:41.545996 TX Vref=22, minBit 8, minWin=24, winSum=400
7801 10:01:41.549593 TX Vref=24, minBit 0, minWin=25, winSum=409
7802 10:01:41.556238 TX Vref=26, minBit 0, minWin=25, winSum=416
7803 10:01:41.559413 TX Vref=28, minBit 1, minWin=25, winSum=416
7804 10:01:41.562988 TX Vref=30, minBit 0, minWin=25, winSum=411
7805 10:01:41.566363 TX Vref=32, minBit 0, minWin=24, winSum=398
7806 10:01:41.569368 TX Vref=34, minBit 0, minWin=23, winSum=389
7807 10:01:41.576538 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 26
7808 10:01:41.576639
7809 10:01:41.580005 Final TX Range 0 Vref 26
7810 10:01:41.580105
7811 10:01:41.580197 ==
7812 10:01:41.582860 Dram Type= 6, Freq= 0, CH_0, rank 0
7813 10:01:41.585858 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7814 10:01:41.585929 ==
7815 10:01:41.585992
7816 10:01:41.586049
7817 10:01:41.589992 TX Vref Scan disable
7818 10:01:41.596373 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7819 10:01:41.597100 == TX Byte 0 ==
7820 10:01:41.599908 u2DelayCellOfst[0]=14 cells (4 PI)
7821 10:01:41.602652 u2DelayCellOfst[1]=18 cells (5 PI)
7822 10:01:41.606271 u2DelayCellOfst[2]=14 cells (4 PI)
7823 10:01:41.609250 u2DelayCellOfst[3]=14 cells (4 PI)
7824 10:01:41.612716 u2DelayCellOfst[4]=11 cells (3 PI)
7825 10:01:41.615784 u2DelayCellOfst[5]=0 cells (0 PI)
7826 10:01:41.619882 u2DelayCellOfst[6]=18 cells (5 PI)
7827 10:01:41.622468 u2DelayCellOfst[7]=22 cells (6 PI)
7828 10:01:41.626044 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7829 10:01:41.629339 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7830 10:01:41.633034 == TX Byte 1 ==
7831 10:01:41.635844 u2DelayCellOfst[8]=0 cells (0 PI)
7832 10:01:41.639550 u2DelayCellOfst[9]=3 cells (1 PI)
7833 10:01:41.640007 u2DelayCellOfst[10]=7 cells (2 PI)
7834 10:01:41.642630 u2DelayCellOfst[11]=3 cells (1 PI)
7835 10:01:41.646009 u2DelayCellOfst[12]=11 cells (3 PI)
7836 10:01:41.649178 u2DelayCellOfst[13]=11 cells (3 PI)
7837 10:01:41.652183 u2DelayCellOfst[14]=14 cells (4 PI)
7838 10:01:41.655787 u2DelayCellOfst[15]=11 cells (3 PI)
7839 10:01:41.662128 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7840 10:01:41.665254 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7841 10:01:41.665718 DramC Write-DBI on
7842 10:01:41.668844 ==
7843 10:01:41.669356 Dram Type= 6, Freq= 0, CH_0, rank 0
7844 10:01:41.675571 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7845 10:01:41.676004 ==
7846 10:01:41.676368
7847 10:01:41.676729
7848 10:01:41.678788 TX Vref Scan disable
7849 10:01:41.679206 == TX Byte 0 ==
7850 10:01:41.685493 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7851 10:01:41.685914 == TX Byte 1 ==
7852 10:01:41.688412 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7853 10:01:41.692147 DramC Write-DBI off
7854 10:01:41.692559
7855 10:01:41.692887 [DATLAT]
7856 10:01:41.694992 Freq=1600, CH0 RK0
7857 10:01:41.695418
7858 10:01:41.695785 DATLAT Default: 0xf
7859 10:01:41.698286 0, 0xFFFF, sum = 0
7860 10:01:41.698708 1, 0xFFFF, sum = 0
7861 10:01:41.702100 2, 0xFFFF, sum = 0
7862 10:01:41.702555 3, 0xFFFF, sum = 0
7863 10:01:41.705250 4, 0xFFFF, sum = 0
7864 10:01:41.705705 5, 0xFFFF, sum = 0
7865 10:01:41.708220 6, 0xFFFF, sum = 0
7866 10:01:41.711464 7, 0xFFFF, sum = 0
7867 10:01:41.712081 8, 0xFFFF, sum = 0
7868 10:01:41.715565 9, 0xFFFF, sum = 0
7869 10:01:41.715986 10, 0xFFFF, sum = 0
7870 10:01:41.718676 11, 0xFFFF, sum = 0
7871 10:01:41.719098 12, 0xFFFF, sum = 0
7872 10:01:41.721243 13, 0xFFFF, sum = 0
7873 10:01:41.721825 14, 0x0, sum = 1
7874 10:01:41.724764 15, 0x0, sum = 2
7875 10:01:41.725197 16, 0x0, sum = 3
7876 10:01:41.728499 17, 0x0, sum = 4
7877 10:01:41.728920 best_step = 15
7878 10:01:41.729249
7879 10:01:41.729614 ==
7880 10:01:41.731508 Dram Type= 6, Freq= 0, CH_0, rank 0
7881 10:01:41.734682 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7882 10:01:41.738102 ==
7883 10:01:41.738524 RX Vref Scan: 1
7884 10:01:41.738976
7885 10:01:41.741508 Set Vref Range= 24 -> 127
7886 10:01:41.741926
7887 10:01:41.744628 RX Vref 24 -> 127, step: 1
7888 10:01:41.745078
7889 10:01:41.745598 RX Delay 11 -> 252, step: 4
7890 10:01:41.745942
7891 10:01:41.748058 Set Vref, RX VrefLevel [Byte0]: 24
7892 10:01:41.750997 [Byte1]: 24
7893 10:01:41.754848
7894 10:01:41.755261 Set Vref, RX VrefLevel [Byte0]: 25
7895 10:01:41.758523 [Byte1]: 25
7896 10:01:41.763260
7897 10:01:41.763676 Set Vref, RX VrefLevel [Byte0]: 26
7898 10:01:41.766092 [Byte1]: 26
7899 10:01:41.770030
7900 10:01:41.770468 Set Vref, RX VrefLevel [Byte0]: 27
7901 10:01:41.773711 [Byte1]: 27
7902 10:01:41.777906
7903 10:01:41.778320 Set Vref, RX VrefLevel [Byte0]: 28
7904 10:01:41.781125 [Byte1]: 28
7905 10:01:41.785282
7906 10:01:41.785763 Set Vref, RX VrefLevel [Byte0]: 29
7907 10:01:41.789210 [Byte1]: 29
7908 10:01:41.792887
7909 10:01:41.793298 Set Vref, RX VrefLevel [Byte0]: 30
7910 10:01:41.796733 [Byte1]: 30
7911 10:01:41.800605
7912 10:01:41.801030 Set Vref, RX VrefLevel [Byte0]: 31
7913 10:01:41.803693 [Byte1]: 31
7914 10:01:41.807757
7915 10:01:41.807840 Set Vref, RX VrefLevel [Byte0]: 32
7916 10:01:41.810985 [Byte1]: 32
7917 10:01:41.815563
7918 10:01:41.815644 Set Vref, RX VrefLevel [Byte0]: 33
7919 10:01:41.818932 [Byte1]: 33
7920 10:01:41.823240
7921 10:01:41.823341 Set Vref, RX VrefLevel [Byte0]: 34
7922 10:01:41.826303 [Byte1]: 34
7923 10:01:41.831111
7924 10:01:41.831183 Set Vref, RX VrefLevel [Byte0]: 35
7925 10:01:41.837303 [Byte1]: 35
7926 10:01:41.837389
7927 10:01:41.841295 Set Vref, RX VrefLevel [Byte0]: 36
7928 10:01:41.843835 [Byte1]: 36
7929 10:01:41.843936
7930 10:01:41.847528 Set Vref, RX VrefLevel [Byte0]: 37
7931 10:01:41.850606 [Byte1]: 37
7932 10:01:41.853694
7933 10:01:41.853902 Set Vref, RX VrefLevel [Byte0]: 38
7934 10:01:41.856810 [Byte1]: 38
7935 10:01:41.861223
7936 10:01:41.861366 Set Vref, RX VrefLevel [Byte0]: 39
7937 10:01:41.864421 [Byte1]: 39
7938 10:01:41.868748
7939 10:01:41.868923 Set Vref, RX VrefLevel [Byte0]: 40
7940 10:01:41.872622 [Byte1]: 40
7941 10:01:41.876552
7942 10:01:41.876733 Set Vref, RX VrefLevel [Byte0]: 41
7943 10:01:41.879765 [Byte1]: 41
7944 10:01:41.884349
7945 10:01:41.884621 Set Vref, RX VrefLevel [Byte0]: 42
7946 10:01:41.887759 [Byte1]: 42
7947 10:01:41.891875
7948 10:01:41.892222 Set Vref, RX VrefLevel [Byte0]: 43
7949 10:01:41.895766 [Byte1]: 43
7950 10:01:41.899538
7951 10:01:41.900030 Set Vref, RX VrefLevel [Byte0]: 44
7952 10:01:41.902807 [Byte1]: 44
7953 10:01:41.907543
7954 10:01:41.908046 Set Vref, RX VrefLevel [Byte0]: 45
7955 10:01:41.910824 [Byte1]: 45
7956 10:01:41.914722
7957 10:01:41.915117 Set Vref, RX VrefLevel [Byte0]: 46
7958 10:01:41.918528 [Byte1]: 46
7959 10:01:41.922525
7960 10:01:41.922915 Set Vref, RX VrefLevel [Byte0]: 47
7961 10:01:41.926633 [Byte1]: 47
7962 10:01:41.930047
7963 10:01:41.930597 Set Vref, RX VrefLevel [Byte0]: 48
7964 10:01:41.936460 [Byte1]: 48
7965 10:01:41.936944
7966 10:01:41.939585 Set Vref, RX VrefLevel [Byte0]: 49
7967 10:01:41.942780 [Byte1]: 49
7968 10:01:41.943247
7969 10:01:41.945708 Set Vref, RX VrefLevel [Byte0]: 50
7970 10:01:41.949046 [Byte1]: 50
7971 10:01:41.952867
7972 10:01:41.952973 Set Vref, RX VrefLevel [Byte0]: 51
7973 10:01:41.955810 [Byte1]: 51
7974 10:01:41.959946
7975 10:01:41.960053 Set Vref, RX VrefLevel [Byte0]: 52
7976 10:01:41.963269 [Byte1]: 52
7977 10:01:41.967691
7978 10:01:41.967761 Set Vref, RX VrefLevel [Byte0]: 53
7979 10:01:41.970984 [Byte1]: 53
7980 10:01:41.975694
7981 10:01:41.975791 Set Vref, RX VrefLevel [Byte0]: 54
7982 10:01:41.978588 [Byte1]: 54
7983 10:01:41.983139
7984 10:01:41.983207 Set Vref, RX VrefLevel [Byte0]: 55
7985 10:01:41.986668 [Byte1]: 55
7986 10:01:41.990852
7987 10:01:41.990929 Set Vref, RX VrefLevel [Byte0]: 56
7988 10:01:41.993985 [Byte1]: 56
7989 10:01:41.998605
7990 10:01:41.998700 Set Vref, RX VrefLevel [Byte0]: 57
7991 10:01:42.001836 [Byte1]: 57
7992 10:01:42.005915
7993 10:01:42.006021 Set Vref, RX VrefLevel [Byte0]: 58
7994 10:01:42.008883 [Byte1]: 58
7995 10:01:42.013663
7996 10:01:42.013812 Set Vref, RX VrefLevel [Byte0]: 59
7997 10:01:42.016776 [Byte1]: 59
7998 10:01:42.021209
7999 10:01:42.021533 Set Vref, RX VrefLevel [Byte0]: 60
8000 10:01:42.024394 [Byte1]: 60
8001 10:01:42.028665
8002 10:01:42.028902 Set Vref, RX VrefLevel [Byte0]: 61
8003 10:01:42.032068 [Byte1]: 61
8004 10:01:42.036753
8005 10:01:42.037049 Set Vref, RX VrefLevel [Byte0]: 62
8006 10:01:42.039878 [Byte1]: 62
8007 10:01:42.045137
8008 10:01:42.045591 Set Vref, RX VrefLevel [Byte0]: 63
8009 10:01:42.047397 [Byte1]: 63
8010 10:01:42.051917
8011 10:01:42.052465 Set Vref, RX VrefLevel [Byte0]: 64
8012 10:01:42.055322 [Byte1]: 64
8013 10:01:42.059706
8014 10:01:42.060174 Set Vref, RX VrefLevel [Byte0]: 65
8015 10:01:42.062542 [Byte1]: 65
8016 10:01:42.067188
8017 10:01:42.067604 Set Vref, RX VrefLevel [Byte0]: 66
8018 10:01:42.071394 [Byte1]: 66
8019 10:01:42.074489
8020 10:01:42.074573 Set Vref, RX VrefLevel [Byte0]: 67
8021 10:01:42.077495 [Byte1]: 67
8022 10:01:42.081951
8023 10:01:42.082037 Set Vref, RX VrefLevel [Byte0]: 68
8024 10:01:42.085508 [Byte1]: 68
8025 10:01:42.089662
8026 10:01:42.089763 Set Vref, RX VrefLevel [Byte0]: 69
8027 10:01:42.092701 [Byte1]: 69
8028 10:01:42.096895
8029 10:01:42.096976 Set Vref, RX VrefLevel [Byte0]: 70
8030 10:01:42.100780 [Byte1]: 70
8031 10:01:42.104456
8032 10:01:42.104554 Set Vref, RX VrefLevel [Byte0]: 71
8033 10:01:42.108031 [Byte1]: 71
8034 10:01:42.113297
8035 10:01:42.113416 Set Vref, RX VrefLevel [Byte0]: 72
8036 10:01:42.116574 [Byte1]: 72
8037 10:01:42.120205
8038 10:01:42.120316 Set Vref, RX VrefLevel [Byte0]: 73
8039 10:01:42.123232 [Byte1]: 73
8040 10:01:42.127569
8041 10:01:42.127694 Set Vref, RX VrefLevel [Byte0]: 74
8042 10:01:42.131166 [Byte1]: 74
8043 10:01:42.135320
8044 10:01:42.135457 Set Vref, RX VrefLevel [Byte0]: 75
8045 10:01:42.138324 [Byte1]: 75
8046 10:01:42.142930
8047 10:01:42.143049 Set Vref, RX VrefLevel [Byte0]: 76
8048 10:01:42.146223 [Byte1]: 76
8049 10:01:42.150294
8050 10:01:42.150445 Set Vref, RX VrefLevel [Byte0]: 77
8051 10:01:42.154142 [Byte1]: 77
8052 10:01:42.158393
8053 10:01:42.158629 Set Vref, RX VrefLevel [Byte0]: 78
8054 10:01:42.161718 [Byte1]: 78
8055 10:01:42.165705
8056 10:01:42.165994 Set Vref, RX VrefLevel [Byte0]: 79
8057 10:01:42.169116 [Byte1]: 79
8058 10:01:42.173960
8059 10:01:42.174330 Set Vref, RX VrefLevel [Byte0]: 80
8060 10:01:42.177252 [Byte1]: 80
8061 10:01:42.181030
8062 10:01:42.181536 Set Vref, RX VrefLevel [Byte0]: 81
8063 10:01:42.184546 [Byte1]: 81
8064 10:01:42.188804
8065 10:01:42.189246 Final RX Vref Byte 0 = 65 to rank0
8066 10:01:42.192083 Final RX Vref Byte 1 = 59 to rank0
8067 10:01:42.195903 Final RX Vref Byte 0 = 65 to rank1
8068 10:01:42.198612 Final RX Vref Byte 1 = 59 to rank1==
8069 10:01:42.202069 Dram Type= 6, Freq= 0, CH_0, rank 0
8070 10:01:42.208553 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8071 10:01:42.209041 ==
8072 10:01:42.209573 DQS Delay:
8073 10:01:42.211723 DQS0 = 0, DQS1 = 0
8074 10:01:42.212164 DQM Delay:
8075 10:01:42.212554 DQM0 = 132, DQM1 = 123
8076 10:01:42.215350 DQ Delay:
8077 10:01:42.218416 DQ0 =130, DQ1 =136, DQ2 =130, DQ3 =132
8078 10:01:42.221332 DQ4 =132, DQ5 =122, DQ6 =138, DQ7 =140
8079 10:01:42.224994 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =118
8080 10:01:42.228901 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =128
8081 10:01:42.228984
8082 10:01:42.229048
8083 10:01:42.229106
8084 10:01:42.231255 [DramC_TX_OE_Calibration] TA2
8085 10:01:42.235045 Original DQ_B0 (3 6) =30, OEN = 27
8086 10:01:42.237868 Original DQ_B1 (3 6) =30, OEN = 27
8087 10:01:42.241665 24, 0x0, End_B0=24 End_B1=24
8088 10:01:42.244566 25, 0x0, End_B0=25 End_B1=25
8089 10:01:42.244635 26, 0x0, End_B0=26 End_B1=26
8090 10:01:42.247792 27, 0x0, End_B0=27 End_B1=27
8091 10:01:42.250826 28, 0x0, End_B0=28 End_B1=28
8092 10:01:42.254269 29, 0x0, End_B0=29 End_B1=29
8093 10:01:42.254385 30, 0x0, End_B0=30 End_B1=30
8094 10:01:42.257974 31, 0x4141, End_B0=30 End_B1=30
8095 10:01:42.261319 Byte0 end_step=30 best_step=27
8096 10:01:42.264389 Byte1 end_step=30 best_step=27
8097 10:01:42.267996 Byte0 TX OE(2T, 0.5T) = (3, 3)
8098 10:01:42.271356 Byte1 TX OE(2T, 0.5T) = (3, 3)
8099 10:01:42.271465
8100 10:01:42.271552
8101 10:01:42.277392 [DQSOSCAuto] RK0, (LSB)MR18= 0x2416, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 391 ps
8102 10:01:42.281054 CH0 RK0: MR19=303, MR18=2416
8103 10:01:42.287826 CH0_RK0: MR19=0x303, MR18=0x2416, DQSOSC=391, MR23=63, INC=24, DEC=16
8104 10:01:42.288027
8105 10:01:42.291367 ----->DramcWriteLeveling(PI) begin...
8106 10:01:42.291594 ==
8107 10:01:42.294042 Dram Type= 6, Freq= 0, CH_0, rank 1
8108 10:01:42.297488 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8109 10:01:42.297688 ==
8110 10:01:42.300632 Write leveling (Byte 0): 36 => 36
8111 10:01:42.304274 Write leveling (Byte 1): 30 => 30
8112 10:01:42.308176 DramcWriteLeveling(PI) end<-----
8113 10:01:42.308530
8114 10:01:42.308831 ==
8115 10:01:42.310864 Dram Type= 6, Freq= 0, CH_0, rank 1
8116 10:01:42.314239 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8117 10:01:42.317437 ==
8118 10:01:42.317879 [Gating] SW mode calibration
8119 10:01:42.327075 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8120 10:01:42.330592 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8121 10:01:42.333908 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8122 10:01:42.340767 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8123 10:01:42.343778 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8124 10:01:42.347149 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8125 10:01:42.353932 1 4 16 | B1->B0 | 2424 3333 | 0 1 | (1 1) (1 1)
8126 10:01:42.357164 1 4 20 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
8127 10:01:42.360013 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8128 10:01:42.366747 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8129 10:01:42.370256 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8130 10:01:42.373505 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8131 10:01:42.379745 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8132 10:01:42.383644 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8133 10:01:42.387327 1 5 16 | B1->B0 | 3434 2525 | 1 0 | (1 0) (1 1)
8134 10:01:42.393057 1 5 20 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
8135 10:01:42.396827 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8136 10:01:42.399622 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8137 10:01:42.406338 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8138 10:01:42.409691 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8139 10:01:42.412773 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8140 10:01:42.419553 1 6 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8141 10:01:42.422454 1 6 16 | B1->B0 | 2727 4545 | 0 0 | (1 1) (0 0)
8142 10:01:42.426375 1 6 20 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
8143 10:01:42.432741 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8144 10:01:42.436180 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8145 10:01:42.438905 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8146 10:01:42.445754 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8147 10:01:42.449602 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8148 10:01:42.452723 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8149 10:01:42.459158 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8150 10:01:42.462276 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8151 10:01:42.465440 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8152 10:01:42.472639 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8153 10:01:42.475217 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8154 10:01:42.479334 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8155 10:01:42.485640 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8156 10:01:42.488674 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8157 10:01:42.492237 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8158 10:01:42.498913 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8159 10:01:42.501581 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8160 10:01:42.505344 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8161 10:01:42.512378 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8162 10:01:42.515032 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8163 10:01:42.517991 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8164 10:01:42.525050 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8165 10:01:42.527906 Total UI for P1: 0, mck2ui 16
8166 10:01:42.531091 best dqsien dly found for B0: ( 1, 9, 8)
8167 10:01:42.534359 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8168 10:01:42.537879 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8169 10:01:42.544398 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8170 10:01:42.547771 Total UI for P1: 0, mck2ui 16
8171 10:01:42.551516 best dqsien dly found for B1: ( 1, 9, 18)
8172 10:01:42.554492 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8173 10:01:42.557518 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8174 10:01:42.557590
8175 10:01:42.561101 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8176 10:01:42.564112 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8177 10:01:42.568277 [Gating] SW calibration Done
8178 10:01:42.568344 ==
8179 10:01:42.571139 Dram Type= 6, Freq= 0, CH_0, rank 1
8180 10:01:42.574398 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8181 10:01:42.574479 ==
8182 10:01:42.577347 RX Vref Scan: 0
8183 10:01:42.577461
8184 10:01:42.580682 RX Vref 0 -> 0, step: 1
8185 10:01:42.580762
8186 10:01:42.580826 RX Delay 0 -> 252, step: 8
8187 10:01:42.587585 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8188 10:01:42.590832 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8189 10:01:42.593970 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8190 10:01:42.597576 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8191 10:01:42.600437 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8192 10:01:42.607420 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8193 10:01:42.610897 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8194 10:01:42.613658 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8195 10:01:42.616883 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8196 10:01:42.620145 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8197 10:01:42.626686 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8198 10:01:42.629951 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8199 10:01:42.633236 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8200 10:01:42.636565 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8201 10:01:42.643363 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8202 10:01:42.646737 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8203 10:01:42.646843 ==
8204 10:01:42.649889 Dram Type= 6, Freq= 0, CH_0, rank 1
8205 10:01:42.653381 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8206 10:01:42.653502 ==
8207 10:01:42.653567 DQS Delay:
8208 10:01:42.656960 DQS0 = 0, DQS1 = 0
8209 10:01:42.657060 DQM Delay:
8210 10:01:42.659984 DQM0 = 133, DQM1 = 128
8211 10:01:42.660084 DQ Delay:
8212 10:01:42.663604 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8213 10:01:42.666415 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8214 10:01:42.669883 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8215 10:01:42.676351 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8216 10:01:42.676431
8217 10:01:42.676495
8218 10:01:42.676553 ==
8219 10:01:42.679894 Dram Type= 6, Freq= 0, CH_0, rank 1
8220 10:01:42.683652 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8221 10:01:42.683733 ==
8222 10:01:42.683797
8223 10:01:42.683855
8224 10:01:42.686859 TX Vref Scan disable
8225 10:01:42.686947 == TX Byte 0 ==
8226 10:01:42.693148 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8227 10:01:42.696213 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8228 10:01:42.696305 == TX Byte 1 ==
8229 10:01:42.702969 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8230 10:01:42.705973 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8231 10:01:42.706082 ==
8232 10:01:42.709283 Dram Type= 6, Freq= 0, CH_0, rank 1
8233 10:01:42.713036 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8234 10:01:42.713156 ==
8235 10:01:42.726870
8236 10:01:42.729514 TX Vref early break, caculate TX vref
8237 10:01:42.732998 TX Vref=16, minBit 1, minWin=22, winSum=381
8238 10:01:42.736366 TX Vref=18, minBit 0, minWin=23, winSum=388
8239 10:01:42.739505 TX Vref=20, minBit 1, minWin=23, winSum=396
8240 10:01:42.743190 TX Vref=22, minBit 0, minWin=24, winSum=406
8241 10:01:42.746199 TX Vref=24, minBit 0, minWin=25, winSum=414
8242 10:01:42.752974 TX Vref=26, minBit 0, minWin=25, winSum=419
8243 10:01:42.756387 TX Vref=28, minBit 0, minWin=24, winSum=413
8244 10:01:42.759741 TX Vref=30, minBit 0, minWin=24, winSum=406
8245 10:01:42.762837 TX Vref=32, minBit 0, minWin=24, winSum=397
8246 10:01:42.769866 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 26
8247 10:01:42.770441
8248 10:01:42.772816 Final TX Range 0 Vref 26
8249 10:01:42.773274
8250 10:01:42.773677 ==
8251 10:01:42.776105 Dram Type= 6, Freq= 0, CH_0, rank 1
8252 10:01:42.779526 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8253 10:01:42.780051 ==
8254 10:01:42.780413
8255 10:01:42.780719
8256 10:01:42.782645 TX Vref Scan disable
8257 10:01:42.789806 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8258 10:01:42.790269 == TX Byte 0 ==
8259 10:01:42.792470 u2DelayCellOfst[0]=11 cells (3 PI)
8260 10:01:42.795837 u2DelayCellOfst[1]=18 cells (5 PI)
8261 10:01:42.799046 u2DelayCellOfst[2]=11 cells (3 PI)
8262 10:01:42.802720 u2DelayCellOfst[3]=14 cells (4 PI)
8263 10:01:42.805907 u2DelayCellOfst[4]=7 cells (2 PI)
8264 10:01:42.809151 u2DelayCellOfst[5]=0 cells (0 PI)
8265 10:01:42.809742 u2DelayCellOfst[6]=14 cells (4 PI)
8266 10:01:42.812611 u2DelayCellOfst[7]=18 cells (5 PI)
8267 10:01:42.819235 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8268 10:01:42.822266 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8269 10:01:42.822679 == TX Byte 1 ==
8270 10:01:42.825925 u2DelayCellOfst[8]=0 cells (0 PI)
8271 10:01:42.829112 u2DelayCellOfst[9]=3 cells (1 PI)
8272 10:01:42.832082 u2DelayCellOfst[10]=7 cells (2 PI)
8273 10:01:42.835763 u2DelayCellOfst[11]=3 cells (1 PI)
8274 10:01:42.838755 u2DelayCellOfst[12]=14 cells (4 PI)
8275 10:01:42.842906 u2DelayCellOfst[13]=14 cells (4 PI)
8276 10:01:42.845656 u2DelayCellOfst[14]=18 cells (5 PI)
8277 10:01:42.848632 u2DelayCellOfst[15]=14 cells (4 PI)
8278 10:01:42.852300 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8279 10:01:42.858775 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8280 10:01:42.859229 DramC Write-DBI on
8281 10:01:42.859562 ==
8282 10:01:42.862354 Dram Type= 6, Freq= 0, CH_0, rank 1
8283 10:01:42.865267 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8284 10:01:42.869180 ==
8285 10:01:42.869697
8286 10:01:42.870050
8287 10:01:42.870356 TX Vref Scan disable
8288 10:01:42.872473 == TX Byte 0 ==
8289 10:01:42.875288 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8290 10:01:42.878548 == TX Byte 1 ==
8291 10:01:42.881618 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
8292 10:01:42.884911 DramC Write-DBI off
8293 10:01:42.885318
8294 10:01:42.885722 [DATLAT]
8295 10:01:42.886033 Freq=1600, CH0 RK1
8296 10:01:42.886361
8297 10:01:42.888349 DATLAT Default: 0xf
8298 10:01:42.891898 0, 0xFFFF, sum = 0
8299 10:01:42.892318 1, 0xFFFF, sum = 0
8300 10:01:42.894986 2, 0xFFFF, sum = 0
8301 10:01:42.895402 3, 0xFFFF, sum = 0
8302 10:01:42.898690 4, 0xFFFF, sum = 0
8303 10:01:42.899107 5, 0xFFFF, sum = 0
8304 10:01:42.901341 6, 0xFFFF, sum = 0
8305 10:01:42.901923 7, 0xFFFF, sum = 0
8306 10:01:42.904843 8, 0xFFFF, sum = 0
8307 10:01:42.905259 9, 0xFFFF, sum = 0
8308 10:01:42.908070 10, 0xFFFF, sum = 0
8309 10:01:42.908510 11, 0xFFFF, sum = 0
8310 10:01:42.911830 12, 0xFFFF, sum = 0
8311 10:01:42.912271 13, 0xFFFF, sum = 0
8312 10:01:42.914632 14, 0x0, sum = 1
8313 10:01:42.915128 15, 0x0, sum = 2
8314 10:01:42.918113 16, 0x0, sum = 3
8315 10:01:42.918533 17, 0x0, sum = 4
8316 10:01:42.921097 best_step = 15
8317 10:01:42.921555
8318 10:01:42.921893 ==
8319 10:01:42.924528 Dram Type= 6, Freq= 0, CH_0, rank 1
8320 10:01:42.927428 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8321 10:01:42.927536 ==
8322 10:01:42.930468 RX Vref Scan: 0
8323 10:01:42.930573
8324 10:01:42.930667 RX Vref 0 -> 0, step: 1
8325 10:01:42.930757
8326 10:01:42.933998 RX Delay 11 -> 252, step: 4
8327 10:01:42.940972 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8328 10:01:42.944290 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8329 10:01:42.947388 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8330 10:01:42.950586 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8331 10:01:42.953840 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8332 10:01:42.960493 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8333 10:01:42.964223 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8334 10:01:42.967110 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8335 10:01:42.971023 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8336 10:01:42.973894 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8337 10:01:42.980227 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8338 10:01:42.984268 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8339 10:01:42.987105 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8340 10:01:42.990958 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8341 10:01:42.997343 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8342 10:01:43.000572 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8343 10:01:43.000677 ==
8344 10:01:43.003972 Dram Type= 6, Freq= 0, CH_0, rank 1
8345 10:01:43.007096 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8346 10:01:43.007184 ==
8347 10:01:43.007256 DQS Delay:
8348 10:01:43.010038 DQS0 = 0, DQS1 = 0
8349 10:01:43.010126 DQM Delay:
8350 10:01:43.013729 DQM0 = 130, DQM1 = 125
8351 10:01:43.013863 DQ Delay:
8352 10:01:43.017394 DQ0 =128, DQ1 =134, DQ2 =124, DQ3 =128
8353 10:01:43.020678 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =140
8354 10:01:43.023365 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
8355 10:01:43.030001 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8356 10:01:43.030079
8357 10:01:43.030146
8358 10:01:43.030205
8359 10:01:43.033467 [DramC_TX_OE_Calibration] TA2
8360 10:01:43.036467 Original DQ_B0 (3 6) =30, OEN = 27
8361 10:01:43.036544 Original DQ_B1 (3 6) =30, OEN = 27
8362 10:01:43.039600 24, 0x0, End_B0=24 End_B1=24
8363 10:01:43.043094 25, 0x0, End_B0=25 End_B1=25
8364 10:01:43.046444 26, 0x0, End_B0=26 End_B1=26
8365 10:01:43.049627 27, 0x0, End_B0=27 End_B1=27
8366 10:01:43.049708 28, 0x0, End_B0=28 End_B1=28
8367 10:01:43.053331 29, 0x0, End_B0=29 End_B1=29
8368 10:01:43.056404 30, 0x0, End_B0=30 End_B1=30
8369 10:01:43.059362 31, 0x4141, End_B0=30 End_B1=30
8370 10:01:43.062726 Byte0 end_step=30 best_step=27
8371 10:01:43.065998 Byte1 end_step=30 best_step=27
8372 10:01:43.066078 Byte0 TX OE(2T, 0.5T) = (3, 3)
8373 10:01:43.069657 Byte1 TX OE(2T, 0.5T) = (3, 3)
8374 10:01:43.069740
8375 10:01:43.069810
8376 10:01:43.080020 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e00, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 394 ps
8377 10:01:43.083103 CH0 RK1: MR19=303, MR18=1E00
8378 10:01:43.085853 CH0_RK1: MR19=0x303, MR18=0x1E00, DQSOSC=394, MR23=63, INC=23, DEC=15
8379 10:01:43.089719 [RxdqsGatingPostProcess] freq 1600
8380 10:01:43.095963 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8381 10:01:43.099461 best DQS0 dly(2T, 0.5T) = (1, 1)
8382 10:01:43.103035 best DQS1 dly(2T, 0.5T) = (1, 1)
8383 10:01:43.105575 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8384 10:01:43.108974 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8385 10:01:43.112713 best DQS0 dly(2T, 0.5T) = (1, 1)
8386 10:01:43.115915 best DQS1 dly(2T, 0.5T) = (1, 1)
8387 10:01:43.116085 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8388 10:01:43.119315 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8389 10:01:43.122289 Pre-setting of DQS Precalculation
8390 10:01:43.129697 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8391 10:01:43.130017 ==
8392 10:01:43.132304 Dram Type= 6, Freq= 0, CH_1, rank 0
8393 10:01:43.135905 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8394 10:01:43.136282 ==
8395 10:01:43.142618 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8396 10:01:43.146151 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8397 10:01:43.149844 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8398 10:01:43.155621 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8399 10:01:43.165248 [CA 0] Center 41 (12~71) winsize 60
8400 10:01:43.168924 [CA 1] Center 42 (13~72) winsize 60
8401 10:01:43.172091 [CA 2] Center 37 (8~66) winsize 59
8402 10:01:43.175358 [CA 3] Center 35 (6~65) winsize 60
8403 10:01:43.178207 [CA 4] Center 36 (7~66) winsize 60
8404 10:01:43.181935 [CA 5] Center 36 (6~66) winsize 61
8405 10:01:43.182347
8406 10:01:43.185446 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8407 10:01:43.185863
8408 10:01:43.188833 [CATrainingPosCal] consider 1 rank data
8409 10:01:43.191553 u2DelayCellTimex100 = 262/100 ps
8410 10:01:43.198527 CA0 delay=41 (12~71),Diff = 6 PI (22 cell)
8411 10:01:43.201873 CA1 delay=42 (13~72),Diff = 7 PI (26 cell)
8412 10:01:43.205460 CA2 delay=37 (8~66),Diff = 2 PI (7 cell)
8413 10:01:43.207992 CA3 delay=35 (6~65),Diff = 0 PI (0 cell)
8414 10:01:43.211903 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
8415 10:01:43.214854 CA5 delay=36 (6~66),Diff = 1 PI (3 cell)
8416 10:01:43.215313
8417 10:01:43.218263 CA PerBit enable=1, Macro0, CA PI delay=35
8418 10:01:43.218687
8419 10:01:43.221376 [CBTSetCACLKResult] CA Dly = 35
8420 10:01:43.224599 CS Dly: 9 (0~40)
8421 10:01:43.227901 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8422 10:01:43.230924 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8423 10:01:43.231517 ==
8424 10:01:43.234950 Dram Type= 6, Freq= 0, CH_1, rank 1
8425 10:01:43.240878 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8426 10:01:43.241292 ==
8427 10:01:43.244377 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8428 10:01:43.250665 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8429 10:01:43.253864 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8430 10:01:43.260188 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8431 10:01:43.268117 [CA 0] Center 43 (14~72) winsize 59
8432 10:01:43.271588 [CA 1] Center 42 (13~72) winsize 60
8433 10:01:43.274937 [CA 2] Center 37 (8~67) winsize 60
8434 10:01:43.278625 [CA 3] Center 37 (7~67) winsize 61
8435 10:01:43.282047 [CA 4] Center 37 (8~67) winsize 60
8436 10:01:43.284700 [CA 5] Center 37 (8~67) winsize 60
8437 10:01:43.285202
8438 10:01:43.288068 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8439 10:01:43.288623
8440 10:01:43.291140 [CATrainingPosCal] consider 2 rank data
8441 10:01:43.294738 u2DelayCellTimex100 = 262/100 ps
8442 10:01:43.301178 CA0 delay=42 (14~71),Diff = 6 PI (22 cell)
8443 10:01:43.304433 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8444 10:01:43.308024 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8445 10:01:43.311082 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8446 10:01:43.314472 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8447 10:01:43.318002 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8448 10:01:43.318418
8449 10:01:43.321363 CA PerBit enable=1, Macro0, CA PI delay=36
8450 10:01:43.322007
8451 10:01:43.324544 [CBTSetCACLKResult] CA Dly = 36
8452 10:01:43.327901 CS Dly: 10 (0~43)
8453 10:01:43.331413 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8454 10:01:43.334391 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8455 10:01:43.334807
8456 10:01:43.337972 ----->DramcWriteLeveling(PI) begin...
8457 10:01:43.338570 ==
8458 10:01:43.340811 Dram Type= 6, Freq= 0, CH_1, rank 0
8459 10:01:43.347593 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8460 10:01:43.348010 ==
8461 10:01:43.351044 Write leveling (Byte 0): 25 => 25
8462 10:01:43.351462 Write leveling (Byte 1): 27 => 27
8463 10:01:43.354510 DramcWriteLeveling(PI) end<-----
8464 10:01:43.355089
8465 10:01:43.357719 ==
8466 10:01:43.358134 Dram Type= 6, Freq= 0, CH_1, rank 0
8467 10:01:43.364066 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8468 10:01:43.364484 ==
8469 10:01:43.367991 [Gating] SW mode calibration
8470 10:01:43.374299 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8471 10:01:43.378058 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8472 10:01:43.383947 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8473 10:01:43.387858 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8474 10:01:43.391280 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8475 10:01:43.397462 1 4 12 | B1->B0 | 3232 3333 | 0 1 | (0 0) (1 1)
8476 10:01:43.400843 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8477 10:01:43.404424 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8478 10:01:43.410436 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8479 10:01:43.413864 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8480 10:01:43.416935 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8481 10:01:43.423737 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8482 10:01:43.427851 1 5 8 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 1)
8483 10:01:43.430545 1 5 12 | B1->B0 | 2727 2323 | 0 0 | (0 1) (1 0)
8484 10:01:43.437252 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8485 10:01:43.440448 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8486 10:01:43.443196 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8487 10:01:43.450262 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8488 10:01:43.453986 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8489 10:01:43.456751 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8490 10:01:43.463343 1 6 8 | B1->B0 | 2424 3636 | 0 1 | (0 0) (0 0)
8491 10:01:43.466716 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8492 10:01:43.470432 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8493 10:01:43.476561 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8494 10:01:43.479147 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8495 10:01:43.482749 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8496 10:01:43.489271 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8497 10:01:43.492593 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8498 10:01:43.496340 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8499 10:01:43.502985 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8500 10:01:43.505651 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8501 10:01:43.508629 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8502 10:01:43.515360 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8503 10:01:43.518453 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8504 10:01:43.522111 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8505 10:01:43.528321 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8506 10:01:43.532428 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8507 10:01:43.534867 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8508 10:01:43.541651 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8509 10:01:43.545554 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8510 10:01:43.548634 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8511 10:01:43.555702 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8512 10:01:43.558699 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8513 10:01:43.561822 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8514 10:01:43.568338 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8515 10:01:43.571446 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8516 10:01:43.574445 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8517 10:01:43.577928 Total UI for P1: 0, mck2ui 16
8518 10:01:43.581481 best dqsien dly found for B0: ( 1, 9, 10)
8519 10:01:43.584368 Total UI for P1: 0, mck2ui 16
8520 10:01:43.587825 best dqsien dly found for B1: ( 1, 9, 12)
8521 10:01:43.590990 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8522 10:01:43.597447 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8523 10:01:43.597528
8524 10:01:43.601005 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8525 10:01:43.604399 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8526 10:01:43.607555 [Gating] SW calibration Done
8527 10:01:43.607639 ==
8528 10:01:43.610550 Dram Type= 6, Freq= 0, CH_1, rank 0
8529 10:01:43.614155 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8530 10:01:43.614266 ==
8531 10:01:43.617572 RX Vref Scan: 0
8532 10:01:43.617669
8533 10:01:43.617761 RX Vref 0 -> 0, step: 1
8534 10:01:43.617857
8535 10:01:43.620744 RX Delay 0 -> 252, step: 8
8536 10:01:43.624085 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8537 10:01:43.630661 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8538 10:01:43.633841 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8539 10:01:43.637091 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8540 10:01:43.640538 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8541 10:01:43.643728 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8542 10:01:43.650027 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8543 10:01:43.654053 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8544 10:01:43.657011 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8545 10:01:43.660578 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8546 10:01:43.663553 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8547 10:01:43.669800 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8548 10:01:43.673322 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8549 10:01:43.676853 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8550 10:01:43.680441 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8551 10:01:43.686314 iDelay=208, Bit 15, Center 139 (88 ~ 191) 104
8552 10:01:43.686410 ==
8553 10:01:43.690080 Dram Type= 6, Freq= 0, CH_1, rank 0
8554 10:01:43.693588 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8555 10:01:43.693671 ==
8556 10:01:43.693736 DQS Delay:
8557 10:01:43.696401 DQS0 = 0, DQS1 = 0
8558 10:01:43.696482 DQM Delay:
8559 10:01:43.699553 DQM0 = 138, DQM1 = 130
8560 10:01:43.699634 DQ Delay:
8561 10:01:43.703113 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =139
8562 10:01:43.706868 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8563 10:01:43.709494 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =123
8564 10:01:43.713596 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8565 10:01:43.713704
8566 10:01:43.713796
8567 10:01:43.716212 ==
8568 10:01:43.719312 Dram Type= 6, Freq= 0, CH_1, rank 0
8569 10:01:43.722452 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8570 10:01:43.722562 ==
8571 10:01:43.722658
8572 10:01:43.722746
8573 10:01:43.726024 TX Vref Scan disable
8574 10:01:43.726105 == TX Byte 0 ==
8575 10:01:43.732799 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8576 10:01:43.736293 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8577 10:01:43.736400 == TX Byte 1 ==
8578 10:01:43.742468 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8579 10:01:43.746048 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8580 10:01:43.746152 ==
8581 10:01:43.748713 Dram Type= 6, Freq= 0, CH_1, rank 0
8582 10:01:43.751926 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8583 10:01:43.752008 ==
8584 10:01:43.765708
8585 10:01:43.768942 TX Vref early break, caculate TX vref
8586 10:01:43.772133 TX Vref=16, minBit 0, minWin=22, winSum=378
8587 10:01:43.775269 TX Vref=18, minBit 5, minWin=22, winSum=389
8588 10:01:43.779509 TX Vref=20, minBit 10, minWin=23, winSum=396
8589 10:01:43.782015 TX Vref=22, minBit 0, minWin=25, winSum=410
8590 10:01:43.789009 TX Vref=24, minBit 0, minWin=25, winSum=419
8591 10:01:43.791509 TX Vref=26, minBit 0, minWin=25, winSum=422
8592 10:01:43.794729 TX Vref=28, minBit 0, minWin=26, winSum=425
8593 10:01:43.798864 TX Vref=30, minBit 1, minWin=25, winSum=418
8594 10:01:43.802001 TX Vref=32, minBit 0, minWin=24, winSum=405
8595 10:01:43.805120 TX Vref=34, minBit 6, minWin=23, winSum=396
8596 10:01:43.811462 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 28
8597 10:01:43.811545
8598 10:01:43.815073 Final TX Range 0 Vref 28
8599 10:01:43.815155
8600 10:01:43.815218 ==
8601 10:01:43.818619 Dram Type= 6, Freq= 0, CH_1, rank 0
8602 10:01:43.821246 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8603 10:01:43.821357 ==
8604 10:01:43.821505
8605 10:01:43.821577
8606 10:01:43.825117 TX Vref Scan disable
8607 10:01:43.831488 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8608 10:01:43.831569 == TX Byte 0 ==
8609 10:01:43.834626 u2DelayCellOfst[0]=18 cells (5 PI)
8610 10:01:43.838226 u2DelayCellOfst[1]=14 cells (4 PI)
8611 10:01:43.841254 u2DelayCellOfst[2]=0 cells (0 PI)
8612 10:01:43.844735 u2DelayCellOfst[3]=7 cells (2 PI)
8613 10:01:43.847835 u2DelayCellOfst[4]=7 cells (2 PI)
8614 10:01:43.850978 u2DelayCellOfst[5]=22 cells (6 PI)
8615 10:01:43.854414 u2DelayCellOfst[6]=22 cells (6 PI)
8616 10:01:43.857742 u2DelayCellOfst[7]=7 cells (2 PI)
8617 10:01:43.861244 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8618 10:01:43.864680 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8619 10:01:43.867890 == TX Byte 1 ==
8620 10:01:43.870842 u2DelayCellOfst[8]=0 cells (0 PI)
8621 10:01:43.874306 u2DelayCellOfst[9]=3 cells (1 PI)
8622 10:01:43.877645 u2DelayCellOfst[10]=11 cells (3 PI)
8623 10:01:43.880590 u2DelayCellOfst[11]=3 cells (1 PI)
8624 10:01:43.880672 u2DelayCellOfst[12]=14 cells (4 PI)
8625 10:01:43.884136 u2DelayCellOfst[13]=18 cells (5 PI)
8626 10:01:43.887414 u2DelayCellOfst[14]=18 cells (5 PI)
8627 10:01:43.890339 u2DelayCellOfst[15]=18 cells (5 PI)
8628 10:01:43.897297 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8629 10:01:43.900378 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8630 10:01:43.903384 DramC Write-DBI on
8631 10:01:43.903468 ==
8632 10:01:43.906850 Dram Type= 6, Freq= 0, CH_1, rank 0
8633 10:01:43.910528 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8634 10:01:43.910609 ==
8635 10:01:43.910673
8636 10:01:43.910732
8637 10:01:43.913586 TX Vref Scan disable
8638 10:01:43.913669 == TX Byte 0 ==
8639 10:01:43.920053 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8640 10:01:43.920134 == TX Byte 1 ==
8641 10:01:43.923566 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8642 10:01:43.926941 DramC Write-DBI off
8643 10:01:43.927022
8644 10:01:43.927086 [DATLAT]
8645 10:01:43.929915 Freq=1600, CH1 RK0
8646 10:01:43.929996
8647 10:01:43.930090 DATLAT Default: 0xf
8648 10:01:43.933611 0, 0xFFFF, sum = 0
8649 10:01:43.933722 1, 0xFFFF, sum = 0
8650 10:01:43.936563 2, 0xFFFF, sum = 0
8651 10:01:43.936645 3, 0xFFFF, sum = 0
8652 10:01:43.940181 4, 0xFFFF, sum = 0
8653 10:01:43.943328 5, 0xFFFF, sum = 0
8654 10:01:43.943426 6, 0xFFFF, sum = 0
8655 10:01:43.946565 7, 0xFFFF, sum = 0
8656 10:01:43.946687 8, 0xFFFF, sum = 0
8657 10:01:43.949886 9, 0xFFFF, sum = 0
8658 10:01:43.950012 10, 0xFFFF, sum = 0
8659 10:01:43.953198 11, 0xFFFF, sum = 0
8660 10:01:43.953292 12, 0xFFFF, sum = 0
8661 10:01:43.957316 13, 0xFFFF, sum = 0
8662 10:01:43.957456 14, 0x0, sum = 1
8663 10:01:43.960221 15, 0x0, sum = 2
8664 10:01:43.960336 16, 0x0, sum = 3
8665 10:01:43.963176 17, 0x0, sum = 4
8666 10:01:43.963326 best_step = 15
8667 10:01:43.963480
8668 10:01:43.963620 ==
8669 10:01:43.966077 Dram Type= 6, Freq= 0, CH_1, rank 0
8670 10:01:43.969916 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8671 10:01:43.972690 ==
8672 10:01:43.972770 RX Vref Scan: 1
8673 10:01:43.972834
8674 10:01:43.976509 Set Vref Range= 24 -> 127
8675 10:01:43.976590
8676 10:01:43.979240 RX Vref 24 -> 127, step: 1
8677 10:01:43.979336
8678 10:01:43.979429 RX Delay 19 -> 252, step: 4
8679 10:01:43.979522
8680 10:01:43.982832 Set Vref, RX VrefLevel [Byte0]: 24
8681 10:01:43.985750 [Byte1]: 24
8682 10:01:43.990243
8683 10:01:43.990323 Set Vref, RX VrefLevel [Byte0]: 25
8684 10:01:43.993291 [Byte1]: 25
8685 10:01:43.997835
8686 10:01:43.997944 Set Vref, RX VrefLevel [Byte0]: 26
8687 10:01:44.000921 [Byte1]: 26
8688 10:01:44.005920
8689 10:01:44.006012 Set Vref, RX VrefLevel [Byte0]: 27
8690 10:01:44.008688 [Byte1]: 27
8691 10:01:44.012522
8692 10:01:44.012657 Set Vref, RX VrefLevel [Byte0]: 28
8693 10:01:44.015857 [Byte1]: 28
8694 10:01:44.020279
8695 10:01:44.020399 Set Vref, RX VrefLevel [Byte0]: 29
8696 10:01:44.023913 [Byte1]: 29
8697 10:01:44.027713
8698 10:01:44.027886 Set Vref, RX VrefLevel [Byte0]: 30
8699 10:01:44.031725 [Byte1]: 30
8700 10:01:44.035982
8701 10:01:44.036151 Set Vref, RX VrefLevel [Byte0]: 31
8702 10:01:44.038848 [Byte1]: 31
8703 10:01:44.043807
8704 10:01:44.044137 Set Vref, RX VrefLevel [Byte0]: 32
8705 10:01:44.049802 [Byte1]: 32
8706 10:01:44.050126
8707 10:01:44.052729 Set Vref, RX VrefLevel [Byte0]: 33
8708 10:01:44.056022 [Byte1]: 33
8709 10:01:44.056268
8710 10:01:44.059642 Set Vref, RX VrefLevel [Byte0]: 34
8711 10:01:44.062897 [Byte1]: 34
8712 10:01:44.065828
8713 10:01:44.066141 Set Vref, RX VrefLevel [Byte0]: 35
8714 10:01:44.069231 [Byte1]: 35
8715 10:01:44.073396
8716 10:01:44.073743 Set Vref, RX VrefLevel [Byte0]: 36
8717 10:01:44.076977 [Byte1]: 36
8718 10:01:44.081164
8719 10:01:44.081401 Set Vref, RX VrefLevel [Byte0]: 37
8720 10:01:44.084722 [Byte1]: 37
8721 10:01:44.089214
8722 10:01:44.089541 Set Vref, RX VrefLevel [Byte0]: 38
8723 10:01:44.092258 [Byte1]: 38
8724 10:01:44.096100
8725 10:01:44.096594 Set Vref, RX VrefLevel [Byte0]: 39
8726 10:01:44.099689 [Byte1]: 39
8727 10:01:44.104072
8728 10:01:44.104454 Set Vref, RX VrefLevel [Byte0]: 40
8729 10:01:44.107151 [Byte1]: 40
8730 10:01:44.111431
8731 10:01:44.111974 Set Vref, RX VrefLevel [Byte0]: 41
8732 10:01:44.114767 [Byte1]: 41
8733 10:01:44.119279
8734 10:01:44.119694 Set Vref, RX VrefLevel [Byte0]: 42
8735 10:01:44.122432 [Byte1]: 42
8736 10:01:44.126714
8737 10:01:44.127249 Set Vref, RX VrefLevel [Byte0]: 43
8738 10:01:44.129662 [Byte1]: 43
8739 10:01:44.134325
8740 10:01:44.134740 Set Vref, RX VrefLevel [Byte0]: 44
8741 10:01:44.137687 [Byte1]: 44
8742 10:01:44.142501
8743 10:01:44.143030 Set Vref, RX VrefLevel [Byte0]: 45
8744 10:01:44.145276 [Byte1]: 45
8745 10:01:44.150373
8746 10:01:44.150922 Set Vref, RX VrefLevel [Byte0]: 46
8747 10:01:44.152541 [Byte1]: 46
8748 10:01:44.156850
8749 10:01:44.157493 Set Vref, RX VrefLevel [Byte0]: 47
8750 10:01:44.160293 [Byte1]: 47
8751 10:01:44.164776
8752 10:01:44.165188 Set Vref, RX VrefLevel [Byte0]: 48
8753 10:01:44.167550 [Byte1]: 48
8754 10:01:44.172064
8755 10:01:44.172611 Set Vref, RX VrefLevel [Byte0]: 49
8756 10:01:44.175323 [Byte1]: 49
8757 10:01:44.179476
8758 10:01:44.180066 Set Vref, RX VrefLevel [Byte0]: 50
8759 10:01:44.182932 [Byte1]: 50
8760 10:01:44.187198
8761 10:01:44.187609 Set Vref, RX VrefLevel [Byte0]: 51
8762 10:01:44.191169 [Byte1]: 51
8763 10:01:44.195386
8764 10:01:44.195915 Set Vref, RX VrefLevel [Byte0]: 52
8765 10:01:44.197926 [Byte1]: 52
8766 10:01:44.202423
8767 10:01:44.202837 Set Vref, RX VrefLevel [Byte0]: 53
8768 10:01:44.205659 [Byte1]: 53
8769 10:01:44.210160
8770 10:01:44.210689 Set Vref, RX VrefLevel [Byte0]: 54
8771 10:01:44.213022 [Byte1]: 54
8772 10:01:44.217929
8773 10:01:44.218344 Set Vref, RX VrefLevel [Byte0]: 55
8774 10:01:44.220891 [Byte1]: 55
8775 10:01:44.225291
8776 10:01:44.225907 Set Vref, RX VrefLevel [Byte0]: 56
8777 10:01:44.228756 [Byte1]: 56
8778 10:01:44.232597
8779 10:01:44.233141 Set Vref, RX VrefLevel [Byte0]: 57
8780 10:01:44.235735 [Byte1]: 57
8781 10:01:44.240230
8782 10:01:44.240529 Set Vref, RX VrefLevel [Byte0]: 58
8783 10:01:44.243595 [Byte1]: 58
8784 10:01:44.247606
8785 10:01:44.247984 Set Vref, RX VrefLevel [Byte0]: 59
8786 10:01:44.251249 [Byte1]: 59
8787 10:01:44.255329
8788 10:01:44.255745 Set Vref, RX VrefLevel [Byte0]: 60
8789 10:01:44.259032 [Byte1]: 60
8790 10:01:44.263323
8791 10:01:44.263888 Set Vref, RX VrefLevel [Byte0]: 61
8792 10:01:44.266372 [Byte1]: 61
8793 10:01:44.270576
8794 10:01:44.270979 Set Vref, RX VrefLevel [Byte0]: 62
8795 10:01:44.273726 [Byte1]: 62
8796 10:01:44.277972
8797 10:01:44.278195 Set Vref, RX VrefLevel [Byte0]: 63
8798 10:01:44.281029 [Byte1]: 63
8799 10:01:44.285436
8800 10:01:44.285528 Set Vref, RX VrefLevel [Byte0]: 64
8801 10:01:44.288543 [Byte1]: 64
8802 10:01:44.292936
8803 10:01:44.293021 Set Vref, RX VrefLevel [Byte0]: 65
8804 10:01:44.295942 [Byte1]: 65
8805 10:01:44.301018
8806 10:01:44.301125 Set Vref, RX VrefLevel [Byte0]: 66
8807 10:01:44.303688 [Byte1]: 66
8808 10:01:44.308137
8809 10:01:44.308217 Set Vref, RX VrefLevel [Byte0]: 67
8810 10:01:44.312002 [Byte1]: 67
8811 10:01:44.315731
8812 10:01:44.315811 Set Vref, RX VrefLevel [Byte0]: 68
8813 10:01:44.319322 [Byte1]: 68
8814 10:01:44.323014
8815 10:01:44.323095 Set Vref, RX VrefLevel [Byte0]: 69
8816 10:01:44.326225 [Byte1]: 69
8817 10:01:44.330389
8818 10:01:44.330498 Set Vref, RX VrefLevel [Byte0]: 70
8819 10:01:44.334094 [Byte1]: 70
8820 10:01:44.338449
8821 10:01:44.338529 Set Vref, RX VrefLevel [Byte0]: 71
8822 10:01:44.341633 [Byte1]: 71
8823 10:01:44.346134
8824 10:01:44.346214 Set Vref, RX VrefLevel [Byte0]: 72
8825 10:01:44.349607 [Byte1]: 72
8826 10:01:44.353629
8827 10:01:44.353710 Set Vref, RX VrefLevel [Byte0]: 73
8828 10:01:44.356699 [Byte1]: 73
8829 10:01:44.361082
8830 10:01:44.361162 Final RX Vref Byte 0 = 53 to rank0
8831 10:01:44.363989 Final RX Vref Byte 1 = 57 to rank0
8832 10:01:44.367579 Final RX Vref Byte 0 = 53 to rank1
8833 10:01:44.371204 Final RX Vref Byte 1 = 57 to rank1==
8834 10:01:44.374479 Dram Type= 6, Freq= 0, CH_1, rank 0
8835 10:01:44.381185 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8836 10:01:44.381266 ==
8837 10:01:44.381330 DQS Delay:
8838 10:01:44.384066 DQS0 = 0, DQS1 = 0
8839 10:01:44.384146 DQM Delay:
8840 10:01:44.384210 DQM0 = 135, DQM1 = 129
8841 10:01:44.387774 DQ Delay:
8842 10:01:44.390709 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =132
8843 10:01:44.394403 DQ4 =132, DQ5 =148, DQ6 =146, DQ7 =128
8844 10:01:44.397272 DQ8 =116, DQ9 =116, DQ10 =132, DQ11 =118
8845 10:01:44.400570 DQ12 =136, DQ13 =138, DQ14 =138, DQ15 =138
8846 10:01:44.400651
8847 10:01:44.400714
8848 10:01:44.400772
8849 10:01:44.404582 [DramC_TX_OE_Calibration] TA2
8850 10:01:44.407023 Original DQ_B0 (3 6) =30, OEN = 27
8851 10:01:44.410457 Original DQ_B1 (3 6) =30, OEN = 27
8852 10:01:44.413742 24, 0x0, End_B0=24 End_B1=24
8853 10:01:44.416831 25, 0x0, End_B0=25 End_B1=25
8854 10:01:44.416912 26, 0x0, End_B0=26 End_B1=26
8855 10:01:44.420059 27, 0x0, End_B0=27 End_B1=27
8856 10:01:44.423794 28, 0x0, End_B0=28 End_B1=28
8857 10:01:44.427518 29, 0x0, End_B0=29 End_B1=29
8858 10:01:44.427599 30, 0x0, End_B0=30 End_B1=30
8859 10:01:44.430265 31, 0x4141, End_B0=30 End_B1=30
8860 10:01:44.433392 Byte0 end_step=30 best_step=27
8861 10:01:44.437077 Byte1 end_step=30 best_step=27
8862 10:01:44.440204 Byte0 TX OE(2T, 0.5T) = (3, 3)
8863 10:01:44.443451 Byte1 TX OE(2T, 0.5T) = (3, 3)
8864 10:01:44.443531
8865 10:01:44.443594
8866 10:01:44.450083 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
8867 10:01:44.453175 CH1 RK0: MR19=303, MR18=1A10
8868 10:01:44.460329 CH1_RK0: MR19=0x303, MR18=0x1A10, DQSOSC=396, MR23=63, INC=23, DEC=15
8869 10:01:44.460410
8870 10:01:44.463176 ----->DramcWriteLeveling(PI) begin...
8871 10:01:44.463258 ==
8872 10:01:44.466764 Dram Type= 6, Freq= 0, CH_1, rank 1
8873 10:01:44.469610 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8874 10:01:44.469739 ==
8875 10:01:44.472816 Write leveling (Byte 0): 22 => 22
8876 10:01:44.476550 Write leveling (Byte 1): 27 => 27
8877 10:01:44.479679 DramcWriteLeveling(PI) end<-----
8878 10:01:44.479788
8879 10:01:44.479876 ==
8880 10:01:44.482987 Dram Type= 6, Freq= 0, CH_1, rank 1
8881 10:01:44.489812 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8882 10:01:44.489898 ==
8883 10:01:44.489963 [Gating] SW mode calibration
8884 10:01:44.499818 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8885 10:01:44.502335 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8886 10:01:44.508884 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8887 10:01:44.512426 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8888 10:01:44.515797 1 4 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8889 10:01:44.519358 1 4 12 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
8890 10:01:44.525813 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8891 10:01:44.529404 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8892 10:01:44.533180 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8893 10:01:44.539317 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8894 10:01:44.541903 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8895 10:01:44.545353 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8896 10:01:44.552058 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
8897 10:01:44.555212 1 5 12 | B1->B0 | 2323 3434 | 0 1 | (1 0) (1 0)
8898 10:01:44.558408 1 5 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
8899 10:01:44.565372 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8900 10:01:44.568602 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8901 10:01:44.571825 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8902 10:01:44.578489 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8903 10:01:44.582007 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8904 10:01:44.585204 1 6 8 | B1->B0 | 3535 2323 | 0 0 | (0 0) (0 0)
8905 10:01:44.592022 1 6 12 | B1->B0 | 4646 2424 | 0 0 | (0 0) (0 0)
8906 10:01:44.595030 1 6 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8907 10:01:44.598206 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8908 10:01:44.604794 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8909 10:01:44.608075 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8910 10:01:44.611557 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8911 10:01:44.618272 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8912 10:01:44.621708 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8913 10:01:44.624537 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8914 10:01:44.631404 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8915 10:01:44.634752 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8916 10:01:44.638082 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8917 10:01:44.644879 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8918 10:01:44.647824 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8919 10:01:44.651198 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8920 10:01:44.657840 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8921 10:01:44.661387 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8922 10:01:44.664688 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8923 10:01:44.670999 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8924 10:01:44.674060 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8925 10:01:44.677532 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8926 10:01:44.684508 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8927 10:01:44.687725 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8928 10:01:44.690797 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8929 10:01:44.697331 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8930 10:01:44.700994 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8931 10:01:44.703863 Total UI for P1: 0, mck2ui 16
8932 10:01:44.707120 best dqsien dly found for B0: ( 1, 9, 12)
8933 10:01:44.711032 Total UI for P1: 0, mck2ui 16
8934 10:01:44.713665 best dqsien dly found for B1: ( 1, 9, 10)
8935 10:01:44.717786 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8936 10:01:44.720594 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8937 10:01:44.720684
8938 10:01:44.723685 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8939 10:01:44.730441 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8940 10:01:44.730518 [Gating] SW calibration Done
8941 10:01:44.730580 ==
8942 10:01:44.733615 Dram Type= 6, Freq= 0, CH_1, rank 1
8943 10:01:44.740311 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8944 10:01:44.740426 ==
8945 10:01:44.740520 RX Vref Scan: 0
8946 10:01:44.740608
8947 10:01:44.743708 RX Vref 0 -> 0, step: 1
8948 10:01:44.743815
8949 10:01:44.746776 RX Delay 0 -> 252, step: 8
8950 10:01:44.750210 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8951 10:01:44.754030 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8952 10:01:44.756812 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8953 10:01:44.763498 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8954 10:01:44.766625 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8955 10:01:44.770176 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8956 10:01:44.773287 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8957 10:01:44.776210 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8958 10:01:44.783215 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8959 10:01:44.786289 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8960 10:01:44.789374 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8961 10:01:44.794087 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8962 10:01:44.797100 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8963 10:01:44.803097 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8964 10:01:44.805975 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8965 10:01:44.809175 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8966 10:01:44.809277 ==
8967 10:01:44.812799 Dram Type= 6, Freq= 0, CH_1, rank 1
8968 10:01:44.815839 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8969 10:01:44.819469 ==
8970 10:01:44.819650 DQS Delay:
8971 10:01:44.819773 DQS0 = 0, DQS1 = 0
8972 10:01:44.823153 DQM Delay:
8973 10:01:44.823259 DQM0 = 136, DQM1 = 129
8974 10:01:44.825658 DQ Delay:
8975 10:01:44.829246 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8976 10:01:44.832258 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8977 10:01:44.836154 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8978 10:01:44.839115 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8979 10:01:44.839215
8980 10:01:44.839309
8981 10:01:44.839396 ==
8982 10:01:44.842154 Dram Type= 6, Freq= 0, CH_1, rank 1
8983 10:01:44.845693 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8984 10:01:44.845765 ==
8985 10:01:44.848705
8986 10:01:44.848777
8987 10:01:44.848844 TX Vref Scan disable
8988 10:01:44.852167 == TX Byte 0 ==
8989 10:01:44.855373 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8990 10:01:44.858841 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8991 10:01:44.862358 == TX Byte 1 ==
8992 10:01:44.865261 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8993 10:01:44.868885 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8994 10:01:44.871908 ==
8995 10:01:44.872010 Dram Type= 6, Freq= 0, CH_1, rank 1
8996 10:01:44.878380 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8997 10:01:44.878455 ==
8998 10:01:44.891824
8999 10:01:44.895574 TX Vref early break, caculate TX vref
9000 10:01:44.898628 TX Vref=16, minBit 0, minWin=22, winSum=377
9001 10:01:44.902380 TX Vref=18, minBit 5, minWin=22, winSum=388
9002 10:01:44.905626 TX Vref=20, minBit 5, minWin=23, winSum=396
9003 10:01:44.909447 TX Vref=22, minBit 5, minWin=23, winSum=402
9004 10:01:44.911761 TX Vref=24, minBit 5, minWin=23, winSum=407
9005 10:01:44.918279 TX Vref=26, minBit 0, minWin=24, winSum=415
9006 10:01:44.922008 TX Vref=28, minBit 0, minWin=23, winSum=414
9007 10:01:44.925054 TX Vref=30, minBit 0, minWin=23, winSum=410
9008 10:01:44.928307 TX Vref=32, minBit 0, minWin=23, winSum=404
9009 10:01:44.931882 TX Vref=34, minBit 0, minWin=21, winSum=395
9010 10:01:44.938419 TX Vref=36, minBit 0, minWin=21, winSum=384
9011 10:01:44.941197 [TxChooseVref] Worse bit 0, Min win 24, Win sum 415, Final Vref 26
9012 10:01:44.941305
9013 10:01:44.944877 Final TX Range 0 Vref 26
9014 10:01:44.944966
9015 10:01:44.945059 ==
9016 10:01:44.948167 Dram Type= 6, Freq= 0, CH_1, rank 1
9017 10:01:44.951240 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9018 10:01:44.954433 ==
9019 10:01:44.954511
9020 10:01:44.954574
9021 10:01:44.954632 TX Vref Scan disable
9022 10:01:44.961133 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
9023 10:01:44.961204 == TX Byte 0 ==
9024 10:01:44.964485 u2DelayCellOfst[0]=18 cells (5 PI)
9025 10:01:44.967781 u2DelayCellOfst[1]=14 cells (4 PI)
9026 10:01:44.970815 u2DelayCellOfst[2]=0 cells (0 PI)
9027 10:01:44.974401 u2DelayCellOfst[3]=7 cells (2 PI)
9028 10:01:44.977704 u2DelayCellOfst[4]=11 cells (3 PI)
9029 10:01:44.981176 u2DelayCellOfst[5]=22 cells (6 PI)
9030 10:01:44.984033 u2DelayCellOfst[6]=18 cells (5 PI)
9031 10:01:44.987653 u2DelayCellOfst[7]=7 cells (2 PI)
9032 10:01:44.990984 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
9033 10:01:44.994084 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
9034 10:01:44.997390 == TX Byte 1 ==
9035 10:01:45.000845 u2DelayCellOfst[8]=0 cells (0 PI)
9036 10:01:45.004197 u2DelayCellOfst[9]=7 cells (2 PI)
9037 10:01:45.007453 u2DelayCellOfst[10]=11 cells (3 PI)
9038 10:01:45.011264 u2DelayCellOfst[11]=3 cells (1 PI)
9039 10:01:45.014037 u2DelayCellOfst[12]=14 cells (4 PI)
9040 10:01:45.014118 u2DelayCellOfst[13]=18 cells (5 PI)
9041 10:01:45.017278 u2DelayCellOfst[14]=18 cells (5 PI)
9042 10:01:45.020981 u2DelayCellOfst[15]=18 cells (5 PI)
9043 10:01:45.027511 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9044 10:01:45.031637 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9045 10:01:45.033854 DramC Write-DBI on
9046 10:01:45.033934 ==
9047 10:01:45.037365 Dram Type= 6, Freq= 0, CH_1, rank 1
9048 10:01:45.040289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9049 10:01:45.040369 ==
9050 10:01:45.040433
9051 10:01:45.040491
9052 10:01:45.044306 TX Vref Scan disable
9053 10:01:45.044387 == TX Byte 0 ==
9054 10:01:45.050443 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
9055 10:01:45.050524 == TX Byte 1 ==
9056 10:01:45.054141 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9057 10:01:45.056814 DramC Write-DBI off
9058 10:01:45.056918
9059 10:01:45.057013 [DATLAT]
9060 10:01:45.060334 Freq=1600, CH1 RK1
9061 10:01:45.060440
9062 10:01:45.060534 DATLAT Default: 0xf
9063 10:01:45.064507 0, 0xFFFF, sum = 0
9064 10:01:45.064589 1, 0xFFFF, sum = 0
9065 10:01:45.066956 2, 0xFFFF, sum = 0
9066 10:01:45.070631 3, 0xFFFF, sum = 0
9067 10:01:45.070712 4, 0xFFFF, sum = 0
9068 10:01:45.073697 5, 0xFFFF, sum = 0
9069 10:01:45.073779 6, 0xFFFF, sum = 0
9070 10:01:45.076492 7, 0xFFFF, sum = 0
9071 10:01:45.076572 8, 0xFFFF, sum = 0
9072 10:01:45.080083 9, 0xFFFF, sum = 0
9073 10:01:45.080164 10, 0xFFFF, sum = 0
9074 10:01:45.083394 11, 0xFFFF, sum = 0
9075 10:01:45.083507 12, 0xFFFF, sum = 0
9076 10:01:45.086963 13, 0xFFFF, sum = 0
9077 10:01:45.087078 14, 0x0, sum = 1
9078 10:01:45.090782 15, 0x0, sum = 2
9079 10:01:45.090875 16, 0x0, sum = 3
9080 10:01:45.093383 17, 0x0, sum = 4
9081 10:01:45.093505 best_step = 15
9082 10:01:45.093570
9083 10:01:45.093629 ==
9084 10:01:45.096287 Dram Type= 6, Freq= 0, CH_1, rank 1
9085 10:01:45.102674 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9086 10:01:45.102779 ==
9087 10:01:45.102875 RX Vref Scan: 0
9088 10:01:45.102965
9089 10:01:45.106225 RX Vref 0 -> 0, step: 1
9090 10:01:45.106328
9091 10:01:45.110158 RX Delay 11 -> 252, step: 4
9092 10:01:45.113162 iDelay=203, Bit 0, Center 140 (87 ~ 194) 108
9093 10:01:45.116647 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9094 10:01:45.119249 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9095 10:01:45.125956 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9096 10:01:45.129649 iDelay=203, Bit 4, Center 132 (75 ~ 190) 116
9097 10:01:45.132829 iDelay=203, Bit 5, Center 142 (91 ~ 194) 104
9098 10:01:45.136076 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9099 10:01:45.139643 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9100 10:01:45.145846 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9101 10:01:45.149264 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9102 10:01:45.152896 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9103 10:01:45.155615 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9104 10:01:45.162612 iDelay=203, Bit 12, Center 134 (79 ~ 190) 112
9105 10:01:45.165660 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9106 10:01:45.168807 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9107 10:01:45.172885 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9108 10:01:45.172966 ==
9109 10:01:45.175376 Dram Type= 6, Freq= 0, CH_1, rank 1
9110 10:01:45.182645 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9111 10:01:45.182731 ==
9112 10:01:45.182796 DQS Delay:
9113 10:01:45.185937 DQS0 = 0, DQS1 = 0
9114 10:01:45.186017 DQM Delay:
9115 10:01:45.186081 DQM0 = 133, DQM1 = 126
9116 10:01:45.188539 DQ Delay:
9117 10:01:45.191809 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
9118 10:01:45.195797 DQ4 =132, DQ5 =142, DQ6 =146, DQ7 =130
9119 10:01:45.198762 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =116
9120 10:01:45.202631 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =138
9121 10:01:45.202710
9122 10:01:45.202773
9123 10:01:45.202830
9124 10:01:45.205092 [DramC_TX_OE_Calibration] TA2
9125 10:01:45.208254 Original DQ_B0 (3 6) =30, OEN = 27
9126 10:01:45.211512 Original DQ_B1 (3 6) =30, OEN = 27
9127 10:01:45.214984 24, 0x0, End_B0=24 End_B1=24
9128 10:01:45.218757 25, 0x0, End_B0=25 End_B1=25
9129 10:01:45.218838 26, 0x0, End_B0=26 End_B1=26
9130 10:01:45.221787 27, 0x0, End_B0=27 End_B1=27
9131 10:01:45.225249 28, 0x0, End_B0=28 End_B1=28
9132 10:01:45.228516 29, 0x0, End_B0=29 End_B1=29
9133 10:01:45.228597 30, 0x0, End_B0=30 End_B1=30
9134 10:01:45.231426 31, 0x4141, End_B0=30 End_B1=30
9135 10:01:45.234851 Byte0 end_step=30 best_step=27
9136 10:01:45.237932 Byte1 end_step=30 best_step=27
9137 10:01:45.241215 Byte0 TX OE(2T, 0.5T) = (3, 3)
9138 10:01:45.244551 Byte1 TX OE(2T, 0.5T) = (3, 3)
9139 10:01:45.244622
9140 10:01:45.244684
9141 10:01:45.251441 [DQSOSCAuto] RK1, (LSB)MR18= 0xf0b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
9142 10:01:45.254864 CH1 RK1: MR19=303, MR18=F0B
9143 10:01:45.261639 CH1_RK1: MR19=0x303, MR18=0xF0B, DQSOSC=402, MR23=63, INC=22, DEC=15
9144 10:01:45.264536 [RxdqsGatingPostProcess] freq 1600
9145 10:01:45.267967 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9146 10:01:45.271183 best DQS0 dly(2T, 0.5T) = (1, 1)
9147 10:01:45.274562 best DQS1 dly(2T, 0.5T) = (1, 1)
9148 10:01:45.278141 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9149 10:01:45.281258 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9150 10:01:45.284499 best DQS0 dly(2T, 0.5T) = (1, 1)
9151 10:01:45.288196 best DQS1 dly(2T, 0.5T) = (1, 1)
9152 10:01:45.291043 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9153 10:01:45.294590 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9154 10:01:45.297646 Pre-setting of DQS Precalculation
9155 10:01:45.300833 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9156 10:01:45.307265 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9157 10:01:45.317683 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9158 10:01:45.317793
9159 10:01:45.317874
9160 10:01:45.320572 [Calibration Summary] 3200 Mbps
9161 10:01:45.320674 CH 0, Rank 0
9162 10:01:45.324156 SW Impedance : PASS
9163 10:01:45.324263 DUTY Scan : NO K
9164 10:01:45.327713 ZQ Calibration : PASS
9165 10:01:45.330901 Jitter Meter : NO K
9166 10:01:45.331006 CBT Training : PASS
9167 10:01:45.333786 Write leveling : PASS
9168 10:01:45.336951 RX DQS gating : PASS
9169 10:01:45.337052 RX DQ/DQS(RDDQC) : PASS
9170 10:01:45.340346 TX DQ/DQS : PASS
9171 10:01:45.343952 RX DATLAT : PASS
9172 10:01:45.344062 RX DQ/DQS(Engine): PASS
9173 10:01:45.347321 TX OE : PASS
9174 10:01:45.347427 All Pass.
9175 10:01:45.347523
9176 10:01:45.350613 CH 0, Rank 1
9177 10:01:45.350686 SW Impedance : PASS
9178 10:01:45.353927 DUTY Scan : NO K
9179 10:01:45.356718 ZQ Calibration : PASS
9180 10:01:45.356830 Jitter Meter : NO K
9181 10:01:45.360509 CBT Training : PASS
9182 10:01:45.360610 Write leveling : PASS
9183 10:01:45.363674 RX DQS gating : PASS
9184 10:01:45.366890 RX DQ/DQS(RDDQC) : PASS
9185 10:01:45.366996 TX DQ/DQS : PASS
9186 10:01:45.370126 RX DATLAT : PASS
9187 10:01:45.373303 RX DQ/DQS(Engine): PASS
9188 10:01:45.373454 TX OE : PASS
9189 10:01:45.376830 All Pass.
9190 10:01:45.376952
9191 10:01:45.377065 CH 1, Rank 0
9192 10:01:45.380269 SW Impedance : PASS
9193 10:01:45.380373 DUTY Scan : NO K
9194 10:01:45.383609 ZQ Calibration : PASS
9195 10:01:45.386912 Jitter Meter : NO K
9196 10:01:45.387012 CBT Training : PASS
9197 10:01:45.390302 Write leveling : PASS
9198 10:01:45.393136 RX DQS gating : PASS
9199 10:01:45.393236 RX DQ/DQS(RDDQC) : PASS
9200 10:01:45.397240 TX DQ/DQS : PASS
9201 10:01:45.399568 RX DATLAT : PASS
9202 10:01:45.399665 RX DQ/DQS(Engine): PASS
9203 10:01:45.403104 TX OE : PASS
9204 10:01:45.403239 All Pass.
9205 10:01:45.403362
9206 10:01:45.406514 CH 1, Rank 1
9207 10:01:45.406619 SW Impedance : PASS
9208 10:01:45.409695 DUTY Scan : NO K
9209 10:01:45.413021 ZQ Calibration : PASS
9210 10:01:45.413125 Jitter Meter : NO K
9211 10:01:45.416893 CBT Training : PASS
9212 10:01:45.420107 Write leveling : PASS
9213 10:01:45.420214 RX DQS gating : PASS
9214 10:01:45.422736 RX DQ/DQS(RDDQC) : PASS
9215 10:01:45.426358 TX DQ/DQS : PASS
9216 10:01:45.426467 RX DATLAT : PASS
9217 10:01:45.429735 RX DQ/DQS(Engine): PASS
9218 10:01:45.429810 TX OE : PASS
9219 10:01:45.432674 All Pass.
9220 10:01:45.432745
9221 10:01:45.432813 DramC Write-DBI on
9222 10:01:45.436283 PER_BANK_REFRESH: Hybrid Mode
9223 10:01:45.439138 TX_TRACKING: ON
9224 10:01:45.446282 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9225 10:01:45.456104 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9226 10:01:45.462823 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9227 10:01:45.465677 [FAST_K] Save calibration result to emmc
9228 10:01:45.469015 sync common calibartion params.
9229 10:01:45.472527 sync cbt_mode0:1, 1:1
9230 10:01:45.472605 dram_init: ddr_geometry: 2
9231 10:01:45.475544 dram_init: ddr_geometry: 2
9232 10:01:45.478746 dram_init: ddr_geometry: 2
9233 10:01:45.478844 0:dram_rank_size:100000000
9234 10:01:45.482158 1:dram_rank_size:100000000
9235 10:01:45.488863 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9236 10:01:45.492628 DFS_SHUFFLE_HW_MODE: ON
9237 10:01:45.495106 dramc_set_vcore_voltage set vcore to 725000
9238 10:01:45.495194 Read voltage for 1600, 0
9239 10:01:45.498413 Vio18 = 0
9240 10:01:45.498507 Vcore = 725000
9241 10:01:45.498581 Vdram = 0
9242 10:01:45.502127 Vddq = 0
9243 10:01:45.502221 Vmddr = 0
9244 10:01:45.505160 switch to 3200 Mbps bootup
9245 10:01:45.505261 [DramcRunTimeConfig]
9246 10:01:45.508387 PHYPLL
9247 10:01:45.508496 DPM_CONTROL_AFTERK: ON
9248 10:01:45.511742 PER_BANK_REFRESH: ON
9249 10:01:45.514850 REFRESH_OVERHEAD_REDUCTION: ON
9250 10:01:45.514972 CMD_PICG_NEW_MODE: OFF
9251 10:01:45.518127 XRTWTW_NEW_MODE: ON
9252 10:01:45.518248 XRTRTR_NEW_MODE: ON
9253 10:01:45.521378 TX_TRACKING: ON
9254 10:01:45.521481 RDSEL_TRACKING: OFF
9255 10:01:45.524542 DQS Precalculation for DVFS: ON
9256 10:01:45.527959 RX_TRACKING: OFF
9257 10:01:45.528041 HW_GATING DBG: ON
9258 10:01:45.531897 ZQCS_ENABLE_LP4: ON
9259 10:01:45.531978 RX_PICG_NEW_MODE: ON
9260 10:01:45.534362 TX_PICG_NEW_MODE: ON
9261 10:01:45.534444 ENABLE_RX_DCM_DPHY: ON
9262 10:01:45.537685 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9263 10:01:45.540811 DUMMY_READ_FOR_TRACKING: OFF
9264 10:01:45.544257 !!! SPM_CONTROL_AFTERK: OFF
9265 10:01:45.547506 !!! SPM could not control APHY
9266 10:01:45.547588 IMPEDANCE_TRACKING: ON
9267 10:01:45.551156 TEMP_SENSOR: ON
9268 10:01:45.551238 HW_SAVE_FOR_SR: OFF
9269 10:01:45.554426 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9270 10:01:45.557770 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9271 10:01:45.560977 Read ODT Tracking: ON
9272 10:01:45.564329 Refresh Rate DeBounce: ON
9273 10:01:45.564410 DFS_NO_QUEUE_FLUSH: ON
9274 10:01:45.567556 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9275 10:01:45.571123 ENABLE_DFS_RUNTIME_MRW: OFF
9276 10:01:45.574618 DDR_RESERVE_NEW_MODE: ON
9277 10:01:45.574700 MR_CBT_SWITCH_FREQ: ON
9278 10:01:45.577921 =========================
9279 10:01:45.596875 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9280 10:01:45.599811 dram_init: ddr_geometry: 2
9281 10:01:45.618111 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9282 10:01:45.621405 dram_init: dram init end (result: 0)
9283 10:01:45.628336 DRAM-K: Full calibration passed in 24675 msecs
9284 10:01:45.631279 MRC: failed to locate region type 0.
9285 10:01:45.631361 DRAM rank0 size:0x100000000,
9286 10:01:45.634790 DRAM rank1 size=0x100000000
9287 10:01:45.644393 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9288 10:01:45.650868 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9289 10:01:45.657552 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9290 10:01:45.667876 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9291 10:01:45.667983 DRAM rank0 size:0x100000000,
9292 10:01:45.670551 DRAM rank1 size=0x100000000
9293 10:01:45.670688 CBMEM:
9294 10:01:45.674135 IMD: root @ 0xfffff000 254 entries.
9295 10:01:45.677686 IMD: root @ 0xffffec00 62 entries.
9296 10:01:45.681114 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9297 10:01:45.687108 WARNING: RO_VPD is uninitialized or empty.
9298 10:01:45.690514 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9299 10:01:45.698040 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9300 10:01:45.711115 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9301 10:01:45.722163 BS: romstage times (exec / console): total (unknown) / 24161 ms
9302 10:01:45.722267
9303 10:01:45.722362
9304 10:01:45.732236 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9305 10:01:45.735281 ARM64: Exception handlers installed.
9306 10:01:45.738683 ARM64: Testing exception
9307 10:01:45.742738 ARM64: Done test exception
9308 10:01:45.742821 Enumerating buses...
9309 10:01:45.745684 Show all devs... Before device enumeration.
9310 10:01:45.748859 Root Device: enabled 1
9311 10:01:45.752192 CPU_CLUSTER: 0: enabled 1
9312 10:01:45.752329 CPU: 00: enabled 1
9313 10:01:45.755437 Compare with tree...
9314 10:01:45.755572 Root Device: enabled 1
9315 10:01:45.758813 CPU_CLUSTER: 0: enabled 1
9316 10:01:45.762390 CPU: 00: enabled 1
9317 10:01:45.762541 Root Device scanning...
9318 10:01:45.765666 scan_static_bus for Root Device
9319 10:01:45.768545 CPU_CLUSTER: 0 enabled
9320 10:01:45.771473 scan_static_bus for Root Device done
9321 10:01:45.775520 scan_bus: bus Root Device finished in 8 msecs
9322 10:01:45.775721 done
9323 10:01:45.782107 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9324 10:01:45.784871 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9325 10:01:45.791711 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9326 10:01:45.798117 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9327 10:01:45.798506 Allocating resources...
9328 10:01:45.801570 Reading resources...
9329 10:01:45.805070 Root Device read_resources bus 0 link: 0
9330 10:01:45.808953 DRAM rank0 size:0x100000000,
9331 10:01:45.809520 DRAM rank1 size=0x100000000
9332 10:01:45.814526 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9333 10:01:45.815115 CPU: 00 missing read_resources
9334 10:01:45.821313 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9335 10:01:45.824447 Root Device read_resources bus 0 link: 0 done
9336 10:01:45.828170 Done reading resources.
9337 10:01:45.831584 Show resources in subtree (Root Device)...After reading.
9338 10:01:45.834273 Root Device child on link 0 CPU_CLUSTER: 0
9339 10:01:45.838421 CPU_CLUSTER: 0 child on link 0 CPU: 00
9340 10:01:45.847570 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9341 10:01:45.848048 CPU: 00
9342 10:01:45.854092 Root Device assign_resources, bus 0 link: 0
9343 10:01:45.857517 CPU_CLUSTER: 0 missing set_resources
9344 10:01:45.861220 Root Device assign_resources, bus 0 link: 0 done
9345 10:01:45.864121 Done setting resources.
9346 10:01:45.867203 Show resources in subtree (Root Device)...After assigning values.
9347 10:01:45.871008 Root Device child on link 0 CPU_CLUSTER: 0
9348 10:01:45.877148 CPU_CLUSTER: 0 child on link 0 CPU: 00
9349 10:01:45.883709 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9350 10:01:45.887256 CPU: 00
9351 10:01:45.887532 Done allocating resources.
9352 10:01:45.893282 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9353 10:01:45.893494 Enabling resources...
9354 10:01:45.896990 done.
9355 10:01:45.899889 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9356 10:01:45.904130 Initializing devices...
9357 10:01:45.904252 Root Device init
9358 10:01:45.906878 init hardware done!
9359 10:01:45.906995 0x00000018: ctrlr->caps
9360 10:01:45.910172 52.000 MHz: ctrlr->f_max
9361 10:01:45.913312 0.400 MHz: ctrlr->f_min
9362 10:01:45.913469 0x40ff8080: ctrlr->voltages
9363 10:01:45.917498 sclk: 390625
9364 10:01:45.917610 Bus Width = 1
9365 10:01:45.920138 sclk: 390625
9366 10:01:45.920257 Bus Width = 1
9367 10:01:45.923319 Early init status = 3
9368 10:01:45.926653 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9369 10:01:45.930105 in-header: 03 fc 00 00 01 00 00 00
9370 10:01:45.933276 in-data: 00
9371 10:01:45.936366 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9372 10:01:45.942790 in-header: 03 fd 00 00 00 00 00 00
9373 10:01:45.946106 in-data:
9374 10:01:45.949937 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9375 10:01:45.953273 in-header: 03 fc 00 00 01 00 00 00
9376 10:01:45.956565 in-data: 00
9377 10:01:45.959626 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9378 10:01:45.964831 in-header: 03 fd 00 00 00 00 00 00
9379 10:01:45.968215 in-data:
9380 10:01:45.971599 [SSUSB] Setting up USB HOST controller...
9381 10:01:45.974885 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9382 10:01:45.978642 [SSUSB] phy power-on done.
9383 10:01:45.981735 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9384 10:01:45.988197 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9385 10:01:45.991417 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9386 10:01:45.998094 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9387 10:01:46.004848 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9388 10:01:46.011735 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9389 10:01:46.018325 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9390 10:01:46.024578 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9391 10:01:46.027749 SPM: binary array size = 0x9dc
9392 10:01:46.031475 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9393 10:01:46.038052 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9394 10:01:46.044780 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9395 10:01:46.051194 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9396 10:01:46.054241 configure_display: Starting display init
9397 10:01:46.088370 anx7625_power_on_init: Init interface.
9398 10:01:46.091509 anx7625_disable_pd_protocol: Disabled PD feature.
9399 10:01:46.095154 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9400 10:01:46.123726 anx7625_start_dp_work: Secure OCM version=00
9401 10:01:46.125855 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9402 10:01:46.141176 sp_tx_get_edid_block: EDID Block = 1
9403 10:01:46.243349 Extracted contents:
9404 10:01:46.246915 header: 00 ff ff ff ff ff ff 00
9405 10:01:46.249776 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9406 10:01:46.253288 version: 01 04
9407 10:01:46.256411 basic params: 95 1f 11 78 0a
9408 10:01:46.260440 chroma info: 76 90 94 55 54 90 27 21 50 54
9409 10:01:46.263606 established: 00 00 00
9410 10:01:46.269628 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9411 10:01:46.273161 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9412 10:01:46.279506 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9413 10:01:46.286041 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9414 10:01:46.292576 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9415 10:01:46.296087 extensions: 00
9416 10:01:46.296171 checksum: fb
9417 10:01:46.296256
9418 10:01:46.299664 Manufacturer: IVO Model 57d Serial Number 0
9419 10:01:46.303495 Made week 0 of 2020
9420 10:01:46.305837 EDID version: 1.4
9421 10:01:46.305920 Digital display
9422 10:01:46.309233 6 bits per primary color channel
9423 10:01:46.309318 DisplayPort interface
9424 10:01:46.313267 Maximum image size: 31 cm x 17 cm
9425 10:01:46.315777 Gamma: 220%
9426 10:01:46.315861 Check DPMS levels
9427 10:01:46.319658 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9428 10:01:46.325957 First detailed timing is preferred timing
9429 10:01:46.326042 Established timings supported:
9430 10:01:46.329646 Standard timings supported:
9431 10:01:46.332443 Detailed timings
9432 10:01:46.335828 Hex of detail: 383680a07038204018303c0035ae10000019
9433 10:01:46.342326 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9434 10:01:46.345941 0780 0798 07c8 0820 hborder 0
9435 10:01:46.349350 0438 043b 0447 0458 vborder 0
9436 10:01:46.353093 -hsync -vsync
9437 10:01:46.353178 Did detailed timing
9438 10:01:46.359579 Hex of detail: 000000000000000000000000000000000000
9439 10:01:46.362342 Manufacturer-specified data, tag 0
9440 10:01:46.365994 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9441 10:01:46.369738 ASCII string: InfoVision
9442 10:01:46.372183 Hex of detail: 000000fe00523134304e574635205248200a
9443 10:01:46.375541 ASCII string: R140NWF5 RH
9444 10:01:46.375625 Checksum
9445 10:01:46.379159 Checksum: 0xfb (valid)
9446 10:01:46.382124 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9447 10:01:46.385438 DSI data_rate: 832800000 bps
9448 10:01:46.392268 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9449 10:01:46.395388 anx7625_parse_edid: pixelclock(138800).
9450 10:01:46.399012 hactive(1920), hsync(48), hfp(24), hbp(88)
9451 10:01:46.401775 vactive(1080), vsync(12), vfp(3), vbp(17)
9452 10:01:46.405253 anx7625_dsi_config: config dsi.
9453 10:01:46.412464 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9454 10:01:46.425417 anx7625_dsi_config: success to config DSI
9455 10:01:46.428817 anx7625_dp_start: MIPI phy setup OK.
9456 10:01:46.431887 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9457 10:01:46.435143 mtk_ddp_mode_set invalid vrefresh 60
9458 10:01:46.438709 main_disp_path_setup
9459 10:01:46.438864 ovl_layer_smi_id_en
9460 10:01:46.441944 ovl_layer_smi_id_en
9461 10:01:46.442099 ccorr_config
9462 10:01:46.442258 aal_config
9463 10:01:46.445246 gamma_config
9464 10:01:46.445485 postmask_config
9465 10:01:46.448953 dither_config
9466 10:01:46.452460 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9467 10:01:46.458646 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9468 10:01:46.462024 Root Device init finished in 554 msecs
9469 10:01:46.465501 CPU_CLUSTER: 0 init
9470 10:01:46.471712 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9471 10:01:46.478428 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9472 10:01:46.478811 APU_MBOX 0x190000b0 = 0x10001
9473 10:01:46.481698 APU_MBOX 0x190001b0 = 0x10001
9474 10:01:46.485036 APU_MBOX 0x190005b0 = 0x10001
9475 10:01:46.489007 APU_MBOX 0x190006b0 = 0x10001
9476 10:01:46.494748 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9477 10:01:46.504366 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9478 10:01:46.516786 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9479 10:01:46.523532 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9480 10:01:46.534963 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9481 10:01:46.544050 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9482 10:01:46.547474 CPU_CLUSTER: 0 init finished in 81 msecs
9483 10:01:46.550691 Devices initialized
9484 10:01:46.553981 Show all devs... After init.
9485 10:01:46.554063 Root Device: enabled 1
9486 10:01:46.557974 CPU_CLUSTER: 0: enabled 1
9487 10:01:46.560526 CPU: 00: enabled 1
9488 10:01:46.564017 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9489 10:01:46.567054 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9490 10:01:46.570397 ELOG: NV offset 0x57f000 size 0x1000
9491 10:01:46.577293 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9492 10:01:46.584505 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9493 10:01:46.587154 ELOG: Event(17) added with size 13 at 2023-11-24 10:01:48 UTC
9494 10:01:46.593505 out: cmd=0x121: 03 db 21 01 00 00 00 00
9495 10:01:46.597205 in-header: 03 92 00 00 2c 00 00 00
9496 10:01:46.609856 in-data: cd 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9497 10:01:46.613679 ELOG: Event(A1) added with size 10 at 2023-11-24 10:01:48 UTC
9498 10:01:46.619965 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9499 10:01:46.626652 ELOG: Event(A0) added with size 9 at 2023-11-24 10:01:48 UTC
9500 10:01:46.630044 elog_add_boot_reason: Logged dev mode boot
9501 10:01:46.636445 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9502 10:01:46.636521 Finalize devices...
9503 10:01:46.640389 Devices finalized
9504 10:01:46.643642 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9505 10:01:46.646561 Writing coreboot table at 0xffe64000
9506 10:01:46.650058 0. 000000000010a000-0000000000113fff: RAMSTAGE
9507 10:01:46.656712 1. 0000000040000000-00000000400fffff: RAM
9508 10:01:46.659667 2. 0000000040100000-000000004032afff: RAMSTAGE
9509 10:01:46.663057 3. 000000004032b000-00000000545fffff: RAM
9510 10:01:46.666594 4. 0000000054600000-000000005465ffff: BL31
9511 10:01:46.669688 5. 0000000054660000-00000000ffe63fff: RAM
9512 10:01:46.676119 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9513 10:01:46.679334 7. 0000000100000000-000000023fffffff: RAM
9514 10:01:46.682856 Passing 5 GPIOs to payload:
9515 10:01:46.685924 NAME | PORT | POLARITY | VALUE
9516 10:01:46.692745 EC in RW | 0x000000aa | low | undefined
9517 10:01:46.696560 EC interrupt | 0x00000005 | low | undefined
9518 10:01:46.702838 TPM interrupt | 0x000000ab | high | undefined
9519 10:01:46.706605 SD card detect | 0x00000011 | high | undefined
9520 10:01:46.709360 speaker enable | 0x00000093 | high | undefined
9521 10:01:46.712501 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9522 10:01:46.716520 in-header: 03 f9 00 00 02 00 00 00
9523 10:01:46.719296 in-data: 02 00
9524 10:01:46.722741 ADC[4]: Raw value=901552 ID=7
9525 10:01:46.725906 ADC[3]: Raw value=213282 ID=1
9526 10:01:46.725987 RAM Code: 0x71
9527 10:01:46.729533 ADC[6]: Raw value=75036 ID=0
9528 10:01:46.732516 ADC[5]: Raw value=212912 ID=1
9529 10:01:46.732589 SKU Code: 0x1
9530 10:01:46.739081 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a1a9
9531 10:01:46.739156 coreboot table: 964 bytes.
9532 10:01:46.742428 IMD ROOT 0. 0xfffff000 0x00001000
9533 10:01:46.745372 IMD SMALL 1. 0xffffe000 0x00001000
9534 10:01:46.749142 RO MCACHE 2. 0xffffc000 0x00001104
9535 10:01:46.752355 CONSOLE 3. 0xfff7c000 0x00080000
9536 10:01:46.755673 FMAP 4. 0xfff7b000 0x00000452
9537 10:01:46.759134 TIME STAMP 5. 0xfff7a000 0x00000910
9538 10:01:46.761829 VBOOT WORK 6. 0xfff66000 0x00014000
9539 10:01:46.765143 RAMOOPS 7. 0xffe66000 0x00100000
9540 10:01:46.769217 COREBOOT 8. 0xffe64000 0x00002000
9541 10:01:46.772374 IMD small region:
9542 10:01:46.775410 IMD ROOT 0. 0xffffec00 0x00000400
9543 10:01:46.778557 VPD 1. 0xffffeb80 0x0000006c
9544 10:01:46.781869 MMC STATUS 2. 0xffffeb60 0x00000004
9545 10:01:46.788520 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9546 10:01:46.788602 Probing TPM: done!
9547 10:01:46.795939 Connected to device vid:did:rid of 1ae0:0028:00
9548 10:01:46.802125 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9549 10:01:46.805572 Initialized TPM device CR50 revision 0
9550 10:01:46.808729 Checking cr50 for pending updates
9551 10:01:46.814686 Reading cr50 TPM mode
9552 10:01:46.823461 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9553 10:01:46.830117 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9554 10:01:46.869658 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9555 10:01:46.873229 Checking segment from ROM address 0x40100000
9556 10:01:46.876854 Checking segment from ROM address 0x4010001c
9557 10:01:46.883274 Loading segment from ROM address 0x40100000
9558 10:01:46.883689 code (compression=0)
9559 10:01:46.893117 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9560 10:01:46.899712 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9561 10:01:46.900182 it's not compressed!
9562 10:01:46.906303 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9563 10:01:46.913282 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9564 10:01:46.930675 Loading segment from ROM address 0x4010001c
9565 10:01:46.931127 Entry Point 0x80000000
9566 10:01:46.933282 Loaded segments
9567 10:01:46.936904 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9568 10:01:46.943295 Jumping to boot code at 0x80000000(0xffe64000)
9569 10:01:46.950236 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9570 10:01:46.956771 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9571 10:01:46.964612 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9572 10:01:46.968026 Checking segment from ROM address 0x40100000
9573 10:01:46.971462 Checking segment from ROM address 0x4010001c
9574 10:01:46.978426 Loading segment from ROM address 0x40100000
9575 10:01:46.978853 code (compression=1)
9576 10:01:46.984420 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9577 10:01:46.994662 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9578 10:01:46.995087 using LZMA
9579 10:01:47.003046 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9580 10:01:47.009397 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9581 10:01:47.012769 Loading segment from ROM address 0x4010001c
9582 10:01:47.013303 Entry Point 0x54601000
9583 10:01:47.016039 Loaded segments
9584 10:01:47.019214 NOTICE: MT8192 bl31_setup
9585 10:01:47.026781 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9586 10:01:47.030143 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9587 10:01:47.033068 WARNING: region 0:
9588 10:01:47.036753 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9589 10:01:47.037299 WARNING: region 1:
9590 10:01:47.043300 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9591 10:01:47.046417 WARNING: region 2:
9592 10:01:47.049393 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9593 10:01:47.052691 WARNING: region 3:
9594 10:01:47.056106 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9595 10:01:47.060347 WARNING: region 4:
9596 10:01:47.066211 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9597 10:01:47.066676 WARNING: region 5:
9598 10:01:47.069785 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9599 10:01:47.073036 WARNING: region 6:
9600 10:01:47.076588 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9601 10:01:47.079478 WARNING: region 7:
9602 10:01:47.082817 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9603 10:01:47.089362 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9604 10:01:47.092798 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9605 10:01:47.099271 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9606 10:01:47.102579 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9607 10:01:47.105970 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9608 10:01:47.112486 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9609 10:01:47.115574 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9610 10:01:47.119418 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9611 10:01:47.126066 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9612 10:01:47.129228 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9613 10:01:47.135308 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9614 10:01:47.139075 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9615 10:01:47.142762 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9616 10:01:47.148839 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9617 10:01:47.151958 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9618 10:01:47.155220 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9619 10:01:47.162080 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9620 10:01:47.165355 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9621 10:01:47.172097 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9622 10:01:47.175256 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9623 10:01:47.179242 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9624 10:01:47.185267 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9625 10:01:47.188316 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9626 10:01:47.191887 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9627 10:01:47.198661 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9628 10:01:47.201347 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9629 10:01:47.208306 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9630 10:01:47.211473 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9631 10:01:47.218263 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9632 10:01:47.221392 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9633 10:01:47.224641 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9634 10:01:47.231339 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9635 10:01:47.234847 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9636 10:01:47.237808 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9637 10:01:47.241445 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9638 10:01:47.247798 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9639 10:01:47.251151 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9640 10:01:47.254935 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9641 10:01:47.260970 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9642 10:01:47.264442 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9643 10:01:47.267930 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9644 10:01:47.271414 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9645 10:01:47.277954 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9646 10:01:47.281366 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9647 10:01:47.284642 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9648 10:01:47.287547 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9649 10:01:47.294906 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9650 10:01:47.297939 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9651 10:01:47.301137 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9652 10:01:47.308017 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9653 10:01:47.311553 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9654 10:01:47.317688 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9655 10:01:47.321139 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9656 10:01:47.324596 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9657 10:01:47.330926 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9658 10:01:47.334494 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9659 10:01:47.340972 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9660 10:01:47.344576 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9661 10:01:47.351215 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9662 10:01:47.354546 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9663 10:01:47.360768 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9664 10:01:47.364047 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9665 10:01:47.367459 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9666 10:01:47.374656 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9667 10:01:47.377336 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9668 10:01:47.384761 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9669 10:01:47.387403 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9670 10:01:47.393761 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9671 10:01:47.397003 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9672 10:01:47.403652 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9673 10:01:47.407066 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9674 10:01:47.410325 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9675 10:01:47.417224 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9676 10:01:47.420585 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9677 10:01:47.427141 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9678 10:01:47.430694 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9679 10:01:47.436808 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9680 10:01:47.440061 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9681 10:01:47.447155 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9682 10:01:47.450192 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9683 10:01:47.453735 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9684 10:01:47.459998 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9685 10:01:47.463907 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9686 10:01:47.470136 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9687 10:01:47.473352 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9688 10:01:47.480223 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9689 10:01:47.483791 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9690 10:01:47.486990 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9691 10:01:47.493851 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9692 10:01:47.496692 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9693 10:01:47.503340 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9694 10:01:47.506456 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9695 10:01:47.512834 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9696 10:01:47.516804 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9697 10:01:47.523321 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9698 10:01:47.526211 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9699 10:01:47.529825 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9700 10:01:47.536364 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9701 10:01:47.540449 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9702 10:01:47.542843 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9703 10:01:47.546222 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9704 10:01:47.553367 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9705 10:01:47.556097 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9706 10:01:47.563012 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9707 10:01:47.566094 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9708 10:01:47.569481 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9709 10:01:47.575745 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9710 10:01:47.579204 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9711 10:01:47.586156 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9712 10:01:47.589134 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9713 10:01:47.592547 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9714 10:01:47.599836 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9715 10:01:47.602536 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9716 10:01:47.608823 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9717 10:01:47.612447 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9718 10:01:47.616216 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9719 10:01:47.622214 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9720 10:01:47.625817 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9721 10:01:47.629500 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9722 10:01:47.635789 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9723 10:01:47.638790 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9724 10:01:47.642489 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9725 10:01:47.645122 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9726 10:01:47.651642 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9727 10:01:47.655077 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9728 10:01:47.658204 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9729 10:01:47.665415 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9730 10:01:47.668363 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9731 10:01:47.674967 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9732 10:01:47.678558 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9733 10:01:47.681356 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9734 10:01:47.688379 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9735 10:01:47.691627 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9736 10:01:47.698194 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9737 10:01:47.701486 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9738 10:01:47.704960 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9739 10:01:47.711433 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9740 10:01:47.714879 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9741 10:01:47.721320 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9742 10:01:47.724908 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9743 10:01:47.727821 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9744 10:01:47.734582 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9745 10:01:47.737877 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9746 10:01:47.746141 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9747 10:01:47.748050 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9748 10:01:47.751367 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9749 10:01:47.758124 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9750 10:01:47.761198 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9751 10:01:47.768429 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9752 10:01:47.771289 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9753 10:01:47.775123 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9754 10:01:47.780992 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9755 10:01:47.784391 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9756 10:01:47.787750 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9757 10:01:47.794501 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9758 10:01:47.797524 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9759 10:01:47.804166 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9760 10:01:47.807502 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9761 10:01:47.810961 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9762 10:01:47.817517 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9763 10:01:47.820525 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9764 10:01:47.827289 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9765 10:01:47.831170 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9766 10:01:47.833871 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9767 10:01:47.840729 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9768 10:01:47.844171 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9769 10:01:47.850264 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9770 10:01:47.854006 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9771 10:01:47.857190 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9772 10:01:47.863460 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9773 10:01:47.866927 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9774 10:01:47.873693 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9775 10:01:47.877058 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9776 10:01:47.880533 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9777 10:01:47.887159 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9778 10:01:47.890473 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9779 10:01:47.896949 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9780 10:01:47.900613 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9781 10:01:47.903849 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9782 10:01:47.909865 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9783 10:01:47.913270 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9784 10:01:47.919710 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9785 10:01:47.922524 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9786 10:01:47.926419 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9787 10:01:47.932480 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9788 10:01:47.935727 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9789 10:01:47.942536 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9790 10:01:47.945399 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9791 10:01:47.952042 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9792 10:01:47.955991 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9793 10:01:47.959019 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9794 10:01:47.965826 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9795 10:01:47.969019 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9796 10:01:47.975588 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9797 10:01:47.978643 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9798 10:01:47.981812 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9799 10:01:47.988352 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9800 10:01:47.991620 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9801 10:01:47.998392 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9802 10:01:48.002001 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9803 10:01:48.008612 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9804 10:01:48.011748 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9805 10:01:48.014901 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9806 10:01:48.021721 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9807 10:01:48.024556 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9808 10:01:48.031616 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9809 10:01:48.034718 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9810 10:01:48.038184 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9811 10:01:48.044867 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9812 10:01:48.048339 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9813 10:01:48.054695 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9814 10:01:48.057948 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9815 10:01:48.064865 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9816 10:01:48.067742 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9817 10:01:48.071499 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9818 10:01:48.078131 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9819 10:01:48.081090 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9820 10:01:48.087732 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9821 10:01:48.091164 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9822 10:01:48.097665 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9823 10:01:48.100895 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9824 10:01:48.104413 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9825 10:01:48.110802 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9826 10:01:48.114387 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9827 10:01:48.120707 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9828 10:01:48.124206 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9829 10:01:48.130931 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9830 10:01:48.134218 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9831 10:01:48.137779 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9832 10:01:48.144070 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9833 10:01:48.148041 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9834 10:01:48.151204 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9835 10:01:48.154113 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9836 10:01:48.160634 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9837 10:01:48.164253 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9838 10:01:48.167547 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9839 10:01:48.173714 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9840 10:01:48.177327 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9841 10:01:48.180644 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9842 10:01:48.187089 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9843 10:01:48.190394 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9844 10:01:48.196960 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9845 10:01:48.200205 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9846 10:01:48.203506 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9847 10:01:48.210475 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9848 10:01:48.214548 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9849 10:01:48.220032 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9850 10:01:48.223535 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9851 10:01:48.226501 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9852 10:01:48.233497 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9853 10:01:48.236958 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9854 10:01:48.240023 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9855 10:01:48.246591 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9856 10:01:48.250295 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9857 10:01:48.253383 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9858 10:01:48.259688 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9859 10:01:48.263209 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9860 10:01:48.269582 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9861 10:01:48.273158 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9862 10:01:48.276503 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9863 10:01:48.283044 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9864 10:01:48.285974 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9865 10:01:48.289377 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9866 10:01:48.296058 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9867 10:01:48.299159 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9868 10:01:48.305916 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9869 10:01:48.309220 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9870 10:01:48.312415 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9871 10:01:48.319258 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9872 10:01:48.322017 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9873 10:01:48.325666 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9874 10:01:48.328872 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9875 10:01:48.335932 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9876 10:01:48.338744 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9877 10:01:48.342582 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9878 10:01:48.345389 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9879 10:01:48.351941 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9880 10:01:48.355189 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9881 10:01:48.358850 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9882 10:01:48.362463 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9883 10:01:48.368285 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9884 10:01:48.371732 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9885 10:01:48.375158 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9886 10:01:48.381633 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9887 10:01:48.384466 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9888 10:01:48.391503 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9889 10:01:48.394671 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9890 10:01:48.401156 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9891 10:01:48.404498 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9892 10:01:48.408325 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9893 10:01:48.414730 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9894 10:01:48.417609 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9895 10:01:48.424402 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9896 10:01:48.427729 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9897 10:01:48.434022 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9898 10:01:48.437630 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9899 10:01:48.440728 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9900 10:01:48.447168 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9901 10:01:48.450287 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9902 10:01:48.456781 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9903 10:01:48.460703 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9904 10:01:48.463503 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9905 10:01:48.470805 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9906 10:01:48.473646 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9907 10:01:48.480151 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9908 10:01:48.483263 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9909 10:01:48.490099 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9910 10:01:48.493040 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9911 10:01:48.496468 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9912 10:01:48.503141 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9913 10:01:48.506594 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9914 10:01:48.512749 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9915 10:01:48.516079 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9916 10:01:48.519449 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9917 10:01:48.526532 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9918 10:01:48.529560 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9919 10:01:48.535765 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9920 10:01:48.539212 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9921 10:01:48.545999 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9922 10:01:48.548845 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9923 10:01:48.555970 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9924 10:01:48.558958 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9925 10:01:48.562324 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9926 10:01:48.568945 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9927 10:01:48.572515 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9928 10:01:48.578843 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9929 10:01:48.582003 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9930 10:01:48.585274 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9931 10:01:48.591773 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9932 10:01:48.595452 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9933 10:01:48.601987 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9934 10:01:48.605050 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9935 10:01:48.608374 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9936 10:01:48.615106 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9937 10:01:48.618576 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9938 10:01:48.625148 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9939 10:01:48.628384 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9940 10:01:48.631435 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9941 10:01:48.639008 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9942 10:01:48.641671 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9943 10:01:48.648044 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9944 10:01:48.651609 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9945 10:01:48.657927 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9946 10:01:48.662192 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9947 10:01:48.664819 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9948 10:01:48.671138 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9949 10:01:48.674636 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9950 10:01:48.680840 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9951 10:01:48.684449 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9952 10:01:48.691313 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9953 10:01:48.693934 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9954 10:01:48.697279 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9955 10:01:48.704437 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9956 10:01:48.707367 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9957 10:01:48.713586 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9958 10:01:48.716950 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9959 10:01:48.723582 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9960 10:01:48.727262 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9961 10:01:48.733432 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9962 10:01:48.736899 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9963 10:01:48.739918 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9964 10:01:48.746575 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9965 10:01:48.750035 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9966 10:01:48.756577 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9967 10:01:48.759886 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9968 10:01:48.767067 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9969 10:01:48.769895 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9970 10:01:48.776742 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9971 10:01:48.779900 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9972 10:01:48.783297 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9973 10:01:48.789996 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9974 10:01:48.793252 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9975 10:01:48.800213 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9976 10:01:48.803103 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9977 10:01:48.809881 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9978 10:01:48.812840 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9979 10:01:48.819351 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9980 10:01:48.823144 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9981 10:01:48.826044 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9982 10:01:48.832546 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9983 10:01:48.836609 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9984 10:01:48.843021 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9985 10:01:48.846300 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9986 10:01:48.852407 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9987 10:01:48.856285 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9988 10:01:48.859924 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9989 10:01:48.865562 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9990 10:01:48.868718 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9991 10:01:48.875688 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9992 10:01:48.879351 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9993 10:01:48.885233 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9994 10:01:48.888566 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9995 10:01:48.895465 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9996 10:01:48.898956 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9997 10:01:48.902547 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9998 10:01:48.908364 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9999 10:01:48.912292 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
10000 10:01:48.918822 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
10001 10:01:48.921880 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
10002 10:01:48.929043 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
10003 10:01:48.931834 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
10004 10:01:48.934947 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
10005 10:01:48.942073 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
10006 10:01:48.945237 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
10007 10:01:48.951592 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
10008 10:01:48.954720 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
10009 10:01:48.961557 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
10010 10:01:48.964603 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
10011 10:01:48.971265 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
10012 10:01:48.974605 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
10013 10:01:48.980991 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
10014 10:01:48.984743 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
10015 10:01:48.991148 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
10016 10:01:48.994551 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
10017 10:01:49.001142 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
10018 10:01:49.004310 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
10019 10:01:49.011082 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
10020 10:01:49.014548 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
10021 10:01:49.021023 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
10022 10:01:49.024077 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
10023 10:01:49.030792 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
10024 10:01:49.033684 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10025 10:01:49.040664 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10026 10:01:49.043578 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10027 10:01:49.050493 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10028 10:01:49.053793 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10029 10:01:49.060277 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10030 10:01:49.063679 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10031 10:01:49.070857 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10032 10:01:49.073529 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10033 10:01:49.080189 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10034 10:01:49.083556 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10035 10:01:49.090081 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10036 10:01:49.093552 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10037 10:01:49.096517 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10038 10:01:49.099750 INFO: [APUAPC] vio 0
10039 10:01:49.106283 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10040 10:01:49.109505 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10041 10:01:49.112893 INFO: [APUAPC] D0_APC_0: 0x400510
10042 10:01:49.116700 INFO: [APUAPC] D0_APC_1: 0x0
10043 10:01:49.119345 INFO: [APUAPC] D0_APC_2: 0x1540
10044 10:01:49.122837 INFO: [APUAPC] D0_APC_3: 0x0
10045 10:01:49.126249 INFO: [APUAPC] D1_APC_0: 0xffffffff
10046 10:01:49.129744 INFO: [APUAPC] D1_APC_1: 0xffffffff
10047 10:01:49.133380 INFO: [APUAPC] D1_APC_2: 0x3fffff
10048 10:01:49.136386 INFO: [APUAPC] D1_APC_3: 0x0
10049 10:01:49.139430 INFO: [APUAPC] D2_APC_0: 0xffffffff
10050 10:01:49.142896 INFO: [APUAPC] D2_APC_1: 0xffffffff
10051 10:01:49.145958 INFO: [APUAPC] D2_APC_2: 0x3fffff
10052 10:01:49.149120 INFO: [APUAPC] D2_APC_3: 0x0
10053 10:01:49.152690 INFO: [APUAPC] D3_APC_0: 0xffffffff
10054 10:01:49.156176 INFO: [APUAPC] D3_APC_1: 0xffffffff
10055 10:01:49.159341 INFO: [APUAPC] D3_APC_2: 0x3fffff
10056 10:01:49.159423 INFO: [APUAPC] D3_APC_3: 0x0
10057 10:01:49.165806 INFO: [APUAPC] D4_APC_0: 0xffffffff
10058 10:01:49.169421 INFO: [APUAPC] D4_APC_1: 0xffffffff
10059 10:01:49.172641 INFO: [APUAPC] D4_APC_2: 0x3fffff
10060 10:01:49.172723 INFO: [APUAPC] D4_APC_3: 0x0
10061 10:01:49.175692 INFO: [APUAPC] D5_APC_0: 0xffffffff
10062 10:01:49.182726 INFO: [APUAPC] D5_APC_1: 0xffffffff
10063 10:01:49.185617 INFO: [APUAPC] D5_APC_2: 0x3fffff
10064 10:01:49.185700 INFO: [APUAPC] D5_APC_3: 0x0
10065 10:01:49.189866 INFO: [APUAPC] D6_APC_0: 0xffffffff
10066 10:01:49.192391 INFO: [APUAPC] D6_APC_1: 0xffffffff
10067 10:01:49.195550 INFO: [APUAPC] D6_APC_2: 0x3fffff
10068 10:01:49.198842 INFO: [APUAPC] D6_APC_3: 0x0
10069 10:01:49.202391 INFO: [APUAPC] D7_APC_0: 0xffffffff
10070 10:01:49.205318 INFO: [APUAPC] D7_APC_1: 0xffffffff
10071 10:01:49.208803 INFO: [APUAPC] D7_APC_2: 0x3fffff
10072 10:01:49.211893 INFO: [APUAPC] D7_APC_3: 0x0
10073 10:01:49.215331 INFO: [APUAPC] D8_APC_0: 0xffffffff
10074 10:01:49.218955 INFO: [APUAPC] D8_APC_1: 0xffffffff
10075 10:01:49.221994 INFO: [APUAPC] D8_APC_2: 0x3fffff
10076 10:01:49.225162 INFO: [APUAPC] D8_APC_3: 0x0
10077 10:01:49.228393 INFO: [APUAPC] D9_APC_0: 0xffffffff
10078 10:01:49.231972 INFO: [APUAPC] D9_APC_1: 0xffffffff
10079 10:01:49.235573 INFO: [APUAPC] D9_APC_2: 0x3fffff
10080 10:01:49.238402 INFO: [APUAPC] D9_APC_3: 0x0
10081 10:01:49.241957 INFO: [APUAPC] D10_APC_0: 0xffffffff
10082 10:01:49.245520 INFO: [APUAPC] D10_APC_1: 0xffffffff
10083 10:01:49.248892 INFO: [APUAPC] D10_APC_2: 0x3fffff
10084 10:01:49.252154 INFO: [APUAPC] D10_APC_3: 0x0
10085 10:01:49.255392 INFO: [APUAPC] D11_APC_0: 0xffffffff
10086 10:01:49.258842 INFO: [APUAPC] D11_APC_1: 0xffffffff
10087 10:01:49.261956 INFO: [APUAPC] D11_APC_2: 0x3fffff
10088 10:01:49.265587 INFO: [APUAPC] D11_APC_3: 0x0
10089 10:01:49.268843 INFO: [APUAPC] D12_APC_0: 0xffffffff
10090 10:01:49.272229 INFO: [APUAPC] D12_APC_1: 0xffffffff
10091 10:01:49.274978 INFO: [APUAPC] D12_APC_2: 0x3fffff
10092 10:01:49.278912 INFO: [APUAPC] D12_APC_3: 0x0
10093 10:01:49.281580 INFO: [APUAPC] D13_APC_0: 0xffffffff
10094 10:01:49.285575 INFO: [APUAPC] D13_APC_1: 0xffffffff
10095 10:01:49.288250 INFO: [APUAPC] D13_APC_2: 0x3fffff
10096 10:01:49.291939 INFO: [APUAPC] D13_APC_3: 0x0
10097 10:01:49.295199 INFO: [APUAPC] D14_APC_0: 0xffffffff
10098 10:01:49.298578 INFO: [APUAPC] D14_APC_1: 0xffffffff
10099 10:01:49.301348 INFO: [APUAPC] D14_APC_2: 0x3fffff
10100 10:01:49.304547 INFO: [APUAPC] D14_APC_3: 0x0
10101 10:01:49.307625 INFO: [APUAPC] D15_APC_0: 0xffffffff
10102 10:01:49.314316 INFO: [APUAPC] D15_APC_1: 0xffffffff
10103 10:01:49.317623 INFO: [APUAPC] D15_APC_2: 0x3fffff
10104 10:01:49.317735 INFO: [APUAPC] D15_APC_3: 0x0
10105 10:01:49.320841 INFO: [APUAPC] APC_CON: 0x4
10106 10:01:49.324242 INFO: [NOCDAPC] D0_APC_0: 0x0
10107 10:01:49.327549 INFO: [NOCDAPC] D0_APC_1: 0x0
10108 10:01:49.330999 INFO: [NOCDAPC] D1_APC_0: 0x0
10109 10:01:49.334238 INFO: [NOCDAPC] D1_APC_1: 0xfff
10110 10:01:49.337315 INFO: [NOCDAPC] D2_APC_0: 0x0
10111 10:01:49.340820 INFO: [NOCDAPC] D2_APC_1: 0xfff
10112 10:01:49.344282 INFO: [NOCDAPC] D3_APC_0: 0x0
10113 10:01:49.347179 INFO: [NOCDAPC] D3_APC_1: 0xfff
10114 10:01:49.347261 INFO: [NOCDAPC] D4_APC_0: 0x0
10115 10:01:49.350717 INFO: [NOCDAPC] D4_APC_1: 0xfff
10116 10:01:49.354230 INFO: [NOCDAPC] D5_APC_0: 0x0
10117 10:01:49.357721 INFO: [NOCDAPC] D5_APC_1: 0xfff
10118 10:01:49.360297 INFO: [NOCDAPC] D6_APC_0: 0x0
10119 10:01:49.364325 INFO: [NOCDAPC] D6_APC_1: 0xfff
10120 10:01:49.367356 INFO: [NOCDAPC] D7_APC_0: 0x0
10121 10:01:49.370461 INFO: [NOCDAPC] D7_APC_1: 0xfff
10122 10:01:49.373576 INFO: [NOCDAPC] D8_APC_0: 0x0
10123 10:01:49.377371 INFO: [NOCDAPC] D8_APC_1: 0xfff
10124 10:01:49.380236 INFO: [NOCDAPC] D9_APC_0: 0x0
10125 10:01:49.380318 INFO: [NOCDAPC] D9_APC_1: 0xfff
10126 10:01:49.383684 INFO: [NOCDAPC] D10_APC_0: 0x0
10127 10:01:49.387040 INFO: [NOCDAPC] D10_APC_1: 0xfff
10128 10:01:49.390346 INFO: [NOCDAPC] D11_APC_0: 0x0
10129 10:01:49.393480 INFO: [NOCDAPC] D11_APC_1: 0xfff
10130 10:01:49.396916 INFO: [NOCDAPC] D12_APC_0: 0x0
10131 10:01:49.400477 INFO: [NOCDAPC] D12_APC_1: 0xfff
10132 10:01:49.403441 INFO: [NOCDAPC] D13_APC_0: 0x0
10133 10:01:49.406674 INFO: [NOCDAPC] D13_APC_1: 0xfff
10134 10:01:49.410013 INFO: [NOCDAPC] D14_APC_0: 0x0
10135 10:01:49.413188 INFO: [NOCDAPC] D14_APC_1: 0xfff
10136 10:01:49.416835 INFO: [NOCDAPC] D15_APC_0: 0x0
10137 10:01:49.419812 INFO: [NOCDAPC] D15_APC_1: 0xfff
10138 10:01:49.423604 INFO: [NOCDAPC] APC_CON: 0x4
10139 10:01:49.427074 INFO: [APUAPC] set_apusys_apc done
10140 10:01:49.430063 INFO: [DEVAPC] devapc_init done
10141 10:01:49.432838 INFO: GICv3 without legacy support detected.
10142 10:01:49.436581 INFO: ARM GICv3 driver initialized in EL3
10143 10:01:49.439613 INFO: Maximum SPI INTID supported: 639
10144 10:01:49.442828 INFO: BL31: Initializing runtime services
10145 10:01:49.449787 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10146 10:01:49.452681 INFO: SPM: enable CPC mode
10147 10:01:49.459584 INFO: mcdi ready for mcusys-off-idle and system suspend
10148 10:01:49.463034 INFO: BL31: Preparing for EL3 exit to normal world
10149 10:01:49.466410 INFO: Entry point address = 0x80000000
10150 10:01:49.469224 INFO: SPSR = 0x8
10151 10:01:49.474058
10152 10:01:49.474139
10153 10:01:49.474204
10154 10:01:49.477545 Starting depthcharge on Spherion...
10155 10:01:49.477627
10156 10:01:49.477691 Wipe memory regions:
10157 10:01:49.477752
10158 10:01:49.478443 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10159 10:01:49.478579 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10160 10:01:49.478664 Setting prompt string to ['asurada:']
10161 10:01:49.478745 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10162 10:01:49.480478 [0x00000040000000, 0x00000054600000)
10163 10:01:49.603615
10164 10:01:49.603749 [0x00000054660000, 0x00000080000000)
10165 10:01:49.863573
10166 10:01:49.863727 [0x000000821a7280, 0x000000ffe64000)
10167 10:01:50.608818
10168 10:01:50.608978 [0x00000100000000, 0x00000240000000)
10169 10:01:52.499099
10170 10:01:52.502541 Initializing XHCI USB controller at 0x11200000.
10171 10:01:53.484059
10172 10:01:53.484626 R8152: Initializing
10173 10:01:53.485000
10174 10:01:53.487216 Version 9 (ocp_data = 6010)
10175 10:01:53.487677
10176 10:01:53.490970 R8152: Done initializing
10177 10:01:53.491556
10178 10:01:53.491932 Adding net device
10179 10:01:54.012611
10180 10:01:54.015715 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10181 10:01:54.016274
10182 10:01:54.016647
10183 10:01:54.016990
10184 10:01:54.017826 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10186 10:01:54.119086 asurada: tftpboot 192.168.201.1 12073315/tftp-deploy-ahuft4sa/kernel/image.itb 12073315/tftp-deploy-ahuft4sa/kernel/cmdline
10187 10:01:54.119648 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10188 10:01:54.120042 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10189 10:01:54.124207 tftpboot 192.168.201.1 12073315/tftp-deploy-ahuft4sa/kernel/image.itp-deploy-ahuft4sa/kernel/cmdline
10190 10:01:54.124635
10191 10:01:54.124970 Waiting for link
10192 10:01:54.326676
10193 10:01:54.327212 done.
10194 10:01:54.327777
10195 10:01:54.328262 MAC: f4:f5:e8:50:de:0a
10196 10:01:54.328857
10197 10:01:54.329841 Sending DHCP discover... done.
10198 10:01:54.330233
10199 10:01:54.333549 Waiting for reply... done.
10200 10:01:54.334017
10201 10:01:54.339880 Sending DHCP request... done.
10202 10:01:54.340618
10203 10:01:54.367621 Waiting for reply... done.
10204 10:01:54.368036
10205 10:01:54.368288 My ip is 192.168.201.14
10206 10:01:54.368511
10207 10:01:54.370715 The DHCP server ip is 192.168.201.1
10208 10:01:54.371089
10209 10:01:54.376706 TFTP server IP predefined by user: 192.168.201.1
10210 10:01:54.376794
10211 10:01:54.383249 Bootfile predefined by user: 12073315/tftp-deploy-ahuft4sa/kernel/image.itb
10212 10:01:54.383334
10213 10:01:54.386618 Sending tftp read request... done.
10214 10:01:54.386701
10215 10:01:54.390040 Waiting for the transfer...
10216 10:01:54.390123
10217 10:01:54.619144 00000000 ################################################################
10218 10:01:54.619298
10219 10:01:54.851136 00080000 ################################################################
10220 10:01:54.851288
10221 10:01:55.080115 00100000 ################################################################
10222 10:01:55.080266
10223 10:01:55.315589 00180000 ################################################################
10224 10:01:55.315737
10225 10:01:55.546753 00200000 ################################################################
10226 10:01:55.546901
10227 10:01:55.782362 00280000 ################################################################
10228 10:01:55.782514
10229 10:01:56.011088 00300000 ################################################################
10230 10:01:56.011238
10231 10:01:56.238733 00380000 ################################################################
10232 10:01:56.238880
10233 10:01:56.467576 00400000 ################################################################
10234 10:01:56.467725
10235 10:01:56.697674 00480000 ################################################################
10236 10:01:56.697823
10237 10:01:56.924897 00500000 ################################################################
10238 10:01:56.925046
10239 10:01:57.158150 00580000 ################################################################
10240 10:01:57.158298
10241 10:01:57.387365 00600000 ################################################################
10242 10:01:57.387515
10243 10:01:57.620895 00680000 ################################################################
10244 10:01:57.621046
10245 10:01:57.848147 00700000 ################################################################
10246 10:01:57.848376
10247 10:01:58.077950 00780000 ################################################################
10248 10:01:58.078101
10249 10:01:58.307619 00800000 ################################################################
10250 10:01:58.307766
10251 10:01:58.542983 00880000 ################################################################
10252 10:01:58.543129
10253 10:01:58.775908 00900000 ################################################################
10254 10:01:58.776056
10255 10:01:59.002060 00980000 ################################################################
10256 10:01:59.002208
10257 10:01:59.234417 00a00000 ################################################################
10258 10:01:59.234565
10259 10:01:59.462772 00a80000 ################################################################
10260 10:01:59.462920
10261 10:01:59.690365 00b00000 ################################################################
10262 10:01:59.690511
10263 10:01:59.919950 00b80000 ################################################################
10264 10:01:59.920150
10265 10:02:00.142908 00c00000 ################################################################
10266 10:02:00.143090
10267 10:02:00.367693 00c80000 ################################################################
10268 10:02:00.367871
10269 10:02:00.596903 00d00000 ################################################################
10270 10:02:00.597081
10271 10:02:00.825296 00d80000 ################################################################
10272 10:02:00.825498
10273 10:02:01.051829 00e00000 ################################################################
10274 10:02:01.052000
10275 10:02:01.278053 00e80000 ################################################################
10276 10:02:01.278200
10277 10:02:01.504590 00f00000 ################################################################
10278 10:02:01.504734
10279 10:02:01.735111 00f80000 ################################################################
10280 10:02:01.735283
10281 10:02:01.971326 01000000 ################################################################
10282 10:02:01.971501
10283 10:02:02.203823 01080000 ################################################################
10284 10:02:02.203964
10285 10:02:02.439213 01100000 ################################################################
10286 10:02:02.439358
10287 10:02:02.673734 01180000 ################################################################
10288 10:02:02.673905
10289 10:02:02.919667 01200000 ################################################################
10290 10:02:02.919823
10291 10:02:03.155695 01280000 ################################################################
10292 10:02:03.155835
10293 10:02:03.397516 01300000 ################################################################
10294 10:02:03.397665
10295 10:02:03.636197 01380000 ################################################################
10296 10:02:03.636366
10297 10:02:03.863949 01400000 ################################################################
10298 10:02:03.864104
10299 10:02:04.108194 01480000 ################################################################
10300 10:02:04.108336
10301 10:02:04.345094 01500000 ################################################################
10302 10:02:04.345246
10303 10:02:04.587414 01580000 ################################################################
10304 10:02:04.587569
10305 10:02:04.852174 01600000 ################################################################
10306 10:02:04.852327
10307 10:02:05.114241 01680000 ################################################################
10308 10:02:05.114386
10309 10:02:05.370338 01700000 ################################################################
10310 10:02:05.370488
10311 10:02:05.611034 01780000 ################################################################
10312 10:02:05.611176
10313 10:02:05.883121 01800000 ################################################################
10314 10:02:05.883267
10315 10:02:06.156022 01880000 ################################################################
10316 10:02:06.156167
10317 10:02:06.413238 01900000 ################################################################
10318 10:02:06.413381
10319 10:02:06.646725 01980000 ################################################################
10320 10:02:06.646864
10321 10:02:06.874202 01a00000 ################################################################
10322 10:02:06.874337
10323 10:02:07.101003 01a80000 ################################################################
10324 10:02:07.101143
10325 10:02:07.327671 01b00000 ################################################################
10326 10:02:07.327804
10327 10:02:07.564311 01b80000 ################################################################
10328 10:02:07.564454
10329 10:02:07.808525 01c00000 ############################################################# done.
10330 10:02:07.808678
10331 10:02:07.811863 The bootfile was 29859330 bytes long.
10332 10:02:07.811953
10333 10:02:07.815156 Sending tftp read request... done.
10334 10:02:07.815249
10335 10:02:07.815322 Waiting for the transfer...
10336 10:02:07.815390
10337 10:02:07.818410 00000000 # done.
10338 10:02:07.818513
10339 10:02:07.825456 Command line loaded dynamically from TFTP file: 12073315/tftp-deploy-ahuft4sa/kernel/cmdline
10340 10:02:07.825566
10341 10:02:07.848207 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12073315/extract-nfsrootfs-ykqohhck,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10342 10:02:07.848500
10343 10:02:07.848667 Loading FIT.
10344 10:02:07.848816
10345 10:02:07.852127 Image ramdisk-1 has 18762476 bytes.
10346 10:02:07.852414
10347 10:02:07.855165 Image fdt-1 has 47278 bytes.
10348 10:02:07.855495
10349 10:02:07.858150 Image kernel-1 has 11047542 bytes.
10350 10:02:07.858542
10351 10:02:07.868280 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10352 10:02:07.868856
10353 10:02:07.885154 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10354 10:02:07.885808
10355 10:02:07.891099 Choosing best match conf-1 for compat google,spherion-rev2.
10356 10:02:07.895350
10357 10:02:07.898797 Connected to device vid:did:rid of 1ae0:0028:00
10358 10:02:07.906794
10359 10:02:07.909817 tpm_get_response: command 0x17b, return code 0x0
10360 10:02:07.910297
10361 10:02:07.912842 ec_init: CrosEC protocol v3 supported (256, 248)
10362 10:02:07.916820
10363 10:02:07.920699 tpm_cleanup: add release locality here.
10364 10:02:07.921281
10365 10:02:07.921819 Shutting down all USB controllers.
10366 10:02:07.923300
10367 10:02:07.923711 Removing current net device
10368 10:02:07.924167
10369 10:02:07.930173 Exiting depthcharge with code 4 at timestamp: 47925969
10370 10:02:07.930761
10371 10:02:07.933321 LZMA decompressing kernel-1 to 0x821a6718
10372 10:02:07.933876
10373 10:02:07.936788 LZMA decompressing kernel-1 to 0x40000000
10374 10:02:09.325893
10375 10:02:09.326462 jumping to kernel
10376 10:02:09.328279 end: 2.2.4 bootloader-commands (duration 00:00:20) [common]
10377 10:02:09.328889 start: 2.2.5 auto-login-action (timeout 00:04:05) [common]
10378 10:02:09.329347 Setting prompt string to ['Linux version [0-9]']
10379 10:02:09.329874 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10380 10:02:09.330336 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10381 10:02:09.409092
10382 10:02:09.412195 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10383 10:02:09.415780 start: 2.2.5.1 login-action (timeout 00:04:05) [common]
10384 10:02:09.416311 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10385 10:02:09.416775 Setting prompt string to []
10386 10:02:09.417319 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10387 10:02:09.417978 Using line separator: #'\n'#
10388 10:02:09.418405 No login prompt set.
10389 10:02:09.418873 Parsing kernel messages
10390 10:02:09.419294 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10391 10:02:09.419971 [login-action] Waiting for messages, (timeout 00:04:05)
10392 10:02:09.435549 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j22848-arm64-gcc-10-defconfig-arm64-chromebook-6q8mw) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Nov 24 09:44:51 UTC 2023
10393 10:02:09.438465 [ 0.000000] random: crng init done
10394 10:02:09.445210 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10395 10:02:09.448562 [ 0.000000] efi: UEFI not found.
10396 10:02:09.455561 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10397 10:02:09.461683 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10398 10:02:09.471260 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10399 10:02:09.481304 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10400 10:02:09.487914 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10401 10:02:09.494736 [ 0.000000] printk: bootconsole [mtk8250] enabled
10402 10:02:09.501273 [ 0.000000] NUMA: No NUMA configuration found
10403 10:02:09.508072 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10404 10:02:09.511017 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10405 10:02:09.514275 [ 0.000000] Zone ranges:
10406 10:02:09.521060 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10407 10:02:09.524039 [ 0.000000] DMA32 empty
10408 10:02:09.530656 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10409 10:02:09.534349 [ 0.000000] Movable zone start for each node
10410 10:02:09.537455 [ 0.000000] Early memory node ranges
10411 10:02:09.543828 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10412 10:02:09.550950 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10413 10:02:09.557627 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10414 10:02:09.563723 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10415 10:02:09.570098 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10416 10:02:09.577270 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10417 10:02:09.633318 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10418 10:02:09.639808 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10419 10:02:09.646798 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10420 10:02:09.649554 [ 0.000000] psci: probing for conduit method from DT.
10421 10:02:09.656640 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10422 10:02:09.659565 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10423 10:02:09.666188 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10424 10:02:09.669599 [ 0.000000] psci: SMC Calling Convention v1.2
10425 10:02:09.675899 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10426 10:02:09.679494 [ 0.000000] Detected VIPT I-cache on CPU0
10427 10:02:09.686367 [ 0.000000] CPU features: detected: GIC system register CPU interface
10428 10:02:09.693193 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10429 10:02:09.699287 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10430 10:02:09.705944 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10431 10:02:09.716237 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10432 10:02:09.722087 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10433 10:02:09.725434 [ 0.000000] alternatives: applying boot alternatives
10434 10:02:09.731955 [ 0.000000] Fallback order for Node 0: 0
10435 10:02:09.738781 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10436 10:02:09.741804 [ 0.000000] Policy zone: Normal
10437 10:02:09.765596 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12073315/extract-nfsrootfs-ykqohhck,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10438 10:02:09.774907 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10439 10:02:09.785532 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10440 10:02:09.795458 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10441 10:02:09.802367 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10442 10:02:09.805059 <6>[ 0.000000] software IO TLB: area num 8.
10443 10:02:09.862294 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10444 10:02:10.012199 <6>[ 0.000000] Memory: 7951296K/8385536K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 401472K reserved, 32768K cma-reserved)
10445 10:02:10.018036 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10446 10:02:10.025182 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10447 10:02:10.028017 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10448 10:02:10.034851 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10449 10:02:10.042268 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10450 10:02:10.045565 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10451 10:02:10.054864 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10452 10:02:10.061780 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10453 10:02:10.067999 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10454 10:02:10.074514 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10455 10:02:10.078105 <6>[ 0.000000] GICv3: 608 SPIs implemented
10456 10:02:10.081799 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10457 10:02:10.087645 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10458 10:02:10.091085 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10459 10:02:10.097644 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10460 10:02:10.110721 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10461 10:02:10.124498 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10462 10:02:10.130898 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10463 10:02:10.138560 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10464 10:02:10.151714 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10465 10:02:10.158851 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10466 10:02:10.164861 <6>[ 0.009182] Console: colour dummy device 80x25
10467 10:02:10.174379 <6>[ 0.013897] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10468 10:02:10.181788 <6>[ 0.024338] pid_max: default: 32768 minimum: 301
10469 10:02:10.184558 <6>[ 0.029241] LSM: Security Framework initializing
10470 10:02:10.190956 <6>[ 0.034177] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10471 10:02:10.201267 <6>[ 0.041991] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10472 10:02:10.211223 <6>[ 0.051396] cblist_init_generic: Setting adjustable number of callback queues.
10473 10:02:10.214383 <6>[ 0.058840] cblist_init_generic: Setting shift to 3 and lim to 1.
10474 10:02:10.223997 <6>[ 0.065178] cblist_init_generic: Setting adjustable number of callback queues.
10475 10:02:10.231301 <6>[ 0.072604] cblist_init_generic: Setting shift to 3 and lim to 1.
10476 10:02:10.234149 <6>[ 0.079042] rcu: Hierarchical SRCU implementation.
10477 10:02:10.240779 <6>[ 0.084058] rcu: Max phase no-delay instances is 1000.
10478 10:02:10.247555 <6>[ 0.091078] EFI services will not be available.
10479 10:02:10.250391 <6>[ 0.096034] smp: Bringing up secondary CPUs ...
10480 10:02:10.259086 <6>[ 0.101110] Detected VIPT I-cache on CPU1
10481 10:02:10.265921 <6>[ 0.101179] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10482 10:02:10.272890 <6>[ 0.101211] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10483 10:02:10.275718 <6>[ 0.101549] Detected VIPT I-cache on CPU2
10484 10:02:10.286004 <6>[ 0.101600] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10485 10:02:10.292292 <6>[ 0.101618] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10486 10:02:10.295522 <6>[ 0.101876] Detected VIPT I-cache on CPU3
10487 10:02:10.302530 <6>[ 0.101922] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10488 10:02:10.309143 <6>[ 0.101935] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10489 10:02:10.312198 <6>[ 0.102238] CPU features: detected: Spectre-v4
10490 10:02:10.318762 <6>[ 0.102245] CPU features: detected: Spectre-BHB
10491 10:02:10.322678 <6>[ 0.102250] Detected PIPT I-cache on CPU4
10492 10:02:10.328719 <6>[ 0.102305] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10493 10:02:10.335241 <6>[ 0.102322] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10494 10:02:10.342016 <6>[ 0.102612] Detected PIPT I-cache on CPU5
10495 10:02:10.348836 <6>[ 0.102675] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10496 10:02:10.355143 <6>[ 0.102692] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10497 10:02:10.358377 <6>[ 0.102971] Detected PIPT I-cache on CPU6
10498 10:02:10.365068 <6>[ 0.103036] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10499 10:02:10.371888 <6>[ 0.103052] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10500 10:02:10.378079 <6>[ 0.103349] Detected PIPT I-cache on CPU7
10501 10:02:10.385002 <6>[ 0.103413] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10502 10:02:10.391240 <6>[ 0.103429] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10503 10:02:10.394982 <6>[ 0.103476] smp: Brought up 1 node, 8 CPUs
10504 10:02:10.401584 <6>[ 0.244764] SMP: Total of 8 processors activated.
10505 10:02:10.404515 <6>[ 0.249685] CPU features: detected: 32-bit EL0 Support
10506 10:02:10.414634 <6>[ 0.255048] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10507 10:02:10.421188 <6>[ 0.263848] CPU features: detected: Common not Private translations
10508 10:02:10.428455 <6>[ 0.270364] CPU features: detected: CRC32 instructions
10509 10:02:10.430894 <6>[ 0.275715] CPU features: detected: RCpc load-acquire (LDAPR)
10510 10:02:10.437579 <6>[ 0.281675] CPU features: detected: LSE atomic instructions
10511 10:02:10.444206 <6>[ 0.287456] CPU features: detected: Privileged Access Never
10512 10:02:10.450647 <6>[ 0.293272] CPU features: detected: RAS Extension Support
10513 10:02:10.457444 <6>[ 0.298915] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10514 10:02:10.461128 <6>[ 0.306179] CPU: All CPU(s) started at EL2
10515 10:02:10.467437 <6>[ 0.310495] alternatives: applying system-wide alternatives
10516 10:02:10.477113 <6>[ 0.321215] devtmpfs: initialized
10517 10:02:10.489565 <6>[ 0.330207] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10518 10:02:10.499009 <6>[ 0.340170] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10519 10:02:10.506607 <6>[ 0.348358] pinctrl core: initialized pinctrl subsystem
10520 10:02:10.509031 <6>[ 0.355030] DMI not present or invalid.
10521 10:02:10.515732 <6>[ 0.359442] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10522 10:02:10.525481 <6>[ 0.366212] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10523 10:02:10.532021 <6>[ 0.373794] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10524 10:02:10.542247 <6>[ 0.382016] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10525 10:02:10.546154 <6>[ 0.390262] audit: initializing netlink subsys (disabled)
10526 10:02:10.555226 <5>[ 0.395952] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10527 10:02:10.562248 <6>[ 0.396654] thermal_sys: Registered thermal governor 'step_wise'
10528 10:02:10.568103 <6>[ 0.403923] thermal_sys: Registered thermal governor 'power_allocator'
10529 10:02:10.572141 <6>[ 0.410179] cpuidle: using governor menu
10530 10:02:10.578366 <6>[ 0.421142] NET: Registered PF_QIPCRTR protocol family
10531 10:02:10.584460 <6>[ 0.426638] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10532 10:02:10.591255 <6>[ 0.433741] ASID allocator initialised with 32768 entries
10533 10:02:10.594935 <6>[ 0.440312] Serial: AMBA PL011 UART driver
10534 10:02:10.604907 <4>[ 0.449136] Trying to register duplicate clock ID: 134
10535 10:02:10.661193 <6>[ 0.508817] KASLR enabled
10536 10:02:10.675260 <6>[ 0.516519] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10537 10:02:10.682155 <6>[ 0.523531] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10538 10:02:10.688774 <6>[ 0.530021] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10539 10:02:10.695248 <6>[ 0.537028] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10540 10:02:10.702007 <6>[ 0.543514] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10541 10:02:10.708890 <6>[ 0.550518] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10542 10:02:10.715312 <6>[ 0.557004] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10543 10:02:10.721574 <6>[ 0.564009] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10544 10:02:10.725383 <6>[ 0.571512] ACPI: Interpreter disabled.
10545 10:02:10.733810 <6>[ 0.577913] iommu: Default domain type: Translated
10546 10:02:10.740185 <6>[ 0.583026] iommu: DMA domain TLB invalidation policy: strict mode
10547 10:02:10.743440 <5>[ 0.589677] SCSI subsystem initialized
10548 10:02:10.750521 <6>[ 0.593842] usbcore: registered new interface driver usbfs
10549 10:02:10.757025 <6>[ 0.599575] usbcore: registered new interface driver hub
10550 10:02:10.760285 <6>[ 0.605129] usbcore: registered new device driver usb
10551 10:02:10.766724 <6>[ 0.611224] pps_core: LinuxPPS API ver. 1 registered
10552 10:02:10.776828 <6>[ 0.616417] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10553 10:02:10.779921 <6>[ 0.625765] PTP clock support registered
10554 10:02:10.783059 <6>[ 0.630006] EDAC MC: Ver: 3.0.0
10555 10:02:10.790718 <6>[ 0.635161] FPGA manager framework
10556 10:02:10.794250 <6>[ 0.638839] Advanced Linux Sound Architecture Driver Initialized.
10557 10:02:10.798311 <6>[ 0.645616] vgaarb: loaded
10558 10:02:10.804436 <6>[ 0.648808] clocksource: Switched to clocksource arch_sys_counter
10559 10:02:10.811292 <5>[ 0.655246] VFS: Disk quotas dquot_6.6.0
10560 10:02:10.817548 <6>[ 0.659429] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10561 10:02:10.820743 <6>[ 0.666618] pnp: PnP ACPI: disabled
10562 10:02:10.829362 <6>[ 0.673272] NET: Registered PF_INET protocol family
10563 10:02:10.838860 <6>[ 0.678860] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10564 10:02:10.849943 <6>[ 0.691181] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10565 10:02:10.860073 <6>[ 0.699992] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10566 10:02:10.866808 <6>[ 0.707962] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10567 10:02:10.876143 <6>[ 0.716661] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10568 10:02:10.882612 <6>[ 0.726413] TCP: Hash tables configured (established 65536 bind 65536)
10569 10:02:10.889772 <6>[ 0.733271] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10570 10:02:10.899361 <6>[ 0.740469] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10571 10:02:10.906159 <6>[ 0.748166] NET: Registered PF_UNIX/PF_LOCAL protocol family
10572 10:02:10.912697 <6>[ 0.754343] RPC: Registered named UNIX socket transport module.
10573 10:02:10.916078 <6>[ 0.760498] RPC: Registered udp transport module.
10574 10:02:10.922056 <6>[ 0.765431] RPC: Registered tcp transport module.
10575 10:02:10.928785 <6>[ 0.770365] RPC: Registered tcp NFSv4.1 backchannel transport module.
10576 10:02:10.932605 <6>[ 0.777032] PCI: CLS 0 bytes, default 64
10577 10:02:10.935142 <6>[ 0.781415] Unpacking initramfs...
10578 10:02:10.952992 <6>[ 0.793408] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10579 10:02:10.962833 <6>[ 0.802076] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10580 10:02:10.966039 <6>[ 0.810937] kvm [1]: IPA Size Limit: 40 bits
10581 10:02:10.972500 <6>[ 0.815467] kvm [1]: GICv3: no GICV resource entry
10582 10:02:10.976042 <6>[ 0.820491] kvm [1]: disabling GICv2 emulation
10583 10:02:10.982124 <6>[ 0.825179] kvm [1]: GIC system register CPU interface enabled
10584 10:02:10.985662 <6>[ 0.831342] kvm [1]: vgic interrupt IRQ18
10585 10:02:10.992051 <6>[ 0.835701] kvm [1]: VHE mode initialized successfully
10586 10:02:10.998654 <5>[ 0.842194] Initialise system trusted keyrings
10587 10:02:11.004802 <6>[ 0.846988] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10588 10:02:11.012686 <6>[ 0.856988] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10589 10:02:11.019017 <5>[ 0.863357] NFS: Registering the id_resolver key type
10590 10:02:11.022586 <5>[ 0.868652] Key type id_resolver registered
10591 10:02:11.029496 <5>[ 0.873067] Key type id_legacy registered
10592 10:02:11.036408 <6>[ 0.877346] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10593 10:02:11.042269 <6>[ 0.884268] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10594 10:02:11.049154 <6>[ 0.892020] 9p: Installing v9fs 9p2000 file system support
10595 10:02:11.086320 <5>[ 0.930384] Key type asymmetric registered
10596 10:02:11.089396 <5>[ 0.934719] Asymmetric key parser 'x509' registered
10597 10:02:11.099286 <6>[ 0.939864] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10598 10:02:11.102370 <6>[ 0.947479] io scheduler mq-deadline registered
10599 10:02:11.105751 <6>[ 0.952254] io scheduler kyber registered
10600 10:02:11.125911 <6>[ 0.969461] EINJ: ACPI disabled.
10601 10:02:11.158125 <4>[ 0.995879] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10602 10:02:11.167621 <4>[ 1.006521] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10603 10:02:11.183017 <6>[ 1.027444] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10604 10:02:11.191850 <6>[ 1.035546] printk: console [ttyS0] disabled
10605 10:02:11.219163 <6>[ 1.060217] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10606 10:02:11.225498 <6>[ 1.069686] printk: console [ttyS0] enabled
10607 10:02:11.229798 <6>[ 1.069686] printk: console [ttyS0] enabled
10608 10:02:11.235430 <6>[ 1.078579] printk: bootconsole [mtk8250] disabled
10609 10:02:11.239130 <6>[ 1.078579] printk: bootconsole [mtk8250] disabled
10610 10:02:11.245565 <6>[ 1.089866] SuperH (H)SCI(F) driver initialized
10611 10:02:11.248862 <6>[ 1.095130] msm_serial: driver initialized
10612 10:02:11.263043 <6>[ 1.104126] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10613 10:02:11.272881 <6>[ 1.112681] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10614 10:02:11.279703 <6>[ 1.121223] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10615 10:02:11.290044 <6>[ 1.129852] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10616 10:02:11.300274 <6>[ 1.138559] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10617 10:02:11.306346 <6>[ 1.147281] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10618 10:02:11.316373 <6>[ 1.155823] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10619 10:02:11.322224 <6>[ 1.164623] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10620 10:02:11.332709 <6>[ 1.173175] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10621 10:02:11.344571 <6>[ 1.188533] loop: module loaded
10622 10:02:11.350972 <6>[ 1.194602] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10623 10:02:11.373593 <4>[ 1.218022] mtk-pmic-keys: Failed to locate of_node [id: -1]
10624 10:02:11.380341 <6>[ 1.224898] megasas: 07.719.03.00-rc1
10625 10:02:11.390061 <6>[ 1.234455] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10626 10:02:11.399976 <6>[ 1.244186] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10627 10:02:11.416493 <6>[ 1.260756] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10628 10:02:11.476764 <6>[ 1.314564] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10629 10:02:11.729573 <6>[ 1.573922] Freeing initrd memory: 18320K
10630 10:02:11.741394 <6>[ 1.585676] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10631 10:02:11.752218 <6>[ 1.596533] tun: Universal TUN/TAP device driver, 1.6
10632 10:02:11.755493 <6>[ 1.602610] thunder_xcv, ver 1.0
10633 10:02:11.759106 <6>[ 1.606114] thunder_bgx, ver 1.0
10634 10:02:11.762181 <6>[ 1.609610] nicpf, ver 1.0
10635 10:02:11.772226 <6>[ 1.613625] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10636 10:02:11.776322 <6>[ 1.621101] hns3: Copyright (c) 2017 Huawei Corporation.
10637 10:02:11.783030 <6>[ 1.626687] hclge is initializing
10638 10:02:11.785753 <6>[ 1.630261] e1000: Intel(R) PRO/1000 Network Driver
10639 10:02:11.792595 <6>[ 1.635390] e1000: Copyright (c) 1999-2006 Intel Corporation.
10640 10:02:11.796174 <6>[ 1.641406] e1000e: Intel(R) PRO/1000 Network Driver
10641 10:02:11.802475 <6>[ 1.646621] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10642 10:02:11.809358 <6>[ 1.652810] igb: Intel(R) Gigabit Ethernet Network Driver
10643 10:02:11.815302 <6>[ 1.658459] igb: Copyright (c) 2007-2014 Intel Corporation.
10644 10:02:11.822486 <6>[ 1.664293] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10645 10:02:11.828758 <6>[ 1.670811] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10646 10:02:11.831862 <6>[ 1.677285] sky2: driver version 1.30
10647 10:02:11.839001 <6>[ 1.682273] VFIO - User Level meta-driver version: 0.3
10648 10:02:11.846138 <6>[ 1.690502] usbcore: registered new interface driver usb-storage
10649 10:02:11.852716 <6>[ 1.696953] usbcore: registered new device driver onboard-usb-hub
10650 10:02:11.862209 <6>[ 1.706117] mt6397-rtc mt6359-rtc: registered as rtc0
10651 10:02:11.871752 <6>[ 1.711597] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-24T10:02:14 UTC (1700820134)
10652 10:02:11.874871 <6>[ 1.721198] i2c_dev: i2c /dev entries driver
10653 10:02:11.891538 <6>[ 1.732899] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10654 10:02:11.912339 <6>[ 1.756829] cpu cpu0: EM: created perf domain
10655 10:02:11.915660 <6>[ 1.761754] cpu cpu4: EM: created perf domain
10656 10:02:11.923042 <6>[ 1.767312] sdhci: Secure Digital Host Controller Interface driver
10657 10:02:11.929820 <6>[ 1.773744] sdhci: Copyright(c) Pierre Ossman
10658 10:02:11.935901 <6>[ 1.778696] Synopsys Designware Multimedia Card Interface Driver
10659 10:02:11.943476 <6>[ 1.785349] sdhci-pltfm: SDHCI platform and OF driver helper
10660 10:02:11.946046 <6>[ 1.785384] mmc0: CQHCI version 5.10
10661 10:02:11.952541 <6>[ 1.795565] ledtrig-cpu: registered to indicate activity on CPUs
10662 10:02:11.960038 <6>[ 1.802520] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10663 10:02:11.966114 <6>[ 1.809569] usbcore: registered new interface driver usbhid
10664 10:02:11.969684 <6>[ 1.815392] usbhid: USB HID core driver
10665 10:02:11.975727 <6>[ 1.819590] spi_master spi0: will run message pump with realtime priority
10666 10:02:12.028043 <6>[ 1.865875] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10667 10:02:12.050343 <6>[ 1.884131] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10668 10:02:12.054142 <6>[ 1.897719] mmc0: Command Queue Engine enabled
10669 10:02:12.060218 <6>[ 1.899287] cros-ec-spi spi0.0: Chrome EC device registered
10670 10:02:12.066708 <6>[ 1.902483] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10671 10:02:12.070050 <6>[ 1.915635] mmcblk0: mmc0:0001 DA4128 116 GiB
10672 10:02:12.081827 <6>[ 1.926133] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10673 10:02:12.091778 <6>[ 1.926208] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10674 10:02:12.098232 <6>[ 1.933408] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10675 10:02:12.101235 <6>[ 1.942629] NET: Registered PF_PACKET protocol family
10676 10:02:12.108258 <6>[ 1.947371] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10677 10:02:12.111581 <6>[ 1.952004] 9pnet: Installing 9P2000 support
10678 10:02:12.118110 <6>[ 1.957902] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10679 10:02:12.125571 <5>[ 1.961704] Key type dns_resolver registered
10680 10:02:12.128577 <6>[ 1.973250] registered taskstats version 1
10681 10:02:12.134908 <5>[ 1.977643] Loading compiled-in X.509 certificates
10682 10:02:12.161865 <4>[ 1.999403] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10683 10:02:12.172297 <4>[ 2.010124] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10684 10:02:12.178059 <3>[ 2.020653] debugfs: File 'uA_load' in directory '/' already present!
10685 10:02:12.184995 <3>[ 2.027352] debugfs: File 'min_uV' in directory '/' already present!
10686 10:02:12.192323 <3>[ 2.034018] debugfs: File 'max_uV' in directory '/' already present!
10687 10:02:12.198637 <3>[ 2.040631] debugfs: File 'constraint_flags' in directory '/' already present!
10688 10:02:12.209234 <3>[ 2.050282] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10689 10:02:12.217792 <6>[ 2.062573] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10690 10:02:12.225003 <6>[ 2.069410] xhci-mtk 11200000.usb: xHCI Host Controller
10691 10:02:12.232045 <6>[ 2.074943] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10692 10:02:12.241824 <6>[ 2.082784] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10693 10:02:12.248224 <6>[ 2.092188] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10694 10:02:12.254718 <6>[ 2.098271] xhci-mtk 11200000.usb: xHCI Host Controller
10695 10:02:12.261937 <6>[ 2.103747] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10696 10:02:12.269465 <6>[ 2.111392] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10697 10:02:12.274456 <6>[ 2.119069] hub 1-0:1.0: USB hub found
10698 10:02:12.278208 <6>[ 2.123082] hub 1-0:1.0: 1 port detected
10699 10:02:12.285096 <6>[ 2.127349] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10700 10:02:12.291219 <6>[ 2.135977] hub 2-0:1.0: USB hub found
10701 10:02:12.294486 <6>[ 2.139995] hub 2-0:1.0: 1 port detected
10702 10:02:12.303138 <6>[ 2.147556] mtk-msdc 11f70000.mmc: Got CD GPIO
10703 10:02:12.314186 <6>[ 2.155257] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10704 10:02:12.320922 <6>[ 2.163286] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10705 10:02:12.330539 <4>[ 2.171184] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10706 10:02:12.340666 <6>[ 2.180708] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10707 10:02:12.347348 <6>[ 2.188786] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10708 10:02:12.354003 <6>[ 2.196857] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10709 10:02:12.364218 <6>[ 2.204780] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10710 10:02:12.370589 <6>[ 2.212598] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10711 10:02:12.380358 <6>[ 2.220415] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10712 10:02:12.390435 <6>[ 2.230749] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10713 10:02:12.397273 <6>[ 2.239108] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10714 10:02:12.406995 <6>[ 2.247453] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10715 10:02:12.413213 <6>[ 2.255791] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10716 10:02:12.423590 <6>[ 2.264129] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10717 10:02:12.430616 <6>[ 2.272470] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10718 10:02:12.440317 <6>[ 2.280809] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10719 10:02:12.446386 <6>[ 2.289148] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10720 10:02:12.456680 <6>[ 2.297487] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10721 10:02:12.463349 <6>[ 2.305825] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10722 10:02:12.473209 <6>[ 2.314164] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10723 10:02:12.479577 <6>[ 2.322502] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10724 10:02:12.490242 <6>[ 2.330842] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10725 10:02:12.499796 <6>[ 2.339181] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10726 10:02:12.506084 <6>[ 2.347519] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10727 10:02:12.513663 <6>[ 2.356239] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10728 10:02:12.520291 <6>[ 2.363373] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10729 10:02:12.526387 <6>[ 2.370150] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10730 10:02:12.532196 <6>[ 2.376902] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10731 10:02:12.542875 <6>[ 2.383836] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10732 10:02:12.550243 <6>[ 2.390681] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10733 10:02:12.559410 <6>[ 2.399808] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10734 10:02:12.569150 <6>[ 2.408933] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10735 10:02:12.579150 <6>[ 2.418227] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10736 10:02:12.589163 <6>[ 2.427698] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10737 10:02:12.596209 <6>[ 2.437166] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10738 10:02:12.605166 <6>[ 2.446290] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10739 10:02:12.616101 <6>[ 2.455757] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10740 10:02:12.625547 <6>[ 2.464877] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10741 10:02:12.635380 <6>[ 2.474171] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10742 10:02:12.644967 <6>[ 2.484331] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10743 10:02:12.655001 <6>[ 2.495845] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10744 10:02:12.661517 <6>[ 2.505400] Trying to probe devices needed for running init ...
10745 10:02:12.684146 <6>[ 2.525353] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10746 10:02:12.713300 <6>[ 2.556786] hub 2-1:1.0: USB hub found
10747 10:02:12.715868 <6>[ 2.561265] hub 2-1:1.0: 3 ports detected
10748 10:02:12.723957 <6>[ 2.568504] hub 2-1:1.0: USB hub found
10749 10:02:12.727559 <6>[ 2.572948] hub 2-1:1.0: 3 ports detected
10750 10:02:12.835772 <6>[ 2.677088] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10751 10:02:12.994650 <6>[ 2.839228] hub 1-1:1.0: USB hub found
10752 10:02:12.997927 <6>[ 2.843785] hub 1-1:1.0: 4 ports detected
10753 10:02:13.007549 <6>[ 2.852418] hub 1-1:1.0: USB hub found
10754 10:02:13.011034 <6>[ 2.856757] hub 1-1:1.0: 4 ports detected
10755 10:02:13.332045 <6>[ 3.173122] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10756 10:02:13.462944 <6>[ 3.307286] hub 1-1.1:1.0: USB hub found
10757 10:02:13.465729 <6>[ 3.311632] hub 1-1.1:1.0: 4 ports detected
10758 10:02:13.579728 <6>[ 3.421221] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10759 10:02:13.711636 <6>[ 3.556544] hub 1-1.4:1.0: USB hub found
10760 10:02:13.716226 <6>[ 3.561176] hub 1-1.4:1.0: 2 ports detected
10761 10:02:13.724197 <6>[ 3.568911] hub 1-1.4:1.0: USB hub found
10762 10:02:13.727547 <6>[ 3.573455] hub 1-1.4:1.0: 2 ports detected
10763 10:02:13.792119 <6>[ 3.633101] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10764 10:02:13.976654 <6>[ 3.817099] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10765 10:02:14.060416 <3>[ 3.905267] usb 1-1.1.4: device descriptor read/64, error -32
10766 10:02:14.252850 <3>[ 4.097262] usb 1-1.1.4: device descriptor read/64, error -32
10767 10:02:14.448543 <6>[ 4.289126] usb 1-1.1.4: new full-speed USB device number 7 using xhci-mtk
10768 10:02:14.532707 <3>[ 4.377304] usb 1-1.1.4: device descriptor read/64, error -32
10769 10:02:14.724688 <3>[ 4.569264] usb 1-1.1.4: device descriptor read/64, error -32
10770 10:02:14.836584 <6>[ 4.681578] usb 1-1.1-port4: attempt power cycle
10771 10:02:14.919482 <6>[ 4.761095] usb 1-1.4.1: new high-speed USB device number 8 using xhci-mtk
10772 10:02:15.107779 <6>[ 4.949077] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10773 10:02:15.503898 <6>[ 5.345106] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10774 10:02:15.509924 <4>[ 5.352571] usb 1-1.1.4: Device not responding to setup address.
10775 10:02:15.720381 <4>[ 5.565306] usb 1-1.1.4: Device not responding to setup address.
10776 10:02:15.932479 <3>[ 5.777118] usb 1-1.1.4: device not accepting address 10, error -71
10777 10:02:16.019855 <6>[ 5.861121] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10778 10:02:16.027345 <4>[ 5.868525] usb 1-1.1.4: Device not responding to setup address.
10779 10:02:16.236270 <4>[ 6.081387] usb 1-1.1.4: Device not responding to setup address.
10780 10:02:16.448607 <3>[ 6.293116] usb 1-1.1.4: device not accepting address 11, error -71
10781 10:02:16.455543 <3>[ 6.300161] usb 1-1.1-port4: unable to enumerate USB device
10782 10:02:24.948820 <6>[ 14.798097] ALSA device list:
10783 10:02:24.955699 <6>[ 14.801393] No soundcards found.
10784 10:02:24.963933 <6>[ 14.809361] Freeing unused kernel memory: 8384K
10785 10:02:24.966600 <6>[ 14.814365] Run /init as init process
10786 10:02:24.978238 Loading, please wait...
10787 10:02:25.012766 Starting systemd-udevd version 252.6-1
10788 10:02:25.312927 <6>[ 15.155093] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10789 10:02:25.319613 <6>[ 15.156034] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10790 10:02:25.329288 <6>[ 15.162806] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10791 10:02:25.332412 <6>[ 15.178279] remoteproc remoteproc0: scp is available
10792 10:02:25.341761 <6>[ 15.179038] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10793 10:02:25.348585 <6>[ 15.184687] remoteproc remoteproc0: powering up scp
10794 10:02:25.354965 <3>[ 15.188051] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10795 10:02:25.362014 <3>[ 15.188064] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10796 10:02:25.371975 <3>[ 15.188069] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10797 10:02:25.378349 <3>[ 15.193473] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10798 10:02:25.387942 <6>[ 15.198025] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10799 10:02:25.395346 <6>[ 15.202609] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10800 10:02:25.404823 <3>[ 15.206036] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10801 10:02:25.411797 <4>[ 15.208148] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10802 10:02:25.418453 <6>[ 15.214140] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10803 10:02:25.425048 <3>[ 15.222210] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10804 10:02:25.435437 <4>[ 15.226785] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10805 10:02:25.437965 <4>[ 15.226785] Fallback method does not support PEC.
10806 10:02:25.445012 <4>[ 15.237742] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10807 10:02:25.455059 <3>[ 15.238792] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10808 10:02:25.461776 <3>[ 15.247670] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10809 10:02:25.470000 <6>[ 15.253863] usbcore: registered new interface driver r8152
10810 10:02:25.477922 <3>[ 15.254490] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10811 10:02:25.481790 <6>[ 15.260351] mc: Linux media interface: v0.10
10812 10:02:25.488565 <3>[ 15.264816] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10813 10:02:25.498051 <3>[ 15.293952] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10814 10:02:25.504855 <3>[ 15.296908] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10815 10:02:25.514267 <6>[ 15.310111] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10816 10:02:25.521275 <3>[ 15.313693] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10817 10:02:25.527831 <6>[ 15.319428] pci_bus 0000:00: root bus resource [bus 00-ff]
10818 10:02:25.534455 <3>[ 15.327501] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10819 10:02:25.540832 <6>[ 15.332019] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10820 10:02:25.550599 <3>[ 15.340135] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10821 10:02:25.560331 <6>[ 15.348865] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10822 10:02:25.566987 <6>[ 15.349267] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10823 10:02:25.577450 <6>[ 15.355875] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10824 10:02:25.583260 <6>[ 15.356270] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10825 10:02:25.593967 <6>[ 15.356309] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10826 10:02:25.600054 <6>[ 15.356317] remoteproc remoteproc0: remote processor scp is now up
10827 10:02:25.606963 <3>[ 15.356941] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10828 10:02:25.617018 <6>[ 15.357990] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10829 10:02:25.626475 <6>[ 15.358376] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10830 10:02:25.632836 <6>[ 15.363839] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10831 10:02:25.639427 <3>[ 15.371886] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10832 10:02:25.645942 <6>[ 15.372478] videodev: Linux video capture interface: v2.00
10833 10:02:25.653531 <6>[ 15.374828] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10834 10:02:25.662808 <6>[ 15.377630] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10835 10:02:25.669542 <6>[ 15.383153] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10836 10:02:25.679087 <3>[ 15.385714] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10837 10:02:25.685507 <3>[ 15.385722] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10838 10:02:25.695653 <3>[ 15.385806] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10839 10:02:25.698618 <6>[ 15.389214] Bluetooth: Core ver 2.22
10840 10:02:25.702317 <6>[ 15.393093] pci 0000:00:00.0: supports D1 D2
10841 10:02:25.708632 <6>[ 15.401454] NET: Registered PF_BLUETOOTH protocol family
10842 10:02:25.715417 <6>[ 15.401894] usbcore: registered new interface driver cdc_ether
10843 10:02:25.721956 <6>[ 15.411227] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10844 10:02:25.728482 <6>[ 15.411448] usbcore: registered new interface driver r8153_ecm
10845 10:02:25.735399 <6>[ 15.418498] Bluetooth: HCI device and connection manager initialized
10846 10:02:25.741913 <6>[ 15.428814] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10847 10:02:25.748322 <6>[ 15.434781] Bluetooth: HCI socket layer initialized
10848 10:02:25.754614 <6>[ 15.443382] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10849 10:02:25.761386 <6>[ 15.444372] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10850 10:02:25.771704 <6>[ 15.445496] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10851 10:02:25.777941 <6>[ 15.445634] usbcore: registered new interface driver uvcvideo
10852 10:02:25.784387 <6>[ 15.449706] Bluetooth: L2CAP socket layer initialized
10853 10:02:25.791458 <6>[ 15.457811] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10854 10:02:25.797482 <6>[ 15.458362] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10855 10:02:25.807353 <4>[ 15.463757] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10856 10:02:25.814095 <4>[ 15.463767] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10857 10:02:25.821199 <6>[ 15.467865] Bluetooth: SCO socket layer initialized
10858 10:02:25.827398 <6>[ 15.476900] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10859 10:02:25.833652 <6>[ 15.508975] r8152 1-1.1.1:1.0 eth0: v1.12.13
10860 10:02:25.840646 <6>[ 15.512685] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10861 10:02:25.847178 <6>[ 15.526918] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10862 10:02:25.850298 <6>[ 15.529122] pci 0000:01:00.0: supports D1 D2
10863 10:02:25.857174 <6>[ 15.529544] usbcore: registered new interface driver btusb
10864 10:02:25.866833 <4>[ 15.530735] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10865 10:02:25.873926 <3>[ 15.530748] Bluetooth: hci0: Failed to load firmware file (-2)
10866 10:02:25.879817 <3>[ 15.530754] Bluetooth: hci0: Failed to set up firmware (-2)
10867 10:02:25.889722 <4>[ 15.530761] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10868 10:02:25.896243 <6>[ 15.740387] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10869 10:02:25.918387 <6>[ 15.760972] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10870 10:02:25.924983 <6>[ 15.767868] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10871 10:02:25.931687 <6>[ 15.775947] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10872 10:02:25.941330 <6>[ 15.783945] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10873 10:02:25.948334 <6>[ 15.791946] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10874 10:02:25.957762 <6>[ 15.799947] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10875 10:02:25.961818 <6>[ 15.807946] pci 0000:00:00.0: PCI bridge to [bus 01]
10876 10:02:25.971542 <6>[ 15.813162] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10877 10:02:25.977555 <6>[ 15.821283] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10878 10:02:25.984266 <6>[ 15.828089] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10879 10:02:25.990989 <6>[ 15.834835] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10880 10:02:26.005020 <5>[ 15.847952] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10881 10:02:26.029831 <5>[ 15.872577] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10882 10:02:26.036260 <4>[ 15.879525] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10883 10:02:26.042843 <6>[ 15.888439] cfg80211: failed to load regulatory.db
10884 10:02:26.092926 <6>[ 15.935930] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10885 10:02:26.099479 <6>[ 15.943453] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10886 10:02:26.124305 <6>[ 15.970261] mt7921e 0000:01:00.0: ASIC revision: 79610010
10887 10:02:26.229817 <4>[ 16.069144] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10888 10:02:26.236185 Begin: Loading essential drivers ... done.
10889 10:02:26.239954 Begin: Running /scripts/init-premount ... done.
10890 10:02:26.246909 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10891 10:02:26.256399 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10892 10:02:26.260390 Device /sys/class/net/enxf4f5e850de0a found
10893 10:02:26.260945 done.
10894 10:02:26.272563 Begin: Waiting up to 180 secs for any network device to become available ... done.
10895 10:02:26.306345 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10896 10:02:26.349522 <4>[ 16.189042] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10897 10:02:26.469707 <4>[ 16.308740] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10898 10:02:26.589569 <4>[ 16.428594] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10899 10:02:26.709177 <4>[ 16.548605] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10900 10:02:26.829139 <4>[ 16.668461] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10901 10:02:26.949064 <4>[ 16.788570] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10902 10:02:27.069071 <4>[ 16.908432] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10903 10:02:27.188566 <4>[ 17.028540] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10904 10:02:27.308396 <4>[ 17.148350] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10905 10:02:27.329275 <6>[ 17.174736] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
10906 10:02:27.365219 IP-Config: no response after 2 secs - giving up
10907 10:02:27.409938 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10908 10:02:27.421471 <3>[ 17.267358] mt7921e 0000:01:00.0: hardware init failed
10909 10:02:27.427994 IP-Config: enxf4f5e850de0a complete (dhcp from 192.168.201.1):
10910 10:02:27.434672 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10911 10:02:27.441102 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10912 10:02:27.447756 host : mt8192-asurada-spherion-r0-cbg-9
10913 10:02:27.454212 domain : lava-rack
10914 10:02:27.457570 rootserver: 192.168.201.1 rootpath:
10915 10:02:27.460576 filename :
10916 10:02:27.559400 done.
10917 10:02:27.565831 Begin: Running /scripts/nfs-bottom ... done.
10918 10:02:27.585940 Begin: Running /scripts/init-bottom ... done.
10919 10:02:28.913503 <6>[ 18.759972] NET: Registered PF_INET6 protocol family
10920 10:02:28.920979 <6>[ 18.767296] Segment Routing with IPv6
10921 10:02:28.924124 <6>[ 18.771316] In-situ OAM (IOAM) with IPv6
10922 10:02:29.108987 <30>[ 18.928959] systemd[1]: systemd 252.6-1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10923 10:02:29.116014 <30>[ 18.961272] systemd[1]: Detected architecture arm64.
10924 10:02:29.124014
10925 10:02:29.126922 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10926 10:02:29.127485
10927 10:02:29.153289 <30>[ 18.999348] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10928 10:02:30.283169 <30>[ 20.126037] systemd[1]: Queued start job for default target graphical.target.
10929 10:02:30.314963 <30>[ 20.158218] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10930 10:02:30.321572 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10931 10:02:30.343701 <30>[ 20.186923] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10932 10:02:30.353448 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10933 10:02:30.372434 <30>[ 20.214800] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10934 10:02:30.381484 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10935 10:02:30.400301 <30>[ 20.243230] systemd[1]: Created slice user.slice - User and Session Slice.
10936 10:02:30.406403 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10937 10:02:30.429898 <30>[ 20.269978] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10938 10:02:30.439890 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10939 10:02:30.458451 <30>[ 20.297328] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10940 10:02:30.464009 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10941 10:02:30.492993 <30>[ 20.325409] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10942 10:02:30.502091 <30>[ 20.345368] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10943 10:02:30.508871 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10944 10:02:30.526397 <30>[ 20.369559] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10945 10:02:30.536390 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10946 10:02:30.551953 <30>[ 20.397663] systemd[1]: Reached target paths.target - Path Units.
10947 10:02:30.557835 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10948 10:02:30.578943 <30>[ 20.421552] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10949 10:02:30.584859 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10950 10:02:30.598369 <30>[ 20.445087] systemd[1]: Reached target slices.target - Slice Units.
10951 10:02:30.608692 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10952 10:02:30.622939 <30>[ 20.469604] systemd[1]: Reached target swap.target - Swaps.
10953 10:02:30.629817 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10954 10:02:30.650271 <30>[ 20.493626] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10955 10:02:30.660206 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10956 10:02:30.678803 <30>[ 20.522074] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10957 10:02:30.688893 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10958 10:02:30.709677 <30>[ 20.552520] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10959 10:02:30.719193 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10960 10:02:30.735506 <30>[ 20.578735] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10961 10:02:30.745019 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10962 10:02:30.763369 <30>[ 20.606394] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10963 10:02:30.769839 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10964 10:02:30.792474 <30>[ 20.634943] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10965 10:02:30.801520 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10966 10:02:30.822232 <30>[ 20.665525] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10967 10:02:30.831964 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10968 10:02:30.850997 <30>[ 20.693621] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10969 10:02:30.860376 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10970 10:02:30.918065 <30>[ 20.761526] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10971 10:02:30.924937 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10972 10:02:30.944579 <30>[ 20.787881] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10973 10:02:30.950838 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10974 10:02:30.973618 <30>[ 20.817127] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10975 10:02:30.980089 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10976 10:02:31.004514 <30>[ 20.841635] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10977 10:02:31.020755 <30>[ 20.864115] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10978 10:02:31.030683 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10979 10:02:31.051208 <30>[ 20.894636] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10980 10:02:31.057903 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10981 10:02:31.083846 <30>[ 20.926971] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10982 10:02:31.090284 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10983 10:02:31.115198 <30>[ 20.958875] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10984 10:02:31.128482 Starting [0;1;39mmodprobe@drm.service<6>[ 20.970144] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10985 10:02:31.131929 [0m - Load Kernel Module drm...
10986 10:02:31.155214 <30>[ 20.998699] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10987 10:02:31.164765 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10988 10:02:31.187311 <30>[ 21.030833] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10989 10:02:31.194328 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10990 10:02:31.228579 <6>[ 21.074467] fuse: init (API version 7.37)
10991 10:02:31.258722 <30>[ 21.102007] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10992 10:02:31.265322 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10993 10:02:31.295298 <30>[ 21.138472] systemd[1]: Starting systemd-journald.service - Journal Service...
10994 10:02:31.302403 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10995 10:02:31.334199 <30>[ 21.177893] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10996 10:02:31.340802 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10997 10:02:31.370433 <30>[ 21.210734] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10998 10:02:31.376956 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10999 10:02:31.403747 <30>[ 21.247263] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
11000 10:02:31.413929 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
11001 10:02:31.437179 <30>[ 21.280301] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
11002 10:02:31.451383 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug Al<3>[ 21.293730] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11003 10:02:31.454544 l udev Devices...
11004 10:02:31.479935 <30>[ 21.322791] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
11005 10:02:31.489785 [[0;32m OK [0m] Mounted [0;<3>[ 21.332641] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11006 10:02:31.496865 1;39mdev-hugepages.mount[0m - Huge Pages File System.
11007 10:02:31.513968 <30>[ 21.357583] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
11008 10:02:31.520685 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
11009 10:02:31.537689 <30>[ 21.381309] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
11010 10:02:31.544761 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
11011 10:02:31.554422 <3>[ 21.397662] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11012 10:02:31.565095 <30>[ 21.407784] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
11013 10:02:31.574680 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
11014 10:02:31.588473 <3>[ 21.431740] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11015 10:02:31.598705 <30>[ 21.442127] systemd[1]: modprobe@configfs.service: Deactivated successfully.
11016 10:02:31.606174 <30>[ 21.450323] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
11017 10:02:31.623020 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - <3>[ 21.463202] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11018 10:02:31.625841 Load Kernel Module configfs.
11019 10:02:31.643344 <30>[ 21.485882] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
11020 10:02:31.649648 <30>[ 21.493580] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
11021 10:02:31.660239 <3>[ 21.495211] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11022 10:02:31.666197 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
11023 10:02:31.684305 <30>[ 21.530537] systemd[1]: modprobe@drm.service: Deactivated successfully.
11024 10:02:31.694529 <3>[ 21.534698] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11025 10:02:31.700375 <30>[ 21.538035] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
11026 10:02:31.711088 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
11027 10:02:31.726860 <3>[ 21.570322] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11028 10:02:31.737788 <30>[ 21.581231] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
11029 10:02:31.747890 <30>[ 21.589686] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
11030 10:02:31.758539 [[0;32m OK [0m] Finished [0;1;39mmodprobe@e<3>[ 21.602140] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11031 10:02:31.765169 fi_psto…m - Load Kernel Module efi_pstore.
11032 10:02:31.783683 <30>[ 21.626887] systemd[1]: modprobe@fuse.service: Deactivated successfully.
11033 10:02:31.790632 <30>[ 21.634864] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
11034 10:02:31.800763 <3>[ 21.636905] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11035 10:02:31.807279 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
11036 10:02:31.825292 <30>[ 21.671353] systemd[1]: modprobe@loop.service: Deactivated successfully.
11037 10:02:31.835936 <30>[ 21.679441] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
11038 10:02:31.842623 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
11039 10:02:31.865217 <30>[ 21.707670] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
11040 10:02:31.871424 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11041 10:02:31.894782 <4>[ 21.731605] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11042 10:02:31.905312 <3>[ 21.747270] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11043 10:02:31.911223 <30>[ 21.748191] systemd[1]: Started systemd-journald.service - Journal Service.
11044 10:02:31.918209 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11045 10:02:31.943293 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11046 10:02:31.967197 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11047 10:02:31.987334 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11048 10:02:32.008766 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11049 10:02:32.066773 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11050 10:02:32.084852 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11051 10:02:32.107212 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11052 10:02:32.136089 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11053 10:02:32.164874 Startin<46>[ 22.008598] systemd-journald[306]: Received client request to flush runtime journal.
11054 10:02:32.171168 g [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11055 10:02:32.196073 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11056 10:02:32.496031 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11057 10:02:32.514031 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11058 10:02:32.535217 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11059 10:02:32.943256 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11060 10:02:33.579362 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11061 10:02:33.598093 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11062 10:02:33.638518 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11063 10:02:33.719868 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11064 10:02:33.737888 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11065 10:02:33.754287 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11066 10:02:33.803711 Starting [0;1;39msystemd-binfmt.se…et Up Additional Binary Formats...
11067 10:02:33.828344 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11068 10:02:33.854308 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11069 10:02:33.885497 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-bi… Set Up Additional Binary Formats.
11070 10:02:33.897276 See 'systemctl status systemd-binfmt.service' for details.
11071 10:02:34.127417 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11072 10:02:34.203451 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11073 10:02:34.226518 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11074 10:02:34.268226 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11075 10:02:34.356427 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11076 10:02:34.391385 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11077 10:02:34.577625 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11078 10:02:34.610280 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11079 10:02:34.672108 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11080 10:02:34.720778 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11081 10:02:34.764083 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11082 10:02:34.814612 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11083 10:02:34.833532 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11084 10:02:34.853241 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11085 10:02:34.864269 <46>[ 24.711945] systemd-journald[306]: Time jumped backwards, rotating.
11086 10:02:34.877978 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11087 10:02:34.910981 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11088 10:02:34.926601 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11089 10:02:34.945061 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11090 10:02:34.961102 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11091 10:02:34.976869 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11092 10:02:35.617079 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11093 10:02:35.947311 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11094 10:02:35.965898 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11095 10:02:36.305828 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11096 10:02:36.328988 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11097 10:02:36.345199 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11098 10:02:36.694689 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11099 10:02:36.717295 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11100 10:02:36.733635 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11101 10:02:36.797621 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11102 10:02:36.836138 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11103 10:02:36.947223 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11104 10:02:36.976887 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11105 10:02:37.173379 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11106 10:02:37.238242 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11107 10:02:37.263841 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11108 10:02:37.281462 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11109 10:02:37.302211 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11110 10:02:37.341131 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11111 10:02:37.363142 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11112 10:02:37.393904 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11113 10:02:37.409603 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11114 10:02:37.469937 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
11115 10:02:37.496926 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11116 10:02:37.552188 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11117 10:02:37.671919 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11118 10:02:37.758668
11119 10:02:37.759176
11120 10:02:37.761789 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11121 10:02:37.762221
11122 10:02:37.764765 debian-bookworm-arm64 login: root (automatic login)
11123 10:02:37.765177
11124 10:02:37.765546
11125 10:02:38.084202 Linux debian-bookworm-arm64 6.1.62-cip9 #1 SMP PREEMPT Fri Nov 24 09:44:51 UTC 2023 aarch64
11126 10:02:38.084762
11127 10:02:38.090552 The programs included with the Debian GNU/Linux system are free software;
11128 10:02:38.096974 the exact distribution terms for each program are described in the
11129 10:02:38.099917 individual files in /usr/share/doc/*/copyright.
11130 10:02:38.100358
11131 10:02:38.107033 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11132 10:02:38.110185 permitted by applicable law.
11133 10:02:39.190785 Matched prompt #10: / #
11135 10:02:39.191926 Setting prompt string to ['/ #']
11136 10:02:39.192355 end: 2.2.5.1 login-action (duration 00:00:30) [common]
11138 10:02:39.193309 end: 2.2.5 auto-login-action (duration 00:00:30) [common]
11139 10:02:39.193804 start: 2.2.6 expect-shell-connection (timeout 00:03:35) [common]
11140 10:02:39.194157 Setting prompt string to ['/ #']
11141 10:02:39.194468 Forcing a shell prompt, looking for ['/ #']
11143 10:02:39.245256 / #
11144 10:02:39.245974 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11145 10:02:39.246439 Waiting using forced prompt support (timeout 00:02:30)
11146 10:02:39.251952
11147 10:02:39.252887 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11148 10:02:39.253462 start: 2.2.7 export-device-env (timeout 00:03:35) [common]
11150 10:02:39.354796 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12073315/extract-nfsrootfs-ykqohhck'
11151 10:02:39.361540 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12073315/extract-nfsrootfs-ykqohhck'
11153 10:02:39.463178 / # export NFS_SERVER_IP='192.168.201.1'
11154 10:02:39.470120 export NFS_SERVER_IP='192.168.201.1'
11155 10:02:39.471051 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11156 10:02:39.471586 end: 2.2 depthcharge-retry (duration 00:01:25) [common]
11157 10:02:39.472081 end: 2 depthcharge-action (duration 00:01:25) [common]
11158 10:02:39.472587 start: 3 lava-test-retry (timeout 00:07:51) [common]
11159 10:02:39.473047 start: 3.1 lava-test-shell (timeout 00:07:51) [common]
11160 10:02:39.473491 Using namespace: common
11162 10:02:39.574652 / # #
11163 10:02:39.575311 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11164 10:02:39.581071 #
11165 10:02:39.581993 Using /lava-12073315
11167 10:02:39.683244 / # export SHELL=/bin/bash
11168 10:02:39.689879 export SHELL=/bin/bash
11170 10:02:39.791705 / # . /lava-12073315/environment
11171 10:02:39.798440 . /lava-12073315/environment
11173 10:02:39.906305 / # /lava-12073315/bin/lava-test-runner /lava-12073315/0
11174 10:02:39.906962 Test shell timeout: 10s (minimum of the action and connection timeout)
11175 10:02:39.912854 /lava-12073315/bin/lava-test-runner /lava-12073315/0
11176 10:02:40.167536 + export TESTRUN_ID=0_timesync-off
11177 10:02:40.170366 + TESTRUN_ID=0_timesync-off
11178 10:02:40.173662 + cd /lava-12073315/0/tests/0_timesync-off
11179 10:02:40.177327 ++ cat uuid
11180 10:02:40.182606 + UUID=12073315_1.6.2.3.1
11181 10:02:40.182684 + set +x
11182 10:02:40.188921 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12073315_1.6.2.3.1>
11183 10:02:40.189239 Received signal: <STARTRUN> 0_timesync-off 12073315_1.6.2.3.1
11184 10:02:40.189357 Starting test lava.0_timesync-off (12073315_1.6.2.3.1)
11185 10:02:40.189504 Skipping test definition patterns.
11186 10:02:40.192244 + systemctl stop systemd-timesyncd
11187 10:02:40.259395 + set +x
11188 10:02:40.262695 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12073315_1.6.2.3.1>
11189 10:02:40.263378 Received signal: <ENDRUN> 0_timesync-off 12073315_1.6.2.3.1
11190 10:02:40.263808 Ending use of test pattern.
11191 10:02:40.264130 Ending test lava.0_timesync-off (12073315_1.6.2.3.1), duration 0.07
11193 10:02:40.341672 + export TESTRUN_ID=1_kselftest-alsa
11194 10:02:40.344543 + TESTRUN_ID=1_kselftest-alsa
11195 10:02:40.350847 + cd /lava-12073315/0/tests/1_kselftest-alsa
11196 10:02:40.351303 ++ cat uuid
11197 10:02:40.356927 + UUID=12073315_1.6.2.3.5
11198 10:02:40.357295 + set +x
11199 10:02:40.363285 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 12073315_1.6.2.3.5>
11200 10:02:40.363967 Received signal: <STARTRUN> 1_kselftest-alsa 12073315_1.6.2.3.5
11201 10:02:40.364319 Starting test lava.1_kselftest-alsa (12073315_1.6.2.3.5)
11202 10:02:40.364730 Skipping test definition patterns.
11203 10:02:40.366634 + cd ./automated/linux/kselftest/
11204 10:02:40.392659 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11205 10:02:40.442527 INFO: install_deps skipped
11206 10:02:40.950064 --2023-11-24 10:02:40-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11207 10:02:40.956836 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11208 10:02:41.085197 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11209 10:02:41.218500 HTTP request sent, awaiting response... 200 OK
11210 10:02:41.222080 Length: 2964448 (2.8M) [application/octet-stream]
11211 10:02:41.224913 Saving to: 'kselftest.tar.xz'
11212 10:02:41.225489
11213 10:02:41.225853
11214 10:02:41.485308 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11215 10:02:41.752381 kselftest.tar.xz 1%[ ] 47.81K 180KB/s
11216 10:02:42.153166 kselftest.tar.xz 7%[> ] 217.50K 408KB/s
11217 10:02:42.462110 kselftest.tar.xz 30%[=====> ] 876.45K 940KB/s
11218 10:02:42.469068 kselftest.tar.xz 81%[===============> ] 2.31M 1.86MB/s
11219 10:02:42.475459 kselftest.tar.xz 100%[===================>] 2.83M 2.26MB/s in 1.2s
11220 10:02:42.475959
11221 10:02:42.730606 2023-11-24 10:02:42 (2.26 MB/s) - 'kselftest.tar.xz' saved [2964448/2964448]
11222 10:02:42.730755
11223 10:02:47.940197 skiplist:
11224 10:02:47.943703 ========================================
11225 10:02:47.946637 ========================================
11226 10:02:47.994956 alsa:mixer-test
11227 10:02:48.016886 ============== Tests to run ===============
11228 10:02:48.017339 alsa:mixer-test
11229 10:02:48.023317 ===========End Tests to run ===============
11230 10:02:48.026633 shardfile-alsa pass
11231 10:02:48.136503 <12>[ 37.985469] kselftest: Running tests in alsa
11232 10:02:48.146584 TAP version 13
11233 10:02:48.161841 1..1
11234 10:02:48.178483 # selftests: alsa: mixer-test
11235 10:02:48.678371 # TAP version 13
11236 10:02:48.678947 # 1..0
11237 10:02:48.684637 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11238 10:02:48.688175 ok 1 selftests: alsa: mixer-test
11239 10:02:49.424097 alsa_mixer-test pass
11240 10:02:49.474618 + ../../utils/send-to-lava.sh ./output/result.txt
11241 10:02:49.537174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
11242 10:02:49.537501 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
11244 10:02:49.575900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11245 10:02:49.576008 + set +x
11246 10:02:49.576248 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11248 10:02:49.583159 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 12073315_1.6.2.3.5>
11249 10:02:49.583410 Received signal: <ENDRUN> 1_kselftest-alsa 12073315_1.6.2.3.5
11250 10:02:49.583485 Ending use of test pattern.
11251 10:02:49.583547 Ending test lava.1_kselftest-alsa (12073315_1.6.2.3.5), duration 9.22
11253 10:02:49.585988 <LAVA_TEST_RUNNER EXIT>
11254 10:02:49.586333 ok: lava_test_shell seems to have completed
11255 10:02:49.586463 alsa_mixer-test: pass
shardfile-alsa: pass
11256 10:02:49.586566 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11257 10:02:49.586667 end: 3 lava-test-retry (duration 00:00:10) [common]
11258 10:02:49.586768 start: 4 finalize (timeout 00:07:41) [common]
11259 10:02:49.586868 start: 4.1 power-off (timeout 00:00:30) [common]
11260 10:02:49.587020 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11261 10:02:49.664405 >> Command sent successfully.
11262 10:02:49.669898 Returned 0 in 0 seconds
11263 10:02:49.770959 end: 4.1 power-off (duration 00:00:00) [common]
11265 10:02:49.772527 start: 4.2 read-feedback (timeout 00:07:41) [common]
11266 10:02:49.773920 Listened to connection for namespace 'common' for up to 1s
11267 10:02:50.773725 Finalising connection for namespace 'common'
11268 10:02:50.774424 Disconnecting from shell: Finalise
11269 10:02:50.774869 / #
11270 10:02:50.876096 end: 4.2 read-feedback (duration 00:00:01) [common]
11271 10:02:50.876820 end: 4 finalize (duration 00:00:01) [common]
11272 10:02:50.877440 Cleaning after the job
11273 10:02:50.877977 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073315/tftp-deploy-ahuft4sa/ramdisk
11274 10:02:50.892753 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073315/tftp-deploy-ahuft4sa/kernel
11275 10:02:50.929285 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073315/tftp-deploy-ahuft4sa/dtb
11276 10:02:50.929623 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073315/tftp-deploy-ahuft4sa/nfsrootfs
11277 10:02:51.033888 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073315/tftp-deploy-ahuft4sa/modules
11278 10:02:51.041448 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12073315
11279 10:02:51.698513 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12073315
11280 10:02:51.698698 Job finished correctly