Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 39
- Kernel Warnings: 27
- Boot result: PASS
- Errors: 0
1 10:00:26.365431 lava-dispatcher, installed at version: 2023.10
2 10:00:26.365634 start: 0 validate
3 10:00:26.365758 Start time: 2023-11-24 10:00:26.365750+00:00 (UTC)
4 10:00:26.365878 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:00:26.366012 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 10:00:26.626701 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:00:26.627443 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:00:26.897297 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:00:26.898115 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:00:27.168082 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:00:27.168852 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 10:00:27.437772 Using caching service: 'http://localhost/cache/?uri=%s'
13 10:00:27.438302 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 10:00:27.706037 validate duration: 1.34
16 10:00:27.706300 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 10:00:27.706409 start: 1.1 download-retry (timeout 00:10:00) [common]
18 10:00:27.706499 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 10:00:27.706628 Not decompressing ramdisk as can be used compressed.
20 10:00:27.706717 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 10:00:27.706784 saving as /var/lib/lava/dispatcher/tmp/12073307/tftp-deploy-qs3gwgws/ramdisk/initrd.cpio.gz
22 10:00:27.706853 total size: 4665395 (4 MB)
23 10:00:27.707917 progress 0 % (0 MB)
24 10:00:27.709316 progress 5 % (0 MB)
25 10:00:27.710618 progress 10 % (0 MB)
26 10:00:27.711862 progress 15 % (0 MB)
27 10:00:27.713099 progress 20 % (0 MB)
28 10:00:27.714321 progress 25 % (1 MB)
29 10:00:27.715587 progress 30 % (1 MB)
30 10:00:27.716803 progress 35 % (1 MB)
31 10:00:27.718020 progress 40 % (1 MB)
32 10:00:27.719434 progress 45 % (2 MB)
33 10:00:27.720650 progress 50 % (2 MB)
34 10:00:27.721860 progress 55 % (2 MB)
35 10:00:27.723111 progress 60 % (2 MB)
36 10:00:27.724336 progress 65 % (2 MB)
37 10:00:27.725548 progress 70 % (3 MB)
38 10:00:27.726783 progress 75 % (3 MB)
39 10:00:27.728040 progress 80 % (3 MB)
40 10:00:27.729442 progress 85 % (3 MB)
41 10:00:27.730701 progress 90 % (4 MB)
42 10:00:27.731918 progress 95 % (4 MB)
43 10:00:27.733149 progress 100 % (4 MB)
44 10:00:27.733305 4 MB downloaded in 0.03 s (168.21 MB/s)
45 10:00:27.733459 end: 1.1.1 http-download (duration 00:00:00) [common]
47 10:00:27.733703 end: 1.1 download-retry (duration 00:00:00) [common]
48 10:00:27.733792 start: 1.2 download-retry (timeout 00:10:00) [common]
49 10:00:27.733878 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 10:00:27.734010 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 10:00:27.734085 saving as /var/lib/lava/dispatcher/tmp/12073307/tftp-deploy-qs3gwgws/kernel/Image
52 10:00:27.734148 total size: 49107456 (46 MB)
53 10:00:27.734210 No compression specified
54 10:00:27.735367 progress 0 % (0 MB)
55 10:00:27.747801 progress 5 % (2 MB)
56 10:00:27.760287 progress 10 % (4 MB)
57 10:00:27.772882 progress 15 % (7 MB)
58 10:00:27.785484 progress 20 % (9 MB)
59 10:00:27.797883 progress 25 % (11 MB)
60 10:00:27.810335 progress 30 % (14 MB)
61 10:00:27.822934 progress 35 % (16 MB)
62 10:00:27.835550 progress 40 % (18 MB)
63 10:00:27.848230 progress 45 % (21 MB)
64 10:00:27.860922 progress 50 % (23 MB)
65 10:00:27.873493 progress 55 % (25 MB)
66 10:00:27.886104 progress 60 % (28 MB)
67 10:00:27.898487 progress 65 % (30 MB)
68 10:00:27.910827 progress 70 % (32 MB)
69 10:00:27.923047 progress 75 % (35 MB)
70 10:00:27.935520 progress 80 % (37 MB)
71 10:00:27.948047 progress 85 % (39 MB)
72 10:00:27.960743 progress 90 % (42 MB)
73 10:00:27.973145 progress 95 % (44 MB)
74 10:00:27.985528 progress 100 % (46 MB)
75 10:00:27.985775 46 MB downloaded in 0.25 s (186.12 MB/s)
76 10:00:27.985937 end: 1.2.1 http-download (duration 00:00:00) [common]
78 10:00:27.986173 end: 1.2 download-retry (duration 00:00:00) [common]
79 10:00:27.986268 start: 1.3 download-retry (timeout 00:10:00) [common]
80 10:00:27.986357 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 10:00:27.986539 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 10:00:27.986612 saving as /var/lib/lava/dispatcher/tmp/12073307/tftp-deploy-qs3gwgws/dtb/mt8192-asurada-spherion-r0.dtb
83 10:00:27.986676 total size: 47278 (0 MB)
84 10:00:27.986740 No compression specified
85 10:00:27.987869 progress 69 % (0 MB)
86 10:00:27.988147 progress 100 % (0 MB)
87 10:00:27.988303 0 MB downloaded in 0.00 s (27.76 MB/s)
88 10:00:27.988427 end: 1.3.1 http-download (duration 00:00:00) [common]
90 10:00:27.988658 end: 1.3 download-retry (duration 00:00:00) [common]
91 10:00:27.988749 start: 1.4 download-retry (timeout 00:10:00) [common]
92 10:00:27.988833 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 10:00:27.988944 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 10:00:27.989014 saving as /var/lib/lava/dispatcher/tmp/12073307/tftp-deploy-qs3gwgws/nfsrootfs/full.rootfs.tar
95 10:00:27.989076 total size: 200813988 (191 MB)
96 10:00:27.989139 Using unxz to decompress xz
97 10:00:27.992710 progress 0 % (0 MB)
98 10:00:28.519048 progress 5 % (9 MB)
99 10:00:29.030160 progress 10 % (19 MB)
100 10:00:29.609746 progress 15 % (28 MB)
101 10:00:29.978622 progress 20 % (38 MB)
102 10:00:30.300095 progress 25 % (47 MB)
103 10:00:30.886489 progress 30 % (57 MB)
104 10:00:31.435663 progress 35 % (67 MB)
105 10:00:32.027269 progress 40 % (76 MB)
106 10:00:32.607692 progress 45 % (86 MB)
107 10:00:33.187236 progress 50 % (95 MB)
108 10:00:33.813150 progress 55 % (105 MB)
109 10:00:34.479057 progress 60 % (114 MB)
110 10:00:34.596776 progress 65 % (124 MB)
111 10:00:34.741348 progress 70 % (134 MB)
112 10:00:34.838512 progress 75 % (143 MB)
113 10:00:34.909845 progress 80 % (153 MB)
114 10:00:34.978727 progress 85 % (162 MB)
115 10:00:35.080110 progress 90 % (172 MB)
116 10:00:35.364582 progress 95 % (181 MB)
117 10:00:35.935358 progress 100 % (191 MB)
118 10:00:35.940594 191 MB downloaded in 7.95 s (24.08 MB/s)
119 10:00:35.940837 end: 1.4.1 http-download (duration 00:00:08) [common]
121 10:00:35.941094 end: 1.4 download-retry (duration 00:00:08) [common]
122 10:00:35.941185 start: 1.5 download-retry (timeout 00:09:52) [common]
123 10:00:35.941272 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 10:00:35.941416 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 10:00:35.941489 saving as /var/lib/lava/dispatcher/tmp/12073307/tftp-deploy-qs3gwgws/modules/modules.tar
126 10:00:35.941557 total size: 8622040 (8 MB)
127 10:00:35.941639 Using unxz to decompress xz
128 10:00:35.945300 progress 0 % (0 MB)
129 10:00:35.966314 progress 5 % (0 MB)
130 10:00:35.990006 progress 10 % (0 MB)
131 10:00:36.013504 progress 15 % (1 MB)
132 10:00:36.036624 progress 20 % (1 MB)
133 10:00:36.060127 progress 25 % (2 MB)
134 10:00:36.085479 progress 30 % (2 MB)
135 10:00:36.111318 progress 35 % (2 MB)
136 10:00:36.134253 progress 40 % (3 MB)
137 10:00:36.157917 progress 45 % (3 MB)
138 10:00:36.182761 progress 50 % (4 MB)
139 10:00:36.206987 progress 55 % (4 MB)
140 10:00:36.231532 progress 60 % (4 MB)
141 10:00:36.258510 progress 65 % (5 MB)
142 10:00:36.283393 progress 70 % (5 MB)
143 10:00:36.307665 progress 75 % (6 MB)
144 10:00:36.334668 progress 80 % (6 MB)
145 10:00:36.360177 progress 85 % (7 MB)
146 10:00:36.385208 progress 90 % (7 MB)
147 10:00:36.414663 progress 95 % (7 MB)
148 10:00:36.444403 progress 100 % (8 MB)
149 10:00:36.449250 8 MB downloaded in 0.51 s (16.20 MB/s)
150 10:00:36.449524 end: 1.5.1 http-download (duration 00:00:01) [common]
152 10:00:36.449785 end: 1.5 download-retry (duration 00:00:01) [common]
153 10:00:36.449877 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 10:00:36.449976 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 10:00:39.624531 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12073307/extract-nfsrootfs-s5xwbqap
156 10:00:39.624741 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 10:00:39.624843 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 10:00:39.625015 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_
159 10:00:39.625140 makedir: /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_/lava-12073307/bin
160 10:00:39.625238 makedir: /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_/lava-12073307/tests
161 10:00:39.625333 makedir: /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_/lava-12073307/results
162 10:00:39.625435 Creating /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_/lava-12073307/bin/lava-add-keys
163 10:00:39.625573 Creating /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_/lava-12073307/bin/lava-add-sources
164 10:00:39.625696 Creating /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_/lava-12073307/bin/lava-background-process-start
165 10:00:39.625818 Creating /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_/lava-12073307/bin/lava-background-process-stop
166 10:00:39.625943 Creating /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_/lava-12073307/bin/lava-common-functions
167 10:00:39.626061 Creating /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_/lava-12073307/bin/lava-echo-ipv4
168 10:00:39.626181 Creating /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_/lava-12073307/bin/lava-install-packages
169 10:00:39.626300 Creating /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_/lava-12073307/bin/lava-installed-packages
170 10:00:39.626463 Creating /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_/lava-12073307/bin/lava-os-build
171 10:00:39.626584 Creating /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_/lava-12073307/bin/lava-probe-channel
172 10:00:39.626703 Creating /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_/lava-12073307/bin/lava-probe-ip
173 10:00:39.626823 Creating /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_/lava-12073307/bin/lava-target-ip
174 10:00:39.626941 Creating /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_/lava-12073307/bin/lava-target-mac
175 10:00:39.627058 Creating /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_/lava-12073307/bin/lava-target-storage
176 10:00:39.627223 Creating /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_/lava-12073307/bin/lava-test-case
177 10:00:39.627345 Creating /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_/lava-12073307/bin/lava-test-event
178 10:00:39.627466 Creating /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_/lava-12073307/bin/lava-test-feedback
179 10:00:39.627584 Creating /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_/lava-12073307/bin/lava-test-raise
180 10:00:39.627702 Creating /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_/lava-12073307/bin/lava-test-reference
181 10:00:39.627820 Creating /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_/lava-12073307/bin/lava-test-runner
182 10:00:39.627939 Creating /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_/lava-12073307/bin/lava-test-set
183 10:00:39.628058 Creating /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_/lava-12073307/bin/lava-test-shell
184 10:00:39.628179 Updating /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_/lava-12073307/bin/lava-add-keys (debian)
185 10:00:39.628330 Updating /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_/lava-12073307/bin/lava-add-sources (debian)
186 10:00:39.628472 Updating /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_/lava-12073307/bin/lava-install-packages (debian)
187 10:00:39.628609 Updating /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_/lava-12073307/bin/lava-installed-packages (debian)
188 10:00:39.628745 Updating /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_/lava-12073307/bin/lava-os-build (debian)
189 10:00:39.628866 Creating /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_/lava-12073307/environment
190 10:00:39.628963 LAVA metadata
191 10:00:39.629033 - LAVA_JOB_ID=12073307
192 10:00:39.629096 - LAVA_DISPATCHER_IP=192.168.201.1
193 10:00:39.629193 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 10:00:39.629264 skipped lava-vland-overlay
195 10:00:39.629337 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 10:00:39.629416 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 10:00:39.629477 skipped lava-multinode-overlay
198 10:00:39.629549 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 10:00:39.629627 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 10:00:39.629700 Loading test definitions
201 10:00:39.629787 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 10:00:39.629857 Using /lava-12073307 at stage 0
203 10:00:39.630119 uuid=12073307_1.6.2.3.1 testdef=None
204 10:00:39.630207 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 10:00:39.630292 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 10:00:39.630920 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 10:00:39.631145 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 10:00:39.631686 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 10:00:39.631955 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 10:00:39.632513 runner path: /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_/lava-12073307/0/tests/0_timesync-off test_uuid 12073307_1.6.2.3.1
213 10:00:39.632713 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 10:00:39.632970 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 10:00:39.633046 Using /lava-12073307 at stage 0
217 10:00:39.633148 Fetching tests from https://github.com/kernelci/test-definitions.git
218 10:00:39.633288 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_/lava-12073307/0/tests/1_kselftest-dt'
219 10:00:56.187121 Running '/usr/bin/git checkout kernelci.org
220 10:00:56.314814 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_/lava-12073307/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
221 10:00:56.315532 uuid=12073307_1.6.2.3.5 testdef=None
222 10:00:56.315695 end: 1.6.2.3.5 git-repo-action (duration 00:00:17) [common]
224 10:00:56.315946 start: 1.6.2.3.6 test-overlay (timeout 00:09:31) [common]
225 10:00:56.316701 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 10:00:56.316933 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:31) [common]
228 10:00:56.317886 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 10:00:56.318121 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:31) [common]
231 10:00:56.319088 runner path: /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_/lava-12073307/0/tests/1_kselftest-dt test_uuid 12073307_1.6.2.3.5
232 10:00:56.319179 BOARD='mt8192-asurada-spherion-r0'
233 10:00:56.319245 BRANCH='cip'
234 10:00:56.319306 SKIPFILE='/dev/null'
235 10:00:56.319365 SKIP_INSTALL='True'
236 10:00:56.319422 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 10:00:56.319481 TST_CASENAME=''
238 10:00:56.319537 TST_CMDFILES='dt'
239 10:00:56.319675 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 10:00:56.319884 Creating lava-test-runner.conf files
242 10:00:56.319951 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12073307/lava-overlay-fmi4hyc_/lava-12073307/0 for stage 0
243 10:00:56.320043 - 0_timesync-off
244 10:00:56.320113 - 1_kselftest-dt
245 10:00:56.320209 end: 1.6.2.3 test-definition (duration 00:00:17) [common]
246 10:00:56.320298 start: 1.6.2.4 compress-overlay (timeout 00:09:31) [common]
247 10:01:03.775342 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 10:01:03.775539 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:24) [common]
249 10:01:03.775632 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 10:01:03.775736 end: 1.6.2 lava-overlay (duration 00:00:24) [common]
251 10:01:03.775829 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:24) [common]
252 10:01:03.891252 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 10:01:03.891694 start: 1.6.4 extract-modules (timeout 00:09:24) [common]
254 10:01:03.891850 extracting modules file /var/lib/lava/dispatcher/tmp/12073307/tftp-deploy-qs3gwgws/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12073307/extract-nfsrootfs-s5xwbqap
255 10:01:04.100026 extracting modules file /var/lib/lava/dispatcher/tmp/12073307/tftp-deploy-qs3gwgws/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12073307/extract-overlay-ramdisk-8yq1057r/ramdisk
256 10:01:04.307615 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 10:01:04.307787 start: 1.6.5 apply-overlay-tftp (timeout 00:09:23) [common]
258 10:01:04.307891 [common] Applying overlay to NFS
259 10:01:04.307964 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12073307/compress-overlay-5cidx2cs/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12073307/extract-nfsrootfs-s5xwbqap
260 10:01:05.217195 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 10:01:05.217360 start: 1.6.6 configure-preseed-file (timeout 00:09:22) [common]
262 10:01:05.217458 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 10:01:05.217551 start: 1.6.7 compress-ramdisk (timeout 00:09:22) [common]
264 10:01:05.217634 Building ramdisk /var/lib/lava/dispatcher/tmp/12073307/extract-overlay-ramdisk-8yq1057r/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12073307/extract-overlay-ramdisk-8yq1057r/ramdisk
265 10:01:05.537172 >> 119398 blocks
266 10:01:07.463956 rename /var/lib/lava/dispatcher/tmp/12073307/extract-overlay-ramdisk-8yq1057r/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12073307/tftp-deploy-qs3gwgws/ramdisk/ramdisk.cpio.gz
267 10:01:07.464371 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 10:01:07.464491 start: 1.6.8 prepare-kernel (timeout 00:09:20) [common]
269 10:01:07.464597 start: 1.6.8.1 prepare-fit (timeout 00:09:20) [common]
270 10:01:07.464704 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12073307/tftp-deploy-qs3gwgws/kernel/Image'
271 10:01:19.806072 Returned 0 in 12 seconds
272 10:01:19.906704 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12073307/tftp-deploy-qs3gwgws/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12073307/tftp-deploy-qs3gwgws/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12073307/tftp-deploy-qs3gwgws/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12073307/tftp-deploy-qs3gwgws/kernel/image.itb
273 10:01:20.222513 output: FIT description: Kernel Image image with one or more FDT blobs
274 10:01:20.222871 output: Created: Fri Nov 24 10:01:20 2023
275 10:01:20.222951 output: Image 0 (kernel-1)
276 10:01:20.223025 output: Description:
277 10:01:20.223093 output: Created: Fri Nov 24 10:01:20 2023
278 10:01:20.223156 output: Type: Kernel Image
279 10:01:20.223223 output: Compression: lzma compressed
280 10:01:20.223283 output: Data Size: 11047542 Bytes = 10788.62 KiB = 10.54 MiB
281 10:01:20.223341 output: Architecture: AArch64
282 10:01:20.223412 output: OS: Linux
283 10:01:20.223472 output: Load Address: 0x00000000
284 10:01:20.223529 output: Entry Point: 0x00000000
285 10:01:20.223593 output: Hash algo: crc32
286 10:01:20.223653 output: Hash value: 2edffaa3
287 10:01:20.223710 output: Image 1 (fdt-1)
288 10:01:20.223766 output: Description: mt8192-asurada-spherion-r0
289 10:01:20.223824 output: Created: Fri Nov 24 10:01:20 2023
290 10:01:20.223878 output: Type: Flat Device Tree
291 10:01:20.223932 output: Compression: uncompressed
292 10:01:20.224019 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 10:01:20.224104 output: Architecture: AArch64
294 10:01:20.224191 output: Hash algo: crc32
295 10:01:20.224275 output: Hash value: cc4352de
296 10:01:20.224362 output: Image 2 (ramdisk-1)
297 10:01:20.224446 output: Description: unavailable
298 10:01:20.224530 output: Created: Fri Nov 24 10:01:20 2023
299 10:01:20.224619 output: Type: RAMDisk Image
300 10:01:20.224675 output: Compression: Unknown Compression
301 10:01:20.224743 output: Data Size: 17801871 Bytes = 17384.64 KiB = 16.98 MiB
302 10:01:20.224811 output: Architecture: AArch64
303 10:01:20.224866 output: OS: Linux
304 10:01:20.224925 output: Load Address: unavailable
305 10:01:20.225007 output: Entry Point: unavailable
306 10:01:20.225063 output: Hash algo: crc32
307 10:01:20.225131 output: Hash value: 0b2352b6
308 10:01:20.225199 output: Default Configuration: 'conf-1'
309 10:01:20.225253 output: Configuration 0 (conf-1)
310 10:01:20.225317 output: Description: mt8192-asurada-spherion-r0
311 10:01:20.225388 output: Kernel: kernel-1
312 10:01:20.225443 output: Init Ramdisk: ramdisk-1
313 10:01:20.225503 output: FDT: fdt-1
314 10:01:20.225583 output: Loadables: kernel-1
315 10:01:20.225638 output:
316 10:01:20.225862 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 10:01:20.226006 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 10:01:20.226160 end: 1.6 prepare-tftp-overlay (duration 00:00:44) [common]
319 10:01:20.226300 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:07) [common]
320 10:01:20.226432 No LXC device requested
321 10:01:20.226565 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 10:01:20.226663 start: 1.8 deploy-device-env (timeout 00:09:07) [common]
323 10:01:20.226760 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 10:01:20.226834 Checking files for TFTP limit of 4294967296 bytes.
325 10:01:20.227406 end: 1 tftp-deploy (duration 00:00:53) [common]
326 10:01:20.227554 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 10:01:20.227698 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 10:01:20.227880 substitutions:
329 10:01:20.227979 - {DTB}: 12073307/tftp-deploy-qs3gwgws/dtb/mt8192-asurada-spherion-r0.dtb
330 10:01:20.228076 - {INITRD}: 12073307/tftp-deploy-qs3gwgws/ramdisk/ramdisk.cpio.gz
331 10:01:20.228138 - {KERNEL}: 12073307/tftp-deploy-qs3gwgws/kernel/Image
332 10:01:20.228213 - {LAVA_MAC}: None
333 10:01:20.228283 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12073307/extract-nfsrootfs-s5xwbqap
334 10:01:20.228343 - {NFS_SERVER_IP}: 192.168.201.1
335 10:01:20.228431 - {PRESEED_CONFIG}: None
336 10:01:20.228492 - {PRESEED_LOCAL}: None
337 10:01:20.228549 - {RAMDISK}: 12073307/tftp-deploy-qs3gwgws/ramdisk/ramdisk.cpio.gz
338 10:01:20.228647 - {ROOT_PART}: None
339 10:01:20.228705 - {ROOT}: None
340 10:01:20.228779 - {SERVER_IP}: 192.168.201.1
341 10:01:20.228847 - {TEE}: None
342 10:01:20.228903 Parsed boot commands:
343 10:01:20.228966 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 10:01:20.229180 Parsed boot commands: tftpboot 192.168.201.1 12073307/tftp-deploy-qs3gwgws/kernel/image.itb 12073307/tftp-deploy-qs3gwgws/kernel/cmdline
345 10:01:20.229301 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 10:01:20.229437 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 10:01:20.229573 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 10:01:20.229699 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 10:01:20.229819 Not connected, no need to disconnect.
350 10:01:20.229938 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 10:01:20.230036 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 10:01:20.230116 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
353 10:01:20.233745 Setting prompt string to ['lava-test: # ']
354 10:01:20.234192 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 10:01:20.234357 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 10:01:20.234526 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 10:01:20.234662 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 10:01:20.235026 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
359 10:01:25.365448 >> Command sent successfully.
360 10:01:25.367889 Returned 0 in 5 seconds
361 10:01:25.468287 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 10:01:25.468632 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 10:01:25.468733 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 10:01:25.468825 Setting prompt string to 'Starting depthcharge on Spherion...'
366 10:01:25.468894 Changing prompt to 'Starting depthcharge on Spherion...'
367 10:01:25.468962 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 10:01:25.469230 [Enter `^Ec?' for help]
369 10:01:25.644554
370 10:01:25.644689
371 10:01:25.644764 F0: 102B 0000
372 10:01:25.644830
373 10:01:25.644891 F3: 1001 0000 [0200]
374 10:01:25.647722
375 10:01:25.647809 F3: 1001 0000
376 10:01:25.647875
377 10:01:25.647937 F7: 102D 0000
378 10:01:25.647998
379 10:01:25.651247 F1: 0000 0000
380 10:01:25.651332
381 10:01:25.651400 V0: 0000 0000 [0001]
382 10:01:25.651463
383 10:01:25.654729 00: 0007 8000
384 10:01:25.654816
385 10:01:25.654883 01: 0000 0000
386 10:01:25.654948
387 10:01:25.658212 BP: 0C00 0209 [0000]
388 10:01:25.658327
389 10:01:25.658454 G0: 1182 0000
390 10:01:25.658520
391 10:01:25.661564 EC: 0000 0021 [4000]
392 10:01:25.661647
393 10:01:25.661715 S7: 0000 0000 [0000]
394 10:01:25.661776
395 10:01:25.665185 CC: 0000 0000 [0001]
396 10:01:25.665282
397 10:01:25.665384 T0: 0000 0040 [010F]
398 10:01:25.665478
399 10:01:25.665577 Jump to BL
400 10:01:25.665671
401 10:01:25.691615
402 10:01:25.691702
403 10:01:25.691769
404 10:01:25.698867 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 10:01:25.702413 ARM64: Exception handlers installed.
406 10:01:25.706911 ARM64: Testing exception
407 10:01:25.709804 ARM64: Done test exception
408 10:01:25.716497 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 10:01:25.726947 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 10:01:25.733336 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 10:01:25.743737 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 10:01:25.750364 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 10:01:25.756875 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 10:01:25.768511 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 10:01:25.775437 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 10:01:25.794889 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 10:01:25.798025 WDT: Last reset was cold boot
418 10:01:25.801220 SPI1(PAD0) initialized at 2873684 Hz
419 10:01:25.804635 SPI5(PAD0) initialized at 992727 Hz
420 10:01:25.807720 VBOOT: Loading verstage.
421 10:01:25.814753 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 10:01:25.818263 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 10:01:25.821311 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 10:01:25.824216 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 10:01:25.831792 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 10:01:25.838862 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 10:01:25.849507 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 10:01:25.849592
429 10:01:25.849659
430 10:01:25.859551 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 10:01:25.863099 ARM64: Exception handlers installed.
432 10:01:25.866124 ARM64: Testing exception
433 10:01:25.866240 ARM64: Done test exception
434 10:01:25.872857 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 10:01:25.876840 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 10:01:25.890578 Probing TPM: . done!
437 10:01:25.890664 TPM ready after 0 ms
438 10:01:25.897502 Connected to device vid:did:rid of 1ae0:0028:00
439 10:01:25.904636 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 10:01:25.960500 Initialized TPM device CR50 revision 0
441 10:01:25.972484 tlcl_send_startup: Startup return code is 0
442 10:01:25.972588 TPM: setup succeeded
443 10:01:25.983705 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 10:01:25.992681 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 10:01:26.002520 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 10:01:26.012306 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 10:01:26.015499 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 10:01:26.024305 in-header: 03 07 00 00 08 00 00 00
449 10:01:26.027890 in-data: aa e4 47 04 13 02 00 00
450 10:01:26.031725 Chrome EC: UHEPI supported
451 10:01:26.038639 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 10:01:26.042590 in-header: 03 ad 00 00 08 00 00 00
453 10:01:26.045777 in-data: 00 20 20 08 00 00 00 00
454 10:01:26.045863 Phase 1
455 10:01:26.049463 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 10:01:26.056992 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 10:01:26.060570 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 10:01:26.064459 Recovery requested (1009000e)
459 10:01:26.073447 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 10:01:26.078907 tlcl_extend: response is 0
461 10:01:26.088627 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 10:01:26.093471 tlcl_extend: response is 0
463 10:01:26.101024 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 10:01:26.121548 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 10:01:26.128348 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 10:01:26.128456
467 10:01:26.128551
468 10:01:26.138680 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 10:01:26.141531 ARM64: Exception handlers installed.
470 10:01:26.141603 ARM64: Testing exception
471 10:01:26.145048 ARM64: Done test exception
472 10:01:26.167047 pmic_efuse_setting: Set efuses in 11 msecs
473 10:01:26.170572 pmwrap_interface_init: Select PMIF_VLD_RDY
474 10:01:26.176901 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 10:01:26.180430 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 10:01:26.183588 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 10:01:26.190580 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 10:01:26.194097 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 10:01:26.201315 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 10:01:26.205045 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 10:01:26.209029 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 10:01:26.212711 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 10:01:26.219811 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 10:01:26.223825 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 10:01:26.227170 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 10:01:26.233958 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 10:01:26.237387 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 10:01:26.244012 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 10:01:26.250927 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 10:01:26.254620 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 10:01:26.261827 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 10:01:26.266172 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 10:01:26.272390 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 10:01:26.279661 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 10:01:26.283327 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 10:01:26.290029 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 10:01:26.293172 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 10:01:26.299819 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 10:01:26.306948 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 10:01:26.310004 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 10:01:26.316727 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 10:01:26.320009 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 10:01:26.326569 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 10:01:26.330061 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 10:01:26.336963 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 10:01:26.339985 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 10:01:26.346736 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 10:01:26.349854 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 10:01:26.356927 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 10:01:26.360249 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 10:01:26.366822 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 10:01:26.369958 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 10:01:26.373486 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 10:01:26.377181 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 10:01:26.384116 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 10:01:26.387802 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 10:01:26.391253 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 10:01:26.397518 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 10:01:26.401148 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 10:01:26.404366 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 10:01:26.407692 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 10:01:26.414066 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 10:01:26.417468 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 10:01:26.420806 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 10:01:26.430988 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 10:01:26.437641 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 10:01:26.441361 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 10:01:26.451317 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 10:01:26.457564 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 10:01:26.464443 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 10:01:26.467923 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 10:01:26.471136 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 10:01:26.479052 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
534 10:01:26.485761 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 10:01:26.489248 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 10:01:26.492252 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 10:01:26.503722 [RTC]rtc_get_frequency_meter,154: input=15, output=772
538 10:01:26.514082 [RTC]rtc_get_frequency_meter,154: input=23, output=956
539 10:01:26.522611 [RTC]rtc_get_frequency_meter,154: input=19, output=866
540 10:01:26.532386 [RTC]rtc_get_frequency_meter,154: input=17, output=819
541 10:01:26.541667 [RTC]rtc_get_frequency_meter,154: input=16, output=794
542 10:01:26.544949 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
543 10:01:26.551910 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
544 10:01:26.554850 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
545 10:01:26.558651 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
546 10:01:26.561884 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
547 10:01:26.565058 ADC[4]: Raw value=903245 ID=7
548 10:01:26.568140 ADC[3]: Raw value=213179 ID=1
549 10:01:26.572010 RAM Code: 0x71
550 10:01:26.575456 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
551 10:01:26.578245 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
552 10:01:26.589252 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
553 10:01:26.596386 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 10:01:26.596472 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
555 10:01:26.600444 in-header: 03 07 00 00 08 00 00 00
556 10:01:26.604276 in-data: aa e4 47 04 13 02 00 00
557 10:01:26.608064 Chrome EC: UHEPI supported
558 10:01:26.615489 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
559 10:01:26.618985 in-header: 03 ed 00 00 08 00 00 00
560 10:01:26.623454 in-data: 80 20 60 08 00 00 00 00
561 10:01:26.623540 MRC: failed to locate region type 0.
562 10:01:26.630937 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
563 10:01:26.633998 DRAM-K: Running full calibration
564 10:01:26.641537 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
565 10:01:26.641646 header.status = 0x0
566 10:01:26.645183 header.version = 0x6 (expected: 0x6)
567 10:01:26.648468 header.size = 0xd00 (expected: 0xd00)
568 10:01:26.648569 header.flags = 0x0
569 10:01:26.655121 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
570 10:01:26.674080 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
571 10:01:26.680610 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
572 10:01:26.684427 dram_init: ddr_geometry: 2
573 10:01:26.687607 [EMI] MDL number = 2
574 10:01:26.687692 [EMI] Get MDL freq = 0
575 10:01:26.690662 dram_init: ddr_type: 0
576 10:01:26.690761 is_discrete_lpddr4: 1
577 10:01:26.693962 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
578 10:01:26.694065
579 10:01:26.694159
580 10:01:26.697471 [Bian_co] ETT version 0.0.0.1
581 10:01:26.704907 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
582 10:01:26.705014
583 10:01:26.708653 dramc_set_vcore_voltage set vcore to 650000
584 10:01:26.708742 Read voltage for 800, 4
585 10:01:26.708837 Vio18 = 0
586 10:01:26.712413 Vcore = 650000
587 10:01:26.712519 Vdram = 0
588 10:01:26.712643 Vddq = 0
589 10:01:26.712739 Vmddr = 0
590 10:01:26.716232 dram_init: config_dvfs: 1
591 10:01:26.720189 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
592 10:01:26.727753 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
593 10:01:26.730874 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
594 10:01:26.734643 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
595 10:01:26.737532 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
596 10:01:26.740723 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
597 10:01:26.744264 MEM_TYPE=3, freq_sel=18
598 10:01:26.747736 sv_algorithm_assistance_LP4_1600
599 10:01:26.751271 ============ PULL DRAM RESETB DOWN ============
600 10:01:26.754642 ========== PULL DRAM RESETB DOWN end =========
601 10:01:26.761107 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
602 10:01:26.764285 ===================================
603 10:01:26.764365 LPDDR4 DRAM CONFIGURATION
604 10:01:26.768101 ===================================
605 10:01:26.771043 EX_ROW_EN[0] = 0x0
606 10:01:26.774476 EX_ROW_EN[1] = 0x0
607 10:01:26.774553 LP4Y_EN = 0x0
608 10:01:26.777667 WORK_FSP = 0x0
609 10:01:26.777742 WL = 0x2
610 10:01:26.781309 RL = 0x2
611 10:01:26.781394 BL = 0x2
612 10:01:26.784569 RPST = 0x0
613 10:01:26.784654 RD_PRE = 0x0
614 10:01:26.788005 WR_PRE = 0x1
615 10:01:26.788090 WR_PST = 0x0
616 10:01:26.791297 DBI_WR = 0x0
617 10:01:26.791381 DBI_RD = 0x0
618 10:01:26.794957 OTF = 0x1
619 10:01:26.797991 ===================================
620 10:01:26.801357 ===================================
621 10:01:26.801443 ANA top config
622 10:01:26.804446 ===================================
623 10:01:26.808015 DLL_ASYNC_EN = 0
624 10:01:26.811506 ALL_SLAVE_EN = 1
625 10:01:26.811592 NEW_RANK_MODE = 1
626 10:01:26.814521 DLL_IDLE_MODE = 1
627 10:01:26.817790 LP45_APHY_COMB_EN = 1
628 10:01:26.821203 TX_ODT_DIS = 1
629 10:01:26.824779 NEW_8X_MODE = 1
630 10:01:26.828008 ===================================
631 10:01:26.831090 ===================================
632 10:01:26.831176 data_rate = 1600
633 10:01:26.834589 CKR = 1
634 10:01:26.837920 DQ_P2S_RATIO = 8
635 10:01:26.841378 ===================================
636 10:01:26.844552 CA_P2S_RATIO = 8
637 10:01:26.847835 DQ_CA_OPEN = 0
638 10:01:26.851471 DQ_SEMI_OPEN = 0
639 10:01:26.851555 CA_SEMI_OPEN = 0
640 10:01:26.854341 CA_FULL_RATE = 0
641 10:01:26.858078 DQ_CKDIV4_EN = 1
642 10:01:26.861272 CA_CKDIV4_EN = 1
643 10:01:26.864513 CA_PREDIV_EN = 0
644 10:01:26.864597 PH8_DLY = 0
645 10:01:26.867858 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
646 10:01:26.871248 DQ_AAMCK_DIV = 4
647 10:01:26.874739 CA_AAMCK_DIV = 4
648 10:01:26.877891 CA_ADMCK_DIV = 4
649 10:01:26.881241 DQ_TRACK_CA_EN = 0
650 10:01:26.884628 CA_PICK = 800
651 10:01:26.884712 CA_MCKIO = 800
652 10:01:26.887674 MCKIO_SEMI = 0
653 10:01:26.891273 PLL_FREQ = 3068
654 10:01:26.894400 DQ_UI_PI_RATIO = 32
655 10:01:26.897843 CA_UI_PI_RATIO = 0
656 10:01:26.901294 ===================================
657 10:01:26.904328 ===================================
658 10:01:26.908103 memory_type:LPDDR4
659 10:01:26.908187 GP_NUM : 10
660 10:01:26.911151 SRAM_EN : 1
661 10:01:26.911234 MD32_EN : 0
662 10:01:26.914618 ===================================
663 10:01:26.918286 [ANA_INIT] >>>>>>>>>>>>>>
664 10:01:26.921842 <<<<<< [CONFIGURE PHASE]: ANA_TX
665 10:01:26.925694 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
666 10:01:26.929780 ===================================
667 10:01:26.929866 data_rate = 1600,PCW = 0X7600
668 10:01:26.933085 ===================================
669 10:01:26.937195 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
670 10:01:26.944162 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
671 10:01:26.947781 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
672 10:01:26.951400 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
673 10:01:26.954839 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
674 10:01:26.958483 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
675 10:01:26.961627 [ANA_INIT] flow start
676 10:01:26.964644 [ANA_INIT] PLL >>>>>>>>
677 10:01:26.964728 [ANA_INIT] PLL <<<<<<<<
678 10:01:26.968166 [ANA_INIT] MIDPI >>>>>>>>
679 10:01:26.971335 [ANA_INIT] MIDPI <<<<<<<<
680 10:01:26.974962 [ANA_INIT] DLL >>>>>>>>
681 10:01:26.975046 [ANA_INIT] flow end
682 10:01:26.978195 ============ LP4 DIFF to SE enter ============
683 10:01:26.984735 ============ LP4 DIFF to SE exit ============
684 10:01:26.984820 [ANA_INIT] <<<<<<<<<<<<<
685 10:01:26.988098 [Flow] Enable top DCM control >>>>>
686 10:01:26.991584 [Flow] Enable top DCM control <<<<<
687 10:01:26.995082 Enable DLL master slave shuffle
688 10:01:27.002207 ==============================================================
689 10:01:27.002295 Gating Mode config
690 10:01:27.009617 ==============================================================
691 10:01:27.009706 Config description:
692 10:01:27.020570 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
693 10:01:27.027657 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
694 10:01:27.031420 SELPH_MODE 0: By rank 1: By Phase
695 10:01:27.035263 ==============================================================
696 10:01:27.038924 GAT_TRACK_EN = 1
697 10:01:27.042993 RX_GATING_MODE = 2
698 10:01:27.046686 RX_GATING_TRACK_MODE = 2
699 10:01:27.050005 SELPH_MODE = 1
700 10:01:27.050090 PICG_EARLY_EN = 1
701 10:01:27.054145 VALID_LAT_VALUE = 1
702 10:01:27.061281 ==============================================================
703 10:01:27.065321 Enter into Gating configuration >>>>
704 10:01:27.065435 Exit from Gating configuration <<<<
705 10:01:27.069081 Enter into DVFS_PRE_config >>>>>
706 10:01:27.080566 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
707 10:01:27.084413 Exit from DVFS_PRE_config <<<<<
708 10:01:27.087872 Enter into PICG configuration >>>>
709 10:01:27.091833 Exit from PICG configuration <<<<
710 10:01:27.091919 [RX_INPUT] configuration >>>>>
711 10:01:27.095647 [RX_INPUT] configuration <<<<<
712 10:01:27.103362 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
713 10:01:27.106883 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
714 10:01:27.114488 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
715 10:01:27.118282 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
716 10:01:27.125053 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
717 10:01:27.132540 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
718 10:01:27.136355 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
719 10:01:27.140210 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
720 10:01:27.143923 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
721 10:01:27.147582 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
722 10:01:27.151278 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
723 10:01:27.154634 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
724 10:01:27.157987 ===================================
725 10:01:27.161924 LPDDR4 DRAM CONFIGURATION
726 10:01:27.165420 ===================================
727 10:01:27.165497 EX_ROW_EN[0] = 0x0
728 10:01:27.169567 EX_ROW_EN[1] = 0x0
729 10:01:27.169648 LP4Y_EN = 0x0
730 10:01:27.173323 WORK_FSP = 0x0
731 10:01:27.173408 WL = 0x2
732 10:01:27.177159 RL = 0x2
733 10:01:27.177244 BL = 0x2
734 10:01:27.180982 RPST = 0x0
735 10:01:27.181067 RD_PRE = 0x0
736 10:01:27.184567 WR_PRE = 0x1
737 10:01:27.184653 WR_PST = 0x0
738 10:01:27.188136 DBI_WR = 0x0
739 10:01:27.188222 DBI_RD = 0x0
740 10:01:27.191167 OTF = 0x1
741 10:01:27.191254 ===================================
742 10:01:27.198687 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
743 10:01:27.202441 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
744 10:01:27.206225 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
745 10:01:27.210209 ===================================
746 10:01:27.210322 LPDDR4 DRAM CONFIGURATION
747 10:01:27.213858 ===================================
748 10:01:27.217429 EX_ROW_EN[0] = 0x10
749 10:01:27.217514 EX_ROW_EN[1] = 0x0
750 10:01:27.221098 LP4Y_EN = 0x0
751 10:01:27.221184 WORK_FSP = 0x0
752 10:01:27.225605 WL = 0x2
753 10:01:27.225691 RL = 0x2
754 10:01:27.228685 BL = 0x2
755 10:01:27.228773 RPST = 0x0
756 10:01:27.232505 RD_PRE = 0x0
757 10:01:27.232590 WR_PRE = 0x1
758 10:01:27.236057 WR_PST = 0x0
759 10:01:27.236144 DBI_WR = 0x0
760 10:01:27.236217 DBI_RD = 0x0
761 10:01:27.239618 OTF = 0x1
762 10:01:27.243597 ===================================
763 10:01:27.246989 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
764 10:01:27.252762 nWR fixed to 40
765 10:01:27.256395 [ModeRegInit_LP4] CH0 RK0
766 10:01:27.256506 [ModeRegInit_LP4] CH0 RK1
767 10:01:27.260534 [ModeRegInit_LP4] CH1 RK0
768 10:01:27.260614 [ModeRegInit_LP4] CH1 RK1
769 10:01:27.264033 match AC timing 13
770 10:01:27.267631 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
771 10:01:27.271252 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
772 10:01:27.275469 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
773 10:01:27.282627 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
774 10:01:27.286510 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
775 10:01:27.286591 [EMI DOE] emi_dcm 0
776 10:01:27.290460 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
777 10:01:27.294335 ==
778 10:01:27.294462 Dram Type= 6, Freq= 0, CH_0, rank 0
779 10:01:27.297798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 10:01:27.301790 ==
781 10:01:27.305353 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 10:01:27.312026 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 10:01:27.320060 [CA 0] Center 38 (7~69) winsize 63
784 10:01:27.323343 [CA 1] Center 38 (7~69) winsize 63
785 10:01:27.326906 [CA 2] Center 35 (5~66) winsize 62
786 10:01:27.330118 [CA 3] Center 35 (5~66) winsize 62
787 10:01:27.333398 [CA 4] Center 34 (4~65) winsize 62
788 10:01:27.336794 [CA 5] Center 33 (3~64) winsize 62
789 10:01:27.336897
790 10:01:27.340025 [CmdBusTrainingLP45] Vref(ca) range 1: 34
791 10:01:27.340122
792 10:01:27.343622 [CATrainingPosCal] consider 1 rank data
793 10:01:27.347109 u2DelayCellTimex100 = 270/100 ps
794 10:01:27.350703 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
795 10:01:27.353480 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
796 10:01:27.357128 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
797 10:01:27.363933 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
798 10:01:27.367168 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
799 10:01:27.370305 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
800 10:01:27.370410
801 10:01:27.373600 CA PerBit enable=1, Macro0, CA PI delay=33
802 10:01:27.373684
803 10:01:27.376903 [CBTSetCACLKResult] CA Dly = 33
804 10:01:27.376989 CS Dly: 5 (0~36)
805 10:01:27.377056 ==
806 10:01:27.380500 Dram Type= 6, Freq= 0, CH_0, rank 1
807 10:01:27.386997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
808 10:01:27.387082 ==
809 10:01:27.390330 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
810 10:01:27.397292 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
811 10:01:27.406758 [CA 0] Center 38 (7~69) winsize 63
812 10:01:27.409641 [CA 1] Center 38 (8~69) winsize 62
813 10:01:27.413282 [CA 2] Center 36 (6~67) winsize 62
814 10:01:27.416665 [CA 3] Center 36 (5~67) winsize 63
815 10:01:27.419594 [CA 4] Center 35 (4~66) winsize 63
816 10:01:27.422927 [CA 5] Center 34 (4~65) winsize 62
817 10:01:27.423001
818 10:01:27.426447 [CmdBusTrainingLP45] Vref(ca) range 1: 32
819 10:01:27.426546
820 10:01:27.429686 [CATrainingPosCal] consider 2 rank data
821 10:01:27.433282 u2DelayCellTimex100 = 270/100 ps
822 10:01:27.436284 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
823 10:01:27.443392 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
824 10:01:27.446262 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
825 10:01:27.449657 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
826 10:01:27.452941 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
827 10:01:27.456084 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
828 10:01:27.456169
829 10:01:27.459565 CA PerBit enable=1, Macro0, CA PI delay=34
830 10:01:27.459652
831 10:01:27.462756 [CBTSetCACLKResult] CA Dly = 34
832 10:01:27.466159 CS Dly: 6 (0~38)
833 10:01:27.466247
834 10:01:27.469517 ----->DramcWriteLeveling(PI) begin...
835 10:01:27.469607 ==
836 10:01:27.472856 Dram Type= 6, Freq= 0, CH_0, rank 0
837 10:01:27.476329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
838 10:01:27.476422 ==
839 10:01:27.479504 Write leveling (Byte 0): 31 => 31
840 10:01:27.483119 Write leveling (Byte 1): 30 => 30
841 10:01:27.486608 DramcWriteLeveling(PI) end<-----
842 10:01:27.486714
843 10:01:27.486799 ==
844 10:01:27.489979 Dram Type= 6, Freq= 0, CH_0, rank 0
845 10:01:27.493172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
846 10:01:27.493301 ==
847 10:01:27.496264 [Gating] SW mode calibration
848 10:01:27.504157 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
849 10:01:27.507544 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
850 10:01:27.511458 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
851 10:01:27.518289 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
852 10:01:27.521570 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 10:01:27.524774 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 10:01:27.528908 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 10:01:27.535607 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 10:01:27.539279 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 10:01:27.542195 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 10:01:27.549601 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 10:01:27.552339 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 10:01:27.555673 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 10:01:27.562326 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 10:01:27.565799 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 10:01:27.569271 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 10:01:27.572398 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 10:01:27.579140 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 10:01:27.582315 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
867 10:01:27.585877 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
868 10:01:27.592839 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
869 10:01:27.595638 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 10:01:27.599631 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 10:01:27.605702 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 10:01:27.609029 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 10:01:27.612533 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 10:01:27.619314 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 10:01:27.622507 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
876 10:01:27.625627 0 9 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
877 10:01:27.632316 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
878 10:01:27.635809 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 10:01:27.639265 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 10:01:27.645905 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 10:01:27.648890 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 10:01:27.652619 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
883 10:01:27.655544 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 0) (0 0)
884 10:01:27.662498 0 10 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
885 10:01:27.665742 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
886 10:01:27.668960 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 10:01:27.675673 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 10:01:27.679133 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 10:01:27.682717 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 10:01:27.689310 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 10:01:27.692612 0 11 4 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
892 10:01:27.695868 0 11 8 | B1->B0 | 2828 4646 | 1 0 | (0 0) (0 0)
893 10:01:27.703027 0 11 12 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
894 10:01:27.706260 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 10:01:27.709471 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 10:01:27.715853 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 10:01:27.719743 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 10:01:27.722689 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
899 10:01:27.729235 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
900 10:01:27.732556 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
901 10:01:27.735881 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 10:01:27.739335 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 10:01:27.746065 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 10:01:27.749364 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 10:01:27.752777 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 10:01:27.759348 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 10:01:27.762551 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 10:01:27.765747 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 10:01:27.772525 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 10:01:27.776024 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 10:01:27.779495 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 10:01:27.786418 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 10:01:27.789833 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 10:01:27.792961 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
915 10:01:27.799491 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
916 10:01:27.803159 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
917 10:01:27.806500 Total UI for P1: 0, mck2ui 16
918 10:01:27.809468 best dqsien dly found for B0: ( 0, 14, 2)
919 10:01:27.813154 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
920 10:01:27.816326 Total UI for P1: 0, mck2ui 16
921 10:01:27.820088 best dqsien dly found for B1: ( 0, 14, 8)
922 10:01:27.823331 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
923 10:01:27.826278 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
924 10:01:27.826365
925 10:01:27.829685 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
926 10:01:27.832935 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
927 10:01:27.836206 [Gating] SW calibration Done
928 10:01:27.836293 ==
929 10:01:27.839640 Dram Type= 6, Freq= 0, CH_0, rank 0
930 10:01:27.842805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 10:01:27.846588 ==
932 10:01:27.846689 RX Vref Scan: 0
933 10:01:27.846774
934 10:01:27.849638 RX Vref 0 -> 0, step: 1
935 10:01:27.849738
936 10:01:27.852799 RX Delay -130 -> 252, step: 16
937 10:01:27.856326 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
938 10:01:27.860000 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
939 10:01:27.862928 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
940 10:01:27.866194 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
941 10:01:27.873390 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
942 10:01:27.876178 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
943 10:01:27.879440 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
944 10:01:27.882928 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
945 10:01:27.886206 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
946 10:01:27.892980 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
947 10:01:27.896207 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
948 10:01:27.899931 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
949 10:01:27.903203 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
950 10:01:27.906432 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
951 10:01:27.913372 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
952 10:01:27.916180 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
953 10:01:27.916268 ==
954 10:01:27.919526 Dram Type= 6, Freq= 0, CH_0, rank 0
955 10:01:27.923044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
956 10:01:27.923132 ==
957 10:01:27.926787 DQS Delay:
958 10:01:27.926875 DQS0 = 0, DQS1 = 0
959 10:01:27.926945 DQM Delay:
960 10:01:27.929604 DQM0 = 93, DQM1 = 82
961 10:01:27.929690 DQ Delay:
962 10:01:27.933440 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
963 10:01:27.936370 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
964 10:01:27.940050 DQ8 =77, DQ9 =61, DQ10 =85, DQ11 =77
965 10:01:27.943224 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
966 10:01:27.943311
967 10:01:27.943380
968 10:01:27.943444 ==
969 10:01:27.946509 Dram Type= 6, Freq= 0, CH_0, rank 0
970 10:01:27.953013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 10:01:27.953100 ==
972 10:01:27.953170
973 10:01:27.953235
974 10:01:27.953298 TX Vref Scan disable
975 10:01:27.956406 == TX Byte 0 ==
976 10:01:27.959910 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
977 10:01:27.963123 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
978 10:01:27.966643 == TX Byte 1 ==
979 10:01:27.969862 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
980 10:01:27.973267 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
981 10:01:27.976704 ==
982 10:01:27.976791 Dram Type= 6, Freq= 0, CH_0, rank 0
983 10:01:27.983027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
984 10:01:27.983114 ==
985 10:01:27.995735 TX Vref=22, minBit 6, minWin=27, winSum=440
986 10:01:27.999087 TX Vref=24, minBit 11, minWin=26, winSum=441
987 10:01:28.002679 TX Vref=26, minBit 6, minWin=27, winSum=446
988 10:01:28.005406 TX Vref=28, minBit 8, minWin=27, winSum=450
989 10:01:28.008890 TX Vref=30, minBit 10, minWin=27, winSum=456
990 10:01:28.015485 TX Vref=32, minBit 4, minWin=28, winSum=454
991 10:01:28.019331 [TxChooseVref] Worse bit 4, Min win 28, Win sum 454, Final Vref 32
992 10:01:28.019420
993 10:01:28.022331 Final TX Range 1 Vref 32
994 10:01:28.022425
995 10:01:28.022495 ==
996 10:01:28.025764 Dram Type= 6, Freq= 0, CH_0, rank 0
997 10:01:28.028895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
998 10:01:28.028983 ==
999 10:01:28.029052
1000 10:01:28.031995
1001 10:01:28.032081 TX Vref Scan disable
1002 10:01:28.035531 == TX Byte 0 ==
1003 10:01:28.038831 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1004 10:01:28.042163 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1005 10:01:28.045858 == TX Byte 1 ==
1006 10:01:28.049053 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1007 10:01:28.055978 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1008 10:01:28.056066
1009 10:01:28.056135 [DATLAT]
1010 10:01:28.056200 Freq=800, CH0 RK0
1011 10:01:28.056263
1012 10:01:28.058878 DATLAT Default: 0xa
1013 10:01:28.058965 0, 0xFFFF, sum = 0
1014 10:01:28.062164 1, 0xFFFF, sum = 0
1015 10:01:28.062253 2, 0xFFFF, sum = 0
1016 10:01:28.065667 3, 0xFFFF, sum = 0
1017 10:01:28.065770 4, 0xFFFF, sum = 0
1018 10:01:28.069041 5, 0xFFFF, sum = 0
1019 10:01:28.069130 6, 0xFFFF, sum = 0
1020 10:01:28.072457 7, 0xFFFF, sum = 0
1021 10:01:28.075620 8, 0xFFFF, sum = 0
1022 10:01:28.075707 9, 0x0, sum = 1
1023 10:01:28.075781 10, 0x0, sum = 2
1024 10:01:28.078872 11, 0x0, sum = 3
1025 10:01:28.078962 12, 0x0, sum = 4
1026 10:01:28.082610 best_step = 10
1027 10:01:28.082694
1028 10:01:28.082762 ==
1029 10:01:28.085666 Dram Type= 6, Freq= 0, CH_0, rank 0
1030 10:01:28.088995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1031 10:01:28.089080 ==
1032 10:01:28.092448 RX Vref Scan: 1
1033 10:01:28.092532
1034 10:01:28.092599 Set Vref Range= 32 -> 127
1035 10:01:28.092662
1036 10:01:28.095657 RX Vref 32 -> 127, step: 1
1037 10:01:28.095741
1038 10:01:28.098886 RX Delay -95 -> 252, step: 8
1039 10:01:28.098970
1040 10:01:28.102262 Set Vref, RX VrefLevel [Byte0]: 32
1041 10:01:28.105515 [Byte1]: 32
1042 10:01:28.105598
1043 10:01:28.109134 Set Vref, RX VrefLevel [Byte0]: 33
1044 10:01:28.112050 [Byte1]: 33
1045 10:01:28.115951
1046 10:01:28.116035 Set Vref, RX VrefLevel [Byte0]: 34
1047 10:01:28.119391 [Byte1]: 34
1048 10:01:28.123459
1049 10:01:28.123555 Set Vref, RX VrefLevel [Byte0]: 35
1050 10:01:28.126764 [Byte1]: 35
1051 10:01:28.131422
1052 10:01:28.131506 Set Vref, RX VrefLevel [Byte0]: 36
1053 10:01:28.134241 [Byte1]: 36
1054 10:01:28.138785
1055 10:01:28.138869 Set Vref, RX VrefLevel [Byte0]: 37
1056 10:01:28.141952 [Byte1]: 37
1057 10:01:28.146900
1058 10:01:28.146984 Set Vref, RX VrefLevel [Byte0]: 38
1059 10:01:28.150580 [Byte1]: 38
1060 10:01:28.153740
1061 10:01:28.153838 Set Vref, RX VrefLevel [Byte0]: 39
1062 10:01:28.157605 [Byte1]: 39
1063 10:01:28.162058
1064 10:01:28.162151 Set Vref, RX VrefLevel [Byte0]: 40
1065 10:01:28.165197 [Byte1]: 40
1066 10:01:28.169762
1067 10:01:28.169883 Set Vref, RX VrefLevel [Byte0]: 41
1068 10:01:28.173281 [Byte1]: 41
1069 10:01:28.176619
1070 10:01:28.176704 Set Vref, RX VrefLevel [Byte0]: 42
1071 10:01:28.180017 [Byte1]: 42
1072 10:01:28.184677
1073 10:01:28.184763 Set Vref, RX VrefLevel [Byte0]: 43
1074 10:01:28.188433 [Byte1]: 43
1075 10:01:28.192234
1076 10:01:28.192318 Set Vref, RX VrefLevel [Byte0]: 44
1077 10:01:28.195280 [Byte1]: 44
1078 10:01:28.199761
1079 10:01:28.199846 Set Vref, RX VrefLevel [Byte0]: 45
1080 10:01:28.202879 [Byte1]: 45
1081 10:01:28.206845
1082 10:01:28.206928 Set Vref, RX VrefLevel [Byte0]: 46
1083 10:01:28.210572 [Byte1]: 46
1084 10:01:28.214574
1085 10:01:28.214658 Set Vref, RX VrefLevel [Byte0]: 47
1086 10:01:28.218318 [Byte1]: 47
1087 10:01:28.222279
1088 10:01:28.222363 Set Vref, RX VrefLevel [Byte0]: 48
1089 10:01:28.225502 [Byte1]: 48
1090 10:01:28.229661
1091 10:01:28.229759 Set Vref, RX VrefLevel [Byte0]: 49
1092 10:01:28.233603 [Byte1]: 49
1093 10:01:28.237558
1094 10:01:28.237642 Set Vref, RX VrefLevel [Byte0]: 50
1095 10:01:28.241166 [Byte1]: 50
1096 10:01:28.245085
1097 10:01:28.245169 Set Vref, RX VrefLevel [Byte0]: 51
1098 10:01:28.248397 [Byte1]: 51
1099 10:01:28.252594
1100 10:01:28.252678 Set Vref, RX VrefLevel [Byte0]: 52
1101 10:01:28.256125 [Byte1]: 52
1102 10:01:28.260445
1103 10:01:28.260529 Set Vref, RX VrefLevel [Byte0]: 53
1104 10:01:28.263717 [Byte1]: 53
1105 10:01:28.267882
1106 10:01:28.267966 Set Vref, RX VrefLevel [Byte0]: 54
1107 10:01:28.271316 [Byte1]: 54
1108 10:01:28.275398
1109 10:01:28.275482 Set Vref, RX VrefLevel [Byte0]: 55
1110 10:01:28.278873 [Byte1]: 55
1111 10:01:28.282925
1112 10:01:28.283008 Set Vref, RX VrefLevel [Byte0]: 56
1113 10:01:28.286219 [Byte1]: 56
1114 10:01:28.290358
1115 10:01:28.290483 Set Vref, RX VrefLevel [Byte0]: 57
1116 10:01:28.293872 [Byte1]: 57
1117 10:01:28.298176
1118 10:01:28.298261 Set Vref, RX VrefLevel [Byte0]: 58
1119 10:01:28.301490 [Byte1]: 58
1120 10:01:28.305852
1121 10:01:28.305936 Set Vref, RX VrefLevel [Byte0]: 59
1122 10:01:28.309097 [Byte1]: 59
1123 10:01:28.313300
1124 10:01:28.313398 Set Vref, RX VrefLevel [Byte0]: 60
1125 10:01:28.316629 [Byte1]: 60
1126 10:01:28.321077
1127 10:01:28.321174 Set Vref, RX VrefLevel [Byte0]: 61
1128 10:01:28.324493 [Byte1]: 61
1129 10:01:28.328622
1130 10:01:28.328704 Set Vref, RX VrefLevel [Byte0]: 62
1131 10:01:28.331811 [Byte1]: 62
1132 10:01:28.336114
1133 10:01:28.336188 Set Vref, RX VrefLevel [Byte0]: 63
1134 10:01:28.339673 [Byte1]: 63
1135 10:01:28.343764
1136 10:01:28.343845 Set Vref, RX VrefLevel [Byte0]: 64
1137 10:01:28.347262 [Byte1]: 64
1138 10:01:28.351490
1139 10:01:28.351589 Set Vref, RX VrefLevel [Byte0]: 65
1140 10:01:28.354543 [Byte1]: 65
1141 10:01:28.359362
1142 10:01:28.359476 Set Vref, RX VrefLevel [Byte0]: 66
1143 10:01:28.362302 [Byte1]: 66
1144 10:01:28.366580
1145 10:01:28.366653 Set Vref, RX VrefLevel [Byte0]: 67
1146 10:01:28.370334 [Byte1]: 67
1147 10:01:28.374301
1148 10:01:28.374406 Set Vref, RX VrefLevel [Byte0]: 68
1149 10:01:28.377396 [Byte1]: 68
1150 10:01:28.381746
1151 10:01:28.381850 Set Vref, RX VrefLevel [Byte0]: 69
1152 10:01:28.385043 [Byte1]: 69
1153 10:01:28.389509
1154 10:01:28.389595 Set Vref, RX VrefLevel [Byte0]: 70
1155 10:01:28.392787 [Byte1]: 70
1156 10:01:28.396988
1157 10:01:28.397087 Set Vref, RX VrefLevel [Byte0]: 71
1158 10:01:28.400749 [Byte1]: 71
1159 10:01:28.404955
1160 10:01:28.405028 Set Vref, RX VrefLevel [Byte0]: 72
1161 10:01:28.408099 [Byte1]: 72
1162 10:01:28.412098
1163 10:01:28.412201 Set Vref, RX VrefLevel [Byte0]: 73
1164 10:01:28.415480 [Byte1]: 73
1165 10:01:28.419735
1166 10:01:28.419823 Set Vref, RX VrefLevel [Byte0]: 74
1167 10:01:28.423203 [Byte1]: 74
1168 10:01:28.427430
1169 10:01:28.427507 Set Vref, RX VrefLevel [Byte0]: 75
1170 10:01:28.430746 [Byte1]: 75
1171 10:01:28.435355
1172 10:01:28.435459 Set Vref, RX VrefLevel [Byte0]: 76
1173 10:01:28.438194 [Byte1]: 76
1174 10:01:28.442534
1175 10:01:28.442607 Final RX Vref Byte 0 = 60 to rank0
1176 10:01:28.445983 Final RX Vref Byte 1 = 58 to rank0
1177 10:01:28.449311 Final RX Vref Byte 0 = 60 to rank1
1178 10:01:28.452354 Final RX Vref Byte 1 = 58 to rank1==
1179 10:01:28.455714 Dram Type= 6, Freq= 0, CH_0, rank 0
1180 10:01:28.462478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1181 10:01:28.462567 ==
1182 10:01:28.462633 DQS Delay:
1183 10:01:28.462694 DQS0 = 0, DQS1 = 0
1184 10:01:28.466050 DQM Delay:
1185 10:01:28.466154 DQM0 = 93, DQM1 = 83
1186 10:01:28.469321 DQ Delay:
1187 10:01:28.472876 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1188 10:01:28.472977 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1189 10:01:28.476289 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =80
1190 10:01:28.479514 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =92
1191 10:01:28.483377
1192 10:01:28.483458
1193 10:01:28.489366 [DQSOSCAuto] RK0, (LSB)MR18= 0x3732, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
1194 10:01:28.493181 CH0 RK0: MR19=606, MR18=3732
1195 10:01:28.500011 CH0_RK0: MR19=0x606, MR18=0x3732, DQSOSC=395, MR23=63, INC=94, DEC=63
1196 10:01:28.500107
1197 10:01:28.503332 ----->DramcWriteLeveling(PI) begin...
1198 10:01:28.503444 ==
1199 10:01:28.506195 Dram Type= 6, Freq= 0, CH_0, rank 1
1200 10:01:28.509493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1201 10:01:28.509602 ==
1202 10:01:28.513112 Write leveling (Byte 0): 31 => 31
1203 10:01:28.516365 Write leveling (Byte 1): 27 => 27
1204 10:01:28.520211 DramcWriteLeveling(PI) end<-----
1205 10:01:28.520313
1206 10:01:28.520408 ==
1207 10:01:28.523222 Dram Type= 6, Freq= 0, CH_0, rank 1
1208 10:01:28.526759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1209 10:01:28.526834 ==
1210 10:01:28.530079 [Gating] SW mode calibration
1211 10:01:28.536705 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1212 10:01:28.543338 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1213 10:01:28.546579 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1214 10:01:28.550127 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1215 10:01:28.553475 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 10:01:28.559921 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 10:01:28.563145 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 10:01:28.566813 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 10:01:28.610635 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 10:01:28.610937 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 10:01:28.611368 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 10:01:28.611659 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 10:01:28.611763 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 10:01:28.612043 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 10:01:28.612590 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 10:01:28.612878 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 10:01:28.613004 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 10:01:28.613101 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 10:01:28.642063 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 10:01:28.642340 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1231 10:01:28.642773 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1232 10:01:28.643067 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 10:01:28.643143 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 10:01:28.643459 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 10:01:28.646720 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 10:01:28.649632 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 10:01:28.653203 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 10:01:28.656456 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 10:01:28.659592 0 9 8 | B1->B0 | 2a2a 3332 | 1 1 | (1 1) (1 1)
1240 10:01:28.663134 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 10:01:28.669851 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 10:01:28.672987 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 10:01:28.676658 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 10:01:28.682984 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 10:01:28.686312 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 10:01:28.690260 0 10 4 | B1->B0 | 3333 2f2f | 1 0 | (1 1) (0 0)
1247 10:01:28.696689 0 10 8 | B1->B0 | 2b2b 2323 | 0 0 | (1 1) (1 0)
1248 10:01:28.700172 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 10:01:28.703070 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 10:01:28.709776 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 10:01:28.713095 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 10:01:28.716706 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 10:01:28.723343 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 10:01:28.726526 0 11 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1255 10:01:28.729908 0 11 8 | B1->B0 | 3535 4242 | 0 0 | (1 1) (0 0)
1256 10:01:28.736875 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 10:01:28.740096 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 10:01:28.743599 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 10:01:28.747143 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 10:01:28.750755 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 10:01:28.758537 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 10:01:28.762017 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1263 10:01:28.765642 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1264 10:01:28.768970 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 10:01:28.775864 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 10:01:28.779577 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 10:01:28.783083 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 10:01:28.786177 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 10:01:28.792732 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 10:01:28.796413 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 10:01:28.799605 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 10:01:28.806174 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 10:01:28.809497 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 10:01:28.813438 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 10:01:28.819426 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 10:01:28.822989 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 10:01:28.826299 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 10:01:28.832796 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1279 10:01:28.836593 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1280 10:01:28.839612 Total UI for P1: 0, mck2ui 16
1281 10:01:28.842925 best dqsien dly found for B0: ( 0, 14, 4)
1282 10:01:28.846198 Total UI for P1: 0, mck2ui 16
1283 10:01:28.850241 best dqsien dly found for B1: ( 0, 14, 4)
1284 10:01:28.852781 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1285 10:01:28.856265 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1286 10:01:28.856350
1287 10:01:28.859950 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1288 10:01:28.862905 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1289 10:01:28.866315 [Gating] SW calibration Done
1290 10:01:28.866456 ==
1291 10:01:28.869780 Dram Type= 6, Freq= 0, CH_0, rank 1
1292 10:01:28.873304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1293 10:01:28.873395 ==
1294 10:01:28.876709 RX Vref Scan: 0
1295 10:01:28.876789
1296 10:01:28.876882 RX Vref 0 -> 0, step: 1
1297 10:01:28.879517
1298 10:01:28.879593 RX Delay -130 -> 252, step: 16
1299 10:01:28.886325 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1300 10:01:28.889910 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1301 10:01:28.892930 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1302 10:01:28.896433 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1303 10:01:28.899758 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1304 10:01:28.906705 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1305 10:01:28.909797 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1306 10:01:28.913564 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1307 10:01:28.916360 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1308 10:01:28.920210 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1309 10:01:28.926527 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1310 10:01:28.930158 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1311 10:01:28.933046 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1312 10:01:28.936612 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
1313 10:01:28.939937 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1314 10:01:28.946201 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1315 10:01:28.946319 ==
1316 10:01:28.950294 Dram Type= 6, Freq= 0, CH_0, rank 1
1317 10:01:28.952981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1318 10:01:28.953061 ==
1319 10:01:28.953145 DQS Delay:
1320 10:01:28.956900 DQS0 = 0, DQS1 = 0
1321 10:01:28.956978 DQM Delay:
1322 10:01:28.959728 DQM0 = 89, DQM1 = 80
1323 10:01:28.959813 DQ Delay:
1324 10:01:28.963136 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1325 10:01:28.966809 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1326 10:01:28.969991 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
1327 10:01:28.973346 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =93
1328 10:01:28.973463
1329 10:01:28.973545
1330 10:01:28.973651 ==
1331 10:01:28.976486 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 10:01:28.980061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 10:01:28.980143 ==
1334 10:01:28.980223
1335 10:01:28.980307
1336 10:01:28.983203 TX Vref Scan disable
1337 10:01:28.986583 == TX Byte 0 ==
1338 10:01:28.989974 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1339 10:01:28.993640 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1340 10:01:28.996995 == TX Byte 1 ==
1341 10:01:29.000098 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1342 10:01:29.003386 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1343 10:01:29.003468 ==
1344 10:01:29.006721 Dram Type= 6, Freq= 0, CH_0, rank 1
1345 10:01:29.013358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1346 10:01:29.013445 ==
1347 10:01:29.025209 TX Vref=22, minBit 3, minWin=27, winSum=445
1348 10:01:29.028504 TX Vref=24, minBit 10, minWin=27, winSum=449
1349 10:01:29.031913 TX Vref=26, minBit 8, minWin=27, winSum=451
1350 10:01:29.035396 TX Vref=28, minBit 8, minWin=28, winSum=457
1351 10:01:29.038681 TX Vref=30, minBit 6, minWin=28, winSum=457
1352 10:01:29.045100 TX Vref=32, minBit 6, minWin=28, winSum=458
1353 10:01:29.048443 [TxChooseVref] Worse bit 6, Min win 28, Win sum 458, Final Vref 32
1354 10:01:29.048519
1355 10:01:29.052118 Final TX Range 1 Vref 32
1356 10:01:29.052190
1357 10:01:29.052252 ==
1358 10:01:29.055251 Dram Type= 6, Freq= 0, CH_0, rank 1
1359 10:01:29.058584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1360 10:01:29.058659 ==
1361 10:01:29.058724
1362 10:01:29.061838
1363 10:01:29.061907 TX Vref Scan disable
1364 10:01:29.065689 == TX Byte 0 ==
1365 10:01:29.069003 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1366 10:01:29.072094 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1367 10:01:29.075266 == TX Byte 1 ==
1368 10:01:29.079268 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1369 10:01:29.082142 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1370 10:01:29.085635
1371 10:01:29.085712 [DATLAT]
1372 10:01:29.085775 Freq=800, CH0 RK1
1373 10:01:29.085839
1374 10:01:29.088778 DATLAT Default: 0xa
1375 10:01:29.088856 0, 0xFFFF, sum = 0
1376 10:01:29.092252 1, 0xFFFF, sum = 0
1377 10:01:29.092326 2, 0xFFFF, sum = 0
1378 10:01:29.095292 3, 0xFFFF, sum = 0
1379 10:01:29.095365 4, 0xFFFF, sum = 0
1380 10:01:29.098743 5, 0xFFFF, sum = 0
1381 10:01:29.098815 6, 0xFFFF, sum = 0
1382 10:01:29.102296 7, 0xFFFF, sum = 0
1383 10:01:29.105407 8, 0xFFFF, sum = 0
1384 10:01:29.105482 9, 0x0, sum = 1
1385 10:01:29.105543 10, 0x0, sum = 2
1386 10:01:29.109248 11, 0x0, sum = 3
1387 10:01:29.109333 12, 0x0, sum = 4
1388 10:01:29.111957 best_step = 10
1389 10:01:29.112028
1390 10:01:29.112088 ==
1391 10:01:29.115686 Dram Type= 6, Freq= 0, CH_0, rank 1
1392 10:01:29.118702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1393 10:01:29.118771 ==
1394 10:01:29.121924 RX Vref Scan: 0
1395 10:01:29.121989
1396 10:01:29.122046 RX Vref 0 -> 0, step: 1
1397 10:01:29.122101
1398 10:01:29.125403 RX Delay -95 -> 252, step: 8
1399 10:01:29.132023 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1400 10:01:29.135654 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1401 10:01:29.138646 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1402 10:01:29.142233 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1403 10:01:29.145353 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1404 10:01:29.152017 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1405 10:01:29.155371 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1406 10:01:29.158812 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1407 10:01:29.162003 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1408 10:01:29.165388 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1409 10:01:29.172163 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1410 10:01:29.175202 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1411 10:01:29.178691 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1412 10:01:29.181923 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1413 10:01:29.185278 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1414 10:01:29.191764 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1415 10:01:29.191839 ==
1416 10:01:29.195242 Dram Type= 6, Freq= 0, CH_0, rank 1
1417 10:01:29.198706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1418 10:01:29.198784 ==
1419 10:01:29.198850 DQS Delay:
1420 10:01:29.202049 DQS0 = 0, DQS1 = 0
1421 10:01:29.202122 DQM Delay:
1422 10:01:29.205679 DQM0 = 91, DQM1 = 82
1423 10:01:29.205749 DQ Delay:
1424 10:01:29.208743 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1425 10:01:29.211961 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1426 10:01:29.215354 DQ8 =76, DQ9 =68, DQ10 =80, DQ11 =80
1427 10:01:29.218958 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =92
1428 10:01:29.219030
1429 10:01:29.219091
1430 10:01:29.226083 [DQSOSCAuto] RK1, (LSB)MR18= 0x4620, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
1431 10:01:29.228689 CH0 RK1: MR19=606, MR18=4620
1432 10:01:29.235637 CH0_RK1: MR19=0x606, MR18=0x4620, DQSOSC=392, MR23=63, INC=96, DEC=64
1433 10:01:29.238954 [RxdqsGatingPostProcess] freq 800
1434 10:01:29.245733 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1435 10:01:29.249074 Pre-setting of DQS Precalculation
1436 10:01:29.252297 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1437 10:01:29.252371 ==
1438 10:01:29.255915 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 10:01:29.258991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 10:01:29.259067 ==
1441 10:01:29.265535 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1442 10:01:29.272184 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1443 10:01:29.280943 [CA 0] Center 36 (6~67) winsize 62
1444 10:01:29.283941 [CA 1] Center 36 (6~67) winsize 62
1445 10:01:29.287306 [CA 2] Center 34 (4~65) winsize 62
1446 10:01:29.290599 [CA 3] Center 34 (4~65) winsize 62
1447 10:01:29.293997 [CA 4] Center 34 (4~65) winsize 62
1448 10:01:29.297327 [CA 5] Center 33 (3~64) winsize 62
1449 10:01:29.297411
1450 10:01:29.300435 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1451 10:01:29.300518
1452 10:01:29.304076 [CATrainingPosCal] consider 1 rank data
1453 10:01:29.307233 u2DelayCellTimex100 = 270/100 ps
1454 10:01:29.310978 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1455 10:01:29.314178 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1456 10:01:29.320800 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1457 10:01:29.324441 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1458 10:01:29.327311 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1459 10:01:29.330740 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1460 10:01:29.330823
1461 10:01:29.334239 CA PerBit enable=1, Macro0, CA PI delay=33
1462 10:01:29.334338
1463 10:01:29.337337 [CBTSetCACLKResult] CA Dly = 33
1464 10:01:29.337421 CS Dly: 5 (0~36)
1465 10:01:29.337487 ==
1466 10:01:29.341033 Dram Type= 6, Freq= 0, CH_1, rank 1
1467 10:01:29.347246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1468 10:01:29.347330 ==
1469 10:01:29.350948 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1470 10:01:29.357479 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1471 10:01:29.366787 [CA 0] Center 37 (7~67) winsize 61
1472 10:01:29.370001 [CA 1] Center 37 (6~68) winsize 63
1473 10:01:29.373274 [CA 2] Center 35 (5~66) winsize 62
1474 10:01:29.376803 [CA 3] Center 34 (4~65) winsize 62
1475 10:01:29.380231 [CA 4] Center 34 (4~65) winsize 62
1476 10:01:29.383504 [CA 5] Center 34 (4~65) winsize 62
1477 10:01:29.383587
1478 10:01:29.386836 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1479 10:01:29.386933
1480 10:01:29.390250 [CATrainingPosCal] consider 2 rank data
1481 10:01:29.393840 u2DelayCellTimex100 = 270/100 ps
1482 10:01:29.397038 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1483 10:01:29.400169 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1484 10:01:29.406395 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1485 10:01:29.410104 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1486 10:01:29.413815 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1487 10:01:29.417233 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1488 10:01:29.417316
1489 10:01:29.420878 CA PerBit enable=1, Macro0, CA PI delay=34
1490 10:01:29.420961
1491 10:01:29.425136 [CBTSetCACLKResult] CA Dly = 34
1492 10:01:29.425220 CS Dly: 6 (0~38)
1493 10:01:29.425286
1494 10:01:29.428267 ----->DramcWriteLeveling(PI) begin...
1495 10:01:29.428351 ==
1496 10:01:29.432398 Dram Type= 6, Freq= 0, CH_1, rank 0
1497 10:01:29.436353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1498 10:01:29.436437 ==
1499 10:01:29.439819 Write leveling (Byte 0): 25 => 25
1500 10:01:29.443418 Write leveling (Byte 1): 29 => 29
1501 10:01:29.443501 DramcWriteLeveling(PI) end<-----
1502 10:01:29.443568
1503 10:01:29.447345 ==
1504 10:01:29.447427 Dram Type= 6, Freq= 0, CH_1, rank 0
1505 10:01:29.454408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1506 10:01:29.454509 ==
1507 10:01:29.454576 [Gating] SW mode calibration
1508 10:01:29.464538 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1509 10:01:29.467882 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1510 10:01:29.471014 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1511 10:01:29.477575 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 10:01:29.481234 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 10:01:29.484459 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 10:01:29.490954 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 10:01:29.494572 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 10:01:29.497670 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 10:01:29.504389 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 10:01:29.507921 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 10:01:29.511093 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 10:01:29.517661 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 10:01:29.521023 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 10:01:29.524651 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 10:01:29.531448 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 10:01:29.534928 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 10:01:29.537933 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 10:01:29.541545 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1527 10:01:29.547910 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1528 10:01:29.551497 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1529 10:01:29.554940 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 10:01:29.561289 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 10:01:29.564834 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 10:01:29.568081 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 10:01:29.574841 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 10:01:29.578050 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 10:01:29.581393 0 9 4 | B1->B0 | 2323 2929 | 0 1 | (0 0) (1 1)
1536 10:01:29.588120 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1537 10:01:29.591331 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 10:01:29.594837 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 10:01:29.601514 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 10:01:29.604737 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 10:01:29.607972 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 10:01:29.611461 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 10:01:29.618119 0 10 4 | B1->B0 | 2d2d 2b2b | 0 0 | (1 0) (1 0)
1544 10:01:29.621716 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 10:01:29.625128 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 10:01:29.631852 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 10:01:29.635140 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 10:01:29.638344 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 10:01:29.644990 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 10:01:29.648429 0 11 0 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
1551 10:01:29.651649 0 11 4 | B1->B0 | 2d2d 3333 | 0 0 | (0 0) (0 0)
1552 10:01:29.658390 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 10:01:29.661807 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 10:01:29.664996 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 10:01:29.671594 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 10:01:29.675162 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 10:01:29.678653 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 10:01:29.681913 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1559 10:01:29.688444 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 10:01:29.691823 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 10:01:29.695274 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 10:01:29.701716 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 10:01:29.705186 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 10:01:29.708486 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 10:01:29.715436 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 10:01:29.718368 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 10:01:29.721827 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 10:01:29.728405 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 10:01:29.731547 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 10:01:29.735103 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 10:01:29.741869 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 10:01:29.744958 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 10:01:29.748417 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 10:01:29.755268 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1575 10:01:29.758577 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1576 10:01:29.761980 Total UI for P1: 0, mck2ui 16
1577 10:01:29.765338 best dqsien dly found for B0: ( 0, 14, 0)
1578 10:01:29.768325 Total UI for P1: 0, mck2ui 16
1579 10:01:29.771828 best dqsien dly found for B1: ( 0, 14, 2)
1580 10:01:29.774922 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1581 10:01:29.778286 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1582 10:01:29.778377
1583 10:01:29.782184 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1584 10:01:29.785167 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1585 10:01:29.788408 [Gating] SW calibration Done
1586 10:01:29.788488 ==
1587 10:01:29.791561 Dram Type= 6, Freq= 0, CH_1, rank 0
1588 10:01:29.795341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1589 10:01:29.795418 ==
1590 10:01:29.798522 RX Vref Scan: 0
1591 10:01:29.798605
1592 10:01:29.798684 RX Vref 0 -> 0, step: 1
1593 10:01:29.801823
1594 10:01:29.801898 RX Delay -130 -> 252, step: 16
1595 10:01:29.808359 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1596 10:01:29.811913 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1597 10:01:29.815043 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1598 10:01:29.818269 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1599 10:01:29.821723 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1600 10:01:29.828505 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1601 10:01:29.832355 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1602 10:01:29.835319 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1603 10:01:29.838340 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1604 10:01:29.841983 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1605 10:01:29.845476 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1606 10:01:29.851818 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1607 10:01:29.855342 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1608 10:01:29.858566 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1609 10:01:29.861775 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1610 10:01:29.868577 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1611 10:01:29.868671 ==
1612 10:01:29.871779 Dram Type= 6, Freq= 0, CH_1, rank 0
1613 10:01:29.875160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1614 10:01:29.875258 ==
1615 10:01:29.875335 DQS Delay:
1616 10:01:29.878714 DQS0 = 0, DQS1 = 0
1617 10:01:29.878791 DQM Delay:
1618 10:01:29.881604 DQM0 = 87, DQM1 = 80
1619 10:01:29.881680 DQ Delay:
1620 10:01:29.885183 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1621 10:01:29.888478 DQ4 =85, DQ5 =93, DQ6 =101, DQ7 =85
1622 10:01:29.891799 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1623 10:01:29.895055 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1624 10:01:29.895136
1625 10:01:29.895224
1626 10:01:29.895300 ==
1627 10:01:29.898476 Dram Type= 6, Freq= 0, CH_1, rank 0
1628 10:01:29.901758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1629 10:01:29.901833 ==
1630 10:01:29.901911
1631 10:01:29.901993
1632 10:01:29.905488 TX Vref Scan disable
1633 10:01:29.908542 == TX Byte 0 ==
1634 10:01:29.911858 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1635 10:01:29.915555 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1636 10:01:29.918555 == TX Byte 1 ==
1637 10:01:29.922219 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1638 10:01:29.925618 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1639 10:01:29.925698 ==
1640 10:01:29.929163 Dram Type= 6, Freq= 0, CH_1, rank 0
1641 10:01:29.932314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1642 10:01:29.935342 ==
1643 10:01:29.947179 TX Vref=22, minBit 10, minWin=27, winSum=451
1644 10:01:29.950539 TX Vref=24, minBit 15, minWin=27, winSum=455
1645 10:01:29.953977 TX Vref=26, minBit 15, minWin=27, winSum=455
1646 10:01:29.957002 TX Vref=28, minBit 15, minWin=27, winSum=457
1647 10:01:29.960379 TX Vref=30, minBit 15, minWin=27, winSum=459
1648 10:01:29.966777 TX Vref=32, minBit 8, minWin=28, winSum=458
1649 10:01:29.970333 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 32
1650 10:01:29.970435
1651 10:01:29.973837 Final TX Range 1 Vref 32
1652 10:01:29.973918
1653 10:01:29.974010 ==
1654 10:01:29.976904 Dram Type= 6, Freq= 0, CH_1, rank 0
1655 10:01:29.980327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1656 10:01:29.983765 ==
1657 10:01:29.983842
1658 10:01:29.983924
1659 10:01:29.984001 TX Vref Scan disable
1660 10:01:29.987506 == TX Byte 0 ==
1661 10:01:29.990826 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1662 10:01:29.994312 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1663 10:01:29.998118 == TX Byte 1 ==
1664 10:01:30.001472 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1665 10:01:30.004933 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1666 10:01:30.005010
1667 10:01:30.008027 [DATLAT]
1668 10:01:30.008114 Freq=800, CH1 RK0
1669 10:01:30.008200
1670 10:01:30.011678 DATLAT Default: 0xa
1671 10:01:30.011753 0, 0xFFFF, sum = 0
1672 10:01:30.015010 1, 0xFFFF, sum = 0
1673 10:01:30.015104 2, 0xFFFF, sum = 0
1674 10:01:30.018066 3, 0xFFFF, sum = 0
1675 10:01:30.018153 4, 0xFFFF, sum = 0
1676 10:01:30.021427 5, 0xFFFF, sum = 0
1677 10:01:30.021541 6, 0xFFFF, sum = 0
1678 10:01:30.024838 7, 0xFFFF, sum = 0
1679 10:01:30.024923 8, 0xFFFF, sum = 0
1680 10:01:30.028139 9, 0x0, sum = 1
1681 10:01:30.028218 10, 0x0, sum = 2
1682 10:01:30.031285 11, 0x0, sum = 3
1683 10:01:30.031374 12, 0x0, sum = 4
1684 10:01:30.034957 best_step = 10
1685 10:01:30.035032
1686 10:01:30.035116 ==
1687 10:01:30.038189 Dram Type= 6, Freq= 0, CH_1, rank 0
1688 10:01:30.041304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1689 10:01:30.041421 ==
1690 10:01:30.041518 RX Vref Scan: 1
1691 10:01:30.044781
1692 10:01:30.044861 Set Vref Range= 32 -> 127
1693 10:01:30.044941
1694 10:01:30.048071 RX Vref 32 -> 127, step: 1
1695 10:01:30.048153
1696 10:01:30.051642 RX Delay -95 -> 252, step: 8
1697 10:01:30.051718
1698 10:01:30.054945 Set Vref, RX VrefLevel [Byte0]: 32
1699 10:01:30.058237 [Byte1]: 32
1700 10:01:30.058322
1701 10:01:30.061321 Set Vref, RX VrefLevel [Byte0]: 33
1702 10:01:30.064909 [Byte1]: 33
1703 10:01:30.064996
1704 10:01:30.068204 Set Vref, RX VrefLevel [Byte0]: 34
1705 10:01:30.071394 [Byte1]: 34
1706 10:01:30.075405
1707 10:01:30.075485 Set Vref, RX VrefLevel [Byte0]: 35
1708 10:01:30.078580 [Byte1]: 35
1709 10:01:30.083096
1710 10:01:30.083179 Set Vref, RX VrefLevel [Byte0]: 36
1711 10:01:30.086259 [Byte1]: 36
1712 10:01:30.090655
1713 10:01:30.090739 Set Vref, RX VrefLevel [Byte0]: 37
1714 10:01:30.094034 [Byte1]: 37
1715 10:01:30.098039
1716 10:01:30.098114 Set Vref, RX VrefLevel [Byte0]: 38
1717 10:01:30.101463 [Byte1]: 38
1718 10:01:30.105904
1719 10:01:30.105978 Set Vref, RX VrefLevel [Byte0]: 39
1720 10:01:30.108975 [Byte1]: 39
1721 10:01:30.113339
1722 10:01:30.113415 Set Vref, RX VrefLevel [Byte0]: 40
1723 10:01:30.116625 [Byte1]: 40
1724 10:01:30.120822
1725 10:01:30.120895 Set Vref, RX VrefLevel [Byte0]: 41
1726 10:01:30.124816 [Byte1]: 41
1727 10:01:30.128547
1728 10:01:30.128632 Set Vref, RX VrefLevel [Byte0]: 42
1729 10:01:30.131646 [Byte1]: 42
1730 10:01:30.135969
1731 10:01:30.136056 Set Vref, RX VrefLevel [Byte0]: 43
1732 10:01:30.139271 [Byte1]: 43
1733 10:01:30.143888
1734 10:01:30.143965 Set Vref, RX VrefLevel [Byte0]: 44
1735 10:01:30.146833 [Byte1]: 44
1736 10:01:30.151425
1737 10:01:30.151502 Set Vref, RX VrefLevel [Byte0]: 45
1738 10:01:30.154549 [Byte1]: 45
1739 10:01:30.159092
1740 10:01:30.159166 Set Vref, RX VrefLevel [Byte0]: 46
1741 10:01:30.162208 [Byte1]: 46
1742 10:01:30.166312
1743 10:01:30.166416 Set Vref, RX VrefLevel [Byte0]: 47
1744 10:01:30.169731 [Byte1]: 47
1745 10:01:30.173887
1746 10:01:30.173968 Set Vref, RX VrefLevel [Byte0]: 48
1747 10:01:30.177437 [Byte1]: 48
1748 10:01:30.181848
1749 10:01:30.181932 Set Vref, RX VrefLevel [Byte0]: 49
1750 10:01:30.185252 [Byte1]: 49
1751 10:01:30.189409
1752 10:01:30.189485 Set Vref, RX VrefLevel [Byte0]: 50
1753 10:01:30.192642 [Byte1]: 50
1754 10:01:30.196787
1755 10:01:30.196869 Set Vref, RX VrefLevel [Byte0]: 51
1756 10:01:30.200183 [Byte1]: 51
1757 10:01:30.204619
1758 10:01:30.204700 Set Vref, RX VrefLevel [Byte0]: 52
1759 10:01:30.207909 [Byte1]: 52
1760 10:01:30.211936
1761 10:01:30.212010 Set Vref, RX VrefLevel [Byte0]: 53
1762 10:01:30.215501 [Byte1]: 53
1763 10:01:30.219764
1764 10:01:30.219833 Set Vref, RX VrefLevel [Byte0]: 54
1765 10:01:30.222931 [Byte1]: 54
1766 10:01:30.227034
1767 10:01:30.227102 Set Vref, RX VrefLevel [Byte0]: 55
1768 10:01:30.230334 [Byte1]: 55
1769 10:01:30.234988
1770 10:01:30.235057 Set Vref, RX VrefLevel [Byte0]: 56
1771 10:01:30.237944 [Byte1]: 56
1772 10:01:30.242394
1773 10:01:30.242482 Set Vref, RX VrefLevel [Byte0]: 57
1774 10:01:30.245573 [Byte1]: 57
1775 10:01:30.250172
1776 10:01:30.250242 Set Vref, RX VrefLevel [Byte0]: 58
1777 10:01:30.253579 [Byte1]: 58
1778 10:01:30.257578
1779 10:01:30.257643 Set Vref, RX VrefLevel [Byte0]: 59
1780 10:01:30.261218 [Byte1]: 59
1781 10:01:30.265321
1782 10:01:30.265390 Set Vref, RX VrefLevel [Byte0]: 60
1783 10:01:30.268451 [Byte1]: 60
1784 10:01:30.272712
1785 10:01:30.272804 Set Vref, RX VrefLevel [Byte0]: 61
1786 10:01:30.276231 [Byte1]: 61
1787 10:01:30.280498
1788 10:01:30.280602 Set Vref, RX VrefLevel [Byte0]: 62
1789 10:01:30.283811 [Byte1]: 62
1790 10:01:30.288173
1791 10:01:30.288258 Set Vref, RX VrefLevel [Byte0]: 63
1792 10:01:30.291427 [Byte1]: 63
1793 10:01:30.295480
1794 10:01:30.295562 Set Vref, RX VrefLevel [Byte0]: 64
1795 10:01:30.299091 [Byte1]: 64
1796 10:01:30.303414
1797 10:01:30.303486 Set Vref, RX VrefLevel [Byte0]: 65
1798 10:01:30.306416 [Byte1]: 65
1799 10:01:30.310800
1800 10:01:30.310887 Set Vref, RX VrefLevel [Byte0]: 66
1801 10:01:30.314224 [Byte1]: 66
1802 10:01:30.318715
1803 10:01:30.318786 Set Vref, RX VrefLevel [Byte0]: 67
1804 10:01:30.321371 [Byte1]: 67
1805 10:01:30.326116
1806 10:01:30.326189 Set Vref, RX VrefLevel [Byte0]: 68
1807 10:01:30.329221 [Byte1]: 68
1808 10:01:30.333458
1809 10:01:30.333531 Set Vref, RX VrefLevel [Byte0]: 69
1810 10:01:30.336795 [Byte1]: 69
1811 10:01:30.340898
1812 10:01:30.340983 Set Vref, RX VrefLevel [Byte0]: 70
1813 10:01:30.344217 [Byte1]: 70
1814 10:01:30.348889
1815 10:01:30.348973 Set Vref, RX VrefLevel [Byte0]: 71
1816 10:01:30.352416 [Byte1]: 71
1817 10:01:30.356486
1818 10:01:30.356556 Set Vref, RX VrefLevel [Byte0]: 72
1819 10:01:30.359771 [Byte1]: 72
1820 10:01:30.363666
1821 10:01:30.363737 Set Vref, RX VrefLevel [Byte0]: 73
1822 10:01:30.367122 [Byte1]: 73
1823 10:01:30.371730
1824 10:01:30.371818 Set Vref, RX VrefLevel [Byte0]: 74
1825 10:01:30.374650 [Byte1]: 74
1826 10:01:30.379137
1827 10:01:30.379219 Set Vref, RX VrefLevel [Byte0]: 75
1828 10:01:30.382307 [Byte1]: 75
1829 10:01:30.386675
1830 10:01:30.386758 Set Vref, RX VrefLevel [Byte0]: 76
1831 10:01:30.390303 [Byte1]: 76
1832 10:01:30.394262
1833 10:01:30.394373 Set Vref, RX VrefLevel [Byte0]: 77
1834 10:01:30.397458 [Byte1]: 77
1835 10:01:30.401817
1836 10:01:30.401902 Final RX Vref Byte 0 = 52 to rank0
1837 10:01:30.405391 Final RX Vref Byte 1 = 64 to rank0
1838 10:01:30.409080 Final RX Vref Byte 0 = 52 to rank1
1839 10:01:30.411994 Final RX Vref Byte 1 = 64 to rank1==
1840 10:01:30.415436 Dram Type= 6, Freq= 0, CH_1, rank 0
1841 10:01:30.421814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1842 10:01:30.421899 ==
1843 10:01:30.421967 DQS Delay:
1844 10:01:30.422029 DQS0 = 0, DQS1 = 0
1845 10:01:30.425274 DQM Delay:
1846 10:01:30.425357 DQM0 = 92, DQM1 = 81
1847 10:01:30.428793 DQ Delay:
1848 10:01:30.431737 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1849 10:01:30.435042 DQ4 =88, DQ5 =104, DQ6 =100, DQ7 =88
1850 10:01:30.438491 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1851 10:01:30.441883 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =88
1852 10:01:30.441967
1853 10:01:30.442033
1854 10:01:30.448825 [DQSOSCAuto] RK0, (LSB)MR18= 0x324f, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1855 10:01:30.451947 CH1 RK0: MR19=606, MR18=324F
1856 10:01:30.458712 CH1_RK0: MR19=0x606, MR18=0x324F, DQSOSC=390, MR23=63, INC=97, DEC=64
1857 10:01:30.458796
1858 10:01:30.461806 ----->DramcWriteLeveling(PI) begin...
1859 10:01:30.461908 ==
1860 10:01:30.465306 Dram Type= 6, Freq= 0, CH_1, rank 1
1861 10:01:30.468582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1862 10:01:30.468691 ==
1863 10:01:30.471841 Write leveling (Byte 0): 28 => 28
1864 10:01:30.475330 Write leveling (Byte 1): 29 => 29
1865 10:01:30.478467 DramcWriteLeveling(PI) end<-----
1866 10:01:30.478551
1867 10:01:30.478617 ==
1868 10:01:30.482055 Dram Type= 6, Freq= 0, CH_1, rank 1
1869 10:01:30.485291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1870 10:01:30.485375 ==
1871 10:01:30.488824 [Gating] SW mode calibration
1872 10:01:30.495332 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1873 10:01:30.502352 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1874 10:01:30.505662 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1875 10:01:30.508863 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1876 10:01:30.515592 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1877 10:01:30.518837 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 10:01:30.522066 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 10:01:30.529099 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 10:01:30.532304 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 10:01:30.535713 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 10:01:30.541965 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 10:01:30.545708 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 10:01:30.548773 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 10:01:30.552168 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 10:01:30.558726 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 10:01:30.562610 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 10:01:30.565676 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 10:01:30.572166 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 10:01:30.575509 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 10:01:30.579057 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1892 10:01:30.585429 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1893 10:01:30.588986 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 10:01:30.592446 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 10:01:30.599004 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 10:01:30.602001 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 10:01:30.605630 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 10:01:30.612294 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 10:01:30.615547 0 9 4 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
1900 10:01:30.618944 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1901 10:01:30.626147 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 10:01:30.629023 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 10:01:30.632400 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1904 10:01:30.635972 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1905 10:01:30.642566 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1906 10:01:30.645866 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1907 10:01:30.649193 0 10 4 | B1->B0 | 2e2e 3030 | 0 0 | (1 0) (0 1)
1908 10:01:30.655631 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1909 10:01:30.659535 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 10:01:30.662566 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 10:01:30.669687 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 10:01:30.672591 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 10:01:30.676183 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 10:01:30.682589 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 10:01:30.686093 0 11 4 | B1->B0 | 3333 3030 | 0 0 | (0 0) (0 0)
1916 10:01:30.689821 0 11 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1917 10:01:30.696514 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 10:01:30.699455 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 10:01:30.703112 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 10:01:30.706232 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1921 10:01:30.712543 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1922 10:01:30.716213 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1923 10:01:30.719557 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1924 10:01:30.726016 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1925 10:01:30.729147 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 10:01:30.732698 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 10:01:30.739306 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 10:01:30.742775 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 10:01:30.745963 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 10:01:30.752582 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 10:01:30.755984 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 10:01:30.759270 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 10:01:30.766086 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 10:01:30.769096 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 10:01:30.772829 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 10:01:30.779400 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 10:01:30.782686 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 10:01:30.786081 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 10:01:30.792419 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 10:01:30.795857 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1941 10:01:30.799581 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1942 10:01:30.802859 Total UI for P1: 0, mck2ui 16
1943 10:01:30.805874 best dqsien dly found for B0: ( 0, 14, 8)
1944 10:01:30.809260 Total UI for P1: 0, mck2ui 16
1945 10:01:30.812745 best dqsien dly found for B1: ( 0, 14, 8)
1946 10:01:30.816211 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1947 10:01:30.819556 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1948 10:01:30.819639
1949 10:01:30.822451 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1950 10:01:30.826106 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1951 10:01:30.829422 [Gating] SW calibration Done
1952 10:01:30.829520 ==
1953 10:01:30.832502 Dram Type= 6, Freq= 0, CH_1, rank 1
1954 10:01:30.839197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1955 10:01:30.839274 ==
1956 10:01:30.839339 RX Vref Scan: 0
1957 10:01:30.839404
1958 10:01:30.842761 RX Vref 0 -> 0, step: 1
1959 10:01:30.842860
1960 10:01:30.845909 RX Delay -130 -> 252, step: 16
1961 10:01:30.849254 iDelay=206, Bit 0, Center 101 (-2 ~ 205) 208
1962 10:01:30.852974 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1963 10:01:30.855972 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1964 10:01:30.859568 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1965 10:01:30.866055 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1966 10:01:30.869578 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1967 10:01:30.872518 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
1968 10:01:30.875891 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1969 10:01:30.879212 iDelay=206, Bit 8, Center 69 (-34 ~ 173) 208
1970 10:01:30.886110 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1971 10:01:30.889179 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1972 10:01:30.892593 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1973 10:01:30.895846 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1974 10:01:30.899218 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1975 10:01:30.905821 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1976 10:01:30.909593 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1977 10:01:30.909691 ==
1978 10:01:30.912500 Dram Type= 6, Freq= 0, CH_1, rank 1
1979 10:01:30.916273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1980 10:01:30.916370 ==
1981 10:01:30.919908 DQS Delay:
1982 10:01:30.919990 DQS0 = 0, DQS1 = 0
1983 10:01:30.920055 DQM Delay:
1984 10:01:30.922863 DQM0 = 90, DQM1 = 81
1985 10:01:30.922946 DQ Delay:
1986 10:01:30.925964 DQ0 =101, DQ1 =77, DQ2 =77, DQ3 =85
1987 10:01:30.929456 DQ4 =93, DQ5 =101, DQ6 =101, DQ7 =85
1988 10:01:30.932873 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1989 10:01:30.936152 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1990 10:01:30.936251
1991 10:01:30.936345
1992 10:01:30.936434 ==
1993 10:01:30.939332 Dram Type= 6, Freq= 0, CH_1, rank 1
1994 10:01:30.946119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1995 10:01:30.946193 ==
1996 10:01:30.946256
1997 10:01:30.946337
1998 10:01:30.946453 TX Vref Scan disable
1999 10:01:30.949754 == TX Byte 0 ==
2000 10:01:30.952641 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2001 10:01:30.959535 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2002 10:01:30.959637 == TX Byte 1 ==
2003 10:01:30.962507 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2004 10:01:30.969364 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2005 10:01:30.969465 ==
2006 10:01:30.972654 Dram Type= 6, Freq= 0, CH_1, rank 1
2007 10:01:30.975975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2008 10:01:30.976079 ==
2009 10:01:30.988369 TX Vref=22, minBit 13, minWin=27, winSum=453
2010 10:01:30.992288 TX Vref=24, minBit 13, minWin=27, winSum=454
2011 10:01:30.995152 TX Vref=26, minBit 8, minWin=28, winSum=457
2012 10:01:30.998471 TX Vref=28, minBit 8, minWin=28, winSum=460
2013 10:01:31.001696 TX Vref=30, minBit 8, minWin=28, winSum=458
2014 10:01:31.008262 TX Vref=32, minBit 9, minWin=27, winSum=456
2015 10:01:31.011585 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 28
2016 10:01:31.011688
2017 10:01:31.015521 Final TX Range 1 Vref 28
2018 10:01:31.015594
2019 10:01:31.015663 ==
2020 10:01:31.018339 Dram Type= 6, Freq= 0, CH_1, rank 1
2021 10:01:31.022151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2022 10:01:31.022256 ==
2023 10:01:31.025071
2024 10:01:31.025181
2025 10:01:31.025275 TX Vref Scan disable
2026 10:01:31.028346 == TX Byte 0 ==
2027 10:01:31.031653 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2028 10:01:31.035232 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2029 10:01:31.038318 == TX Byte 1 ==
2030 10:01:31.042115 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2031 10:01:31.045361 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2032 10:01:31.048799
2033 10:01:31.048889 [DATLAT]
2034 10:01:31.048980 Freq=800, CH1 RK1
2035 10:01:31.049071
2036 10:01:31.051682 DATLAT Default: 0xa
2037 10:01:31.051782 0, 0xFFFF, sum = 0
2038 10:01:31.055165 1, 0xFFFF, sum = 0
2039 10:01:31.055239 2, 0xFFFF, sum = 0
2040 10:01:31.058325 3, 0xFFFF, sum = 0
2041 10:01:31.058441 4, 0xFFFF, sum = 0
2042 10:01:31.061630 5, 0xFFFF, sum = 0
2043 10:01:31.065162 6, 0xFFFF, sum = 0
2044 10:01:31.065234 7, 0xFFFF, sum = 0
2045 10:01:31.068357 8, 0xFFFF, sum = 0
2046 10:01:31.068441 9, 0x0, sum = 1
2047 10:01:31.068538 10, 0x0, sum = 2
2048 10:01:31.072035 11, 0x0, sum = 3
2049 10:01:31.072146 12, 0x0, sum = 4
2050 10:01:31.075174 best_step = 10
2051 10:01:31.075288
2052 10:01:31.075388 ==
2053 10:01:31.078356 Dram Type= 6, Freq= 0, CH_1, rank 1
2054 10:01:31.081853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2055 10:01:31.081953 ==
2056 10:01:31.084990 RX Vref Scan: 0
2057 10:01:31.085096
2058 10:01:31.085188 RX Vref 0 -> 0, step: 1
2059 10:01:31.085284
2060 10:01:31.088478 RX Delay -79 -> 252, step: 8
2061 10:01:31.094923 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2062 10:01:31.098331 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2063 10:01:31.101637 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2064 10:01:31.104930 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2065 10:01:31.108261 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2066 10:01:31.114994 iDelay=209, Bit 5, Center 104 (1 ~ 208) 208
2067 10:01:31.118742 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2068 10:01:31.121550 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2069 10:01:31.125217 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2070 10:01:31.128519 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2071 10:01:31.134887 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2072 10:01:31.138303 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2073 10:01:31.141811 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2074 10:01:31.145596 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2075 10:01:31.148397 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2076 10:01:31.155357 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2077 10:01:31.155463 ==
2078 10:01:31.158345 Dram Type= 6, Freq= 0, CH_1, rank 1
2079 10:01:31.161798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2080 10:01:31.161900 ==
2081 10:01:31.161991 DQS Delay:
2082 10:01:31.165119 DQS0 = 0, DQS1 = 0
2083 10:01:31.165218 DQM Delay:
2084 10:01:31.168572 DQM0 = 91, DQM1 = 83
2085 10:01:31.168669 DQ Delay:
2086 10:01:31.171730 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2087 10:01:31.175274 DQ4 =92, DQ5 =104, DQ6 =96, DQ7 =88
2088 10:01:31.178513 DQ8 =68, DQ9 =72, DQ10 =88, DQ11 =80
2089 10:01:31.182121 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
2090 10:01:31.182218
2091 10:01:31.182310
2092 10:01:31.188480 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e13, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2093 10:01:31.191873 CH1 RK1: MR19=606, MR18=3E13
2094 10:01:31.198260 CH1_RK1: MR19=0x606, MR18=0x3E13, DQSOSC=394, MR23=63, INC=95, DEC=63
2095 10:01:31.201660 [RxdqsGatingPostProcess] freq 800
2096 10:01:31.208468 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2097 10:01:31.208575 Pre-setting of DQS Precalculation
2098 10:01:31.214936 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2099 10:01:31.221756 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2100 10:01:31.228638 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2101 10:01:31.228740
2102 10:01:31.228833
2103 10:01:31.231824 [Calibration Summary] 1600 Mbps
2104 10:01:31.235360 CH 0, Rank 0
2105 10:01:31.235436 SW Impedance : PASS
2106 10:01:31.238373 DUTY Scan : NO K
2107 10:01:31.238456 ZQ Calibration : PASS
2108 10:01:31.241732 Jitter Meter : NO K
2109 10:01:31.245454 CBT Training : PASS
2110 10:01:31.245555 Write leveling : PASS
2111 10:01:31.248641 RX DQS gating : PASS
2112 10:01:31.251784 RX DQ/DQS(RDDQC) : PASS
2113 10:01:31.251858 TX DQ/DQS : PASS
2114 10:01:31.255000 RX DATLAT : PASS
2115 10:01:31.258733 RX DQ/DQS(Engine): PASS
2116 10:01:31.258811 TX OE : NO K
2117 10:01:31.262162 All Pass.
2118 10:01:31.262263
2119 10:01:31.262354 CH 0, Rank 1
2120 10:01:31.265435 SW Impedance : PASS
2121 10:01:31.265536 DUTY Scan : NO K
2122 10:01:31.268618 ZQ Calibration : PASS
2123 10:01:31.271969 Jitter Meter : NO K
2124 10:01:31.272070 CBT Training : PASS
2125 10:01:31.275325 Write leveling : PASS
2126 10:01:31.278241 RX DQS gating : PASS
2127 10:01:31.278323 RX DQ/DQS(RDDQC) : PASS
2128 10:01:31.282120 TX DQ/DQS : PASS
2129 10:01:31.285112 RX DATLAT : PASS
2130 10:01:31.285247 RX DQ/DQS(Engine): PASS
2131 10:01:31.288281 TX OE : NO K
2132 10:01:31.288380 All Pass.
2133 10:01:31.288474
2134 10:01:31.292030 CH 1, Rank 0
2135 10:01:31.292129 SW Impedance : PASS
2136 10:01:31.295299 DUTY Scan : NO K
2137 10:01:31.295384 ZQ Calibration : PASS
2138 10:01:31.298551 Jitter Meter : NO K
2139 10:01:31.301685 CBT Training : PASS
2140 10:01:31.301783 Write leveling : PASS
2141 10:01:31.304926 RX DQS gating : PASS
2142 10:01:31.308499 RX DQ/DQS(RDDQC) : PASS
2143 10:01:31.308597 TX DQ/DQS : PASS
2144 10:01:31.311947 RX DATLAT : PASS
2145 10:01:31.314913 RX DQ/DQS(Engine): PASS
2146 10:01:31.315013 TX OE : NO K
2147 10:01:31.318407 All Pass.
2148 10:01:31.318509
2149 10:01:31.318574 CH 1, Rank 1
2150 10:01:31.321508 SW Impedance : PASS
2151 10:01:31.321605 DUTY Scan : NO K
2152 10:01:31.325089 ZQ Calibration : PASS
2153 10:01:31.328456 Jitter Meter : NO K
2154 10:01:31.328529 CBT Training : PASS
2155 10:01:31.331883 Write leveling : PASS
2156 10:01:31.331980 RX DQS gating : PASS
2157 10:01:31.335171 RX DQ/DQS(RDDQC) : PASS
2158 10:01:31.338256 TX DQ/DQS : PASS
2159 10:01:31.338371 RX DATLAT : PASS
2160 10:01:31.341887 RX DQ/DQS(Engine): PASS
2161 10:01:31.345101 TX OE : NO K
2162 10:01:31.345204 All Pass.
2163 10:01:31.345295
2164 10:01:31.348566 DramC Write-DBI off
2165 10:01:31.348639 PER_BANK_REFRESH: Hybrid Mode
2166 10:01:31.351894 TX_TRACKING: ON
2167 10:01:31.355314 [GetDramInforAfterCalByMRR] Vendor 6.
2168 10:01:31.358670 [GetDramInforAfterCalByMRR] Revision 606.
2169 10:01:31.362075 [GetDramInforAfterCalByMRR] Revision 2 0.
2170 10:01:31.362183 MR0 0x3b3b
2171 10:01:31.365449 MR8 0x5151
2172 10:01:31.368613 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2173 10:01:31.368715
2174 10:01:31.368807 MR0 0x3b3b
2175 10:01:31.368895 MR8 0x5151
2176 10:01:31.375309 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2177 10:01:31.375415
2178 10:01:31.381727 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2179 10:01:31.384922 [FAST_K] Save calibration result to emmc
2180 10:01:31.388380 [FAST_K] Save calibration result to emmc
2181 10:01:31.391944 dram_init: config_dvfs: 1
2182 10:01:31.395223 dramc_set_vcore_voltage set vcore to 662500
2183 10:01:31.398656 Read voltage for 1200, 2
2184 10:01:31.398731 Vio18 = 0
2185 10:01:31.401759 Vcore = 662500
2186 10:01:31.401855 Vdram = 0
2187 10:01:31.401947 Vddq = 0
2188 10:01:31.402035 Vmddr = 0
2189 10:01:31.408405 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2190 10:01:31.414950 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2191 10:01:31.415034 MEM_TYPE=3, freq_sel=15
2192 10:01:31.418348 sv_algorithm_assistance_LP4_1600
2193 10:01:31.422391 ============ PULL DRAM RESETB DOWN ============
2194 10:01:31.428532 ========== PULL DRAM RESETB DOWN end =========
2195 10:01:31.432110 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2196 10:01:31.435108 ===================================
2197 10:01:31.438697 LPDDR4 DRAM CONFIGURATION
2198 10:01:31.441977 ===================================
2199 10:01:31.442061 EX_ROW_EN[0] = 0x0
2200 10:01:31.445058 EX_ROW_EN[1] = 0x0
2201 10:01:31.445141 LP4Y_EN = 0x0
2202 10:01:31.448515 WORK_FSP = 0x0
2203 10:01:31.448598 WL = 0x4
2204 10:01:31.451949 RL = 0x4
2205 10:01:31.452042 BL = 0x2
2206 10:01:31.455214 RPST = 0x0
2207 10:01:31.458704 RD_PRE = 0x0
2208 10:01:31.458779 WR_PRE = 0x1
2209 10:01:31.462075 WR_PST = 0x0
2210 10:01:31.462147 DBI_WR = 0x0
2211 10:01:31.465254 DBI_RD = 0x0
2212 10:01:31.465323 OTF = 0x1
2213 10:01:31.468564 ===================================
2214 10:01:31.472269 ===================================
2215 10:01:31.472359 ANA top config
2216 10:01:31.475285 ===================================
2217 10:01:31.478870 DLL_ASYNC_EN = 0
2218 10:01:31.481968 ALL_SLAVE_EN = 0
2219 10:01:31.485415 NEW_RANK_MODE = 1
2220 10:01:31.488619 DLL_IDLE_MODE = 1
2221 10:01:31.488691 LP45_APHY_COMB_EN = 1
2222 10:01:31.492290 TX_ODT_DIS = 1
2223 10:01:31.495497 NEW_8X_MODE = 1
2224 10:01:31.498668 ===================================
2225 10:01:31.502061 ===================================
2226 10:01:31.505487 data_rate = 2400
2227 10:01:31.508836 CKR = 1
2228 10:01:31.508914 DQ_P2S_RATIO = 8
2229 10:01:31.512497 ===================================
2230 10:01:31.515868 CA_P2S_RATIO = 8
2231 10:01:31.518986 DQ_CA_OPEN = 0
2232 10:01:31.522164 DQ_SEMI_OPEN = 0
2233 10:01:31.525448 CA_SEMI_OPEN = 0
2234 10:01:31.525532 CA_FULL_RATE = 0
2235 10:01:31.529245 DQ_CKDIV4_EN = 0
2236 10:01:31.532589 CA_CKDIV4_EN = 0
2237 10:01:31.535367 CA_PREDIV_EN = 0
2238 10:01:31.538874 PH8_DLY = 17
2239 10:01:31.542526 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2240 10:01:31.542609 DQ_AAMCK_DIV = 4
2241 10:01:31.545394 CA_AAMCK_DIV = 4
2242 10:01:31.548828 CA_ADMCK_DIV = 4
2243 10:01:31.552183 DQ_TRACK_CA_EN = 0
2244 10:01:31.555522 CA_PICK = 1200
2245 10:01:31.559047 CA_MCKIO = 1200
2246 10:01:31.562136 MCKIO_SEMI = 0
2247 10:01:31.562220 PLL_FREQ = 2366
2248 10:01:31.565597 DQ_UI_PI_RATIO = 32
2249 10:01:31.569122 CA_UI_PI_RATIO = 0
2250 10:01:31.572575 ===================================
2251 10:01:31.575420 ===================================
2252 10:01:31.579075 memory_type:LPDDR4
2253 10:01:31.579158 GP_NUM : 10
2254 10:01:31.582056 SRAM_EN : 1
2255 10:01:31.585928 MD32_EN : 0
2256 10:01:31.589034 ===================================
2257 10:01:31.589117 [ANA_INIT] >>>>>>>>>>>>>>
2258 10:01:31.592092 <<<<<< [CONFIGURE PHASE]: ANA_TX
2259 10:01:31.595868 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2260 10:01:31.598759 ===================================
2261 10:01:31.602196 data_rate = 2400,PCW = 0X5b00
2262 10:01:31.605642 ===================================
2263 10:01:31.608687 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2264 10:01:31.615565 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2265 10:01:31.619313 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2266 10:01:31.625545 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2267 10:01:31.629393 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2268 10:01:31.632177 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2269 10:01:31.632260 [ANA_INIT] flow start
2270 10:01:31.635639 [ANA_INIT] PLL >>>>>>>>
2271 10:01:31.639366 [ANA_INIT] PLL <<<<<<<<
2272 10:01:31.639810 [ANA_INIT] MIDPI >>>>>>>>
2273 10:01:31.642946 [ANA_INIT] MIDPI <<<<<<<<
2274 10:01:31.646144 [ANA_INIT] DLL >>>>>>>>
2275 10:01:31.649431 [ANA_INIT] DLL <<<<<<<<
2276 10:01:31.649930 [ANA_INIT] flow end
2277 10:01:31.653055 ============ LP4 DIFF to SE enter ============
2278 10:01:31.659483 ============ LP4 DIFF to SE exit ============
2279 10:01:31.659990 [ANA_INIT] <<<<<<<<<<<<<
2280 10:01:31.663253 [Flow] Enable top DCM control >>>>>
2281 10:01:31.666205 [Flow] Enable top DCM control <<<<<
2282 10:01:31.669687 Enable DLL master slave shuffle
2283 10:01:31.676136 ==============================================================
2284 10:01:31.676608 Gating Mode config
2285 10:01:31.682842 ==============================================================
2286 10:01:31.686140 Config description:
2287 10:01:31.692905 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2288 10:01:31.699529 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2289 10:01:31.706631 SELPH_MODE 0: By rank 1: By Phase
2290 10:01:31.709999 ==============================================================
2291 10:01:31.712998 GAT_TRACK_EN = 1
2292 10:01:31.716214 RX_GATING_MODE = 2
2293 10:01:31.719805 RX_GATING_TRACK_MODE = 2
2294 10:01:31.722813 SELPH_MODE = 1
2295 10:01:31.726272 PICG_EARLY_EN = 1
2296 10:01:31.729443 VALID_LAT_VALUE = 1
2297 10:01:31.736608 ==============================================================
2298 10:01:31.739842 Enter into Gating configuration >>>>
2299 10:01:31.742971 Exit from Gating configuration <<<<
2300 10:01:31.743399 Enter into DVFS_PRE_config >>>>>
2301 10:01:31.756209 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2302 10:01:31.759719 Exit from DVFS_PRE_config <<<<<
2303 10:01:31.763088 Enter into PICG configuration >>>>
2304 10:01:31.766332 Exit from PICG configuration <<<<
2305 10:01:31.766801 [RX_INPUT] configuration >>>>>
2306 10:01:31.769709 [RX_INPUT] configuration <<<<<
2307 10:01:31.776584 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2308 10:01:31.779670 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2309 10:01:31.786361 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2310 10:01:31.792970 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2311 10:01:31.799781 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2312 10:01:31.806101 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2313 10:01:31.809697 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2314 10:01:31.813207 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2315 10:01:31.819940 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2316 10:01:31.823366 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2317 10:01:31.826496 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2318 10:01:31.829714 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2319 10:01:31.833054 ===================================
2320 10:01:31.836494 LPDDR4 DRAM CONFIGURATION
2321 10:01:31.839569 ===================================
2322 10:01:31.842914 EX_ROW_EN[0] = 0x0
2323 10:01:31.843341 EX_ROW_EN[1] = 0x0
2324 10:01:31.846109 LP4Y_EN = 0x0
2325 10:01:31.846577 WORK_FSP = 0x0
2326 10:01:31.849659 WL = 0x4
2327 10:01:31.850061 RL = 0x4
2328 10:01:31.852933 BL = 0x2
2329 10:01:31.853335 RPST = 0x0
2330 10:01:31.856407 RD_PRE = 0x0
2331 10:01:31.856812 WR_PRE = 0x1
2332 10:01:31.859639 WR_PST = 0x0
2333 10:01:31.860019 DBI_WR = 0x0
2334 10:01:31.862851 DBI_RD = 0x0
2335 10:01:31.863242 OTF = 0x1
2336 10:01:31.866650 ===================================
2337 10:01:31.869777 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2338 10:01:31.876769 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2339 10:01:31.879891 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2340 10:01:31.883605 ===================================
2341 10:01:31.886722 LPDDR4 DRAM CONFIGURATION
2342 10:01:31.889709 ===================================
2343 10:01:31.890199 EX_ROW_EN[0] = 0x10
2344 10:01:31.893439 EX_ROW_EN[1] = 0x0
2345 10:01:31.896699 LP4Y_EN = 0x0
2346 10:01:31.897185 WORK_FSP = 0x0
2347 10:01:31.899819 WL = 0x4
2348 10:01:31.900309 RL = 0x4
2349 10:01:31.903289 BL = 0x2
2350 10:01:31.903777 RPST = 0x0
2351 10:01:31.906954 RD_PRE = 0x0
2352 10:01:31.907443 WR_PRE = 0x1
2353 10:01:31.909804 WR_PST = 0x0
2354 10:01:31.910285 DBI_WR = 0x0
2355 10:01:31.913525 DBI_RD = 0x0
2356 10:01:31.914159 OTF = 0x1
2357 10:01:31.916846 ===================================
2358 10:01:31.923126 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2359 10:01:31.923618 ==
2360 10:01:31.926367 Dram Type= 6, Freq= 0, CH_0, rank 0
2361 10:01:31.929887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2362 10:01:31.930512 ==
2363 10:01:31.932990 [Duty_Offset_Calibration]
2364 10:01:31.936509 B0:2 B1:0 CA:1
2365 10:01:31.936802
2366 10:01:31.939807 [DutyScan_Calibration_Flow] k_type=0
2367 10:01:31.947013
2368 10:01:31.947337 ==CLK 0==
2369 10:01:31.950332 Final CLK duty delay cell = -4
2370 10:01:31.953874 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2371 10:01:31.956924 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2372 10:01:31.960643 [-4] AVG Duty = 4969%(X100)
2373 10:01:31.960837
2374 10:01:31.963667 CH0 CLK Duty spec in!! Max-Min= 124%
2375 10:01:31.967015 [DutyScan_Calibration_Flow] ====Done====
2376 10:01:31.967270
2377 10:01:31.970039 [DutyScan_Calibration_Flow] k_type=1
2378 10:01:31.986044
2379 10:01:31.986377 ==DQS 0 ==
2380 10:01:31.988954 Final DQS duty delay cell = 0
2381 10:01:31.992479 [0] MAX Duty = 5187%(X100), DQS PI = 30
2382 10:01:31.995828 [0] MIN Duty = 4938%(X100), DQS PI = 0
2383 10:01:31.996231 [0] AVG Duty = 5062%(X100)
2384 10:01:31.999354
2385 10:01:31.999751 ==DQS 1 ==
2386 10:01:32.002374 Final DQS duty delay cell = -4
2387 10:01:32.005479 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2388 10:01:32.008650 [-4] MIN Duty = 4907%(X100), DQS PI = 8
2389 10:01:32.012225 [-4] AVG Duty = 5015%(X100)
2390 10:01:32.012334
2391 10:01:32.015542 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2392 10:01:32.015652
2393 10:01:32.019485 CH0 DQS 1 Duty spec in!! Max-Min= 217%
2394 10:01:32.022600 [DutyScan_Calibration_Flow] ====Done====
2395 10:01:32.023055
2396 10:01:32.026071 [DutyScan_Calibration_Flow] k_type=3
2397 10:01:32.042494
2398 10:01:32.042579 ==DQM 0 ==
2399 10:01:32.045621 Final DQM duty delay cell = 0
2400 10:01:32.049163 [0] MAX Duty = 5062%(X100), DQS PI = 24
2401 10:01:32.052192 [0] MIN Duty = 4813%(X100), DQS PI = 2
2402 10:01:32.052293 [0] AVG Duty = 4937%(X100)
2403 10:01:32.055967
2404 10:01:32.056074 ==DQM 1 ==
2405 10:01:32.058983 Final DQM duty delay cell = 0
2406 10:01:32.062199 [0] MAX Duty = 5187%(X100), DQS PI = 48
2407 10:01:32.065613 [0] MIN Duty = 5000%(X100), DQS PI = 22
2408 10:01:32.065722 [0] AVG Duty = 5093%(X100)
2409 10:01:32.068950
2410 10:01:32.072312 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2411 10:01:32.072423
2412 10:01:32.075190 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2413 10:01:32.078683 [DutyScan_Calibration_Flow] ====Done====
2414 10:01:32.078763
2415 10:01:32.082025 [DutyScan_Calibration_Flow] k_type=2
2416 10:01:32.099197
2417 10:01:32.099370 ==DQ 0 ==
2418 10:01:32.102177 Final DQ duty delay cell = -4
2419 10:01:32.105574 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2420 10:01:32.108803 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2421 10:01:32.111966 [-4] AVG Duty = 4968%(X100)
2422 10:01:32.112072
2423 10:01:32.112167 ==DQ 1 ==
2424 10:01:32.115671 Final DQ duty delay cell = 4
2425 10:01:32.118871 [4] MAX Duty = 5093%(X100), DQS PI = 4
2426 10:01:32.122040 [4] MIN Duty = 5031%(X100), DQS PI = 0
2427 10:01:32.122150 [4] AVG Duty = 5062%(X100)
2428 10:01:32.125361
2429 10:01:32.128727 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2430 10:01:32.128841
2431 10:01:32.132316 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2432 10:01:32.135669 [DutyScan_Calibration_Flow] ====Done====
2433 10:01:32.135770 ==
2434 10:01:32.138703 Dram Type= 6, Freq= 0, CH_1, rank 0
2435 10:01:32.142281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2436 10:01:32.142391 ==
2437 10:01:32.145707 [Duty_Offset_Calibration]
2438 10:01:32.145779 B0:0 B1:-1 CA:2
2439 10:01:32.145866
2440 10:01:32.148937 [DutyScan_Calibration_Flow] k_type=0
2441 10:01:32.159033
2442 10:01:32.159137 ==CLK 0==
2443 10:01:32.162238 Final CLK duty delay cell = 0
2444 10:01:32.165909 [0] MAX Duty = 5156%(X100), DQS PI = 16
2445 10:01:32.169155 [0] MIN Duty = 4938%(X100), DQS PI = 44
2446 10:01:32.169249 [0] AVG Duty = 5047%(X100)
2447 10:01:32.172206
2448 10:01:32.175721 CH1 CLK Duty spec in!! Max-Min= 218%
2449 10:01:32.179026 [DutyScan_Calibration_Flow] ====Done====
2450 10:01:32.179137
2451 10:01:32.182226 [DutyScan_Calibration_Flow] k_type=1
2452 10:01:32.198504
2453 10:01:32.198669 ==DQS 0 ==
2454 10:01:32.201477 Final DQS duty delay cell = 0
2455 10:01:32.205017 [0] MAX Duty = 5093%(X100), DQS PI = 24
2456 10:01:32.208549 [0] MIN Duty = 4969%(X100), DQS PI = 0
2457 10:01:32.208842 [0] AVG Duty = 5031%(X100)
2458 10:01:32.211848
2459 10:01:32.212139 ==DQS 1 ==
2460 10:01:32.215356 Final DQS duty delay cell = 0
2461 10:01:32.218465 [0] MAX Duty = 5156%(X100), DQS PI = 0
2462 10:01:32.221934 [0] MIN Duty = 4844%(X100), DQS PI = 36
2463 10:01:32.222474 [0] AVG Duty = 5000%(X100)
2464 10:01:32.225333
2465 10:01:32.228668 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2466 10:01:32.229242
2467 10:01:32.231976 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2468 10:01:32.235272 [DutyScan_Calibration_Flow] ====Done====
2469 10:01:32.235876
2470 10:01:32.238654 [DutyScan_Calibration_Flow] k_type=3
2471 10:01:32.255280
2472 10:01:32.255975 ==DQM 0 ==
2473 10:01:32.258633 Final DQM duty delay cell = 4
2474 10:01:32.261946 [4] MAX Duty = 5093%(X100), DQS PI = 20
2475 10:01:32.265194 [4] MIN Duty = 4969%(X100), DQS PI = 28
2476 10:01:32.265885 [4] AVG Duty = 5031%(X100)
2477 10:01:32.268448
2478 10:01:32.269077 ==DQM 1 ==
2479 10:01:32.271868 Final DQM duty delay cell = -4
2480 10:01:32.275145 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2481 10:01:32.278500 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2482 10:01:32.281941 [-4] AVG Duty = 4875%(X100)
2483 10:01:32.282584
2484 10:01:32.285190 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2485 10:01:32.285712
2486 10:01:32.288802 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2487 10:01:32.292055 [DutyScan_Calibration_Flow] ====Done====
2488 10:01:32.292687
2489 10:01:32.295542 [DutyScan_Calibration_Flow] k_type=2
2490 10:01:32.312287
2491 10:01:32.312813 ==DQ 0 ==
2492 10:01:32.315505 Final DQ duty delay cell = 0
2493 10:01:32.318718 [0] MAX Duty = 5062%(X100), DQS PI = 20
2494 10:01:32.322543 [0] MIN Duty = 4938%(X100), DQS PI = 44
2495 10:01:32.323109 [0] AVG Duty = 5000%(X100)
2496 10:01:32.325728
2497 10:01:32.326280 ==DQ 1 ==
2498 10:01:32.328910 Final DQ duty delay cell = 0
2499 10:01:32.331895 [0] MAX Duty = 5031%(X100), DQS PI = 2
2500 10:01:32.334890 [0] MIN Duty = 4813%(X100), DQS PI = 34
2501 10:01:32.334972 [0] AVG Duty = 4922%(X100)
2502 10:01:32.335041
2503 10:01:32.338653 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2504 10:01:32.338753
2505 10:01:32.342120 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2506 10:01:32.348264 [DutyScan_Calibration_Flow] ====Done====
2507 10:01:32.351471 nWR fixed to 30
2508 10:01:32.351543 [ModeRegInit_LP4] CH0 RK0
2509 10:01:32.354945 [ModeRegInit_LP4] CH0 RK1
2510 10:01:32.358506 [ModeRegInit_LP4] CH1 RK0
2511 10:01:32.358575 [ModeRegInit_LP4] CH1 RK1
2512 10:01:32.361726 match AC timing 7
2513 10:01:32.365417 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2514 10:01:32.368463 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2515 10:01:32.374671 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2516 10:01:32.378191 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2517 10:01:32.385239 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2518 10:01:32.385340 ==
2519 10:01:32.388239 Dram Type= 6, Freq= 0, CH_0, rank 0
2520 10:01:32.391798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2521 10:01:32.391869 ==
2522 10:01:32.398740 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2523 10:01:32.401748 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2524 10:01:32.411551 [CA 0] Center 38 (7~69) winsize 63
2525 10:01:32.414955 [CA 1] Center 38 (8~69) winsize 62
2526 10:01:32.418426 [CA 2] Center 35 (5~66) winsize 62
2527 10:01:32.422279 [CA 3] Center 35 (4~66) winsize 63
2528 10:01:32.425008 [CA 4] Center 34 (4~65) winsize 62
2529 10:01:32.428016 [CA 5] Center 33 (3~63) winsize 61
2530 10:01:32.428089
2531 10:01:32.431838 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2532 10:01:32.431935
2533 10:01:32.434984 [CATrainingPosCal] consider 1 rank data
2534 10:01:32.438410 u2DelayCellTimex100 = 270/100 ps
2535 10:01:32.441515 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2536 10:01:32.445004 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2537 10:01:32.452233 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2538 10:01:32.454741 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2539 10:01:32.458399 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2540 10:01:32.461959 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2541 10:01:32.462057
2542 10:01:32.465081 CA PerBit enable=1, Macro0, CA PI delay=33
2543 10:01:32.465151
2544 10:01:32.468460 [CBTSetCACLKResult] CA Dly = 33
2545 10:01:32.468548 CS Dly: 6 (0~37)
2546 10:01:32.468619 ==
2547 10:01:32.471842 Dram Type= 6, Freq= 0, CH_0, rank 1
2548 10:01:32.478294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2549 10:01:32.478436 ==
2550 10:01:32.481490 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2551 10:01:32.488347 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2552 10:01:32.497545 [CA 0] Center 39 (8~70) winsize 63
2553 10:01:32.500752 [CA 1] Center 38 (8~69) winsize 62
2554 10:01:32.503960 [CA 2] Center 35 (5~66) winsize 62
2555 10:01:32.507315 [CA 3] Center 35 (5~66) winsize 62
2556 10:01:32.510528 [CA 4] Center 34 (4~65) winsize 62
2557 10:01:32.514315 [CA 5] Center 33 (3~64) winsize 62
2558 10:01:32.514430
2559 10:01:32.517423 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2560 10:01:32.517524
2561 10:01:32.520652 [CATrainingPosCal] consider 2 rank data
2562 10:01:32.523774 u2DelayCellTimex100 = 270/100 ps
2563 10:01:32.527821 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2564 10:01:32.531121 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2565 10:01:32.537789 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2566 10:01:32.541030 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2567 10:01:32.545013 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2568 10:01:32.547955 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2569 10:01:32.548431
2570 10:01:32.551117 CA PerBit enable=1, Macro0, CA PI delay=33
2571 10:01:32.551594
2572 10:01:32.554259 [CBTSetCACLKResult] CA Dly = 33
2573 10:01:32.554767 CS Dly: 7 (0~39)
2574 10:01:32.555146
2575 10:01:32.558513 ----->DramcWriteLeveling(PI) begin...
2576 10:01:32.560896 ==
2577 10:01:32.560980 Dram Type= 6, Freq= 0, CH_0, rank 0
2578 10:01:32.567595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2579 10:01:32.567680 ==
2580 10:01:32.570770 Write leveling (Byte 0): 36 => 36
2581 10:01:32.573903 Write leveling (Byte 1): 32 => 32
2582 10:01:32.577366 DramcWriteLeveling(PI) end<-----
2583 10:01:32.577486
2584 10:01:32.577557 ==
2585 10:01:32.580889 Dram Type= 6, Freq= 0, CH_0, rank 0
2586 10:01:32.583859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2587 10:01:32.583983 ==
2588 10:01:32.587303 [Gating] SW mode calibration
2589 10:01:32.594187 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2590 10:01:32.597240 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2591 10:01:32.603861 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2592 10:01:32.607491 0 15 4 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
2593 10:01:32.610719 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2594 10:01:32.617789 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2595 10:01:32.620883 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2596 10:01:32.624230 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2597 10:01:32.630826 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2598 10:01:32.634199 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2599 10:01:32.637585 1 0 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
2600 10:01:32.643980 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 10:01:32.647254 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2602 10:01:32.650771 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2603 10:01:32.657248 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2604 10:01:32.661146 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2605 10:01:32.664469 1 0 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2606 10:01:32.667574 1 0 28 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
2607 10:01:32.673976 1 1 0 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
2608 10:01:32.677349 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 10:01:32.680893 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 10:01:32.687509 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2611 10:01:32.691081 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2612 10:01:32.694469 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2613 10:01:32.701477 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2614 10:01:32.704649 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2615 10:01:32.707852 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2616 10:01:32.714303 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 10:01:32.717610 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 10:01:32.720983 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 10:01:32.727541 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 10:01:32.731180 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 10:01:32.734339 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 10:01:32.740845 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 10:01:32.744412 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 10:01:32.747556 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 10:01:32.750958 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 10:01:32.757796 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 10:01:32.761134 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 10:01:32.764427 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 10:01:32.770905 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 10:01:32.774628 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2631 10:01:32.777755 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2632 10:01:32.781100 Total UI for P1: 0, mck2ui 16
2633 10:01:32.784249 best dqsien dly found for B0: ( 1, 3, 28)
2634 10:01:32.791141 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2635 10:01:32.791258 Total UI for P1: 0, mck2ui 16
2636 10:01:32.798076 best dqsien dly found for B1: ( 1, 4, 0)
2637 10:01:32.801018 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2638 10:01:32.804408 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2639 10:01:32.804479
2640 10:01:32.807801 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2641 10:01:32.810922 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2642 10:01:32.814243 [Gating] SW calibration Done
2643 10:01:32.814317 ==
2644 10:01:32.817929 Dram Type= 6, Freq= 0, CH_0, rank 0
2645 10:01:32.820882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2646 10:01:32.820949 ==
2647 10:01:32.824283 RX Vref Scan: 0
2648 10:01:32.824351
2649 10:01:32.824411 RX Vref 0 -> 0, step: 1
2650 10:01:32.824472
2651 10:01:32.827706 RX Delay -40 -> 252, step: 8
2652 10:01:32.830841 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2653 10:01:32.838243 iDelay=208, Bit 1, Center 119 (48 ~ 191) 144
2654 10:01:32.841464 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2655 10:01:32.845050 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2656 10:01:32.848218 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2657 10:01:32.851412 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2658 10:01:32.854969 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2659 10:01:32.861334 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2660 10:01:32.864801 iDelay=208, Bit 8, Center 103 (40 ~ 167) 128
2661 10:01:32.868181 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2662 10:01:32.871257 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2663 10:01:32.874637 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2664 10:01:32.881337 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2665 10:01:32.884946 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2666 10:01:32.888142 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2667 10:01:32.891595 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2668 10:01:32.892065 ==
2669 10:01:32.894950 Dram Type= 6, Freq= 0, CH_0, rank 0
2670 10:01:32.901279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2671 10:01:32.901754 ==
2672 10:01:32.902131 DQS Delay:
2673 10:01:32.904916 DQS0 = 0, DQS1 = 0
2674 10:01:32.905407 DQM Delay:
2675 10:01:32.905780 DQM0 = 122, DQM1 = 110
2676 10:01:32.908045 DQ Delay:
2677 10:01:32.911231 DQ0 =123, DQ1 =119, DQ2 =119, DQ3 =119
2678 10:01:32.914811 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2679 10:01:32.917936 DQ8 =103, DQ9 =99, DQ10 =107, DQ11 =107
2680 10:01:32.921248 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2681 10:01:32.921717
2682 10:01:32.922090
2683 10:01:32.922485 ==
2684 10:01:32.924714 Dram Type= 6, Freq= 0, CH_0, rank 0
2685 10:01:32.927879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2686 10:01:32.931305 ==
2687 10:01:32.931774
2688 10:01:32.932148
2689 10:01:32.932491 TX Vref Scan disable
2690 10:01:32.934982 == TX Byte 0 ==
2691 10:01:32.938238 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2692 10:01:32.941458 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2693 10:01:32.944341 == TX Byte 1 ==
2694 10:01:32.948231 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2695 10:01:32.951452 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2696 10:01:32.951930 ==
2697 10:01:32.954977 Dram Type= 6, Freq= 0, CH_0, rank 0
2698 10:01:32.961219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2699 10:01:32.961699 ==
2700 10:01:32.972230 TX Vref=22, minBit 3, minWin=24, winSum=404
2701 10:01:32.975666 TX Vref=24, minBit 0, minWin=24, winSum=406
2702 10:01:32.979643 TX Vref=26, minBit 1, minWin=25, winSum=417
2703 10:01:32.982417 TX Vref=28, minBit 1, minWin=25, winSum=420
2704 10:01:32.986154 TX Vref=30, minBit 3, minWin=25, winSum=419
2705 10:01:32.989272 TX Vref=32, minBit 1, minWin=25, winSum=415
2706 10:01:32.995925 [TxChooseVref] Worse bit 1, Min win 25, Win sum 420, Final Vref 28
2707 10:01:32.996497
2708 10:01:32.999209 Final TX Range 1 Vref 28
2709 10:01:32.999683
2710 10:01:33.000056 ==
2711 10:01:33.002452 Dram Type= 6, Freq= 0, CH_0, rank 0
2712 10:01:33.006018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2713 10:01:33.006527 ==
2714 10:01:33.006911
2715 10:01:33.007264
2716 10:01:33.009361 TX Vref Scan disable
2717 10:01:33.012657 == TX Byte 0 ==
2718 10:01:33.016223 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2719 10:01:33.019436 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2720 10:01:33.022375 == TX Byte 1 ==
2721 10:01:33.025734 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2722 10:01:33.029105 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2723 10:01:33.029707
2724 10:01:33.032773 [DATLAT]
2725 10:01:33.033366 Freq=1200, CH0 RK0
2726 10:01:33.033930
2727 10:01:33.035715 DATLAT Default: 0xd
2728 10:01:33.036266 0, 0xFFFF, sum = 0
2729 10:01:33.039708 1, 0xFFFF, sum = 0
2730 10:01:33.040314 2, 0xFFFF, sum = 0
2731 10:01:33.042729 3, 0xFFFF, sum = 0
2732 10:01:33.043282 4, 0xFFFF, sum = 0
2733 10:01:33.046213 5, 0xFFFF, sum = 0
2734 10:01:33.046893 6, 0xFFFF, sum = 0
2735 10:01:33.049235 7, 0xFFFF, sum = 0
2736 10:01:33.049820 8, 0xFFFF, sum = 0
2737 10:01:33.052460 9, 0xFFFF, sum = 0
2738 10:01:33.052920 10, 0xFFFF, sum = 0
2739 10:01:33.055961 11, 0xFFFF, sum = 0
2740 10:01:33.056346 12, 0x0, sum = 1
2741 10:01:33.058956 13, 0x0, sum = 2
2742 10:01:33.059305 14, 0x0, sum = 3
2743 10:01:33.062164 15, 0x0, sum = 4
2744 10:01:33.062589 best_step = 13
2745 10:01:33.062853
2746 10:01:33.063096 ==
2747 10:01:33.065905 Dram Type= 6, Freq= 0, CH_0, rank 0
2748 10:01:33.072692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2749 10:01:33.073169 ==
2750 10:01:33.073615 RX Vref Scan: 1
2751 10:01:33.074035
2752 10:01:33.076082 Set Vref Range= 32 -> 127
2753 10:01:33.076557
2754 10:01:33.079697 RX Vref 32 -> 127, step: 1
2755 10:01:33.080191
2756 10:01:33.080619 RX Delay -13 -> 252, step: 4
2757 10:01:33.082688
2758 10:01:33.083166 Set Vref, RX VrefLevel [Byte0]: 32
2759 10:01:33.085780 [Byte1]: 32
2760 10:01:33.090609
2761 10:01:33.091120 Set Vref, RX VrefLevel [Byte0]: 33
2762 10:01:33.093668 [Byte1]: 33
2763 10:01:33.098495
2764 10:01:33.099011 Set Vref, RX VrefLevel [Byte0]: 34
2765 10:01:33.101541 [Byte1]: 34
2766 10:01:33.106503
2767 10:01:33.107026 Set Vref, RX VrefLevel [Byte0]: 35
2768 10:01:33.109537 [Byte1]: 35
2769 10:01:33.114017
2770 10:01:33.114536 Set Vref, RX VrefLevel [Byte0]: 36
2771 10:01:33.117288 [Byte1]: 36
2772 10:01:33.121830
2773 10:01:33.122375 Set Vref, RX VrefLevel [Byte0]: 37
2774 10:01:33.125258 [Byte1]: 37
2775 10:01:33.129604
2776 10:01:33.129719 Set Vref, RX VrefLevel [Byte0]: 38
2777 10:01:33.132706 [Byte1]: 38
2778 10:01:33.138009
2779 10:01:33.138511 Set Vref, RX VrefLevel [Byte0]: 39
2780 10:01:33.141316 [Byte1]: 39
2781 10:01:33.145978
2782 10:01:33.146706 Set Vref, RX VrefLevel [Byte0]: 40
2783 10:01:33.149155 [Byte1]: 40
2784 10:01:33.153914
2785 10:01:33.154607 Set Vref, RX VrefLevel [Byte0]: 41
2786 10:01:33.156769 [Byte1]: 41
2787 10:01:33.161532
2788 10:01:33.162180 Set Vref, RX VrefLevel [Byte0]: 42
2789 10:01:33.165042 [Byte1]: 42
2790 10:01:33.169632
2791 10:01:33.170287 Set Vref, RX VrefLevel [Byte0]: 43
2792 10:01:33.172698 [Byte1]: 43
2793 10:01:33.177284
2794 10:01:33.177933 Set Vref, RX VrefLevel [Byte0]: 44
2795 10:01:33.180579 [Byte1]: 44
2796 10:01:33.185062
2797 10:01:33.185702 Set Vref, RX VrefLevel [Byte0]: 45
2798 10:01:33.188418 [Byte1]: 45
2799 10:01:33.193398
2800 10:01:33.193886 Set Vref, RX VrefLevel [Byte0]: 46
2801 10:01:33.196386 [Byte1]: 46
2802 10:01:33.201322
2803 10:01:33.201800 Set Vref, RX VrefLevel [Byte0]: 47
2804 10:01:33.204303 [Byte1]: 47
2805 10:01:33.208753
2806 10:01:33.209083 Set Vref, RX VrefLevel [Byte0]: 48
2807 10:01:33.212222 [Byte1]: 48
2808 10:01:33.216505
2809 10:01:33.216831 Set Vref, RX VrefLevel [Byte0]: 49
2810 10:01:33.220487 [Byte1]: 49
2811 10:01:33.224487
2812 10:01:33.224825 Set Vref, RX VrefLevel [Byte0]: 50
2813 10:01:33.228040 [Byte1]: 50
2814 10:01:33.232485
2815 10:01:33.232817 Set Vref, RX VrefLevel [Byte0]: 51
2816 10:01:33.235922 [Byte1]: 51
2817 10:01:33.240280
2818 10:01:33.240614 Set Vref, RX VrefLevel [Byte0]: 52
2819 10:01:33.243455 [Byte1]: 52
2820 10:01:33.248158
2821 10:01:33.248490 Set Vref, RX VrefLevel [Byte0]: 53
2822 10:01:33.251481 [Byte1]: 53
2823 10:01:33.255983
2824 10:01:33.256317 Set Vref, RX VrefLevel [Byte0]: 54
2825 10:01:33.259285 [Byte1]: 54
2826 10:01:33.263935
2827 10:01:33.264269 Set Vref, RX VrefLevel [Byte0]: 55
2828 10:01:33.267233 [Byte1]: 55
2829 10:01:33.271827
2830 10:01:33.272158 Set Vref, RX VrefLevel [Byte0]: 56
2831 10:01:33.275086 [Byte1]: 56
2832 10:01:33.279831
2833 10:01:33.280342 Set Vref, RX VrefLevel [Byte0]: 57
2834 10:01:33.283395 [Byte1]: 57
2835 10:01:33.287716
2836 10:01:33.288049 Set Vref, RX VrefLevel [Byte0]: 58
2837 10:01:33.291282 [Byte1]: 58
2838 10:01:33.295573
2839 10:01:33.295909 Set Vref, RX VrefLevel [Byte0]: 59
2840 10:01:33.298760 [Byte1]: 59
2841 10:01:33.303556
2842 10:01:33.303891 Set Vref, RX VrefLevel [Byte0]: 60
2843 10:01:33.306686 [Byte1]: 60
2844 10:01:33.311173
2845 10:01:33.311508 Set Vref, RX VrefLevel [Byte0]: 61
2846 10:01:33.314879 [Byte1]: 61
2847 10:01:33.319212
2848 10:01:33.319547 Set Vref, RX VrefLevel [Byte0]: 62
2849 10:01:33.322734 [Byte1]: 62
2850 10:01:33.327510
2851 10:01:33.327844 Set Vref, RX VrefLevel [Byte0]: 63
2852 10:01:33.330255 [Byte1]: 63
2853 10:01:33.334856
2854 10:01:33.335238 Set Vref, RX VrefLevel [Byte0]: 64
2855 10:01:33.338074 [Byte1]: 64
2856 10:01:33.342430
2857 10:01:33.342515 Set Vref, RX VrefLevel [Byte0]: 65
2858 10:01:33.345848 [Byte1]: 65
2859 10:01:33.350983
2860 10:01:33.351067 Set Vref, RX VrefLevel [Byte0]: 66
2861 10:01:33.353975 [Byte1]: 66
2862 10:01:33.358323
2863 10:01:33.358442 Set Vref, RX VrefLevel [Byte0]: 67
2864 10:01:33.361748 [Byte1]: 67
2865 10:01:33.366505
2866 10:01:33.366598 Set Vref, RX VrefLevel [Byte0]: 68
2867 10:01:33.369855 [Byte1]: 68
2868 10:01:33.374391
2869 10:01:33.374526 Final RX Vref Byte 0 = 58 to rank0
2870 10:01:33.377369 Final RX Vref Byte 1 = 50 to rank0
2871 10:01:33.380907 Final RX Vref Byte 0 = 58 to rank1
2872 10:01:33.384435 Final RX Vref Byte 1 = 50 to rank1==
2873 10:01:33.387319 Dram Type= 6, Freq= 0, CH_0, rank 0
2874 10:01:33.394572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2875 10:01:33.394729 ==
2876 10:01:33.394855 DQS Delay:
2877 10:01:33.394971 DQS0 = 0, DQS1 = 0
2878 10:01:33.397840 DQM Delay:
2879 10:01:33.398018 DQM0 = 122, DQM1 = 109
2880 10:01:33.400854 DQ Delay:
2881 10:01:33.404217 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2882 10:01:33.407473 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2883 10:01:33.411056 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =108
2884 10:01:33.414120 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2885 10:01:33.414204
2886 10:01:33.414271
2887 10:01:33.420785 [DQSOSCAuto] RK0, (LSB)MR18= 0xd0a, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
2888 10:01:33.424275 CH0 RK0: MR19=404, MR18=D0A
2889 10:01:33.430778 CH0_RK0: MR19=0x404, MR18=0xD0A, DQSOSC=405, MR23=63, INC=39, DEC=26
2890 10:01:33.430872
2891 10:01:33.434016 ----->DramcWriteLeveling(PI) begin...
2892 10:01:33.434103 ==
2893 10:01:33.437395 Dram Type= 6, Freq= 0, CH_0, rank 1
2894 10:01:33.440829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2895 10:01:33.440914 ==
2896 10:01:33.444263 Write leveling (Byte 0): 34 => 34
2897 10:01:33.447864 Write leveling (Byte 1): 30 => 30
2898 10:01:33.450852 DramcWriteLeveling(PI) end<-----
2899 10:01:33.450947
2900 10:01:33.451033 ==
2901 10:01:33.454350 Dram Type= 6, Freq= 0, CH_0, rank 1
2902 10:01:33.460759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2903 10:01:33.460875 ==
2904 10:01:33.460964 [Gating] SW mode calibration
2905 10:01:33.471166 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2906 10:01:33.474421 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2907 10:01:33.477727 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2908 10:01:33.484367 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2909 10:01:33.487776 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2910 10:01:33.491109 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2911 10:01:33.497739 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2912 10:01:33.500954 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2913 10:01:33.504505 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2914 10:01:33.511292 0 15 28 | B1->B0 | 3434 3232 | 1 0 | (0 0) (0 1)
2915 10:01:33.514458 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 10:01:33.517789 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2917 10:01:33.520883 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2918 10:01:33.527580 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2919 10:01:33.530869 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2920 10:01:33.534252 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2921 10:01:33.541031 1 0 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2922 10:01:33.544082 1 0 28 | B1->B0 | 3838 4040 | 0 0 | (0 0) (0 0)
2923 10:01:33.547599 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 10:01:33.554231 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 10:01:33.557656 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2926 10:01:33.561087 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2927 10:01:33.567608 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2928 10:01:33.570950 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2929 10:01:33.574557 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2930 10:01:33.581378 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2931 10:01:33.584388 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2932 10:01:33.587702 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 10:01:33.594250 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 10:01:33.597961 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 10:01:33.601220 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 10:01:33.607864 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 10:01:33.611394 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 10:01:33.614592 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 10:01:33.617956 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 10:01:33.624474 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 10:01:33.627775 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 10:01:33.631410 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 10:01:33.637928 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 10:01:33.641398 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 10:01:33.644713 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 10:01:33.651237 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2947 10:01:33.654623 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2948 10:01:33.658792 Total UI for P1: 0, mck2ui 16
2949 10:01:33.661565 best dqsien dly found for B1: ( 1, 3, 28)
2950 10:01:33.664641 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2951 10:01:33.667801 Total UI for P1: 0, mck2ui 16
2952 10:01:33.671655 best dqsien dly found for B0: ( 1, 3, 30)
2953 10:01:33.675087 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2954 10:01:33.678164 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2955 10:01:33.678247
2956 10:01:33.681629 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2957 10:01:33.688160 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2958 10:01:33.688244 [Gating] SW calibration Done
2959 10:01:33.688308 ==
2960 10:01:33.691403 Dram Type= 6, Freq= 0, CH_0, rank 1
2961 10:01:33.698185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2962 10:01:33.698260 ==
2963 10:01:33.698323 RX Vref Scan: 0
2964 10:01:33.698419
2965 10:01:33.701724 RX Vref 0 -> 0, step: 1
2966 10:01:33.701798
2967 10:01:33.704866 RX Delay -40 -> 252, step: 8
2968 10:01:33.708315 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2969 10:01:33.711443 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2970 10:01:33.714906 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2971 10:01:33.718214 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2972 10:01:33.725043 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2973 10:01:33.728270 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2974 10:01:33.731789 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2975 10:01:33.734927 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2976 10:01:33.738635 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2977 10:01:33.744964 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2978 10:01:33.748286 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2979 10:01:33.751522 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2980 10:01:33.755084 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2981 10:01:33.758207 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2982 10:01:33.765013 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2983 10:01:33.768780 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2984 10:01:33.768893 ==
2985 10:01:33.771725 Dram Type= 6, Freq= 0, CH_0, rank 1
2986 10:01:33.775346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2987 10:01:33.775426 ==
2988 10:01:33.778206 DQS Delay:
2989 10:01:33.778320 DQS0 = 0, DQS1 = 0
2990 10:01:33.778432 DQM Delay:
2991 10:01:33.781792 DQM0 = 120, DQM1 = 108
2992 10:01:33.781904 DQ Delay:
2993 10:01:33.785256 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2994 10:01:33.788581 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2995 10:01:33.791628 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2996 10:01:33.795007 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2997 10:01:33.798361
2998 10:01:33.798500
2999 10:01:33.798595 ==
3000 10:01:33.802179 Dram Type= 6, Freq= 0, CH_0, rank 1
3001 10:01:33.805165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3002 10:01:33.805282 ==
3003 10:01:33.805404
3004 10:01:33.805511
3005 10:01:33.808657 TX Vref Scan disable
3006 10:01:33.808741 == TX Byte 0 ==
3007 10:01:33.815542 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3008 10:01:33.819175 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3009 10:01:33.819604 == TX Byte 1 ==
3010 10:01:33.822744 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3011 10:01:33.829134 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3012 10:01:33.829924 ==
3013 10:01:33.832412 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 10:01:33.835741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 10:01:33.836221 ==
3016 10:01:33.848453 TX Vref=22, minBit 7, minWin=23, winSum=412
3017 10:01:33.851908 TX Vref=24, minBit 4, minWin=24, winSum=418
3018 10:01:33.854777 TX Vref=26, minBit 1, minWin=24, winSum=420
3019 10:01:33.857836 TX Vref=28, minBit 1, minWin=24, winSum=418
3020 10:01:33.861132 TX Vref=30, minBit 0, minWin=25, winSum=422
3021 10:01:33.864720 TX Vref=32, minBit 2, minWin=25, winSum=423
3022 10:01:33.871159 [TxChooseVref] Worse bit 2, Min win 25, Win sum 423, Final Vref 32
3023 10:01:33.871960
3024 10:01:33.874618 Final TX Range 1 Vref 32
3025 10:01:33.875349
3026 10:01:33.875996 ==
3027 10:01:33.878200 Dram Type= 6, Freq= 0, CH_0, rank 1
3028 10:01:33.881527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3029 10:01:33.882299 ==
3030 10:01:33.882982
3031 10:01:33.884876
3032 10:01:33.885500 TX Vref Scan disable
3033 10:01:33.887930 == TX Byte 0 ==
3034 10:01:33.891343 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3035 10:01:33.894984 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3036 10:01:33.898164 == TX Byte 1 ==
3037 10:01:33.901450 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3038 10:01:33.904632 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3039 10:01:33.905158
3040 10:01:33.907580 [DATLAT]
3041 10:01:33.907665 Freq=1200, CH0 RK1
3042 10:01:33.907758
3043 10:01:33.911236 DATLAT Default: 0xd
3044 10:01:33.911322 0, 0xFFFF, sum = 0
3045 10:01:33.914303 1, 0xFFFF, sum = 0
3046 10:01:33.914431 2, 0xFFFF, sum = 0
3047 10:01:33.917889 3, 0xFFFF, sum = 0
3048 10:01:33.917996 4, 0xFFFF, sum = 0
3049 10:01:33.920827 5, 0xFFFF, sum = 0
3050 10:01:33.924309 6, 0xFFFF, sum = 0
3051 10:01:33.924400 7, 0xFFFF, sum = 0
3052 10:01:33.927499 8, 0xFFFF, sum = 0
3053 10:01:33.927585 9, 0xFFFF, sum = 0
3054 10:01:33.930786 10, 0xFFFF, sum = 0
3055 10:01:33.930901 11, 0xFFFF, sum = 0
3056 10:01:33.934240 12, 0x0, sum = 1
3057 10:01:33.934343 13, 0x0, sum = 2
3058 10:01:33.937641 14, 0x0, sum = 3
3059 10:01:33.937716 15, 0x0, sum = 4
3060 10:01:33.937781 best_step = 13
3061 10:01:33.937842
3062 10:01:33.940995 ==
3063 10:01:33.944393 Dram Type= 6, Freq= 0, CH_0, rank 1
3064 10:01:33.947553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3065 10:01:33.947629 ==
3066 10:01:33.947699 RX Vref Scan: 0
3067 10:01:33.947772
3068 10:01:33.951025 RX Vref 0 -> 0, step: 1
3069 10:01:33.951103
3070 10:01:33.954101 RX Delay -21 -> 252, step: 4
3071 10:01:33.957802 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3072 10:01:33.964283 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3073 10:01:33.967636 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3074 10:01:33.970830 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3075 10:01:33.974280 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3076 10:01:33.978072 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3077 10:01:33.981150 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3078 10:01:33.987967 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3079 10:01:33.991458 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3080 10:01:33.994836 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3081 10:01:33.998322 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3082 10:01:34.000975 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3083 10:01:34.008144 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3084 10:01:34.010844 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3085 10:01:34.014585 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3086 10:01:34.017686 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3087 10:01:34.018162 ==
3088 10:01:34.021077 Dram Type= 6, Freq= 0, CH_0, rank 1
3089 10:01:34.028376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3090 10:01:34.028900 ==
3091 10:01:34.029285 DQS Delay:
3092 10:01:34.031561 DQS0 = 0, DQS1 = 0
3093 10:01:34.032103 DQM Delay:
3094 10:01:34.032648 DQM0 = 119, DQM1 = 108
3095 10:01:34.034651 DQ Delay:
3096 10:01:34.037960 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =114
3097 10:01:34.041071 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3098 10:01:34.044548 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3099 10:01:34.047851 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3100 10:01:34.047935
3101 10:01:34.048002
3102 10:01:34.054293 [DQSOSCAuto] RK1, (LSB)MR18= 0xcf3, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 405 ps
3103 10:01:34.057601 CH0 RK1: MR19=403, MR18=CF3
3104 10:01:34.064375 CH0_RK1: MR19=0x403, MR18=0xCF3, DQSOSC=405, MR23=63, INC=39, DEC=26
3105 10:01:34.067750 [RxdqsGatingPostProcess] freq 1200
3106 10:01:34.074846 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3107 10:01:34.074928 best DQS0 dly(2T, 0.5T) = (0, 11)
3108 10:01:34.077786 best DQS1 dly(2T, 0.5T) = (0, 12)
3109 10:01:34.081040 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3110 10:01:34.084297 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3111 10:01:34.088177 best DQS0 dly(2T, 0.5T) = (0, 11)
3112 10:01:34.091311 best DQS1 dly(2T, 0.5T) = (0, 11)
3113 10:01:34.094688 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3114 10:01:34.098124 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3115 10:01:34.101086 Pre-setting of DQS Precalculation
3116 10:01:34.104700 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3117 10:01:34.107880 ==
3118 10:01:34.107952 Dram Type= 6, Freq= 0, CH_1, rank 0
3119 10:01:34.114634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3120 10:01:34.114745 ==
3121 10:01:34.117680 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3122 10:01:34.124659 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3123 10:01:34.133960 [CA 0] Center 37 (7~68) winsize 62
3124 10:01:34.137098 [CA 1] Center 37 (7~68) winsize 62
3125 10:01:34.140497 [CA 2] Center 35 (5~65) winsize 61
3126 10:01:34.143655 [CA 3] Center 34 (4~65) winsize 62
3127 10:01:34.147235 [CA 4] Center 34 (4~64) winsize 61
3128 10:01:34.150794 [CA 5] Center 33 (3~64) winsize 62
3129 10:01:34.151280
3130 10:01:34.154109 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3131 10:01:34.154572
3132 10:01:34.157177 [CATrainingPosCal] consider 1 rank data
3133 10:01:34.160421 u2DelayCellTimex100 = 270/100 ps
3134 10:01:34.163551 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3135 10:01:34.167205 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3136 10:01:34.173527 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3137 10:01:34.176940 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3138 10:01:34.180120 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3139 10:01:34.183384 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3140 10:01:34.183493
3141 10:01:34.186790 CA PerBit enable=1, Macro0, CA PI delay=33
3142 10:01:34.186864
3143 10:01:34.190073 [CBTSetCACLKResult] CA Dly = 33
3144 10:01:34.190176 CS Dly: 5 (0~36)
3145 10:01:34.190268 ==
3146 10:01:34.193505 Dram Type= 6, Freq= 0, CH_1, rank 1
3147 10:01:34.200497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3148 10:01:34.200604 ==
3149 10:01:34.203639 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3150 10:01:34.210260 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3151 10:01:34.219197 [CA 0] Center 38 (8~68) winsize 61
3152 10:01:34.222988 [CA 1] Center 38 (7~69) winsize 63
3153 10:01:34.225906 [CA 2] Center 35 (5~66) winsize 62
3154 10:01:34.229358 [CA 3] Center 35 (5~65) winsize 61
3155 10:01:34.232393 [CA 4] Center 34 (5~64) winsize 60
3156 10:01:34.236038 [CA 5] Center 33 (3~64) winsize 62
3157 10:01:34.236114
3158 10:01:34.239219 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3159 10:01:34.239317
3160 10:01:34.242551 [CATrainingPosCal] consider 2 rank data
3161 10:01:34.246134 u2DelayCellTimex100 = 270/100 ps
3162 10:01:34.249439 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3163 10:01:34.252656 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3164 10:01:34.259371 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3165 10:01:34.262582 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
3166 10:01:34.265882 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3167 10:01:34.269493 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3168 10:01:34.269593
3169 10:01:34.272856 CA PerBit enable=1, Macro0, CA PI delay=33
3170 10:01:34.272933
3171 10:01:34.276206 [CBTSetCACLKResult] CA Dly = 33
3172 10:01:34.276283 CS Dly: 6 (0~39)
3173 10:01:34.276348
3174 10:01:34.279508 ----->DramcWriteLeveling(PI) begin...
3175 10:01:34.282247 ==
3176 10:01:34.285724 Dram Type= 6, Freq= 0, CH_1, rank 0
3177 10:01:34.289327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3178 10:01:34.289434 ==
3179 10:01:34.292700 Write leveling (Byte 0): 25 => 25
3180 10:01:34.295712 Write leveling (Byte 1): 30 => 30
3181 10:01:34.299559 DramcWriteLeveling(PI) end<-----
3182 10:01:34.299644
3183 10:01:34.299711 ==
3184 10:01:34.302968 Dram Type= 6, Freq= 0, CH_1, rank 0
3185 10:01:34.306244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3186 10:01:34.306329 ==
3187 10:01:34.309162 [Gating] SW mode calibration
3188 10:01:34.315614 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3189 10:01:34.319312 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3190 10:01:34.325783 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3191 10:01:34.329736 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3192 10:01:34.332639 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3193 10:01:34.339395 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3194 10:01:34.342671 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3195 10:01:34.346113 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3196 10:01:34.352899 0 15 24 | B1->B0 | 2e2e 2a2a | 0 0 | (0 0) (1 0)
3197 10:01:34.355898 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3198 10:01:34.359293 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3199 10:01:34.366167 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3200 10:01:34.369681 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3201 10:01:34.372849 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3202 10:01:34.376087 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3203 10:01:34.382699 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3204 10:01:34.386457 1 0 24 | B1->B0 | 3737 4444 | 0 0 | (0 0) (0 0)
3205 10:01:34.389595 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 10:01:34.396612 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 10:01:34.399610 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 10:01:34.403321 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3209 10:01:34.409519 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3210 10:01:34.412871 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3211 10:01:34.416256 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3212 10:01:34.422774 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3213 10:01:34.426562 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3214 10:01:34.429832 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 10:01:34.435942 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 10:01:34.439495 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 10:01:34.442856 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 10:01:34.449597 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 10:01:34.452987 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 10:01:34.456047 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 10:01:34.462823 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 10:01:34.466298 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 10:01:34.469695 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 10:01:34.472818 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 10:01:34.479287 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 10:01:34.482985 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 10:01:34.486824 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 10:01:34.493093 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3229 10:01:34.496252 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3230 10:01:34.500010 Total UI for P1: 0, mck2ui 16
3231 10:01:34.503161 best dqsien dly found for B0: ( 1, 3, 24)
3232 10:01:34.506271 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3233 10:01:34.509713 Total UI for P1: 0, mck2ui 16
3234 10:01:34.513397 best dqsien dly found for B1: ( 1, 3, 26)
3235 10:01:34.516674 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3236 10:01:34.519661 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3237 10:01:34.519746
3238 10:01:34.526267 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3239 10:01:34.529839 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3240 10:01:34.529925 [Gating] SW calibration Done
3241 10:01:34.532969 ==
3242 10:01:34.536331 Dram Type= 6, Freq= 0, CH_1, rank 0
3243 10:01:34.539939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3244 10:01:34.540024 ==
3245 10:01:34.540090 RX Vref Scan: 0
3246 10:01:34.540152
3247 10:01:34.542957 RX Vref 0 -> 0, step: 1
3248 10:01:34.543041
3249 10:01:34.546373 RX Delay -40 -> 252, step: 8
3250 10:01:34.549492 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3251 10:01:34.552801 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3252 10:01:34.556359 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3253 10:01:34.563142 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3254 10:01:34.566891 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3255 10:01:34.569766 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3256 10:01:34.573285 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3257 10:01:34.576660 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3258 10:01:34.580205 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3259 10:01:34.586741 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3260 10:01:34.590126 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3261 10:01:34.593296 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3262 10:01:34.596901 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3263 10:01:34.603585 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3264 10:01:34.606551 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3265 10:01:34.610004 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3266 10:01:34.610105 ==
3267 10:01:34.613184 Dram Type= 6, Freq= 0, CH_1, rank 0
3268 10:01:34.616860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3269 10:01:34.616965 ==
3270 10:01:34.620112 DQS Delay:
3271 10:01:34.620212 DQS0 = 0, DQS1 = 0
3272 10:01:34.620305 DQM Delay:
3273 10:01:34.623094 DQM0 = 120, DQM1 = 112
3274 10:01:34.623190 DQ Delay:
3275 10:01:34.626339 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3276 10:01:34.629910 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =119
3277 10:01:34.633170 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3278 10:01:34.640182 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3279 10:01:34.640294
3280 10:01:34.640400
3281 10:01:34.640506 ==
3282 10:01:34.643337 Dram Type= 6, Freq= 0, CH_1, rank 0
3283 10:01:34.646644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3284 10:01:34.646753 ==
3285 10:01:34.646847
3286 10:01:34.646934
3287 10:01:34.650559 TX Vref Scan disable
3288 10:01:34.650653 == TX Byte 0 ==
3289 10:01:34.656542 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3290 10:01:34.660117 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3291 10:01:34.660230 == TX Byte 1 ==
3292 10:01:34.667031 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3293 10:01:34.670577 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3294 10:01:34.670680 ==
3295 10:01:34.673427 Dram Type= 6, Freq= 0, CH_1, rank 0
3296 10:01:34.676595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3297 10:01:34.676697 ==
3298 10:01:34.689307 TX Vref=22, minBit 1, minWin=24, winSum=408
3299 10:01:34.692904 TX Vref=24, minBit 1, minWin=25, winSum=413
3300 10:01:34.695899 TX Vref=26, minBit 10, minWin=25, winSum=418
3301 10:01:34.699510 TX Vref=28, minBit 0, minWin=26, winSum=421
3302 10:01:34.702900 TX Vref=30, minBit 1, minWin=26, winSum=424
3303 10:01:34.709457 TX Vref=32, minBit 14, minWin=25, winSum=424
3304 10:01:34.712647 [TxChooseVref] Worse bit 1, Min win 26, Win sum 424, Final Vref 30
3305 10:01:34.712758
3306 10:01:34.716248 Final TX Range 1 Vref 30
3307 10:01:34.716334
3308 10:01:34.716422 ==
3309 10:01:34.719473 Dram Type= 6, Freq= 0, CH_1, rank 0
3310 10:01:34.722934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3311 10:01:34.723014 ==
3312 10:01:34.723094
3313 10:01:34.726248
3314 10:01:34.726346 TX Vref Scan disable
3315 10:01:34.729713 == TX Byte 0 ==
3316 10:01:34.732937 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3317 10:01:34.736365 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3318 10:01:34.739523 == TX Byte 1 ==
3319 10:01:34.743175 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3320 10:01:34.746309 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3321 10:01:34.746429
3322 10:01:34.749660 [DATLAT]
3323 10:01:34.749747 Freq=1200, CH1 RK0
3324 10:01:34.749846
3325 10:01:34.752901 DATLAT Default: 0xd
3326 10:01:34.753000 0, 0xFFFF, sum = 0
3327 10:01:34.756636 1, 0xFFFF, sum = 0
3328 10:01:34.756737 2, 0xFFFF, sum = 0
3329 10:01:34.759515 3, 0xFFFF, sum = 0
3330 10:01:34.759650 4, 0xFFFF, sum = 0
3331 10:01:34.762778 5, 0xFFFF, sum = 0
3332 10:01:34.762853 6, 0xFFFF, sum = 0
3333 10:01:34.766290 7, 0xFFFF, sum = 0
3334 10:01:34.769542 8, 0xFFFF, sum = 0
3335 10:01:34.769618 9, 0xFFFF, sum = 0
3336 10:01:34.772819 10, 0xFFFF, sum = 0
3337 10:01:34.772920 11, 0xFFFF, sum = 0
3338 10:01:34.775990 12, 0x0, sum = 1
3339 10:01:34.776067 13, 0x0, sum = 2
3340 10:01:34.779276 14, 0x0, sum = 3
3341 10:01:34.779354 15, 0x0, sum = 4
3342 10:01:34.779433 best_step = 13
3343 10:01:34.779509
3344 10:01:34.782669 ==
3345 10:01:34.785988 Dram Type= 6, Freq= 0, CH_1, rank 0
3346 10:01:34.789124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3347 10:01:34.789258 ==
3348 10:01:34.789360 RX Vref Scan: 1
3349 10:01:34.789488
3350 10:01:34.792551 Set Vref Range= 32 -> 127
3351 10:01:34.792656
3352 10:01:34.796146 RX Vref 32 -> 127, step: 1
3353 10:01:34.796258
3354 10:01:34.799265 RX Delay -13 -> 252, step: 4
3355 10:01:34.799371
3356 10:01:34.802728 Set Vref, RX VrefLevel [Byte0]: 32
3357 10:01:34.805766 [Byte1]: 32
3358 10:01:34.805861
3359 10:01:34.809544 Set Vref, RX VrefLevel [Byte0]: 33
3360 10:01:34.812394 [Byte1]: 33
3361 10:01:34.812493
3362 10:01:34.816356 Set Vref, RX VrefLevel [Byte0]: 34
3363 10:01:34.818984 [Byte1]: 34
3364 10:01:34.823772
3365 10:01:34.823876 Set Vref, RX VrefLevel [Byte0]: 35
3366 10:01:34.827090 [Byte1]: 35
3367 10:01:34.831652
3368 10:01:34.831726 Set Vref, RX VrefLevel [Byte0]: 36
3369 10:01:34.835284 [Byte1]: 36
3370 10:01:34.839241
3371 10:01:34.839337 Set Vref, RX VrefLevel [Byte0]: 37
3372 10:01:34.842898 [Byte1]: 37
3373 10:01:34.847406
3374 10:01:34.847506 Set Vref, RX VrefLevel [Byte0]: 38
3375 10:01:34.850522 [Byte1]: 38
3376 10:01:34.855302
3377 10:01:34.855370 Set Vref, RX VrefLevel [Byte0]: 39
3378 10:01:34.858400 [Byte1]: 39
3379 10:01:34.863063
3380 10:01:34.863130 Set Vref, RX VrefLevel [Byte0]: 40
3381 10:01:34.866267 [Byte1]: 40
3382 10:01:34.870902
3383 10:01:34.870993 Set Vref, RX VrefLevel [Byte0]: 41
3384 10:01:34.874339 [Byte1]: 41
3385 10:01:34.878724
3386 10:01:34.878799 Set Vref, RX VrefLevel [Byte0]: 42
3387 10:01:34.885064 [Byte1]: 42
3388 10:01:34.885171
3389 10:01:34.888531 Set Vref, RX VrefLevel [Byte0]: 43
3390 10:01:34.892047 [Byte1]: 43
3391 10:01:34.892143
3392 10:01:34.895470 Set Vref, RX VrefLevel [Byte0]: 44
3393 10:01:34.898683 [Byte1]: 44
3394 10:01:34.902360
3395 10:01:34.902477 Set Vref, RX VrefLevel [Byte0]: 45
3396 10:01:34.905848 [Byte1]: 45
3397 10:01:34.910253
3398 10:01:34.910349 Set Vref, RX VrefLevel [Byte0]: 46
3399 10:01:34.913637 [Byte1]: 46
3400 10:01:34.918333
3401 10:01:34.918437 Set Vref, RX VrefLevel [Byte0]: 47
3402 10:01:34.921923 [Byte1]: 47
3403 10:01:34.926603
3404 10:01:34.926698 Set Vref, RX VrefLevel [Byte0]: 48
3405 10:01:34.929761 [Byte1]: 48
3406 10:01:34.934034
3407 10:01:34.934146 Set Vref, RX VrefLevel [Byte0]: 49
3408 10:01:34.937355 [Byte1]: 49
3409 10:01:34.942102
3410 10:01:34.942182 Set Vref, RX VrefLevel [Byte0]: 50
3411 10:01:34.945414 [Byte1]: 50
3412 10:01:34.949633
3413 10:01:34.949705 Set Vref, RX VrefLevel [Byte0]: 51
3414 10:01:34.953006 [Byte1]: 51
3415 10:01:34.957723
3416 10:01:34.957793 Set Vref, RX VrefLevel [Byte0]: 52
3417 10:01:34.961036 [Byte1]: 52
3418 10:01:34.965605
3419 10:01:34.965697 Set Vref, RX VrefLevel [Byte0]: 53
3420 10:01:34.968965 [Byte1]: 53
3421 10:01:34.973353
3422 10:01:34.973448 Set Vref, RX VrefLevel [Byte0]: 54
3423 10:01:34.976561 [Byte1]: 54
3424 10:01:34.981337
3425 10:01:34.981433 Set Vref, RX VrefLevel [Byte0]: 55
3426 10:01:34.984557 [Byte1]: 55
3427 10:01:34.989187
3428 10:01:34.989287 Set Vref, RX VrefLevel [Byte0]: 56
3429 10:01:34.992345 [Byte1]: 56
3430 10:01:34.997349
3431 10:01:34.997447 Set Vref, RX VrefLevel [Byte0]: 57
3432 10:01:35.000853 [Byte1]: 57
3433 10:01:35.005240
3434 10:01:35.005335 Set Vref, RX VrefLevel [Byte0]: 58
3435 10:01:35.008590 [Byte1]: 58
3436 10:01:35.012832
3437 10:01:35.012934 Set Vref, RX VrefLevel [Byte0]: 59
3438 10:01:35.016077 [Byte1]: 59
3439 10:01:35.020740
3440 10:01:35.020815 Set Vref, RX VrefLevel [Byte0]: 60
3441 10:01:35.024389 [Byte1]: 60
3442 10:01:35.028680
3443 10:01:35.028776 Set Vref, RX VrefLevel [Byte0]: 61
3444 10:01:35.032051 [Byte1]: 61
3445 10:01:35.036565
3446 10:01:35.036665 Set Vref, RX VrefLevel [Byte0]: 62
3447 10:01:35.040012 [Byte1]: 62
3448 10:01:35.044506
3449 10:01:35.044601 Set Vref, RX VrefLevel [Byte0]: 63
3450 10:01:35.047885 [Byte1]: 63
3451 10:01:35.052346
3452 10:01:35.052440 Set Vref, RX VrefLevel [Byte0]: 64
3453 10:01:35.055497 [Byte1]: 64
3454 10:01:35.060249
3455 10:01:35.060342 Set Vref, RX VrefLevel [Byte0]: 65
3456 10:01:35.063471 [Byte1]: 65
3457 10:01:35.067836
3458 10:01:35.067904 Set Vref, RX VrefLevel [Byte0]: 66
3459 10:01:35.071286 [Byte1]: 66
3460 10:01:35.076088
3461 10:01:35.076194 Set Vref, RX VrefLevel [Byte0]: 67
3462 10:01:35.079546 [Byte1]: 67
3463 10:01:35.083958
3464 10:01:35.084078 Final RX Vref Byte 0 = 54 to rank0
3465 10:01:35.087249 Final RX Vref Byte 1 = 58 to rank0
3466 10:01:35.090702 Final RX Vref Byte 0 = 54 to rank1
3467 10:01:35.093804 Final RX Vref Byte 1 = 58 to rank1==
3468 10:01:35.097492 Dram Type= 6, Freq= 0, CH_1, rank 0
3469 10:01:35.104350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3470 10:01:35.104440 ==
3471 10:01:35.104511 DQS Delay:
3472 10:01:35.104577 DQS0 = 0, DQS1 = 0
3473 10:01:35.107602 DQM Delay:
3474 10:01:35.107781 DQM0 = 119, DQM1 = 113
3475 10:01:35.110777 DQ Delay:
3476 10:01:35.113856 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3477 10:01:35.117369 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =118
3478 10:01:35.120419 DQ8 =102, DQ9 =100, DQ10 =118, DQ11 =108
3479 10:01:35.124187 DQ12 =124, DQ13 =118, DQ14 =120, DQ15 =120
3480 10:01:35.124351
3481 10:01:35.124477
3482 10:01:35.130735 [DQSOSCAuto] RK0, (LSB)MR18= 0x518, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 408 ps
3483 10:01:35.133883 CH1 RK0: MR19=404, MR18=518
3484 10:01:35.140905 CH1_RK0: MR19=0x404, MR18=0x518, DQSOSC=400, MR23=63, INC=40, DEC=27
3485 10:01:35.140981
3486 10:01:35.143992 ----->DramcWriteLeveling(PI) begin...
3487 10:01:35.144063 ==
3488 10:01:35.147515 Dram Type= 6, Freq= 0, CH_1, rank 1
3489 10:01:35.150602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3490 10:01:35.150682 ==
3491 10:01:35.154162 Write leveling (Byte 0): 24 => 24
3492 10:01:35.157357 Write leveling (Byte 1): 29 => 29
3493 10:01:35.160731 DramcWriteLeveling(PI) end<-----
3494 10:01:35.160800
3495 10:01:35.160862 ==
3496 10:01:35.163936 Dram Type= 6, Freq= 0, CH_1, rank 1
3497 10:01:35.167201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3498 10:01:35.170883 ==
3499 10:01:35.170954 [Gating] SW mode calibration
3500 10:01:35.180609 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3501 10:01:35.184517 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3502 10:01:35.187455 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3503 10:01:35.194479 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3504 10:01:35.197314 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3505 10:01:35.200890 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3506 10:01:35.207449 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3507 10:01:35.211101 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3508 10:01:35.214059 0 15 24 | B1->B0 | 2d2d 3434 | 1 1 | (1 0) (1 0)
3509 10:01:35.220651 0 15 28 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 0)
3510 10:01:35.223732 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3511 10:01:35.227311 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3512 10:01:35.234322 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3513 10:01:35.237377 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3514 10:01:35.241136 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3515 10:01:35.247257 1 0 20 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
3516 10:01:35.250672 1 0 24 | B1->B0 | 3737 2828 | 0 0 | (0 0) (0 0)
3517 10:01:35.254103 1 0 28 | B1->B0 | 4646 3e3e | 0 0 | (0 0) (0 0)
3518 10:01:35.257385 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3519 10:01:35.263960 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3520 10:01:35.267683 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3521 10:01:35.271038 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3522 10:01:35.277945 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3523 10:01:35.280807 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3524 10:01:35.284389 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3525 10:01:35.291299 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3526 10:01:35.294712 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 10:01:35.298096 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 10:01:35.304896 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 10:01:35.307525 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 10:01:35.311309 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 10:01:35.317450 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 10:01:35.320729 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 10:01:35.323880 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 10:01:35.330614 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 10:01:35.333869 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 10:01:35.337232 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 10:01:35.344076 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 10:01:35.347161 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 10:01:35.350937 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 10:01:35.353876 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3541 10:01:35.360586 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3542 10:01:35.364208 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3543 10:01:35.367604 Total UI for P1: 0, mck2ui 16
3544 10:01:35.370865 best dqsien dly found for B0: ( 1, 3, 26)
3545 10:01:35.374084 Total UI for P1: 0, mck2ui 16
3546 10:01:35.377262 best dqsien dly found for B1: ( 1, 3, 26)
3547 10:01:35.380641 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3548 10:01:35.383918 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3549 10:01:35.384018
3550 10:01:35.387545 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3551 10:01:35.391020 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3552 10:01:35.394060 [Gating] SW calibration Done
3553 10:01:35.394159 ==
3554 10:01:35.397225 Dram Type= 6, Freq= 0, CH_1, rank 1
3555 10:01:35.400936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3556 10:01:35.403967 ==
3557 10:01:35.404071 RX Vref Scan: 0
3558 10:01:35.404162
3559 10:01:35.407367 RX Vref 0 -> 0, step: 1
3560 10:01:35.407500
3561 10:01:35.410720 RX Delay -40 -> 252, step: 8
3562 10:01:35.413942 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3563 10:01:35.417458 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3564 10:01:35.420564 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3565 10:01:35.423939 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3566 10:01:35.430655 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3567 10:01:35.433708 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3568 10:01:35.436997 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3569 10:01:35.440413 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3570 10:01:35.443955 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3571 10:01:35.450584 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3572 10:01:35.454553 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3573 10:01:35.457272 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3574 10:01:35.460861 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3575 10:01:35.463976 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3576 10:01:35.470485 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3577 10:01:35.473789 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3578 10:01:35.473889 ==
3579 10:01:35.477194 Dram Type= 6, Freq= 0, CH_1, rank 1
3580 10:01:35.480476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3581 10:01:35.480582 ==
3582 10:01:35.483812 DQS Delay:
3583 10:01:35.483908 DQS0 = 0, DQS1 = 0
3584 10:01:35.483973 DQM Delay:
3585 10:01:35.487101 DQM0 = 119, DQM1 = 113
3586 10:01:35.487182 DQ Delay:
3587 10:01:35.490669 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3588 10:01:35.493671 DQ4 =115, DQ5 =131, DQ6 =127, DQ7 =119
3589 10:01:35.497084 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3590 10:01:35.504033 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3591 10:01:35.504137
3592 10:01:35.504233
3593 10:01:35.504326 ==
3594 10:01:35.507019 Dram Type= 6, Freq= 0, CH_1, rank 1
3595 10:01:35.510410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3596 10:01:35.510481 ==
3597 10:01:35.510544
3598 10:01:35.510624
3599 10:01:35.514285 TX Vref Scan disable
3600 10:01:35.514387 == TX Byte 0 ==
3601 10:01:35.520942 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3602 10:01:35.524401 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3603 10:01:35.524473 == TX Byte 1 ==
3604 10:01:35.530372 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3605 10:01:35.533984 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3606 10:01:35.534067 ==
3607 10:01:35.537152 Dram Type= 6, Freq= 0, CH_1, rank 1
3608 10:01:35.540352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3609 10:01:35.540451 ==
3610 10:01:35.553292 TX Vref=22, minBit 1, minWin=25, winSum=413
3611 10:01:35.556546 TX Vref=24, minBit 1, minWin=25, winSum=419
3612 10:01:35.560225 TX Vref=26, minBit 1, minWin=26, winSum=426
3613 10:01:35.563206 TX Vref=28, minBit 1, minWin=26, winSum=430
3614 10:01:35.566626 TX Vref=30, minBit 1, minWin=26, winSum=427
3615 10:01:35.573159 TX Vref=32, minBit 1, minWin=26, winSum=426
3616 10:01:35.576142 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 28
3617 10:01:35.576252
3618 10:01:35.579492 Final TX Range 1 Vref 28
3619 10:01:35.579594
3620 10:01:35.579688 ==
3621 10:01:35.582966 Dram Type= 6, Freq= 0, CH_1, rank 1
3622 10:01:35.586048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3623 10:01:35.589878 ==
3624 10:01:35.590011
3625 10:01:35.590105
3626 10:01:35.590216 TX Vref Scan disable
3627 10:01:35.593225 == TX Byte 0 ==
3628 10:01:35.596608 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3629 10:01:35.599494 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3630 10:01:35.602692 == TX Byte 1 ==
3631 10:01:35.606472 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3632 10:01:35.609613 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3633 10:01:35.612857
3634 10:01:35.612954 [DATLAT]
3635 10:01:35.613059 Freq=1200, CH1 RK1
3636 10:01:35.613149
3637 10:01:35.616274 DATLAT Default: 0xd
3638 10:01:35.616373 0, 0xFFFF, sum = 0
3639 10:01:35.619708 1, 0xFFFF, sum = 0
3640 10:01:35.623028 2, 0xFFFF, sum = 0
3641 10:01:35.623101 3, 0xFFFF, sum = 0
3642 10:01:35.626270 4, 0xFFFF, sum = 0
3643 10:01:35.626376 5, 0xFFFF, sum = 0
3644 10:01:35.629470 6, 0xFFFF, sum = 0
3645 10:01:35.629583 7, 0xFFFF, sum = 0
3646 10:01:35.633253 8, 0xFFFF, sum = 0
3647 10:01:35.633394 9, 0xFFFF, sum = 0
3648 10:01:35.636110 10, 0xFFFF, sum = 0
3649 10:01:35.636182 11, 0xFFFF, sum = 0
3650 10:01:35.639425 12, 0x0, sum = 1
3651 10:01:35.639584 13, 0x0, sum = 2
3652 10:01:35.642718 14, 0x0, sum = 3
3653 10:01:35.642828 15, 0x0, sum = 4
3654 10:01:35.642922 best_step = 13
3655 10:01:35.646001
3656 10:01:35.646113 ==
3657 10:01:35.649313 Dram Type= 6, Freq= 0, CH_1, rank 1
3658 10:01:35.652646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3659 10:01:35.652736 ==
3660 10:01:35.652803 RX Vref Scan: 0
3661 10:01:35.652865
3662 10:01:35.655768 RX Vref 0 -> 0, step: 1
3663 10:01:35.655881
3664 10:01:35.659248 RX Delay -13 -> 252, step: 4
3665 10:01:35.662687 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3666 10:01:35.669186 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3667 10:01:35.672641 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3668 10:01:35.676233 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3669 10:01:35.679715 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3670 10:01:35.682777 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3671 10:01:35.689414 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3672 10:01:35.692784 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3673 10:01:35.695728 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3674 10:01:35.699380 iDelay=195, Bit 9, Center 104 (39 ~ 170) 132
3675 10:01:35.702602 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3676 10:01:35.709081 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3677 10:01:35.712422 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3678 10:01:35.715884 iDelay=195, Bit 13, Center 120 (55 ~ 186) 132
3679 10:01:35.719387 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3680 10:01:35.722418 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3681 10:01:35.726263 ==
3682 10:01:35.729242 Dram Type= 6, Freq= 0, CH_1, rank 1
3683 10:01:35.732329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3684 10:01:35.732446 ==
3685 10:01:35.732547 DQS Delay:
3686 10:01:35.735919 DQS0 = 0, DQS1 = 0
3687 10:01:35.736033 DQM Delay:
3688 10:01:35.739184 DQM0 = 119, DQM1 = 113
3689 10:01:35.739270 DQ Delay:
3690 10:01:35.742335 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =116
3691 10:01:35.745773 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3692 10:01:35.749307 DQ8 =100, DQ9 =104, DQ10 =112, DQ11 =108
3693 10:01:35.752508 DQ12 =122, DQ13 =120, DQ14 =120, DQ15 =124
3694 10:01:35.752594
3695 10:01:35.752663
3696 10:01:35.762699 [DQSOSCAuto] RK1, (LSB)MR18= 0xbef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3697 10:01:35.762787 CH1 RK1: MR19=403, MR18=BEF
3698 10:01:35.769015 CH1_RK1: MR19=0x403, MR18=0xBEF, DQSOSC=405, MR23=63, INC=39, DEC=26
3699 10:01:35.772539 [RxdqsGatingPostProcess] freq 1200
3700 10:01:35.779240 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3701 10:01:35.782723 best DQS0 dly(2T, 0.5T) = (0, 11)
3702 10:01:35.786100 best DQS1 dly(2T, 0.5T) = (0, 11)
3703 10:01:35.789270 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3704 10:01:35.792941 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3705 10:01:35.795691 best DQS0 dly(2T, 0.5T) = (0, 11)
3706 10:01:35.799003 best DQS1 dly(2T, 0.5T) = (0, 11)
3707 10:01:35.802408 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3708 10:01:35.805826 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3709 10:01:35.806132 Pre-setting of DQS Precalculation
3710 10:01:35.812532 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3711 10:01:35.818728 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3712 10:01:35.825465 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3713 10:01:35.825554
3714 10:01:35.825625
3715 10:01:35.828819 [Calibration Summary] 2400 Mbps
3716 10:01:35.832186 CH 0, Rank 0
3717 10:01:35.832281 SW Impedance : PASS
3718 10:01:35.836029 DUTY Scan : NO K
3719 10:01:35.839171 ZQ Calibration : PASS
3720 10:01:35.839740 Jitter Meter : NO K
3721 10:01:35.842453 CBT Training : PASS
3722 10:01:35.845807 Write leveling : PASS
3723 10:01:35.846278 RX DQS gating : PASS
3724 10:01:35.848752 RX DQ/DQS(RDDQC) : PASS
3725 10:01:35.852211 TX DQ/DQS : PASS
3726 10:01:35.852682 RX DATLAT : PASS
3727 10:01:35.855448 RX DQ/DQS(Engine): PASS
3728 10:01:35.855916 TX OE : NO K
3729 10:01:35.858777 All Pass.
3730 10:01:35.859245
3731 10:01:35.859614 CH 0, Rank 1
3732 10:01:35.862251 SW Impedance : PASS
3733 10:01:35.862754 DUTY Scan : NO K
3734 10:01:35.866091 ZQ Calibration : PASS
3735 10:01:35.869486 Jitter Meter : NO K
3736 10:01:35.869953 CBT Training : PASS
3737 10:01:35.872144 Write leveling : PASS
3738 10:01:35.875699 RX DQS gating : PASS
3739 10:01:35.876169 RX DQ/DQS(RDDQC) : PASS
3740 10:01:35.878613 TX DQ/DQS : PASS
3741 10:01:35.882323 RX DATLAT : PASS
3742 10:01:35.882858 RX DQ/DQS(Engine): PASS
3743 10:01:35.884954 TX OE : NO K
3744 10:01:35.885362 All Pass.
3745 10:01:35.885976
3746 10:01:35.888434 CH 1, Rank 0
3747 10:01:35.888905 SW Impedance : PASS
3748 10:01:35.892108 DUTY Scan : NO K
3749 10:01:35.895444 ZQ Calibration : PASS
3750 10:01:35.895910 Jitter Meter : NO K
3751 10:01:35.898894 CBT Training : PASS
3752 10:01:35.902078 Write leveling : PASS
3753 10:01:35.902814 RX DQS gating : PASS
3754 10:01:35.905101 RX DQ/DQS(RDDQC) : PASS
3755 10:01:35.908568 TX DQ/DQS : PASS
3756 10:01:35.909233 RX DATLAT : PASS
3757 10:01:35.911616 RX DQ/DQS(Engine): PASS
3758 10:01:35.912353 TX OE : NO K
3759 10:01:35.915040 All Pass.
3760 10:01:35.915721
3761 10:01:35.916351 CH 1, Rank 1
3762 10:01:35.918488 SW Impedance : PASS
3763 10:01:35.919228 DUTY Scan : NO K
3764 10:01:35.922168 ZQ Calibration : PASS
3765 10:01:35.925509 Jitter Meter : NO K
3766 10:01:35.926219 CBT Training : PASS
3767 10:01:35.928510 Write leveling : PASS
3768 10:01:35.931957 RX DQS gating : PASS
3769 10:01:35.932673 RX DQ/DQS(RDDQC) : PASS
3770 10:01:35.934852 TX DQ/DQS : PASS
3771 10:01:35.938426 RX DATLAT : PASS
3772 10:01:35.939165 RX DQ/DQS(Engine): PASS
3773 10:01:35.941891 TX OE : NO K
3774 10:01:35.942610 All Pass.
3775 10:01:35.943223
3776 10:01:35.944998 DramC Write-DBI off
3777 10:01:35.948172 PER_BANK_REFRESH: Hybrid Mode
3778 10:01:35.948565 TX_TRACKING: ON
3779 10:01:35.958242 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3780 10:01:35.961554 [FAST_K] Save calibration result to emmc
3781 10:01:35.964650 dramc_set_vcore_voltage set vcore to 650000
3782 10:01:35.967963 Read voltage for 600, 5
3783 10:01:35.968158 Vio18 = 0
3784 10:01:35.968314 Vcore = 650000
3785 10:01:35.971218 Vdram = 0
3786 10:01:35.971302 Vddq = 0
3787 10:01:35.971369 Vmddr = 0
3788 10:01:35.977944 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3789 10:01:35.981363 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3790 10:01:35.984514 MEM_TYPE=3, freq_sel=19
3791 10:01:35.988011 sv_algorithm_assistance_LP4_1600
3792 10:01:35.991095 ============ PULL DRAM RESETB DOWN ============
3793 10:01:35.994378 ========== PULL DRAM RESETB DOWN end =========
3794 10:01:36.000945 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3795 10:01:36.004464 ===================================
3796 10:01:36.007541 LPDDR4 DRAM CONFIGURATION
3797 10:01:36.010932 ===================================
3798 10:01:36.011016 EX_ROW_EN[0] = 0x0
3799 10:01:36.014161 EX_ROW_EN[1] = 0x0
3800 10:01:36.014244 LP4Y_EN = 0x0
3801 10:01:36.017415 WORK_FSP = 0x0
3802 10:01:36.017499 WL = 0x2
3803 10:01:36.021237 RL = 0x2
3804 10:01:36.021320 BL = 0x2
3805 10:01:36.024177 RPST = 0x0
3806 10:01:36.024270 RD_PRE = 0x0
3807 10:01:36.027611 WR_PRE = 0x1
3808 10:01:36.027694 WR_PST = 0x0
3809 10:01:36.031355 DBI_WR = 0x0
3810 10:01:36.031438 DBI_RD = 0x0
3811 10:01:36.034346 OTF = 0x1
3812 10:01:36.037616 ===================================
3813 10:01:36.040631 ===================================
3814 10:01:36.040715 ANA top config
3815 10:01:36.044522 ===================================
3816 10:01:36.047248 DLL_ASYNC_EN = 0
3817 10:01:36.050830 ALL_SLAVE_EN = 1
3818 10:01:36.054108 NEW_RANK_MODE = 1
3819 10:01:36.054191 DLL_IDLE_MODE = 1
3820 10:01:36.057540 LP45_APHY_COMB_EN = 1
3821 10:01:36.060943 TX_ODT_DIS = 1
3822 10:01:36.064078 NEW_8X_MODE = 1
3823 10:01:36.067269 ===================================
3824 10:01:36.070867 ===================================
3825 10:01:36.074309 data_rate = 1200
3826 10:01:36.074419 CKR = 1
3827 10:01:36.077242 DQ_P2S_RATIO = 8
3828 10:01:36.080643 ===================================
3829 10:01:36.084009 CA_P2S_RATIO = 8
3830 10:01:36.087584 DQ_CA_OPEN = 0
3831 10:01:36.090909 DQ_SEMI_OPEN = 0
3832 10:01:36.094296 CA_SEMI_OPEN = 0
3833 10:01:36.094372 CA_FULL_RATE = 0
3834 10:01:36.097436 DQ_CKDIV4_EN = 1
3835 10:01:36.100796 CA_CKDIV4_EN = 1
3836 10:01:36.104160 CA_PREDIV_EN = 0
3837 10:01:36.107222 PH8_DLY = 0
3838 10:01:36.110886 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3839 10:01:36.110961 DQ_AAMCK_DIV = 4
3840 10:01:36.114212 CA_AAMCK_DIV = 4
3841 10:01:36.117421 CA_ADMCK_DIV = 4
3842 10:01:36.121013 DQ_TRACK_CA_EN = 0
3843 10:01:36.124171 CA_PICK = 600
3844 10:01:36.127492 CA_MCKIO = 600
3845 10:01:36.127565 MCKIO_SEMI = 0
3846 10:01:36.131093 PLL_FREQ = 2288
3847 10:01:36.134246 DQ_UI_PI_RATIO = 32
3848 10:01:36.137624 CA_UI_PI_RATIO = 0
3849 10:01:36.140558 ===================================
3850 10:01:36.143742 ===================================
3851 10:01:36.147265 memory_type:LPDDR4
3852 10:01:36.147335 GP_NUM : 10
3853 10:01:36.150631 SRAM_EN : 1
3854 10:01:36.154044 MD32_EN : 0
3855 10:01:36.157121 ===================================
3856 10:01:36.157190 [ANA_INIT] >>>>>>>>>>>>>>
3857 10:01:36.160903 <<<<<< [CONFIGURE PHASE]: ANA_TX
3858 10:01:36.163950 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3859 10:01:36.167390 ===================================
3860 10:01:36.170595 data_rate = 1200,PCW = 0X5800
3861 10:01:36.173820 ===================================
3862 10:01:36.177294 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3863 10:01:36.183690 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3864 10:01:36.187155 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3865 10:01:36.193782 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3866 10:01:36.197201 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3867 10:01:36.200940 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3868 10:01:36.201025 [ANA_INIT] flow start
3869 10:01:36.204205 [ANA_INIT] PLL >>>>>>>>
3870 10:01:36.207235 [ANA_INIT] PLL <<<<<<<<
3871 10:01:36.207319 [ANA_INIT] MIDPI >>>>>>>>
3872 10:01:36.210889 [ANA_INIT] MIDPI <<<<<<<<
3873 10:01:36.213852 [ANA_INIT] DLL >>>>>>>>
3874 10:01:36.213936 [ANA_INIT] flow end
3875 10:01:36.220548 ============ LP4 DIFF to SE enter ============
3876 10:01:36.223831 ============ LP4 DIFF to SE exit ============
3877 10:01:36.227300 [ANA_INIT] <<<<<<<<<<<<<
3878 10:01:36.230381 [Flow] Enable top DCM control >>>>>
3879 10:01:36.233988 [Flow] Enable top DCM control <<<<<
3880 10:01:36.234129 Enable DLL master slave shuffle
3881 10:01:36.240175 ==============================================================
3882 10:01:36.243904 Gating Mode config
3883 10:01:36.246810 ==============================================================
3884 10:01:36.250437 Config description:
3885 10:01:36.260229 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3886 10:01:36.267251 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3887 10:01:36.269926 SELPH_MODE 0: By rank 1: By Phase
3888 10:01:36.276690 ==============================================================
3889 10:01:36.280431 GAT_TRACK_EN = 1
3890 10:01:36.283664 RX_GATING_MODE = 2
3891 10:01:36.286931 RX_GATING_TRACK_MODE = 2
3892 10:01:36.290031 SELPH_MODE = 1
3893 10:01:36.290141 PICG_EARLY_EN = 1
3894 10:01:36.293412 VALID_LAT_VALUE = 1
3895 10:01:36.300119 ==============================================================
3896 10:01:36.303531 Enter into Gating configuration >>>>
3897 10:01:36.306584 Exit from Gating configuration <<<<
3898 10:01:36.309857 Enter into DVFS_PRE_config >>>>>
3899 10:01:36.319960 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3900 10:01:36.323331 Exit from DVFS_PRE_config <<<<<
3901 10:01:36.326693 Enter into PICG configuration >>>>
3902 10:01:36.329939 Exit from PICG configuration <<<<
3903 10:01:36.333178 [RX_INPUT] configuration >>>>>
3904 10:01:36.336260 [RX_INPUT] configuration <<<<<
3905 10:01:36.339651 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3906 10:01:36.346318 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3907 10:01:36.353047 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3908 10:01:36.359507 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3909 10:01:36.366250 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3910 10:01:36.373274 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3911 10:01:36.376315 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3912 10:01:36.379836 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3913 10:01:36.383126 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3914 10:01:36.386184 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3915 10:01:36.393280 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3916 10:01:36.396275 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3917 10:01:36.399454 ===================================
3918 10:01:36.402823 LPDDR4 DRAM CONFIGURATION
3919 10:01:36.406335 ===================================
3920 10:01:36.406449 EX_ROW_EN[0] = 0x0
3921 10:01:36.409573 EX_ROW_EN[1] = 0x0
3922 10:01:36.409657 LP4Y_EN = 0x0
3923 10:01:36.413083 WORK_FSP = 0x0
3924 10:01:36.413156 WL = 0x2
3925 10:01:36.416309 RL = 0x2
3926 10:01:36.416379 BL = 0x2
3927 10:01:36.419552 RPST = 0x0
3928 10:01:36.422930 RD_PRE = 0x0
3929 10:01:36.423009 WR_PRE = 0x1
3930 10:01:36.426545 WR_PST = 0x0
3931 10:01:36.426626 DBI_WR = 0x0
3932 10:01:36.429216 DBI_RD = 0x0
3933 10:01:36.429285 OTF = 0x1
3934 10:01:36.433116 ===================================
3935 10:01:36.436353 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3936 10:01:36.442573 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3937 10:01:36.445770 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3938 10:01:36.449362 ===================================
3939 10:01:36.452740 LPDDR4 DRAM CONFIGURATION
3940 10:01:36.456566 ===================================
3941 10:01:36.456645 EX_ROW_EN[0] = 0x10
3942 10:01:36.459225 EX_ROW_EN[1] = 0x0
3943 10:01:36.459306 LP4Y_EN = 0x0
3944 10:01:36.462800 WORK_FSP = 0x0
3945 10:01:36.462915 WL = 0x2
3946 10:01:36.465901 RL = 0x2
3947 10:01:36.466013 BL = 0x2
3948 10:01:36.469107 RPST = 0x0
3949 10:01:36.469206 RD_PRE = 0x0
3950 10:01:36.472539 WR_PRE = 0x1
3951 10:01:36.472646 WR_PST = 0x0
3952 10:01:36.475943 DBI_WR = 0x0
3953 10:01:36.479367 DBI_RD = 0x0
3954 10:01:36.479480 OTF = 0x1
3955 10:01:36.482315 ===================================
3956 10:01:36.489050 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3957 10:01:36.492678 nWR fixed to 30
3958 10:01:36.496172 [ModeRegInit_LP4] CH0 RK0
3959 10:01:36.496244 [ModeRegInit_LP4] CH0 RK1
3960 10:01:36.499353 [ModeRegInit_LP4] CH1 RK0
3961 10:01:36.502684 [ModeRegInit_LP4] CH1 RK1
3962 10:01:36.502754 match AC timing 17
3963 10:01:36.509235 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3964 10:01:36.512905 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3965 10:01:36.516361 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3966 10:01:36.522281 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3967 10:01:36.525859 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3968 10:01:36.525967 ==
3969 10:01:36.529132 Dram Type= 6, Freq= 0, CH_0, rank 0
3970 10:01:36.532812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3971 10:01:36.532882 ==
3972 10:01:36.539668 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3973 10:01:36.546010 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3974 10:01:36.549185 [CA 0] Center 36 (6~67) winsize 62
3975 10:01:36.552934 [CA 1] Center 36 (6~67) winsize 62
3976 10:01:36.555875 [CA 2] Center 34 (4~65) winsize 62
3977 10:01:36.559522 [CA 3] Center 34 (4~65) winsize 62
3978 10:01:36.562620 [CA 4] Center 33 (3~64) winsize 62
3979 10:01:36.565877 [CA 5] Center 33 (2~64) winsize 63
3980 10:01:36.565945
3981 10:01:36.568995 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3982 10:01:36.569061
3983 10:01:36.572496 [CATrainingPosCal] consider 1 rank data
3984 10:01:36.575631 u2DelayCellTimex100 = 270/100 ps
3985 10:01:36.579071 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3986 10:01:36.582274 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3987 10:01:36.585944 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3988 10:01:36.589019 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3989 10:01:36.592262 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3990 10:01:36.595761 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3991 10:01:36.599282
3992 10:01:36.602565 CA PerBit enable=1, Macro0, CA PI delay=33
3993 10:01:36.602673
3994 10:01:36.605482 [CBTSetCACLKResult] CA Dly = 33
3995 10:01:36.605583 CS Dly: 4 (0~35)
3996 10:01:36.605681 ==
3997 10:01:36.608891 Dram Type= 6, Freq= 0, CH_0, rank 1
3998 10:01:36.612309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3999 10:01:36.612419 ==
4000 10:01:36.618824 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4001 10:01:36.625405 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4002 10:01:36.628847 [CA 0] Center 36 (6~67) winsize 62
4003 10:01:36.632367 [CA 1] Center 36 (6~67) winsize 62
4004 10:01:36.635998 [CA 2] Center 34 (4~65) winsize 62
4005 10:01:36.638883 [CA 3] Center 34 (4~65) winsize 62
4006 10:01:36.642486 [CA 4] Center 34 (3~65) winsize 63
4007 10:01:36.645374 [CA 5] Center 33 (3~64) winsize 62
4008 10:01:36.645480
4009 10:01:36.649025 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4010 10:01:36.649128
4011 10:01:36.652240 [CATrainingPosCal] consider 2 rank data
4012 10:01:36.655383 u2DelayCellTimex100 = 270/100 ps
4013 10:01:36.658799 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4014 10:01:36.662246 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4015 10:01:36.665414 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4016 10:01:36.668760 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4017 10:01:36.675408 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4018 10:01:36.678831 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4019 10:01:36.678941
4020 10:01:36.682216 CA PerBit enable=1, Macro0, CA PI delay=33
4021 10:01:36.682323
4022 10:01:36.685806 [CBTSetCACLKResult] CA Dly = 33
4023 10:01:36.685942 CS Dly: 5 (0~37)
4024 10:01:36.686069
4025 10:01:36.688691 ----->DramcWriteLeveling(PI) begin...
4026 10:01:36.688809 ==
4027 10:01:36.692190 Dram Type= 6, Freq= 0, CH_0, rank 0
4028 10:01:36.698548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4029 10:01:36.698657 ==
4030 10:01:36.701791 Write leveling (Byte 0): 32 => 32
4031 10:01:36.701899 Write leveling (Byte 1): 32 => 32
4032 10:01:36.705402 DramcWriteLeveling(PI) end<-----
4033 10:01:36.705511
4034 10:01:36.708476 ==
4035 10:01:36.708606 Dram Type= 6, Freq= 0, CH_0, rank 0
4036 10:01:36.715352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4037 10:01:36.715464 ==
4038 10:01:36.718675 [Gating] SW mode calibration
4039 10:01:36.724896 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4040 10:01:36.728194 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4041 10:01:36.734999 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4042 10:01:36.738329 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4043 10:01:36.741637 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4044 10:01:36.748424 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (1 1)
4045 10:01:36.751604 0 9 16 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
4046 10:01:36.754815 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 10:01:36.761975 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4048 10:01:36.765099 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4049 10:01:36.768387 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4050 10:01:36.774897 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4051 10:01:36.778608 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4052 10:01:36.781697 0 10 12 | B1->B0 | 2424 3d3d | 0 1 | (0 0) (0 0)
4053 10:01:36.785234 0 10 16 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
4054 10:01:36.791545 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 10:01:36.795289 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 10:01:36.798325 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 10:01:36.805164 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 10:01:36.808412 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 10:01:36.811743 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4060 10:01:36.818269 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4061 10:01:36.821579 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4062 10:01:36.824963 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 10:01:36.831645 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 10:01:36.834868 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 10:01:36.838054 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 10:01:36.844900 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 10:01:36.848109 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 10:01:36.851486 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 10:01:36.858043 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 10:01:36.861951 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 10:01:36.865129 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 10:01:36.871484 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 10:01:36.874781 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 10:01:36.878289 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 10:01:36.884994 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 10:01:36.887775 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4077 10:01:36.891466 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4078 10:01:36.894435 Total UI for P1: 0, mck2ui 16
4079 10:01:36.897876 best dqsien dly found for B0: ( 0, 13, 12)
4080 10:01:36.901172 Total UI for P1: 0, mck2ui 16
4081 10:01:36.904604 best dqsien dly found for B1: ( 0, 13, 14)
4082 10:01:36.908044 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4083 10:01:36.911054 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4084 10:01:36.911140
4085 10:01:36.914375 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4086 10:01:36.921122 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4087 10:01:36.921208 [Gating] SW calibration Done
4088 10:01:36.921278 ==
4089 10:01:36.924833 Dram Type= 6, Freq= 0, CH_0, rank 0
4090 10:01:36.931819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4091 10:01:36.931904 ==
4092 10:01:36.931972 RX Vref Scan: 0
4093 10:01:36.932034
4094 10:01:36.934671 RX Vref 0 -> 0, step: 1
4095 10:01:36.934755
4096 10:01:36.938114 RX Delay -230 -> 252, step: 16
4097 10:01:36.941375 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4098 10:01:36.944850 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4099 10:01:36.951568 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4100 10:01:36.954661 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4101 10:01:36.957855 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4102 10:01:36.961183 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4103 10:01:36.964471 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4104 10:01:36.971030 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4105 10:01:36.974309 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4106 10:01:36.977932 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4107 10:01:36.980953 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4108 10:01:36.987806 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4109 10:01:36.990954 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4110 10:01:36.994279 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4111 10:01:36.997543 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4112 10:01:37.004250 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4113 10:01:37.004335 ==
4114 10:01:37.007437 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 10:01:37.011018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 10:01:37.011102 ==
4117 10:01:37.011170 DQS Delay:
4118 10:01:37.014165 DQS0 = 0, DQS1 = 0
4119 10:01:37.014250 DQM Delay:
4120 10:01:37.017594 DQM0 = 50, DQM1 = 39
4121 10:01:37.017678 DQ Delay:
4122 10:01:37.020773 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =49
4123 10:01:37.024015 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4124 10:01:37.027498 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4125 10:01:37.030893 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =49
4126 10:01:37.030977
4127 10:01:37.031044
4128 10:01:37.031106 ==
4129 10:01:37.033937 Dram Type= 6, Freq= 0, CH_0, rank 0
4130 10:01:37.037180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4131 10:01:37.037285 ==
4132 10:01:37.037367
4133 10:01:37.041067
4134 10:01:37.041167 TX Vref Scan disable
4135 10:01:37.044218 == TX Byte 0 ==
4136 10:01:37.047478 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4137 10:01:37.050867 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4138 10:01:37.053972 == TX Byte 1 ==
4139 10:01:37.057045 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4140 10:01:37.060622 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4141 10:01:37.060730 ==
4142 10:01:37.063828 Dram Type= 6, Freq= 0, CH_0, rank 0
4143 10:01:37.070514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4144 10:01:37.070621 ==
4145 10:01:37.070724
4146 10:01:37.070825
4147 10:01:37.070923 TX Vref Scan disable
4148 10:01:37.074851 == TX Byte 0 ==
4149 10:01:37.078311 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4150 10:01:37.081902 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4151 10:01:37.084985 == TX Byte 1 ==
4152 10:01:37.087973 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4153 10:01:37.094862 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4154 10:01:37.094943
4155 10:01:37.095031 [DATLAT]
4156 10:01:37.095130 Freq=600, CH0 RK0
4157 10:01:37.095232
4158 10:01:37.098330 DATLAT Default: 0x9
4159 10:01:37.098460 0, 0xFFFF, sum = 0
4160 10:01:37.101566 1, 0xFFFF, sum = 0
4161 10:01:37.101645 2, 0xFFFF, sum = 0
4162 10:01:37.104674 3, 0xFFFF, sum = 0
4163 10:01:37.104776 4, 0xFFFF, sum = 0
4164 10:01:37.108092 5, 0xFFFF, sum = 0
4165 10:01:37.111671 6, 0xFFFF, sum = 0
4166 10:01:37.111774 7, 0xFFFF, sum = 0
4167 10:01:37.111854 8, 0x0, sum = 1
4168 10:01:37.114670 9, 0x0, sum = 2
4169 10:01:37.114745 10, 0x0, sum = 3
4170 10:01:37.118155 11, 0x0, sum = 4
4171 10:01:37.118257 best_step = 9
4172 10:01:37.118357
4173 10:01:37.118463 ==
4174 10:01:37.121567 Dram Type= 6, Freq= 0, CH_0, rank 0
4175 10:01:37.128293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4176 10:01:37.128370 ==
4177 10:01:37.128457 RX Vref Scan: 1
4178 10:01:37.128533
4179 10:01:37.131421 RX Vref 0 -> 0, step: 1
4180 10:01:37.131497
4181 10:01:37.134578 RX Delay -179 -> 252, step: 8
4182 10:01:37.134677
4183 10:01:37.138456 Set Vref, RX VrefLevel [Byte0]: 58
4184 10:01:37.141826 [Byte1]: 50
4185 10:01:37.141926
4186 10:01:37.144624 Final RX Vref Byte 0 = 58 to rank0
4187 10:01:37.148386 Final RX Vref Byte 1 = 50 to rank0
4188 10:01:37.151194 Final RX Vref Byte 0 = 58 to rank1
4189 10:01:37.155059 Final RX Vref Byte 1 = 50 to rank1==
4190 10:01:37.158261 Dram Type= 6, Freq= 0, CH_0, rank 0
4191 10:01:37.161215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4192 10:01:37.161317 ==
4193 10:01:37.164853 DQS Delay:
4194 10:01:37.164956 DQS0 = 0, DQS1 = 0
4195 10:01:37.165056 DQM Delay:
4196 10:01:37.168083 DQM0 = 50, DQM1 = 37
4197 10:01:37.168183 DQ Delay:
4198 10:01:37.171256 DQ0 =48, DQ1 =52, DQ2 =44, DQ3 =48
4199 10:01:37.174572 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4200 10:01:37.178073 DQ8 =32, DQ9 =24, DQ10 =36, DQ11 =32
4201 10:01:37.181705 DQ12 =40, DQ13 =40, DQ14 =48, DQ15 =44
4202 10:01:37.181810
4203 10:01:37.181891
4204 10:01:37.191566 [DQSOSCAuto] RK0, (LSB)MR18= 0x5a54, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4205 10:01:37.194676 CH0 RK0: MR19=808, MR18=5A54
4206 10:01:37.197863 CH0_RK0: MR19=0x808, MR18=0x5A54, DQSOSC=392, MR23=63, INC=170, DEC=113
4207 10:01:37.197967
4208 10:01:37.201290 ----->DramcWriteLeveling(PI) begin...
4209 10:01:37.204897 ==
4210 10:01:37.207985 Dram Type= 6, Freq= 0, CH_0, rank 1
4211 10:01:37.211605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4212 10:01:37.211681 ==
4213 10:01:37.214840 Write leveling (Byte 0): 33 => 33
4214 10:01:37.218074 Write leveling (Byte 1): 33 => 33
4215 10:01:37.221241 DramcWriteLeveling(PI) end<-----
4216 10:01:37.221342
4217 10:01:37.221441 ==
4218 10:01:37.224720 Dram Type= 6, Freq= 0, CH_0, rank 1
4219 10:01:37.228322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4220 10:01:37.228421 ==
4221 10:01:37.231156 [Gating] SW mode calibration
4222 10:01:37.238185 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4223 10:01:37.241211 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4224 10:01:37.247931 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4225 10:01:37.251166 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4226 10:01:37.254948 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4227 10:01:37.261449 0 9 12 | B1->B0 | 3131 3232 | 0 0 | (0 0) (0 0)
4228 10:01:37.264654 0 9 16 | B1->B0 | 2b2b 2424 | 0 0 | (0 0) (0 0)
4229 10:01:37.267807 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 10:01:37.274252 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4231 10:01:37.278075 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4232 10:01:37.281090 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4233 10:01:37.287897 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 10:01:37.291455 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 10:01:37.294575 0 10 12 | B1->B0 | 2a2a 3131 | 0 1 | (0 0) (0 0)
4236 10:01:37.301175 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 10:01:37.304349 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 10:01:37.307704 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 10:01:37.314340 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 10:01:37.317985 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 10:01:37.320976 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 10:01:37.327595 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 10:01:37.330754 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4244 10:01:37.334318 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 10:01:37.340867 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 10:01:37.344417 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 10:01:37.347826 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 10:01:37.354405 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 10:01:37.357326 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 10:01:37.360572 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 10:01:37.367441 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 10:01:37.370757 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 10:01:37.374261 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 10:01:37.377653 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 10:01:37.384172 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 10:01:37.387533 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 10:01:37.390522 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 10:01:37.397365 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 10:01:37.400665 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4260 10:01:37.404253 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4261 10:01:37.407264 Total UI for P1: 0, mck2ui 16
4262 10:01:37.410662 best dqsien dly found for B0: ( 0, 13, 12)
4263 10:01:37.414083 Total UI for P1: 0, mck2ui 16
4264 10:01:37.417279 best dqsien dly found for B1: ( 0, 13, 12)
4265 10:01:37.420744 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4266 10:01:37.424139 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4267 10:01:37.427280
4268 10:01:37.430705 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4269 10:01:37.433896 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4270 10:01:37.437268 [Gating] SW calibration Done
4271 10:01:37.437351 ==
4272 10:01:37.440388 Dram Type= 6, Freq= 0, CH_0, rank 1
4273 10:01:37.444275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4274 10:01:37.444360 ==
4275 10:01:37.444427 RX Vref Scan: 0
4276 10:01:37.447182
4277 10:01:37.447266 RX Vref 0 -> 0, step: 1
4278 10:01:37.447332
4279 10:01:37.450319 RX Delay -230 -> 252, step: 16
4280 10:01:37.453837 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4281 10:01:37.460716 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4282 10:01:37.464128 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4283 10:01:37.467198 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4284 10:01:37.470740 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4285 10:01:37.473797 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4286 10:01:37.480345 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4287 10:01:37.484023 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4288 10:01:37.486798 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4289 10:01:37.490300 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4290 10:01:37.496889 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4291 10:01:37.500203 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4292 10:01:37.503608 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4293 10:01:37.506806 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4294 10:01:37.513874 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4295 10:01:37.517123 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4296 10:01:37.517207 ==
4297 10:01:37.520138 Dram Type= 6, Freq= 0, CH_0, rank 1
4298 10:01:37.523372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4299 10:01:37.523456 ==
4300 10:01:37.526957 DQS Delay:
4301 10:01:37.527039 DQS0 = 0, DQS1 = 0
4302 10:01:37.527105 DQM Delay:
4303 10:01:37.530134 DQM0 = 50, DQM1 = 42
4304 10:01:37.530217 DQ Delay:
4305 10:01:37.533677 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4306 10:01:37.536788 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4307 10:01:37.539848 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4308 10:01:37.543195 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4309 10:01:37.543279
4310 10:01:37.543344
4311 10:01:37.543405 ==
4312 10:01:37.546711 Dram Type= 6, Freq= 0, CH_0, rank 1
4313 10:01:37.550011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4314 10:01:37.553376 ==
4315 10:01:37.553459
4316 10:01:37.553526
4317 10:01:37.553588 TX Vref Scan disable
4318 10:01:37.556660 == TX Byte 0 ==
4319 10:01:37.560186 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4320 10:01:37.566641 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4321 10:01:37.566725 == TX Byte 1 ==
4322 10:01:37.569932 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4323 10:01:37.577183 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4324 10:01:37.577268 ==
4325 10:01:37.579942 Dram Type= 6, Freq= 0, CH_0, rank 1
4326 10:01:37.583207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4327 10:01:37.583292 ==
4328 10:01:37.583358
4329 10:01:37.583419
4330 10:01:37.586686 TX Vref Scan disable
4331 10:01:37.586769 == TX Byte 0 ==
4332 10:01:37.593300 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4333 10:01:37.596491 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4334 10:01:37.599867 == TX Byte 1 ==
4335 10:01:37.603203 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4336 10:01:37.606510 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4337 10:01:37.606595
4338 10:01:37.606662 [DATLAT]
4339 10:01:37.609684 Freq=600, CH0 RK1
4340 10:01:37.609767
4341 10:01:37.609834 DATLAT Default: 0x9
4342 10:01:37.613193 0, 0xFFFF, sum = 0
4343 10:01:37.616452 1, 0xFFFF, sum = 0
4344 10:01:37.616537 2, 0xFFFF, sum = 0
4345 10:01:37.619851 3, 0xFFFF, sum = 0
4346 10:01:37.619937 4, 0xFFFF, sum = 0
4347 10:01:37.623102 5, 0xFFFF, sum = 0
4348 10:01:37.623187 6, 0xFFFF, sum = 0
4349 10:01:37.626420 7, 0xFFFF, sum = 0
4350 10:01:37.626505 8, 0x0, sum = 1
4351 10:01:37.626572 9, 0x0, sum = 2
4352 10:01:37.629732 10, 0x0, sum = 3
4353 10:01:37.629817 11, 0x0, sum = 4
4354 10:01:37.633232 best_step = 9
4355 10:01:37.633316
4356 10:01:37.633382 ==
4357 10:01:37.636545 Dram Type= 6, Freq= 0, CH_0, rank 1
4358 10:01:37.639923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4359 10:01:37.640008 ==
4360 10:01:37.642881 RX Vref Scan: 0
4361 10:01:37.642962
4362 10:01:37.643027 RX Vref 0 -> 0, step: 1
4363 10:01:37.643087
4364 10:01:37.646193 RX Delay -179 -> 252, step: 8
4365 10:01:37.653559 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4366 10:01:37.656842 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4367 10:01:37.660080 iDelay=205, Bit 2, Center 48 (-99 ~ 196) 296
4368 10:01:37.663519 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4369 10:01:37.666878 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4370 10:01:37.673608 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4371 10:01:37.676997 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4372 10:01:37.680080 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4373 10:01:37.683663 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4374 10:01:37.690246 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4375 10:01:37.693653 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4376 10:01:37.696906 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4377 10:01:37.700441 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4378 10:01:37.703380 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4379 10:01:37.709892 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4380 10:01:37.713154 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4381 10:01:37.713236 ==
4382 10:01:37.716505 Dram Type= 6, Freq= 0, CH_0, rank 1
4383 10:01:37.720162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4384 10:01:37.720245 ==
4385 10:01:37.723006 DQS Delay:
4386 10:01:37.723089 DQS0 = 0, DQS1 = 0
4387 10:01:37.723154 DQM Delay:
4388 10:01:37.726609 DQM0 = 48, DQM1 = 41
4389 10:01:37.726690 DQ Delay:
4390 10:01:37.729906 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =44
4391 10:01:37.733105 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4392 10:01:37.736866 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =36
4393 10:01:37.740021 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =52
4394 10:01:37.740102
4395 10:01:37.740166
4396 10:01:37.749987 [DQSOSCAuto] RK1, (LSB)MR18= 0x6633, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
4397 10:01:37.753631 CH0 RK1: MR19=808, MR18=6633
4398 10:01:37.756705 CH0_RK1: MR19=0x808, MR18=0x6633, DQSOSC=390, MR23=63, INC=172, DEC=114
4399 10:01:37.760283 [RxdqsGatingPostProcess] freq 600
4400 10:01:37.766360 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4401 10:01:37.769880 Pre-setting of DQS Precalculation
4402 10:01:37.773336 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4403 10:01:37.773418 ==
4404 10:01:37.776572 Dram Type= 6, Freq= 0, CH_1, rank 0
4405 10:01:37.782982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4406 10:01:37.783064 ==
4407 10:01:37.786168 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4408 10:01:37.793121 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4409 10:01:37.796623 [CA 0] Center 35 (5~66) winsize 62
4410 10:01:37.799725 [CA 1] Center 35 (5~66) winsize 62
4411 10:01:37.802757 [CA 2] Center 34 (4~65) winsize 62
4412 10:01:37.806306 [CA 3] Center 33 (3~64) winsize 62
4413 10:01:37.809498 [CA 4] Center 34 (3~65) winsize 63
4414 10:01:37.812845 [CA 5] Center 33 (3~64) winsize 62
4415 10:01:37.812927
4416 10:01:37.816467 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4417 10:01:37.816548
4418 10:01:37.819814 [CATrainingPosCal] consider 1 rank data
4419 10:01:37.822777 u2DelayCellTimex100 = 270/100 ps
4420 10:01:37.825982 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4421 10:01:37.829662 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4422 10:01:37.836171 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4423 10:01:37.839849 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4424 10:01:37.843175 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4425 10:01:37.846035 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4426 10:01:37.846117
4427 10:01:37.849293 CA PerBit enable=1, Macro0, CA PI delay=33
4428 10:01:37.849377
4429 10:01:37.852743 [CBTSetCACLKResult] CA Dly = 33
4430 10:01:37.852812 CS Dly: 5 (0~36)
4431 10:01:37.855784 ==
4432 10:01:37.859562 Dram Type= 6, Freq= 0, CH_1, rank 1
4433 10:01:37.862423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4434 10:01:37.862502 ==
4435 10:01:37.865966 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4436 10:01:37.872418 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4437 10:01:37.876339 [CA 0] Center 35 (5~66) winsize 62
4438 10:01:37.879696 [CA 1] Center 35 (5~66) winsize 62
4439 10:01:37.883292 [CA 2] Center 34 (4~65) winsize 62
4440 10:01:37.886094 [CA 3] Center 34 (4~65) winsize 62
4441 10:01:37.890173 [CA 4] Center 34 (4~65) winsize 62
4442 10:01:37.893125 [CA 5] Center 34 (3~65) winsize 63
4443 10:01:37.893210
4444 10:01:37.896238 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4445 10:01:37.896317
4446 10:01:37.899445 [CATrainingPosCal] consider 2 rank data
4447 10:01:37.902735 u2DelayCellTimex100 = 270/100 ps
4448 10:01:37.906129 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4449 10:01:37.912643 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4450 10:01:37.916380 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4451 10:01:37.919600 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4452 10:01:37.922972 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4453 10:01:37.926095 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4454 10:01:37.926226
4455 10:01:37.929490 CA PerBit enable=1, Macro0, CA PI delay=33
4456 10:01:37.929574
4457 10:01:37.932736 [CBTSetCACLKResult] CA Dly = 33
4458 10:01:37.932819 CS Dly: 5 (0~37)
4459 10:01:37.936397
4460 10:01:37.939207 ----->DramcWriteLeveling(PI) begin...
4461 10:01:37.939295 ==
4462 10:01:37.942711 Dram Type= 6, Freq= 0, CH_1, rank 0
4463 10:01:37.945893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4464 10:01:37.945986 ==
4465 10:01:37.949483 Write leveling (Byte 0): 29 => 29
4466 10:01:37.952590 Write leveling (Byte 1): 30 => 30
4467 10:01:37.955938 DramcWriteLeveling(PI) end<-----
4468 10:01:37.956025
4469 10:01:37.956092 ==
4470 10:01:37.959267 Dram Type= 6, Freq= 0, CH_1, rank 0
4471 10:01:37.962948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4472 10:01:37.963033 ==
4473 10:01:37.966050 [Gating] SW mode calibration
4474 10:01:37.972880 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4475 10:01:37.979586 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4476 10:01:37.982674 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4477 10:01:37.985887 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4478 10:01:37.992479 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4479 10:01:37.995645 0 9 12 | B1->B0 | 2e2e 2f2f | 0 0 | (0 0) (1 1)
4480 10:01:37.999226 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 10:01:38.005528 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 10:01:38.008962 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4483 10:01:38.012434 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4484 10:01:38.019291 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4485 10:01:38.022290 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4486 10:01:38.026115 0 10 8 | B1->B0 | 2525 2f2f | 0 0 | (0 0) (0 0)
4487 10:01:38.029126 0 10 12 | B1->B0 | 3a3a 4141 | 0 0 | (1 1) (0 0)
4488 10:01:38.035628 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 10:01:38.039103 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 10:01:38.042340 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 10:01:38.048887 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4492 10:01:38.052221 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 10:01:38.055722 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 10:01:38.062106 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 10:01:38.065200 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4496 10:01:38.068594 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4497 10:01:38.075355 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 10:01:38.078719 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 10:01:38.081980 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 10:01:38.089283 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 10:01:38.092517 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 10:01:38.095611 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 10:01:38.102197 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 10:01:38.105612 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 10:01:38.108847 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 10:01:38.115420 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 10:01:38.118847 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 10:01:38.122238 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 10:01:38.128993 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 10:01:38.132471 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 10:01:38.135558 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4512 10:01:38.138660 Total UI for P1: 0, mck2ui 16
4513 10:01:38.142084 best dqsien dly found for B0: ( 0, 13, 10)
4514 10:01:38.145578 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4515 10:01:38.148633 Total UI for P1: 0, mck2ui 16
4516 10:01:38.152321 best dqsien dly found for B1: ( 0, 13, 12)
4517 10:01:38.155702 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4518 10:01:38.162073 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4519 10:01:38.162156
4520 10:01:38.165624 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4521 10:01:38.168874 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4522 10:01:38.171927 [Gating] SW calibration Done
4523 10:01:38.172011 ==
4524 10:01:38.175177 Dram Type= 6, Freq= 0, CH_1, rank 0
4525 10:01:38.179210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4526 10:01:38.179320 ==
4527 10:01:38.181759 RX Vref Scan: 0
4528 10:01:38.181841
4529 10:01:38.181907 RX Vref 0 -> 0, step: 1
4530 10:01:38.181969
4531 10:01:38.185580 RX Delay -230 -> 252, step: 16
4532 10:01:38.188451 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4533 10:01:38.195223 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4534 10:01:38.198567 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4535 10:01:38.202520 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4536 10:01:38.205156 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4537 10:01:38.208710 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4538 10:01:38.215439 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4539 10:01:38.218575 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4540 10:01:38.221971 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4541 10:01:38.225299 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4542 10:01:38.228601 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4543 10:01:38.235332 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4544 10:01:38.238755 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4545 10:01:38.242039 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4546 10:01:38.245604 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4547 10:01:38.252031 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4548 10:01:38.252115 ==
4549 10:01:38.255263 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 10:01:38.258871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 10:01:38.258955 ==
4552 10:01:38.259022 DQS Delay:
4553 10:01:38.261730 DQS0 = 0, DQS1 = 0
4554 10:01:38.261813 DQM Delay:
4555 10:01:38.265093 DQM0 = 54, DQM1 = 46
4556 10:01:38.265177 DQ Delay:
4557 10:01:38.268505 DQ0 =57, DQ1 =49, DQ2 =49, DQ3 =49
4558 10:01:38.271818 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4559 10:01:38.275111 DQ8 =25, DQ9 =33, DQ10 =49, DQ11 =41
4560 10:01:38.278557 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4561 10:01:38.278640
4562 10:01:38.278706
4563 10:01:38.278767 ==
4564 10:01:38.281815 Dram Type= 6, Freq= 0, CH_1, rank 0
4565 10:01:38.285246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4566 10:01:38.288873 ==
4567 10:01:38.288956
4568 10:01:38.289021
4569 10:01:38.289082 TX Vref Scan disable
4570 10:01:38.291649 == TX Byte 0 ==
4571 10:01:38.295210 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4572 10:01:38.298427 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4573 10:01:38.301469 == TX Byte 1 ==
4574 10:01:38.304765 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4575 10:01:38.308515 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4576 10:01:38.311674 ==
4577 10:01:38.315408 Dram Type= 6, Freq= 0, CH_1, rank 0
4578 10:01:38.318402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4579 10:01:38.318524 ==
4580 10:01:38.318619
4581 10:01:38.318710
4582 10:01:38.321462 TX Vref Scan disable
4583 10:01:38.321545 == TX Byte 0 ==
4584 10:01:38.328092 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4585 10:01:38.331278 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4586 10:01:38.331362 == TX Byte 1 ==
4587 10:01:38.338474 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4588 10:01:38.341320 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4589 10:01:38.341403
4590 10:01:38.341470 [DATLAT]
4591 10:01:38.344966 Freq=600, CH1 RK0
4592 10:01:38.345050
4593 10:01:38.345117 DATLAT Default: 0x9
4594 10:01:38.348118 0, 0xFFFF, sum = 0
4595 10:01:38.348202 1, 0xFFFF, sum = 0
4596 10:01:38.351031 2, 0xFFFF, sum = 0
4597 10:01:38.354731 3, 0xFFFF, sum = 0
4598 10:01:38.354816 4, 0xFFFF, sum = 0
4599 10:01:38.357806 5, 0xFFFF, sum = 0
4600 10:01:38.357891 6, 0xFFFF, sum = 0
4601 10:01:38.361317 7, 0xFFFF, sum = 0
4602 10:01:38.361401 8, 0x0, sum = 1
4603 10:01:38.361468 9, 0x0, sum = 2
4604 10:01:38.364316 10, 0x0, sum = 3
4605 10:01:38.364400 11, 0x0, sum = 4
4606 10:01:38.367745 best_step = 9
4607 10:01:38.367829
4608 10:01:38.367895 ==
4609 10:01:38.371448 Dram Type= 6, Freq= 0, CH_1, rank 0
4610 10:01:38.374868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4611 10:01:38.374951 ==
4612 10:01:38.377489 RX Vref Scan: 1
4613 10:01:38.377572
4614 10:01:38.377638 RX Vref 0 -> 0, step: 1
4615 10:01:38.377700
4616 10:01:38.380862 RX Delay -179 -> 252, step: 8
4617 10:01:38.380945
4618 10:01:38.384410 Set Vref, RX VrefLevel [Byte0]: 54
4619 10:01:38.387477 [Byte1]: 58
4620 10:01:38.391865
4621 10:01:38.391949 Final RX Vref Byte 0 = 54 to rank0
4622 10:01:38.394826 Final RX Vref Byte 1 = 58 to rank0
4623 10:01:38.398380 Final RX Vref Byte 0 = 54 to rank1
4624 10:01:38.401956 Final RX Vref Byte 1 = 58 to rank1==
4625 10:01:38.405142 Dram Type= 6, Freq= 0, CH_1, rank 0
4626 10:01:38.411871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4627 10:01:38.411955 ==
4628 10:01:38.412021 DQS Delay:
4629 10:01:38.412082 DQS0 = 0, DQS1 = 0
4630 10:01:38.414912 DQM Delay:
4631 10:01:38.414995 DQM0 = 48, DQM1 = 41
4632 10:01:38.418400 DQ Delay:
4633 10:01:38.421391 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4634 10:01:38.425258 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =44
4635 10:01:38.428538 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4636 10:01:38.431603 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4637 10:01:38.431686
4638 10:01:38.431752
4639 10:01:38.438070 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e74, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4640 10:01:38.441620 CH1 RK0: MR19=808, MR18=4E74
4641 10:01:38.447952 CH1_RK0: MR19=0x808, MR18=0x4E74, DQSOSC=388, MR23=63, INC=174, DEC=116
4642 10:01:38.448035
4643 10:01:38.451306 ----->DramcWriteLeveling(PI) begin...
4644 10:01:38.451391 ==
4645 10:01:38.454687 Dram Type= 6, Freq= 0, CH_1, rank 1
4646 10:01:38.457855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4647 10:01:38.457939 ==
4648 10:01:38.461270 Write leveling (Byte 0): 31 => 31
4649 10:01:38.464688 Write leveling (Byte 1): 31 => 31
4650 10:01:38.468235 DramcWriteLeveling(PI) end<-----
4651 10:01:38.468317
4652 10:01:38.468383 ==
4653 10:01:38.471047 Dram Type= 6, Freq= 0, CH_1, rank 1
4654 10:01:38.474688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4655 10:01:38.474772 ==
4656 10:01:38.477750 [Gating] SW mode calibration
4657 10:01:38.484686 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4658 10:01:38.491109 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4659 10:01:38.494655 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4660 10:01:38.501024 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4661 10:01:38.504399 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4662 10:01:38.507763 0 9 12 | B1->B0 | 2b2b 3131 | 1 1 | (1 1) (1 0)
4663 10:01:38.514322 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4664 10:01:38.517990 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4665 10:01:38.521397 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4666 10:01:38.524293 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4667 10:01:38.530895 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4668 10:01:38.534753 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4669 10:01:38.537649 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4670 10:01:38.544512 0 10 12 | B1->B0 | 3f3f 2d2d | 0 0 | (1 1) (0 0)
4671 10:01:38.547798 0 10 16 | B1->B0 | 4646 4343 | 0 0 | (0 0) (1 1)
4672 10:01:38.550872 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 10:01:38.557672 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 10:01:38.561006 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4675 10:01:38.564710 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4676 10:01:38.571245 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4677 10:01:38.574223 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4678 10:01:38.577809 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4679 10:01:38.584203 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 10:01:38.587669 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 10:01:38.590747 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 10:01:38.597504 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 10:01:38.601216 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 10:01:38.604669 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 10:01:38.610630 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 10:01:38.614325 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 10:01:38.617188 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 10:01:38.624033 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 10:01:38.627582 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 10:01:38.630596 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 10:01:38.637252 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 10:01:38.640815 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 10:01:38.644071 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4694 10:01:38.650295 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4695 10:01:38.650367 Total UI for P1: 0, mck2ui 16
4696 10:01:38.654137 best dqsien dly found for B0: ( 0, 13, 8)
4697 10:01:38.660557 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4698 10:01:38.663693 Total UI for P1: 0, mck2ui 16
4699 10:01:38.667607 best dqsien dly found for B1: ( 0, 13, 12)
4700 10:01:38.670507 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4701 10:01:38.673946 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4702 10:01:38.674026
4703 10:01:38.677117 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4704 10:01:38.680499 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4705 10:01:38.683760 [Gating] SW calibration Done
4706 10:01:38.683835 ==
4707 10:01:38.687010 Dram Type= 6, Freq= 0, CH_1, rank 1
4708 10:01:38.690625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4709 10:01:38.690737 ==
4710 10:01:38.693890 RX Vref Scan: 0
4711 10:01:38.693967
4712 10:01:38.697166 RX Vref 0 -> 0, step: 1
4713 10:01:38.697249
4714 10:01:38.697317 RX Delay -230 -> 252, step: 16
4715 10:01:38.704049 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4716 10:01:38.707518 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4717 10:01:38.710370 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4718 10:01:38.713855 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4719 10:01:38.720516 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4720 10:01:38.723978 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4721 10:01:38.727589 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4722 10:01:38.730311 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4723 10:01:38.733982 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4724 10:01:38.740658 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4725 10:01:38.743635 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4726 10:01:38.747061 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4727 10:01:38.750330 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4728 10:01:38.757110 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4729 10:01:38.760541 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4730 10:01:38.763370 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4731 10:01:38.763453 ==
4732 10:01:38.767158 Dram Type= 6, Freq= 0, CH_1, rank 1
4733 10:01:38.770262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4734 10:01:38.770375 ==
4735 10:01:38.773943 DQS Delay:
4736 10:01:38.774025 DQS0 = 0, DQS1 = 0
4737 10:01:38.776673 DQM Delay:
4738 10:01:38.776756 DQM0 = 52, DQM1 = 47
4739 10:01:38.776822 DQ Delay:
4740 10:01:38.780216 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4741 10:01:38.783635 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4742 10:01:38.786642 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4743 10:01:38.790076 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4744 10:01:38.790211
4745 10:01:38.790328
4746 10:01:38.793410 ==
4747 10:01:38.797156 Dram Type= 6, Freq= 0, CH_1, rank 1
4748 10:01:38.799934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4749 10:01:38.800059 ==
4750 10:01:38.800157
4751 10:01:38.800249
4752 10:01:38.803858 TX Vref Scan disable
4753 10:01:38.804324 == TX Byte 0 ==
4754 10:01:38.810221 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4755 10:01:38.813530 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4756 10:01:38.813999 == TX Byte 1 ==
4757 10:01:38.819934 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4758 10:01:38.823391 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4759 10:01:38.823932 ==
4760 10:01:38.826779 Dram Type= 6, Freq= 0, CH_1, rank 1
4761 10:01:38.829902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4762 10:01:38.830378 ==
4763 10:01:38.830810
4764 10:01:38.831162
4765 10:01:38.833401 TX Vref Scan disable
4766 10:01:38.836448 == TX Byte 0 ==
4767 10:01:38.840016 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4768 10:01:38.842980 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4769 10:01:38.846228 == TX Byte 1 ==
4770 10:01:38.849535 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4771 10:01:38.852978 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4772 10:01:38.855784
4773 10:01:38.855867 [DATLAT]
4774 10:01:38.855934 Freq=600, CH1 RK1
4775 10:01:38.855997
4776 10:01:38.859510 DATLAT Default: 0x9
4777 10:01:38.859594 0, 0xFFFF, sum = 0
4778 10:01:38.863098 1, 0xFFFF, sum = 0
4779 10:01:38.863184 2, 0xFFFF, sum = 0
4780 10:01:38.866273 3, 0xFFFF, sum = 0
4781 10:01:38.866359 4, 0xFFFF, sum = 0
4782 10:01:38.869481 5, 0xFFFF, sum = 0
4783 10:01:38.869566 6, 0xFFFF, sum = 0
4784 10:01:38.872586 7, 0xFFFF, sum = 0
4785 10:01:38.872677 8, 0x0, sum = 1
4786 10:01:38.875700 9, 0x0, sum = 2
4787 10:01:38.875785 10, 0x0, sum = 3
4788 10:01:38.879032 11, 0x0, sum = 4
4789 10:01:38.879117 best_step = 9
4790 10:01:38.879183
4791 10:01:38.879244 ==
4792 10:01:38.882491 Dram Type= 6, Freq= 0, CH_1, rank 1
4793 10:01:38.889191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4794 10:01:38.889304 ==
4795 10:01:38.889436 RX Vref Scan: 0
4796 10:01:38.889528
4797 10:01:38.892487 RX Vref 0 -> 0, step: 1
4798 10:01:38.892572
4799 10:01:38.895848 RX Delay -163 -> 252, step: 8
4800 10:01:38.899364 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4801 10:01:38.905834 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4802 10:01:38.909085 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4803 10:01:38.912359 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4804 10:01:38.915654 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4805 10:01:38.918804 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4806 10:01:38.925512 iDelay=205, Bit 6, Center 52 (-91 ~ 196) 288
4807 10:01:38.928789 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4808 10:01:38.932270 iDelay=205, Bit 8, Center 28 (-115 ~ 172) 288
4809 10:01:38.935700 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4810 10:01:38.939442 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4811 10:01:38.945327 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4812 10:01:38.948850 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4813 10:01:38.952036 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4814 10:01:38.955514 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4815 10:01:38.962209 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4816 10:01:38.962317 ==
4817 10:01:38.965413 Dram Type= 6, Freq= 0, CH_1, rank 1
4818 10:01:38.968844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4819 10:01:38.968928 ==
4820 10:01:38.968994 DQS Delay:
4821 10:01:38.972374 DQS0 = 0, DQS1 = 0
4822 10:01:38.972457 DQM Delay:
4823 10:01:38.975483 DQM0 = 48, DQM1 = 43
4824 10:01:38.975566 DQ Delay:
4825 10:01:38.978895 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =44
4826 10:01:38.982335 DQ4 =48, DQ5 =60, DQ6 =52, DQ7 =48
4827 10:01:38.985629 DQ8 =28, DQ9 =32, DQ10 =40, DQ11 =40
4828 10:01:38.988762 DQ12 =56, DQ13 =48, DQ14 =48, DQ15 =56
4829 10:01:38.988851
4830 10:01:38.988922
4831 10:01:38.995642 [DQSOSCAuto] RK1, (LSB)MR18= 0x5a21, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
4832 10:01:38.998950 CH1 RK1: MR19=808, MR18=5A21
4833 10:01:39.005467 CH1_RK1: MR19=0x808, MR18=0x5A21, DQSOSC=392, MR23=63, INC=170, DEC=113
4834 10:01:39.008821 [RxdqsGatingPostProcess] freq 600
4835 10:01:39.015734 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4836 10:01:39.018997 Pre-setting of DQS Precalculation
4837 10:01:39.022059 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4838 10:01:39.028835 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4839 10:01:39.035393 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4840 10:01:39.035630
4841 10:01:39.035821
4842 10:01:39.039373 [Calibration Summary] 1200 Mbps
4843 10:01:39.042435 CH 0, Rank 0
4844 10:01:39.042713 SW Impedance : PASS
4845 10:01:39.045909 DUTY Scan : NO K
4846 10:01:39.048921 ZQ Calibration : PASS
4847 10:01:39.049371 Jitter Meter : NO K
4848 10:01:39.052293 CBT Training : PASS
4849 10:01:39.052817 Write leveling : PASS
4850 10:01:39.055505 RX DQS gating : PASS
4851 10:01:39.058905 RX DQ/DQS(RDDQC) : PASS
4852 10:01:39.059354 TX DQ/DQS : PASS
4853 10:01:39.062307 RX DATLAT : PASS
4854 10:01:39.065576 RX DQ/DQS(Engine): PASS
4855 10:01:39.066204 TX OE : NO K
4856 10:01:39.068813 All Pass.
4857 10:01:39.069424
4858 10:01:39.069904 CH 0, Rank 1
4859 10:01:39.072048 SW Impedance : PASS
4860 10:01:39.072748 DUTY Scan : NO K
4861 10:01:39.075660 ZQ Calibration : PASS
4862 10:01:39.078615 Jitter Meter : NO K
4863 10:01:39.079177 CBT Training : PASS
4864 10:01:39.082276 Write leveling : PASS
4865 10:01:39.085282 RX DQS gating : PASS
4866 10:01:39.085876 RX DQ/DQS(RDDQC) : PASS
4867 10:01:39.089294 TX DQ/DQS : PASS
4868 10:01:39.092050 RX DATLAT : PASS
4869 10:01:39.092687 RX DQ/DQS(Engine): PASS
4870 10:01:39.095550 TX OE : NO K
4871 10:01:39.096165 All Pass.
4872 10:01:39.096729
4873 10:01:39.098655 CH 1, Rank 0
4874 10:01:39.099139 SW Impedance : PASS
4875 10:01:39.102323 DUTY Scan : NO K
4876 10:01:39.105544 ZQ Calibration : PASS
4877 10:01:39.106075 Jitter Meter : NO K
4878 10:01:39.109069 CBT Training : PASS
4879 10:01:39.109648 Write leveling : PASS
4880 10:01:39.112302 RX DQS gating : PASS
4881 10:01:39.115360 RX DQ/DQS(RDDQC) : PASS
4882 10:01:39.115847 TX DQ/DQS : PASS
4883 10:01:39.118472 RX DATLAT : PASS
4884 10:01:39.122003 RX DQ/DQS(Engine): PASS
4885 10:01:39.122638 TX OE : NO K
4886 10:01:39.125296 All Pass.
4887 10:01:39.125854
4888 10:01:39.126280 CH 1, Rank 1
4889 10:01:39.128787 SW Impedance : PASS
4890 10:01:39.129259 DUTY Scan : NO K
4891 10:01:39.132365 ZQ Calibration : PASS
4892 10:01:39.135131 Jitter Meter : NO K
4893 10:01:39.135633 CBT Training : PASS
4894 10:01:39.138869 Write leveling : PASS
4895 10:01:39.141689 RX DQS gating : PASS
4896 10:01:39.142183 RX DQ/DQS(RDDQC) : PASS
4897 10:01:39.145237 TX DQ/DQS : PASS
4898 10:01:39.148612 RX DATLAT : PASS
4899 10:01:39.149100 RX DQ/DQS(Engine): PASS
4900 10:01:39.151847 TX OE : NO K
4901 10:01:39.152448 All Pass.
4902 10:01:39.152977
4903 10:01:39.155248 DramC Write-DBI off
4904 10:01:39.158798 PER_BANK_REFRESH: Hybrid Mode
4905 10:01:39.159310 TX_TRACKING: ON
4906 10:01:39.168865 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4907 10:01:39.171938 [FAST_K] Save calibration result to emmc
4908 10:01:39.175831 dramc_set_vcore_voltage set vcore to 662500
4909 10:01:39.176475 Read voltage for 933, 3
4910 10:01:39.178216 Vio18 = 0
4911 10:01:39.178892 Vcore = 662500
4912 10:01:39.179432 Vdram = 0
4913 10:01:39.181763 Vddq = 0
4914 10:01:39.182324 Vmddr = 0
4915 10:01:39.188456 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4916 10:01:39.191844 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4917 10:01:39.194910 MEM_TYPE=3, freq_sel=17
4918 10:01:39.198273 sv_algorithm_assistance_LP4_1600
4919 10:01:39.201793 ============ PULL DRAM RESETB DOWN ============
4920 10:01:39.205057 ========== PULL DRAM RESETB DOWN end =========
4921 10:01:39.211742 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4922 10:01:39.215079 ===================================
4923 10:01:39.215589 LPDDR4 DRAM CONFIGURATION
4924 10:01:39.218311 ===================================
4925 10:01:39.221952 EX_ROW_EN[0] = 0x0
4926 10:01:39.222470 EX_ROW_EN[1] = 0x0
4927 10:01:39.224984 LP4Y_EN = 0x0
4928 10:01:39.228129 WORK_FSP = 0x0
4929 10:01:39.228787 WL = 0x3
4930 10:01:39.232080 RL = 0x3
4931 10:01:39.232591 BL = 0x2
4932 10:01:39.235313 RPST = 0x0
4933 10:01:39.235811 RD_PRE = 0x0
4934 10:01:39.238690 WR_PRE = 0x1
4935 10:01:39.239195 WR_PST = 0x0
4936 10:01:39.242315 DBI_WR = 0x0
4937 10:01:39.242831 DBI_RD = 0x0
4938 10:01:39.244857 OTF = 0x1
4939 10:01:39.248169 ===================================
4940 10:01:39.251636 ===================================
4941 10:01:39.252155 ANA top config
4942 10:01:39.254922 ===================================
4943 10:01:39.258273 DLL_ASYNC_EN = 0
4944 10:01:39.261498 ALL_SLAVE_EN = 1
4945 10:01:39.261963 NEW_RANK_MODE = 1
4946 10:01:39.265252 DLL_IDLE_MODE = 1
4947 10:01:39.268540 LP45_APHY_COMB_EN = 1
4948 10:01:39.271871 TX_ODT_DIS = 1
4949 10:01:39.272389 NEW_8X_MODE = 1
4950 10:01:39.275084 ===================================
4951 10:01:39.278262 ===================================
4952 10:01:39.281545 data_rate = 1866
4953 10:01:39.285346 CKR = 1
4954 10:01:39.288299 DQ_P2S_RATIO = 8
4955 10:01:39.291599 ===================================
4956 10:01:39.295053 CA_P2S_RATIO = 8
4957 10:01:39.298298 DQ_CA_OPEN = 0
4958 10:01:39.299027 DQ_SEMI_OPEN = 0
4959 10:01:39.301743 CA_SEMI_OPEN = 0
4960 10:01:39.305395 CA_FULL_RATE = 0
4961 10:01:39.308083 DQ_CKDIV4_EN = 1
4962 10:01:39.311926 CA_CKDIV4_EN = 1
4963 10:01:39.315033 CA_PREDIV_EN = 0
4964 10:01:39.315604 PH8_DLY = 0
4965 10:01:39.318273 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4966 10:01:39.321548 DQ_AAMCK_DIV = 4
4967 10:01:39.324832 CA_AAMCK_DIV = 4
4968 10:01:39.328105 CA_ADMCK_DIV = 4
4969 10:01:39.331690 DQ_TRACK_CA_EN = 0
4970 10:01:39.332187 CA_PICK = 933
4971 10:01:39.334816 CA_MCKIO = 933
4972 10:01:39.338616 MCKIO_SEMI = 0
4973 10:01:39.341639 PLL_FREQ = 3732
4974 10:01:39.344967 DQ_UI_PI_RATIO = 32
4975 10:01:39.348123 CA_UI_PI_RATIO = 0
4976 10:01:39.351997 ===================================
4977 10:01:39.354804 ===================================
4978 10:01:39.355283 memory_type:LPDDR4
4979 10:01:39.358274 GP_NUM : 10
4980 10:01:39.361854 SRAM_EN : 1
4981 10:01:39.362297 MD32_EN : 0
4982 10:01:39.365007 ===================================
4983 10:01:39.368236 [ANA_INIT] >>>>>>>>>>>>>>
4984 10:01:39.371673 <<<<<< [CONFIGURE PHASE]: ANA_TX
4985 10:01:39.374736 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4986 10:01:39.378076 ===================================
4987 10:01:39.381249 data_rate = 1866,PCW = 0X8f00
4988 10:01:39.384668 ===================================
4989 10:01:39.387823 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4990 10:01:39.391386 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4991 10:01:39.398027 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4992 10:01:39.404502 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4993 10:01:39.407800 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4994 10:01:39.410929 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4995 10:01:39.411406 [ANA_INIT] flow start
4996 10:01:39.414642 [ANA_INIT] PLL >>>>>>>>
4997 10:01:39.417960 [ANA_INIT] PLL <<<<<<<<
4998 10:01:39.418471 [ANA_INIT] MIDPI >>>>>>>>
4999 10:01:39.421163 [ANA_INIT] MIDPI <<<<<<<<
5000 10:01:39.424675 [ANA_INIT] DLL >>>>>>>>
5001 10:01:39.425150 [ANA_INIT] flow end
5002 10:01:39.430897 ============ LP4 DIFF to SE enter ============
5003 10:01:39.434454 ============ LP4 DIFF to SE exit ============
5004 10:01:39.434930 [ANA_INIT] <<<<<<<<<<<<<
5005 10:01:39.437649 [Flow] Enable top DCM control >>>>>
5006 10:01:39.440793 [Flow] Enable top DCM control <<<<<
5007 10:01:39.444085 Enable DLL master slave shuffle
5008 10:01:39.450880 ==============================================================
5009 10:01:39.454326 Gating Mode config
5010 10:01:39.457541 ==============================================================
5011 10:01:39.461041 Config description:
5012 10:01:39.470477 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5013 10:01:39.477146 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5014 10:01:39.480647 SELPH_MODE 0: By rank 1: By Phase
5015 10:01:39.487051 ==============================================================
5016 10:01:39.490289 GAT_TRACK_EN = 1
5017 10:01:39.493862 RX_GATING_MODE = 2
5018 10:01:39.497351 RX_GATING_TRACK_MODE = 2
5019 10:01:39.497821 SELPH_MODE = 1
5020 10:01:39.500900 PICG_EARLY_EN = 1
5021 10:01:39.504078 VALID_LAT_VALUE = 1
5022 10:01:39.510471 ==============================================================
5023 10:01:39.513943 Enter into Gating configuration >>>>
5024 10:01:39.517082 Exit from Gating configuration <<<<
5025 10:01:39.520825 Enter into DVFS_PRE_config >>>>>
5026 10:01:39.530909 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5027 10:01:39.534300 Exit from DVFS_PRE_config <<<<<
5028 10:01:39.537173 Enter into PICG configuration >>>>
5029 10:01:39.540392 Exit from PICG configuration <<<<
5030 10:01:39.544114 [RX_INPUT] configuration >>>>>
5031 10:01:39.547423 [RX_INPUT] configuration <<<<<
5032 10:01:39.550685 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5033 10:01:39.557073 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5034 10:01:39.563807 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5035 10:01:39.570253 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5036 10:01:39.576725 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5037 10:01:39.580411 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5038 10:01:39.587280 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5039 10:01:39.590212 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5040 10:01:39.593430 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5041 10:01:39.596730 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5042 10:01:39.600102 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5043 10:01:39.606827 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5044 10:01:39.610070 ===================================
5045 10:01:39.613606 LPDDR4 DRAM CONFIGURATION
5046 10:01:39.616904 ===================================
5047 10:01:39.617399 EX_ROW_EN[0] = 0x0
5048 10:01:39.620250 EX_ROW_EN[1] = 0x0
5049 10:01:39.620728 LP4Y_EN = 0x0
5050 10:01:39.623289 WORK_FSP = 0x0
5051 10:01:39.623756 WL = 0x3
5052 10:01:39.626684 RL = 0x3
5053 10:01:39.627150 BL = 0x2
5054 10:01:39.630313 RPST = 0x0
5055 10:01:39.630982 RD_PRE = 0x0
5056 10:01:39.633464 WR_PRE = 0x1
5057 10:01:39.633931 WR_PST = 0x0
5058 10:01:39.636850 DBI_WR = 0x0
5059 10:01:39.637317 DBI_RD = 0x0
5060 10:01:39.640080 OTF = 0x1
5061 10:01:39.643404 ===================================
5062 10:01:39.647026 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5063 10:01:39.650127 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5064 10:01:39.657150 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5065 10:01:39.660118 ===================================
5066 10:01:39.660546 LPDDR4 DRAM CONFIGURATION
5067 10:01:39.663500 ===================================
5068 10:01:39.666830 EX_ROW_EN[0] = 0x10
5069 10:01:39.669959 EX_ROW_EN[1] = 0x0
5070 10:01:39.670454 LP4Y_EN = 0x0
5071 10:01:39.673325 WORK_FSP = 0x0
5072 10:01:39.673746 WL = 0x3
5073 10:01:39.676671 RL = 0x3
5074 10:01:39.677094 BL = 0x2
5075 10:01:39.679757 RPST = 0x0
5076 10:01:39.680179 RD_PRE = 0x0
5077 10:01:39.682911 WR_PRE = 0x1
5078 10:01:39.683336 WR_PST = 0x0
5079 10:01:39.686944 DBI_WR = 0x0
5080 10:01:39.687371 DBI_RD = 0x0
5081 10:01:39.689937 OTF = 0x1
5082 10:01:39.693199 ===================================
5083 10:01:39.699666 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5084 10:01:39.703137 nWR fixed to 30
5085 10:01:39.703601 [ModeRegInit_LP4] CH0 RK0
5086 10:01:39.706900 [ModeRegInit_LP4] CH0 RK1
5087 10:01:39.710014 [ModeRegInit_LP4] CH1 RK0
5088 10:01:39.713475 [ModeRegInit_LP4] CH1 RK1
5089 10:01:39.713906 match AC timing 9
5090 10:01:39.719789 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5091 10:01:39.723158 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5092 10:01:39.726637 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5093 10:01:39.733222 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5094 10:01:39.736431 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5095 10:01:39.736863 ==
5096 10:01:39.739915 Dram Type= 6, Freq= 0, CH_0, rank 0
5097 10:01:39.743183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5098 10:01:39.743616 ==
5099 10:01:39.749988 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5100 10:01:39.756683 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5101 10:01:39.759845 [CA 0] Center 38 (7~69) winsize 63
5102 10:01:39.763574 [CA 1] Center 38 (8~69) winsize 62
5103 10:01:39.766607 [CA 2] Center 35 (5~66) winsize 62
5104 10:01:39.769845 [CA 3] Center 34 (4~65) winsize 62
5105 10:01:39.773186 [CA 4] Center 34 (4~65) winsize 62
5106 10:01:39.776415 [CA 5] Center 33 (3~64) winsize 62
5107 10:01:39.776844
5108 10:01:39.779636 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5109 10:01:39.780070
5110 10:01:39.782900 [CATrainingPosCal] consider 1 rank data
5111 10:01:39.786231 u2DelayCellTimex100 = 270/100 ps
5112 10:01:39.789629 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5113 10:01:39.792917 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5114 10:01:39.796179 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5115 10:01:39.799296 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5116 10:01:39.802772 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5117 10:01:39.806059 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5118 10:01:39.806143
5119 10:01:39.809129 CA PerBit enable=1, Macro0, CA PI delay=33
5120 10:01:39.812493
5121 10:01:39.812576 [CBTSetCACLKResult] CA Dly = 33
5122 10:01:39.815741 CS Dly: 6 (0~37)
5123 10:01:39.815826 ==
5124 10:01:39.819370 Dram Type= 6, Freq= 0, CH_0, rank 1
5125 10:01:39.822633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5126 10:01:39.822727 ==
5127 10:01:39.829126 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5128 10:01:39.835793 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5129 10:01:39.839266 [CA 0] Center 38 (8~69) winsize 62
5130 10:01:39.842133 [CA 1] Center 38 (8~68) winsize 61
5131 10:01:39.845657 [CA 2] Center 36 (6~66) winsize 61
5132 10:01:39.849116 [CA 3] Center 35 (5~66) winsize 62
5133 10:01:39.852159 [CA 4] Center 35 (5~65) winsize 61
5134 10:01:39.855481 [CA 5] Center 34 (4~64) winsize 61
5135 10:01:39.855660
5136 10:01:39.859104 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5137 10:01:39.859310
5138 10:01:39.861999 [CATrainingPosCal] consider 2 rank data
5139 10:01:39.865172 u2DelayCellTimex100 = 270/100 ps
5140 10:01:39.868744 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5141 10:01:39.872490 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5142 10:01:39.875798 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5143 10:01:39.878569 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5144 10:01:39.881921 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5145 10:01:39.885208 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5146 10:01:39.888841
5147 10:01:39.892477 CA PerBit enable=1, Macro0, CA PI delay=34
5148 10:01:39.893083
5149 10:01:39.895890 [CBTSetCACLKResult] CA Dly = 34
5150 10:01:39.896614 CS Dly: 7 (0~40)
5151 10:01:39.897022
5152 10:01:39.899108 ----->DramcWriteLeveling(PI) begin...
5153 10:01:39.899593 ==
5154 10:01:39.902188 Dram Type= 6, Freq= 0, CH_0, rank 0
5155 10:01:39.905703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5156 10:01:39.909121 ==
5157 10:01:39.909593 Write leveling (Byte 0): 34 => 34
5158 10:01:39.912313 Write leveling (Byte 1): 29 => 29
5159 10:01:39.915471 DramcWriteLeveling(PI) end<-----
5160 10:01:39.915967
5161 10:01:39.916365 ==
5162 10:01:39.918770 Dram Type= 6, Freq= 0, CH_0, rank 0
5163 10:01:39.925381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5164 10:01:39.926004 ==
5165 10:01:39.926445 [Gating] SW mode calibration
5166 10:01:39.935322 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5167 10:01:39.938689 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5168 10:01:39.945484 0 14 0 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
5169 10:01:39.948604 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5170 10:01:39.952058 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5171 10:01:39.959057 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5172 10:01:39.962080 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5173 10:01:39.965398 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5174 10:01:39.969143 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
5175 10:01:39.975546 0 14 28 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
5176 10:01:39.978882 0 15 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5177 10:01:39.982051 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 10:01:39.989265 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5179 10:01:39.991824 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5180 10:01:39.995432 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5181 10:01:40.001940 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5182 10:01:40.005623 0 15 24 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
5183 10:01:40.008649 0 15 28 | B1->B0 | 2b2b 4646 | 1 0 | (0 0) (0 0)
5184 10:01:40.015523 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 10:01:40.018898 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 10:01:40.022072 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 10:01:40.028687 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 10:01:40.032072 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5189 10:01:40.035402 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5190 10:01:40.041760 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5191 10:01:40.045246 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5192 10:01:40.048317 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 10:01:40.055165 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 10:01:40.058436 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 10:01:40.061759 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 10:01:40.068250 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 10:01:40.071670 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 10:01:40.074874 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 10:01:40.081767 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 10:01:40.084726 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 10:01:40.088332 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 10:01:40.094916 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 10:01:40.098020 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 10:01:40.101505 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 10:01:40.104792 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 10:01:40.111268 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5207 10:01:40.114495 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5208 10:01:40.118014 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5209 10:01:40.121741 Total UI for P1: 0, mck2ui 16
5210 10:01:40.124676 best dqsien dly found for B0: ( 1, 2, 26)
5211 10:01:40.128125 Total UI for P1: 0, mck2ui 16
5212 10:01:40.131348 best dqsien dly found for B1: ( 1, 2, 28)
5213 10:01:40.134579 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5214 10:01:40.138033 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5215 10:01:40.141500
5216 10:01:40.144968 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5217 10:01:40.147856 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5218 10:01:40.151343 [Gating] SW calibration Done
5219 10:01:40.151813 ==
5220 10:01:40.154507 Dram Type= 6, Freq= 0, CH_0, rank 0
5221 10:01:40.158158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5222 10:01:40.158678 ==
5223 10:01:40.159058 RX Vref Scan: 0
5224 10:01:40.159407
5225 10:01:40.161420 RX Vref 0 -> 0, step: 1
5226 10:01:40.161889
5227 10:01:40.164725 RX Delay -80 -> 252, step: 8
5228 10:01:40.167814 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5229 10:01:40.171522 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5230 10:01:40.177965 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5231 10:01:40.181100 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5232 10:01:40.184897 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5233 10:01:40.187673 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5234 10:01:40.190971 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5235 10:01:40.197794 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5236 10:01:40.201135 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5237 10:01:40.204480 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5238 10:01:40.207482 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5239 10:01:40.211254 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5240 10:01:40.214642 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5241 10:01:40.220693 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5242 10:01:40.224216 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5243 10:01:40.227716 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5244 10:01:40.228237 ==
5245 10:01:40.231030 Dram Type= 6, Freq= 0, CH_0, rank 0
5246 10:01:40.234147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5247 10:01:40.234674 ==
5248 10:01:40.237578 DQS Delay:
5249 10:01:40.237964 DQS0 = 0, DQS1 = 0
5250 10:01:40.238325 DQM Delay:
5251 10:01:40.240703 DQM0 = 106, DQM1 = 90
5252 10:01:40.241098 DQ Delay:
5253 10:01:40.244258 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =103
5254 10:01:40.247741 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5255 10:01:40.251040 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5256 10:01:40.254170 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5257 10:01:40.254641
5258 10:01:40.254993
5259 10:01:40.257584 ==
5260 10:01:40.258094 Dram Type= 6, Freq= 0, CH_0, rank 0
5261 10:01:40.264135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5262 10:01:40.264547 ==
5263 10:01:40.264905
5264 10:01:40.265247
5265 10:01:40.267721 TX Vref Scan disable
5266 10:01:40.268122 == TX Byte 0 ==
5267 10:01:40.271140 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5268 10:01:40.277438 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5269 10:01:40.277935 == TX Byte 1 ==
5270 10:01:40.280760 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5271 10:01:40.287469 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5272 10:01:40.287894 ==
5273 10:01:40.290730 Dram Type= 6, Freq= 0, CH_0, rank 0
5274 10:01:40.294515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5275 10:01:40.294937 ==
5276 10:01:40.295270
5277 10:01:40.295592
5278 10:01:40.297233 TX Vref Scan disable
5279 10:01:40.300513 == TX Byte 0 ==
5280 10:01:40.303887 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5281 10:01:40.307468 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5282 10:01:40.310492 == TX Byte 1 ==
5283 10:01:40.313622 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5284 10:01:40.316950 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5285 10:01:40.317372
5286 10:01:40.320348 [DATLAT]
5287 10:01:40.320808 Freq=933, CH0 RK0
5288 10:01:40.321168
5289 10:01:40.323569 DATLAT Default: 0xd
5290 10:01:40.324029 0, 0xFFFF, sum = 0
5291 10:01:40.327200 1, 0xFFFF, sum = 0
5292 10:01:40.327625 2, 0xFFFF, sum = 0
5293 10:01:40.330511 3, 0xFFFF, sum = 0
5294 10:01:40.330976 4, 0xFFFF, sum = 0
5295 10:01:40.333728 5, 0xFFFF, sum = 0
5296 10:01:40.334162 6, 0xFFFF, sum = 0
5297 10:01:40.337041 7, 0xFFFF, sum = 0
5298 10:01:40.337471 8, 0xFFFF, sum = 0
5299 10:01:40.340176 9, 0xFFFF, sum = 0
5300 10:01:40.340606 10, 0x0, sum = 1
5301 10:01:40.343679 11, 0x0, sum = 2
5302 10:01:40.344129 12, 0x0, sum = 3
5303 10:01:40.346980 13, 0x0, sum = 4
5304 10:01:40.347406 best_step = 11
5305 10:01:40.347736
5306 10:01:40.348049 ==
5307 10:01:40.350669 Dram Type= 6, Freq= 0, CH_0, rank 0
5308 10:01:40.353925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5309 10:01:40.356819 ==
5310 10:01:40.357261 RX Vref Scan: 1
5311 10:01:40.357702
5312 10:01:40.360273 RX Vref 0 -> 0, step: 1
5313 10:01:40.360714
5314 10:01:40.363973 RX Delay -53 -> 252, step: 4
5315 10:01:40.364458
5316 10:01:40.367033 Set Vref, RX VrefLevel [Byte0]: 58
5317 10:01:40.370561 [Byte1]: 50
5318 10:01:40.371005
5319 10:01:40.373602 Final RX Vref Byte 0 = 58 to rank0
5320 10:01:40.376848 Final RX Vref Byte 1 = 50 to rank0
5321 10:01:40.380091 Final RX Vref Byte 0 = 58 to rank1
5322 10:01:40.383593 Final RX Vref Byte 1 = 50 to rank1==
5323 10:01:40.386820 Dram Type= 6, Freq= 0, CH_0, rank 0
5324 10:01:40.390288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5325 10:01:40.390772 ==
5326 10:01:40.393726 DQS Delay:
5327 10:01:40.394303 DQS0 = 0, DQS1 = 0
5328 10:01:40.394781 DQM Delay:
5329 10:01:40.396812 DQM0 = 107, DQM1 = 92
5330 10:01:40.397365 DQ Delay:
5331 10:01:40.399969 DQ0 =108, DQ1 =108, DQ2 =102, DQ3 =106
5332 10:01:40.403584 DQ4 =108, DQ5 =98, DQ6 =116, DQ7 =114
5333 10:01:40.406929 DQ8 =86, DQ9 =82, DQ10 =90, DQ11 =90
5334 10:01:40.410099 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =98
5335 10:01:40.410582
5336 10:01:40.411038
5337 10:01:40.420165 [DQSOSCAuto] RK0, (LSB)MR18= 0x211c, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
5338 10:01:40.423254 CH0 RK0: MR19=505, MR18=211C
5339 10:01:40.426865 CH0_RK0: MR19=0x505, MR18=0x211C, DQSOSC=411, MR23=63, INC=64, DEC=42
5340 10:01:40.430080
5341 10:01:40.433726 ----->DramcWriteLeveling(PI) begin...
5342 10:01:40.434245 ==
5343 10:01:40.436637 Dram Type= 6, Freq= 0, CH_0, rank 1
5344 10:01:40.440262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5345 10:01:40.440707 ==
5346 10:01:40.443183 Write leveling (Byte 0): 35 => 35
5347 10:01:40.446482 Write leveling (Byte 1): 26 => 26
5348 10:01:40.449831 DramcWriteLeveling(PI) end<-----
5349 10:01:40.450270
5350 10:01:40.450755 ==
5351 10:01:40.453447 Dram Type= 6, Freq= 0, CH_0, rank 1
5352 10:01:40.456830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5353 10:01:40.457275 ==
5354 10:01:40.459897 [Gating] SW mode calibration
5355 10:01:40.466427 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5356 10:01:40.473430 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5357 10:01:40.476534 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5358 10:01:40.479844 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5359 10:01:40.486337 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5360 10:01:40.489800 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5361 10:01:40.492889 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5362 10:01:40.499937 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5363 10:01:40.502882 0 14 24 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 0)
5364 10:01:40.506888 0 14 28 | B1->B0 | 2f2f 2626 | 0 0 | (1 0) (0 0)
5365 10:01:40.509894 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5366 10:01:40.516386 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5367 10:01:40.519609 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5368 10:01:40.523158 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5369 10:01:40.529491 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5370 10:01:40.532853 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5371 10:01:40.536360 0 15 24 | B1->B0 | 2a2a 2c2c | 0 0 | (0 0) (0 0)
5372 10:01:40.542958 0 15 28 | B1->B0 | 3a3a 4141 | 0 0 | (0 0) (0 0)
5373 10:01:40.546155 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 10:01:40.549705 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 10:01:40.556436 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 10:01:40.559451 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 10:01:40.563096 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 10:01:40.569703 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 10:01:40.572930 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 10:01:40.576639 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5381 10:01:40.582959 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 10:01:40.586597 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 10:01:40.589999 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 10:01:40.596313 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 10:01:40.599345 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 10:01:40.602843 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 10:01:40.609433 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 10:01:40.612987 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 10:01:40.616276 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 10:01:40.622867 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 10:01:40.626301 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 10:01:40.629703 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 10:01:40.636105 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 10:01:40.639722 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 10:01:40.642906 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 10:01:40.646490 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5397 10:01:40.652949 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5398 10:01:40.656197 Total UI for P1: 0, mck2ui 16
5399 10:01:40.659127 best dqsien dly found for B0: ( 1, 2, 28)
5400 10:01:40.662542 Total UI for P1: 0, mck2ui 16
5401 10:01:40.666039 best dqsien dly found for B1: ( 1, 2, 28)
5402 10:01:40.669104 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5403 10:01:40.672317 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5404 10:01:40.672779
5405 10:01:40.675884 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5406 10:01:40.678883 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5407 10:01:40.682661 [Gating] SW calibration Done
5408 10:01:40.683125 ==
5409 10:01:40.685614 Dram Type= 6, Freq= 0, CH_0, rank 1
5410 10:01:40.688987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5411 10:01:40.689456 ==
5412 10:01:40.692488 RX Vref Scan: 0
5413 10:01:40.693048
5414 10:01:40.695939 RX Vref 0 -> 0, step: 1
5415 10:01:40.696498
5416 10:01:40.696867 RX Delay -80 -> 252, step: 8
5417 10:01:40.702490 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5418 10:01:40.705624 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5419 10:01:40.708872 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5420 10:01:40.712430 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5421 10:01:40.715698 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5422 10:01:40.718866 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5423 10:01:40.725688 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5424 10:01:40.728757 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5425 10:01:40.732115 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5426 10:01:40.736091 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5427 10:01:40.738998 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5428 10:01:40.745507 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5429 10:01:40.748896 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5430 10:01:40.751953 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5431 10:01:40.755186 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5432 10:01:40.759065 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5433 10:01:40.759628 ==
5434 10:01:40.762095 Dram Type= 6, Freq= 0, CH_0, rank 1
5435 10:01:40.768828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5436 10:01:40.769371 ==
5437 10:01:40.769915 DQS Delay:
5438 10:01:40.770280 DQS0 = 0, DQS1 = 0
5439 10:01:40.772341 DQM Delay:
5440 10:01:40.772906 DQM0 = 104, DQM1 = 91
5441 10:01:40.775181 DQ Delay:
5442 10:01:40.778635 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5443 10:01:40.781546 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =111
5444 10:01:40.785026 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =87
5445 10:01:40.788383 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5446 10:01:40.788845
5447 10:01:40.789317
5448 10:01:40.789668 ==
5449 10:01:40.791573 Dram Type= 6, Freq= 0, CH_0, rank 1
5450 10:01:40.794880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5451 10:01:40.795348 ==
5452 10:01:40.795712
5453 10:01:40.796048
5454 10:01:40.798637 TX Vref Scan disable
5455 10:01:40.802303 == TX Byte 0 ==
5456 10:01:40.805222 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5457 10:01:40.808513 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5458 10:01:40.811758 == TX Byte 1 ==
5459 10:01:40.815103 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5460 10:01:40.818522 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5461 10:01:40.819073 ==
5462 10:01:40.822009 Dram Type= 6, Freq= 0, CH_0, rank 1
5463 10:01:40.825367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5464 10:01:40.825833 ==
5465 10:01:40.828375
5466 10:01:40.828928
5467 10:01:40.829297 TX Vref Scan disable
5468 10:01:40.832578 == TX Byte 0 ==
5469 10:01:40.835586 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5470 10:01:40.841763 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5471 10:01:40.842320 == TX Byte 1 ==
5472 10:01:40.845411 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5473 10:01:40.848390 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5474 10:01:40.852252
5475 10:01:40.852960 [DATLAT]
5476 10:01:40.853343 Freq=933, CH0 RK1
5477 10:01:40.853694
5478 10:01:40.855217 DATLAT Default: 0xb
5479 10:01:40.855680 0, 0xFFFF, sum = 0
5480 10:01:40.858486 1, 0xFFFF, sum = 0
5481 10:01:40.858955 2, 0xFFFF, sum = 0
5482 10:01:40.861727 3, 0xFFFF, sum = 0
5483 10:01:40.862210 4, 0xFFFF, sum = 0
5484 10:01:40.865091 5, 0xFFFF, sum = 0
5485 10:01:40.868601 6, 0xFFFF, sum = 0
5486 10:01:40.869178 7, 0xFFFF, sum = 0
5487 10:01:40.871757 8, 0xFFFF, sum = 0
5488 10:01:40.872332 9, 0xFFFF, sum = 0
5489 10:01:40.875020 10, 0x0, sum = 1
5490 10:01:40.875502 11, 0x0, sum = 2
5491 10:01:40.878547 12, 0x0, sum = 3
5492 10:01:40.879139 13, 0x0, sum = 4
5493 10:01:40.879528 best_step = 11
5494 10:01:40.879901
5495 10:01:40.881719 ==
5496 10:01:40.885410 Dram Type= 6, Freq= 0, CH_0, rank 1
5497 10:01:40.888429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5498 10:01:40.888911 ==
5499 10:01:40.889369 RX Vref Scan: 0
5500 10:01:40.889747
5501 10:01:40.891723 RX Vref 0 -> 0, step: 1
5502 10:01:40.892296
5503 10:01:40.895265 RX Delay -53 -> 252, step: 4
5504 10:01:40.898544 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5505 10:01:40.905419 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5506 10:01:40.908256 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5507 10:01:40.911564 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5508 10:01:40.915282 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5509 10:01:40.918475 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5510 10:01:40.924814 iDelay=199, Bit 6, Center 110 (23 ~ 198) 176
5511 10:01:40.928318 iDelay=199, Bit 7, Center 110 (23 ~ 198) 176
5512 10:01:40.931608 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5513 10:01:40.934573 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5514 10:01:40.937984 iDelay=199, Bit 10, Center 92 (7 ~ 178) 172
5515 10:01:40.941533 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5516 10:01:40.948158 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5517 10:01:40.951575 iDelay=199, Bit 13, Center 96 (15 ~ 178) 164
5518 10:01:40.954660 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5519 10:01:40.957945 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5520 10:01:40.958450 ==
5521 10:01:40.961706 Dram Type= 6, Freq= 0, CH_0, rank 1
5522 10:01:40.968263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5523 10:01:40.968839 ==
5524 10:01:40.969226 DQS Delay:
5525 10:01:40.969578 DQS0 = 0, DQS1 = 0
5526 10:01:40.971225 DQM Delay:
5527 10:01:40.971699 DQM0 = 104, DQM1 = 92
5528 10:01:40.974715 DQ Delay:
5529 10:01:40.978151 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =98
5530 10:01:40.981511 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =110
5531 10:01:40.984895 DQ8 =84, DQ9 =80, DQ10 =92, DQ11 =92
5532 10:01:40.988021 DQ12 =96, DQ13 =96, DQ14 =98, DQ15 =98
5533 10:01:40.988497
5534 10:01:40.988871
5535 10:01:40.994830 [DQSOSCAuto] RK1, (LSB)MR18= 0x2506, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 410 ps
5536 10:01:40.998294 CH0 RK1: MR19=505, MR18=2506
5537 10:01:41.004889 CH0_RK1: MR19=0x505, MR18=0x2506, DQSOSC=410, MR23=63, INC=64, DEC=42
5538 10:01:41.007864 [RxdqsGatingPostProcess] freq 933
5539 10:01:41.011917 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5540 10:01:41.014742 best DQS0 dly(2T, 0.5T) = (0, 10)
5541 10:01:41.018128 best DQS1 dly(2T, 0.5T) = (0, 10)
5542 10:01:41.021733 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5543 10:01:41.024733 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5544 10:01:41.028068 best DQS0 dly(2T, 0.5T) = (0, 10)
5545 10:01:41.031818 best DQS1 dly(2T, 0.5T) = (0, 10)
5546 10:01:41.035061 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5547 10:01:41.038600 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5548 10:01:41.041577 Pre-setting of DQS Precalculation
5549 10:01:41.044878 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5550 10:01:41.045454 ==
5551 10:01:41.047758 Dram Type= 6, Freq= 0, CH_1, rank 0
5552 10:01:41.054700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5553 10:01:41.055265 ==
5554 10:01:41.058046 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5555 10:01:41.064556 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5556 10:01:41.068098 [CA 0] Center 37 (7~68) winsize 62
5557 10:01:41.071131 [CA 1] Center 37 (7~68) winsize 62
5558 10:01:41.074787 [CA 2] Center 35 (5~66) winsize 62
5559 10:01:41.077872 [CA 3] Center 34 (4~65) winsize 62
5560 10:01:41.081451 [CA 4] Center 34 (4~65) winsize 62
5561 10:01:41.084442 [CA 5] Center 34 (3~65) winsize 63
5562 10:01:41.084919
5563 10:01:41.087602 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5564 10:01:41.088080
5565 10:01:41.090939 [CATrainingPosCal] consider 1 rank data
5566 10:01:41.094593 u2DelayCellTimex100 = 270/100 ps
5567 10:01:41.097664 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5568 10:01:41.104596 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5569 10:01:41.107846 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5570 10:01:41.111180 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5571 10:01:41.114783 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5572 10:01:41.117925 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
5573 10:01:41.118532
5574 10:01:41.121014 CA PerBit enable=1, Macro0, CA PI delay=34
5575 10:01:41.121637
5576 10:01:41.124137 [CBTSetCACLKResult] CA Dly = 34
5577 10:01:41.124613 CS Dly: 5 (0~36)
5578 10:01:41.127648 ==
5579 10:01:41.130781 Dram Type= 6, Freq= 0, CH_1, rank 1
5580 10:01:41.134128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5581 10:01:41.134638 ==
5582 10:01:41.137629 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5583 10:01:41.143942 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5584 10:01:41.147989 [CA 0] Center 37 (7~68) winsize 62
5585 10:01:41.151285 [CA 1] Center 37 (7~68) winsize 62
5586 10:01:41.154170 [CA 2] Center 35 (5~66) winsize 62
5587 10:01:41.157857 [CA 3] Center 34 (4~65) winsize 62
5588 10:01:41.161383 [CA 4] Center 34 (4~65) winsize 62
5589 10:01:41.164623 [CA 5] Center 34 (4~64) winsize 61
5590 10:01:41.165195
5591 10:01:41.168175 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5592 10:01:41.168753
5593 10:01:41.170990 [CATrainingPosCal] consider 2 rank data
5594 10:01:41.174515 u2DelayCellTimex100 = 270/100 ps
5595 10:01:41.178134 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5596 10:01:41.181161 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5597 10:01:41.187407 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5598 10:01:41.190707 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5599 10:01:41.194642 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5600 10:01:41.197558 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5601 10:01:41.198036
5602 10:01:41.200923 CA PerBit enable=1, Macro0, CA PI delay=34
5603 10:01:41.201402
5604 10:01:41.204608 [CBTSetCACLKResult] CA Dly = 34
5605 10:01:41.205185 CS Dly: 6 (0~38)
5606 10:01:41.205568
5607 10:01:41.210648 ----->DramcWriteLeveling(PI) begin...
5608 10:01:41.211213 ==
5609 10:01:41.214847 Dram Type= 6, Freq= 0, CH_1, rank 0
5610 10:01:41.217793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5611 10:01:41.218364 ==
5612 10:01:41.221187 Write leveling (Byte 0): 29 => 29
5613 10:01:41.223846 Write leveling (Byte 1): 31 => 31
5614 10:01:41.227362 DramcWriteLeveling(PI) end<-----
5615 10:01:41.227837
5616 10:01:41.228215 ==
5617 10:01:41.231162 Dram Type= 6, Freq= 0, CH_1, rank 0
5618 10:01:41.234076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5619 10:01:41.234705 ==
5620 10:01:41.237714 [Gating] SW mode calibration
5621 10:01:41.244362 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5622 10:01:41.250826 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5623 10:01:41.254014 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5624 10:01:41.257101 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5625 10:01:41.264654 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5626 10:01:41.267303 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5627 10:01:41.270628 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5628 10:01:41.277346 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5629 10:01:41.280277 0 14 24 | B1->B0 | 3131 3131 | 1 0 | (1 1) (0 1)
5630 10:01:41.283813 0 14 28 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
5631 10:01:41.290743 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5632 10:01:41.293490 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5633 10:01:41.297195 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5634 10:01:41.303441 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5635 10:01:41.306830 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5636 10:01:41.310328 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5637 10:01:41.316911 0 15 24 | B1->B0 | 2626 2b2b | 0 0 | (0 0) (0 0)
5638 10:01:41.320333 0 15 28 | B1->B0 | 3f3f 4242 | 0 0 | (0 0) (0 0)
5639 10:01:41.323424 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 10:01:41.326883 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5641 10:01:41.333528 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 10:01:41.336824 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 10:01:41.340540 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 10:01:41.346989 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5645 10:01:41.349988 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5646 10:01:41.353503 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5647 10:01:41.360473 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 10:01:41.363678 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 10:01:41.366649 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 10:01:41.372925 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 10:01:41.376670 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 10:01:41.380187 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 10:01:41.386666 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 10:01:41.389805 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 10:01:41.393398 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 10:01:41.399688 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 10:01:41.403272 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 10:01:41.406172 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 10:01:41.413056 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 10:01:41.416577 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5661 10:01:41.419637 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5662 10:01:41.426560 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5663 10:01:41.427125 Total UI for P1: 0, mck2ui 16
5664 10:01:41.433198 best dqsien dly found for B0: ( 1, 2, 22)
5665 10:01:41.433772 Total UI for P1: 0, mck2ui 16
5666 10:01:41.440376 best dqsien dly found for B1: ( 1, 2, 26)
5667 10:01:41.443100 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5668 10:01:41.446748 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5669 10:01:41.447326
5670 10:01:41.449815 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5671 10:01:41.453327 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5672 10:01:41.456518 [Gating] SW calibration Done
5673 10:01:41.457100 ==
5674 10:01:41.459818 Dram Type= 6, Freq= 0, CH_1, rank 0
5675 10:01:41.463259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5676 10:01:41.463833 ==
5677 10:01:41.466638 RX Vref Scan: 0
5678 10:01:41.467208
5679 10:01:41.467788 RX Vref 0 -> 0, step: 1
5680 10:01:41.468211
5681 10:01:41.469451 RX Delay -80 -> 252, step: 8
5682 10:01:41.473423 iDelay=208, Bit 0, Center 111 (32 ~ 191) 160
5683 10:01:41.479682 iDelay=208, Bit 1, Center 99 (16 ~ 183) 168
5684 10:01:41.483212 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5685 10:01:41.486007 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5686 10:01:41.489685 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5687 10:01:41.492949 iDelay=208, Bit 5, Center 115 (32 ~ 199) 168
5688 10:01:41.496343 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5689 10:01:41.502742 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5690 10:01:41.506049 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5691 10:01:41.509485 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5692 10:01:41.512743 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5693 10:01:41.516107 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5694 10:01:41.522935 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5695 10:01:41.525931 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5696 10:01:41.529806 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5697 10:01:41.532620 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5698 10:01:41.533097 ==
5699 10:01:41.536474 Dram Type= 6, Freq= 0, CH_1, rank 0
5700 10:01:41.539375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5701 10:01:41.539948 ==
5702 10:01:41.542716 DQS Delay:
5703 10:01:41.543286 DQS0 = 0, DQS1 = 0
5704 10:01:41.546368 DQM Delay:
5705 10:01:41.546969 DQM0 = 105, DQM1 = 95
5706 10:01:41.547351 DQ Delay:
5707 10:01:41.549532 DQ0 =111, DQ1 =99, DQ2 =95, DQ3 =103
5708 10:01:41.555942 DQ4 =103, DQ5 =115, DQ6 =115, DQ7 =103
5709 10:01:41.556513 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5710 10:01:41.562683 DQ12 =103, DQ13 =99, DQ14 =103, DQ15 =99
5711 10:01:41.563237
5712 10:01:41.563611
5713 10:01:41.563963 ==
5714 10:01:41.565728 Dram Type= 6, Freq= 0, CH_1, rank 0
5715 10:01:41.569269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5716 10:01:41.569750 ==
5717 10:01:41.570161
5718 10:01:41.570546
5719 10:01:41.572493 TX Vref Scan disable
5720 10:01:41.573179 == TX Byte 0 ==
5721 10:01:41.579316 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5722 10:01:41.582602 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5723 10:01:41.583073 == TX Byte 1 ==
5724 10:01:41.589236 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5725 10:01:41.592991 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5726 10:01:41.593562 ==
5727 10:01:41.595934 Dram Type= 6, Freq= 0, CH_1, rank 0
5728 10:01:41.598908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5729 10:01:41.599379 ==
5730 10:01:41.599751
5731 10:01:41.600092
5732 10:01:41.602236 TX Vref Scan disable
5733 10:01:41.605620 == TX Byte 0 ==
5734 10:01:41.609327 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5735 10:01:41.612483 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5736 10:01:41.615617 == TX Byte 1 ==
5737 10:01:41.619728 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5738 10:01:41.622745 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5739 10:01:41.623224
5740 10:01:41.625813 [DATLAT]
5741 10:01:41.626285 Freq=933, CH1 RK0
5742 10:01:41.626696
5743 10:01:41.628998 DATLAT Default: 0xd
5744 10:01:41.629469 0, 0xFFFF, sum = 0
5745 10:01:41.632597 1, 0xFFFF, sum = 0
5746 10:01:41.633177 2, 0xFFFF, sum = 0
5747 10:01:41.635962 3, 0xFFFF, sum = 0
5748 10:01:41.636541 4, 0xFFFF, sum = 0
5749 10:01:41.639340 5, 0xFFFF, sum = 0
5750 10:01:41.639923 6, 0xFFFF, sum = 0
5751 10:01:41.642110 7, 0xFFFF, sum = 0
5752 10:01:41.642635 8, 0xFFFF, sum = 0
5753 10:01:41.645669 9, 0xFFFF, sum = 0
5754 10:01:41.646249 10, 0x0, sum = 1
5755 10:01:41.649260 11, 0x0, sum = 2
5756 10:01:41.649835 12, 0x0, sum = 3
5757 10:01:41.652560 13, 0x0, sum = 4
5758 10:01:41.653140 best_step = 11
5759 10:01:41.653522
5760 10:01:41.653924 ==
5761 10:01:41.655870 Dram Type= 6, Freq= 0, CH_1, rank 0
5762 10:01:41.662901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5763 10:01:41.663479 ==
5764 10:01:41.663868 RX Vref Scan: 1
5765 10:01:41.664217
5766 10:01:41.665457 RX Vref 0 -> 0, step: 1
5767 10:01:41.665928
5768 10:01:41.669323 RX Delay -53 -> 252, step: 4
5769 10:01:41.669894
5770 10:01:41.672224 Set Vref, RX VrefLevel [Byte0]: 54
5771 10:01:41.675887 [Byte1]: 58
5772 10:01:41.676462
5773 10:01:41.679319 Final RX Vref Byte 0 = 54 to rank0
5774 10:01:41.682033 Final RX Vref Byte 1 = 58 to rank0
5775 10:01:41.685764 Final RX Vref Byte 0 = 54 to rank1
5776 10:01:41.689045 Final RX Vref Byte 1 = 58 to rank1==
5777 10:01:41.692235 Dram Type= 6, Freq= 0, CH_1, rank 0
5778 10:01:41.696092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5779 10:01:41.696670 ==
5780 10:01:41.698891 DQS Delay:
5781 10:01:41.699364 DQS0 = 0, DQS1 = 0
5782 10:01:41.699745 DQM Delay:
5783 10:01:41.702090 DQM0 = 108, DQM1 = 101
5784 10:01:41.702605 DQ Delay:
5785 10:01:41.705477 DQ0 =110, DQ1 =102, DQ2 =100, DQ3 =106
5786 10:01:41.709088 DQ4 =106, DQ5 =116, DQ6 =118, DQ7 =106
5787 10:01:41.712397 DQ8 =92, DQ9 =90, DQ10 =102, DQ11 =94
5788 10:01:41.718951 DQ12 =110, DQ13 =106, DQ14 =108, DQ15 =106
5789 10:01:41.719509
5790 10:01:41.719886
5791 10:01:41.725697 [DQSOSCAuto] RK0, (LSB)MR18= 0x1931, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5792 10:01:41.729068 CH1 RK0: MR19=505, MR18=1931
5793 10:01:41.735544 CH1_RK0: MR19=0x505, MR18=0x1931, DQSOSC=406, MR23=63, INC=65, DEC=43
5794 10:01:41.736114
5795 10:01:41.738447 ----->DramcWriteLeveling(PI) begin...
5796 10:01:41.738922 ==
5797 10:01:41.742076 Dram Type= 6, Freq= 0, CH_1, rank 1
5798 10:01:41.745783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5799 10:01:41.746366 ==
5800 10:01:41.749044 Write leveling (Byte 0): 27 => 27
5801 10:01:41.752135 Write leveling (Byte 1): 27 => 27
5802 10:01:41.755862 DramcWriteLeveling(PI) end<-----
5803 10:01:41.756433
5804 10:01:41.756809 ==
5805 10:01:41.759158 Dram Type= 6, Freq= 0, CH_1, rank 1
5806 10:01:41.761925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5807 10:01:41.762531 ==
5808 10:01:41.765359 [Gating] SW mode calibration
5809 10:01:41.771789 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5810 10:01:41.778908 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5811 10:01:41.781808 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5812 10:01:41.788348 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5813 10:01:41.791835 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5814 10:01:41.795254 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5815 10:01:41.801762 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5816 10:01:41.805351 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5817 10:01:41.808578 0 14 24 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5818 10:01:41.814758 0 14 28 | B1->B0 | 2323 2e2e | 0 1 | (1 0) (1 0)
5819 10:01:41.818350 0 15 0 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
5820 10:01:41.821644 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5821 10:01:41.827904 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5822 10:01:41.831644 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5823 10:01:41.835244 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5824 10:01:41.838516 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5825 10:01:41.844629 0 15 24 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (0 0)
5826 10:01:41.848053 0 15 28 | B1->B0 | 3c3c 3434 | 0 1 | (1 1) (0 0)
5827 10:01:41.851509 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5828 10:01:41.858162 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 10:01:41.861828 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5830 10:01:41.864838 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5831 10:01:41.871254 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 10:01:41.875038 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5833 10:01:41.878043 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5834 10:01:41.884803 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5835 10:01:41.887917 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 10:01:41.891024 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 10:01:41.898042 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 10:01:41.901234 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 10:01:41.904329 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 10:01:41.911122 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 10:01:41.914266 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 10:01:41.918548 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 10:01:41.924475 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 10:01:41.927852 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 10:01:41.930881 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 10:01:41.937925 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 10:01:41.941313 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 10:01:41.944685 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 10:01:41.951099 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5850 10:01:41.954447 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5851 10:01:41.957499 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5852 10:01:41.961178 Total UI for P1: 0, mck2ui 16
5853 10:01:41.964381 best dqsien dly found for B0: ( 1, 2, 26)
5854 10:01:41.967509 Total UI for P1: 0, mck2ui 16
5855 10:01:41.971101 best dqsien dly found for B1: ( 1, 2, 26)
5856 10:01:41.974426 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5857 10:01:41.977485 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5858 10:01:41.977998
5859 10:01:41.980671 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5860 10:01:41.987345 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5861 10:01:41.987857 [Gating] SW calibration Done
5862 10:01:41.988201 ==
5863 10:01:41.990561 Dram Type= 6, Freq= 0, CH_1, rank 1
5864 10:01:41.997441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5865 10:01:41.997952 ==
5866 10:01:41.998292 RX Vref Scan: 0
5867 10:01:41.998692
5868 10:01:42.000622 RX Vref 0 -> 0, step: 1
5869 10:01:42.001042
5870 10:01:42.003991 RX Delay -80 -> 252, step: 8
5871 10:01:42.007277 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5872 10:01:42.010685 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5873 10:01:42.014144 iDelay=200, Bit 2, Center 91 (8 ~ 175) 168
5874 10:01:42.017592 iDelay=200, Bit 3, Center 103 (16 ~ 191) 176
5875 10:01:42.023847 iDelay=200, Bit 4, Center 107 (24 ~ 191) 168
5876 10:01:42.027603 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5877 10:01:42.030783 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5878 10:01:42.033901 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5879 10:01:42.037074 iDelay=200, Bit 8, Center 87 (0 ~ 175) 176
5880 10:01:42.044023 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5881 10:01:42.047453 iDelay=200, Bit 10, Center 99 (8 ~ 191) 184
5882 10:01:42.050721 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5883 10:01:42.054063 iDelay=200, Bit 12, Center 111 (24 ~ 199) 176
5884 10:01:42.057442 iDelay=200, Bit 13, Center 107 (16 ~ 199) 184
5885 10:01:42.063783 iDelay=200, Bit 14, Center 107 (16 ~ 199) 184
5886 10:01:42.067190 iDelay=200, Bit 15, Center 107 (16 ~ 199) 184
5887 10:01:42.067664 ==
5888 10:01:42.070620 Dram Type= 6, Freq= 0, CH_1, rank 1
5889 10:01:42.073908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5890 10:01:42.074517 ==
5891 10:01:42.074897 DQS Delay:
5892 10:01:42.077375 DQS0 = 0, DQS1 = 0
5893 10:01:42.077942 DQM Delay:
5894 10:01:42.080559 DQM0 = 104, DQM1 = 99
5895 10:01:42.081125 DQ Delay:
5896 10:01:42.084050 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =103
5897 10:01:42.087137 DQ4 =107, DQ5 =111, DQ6 =111, DQ7 =103
5898 10:01:42.090523 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5899 10:01:42.094235 DQ12 =111, DQ13 =107, DQ14 =107, DQ15 =107
5900 10:01:42.094833
5901 10:01:42.095205
5902 10:01:42.097664 ==
5903 10:01:42.098242 Dram Type= 6, Freq= 0, CH_1, rank 1
5904 10:01:42.103843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5905 10:01:42.104571 ==
5906 10:01:42.104972
5907 10:01:42.105320
5908 10:01:42.107330 TX Vref Scan disable
5909 10:01:42.107798 == TX Byte 0 ==
5910 10:01:42.110264 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5911 10:01:42.117499 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5912 10:01:42.118210 == TX Byte 1 ==
5913 10:01:42.120571 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5914 10:01:42.127158 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5915 10:01:42.127725 ==
5916 10:01:42.130481 Dram Type= 6, Freq= 0, CH_1, rank 1
5917 10:01:42.133817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5918 10:01:42.134418 ==
5919 10:01:42.134800
5920 10:01:42.135147
5921 10:01:42.137281 TX Vref Scan disable
5922 10:01:42.140573 == TX Byte 0 ==
5923 10:01:42.143711 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5924 10:01:42.147199 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5925 10:01:42.150811 == TX Byte 1 ==
5926 10:01:42.154233 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5927 10:01:42.157316 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5928 10:01:42.157884
5929 10:01:42.158276 [DATLAT]
5930 10:01:42.161074 Freq=933, CH1 RK1
5931 10:01:42.161543
5932 10:01:42.163586 DATLAT Default: 0xb
5933 10:01:42.164049 0, 0xFFFF, sum = 0
5934 10:01:42.167003 1, 0xFFFF, sum = 0
5935 10:01:42.167478 2, 0xFFFF, sum = 0
5936 10:01:42.170586 3, 0xFFFF, sum = 0
5937 10:01:42.171158 4, 0xFFFF, sum = 0
5938 10:01:42.173960 5, 0xFFFF, sum = 0
5939 10:01:42.174567 6, 0xFFFF, sum = 0
5940 10:01:42.176741 7, 0xFFFF, sum = 0
5941 10:01:42.177212 8, 0xFFFF, sum = 0
5942 10:01:42.180030 9, 0xFFFF, sum = 0
5943 10:01:42.180503 10, 0x0, sum = 1
5944 10:01:42.183262 11, 0x0, sum = 2
5945 10:01:42.183737 12, 0x0, sum = 3
5946 10:01:42.187027 13, 0x0, sum = 4
5947 10:01:42.187601 best_step = 11
5948 10:01:42.187974
5949 10:01:42.188317 ==
5950 10:01:42.190102 Dram Type= 6, Freq= 0, CH_1, rank 1
5951 10:01:42.193846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5952 10:01:42.194454 ==
5953 10:01:42.197063 RX Vref Scan: 0
5954 10:01:42.197634
5955 10:01:42.200353 RX Vref 0 -> 0, step: 1
5956 10:01:42.200933
5957 10:01:42.201310 RX Delay -45 -> 252, step: 4
5958 10:01:42.208274 iDelay=199, Bit 0, Center 112 (39 ~ 186) 148
5959 10:01:42.211305 iDelay=199, Bit 1, Center 100 (23 ~ 178) 156
5960 10:01:42.214447 iDelay=199, Bit 2, Center 96 (19 ~ 174) 156
5961 10:01:42.218271 iDelay=199, Bit 3, Center 106 (27 ~ 186) 160
5962 10:01:42.221281 iDelay=199, Bit 4, Center 108 (31 ~ 186) 156
5963 10:01:42.228059 iDelay=199, Bit 5, Center 118 (39 ~ 198) 160
5964 10:01:42.231703 iDelay=199, Bit 6, Center 114 (35 ~ 194) 160
5965 10:01:42.235013 iDelay=199, Bit 7, Center 106 (31 ~ 182) 152
5966 10:01:42.237982 iDelay=199, Bit 8, Center 90 (11 ~ 170) 160
5967 10:01:42.241291 iDelay=199, Bit 9, Center 92 (11 ~ 174) 164
5968 10:01:42.248506 iDelay=199, Bit 10, Center 102 (19 ~ 186) 168
5969 10:01:42.250995 iDelay=199, Bit 11, Center 96 (15 ~ 178) 164
5970 10:01:42.254604 iDelay=199, Bit 12, Center 110 (27 ~ 194) 168
5971 10:01:42.258067 iDelay=199, Bit 13, Center 106 (23 ~ 190) 168
5972 10:01:42.261280 iDelay=199, Bit 14, Center 106 (23 ~ 190) 168
5973 10:01:42.267656 iDelay=199, Bit 15, Center 110 (27 ~ 194) 168
5974 10:01:42.268230 ==
5975 10:01:42.271264 Dram Type= 6, Freq= 0, CH_1, rank 1
5976 10:01:42.274737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5977 10:01:42.275311 ==
5978 10:01:42.275686 DQS Delay:
5979 10:01:42.278011 DQS0 = 0, DQS1 = 0
5980 10:01:42.278624 DQM Delay:
5981 10:01:42.281442 DQM0 = 107, DQM1 = 101
5982 10:01:42.282016 DQ Delay:
5983 10:01:42.284924 DQ0 =112, DQ1 =100, DQ2 =96, DQ3 =106
5984 10:01:42.287788 DQ4 =108, DQ5 =118, DQ6 =114, DQ7 =106
5985 10:01:42.291031 DQ8 =90, DQ9 =92, DQ10 =102, DQ11 =96
5986 10:01:42.294595 DQ12 =110, DQ13 =106, DQ14 =106, DQ15 =110
5987 10:01:42.295167
5988 10:01:42.295540
5989 10:01:42.304831 [DQSOSCAuto] RK1, (LSB)MR18= 0x2400, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
5990 10:01:42.307342 CH1 RK1: MR19=505, MR18=2400
5991 10:01:42.314098 CH1_RK1: MR19=0x505, MR18=0x2400, DQSOSC=410, MR23=63, INC=64, DEC=42
5992 10:01:42.314812 [RxdqsGatingPostProcess] freq 933
5993 10:01:42.320896 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5994 10:01:42.324103 best DQS0 dly(2T, 0.5T) = (0, 10)
5995 10:01:42.327851 best DQS1 dly(2T, 0.5T) = (0, 10)
5996 10:01:42.331222 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5997 10:01:42.334259 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5998 10:01:42.338187 best DQS0 dly(2T, 0.5T) = (0, 10)
5999 10:01:42.341269 best DQS1 dly(2T, 0.5T) = (0, 10)
6000 10:01:42.344068 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6001 10:01:42.347646 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6002 10:01:42.350953 Pre-setting of DQS Precalculation
6003 10:01:42.354111 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6004 10:01:42.361324 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6005 10:01:42.367855 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6006 10:01:42.368439
6007 10:01:42.370889
6008 10:01:42.371469 [Calibration Summary] 1866 Mbps
6009 10:01:42.374468 CH 0, Rank 0
6010 10:01:42.375064 SW Impedance : PASS
6011 10:01:42.377658 DUTY Scan : NO K
6012 10:01:42.380661 ZQ Calibration : PASS
6013 10:01:42.381139 Jitter Meter : NO K
6014 10:01:42.384321 CBT Training : PASS
6015 10:01:42.387342 Write leveling : PASS
6016 10:01:42.387819 RX DQS gating : PASS
6017 10:01:42.390617 RX DQ/DQS(RDDQC) : PASS
6018 10:01:42.394124 TX DQ/DQS : PASS
6019 10:01:42.394752 RX DATLAT : PASS
6020 10:01:42.397475 RX DQ/DQS(Engine): PASS
6021 10:01:42.398052 TX OE : NO K
6022 10:01:42.401090 All Pass.
6023 10:01:42.401670
6024 10:01:42.402050 CH 0, Rank 1
6025 10:01:42.404386 SW Impedance : PASS
6026 10:01:42.404861 DUTY Scan : NO K
6027 10:01:42.407402 ZQ Calibration : PASS
6028 10:01:42.410651 Jitter Meter : NO K
6029 10:01:42.411125 CBT Training : PASS
6030 10:01:42.413895 Write leveling : PASS
6031 10:01:42.417294 RX DQS gating : PASS
6032 10:01:42.417768 RX DQ/DQS(RDDQC) : PASS
6033 10:01:42.420814 TX DQ/DQS : PASS
6034 10:01:42.423929 RX DATLAT : PASS
6035 10:01:42.424405 RX DQ/DQS(Engine): PASS
6036 10:01:42.427129 TX OE : NO K
6037 10:01:42.427606 All Pass.
6038 10:01:42.427982
6039 10:01:42.430652 CH 1, Rank 0
6040 10:01:42.431120 SW Impedance : PASS
6041 10:01:42.433804 DUTY Scan : NO K
6042 10:01:42.437466 ZQ Calibration : PASS
6043 10:01:42.438057 Jitter Meter : NO K
6044 10:01:42.441000 CBT Training : PASS
6045 10:01:42.443925 Write leveling : PASS
6046 10:01:42.444402 RX DQS gating : PASS
6047 10:01:42.447232 RX DQ/DQS(RDDQC) : PASS
6048 10:01:42.450755 TX DQ/DQS : PASS
6049 10:01:42.451340 RX DATLAT : PASS
6050 10:01:42.454280 RX DQ/DQS(Engine): PASS
6051 10:01:42.454783 TX OE : NO K
6052 10:01:42.457472 All Pass.
6053 10:01:42.458069
6054 10:01:42.458564 CH 1, Rank 1
6055 10:01:42.460787 SW Impedance : PASS
6056 10:01:42.461370 DUTY Scan : NO K
6057 10:01:42.464127 ZQ Calibration : PASS
6058 10:01:42.467888 Jitter Meter : NO K
6059 10:01:42.468473 CBT Training : PASS
6060 10:01:42.470341 Write leveling : PASS
6061 10:01:42.473922 RX DQS gating : PASS
6062 10:01:42.474542 RX DQ/DQS(RDDQC) : PASS
6063 10:01:42.477363 TX DQ/DQS : PASS
6064 10:01:42.480738 RX DATLAT : PASS
6065 10:01:42.481323 RX DQ/DQS(Engine): PASS
6066 10:01:42.483757 TX OE : NO K
6067 10:01:42.484235 All Pass.
6068 10:01:42.484611
6069 10:01:42.487179 DramC Write-DBI off
6070 10:01:42.490569 PER_BANK_REFRESH: Hybrid Mode
6071 10:01:42.491221 TX_TRACKING: ON
6072 10:01:42.500702 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6073 10:01:42.504138 [FAST_K] Save calibration result to emmc
6074 10:01:42.507329 dramc_set_vcore_voltage set vcore to 650000
6075 10:01:42.510858 Read voltage for 400, 6
6076 10:01:42.511335 Vio18 = 0
6077 10:01:42.511712 Vcore = 650000
6078 10:01:42.513507 Vdram = 0
6079 10:01:42.513977 Vddq = 0
6080 10:01:42.514349 Vmddr = 0
6081 10:01:42.520355 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6082 10:01:42.523586 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6083 10:01:42.527332 MEM_TYPE=3, freq_sel=20
6084 10:01:42.530663 sv_algorithm_assistance_LP4_800
6085 10:01:42.533895 ============ PULL DRAM RESETB DOWN ============
6086 10:01:42.537105 ========== PULL DRAM RESETB DOWN end =========
6087 10:01:42.544241 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6088 10:01:42.547449 ===================================
6089 10:01:42.547935 LPDDR4 DRAM CONFIGURATION
6090 10:01:42.550631 ===================================
6091 10:01:42.554300 EX_ROW_EN[0] = 0x0
6092 10:01:42.556916 EX_ROW_EN[1] = 0x0
6093 10:01:42.557382 LP4Y_EN = 0x0
6094 10:01:42.560468 WORK_FSP = 0x0
6095 10:01:42.561042 WL = 0x2
6096 10:01:42.563623 RL = 0x2
6097 10:01:42.564086 BL = 0x2
6098 10:01:42.567088 RPST = 0x0
6099 10:01:42.567657 RD_PRE = 0x0
6100 10:01:42.570549 WR_PRE = 0x1
6101 10:01:42.571118 WR_PST = 0x0
6102 10:01:42.573841 DBI_WR = 0x0
6103 10:01:42.574436 DBI_RD = 0x0
6104 10:01:42.577363 OTF = 0x1
6105 10:01:42.580066 ===================================
6106 10:01:42.583591 ===================================
6107 10:01:42.584062 ANA top config
6108 10:01:42.586621 ===================================
6109 10:01:42.590269 DLL_ASYNC_EN = 0
6110 10:01:42.593963 ALL_SLAVE_EN = 1
6111 10:01:42.594577 NEW_RANK_MODE = 1
6112 10:01:42.596781 DLL_IDLE_MODE = 1
6113 10:01:42.600257 LP45_APHY_COMB_EN = 1
6114 10:01:42.603346 TX_ODT_DIS = 1
6115 10:01:42.606631 NEW_8X_MODE = 1
6116 10:01:42.609993 ===================================
6117 10:01:42.613545 ===================================
6118 10:01:42.616610 data_rate = 800
6119 10:01:42.617186 CKR = 1
6120 10:01:42.619744 DQ_P2S_RATIO = 4
6121 10:01:42.623171 ===================================
6122 10:01:42.626553 CA_P2S_RATIO = 4
6123 10:01:42.630372 DQ_CA_OPEN = 0
6124 10:01:42.633400 DQ_SEMI_OPEN = 1
6125 10:01:42.633865 CA_SEMI_OPEN = 1
6126 10:01:42.636850 CA_FULL_RATE = 0
6127 10:01:42.640283 DQ_CKDIV4_EN = 0
6128 10:01:42.643105 CA_CKDIV4_EN = 1
6129 10:01:42.646685 CA_PREDIV_EN = 0
6130 10:01:42.650193 PH8_DLY = 0
6131 10:01:42.650808 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6132 10:01:42.653514 DQ_AAMCK_DIV = 0
6133 10:01:42.656918 CA_AAMCK_DIV = 0
6134 10:01:42.659963 CA_ADMCK_DIV = 4
6135 10:01:42.663669 DQ_TRACK_CA_EN = 0
6136 10:01:42.666804 CA_PICK = 800
6137 10:01:42.670016 CA_MCKIO = 400
6138 10:01:42.670633 MCKIO_SEMI = 400
6139 10:01:42.673412 PLL_FREQ = 3016
6140 10:01:42.676765 DQ_UI_PI_RATIO = 32
6141 10:01:42.680760 CA_UI_PI_RATIO = 32
6142 10:01:42.683603 ===================================
6143 10:01:42.686942 ===================================
6144 10:01:42.690167 memory_type:LPDDR4
6145 10:01:42.690794 GP_NUM : 10
6146 10:01:42.693685 SRAM_EN : 1
6147 10:01:42.696804 MD32_EN : 0
6148 10:01:42.697373 ===================================
6149 10:01:42.700080 [ANA_INIT] >>>>>>>>>>>>>>
6150 10:01:42.703293 <<<<<< [CONFIGURE PHASE]: ANA_TX
6151 10:01:42.706678 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6152 10:01:42.710181 ===================================
6153 10:01:42.713684 data_rate = 800,PCW = 0X7400
6154 10:01:42.716568 ===================================
6155 10:01:42.720270 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6156 10:01:42.726528 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6157 10:01:42.736649 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6158 10:01:42.740117 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6159 10:01:42.746209 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6160 10:01:42.750124 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6161 10:01:42.750742 [ANA_INIT] flow start
6162 10:01:42.753003 [ANA_INIT] PLL >>>>>>>>
6163 10:01:42.756472 [ANA_INIT] PLL <<<<<<<<
6164 10:01:42.756941 [ANA_INIT] MIDPI >>>>>>>>
6165 10:01:42.760005 [ANA_INIT] MIDPI <<<<<<<<
6166 10:01:42.762962 [ANA_INIT] DLL >>>>>>>>
6167 10:01:42.763557 [ANA_INIT] flow end
6168 10:01:42.766363 ============ LP4 DIFF to SE enter ============
6169 10:01:42.773323 ============ LP4 DIFF to SE exit ============
6170 10:01:42.773892 [ANA_INIT] <<<<<<<<<<<<<
6171 10:01:42.776436 [Flow] Enable top DCM control >>>>>
6172 10:01:42.779739 [Flow] Enable top DCM control <<<<<
6173 10:01:42.783166 Enable DLL master slave shuffle
6174 10:01:42.789737 ==============================================================
6175 10:01:42.790324 Gating Mode config
6176 10:01:42.796431 ==============================================================
6177 10:01:42.799669 Config description:
6178 10:01:42.809893 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6179 10:01:42.816387 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6180 10:01:42.819603 SELPH_MODE 0: By rank 1: By Phase
6181 10:01:42.826126 ==============================================================
6182 10:01:42.829095 GAT_TRACK_EN = 0
6183 10:01:42.832758 RX_GATING_MODE = 2
6184 10:01:42.833348 RX_GATING_TRACK_MODE = 2
6185 10:01:42.835944 SELPH_MODE = 1
6186 10:01:42.839559 PICG_EARLY_EN = 1
6187 10:01:42.842890 VALID_LAT_VALUE = 1
6188 10:01:42.849586 ==============================================================
6189 10:01:42.852815 Enter into Gating configuration >>>>
6190 10:01:42.856251 Exit from Gating configuration <<<<
6191 10:01:42.859032 Enter into DVFS_PRE_config >>>>>
6192 10:01:42.868970 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6193 10:01:42.872547 Exit from DVFS_PRE_config <<<<<
6194 10:01:42.876004 Enter into PICG configuration >>>>
6195 10:01:42.879505 Exit from PICG configuration <<<<
6196 10:01:42.882259 [RX_INPUT] configuration >>>>>
6197 10:01:42.885753 [RX_INPUT] configuration <<<<<
6198 10:01:42.889385 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6199 10:01:42.896041 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6200 10:01:42.902313 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6201 10:01:42.908952 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6202 10:01:42.912106 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6203 10:01:42.919258 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6204 10:01:42.922209 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6205 10:01:42.928629 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6206 10:01:42.932598 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6207 10:01:42.935624 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6208 10:01:42.938619 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6209 10:01:42.945466 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6210 10:01:42.948603 ===================================
6211 10:01:42.949082 LPDDR4 DRAM CONFIGURATION
6212 10:01:42.952197 ===================================
6213 10:01:42.955508 EX_ROW_EN[0] = 0x0
6214 10:01:42.958766 EX_ROW_EN[1] = 0x0
6215 10:01:42.959440 LP4Y_EN = 0x0
6216 10:01:42.962201 WORK_FSP = 0x0
6217 10:01:42.962799 WL = 0x2
6218 10:01:42.965844 RL = 0x2
6219 10:01:42.966452 BL = 0x2
6220 10:01:42.969315 RPST = 0x0
6221 10:01:42.969893 RD_PRE = 0x0
6222 10:01:42.972316 WR_PRE = 0x1
6223 10:01:42.972790 WR_PST = 0x0
6224 10:01:42.975560 DBI_WR = 0x0
6225 10:01:42.976139 DBI_RD = 0x0
6226 10:01:42.978565 OTF = 0x1
6227 10:01:42.981732 ===================================
6228 10:01:42.985349 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6229 10:01:42.988481 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6230 10:01:42.995434 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6231 10:01:42.998581 ===================================
6232 10:01:42.999060 LPDDR4 DRAM CONFIGURATION
6233 10:01:43.001819 ===================================
6234 10:01:43.005413 EX_ROW_EN[0] = 0x10
6235 10:01:43.008769 EX_ROW_EN[1] = 0x0
6236 10:01:43.009241 LP4Y_EN = 0x0
6237 10:01:43.011737 WORK_FSP = 0x0
6238 10:01:43.012235 WL = 0x2
6239 10:01:43.014956 RL = 0x2
6240 10:01:43.015425 BL = 0x2
6241 10:01:43.018447 RPST = 0x0
6242 10:01:43.019023 RD_PRE = 0x0
6243 10:01:43.022329 WR_PRE = 0x1
6244 10:01:43.022951 WR_PST = 0x0
6245 10:01:43.025283 DBI_WR = 0x0
6246 10:01:43.025966 DBI_RD = 0x0
6247 10:01:43.028384 OTF = 0x1
6248 10:01:43.031861 ===================================
6249 10:01:43.038533 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6250 10:01:43.041703 nWR fixed to 30
6251 10:01:43.042335 [ModeRegInit_LP4] CH0 RK0
6252 10:01:43.045237 [ModeRegInit_LP4] CH0 RK1
6253 10:01:43.048497 [ModeRegInit_LP4] CH1 RK0
6254 10:01:43.051592 [ModeRegInit_LP4] CH1 RK1
6255 10:01:43.052160 match AC timing 19
6256 10:01:43.058566 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6257 10:01:43.061810 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6258 10:01:43.064890 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6259 10:01:43.071718 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6260 10:01:43.075196 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6261 10:01:43.075786 ==
6262 10:01:43.078017 Dram Type= 6, Freq= 0, CH_0, rank 0
6263 10:01:43.081696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6264 10:01:43.082193 ==
6265 10:01:43.088378 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6266 10:01:43.094551 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6267 10:01:43.098463 [CA 0] Center 36 (8~64) winsize 57
6268 10:01:43.099046 [CA 1] Center 36 (8~64) winsize 57
6269 10:01:43.101361 [CA 2] Center 36 (8~64) winsize 57
6270 10:01:43.104865 [CA 3] Center 36 (8~64) winsize 57
6271 10:01:43.107778 [CA 4] Center 36 (8~64) winsize 57
6272 10:01:43.111322 [CA 5] Center 36 (8~64) winsize 57
6273 10:01:43.111904
6274 10:01:43.115075 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6275 10:01:43.115551
6276 10:01:43.118653 [CATrainingPosCal] consider 1 rank data
6277 10:01:43.121401 u2DelayCellTimex100 = 270/100 ps
6278 10:01:43.124470 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 10:01:43.131036 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 10:01:43.134641 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 10:01:43.138240 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 10:01:43.141471 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 10:01:43.144556 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 10:01:43.145129
6285 10:01:43.147851 CA PerBit enable=1, Macro0, CA PI delay=36
6286 10:01:43.148319
6287 10:01:43.151724 [CBTSetCACLKResult] CA Dly = 36
6288 10:01:43.152309 CS Dly: 1 (0~32)
6289 10:01:43.154788 ==
6290 10:01:43.157848 Dram Type= 6, Freq= 0, CH_0, rank 1
6291 10:01:43.161621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6292 10:01:43.162203 ==
6293 10:01:43.164755 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6294 10:01:43.171033 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6295 10:01:43.174549 [CA 0] Center 36 (8~64) winsize 57
6296 10:01:43.177957 [CA 1] Center 36 (8~64) winsize 57
6297 10:01:43.181504 [CA 2] Center 36 (8~64) winsize 57
6298 10:01:43.184007 [CA 3] Center 36 (8~64) winsize 57
6299 10:01:43.188065 [CA 4] Center 36 (8~64) winsize 57
6300 10:01:43.190922 [CA 5] Center 36 (8~64) winsize 57
6301 10:01:43.191682
6302 10:01:43.193938 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6303 10:01:43.194441
6304 10:01:43.197538 [CATrainingPosCal] consider 2 rank data
6305 10:01:43.201079 u2DelayCellTimex100 = 270/100 ps
6306 10:01:43.204146 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 10:01:43.207541 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 10:01:43.211065 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 10:01:43.213936 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 10:01:43.220853 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 10:01:43.224132 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 10:01:43.224608
6313 10:01:43.227115 CA PerBit enable=1, Macro0, CA PI delay=36
6314 10:01:43.227590
6315 10:01:43.230577 [CBTSetCACLKResult] CA Dly = 36
6316 10:01:43.231053 CS Dly: 1 (0~32)
6317 10:01:43.231429
6318 10:01:43.234078 ----->DramcWriteLeveling(PI) begin...
6319 10:01:43.234715 ==
6320 10:01:43.237730 Dram Type= 6, Freq= 0, CH_0, rank 0
6321 10:01:43.244390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6322 10:01:43.245013 ==
6323 10:01:43.247465 Write leveling (Byte 0): 40 => 8
6324 10:01:43.248060 Write leveling (Byte 1): 32 => 0
6325 10:01:43.250761 DramcWriteLeveling(PI) end<-----
6326 10:01:43.251324
6327 10:01:43.253803 ==
6328 10:01:43.257304 Dram Type= 6, Freq= 0, CH_0, rank 0
6329 10:01:43.261147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6330 10:01:43.261778 ==
6331 10:01:43.263745 [Gating] SW mode calibration
6332 10:01:43.271195 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6333 10:01:43.274048 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6334 10:01:43.280637 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6335 10:01:43.284167 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6336 10:01:43.287260 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6337 10:01:43.293631 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6338 10:01:43.296779 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6339 10:01:43.300359 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6340 10:01:43.307045 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6341 10:01:43.310268 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6342 10:01:43.313435 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6343 10:01:43.316705 Total UI for P1: 0, mck2ui 16
6344 10:01:43.320376 best dqsien dly found for B0: ( 0, 14, 24)
6345 10:01:43.323513 Total UI for P1: 0, mck2ui 16
6346 10:01:43.326821 best dqsien dly found for B1: ( 0, 14, 24)
6347 10:01:43.330501 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6348 10:01:43.333389 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6349 10:01:43.333863
6350 10:01:43.340535 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6351 10:01:43.343336 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6352 10:01:43.343814 [Gating] SW calibration Done
6353 10:01:43.346939 ==
6354 10:01:43.349966 Dram Type= 6, Freq= 0, CH_0, rank 0
6355 10:01:43.353690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6356 10:01:43.354311 ==
6357 10:01:43.354766 RX Vref Scan: 0
6358 10:01:43.355131
6359 10:01:43.356753 RX Vref 0 -> 0, step: 1
6360 10:01:43.357217
6361 10:01:43.359931 RX Delay -410 -> 252, step: 16
6362 10:01:43.363224 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6363 10:01:43.366730 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6364 10:01:43.373071 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6365 10:01:43.376250 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6366 10:01:43.379651 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6367 10:01:43.383258 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6368 10:01:43.389813 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6369 10:01:43.392961 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6370 10:01:43.396208 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6371 10:01:43.399644 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6372 10:01:43.406625 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6373 10:01:43.409622 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6374 10:01:43.413066 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6375 10:01:43.420003 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6376 10:01:43.422905 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6377 10:01:43.426499 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6378 10:01:43.427051 ==
6379 10:01:43.429661 Dram Type= 6, Freq= 0, CH_0, rank 0
6380 10:01:43.432638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6381 10:01:43.436216 ==
6382 10:01:43.436774 DQS Delay:
6383 10:01:43.437154 DQS0 = 27, DQS1 = 35
6384 10:01:43.439026 DQM Delay:
6385 10:01:43.439484 DQM0 = 11, DQM1 = 6
6386 10:01:43.442578 DQ Delay:
6387 10:01:43.443039 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =0
6388 10:01:43.446088 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6389 10:01:43.449419 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6390 10:01:43.452936 DQ12 =8, DQ13 =8, DQ14 =16, DQ15 =8
6391 10:01:43.453498
6392 10:01:43.453863
6393 10:01:43.454206 ==
6394 10:01:43.455650 Dram Type= 6, Freq= 0, CH_0, rank 0
6395 10:01:43.462503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 10:01:43.463056 ==
6397 10:01:43.463443
6398 10:01:43.463789
6399 10:01:43.464118 TX Vref Scan disable
6400 10:01:43.465395 == TX Byte 0 ==
6401 10:01:43.469187 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6402 10:01:43.472306 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6403 10:01:43.476202 == TX Byte 1 ==
6404 10:01:43.479106 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6405 10:01:43.482280 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6406 10:01:43.485509 ==
6407 10:01:43.489037 Dram Type= 6, Freq= 0, CH_0, rank 0
6408 10:01:43.492571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6409 10:01:43.493038 ==
6410 10:01:43.493482
6411 10:01:43.493843
6412 10:01:43.495445 TX Vref Scan disable
6413 10:01:43.495972 == TX Byte 0 ==
6414 10:01:43.498941 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6415 10:01:43.505485 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6416 10:01:43.505950 == TX Byte 1 ==
6417 10:01:43.509032 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6418 10:01:43.515371 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6419 10:01:43.515980
6420 10:01:43.516367 [DATLAT]
6421 10:01:43.516717 Freq=400, CH0 RK0
6422 10:01:43.518556
6423 10:01:43.519105 DATLAT Default: 0xf
6424 10:01:43.522073 0, 0xFFFF, sum = 0
6425 10:01:43.522696 1, 0xFFFF, sum = 0
6426 10:01:43.525304 2, 0xFFFF, sum = 0
6427 10:01:43.525864 3, 0xFFFF, sum = 0
6428 10:01:43.528776 4, 0xFFFF, sum = 0
6429 10:01:43.529338 5, 0xFFFF, sum = 0
6430 10:01:43.532104 6, 0xFFFF, sum = 0
6431 10:01:43.532606 7, 0xFFFF, sum = 0
6432 10:01:43.535085 8, 0xFFFF, sum = 0
6433 10:01:43.535551 9, 0xFFFF, sum = 0
6434 10:01:43.538521 10, 0xFFFF, sum = 0
6435 10:01:43.539086 11, 0xFFFF, sum = 0
6436 10:01:43.541778 12, 0xFFFF, sum = 0
6437 10:01:43.542509 13, 0x0, sum = 1
6438 10:01:43.545007 14, 0x0, sum = 2
6439 10:01:43.545474 15, 0x0, sum = 3
6440 10:01:43.548584 16, 0x0, sum = 4
6441 10:01:43.549054 best_step = 14
6442 10:01:43.549419
6443 10:01:43.549761 ==
6444 10:01:43.551860 Dram Type= 6, Freq= 0, CH_0, rank 0
6445 10:01:43.558211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6446 10:01:43.558795 ==
6447 10:01:43.559253 RX Vref Scan: 1
6448 10:01:43.559608
6449 10:01:43.561578 RX Vref 0 -> 0, step: 1
6450 10:01:43.562060
6451 10:01:43.564655 RX Delay -311 -> 252, step: 8
6452 10:01:43.565119
6453 10:01:43.568331 Set Vref, RX VrefLevel [Byte0]: 58
6454 10:01:43.571557 [Byte1]: 50
6455 10:01:43.572117
6456 10:01:43.575022 Final RX Vref Byte 0 = 58 to rank0
6457 10:01:43.578078 Final RX Vref Byte 1 = 50 to rank0
6458 10:01:43.581809 Final RX Vref Byte 0 = 58 to rank1
6459 10:01:43.584650 Final RX Vref Byte 1 = 50 to rank1==
6460 10:01:43.588087 Dram Type= 6, Freq= 0, CH_0, rank 0
6461 10:01:43.591539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6462 10:01:43.594884 ==
6463 10:01:43.595351 DQS Delay:
6464 10:01:43.595719 DQS0 = 28, DQS1 = 48
6465 10:01:43.598927 DQM Delay:
6466 10:01:43.599484 DQM0 = 12, DQM1 = 15
6467 10:01:43.601723 DQ Delay:
6468 10:01:43.602278 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6469 10:01:43.604535 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6470 10:01:43.608272 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6471 10:01:43.611050 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6472 10:01:43.611514
6473 10:01:43.611881
6474 10:01:43.621331 [DQSOSCAuto] RK0, (LSB)MR18= 0xa89f, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6475 10:01:43.625037 CH0 RK0: MR19=C0C, MR18=A89F
6476 10:01:43.631092 CH0_RK0: MR19=0xC0C, MR18=0xA89F, DQSOSC=388, MR23=63, INC=392, DEC=261
6477 10:01:43.631779 ==
6478 10:01:43.634956 Dram Type= 6, Freq= 0, CH_0, rank 1
6479 10:01:43.638122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 10:01:43.638717 ==
6481 10:01:43.641149 [Gating] SW mode calibration
6482 10:01:43.647786 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6483 10:01:43.651531 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6484 10:01:43.657869 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6485 10:01:43.660946 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6486 10:01:43.664800 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6487 10:01:43.671242 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6488 10:01:43.674132 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6489 10:01:43.677671 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6490 10:01:43.684180 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6491 10:01:43.687572 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6492 10:01:43.690871 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6493 10:01:43.694175 Total UI for P1: 0, mck2ui 16
6494 10:01:43.697849 best dqsien dly found for B0: ( 0, 14, 24)
6495 10:01:43.701075 Total UI for P1: 0, mck2ui 16
6496 10:01:43.704321 best dqsien dly found for B1: ( 0, 14, 24)
6497 10:01:43.707923 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6498 10:01:43.711054 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6499 10:01:43.711601
6500 10:01:43.717782 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6501 10:01:43.721224 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6502 10:01:43.721783 [Gating] SW calibration Done
6503 10:01:43.724460 ==
6504 10:01:43.727710 Dram Type= 6, Freq= 0, CH_0, rank 1
6505 10:01:43.730928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6506 10:01:43.731398 ==
6507 10:01:43.731763 RX Vref Scan: 0
6508 10:01:43.732105
6509 10:01:43.734548 RX Vref 0 -> 0, step: 1
6510 10:01:43.735015
6511 10:01:43.737867 RX Delay -410 -> 252, step: 16
6512 10:01:43.740973 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6513 10:01:43.747773 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6514 10:01:43.750930 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6515 10:01:43.753932 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6516 10:01:43.757235 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6517 10:01:43.764179 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6518 10:01:43.767184 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6519 10:01:43.771246 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6520 10:01:43.774288 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6521 10:01:43.780346 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6522 10:01:43.783729 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6523 10:01:43.787022 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6524 10:01:43.790611 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6525 10:01:43.797422 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6526 10:01:43.800370 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6527 10:01:43.803729 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6528 10:01:43.804291 ==
6529 10:01:43.807225 Dram Type= 6, Freq= 0, CH_0, rank 1
6530 10:01:43.813572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6531 10:01:43.814132 ==
6532 10:01:43.814535 DQS Delay:
6533 10:01:43.816989 DQS0 = 27, DQS1 = 43
6534 10:01:43.817514 DQM Delay:
6535 10:01:43.818059 DQM0 = 9, DQM1 = 15
6536 10:01:43.820062 DQ Delay:
6537 10:01:43.820618 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6538 10:01:43.823618 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6539 10:01:43.826624 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6540 10:01:43.830284 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6541 10:01:43.830799
6542 10:01:43.831175
6543 10:01:43.833459 ==
6544 10:01:43.836561 Dram Type= 6, Freq= 0, CH_0, rank 1
6545 10:01:43.840318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6546 10:01:43.840907 ==
6547 10:01:43.841291
6548 10:01:43.841642
6549 10:01:43.843939 TX Vref Scan disable
6550 10:01:43.844510 == TX Byte 0 ==
6551 10:01:43.846900 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6552 10:01:43.853642 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6553 10:01:43.854219 == TX Byte 1 ==
6554 10:01:43.856708 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6555 10:01:43.860428 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6556 10:01:43.863726 ==
6557 10:01:43.866893 Dram Type= 6, Freq= 0, CH_0, rank 1
6558 10:01:43.869826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6559 10:01:43.870435 ==
6560 10:01:43.870929
6561 10:01:43.871378
6562 10:01:43.873313 TX Vref Scan disable
6563 10:01:43.873905 == TX Byte 0 ==
6564 10:01:43.876205 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6565 10:01:43.883007 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6566 10:01:43.883598 == TX Byte 1 ==
6567 10:01:43.886453 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6568 10:01:43.893321 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6569 10:01:43.893807
6570 10:01:43.894287 [DATLAT]
6571 10:01:43.894776 Freq=400, CH0 RK1
6572 10:01:43.895223
6573 10:01:43.896327 DATLAT Default: 0xe
6574 10:01:43.896808 0, 0xFFFF, sum = 0
6575 10:01:43.899884 1, 0xFFFF, sum = 0
6576 10:01:43.902948 2, 0xFFFF, sum = 0
6577 10:01:43.903538 3, 0xFFFF, sum = 0
6578 10:01:43.906367 4, 0xFFFF, sum = 0
6579 10:01:43.906882 5, 0xFFFF, sum = 0
6580 10:01:43.909766 6, 0xFFFF, sum = 0
6581 10:01:43.910357 7, 0xFFFF, sum = 0
6582 10:01:43.913408 8, 0xFFFF, sum = 0
6583 10:01:43.913997 9, 0xFFFF, sum = 0
6584 10:01:43.916332 10, 0xFFFF, sum = 0
6585 10:01:43.916822 11, 0xFFFF, sum = 0
6586 10:01:43.919641 12, 0xFFFF, sum = 0
6587 10:01:43.920129 13, 0x0, sum = 1
6588 10:01:43.922691 14, 0x0, sum = 2
6589 10:01:43.923176 15, 0x0, sum = 3
6590 10:01:43.926429 16, 0x0, sum = 4
6591 10:01:43.926925 best_step = 14
6592 10:01:43.927404
6593 10:01:43.927854 ==
6594 10:01:43.929268 Dram Type= 6, Freq= 0, CH_0, rank 1
6595 10:01:43.932832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6596 10:01:43.936348 ==
6597 10:01:43.936929 RX Vref Scan: 0
6598 10:01:43.937417
6599 10:01:43.940052 RX Vref 0 -> 0, step: 1
6600 10:01:43.940637
6601 10:01:43.943036 RX Delay -327 -> 252, step: 8
6602 10:01:43.946148 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6603 10:01:43.952746 iDelay=217, Bit 1, Center -20 (-247 ~ 208) 456
6604 10:01:43.956183 iDelay=217, Bit 2, Center -20 (-239 ~ 200) 440
6605 10:01:43.959496 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6606 10:01:43.962597 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6607 10:01:43.969318 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6608 10:01:43.973129 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6609 10:01:43.976295 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6610 10:01:43.979127 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6611 10:01:43.986083 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6612 10:01:43.989068 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6613 10:01:43.992466 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6614 10:01:43.995705 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6615 10:01:44.002598 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6616 10:01:44.005999 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6617 10:01:44.009280 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6618 10:01:44.009871 ==
6619 10:01:44.012568 Dram Type= 6, Freq= 0, CH_0, rank 1
6620 10:01:44.019085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6621 10:01:44.019646 ==
6622 10:01:44.020032 DQS Delay:
6623 10:01:44.022576 DQS0 = 28, DQS1 = 44
6624 10:01:44.023041 DQM Delay:
6625 10:01:44.023444 DQM0 = 9, DQM1 = 16
6626 10:01:44.025607 DQ Delay:
6627 10:01:44.028789 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =4
6628 10:01:44.029264 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6629 10:01:44.032447 DQ8 =12, DQ9 =0, DQ10 =16, DQ11 =12
6630 10:01:44.035847 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6631 10:01:44.036740
6632 10:01:44.039167
6633 10:01:44.045641 [DQSOSCAuto] RK1, (LSB)MR18= 0xb86d, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 386 ps
6634 10:01:44.049473 CH0 RK1: MR19=C0C, MR18=B86D
6635 10:01:44.055818 CH0_RK1: MR19=0xC0C, MR18=0xB86D, DQSOSC=386, MR23=63, INC=396, DEC=264
6636 10:01:44.059163 [RxdqsGatingPostProcess] freq 400
6637 10:01:44.062725 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6638 10:01:44.065981 best DQS0 dly(2T, 0.5T) = (0, 10)
6639 10:01:44.069788 best DQS1 dly(2T, 0.5T) = (0, 10)
6640 10:01:44.072816 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6641 10:01:44.075910 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6642 10:01:44.079533 best DQS0 dly(2T, 0.5T) = (0, 10)
6643 10:01:44.082554 best DQS1 dly(2T, 0.5T) = (0, 10)
6644 10:01:44.085886 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6645 10:01:44.088855 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6646 10:01:44.092393 Pre-setting of DQS Precalculation
6647 10:01:44.096004 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6648 10:01:44.096446 ==
6649 10:01:44.099514 Dram Type= 6, Freq= 0, CH_1, rank 0
6650 10:01:44.102685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6651 10:01:44.105880 ==
6652 10:01:44.109354 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6653 10:01:44.116192 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6654 10:01:44.119311 [CA 0] Center 36 (8~64) winsize 57
6655 10:01:44.122741 [CA 1] Center 36 (8~64) winsize 57
6656 10:01:44.125956 [CA 2] Center 36 (8~64) winsize 57
6657 10:01:44.129351 [CA 3] Center 36 (8~64) winsize 57
6658 10:01:44.132426 [CA 4] Center 36 (8~64) winsize 57
6659 10:01:44.136117 [CA 5] Center 36 (8~64) winsize 57
6660 10:01:44.136657
6661 10:01:44.139768 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6662 10:01:44.140307
6663 10:01:44.142335 [CATrainingPosCal] consider 1 rank data
6664 10:01:44.145991 u2DelayCellTimex100 = 270/100 ps
6665 10:01:44.149432 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 10:01:44.152508 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 10:01:44.155439 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 10:01:44.158968 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 10:01:44.162291 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 10:01:44.165596 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 10:01:44.166138
6672 10:01:44.172551 CA PerBit enable=1, Macro0, CA PI delay=36
6673 10:01:44.173090
6674 10:01:44.173537 [CBTSetCACLKResult] CA Dly = 36
6675 10:01:44.175853 CS Dly: 1 (0~32)
6676 10:01:44.176396 ==
6677 10:01:44.179125 Dram Type= 6, Freq= 0, CH_1, rank 1
6678 10:01:44.182028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6679 10:01:44.182600 ==
6680 10:01:44.188971 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6681 10:01:44.195176 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6682 10:01:44.198727 [CA 0] Center 36 (8~64) winsize 57
6683 10:01:44.201988 [CA 1] Center 36 (8~64) winsize 57
6684 10:01:44.205508 [CA 2] Center 36 (8~64) winsize 57
6685 10:01:44.206053 [CA 3] Center 36 (8~64) winsize 57
6686 10:01:44.208917 [CA 4] Center 36 (8~64) winsize 57
6687 10:01:44.211946 [CA 5] Center 36 (8~64) winsize 57
6688 10:01:44.212389
6689 10:01:44.218431 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6690 10:01:44.219031
6691 10:01:44.222185 [CATrainingPosCal] consider 2 rank data
6692 10:01:44.225012 u2DelayCellTimex100 = 270/100 ps
6693 10:01:44.228339 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 10:01:44.231906 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 10:01:44.234883 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 10:01:44.238623 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 10:01:44.241637 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 10:01:44.245218 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 10:01:44.245786
6700 10:01:44.248749 CA PerBit enable=1, Macro0, CA PI delay=36
6701 10:01:44.249317
6702 10:01:44.251777 [CBTSetCACLKResult] CA Dly = 36
6703 10:01:44.255217 CS Dly: 1 (0~32)
6704 10:01:44.255785
6705 10:01:44.258215 ----->DramcWriteLeveling(PI) begin...
6706 10:01:44.258824 ==
6707 10:01:44.261401 Dram Type= 6, Freq= 0, CH_1, rank 0
6708 10:01:44.264397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6709 10:01:44.264877 ==
6710 10:01:44.268590 Write leveling (Byte 0): 40 => 8
6711 10:01:44.271473 Write leveling (Byte 1): 32 => 0
6712 10:01:44.274652 DramcWriteLeveling(PI) end<-----
6713 10:01:44.275218
6714 10:01:44.275597 ==
6715 10:01:44.277952 Dram Type= 6, Freq= 0, CH_1, rank 0
6716 10:01:44.281423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6717 10:01:44.281993 ==
6718 10:01:44.285111 [Gating] SW mode calibration
6719 10:01:44.291759 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6720 10:01:44.298069 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6721 10:01:44.301172 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6722 10:01:44.304428 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6723 10:01:44.311109 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6724 10:01:44.314517 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6725 10:01:44.317529 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6726 10:01:44.323942 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6727 10:01:44.327694 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6728 10:01:44.330918 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6729 10:01:44.337415 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6730 10:01:44.341111 Total UI for P1: 0, mck2ui 16
6731 10:01:44.343924 best dqsien dly found for B0: ( 0, 14, 24)
6732 10:01:44.347359 Total UI for P1: 0, mck2ui 16
6733 10:01:44.351040 best dqsien dly found for B1: ( 0, 14, 24)
6734 10:01:44.354216 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6735 10:01:44.357200 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6736 10:01:44.357772
6737 10:01:44.360614 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6738 10:01:44.363779 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6739 10:01:44.367432 [Gating] SW calibration Done
6740 10:01:44.367997 ==
6741 10:01:44.371018 Dram Type= 6, Freq= 0, CH_1, rank 0
6742 10:01:44.373819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6743 10:01:44.374418 ==
6744 10:01:44.377132 RX Vref Scan: 0
6745 10:01:44.377691
6746 10:01:44.380724 RX Vref 0 -> 0, step: 1
6747 10:01:44.381297
6748 10:01:44.381677 RX Delay -410 -> 252, step: 16
6749 10:01:44.387260 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6750 10:01:44.390620 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6751 10:01:44.393913 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6752 10:01:44.396990 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6753 10:01:44.404333 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6754 10:01:44.407648 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6755 10:01:44.410656 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6756 10:01:44.413856 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6757 10:01:44.420465 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6758 10:01:44.423687 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6759 10:01:44.427288 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6760 10:01:44.430480 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6761 10:01:44.437427 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6762 10:01:44.440189 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6763 10:01:44.443688 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6764 10:01:44.450465 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6765 10:01:44.451033 ==
6766 10:01:44.453933 Dram Type= 6, Freq= 0, CH_1, rank 0
6767 10:01:44.457426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6768 10:01:44.457999 ==
6769 10:01:44.458381 DQS Delay:
6770 10:01:44.460452 DQS0 = 27, DQS1 = 43
6771 10:01:44.460920 DQM Delay:
6772 10:01:44.463864 DQM0 = 7, DQM1 = 17
6773 10:01:44.464461 DQ Delay:
6774 10:01:44.467127 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6775 10:01:44.470590 DQ4 =8, DQ5 =8, DQ6 =16, DQ7 =0
6776 10:01:44.474417 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6777 10:01:44.476813 DQ12 =32, DQ13 =32, DQ14 =16, DQ15 =24
6778 10:01:44.477389
6779 10:01:44.477769
6780 10:01:44.478117 ==
6781 10:01:44.480098 Dram Type= 6, Freq= 0, CH_1, rank 0
6782 10:01:44.483477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 10:01:44.484052 ==
6784 10:01:44.484428
6785 10:01:44.484778
6786 10:01:44.486607 TX Vref Scan disable
6787 10:01:44.487083 == TX Byte 0 ==
6788 10:01:44.493585 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6789 10:01:44.496738 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6790 10:01:44.497219 == TX Byte 1 ==
6791 10:01:44.503556 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6792 10:01:44.507000 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6793 10:01:44.507571 ==
6794 10:01:44.509877 Dram Type= 6, Freq= 0, CH_1, rank 0
6795 10:01:44.513700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6796 10:01:44.514275 ==
6797 10:01:44.514716
6798 10:01:44.515072
6799 10:01:44.516699 TX Vref Scan disable
6800 10:01:44.520378 == TX Byte 0 ==
6801 10:01:44.523385 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6802 10:01:44.526835 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6803 10:01:44.530088 == TX Byte 1 ==
6804 10:01:44.533074 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6805 10:01:44.536707 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6806 10:01:44.537281
6807 10:01:44.537656 [DATLAT]
6808 10:01:44.539944 Freq=400, CH1 RK0
6809 10:01:44.540422
6810 10:01:44.540798 DATLAT Default: 0xf
6811 10:01:44.543162 0, 0xFFFF, sum = 0
6812 10:01:44.543646 1, 0xFFFF, sum = 0
6813 10:01:44.546459 2, 0xFFFF, sum = 0
6814 10:01:44.549882 3, 0xFFFF, sum = 0
6815 10:01:44.550577 4, 0xFFFF, sum = 0
6816 10:01:44.553034 5, 0xFFFF, sum = 0
6817 10:01:44.553515 6, 0xFFFF, sum = 0
6818 10:01:44.556943 7, 0xFFFF, sum = 0
6819 10:01:44.557521 8, 0xFFFF, sum = 0
6820 10:01:44.559905 9, 0xFFFF, sum = 0
6821 10:01:44.560483 10, 0xFFFF, sum = 0
6822 10:01:44.563299 11, 0xFFFF, sum = 0
6823 10:01:44.563878 12, 0xFFFF, sum = 0
6824 10:01:44.566544 13, 0x0, sum = 1
6825 10:01:44.567123 14, 0x0, sum = 2
6826 10:01:44.569819 15, 0x0, sum = 3
6827 10:01:44.570418 16, 0x0, sum = 4
6828 10:01:44.573244 best_step = 14
6829 10:01:44.573816
6830 10:01:44.574192 ==
6831 10:01:44.576577 Dram Type= 6, Freq= 0, CH_1, rank 0
6832 10:01:44.579787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6833 10:01:44.580365 ==
6834 10:01:44.580747 RX Vref Scan: 1
6835 10:01:44.583538
6836 10:01:44.584111 RX Vref 0 -> 0, step: 1
6837 10:01:44.584492
6838 10:01:44.586301 RX Delay -327 -> 252, step: 8
6839 10:01:44.586811
6840 10:01:44.589634 Set Vref, RX VrefLevel [Byte0]: 54
6841 10:01:44.592823 [Byte1]: 58
6842 10:01:44.596718
6843 10:01:44.597188 Final RX Vref Byte 0 = 54 to rank0
6844 10:01:44.600088 Final RX Vref Byte 1 = 58 to rank0
6845 10:01:44.603411 Final RX Vref Byte 0 = 54 to rank1
6846 10:01:44.607071 Final RX Vref Byte 1 = 58 to rank1==
6847 10:01:44.610231 Dram Type= 6, Freq= 0, CH_1, rank 0
6848 10:01:44.616761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6849 10:01:44.617343 ==
6850 10:01:44.617725 DQS Delay:
6851 10:01:44.620308 DQS0 = 28, DQS1 = 40
6852 10:01:44.620781 DQM Delay:
6853 10:01:44.621412 DQM0 = 8, DQM1 = 12
6854 10:01:44.623714 DQ Delay:
6855 10:01:44.627115 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6856 10:01:44.627592 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6857 10:01:44.630428 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6858 10:01:44.633502 DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =16
6859 10:01:44.633975
6860 10:01:44.634523
6861 10:01:44.643724 [DQSOSCAuto] RK0, (LSB)MR18= 0x95cf, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6862 10:01:44.646715 CH1 RK0: MR19=C0C, MR18=95CF
6863 10:01:44.653089 CH1_RK0: MR19=0xC0C, MR18=0x95CF, DQSOSC=384, MR23=63, INC=400, DEC=267
6864 10:01:44.653641 ==
6865 10:01:44.657305 Dram Type= 6, Freq= 0, CH_1, rank 1
6866 10:01:44.660418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 10:01:44.660899 ==
6868 10:01:44.664098 [Gating] SW mode calibration
6869 10:01:44.670450 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6870 10:01:44.673806 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6871 10:01:44.680050 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6872 10:01:44.684097 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6873 10:01:44.686990 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6874 10:01:44.693719 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6875 10:01:44.696730 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6876 10:01:44.700527 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6877 10:01:44.706848 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6878 10:01:44.710550 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6879 10:01:44.714216 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6880 10:01:44.716727 Total UI for P1: 0, mck2ui 16
6881 10:01:44.720066 best dqsien dly found for B0: ( 0, 14, 24)
6882 10:01:44.723363 Total UI for P1: 0, mck2ui 16
6883 10:01:44.726323 best dqsien dly found for B1: ( 0, 14, 24)
6884 10:01:44.729957 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6885 10:01:44.732941 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6886 10:01:44.733418
6887 10:01:44.740084 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6888 10:01:44.743455 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6889 10:01:44.746759 [Gating] SW calibration Done
6890 10:01:44.747331 ==
6891 10:01:44.750554 Dram Type= 6, Freq= 0, CH_1, rank 1
6892 10:01:44.753450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6893 10:01:44.753928 ==
6894 10:01:44.754307 RX Vref Scan: 0
6895 10:01:44.754707
6896 10:01:44.757201 RX Vref 0 -> 0, step: 1
6897 10:01:44.757786
6898 10:01:44.759862 RX Delay -410 -> 252, step: 16
6899 10:01:44.763141 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6900 10:01:44.766624 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6901 10:01:44.773551 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6902 10:01:44.776528 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6903 10:01:44.780140 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6904 10:01:44.783644 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6905 10:01:44.789968 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6906 10:01:44.793373 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6907 10:01:44.796471 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6908 10:01:44.800162 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6909 10:01:44.806991 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6910 10:01:44.810049 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6911 10:01:44.813408 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6912 10:01:44.820103 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6913 10:01:44.823442 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6914 10:01:44.826420 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6915 10:01:44.826986 ==
6916 10:01:44.829851 Dram Type= 6, Freq= 0, CH_1, rank 1
6917 10:01:44.833032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6918 10:01:44.833512 ==
6919 10:01:44.836768 DQS Delay:
6920 10:01:44.837331 DQS0 = 35, DQS1 = 43
6921 10:01:44.840152 DQM Delay:
6922 10:01:44.840724 DQM0 = 16, DQM1 = 18
6923 10:01:44.841110 DQ Delay:
6924 10:01:44.843123 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6925 10:01:44.846791 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6926 10:01:44.850146 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6927 10:01:44.853175 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6928 10:01:44.853741
6929 10:01:44.854115
6930 10:01:44.854509 ==
6931 10:01:44.856944 Dram Type= 6, Freq= 0, CH_1, rank 1
6932 10:01:44.862962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6933 10:01:44.863515 ==
6934 10:01:44.863894
6935 10:01:44.864244
6936 10:01:44.866699 TX Vref Scan disable
6937 10:01:44.867258 == TX Byte 0 ==
6938 10:01:44.869937 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6939 10:01:44.873617 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6940 10:01:44.876490 == TX Byte 1 ==
6941 10:01:44.879924 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6942 10:01:44.883195 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6943 10:01:44.886545 ==
6944 10:01:44.889572 Dram Type= 6, Freq= 0, CH_1, rank 1
6945 10:01:44.893435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6946 10:01:44.894014 ==
6947 10:01:44.894426
6948 10:01:44.894788
6949 10:01:44.896173 TX Vref Scan disable
6950 10:01:44.896696 == TX Byte 0 ==
6951 10:01:44.899611 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6952 10:01:44.906660 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6953 10:01:44.907243 == TX Byte 1 ==
6954 10:01:44.910053 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6955 10:01:44.913039 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6956 10:01:44.916292
6957 10:01:44.916862 [DATLAT]
6958 10:01:44.917241 Freq=400, CH1 RK1
6959 10:01:44.917597
6960 10:01:44.919814 DATLAT Default: 0xe
6961 10:01:44.920380 0, 0xFFFF, sum = 0
6962 10:01:44.923142 1, 0xFFFF, sum = 0
6963 10:01:44.923779 2, 0xFFFF, sum = 0
6964 10:01:44.926330 3, 0xFFFF, sum = 0
6965 10:01:44.929494 4, 0xFFFF, sum = 0
6966 10:01:44.930188 5, 0xFFFF, sum = 0
6967 10:01:44.932726 6, 0xFFFF, sum = 0
6968 10:01:44.933236 7, 0xFFFF, sum = 0
6969 10:01:44.936209 8, 0xFFFF, sum = 0
6970 10:01:44.936826 9, 0xFFFF, sum = 0
6971 10:01:44.939308 10, 0xFFFF, sum = 0
6972 10:01:44.939792 11, 0xFFFF, sum = 0
6973 10:01:44.942917 12, 0xFFFF, sum = 0
6974 10:01:44.943501 13, 0x0, sum = 1
6975 10:01:44.945840 14, 0x0, sum = 2
6976 10:01:44.946321 15, 0x0, sum = 3
6977 10:01:44.949772 16, 0x0, sum = 4
6978 10:01:44.950350 best_step = 14
6979 10:01:44.950767
6980 10:01:44.951121 ==
6981 10:01:44.952942 Dram Type= 6, Freq= 0, CH_1, rank 1
6982 10:01:44.956472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6983 10:01:44.957051 ==
6984 10:01:44.959459 RX Vref Scan: 0
6985 10:01:44.960030
6986 10:01:44.962496 RX Vref 0 -> 0, step: 1
6987 10:01:44.962970
6988 10:01:44.963346 RX Delay -327 -> 252, step: 8
6989 10:01:44.971471 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6990 10:01:44.975313 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6991 10:01:44.978553 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6992 10:01:44.981455 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6993 10:01:44.988130 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6994 10:01:44.991738 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6995 10:01:44.994511 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6996 10:01:44.998198 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6997 10:01:45.004622 iDelay=217, Bit 8, Center -40 (-271 ~ 192) 464
6998 10:01:45.007888 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6999 10:01:45.011156 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
7000 10:01:45.014549 iDelay=217, Bit 11, Center -32 (-263 ~ 200) 464
7001 10:01:45.021304 iDelay=217, Bit 12, Center -16 (-247 ~ 216) 464
7002 10:01:45.024278 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
7003 10:01:45.027704 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
7004 10:01:45.034504 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
7005 10:01:45.034976 ==
7006 10:01:45.037987 Dram Type= 6, Freq= 0, CH_1, rank 1
7007 10:01:45.041682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7008 10:01:45.042257 ==
7009 10:01:45.042695 DQS Delay:
7010 10:01:45.044346 DQS0 = 32, DQS1 = 40
7011 10:01:45.044817 DQM Delay:
7012 10:01:45.047728 DQM0 = 12, DQM1 = 15
7013 10:01:45.048198 DQ Delay:
7014 10:01:45.051412 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
7015 10:01:45.054652 DQ4 =16, DQ5 =20, DQ6 =16, DQ7 =8
7016 10:01:45.057922 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =8
7017 10:01:45.061308 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
7018 10:01:45.061881
7019 10:01:45.062258
7020 10:01:45.067683 [DQSOSCAuto] RK1, (LSB)MR18= 0xaa53, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
7021 10:01:45.071014 CH1 RK1: MR19=C0C, MR18=AA53
7022 10:01:45.077555 CH1_RK1: MR19=0xC0C, MR18=0xAA53, DQSOSC=388, MR23=63, INC=392, DEC=261
7023 10:01:45.080929 [RxdqsGatingPostProcess] freq 400
7024 10:01:45.087337 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7025 10:01:45.090817 best DQS0 dly(2T, 0.5T) = (0, 10)
7026 10:01:45.091248 best DQS1 dly(2T, 0.5T) = (0, 10)
7027 10:01:45.094067 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7028 10:01:45.097392 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7029 10:01:45.101145 best DQS0 dly(2T, 0.5T) = (0, 10)
7030 10:01:45.104395 best DQS1 dly(2T, 0.5T) = (0, 10)
7031 10:01:45.108293 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7032 10:01:45.111186 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7033 10:01:45.114270 Pre-setting of DQS Precalculation
7034 10:01:45.121115 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7035 10:01:45.127577 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7036 10:01:45.133842 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7037 10:01:45.134273
7038 10:01:45.134650
7039 10:01:45.137374 [Calibration Summary] 800 Mbps
7040 10:01:45.137905 CH 0, Rank 0
7041 10:01:45.141290 SW Impedance : PASS
7042 10:01:45.144113 DUTY Scan : NO K
7043 10:01:45.144638 ZQ Calibration : PASS
7044 10:01:45.147338 Jitter Meter : NO K
7045 10:01:45.147868 CBT Training : PASS
7046 10:01:45.150403 Write leveling : PASS
7047 10:01:45.153749 RX DQS gating : PASS
7048 10:01:45.154175 RX DQ/DQS(RDDQC) : PASS
7049 10:01:45.157257 TX DQ/DQS : PASS
7050 10:01:45.160768 RX DATLAT : PASS
7051 10:01:45.161410 RX DQ/DQS(Engine): PASS
7052 10:01:45.164474 TX OE : NO K
7053 10:01:45.165005 All Pass.
7054 10:01:45.165348
7055 10:01:45.167068 CH 0, Rank 1
7056 10:01:45.167494 SW Impedance : PASS
7057 10:01:45.170538 DUTY Scan : NO K
7058 10:01:45.174058 ZQ Calibration : PASS
7059 10:01:45.174625 Jitter Meter : NO K
7060 10:01:45.177332 CBT Training : PASS
7061 10:01:45.181047 Write leveling : NO K
7062 10:01:45.181584 RX DQS gating : PASS
7063 10:01:45.183974 RX DQ/DQS(RDDQC) : PASS
7064 10:01:45.187313 TX DQ/DQS : PASS
7065 10:01:45.187847 RX DATLAT : PASS
7066 10:01:45.190788 RX DQ/DQS(Engine): PASS
7067 10:01:45.191363 TX OE : NO K
7068 10:01:45.194262 All Pass.
7069 10:01:45.194829
7070 10:01:45.195176 CH 1, Rank 0
7071 10:01:45.196993 SW Impedance : PASS
7072 10:01:45.197419 DUTY Scan : NO K
7073 10:01:45.200409 ZQ Calibration : PASS
7074 10:01:45.203809 Jitter Meter : NO K
7075 10:01:45.204235 CBT Training : PASS
7076 10:01:45.207267 Write leveling : PASS
7077 10:01:45.210746 RX DQS gating : PASS
7078 10:01:45.211290 RX DQ/DQS(RDDQC) : PASS
7079 10:01:45.213937 TX DQ/DQS : PASS
7080 10:01:45.217651 RX DATLAT : PASS
7081 10:01:45.218181 RX DQ/DQS(Engine): PASS
7082 10:01:45.220360 TX OE : NO K
7083 10:01:45.220789 All Pass.
7084 10:01:45.221125
7085 10:01:45.223677 CH 1, Rank 1
7086 10:01:45.224102 SW Impedance : PASS
7087 10:01:45.227037 DUTY Scan : NO K
7088 10:01:45.230251 ZQ Calibration : PASS
7089 10:01:45.230716 Jitter Meter : NO K
7090 10:01:45.233670 CBT Training : PASS
7091 10:01:45.237250 Write leveling : NO K
7092 10:01:45.237778 RX DQS gating : PASS
7093 10:01:45.240611 RX DQ/DQS(RDDQC) : PASS
7094 10:01:45.241140 TX DQ/DQS : PASS
7095 10:01:45.243841 RX DATLAT : PASS
7096 10:01:45.247409 RX DQ/DQS(Engine): PASS
7097 10:01:45.247936 TX OE : NO K
7098 10:01:45.250158 All Pass.
7099 10:01:45.250623
7100 10:01:45.250961 DramC Write-DBI off
7101 10:01:45.253828 PER_BANK_REFRESH: Hybrid Mode
7102 10:01:45.257340 TX_TRACKING: ON
7103 10:01:45.264026 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7104 10:01:45.267191 [FAST_K] Save calibration result to emmc
7105 10:01:45.270752 dramc_set_vcore_voltage set vcore to 725000
7106 10:01:45.274064 Read voltage for 1600, 0
7107 10:01:45.274632 Vio18 = 0
7108 10:01:45.277571 Vcore = 725000
7109 10:01:45.278090 Vdram = 0
7110 10:01:45.278460 Vddq = 0
7111 10:01:45.280348 Vmddr = 0
7112 10:01:45.283922 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7113 10:01:45.290313 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7114 10:01:45.290873 MEM_TYPE=3, freq_sel=13
7115 10:01:45.293836 sv_algorithm_assistance_LP4_3733
7116 10:01:45.300839 ============ PULL DRAM RESETB DOWN ============
7117 10:01:45.303658 ========== PULL DRAM RESETB DOWN end =========
7118 10:01:45.307158 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7119 10:01:45.310643 ===================================
7120 10:01:45.313507 LPDDR4 DRAM CONFIGURATION
7121 10:01:45.317117 ===================================
7122 10:01:45.320556 EX_ROW_EN[0] = 0x0
7123 10:01:45.321089 EX_ROW_EN[1] = 0x0
7124 10:01:45.323806 LP4Y_EN = 0x0
7125 10:01:45.324333 WORK_FSP = 0x1
7126 10:01:45.327036 WL = 0x5
7127 10:01:45.327461 RL = 0x5
7128 10:01:45.330224 BL = 0x2
7129 10:01:45.330787 RPST = 0x0
7130 10:01:45.333591 RD_PRE = 0x0
7131 10:01:45.334013 WR_PRE = 0x1
7132 10:01:45.337159 WR_PST = 0x1
7133 10:01:45.337689 DBI_WR = 0x0
7134 10:01:45.340229 DBI_RD = 0x0
7135 10:01:45.340757 OTF = 0x1
7136 10:01:45.343254 ===================================
7137 10:01:45.346478 ===================================
7138 10:01:45.349652 ANA top config
7139 10:01:45.353209 ===================================
7140 10:01:45.356462 DLL_ASYNC_EN = 0
7141 10:01:45.356991 ALL_SLAVE_EN = 0
7142 10:01:45.359938 NEW_RANK_MODE = 1
7143 10:01:45.362915 DLL_IDLE_MODE = 1
7144 10:01:45.366511 LP45_APHY_COMB_EN = 1
7145 10:01:45.369944 TX_ODT_DIS = 0
7146 10:01:45.370501 NEW_8X_MODE = 1
7147 10:01:45.373436 ===================================
7148 10:01:45.376800 ===================================
7149 10:01:45.379742 data_rate = 3200
7150 10:01:45.382938 CKR = 1
7151 10:01:45.386110 DQ_P2S_RATIO = 8
7152 10:01:45.390089 ===================================
7153 10:01:45.392966 CA_P2S_RATIO = 8
7154 10:01:45.393398 DQ_CA_OPEN = 0
7155 10:01:45.396375 DQ_SEMI_OPEN = 0
7156 10:01:45.399484 CA_SEMI_OPEN = 0
7157 10:01:45.402901 CA_FULL_RATE = 0
7158 10:01:45.406179 DQ_CKDIV4_EN = 0
7159 10:01:45.409903 CA_CKDIV4_EN = 0
7160 10:01:45.410463 CA_PREDIV_EN = 0
7161 10:01:45.413145 PH8_DLY = 12
7162 10:01:45.416619 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7163 10:01:45.420054 DQ_AAMCK_DIV = 4
7164 10:01:45.423201 CA_AAMCK_DIV = 4
7165 10:01:45.426179 CA_ADMCK_DIV = 4
7166 10:01:45.426781 DQ_TRACK_CA_EN = 0
7167 10:01:45.429521 CA_PICK = 1600
7168 10:01:45.432645 CA_MCKIO = 1600
7169 10:01:45.436243 MCKIO_SEMI = 0
7170 10:01:45.439463 PLL_FREQ = 3068
7171 10:01:45.442894 DQ_UI_PI_RATIO = 32
7172 10:01:45.446192 CA_UI_PI_RATIO = 0
7173 10:01:45.449405 ===================================
7174 10:01:45.452648 ===================================
7175 10:01:45.453187 memory_type:LPDDR4
7176 10:01:45.456182 GP_NUM : 10
7177 10:01:45.459283 SRAM_EN : 1
7178 10:01:45.459727 MD32_EN : 0
7179 10:01:45.462671 ===================================
7180 10:01:45.465989 [ANA_INIT] >>>>>>>>>>>>>>
7181 10:01:45.469276 <<<<<< [CONFIGURE PHASE]: ANA_TX
7182 10:01:45.472568 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7183 10:01:45.475998 ===================================
7184 10:01:45.479329 data_rate = 3200,PCW = 0X7600
7185 10:01:45.482751 ===================================
7186 10:01:45.485942 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7187 10:01:45.489275 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7188 10:01:45.495821 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7189 10:01:45.499577 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7190 10:01:45.502732 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7191 10:01:45.506165 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7192 10:01:45.509407 [ANA_INIT] flow start
7193 10:01:45.512350 [ANA_INIT] PLL >>>>>>>>
7194 10:01:45.512776 [ANA_INIT] PLL <<<<<<<<
7195 10:01:45.516101 [ANA_INIT] MIDPI >>>>>>>>
7196 10:01:45.518944 [ANA_INIT] MIDPI <<<<<<<<
7197 10:01:45.522748 [ANA_INIT] DLL >>>>>>>>
7198 10:01:45.523278 [ANA_INIT] DLL <<<<<<<<
7199 10:01:45.525866 [ANA_INIT] flow end
7200 10:01:45.529138 ============ LP4 DIFF to SE enter ============
7201 10:01:45.532459 ============ LP4 DIFF to SE exit ============
7202 10:01:45.535550 [ANA_INIT] <<<<<<<<<<<<<
7203 10:01:45.539277 [Flow] Enable top DCM control >>>>>
7204 10:01:45.542244 [Flow] Enable top DCM control <<<<<
7205 10:01:45.545701 Enable DLL master slave shuffle
7206 10:01:45.552316 ==============================================================
7207 10:01:45.552746 Gating Mode config
7208 10:01:45.559135 ==============================================================
7209 10:01:45.559660 Config description:
7210 10:01:45.568826 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7211 10:01:45.575554 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7212 10:01:45.582470 SELPH_MODE 0: By rank 1: By Phase
7213 10:01:45.585609 ==============================================================
7214 10:01:45.589075 GAT_TRACK_EN = 1
7215 10:01:45.592061 RX_GATING_MODE = 2
7216 10:01:45.595404 RX_GATING_TRACK_MODE = 2
7217 10:01:45.598615 SELPH_MODE = 1
7218 10:01:45.602409 PICG_EARLY_EN = 1
7219 10:01:45.605468 VALID_LAT_VALUE = 1
7220 10:01:45.608872 ==============================================================
7221 10:01:45.612106 Enter into Gating configuration >>>>
7222 10:01:45.615510 Exit from Gating configuration <<<<
7223 10:01:45.619050 Enter into DVFS_PRE_config >>>>>
7224 10:01:45.632372 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7225 10:01:45.635064 Exit from DVFS_PRE_config <<<<<
7226 10:01:45.638758 Enter into PICG configuration >>>>
7227 10:01:45.642476 Exit from PICG configuration <<<<
7228 10:01:45.643040 [RX_INPUT] configuration >>>>>
7229 10:01:45.645282 [RX_INPUT] configuration <<<<<
7230 10:01:45.652085 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7231 10:01:45.655608 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7232 10:01:45.661942 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7233 10:01:45.668852 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7234 10:01:45.674973 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7235 10:01:45.681818 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7236 10:01:45.685290 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7237 10:01:45.688592 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7238 10:01:45.694902 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7239 10:01:45.698003 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7240 10:01:45.701909 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7241 10:01:45.705100 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7242 10:01:45.708681 ===================================
7243 10:01:45.711739 LPDDR4 DRAM CONFIGURATION
7244 10:01:45.714917 ===================================
7245 10:01:45.718185 EX_ROW_EN[0] = 0x0
7246 10:01:45.718775 EX_ROW_EN[1] = 0x0
7247 10:01:45.721679 LP4Y_EN = 0x0
7248 10:01:45.722247 WORK_FSP = 0x1
7249 10:01:45.724791 WL = 0x5
7250 10:01:45.725357 RL = 0x5
7251 10:01:45.727933 BL = 0x2
7252 10:01:45.728428 RPST = 0x0
7253 10:01:45.731052 RD_PRE = 0x0
7254 10:01:45.731546 WR_PRE = 0x1
7255 10:01:45.734714 WR_PST = 0x1
7256 10:01:45.735189 DBI_WR = 0x0
7257 10:01:45.738092 DBI_RD = 0x0
7258 10:01:45.741391 OTF = 0x1
7259 10:01:45.744749 ===================================
7260 10:01:45.747933 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7261 10:01:45.751813 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7262 10:01:45.754728 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7263 10:01:45.758056 ===================================
7264 10:01:45.761422 LPDDR4 DRAM CONFIGURATION
7265 10:01:45.764693 ===================================
7266 10:01:45.768041 EX_ROW_EN[0] = 0x10
7267 10:01:45.768518 EX_ROW_EN[1] = 0x0
7268 10:01:45.771335 LP4Y_EN = 0x0
7269 10:01:45.771925 WORK_FSP = 0x1
7270 10:01:45.774486 WL = 0x5
7271 10:01:45.775067 RL = 0x5
7272 10:01:45.778023 BL = 0x2
7273 10:01:45.778664 RPST = 0x0
7274 10:01:45.781003 RD_PRE = 0x0
7275 10:01:45.781483 WR_PRE = 0x1
7276 10:01:45.784561 WR_PST = 0x1
7277 10:01:45.785037 DBI_WR = 0x0
7278 10:01:45.787657 DBI_RD = 0x0
7279 10:01:45.788136 OTF = 0x1
7280 10:01:45.790928 ===================================
7281 10:01:45.797743 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7282 10:01:45.798367 ==
7283 10:01:45.800826 Dram Type= 6, Freq= 0, CH_0, rank 0
7284 10:01:45.808240 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7285 10:01:45.808836 ==
7286 10:01:45.809324 [Duty_Offset_Calibration]
7287 10:01:45.810755 B0:2 B1:0 CA:1
7288 10:01:45.811232
7289 10:01:45.814425 [DutyScan_Calibration_Flow] k_type=0
7290 10:01:45.823234
7291 10:01:45.823871 ==CLK 0==
7292 10:01:45.826798 Final CLK duty delay cell = -4
7293 10:01:45.829381 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7294 10:01:45.832594 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7295 10:01:45.836322 [-4] AVG Duty = 4937%(X100)
7296 10:01:45.836798
7297 10:01:45.839621 CH0 CLK Duty spec in!! Max-Min= 187%
7298 10:01:45.842861 [DutyScan_Calibration_Flow] ====Done====
7299 10:01:45.843341
7300 10:01:45.845978 [DutyScan_Calibration_Flow] k_type=1
7301 10:01:45.862320
7302 10:01:45.862940 ==DQS 0 ==
7303 10:01:45.865591 Final DQS duty delay cell = 0
7304 10:01:45.868983 [0] MAX Duty = 5249%(X100), DQS PI = 32
7305 10:01:45.872395 [0] MIN Duty = 4969%(X100), DQS PI = 0
7306 10:01:45.872995 [0] AVG Duty = 5109%(X100)
7307 10:01:45.875741
7308 10:01:45.876217 ==DQS 1 ==
7309 10:01:45.879331 Final DQS duty delay cell = -4
7310 10:01:45.882491 [-4] MAX Duty = 5125%(X100), DQS PI = 46
7311 10:01:45.885542 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7312 10:01:45.888761 [-4] AVG Duty = 5000%(X100)
7313 10:01:45.889240
7314 10:01:45.892593 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7315 10:01:45.893195
7316 10:01:45.895681 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7317 10:01:45.898750 [DutyScan_Calibration_Flow] ====Done====
7318 10:01:45.899230
7319 10:01:45.901832 [DutyScan_Calibration_Flow] k_type=3
7320 10:01:45.918922
7321 10:01:45.919503 ==DQM 0 ==
7322 10:01:45.922586 Final DQM duty delay cell = 0
7323 10:01:45.925881 [0] MAX Duty = 5124%(X100), DQS PI = 26
7324 10:01:45.928785 [0] MIN Duty = 4813%(X100), DQS PI = 50
7325 10:01:45.931949 [0] AVG Duty = 4968%(X100)
7326 10:01:45.932432
7327 10:01:45.932905 ==DQM 1 ==
7328 10:01:45.935372 Final DQM duty delay cell = -4
7329 10:01:45.938947 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7330 10:01:45.942071 [-4] MIN Duty = 4751%(X100), DQS PI = 18
7331 10:01:45.945483 [-4] AVG Duty = 4891%(X100)
7332 10:01:45.946069
7333 10:01:45.948905 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7334 10:01:45.949491
7335 10:01:45.951924 CH0 DQM 1 Duty spec in!! Max-Min= 280%
7336 10:01:45.955303 [DutyScan_Calibration_Flow] ====Done====
7337 10:01:45.955891
7338 10:01:45.958537 [DutyScan_Calibration_Flow] k_type=2
7339 10:01:45.976698
7340 10:01:45.977281 ==DQ 0 ==
7341 10:01:45.979865 Final DQ duty delay cell = 0
7342 10:01:45.983325 [0] MAX Duty = 5156%(X100), DQS PI = 36
7343 10:01:45.986607 [0] MIN Duty = 5000%(X100), DQS PI = 2
7344 10:01:45.987089 [0] AVG Duty = 5078%(X100)
7345 10:01:45.987564
7346 10:01:45.989857 ==DQ 1 ==
7347 10:01:45.993252 Final DQ duty delay cell = 0
7348 10:01:45.996616 [0] MAX Duty = 4969%(X100), DQS PI = 44
7349 10:01:45.999829 [0] MIN Duty = 4875%(X100), DQS PI = 10
7350 10:01:46.000316 [0] AVG Duty = 4922%(X100)
7351 10:01:46.000925
7352 10:01:46.003074 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7353 10:01:46.006448
7354 10:01:46.006915 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7355 10:01:46.012892 [DutyScan_Calibration_Flow] ====Done====
7356 10:01:46.013479 ==
7357 10:01:46.016344 Dram Type= 6, Freq= 0, CH_1, rank 0
7358 10:01:46.019891 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7359 10:01:46.020485 ==
7360 10:01:46.022896 [Duty_Offset_Calibration]
7361 10:01:46.023490 B0:0 B1:-1 CA:2
7362 10:01:46.024006
7363 10:01:46.026094 [DutyScan_Calibration_Flow] k_type=0
7364 10:01:46.036470
7365 10:01:46.037031 ==CLK 0==
7366 10:01:46.039488 Final CLK duty delay cell = 0
7367 10:01:46.042784 [0] MAX Duty = 5156%(X100), DQS PI = 10
7368 10:01:46.046623 [0] MIN Duty = 4906%(X100), DQS PI = 46
7369 10:01:46.046939 [0] AVG Duty = 5031%(X100)
7370 10:01:46.049617
7371 10:01:46.053080 CH1 CLK Duty spec in!! Max-Min= 250%
7372 10:01:46.056391 [DutyScan_Calibration_Flow] ====Done====
7373 10:01:46.056670
7374 10:01:46.059567 [DutyScan_Calibration_Flow] k_type=1
7375 10:01:46.076259
7376 10:01:46.076535 ==DQS 0 ==
7377 10:01:46.079518 Final DQS duty delay cell = 0
7378 10:01:46.082577 [0] MAX Duty = 5124%(X100), DQS PI = 26
7379 10:01:46.086540 [0] MIN Duty = 4969%(X100), DQS PI = 0
7380 10:01:46.086873 [0] AVG Duty = 5046%(X100)
7381 10:01:46.089877
7382 10:01:46.090332 ==DQS 1 ==
7383 10:01:46.093233 Final DQS duty delay cell = 0
7384 10:01:46.096101 [0] MAX Duty = 5187%(X100), DQS PI = 0
7385 10:01:46.099774 [0] MIN Duty = 4844%(X100), DQS PI = 32
7386 10:01:46.100344 [0] AVG Duty = 5015%(X100)
7387 10:01:46.102627
7388 10:01:46.106029 CH1 DQS 0 Duty spec in!! Max-Min= 155%
7389 10:01:46.106513
7390 10:01:46.109393 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7391 10:01:46.112594 [DutyScan_Calibration_Flow] ====Done====
7392 10:01:46.113047
7393 10:01:46.115781 [DutyScan_Calibration_Flow] k_type=3
7394 10:01:46.133938
7395 10:01:46.134667 ==DQM 0 ==
7396 10:01:46.137030 Final DQM duty delay cell = 4
7397 10:01:46.140505 [4] MAX Duty = 5125%(X100), DQS PI = 22
7398 10:01:46.143883 [4] MIN Duty = 4969%(X100), DQS PI = 44
7399 10:01:46.147342 [4] AVG Duty = 5047%(X100)
7400 10:01:46.147903
7401 10:01:46.148266 ==DQM 1 ==
7402 10:01:46.150752 Final DQM duty delay cell = 0
7403 10:01:46.153773 [0] MAX Duty = 5281%(X100), DQS PI = 60
7404 10:01:46.157142 [0] MIN Duty = 4907%(X100), DQS PI = 34
7405 10:01:46.160152 [0] AVG Duty = 5094%(X100)
7406 10:01:46.160607
7407 10:01:46.164113 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7408 10:01:46.164673
7409 10:01:46.167336 CH1 DQM 1 Duty spec in!! Max-Min= 374%
7410 10:01:46.170671 [DutyScan_Calibration_Flow] ====Done====
7411 10:01:46.171224
7412 10:01:46.174024 [DutyScan_Calibration_Flow] k_type=2
7413 10:01:46.191033
7414 10:01:46.191579 ==DQ 0 ==
7415 10:01:46.194491 Final DQ duty delay cell = 0
7416 10:01:46.197703 [0] MAX Duty = 5093%(X100), DQS PI = 18
7417 10:01:46.200746 [0] MIN Duty = 4969%(X100), DQS PI = 46
7418 10:01:46.201374 [0] AVG Duty = 5031%(X100)
7419 10:01:46.204249
7420 10:01:46.204703 ==DQ 1 ==
7421 10:01:46.207489 Final DQ duty delay cell = 0
7422 10:01:46.210412 [0] MAX Duty = 5062%(X100), DQS PI = 2
7423 10:01:46.214446 [0] MIN Duty = 4813%(X100), DQS PI = 34
7424 10:01:46.215007 [0] AVG Duty = 4937%(X100)
7425 10:01:46.217158
7426 10:01:46.221095 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7427 10:01:46.221652
7428 10:01:46.224248 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7429 10:01:46.227489 [DutyScan_Calibration_Flow] ====Done====
7430 10:01:46.230522 nWR fixed to 30
7431 10:01:46.231105 [ModeRegInit_LP4] CH0 RK0
7432 10:01:46.233761 [ModeRegInit_LP4] CH0 RK1
7433 10:01:46.237076 [ModeRegInit_LP4] CH1 RK0
7434 10:01:46.240986 [ModeRegInit_LP4] CH1 RK1
7435 10:01:46.241554 match AC timing 5
7436 10:01:46.244044 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7437 10:01:46.250972 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7438 10:01:46.254061 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7439 10:01:46.260467 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7440 10:01:46.263859 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7441 10:01:46.264444 [MiockJmeterHQA]
7442 10:01:46.264823
7443 10:01:46.267228 [DramcMiockJmeter] u1RxGatingPI = 0
7444 10:01:46.270594 0 : 4366, 4138
7445 10:01:46.271169 4 : 4363, 4137
7446 10:01:46.271549 8 : 4252, 4027
7447 10:01:46.273984 12 : 4252, 4027
7448 10:01:46.274615 16 : 4255, 4030
7449 10:01:46.277671 20 : 4252, 4027
7450 10:01:46.278256 24 : 4363, 4139
7451 10:01:46.280629 28 : 4363, 4138
7452 10:01:46.281107 32 : 4363, 4140
7453 10:01:46.284010 36 : 4250, 4026
7454 10:01:46.284594 40 : 4361, 4138
7455 10:01:46.284974 44 : 4363, 4137
7456 10:01:46.287610 48 : 4250, 4027
7457 10:01:46.288194 52 : 4252, 4027
7458 10:01:46.290544 56 : 4253, 4026
7459 10:01:46.291066 60 : 4250, 4027
7460 10:01:46.293882 64 : 4250, 4027
7461 10:01:46.294509 68 : 4250, 4026
7462 10:01:46.297338 72 : 4254, 4030
7463 10:01:46.297815 76 : 4255, 4029
7464 10:01:46.298191 80 : 4250, 4027
7465 10:01:46.300781 84 : 4252, 4029
7466 10:01:46.301423 88 : 4250, 3587
7467 10:01:46.304214 92 : 4363, 0
7468 10:01:46.304689 96 : 4250, 0
7469 10:01:46.305094 100 : 4254, 0
7470 10:01:46.307298 104 : 4250, 0
7471 10:01:46.307775 108 : 4250, 0
7472 10:01:46.310654 112 : 4361, 0
7473 10:01:46.311231 116 : 4250, 0
7474 10:01:46.311641 120 : 4250, 0
7475 10:01:46.314260 124 : 4250, 0
7476 10:01:46.314804 128 : 4360, 0
7477 10:01:46.315187 132 : 4250, 0
7478 10:01:46.317007 136 : 4250, 0
7479 10:01:46.317484 140 : 4250, 0
7480 10:01:46.320458 144 : 4250, 0
7481 10:01:46.321047 148 : 4360, 0
7482 10:01:46.321435 152 : 4252, 0
7483 10:01:46.323594 156 : 4250, 0
7484 10:01:46.324098 160 : 4250, 0
7485 10:01:46.327191 164 : 4363, 0
7486 10:01:46.327830 168 : 4250, 0
7487 10:01:46.328410 172 : 4250, 0
7488 10:01:46.330439 176 : 4250, 0
7489 10:01:46.330927 180 : 4360, 0
7490 10:01:46.333529 184 : 4250, 0
7491 10:01:46.334135 188 : 4250, 0
7492 10:01:46.334813 192 : 4250, 0
7493 10:01:46.336917 196 : 4250, 0
7494 10:01:46.337393 200 : 4361, 10
7495 10:01:46.340465 204 : 4255, 2196
7496 10:01:46.341059 208 : 4252, 4029
7497 10:01:46.343700 212 : 4360, 4138
7498 10:01:46.344314 216 : 4250, 4027
7499 10:01:46.344706 220 : 4255, 4029
7500 10:01:46.346908 224 : 4250, 4026
7501 10:01:46.347386 228 : 4250, 4027
7502 10:01:46.350476 232 : 4250, 4027
7503 10:01:46.350956 236 : 4250, 4027
7504 10:01:46.353526 240 : 4250, 4027
7505 10:01:46.354056 244 : 4250, 4027
7506 10:01:46.357323 248 : 4252, 4030
7507 10:01:46.357913 252 : 4250, 4027
7508 10:01:46.360547 256 : 4250, 4027
7509 10:01:46.361134 260 : 4361, 4137
7510 10:01:46.363817 264 : 4250, 4027
7511 10:01:46.364334 268 : 4361, 4137
7512 10:01:46.367315 272 : 4250, 4027
7513 10:01:46.367899 276 : 4250, 4026
7514 10:01:46.368285 280 : 4250, 4027
7515 10:01:46.370495 284 : 4249, 4027
7516 10:01:46.371079 288 : 4249, 4027
7517 10:01:46.374214 292 : 4250, 4027
7518 10:01:46.374842 296 : 4250, 4027
7519 10:01:46.376820 300 : 4252, 4029
7520 10:01:46.377299 304 : 4250, 4026
7521 10:01:46.380428 308 : 4250, 4027
7522 10:01:46.381020 312 : 4361, 4048
7523 10:01:46.383764 316 : 4249, 2229
7524 10:01:46.384351 320 : 4361, 20
7525 10:01:46.384741
7526 10:01:46.387030 MIOCK jitter meter ch=0
7527 10:01:46.387504
7528 10:01:46.390276 1T = (320-92) = 228 dly cells
7529 10:01:46.393498 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7530 10:01:46.393972 ==
7531 10:01:46.396674 Dram Type= 6, Freq= 0, CH_0, rank 0
7532 10:01:46.403373 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7533 10:01:46.403852 ==
7534 10:01:46.406510 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7535 10:01:46.413962 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7536 10:01:46.416833 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7537 10:01:46.423069 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7538 10:01:46.431344 [CA 0] Center 43 (13~73) winsize 61
7539 10:01:46.434479 [CA 1] Center 43 (13~73) winsize 61
7540 10:01:46.437422 [CA 2] Center 38 (8~68) winsize 61
7541 10:01:46.441401 [CA 3] Center 37 (8~67) winsize 60
7542 10:01:46.444352 [CA 4] Center 36 (6~66) winsize 61
7543 10:01:46.447833 [CA 5] Center 35 (5~65) winsize 61
7544 10:01:46.448406
7545 10:01:46.451089 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7546 10:01:46.451564
7547 10:01:46.454298 [CATrainingPosCal] consider 1 rank data
7548 10:01:46.458021 u2DelayCellTimex100 = 285/100 ps
7549 10:01:46.461404 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7550 10:01:46.467964 CA1 delay=43 (13~73),Diff = 8 PI (27 cell)
7551 10:01:46.471149 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7552 10:01:46.474478 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7553 10:01:46.477897 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7554 10:01:46.481040 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7555 10:01:46.481610
7556 10:01:46.484754 CA PerBit enable=1, Macro0, CA PI delay=35
7557 10:01:46.485326
7558 10:01:46.487788 [CBTSetCACLKResult] CA Dly = 35
7559 10:01:46.491091 CS Dly: 9 (0~40)
7560 10:01:46.494326 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7561 10:01:46.498078 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7562 10:01:46.498694 ==
7563 10:01:46.501149 Dram Type= 6, Freq= 0, CH_0, rank 1
7564 10:01:46.504570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7565 10:01:46.505152 ==
7566 10:01:46.510922 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7567 10:01:46.514499 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7568 10:01:46.520917 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7569 10:01:46.524433 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7570 10:01:46.534683 [CA 0] Center 43 (13~74) winsize 62
7571 10:01:46.537855 [CA 1] Center 43 (13~73) winsize 61
7572 10:01:46.541100 [CA 2] Center 38 (8~68) winsize 61
7573 10:01:46.544339 [CA 3] Center 38 (9~68) winsize 60
7574 10:01:46.548382 [CA 4] Center 36 (7~66) winsize 60
7575 10:01:46.550830 [CA 5] Center 36 (6~66) winsize 61
7576 10:01:46.551306
7577 10:01:46.554596 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7578 10:01:46.555158
7579 10:01:46.557466 [CATrainingPosCal] consider 2 rank data
7580 10:01:46.560655 u2DelayCellTimex100 = 285/100 ps
7581 10:01:46.564579 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7582 10:01:46.571486 CA1 delay=43 (13~73),Diff = 8 PI (27 cell)
7583 10:01:46.574081 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7584 10:01:46.577828 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7585 10:01:46.581272 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7586 10:01:46.584328 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7587 10:01:46.584901
7588 10:01:46.587493 CA PerBit enable=1, Macro0, CA PI delay=35
7589 10:01:46.588067
7590 10:01:46.590983 [CBTSetCACLKResult] CA Dly = 35
7591 10:01:46.594102 CS Dly: 10 (0~43)
7592 10:01:46.597521 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7593 10:01:46.600582 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7594 10:01:46.601133
7595 10:01:46.604255 ----->DramcWriteLeveling(PI) begin...
7596 10:01:46.604739 ==
7597 10:01:46.607693 Dram Type= 6, Freq= 0, CH_0, rank 0
7598 10:01:46.614466 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7599 10:01:46.615036 ==
7600 10:01:46.617490 Write leveling (Byte 0): 35 => 35
7601 10:01:46.618094 Write leveling (Byte 1): 30 => 30
7602 10:01:46.620773 DramcWriteLeveling(PI) end<-----
7603 10:01:46.621337
7604 10:01:46.624129 ==
7605 10:01:46.624698 Dram Type= 6, Freq= 0, CH_0, rank 0
7606 10:01:46.630965 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7607 10:01:46.631541 ==
7608 10:01:46.633891 [Gating] SW mode calibration
7609 10:01:46.640688 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7610 10:01:46.643668 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7611 10:01:46.650501 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7612 10:01:46.653723 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7613 10:01:46.656975 1 4 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
7614 10:01:46.663668 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7615 10:01:46.667090 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7616 10:01:46.670294 1 4 20 | B1->B0 | 3332 3434 | 1 1 | (1 1) (1 1)
7617 10:01:46.677272 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7618 10:01:46.680561 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7619 10:01:46.683528 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7620 10:01:46.690557 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7621 10:01:46.694075 1 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
7622 10:01:46.696732 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7623 10:01:46.703322 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7624 10:01:46.707081 1 5 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
7625 10:01:46.710235 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7626 10:01:46.716715 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7627 10:01:46.720393 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7628 10:01:46.723978 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7629 10:01:46.726997 1 6 8 | B1->B0 | 2323 3b3b | 0 1 | (0 0) (0 0)
7630 10:01:46.733430 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7631 10:01:46.736944 1 6 16 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
7632 10:01:46.740533 1 6 20 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7633 10:01:46.746788 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7634 10:01:46.749892 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7635 10:01:46.753179 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7636 10:01:46.759996 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7637 10:01:46.763495 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7638 10:01:46.766546 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7639 10:01:46.773466 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7640 10:01:46.776612 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7641 10:01:46.780129 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7642 10:01:46.786794 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 10:01:46.790115 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 10:01:46.794099 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 10:01:46.800157 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 10:01:46.803361 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 10:01:46.807201 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 10:01:46.813215 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 10:01:46.816794 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 10:01:46.820156 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 10:01:46.826904 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 10:01:46.830178 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 10:01:46.833099 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7654 10:01:46.839806 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7655 10:01:46.840381 Total UI for P1: 0, mck2ui 16
7656 10:01:46.842966 best dqsien dly found for B0: ( 1, 9, 8)
7657 10:01:46.850012 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7658 10:01:46.853693 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7659 10:01:46.856511 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7660 10:01:46.859822 Total UI for P1: 0, mck2ui 16
7661 10:01:46.863070 best dqsien dly found for B1: ( 1, 9, 18)
7662 10:01:46.866169 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7663 10:01:46.869879 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7664 10:01:46.872911
7665 10:01:46.876560 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7666 10:01:46.879655 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7667 10:01:46.882937 [Gating] SW calibration Done
7668 10:01:46.883405 ==
7669 10:01:46.886109 Dram Type= 6, Freq= 0, CH_0, rank 0
7670 10:01:46.889672 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7671 10:01:46.890289 ==
7672 10:01:46.890705 RX Vref Scan: 0
7673 10:01:46.893043
7674 10:01:46.893506 RX Vref 0 -> 0, step: 1
7675 10:01:46.893874
7676 10:01:46.896095 RX Delay 0 -> 252, step: 8
7677 10:01:46.899519 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7678 10:01:46.902890 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7679 10:01:46.909473 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7680 10:01:46.912936 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7681 10:01:46.915970 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7682 10:01:46.919049 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7683 10:01:46.922986 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7684 10:01:46.929717 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7685 10:01:46.932968 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7686 10:01:46.935660 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7687 10:01:46.938942 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7688 10:01:46.942306 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
7689 10:01:46.949161 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7690 10:01:46.952479 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7691 10:01:46.955622 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7692 10:01:46.958775 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
7693 10:01:46.959242 ==
7694 10:01:46.962490 Dram Type= 6, Freq= 0, CH_0, rank 0
7695 10:01:46.968795 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7696 10:01:46.969391 ==
7697 10:01:46.969771 DQS Delay:
7698 10:01:46.972191 DQS0 = 0, DQS1 = 0
7699 10:01:46.972657 DQM Delay:
7700 10:01:46.975667 DQM0 = 137, DQM1 = 126
7701 10:01:46.976130 DQ Delay:
7702 10:01:46.978698 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7703 10:01:46.982052 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7704 10:01:46.985544 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =127
7705 10:01:46.988921 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =131
7706 10:01:46.989486
7707 10:01:46.989855
7708 10:01:46.990194 ==
7709 10:01:46.992114 Dram Type= 6, Freq= 0, CH_0, rank 0
7710 10:01:46.998447 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7711 10:01:46.999044 ==
7712 10:01:46.999421
7713 10:01:46.999762
7714 10:01:47.000093 TX Vref Scan disable
7715 10:01:47.001799 == TX Byte 0 ==
7716 10:01:47.005364 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7717 10:01:47.011973 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7718 10:01:47.012542 == TX Byte 1 ==
7719 10:01:47.014980 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7720 10:01:47.021858 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7721 10:01:47.022463 ==
7722 10:01:47.024926 Dram Type= 6, Freq= 0, CH_0, rank 0
7723 10:01:47.028269 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7724 10:01:47.028848 ==
7725 10:01:47.039745
7726 10:01:47.043092 TX Vref early break, caculate TX vref
7727 10:01:47.046943 TX Vref=16, minBit 4, minWin=23, winSum=377
7728 10:01:47.049928 TX Vref=18, minBit 6, minWin=23, winSum=386
7729 10:01:47.053304 TX Vref=20, minBit 6, minWin=23, winSum=397
7730 10:01:47.056694 TX Vref=22, minBit 7, minWin=24, winSum=409
7731 10:01:47.059895 TX Vref=24, minBit 5, minWin=25, winSum=417
7732 10:01:47.066242 TX Vref=26, minBit 12, minWin=25, winSum=424
7733 10:01:47.069843 TX Vref=28, minBit 0, minWin=26, winSum=434
7734 10:01:47.073255 TX Vref=30, minBit 0, minWin=26, winSum=422
7735 10:01:47.077077 TX Vref=32, minBit 1, minWin=25, winSum=411
7736 10:01:47.083214 [TxChooseVref] Worse bit 0, Min win 26, Win sum 434, Final Vref 28
7737 10:01:47.083784
7738 10:01:47.086111 Final TX Range 0 Vref 28
7739 10:01:47.086600
7740 10:01:47.086971 ==
7741 10:01:47.089875 Dram Type= 6, Freq= 0, CH_0, rank 0
7742 10:01:47.092945 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7743 10:01:47.093419 ==
7744 10:01:47.093790
7745 10:01:47.094131
7746 10:01:47.096525 TX Vref Scan disable
7747 10:01:47.099480 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7748 10:01:47.102817 == TX Byte 0 ==
7749 10:01:47.106355 u2DelayCellOfst[0]=10 cells (3 PI)
7750 10:01:47.110180 u2DelayCellOfst[1]=17 cells (5 PI)
7751 10:01:47.112845 u2DelayCellOfst[2]=10 cells (3 PI)
7752 10:01:47.116550 u2DelayCellOfst[3]=10 cells (3 PI)
7753 10:01:47.119949 u2DelayCellOfst[4]=6 cells (2 PI)
7754 10:01:47.120566 u2DelayCellOfst[5]=0 cells (0 PI)
7755 10:01:47.122793 u2DelayCellOfst[6]=17 cells (5 PI)
7756 10:01:47.125981 u2DelayCellOfst[7]=13 cells (4 PI)
7757 10:01:47.132934 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7758 10:01:47.136099 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7759 10:01:47.136807 == TX Byte 1 ==
7760 10:01:47.139529 u2DelayCellOfst[8]=0 cells (0 PI)
7761 10:01:47.142899 u2DelayCellOfst[9]=0 cells (0 PI)
7762 10:01:47.146190 u2DelayCellOfst[10]=6 cells (2 PI)
7763 10:01:47.149534 u2DelayCellOfst[11]=3 cells (1 PI)
7764 10:01:47.152790 u2DelayCellOfst[12]=13 cells (4 PI)
7765 10:01:47.156596 u2DelayCellOfst[13]=13 cells (4 PI)
7766 10:01:47.160156 u2DelayCellOfst[14]=13 cells (4 PI)
7767 10:01:47.162870 u2DelayCellOfst[15]=10 cells (3 PI)
7768 10:01:47.166509 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7769 10:01:47.169636 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7770 10:01:47.172668 DramC Write-DBI on
7771 10:01:47.173137 ==
7772 10:01:47.176942 Dram Type= 6, Freq= 0, CH_0, rank 0
7773 10:01:47.179953 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7774 10:01:47.180604 ==
7775 10:01:47.180984
7776 10:01:47.181331
7777 10:01:47.183377 TX Vref Scan disable
7778 10:01:47.186506 == TX Byte 0 ==
7779 10:01:47.189899 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7780 10:01:47.190476 == TX Byte 1 ==
7781 10:01:47.196343 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7782 10:01:47.196810 DramC Write-DBI off
7783 10:01:47.197184
7784 10:01:47.199619 [DATLAT]
7785 10:01:47.200087 Freq=1600, CH0 RK0
7786 10:01:47.200521
7787 10:01:47.202903 DATLAT Default: 0xf
7788 10:01:47.203401 0, 0xFFFF, sum = 0
7789 10:01:47.206329 1, 0xFFFF, sum = 0
7790 10:01:47.206911 2, 0xFFFF, sum = 0
7791 10:01:47.209599 3, 0xFFFF, sum = 0
7792 10:01:47.210248 4, 0xFFFF, sum = 0
7793 10:01:47.212832 5, 0xFFFF, sum = 0
7794 10:01:47.213327 6, 0xFFFF, sum = 0
7795 10:01:47.216396 7, 0xFFFF, sum = 0
7796 10:01:47.216978 8, 0xFFFF, sum = 0
7797 10:01:47.219388 9, 0xFFFF, sum = 0
7798 10:01:47.219864 10, 0xFFFF, sum = 0
7799 10:01:47.222858 11, 0xFFFF, sum = 0
7800 10:01:47.225836 12, 0xFFFF, sum = 0
7801 10:01:47.226308 13, 0xFFFF, sum = 0
7802 10:01:47.229568 14, 0x0, sum = 1
7803 10:01:47.230148 15, 0x0, sum = 2
7804 10:01:47.232592 16, 0x0, sum = 3
7805 10:01:47.233066 17, 0x0, sum = 4
7806 10:01:47.233445 best_step = 15
7807 10:01:47.233843
7808 10:01:47.236226 ==
7809 10:01:47.239124 Dram Type= 6, Freq= 0, CH_0, rank 0
7810 10:01:47.242853 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7811 10:01:47.243440 ==
7812 10:01:47.243822 RX Vref Scan: 1
7813 10:01:47.244172
7814 10:01:47.246225 Set Vref Range= 24 -> 127
7815 10:01:47.246758
7816 10:01:47.249191 RX Vref 24 -> 127, step: 1
7817 10:01:47.249770
7818 10:01:47.252776 RX Delay 19 -> 252, step: 4
7819 10:01:47.253357
7820 10:01:47.255967 Set Vref, RX VrefLevel [Byte0]: 24
7821 10:01:47.258947 [Byte1]: 24
7822 10:01:47.259418
7823 10:01:47.262510 Set Vref, RX VrefLevel [Byte0]: 25
7824 10:01:47.266044 [Byte1]: 25
7825 10:01:47.266675
7826 10:01:47.269453 Set Vref, RX VrefLevel [Byte0]: 26
7827 10:01:47.272705 [Byte1]: 26
7828 10:01:47.276027
7829 10:01:47.276608 Set Vref, RX VrefLevel [Byte0]: 27
7830 10:01:47.279030 [Byte1]: 27
7831 10:01:47.283317
7832 10:01:47.283896 Set Vref, RX VrefLevel [Byte0]: 28
7833 10:01:47.287053 [Byte1]: 28
7834 10:01:47.291052
7835 10:01:47.291641 Set Vref, RX VrefLevel [Byte0]: 29
7836 10:01:47.294469 [Byte1]: 29
7837 10:01:47.298464
7838 10:01:47.299042 Set Vref, RX VrefLevel [Byte0]: 30
7839 10:01:47.301662 [Byte1]: 30
7840 10:01:47.306317
7841 10:01:47.306962 Set Vref, RX VrefLevel [Byte0]: 31
7842 10:01:47.309559 [Byte1]: 31
7843 10:01:47.313399
7844 10:01:47.313868 Set Vref, RX VrefLevel [Byte0]: 32
7845 10:01:47.316912 [Byte1]: 32
7846 10:01:47.321235
7847 10:01:47.321853 Set Vref, RX VrefLevel [Byte0]: 33
7848 10:01:47.324477 [Byte1]: 33
7849 10:01:47.328958
7850 10:01:47.329594 Set Vref, RX VrefLevel [Byte0]: 34
7851 10:01:47.332380 [Byte1]: 34
7852 10:01:47.336751
7853 10:01:47.337329 Set Vref, RX VrefLevel [Byte0]: 35
7854 10:01:47.339794 [Byte1]: 35
7855 10:01:47.344175
7856 10:01:47.344755 Set Vref, RX VrefLevel [Byte0]: 36
7857 10:01:47.346931 [Byte1]: 36
7858 10:01:47.351327
7859 10:01:47.351905 Set Vref, RX VrefLevel [Byte0]: 37
7860 10:01:47.354958 [Byte1]: 37
7861 10:01:47.359219
7862 10:01:47.359800 Set Vref, RX VrefLevel [Byte0]: 38
7863 10:01:47.362430 [Byte1]: 38
7864 10:01:47.366902
7865 10:01:47.367370 Set Vref, RX VrefLevel [Byte0]: 39
7866 10:01:47.370130 [Byte1]: 39
7867 10:01:47.374252
7868 10:01:47.374873 Set Vref, RX VrefLevel [Byte0]: 40
7869 10:01:47.377557 [Byte1]: 40
7870 10:01:47.382187
7871 10:01:47.382821 Set Vref, RX VrefLevel [Byte0]: 41
7872 10:01:47.385044 [Byte1]: 41
7873 10:01:47.389541
7874 10:01:47.390117 Set Vref, RX VrefLevel [Byte0]: 42
7875 10:01:47.393045 [Byte1]: 42
7876 10:01:47.397524
7877 10:01:47.398166 Set Vref, RX VrefLevel [Byte0]: 43
7878 10:01:47.400081 [Byte1]: 43
7879 10:01:47.404458
7880 10:01:47.404925 Set Vref, RX VrefLevel [Byte0]: 44
7881 10:01:47.407907 [Byte1]: 44
7882 10:01:47.412264
7883 10:01:47.412837 Set Vref, RX VrefLevel [Byte0]: 45
7884 10:01:47.415440 [Byte1]: 45
7885 10:01:47.419950
7886 10:01:47.420534 Set Vref, RX VrefLevel [Byte0]: 46
7887 10:01:47.423001 [Byte1]: 46
7888 10:01:47.427405
7889 10:01:47.428054 Set Vref, RX VrefLevel [Byte0]: 47
7890 10:01:47.430299 [Byte1]: 47
7891 10:01:47.434700
7892 10:01:47.435274 Set Vref, RX VrefLevel [Byte0]: 48
7893 10:01:47.437860 [Byte1]: 48
7894 10:01:47.442252
7895 10:01:47.442878 Set Vref, RX VrefLevel [Byte0]: 49
7896 10:01:47.445832 [Byte1]: 49
7897 10:01:47.450854
7898 10:01:47.451435 Set Vref, RX VrefLevel [Byte0]: 50
7899 10:01:47.453728 [Byte1]: 50
7900 10:01:47.457726
7901 10:01:47.458325 Set Vref, RX VrefLevel [Byte0]: 51
7902 10:01:47.460710 [Byte1]: 51
7903 10:01:47.465667
7904 10:01:47.466249 Set Vref, RX VrefLevel [Byte0]: 52
7905 10:01:47.468561 [Byte1]: 52
7906 10:01:47.473044
7907 10:01:47.473627 Set Vref, RX VrefLevel [Byte0]: 53
7908 10:01:47.475990 [Byte1]: 53
7909 10:01:47.480241
7910 10:01:47.480817 Set Vref, RX VrefLevel [Byte0]: 54
7911 10:01:47.483759 [Byte1]: 54
7912 10:01:47.487802
7913 10:01:47.488385 Set Vref, RX VrefLevel [Byte0]: 55
7914 10:01:47.491315 [Byte1]: 55
7915 10:01:47.495680
7916 10:01:47.496334 Set Vref, RX VrefLevel [Byte0]: 56
7917 10:01:47.498792 [Byte1]: 56
7918 10:01:47.502823
7919 10:01:47.503322 Set Vref, RX VrefLevel [Byte0]: 57
7920 10:01:47.506306 [Byte1]: 57
7921 10:01:47.510325
7922 10:01:47.510877 Set Vref, RX VrefLevel [Byte0]: 58
7923 10:01:47.514069 [Byte1]: 58
7924 10:01:47.518227
7925 10:01:47.518831 Set Vref, RX VrefLevel [Byte0]: 59
7926 10:01:47.521322 [Byte1]: 59
7927 10:01:47.525668
7928 10:01:47.526239 Set Vref, RX VrefLevel [Byte0]: 60
7929 10:01:47.529435 [Byte1]: 60
7930 10:01:47.533223
7931 10:01:47.533788 Set Vref, RX VrefLevel [Byte0]: 61
7932 10:01:47.536594 [Byte1]: 61
7933 10:01:47.540566
7934 10:01:47.541033 Set Vref, RX VrefLevel [Byte0]: 62
7935 10:01:47.544128 [Byte1]: 62
7936 10:01:47.548202
7937 10:01:47.548699 Set Vref, RX VrefLevel [Byte0]: 63
7938 10:01:47.551799 [Byte1]: 63
7939 10:01:47.555983
7940 10:01:47.556555 Set Vref, RX VrefLevel [Byte0]: 64
7941 10:01:47.559227 [Byte1]: 64
7942 10:01:47.563393
7943 10:01:47.563963 Set Vref, RX VrefLevel [Byte0]: 65
7944 10:01:47.567328 [Byte1]: 65
7945 10:01:47.571306
7946 10:01:47.571874 Set Vref, RX VrefLevel [Byte0]: 66
7947 10:01:47.574327 [Byte1]: 66
7948 10:01:47.579024
7949 10:01:47.579593 Set Vref, RX VrefLevel [Byte0]: 67
7950 10:01:47.582031 [Byte1]: 67
7951 10:01:47.586237
7952 10:01:47.586845 Set Vref, RX VrefLevel [Byte0]: 68
7953 10:01:47.589881 [Byte1]: 68
7954 10:01:47.593554
7955 10:01:47.594016 Set Vref, RX VrefLevel [Byte0]: 69
7956 10:01:47.596988 [Byte1]: 69
7957 10:01:47.601781
7958 10:01:47.602506 Set Vref, RX VrefLevel [Byte0]: 70
7959 10:01:47.604983 [Byte1]: 70
7960 10:01:47.609041
7961 10:01:47.609611 Set Vref, RX VrefLevel [Byte0]: 71
7962 10:01:47.612402 [Byte1]: 71
7963 10:01:47.616416
7964 10:01:47.616989 Set Vref, RX VrefLevel [Byte0]: 72
7965 10:01:47.620064 [Byte1]: 72
7966 10:01:47.623948
7967 10:01:47.624515 Set Vref, RX VrefLevel [Byte0]: 73
7968 10:01:47.627564 [Byte1]: 73
7969 10:01:47.631483
7970 10:01:47.631956 Set Vref, RX VrefLevel [Byte0]: 74
7971 10:01:47.635048 [Byte1]: 74
7972 10:01:47.639091
7973 10:01:47.639607 Set Vref, RX VrefLevel [Byte0]: 75
7974 10:01:47.642412 [Byte1]: 75
7975 10:01:47.646714
7976 10:01:47.647285 Set Vref, RX VrefLevel [Byte0]: 76
7977 10:01:47.650328 [Byte1]: 76
7978 10:01:47.654450
7979 10:01:47.655024 Set Vref, RX VrefLevel [Byte0]: 77
7980 10:01:47.657634 [Byte1]: 77
7981 10:01:47.662078
7982 10:01:47.662591 Set Vref, RX VrefLevel [Byte0]: 78
7983 10:01:47.665565 [Byte1]: 78
7984 10:01:47.669738
7985 10:01:47.670367 Set Vref, RX VrefLevel [Byte0]: 79
7986 10:01:47.673421 [Byte1]: 79
7987 10:01:47.677411
7988 10:01:47.677977 Set Vref, RX VrefLevel [Byte0]: 80
7989 10:01:47.680401 [Byte1]: 80
7990 10:01:47.684648
7991 10:01:47.685218 Final RX Vref Byte 0 = 62 to rank0
7992 10:01:47.688104 Final RX Vref Byte 1 = 60 to rank0
7993 10:01:47.691735 Final RX Vref Byte 0 = 62 to rank1
7994 10:01:47.694528 Final RX Vref Byte 1 = 60 to rank1==
7995 10:01:47.697806 Dram Type= 6, Freq= 0, CH_0, rank 0
7996 10:01:47.704535 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7997 10:01:47.705181 ==
7998 10:01:47.705564 DQS Delay:
7999 10:01:47.707603 DQS0 = 0, DQS1 = 0
8000 10:01:47.708068 DQM Delay:
8001 10:01:47.708435 DQM0 = 136, DQM1 = 125
8002 10:01:47.711573 DQ Delay:
8003 10:01:47.714637 DQ0 =136, DQ1 =136, DQ2 =132, DQ3 =134
8004 10:01:47.717892 DQ4 =140, DQ5 =124, DQ6 =146, DQ7 =144
8005 10:01:47.721392 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =118
8006 10:01:47.725036 DQ12 =130, DQ13 =128, DQ14 =136, DQ15 =134
8007 10:01:47.725610
8008 10:01:47.725977
8009 10:01:47.726319
8010 10:01:47.727439 [DramC_TX_OE_Calibration] TA2
8011 10:01:47.731073 Original DQ_B0 (3 6) =30, OEN = 27
8012 10:01:47.734461 Original DQ_B1 (3 6) =30, OEN = 27
8013 10:01:47.737533 24, 0x0, End_B0=24 End_B1=24
8014 10:01:47.738034 25, 0x0, End_B0=25 End_B1=25
8015 10:01:47.740773 26, 0x0, End_B0=26 End_B1=26
8016 10:01:47.744318 27, 0x0, End_B0=27 End_B1=27
8017 10:01:47.747678 28, 0x0, End_B0=28 End_B1=28
8018 10:01:47.751362 29, 0x0, End_B0=29 End_B1=29
8019 10:01:47.751909 30, 0x0, End_B0=30 End_B1=30
8020 10:01:47.753952 31, 0x4545, End_B0=30 End_B1=30
8021 10:01:47.757433 Byte0 end_step=30 best_step=27
8022 10:01:47.760777 Byte1 end_step=30 best_step=27
8023 10:01:47.764195 Byte0 TX OE(2T, 0.5T) = (3, 3)
8024 10:01:47.767537 Byte1 TX OE(2T, 0.5T) = (3, 3)
8025 10:01:47.768117
8026 10:01:47.768497
8027 10:01:47.774054 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
8028 10:01:47.777651 CH0 RK0: MR19=303, MR18=1D1B
8029 10:01:47.784304 CH0_RK0: MR19=0x303, MR18=0x1D1B, DQSOSC=395, MR23=63, INC=23, DEC=15
8030 10:01:47.784888
8031 10:01:47.787514 ----->DramcWriteLeveling(PI) begin...
8032 10:01:47.788108 ==
8033 10:01:47.790647 Dram Type= 6, Freq= 0, CH_0, rank 1
8034 10:01:47.794166 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8035 10:01:47.794675 ==
8036 10:01:47.797100 Write leveling (Byte 0): 37 => 37
8037 10:01:47.800550 Write leveling (Byte 1): 29 => 29
8038 10:01:47.803710 DramcWriteLeveling(PI) end<-----
8039 10:01:47.804282
8040 10:01:47.804660 ==
8041 10:01:47.807286 Dram Type= 6, Freq= 0, CH_0, rank 1
8042 10:01:47.810767 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8043 10:01:47.811343 ==
8044 10:01:47.814205 [Gating] SW mode calibration
8045 10:01:47.820636 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8046 10:01:47.827575 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8047 10:01:47.830653 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8048 10:01:47.837332 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8049 10:01:47.840351 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8050 10:01:47.843472 1 4 12 | B1->B0 | 2424 3333 | 0 1 | (0 0) (1 1)
8051 10:01:47.850296 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8052 10:01:47.853846 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8053 10:01:47.857370 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8054 10:01:47.860371 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8055 10:01:47.866990 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8056 10:01:47.870583 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8057 10:01:47.874044 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8058 10:01:47.880506 1 5 12 | B1->B0 | 3333 2929 | 1 0 | (1 0) (1 0)
8059 10:01:47.883719 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8060 10:01:47.887294 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8061 10:01:47.893528 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8062 10:01:47.896973 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8063 10:01:47.899948 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8064 10:01:47.906833 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8065 10:01:47.910192 1 6 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8066 10:01:47.913980 1 6 12 | B1->B0 | 2b2b 4545 | 1 0 | (0 0) (0 0)
8067 10:01:47.920262 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8068 10:01:47.923587 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8069 10:01:47.927247 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8070 10:01:47.933574 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8071 10:01:47.936550 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8072 10:01:47.939973 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8073 10:01:47.946891 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8074 10:01:47.950062 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8075 10:01:47.953123 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8076 10:01:47.959572 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8077 10:01:47.963307 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 10:01:47.966503 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 10:01:47.973186 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 10:01:47.976395 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 10:01:47.980014 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 10:01:47.986667 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 10:01:47.990020 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 10:01:47.992931 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 10:01:47.999703 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 10:01:48.003092 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 10:01:48.006284 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 10:01:48.010060 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 10:01:48.016549 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8090 10:01:48.019847 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8091 10:01:48.023343 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8092 10:01:48.029842 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8093 10:01:48.033516 Total UI for P1: 0, mck2ui 16
8094 10:01:48.036344 best dqsien dly found for B0: ( 1, 9, 12)
8095 10:01:48.039688 Total UI for P1: 0, mck2ui 16
8096 10:01:48.043046 best dqsien dly found for B1: ( 1, 9, 16)
8097 10:01:48.046578 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8098 10:01:48.049789 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8099 10:01:48.050362
8100 10:01:48.053517 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8101 10:01:48.056208 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8102 10:01:48.059513 [Gating] SW calibration Done
8103 10:01:48.059977 ==
8104 10:01:48.063236 Dram Type= 6, Freq= 0, CH_0, rank 1
8105 10:01:48.066327 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8106 10:01:48.066943 ==
8107 10:01:48.070191 RX Vref Scan: 0
8108 10:01:48.070845
8109 10:01:48.071229 RX Vref 0 -> 0, step: 1
8110 10:01:48.073613
8111 10:01:48.074199 RX Delay 0 -> 252, step: 8
8112 10:01:48.079441 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8113 10:01:48.082976 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8114 10:01:48.086484 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8115 10:01:48.089687 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8116 10:01:48.092842 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8117 10:01:48.096411 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8118 10:01:48.102715 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8119 10:01:48.106223 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8120 10:01:48.109902 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8121 10:01:48.113146 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8122 10:01:48.116726 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8123 10:01:48.122566 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8124 10:01:48.126174 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8125 10:01:48.129529 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8126 10:01:48.132908 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8127 10:01:48.139171 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8128 10:01:48.139734 ==
8129 10:01:48.142460 Dram Type= 6, Freq= 0, CH_0, rank 1
8130 10:01:48.146210 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8131 10:01:48.146846 ==
8132 10:01:48.147228 DQS Delay:
8133 10:01:48.149456 DQS0 = 0, DQS1 = 0
8134 10:01:48.150033 DQM Delay:
8135 10:01:48.152459 DQM0 = 135, DQM1 = 126
8136 10:01:48.152928 DQ Delay:
8137 10:01:48.156032 DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131
8138 10:01:48.159623 DQ4 =135, DQ5 =127, DQ6 =143, DQ7 =143
8139 10:01:48.162727 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =123
8140 10:01:48.165586 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8141 10:01:48.166103
8142 10:01:48.166518
8143 10:01:48.169240 ==
8144 10:01:48.169708 Dram Type= 6, Freq= 0, CH_0, rank 1
8145 10:01:48.175642 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8146 10:01:48.176200 ==
8147 10:01:48.176575
8148 10:01:48.176920
8149 10:01:48.179050 TX Vref Scan disable
8150 10:01:48.179517 == TX Byte 0 ==
8151 10:01:48.182637 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8152 10:01:48.189136 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8153 10:01:48.189720 == TX Byte 1 ==
8154 10:01:48.192452 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8155 10:01:48.199327 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8156 10:01:48.199912 ==
8157 10:01:48.202436 Dram Type= 6, Freq= 0, CH_0, rank 1
8158 10:01:48.205801 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8159 10:01:48.206280 ==
8160 10:01:48.220789
8161 10:01:48.223933 TX Vref early break, caculate TX vref
8162 10:01:48.227605 TX Vref=16, minBit 3, minWin=23, winSum=387
8163 10:01:48.231065 TX Vref=18, minBit 8, minWin=23, winSum=394
8164 10:01:48.234226 TX Vref=20, minBit 8, minWin=24, winSum=408
8165 10:01:48.237969 TX Vref=22, minBit 0, minWin=24, winSum=416
8166 10:01:48.240497 TX Vref=24, minBit 0, minWin=25, winSum=421
8167 10:01:48.247797 TX Vref=26, minBit 0, minWin=26, winSum=432
8168 10:01:48.251342 TX Vref=28, minBit 2, minWin=26, winSum=432
8169 10:01:48.254421 TX Vref=30, minBit 0, minWin=25, winSum=427
8170 10:01:48.257831 TX Vref=32, minBit 0, minWin=25, winSum=419
8171 10:01:48.260829 TX Vref=34, minBit 0, minWin=25, winSum=411
8172 10:01:48.264532 TX Vref=36, minBit 1, minWin=24, winSum=403
8173 10:01:48.270751 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 26
8174 10:01:48.271341
8175 10:01:48.273895 Final TX Range 0 Vref 26
8176 10:01:48.274510
8177 10:01:48.274996 ==
8178 10:01:48.277516 Dram Type= 6, Freq= 0, CH_0, rank 1
8179 10:01:48.280656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8180 10:01:48.281242 ==
8181 10:01:48.281730
8182 10:01:48.282175
8183 10:01:48.284125 TX Vref Scan disable
8184 10:01:48.291042 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8185 10:01:48.291641 == TX Byte 0 ==
8186 10:01:48.294073 u2DelayCellOfst[0]=13 cells (4 PI)
8187 10:01:48.297225 u2DelayCellOfst[1]=20 cells (6 PI)
8188 10:01:48.300286 u2DelayCellOfst[2]=13 cells (4 PI)
8189 10:01:48.303960 u2DelayCellOfst[3]=13 cells (4 PI)
8190 10:01:48.307123 u2DelayCellOfst[4]=10 cells (3 PI)
8191 10:01:48.310433 u2DelayCellOfst[5]=0 cells (0 PI)
8192 10:01:48.313876 u2DelayCellOfst[6]=20 cells (6 PI)
8193 10:01:48.317155 u2DelayCellOfst[7]=17 cells (5 PI)
8194 10:01:48.320250 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8195 10:01:48.323835 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8196 10:01:48.326629 == TX Byte 1 ==
8197 10:01:48.330166 u2DelayCellOfst[8]=0 cells (0 PI)
8198 10:01:48.333999 u2DelayCellOfst[9]=3 cells (1 PI)
8199 10:01:48.334628 u2DelayCellOfst[10]=6 cells (2 PI)
8200 10:01:48.337163 u2DelayCellOfst[11]=3 cells (1 PI)
8201 10:01:48.340232 u2DelayCellOfst[12]=13 cells (4 PI)
8202 10:01:48.343411 u2DelayCellOfst[13]=13 cells (4 PI)
8203 10:01:48.347087 u2DelayCellOfst[14]=13 cells (4 PI)
8204 10:01:48.350697 u2DelayCellOfst[15]=13 cells (4 PI)
8205 10:01:48.357051 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8206 10:01:48.360429 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8207 10:01:48.360998 DramC Write-DBI on
8208 10:01:48.361372 ==
8209 10:01:48.363610 Dram Type= 6, Freq= 0, CH_0, rank 1
8210 10:01:48.370246 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8211 10:01:48.370870 ==
8212 10:01:48.371253
8213 10:01:48.371601
8214 10:01:48.371936 TX Vref Scan disable
8215 10:01:48.374773 == TX Byte 0 ==
8216 10:01:48.377865 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8217 10:01:48.381263 == TX Byte 1 ==
8218 10:01:48.384744 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8219 10:01:48.387345 DramC Write-DBI off
8220 10:01:48.387854
8221 10:01:48.388248 [DATLAT]
8222 10:01:48.388601 Freq=1600, CH0 RK1
8223 10:01:48.388942
8224 10:01:48.390518 DATLAT Default: 0xf
8225 10:01:48.390993 0, 0xFFFF, sum = 0
8226 10:01:48.394020 1, 0xFFFF, sum = 0
8227 10:01:48.394539 2, 0xFFFF, sum = 0
8228 10:01:48.397823 3, 0xFFFF, sum = 0
8229 10:01:48.400854 4, 0xFFFF, sum = 0
8230 10:01:48.401425 5, 0xFFFF, sum = 0
8231 10:01:48.404076 6, 0xFFFF, sum = 0
8232 10:01:48.404571 7, 0xFFFF, sum = 0
8233 10:01:48.407309 8, 0xFFFF, sum = 0
8234 10:01:48.407815 9, 0xFFFF, sum = 0
8235 10:01:48.410455 10, 0xFFFF, sum = 0
8236 10:01:48.410950 11, 0xFFFF, sum = 0
8237 10:01:48.414497 12, 0xFFFF, sum = 0
8238 10:01:48.415074 13, 0xFFFF, sum = 0
8239 10:01:48.417125 14, 0x0, sum = 1
8240 10:01:48.417622 15, 0x0, sum = 2
8241 10:01:48.420548 16, 0x0, sum = 3
8242 10:01:48.421024 17, 0x0, sum = 4
8243 10:01:48.424367 best_step = 15
8244 10:01:48.424942
8245 10:01:48.425317 ==
8246 10:01:48.427234 Dram Type= 6, Freq= 0, CH_0, rank 1
8247 10:01:48.430902 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8248 10:01:48.431479 ==
8249 10:01:48.431855 RX Vref Scan: 0
8250 10:01:48.434089
8251 10:01:48.434704 RX Vref 0 -> 0, step: 1
8252 10:01:48.435085
8253 10:01:48.437242 RX Delay 11 -> 252, step: 4
8254 10:01:48.440917 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8255 10:01:48.447235 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8256 10:01:48.450936 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8257 10:01:48.453810 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8258 10:01:48.457242 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8259 10:01:48.461064 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8260 10:01:48.467097 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8261 10:01:48.471048 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8262 10:01:48.474567 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8263 10:01:48.477700 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8264 10:01:48.481043 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8265 10:01:48.487704 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8266 10:01:48.490547 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8267 10:01:48.493846 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8268 10:01:48.497764 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8269 10:01:48.500784 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8270 10:01:48.504222 ==
8271 10:01:48.504711 Dram Type= 6, Freq= 0, CH_0, rank 1
8272 10:01:48.510580 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8273 10:01:48.511168 ==
8274 10:01:48.511555 DQS Delay:
8275 10:01:48.514255 DQS0 = 0, DQS1 = 0
8276 10:01:48.514884 DQM Delay:
8277 10:01:48.517183 DQM0 = 133, DQM1 = 123
8278 10:01:48.517772 DQ Delay:
8279 10:01:48.520586 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =130
8280 10:01:48.523787 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8281 10:01:48.527092 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8282 10:01:48.530603 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8283 10:01:48.531197
8284 10:01:48.531577
8285 10:01:48.531925
8286 10:01:48.533819 [DramC_TX_OE_Calibration] TA2
8287 10:01:48.536974 Original DQ_B0 (3 6) =30, OEN = 27
8288 10:01:48.540272 Original DQ_B1 (3 6) =30, OEN = 27
8289 10:01:48.544087 24, 0x0, End_B0=24 End_B1=24
8290 10:01:48.546901 25, 0x0, End_B0=25 End_B1=25
8291 10:01:48.547387 26, 0x0, End_B0=26 End_B1=26
8292 10:01:48.550917 27, 0x0, End_B0=27 End_B1=27
8293 10:01:48.553455 28, 0x0, End_B0=28 End_B1=28
8294 10:01:48.557543 29, 0x0, End_B0=29 End_B1=29
8295 10:01:48.558120 30, 0x0, End_B0=30 End_B1=30
8296 10:01:48.560967 31, 0x4141, End_B0=30 End_B1=30
8297 10:01:48.563782 Byte0 end_step=30 best_step=27
8298 10:01:48.566985 Byte1 end_step=30 best_step=27
8299 10:01:48.570513 Byte0 TX OE(2T, 0.5T) = (3, 3)
8300 10:01:48.573731 Byte1 TX OE(2T, 0.5T) = (3, 3)
8301 10:01:48.574309
8302 10:01:48.574731
8303 10:01:48.580256 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e0b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 394 ps
8304 10:01:48.583920 CH0 RK1: MR19=303, MR18=1E0B
8305 10:01:48.590469 CH0_RK1: MR19=0x303, MR18=0x1E0B, DQSOSC=394, MR23=63, INC=23, DEC=15
8306 10:01:48.593610 [RxdqsGatingPostProcess] freq 1600
8307 10:01:48.599953 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8308 10:01:48.600432 best DQS0 dly(2T, 0.5T) = (1, 1)
8309 10:01:48.603310 best DQS1 dly(2T, 0.5T) = (1, 1)
8310 10:01:48.606653 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8311 10:01:48.610023 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8312 10:01:48.613586 best DQS0 dly(2T, 0.5T) = (1, 1)
8313 10:01:48.616932 best DQS1 dly(2T, 0.5T) = (1, 1)
8314 10:01:48.620137 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8315 10:01:48.623448 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8316 10:01:48.626736 Pre-setting of DQS Precalculation
8317 10:01:48.630140 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8318 10:01:48.630761 ==
8319 10:01:48.633514 Dram Type= 6, Freq= 0, CH_1, rank 0
8320 10:01:48.640455 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8321 10:01:48.640937 ==
8322 10:01:48.643022 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8323 10:01:48.650008 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8324 10:01:48.653550 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8325 10:01:48.659876 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8326 10:01:48.667632 [CA 0] Center 40 (11~70) winsize 60
8327 10:01:48.670912 [CA 1] Center 41 (11~71) winsize 61
8328 10:01:48.674436 [CA 2] Center 37 (8~67) winsize 60
8329 10:01:48.677743 [CA 3] Center 36 (7~66) winsize 60
8330 10:01:48.680917 [CA 4] Center 36 (7~66) winsize 60
8331 10:01:48.684013 [CA 5] Center 35 (5~66) winsize 62
8332 10:01:48.684584
8333 10:01:48.687530 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8334 10:01:48.688105
8335 10:01:48.690893 [CATrainingPosCal] consider 1 rank data
8336 10:01:48.693565 u2DelayCellTimex100 = 285/100 ps
8337 10:01:48.696969 CA0 delay=40 (11~70),Diff = 5 PI (17 cell)
8338 10:01:48.704373 CA1 delay=41 (11~71),Diff = 6 PI (20 cell)
8339 10:01:48.707067 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
8340 10:01:48.710691 CA3 delay=36 (7~66),Diff = 1 PI (3 cell)
8341 10:01:48.713846 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
8342 10:01:48.717018 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
8343 10:01:48.717600
8344 10:01:48.720537 CA PerBit enable=1, Macro0, CA PI delay=35
8345 10:01:48.721030
8346 10:01:48.723928 [CBTSetCACLKResult] CA Dly = 35
8347 10:01:48.724483 CS Dly: 9 (0~40)
8348 10:01:48.730362 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8349 10:01:48.734160 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8350 10:01:48.734755 ==
8351 10:01:48.737079 Dram Type= 6, Freq= 0, CH_1, rank 1
8352 10:01:48.740245 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8353 10:01:48.740769 ==
8354 10:01:48.747169 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8355 10:01:48.750425 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8356 10:01:48.757040 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8357 10:01:48.760521 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8358 10:01:48.770923 [CA 0] Center 42 (13~72) winsize 60
8359 10:01:48.773471 [CA 1] Center 42 (13~72) winsize 60
8360 10:01:48.777085 [CA 2] Center 38 (9~68) winsize 60
8361 10:01:48.780251 [CA 3] Center 37 (8~67) winsize 60
8362 10:01:48.783230 [CA 4] Center 39 (10~68) winsize 59
8363 10:01:48.786781 [CA 5] Center 37 (8~67) winsize 60
8364 10:01:48.787219
8365 10:01:48.790042 [CmdBusTrainingLP45] Vref(ca) range 0: 28
8366 10:01:48.790500
8367 10:01:48.793317 [CATrainingPosCal] consider 2 rank data
8368 10:01:48.797049 u2DelayCellTimex100 = 285/100 ps
8369 10:01:48.803286 CA0 delay=41 (13~70),Diff = 4 PI (13 cell)
8370 10:01:48.806650 CA1 delay=42 (13~71),Diff = 5 PI (17 cell)
8371 10:01:48.810007 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8372 10:01:48.813486 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8373 10:01:48.816804 CA4 delay=38 (10~66),Diff = 1 PI (3 cell)
8374 10:01:48.819826 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8375 10:01:48.820421
8376 10:01:48.823131 CA PerBit enable=1, Macro0, CA PI delay=37
8377 10:01:48.823595
8378 10:01:48.826727 [CBTSetCACLKResult] CA Dly = 37
8379 10:01:48.829678 CS Dly: 10 (0~42)
8380 10:01:48.833357 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8381 10:01:48.836495 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8382 10:01:48.836915
8383 10:01:48.839763 ----->DramcWriteLeveling(PI) begin...
8384 10:01:48.840195 ==
8385 10:01:48.843205 Dram Type= 6, Freq= 0, CH_1, rank 0
8386 10:01:48.849538 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8387 10:01:48.849992 ==
8388 10:01:48.852883 Write leveling (Byte 0): 24 => 24
8389 10:01:48.856331 Write leveling (Byte 1): 27 => 27
8390 10:01:48.856856 DramcWriteLeveling(PI) end<-----
8391 10:01:48.860005
8392 10:01:48.860522 ==
8393 10:01:48.862705 Dram Type= 6, Freq= 0, CH_1, rank 0
8394 10:01:48.866204 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8395 10:01:48.866770 ==
8396 10:01:48.869277 [Gating] SW mode calibration
8397 10:01:48.875974 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8398 10:01:48.879402 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8399 10:01:48.886153 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 10:01:48.889571 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8401 10:01:48.892494 1 4 8 | B1->B0 | 2727 2a2a | 0 1 | (0 0) (0 0)
8402 10:01:48.899565 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8403 10:01:48.902713 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8404 10:01:48.906199 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8405 10:01:48.912336 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8406 10:01:48.915809 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8407 10:01:48.919084 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8408 10:01:48.925985 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8409 10:01:48.929245 1 5 8 | B1->B0 | 2727 2626 | 0 0 | (0 1) (0 1)
8410 10:01:48.932595 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8411 10:01:48.938870 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8412 10:01:48.942614 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8413 10:01:48.945708 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8414 10:01:48.952312 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8415 10:01:48.955621 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8416 10:01:48.958983 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8417 10:01:48.965762 1 6 8 | B1->B0 | 3939 4242 | 1 0 | (0 0) (0 0)
8418 10:01:48.968870 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8419 10:01:48.972565 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8420 10:01:48.978784 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8421 10:01:48.982333 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8422 10:01:48.985742 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8423 10:01:48.992557 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8424 10:01:48.995375 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8425 10:01:48.998824 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8426 10:01:49.005459 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8427 10:01:49.008357 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 10:01:49.011779 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 10:01:49.018926 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 10:01:49.021989 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 10:01:49.025079 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 10:01:49.032050 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 10:01:49.034752 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 10:01:49.038241 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 10:01:49.044823 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 10:01:49.047899 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 10:01:49.051684 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 10:01:49.058267 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 10:01:49.061537 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 10:01:49.064850 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8441 10:01:49.071172 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8442 10:01:49.074980 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8443 10:01:49.078123 Total UI for P1: 0, mck2ui 16
8444 10:01:49.081367 best dqsien dly found for B0: ( 1, 9, 6)
8445 10:01:49.084721 Total UI for P1: 0, mck2ui 16
8446 10:01:49.087989 best dqsien dly found for B1: ( 1, 9, 8)
8447 10:01:49.091284 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8448 10:01:49.094761 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8449 10:01:49.095239
8450 10:01:49.098234 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8451 10:01:49.101586 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8452 10:01:49.104898 [Gating] SW calibration Done
8453 10:01:49.105460 ==
8454 10:01:49.108418 Dram Type= 6, Freq= 0, CH_1, rank 0
8455 10:01:49.111433 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8456 10:01:49.111917 ==
8457 10:01:49.114932 RX Vref Scan: 0
8458 10:01:49.115487
8459 10:01:49.115858 RX Vref 0 -> 0, step: 1
8460 10:01:49.118025
8461 10:01:49.118618 RX Delay 0 -> 252, step: 8
8462 10:01:49.121778 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8463 10:01:49.128075 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8464 10:01:49.131380 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8465 10:01:49.134855 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8466 10:01:49.137891 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8467 10:01:49.141009 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8468 10:01:49.147506 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8469 10:01:49.151032 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8470 10:01:49.154351 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8471 10:01:49.158128 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8472 10:01:49.161477 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8473 10:01:49.167873 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8474 10:01:49.170877 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8475 10:01:49.174514 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8476 10:01:49.177790 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8477 10:01:49.181255 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8478 10:01:49.181726 ==
8479 10:01:49.184137 Dram Type= 6, Freq= 0, CH_1, rank 0
8480 10:01:49.190937 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8481 10:01:49.191614 ==
8482 10:01:49.192046 DQS Delay:
8483 10:01:49.194238 DQS0 = 0, DQS1 = 0
8484 10:01:49.194749 DQM Delay:
8485 10:01:49.197469 DQM0 = 138, DQM1 = 131
8486 10:01:49.197935 DQ Delay:
8487 10:01:49.201205 DQ0 =139, DQ1 =135, DQ2 =127, DQ3 =139
8488 10:01:49.204223 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8489 10:01:49.207469 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8490 10:01:49.210828 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8491 10:01:49.211299
8492 10:01:49.211671
8493 10:01:49.212016 ==
8494 10:01:49.214300 Dram Type= 6, Freq= 0, CH_1, rank 0
8495 10:01:49.220824 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8496 10:01:49.221298 ==
8497 10:01:49.221673
8498 10:01:49.222019
8499 10:01:49.222349 TX Vref Scan disable
8500 10:01:49.224185 == TX Byte 0 ==
8501 10:01:49.227565 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8502 10:01:49.230698 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8503 10:01:49.234017 == TX Byte 1 ==
8504 10:01:49.237552 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8505 10:01:49.243984 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8506 10:01:49.244414 ==
8507 10:01:49.247124 Dram Type= 6, Freq= 0, CH_1, rank 0
8508 10:01:49.250424 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8509 10:01:49.250856 ==
8510 10:01:49.263983
8511 10:01:49.267352 TX Vref early break, caculate TX vref
8512 10:01:49.271110 TX Vref=16, minBit 10, minWin=21, winSum=372
8513 10:01:49.273640 TX Vref=18, minBit 10, minWin=21, winSum=377
8514 10:01:49.277314 TX Vref=20, minBit 12, minWin=23, winSum=395
8515 10:01:49.280341 TX Vref=22, minBit 10, minWin=24, winSum=401
8516 10:01:49.287259 TX Vref=24, minBit 10, minWin=24, winSum=413
8517 10:01:49.290653 TX Vref=26, minBit 10, minWin=25, winSum=419
8518 10:01:49.293958 TX Vref=28, minBit 10, minWin=24, winSum=423
8519 10:01:49.297030 TX Vref=30, minBit 8, minWin=25, winSum=417
8520 10:01:49.300566 TX Vref=32, minBit 12, minWin=24, winSum=410
8521 10:01:49.303471 TX Vref=34, minBit 8, minWin=24, winSum=402
8522 10:01:49.310380 TX Vref=36, minBit 12, minWin=23, winSum=392
8523 10:01:49.314275 [TxChooseVref] Worse bit 10, Min win 25, Win sum 419, Final Vref 26
8524 10:01:49.317194
8525 10:01:49.317786 Final TX Range 0 Vref 26
8526 10:01:49.318283
8527 10:01:49.318786 ==
8528 10:01:49.320083 Dram Type= 6, Freq= 0, CH_1, rank 0
8529 10:01:49.327367 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8530 10:01:49.327972 ==
8531 10:01:49.328468
8532 10:01:49.328927
8533 10:01:49.329373 TX Vref Scan disable
8534 10:01:49.334338 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8535 10:01:49.334985 == TX Byte 0 ==
8536 10:01:49.337652 u2DelayCellOfst[0]=17 cells (5 PI)
8537 10:01:49.340613 u2DelayCellOfst[1]=13 cells (4 PI)
8538 10:01:49.344235 u2DelayCellOfst[2]=0 cells (0 PI)
8539 10:01:49.347568 u2DelayCellOfst[3]=10 cells (3 PI)
8540 10:01:49.350997 u2DelayCellOfst[4]=10 cells (3 PI)
8541 10:01:49.354249 u2DelayCellOfst[5]=20 cells (6 PI)
8542 10:01:49.357463 u2DelayCellOfst[6]=20 cells (6 PI)
8543 10:01:49.360972 u2DelayCellOfst[7]=10 cells (3 PI)
8544 10:01:49.363925 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8545 10:01:49.367245 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8546 10:01:49.370586 == TX Byte 1 ==
8547 10:01:49.373982 u2DelayCellOfst[8]=0 cells (0 PI)
8548 10:01:49.377124 u2DelayCellOfst[9]=3 cells (1 PI)
8549 10:01:49.380588 u2DelayCellOfst[10]=10 cells (3 PI)
8550 10:01:49.383761 u2DelayCellOfst[11]=3 cells (1 PI)
8551 10:01:49.384258 u2DelayCellOfst[12]=13 cells (4 PI)
8552 10:01:49.387227 u2DelayCellOfst[13]=17 cells (5 PI)
8553 10:01:49.390363 u2DelayCellOfst[14]=20 cells (6 PI)
8554 10:01:49.394107 u2DelayCellOfst[15]=20 cells (6 PI)
8555 10:01:49.400356 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8556 10:01:49.403969 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8557 10:01:49.404551 DramC Write-DBI on
8558 10:01:49.406997 ==
8559 10:01:49.410551 Dram Type= 6, Freq= 0, CH_1, rank 0
8560 10:01:49.414050 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8561 10:01:49.414669 ==
8562 10:01:49.415058
8563 10:01:49.415407
8564 10:01:49.417286 TX Vref Scan disable
8565 10:01:49.417852 == TX Byte 0 ==
8566 10:01:49.423954 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8567 10:01:49.424536 == TX Byte 1 ==
8568 10:01:49.427293 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8569 10:01:49.430320 DramC Write-DBI off
8570 10:01:49.430965
8571 10:01:49.431346 [DATLAT]
8572 10:01:49.433603 Freq=1600, CH1 RK0
8573 10:01:49.434077
8574 10:01:49.434521 DATLAT Default: 0xf
8575 10:01:49.436924 0, 0xFFFF, sum = 0
8576 10:01:49.437499 1, 0xFFFF, sum = 0
8577 10:01:49.440214 2, 0xFFFF, sum = 0
8578 10:01:49.440698 3, 0xFFFF, sum = 0
8579 10:01:49.444056 4, 0xFFFF, sum = 0
8580 10:01:49.444638 5, 0xFFFF, sum = 0
8581 10:01:49.447009 6, 0xFFFF, sum = 0
8582 10:01:49.447495 7, 0xFFFF, sum = 0
8583 10:01:49.450271 8, 0xFFFF, sum = 0
8584 10:01:49.450855 9, 0xFFFF, sum = 0
8585 10:01:49.453594 10, 0xFFFF, sum = 0
8586 10:01:49.457038 11, 0xFFFF, sum = 0
8587 10:01:49.457616 12, 0xFFFF, sum = 0
8588 10:01:49.460002 13, 0xFFFF, sum = 0
8589 10:01:49.460483 14, 0x0, sum = 1
8590 10:01:49.463666 15, 0x0, sum = 2
8591 10:01:49.464250 16, 0x0, sum = 3
8592 10:01:49.466901 17, 0x0, sum = 4
8593 10:01:49.467480 best_step = 15
8594 10:01:49.467860
8595 10:01:49.468210 ==
8596 10:01:49.470428 Dram Type= 6, Freq= 0, CH_1, rank 0
8597 10:01:49.473714 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8598 10:01:49.474294 ==
8599 10:01:49.476977 RX Vref Scan: 1
8600 10:01:49.477490
8601 10:01:49.480327 Set Vref Range= 24 -> 127
8602 10:01:49.480804
8603 10:01:49.481177 RX Vref 24 -> 127, step: 1
8604 10:01:49.481527
8605 10:01:49.483661 RX Delay 19 -> 252, step: 4
8606 10:01:49.484135
8607 10:01:49.487040 Set Vref, RX VrefLevel [Byte0]: 24
8608 10:01:49.490345 [Byte1]: 24
8609 10:01:49.490899
8610 10:01:49.493756 Set Vref, RX VrefLevel [Byte0]: 25
8611 10:01:49.496705 [Byte1]: 25
8612 10:01:49.500929
8613 10:01:49.501403 Set Vref, RX VrefLevel [Byte0]: 26
8614 10:01:49.504090 [Byte1]: 26
8615 10:01:49.508638
8616 10:01:49.509108 Set Vref, RX VrefLevel [Byte0]: 27
8617 10:01:49.511899 [Byte1]: 27
8618 10:01:49.515971
8619 10:01:49.516535 Set Vref, RX VrefLevel [Byte0]: 28
8620 10:01:49.519655 [Byte1]: 28
8621 10:01:49.523621
8622 10:01:49.524191 Set Vref, RX VrefLevel [Byte0]: 29
8623 10:01:49.526993 [Byte1]: 29
8624 10:01:49.531559
8625 10:01:49.532130 Set Vref, RX VrefLevel [Byte0]: 30
8626 10:01:49.534594 [Byte1]: 30
8627 10:01:49.538975
8628 10:01:49.539538 Set Vref, RX VrefLevel [Byte0]: 31
8629 10:01:49.541904 [Byte1]: 31
8630 10:01:49.546371
8631 10:01:49.546976 Set Vref, RX VrefLevel [Byte0]: 32
8632 10:01:49.549450 [Byte1]: 32
8633 10:01:49.554247
8634 10:01:49.554851 Set Vref, RX VrefLevel [Byte0]: 33
8635 10:01:49.557202 [Byte1]: 33
8636 10:01:49.561903
8637 10:01:49.562535 Set Vref, RX VrefLevel [Byte0]: 34
8638 10:01:49.564938 [Byte1]: 34
8639 10:01:49.569206
8640 10:01:49.569780 Set Vref, RX VrefLevel [Byte0]: 35
8641 10:01:49.572847 [Byte1]: 35
8642 10:01:49.576860
8643 10:01:49.577431 Set Vref, RX VrefLevel [Byte0]: 36
8644 10:01:49.580023 [Byte1]: 36
8645 10:01:49.584480
8646 10:01:49.585052 Set Vref, RX VrefLevel [Byte0]: 37
8647 10:01:49.587686 [Byte1]: 37
8648 10:01:49.591829
8649 10:01:49.592407 Set Vref, RX VrefLevel [Byte0]: 38
8650 10:01:49.595131 [Byte1]: 38
8651 10:01:49.599215
8652 10:01:49.599687 Set Vref, RX VrefLevel [Byte0]: 39
8653 10:01:49.602757 [Byte1]: 39
8654 10:01:49.606792
8655 10:01:49.607361 Set Vref, RX VrefLevel [Byte0]: 40
8656 10:01:49.610463 [Byte1]: 40
8657 10:01:49.614489
8658 10:01:49.615053 Set Vref, RX VrefLevel [Byte0]: 41
8659 10:01:49.617822 [Byte1]: 41
8660 10:01:49.622178
8661 10:01:49.622808 Set Vref, RX VrefLevel [Byte0]: 42
8662 10:01:49.625016 [Byte1]: 42
8663 10:01:49.629851
8664 10:01:49.630459 Set Vref, RX VrefLevel [Byte0]: 43
8665 10:01:49.633545 [Byte1]: 43
8666 10:01:49.637144
8667 10:01:49.637714 Set Vref, RX VrefLevel [Byte0]: 44
8668 10:01:49.640570 [Byte1]: 44
8669 10:01:49.644734
8670 10:01:49.645208 Set Vref, RX VrefLevel [Byte0]: 45
8671 10:01:49.648241 [Byte1]: 45
8672 10:01:49.652594
8673 10:01:49.653164 Set Vref, RX VrefLevel [Byte0]: 46
8674 10:01:49.655874 [Byte1]: 46
8675 10:01:49.660195
8676 10:01:49.660764 Set Vref, RX VrefLevel [Byte0]: 47
8677 10:01:49.662997 [Byte1]: 47
8678 10:01:49.667654
8679 10:01:49.668220 Set Vref, RX VrefLevel [Byte0]: 48
8680 10:01:49.670912 [Byte1]: 48
8681 10:01:49.675133
8682 10:01:49.675705 Set Vref, RX VrefLevel [Byte0]: 49
8683 10:01:49.678374 [Byte1]: 49
8684 10:01:49.682670
8685 10:01:49.683237 Set Vref, RX VrefLevel [Byte0]: 50
8686 10:01:49.685768 [Byte1]: 50
8687 10:01:49.690179
8688 10:01:49.690777 Set Vref, RX VrefLevel [Byte0]: 51
8689 10:01:49.693541 [Byte1]: 51
8690 10:01:49.697456
8691 10:01:49.697930 Set Vref, RX VrefLevel [Byte0]: 52
8692 10:01:49.700725 [Byte1]: 52
8693 10:01:49.705488
8694 10:01:49.708439 Set Vref, RX VrefLevel [Byte0]: 53
8695 10:01:49.711974 [Byte1]: 53
8696 10:01:49.712546
8697 10:01:49.715097 Set Vref, RX VrefLevel [Byte0]: 54
8698 10:01:49.718610 [Byte1]: 54
8699 10:01:49.719180
8700 10:01:49.721787 Set Vref, RX VrefLevel [Byte0]: 55
8701 10:01:49.725025 [Byte1]: 55
8702 10:01:49.725519
8703 10:01:49.728645 Set Vref, RX VrefLevel [Byte0]: 56
8704 10:01:49.731738 [Byte1]: 56
8705 10:01:49.735802
8706 10:01:49.736372 Set Vref, RX VrefLevel [Byte0]: 57
8707 10:01:49.738780 [Byte1]: 57
8708 10:01:49.743034
8709 10:01:49.743499 Set Vref, RX VrefLevel [Byte0]: 58
8710 10:01:49.746475 [Byte1]: 58
8711 10:01:49.750572
8712 10:01:49.751052 Set Vref, RX VrefLevel [Byte0]: 59
8713 10:01:49.753956 [Byte1]: 59
8714 10:01:49.758424
8715 10:01:49.758997 Set Vref, RX VrefLevel [Byte0]: 60
8716 10:01:49.761880 [Byte1]: 60
8717 10:01:49.765800
8718 10:01:49.766361 Set Vref, RX VrefLevel [Byte0]: 61
8719 10:01:49.769567 [Byte1]: 61
8720 10:01:49.773877
8721 10:01:49.774492 Set Vref, RX VrefLevel [Byte0]: 62
8722 10:01:49.777324 [Byte1]: 62
8723 10:01:49.781064
8724 10:01:49.781632 Set Vref, RX VrefLevel [Byte0]: 63
8725 10:01:49.784582 [Byte1]: 63
8726 10:01:49.788705
8727 10:01:49.789273 Set Vref, RX VrefLevel [Byte0]: 64
8728 10:01:49.791994 [Byte1]: 64
8729 10:01:49.796400
8730 10:01:49.797009 Set Vref, RX VrefLevel [Byte0]: 65
8731 10:01:49.799240 [Byte1]: 65
8732 10:01:49.803795
8733 10:01:49.804378 Set Vref, RX VrefLevel [Byte0]: 66
8734 10:01:49.807125 [Byte1]: 66
8735 10:01:49.811582
8736 10:01:49.812049 Set Vref, RX VrefLevel [Byte0]: 67
8737 10:01:49.814447 [Byte1]: 67
8738 10:01:49.818612
8739 10:01:49.819077 Set Vref, RX VrefLevel [Byte0]: 68
8740 10:01:49.822488 [Byte1]: 68
8741 10:01:49.826453
8742 10:01:49.826920 Set Vref, RX VrefLevel [Byte0]: 69
8743 10:01:49.829793 [Byte1]: 69
8744 10:01:49.834276
8745 10:01:49.834894 Set Vref, RX VrefLevel [Byte0]: 70
8746 10:01:49.837433 [Byte1]: 70
8747 10:01:49.841670
8748 10:01:49.842139 Set Vref, RX VrefLevel [Byte0]: 71
8749 10:01:49.844693 [Byte1]: 71
8750 10:01:49.849189
8751 10:01:49.849788 Set Vref, RX VrefLevel [Byte0]: 72
8752 10:01:49.852517 [Byte1]: 72
8753 10:01:49.856719
8754 10:01:49.857287 Set Vref, RX VrefLevel [Byte0]: 73
8755 10:01:49.860346 [Byte1]: 73
8756 10:01:49.864511
8757 10:01:49.865082 Set Vref, RX VrefLevel [Byte0]: 74
8758 10:01:49.867844 [Byte1]: 74
8759 10:01:49.872230
8760 10:01:49.872795 Set Vref, RX VrefLevel [Byte0]: 75
8761 10:01:49.875240 [Byte1]: 75
8762 10:01:49.879616
8763 10:01:49.880185 Set Vref, RX VrefLevel [Byte0]: 76
8764 10:01:49.882923 [Byte1]: 76
8765 10:01:49.887235
8766 10:01:49.887807 Set Vref, RX VrefLevel [Byte0]: 77
8767 10:01:49.890556 [Byte1]: 77
8768 10:01:49.895345
8769 10:01:49.895911 Final RX Vref Byte 0 = 53 to rank0
8770 10:01:49.898041 Final RX Vref Byte 1 = 62 to rank0
8771 10:01:49.901338 Final RX Vref Byte 0 = 53 to rank1
8772 10:01:49.904728 Final RX Vref Byte 1 = 62 to rank1==
8773 10:01:49.907872 Dram Type= 6, Freq= 0, CH_1, rank 0
8774 10:01:49.914851 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8775 10:01:49.915326 ==
8776 10:01:49.915696 DQS Delay:
8777 10:01:49.916041 DQS0 = 0, DQS1 = 0
8778 10:01:49.918556 DQM Delay:
8779 10:01:49.919123 DQM0 = 133, DQM1 = 129
8780 10:01:49.921368 DQ Delay:
8781 10:01:49.924480 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8782 10:01:49.928150 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
8783 10:01:49.931177 DQ8 =116, DQ9 =120, DQ10 =134, DQ11 =122
8784 10:01:49.934875 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =136
8785 10:01:49.935344
8786 10:01:49.935713
8787 10:01:49.936052
8788 10:01:49.937959 [DramC_TX_OE_Calibration] TA2
8789 10:01:49.941072 Original DQ_B0 (3 6) =30, OEN = 27
8790 10:01:49.944327 Original DQ_B1 (3 6) =30, OEN = 27
8791 10:01:49.947673 24, 0x0, End_B0=24 End_B1=24
8792 10:01:49.948250 25, 0x0, End_B0=25 End_B1=25
8793 10:01:49.950844 26, 0x0, End_B0=26 End_B1=26
8794 10:01:49.954566 27, 0x0, End_B0=27 End_B1=27
8795 10:01:49.957814 28, 0x0, End_B0=28 End_B1=28
8796 10:01:49.958433 29, 0x0, End_B0=29 End_B1=29
8797 10:01:49.961350 30, 0x0, End_B0=30 End_B1=30
8798 10:01:49.965063 31, 0x4141, End_B0=30 End_B1=30
8799 10:01:49.967932 Byte0 end_step=30 best_step=27
8800 10:01:49.971338 Byte1 end_step=30 best_step=27
8801 10:01:49.974913 Byte0 TX OE(2T, 0.5T) = (3, 3)
8802 10:01:49.975483 Byte1 TX OE(2T, 0.5T) = (3, 3)
8803 10:01:49.977850
8804 10:01:49.978453
8805 10:01:49.984666 [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8806 10:01:49.988001 CH1 RK0: MR19=303, MR18=1826
8807 10:01:49.994774 CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16
8808 10:01:49.995346
8809 10:01:49.997604 ----->DramcWriteLeveling(PI) begin...
8810 10:01:49.998186 ==
8811 10:01:50.001434 Dram Type= 6, Freq= 0, CH_1, rank 1
8812 10:01:50.004527 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8813 10:01:50.005106 ==
8814 10:01:50.007621 Write leveling (Byte 0): 24 => 24
8815 10:01:50.010841 Write leveling (Byte 1): 27 => 27
8816 10:01:50.014335 DramcWriteLeveling(PI) end<-----
8817 10:01:50.015083
8818 10:01:50.015470 ==
8819 10:01:50.017823 Dram Type= 6, Freq= 0, CH_1, rank 1
8820 10:01:50.020844 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8821 10:01:50.021427 ==
8822 10:01:50.024396 [Gating] SW mode calibration
8823 10:01:50.031181 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8824 10:01:50.037878 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8825 10:01:50.041431 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8826 10:01:50.044375 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8827 10:01:50.050964 1 4 8 | B1->B0 | 3030 2323 | 1 0 | (1 1) (0 0)
8828 10:01:50.054177 1 4 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
8829 10:01:50.057813 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8830 10:01:50.064450 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8831 10:01:50.067794 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8832 10:01:50.071246 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8833 10:01:50.077613 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8834 10:01:50.081101 1 5 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8835 10:01:50.084543 1 5 8 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 0)
8836 10:01:50.091031 1 5 12 | B1->B0 | 2323 3030 | 0 0 | (1 0) (0 1)
8837 10:01:50.094280 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8838 10:01:50.097787 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8839 10:01:50.104207 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8840 10:01:50.107357 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8841 10:01:50.110911 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8842 10:01:50.117569 1 6 4 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
8843 10:01:50.120478 1 6 8 | B1->B0 | 4545 2424 | 0 0 | (0 0) (0 0)
8844 10:01:50.123723 1 6 12 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
8845 10:01:50.130509 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8846 10:01:50.134298 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8847 10:01:50.137069 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8848 10:01:50.144181 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8849 10:01:50.147048 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8850 10:01:50.150246 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8851 10:01:50.154006 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8852 10:01:50.160208 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8853 10:01:50.163806 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8854 10:01:50.166846 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 10:01:50.173981 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 10:01:50.177617 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 10:01:50.180537 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 10:01:50.187023 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 10:01:50.190751 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 10:01:50.194112 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 10:01:50.200421 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 10:01:50.203878 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 10:01:50.206662 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 10:01:50.213212 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 10:01:50.216764 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 10:01:50.219551 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 10:01:50.226548 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8868 10:01:50.229852 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8869 10:01:50.232817 Total UI for P1: 0, mck2ui 16
8870 10:01:50.236433 best dqsien dly found for B0: ( 1, 9, 8)
8871 10:01:50.239848 Total UI for P1: 0, mck2ui 16
8872 10:01:50.243255 best dqsien dly found for B1: ( 1, 9, 8)
8873 10:01:50.246551 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8874 10:01:50.249654 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8875 10:01:50.250189
8876 10:01:50.253234 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8877 10:01:50.256641 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8878 10:01:50.259929 [Gating] SW calibration Done
8879 10:01:50.260397 ==
8880 10:01:50.263573 Dram Type= 6, Freq= 0, CH_1, rank 1
8881 10:01:50.266701 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8882 10:01:50.267191 ==
8883 10:01:50.270064 RX Vref Scan: 0
8884 10:01:50.270686
8885 10:01:50.273202 RX Vref 0 -> 0, step: 1
8886 10:01:50.273668
8887 10:01:50.274038 RX Delay 0 -> 252, step: 8
8888 10:01:50.279930 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8889 10:01:50.283612 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8890 10:01:50.286470 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8891 10:01:50.290230 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8892 10:01:50.292604 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8893 10:01:50.300317 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8894 10:01:50.303582 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8895 10:01:50.306445 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8896 10:01:50.309701 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8897 10:01:50.312980 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8898 10:01:50.320133 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8899 10:01:50.323037 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8900 10:01:50.326328 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8901 10:01:50.329758 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8902 10:01:50.333484 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8903 10:01:50.339474 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8904 10:01:50.339963 ==
8905 10:01:50.343150 Dram Type= 6, Freq= 0, CH_1, rank 1
8906 10:01:50.346145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8907 10:01:50.346680 ==
8908 10:01:50.347061 DQS Delay:
8909 10:01:50.349089 DQS0 = 0, DQS1 = 0
8910 10:01:50.349550 DQM Delay:
8911 10:01:50.352540 DQM0 = 136, DQM1 = 132
8912 10:01:50.353008 DQ Delay:
8913 10:01:50.356203 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8914 10:01:50.359559 DQ4 =135, DQ5 =147, DQ6 =139, DQ7 =139
8915 10:01:50.362987 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8916 10:01:50.366147 DQ12 =143, DQ13 =139, DQ14 =139, DQ15 =143
8917 10:01:50.369509
8918 10:01:50.369971
8919 10:01:50.370340 ==
8920 10:01:50.372475 Dram Type= 6, Freq= 0, CH_1, rank 1
8921 10:01:50.375937 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8922 10:01:50.376409 ==
8923 10:01:50.376780
8924 10:01:50.377126
8925 10:01:50.379286 TX Vref Scan disable
8926 10:01:50.379833 == TX Byte 0 ==
8927 10:01:50.386216 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8928 10:01:50.389790 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8929 10:01:50.390363 == TX Byte 1 ==
8930 10:01:50.396202 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8931 10:01:50.399430 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8932 10:01:50.400005 ==
8933 10:01:50.402903 Dram Type= 6, Freq= 0, CH_1, rank 1
8934 10:01:50.406216 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8935 10:01:50.406830 ==
8936 10:01:50.420596
8937 10:01:50.423934 TX Vref early break, caculate TX vref
8938 10:01:50.427145 TX Vref=16, minBit 9, minWin=23, winSum=385
8939 10:01:50.430756 TX Vref=18, minBit 10, minWin=23, winSum=398
8940 10:01:50.434326 TX Vref=20, minBit 13, minWin=23, winSum=405
8941 10:01:50.437422 TX Vref=22, minBit 9, minWin=24, winSum=411
8942 10:01:50.440483 TX Vref=24, minBit 10, minWin=25, winSum=419
8943 10:01:50.447087 TX Vref=26, minBit 9, minWin=25, winSum=425
8944 10:01:50.450982 TX Vref=28, minBit 15, minWin=25, winSum=425
8945 10:01:50.453703 TX Vref=30, minBit 15, minWin=25, winSum=422
8946 10:01:50.457109 TX Vref=32, minBit 1, minWin=25, winSum=415
8947 10:01:50.460311 TX Vref=34, minBit 0, minWin=24, winSum=407
8948 10:01:50.464047 TX Vref=36, minBit 10, minWin=23, winSum=396
8949 10:01:50.470427 [TxChooseVref] Worse bit 9, Min win 25, Win sum 425, Final Vref 26
8950 10:01:50.470905
8951 10:01:50.473570 Final TX Range 0 Vref 26
8952 10:01:50.474040
8953 10:01:50.474514 ==
8954 10:01:50.477202 Dram Type= 6, Freq= 0, CH_1, rank 1
8955 10:01:50.480600 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8956 10:01:50.481180 ==
8957 10:01:50.481551
8958 10:01:50.484034
8959 10:01:50.484658 TX Vref Scan disable
8960 10:01:50.490603 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8961 10:01:50.491076 == TX Byte 0 ==
8962 10:01:50.493952 u2DelayCellOfst[0]=13 cells (4 PI)
8963 10:01:50.497412 u2DelayCellOfst[1]=10 cells (3 PI)
8964 10:01:50.500795 u2DelayCellOfst[2]=0 cells (0 PI)
8965 10:01:50.504158 u2DelayCellOfst[3]=3 cells (1 PI)
8966 10:01:50.507037 u2DelayCellOfst[4]=6 cells (2 PI)
8967 10:01:50.510453 u2DelayCellOfst[5]=17 cells (5 PI)
8968 10:01:50.513741 u2DelayCellOfst[6]=17 cells (5 PI)
8969 10:01:50.516894 u2DelayCellOfst[7]=3 cells (1 PI)
8970 10:01:50.520873 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8971 10:01:50.523659 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8972 10:01:50.527352 == TX Byte 1 ==
8973 10:01:50.530895 u2DelayCellOfst[8]=0 cells (0 PI)
8974 10:01:50.533872 u2DelayCellOfst[9]=3 cells (1 PI)
8975 10:01:50.534479 u2DelayCellOfst[10]=10 cells (3 PI)
8976 10:01:50.536860 u2DelayCellOfst[11]=3 cells (1 PI)
8977 10:01:50.540243 u2DelayCellOfst[12]=13 cells (4 PI)
8978 10:01:50.543739 u2DelayCellOfst[13]=17 cells (5 PI)
8979 10:01:50.546990 u2DelayCellOfst[14]=17 cells (5 PI)
8980 10:01:50.550485 u2DelayCellOfst[15]=17 cells (5 PI)
8981 10:01:50.556826 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8982 10:01:50.560015 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8983 10:01:50.560583 DramC Write-DBI on
8984 10:01:50.560957 ==
8985 10:01:50.562826 Dram Type= 6, Freq= 0, CH_1, rank 1
8986 10:01:50.569594 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8987 10:01:50.570154 ==
8988 10:01:50.570572
8989 10:01:50.570925
8990 10:01:50.572925 TX Vref Scan disable
8991 10:01:50.573453 == TX Byte 0 ==
8992 10:01:50.579538 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8993 10:01:50.580123 == TX Byte 1 ==
8994 10:01:50.582746 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8995 10:01:50.586444 DramC Write-DBI off
8996 10:01:50.587060
8997 10:01:50.587470 [DATLAT]
8998 10:01:50.589450 Freq=1600, CH1 RK1
8999 10:01:50.589927
9000 10:01:50.590303 DATLAT Default: 0xf
9001 10:01:50.592778 0, 0xFFFF, sum = 0
9002 10:01:50.593268 1, 0xFFFF, sum = 0
9003 10:01:50.596643 2, 0xFFFF, sum = 0
9004 10:01:50.597226 3, 0xFFFF, sum = 0
9005 10:01:50.599415 4, 0xFFFF, sum = 0
9006 10:01:50.599900 5, 0xFFFF, sum = 0
9007 10:01:50.602718 6, 0xFFFF, sum = 0
9008 10:01:50.603215 7, 0xFFFF, sum = 0
9009 10:01:50.606211 8, 0xFFFF, sum = 0
9010 10:01:50.606777 9, 0xFFFF, sum = 0
9011 10:01:50.609439 10, 0xFFFF, sum = 0
9012 10:01:50.609914 11, 0xFFFF, sum = 0
9013 10:01:50.613060 12, 0xFFFF, sum = 0
9014 10:01:50.616034 13, 0xFFFF, sum = 0
9015 10:01:50.616510 14, 0x0, sum = 1
9016 10:01:50.619485 15, 0x0, sum = 2
9017 10:01:50.619957 16, 0x0, sum = 3
9018 10:01:50.620329 17, 0x0, sum = 4
9019 10:01:50.622499 best_step = 15
9020 10:01:50.622962
9021 10:01:50.623331 ==
9022 10:01:50.626441 Dram Type= 6, Freq= 0, CH_1, rank 1
9023 10:01:50.629194 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9024 10:01:50.629662 ==
9025 10:01:50.632923 RX Vref Scan: 0
9026 10:01:50.633389
9027 10:01:50.633756 RX Vref 0 -> 0, step: 1
9028 10:01:50.636489
9029 10:01:50.637056 RX Delay 19 -> 252, step: 4
9030 10:01:50.643032 iDelay=195, Bit 0, Center 138 (95 ~ 182) 88
9031 10:01:50.646311 iDelay=195, Bit 1, Center 130 (87 ~ 174) 88
9032 10:01:50.649950 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
9033 10:01:50.652989 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9034 10:01:50.656253 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9035 10:01:50.662838 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9036 10:01:50.665590 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
9037 10:01:50.669089 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
9038 10:01:50.672488 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
9039 10:01:50.676147 iDelay=195, Bit 9, Center 120 (71 ~ 170) 100
9040 10:01:50.682219 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9041 10:01:50.685685 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
9042 10:01:50.689246 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9043 10:01:50.692328 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9044 10:01:50.696057 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9045 10:01:50.702271 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
9046 10:01:50.702800 ==
9047 10:01:50.706111 Dram Type= 6, Freq= 0, CH_1, rank 1
9048 10:01:50.709209 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9049 10:01:50.709785 ==
9050 10:01:50.710164 DQS Delay:
9051 10:01:50.712860 DQS0 = 0, DQS1 = 0
9052 10:01:50.713350 DQM Delay:
9053 10:01:50.715916 DQM0 = 133, DQM1 = 130
9054 10:01:50.716380 DQ Delay:
9055 10:01:50.718903 DQ0 =138, DQ1 =130, DQ2 =120, DQ3 =130
9056 10:01:50.722069 DQ4 =134, DQ5 =146, DQ6 =142, DQ7 =130
9057 10:01:50.725877 DQ8 =112, DQ9 =120, DQ10 =130, DQ11 =126
9058 10:01:50.729125 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
9059 10:01:50.729597
9060 10:01:50.729963
9061 10:01:50.732410
9062 10:01:50.732881 [DramC_TX_OE_Calibration] TA2
9063 10:01:50.735613 Original DQ_B0 (3 6) =30, OEN = 27
9064 10:01:50.739102 Original DQ_B1 (3 6) =30, OEN = 27
9065 10:01:50.741988 24, 0x0, End_B0=24 End_B1=24
9066 10:01:50.745605 25, 0x0, End_B0=25 End_B1=25
9067 10:01:50.748967 26, 0x0, End_B0=26 End_B1=26
9068 10:01:50.749300 27, 0x0, End_B0=27 End_B1=27
9069 10:01:50.751969 28, 0x0, End_B0=28 End_B1=28
9070 10:01:50.755220 29, 0x0, End_B0=29 End_B1=29
9071 10:01:50.758723 30, 0x0, End_B0=30 End_B1=30
9072 10:01:50.758920 31, 0x5151, End_B0=30 End_B1=30
9073 10:01:50.762136 Byte0 end_step=30 best_step=27
9074 10:01:50.765200 Byte1 end_step=30 best_step=27
9075 10:01:50.768740 Byte0 TX OE(2T, 0.5T) = (3, 3)
9076 10:01:50.771947 Byte1 TX OE(2T, 0.5T) = (3, 3)
9077 10:01:50.772139
9078 10:01:50.772292
9079 10:01:50.778368 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
9080 10:01:50.781548 CH1 RK1: MR19=303, MR18=1C07
9081 10:01:50.788309 CH1_RK1: MR19=0x303, MR18=0x1C07, DQSOSC=395, MR23=63, INC=23, DEC=15
9082 10:01:50.791682 [RxdqsGatingPostProcess] freq 1600
9083 10:01:50.798312 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9084 10:01:50.801668 best DQS0 dly(2T, 0.5T) = (1, 1)
9085 10:01:50.801828 best DQS1 dly(2T, 0.5T) = (1, 1)
9086 10:01:50.804748 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9087 10:01:50.808120 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9088 10:01:50.811436 best DQS0 dly(2T, 0.5T) = (1, 1)
9089 10:01:50.815133 best DQS1 dly(2T, 0.5T) = (1, 1)
9090 10:01:50.818399 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9091 10:01:50.821450 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9092 10:01:50.824673 Pre-setting of DQS Precalculation
9093 10:01:50.828145 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9094 10:01:50.837932 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9095 10:01:50.844969 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9096 10:01:50.845141
9097 10:01:50.845270
9098 10:01:50.847811 [Calibration Summary] 3200 Mbps
9099 10:01:50.847970 CH 0, Rank 0
9100 10:01:50.851259 SW Impedance : PASS
9101 10:01:50.851417 DUTY Scan : NO K
9102 10:01:50.855059 ZQ Calibration : PASS
9103 10:01:50.857932 Jitter Meter : NO K
9104 10:01:50.858084 CBT Training : PASS
9105 10:01:50.861191 Write leveling : PASS
9106 10:01:50.864819 RX DQS gating : PASS
9107 10:01:50.865072 RX DQ/DQS(RDDQC) : PASS
9108 10:01:50.868124 TX DQ/DQS : PASS
9109 10:01:50.871410 RX DATLAT : PASS
9110 10:01:50.871573 RX DQ/DQS(Engine): PASS
9111 10:01:50.874492 TX OE : PASS
9112 10:01:50.874694 All Pass.
9113 10:01:50.874873
9114 10:01:50.877914 CH 0, Rank 1
9115 10:01:50.878131 SW Impedance : PASS
9116 10:01:50.881016 DUTY Scan : NO K
9117 10:01:50.884545 ZQ Calibration : PASS
9118 10:01:50.884720 Jitter Meter : NO K
9119 10:01:50.887687 CBT Training : PASS
9120 10:01:50.891186 Write leveling : PASS
9121 10:01:50.891349 RX DQS gating : PASS
9122 10:01:50.894373 RX DQ/DQS(RDDQC) : PASS
9123 10:01:50.894596 TX DQ/DQS : PASS
9124 10:01:50.897592 RX DATLAT : PASS
9125 10:01:50.900934 RX DQ/DQS(Engine): PASS
9126 10:01:50.901106 TX OE : PASS
9127 10:01:50.904557 All Pass.
9128 10:01:50.904774
9129 10:01:50.904925 CH 1, Rank 0
9130 10:01:50.907977 SW Impedance : PASS
9131 10:01:50.908140 DUTY Scan : NO K
9132 10:01:50.910873 ZQ Calibration : PASS
9133 10:01:50.914678 Jitter Meter : NO K
9134 10:01:50.914848 CBT Training : PASS
9135 10:01:50.917568 Write leveling : PASS
9136 10:01:50.921001 RX DQS gating : PASS
9137 10:01:50.921154 RX DQ/DQS(RDDQC) : PASS
9138 10:01:50.924559 TX DQ/DQS : PASS
9139 10:01:50.928073 RX DATLAT : PASS
9140 10:01:50.928237 RX DQ/DQS(Engine): PASS
9141 10:01:50.931310 TX OE : PASS
9142 10:01:50.931395 All Pass.
9143 10:01:50.931461
9144 10:01:50.934504 CH 1, Rank 1
9145 10:01:50.934588 SW Impedance : PASS
9146 10:01:50.937772 DUTY Scan : NO K
9147 10:01:50.941100 ZQ Calibration : PASS
9148 10:01:50.941184 Jitter Meter : NO K
9149 10:01:50.944105 CBT Training : PASS
9150 10:01:50.944196 Write leveling : PASS
9151 10:01:50.947450 RX DQS gating : PASS
9152 10:01:50.951163 RX DQ/DQS(RDDQC) : PASS
9153 10:01:50.951247 TX DQ/DQS : PASS
9154 10:01:50.954181 RX DATLAT : PASS
9155 10:01:50.957449 RX DQ/DQS(Engine): PASS
9156 10:01:50.957534 TX OE : PASS
9157 10:01:50.960983 All Pass.
9158 10:01:50.961067
9159 10:01:50.961134 DramC Write-DBI on
9160 10:01:50.964141 PER_BANK_REFRESH: Hybrid Mode
9161 10:01:50.964226 TX_TRACKING: ON
9162 10:01:50.974611 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9163 10:01:50.984229 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9164 10:01:50.990974 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9165 10:01:50.994204 [FAST_K] Save calibration result to emmc
9166 10:01:50.997415 sync common calibartion params.
9167 10:01:50.997494 sync cbt_mode0:1, 1:1
9168 10:01:51.001087 dram_init: ddr_geometry: 2
9169 10:01:51.004082 dram_init: ddr_geometry: 2
9170 10:01:51.004158 dram_init: ddr_geometry: 2
9171 10:01:51.007323 0:dram_rank_size:100000000
9172 10:01:51.010843 1:dram_rank_size:100000000
9173 10:01:51.017430 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9174 10:01:51.017515 DFS_SHUFFLE_HW_MODE: ON
9175 10:01:51.020800 dramc_set_vcore_voltage set vcore to 725000
9176 10:01:51.023984 Read voltage for 1600, 0
9177 10:01:51.024069 Vio18 = 0
9178 10:01:51.027563 Vcore = 725000
9179 10:01:51.027648 Vdram = 0
9180 10:01:51.027714 Vddq = 0
9181 10:01:51.030804 Vmddr = 0
9182 10:01:51.030888 switch to 3200 Mbps bootup
9183 10:01:51.034212 [DramcRunTimeConfig]
9184 10:01:51.034296 PHYPLL
9185 10:01:51.037382 DPM_CONTROL_AFTERK: ON
9186 10:01:51.037476 PER_BANK_REFRESH: ON
9187 10:01:51.040743 REFRESH_OVERHEAD_REDUCTION: ON
9188 10:01:51.043977 CMD_PICG_NEW_MODE: OFF
9189 10:01:51.044074 XRTWTW_NEW_MODE: ON
9190 10:01:51.047402 XRTRTR_NEW_MODE: ON
9191 10:01:51.047507 TX_TRACKING: ON
9192 10:01:51.050923 RDSEL_TRACKING: OFF
9193 10:01:51.054123 DQS Precalculation for DVFS: ON
9194 10:01:51.054238 RX_TRACKING: OFF
9195 10:01:51.057337 HW_GATING DBG: ON
9196 10:01:51.057462 ZQCS_ENABLE_LP4: ON
9197 10:01:51.061321 RX_PICG_NEW_MODE: ON
9198 10:01:51.061460 TX_PICG_NEW_MODE: ON
9199 10:01:51.064238 ENABLE_RX_DCM_DPHY: ON
9200 10:01:51.067202 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9201 10:01:51.070691 DUMMY_READ_FOR_TRACKING: OFF
9202 10:01:51.070847 !!! SPM_CONTROL_AFTERK: OFF
9203 10:01:51.074038 !!! SPM could not control APHY
9204 10:01:51.077468 IMPEDANCE_TRACKING: ON
9205 10:01:51.077674 TEMP_SENSOR: ON
9206 10:01:51.081213 HW_SAVE_FOR_SR: OFF
9207 10:01:51.084132 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9208 10:01:51.088115 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9209 10:01:51.088520 Read ODT Tracking: ON
9210 10:01:51.090936 Refresh Rate DeBounce: ON
9211 10:01:51.094699 DFS_NO_QUEUE_FLUSH: ON
9212 10:01:51.097953 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9213 10:01:51.101342 ENABLE_DFS_RUNTIME_MRW: OFF
9214 10:01:51.101843 DDR_RESERVE_NEW_MODE: ON
9215 10:01:51.104140 MR_CBT_SWITCH_FREQ: ON
9216 10:01:51.104615 =========================
9217 10:01:51.124910 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9218 10:01:51.127954 dram_init: ddr_geometry: 2
9219 10:01:51.146546 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9220 10:01:51.150026 dram_init: dram init end (result: 0)
9221 10:01:51.156196 DRAM-K: Full calibration passed in 24510 msecs
9222 10:01:51.159880 MRC: failed to locate region type 0.
9223 10:01:51.160387 DRAM rank0 size:0x100000000,
9224 10:01:51.162718 DRAM rank1 size=0x100000000
9225 10:01:51.173106 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9226 10:01:51.179396 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9227 10:01:51.185862 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9228 10:01:51.192411 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9229 10:01:51.195869 DRAM rank0 size:0x100000000,
9230 10:01:51.199328 DRAM rank1 size=0x100000000
9231 10:01:51.199801 CBMEM:
9232 10:01:51.202271 IMD: root @ 0xfffff000 254 entries.
9233 10:01:51.205909 IMD: root @ 0xffffec00 62 entries.
9234 10:01:51.209345 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9235 10:01:51.212914 WARNING: RO_VPD is uninitialized or empty.
9236 10:01:51.219060 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9237 10:01:51.226692 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9238 10:01:51.239145 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9239 10:01:51.250852 BS: romstage times (exec / console): total (unknown) / 24008 ms
9240 10:01:51.251335
9241 10:01:51.251809
9242 10:01:51.260581 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9243 10:01:51.263640 ARM64: Exception handlers installed.
9244 10:01:51.266948 ARM64: Testing exception
9245 10:01:51.270556 ARM64: Done test exception
9246 10:01:51.271023 Enumerating buses...
9247 10:01:51.273609 Show all devs... Before device enumeration.
9248 10:01:51.277410 Root Device: enabled 1
9249 10:01:51.280715 CPU_CLUSTER: 0: enabled 1
9250 10:01:51.281288 CPU: 00: enabled 1
9251 10:01:51.283985 Compare with tree...
9252 10:01:51.284559 Root Device: enabled 1
9253 10:01:51.286997 CPU_CLUSTER: 0: enabled 1
9254 10:01:51.290404 CPU: 00: enabled 1
9255 10:01:51.290874 Root Device scanning...
9256 10:01:51.294064 scan_static_bus for Root Device
9257 10:01:51.297473 CPU_CLUSTER: 0 enabled
9258 10:01:51.300452 scan_static_bus for Root Device done
9259 10:01:51.303770 scan_bus: bus Root Device finished in 8 msecs
9260 10:01:51.304343 done
9261 10:01:51.310680 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9262 10:01:51.313386 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9263 10:01:51.320523 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9264 10:01:51.323566 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9265 10:01:51.326972 Allocating resources...
9266 10:01:51.330469 Reading resources...
9267 10:01:51.333661 Root Device read_resources bus 0 link: 0
9268 10:01:51.334244 DRAM rank0 size:0x100000000,
9269 10:01:51.336792 DRAM rank1 size=0x100000000
9270 10:01:51.340388 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9271 10:01:51.343602 CPU: 00 missing read_resources
9272 10:01:51.346667 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9273 10:01:51.353234 Root Device read_resources bus 0 link: 0 done
9274 10:01:51.353796 Done reading resources.
9275 10:01:51.359926 Show resources in subtree (Root Device)...After reading.
9276 10:01:51.363161 Root Device child on link 0 CPU_CLUSTER: 0
9277 10:01:51.366576 CPU_CLUSTER: 0 child on link 0 CPU: 00
9278 10:01:51.376998 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9279 10:01:51.377576 CPU: 00
9280 10:01:51.380582 Root Device assign_resources, bus 0 link: 0
9281 10:01:51.383688 CPU_CLUSTER: 0 missing set_resources
9282 10:01:51.390148 Root Device assign_resources, bus 0 link: 0 done
9283 10:01:51.390763 Done setting resources.
9284 10:01:51.396744 Show resources in subtree (Root Device)...After assigning values.
9285 10:01:51.399903 Root Device child on link 0 CPU_CLUSTER: 0
9286 10:01:51.402952 CPU_CLUSTER: 0 child on link 0 CPU: 00
9287 10:01:51.413493 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9288 10:01:51.414075 CPU: 00
9289 10:01:51.416811 Done allocating resources.
9290 10:01:51.419801 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9291 10:01:51.423220 Enabling resources...
9292 10:01:51.423791 done.
9293 10:01:51.429453 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9294 10:01:51.430012 Initializing devices...
9295 10:01:51.433144 Root Device init
9296 10:01:51.433717 init hardware done!
9297 10:01:51.436595 0x00000018: ctrlr->caps
9298 10:01:51.439690 52.000 MHz: ctrlr->f_max
9299 10:01:51.440277 0.400 MHz: ctrlr->f_min
9300 10:01:51.442886 0x40ff8080: ctrlr->voltages
9301 10:01:51.443458 sclk: 390625
9302 10:01:51.446156 Bus Width = 1
9303 10:01:51.446673 sclk: 390625
9304 10:01:51.449146 Bus Width = 1
9305 10:01:51.449609 Early init status = 3
9306 10:01:51.455851 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9307 10:01:51.459323 in-header: 03 fc 00 00 01 00 00 00
9308 10:01:51.459803 in-data: 00
9309 10:01:51.466072 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9310 10:01:51.469248 in-header: 03 fd 00 00 00 00 00 00
9311 10:01:51.472808 in-data:
9312 10:01:51.476363 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9313 10:01:51.479616 in-header: 03 fc 00 00 01 00 00 00
9314 10:01:51.482794 in-data: 00
9315 10:01:51.486073 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9316 10:01:51.490285 in-header: 03 fd 00 00 00 00 00 00
9317 10:01:51.493654 in-data:
9318 10:01:51.497313 [SSUSB] Setting up USB HOST controller...
9319 10:01:51.500434 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9320 10:01:51.503757 [SSUSB] phy power-on done.
9321 10:01:51.507047 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9322 10:01:51.514192 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9323 10:01:51.516945 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9324 10:01:51.523811 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9325 10:01:51.530430 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9326 10:01:51.537231 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9327 10:01:51.543471 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9328 10:01:51.550082 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9329 10:01:51.554124 SPM: binary array size = 0x9dc
9330 10:01:51.556831 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9331 10:01:51.563243 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9332 10:01:51.570059 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9333 10:01:51.573263 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9334 10:01:51.580162 configure_display: Starting display init
9335 10:01:51.613984 anx7625_power_on_init: Init interface.
9336 10:01:51.617462 anx7625_disable_pd_protocol: Disabled PD feature.
9337 10:01:51.620951 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9338 10:01:51.648222 anx7625_start_dp_work: Secure OCM version=00
9339 10:01:51.651828 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9340 10:01:51.666555 sp_tx_get_edid_block: EDID Block = 1
9341 10:01:51.769399 Extracted contents:
9342 10:01:51.772336 header: 00 ff ff ff ff ff ff 00
9343 10:01:51.775513 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9344 10:01:51.779272 version: 01 04
9345 10:01:51.782231 basic params: 95 1f 11 78 0a
9346 10:01:51.785328 chroma info: 76 90 94 55 54 90 27 21 50 54
9347 10:01:51.788857 established: 00 00 00
9348 10:01:51.795519 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9349 10:01:51.798990 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9350 10:01:51.805596 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9351 10:01:51.811758 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9352 10:01:51.818884 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9353 10:01:51.822115 extensions: 00
9354 10:01:51.822737 checksum: fb
9355 10:01:51.823118
9356 10:01:51.825401 Manufacturer: IVO Model 57d Serial Number 0
9357 10:01:51.828606 Made week 0 of 2020
9358 10:01:51.829190 EDID version: 1.4
9359 10:01:51.831865 Digital display
9360 10:01:51.834979 6 bits per primary color channel
9361 10:01:51.835446 DisplayPort interface
9362 10:01:51.838380 Maximum image size: 31 cm x 17 cm
9363 10:01:51.841540 Gamma: 220%
9364 10:01:51.841996 Check DPMS levels
9365 10:01:51.845161 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9366 10:01:51.848419 First detailed timing is preferred timing
9367 10:01:51.851851 Established timings supported:
9368 10:01:51.855772 Standard timings supported:
9369 10:01:51.858573 Detailed timings
9370 10:01:51.861615 Hex of detail: 383680a07038204018303c0035ae10000019
9371 10:01:51.864989 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9372 10:01:51.871767 0780 0798 07c8 0820 hborder 0
9373 10:01:51.875108 0438 043b 0447 0458 vborder 0
9374 10:01:51.878245 -hsync -vsync
9375 10:01:51.878767 Did detailed timing
9376 10:01:51.885102 Hex of detail: 000000000000000000000000000000000000
9377 10:01:51.885674 Manufacturer-specified data, tag 0
9378 10:01:51.891392 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9379 10:01:51.894721 ASCII string: InfoVision
9380 10:01:51.898067 Hex of detail: 000000fe00523134304e574635205248200a
9381 10:01:51.901254 ASCII string: R140NWF5 RH
9382 10:01:51.901713 Checksum
9383 10:01:51.905030 Checksum: 0xfb (valid)
9384 10:01:51.908244 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9385 10:01:51.911824 DSI data_rate: 832800000 bps
9386 10:01:51.918518 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9387 10:01:51.921331 anx7625_parse_edid: pixelclock(138800).
9388 10:01:51.925139 hactive(1920), hsync(48), hfp(24), hbp(88)
9389 10:01:51.927819 vactive(1080), vsync(12), vfp(3), vbp(17)
9390 10:01:51.931269 anx7625_dsi_config: config dsi.
9391 10:01:51.938325 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9392 10:01:51.951288 anx7625_dsi_config: success to config DSI
9393 10:01:51.954534 anx7625_dp_start: MIPI phy setup OK.
9394 10:01:51.957950 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9395 10:01:51.960671 mtk_ddp_mode_set invalid vrefresh 60
9396 10:01:51.964730 main_disp_path_setup
9397 10:01:51.965380 ovl_layer_smi_id_en
9398 10:01:51.967677 ovl_layer_smi_id_en
9399 10:01:51.968280 ccorr_config
9400 10:01:51.968653 aal_config
9401 10:01:51.970957 gamma_config
9402 10:01:51.971413 postmask_config
9403 10:01:51.974282 dither_config
9404 10:01:51.977792 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9405 10:01:51.984372 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9406 10:01:51.987739 Root Device init finished in 551 msecs
9407 10:01:51.988295 CPU_CLUSTER: 0 init
9408 10:01:51.997514 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9409 10:01:52.001053 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9410 10:01:52.004392 APU_MBOX 0x190000b0 = 0x10001
9411 10:01:52.007373 APU_MBOX 0x190001b0 = 0x10001
9412 10:01:52.010775 APU_MBOX 0x190005b0 = 0x10001
9413 10:01:52.014056 APU_MBOX 0x190006b0 = 0x10001
9414 10:01:52.017416 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9415 10:01:52.030417 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9416 10:01:52.042351 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9417 10:01:52.048540 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9418 10:01:52.060307 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9419 10:01:52.069839 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9420 10:01:52.073265 CPU_CLUSTER: 0 init finished in 81 msecs
9421 10:01:52.076126 Devices initialized
9422 10:01:52.079379 Show all devs... After init.
9423 10:01:52.079839 Root Device: enabled 1
9424 10:01:52.083093 CPU_CLUSTER: 0: enabled 1
9425 10:01:52.086446 CPU: 00: enabled 1
9426 10:01:52.089802 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9427 10:01:52.093002 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9428 10:01:52.096130 ELOG: NV offset 0x57f000 size 0x1000
9429 10:01:52.102964 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9430 10:01:52.109933 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9431 10:01:52.112664 ELOG: Event(17) added with size 13 at 2023-11-24 10:01:19 UTC
9432 10:01:52.116067 out: cmd=0x121: 03 db 21 01 00 00 00 00
9433 10:01:52.121041 in-header: 03 2c 00 00 2c 00 00 00
9434 10:01:52.134442 in-data: 33 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9435 10:01:52.140952 ELOG: Event(A1) added with size 10 at 2023-11-24 10:01:19 UTC
9436 10:01:52.147420 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9437 10:01:52.153787 ELOG: Event(A0) added with size 9 at 2023-11-24 10:01:19 UTC
9438 10:01:52.157905 elog_add_boot_reason: Logged dev mode boot
9439 10:01:52.160895 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9440 10:01:52.163762 Finalize devices...
9441 10:01:52.164240 Devices finalized
9442 10:01:52.170221 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9443 10:01:52.174161 Writing coreboot table at 0xffe64000
9444 10:01:52.177397 0. 000000000010a000-0000000000113fff: RAMSTAGE
9445 10:01:52.180230 1. 0000000040000000-00000000400fffff: RAM
9446 10:01:52.186928 2. 0000000040100000-000000004032afff: RAMSTAGE
9447 10:01:52.190140 3. 000000004032b000-00000000545fffff: RAM
9448 10:01:52.193550 4. 0000000054600000-000000005465ffff: BL31
9449 10:01:52.196544 5. 0000000054660000-00000000ffe63fff: RAM
9450 10:01:52.203635 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9451 10:01:52.206962 7. 0000000100000000-000000023fffffff: RAM
9452 10:01:52.210297 Passing 5 GPIOs to payload:
9453 10:01:52.213032 NAME | PORT | POLARITY | VALUE
9454 10:01:52.216535 EC in RW | 0x000000aa | low | undefined
9455 10:01:52.223330 EC interrupt | 0x00000005 | low | undefined
9456 10:01:52.226451 TPM interrupt | 0x000000ab | high | undefined
9457 10:01:52.233383 SD card detect | 0x00000011 | high | undefined
9458 10:01:52.236828 speaker enable | 0x00000093 | high | undefined
9459 10:01:52.240387 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9460 10:01:52.243080 in-header: 03 f9 00 00 02 00 00 00
9461 10:01:52.243550 in-data: 02 00
9462 10:01:52.246273 ADC[4]: Raw value=901032 ID=7
9463 10:01:52.250105 ADC[3]: Raw value=212810 ID=1
9464 10:01:52.253142 RAM Code: 0x71
9465 10:01:52.253620 ADC[6]: Raw value=74502 ID=0
9466 10:01:52.256559 ADC[5]: Raw value=212072 ID=1
9467 10:01:52.259925 SKU Code: 0x1
9468 10:01:52.262997 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum f933
9469 10:01:52.266519 coreboot table: 964 bytes.
9470 10:01:52.269956 IMD ROOT 0. 0xfffff000 0x00001000
9471 10:01:52.273045 IMD SMALL 1. 0xffffe000 0x00001000
9472 10:01:52.276275 RO MCACHE 2. 0xffffc000 0x00001104
9473 10:01:52.279513 CONSOLE 3. 0xfff7c000 0x00080000
9474 10:01:52.282661 FMAP 4. 0xfff7b000 0x00000452
9475 10:01:52.286322 TIME STAMP 5. 0xfff7a000 0x00000910
9476 10:01:52.289680 VBOOT WORK 6. 0xfff66000 0x00014000
9477 10:01:52.292838 RAMOOPS 7. 0xffe66000 0x00100000
9478 10:01:52.296224 COREBOOT 8. 0xffe64000 0x00002000
9479 10:01:52.296807 IMD small region:
9480 10:01:52.299372 IMD ROOT 0. 0xffffec00 0x00000400
9481 10:01:52.302958 VPD 1. 0xffffeb80 0x0000006c
9482 10:01:52.309798 MMC STATUS 2. 0xffffeb60 0x00000004
9483 10:01:52.312664 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9484 10:01:52.316068 Probing TPM: done!
9485 10:01:52.319476 Connected to device vid:did:rid of 1ae0:0028:00
9486 10:01:52.330046 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9487 10:01:52.332817 Initialized TPM device CR50 revision 0
9488 10:01:52.336921 Checking cr50 for pending updates
9489 10:01:52.340749 Reading cr50 TPM mode
9490 10:01:52.348945 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9491 10:01:52.355618 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9492 10:01:52.395650 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9493 10:01:52.398885 Checking segment from ROM address 0x40100000
9494 10:01:52.402263 Checking segment from ROM address 0x4010001c
9495 10:01:52.409293 Loading segment from ROM address 0x40100000
9496 10:01:52.409852 code (compression=0)
9497 10:01:52.415565 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9498 10:01:52.425971 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9499 10:01:52.426485 it's not compressed!
9500 10:01:52.432101 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9501 10:01:52.435988 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9502 10:01:52.455959 Loading segment from ROM address 0x4010001c
9503 10:01:52.456531 Entry Point 0x80000000
9504 10:01:52.459167 Loaded segments
9505 10:01:52.462592 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9506 10:01:52.469399 Jumping to boot code at 0x80000000(0xffe64000)
9507 10:01:52.475680 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9508 10:01:52.482691 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9509 10:01:52.490298 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9510 10:01:52.493621 Checking segment from ROM address 0x40100000
9511 10:01:52.497265 Checking segment from ROM address 0x4010001c
9512 10:01:52.503885 Loading segment from ROM address 0x40100000
9513 10:01:52.504352 code (compression=1)
9514 10:01:52.510661 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9515 10:01:52.520525 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9516 10:01:52.520953 using LZMA
9517 10:01:52.528739 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9518 10:01:52.535336 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9519 10:01:52.538864 Loading segment from ROM address 0x4010001c
9520 10:01:52.539285 Entry Point 0x54601000
9521 10:01:52.541942 Loaded segments
9522 10:01:52.545139 NOTICE: MT8192 bl31_setup
9523 10:01:52.552616 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9524 10:01:52.555466 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9525 10:01:52.558920 WARNING: region 0:
9526 10:01:52.562225 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9527 10:01:52.562688 WARNING: region 1:
9528 10:01:52.569115 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9529 10:01:52.572972 WARNING: region 2:
9530 10:01:52.576670 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9531 10:01:52.579036 WARNING: region 3:
9532 10:01:52.582674 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9533 10:01:52.585917 WARNING: region 4:
9534 10:01:52.592272 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9535 10:01:52.592845 WARNING: region 5:
9536 10:01:52.595855 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9537 10:01:52.599153 WARNING: region 6:
9538 10:01:52.602368 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9539 10:01:52.602878 WARNING: region 7:
9540 10:01:52.608980 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9541 10:01:52.615969 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9542 10:01:52.619389 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9543 10:01:52.622198 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9544 10:01:52.628931 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9545 10:01:52.632662 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9546 10:01:52.635922 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9547 10:01:52.642949 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9548 10:01:52.645574 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9549 10:01:52.648951 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9550 10:01:52.656252 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9551 10:01:52.659259 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9552 10:01:52.665976 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9553 10:01:52.669228 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9554 10:01:52.672543 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9555 10:01:52.679333 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9556 10:01:52.682780 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9557 10:01:52.685925 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9558 10:01:52.692614 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9559 10:01:52.696147 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9560 10:01:52.702540 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9561 10:01:52.706073 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9562 10:01:52.709739 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9563 10:01:52.715847 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9564 10:01:52.719346 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9565 10:01:52.726217 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9566 10:01:52.729363 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9567 10:01:52.732854 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9568 10:01:52.739243 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9569 10:01:52.742858 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9570 10:01:52.745927 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9571 10:01:52.752393 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9572 10:01:52.755977 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9573 10:01:52.759329 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9574 10:01:52.766273 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9575 10:01:52.769588 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9576 10:01:52.772504 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9577 10:01:52.776331 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9578 10:01:52.782845 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9579 10:01:52.786603 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9580 10:01:52.789175 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9581 10:01:52.792562 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9582 10:01:52.799667 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9583 10:01:52.802538 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9584 10:01:52.805937 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9585 10:01:52.809533 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9586 10:01:52.815902 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9587 10:01:52.819270 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9588 10:01:52.822359 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9589 10:01:52.829221 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9590 10:01:52.832365 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9591 10:01:52.839115 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9592 10:01:52.842499 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9593 10:01:52.845859 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9594 10:01:52.852482 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9595 10:01:52.856177 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9596 10:01:52.862592 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9597 10:01:52.866013 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9598 10:01:52.869030 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9599 10:01:52.876289 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9600 10:01:52.879720 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9601 10:01:52.886260 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9602 10:01:52.889016 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9603 10:01:52.896315 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9604 10:01:52.899630 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9605 10:01:52.902980 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9606 10:01:52.909658 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9607 10:01:52.912945 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9608 10:01:52.919309 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9609 10:01:52.922986 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9610 10:01:52.929611 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9611 10:01:52.933325 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9612 10:01:52.936182 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9613 10:01:52.943271 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9614 10:01:52.946313 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9615 10:01:52.953065 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9616 10:01:52.956108 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9617 10:01:52.963131 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9618 10:01:52.966380 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9619 10:01:52.969849 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9620 10:01:52.976574 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9621 10:01:52.979819 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9622 10:01:52.985987 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9623 10:01:52.989592 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9624 10:01:52.996102 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9625 10:01:52.999485 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9626 10:01:53.003047 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9627 10:01:53.009559 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9628 10:01:53.012927 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9629 10:01:53.019412 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9630 10:01:53.023165 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9631 10:01:53.029638 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9632 10:01:53.032743 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9633 10:01:53.035950 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9634 10:01:53.042440 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9635 10:01:53.046199 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9636 10:01:53.052562 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9637 10:01:53.055965 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9638 10:01:53.059112 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9639 10:01:53.065931 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9640 10:01:53.069225 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9641 10:01:53.072421 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9642 10:01:53.076067 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9643 10:01:53.083027 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9644 10:01:53.085973 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9645 10:01:53.092722 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9646 10:01:53.096451 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9647 10:01:53.099973 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9648 10:01:53.106151 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9649 10:01:53.109544 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9650 10:01:53.116190 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9651 10:01:53.119360 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9652 10:01:53.122680 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9653 10:01:53.129701 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9654 10:01:53.132990 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9655 10:01:53.139807 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9656 10:01:53.142967 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9657 10:01:53.146014 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9658 10:01:53.149402 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9659 10:01:53.156303 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9660 10:01:53.159389 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9661 10:01:53.162892 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9662 10:01:53.166090 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9663 10:01:53.172908 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9664 10:01:53.176434 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9665 10:01:53.179413 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9666 10:01:53.186468 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9667 10:01:53.189667 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9668 10:01:53.196759 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9669 10:01:53.200117 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9670 10:01:53.203067 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9671 10:01:53.209964 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9672 10:01:53.213909 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9673 10:01:53.219933 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9674 10:01:53.223080 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9675 10:01:53.227251 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9676 10:01:53.233507 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9677 10:01:53.236878 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9678 10:01:53.239920 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9679 10:01:53.246688 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9680 10:01:53.250167 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9681 10:01:53.256647 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9682 10:01:53.260373 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9683 10:01:53.263412 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9684 10:01:53.269950 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9685 10:01:53.273262 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9686 10:01:53.276367 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9687 10:01:53.283044 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9688 10:01:53.286715 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9689 10:01:53.293148 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9690 10:01:53.296514 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9691 10:01:53.299892 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9692 10:01:53.306487 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9693 10:01:53.309803 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9694 10:01:53.316317 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9695 10:01:53.319732 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9696 10:01:53.323087 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9697 10:01:53.329787 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9698 10:01:53.333130 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9699 10:01:53.339693 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9700 10:01:53.342807 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9701 10:01:53.346053 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9702 10:01:53.352911 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9703 10:01:53.356391 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9704 10:01:53.362959 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9705 10:01:53.366170 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9706 10:01:53.369340 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9707 10:01:53.376486 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9708 10:01:53.379751 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9709 10:01:53.382696 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9710 10:01:53.389670 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9711 10:01:53.392566 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9712 10:01:53.399298 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9713 10:01:53.402743 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9714 10:01:53.405644 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9715 10:01:53.412652 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9716 10:01:53.415863 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9717 10:01:53.422363 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9718 10:01:53.426055 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9719 10:01:53.429138 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9720 10:01:53.435854 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9721 10:01:53.438996 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9722 10:01:53.445519 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9723 10:01:53.449120 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9724 10:01:53.452289 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9725 10:01:53.458938 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9726 10:01:53.462193 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9727 10:01:53.465579 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9728 10:01:53.472151 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9729 10:01:53.475395 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9730 10:01:53.481905 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9731 10:01:53.485554 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9732 10:01:53.491947 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9733 10:01:53.495705 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9734 10:01:53.498821 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9735 10:01:53.505485 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9736 10:01:53.508313 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9737 10:01:53.514999 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9738 10:01:53.518261 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9739 10:01:53.525018 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9740 10:01:53.528388 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9741 10:01:53.532139 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9742 10:01:53.538306 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9743 10:01:53.541829 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9744 10:01:53.548110 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9745 10:01:53.551518 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9746 10:01:53.558135 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9747 10:01:53.561398 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9748 10:01:53.564986 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9749 10:01:53.571415 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9750 10:01:53.574637 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9751 10:01:53.581675 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9752 10:01:53.585139 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9753 10:01:53.588326 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9754 10:01:53.595015 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9755 10:01:53.597957 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9756 10:01:53.604853 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9757 10:01:53.608010 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9758 10:01:53.614524 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9759 10:01:53.617904 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9760 10:01:53.621279 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9761 10:01:53.627905 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9762 10:01:53.631618 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9763 10:01:53.638269 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9764 10:01:53.641424 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9765 10:01:53.644619 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9766 10:01:53.651078 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9767 10:01:53.654674 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9768 10:01:53.661235 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9769 10:01:53.664676 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9770 10:01:53.667989 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9771 10:01:53.671187 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9772 10:01:53.677662 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9773 10:01:53.681211 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9774 10:01:53.684331 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9775 10:01:53.691249 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9776 10:01:53.694428 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9777 10:01:53.698042 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9778 10:01:53.704532 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9779 10:01:53.707968 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9780 10:01:53.710932 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9781 10:01:53.717751 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9782 10:01:53.721119 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9783 10:01:53.727782 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9784 10:01:53.730947 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9785 10:01:53.734676 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9786 10:01:53.741085 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9787 10:01:53.744395 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9788 10:01:53.747459 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9789 10:01:53.754295 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9790 10:01:53.757786 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9791 10:01:53.760961 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9792 10:01:53.767776 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9793 10:01:53.770706 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9794 10:01:53.774283 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9795 10:01:53.780888 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9796 10:01:53.784121 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9797 10:01:53.790968 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9798 10:01:53.794058 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9799 10:01:53.797478 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9800 10:01:53.804020 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9801 10:01:53.807517 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9802 10:01:53.810793 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9803 10:01:53.817605 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9804 10:01:53.820935 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9805 10:01:53.823878 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9806 10:01:53.830489 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9807 10:01:53.833982 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9808 10:01:53.840711 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9809 10:01:53.844056 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9810 10:01:53.847160 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9811 10:01:53.850331 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9812 10:01:53.856972 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9813 10:01:53.860748 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9814 10:01:53.863919 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9815 10:01:53.867382 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9816 10:01:53.873700 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9817 10:01:53.877011 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9818 10:01:53.880767 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9819 10:01:53.883803 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9820 10:01:53.890159 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9821 10:01:53.893652 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9822 10:01:53.896759 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9823 10:01:53.903784 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9824 10:01:53.906830 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9825 10:01:53.910212 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9826 10:01:53.916618 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9827 10:01:53.920284 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9828 10:01:53.926942 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9829 10:01:53.930566 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9830 10:01:53.933351 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9831 10:01:53.940241 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9832 10:01:53.943675 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9833 10:01:53.950237 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9834 10:01:53.953494 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9835 10:01:53.960202 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9836 10:01:53.963724 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9837 10:01:53.967150 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9838 10:01:53.973388 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9839 10:01:53.977252 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9840 10:01:53.980529 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9841 10:01:53.986811 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9842 10:01:53.990435 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9843 10:01:53.996781 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9844 10:01:54.000140 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9845 10:01:54.006685 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9846 10:01:54.010526 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9847 10:01:54.013384 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9848 10:01:54.020197 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9849 10:01:54.023338 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9850 10:01:54.030331 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9851 10:01:54.033543 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9852 10:01:54.036837 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9853 10:01:54.043549 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9854 10:01:54.046895 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9855 10:01:54.050305 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9856 10:01:54.056663 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9857 10:01:54.060217 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9858 10:01:54.066672 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9859 10:01:54.069937 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9860 10:01:54.076415 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9861 10:01:54.079834 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9862 10:01:54.083333 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9863 10:01:54.089718 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9864 10:01:54.093123 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9865 10:01:54.099957 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9866 10:01:54.103152 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9867 10:01:54.106283 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9868 10:01:54.113083 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9869 10:01:54.116565 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9870 10:01:54.123157 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9871 10:01:54.126560 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9872 10:01:54.129986 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9873 10:01:54.136227 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9874 10:01:54.139860 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9875 10:01:54.146236 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9876 10:01:54.149733 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9877 10:01:54.156215 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9878 10:01:54.159939 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9879 10:01:54.163304 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9880 10:01:54.169253 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9881 10:01:54.172975 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9882 10:01:54.179460 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9883 10:01:54.182562 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9884 10:01:54.185967 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9885 10:01:54.193170 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9886 10:01:54.196152 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9887 10:01:54.202806 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9888 10:01:54.206103 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9889 10:01:54.209249 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9890 10:01:54.216136 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9891 10:01:54.219677 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9892 10:01:54.225755 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9893 10:01:54.229457 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9894 10:01:54.232612 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9895 10:01:54.239252 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9896 10:01:54.242494 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9897 10:01:54.249403 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9898 10:01:54.252480 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9899 10:01:54.259260 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9900 10:01:54.262921 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9901 10:01:54.269458 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9902 10:01:54.272542 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9903 10:01:54.276050 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9904 10:01:54.282495 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9905 10:01:54.285937 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9906 10:01:54.292608 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9907 10:01:54.295998 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9908 10:01:54.302482 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9909 10:01:54.305829 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9910 10:01:54.309054 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9911 10:01:54.316097 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9912 10:01:54.319460 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9913 10:01:54.325699 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9914 10:01:54.329114 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9915 10:01:54.335655 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9916 10:01:54.339045 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9917 10:01:54.342628 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9918 10:01:54.348879 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9919 10:01:54.352455 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9920 10:01:54.358767 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9921 10:01:54.362540 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9922 10:01:54.368990 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9923 10:01:54.372406 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9924 10:01:54.376040 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9925 10:01:54.382653 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9926 10:01:54.385878 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9927 10:01:54.392474 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9928 10:01:54.395867 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9929 10:01:54.402759 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9930 10:01:54.405808 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9931 10:01:54.409429 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9932 10:01:54.415264 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9933 10:01:54.418978 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9934 10:01:54.425486 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9935 10:01:54.429271 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9936 10:01:54.435254 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9937 10:01:54.438911 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9938 10:01:54.442278 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9939 10:01:54.448875 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9940 10:01:54.452405 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9941 10:01:54.458624 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9942 10:01:54.462565 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9943 10:01:54.465440 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9944 10:01:54.472082 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9945 10:01:54.475447 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9946 10:01:54.482489 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9947 10:01:54.485208 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9948 10:01:54.492058 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9949 10:01:54.495732 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9950 10:01:54.502039 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9951 10:01:54.505584 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9952 10:01:54.512307 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9953 10:01:54.515454 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9954 10:01:54.521820 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9955 10:01:54.525324 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9956 10:01:54.532182 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9957 10:01:54.535143 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9958 10:01:54.542075 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9959 10:01:54.545334 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9960 10:01:54.548689 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9961 10:01:54.555003 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9962 10:01:54.558536 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9963 10:01:54.565425 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9964 10:01:54.568801 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9965 10:01:54.575514 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9966 10:01:54.578746 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9967 10:01:54.585396 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9968 10:01:54.588504 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9969 10:01:54.595253 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9970 10:01:54.598436 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9971 10:01:54.605677 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9972 10:01:54.608591 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9973 10:01:54.615311 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9974 10:01:54.618731 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9975 10:01:54.625123 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9976 10:01:54.625656 INFO: [APUAPC] vio 0
9977 10:01:54.632088 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9978 10:01:54.635508 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9979 10:01:54.638709 INFO: [APUAPC] D0_APC_0: 0x400510
9980 10:01:54.641959 INFO: [APUAPC] D0_APC_1: 0x0
9981 10:01:54.645274 INFO: [APUAPC] D0_APC_2: 0x1540
9982 10:01:54.648494 INFO: [APUAPC] D0_APC_3: 0x0
9983 10:01:54.652114 INFO: [APUAPC] D1_APC_0: 0xffffffff
9984 10:01:54.655204 INFO: [APUAPC] D1_APC_1: 0xffffffff
9985 10:01:54.658572 INFO: [APUAPC] D1_APC_2: 0x3fffff
9986 10:01:54.661711 INFO: [APUAPC] D1_APC_3: 0x0
9987 10:01:54.665498 INFO: [APUAPC] D2_APC_0: 0xffffffff
9988 10:01:54.668716 INFO: [APUAPC] D2_APC_1: 0xffffffff
9989 10:01:54.672109 INFO: [APUAPC] D2_APC_2: 0x3fffff
9990 10:01:54.675398 INFO: [APUAPC] D2_APC_3: 0x0
9991 10:01:54.678865 INFO: [APUAPC] D3_APC_0: 0xffffffff
9992 10:01:54.682131 INFO: [APUAPC] D3_APC_1: 0xffffffff
9993 10:01:54.685241 INFO: [APUAPC] D3_APC_2: 0x3fffff
9994 10:01:54.688754 INFO: [APUAPC] D3_APC_3: 0x0
9995 10:01:54.691582 INFO: [APUAPC] D4_APC_0: 0xffffffff
9996 10:01:54.694875 INFO: [APUAPC] D4_APC_1: 0xffffffff
9997 10:01:54.698552 INFO: [APUAPC] D4_APC_2: 0x3fffff
9998 10:01:54.701811 INFO: [APUAPC] D4_APC_3: 0x0
9999 10:01:54.704974 INFO: [APUAPC] D5_APC_0: 0xffffffff
10000 10:01:54.708497 INFO: [APUAPC] D5_APC_1: 0xffffffff
10001 10:01:54.711854 INFO: [APUAPC] D5_APC_2: 0x3fffff
10002 10:01:54.712439 INFO: [APUAPC] D5_APC_3: 0x0
10003 10:01:54.714817 INFO: [APUAPC] D6_APC_0: 0xffffffff
10004 10:01:54.718573 INFO: [APUAPC] D6_APC_1: 0xffffffff
10005 10:01:54.722001 INFO: [APUAPC] D6_APC_2: 0x3fffff
10006 10:01:54.724859 INFO: [APUAPC] D6_APC_3: 0x0
10007 10:01:54.728118 INFO: [APUAPC] D7_APC_0: 0xffffffff
10008 10:01:54.731645 INFO: [APUAPC] D7_APC_1: 0xffffffff
10009 10:01:54.734924 INFO: [APUAPC] D7_APC_2: 0x3fffff
10010 10:01:54.737698 INFO: [APUAPC] D7_APC_3: 0x0
10011 10:01:54.741257 INFO: [APUAPC] D8_APC_0: 0xffffffff
10012 10:01:54.744779 INFO: [APUAPC] D8_APC_1: 0xffffffff
10013 10:01:54.747975 INFO: [APUAPC] D8_APC_2: 0x3fffff
10014 10:01:54.750945 INFO: [APUAPC] D8_APC_3: 0x0
10015 10:01:54.754378 INFO: [APUAPC] D9_APC_0: 0xffffffff
10016 10:01:54.757552 INFO: [APUAPC] D9_APC_1: 0xffffffff
10017 10:01:54.761153 INFO: [APUAPC] D9_APC_2: 0x3fffff
10018 10:01:54.764155 INFO: [APUAPC] D9_APC_3: 0x0
10019 10:01:54.767702 INFO: [APUAPC] D10_APC_0: 0xffffffff
10020 10:01:54.771081 INFO: [APUAPC] D10_APC_1: 0xffffffff
10021 10:01:54.774260 INFO: [APUAPC] D10_APC_2: 0x3fffff
10022 10:01:54.777745 INFO: [APUAPC] D10_APC_3: 0x0
10023 10:01:54.781165 INFO: [APUAPC] D11_APC_0: 0xffffffff
10024 10:01:54.784345 INFO: [APUAPC] D11_APC_1: 0xffffffff
10025 10:01:54.788038 INFO: [APUAPC] D11_APC_2: 0x3fffff
10026 10:01:54.790889 INFO: [APUAPC] D11_APC_3: 0x0
10027 10:01:54.794173 INFO: [APUAPC] D12_APC_0: 0xffffffff
10028 10:01:54.797742 INFO: [APUAPC] D12_APC_1: 0xffffffff
10029 10:01:54.801042 INFO: [APUAPC] D12_APC_2: 0x3fffff
10030 10:01:54.804435 INFO: [APUAPC] D12_APC_3: 0x0
10031 10:01:54.807689 INFO: [APUAPC] D13_APC_0: 0xffffffff
10032 10:01:54.811080 INFO: [APUAPC] D13_APC_1: 0xffffffff
10033 10:01:54.814210 INFO: [APUAPC] D13_APC_2: 0x3fffff
10034 10:01:54.817743 INFO: [APUAPC] D13_APC_3: 0x0
10035 10:01:54.821284 INFO: [APUAPC] D14_APC_0: 0xffffffff
10036 10:01:54.824539 INFO: [APUAPC] D14_APC_1: 0xffffffff
10037 10:01:54.828088 INFO: [APUAPC] D14_APC_2: 0x3fffff
10038 10:01:54.831502 INFO: [APUAPC] D14_APC_3: 0x0
10039 10:01:54.834431 INFO: [APUAPC] D15_APC_0: 0xffffffff
10040 10:01:54.837880 INFO: [APUAPC] D15_APC_1: 0xffffffff
10041 10:01:54.841239 INFO: [APUAPC] D15_APC_2: 0x3fffff
10042 10:01:54.845053 INFO: [APUAPC] D15_APC_3: 0x0
10043 10:01:54.848012 INFO: [APUAPC] APC_CON: 0x4
10044 10:01:54.851333 INFO: [NOCDAPC] D0_APC_0: 0x0
10045 10:01:54.854820 INFO: [NOCDAPC] D0_APC_1: 0x0
10046 10:01:54.858212 INFO: [NOCDAPC] D1_APC_0: 0x0
10047 10:01:54.861276 INFO: [NOCDAPC] D1_APC_1: 0xfff
10048 10:01:54.861823 INFO: [NOCDAPC] D2_APC_0: 0x0
10049 10:01:54.864612 INFO: [NOCDAPC] D2_APC_1: 0xfff
10050 10:01:54.868674 INFO: [NOCDAPC] D3_APC_0: 0x0
10051 10:01:54.871245 INFO: [NOCDAPC] D3_APC_1: 0xfff
10052 10:01:54.874808 INFO: [NOCDAPC] D4_APC_0: 0x0
10053 10:01:54.877589 INFO: [NOCDAPC] D4_APC_1: 0xfff
10054 10:01:54.881307 INFO: [NOCDAPC] D5_APC_0: 0x0
10055 10:01:54.884432 INFO: [NOCDAPC] D5_APC_1: 0xfff
10056 10:01:54.888226 INFO: [NOCDAPC] D6_APC_0: 0x0
10057 10:01:54.891228 INFO: [NOCDAPC] D6_APC_1: 0xfff
10058 10:01:54.894683 INFO: [NOCDAPC] D7_APC_0: 0x0
10059 10:01:54.895105 INFO: [NOCDAPC] D7_APC_1: 0xfff
10060 10:01:54.897728 INFO: [NOCDAPC] D8_APC_0: 0x0
10061 10:01:54.900918 INFO: [NOCDAPC] D8_APC_1: 0xfff
10062 10:01:54.904230 INFO: [NOCDAPC] D9_APC_0: 0x0
10063 10:01:54.907658 INFO: [NOCDAPC] D9_APC_1: 0xfff
10064 10:01:54.910984 INFO: [NOCDAPC] D10_APC_0: 0x0
10065 10:01:54.914772 INFO: [NOCDAPC] D10_APC_1: 0xfff
10066 10:01:54.917798 INFO: [NOCDAPC] D11_APC_0: 0x0
10067 10:01:54.921077 INFO: [NOCDAPC] D11_APC_1: 0xfff
10068 10:01:54.924583 INFO: [NOCDAPC] D12_APC_0: 0x0
10069 10:01:54.927743 INFO: [NOCDAPC] D12_APC_1: 0xfff
10070 10:01:54.931540 INFO: [NOCDAPC] D13_APC_0: 0x0
10071 10:01:54.934594 INFO: [NOCDAPC] D13_APC_1: 0xfff
10072 10:01:54.935020 INFO: [NOCDAPC] D14_APC_0: 0x0
10073 10:01:54.938027 INFO: [NOCDAPC] D14_APC_1: 0xfff
10074 10:01:54.941381 INFO: [NOCDAPC] D15_APC_0: 0x0
10075 10:01:54.944480 INFO: [NOCDAPC] D15_APC_1: 0xfff
10076 10:01:54.947921 INFO: [NOCDAPC] APC_CON: 0x4
10077 10:01:54.950909 INFO: [APUAPC] set_apusys_apc done
10078 10:01:54.954762 INFO: [DEVAPC] devapc_init done
10079 10:01:54.957605 INFO: GICv3 without legacy support detected.
10080 10:01:54.964768 INFO: ARM GICv3 driver initialized in EL3
10081 10:01:54.967911 INFO: Maximum SPI INTID supported: 639
10082 10:01:54.970775 INFO: BL31: Initializing runtime services
10083 10:01:54.977554 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10084 10:01:54.978192 INFO: SPM: enable CPC mode
10085 10:01:54.984302 INFO: mcdi ready for mcusys-off-idle and system suspend
10086 10:01:54.987725 INFO: BL31: Preparing for EL3 exit to normal world
10087 10:01:54.994165 INFO: Entry point address = 0x80000000
10088 10:01:54.994668 INFO: SPSR = 0x8
10089 10:01:55.000659
10090 10:01:55.001152
10091 10:01:55.001534
10092 10:01:55.003567 Starting depthcharge on Spherion...
10093 10:01:55.003992
10094 10:01:55.004376 Wipe memory regions:
10095 10:01:55.004724
10096 10:01:55.007387 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10097 10:01:55.008105 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10098 10:01:55.008613 Setting prompt string to ['asurada:']
10099 10:01:55.009046 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10100 10:01:55.009732 [0x00000040000000, 0x00000054600000)
10101 10:01:55.129460
10102 10:01:55.130037 [0x00000054660000, 0x00000080000000)
10103 10:01:55.390100
10104 10:01:55.390764 [0x000000821a7280, 0x000000ffe64000)
10105 10:01:56.135151
10106 10:01:56.135674 [0x00000100000000, 0x00000240000000)
10107 10:01:58.025200
10108 10:01:58.027894 Initializing XHCI USB controller at 0x11200000.
10109 10:01:59.065825
10110 10:01:59.069054 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10111 10:01:59.069141
10112 10:01:59.069209
10113 10:01:59.069272
10114 10:01:59.069560 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10116 10:01:59.169954 asurada: tftpboot 192.168.201.1 12073307/tftp-deploy-qs3gwgws/kernel/image.itb 12073307/tftp-deploy-qs3gwgws/kernel/cmdline
10117 10:01:59.170572 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10118 10:01:59.171112 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10119 10:01:59.175597 tftpboot 192.168.201.1 12073307/tftp-deploy-qs3gwgws/kernel/image.itp-deploy-qs3gwgws/kernel/cmdline
10120 10:01:59.176038
10121 10:01:59.176383 Waiting for link
10122 10:01:59.335200
10123 10:01:59.335335 R8152: Initializing
10124 10:01:59.335404
10125 10:01:59.338904 Version 9 (ocp_data = 6010)
10126 10:01:59.339016
10127 10:01:59.341968 R8152: Done initializing
10128 10:01:59.342052
10129 10:01:59.342120 Adding net device
10130 10:02:01.287080
10131 10:02:01.287268 done.
10132 10:02:01.287339
10133 10:02:01.287402 MAC: 00:e0:4c:72:2d:d6
10134 10:02:01.287463
10135 10:02:01.290236 Sending DHCP discover... done.
10136 10:02:01.290354
10137 10:02:01.293588 Waiting for reply... done.
10138 10:02:01.293665
10139 10:02:01.297148 Sending DHCP request... done.
10140 10:02:01.297258
10141 10:02:01.304236 Waiting for reply... done.
10142 10:02:01.304321
10143 10:02:01.304388 My ip is 192.168.201.21
10144 10:02:01.304450
10145 10:02:01.307680 The DHCP server ip is 192.168.201.1
10146 10:02:01.307764
10147 10:02:01.314097 TFTP server IP predefined by user: 192.168.201.1
10148 10:02:01.314206
10149 10:02:01.320726 Bootfile predefined by user: 12073307/tftp-deploy-qs3gwgws/kernel/image.itb
10150 10:02:01.320816
10151 10:02:01.324033 Sending tftp read request... done.
10152 10:02:01.324123
10153 10:02:01.324194 Waiting for the transfer...
10154 10:02:01.327583
10155 10:02:01.590993 00000000 ################################################################
10156 10:02:01.591161
10157 10:02:01.835965 00080000 ################################################################
10158 10:02:01.836101
10159 10:02:02.084037 00100000 ################################################################
10160 10:02:02.084175
10161 10:02:02.328140 00180000 ################################################################
10162 10:02:02.328272
10163 10:02:02.576846 00200000 ################################################################
10164 10:02:02.577019
10165 10:02:02.826317 00280000 ################################################################
10166 10:02:02.826488
10167 10:02:03.072024 00300000 ################################################################
10168 10:02:03.072176
10169 10:02:03.315957 00380000 ################################################################
10170 10:02:03.316101
10171 10:02:03.566549 00400000 ################################################################
10172 10:02:03.566687
10173 10:02:03.813730 00480000 ################################################################
10174 10:02:03.813875
10175 10:02:04.061036 00500000 ################################################################
10176 10:02:04.061170
10177 10:02:04.327782 00580000 ################################################################
10178 10:02:04.327950
10179 10:02:04.577739 00600000 ################################################################
10180 10:02:04.577904
10181 10:02:04.822129 00680000 ################################################################
10182 10:02:04.822294
10183 10:02:05.087674 00700000 ################################################################
10184 10:02:05.087817
10185 10:02:05.335122 00780000 ################################################################
10186 10:02:05.335262
10187 10:02:05.579760 00800000 ################################################################
10188 10:02:05.579932
10189 10:02:05.825919 00880000 ################################################################
10190 10:02:05.826061
10191 10:02:06.070635 00900000 ################################################################
10192 10:02:06.070766
10193 10:02:06.316535 00980000 ################################################################
10194 10:02:06.316684
10195 10:02:06.565348 00a00000 ################################################################
10196 10:02:06.565514
10197 10:02:06.823333 00a80000 ################################################################
10198 10:02:06.823520
10199 10:02:07.095359 00b00000 ################################################################
10200 10:02:07.095497
10201 10:02:07.345919 00b80000 ################################################################
10202 10:02:07.346053
10203 10:02:07.591993 00c00000 ################################################################
10204 10:02:07.592126
10205 10:02:07.835948 00c80000 ################################################################
10206 10:02:07.836107
10207 10:02:08.079786 00d00000 ################################################################
10208 10:02:08.079950
10209 10:02:08.324887 00d80000 ################################################################
10210 10:02:08.325046
10211 10:02:08.570134 00e00000 ################################################################
10212 10:02:08.570299
10213 10:02:08.815111 00e80000 ################################################################
10214 10:02:08.815245
10215 10:02:09.059542 00f00000 ################################################################
10216 10:02:09.059703
10217 10:02:09.305703 00f80000 ################################################################
10218 10:02:09.305870
10219 10:02:09.550506 01000000 ################################################################
10220 10:02:09.550642
10221 10:02:09.801287 01080000 ################################################################
10222 10:02:09.801449
10223 10:02:10.045006 01100000 ################################################################
10224 10:02:10.045169
10225 10:02:10.289418 01180000 ################################################################
10226 10:02:10.289550
10227 10:02:10.534681 01200000 ################################################################
10228 10:02:10.534842
10229 10:02:10.780094 01280000 ################################################################
10230 10:02:10.780235
10231 10:02:11.024795 01300000 ################################################################
10232 10:02:11.024949
10233 10:02:11.270035 01380000 ################################################################
10234 10:02:11.270176
10235 10:02:11.514612 01400000 ################################################################
10236 10:02:11.514755
10237 10:02:11.759624 01480000 ################################################################
10238 10:02:11.759758
10239 10:02:12.003337 01500000 ################################################################
10240 10:02:12.003469
10241 10:02:12.248254 01580000 ################################################################
10242 10:02:12.248390
10243 10:02:12.494270 01600000 ################################################################
10244 10:02:12.494459
10245 10:02:12.738903 01680000 ################################################################
10246 10:02:12.739047
10247 10:02:12.982987 01700000 ################################################################
10248 10:02:12.983125
10249 10:02:13.229418 01780000 ################################################################
10250 10:02:13.229554
10251 10:02:13.474192 01800000 ################################################################
10252 10:02:13.474329
10253 10:02:13.718828 01880000 ################################################################
10254 10:02:13.718961
10255 10:02:13.962952 01900000 ################################################################
10256 10:02:13.963088
10257 10:02:14.207939 01980000 ################################################################
10258 10:02:14.208103
10259 10:02:14.458549 01a00000 ################################################################
10260 10:02:14.458683
10261 10:02:14.702331 01a80000 ################################################################
10262 10:02:14.702506
10263 10:02:14.946858 01b00000 ################################################################
10264 10:02:14.946994
10265 10:02:14.974725 01b80000 ######## done.
10266 10:02:14.974824
10267 10:02:14.977645 The bootfile was 28898726 bytes long.
10268 10:02:14.977723
10269 10:02:14.981240 Sending tftp read request... done.
10270 10:02:14.981338
10271 10:02:14.984486 Waiting for the transfer...
10272 10:02:14.984566
10273 10:02:14.987876 00000000 # done.
10274 10:02:14.987953
10275 10:02:14.994616 Command line loaded dynamically from TFTP file: 12073307/tftp-deploy-qs3gwgws/kernel/cmdline
10276 10:02:14.994694
10277 10:02:15.017842 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12073307/extract-nfsrootfs-s5xwbqap,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10278 10:02:15.017974
10279 10:02:15.018073 Loading FIT.
10280 10:02:15.018166
10281 10:02:15.021065 Image ramdisk-1 has 17801871 bytes.
10282 10:02:15.021182
10283 10:02:15.024800 Image fdt-1 has 47278 bytes.
10284 10:02:15.024927
10285 10:02:15.028040 Image kernel-1 has 11047542 bytes.
10286 10:02:15.028181
10287 10:02:15.034664 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10288 10:02:15.034825
10289 10:02:15.054744 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10290 10:02:15.055193
10291 10:02:15.057900 Choosing best match conf-1 for compat google,spherion-rev2.
10292 10:02:15.062981
10293 10:02:15.067499 Connected to device vid:did:rid of 1ae0:0028:00
10294 10:02:15.075811
10295 10:02:15.079137 tpm_get_response: command 0x17b, return code 0x0
10296 10:02:15.079634
10297 10:02:15.082153 ec_init: CrosEC protocol v3 supported (256, 248)
10298 10:02:15.086280
10299 10:02:15.089689 tpm_cleanup: add release locality here.
10300 10:02:15.090161
10301 10:02:15.090578 Shutting down all USB controllers.
10302 10:02:15.093166
10303 10:02:15.093640 Removing current net device
10304 10:02:15.094013
10305 10:02:15.099746 Exiting depthcharge with code 4 at timestamp: 49404050
10306 10:02:15.100219
10307 10:02:15.102710 LZMA decompressing kernel-1 to 0x821a6718
10308 10:02:15.102793
10309 10:02:15.105752 LZMA decompressing kernel-1 to 0x40000000
10310 10:02:16.495263
10311 10:02:16.495410 jumping to kernel
10312 10:02:16.495858 end: 2.2.4 bootloader-commands (duration 00:00:21) [common]
10313 10:02:16.495963 start: 2.2.5 auto-login-action (timeout 00:04:04) [common]
10314 10:02:16.496054 Setting prompt string to ['Linux version [0-9]']
10315 10:02:16.496127 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10316 10:02:16.496195 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10317 10:02:16.577637
10318 10:02:16.580967 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10319 10:02:16.584415 start: 2.2.5.1 login-action (timeout 00:04:04) [common]
10320 10:02:16.584510 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10321 10:02:16.584583 Setting prompt string to []
10322 10:02:16.584661 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10323 10:02:16.584735 Using line separator: #'\n'#
10324 10:02:16.584796 No login prompt set.
10325 10:02:16.584859 Parsing kernel messages
10326 10:02:16.584916 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10327 10:02:16.585019 [login-action] Waiting for messages, (timeout 00:04:04)
10328 10:02:16.604128 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j22848-arm64-gcc-10-defconfig-arm64-chromebook-6q8mw) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Nov 24 09:44:51 UTC 2023
10329 10:02:16.607470 [ 0.000000] random: crng init done
10330 10:02:16.611097 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10331 10:02:16.614290 [ 0.000000] efi: UEFI not found.
10332 10:02:16.624454 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10333 10:02:16.630630 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10334 10:02:16.640555 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10335 10:02:16.650852 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10336 10:02:16.657692 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10337 10:02:16.661050 [ 0.000000] printk: bootconsole [mtk8250] enabled
10338 10:02:16.669631 [ 0.000000] NUMA: No NUMA configuration found
10339 10:02:16.675946 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10340 10:02:16.682626 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10341 10:02:16.682710 [ 0.000000] Zone ranges:
10342 10:02:16.689314 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10343 10:02:16.692437 [ 0.000000] DMA32 empty
10344 10:02:16.699267 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10345 10:02:16.702795 [ 0.000000] Movable zone start for each node
10346 10:02:16.705791 [ 0.000000] Early memory node ranges
10347 10:02:16.712555 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10348 10:02:16.719181 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10349 10:02:16.725703 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10350 10:02:16.732137 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10351 10:02:16.738623 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10352 10:02:16.745476 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10353 10:02:16.801975 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10354 10:02:16.808551 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10355 10:02:16.815279 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10356 10:02:16.818513 [ 0.000000] psci: probing for conduit method from DT.
10357 10:02:16.825436 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10358 10:02:16.828457 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10359 10:02:16.835439 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10360 10:02:16.838672 [ 0.000000] psci: SMC Calling Convention v1.2
10361 10:02:16.845338 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10362 10:02:16.848500 [ 0.000000] Detected VIPT I-cache on CPU0
10363 10:02:16.855132 [ 0.000000] CPU features: detected: GIC system register CPU interface
10364 10:02:16.861742 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10365 10:02:16.868593 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10366 10:02:16.875356 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10367 10:02:16.882002 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10368 10:02:16.891847 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10369 10:02:16.894995 [ 0.000000] alternatives: applying boot alternatives
10370 10:02:16.901503 [ 0.000000] Fallback order for Node 0: 0
10371 10:02:16.908392 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10372 10:02:16.911840 [ 0.000000] Policy zone: Normal
10373 10:02:16.934486 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12073307/extract-nfsrootfs-s5xwbqap,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10374 10:02:16.944395 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10375 10:02:16.954183 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10376 10:02:16.964060 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10377 10:02:16.970742 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10378 10:02:16.974013 <6>[ 0.000000] software IO TLB: area num 8.
10379 10:02:17.030645 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10380 10:02:17.179679 <6>[ 0.000000] Memory: 7952232K/8385536K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 400536K reserved, 32768K cma-reserved)
10381 10:02:17.186650 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10382 10:02:17.193285 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10383 10:02:17.196384 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10384 10:02:17.203204 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10385 10:02:17.209979 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10386 10:02:17.213162 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10387 10:02:17.222780 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10388 10:02:17.229701 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10389 10:02:17.233187 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10390 10:02:17.240733 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10391 10:02:17.244338 <6>[ 0.000000] GICv3: 608 SPIs implemented
10392 10:02:17.251006 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10393 10:02:17.254237 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10394 10:02:17.257337 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10395 10:02:17.267108 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10396 10:02:17.276983 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10397 10:02:17.290204 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10398 10:02:17.296509 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10399 10:02:17.306284 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10400 10:02:17.319583 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10401 10:02:17.326138 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10402 10:02:17.333065 <6>[ 0.009232] Console: colour dummy device 80x25
10403 10:02:17.342793 <6>[ 0.013957] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10404 10:02:17.346153 <6>[ 0.024464] pid_max: default: 32768 minimum: 301
10405 10:02:17.352820 <6>[ 0.029336] LSM: Security Framework initializing
10406 10:02:17.359433 <6>[ 0.034274] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10407 10:02:17.369344 <6>[ 0.042135] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10408 10:02:17.376006 <6>[ 0.051543] cblist_init_generic: Setting adjustable number of callback queues.
10409 10:02:17.382484 <6>[ 0.059032] cblist_init_generic: Setting shift to 3 and lim to 1.
10410 10:02:17.392758 <6>[ 0.065410] cblist_init_generic: Setting adjustable number of callback queues.
10411 10:02:17.399487 <6>[ 0.072837] cblist_init_generic: Setting shift to 3 and lim to 1.
10412 10:02:17.402850 <6>[ 0.079277] rcu: Hierarchical SRCU implementation.
10413 10:02:17.409491 <6>[ 0.084323] rcu: Max phase no-delay instances is 1000.
10414 10:02:17.415912 <6>[ 0.091343] EFI services will not be available.
10415 10:02:17.419167 <6>[ 0.096294] smp: Bringing up secondary CPUs ...
10416 10:02:17.427757 <6>[ 0.101339] Detected VIPT I-cache on CPU1
10417 10:02:17.434055 <6>[ 0.101408] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10418 10:02:17.441043 <6>[ 0.101441] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10419 10:02:17.444485 <6>[ 0.101778] Detected VIPT I-cache on CPU2
10420 10:02:17.450849 <6>[ 0.101828] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10421 10:02:17.457476 <6>[ 0.101844] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10422 10:02:17.463992 <6>[ 0.102099] Detected VIPT I-cache on CPU3
10423 10:02:17.470910 <6>[ 0.102145] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10424 10:02:17.477231 <6>[ 0.102159] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10425 10:02:17.480619 <6>[ 0.102461] CPU features: detected: Spectre-v4
10426 10:02:17.487345 <6>[ 0.102468] CPU features: detected: Spectre-BHB
10427 10:02:17.490366 <6>[ 0.102473] Detected PIPT I-cache on CPU4
10428 10:02:17.497179 <6>[ 0.102532] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10429 10:02:17.503931 <6>[ 0.102549] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10430 10:02:17.510671 <6>[ 0.102844] Detected PIPT I-cache on CPU5
10431 10:02:17.517081 <6>[ 0.102910] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10432 10:02:17.523994 <6>[ 0.102926] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10433 10:02:17.526919 <6>[ 0.103208] Detected PIPT I-cache on CPU6
10434 10:02:17.533761 <6>[ 0.103273] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10435 10:02:17.540418 <6>[ 0.103289] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10436 10:02:17.547080 <6>[ 0.103588] Detected PIPT I-cache on CPU7
10437 10:02:17.553576 <6>[ 0.103654] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10438 10:02:17.560164 <6>[ 0.103670] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10439 10:02:17.563353 <6>[ 0.103717] smp: Brought up 1 node, 8 CPUs
10440 10:02:17.569991 <6>[ 0.244981] SMP: Total of 8 processors activated.
10441 10:02:17.573278 <6>[ 0.249902] CPU features: detected: 32-bit EL0 Support
10442 10:02:17.583163 <6>[ 0.255297] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10443 10:02:17.589907 <6>[ 0.264097] CPU features: detected: Common not Private translations
10444 10:02:17.593434 <6>[ 0.270572] CPU features: detected: CRC32 instructions
10445 10:02:17.600059 <6>[ 0.275923] CPU features: detected: RCpc load-acquire (LDAPR)
10446 10:02:17.606641 <6>[ 0.281883] CPU features: detected: LSE atomic instructions
10447 10:02:17.613215 <6>[ 0.287664] CPU features: detected: Privileged Access Never
10448 10:02:17.616242 <6>[ 0.293444] CPU features: detected: RAS Extension Support
10449 10:02:17.622851 <6>[ 0.299052] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10450 10:02:17.629556 <6>[ 0.306306] CPU: All CPU(s) started at EL2
10451 10:02:17.636466 <6>[ 0.310622] alternatives: applying system-wide alternatives
10452 10:02:17.644651 <6>[ 0.321365] devtmpfs: initialized
10453 10:02:17.657059 <6>[ 0.330331] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10454 10:02:17.667464 <6>[ 0.340293] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10455 10:02:17.670050 <6>[ 0.348076] pinctrl core: initialized pinctrl subsystem
10456 10:02:17.677996 <6>[ 0.354865] DMI not present or invalid.
10457 10:02:17.684591 <6>[ 0.359282] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10458 10:02:17.691468 <6>[ 0.366171] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10459 10:02:17.701685 <6>[ 0.373754] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10460 10:02:17.708025 <6>[ 0.381984] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10461 10:02:17.714547 <6>[ 0.390227] audit: initializing netlink subsys (disabled)
10462 10:02:17.721316 <5>[ 0.395917] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10463 10:02:17.728062 <6>[ 0.396664] thermal_sys: Registered thermal governor 'step_wise'
10464 10:02:17.734488 <6>[ 0.403885] thermal_sys: Registered thermal governor 'power_allocator'
10465 10:02:17.737678 <6>[ 0.410140] cpuidle: using governor menu
10466 10:02:17.744296 <6>[ 0.421099] NET: Registered PF_QIPCRTR protocol family
10467 10:02:17.751375 <6>[ 0.426595] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10468 10:02:17.757712 <6>[ 0.433699] ASID allocator initialised with 32768 entries
10469 10:02:17.764328 <6>[ 0.440314] Serial: AMBA PL011 UART driver
10470 10:02:17.772648 <4>[ 0.449480] Trying to register duplicate clock ID: 134
10471 10:02:17.829942 <6>[ 0.509632] KASLR enabled
10472 10:02:17.844332 <6>[ 0.517363] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10473 10:02:17.850736 <6>[ 0.524379] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10474 10:02:17.857486 <6>[ 0.530869] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10475 10:02:17.863865 <6>[ 0.537874] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10476 10:02:17.870564 <6>[ 0.544361] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10477 10:02:17.877188 <6>[ 0.551369] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10478 10:02:17.884071 <6>[ 0.557856] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10479 10:02:17.890293 <6>[ 0.564863] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10480 10:02:17.894043 <6>[ 0.572368] ACPI: Interpreter disabled.
10481 10:02:17.902397 <6>[ 0.578865] iommu: Default domain type: Translated
10482 10:02:17.908605 <6>[ 0.583976] iommu: DMA domain TLB invalidation policy: strict mode
10483 10:02:17.911954 <5>[ 0.590633] SCSI subsystem initialized
10484 10:02:17.918692 <6>[ 0.594792] usbcore: registered new interface driver usbfs
10485 10:02:17.925270 <6>[ 0.600525] usbcore: registered new interface driver hub
10486 10:02:17.928514 <6>[ 0.606078] usbcore: registered new device driver usb
10487 10:02:17.935697 <6>[ 0.612230] pps_core: LinuxPPS API ver. 1 registered
10488 10:02:17.945726 <6>[ 0.617423] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10489 10:02:17.948731 <6>[ 0.626773] PTP clock support registered
10490 10:02:17.952099 <6>[ 0.631019] EDAC MC: Ver: 3.0.0
10491 10:02:17.959578 <6>[ 0.636229] FPGA manager framework
10492 10:02:17.966080 <6>[ 0.639911] Advanced Linux Sound Architecture Driver Initialized.
10493 10:02:17.969513 <6>[ 0.646679] vgaarb: loaded
10494 10:02:17.976044 <6>[ 0.649794] clocksource: Switched to clocksource arch_sys_counter
10495 10:02:17.979503 <5>[ 0.656225] VFS: Disk quotas dquot_6.6.0
10496 10:02:17.986303 <6>[ 0.660411] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10497 10:02:17.989299 <6>[ 0.667599] pnp: PnP ACPI: disabled
10498 10:02:17.997621 <6>[ 0.674263] NET: Registered PF_INET protocol family
10499 10:02:18.007451 <6>[ 0.679845] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10500 10:02:18.019024 <6>[ 0.692140] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10501 10:02:18.029427 <6>[ 0.700954] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10502 10:02:18.035531 <6>[ 0.708922] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10503 10:02:18.042450 <6>[ 0.717620] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10504 10:02:18.054348 <6>[ 0.727371] TCP: Hash tables configured (established 65536 bind 65536)
10505 10:02:18.061458 <6>[ 0.734228] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10506 10:02:18.067289 <6>[ 0.741426] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10507 10:02:18.074030 <6>[ 0.749128] NET: Registered PF_UNIX/PF_LOCAL protocol family
10508 10:02:18.081175 <6>[ 0.755305] RPC: Registered named UNIX socket transport module.
10509 10:02:18.084097 <6>[ 0.761458] RPC: Registered udp transport module.
10510 10:02:18.090955 <6>[ 0.766391] RPC: Registered tcp transport module.
10511 10:02:18.097423 <6>[ 0.771324] RPC: Registered tcp NFSv4.1 backchannel transport module.
10512 10:02:18.100536 <6>[ 0.777989] PCI: CLS 0 bytes, default 64
10513 10:02:18.104112 <6>[ 0.782383] Unpacking initramfs...
10514 10:02:18.128606 <6>[ 0.801887] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10515 10:02:18.138784 <6>[ 0.810537] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10516 10:02:18.141964 <6>[ 0.819415] kvm [1]: IPA Size Limit: 40 bits
10517 10:02:18.148800 <6>[ 0.823943] kvm [1]: GICv3: no GICV resource entry
10518 10:02:18.152194 <6>[ 0.828964] kvm [1]: disabling GICv2 emulation
10519 10:02:18.158678 <6>[ 0.833653] kvm [1]: GIC system register CPU interface enabled
10520 10:02:18.162000 <6>[ 0.839816] kvm [1]: vgic interrupt IRQ18
10521 10:02:18.168882 <6>[ 0.844172] kvm [1]: VHE mode initialized successfully
10522 10:02:18.175288 <5>[ 0.850641] Initialise system trusted keyrings
10523 10:02:18.181988 <6>[ 0.855492] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10524 10:02:18.189300 <6>[ 0.865470] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10525 10:02:18.196047 <5>[ 0.871904] NFS: Registering the id_resolver key type
10526 10:02:18.199154 <5>[ 0.877206] Key type id_resolver registered
10527 10:02:18.205567 <5>[ 0.881622] Key type id_legacy registered
10528 10:02:18.212010 <6>[ 0.885900] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10529 10:02:18.218654 <6>[ 0.892823] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10530 10:02:18.225495 <6>[ 0.900531] 9p: Installing v9fs 9p2000 file system support
10531 10:02:18.262464 <5>[ 0.939032] Key type asymmetric registered
10532 10:02:18.265718 <5>[ 0.943364] Asymmetric key parser 'x509' registered
10533 10:02:18.275940 <6>[ 0.948505] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10534 10:02:18.279268 <6>[ 0.956120] io scheduler mq-deadline registered
10535 10:02:18.282443 <6>[ 0.960899] io scheduler kyber registered
10536 10:02:18.302081 <6>[ 0.978480] EINJ: ACPI disabled.
10537 10:02:18.335507 <4>[ 1.005161] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10538 10:02:18.345284 <4>[ 1.015803] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10539 10:02:18.360939 <6>[ 1.037048] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10540 10:02:18.368868 <6>[ 1.045102] printk: console [ttyS0] disabled
10541 10:02:18.397022 <6>[ 1.069753] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10542 10:02:18.403408 <6>[ 1.079237] printk: console [ttyS0] enabled
10543 10:02:18.406715 <6>[ 1.079237] printk: console [ttyS0] enabled
10544 10:02:18.413421 <6>[ 1.088131] printk: bootconsole [mtk8250] disabled
10545 10:02:18.416945 <6>[ 1.088131] printk: bootconsole [mtk8250] disabled
10546 10:02:18.423392 <6>[ 1.099399] SuperH (H)SCI(F) driver initialized
10547 10:02:18.426544 <6>[ 1.104703] msm_serial: driver initialized
10548 10:02:18.440664 <6>[ 1.113850] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10549 10:02:18.450704 <6>[ 1.122413] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10550 10:02:18.457238 <6>[ 1.130957] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10551 10:02:18.467067 <6>[ 1.139586] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10552 10:02:18.473823 <6>[ 1.148294] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10553 10:02:18.483994 <6>[ 1.157008] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10554 10:02:18.493835 <6>[ 1.165548] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10555 10:02:18.500242 <6>[ 1.174363] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10556 10:02:18.509986 <6>[ 1.182907] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10557 10:02:18.522024 <6>[ 1.198721] loop: module loaded
10558 10:02:18.528596 <6>[ 1.204659] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10559 10:02:18.551530 <4>[ 1.228070] mtk-pmic-keys: Failed to locate of_node [id: -1]
10560 10:02:18.558580 <6>[ 1.234943] megasas: 07.719.03.00-rc1
10561 10:02:18.568014 <6>[ 1.244597] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10562 10:02:18.577098 <6>[ 1.253165] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10563 10:02:18.593429 <6>[ 1.269817] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10564 10:02:18.649169 <6>[ 1.319164] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10565 10:02:18.845803 <6>[ 1.522769] Freeing initrd memory: 17384K
10566 10:02:18.856687 <6>[ 1.533321] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10567 10:02:18.867401 <6>[ 1.544268] tun: Universal TUN/TAP device driver, 1.6
10568 10:02:18.870941 <6>[ 1.550369] thunder_xcv, ver 1.0
10569 10:02:18.873925 <6>[ 1.553869] thunder_bgx, ver 1.0
10570 10:02:18.877432 <6>[ 1.557359] nicpf, ver 1.0
10571 10:02:18.887819 <6>[ 1.561402] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10572 10:02:18.891186 <6>[ 1.568877] hns3: Copyright (c) 2017 Huawei Corporation.
10573 10:02:18.894798 <6>[ 1.574464] hclge is initializing
10574 10:02:18.901629 <6>[ 1.578043] e1000: Intel(R) PRO/1000 Network Driver
10575 10:02:18.907961 <6>[ 1.583173] e1000: Copyright (c) 1999-2006 Intel Corporation.
10576 10:02:18.911238 <6>[ 1.589187] e1000e: Intel(R) PRO/1000 Network Driver
10577 10:02:18.918000 <6>[ 1.594402] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10578 10:02:18.924643 <6>[ 1.600588] igb: Intel(R) Gigabit Ethernet Network Driver
10579 10:02:18.931065 <6>[ 1.606238] igb: Copyright (c) 2007-2014 Intel Corporation.
10580 10:02:18.937830 <6>[ 1.612073] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10581 10:02:18.944570 <6>[ 1.618591] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10582 10:02:18.947658 <6>[ 1.625064] sky2: driver version 1.30
10583 10:02:18.954282 <6>[ 1.630101] VFIO - User Level meta-driver version: 0.3
10584 10:02:18.961971 <6>[ 1.638396] usbcore: registered new interface driver usb-storage
10585 10:02:18.968502 <6>[ 1.644840] usbcore: registered new device driver onboard-usb-hub
10586 10:02:18.977163 <6>[ 1.654083] mt6397-rtc mt6359-rtc: registered as rtc0
10587 10:02:18.987423 <6>[ 1.659550] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-24T10:01:46 UTC (1700820106)
10588 10:02:18.990830 <6>[ 1.669134] i2c_dev: i2c /dev entries driver
10589 10:02:19.007354 <6>[ 1.681050] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10590 10:02:19.027724 <6>[ 1.704054] cpu cpu0: EM: created perf domain
10591 10:02:19.030766 <6>[ 1.708972] cpu cpu4: EM: created perf domain
10592 10:02:19.038147 <6>[ 1.714567] sdhci: Secure Digital Host Controller Interface driver
10593 10:02:19.044317 <6>[ 1.720998] sdhci: Copyright(c) Pierre Ossman
10594 10:02:19.051626 <6>[ 1.725962] Synopsys Designware Multimedia Card Interface Driver
10595 10:02:19.054536 <6>[ 1.732601] mmc0: CQHCI version 5.10
10596 10:02:19.061392 <6>[ 1.732610] sdhci-pltfm: SDHCI platform and OF driver helper
10597 10:02:19.067941 <6>[ 1.743470] ledtrig-cpu: registered to indicate activity on CPUs
10598 10:02:19.074771 <6>[ 1.750427] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10599 10:02:19.081410 <6>[ 1.757483] usbcore: registered new interface driver usbhid
10600 10:02:19.084518 <6>[ 1.763306] usbhid: USB HID core driver
10601 10:02:19.091376 <6>[ 1.767504] spi_master spi0: will run message pump with realtime priority
10602 10:02:19.138782 <6>[ 1.808479] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10603 10:02:19.158292 <6>[ 1.823837] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10604 10:02:19.161008 <6>[ 1.837429] mmc0: Command Queue Engine enabled
10605 10:02:19.168339 <6>[ 1.839717] cros-ec-spi spi0.0: Chrome EC device registered
10606 10:02:19.174349 <6>[ 1.842165] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10607 10:02:19.177772 <6>[ 1.855458] mmcblk0: mmc0:0001 DA4128 116 GiB
10608 10:02:19.190034 <6>[ 1.862679] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10609 10:02:19.196529 <6>[ 1.866086] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10610 10:02:19.203397 <6>[ 1.873060] NET: Registered PF_PACKET protocol family
10611 10:02:19.206080 <6>[ 1.879459] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10612 10:02:19.213469 <6>[ 1.883335] 9pnet: Installing 9P2000 support
10613 10:02:19.216120 <6>[ 1.889113] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10614 10:02:19.222981 <5>[ 1.893009] Key type dns_resolver registered
10615 10:02:19.226170 <6>[ 1.898879] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10616 10:02:19.233177 <6>[ 1.903271] registered taskstats version 1
10617 10:02:19.236119 <5>[ 1.913637] Loading compiled-in X.509 certificates
10618 10:02:19.265409 <4>[ 1.935127] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10619 10:02:19.275150 <4>[ 1.945872] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10620 10:02:19.281819 <3>[ 1.956410] debugfs: File 'uA_load' in directory '/' already present!
10621 10:02:19.288257 <3>[ 1.963108] debugfs: File 'min_uV' in directory '/' already present!
10622 10:02:19.294993 <3>[ 1.969714] debugfs: File 'max_uV' in directory '/' already present!
10623 10:02:19.301867 <3>[ 1.976378] debugfs: File 'constraint_flags' in directory '/' already present!
10624 10:02:19.313003 <3>[ 1.986248] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10625 10:02:19.322043 <6>[ 1.998885] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10626 10:02:19.328680 <6>[ 2.005555] xhci-mtk 11200000.usb: xHCI Host Controller
10627 10:02:19.335288 <6>[ 2.011041] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10628 10:02:19.345843 <6>[ 2.018877] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10629 10:02:19.352119 <6>[ 2.028300] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10630 10:02:19.358726 <6>[ 2.034358] xhci-mtk 11200000.usb: xHCI Host Controller
10631 10:02:19.365531 <6>[ 2.039838] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10632 10:02:19.372122 <6>[ 2.047484] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10633 10:02:19.378816 <6>[ 2.055145] hub 1-0:1.0: USB hub found
10634 10:02:19.382062 <6>[ 2.059153] hub 1-0:1.0: 1 port detected
10635 10:02:19.388888 <6>[ 2.063419] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10636 10:02:19.395746 <6>[ 2.071966] hub 2-0:1.0: USB hub found
10637 10:02:19.398961 <6>[ 2.075971] hub 2-0:1.0: 1 port detected
10638 10:02:19.407383 <6>[ 2.084178] mtk-msdc 11f70000.mmc: Got CD GPIO
10639 10:02:19.418164 <6>[ 2.091441] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10640 10:02:19.424558 <6>[ 2.099465] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10641 10:02:19.435176 <4>[ 2.107381] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10642 10:02:19.444938 <6>[ 2.116913] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10643 10:02:19.451660 <6>[ 2.124990] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10644 10:02:19.458174 <6>[ 2.133007] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10645 10:02:19.468411 <6>[ 2.140932] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10646 10:02:19.474761 <6>[ 2.148748] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10647 10:02:19.484872 <6>[ 2.156565] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10648 10:02:19.494882 <6>[ 2.166811] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10649 10:02:19.501765 <6>[ 2.175198] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10650 10:02:19.511886 <6>[ 2.183537] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10651 10:02:19.518494 <6>[ 2.191875] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10652 10:02:19.528925 <6>[ 2.200215] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10653 10:02:19.535503 <6>[ 2.208555] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10654 10:02:19.545174 <6>[ 2.216896] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10655 10:02:19.551918 <6>[ 2.225235] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10656 10:02:19.562090 <6>[ 2.233574] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10657 10:02:19.568812 <6>[ 2.241912] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10658 10:02:19.578516 <6>[ 2.250267] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10659 10:02:19.585518 <6>[ 2.258607] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10660 10:02:19.595026 <6>[ 2.266945] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10661 10:02:19.601859 <6>[ 2.275283] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10662 10:02:19.611798 <6>[ 2.283622] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10663 10:02:19.618513 <6>[ 2.292214] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10664 10:02:19.625311 <6>[ 2.299428] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10665 10:02:19.631743 <6>[ 2.306307] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10666 10:02:19.638653 <6>[ 2.313141] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10667 10:02:19.645462 <6>[ 2.320137] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10668 10:02:19.655334 <6>[ 2.327011] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10669 10:02:19.665114 <6>[ 2.336141] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10670 10:02:19.671953 <6>[ 2.345259] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10671 10:02:19.682507 <6>[ 2.354553] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10672 10:02:19.692307 <6>[ 2.364024] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10673 10:02:19.701388 <6>[ 2.373491] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10674 10:02:19.711491 <6>[ 2.382612] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10675 10:02:19.721390 <6>[ 2.392080] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10676 10:02:19.728104 <6>[ 2.401201] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10677 10:02:19.737866 <6>[ 2.410498] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10678 10:02:19.748265 <6>[ 2.420658] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10679 10:02:19.759498 <6>[ 2.432238] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10680 10:02:19.766039 <6>[ 2.442061] Trying to probe devices needed for running init ...
10681 10:02:19.788835 <6>[ 2.462066] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10682 10:02:19.816590 <6>[ 2.492905] hub 2-1:1.0: USB hub found
10683 10:02:19.819641 <6>[ 2.497333] hub 2-1:1.0: 3 ports detected
10684 10:02:19.827822 <6>[ 2.504481] hub 2-1:1.0: USB hub found
10685 10:02:19.831184 <6>[ 2.508913] hub 2-1:1.0: 3 ports detected
10686 10:02:19.941022 <6>[ 2.614095] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10687 10:02:20.100093 <6>[ 2.776084] hub 1-1:1.0: USB hub found
10688 10:02:20.102952 <6>[ 2.780557] hub 1-1:1.0: 4 ports detected
10689 10:02:20.112384 <6>[ 2.788594] hub 1-1:1.0: USB hub found
10690 10:02:20.115596 <6>[ 2.793155] hub 1-1:1.0: 4 ports detected
10691 10:02:20.185019 <6>[ 2.858268] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10692 10:02:20.436580 <6>[ 3.110090] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10693 10:02:20.569426 <6>[ 3.245990] hub 1-1.4:1.0: USB hub found
10694 10:02:20.572805 <6>[ 3.250651] hub 1-1.4:1.0: 2 ports detected
10695 10:02:20.582780 <6>[ 3.259276] hub 1-1.4:1.0: USB hub found
10696 10:02:20.585725 <6>[ 3.263885] hub 1-1.4:1.0: 2 ports detected
10697 10:02:20.884275 <6>[ 3.558086] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10698 10:02:21.076110 <6>[ 3.750048] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10699 10:02:32.054253 <6>[ 14.735124] ALSA device list:
10700 10:02:32.060596 <6>[ 14.738419] No soundcards found.
10701 10:02:32.068256 <6>[ 14.746361] Freeing unused kernel memory: 8384K
10702 10:02:32.071711 <6>[ 14.751414] Run /init as init process
10703 10:02:32.083253 Loading, please wait...
10704 10:02:32.103807 Starting version 247.3-7+deb11u2
10705 10:02:32.334628 <6>[ 15.009239] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10706 10:02:32.348238 <6>[ 15.022499] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10707 10:02:32.354799 <6>[ 15.029205] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10708 10:02:32.364951 <6>[ 15.031514] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10709 10:02:32.371245 <3>[ 15.041654] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10710 10:02:32.380821 <6>[ 15.048288] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10711 10:02:32.384414 <6>[ 15.052870] remoteproc remoteproc0: scp is available
10712 10:02:32.390800 <6>[ 15.053049] remoteproc remoteproc0: powering up scp
10713 10:02:32.401169 <6>[ 15.053064] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10714 10:02:32.404026 <6>[ 15.053112] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10715 10:02:32.413840 <3>[ 15.055548] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10716 10:02:32.420383 <4>[ 15.064486] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10717 10:02:32.427648 <4>[ 15.064486] Fallback method does not support PEC.
10718 10:02:32.430777 <6>[ 15.064925] mc: Linux media interface: v0.10
10719 10:02:32.437672 <3>[ 15.068782] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10720 10:02:32.445043 <6>[ 15.075410] videodev: Linux video capture interface: v2.00
10721 10:02:32.454966 <3>[ 15.082590] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10722 10:02:32.461410 <4>[ 15.083232] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10723 10:02:32.468347 <4>[ 15.083490] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10724 10:02:32.475423 <6>[ 15.089846] usbcore: registered new interface driver r8152
10725 10:02:32.481714 <3>[ 15.096112] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10726 10:02:32.491763 <3>[ 15.123605] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10727 10:02:32.498451 <3>[ 15.128175] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10728 10:02:32.509087 <3>[ 15.156796] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10729 10:02:32.515321 <3>[ 15.164770] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10730 10:02:32.521602 <6>[ 15.178807] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10731 10:02:32.531503 <3>[ 15.181719] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10732 10:02:32.538325 <6>[ 15.183152] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10733 10:02:32.544795 <6>[ 15.183157] pci_bus 0000:00: root bus resource [bus 00-ff]
10734 10:02:32.551532 <6>[ 15.183164] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10735 10:02:32.561438 <6>[ 15.183168] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10736 10:02:32.568284 <6>[ 15.183197] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10737 10:02:32.574808 <6>[ 15.183212] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10738 10:02:32.578276 <6>[ 15.183283] pci 0000:00:00.0: supports D1 D2
10739 10:02:32.584858 <6>[ 15.183286] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10740 10:02:32.594698 <6>[ 15.184437] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10741 10:02:32.601250 <6>[ 15.184514] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10742 10:02:32.608036 <6>[ 15.184539] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10743 10:02:32.614302 <6>[ 15.184554] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10744 10:02:32.624323 <6>[ 15.184569] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10745 10:02:32.627670 <6>[ 15.184673] pci 0000:01:00.0: supports D1 D2
10746 10:02:32.634466 <6>[ 15.184675] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10747 10:02:32.643906 <6>[ 15.190591] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10748 10:02:32.651049 <6>[ 15.194056] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10749 10:02:32.657586 <6>[ 15.194091] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10750 10:02:32.667254 <6>[ 15.194095] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10751 10:02:32.673917 <6>[ 15.194106] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10752 10:02:32.680478 <6>[ 15.194119] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10753 10:02:32.690506 <6>[ 15.194135] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10754 10:02:32.693933 <6>[ 15.194154] pci 0000:00:00.0: PCI bridge to [bus 01]
10755 10:02:32.703694 <6>[ 15.194164] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10756 10:02:32.710306 <6>[ 15.194416] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10757 10:02:32.717957 <6>[ 15.195000] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10758 10:02:32.720575 <6>[ 15.195542] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10759 10:02:32.731437 <3>[ 15.199243] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10760 10:02:32.737483 <6>[ 15.206013] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10761 10:02:32.743652 <6>[ 15.206344] remoteproc remoteproc0: remote processor scp is now up
10762 10:02:32.750516 <6>[ 15.207419] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10763 10:02:32.760455 <6>[ 15.209927] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10764 10:02:32.770625 <6>[ 15.210027] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10765 10:02:32.780695 <6>[ 15.213860] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10766 10:02:32.787007 <6>[ 15.214156] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10767 10:02:32.797369 <3>[ 15.214309] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10768 10:02:32.803216 <3>[ 15.214315] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10769 10:02:32.813430 <3>[ 15.214318] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10770 10:02:32.819795 <3>[ 15.214364] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10771 10:02:32.829711 <3>[ 15.214368] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10772 10:02:32.836295 <3>[ 15.214370] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10773 10:02:32.846155 <3>[ 15.214374] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10774 10:02:32.852819 <3>[ 15.214377] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10775 10:02:32.859624 <3>[ 15.214391] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10776 10:02:32.869157 <4>[ 15.245049] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10777 10:02:32.879345 <5>[ 15.271519] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10778 10:02:32.886053 <4>[ 15.277332] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10779 10:02:32.892521 <6>[ 15.291203] usbcore: registered new interface driver cdc_ether
10780 10:02:32.899146 <5>[ 15.307229] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10781 10:02:32.905922 <6>[ 15.317972] usbcore: registered new interface driver r8153_ecm
10782 10:02:32.912353 <6>[ 15.318382] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10783 10:02:32.918995 <4>[ 15.326428] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10784 10:02:32.925448 <6>[ 15.329852] Bluetooth: Core ver 2.22
10785 10:02:32.928847 <6>[ 15.329949] NET: Registered PF_BLUETOOTH protocol family
10786 10:02:32.935465 <6>[ 15.329952] Bluetooth: HCI device and connection manager initialized
10787 10:02:32.941866 <6>[ 15.329980] Bluetooth: HCI socket layer initialized
10788 10:02:32.945440 <6>[ 15.329987] Bluetooth: L2CAP socket layer initialized
10789 10:02:32.952257 <6>[ 15.330001] Bluetooth: SCO socket layer initialized
10790 10:02:32.958746 <6>[ 15.334318] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10791 10:02:32.964933 <6>[ 15.341007] cfg80211: failed to load regulatory.db
10792 10:02:32.975029 <6>[ 15.370158] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10793 10:02:32.982090 <6>[ 15.379272] usbcore: registered new interface driver btusb
10794 10:02:32.991371 <4>[ 15.380019] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10795 10:02:32.998621 <3>[ 15.380026] Bluetooth: hci0: Failed to load firmware file (-2)
10796 10:02:33.004619 <3>[ 15.380028] Bluetooth: hci0: Failed to set up firmware (-2)
10797 10:02:33.015060 <4>[ 15.380030] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10798 10:02:33.018015 <6>[ 15.381895] r8152 2-1.3:1.0 eth0: v1.12.13
10799 10:02:33.024723 <6>[ 15.386610] usbcore: registered new interface driver uvcvideo
10800 10:02:33.031262 <6>[ 15.389052] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10801 10:02:33.038351 <6>[ 15.420415] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10802 10:02:33.044508 <6>[ 15.721678] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10803 10:02:33.070648 <6>[ 15.748397] mt7921e 0000:01:00.0: ASIC revision: 79610010
10804 10:02:33.177625 <4>[ 15.849107] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10805 10:02:33.192412 Begin: Loading essential drivers ... done.
10806 10:02:33.199120 Begin: Running /scripts/init-premount ... done.
10807 10:02:33.205950 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10808 10:02:33.213114 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10809 10:02:33.215685 Device /sys/class/net/enx00e04c722dd6 found
10810 10:02:33.219017 done.
10811 10:02:33.267408 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10812 10:02:33.296359 <4>[ 15.967762] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10813 10:02:33.412067 <4>[ 16.083321] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10814 10:02:33.527938 <4>[ 16.199184] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10815 10:02:33.643962 <4>[ 16.315098] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10816 10:02:33.759457 <4>[ 16.431018] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10817 10:02:33.875836 <4>[ 16.547082] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10818 10:02:33.991505 <4>[ 16.662930] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10819 10:02:34.107501 <4>[ 16.778910] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10820 10:02:34.223164 <4>[ 16.894790] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10821 10:02:34.330696 <3>[ 17.008794] mt7921e 0000:01:00.0: hardware init failed
10822 10:02:34.390780 <6>[ 17.068524] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
10823 10:02:34.481640 IP-Config: no response after 2 secs - giving up
10824 10:02:34.531273 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10825 10:02:34.534612 IP-Config: enx00e04c722dd6 complete (dhcp from 192.168.201.1):
10826 10:02:34.544239 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10827 10:02:34.550916 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10828 10:02:34.557925 host : mt8192-asurada-spherion-r0-cbg-1
10829 10:02:34.564583 domain : lava-rack
10830 10:02:34.567686 rootserver: 192.168.201.1 rootpath:
10831 10:02:34.568156 filename :
10832 10:02:34.670338 done.
10833 10:02:34.677716 Begin: Running /scripts/nfs-bottom ... done.
10834 10:02:34.696480 Begin: Running /scripts/init-bottom ... done.
10835 10:02:35.908149 <6>[ 18.586421] NET: Registered PF_INET6 protocol family
10836 10:02:35.915896 <6>[ 18.593933] Segment Routing with IPv6
10837 10:02:35.919081 <6>[ 18.597928] In-situ OAM (IOAM) with IPv6
10838 10:02:36.043926 <30>[ 18.702394] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10839 10:02:36.047281 <30>[ 18.726811] systemd[1]: Detected architecture arm64.
10840 10:02:36.070141
10841 10:02:36.073652 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10842 10:02:36.074132
10843 10:02:36.090694 <30>[ 18.769065] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10844 10:02:37.001929 <30>[ 19.677047] systemd[1]: Queued start job for default target Graphical Interface.
10845 10:02:37.030513 <30>[ 19.708459] systemd[1]: Created slice system-getty.slice.
10846 10:02:37.036754 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10847 10:02:37.052935 <30>[ 19.731502] systemd[1]: Created slice system-modprobe.slice.
10848 10:02:37.059573 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10849 10:02:37.076790 <30>[ 19.755306] systemd[1]: Created slice system-serial\x2dgetty.slice.
10850 10:02:37.087076 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10851 10:02:37.100717 <30>[ 19.779132] systemd[1]: Created slice User and Session Slice.
10852 10:02:37.107126 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10853 10:02:37.127626 <30>[ 19.802916] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10854 10:02:37.137568 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10855 10:02:37.155859 <30>[ 19.830873] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10856 10:02:37.162371 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10857 10:02:37.186643 <30>[ 19.858270] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10858 10:02:37.193284 <30>[ 19.870557] systemd[1]: Reached target Local Encrypted Volumes.
10859 10:02:37.199939 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10860 10:02:37.216023 <30>[ 19.894294] systemd[1]: Reached target Paths.
10861 10:02:37.219056 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10862 10:02:37.235940 <30>[ 19.914089] systemd[1]: Reached target Remote File Systems.
10863 10:02:37.242141 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10864 10:02:37.259833 <30>[ 19.938312] systemd[1]: Reached target Slices.
10865 10:02:37.266479 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10866 10:02:37.279712 <30>[ 19.958108] systemd[1]: Reached target Swap.
10867 10:02:37.282986 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10868 10:02:37.303376 <30>[ 19.978595] systemd[1]: Listening on initctl Compatibility Named Pipe.
10869 10:02:37.310483 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10870 10:02:37.316691 <30>[ 19.994940] systemd[1]: Listening on Journal Audit Socket.
10871 10:02:37.323260 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10872 10:02:37.341378 <30>[ 20.019588] systemd[1]: Listening on Journal Socket (/dev/log).
10873 10:02:37.347695 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10874 10:02:37.364479 <30>[ 20.042671] systemd[1]: Listening on Journal Socket.
10875 10:02:37.370594 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10876 10:02:37.388411 <30>[ 20.063164] systemd[1]: Listening on Network Service Netlink Socket.
10877 10:02:37.394764 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10878 10:02:37.410750 <30>[ 20.089205] systemd[1]: Listening on udev Control Socket.
10879 10:02:37.417756 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10880 10:02:37.432267 <30>[ 20.110551] systemd[1]: Listening on udev Kernel Socket.
10881 10:02:37.438481 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10882 10:02:37.492011 <30>[ 20.170445] systemd[1]: Mounting Huge Pages File System...
10883 10:02:37.498465 Mounting [0;1;39mHuge Pages File System[0m...
10884 10:02:37.514004 <30>[ 20.192411] systemd[1]: Mounting POSIX Message Queue File System...
10885 10:02:37.520617 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10886 10:02:37.538838 <30>[ 20.217345] systemd[1]: Mounting Kernel Debug File System...
10887 10:02:37.545255 Mounting [0;1;39mKernel Debug File System[0m...
10888 10:02:37.563279 <30>[ 20.238486] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10889 10:02:37.578494 <30>[ 20.253863] systemd[1]: Starting Create list of static device nodes for the current kernel...
10890 10:02:37.584998 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10891 10:02:37.610322 <30>[ 20.289165] systemd[1]: Starting Load Kernel Module configfs...
10892 10:02:37.617825 Starting [0;1;39mLoad Kernel Module configfs[0m...
10893 10:02:37.640316 <30>[ 20.318906] systemd[1]: Starting Load Kernel Module drm...
10894 10:02:37.647030 Starting [0;1;39mLoad Kernel Module drm[0m...
10895 10:02:37.664218 <30>[ 20.342859] systemd[1]: Starting Load Kernel Module fuse...
10896 10:02:37.670729 Starting [0;1;39mLoad Kernel Module fuse[0m...
10897 10:02:37.704729 <6>[ 20.383200] fuse: init (API version 7.37)
10898 10:02:37.714504 <30>[ 20.383607] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10899 10:02:37.748662 <30>[ 20.426913] systemd[1]: Starting Journal Service...
10900 10:02:37.755180 Starting [0;1;39mJournal Service[0m...
10901 10:02:37.779609 <30>[ 20.457946] systemd[1]: Starting Load Kernel Modules...
10902 10:02:37.785685 Starting [0;1;39mLoad Kernel Modules[0m...
10903 10:02:37.807803 <30>[ 20.482984] systemd[1]: Starting Remount Root and Kernel File Systems...
10904 10:02:37.814124 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10905 10:02:37.835155 <30>[ 20.514046] systemd[1]: Starting Coldplug All udev Devices...
10906 10:02:37.842039 Starting [0;1;39mColdplug All udev Devices[0m...
10907 10:02:37.864472 <30>[ 20.543309] systemd[1]: Mounted Huge Pages File System.
10908 10:02:37.871204 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10909 10:02:37.887875 <3>[ 20.563327] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10910 10:02:37.894345 <30>[ 20.572963] systemd[1]: Mounted POSIX Message Queue File System.
10911 10:02:37.901027 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10912 10:02:37.917162 <3>[ 20.592599] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 10:02:37.923963 <30>[ 20.602685] systemd[1]: Mounted Kernel Debug File System.
10914 10:02:37.930849 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10915 10:02:37.952908 <30>[ 20.627664] systemd[1]: Finished Create list of static device nodes for the current kernel.
10916 10:02:37.963043 <3>[ 20.633915] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10917 10:02:37.969400 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10918 10:02:37.984925 <30>[ 20.662875] systemd[1]: modprobe@configfs.service: Succeeded.
10919 10:02:37.994552 <3>[ 20.665196] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10920 10:02:38.001220 <30>[ 20.669843] systemd[1]: Finished Load Kernel Module configfs.
10921 10:02:38.007467 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10922 10:02:38.020516 <30>[ 20.699076] systemd[1]: modprobe@drm.service: Succeeded.
10923 10:02:38.030111 <3>[ 20.701513] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10924 10:02:38.037177 <30>[ 20.705727] systemd[1]: Finished Load Kernel Module drm.
10925 10:02:38.040328 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10926 10:02:38.057258 <30>[ 20.735657] systemd[1]: modprobe@fuse.service: Succeeded.
10927 10:02:38.067281 <3>[ 20.736979] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10928 10:02:38.073789 <30>[ 20.742763] systemd[1]: Finished Load Kernel Module fuse.
10929 10:02:38.080280 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10930 10:02:38.097529 <30>[ 20.776091] systemd[1]: Finished Load Kernel Modules.
10931 10:02:38.107932 <3>[ 20.776759] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 10:02:38.111139 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10933 10:02:38.129582 <30>[ 20.807864] systemd[1]: Finished Remount Root and Kernel File Systems.
10934 10:02:38.140091 <3>[ 20.814533] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 10:02:38.146439 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10936 10:02:38.171605 <3>[ 20.846555] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10937 10:02:38.207619 <3>[ 20.881944] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10938 10:02:38.213960 <30>[ 20.884545] systemd[1]: Mounting FUSE Control File System...
10939 10:02:38.220264 Mounting [0;1;39mFUSE Control File System[0m...
10940 10:02:38.239830 <30>[ 20.915374] systemd[1]: Mounting Kernel Configuration File System...
10941 10:02:38.243259 Mounting [0;1;39mKernel Configuration File System[0m...
10942 10:02:38.269126 <30>[ 20.944184] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10943 10:02:38.279041 <30>[ 20.953414] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10944 10:02:38.308518 <30>[ 20.987192] systemd[1]: Starting Load/Save Random Seed...
10945 10:02:38.314919 Starting [0;1;39mLoad/Save Random Seed[0m...
10946 10:02:38.332092 <30>[ 21.011021] systemd[1]: Starting Apply Kernel Variables...
10947 10:02:38.339282 Starting [0;1;39mApply Kernel Variables[0m...
10948 10:02:38.358056 <4>[ 21.026622] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10949 10:02:38.367523 <3>[ 21.042411] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10950 10:02:38.391734 <30>[ 21.070815] systemd[1]: Starting Create System Users...
10951 10:02:38.398212 Starting [0;1;39mCreate System Users[0m...
10952 10:02:38.414367 <30>[ 21.093142] systemd[1]: Started Journal Service.
10953 10:02:38.421062 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10954 10:02:38.444985 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10955 10:02:38.459136 See 'systemctl status systemd-udev-trigger.service' for details.
10956 10:02:38.475705 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10957 10:02:38.491648 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10958 10:02:38.509007 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10959 10:02:38.529231 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10960 10:02:38.544966 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10961 10:02:38.592360 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10962 10:02:38.610759 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10963 10:02:38.649910 <46>[ 21.325972] systemd-journald[291]: Received client request to flush runtime journal.
10964 10:02:38.703782 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10965 10:02:38.716055 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10966 10:02:38.731274 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10967 10:02:38.795308 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10968 10:02:40.056386 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10969 10:02:40.135997 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10970 10:02:40.157804 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10971 10:02:40.185157 Starting [0;1;39mNetwork Service[0m...
10972 10:02:40.538999 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10973 10:02:40.561873 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10974 10:02:40.636095 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10975 10:02:40.883051 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10976 10:02:40.915503 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10977 10:02:40.934307 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10978 10:02:40.947037 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10979 10:02:40.983633 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10980 10:02:41.005160 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10981 10:02:41.020645 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10982 10:02:41.084014 Starting [0;1;39mNetwork Name Resolution[0m...
10983 10:02:41.111706 Starting [0;1;39mNetwork Time Synchronization[0m...
10984 10:02:41.132654 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10985 10:02:41.190558 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10986 10:02:41.297160 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10987 10:02:41.311458 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10988 10:02:41.330119 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10989 10:02:41.342906 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10990 10:02:41.359265 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10991 10:02:41.479227 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10992 10:02:41.540921 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10993 10:02:41.587877 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10994 10:02:42.130134 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10995 10:02:42.142960 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10996 10:02:42.309199 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10997 10:02:42.323258 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10998 10:02:42.338765 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10999 10:02:42.388272 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11000 10:02:42.710889 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11001 10:02:42.811740 Starting [0;1;39mUser Login Management[0m...
11002 10:02:42.832775 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11003 10:02:42.854211 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11004 10:02:42.874988 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11005 10:02:42.919909 Starting [0;1;39mPermit User Sessions[0m...
11006 10:02:43.053696 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11007 10:02:43.098485 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11008 10:02:43.135575 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11009 10:02:43.175676 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11010 10:02:43.191652 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11011 10:02:43.214101 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11012 10:02:43.220761 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11013 10:02:43.239341 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11014 10:02:43.291187 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11015 10:02:43.342080 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11016 10:02:43.414878
11017 10:02:43.415059
11018 10:02:43.418612 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11019 10:02:43.418726
11020 10:02:43.421510 debian-bullseye-arm64 login: root (automatic login)
11021 10:02:43.421632
11022 10:02:43.421730
11023 10:02:43.791200 Linux debian-bullseye-arm64 6.1.62-cip9 #1 SMP PREEMPT Fri Nov 24 09:44:51 UTC 2023 aarch64
11024 10:02:43.791721
11025 10:02:43.797476 The programs included with the Debian GNU/Linux system are free software;
11026 10:02:43.804022 the exact distribution terms for each program are described in the
11027 10:02:43.807354 individual files in /usr/share/doc/*/copyright.
11028 10:02:43.807439
11029 10:02:43.814014 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11030 10:02:43.817661 permitted by applicable law.
11031 10:02:44.684583 Matched prompt #10: / #
11033 10:02:44.685748 Setting prompt string to ['/ #']
11034 10:02:44.686250 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11036 10:02:44.687445 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11037 10:02:44.687947 start: 2.2.6 expect-shell-connection (timeout 00:03:36) [common]
11038 10:02:44.688347 Setting prompt string to ['/ #']
11039 10:02:44.688693 Forcing a shell prompt, looking for ['/ #']
11041 10:02:44.739220 / #
11042 10:02:44.739548 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11043 10:02:44.739751 Waiting using forced prompt support (timeout 00:02:30)
11044 10:02:44.745020
11045 10:02:44.745700 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11046 10:02:44.746042 start: 2.2.7 export-device-env (timeout 00:03:35) [common]
11048 10:02:44.847147 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12073307/extract-nfsrootfs-s5xwbqap'
11049 10:02:44.853815 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12073307/extract-nfsrootfs-s5xwbqap'
11051 10:02:44.955381 / # export NFS_SERVER_IP='192.168.201.1'
11052 10:02:44.961875 export NFS_SERVER_IP='192.168.201.1'
11053 10:02:44.962882 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11054 10:02:44.963444 end: 2.2 depthcharge-retry (duration 00:01:25) [common]
11055 10:02:44.963986 end: 2 depthcharge-action (duration 00:01:25) [common]
11056 10:02:44.964503 start: 3 lava-test-retry (timeout 00:07:43) [common]
11057 10:02:44.964996 start: 3.1 lava-test-shell (timeout 00:07:43) [common]
11058 10:02:44.965409 Using namespace: common
11060 10:02:45.066582 / # #
11061 10:02:45.067230 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11062 10:02:45.072826 #
11063 10:02:45.073711 Using /lava-12073307
11065 10:02:45.175003 / # export SHELL=/bin/bash
11066 10:02:45.181852 export SHELL=/bin/bash
11068 10:02:45.283573 / # . /lava-12073307/environment
11069 10:02:45.290162 . /lava-12073307/environment
11071 10:02:45.397497 / # /lava-12073307/bin/lava-test-runner /lava-12073307/0
11072 10:02:45.398145 Test shell timeout: 10s (minimum of the action and connection timeout)
11073 10:02:45.404013 /lava-12073307/bin/lava-test-runner /lava-12073307/0
11074 10:02:45.702310 + export TESTRUN_ID=0_timesync-off
11075 10:02:45.705479 + TESTRUN_ID=0_timesync-off
11076 10:02:45.708663 + cd /lava-12073307/0/tests/0_timesync-off
11077 10:02:45.712071 ++ cat uuid
11078 10:02:45.716973 + UUID=12073307_1.6.2.3.1
11079 10:02:45.717410 + set +x
11080 10:02:45.723472 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12073307_1.6.2.3.1>
11081 10:02:45.724195 Received signal: <STARTRUN> 0_timesync-off 12073307_1.6.2.3.1
11082 10:02:45.724607 Starting test lava.0_timesync-off (12073307_1.6.2.3.1)
11083 10:02:45.725030 Skipping test definition patterns.
11084 10:02:45.726908 + systemctl stop systemd-timesyncd
11085 10:02:45.794429 + set +x
11086 10:02:45.797716 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12073307_1.6.2.3.1>
11087 10:02:45.798493 Received signal: <ENDRUN> 0_timesync-off 12073307_1.6.2.3.1
11088 10:02:45.798986 Ending use of test pattern.
11089 10:02:45.799318 Ending test lava.0_timesync-off (12073307_1.6.2.3.1), duration 0.07
11091 10:02:45.878824 + export TESTRUN_ID=1_kselftest-dt
11092 10:02:45.882269 + TESTRUN_ID=1_kselftest-dt
11093 10:02:45.885208 + cd /lava-12073307/0/tests/1_kselftest-dt
11094 10:02:45.888569 ++ cat uuid
11095 10:02:45.893849 + UUID=12073307_1.6.2.3.5
11096 10:02:45.894351 + set +x
11097 10:02:45.900358 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 12073307_1.6.2.3.5>
11098 10:02:45.901045 Received signal: <STARTRUN> 1_kselftest-dt 12073307_1.6.2.3.5
11099 10:02:45.901431 Starting test lava.1_kselftest-dt (12073307_1.6.2.3.5)
11100 10:02:45.901861 Skipping test definition patterns.
11101 10:02:45.903876 + cd ./automated/linux/kselftest/
11102 10:02:45.930102 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11103 10:02:45.969803 INFO: install_deps skipped
11104 10:02:46.097867 --2023-11-24 10:02:11-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11105 10:02:46.134304 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11106 10:02:46.288840 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11107 10:02:46.439817 HTTP request sent, awaiting response... 200 OK
11108 10:02:46.442925 Length: 2964448 (2.8M) [application/octet-stream]
11109 10:02:46.446700 Saving to: 'kselftest.tar.xz'
11110 10:02:46.447268
11111 10:02:46.447647
11112 10:02:46.735564 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11113 10:02:47.035159 kselftest.tar.xz 1%[ ] 49.22K 167KB/s
11114 10:02:47.332502 kselftest.tar.xz 7%[> ] 206.18K 347KB/s
11115 10:02:47.619606 kselftest.tar.xz 19%[==> ] 562.53K 631KB/s
11116 10:02:47.889899 kselftest.tar.xz 35%[======> ] 1.00M 870KB/s
11117 10:02:48.165170 kselftest.tar.xz 70%[=============> ] 1.98M 1.37MB/s
11118 10:02:48.337132 kselftest.tar.xz 78%[==============> ] 2.22M 1.29MB/s
11119 10:02:48.343899 kselftest.tar.xz 100%[===================>] 2.83M 1.49MB/s in 1.9s
11120 10:02:48.344475
11121 10:02:48.600549 2023-11-24 10:02:13 (1.49 MB/s) - 'kselftest.tar.xz' saved [2964448/2964448]
11122 10:02:48.600720
11123 10:02:53.668057 skiplist:
11124 10:02:53.671092 ========================================
11125 10:02:53.674208 ========================================
11126 10:02:53.740309 ============== Tests to run ===============
11127 10:02:53.743497 ===========End Tests to run ===============
11128 10:02:53.747381 shardfile-dt fail
11129 10:02:53.771305 ./kselftest.sh: 131: cannot open /lava-12073307/0/tests/1_kselftest-dt/automated/linux/kselftest/output/kselftest.txt: No such file
11130 10:02:53.774485 + ../../utils/send-to-lava.sh ./output/result.txt
11131 10:02:53.853059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=fail>
11132 10:02:53.853570 + set +x
11133 10:02:53.854232 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=fail
11135 10:02:53.859423 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 12073307_1.6.2.3.5>
11136 10:02:53.860158 Received signal: <ENDRUN> 1_kselftest-dt 12073307_1.6.2.3.5
11137 10:02:53.860577 Ending use of test pattern.
11138 10:02:53.860939 Ending test lava.1_kselftest-dt (12073307_1.6.2.3.5), duration 7.96
11140 10:02:53.862147 ok: lava_test_shell seems to have completed
11141 10:02:53.862714 shardfile-dt: fail
11142 10:02:53.863165 end: 3.1 lava-test-shell (duration 00:00:09) [common]
11143 10:02:53.863629 end: 3 lava-test-retry (duration 00:00:09) [common]
11144 10:02:53.864113 start: 4 finalize (timeout 00:07:34) [common]
11145 10:02:53.864598 start: 4.1 power-off (timeout 00:00:30) [common]
11146 10:02:53.865346 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11147 10:02:53.984588 >> Command sent successfully.
11148 10:02:53.989006 Returned 0 in 0 seconds
11149 10:02:54.089982 end: 4.1 power-off (duration 00:00:00) [common]
11151 10:02:54.091714 start: 4.2 read-feedback (timeout 00:07:34) [common]
11153 10:02:54.093978 Listened to connection for namespace 'common' for up to 1s
11154 10:02:55.093711 Finalising connection for namespace 'common'
11155 10:02:55.094490 Disconnecting from shell: Finalise
11156 10:02:55.095003 / #
11157 10:02:55.196127 end: 4.2 read-feedback (duration 00:00:01) [common]
11158 10:02:55.196894 end: 4 finalize (duration 00:00:01) [common]
11159 10:02:55.197587 Cleaning after the job
11160 10:02:55.198174 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073307/tftp-deploy-qs3gwgws/ramdisk
11161 10:02:55.209150 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073307/tftp-deploy-qs3gwgws/kernel
11162 10:02:55.237161 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073307/tftp-deploy-qs3gwgws/dtb
11163 10:02:55.237498 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073307/tftp-deploy-qs3gwgws/nfsrootfs
11164 10:02:55.308807 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073307/tftp-deploy-qs3gwgws/modules
11165 10:02:55.314258 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12073307
11166 10:02:55.816128 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12073307
11167 10:02:55.816318 Job finished correctly