Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 37
- Kernel Warnings: 27
- Boot result: PASS
- Errors: 0
1 09:56:25.976291 lava-dispatcher, installed at version: 2023.10
2 09:56:25.976493 start: 0 validate
3 09:56:25.976627 Start time: 2023-11-24 09:56:25.976618+00:00 (UTC)
4 09:56:25.976740 Using caching service: 'http://localhost/cache/?uri=%s'
5 09:56:25.976868 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 09:56:26.236245 Using caching service: 'http://localhost/cache/?uri=%s'
7 09:56:26.236421 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 09:56:26.503354 Using caching service: 'http://localhost/cache/?uri=%s'
9 09:56:26.503544 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 09:57:26.827893 Using caching service: 'http://localhost/cache/?uri=%s'
11 09:57:26.828629 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 09:57:27.355627 Using caching service: 'http://localhost/cache/?uri=%s'
13 09:57:27.356334 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 09:57:27.622652 validate duration: 61.65
16 09:57:27.622972 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 09:57:27.623066 start: 1.1 download-retry (timeout 00:10:00) [common]
18 09:57:27.623148 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 09:57:27.623280 Not decompressing ramdisk as can be used compressed.
20 09:57:27.623362 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 09:57:27.623425 saving as /var/lib/lava/dispatcher/tmp/12073277/tftp-deploy-4j2yyqmd/ramdisk/initrd.cpio.gz
22 09:57:27.623490 total size: 4665395 (4 MB)
23 09:57:31.242973 progress 0 % (0 MB)
24 09:57:31.252221 progress 5 % (0 MB)
25 09:57:31.259473 progress 10 % (0 MB)
26 09:57:31.266726 progress 15 % (0 MB)
27 09:57:31.273970 progress 20 % (0 MB)
28 09:57:31.279522 progress 25 % (1 MB)
29 09:57:31.283552 progress 30 % (1 MB)
30 09:57:31.286930 progress 35 % (1 MB)
31 09:57:31.289854 progress 40 % (1 MB)
32 09:57:31.292756 progress 45 % (2 MB)
33 09:57:31.295112 progress 50 % (2 MB)
34 09:57:31.297290 progress 55 % (2 MB)
35 09:57:31.299311 progress 60 % (2 MB)
36 09:57:31.301311 progress 65 % (2 MB)
37 09:57:31.303076 progress 70 % (3 MB)
38 09:57:31.304852 progress 75 % (3 MB)
39 09:57:31.306582 progress 80 % (3 MB)
40 09:57:31.308376 progress 85 % (3 MB)
41 09:57:31.310014 progress 90 % (4 MB)
42 09:57:31.311558 progress 95 % (4 MB)
43 09:57:31.313093 progress 100 % (4 MB)
44 09:57:31.313274 4 MB downloaded in 3.69 s (1.21 MB/s)
45 09:57:31.313459 end: 1.1.1 http-download (duration 00:00:04) [common]
47 09:57:31.313729 end: 1.1 download-retry (duration 00:00:04) [common]
48 09:57:31.313833 start: 1.2 download-retry (timeout 00:09:56) [common]
49 09:57:31.313932 start: 1.2.1 http-download (timeout 00:09:56) [common]
50 09:57:31.314089 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 09:57:31.314169 saving as /var/lib/lava/dispatcher/tmp/12073277/tftp-deploy-4j2yyqmd/kernel/Image
52 09:57:31.314240 total size: 49107456 (46 MB)
53 09:57:31.314309 No compression specified
54 09:57:31.315560 progress 0 % (0 MB)
55 09:57:31.328432 progress 5 % (2 MB)
56 09:57:31.340897 progress 10 % (4 MB)
57 09:57:31.360340 progress 15 % (7 MB)
58 09:57:31.381248 progress 20 % (9 MB)
59 09:57:31.396758 progress 25 % (11 MB)
60 09:57:31.409793 progress 30 % (14 MB)
61 09:57:31.423369 progress 35 % (16 MB)
62 09:57:31.436199 progress 40 % (18 MB)
63 09:57:31.449084 progress 45 % (21 MB)
64 09:57:31.462190 progress 50 % (23 MB)
65 09:57:31.475167 progress 55 % (25 MB)
66 09:57:31.488033 progress 60 % (28 MB)
67 09:57:31.500949 progress 65 % (30 MB)
68 09:57:31.514030 progress 70 % (32 MB)
69 09:57:31.526962 progress 75 % (35 MB)
70 09:57:31.539957 progress 80 % (37 MB)
71 09:57:31.553679 progress 85 % (39 MB)
72 09:57:31.566943 progress 90 % (42 MB)
73 09:57:31.581051 progress 95 % (44 MB)
74 09:57:31.593864 progress 100 % (46 MB)
75 09:57:31.594117 46 MB downloaded in 0.28 s (167.34 MB/s)
76 09:57:31.594277 end: 1.2.1 http-download (duration 00:00:00) [common]
78 09:57:31.594512 end: 1.2 download-retry (duration 00:00:00) [common]
79 09:57:31.594601 start: 1.3 download-retry (timeout 00:09:56) [common]
80 09:57:31.594687 start: 1.3.1 http-download (timeout 00:09:56) [common]
81 09:57:31.594830 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 09:57:31.594909 saving as /var/lib/lava/dispatcher/tmp/12073277/tftp-deploy-4j2yyqmd/dtb/mt8192-asurada-spherion-r0.dtb
83 09:57:31.594973 total size: 47278 (0 MB)
84 09:57:31.595035 No compression specified
85 09:57:31.596196 progress 69 % (0 MB)
86 09:57:31.596479 progress 100 % (0 MB)
87 09:57:31.596646 0 MB downloaded in 0.00 s (26.97 MB/s)
88 09:57:31.596772 end: 1.3.1 http-download (duration 00:00:00) [common]
90 09:57:31.596998 end: 1.3 download-retry (duration 00:00:00) [common]
91 09:57:31.597085 start: 1.4 download-retry (timeout 00:09:56) [common]
92 09:57:31.597171 start: 1.4.1 http-download (timeout 00:09:56) [common]
93 09:57:31.597292 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 09:57:31.597361 saving as /var/lib/lava/dispatcher/tmp/12073277/tftp-deploy-4j2yyqmd/nfsrootfs/full.rootfs.tar
95 09:57:31.597424 total size: 200813988 (191 MB)
96 09:57:31.597487 Using unxz to decompress xz
97 09:57:31.601691 progress 0 % (0 MB)
98 09:57:32.147374 progress 5 % (9 MB)
99 09:57:32.696304 progress 10 % (19 MB)
100 09:57:33.306626 progress 15 % (28 MB)
101 09:57:33.694410 progress 20 % (38 MB)
102 09:57:34.033472 progress 25 % (47 MB)
103 09:57:34.662273 progress 30 % (57 MB)
104 09:57:35.226854 progress 35 % (67 MB)
105 09:57:35.840396 progress 40 % (76 MB)
106 09:57:36.436063 progress 45 % (86 MB)
107 09:57:37.061404 progress 50 % (95 MB)
108 09:57:37.723979 progress 55 % (105 MB)
109 09:57:38.423212 progress 60 % (114 MB)
110 09:57:38.557459 progress 65 % (124 MB)
111 09:57:38.719180 progress 70 % (134 MB)
112 09:57:38.827202 progress 75 % (143 MB)
113 09:57:38.917152 progress 80 % (153 MB)
114 09:57:38.999958 progress 85 % (162 MB)
115 09:57:39.118956 progress 90 % (172 MB)
116 09:57:39.424192 progress 95 % (181 MB)
117 09:57:40.023679 progress 100 % (191 MB)
118 09:57:40.029117 191 MB downloaded in 8.43 s (22.71 MB/s)
119 09:57:40.029424 end: 1.4.1 http-download (duration 00:00:08) [common]
121 09:57:40.029698 end: 1.4 download-retry (duration 00:00:08) [common]
122 09:57:40.029790 start: 1.5 download-retry (timeout 00:09:48) [common]
123 09:57:40.029880 start: 1.5.1 http-download (timeout 00:09:48) [common]
124 09:57:40.030040 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 09:57:40.030113 saving as /var/lib/lava/dispatcher/tmp/12073277/tftp-deploy-4j2yyqmd/modules/modules.tar
126 09:57:40.030176 total size: 8622040 (8 MB)
127 09:57:40.030241 Using unxz to decompress xz
128 09:57:40.303269 progress 0 % (0 MB)
129 09:57:40.324446 progress 5 % (0 MB)
130 09:57:40.350638 progress 10 % (0 MB)
131 09:57:40.375985 progress 15 % (1 MB)
132 09:57:40.402040 progress 20 % (1 MB)
133 09:57:40.428268 progress 25 % (2 MB)
134 09:57:40.456719 progress 30 % (2 MB)
135 09:57:40.485027 progress 35 % (2 MB)
136 09:57:40.510505 progress 40 % (3 MB)
137 09:57:40.537038 progress 45 % (3 MB)
138 09:57:40.564660 progress 50 % (4 MB)
139 09:57:40.589917 progress 55 % (4 MB)
140 09:57:40.616064 progress 60 % (4 MB)
141 09:57:40.644934 progress 65 % (5 MB)
142 09:57:40.670740 progress 70 % (5 MB)
143 09:57:40.695009 progress 75 % (6 MB)
144 09:57:40.722625 progress 80 % (6 MB)
145 09:57:40.749561 progress 85 % (7 MB)
146 09:57:40.775254 progress 90 % (7 MB)
147 09:57:40.805533 progress 95 % (7 MB)
148 09:57:40.836657 progress 100 % (8 MB)
149 09:57:40.841658 8 MB downloaded in 0.81 s (10.13 MB/s)
150 09:57:40.841952 end: 1.5.1 http-download (duration 00:00:01) [common]
152 09:57:40.842224 end: 1.5 download-retry (duration 00:00:01) [common]
153 09:57:40.842340 start: 1.6 prepare-tftp-overlay (timeout 00:09:47) [common]
154 09:57:40.842466 start: 1.6.1 extract-nfsrootfs (timeout 00:09:47) [common]
155 09:57:44.389978 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12073277/extract-nfsrootfs-vxspfp2o
156 09:57:44.390198 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 09:57:44.390330 start: 1.6.2 lava-overlay (timeout 00:09:43) [common]
158 09:57:44.390546 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho
159 09:57:44.390682 makedir: /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho/lava-12073277/bin
160 09:57:44.390788 makedir: /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho/lava-12073277/tests
161 09:57:44.390902 makedir: /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho/lava-12073277/results
162 09:57:44.391009 Creating /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho/lava-12073277/bin/lava-add-keys
163 09:57:44.391164 Creating /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho/lava-12073277/bin/lava-add-sources
164 09:57:44.391315 Creating /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho/lava-12073277/bin/lava-background-process-start
165 09:57:44.391445 Creating /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho/lava-12073277/bin/lava-background-process-stop
166 09:57:44.391573 Creating /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho/lava-12073277/bin/lava-common-functions
167 09:57:44.391700 Creating /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho/lava-12073277/bin/lava-echo-ipv4
168 09:57:44.391827 Creating /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho/lava-12073277/bin/lava-install-packages
169 09:57:44.391953 Creating /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho/lava-12073277/bin/lava-installed-packages
170 09:57:44.392079 Creating /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho/lava-12073277/bin/lava-os-build
171 09:57:44.392205 Creating /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho/lava-12073277/bin/lava-probe-channel
172 09:57:44.392331 Creating /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho/lava-12073277/bin/lava-probe-ip
173 09:57:44.392456 Creating /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho/lava-12073277/bin/lava-target-ip
174 09:57:44.392580 Creating /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho/lava-12073277/bin/lava-target-mac
175 09:57:44.392706 Creating /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho/lava-12073277/bin/lava-target-storage
176 09:57:44.392833 Creating /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho/lava-12073277/bin/lava-test-case
177 09:57:44.392961 Creating /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho/lava-12073277/bin/lava-test-event
178 09:57:44.393085 Creating /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho/lava-12073277/bin/lava-test-feedback
179 09:57:44.393210 Creating /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho/lava-12073277/bin/lava-test-raise
180 09:57:44.393334 Creating /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho/lava-12073277/bin/lava-test-reference
181 09:57:44.393460 Creating /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho/lava-12073277/bin/lava-test-runner
182 09:57:44.393585 Creating /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho/lava-12073277/bin/lava-test-set
183 09:57:44.393712 Creating /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho/lava-12073277/bin/lava-test-shell
184 09:57:44.393839 Updating /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho/lava-12073277/bin/lava-add-keys (debian)
185 09:57:44.393996 Updating /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho/lava-12073277/bin/lava-add-sources (debian)
186 09:57:44.394143 Updating /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho/lava-12073277/bin/lava-install-packages (debian)
187 09:57:44.394283 Updating /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho/lava-12073277/bin/lava-installed-packages (debian)
188 09:57:44.394422 Updating /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho/lava-12073277/bin/lava-os-build (debian)
189 09:57:44.394545 Creating /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho/lava-12073277/environment
190 09:57:44.394641 LAVA metadata
191 09:57:44.394712 - LAVA_JOB_ID=12073277
192 09:57:44.394776 - LAVA_DISPATCHER_IP=192.168.201.1
193 09:57:44.395056 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:43) [common]
194 09:57:44.395127 skipped lava-vland-overlay
195 09:57:44.395205 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 09:57:44.395302 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:43) [common]
197 09:57:44.395363 skipped lava-multinode-overlay
198 09:57:44.395435 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 09:57:44.395513 start: 1.6.2.3 test-definition (timeout 00:09:43) [common]
200 09:57:44.395590 Loading test definitions
201 09:57:44.395677 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:43) [common]
202 09:57:44.395748 Using /lava-12073277 at stage 0
203 09:57:44.396044 uuid=12073277_1.6.2.3.1 testdef=None
204 09:57:44.396133 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 09:57:44.396215 start: 1.6.2.3.2 test-overlay (timeout 00:09:43) [common]
206 09:57:44.396674 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 09:57:44.396895 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:43) [common]
209 09:57:44.397451 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 09:57:44.397681 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:43) [common]
212 09:57:44.398223 runner path: /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho/lava-12073277/0/tests/0_timesync-off test_uuid 12073277_1.6.2.3.1
213 09:57:44.398380 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 09:57:44.398603 start: 1.6.2.3.5 git-repo-action (timeout 00:09:43) [common]
216 09:57:44.398677 Using /lava-12073277 at stage 0
217 09:57:44.398775 Fetching tests from https://github.com/kernelci/test-definitions.git
218 09:57:44.398854 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho/lava-12073277/0/tests/1_kselftest-tpm2'
219 09:57:56.200654 Running '/usr/bin/git checkout kernelci.org
220 09:57:56.357085 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 09:57:56.357869 uuid=12073277_1.6.2.3.5 testdef=None
222 09:57:56.358044 end: 1.6.2.3.5 git-repo-action (duration 00:00:12) [common]
224 09:57:56.358304 start: 1.6.2.3.6 test-overlay (timeout 00:09:31) [common]
225 09:57:56.359099 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 09:57:56.359436 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:31) [common]
228 09:57:56.360454 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 09:57:56.360691 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:31) [common]
231 09:57:56.361758 runner path: /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho/lava-12073277/0/tests/1_kselftest-tpm2 test_uuid 12073277_1.6.2.3.5
232 09:57:56.361855 BOARD='mt8192-asurada-spherion-r0'
233 09:57:56.361920 BRANCH='cip'
234 09:57:56.361979 SKIPFILE='/dev/null'
235 09:57:56.362041 SKIP_INSTALL='True'
236 09:57:56.362104 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 09:57:56.362162 TST_CASENAME=''
238 09:57:56.362217 TST_CMDFILES='tpm2'
239 09:57:56.362362 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 09:57:56.362567 Creating lava-test-runner.conf files
242 09:57:56.362630 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12073277/lava-overlay-2of8qjho/lava-12073277/0 for stage 0
243 09:57:56.362726 - 0_timesync-off
244 09:57:56.362797 - 1_kselftest-tpm2
245 09:57:56.362917 end: 1.6.2.3 test-definition (duration 00:00:12) [common]
246 09:57:56.363017 start: 1.6.2.4 compress-overlay (timeout 00:09:31) [common]
247 09:58:04.052700 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 09:58:04.052895 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:24) [common]
249 09:58:04.052991 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 09:58:04.053095 end: 1.6.2 lava-overlay (duration 00:00:20) [common]
251 09:58:04.053189 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:24) [common]
252 09:58:04.177255 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 09:58:04.177676 start: 1.6.4 extract-modules (timeout 00:09:23) [common]
254 09:58:04.177831 extracting modules file /var/lib/lava/dispatcher/tmp/12073277/tftp-deploy-4j2yyqmd/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12073277/extract-nfsrootfs-vxspfp2o
255 09:58:04.415604 extracting modules file /var/lib/lava/dispatcher/tmp/12073277/tftp-deploy-4j2yyqmd/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12073277/extract-overlay-ramdisk-o8qvk7gi/ramdisk
256 09:58:04.652280 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 09:58:04.652463 start: 1.6.5 apply-overlay-tftp (timeout 00:09:23) [common]
258 09:58:04.652562 [common] Applying overlay to NFS
259 09:58:04.652637 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12073277/compress-overlay-pe6ku5pw/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12073277/extract-nfsrootfs-vxspfp2o
260 09:58:05.602105 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 09:58:05.602304 start: 1.6.6 configure-preseed-file (timeout 00:09:22) [common]
262 09:58:05.602413 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 09:58:05.602507 start: 1.6.7 compress-ramdisk (timeout 00:09:22) [common]
264 09:58:05.602590 Building ramdisk /var/lib/lava/dispatcher/tmp/12073277/extract-overlay-ramdisk-o8qvk7gi/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12073277/extract-overlay-ramdisk-o8qvk7gi/ramdisk
265 09:58:05.914872 >> 119398 blocks
266 09:58:07.881957 rename /var/lib/lava/dispatcher/tmp/12073277/extract-overlay-ramdisk-o8qvk7gi/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12073277/tftp-deploy-4j2yyqmd/ramdisk/ramdisk.cpio.gz
267 09:58:07.882400 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 09:58:07.882530 start: 1.6.8 prepare-kernel (timeout 00:09:20) [common]
269 09:58:07.882632 start: 1.6.8.1 prepare-fit (timeout 00:09:20) [common]
270 09:58:07.882740 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12073277/tftp-deploy-4j2yyqmd/kernel/Image'
271 09:58:21.600180 Returned 0 in 13 seconds
272 09:58:21.700801 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12073277/tftp-deploy-4j2yyqmd/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12073277/tftp-deploy-4j2yyqmd/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12073277/tftp-deploy-4j2yyqmd/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12073277/tftp-deploy-4j2yyqmd/kernel/image.itb
273 09:58:22.050644 output: FIT description: Kernel Image image with one or more FDT blobs
274 09:58:22.051133 output: Created: Fri Nov 24 09:58:21 2023
275 09:58:22.051261 output: Image 0 (kernel-1)
276 09:58:22.051359 output: Description:
277 09:58:22.051456 output: Created: Fri Nov 24 09:58:21 2023
278 09:58:22.051552 output: Type: Kernel Image
279 09:58:22.051649 output: Compression: lzma compressed
280 09:58:22.051743 output: Data Size: 11047542 Bytes = 10788.62 KiB = 10.54 MiB
281 09:58:22.051840 output: Architecture: AArch64
282 09:58:22.051938 output: OS: Linux
283 09:58:22.052032 output: Load Address: 0x00000000
284 09:58:22.052129 output: Entry Point: 0x00000000
285 09:58:22.052227 output: Hash algo: crc32
286 09:58:22.052325 output: Hash value: 2edffaa3
287 09:58:22.052423 output: Image 1 (fdt-1)
288 09:58:22.052513 output: Description: mt8192-asurada-spherion-r0
289 09:58:22.052606 output: Created: Fri Nov 24 09:58:21 2023
290 09:58:22.052697 output: Type: Flat Device Tree
291 09:58:22.052788 output: Compression: uncompressed
292 09:58:22.052878 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 09:58:22.052969 output: Architecture: AArch64
294 09:58:22.053060 output: Hash algo: crc32
295 09:58:22.053150 output: Hash value: cc4352de
296 09:58:22.053240 output: Image 2 (ramdisk-1)
297 09:58:22.053329 output: Description: unavailable
298 09:58:22.053419 output: Created: Fri Nov 24 09:58:21 2023
299 09:58:22.053509 output: Type: RAMDisk Image
300 09:58:22.053598 output: Compression: Unknown Compression
301 09:58:22.053689 output: Data Size: 17793271 Bytes = 17376.24 KiB = 16.97 MiB
302 09:58:22.053780 output: Architecture: AArch64
303 09:58:22.053870 output: OS: Linux
304 09:58:22.053959 output: Load Address: unavailable
305 09:58:22.054048 output: Entry Point: unavailable
306 09:58:22.054138 output: Hash algo: crc32
307 09:58:22.054228 output: Hash value: 9ebd0ef8
308 09:58:22.054318 output: Default Configuration: 'conf-1'
309 09:58:22.054407 output: Configuration 0 (conf-1)
310 09:58:22.054499 output: Description: mt8192-asurada-spherion-r0
311 09:58:22.054590 output: Kernel: kernel-1
312 09:58:22.054681 output: Init Ramdisk: ramdisk-1
313 09:58:22.054770 output: FDT: fdt-1
314 09:58:22.054870 output: Loadables: kernel-1
315 09:58:22.054960 output:
316 09:58:22.055249 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 09:58:22.055396 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 09:58:22.055556 end: 1.6 prepare-tftp-overlay (duration 00:00:41) [common]
319 09:58:22.055709 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:06) [common]
320 09:58:22.055835 No LXC device requested
321 09:58:22.055960 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 09:58:22.056095 start: 1.8 deploy-device-env (timeout 00:09:06) [common]
323 09:58:22.056217 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 09:58:22.056326 Checking files for TFTP limit of 4294967296 bytes.
325 09:58:22.057068 end: 1 tftp-deploy (duration 00:00:54) [common]
326 09:58:22.057215 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 09:58:22.057347 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 09:58:22.057532 substitutions:
329 09:58:22.057639 - {DTB}: 12073277/tftp-deploy-4j2yyqmd/dtb/mt8192-asurada-spherion-r0.dtb
330 09:58:22.057740 - {INITRD}: 12073277/tftp-deploy-4j2yyqmd/ramdisk/ramdisk.cpio.gz
331 09:58:22.057836 - {KERNEL}: 12073277/tftp-deploy-4j2yyqmd/kernel/Image
332 09:58:22.057929 - {LAVA_MAC}: None
333 09:58:22.058022 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12073277/extract-nfsrootfs-vxspfp2o
334 09:58:22.058114 - {NFS_SERVER_IP}: 192.168.201.1
335 09:58:22.058205 - {PRESEED_CONFIG}: None
336 09:58:22.058295 - {PRESEED_LOCAL}: None
337 09:58:22.058386 - {RAMDISK}: 12073277/tftp-deploy-4j2yyqmd/ramdisk/ramdisk.cpio.gz
338 09:58:22.058477 - {ROOT_PART}: None
339 09:58:22.058567 - {ROOT}: None
340 09:58:22.058657 - {SERVER_IP}: 192.168.201.1
341 09:58:22.058747 - {TEE}: None
342 09:58:22.058838 Parsed boot commands:
343 09:58:22.058935 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 09:58:22.059213 Parsed boot commands: tftpboot 192.168.201.1 12073277/tftp-deploy-4j2yyqmd/kernel/image.itb 12073277/tftp-deploy-4j2yyqmd/kernel/cmdline
345 09:58:22.059352 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 09:58:22.059485 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 09:58:22.059627 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 09:58:22.059760 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 09:58:22.059875 Not connected, no need to disconnect.
350 09:58:22.059993 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 09:58:22.060121 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 09:58:22.060230 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
353 09:58:22.065424 Setting prompt string to ['lava-test: # ']
354 09:58:22.065988 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 09:58:22.066165 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 09:58:22.066328 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 09:58:22.066472 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 09:58:22.066780 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
359 09:58:27.201850 >> Command sent successfully.
360 09:58:27.204458 Returned 0 in 5 seconds
361 09:58:27.304871 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 09:58:27.305215 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 09:58:27.305323 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 09:58:27.305415 Setting prompt string to 'Starting depthcharge on Spherion...'
366 09:58:27.305485 Changing prompt to 'Starting depthcharge on Spherion...'
367 09:58:27.305554 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 09:58:27.305834 [Enter `^Ec?' for help]
369 09:58:27.479581
370 09:58:27.479769
371 09:58:27.479896 F0: 102B 0000
372 09:58:27.479996
373 09:58:27.480089 F3: 1001 0000 [0200]
374 09:58:27.482939
375 09:58:27.483035 F3: 1001 0000
376 09:58:27.483106
377 09:58:27.483171 F7: 102D 0000
378 09:58:27.483233
379 09:58:27.485976 F1: 0000 0000
380 09:58:27.486053
381 09:58:27.486117 V0: 0000 0000 [0001]
382 09:58:27.486179
383 09:58:27.489669 00: 0007 8000
384 09:58:27.489804
385 09:58:27.489913 01: 0000 0000
386 09:58:27.490019
387 09:58:27.492817 BP: 0C00 0209 [0000]
388 09:58:27.492926
389 09:58:27.493030 G0: 1182 0000
390 09:58:27.493136
391 09:58:27.496488 EC: 0000 0021 [4000]
392 09:58:27.496580
393 09:58:27.496649 S7: 0000 0000 [0000]
394 09:58:27.496712
395 09:58:27.500089 CC: 0000 0000 [0001]
396 09:58:27.500276
397 09:58:27.500415 T0: 0000 0040 [010F]
398 09:58:27.500541
399 09:58:27.500607 Jump to BL
400 09:58:27.500668
401 09:58:27.526836
402 09:58:27.526997
403 09:58:27.527080
404 09:58:27.533795 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 09:58:27.537451 ARM64: Exception handlers installed.
406 09:58:27.540867 ARM64: Testing exception
407 09:58:27.544421 ARM64: Done test exception
408 09:58:27.551102 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 09:58:27.561894 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 09:58:27.568684 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 09:58:27.578787 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 09:58:27.585052 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 09:58:27.591913 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 09:58:27.603353 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 09:58:27.610764 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 09:58:27.629658 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 09:58:27.632675 WDT: Last reset was cold boot
418 09:58:27.636375 SPI1(PAD0) initialized at 2873684 Hz
419 09:58:27.639551 SPI5(PAD0) initialized at 992727 Hz
420 09:58:27.642611 VBOOT: Loading verstage.
421 09:58:27.649704 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 09:58:27.653454 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 09:58:27.656271 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 09:58:27.659289 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 09:58:27.667206 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 09:58:27.673362 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 09:58:27.684892 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
428 09:58:27.684987
429 09:58:27.685056
430 09:58:27.694644 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 09:58:27.698193 ARM64: Exception handlers installed.
432 09:58:27.701116 ARM64: Testing exception
433 09:58:27.701197 ARM64: Done test exception
434 09:58:27.707803 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 09:58:27.711389 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 09:58:27.726799 Probing TPM: . done!
437 09:58:27.726913 TPM ready after 0 ms
438 09:58:27.733588 Connected to device vid:did:rid of 1ae0:0028:00
439 09:58:27.740183 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 09:58:27.797276 Initialized TPM device CR50 revision 0
441 09:58:27.808919 tlcl_send_startup: Startup return code is 0
442 09:58:27.809065 TPM: setup succeeded
443 09:58:27.820669 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 09:58:27.829412 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 09:58:27.841139 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 09:58:27.851259 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 09:58:27.855021 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 09:58:27.860526 in-header: 03 07 00 00 08 00 00 00
449 09:58:27.863483 in-data: aa e4 47 04 13 02 00 00
450 09:58:27.867365 Chrome EC: UHEPI supported
451 09:58:27.874596 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 09:58:27.878446 in-header: 03 ad 00 00 08 00 00 00
453 09:58:27.882277 in-data: 00 20 20 08 00 00 00 00
454 09:58:27.882379 Phase 1
455 09:58:27.885454 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 09:58:27.892923 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 09:58:27.896688 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 09:58:27.900398 Recovery requested (1009000e)
459 09:58:27.909299 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 09:58:27.914304 tlcl_extend: response is 0
461 09:58:27.923958 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 09:58:27.929840 tlcl_extend: response is 0
463 09:58:27.936520 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 09:58:27.956181 read SPI 0x210d4 0x2173b: 15147 us, 9045 KB/s, 72.360 Mbps
465 09:58:27.962993 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 09:58:27.963090
467 09:58:27.963159
468 09:58:27.973936 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 09:58:27.977537 ARM64: Exception handlers installed.
470 09:58:27.977621 ARM64: Testing exception
471 09:58:27.980589 ARM64: Done test exception
472 09:58:28.001528 pmic_efuse_setting: Set efuses in 11 msecs
473 09:58:28.005661 pmwrap_interface_init: Select PMIF_VLD_RDY
474 09:58:28.012365 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 09:58:28.015527 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 09:58:28.019047 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 09:58:28.026421 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 09:58:28.029984 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 09:58:28.033999 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 09:58:28.041634 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 09:58:28.045285 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 09:58:28.049213 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 09:58:28.052882 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 09:58:28.060294 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 09:58:28.064113 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 09:58:28.067861 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 09:58:28.075040 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 09:58:28.079126 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 09:58:28.086595 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 09:58:28.090335 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 09:58:28.097731 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 09:58:28.101506 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 09:58:28.109005 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 09:58:28.112697 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 09:58:28.119954 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 09:58:28.123560 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 09:58:28.131148 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 09:58:28.134991 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 09:58:28.142065 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 09:58:28.145639 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 09:58:28.149525 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 09:58:28.156867 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 09:58:28.161190 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 09:58:28.164295 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 09:58:28.171867 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 09:58:28.175630 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 09:58:28.179200 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 09:58:28.186569 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 09:58:28.189880 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 09:58:28.197522 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 09:58:28.201180 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 09:58:28.204965 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 09:58:28.208646 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 09:58:28.212361 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 09:58:28.219768 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 09:58:28.222958 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 09:58:28.227148 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 09:58:28.230985 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 09:58:28.234602 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 09:58:28.238207 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 09:58:28.245544 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 09:58:28.249339 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 09:58:28.253182 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 09:58:28.256565 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 09:58:28.264575 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 09:58:28.271865 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 09:58:28.278784 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 09:58:28.286187 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 09:58:28.293489 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 09:58:28.297664 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 09:58:28.304488 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 09:58:28.308682 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 09:58:28.315485 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x26
534 09:58:28.319305 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 09:58:28.327157 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 09:58:28.330165 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 09:58:28.340067 [RTC]rtc_get_frequency_meter,154: input=15, output=791
538 09:58:28.349302 [RTC]rtc_get_frequency_meter,154: input=23, output=979
539 09:58:28.357982 [RTC]rtc_get_frequency_meter,154: input=19, output=884
540 09:58:28.367493 [RTC]rtc_get_frequency_meter,154: input=17, output=836
541 09:58:28.377783 [RTC]rtc_get_frequency_meter,154: input=16, output=813
542 09:58:28.387530 [RTC]rtc_get_frequency_meter,154: input=15, output=790
543 09:58:28.397546 [RTC]rtc_get_frequency_meter,154: input=16, output=812
544 09:58:28.400575 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
545 09:58:28.404339 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
546 09:58:28.408391 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 09:58:28.415291 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 09:58:28.419167 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 09:58:28.422825 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 09:58:28.425867 ADC[4]: Raw value=901328 ID=7
551 09:58:28.430220 ADC[3]: Raw value=213336 ID=1
552 09:58:28.430310 RAM Code: 0x71
553 09:58:28.433873 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 09:58:28.437575 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 09:58:28.448679 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 09:58:28.452468 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 09:58:28.456333 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 09:58:28.459854 in-header: 03 07 00 00 08 00 00 00
559 09:58:28.463627 in-data: aa e4 47 04 13 02 00 00
560 09:58:28.467686 Chrome EC: UHEPI supported
561 09:58:28.474653 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 09:58:28.478169 in-header: 03 ed 00 00 08 00 00 00
563 09:58:28.478253 in-data: 80 20 60 08 00 00 00 00
564 09:58:28.481806 MRC: failed to locate region type 0.
565 09:58:28.489444 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 09:58:28.492824 DRAM-K: Running full calibration
567 09:58:28.500417 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 09:58:28.500505 header.status = 0x0
569 09:58:28.504290 header.version = 0x6 (expected: 0x6)
570 09:58:28.507972 header.size = 0xd00 (expected: 0xd00)
571 09:58:28.508079 header.flags = 0x0
572 09:58:28.515231 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 09:58:28.534405 read SPI 0x72590 0x1c583: 12504 us, 9284 KB/s, 74.272 Mbps
574 09:58:28.541680 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 09:58:28.541769 dram_init: ddr_geometry: 2
576 09:58:28.545410 [EMI] MDL number = 2
577 09:58:28.545491 [EMI] Get MDL freq = 0
578 09:58:28.549746 dram_init: ddr_type: 0
579 09:58:28.549854 is_discrete_lpddr4: 1
580 09:58:28.553406 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 09:58:28.553502
582 09:58:28.553570
583 09:58:28.557037 [Bian_co] ETT version 0.0.0.1
584 09:58:28.561338 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 09:58:28.561426
586 09:58:28.564568 dramc_set_vcore_voltage set vcore to 650000
587 09:58:28.568256 Read voltage for 800, 4
588 09:58:28.568342 Vio18 = 0
589 09:58:28.571867 Vcore = 650000
590 09:58:28.571953 Vdram = 0
591 09:58:28.572021 Vddq = 0
592 09:58:28.572084 Vmddr = 0
593 09:58:28.575303 dram_init: config_dvfs: 1
594 09:58:28.579310 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 09:58:28.587103 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 09:58:28.590213 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
597 09:58:28.593908 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
598 09:58:28.596921 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
599 09:58:28.600364 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
600 09:58:28.603372 MEM_TYPE=3, freq_sel=18
601 09:58:28.607068 sv_algorithm_assistance_LP4_1600
602 09:58:28.610295 ============ PULL DRAM RESETB DOWN ============
603 09:58:28.614036 ========== PULL DRAM RESETB DOWN end =========
604 09:58:28.620264 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 09:58:28.623849 ===================================
606 09:58:28.623935 LPDDR4 DRAM CONFIGURATION
607 09:58:28.626850 ===================================
608 09:58:28.630655 EX_ROW_EN[0] = 0x0
609 09:58:28.633574 EX_ROW_EN[1] = 0x0
610 09:58:28.633660 LP4Y_EN = 0x0
611 09:58:28.637151 WORK_FSP = 0x0
612 09:58:28.637238 WL = 0x2
613 09:58:28.640368 RL = 0x2
614 09:58:28.640448 BL = 0x2
615 09:58:28.644013 RPST = 0x0
616 09:58:28.644126 RD_PRE = 0x0
617 09:58:28.647597 WR_PRE = 0x1
618 09:58:28.647677 WR_PST = 0x0
619 09:58:28.650782 DBI_WR = 0x0
620 09:58:28.650892 DBI_RD = 0x0
621 09:58:28.653836 OTF = 0x1
622 09:58:28.657610 ===================================
623 09:58:28.661176 ===================================
624 09:58:28.661257 ANA top config
625 09:58:28.664348 ===================================
626 09:58:28.667344 DLL_ASYNC_EN = 0
627 09:58:28.671021 ALL_SLAVE_EN = 1
628 09:58:28.671111 NEW_RANK_MODE = 1
629 09:58:28.674079 DLL_IDLE_MODE = 1
630 09:58:28.677726 LP45_APHY_COMB_EN = 1
631 09:58:28.680865 TX_ODT_DIS = 1
632 09:58:28.680943 NEW_8X_MODE = 1
633 09:58:28.684215 ===================================
634 09:58:28.687660 ===================================
635 09:58:28.691110 data_rate = 1600
636 09:58:28.694225 CKR = 1
637 09:58:28.697785 DQ_P2S_RATIO = 8
638 09:58:28.701214 ===================================
639 09:58:28.704307 CA_P2S_RATIO = 8
640 09:58:28.708023 DQ_CA_OPEN = 0
641 09:58:28.708111 DQ_SEMI_OPEN = 0
642 09:58:28.711104 CA_SEMI_OPEN = 0
643 09:58:28.714080 CA_FULL_RATE = 0
644 09:58:28.717870 DQ_CKDIV4_EN = 1
645 09:58:28.721166 CA_CKDIV4_EN = 1
646 09:58:28.721252 CA_PREDIV_EN = 0
647 09:58:28.724118 PH8_DLY = 0
648 09:58:28.727834 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 09:58:28.730967 DQ_AAMCK_DIV = 4
650 09:58:28.734548 CA_AAMCK_DIV = 4
651 09:58:28.737970 CA_ADMCK_DIV = 4
652 09:58:28.738056 DQ_TRACK_CA_EN = 0
653 09:58:28.741339 CA_PICK = 800
654 09:58:28.744254 CA_MCKIO = 800
655 09:58:28.747900 MCKIO_SEMI = 0
656 09:58:28.751608 PLL_FREQ = 3068
657 09:58:28.755394 DQ_UI_PI_RATIO = 32
658 09:58:28.755481 CA_UI_PI_RATIO = 0
659 09:58:28.758982 ===================================
660 09:58:28.762729 ===================================
661 09:58:28.766445 memory_type:LPDDR4
662 09:58:28.766533 GP_NUM : 10
663 09:58:28.770194 SRAM_EN : 1
664 09:58:28.770282 MD32_EN : 0
665 09:58:28.773957 ===================================
666 09:58:28.778386 [ANA_INIT] >>>>>>>>>>>>>>
667 09:58:28.781959 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 09:58:28.785592 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 09:58:28.785687 ===================================
670 09:58:28.788647 data_rate = 1600,PCW = 0X7600
671 09:58:28.792077 ===================================
672 09:58:28.795665 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 09:58:28.801876 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 09:58:28.808689 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 09:58:28.812065 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 09:58:28.815890 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 09:58:28.818910 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 09:58:28.822016 [ANA_INIT] flow start
679 09:58:28.822104 [ANA_INIT] PLL >>>>>>>>
680 09:58:28.825685 [ANA_INIT] PLL <<<<<<<<
681 09:58:28.829332 [ANA_INIT] MIDPI >>>>>>>>
682 09:58:28.829418 [ANA_INIT] MIDPI <<<<<<<<
683 09:58:28.832606 [ANA_INIT] DLL >>>>>>>>
684 09:58:28.835966 [ANA_INIT] flow end
685 09:58:28.838950 ============ LP4 DIFF to SE enter ============
686 09:58:28.842646 ============ LP4 DIFF to SE exit ============
687 09:58:28.846013 [ANA_INIT] <<<<<<<<<<<<<
688 09:58:28.848979 [Flow] Enable top DCM control >>>>>
689 09:58:28.852348 [Flow] Enable top DCM control <<<<<
690 09:58:28.855934 Enable DLL master slave shuffle
691 09:58:28.859519 ==============================================================
692 09:58:28.862654 Gating Mode config
693 09:58:28.866199 ==============================================================
694 09:58:28.869345 Config description:
695 09:58:28.879224 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 09:58:28.886075 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 09:58:28.889630 SELPH_MODE 0: By rank 1: By Phase
698 09:58:28.896224 ==============================================================
699 09:58:28.899480 GAT_TRACK_EN = 1
700 09:58:28.902750 RX_GATING_MODE = 2
701 09:58:28.906455 RX_GATING_TRACK_MODE = 2
702 09:58:28.906542 SELPH_MODE = 1
703 09:58:28.909575 PICG_EARLY_EN = 1
704 09:58:28.912690 VALID_LAT_VALUE = 1
705 09:58:28.919884 ==============================================================
706 09:58:28.922703 Enter into Gating configuration >>>>
707 09:58:28.926162 Exit from Gating configuration <<<<
708 09:58:28.930003 Enter into DVFS_PRE_config >>>>>
709 09:58:28.939646 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 09:58:28.943237 Exit from DVFS_PRE_config <<<<<
711 09:58:28.946233 Enter into PICG configuration >>>>
712 09:58:28.949856 Exit from PICG configuration <<<<
713 09:58:28.953377 [RX_INPUT] configuration >>>>>
714 09:58:28.956645 [RX_INPUT] configuration <<<<<
715 09:58:28.960109 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 09:58:28.966377 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 09:58:28.970477 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 09:58:28.977368 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 09:58:28.984436 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 09:58:28.991012 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 09:58:28.994262 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 09:58:28.997332 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 09:58:29.000990 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 09:58:29.007773 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 09:58:29.011125 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 09:58:29.014523 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 09:58:29.017674 ===================================
728 09:58:29.021475 LPDDR4 DRAM CONFIGURATION
729 09:58:29.024482 ===================================
730 09:58:29.024569 EX_ROW_EN[0] = 0x0
731 09:58:29.027993 EX_ROW_EN[1] = 0x0
732 09:58:29.031647 LP4Y_EN = 0x0
733 09:58:29.031732 WORK_FSP = 0x0
734 09:58:29.034615 WL = 0x2
735 09:58:29.034700 RL = 0x2
736 09:58:29.037899 BL = 0x2
737 09:58:29.037987 RPST = 0x0
738 09:58:29.041048 RD_PRE = 0x0
739 09:58:29.041134 WR_PRE = 0x1
740 09:58:29.044658 WR_PST = 0x0
741 09:58:29.044744 DBI_WR = 0x0
742 09:58:29.048265 DBI_RD = 0x0
743 09:58:29.048351 OTF = 0x1
744 09:58:29.051307 ===================================
745 09:58:29.055139 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 09:58:29.061650 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 09:58:29.064968 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 09:58:29.068579 ===================================
749 09:58:29.071589 LPDDR4 DRAM CONFIGURATION
750 09:58:29.075243 ===================================
751 09:58:29.075326 EX_ROW_EN[0] = 0x10
752 09:58:29.078325 EX_ROW_EN[1] = 0x0
753 09:58:29.078412 LP4Y_EN = 0x0
754 09:58:29.081818 WORK_FSP = 0x0
755 09:58:29.081902 WL = 0x2
756 09:58:29.084938 RL = 0x2
757 09:58:29.085024 BL = 0x2
758 09:58:29.088119 RPST = 0x0
759 09:58:29.088206 RD_PRE = 0x0
760 09:58:29.091575 WR_PRE = 0x1
761 09:58:29.091661 WR_PST = 0x0
762 09:58:29.095252 DBI_WR = 0x0
763 09:58:29.095338 DBI_RD = 0x0
764 09:58:29.098315 OTF = 0x1
765 09:58:29.102019 ===================================
766 09:58:29.108193 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 09:58:29.111955 nWR fixed to 40
768 09:58:29.115144 [ModeRegInit_LP4] CH0 RK0
769 09:58:29.115233 [ModeRegInit_LP4] CH0 RK1
770 09:58:29.118575 [ModeRegInit_LP4] CH1 RK0
771 09:58:29.121852 [ModeRegInit_LP4] CH1 RK1
772 09:58:29.121939 match AC timing 13
773 09:58:29.128857 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 09:58:29.131851 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 09:58:29.134909 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 09:58:29.141946 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 09:58:29.145533 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 09:58:29.145631 [EMI DOE] emi_dcm 0
779 09:58:29.152154 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 09:58:29.152249 ==
781 09:58:29.155118 Dram Type= 6, Freq= 0, CH_0, rank 0
782 09:58:29.158926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 09:58:29.159005 ==
784 09:58:29.165627 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 09:58:29.168558 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 09:58:29.178984 [CA 0] Center 37 (6~68) winsize 63
787 09:58:29.182768 [CA 1] Center 37 (6~68) winsize 63
788 09:58:29.185822 [CA 2] Center 35 (5~66) winsize 62
789 09:58:29.188868 [CA 3] Center 34 (4~65) winsize 62
790 09:58:29.192671 [CA 4] Center 34 (3~65) winsize 63
791 09:58:29.195690 [CA 5] Center 33 (3~64) winsize 62
792 09:58:29.195776
793 09:58:29.199492 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 09:58:29.199578
795 09:58:29.202540 [CATrainingPosCal] consider 1 rank data
796 09:58:29.205580 u2DelayCellTimex100 = 270/100 ps
797 09:58:29.209377 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
798 09:58:29.212463 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 09:58:29.219170 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
800 09:58:29.222521 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 09:58:29.226262 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
802 09:58:29.229086 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 09:58:29.229172
804 09:58:29.232467 CA PerBit enable=1, Macro0, CA PI delay=33
805 09:58:29.232580
806 09:58:29.236356 [CBTSetCACLKResult] CA Dly = 33
807 09:58:29.236442 CS Dly: 5 (0~36)
808 09:58:29.236510 ==
809 09:58:29.239349 Dram Type= 6, Freq= 0, CH_0, rank 1
810 09:58:29.246338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 09:58:29.246426 ==
812 09:58:29.249557 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 09:58:29.255931 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 09:58:29.265065 [CA 0] Center 37 (7~68) winsize 62
815 09:58:29.268739 [CA 1] Center 37 (7~68) winsize 62
816 09:58:29.271904 [CA 2] Center 35 (4~66) winsize 63
817 09:58:29.275729 [CA 3] Center 35 (4~66) winsize 63
818 09:58:29.278849 [CA 4] Center 34 (3~65) winsize 63
819 09:58:29.282242 [CA 5] Center 33 (3~64) winsize 62
820 09:58:29.282322
821 09:58:29.285220 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 09:58:29.285306
823 09:58:29.288864 [CATrainingPosCal] consider 2 rank data
824 09:58:29.292445 u2DelayCellTimex100 = 270/100 ps
825 09:58:29.295473 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 09:58:29.299148 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 09:58:29.302225 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
828 09:58:29.309141 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 09:58:29.312327 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
830 09:58:29.316028 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 09:58:29.316114
832 09:58:29.319159 CA PerBit enable=1, Macro0, CA PI delay=33
833 09:58:29.319246
834 09:58:29.322206 [CBTSetCACLKResult] CA Dly = 33
835 09:58:29.322292 CS Dly: 6 (0~38)
836 09:58:29.322360
837 09:58:29.325950 ----->DramcWriteLeveling(PI) begin...
838 09:58:29.326041 ==
839 09:58:29.328978 Dram Type= 6, Freq= 0, CH_0, rank 0
840 09:58:29.336058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 09:58:29.336151 ==
842 09:58:29.336246 Write leveling (Byte 0): 31 => 31
843 09:58:29.339962 Write leveling (Byte 1): 28 => 28
844 09:58:29.343522 DramcWriteLeveling(PI) end<-----
845 09:58:29.343608
846 09:58:29.343685 ==
847 09:58:29.347091 Dram Type= 6, Freq= 0, CH_0, rank 0
848 09:58:29.350759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 09:58:29.350886 ==
850 09:58:29.354328 [Gating] SW mode calibration
851 09:58:29.361306 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 09:58:29.368577 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 09:58:29.371678 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 09:58:29.375409 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 09:58:29.378399 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 09:58:29.385006 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
857 09:58:29.388589 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 09:58:29.391950 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 09:58:29.398713 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 09:58:29.402384 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 09:58:29.405512 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 09:58:29.412290 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 09:58:29.415408 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 09:58:29.419085 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 09:58:29.422110 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 09:58:29.428997 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 09:58:29.432056 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 09:58:29.435941 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 09:58:29.442808 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 09:58:29.445979 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 09:58:29.449419 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
872 09:58:29.455864 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 09:58:29.459293 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 09:58:29.462392 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 09:58:29.469264 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 09:58:29.472578 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 09:58:29.476043 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 09:58:29.479508 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 09:58:29.486301 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
880 09:58:29.489389 0 9 12 | B1->B0 | 2626 3333 | 1 0 | (1 1) (0 0)
881 09:58:29.492543 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 09:58:29.499312 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 09:58:29.503054 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 09:58:29.505992 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 09:58:29.512796 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 09:58:29.516513 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
887 09:58:29.519553 0 10 8 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
888 09:58:29.526277 0 10 12 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
889 09:58:29.530080 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 09:58:29.533145 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 09:58:29.539916 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 09:58:29.542920 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 09:58:29.546640 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 09:58:29.549749 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
895 09:58:29.556359 0 11 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
896 09:58:29.559942 0 11 12 | B1->B0 | 3333 4242 | 1 1 | (0 0) (0 0)
897 09:58:29.563100 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 09:58:29.569642 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 09:58:29.573193 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 09:58:29.576632 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 09:58:29.583590 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 09:58:29.586816 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 09:58:29.590164 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
904 09:58:29.596659 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
905 09:58:29.600245 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 09:58:29.603748 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 09:58:29.606885 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 09:58:29.613562 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 09:58:29.617362 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 09:58:29.620360 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 09:58:29.627311 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 09:58:29.630358 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 09:58:29.634222 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 09:58:29.640480 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 09:58:29.644145 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 09:58:29.647297 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 09:58:29.650985 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 09:58:29.657162 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 09:58:29.661092 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
920 09:58:29.664062 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
921 09:58:29.667818 Total UI for P1: 0, mck2ui 16
922 09:58:29.670782 best dqsien dly found for B0: ( 0, 14, 8)
923 09:58:29.674155 Total UI for P1: 0, mck2ui 16
924 09:58:29.677620 best dqsien dly found for B1: ( 0, 14, 8)
925 09:58:29.680978 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
926 09:58:29.684508 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 09:58:29.684631
928 09:58:29.691190 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
929 09:58:29.694225 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 09:58:29.694310 [Gating] SW calibration Done
931 09:58:29.694403 ==
932 09:58:29.697799 Dram Type= 6, Freq= 0, CH_0, rank 0
933 09:58:29.704727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 09:58:29.704819 ==
935 09:58:29.704913 RX Vref Scan: 0
936 09:58:29.704995
937 09:58:29.707889 RX Vref 0 -> 0, step: 1
938 09:58:29.707972
939 09:58:29.711385 RX Delay -130 -> 252, step: 16
940 09:58:29.714674 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 09:58:29.717743 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 09:58:29.721322 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 09:58:29.728013 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 09:58:29.731251 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
945 09:58:29.735030 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
946 09:58:29.738010 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
947 09:58:29.741580 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
948 09:58:29.744662 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
949 09:58:29.751569 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
950 09:58:29.754610 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
951 09:58:29.758235 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
952 09:58:29.761325 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
953 09:58:29.765081 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
954 09:58:29.772146 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 09:58:29.775088 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
956 09:58:29.775169 ==
957 09:58:29.778530 Dram Type= 6, Freq= 0, CH_0, rank 0
958 09:58:29.781387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 09:58:29.781493 ==
960 09:58:29.784964 DQS Delay:
961 09:58:29.785081 DQS0 = 0, DQS1 = 0
962 09:58:29.785179 DQM Delay:
963 09:58:29.788214 DQM0 = 88, DQM1 = 78
964 09:58:29.788303 DQ Delay:
965 09:58:29.791973 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 09:58:29.795369 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
967 09:58:29.798445 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =77
968 09:58:29.802031 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =93
969 09:58:29.802109
970 09:58:29.802174
971 09:58:29.802239 ==
972 09:58:29.805374 Dram Type= 6, Freq= 0, CH_0, rank 0
973 09:58:29.812243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 09:58:29.812338 ==
975 09:58:29.812409
976 09:58:29.812474
977 09:58:29.812533 TX Vref Scan disable
978 09:58:29.815600 == TX Byte 0 ==
979 09:58:29.818822 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
980 09:58:29.822082 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
981 09:58:29.825489 == TX Byte 1 ==
982 09:58:29.829105 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
983 09:58:29.832087 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
984 09:58:29.835794 ==
985 09:58:29.838678 Dram Type= 6, Freq= 0, CH_0, rank 0
986 09:58:29.842425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 09:58:29.842545 ==
988 09:58:29.854991 TX Vref=22, minBit 5, minWin=27, winSum=442
989 09:58:29.858570 TX Vref=24, minBit 5, minWin=27, winSum=445
990 09:58:29.861677 TX Vref=26, minBit 5, minWin=27, winSum=450
991 09:58:29.864781 TX Vref=28, minBit 5, minWin=27, winSum=453
992 09:58:29.868469 TX Vref=30, minBit 5, minWin=27, winSum=453
993 09:58:29.871448 TX Vref=32, minBit 2, minWin=28, winSum=455
994 09:58:29.878358 [TxChooseVref] Worse bit 2, Min win 28, Win sum 455, Final Vref 32
995 09:58:29.878448
996 09:58:29.881908 Final TX Range 1 Vref 32
997 09:58:29.881996
998 09:58:29.882080 ==
999 09:58:29.884865 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 09:58:29.888504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 09:58:29.888592 ==
1002 09:58:29.888665
1003 09:58:29.888730
1004 09:58:29.891708 TX Vref Scan disable
1005 09:58:29.895293 == TX Byte 0 ==
1006 09:58:29.898289 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1007 09:58:29.902044 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1008 09:58:29.905136 == TX Byte 1 ==
1009 09:58:29.908432 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1010 09:58:29.912143 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1011 09:58:29.912264
1012 09:58:29.915161 [DATLAT]
1013 09:58:29.915253 Freq=800, CH0 RK0
1014 09:58:29.915345
1015 09:58:29.918830 DATLAT Default: 0xa
1016 09:58:29.918928 0, 0xFFFF, sum = 0
1017 09:58:29.921805 1, 0xFFFF, sum = 0
1018 09:58:29.921928 2, 0xFFFF, sum = 0
1019 09:58:29.925505 3, 0xFFFF, sum = 0
1020 09:58:29.925613 4, 0xFFFF, sum = 0
1021 09:58:29.928675 5, 0xFFFF, sum = 0
1022 09:58:29.928764 6, 0xFFFF, sum = 0
1023 09:58:29.932408 7, 0xFFFF, sum = 0
1024 09:58:29.932553 8, 0xFFFF, sum = 0
1025 09:58:29.935340 9, 0x0, sum = 1
1026 09:58:29.935427 10, 0x0, sum = 2
1027 09:58:29.938536 11, 0x0, sum = 3
1028 09:58:29.938629 12, 0x0, sum = 4
1029 09:58:29.942176 best_step = 10
1030 09:58:29.942273
1031 09:58:29.942364 ==
1032 09:58:29.945636 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 09:58:29.949291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 09:58:29.949382 ==
1035 09:58:29.949493 RX Vref Scan: 1
1036 09:58:29.949588
1037 09:58:29.952215 Set Vref Range= 32 -> 127
1038 09:58:29.952318
1039 09:58:29.955824 RX Vref 32 -> 127, step: 1
1040 09:58:29.955909
1041 09:58:29.958873 RX Delay -111 -> 252, step: 8
1042 09:58:29.958956
1043 09:58:29.962092 Set Vref, RX VrefLevel [Byte0]: 32
1044 09:58:29.965432 [Byte1]: 32
1045 09:58:29.965550
1046 09:58:29.968802 Set Vref, RX VrefLevel [Byte0]: 33
1047 09:58:29.973236 [Byte1]: 33
1048 09:58:29.973344
1049 09:58:29.976358 Set Vref, RX VrefLevel [Byte0]: 34
1050 09:58:29.979341 [Byte1]: 34
1051 09:58:29.983234
1052 09:58:29.983311 Set Vref, RX VrefLevel [Byte0]: 35
1053 09:58:29.986336 [Byte1]: 35
1054 09:58:29.990511
1055 09:58:29.990592 Set Vref, RX VrefLevel [Byte0]: 36
1056 09:58:29.993561 [Byte1]: 36
1057 09:58:29.997866
1058 09:58:29.997938 Set Vref, RX VrefLevel [Byte0]: 37
1059 09:58:30.001694 [Byte1]: 37
1060 09:58:30.006568
1061 09:58:30.006655 Set Vref, RX VrefLevel [Byte0]: 38
1062 09:58:30.009706 [Byte1]: 38
1063 09:58:30.013842
1064 09:58:30.013950 Set Vref, RX VrefLevel [Byte0]: 39
1065 09:58:30.017277 [Byte1]: 39
1066 09:58:30.021492
1067 09:58:30.021575 Set Vref, RX VrefLevel [Byte0]: 40
1068 09:58:30.024852 [Byte1]: 40
1069 09:58:30.028698
1070 09:58:30.028777 Set Vref, RX VrefLevel [Byte0]: 41
1071 09:58:30.032277 [Byte1]: 41
1072 09:58:30.036631
1073 09:58:30.036711 Set Vref, RX VrefLevel [Byte0]: 42
1074 09:58:30.040406 [Byte1]: 42
1075 09:58:30.044051
1076 09:58:30.044128 Set Vref, RX VrefLevel [Byte0]: 43
1077 09:58:30.047159 [Byte1]: 43
1078 09:58:30.051431
1079 09:58:30.051513 Set Vref, RX VrefLevel [Byte0]: 44
1080 09:58:30.058247 [Byte1]: 44
1081 09:58:30.058327
1082 09:58:30.061420 Set Vref, RX VrefLevel [Byte0]: 45
1083 09:58:30.065023 [Byte1]: 45
1084 09:58:30.065102
1085 09:58:30.068059 Set Vref, RX VrefLevel [Byte0]: 46
1086 09:58:30.071236 [Byte1]: 46
1087 09:58:30.071340
1088 09:58:30.074885 Set Vref, RX VrefLevel [Byte0]: 47
1089 09:58:30.078090 [Byte1]: 47
1090 09:58:30.081949
1091 09:58:30.082023 Set Vref, RX VrefLevel [Byte0]: 48
1092 09:58:30.085491 [Byte1]: 48
1093 09:58:30.089897
1094 09:58:30.089979 Set Vref, RX VrefLevel [Byte0]: 49
1095 09:58:30.093290 [Byte1]: 49
1096 09:58:30.097604
1097 09:58:30.097674 Set Vref, RX VrefLevel [Byte0]: 50
1098 09:58:30.100658 [Byte1]: 50
1099 09:58:30.105001
1100 09:58:30.105075 Set Vref, RX VrefLevel [Byte0]: 51
1101 09:58:30.108853 [Byte1]: 51
1102 09:58:30.112839
1103 09:58:30.112911 Set Vref, RX VrefLevel [Byte0]: 52
1104 09:58:30.115963 [Byte1]: 52
1105 09:58:30.120167
1106 09:58:30.120240 Set Vref, RX VrefLevel [Byte0]: 53
1107 09:58:30.123875 [Byte1]: 53
1108 09:58:30.127980
1109 09:58:30.128054 Set Vref, RX VrefLevel [Byte0]: 54
1110 09:58:30.131200 [Byte1]: 54
1111 09:58:30.135590
1112 09:58:30.135666 Set Vref, RX VrefLevel [Byte0]: 55
1113 09:58:30.138904 [Byte1]: 55
1114 09:58:30.143156
1115 09:58:30.143237 Set Vref, RX VrefLevel [Byte0]: 56
1116 09:58:30.146591 [Byte1]: 56
1117 09:58:30.151133
1118 09:58:30.151215 Set Vref, RX VrefLevel [Byte0]: 57
1119 09:58:30.154248 [Byte1]: 57
1120 09:58:30.158586
1121 09:58:30.158665 Set Vref, RX VrefLevel [Byte0]: 58
1122 09:58:30.162192 [Byte1]: 58
1123 09:58:30.166250
1124 09:58:30.166361 Set Vref, RX VrefLevel [Byte0]: 59
1125 09:58:30.169561 [Byte1]: 59
1126 09:58:30.173634
1127 09:58:30.173732 Set Vref, RX VrefLevel [Byte0]: 60
1128 09:58:30.177194 [Byte1]: 60
1129 09:58:30.181828
1130 09:58:30.181926 Set Vref, RX VrefLevel [Byte0]: 61
1131 09:58:30.184852 [Byte1]: 61
1132 09:58:30.189212
1133 09:58:30.189293 Set Vref, RX VrefLevel [Byte0]: 62
1134 09:58:30.192445 [Byte1]: 62
1135 09:58:30.196670
1136 09:58:30.196745 Set Vref, RX VrefLevel [Byte0]: 63
1137 09:58:30.200414 [Byte1]: 63
1138 09:58:30.204696
1139 09:58:30.204779 Set Vref, RX VrefLevel [Byte0]: 64
1140 09:58:30.207799 [Byte1]: 64
1141 09:58:30.211928
1142 09:58:30.212006 Set Vref, RX VrefLevel [Byte0]: 65
1143 09:58:30.215224 [Byte1]: 65
1144 09:58:30.220275
1145 09:58:30.220350 Set Vref, RX VrefLevel [Byte0]: 66
1146 09:58:30.223414 [Byte1]: 66
1147 09:58:30.227236
1148 09:58:30.227311 Set Vref, RX VrefLevel [Byte0]: 67
1149 09:58:30.230930 [Byte1]: 67
1150 09:58:30.235141
1151 09:58:30.235239 Set Vref, RX VrefLevel [Byte0]: 68
1152 09:58:30.238608 [Byte1]: 68
1153 09:58:30.242721
1154 09:58:30.242796 Set Vref, RX VrefLevel [Byte0]: 69
1155 09:58:30.245905 [Byte1]: 69
1156 09:58:30.250077
1157 09:58:30.250155 Set Vref, RX VrefLevel [Byte0]: 70
1158 09:58:30.253517 [Byte1]: 70
1159 09:58:30.258090
1160 09:58:30.258169 Set Vref, RX VrefLevel [Byte0]: 71
1161 09:58:30.261584 [Byte1]: 71
1162 09:58:30.265478
1163 09:58:30.265555 Set Vref, RX VrefLevel [Byte0]: 72
1164 09:58:30.269196 [Byte1]: 72
1165 09:58:30.273475
1166 09:58:30.273550 Set Vref, RX VrefLevel [Byte0]: 73
1167 09:58:30.276392 [Byte1]: 73
1168 09:58:30.280991
1169 09:58:30.281075 Set Vref, RX VrefLevel [Byte0]: 74
1170 09:58:30.284101 [Byte1]: 74
1171 09:58:30.288792
1172 09:58:30.288874 Set Vref, RX VrefLevel [Byte0]: 75
1173 09:58:30.291936 [Byte1]: 75
1174 09:58:30.296331
1175 09:58:30.296421 Set Vref, RX VrefLevel [Byte0]: 76
1176 09:58:30.299369 [Byte1]: 76
1177 09:58:30.304191
1178 09:58:30.304277 Final RX Vref Byte 0 = 60 to rank0
1179 09:58:30.307311 Final RX Vref Byte 1 = 61 to rank0
1180 09:58:30.310423 Final RX Vref Byte 0 = 60 to rank1
1181 09:58:30.314220 Final RX Vref Byte 1 = 61 to rank1==
1182 09:58:30.317336 Dram Type= 6, Freq= 0, CH_0, rank 0
1183 09:58:30.320834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1184 09:58:30.324036 ==
1185 09:58:30.324108 DQS Delay:
1186 09:58:30.324176 DQS0 = 0, DQS1 = 0
1187 09:58:30.327182 DQM Delay:
1188 09:58:30.327258 DQM0 = 87, DQM1 = 78
1189 09:58:30.330843 DQ Delay:
1190 09:58:30.333988 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1191 09:58:30.334067 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1192 09:58:30.337829 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =72
1193 09:58:30.340767 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1194 09:58:30.340837
1195 09:58:30.344450
1196 09:58:30.351228 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b12, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 398 ps
1197 09:58:30.354109 CH0 RK0: MR19=606, MR18=2B12
1198 09:58:30.360944 CH0_RK0: MR19=0x606, MR18=0x2B12, DQSOSC=398, MR23=63, INC=93, DEC=62
1199 09:58:30.361022
1200 09:58:30.364535 ----->DramcWriteLeveling(PI) begin...
1201 09:58:30.364615 ==
1202 09:58:30.367882 Dram Type= 6, Freq= 0, CH_0, rank 1
1203 09:58:30.371185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1204 09:58:30.371271 ==
1205 09:58:30.374602 Write leveling (Byte 0): 29 => 29
1206 09:58:30.377915 Write leveling (Byte 1): 27 => 27
1207 09:58:30.381012 DramcWriteLeveling(PI) end<-----
1208 09:58:30.381085
1209 09:58:30.381148 ==
1210 09:58:30.384507 Dram Type= 6, Freq= 0, CH_0, rank 1
1211 09:58:30.387993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1212 09:58:30.388075 ==
1213 09:58:30.390986 [Gating] SW mode calibration
1214 09:58:30.397752 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1215 09:58:30.404352 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1216 09:58:30.407862 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1217 09:58:30.411012 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1218 09:58:30.414748 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1219 09:58:30.458623 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 09:58:30.458896 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 09:58:30.458984 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 09:58:30.459064 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 09:58:30.459127 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 09:58:30.459205 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 09:58:30.459450 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 09:58:30.459699 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 09:58:30.460246 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 09:58:30.460313 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 09:58:30.502576 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 09:58:30.502895 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 09:58:30.503015 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 09:58:30.503131 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1233 09:58:30.503225 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1234 09:58:30.503343 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1235 09:58:30.503458 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 09:58:30.503743 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 09:58:30.504035 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 09:58:30.504133 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 09:58:30.511049 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 09:58:30.514098 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 09:58:30.517554 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 09:58:30.520795 0 9 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
1243 09:58:30.527979 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1244 09:58:30.531151 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 09:58:30.534038 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 09:58:30.537719 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 09:58:30.544426 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 09:58:30.547590 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 09:58:30.551284 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
1250 09:58:30.557496 0 10 8 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
1251 09:58:30.561286 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 09:58:30.564230 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 09:58:30.571198 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 09:58:30.574558 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 09:58:30.577989 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 09:58:30.585372 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 09:58:30.589155 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1258 09:58:30.592866 0 11 8 | B1->B0 | 2323 3f3f | 0 1 | (0 0) (0 0)
1259 09:58:30.596566 0 11 12 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
1260 09:58:30.600351 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 09:58:30.603443 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 09:58:30.610036 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 09:58:30.614166 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 09:58:30.617571 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 09:58:30.624323 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 09:58:30.627800 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1267 09:58:30.630794 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1268 09:58:30.633930 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 09:58:30.640802 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 09:58:30.644177 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 09:58:30.647287 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 09:58:30.654304 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 09:58:30.657943 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 09:58:30.660962 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 09:58:30.667688 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 09:58:30.671241 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 09:58:30.674392 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 09:58:30.681082 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 09:58:30.684472 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 09:58:30.687854 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 09:58:30.691436 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1282 09:58:30.698283 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1283 09:58:30.701381 Total UI for P1: 0, mck2ui 16
1284 09:58:30.704408 best dqsien dly found for B0: ( 0, 14, 4)
1285 09:58:30.708124 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1286 09:58:30.711114 Total UI for P1: 0, mck2ui 16
1287 09:58:30.714892 best dqsien dly found for B1: ( 0, 14, 8)
1288 09:58:30.717915 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1289 09:58:30.721240 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1290 09:58:30.721322
1291 09:58:30.724691 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1292 09:58:30.728467 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1293 09:58:30.731601 [Gating] SW calibration Done
1294 09:58:30.731682 ==
1295 09:58:30.735198 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 09:58:30.738711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 09:58:30.738819 ==
1298 09:58:30.741589 RX Vref Scan: 0
1299 09:58:30.741696
1300 09:58:30.745202 RX Vref 0 -> 0, step: 1
1301 09:58:30.745285
1302 09:58:30.745349 RX Delay -130 -> 252, step: 16
1303 09:58:30.752157 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1304 09:58:30.755464 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1305 09:58:30.758663 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1306 09:58:30.762235 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1307 09:58:30.765361 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1308 09:58:30.772167 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1309 09:58:30.775226 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1310 09:58:30.779011 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1311 09:58:30.782078 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1312 09:58:30.785550 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1313 09:58:30.788826 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1314 09:58:30.795560 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1315 09:58:30.799181 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1316 09:58:30.802302 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1317 09:58:30.805320 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1318 09:58:30.812122 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1319 09:58:30.812205 ==
1320 09:58:30.815795 Dram Type= 6, Freq= 0, CH_0, rank 1
1321 09:58:30.818994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1322 09:58:30.819093 ==
1323 09:58:30.819159 DQS Delay:
1324 09:58:30.822446 DQS0 = 0, DQS1 = 0
1325 09:58:30.822528 DQM Delay:
1326 09:58:30.825920 DQM0 = 87, DQM1 = 76
1327 09:58:30.826002 DQ Delay:
1328 09:58:30.828880 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1329 09:58:30.832132 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =93
1330 09:58:30.835862 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =77
1331 09:58:30.838943 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1332 09:58:30.839039
1333 09:58:30.839104
1334 09:58:30.839164 ==
1335 09:58:30.842573 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 09:58:30.845737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 09:58:30.845820 ==
1338 09:58:30.845885
1339 09:58:30.845945
1340 09:58:30.849246 TX Vref Scan disable
1341 09:58:30.852383 == TX Byte 0 ==
1342 09:58:30.855984 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1343 09:58:30.858908 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1344 09:58:30.862282 == TX Byte 1 ==
1345 09:58:30.866204 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1346 09:58:30.869439 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1347 09:58:30.869521 ==
1348 09:58:30.872700 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 09:58:30.876264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 09:58:30.876347 ==
1351 09:58:30.890827 TX Vref=22, minBit 1, minWin=27, winSum=438
1352 09:58:30.894043 TX Vref=24, minBit 3, minWin=27, winSum=441
1353 09:58:30.896990 TX Vref=26, minBit 9, minWin=27, winSum=448
1354 09:58:30.900613 TX Vref=28, minBit 8, minWin=27, winSum=451
1355 09:58:30.904007 TX Vref=30, minBit 8, minWin=27, winSum=453
1356 09:58:30.907058 TX Vref=32, minBit 8, minWin=27, winSum=447
1357 09:58:30.913985 [TxChooseVref] Worse bit 8, Min win 27, Win sum 453, Final Vref 30
1358 09:58:30.914065
1359 09:58:30.917224 Final TX Range 1 Vref 30
1360 09:58:30.917317
1361 09:58:30.917380 ==
1362 09:58:30.920802 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 09:58:30.923993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 09:58:30.924068 ==
1365 09:58:30.924133
1366 09:58:30.924194
1367 09:58:30.927502 TX Vref Scan disable
1368 09:58:30.931014 == TX Byte 0 ==
1369 09:58:30.934256 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1370 09:58:30.937486 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1371 09:58:30.940751 == TX Byte 1 ==
1372 09:58:30.944425 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1373 09:58:30.947461 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1374 09:58:30.947535
1375 09:58:30.951066 [DATLAT]
1376 09:58:30.951152 Freq=800, CH0 RK1
1377 09:58:30.951218
1378 09:58:30.954207 DATLAT Default: 0xa
1379 09:58:30.954299 0, 0xFFFF, sum = 0
1380 09:58:30.957883 1, 0xFFFF, sum = 0
1381 09:58:30.957959 2, 0xFFFF, sum = 0
1382 09:58:30.960963 3, 0xFFFF, sum = 0
1383 09:58:30.961048 4, 0xFFFF, sum = 0
1384 09:58:30.964730 5, 0xFFFF, sum = 0
1385 09:58:30.964830 6, 0xFFFF, sum = 0
1386 09:58:30.967882 7, 0xFFFF, sum = 0
1387 09:58:30.967954 8, 0xFFFF, sum = 0
1388 09:58:30.971430 9, 0x0, sum = 1
1389 09:58:30.971527 10, 0x0, sum = 2
1390 09:58:30.974538 11, 0x0, sum = 3
1391 09:58:30.974621 12, 0x0, sum = 4
1392 09:58:30.977860 best_step = 10
1393 09:58:30.977933
1394 09:58:30.978000 ==
1395 09:58:30.981374 Dram Type= 6, Freq= 0, CH_0, rank 1
1396 09:58:30.984784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1397 09:58:30.984874 ==
1398 09:58:30.984941 RX Vref Scan: 0
1399 09:58:30.985003
1400 09:58:30.987830 RX Vref 0 -> 0, step: 1
1401 09:58:30.987961
1402 09:58:30.991406 RX Delay -95 -> 252, step: 8
1403 09:58:30.994357 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1404 09:58:31.001802 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1405 09:58:31.004743 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1406 09:58:31.007739 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1407 09:58:31.011253 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1408 09:58:31.014654 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1409 09:58:31.021581 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1410 09:58:31.024750 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1411 09:58:31.028298 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1412 09:58:31.031465 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1413 09:58:31.035091 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1414 09:58:31.038196 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1415 09:58:31.045122 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1416 09:58:31.048199 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1417 09:58:31.051574 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1418 09:58:31.055358 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1419 09:58:31.055438 ==
1420 09:58:31.058560 Dram Type= 6, Freq= 0, CH_0, rank 1
1421 09:58:31.065544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1422 09:58:31.065632 ==
1423 09:58:31.065697 DQS Delay:
1424 09:58:31.065757 DQS0 = 0, DQS1 = 0
1425 09:58:31.068671 DQM Delay:
1426 09:58:31.068758 DQM0 = 87, DQM1 = 78
1427 09:58:31.071715 DQ Delay:
1428 09:58:31.075440 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1429 09:58:31.075535 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1430 09:58:31.078792 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1431 09:58:31.082036 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88
1432 09:58:31.085085
1433 09:58:31.085171
1434 09:58:31.091988 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f18, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1435 09:58:31.095600 CH0 RK1: MR19=606, MR18=2F18
1436 09:58:31.102008 CH0_RK1: MR19=0x606, MR18=0x2F18, DQSOSC=397, MR23=63, INC=93, DEC=62
1437 09:58:31.102125 [RxdqsGatingPostProcess] freq 800
1438 09:58:31.109128 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1439 09:58:31.112119 Pre-setting of DQS Precalculation
1440 09:58:31.119252 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1441 09:58:31.119337 ==
1442 09:58:31.122081 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 09:58:31.125672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 09:58:31.125762 ==
1445 09:58:31.128722 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1446 09:58:31.135501 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1447 09:58:31.145474 [CA 0] Center 36 (6~67) winsize 62
1448 09:58:31.148492 [CA 1] Center 36 (6~66) winsize 61
1449 09:58:31.152025 [CA 2] Center 34 (4~64) winsize 61
1450 09:58:31.155387 [CA 3] Center 33 (3~64) winsize 62
1451 09:58:31.159097 [CA 4] Center 34 (3~65) winsize 63
1452 09:58:31.161745 [CA 5] Center 33 (3~64) winsize 62
1453 09:58:31.161831
1454 09:58:31.165557 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1455 09:58:31.165643
1456 09:58:31.168595 [CATrainingPosCal] consider 1 rank data
1457 09:58:31.172237 u2DelayCellTimex100 = 270/100 ps
1458 09:58:31.175346 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1459 09:58:31.178938 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1460 09:58:31.181953 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1461 09:58:31.188745 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1462 09:58:31.192504 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1463 09:58:31.195385 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1464 09:58:31.195483
1465 09:58:31.199008 CA PerBit enable=1, Macro0, CA PI delay=33
1466 09:58:31.199102
1467 09:58:31.202320 [CBTSetCACLKResult] CA Dly = 33
1468 09:58:31.202408 CS Dly: 4 (0~35)
1469 09:58:31.202494 ==
1470 09:58:31.205936 Dram Type= 6, Freq= 0, CH_1, rank 1
1471 09:58:31.212697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1472 09:58:31.212813 ==
1473 09:58:31.216048 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1474 09:58:31.222026 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1475 09:58:31.231481 [CA 0] Center 36 (6~67) winsize 62
1476 09:58:31.234587 [CA 1] Center 36 (6~66) winsize 61
1477 09:58:31.238164 [CA 2] Center 34 (4~65) winsize 62
1478 09:58:31.241411 [CA 3] Center 33 (3~64) winsize 62
1479 09:58:31.245074 [CA 4] Center 34 (4~65) winsize 62
1480 09:58:31.248186 [CA 5] Center 33 (3~64) winsize 62
1481 09:58:31.248271
1482 09:58:31.251971 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1483 09:58:31.252056
1484 09:58:31.255777 [CATrainingPosCal] consider 2 rank data
1485 09:58:31.259655 u2DelayCellTimex100 = 270/100 ps
1486 09:58:31.263603 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1487 09:58:31.267283 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1488 09:58:31.270549 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1489 09:58:31.274858 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1490 09:58:31.278003 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1491 09:58:31.281840 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1492 09:58:31.281975
1493 09:58:31.285634 CA PerBit enable=1, Macro0, CA PI delay=33
1494 09:58:31.285767
1495 09:58:31.289140 [CBTSetCACLKResult] CA Dly = 33
1496 09:58:31.289282 CS Dly: 5 (0~37)
1497 09:58:31.289404
1498 09:58:31.292031 ----->DramcWriteLeveling(PI) begin...
1499 09:58:31.292164 ==
1500 09:58:31.295649 Dram Type= 6, Freq= 0, CH_1, rank 0
1501 09:58:31.299293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1502 09:58:31.299381 ==
1503 09:58:31.302218 Write leveling (Byte 0): 28 => 28
1504 09:58:31.305985 Write leveling (Byte 1): 29 => 29
1505 09:58:31.309027 DramcWriteLeveling(PI) end<-----
1506 09:58:31.309110
1507 09:58:31.309201 ==
1508 09:58:31.312618 Dram Type= 6, Freq= 0, CH_1, rank 0
1509 09:58:31.319457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1510 09:58:31.319572 ==
1511 09:58:31.319667 [Gating] SW mode calibration
1512 09:58:31.329323 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1513 09:58:31.332938 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1514 09:58:31.335999 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1515 09:58:31.342791 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (1 1) (1 0)
1516 09:58:31.346358 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1517 09:58:31.349501 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 09:58:31.353292 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 09:58:31.360130 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 09:58:31.363192 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 09:58:31.366851 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 09:58:31.373148 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 09:58:31.376419 0 7 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1524 09:58:31.379450 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 09:58:31.386324 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1526 09:58:31.390003 0 7 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1527 09:58:31.392898 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 09:58:31.400046 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 09:58:31.402984 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 09:58:31.406539 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 09:58:31.413375 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1532 09:58:31.416398 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1533 09:58:31.419858 0 8 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1534 09:58:31.426505 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 09:58:31.430322 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 09:58:31.433363 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 09:58:31.436502 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 09:58:31.443240 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 09:58:31.446750 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 09:58:31.450387 0 9 8 | B1->B0 | 2424 2727 | 0 1 | (0 0) (0 0)
1541 09:58:31.457050 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1542 09:58:31.459990 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 09:58:31.463564 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1544 09:58:31.470196 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 09:58:31.473764 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 09:58:31.476820 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 09:58:31.483928 0 10 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1548 09:58:31.487179 0 10 8 | B1->B0 | 2b2b 2e2e | 0 0 | (1 0) (0 0)
1549 09:58:31.490277 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 09:58:31.493887 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 09:58:31.500544 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 09:58:31.504068 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 09:58:31.507056 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 09:58:31.513973 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 09:58:31.517131 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 09:58:31.520910 0 11 8 | B1->B0 | 3333 3232 | 0 1 | (0 0) (0 0)
1557 09:58:31.527416 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 09:58:31.530651 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 09:58:31.534487 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 09:58:31.540661 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 09:58:31.543928 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 09:58:31.547461 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 09:58:31.554070 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1564 09:58:31.557638 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1565 09:58:31.560933 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 09:58:31.564173 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 09:58:31.570750 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 09:58:31.574326 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 09:58:31.577980 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 09:58:31.584636 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 09:58:31.588051 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 09:58:31.591021 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 09:58:31.597720 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 09:58:31.601271 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 09:58:31.604302 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 09:58:31.608035 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 09:58:31.614900 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 09:58:31.618083 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 09:58:31.621591 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 09:58:31.627815 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1581 09:58:31.631591 Total UI for P1: 0, mck2ui 16
1582 09:58:31.634913 best dqsien dly found for B0: ( 0, 14, 6)
1583 09:58:31.635028 Total UI for P1: 0, mck2ui 16
1584 09:58:31.641835 best dqsien dly found for B1: ( 0, 14, 6)
1585 09:58:31.644974 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1586 09:58:31.647905 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1587 09:58:31.648008
1588 09:58:31.651594 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1589 09:58:31.654748 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1590 09:58:31.658374 [Gating] SW calibration Done
1591 09:58:31.658454 ==
1592 09:58:31.661445 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 09:58:31.665207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 09:58:31.665314 ==
1595 09:58:31.668282 RX Vref Scan: 0
1596 09:58:31.668361
1597 09:58:31.668426 RX Vref 0 -> 0, step: 1
1598 09:58:31.668493
1599 09:58:31.671760 RX Delay -130 -> 252, step: 16
1600 09:58:31.675096 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1601 09:58:31.681737 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1602 09:58:31.685167 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1603 09:58:31.688337 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1604 09:58:31.691791 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1605 09:58:31.695245 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1606 09:58:31.698128 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1607 09:58:31.705015 iDelay=222, Bit 7, Center 69 (-50 ~ 189) 240
1608 09:58:31.708666 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1609 09:58:31.711848 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1610 09:58:31.715252 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1611 09:58:31.718406 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1612 09:58:31.724999 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1613 09:58:31.728890 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1614 09:58:31.731817 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1615 09:58:31.734986 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1616 09:58:31.735067 ==
1617 09:58:31.738686 Dram Type= 6, Freq= 0, CH_1, rank 0
1618 09:58:31.745467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1619 09:58:31.745579 ==
1620 09:58:31.745685 DQS Delay:
1621 09:58:31.745777 DQS0 = 0, DQS1 = 0
1622 09:58:31.748574 DQM Delay:
1623 09:58:31.748657 DQM0 = 82, DQM1 = 73
1624 09:58:31.752091 DQ Delay:
1625 09:58:31.755251 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1626 09:58:31.755335 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =69
1627 09:58:31.759192 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1628 09:58:31.762108 DQ12 =85, DQ13 =77, DQ14 =77, DQ15 =77
1629 09:58:31.765807
1630 09:58:31.765890
1631 09:58:31.765956 ==
1632 09:58:31.769049 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 09:58:31.772287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 09:58:31.772371 ==
1635 09:58:31.772439
1636 09:58:31.772501
1637 09:58:31.775874 TX Vref Scan disable
1638 09:58:31.775958 == TX Byte 0 ==
1639 09:58:31.782516 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1640 09:58:31.785513 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1641 09:58:31.785596 == TX Byte 1 ==
1642 09:58:31.792344 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1643 09:58:31.795928 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1644 09:58:31.796014 ==
1645 09:58:31.798782 Dram Type= 6, Freq= 0, CH_1, rank 0
1646 09:58:31.802215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1647 09:58:31.802300 ==
1648 09:58:31.815856 TX Vref=22, minBit 0, minWin=27, winSum=437
1649 09:58:31.818816 TX Vref=24, minBit 0, minWin=27, winSum=439
1650 09:58:31.822460 TX Vref=26, minBit 0, minWin=27, winSum=442
1651 09:58:31.826052 TX Vref=28, minBit 1, minWin=27, winSum=451
1652 09:58:31.829175 TX Vref=30, minBit 11, minWin=27, winSum=451
1653 09:58:31.832845 TX Vref=32, minBit 0, minWin=28, winSum=453
1654 09:58:31.840200 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 32
1655 09:58:31.840295
1656 09:58:31.843308 Final TX Range 1 Vref 32
1657 09:58:31.843388
1658 09:58:31.843453 ==
1659 09:58:31.846258 Dram Type= 6, Freq= 0, CH_1, rank 0
1660 09:58:31.850025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1661 09:58:31.850127 ==
1662 09:58:31.850195
1663 09:58:31.850260
1664 09:58:31.853113 TX Vref Scan disable
1665 09:58:31.856891 == TX Byte 0 ==
1666 09:58:31.859848 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1667 09:58:31.863050 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1668 09:58:31.866759 == TX Byte 1 ==
1669 09:58:31.870029 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1670 09:58:31.873473 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1671 09:58:31.873560
1672 09:58:31.873646 [DATLAT]
1673 09:58:31.876721 Freq=800, CH1 RK0
1674 09:58:31.876833
1675 09:58:31.880253 DATLAT Default: 0xa
1676 09:58:31.880344 0, 0xFFFF, sum = 0
1677 09:58:31.883224 1, 0xFFFF, sum = 0
1678 09:58:31.883306 2, 0xFFFF, sum = 0
1679 09:58:31.886735 3, 0xFFFF, sum = 0
1680 09:58:31.886844 4, 0xFFFF, sum = 0
1681 09:58:31.889974 5, 0xFFFF, sum = 0
1682 09:58:31.890064 6, 0xFFFF, sum = 0
1683 09:58:31.893814 7, 0xFFFF, sum = 0
1684 09:58:31.893911 8, 0xFFFF, sum = 0
1685 09:58:31.896651 9, 0x0, sum = 1
1686 09:58:31.896753 10, 0x0, sum = 2
1687 09:58:31.900407 11, 0x0, sum = 3
1688 09:58:31.900499 12, 0x0, sum = 4
1689 09:58:31.900586 best_step = 10
1690 09:58:31.900665
1691 09:58:31.903549 ==
1692 09:58:31.906851 Dram Type= 6, Freq= 0, CH_1, rank 0
1693 09:58:31.910140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1694 09:58:31.910224 ==
1695 09:58:31.910311 RX Vref Scan: 1
1696 09:58:31.910393
1697 09:58:31.913682 Set Vref Range= 32 -> 127
1698 09:58:31.913766
1699 09:58:31.917033 RX Vref 32 -> 127, step: 1
1700 09:58:31.917136
1701 09:58:31.920407 RX Delay -111 -> 252, step: 8
1702 09:58:31.920506
1703 09:58:31.923751 Set Vref, RX VrefLevel [Byte0]: 32
1704 09:58:31.926743 [Byte1]: 32
1705 09:58:31.926826
1706 09:58:31.930440 Set Vref, RX VrefLevel [Byte0]: 33
1707 09:58:31.933448 [Byte1]: 33
1708 09:58:31.933537
1709 09:58:31.937055 Set Vref, RX VrefLevel [Byte0]: 34
1710 09:58:31.940353 [Byte1]: 34
1711 09:58:31.944012
1712 09:58:31.944105 Set Vref, RX VrefLevel [Byte0]: 35
1713 09:58:31.947205 [Byte1]: 35
1714 09:58:31.951385
1715 09:58:31.951467 Set Vref, RX VrefLevel [Byte0]: 36
1716 09:58:31.955002 [Byte1]: 36
1717 09:58:31.958782
1718 09:58:31.958870 Set Vref, RX VrefLevel [Byte0]: 37
1719 09:58:31.962537 [Byte1]: 37
1720 09:58:31.966880
1721 09:58:31.966973 Set Vref, RX VrefLevel [Byte0]: 38
1722 09:58:31.970090 [Byte1]: 38
1723 09:58:31.974251
1724 09:58:31.974350 Set Vref, RX VrefLevel [Byte0]: 39
1725 09:58:31.977472 [Byte1]: 39
1726 09:58:31.981996
1727 09:58:31.982111 Set Vref, RX VrefLevel [Byte0]: 40
1728 09:58:31.985121 [Byte1]: 40
1729 09:58:31.989938
1730 09:58:31.990027 Set Vref, RX VrefLevel [Byte0]: 41
1731 09:58:31.992878 [Byte1]: 41
1732 09:58:31.997164
1733 09:58:31.997275 Set Vref, RX VrefLevel [Byte0]: 42
1734 09:58:32.000430 [Byte1]: 42
1735 09:58:32.005228
1736 09:58:32.005339 Set Vref, RX VrefLevel [Byte0]: 43
1737 09:58:32.008528 [Byte1]: 43
1738 09:58:32.012860
1739 09:58:32.012942 Set Vref, RX VrefLevel [Byte0]: 44
1740 09:58:32.015761 [Byte1]: 44
1741 09:58:32.020279
1742 09:58:32.020385 Set Vref, RX VrefLevel [Byte0]: 45
1743 09:58:32.023717 [Byte1]: 45
1744 09:58:32.027769
1745 09:58:32.027878 Set Vref, RX VrefLevel [Byte0]: 46
1746 09:58:32.031162 [Byte1]: 46
1747 09:58:32.035784
1748 09:58:32.035871 Set Vref, RX VrefLevel [Byte0]: 47
1749 09:58:32.038760 [Byte1]: 47
1750 09:58:32.042857
1751 09:58:32.042952 Set Vref, RX VrefLevel [Byte0]: 48
1752 09:58:32.046269 [Byte1]: 48
1753 09:58:32.050609
1754 09:58:32.050714 Set Vref, RX VrefLevel [Byte0]: 49
1755 09:58:32.054366 [Byte1]: 49
1756 09:58:32.058620
1757 09:58:32.058732 Set Vref, RX VrefLevel [Byte0]: 50
1758 09:58:32.061540 [Byte1]: 50
1759 09:58:32.065865
1760 09:58:32.065986 Set Vref, RX VrefLevel [Byte0]: 51
1761 09:58:32.069602 [Byte1]: 51
1762 09:58:32.074173
1763 09:58:32.074282 Set Vref, RX VrefLevel [Byte0]: 52
1764 09:58:32.077093 [Byte1]: 52
1765 09:58:32.081336
1766 09:58:32.081447 Set Vref, RX VrefLevel [Byte0]: 53
1767 09:58:32.085028 [Byte1]: 53
1768 09:58:32.088857
1769 09:58:32.088982 Set Vref, RX VrefLevel [Byte0]: 54
1770 09:58:32.092379 [Byte1]: 54
1771 09:58:32.096712
1772 09:58:32.096826 Set Vref, RX VrefLevel [Byte0]: 55
1773 09:58:32.099795 [Byte1]: 55
1774 09:58:32.104581
1775 09:58:32.104718 Set Vref, RX VrefLevel [Byte0]: 56
1776 09:58:32.107752 [Byte1]: 56
1777 09:58:32.112018
1778 09:58:32.112094 Set Vref, RX VrefLevel [Byte0]: 57
1779 09:58:32.115205 [Byte1]: 57
1780 09:58:32.119496
1781 09:58:32.119572 Set Vref, RX VrefLevel [Byte0]: 58
1782 09:58:32.123275 [Byte1]: 58
1783 09:58:32.127161
1784 09:58:32.127235 Set Vref, RX VrefLevel [Byte0]: 59
1785 09:58:32.130755 [Byte1]: 59
1786 09:58:32.134824
1787 09:58:32.134920 Set Vref, RX VrefLevel [Byte0]: 60
1788 09:58:32.138071 [Byte1]: 60
1789 09:58:32.142835
1790 09:58:32.142924 Set Vref, RX VrefLevel [Byte0]: 61
1791 09:58:32.146157 [Byte1]: 61
1792 09:58:32.150001
1793 09:58:32.150079 Set Vref, RX VrefLevel [Byte0]: 62
1794 09:58:32.153409 [Byte1]: 62
1795 09:58:32.157926
1796 09:58:32.158032 Set Vref, RX VrefLevel [Byte0]: 63
1797 09:58:32.161737 [Byte1]: 63
1798 09:58:32.165475
1799 09:58:32.165552 Set Vref, RX VrefLevel [Byte0]: 64
1800 09:58:32.168757 [Byte1]: 64
1801 09:58:32.172953
1802 09:58:32.173031 Set Vref, RX VrefLevel [Byte0]: 65
1803 09:58:32.176795 [Byte1]: 65
1804 09:58:32.180537
1805 09:58:32.180619 Set Vref, RX VrefLevel [Byte0]: 66
1806 09:58:32.184173 [Byte1]: 66
1807 09:58:32.188451
1808 09:58:32.188545 Set Vref, RX VrefLevel [Byte0]: 67
1809 09:58:32.192109 [Byte1]: 67
1810 09:58:32.196416
1811 09:58:32.196501 Set Vref, RX VrefLevel [Byte0]: 68
1812 09:58:32.199259 [Byte1]: 68
1813 09:58:32.203730
1814 09:58:32.203841 Set Vref, RX VrefLevel [Byte0]: 69
1815 09:58:32.207210 [Byte1]: 69
1816 09:58:32.211661
1817 09:58:32.211753 Set Vref, RX VrefLevel [Byte0]: 70
1818 09:58:32.214719 [Byte1]: 70
1819 09:58:32.218952
1820 09:58:32.219033 Set Vref, RX VrefLevel [Byte0]: 71
1821 09:58:32.222699 [Byte1]: 71
1822 09:58:32.226481
1823 09:58:32.226583 Set Vref, RX VrefLevel [Byte0]: 72
1824 09:58:32.230128 [Byte1]: 72
1825 09:58:32.234479
1826 09:58:32.234593 Set Vref, RX VrefLevel [Byte0]: 73
1827 09:58:32.237490 [Byte1]: 73
1828 09:58:32.242048
1829 09:58:32.242127 Set Vref, RX VrefLevel [Byte0]: 74
1830 09:58:32.245249 [Byte1]: 74
1831 09:58:32.249552
1832 09:58:32.249630 Set Vref, RX VrefLevel [Byte0]: 75
1833 09:58:32.253254 [Byte1]: 75
1834 09:58:32.257501
1835 09:58:32.257613 Set Vref, RX VrefLevel [Byte0]: 76
1836 09:58:32.260475 [Byte1]: 76
1837 09:58:32.264941
1838 09:58:32.265048 Set Vref, RX VrefLevel [Byte0]: 77
1839 09:58:32.268032 [Byte1]: 77
1840 09:58:32.272694
1841 09:58:32.272785 Set Vref, RX VrefLevel [Byte0]: 78
1842 09:58:32.275605 [Byte1]: 78
1843 09:58:32.280497
1844 09:58:32.280580 Final RX Vref Byte 0 = 61 to rank0
1845 09:58:32.283596 Final RX Vref Byte 1 = 57 to rank0
1846 09:58:32.286812 Final RX Vref Byte 0 = 61 to rank1
1847 09:58:32.290380 Final RX Vref Byte 1 = 57 to rank1==
1848 09:58:32.293950 Dram Type= 6, Freq= 0, CH_1, rank 0
1849 09:58:32.297060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1850 09:58:32.300100 ==
1851 09:58:32.300181 DQS Delay:
1852 09:58:32.300270 DQS0 = 0, DQS1 = 0
1853 09:58:32.303632 DQM Delay:
1854 09:58:32.303752 DQM0 = 83, DQM1 = 73
1855 09:58:32.306748 DQ Delay:
1856 09:58:32.310404 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =84
1857 09:58:32.310509 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =80
1858 09:58:32.313963 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =68
1859 09:58:32.317097 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =76
1860 09:58:32.317205
1861 09:58:32.320084
1862 09:58:32.326909 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c02, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
1863 09:58:32.330189 CH1 RK0: MR19=606, MR18=2C02
1864 09:58:32.337060 CH1_RK0: MR19=0x606, MR18=0x2C02, DQSOSC=398, MR23=63, INC=93, DEC=62
1865 09:58:32.337175
1866 09:58:32.340192 ----->DramcWriteLeveling(PI) begin...
1867 09:58:32.340307 ==
1868 09:58:32.343855 Dram Type= 6, Freq= 0, CH_1, rank 1
1869 09:58:32.346716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1870 09:58:32.346830 ==
1871 09:58:32.350187 Write leveling (Byte 0): 28 => 28
1872 09:58:32.353998 Write leveling (Byte 1): 28 => 28
1873 09:58:32.357009 DramcWriteLeveling(PI) end<-----
1874 09:58:32.357124
1875 09:58:32.357221 ==
1876 09:58:32.360106 Dram Type= 6, Freq= 0, CH_1, rank 1
1877 09:58:32.363887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1878 09:58:32.364001 ==
1879 09:58:32.367037 [Gating] SW mode calibration
1880 09:58:32.373832 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1881 09:58:32.380315 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1882 09:58:32.383820 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1883 09:58:32.387484 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1884 09:58:32.393668 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1885 09:58:32.397181 0 6 12 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1886 09:58:32.400531 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 09:58:32.403844 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 09:58:32.411007 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 09:58:32.413986 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 09:58:32.417095 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 09:58:32.424019 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 09:58:32.427661 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 09:58:32.430715 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1894 09:58:32.437492 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1895 09:58:32.440734 0 7 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1896 09:58:32.444454 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 09:58:32.450596 0 7 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1898 09:58:32.454313 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 1)
1899 09:58:32.457853 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1900 09:58:32.461308 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 09:58:32.467482 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 09:58:32.470718 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 09:58:32.474418 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 09:58:32.481114 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 09:58:32.484467 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 09:58:32.487988 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 09:58:32.494210 0 9 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1908 09:58:32.497894 0 9 8 | B1->B0 | 2a2a 3434 | 1 1 | (0 0) (1 1)
1909 09:58:32.500975 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1910 09:58:32.508120 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1911 09:58:32.511522 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1912 09:58:32.514555 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1913 09:58:32.521857 0 9 28 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1914 09:58:32.524665 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1915 09:58:32.528283 0 10 4 | B1->B0 | 3030 2b2b | 0 0 | (0 1) (0 0)
1916 09:58:32.531316 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1917 09:58:32.538264 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 09:58:32.541397 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 09:58:32.545111 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 09:58:32.551949 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 09:58:32.554908 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 09:58:32.558765 0 11 0 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
1923 09:58:32.565328 0 11 4 | B1->B0 | 2b2b 2f2f | 0 0 | (0 0) (0 0)
1924 09:58:32.568473 0 11 8 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
1925 09:58:32.572158 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 09:58:32.575734 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 09:58:32.581915 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 09:58:32.585716 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 09:58:32.588722 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 09:58:32.595653 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1931 09:58:32.598942 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1932 09:58:32.601947 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 09:58:32.608876 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 09:58:32.611990 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 09:58:32.615576 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 09:58:32.621943 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 09:58:32.625574 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 09:58:32.629062 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 09:58:32.635779 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 09:58:32.639231 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 09:58:32.642709 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 09:58:32.645806 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 09:58:32.652083 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 09:58:32.655942 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 09:58:32.658916 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 09:58:32.665923 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 09:58:32.668980 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1948 09:58:32.672618 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1949 09:58:32.675507 Total UI for P1: 0, mck2ui 16
1950 09:58:32.679295 best dqsien dly found for B1: ( 0, 14, 6)
1951 09:58:32.685915 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1952 09:58:32.686041 Total UI for P1: 0, mck2ui 16
1953 09:58:32.688982 best dqsien dly found for B0: ( 0, 14, 6)
1954 09:58:32.695672 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1955 09:58:32.699237 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1956 09:58:32.699349
1957 09:58:32.702553 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1958 09:58:32.706237 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1959 09:58:32.709266 [Gating] SW calibration Done
1960 09:58:32.709354 ==
1961 09:58:32.712971 Dram Type= 6, Freq= 0, CH_1, rank 1
1962 09:58:32.716031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1963 09:58:32.716115 ==
1964 09:58:32.716181 RX Vref Scan: 0
1965 09:58:32.716243
1966 09:58:32.719261 RX Vref 0 -> 0, step: 1
1967 09:58:32.719373
1968 09:58:32.722790 RX Delay -130 -> 252, step: 16
1969 09:58:32.726306 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1970 09:58:32.729712 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1971 09:58:32.736334 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1972 09:58:32.740020 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1973 09:58:32.742988 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1974 09:58:32.746450 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1975 09:58:32.749388 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1976 09:58:32.753201 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1977 09:58:32.760062 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1978 09:58:32.763210 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1979 09:58:32.766260 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1980 09:58:32.770111 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1981 09:58:32.773156 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1982 09:58:32.780074 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1983 09:58:32.783137 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1984 09:58:32.787013 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1985 09:58:32.787100 ==
1986 09:58:32.789923 Dram Type= 6, Freq= 0, CH_1, rank 1
1987 09:58:32.793369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1988 09:58:32.793459 ==
1989 09:58:32.796730 DQS Delay:
1990 09:58:32.796815 DQS0 = 0, DQS1 = 0
1991 09:58:32.799761 DQM Delay:
1992 09:58:32.799872 DQM0 = 80, DQM1 = 76
1993 09:58:32.799966 DQ Delay:
1994 09:58:32.803499 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1995 09:58:32.806585 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =69
1996 09:58:32.809921 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1997 09:58:32.813524 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1998 09:58:32.813606
1999 09:58:32.813691
2000 09:58:32.813771 ==
2001 09:58:32.817049 Dram Type= 6, Freq= 0, CH_1, rank 1
2002 09:58:32.823236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2003 09:58:32.823359 ==
2004 09:58:32.823467
2005 09:58:32.823568
2006 09:58:32.823664 TX Vref Scan disable
2007 09:58:32.827473 == TX Byte 0 ==
2008 09:58:32.830434 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2009 09:58:32.837497 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2010 09:58:32.837583 == TX Byte 1 ==
2011 09:58:32.840586 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2012 09:58:32.843849 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2013 09:58:32.847373 ==
2014 09:58:32.851143 Dram Type= 6, Freq= 0, CH_1, rank 1
2015 09:58:32.854060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2016 09:58:32.854149 ==
2017 09:58:32.866318 TX Vref=22, minBit 1, minWin=27, winSum=444
2018 09:58:32.869500 TX Vref=24, minBit 1, minWin=27, winSum=443
2019 09:58:32.873253 TX Vref=26, minBit 10, minWin=27, winSum=445
2020 09:58:32.876376 TX Vref=28, minBit 12, minWin=27, winSum=449
2021 09:58:32.880057 TX Vref=30, minBit 0, minWin=28, winSum=452
2022 09:58:32.883317 TX Vref=32, minBit 0, minWin=28, winSum=452
2023 09:58:32.890280 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 30
2024 09:58:32.890398
2025 09:58:32.893445 Final TX Range 1 Vref 30
2026 09:58:32.893532
2027 09:58:32.893623 ==
2028 09:58:32.896283 Dram Type= 6, Freq= 0, CH_1, rank 1
2029 09:58:32.899995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2030 09:58:32.900107 ==
2031 09:58:32.900215
2032 09:58:32.900313
2033 09:58:32.903250 TX Vref Scan disable
2034 09:58:32.906759 == TX Byte 0 ==
2035 09:58:32.909790 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2036 09:58:32.913404 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2037 09:58:32.916487 == TX Byte 1 ==
2038 09:58:32.920544 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2039 09:58:32.923519 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2040 09:58:32.923605
2041 09:58:32.927145 [DATLAT]
2042 09:58:32.927233 Freq=800, CH1 RK1
2043 09:58:32.927300
2044 09:58:32.930132 DATLAT Default: 0xa
2045 09:58:32.930248 0, 0xFFFF, sum = 0
2046 09:58:32.933157 1, 0xFFFF, sum = 0
2047 09:58:32.933243 2, 0xFFFF, sum = 0
2048 09:58:32.936879 3, 0xFFFF, sum = 0
2049 09:58:32.936969 4, 0xFFFF, sum = 0
2050 09:58:32.940234 5, 0xFFFF, sum = 0
2051 09:58:32.940324 6, 0xFFFF, sum = 0
2052 09:58:32.943507 7, 0xFFFF, sum = 0
2053 09:58:32.943598 8, 0xFFFF, sum = 0
2054 09:58:32.946583 9, 0x0, sum = 1
2055 09:58:32.946675 10, 0x0, sum = 2
2056 09:58:32.950430 11, 0x0, sum = 3
2057 09:58:32.950521 12, 0x0, sum = 4
2058 09:58:32.953550 best_step = 10
2059 09:58:32.953638
2060 09:58:32.953725 ==
2061 09:58:32.956621 Dram Type= 6, Freq= 0, CH_1, rank 1
2062 09:58:32.960002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2063 09:58:32.960096 ==
2064 09:58:32.963549 RX Vref Scan: 0
2065 09:58:32.963659
2066 09:58:32.963745 RX Vref 0 -> 0, step: 1
2067 09:58:32.963826
2068 09:58:32.966700 RX Delay -111 -> 252, step: 8
2069 09:58:32.973582 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2070 09:58:32.976835 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
2071 09:58:32.979906 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2072 09:58:32.983657 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2073 09:58:32.986832 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2074 09:58:32.990307 iDelay=209, Bit 5, Center 92 (-15 ~ 200) 216
2075 09:58:32.996669 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2076 09:58:33.000255 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2077 09:58:33.003233 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
2078 09:58:33.006945 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2079 09:58:33.010471 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2080 09:58:33.017151 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2081 09:58:33.020110 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2082 09:58:33.023266 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2083 09:58:33.026876 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2084 09:58:33.033349 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2085 09:58:33.033464 ==
2086 09:58:33.036866 Dram Type= 6, Freq= 0, CH_1, rank 1
2087 09:58:33.040456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2088 09:58:33.040570 ==
2089 09:58:33.040674 DQS Delay:
2090 09:58:33.043445 DQS0 = 0, DQS1 = 0
2091 09:58:33.043530 DQM Delay:
2092 09:58:33.046944 DQM0 = 81, DQM1 = 76
2093 09:58:33.047051 DQ Delay:
2094 09:58:33.050517 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2095 09:58:33.053977 DQ4 =84, DQ5 =92, DQ6 =92, DQ7 =76
2096 09:58:33.057085 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
2097 09:58:33.060817 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2098 09:58:33.060928
2099 09:58:33.061030
2100 09:58:33.066864 [DQSOSCAuto] RK1, (LSB)MR18= 0x2530, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
2101 09:58:33.070436 CH1 RK1: MR19=606, MR18=2530
2102 09:58:33.077263 CH1_RK1: MR19=0x606, MR18=0x2530, DQSOSC=397, MR23=63, INC=93, DEC=62
2103 09:58:33.080439 [RxdqsGatingPostProcess] freq 800
2104 09:58:33.084059 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2105 09:58:33.087299 Pre-setting of DQS Precalculation
2106 09:58:33.094044 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2107 09:58:33.100425 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2108 09:58:33.107319 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2109 09:58:33.107434
2110 09:58:33.107530
2111 09:58:33.110423 [Calibration Summary] 1600 Mbps
2112 09:58:33.110526 CH 0, Rank 0
2113 09:58:33.114206 SW Impedance : PASS
2114 09:58:33.117190 DUTY Scan : NO K
2115 09:58:33.117297 ZQ Calibration : PASS
2116 09:58:33.120862 Jitter Meter : NO K
2117 09:58:33.123803 CBT Training : PASS
2118 09:58:33.123914 Write leveling : PASS
2119 09:58:33.127723 RX DQS gating : PASS
2120 09:58:33.131239 RX DQ/DQS(RDDQC) : PASS
2121 09:58:33.131364 TX DQ/DQS : PASS
2122 09:58:33.134231 RX DATLAT : PASS
2123 09:58:33.134342 RX DQ/DQS(Engine): PASS
2124 09:58:33.137265 TX OE : NO K
2125 09:58:33.137378 All Pass.
2126 09:58:33.137483
2127 09:58:33.140901 CH 0, Rank 1
2128 09:58:33.141020 SW Impedance : PASS
2129 09:58:33.144424 DUTY Scan : NO K
2130 09:58:33.147491 ZQ Calibration : PASS
2131 09:58:33.147599 Jitter Meter : NO K
2132 09:58:33.150748 CBT Training : PASS
2133 09:58:33.154175 Write leveling : PASS
2134 09:58:33.154283 RX DQS gating : PASS
2135 09:58:33.157466 RX DQ/DQS(RDDQC) : PASS
2136 09:58:33.160993 TX DQ/DQS : PASS
2137 09:58:33.161104 RX DATLAT : PASS
2138 09:58:33.164465 RX DQ/DQS(Engine): PASS
2139 09:58:33.164617 TX OE : NO K
2140 09:58:33.167576 All Pass.
2141 09:58:33.167685
2142 09:58:33.167779 CH 1, Rank 0
2143 09:58:33.171371 SW Impedance : PASS
2144 09:58:33.171491 DUTY Scan : NO K
2145 09:58:33.175011 ZQ Calibration : PASS
2146 09:58:33.177969 Jitter Meter : NO K
2147 09:58:33.178055 CBT Training : PASS
2148 09:58:33.181135 Write leveling : PASS
2149 09:58:33.184789 RX DQS gating : PASS
2150 09:58:33.184881 RX DQ/DQS(RDDQC) : PASS
2151 09:58:33.187877 TX DQ/DQS : PASS
2152 09:58:33.191209 RX DATLAT : PASS
2153 09:58:33.191326 RX DQ/DQS(Engine): PASS
2154 09:58:33.194631 TX OE : NO K
2155 09:58:33.194743 All Pass.
2156 09:58:33.194838
2157 09:58:33.194934 CH 1, Rank 1
2158 09:58:33.198503 SW Impedance : PASS
2159 09:58:33.201774 DUTY Scan : NO K
2160 09:58:33.201863 ZQ Calibration : PASS
2161 09:58:33.205206 Jitter Meter : NO K
2162 09:58:33.208086 CBT Training : PASS
2163 09:58:33.208196 Write leveling : PASS
2164 09:58:33.211923 RX DQS gating : PASS
2165 09:58:33.214865 RX DQ/DQS(RDDQC) : PASS
2166 09:58:33.214971 TX DQ/DQS : PASS
2167 09:58:33.218160 RX DATLAT : PASS
2168 09:58:33.221967 RX DQ/DQS(Engine): PASS
2169 09:58:33.222046 TX OE : NO K
2170 09:58:33.222111 All Pass.
2171 09:58:33.224917
2172 09:58:33.225009 DramC Write-DBI off
2173 09:58:33.228628 PER_BANK_REFRESH: Hybrid Mode
2174 09:58:33.228705 TX_TRACKING: ON
2175 09:58:33.231528 [GetDramInforAfterCalByMRR] Vendor 6.
2176 09:58:33.235128 [GetDramInforAfterCalByMRR] Revision 606.
2177 09:58:33.242097 [GetDramInforAfterCalByMRR] Revision 2 0.
2178 09:58:33.242181 MR0 0x3b3b
2179 09:58:33.242265 MR8 0x5151
2180 09:58:33.244895 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2181 09:58:33.244981
2182 09:58:33.248679 MR0 0x3b3b
2183 09:58:33.248802 MR8 0x5151
2184 09:58:33.251533 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2185 09:58:33.251643
2186 09:58:33.262122 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2187 09:58:33.265587 [FAST_K] Save calibration result to emmc
2188 09:58:33.268336 [FAST_K] Save calibration result to emmc
2189 09:58:33.271917 dram_init: config_dvfs: 1
2190 09:58:33.275580 dramc_set_vcore_voltage set vcore to 662500
2191 09:58:33.275700 Read voltage for 1200, 2
2192 09:58:33.278938 Vio18 = 0
2193 09:58:33.279039 Vcore = 662500
2194 09:58:33.279105 Vdram = 0
2195 09:58:33.282374 Vddq = 0
2196 09:58:33.282481 Vmddr = 0
2197 09:58:33.285391 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2198 09:58:33.292436 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2199 09:58:33.295468 MEM_TYPE=3, freq_sel=15
2200 09:58:33.298714 sv_algorithm_assistance_LP4_1600
2201 09:58:33.302571 ============ PULL DRAM RESETB DOWN ============
2202 09:58:33.305498 ========== PULL DRAM RESETB DOWN end =========
2203 09:58:33.309450 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2204 09:58:33.312460 ===================================
2205 09:58:33.315512 LPDDR4 DRAM CONFIGURATION
2206 09:58:33.319212 ===================================
2207 09:58:33.322412 EX_ROW_EN[0] = 0x0
2208 09:58:33.322491 EX_ROW_EN[1] = 0x0
2209 09:58:33.325545 LP4Y_EN = 0x0
2210 09:58:33.325622 WORK_FSP = 0x0
2211 09:58:33.329275 WL = 0x4
2212 09:58:33.329366 RL = 0x4
2213 09:58:33.332590 BL = 0x2
2214 09:58:33.332668 RPST = 0x0
2215 09:58:33.335545 RD_PRE = 0x0
2216 09:58:33.335623 WR_PRE = 0x1
2217 09:58:33.339261 WR_PST = 0x0
2218 09:58:33.339339 DBI_WR = 0x0
2219 09:58:33.342257 DBI_RD = 0x0
2220 09:58:33.342333 OTF = 0x1
2221 09:58:33.346215 ===================================
2222 09:58:33.348958 ===================================
2223 09:58:33.352553 ANA top config
2224 09:58:33.356214 ===================================
2225 09:58:33.359082 DLL_ASYNC_EN = 0
2226 09:58:33.359162 ALL_SLAVE_EN = 0
2227 09:58:33.362486 NEW_RANK_MODE = 1
2228 09:58:33.365787 DLL_IDLE_MODE = 1
2229 09:58:33.369219 LP45_APHY_COMB_EN = 1
2230 09:58:33.369330 TX_ODT_DIS = 1
2231 09:58:33.372435 NEW_8X_MODE = 1
2232 09:58:33.375937 ===================================
2233 09:58:33.379311 ===================================
2234 09:58:33.383077 data_rate = 2400
2235 09:58:33.386018 CKR = 1
2236 09:58:33.389287 DQ_P2S_RATIO = 8
2237 09:58:33.392924 ===================================
2238 09:58:33.393042 CA_P2S_RATIO = 8
2239 09:58:33.395824 DQ_CA_OPEN = 0
2240 09:58:33.399590 DQ_SEMI_OPEN = 0
2241 09:58:33.402844 CA_SEMI_OPEN = 0
2242 09:58:33.406145 CA_FULL_RATE = 0
2243 09:58:33.409540 DQ_CKDIV4_EN = 0
2244 09:58:33.409617 CA_CKDIV4_EN = 0
2245 09:58:33.412594 CA_PREDIV_EN = 0
2246 09:58:33.416372 PH8_DLY = 17
2247 09:58:33.419414 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2248 09:58:33.423272 DQ_AAMCK_DIV = 4
2249 09:58:33.426319 CA_AAMCK_DIV = 4
2250 09:58:33.426394 CA_ADMCK_DIV = 4
2251 09:58:33.429491 DQ_TRACK_CA_EN = 0
2252 09:58:33.433310 CA_PICK = 1200
2253 09:58:33.436341 CA_MCKIO = 1200
2254 09:58:33.440031 MCKIO_SEMI = 0
2255 09:58:33.443157 PLL_FREQ = 2366
2256 09:58:33.446675 DQ_UI_PI_RATIO = 32
2257 09:58:33.446782 CA_UI_PI_RATIO = 0
2258 09:58:33.449741 ===================================
2259 09:58:33.452807 ===================================
2260 09:58:33.456541 memory_type:LPDDR4
2261 09:58:33.460074 GP_NUM : 10
2262 09:58:33.460150 SRAM_EN : 1
2263 09:58:33.462849 MD32_EN : 0
2264 09:58:33.466753 ===================================
2265 09:58:33.469960 [ANA_INIT] >>>>>>>>>>>>>>
2266 09:58:33.470071 <<<<<< [CONFIGURE PHASE]: ANA_TX
2267 09:58:33.473471 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2268 09:58:33.476819 ===================================
2269 09:58:33.479944 data_rate = 2400,PCW = 0X5b00
2270 09:58:33.483174 ===================================
2271 09:58:33.486772 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2272 09:58:33.493713 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2273 09:58:33.496703 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2274 09:58:33.503449 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2275 09:58:33.506537 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2276 09:58:33.510444 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2277 09:58:33.513327 [ANA_INIT] flow start
2278 09:58:33.513403 [ANA_INIT] PLL >>>>>>>>
2279 09:58:33.517193 [ANA_INIT] PLL <<<<<<<<
2280 09:58:33.520092 [ANA_INIT] MIDPI >>>>>>>>
2281 09:58:33.520167 [ANA_INIT] MIDPI <<<<<<<<
2282 09:58:33.523316 [ANA_INIT] DLL >>>>>>>>
2283 09:58:33.527168 [ANA_INIT] DLL <<<<<<<<
2284 09:58:33.527250 [ANA_INIT] flow end
2285 09:58:33.530588 ============ LP4 DIFF to SE enter ============
2286 09:58:33.537345 ============ LP4 DIFF to SE exit ============
2287 09:58:33.537427 [ANA_INIT] <<<<<<<<<<<<<
2288 09:58:33.540432 [Flow] Enable top DCM control >>>>>
2289 09:58:33.543656 [Flow] Enable top DCM control <<<<<
2290 09:58:33.547416 Enable DLL master slave shuffle
2291 09:58:33.553648 ==============================================================
2292 09:58:33.553735 Gating Mode config
2293 09:58:33.560618 ==============================================================
2294 09:58:33.563755 Config description:
2295 09:58:33.570821 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2296 09:58:33.577493 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2297 09:58:33.584378 SELPH_MODE 0: By rank 1: By Phase
2298 09:58:33.590835 ==============================================================
2299 09:58:33.590943 GAT_TRACK_EN = 1
2300 09:58:33.593981 RX_GATING_MODE = 2
2301 09:58:33.597305 RX_GATING_TRACK_MODE = 2
2302 09:58:33.600733 SELPH_MODE = 1
2303 09:58:33.604039 PICG_EARLY_EN = 1
2304 09:58:33.607513 VALID_LAT_VALUE = 1
2305 09:58:33.614348 ==============================================================
2306 09:58:33.617320 Enter into Gating configuration >>>>
2307 09:58:33.620981 Exit from Gating configuration <<<<
2308 09:58:33.624237 Enter into DVFS_PRE_config >>>>>
2309 09:58:33.634174 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2310 09:58:33.638092 Exit from DVFS_PRE_config <<<<<
2311 09:58:33.641186 Enter into PICG configuration >>>>
2312 09:58:33.644248 Exit from PICG configuration <<<<
2313 09:58:33.644335 [RX_INPUT] configuration >>>>>
2314 09:58:33.647959 [RX_INPUT] configuration <<<<<
2315 09:58:33.654398 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2316 09:58:33.657854 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2317 09:58:33.664377 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2318 09:58:33.671079 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2319 09:58:33.677941 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2320 09:58:33.684907 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2321 09:58:33.688061 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2322 09:58:33.691240 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2323 09:58:33.694657 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2324 09:58:33.701250 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2325 09:58:33.704675 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2326 09:58:33.707813 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2327 09:58:33.711285 ===================================
2328 09:58:33.714770 LPDDR4 DRAM CONFIGURATION
2329 09:58:33.718064 ===================================
2330 09:58:33.718146 EX_ROW_EN[0] = 0x0
2331 09:58:33.721497 EX_ROW_EN[1] = 0x0
2332 09:58:33.725134 LP4Y_EN = 0x0
2333 09:58:33.725219 WORK_FSP = 0x0
2334 09:58:33.728208 WL = 0x4
2335 09:58:33.728292 RL = 0x4
2336 09:58:33.731326 BL = 0x2
2337 09:58:33.731411 RPST = 0x0
2338 09:58:33.735051 RD_PRE = 0x0
2339 09:58:33.735135 WR_PRE = 0x1
2340 09:58:33.738273 WR_PST = 0x0
2341 09:58:33.738357 DBI_WR = 0x0
2342 09:58:33.741572 DBI_RD = 0x0
2343 09:58:33.741656 OTF = 0x1
2344 09:58:33.745452 ===================================
2345 09:58:33.748586 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2346 09:58:33.754829 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2347 09:58:33.758485 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2348 09:58:33.761679 ===================================
2349 09:58:33.765026 LPDDR4 DRAM CONFIGURATION
2350 09:58:33.768265 ===================================
2351 09:58:33.768351 EX_ROW_EN[0] = 0x10
2352 09:58:33.772069 EX_ROW_EN[1] = 0x0
2353 09:58:33.772153 LP4Y_EN = 0x0
2354 09:58:33.775230 WORK_FSP = 0x0
2355 09:58:33.775343 WL = 0x4
2356 09:58:33.778325 RL = 0x4
2357 09:58:33.778409 BL = 0x2
2358 09:58:33.781489 RPST = 0x0
2359 09:58:33.781573 RD_PRE = 0x0
2360 09:58:33.785288 WR_PRE = 0x1
2361 09:58:33.785371 WR_PST = 0x0
2362 09:58:33.788365 DBI_WR = 0x0
2363 09:58:33.788449 DBI_RD = 0x0
2364 09:58:33.791570 OTF = 0x1
2365 09:58:33.795077 ===================================
2366 09:58:33.801712 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2367 09:58:33.801843 ==
2368 09:58:33.805084 Dram Type= 6, Freq= 0, CH_0, rank 0
2369 09:58:33.808483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2370 09:58:33.808567 ==
2371 09:58:33.811885 [Duty_Offset_Calibration]
2372 09:58:33.811967 B0:2 B1:-1 CA:1
2373 09:58:33.812047
2374 09:58:33.815237 [DutyScan_Calibration_Flow] k_type=0
2375 09:58:33.825219
2376 09:58:33.825304 ==CLK 0==
2377 09:58:33.828657 Final CLK duty delay cell = -4
2378 09:58:33.831658 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2379 09:58:33.835326 [-4] MIN Duty = 4875%(X100), DQS PI = 32
2380 09:58:33.838858 [-4] AVG Duty = 4953%(X100)
2381 09:58:33.838964
2382 09:58:33.841820 CH0 CLK Duty spec in!! Max-Min= 156%
2383 09:58:33.845525 [DutyScan_Calibration_Flow] ====Done====
2384 09:58:33.845621
2385 09:58:33.848663 [DutyScan_Calibration_Flow] k_type=1
2386 09:58:33.862942
2387 09:58:33.863041 ==DQS 0 ==
2388 09:58:33.866630 Final DQS duty delay cell = -4
2389 09:58:33.870271 [-4] MAX Duty = 5000%(X100), DQS PI = 44
2390 09:58:33.873304 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2391 09:58:33.876422 [-4] AVG Duty = 4938%(X100)
2392 09:58:33.876505
2393 09:58:33.876569 ==DQS 1 ==
2394 09:58:33.880166 Final DQS duty delay cell = -4
2395 09:58:33.883392 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2396 09:58:33.886376 [-4] MIN Duty = 5000%(X100), DQS PI = 44
2397 09:58:33.890114 [-4] AVG Duty = 5062%(X100)
2398 09:58:33.890212
2399 09:58:33.894067 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2400 09:58:33.894188
2401 09:58:33.896898 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2402 09:58:33.899999 [DutyScan_Calibration_Flow] ====Done====
2403 09:58:33.900081
2404 09:58:33.903659 [DutyScan_Calibration_Flow] k_type=3
2405 09:58:33.920473
2406 09:58:33.920571 ==DQM 0 ==
2407 09:58:33.923793 Final DQM duty delay cell = 0
2408 09:58:33.926846 [0] MAX Duty = 5031%(X100), DQS PI = 54
2409 09:58:33.930465 [0] MIN Duty = 4907%(X100), DQS PI = 2
2410 09:58:33.930549 [0] AVG Duty = 4969%(X100)
2411 09:58:33.933408
2412 09:58:33.933491 ==DQM 1 ==
2413 09:58:33.936955 Final DQM duty delay cell = 0
2414 09:58:33.940336 [0] MAX Duty = 5156%(X100), DQS PI = 62
2415 09:58:33.944073 [0] MIN Duty = 4969%(X100), DQS PI = 10
2416 09:58:33.944153 [0] AVG Duty = 5062%(X100)
2417 09:58:33.947167
2418 09:58:33.950270 CH0 DQM 0 Duty spec in!! Max-Min= 124%
2419 09:58:33.950368
2420 09:58:33.953754 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2421 09:58:33.957340 [DutyScan_Calibration_Flow] ====Done====
2422 09:58:33.957450
2423 09:58:33.960367 [DutyScan_Calibration_Flow] k_type=2
2424 09:58:33.975984
2425 09:58:33.976121 ==DQ 0 ==
2426 09:58:33.979540 Final DQ duty delay cell = -4
2427 09:58:33.983122 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2428 09:58:33.986153 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2429 09:58:33.989272 [-4] AVG Duty = 4969%(X100)
2430 09:58:33.989349
2431 09:58:33.989413 ==DQ 1 ==
2432 09:58:33.993072 Final DQ duty delay cell = 0
2433 09:58:33.996300 [0] MAX Duty = 5031%(X100), DQS PI = 18
2434 09:58:34.000042 [0] MIN Duty = 4907%(X100), DQS PI = 46
2435 09:58:34.000128 [0] AVG Duty = 4969%(X100)
2436 09:58:34.000195
2437 09:58:34.003168 CH0 DQ 0 Duty spec in!! Max-Min= 186%
2438 09:58:34.006701
2439 09:58:34.009691 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2440 09:58:34.013262 [DutyScan_Calibration_Flow] ====Done====
2441 09:58:34.013363 ==
2442 09:58:34.016365 Dram Type= 6, Freq= 0, CH_1, rank 0
2443 09:58:34.019959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2444 09:58:34.020037 ==
2445 09:58:34.022843 [Duty_Offset_Calibration]
2446 09:58:34.022963 B0:1 B1:1 CA:2
2447 09:58:34.023051
2448 09:58:34.026326 [DutyScan_Calibration_Flow] k_type=0
2449 09:58:34.036566
2450 09:58:34.036644 ==CLK 0==
2451 09:58:34.039977 Final CLK duty delay cell = 0
2452 09:58:34.042924 [0] MAX Duty = 5187%(X100), DQS PI = 24
2453 09:58:34.046494 [0] MIN Duty = 4969%(X100), DQS PI = 40
2454 09:58:34.046579 [0] AVG Duty = 5078%(X100)
2455 09:58:34.049956
2456 09:58:34.050038 CH1 CLK Duty spec in!! Max-Min= 218%
2457 09:58:34.056760 [DutyScan_Calibration_Flow] ====Done====
2458 09:58:34.056843
2459 09:58:34.060137 [DutyScan_Calibration_Flow] k_type=1
2460 09:58:34.075655
2461 09:58:34.075738 ==DQS 0 ==
2462 09:58:34.078825 Final DQS duty delay cell = 0
2463 09:58:34.082329 [0] MAX Duty = 5031%(X100), DQS PI = 18
2464 09:58:34.085900 [0] MIN Duty = 4844%(X100), DQS PI = 48
2465 09:58:34.085983 [0] AVG Duty = 4937%(X100)
2466 09:58:34.089012
2467 09:58:34.089095 ==DQS 1 ==
2468 09:58:34.092384 Final DQS duty delay cell = 0
2469 09:58:34.095656 [0] MAX Duty = 5031%(X100), DQS PI = 36
2470 09:58:34.099383 [0] MIN Duty = 4907%(X100), DQS PI = 8
2471 09:58:34.099478 [0] AVG Duty = 4969%(X100)
2472 09:58:34.099547
2473 09:58:34.105569 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2474 09:58:34.105686
2475 09:58:34.109314 CH1 DQS 1 Duty spec in!! Max-Min= 124%
2476 09:58:34.112980 [DutyScan_Calibration_Flow] ====Done====
2477 09:58:34.113062
2478 09:58:34.116020 [DutyScan_Calibration_Flow] k_type=3
2479 09:58:34.132065
2480 09:58:34.132147 ==DQM 0 ==
2481 09:58:34.135584 Final DQM duty delay cell = 0
2482 09:58:34.138831 [0] MAX Duty = 5093%(X100), DQS PI = 18
2483 09:58:34.142214 [0] MIN Duty = 4907%(X100), DQS PI = 44
2484 09:58:34.142296 [0] AVG Duty = 5000%(X100)
2485 09:58:34.145602
2486 09:58:34.145684 ==DQM 1 ==
2487 09:58:34.148787 Final DQM duty delay cell = 0
2488 09:58:34.152226 [0] MAX Duty = 5156%(X100), DQS PI = 62
2489 09:58:34.155595 [0] MIN Duty = 4938%(X100), DQS PI = 24
2490 09:58:34.155676 [0] AVG Duty = 5047%(X100)
2491 09:58:34.159172
2492 09:58:34.162181 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2493 09:58:34.162263
2494 09:58:34.166008 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2495 09:58:34.169239 [DutyScan_Calibration_Flow] ====Done====
2496 09:58:34.169322
2497 09:58:34.172182 [DutyScan_Calibration_Flow] k_type=2
2498 09:58:34.189075
2499 09:58:34.189160 ==DQ 0 ==
2500 09:58:34.192028 Final DQ duty delay cell = 0
2501 09:58:34.195130 [0] MAX Duty = 5156%(X100), DQS PI = 18
2502 09:58:34.198699 [0] MIN Duty = 4938%(X100), DQS PI = 14
2503 09:58:34.198812 [0] AVG Duty = 5047%(X100)
2504 09:58:34.201780
2505 09:58:34.201859 ==DQ 1 ==
2506 09:58:34.205514 Final DQ duty delay cell = 0
2507 09:58:34.208615 [0] MAX Duty = 5124%(X100), DQS PI = 56
2508 09:58:34.212562 [0] MIN Duty = 5031%(X100), DQS PI = 2
2509 09:58:34.212645 [0] AVG Duty = 5077%(X100)
2510 09:58:34.212737
2511 09:58:34.215509 CH1 DQ 0 Duty spec in!! Max-Min= 218%
2512 09:58:34.215594
2513 09:58:34.219182 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2514 09:58:34.222260 [DutyScan_Calibration_Flow] ====Done====
2515 09:58:34.227410 nWR fixed to 30
2516 09:58:34.231062 [ModeRegInit_LP4] CH0 RK0
2517 09:58:34.231154 [ModeRegInit_LP4] CH0 RK1
2518 09:58:34.234812 [ModeRegInit_LP4] CH1 RK0
2519 09:58:34.237867 [ModeRegInit_LP4] CH1 RK1
2520 09:58:34.237971 match AC timing 7
2521 09:58:34.244295 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2522 09:58:34.247748 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2523 09:58:34.251254 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2524 09:58:34.257965 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2525 09:58:34.261471 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2526 09:58:34.261579 ==
2527 09:58:34.264730 Dram Type= 6, Freq= 0, CH_0, rank 0
2528 09:58:34.267813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2529 09:58:34.267940 ==
2530 09:58:34.274638 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2531 09:58:34.281248 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2532 09:58:34.288600 [CA 0] Center 40 (10~71) winsize 62
2533 09:58:34.292271 [CA 1] Center 39 (9~70) winsize 62
2534 09:58:34.295470 [CA 2] Center 36 (6~67) winsize 62
2535 09:58:34.299070 [CA 3] Center 36 (5~67) winsize 63
2536 09:58:34.301964 [CA 4] Center 35 (5~65) winsize 61
2537 09:58:34.305883 [CA 5] Center 34 (4~64) winsize 61
2538 09:58:34.305990
2539 09:58:34.308923 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2540 09:58:34.309030
2541 09:58:34.312625 [CATrainingPosCal] consider 1 rank data
2542 09:58:34.315491 u2DelayCellTimex100 = 270/100 ps
2543 09:58:34.318677 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2544 09:58:34.322256 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2545 09:58:34.328998 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2546 09:58:34.332662 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2547 09:58:34.335818 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2548 09:58:34.338822 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2549 09:58:34.338952
2550 09:58:34.342419 CA PerBit enable=1, Macro0, CA PI delay=34
2551 09:58:34.342489
2552 09:58:34.345646 [CBTSetCACLKResult] CA Dly = 34
2553 09:58:34.345718 CS Dly: 7 (0~38)
2554 09:58:34.345786 ==
2555 09:58:34.349211 Dram Type= 6, Freq= 0, CH_0, rank 1
2556 09:58:34.355833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2557 09:58:34.355922 ==
2558 09:58:34.359172 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2559 09:58:34.365888 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2560 09:58:34.374795 [CA 0] Center 39 (9~70) winsize 62
2561 09:58:34.377966 [CA 1] Center 40 (10~70) winsize 61
2562 09:58:34.381066 [CA 2] Center 36 (6~67) winsize 62
2563 09:58:34.384871 [CA 3] Center 36 (5~67) winsize 63
2564 09:58:34.387972 [CA 4] Center 34 (4~65) winsize 62
2565 09:58:34.391613 [CA 5] Center 34 (4~64) winsize 61
2566 09:58:34.391718
2567 09:58:34.394747 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2568 09:58:34.394852
2569 09:58:34.398508 [CATrainingPosCal] consider 2 rank data
2570 09:58:34.401432 u2DelayCellTimex100 = 270/100 ps
2571 09:58:34.405094 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2572 09:58:34.408148 CA1 delay=40 (10~70),Diff = 6 PI (28 cell)
2573 09:58:34.414792 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2574 09:58:34.418551 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2575 09:58:34.421599 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2576 09:58:34.425231 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2577 09:58:34.425320
2578 09:58:34.428167 CA PerBit enable=1, Macro0, CA PI delay=34
2579 09:58:34.428244
2580 09:58:34.431421 [CBTSetCACLKResult] CA Dly = 34
2581 09:58:34.431502 CS Dly: 8 (0~41)
2582 09:58:34.431586
2583 09:58:34.435136 ----->DramcWriteLeveling(PI) begin...
2584 09:58:34.435226 ==
2585 09:58:34.438467 Dram Type= 6, Freq= 0, CH_0, rank 0
2586 09:58:34.445106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2587 09:58:34.445189 ==
2588 09:58:34.448177 Write leveling (Byte 0): 30 => 30
2589 09:58:34.451857 Write leveling (Byte 1): 30 => 30
2590 09:58:34.451938 DramcWriteLeveling(PI) end<-----
2591 09:58:34.452001
2592 09:58:34.454817 ==
2593 09:58:34.458723 Dram Type= 6, Freq= 0, CH_0, rank 0
2594 09:58:34.462080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2595 09:58:34.462162 ==
2596 09:58:34.464972 [Gating] SW mode calibration
2597 09:58:34.472187 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2598 09:58:34.474950 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2599 09:58:34.481924 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2600 09:58:34.485234 0 15 4 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
2601 09:58:34.488748 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2602 09:58:34.495524 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2603 09:58:34.498742 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2604 09:58:34.501807 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2605 09:58:34.505603 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2606 09:58:34.512095 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2607 09:58:34.515710 1 0 0 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
2608 09:58:34.519145 1 0 4 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
2609 09:58:34.525698 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2610 09:58:34.529253 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2611 09:58:34.532218 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2612 09:58:34.539374 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2613 09:58:34.542469 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2614 09:58:34.545627 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2615 09:58:34.552432 1 1 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2616 09:58:34.556090 1 1 4 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
2617 09:58:34.559108 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2618 09:58:34.565873 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 09:58:34.569385 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 09:58:34.572469 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2621 09:58:34.576277 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2622 09:58:34.582630 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2623 09:58:34.586358 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2624 09:58:34.589259 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2625 09:58:34.596382 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 09:58:34.599376 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 09:58:34.603122 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 09:58:34.609292 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 09:58:34.612856 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 09:58:34.616274 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 09:58:34.622569 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 09:58:34.626380 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 09:58:34.629480 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 09:58:34.632582 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 09:58:34.639392 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 09:58:34.643012 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 09:58:34.646143 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 09:58:34.652871 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 09:58:34.656015 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2640 09:58:34.659931 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2641 09:58:34.666614 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2642 09:58:34.666715 Total UI for P1: 0, mck2ui 16
2643 09:58:34.673316 best dqsien dly found for B0: ( 1, 4, 2)
2644 09:58:34.673394 Total UI for P1: 0, mck2ui 16
2645 09:58:34.679494 best dqsien dly found for B1: ( 1, 4, 2)
2646 09:58:34.683003 best DQS0 dly(MCK, UI, PI) = (1, 4, 2)
2647 09:58:34.686436 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2648 09:58:34.686518
2649 09:58:34.690032 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 2)
2650 09:58:34.693078 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2651 09:58:34.696579 [Gating] SW calibration Done
2652 09:58:34.696664 ==
2653 09:58:34.699617 Dram Type= 6, Freq= 0, CH_0, rank 0
2654 09:58:34.703284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2655 09:58:34.703366 ==
2656 09:58:34.703431 RX Vref Scan: 0
2657 09:58:34.703490
2658 09:58:34.707023 RX Vref 0 -> 0, step: 1
2659 09:58:34.707104
2660 09:58:34.710188 RX Delay -40 -> 252, step: 8
2661 09:58:34.713152 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2662 09:58:34.716870 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2663 09:58:34.723621 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2664 09:58:34.727112 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2665 09:58:34.730111 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2666 09:58:34.733730 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2667 09:58:34.736825 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2668 09:58:34.740032 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2669 09:58:34.746873 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2670 09:58:34.750532 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2671 09:58:34.753593 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2672 09:58:34.757224 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2673 09:58:34.760318 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2674 09:58:34.767133 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2675 09:58:34.770292 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2676 09:58:34.773924 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2677 09:58:34.774005 ==
2678 09:58:34.776999 Dram Type= 6, Freq= 0, CH_0, rank 0
2679 09:58:34.780698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2680 09:58:34.780815 ==
2681 09:58:34.783895 DQS Delay:
2682 09:58:34.783976 DQS0 = 0, DQS1 = 0
2683 09:58:34.787349 DQM Delay:
2684 09:58:34.787430 DQM0 = 116, DQM1 = 107
2685 09:58:34.787494 DQ Delay:
2686 09:58:34.790787 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =115
2687 09:58:34.793674 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2688 09:58:34.797405 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2689 09:58:34.804235 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2690 09:58:34.804317
2691 09:58:34.804381
2692 09:58:34.804439 ==
2693 09:58:34.807264 Dram Type= 6, Freq= 0, CH_0, rank 0
2694 09:58:34.810753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2695 09:58:34.810835 ==
2696 09:58:34.810942
2697 09:58:34.811000
2698 09:58:34.814535 TX Vref Scan disable
2699 09:58:34.814616 == TX Byte 0 ==
2700 09:58:34.820559 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2701 09:58:34.824118 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2702 09:58:34.824199 == TX Byte 1 ==
2703 09:58:34.831272 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2704 09:58:34.834012 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2705 09:58:34.834092 ==
2706 09:58:34.837477 Dram Type= 6, Freq= 0, CH_0, rank 0
2707 09:58:34.840616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2708 09:58:34.840698 ==
2709 09:58:34.853245 TX Vref=22, minBit 1, minWin=24, winSum=415
2710 09:58:34.856393 TX Vref=24, minBit 5, minWin=25, winSum=420
2711 09:58:34.860248 TX Vref=26, minBit 7, minWin=24, winSum=424
2712 09:58:34.863272 TX Vref=28, minBit 1, minWin=26, winSum=429
2713 09:58:34.866607 TX Vref=30, minBit 1, minWin=26, winSum=432
2714 09:58:34.870036 TX Vref=32, minBit 1, minWin=26, winSum=433
2715 09:58:34.876712 [TxChooseVref] Worse bit 1, Min win 26, Win sum 433, Final Vref 32
2716 09:58:34.876796
2717 09:58:34.880126 Final TX Range 1 Vref 32
2718 09:58:34.880216
2719 09:58:34.880306 ==
2720 09:58:34.883211 Dram Type= 6, Freq= 0, CH_0, rank 0
2721 09:58:34.886819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2722 09:58:34.886937 ==
2723 09:58:34.887001
2724 09:58:34.887059
2725 09:58:34.890233 TX Vref Scan disable
2726 09:58:34.893554 == TX Byte 0 ==
2727 09:58:34.896657 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2728 09:58:34.900209 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2729 09:58:34.903829 == TX Byte 1 ==
2730 09:58:34.906838 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2731 09:58:34.909992 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2732 09:58:34.910083
2733 09:58:34.913604 [DATLAT]
2734 09:58:34.913685 Freq=1200, CH0 RK0
2735 09:58:34.913749
2736 09:58:34.916731 DATLAT Default: 0xd
2737 09:58:34.916819 0, 0xFFFF, sum = 0
2738 09:58:34.920309 1, 0xFFFF, sum = 0
2739 09:58:34.920399 2, 0xFFFF, sum = 0
2740 09:58:34.923941 3, 0xFFFF, sum = 0
2741 09:58:34.924023 4, 0xFFFF, sum = 0
2742 09:58:34.927083 5, 0xFFFF, sum = 0
2743 09:58:34.927173 6, 0xFFFF, sum = 0
2744 09:58:34.930820 7, 0xFFFF, sum = 0
2745 09:58:34.930926 8, 0xFFFF, sum = 0
2746 09:58:34.934030 9, 0xFFFF, sum = 0
2747 09:58:34.934111 10, 0xFFFF, sum = 0
2748 09:58:34.937259 11, 0xFFFF, sum = 0
2749 09:58:34.937340 12, 0x0, sum = 1
2750 09:58:34.940859 13, 0x0, sum = 2
2751 09:58:34.940941 14, 0x0, sum = 3
2752 09:58:34.944065 15, 0x0, sum = 4
2753 09:58:34.944146 best_step = 13
2754 09:58:34.944209
2755 09:58:34.944267 ==
2756 09:58:34.947112 Dram Type= 6, Freq= 0, CH_0, rank 0
2757 09:58:34.950631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2758 09:58:34.954179 ==
2759 09:58:34.954259 RX Vref Scan: 1
2760 09:58:34.954323
2761 09:58:34.957651 Set Vref Range= 32 -> 127
2762 09:58:34.957740
2763 09:58:34.957803 RX Vref 32 -> 127, step: 1
2764 09:58:34.960700
2765 09:58:34.960780 RX Delay -21 -> 252, step: 4
2766 09:58:34.960843
2767 09:58:34.964509 Set Vref, RX VrefLevel [Byte0]: 32
2768 09:58:34.967654 [Byte1]: 32
2769 09:58:34.971212
2770 09:58:34.971292 Set Vref, RX VrefLevel [Byte0]: 33
2771 09:58:34.974707 [Byte1]: 33
2772 09:58:34.979437
2773 09:58:34.979525 Set Vref, RX VrefLevel [Byte0]: 34
2774 09:58:34.982537 [Byte1]: 34
2775 09:58:34.987371
2776 09:58:34.987451 Set Vref, RX VrefLevel [Byte0]: 35
2777 09:58:34.990471 [Byte1]: 35
2778 09:58:34.995256
2779 09:58:34.995337 Set Vref, RX VrefLevel [Byte0]: 36
2780 09:58:34.998374 [Byte1]: 36
2781 09:58:35.003168
2782 09:58:35.003245 Set Vref, RX VrefLevel [Byte0]: 37
2783 09:58:35.006291 [Byte1]: 37
2784 09:58:35.010966
2785 09:58:35.011041 Set Vref, RX VrefLevel [Byte0]: 38
2786 09:58:35.014081 [Byte1]: 38
2787 09:58:35.019018
2788 09:58:35.019092 Set Vref, RX VrefLevel [Byte0]: 39
2789 09:58:35.022134 [Byte1]: 39
2790 09:58:35.026763
2791 09:58:35.026855 Set Vref, RX VrefLevel [Byte0]: 40
2792 09:58:35.030486 [Byte1]: 40
2793 09:58:35.034803
2794 09:58:35.034928 Set Vref, RX VrefLevel [Byte0]: 41
2795 09:58:35.037895 [Byte1]: 41
2796 09:58:35.042870
2797 09:58:35.042967 Set Vref, RX VrefLevel [Byte0]: 42
2798 09:58:35.045876 [Byte1]: 42
2799 09:58:35.050819
2800 09:58:35.050939 Set Vref, RX VrefLevel [Byte0]: 43
2801 09:58:35.053735 [Byte1]: 43
2802 09:58:35.058562
2803 09:58:35.058667 Set Vref, RX VrefLevel [Byte0]: 44
2804 09:58:35.062194 [Byte1]: 44
2805 09:58:35.066389
2806 09:58:35.066470 Set Vref, RX VrefLevel [Byte0]: 45
2807 09:58:35.070153 [Byte1]: 45
2808 09:58:35.074583
2809 09:58:35.074664 Set Vref, RX VrefLevel [Byte0]: 46
2810 09:58:35.077460 [Byte1]: 46
2811 09:58:35.082461
2812 09:58:35.082542 Set Vref, RX VrefLevel [Byte0]: 47
2813 09:58:35.086011 [Byte1]: 47
2814 09:58:35.090215
2815 09:58:35.090296 Set Vref, RX VrefLevel [Byte0]: 48
2816 09:58:35.093349 [Byte1]: 48
2817 09:58:35.098294
2818 09:58:35.098381 Set Vref, RX VrefLevel [Byte0]: 49
2819 09:58:35.101291 [Byte1]: 49
2820 09:58:35.105900
2821 09:58:35.105980 Set Vref, RX VrefLevel [Byte0]: 50
2822 09:58:35.109576 [Byte1]: 50
2823 09:58:35.113982
2824 09:58:35.114062 Set Vref, RX VrefLevel [Byte0]: 51
2825 09:58:35.117425 [Byte1]: 51
2826 09:58:35.122380
2827 09:58:35.122460 Set Vref, RX VrefLevel [Byte0]: 52
2828 09:58:35.125695 [Byte1]: 52
2829 09:58:35.129624
2830 09:58:35.129704 Set Vref, RX VrefLevel [Byte0]: 53
2831 09:58:35.133071 [Byte1]: 53
2832 09:58:35.137850
2833 09:58:35.137930 Set Vref, RX VrefLevel [Byte0]: 54
2834 09:58:35.140973 [Byte1]: 54
2835 09:58:35.146037
2836 09:58:35.146117 Set Vref, RX VrefLevel [Byte0]: 55
2837 09:58:35.148984 [Byte1]: 55
2838 09:58:35.153807
2839 09:58:35.153886 Set Vref, RX VrefLevel [Byte0]: 56
2840 09:58:35.156912 [Byte1]: 56
2841 09:58:35.161874
2842 09:58:35.161963 Set Vref, RX VrefLevel [Byte0]: 57
2843 09:58:35.164654 [Byte1]: 57
2844 09:58:35.169818
2845 09:58:35.169898 Set Vref, RX VrefLevel [Byte0]: 58
2846 09:58:35.172893 [Byte1]: 58
2847 09:58:35.177170
2848 09:58:35.177250 Set Vref, RX VrefLevel [Byte0]: 59
2849 09:58:35.181009 [Byte1]: 59
2850 09:58:35.185209
2851 09:58:35.185290 Set Vref, RX VrefLevel [Byte0]: 60
2852 09:58:35.188911 [Byte1]: 60
2853 09:58:35.192967
2854 09:58:35.193080 Set Vref, RX VrefLevel [Byte0]: 61
2855 09:58:35.196582 [Byte1]: 61
2856 09:58:35.201069
2857 09:58:35.201151 Set Vref, RX VrefLevel [Byte0]: 62
2858 09:58:35.204747 [Byte1]: 62
2859 09:58:35.209034
2860 09:58:35.209117 Set Vref, RX VrefLevel [Byte0]: 63
2861 09:58:35.212531 [Byte1]: 63
2862 09:58:35.217282
2863 09:58:35.217364 Set Vref, RX VrefLevel [Byte0]: 64
2864 09:58:35.220239 [Byte1]: 64
2865 09:58:35.225043
2866 09:58:35.225125 Set Vref, RX VrefLevel [Byte0]: 65
2867 09:58:35.228332 [Byte1]: 65
2868 09:58:35.233192
2869 09:58:35.233273 Set Vref, RX VrefLevel [Byte0]: 66
2870 09:58:35.236521 [Byte1]: 66
2871 09:58:35.241207
2872 09:58:35.241288 Set Vref, RX VrefLevel [Byte0]: 67
2873 09:58:35.244162 [Byte1]: 67
2874 09:58:35.248529
2875 09:58:35.248611 Set Vref, RX VrefLevel [Byte0]: 68
2876 09:58:35.252086 [Byte1]: 68
2877 09:58:35.256494
2878 09:58:35.256575 Final RX Vref Byte 0 = 53 to rank0
2879 09:58:35.260317 Final RX Vref Byte 1 = 49 to rank0
2880 09:58:35.263279 Final RX Vref Byte 0 = 53 to rank1
2881 09:58:35.267242 Final RX Vref Byte 1 = 49 to rank1==
2882 09:58:35.270159 Dram Type= 6, Freq= 0, CH_0, rank 0
2883 09:58:35.273314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2884 09:58:35.277306 ==
2885 09:58:35.277388 DQS Delay:
2886 09:58:35.277452 DQS0 = 0, DQS1 = 0
2887 09:58:35.280180 DQM Delay:
2888 09:58:35.280262 DQM0 = 115, DQM1 = 104
2889 09:58:35.283366 DQ Delay:
2890 09:58:35.287055 DQ0 =116, DQ1 =114, DQ2 =112, DQ3 =114
2891 09:58:35.290253 DQ4 =116, DQ5 =108, DQ6 =122, DQ7 =122
2892 09:58:35.293668 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2893 09:58:35.296700 DQ12 =112, DQ13 =108, DQ14 =118, DQ15 =112
2894 09:58:35.296782
2895 09:58:35.296854
2896 09:58:35.303542 [DQSOSCAuto] RK0, (LSB)MR18= 0xfaea, (MSB)MR19= 0x303, tDQSOscB0 = 419 ps tDQSOscB1 = 412 ps
2897 09:58:35.307160 CH0 RK0: MR19=303, MR18=FAEA
2898 09:58:35.313699 CH0_RK0: MR19=0x303, MR18=0xFAEA, DQSOSC=412, MR23=63, INC=38, DEC=25
2899 09:58:35.313777
2900 09:58:35.317268 ----->DramcWriteLeveling(PI) begin...
2901 09:58:35.317346 ==
2902 09:58:35.320448 Dram Type= 6, Freq= 0, CH_0, rank 1
2903 09:58:35.324019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2904 09:58:35.324092 ==
2905 09:58:35.327053 Write leveling (Byte 0): 32 => 32
2906 09:58:35.330839 Write leveling (Byte 1): 29 => 29
2907 09:58:35.333649 DramcWriteLeveling(PI) end<-----
2908 09:58:35.333720
2909 09:58:35.333779 ==
2910 09:58:35.337285 Dram Type= 6, Freq= 0, CH_0, rank 1
2911 09:58:35.340406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2912 09:58:35.340476 ==
2913 09:58:35.344001 [Gating] SW mode calibration
2914 09:58:35.350572 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2915 09:58:35.357311 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2916 09:58:35.361174 0 15 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2917 09:58:35.367303 0 15 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
2918 09:58:35.371015 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2919 09:58:35.374200 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2920 09:58:35.377319 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2921 09:58:35.384029 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2922 09:58:35.387545 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2923 09:58:35.391076 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
2924 09:58:35.397948 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
2925 09:58:35.400927 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2926 09:58:35.404417 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2927 09:58:35.411114 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2928 09:58:35.414724 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2929 09:58:35.417933 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2930 09:58:35.424424 1 0 24 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
2931 09:58:35.427743 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2932 09:58:35.431106 1 1 0 | B1->B0 | 3838 4242 | 0 0 | (0 0) (0 0)
2933 09:58:35.434802 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2934 09:58:35.441884 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 09:58:35.445004 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 09:58:35.447982 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 09:58:35.455071 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 09:58:35.458604 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 09:58:35.461854 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2940 09:58:35.468094 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2941 09:58:35.472042 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2942 09:58:35.474870 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 09:58:35.478806 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 09:58:35.485317 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 09:58:35.488835 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 09:58:35.491810 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 09:58:35.499046 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 09:58:35.501942 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 09:58:35.505078 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 09:58:35.511827 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 09:58:35.515451 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 09:58:35.518359 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 09:58:35.525797 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 09:58:35.528689 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 09:58:35.532011 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2956 09:58:35.535340 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2957 09:58:35.538848 Total UI for P1: 0, mck2ui 16
2958 09:58:35.542012 best dqsien dly found for B0: ( 1, 3, 28)
2959 09:58:35.548620 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2960 09:58:35.552358 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2961 09:58:35.555456 Total UI for P1: 0, mck2ui 16
2962 09:58:35.559093 best dqsien dly found for B1: ( 1, 4, 2)
2963 09:58:35.562292 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2964 09:58:35.565490 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2965 09:58:35.565587
2966 09:58:35.569414 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2967 09:58:35.572317 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2968 09:58:35.576102 [Gating] SW calibration Done
2969 09:58:35.576185 ==
2970 09:58:35.579279 Dram Type= 6, Freq= 0, CH_0, rank 1
2971 09:58:35.582277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2972 09:58:35.586060 ==
2973 09:58:35.586141 RX Vref Scan: 0
2974 09:58:35.586205
2975 09:58:35.589086 RX Vref 0 -> 0, step: 1
2976 09:58:35.589168
2977 09:58:35.589232 RX Delay -40 -> 252, step: 8
2978 09:58:35.595948 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2979 09:58:35.599345 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2980 09:58:35.602597 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2981 09:58:35.606086 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2982 09:58:35.609102 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2983 09:58:35.615887 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2984 09:58:35.619560 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2985 09:58:35.623090 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2986 09:58:35.626162 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2987 09:58:35.629678 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2988 09:58:35.632736 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2989 09:58:35.639818 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2990 09:58:35.642974 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2991 09:58:35.646106 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2992 09:58:35.649644 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2993 09:58:35.652755 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2994 09:58:35.656686 ==
2995 09:58:35.656764 Dram Type= 6, Freq= 0, CH_0, rank 1
2996 09:58:35.663115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2997 09:58:35.663192 ==
2998 09:58:35.663265 DQS Delay:
2999 09:58:35.666465 DQS0 = 0, DQS1 = 0
3000 09:58:35.666540 DQM Delay:
3001 09:58:35.670153 DQM0 = 115, DQM1 = 105
3002 09:58:35.670223 DQ Delay:
3003 09:58:35.673213 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
3004 09:58:35.676613 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
3005 09:58:35.679769 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
3006 09:58:35.683336 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
3007 09:58:35.683411
3008 09:58:35.683477
3009 09:58:35.683537 ==
3010 09:58:35.686645 Dram Type= 6, Freq= 0, CH_0, rank 1
3011 09:58:35.689732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3012 09:58:35.693456 ==
3013 09:58:35.693530
3014 09:58:35.693592
3015 09:58:35.693650 TX Vref Scan disable
3016 09:58:35.696359 == TX Byte 0 ==
3017 09:58:35.700053 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3018 09:58:35.703052 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3019 09:58:35.706761 == TX Byte 1 ==
3020 09:58:35.709850 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3021 09:58:35.713196 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3022 09:58:35.716541 ==
3023 09:58:35.716623 Dram Type= 6, Freq= 0, CH_0, rank 1
3024 09:58:35.723158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3025 09:58:35.723240 ==
3026 09:58:35.734456 TX Vref=22, minBit 0, minWin=25, winSum=422
3027 09:58:35.737944 TX Vref=24, minBit 1, minWin=26, winSum=429
3028 09:58:35.741055 TX Vref=26, minBit 5, minWin=26, winSum=437
3029 09:58:35.744584 TX Vref=28, minBit 2, minWin=26, winSum=438
3030 09:58:35.747628 TX Vref=30, minBit 0, minWin=27, winSum=439
3031 09:58:35.750973 TX Vref=32, minBit 3, minWin=26, winSum=437
3032 09:58:35.758064 [TxChooseVref] Worse bit 0, Min win 27, Win sum 439, Final Vref 30
3033 09:58:35.758146
3034 09:58:35.761147 Final TX Range 1 Vref 30
3035 09:58:35.761218
3036 09:58:35.761278 ==
3037 09:58:35.764851 Dram Type= 6, Freq= 0, CH_0, rank 1
3038 09:58:35.767937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3039 09:58:35.768019 ==
3040 09:58:35.768084
3041 09:58:35.768149
3042 09:58:35.770981 TX Vref Scan disable
3043 09:58:35.774757 == TX Byte 0 ==
3044 09:58:35.777804 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3045 09:58:35.781709 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3046 09:58:35.784560 == TX Byte 1 ==
3047 09:58:35.787676 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3048 09:58:35.791437 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3049 09:58:35.791513
3050 09:58:35.794563 [DATLAT]
3051 09:58:35.794668 Freq=1200, CH0 RK1
3052 09:58:35.794768
3053 09:58:35.798292 DATLAT Default: 0xd
3054 09:58:35.798372 0, 0xFFFF, sum = 0
3055 09:58:35.801453 1, 0xFFFF, sum = 0
3056 09:58:35.801557 2, 0xFFFF, sum = 0
3057 09:58:35.804540 3, 0xFFFF, sum = 0
3058 09:58:35.804628 4, 0xFFFF, sum = 0
3059 09:58:35.808224 5, 0xFFFF, sum = 0
3060 09:58:35.808307 6, 0xFFFF, sum = 0
3061 09:58:35.811479 7, 0xFFFF, sum = 0
3062 09:58:35.811553 8, 0xFFFF, sum = 0
3063 09:58:35.814873 9, 0xFFFF, sum = 0
3064 09:58:35.814959 10, 0xFFFF, sum = 0
3065 09:58:35.817928 11, 0xFFFF, sum = 0
3066 09:58:35.818006 12, 0x0, sum = 1
3067 09:58:35.821476 13, 0x0, sum = 2
3068 09:58:35.821583 14, 0x0, sum = 3
3069 09:58:35.824382 15, 0x0, sum = 4
3070 09:58:35.824468 best_step = 13
3071 09:58:35.824532
3072 09:58:35.824598 ==
3073 09:58:35.828119 Dram Type= 6, Freq= 0, CH_0, rank 1
3074 09:58:35.834527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3075 09:58:35.834642 ==
3076 09:58:35.834735 RX Vref Scan: 0
3077 09:58:35.834827
3078 09:58:35.838118 RX Vref 0 -> 0, step: 1
3079 09:58:35.838194
3080 09:58:35.841412 RX Delay -21 -> 252, step: 4
3081 09:58:35.844690 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3082 09:58:35.848104 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3083 09:58:35.851644 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3084 09:58:35.858419 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3085 09:58:35.861469 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3086 09:58:35.865251 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3087 09:58:35.868318 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3088 09:58:35.871573 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3089 09:58:35.878343 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3090 09:58:35.882046 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3091 09:58:35.885153 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3092 09:58:35.888202 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3093 09:58:35.891816 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3094 09:58:35.898553 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3095 09:58:35.901825 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3096 09:58:35.904877 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3097 09:58:35.904961 ==
3098 09:58:35.908494 Dram Type= 6, Freq= 0, CH_0, rank 1
3099 09:58:35.911648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3100 09:58:35.911733 ==
3101 09:58:35.914955 DQS Delay:
3102 09:58:35.915042 DQS0 = 0, DQS1 = 0
3103 09:58:35.918365 DQM Delay:
3104 09:58:35.918448 DQM0 = 114, DQM1 = 104
3105 09:58:35.918517 DQ Delay:
3106 09:58:35.921926 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3107 09:58:35.925016 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3108 09:58:35.928630 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3109 09:58:35.935018 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =110
3110 09:58:35.935107
3111 09:58:35.935175
3112 09:58:35.941660 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 408 ps
3113 09:58:35.945171 CH0 RK1: MR19=403, MR18=3F4
3114 09:58:35.951834 CH0_RK1: MR19=0x403, MR18=0x3F4, DQSOSC=408, MR23=63, INC=39, DEC=26
3115 09:58:35.955309 [RxdqsGatingPostProcess] freq 1200
3116 09:58:35.958848 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3117 09:58:35.961742 best DQS0 dly(2T, 0.5T) = (0, 12)
3118 09:58:35.965410 best DQS1 dly(2T, 0.5T) = (0, 12)
3119 09:58:35.968530 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3120 09:58:35.971704 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3121 09:58:35.975387 best DQS0 dly(2T, 0.5T) = (0, 11)
3122 09:58:35.978447 best DQS1 dly(2T, 0.5T) = (0, 12)
3123 09:58:35.982005 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3124 09:58:35.985786 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3125 09:58:35.988896 Pre-setting of DQS Precalculation
3126 09:58:35.991884 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3127 09:58:35.991997 ==
3128 09:58:35.995482 Dram Type= 6, Freq= 0, CH_1, rank 0
3129 09:58:35.998920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3130 09:58:35.999009 ==
3131 09:58:36.005823 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3132 09:58:36.012107 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3133 09:58:36.020166 [CA 0] Center 38 (8~68) winsize 61
3134 09:58:36.023150 [CA 1] Center 38 (8~68) winsize 61
3135 09:58:36.026837 [CA 2] Center 35 (5~65) winsize 61
3136 09:58:36.030128 [CA 3] Center 34 (4~65) winsize 62
3137 09:58:36.033114 [CA 4] Center 34 (4~65) winsize 62
3138 09:58:36.036596 [CA 5] Center 34 (4~64) winsize 61
3139 09:58:36.036678
3140 09:58:36.040053 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3141 09:58:36.040164
3142 09:58:36.043626 [CATrainingPosCal] consider 1 rank data
3143 09:58:36.046704 u2DelayCellTimex100 = 270/100 ps
3144 09:58:36.050185 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3145 09:58:36.053038 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3146 09:58:36.057035 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3147 09:58:36.063749 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3148 09:58:36.066663 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3149 09:58:36.070152 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3150 09:58:36.070260
3151 09:58:36.073283 CA PerBit enable=1, Macro0, CA PI delay=34
3152 09:58:36.073365
3153 09:58:36.077150 [CBTSetCACLKResult] CA Dly = 34
3154 09:58:36.077232 CS Dly: 6 (0~37)
3155 09:58:36.077297 ==
3156 09:58:36.080337 Dram Type= 6, Freq= 0, CH_1, rank 1
3157 09:58:36.084003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3158 09:58:36.086757 ==
3159 09:58:36.090461 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3160 09:58:36.097338 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3161 09:58:36.105285 [CA 0] Center 38 (8~68) winsize 61
3162 09:58:36.108974 [CA 1] Center 38 (9~68) winsize 60
3163 09:58:36.112079 [CA 2] Center 34 (4~65) winsize 62
3164 09:58:36.115255 [CA 3] Center 34 (4~65) winsize 62
3165 09:58:36.118942 [CA 4] Center 34 (4~65) winsize 62
3166 09:58:36.122136 [CA 5] Center 33 (3~63) winsize 61
3167 09:58:36.122220
3168 09:58:36.125941 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3169 09:58:36.126025
3170 09:58:36.128927 [CATrainingPosCal] consider 2 rank data
3171 09:58:36.132549 u2DelayCellTimex100 = 270/100 ps
3172 09:58:36.135759 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3173 09:58:36.138897 CA1 delay=38 (9~68),Diff = 5 PI (24 cell)
3174 09:58:36.142392 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3175 09:58:36.149284 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3176 09:58:36.152526 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3177 09:58:36.156139 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3178 09:58:36.156218
3179 09:58:36.159260 CA PerBit enable=1, Macro0, CA PI delay=33
3180 09:58:36.159334
3181 09:58:36.162388 [CBTSetCACLKResult] CA Dly = 33
3182 09:58:36.162471 CS Dly: 7 (0~40)
3183 09:58:36.162541
3184 09:58:36.165988 ----->DramcWriteLeveling(PI) begin...
3185 09:58:36.166074 ==
3186 09:58:36.169013 Dram Type= 6, Freq= 0, CH_1, rank 0
3187 09:58:36.175801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3188 09:58:36.175913 ==
3189 09:58:36.179307 Write leveling (Byte 0): 26 => 26
3190 09:58:36.179389 Write leveling (Byte 1): 30 => 30
3191 09:58:36.182708 DramcWriteLeveling(PI) end<-----
3192 09:58:36.182794
3193 09:58:36.182871 ==
3194 09:58:36.186342 Dram Type= 6, Freq= 0, CH_1, rank 0
3195 09:58:36.192866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3196 09:58:36.192951 ==
3197 09:58:36.195836 [Gating] SW mode calibration
3198 09:58:36.202782 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3199 09:58:36.206437 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3200 09:58:36.212992 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3201 09:58:36.216046 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3202 09:58:36.219801 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3203 09:58:36.222781 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3204 09:58:36.229533 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3205 09:58:36.233076 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3206 09:58:36.236067 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3207 09:58:36.242759 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3208 09:58:36.245902 1 0 0 | B1->B0 | 2525 2e2e | 0 0 | (1 0) (0 1)
3209 09:58:36.249523 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3210 09:58:36.256324 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3211 09:58:36.259351 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3212 09:58:36.263084 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3213 09:58:36.269432 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3214 09:58:36.273250 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3215 09:58:36.276177 1 0 28 | B1->B0 | 2f2f 2727 | 0 0 | (0 0) (0 0)
3216 09:58:36.283395 1 1 0 | B1->B0 | 4141 3434 | 0 0 | (0 0) (0 0)
3217 09:58:36.286450 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3218 09:58:36.289651 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 09:58:36.296652 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 09:58:36.300316 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3221 09:58:36.302933 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 09:58:36.306094 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 09:58:36.313360 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 09:58:36.316401 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3225 09:58:36.320123 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 09:58:36.326486 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 09:58:36.329880 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 09:58:36.333457 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 09:58:36.340227 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 09:58:36.343268 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 09:58:36.346964 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 09:58:36.353738 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 09:58:36.356931 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 09:58:36.359979 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 09:58:36.363657 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 09:58:36.369954 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 09:58:36.373242 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 09:58:36.376638 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 09:58:36.383383 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3240 09:58:36.386882 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3241 09:58:36.390646 Total UI for P1: 0, mck2ui 16
3242 09:58:36.393652 best dqsien dly found for B1: ( 1, 3, 28)
3243 09:58:36.396712 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3244 09:58:36.400583 Total UI for P1: 0, mck2ui 16
3245 09:58:36.403837 best dqsien dly found for B0: ( 1, 3, 30)
3246 09:58:36.407080 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3247 09:58:36.410746 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3248 09:58:36.410851
3249 09:58:36.413974 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3250 09:58:36.420852 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3251 09:58:36.420932 [Gating] SW calibration Done
3252 09:58:36.420997 ==
3253 09:58:36.424205 Dram Type= 6, Freq= 0, CH_1, rank 0
3254 09:58:36.430404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3255 09:58:36.430490 ==
3256 09:58:36.430557 RX Vref Scan: 0
3257 09:58:36.430619
3258 09:58:36.434288 RX Vref 0 -> 0, step: 1
3259 09:58:36.434372
3260 09:58:36.437350 RX Delay -40 -> 252, step: 8
3261 09:58:36.440843 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3262 09:58:36.444337 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3263 09:58:36.447264 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3264 09:58:36.450858 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3265 09:58:36.457595 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3266 09:58:36.460684 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3267 09:58:36.464311 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3268 09:58:36.467393 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3269 09:58:36.471118 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3270 09:58:36.477760 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3271 09:58:36.480660 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3272 09:58:36.484556 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3273 09:58:36.487492 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3274 09:58:36.491045 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3275 09:58:36.497588 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3276 09:58:36.501298 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3277 09:58:36.501384 ==
3278 09:58:36.504339 Dram Type= 6, Freq= 0, CH_1, rank 0
3279 09:58:36.508020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3280 09:58:36.508105 ==
3281 09:58:36.508189 DQS Delay:
3282 09:58:36.511081 DQS0 = 0, DQS1 = 0
3283 09:58:36.511165 DQM Delay:
3284 09:58:36.514683 DQM0 = 116, DQM1 = 109
3285 09:58:36.514793 DQ Delay:
3286 09:58:36.517759 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3287 09:58:36.521479 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3288 09:58:36.524588 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3289 09:58:36.528170 DQ12 =123, DQ13 =115, DQ14 =115, DQ15 =115
3290 09:58:36.528254
3291 09:58:36.528319
3292 09:58:36.531104 ==
3293 09:58:36.534775 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 09:58:36.538032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 09:58:36.538137 ==
3296 09:58:36.538242
3297 09:58:36.538332
3298 09:58:36.541653 TX Vref Scan disable
3299 09:58:36.541754 == TX Byte 0 ==
3300 09:58:36.544673 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3301 09:58:36.551339 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3302 09:58:36.551425 == TX Byte 1 ==
3303 09:58:36.554930 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3304 09:58:36.561648 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3305 09:58:36.561733 ==
3306 09:58:36.564818 Dram Type= 6, Freq= 0, CH_1, rank 0
3307 09:58:36.568273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3308 09:58:36.568358 ==
3309 09:58:36.580032 TX Vref=22, minBit 2, minWin=25, winSum=410
3310 09:58:36.583798 TX Vref=24, minBit 2, minWin=25, winSum=414
3311 09:58:36.586882 TX Vref=26, minBit 1, minWin=26, winSum=421
3312 09:58:36.590304 TX Vref=28, minBit 0, minWin=26, winSum=426
3313 09:58:36.593658 TX Vref=30, minBit 15, minWin=25, winSum=426
3314 09:58:36.597062 TX Vref=32, minBit 11, minWin=25, winSum=424
3315 09:58:36.603488 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 28
3316 09:58:36.603577
3317 09:58:36.607185 Final TX Range 1 Vref 28
3318 09:58:36.607268
3319 09:58:36.607332 ==
3320 09:58:36.610216 Dram Type= 6, Freq= 0, CH_1, rank 0
3321 09:58:36.613887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3322 09:58:36.614027 ==
3323 09:58:36.614122
3324 09:58:36.614212
3325 09:58:36.616897 TX Vref Scan disable
3326 09:58:36.620653 == TX Byte 0 ==
3327 09:58:36.623860 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3328 09:58:36.626868 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3329 09:58:36.630624 == TX Byte 1 ==
3330 09:58:36.633673 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3331 09:58:36.637273 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3332 09:58:36.637356
3333 09:58:36.640920 [DATLAT]
3334 09:58:36.641018 Freq=1200, CH1 RK0
3335 09:58:36.641156
3336 09:58:36.643871 DATLAT Default: 0xd
3337 09:58:36.643953 0, 0xFFFF, sum = 0
3338 09:58:36.647509 1, 0xFFFF, sum = 0
3339 09:58:36.647592 2, 0xFFFF, sum = 0
3340 09:58:36.650642 3, 0xFFFF, sum = 0
3341 09:58:36.650726 4, 0xFFFF, sum = 0
3342 09:58:36.653675 5, 0xFFFF, sum = 0
3343 09:58:36.653759 6, 0xFFFF, sum = 0
3344 09:58:36.657204 7, 0xFFFF, sum = 0
3345 09:58:36.657290 8, 0xFFFF, sum = 0
3346 09:58:36.660822 9, 0xFFFF, sum = 0
3347 09:58:36.660905 10, 0xFFFF, sum = 0
3348 09:58:36.663734 11, 0xFFFF, sum = 0
3349 09:58:36.663817 12, 0x0, sum = 1
3350 09:58:36.667407 13, 0x0, sum = 2
3351 09:58:36.667490 14, 0x0, sum = 3
3352 09:58:36.670542 15, 0x0, sum = 4
3353 09:58:36.670626 best_step = 13
3354 09:58:36.670690
3355 09:58:36.670751 ==
3356 09:58:36.673552 Dram Type= 6, Freq= 0, CH_1, rank 0
3357 09:58:36.680536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3358 09:58:36.680619 ==
3359 09:58:36.680684 RX Vref Scan: 1
3360 09:58:36.680744
3361 09:58:36.684152 Set Vref Range= 32 -> 127
3362 09:58:36.684234
3363 09:58:36.687145 RX Vref 32 -> 127, step: 1
3364 09:58:36.687228
3365 09:58:36.687292 RX Delay -21 -> 252, step: 4
3366 09:58:36.690827
3367 09:58:36.690933 Set Vref, RX VrefLevel [Byte0]: 32
3368 09:58:36.693898 [Byte1]: 32
3369 09:58:36.698523
3370 09:58:36.698609 Set Vref, RX VrefLevel [Byte0]: 33
3371 09:58:36.702050 [Byte1]: 33
3372 09:58:36.706637
3373 09:58:36.706720 Set Vref, RX VrefLevel [Byte0]: 34
3374 09:58:36.710065 [Byte1]: 34
3375 09:58:36.714317
3376 09:58:36.714400 Set Vref, RX VrefLevel [Byte0]: 35
3377 09:58:36.717299 [Byte1]: 35
3378 09:58:36.722274
3379 09:58:36.722357 Set Vref, RX VrefLevel [Byte0]: 36
3380 09:58:36.725314 [Byte1]: 36
3381 09:58:36.730277
3382 09:58:36.730360 Set Vref, RX VrefLevel [Byte0]: 37
3383 09:58:36.733402 [Byte1]: 37
3384 09:58:36.737742
3385 09:58:36.737825 Set Vref, RX VrefLevel [Byte0]: 38
3386 09:58:36.741493 [Byte1]: 38
3387 09:58:36.745995
3388 09:58:36.746079 Set Vref, RX VrefLevel [Byte0]: 39
3389 09:58:36.749506 [Byte1]: 39
3390 09:58:36.753767
3391 09:58:36.753850 Set Vref, RX VrefLevel [Byte0]: 40
3392 09:58:36.757376 [Byte1]: 40
3393 09:58:36.762021
3394 09:58:36.762135 Set Vref, RX VrefLevel [Byte0]: 41
3395 09:58:36.765035 [Byte1]: 41
3396 09:58:36.769717
3397 09:58:36.769800 Set Vref, RX VrefLevel [Byte0]: 42
3398 09:58:36.772796 [Byte1]: 42
3399 09:58:36.777837
3400 09:58:36.777920 Set Vref, RX VrefLevel [Byte0]: 43
3401 09:58:36.780838 [Byte1]: 43
3402 09:58:36.785749
3403 09:58:36.785833 Set Vref, RX VrefLevel [Byte0]: 44
3404 09:58:36.788746 [Byte1]: 44
3405 09:58:36.793757
3406 09:58:36.793840 Set Vref, RX VrefLevel [Byte0]: 45
3407 09:58:36.796921 [Byte1]: 45
3408 09:58:36.801313
3409 09:58:36.801471 Set Vref, RX VrefLevel [Byte0]: 46
3410 09:58:36.804843 [Byte1]: 46
3411 09:58:36.809416
3412 09:58:36.809536 Set Vref, RX VrefLevel [Byte0]: 47
3413 09:58:36.812876 [Byte1]: 47
3414 09:58:36.817471
3415 09:58:36.817542 Set Vref, RX VrefLevel [Byte0]: 48
3416 09:58:36.820537 [Byte1]: 48
3417 09:58:36.825188
3418 09:58:36.825264 Set Vref, RX VrefLevel [Byte0]: 49
3419 09:58:36.828295 [Byte1]: 49
3420 09:58:36.833241
3421 09:58:36.833349 Set Vref, RX VrefLevel [Byte0]: 50
3422 09:58:36.836404 [Byte1]: 50
3423 09:58:36.841237
3424 09:58:36.841312 Set Vref, RX VrefLevel [Byte0]: 51
3425 09:58:36.844320 [Byte1]: 51
3426 09:58:36.848621
3427 09:58:36.848695 Set Vref, RX VrefLevel [Byte0]: 52
3428 09:58:36.852344 [Byte1]: 52
3429 09:58:36.856624
3430 09:58:36.856702 Set Vref, RX VrefLevel [Byte0]: 53
3431 09:58:36.860313 [Byte1]: 53
3432 09:58:36.864960
3433 09:58:36.865065 Set Vref, RX VrefLevel [Byte0]: 54
3434 09:58:36.867897 [Byte1]: 54
3435 09:58:36.872556
3436 09:58:36.872661 Set Vref, RX VrefLevel [Byte0]: 55
3437 09:58:36.875916 [Byte1]: 55
3438 09:58:36.880245
3439 09:58:36.880348 Set Vref, RX VrefLevel [Byte0]: 56
3440 09:58:36.884052 [Byte1]: 56
3441 09:58:36.888873
3442 09:58:36.888979 Set Vref, RX VrefLevel [Byte0]: 57
3443 09:58:36.891845 [Byte1]: 57
3444 09:58:36.896770
3445 09:58:36.896857 Set Vref, RX VrefLevel [Byte0]: 58
3446 09:58:36.899784 [Byte1]: 58
3447 09:58:36.904333
3448 09:58:36.904447 Set Vref, RX VrefLevel [Byte0]: 59
3449 09:58:36.907440 [Byte1]: 59
3450 09:58:36.912602
3451 09:58:36.912712 Set Vref, RX VrefLevel [Byte0]: 60
3452 09:58:36.915647 [Byte1]: 60
3453 09:58:36.919951
3454 09:58:36.920049 Set Vref, RX VrefLevel [Byte0]: 61
3455 09:58:36.923492 [Byte1]: 61
3456 09:58:36.928150
3457 09:58:36.928229 Set Vref, RX VrefLevel [Byte0]: 62
3458 09:58:36.931819 [Byte1]: 62
3459 09:58:36.936016
3460 09:58:36.936095 Set Vref, RX VrefLevel [Byte0]: 63
3461 09:58:36.939261 [Byte1]: 63
3462 09:58:36.944187
3463 09:58:36.944270 Set Vref, RX VrefLevel [Byte0]: 64
3464 09:58:36.947380 [Byte1]: 64
3465 09:58:36.952121
3466 09:58:36.952200 Set Vref, RX VrefLevel [Byte0]: 65
3467 09:58:36.955306 [Byte1]: 65
3468 09:58:36.959496
3469 09:58:36.959575 Set Vref, RX VrefLevel [Byte0]: 66
3470 09:58:36.963080 [Byte1]: 66
3471 09:58:36.967833
3472 09:58:36.967944 Set Vref, RX VrefLevel [Byte0]: 67
3473 09:58:36.970798 [Byte1]: 67
3474 09:58:36.975657
3475 09:58:36.975762 Set Vref, RX VrefLevel [Byte0]: 68
3476 09:58:36.979435 [Byte1]: 68
3477 09:58:36.983236
3478 09:58:36.983314 Final RX Vref Byte 0 = 57 to rank0
3479 09:58:36.986842 Final RX Vref Byte 1 = 45 to rank0
3480 09:58:36.990067 Final RX Vref Byte 0 = 57 to rank1
3481 09:58:36.993696 Final RX Vref Byte 1 = 45 to rank1==
3482 09:58:36.997207 Dram Type= 6, Freq= 0, CH_1, rank 0
3483 09:58:37.000268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3484 09:58:37.003464 ==
3485 09:58:37.003570 DQS Delay:
3486 09:58:37.003662 DQS0 = 0, DQS1 = 0
3487 09:58:37.007072 DQM Delay:
3488 09:58:37.007176 DQM0 = 116, DQM1 = 108
3489 09:58:37.010170 DQ Delay:
3490 09:58:37.013608 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =112
3491 09:58:37.016905 DQ4 =116, DQ5 =126, DQ6 =128, DQ7 =112
3492 09:58:37.020307 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =102
3493 09:58:37.023944 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =114
3494 09:58:37.024061
3495 09:58:37.024153
3496 09:58:37.030570 [DQSOSCAuto] RK0, (LSB)MR18= 0xffe4, (MSB)MR19= 0x303, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
3497 09:58:37.033701 CH1 RK0: MR19=303, MR18=FFE4
3498 09:58:37.040309 CH1_RK0: MR19=0x303, MR18=0xFFE4, DQSOSC=410, MR23=63, INC=39, DEC=26
3499 09:58:37.040413
3500 09:58:37.044057 ----->DramcWriteLeveling(PI) begin...
3501 09:58:37.044150 ==
3502 09:58:37.047320 Dram Type= 6, Freq= 0, CH_1, rank 1
3503 09:58:37.050760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3504 09:58:37.050902 ==
3505 09:58:37.053974 Write leveling (Byte 0): 27 => 27
3506 09:58:37.057593 Write leveling (Byte 1): 27 => 27
3507 09:58:37.060729 DramcWriteLeveling(PI) end<-----
3508 09:58:37.060807
3509 09:58:37.060871 ==
3510 09:58:37.063800 Dram Type= 6, Freq= 0, CH_1, rank 1
3511 09:58:37.067546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3512 09:58:37.067649 ==
3513 09:58:37.070590 [Gating] SW mode calibration
3514 09:58:37.077798 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3515 09:58:37.084347 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3516 09:58:37.087516 0 15 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3517 09:58:37.094067 0 15 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3518 09:58:37.097569 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3519 09:58:37.101136 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3520 09:58:37.104207 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3521 09:58:37.111129 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3522 09:58:37.114656 0 15 24 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 1)
3523 09:58:37.117802 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
3524 09:58:37.124859 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3525 09:58:37.127749 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3526 09:58:37.131401 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3527 09:58:37.138029 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3528 09:58:37.141613 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3529 09:58:37.144622 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3530 09:58:37.151373 1 0 24 | B1->B0 | 2727 3f3f | 0 0 | (0 0) (1 1)
3531 09:58:37.154521 1 0 28 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
3532 09:58:37.158174 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3533 09:58:37.161400 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3534 09:58:37.168011 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 09:58:37.171623 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3536 09:58:37.174963 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3537 09:58:37.181556 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3538 09:58:37.184842 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3539 09:58:37.187923 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3540 09:58:37.194492 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 09:58:37.198039 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 09:58:37.201787 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 09:58:37.208412 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 09:58:37.211494 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 09:58:37.214582 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 09:58:37.221301 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 09:58:37.225220 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 09:58:37.228635 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 09:58:37.234874 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 09:58:37.238580 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 09:58:37.241575 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 09:58:37.245109 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 09:58:37.252095 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 09:58:37.255186 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3555 09:58:37.258082 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3556 09:58:37.261834 Total UI for P1: 0, mck2ui 16
3557 09:58:37.265028 best dqsien dly found for B0: ( 1, 3, 24)
3558 09:58:37.271766 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3559 09:58:37.271873 Total UI for P1: 0, mck2ui 16
3560 09:58:37.278077 best dqsien dly found for B1: ( 1, 3, 28)
3561 09:58:37.281745 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3562 09:58:37.284913 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3563 09:58:37.285018
3564 09:58:37.288168 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3565 09:58:37.291699 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3566 09:58:37.295239 [Gating] SW calibration Done
3567 09:58:37.295348 ==
3568 09:58:37.298210 Dram Type= 6, Freq= 0, CH_1, rank 1
3569 09:58:37.301627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3570 09:58:37.301710 ==
3571 09:58:37.305167 RX Vref Scan: 0
3572 09:58:37.305247
3573 09:58:37.305311 RX Vref 0 -> 0, step: 1
3574 09:58:37.305377
3575 09:58:37.308676 RX Delay -40 -> 252, step: 8
3576 09:58:37.311843 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3577 09:58:37.318506 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3578 09:58:37.321667 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3579 09:58:37.325347 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3580 09:58:37.328747 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3581 09:58:37.331729 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3582 09:58:37.338341 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3583 09:58:37.341868 iDelay=200, Bit 7, Center 107 (40 ~ 175) 136
3584 09:58:37.345265 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3585 09:58:37.348823 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3586 09:58:37.351857 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3587 09:58:37.354966 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3588 09:58:37.361868 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3589 09:58:37.364974 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3590 09:58:37.368645 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3591 09:58:37.371706 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3592 09:58:37.371787 ==
3593 09:58:37.375623 Dram Type= 6, Freq= 0, CH_1, rank 1
3594 09:58:37.381812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3595 09:58:37.381894 ==
3596 09:58:37.381960 DQS Delay:
3597 09:58:37.382022 DQS0 = 0, DQS1 = 0
3598 09:58:37.385454 DQM Delay:
3599 09:58:37.385533 DQM0 = 114, DQM1 = 108
3600 09:58:37.388771 DQ Delay:
3601 09:58:37.391929 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =115
3602 09:58:37.395628 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =107
3603 09:58:37.398739 DQ8 =95, DQ9 =99, DQ10 =107, DQ11 =99
3604 09:58:37.402552 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3605 09:58:37.402660
3606 09:58:37.402763
3607 09:58:37.402864 ==
3608 09:58:37.405338 Dram Type= 6, Freq= 0, CH_1, rank 1
3609 09:58:37.409164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3610 09:58:37.409271 ==
3611 09:58:37.409342
3612 09:58:37.409403
3613 09:58:37.412188 TX Vref Scan disable
3614 09:58:37.415582 == TX Byte 0 ==
3615 09:58:37.418889 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3616 09:58:37.422066 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3617 09:58:37.425858 == TX Byte 1 ==
3618 09:58:37.428991 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3619 09:58:37.432140 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3620 09:58:37.432218 ==
3621 09:58:37.435255 Dram Type= 6, Freq= 0, CH_1, rank 1
3622 09:58:37.442160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3623 09:58:37.442243 ==
3624 09:58:37.452229 TX Vref=22, minBit 1, minWin=25, winSum=417
3625 09:58:37.455581 TX Vref=24, minBit 0, minWin=26, winSum=425
3626 09:58:37.459107 TX Vref=26, minBit 0, minWin=26, winSum=429
3627 09:58:37.462295 TX Vref=28, minBit 3, minWin=26, winSum=433
3628 09:58:37.465378 TX Vref=30, minBit 4, minWin=26, winSum=437
3629 09:58:37.469064 TX Vref=32, minBit 2, minWin=26, winSum=436
3630 09:58:37.475884 [TxChooseVref] Worse bit 4, Min win 26, Win sum 437, Final Vref 30
3631 09:58:37.475964
3632 09:58:37.478954 Final TX Range 1 Vref 30
3633 09:58:37.479028
3634 09:58:37.479091 ==
3635 09:58:37.482201 Dram Type= 6, Freq= 0, CH_1, rank 1
3636 09:58:37.485991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3637 09:58:37.486063 ==
3638 09:58:37.486126
3639 09:58:37.486185
3640 09:58:37.489094 TX Vref Scan disable
3641 09:58:37.492161 == TX Byte 0 ==
3642 09:58:37.495387 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3643 09:58:37.498848 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3644 09:58:37.502601 == TX Byte 1 ==
3645 09:58:37.505774 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3646 09:58:37.509387 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3647 09:58:37.509462
3648 09:58:37.512473 [DATLAT]
3649 09:58:37.512546 Freq=1200, CH1 RK1
3650 09:58:37.512610
3651 09:58:37.515801 DATLAT Default: 0xd
3652 09:58:37.515883 0, 0xFFFF, sum = 0
3653 09:58:37.519035 1, 0xFFFF, sum = 0
3654 09:58:37.519111 2, 0xFFFF, sum = 0
3655 09:58:37.522668 3, 0xFFFF, sum = 0
3656 09:58:37.522767 4, 0xFFFF, sum = 0
3657 09:58:37.525611 5, 0xFFFF, sum = 0
3658 09:58:37.525711 6, 0xFFFF, sum = 0
3659 09:58:37.529093 7, 0xFFFF, sum = 0
3660 09:58:37.529193 8, 0xFFFF, sum = 0
3661 09:58:37.532476 9, 0xFFFF, sum = 0
3662 09:58:37.532553 10, 0xFFFF, sum = 0
3663 09:58:37.535908 11, 0xFFFF, sum = 0
3664 09:58:37.535997 12, 0x0, sum = 1
3665 09:58:37.539021 13, 0x0, sum = 2
3666 09:58:37.539098 14, 0x0, sum = 3
3667 09:58:37.542259 15, 0x0, sum = 4
3668 09:58:37.542341 best_step = 13
3669 09:58:37.542427
3670 09:58:37.542521 ==
3671 09:58:37.545976 Dram Type= 6, Freq= 0, CH_1, rank 1
3672 09:58:37.552572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3673 09:58:37.552654 ==
3674 09:58:37.552728 RX Vref Scan: 0
3675 09:58:37.552791
3676 09:58:37.555606 RX Vref 0 -> 0, step: 1
3677 09:58:37.555684
3678 09:58:37.559135 RX Delay -21 -> 252, step: 4
3679 09:58:37.562543 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3680 09:58:37.565855 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3681 09:58:37.572794 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3682 09:58:37.575792 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3683 09:58:37.579560 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3684 09:58:37.582668 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3685 09:58:37.585792 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3686 09:58:37.589463 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3687 09:58:37.596441 iDelay=191, Bit 8, Center 94 (27 ~ 162) 136
3688 09:58:37.599641 iDelay=191, Bit 9, Center 96 (31 ~ 162) 132
3689 09:58:37.602621 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3690 09:58:37.605854 iDelay=191, Bit 11, Center 100 (35 ~ 166) 132
3691 09:58:37.609470 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3692 09:58:37.616293 iDelay=191, Bit 13, Center 116 (51 ~ 182) 132
3693 09:58:37.619512 iDelay=191, Bit 14, Center 116 (55 ~ 178) 124
3694 09:58:37.622597 iDelay=191, Bit 15, Center 116 (51 ~ 182) 132
3695 09:58:37.622687 ==
3696 09:58:37.625808 Dram Type= 6, Freq= 0, CH_1, rank 1
3697 09:58:37.629517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3698 09:58:37.629596 ==
3699 09:58:37.632491 DQS Delay:
3700 09:58:37.632576 DQS0 = 0, DQS1 = 0
3701 09:58:37.636109 DQM Delay:
3702 09:58:37.636181 DQM0 = 113, DQM1 = 107
3703 09:58:37.636243 DQ Delay:
3704 09:58:37.642748 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =112
3705 09:58:37.645761 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3706 09:58:37.649110 DQ8 =94, DQ9 =96, DQ10 =110, DQ11 =100
3707 09:58:37.652556 DQ12 =114, DQ13 =116, DQ14 =116, DQ15 =116
3708 09:58:37.652661
3709 09:58:37.652734
3710 09:58:37.659505 [DQSOSCAuto] RK1, (LSB)MR18= 0xf7fe, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 413 ps
3711 09:58:37.662892 CH1 RK1: MR19=303, MR18=F7FE
3712 09:58:37.669644 CH1_RK1: MR19=0x303, MR18=0xF7FE, DQSOSC=410, MR23=63, INC=39, DEC=26
3713 09:58:37.672886 [RxdqsGatingPostProcess] freq 1200
3714 09:58:37.676254 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3715 09:58:37.679575 best DQS0 dly(2T, 0.5T) = (0, 11)
3716 09:58:37.682488 best DQS1 dly(2T, 0.5T) = (0, 11)
3717 09:58:37.686271 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3718 09:58:37.689403 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3719 09:58:37.692541 best DQS0 dly(2T, 0.5T) = (0, 11)
3720 09:58:37.696172 best DQS1 dly(2T, 0.5T) = (0, 11)
3721 09:58:37.699312 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3722 09:58:37.703063 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3723 09:58:37.706018 Pre-setting of DQS Precalculation
3724 09:58:37.709156 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3725 09:58:37.719637 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3726 09:58:37.725939 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3727 09:58:37.726020
3728 09:58:37.726086
3729 09:58:37.729638 [Calibration Summary] 2400 Mbps
3730 09:58:37.729714 CH 0, Rank 0
3731 09:58:37.732784 SW Impedance : PASS
3732 09:58:37.732860 DUTY Scan : NO K
3733 09:58:37.736390 ZQ Calibration : PASS
3734 09:58:37.739990 Jitter Meter : NO K
3735 09:58:37.740065 CBT Training : PASS
3736 09:58:37.743071 Write leveling : PASS
3737 09:58:37.746026 RX DQS gating : PASS
3738 09:58:37.746101 RX DQ/DQS(RDDQC) : PASS
3739 09:58:37.749853 TX DQ/DQS : PASS
3740 09:58:37.749962 RX DATLAT : PASS
3741 09:58:37.752938 RX DQ/DQS(Engine): PASS
3742 09:58:37.756457 TX OE : NO K
3743 09:58:37.756536 All Pass.
3744 09:58:37.756628
3745 09:58:37.756697 CH 0, Rank 1
3746 09:58:37.760019 SW Impedance : PASS
3747 09:58:37.762931 DUTY Scan : NO K
3748 09:58:37.763034 ZQ Calibration : PASS
3749 09:58:37.766775 Jitter Meter : NO K
3750 09:58:37.770032 CBT Training : PASS
3751 09:58:37.770112 Write leveling : PASS
3752 09:58:37.773621 RX DQS gating : PASS
3753 09:58:37.776619 RX DQ/DQS(RDDQC) : PASS
3754 09:58:37.776728 TX DQ/DQS : PASS
3755 09:58:37.780319 RX DATLAT : PASS
3756 09:58:37.780434 RX DQ/DQS(Engine): PASS
3757 09:58:37.783345 TX OE : NO K
3758 09:58:37.783451 All Pass.
3759 09:58:37.783556
3760 09:58:37.786840 CH 1, Rank 0
3761 09:58:37.786952 SW Impedance : PASS
3762 09:58:37.790307 DUTY Scan : NO K
3763 09:58:37.793211 ZQ Calibration : PASS
3764 09:58:37.793319 Jitter Meter : NO K
3765 09:58:37.796559 CBT Training : PASS
3766 09:58:37.800125 Write leveling : PASS
3767 09:58:37.800237 RX DQS gating : PASS
3768 09:58:37.803156 RX DQ/DQS(RDDQC) : PASS
3769 09:58:37.806902 TX DQ/DQS : PASS
3770 09:58:37.807009 RX DATLAT : PASS
3771 09:58:37.809993 RX DQ/DQS(Engine): PASS
3772 09:58:37.813456 TX OE : NO K
3773 09:58:37.813567 All Pass.
3774 09:58:37.813662
3775 09:58:37.813751 CH 1, Rank 1
3776 09:58:37.816710 SW Impedance : PASS
3777 09:58:37.819769 DUTY Scan : NO K
3778 09:58:37.819872 ZQ Calibration : PASS
3779 09:58:37.823372 Jitter Meter : NO K
3780 09:58:37.826361 CBT Training : PASS
3781 09:58:37.826463 Write leveling : PASS
3782 09:58:37.830176 RX DQS gating : PASS
3783 09:58:37.830249 RX DQ/DQS(RDDQC) : PASS
3784 09:58:37.833343 TX DQ/DQS : PASS
3785 09:58:37.836611 RX DATLAT : PASS
3786 09:58:37.836687 RX DQ/DQS(Engine): PASS
3787 09:58:37.839678 TX OE : NO K
3788 09:58:37.839763 All Pass.
3789 09:58:37.839830
3790 09:58:37.843348 DramC Write-DBI off
3791 09:58:37.846370 PER_BANK_REFRESH: Hybrid Mode
3792 09:58:37.846442 TX_TRACKING: ON
3793 09:58:37.856872 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3794 09:58:37.860147 [FAST_K] Save calibration result to emmc
3795 09:58:37.863092 dramc_set_vcore_voltage set vcore to 650000
3796 09:58:37.866700 Read voltage for 600, 5
3797 09:58:37.866812 Vio18 = 0
3798 09:58:37.866929 Vcore = 650000
3799 09:58:37.869702 Vdram = 0
3800 09:58:37.869806 Vddq = 0
3801 09:58:37.869900 Vmddr = 0
3802 09:58:37.876607 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3803 09:58:37.879540 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3804 09:58:37.883144 MEM_TYPE=3, freq_sel=19
3805 09:58:37.886828 sv_algorithm_assistance_LP4_1600
3806 09:58:37.889930 ============ PULL DRAM RESETB DOWN ============
3807 09:58:37.893432 ========== PULL DRAM RESETB DOWN end =========
3808 09:58:37.900270 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3809 09:58:37.903241 ===================================
3810 09:58:37.906781 LPDDR4 DRAM CONFIGURATION
3811 09:58:37.910071 ===================================
3812 09:58:37.910178 EX_ROW_EN[0] = 0x0
3813 09:58:37.913336 EX_ROW_EN[1] = 0x0
3814 09:58:37.913441 LP4Y_EN = 0x0
3815 09:58:37.916691 WORK_FSP = 0x0
3816 09:58:37.916798 WL = 0x2
3817 09:58:37.920309 RL = 0x2
3818 09:58:37.920424 BL = 0x2
3819 09:58:37.923235 RPST = 0x0
3820 09:58:37.923321 RD_PRE = 0x0
3821 09:58:37.926449 WR_PRE = 0x1
3822 09:58:37.926536 WR_PST = 0x0
3823 09:58:37.930140 DBI_WR = 0x0
3824 09:58:37.930225 DBI_RD = 0x0
3825 09:58:37.933290 OTF = 0x1
3826 09:58:37.936970 ===================================
3827 09:58:37.940290 ===================================
3828 09:58:37.940392 ANA top config
3829 09:58:37.943329 ===================================
3830 09:58:37.946870 DLL_ASYNC_EN = 0
3831 09:58:37.949879 ALL_SLAVE_EN = 1
3832 09:58:37.953604 NEW_RANK_MODE = 1
3833 09:58:37.953710 DLL_IDLE_MODE = 1
3834 09:58:37.956718 LP45_APHY_COMB_EN = 1
3835 09:58:37.959864 TX_ODT_DIS = 1
3836 09:58:37.963687 NEW_8X_MODE = 1
3837 09:58:37.966816 ===================================
3838 09:58:37.970414 ===================================
3839 09:58:37.970525 data_rate = 1200
3840 09:58:37.973359 CKR = 1
3841 09:58:37.976506 DQ_P2S_RATIO = 8
3842 09:58:37.980170 ===================================
3843 09:58:37.983384 CA_P2S_RATIO = 8
3844 09:58:37.986597 DQ_CA_OPEN = 0
3845 09:58:37.990054 DQ_SEMI_OPEN = 0
3846 09:58:37.990129 CA_SEMI_OPEN = 0
3847 09:58:37.993482 CA_FULL_RATE = 0
3848 09:58:37.997034 DQ_CKDIV4_EN = 1
3849 09:58:38.000023 CA_CKDIV4_EN = 1
3850 09:58:38.003666 CA_PREDIV_EN = 0
3851 09:58:38.006841 PH8_DLY = 0
3852 09:58:38.006938 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3853 09:58:38.009908 DQ_AAMCK_DIV = 4
3854 09:58:38.013430 CA_AAMCK_DIV = 4
3855 09:58:38.016972 CA_ADMCK_DIV = 4
3856 09:58:38.020228 DQ_TRACK_CA_EN = 0
3857 09:58:38.023563 CA_PICK = 600
3858 09:58:38.023645 CA_MCKIO = 600
3859 09:58:38.027038 MCKIO_SEMI = 0
3860 09:58:38.030035 PLL_FREQ = 2288
3861 09:58:38.033491 DQ_UI_PI_RATIO = 32
3862 09:58:38.037139 CA_UI_PI_RATIO = 0
3863 09:58:38.040291 ===================================
3864 09:58:38.043407 ===================================
3865 09:58:38.047217 memory_type:LPDDR4
3866 09:58:38.047321 GP_NUM : 10
3867 09:58:38.050339 SRAM_EN : 1
3868 09:58:38.050419 MD32_EN : 0
3869 09:58:38.053246 ===================================
3870 09:58:38.057085 [ANA_INIT] >>>>>>>>>>>>>>
3871 09:58:38.060086 <<<<<< [CONFIGURE PHASE]: ANA_TX
3872 09:58:38.063755 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3873 09:58:38.067078 ===================================
3874 09:58:38.069988 data_rate = 1200,PCW = 0X5800
3875 09:58:38.073807 ===================================
3876 09:58:38.076934 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3877 09:58:38.079928 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3878 09:58:38.086633 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3879 09:58:38.090382 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3880 09:58:38.096993 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3881 09:58:38.099923 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3882 09:58:38.100009 [ANA_INIT] flow start
3883 09:58:38.103577 [ANA_INIT] PLL >>>>>>>>
3884 09:58:38.106842 [ANA_INIT] PLL <<<<<<<<
3885 09:58:38.106926 [ANA_INIT] MIDPI >>>>>>>>
3886 09:58:38.110184 [ANA_INIT] MIDPI <<<<<<<<
3887 09:58:38.113490 [ANA_INIT] DLL >>>>>>>>
3888 09:58:38.113597 [ANA_INIT] flow end
3889 09:58:38.116528 ============ LP4 DIFF to SE enter ============
3890 09:58:38.123140 ============ LP4 DIFF to SE exit ============
3891 09:58:38.123219 [ANA_INIT] <<<<<<<<<<<<<
3892 09:58:38.126840 [Flow] Enable top DCM control >>>>>
3893 09:58:38.130276 [Flow] Enable top DCM control <<<<<
3894 09:58:38.133277 Enable DLL master slave shuffle
3895 09:58:38.139832 ==============================================================
3896 09:58:38.139942 Gating Mode config
3897 09:58:38.146786 ==============================================================
3898 09:58:38.149836 Config description:
3899 09:58:38.160259 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3900 09:58:38.167071 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3901 09:58:38.169901 SELPH_MODE 0: By rank 1: By Phase
3902 09:58:38.176831 ==============================================================
3903 09:58:38.179873 GAT_TRACK_EN = 1
3904 09:58:38.179948 RX_GATING_MODE = 2
3905 09:58:38.183010 RX_GATING_TRACK_MODE = 2
3906 09:58:38.186732 SELPH_MODE = 1
3907 09:58:38.189967 PICG_EARLY_EN = 1
3908 09:58:38.193591 VALID_LAT_VALUE = 1
3909 09:58:38.200196 ==============================================================
3910 09:58:38.203084 Enter into Gating configuration >>>>
3911 09:58:38.206857 Exit from Gating configuration <<<<
3912 09:58:38.209790 Enter into DVFS_PRE_config >>>>>
3913 09:58:38.219846 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3914 09:58:38.223450 Exit from DVFS_PRE_config <<<<<
3915 09:58:38.227071 Enter into PICG configuration >>>>
3916 09:58:38.229771 Exit from PICG configuration <<<<
3917 09:58:38.233491 [RX_INPUT] configuration >>>>>
3918 09:58:38.233583 [RX_INPUT] configuration <<<<<
3919 09:58:38.239943 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3920 09:58:38.246635 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3921 09:58:38.250289 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3922 09:58:38.257027 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3923 09:58:38.263533 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3924 09:58:38.269794 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3925 09:58:38.273442 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3926 09:58:38.276424 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3927 09:58:38.283246 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3928 09:58:38.286965 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3929 09:58:38.289821 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3930 09:58:38.296921 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3931 09:58:38.300383 ===================================
3932 09:58:38.300466 LPDDR4 DRAM CONFIGURATION
3933 09:58:38.303478 ===================================
3934 09:58:38.306397 EX_ROW_EN[0] = 0x0
3935 09:58:38.306470 EX_ROW_EN[1] = 0x0
3936 09:58:38.309734 LP4Y_EN = 0x0
3937 09:58:38.309816 WORK_FSP = 0x0
3938 09:58:38.313457 WL = 0x2
3939 09:58:38.316368 RL = 0x2
3940 09:58:38.316441 BL = 0x2
3941 09:58:38.320134 RPST = 0x0
3942 09:58:38.320208 RD_PRE = 0x0
3943 09:58:38.323252 WR_PRE = 0x1
3944 09:58:38.323335 WR_PST = 0x0
3945 09:58:38.326870 DBI_WR = 0x0
3946 09:58:38.326953 DBI_RD = 0x0
3947 09:58:38.329768 OTF = 0x1
3948 09:58:38.333085 ===================================
3949 09:58:38.336136 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3950 09:58:38.339780 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3951 09:58:38.346293 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3952 09:58:38.346400 ===================================
3953 09:58:38.349465 LPDDR4 DRAM CONFIGURATION
3954 09:58:38.352854 ===================================
3955 09:58:38.356263 EX_ROW_EN[0] = 0x10
3956 09:58:38.356345 EX_ROW_EN[1] = 0x0
3957 09:58:38.359997 LP4Y_EN = 0x0
3958 09:58:38.360078 WORK_FSP = 0x0
3959 09:58:38.362950 WL = 0x2
3960 09:58:38.365880 RL = 0x2
3961 09:58:38.365967 BL = 0x2
3962 09:58:38.369522 RPST = 0x0
3963 09:58:38.369631 RD_PRE = 0x0
3964 09:58:38.372762 WR_PRE = 0x1
3965 09:58:38.372879 WR_PST = 0x0
3966 09:58:38.376008 DBI_WR = 0x0
3967 09:58:38.376118 DBI_RD = 0x0
3968 09:58:38.379315 OTF = 0x1
3969 09:58:38.383096 ===================================
3970 09:58:38.386208 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3971 09:58:38.391852 nWR fixed to 30
3972 09:58:38.395267 [ModeRegInit_LP4] CH0 RK0
3973 09:58:38.395383 [ModeRegInit_LP4] CH0 RK1
3974 09:58:38.398233 [ModeRegInit_LP4] CH1 RK0
3975 09:58:38.401417 [ModeRegInit_LP4] CH1 RK1
3976 09:58:38.401535 match AC timing 17
3977 09:58:38.408194 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3978 09:58:38.411211 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3979 09:58:38.415339 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3980 09:58:38.421753 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3981 09:58:38.424871 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3982 09:58:38.424970 ==
3983 09:58:38.428500 Dram Type= 6, Freq= 0, CH_0, rank 0
3984 09:58:38.431612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3985 09:58:38.431743 ==
3986 09:58:38.438463 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3987 09:58:38.444991 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3988 09:58:38.447956 [CA 0] Center 36 (6~66) winsize 61
3989 09:58:38.451500 [CA 1] Center 36 (6~66) winsize 61
3990 09:58:38.454812 [CA 2] Center 34 (4~65) winsize 62
3991 09:58:38.458181 [CA 3] Center 34 (4~65) winsize 62
3992 09:58:38.462064 [CA 4] Center 34 (4~64) winsize 61
3993 09:58:38.465001 [CA 5] Center 33 (3~64) winsize 62
3994 09:58:38.465167
3995 09:58:38.468583 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3996 09:58:38.468729
3997 09:58:38.471622 [CATrainingPosCal] consider 1 rank data
3998 09:58:38.474900 u2DelayCellTimex100 = 270/100 ps
3999 09:58:38.478184 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4000 09:58:38.482091 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4001 09:58:38.485498 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4002 09:58:38.488324 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4003 09:58:38.492043 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4004 09:58:38.495282 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4005 09:58:38.495386
4006 09:58:38.501440 CA PerBit enable=1, Macro0, CA PI delay=33
4007 09:58:38.501537
4008 09:58:38.501607 [CBTSetCACLKResult] CA Dly = 33
4009 09:58:38.505098 CS Dly: 5 (0~36)
4010 09:58:38.505182 ==
4011 09:58:38.508191 Dram Type= 6, Freq= 0, CH_0, rank 1
4012 09:58:38.511903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4013 09:58:38.512025 ==
4014 09:58:38.518676 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4015 09:58:38.525623 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4016 09:58:38.528907 [CA 0] Center 35 (5~66) winsize 62
4017 09:58:38.531776 [CA 1] Center 36 (6~66) winsize 61
4018 09:58:38.535623 [CA 2] Center 34 (4~65) winsize 62
4019 09:58:38.538597 [CA 3] Center 34 (4~64) winsize 61
4020 09:58:38.542464 [CA 4] Center 33 (3~64) winsize 62
4021 09:58:38.545304 [CA 5] Center 33 (3~64) winsize 62
4022 09:58:38.545394
4023 09:58:38.548861 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4024 09:58:38.548959
4025 09:58:38.551807 [CATrainingPosCal] consider 2 rank data
4026 09:58:38.555523 u2DelayCellTimex100 = 270/100 ps
4027 09:58:38.558567 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4028 09:58:38.562208 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4029 09:58:38.565119 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4030 09:58:38.568942 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4031 09:58:38.571860 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4032 09:58:38.575316 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4033 09:58:38.575467
4034 09:58:38.578703 CA PerBit enable=1, Macro0, CA PI delay=33
4035 09:58:38.578804
4036 09:58:38.582029 [CBTSetCACLKResult] CA Dly = 33
4037 09:58:38.585338 CS Dly: 5 (0~36)
4038 09:58:38.585422
4039 09:58:38.588732 ----->DramcWriteLeveling(PI) begin...
4040 09:58:38.588818 ==
4041 09:58:38.592217 Dram Type= 6, Freq= 0, CH_0, rank 0
4042 09:58:38.595490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4043 09:58:38.595575 ==
4044 09:58:38.598808 Write leveling (Byte 0): 31 => 31
4045 09:58:38.602186 Write leveling (Byte 1): 29 => 29
4046 09:58:38.605352 DramcWriteLeveling(PI) end<-----
4047 09:58:38.605459
4048 09:58:38.605557 ==
4049 09:58:38.608504 Dram Type= 6, Freq= 0, CH_0, rank 0
4050 09:58:38.612182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4051 09:58:38.612285 ==
4052 09:58:38.615505 [Gating] SW mode calibration
4053 09:58:38.622105 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4054 09:58:38.628940 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4055 09:58:38.631992 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4056 09:58:38.635722 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4057 09:58:38.642082 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4058 09:58:38.645739 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4059 09:58:38.648681 0 9 16 | B1->B0 | 3131 2c2c | 0 0 | (0 0) (1 1)
4060 09:58:38.655771 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4061 09:58:38.658807 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4062 09:58:38.662159 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4063 09:58:38.668573 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4064 09:58:38.672412 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4065 09:58:38.675492 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4066 09:58:38.682117 0 10 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4067 09:58:38.685638 0 10 16 | B1->B0 | 3030 4444 | 0 0 | (0 0) (0 0)
4068 09:58:38.688649 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4069 09:58:38.695703 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4070 09:58:38.698681 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4071 09:58:38.702343 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4072 09:58:38.709183 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 09:58:38.712357 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4074 09:58:38.715786 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4075 09:58:38.718941 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4076 09:58:38.725577 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 09:58:38.728764 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 09:58:38.732555 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 09:58:38.739354 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 09:58:38.742601 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 09:58:38.745677 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 09:58:38.752366 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 09:58:38.755865 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 09:58:38.758984 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 09:58:38.765691 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 09:58:38.769345 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 09:58:38.772495 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 09:58:38.779331 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 09:58:38.782813 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 09:58:38.786061 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4091 09:58:38.792738 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4092 09:58:38.792849 Total UI for P1: 0, mck2ui 16
4093 09:58:38.795564 best dqsien dly found for B0: ( 0, 13, 12)
4094 09:58:38.802365 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4095 09:58:38.806063 Total UI for P1: 0, mck2ui 16
4096 09:58:38.809362 best dqsien dly found for B1: ( 0, 13, 14)
4097 09:58:38.812783 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4098 09:58:38.815680 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4099 09:58:38.815790
4100 09:58:38.819133 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4101 09:58:38.822513 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4102 09:58:38.826072 [Gating] SW calibration Done
4103 09:58:38.826186 ==
4104 09:58:38.829515 Dram Type= 6, Freq= 0, CH_0, rank 0
4105 09:58:38.832749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4106 09:58:38.832853 ==
4107 09:58:38.835866 RX Vref Scan: 0
4108 09:58:38.835965
4109 09:58:38.836055 RX Vref 0 -> 0, step: 1
4110 09:58:38.839670
4111 09:58:38.839781 RX Delay -230 -> 252, step: 16
4112 09:58:38.845832 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4113 09:58:38.849576 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4114 09:58:38.852753 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4115 09:58:38.855814 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4116 09:58:38.859247 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4117 09:58:38.865981 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4118 09:58:38.869011 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4119 09:58:38.872836 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4120 09:58:38.875743 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4121 09:58:38.883248 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4122 09:58:38.886120 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4123 09:58:38.889673 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4124 09:58:38.892559 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4125 09:58:38.896233 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4126 09:58:38.902820 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4127 09:58:38.906048 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4128 09:58:38.906142 ==
4129 09:58:38.909861 Dram Type= 6, Freq= 0, CH_0, rank 0
4130 09:58:38.912580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4131 09:58:38.912688 ==
4132 09:58:38.916325 DQS Delay:
4133 09:58:38.916462 DQS0 = 0, DQS1 = 0
4134 09:58:38.916586 DQM Delay:
4135 09:58:38.919936 DQM0 = 42, DQM1 = 33
4136 09:58:38.920054 DQ Delay:
4137 09:58:38.923114 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4138 09:58:38.926408 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4139 09:58:38.929505 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4140 09:58:38.932881 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =49
4141 09:58:38.932994
4142 09:58:38.933089
4143 09:58:38.933178 ==
4144 09:58:38.936224 Dram Type= 6, Freq= 0, CH_0, rank 0
4145 09:58:38.942957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4146 09:58:38.943041 ==
4147 09:58:38.943130
4148 09:58:38.943194
4149 09:58:38.943253 TX Vref Scan disable
4150 09:58:38.946714 == TX Byte 0 ==
4151 09:58:38.949855 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4152 09:58:38.953603 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4153 09:58:38.956563 == TX Byte 1 ==
4154 09:58:38.960384 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4155 09:58:38.963278 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4156 09:58:38.966903 ==
4157 09:58:38.970200 Dram Type= 6, Freq= 0, CH_0, rank 0
4158 09:58:38.973404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4159 09:58:38.973512 ==
4160 09:58:38.973606
4161 09:58:38.973695
4162 09:58:38.976419 TX Vref Scan disable
4163 09:58:38.976495 == TX Byte 0 ==
4164 09:58:38.983685 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4165 09:58:38.986775 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4166 09:58:38.986882 == TX Byte 1 ==
4167 09:58:38.993514 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4168 09:58:38.996627 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4169 09:58:38.996730
4170 09:58:38.996825 [DATLAT]
4171 09:58:39.000149 Freq=600, CH0 RK0
4172 09:58:39.000240
4173 09:58:39.000306 DATLAT Default: 0x9
4174 09:58:39.003609 0, 0xFFFF, sum = 0
4175 09:58:39.003694 1, 0xFFFF, sum = 0
4176 09:58:39.007164 2, 0xFFFF, sum = 0
4177 09:58:39.007248 3, 0xFFFF, sum = 0
4178 09:58:39.010237 4, 0xFFFF, sum = 0
4179 09:58:39.010310 5, 0xFFFF, sum = 0
4180 09:58:39.013784 6, 0xFFFF, sum = 0
4181 09:58:39.013869 7, 0xFFFF, sum = 0
4182 09:58:39.016873 8, 0x0, sum = 1
4183 09:58:39.016957 9, 0x0, sum = 2
4184 09:58:39.020376 10, 0x0, sum = 3
4185 09:58:39.020490 11, 0x0, sum = 4
4186 09:58:39.023423 best_step = 9
4187 09:58:39.023535
4188 09:58:39.023630 ==
4189 09:58:39.027164 Dram Type= 6, Freq= 0, CH_0, rank 0
4190 09:58:39.030049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4191 09:58:39.030140 ==
4192 09:58:39.033406 RX Vref Scan: 1
4193 09:58:39.033519
4194 09:58:39.033612 RX Vref 0 -> 0, step: 1
4195 09:58:39.033713
4196 09:58:39.036740 RX Delay -195 -> 252, step: 8
4197 09:58:39.036823
4198 09:58:39.040252 Set Vref, RX VrefLevel [Byte0]: 53
4199 09:58:39.043382 [Byte1]: 49
4200 09:58:39.047346
4201 09:58:39.047434 Final RX Vref Byte 0 = 53 to rank0
4202 09:58:39.050430 Final RX Vref Byte 1 = 49 to rank0
4203 09:58:39.054143 Final RX Vref Byte 0 = 53 to rank1
4204 09:58:39.057369 Final RX Vref Byte 1 = 49 to rank1==
4205 09:58:39.060402 Dram Type= 6, Freq= 0, CH_0, rank 0
4206 09:58:39.064239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4207 09:58:39.067474 ==
4208 09:58:39.067587 DQS Delay:
4209 09:58:39.067684 DQS0 = 0, DQS1 = 0
4210 09:58:39.070287 DQM Delay:
4211 09:58:39.070395 DQM0 = 42, DQM1 = 34
4212 09:58:39.073937 DQ Delay:
4213 09:58:39.077318 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =40
4214 09:58:39.077399 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4215 09:58:39.080400 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =32
4216 09:58:39.083866 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4217 09:58:39.087577
4218 09:58:39.087665
4219 09:58:39.093552 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c1b, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
4220 09:58:39.097347 CH0 RK0: MR19=808, MR18=3C1B
4221 09:58:39.104264 CH0_RK0: MR19=0x808, MR18=0x3C1B, DQSOSC=398, MR23=63, INC=165, DEC=110
4222 09:58:39.104384
4223 09:58:39.107170 ----->DramcWriteLeveling(PI) begin...
4224 09:58:39.107284 ==
4225 09:58:39.110500 Dram Type= 6, Freq= 0, CH_0, rank 1
4226 09:58:39.114346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4227 09:58:39.114450 ==
4228 09:58:39.117302 Write leveling (Byte 0): 32 => 32
4229 09:58:39.120959 Write leveling (Byte 1): 30 => 30
4230 09:58:39.123911 DramcWriteLeveling(PI) end<-----
4231 09:58:39.124015
4232 09:58:39.124113 ==
4233 09:58:39.127024 Dram Type= 6, Freq= 0, CH_0, rank 1
4234 09:58:39.130435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4235 09:58:39.130518 ==
4236 09:58:39.134068 [Gating] SW mode calibration
4237 09:58:39.140966 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4238 09:58:39.147780 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4239 09:58:39.150627 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4240 09:58:39.154175 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4241 09:58:39.160420 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4242 09:58:39.164399 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
4243 09:58:39.167433 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4244 09:58:39.174088 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4245 09:58:39.177132 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4246 09:58:39.180758 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4247 09:58:39.187209 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4248 09:58:39.190781 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4249 09:58:39.193923 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4250 09:58:39.197589 0 10 12 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
4251 09:58:39.204198 0 10 16 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
4252 09:58:39.207383 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 09:58:39.210898 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4254 09:58:39.217221 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4255 09:58:39.220720 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 09:58:39.223969 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 09:58:39.230763 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4258 09:58:39.233927 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4259 09:58:39.237488 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4260 09:58:39.243915 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4261 09:58:39.247205 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 09:58:39.250769 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 09:58:39.257363 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 09:58:39.260945 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 09:58:39.264048 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 09:58:39.270935 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 09:58:39.274020 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 09:58:39.277473 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 09:58:39.284200 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 09:58:39.287241 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 09:58:39.290718 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 09:58:39.294279 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 09:58:39.300666 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4274 09:58:39.304210 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4275 09:58:39.307368 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4276 09:58:39.310985 Total UI for P1: 0, mck2ui 16
4277 09:58:39.314018 best dqsien dly found for B0: ( 0, 13, 10)
4278 09:58:39.317743 Total UI for P1: 0, mck2ui 16
4279 09:58:39.320603 best dqsien dly found for B1: ( 0, 13, 12)
4280 09:58:39.324098 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4281 09:58:39.327583 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4282 09:58:39.327687
4283 09:58:39.334199 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4284 09:58:39.337393 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4285 09:58:39.340930 [Gating] SW calibration Done
4286 09:58:39.341032 ==
4287 09:58:39.344516 Dram Type= 6, Freq= 0, CH_0, rank 1
4288 09:58:39.347547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4289 09:58:39.347630 ==
4290 09:58:39.347695 RX Vref Scan: 0
4291 09:58:39.347755
4292 09:58:39.350945 RX Vref 0 -> 0, step: 1
4293 09:58:39.351047
4294 09:58:39.356018 RX Delay -230 -> 252, step: 16
4295 09:58:39.357726 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4296 09:58:39.361210 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4297 09:58:39.367978 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4298 09:58:39.371141 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4299 09:58:39.374132 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4300 09:58:39.377886 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4301 09:58:39.381150 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4302 09:58:39.387524 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4303 09:58:39.391138 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4304 09:58:39.394101 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4305 09:58:39.397833 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4306 09:58:39.404544 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4307 09:58:39.407967 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4308 09:58:39.411077 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4309 09:58:39.414288 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4310 09:58:39.421061 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4311 09:58:39.421176 ==
4312 09:58:39.424710 Dram Type= 6, Freq= 0, CH_0, rank 1
4313 09:58:39.427727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4314 09:58:39.427841 ==
4315 09:58:39.427938 DQS Delay:
4316 09:58:39.431206 DQS0 = 0, DQS1 = 0
4317 09:58:39.431301 DQM Delay:
4318 09:58:39.434791 DQM0 = 37, DQM1 = 31
4319 09:58:39.434901 DQ Delay:
4320 09:58:39.437965 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4321 09:58:39.441077 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4322 09:58:39.444818 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4323 09:58:39.447822 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =41
4324 09:58:39.447919
4325 09:58:39.447987
4326 09:58:39.448047 ==
4327 09:58:39.451617 Dram Type= 6, Freq= 0, CH_0, rank 1
4328 09:58:39.454619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4329 09:58:39.454736 ==
4330 09:58:39.454842
4331 09:58:39.454922
4332 09:58:39.457943 TX Vref Scan disable
4333 09:58:39.461040 == TX Byte 0 ==
4334 09:58:39.464529 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4335 09:58:39.468190 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4336 09:58:39.471591 == TX Byte 1 ==
4337 09:58:39.474691 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4338 09:58:39.477912 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4339 09:58:39.478048 ==
4340 09:58:39.481494 Dram Type= 6, Freq= 0, CH_0, rank 1
4341 09:58:39.485141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 09:58:39.485288 ==
4343 09:58:39.488215
4344 09:58:39.488306
4345 09:58:39.488374 TX Vref Scan disable
4346 09:58:39.491882 == TX Byte 0 ==
4347 09:58:39.495091 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4348 09:58:39.498520 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4349 09:58:39.501543 == TX Byte 1 ==
4350 09:58:39.505355 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4351 09:58:39.508387 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4352 09:58:39.512117
4353 09:58:39.512205 [DATLAT]
4354 09:58:39.512268 Freq=600, CH0 RK1
4355 09:58:39.512329
4356 09:58:39.514994 DATLAT Default: 0x9
4357 09:58:39.515067 0, 0xFFFF, sum = 0
4358 09:58:39.518636 1, 0xFFFF, sum = 0
4359 09:58:39.518714 2, 0xFFFF, sum = 0
4360 09:58:39.521827 3, 0xFFFF, sum = 0
4361 09:58:39.521929 4, 0xFFFF, sum = 0
4362 09:58:39.524999 5, 0xFFFF, sum = 0
4363 09:58:39.525079 6, 0xFFFF, sum = 0
4364 09:58:39.528844 7, 0xFFFF, sum = 0
4365 09:58:39.528929 8, 0x0, sum = 1
4366 09:58:39.532364 9, 0x0, sum = 2
4367 09:58:39.532459 10, 0x0, sum = 3
4368 09:58:39.535261 11, 0x0, sum = 4
4369 09:58:39.535344 best_step = 9
4370 09:58:39.535409
4371 09:58:39.535469 ==
4372 09:58:39.538760 Dram Type= 6, Freq= 0, CH_0, rank 1
4373 09:58:39.545524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4374 09:58:39.545609 ==
4375 09:58:39.545674 RX Vref Scan: 0
4376 09:58:39.545735
4377 09:58:39.548684 RX Vref 0 -> 0, step: 1
4378 09:58:39.548769
4379 09:58:39.551711 RX Delay -195 -> 252, step: 8
4380 09:58:39.554977 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4381 09:58:39.562416 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4382 09:58:39.565150 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4383 09:58:39.568646 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4384 09:58:39.571769 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4385 09:58:39.575495 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4386 09:58:39.582201 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4387 09:58:39.585346 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4388 09:58:39.588454 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4389 09:58:39.592049 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4390 09:58:39.595083 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4391 09:58:39.602246 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4392 09:58:39.605191 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4393 09:58:39.608374 iDelay=205, Bit 13, Center 36 (-115 ~ 188) 304
4394 09:58:39.612185 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4395 09:58:39.618760 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4396 09:58:39.618840 ==
4397 09:58:39.621834 Dram Type= 6, Freq= 0, CH_0, rank 1
4398 09:58:39.625609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4399 09:58:39.625692 ==
4400 09:58:39.625781 DQS Delay:
4401 09:58:39.628724 DQS0 = 0, DQS1 = 0
4402 09:58:39.628806 DQM Delay:
4403 09:58:39.631759 DQM0 = 39, DQM1 = 33
4404 09:58:39.631841 DQ Delay:
4405 09:58:39.635370 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4406 09:58:39.638413 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =48
4407 09:58:39.641997 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4408 09:58:39.645439 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4409 09:58:39.645522
4410 09:58:39.645586
4411 09:58:39.652109 [DQSOSCAuto] RK1, (LSB)MR18= 0x4526, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4412 09:58:39.655158 CH0 RK1: MR19=808, MR18=4526
4413 09:58:39.662019 CH0_RK1: MR19=0x808, MR18=0x4526, DQSOSC=396, MR23=63, INC=167, DEC=111
4414 09:58:39.665653 [RxdqsGatingPostProcess] freq 600
4415 09:58:39.672446 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4416 09:58:39.675182 Pre-setting of DQS Precalculation
4417 09:58:39.678647 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4418 09:58:39.678730 ==
4419 09:58:39.682118 Dram Type= 6, Freq= 0, CH_1, rank 0
4420 09:58:39.685762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4421 09:58:39.685846 ==
4422 09:58:39.691880 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4423 09:58:39.698620 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4424 09:58:39.702233 [CA 0] Center 35 (5~65) winsize 61
4425 09:58:39.705751 [CA 1] Center 35 (5~65) winsize 61
4426 09:58:39.709105 [CA 2] Center 34 (4~64) winsize 61
4427 09:58:39.712176 [CA 3] Center 33 (3~64) winsize 62
4428 09:58:39.715814 [CA 4] Center 34 (3~65) winsize 63
4429 09:58:39.718930 [CA 5] Center 33 (3~64) winsize 62
4430 09:58:39.719011
4431 09:58:39.721988 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4432 09:58:39.722065
4433 09:58:39.725616 [CATrainingPosCal] consider 1 rank data
4434 09:58:39.728843 u2DelayCellTimex100 = 270/100 ps
4435 09:58:39.731947 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4436 09:58:39.735613 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4437 09:58:39.738689 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4438 09:58:39.742372 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4439 09:58:39.745419 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4440 09:58:39.748929 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4441 09:58:39.749004
4442 09:58:39.755664 CA PerBit enable=1, Macro0, CA PI delay=33
4443 09:58:39.755765
4444 09:58:39.758740 [CBTSetCACLKResult] CA Dly = 33
4445 09:58:39.758843 CS Dly: 4 (0~35)
4446 09:58:39.758933 ==
4447 09:58:39.762498 Dram Type= 6, Freq= 0, CH_1, rank 1
4448 09:58:39.765508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4449 09:58:39.765591 ==
4450 09:58:39.772259 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4451 09:58:39.779156 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4452 09:58:39.782667 [CA 0] Center 35 (5~66) winsize 62
4453 09:58:39.785928 [CA 1] Center 35 (5~66) winsize 62
4454 09:58:39.789225 [CA 2] Center 34 (3~65) winsize 63
4455 09:58:39.792534 [CA 3] Center 34 (3~65) winsize 63
4456 09:58:39.795599 [CA 4] Center 34 (4~65) winsize 62
4457 09:58:39.799200 [CA 5] Center 33 (3~64) winsize 62
4458 09:58:39.799288
4459 09:58:39.802360 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4460 09:58:39.802440
4461 09:58:39.805929 [CATrainingPosCal] consider 2 rank data
4462 09:58:39.809008 u2DelayCellTimex100 = 270/100 ps
4463 09:58:39.812524 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4464 09:58:39.816030 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4465 09:58:39.819162 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4466 09:58:39.822173 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4467 09:58:39.825814 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4468 09:58:39.828922 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4469 09:58:39.828995
4470 09:58:39.835838 CA PerBit enable=1, Macro0, CA PI delay=33
4471 09:58:39.835914
4472 09:58:39.835977 [CBTSetCACLKResult] CA Dly = 33
4473 09:58:39.838774 CS Dly: 5 (0~38)
4474 09:58:39.838843
4475 09:58:39.842624 ----->DramcWriteLeveling(PI) begin...
4476 09:58:39.842697 ==
4477 09:58:39.845636 Dram Type= 6, Freq= 0, CH_1, rank 0
4478 09:58:39.849368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4479 09:58:39.849441 ==
4480 09:58:39.852638 Write leveling (Byte 0): 28 => 28
4481 09:58:39.855527 Write leveling (Byte 1): 31 => 31
4482 09:58:39.859053 DramcWriteLeveling(PI) end<-----
4483 09:58:39.859127
4484 09:58:39.859212 ==
4485 09:58:39.862440 Dram Type= 6, Freq= 0, CH_1, rank 0
4486 09:58:39.865758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4487 09:58:39.868914 ==
4488 09:58:39.868993 [Gating] SW mode calibration
4489 09:58:39.875808 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4490 09:58:39.882559 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4491 09:58:39.885617 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4492 09:58:39.892408 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4493 09:58:39.895710 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4494 09:58:39.899171 0 9 12 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 1)
4495 09:58:39.905824 0 9 16 | B1->B0 | 2a2a 2727 | 0 0 | (0 0) (0 0)
4496 09:58:39.909429 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4497 09:58:39.912599 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4498 09:58:39.915777 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4499 09:58:39.922462 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4500 09:58:39.926332 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4501 09:58:39.929280 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4502 09:58:39.936065 0 10 12 | B1->B0 | 2a2a 2f2f | 1 0 | (0 0) (0 0)
4503 09:58:39.939229 0 10 16 | B1->B0 | 3939 3c3c | 0 0 | (0 0) (0 0)
4504 09:58:39.942810 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 09:58:39.949415 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4506 09:58:39.952562 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4507 09:58:39.956278 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4508 09:58:39.962521 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 09:58:39.966173 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 09:58:39.968995 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4511 09:58:39.976158 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4512 09:58:39.979055 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 09:58:39.982766 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 09:58:39.988867 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 09:58:39.992614 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 09:58:39.995741 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 09:58:40.002486 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 09:58:40.005967 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 09:58:40.008894 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 09:58:40.012435 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 09:58:40.018923 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 09:58:40.022287 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 09:58:40.025615 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 09:58:40.032018 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 09:58:40.035808 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 09:58:40.038776 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 09:58:40.045592 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4528 09:58:40.049183 Total UI for P1: 0, mck2ui 16
4529 09:58:40.052170 best dqsien dly found for B0: ( 0, 13, 14)
4530 09:58:40.052243 Total UI for P1: 0, mck2ui 16
4531 09:58:40.058926 best dqsien dly found for B1: ( 0, 13, 14)
4532 09:58:40.062674 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4533 09:58:40.065610 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4534 09:58:40.065710
4535 09:58:40.069408 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4536 09:58:40.072663 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4537 09:58:40.076104 [Gating] SW calibration Done
4538 09:58:40.076184 ==
4539 09:58:40.079212 Dram Type= 6, Freq= 0, CH_1, rank 0
4540 09:58:40.082776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4541 09:58:40.082852 ==
4542 09:58:40.086246 RX Vref Scan: 0
4543 09:58:40.086334
4544 09:58:40.086440 RX Vref 0 -> 0, step: 1
4545 09:58:40.086541
4546 09:58:40.089392 RX Delay -230 -> 252, step: 16
4547 09:58:40.092429 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4548 09:58:40.099288 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4549 09:58:40.103059 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4550 09:58:40.106179 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4551 09:58:40.109207 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4552 09:58:40.116090 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4553 09:58:40.119659 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4554 09:58:40.122784 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4555 09:58:40.125986 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4556 09:58:40.129438 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4557 09:58:40.136064 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4558 09:58:40.139264 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4559 09:58:40.142999 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4560 09:58:40.146154 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4561 09:58:40.153218 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4562 09:58:40.156294 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4563 09:58:40.156411 ==
4564 09:58:40.159536 Dram Type= 6, Freq= 0, CH_1, rank 0
4565 09:58:40.162739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4566 09:58:40.162848 ==
4567 09:58:40.166417 DQS Delay:
4568 09:58:40.166493 DQS0 = 0, DQS1 = 0
4569 09:58:40.166563 DQM Delay:
4570 09:58:40.169602 DQM0 = 42, DQM1 = 35
4571 09:58:40.169677 DQ Delay:
4572 09:58:40.172661 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4573 09:58:40.176417 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =33
4574 09:58:40.179405 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4575 09:58:40.182932 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4576 09:58:40.183015
4577 09:58:40.183091
4578 09:58:40.183153 ==
4579 09:58:40.186179 Dram Type= 6, Freq= 0, CH_1, rank 0
4580 09:58:40.189849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4581 09:58:40.193223 ==
4582 09:58:40.193300
4583 09:58:40.193364
4584 09:58:40.193432 TX Vref Scan disable
4585 09:58:40.196275 == TX Byte 0 ==
4586 09:58:40.199917 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4587 09:58:40.203000 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4588 09:58:40.206721 == TX Byte 1 ==
4589 09:58:40.209737 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4590 09:58:40.213448 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4591 09:58:40.213566 ==
4592 09:58:40.216489 Dram Type= 6, Freq= 0, CH_1, rank 0
4593 09:58:40.223532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4594 09:58:40.223612 ==
4595 09:58:40.223677
4596 09:58:40.223743
4597 09:58:40.223806 TX Vref Scan disable
4598 09:58:40.227979 == TX Byte 0 ==
4599 09:58:40.231546 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4600 09:58:40.237765 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4601 09:58:40.237843 == TX Byte 1 ==
4602 09:58:40.241448 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4603 09:58:40.247590 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4604 09:58:40.247667
4605 09:58:40.247737 [DATLAT]
4606 09:58:40.247797 Freq=600, CH1 RK0
4607 09:58:40.247854
4608 09:58:40.251171 DATLAT Default: 0x9
4609 09:58:40.251253 0, 0xFFFF, sum = 0
4610 09:58:40.254554 1, 0xFFFF, sum = 0
4611 09:58:40.254640 2, 0xFFFF, sum = 0
4612 09:58:40.257818 3, 0xFFFF, sum = 0
4613 09:58:40.257912 4, 0xFFFF, sum = 0
4614 09:58:40.261231 5, 0xFFFF, sum = 0
4615 09:58:40.264438 6, 0xFFFF, sum = 0
4616 09:58:40.264517 7, 0xFFFF, sum = 0
4617 09:58:40.264582 8, 0x0, sum = 1
4618 09:58:40.268163 9, 0x0, sum = 2
4619 09:58:40.268242 10, 0x0, sum = 3
4620 09:58:40.271359 11, 0x0, sum = 4
4621 09:58:40.271433 best_step = 9
4622 09:58:40.271504
4623 09:58:40.271562 ==
4624 09:58:40.274480 Dram Type= 6, Freq= 0, CH_1, rank 0
4625 09:58:40.281310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4626 09:58:40.281387 ==
4627 09:58:40.281455 RX Vref Scan: 1
4628 09:58:40.281519
4629 09:58:40.284344 RX Vref 0 -> 0, step: 1
4630 09:58:40.284423
4631 09:58:40.287634 RX Delay -195 -> 252, step: 8
4632 09:58:40.287701
4633 09:58:40.291576 Set Vref, RX VrefLevel [Byte0]: 57
4634 09:58:40.294538 [Byte1]: 45
4635 09:58:40.294620
4636 09:58:40.297678 Final RX Vref Byte 0 = 57 to rank0
4637 09:58:40.301508 Final RX Vref Byte 1 = 45 to rank0
4638 09:58:40.304473 Final RX Vref Byte 0 = 57 to rank1
4639 09:58:40.308209 Final RX Vref Byte 1 = 45 to rank1==
4640 09:58:40.311219 Dram Type= 6, Freq= 0, CH_1, rank 0
4641 09:58:40.314993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4642 09:58:40.315076 ==
4643 09:58:40.318070 DQS Delay:
4644 09:58:40.318168 DQS0 = 0, DQS1 = 0
4645 09:58:40.318251 DQM Delay:
4646 09:58:40.321191 DQM0 = 42, DQM1 = 32
4647 09:58:40.321270 DQ Delay:
4648 09:58:40.324791 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =44
4649 09:58:40.328275 DQ4 =44, DQ5 =52, DQ6 =52, DQ7 =36
4650 09:58:40.331481 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =28
4651 09:58:40.334723 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =36
4652 09:58:40.334800
4653 09:58:40.334905
4654 09:58:40.345094 [DQSOSCAuto] RK0, (LSB)MR18= 0x4108, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
4655 09:58:40.345179 CH1 RK0: MR19=808, MR18=4108
4656 09:58:40.351290 CH1_RK0: MR19=0x808, MR18=0x4108, DQSOSC=397, MR23=63, INC=166, DEC=110
4657 09:58:40.351373
4658 09:58:40.354747 ----->DramcWriteLeveling(PI) begin...
4659 09:58:40.354858 ==
4660 09:58:40.358681 Dram Type= 6, Freq= 0, CH_1, rank 1
4661 09:58:40.364779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4662 09:58:40.364858 ==
4663 09:58:40.368306 Write leveling (Byte 0): 31 => 31
4664 09:58:40.371874 Write leveling (Byte 1): 31 => 31
4665 09:58:40.371951 DramcWriteLeveling(PI) end<-----
4666 09:58:40.372040
4667 09:58:40.374880 ==
4668 09:58:40.378009 Dram Type= 6, Freq= 0, CH_1, rank 1
4669 09:58:40.381827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4670 09:58:40.381909 ==
4671 09:58:40.385098 [Gating] SW mode calibration
4672 09:58:40.391911 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4673 09:58:40.394988 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4674 09:58:40.401807 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4675 09:58:40.405044 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4676 09:58:40.408251 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4677 09:58:40.414767 0 9 12 | B1->B0 | 2f2f 2525 | 1 1 | (1 1) (1 0)
4678 09:58:40.418418 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4679 09:58:40.421864 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4680 09:58:40.424917 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4681 09:58:40.432180 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4682 09:58:40.435042 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4683 09:58:40.438748 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4684 09:58:40.445127 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4685 09:58:40.448520 0 10 12 | B1->B0 | 2f2f 3c3c | 0 0 | (0 0) (0 0)
4686 09:58:40.451697 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4687 09:58:40.458625 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4688 09:58:40.461754 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4689 09:58:40.465576 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4690 09:58:40.471690 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4691 09:58:40.475511 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4692 09:58:40.478481 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4693 09:58:40.481947 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4694 09:58:40.488741 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 09:58:40.491812 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 09:58:40.495170 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 09:58:40.501951 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 09:58:40.505460 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 09:58:40.508762 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 09:58:40.515839 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 09:58:40.519222 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 09:58:40.522356 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 09:58:40.529130 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 09:58:40.532144 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 09:58:40.535573 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 09:58:40.542411 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 09:58:40.545459 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 09:58:40.549164 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4709 09:58:40.552206 Total UI for P1: 0, mck2ui 16
4710 09:58:40.555876 best dqsien dly found for B0: ( 0, 13, 6)
4711 09:58:40.558645 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4712 09:58:40.562310 Total UI for P1: 0, mck2ui 16
4713 09:58:40.565805 best dqsien dly found for B1: ( 0, 13, 10)
4714 09:58:40.568897 best DQS0 dly(MCK, UI, PI) = (0, 13, 6)
4715 09:58:40.575838 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4716 09:58:40.575915
4717 09:58:40.578977 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 6)
4718 09:58:40.582609 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4719 09:58:40.585600 [Gating] SW calibration Done
4720 09:58:40.585682 ==
4721 09:58:40.588907 Dram Type= 6, Freq= 0, CH_1, rank 1
4722 09:58:40.592592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4723 09:58:40.592667 ==
4724 09:58:40.592729 RX Vref Scan: 0
4725 09:58:40.592787
4726 09:58:40.595937 RX Vref 0 -> 0, step: 1
4727 09:58:40.596039
4728 09:58:40.599084 RX Delay -230 -> 252, step: 16
4729 09:58:40.602696 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4730 09:58:40.606058 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4731 09:58:40.612182 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4732 09:58:40.615727 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4733 09:58:40.619461 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4734 09:58:40.622436 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4735 09:58:40.629571 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4736 09:58:40.632626 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4737 09:58:40.636148 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4738 09:58:40.639444 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4739 09:58:40.642758 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4740 09:58:40.649621 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4741 09:58:40.652789 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4742 09:58:40.655863 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4743 09:58:40.659539 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4744 09:58:40.666199 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4745 09:58:40.666312 ==
4746 09:58:40.669206 Dram Type= 6, Freq= 0, CH_1, rank 1
4747 09:58:40.672783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4748 09:58:40.672888 ==
4749 09:58:40.672990 DQS Delay:
4750 09:58:40.676034 DQS0 = 0, DQS1 = 0
4751 09:58:40.676172 DQM Delay:
4752 09:58:40.679534 DQM0 = 40, DQM1 = 34
4753 09:58:40.679607 DQ Delay:
4754 09:58:40.682621 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4755 09:58:40.685813 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33
4756 09:58:40.689475 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4757 09:58:40.692959 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4758 09:58:40.693034
4759 09:58:40.693095
4760 09:58:40.693151 ==
4761 09:58:40.696252 Dram Type= 6, Freq= 0, CH_1, rank 1
4762 09:58:40.699229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4763 09:58:40.699300 ==
4764 09:58:40.699360
4765 09:58:40.699415
4766 09:58:40.702942 TX Vref Scan disable
4767 09:58:40.706087 == TX Byte 0 ==
4768 09:58:40.709400 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4769 09:58:40.713061 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4770 09:58:40.715949 == TX Byte 1 ==
4771 09:58:40.719271 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4772 09:58:40.722668 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4773 09:58:40.722777 ==
4774 09:58:40.726355 Dram Type= 6, Freq= 0, CH_1, rank 1
4775 09:58:40.729401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4776 09:58:40.732914 ==
4777 09:58:40.732990
4778 09:58:40.733060
4779 09:58:40.733151 TX Vref Scan disable
4780 09:58:40.736427 == TX Byte 0 ==
4781 09:58:40.740125 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4782 09:58:40.744136 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4783 09:58:40.746825 == TX Byte 1 ==
4784 09:58:40.749946 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4785 09:58:40.753708 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4786 09:58:40.756819
4787 09:58:40.756891 [DATLAT]
4788 09:58:40.756953 Freq=600, CH1 RK1
4789 09:58:40.757012
4790 09:58:40.759993 DATLAT Default: 0x9
4791 09:58:40.760069 0, 0xFFFF, sum = 0
4792 09:58:40.763155 1, 0xFFFF, sum = 0
4793 09:58:40.763225 2, 0xFFFF, sum = 0
4794 09:58:40.767037 3, 0xFFFF, sum = 0
4795 09:58:40.767108 4, 0xFFFF, sum = 0
4796 09:58:40.770045 5, 0xFFFF, sum = 0
4797 09:58:40.773158 6, 0xFFFF, sum = 0
4798 09:58:40.773235 7, 0xFFFF, sum = 0
4799 09:58:40.773299 8, 0x0, sum = 1
4800 09:58:40.777038 9, 0x0, sum = 2
4801 09:58:40.777112 10, 0x0, sum = 3
4802 09:58:40.779939 11, 0x0, sum = 4
4803 09:58:40.780014 best_step = 9
4804 09:58:40.780074
4805 09:58:40.780130 ==
4806 09:58:40.783435 Dram Type= 6, Freq= 0, CH_1, rank 1
4807 09:58:40.790325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4808 09:58:40.790402 ==
4809 09:58:40.790464 RX Vref Scan: 0
4810 09:58:40.790523
4811 09:58:40.793383 RX Vref 0 -> 0, step: 1
4812 09:58:40.793455
4813 09:58:40.797261 RX Delay -179 -> 252, step: 8
4814 09:58:40.800142 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4815 09:58:40.803516 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4816 09:58:40.810340 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4817 09:58:40.813846 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4818 09:58:40.816904 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4819 09:58:40.820389 iDelay=205, Bit 5, Center 52 (-99 ~ 204) 304
4820 09:58:40.827048 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4821 09:58:40.830361 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4822 09:58:40.833468 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4823 09:58:40.837225 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4824 09:58:40.840052 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4825 09:58:40.847037 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4826 09:58:40.849891 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4827 09:58:40.853507 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4828 09:58:40.856725 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4829 09:58:40.863462 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4830 09:58:40.863537 ==
4831 09:58:40.867255 Dram Type= 6, Freq= 0, CH_1, rank 1
4832 09:58:40.870310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4833 09:58:40.870381 ==
4834 09:58:40.870442 DQS Delay:
4835 09:58:40.873390 DQS0 = 0, DQS1 = 0
4836 09:58:40.873460 DQM Delay:
4837 09:58:40.877174 DQM0 = 39, DQM1 = 33
4838 09:58:40.877244 DQ Delay:
4839 09:58:40.880283 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4840 09:58:40.883418 DQ4 =40, DQ5 =52, DQ6 =48, DQ7 =32
4841 09:58:40.887238 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =28
4842 09:58:40.890406 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =44
4843 09:58:40.890480
4844 09:58:40.890542
4845 09:58:40.896689 [DQSOSCAuto] RK1, (LSB)MR18= 0x3746, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
4846 09:58:40.900448 CH1 RK1: MR19=808, MR18=3746
4847 09:58:40.907181 CH1_RK1: MR19=0x808, MR18=0x3746, DQSOSC=396, MR23=63, INC=167, DEC=111
4848 09:58:40.910118 [RxdqsGatingPostProcess] freq 600
4849 09:58:40.917036 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4850 09:58:40.920590 Pre-setting of DQS Precalculation
4851 09:58:40.923624 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4852 09:58:40.930139 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4853 09:58:40.937125 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4854 09:58:40.937203
4855 09:58:40.937265
4856 09:58:40.940170 [Calibration Summary] 1200 Mbps
4857 09:58:40.943901 CH 0, Rank 0
4858 09:58:40.943972 SW Impedance : PASS
4859 09:58:40.947333 DUTY Scan : NO K
4860 09:58:40.950160 ZQ Calibration : PASS
4861 09:58:40.950230 Jitter Meter : NO K
4862 09:58:40.953886 CBT Training : PASS
4863 09:58:40.953959 Write leveling : PASS
4864 09:58:40.956812 RX DQS gating : PASS
4865 09:58:40.960450 RX DQ/DQS(RDDQC) : PASS
4866 09:58:40.960526 TX DQ/DQS : PASS
4867 09:58:40.963751 RX DATLAT : PASS
4868 09:58:40.967471 RX DQ/DQS(Engine): PASS
4869 09:58:40.967542 TX OE : NO K
4870 09:58:40.970460 All Pass.
4871 09:58:40.970529
4872 09:58:40.970588 CH 0, Rank 1
4873 09:58:40.973616 SW Impedance : PASS
4874 09:58:40.973684 DUTY Scan : NO K
4875 09:58:40.976780 ZQ Calibration : PASS
4876 09:58:40.980465 Jitter Meter : NO K
4877 09:58:40.980531 CBT Training : PASS
4878 09:58:40.983716 Write leveling : PASS
4879 09:58:40.987395 RX DQS gating : PASS
4880 09:58:40.987465 RX DQ/DQS(RDDQC) : PASS
4881 09:58:40.990452 TX DQ/DQS : PASS
4882 09:58:40.990522 RX DATLAT : PASS
4883 09:58:40.993485 RX DQ/DQS(Engine): PASS
4884 09:58:40.997138 TX OE : NO K
4885 09:58:40.997209 All Pass.
4886 09:58:40.997274
4887 09:58:40.997332 CH 1, Rank 0
4888 09:58:41.000286 SW Impedance : PASS
4889 09:58:41.003980 DUTY Scan : NO K
4890 09:58:41.004100 ZQ Calibration : PASS
4891 09:58:41.006765 Jitter Meter : NO K
4892 09:58:41.010551 CBT Training : PASS
4893 09:58:41.010647 Write leveling : PASS
4894 09:58:41.013407 RX DQS gating : PASS
4895 09:58:41.016998 RX DQ/DQS(RDDQC) : PASS
4896 09:58:41.017074 TX DQ/DQS : PASS
4897 09:58:41.020172 RX DATLAT : PASS
4898 09:58:41.023702 RX DQ/DQS(Engine): PASS
4899 09:58:41.023776 TX OE : NO K
4900 09:58:41.026790 All Pass.
4901 09:58:41.026921
4902 09:58:41.026982 CH 1, Rank 1
4903 09:58:41.030526 SW Impedance : PASS
4904 09:58:41.030600 DUTY Scan : NO K
4905 09:58:41.033356 ZQ Calibration : PASS
4906 09:58:41.036951 Jitter Meter : NO K
4907 09:58:41.037025 CBT Training : PASS
4908 09:58:41.040471 Write leveling : PASS
4909 09:58:41.040540 RX DQS gating : PASS
4910 09:58:41.043467 RX DQ/DQS(RDDQC) : PASS
4911 09:58:41.047171 TX DQ/DQS : PASS
4912 09:58:41.047253 RX DATLAT : PASS
4913 09:58:41.049958 RX DQ/DQS(Engine): PASS
4914 09:58:41.053598 TX OE : NO K
4915 09:58:41.053696 All Pass.
4916 09:58:41.053784
4917 09:58:41.057161 DramC Write-DBI off
4918 09:58:41.057264 PER_BANK_REFRESH: Hybrid Mode
4919 09:58:41.060213 TX_TRACKING: ON
4920 09:58:41.067028 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4921 09:58:41.073790 [FAST_K] Save calibration result to emmc
4922 09:58:41.076926 dramc_set_vcore_voltage set vcore to 662500
4923 09:58:41.076999 Read voltage for 933, 3
4924 09:58:41.080534 Vio18 = 0
4925 09:58:41.080603 Vcore = 662500
4926 09:58:41.080663 Vdram = 0
4927 09:58:41.083643 Vddq = 0
4928 09:58:41.083722 Vmddr = 0
4929 09:58:41.087347 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4930 09:58:41.093555 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4931 09:58:41.097237 MEM_TYPE=3, freq_sel=17
4932 09:58:41.100321 sv_algorithm_assistance_LP4_1600
4933 09:58:41.103543 ============ PULL DRAM RESETB DOWN ============
4934 09:58:41.107257 ========== PULL DRAM RESETB DOWN end =========
4935 09:58:41.110401 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4936 09:58:41.114093 ===================================
4937 09:58:41.117247 LPDDR4 DRAM CONFIGURATION
4938 09:58:41.120524 ===================================
4939 09:58:41.123753 EX_ROW_EN[0] = 0x0
4940 09:58:41.123827 EX_ROW_EN[1] = 0x0
4941 09:58:41.127166 LP4Y_EN = 0x0
4942 09:58:41.127269 WORK_FSP = 0x0
4943 09:58:41.130299 WL = 0x3
4944 09:58:41.130418 RL = 0x3
4945 09:58:41.133588 BL = 0x2
4946 09:58:41.133668 RPST = 0x0
4947 09:58:41.137208 RD_PRE = 0x0
4948 09:58:41.137289 WR_PRE = 0x1
4949 09:58:41.140522 WR_PST = 0x0
4950 09:58:41.140600 DBI_WR = 0x0
4951 09:58:41.143602 DBI_RD = 0x0
4952 09:58:41.143686 OTF = 0x1
4953 09:58:41.147016 ===================================
4954 09:58:41.150537 ===================================
4955 09:58:41.153937 ANA top config
4956 09:58:41.156995 ===================================
4957 09:58:41.160488 DLL_ASYNC_EN = 0
4958 09:58:41.160561 ALL_SLAVE_EN = 1
4959 09:58:41.163484 NEW_RANK_MODE = 1
4960 09:58:41.167151 DLL_IDLE_MODE = 1
4961 09:58:41.170604 LP45_APHY_COMB_EN = 1
4962 09:58:41.170713 TX_ODT_DIS = 1
4963 09:58:41.173717 NEW_8X_MODE = 1
4964 09:58:41.177310 ===================================
4965 09:58:41.180481 ===================================
4966 09:58:41.183531 data_rate = 1866
4967 09:58:41.187271 CKR = 1
4968 09:58:41.190363 DQ_P2S_RATIO = 8
4969 09:58:41.193481 ===================================
4970 09:58:41.197235 CA_P2S_RATIO = 8
4971 09:58:41.197317 DQ_CA_OPEN = 0
4972 09:58:41.200457 DQ_SEMI_OPEN = 0
4973 09:58:41.203517 CA_SEMI_OPEN = 0
4974 09:58:41.207209 CA_FULL_RATE = 0
4975 09:58:41.210189 DQ_CKDIV4_EN = 1
4976 09:58:41.213824 CA_CKDIV4_EN = 1
4977 09:58:41.213895 CA_PREDIV_EN = 0
4978 09:58:41.217160 PH8_DLY = 0
4979 09:58:41.220795 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4980 09:58:41.223844 DQ_AAMCK_DIV = 4
4981 09:58:41.226780 CA_AAMCK_DIV = 4
4982 09:58:41.230343 CA_ADMCK_DIV = 4
4983 09:58:41.230413 DQ_TRACK_CA_EN = 0
4984 09:58:41.233875 CA_PICK = 933
4985 09:58:41.237321 CA_MCKIO = 933
4986 09:58:41.240364 MCKIO_SEMI = 0
4987 09:58:41.243848 PLL_FREQ = 3732
4988 09:58:41.247111 DQ_UI_PI_RATIO = 32
4989 09:58:41.250225 CA_UI_PI_RATIO = 0
4990 09:58:41.253846 ===================================
4991 09:58:41.253922 ===================================
4992 09:58:41.257135 memory_type:LPDDR4
4993 09:58:41.260512 GP_NUM : 10
4994 09:58:41.260599 SRAM_EN : 1
4995 09:58:41.263835 MD32_EN : 0
4996 09:58:41.267481 ===================================
4997 09:58:41.270631 [ANA_INIT] >>>>>>>>>>>>>>
4998 09:58:41.273886 <<<<<< [CONFIGURE PHASE]: ANA_TX
4999 09:58:41.277446 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5000 09:58:41.280670 ===================================
5001 09:58:41.280756 data_rate = 1866,PCW = 0X8f00
5002 09:58:41.284158 ===================================
5003 09:58:41.287415 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5004 09:58:41.294227 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5005 09:58:41.300330 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5006 09:58:41.304188 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5007 09:58:41.307401 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5008 09:58:41.310418 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5009 09:58:41.313513 [ANA_INIT] flow start
5010 09:58:41.317294 [ANA_INIT] PLL >>>>>>>>
5011 09:58:41.317380 [ANA_INIT] PLL <<<<<<<<
5012 09:58:41.320360 [ANA_INIT] MIDPI >>>>>>>>
5013 09:58:41.323583 [ANA_INIT] MIDPI <<<<<<<<
5014 09:58:41.323670 [ANA_INIT] DLL >>>>>>>>
5015 09:58:41.327425 [ANA_INIT] flow end
5016 09:58:41.330453 ============ LP4 DIFF to SE enter ============
5017 09:58:41.334086 ============ LP4 DIFF to SE exit ============
5018 09:58:41.337020 [ANA_INIT] <<<<<<<<<<<<<
5019 09:58:41.340566 [Flow] Enable top DCM control >>>>>
5020 09:58:41.343597 [Flow] Enable top DCM control <<<<<
5021 09:58:41.346984 Enable DLL master slave shuffle
5022 09:58:41.353320 ==============================================================
5023 09:58:41.353430 Gating Mode config
5024 09:58:41.360175 ==============================================================
5025 09:58:41.360287 Config description:
5026 09:58:41.370249 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5027 09:58:41.377045 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5028 09:58:41.383357 SELPH_MODE 0: By rank 1: By Phase
5029 09:58:41.386910 ==============================================================
5030 09:58:41.390011 GAT_TRACK_EN = 1
5031 09:58:41.393450 RX_GATING_MODE = 2
5032 09:58:41.396673 RX_GATING_TRACK_MODE = 2
5033 09:58:41.400394 SELPH_MODE = 1
5034 09:58:41.403578 PICG_EARLY_EN = 1
5035 09:58:41.406920 VALID_LAT_VALUE = 1
5036 09:58:41.413499 ==============================================================
5037 09:58:41.416642 Enter into Gating configuration >>>>
5038 09:58:41.416718 Exit from Gating configuration <<<<
5039 09:58:41.420206 Enter into DVFS_PRE_config >>>>>
5040 09:58:41.433328 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5041 09:58:41.436683 Exit from DVFS_PRE_config <<<<<
5042 09:58:41.439926 Enter into PICG configuration >>>>
5043 09:58:41.443708 Exit from PICG configuration <<<<
5044 09:58:41.443788 [RX_INPUT] configuration >>>>>
5045 09:58:41.446735 [RX_INPUT] configuration <<<<<
5046 09:58:41.453149 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5047 09:58:41.456517 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5048 09:58:41.463150 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5049 09:58:41.470250 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5050 09:58:41.476548 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5051 09:58:41.483582 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5052 09:58:41.486915 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5053 09:58:41.490243 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5054 09:58:41.493869 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5055 09:58:41.500610 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5056 09:58:41.503465 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5057 09:58:41.506774 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5058 09:58:41.510103 ===================================
5059 09:58:41.513829 LPDDR4 DRAM CONFIGURATION
5060 09:58:41.517023 ===================================
5061 09:58:41.517101 EX_ROW_EN[0] = 0x0
5062 09:58:41.519982 EX_ROW_EN[1] = 0x0
5063 09:58:41.523700 LP4Y_EN = 0x0
5064 09:58:41.523774 WORK_FSP = 0x0
5065 09:58:41.526794 WL = 0x3
5066 09:58:41.526900 RL = 0x3
5067 09:58:41.530421 BL = 0x2
5068 09:58:41.530519 RPST = 0x0
5069 09:58:41.533850 RD_PRE = 0x0
5070 09:58:41.533953 WR_PRE = 0x1
5071 09:58:41.536844 WR_PST = 0x0
5072 09:58:41.536915 DBI_WR = 0x0
5073 09:58:41.540511 DBI_RD = 0x0
5074 09:58:41.540582 OTF = 0x1
5075 09:58:41.543416 ===================================
5076 09:58:41.547064 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5077 09:58:41.553894 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5078 09:58:41.557008 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5079 09:58:41.560502 ===================================
5080 09:58:41.563558 LPDDR4 DRAM CONFIGURATION
5081 09:58:41.567338 ===================================
5082 09:58:41.567415 EX_ROW_EN[0] = 0x10
5083 09:58:41.570445 EX_ROW_EN[1] = 0x0
5084 09:58:41.570517 LP4Y_EN = 0x0
5085 09:58:41.574080 WORK_FSP = 0x0
5086 09:58:41.574185 WL = 0x3
5087 09:58:41.576896 RL = 0x3
5088 09:58:41.577027 BL = 0x2
5089 09:58:41.580417 RPST = 0x0
5090 09:58:41.583962 RD_PRE = 0x0
5091 09:58:41.584034 WR_PRE = 0x1
5092 09:58:41.587070 WR_PST = 0x0
5093 09:58:41.587173 DBI_WR = 0x0
5094 09:58:41.590629 DBI_RD = 0x0
5095 09:58:41.590725 OTF = 0x1
5096 09:58:41.594072 ===================================
5097 09:58:41.600469 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5098 09:58:41.604305 nWR fixed to 30
5099 09:58:41.607259 [ModeRegInit_LP4] CH0 RK0
5100 09:58:41.607350 [ModeRegInit_LP4] CH0 RK1
5101 09:58:41.610943 [ModeRegInit_LP4] CH1 RK0
5102 09:58:41.613862 [ModeRegInit_LP4] CH1 RK1
5103 09:58:41.613970 match AC timing 9
5104 09:58:41.620569 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5105 09:58:41.624304 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5106 09:58:41.627414 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5107 09:58:41.634309 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5108 09:58:41.637367 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5109 09:58:41.637443 ==
5110 09:58:41.640454 Dram Type= 6, Freq= 0, CH_0, rank 0
5111 09:58:41.644217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5112 09:58:41.644305 ==
5113 09:58:41.650884 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5114 09:58:41.657593 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5115 09:58:41.660565 [CA 0] Center 38 (8~69) winsize 62
5116 09:58:41.664454 [CA 1] Center 37 (7~68) winsize 62
5117 09:58:41.667380 [CA 2] Center 35 (5~66) winsize 62
5118 09:58:41.670838 [CA 3] Center 35 (4~66) winsize 63
5119 09:58:41.673788 [CA 4] Center 34 (4~64) winsize 61
5120 09:58:41.677211 [CA 5] Center 34 (4~64) winsize 61
5121 09:58:41.677335
5122 09:58:41.680699 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5123 09:58:41.680774
5124 09:58:41.684281 [CATrainingPosCal] consider 1 rank data
5125 09:58:41.687497 u2DelayCellTimex100 = 270/100 ps
5126 09:58:41.691036 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5127 09:58:41.694309 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5128 09:58:41.697171 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5129 09:58:41.700936 CA3 delay=35 (4~66),Diff = 1 PI (6 cell)
5130 09:58:41.703883 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5131 09:58:41.707361 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5132 09:58:41.707466
5133 09:58:41.710556 CA PerBit enable=1, Macro0, CA PI delay=34
5134 09:58:41.713911
5135 09:58:41.713987 [CBTSetCACLKResult] CA Dly = 34
5136 09:58:41.717609 CS Dly: 6 (0~37)
5137 09:58:41.717712 ==
5138 09:58:41.720787 Dram Type= 6, Freq= 0, CH_0, rank 1
5139 09:58:41.724134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5140 09:58:41.724233 ==
5141 09:58:41.731089 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5142 09:58:41.737920 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5143 09:58:41.740981 [CA 0] Center 38 (8~69) winsize 62
5144 09:58:41.744138 [CA 1] Center 38 (8~69) winsize 62
5145 09:58:41.747263 [CA 2] Center 35 (5~66) winsize 62
5146 09:58:41.750464 [CA 3] Center 35 (5~66) winsize 62
5147 09:58:41.754086 [CA 4] Center 34 (4~64) winsize 61
5148 09:58:41.757699 [CA 5] Center 33 (3~64) winsize 62
5149 09:58:41.757774
5150 09:58:41.760953 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5151 09:58:41.761022
5152 09:58:41.764162 [CATrainingPosCal] consider 2 rank data
5153 09:58:41.767235 u2DelayCellTimex100 = 270/100 ps
5154 09:58:41.770902 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5155 09:58:41.774051 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5156 09:58:41.777169 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5157 09:58:41.780758 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5158 09:58:41.784142 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5159 09:58:41.787420 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5160 09:58:41.787560
5161 09:58:41.790828 CA PerBit enable=1, Macro0, CA PI delay=34
5162 09:58:41.794213
5163 09:58:41.794285 [CBTSetCACLKResult] CA Dly = 34
5164 09:58:41.797474 CS Dly: 7 (0~39)
5165 09:58:41.797550
5166 09:58:41.801098 ----->DramcWriteLeveling(PI) begin...
5167 09:58:41.801171 ==
5168 09:58:41.804253 Dram Type= 6, Freq= 0, CH_0, rank 0
5169 09:58:41.807337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5170 09:58:41.807417 ==
5171 09:58:41.811059 Write leveling (Byte 0): 28 => 28
5172 09:58:41.814095 Write leveling (Byte 1): 25 => 25
5173 09:58:41.817471 DramcWriteLeveling(PI) end<-----
5174 09:58:41.817562
5175 09:58:41.817626 ==
5176 09:58:41.820921 Dram Type= 6, Freq= 0, CH_0, rank 0
5177 09:58:41.824588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5178 09:58:41.824658 ==
5179 09:58:41.827606 [Gating] SW mode calibration
5180 09:58:41.833998 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5181 09:58:41.840957 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5182 09:58:41.844329 0 14 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5183 09:58:41.850978 0 14 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5184 09:58:41.854741 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5185 09:58:41.857715 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5186 09:58:41.860699 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5187 09:58:41.867612 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5188 09:58:41.870708 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5189 09:58:41.874559 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
5190 09:58:41.880705 0 15 0 | B1->B0 | 3131 2d2d | 1 0 | (1 1) (0 0)
5191 09:58:41.884347 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5192 09:58:41.887397 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5193 09:58:41.894468 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5194 09:58:41.897331 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5195 09:58:41.901113 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5196 09:58:41.907775 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5197 09:58:41.910974 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5198 09:58:41.914613 1 0 0 | B1->B0 | 2c2c 3a3a | 0 1 | (0 0) (0 0)
5199 09:58:41.920799 1 0 4 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5200 09:58:41.924385 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5201 09:58:41.927768 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5202 09:58:41.934232 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5203 09:58:41.937995 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5204 09:58:41.940866 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5205 09:58:41.947551 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5206 09:58:41.950723 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5207 09:58:41.954479 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 09:58:41.957650 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 09:58:41.964458 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 09:58:41.967539 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 09:58:41.971324 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 09:58:41.977536 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 09:58:41.980659 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 09:58:41.984193 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 09:58:41.990855 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 09:58:41.994030 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 09:58:41.997749 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 09:58:42.004305 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 09:58:42.007918 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 09:58:42.010709 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5221 09:58:42.017421 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5222 09:58:42.021266 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5223 09:58:42.024473 Total UI for P1: 0, mck2ui 16
5224 09:58:42.028173 best dqsien dly found for B0: ( 1, 2, 26)
5225 09:58:42.031258 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5226 09:58:42.034518 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5227 09:58:42.037861 Total UI for P1: 0, mck2ui 16
5228 09:58:42.041033 best dqsien dly found for B1: ( 1, 3, 0)
5229 09:58:42.044262 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5230 09:58:42.047821 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5231 09:58:42.051314
5232 09:58:42.054503 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5233 09:58:42.057594 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5234 09:58:42.061341 [Gating] SW calibration Done
5235 09:58:42.061445 ==
5236 09:58:42.064425 Dram Type= 6, Freq= 0, CH_0, rank 0
5237 09:58:42.068191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5238 09:58:42.068272 ==
5239 09:58:42.068335 RX Vref Scan: 0
5240 09:58:42.068407
5241 09:58:42.071104 RX Vref 0 -> 0, step: 1
5242 09:58:42.071176
5243 09:58:42.074789 RX Delay -80 -> 252, step: 8
5244 09:58:42.077810 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5245 09:58:42.081144 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5246 09:58:42.084754 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5247 09:58:42.091041 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5248 09:58:42.094579 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5249 09:58:42.097789 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5250 09:58:42.101480 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5251 09:58:42.105073 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5252 09:58:42.108250 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5253 09:58:42.114843 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5254 09:58:42.118057 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5255 09:58:42.121461 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5256 09:58:42.124766 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5257 09:58:42.128111 iDelay=200, Bit 13, Center 91 (-8 ~ 191) 200
5258 09:58:42.131481 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5259 09:58:42.138316 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5260 09:58:42.138395 ==
5261 09:58:42.141220 Dram Type= 6, Freq= 0, CH_0, rank 0
5262 09:58:42.144734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5263 09:58:42.144808 ==
5264 09:58:42.144869 DQS Delay:
5265 09:58:42.147971 DQS0 = 0, DQS1 = 0
5266 09:58:42.148045 DQM Delay:
5267 09:58:42.151523 DQM0 = 97, DQM1 = 87
5268 09:58:42.151607 DQ Delay:
5269 09:58:42.154938 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =91
5270 09:58:42.158550 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5271 09:58:42.161396 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5272 09:58:42.165173 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5273 09:58:42.165250
5274 09:58:42.165313
5275 09:58:42.165378 ==
5276 09:58:42.168221 Dram Type= 6, Freq= 0, CH_0, rank 0
5277 09:58:42.171270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5278 09:58:42.171357 ==
5279 09:58:42.171453
5280 09:58:42.174972
5281 09:58:42.175054 TX Vref Scan disable
5282 09:58:42.178120 == TX Byte 0 ==
5283 09:58:42.181761 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5284 09:58:42.184856 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5285 09:58:42.187918 == TX Byte 1 ==
5286 09:58:42.191732 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5287 09:58:42.194853 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5288 09:58:42.195023 ==
5289 09:58:42.198020 Dram Type= 6, Freq= 0, CH_0, rank 0
5290 09:58:42.204886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5291 09:58:42.204963 ==
5292 09:58:42.205025
5293 09:58:42.205086
5294 09:58:42.205142 TX Vref Scan disable
5295 09:58:42.209152 == TX Byte 0 ==
5296 09:58:42.212118 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5297 09:58:42.215750 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5298 09:58:42.218695 == TX Byte 1 ==
5299 09:58:42.222476 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5300 09:58:42.225569 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5301 09:58:42.229185
5302 09:58:42.229256 [DATLAT]
5303 09:58:42.229320 Freq=933, CH0 RK0
5304 09:58:42.229381
5305 09:58:42.232349 DATLAT Default: 0xd
5306 09:58:42.232446 0, 0xFFFF, sum = 0
5307 09:58:42.235761 1, 0xFFFF, sum = 0
5308 09:58:42.235857 2, 0xFFFF, sum = 0
5309 09:58:42.239227 3, 0xFFFF, sum = 0
5310 09:58:42.239297 4, 0xFFFF, sum = 0
5311 09:58:42.242386 5, 0xFFFF, sum = 0
5312 09:58:42.242458 6, 0xFFFF, sum = 0
5313 09:58:42.245534 7, 0xFFFF, sum = 0
5314 09:58:42.249089 8, 0xFFFF, sum = 0
5315 09:58:42.249160 9, 0xFFFF, sum = 0
5316 09:58:42.249221 10, 0x0, sum = 1
5317 09:58:42.252548 11, 0x0, sum = 2
5318 09:58:42.252616 12, 0x0, sum = 3
5319 09:58:42.256006 13, 0x0, sum = 4
5320 09:58:42.256077 best_step = 11
5321 09:58:42.256136
5322 09:58:42.256193 ==
5323 09:58:42.259059 Dram Type= 6, Freq= 0, CH_0, rank 0
5324 09:58:42.265903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5325 09:58:42.265994 ==
5326 09:58:42.266061 RX Vref Scan: 1
5327 09:58:42.266122
5328 09:58:42.269367 RX Vref 0 -> 0, step: 1
5329 09:58:42.269438
5330 09:58:42.272722 RX Delay -61 -> 252, step: 4
5331 09:58:42.272790
5332 09:58:42.275659 Set Vref, RX VrefLevel [Byte0]: 53
5333 09:58:42.279121 [Byte1]: 49
5334 09:58:42.279237
5335 09:58:42.282302 Final RX Vref Byte 0 = 53 to rank0
5336 09:58:42.285961 Final RX Vref Byte 1 = 49 to rank0
5337 09:58:42.288967 Final RX Vref Byte 0 = 53 to rank1
5338 09:58:42.292584 Final RX Vref Byte 1 = 49 to rank1==
5339 09:58:42.295655 Dram Type= 6, Freq= 0, CH_0, rank 0
5340 09:58:42.299452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5341 09:58:42.299522 ==
5342 09:58:42.302550 DQS Delay:
5343 09:58:42.302628 DQS0 = 0, DQS1 = 0
5344 09:58:42.302689 DQM Delay:
5345 09:58:42.305777 DQM0 = 96, DQM1 = 87
5346 09:58:42.305874 DQ Delay:
5347 09:58:42.309093 DQ0 =98, DQ1 =98, DQ2 =92, DQ3 =94
5348 09:58:42.312577 DQ4 =98, DQ5 =86, DQ6 =104, DQ7 =102
5349 09:58:42.315765 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =80
5350 09:58:42.318871 DQ12 =94, DQ13 =90, DQ14 =102, DQ15 =98
5351 09:58:42.318954
5352 09:58:42.319016
5353 09:58:42.329273 [DQSOSCAuto] RK0, (LSB)MR18= 0x14ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 415 ps
5354 09:58:42.332274 CH0 RK0: MR19=504, MR18=14FF
5355 09:58:42.335866 CH0_RK0: MR19=0x504, MR18=0x14FF, DQSOSC=415, MR23=63, INC=62, DEC=41
5356 09:58:42.335940
5357 09:58:42.339035 ----->DramcWriteLeveling(PI) begin...
5358 09:58:42.342588 ==
5359 09:58:42.346031 Dram Type= 6, Freq= 0, CH_0, rank 1
5360 09:58:42.349476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5361 09:58:42.349553 ==
5362 09:58:42.352297 Write leveling (Byte 0): 30 => 30
5363 09:58:42.356068 Write leveling (Byte 1): 29 => 29
5364 09:58:42.359445 DramcWriteLeveling(PI) end<-----
5365 09:58:42.359524
5366 09:58:42.359586 ==
5367 09:58:42.362512 Dram Type= 6, Freq= 0, CH_0, rank 1
5368 09:58:42.365728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5369 09:58:42.365799 ==
5370 09:58:42.368999 [Gating] SW mode calibration
5371 09:58:42.376180 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5372 09:58:42.379464 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5373 09:58:42.385921 0 14 0 | B1->B0 | 2424 3434 | 1 1 | (0 0) (1 1)
5374 09:58:42.388926 0 14 4 | B1->B0 | 3130 3434 | 1 1 | (0 0) (1 1)
5375 09:58:42.392663 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5376 09:58:42.399339 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5377 09:58:42.402691 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5378 09:58:42.405715 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5379 09:58:42.412370 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5380 09:58:42.416209 0 14 28 | B1->B0 | 3333 2b2b | 0 1 | (0 0) (1 0)
5381 09:58:42.419280 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
5382 09:58:42.426020 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5383 09:58:42.429643 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5384 09:58:42.432795 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5385 09:58:42.436360 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5386 09:58:42.443276 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5387 09:58:42.446181 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5388 09:58:42.449392 0 15 28 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
5389 09:58:42.455882 1 0 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
5390 09:58:42.459359 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5391 09:58:42.462792 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5392 09:58:42.469348 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5393 09:58:42.473351 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5394 09:58:42.476170 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5395 09:58:42.483135 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5396 09:58:42.486076 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5397 09:58:42.489433 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5398 09:58:42.496067 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5399 09:58:42.499694 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 09:58:42.502938 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 09:58:42.509747 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 09:58:42.512741 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 09:58:42.516562 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 09:58:42.523015 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 09:58:42.526118 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 09:58:42.529690 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 09:58:42.532765 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 09:58:42.539384 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 09:58:42.542893 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 09:58:42.546028 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 09:58:42.552765 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5412 09:58:42.556301 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5413 09:58:42.559459 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5414 09:58:42.566517 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5415 09:58:42.566599 Total UI for P1: 0, mck2ui 16
5416 09:58:42.573031 best dqsien dly found for B0: ( 1, 2, 28)
5417 09:58:42.576338 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5418 09:58:42.579914 Total UI for P1: 0, mck2ui 16
5419 09:58:42.582930 best dqsien dly found for B1: ( 1, 3, 2)
5420 09:58:42.586731 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5421 09:58:42.589973 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5422 09:58:42.590055
5423 09:58:42.593321 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5424 09:58:42.596399 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5425 09:58:42.600185 [Gating] SW calibration Done
5426 09:58:42.600269 ==
5427 09:58:42.602928 Dram Type= 6, Freq= 0, CH_0, rank 1
5428 09:58:42.606349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5429 09:58:42.606437 ==
5430 09:58:42.609730 RX Vref Scan: 0
5431 09:58:42.609841
5432 09:58:42.613394 RX Vref 0 -> 0, step: 1
5433 09:58:42.613475
5434 09:58:42.613540 RX Delay -80 -> 252, step: 8
5435 09:58:42.619599 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5436 09:58:42.623255 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5437 09:58:42.626909 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5438 09:58:42.630107 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5439 09:58:42.633144 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5440 09:58:42.636256 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5441 09:58:42.640107 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5442 09:58:42.646775 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5443 09:58:42.649961 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5444 09:58:42.653591 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5445 09:58:42.656744 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5446 09:58:42.660301 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5447 09:58:42.666829 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5448 09:58:42.669880 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5449 09:58:42.673441 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5450 09:58:42.676499 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5451 09:58:42.676596 ==
5452 09:58:42.679935 Dram Type= 6, Freq= 0, CH_0, rank 1
5453 09:58:42.683261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5454 09:58:42.683359 ==
5455 09:58:42.686811 DQS Delay:
5456 09:58:42.686947 DQS0 = 0, DQS1 = 0
5457 09:58:42.689919 DQM Delay:
5458 09:58:42.690023 DQM0 = 97, DQM1 = 86
5459 09:58:42.690113 DQ Delay:
5460 09:58:42.693614 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =91
5461 09:58:42.696730 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =103
5462 09:58:42.700170 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =75
5463 09:58:42.703468 DQ12 =87, DQ13 =91, DQ14 =99, DQ15 =95
5464 09:58:42.703545
5465 09:58:42.703630
5466 09:58:42.706775 ==
5467 09:58:42.710426 Dram Type= 6, Freq= 0, CH_0, rank 1
5468 09:58:42.713691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5469 09:58:42.713771 ==
5470 09:58:42.713845
5471 09:58:42.713910
5472 09:58:42.716587 TX Vref Scan disable
5473 09:58:42.716687 == TX Byte 0 ==
5474 09:58:42.720109 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5475 09:58:42.727093 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5476 09:58:42.727260 == TX Byte 1 ==
5477 09:58:42.730487 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5478 09:58:42.736763 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5479 09:58:42.736872 ==
5480 09:58:42.740414 Dram Type= 6, Freq= 0, CH_0, rank 1
5481 09:58:42.743409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5482 09:58:42.743490 ==
5483 09:58:42.743552
5484 09:58:42.743619
5485 09:58:42.747166 TX Vref Scan disable
5486 09:58:42.750177 == TX Byte 0 ==
5487 09:58:42.753873 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5488 09:58:42.756942 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5489 09:58:42.760039 == TX Byte 1 ==
5490 09:58:42.763504 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5491 09:58:42.767089 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5492 09:58:42.767218
5493 09:58:42.767326 [DATLAT]
5494 09:58:42.770159 Freq=933, CH0 RK1
5495 09:58:42.770236
5496 09:58:42.770304 DATLAT Default: 0xb
5497 09:58:42.773832 0, 0xFFFF, sum = 0
5498 09:58:42.773924 1, 0xFFFF, sum = 0
5499 09:58:42.777305 2, 0xFFFF, sum = 0
5500 09:58:42.780523 3, 0xFFFF, sum = 0
5501 09:58:42.780597 4, 0xFFFF, sum = 0
5502 09:58:42.783731 5, 0xFFFF, sum = 0
5503 09:58:42.783812 6, 0xFFFF, sum = 0
5504 09:58:42.787266 7, 0xFFFF, sum = 0
5505 09:58:42.787338 8, 0xFFFF, sum = 0
5506 09:58:42.790247 9, 0xFFFF, sum = 0
5507 09:58:42.790358 10, 0x0, sum = 1
5508 09:58:42.793587 11, 0x0, sum = 2
5509 09:58:42.793674 12, 0x0, sum = 3
5510 09:58:42.793746 13, 0x0, sum = 4
5511 09:58:42.797120 best_step = 11
5512 09:58:42.797234
5513 09:58:42.797329 ==
5514 09:58:42.800856 Dram Type= 6, Freq= 0, CH_0, rank 1
5515 09:58:42.804059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5516 09:58:42.804143 ==
5517 09:58:42.807176 RX Vref Scan: 0
5518 09:58:42.807280
5519 09:58:42.807376 RX Vref 0 -> 0, step: 1
5520 09:58:42.807475
5521 09:58:42.810565 RX Delay -61 -> 252, step: 4
5522 09:58:42.818061 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5523 09:58:42.821221 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5524 09:58:42.824682 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5525 09:58:42.828195 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5526 09:58:42.831224 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5527 09:58:42.834439 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5528 09:58:42.841321 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5529 09:58:42.844451 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5530 09:58:42.848034 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5531 09:58:42.851141 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5532 09:58:42.854834 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5533 09:58:42.857909 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5534 09:58:42.864593 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5535 09:58:42.867663 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5536 09:58:42.871210 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5537 09:58:42.874908 iDelay=199, Bit 15, Center 96 (11 ~ 182) 172
5538 09:58:42.875014 ==
5539 09:58:42.877950 Dram Type= 6, Freq= 0, CH_0, rank 1
5540 09:58:42.881430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5541 09:58:42.884571 ==
5542 09:58:42.884644 DQS Delay:
5543 09:58:42.884708 DQS0 = 0, DQS1 = 0
5544 09:58:42.888185 DQM Delay:
5545 09:58:42.888251 DQM0 = 95, DQM1 = 88
5546 09:58:42.891275 DQ Delay:
5547 09:58:42.891340 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5548 09:58:42.894946 DQ4 =94, DQ5 =84, DQ6 =104, DQ7 =102
5549 09:58:42.897911 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =80
5550 09:58:42.901290 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =96
5551 09:58:42.904450
5552 09:58:42.904525
5553 09:58:42.911286 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d0a, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 412 ps
5554 09:58:42.914808 CH0 RK1: MR19=505, MR18=1D0A
5555 09:58:42.921074 CH0_RK1: MR19=0x505, MR18=0x1D0A, DQSOSC=412, MR23=63, INC=63, DEC=42
5556 09:58:42.924657 [RxdqsGatingPostProcess] freq 933
5557 09:58:42.927799 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5558 09:58:42.931213 best DQS0 dly(2T, 0.5T) = (0, 10)
5559 09:58:42.934788 best DQS1 dly(2T, 0.5T) = (0, 11)
5560 09:58:42.937791 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5561 09:58:42.941457 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5562 09:58:42.944501 best DQS0 dly(2T, 0.5T) = (0, 10)
5563 09:58:42.948183 best DQS1 dly(2T, 0.5T) = (0, 11)
5564 09:58:42.951383 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5565 09:58:42.954886 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5566 09:58:42.957933 Pre-setting of DQS Precalculation
5567 09:58:42.961632 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5568 09:58:42.961724 ==
5569 09:58:42.964842 Dram Type= 6, Freq= 0, CH_1, rank 0
5570 09:58:42.967859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5571 09:58:42.971407 ==
5572 09:58:42.974460 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5573 09:58:42.980995 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5574 09:58:42.984650 [CA 0] Center 36 (6~67) winsize 62
5575 09:58:42.988169 [CA 1] Center 36 (6~67) winsize 62
5576 09:58:42.991317 [CA 2] Center 34 (4~64) winsize 61
5577 09:58:42.994406 [CA 3] Center 34 (4~64) winsize 61
5578 09:58:42.997687 [CA 4] Center 34 (4~64) winsize 61
5579 09:58:43.001376 [CA 5] Center 33 (3~64) winsize 62
5580 09:58:43.001463
5581 09:58:43.004461 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5582 09:58:43.004541
5583 09:58:43.008240 [CATrainingPosCal] consider 1 rank data
5584 09:58:43.011162 u2DelayCellTimex100 = 270/100 ps
5585 09:58:43.014493 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5586 09:58:43.018107 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5587 09:58:43.021158 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5588 09:58:43.024973 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5589 09:58:43.028064 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5590 09:58:43.034877 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5591 09:58:43.034960
5592 09:58:43.037775 CA PerBit enable=1, Macro0, CA PI delay=33
5593 09:58:43.037854
5594 09:58:43.041673 [CBTSetCACLKResult] CA Dly = 33
5595 09:58:43.041756 CS Dly: 4 (0~35)
5596 09:58:43.041836 ==
5597 09:58:43.044960 Dram Type= 6, Freq= 0, CH_1, rank 1
5598 09:58:43.048067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5599 09:58:43.048176 ==
5600 09:58:43.054746 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5601 09:58:43.061665 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5602 09:58:43.064606 [CA 0] Center 36 (6~67) winsize 62
5603 09:58:43.067760 [CA 1] Center 36 (6~67) winsize 62
5604 09:58:43.071531 [CA 2] Center 33 (3~64) winsize 62
5605 09:58:43.074435 [CA 3] Center 33 (3~64) winsize 62
5606 09:58:43.077991 [CA 4] Center 34 (3~65) winsize 63
5607 09:58:43.081560 [CA 5] Center 33 (3~63) winsize 61
5608 09:58:43.081672
5609 09:58:43.084628 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5610 09:58:43.084716
5611 09:58:43.088241 [CATrainingPosCal] consider 2 rank data
5612 09:58:43.091250 u2DelayCellTimex100 = 270/100 ps
5613 09:58:43.094972 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5614 09:58:43.098184 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5615 09:58:43.101174 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5616 09:58:43.105011 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5617 09:58:43.107884 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5618 09:58:43.111135 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5619 09:58:43.114766
5620 09:58:43.118004 CA PerBit enable=1, Macro0, CA PI delay=33
5621 09:58:43.118088
5622 09:58:43.121209 [CBTSetCACLKResult] CA Dly = 33
5623 09:58:43.121292 CS Dly: 5 (0~38)
5624 09:58:43.121357
5625 09:58:43.124516 ----->DramcWriteLeveling(PI) begin...
5626 09:58:43.124614 ==
5627 09:58:43.127883 Dram Type= 6, Freq= 0, CH_1, rank 0
5628 09:58:43.131641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5629 09:58:43.134636 ==
5630 09:58:43.134745 Write leveling (Byte 0): 27 => 27
5631 09:58:43.138267 Write leveling (Byte 1): 29 => 29
5632 09:58:43.141570 DramcWriteLeveling(PI) end<-----
5633 09:58:43.141680
5634 09:58:43.141744 ==
5635 09:58:43.145035 Dram Type= 6, Freq= 0, CH_1, rank 0
5636 09:58:43.151222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5637 09:58:43.151310 ==
5638 09:58:43.151382 [Gating] SW mode calibration
5639 09:58:43.161389 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5640 09:58:43.165128 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5641 09:58:43.168494 0 14 0 | B1->B0 | 2d2d 3030 | 0 0 | (0 0) (1 1)
5642 09:58:43.174752 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5643 09:58:43.178502 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5644 09:58:43.182113 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5645 09:58:43.188199 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5646 09:58:43.191877 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5647 09:58:43.195395 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5648 09:58:43.201622 0 14 28 | B1->B0 | 3131 3131 | 1 1 | (1 1) (1 1)
5649 09:58:43.204864 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5650 09:58:43.208632 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5651 09:58:43.214900 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5652 09:58:43.218646 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5653 09:58:43.221801 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5654 09:58:43.224937 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5655 09:58:43.231434 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5656 09:58:43.234784 0 15 28 | B1->B0 | 2c2c 2c2c | 0 0 | (0 0) (0 0)
5657 09:58:43.238257 1 0 0 | B1->B0 | 4444 4343 | 0 0 | (0 0) (0 0)
5658 09:58:43.245065 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5659 09:58:43.248544 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5660 09:58:43.251931 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5661 09:58:43.258439 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5662 09:58:43.261969 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5663 09:58:43.265571 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5664 09:58:43.272035 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5665 09:58:43.274990 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5666 09:58:43.278567 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 09:58:43.285444 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 09:58:43.288595 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 09:58:43.291719 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 09:58:43.298915 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 09:58:43.301893 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 09:58:43.305005 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 09:58:43.308796 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 09:58:43.315555 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 09:58:43.318679 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 09:58:43.321852 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 09:58:43.328975 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 09:58:43.331993 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 09:58:43.334968 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5680 09:58:43.342341 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5681 09:58:43.344976 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5682 09:58:43.348399 Total UI for P1: 0, mck2ui 16
5683 09:58:43.351745 best dqsien dly found for B0: ( 1, 2, 26)
5684 09:58:43.354976 Total UI for P1: 0, mck2ui 16
5685 09:58:43.358528 best dqsien dly found for B1: ( 1, 2, 26)
5686 09:58:43.362073 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5687 09:58:43.365132 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5688 09:58:43.365246
5689 09:58:43.368648 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5690 09:58:43.372800 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5691 09:58:43.375406 [Gating] SW calibration Done
5692 09:58:43.375528 ==
5693 09:58:43.378388 Dram Type= 6, Freq= 0, CH_1, rank 0
5694 09:58:43.381899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5695 09:58:43.384989 ==
5696 09:58:43.385073 RX Vref Scan: 0
5697 09:58:43.385138
5698 09:58:43.388585 RX Vref 0 -> 0, step: 1
5699 09:58:43.388668
5700 09:58:43.388733 RX Delay -80 -> 252, step: 8
5701 09:58:43.395281 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5702 09:58:43.398981 iDelay=200, Bit 1, Center 95 (0 ~ 191) 192
5703 09:58:43.401939 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5704 09:58:43.405444 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5705 09:58:43.408588 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5706 09:58:43.412301 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5707 09:58:43.418555 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5708 09:58:43.422361 iDelay=200, Bit 7, Center 95 (0 ~ 191) 192
5709 09:58:43.425481 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5710 09:58:43.428773 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5711 09:58:43.432494 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5712 09:58:43.435684 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5713 09:58:43.442426 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5714 09:58:43.445472 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5715 09:58:43.449191 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5716 09:58:43.452168 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5717 09:58:43.452248 ==
5718 09:58:43.455715 Dram Type= 6, Freq= 0, CH_1, rank 0
5719 09:58:43.459343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5720 09:58:43.459447 ==
5721 09:58:43.462193 DQS Delay:
5722 09:58:43.462296 DQS0 = 0, DQS1 = 0
5723 09:58:43.465748 DQM Delay:
5724 09:58:43.465850 DQM0 = 96, DQM1 = 88
5725 09:58:43.465940 DQ Delay:
5726 09:58:43.469061 DQ0 =99, DQ1 =95, DQ2 =83, DQ3 =95
5727 09:58:43.472104 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =95
5728 09:58:43.475869 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5729 09:58:43.478832 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5730 09:58:43.478946
5731 09:58:43.479039
5732 09:58:43.482302 ==
5733 09:58:43.485854 Dram Type= 6, Freq= 0, CH_1, rank 0
5734 09:58:43.489173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5735 09:58:43.489261 ==
5736 09:58:43.489345
5737 09:58:43.489408
5738 09:58:43.492189 TX Vref Scan disable
5739 09:58:43.492263 == TX Byte 0 ==
5740 09:58:43.495961 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5741 09:58:43.502399 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5742 09:58:43.502478 == TX Byte 1 ==
5743 09:58:43.505500 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5744 09:58:43.512639 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5745 09:58:43.512735 ==
5746 09:58:43.515803 Dram Type= 6, Freq= 0, CH_1, rank 0
5747 09:58:43.518788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 09:58:43.518881 ==
5749 09:58:43.518948
5750 09:58:43.519046
5751 09:58:43.522581 TX Vref Scan disable
5752 09:58:43.525877 == TX Byte 0 ==
5753 09:58:43.529329 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5754 09:58:43.532437 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5755 09:58:43.535657 == TX Byte 1 ==
5756 09:58:43.539419 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5757 09:58:43.542404 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5758 09:58:43.542489
5759 09:58:43.542555 [DATLAT]
5760 09:58:43.546136 Freq=933, CH1 RK0
5761 09:58:43.546220
5762 09:58:43.546287 DATLAT Default: 0xd
5763 09:58:43.549476 0, 0xFFFF, sum = 0
5764 09:58:43.549562 1, 0xFFFF, sum = 0
5765 09:58:43.552448 2, 0xFFFF, sum = 0
5766 09:58:43.552534 3, 0xFFFF, sum = 0
5767 09:58:43.556149 4, 0xFFFF, sum = 0
5768 09:58:43.559221 5, 0xFFFF, sum = 0
5769 09:58:43.559318 6, 0xFFFF, sum = 0
5770 09:58:43.562449 7, 0xFFFF, sum = 0
5771 09:58:43.562536 8, 0xFFFF, sum = 0
5772 09:58:43.566114 9, 0xFFFF, sum = 0
5773 09:58:43.566200 10, 0x0, sum = 1
5774 09:58:43.568898 11, 0x0, sum = 2
5775 09:58:43.568983 12, 0x0, sum = 3
5776 09:58:43.569050 13, 0x0, sum = 4
5777 09:58:43.572680 best_step = 11
5778 09:58:43.572764
5779 09:58:43.572830 ==
5780 09:58:43.576208 Dram Type= 6, Freq= 0, CH_1, rank 0
5781 09:58:43.579482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5782 09:58:43.579567 ==
5783 09:58:43.582432 RX Vref Scan: 1
5784 09:58:43.582516
5785 09:58:43.582582 RX Vref 0 -> 0, step: 1
5786 09:58:43.585981
5787 09:58:43.586066 RX Delay -61 -> 252, step: 4
5788 09:58:43.586133
5789 09:58:43.589064 Set Vref, RX VrefLevel [Byte0]: 57
5790 09:58:43.592632 [Byte1]: 45
5791 09:58:43.596712
5792 09:58:43.596795 Final RX Vref Byte 0 = 57 to rank0
5793 09:58:43.600198 Final RX Vref Byte 1 = 45 to rank0
5794 09:58:43.603721 Final RX Vref Byte 0 = 57 to rank1
5795 09:58:43.607166 Final RX Vref Byte 1 = 45 to rank1==
5796 09:58:43.610296 Dram Type= 6, Freq= 0, CH_1, rank 0
5797 09:58:43.616693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5798 09:58:43.616783 ==
5799 09:58:43.616853 DQS Delay:
5800 09:58:43.616916 DQS0 = 0, DQS1 = 0
5801 09:58:43.620421 DQM Delay:
5802 09:58:43.620505 DQM0 = 97, DQM1 = 89
5803 09:58:43.623670 DQ Delay:
5804 09:58:43.626803 DQ0 =100, DQ1 =92, DQ2 =86, DQ3 =96
5805 09:58:43.630134 DQ4 =96, DQ5 =108, DQ6 =106, DQ7 =96
5806 09:58:43.633568 DQ8 =80, DQ9 =76, DQ10 =88, DQ11 =84
5807 09:58:43.636702 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =94
5808 09:58:43.636787
5809 09:58:43.636870
5810 09:58:43.643682 [DQSOSCAuto] RK0, (LSB)MR18= 0x12ee, (MSB)MR19= 0x504, tDQSOscB0 = 428 ps tDQSOscB1 = 416 ps
5811 09:58:43.646539 CH1 RK0: MR19=504, MR18=12EE
5812 09:58:43.653325 CH1_RK0: MR19=0x504, MR18=0x12EE, DQSOSC=416, MR23=63, INC=62, DEC=41
5813 09:58:43.653411
5814 09:58:43.657162 ----->DramcWriteLeveling(PI) begin...
5815 09:58:43.657249 ==
5816 09:58:43.660198 Dram Type= 6, Freq= 0, CH_1, rank 1
5817 09:58:43.663708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5818 09:58:43.663794 ==
5819 09:58:43.667113 Write leveling (Byte 0): 30 => 30
5820 09:58:43.670249 Write leveling (Byte 1): 28 => 28
5821 09:58:43.673669 DramcWriteLeveling(PI) end<-----
5822 09:58:43.673753
5823 09:58:43.673818 ==
5824 09:58:43.676992 Dram Type= 6, Freq= 0, CH_1, rank 1
5825 09:58:43.680254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5826 09:58:43.680344 ==
5827 09:58:43.684088 [Gating] SW mode calibration
5828 09:58:43.690205 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5829 09:58:43.696959 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5830 09:58:43.700188 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5831 09:58:43.703795 0 14 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5832 09:58:43.710616 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5833 09:58:43.713917 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5834 09:58:43.716731 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5835 09:58:43.723730 0 14 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5836 09:58:43.726821 0 14 24 | B1->B0 | 3232 2b2b | 0 1 | (0 0) (1 0)
5837 09:58:43.730429 0 14 28 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
5838 09:58:43.736923 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5839 09:58:43.740635 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5840 09:58:43.743784 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5841 09:58:43.750108 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5842 09:58:43.753986 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5843 09:58:43.757019 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5844 09:58:43.764058 0 15 24 | B1->B0 | 2424 3838 | 0 0 | (0 0) (0 0)
5845 09:58:43.766996 0 15 28 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5846 09:58:43.770168 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5847 09:58:43.773548 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5848 09:58:43.780339 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5849 09:58:43.783941 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5850 09:58:43.787500 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5851 09:58:43.794230 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5852 09:58:43.797504 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5853 09:58:43.800913 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 09:58:43.807443 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 09:58:43.811073 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 09:58:43.813950 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 09:58:43.820522 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 09:58:43.824180 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 09:58:43.827131 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 09:58:43.834180 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 09:58:43.837311 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 09:58:43.840306 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 09:58:43.847171 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 09:58:43.850350 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 09:58:43.854031 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 09:58:43.857216 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 09:58:43.864071 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 09:58:43.867245 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5869 09:58:43.870418 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5870 09:58:43.873992 Total UI for P1: 0, mck2ui 16
5871 09:58:43.877150 best dqsien dly found for B0: ( 1, 2, 24)
5872 09:58:43.880756 Total UI for P1: 0, mck2ui 16
5873 09:58:43.883851 best dqsien dly found for B1: ( 1, 2, 24)
5874 09:58:43.886901 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5875 09:58:43.890551 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5876 09:58:43.894021
5877 09:58:43.897191 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5878 09:58:43.900170 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5879 09:58:43.904028 [Gating] SW calibration Done
5880 09:58:43.904113 ==
5881 09:58:43.907097 Dram Type= 6, Freq= 0, CH_1, rank 1
5882 09:58:43.910230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5883 09:58:43.910342 ==
5884 09:58:43.910437 RX Vref Scan: 0
5885 09:58:43.910528
5886 09:58:43.913582 RX Vref 0 -> 0, step: 1
5887 09:58:43.913689
5888 09:58:43.916910 RX Delay -80 -> 252, step: 8
5889 09:58:43.920328 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5890 09:58:43.923762 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5891 09:58:43.930559 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5892 09:58:43.933548 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5893 09:58:43.937085 iDelay=200, Bit 4, Center 91 (-8 ~ 191) 200
5894 09:58:43.940540 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5895 09:58:43.943423 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5896 09:58:43.947152 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5897 09:58:43.953928 iDelay=200, Bit 8, Center 75 (-24 ~ 175) 200
5898 09:58:43.957079 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5899 09:58:43.960224 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5900 09:58:43.963983 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5901 09:58:43.966914 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5902 09:58:43.974014 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5903 09:58:43.974100 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5904 09:58:43.980470 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5905 09:58:43.980552 ==
5906 09:58:43.983745 Dram Type= 6, Freq= 0, CH_1, rank 1
5907 09:58:43.987452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5908 09:58:43.987537 ==
5909 09:58:43.987604 DQS Delay:
5910 09:58:43.990274 DQS0 = 0, DQS1 = 0
5911 09:58:43.990351 DQM Delay:
5912 09:58:43.993945 DQM0 = 93, DQM1 = 89
5913 09:58:43.994029 DQ Delay:
5914 09:58:43.997358 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =95
5915 09:58:44.000364 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =87
5916 09:58:44.003575 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5917 09:58:44.007499 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =95
5918 09:58:44.007577
5919 09:58:44.007648
5920 09:58:44.007710 ==
5921 09:58:44.010850 Dram Type= 6, Freq= 0, CH_1, rank 1
5922 09:58:44.013908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5923 09:58:44.013993 ==
5924 09:58:44.016964
5925 09:58:44.017043
5926 09:58:44.017106 TX Vref Scan disable
5927 09:58:44.020572 == TX Byte 0 ==
5928 09:58:44.023962 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5929 09:58:44.027358 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5930 09:58:44.031054 == TX Byte 1 ==
5931 09:58:44.034017 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5932 09:58:44.037228 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5933 09:58:44.037306 ==
5934 09:58:44.040380 Dram Type= 6, Freq= 0, CH_1, rank 1
5935 09:58:44.047386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5936 09:58:44.047475 ==
5937 09:58:44.047540
5938 09:58:44.047601
5939 09:58:44.047659 TX Vref Scan disable
5940 09:58:44.051160 == TX Byte 0 ==
5941 09:58:44.054781 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5942 09:58:44.057810 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5943 09:58:44.061478 == TX Byte 1 ==
5944 09:58:44.064837 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5945 09:58:44.068141 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5946 09:58:44.071549
5947 09:58:44.071625 [DATLAT]
5948 09:58:44.071689 Freq=933, CH1 RK1
5949 09:58:44.071750
5950 09:58:44.074550 DATLAT Default: 0xb
5951 09:58:44.074624 0, 0xFFFF, sum = 0
5952 09:58:44.078307 1, 0xFFFF, sum = 0
5953 09:58:44.078384 2, 0xFFFF, sum = 0
5954 09:58:44.081143 3, 0xFFFF, sum = 0
5955 09:58:44.081255 4, 0xFFFF, sum = 0
5956 09:58:44.084884 5, 0xFFFF, sum = 0
5957 09:58:44.084990 6, 0xFFFF, sum = 0
5958 09:58:44.087888 7, 0xFFFF, sum = 0
5959 09:58:44.091474 8, 0xFFFF, sum = 0
5960 09:58:44.091559 9, 0xFFFF, sum = 0
5961 09:58:44.094903 10, 0x0, sum = 1
5962 09:58:44.095005 11, 0x0, sum = 2
5963 09:58:44.095101 12, 0x0, sum = 3
5964 09:58:44.098263 13, 0x0, sum = 4
5965 09:58:44.098335 best_step = 11
5966 09:58:44.098397
5967 09:58:44.098479 ==
5968 09:58:44.101065 Dram Type= 6, Freq= 0, CH_1, rank 1
5969 09:58:44.108029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5970 09:58:44.108139 ==
5971 09:58:44.108231 RX Vref Scan: 0
5972 09:58:44.108337
5973 09:58:44.111634 RX Vref 0 -> 0, step: 1
5974 09:58:44.111715
5975 09:58:44.114468 RX Delay -69 -> 252, step: 4
5976 09:58:44.118223 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5977 09:58:44.124509 iDelay=199, Bit 1, Center 88 (-5 ~ 182) 188
5978 09:58:44.127930 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5979 09:58:44.131289 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5980 09:58:44.134758 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5981 09:58:44.137938 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5982 09:58:44.141636 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5983 09:58:44.144342 iDelay=199, Bit 7, Center 92 (3 ~ 182) 180
5984 09:58:44.151242 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5985 09:58:44.154650 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5986 09:58:44.158150 iDelay=199, Bit 10, Center 94 (7 ~ 182) 176
5987 09:58:44.161918 iDelay=199, Bit 11, Center 82 (-5 ~ 170) 176
5988 09:58:44.164689 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5989 09:58:44.168059 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
5990 09:58:44.175219 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5991 09:58:44.178078 iDelay=199, Bit 15, Center 98 (11 ~ 186) 176
5992 09:58:44.178164 ==
5993 09:58:44.181785 Dram Type= 6, Freq= 0, CH_1, rank 1
5994 09:58:44.184884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5995 09:58:44.184968 ==
5996 09:58:44.188438 DQS Delay:
5997 09:58:44.188520 DQS0 = 0, DQS1 = 0
5998 09:58:44.188587 DQM Delay:
5999 09:58:44.191353 DQM0 = 95, DQM1 = 90
6000 09:58:44.191434 DQ Delay:
6001 09:58:44.194892 DQ0 =98, DQ1 =88, DQ2 =86, DQ3 =94
6002 09:58:44.197962 DQ4 =96, DQ5 =106, DQ6 =102, DQ7 =92
6003 09:58:44.201497 DQ8 =78, DQ9 =80, DQ10 =94, DQ11 =82
6004 09:58:44.204631 DQ12 =96, DQ13 =98, DQ14 =98, DQ15 =98
6005 09:58:44.204715
6006 09:58:44.204784
6007 09:58:44.215325 [DQSOSCAuto] RK1, (LSB)MR18= 0xe17, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
6008 09:58:44.215418 CH1 RK1: MR19=505, MR18=E17
6009 09:58:44.221686 CH1_RK1: MR19=0x505, MR18=0xE17, DQSOSC=414, MR23=63, INC=63, DEC=42
6010 09:58:44.224625 [RxdqsGatingPostProcess] freq 933
6011 09:58:44.231888 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6012 09:58:44.234616 best DQS0 dly(2T, 0.5T) = (0, 10)
6013 09:58:44.238105 best DQS1 dly(2T, 0.5T) = (0, 10)
6014 09:58:44.241225 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6015 09:58:44.244702 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6016 09:58:44.244781 best DQS0 dly(2T, 0.5T) = (0, 10)
6017 09:58:44.247840 best DQS1 dly(2T, 0.5T) = (0, 10)
6018 09:58:44.251334 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6019 09:58:44.255046 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6020 09:58:44.257915 Pre-setting of DQS Precalculation
6021 09:58:44.264819 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6022 09:58:44.271514 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6023 09:58:44.277813 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6024 09:58:44.277985
6025 09:58:44.278059
6026 09:58:44.281206 [Calibration Summary] 1866 Mbps
6027 09:58:44.281318 CH 0, Rank 0
6028 09:58:44.284478 SW Impedance : PASS
6029 09:58:44.288126 DUTY Scan : NO K
6030 09:58:44.288208 ZQ Calibration : PASS
6031 09:58:44.291184 Jitter Meter : NO K
6032 09:58:44.294835 CBT Training : PASS
6033 09:58:44.294926 Write leveling : PASS
6034 09:58:44.298231 RX DQS gating : PASS
6035 09:58:44.301348 RX DQ/DQS(RDDQC) : PASS
6036 09:58:44.301452 TX DQ/DQS : PASS
6037 09:58:44.304272 RX DATLAT : PASS
6038 09:58:44.308007 RX DQ/DQS(Engine): PASS
6039 09:58:44.308087 TX OE : NO K
6040 09:58:44.310991 All Pass.
6041 09:58:44.311074
6042 09:58:44.311148 CH 0, Rank 1
6043 09:58:44.314733 SW Impedance : PASS
6044 09:58:44.314833 DUTY Scan : NO K
6045 09:58:44.317697 ZQ Calibration : PASS
6046 09:58:44.321102 Jitter Meter : NO K
6047 09:58:44.321209 CBT Training : PASS
6048 09:58:44.324458 Write leveling : PASS
6049 09:58:44.324534 RX DQS gating : PASS
6050 09:58:44.327975 RX DQ/DQS(RDDQC) : PASS
6051 09:58:44.331695 TX DQ/DQS : PASS
6052 09:58:44.331770 RX DATLAT : PASS
6053 09:58:44.334548 RX DQ/DQS(Engine): PASS
6054 09:58:44.338247 TX OE : NO K
6055 09:58:44.338349 All Pass.
6056 09:58:44.338449
6057 09:58:44.338539 CH 1, Rank 0
6058 09:58:44.341281 SW Impedance : PASS
6059 09:58:44.344716 DUTY Scan : NO K
6060 09:58:44.344790 ZQ Calibration : PASS
6061 09:58:44.348150 Jitter Meter : NO K
6062 09:58:44.351192 CBT Training : PASS
6063 09:58:44.351265 Write leveling : PASS
6064 09:58:44.354901 RX DQS gating : PASS
6065 09:58:44.357863 RX DQ/DQS(RDDQC) : PASS
6066 09:58:44.357936 TX DQ/DQS : PASS
6067 09:58:44.361462 RX DATLAT : PASS
6068 09:58:44.361564 RX DQ/DQS(Engine): PASS
6069 09:58:44.364685 TX OE : NO K
6070 09:58:44.364798 All Pass.
6071 09:58:44.364889
6072 09:58:44.368159 CH 1, Rank 1
6073 09:58:44.368259 SW Impedance : PASS
6074 09:58:44.371450 DUTY Scan : NO K
6075 09:58:44.374437 ZQ Calibration : PASS
6076 09:58:44.374510 Jitter Meter : NO K
6077 09:58:44.378147 CBT Training : PASS
6078 09:58:44.381398 Write leveling : PASS
6079 09:58:44.381476 RX DQS gating : PASS
6080 09:58:44.384748 RX DQ/DQS(RDDQC) : PASS
6081 09:58:44.388073 TX DQ/DQS : PASS
6082 09:58:44.388158 RX DATLAT : PASS
6083 09:58:44.391568 RX DQ/DQS(Engine): PASS
6084 09:58:44.395082 TX OE : NO K
6085 09:58:44.395194 All Pass.
6086 09:58:44.395347
6087 09:58:44.395472 DramC Write-DBI off
6088 09:58:44.398018 PER_BANK_REFRESH: Hybrid Mode
6089 09:58:44.401427 TX_TRACKING: ON
6090 09:58:44.408051 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6091 09:58:44.411718 [FAST_K] Save calibration result to emmc
6092 09:58:44.418455 dramc_set_vcore_voltage set vcore to 650000
6093 09:58:44.418570 Read voltage for 400, 6
6094 09:58:44.418661 Vio18 = 0
6095 09:58:44.421413 Vcore = 650000
6096 09:58:44.421497 Vdram = 0
6097 09:58:44.421562 Vddq = 0
6098 09:58:44.425372 Vmddr = 0
6099 09:58:44.428129 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6100 09:58:44.434562 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6101 09:58:44.438196 MEM_TYPE=3, freq_sel=20
6102 09:58:44.438324 sv_algorithm_assistance_LP4_800
6103 09:58:44.445080 ============ PULL DRAM RESETB DOWN ============
6104 09:58:44.448454 ========== PULL DRAM RESETB DOWN end =========
6105 09:58:44.451425 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6106 09:58:44.454854 ===================================
6107 09:58:44.458013 LPDDR4 DRAM CONFIGURATION
6108 09:58:44.461477 ===================================
6109 09:58:44.461559 EX_ROW_EN[0] = 0x0
6110 09:58:44.465078 EX_ROW_EN[1] = 0x0
6111 09:58:44.468141 LP4Y_EN = 0x0
6112 09:58:44.468254 WORK_FSP = 0x0
6113 09:58:44.471615 WL = 0x2
6114 09:58:44.471712 RL = 0x2
6115 09:58:44.475385 BL = 0x2
6116 09:58:44.475467 RPST = 0x0
6117 09:58:44.478263 RD_PRE = 0x0
6118 09:58:44.478361 WR_PRE = 0x1
6119 09:58:44.481670 WR_PST = 0x0
6120 09:58:44.481752 DBI_WR = 0x0
6121 09:58:44.485169 DBI_RD = 0x0
6122 09:58:44.485253 OTF = 0x1
6123 09:58:44.488633 ===================================
6124 09:58:44.491706 ===================================
6125 09:58:44.495110 ANA top config
6126 09:58:44.498785 ===================================
6127 09:58:44.498927 DLL_ASYNC_EN = 0
6128 09:58:44.501482 ALL_SLAVE_EN = 1
6129 09:58:44.505020 NEW_RANK_MODE = 1
6130 09:58:44.508374 DLL_IDLE_MODE = 1
6131 09:58:44.508456 LP45_APHY_COMB_EN = 1
6132 09:58:44.511769 TX_ODT_DIS = 1
6133 09:58:44.515056 NEW_8X_MODE = 1
6134 09:58:44.518641 ===================================
6135 09:58:44.522163 ===================================
6136 09:58:44.525282 data_rate = 800
6137 09:58:44.528943 CKR = 1
6138 09:58:44.531949 DQ_P2S_RATIO = 4
6139 09:58:44.535486 ===================================
6140 09:58:44.535569 CA_P2S_RATIO = 4
6141 09:58:44.538308 DQ_CA_OPEN = 0
6142 09:58:44.542021 DQ_SEMI_OPEN = 1
6143 09:58:44.545327 CA_SEMI_OPEN = 1
6144 09:58:44.549020 CA_FULL_RATE = 0
6145 09:58:44.549118 DQ_CKDIV4_EN = 0
6146 09:58:44.551825 CA_CKDIV4_EN = 1
6147 09:58:44.555314 CA_PREDIV_EN = 0
6148 09:58:44.558437 PH8_DLY = 0
6149 09:58:44.561996 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6150 09:58:44.565072 DQ_AAMCK_DIV = 0
6151 09:58:44.565187 CA_AAMCK_DIV = 0
6152 09:58:44.568541 CA_ADMCK_DIV = 4
6153 09:58:44.571567 DQ_TRACK_CA_EN = 0
6154 09:58:44.575091 CA_PICK = 800
6155 09:58:44.578594 CA_MCKIO = 400
6156 09:58:44.581655 MCKIO_SEMI = 400
6157 09:58:44.585248 PLL_FREQ = 3016
6158 09:58:44.588781 DQ_UI_PI_RATIO = 32
6159 09:58:44.588853 CA_UI_PI_RATIO = 32
6160 09:58:44.591742 ===================================
6161 09:58:44.595223 ===================================
6162 09:58:44.598649 memory_type:LPDDR4
6163 09:58:44.602093 GP_NUM : 10
6164 09:58:44.602188 SRAM_EN : 1
6165 09:58:44.605030 MD32_EN : 0
6166 09:58:44.608414 ===================================
6167 09:58:44.611943 [ANA_INIT] >>>>>>>>>>>>>>
6168 09:58:44.612026 <<<<<< [CONFIGURE PHASE]: ANA_TX
6169 09:58:44.615284 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6170 09:58:44.618575 ===================================
6171 09:58:44.621535 data_rate = 800,PCW = 0X7400
6172 09:58:44.625206 ===================================
6173 09:58:44.628193 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6174 09:58:44.634974 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6175 09:58:44.645440 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6176 09:58:44.651850 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6177 09:58:44.654578 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6178 09:58:44.658031 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6179 09:58:44.658137 [ANA_INIT] flow start
6180 09:58:44.661487 [ANA_INIT] PLL >>>>>>>>
6181 09:58:44.665089 [ANA_INIT] PLL <<<<<<<<
6182 09:58:44.668002 [ANA_INIT] MIDPI >>>>>>>>
6183 09:58:44.668075 [ANA_INIT] MIDPI <<<<<<<<
6184 09:58:44.671568 [ANA_INIT] DLL >>>>>>>>
6185 09:58:44.675152 [ANA_INIT] flow end
6186 09:58:44.678213 ============ LP4 DIFF to SE enter ============
6187 09:58:44.681839 ============ LP4 DIFF to SE exit ============
6188 09:58:44.684821 [ANA_INIT] <<<<<<<<<<<<<
6189 09:58:44.688384 [Flow] Enable top DCM control >>>>>
6190 09:58:44.691517 [Flow] Enable top DCM control <<<<<
6191 09:58:44.691630 Enable DLL master slave shuffle
6192 09:58:44.698103 ==============================================================
6193 09:58:44.701837 Gating Mode config
6194 09:58:44.705181 ==============================================================
6195 09:58:44.708560 Config description:
6196 09:58:44.718544 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6197 09:58:44.725466 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6198 09:58:44.728300 SELPH_MODE 0: By rank 1: By Phase
6199 09:58:44.735058 ==============================================================
6200 09:58:44.738489 GAT_TRACK_EN = 0
6201 09:58:44.741533 RX_GATING_MODE = 2
6202 09:58:44.745126 RX_GATING_TRACK_MODE = 2
6203 09:58:44.745213 SELPH_MODE = 1
6204 09:58:44.748800 PICG_EARLY_EN = 1
6205 09:58:44.751862 VALID_LAT_VALUE = 1
6206 09:58:44.758737 ==============================================================
6207 09:58:44.762207 Enter into Gating configuration >>>>
6208 09:58:44.765242 Exit from Gating configuration <<<<
6209 09:58:44.768471 Enter into DVFS_PRE_config >>>>>
6210 09:58:44.778491 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6211 09:58:44.782201 Exit from DVFS_PRE_config <<<<<
6212 09:58:44.785221 Enter into PICG configuration >>>>
6213 09:58:44.788703 Exit from PICG configuration <<<<
6214 09:58:44.792309 [RX_INPUT] configuration >>>>>
6215 09:58:44.795351 [RX_INPUT] configuration <<<<<
6216 09:58:44.799042 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6217 09:58:44.805440 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6218 09:58:44.812479 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6219 09:58:44.818781 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6220 09:58:44.822347 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6221 09:58:44.828582 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6222 09:58:44.832150 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6223 09:58:44.839026 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6224 09:58:44.841979 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6225 09:58:44.845548 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6226 09:58:44.848533 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6227 09:58:44.855392 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6228 09:58:44.858917 ===================================
6229 09:58:44.859000 LPDDR4 DRAM CONFIGURATION
6230 09:58:44.862489 ===================================
6231 09:58:44.865311 EX_ROW_EN[0] = 0x0
6232 09:58:44.865390 EX_ROW_EN[1] = 0x0
6233 09:58:44.868786 LP4Y_EN = 0x0
6234 09:58:44.872461 WORK_FSP = 0x0
6235 09:58:44.872539 WL = 0x2
6236 09:58:44.875249 RL = 0x2
6237 09:58:44.875356 BL = 0x2
6238 09:58:44.878759 RPST = 0x0
6239 09:58:44.878873 RD_PRE = 0x0
6240 09:58:44.882120 WR_PRE = 0x1
6241 09:58:44.882215 WR_PST = 0x0
6242 09:58:44.885874 DBI_WR = 0x0
6243 09:58:44.885984 DBI_RD = 0x0
6244 09:58:44.889284 OTF = 0x1
6245 09:58:44.892196 ===================================
6246 09:58:44.896065 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6247 09:58:44.898838 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6248 09:58:44.902576 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6249 09:58:44.905827 ===================================
6250 09:58:44.909253 LPDDR4 DRAM CONFIGURATION
6251 09:58:44.912234 ===================================
6252 09:58:44.915913 EX_ROW_EN[0] = 0x10
6253 09:58:44.915995 EX_ROW_EN[1] = 0x0
6254 09:58:44.918792 LP4Y_EN = 0x0
6255 09:58:44.918918 WORK_FSP = 0x0
6256 09:58:44.922195 WL = 0x2
6257 09:58:44.922280 RL = 0x2
6258 09:58:44.925716 BL = 0x2
6259 09:58:44.925800 RPST = 0x0
6260 09:58:44.929378 RD_PRE = 0x0
6261 09:58:44.929462 WR_PRE = 0x1
6262 09:58:44.932744 WR_PST = 0x0
6263 09:58:44.932829 DBI_WR = 0x0
6264 09:58:44.935929 DBI_RD = 0x0
6265 09:58:44.936014 OTF = 0x1
6266 09:58:44.939059 ===================================
6267 09:58:44.945876 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6268 09:58:44.950749 nWR fixed to 30
6269 09:58:44.953942 [ModeRegInit_LP4] CH0 RK0
6270 09:58:44.954026 [ModeRegInit_LP4] CH0 RK1
6271 09:58:44.957454 [ModeRegInit_LP4] CH1 RK0
6272 09:58:44.960638 [ModeRegInit_LP4] CH1 RK1
6273 09:58:44.960725 match AC timing 19
6274 09:58:44.967833 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6275 09:58:44.970880 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6276 09:58:44.974391 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6277 09:58:44.980923 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6278 09:58:44.984730 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6279 09:58:44.984813 ==
6280 09:58:44.987653 Dram Type= 6, Freq= 0, CH_0, rank 0
6281 09:58:44.990769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6282 09:58:44.990879 ==
6283 09:58:44.997646 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6284 09:58:45.004390 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6285 09:58:45.007476 [CA 0] Center 36 (8~64) winsize 57
6286 09:58:45.007555 [CA 1] Center 36 (8~64) winsize 57
6287 09:58:45.011005 [CA 2] Center 36 (8~64) winsize 57
6288 09:58:45.014119 [CA 3] Center 36 (8~64) winsize 57
6289 09:58:45.017556 [CA 4] Center 36 (8~64) winsize 57
6290 09:58:45.021355 [CA 5] Center 36 (8~64) winsize 57
6291 09:58:45.021436
6292 09:58:45.024099 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6293 09:58:45.024202
6294 09:58:45.027541 [CATrainingPosCal] consider 1 rank data
6295 09:58:45.031210 u2DelayCellTimex100 = 270/100 ps
6296 09:58:45.034206 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 09:58:45.041447 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 09:58:45.044271 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 09:58:45.047483 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 09:58:45.050796 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 09:58:45.054295 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 09:58:45.054389
6303 09:58:45.057379 CA PerBit enable=1, Macro0, CA PI delay=36
6304 09:58:45.057490
6305 09:58:45.060900 [CBTSetCACLKResult] CA Dly = 36
6306 09:58:45.061010 CS Dly: 1 (0~32)
6307 09:58:45.064589 ==
6308 09:58:45.064666 Dram Type= 6, Freq= 0, CH_0, rank 1
6309 09:58:45.071221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6310 09:58:45.071326 ==
6311 09:58:45.074122 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6312 09:58:45.080849 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6313 09:58:45.084439 [CA 0] Center 36 (8~64) winsize 57
6314 09:58:45.087816 [CA 1] Center 36 (8~64) winsize 57
6315 09:58:45.091473 [CA 2] Center 36 (8~64) winsize 57
6316 09:58:45.094465 [CA 3] Center 36 (8~64) winsize 57
6317 09:58:45.097592 [CA 4] Center 36 (8~64) winsize 57
6318 09:58:45.100982 [CA 5] Center 36 (8~64) winsize 57
6319 09:58:45.101053
6320 09:58:45.104195 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6321 09:58:45.104296
6322 09:58:45.107627 [CATrainingPosCal] consider 2 rank data
6323 09:58:45.111061 u2DelayCellTimex100 = 270/100 ps
6324 09:58:45.114791 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 09:58:45.118354 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6326 09:58:45.121421 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6327 09:58:45.124510 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6328 09:58:45.127688 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6329 09:58:45.131041 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6330 09:58:45.131120
6331 09:58:45.138028 CA PerBit enable=1, Macro0, CA PI delay=36
6332 09:58:45.138108
6333 09:58:45.141273 [CBTSetCACLKResult] CA Dly = 36
6334 09:58:45.141344 CS Dly: 1 (0~32)
6335 09:58:45.141409
6336 09:58:45.144694 ----->DramcWriteLeveling(PI) begin...
6337 09:58:45.144762 ==
6338 09:58:45.147693 Dram Type= 6, Freq= 0, CH_0, rank 0
6339 09:58:45.151136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6340 09:58:45.151214 ==
6341 09:58:45.154970 Write leveling (Byte 0): 40 => 8
6342 09:58:45.158045 Write leveling (Byte 1): 32 => 0
6343 09:58:45.161423 DramcWriteLeveling(PI) end<-----
6344 09:58:45.161516
6345 09:58:45.161585 ==
6346 09:58:45.164621 Dram Type= 6, Freq= 0, CH_0, rank 0
6347 09:58:45.167991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 09:58:45.171563 ==
6349 09:58:45.171652 [Gating] SW mode calibration
6350 09:58:45.178225 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6351 09:58:45.184650 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6352 09:58:45.187980 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6353 09:58:45.194622 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6354 09:58:45.197677 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6355 09:58:45.201273 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6356 09:58:45.207835 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6357 09:58:45.210937 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6358 09:58:45.214255 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6359 09:58:45.221139 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6360 09:58:45.224539 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6361 09:58:45.227545 Total UI for P1: 0, mck2ui 16
6362 09:58:45.231171 best dqsien dly found for B0: ( 0, 14, 24)
6363 09:58:45.234201 Total UI for P1: 0, mck2ui 16
6364 09:58:45.237940 best dqsien dly found for B1: ( 0, 14, 24)
6365 09:58:45.241279 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6366 09:58:45.244191 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6367 09:58:45.244294
6368 09:58:45.247864 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6369 09:58:45.250924 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6370 09:58:45.254700 [Gating] SW calibration Done
6371 09:58:45.254803 ==
6372 09:58:45.258280 Dram Type= 6, Freq= 0, CH_0, rank 0
6373 09:58:45.261199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6374 09:58:45.261308 ==
6375 09:58:45.264514 RX Vref Scan: 0
6376 09:58:45.264630
6377 09:58:45.267745 RX Vref 0 -> 0, step: 1
6378 09:58:45.267856
6379 09:58:45.267922 RX Delay -410 -> 252, step: 16
6380 09:58:45.274513 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6381 09:58:45.277845 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6382 09:58:45.281453 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6383 09:58:45.284624 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6384 09:58:45.291466 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6385 09:58:45.295007 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6386 09:58:45.297989 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6387 09:58:45.301509 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6388 09:58:45.308184 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6389 09:58:45.311260 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6390 09:58:45.314735 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6391 09:58:45.318360 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6392 09:58:45.324906 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6393 09:58:45.328307 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6394 09:58:45.331756 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6395 09:58:45.335021 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6396 09:58:45.338200 ==
6397 09:58:45.338277 Dram Type= 6, Freq= 0, CH_0, rank 0
6398 09:58:45.344792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6399 09:58:45.344873 ==
6400 09:58:45.344939 DQS Delay:
6401 09:58:45.348178 DQS0 = 35, DQS1 = 51
6402 09:58:45.348285 DQM Delay:
6403 09:58:45.351692 DQM0 = 7, DQM1 = 11
6404 09:58:45.351768 DQ Delay:
6405 09:58:45.354720 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6406 09:58:45.358393 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6407 09:58:45.358501 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6408 09:58:45.361370 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6409 09:58:45.365020
6410 09:58:45.365095
6411 09:58:45.365156 ==
6412 09:58:45.368636 Dram Type= 6, Freq= 0, CH_0, rank 0
6413 09:58:45.371514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6414 09:58:45.371592 ==
6415 09:58:45.371654
6416 09:58:45.371711
6417 09:58:45.375156 TX Vref Scan disable
6418 09:58:45.375247 == TX Byte 0 ==
6419 09:58:45.378344 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6420 09:58:45.384992 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6421 09:58:45.385072 == TX Byte 1 ==
6422 09:58:45.388365 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6423 09:58:45.394887 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6424 09:58:45.394993 ==
6425 09:58:45.398667 Dram Type= 6, Freq= 0, CH_0, rank 0
6426 09:58:45.401996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6427 09:58:45.402082 ==
6428 09:58:45.402145
6429 09:58:45.402208
6430 09:58:45.405082 TX Vref Scan disable
6431 09:58:45.405195 == TX Byte 0 ==
6432 09:58:45.409027 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6433 09:58:45.415072 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6434 09:58:45.415169 == TX Byte 1 ==
6435 09:58:45.418138 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6436 09:58:45.425299 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6437 09:58:45.425383
6438 09:58:45.425448 [DATLAT]
6439 09:58:45.425508 Freq=400, CH0 RK0
6440 09:58:45.428651
6441 09:58:45.428729 DATLAT Default: 0xf
6442 09:58:45.431643 0, 0xFFFF, sum = 0
6443 09:58:45.431716 1, 0xFFFF, sum = 0
6444 09:58:45.435444 2, 0xFFFF, sum = 0
6445 09:58:45.435519 3, 0xFFFF, sum = 0
6446 09:58:45.438568 4, 0xFFFF, sum = 0
6447 09:58:45.438674 5, 0xFFFF, sum = 0
6448 09:58:45.442001 6, 0xFFFF, sum = 0
6449 09:58:45.442125 7, 0xFFFF, sum = 0
6450 09:58:45.445160 8, 0xFFFF, sum = 0
6451 09:58:45.445239 9, 0xFFFF, sum = 0
6452 09:58:45.449085 10, 0xFFFF, sum = 0
6453 09:58:45.449168 11, 0xFFFF, sum = 0
6454 09:58:45.452112 12, 0xFFFF, sum = 0
6455 09:58:45.452194 13, 0x0, sum = 1
6456 09:58:45.455303 14, 0x0, sum = 2
6457 09:58:45.455383 15, 0x0, sum = 3
6458 09:58:45.459126 16, 0x0, sum = 4
6459 09:58:45.459209 best_step = 14
6460 09:58:45.459271
6461 09:58:45.459340 ==
6462 09:58:45.462015 Dram Type= 6, Freq= 0, CH_0, rank 0
6463 09:58:45.465683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 09:58:45.465799 ==
6465 09:58:45.468703 RX Vref Scan: 1
6466 09:58:45.468783
6467 09:58:45.472284 RX Vref 0 -> 0, step: 1
6468 09:58:45.472381
6469 09:58:45.472451 RX Delay -343 -> 252, step: 8
6470 09:58:45.475639
6471 09:58:45.475728 Set Vref, RX VrefLevel [Byte0]: 53
6472 09:58:45.479144 [Byte1]: 49
6473 09:58:45.484343
6474 09:58:45.484423 Final RX Vref Byte 0 = 53 to rank0
6475 09:58:45.487736 Final RX Vref Byte 1 = 49 to rank0
6476 09:58:45.491190 Final RX Vref Byte 0 = 53 to rank1
6477 09:58:45.494129 Final RX Vref Byte 1 = 49 to rank1==
6478 09:58:45.497800 Dram Type= 6, Freq= 0, CH_0, rank 0
6479 09:58:45.504350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 09:58:45.504459 ==
6481 09:58:45.504558 DQS Delay:
6482 09:58:45.507930 DQS0 = 40, DQS1 = 56
6483 09:58:45.508031 DQM Delay:
6484 09:58:45.508126 DQM0 = 8, DQM1 = 12
6485 09:58:45.510855 DQ Delay:
6486 09:58:45.510961 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =4
6487 09:58:45.514710 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6488 09:58:45.517679 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6489 09:58:45.520739 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =24
6490 09:58:45.520819
6491 09:58:45.520883
6492 09:58:45.531083 [DQSOSCAuto] RK0, (LSB)MR18= 0x8e5b, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 392 ps
6493 09:58:45.534408 CH0 RK0: MR19=C0C, MR18=8E5B
6494 09:58:45.541163 CH0_RK0: MR19=0xC0C, MR18=0x8E5B, DQSOSC=392, MR23=63, INC=384, DEC=256
6495 09:58:45.541242 ==
6496 09:58:45.544543 Dram Type= 6, Freq= 0, CH_0, rank 1
6497 09:58:45.547508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 09:58:45.547586 ==
6499 09:58:45.551088 [Gating] SW mode calibration
6500 09:58:45.557505 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6501 09:58:45.560965 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6502 09:58:45.567657 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6503 09:58:45.571337 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6504 09:58:45.574244 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6505 09:58:45.580799 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6506 09:58:45.584205 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6507 09:58:45.587612 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6508 09:58:45.594338 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6509 09:58:45.597939 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6510 09:58:45.601150 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6511 09:58:45.604530 Total UI for P1: 0, mck2ui 16
6512 09:58:45.608061 best dqsien dly found for B0: ( 0, 14, 24)
6513 09:58:45.610933 Total UI for P1: 0, mck2ui 16
6514 09:58:45.614500 best dqsien dly found for B1: ( 0, 14, 24)
6515 09:58:45.617833 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6516 09:58:45.621243 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6517 09:58:45.621324
6518 09:58:45.624317 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6519 09:58:45.631052 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6520 09:58:45.631138 [Gating] SW calibration Done
6521 09:58:45.631220 ==
6522 09:58:45.634807 Dram Type= 6, Freq= 0, CH_0, rank 1
6523 09:58:45.641240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6524 09:58:45.641321 ==
6525 09:58:45.641386 RX Vref Scan: 0
6526 09:58:45.641447
6527 09:58:45.644513 RX Vref 0 -> 0, step: 1
6528 09:58:45.644591
6529 09:58:45.648335 RX Delay -410 -> 252, step: 16
6530 09:58:45.651465 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6531 09:58:45.654640 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6532 09:58:45.658121 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6533 09:58:45.664702 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6534 09:58:45.668474 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6535 09:58:45.671471 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6536 09:58:45.674961 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6537 09:58:45.681271 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6538 09:58:45.684729 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6539 09:58:45.687969 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6540 09:58:45.691367 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6541 09:58:45.698116 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6542 09:58:45.701381 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6543 09:58:45.704744 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6544 09:58:45.711293 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6545 09:58:45.714659 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6546 09:58:45.714775 ==
6547 09:58:45.718257 Dram Type= 6, Freq= 0, CH_0, rank 1
6548 09:58:45.721276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6549 09:58:45.721362 ==
6550 09:58:45.724872 DQS Delay:
6551 09:58:45.724949 DQS0 = 43, DQS1 = 51
6552 09:58:45.725011 DQM Delay:
6553 09:58:45.727850 DQM0 = 11, DQM1 = 11
6554 09:58:45.727929 DQ Delay:
6555 09:58:45.731172 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6556 09:58:45.734671 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6557 09:58:45.738259 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6558 09:58:45.741269 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6559 09:58:45.741376
6560 09:58:45.741471
6561 09:58:45.741538 ==
6562 09:58:45.744830 Dram Type= 6, Freq= 0, CH_0, rank 1
6563 09:58:45.747778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6564 09:58:45.747890 ==
6565 09:58:45.747990
6566 09:58:45.751241
6567 09:58:45.751319 TX Vref Scan disable
6568 09:58:45.755038 == TX Byte 0 ==
6569 09:58:45.758036 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6570 09:58:45.761219 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6571 09:58:45.764568 == TX Byte 1 ==
6572 09:58:45.768227 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6573 09:58:45.771215 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6574 09:58:45.771291 ==
6575 09:58:45.775040 Dram Type= 6, Freq= 0, CH_0, rank 1
6576 09:58:45.777860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6577 09:58:45.777936 ==
6578 09:58:45.778002
6579 09:58:45.780961
6580 09:58:45.781068 TX Vref Scan disable
6581 09:58:45.784315 == TX Byte 0 ==
6582 09:58:45.787835 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6583 09:58:45.791226 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6584 09:58:45.794553 == TX Byte 1 ==
6585 09:58:45.797975 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6586 09:58:45.801055 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6587 09:58:45.801140
6588 09:58:45.801210 [DATLAT]
6589 09:58:45.804224 Freq=400, CH0 RK1
6590 09:58:45.804307
6591 09:58:45.804391 DATLAT Default: 0xe
6592 09:58:45.807944 0, 0xFFFF, sum = 0
6593 09:58:45.808025 1, 0xFFFF, sum = 0
6594 09:58:45.811039 2, 0xFFFF, sum = 0
6595 09:58:45.814772 3, 0xFFFF, sum = 0
6596 09:58:45.814956 4, 0xFFFF, sum = 0
6597 09:58:45.817989 5, 0xFFFF, sum = 0
6598 09:58:45.818073 6, 0xFFFF, sum = 0
6599 09:58:45.821400 7, 0xFFFF, sum = 0
6600 09:58:45.821488 8, 0xFFFF, sum = 0
6601 09:58:45.824648 9, 0xFFFF, sum = 0
6602 09:58:45.824727 10, 0xFFFF, sum = 0
6603 09:58:45.828078 11, 0xFFFF, sum = 0
6604 09:58:45.828191 12, 0xFFFF, sum = 0
6605 09:58:45.831613 13, 0x0, sum = 1
6606 09:58:45.831700 14, 0x0, sum = 2
6607 09:58:45.834672 15, 0x0, sum = 3
6608 09:58:45.834793 16, 0x0, sum = 4
6609 09:58:45.837741 best_step = 14
6610 09:58:45.837849
6611 09:58:45.837910 ==
6612 09:58:45.841418 Dram Type= 6, Freq= 0, CH_0, rank 1
6613 09:58:45.844443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6614 09:58:45.844523 ==
6615 09:58:45.844619 RX Vref Scan: 0
6616 09:58:45.844681
6617 09:58:45.847964 RX Vref 0 -> 0, step: 1
6618 09:58:45.848041
6619 09:58:45.850877 RX Delay -343 -> 252, step: 8
6620 09:58:45.858633 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6621 09:58:45.861741 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6622 09:58:45.865236 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6623 09:58:45.868319 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6624 09:58:45.875764 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6625 09:58:45.878664 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6626 09:58:45.881801 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6627 09:58:45.885448 iDelay=217, Bit 7, Center -32 (-271 ~ 208) 480
6628 09:58:45.891825 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6629 09:58:45.895547 iDelay=217, Bit 9, Center -56 (-295 ~ 184) 480
6630 09:58:45.898480 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6631 09:58:45.901848 iDelay=217, Bit 11, Center -52 (-287 ~ 184) 472
6632 09:58:45.908534 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6633 09:58:45.911835 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6634 09:58:45.915504 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6635 09:58:45.918652 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6636 09:58:45.921896 ==
6637 09:58:45.921976 Dram Type= 6, Freq= 0, CH_0, rank 1
6638 09:58:45.929009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6639 09:58:45.929120 ==
6640 09:58:45.929214 DQS Delay:
6641 09:58:45.932385 DQS0 = 48, DQS1 = 60
6642 09:58:45.932554 DQM Delay:
6643 09:58:45.935631 DQM0 = 12, DQM1 = 14
6644 09:58:45.935713 DQ Delay:
6645 09:58:45.938505 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6646 09:58:45.942029 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6647 09:58:45.945259 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6648 09:58:45.948866 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6649 09:58:45.948950
6650 09:58:45.949014
6651 09:58:45.955351 [DQSOSCAuto] RK1, (LSB)MR18= 0x9769, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 390 ps
6652 09:58:45.958900 CH0 RK1: MR19=C0C, MR18=9769
6653 09:58:45.965510 CH0_RK1: MR19=0xC0C, MR18=0x9769, DQSOSC=390, MR23=63, INC=388, DEC=258
6654 09:58:45.968627 [RxdqsGatingPostProcess] freq 400
6655 09:58:45.972092 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6656 09:58:45.975927 best DQS0 dly(2T, 0.5T) = (0, 10)
6657 09:58:45.978777 best DQS1 dly(2T, 0.5T) = (0, 10)
6658 09:58:45.982397 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6659 09:58:45.985298 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6660 09:58:45.988972 best DQS0 dly(2T, 0.5T) = (0, 10)
6661 09:58:45.991929 best DQS1 dly(2T, 0.5T) = (0, 10)
6662 09:58:45.995495 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6663 09:58:45.998575 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6664 09:58:46.002027 Pre-setting of DQS Precalculation
6665 09:58:46.005704 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6666 09:58:46.005795 ==
6667 09:58:46.009109 Dram Type= 6, Freq= 0, CH_1, rank 0
6668 09:58:46.015540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6669 09:58:46.015636 ==
6670 09:58:46.018985 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6671 09:58:46.025556 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6672 09:58:46.029006 [CA 0] Center 36 (8~64) winsize 57
6673 09:58:46.032289 [CA 1] Center 36 (8~64) winsize 57
6674 09:58:46.035511 [CA 2] Center 36 (8~64) winsize 57
6675 09:58:46.038977 [CA 3] Center 36 (8~64) winsize 57
6676 09:58:46.042332 [CA 4] Center 36 (8~64) winsize 57
6677 09:58:46.045660 [CA 5] Center 36 (8~64) winsize 57
6678 09:58:46.045741
6679 09:58:46.049057 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6680 09:58:46.049162
6681 09:58:46.052054 [CATrainingPosCal] consider 1 rank data
6682 09:58:46.055663 u2DelayCellTimex100 = 270/100 ps
6683 09:58:46.058752 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 09:58:46.062320 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 09:58:46.065928 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 09:58:46.068954 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 09:58:46.072656 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 09:58:46.075552 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 09:58:46.075628
6690 09:58:46.079108 CA PerBit enable=1, Macro0, CA PI delay=36
6691 09:58:46.082040
6692 09:58:46.082114 [CBTSetCACLKResult] CA Dly = 36
6693 09:58:46.085483 CS Dly: 1 (0~32)
6694 09:58:46.085554 ==
6695 09:58:46.089370 Dram Type= 6, Freq= 0, CH_1, rank 1
6696 09:58:46.092468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6697 09:58:46.092571 ==
6698 09:58:46.098963 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6699 09:58:46.105844 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6700 09:58:46.109309 [CA 0] Center 36 (8~64) winsize 57
6701 09:58:46.112320 [CA 1] Center 36 (8~64) winsize 57
6702 09:58:46.112426 [CA 2] Center 36 (8~64) winsize 57
6703 09:58:46.115934 [CA 3] Center 36 (8~64) winsize 57
6704 09:58:46.118698 [CA 4] Center 36 (8~64) winsize 57
6705 09:58:46.122361 [CA 5] Center 36 (8~64) winsize 57
6706 09:58:46.122438
6707 09:58:46.125956 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6708 09:58:46.126059
6709 09:58:46.132391 [CATrainingPosCal] consider 2 rank data
6710 09:58:46.132470 u2DelayCellTimex100 = 270/100 ps
6711 09:58:46.138657 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 09:58:46.142382 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6713 09:58:46.145807 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6714 09:58:46.148591 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6715 09:58:46.152101 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6716 09:58:46.155658 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6717 09:58:46.155735
6718 09:58:46.158925 CA PerBit enable=1, Macro0, CA PI delay=36
6719 09:58:46.159009
6720 09:58:46.162215 [CBTSetCACLKResult] CA Dly = 36
6721 09:58:46.162314 CS Dly: 1 (0~32)
6722 09:58:46.165551
6723 09:58:46.169270 ----->DramcWriteLeveling(PI) begin...
6724 09:58:46.169352 ==
6725 09:58:46.172298 Dram Type= 6, Freq= 0, CH_1, rank 0
6726 09:58:46.176050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6727 09:58:46.176128 ==
6728 09:58:46.179064 Write leveling (Byte 0): 40 => 8
6729 09:58:46.182389 Write leveling (Byte 1): 40 => 8
6730 09:58:46.185529 DramcWriteLeveling(PI) end<-----
6731 09:58:46.185607
6732 09:58:46.185685 ==
6733 09:58:46.189047 Dram Type= 6, Freq= 0, CH_1, rank 0
6734 09:58:46.192228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 09:58:46.192310 ==
6736 09:58:46.196100 [Gating] SW mode calibration
6737 09:58:46.202296 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6738 09:58:46.205841 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6739 09:58:46.212366 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6740 09:58:46.215940 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6741 09:58:46.219414 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6742 09:58:46.225883 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6743 09:58:46.229329 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6744 09:58:46.232648 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6745 09:58:46.239206 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6746 09:58:46.242468 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6747 09:58:46.245663 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6748 09:58:46.249227 Total UI for P1: 0, mck2ui 16
6749 09:58:46.252397 best dqsien dly found for B0: ( 0, 14, 24)
6750 09:58:46.255665 Total UI for P1: 0, mck2ui 16
6751 09:58:46.259344 best dqsien dly found for B1: ( 0, 14, 24)
6752 09:58:46.262635 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6753 09:58:46.266046 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6754 09:58:46.266132
6755 09:58:46.269613 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6756 09:58:46.275996 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6757 09:58:46.276105 [Gating] SW calibration Done
6758 09:58:46.279120 ==
6759 09:58:46.279197 Dram Type= 6, Freq= 0, CH_1, rank 0
6760 09:58:46.286258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6761 09:58:46.286339 ==
6762 09:58:46.286405 RX Vref Scan: 0
6763 09:58:46.286466
6764 09:58:46.289349 RX Vref 0 -> 0, step: 1
6765 09:58:46.289420
6766 09:58:46.292923 RX Delay -410 -> 252, step: 16
6767 09:58:46.296056 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6768 09:58:46.299577 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6769 09:58:46.305844 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6770 09:58:46.309556 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6771 09:58:46.313139 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6772 09:58:46.316200 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6773 09:58:46.319764 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6774 09:58:46.326325 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6775 09:58:46.330074 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6776 09:58:46.332906 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6777 09:58:46.336277 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6778 09:58:46.342928 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6779 09:58:46.346159 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6780 09:58:46.349700 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6781 09:58:46.356358 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6782 09:58:46.359849 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6783 09:58:46.359931 ==
6784 09:58:46.363092 Dram Type= 6, Freq= 0, CH_1, rank 0
6785 09:58:46.366336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6786 09:58:46.366449 ==
6787 09:58:46.366545 DQS Delay:
6788 09:58:46.369530 DQS0 = 51, DQS1 = 59
6789 09:58:46.369635 DQM Delay:
6790 09:58:46.372919 DQM0 = 19, DQM1 = 17
6791 09:58:46.373023 DQ Delay:
6792 09:58:46.376438 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6793 09:58:46.379731 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6794 09:58:46.383065 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6795 09:58:46.386703 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6796 09:58:46.386786
6797 09:58:46.386852
6798 09:58:46.386924 ==
6799 09:58:46.389734 Dram Type= 6, Freq= 0, CH_1, rank 0
6800 09:58:46.393316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6801 09:58:46.396857 ==
6802 09:58:46.396931
6803 09:58:46.396993
6804 09:58:46.397052 TX Vref Scan disable
6805 09:58:46.399841 == TX Byte 0 ==
6806 09:58:46.403079 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6807 09:58:46.406448 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6808 09:58:46.410226 == TX Byte 1 ==
6809 09:58:46.413356 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6810 09:58:46.416559 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6811 09:58:46.416669 ==
6812 09:58:46.420099 Dram Type= 6, Freq= 0, CH_1, rank 0
6813 09:58:46.423166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6814 09:58:46.426753 ==
6815 09:58:46.426854
6816 09:58:46.426941
6817 09:58:46.427005 TX Vref Scan disable
6818 09:58:46.429781 == TX Byte 0 ==
6819 09:58:46.433567 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6820 09:58:46.437070 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6821 09:58:46.439837 == TX Byte 1 ==
6822 09:58:46.443340 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6823 09:58:46.446856 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6824 09:58:46.446958
6825 09:58:46.447027 [DATLAT]
6826 09:58:46.450040 Freq=400, CH1 RK0
6827 09:58:46.450146
6828 09:58:46.450249 DATLAT Default: 0xf
6829 09:58:46.453710 0, 0xFFFF, sum = 0
6830 09:58:46.456499 1, 0xFFFF, sum = 0
6831 09:58:46.456613 2, 0xFFFF, sum = 0
6832 09:58:46.460435 3, 0xFFFF, sum = 0
6833 09:58:46.460540 4, 0xFFFF, sum = 0
6834 09:58:46.463142 5, 0xFFFF, sum = 0
6835 09:58:46.463216 6, 0xFFFF, sum = 0
6836 09:58:46.466628 7, 0xFFFF, sum = 0
6837 09:58:46.466744 8, 0xFFFF, sum = 0
6838 09:58:46.470190 9, 0xFFFF, sum = 0
6839 09:58:46.470290 10, 0xFFFF, sum = 0
6840 09:58:46.473347 11, 0xFFFF, sum = 0
6841 09:58:46.473465 12, 0xFFFF, sum = 0
6842 09:58:46.476920 13, 0x0, sum = 1
6843 09:58:46.477023 14, 0x0, sum = 2
6844 09:58:46.479707 15, 0x0, sum = 3
6845 09:58:46.479827 16, 0x0, sum = 4
6846 09:58:46.483119 best_step = 14
6847 09:58:46.483199
6848 09:58:46.483264 ==
6849 09:58:46.486634 Dram Type= 6, Freq= 0, CH_1, rank 0
6850 09:58:46.489890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 09:58:46.489965 ==
6852 09:58:46.490027 RX Vref Scan: 1
6853 09:58:46.493205
6854 09:58:46.493307 RX Vref 0 -> 0, step: 1
6855 09:58:46.493397
6856 09:58:46.497455 RX Delay -359 -> 252, step: 8
6857 09:58:46.497533
6858 09:58:46.499849 Set Vref, RX VrefLevel [Byte0]: 57
6859 09:58:46.503462 [Byte1]: 45
6860 09:58:46.507901
6861 09:58:46.508004 Final RX Vref Byte 0 = 57 to rank0
6862 09:58:46.510814 Final RX Vref Byte 1 = 45 to rank0
6863 09:58:46.513995 Final RX Vref Byte 0 = 57 to rank1
6864 09:58:46.517434 Final RX Vref Byte 1 = 45 to rank1==
6865 09:58:46.521049 Dram Type= 6, Freq= 0, CH_1, rank 0
6866 09:58:46.527728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 09:58:46.527813 ==
6868 09:58:46.527879 DQS Delay:
6869 09:58:46.527940 DQS0 = 48, DQS1 = 60
6870 09:58:46.530737 DQM Delay:
6871 09:58:46.530847 DQM0 = 11, DQM1 = 12
6872 09:58:46.534423 DQ Delay:
6873 09:58:46.537455 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6874 09:58:46.537539 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6875 09:58:46.541224 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6876 09:58:46.544024 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6877 09:58:46.544107
6878 09:58:46.544172
6879 09:58:46.554385 [DQSOSCAuto] RK0, (LSB)MR18= 0x8831, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6880 09:58:46.558122 CH1 RK0: MR19=C0C, MR18=8831
6881 09:58:46.561015 CH1_RK0: MR19=0xC0C, MR18=0x8831, DQSOSC=392, MR23=63, INC=384, DEC=256
6882 09:58:46.563971 ==
6883 09:58:46.567752 Dram Type= 6, Freq= 0, CH_1, rank 1
6884 09:58:46.571155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 09:58:46.571257 ==
6886 09:58:46.574203 [Gating] SW mode calibration
6887 09:58:46.580856 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6888 09:58:46.584309 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6889 09:58:46.590794 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6890 09:58:46.594319 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6891 09:58:46.597901 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6892 09:58:46.604124 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6893 09:58:46.607820 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6894 09:58:46.610885 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6895 09:58:46.617336 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6896 09:58:46.620919 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6897 09:58:46.624578 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6898 09:58:46.627578 Total UI for P1: 0, mck2ui 16
6899 09:58:46.631194 best dqsien dly found for B0: ( 0, 14, 24)
6900 09:58:46.634261 Total UI for P1: 0, mck2ui 16
6901 09:58:46.637620 best dqsien dly found for B1: ( 0, 14, 24)
6902 09:58:46.640661 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6903 09:58:46.644368 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6904 09:58:46.644447
6905 09:58:46.647336 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6906 09:58:46.654647 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6907 09:58:46.654728 [Gating] SW calibration Done
6908 09:58:46.657369 ==
6909 09:58:46.657446 Dram Type= 6, Freq= 0, CH_1, rank 1
6910 09:58:46.664244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6911 09:58:46.664334 ==
6912 09:58:46.664419 RX Vref Scan: 0
6913 09:58:46.664498
6914 09:58:46.668040 RX Vref 0 -> 0, step: 1
6915 09:58:46.668118
6916 09:58:46.671134 RX Delay -410 -> 252, step: 16
6917 09:58:46.674005 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6918 09:58:46.677681 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6919 09:58:46.684286 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6920 09:58:46.687816 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6921 09:58:46.690820 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6922 09:58:46.694193 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6923 09:58:46.701091 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6924 09:58:46.704067 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6925 09:58:46.707655 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6926 09:58:46.711049 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6927 09:58:46.718143 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6928 09:58:46.721205 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6929 09:58:46.724413 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6930 09:58:46.727956 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6931 09:58:46.734621 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6932 09:58:46.737638 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6933 09:58:46.737723 ==
6934 09:58:46.741004 Dram Type= 6, Freq= 0, CH_1, rank 1
6935 09:58:46.744271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6936 09:58:46.744355 ==
6937 09:58:46.747718 DQS Delay:
6938 09:58:46.747802 DQS0 = 43, DQS1 = 51
6939 09:58:46.747868 DQM Delay:
6940 09:58:46.751403 DQM0 = 9, DQM1 = 9
6941 09:58:46.751487 DQ Delay:
6942 09:58:46.754273 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6943 09:58:46.757881 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6944 09:58:46.761568 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6945 09:58:46.764463 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6946 09:58:46.764548
6947 09:58:46.764614
6948 09:58:46.764675 ==
6949 09:58:46.767936 Dram Type= 6, Freq= 0, CH_1, rank 1
6950 09:58:46.771302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6951 09:58:46.771387 ==
6952 09:58:46.771453
6953 09:58:46.771514
6954 09:58:46.774320 TX Vref Scan disable
6955 09:58:46.777790 == TX Byte 0 ==
6956 09:58:46.781405 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6957 09:58:46.784515 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6958 09:58:46.784600 == TX Byte 1 ==
6959 09:58:46.790925 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6960 09:58:46.794537 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6961 09:58:46.794617 ==
6962 09:58:46.797546 Dram Type= 6, Freq= 0, CH_1, rank 1
6963 09:58:46.801047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6964 09:58:46.801124 ==
6965 09:58:46.801187
6966 09:58:46.801246
6967 09:58:46.804449 TX Vref Scan disable
6968 09:58:46.807868 == TX Byte 0 ==
6969 09:58:46.811506 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6970 09:58:46.814710 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6971 09:58:46.814831 == TX Byte 1 ==
6972 09:58:46.820963 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6973 09:58:46.824529 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6974 09:58:46.824640
6975 09:58:46.824741 [DATLAT]
6976 09:58:46.828245 Freq=400, CH1 RK1
6977 09:58:46.828320
6978 09:58:46.828386 DATLAT Default: 0xe
6979 09:58:46.831096 0, 0xFFFF, sum = 0
6980 09:58:46.831204 1, 0xFFFF, sum = 0
6981 09:58:46.834657 2, 0xFFFF, sum = 0
6982 09:58:46.834761 3, 0xFFFF, sum = 0
6983 09:58:46.838249 4, 0xFFFF, sum = 0
6984 09:58:46.838326 5, 0xFFFF, sum = 0
6985 09:58:46.841189 6, 0xFFFF, sum = 0
6986 09:58:46.841272 7, 0xFFFF, sum = 0
6987 09:58:46.844670 8, 0xFFFF, sum = 0
6988 09:58:46.844790 9, 0xFFFF, sum = 0
6989 09:58:46.848176 10, 0xFFFF, sum = 0
6990 09:58:46.848282 11, 0xFFFF, sum = 0
6991 09:58:46.851345 12, 0xFFFF, sum = 0
6992 09:58:46.851422 13, 0x0, sum = 1
6993 09:58:46.855104 14, 0x0, sum = 2
6994 09:58:46.855182 15, 0x0, sum = 3
6995 09:58:46.858022 16, 0x0, sum = 4
6996 09:58:46.858099 best_step = 14
6997 09:58:46.858160
6998 09:58:46.858218 ==
6999 09:58:46.861792 Dram Type= 6, Freq= 0, CH_1, rank 1
7000 09:58:46.868208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7001 09:58:46.868294 ==
7002 09:58:46.868361 RX Vref Scan: 0
7003 09:58:46.868424
7004 09:58:46.871496 RX Vref 0 -> 0, step: 1
7005 09:58:46.871607
7006 09:58:46.875228 RX Delay -343 -> 252, step: 8
7007 09:58:46.881844 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
7008 09:58:46.884704 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
7009 09:58:46.888383 iDelay=217, Bit 2, Center -48 (-287 ~ 192) 480
7010 09:58:46.891433 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
7011 09:58:46.897858 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
7012 09:58:46.901694 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
7013 09:58:46.904737 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
7014 09:58:46.908245 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
7015 09:58:46.914658 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
7016 09:58:46.917918 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
7017 09:58:46.921167 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
7018 09:58:46.924473 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
7019 09:58:46.931417 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
7020 09:58:46.934881 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
7021 09:58:46.938213 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
7022 09:58:46.941210 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
7023 09:58:46.944775 ==
7024 09:58:46.948223 Dram Type= 6, Freq= 0, CH_1, rank 1
7025 09:58:46.951235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7026 09:58:46.951315 ==
7027 09:58:46.951379 DQS Delay:
7028 09:58:46.954925 DQS0 = 48, DQS1 = 60
7029 09:58:46.955003 DQM Delay:
7030 09:58:46.957913 DQM0 = 9, DQM1 = 14
7031 09:58:46.957983 DQ Delay:
7032 09:58:46.961534 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
7033 09:58:46.964618 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =4
7034 09:58:46.968293 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
7035 09:58:46.971724 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =24
7036 09:58:46.971810
7037 09:58:46.971889
7038 09:58:46.978387 [DQSOSCAuto] RK1, (LSB)MR18= 0x748a, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 395 ps
7039 09:58:46.981413 CH1 RK1: MR19=C0C, MR18=748A
7040 09:58:46.988505 CH1_RK1: MR19=0xC0C, MR18=0x748A, DQSOSC=392, MR23=63, INC=384, DEC=256
7041 09:58:46.991556 [RxdqsGatingPostProcess] freq 400
7042 09:58:46.995248 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7043 09:58:46.998019 best DQS0 dly(2T, 0.5T) = (0, 10)
7044 09:58:47.002119 best DQS1 dly(2T, 0.5T) = (0, 10)
7045 09:58:47.004934 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7046 09:58:47.008230 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7047 09:58:47.011676 best DQS0 dly(2T, 0.5T) = (0, 10)
7048 09:58:47.014798 best DQS1 dly(2T, 0.5T) = (0, 10)
7049 09:58:47.018239 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7050 09:58:47.021254 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7051 09:58:47.024655 Pre-setting of DQS Precalculation
7052 09:58:47.028322 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7053 09:58:47.034920 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7054 09:58:47.045115 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7055 09:58:47.045212
7056 09:58:47.045280
7057 09:58:47.048418 [Calibration Summary] 800 Mbps
7058 09:58:47.048503 CH 0, Rank 0
7059 09:58:47.051766 SW Impedance : PASS
7060 09:58:47.051851 DUTY Scan : NO K
7061 09:58:47.054953 ZQ Calibration : PASS
7062 09:58:47.055038 Jitter Meter : NO K
7063 09:58:47.057989 CBT Training : PASS
7064 09:58:47.061755 Write leveling : PASS
7065 09:58:47.061839 RX DQS gating : PASS
7066 09:58:47.065071 RX DQ/DQS(RDDQC) : PASS
7067 09:58:47.068176 TX DQ/DQS : PASS
7068 09:58:47.068262 RX DATLAT : PASS
7069 09:58:47.071714 RX DQ/DQS(Engine): PASS
7070 09:58:47.074678 TX OE : NO K
7071 09:58:47.074762 All Pass.
7072 09:58:47.074828
7073 09:58:47.074901 CH 0, Rank 1
7074 09:58:47.078058 SW Impedance : PASS
7075 09:58:47.081661 DUTY Scan : NO K
7076 09:58:47.081744 ZQ Calibration : PASS
7077 09:58:47.085068 Jitter Meter : NO K
7078 09:58:47.088102 CBT Training : PASS
7079 09:58:47.088186 Write leveling : NO K
7080 09:58:47.091464 RX DQS gating : PASS
7081 09:58:47.094771 RX DQ/DQS(RDDQC) : PASS
7082 09:58:47.094883 TX DQ/DQS : PASS
7083 09:58:47.098456 RX DATLAT : PASS
7084 09:58:47.098559 RX DQ/DQS(Engine): PASS
7085 09:58:47.101405 TX OE : NO K
7086 09:58:47.101483 All Pass.
7087 09:58:47.101550
7088 09:58:47.104793 CH 1, Rank 0
7089 09:58:47.104874 SW Impedance : PASS
7090 09:58:47.108462 DUTY Scan : NO K
7091 09:58:47.111508 ZQ Calibration : PASS
7092 09:58:47.111589 Jitter Meter : NO K
7093 09:58:47.115241 CBT Training : PASS
7094 09:58:47.118454 Write leveling : PASS
7095 09:58:47.118563 RX DQS gating : PASS
7096 09:58:47.121953 RX DQ/DQS(RDDQC) : PASS
7097 09:58:47.124898 TX DQ/DQS : PASS
7098 09:58:47.124978 RX DATLAT : PASS
7099 09:58:47.128627 RX DQ/DQS(Engine): PASS
7100 09:58:47.131909 TX OE : NO K
7101 09:58:47.131989 All Pass.
7102 09:58:47.132064
7103 09:58:47.132161 CH 1, Rank 1
7104 09:58:47.134752 SW Impedance : PASS
7105 09:58:47.138283 DUTY Scan : NO K
7106 09:58:47.138387 ZQ Calibration : PASS
7107 09:58:47.141649 Jitter Meter : NO K
7108 09:58:47.141723 CBT Training : PASS
7109 09:58:47.145177 Write leveling : NO K
7110 09:58:47.148468 RX DQS gating : PASS
7111 09:58:47.148549 RX DQ/DQS(RDDQC) : PASS
7112 09:58:47.151471 TX DQ/DQS : PASS
7113 09:58:47.154895 RX DATLAT : PASS
7114 09:58:47.154973 RX DQ/DQS(Engine): PASS
7115 09:58:47.158199 TX OE : NO K
7116 09:58:47.158299 All Pass.
7117 09:58:47.158392
7118 09:58:47.161395 DramC Write-DBI off
7119 09:58:47.164911 PER_BANK_REFRESH: Hybrid Mode
7120 09:58:47.164990 TX_TRACKING: ON
7121 09:58:47.174610 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7122 09:58:47.178113 [FAST_K] Save calibration result to emmc
7123 09:58:47.181098 dramc_set_vcore_voltage set vcore to 725000
7124 09:58:47.184438 Read voltage for 1600, 0
7125 09:58:47.184517 Vio18 = 0
7126 09:58:47.184581 Vcore = 725000
7127 09:58:47.188153 Vdram = 0
7128 09:58:47.188255 Vddq = 0
7129 09:58:47.188320 Vmddr = 0
7130 09:58:47.194587 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7131 09:58:47.198152 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7132 09:58:47.201578 MEM_TYPE=3, freq_sel=13
7133 09:58:47.204555 sv_algorithm_assistance_LP4_3733
7134 09:58:47.208142 ============ PULL DRAM RESETB DOWN ============
7135 09:58:47.211809 ========== PULL DRAM RESETB DOWN end =========
7136 09:58:47.217975 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7137 09:58:47.221567 ===================================
7138 09:58:47.224563 LPDDR4 DRAM CONFIGURATION
7139 09:58:47.224648 ===================================
7140 09:58:47.228260 EX_ROW_EN[0] = 0x0
7141 09:58:47.231552 EX_ROW_EN[1] = 0x0
7142 09:58:47.231637 LP4Y_EN = 0x0
7143 09:58:47.234556 WORK_FSP = 0x1
7144 09:58:47.234639 WL = 0x5
7145 09:58:47.238018 RL = 0x5
7146 09:58:47.238103 BL = 0x2
7147 09:58:47.241571 RPST = 0x0
7148 09:58:47.241654 RD_PRE = 0x0
7149 09:58:47.244659 WR_PRE = 0x1
7150 09:58:47.244742 WR_PST = 0x1
7151 09:58:47.248196 DBI_WR = 0x0
7152 09:58:47.248280 DBI_RD = 0x0
7153 09:58:47.251642 OTF = 0x1
7154 09:58:47.255030 ===================================
7155 09:58:47.257991 ===================================
7156 09:58:47.258076 ANA top config
7157 09:58:47.261412 ===================================
7158 09:58:47.265002 DLL_ASYNC_EN = 0
7159 09:58:47.268627 ALL_SLAVE_EN = 0
7160 09:58:47.271555 NEW_RANK_MODE = 1
7161 09:58:47.271631 DLL_IDLE_MODE = 1
7162 09:58:47.274761 LP45_APHY_COMB_EN = 1
7163 09:58:47.278543 TX_ODT_DIS = 0
7164 09:58:47.281824 NEW_8X_MODE = 1
7165 09:58:47.285370 ===================================
7166 09:58:47.288256 ===================================
7167 09:58:47.288332 data_rate = 3200
7168 09:58:47.291798 CKR = 1
7169 09:58:47.295370 DQ_P2S_RATIO = 8
7170 09:58:47.298168 ===================================
7171 09:58:47.301795 CA_P2S_RATIO = 8
7172 09:58:47.305289 DQ_CA_OPEN = 0
7173 09:58:47.308225 DQ_SEMI_OPEN = 0
7174 09:58:47.308339 CA_SEMI_OPEN = 0
7175 09:58:47.311839 CA_FULL_RATE = 0
7176 09:58:47.315425 DQ_CKDIV4_EN = 0
7177 09:58:47.318454 CA_CKDIV4_EN = 0
7178 09:58:47.322026 CA_PREDIV_EN = 0
7179 09:58:47.325098 PH8_DLY = 12
7180 09:58:47.325178 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7181 09:58:47.328723 DQ_AAMCK_DIV = 4
7182 09:58:47.331998 CA_AAMCK_DIV = 4
7183 09:58:47.335448 CA_ADMCK_DIV = 4
7184 09:58:47.338783 DQ_TRACK_CA_EN = 0
7185 09:58:47.342109 CA_PICK = 1600
7186 09:58:47.342203 CA_MCKIO = 1600
7187 09:58:47.345200 MCKIO_SEMI = 0
7188 09:58:47.348476 PLL_FREQ = 3068
7189 09:58:47.352223 DQ_UI_PI_RATIO = 32
7190 09:58:47.355125 CA_UI_PI_RATIO = 0
7191 09:58:47.358660 ===================================
7192 09:58:47.361772 ===================================
7193 09:58:47.365231 memory_type:LPDDR4
7194 09:58:47.365304 GP_NUM : 10
7195 09:58:47.368443 SRAM_EN : 1
7196 09:58:47.368524 MD32_EN : 0
7197 09:58:47.372115 ===================================
7198 09:58:47.375294 [ANA_INIT] >>>>>>>>>>>>>>
7199 09:58:47.378788 <<<<<< [CONFIGURE PHASE]: ANA_TX
7200 09:58:47.382212 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7201 09:58:47.386026 ===================================
7202 09:58:47.388638 data_rate = 3200,PCW = 0X7600
7203 09:58:47.392243 ===================================
7204 09:58:47.395592 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7205 09:58:47.398501 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7206 09:58:47.405535 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7207 09:58:47.409065 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7208 09:58:47.412097 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7209 09:58:47.415669 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7210 09:58:47.419087 [ANA_INIT] flow start
7211 09:58:47.422267 [ANA_INIT] PLL >>>>>>>>
7212 09:58:47.422367 [ANA_INIT] PLL <<<<<<<<
7213 09:58:47.425289 [ANA_INIT] MIDPI >>>>>>>>
7214 09:58:47.428868 [ANA_INIT] MIDPI <<<<<<<<
7215 09:58:47.432357 [ANA_INIT] DLL >>>>>>>>
7216 09:58:47.432434 [ANA_INIT] DLL <<<<<<<<
7217 09:58:47.435495 [ANA_INIT] flow end
7218 09:58:47.438936 ============ LP4 DIFF to SE enter ============
7219 09:58:47.442178 ============ LP4 DIFF to SE exit ============
7220 09:58:47.445599 [ANA_INIT] <<<<<<<<<<<<<
7221 09:58:47.449039 [Flow] Enable top DCM control >>>>>
7222 09:58:47.451953 [Flow] Enable top DCM control <<<<<
7223 09:58:47.455642 Enable DLL master slave shuffle
7224 09:58:47.458734 ==============================================================
7225 09:58:47.462276 Gating Mode config
7226 09:58:47.469099 ==============================================================
7227 09:58:47.469180 Config description:
7228 09:58:47.479268 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7229 09:58:47.485924 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7230 09:58:47.492508 SELPH_MODE 0: By rank 1: By Phase
7231 09:58:47.495427 ==============================================================
7232 09:58:47.498904 GAT_TRACK_EN = 1
7233 09:58:47.502465 RX_GATING_MODE = 2
7234 09:58:47.505675 RX_GATING_TRACK_MODE = 2
7235 09:58:47.509162 SELPH_MODE = 1
7236 09:58:47.512230 PICG_EARLY_EN = 1
7237 09:58:47.515770 VALID_LAT_VALUE = 1
7238 09:58:47.518792 ==============================================================
7239 09:58:47.522382 Enter into Gating configuration >>>>
7240 09:58:47.526029 Exit from Gating configuration <<<<
7241 09:58:47.529034 Enter into DVFS_PRE_config >>>>>
7242 09:58:47.542678 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7243 09:58:47.542791 Exit from DVFS_PRE_config <<<<<
7244 09:58:47.546002 Enter into PICG configuration >>>>
7245 09:58:47.549492 Exit from PICG configuration <<<<
7246 09:58:47.552415 [RX_INPUT] configuration >>>>>
7247 09:58:47.556057 [RX_INPUT] configuration <<<<<
7248 09:58:47.562568 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7249 09:58:47.566104 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7250 09:58:47.572787 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7251 09:58:47.579583 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7252 09:58:47.586196 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7253 09:58:47.589390 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7254 09:58:47.596229 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7255 09:58:47.599493 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7256 09:58:47.603002 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7257 09:58:47.606433 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7258 09:58:47.612794 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7259 09:58:47.616010 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7260 09:58:47.619484 ===================================
7261 09:58:47.622811 LPDDR4 DRAM CONFIGURATION
7262 09:58:47.626499 ===================================
7263 09:58:47.626610 EX_ROW_EN[0] = 0x0
7264 09:58:47.629639 EX_ROW_EN[1] = 0x0
7265 09:58:47.629722 LP4Y_EN = 0x0
7266 09:58:47.633114 WORK_FSP = 0x1
7267 09:58:47.633198 WL = 0x5
7268 09:58:47.636080 RL = 0x5
7269 09:58:47.636167 BL = 0x2
7270 09:58:47.639732 RPST = 0x0
7271 09:58:47.639816 RD_PRE = 0x0
7272 09:58:47.642876 WR_PRE = 0x1
7273 09:58:47.642959 WR_PST = 0x1
7274 09:58:47.646421 DBI_WR = 0x0
7275 09:58:47.646504 DBI_RD = 0x0
7276 09:58:47.649307 OTF = 0x1
7277 09:58:47.652906 ===================================
7278 09:58:47.656325 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7279 09:58:47.659862 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7280 09:58:47.666343 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7281 09:58:47.670079 ===================================
7282 09:58:47.670164 LPDDR4 DRAM CONFIGURATION
7283 09:58:47.673051 ===================================
7284 09:58:47.676166 EX_ROW_EN[0] = 0x10
7285 09:58:47.679877 EX_ROW_EN[1] = 0x0
7286 09:58:47.679962 LP4Y_EN = 0x0
7287 09:58:47.682844 WORK_FSP = 0x1
7288 09:58:47.682936 WL = 0x5
7289 09:58:47.686445 RL = 0x5
7290 09:58:47.686528 BL = 0x2
7291 09:58:47.689767 RPST = 0x0
7292 09:58:47.689852 RD_PRE = 0x0
7293 09:58:47.692816 WR_PRE = 0x1
7294 09:58:47.692921 WR_PST = 0x1
7295 09:58:47.696208 DBI_WR = 0x0
7296 09:58:47.696290 DBI_RD = 0x0
7297 09:58:47.699930 OTF = 0x1
7298 09:58:47.702960 ===================================
7299 09:58:47.709507 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7300 09:58:47.709589 ==
7301 09:58:47.713140 Dram Type= 6, Freq= 0, CH_0, rank 0
7302 09:58:47.716540 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7303 09:58:47.716659 ==
7304 09:58:47.719991 [Duty_Offset_Calibration]
7305 09:58:47.720073 B0:2 B1:-1 CA:1
7306 09:58:47.720138
7307 09:58:47.722819 [DutyScan_Calibration_Flow] k_type=0
7308 09:58:47.732563
7309 09:58:47.732644 ==CLK 0==
7310 09:58:47.735933 Final CLK duty delay cell = -4
7311 09:58:47.739089 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7312 09:58:47.742560 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7313 09:58:47.746061 [-4] AVG Duty = 4937%(X100)
7314 09:58:47.746143
7315 09:58:47.749095 CH0 CLK Duty spec in!! Max-Min= 187%
7316 09:58:47.752462 [DutyScan_Calibration_Flow] ====Done====
7317 09:58:47.752574
7318 09:58:47.756056 [DutyScan_Calibration_Flow] k_type=1
7319 09:58:47.772179
7320 09:58:47.772261 ==DQS 0 ==
7321 09:58:47.775170 Final DQS duty delay cell = 0
7322 09:58:47.778798 [0] MAX Duty = 5125%(X100), DQS PI = 56
7323 09:58:47.781943 [0] MIN Duty = 5000%(X100), DQS PI = 14
7324 09:58:47.785416 [0] AVG Duty = 5062%(X100)
7325 09:58:47.785527
7326 09:58:47.785620 ==DQS 1 ==
7327 09:58:47.788961 Final DQS duty delay cell = -4
7328 09:58:47.791962 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7329 09:58:47.795787 [-4] MIN Duty = 5031%(X100), DQS PI = 22
7330 09:58:47.799047 [-4] AVG Duty = 5062%(X100)
7331 09:58:47.799149
7332 09:58:47.802455 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7333 09:58:47.802585
7334 09:58:47.805450 CH0 DQS 1 Duty spec in!! Max-Min= 62%
7335 09:58:47.809160 [DutyScan_Calibration_Flow] ====Done====
7336 09:58:47.809245
7337 09:58:47.812099 [DutyScan_Calibration_Flow] k_type=3
7338 09:58:47.829568
7339 09:58:47.829659 ==DQM 0 ==
7340 09:58:47.832996 Final DQM duty delay cell = 0
7341 09:58:47.836187 [0] MAX Duty = 5000%(X100), DQS PI = 18
7342 09:58:47.839416 [0] MIN Duty = 4875%(X100), DQS PI = 6
7343 09:58:47.839499 [0] AVG Duty = 4937%(X100)
7344 09:58:47.842803
7345 09:58:47.842900 ==DQM 1 ==
7346 09:58:47.846373 Final DQM duty delay cell = 0
7347 09:58:47.849265 [0] MAX Duty = 5218%(X100), DQS PI = 58
7348 09:58:47.852632 [0] MIN Duty = 4969%(X100), DQS PI = 20
7349 09:58:47.852715 [0] AVG Duty = 5093%(X100)
7350 09:58:47.856200
7351 09:58:47.859713 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7352 09:58:47.859835
7353 09:58:47.862775 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7354 09:58:47.866268 [DutyScan_Calibration_Flow] ====Done====
7355 09:58:47.866363
7356 09:58:47.869568 [DutyScan_Calibration_Flow] k_type=2
7357 09:58:47.885953
7358 09:58:47.886036 ==DQ 0 ==
7359 09:58:47.889015 Final DQ duty delay cell = -4
7360 09:58:47.892530 [-4] MAX Duty = 5031%(X100), DQS PI = 56
7361 09:58:47.896082 [-4] MIN Duty = 4844%(X100), DQS PI = 26
7362 09:58:47.898856 [-4] AVG Duty = 4937%(X100)
7363 09:58:47.898975
7364 09:58:47.899069 ==DQ 1 ==
7365 09:58:47.902492 Final DQ duty delay cell = 0
7366 09:58:47.906106 [0] MAX Duty = 5031%(X100), DQS PI = 30
7367 09:58:47.909175 [0] MIN Duty = 4907%(X100), DQS PI = 18
7368 09:58:47.909281 [0] AVG Duty = 4969%(X100)
7369 09:58:47.912518
7370 09:58:47.916031 CH0 DQ 0 Duty spec in!! Max-Min= 187%
7371 09:58:47.916103
7372 09:58:47.919255 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7373 09:58:47.922268 [DutyScan_Calibration_Flow] ====Done====
7374 09:58:47.922340 ==
7375 09:58:47.925850 Dram Type= 6, Freq= 0, CH_1, rank 0
7376 09:58:47.928921 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7377 09:58:47.929006 ==
7378 09:58:47.932657 [Duty_Offset_Calibration]
7379 09:58:47.932740 B0:1 B1:1 CA:2
7380 09:58:47.932805
7381 09:58:47.936027 [DutyScan_Calibration_Flow] k_type=0
7382 09:58:47.946408
7383 09:58:47.946491 ==CLK 0==
7384 09:58:47.949525 Final CLK duty delay cell = 0
7385 09:58:47.952949 [0] MAX Duty = 5187%(X100), DQS PI = 24
7386 09:58:47.956322 [0] MIN Duty = 4938%(X100), DQS PI = 50
7387 09:58:47.956405 [0] AVG Duty = 5062%(X100)
7388 09:58:47.959971
7389 09:58:47.960053 CH1 CLK Duty spec in!! Max-Min= 249%
7390 09:58:47.966231 [DutyScan_Calibration_Flow] ====Done====
7391 09:58:47.966314
7392 09:58:47.969392 [DutyScan_Calibration_Flow] k_type=1
7393 09:58:47.985792
7394 09:58:47.985875 ==DQS 0 ==
7395 09:58:47.989263 Final DQS duty delay cell = 0
7396 09:58:47.992465 [0] MAX Duty = 5062%(X100), DQS PI = 20
7397 09:58:47.996016 [0] MIN Duty = 4813%(X100), DQS PI = 52
7398 09:58:47.999631 [0] AVG Duty = 4937%(X100)
7399 09:58:47.999714
7400 09:58:47.999779 ==DQS 1 ==
7401 09:58:48.002589 Final DQS duty delay cell = 0
7402 09:58:48.006073 [0] MAX Duty = 5062%(X100), DQS PI = 54
7403 09:58:48.009531 [0] MIN Duty = 4938%(X100), DQS PI = 12
7404 09:58:48.009643 [0] AVG Duty = 5000%(X100)
7405 09:58:48.012407
7406 09:58:48.016103 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7407 09:58:48.016185
7408 09:58:48.019137 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7409 09:58:48.022831 [DutyScan_Calibration_Flow] ====Done====
7410 09:58:48.022924
7411 09:58:48.025846 [DutyScan_Calibration_Flow] k_type=3
7412 09:58:48.042608
7413 09:58:48.042691 ==DQM 0 ==
7414 09:58:48.046250 Final DQM duty delay cell = 0
7415 09:58:48.049520 [0] MAX Duty = 5124%(X100), DQS PI = 18
7416 09:58:48.052672 [0] MIN Duty = 4844%(X100), DQS PI = 50
7417 09:58:48.052756 [0] AVG Duty = 4984%(X100)
7418 09:58:48.056144
7419 09:58:48.056227 ==DQM 1 ==
7420 09:58:48.059691 Final DQM duty delay cell = 0
7421 09:58:48.063213 [0] MAX Duty = 5125%(X100), DQS PI = 8
7422 09:58:48.066205 [0] MIN Duty = 4875%(X100), DQS PI = 22
7423 09:58:48.066288 [0] AVG Duty = 5000%(X100)
7424 09:58:48.069385
7425 09:58:48.073036 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7426 09:58:48.073121
7427 09:58:48.076513 CH1 DQM 1 Duty spec in!! Max-Min= 250%
7428 09:58:48.079558 [DutyScan_Calibration_Flow] ====Done====
7429 09:58:48.079643
7430 09:58:48.082759 [DutyScan_Calibration_Flow] k_type=2
7431 09:58:48.099587
7432 09:58:48.099675 ==DQ 0 ==
7433 09:58:48.102912 Final DQ duty delay cell = 0
7434 09:58:48.106388 [0] MAX Duty = 5156%(X100), DQS PI = 20
7435 09:58:48.109455 [0] MIN Duty = 4907%(X100), DQS PI = 52
7436 09:58:48.109538 [0] AVG Duty = 5031%(X100)
7437 09:58:48.109603
7438 09:58:48.113027 ==DQ 1 ==
7439 09:58:48.116513 Final DQ duty delay cell = 0
7440 09:58:48.119534 [0] MAX Duty = 5093%(X100), DQS PI = 6
7441 09:58:48.123027 [0] MIN Duty = 5031%(X100), DQS PI = 0
7442 09:58:48.123139 [0] AVG Duty = 5062%(X100)
7443 09:58:48.123205
7444 09:58:48.126010 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7445 09:58:48.126095
7446 09:58:48.129721 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7447 09:58:48.136443 [DutyScan_Calibration_Flow] ====Done====
7448 09:58:48.139434 nWR fixed to 30
7449 09:58:48.139520 [ModeRegInit_LP4] CH0 RK0
7450 09:58:48.143198 [ModeRegInit_LP4] CH0 RK1
7451 09:58:48.146017 [ModeRegInit_LP4] CH1 RK0
7452 09:58:48.146101 [ModeRegInit_LP4] CH1 RK1
7453 09:58:48.149654 match AC timing 5
7454 09:58:48.153177 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7455 09:58:48.156014 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7456 09:58:48.162840 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7457 09:58:48.166120 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7458 09:58:48.172873 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7459 09:58:48.172986 [MiockJmeterHQA]
7460 09:58:48.173080
7461 09:58:48.176523 [DramcMiockJmeter] u1RxGatingPI = 0
7462 09:58:48.176607 0 : 4252, 4027
7463 09:58:48.179649 4 : 4257, 4029
7464 09:58:48.179735 8 : 4257, 4032
7465 09:58:48.183175 12 : 4253, 4027
7466 09:58:48.183263 16 : 4252, 4027
7467 09:58:48.186319 20 : 4368, 4140
7468 09:58:48.186441 24 : 4253, 4027
7469 09:58:48.186560 28 : 4252, 4027
7470 09:58:48.189609 32 : 4363, 4138
7471 09:58:48.189759 36 : 4255, 4029
7472 09:58:48.192973 40 : 4250, 4027
7473 09:58:48.193074 44 : 4250, 4026
7474 09:58:48.196283 48 : 4363, 4140
7475 09:58:48.196371 52 : 4253, 4029
7476 09:58:48.199831 56 : 4257, 4034
7477 09:58:48.199909 60 : 4361, 4137
7478 09:58:48.199985 64 : 4250, 4027
7479 09:58:48.203191 68 : 4250, 4026
7480 09:58:48.203268 72 : 4363, 4137
7481 09:58:48.206101 76 : 4250, 4027
7482 09:58:48.206181 80 : 4250, 4027
7483 09:58:48.209711 84 : 4253, 4029
7484 09:58:48.209794 88 : 4258, 4031
7485 09:58:48.212865 92 : 4253, 4029
7486 09:58:48.212953 96 : 4361, 3494
7487 09:58:48.213022 100 : 4252, 0
7488 09:58:48.216467 104 : 4255, 0
7489 09:58:48.216549 108 : 4252, 0
7490 09:58:48.220018 112 : 4363, 0
7491 09:58:48.220108 116 : 4250, 0
7492 09:58:48.220175 120 : 4363, 0
7493 09:58:48.223057 124 : 4250, 0
7494 09:58:48.223143 128 : 4255, 0
7495 09:58:48.223211 132 : 4250, 0
7496 09:58:48.226819 136 : 4253, 0
7497 09:58:48.226912 140 : 4255, 0
7498 09:58:48.229831 144 : 4253, 0
7499 09:58:48.229944 148 : 4250, 0
7500 09:58:48.230015 152 : 4254, 0
7501 09:58:48.233395 156 : 4250, 0
7502 09:58:48.233502 160 : 4250, 0
7503 09:58:48.236387 164 : 4250, 0
7504 09:58:48.236491 168 : 4255, 0
7505 09:58:48.236588 172 : 4250, 0
7506 09:58:48.239979 176 : 4250, 0
7507 09:58:48.240087 180 : 4257, 0
7508 09:58:48.240181 184 : 4363, 0
7509 09:58:48.243581 188 : 4363, 0
7510 09:58:48.243689 192 : 4252, 0
7511 09:58:48.246574 196 : 4252, 0
7512 09:58:48.246683 200 : 4361, 0
7513 09:58:48.246778 204 : 4252, 0
7514 09:58:48.249770 208 : 4255, 0
7515 09:58:48.249857 212 : 4250, 186
7516 09:58:48.253104 216 : 4252, 3832
7517 09:58:48.253182 220 : 4250, 4027
7518 09:58:48.256764 224 : 4250, 4027
7519 09:58:48.256844 228 : 4250, 4027
7520 09:58:48.259795 232 : 4250, 4026
7521 09:58:48.259871 236 : 4363, 4140
7522 09:58:48.259934 240 : 4364, 4140
7523 09:58:48.263470 244 : 4361, 4138
7524 09:58:48.263547 248 : 4366, 4140
7525 09:58:48.266754 252 : 4250, 4027
7526 09:58:48.266856 256 : 4365, 4142
7527 09:58:48.270115 260 : 4252, 4029
7528 09:58:48.270201 264 : 4253, 4029
7529 09:58:48.273212 268 : 4252, 4029
7530 09:58:48.273309 272 : 4365, 4140
7531 09:58:48.276701 276 : 4366, 4140
7532 09:58:48.276787 280 : 4255, 4029
7533 09:58:48.279660 284 : 4253, 4029
7534 09:58:48.279746 288 : 4255, 4029
7535 09:58:48.279813 292 : 4250, 4027
7536 09:58:48.283294 296 : 4255, 4030
7537 09:58:48.283380 300 : 4250, 4027
7538 09:58:48.286424 304 : 4255, 4032
7539 09:58:48.286510 308 : 4255, 4029
7540 09:58:48.289948 312 : 4363, 4137
7541 09:58:48.290033 316 : 4255, 4029
7542 09:58:48.292987 320 : 4252, 4029
7543 09:58:48.293072 324 : 4365, 4140
7544 09:58:48.296480 328 : 4250, 4027
7545 09:58:48.296565 332 : 4250, 3188
7546 09:58:48.299825 336 : 4250, 108
7547 09:58:48.299910
7548 09:58:48.299976 MIOCK jitter meter ch=0
7549 09:58:48.300038
7550 09:58:48.303428 1T = (336-100) = 236 dly cells
7551 09:58:48.309932 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7552 09:58:48.310017 ==
7553 09:58:48.313103 Dram Type= 6, Freq= 0, CH_0, rank 0
7554 09:58:48.316439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7555 09:58:48.316523 ==
7556 09:58:48.323144 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7557 09:58:48.326934 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7558 09:58:48.329941 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7559 09:58:48.336491 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7560 09:58:48.346157 [CA 0] Center 44 (14~75) winsize 62
7561 09:58:48.349238 [CA 1] Center 44 (13~75) winsize 63
7562 09:58:48.353105 [CA 2] Center 40 (11~69) winsize 59
7563 09:58:48.356409 [CA 3] Center 39 (10~69) winsize 60
7564 09:58:48.359468 [CA 4] Center 38 (8~68) winsize 61
7565 09:58:48.362699 [CA 5] Center 37 (7~67) winsize 61
7566 09:58:48.362783
7567 09:58:48.366196 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7568 09:58:48.366281
7569 09:58:48.369659 [CATrainingPosCal] consider 1 rank data
7570 09:58:48.372812 u2DelayCellTimex100 = 275/100 ps
7571 09:58:48.376025 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7572 09:58:48.383125 CA1 delay=44 (13~75),Diff = 7 PI (24 cell)
7573 09:58:48.386155 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7574 09:58:48.390059 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7575 09:58:48.393470 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
7576 09:58:48.396219 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7577 09:58:48.396326
7578 09:58:48.399910 CA PerBit enable=1, Macro0, CA PI delay=37
7579 09:58:48.399993
7580 09:58:48.402991 [CBTSetCACLKResult] CA Dly = 37
7581 09:58:48.406216 CS Dly: 10 (0~41)
7582 09:58:48.409734 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7583 09:58:48.412817 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7584 09:58:48.412900 ==
7585 09:58:48.416546 Dram Type= 6, Freq= 0, CH_0, rank 1
7586 09:58:48.419413 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7587 09:58:48.423203 ==
7588 09:58:48.426265 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7589 09:58:48.429666 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7590 09:58:48.436411 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7591 09:58:48.439717 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7592 09:58:48.449867 [CA 0] Center 44 (14~75) winsize 62
7593 09:58:48.453468 [CA 1] Center 44 (14~75) winsize 62
7594 09:58:48.457096 [CA 2] Center 40 (11~69) winsize 59
7595 09:58:48.460153 [CA 3] Center 39 (10~69) winsize 60
7596 09:58:48.463970 [CA 4] Center 38 (9~68) winsize 60
7597 09:58:48.466936 [CA 5] Center 37 (7~67) winsize 61
7598 09:58:48.467043
7599 09:58:48.469917 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7600 09:58:48.470028
7601 09:58:48.473276 [CATrainingPosCal] consider 2 rank data
7602 09:58:48.477072 u2DelayCellTimex100 = 275/100 ps
7603 09:58:48.480048 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7604 09:58:48.486856 CA1 delay=44 (14~75),Diff = 7 PI (24 cell)
7605 09:58:48.490214 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7606 09:58:48.493813 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7607 09:58:48.496990 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
7608 09:58:48.500497 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7609 09:58:48.500598
7610 09:58:48.503620 CA PerBit enable=1, Macro0, CA PI delay=37
7611 09:58:48.503724
7612 09:58:48.506978 [CBTSetCACLKResult] CA Dly = 37
7613 09:58:48.510351 CS Dly: 11 (0~44)
7614 09:58:48.513604 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7615 09:58:48.516992 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7616 09:58:48.517099
7617 09:58:48.520167 ----->DramcWriteLeveling(PI) begin...
7618 09:58:48.520279 ==
7619 09:58:48.523929 Dram Type= 6, Freq= 0, CH_0, rank 0
7620 09:58:48.526856 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7621 09:58:48.530221 ==
7622 09:58:48.530299 Write leveling (Byte 0): 32 => 32
7623 09:58:48.534057 Write leveling (Byte 1): 27 => 27
7624 09:58:48.536819 DramcWriteLeveling(PI) end<-----
7625 09:58:48.536930
7626 09:58:48.537026 ==
7627 09:58:48.540254 Dram Type= 6, Freq= 0, CH_0, rank 0
7628 09:58:48.546823 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7629 09:58:48.546928 ==
7630 09:58:48.546996 [Gating] SW mode calibration
7631 09:58:48.556885 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7632 09:58:48.560574 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7633 09:58:48.564173 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7634 09:58:48.570162 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7635 09:58:48.573779 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7636 09:58:48.576848 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7637 09:58:48.583866 1 4 16 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7638 09:58:48.587278 1 4 20 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
7639 09:58:48.590581 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7640 09:58:48.597203 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7641 09:58:48.600566 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7642 09:58:48.603581 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7643 09:58:48.610342 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7644 09:58:48.614091 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7645 09:58:48.617253 1 5 16 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
7646 09:58:48.623535 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7647 09:58:48.627067 1 5 24 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
7648 09:58:48.630846 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7649 09:58:48.633919 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7650 09:58:48.640766 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7651 09:58:48.643974 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7652 09:58:48.647012 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7653 09:58:48.654056 1 6 16 | B1->B0 | 2323 3837 | 0 1 | (0 0) (0 0)
7654 09:58:48.657544 1 6 20 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
7655 09:58:48.660454 1 6 24 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
7656 09:58:48.667371 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7657 09:58:48.671015 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7658 09:58:48.674052 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7659 09:58:48.680719 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7660 09:58:48.684152 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7661 09:58:48.687216 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7662 09:58:48.694275 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7663 09:58:48.697348 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7664 09:58:48.700501 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7665 09:58:48.707333 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 09:58:48.710476 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 09:58:48.714259 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 09:58:48.717274 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 09:58:48.723959 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 09:58:48.727972 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 09:58:48.730715 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 09:58:48.737769 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7673 09:58:48.740895 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7674 09:58:48.744490 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7675 09:58:48.750930 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7676 09:58:48.754445 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 09:58:48.757906 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7678 09:58:48.764511 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7679 09:58:48.764638 Total UI for P1: 0, mck2ui 16
7680 09:58:48.770740 best dqsien dly found for B0: ( 1, 9, 16)
7681 09:58:48.774057 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7682 09:58:48.777733 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7683 09:58:48.780968 Total UI for P1: 0, mck2ui 16
7684 09:58:48.784137 best dqsien dly found for B1: ( 1, 9, 22)
7685 09:58:48.787787 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7686 09:58:48.790901 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7687 09:58:48.791001
7688 09:58:48.794029 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7689 09:58:48.800862 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7690 09:58:48.800966 [Gating] SW calibration Done
7691 09:58:48.804409 ==
7692 09:58:48.804486 Dram Type= 6, Freq= 0, CH_0, rank 0
7693 09:58:48.810605 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7694 09:58:48.810717 ==
7695 09:58:48.810817 RX Vref Scan: 0
7696 09:58:48.810922
7697 09:58:48.814301 RX Vref 0 -> 0, step: 1
7698 09:58:48.814374
7699 09:58:48.817482 RX Delay 0 -> 252, step: 8
7700 09:58:48.820562 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7701 09:58:48.824256 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7702 09:58:48.827164 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7703 09:58:48.834059 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7704 09:58:48.837873 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7705 09:58:48.840686 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7706 09:58:48.844222 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7707 09:58:48.847311 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7708 09:58:48.851109 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7709 09:58:48.857596 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7710 09:58:48.860689 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7711 09:58:48.864233 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7712 09:58:48.867126 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7713 09:58:48.870899 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7714 09:58:48.877858 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7715 09:58:48.880734 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7716 09:58:48.880848 ==
7717 09:58:48.884673 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 09:58:48.887306 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7719 09:58:48.887401 ==
7720 09:58:48.891090 DQS Delay:
7721 09:58:48.891175 DQS0 = 0, DQS1 = 0
7722 09:58:48.891240 DQM Delay:
7723 09:58:48.894022 DQM0 = 132, DQM1 = 123
7724 09:58:48.894126 DQ Delay:
7725 09:58:48.897843 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7726 09:58:48.900879 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7727 09:58:48.908009 DQ8 =111, DQ9 =111, DQ10 =119, DQ11 =115
7728 09:58:48.910822 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7729 09:58:48.910923
7730 09:58:48.910990
7731 09:58:48.911051 ==
7732 09:58:48.914311 Dram Type= 6, Freq= 0, CH_0, rank 0
7733 09:58:48.917973 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7734 09:58:48.918079 ==
7735 09:58:48.918181
7736 09:58:48.918288
7737 09:58:48.921026 TX Vref Scan disable
7738 09:58:48.921135 == TX Byte 0 ==
7739 09:58:48.927885 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7740 09:58:48.930873 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7741 09:58:48.930953 == TX Byte 1 ==
7742 09:58:48.937728 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7743 09:58:48.941160 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7744 09:58:48.941267 ==
7745 09:58:48.944320 Dram Type= 6, Freq= 0, CH_0, rank 0
7746 09:58:48.947532 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7747 09:58:48.947612 ==
7748 09:58:48.963386
7749 09:58:48.966324 TX Vref early break, caculate TX vref
7750 09:58:48.969750 TX Vref=16, minBit 1, minWin=21, winSum=352
7751 09:58:48.973367 TX Vref=18, minBit 7, minWin=21, winSum=365
7752 09:58:48.976392 TX Vref=20, minBit 4, minWin=22, winSum=378
7753 09:58:48.979721 TX Vref=22, minBit 7, minWin=23, winSum=385
7754 09:58:48.983049 TX Vref=24, minBit 1, minWin=24, winSum=397
7755 09:58:48.989951 TX Vref=26, minBit 4, minWin=24, winSum=409
7756 09:58:48.993217 TX Vref=28, minBit 1, minWin=24, winSum=412
7757 09:58:48.996099 TX Vref=30, minBit 4, minWin=24, winSum=410
7758 09:58:48.999348 TX Vref=32, minBit 0, minWin=24, winSum=406
7759 09:58:49.002930 TX Vref=34, minBit 0, minWin=23, winSum=392
7760 09:58:49.006548 TX Vref=36, minBit 0, minWin=22, winSum=382
7761 09:58:49.013189 [TxChooseVref] Worse bit 1, Min win 24, Win sum 412, Final Vref 28
7762 09:58:49.013298
7763 09:58:49.016678 Final TX Range 0 Vref 28
7764 09:58:49.016784
7765 09:58:49.016879 ==
7766 09:58:49.019723 Dram Type= 6, Freq= 0, CH_0, rank 0
7767 09:58:49.022864 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7768 09:58:49.022950 ==
7769 09:58:49.023048
7770 09:58:49.023139
7771 09:58:49.026423 TX Vref Scan disable
7772 09:58:49.033105 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7773 09:58:49.033215 == TX Byte 0 ==
7774 09:58:49.036265 u2DelayCellOfst[0]=17 cells (5 PI)
7775 09:58:49.039575 u2DelayCellOfst[1]=24 cells (7 PI)
7776 09:58:49.043169 u2DelayCellOfst[2]=14 cells (4 PI)
7777 09:58:49.046076 u2DelayCellOfst[3]=17 cells (5 PI)
7778 09:58:49.049796 u2DelayCellOfst[4]=10 cells (3 PI)
7779 09:58:49.052836 u2DelayCellOfst[5]=0 cells (0 PI)
7780 09:58:49.056641 u2DelayCellOfst[6]=24 cells (7 PI)
7781 09:58:49.059647 u2DelayCellOfst[7]=21 cells (6 PI)
7782 09:58:49.063267 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7783 09:58:49.066158 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7784 09:58:49.069876 == TX Byte 1 ==
7785 09:58:49.072790 u2DelayCellOfst[8]=0 cells (0 PI)
7786 09:58:49.072870 u2DelayCellOfst[9]=0 cells (0 PI)
7787 09:58:49.076791 u2DelayCellOfst[10]=7 cells (2 PI)
7788 09:58:49.079761 u2DelayCellOfst[11]=3 cells (1 PI)
7789 09:58:49.082761 u2DelayCellOfst[12]=10 cells (3 PI)
7790 09:58:49.086615 u2DelayCellOfst[13]=10 cells (3 PI)
7791 09:58:49.089841 u2DelayCellOfst[14]=17 cells (5 PI)
7792 09:58:49.093091 u2DelayCellOfst[15]=10 cells (3 PI)
7793 09:58:49.096542 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7794 09:58:49.102869 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7795 09:58:49.102959 DramC Write-DBI on
7796 09:58:49.103025 ==
7797 09:58:49.106916 Dram Type= 6, Freq= 0, CH_0, rank 0
7798 09:58:49.109956 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7799 09:58:49.112871 ==
7800 09:58:49.112951
7801 09:58:49.113017
7802 09:58:49.113110 TX Vref Scan disable
7803 09:58:49.116712 == TX Byte 0 ==
7804 09:58:49.120242 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7805 09:58:49.123308 == TX Byte 1 ==
7806 09:58:49.126746 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7807 09:58:49.126868 DramC Write-DBI off
7808 09:58:49.129881
7809 09:58:49.129974 [DATLAT]
7810 09:58:49.130073 Freq=1600, CH0 RK0
7811 09:58:49.130173
7812 09:58:49.133492 DATLAT Default: 0xf
7813 09:58:49.133599 0, 0xFFFF, sum = 0
7814 09:58:49.136647 1, 0xFFFF, sum = 0
7815 09:58:49.136757 2, 0xFFFF, sum = 0
7816 09:58:49.140360 3, 0xFFFF, sum = 0
7817 09:58:49.143035 4, 0xFFFF, sum = 0
7818 09:58:49.143122 5, 0xFFFF, sum = 0
7819 09:58:49.146636 6, 0xFFFF, sum = 0
7820 09:58:49.146745 7, 0xFFFF, sum = 0
7821 09:58:49.150016 8, 0xFFFF, sum = 0
7822 09:58:49.150106 9, 0xFFFF, sum = 0
7823 09:58:49.153082 10, 0xFFFF, sum = 0
7824 09:58:49.153192 11, 0xFFFF, sum = 0
7825 09:58:49.156765 12, 0xFFFF, sum = 0
7826 09:58:49.156876 13, 0xFFFF, sum = 0
7827 09:58:49.160621 14, 0x0, sum = 1
7828 09:58:49.160728 15, 0x0, sum = 2
7829 09:58:49.163560 16, 0x0, sum = 3
7830 09:58:49.163672 17, 0x0, sum = 4
7831 09:58:49.167191 best_step = 15
7832 09:58:49.167297
7833 09:58:49.167392 ==
7834 09:58:49.169971 Dram Type= 6, Freq= 0, CH_0, rank 0
7835 09:58:49.173956 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7836 09:58:49.174045 ==
7837 09:58:49.174144 RX Vref Scan: 1
7838 09:58:49.174237
7839 09:58:49.177021 Set Vref Range= 24 -> 127
7840 09:58:49.177097
7841 09:58:49.180164 RX Vref 24 -> 127, step: 1
7842 09:58:49.180273
7843 09:58:49.183817 RX Delay 11 -> 252, step: 4
7844 09:58:49.183922
7845 09:58:49.186895 Set Vref, RX VrefLevel [Byte0]: 24
7846 09:58:49.190104 [Byte1]: 24
7847 09:58:49.190206
7848 09:58:49.193921 Set Vref, RX VrefLevel [Byte0]: 25
7849 09:58:49.196978 [Byte1]: 25
7850 09:58:49.197063
7851 09:58:49.200288 Set Vref, RX VrefLevel [Byte0]: 26
7852 09:58:49.203816 [Byte1]: 26
7853 09:58:49.207143
7854 09:58:49.207252 Set Vref, RX VrefLevel [Byte0]: 27
7855 09:58:49.210686 [Byte1]: 27
7856 09:58:49.214851
7857 09:58:49.214959 Set Vref, RX VrefLevel [Byte0]: 28
7858 09:58:49.218122 [Byte1]: 28
7859 09:58:49.222334
7860 09:58:49.222449 Set Vref, RX VrefLevel [Byte0]: 29
7861 09:58:49.225844 [Byte1]: 29
7862 09:58:49.229995
7863 09:58:49.230108 Set Vref, RX VrefLevel [Byte0]: 30
7864 09:58:49.233536 [Byte1]: 30
7865 09:58:49.237647
7866 09:58:49.237755 Set Vref, RX VrefLevel [Byte0]: 31
7867 09:58:49.240477 [Byte1]: 31
7868 09:58:49.245056
7869 09:58:49.245170 Set Vref, RX VrefLevel [Byte0]: 32
7870 09:58:49.248125 [Byte1]: 32
7871 09:58:49.253062
7872 09:58:49.253172 Set Vref, RX VrefLevel [Byte0]: 33
7873 09:58:49.255875 [Byte1]: 33
7874 09:58:49.260540
7875 09:58:49.260624 Set Vref, RX VrefLevel [Byte0]: 34
7876 09:58:49.263696 [Byte1]: 34
7877 09:58:49.268035
7878 09:58:49.268124 Set Vref, RX VrefLevel [Byte0]: 35
7879 09:58:49.270955 [Byte1]: 35
7880 09:58:49.275789
7881 09:58:49.275869 Set Vref, RX VrefLevel [Byte0]: 36
7882 09:58:49.278844 [Byte1]: 36
7883 09:58:49.283056
7884 09:58:49.283138 Set Vref, RX VrefLevel [Byte0]: 37
7885 09:58:49.286232 [Byte1]: 37
7886 09:58:49.290525
7887 09:58:49.290637 Set Vref, RX VrefLevel [Byte0]: 38
7888 09:58:49.294204 [Byte1]: 38
7889 09:58:49.298460
7890 09:58:49.298566 Set Vref, RX VrefLevel [Byte0]: 39
7891 09:58:49.301534 [Byte1]: 39
7892 09:58:49.306038
7893 09:58:49.306118 Set Vref, RX VrefLevel [Byte0]: 40
7894 09:58:49.309242 [Byte1]: 40
7895 09:58:49.313367
7896 09:58:49.313472 Set Vref, RX VrefLevel [Byte0]: 41
7897 09:58:49.317109 [Byte1]: 41
7898 09:58:49.321339
7899 09:58:49.321452 Set Vref, RX VrefLevel [Byte0]: 42
7900 09:58:49.324665 [Byte1]: 42
7901 09:58:49.329261
7902 09:58:49.329368 Set Vref, RX VrefLevel [Byte0]: 43
7903 09:58:49.332150 [Byte1]: 43
7904 09:58:49.336499
7905 09:58:49.336607 Set Vref, RX VrefLevel [Byte0]: 44
7906 09:58:49.339800 [Byte1]: 44
7907 09:58:49.344007
7908 09:58:49.344116 Set Vref, RX VrefLevel [Byte0]: 45
7909 09:58:49.347385 [Byte1]: 45
7910 09:58:49.351702
7911 09:58:49.351784 Set Vref, RX VrefLevel [Byte0]: 46
7912 09:58:49.355231 [Byte1]: 46
7913 09:58:49.359352
7914 09:58:49.359436 Set Vref, RX VrefLevel [Byte0]: 47
7915 09:58:49.362849 [Byte1]: 47
7916 09:58:49.366954
7917 09:58:49.367040 Set Vref, RX VrefLevel [Byte0]: 48
7918 09:58:49.369936 [Byte1]: 48
7919 09:58:49.374712
7920 09:58:49.374821 Set Vref, RX VrefLevel [Byte0]: 49
7921 09:58:49.377667 [Byte1]: 49
7922 09:58:49.382453
7923 09:58:49.382562 Set Vref, RX VrefLevel [Byte0]: 50
7924 09:58:49.385717 [Byte1]: 50
7925 09:58:49.389969
7926 09:58:49.390067 Set Vref, RX VrefLevel [Byte0]: 51
7927 09:58:49.393166 [Byte1]: 51
7928 09:58:49.397339
7929 09:58:49.397420 Set Vref, RX VrefLevel [Byte0]: 52
7930 09:58:49.400465 [Byte1]: 52
7931 09:58:49.404771
7932 09:58:49.404877 Set Vref, RX VrefLevel [Byte0]: 53
7933 09:58:49.408457 [Byte1]: 53
7934 09:58:49.412759
7935 09:58:49.412866 Set Vref, RX VrefLevel [Byte0]: 54
7936 09:58:49.415692 [Byte1]: 54
7937 09:58:49.420141
7938 09:58:49.420260 Set Vref, RX VrefLevel [Byte0]: 55
7939 09:58:49.423252 [Byte1]: 55
7940 09:58:49.427614
7941 09:58:49.427737 Set Vref, RX VrefLevel [Byte0]: 56
7942 09:58:49.430755 [Byte1]: 56
7943 09:58:49.435507
7944 09:58:49.435616 Set Vref, RX VrefLevel [Byte0]: 57
7945 09:58:49.438716 [Byte1]: 57
7946 09:58:49.442914
7947 09:58:49.443024 Set Vref, RX VrefLevel [Byte0]: 58
7948 09:58:49.446442 [Byte1]: 58
7949 09:58:49.451077
7950 09:58:49.451183 Set Vref, RX VrefLevel [Byte0]: 59
7951 09:58:49.453629 [Byte1]: 59
7952 09:58:49.458213
7953 09:58:49.458327 Set Vref, RX VrefLevel [Byte0]: 60
7954 09:58:49.461362 [Byte1]: 60
7955 09:58:49.465986
7956 09:58:49.466069 Set Vref, RX VrefLevel [Byte0]: 61
7957 09:58:49.469242 [Byte1]: 61
7958 09:58:49.473164
7959 09:58:49.473274 Set Vref, RX VrefLevel [Byte0]: 62
7960 09:58:49.476862 [Byte1]: 62
7961 09:58:49.481168
7962 09:58:49.481283 Set Vref, RX VrefLevel [Byte0]: 63
7963 09:58:49.484278 [Byte1]: 63
7964 09:58:49.488471
7965 09:58:49.488579 Set Vref, RX VrefLevel [Byte0]: 64
7966 09:58:49.492159 [Byte1]: 64
7967 09:58:49.496651
7968 09:58:49.496770 Set Vref, RX VrefLevel [Byte0]: 65
7969 09:58:49.499501 [Byte1]: 65
7970 09:58:49.503782
7971 09:58:49.503896 Set Vref, RX VrefLevel [Byte0]: 66
7972 09:58:49.507274 [Byte1]: 66
7973 09:58:49.511780
7974 09:58:49.511862 Set Vref, RX VrefLevel [Byte0]: 67
7975 09:58:49.514633 [Byte1]: 67
7976 09:58:49.518964
7977 09:58:49.519071 Set Vref, RX VrefLevel [Byte0]: 68
7978 09:58:49.525524 [Byte1]: 68
7979 09:58:49.525612
7980 09:58:49.529237 Set Vref, RX VrefLevel [Byte0]: 69
7981 09:58:49.532624 [Byte1]: 69
7982 09:58:49.532709
7983 09:58:49.535467 Set Vref, RX VrefLevel [Byte0]: 70
7984 09:58:49.539096 [Byte1]: 70
7985 09:58:49.539177
7986 09:58:49.542130 Set Vref, RX VrefLevel [Byte0]: 71
7987 09:58:49.545727 [Byte1]: 71
7988 09:58:49.549267
7989 09:58:49.549345 Set Vref, RX VrefLevel [Byte0]: 72
7990 09:58:49.552715 [Byte1]: 72
7991 09:58:49.556891
7992 09:58:49.556976 Set Vref, RX VrefLevel [Byte0]: 73
7993 09:58:49.560487 [Byte1]: 73
7994 09:58:49.564803
7995 09:58:49.564910 Set Vref, RX VrefLevel [Byte0]: 74
7996 09:58:49.567786 [Byte1]: 74
7997 09:58:49.572754
7998 09:58:49.572835 Set Vref, RX VrefLevel [Byte0]: 75
7999 09:58:49.575590 [Byte1]: 75
8000 09:58:49.580081
8001 09:58:49.580191 Set Vref, RX VrefLevel [Byte0]: 76
8002 09:58:49.582974 [Byte1]: 76
8003 09:58:49.587782
8004 09:58:49.587857 Final RX Vref Byte 0 = 61 to rank0
8005 09:58:49.590667 Final RX Vref Byte 1 = 63 to rank0
8006 09:58:49.594646 Final RX Vref Byte 0 = 61 to rank1
8007 09:58:49.597480 Final RX Vref Byte 1 = 63 to rank1==
8008 09:58:49.601123 Dram Type= 6, Freq= 0, CH_0, rank 0
8009 09:58:49.607839 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8010 09:58:49.607948 ==
8011 09:58:49.608046 DQS Delay:
8012 09:58:49.608125 DQS0 = 0, DQS1 = 0
8013 09:58:49.610902 DQM Delay:
8014 09:58:49.610987 DQM0 = 129, DQM1 = 121
8015 09:58:49.614095 DQ Delay:
8016 09:58:49.617649 DQ0 =130, DQ1 =132, DQ2 =126, DQ3 =126
8017 09:58:49.621214 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
8018 09:58:49.624189 DQ8 =110, DQ9 =108, DQ10 =122, DQ11 =116
8019 09:58:49.627935 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =132
8020 09:58:49.628038
8021 09:58:49.628130
8022 09:58:49.628224
8023 09:58:49.630956 [DramC_TX_OE_Calibration] TA2
8024 09:58:49.634113 Original DQ_B0 (3 6) =30, OEN = 27
8025 09:58:49.637823 Original DQ_B1 (3 6) =30, OEN = 27
8026 09:58:49.641114 24, 0x0, End_B0=24 End_B1=24
8027 09:58:49.641231 25, 0x0, End_B0=25 End_B1=25
8028 09:58:49.644193 26, 0x0, End_B0=26 End_B1=26
8029 09:58:49.647922 27, 0x0, End_B0=27 End_B1=27
8030 09:58:49.651024 28, 0x0, End_B0=28 End_B1=28
8031 09:58:49.651133 29, 0x0, End_B0=29 End_B1=29
8032 09:58:49.654646 30, 0x0, End_B0=30 End_B1=30
8033 09:58:49.657604 31, 0x4141, End_B0=30 End_B1=30
8034 09:58:49.660911 Byte0 end_step=30 best_step=27
8035 09:58:49.664967 Byte1 end_step=30 best_step=27
8036 09:58:49.667670 Byte0 TX OE(2T, 0.5T) = (3, 3)
8037 09:58:49.667778 Byte1 TX OE(2T, 0.5T) = (3, 3)
8038 09:58:49.667874
8039 09:58:49.667966
8040 09:58:49.678018 [DQSOSCAuto] RK0, (LSB)MR18= 0x1509, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
8041 09:58:49.680960 CH0 RK0: MR19=303, MR18=1509
8042 09:58:49.684515 CH0_RK0: MR19=0x303, MR18=0x1509, DQSOSC=399, MR23=63, INC=23, DEC=15
8043 09:58:49.688206
8044 09:58:49.691195 ----->DramcWriteLeveling(PI) begin...
8045 09:58:49.691291 ==
8046 09:58:49.694572 Dram Type= 6, Freq= 0, CH_0, rank 1
8047 09:58:49.697794 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8048 09:58:49.697901 ==
8049 09:58:49.701060 Write leveling (Byte 0): 34 => 34
8050 09:58:49.704763 Write leveling (Byte 1): 27 => 27
8051 09:58:49.707885 DramcWriteLeveling(PI) end<-----
8052 09:58:49.707966
8053 09:58:49.708033 ==
8054 09:58:49.711385 Dram Type= 6, Freq= 0, CH_0, rank 1
8055 09:58:49.714486 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8056 09:58:49.714596 ==
8057 09:58:49.718212 [Gating] SW mode calibration
8058 09:58:49.724618 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8059 09:58:49.731490 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8060 09:58:49.734614 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8061 09:58:49.737788 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8062 09:58:49.744895 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8063 09:58:49.748057 1 4 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8064 09:58:49.751050 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8065 09:58:49.754719 1 4 20 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
8066 09:58:49.760953 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8067 09:58:49.764683 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8068 09:58:49.767627 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 09:58:49.774432 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8070 09:58:49.777678 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
8071 09:58:49.781542 1 5 12 | B1->B0 | 3434 2828 | 1 1 | (1 1) (1 0)
8072 09:58:49.788016 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8073 09:58:49.791326 1 5 20 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
8074 09:58:49.794361 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8075 09:58:49.801163 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 09:58:49.804704 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 09:58:49.807804 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 09:58:49.814760 1 6 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8079 09:58:49.818106 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8080 09:58:49.821152 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8081 09:58:49.827892 1 6 20 | B1->B0 | 3333 4646 | 0 0 | (1 1) (0 0)
8082 09:58:49.831051 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8083 09:58:49.834694 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8084 09:58:49.841353 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 09:58:49.844450 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 09:58:49.847785 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8087 09:58:49.851426 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8088 09:58:49.858098 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8089 09:58:49.861029 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8090 09:58:49.864742 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8091 09:58:49.871624 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 09:58:49.874419 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 09:58:49.878219 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 09:58:49.884780 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 09:58:49.887764 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 09:58:49.891796 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 09:58:49.897754 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 09:58:49.901278 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 09:58:49.904952 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 09:58:49.911308 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 09:58:49.914731 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 09:58:49.918083 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8103 09:58:49.924635 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8104 09:58:49.928245 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8105 09:58:49.931685 Total UI for P1: 0, mck2ui 16
8106 09:58:49.934736 best dqsien dly found for B0: ( 1, 9, 10)
8107 09:58:49.938287 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8108 09:58:49.941265 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8109 09:58:49.944954 Total UI for P1: 0, mck2ui 16
8110 09:58:49.948062 best dqsien dly found for B1: ( 1, 9, 18)
8111 09:58:49.951711 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8112 09:58:49.954842 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8113 09:58:49.954949
8114 09:58:49.961635 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8115 09:58:49.964954 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8116 09:58:49.968483 [Gating] SW calibration Done
8117 09:58:49.968598 ==
8118 09:58:49.971348 Dram Type= 6, Freq= 0, CH_0, rank 1
8119 09:58:49.975128 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8120 09:58:49.975303 ==
8121 09:58:49.975432 RX Vref Scan: 0
8122 09:58:49.975552
8123 09:58:49.978518 RX Vref 0 -> 0, step: 1
8124 09:58:49.978614
8125 09:58:49.981493 RX Delay 0 -> 252, step: 8
8126 09:58:49.985100 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8127 09:58:49.988713 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8128 09:58:49.991721 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
8129 09:58:49.998523 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8130 09:58:50.002112 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8131 09:58:50.005087 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8132 09:58:50.008629 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8133 09:58:50.011974 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8134 09:58:50.018571 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8135 09:58:50.021525 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8136 09:58:50.024932 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8137 09:58:50.028320 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8138 09:58:50.031692 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8139 09:58:50.038664 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8140 09:58:50.041732 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8141 09:58:50.045100 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8142 09:58:50.045183 ==
8143 09:58:50.048723 Dram Type= 6, Freq= 0, CH_0, rank 1
8144 09:58:50.052171 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8145 09:58:50.052253 ==
8146 09:58:50.055897 DQS Delay:
8147 09:58:50.056012 DQS0 = 0, DQS1 = 0
8148 09:58:50.056107 DQM Delay:
8149 09:58:50.058798 DQM0 = 131, DQM1 = 123
8150 09:58:50.058906 DQ Delay:
8151 09:58:50.061958 DQ0 =131, DQ1 =131, DQ2 =131, DQ3 =127
8152 09:58:50.065504 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8153 09:58:50.072318 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
8154 09:58:50.075190 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
8155 09:58:50.075299
8156 09:58:50.075397
8157 09:58:50.075491 ==
8158 09:58:50.078830 Dram Type= 6, Freq= 0, CH_0, rank 1
8159 09:58:50.081892 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8160 09:58:50.081997 ==
8161 09:58:50.082090
8162 09:58:50.082180
8163 09:58:50.085510 TX Vref Scan disable
8164 09:58:50.088596 == TX Byte 0 ==
8165 09:58:50.092205 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8166 09:58:50.095272 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8167 09:58:50.098728 == TX Byte 1 ==
8168 09:58:50.102276 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8169 09:58:50.105206 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8170 09:58:50.105307 ==
8171 09:58:50.108885 Dram Type= 6, Freq= 0, CH_0, rank 1
8172 09:58:50.112490 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8173 09:58:50.112591 ==
8174 09:58:50.127833
8175 09:58:50.131733 TX Vref early break, caculate TX vref
8176 09:58:50.134723 TX Vref=16, minBit 8, minWin=22, winSum=372
8177 09:58:50.138173 TX Vref=18, minBit 0, minWin=23, winSum=384
8178 09:58:50.141721 TX Vref=20, minBit 0, minWin=23, winSum=388
8179 09:58:50.144718 TX Vref=22, minBit 0, minWin=24, winSum=399
8180 09:58:50.148228 TX Vref=24, minBit 4, minWin=24, winSum=401
8181 09:58:50.154957 TX Vref=26, minBit 0, minWin=25, winSum=412
8182 09:58:50.157962 TX Vref=28, minBit 4, minWin=25, winSum=421
8183 09:58:50.161118 TX Vref=30, minBit 4, minWin=25, winSum=418
8184 09:58:50.164405 TX Vref=32, minBit 0, minWin=25, winSum=415
8185 09:58:50.168204 TX Vref=34, minBit 8, minWin=24, winSum=403
8186 09:58:50.171203 TX Vref=36, minBit 0, minWin=23, winSum=389
8187 09:58:50.178224 [TxChooseVref] Worse bit 4, Min win 25, Win sum 421, Final Vref 28
8188 09:58:50.178328
8189 09:58:50.181462 Final TX Range 0 Vref 28
8190 09:58:50.181567
8191 09:58:50.181643 ==
8192 09:58:50.184472 Dram Type= 6, Freq= 0, CH_0, rank 1
8193 09:58:50.187991 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8194 09:58:50.188062 ==
8195 09:58:50.188123
8196 09:58:50.188185
8197 09:58:50.190977 TX Vref Scan disable
8198 09:58:50.197785 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8199 09:58:50.197885 == TX Byte 0 ==
8200 09:58:50.201226 u2DelayCellOfst[0]=14 cells (4 PI)
8201 09:58:50.204950 u2DelayCellOfst[1]=17 cells (5 PI)
8202 09:58:50.208127 u2DelayCellOfst[2]=10 cells (3 PI)
8203 09:58:50.211300 u2DelayCellOfst[3]=10 cells (3 PI)
8204 09:58:50.214325 u2DelayCellOfst[4]=10 cells (3 PI)
8205 09:58:50.217726 u2DelayCellOfst[5]=0 cells (0 PI)
8206 09:58:50.221191 u2DelayCellOfst[6]=17 cells (5 PI)
8207 09:58:50.224776 u2DelayCellOfst[7]=17 cells (5 PI)
8208 09:58:50.227707 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8209 09:58:50.231266 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8210 09:58:50.234468 == TX Byte 1 ==
8211 09:58:50.237830 u2DelayCellOfst[8]=0 cells (0 PI)
8212 09:58:50.237912 u2DelayCellOfst[9]=0 cells (0 PI)
8213 09:58:50.241433 u2DelayCellOfst[10]=7 cells (2 PI)
8214 09:58:50.244408 u2DelayCellOfst[11]=3 cells (1 PI)
8215 09:58:50.248192 u2DelayCellOfst[12]=14 cells (4 PI)
8216 09:58:50.250963 u2DelayCellOfst[13]=10 cells (3 PI)
8217 09:58:50.254570 u2DelayCellOfst[14]=14 cells (4 PI)
8218 09:58:50.258075 u2DelayCellOfst[15]=10 cells (3 PI)
8219 09:58:50.261445 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8220 09:58:50.267819 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8221 09:58:50.267905 DramC Write-DBI on
8222 09:58:50.267977 ==
8223 09:58:50.271305 Dram Type= 6, Freq= 0, CH_0, rank 1
8224 09:58:50.277978 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8225 09:58:50.278062 ==
8226 09:58:50.278127
8227 09:58:50.278187
8228 09:58:50.278245 TX Vref Scan disable
8229 09:58:50.281721 == TX Byte 0 ==
8230 09:58:50.285161 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8231 09:58:50.288018 == TX Byte 1 ==
8232 09:58:50.291395 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8233 09:58:50.295245 DramC Write-DBI off
8234 09:58:50.295330
8235 09:58:50.295414 [DATLAT]
8236 09:58:50.295504 Freq=1600, CH0 RK1
8237 09:58:50.295600
8238 09:58:50.297989 DATLAT Default: 0xf
8239 09:58:50.298091 0, 0xFFFF, sum = 0
8240 09:58:50.301717 1, 0xFFFF, sum = 0
8241 09:58:50.301827 2, 0xFFFF, sum = 0
8242 09:58:50.304758 3, 0xFFFF, sum = 0
8243 09:58:50.308458 4, 0xFFFF, sum = 0
8244 09:58:50.308622 5, 0xFFFF, sum = 0
8245 09:58:50.311766 6, 0xFFFF, sum = 0
8246 09:58:50.311877 7, 0xFFFF, sum = 0
8247 09:58:50.315344 8, 0xFFFF, sum = 0
8248 09:58:50.315428 9, 0xFFFF, sum = 0
8249 09:58:50.318543 10, 0xFFFF, sum = 0
8250 09:58:50.318653 11, 0xFFFF, sum = 0
8251 09:58:50.321508 12, 0xFFFF, sum = 0
8252 09:58:50.321591 13, 0xFFFF, sum = 0
8253 09:58:50.325138 14, 0x0, sum = 1
8254 09:58:50.325222 15, 0x0, sum = 2
8255 09:58:50.328417 16, 0x0, sum = 3
8256 09:58:50.328501 17, 0x0, sum = 4
8257 09:58:50.328567 best_step = 15
8258 09:58:50.332020
8259 09:58:50.332101 ==
8260 09:58:50.335122 Dram Type= 6, Freq= 0, CH_0, rank 1
8261 09:58:50.338765 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8262 09:58:50.338912 ==
8263 09:58:50.338981 RX Vref Scan: 0
8264 09:58:50.339042
8265 09:58:50.341724 RX Vref 0 -> 0, step: 1
8266 09:58:50.341832
8267 09:58:50.345484 RX Delay 11 -> 252, step: 4
8268 09:58:50.348304 iDelay=195, Bit 0, Center 126 (71 ~ 182) 112
8269 09:58:50.355179 iDelay=195, Bit 1, Center 130 (75 ~ 186) 112
8270 09:58:50.358125 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8271 09:58:50.361813 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8272 09:58:50.364903 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8273 09:58:50.368294 iDelay=195, Bit 5, Center 116 (63 ~ 170) 108
8274 09:58:50.372145 iDelay=195, Bit 6, Center 136 (79 ~ 194) 116
8275 09:58:50.378372 iDelay=195, Bit 7, Center 136 (83 ~ 190) 108
8276 09:58:50.381541 iDelay=195, Bit 8, Center 112 (59 ~ 166) 108
8277 09:58:50.384946 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8278 09:58:50.388323 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8279 09:58:50.391621 iDelay=195, Bit 11, Center 116 (63 ~ 170) 108
8280 09:58:50.398323 iDelay=195, Bit 12, Center 126 (75 ~ 178) 104
8281 09:58:50.401904 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
8282 09:58:50.405452 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8283 09:58:50.408449 iDelay=195, Bit 15, Center 132 (75 ~ 190) 116
8284 09:58:50.408556 ==
8285 09:58:50.412028 Dram Type= 6, Freq= 0, CH_0, rank 1
8286 09:58:50.418578 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8287 09:58:50.418679 ==
8288 09:58:50.418773 DQS Delay:
8289 09:58:50.421978 DQS0 = 0, DQS1 = 0
8290 09:58:50.422053 DQM Delay:
8291 09:58:50.422115 DQM0 = 127, DQM1 = 122
8292 09:58:50.425117 DQ Delay:
8293 09:58:50.428549 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8294 09:58:50.431776 DQ4 =128, DQ5 =116, DQ6 =136, DQ7 =136
8295 09:58:50.435172 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8296 09:58:50.438517 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =132
8297 09:58:50.438616
8298 09:58:50.438717
8299 09:58:50.438807
8300 09:58:50.442003 [DramC_TX_OE_Calibration] TA2
8301 09:58:50.445061 Original DQ_B0 (3 6) =30, OEN = 27
8302 09:58:50.448606 Original DQ_B1 (3 6) =30, OEN = 27
8303 09:58:50.452090 24, 0x0, End_B0=24 End_B1=24
8304 09:58:50.452192 25, 0x0, End_B0=25 End_B1=25
8305 09:58:50.455203 26, 0x0, End_B0=26 End_B1=26
8306 09:58:50.458823 27, 0x0, End_B0=27 End_B1=27
8307 09:58:50.461875 28, 0x0, End_B0=28 End_B1=28
8308 09:58:50.461975 29, 0x0, End_B0=29 End_B1=29
8309 09:58:50.465533 30, 0x0, End_B0=30 End_B1=30
8310 09:58:50.468555 31, 0x4141, End_B0=30 End_B1=30
8311 09:58:50.472239 Byte0 end_step=30 best_step=27
8312 09:58:50.475297 Byte1 end_step=30 best_step=27
8313 09:58:50.478758 Byte0 TX OE(2T, 0.5T) = (3, 3)
8314 09:58:50.478856 Byte1 TX OE(2T, 0.5T) = (3, 3)
8315 09:58:50.478966
8316 09:58:50.479053
8317 09:58:50.488883 [DQSOSCAuto] RK1, (LSB)MR18= 0x190f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8318 09:58:50.492149 CH0 RK1: MR19=303, MR18=190F
8319 09:58:50.495585 CH0_RK1: MR19=0x303, MR18=0x190F, DQSOSC=397, MR23=63, INC=23, DEC=15
8320 09:58:50.499118 [RxdqsGatingPostProcess] freq 1600
8321 09:58:50.505923 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8322 09:58:50.509068 best DQS0 dly(2T, 0.5T) = (1, 1)
8323 09:58:50.512652 best DQS1 dly(2T, 0.5T) = (1, 1)
8324 09:58:50.516134 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8325 09:58:50.519098 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8326 09:58:50.522723 best DQS0 dly(2T, 0.5T) = (1, 1)
8327 09:58:50.522829 best DQS1 dly(2T, 0.5T) = (1, 1)
8328 09:58:50.525802 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8329 09:58:50.529474 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8330 09:58:50.532714 Pre-setting of DQS Precalculation
8331 09:58:50.539211 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8332 09:58:50.539295 ==
8333 09:58:50.542342 Dram Type= 6, Freq= 0, CH_1, rank 0
8334 09:58:50.545965 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8335 09:58:50.546048 ==
8336 09:58:50.552340 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8337 09:58:50.555593 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8338 09:58:50.558943 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8339 09:58:50.565604 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8340 09:58:50.574823 [CA 0] Center 43 (14~72) winsize 59
8341 09:58:50.578289 [CA 1] Center 43 (14~72) winsize 59
8342 09:58:50.581221 [CA 2] Center 38 (10~67) winsize 58
8343 09:58:50.584896 [CA 3] Center 37 (8~66) winsize 59
8344 09:58:50.587959 [CA 4] Center 38 (8~68) winsize 61
8345 09:58:50.591447 [CA 5] Center 37 (8~66) winsize 59
8346 09:58:50.591529
8347 09:58:50.594966 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8348 09:58:50.595040
8349 09:58:50.598548 [CATrainingPosCal] consider 1 rank data
8350 09:58:50.601432 u2DelayCellTimex100 = 275/100 ps
8351 09:58:50.604873 CA0 delay=43 (14~72),Diff = 6 PI (21 cell)
8352 09:58:50.611377 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8353 09:58:50.614824 CA2 delay=38 (10~67),Diff = 1 PI (3 cell)
8354 09:58:50.618194 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8355 09:58:50.621359 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8356 09:58:50.625193 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8357 09:58:50.625276
8358 09:58:50.628287 CA PerBit enable=1, Macro0, CA PI delay=37
8359 09:58:50.628370
8360 09:58:50.631595 [CBTSetCACLKResult] CA Dly = 37
8361 09:58:50.631677 CS Dly: 9 (0~40)
8362 09:58:50.638290 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8363 09:58:50.641910 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8364 09:58:50.641992 ==
8365 09:58:50.644973 Dram Type= 6, Freq= 0, CH_1, rank 1
8366 09:58:50.648439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8367 09:58:50.648521 ==
8368 09:58:50.654871 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8369 09:58:50.658191 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8370 09:58:50.664811 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8371 09:58:50.668442 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8372 09:58:50.677935 [CA 0] Center 43 (14~72) winsize 59
8373 09:58:50.681626 [CA 1] Center 43 (14~72) winsize 59
8374 09:58:50.684764 [CA 2] Center 37 (8~67) winsize 60
8375 09:58:50.687724 [CA 3] Center 36 (7~66) winsize 60
8376 09:58:50.691252 [CA 4] Center 38 (9~67) winsize 59
8377 09:58:50.694841 [CA 5] Center 36 (7~66) winsize 60
8378 09:58:50.694992
8379 09:58:50.697962 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8380 09:58:50.698043
8381 09:58:50.701448 [CATrainingPosCal] consider 2 rank data
8382 09:58:50.704459 u2DelayCellTimex100 = 275/100 ps
8383 09:58:50.708040 CA0 delay=43 (14~72),Diff = 6 PI (21 cell)
8384 09:58:50.714405 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8385 09:58:50.717831 CA2 delay=38 (10~67),Diff = 1 PI (3 cell)
8386 09:58:50.721565 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8387 09:58:50.724618 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8388 09:58:50.727684 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8389 09:58:50.727766
8390 09:58:50.731424 CA PerBit enable=1, Macro0, CA PI delay=37
8391 09:58:50.731505
8392 09:58:50.734679 [CBTSetCACLKResult] CA Dly = 37
8393 09:58:50.737964 CS Dly: 11 (0~45)
8394 09:58:50.741333 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8395 09:58:50.744756 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8396 09:58:50.744837
8397 09:58:50.747722 ----->DramcWriteLeveling(PI) begin...
8398 09:58:50.747806 ==
8399 09:58:50.751133 Dram Type= 6, Freq= 0, CH_1, rank 0
8400 09:58:50.754767 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8401 09:58:50.757950 ==
8402 09:58:50.758032 Write leveling (Byte 0): 26 => 26
8403 09:58:50.761467 Write leveling (Byte 1): 27 => 27
8404 09:58:50.764308 DramcWriteLeveling(PI) end<-----
8405 09:58:50.764389
8406 09:58:50.764453 ==
8407 09:58:50.767628 Dram Type= 6, Freq= 0, CH_1, rank 0
8408 09:58:50.774722 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8409 09:58:50.774805 ==
8410 09:58:50.774892 [Gating] SW mode calibration
8411 09:58:50.784870 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8412 09:58:50.788041 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8413 09:58:50.791718 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8414 09:58:50.798276 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8415 09:58:50.801538 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8416 09:58:50.804994 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8417 09:58:50.811518 1 4 16 | B1->B0 | 2f2f 2626 | 1 0 | (1 1) (0 0)
8418 09:58:50.814913 1 4 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8419 09:58:50.818275 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8420 09:58:50.824945 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8421 09:58:50.828496 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8422 09:58:50.831416 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8423 09:58:50.838164 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8424 09:58:50.841245 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8425 09:58:50.844715 1 5 16 | B1->B0 | 2929 2e2e | 0 0 | (0 1) (0 1)
8426 09:58:50.851508 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8427 09:58:50.854785 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8428 09:58:50.858466 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8429 09:58:50.861564 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8430 09:58:50.868358 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8431 09:58:50.871741 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8432 09:58:50.874606 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8433 09:58:50.881367 1 6 16 | B1->B0 | 3535 2828 | 0 0 | (0 0) (0 0)
8434 09:58:50.884906 1 6 20 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8435 09:58:50.888168 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8436 09:58:50.895200 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8437 09:58:50.898677 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 09:58:50.901880 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8439 09:58:50.908266 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8440 09:58:50.911909 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8441 09:58:50.914812 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8442 09:58:50.921784 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 09:58:50.925348 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 09:58:50.928155 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 09:58:50.931868 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 09:58:50.938547 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 09:58:50.942295 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 09:58:50.945042 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 09:58:50.951758 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 09:58:50.955002 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 09:58:50.958652 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 09:58:50.965281 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 09:58:50.968410 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 09:58:50.971923 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 09:58:50.978518 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 09:58:50.981783 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8457 09:58:50.984902 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8458 09:58:50.991977 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8459 09:58:50.992060 Total UI for P1: 0, mck2ui 16
8460 09:58:50.998367 best dqsien dly found for B0: ( 1, 9, 14)
8461 09:58:50.998449 Total UI for P1: 0, mck2ui 16
8462 09:58:51.001875 best dqsien dly found for B1: ( 1, 9, 14)
8463 09:58:51.008664 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8464 09:58:51.011882 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8465 09:58:51.011959
8466 09:58:51.014996 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8467 09:58:51.018563 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8468 09:58:51.021761 [Gating] SW calibration Done
8469 09:58:51.021844 ==
8470 09:58:51.025143 Dram Type= 6, Freq= 0, CH_1, rank 0
8471 09:58:51.028575 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8472 09:58:51.028661 ==
8473 09:58:51.031844 RX Vref Scan: 0
8474 09:58:51.031920
8475 09:58:51.031991 RX Vref 0 -> 0, step: 1
8476 09:58:51.032051
8477 09:58:51.034962 RX Delay 0 -> 252, step: 8
8478 09:58:51.038545 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8479 09:58:51.041809 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8480 09:58:51.048903 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8481 09:58:51.052506 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8482 09:58:51.055545 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8483 09:58:51.059004 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8484 09:58:51.061962 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8485 09:58:51.068838 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8486 09:58:51.071859 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8487 09:58:51.075571 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8488 09:58:51.078430 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8489 09:58:51.082162 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8490 09:58:51.088312 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8491 09:58:51.091759 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8492 09:58:51.094829 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8493 09:58:51.098521 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8494 09:58:51.098615 ==
8495 09:58:51.101541 Dram Type= 6, Freq= 0, CH_1, rank 0
8496 09:58:51.108712 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8497 09:58:51.108795 ==
8498 09:58:51.108861 DQS Delay:
8499 09:58:51.108921 DQS0 = 0, DQS1 = 0
8500 09:58:51.111519 DQM Delay:
8501 09:58:51.111601 DQM0 = 134, DQM1 = 126
8502 09:58:51.115203 DQ Delay:
8503 09:58:51.118162 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8504 09:58:51.121874 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =131
8505 09:58:51.124824 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8506 09:58:51.128360 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8507 09:58:51.128447
8508 09:58:51.128511
8509 09:58:51.128590 ==
8510 09:58:51.131951 Dram Type= 6, Freq= 0, CH_1, rank 0
8511 09:58:51.134857 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8512 09:58:51.138272 ==
8513 09:58:51.138356
8514 09:58:51.138419
8515 09:58:51.138477 TX Vref Scan disable
8516 09:58:51.141485 == TX Byte 0 ==
8517 09:58:51.145037 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8518 09:58:51.148123 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8519 09:58:51.151696 == TX Byte 1 ==
8520 09:58:51.155133 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8521 09:58:51.158236 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8522 09:58:51.158319 ==
8523 09:58:51.161747 Dram Type= 6, Freq= 0, CH_1, rank 0
8524 09:58:51.168221 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8525 09:58:51.168304 ==
8526 09:58:51.179980
8527 09:58:51.183701 TX Vref early break, caculate TX vref
8528 09:58:51.186679 TX Vref=16, minBit 5, minWin=21, winSum=359
8529 09:58:51.190093 TX Vref=18, minBit 8, minWin=21, winSum=370
8530 09:58:51.193701 TX Vref=20, minBit 0, minWin=23, winSum=386
8531 09:58:51.196885 TX Vref=22, minBit 8, minWin=23, winSum=394
8532 09:58:51.199990 TX Vref=24, minBit 8, minWin=23, winSum=398
8533 09:58:51.206679 TX Vref=26, minBit 0, minWin=24, winSum=412
8534 09:58:51.210221 TX Vref=28, minBit 0, minWin=26, winSum=423
8535 09:58:51.213281 TX Vref=30, minBit 8, minWin=24, winSum=415
8536 09:58:51.216946 TX Vref=32, minBit 0, minWin=25, winSum=410
8537 09:58:51.219925 TX Vref=34, minBit 11, minWin=23, winSum=398
8538 09:58:51.226789 [TxChooseVref] Worse bit 0, Min win 26, Win sum 423, Final Vref 28
8539 09:58:51.226933
8540 09:58:51.230287 Final TX Range 0 Vref 28
8541 09:58:51.230370
8542 09:58:51.230436 ==
8543 09:58:51.233255 Dram Type= 6, Freq= 0, CH_1, rank 0
8544 09:58:51.236795 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8545 09:58:51.236905 ==
8546 09:58:51.237019
8547 09:58:51.237080
8548 09:58:51.240119 TX Vref Scan disable
8549 09:58:51.247020 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8550 09:58:51.247105 == TX Byte 0 ==
8551 09:58:51.250236 u2DelayCellOfst[0]=17 cells (5 PI)
8552 09:58:51.253802 u2DelayCellOfst[1]=14 cells (4 PI)
8553 09:58:51.256674 u2DelayCellOfst[2]=0 cells (0 PI)
8554 09:58:51.260220 u2DelayCellOfst[3]=7 cells (2 PI)
8555 09:58:51.263814 u2DelayCellOfst[4]=7 cells (2 PI)
8556 09:58:51.266843 u2DelayCellOfst[5]=21 cells (6 PI)
8557 09:58:51.266946 u2DelayCellOfst[6]=17 cells (5 PI)
8558 09:58:51.270341 u2DelayCellOfst[7]=7 cells (2 PI)
8559 09:58:51.276964 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8560 09:58:51.280471 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8561 09:58:51.280554 == TX Byte 1 ==
8562 09:58:51.283411 u2DelayCellOfst[8]=0 cells (0 PI)
8563 09:58:51.286999 u2DelayCellOfst[9]=7 cells (2 PI)
8564 09:58:51.290238 u2DelayCellOfst[10]=10 cells (3 PI)
8565 09:58:51.293621 u2DelayCellOfst[11]=7 cells (2 PI)
8566 09:58:51.296573 u2DelayCellOfst[12]=14 cells (4 PI)
8567 09:58:51.300140 u2DelayCellOfst[13]=17 cells (5 PI)
8568 09:58:51.303787 u2DelayCellOfst[14]=17 cells (5 PI)
8569 09:58:51.306642 u2DelayCellOfst[15]=17 cells (5 PI)
8570 09:58:51.310283 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8571 09:58:51.313296 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8572 09:58:51.316901 DramC Write-DBI on
8573 09:58:51.316983 ==
8574 09:58:51.320069 Dram Type= 6, Freq= 0, CH_1, rank 0
8575 09:58:51.323355 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8576 09:58:51.323441 ==
8577 09:58:51.323507
8578 09:58:51.323568
8579 09:58:51.326599 TX Vref Scan disable
8580 09:58:51.330254 == TX Byte 0 ==
8581 09:58:51.333243 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8582 09:58:51.336773 == TX Byte 1 ==
8583 09:58:51.339809 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8584 09:58:51.339892 DramC Write-DBI off
8585 09:58:51.339957
8586 09:58:51.343576 [DATLAT]
8587 09:58:51.343657 Freq=1600, CH1 RK0
8588 09:58:51.343723
8589 09:58:51.346521 DATLAT Default: 0xf
8590 09:58:51.346630 0, 0xFFFF, sum = 0
8591 09:58:51.350097 1, 0xFFFF, sum = 0
8592 09:58:51.350194 2, 0xFFFF, sum = 0
8593 09:58:51.353136 3, 0xFFFF, sum = 0
8594 09:58:51.353220 4, 0xFFFF, sum = 0
8595 09:58:51.356774 5, 0xFFFF, sum = 0
8596 09:58:51.356881 6, 0xFFFF, sum = 0
8597 09:58:51.359907 7, 0xFFFF, sum = 0
8598 09:58:51.359991 8, 0xFFFF, sum = 0
8599 09:58:51.363384 9, 0xFFFF, sum = 0
8600 09:58:51.363467 10, 0xFFFF, sum = 0
8601 09:58:51.366521 11, 0xFFFF, sum = 0
8602 09:58:51.370470 12, 0xFFFF, sum = 0
8603 09:58:51.370581 13, 0xFFFF, sum = 0
8604 09:58:51.373329 14, 0x0, sum = 1
8605 09:58:51.373408 15, 0x0, sum = 2
8606 09:58:51.373476 16, 0x0, sum = 3
8607 09:58:51.377074 17, 0x0, sum = 4
8608 09:58:51.377158 best_step = 15
8609 09:58:51.377222
8610 09:58:51.377286 ==
8611 09:58:51.379949 Dram Type= 6, Freq= 0, CH_1, rank 0
8612 09:58:51.386950 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8613 09:58:51.387061 ==
8614 09:58:51.387154 RX Vref Scan: 1
8615 09:58:51.387243
8616 09:58:51.390057 Set Vref Range= 24 -> 127
8617 09:58:51.390139
8618 09:58:51.393554 RX Vref 24 -> 127, step: 1
8619 09:58:51.393637
8620 09:58:51.397002 RX Delay 11 -> 252, step: 4
8621 09:58:51.397084
8622 09:58:51.397149 Set Vref, RX VrefLevel [Byte0]: 24
8623 09:58:51.399942 [Byte1]: 24
8624 09:58:51.404524
8625 09:58:51.404606 Set Vref, RX VrefLevel [Byte0]: 25
8626 09:58:51.407716 [Byte1]: 25
8627 09:58:51.412408
8628 09:58:51.412490 Set Vref, RX VrefLevel [Byte0]: 26
8629 09:58:51.415411 [Byte1]: 26
8630 09:58:51.419575
8631 09:58:51.419657 Set Vref, RX VrefLevel [Byte0]: 27
8632 09:58:51.423164 [Byte1]: 27
8633 09:58:51.427518
8634 09:58:51.427600 Set Vref, RX VrefLevel [Byte0]: 28
8635 09:58:51.430459 [Byte1]: 28
8636 09:58:51.435213
8637 09:58:51.435294 Set Vref, RX VrefLevel [Byte0]: 29
8638 09:58:51.438304 [Byte1]: 29
8639 09:58:51.442547
8640 09:58:51.442628 Set Vref, RX VrefLevel [Byte0]: 30
8641 09:58:51.446059 [Byte1]: 30
8642 09:58:51.450307
8643 09:58:51.450415 Set Vref, RX VrefLevel [Byte0]: 31
8644 09:58:51.453809 [Byte1]: 31
8645 09:58:51.457889
8646 09:58:51.457971 Set Vref, RX VrefLevel [Byte0]: 32
8647 09:58:51.461228 [Byte1]: 32
8648 09:58:51.465553
8649 09:58:51.465636 Set Vref, RX VrefLevel [Byte0]: 33
8650 09:58:51.468544 [Byte1]: 33
8651 09:58:51.473094
8652 09:58:51.473176 Set Vref, RX VrefLevel [Byte0]: 34
8653 09:58:51.479331 [Byte1]: 34
8654 09:58:51.479413
8655 09:58:51.482854 Set Vref, RX VrefLevel [Byte0]: 35
8656 09:58:51.486042 [Byte1]: 35
8657 09:58:51.486125
8658 09:58:51.489780 Set Vref, RX VrefLevel [Byte0]: 36
8659 09:58:51.493127 [Byte1]: 36
8660 09:58:51.493241
8661 09:58:51.496303 Set Vref, RX VrefLevel [Byte0]: 37
8662 09:58:51.499719 [Byte1]: 37
8663 09:58:51.503304
8664 09:58:51.503386 Set Vref, RX VrefLevel [Byte0]: 38
8665 09:58:51.506791 [Byte1]: 38
8666 09:58:51.510834
8667 09:58:51.510971 Set Vref, RX VrefLevel [Byte0]: 39
8668 09:58:51.514432 [Byte1]: 39
8669 09:58:51.518676
8670 09:58:51.518757 Set Vref, RX VrefLevel [Byte0]: 40
8671 09:58:51.522200 [Byte1]: 40
8672 09:58:51.526720
8673 09:58:51.526804 Set Vref, RX VrefLevel [Byte0]: 41
8674 09:58:51.529816 [Byte1]: 41
8675 09:58:51.533926
8676 09:58:51.534009 Set Vref, RX VrefLevel [Byte0]: 42
8677 09:58:51.537647 [Byte1]: 42
8678 09:58:51.541664
8679 09:58:51.541741 Set Vref, RX VrefLevel [Byte0]: 43
8680 09:58:51.544753 [Byte1]: 43
8681 09:58:51.549116
8682 09:58:51.549192 Set Vref, RX VrefLevel [Byte0]: 44
8683 09:58:51.552340 [Byte1]: 44
8684 09:58:51.556928
8685 09:58:51.557009 Set Vref, RX VrefLevel [Byte0]: 45
8686 09:58:51.559859 [Byte1]: 45
8687 09:58:51.564563
8688 09:58:51.564645 Set Vref, RX VrefLevel [Byte0]: 46
8689 09:58:51.567770 [Byte1]: 46
8690 09:58:51.572015
8691 09:58:51.572096 Set Vref, RX VrefLevel [Byte0]: 47
8692 09:58:51.578534 [Byte1]: 47
8693 09:58:51.578616
8694 09:58:51.582138 Set Vref, RX VrefLevel [Byte0]: 48
8695 09:58:51.585435 [Byte1]: 48
8696 09:58:51.585525
8697 09:58:51.588160 Set Vref, RX VrefLevel [Byte0]: 49
8698 09:58:51.591512 [Byte1]: 49
8699 09:58:51.591594
8700 09:58:51.594815 Set Vref, RX VrefLevel [Byte0]: 50
8701 09:58:51.598439 [Byte1]: 50
8702 09:58:51.602593
8703 09:58:51.602675 Set Vref, RX VrefLevel [Byte0]: 51
8704 09:58:51.605581 [Byte1]: 51
8705 09:58:51.610373
8706 09:58:51.610455 Set Vref, RX VrefLevel [Byte0]: 52
8707 09:58:51.613283 [Byte1]: 52
8708 09:58:51.617790
8709 09:58:51.617873 Set Vref, RX VrefLevel [Byte0]: 53
8710 09:58:51.621079 [Byte1]: 53
8711 09:58:51.625418
8712 09:58:51.625500 Set Vref, RX VrefLevel [Byte0]: 54
8713 09:58:51.629029 [Byte1]: 54
8714 09:58:51.633386
8715 09:58:51.633467 Set Vref, RX VrefLevel [Byte0]: 55
8716 09:58:51.636277 [Byte1]: 55
8717 09:58:51.640473
8718 09:58:51.640555 Set Vref, RX VrefLevel [Byte0]: 56
8719 09:58:51.644113 [Byte1]: 56
8720 09:58:51.648341
8721 09:58:51.648444 Set Vref, RX VrefLevel [Byte0]: 57
8722 09:58:51.651483 [Byte1]: 57
8723 09:58:51.655573
8724 09:58:51.655659 Set Vref, RX VrefLevel [Byte0]: 58
8725 09:58:51.659303 [Byte1]: 58
8726 09:58:51.663097
8727 09:58:51.663180 Set Vref, RX VrefLevel [Byte0]: 59
8728 09:58:51.666544 [Byte1]: 59
8729 09:58:51.670972
8730 09:58:51.671055 Set Vref, RX VrefLevel [Byte0]: 60
8731 09:58:51.674474 [Byte1]: 60
8732 09:58:51.678809
8733 09:58:51.678945 Set Vref, RX VrefLevel [Byte0]: 61
8734 09:58:51.682140 [Byte1]: 61
8735 09:58:51.686124
8736 09:58:51.686206 Set Vref, RX VrefLevel [Byte0]: 62
8737 09:58:51.689211 [Byte1]: 62
8738 09:58:51.694034
8739 09:58:51.694116 Set Vref, RX VrefLevel [Byte0]: 63
8740 09:58:51.697147 [Byte1]: 63
8741 09:58:51.701207
8742 09:58:51.701289 Set Vref, RX VrefLevel [Byte0]: 64
8743 09:58:51.704907 [Byte1]: 64
8744 09:58:51.709252
8745 09:58:51.709379 Set Vref, RX VrefLevel [Byte0]: 65
8746 09:58:51.712215 [Byte1]: 65
8747 09:58:51.716939
8748 09:58:51.717016 Set Vref, RX VrefLevel [Byte0]: 66
8749 09:58:51.719782 [Byte1]: 66
8750 09:58:51.724520
8751 09:58:51.724603 Set Vref, RX VrefLevel [Byte0]: 67
8752 09:58:51.727678 [Byte1]: 67
8753 09:58:51.731980
8754 09:58:51.732056 Set Vref, RX VrefLevel [Byte0]: 68
8755 09:58:51.736160 [Byte1]: 68
8756 09:58:51.739741
8757 09:58:51.739826 Set Vref, RX VrefLevel [Byte0]: 69
8758 09:58:51.742857 [Byte1]: 69
8759 09:58:51.747419
8760 09:58:51.747502 Set Vref, RX VrefLevel [Byte0]: 70
8761 09:58:51.750353 [Byte1]: 70
8762 09:58:51.754662
8763 09:58:51.754769 Set Vref, RX VrefLevel [Byte0]: 71
8764 09:58:51.757826 [Byte1]: 71
8765 09:58:51.762058
8766 09:58:51.762143 Set Vref, RX VrefLevel [Byte0]: 72
8767 09:58:51.765639 [Byte1]: 72
8768 09:58:51.770303
8769 09:58:51.770380 Set Vref, RX VrefLevel [Byte0]: 73
8770 09:58:51.773393 [Byte1]: 73
8771 09:58:51.777572
8772 09:58:51.777689 Set Vref, RX VrefLevel [Byte0]: 74
8773 09:58:51.780722 [Byte1]: 74
8774 09:58:51.784974
8775 09:58:51.785054 Set Vref, RX VrefLevel [Byte0]: 75
8776 09:58:51.788787 [Byte1]: 75
8777 09:58:51.792640
8778 09:58:51.792719 Set Vref, RX VrefLevel [Byte0]: 76
8779 09:58:51.795823 [Byte1]: 76
8780 09:58:51.800639
8781 09:58:51.800751 Set Vref, RX VrefLevel [Byte0]: 77
8782 09:58:51.803815 [Byte1]: 77
8783 09:58:51.808032
8784 09:58:51.808106 Final RX Vref Byte 0 = 60 to rank0
8785 09:58:51.811155 Final RX Vref Byte 1 = 54 to rank0
8786 09:58:51.814839 Final RX Vref Byte 0 = 60 to rank1
8787 09:58:51.818170 Final RX Vref Byte 1 = 54 to rank1==
8788 09:58:51.821272 Dram Type= 6, Freq= 0, CH_1, rank 0
8789 09:58:51.825123 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8790 09:58:51.827873 ==
8791 09:58:51.827951 DQS Delay:
8792 09:58:51.828015 DQS0 = 0, DQS1 = 0
8793 09:58:51.831590 DQM Delay:
8794 09:58:51.831665 DQM0 = 130, DQM1 = 124
8795 09:58:51.834496 DQ Delay:
8796 09:58:51.838086 DQ0 =134, DQ1 =126, DQ2 =120, DQ3 =128
8797 09:58:51.841452 DQ4 =130, DQ5 =142, DQ6 =140, DQ7 =126
8798 09:58:51.844648 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
8799 09:58:51.848018 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8800 09:58:51.848092
8801 09:58:51.848154
8802 09:58:51.848212
8803 09:58:51.851441 [DramC_TX_OE_Calibration] TA2
8804 09:58:51.854704 Original DQ_B0 (3 6) =30, OEN = 27
8805 09:58:51.858066 Original DQ_B1 (3 6) =30, OEN = 27
8806 09:58:51.861586 24, 0x0, End_B0=24 End_B1=24
8807 09:58:51.861670 25, 0x0, End_B0=25 End_B1=25
8808 09:58:51.864564 26, 0x0, End_B0=26 End_B1=26
8809 09:58:51.867943 27, 0x0, End_B0=27 End_B1=27
8810 09:58:51.871291 28, 0x0, End_B0=28 End_B1=28
8811 09:58:51.871374 29, 0x0, End_B0=29 End_B1=29
8812 09:58:51.874670 30, 0x0, End_B0=30 End_B1=30
8813 09:58:51.878210 31, 0x4141, End_B0=30 End_B1=30
8814 09:58:51.881351 Byte0 end_step=30 best_step=27
8815 09:58:51.884364 Byte1 end_step=30 best_step=27
8816 09:58:51.888012 Byte0 TX OE(2T, 0.5T) = (3, 3)
8817 09:58:51.888094 Byte1 TX OE(2T, 0.5T) = (3, 3)
8818 09:58:51.888159
8819 09:58:51.891603
8820 09:58:51.898218 [DQSOSCAuto] RK0, (LSB)MR18= 0x15ff, (MSB)MR19= 0x302, tDQSOscB0 = 410 ps tDQSOscB1 = 399 ps
8821 09:58:51.901263 CH1 RK0: MR19=302, MR18=15FF
8822 09:58:51.908467 CH1_RK0: MR19=0x302, MR18=0x15FF, DQSOSC=399, MR23=63, INC=23, DEC=15
8823 09:58:51.908550
8824 09:58:51.911555 ----->DramcWriteLeveling(PI) begin...
8825 09:58:51.911639 ==
8826 09:58:51.914797 Dram Type= 6, Freq= 0, CH_1, rank 1
8827 09:58:51.918406 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8828 09:58:51.918489 ==
8829 09:58:51.921646 Write leveling (Byte 0): 27 => 27
8830 09:58:51.924823 Write leveling (Byte 1): 27 => 27
8831 09:58:51.928512 DramcWriteLeveling(PI) end<-----
8832 09:58:51.928584
8833 09:58:51.928647 ==
8834 09:58:51.931623 Dram Type= 6, Freq= 0, CH_1, rank 1
8835 09:58:51.934617 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8836 09:58:51.934700 ==
8837 09:58:51.938236 [Gating] SW mode calibration
8838 09:58:51.944942 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8839 09:58:51.951660 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8840 09:58:51.954965 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8841 09:58:51.958382 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8842 09:58:51.961446 1 4 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8843 09:58:51.968278 1 4 12 | B1->B0 | 2626 3434 | 0 0 | (0 0) (0 0)
8844 09:58:51.971875 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8845 09:58:51.975186 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8846 09:58:51.981660 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8847 09:58:51.984790 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8848 09:58:51.988204 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8849 09:58:51.995069 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8850 09:58:51.998641 1 5 8 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
8851 09:58:52.001641 1 5 12 | B1->B0 | 3030 2424 | 0 0 | (0 0) (0 0)
8852 09:58:52.008100 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8853 09:58:52.011734 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8854 09:58:52.014759 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8855 09:58:52.021471 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8856 09:58:52.024962 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8857 09:58:52.028577 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8858 09:58:52.034822 1 6 8 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
8859 09:58:52.038464 1 6 12 | B1->B0 | 3d3d 4545 | 0 0 | (0 0) (0 0)
8860 09:58:52.042049 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8861 09:58:52.045018 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8862 09:58:52.052197 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8863 09:58:52.055239 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8864 09:58:52.058761 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8865 09:58:52.065596 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8866 09:58:52.068645 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8867 09:58:52.072155 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8868 09:58:52.078782 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 09:58:52.081849 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8870 09:58:52.085393 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8871 09:58:52.091946 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8872 09:58:52.095183 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8873 09:58:52.098923 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8874 09:58:52.105307 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8875 09:58:52.108357 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8876 09:58:52.111866 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8877 09:58:52.118785 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8878 09:58:52.122036 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8879 09:58:52.125480 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8880 09:58:52.132139 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8881 09:58:52.135532 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8882 09:58:52.138607 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8883 09:58:52.145299 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8884 09:58:52.145382 Total UI for P1: 0, mck2ui 16
8885 09:58:52.148306 best dqsien dly found for B0: ( 1, 9, 6)
8886 09:58:52.155054 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8887 09:58:52.158255 Total UI for P1: 0, mck2ui 16
8888 09:58:52.161918 best dqsien dly found for B1: ( 1, 9, 12)
8889 09:58:52.164876 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8890 09:58:52.168487 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8891 09:58:52.168569
8892 09:58:52.171255 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8893 09:58:52.175186 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8894 09:58:52.178480 [Gating] SW calibration Done
8895 09:58:52.178561 ==
8896 09:58:52.181357 Dram Type= 6, Freq= 0, CH_1, rank 1
8897 09:58:52.184954 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8898 09:58:52.185036 ==
8899 09:58:52.188454 RX Vref Scan: 0
8900 09:58:52.188535
8901 09:58:52.191795 RX Vref 0 -> 0, step: 1
8902 09:58:52.191876
8903 09:58:52.191940 RX Delay 0 -> 252, step: 8
8904 09:58:52.198254 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8905 09:58:52.201435 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8906 09:58:52.204964 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8907 09:58:52.208000 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8908 09:58:52.211459 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8909 09:58:52.214708 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8910 09:58:52.221576 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8911 09:58:52.224751 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8912 09:58:52.228045 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8913 09:58:52.231416 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8914 09:58:52.234802 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8915 09:58:52.241808 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8916 09:58:52.245029 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8917 09:58:52.248636 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8918 09:58:52.251740 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8919 09:58:52.258237 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8920 09:58:52.258318 ==
8921 09:58:52.261919 Dram Type= 6, Freq= 0, CH_1, rank 1
8922 09:58:52.264899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8923 09:58:52.264982 ==
8924 09:58:52.265047 DQS Delay:
8925 09:58:52.267980 DQS0 = 0, DQS1 = 0
8926 09:58:52.268087 DQM Delay:
8927 09:58:52.271743 DQM0 = 131, DQM1 = 127
8928 09:58:52.271824 DQ Delay:
8929 09:58:52.275154 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8930 09:58:52.277949 DQ4 =127, DQ5 =147, DQ6 =139, DQ7 =127
8931 09:58:52.281599 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8932 09:58:52.284850 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8933 09:58:52.284932
8934 09:58:52.284996
8935 09:58:52.285055 ==
8936 09:58:52.288442 Dram Type= 6, Freq= 0, CH_1, rank 1
8937 09:58:52.295163 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8938 09:58:52.295245 ==
8939 09:58:52.295309
8940 09:58:52.295368
8941 09:58:52.295424 TX Vref Scan disable
8942 09:58:52.298733 == TX Byte 0 ==
8943 09:58:52.301792 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8944 09:58:52.308387 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8945 09:58:52.308468 == TX Byte 1 ==
8946 09:58:52.312172 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8947 09:58:52.318646 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8948 09:58:52.318728 ==
8949 09:58:52.321671 Dram Type= 6, Freq= 0, CH_1, rank 1
8950 09:58:52.324938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8951 09:58:52.325022 ==
8952 09:58:52.338197
8953 09:58:52.341736 TX Vref early break, caculate TX vref
8954 09:58:52.345179 TX Vref=16, minBit 8, minWin=22, winSum=377
8955 09:58:52.348600 TX Vref=18, minBit 0, minWin=23, winSum=384
8956 09:58:52.351853 TX Vref=20, minBit 8, minWin=23, winSum=392
8957 09:58:52.355347 TX Vref=22, minBit 5, minWin=24, winSum=399
8958 09:58:52.358449 TX Vref=24, minBit 0, minWin=25, winSum=411
8959 09:58:52.365215 TX Vref=26, minBit 0, minWin=25, winSum=415
8960 09:58:52.368582 TX Vref=28, minBit 0, minWin=26, winSum=422
8961 09:58:52.371685 TX Vref=30, minBit 0, minWin=24, winSum=417
8962 09:58:52.375234 TX Vref=32, minBit 0, minWin=25, winSum=413
8963 09:58:52.378406 TX Vref=34, minBit 0, minWin=24, winSum=401
8964 09:58:52.381927 TX Vref=36, minBit 0, minWin=24, winSum=396
8965 09:58:52.388880 [TxChooseVref] Worse bit 0, Min win 26, Win sum 422, Final Vref 28
8966 09:58:52.388963
8967 09:58:52.392214 Final TX Range 0 Vref 28
8968 09:58:52.392296
8969 09:58:52.392360 ==
8970 09:58:52.395345 Dram Type= 6, Freq= 0, CH_1, rank 1
8971 09:58:52.398536 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8972 09:58:52.398619 ==
8973 09:58:52.398683
8974 09:58:52.398742
8975 09:58:52.402078 TX Vref Scan disable
8976 09:58:52.408638 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8977 09:58:52.408720 == TX Byte 0 ==
8978 09:58:52.412237 u2DelayCellOfst[0]=17 cells (5 PI)
8979 09:58:52.415444 u2DelayCellOfst[1]=10 cells (3 PI)
8980 09:58:52.418828 u2DelayCellOfst[2]=0 cells (0 PI)
8981 09:58:52.421760 u2DelayCellOfst[3]=7 cells (2 PI)
8982 09:58:52.425246 u2DelayCellOfst[4]=7 cells (2 PI)
8983 09:58:52.428985 u2DelayCellOfst[5]=17 cells (5 PI)
8984 09:58:52.429067 u2DelayCellOfst[6]=17 cells (5 PI)
8985 09:58:52.432034 u2DelayCellOfst[7]=7 cells (2 PI)
8986 09:58:52.438905 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8987 09:58:52.441932 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8988 09:58:52.442014 == TX Byte 1 ==
8989 09:58:52.445536 u2DelayCellOfst[8]=0 cells (0 PI)
8990 09:58:52.448401 u2DelayCellOfst[9]=7 cells (2 PI)
8991 09:58:52.452068 u2DelayCellOfst[10]=10 cells (3 PI)
8992 09:58:52.455312 u2DelayCellOfst[11]=7 cells (2 PI)
8993 09:58:52.459060 u2DelayCellOfst[12]=14 cells (4 PI)
8994 09:58:52.461898 u2DelayCellOfst[13]=14 cells (4 PI)
8995 09:58:52.465360 u2DelayCellOfst[14]=17 cells (5 PI)
8996 09:58:52.468584 u2DelayCellOfst[15]=14 cells (4 PI)
8997 09:58:52.472198 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8998 09:58:52.475670 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8999 09:58:52.478756 DramC Write-DBI on
9000 09:58:52.478837 ==
9001 09:58:52.482071 Dram Type= 6, Freq= 0, CH_1, rank 1
9002 09:58:52.485391 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9003 09:58:52.485473 ==
9004 09:58:52.485538
9005 09:58:52.485597
9006 09:58:52.489055 TX Vref Scan disable
9007 09:58:52.492080 == TX Byte 0 ==
9008 09:58:52.495297 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
9009 09:58:52.498726 == TX Byte 1 ==
9010 09:58:52.502216 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9011 09:58:52.502298 DramC Write-DBI off
9012 09:58:52.502362
9013 09:58:52.505372 [DATLAT]
9014 09:58:52.505453 Freq=1600, CH1 RK1
9015 09:58:52.505517
9016 09:58:52.508922 DATLAT Default: 0xf
9017 09:58:52.509004 0, 0xFFFF, sum = 0
9018 09:58:52.512317 1, 0xFFFF, sum = 0
9019 09:58:52.512399 2, 0xFFFF, sum = 0
9020 09:58:52.515269 3, 0xFFFF, sum = 0
9021 09:58:52.515351 4, 0xFFFF, sum = 0
9022 09:58:52.518933 5, 0xFFFF, sum = 0
9023 09:58:52.519016 6, 0xFFFF, sum = 0
9024 09:58:52.522014 7, 0xFFFF, sum = 0
9025 09:58:52.522095 8, 0xFFFF, sum = 0
9026 09:58:52.525491 9, 0xFFFF, sum = 0
9027 09:58:52.525575 10, 0xFFFF, sum = 0
9028 09:58:52.529065 11, 0xFFFF, sum = 0
9029 09:58:52.529149 12, 0xFFFF, sum = 0
9030 09:58:52.532099 13, 0xFFFF, sum = 0
9031 09:58:52.535397 14, 0x0, sum = 1
9032 09:58:52.535480 15, 0x0, sum = 2
9033 09:58:52.535544 16, 0x0, sum = 3
9034 09:58:52.538480 17, 0x0, sum = 4
9035 09:58:52.538563 best_step = 15
9036 09:58:52.538627
9037 09:58:52.542316 ==
9038 09:58:52.542427 Dram Type= 6, Freq= 0, CH_1, rank 1
9039 09:58:52.548668 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9040 09:58:52.548750 ==
9041 09:58:52.548814 RX Vref Scan: 0
9042 09:58:52.548874
9043 09:58:52.552261 RX Vref 0 -> 0, step: 1
9044 09:58:52.552342
9045 09:58:52.555232 RX Delay 11 -> 252, step: 4
9046 09:58:52.558880 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
9047 09:58:52.562674 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
9048 09:58:52.568615 iDelay=191, Bit 2, Center 118 (67 ~ 170) 104
9049 09:58:52.572155 iDelay=191, Bit 3, Center 128 (75 ~ 182) 108
9050 09:58:52.575798 iDelay=191, Bit 4, Center 130 (79 ~ 182) 104
9051 09:58:52.578793 iDelay=191, Bit 5, Center 142 (95 ~ 190) 96
9052 09:58:52.582499 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
9053 09:58:52.585698 iDelay=191, Bit 7, Center 126 (75 ~ 178) 104
9054 09:58:52.592161 iDelay=191, Bit 8, Center 112 (55 ~ 170) 116
9055 09:58:52.595595 iDelay=191, Bit 9, Center 114 (59 ~ 170) 112
9056 09:58:52.598904 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
9057 09:58:52.601890 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
9058 09:58:52.605532 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
9059 09:58:52.612243 iDelay=191, Bit 13, Center 136 (83 ~ 190) 108
9060 09:58:52.615173 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
9061 09:58:52.618620 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
9062 09:58:52.618702 ==
9063 09:58:52.622300 Dram Type= 6, Freq= 0, CH_1, rank 1
9064 09:58:52.625442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9065 09:58:52.629258 ==
9066 09:58:52.629354 DQS Delay:
9067 09:58:52.629418 DQS0 = 0, DQS1 = 0
9068 09:58:52.632078 DQM Delay:
9069 09:58:52.632162 DQM0 = 129, DQM1 = 126
9070 09:58:52.635537 DQ Delay:
9071 09:58:52.639266 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =128
9072 09:58:52.642322 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =126
9073 09:58:52.645811 DQ8 =112, DQ9 =114, DQ10 =128, DQ11 =118
9074 09:58:52.649017 DQ12 =134, DQ13 =136, DQ14 =134, DQ15 =134
9075 09:58:52.649099
9076 09:58:52.649163
9077 09:58:52.649223
9078 09:58:52.652225 [DramC_TX_OE_Calibration] TA2
9079 09:58:52.655376 Original DQ_B0 (3 6) =30, OEN = 27
9080 09:58:52.659031 Original DQ_B1 (3 6) =30, OEN = 27
9081 09:58:52.659113 24, 0x0, End_B0=24 End_B1=24
9082 09:58:52.662145 25, 0x0, End_B0=25 End_B1=25
9083 09:58:52.665734 26, 0x0, End_B0=26 End_B1=26
9084 09:58:52.668757 27, 0x0, End_B0=27 End_B1=27
9085 09:58:52.672343 28, 0x0, End_B0=28 End_B1=28
9086 09:58:52.672432 29, 0x0, End_B0=29 End_B1=29
9087 09:58:52.675634 30, 0x0, End_B0=30 End_B1=30
9088 09:58:52.679178 31, 0x4141, End_B0=30 End_B1=30
9089 09:58:52.682177 Byte0 end_step=30 best_step=27
9090 09:58:52.685303 Byte1 end_step=30 best_step=27
9091 09:58:52.685384 Byte0 TX OE(2T, 0.5T) = (3, 3)
9092 09:58:52.688915 Byte1 TX OE(2T, 0.5T) = (3, 3)
9093 09:58:52.688996
9094 09:58:52.689059
9095 09:58:52.698671 [DQSOSCAuto] RK1, (LSB)MR18= 0xe15, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
9096 09:58:52.702734 CH1 RK1: MR19=303, MR18=E15
9097 09:58:52.705525 CH1_RK1: MR19=0x303, MR18=0xE15, DQSOSC=399, MR23=63, INC=23, DEC=15
9098 09:58:52.709171 [RxdqsGatingPostProcess] freq 1600
9099 09:58:52.715733 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9100 09:58:52.719126 best DQS0 dly(2T, 0.5T) = (1, 1)
9101 09:58:52.722310 best DQS1 dly(2T, 0.5T) = (1, 1)
9102 09:58:52.725786 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9103 09:58:52.728823 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9104 09:58:52.728907 best DQS0 dly(2T, 0.5T) = (1, 1)
9105 09:58:52.732261 best DQS1 dly(2T, 0.5T) = (1, 1)
9106 09:58:52.735688 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9107 09:58:52.738869 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9108 09:58:52.742326 Pre-setting of DQS Precalculation
9109 09:58:52.749073 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9110 09:58:52.755511 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9111 09:58:52.762712 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9112 09:58:52.762798
9113 09:58:52.762868
9114 09:58:52.765848 [Calibration Summary] 3200 Mbps
9115 09:58:52.765930 CH 0, Rank 0
9116 09:58:52.769249 SW Impedance : PASS
9117 09:58:52.772284 DUTY Scan : NO K
9118 09:58:52.772367 ZQ Calibration : PASS
9119 09:58:52.776077 Jitter Meter : NO K
9120 09:58:52.779070 CBT Training : PASS
9121 09:58:52.779153 Write leveling : PASS
9122 09:58:52.782412 RX DQS gating : PASS
9123 09:58:52.782494 RX DQ/DQS(RDDQC) : PASS
9124 09:58:52.785997 TX DQ/DQS : PASS
9125 09:58:52.789487 RX DATLAT : PASS
9126 09:58:52.789569 RX DQ/DQS(Engine): PASS
9127 09:58:52.792698 TX OE : PASS
9128 09:58:52.792780 All Pass.
9129 09:58:52.792844
9130 09:58:52.795750 CH 0, Rank 1
9131 09:58:52.795832 SW Impedance : PASS
9132 09:58:52.799214 DUTY Scan : NO K
9133 09:58:52.803023 ZQ Calibration : PASS
9134 09:58:52.803105 Jitter Meter : NO K
9135 09:58:52.806291 CBT Training : PASS
9136 09:58:52.809329 Write leveling : PASS
9137 09:58:52.809411 RX DQS gating : PASS
9138 09:58:52.812923 RX DQ/DQS(RDDQC) : PASS
9139 09:58:52.813032 TX DQ/DQS : PASS
9140 09:58:52.815984 RX DATLAT : PASS
9141 09:58:52.819831 RX DQ/DQS(Engine): PASS
9142 09:58:52.819913 TX OE : PASS
9143 09:58:52.822544 All Pass.
9144 09:58:52.822626
9145 09:58:52.822721 CH 1, Rank 0
9146 09:58:52.825835 SW Impedance : PASS
9147 09:58:52.825918 DUTY Scan : NO K
9148 09:58:52.829178 ZQ Calibration : PASS
9149 09:58:52.832774 Jitter Meter : NO K
9150 09:58:52.832901 CBT Training : PASS
9151 09:58:52.836121 Write leveling : PASS
9152 09:58:52.839402 RX DQS gating : PASS
9153 09:58:52.839494 RX DQ/DQS(RDDQC) : PASS
9154 09:58:52.842719 TX DQ/DQS : PASS
9155 09:58:52.846090 RX DATLAT : PASS
9156 09:58:52.846172 RX DQ/DQS(Engine): PASS
9157 09:58:52.849825 TX OE : PASS
9158 09:58:52.849907 All Pass.
9159 09:58:52.849971
9160 09:58:52.852395 CH 1, Rank 1
9161 09:58:52.852495 SW Impedance : PASS
9162 09:58:52.856057 DUTY Scan : NO K
9163 09:58:52.859118 ZQ Calibration : PASS
9164 09:58:52.859201 Jitter Meter : NO K
9165 09:58:52.862741 CBT Training : PASS
9166 09:58:52.862850 Write leveling : PASS
9167 09:58:52.865624 RX DQS gating : PASS
9168 09:58:52.869235 RX DQ/DQS(RDDQC) : PASS
9169 09:58:52.869322 TX DQ/DQS : PASS
9170 09:58:52.872804 RX DATLAT : PASS
9171 09:58:52.876026 RX DQ/DQS(Engine): PASS
9172 09:58:52.876108 TX OE : PASS
9173 09:58:52.879112 All Pass.
9174 09:58:52.879193
9175 09:58:52.879258 DramC Write-DBI on
9176 09:58:52.882608 PER_BANK_REFRESH: Hybrid Mode
9177 09:58:52.882726 TX_TRACKING: ON
9178 09:58:52.892826 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9179 09:58:52.902825 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9180 09:58:52.909216 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9181 09:58:52.912788 [FAST_K] Save calibration result to emmc
9182 09:58:52.915824 sync common calibartion params.
9183 09:58:52.915899 sync cbt_mode0:1, 1:1
9184 09:58:52.919318 dram_init: ddr_geometry: 2
9185 09:58:52.922657 dram_init: ddr_geometry: 2
9186 09:58:52.922757 dram_init: ddr_geometry: 2
9187 09:58:52.925975 0:dram_rank_size:100000000
9188 09:58:52.929590 1:dram_rank_size:100000000
9189 09:58:52.936155 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9190 09:58:52.936247 DFS_SHUFFLE_HW_MODE: ON
9191 09:58:52.939487 dramc_set_vcore_voltage set vcore to 725000
9192 09:58:52.942377 Read voltage for 1600, 0
9193 09:58:52.942483 Vio18 = 0
9194 09:58:52.946149 Vcore = 725000
9195 09:58:52.946253 Vdram = 0
9196 09:58:52.946345 Vddq = 0
9197 09:58:52.949071 Vmddr = 0
9198 09:58:52.949170 switch to 3200 Mbps bootup
9199 09:58:52.952489 [DramcRunTimeConfig]
9200 09:58:52.952561 PHYPLL
9201 09:58:52.955610 DPM_CONTROL_AFTERK: ON
9202 09:58:52.955682 PER_BANK_REFRESH: ON
9203 09:58:52.958911 REFRESH_OVERHEAD_REDUCTION: ON
9204 09:58:52.962427 CMD_PICG_NEW_MODE: OFF
9205 09:58:52.962527 XRTWTW_NEW_MODE: ON
9206 09:58:52.965605 XRTRTR_NEW_MODE: ON
9207 09:58:52.965703 TX_TRACKING: ON
9208 09:58:52.969297 RDSEL_TRACKING: OFF
9209 09:58:52.972620 DQS Precalculation for DVFS: ON
9210 09:58:52.972722 RX_TRACKING: OFF
9211 09:58:52.975509 HW_GATING DBG: ON
9212 09:58:52.975583 ZQCS_ENABLE_LP4: ON
9213 09:58:52.979063 RX_PICG_NEW_MODE: ON
9214 09:58:52.979134 TX_PICG_NEW_MODE: ON
9215 09:58:52.982299 ENABLE_RX_DCM_DPHY: ON
9216 09:58:52.985510 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9217 09:58:52.988997 DUMMY_READ_FOR_TRACKING: OFF
9218 09:58:52.989100 !!! SPM_CONTROL_AFTERK: OFF
9219 09:58:52.992509 !!! SPM could not control APHY
9220 09:58:52.995666 IMPEDANCE_TRACKING: ON
9221 09:58:52.995755 TEMP_SENSOR: ON
9222 09:58:52.999082 HW_SAVE_FOR_SR: OFF
9223 09:58:53.002246 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9224 09:58:53.005869 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9225 09:58:53.005956 Read ODT Tracking: ON
9226 09:58:53.009268 Refresh Rate DeBounce: ON
9227 09:58:53.012746 DFS_NO_QUEUE_FLUSH: ON
9228 09:58:53.016037 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9229 09:58:53.016158 ENABLE_DFS_RUNTIME_MRW: OFF
9230 09:58:53.019095 DDR_RESERVE_NEW_MODE: ON
9231 09:58:53.022820 MR_CBT_SWITCH_FREQ: ON
9232 09:58:53.022947 =========================
9233 09:58:53.042414 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9234 09:58:53.045587 dram_init: ddr_geometry: 2
9235 09:58:53.064340 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9236 09:58:53.067715 dram_init: dram init end (result: 0)
9237 09:58:53.074301 DRAM-K: Full calibration passed in 24569 msecs
9238 09:58:53.077400 MRC: failed to locate region type 0.
9239 09:58:53.077518 DRAM rank0 size:0x100000000,
9240 09:58:53.080802 DRAM rank1 size=0x100000000
9241 09:58:53.091093 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9242 09:58:53.097681 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9243 09:58:53.104347 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9244 09:58:53.110540 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9245 09:58:53.114275 DRAM rank0 size:0x100000000,
9246 09:58:53.117199 DRAM rank1 size=0x100000000
9247 09:58:53.117313 CBMEM:
9248 09:58:53.120832 IMD: root @ 0xfffff000 254 entries.
9249 09:58:53.123799 IMD: root @ 0xffffec00 62 entries.
9250 09:58:53.127545 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9251 09:58:53.130525 WARNING: RO_VPD is uninitialized or empty.
9252 09:58:53.137181 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9253 09:58:53.144480 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9254 09:58:53.157116 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9255 09:58:53.168544 BS: romstage times (exec / console): total (unknown) / 24073 ms
9256 09:58:53.168628
9257 09:58:53.168693
9258 09:58:53.178118 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9259 09:58:53.181787 ARM64: Exception handlers installed.
9260 09:58:53.184831 ARM64: Testing exception
9261 09:58:53.188132 ARM64: Done test exception
9262 09:58:53.188213 Enumerating buses...
9263 09:58:53.191934 Show all devs... Before device enumeration.
9264 09:58:53.195109 Root Device: enabled 1
9265 09:58:53.198170 CPU_CLUSTER: 0: enabled 1
9266 09:58:53.198252 CPU: 00: enabled 1
9267 09:58:53.201938 Compare with tree...
9268 09:58:53.202020 Root Device: enabled 1
9269 09:58:53.204974 CPU_CLUSTER: 0: enabled 1
9270 09:58:53.208206 CPU: 00: enabled 1
9271 09:58:53.208288 Root Device scanning...
9272 09:58:53.211817 scan_static_bus for Root Device
9273 09:58:53.214696 CPU_CLUSTER: 0 enabled
9274 09:58:53.218532 scan_static_bus for Root Device done
9275 09:58:53.221568 scan_bus: bus Root Device finished in 8 msecs
9276 09:58:53.221681 done
9277 09:58:53.228157 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9278 09:58:53.231487 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9279 09:58:53.238047 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9280 09:58:53.241629 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9281 09:58:53.245323 Allocating resources...
9282 09:58:53.245404 Reading resources...
9283 09:58:53.251445 Root Device read_resources bus 0 link: 0
9284 09:58:53.251528 DRAM rank0 size:0x100000000,
9285 09:58:53.255023 DRAM rank1 size=0x100000000
9286 09:58:53.258071 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9287 09:58:53.261408 CPU: 00 missing read_resources
9288 09:58:53.264742 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9289 09:58:53.271854 Root Device read_resources bus 0 link: 0 done
9290 09:58:53.271937 Done reading resources.
9291 09:58:53.278630 Show resources in subtree (Root Device)...After reading.
9292 09:58:53.281674 Root Device child on link 0 CPU_CLUSTER: 0
9293 09:58:53.284705 CPU_CLUSTER: 0 child on link 0 CPU: 00
9294 09:58:53.294917 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9295 09:58:53.295026 CPU: 00
9296 09:58:53.298501 Root Device assign_resources, bus 0 link: 0
9297 09:58:53.301817 CPU_CLUSTER: 0 missing set_resources
9298 09:58:53.305169 Root Device assign_resources, bus 0 link: 0 done
9299 09:58:53.308502 Done setting resources.
9300 09:58:53.315033 Show resources in subtree (Root Device)...After assigning values.
9301 09:58:53.318443 Root Device child on link 0 CPU_CLUSTER: 0
9302 09:58:53.321888 CPU_CLUSTER: 0 child on link 0 CPU: 00
9303 09:58:53.331843 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9304 09:58:53.331935 CPU: 00
9305 09:58:53.335013 Done allocating resources.
9306 09:58:53.338555 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9307 09:58:53.342143 Enabling resources...
9308 09:58:53.342226 done.
9309 09:58:53.345429 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9310 09:58:53.348917 Initializing devices...
9311 09:58:53.348998 Root Device init
9312 09:58:53.352020 init hardware done!
9313 09:58:53.355786 0x00000018: ctrlr->caps
9314 09:58:53.355870 52.000 MHz: ctrlr->f_max
9315 09:58:53.358559 0.400 MHz: ctrlr->f_min
9316 09:58:53.362349 0x40ff8080: ctrlr->voltages
9317 09:58:53.362432 sclk: 390625
9318 09:58:53.365332 Bus Width = 1
9319 09:58:53.365413 sclk: 390625
9320 09:58:53.365477 Bus Width = 1
9321 09:58:53.369005 Early init status = 3
9322 09:58:53.371608 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9323 09:58:53.376124 in-header: 03 fb 00 00 01 00 00 00
9324 09:58:53.379076 in-data: 01
9325 09:58:53.382766 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9326 09:58:53.386451 in-header: 03 fb 00 00 01 00 00 00
9327 09:58:53.389571 in-data: 01
9328 09:58:53.393134 [SSUSB] Setting up USB HOST controller...
9329 09:58:53.396126 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9330 09:58:53.400053 [SSUSB] phy power-on done.
9331 09:58:53.403043 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9332 09:58:53.409451 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9333 09:58:53.412785 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9334 09:58:53.419443 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9335 09:58:53.426081 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9336 09:58:53.432938 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9337 09:58:53.439401 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9338 09:58:53.446051 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9339 09:58:53.449688 SPM: binary array size = 0x9dc
9340 09:58:53.452758 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9341 09:58:53.459746 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9342 09:58:53.466083 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9343 09:58:53.469328 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9344 09:58:53.475803 configure_display: Starting display init
9345 09:58:53.509977 anx7625_power_on_init: Init interface.
9346 09:58:53.513501 anx7625_disable_pd_protocol: Disabled PD feature.
9347 09:58:53.516252 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9348 09:58:53.544358 anx7625_start_dp_work: Secure OCM version=00
9349 09:58:53.547283 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9350 09:58:53.562208 sp_tx_get_edid_block: EDID Block = 1
9351 09:58:53.664918 Extracted contents:
9352 09:58:53.667984 header: 00 ff ff ff ff ff ff 00
9353 09:58:53.671469 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9354 09:58:53.674964 version: 01 04
9355 09:58:53.678277 basic params: 95 1f 11 78 0a
9356 09:58:53.681696 chroma info: 76 90 94 55 54 90 27 21 50 54
9357 09:58:53.684982 established: 00 00 00
9358 09:58:53.691594 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9359 09:58:53.694718 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9360 09:58:53.701676 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9361 09:58:53.708243 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9362 09:58:53.715451 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9363 09:58:53.718077 extensions: 00
9364 09:58:53.718159 checksum: fb
9365 09:58:53.718223
9366 09:58:53.721660 Manufacturer: IVO Model 57d Serial Number 0
9367 09:58:53.724909 Made week 0 of 2020
9368 09:58:53.724990 EDID version: 1.4
9369 09:58:53.728330 Digital display
9370 09:58:53.731418 6 bits per primary color channel
9371 09:58:53.731498 DisplayPort interface
9372 09:58:53.734986 Maximum image size: 31 cm x 17 cm
9373 09:58:53.735075 Gamma: 220%
9374 09:58:53.738192 Check DPMS levels
9375 09:58:53.741475 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9376 09:58:53.744918 First detailed timing is preferred timing
9377 09:58:53.748207 Established timings supported:
9378 09:58:53.751977 Standard timings supported:
9379 09:58:53.752058 Detailed timings
9380 09:58:53.758589 Hex of detail: 383680a07038204018303c0035ae10000019
9381 09:58:53.761339 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9382 09:58:53.764943 0780 0798 07c8 0820 hborder 0
9383 09:58:53.771739 0438 043b 0447 0458 vborder 0
9384 09:58:53.771820 -hsync -vsync
9385 09:58:53.774896 Did detailed timing
9386 09:58:53.778362 Hex of detail: 000000000000000000000000000000000000
9387 09:58:53.781241 Manufacturer-specified data, tag 0
9388 09:58:53.788007 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9389 09:58:53.788088 ASCII string: InfoVision
9390 09:58:53.795154 Hex of detail: 000000fe00523134304e574635205248200a
9391 09:58:53.795235 ASCII string: R140NWF5 RH
9392 09:58:53.798315 Checksum
9393 09:58:53.798407 Checksum: 0xfb (valid)
9394 09:58:53.805040 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9395 09:58:53.805147 DSI data_rate: 832800000 bps
9396 09:58:53.812265 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9397 09:58:53.815695 anx7625_parse_edid: pixelclock(138800).
9398 09:58:53.819364 hactive(1920), hsync(48), hfp(24), hbp(88)
9399 09:58:53.822687 vactive(1080), vsync(12), vfp(3), vbp(17)
9400 09:58:53.825849 anx7625_dsi_config: config dsi.
9401 09:58:53.832542 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9402 09:58:53.846668 anx7625_dsi_config: success to config DSI
9403 09:58:53.850555 anx7625_dp_start: MIPI phy setup OK.
9404 09:58:53.853824 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9405 09:58:53.856887 mtk_ddp_mode_set invalid vrefresh 60
9406 09:58:53.859965 main_disp_path_setup
9407 09:58:53.860049 ovl_layer_smi_id_en
9408 09:58:53.863782 ovl_layer_smi_id_en
9409 09:58:53.863865 ccorr_config
9410 09:58:53.863949 aal_config
9411 09:58:53.866645 gamma_config
9412 09:58:53.866728 postmask_config
9413 09:58:53.870620 dither_config
9414 09:58:53.873500 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9415 09:58:53.879946 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9416 09:58:53.883462 Root Device init finished in 529 msecs
9417 09:58:53.883566 CPU_CLUSTER: 0 init
9418 09:58:53.893670 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9419 09:58:53.896498 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9420 09:58:53.900170 APU_MBOX 0x190000b0 = 0x10001
9421 09:58:53.903489 APU_MBOX 0x190001b0 = 0x10001
9422 09:58:53.906491 APU_MBOX 0x190005b0 = 0x10001
9423 09:58:53.909969 APU_MBOX 0x190006b0 = 0x10001
9424 09:58:53.913529 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9425 09:58:53.926232 read SPI 0x539f4 0xe237: 6250 us, 9265 KB/s, 74.120 Mbps
9426 09:58:53.938678 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9427 09:58:53.944980 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9428 09:58:53.956689 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9429 09:58:53.965472 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9430 09:58:53.969269 CPU_CLUSTER: 0 init finished in 81 msecs
9431 09:58:53.972422 Devices initialized
9432 09:58:53.975516 Show all devs... After init.
9433 09:58:53.975598 Root Device: enabled 1
9434 09:58:53.979325 CPU_CLUSTER: 0: enabled 1
9435 09:58:53.982137 CPU: 00: enabled 1
9436 09:58:53.985812 BS: BS_DEV_INIT run times (exec / console): 206 / 428 ms
9437 09:58:53.989167 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9438 09:58:53.992258 ELOG: NV offset 0x57f000 size 0x1000
9439 09:58:53.999029 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9440 09:58:54.005527 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9441 09:58:54.009219 ELOG: Event(17) added with size 13 at 2023-11-24 09:58:55 UTC
9442 09:58:54.012479 out: cmd=0x121: 03 db 21 01 00 00 00 00
9443 09:58:54.016002 in-header: 03 f9 00 00 2c 00 00 00
9444 09:58:54.029434 in-data: 66 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9445 09:58:54.036192 ELOG: Event(A1) added with size 10 at 2023-11-24 09:58:55 UTC
9446 09:58:54.042431 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9447 09:58:54.049962 ELOG: Event(A0) added with size 9 at 2023-11-24 09:58:55 UTC
9448 09:58:54.053116 elog_add_boot_reason: Logged dev mode boot
9449 09:58:54.056151 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9450 09:58:54.059758 Finalize devices...
9451 09:58:54.059836 Devices finalized
9452 09:58:54.066128 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9453 09:58:54.069316 Writing coreboot table at 0xffe64000
9454 09:58:54.072611 0. 000000000010a000-0000000000113fff: RAMSTAGE
9455 09:58:54.075799 1. 0000000040000000-00000000400fffff: RAM
9456 09:58:54.079409 2. 0000000040100000-000000004032afff: RAMSTAGE
9457 09:58:54.086072 3. 000000004032b000-00000000545fffff: RAM
9458 09:58:54.089286 4. 0000000054600000-000000005465ffff: BL31
9459 09:58:54.092634 5. 0000000054660000-00000000ffe63fff: RAM
9460 09:58:54.096139 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9461 09:58:54.102700 7. 0000000100000000-000000023fffffff: RAM
9462 09:58:54.102810 Passing 5 GPIOs to payload:
9463 09:58:54.109583 NAME | PORT | POLARITY | VALUE
9464 09:58:54.113117 EC in RW | 0x000000aa | low | undefined
9465 09:58:54.116035 EC interrupt | 0x00000005 | low | undefined
9466 09:58:54.122813 TPM interrupt | 0x000000ab | high | undefined
9467 09:58:54.126693 SD card detect | 0x00000011 | high | undefined
9468 09:58:54.133271 speaker enable | 0x00000093 | high | undefined
9469 09:58:54.136218 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9470 09:58:54.139431 in-header: 03 f9 00 00 02 00 00 00
9471 09:58:54.139538 in-data: 02 00
9472 09:58:54.142597 ADC[4]: Raw value=900221 ID=7
9473 09:58:54.146163 ADC[3]: Raw value=213336 ID=1
9474 09:58:54.146247 RAM Code: 0x71
9475 09:58:54.149710 ADC[6]: Raw value=74557 ID=0
9476 09:58:54.152619 ADC[5]: Raw value=212229 ID=1
9477 09:58:54.152727 SKU Code: 0x1
9478 09:58:54.159303 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 5bd5
9479 09:58:54.162981 coreboot table: 964 bytes.
9480 09:58:54.166066 IMD ROOT 0. 0xfffff000 0x00001000
9481 09:58:54.169796 IMD SMALL 1. 0xffffe000 0x00001000
9482 09:58:54.184791 RO MCACHE 2. 0xffffc000 0x00001104
9483 09:58:54.184882 CONSOLE 3. 0xfff7c000 0x00080000
9484 09:58:54.184971 FMAP 4. 0xfff7b000 0x00000452
9485 09:58:54.185063 TIME STAMP 5. 0xfff7a000 0x00000910
9486 09:58:54.185868 VBOOT WORK 6. 0xfff66000 0x00014000
9487 09:58:54.189249 RAMOOPS 7. 0xffe66000 0x00100000
9488 09:58:54.193071 COREBOOT 8. 0xffe64000 0x00002000
9489 09:58:54.193152 IMD small region:
9490 09:58:54.196509 IMD ROOT 0. 0xffffec00 0x00000400
9491 09:58:54.200106 VPD 1. 0xffffeb80 0x0000006c
9492 09:58:54.203006 MMC STATUS 2. 0xffffeb60 0x00000004
9493 09:58:54.209479 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9494 09:58:54.209561 Probing TPM: done!
9495 09:58:54.217071 Connected to device vid:did:rid of 1ae0:0028:00
9496 09:58:54.223359 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9497 09:58:54.226751 Initialized TPM device CR50 revision 0
9498 09:58:54.230177 Checking cr50 for pending updates
9499 09:58:54.235313 Reading cr50 TPM mode
9500 09:58:54.244435 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9501 09:58:54.250733 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9502 09:58:54.290813 read SPI 0x3990ec 0x4f1b0: 34858 us, 9295 KB/s, 74.360 Mbps
9503 09:58:54.294320 Checking segment from ROM address 0x40100000
9504 09:58:54.297768 Checking segment from ROM address 0x4010001c
9505 09:58:54.304226 Loading segment from ROM address 0x40100000
9506 09:58:54.304310 code (compression=0)
9507 09:58:54.311528 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9508 09:58:54.321002 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9509 09:58:54.321095 it's not compressed!
9510 09:58:54.327810 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9511 09:58:54.330726 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9512 09:58:54.351058 Loading segment from ROM address 0x4010001c
9513 09:58:54.351182 Entry Point 0x80000000
9514 09:58:54.354689 Loaded segments
9515 09:58:54.358444 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9516 09:58:54.364520 Jumping to boot code at 0x80000000(0xffe64000)
9517 09:58:54.371634 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9518 09:58:54.378055 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9519 09:58:54.385514 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9520 09:58:54.389122 Checking segment from ROM address 0x40100000
9521 09:58:54.392662 Checking segment from ROM address 0x4010001c
9522 09:58:54.396129 Loading segment from ROM address 0x40100000
9523 09:58:54.399107 code (compression=1)
9524 09:58:54.405727 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9525 09:58:54.415878 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9526 09:58:54.415984 using LZMA
9527 09:58:54.424438 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9528 09:58:54.430896 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9529 09:58:54.434335 Loading segment from ROM address 0x4010001c
9530 09:58:54.434434 Entry Point 0x54601000
9531 09:58:54.437479 Loaded segments
9532 09:58:54.440765 NOTICE: MT8192 bl31_setup
9533 09:58:54.447889 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9534 09:58:54.450947 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9535 09:58:54.454240 WARNING: region 0:
9536 09:58:54.457771 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9537 09:58:54.457871 WARNING: region 1:
9538 09:58:54.464310 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9539 09:58:54.467803 WARNING: region 2:
9540 09:58:54.471128 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9541 09:58:54.474727 WARNING: region 3:
9542 09:58:54.478091 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9543 09:58:54.481082 WARNING: region 4:
9544 09:58:54.484504 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9545 09:58:54.487912 WARNING: region 5:
9546 09:58:54.491542 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9547 09:58:54.495145 WARNING: region 6:
9548 09:58:54.498002 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9549 09:58:54.498076 WARNING: region 7:
9550 09:58:54.504947 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9551 09:58:54.511430 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9552 09:58:54.514716 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9553 09:58:54.518238 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9554 09:58:54.521778 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9555 09:58:54.528467 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9556 09:58:54.531857 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9557 09:58:54.538653 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9558 09:58:54.541627 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9559 09:58:54.545235 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9560 09:58:54.552262 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9561 09:58:54.555611 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9562 09:58:54.559040 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9563 09:58:54.565611 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9564 09:58:54.569013 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9565 09:58:54.572036 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9566 09:58:54.579256 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9567 09:58:54.582275 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9568 09:58:54.585720 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9569 09:58:54.592167 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9570 09:58:54.595698 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9571 09:58:54.602279 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9572 09:58:54.605768 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9573 09:58:54.609140 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9574 09:58:54.616008 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9575 09:58:54.619350 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9576 09:58:54.622994 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9577 09:58:54.629411 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9578 09:58:54.632806 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9579 09:58:54.639788 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9580 09:58:54.643295 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9581 09:58:54.646322 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9582 09:58:54.652889 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9583 09:58:54.656376 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9584 09:58:54.660108 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9585 09:58:54.663205 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9586 09:58:54.669513 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9587 09:58:54.672872 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9588 09:58:54.676117 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9589 09:58:54.679666 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9590 09:58:54.686767 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9591 09:58:54.690240 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9592 09:58:54.693282 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9593 09:58:54.696616 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9594 09:58:54.703413 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9595 09:58:54.706780 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9596 09:58:54.710625 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9597 09:58:54.713371 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9598 09:58:54.720678 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9599 09:58:54.723757 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9600 09:58:54.726701 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9601 09:58:54.733736 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9602 09:58:54.737213 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9603 09:58:54.743799 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9604 09:58:54.747337 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9605 09:58:54.750685 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9606 09:58:54.757187 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9607 09:58:54.760794 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9608 09:58:54.767222 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9609 09:58:54.770495 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9610 09:58:54.777241 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9611 09:58:54.780740 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9612 09:58:54.783863 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9613 09:58:54.790848 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9614 09:58:54.793918 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9615 09:58:54.800857 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9616 09:58:54.804429 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9617 09:58:54.810824 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9618 09:58:54.814121 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9619 09:58:54.817416 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9620 09:58:54.824583 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9621 09:58:54.827232 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9622 09:58:54.834410 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9623 09:58:54.837610 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9624 09:58:54.840634 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9625 09:58:54.847637 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9626 09:58:54.850999 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9627 09:58:54.857743 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9628 09:58:54.861252 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9629 09:58:54.867893 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9630 09:58:54.871423 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9631 09:58:54.874855 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9632 09:58:54.881027 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9633 09:58:54.884775 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9634 09:58:54.891438 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9635 09:58:54.894423 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9636 09:58:54.901320 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9637 09:58:54.904606 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9638 09:58:54.908015 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9639 09:58:54.914557 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9640 09:58:54.918099 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9641 09:58:54.924860 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9642 09:58:54.928500 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9643 09:58:54.934527 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9644 09:58:54.938375 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9645 09:58:54.941808 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9646 09:58:54.948160 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9647 09:58:54.951826 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9648 09:58:54.955024 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9649 09:58:54.961746 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9650 09:58:54.965190 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9651 09:58:54.968477 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9652 09:58:54.971805 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9653 09:58:54.978343 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9654 09:58:54.981899 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9655 09:58:54.988581 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9656 09:58:54.991964 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9657 09:58:54.995431 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9658 09:58:55.001713 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9659 09:58:55.005517 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9660 09:58:55.012371 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9661 09:58:55.015320 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9662 09:58:55.019039 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9663 09:58:55.025669 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9664 09:58:55.029266 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9665 09:58:55.035339 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9666 09:58:55.038735 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9667 09:58:55.042317 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9668 09:58:55.045860 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9669 09:58:55.052598 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9670 09:58:55.055653 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9671 09:58:55.059176 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9672 09:58:55.062578 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9673 09:58:55.069357 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9674 09:58:55.072899 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9675 09:58:55.076161 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9676 09:58:55.082368 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9677 09:58:55.085832 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9678 09:58:55.089488 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9679 09:58:55.096017 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9680 09:58:55.099837 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9681 09:58:55.102595 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9682 09:58:55.109282 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9683 09:58:55.112742 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9684 09:58:55.119910 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9685 09:58:55.123257 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9686 09:58:55.126343 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9687 09:58:55.132801 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9688 09:58:55.136357 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9689 09:58:55.139571 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9690 09:58:55.146436 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9691 09:58:55.150058 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9692 09:58:55.156361 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9693 09:58:55.159686 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9694 09:58:55.163120 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9695 09:58:55.170016 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9696 09:58:55.173278 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9697 09:58:55.176635 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9698 09:58:55.183371 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9699 09:58:55.186599 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9700 09:58:55.193618 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9701 09:58:55.196870 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9702 09:58:55.200485 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9703 09:58:55.206787 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9704 09:58:55.209911 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9705 09:58:55.213236 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9706 09:58:55.220549 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9707 09:58:55.223787 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9708 09:58:55.230350 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9709 09:58:55.233938 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9710 09:58:55.236864 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9711 09:58:55.243564 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9712 09:58:55.246877 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9713 09:58:55.253925 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9714 09:58:55.256866 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9715 09:58:55.260416 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9716 09:58:55.267282 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9717 09:58:55.270306 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9718 09:58:55.273997 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9719 09:58:55.280630 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9720 09:58:55.284244 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9721 09:58:55.290915 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9722 09:58:55.294545 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9723 09:58:55.297207 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9724 09:58:55.304508 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9725 09:58:55.307815 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9726 09:58:55.311234 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9727 09:58:55.317954 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9728 09:58:55.321325 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9729 09:58:55.328005 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9730 09:58:55.331570 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9731 09:58:55.334124 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9732 09:58:55.341233 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9733 09:58:55.344675 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9734 09:58:55.348049 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9735 09:58:55.354168 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9736 09:58:55.357652 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9737 09:58:55.364389 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9738 09:58:55.367776 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9739 09:58:55.371285 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9740 09:58:55.378066 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9741 09:58:55.380836 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9742 09:58:55.387674 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9743 09:58:55.391008 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9744 09:58:55.397860 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9745 09:58:55.400773 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9746 09:58:55.404781 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9747 09:58:55.411168 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9748 09:58:55.414401 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9749 09:58:55.420781 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9750 09:58:55.424360 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9751 09:58:55.427378 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9752 09:58:55.434035 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9753 09:58:55.437366 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9754 09:58:55.444063 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9755 09:58:55.447865 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9756 09:58:55.451020 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9757 09:58:55.457795 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9758 09:58:55.461394 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9759 09:58:55.467671 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9760 09:58:55.471160 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9761 09:58:55.477807 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9762 09:58:55.480972 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9763 09:58:55.483967 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9764 09:58:55.490849 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9765 09:58:55.493996 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9766 09:58:55.500826 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9767 09:58:55.504271 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9768 09:58:55.507435 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9769 09:58:55.514132 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9770 09:58:55.518082 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9771 09:58:55.524246 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9772 09:58:55.528525 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9773 09:58:55.531023 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9774 09:58:55.537872 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9775 09:58:55.541283 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9776 09:58:55.548119 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9777 09:58:55.550922 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9778 09:58:55.554480 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9779 09:58:55.561000 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9780 09:58:55.564501 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9781 09:58:55.567886 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9782 09:58:55.571377 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9783 09:58:55.577966 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9784 09:58:55.581116 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9785 09:58:55.584402 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9786 09:58:55.591114 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9787 09:58:55.594512 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9788 09:58:55.598045 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9789 09:58:55.605250 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9790 09:58:55.607901 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9791 09:58:55.611370 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9792 09:58:55.618018 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9793 09:58:55.621648 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9794 09:58:55.624724 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9795 09:58:55.631541 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9796 09:58:55.634584 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9797 09:58:55.641498 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9798 09:58:55.645173 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9799 09:58:55.648738 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9800 09:58:55.654777 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9801 09:58:55.658189 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9802 09:58:55.661775 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9803 09:58:55.668027 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9804 09:58:55.671676 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9805 09:58:55.674895 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9806 09:58:55.681746 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9807 09:58:55.685201 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9808 09:58:55.691265 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9809 09:58:55.694790 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9810 09:58:55.697524 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9811 09:58:55.704998 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9812 09:58:55.707617 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9813 09:58:55.711369 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9814 09:58:55.718100 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9815 09:58:55.721783 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9816 09:58:55.724238 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9817 09:58:55.731532 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9818 09:58:55.734539 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9819 09:58:55.737898 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9820 09:58:55.744574 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9821 09:58:55.747913 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9822 09:58:55.751329 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9823 09:58:55.754812 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9824 09:58:55.758284 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9825 09:58:55.765085 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9826 09:58:55.768516 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9827 09:58:55.771672 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9828 09:58:55.774637 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9829 09:58:55.781051 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9830 09:58:55.784698 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9831 09:58:55.788269 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9832 09:58:55.791338 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9833 09:58:55.797768 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9834 09:58:55.801375 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9835 09:58:55.808500 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9836 09:58:55.811241 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9837 09:58:55.818066 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9838 09:58:55.821531 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9839 09:58:55.825163 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9840 09:58:55.831352 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9841 09:58:55.834617 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9842 09:58:55.841460 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9843 09:58:55.844532 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9844 09:58:55.847821 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9845 09:58:55.854788 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9846 09:58:55.857918 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9847 09:58:55.865261 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9848 09:58:55.867990 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9849 09:58:55.871473 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9850 09:58:55.878014 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9851 09:58:55.881645 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9852 09:58:55.887977 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9853 09:58:55.891924 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9854 09:58:55.894570 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9855 09:58:55.901644 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9856 09:58:55.904533 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9857 09:58:55.911421 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9858 09:58:55.914683 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9859 09:58:55.918064 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9860 09:58:55.925325 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9861 09:58:55.927973 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9862 09:58:55.934847 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9863 09:58:55.938358 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9864 09:58:55.942042 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9865 09:58:55.947996 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9866 09:58:55.951809 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9867 09:58:55.958342 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9868 09:58:55.961695 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9869 09:58:55.965363 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9870 09:58:55.971727 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9871 09:58:55.975216 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9872 09:58:55.978522 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9873 09:58:55.984966 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9874 09:58:55.988532 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9875 09:58:55.995140 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9876 09:58:55.998568 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9877 09:58:56.005458 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9878 09:58:56.008382 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9879 09:58:56.011907 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9880 09:58:56.018775 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9881 09:58:56.021587 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9882 09:58:56.025085 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9883 09:58:56.031899 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9884 09:58:56.035358 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9885 09:58:56.041625 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9886 09:58:56.045243 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9887 09:58:56.052129 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9888 09:58:56.055585 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9889 09:58:56.058525 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9890 09:58:56.065033 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9891 09:58:56.068432 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9892 09:58:56.075494 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9893 09:58:56.078696 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9894 09:58:56.081757 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9895 09:58:56.088460 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9896 09:58:56.092221 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9897 09:58:56.095203 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9898 09:58:56.102237 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9899 09:58:56.105138 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9900 09:58:56.112876 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9901 09:58:56.115230 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9902 09:58:56.122153 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9903 09:58:56.125448 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9904 09:58:56.128898 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9905 09:58:56.135437 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9906 09:58:56.138606 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9907 09:58:56.145476 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9908 09:58:56.149124 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9909 09:58:56.152220 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9910 09:58:56.159145 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9911 09:58:56.162616 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9912 09:58:56.169327 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9913 09:58:56.172215 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9914 09:58:56.175698 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9915 09:58:56.182750 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9916 09:58:56.185671 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9917 09:58:56.192329 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9918 09:58:56.195915 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9919 09:58:56.202391 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9920 09:58:56.205771 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9921 09:58:56.209429 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9922 09:58:56.215632 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9923 09:58:56.219032 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9924 09:58:56.225715 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9925 09:58:56.229014 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9926 09:58:56.235945 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9927 09:58:56.239136 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9928 09:58:56.242477 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9929 09:58:56.249080 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9930 09:58:56.252279 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9931 09:58:56.259383 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9932 09:58:56.262353 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9933 09:58:56.269143 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9934 09:58:56.272631 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9935 09:58:56.276014 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9936 09:58:56.282665 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9937 09:58:56.285817 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9938 09:58:56.293202 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9939 09:58:56.295883 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9940 09:58:56.302841 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9941 09:58:56.306229 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9942 09:58:56.309604 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9943 09:58:56.316046 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9944 09:58:56.319755 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9945 09:58:56.325960 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9946 09:58:56.329393 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9947 09:58:56.332766 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9948 09:58:56.339889 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9949 09:58:56.342906 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9950 09:58:56.349256 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9951 09:58:56.352624 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9952 09:58:56.359757 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9953 09:58:56.362696 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9954 09:58:56.366725 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9955 09:58:56.372925 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9956 09:58:56.376395 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9957 09:58:56.383199 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9958 09:58:56.386379 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9959 09:58:56.393022 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9960 09:58:56.396380 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9961 09:58:56.403044 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9962 09:58:56.406275 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9963 09:58:56.409689 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9964 09:58:56.416855 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9965 09:58:56.419990 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9966 09:58:56.426426 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9967 09:58:56.429765 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9968 09:58:56.436461 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9969 09:58:56.440084 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9970 09:58:56.446695 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9971 09:58:56.450119 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9972 09:58:56.456522 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9973 09:58:56.459977 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9974 09:58:56.466434 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9975 09:58:56.470058 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9976 09:58:56.476726 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9977 09:58:56.480564 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9978 09:58:56.486526 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9979 09:58:56.490243 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9980 09:58:56.497164 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9981 09:58:56.500335 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9982 09:58:56.507352 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9983 09:58:56.510225 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9984 09:58:56.516707 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9985 09:58:56.520221 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9986 09:58:56.520333 INFO: [APUAPC] vio 0
9987 09:58:56.527804 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9988 09:58:56.531155 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9989 09:58:56.534313 INFO: [APUAPC] D0_APC_0: 0x400510
9990 09:58:56.537750 INFO: [APUAPC] D0_APC_1: 0x0
9991 09:58:56.540977 INFO: [APUAPC] D0_APC_2: 0x1540
9992 09:58:56.544377 INFO: [APUAPC] D0_APC_3: 0x0
9993 09:58:56.547487 INFO: [APUAPC] D1_APC_0: 0xffffffff
9994 09:58:56.550755 INFO: [APUAPC] D1_APC_1: 0xffffffff
9995 09:58:56.554074 INFO: [APUAPC] D1_APC_2: 0x3fffff
9996 09:58:56.557675 INFO: [APUAPC] D1_APC_3: 0x0
9997 09:58:56.561491 INFO: [APUAPC] D2_APC_0: 0xffffffff
9998 09:58:56.564179 INFO: [APUAPC] D2_APC_1: 0xffffffff
9999 09:58:56.567733 INFO: [APUAPC] D2_APC_2: 0x3fffff
10000 09:58:56.571302 INFO: [APUAPC] D2_APC_3: 0x0
10001 09:58:56.574630 INFO: [APUAPC] D3_APC_0: 0xffffffff
10002 09:58:56.577985 INFO: [APUAPC] D3_APC_1: 0xffffffff
10003 09:58:56.581518 INFO: [APUAPC] D3_APC_2: 0x3fffff
10004 09:58:56.581597 INFO: [APUAPC] D3_APC_3: 0x0
10005 09:58:56.584548 INFO: [APUAPC] D4_APC_0: 0xffffffff
10006 09:58:56.587828 INFO: [APUAPC] D4_APC_1: 0xffffffff
10007 09:58:56.591248 INFO: [APUAPC] D4_APC_2: 0x3fffff
10008 09:58:56.594547 INFO: [APUAPC] D4_APC_3: 0x0
10009 09:58:56.598053 INFO: [APUAPC] D5_APC_0: 0xffffffff
10010 09:58:56.601390 INFO: [APUAPC] D5_APC_1: 0xffffffff
10011 09:58:56.604499 INFO: [APUAPC] D5_APC_2: 0x3fffff
10012 09:58:56.607953 INFO: [APUAPC] D5_APC_3: 0x0
10013 09:58:56.611256 INFO: [APUAPC] D6_APC_0: 0xffffffff
10014 09:58:56.614472 INFO: [APUAPC] D6_APC_1: 0xffffffff
10015 09:58:56.617998 INFO: [APUAPC] D6_APC_2: 0x3fffff
10016 09:58:56.621286 INFO: [APUAPC] D6_APC_3: 0x0
10017 09:58:56.624822 INFO: [APUAPC] D7_APC_0: 0xffffffff
10018 09:58:56.628172 INFO: [APUAPC] D7_APC_1: 0xffffffff
10019 09:58:56.631111 INFO: [APUAPC] D7_APC_2: 0x3fffff
10020 09:58:56.634635 INFO: [APUAPC] D7_APC_3: 0x0
10021 09:58:56.637761 INFO: [APUAPC] D8_APC_0: 0xffffffff
10022 09:58:56.641305 INFO: [APUAPC] D8_APC_1: 0xffffffff
10023 09:58:56.644554 INFO: [APUAPC] D8_APC_2: 0x3fffff
10024 09:58:56.648210 INFO: [APUAPC] D8_APC_3: 0x0
10025 09:58:56.651360 INFO: [APUAPC] D9_APC_0: 0xffffffff
10026 09:58:56.654451 INFO: [APUAPC] D9_APC_1: 0xffffffff
10027 09:58:56.658091 INFO: [APUAPC] D9_APC_2: 0x3fffff
10028 09:58:56.661188 INFO: [APUAPC] D9_APC_3: 0x0
10029 09:58:56.664697 INFO: [APUAPC] D10_APC_0: 0xffffffff
10030 09:58:56.668130 INFO: [APUAPC] D10_APC_1: 0xffffffff
10031 09:58:56.671169 INFO: [APUAPC] D10_APC_2: 0x3fffff
10032 09:58:56.674555 INFO: [APUAPC] D10_APC_3: 0x0
10033 09:58:56.677812 INFO: [APUAPC] D11_APC_0: 0xffffffff
10034 09:58:56.681225 INFO: [APUAPC] D11_APC_1: 0xffffffff
10035 09:58:56.684884 INFO: [APUAPC] D11_APC_2: 0x3fffff
10036 09:58:56.687722 INFO: [APUAPC] D11_APC_3: 0x0
10037 09:58:56.691118 INFO: [APUAPC] D12_APC_0: 0xffffffff
10038 09:58:56.695051 INFO: [APUAPC] D12_APC_1: 0xffffffff
10039 09:58:56.698118 INFO: [APUAPC] D12_APC_2: 0x3fffff
10040 09:58:56.701422 INFO: [APUAPC] D12_APC_3: 0x0
10041 09:58:56.704924 INFO: [APUAPC] D13_APC_0: 0xffffffff
10042 09:58:56.707907 INFO: [APUAPC] D13_APC_1: 0xffffffff
10043 09:58:56.711483 INFO: [APUAPC] D13_APC_2: 0x3fffff
10044 09:58:56.714709 INFO: [APUAPC] D13_APC_3: 0x0
10045 09:58:56.718425 INFO: [APUAPC] D14_APC_0: 0xffffffff
10046 09:58:56.721472 INFO: [APUAPC] D14_APC_1: 0xffffffff
10047 09:58:56.724847 INFO: [APUAPC] D14_APC_2: 0x3fffff
10048 09:58:56.727970 INFO: [APUAPC] D14_APC_3: 0x0
10049 09:58:56.731549 INFO: [APUAPC] D15_APC_0: 0xffffffff
10050 09:58:56.735127 INFO: [APUAPC] D15_APC_1: 0xffffffff
10051 09:58:56.738355 INFO: [APUAPC] D15_APC_2: 0x3fffff
10052 09:58:56.741310 INFO: [APUAPC] D15_APC_3: 0x0
10053 09:58:56.744785 INFO: [APUAPC] APC_CON: 0x4
10054 09:58:56.744871 INFO: [NOCDAPC] D0_APC_0: 0x0
10055 09:58:56.748151 INFO: [NOCDAPC] D0_APC_1: 0x0
10056 09:58:56.751616 INFO: [NOCDAPC] D1_APC_0: 0x0
10057 09:58:56.754845 INFO: [NOCDAPC] D1_APC_1: 0xfff
10058 09:58:56.758398 INFO: [NOCDAPC] D2_APC_0: 0x0
10059 09:58:56.761389 INFO: [NOCDAPC] D2_APC_1: 0xfff
10060 09:58:56.765021 INFO: [NOCDAPC] D3_APC_0: 0x0
10061 09:58:56.768512 INFO: [NOCDAPC] D3_APC_1: 0xfff
10062 09:58:56.771582 INFO: [NOCDAPC] D4_APC_0: 0x0
10063 09:58:56.775160 INFO: [NOCDAPC] D4_APC_1: 0xfff
10064 09:58:56.775246 INFO: [NOCDAPC] D5_APC_0: 0x0
10065 09:58:56.778170 INFO: [NOCDAPC] D5_APC_1: 0xfff
10066 09:58:56.781640 INFO: [NOCDAPC] D6_APC_0: 0x0
10067 09:58:56.784914 INFO: [NOCDAPC] D6_APC_1: 0xfff
10068 09:58:56.788400 INFO: [NOCDAPC] D7_APC_0: 0x0
10069 09:58:56.792021 INFO: [NOCDAPC] D7_APC_1: 0xfff
10070 09:58:56.795390 INFO: [NOCDAPC] D8_APC_0: 0x0
10071 09:58:56.798296 INFO: [NOCDAPC] D8_APC_1: 0xfff
10072 09:58:56.802049 INFO: [NOCDAPC] D9_APC_0: 0x0
10073 09:58:56.804801 INFO: [NOCDAPC] D9_APC_1: 0xfff
10074 09:58:56.804887 INFO: [NOCDAPC] D10_APC_0: 0x0
10075 09:58:56.808557 INFO: [NOCDAPC] D10_APC_1: 0xfff
10076 09:58:56.811947 INFO: [NOCDAPC] D11_APC_0: 0x0
10077 09:58:56.815372 INFO: [NOCDAPC] D11_APC_1: 0xfff
10078 09:58:56.818449 INFO: [NOCDAPC] D12_APC_0: 0x0
10079 09:58:56.821822 INFO: [NOCDAPC] D12_APC_1: 0xfff
10080 09:58:56.824919 INFO: [NOCDAPC] D13_APC_0: 0x0
10081 09:58:56.828278 INFO: [NOCDAPC] D13_APC_1: 0xfff
10082 09:58:56.831599 INFO: [NOCDAPC] D14_APC_0: 0x0
10083 09:58:56.835053 INFO: [NOCDAPC] D14_APC_1: 0xfff
10084 09:58:56.838440 INFO: [NOCDAPC] D15_APC_0: 0x0
10085 09:58:56.841245 INFO: [NOCDAPC] D15_APC_1: 0xfff
10086 09:58:56.844785 INFO: [NOCDAPC] APC_CON: 0x4
10087 09:58:56.848056 INFO: [APUAPC] set_apusys_apc done
10088 09:58:56.851397 INFO: [DEVAPC] devapc_init done
10089 09:58:56.854717 INFO: GICv3 without legacy support detected.
10090 09:58:56.858276 INFO: ARM GICv3 driver initialized in EL3
10091 09:58:56.861258 INFO: Maximum SPI INTID supported: 639
10092 09:58:56.865024 INFO: BL31: Initializing runtime services
10093 09:58:56.871346 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10094 09:58:56.874701 INFO: SPM: enable CPC mode
10095 09:58:56.878062 INFO: mcdi ready for mcusys-off-idle and system suspend
10096 09:58:56.885228 INFO: BL31: Preparing for EL3 exit to normal world
10097 09:58:56.888325 INFO: Entry point address = 0x80000000
10098 09:58:56.891278 INFO: SPSR = 0x8
10099 09:58:56.895906
10100 09:58:56.895986
10101 09:58:56.896053
10102 09:58:56.896737 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10103 09:58:56.896845 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10104 09:58:56.896930 Setting prompt string to ['asurada:']
10105 09:58:56.897015 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10106 09:58:56.898932 Starting depthcharge on Spherion...
10107 09:58:56.899034
10108 09:58:56.899101 Wipe memory regions:
10109 09:58:56.899162
10110 09:58:56.902523 [0x00000040000000, 0x00000054600000)
10111 09:58:57.024816
10112 09:58:57.024956 [0x00000054660000, 0x00000080000000)
10113 09:58:57.285581
10114 09:58:57.286078 [0x000000821a7280, 0x000000ffe64000)
10115 09:58:58.030085
10116 09:58:58.030802 [0x00000100000000, 0x00000240000000)
10117 09:58:59.919247
10118 09:58:59.921845 Initializing XHCI USB controller at 0x11200000.
10119 09:59:00.960004
10120 09:59:00.963015 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10121 09:59:00.963103
10122 09:59:00.963168
10123 09:59:00.963230
10124 09:59:00.963515 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10126 09:59:01.064049 asurada: tftpboot 192.168.201.1 12073277/tftp-deploy-4j2yyqmd/kernel/image.itb 12073277/tftp-deploy-4j2yyqmd/kernel/cmdline
10127 09:59:01.064626 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10128 09:59:01.065034 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10129 09:59:01.069091 tftpboot 192.168.201.1 12073277/tftp-deploy-4j2yyqmd/kernel/image.ittp-deploy-4j2yyqmd/kernel/cmdline
10130 09:59:01.069529
10131 09:59:01.069865 Waiting for link
10132 09:59:01.230050
10133 09:59:01.230534 R8152: Initializing
10134 09:59:01.230896
10135 09:59:01.233365 Version 6 (ocp_data = 5c30)
10136 09:59:01.233855
10137 09:59:01.236439 R8152: Done initializing
10138 09:59:01.236924
10139 09:59:01.237267 Adding net device
10140 09:59:03.327367
10141 09:59:03.327920 done.
10142 09:59:03.328380
10143 09:59:03.328792 MAC: 00:24:32:30:78:52
10144 09:59:03.329124
10145 09:59:03.331501 Sending DHCP discover... done.
10146 09:59:03.331924
10147 09:59:03.334231 Waiting for reply... done.
10148 09:59:03.334759
10149 09:59:03.337097 Sending DHCP request... done.
10150 09:59:03.337694
10151 09:59:03.348594 Waiting for reply... done.
10152 09:59:03.349215
10153 09:59:03.349573 My ip is 192.168.201.14
10154 09:59:03.350066
10155 09:59:03.351675 The DHCP server ip is 192.168.201.1
10156 09:59:03.352126
10157 09:59:03.358440 TFTP server IP predefined by user: 192.168.201.1
10158 09:59:03.359093
10159 09:59:03.365477 Bootfile predefined by user: 12073277/tftp-deploy-4j2yyqmd/kernel/image.itb
10160 09:59:03.365929
10161 09:59:03.366360 Sending tftp read request... done.
10162 09:59:03.368266
10163 09:59:03.374283 Waiting for the transfer...
10164 09:59:03.374703
10165 09:59:04.029469 00000000 ################################################################
10166 09:59:04.029981
10167 09:59:04.741720 00080000 ################################################################
10168 09:59:04.742242
10169 09:59:05.432958 00100000 ################################################################
10170 09:59:05.433551
10171 09:59:06.104248 00180000 ################################################################
10172 09:59:06.104393
10173 09:59:06.812125 00200000 ################################################################
10174 09:59:06.812668
10175 09:59:07.463232 00280000 ################################################################
10176 09:59:07.463416
10177 09:59:08.044876 00300000 ################################################################
10178 09:59:08.045023
10179 09:59:08.611032 00380000 ################################################################
10180 09:59:08.611234
10181 09:59:09.182023 00400000 ################################################################
10182 09:59:09.182188
10183 09:59:09.773584 00480000 ################################################################
10184 09:59:09.773731
10185 09:59:10.366503 00500000 ################################################################
10186 09:59:10.366653
10187 09:59:10.946956 00580000 ################################################################
10188 09:59:10.947107
10189 09:59:11.525556 00600000 ################################################################
10190 09:59:11.525706
10191 09:59:12.111272 00680000 ################################################################
10192 09:59:12.111419
10193 09:59:12.714234 00700000 ################################################################
10194 09:59:12.714384
10195 09:59:13.305921 00780000 ################################################################
10196 09:59:13.306071
10197 09:59:13.888068 00800000 ################################################################
10198 09:59:13.888217
10199 09:59:14.483325 00880000 ################################################################
10200 09:59:14.483467
10201 09:59:15.070736 00900000 ################################################################
10202 09:59:15.070914
10203 09:59:15.648854 00980000 ################################################################
10204 09:59:15.648994
10205 09:59:16.207436 00a00000 ################################################################
10206 09:59:16.207636
10207 09:59:16.777789 00a80000 ################################################################
10208 09:59:16.777939
10209 09:59:17.347147 00b00000 ################################################################
10210 09:59:17.347297
10211 09:59:17.928944 00b80000 ################################################################
10212 09:59:17.929092
10213 09:59:18.526324 00c00000 ################################################################
10214 09:59:18.526478
10215 09:59:19.122064 00c80000 ################################################################
10216 09:59:19.122214
10217 09:59:19.693513 00d00000 ################################################################
10218 09:59:19.693674
10219 09:59:20.240138 00d80000 ################################################################
10220 09:59:20.240297
10221 09:59:20.843200 00e00000 ################################################################
10222 09:59:20.843902
10223 09:59:21.480199 00e80000 ################################################################
10224 09:59:21.480360
10225 09:59:22.141169 00f00000 ################################################################
10226 09:59:22.141314
10227 09:59:22.721872 00f80000 ################################################################
10228 09:59:22.722001
10229 09:59:23.272832 01000000 ################################################################
10230 09:59:23.272999
10231 09:59:23.892706 01080000 ################################################################
10232 09:59:23.892858
10233 09:59:24.545747 01100000 ################################################################
10234 09:59:24.545887
10235 09:59:25.125934 01180000 ################################################################
10236 09:59:25.126076
10237 09:59:25.693617 01200000 ################################################################
10238 09:59:25.693751
10239 09:59:26.261652 01280000 ################################################################
10240 09:59:26.261834
10241 09:59:26.842116 01300000 ################################################################
10242 09:59:26.842263
10243 09:59:27.399555 01380000 ################################################################
10244 09:59:27.399693
10245 09:59:27.961702 01400000 ################################################################
10246 09:59:27.961879
10247 09:59:28.517899 01480000 ################################################################
10248 09:59:28.518046
10249 09:59:29.077496 01500000 ################################################################
10250 09:59:29.077632
10251 09:59:29.635871 01580000 ################################################################
10252 09:59:29.636021
10253 09:59:30.167115 01600000 ################################################################
10254 09:59:30.167256
10255 09:59:30.760147 01680000 ################################################################
10256 09:59:30.760297
10257 09:59:31.335339 01700000 ################################################################
10258 09:59:31.335491
10259 09:59:31.942620 01780000 ################################################################
10260 09:59:31.942791
10261 09:59:32.498377 01800000 ################################################################
10262 09:59:32.498536
10263 09:59:33.040074 01880000 ################################################################
10264 09:59:33.040227
10265 09:59:33.612535 01900000 ################################################################
10266 09:59:33.612689
10267 09:59:34.187921 01980000 ################################################################
10268 09:59:34.188090
10269 09:59:34.753605 01a00000 ################################################################
10270 09:59:34.753751
10271 09:59:35.387497 01a80000 ################################################################
10272 09:59:35.387644
10273 09:59:35.999252 01b00000 ################################################################
10274 09:59:35.999400
10275 09:59:36.063091 01b80000 ####### done.
10276 09:59:36.063206
10277 09:59:36.066679 The bootfile was 28890126 bytes long.
10278 09:59:36.066766
10279 09:59:36.069576 Sending tftp read request... done.
10280 09:59:36.069659
10281 09:59:36.069724 Waiting for the transfer...
10282 09:59:36.069784
10283 09:59:36.073051 00000000 # done.
10284 09:59:36.073136
10285 09:59:36.079484 Command line loaded dynamically from TFTP file: 12073277/tftp-deploy-4j2yyqmd/kernel/cmdline
10286 09:59:36.079573
10287 09:59:36.103112 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12073277/extract-nfsrootfs-vxspfp2o,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10288 09:59:36.103209
10289 09:59:36.103275 Loading FIT.
10290 09:59:36.103336
10291 09:59:36.106569 Image ramdisk-1 has 17793271 bytes.
10292 09:59:36.106652
10293 09:59:36.110231 Image fdt-1 has 47278 bytes.
10294 09:59:36.110313
10295 09:59:36.113175 Image kernel-1 has 11047542 bytes.
10296 09:59:36.113258
10297 09:59:36.119830 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10298 09:59:36.123358
10299 09:59:36.139748 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10300 09:59:36.139842
10301 09:59:36.143059 Choosing best match conf-1 for compat google,spherion-rev2.
10302 09:59:36.148536
10303 09:59:36.153358 Connected to device vid:did:rid of 1ae0:0028:00
10304 09:59:36.160425
10305 09:59:36.163661 tpm_get_response: command 0x17b, return code 0x0
10306 09:59:36.163744
10307 09:59:36.166925 ec_init: CrosEC protocol v3 supported (256, 248)
10308 09:59:36.171722
10309 09:59:36.175596 tpm_cleanup: add release locality here.
10310 09:59:36.175680
10311 09:59:36.175746 Shutting down all USB controllers.
10312 09:59:36.178800
10313 09:59:36.178958 Removing current net device
10314 09:59:36.179025
10315 09:59:36.185281 Exiting depthcharge with code 4 at timestamp: 68655258
10316 09:59:36.185364
10317 09:59:36.189374 LZMA decompressing kernel-1 to 0x821a6718
10318 09:59:36.189456
10319 09:59:36.191907 LZMA decompressing kernel-1 to 0x40000000
10320 09:59:37.581203
10321 09:59:37.581672 jumping to kernel
10322 09:59:37.583149 end: 2.2.4 bootloader-commands (duration 00:00:41) [common]
10323 09:59:37.583596 start: 2.2.5 auto-login-action (timeout 00:03:44) [common]
10324 09:59:37.583943 Setting prompt string to ['Linux version [0-9]']
10325 09:59:37.584301 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10326 09:59:37.584619 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10327 09:59:37.663449
10328 09:59:37.666625 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10329 09:59:37.670229 start: 2.2.5.1 login-action (timeout 00:03:44) [common]
10330 09:59:37.670654 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10331 09:59:37.671043 Setting prompt string to []
10332 09:59:37.671412 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10333 09:59:37.671750 Using line separator: #'\n'#
10334 09:59:37.672034 No login prompt set.
10335 09:59:37.672330 Parsing kernel messages
10336 09:59:37.672787 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10337 09:59:37.673338 [login-action] Waiting for messages, (timeout 00:03:44)
10338 09:59:37.689543 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j22848-arm64-gcc-10-defconfig-arm64-chromebook-6q8mw) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Nov 24 09:44:51 UTC 2023
10339 09:59:37.692762 [ 0.000000] random: crng init done
10340 09:59:37.699345 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10341 09:59:37.702847 [ 0.000000] efi: UEFI not found.
10342 09:59:37.709137 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10343 09:59:37.715892 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10344 09:59:37.725895 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10345 09:59:37.736289 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10346 09:59:37.742612 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10347 09:59:37.746092 [ 0.000000] printk: bootconsole [mtk8250] enabled
10348 09:59:37.754548 [ 0.000000] NUMA: No NUMA configuration found
10349 09:59:37.761811 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10350 09:59:37.767775 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10351 09:59:37.767859 [ 0.000000] Zone ranges:
10352 09:59:37.774894 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10353 09:59:37.778023 [ 0.000000] DMA32 empty
10354 09:59:37.784868 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10355 09:59:37.788475 [ 0.000000] Movable zone start for each node
10356 09:59:37.791242 [ 0.000000] Early memory node ranges
10357 09:59:37.798074 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10358 09:59:37.804775 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10359 09:59:37.811722 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10360 09:59:37.818784 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10361 09:59:37.824888 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10362 09:59:37.831393 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10363 09:59:37.887934 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10364 09:59:37.894263 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10365 09:59:37.900778 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10366 09:59:37.904087 [ 0.000000] psci: probing for conduit method from DT.
10367 09:59:37.910989 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10368 09:59:37.914204 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10369 09:59:37.920723 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10370 09:59:37.924114 [ 0.000000] psci: SMC Calling Convention v1.2
10371 09:59:37.930763 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10372 09:59:37.937715 [ 0.000000] Detected VIPT I-cache on CPU0
10373 09:59:37.940915 [ 0.000000] CPU features: detected: GIC system register CPU interface
10374 09:59:37.947704 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10375 09:59:37.954031 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10376 09:59:37.961778 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10377 09:59:37.967371 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10378 09:59:37.973825 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10379 09:59:37.980396 [ 0.000000] alternatives: applying boot alternatives
10380 09:59:37.983948 [ 0.000000] Fallback order for Node 0: 0
10381 09:59:37.993674 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10382 09:59:37.994096 [ 0.000000] Policy zone: Normal
10383 09:59:38.017197 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12073277/extract-nfsrootfs-vxspfp2o,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10384 09:59:38.030362 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10385 09:59:38.040038 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10386 09:59:38.049959 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10387 09:59:38.056949 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10388 09:59:38.060404 <6>[ 0.000000] software IO TLB: area num 8.
10389 09:59:38.116600 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10390 09:59:38.265112 <6>[ 0.000000] Memory: 7952244K/8385536K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 400524K reserved, 32768K cma-reserved)
10391 09:59:38.272027 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10392 09:59:38.278929 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10393 09:59:38.281896 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10394 09:59:38.288746 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10395 09:59:38.295333 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10396 09:59:38.298640 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10397 09:59:38.308178 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10398 09:59:38.315293 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10399 09:59:38.318196 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10400 09:59:38.326020 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10401 09:59:38.329624 <6>[ 0.000000] GICv3: 608 SPIs implemented
10402 09:59:38.335737 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10403 09:59:38.339082 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10404 09:59:38.342342 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10405 09:59:38.352435 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10406 09:59:38.362624 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10407 09:59:38.376181 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10408 09:59:38.382960 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10409 09:59:38.391569 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10410 09:59:38.404993 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10411 09:59:38.411745 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10412 09:59:38.418361 <6>[ 0.009237] Console: colour dummy device 80x25
10413 09:59:38.428367 <6>[ 0.013992] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10414 09:59:38.434564 <6>[ 0.024499] pid_max: default: 32768 minimum: 301
10415 09:59:38.437862 <6>[ 0.029402] LSM: Security Framework initializing
10416 09:59:38.444951 <6>[ 0.034372] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10417 09:59:38.454378 <6>[ 0.042186] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10418 09:59:38.461399 <6>[ 0.051646] cblist_init_generic: Setting adjustable number of callback queues.
10419 09:59:38.467598 <6>[ 0.059122] cblist_init_generic: Setting shift to 3 and lim to 1.
10420 09:59:38.478019 <6>[ 0.065461] cblist_init_generic: Setting adjustable number of callback queues.
10421 09:59:38.484603 <6>[ 0.072888] cblist_init_generic: Setting shift to 3 and lim to 1.
10422 09:59:38.487950 <6>[ 0.079325] rcu: Hierarchical SRCU implementation.
10423 09:59:38.494361 <6>[ 0.084340] rcu: Max phase no-delay instances is 1000.
10424 09:59:38.501165 <6>[ 0.091360] EFI services will not be available.
10425 09:59:38.504724 <6>[ 0.096318] smp: Bringing up secondary CPUs ...
10426 09:59:38.512683 <6>[ 0.101366] Detected VIPT I-cache on CPU1
10427 09:59:38.519313 <6>[ 0.101434] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10428 09:59:38.525869 <6>[ 0.101468] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10429 09:59:38.529681 <6>[ 0.101797] Detected VIPT I-cache on CPU2
10430 09:59:38.536142 <6>[ 0.101845] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10431 09:59:38.542658 <6>[ 0.101861] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10432 09:59:38.549289 <6>[ 0.102122] Detected VIPT I-cache on CPU3
10433 09:59:38.556116 <6>[ 0.102167] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10434 09:59:38.562400 <6>[ 0.102180] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10435 09:59:38.565679 <6>[ 0.102484] CPU features: detected: Spectre-v4
10436 09:59:38.572495 <6>[ 0.102491] CPU features: detected: Spectre-BHB
10437 09:59:38.576104 <6>[ 0.102496] Detected PIPT I-cache on CPU4
10438 09:59:38.582524 <6>[ 0.102553] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10439 09:59:38.589740 <6>[ 0.102569] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10440 09:59:38.592654 <6>[ 0.102861] Detected PIPT I-cache on CPU5
10441 09:59:38.602579 <6>[ 0.102924] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10442 09:59:38.609349 <6>[ 0.102940] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10443 09:59:38.612548 <6>[ 0.103221] Detected PIPT I-cache on CPU6
10444 09:59:38.619124 <6>[ 0.103286] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10445 09:59:38.625635 <6>[ 0.103302] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10446 09:59:38.628854 <6>[ 0.103596] Detected PIPT I-cache on CPU7
10447 09:59:38.638697 <6>[ 0.103660] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10448 09:59:38.645558 <6>[ 0.103676] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10449 09:59:38.649308 <6>[ 0.103723] smp: Brought up 1 node, 8 CPUs
10450 09:59:38.652445 <6>[ 0.245048] SMP: Total of 8 processors activated.
10451 09:59:38.658992 <6>[ 0.249968] CPU features: detected: 32-bit EL0 Support
10452 09:59:38.668774 <6>[ 0.255330] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10453 09:59:38.675496 <6>[ 0.264131] CPU features: detected: Common not Private translations
10454 09:59:38.678665 <6>[ 0.270606] CPU features: detected: CRC32 instructions
10455 09:59:38.685100 <6>[ 0.275958] CPU features: detected: RCpc load-acquire (LDAPR)
10456 09:59:38.692016 <6>[ 0.281954] CPU features: detected: LSE atomic instructions
10457 09:59:38.695465 <6>[ 0.287736] CPU features: detected: Privileged Access Never
10458 09:59:38.702083 <6>[ 0.293515] CPU features: detected: RAS Extension Support
10459 09:59:38.708511 <6>[ 0.299124] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10460 09:59:38.715845 <6>[ 0.306346] CPU: All CPU(s) started at EL2
10461 09:59:38.718651 <6>[ 0.310689] alternatives: applying system-wide alternatives
10462 09:59:38.730176 <6>[ 0.321386] devtmpfs: initialized
10463 09:59:38.742235 <6>[ 0.330338] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10464 09:59:38.751958 <6>[ 0.340304] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10465 09:59:38.759057 <6>[ 0.348491] pinctrl core: initialized pinctrl subsystem
10466 09:59:38.762131 <6>[ 0.355163] DMI not present or invalid.
10467 09:59:38.768835 <6>[ 0.359577] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10468 09:59:38.778621 <6>[ 0.366466] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10469 09:59:38.785565 <6>[ 0.374052] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10470 09:59:38.795160 <6>[ 0.382274] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10471 09:59:38.798499 <6>[ 0.390518] audit: initializing netlink subsys (disabled)
10472 09:59:38.808529 <5>[ 0.396200] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10473 09:59:38.812433 <6>[ 0.396898] thermal_sys: Registered thermal governor 'step_wise'
10474 09:59:38.821960 <6>[ 0.404170] thermal_sys: Registered thermal governor 'power_allocator'
10475 09:59:38.825276 <6>[ 0.410429] cpuidle: using governor menu
10476 09:59:38.828704 <6>[ 0.421394] NET: Registered PF_QIPCRTR protocol family
10477 09:59:38.839234 <6>[ 0.426887] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10478 09:59:38.842210 <6>[ 0.433992] ASID allocator initialised with 32768 entries
10479 09:59:38.849116 <6>[ 0.440558] Serial: AMBA PL011 UART driver
10480 09:59:38.857587 <4>[ 0.449328] Trying to register duplicate clock ID: 134
10481 09:59:38.914065 <6>[ 0.508871] KASLR enabled
10482 09:59:38.928594 <6>[ 0.516580] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10483 09:59:38.935326 <6>[ 0.523595] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10484 09:59:38.941762 <6>[ 0.530088] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10485 09:59:38.948555 <6>[ 0.537094] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10486 09:59:38.955355 <6>[ 0.543584] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10487 09:59:38.961872 <6>[ 0.550590] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10488 09:59:38.968779 <6>[ 0.557081] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10489 09:59:38.975156 <6>[ 0.564088] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10490 09:59:38.978478 <6>[ 0.571594] ACPI: Interpreter disabled.
10491 09:59:38.986743 <6>[ 0.578018] iommu: Default domain type: Translated
10492 09:59:38.993733 <6>[ 0.583132] iommu: DMA domain TLB invalidation policy: strict mode
10493 09:59:38.997284 <5>[ 0.589791] SCSI subsystem initialized
10494 09:59:39.003316 <6>[ 0.593955] usbcore: registered new interface driver usbfs
10495 09:59:39.009644 <6>[ 0.599689] usbcore: registered new interface driver hub
10496 09:59:39.013096 <6>[ 0.605243] usbcore: registered new device driver usb
10497 09:59:39.020295 <6>[ 0.611341] pps_core: LinuxPPS API ver. 1 registered
10498 09:59:39.030314 <6>[ 0.616536] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10499 09:59:39.033757 <6>[ 0.625886] PTP clock support registered
10500 09:59:39.036790 <6>[ 0.630130] EDAC MC: Ver: 3.0.0
10501 09:59:39.044650 <6>[ 0.635278] FPGA manager framework
10502 09:59:39.047306 <6>[ 0.638958] Advanced Linux Sound Architecture Driver Initialized.
10503 09:59:39.051215 <6>[ 0.645733] vgaarb: loaded
10504 09:59:39.057905 <6>[ 0.648916] clocksource: Switched to clocksource arch_sys_counter
10505 09:59:39.064587 <5>[ 0.655355] VFS: Disk quotas dquot_6.6.0
10506 09:59:39.071196 <6>[ 0.659543] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10507 09:59:39.073824 <6>[ 0.666736] pnp: PnP ACPI: disabled
10508 09:59:39.082028 <6>[ 0.673377] NET: Registered PF_INET protocol family
10509 09:59:39.088701 <6>[ 0.678967] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10510 09:59:39.103008 <6>[ 0.691251] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10511 09:59:39.113131 <6>[ 0.700066] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10512 09:59:39.119953 <6>[ 0.708037] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10513 09:59:39.126338 <6>[ 0.716738] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10514 09:59:39.138613 <6>[ 0.726485] TCP: Hash tables configured (established 65536 bind 65536)
10515 09:59:39.145194 <6>[ 0.733345] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10516 09:59:39.151774 <6>[ 0.740544] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10517 09:59:39.158358 <6>[ 0.748234] NET: Registered PF_UNIX/PF_LOCAL protocol family
10518 09:59:39.165205 <6>[ 0.754413] RPC: Registered named UNIX socket transport module.
10519 09:59:39.168561 <6>[ 0.760567] RPC: Registered udp transport module.
10520 09:59:39.174907 <6>[ 0.765504] RPC: Registered tcp transport module.
10521 09:59:39.182168 <6>[ 0.770436] RPC: Registered tcp NFSv4.1 backchannel transport module.
10522 09:59:39.185159 <6>[ 0.777108] PCI: CLS 0 bytes, default 64
10523 09:59:39.188409 <6>[ 0.781387] Unpacking initramfs...
10524 09:59:39.213268 <6>[ 0.801037] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10525 09:59:39.223033 <6>[ 0.809696] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10526 09:59:39.226697 <6>[ 0.818553] kvm [1]: IPA Size Limit: 40 bits
10527 09:59:39.233518 <6>[ 0.823087] kvm [1]: GICv3: no GICV resource entry
10528 09:59:39.236642 <6>[ 0.828112] kvm [1]: disabling GICv2 emulation
10529 09:59:39.242691 <6>[ 0.832810] kvm [1]: GIC system register CPU interface enabled
10530 09:59:39.246371 <6>[ 0.838982] kvm [1]: vgic interrupt IRQ18
10531 09:59:39.252642 <6>[ 0.843338] kvm [1]: VHE mode initialized successfully
10532 09:59:39.259455 <5>[ 0.849844] Initialise system trusted keyrings
10533 09:59:39.265881 <6>[ 0.854732] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10534 09:59:39.273509 <6>[ 0.864774] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10535 09:59:39.280166 <5>[ 0.871210] NFS: Registering the id_resolver key type
10536 09:59:39.283838 <5>[ 0.876519] Key type id_resolver registered
10537 09:59:39.290323 <5>[ 0.880935] Key type id_legacy registered
10538 09:59:39.297355 <6>[ 0.885215] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10539 09:59:39.303367 <6>[ 0.892141] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10540 09:59:39.310012 <6>[ 0.899857] 9p: Installing v9fs 9p2000 file system support
10541 09:59:39.346889 <5>[ 0.938383] Key type asymmetric registered
10542 09:59:39.350291 <5>[ 0.942733] Asymmetric key parser 'x509' registered
10543 09:59:39.360335 <6>[ 0.947904] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10544 09:59:39.363458 <6>[ 0.955525] io scheduler mq-deadline registered
10545 09:59:39.366672 <6>[ 0.960288] io scheduler kyber registered
10546 09:59:39.386581 <6>[ 0.977501] EINJ: ACPI disabled.
10547 09:59:39.418690 <4>[ 1.003482] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10548 09:59:39.428571 <4>[ 1.014138] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10549 09:59:39.443686 <6>[ 1.034964] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10550 09:59:39.451849 <6>[ 1.042925] printk: console [ttyS0] disabled
10551 09:59:39.479288 <6>[ 1.067570] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10552 09:59:39.486465 <6>[ 1.077048] printk: console [ttyS0] enabled
10553 09:59:39.489821 <6>[ 1.077048] printk: console [ttyS0] enabled
10554 09:59:39.496700 <6>[ 1.085950] printk: bootconsole [mtk8250] disabled
10555 09:59:39.499772 <6>[ 1.085950] printk: bootconsole [mtk8250] disabled
10556 09:59:39.506174 <6>[ 1.097169] SuperH (H)SCI(F) driver initialized
10557 09:59:39.509498 <6>[ 1.102438] msm_serial: driver initialized
10558 09:59:39.523426 <6>[ 1.111463] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10559 09:59:39.533371 <6>[ 1.120010] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10560 09:59:39.540241 <6>[ 1.128553] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10561 09:59:39.549886 <6>[ 1.137183] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10562 09:59:39.560057 <6>[ 1.145889] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10563 09:59:39.566507 <6>[ 1.154605] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10564 09:59:39.576533 <6>[ 1.163146] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10565 09:59:39.582938 <6>[ 1.171955] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10566 09:59:39.593023 <6>[ 1.180498] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10567 09:59:39.604778 <6>[ 1.196131] loop: module loaded
10568 09:59:39.611615 <6>[ 1.201881] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10569 09:59:39.633951 <4>[ 1.225350] mtk-pmic-keys: Failed to locate of_node [id: -1]
10570 09:59:39.640916 <6>[ 1.232276] megasas: 07.719.03.00-rc1
10571 09:59:39.650624 <6>[ 1.242037] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10572 09:59:39.657488 <6>[ 1.248330] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10573 09:59:39.673497 <6>[ 1.264862] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10574 09:59:39.730357 <6>[ 1.314851] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10575 09:59:39.929057 <6>[ 1.520514] Freeing initrd memory: 17372K
10576 09:59:39.939227 <6>[ 1.530803] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10577 09:59:39.950397 <6>[ 1.541788] tun: Universal TUN/TAP device driver, 1.6
10578 09:59:39.953751 <6>[ 1.547854] thunder_xcv, ver 1.0
10579 09:59:39.957140 <6>[ 1.551361] thunder_bgx, ver 1.0
10580 09:59:39.960441 <6>[ 1.554855] nicpf, ver 1.0
10581 09:59:39.971010 <6>[ 1.558879] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10582 09:59:39.974379 <6>[ 1.566359] hns3: Copyright (c) 2017 Huawei Corporation.
10583 09:59:39.977559 <6>[ 1.571950] hclge is initializing
10584 09:59:39.984281 <6>[ 1.575524] e1000: Intel(R) PRO/1000 Network Driver
10585 09:59:39.990688 <6>[ 1.580653] e1000: Copyright (c) 1999-2006 Intel Corporation.
10586 09:59:39.994179 <6>[ 1.586665] e1000e: Intel(R) PRO/1000 Network Driver
10587 09:59:40.000840 <6>[ 1.591880] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10588 09:59:40.007687 <6>[ 1.598067] igb: Intel(R) Gigabit Ethernet Network Driver
10589 09:59:40.014837 <6>[ 1.603718] igb: Copyright (c) 2007-2014 Intel Corporation.
10590 09:59:40.020944 <6>[ 1.609555] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10591 09:59:40.024778 <6>[ 1.616072] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10592 09:59:40.031736 <6>[ 1.622544] sky2: driver version 1.30
10593 09:59:40.038335 <6>[ 1.627541] VFIO - User Level meta-driver version: 0.3
10594 09:59:40.044960 <6>[ 1.635810] usbcore: registered new interface driver usb-storage
10595 09:59:40.051606 <6>[ 1.642267] usbcore: registered new device driver onboard-usb-hub
10596 09:59:40.060172 <6>[ 1.651488] mt6397-rtc mt6359-rtc: registered as rtc0
10597 09:59:40.070251 <6>[ 1.656957] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-24T09:59:41 UTC (1700819981)
10598 09:59:40.073531 <6>[ 1.666530] i2c_dev: i2c /dev entries driver
10599 09:59:40.090537 <6>[ 1.678453] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10600 09:59:40.110119 <6>[ 1.701447] cpu cpu0: EM: created perf domain
10601 09:59:40.113357 <6>[ 1.706392] cpu cpu4: EM: created perf domain
10602 09:59:40.120412 <6>[ 1.712022] sdhci: Secure Digital Host Controller Interface driver
10603 09:59:40.127260 <6>[ 1.718453] sdhci: Copyright(c) Pierre Ossman
10604 09:59:40.134181 <6>[ 1.723412] Synopsys Designware Multimedia Card Interface Driver
10605 09:59:40.140647 <6>[ 1.730052] sdhci-pltfm: SDHCI platform and OF driver helper
10606 09:59:40.144652 <6>[ 1.730171] mmc0: CQHCI version 5.10
10607 09:59:40.150781 <6>[ 1.740065] ledtrig-cpu: registered to indicate activity on CPUs
10608 09:59:40.157836 <6>[ 1.746999] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10609 09:59:40.164253 <6>[ 1.754045] usbcore: registered new interface driver usbhid
10610 09:59:40.167955 <6>[ 1.759869] usbhid: USB HID core driver
10611 09:59:40.174114 <6>[ 1.764074] spi_master spi0: will run message pump with realtime priority
10612 09:59:40.216506 <6>[ 1.801163] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10613 09:59:40.231554 <6>[ 1.815936] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10614 09:59:40.238381 <6>[ 1.829558] mmc0: Command Queue Engine enabled
10615 09:59:40.245981 <6>[ 1.834338] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10616 09:59:40.251802 <6>[ 1.841312] cros-ec-spi spi0.0: Chrome EC device registered
10617 09:59:40.255246 <6>[ 1.841730] mmcblk0: mmc0:0001 DA4128 116 GiB
10618 09:59:40.266170 <6>[ 1.857370] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10619 09:59:40.274058 <6>[ 1.864815] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10620 09:59:40.280451 <6>[ 1.870716] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10621 09:59:40.287297 <6>[ 1.876558] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10622 09:59:40.302511 <6>[ 1.890303] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10623 09:59:40.309923 <6>[ 1.900943] NET: Registered PF_PACKET protocol family
10624 09:59:40.313150 <6>[ 1.906337] 9pnet: Installing 9P2000 support
10625 09:59:40.319542 <5>[ 1.910903] Key type dns_resolver registered
10626 09:59:40.322853 <6>[ 1.915911] registered taskstats version 1
10627 09:59:40.329828 <5>[ 1.920294] Loading compiled-in X.509 certificates
10628 09:59:40.361892 <4>[ 1.946323] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10629 09:59:40.371923 <4>[ 1.957217] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10630 09:59:40.378414 <3>[ 1.967757] debugfs: File 'uA_load' in directory '/' already present!
10631 09:59:40.385528 <3>[ 1.974465] debugfs: File 'min_uV' in directory '/' already present!
10632 09:59:40.391737 <3>[ 1.981075] debugfs: File 'max_uV' in directory '/' already present!
10633 09:59:40.398673 <3>[ 1.987686] debugfs: File 'constraint_flags' in directory '/' already present!
10634 09:59:40.409615 <3>[ 1.997578] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10635 09:59:40.424453 <6>[ 2.015689] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10636 09:59:40.431364 <6>[ 2.022533] xhci-mtk 11200000.usb: xHCI Host Controller
10637 09:59:40.437798 <6>[ 2.028032] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10638 09:59:40.447738 <6>[ 2.035898] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10639 09:59:40.454657 <6>[ 2.045338] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10640 09:59:40.461140 <6>[ 2.051453] xhci-mtk 11200000.usb: xHCI Host Controller
10641 09:59:40.468433 <6>[ 2.056941] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10642 09:59:40.475333 <6>[ 2.064682] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10643 09:59:40.482287 <6>[ 2.072450] hub 1-0:1.0: USB hub found
10644 09:59:40.485073 <6>[ 2.076481] hub 1-0:1.0: 1 port detected
10645 09:59:40.491555 <6>[ 2.080786] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10646 09:59:40.498906 <6>[ 2.089654] hub 2-0:1.0: USB hub found
10647 09:59:40.502143 <6>[ 2.093682] hub 2-0:1.0: 1 port detected
10648 09:59:40.510211 <6>[ 2.101830] mtk-msdc 11f70000.mmc: Got CD GPIO
10649 09:59:40.522463 <6>[ 2.110051] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10650 09:59:40.528611 <6>[ 2.118084] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10651 09:59:40.538857 <4>[ 2.125998] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10652 09:59:40.548765 <6>[ 2.135566] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10653 09:59:40.555412 <6>[ 2.143643] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10654 09:59:40.562411 <6>[ 2.151666] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10655 09:59:40.572206 <6>[ 2.159584] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10656 09:59:40.578991 <6>[ 2.167401] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10657 09:59:40.589422 <6>[ 2.175218] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10658 09:59:40.599481 <6>[ 2.185710] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10659 09:59:40.606465 <6>[ 2.194080] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10660 09:59:40.616069 <6>[ 2.202427] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10661 09:59:40.622516 <6>[ 2.210766] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10662 09:59:40.632805 <6>[ 2.219105] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10663 09:59:40.639142 <6>[ 2.227444] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10664 09:59:40.649460 <6>[ 2.235783] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10665 09:59:40.656262 <6>[ 2.244122] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10666 09:59:40.666030 <6>[ 2.252465] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10667 09:59:40.672364 <6>[ 2.260803] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10668 09:59:40.679624 <6>[ 2.269141] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10669 09:59:40.689382 <6>[ 2.277479] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10670 09:59:40.695911 <6>[ 2.285818] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10671 09:59:40.706315 <6>[ 2.294156] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10672 09:59:40.712984 <6>[ 2.302495] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10673 09:59:40.719492 <6>[ 2.311207] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10674 09:59:40.726836 <6>[ 2.318350] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10675 09:59:40.733363 <6>[ 2.325113] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10676 09:59:40.743601 <6>[ 2.331869] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10677 09:59:40.750577 <6>[ 2.338801] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10678 09:59:40.756902 <6>[ 2.345642] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10679 09:59:40.766974 <6>[ 2.354769] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10680 09:59:40.776909 <6>[ 2.363888] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10681 09:59:40.787103 <6>[ 2.373199] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10682 09:59:40.797014 <6>[ 2.382679] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10683 09:59:40.803989 <6>[ 2.392148] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10684 09:59:40.813658 <6>[ 2.401270] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10685 09:59:40.823862 <6>[ 2.410740] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10686 09:59:40.833332 <6>[ 2.419859] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10687 09:59:40.843429 <6>[ 2.429152] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10688 09:59:40.853055 <6>[ 2.439325] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10689 09:59:40.863160 <6>[ 2.450872] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10690 09:59:40.869781 <6>[ 2.460654] Trying to probe devices needed for running init ...
10691 09:59:40.912427 <6>[ 2.501025] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10692 09:59:41.068115 <6>[ 2.659121] hub 1-1:1.0: USB hub found
10693 09:59:41.071466 <6>[ 2.663650] hub 1-1:1.0: 4 ports detected
10694 09:59:41.080769 <6>[ 2.672490] hub 1-1:1.0: USB hub found
10695 09:59:41.084124 <6>[ 2.676829] hub 1-1:1.0: 4 ports detected
10696 09:59:41.192894 <6>[ 2.781543] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10697 09:59:41.219191 <6>[ 2.810623] hub 2-1:1.0: USB hub found
10698 09:59:41.222300 <6>[ 2.815029] hub 2-1:1.0: 3 ports detected
10699 09:59:41.231264 <6>[ 2.822985] hub 2-1:1.0: USB hub found
10700 09:59:41.234914 <6>[ 2.827524] hub 2-1:1.0: 3 ports detected
10701 09:59:41.408809 <6>[ 2.997215] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10702 09:59:41.541016 <6>[ 3.132720] hub 1-1.4:1.0: USB hub found
10703 09:59:41.543910 <6>[ 3.137356] hub 1-1.4:1.0: 2 ports detected
10704 09:59:41.553444 <6>[ 3.145230] hub 1-1.4:1.0: USB hub found
10705 09:59:41.556382 <6>[ 3.149835] hub 1-1.4:1.0: 2 ports detected
10706 09:59:41.620703 <6>[ 3.209412] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10707 09:59:41.853045 <6>[ 3.441231] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10708 09:59:42.044900 <6>[ 3.633232] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10709 09:59:53.169952 <6>[ 14.766200] ALSA device list:
10710 09:59:53.176773 <6>[ 14.769495] No soundcards found.
10711 09:59:53.184549 <6>[ 14.777427] Freeing unused kernel memory: 8384K
10712 09:59:53.187900 <6>[ 14.782411] Run /init as init process
10713 09:59:53.199412 Loading, please wait...
10714 09:59:53.219996 Starting version 247.3-7+deb11u2
10715 09:59:53.443249 <6>[ 15.033107] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10716 09:59:53.455280 <6>[ 15.048411] remoteproc remoteproc0: scp is available
10717 09:59:53.462057 <6>[ 15.053890] remoteproc remoteproc0: powering up scp
10718 09:59:53.468910 <6>[ 15.059025] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10719 09:59:53.475638 <6>[ 15.067509] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10720 09:59:53.489407 <6>[ 15.078896] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10721 09:59:53.496068 <6>[ 15.086532] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10722 09:59:53.506036 <3>[ 15.089666] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10723 09:59:53.512679 <6>[ 15.095230] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10724 09:59:53.522610 <4>[ 15.107516] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10725 09:59:53.529343 <3>[ 15.112074] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10726 09:59:53.536103 <3>[ 15.112098] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10727 09:59:53.545938 <3>[ 15.114409] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10728 09:59:53.548987 <6>[ 15.117973] mc: Linux media interface: v0.10
10729 09:59:53.555975 <4>[ 15.122810] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10730 09:59:53.565843 <3>[ 15.127669] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10731 09:59:53.572424 <6>[ 15.135055] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10732 09:59:53.578888 <6>[ 15.145040] usbcore: registered new interface driver r8152
10733 09:59:53.585490 <3>[ 15.148264] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10734 09:59:53.596320 <4>[ 15.167192] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10735 09:59:53.599250 <4>[ 15.167192] Fallback method does not support PEC.
10736 09:59:53.609435 <3>[ 15.171286] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10737 09:59:53.616101 <3>[ 15.171292] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10738 09:59:53.625967 <3>[ 15.193261] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10739 09:59:53.636169 <6>[ 15.193317] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10740 09:59:53.645904 <6>[ 15.193708] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10741 09:59:53.652771 <6>[ 15.194180] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10742 09:59:53.659367 <6>[ 15.198746] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10743 09:59:53.669521 <3>[ 15.199351] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10744 09:59:53.676039 <3>[ 15.199435] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10745 09:59:53.686742 <3>[ 15.199444] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10746 09:59:53.692627 <3>[ 15.199452] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10747 09:59:53.699232 <3>[ 15.199527] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10748 09:59:53.709926 <3>[ 15.199536] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10749 09:59:53.716048 <3>[ 15.199544] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10750 09:59:53.726148 <3>[ 15.199553] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10751 09:59:53.732478 <3>[ 15.199561] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10752 09:59:53.742703 <3>[ 15.199601] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10753 09:59:53.749446 <6>[ 15.200046] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10754 09:59:53.756608 <6>[ 15.201328] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10755 09:59:53.763156 <6>[ 15.222350] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10756 09:59:53.769917 <6>[ 15.223685] remoteproc remoteproc0: remote processor scp is now up
10757 09:59:53.779612 <6>[ 15.250009] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10758 09:59:53.783410 <6>[ 15.258704] pci_bus 0000:00: root bus resource [bus 00-ff]
10759 09:59:53.793001 <6>[ 15.307246] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10760 09:59:53.799779 <6>[ 15.315194] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10761 09:59:53.809718 <4>[ 15.323384] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10762 09:59:53.819693 <6>[ 15.331374] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10763 09:59:53.826162 <6>[ 15.340118] videodev: Linux video capture interface: v2.00
10764 09:59:53.832918 <6>[ 15.340137] usbcore: registered new interface driver cdc_ether
10765 09:59:53.840059 <4>[ 15.342577] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10766 09:59:53.846269 <6>[ 15.347735] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10767 09:59:53.852790 <6>[ 15.347954] usbcore: registered new interface driver r8153_ecm
10768 09:59:53.859528 <3>[ 15.354735] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10769 09:59:53.863487 <6>[ 15.369918] Bluetooth: Core ver 2.22
10770 09:59:53.872736 <6>[ 15.376410] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10771 09:59:53.876231 <6>[ 15.382201] NET: Registered PF_BLUETOOTH protocol family
10772 09:59:53.883114 <6>[ 15.391493] pci 0000:00:00.0: supports D1 D2
10773 09:59:53.889044 <6>[ 15.398542] Bluetooth: HCI device and connection manager initialized
10774 09:59:53.895989 <6>[ 15.407575] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10775 09:59:53.898991 <6>[ 15.407621] r8152 2-1.3:1.0 eth0: v1.12.13
10776 09:59:53.905988 <6>[ 15.417491] Bluetooth: HCI socket layer initialized
10777 09:59:53.912753 <6>[ 15.424272] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10778 09:59:53.918937 <6>[ 15.424311] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10779 09:59:53.926159 <6>[ 15.424406] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10780 09:59:53.932425 <6>[ 15.424432] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10781 09:59:53.942814 <6>[ 15.424448] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10782 09:59:53.949248 <6>[ 15.424463] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10783 09:59:53.952594 <6>[ 15.424567] pci 0000:01:00.0: supports D1 D2
10784 09:59:53.959132 <6>[ 15.424569] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10785 09:59:53.965780 <6>[ 15.425045] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10786 09:59:53.972324 <6>[ 15.429296] Bluetooth: L2CAP socket layer initialized
10787 09:59:53.975880 <6>[ 15.429330] Bluetooth: SCO socket layer initialized
10788 09:59:53.982756 <6>[ 15.433043] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10789 09:59:53.992319 <6>[ 15.433067] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10790 09:59:53.999283 <6>[ 15.433070] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10791 09:59:54.009022 <6>[ 15.433078] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10792 09:59:54.015791 <6>[ 15.433091] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10793 09:59:54.022224 <6>[ 15.433104] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10794 09:59:54.029203 <6>[ 15.433115] pci 0000:00:00.0: PCI bridge to [bus 01]
10795 09:59:54.035327 <6>[ 15.433120] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10796 09:59:54.042220 <6>[ 15.433238] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10797 09:59:54.048721 <6>[ 15.433703] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10798 09:59:54.055377 <6>[ 15.434122] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10799 09:59:54.068535 <6>[ 15.440037] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10800 09:59:54.075808 <6>[ 15.451817] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10801 09:59:54.078698 <6>[ 15.458770] usbcore: registered new interface driver uvcvideo
10802 09:59:54.085123 <6>[ 15.480337] usbcore: registered new interface driver btusb
10803 09:59:54.095605 <4>[ 15.480994] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10804 09:59:54.102198 <3>[ 15.481010] Bluetooth: hci0: Failed to load firmware file (-2)
10805 09:59:54.108632 <3>[ 15.481015] Bluetooth: hci0: Failed to set up firmware (-2)
10806 09:59:54.118683 <4>[ 15.481020] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10807 09:59:54.125533 <5>[ 15.495328] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10808 09:59:54.151598 <5>[ 15.741079] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10809 09:59:54.158138 <4>[ 15.747951] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10810 09:59:54.164960 <6>[ 15.756824] cfg80211: failed to load regulatory.db
10811 09:59:54.208962 <6>[ 15.798700] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10812 09:59:54.215428 <6>[ 15.806206] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10813 09:59:54.240057 <6>[ 15.832834] mt7921e 0000:01:00.0: ASIC revision: 79610010
10814 09:59:54.346287 <4>[ 15.932475] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10815 09:59:54.361543 Begin: Loading essential drivers ... done.
10816 09:59:54.365403 Begin: Running /scripts/init-premount ... done.
10817 09:59:54.371715 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10818 09:59:54.381523 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10819 09:59:54.384781 Device /sys/class/net/enx002432307852 found
10820 09:59:54.385353 done.
10821 09:59:54.435705 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10822 09:59:54.464883 <4>[ 16.051747] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10823 09:59:54.583497 <4>[ 16.170310] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10824 09:59:54.699536 <4>[ 16.286179] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10825 09:59:54.815716 <4>[ 16.402119] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10826 09:59:54.931490 <4>[ 16.518084] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10827 09:59:55.047639 <4>[ 16.634049] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10828 09:59:55.164313 <4>[ 16.749963] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10829 09:59:55.279162 <4>[ 16.865893] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10830 09:59:55.395547 <4>[ 16.981827] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10831 09:59:55.458768 <6>[ 17.051489] r8152 2-1.3:1.0 enx002432307852: carrier on
10832 09:59:55.503294 <3>[ 17.095779] mt7921e 0000:01:00.0: hardware init failed
10833 09:59:55.564200 IP-Config: no response after 2 secs - giving up
10834 09:59:55.619877 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10835 09:59:55.623205 IP-Config: enx002432307852 complete (dhcp from 192.168.201.1):
10836 09:59:55.629908 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10837 09:59:55.636320 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10838 09:59:55.642962 host : mt8192-asurada-spherion-r0-cbg-3
10839 09:59:55.649562 domain : lava-rack
10840 09:59:55.652805 rootserver: 192.168.201.1 rootpath:
10841 09:59:55.655957 filename :
10842 09:59:55.754554 done.
10843 09:59:55.762595 Begin: Running /scripts/nfs-bottom ... done.
10844 09:59:55.785916 Begin: Running /scripts/init-bottom ... done.
10845 09:59:57.027797 <6>[ 18.621302] NET: Registered PF_INET6 protocol family
10846 09:59:57.034607 <6>[ 18.628696] Segment Routing with IPv6
10847 09:59:57.038089 <6>[ 18.632674] In-situ OAM (IOAM) with IPv6
10848 09:59:57.155180 <30>[ 18.728803] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10849 09:59:57.158222 <30>[ 18.753291] systemd[1]: Detected architecture arm64.
10850 09:59:57.180489
10851 09:59:57.183715 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10852 09:59:57.183825
10853 09:59:57.206119 <30>[ 18.799704] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10854 09:59:58.072549 <30>[ 19.662966] systemd[1]: Queued start job for default target Graphical Interface.
10855 09:59:58.105660 <30>[ 19.699618] systemd[1]: Created slice system-getty.slice.
10856 09:59:58.112315 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10857 09:59:58.128767 <30>[ 19.722623] systemd[1]: Created slice system-modprobe.slice.
10858 09:59:58.135381 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10859 09:59:58.152552 <30>[ 19.746436] systemd[1]: Created slice system-serial\x2dgetty.slice.
10860 09:59:58.162388 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10861 09:59:58.176402 <30>[ 19.770246] systemd[1]: Created slice User and Session Slice.
10862 09:59:58.183127 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10863 09:59:58.203592 <30>[ 19.794047] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10864 09:59:58.213324 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10865 09:59:58.231405 <30>[ 19.821964] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10866 09:59:58.237950 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10867 09:59:58.261897 <30>[ 19.849368] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10868 09:59:58.268901 <30>[ 19.861519] systemd[1]: Reached target Local Encrypted Volumes.
10869 09:59:58.275218 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10870 09:59:58.291962 <30>[ 19.885780] systemd[1]: Reached target Paths.
10871 09:59:58.298514 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10872 09:59:58.311240 <30>[ 19.905200] systemd[1]: Reached target Remote File Systems.
10873 09:59:58.318481 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10874 09:59:58.335595 <30>[ 19.929578] systemd[1]: Reached target Slices.
10875 09:59:58.342199 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10876 09:59:58.355386 <30>[ 19.949221] systemd[1]: Reached target Swap.
10877 09:59:58.358417 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10878 09:59:58.378877 <30>[ 19.969649] systemd[1]: Listening on initctl Compatibility Named Pipe.
10879 09:59:58.385659 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10880 09:59:58.392062 <30>[ 19.985849] systemd[1]: Listening on Journal Audit Socket.
10881 09:59:58.398694 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10882 09:59:58.416442 <30>[ 20.010524] systemd[1]: Listening on Journal Socket (/dev/log).
10883 09:59:58.423133 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10884 09:59:58.439607 <30>[ 20.033763] systemd[1]: Listening on Journal Socket.
10885 09:59:58.446257 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10886 09:59:58.461006 <30>[ 20.054745] systemd[1]: Listening on Network Service Netlink Socket.
10887 09:59:58.471084 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10888 09:59:58.486586 <30>[ 20.080277] systemd[1]: Listening on udev Control Socket.
10889 09:59:58.492690 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10890 09:59:58.507558 <30>[ 20.101628] systemd[1]: Listening on udev Kernel Socket.
10891 09:59:58.514357 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10892 09:59:58.555224 <30>[ 20.149244] systemd[1]: Mounting Huge Pages File System...
10893 09:59:58.562167 Mounting [0;1;39mHuge Pages File System[0m...
10894 09:59:58.579507 <30>[ 20.173536] systemd[1]: Mounting POSIX Message Queue File System...
10895 09:59:58.586794 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10896 09:59:58.607560 <30>[ 20.201586] systemd[1]: Mounting Kernel Debug File System...
10897 09:59:58.614412 Mounting [0;1;39mKernel Debug File System[0m...
10898 09:59:58.631130 <30>[ 20.221704] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10899 09:59:58.645167 <30>[ 20.235999] systemd[1]: Starting Create list of static device nodes for the current kernel...
10900 09:59:58.651968 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10901 09:59:58.674064 <30>[ 20.267781] systemd[1]: Starting Load Kernel Module configfs...
10902 09:59:58.680562 Starting [0;1;39mLoad Kernel Module configfs[0m...
10903 09:59:58.702572 <30>[ 20.296528] systemd[1]: Starting Load Kernel Module drm...
10904 09:59:58.709138 Starting [0;1;39mLoad Kernel Module drm[0m...
10905 09:59:58.727652 <30>[ 20.321857] systemd[1]: Starting Load Kernel Module fuse...
10906 09:59:58.734353 Starting [0;1;39mLoad Kernel Module fuse[0m...
10907 09:59:58.771314 <30>[ 20.361854] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10908 09:59:58.778401 <6>[ 20.372402] fuse: init (API version 7.37)
10909 09:59:58.815981 <30>[ 20.409895] systemd[1]: Starting Journal Service...
10910 09:59:58.823042 Starting [0;1;39mJournal Service[0m...
10911 09:59:58.846272 <30>[ 20.439929] systemd[1]: Starting Load Kernel Modules...
10912 09:59:58.852538 Starting [0;1;39mLoad Kernel Modules[0m...
10913 09:59:58.875468 <30>[ 20.466247] systemd[1]: Starting Remount Root and Kernel File Systems...
10914 09:59:58.882472 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10915 09:59:58.900281 <30>[ 20.493423] systemd[1]: Starting Coldplug All udev Devices...
10916 09:59:58.906320 Starting [0;1;39mColdplug All udev Devices[0m...
10917 09:59:58.923100 <30>[ 20.517235] systemd[1]: Mounted Huge Pages File System.
10918 09:59:58.929692 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10919 09:59:58.943572 <30>[ 20.537558] systemd[1]: Mounted POSIX Message Queue File System.
10920 09:59:58.950348 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10921 09:59:58.967984 <30>[ 20.561637] systemd[1]: Mounted Kernel Debug File System.
10922 09:59:58.981665 [[0;32m OK [0m] Mounted [0;1;39mKernel Debu<3>[ 20.571104] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 09:59:58.981754 g File System[0m.
10924 09:59:59.003801 <30>[ 20.594088] systemd[1]: Finished Create list of static device nodes for the current kernel.
10925 09:59:59.017813 [[0;32m OK [0m] Finished [0;1;39mCreate lis<3>[ 20.606504] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10926 09:59:59.021410 t of st… nodes for the current kernel[0m.
10927 09:59:59.036108 <30>[ 20.630064] systemd[1]: modprobe@configfs.service: Succeeded.
10928 09:59:59.043045 <30>[ 20.636855] systemd[1]: Finished Load Kernel Module configfs.
10929 09:59:59.049514 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10930 09:59:59.064255 <30>[ 20.657915] systemd[1]: modprobe@drm.service: Succeeded.
10931 09:59:59.074576 <3>[ 20.658989] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 09:59:59.077541 <30>[ 20.664186] systemd[1]: Finished Load Kernel Module drm.
10933 09:59:59.084280 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10934 09:59:59.102640 <3>[ 20.693277] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 09:59:59.109223 <30>[ 20.694696] systemd[1]: modprobe@fuse.service: Succeeded.
10936 09:59:59.115643 <30>[ 20.708537] systemd[1]: Finished Load Kernel Module fuse.
10937 09:59:59.123127 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10938 09:59:59.133148 <3>[ 20.723282] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10939 09:59:59.139736 <30>[ 20.733406] systemd[1]: Finished Load Kernel Modules.
10940 09:59:59.146208 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10941 09:59:59.161910 <3>[ 20.752688] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10942 09:59:59.172213 <30>[ 20.763219] systemd[1]: Finished Remount Root and Kernel File Systems.
10943 09:59:59.179289 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10944 09:59:59.192696 <3>[ 20.782742] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10945 09:59:59.221844 <3>[ 20.812466] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10946 09:59:59.235169 <30>[ 20.829432] systemd[1]: Mounting FUSE Control File System...
10947 09:59:59.242752 Mounting [0;1;39mFUSE Control File System[0m...
10948 09:59:59.252500 <3>[ 20.842268] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10949 09:59:59.261971 <30>[ 20.856154] systemd[1]: Mounting Kernel Configuration File System...
10950 09:59:59.269156 Mounting [0;1;39mKernel Configuration File System[0m...
10951 09:59:59.287877 <3>[ 20.878255] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 09:59:59.302508 <30>[ 20.893360] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10953 09:59:59.313050 <30>[ 20.902494] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10954 09:59:59.336894 <30>[ 20.930270] systemd[1]: Starting Load/Save Random Seed...
10955 09:59:59.344077 Starting [0;1;39mLoad/Save Random Seed[0m...
10956 09:59:59.360220 <30>[ 20.953779] systemd[1]: Starting Apply Kernel Variables...
10957 09:59:59.366540 Starting [0;1;39mApply Kernel Variables[0m...
10958 09:59:59.393538 <4>[ 20.977347] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10959 09:59:59.400118 <30>[ 20.979038] systemd[1]: Starting Create System Users...
10960 09:59:59.406818 <3>[ 20.993119] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10961 09:59:59.413550 Starting [0;1;39mCreate System Users[0m...
10962 09:59:59.430085 <30>[ 21.023614] systemd[1]: Started Journal Service.
10963 09:59:59.436046 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10964 09:59:59.456739 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10965 09:59:59.471068 See 'systemctl status systemd-udev-trigger.service' for details.
10966 09:59:59.487878 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10967 09:59:59.503983 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10968 09:59:59.521208 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10969 09:59:59.536781 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10970 09:59:59.553045 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10971 09:59:59.595932 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10972 09:59:59.617013 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10973 09:59:59.655598 <46>[ 21.246745] systemd-journald[291]: Received client request to flush runtime journal.
10974 09:59:59.713243 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10975 09:59:59.731918 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10976 09:59:59.747163 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10977 09:59:59.803811 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10978 10:00:01.104525 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10979 10:00:01.164031 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10980 10:00:01.202193 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10981 10:00:01.256945 Starting [0;1;39mNetwork Service[0m...
10982 10:00:01.552261 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10983 10:00:01.575465 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10984 10:00:01.628857 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10985 10:00:01.914651 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10986 10:00:01.934492 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10987 10:00:01.972854 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10988 10:00:01.993412 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10989 10:00:02.022971 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10990 10:00:02.039267 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10991 10:00:02.076309 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10992 10:00:02.123813 Starting [0;1;39mNetwork Name Resolution[0m...
10993 10:00:02.151468 Starting [0;1;39mNetwork Time Synchronization[0m...
10994 10:00:02.173105 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10995 10:00:02.234289 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10996 10:00:02.337849 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10997 10:00:02.359511 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10998 10:00:02.378488 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10999 10:00:02.391029 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11000 10:00:02.406847 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11001 10:00:02.544587 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
11002 10:00:02.583020 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
11003 10:00:02.605281 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
11004 10:00:02.723227 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11005 10:00:02.739045 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11006 10:00:02.995362 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11007 10:00:03.006774 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11008 10:00:03.022852 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11009 10:00:03.063213 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11010 10:00:03.395552 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11011 10:00:03.739493 Starting [0;1;39mUser Login Management[0m...
11012 10:00:03.889792 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11013 10:00:03.906997 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11014 10:00:03.926226 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11015 10:00:03.980426 Starting [0;1;39mPermit User Sessions[0m...
11016 10:00:04.003755 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11017 10:00:04.116221 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11018 10:00:04.132468 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11019 10:00:04.176758 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11020 10:00:04.224049 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11021 10:00:04.242134 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11022 10:00:04.256908 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11023 10:00:04.276667 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11024 10:00:04.337123 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11025 10:00:04.411841 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11026 10:00:04.480518
11027 10:00:04.480640
11028 10:00:04.483974 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11029 10:00:04.484060
11030 10:00:04.487557 debian-bullseye-arm64 login: root (automatic login)
11031 10:00:04.487643
11032 10:00:04.487729
11033 10:00:04.866582 Linux debian-bullseye-arm64 6.1.62-cip9 #1 SMP PREEMPT Fri Nov 24 09:44:51 UTC 2023 aarch64
11034 10:00:04.866725
11035 10:00:04.873490 The programs included with the Debian GNU/Linux system are free software;
11036 10:00:04.880021 the exact distribution terms for each program are described in the
11037 10:00:04.883281 individual files in /usr/share/doc/*/copyright.
11038 10:00:04.883367
11039 10:00:04.890057 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11040 10:00:04.893479 permitted by applicable law.
11041 10:00:05.788463 Matched prompt #10: / #
11043 10:00:05.788772 Setting prompt string to ['/ #']
11044 10:00:05.788889 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11046 10:00:05.789119 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11047 10:00:05.789251 start: 2.2.6 expect-shell-connection (timeout 00:03:16) [common]
11048 10:00:05.789355 Setting prompt string to ['/ #']
11049 10:00:05.789453 Forcing a shell prompt, looking for ['/ #']
11051 10:00:05.839716 / #
11052 10:00:05.839824 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11053 10:00:05.839958 Waiting using forced prompt support (timeout 00:02:30)
11054 10:00:05.844311
11055 10:00:05.844595 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11056 10:00:05.844705 start: 2.2.7 export-device-env (timeout 00:03:16) [common]
11058 10:00:05.945054 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12073277/extract-nfsrootfs-vxspfp2o'
11059 10:00:05.950372 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12073277/extract-nfsrootfs-vxspfp2o'
11061 10:00:06.050928 / # export NFS_SERVER_IP='192.168.201.1'
11062 10:00:06.055986 export NFS_SERVER_IP='192.168.201.1'
11063 10:00:06.056277 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11064 10:00:06.056392 end: 2.2 depthcharge-retry (duration 00:01:44) [common]
11065 10:00:06.056502 end: 2 depthcharge-action (duration 00:01:44) [common]
11066 10:00:06.056612 start: 3 lava-test-retry (timeout 00:07:22) [common]
11067 10:00:06.056719 start: 3.1 lava-test-shell (timeout 00:07:22) [common]
11068 10:00:06.056807 Using namespace: common
11070 10:00:06.157144 / # #
11071 10:00:06.157267 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11072 10:00:06.162143 #
11073 10:00:06.162444 Using /lava-12073277
11075 10:00:06.262792 / # export SHELL=/bin/bash
11076 10:00:06.268164 export SHELL=/bin/bash
11078 10:00:06.368692 / # . /lava-12073277/environment
11079 10:00:06.374166 . /lava-12073277/environment
11081 10:00:06.481036 / # /lava-12073277/bin/lava-test-runner /lava-12073277/0
11082 10:00:06.481166 Test shell timeout: 10s (minimum of the action and connection timeout)
11083 10:00:06.485981 /lava-12073277/bin/lava-test-runner /lava-12073277/0
11084 10:00:06.829932 + export TESTRUN_ID=0_timesync-off
11085 10:00:06.833567 + TESTRUN_ID=0_timesync-off
11086 10:00:06.836788 + cd /lava-12073277/0/tests/0_timesync-off
11087 10:00:06.840011 ++ cat uuid
11088 10:00:06.850124 + UUID=12073277_1.6.2.3.1
11089 10:00:06.850585 + set +x
11090 10:00:06.856393 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12073277_1.6.2.3.1>
11091 10:00:06.857118 Received signal: <STARTRUN> 0_timesync-off 12073277_1.6.2.3.1
11092 10:00:06.857489 Starting test lava.0_timesync-off (12073277_1.6.2.3.1)
11093 10:00:06.857910 Skipping test definition patterns.
11094 10:00:06.859463 + systemctl stop systemd-timesyncd
11095 10:00:06.928126 + set +x
11096 10:00:06.931579 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12073277_1.6.2.3.1>
11097 10:00:06.932284 Received signal: <ENDRUN> 0_timesync-off 12073277_1.6.2.3.1
11098 10:00:06.932737 Ending use of test pattern.
11099 10:00:06.933125 Ending test lava.0_timesync-off (12073277_1.6.2.3.1), duration 0.08
11101 10:00:07.039420 + export TESTRUN_ID=1_kselftest-tpm2
11102 10:00:07.043232 + TESTRUN_ID=1_kselftest-tpm2
11103 10:00:07.046392 + cd /lava-12073277/0/tests/1_kselftest-tpm2
11104 10:00:07.049570 ++ cat uuid
11105 10:00:07.058581 + UUID=12073277_1.6.2.3.5
11106 10:00:07.059308 + set +x
11107 10:00:07.065227 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 12073277_1.6.2.3.5>
11108 10:00:07.065905 Received signal: <STARTRUN> 1_kselftest-tpm2 12073277_1.6.2.3.5
11109 10:00:07.066257 Starting test lava.1_kselftest-tpm2 (12073277_1.6.2.3.5)
11110 10:00:07.066640 Skipping test definition patterns.
11111 10:00:07.068376 + cd ./automated/linux/kselftest/
11112 10:00:07.095129 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11113 10:00:07.170962 INFO: install_deps skipped
11114 10:00:07.307222 --2023-11-24 10:00:07-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11115 10:00:07.323669 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11116 10:00:07.456477 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11117 10:00:07.589673 HTTP request sent, awaiting response... 200 OK
11118 10:00:07.593190 Length: 2964448 (2.8M) [application/octet-stream]
11119 10:00:07.596058 Saving to: 'kselftest.tar.xz'
11120 10:00:07.596148
11121 10:00:07.596220
11122 10:00:07.855792 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11123 10:00:08.122597 kselftest.tar.xz 1%[ ] 47.81K 181KB/s
11124 10:00:08.435295 kselftest.tar.xz 7%[> ] 219.84K 414KB/s
11125 10:00:08.762102 kselftest.tar.xz 27%[====> ] 801.50K 949KB/s
11126 10:00:08.841697 kselftest.tar.xz 68%[============> ] 1.93M 1.65MB/s
11127 10:00:08.848662 kselftest.tar.xz 100%[===================>] 2.83M 2.26MB/s in 1.3s
11128 10:00:08.848755
11129 10:00:09.106523 2023-11-24 10:00:09 (2.26 MB/s) - 'kselftest.tar.xz' saved [2964448/2964448]
11130 10:00:09.106661
11131 10:00:15.922967 skiplist:
11132 10:00:15.926650 ========================================
11133 10:00:15.929696 ========================================
11134 10:00:15.989123 tpm2:test_smoke.sh
11135 10:00:15.992391 tpm2:test_space.sh
11136 10:00:16.012740 ============== Tests to run ===============
11137 10:00:16.016885 tpm2:test_smoke.sh
11138 10:00:16.020269 tpm2:test_space.sh
11139 10:00:16.023941 ===========End Tests to run ===============
11140 10:00:16.027188 shardfile-tpm2 pass
11141 10:00:16.163026 <12>[ 37.758632] kselftest: Running tests in tpm2
11142 10:00:16.176046 TAP version 13
11143 10:00:16.192444 1..2
11144 10:00:16.236593 # selftests: tpm2: test_smoke.sh
11145 10:00:17.763296 # test_read_partial_overwrite (tpm2_tests.SmokeTest) ... ERROR
11146 10:00:17.766480 # test_read_partial_resp (tpm2_tests.SmokeTest) ... ERROR
11147 10:00:17.773317 # Exception ignored in: <function Client.__del__ at 0xffffac9c4d30>
11148 10:00:17.776265 # Traceback (most recent call last):
11149 10:00:17.786660 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11150 10:00:17.787132 # if self.tpm:
11151 10:00:17.792977 # AttributeError: 'Client' object has no attribute 'tpm'
11152 10:00:17.796839 # test_seal_with_auth (tpm2_tests.SmokeTest) ... ERROR
11153 10:00:17.802975 # Exception ignored in: <function Client.__del__ at 0xffffac9c4d30>
11154 10:00:17.806571 # Traceback (most recent call last):
11155 10:00:17.816271 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11156 10:00:17.819818 # if self.tpm:
11157 10:00:17.823131 # AttributeError: 'Client' object has no attribute 'tpm'
11158 10:00:17.829738 # test_seal_with_policy (tpm2_tests.SmokeTest) ... ERROR
11159 10:00:17.833130 # Exception ignored in: <function Client.__del__ at 0xffffac9c4d30>
11160 10:00:17.836439 # Traceback (most recent call last):
11161 10:00:17.846817 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11162 10:00:17.850179 # if self.tpm:
11163 10:00:17.853259 # AttributeError: 'Client' object has no attribute 'tpm'
11164 10:00:17.859851 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest) ... ERROR
11165 10:00:17.866678 # Exception ignored in: <function Client.__del__ at 0xffffac9c4d30>
11166 10:00:17.870259 # Traceback (most recent call last):
11167 10:00:17.879889 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11168 10:00:17.880309 # if self.tpm:
11169 10:00:17.886999 # AttributeError: 'Client' object has no attribute 'tpm'
11170 10:00:17.889837 # test_send_two_cmds (tpm2_tests.SmokeTest) ... ERROR
11171 10:00:17.896903 # Exception ignored in: <function Client.__del__ at 0xffffac9c4d30>
11172 10:00:17.900339 # Traceback (most recent call last):
11173 10:00:17.910365 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11174 10:00:17.910797 # if self.tpm:
11175 10:00:17.917011 # AttributeError: 'Client' object has no attribute 'tpm'
11176 10:00:17.920376 # test_too_short_cmd (tpm2_tests.SmokeTest) ... ERROR
11177 10:00:17.926672 # Exception ignored in: <function Client.__del__ at 0xffffac9c4d30>
11178 10:00:17.930089 # Traceback (most recent call last):
11179 10:00:17.940517 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11180 10:00:17.943932 # if self.tpm:
11181 10:00:17.946767 # AttributeError: 'Client' object has no attribute 'tpm'
11182 10:00:17.953997 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest) ... ERROR
11183 10:00:17.960310 # Exception ignored in: <function Client.__del__ at 0xffffac9c4d30>
11184 10:00:17.963761 # Traceback (most recent call last):
11185 10:00:17.973620 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11186 10:00:17.974043 # if self.tpm:
11187 10:00:17.980290 # AttributeError: 'Client' object has no attribute 'tpm'
11188 10:00:17.983636 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest) ... ERROR
11189 10:00:17.990536 # Exception ignored in: <function Client.__del__ at 0xffffac9c4d30>
11190 10:00:17.993575 # Traceback (most recent call last):
11191 10:00:18.003971 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11192 10:00:18.004391 # if self.tpm:
11193 10:00:18.010262 # AttributeError: 'Client' object has no attribute 'tpm'
11194 10:00:18.010734 #
11195 10:00:18.017199 # ======================================================================
11196 10:00:18.023845 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest)
11197 10:00:18.030814 # ----------------------------------------------------------------------
11198 10:00:18.031251 # Traceback (most recent call last):
11199 10:00:18.043702 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11200 10:00:18.047636 # self.root_key = self.client.create_root_key()
11201 10:00:18.057334 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11202 10:00:18.063674 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11203 10:00:18.073824 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11204 10:00:18.077356 # raise ProtocolError(cc, rc)
11205 10:00:18.080522 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11206 10:00:18.083649 #
11207 10:00:18.087406 # ======================================================================
11208 10:00:18.093863 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest)
11209 10:00:18.100339 # ----------------------------------------------------------------------
11210 10:00:18.107393 # Traceback (most recent call last):
11211 10:00:18.115553 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11212 10:00:18.116022 # self.client = tpm2.Client()
11213 10:00:18.125927 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11214 10:00:18.132553 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11215 10:00:18.135598 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11216 10:00:18.136017 #
11217 10:00:18.142616 # ======================================================================
11218 10:00:18.148916 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest)
11219 10:00:18.152265 # ----------------------------------------------------------------------
11220 10:00:18.155908 # Traceback (most recent call last):
11221 10:00:18.165790 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11222 10:00:18.169253 # self.client = tpm2.Client()
11223 10:00:18.179556 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11224 10:00:18.185682 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11225 10:00:18.189723 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11226 10:00:18.190146 #
11227 10:00:18.195904 # ======================================================================
11228 10:00:18.202943 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest)
11229 10:00:18.209507 # ----------------------------------------------------------------------
11230 10:00:18.212604 # Traceback (most recent call last):
11231 10:00:18.222639 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11232 10:00:18.225556 # self.client = tpm2.Client()
11233 10:00:18.235626 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11234 10:00:18.239075 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11235 10:00:18.245503 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11236 10:00:18.245990 #
11237 10:00:18.252855 # ======================================================================
11238 10:00:18.256007 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest)
11239 10:00:18.262535 # ----------------------------------------------------------------------
11240 10:00:18.266001 # Traceback (most recent call last):
11241 10:00:18.276027 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11242 10:00:18.279231 # self.client = tpm2.Client()
11243 10:00:18.289373 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11244 10:00:18.295823 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11245 10:00:18.299577 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11246 10:00:18.300006 #
11247 10:00:18.305912 # ======================================================================
11248 10:00:18.309596 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest)
11249 10:00:18.316246 # ----------------------------------------------------------------------
11250 10:00:18.319344 # Traceback (most recent call last):
11251 10:00:18.329442 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11252 10:00:18.332944 # self.client = tpm2.Client()
11253 10:00:18.343031 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11254 10:00:18.349410 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11255 10:00:18.352835 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11256 10:00:18.353288 #
11257 10:00:18.359828 # ======================================================================
11258 10:00:18.366505 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest)
11259 10:00:18.372636 # ----------------------------------------------------------------------
11260 10:00:18.376563 # Traceback (most recent call last):
11261 10:00:18.386298 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11262 10:00:18.386984 # self.client = tpm2.Client()
11263 10:00:18.396208 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11264 10:00:18.402800 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11265 10:00:18.406516 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11266 10:00:18.409568 #
11267 10:00:18.413115 # ======================================================================
11268 10:00:18.419822 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest)
11269 10:00:18.426372 # ----------------------------------------------------------------------
11270 10:00:18.429582 # Traceback (most recent call last):
11271 10:00:18.440736 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11272 10:00:18.444085 # self.client = tpm2.Client()
11273 10:00:18.451384 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11274 10:00:18.458914 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11275 10:00:18.461304 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11276 10:00:18.461728 #
11277 10:00:18.469443 # ======================================================================
11278 10:00:18.473447 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest)
11279 10:00:18.480209 # ----------------------------------------------------------------------
11280 10:00:18.483797 # Traceback (most recent call last):
11281 10:00:18.494787 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11282 10:00:18.498081 # self.client = tpm2.Client()
11283 10:00:18.508862 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11284 10:00:18.512399 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11285 10:00:18.517359 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11286 10:00:18.517792 #
11287 10:00:18.523949 # ----------------------------------------------------------------------
11288 10:00:18.527445 # Ran 9 tests in 0.040s
11289 10:00:18.527864 #
11290 10:00:18.528194 # FAILED (errors=9)
11291 10:00:18.534287 # test_async (tpm2_tests.AsyncTest) ... ok
11292 10:00:18.537320 # test_flush_invalid_context (tpm2_tests.AsyncTest) ... ok
11293 10:00:18.537740 #
11294 10:00:18.544233 # ----------------------------------------------------------------------
11295 10:00:18.547376 # Ran 2 tests in 0.034s
11296 10:00:18.547905 #
11297 10:00:18.548252 # OK
11298 10:00:18.551033 ok 1 selftests: tpm2: test_smoke.sh
11299 10:00:18.554135 # selftests: tpm2: test_space.sh
11300 10:00:18.557549 # test_flush_context (tpm2_tests.SpaceTest) ... ERROR
11301 10:00:18.563925 # test_get_handles (tpm2_tests.SpaceTest) ... ERROR
11302 10:00:18.567411 # test_invalid_cc (tpm2_tests.SpaceTest) ... ERROR
11303 10:00:18.574208 # test_make_two_spaces (tpm2_tests.SpaceTest) ... ERROR
11304 10:00:18.574754 #
11305 10:00:18.580685 # ======================================================================
11306 10:00:18.584375 # ERROR: test_flush_context (tpm2_tests.SpaceTest)
11307 10:00:18.591170 # ----------------------------------------------------------------------
11308 10:00:18.595176 # Traceback (most recent call last):
11309 10:00:18.604299 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11310 10:00:18.607576 # root1 = space1.create_root_key()
11311 10:00:18.618067 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11312 10:00:18.624139 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11313 10:00:18.634319 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11314 10:00:18.637420 # raise ProtocolError(cc, rc)
11315 10:00:18.644198 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11316 10:00:18.644640 #
11317 10:00:18.650800 # ======================================================================
11318 10:00:18.654260 # ERROR: test_get_handles (tpm2_tests.SpaceTest)
11319 10:00:18.660772 # ----------------------------------------------------------------------
11320 10:00:18.664116 # Traceback (most recent call last):
11321 10:00:18.674533 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11322 10:00:18.677565 # space1.create_root_key()
11323 10:00:18.687711 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11324 10:00:18.694600 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11325 10:00:18.704793 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11326 10:00:18.708048 # raise ProtocolError(cc, rc)
11327 10:00:18.714605 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11328 10:00:18.715066 #
11329 10:00:18.721379 # ======================================================================
11330 10:00:18.724799 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest)
11331 10:00:18.731229 # ----------------------------------------------------------------------
11332 10:00:18.734719 # Traceback (most recent call last):
11333 10:00:18.744541 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11334 10:00:18.747599 # root1 = space1.create_root_key()
11335 10:00:18.757591 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11336 10:00:18.764220 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11337 10:00:18.774555 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11338 10:00:18.777528 # raise ProtocolError(cc, rc)
11339 10:00:18.784169 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11340 10:00:18.784250 #
11341 10:00:18.790954 # ======================================================================
11342 10:00:18.794572 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest)
11343 10:00:18.801080 # ----------------------------------------------------------------------
11344 10:00:18.804230 # Traceback (most recent call last):
11345 10:00:18.814178 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11346 10:00:18.817670 # root1 = space1.create_root_key()
11347 10:00:18.827833 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11348 10:00:18.834513 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11349 10:00:18.844325 # File "/lava-12073277/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11350 10:00:18.847593 # raise ProtocolError(cc, rc)
11351 10:00:18.854430 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11352 10:00:18.854511 #
11353 10:00:18.861422 # ----------------------------------------------------------------------
11354 10:00:18.861508 # Ran 4 tests in 0.097s
11355 10:00:18.864633 #
11356 10:00:18.864725 # FAILED (errors=4)
11357 10:00:18.867964 not ok 2 selftests: tpm2: test_space.sh # exit=1
11358 10:00:18.871083 tpm2_test_smoke_sh pass
11359 10:00:18.874587 tpm2_test_space_sh fail
11360 10:00:18.878355 + ../../utils/send-to-lava.sh ./output/result.txt
11361 10:00:18.885087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-tpm2 RESULT=pass>
11362 10:00:18.885854 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-tpm2 RESULT=pass
11364 10:00:18.888553 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11366 10:00:18.891220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11367 10:00:18.953797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11368 10:00:18.954537 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11370 10:00:18.957105 + set +x
11371 10:00:18.960483 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 12073277_1.6.2.3.5>
11372 10:00:18.961156 Received signal: <ENDRUN> 1_kselftest-tpm2 12073277_1.6.2.3.5
11373 10:00:18.961538 Ending use of test pattern.
11374 10:00:18.961853 Ending test lava.1_kselftest-tpm2 (12073277_1.6.2.3.5), duration 11.90
11376 10:00:18.963387 <LAVA_TEST_RUNNER EXIT>
11377 10:00:18.964058 ok: lava_test_shell seems to have completed
11378 10:00:18.964856 shardfile-tpm2: pass
tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11379 10:00:18.965298 end: 3.1 lava-test-shell (duration 00:00:13) [common]
11380 10:00:18.965724 end: 3 lava-test-retry (duration 00:00:13) [common]
11381 10:00:18.966154 start: 4 finalize (timeout 00:07:09) [common]
11382 10:00:18.966595 start: 4.1 power-off (timeout 00:00:30) [common]
11383 10:00:18.967397 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11384 10:00:19.052755 >> Command sent successfully.
11385 10:00:19.057394 Returned 0 in 0 seconds
11386 10:00:19.158142 end: 4.1 power-off (duration 00:00:00) [common]
11388 10:00:19.158976 start: 4.2 read-feedback (timeout 00:07:08) [common]
11389 10:00:19.159758 Listened to connection for namespace 'common' for up to 1s
11390 10:00:20.160540 Finalising connection for namespace 'common'
11391 10:00:20.160961 Disconnecting from shell: Finalise
11392 10:00:20.161244 / #
11393 10:00:20.261735 end: 4.2 read-feedback (duration 00:00:01) [common]
11394 10:00:20.261918 end: 4 finalize (duration 00:00:01) [common]
11395 10:00:20.262062 Cleaning after the job
11396 10:00:20.262172 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073277/tftp-deploy-4j2yyqmd/ramdisk
11397 10:00:20.265048 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073277/tftp-deploy-4j2yyqmd/kernel
11398 10:00:20.277249 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073277/tftp-deploy-4j2yyqmd/dtb
11399 10:00:20.277440 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073277/tftp-deploy-4j2yyqmd/nfsrootfs
11400 10:00:20.368058 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073277/tftp-deploy-4j2yyqmd/modules
11401 10:00:20.375348 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12073277
11402 10:00:21.016649 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12073277
11403 10:00:21.016835 Job finished correctly