Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 34
- Kernel Warnings: 27
- Boot result: PASS
- Errors: 0
1 09:56:18.289327 lava-dispatcher, installed at version: 2023.10
2 09:56:18.289549 start: 0 validate
3 09:56:18.289690 Start time: 2023-11-24 09:56:18.289680+00:00 (UTC)
4 09:56:18.289815 Using caching service: 'http://localhost/cache/?uri=%s'
5 09:56:18.289947 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 09:56:18.563124 Using caching service: 'http://localhost/cache/?uri=%s'
7 09:56:18.563305 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 09:56:52.087849 Using caching service: 'http://localhost/cache/?uri=%s'
9 09:56:52.088663 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 09:56:52.358177 Using caching service: 'http://localhost/cache/?uri=%s'
11 09:56:52.358914 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 09:56:52.883071 Using caching service: 'http://localhost/cache/?uri=%s'
13 09:56:52.883810 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 09:57:01.398116 validate duration: 43.11
16 09:57:01.399358 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 09:57:01.399905 start: 1.1 download-retry (timeout 00:10:00) [common]
18 09:57:01.400432 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 09:57:01.401171 Not decompressing ramdisk as can be used compressed.
20 09:57:01.401664 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230623.0/arm64/initrd.cpio.gz
21 09:57:01.402157 saving as /var/lib/lava/dispatcher/tmp/12073290/tftp-deploy-zjenkfgv/ramdisk/initrd.cpio.gz
22 09:57:01.402580 total size: 4665398 (4 MB)
23 09:57:01.673600 progress 0 % (0 MB)
24 09:57:01.674963 progress 5 % (0 MB)
25 09:57:01.676214 progress 10 % (0 MB)
26 09:57:01.677917 progress 15 % (0 MB)
27 09:57:01.679284 progress 20 % (0 MB)
28 09:57:01.680659 progress 25 % (1 MB)
29 09:57:01.681918 progress 30 % (1 MB)
30 09:57:01.683282 progress 35 % (1 MB)
31 09:57:01.684642 progress 40 % (1 MB)
32 09:57:01.686029 progress 45 % (2 MB)
33 09:57:01.687382 progress 50 % (2 MB)
34 09:57:01.688710 progress 55 % (2 MB)
35 09:57:01.689960 progress 60 % (2 MB)
36 09:57:01.691231 progress 65 % (2 MB)
37 09:57:01.692576 progress 70 % (3 MB)
38 09:57:01.693884 progress 75 % (3 MB)
39 09:57:01.695169 progress 80 % (3 MB)
40 09:57:01.696650 progress 85 % (3 MB)
41 09:57:01.698078 progress 90 % (4 MB)
42 09:57:01.699333 progress 95 % (4 MB)
43 09:57:01.700668 progress 100 % (4 MB)
44 09:57:01.700827 4 MB downloaded in 0.30 s (14.92 MB/s)
45 09:57:01.700988 end: 1.1.1 http-download (duration 00:00:00) [common]
47 09:57:01.701222 end: 1.1 download-retry (duration 00:00:00) [common]
48 09:57:01.701306 start: 1.2 download-retry (timeout 00:10:00) [common]
49 09:57:01.701391 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 09:57:01.701595 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 09:57:01.701673 saving as /var/lib/lava/dispatcher/tmp/12073290/tftp-deploy-zjenkfgv/kernel/Image
52 09:57:01.701735 total size: 49107456 (46 MB)
53 09:57:01.701795 No compression specified
54 09:57:01.702985 progress 0 % (0 MB)
55 09:57:01.716757 progress 5 % (2 MB)
56 09:57:01.729976 progress 10 % (4 MB)
57 09:57:01.743308 progress 15 % (7 MB)
58 09:57:01.756397 progress 20 % (9 MB)
59 09:57:01.769735 progress 25 % (11 MB)
60 09:57:01.783055 progress 30 % (14 MB)
61 09:57:01.796408 progress 35 % (16 MB)
62 09:57:01.809812 progress 40 % (18 MB)
63 09:57:01.823604 progress 45 % (21 MB)
64 09:57:01.836964 progress 50 % (23 MB)
65 09:57:01.850265 progress 55 % (25 MB)
66 09:57:01.863833 progress 60 % (28 MB)
67 09:57:01.877231 progress 65 % (30 MB)
68 09:57:01.890829 progress 70 % (32 MB)
69 09:57:01.903923 progress 75 % (35 MB)
70 09:57:01.917218 progress 80 % (37 MB)
71 09:57:01.930643 progress 85 % (39 MB)
72 09:57:01.944660 progress 90 % (42 MB)
73 09:57:01.957867 progress 95 % (44 MB)
74 09:57:01.970799 progress 100 % (46 MB)
75 09:57:01.971047 46 MB downloaded in 0.27 s (173.90 MB/s)
76 09:57:01.971205 end: 1.2.1 http-download (duration 00:00:00) [common]
78 09:57:01.971431 end: 1.2 download-retry (duration 00:00:00) [common]
79 09:57:01.971522 start: 1.3 download-retry (timeout 00:09:59) [common]
80 09:57:01.971606 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 09:57:01.971747 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 09:57:01.971815 saving as /var/lib/lava/dispatcher/tmp/12073290/tftp-deploy-zjenkfgv/dtb/mt8192-asurada-spherion-r0.dtb
83 09:57:01.971874 total size: 47278 (0 MB)
84 09:57:01.971934 No compression specified
85 09:57:01.973041 progress 69 % (0 MB)
86 09:57:01.973316 progress 100 % (0 MB)
87 09:57:01.973474 0 MB downloaded in 0.00 s (28.23 MB/s)
88 09:57:01.973597 end: 1.3.1 http-download (duration 00:00:00) [common]
90 09:57:01.973816 end: 1.3 download-retry (duration 00:00:00) [common]
91 09:57:01.973902 start: 1.4 download-retry (timeout 00:09:59) [common]
92 09:57:01.973982 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 09:57:01.974093 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230623.0/arm64/full.rootfs.tar.xz
94 09:57:01.974159 saving as /var/lib/lava/dispatcher/tmp/12073290/tftp-deploy-zjenkfgv/nfsrootfs/full.rootfs.tar
95 09:57:01.974218 total size: 89451516 (85 MB)
96 09:57:01.974278 Using unxz to decompress xz
97 09:57:01.978636 progress 0 % (0 MB)
98 09:57:02.193490 progress 5 % (4 MB)
99 09:57:02.415959 progress 10 % (8 MB)
100 09:57:02.675954 progress 15 % (12 MB)
101 09:57:02.875324 progress 20 % (17 MB)
102 09:57:02.972949 progress 25 % (21 MB)
103 09:57:03.229416 progress 30 % (25 MB)
104 09:57:03.524450 progress 35 % (29 MB)
105 09:57:03.791399 progress 40 % (34 MB)
106 09:57:04.060277 progress 45 % (38 MB)
107 09:57:04.311994 progress 50 % (42 MB)
108 09:57:04.581774 progress 55 % (46 MB)
109 09:57:04.838437 progress 60 % (51 MB)
110 09:57:05.109030 progress 65 % (55 MB)
111 09:57:05.404467 progress 70 % (59 MB)
112 09:57:05.709627 progress 75 % (64 MB)
113 09:57:06.009485 progress 80 % (68 MB)
114 09:57:06.268226 progress 85 % (72 MB)
115 09:57:06.508384 progress 90 % (76 MB)
116 09:57:06.781500 progress 95 % (81 MB)
117 09:57:07.056709 progress 100 % (85 MB)
118 09:57:07.062902 85 MB downloaded in 5.09 s (16.76 MB/s)
119 09:57:07.063178 end: 1.4.1 http-download (duration 00:00:05) [common]
121 09:57:07.063477 end: 1.4 download-retry (duration 00:00:05) [common]
122 09:57:07.063569 start: 1.5 download-retry (timeout 00:09:54) [common]
123 09:57:07.063656 start: 1.5.1 http-download (timeout 00:09:54) [common]
124 09:57:07.063818 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 09:57:07.063891 saving as /var/lib/lava/dispatcher/tmp/12073290/tftp-deploy-zjenkfgv/modules/modules.tar
126 09:57:07.063953 total size: 8622040 (8 MB)
127 09:57:07.064048 Using unxz to decompress xz
128 09:57:07.333013 progress 0 % (0 MB)
129 09:57:07.354800 progress 5 % (0 MB)
130 09:57:07.379677 progress 10 % (0 MB)
131 09:57:07.404285 progress 15 % (1 MB)
132 09:57:07.429536 progress 20 % (1 MB)
133 09:57:07.454277 progress 25 % (2 MB)
134 09:57:07.480882 progress 30 % (2 MB)
135 09:57:07.507336 progress 35 % (2 MB)
136 09:57:07.531075 progress 40 % (3 MB)
137 09:57:07.555821 progress 45 % (3 MB)
138 09:57:07.581546 progress 50 % (4 MB)
139 09:57:07.606216 progress 55 % (4 MB)
140 09:57:07.631527 progress 60 % (4 MB)
141 09:57:07.659387 progress 65 % (5 MB)
142 09:57:07.685011 progress 70 % (5 MB)
143 09:57:07.708632 progress 75 % (6 MB)
144 09:57:07.735773 progress 80 % (6 MB)
145 09:57:07.762790 progress 85 % (7 MB)
146 09:57:07.789959 progress 90 % (7 MB)
147 09:57:07.821906 progress 95 % (7 MB)
148 09:57:07.853468 progress 100 % (8 MB)
149 09:57:07.858469 8 MB downloaded in 0.79 s (10.35 MB/s)
150 09:57:07.858722 end: 1.5.1 http-download (duration 00:00:01) [common]
152 09:57:07.858985 end: 1.5 download-retry (duration 00:00:01) [common]
153 09:57:07.859080 start: 1.6 prepare-tftp-overlay (timeout 00:09:54) [common]
154 09:57:07.859178 start: 1.6.1 extract-nfsrootfs (timeout 00:09:54) [common]
155 09:57:09.649968 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12073290/extract-nfsrootfs-x41g6wi2
156 09:57:09.650219 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 09:57:09.650320 start: 1.6.2 lava-overlay (timeout 00:09:52) [common]
158 09:57:09.650488 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12073290/lava-overlay-191lhxep
159 09:57:09.650619 makedir: /var/lib/lava/dispatcher/tmp/12073290/lava-overlay-191lhxep/lava-12073290/bin
160 09:57:09.650721 makedir: /var/lib/lava/dispatcher/tmp/12073290/lava-overlay-191lhxep/lava-12073290/tests
161 09:57:09.650818 makedir: /var/lib/lava/dispatcher/tmp/12073290/lava-overlay-191lhxep/lava-12073290/results
162 09:57:09.650919 Creating /var/lib/lava/dispatcher/tmp/12073290/lava-overlay-191lhxep/lava-12073290/bin/lava-add-keys
163 09:57:09.651061 Creating /var/lib/lava/dispatcher/tmp/12073290/lava-overlay-191lhxep/lava-12073290/bin/lava-add-sources
164 09:57:09.651212 Creating /var/lib/lava/dispatcher/tmp/12073290/lava-overlay-191lhxep/lava-12073290/bin/lava-background-process-start
165 09:57:09.651353 Creating /var/lib/lava/dispatcher/tmp/12073290/lava-overlay-191lhxep/lava-12073290/bin/lava-background-process-stop
166 09:57:09.651482 Creating /var/lib/lava/dispatcher/tmp/12073290/lava-overlay-191lhxep/lava-12073290/bin/lava-common-functions
167 09:57:09.651608 Creating /var/lib/lava/dispatcher/tmp/12073290/lava-overlay-191lhxep/lava-12073290/bin/lava-echo-ipv4
168 09:57:09.651734 Creating /var/lib/lava/dispatcher/tmp/12073290/lava-overlay-191lhxep/lava-12073290/bin/lava-install-packages
169 09:57:09.651859 Creating /var/lib/lava/dispatcher/tmp/12073290/lava-overlay-191lhxep/lava-12073290/bin/lava-installed-packages
170 09:57:09.651981 Creating /var/lib/lava/dispatcher/tmp/12073290/lava-overlay-191lhxep/lava-12073290/bin/lava-os-build
171 09:57:09.652105 Creating /var/lib/lava/dispatcher/tmp/12073290/lava-overlay-191lhxep/lava-12073290/bin/lava-probe-channel
172 09:57:09.652236 Creating /var/lib/lava/dispatcher/tmp/12073290/lava-overlay-191lhxep/lava-12073290/bin/lava-probe-ip
173 09:57:09.652362 Creating /var/lib/lava/dispatcher/tmp/12073290/lava-overlay-191lhxep/lava-12073290/bin/lava-target-ip
174 09:57:09.652485 Creating /var/lib/lava/dispatcher/tmp/12073290/lava-overlay-191lhxep/lava-12073290/bin/lava-target-mac
175 09:57:09.652608 Creating /var/lib/lava/dispatcher/tmp/12073290/lava-overlay-191lhxep/lava-12073290/bin/lava-target-storage
176 09:57:09.652733 Creating /var/lib/lava/dispatcher/tmp/12073290/lava-overlay-191lhxep/lava-12073290/bin/lava-test-case
177 09:57:09.652861 Creating /var/lib/lava/dispatcher/tmp/12073290/lava-overlay-191lhxep/lava-12073290/bin/lava-test-event
178 09:57:09.652986 Creating /var/lib/lava/dispatcher/tmp/12073290/lava-overlay-191lhxep/lava-12073290/bin/lava-test-feedback
179 09:57:09.653110 Creating /var/lib/lava/dispatcher/tmp/12073290/lava-overlay-191lhxep/lava-12073290/bin/lava-test-raise
180 09:57:09.653233 Creating /var/lib/lava/dispatcher/tmp/12073290/lava-overlay-191lhxep/lava-12073290/bin/lava-test-reference
181 09:57:09.653357 Creating /var/lib/lava/dispatcher/tmp/12073290/lava-overlay-191lhxep/lava-12073290/bin/lava-test-runner
182 09:57:09.653483 Creating /var/lib/lava/dispatcher/tmp/12073290/lava-overlay-191lhxep/lava-12073290/bin/lava-test-set
183 09:57:09.653608 Creating /var/lib/lava/dispatcher/tmp/12073290/lava-overlay-191lhxep/lava-12073290/bin/lava-test-shell
184 09:57:09.653733 Updating /var/lib/lava/dispatcher/tmp/12073290/lava-overlay-191lhxep/lava-12073290/bin/lava-install-packages (oe)
185 09:57:09.653887 Updating /var/lib/lava/dispatcher/tmp/12073290/lava-overlay-191lhxep/lava-12073290/bin/lava-installed-packages (oe)
186 09:57:09.654008 Creating /var/lib/lava/dispatcher/tmp/12073290/lava-overlay-191lhxep/lava-12073290/environment
187 09:57:09.654109 LAVA metadata
188 09:57:09.654179 - LAVA_JOB_ID=12073290
189 09:57:09.654241 - LAVA_DISPATCHER_IP=192.168.201.1
190 09:57:09.654343 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:52) [common]
191 09:57:09.654407 skipped lava-vland-overlay
192 09:57:09.654478 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 09:57:09.654553 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:52) [common]
194 09:57:09.654612 skipped lava-multinode-overlay
195 09:57:09.654682 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 09:57:09.654758 start: 1.6.2.3 test-definition (timeout 00:09:52) [common]
197 09:57:09.654827 Loading test definitions
198 09:57:09.654914 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:52) [common]
199 09:57:09.654981 Using /lava-12073290 at stage 0
200 09:57:09.655287 uuid=12073290_1.6.2.3.1 testdef=None
201 09:57:09.655373 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 09:57:09.655454 start: 1.6.2.3.2 test-overlay (timeout 00:09:52) [common]
203 09:57:09.655966 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 09:57:09.656537 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:52) [common]
206 09:57:09.657145 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 09:57:09.657368 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:52) [common]
209 09:57:09.657949 runner path: /var/lib/lava/dispatcher/tmp/12073290/lava-overlay-191lhxep/lava-12073290/0/tests/0_lc-compliance test_uuid 12073290_1.6.2.3.1
210 09:57:09.658105 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 09:57:09.658312 Creating lava-test-runner.conf files
213 09:57:09.658373 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12073290/lava-overlay-191lhxep/lava-12073290/0 for stage 0
214 09:57:09.658459 - 0_lc-compliance
215 09:57:09.658553 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 09:57:09.658635 start: 1.6.2.4 compress-overlay (timeout 00:09:52) [common]
217 09:57:09.664735 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 09:57:09.664878 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:52) [common]
219 09:57:09.664991 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 09:57:09.665106 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 09:57:09.665218 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:52) [common]
222 09:57:09.787478 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 09:57:09.787858 start: 1.6.4 extract-modules (timeout 00:09:52) [common]
224 09:57:09.787977 extracting modules file /var/lib/lava/dispatcher/tmp/12073290/tftp-deploy-zjenkfgv/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12073290/extract-nfsrootfs-x41g6wi2
225 09:57:10.015667 extracting modules file /var/lib/lava/dispatcher/tmp/12073290/tftp-deploy-zjenkfgv/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12073290/extract-overlay-ramdisk-jfckl_2r/ramdisk
226 09:57:10.246672 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 09:57:10.246844 start: 1.6.5 apply-overlay-tftp (timeout 00:09:51) [common]
228 09:57:10.246937 [common] Applying overlay to NFS
229 09:57:10.247006 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12073290/compress-overlay-s2jhxutd/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12073290/extract-nfsrootfs-x41g6wi2
230 09:57:10.253542 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 09:57:10.253656 start: 1.6.6 configure-preseed-file (timeout 00:09:51) [common]
232 09:57:10.253742 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 09:57:10.253828 start: 1.6.7 compress-ramdisk (timeout 00:09:51) [common]
234 09:57:10.253909 Building ramdisk /var/lib/lava/dispatcher/tmp/12073290/extract-overlay-ramdisk-jfckl_2r/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12073290/extract-overlay-ramdisk-jfckl_2r/ramdisk
235 09:57:10.586178 >> 119398 blocks
236 09:57:12.537677 rename /var/lib/lava/dispatcher/tmp/12073290/extract-overlay-ramdisk-jfckl_2r/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12073290/tftp-deploy-zjenkfgv/ramdisk/ramdisk.cpio.gz
237 09:57:12.538134 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 09:57:12.538298 start: 1.6.8 prepare-kernel (timeout 00:09:49) [common]
239 09:57:12.538432 start: 1.6.8.1 prepare-fit (timeout 00:09:49) [common]
240 09:57:12.538542 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12073290/tftp-deploy-zjenkfgv/kernel/Image'
241 09:57:25.462116 Returned 0 in 12 seconds
242 09:57:25.562778 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12073290/tftp-deploy-zjenkfgv/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12073290/tftp-deploy-zjenkfgv/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12073290/tftp-deploy-zjenkfgv/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12073290/tftp-deploy-zjenkfgv/kernel/image.itb
243 09:57:25.918860 output: FIT description: Kernel Image image with one or more FDT blobs
244 09:57:25.919240 output: Created: Fri Nov 24 09:57:25 2023
245 09:57:25.919321 output: Image 0 (kernel-1)
246 09:57:25.919384 output: Description:
247 09:57:25.919442 output: Created: Fri Nov 24 09:57:25 2023
248 09:57:25.919501 output: Type: Kernel Image
249 09:57:25.919560 output: Compression: lzma compressed
250 09:57:25.919618 output: Data Size: 11047542 Bytes = 10788.62 KiB = 10.54 MiB
251 09:57:25.919677 output: Architecture: AArch64
252 09:57:25.919733 output: OS: Linux
253 09:57:25.919791 output: Load Address: 0x00000000
254 09:57:25.919849 output: Entry Point: 0x00000000
255 09:57:25.919906 output: Hash algo: crc32
256 09:57:25.919962 output: Hash value: 2edffaa3
257 09:57:25.920018 output: Image 1 (fdt-1)
258 09:57:25.920070 output: Description: mt8192-asurada-spherion-r0
259 09:57:25.920122 output: Created: Fri Nov 24 09:57:25 2023
260 09:57:25.920174 output: Type: Flat Device Tree
261 09:57:25.920238 output: Compression: uncompressed
262 09:57:25.920291 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
263 09:57:25.920343 output: Architecture: AArch64
264 09:57:25.920394 output: Hash algo: crc32
265 09:57:25.920446 output: Hash value: cc4352de
266 09:57:25.920497 output: Image 2 (ramdisk-1)
267 09:57:25.920549 output: Description: unavailable
268 09:57:25.920600 output: Created: Fri Nov 24 09:57:25 2023
269 09:57:25.920652 output: Type: RAMDisk Image
270 09:57:25.920706 output: Compression: Unknown Compression
271 09:57:25.920772 output: Data Size: 17793361 Bytes = 17376.33 KiB = 16.97 MiB
272 09:57:25.920825 output: Architecture: AArch64
273 09:57:25.920876 output: OS: Linux
274 09:57:25.920928 output: Load Address: unavailable
275 09:57:25.920979 output: Entry Point: unavailable
276 09:57:25.921031 output: Hash algo: crc32
277 09:57:25.921082 output: Hash value: eedfe702
278 09:57:25.921133 output: Default Configuration: 'conf-1'
279 09:57:25.921184 output: Configuration 0 (conf-1)
280 09:57:25.921235 output: Description: mt8192-asurada-spherion-r0
281 09:57:25.921286 output: Kernel: kernel-1
282 09:57:25.921337 output: Init Ramdisk: ramdisk-1
283 09:57:25.921387 output: FDT: fdt-1
284 09:57:25.921439 output: Loadables: kernel-1
285 09:57:25.921490 output:
286 09:57:25.921695 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
287 09:57:25.921791 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
288 09:57:25.921896 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
289 09:57:25.921987 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:35) [common]
290 09:57:25.922066 No LXC device requested
291 09:57:25.922146 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 09:57:25.922227 start: 1.8 deploy-device-env (timeout 00:09:35) [common]
293 09:57:25.922302 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 09:57:25.922373 Checking files for TFTP limit of 4294967296 bytes.
295 09:57:25.922879 end: 1 tftp-deploy (duration 00:00:25) [common]
296 09:57:25.922981 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 09:57:25.923071 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 09:57:25.923196 substitutions:
299 09:57:25.923261 - {DTB}: 12073290/tftp-deploy-zjenkfgv/dtb/mt8192-asurada-spherion-r0.dtb
300 09:57:25.923325 - {INITRD}: 12073290/tftp-deploy-zjenkfgv/ramdisk/ramdisk.cpio.gz
301 09:57:25.923383 - {KERNEL}: 12073290/tftp-deploy-zjenkfgv/kernel/Image
302 09:57:25.923439 - {LAVA_MAC}: None
303 09:57:25.923494 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12073290/extract-nfsrootfs-x41g6wi2
304 09:57:25.923549 - {NFS_SERVER_IP}: 192.168.201.1
305 09:57:25.923602 - {PRESEED_CONFIG}: None
306 09:57:25.923655 - {PRESEED_LOCAL}: None
307 09:57:25.923707 - {RAMDISK}: 12073290/tftp-deploy-zjenkfgv/ramdisk/ramdisk.cpio.gz
308 09:57:25.923760 - {ROOT_PART}: None
309 09:57:25.923812 - {ROOT}: None
310 09:57:25.923865 - {SERVER_IP}: 192.168.201.1
311 09:57:25.923917 - {TEE}: None
312 09:57:25.923969 Parsed boot commands:
313 09:57:25.924021 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 09:57:25.924207 Parsed boot commands: tftpboot 192.168.201.1 12073290/tftp-deploy-zjenkfgv/kernel/image.itb 12073290/tftp-deploy-zjenkfgv/kernel/cmdline
315 09:57:25.924296 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 09:57:25.924381 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 09:57:25.924473 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 09:57:25.924557 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 09:57:25.924628 Not connected, no need to disconnect.
320 09:57:25.924737 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 09:57:25.924821 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 09:57:25.924890 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
323 09:57:25.929086 Setting prompt string to ['lava-test: # ']
324 09:57:25.929462 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 09:57:25.929568 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 09:57:25.929669 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 09:57:25.929757 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 09:57:25.929989 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
329 09:57:31.069672 >> Command sent successfully.
330 09:57:31.072005 Returned 0 in 5 seconds
331 09:57:31.172358 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 09:57:31.172680 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 09:57:31.172778 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 09:57:31.172859 Setting prompt string to 'Starting depthcharge on Spherion...'
336 09:57:31.172927 Changing prompt to 'Starting depthcharge on Spherion...'
337 09:57:31.172995 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 09:57:31.173262 [Enter `^Ec?' for help]
339 09:57:31.346644
340 09:57:31.346806
341 09:57:31.346878 F0: 102B 0000
342 09:57:31.346942
343 09:57:31.347002 F3: 1001 0000 [0200]
344 09:57:31.347060
345 09:57:31.349983 F3: 1001 0000
346 09:57:31.350065
347 09:57:31.350130 F7: 102D 0000
348 09:57:31.350190
349 09:57:31.350248 F1: 0000 0000
350 09:57:31.350304
351 09:57:31.353379 V0: 0000 0000 [0001]
352 09:57:31.353461
353 09:57:31.353526 00: 0007 8000
354 09:57:31.353591
355 09:57:31.356990 01: 0000 0000
356 09:57:31.357073
357 09:57:31.357140 BP: 0C00 0209 [0000]
358 09:57:31.357200
359 09:57:31.361455 G0: 1182 0000
360 09:57:31.361536
361 09:57:31.361600 EC: 0000 0021 [4000]
362 09:57:31.361660
363 09:57:31.364421 S7: 0000 0000 [0000]
364 09:57:31.364502
365 09:57:31.364566 CC: 0000 0000 [0001]
366 09:57:31.364626
367 09:57:31.368000 T0: 0000 0040 [010F]
368 09:57:31.368082
369 09:57:31.368146 Jump to BL
370 09:57:31.368215
371 09:57:31.392724
372 09:57:31.392827
373 09:57:31.392893
374 09:57:31.400440 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
375 09:57:31.404366 ARM64: Exception handlers installed.
376 09:57:31.407844 ARM64: Testing exception
377 09:57:31.407926 ARM64: Done test exception
378 09:57:31.418822 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
379 09:57:31.425548 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
380 09:57:31.432971 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
381 09:57:31.443496 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
382 09:57:31.450074 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
383 09:57:31.460371 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
384 09:57:31.471568 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
385 09:57:31.478408 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
386 09:57:31.495537 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
387 09:57:31.499292 WDT: Last reset was cold boot
388 09:57:31.502341 SPI1(PAD0) initialized at 2873684 Hz
389 09:57:31.505413 SPI5(PAD0) initialized at 992727 Hz
390 09:57:31.508828 VBOOT: Loading verstage.
391 09:57:31.515548 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
392 09:57:31.519234 FMAP: Found "FLASH" version 1.1 at 0x20000.
393 09:57:31.522307 FMAP: base = 0x0 size = 0x800000 #areas = 25
394 09:57:31.525575 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
395 09:57:31.533235 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
396 09:57:31.539515 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
397 09:57:31.550547 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
398 09:57:31.550631
399 09:57:31.550696
400 09:57:31.560875 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
401 09:57:31.564140 ARM64: Exception handlers installed.
402 09:57:31.567438 ARM64: Testing exception
403 09:57:31.567520 ARM64: Done test exception
404 09:57:31.574349 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
405 09:57:31.577740 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
406 09:57:31.591510 Probing TPM: . done!
407 09:57:31.591602 TPM ready after 0 ms
408 09:57:31.598281 Connected to device vid:did:rid of 1ae0:0028:00
409 09:57:31.605174 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
410 09:57:31.608972 Initialized TPM device CR50 revision 0
411 09:57:31.657308 tlcl_send_startup: Startup return code is 0
412 09:57:31.657464 TPM: setup succeeded
413 09:57:31.669106 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
414 09:57:31.677424 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 09:57:31.688965 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
416 09:57:31.698667 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
417 09:57:31.701998 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
418 09:57:31.706925 in-header: 03 07 00 00 08 00 00 00
419 09:57:31.710268 in-data: aa e4 47 04 13 02 00 00
420 09:57:31.714184 Chrome EC: UHEPI supported
421 09:57:31.720745 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
422 09:57:31.724384 in-header: 03 9d 00 00 08 00 00 00
423 09:57:31.728502 in-data: 10 20 20 08 00 00 00 00
424 09:57:31.728593 Phase 1
425 09:57:31.732017 FMAP: area GBB found @ 3f5000 (12032 bytes)
426 09:57:31.739663 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
427 09:57:31.747059 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
428 09:57:31.747143 Recovery requested (1009000e)
429 09:57:31.755685 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 09:57:31.760906 tlcl_extend: response is 0
431 09:57:31.768807 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 09:57:31.774201 tlcl_extend: response is 0
433 09:57:31.781553 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 09:57:31.801972 read SPI 0x210d4 0x2173b: 15146 us, 9046 KB/s, 72.368 Mbps
435 09:57:31.809223 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 09:57:31.809335
437 09:57:31.809432
438 09:57:31.817226 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 09:57:31.820552 ARM64: Exception handlers installed.
440 09:57:31.824258 ARM64: Testing exception
441 09:57:31.827393 ARM64: Done test exception
442 09:57:31.844103 pmic_efuse_setting: Set efuses in 11 msecs
443 09:57:31.853421 pmwrap_interface_init: Select PMIF_VLD_RDY
444 09:57:31.856309 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 09:57:31.860368 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 09:57:31.867444 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 09:57:31.871599 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 09:57:31.875498 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 09:57:31.882437 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 09:57:31.885679 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 09:57:31.889548 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 09:57:31.893135 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 09:57:31.899187 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 09:57:31.902738 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 09:57:31.909408 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 09:57:31.912871 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 09:57:31.919444 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 09:57:31.925998 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 09:57:31.929517 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 09:57:31.935903 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 09:57:31.942758 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 09:57:31.946278 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 09:57:31.952900 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 09:57:31.960848 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 09:57:31.964104 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 09:57:31.971126 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 09:57:31.974329 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 09:57:31.981717 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 09:57:31.988383 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 09:57:31.991625 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 09:57:31.994819 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 09:57:32.001349 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 09:57:32.004896 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 09:57:32.012344 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 09:57:32.016280 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 09:57:32.020136 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 09:57:32.026732 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 09:57:32.030433 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 09:57:32.037886 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 09:57:32.041116 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 09:57:32.044527 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 09:57:32.051534 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 09:57:32.054376 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 09:57:32.058007 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 09:57:32.064732 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 09:57:32.067921 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 09:57:32.071549 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 09:57:32.077753 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 09:57:32.080942 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 09:57:32.084481 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 09:57:32.088327 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 09:57:32.094736 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 09:57:32.097934 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 09:57:32.101313 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 09:57:32.111416 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
496 09:57:32.117741 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 09:57:32.124611 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 09:57:32.131439 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 09:57:32.141167 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 09:57:32.144493 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 09:57:32.147637 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 09:57:32.154187 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 09:57:32.161311 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x14
504 09:57:32.164449 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 09:57:32.171518 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
506 09:57:32.174745 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 09:57:32.184118 [RTC]rtc_get_frequency_meter,154: input=15, output=794
508 09:57:32.187983 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
509 09:57:32.194146 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
510 09:57:32.197356 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
511 09:57:32.201075 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
512 09:57:32.204636 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
513 09:57:32.207464 ADC[4]: Raw value=894821 ID=7
514 09:57:32.211082 ADC[3]: Raw value=213440 ID=1
515 09:57:32.211193 RAM Code: 0x71
516 09:57:32.217568 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
517 09:57:32.220706 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
518 09:57:32.231218 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
519 09:57:32.237962 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
520 09:57:32.241947 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
521 09:57:32.245345 in-header: 03 07 00 00 08 00 00 00
522 09:57:32.248317 in-data: aa e4 47 04 13 02 00 00
523 09:57:32.248400 Chrome EC: UHEPI supported
524 09:57:32.255039 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
525 09:57:32.258864 in-header: 03 d5 00 00 08 00 00 00
526 09:57:32.262635 in-data: 98 20 60 08 00 00 00 00
527 09:57:32.266394 MRC: failed to locate region type 0.
528 09:57:32.273819 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
529 09:57:32.277373 DRAM-K: Running full calibration
530 09:57:32.283945 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
531 09:57:32.284027 header.status = 0x0
532 09:57:32.287758 header.version = 0x6 (expected: 0x6)
533 09:57:32.291425 header.size = 0xd00 (expected: 0xd00)
534 09:57:32.291507 header.flags = 0x0
535 09:57:32.297987 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
536 09:57:32.316106 read SPI 0x72590 0x1c583: 12501 us, 9287 KB/s, 74.296 Mbps
537 09:57:32.322971 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
538 09:57:32.326662 dram_init: ddr_geometry: 2
539 09:57:32.329983 [EMI] MDL number = 2
540 09:57:32.330065 [EMI] Get MDL freq = 0
541 09:57:32.332944 dram_init: ddr_type: 0
542 09:57:32.333025 is_discrete_lpddr4: 1
543 09:57:32.336326 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
544 09:57:32.336408
545 09:57:32.336473
546 09:57:32.339906 [Bian_co] ETT version 0.0.0.1
547 09:57:32.346185 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
548 09:57:32.346269
549 09:57:32.349603 dramc_set_vcore_voltage set vcore to 650000
550 09:57:32.349686 Read voltage for 800, 4
551 09:57:32.352970 Vio18 = 0
552 09:57:32.353052 Vcore = 650000
553 09:57:32.353117 Vdram = 0
554 09:57:32.356827 Vddq = 0
555 09:57:32.356910 Vmddr = 0
556 09:57:32.359814 dram_init: config_dvfs: 1
557 09:57:32.363031 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
558 09:57:32.370045 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
559 09:57:32.373462 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
560 09:57:32.376900 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
561 09:57:32.380148 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
562 09:57:32.383217 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
563 09:57:32.386568 MEM_TYPE=3, freq_sel=18
564 09:57:32.389604 sv_algorithm_assistance_LP4_1600
565 09:57:32.393237 ============ PULL DRAM RESETB DOWN ============
566 09:57:32.396475 ========== PULL DRAM RESETB DOWN end =========
567 09:57:32.403059 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
568 09:57:32.406925 ===================================
569 09:57:32.407010 LPDDR4 DRAM CONFIGURATION
570 09:57:32.409745 ===================================
571 09:57:32.413107 EX_ROW_EN[0] = 0x0
572 09:57:32.416784 EX_ROW_EN[1] = 0x0
573 09:57:32.416866 LP4Y_EN = 0x0
574 09:57:32.419871 WORK_FSP = 0x0
575 09:57:32.419953 WL = 0x2
576 09:57:32.422949 RL = 0x2
577 09:57:32.423030 BL = 0x2
578 09:57:32.426308 RPST = 0x0
579 09:57:32.426390 RD_PRE = 0x0
580 09:57:32.429672 WR_PRE = 0x1
581 09:57:32.429753 WR_PST = 0x0
582 09:57:32.433411 DBI_WR = 0x0
583 09:57:32.433493 DBI_RD = 0x0
584 09:57:32.436365 OTF = 0x1
585 09:57:32.439738 ===================================
586 09:57:32.443466 ===================================
587 09:57:32.443549 ANA top config
588 09:57:32.446970 ===================================
589 09:57:32.450649 DLL_ASYNC_EN = 0
590 09:57:32.454059 ALL_SLAVE_EN = 1
591 09:57:32.454139 NEW_RANK_MODE = 1
592 09:57:32.457449 DLL_IDLE_MODE = 1
593 09:57:32.461304 LP45_APHY_COMB_EN = 1
594 09:57:32.461388 TX_ODT_DIS = 1
595 09:57:32.465360 NEW_8X_MODE = 1
596 09:57:32.468822 ===================================
597 09:57:32.472583 ===================================
598 09:57:32.476198 data_rate = 1600
599 09:57:32.476338 CKR = 1
600 09:57:32.479770 DQ_P2S_RATIO = 8
601 09:57:32.483274 ===================================
602 09:57:32.487018 CA_P2S_RATIO = 8
603 09:57:32.490804 DQ_CA_OPEN = 0
604 09:57:32.490889 DQ_SEMI_OPEN = 0
605 09:57:32.494812 CA_SEMI_OPEN = 0
606 09:57:32.498518 CA_FULL_RATE = 0
607 09:57:32.501957 DQ_CKDIV4_EN = 1
608 09:57:32.502040 CA_CKDIV4_EN = 1
609 09:57:32.505867 CA_PREDIV_EN = 0
610 09:57:32.509298 PH8_DLY = 0
611 09:57:32.513811 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
612 09:57:32.513895 DQ_AAMCK_DIV = 4
613 09:57:32.516743 CA_AAMCK_DIV = 4
614 09:57:32.520564 CA_ADMCK_DIV = 4
615 09:57:32.520650 DQ_TRACK_CA_EN = 0
616 09:57:32.524074 CA_PICK = 800
617 09:57:32.528550 CA_MCKIO = 800
618 09:57:32.531457 MCKIO_SEMI = 0
619 09:57:32.534598 PLL_FREQ = 3068
620 09:57:32.538208 DQ_UI_PI_RATIO = 32
621 09:57:32.538290 CA_UI_PI_RATIO = 0
622 09:57:32.541465 ===================================
623 09:57:32.544662 ===================================
624 09:57:32.548462 memory_type:LPDDR4
625 09:57:32.551545 GP_NUM : 10
626 09:57:32.551627 SRAM_EN : 1
627 09:57:32.554973 MD32_EN : 0
628 09:57:32.558238 ===================================
629 09:57:32.561975 [ANA_INIT] >>>>>>>>>>>>>>
630 09:57:32.562057 <<<<<< [CONFIGURE PHASE]: ANA_TX
631 09:57:32.564866 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
632 09:57:32.568373 ===================================
633 09:57:32.571623 data_rate = 1600,PCW = 0X7600
634 09:57:32.575158 ===================================
635 09:57:32.578316 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
636 09:57:32.584810 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
637 09:57:32.591642 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
638 09:57:32.594828 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
639 09:57:32.598249 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
640 09:57:32.601985 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
641 09:57:32.602071 [ANA_INIT] flow start
642 09:57:32.605729 [ANA_INIT] PLL >>>>>>>>
643 09:57:32.609897 [ANA_INIT] PLL <<<<<<<<
644 09:57:32.609988 [ANA_INIT] MIDPI >>>>>>>>
645 09:57:32.613599 [ANA_INIT] MIDPI <<<<<<<<
646 09:57:32.617384 [ANA_INIT] DLL >>>>>>>>
647 09:57:32.617467 [ANA_INIT] flow end
648 09:57:32.620935 ============ LP4 DIFF to SE enter ============
649 09:57:32.624297 ============ LP4 DIFF to SE exit ============
650 09:57:32.628033 [ANA_INIT] <<<<<<<<<<<<<
651 09:57:32.631675 [Flow] Enable top DCM control >>>>>
652 09:57:32.635557 [Flow] Enable top DCM control <<<<<
653 09:57:32.639275 Enable DLL master slave shuffle
654 09:57:32.643226 ==============================================================
655 09:57:32.643347 Gating Mode config
656 09:57:32.650253 ==============================================================
657 09:57:32.653132 Config description:
658 09:57:32.663346 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
659 09:57:32.669919 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
660 09:57:32.673518 SELPH_MODE 0: By rank 1: By Phase
661 09:57:32.680197 ==============================================================
662 09:57:32.683345 GAT_TRACK_EN = 1
663 09:57:32.683429 RX_GATING_MODE = 2
664 09:57:32.686543 RX_GATING_TRACK_MODE = 2
665 09:57:32.689931 SELPH_MODE = 1
666 09:57:32.693214 PICG_EARLY_EN = 1
667 09:57:32.696534 VALID_LAT_VALUE = 1
668 09:57:32.703133 ==============================================================
669 09:57:32.706637 Enter into Gating configuration >>>>
670 09:57:32.709987 Exit from Gating configuration <<<<
671 09:57:32.713093 Enter into DVFS_PRE_config >>>>>
672 09:57:32.723602 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
673 09:57:32.727323 Exit from DVFS_PRE_config <<<<<
674 09:57:32.730506 Enter into PICG configuration >>>>
675 09:57:32.734523 Exit from PICG configuration <<<<
676 09:57:32.734608 [RX_INPUT] configuration >>>>>
677 09:57:32.738523 [RX_INPUT] configuration <<<<<
678 09:57:32.742006 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
679 09:57:32.748969 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
680 09:57:32.756235 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
681 09:57:32.759782 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
682 09:57:32.767124 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
683 09:57:32.774008 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
684 09:57:32.777716 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
685 09:57:32.781486 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
686 09:57:32.785237 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
687 09:57:32.788707 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
688 09:57:32.791994 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
689 09:57:32.799978 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
690 09:57:32.803381 ===================================
691 09:57:32.803468 LPDDR4 DRAM CONFIGURATION
692 09:57:32.806589 ===================================
693 09:57:32.810492 EX_ROW_EN[0] = 0x0
694 09:57:32.810576 EX_ROW_EN[1] = 0x0
695 09:57:32.813973 LP4Y_EN = 0x0
696 09:57:32.814082 WORK_FSP = 0x0
697 09:57:32.817966 WL = 0x2
698 09:57:32.818090 RL = 0x2
699 09:57:32.821331 BL = 0x2
700 09:57:32.821410 RPST = 0x0
701 09:57:32.825180 RD_PRE = 0x0
702 09:57:32.825264 WR_PRE = 0x1
703 09:57:32.825330 WR_PST = 0x0
704 09:57:32.829011 DBI_WR = 0x0
705 09:57:32.829129 DBI_RD = 0x0
706 09:57:32.832634 OTF = 0x1
707 09:57:32.836329 ===================================
708 09:57:32.839913 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
709 09:57:32.843176 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
710 09:57:32.847596 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
711 09:57:32.851292 ===================================
712 09:57:32.854605 LPDDR4 DRAM CONFIGURATION
713 09:57:32.858295 ===================================
714 09:57:32.858376 EX_ROW_EN[0] = 0x10
715 09:57:32.861477 EX_ROW_EN[1] = 0x0
716 09:57:32.861552 LP4Y_EN = 0x0
717 09:57:32.865306 WORK_FSP = 0x0
718 09:57:32.865390 WL = 0x2
719 09:57:32.868907 RL = 0x2
720 09:57:32.868991 BL = 0x2
721 09:57:32.873312 RPST = 0x0
722 09:57:32.873397 RD_PRE = 0x0
723 09:57:32.873464 WR_PRE = 0x1
724 09:57:32.876537 WR_PST = 0x0
725 09:57:32.876627 DBI_WR = 0x0
726 09:57:32.880890 DBI_RD = 0x0
727 09:57:32.880986 OTF = 0x1
728 09:57:32.884043 ===================================
729 09:57:32.890978 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
730 09:57:32.894903 nWR fixed to 40
731 09:57:32.898939 [ModeRegInit_LP4] CH0 RK0
732 09:57:32.899056 [ModeRegInit_LP4] CH0 RK1
733 09:57:32.902527 [ModeRegInit_LP4] CH1 RK0
734 09:57:32.902643 [ModeRegInit_LP4] CH1 RK1
735 09:57:32.906377 match AC timing 13
736 09:57:32.909969 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
737 09:57:32.913572 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
738 09:57:32.917422 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
739 09:57:32.924647 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
740 09:57:32.928169 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
741 09:57:32.928283 [EMI DOE] emi_dcm 0
742 09:57:32.931928 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
743 09:57:32.935430 ==
744 09:57:32.940044 Dram Type= 6, Freq= 0, CH_0, rank 0
745 09:57:32.940158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
746 09:57:32.944019 ==
747 09:57:32.947317 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
748 09:57:32.954395 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
749 09:57:32.962457 [CA 0] Center 38 (7~69) winsize 63
750 09:57:32.966552 [CA 1] Center 37 (7~68) winsize 62
751 09:57:32.970039 [CA 2] Center 35 (5~66) winsize 62
752 09:57:32.973510 [CA 3] Center 35 (5~66) winsize 62
753 09:57:32.977375 [CA 4] Center 34 (4~65) winsize 62
754 09:57:32.981411 [CA 5] Center 34 (4~65) winsize 62
755 09:57:32.981496
756 09:57:32.984833 [CmdBusTrainingLP45] Vref(ca) range 1: 34
757 09:57:32.984917
758 09:57:32.988633 [CATrainingPosCal] consider 1 rank data
759 09:57:32.988719 u2DelayCellTimex100 = 270/100 ps
760 09:57:32.992121 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
761 09:57:32.995704 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
762 09:57:32.999252 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
763 09:57:33.002784 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
764 09:57:33.006979 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
765 09:57:33.010549 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
766 09:57:33.010634
767 09:57:33.014410 CA PerBit enable=1, Macro0, CA PI delay=34
768 09:57:33.014494
769 09:57:33.017988 [CBTSetCACLKResult] CA Dly = 34
770 09:57:33.021551 CS Dly: 6 (0~37)
771 09:57:33.021635 ==
772 09:57:33.025273 Dram Type= 6, Freq= 0, CH_0, rank 1
773 09:57:33.029037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 09:57:33.029120 ==
775 09:57:33.032378 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
776 09:57:33.038294 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
777 09:57:33.048437 [CA 0] Center 38 (7~69) winsize 63
778 09:57:33.051984 [CA 1] Center 38 (7~69) winsize 63
779 09:57:33.055158 [CA 2] Center 35 (5~66) winsize 62
780 09:57:33.058449 [CA 3] Center 35 (5~66) winsize 62
781 09:57:33.061859 [CA 4] Center 34 (4~65) winsize 62
782 09:57:33.065163 [CA 5] Center 34 (4~65) winsize 62
783 09:57:33.065248
784 09:57:33.068681 [CmdBusTrainingLP45] Vref(ca) range 1: 34
785 09:57:33.068765
786 09:57:33.072131 [CATrainingPosCal] consider 2 rank data
787 09:57:33.075249 u2DelayCellTimex100 = 270/100 ps
788 09:57:33.078437 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
789 09:57:33.081950 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
790 09:57:33.088468 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
791 09:57:33.091720 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
792 09:57:33.095166 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
793 09:57:33.098679 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
794 09:57:33.098765
795 09:57:33.102252 CA PerBit enable=1, Macro0, CA PI delay=34
796 09:57:33.102339
797 09:57:33.105115 [CBTSetCACLKResult] CA Dly = 34
798 09:57:33.105202 CS Dly: 6 (0~38)
799 09:57:33.105291
800 09:57:33.108224 ----->DramcWriteLeveling(PI) begin...
801 09:57:33.111970 ==
802 09:57:33.112057 Dram Type= 6, Freq= 0, CH_0, rank 0
803 09:57:33.118820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
804 09:57:33.118908 ==
805 09:57:33.122057 Write leveling (Byte 0): 32 => 32
806 09:57:33.125159 Write leveling (Byte 1): 32 => 32
807 09:57:33.125264 DramcWriteLeveling(PI) end<-----
808 09:57:33.128487
809 09:57:33.128576 ==
810 09:57:33.131927 Dram Type= 6, Freq= 0, CH_0, rank 0
811 09:57:33.135524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
812 09:57:33.135611 ==
813 09:57:33.138345 [Gating] SW mode calibration
814 09:57:33.144814 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
815 09:57:33.148515 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
816 09:57:33.154931 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
817 09:57:33.158301 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
818 09:57:33.162048 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
819 09:57:33.168424 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 09:57:33.171555 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 09:57:33.174768 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 09:57:33.181689 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 09:57:33.185404 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 09:57:33.189300 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 09:57:33.192544 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 09:57:33.200337 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 09:57:33.203309 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 09:57:33.207338 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 09:57:33.210407 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 09:57:33.218058 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 09:57:33.221027 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 09:57:33.224253 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 09:57:33.227606 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 09:57:33.234158 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
835 09:57:33.237519 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
836 09:57:33.240835 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 09:57:33.247510 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 09:57:33.250851 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 09:57:33.254518 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 09:57:33.260771 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 09:57:33.264489 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 09:57:33.267396 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
843 09:57:33.274323 0 9 12 | B1->B0 | 2727 2d2d | 0 1 | (0 0) (0 0)
844 09:57:33.277669 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
845 09:57:33.281454 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
846 09:57:33.287988 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
847 09:57:33.290745 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
848 09:57:33.294290 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
849 09:57:33.297423 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
850 09:57:33.304389 0 10 8 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 1)
851 09:57:33.307509 0 10 12 | B1->B0 | 2a2a 2424 | 0 0 | (0 1) (0 0)
852 09:57:33.311164 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 09:57:33.317804 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 09:57:33.320915 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 09:57:33.324565 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 09:57:33.331017 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 09:57:33.334672 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 09:57:33.337818 0 11 8 | B1->B0 | 2424 2a2a | 0 1 | (0 0) (0 0)
859 09:57:33.344747 0 11 12 | B1->B0 | 3232 4040 | 1 0 | (0 0) (0 0)
860 09:57:33.347893 0 11 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
861 09:57:33.351241 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
862 09:57:33.357895 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
863 09:57:33.361349 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 09:57:33.364548 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 09:57:33.368393 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 09:57:33.374521 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 09:57:33.377840 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
868 09:57:33.381134 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
869 09:57:33.387926 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
870 09:57:33.391126 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
871 09:57:33.394878 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 09:57:33.401477 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 09:57:33.404953 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 09:57:33.407904 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 09:57:33.414808 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 09:57:33.418107 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 09:57:33.421768 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 09:57:33.428056 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 09:57:33.431373 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 09:57:33.434637 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 09:57:33.441639 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 09:57:33.444578 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
883 09:57:33.448179 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
884 09:57:33.451148 Total UI for P1: 0, mck2ui 16
885 09:57:33.454751 best dqsien dly found for B0: ( 0, 14, 8)
886 09:57:33.458137 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 09:57:33.461093 Total UI for P1: 0, mck2ui 16
888 09:57:33.464474 best dqsien dly found for B1: ( 0, 14, 12)
889 09:57:33.468072 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
890 09:57:33.474732 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
891 09:57:33.474819
892 09:57:33.478008 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
893 09:57:33.481446 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
894 09:57:33.484527 [Gating] SW calibration Done
895 09:57:33.484613 ==
896 09:57:33.487906 Dram Type= 6, Freq= 0, CH_0, rank 0
897 09:57:33.491503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
898 09:57:33.491590 ==
899 09:57:33.491678 RX Vref Scan: 0
900 09:57:33.491761
901 09:57:33.494694 RX Vref 0 -> 0, step: 1
902 09:57:33.494796
903 09:57:33.498152 RX Delay -130 -> 252, step: 16
904 09:57:33.501374 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
905 09:57:33.504424 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
906 09:57:33.511430 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
907 09:57:33.514917 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
908 09:57:33.517876 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
909 09:57:33.521576 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
910 09:57:33.525208 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
911 09:57:33.531521 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
912 09:57:33.534735 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
913 09:57:33.538234 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
914 09:57:33.541719 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
915 09:57:33.548680 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
916 09:57:33.551782 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
917 09:57:33.555225 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
918 09:57:33.558178 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
919 09:57:33.561532 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
920 09:57:33.561619 ==
921 09:57:33.565098 Dram Type= 6, Freq= 0, CH_0, rank 0
922 09:57:33.568681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
923 09:57:33.571497 ==
924 09:57:33.571582 DQS Delay:
925 09:57:33.571671 DQS0 = 0, DQS1 = 0
926 09:57:33.574914 DQM Delay:
927 09:57:33.575000 DQM0 = 81, DQM1 = 69
928 09:57:33.578662 DQ Delay:
929 09:57:33.578748 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
930 09:57:33.581945 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
931 09:57:33.584747 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
932 09:57:33.588067 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
933 09:57:33.588153
934 09:57:33.591418
935 09:57:33.591504 ==
936 09:57:33.595860 Dram Type= 6, Freq= 0, CH_0, rank 0
937 09:57:33.598764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
938 09:57:33.598872 ==
939 09:57:33.598961
940 09:57:33.599043
941 09:57:33.599123 TX Vref Scan disable
942 09:57:33.602818 == TX Byte 0 ==
943 09:57:33.606094 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
944 09:57:33.609520 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
945 09:57:33.612627 == TX Byte 1 ==
946 09:57:33.615882 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
947 09:57:33.618993 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
948 09:57:33.622733 ==
949 09:57:33.625857 Dram Type= 6, Freq= 0, CH_0, rank 0
950 09:57:33.629177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
951 09:57:33.629261 ==
952 09:57:33.641260 TX Vref=22, minBit 10, minWin=26, winSum=432
953 09:57:33.644549 TX Vref=24, minBit 3, minWin=26, winSum=432
954 09:57:33.647903 TX Vref=26, minBit 2, minWin=27, winSum=445
955 09:57:33.651720 TX Vref=28, minBit 10, minWin=27, winSum=446
956 09:57:33.655108 TX Vref=30, minBit 9, minWin=27, winSum=443
957 09:57:33.661475 TX Vref=32, minBit 1, minWin=27, winSum=440
958 09:57:33.664897 [TxChooseVref] Worse bit 10, Min win 27, Win sum 446, Final Vref 28
959 09:57:33.664981
960 09:57:33.668313 Final TX Range 1 Vref 28
961 09:57:33.668397
962 09:57:33.668466 ==
963 09:57:33.671653 Dram Type= 6, Freq= 0, CH_0, rank 0
964 09:57:33.675227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
965 09:57:33.675339 ==
966 09:57:33.677986
967 09:57:33.678084
968 09:57:33.678150 TX Vref Scan disable
969 09:57:33.681451 == TX Byte 0 ==
970 09:57:33.685260 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
971 09:57:33.688305 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
972 09:57:33.691666 == TX Byte 1 ==
973 09:57:33.694828 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
974 09:57:33.698100 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
975 09:57:33.701626
976 09:57:33.701709 [DATLAT]
977 09:57:33.701822 Freq=800, CH0 RK0
978 09:57:33.701906
979 09:57:33.705094 DATLAT Default: 0xa
980 09:57:33.705177 0, 0xFFFF, sum = 0
981 09:57:33.708707 1, 0xFFFF, sum = 0
982 09:57:33.708792 2, 0xFFFF, sum = 0
983 09:57:33.711400 3, 0xFFFF, sum = 0
984 09:57:33.711484 4, 0xFFFF, sum = 0
985 09:57:33.714903 5, 0xFFFF, sum = 0
986 09:57:33.715052 6, 0xFFFF, sum = 0
987 09:57:33.718705 7, 0xFFFF, sum = 0
988 09:57:33.718819 8, 0xFFFF, sum = 0
989 09:57:33.721930 9, 0x0, sum = 1
990 09:57:33.722005 10, 0x0, sum = 2
991 09:57:33.725038 11, 0x0, sum = 3
992 09:57:33.725121 12, 0x0, sum = 4
993 09:57:33.728577 best_step = 10
994 09:57:33.728659
995 09:57:33.728748 ==
996 09:57:33.731540 Dram Type= 6, Freq= 0, CH_0, rank 0
997 09:57:33.734931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
998 09:57:33.735016 ==
999 09:57:33.738248 RX Vref Scan: 1
1000 09:57:33.738331
1001 09:57:33.738397 Set Vref Range= 32 -> 127
1002 09:57:33.738458
1003 09:57:33.741796 RX Vref 32 -> 127, step: 1
1004 09:57:33.741879
1005 09:57:33.745194 RX Delay -111 -> 252, step: 8
1006 09:57:33.745276
1007 09:57:33.748181 Set Vref, RX VrefLevel [Byte0]: 32
1008 09:57:33.752174 [Byte1]: 32
1009 09:57:33.752281
1010 09:57:33.755093 Set Vref, RX VrefLevel [Byte0]: 33
1011 09:57:33.758507 [Byte1]: 33
1012 09:57:33.761961
1013 09:57:33.762044 Set Vref, RX VrefLevel [Byte0]: 34
1014 09:57:33.768296 [Byte1]: 34
1015 09:57:33.768378
1016 09:57:33.771955 Set Vref, RX VrefLevel [Byte0]: 35
1017 09:57:33.775000 [Byte1]: 35
1018 09:57:33.775080
1019 09:57:33.778947 Set Vref, RX VrefLevel [Byte0]: 36
1020 09:57:33.782054 [Byte1]: 36
1021 09:57:33.782136
1022 09:57:33.785708 Set Vref, RX VrefLevel [Byte0]: 37
1023 09:57:33.788978 [Byte1]: 37
1024 09:57:33.792696
1025 09:57:33.792781 Set Vref, RX VrefLevel [Byte0]: 38
1026 09:57:33.795769 [Byte1]: 38
1027 09:57:33.800540
1028 09:57:33.800619 Set Vref, RX VrefLevel [Byte0]: 39
1029 09:57:33.803575 [Byte1]: 39
1030 09:57:33.807804
1031 09:57:33.807885 Set Vref, RX VrefLevel [Byte0]: 40
1032 09:57:33.811217 [Byte1]: 40
1033 09:57:33.815566
1034 09:57:33.815696 Set Vref, RX VrefLevel [Byte0]: 41
1035 09:57:33.818561 [Byte1]: 41
1036 09:57:33.823149
1037 09:57:33.823249 Set Vref, RX VrefLevel [Byte0]: 42
1038 09:57:33.826310 [Byte1]: 42
1039 09:57:33.830773
1040 09:57:33.830870 Set Vref, RX VrefLevel [Byte0]: 43
1041 09:57:33.834461 [Byte1]: 43
1042 09:57:33.838510
1043 09:57:33.838599 Set Vref, RX VrefLevel [Byte0]: 44
1044 09:57:33.841671 [Byte1]: 44
1045 09:57:33.846342
1046 09:57:33.846430 Set Vref, RX VrefLevel [Byte0]: 45
1047 09:57:33.849880 [Byte1]: 45
1048 09:57:33.854571
1049 09:57:33.854645 Set Vref, RX VrefLevel [Byte0]: 46
1050 09:57:33.857790 [Byte1]: 46
1051 09:57:33.861603
1052 09:57:33.861683 Set Vref, RX VrefLevel [Byte0]: 47
1053 09:57:33.864829 [Byte1]: 47
1054 09:57:33.869009
1055 09:57:33.869105 Set Vref, RX VrefLevel [Byte0]: 48
1056 09:57:33.872437 [Byte1]: 48
1057 09:57:33.877386
1058 09:57:33.877467 Set Vref, RX VrefLevel [Byte0]: 49
1059 09:57:33.880142 [Byte1]: 49
1060 09:57:33.884579
1061 09:57:33.884659 Set Vref, RX VrefLevel [Byte0]: 50
1062 09:57:33.887729 [Byte1]: 50
1063 09:57:33.892155
1064 09:57:33.892272 Set Vref, RX VrefLevel [Byte0]: 51
1065 09:57:33.895628 [Byte1]: 51
1066 09:57:33.899764
1067 09:57:33.899844 Set Vref, RX VrefLevel [Byte0]: 52
1068 09:57:33.903338 [Byte1]: 52
1069 09:57:33.907592
1070 09:57:33.907672 Set Vref, RX VrefLevel [Byte0]: 53
1071 09:57:33.910508 [Byte1]: 53
1072 09:57:33.915828
1073 09:57:33.915907 Set Vref, RX VrefLevel [Byte0]: 54
1074 09:57:33.918355 [Byte1]: 54
1075 09:57:33.922587
1076 09:57:33.922667 Set Vref, RX VrefLevel [Byte0]: 55
1077 09:57:33.925955 [Byte1]: 55
1078 09:57:33.930325
1079 09:57:33.930405 Set Vref, RX VrefLevel [Byte0]: 56
1080 09:57:33.933869 [Byte1]: 56
1081 09:57:33.937768
1082 09:57:33.937856 Set Vref, RX VrefLevel [Byte0]: 57
1083 09:57:33.941423 [Byte1]: 57
1084 09:57:33.945898
1085 09:57:33.945979 Set Vref, RX VrefLevel [Byte0]: 58
1086 09:57:33.948633 [Byte1]: 58
1087 09:57:33.952997
1088 09:57:33.953083 Set Vref, RX VrefLevel [Byte0]: 59
1089 09:57:33.956285 [Byte1]: 59
1090 09:57:33.960949
1091 09:57:33.961024 Set Vref, RX VrefLevel [Byte0]: 60
1092 09:57:33.964110 [Byte1]: 60
1093 09:57:33.968427
1094 09:57:33.968507 Set Vref, RX VrefLevel [Byte0]: 61
1095 09:57:33.971598 [Byte1]: 61
1096 09:57:33.975881
1097 09:57:33.975961 Set Vref, RX VrefLevel [Byte0]: 62
1098 09:57:33.979416 [Byte1]: 62
1099 09:57:33.983424
1100 09:57:33.983530 Set Vref, RX VrefLevel [Byte0]: 63
1101 09:57:33.986876 [Byte1]: 63
1102 09:57:33.991508
1103 09:57:33.991588 Set Vref, RX VrefLevel [Byte0]: 64
1104 09:57:33.994709 [Byte1]: 64
1105 09:57:33.998965
1106 09:57:33.999073 Set Vref, RX VrefLevel [Byte0]: 65
1107 09:57:34.002240 [Byte1]: 65
1108 09:57:34.006626
1109 09:57:34.006722 Set Vref, RX VrefLevel [Byte0]: 66
1110 09:57:34.009826 [Byte1]: 66
1111 09:57:34.014136
1112 09:57:34.014242 Set Vref, RX VrefLevel [Byte0]: 67
1113 09:57:34.017637 [Byte1]: 67
1114 09:57:34.021692
1115 09:57:34.021776 Set Vref, RX VrefLevel [Byte0]: 68
1116 09:57:34.025557 [Byte1]: 68
1117 09:57:34.029593
1118 09:57:34.029706 Set Vref, RX VrefLevel [Byte0]: 69
1119 09:57:34.032718 [Byte1]: 69
1120 09:57:34.037371
1121 09:57:34.037484 Set Vref, RX VrefLevel [Byte0]: 70
1122 09:57:34.040431 [Byte1]: 70
1123 09:57:34.044606
1124 09:57:34.044694 Set Vref, RX VrefLevel [Byte0]: 71
1125 09:57:34.048301 [Byte1]: 71
1126 09:57:34.052769
1127 09:57:34.052849 Set Vref, RX VrefLevel [Byte0]: 72
1128 09:57:34.055739 [Byte1]: 72
1129 09:57:34.060405
1130 09:57:34.060509 Set Vref, RX VrefLevel [Byte0]: 73
1131 09:57:34.063770 [Byte1]: 73
1132 09:57:34.067547
1133 09:57:34.067655 Set Vref, RX VrefLevel [Byte0]: 74
1134 09:57:34.071309 [Byte1]: 74
1135 09:57:34.075192
1136 09:57:34.075303 Set Vref, RX VrefLevel [Byte0]: 75
1137 09:57:34.078861 [Byte1]: 75
1138 09:57:34.083347
1139 09:57:34.083428 Set Vref, RX VrefLevel [Byte0]: 76
1140 09:57:34.086504 [Byte1]: 76
1141 09:57:34.090893
1142 09:57:34.090999 Set Vref, RX VrefLevel [Byte0]: 77
1143 09:57:34.093960 [Byte1]: 77
1144 09:57:34.098681
1145 09:57:34.098761 Set Vref, RX VrefLevel [Byte0]: 78
1146 09:57:34.101837 [Byte1]: 78
1147 09:57:34.106064
1148 09:57:34.106145 Set Vref, RX VrefLevel [Byte0]: 79
1149 09:57:34.109109 [Byte1]: 79
1150 09:57:34.113472
1151 09:57:34.113575 Final RX Vref Byte 0 = 66 to rank0
1152 09:57:34.116961 Final RX Vref Byte 1 = 60 to rank0
1153 09:57:34.120113 Final RX Vref Byte 0 = 66 to rank1
1154 09:57:34.123940 Final RX Vref Byte 1 = 60 to rank1==
1155 09:57:34.127144 Dram Type= 6, Freq= 0, CH_0, rank 0
1156 09:57:34.134070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1157 09:57:34.134151 ==
1158 09:57:34.134215 DQS Delay:
1159 09:57:34.134274 DQS0 = 0, DQS1 = 0
1160 09:57:34.137112 DQM Delay:
1161 09:57:34.137192 DQM0 = 81, DQM1 = 67
1162 09:57:34.140686 DQ Delay:
1163 09:57:34.143977 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1164 09:57:34.144074 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1165 09:57:34.147159 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1166 09:57:34.150615 DQ12 =72, DQ13 =72, DQ14 =76, DQ15 =76
1167 09:57:34.153610
1168 09:57:34.153690
1169 09:57:34.160489 [DQSOSCAuto] RK0, (LSB)MR18= 0x2929, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
1170 09:57:34.164086 CH0 RK0: MR19=606, MR18=2929
1171 09:57:34.170392 CH0_RK0: MR19=0x606, MR18=0x2929, DQSOSC=399, MR23=63, INC=92, DEC=61
1172 09:57:34.170495
1173 09:57:34.173642 ----->DramcWriteLeveling(PI) begin...
1174 09:57:34.173749 ==
1175 09:57:34.177232 Dram Type= 6, Freq= 0, CH_0, rank 1
1176 09:57:34.180209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1177 09:57:34.180331 ==
1178 09:57:34.183977 Write leveling (Byte 0): 34 => 34
1179 09:57:34.187075 Write leveling (Byte 1): 31 => 31
1180 09:57:34.190393 DramcWriteLeveling(PI) end<-----
1181 09:57:34.190501
1182 09:57:34.190582 ==
1183 09:57:34.193886 Dram Type= 6, Freq= 0, CH_0, rank 1
1184 09:57:34.197076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1185 09:57:34.197160 ==
1186 09:57:34.200373 [Gating] SW mode calibration
1187 09:57:34.206961 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1188 09:57:34.213902 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1189 09:57:34.217383 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1190 09:57:34.220304 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1191 09:57:34.226972 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1192 09:57:34.230652 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 09:57:34.234330 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 09:57:34.240668 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 09:57:34.244015 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 09:57:34.247220 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 09:57:34.250655 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 09:57:34.257338 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 09:57:34.260845 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 09:57:34.263840 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 09:57:34.270382 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 09:57:34.314396 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 09:57:34.314730 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 09:57:34.314816 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 09:57:34.314888 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 09:57:34.314949 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1207 09:57:34.315215 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1208 09:57:34.316014 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 09:57:34.316081 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 09:57:34.316363 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 09:57:34.316698 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 09:57:34.358404 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 09:57:34.359033 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 09:57:34.359114 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 09:57:34.359793 0 9 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
1216 09:57:34.360061 0 9 12 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1217 09:57:34.360130 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1218 09:57:34.360191 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1219 09:57:34.360286 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1220 09:57:34.360624 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1221 09:57:34.361164 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1222 09:57:34.379324 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
1223 09:57:34.379835 0 10 8 | B1->B0 | 3030 2626 | 1 0 | (1 0) (0 0)
1224 09:57:34.379953 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 09:57:34.380060 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 09:57:34.383479 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 09:57:34.386390 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 09:57:34.390162 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 09:57:34.392930 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 09:57:34.396145 0 11 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1231 09:57:34.402820 0 11 8 | B1->B0 | 2e2e 4040 | 0 0 | (0 0) (0 0)
1232 09:57:34.406209 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1233 09:57:34.409703 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1234 09:57:34.416592 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 09:57:34.419738 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1236 09:57:34.422842 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1237 09:57:34.426514 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1238 09:57:34.434053 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1239 09:57:34.437602 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1240 09:57:34.441835 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1241 09:57:34.444908 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 09:57:34.452013 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 09:57:34.455379 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 09:57:34.459459 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 09:57:34.462423 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 09:57:34.469029 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 09:57:34.472665 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 09:57:34.475750 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 09:57:34.479179 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 09:57:34.485930 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 09:57:34.488836 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 09:57:34.492151 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 09:57:34.499100 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 09:57:34.502424 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 09:57:34.505682 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1256 09:57:34.509539 Total UI for P1: 0, mck2ui 16
1257 09:57:34.512576 best dqsien dly found for B0: ( 0, 14, 6)
1258 09:57:34.519325 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 09:57:34.519438 Total UI for P1: 0, mck2ui 16
1260 09:57:34.526230 best dqsien dly found for B1: ( 0, 14, 8)
1261 09:57:34.529392 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1262 09:57:34.532535 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1263 09:57:34.532668
1264 09:57:34.535797 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1265 09:57:34.539720 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1266 09:57:34.542716 [Gating] SW calibration Done
1267 09:57:34.542797 ==
1268 09:57:34.545612 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 09:57:34.548990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 09:57:34.549073 ==
1271 09:57:34.552820 RX Vref Scan: 0
1272 09:57:34.552902
1273 09:57:34.552969 RX Vref 0 -> 0, step: 1
1274 09:57:34.553029
1275 09:57:34.555683 RX Delay -130 -> 252, step: 16
1276 09:57:34.559068 iDelay=222, Bit 0, Center 69 (-50 ~ 189) 240
1277 09:57:34.566049 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1278 09:57:34.569201 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1279 09:57:34.572385 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1280 09:57:34.576043 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1281 09:57:34.579222 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1282 09:57:34.586068 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1283 09:57:34.589082 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1284 09:57:34.592656 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1285 09:57:34.595807 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1286 09:57:34.598975 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1287 09:57:34.605550 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1288 09:57:34.608888 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1289 09:57:34.612357 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1290 09:57:34.615614 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1291 09:57:34.618882 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1292 09:57:34.618972 ==
1293 09:57:34.622627 Dram Type= 6, Freq= 0, CH_0, rank 1
1294 09:57:34.629242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1295 09:57:34.629325 ==
1296 09:57:34.629390 DQS Delay:
1297 09:57:34.632507 DQS0 = 0, DQS1 = 0
1298 09:57:34.632589 DQM Delay:
1299 09:57:34.632654 DQM0 = 76, DQM1 = 69
1300 09:57:34.635877 DQ Delay:
1301 09:57:34.638862 DQ0 =69, DQ1 =85, DQ2 =69, DQ3 =69
1302 09:57:34.642551 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =93
1303 09:57:34.646111 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1304 09:57:34.649750 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1305 09:57:34.649831
1306 09:57:34.649895
1307 09:57:34.649953 ==
1308 09:57:34.652563 Dram Type= 6, Freq= 0, CH_0, rank 1
1309 09:57:34.655891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1310 09:57:34.655971 ==
1311 09:57:34.656035
1312 09:57:34.656094
1313 09:57:34.659035 TX Vref Scan disable
1314 09:57:34.659115 == TX Byte 0 ==
1315 09:57:34.665900 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1316 09:57:34.669089 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1317 09:57:34.669171 == TX Byte 1 ==
1318 09:57:34.676077 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1319 09:57:34.679434 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1320 09:57:34.679517 ==
1321 09:57:34.682376 Dram Type= 6, Freq= 0, CH_0, rank 1
1322 09:57:34.685720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1323 09:57:34.685821 ==
1324 09:57:34.700133 TX Vref=22, minBit 13, minWin=26, winSum=438
1325 09:57:34.703646 TX Vref=24, minBit 5, minWin=26, winSum=434
1326 09:57:34.706949 TX Vref=26, minBit 1, minWin=27, winSum=442
1327 09:57:34.710406 TX Vref=28, minBit 1, minWin=27, winSum=440
1328 09:57:34.713359 TX Vref=30, minBit 1, minWin=27, winSum=442
1329 09:57:34.720362 TX Vref=32, minBit 10, minWin=27, winSum=443
1330 09:57:34.723562 [TxChooseVref] Worse bit 10, Min win 27, Win sum 443, Final Vref 32
1331 09:57:34.723645
1332 09:57:34.726980 Final TX Range 1 Vref 32
1333 09:57:34.727062
1334 09:57:34.727127 ==
1335 09:57:34.729915 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 09:57:34.733302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 09:57:34.736713 ==
1338 09:57:34.736795
1339 09:57:34.736861
1340 09:57:34.736924 TX Vref Scan disable
1341 09:57:34.740476 == TX Byte 0 ==
1342 09:57:34.743636 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1343 09:57:34.747217 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1344 09:57:34.749984 == TX Byte 1 ==
1345 09:57:34.753818 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1346 09:57:34.760520 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1347 09:57:34.760629
1348 09:57:34.760703 [DATLAT]
1349 09:57:34.760764 Freq=800, CH0 RK1
1350 09:57:34.760821
1351 09:57:34.763716 DATLAT Default: 0xa
1352 09:57:34.763796 0, 0xFFFF, sum = 0
1353 09:57:34.766836 1, 0xFFFF, sum = 0
1354 09:57:34.766919 2, 0xFFFF, sum = 0
1355 09:57:34.770010 3, 0xFFFF, sum = 0
1356 09:57:34.773935 4, 0xFFFF, sum = 0
1357 09:57:34.774016 5, 0xFFFF, sum = 0
1358 09:57:34.776827 6, 0xFFFF, sum = 0
1359 09:57:34.776909 7, 0xFFFF, sum = 0
1360 09:57:34.780577 8, 0xFFFF, sum = 0
1361 09:57:34.780673 9, 0x0, sum = 1
1362 09:57:34.780738 10, 0x0, sum = 2
1363 09:57:34.783607 11, 0x0, sum = 3
1364 09:57:34.783688 12, 0x0, sum = 4
1365 09:57:34.786917 best_step = 10
1366 09:57:34.786996
1367 09:57:34.787059 ==
1368 09:57:34.790173 Dram Type= 6, Freq= 0, CH_0, rank 1
1369 09:57:34.793698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1370 09:57:34.793779 ==
1371 09:57:34.796944 RX Vref Scan: 0
1372 09:57:34.797023
1373 09:57:34.797085 RX Vref 0 -> 0, step: 1
1374 09:57:34.797144
1375 09:57:34.800075 RX Delay -111 -> 252, step: 8
1376 09:57:34.807053 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1377 09:57:34.810670 iDelay=209, Bit 1, Center 80 (-31 ~ 192) 224
1378 09:57:34.813562 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1379 09:57:34.817221 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
1380 09:57:34.820354 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1381 09:57:34.826928 iDelay=209, Bit 5, Center 64 (-47 ~ 176) 224
1382 09:57:34.830219 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1383 09:57:34.833905 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1384 09:57:34.837019 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1385 09:57:34.840551 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1386 09:57:34.847104 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1387 09:57:34.850252 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1388 09:57:34.853697 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1389 09:57:34.857016 iDelay=209, Bit 13, Center 72 (-47 ~ 192) 240
1390 09:57:34.860516 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1391 09:57:34.867176 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1392 09:57:34.867256 ==
1393 09:57:34.870249 Dram Type= 6, Freq= 0, CH_0, rank 1
1394 09:57:34.873795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1395 09:57:34.873875 ==
1396 09:57:34.873937 DQS Delay:
1397 09:57:34.876908 DQS0 = 0, DQS1 = 0
1398 09:57:34.876987 DQM Delay:
1399 09:57:34.880580 DQM0 = 79, DQM1 = 70
1400 09:57:34.880670 DQ Delay:
1401 09:57:34.883855 DQ0 =80, DQ1 =80, DQ2 =76, DQ3 =76
1402 09:57:34.886949 DQ4 =76, DQ5 =64, DQ6 =92, DQ7 =92
1403 09:57:34.890222 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1404 09:57:34.893685 DQ12 =76, DQ13 =72, DQ14 =80, DQ15 =80
1405 09:57:34.893764
1406 09:57:34.893826
1407 09:57:34.903754 [DQSOSCAuto] RK1, (LSB)MR18= 0x4823, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
1408 09:57:34.903837 CH0 RK1: MR19=606, MR18=4823
1409 09:57:34.910689 CH0_RK1: MR19=0x606, MR18=0x4823, DQSOSC=391, MR23=63, INC=96, DEC=64
1410 09:57:34.913926 [RxdqsGatingPostProcess] freq 800
1411 09:57:34.920721 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1412 09:57:34.923566 Pre-setting of DQS Precalculation
1413 09:57:34.927092 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1414 09:57:34.927173 ==
1415 09:57:34.930315 Dram Type= 6, Freq= 0, CH_1, rank 0
1416 09:57:34.933452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1417 09:57:34.933533 ==
1418 09:57:34.940173 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1419 09:57:34.946914 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1420 09:57:34.955515 [CA 0] Center 36 (6~66) winsize 61
1421 09:57:34.958633 [CA 1] Center 36 (6~67) winsize 62
1422 09:57:34.962115 [CA 2] Center 34 (5~64) winsize 60
1423 09:57:34.965217 [CA 3] Center 34 (4~64) winsize 61
1424 09:57:34.968544 [CA 4] Center 34 (4~64) winsize 61
1425 09:57:34.971855 [CA 5] Center 34 (4~64) winsize 61
1426 09:57:34.971935
1427 09:57:34.975230 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1428 09:57:34.975309
1429 09:57:34.978909 [CATrainingPosCal] consider 1 rank data
1430 09:57:34.981823 u2DelayCellTimex100 = 270/100 ps
1431 09:57:34.985967 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1432 09:57:34.988553 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1433 09:57:34.995398 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1434 09:57:34.998532 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1435 09:57:35.002077 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1436 09:57:35.005600 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1437 09:57:35.005680
1438 09:57:35.008584 CA PerBit enable=1, Macro0, CA PI delay=34
1439 09:57:35.008721
1440 09:57:35.011789 [CBTSetCACLKResult] CA Dly = 34
1441 09:57:35.011898 CS Dly: 5 (0~36)
1442 09:57:35.015492 ==
1443 09:57:35.015573 Dram Type= 6, Freq= 0, CH_1, rank 1
1444 09:57:35.021807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1445 09:57:35.021889 ==
1446 09:57:35.025352 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1447 09:57:35.032035 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1448 09:57:35.041885 [CA 0] Center 37 (7~67) winsize 61
1449 09:57:35.044782 [CA 1] Center 36 (6~67) winsize 62
1450 09:57:35.048577 [CA 2] Center 35 (5~65) winsize 61
1451 09:57:35.051452 [CA 3] Center 34 (4~64) winsize 61
1452 09:57:35.054745 [CA 4] Center 34 (4~65) winsize 62
1453 09:57:35.058310 [CA 5] Center 34 (4~64) winsize 61
1454 09:57:35.058391
1455 09:57:35.061403 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1456 09:57:35.061484
1457 09:57:35.064941 [CATrainingPosCal] consider 2 rank data
1458 09:57:35.067933 u2DelayCellTimex100 = 270/100 ps
1459 09:57:35.071301 CA0 delay=36 (7~66),Diff = 2 PI (14 cell)
1460 09:57:35.074837 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1461 09:57:35.081564 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1462 09:57:35.084958 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1463 09:57:35.088766 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1464 09:57:35.092748 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1465 09:57:35.092841
1466 09:57:35.096124 CA PerBit enable=1, Macro0, CA PI delay=34
1467 09:57:35.096263
1468 09:57:35.096343 [CBTSetCACLKResult] CA Dly = 34
1469 09:57:35.100037 CS Dly: 6 (0~38)
1470 09:57:35.100117
1471 09:57:35.103444 ----->DramcWriteLeveling(PI) begin...
1472 09:57:35.103526 ==
1473 09:57:35.107384 Dram Type= 6, Freq= 0, CH_1, rank 0
1474 09:57:35.110837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1475 09:57:35.110918 ==
1476 09:57:35.114479 Write leveling (Byte 0): 26 => 26
1477 09:57:35.118263 Write leveling (Byte 1): 31 => 31
1478 09:57:35.121914 DramcWriteLeveling(PI) end<-----
1479 09:57:35.121996
1480 09:57:35.122060 ==
1481 09:57:35.125451 Dram Type= 6, Freq= 0, CH_1, rank 0
1482 09:57:35.128741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1483 09:57:35.128821 ==
1484 09:57:35.131911 [Gating] SW mode calibration
1485 09:57:35.138287 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1486 09:57:35.141546 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1487 09:57:35.148318 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1488 09:57:35.151449 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1489 09:57:35.155040 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1490 09:57:35.162154 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 09:57:35.165114 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 09:57:35.168167 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 09:57:35.174816 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 09:57:35.177977 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 09:57:35.181542 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 09:57:35.188043 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 09:57:35.191321 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 09:57:35.194703 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 09:57:35.202222 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 09:57:35.205184 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 09:57:35.208009 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 09:57:35.214664 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 09:57:35.218191 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 09:57:35.221947 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1505 09:57:35.224899 0 8 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1506 09:57:35.231752 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 09:57:35.234986 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 09:57:35.238522 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 09:57:35.244989 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 09:57:35.248374 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 09:57:35.251539 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 09:57:35.258858 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 09:57:35.261574 0 9 8 | B1->B0 | 2828 2a2a | 0 0 | (0 0) (0 0)
1514 09:57:35.265141 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1515 09:57:35.271546 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1516 09:57:35.275413 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1517 09:57:35.278404 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1518 09:57:35.285058 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1519 09:57:35.288467 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1520 09:57:35.292197 0 10 4 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
1521 09:57:35.294891 0 10 8 | B1->B0 | 2f2f 2e2e | 0 0 | (0 0) (0 1)
1522 09:57:35.301972 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 09:57:35.305046 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 09:57:35.308412 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 09:57:35.314999 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 09:57:35.318545 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 09:57:35.321765 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 09:57:35.328397 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1529 09:57:35.331539 0 11 8 | B1->B0 | 3737 3838 | 0 0 | (0 0) (0 0)
1530 09:57:35.335197 0 11 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1531 09:57:35.342246 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1532 09:57:35.345562 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1533 09:57:35.348328 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1534 09:57:35.355256 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 09:57:35.358611 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1536 09:57:35.361490 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1537 09:57:35.368475 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1538 09:57:35.371589 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1539 09:57:35.374896 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 09:57:35.381512 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 09:57:35.384893 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 09:57:35.388420 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 09:57:35.391835 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 09:57:35.398608 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 09:57:35.401530 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 09:57:35.405150 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 09:57:35.411711 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 09:57:35.415491 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 09:57:35.418789 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 09:57:35.424850 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 09:57:35.428579 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 09:57:35.431766 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 09:57:35.438356 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 09:57:35.441429 Total UI for P1: 0, mck2ui 16
1555 09:57:35.444857 best dqsien dly found for B0: ( 0, 14, 6)
1556 09:57:35.444940 Total UI for P1: 0, mck2ui 16
1557 09:57:35.451641 best dqsien dly found for B1: ( 0, 14, 6)
1558 09:57:35.454769 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1559 09:57:35.458388 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1560 09:57:35.458470
1561 09:57:35.461592 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1562 09:57:35.464740 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1563 09:57:35.468624 [Gating] SW calibration Done
1564 09:57:35.468706 ==
1565 09:57:35.471918 Dram Type= 6, Freq= 0, CH_1, rank 0
1566 09:57:35.475340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1567 09:57:35.475424 ==
1568 09:57:35.478340 RX Vref Scan: 0
1569 09:57:35.478422
1570 09:57:35.478486 RX Vref 0 -> 0, step: 1
1571 09:57:35.478545
1572 09:57:35.481995 RX Delay -130 -> 252, step: 16
1573 09:57:35.485117 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1574 09:57:35.491474 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1575 09:57:35.494700 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1576 09:57:35.498305 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1577 09:57:35.501371 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1578 09:57:35.504692 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1579 09:57:35.511416 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1580 09:57:35.514834 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1581 09:57:35.518216 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1582 09:57:35.521439 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1583 09:57:35.524687 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1584 09:57:35.531287 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1585 09:57:35.534724 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1586 09:57:35.538535 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1587 09:57:35.541590 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1588 09:57:35.544825 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1589 09:57:35.548054 ==
1590 09:57:35.548140 Dram Type= 6, Freq= 0, CH_1, rank 0
1591 09:57:35.554609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1592 09:57:35.554703 ==
1593 09:57:35.554768 DQS Delay:
1594 09:57:35.558129 DQS0 = 0, DQS1 = 0
1595 09:57:35.558211 DQM Delay:
1596 09:57:35.561247 DQM0 = 82, DQM1 = 72
1597 09:57:35.561330 DQ Delay:
1598 09:57:35.564953 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1599 09:57:35.567833 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1600 09:57:35.571075 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1601 09:57:35.574757 DQ12 =85, DQ13 =77, DQ14 =77, DQ15 =77
1602 09:57:35.574844
1603 09:57:35.574907
1604 09:57:35.574965 ==
1605 09:57:35.578082 Dram Type= 6, Freq= 0, CH_1, rank 0
1606 09:57:35.581267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1607 09:57:35.581350 ==
1608 09:57:35.581413
1609 09:57:35.581473
1610 09:57:35.584520 TX Vref Scan disable
1611 09:57:35.587944 == TX Byte 0 ==
1612 09:57:35.591295 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1613 09:57:35.594368 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1614 09:57:35.598083 == TX Byte 1 ==
1615 09:57:35.601418 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1616 09:57:35.604620 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1617 09:57:35.604703 ==
1618 09:57:35.608135 Dram Type= 6, Freq= 0, CH_1, rank 0
1619 09:57:35.611008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1620 09:57:35.614278 ==
1621 09:57:35.626029 TX Vref=22, minBit 1, minWin=27, winSum=441
1622 09:57:35.629496 TX Vref=24, minBit 5, minWin=27, winSum=446
1623 09:57:35.632792 TX Vref=26, minBit 9, minWin=27, winSum=448
1624 09:57:35.636240 TX Vref=28, minBit 8, minWin=27, winSum=447
1625 09:57:35.639190 TX Vref=30, minBit 5, minWin=27, winSum=450
1626 09:57:35.642863 TX Vref=32, minBit 0, minWin=27, winSum=449
1627 09:57:35.649565 [TxChooseVref] Worse bit 5, Min win 27, Win sum 450, Final Vref 30
1628 09:57:35.649664
1629 09:57:35.652671 Final TX Range 1 Vref 30
1630 09:57:35.652755
1631 09:57:35.652819 ==
1632 09:57:35.656066 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 09:57:35.659204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 09:57:35.659287 ==
1635 09:57:35.659352
1636 09:57:35.662572
1637 09:57:35.662653 TX Vref Scan disable
1638 09:57:35.667274 == TX Byte 0 ==
1639 09:57:35.670598 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1640 09:57:35.674009 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1641 09:57:35.677403 == TX Byte 1 ==
1642 09:57:35.680815 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1643 09:57:35.683761 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1644 09:57:35.683844
1645 09:57:35.683909 [DATLAT]
1646 09:57:35.687602 Freq=800, CH1 RK0
1647 09:57:35.687684
1648 09:57:35.690774 DATLAT Default: 0xa
1649 09:57:35.690855 0, 0xFFFF, sum = 0
1650 09:57:35.693716 1, 0xFFFF, sum = 0
1651 09:57:35.693805 2, 0xFFFF, sum = 0
1652 09:57:35.697059 3, 0xFFFF, sum = 0
1653 09:57:35.697143 4, 0xFFFF, sum = 0
1654 09:57:35.700841 5, 0xFFFF, sum = 0
1655 09:57:35.700925 6, 0xFFFF, sum = 0
1656 09:57:35.703920 7, 0xFFFF, sum = 0
1657 09:57:35.704003 8, 0xFFFF, sum = 0
1658 09:57:35.707640 9, 0x0, sum = 1
1659 09:57:35.707725 10, 0x0, sum = 2
1660 09:57:35.710550 11, 0x0, sum = 3
1661 09:57:35.710633 12, 0x0, sum = 4
1662 09:57:35.710699 best_step = 10
1663 09:57:35.710758
1664 09:57:35.714210 ==
1665 09:57:35.717406 Dram Type= 6, Freq= 0, CH_1, rank 0
1666 09:57:35.720462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1667 09:57:35.720547 ==
1668 09:57:35.720612 RX Vref Scan: 1
1669 09:57:35.720671
1670 09:57:35.723838 Set Vref Range= 32 -> 127
1671 09:57:35.723919
1672 09:57:35.727122 RX Vref 32 -> 127, step: 1
1673 09:57:35.727204
1674 09:57:35.730539 RX Delay -111 -> 252, step: 8
1675 09:57:35.730620
1676 09:57:35.734001 Set Vref, RX VrefLevel [Byte0]: 32
1677 09:57:35.737573 [Byte1]: 32
1678 09:57:35.737665
1679 09:57:35.740467 Set Vref, RX VrefLevel [Byte0]: 33
1680 09:57:35.744132 [Byte1]: 33
1681 09:57:35.744247
1682 09:57:35.747274 Set Vref, RX VrefLevel [Byte0]: 34
1683 09:57:35.750413 [Byte1]: 34
1684 09:57:35.754181
1685 09:57:35.754266 Set Vref, RX VrefLevel [Byte0]: 35
1686 09:57:35.757368 [Byte1]: 35
1687 09:57:35.761838
1688 09:57:35.761925 Set Vref, RX VrefLevel [Byte0]: 36
1689 09:57:35.765098 [Byte1]: 36
1690 09:57:35.769623
1691 09:57:35.769719 Set Vref, RX VrefLevel [Byte0]: 37
1692 09:57:35.773071 [Byte1]: 37
1693 09:57:35.776988
1694 09:57:35.777081 Set Vref, RX VrefLevel [Byte0]: 38
1695 09:57:35.780656 [Byte1]: 38
1696 09:57:35.784788
1697 09:57:35.784877 Set Vref, RX VrefLevel [Byte0]: 39
1698 09:57:35.788055 [Byte1]: 39
1699 09:57:35.792183
1700 09:57:35.792308 Set Vref, RX VrefLevel [Byte0]: 40
1701 09:57:35.795917 [Byte1]: 40
1702 09:57:35.799966
1703 09:57:35.800053 Set Vref, RX VrefLevel [Byte0]: 41
1704 09:57:35.803852 [Byte1]: 41
1705 09:57:35.807497
1706 09:57:35.807578 Set Vref, RX VrefLevel [Byte0]: 42
1707 09:57:35.811480 [Byte1]: 42
1708 09:57:35.815632
1709 09:57:35.815721 Set Vref, RX VrefLevel [Byte0]: 43
1710 09:57:35.819008 [Byte1]: 43
1711 09:57:35.822997
1712 09:57:35.823086 Set Vref, RX VrefLevel [Byte0]: 44
1713 09:57:35.826292 [Byte1]: 44
1714 09:57:35.831145
1715 09:57:35.831233 Set Vref, RX VrefLevel [Byte0]: 45
1716 09:57:35.833943 [Byte1]: 45
1717 09:57:35.838468
1718 09:57:35.838561 Set Vref, RX VrefLevel [Byte0]: 46
1719 09:57:35.841706 [Byte1]: 46
1720 09:57:35.846250
1721 09:57:35.846340 Set Vref, RX VrefLevel [Byte0]: 47
1722 09:57:35.849220 [Byte1]: 47
1723 09:57:35.854037
1724 09:57:35.854135 Set Vref, RX VrefLevel [Byte0]: 48
1725 09:57:35.856868 [Byte1]: 48
1726 09:57:35.861532
1727 09:57:35.861621 Set Vref, RX VrefLevel [Byte0]: 49
1728 09:57:35.864732 [Byte1]: 49
1729 09:57:35.868858
1730 09:57:35.868947 Set Vref, RX VrefLevel [Byte0]: 50
1731 09:57:35.872048 [Byte1]: 50
1732 09:57:35.876387
1733 09:57:35.876479 Set Vref, RX VrefLevel [Byte0]: 51
1734 09:57:35.879930 [Byte1]: 51
1735 09:57:35.884194
1736 09:57:35.884325 Set Vref, RX VrefLevel [Byte0]: 52
1737 09:57:35.887675 [Byte1]: 52
1738 09:57:35.892439
1739 09:57:35.892531 Set Vref, RX VrefLevel [Byte0]: 53
1740 09:57:35.895195 [Byte1]: 53
1741 09:57:35.899496
1742 09:57:35.899583 Set Vref, RX VrefLevel [Byte0]: 54
1743 09:57:35.902729 [Byte1]: 54
1744 09:57:35.907194
1745 09:57:35.907288 Set Vref, RX VrefLevel [Byte0]: 55
1746 09:57:35.910509 [Byte1]: 55
1747 09:57:35.915084
1748 09:57:35.915174 Set Vref, RX VrefLevel [Byte0]: 56
1749 09:57:35.918119 [Byte1]: 56
1750 09:57:35.922533
1751 09:57:35.922620 Set Vref, RX VrefLevel [Byte0]: 57
1752 09:57:35.925712 [Byte1]: 57
1753 09:57:35.930095
1754 09:57:35.930193 Set Vref, RX VrefLevel [Byte0]: 58
1755 09:57:35.933716 [Byte1]: 58
1756 09:57:35.937793
1757 09:57:35.937884 Set Vref, RX VrefLevel [Byte0]: 59
1758 09:57:35.941532 [Byte1]: 59
1759 09:57:35.945547
1760 09:57:35.945636 Set Vref, RX VrefLevel [Byte0]: 60
1761 09:57:35.948708 [Byte1]: 60
1762 09:57:35.952877
1763 09:57:35.952966 Set Vref, RX VrefLevel [Byte0]: 61
1764 09:57:35.956188 [Byte1]: 61
1765 09:57:35.960452
1766 09:57:35.960543 Set Vref, RX VrefLevel [Byte0]: 62
1767 09:57:35.967228 [Byte1]: 62
1768 09:57:35.967329
1769 09:57:35.970293 Set Vref, RX VrefLevel [Byte0]: 63
1770 09:57:35.974203 [Byte1]: 63
1771 09:57:35.974295
1772 09:57:35.977253 Set Vref, RX VrefLevel [Byte0]: 64
1773 09:57:35.980379 [Byte1]: 64
1774 09:57:35.980473
1775 09:57:35.983860 Set Vref, RX VrefLevel [Byte0]: 65
1776 09:57:35.987227 [Byte1]: 65
1777 09:57:35.991298
1778 09:57:35.991387 Set Vref, RX VrefLevel [Byte0]: 66
1779 09:57:35.994874 [Byte1]: 66
1780 09:57:35.999039
1781 09:57:35.999127 Set Vref, RX VrefLevel [Byte0]: 67
1782 09:57:36.002293 [Byte1]: 67
1783 09:57:36.006597
1784 09:57:36.006688 Set Vref, RX VrefLevel [Byte0]: 68
1785 09:57:36.010137 [Byte1]: 68
1786 09:57:36.014363
1787 09:57:36.014470 Set Vref, RX VrefLevel [Byte0]: 69
1788 09:57:36.017837 [Byte1]: 69
1789 09:57:36.021977
1790 09:57:36.022069 Set Vref, RX VrefLevel [Byte0]: 70
1791 09:57:36.025247 [Byte1]: 70
1792 09:57:36.029469
1793 09:57:36.029557 Set Vref, RX VrefLevel [Byte0]: 71
1794 09:57:36.033122 [Byte1]: 71
1795 09:57:36.037343
1796 09:57:36.037432 Set Vref, RX VrefLevel [Byte0]: 72
1797 09:57:36.040375 [Byte1]: 72
1798 09:57:36.044696
1799 09:57:36.044787 Set Vref, RX VrefLevel [Byte0]: 73
1800 09:57:36.048061 [Byte1]: 73
1801 09:57:36.052815
1802 09:57:36.052909 Set Vref, RX VrefLevel [Byte0]: 74
1803 09:57:36.055603 [Byte1]: 74
1804 09:57:36.060273
1805 09:57:36.060391 Final RX Vref Byte 0 = 60 to rank0
1806 09:57:36.063441 Final RX Vref Byte 1 = 55 to rank0
1807 09:57:36.066712 Final RX Vref Byte 0 = 60 to rank1
1808 09:57:36.069988 Final RX Vref Byte 1 = 55 to rank1==
1809 09:57:36.073366 Dram Type= 6, Freq= 0, CH_1, rank 0
1810 09:57:36.079992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1811 09:57:36.080098 ==
1812 09:57:36.080164 DQS Delay:
1813 09:57:36.080266 DQS0 = 0, DQS1 = 0
1814 09:57:36.083498 DQM Delay:
1815 09:57:36.083581 DQM0 = 81, DQM1 = 71
1816 09:57:36.086923 DQ Delay:
1817 09:57:36.090049 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1818 09:57:36.090196 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1819 09:57:36.093254 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1820 09:57:36.100041 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1821 09:57:36.100159
1822 09:57:36.100251
1823 09:57:36.106462 [DQSOSCAuto] RK0, (LSB)MR18= 0xe18, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
1824 09:57:36.110097 CH1 RK0: MR19=606, MR18=E18
1825 09:57:36.116447 CH1_RK0: MR19=0x606, MR18=0xE18, DQSOSC=403, MR23=63, INC=90, DEC=60
1826 09:57:36.116552
1827 09:57:36.120050 ----->DramcWriteLeveling(PI) begin...
1828 09:57:36.120138 ==
1829 09:57:36.123919 Dram Type= 6, Freq= 0, CH_1, rank 1
1830 09:57:36.126823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1831 09:57:36.126911 ==
1832 09:57:36.130259 Write leveling (Byte 0): 26 => 26
1833 09:57:36.133486 Write leveling (Byte 1): 29 => 29
1834 09:57:36.136487 DramcWriteLeveling(PI) end<-----
1835 09:57:36.136575
1836 09:57:36.136639 ==
1837 09:57:36.139780 Dram Type= 6, Freq= 0, CH_1, rank 1
1838 09:57:36.143508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1839 09:57:36.143597 ==
1840 09:57:36.146839 [Gating] SW mode calibration
1841 09:57:36.153429 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1842 09:57:36.159804 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1843 09:57:36.163639 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1844 09:57:36.166871 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1845 09:57:36.173113 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 09:57:36.176934 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 09:57:36.179872 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 09:57:36.186799 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 09:57:36.190168 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 09:57:36.193439 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 09:57:36.196870 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 09:57:36.203320 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 09:57:36.206771 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 09:57:36.209847 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 09:57:36.216967 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 09:57:36.219907 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 09:57:36.223613 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 09:57:36.230096 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 09:57:36.233290 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 09:57:36.236756 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1861 09:57:36.243372 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 09:57:36.247126 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 09:57:36.250364 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 09:57:36.256887 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 09:57:36.259977 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 09:57:36.263321 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 09:57:36.270031 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 09:57:36.273602 0 9 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1869 09:57:36.276552 0 9 8 | B1->B0 | 302f 3434 | 1 1 | (1 1) (1 1)
1870 09:57:36.283524 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1871 09:57:36.286686 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1872 09:57:36.290835 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1873 09:57:36.293399 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1874 09:57:36.300030 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1875 09:57:36.303592 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1876 09:57:36.307062 0 10 4 | B1->B0 | 3131 2d2d | 1 1 | (1 1) (1 1)
1877 09:57:36.313684 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1878 09:57:36.316697 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 09:57:36.320072 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 09:57:36.327015 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 09:57:36.330475 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 09:57:36.333670 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 09:57:36.340052 0 11 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1884 09:57:36.343508 0 11 4 | B1->B0 | 2a2a 3737 | 0 0 | (1 1) (0 0)
1885 09:57:36.346657 0 11 8 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1886 09:57:36.353403 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1887 09:57:36.356790 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1888 09:57:36.360250 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1889 09:57:36.366949 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1890 09:57:36.370119 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1891 09:57:36.373588 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1892 09:57:36.376743 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1893 09:57:36.383728 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 09:57:36.387094 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 09:57:36.390412 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 09:57:36.396904 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 09:57:36.400115 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 09:57:36.403804 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 09:57:36.410369 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 09:57:36.413462 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 09:57:36.417027 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 09:57:36.423689 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 09:57:36.427038 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 09:57:36.430151 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 09:57:36.436949 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 09:57:36.440732 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 09:57:36.443433 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1908 09:57:36.450310 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1909 09:57:36.453692 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1910 09:57:36.457206 Total UI for P1: 0, mck2ui 16
1911 09:57:36.460026 best dqsien dly found for B0: ( 0, 14, 2)
1912 09:57:36.463390 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 09:57:36.466871 Total UI for P1: 0, mck2ui 16
1914 09:57:36.470003 best dqsien dly found for B1: ( 0, 14, 8)
1915 09:57:36.473994 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1916 09:57:36.476980 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1917 09:57:36.477071
1918 09:57:36.480552 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1919 09:57:36.483896 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1920 09:57:36.486910 [Gating] SW calibration Done
1921 09:57:36.486997 ==
1922 09:57:36.490486 Dram Type= 6, Freq= 0, CH_1, rank 1
1923 09:57:36.496741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1924 09:57:36.496844 ==
1925 09:57:36.496911 RX Vref Scan: 0
1926 09:57:36.496971
1927 09:57:36.499912 RX Vref 0 -> 0, step: 1
1928 09:57:36.499995
1929 09:57:36.503526 RX Delay -130 -> 252, step: 16
1930 09:57:36.507100 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1931 09:57:36.510152 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1932 09:57:36.514124 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1933 09:57:36.516829 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1934 09:57:36.523543 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1935 09:57:36.527086 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1936 09:57:36.529992 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1937 09:57:36.533436 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1938 09:57:36.536948 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1939 09:57:36.543607 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1940 09:57:36.546633 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1941 09:57:36.550523 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1942 09:57:36.553638 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1943 09:57:36.557277 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1944 09:57:36.563581 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1945 09:57:36.566992 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1946 09:57:36.567083 ==
1947 09:57:36.570231 Dram Type= 6, Freq= 0, CH_1, rank 1
1948 09:57:36.573338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1949 09:57:36.573425 ==
1950 09:57:36.576779 DQS Delay:
1951 09:57:36.576864 DQS0 = 0, DQS1 = 0
1952 09:57:36.576928 DQM Delay:
1953 09:57:36.580082 DQM0 = 77, DQM1 = 71
1954 09:57:36.580179 DQ Delay:
1955 09:57:36.583551 DQ0 =85, DQ1 =69, DQ2 =61, DQ3 =77
1956 09:57:36.586757 DQ4 =69, DQ5 =85, DQ6 =93, DQ7 =77
1957 09:57:36.590111 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1958 09:57:36.593717 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1959 09:57:36.593804
1960 09:57:36.593868
1961 09:57:36.593926 ==
1962 09:57:36.597192 Dram Type= 6, Freq= 0, CH_1, rank 1
1963 09:57:36.603429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1964 09:57:36.603532 ==
1965 09:57:36.603597
1966 09:57:36.603656
1967 09:57:36.603711 TX Vref Scan disable
1968 09:57:36.607130 == TX Byte 0 ==
1969 09:57:36.610454 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1970 09:57:36.613554 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1971 09:57:36.617180 == TX Byte 1 ==
1972 09:57:36.620384 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1973 09:57:36.626906 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1974 09:57:36.627012 ==
1975 09:57:36.630166 Dram Type= 6, Freq= 0, CH_1, rank 1
1976 09:57:36.633604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1977 09:57:36.633692 ==
1978 09:57:36.646641 TX Vref=22, minBit 1, minWin=28, winSum=453
1979 09:57:36.649499 TX Vref=24, minBit 1, minWin=27, winSum=456
1980 09:57:36.653238 TX Vref=26, minBit 0, minWin=28, winSum=461
1981 09:57:36.656491 TX Vref=28, minBit 1, minWin=28, winSum=460
1982 09:57:36.659444 TX Vref=30, minBit 1, minWin=28, winSum=463
1983 09:57:36.663172 TX Vref=32, minBit 5, minWin=27, winSum=460
1984 09:57:36.670194 [TxChooseVref] Worse bit 1, Min win 28, Win sum 463, Final Vref 30
1985 09:57:36.670300
1986 09:57:36.672862 Final TX Range 1 Vref 30
1987 09:57:36.672961
1988 09:57:36.673038 ==
1989 09:57:36.676599 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 09:57:36.679670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 09:57:36.679759 ==
1992 09:57:36.679825
1993 09:57:36.679884
1994 09:57:36.682900 TX Vref Scan disable
1995 09:57:36.686783 == TX Byte 0 ==
1996 09:57:36.690078 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1997 09:57:36.693236 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1998 09:57:36.696395 == TX Byte 1 ==
1999 09:57:36.699637 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2000 09:57:36.702906 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2001 09:57:36.706416
2002 09:57:36.706509 [DATLAT]
2003 09:57:36.706576 Freq=800, CH1 RK1
2004 09:57:36.706636
2005 09:57:36.709701 DATLAT Default: 0xa
2006 09:57:36.709784 0, 0xFFFF, sum = 0
2007 09:57:36.712920 1, 0xFFFF, sum = 0
2008 09:57:36.713030 2, 0xFFFF, sum = 0
2009 09:57:36.716560 3, 0xFFFF, sum = 0
2010 09:57:36.716644 4, 0xFFFF, sum = 0
2011 09:57:36.719595 5, 0xFFFF, sum = 0
2012 09:57:36.719680 6, 0xFFFF, sum = 0
2013 09:57:36.722811 7, 0xFFFF, sum = 0
2014 09:57:36.726187 8, 0xFFFF, sum = 0
2015 09:57:36.726274 9, 0x0, sum = 1
2016 09:57:36.726340 10, 0x0, sum = 2
2017 09:57:36.729809 11, 0x0, sum = 3
2018 09:57:36.729894 12, 0x0, sum = 4
2019 09:57:36.732795 best_step = 10
2020 09:57:36.732880
2021 09:57:36.732945 ==
2022 09:57:36.736118 Dram Type= 6, Freq= 0, CH_1, rank 1
2023 09:57:36.739730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2024 09:57:36.739817 ==
2025 09:57:36.742895 RX Vref Scan: 0
2026 09:57:36.742980
2027 09:57:36.743045 RX Vref 0 -> 0, step: 1
2028 09:57:36.743106
2029 09:57:36.746449 RX Delay -111 -> 252, step: 8
2030 09:57:36.753438 iDelay=209, Bit 0, Center 84 (-39 ~ 208) 248
2031 09:57:36.756735 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2032 09:57:36.760102 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2033 09:57:36.763285 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2034 09:57:36.766722 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2035 09:57:36.773794 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2036 09:57:36.776551 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2037 09:57:36.779985 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2038 09:57:36.783670 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2039 09:57:36.786802 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2040 09:57:36.790282 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2041 09:57:36.796730 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2042 09:57:36.800383 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2043 09:57:36.803582 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2044 09:57:36.806863 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2045 09:57:36.813278 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2046 09:57:36.813385 ==
2047 09:57:36.816834 Dram Type= 6, Freq= 0, CH_1, rank 1
2048 09:57:36.819856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2049 09:57:36.819969 ==
2050 09:57:36.820064 DQS Delay:
2051 09:57:36.823710 DQS0 = 0, DQS1 = 0
2052 09:57:36.823817 DQM Delay:
2053 09:57:36.826724 DQM0 = 78, DQM1 = 73
2054 09:57:36.826807 DQ Delay:
2055 09:57:36.830207 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =72
2056 09:57:36.833726 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2057 09:57:36.836719 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
2058 09:57:36.839960 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2059 09:57:36.840049
2060 09:57:36.840113
2061 09:57:36.846876 [DQSOSCAuto] RK1, (LSB)MR18= 0x243c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
2062 09:57:36.850026 CH1 RK1: MR19=606, MR18=243C
2063 09:57:36.856638 CH1_RK1: MR19=0x606, MR18=0x243C, DQSOSC=394, MR23=63, INC=95, DEC=63
2064 09:57:36.860063 [RxdqsGatingPostProcess] freq 800
2065 09:57:36.866617 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2066 09:57:36.866742 Pre-setting of DQS Precalculation
2067 09:57:36.873393 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2068 09:57:36.880164 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2069 09:57:36.886812 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2070 09:57:36.886930
2071 09:57:36.886997
2072 09:57:36.890596 [Calibration Summary] 1600 Mbps
2073 09:57:36.893926 CH 0, Rank 0
2074 09:57:36.894014 SW Impedance : PASS
2075 09:57:36.896810 DUTY Scan : NO K
2076 09:57:36.896895 ZQ Calibration : PASS
2077 09:57:36.900418 Jitter Meter : NO K
2078 09:57:36.903597 CBT Training : PASS
2079 09:57:36.903682 Write leveling : PASS
2080 09:57:36.907136 RX DQS gating : PASS
2081 09:57:36.910155 RX DQ/DQS(RDDQC) : PASS
2082 09:57:36.910240 TX DQ/DQS : PASS
2083 09:57:36.913884 RX DATLAT : PASS
2084 09:57:36.916948 RX DQ/DQS(Engine): PASS
2085 09:57:36.917031 TX OE : NO K
2086 09:57:36.920444 All Pass.
2087 09:57:36.920527
2088 09:57:36.920593 CH 0, Rank 1
2089 09:57:36.923748 SW Impedance : PASS
2090 09:57:36.923831 DUTY Scan : NO K
2091 09:57:36.926871 ZQ Calibration : PASS
2092 09:57:36.930402 Jitter Meter : NO K
2093 09:57:36.930491 CBT Training : PASS
2094 09:57:36.934015 Write leveling : PASS
2095 09:57:36.934098 RX DQS gating : PASS
2096 09:57:36.937124 RX DQ/DQS(RDDQC) : PASS
2097 09:57:36.940171 TX DQ/DQS : PASS
2098 09:57:36.940297 RX DATLAT : PASS
2099 09:57:36.943529 RX DQ/DQS(Engine): PASS
2100 09:57:36.946754 TX OE : NO K
2101 09:57:36.946839 All Pass.
2102 09:57:36.946903
2103 09:57:36.946963 CH 1, Rank 0
2104 09:57:36.950454 SW Impedance : PASS
2105 09:57:36.953791 DUTY Scan : NO K
2106 09:57:36.953876 ZQ Calibration : PASS
2107 09:57:36.956892 Jitter Meter : NO K
2108 09:57:36.960404 CBT Training : PASS
2109 09:57:36.960489 Write leveling : PASS
2110 09:57:36.963973 RX DQS gating : PASS
2111 09:57:36.967268 RX DQ/DQS(RDDQC) : PASS
2112 09:57:36.967353 TX DQ/DQS : PASS
2113 09:57:36.970420 RX DATLAT : PASS
2114 09:57:36.973475 RX DQ/DQS(Engine): PASS
2115 09:57:36.973560 TX OE : NO K
2116 09:57:36.973625 All Pass.
2117 09:57:36.973686
2118 09:57:36.977217 CH 1, Rank 1
2119 09:57:36.980393 SW Impedance : PASS
2120 09:57:36.980480 DUTY Scan : NO K
2121 09:57:36.983389 ZQ Calibration : PASS
2122 09:57:36.983484 Jitter Meter : NO K
2123 09:57:36.987563 CBT Training : PASS
2124 09:57:36.990279 Write leveling : PASS
2125 09:57:36.990365 RX DQS gating : PASS
2126 09:57:36.993514 RX DQ/DQS(RDDQC) : PASS
2127 09:57:36.997091 TX DQ/DQS : PASS
2128 09:57:36.997180 RX DATLAT : PASS
2129 09:57:37.000603 RX DQ/DQS(Engine): PASS
2130 09:57:37.003602 TX OE : NO K
2131 09:57:37.003686 All Pass.
2132 09:57:37.003751
2133 09:57:37.007067 DramC Write-DBI off
2134 09:57:37.007151 PER_BANK_REFRESH: Hybrid Mode
2135 09:57:37.010387 TX_TRACKING: ON
2136 09:57:37.013422 [GetDramInforAfterCalByMRR] Vendor 6.
2137 09:57:37.016753 [GetDramInforAfterCalByMRR] Revision 606.
2138 09:57:37.020406 [GetDramInforAfterCalByMRR] Revision 2 0.
2139 09:57:37.020496 MR0 0x3b3b
2140 09:57:37.023564 MR8 0x5151
2141 09:57:37.026839 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2142 09:57:37.026933
2143 09:57:37.026998 MR0 0x3b3b
2144 09:57:37.027058 MR8 0x5151
2145 09:57:37.030157 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2146 09:57:37.033573
2147 09:57:37.040372 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2148 09:57:37.043610 [FAST_K] Save calibration result to emmc
2149 09:57:37.047177 [FAST_K] Save calibration result to emmc
2150 09:57:37.050573 dram_init: config_dvfs: 1
2151 09:57:37.053487 dramc_set_vcore_voltage set vcore to 662500
2152 09:57:37.056839 Read voltage for 1200, 2
2153 09:57:37.056925 Vio18 = 0
2154 09:57:37.060372 Vcore = 662500
2155 09:57:37.060456 Vdram = 0
2156 09:57:37.060520 Vddq = 0
2157 09:57:37.060578 Vmddr = 0
2158 09:57:37.067051 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2159 09:57:37.073585 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2160 09:57:37.073686 MEM_TYPE=3, freq_sel=15
2161 09:57:37.076969 sv_algorithm_assistance_LP4_1600
2162 09:57:37.080347 ============ PULL DRAM RESETB DOWN ============
2163 09:57:37.087394 ========== PULL DRAM RESETB DOWN end =========
2164 09:57:37.090845 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2165 09:57:37.093724 ===================================
2166 09:57:37.097376 LPDDR4 DRAM CONFIGURATION
2167 09:57:37.100450 ===================================
2168 09:57:37.100538 EX_ROW_EN[0] = 0x0
2169 09:57:37.103629 EX_ROW_EN[1] = 0x0
2170 09:57:37.103713 LP4Y_EN = 0x0
2171 09:57:37.108123 WORK_FSP = 0x0
2172 09:57:37.108273 WL = 0x4
2173 09:57:37.110383 RL = 0x4
2174 09:57:37.110464 BL = 0x2
2175 09:57:37.113782 RPST = 0x0
2176 09:57:37.113881 RD_PRE = 0x0
2177 09:57:37.116898 WR_PRE = 0x1
2178 09:57:37.116985 WR_PST = 0x0
2179 09:57:37.120462 DBI_WR = 0x0
2180 09:57:37.123681 DBI_RD = 0x0
2181 09:57:37.123792 OTF = 0x1
2182 09:57:37.127208 ===================================
2183 09:57:37.130362 ===================================
2184 09:57:37.130445 ANA top config
2185 09:57:37.133720 ===================================
2186 09:57:37.136750 DLL_ASYNC_EN = 0
2187 09:57:37.140190 ALL_SLAVE_EN = 0
2188 09:57:37.143465 NEW_RANK_MODE = 1
2189 09:57:37.146599 DLL_IDLE_MODE = 1
2190 09:57:37.146682 LP45_APHY_COMB_EN = 1
2191 09:57:37.150013 TX_ODT_DIS = 1
2192 09:57:37.153348 NEW_8X_MODE = 1
2193 09:57:37.156667 ===================================
2194 09:57:37.159992 ===================================
2195 09:57:37.163630 data_rate = 2400
2196 09:57:37.166720 CKR = 1
2197 09:57:37.166807 DQ_P2S_RATIO = 8
2198 09:57:37.170003 ===================================
2199 09:57:37.173654 CA_P2S_RATIO = 8
2200 09:57:37.176799 DQ_CA_OPEN = 0
2201 09:57:37.179893 DQ_SEMI_OPEN = 0
2202 09:57:37.183796 CA_SEMI_OPEN = 0
2203 09:57:37.186784 CA_FULL_RATE = 0
2204 09:57:37.186872 DQ_CKDIV4_EN = 0
2205 09:57:37.190224 CA_CKDIV4_EN = 0
2206 09:57:37.193397 CA_PREDIV_EN = 0
2207 09:57:37.196653 PH8_DLY = 17
2208 09:57:37.200162 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2209 09:57:37.203434 DQ_AAMCK_DIV = 4
2210 09:57:37.203520 CA_AAMCK_DIV = 4
2211 09:57:37.206931 CA_ADMCK_DIV = 4
2212 09:57:37.209889 DQ_TRACK_CA_EN = 0
2213 09:57:37.213251 CA_PICK = 1200
2214 09:57:37.216716 CA_MCKIO = 1200
2215 09:57:37.220173 MCKIO_SEMI = 0
2216 09:57:37.223491 PLL_FREQ = 2366
2217 09:57:37.223604 DQ_UI_PI_RATIO = 32
2218 09:57:37.226502 CA_UI_PI_RATIO = 0
2219 09:57:37.230231 ===================================
2220 09:57:37.233496 ===================================
2221 09:57:37.236972 memory_type:LPDDR4
2222 09:57:37.240140 GP_NUM : 10
2223 09:57:37.240252 SRAM_EN : 1
2224 09:57:37.243479 MD32_EN : 0
2225 09:57:37.246749 ===================================
2226 09:57:37.246834 [ANA_INIT] >>>>>>>>>>>>>>
2227 09:57:37.250259 <<<<<< [CONFIGURE PHASE]: ANA_TX
2228 09:57:37.253657 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2229 09:57:37.256804 ===================================
2230 09:57:37.259985 data_rate = 2400,PCW = 0X5b00
2231 09:57:37.263192 ===================================
2232 09:57:37.267046 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2233 09:57:37.273495 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2234 09:57:37.276664 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2235 09:57:37.283470 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2236 09:57:37.287008 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2237 09:57:37.290032 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2238 09:57:37.293601 [ANA_INIT] flow start
2239 09:57:37.293687 [ANA_INIT] PLL >>>>>>>>
2240 09:57:37.296585 [ANA_INIT] PLL <<<<<<<<
2241 09:57:37.299960 [ANA_INIT] MIDPI >>>>>>>>
2242 09:57:37.300046 [ANA_INIT] MIDPI <<<<<<<<
2243 09:57:37.303790 [ANA_INIT] DLL >>>>>>>>
2244 09:57:37.306652 [ANA_INIT] DLL <<<<<<<<
2245 09:57:37.306736 [ANA_INIT] flow end
2246 09:57:37.310231 ============ LP4 DIFF to SE enter ============
2247 09:57:37.316982 ============ LP4 DIFF to SE exit ============
2248 09:57:37.317095 [ANA_INIT] <<<<<<<<<<<<<
2249 09:57:37.320241 [Flow] Enable top DCM control >>>>>
2250 09:57:37.323882 [Flow] Enable top DCM control <<<<<
2251 09:57:37.327013 Enable DLL master slave shuffle
2252 09:57:37.333655 ==============================================================
2253 09:57:37.333761 Gating Mode config
2254 09:57:37.340563 ==============================================================
2255 09:57:37.343873 Config description:
2256 09:57:37.353360 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2257 09:57:37.360154 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2258 09:57:37.363803 SELPH_MODE 0: By rank 1: By Phase
2259 09:57:37.369947 ==============================================================
2260 09:57:37.373863 GAT_TRACK_EN = 1
2261 09:57:37.373959 RX_GATING_MODE = 2
2262 09:57:37.377070 RX_GATING_TRACK_MODE = 2
2263 09:57:37.380176 SELPH_MODE = 1
2264 09:57:37.383441 PICG_EARLY_EN = 1
2265 09:57:37.386956 VALID_LAT_VALUE = 1
2266 09:57:37.393393 ==============================================================
2267 09:57:37.397060 Enter into Gating configuration >>>>
2268 09:57:37.400132 Exit from Gating configuration <<<<
2269 09:57:37.403530 Enter into DVFS_PRE_config >>>>>
2270 09:57:37.413466 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2271 09:57:37.416815 Exit from DVFS_PRE_config <<<<<
2272 09:57:37.420192 Enter into PICG configuration >>>>
2273 09:57:37.423533 Exit from PICG configuration <<<<
2274 09:57:37.426764 [RX_INPUT] configuration >>>>>
2275 09:57:37.426854 [RX_INPUT] configuration <<<<<
2276 09:57:37.433365 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2277 09:57:37.440081 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2278 09:57:37.446491 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2279 09:57:37.449961 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2280 09:57:37.457299 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2281 09:57:37.463630 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2282 09:57:37.466928 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2283 09:57:37.470206 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2284 09:57:37.476683 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2285 09:57:37.480178 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2286 09:57:37.483320 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2287 09:57:37.490363 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2288 09:57:37.493367 ===================================
2289 09:57:37.493460 LPDDR4 DRAM CONFIGURATION
2290 09:57:37.496496 ===================================
2291 09:57:37.500079 EX_ROW_EN[0] = 0x0
2292 09:57:37.500191 EX_ROW_EN[1] = 0x0
2293 09:57:37.503380 LP4Y_EN = 0x0
2294 09:57:37.503463 WORK_FSP = 0x0
2295 09:57:37.506715 WL = 0x4
2296 09:57:37.510196 RL = 0x4
2297 09:57:37.510281 BL = 0x2
2298 09:57:37.513140 RPST = 0x0
2299 09:57:37.513224 RD_PRE = 0x0
2300 09:57:37.516779 WR_PRE = 0x1
2301 09:57:37.516870 WR_PST = 0x0
2302 09:57:37.519954 DBI_WR = 0x0
2303 09:57:37.520068 DBI_RD = 0x0
2304 09:57:37.523630 OTF = 0x1
2305 09:57:37.526676 ===================================
2306 09:57:37.530020 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2307 09:57:37.533259 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2308 09:57:37.536920 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2309 09:57:37.540384 ===================================
2310 09:57:37.543519 LPDDR4 DRAM CONFIGURATION
2311 09:57:37.546524 ===================================
2312 09:57:37.550642 EX_ROW_EN[0] = 0x10
2313 09:57:37.550733 EX_ROW_EN[1] = 0x0
2314 09:57:37.553394 LP4Y_EN = 0x0
2315 09:57:37.553477 WORK_FSP = 0x0
2316 09:57:37.556995 WL = 0x4
2317 09:57:37.557078 RL = 0x4
2318 09:57:37.560082 BL = 0x2
2319 09:57:37.560189 RPST = 0x0
2320 09:57:37.563292 RD_PRE = 0x0
2321 09:57:37.563374 WR_PRE = 0x1
2322 09:57:37.566529 WR_PST = 0x0
2323 09:57:37.566612 DBI_WR = 0x0
2324 09:57:37.570046 DBI_RD = 0x0
2325 09:57:37.573366 OTF = 0x1
2326 09:57:37.576769 ===================================
2327 09:57:37.579795 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2328 09:57:37.579883 ==
2329 09:57:37.583357 Dram Type= 6, Freq= 0, CH_0, rank 0
2330 09:57:37.589815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2331 09:57:37.589928 ==
2332 09:57:37.589993 [Duty_Offset_Calibration]
2333 09:57:37.592986 B0:2 B1:0 CA:3
2334 09:57:37.593068
2335 09:57:37.596677 [DutyScan_Calibration_Flow] k_type=0
2336 09:57:37.605511
2337 09:57:37.605620 ==CLK 0==
2338 09:57:37.609192 Final CLK duty delay cell = 0
2339 09:57:37.612461 [0] MAX Duty = 5062%(X100), DQS PI = 20
2340 09:57:37.615395 [0] MIN Duty = 4906%(X100), DQS PI = 54
2341 09:57:37.615477 [0] AVG Duty = 4984%(X100)
2342 09:57:37.618838
2343 09:57:37.622097 CH0 CLK Duty spec in!! Max-Min= 156%
2344 09:57:37.625534 [DutyScan_Calibration_Flow] ====Done====
2345 09:57:37.625620
2346 09:57:37.628759 [DutyScan_Calibration_Flow] k_type=1
2347 09:57:37.644906
2348 09:57:37.645037 ==DQS 0 ==
2349 09:57:37.648054 Final DQS duty delay cell = 0
2350 09:57:37.651264 [0] MAX Duty = 5062%(X100), DQS PI = 12
2351 09:57:37.654811 [0] MIN Duty = 4907%(X100), DQS PI = 2
2352 09:57:37.657990 [0] AVG Duty = 4984%(X100)
2353 09:57:37.658075
2354 09:57:37.658139 ==DQS 1 ==
2355 09:57:37.661714 Final DQS duty delay cell = 0
2356 09:57:37.664660 [0] MAX Duty = 5125%(X100), DQS PI = 26
2357 09:57:37.667998 [0] MIN Duty = 5031%(X100), DQS PI = 2
2358 09:57:37.671476 [0] AVG Duty = 5078%(X100)
2359 09:57:37.671559
2360 09:57:37.674819 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2361 09:57:37.674901
2362 09:57:37.677951 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2363 09:57:37.681475 [DutyScan_Calibration_Flow] ====Done====
2364 09:57:37.681560
2365 09:57:37.684372 [DutyScan_Calibration_Flow] k_type=3
2366 09:57:37.701295
2367 09:57:37.701443 ==DQM 0 ==
2368 09:57:37.704612 Final DQM duty delay cell = 0
2369 09:57:37.707655 [0] MAX Duty = 5124%(X100), DQS PI = 26
2370 09:57:37.711476 [0] MIN Duty = 4907%(X100), DQS PI = 0
2371 09:57:37.711578 [0] AVG Duty = 5015%(X100)
2372 09:57:37.714438
2373 09:57:37.714523 ==DQM 1 ==
2374 09:57:37.718273 Final DQM duty delay cell = 0
2375 09:57:37.721433 [0] MAX Duty = 4969%(X100), DQS PI = 52
2376 09:57:37.724420 [0] MIN Duty = 4876%(X100), DQS PI = 8
2377 09:57:37.724532 [0] AVG Duty = 4922%(X100)
2378 09:57:37.727638
2379 09:57:37.731172 CH0 DQM 0 Duty spec in!! Max-Min= 217%
2380 09:57:37.731255
2381 09:57:37.734627 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2382 09:57:37.737963 [DutyScan_Calibration_Flow] ====Done====
2383 09:57:37.738055
2384 09:57:37.741335 [DutyScan_Calibration_Flow] k_type=2
2385 09:57:37.756104
2386 09:57:37.756278 ==DQ 0 ==
2387 09:57:37.759244 Final DQ duty delay cell = -4
2388 09:57:37.762384 [-4] MAX Duty = 5031%(X100), DQS PI = 18
2389 09:57:37.765868 [-4] MIN Duty = 4907%(X100), DQS PI = 42
2390 09:57:37.769100 [-4] AVG Duty = 4969%(X100)
2391 09:57:37.769186
2392 09:57:37.769250 ==DQ 1 ==
2393 09:57:37.772953 Final DQ duty delay cell = -4
2394 09:57:37.775919 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2395 09:57:37.779635 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2396 09:57:37.782985 [-4] AVG Duty = 4938%(X100)
2397 09:57:37.783075
2398 09:57:37.785810 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2399 09:57:37.785894
2400 09:57:37.789131 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2401 09:57:37.792527 [DutyScan_Calibration_Flow] ====Done====
2402 09:57:37.792616 ==
2403 09:57:37.795795 Dram Type= 6, Freq= 0, CH_1, rank 0
2404 09:57:37.799157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2405 09:57:37.799246 ==
2406 09:57:37.802722 [Duty_Offset_Calibration]
2407 09:57:37.802806 B0:1 B1:-2 CA:0
2408 09:57:37.802871
2409 09:57:37.805697 [DutyScan_Calibration_Flow] k_type=0
2410 09:57:37.816947
2411 09:57:37.817091 ==CLK 0==
2412 09:57:37.820006 Final CLK duty delay cell = 0
2413 09:57:37.823510 [0] MAX Duty = 5062%(X100), DQS PI = 30
2414 09:57:37.826484 [0] MIN Duty = 4876%(X100), DQS PI = 2
2415 09:57:37.826573 [0] AVG Duty = 4969%(X100)
2416 09:57:37.826641
2417 09:57:37.830592 CH1 CLK Duty spec in!! Max-Min= 186%
2418 09:57:37.836528 [DutyScan_Calibration_Flow] ====Done====
2419 09:57:37.836625
2420 09:57:37.839682 [DutyScan_Calibration_Flow] k_type=1
2421 09:57:37.854921
2422 09:57:37.855064 ==DQS 0 ==
2423 09:57:37.858482 Final DQS duty delay cell = -4
2424 09:57:37.861621 [-4] MAX Duty = 5000%(X100), DQS PI = 24
2425 09:57:37.864976 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2426 09:57:37.868263 [-4] AVG Duty = 4953%(X100)
2427 09:57:37.868353
2428 09:57:37.868418 ==DQS 1 ==
2429 09:57:37.871788 Final DQS duty delay cell = 0
2430 09:57:37.875164 [0] MAX Duty = 5093%(X100), DQS PI = 0
2431 09:57:37.878288 [0] MIN Duty = 4844%(X100), DQS PI = 26
2432 09:57:37.881880 [0] AVG Duty = 4968%(X100)
2433 09:57:37.881968
2434 09:57:37.884961 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2435 09:57:37.885042
2436 09:57:37.888197 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2437 09:57:37.891565 [DutyScan_Calibration_Flow] ====Done====
2438 09:57:37.891648
2439 09:57:37.895274 [DutyScan_Calibration_Flow] k_type=3
2440 09:57:37.911917
2441 09:57:37.912070 ==DQM 0 ==
2442 09:57:37.915177 Final DQM duty delay cell = 0
2443 09:57:37.918521 [0] MAX Duty = 5000%(X100), DQS PI = 24
2444 09:57:37.921575 [0] MIN Duty = 4844%(X100), DQS PI = 56
2445 09:57:37.924775 [0] AVG Duty = 4922%(X100)
2446 09:57:37.924871
2447 09:57:37.924947 ==DQM 1 ==
2448 09:57:37.928309 Final DQM duty delay cell = 0
2449 09:57:37.931798 [0] MAX Duty = 5031%(X100), DQS PI = 36
2450 09:57:37.934823 [0] MIN Duty = 4907%(X100), DQS PI = 0
2451 09:57:37.934953 [0] AVG Duty = 4969%(X100)
2452 09:57:37.938039
2453 09:57:37.941471 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2454 09:57:37.941561
2455 09:57:37.944628 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2456 09:57:37.948406 [DutyScan_Calibration_Flow] ====Done====
2457 09:57:37.948489
2458 09:57:37.951467 [DutyScan_Calibration_Flow] k_type=2
2459 09:57:37.967969
2460 09:57:37.968119 ==DQ 0 ==
2461 09:57:37.971381 Final DQ duty delay cell = 0
2462 09:57:37.974724 [0] MAX Duty = 5093%(X100), DQS PI = 32
2463 09:57:37.977797 [0] MIN Duty = 4938%(X100), DQS PI = 54
2464 09:57:37.977883 [0] AVG Duty = 5015%(X100)
2465 09:57:37.980942
2466 09:57:37.981027 ==DQ 1 ==
2467 09:57:37.984588 Final DQ duty delay cell = 0
2468 09:57:37.987794 [0] MAX Duty = 5125%(X100), DQS PI = 36
2469 09:57:37.990883 [0] MIN Duty = 4969%(X100), DQS PI = 26
2470 09:57:37.990968 [0] AVG Duty = 5047%(X100)
2471 09:57:37.994716
2472 09:57:37.997735 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2473 09:57:37.997818
2474 09:57:38.001594 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2475 09:57:38.004683 [DutyScan_Calibration_Flow] ====Done====
2476 09:57:38.007922 nWR fixed to 30
2477 09:57:38.008032 [ModeRegInit_LP4] CH0 RK0
2478 09:57:38.011298 [ModeRegInit_LP4] CH0 RK1
2479 09:57:38.014267 [ModeRegInit_LP4] CH1 RK0
2480 09:57:38.017514 [ModeRegInit_LP4] CH1 RK1
2481 09:57:38.017600 match AC timing 7
2482 09:57:38.021566 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2483 09:57:38.027988 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2484 09:57:38.031204 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2485 09:57:38.034700 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2486 09:57:38.041564 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2487 09:57:38.041670 ==
2488 09:57:38.044483 Dram Type= 6, Freq= 0, CH_0, rank 0
2489 09:57:38.047928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2490 09:57:38.048015 ==
2491 09:57:38.054414 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2492 09:57:38.060994 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2493 09:57:38.068182 [CA 0] Center 40 (10~71) winsize 62
2494 09:57:38.071256 [CA 1] Center 39 (9~70) winsize 62
2495 09:57:38.074732 [CA 2] Center 36 (6~66) winsize 61
2496 09:57:38.078070 [CA 3] Center 35 (5~66) winsize 62
2497 09:57:38.081219 [CA 4] Center 34 (4~65) winsize 62
2498 09:57:38.085053 [CA 5] Center 33 (3~63) winsize 61
2499 09:57:38.085141
2500 09:57:38.087734 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2501 09:57:38.087814
2502 09:57:38.091098 [CATrainingPosCal] consider 1 rank data
2503 09:57:38.094777 u2DelayCellTimex100 = 270/100 ps
2504 09:57:38.098247 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2505 09:57:38.104582 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2506 09:57:38.107748 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2507 09:57:38.111449 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2508 09:57:38.114421 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2509 09:57:38.117840 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2510 09:57:38.117926
2511 09:57:38.121636 CA PerBit enable=1, Macro0, CA PI delay=33
2512 09:57:38.121743
2513 09:57:38.125085 [CBTSetCACLKResult] CA Dly = 33
2514 09:57:38.125167 CS Dly: 7 (0~38)
2515 09:57:38.127805 ==
2516 09:57:38.131174 Dram Type= 6, Freq= 0, CH_0, rank 1
2517 09:57:38.134597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 09:57:38.134681 ==
2519 09:57:38.137869 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2520 09:57:38.144426 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2521 09:57:38.154126 [CA 0] Center 40 (10~70) winsize 61
2522 09:57:38.157500 [CA 1] Center 39 (9~70) winsize 62
2523 09:57:38.160687 [CA 2] Center 35 (5~66) winsize 62
2524 09:57:38.164005 [CA 3] Center 35 (5~66) winsize 62
2525 09:57:38.167510 [CA 4] Center 34 (4~65) winsize 62
2526 09:57:38.170600 [CA 5] Center 33 (3~63) winsize 61
2527 09:57:38.170684
2528 09:57:38.173978 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2529 09:57:38.174059
2530 09:57:38.177414 [CATrainingPosCal] consider 2 rank data
2531 09:57:38.180687 u2DelayCellTimex100 = 270/100 ps
2532 09:57:38.184182 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2533 09:57:38.190563 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2534 09:57:38.194099 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2535 09:57:38.197272 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2536 09:57:38.200478 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2537 09:57:38.203786 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2538 09:57:38.203983
2539 09:57:38.207410 CA PerBit enable=1, Macro0, CA PI delay=33
2540 09:57:38.207491
2541 09:57:38.210562 [CBTSetCACLKResult] CA Dly = 33
2542 09:57:38.210645 CS Dly: 8 (0~40)
2543 09:57:38.214204
2544 09:57:38.217140 ----->DramcWriteLeveling(PI) begin...
2545 09:57:38.217225 ==
2546 09:57:38.220959 Dram Type= 6, Freq= 0, CH_0, rank 0
2547 09:57:38.223748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2548 09:57:38.223844 ==
2549 09:57:38.227152 Write leveling (Byte 0): 35 => 35
2550 09:57:38.230601 Write leveling (Byte 1): 29 => 29
2551 09:57:38.233847 DramcWriteLeveling(PI) end<-----
2552 09:57:38.233932
2553 09:57:38.233995 ==
2554 09:57:38.237005 Dram Type= 6, Freq= 0, CH_0, rank 0
2555 09:57:38.240682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2556 09:57:38.240766 ==
2557 09:57:38.243882 [Gating] SW mode calibration
2558 09:57:38.250825 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2559 09:57:38.257224 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2560 09:57:38.260449 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2561 09:57:38.263778 0 15 4 | B1->B0 | 2625 3434 | 1 0 | (0 0) (0 0)
2562 09:57:38.270552 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2563 09:57:38.273738 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2564 09:57:38.277236 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2565 09:57:38.283608 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2566 09:57:38.287018 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2567 09:57:38.290455 0 15 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2568 09:57:38.293769 1 0 0 | B1->B0 | 3333 2e2e | 1 0 | (1 0) (0 1)
2569 09:57:38.300712 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2570 09:57:38.303886 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2571 09:57:38.307117 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2572 09:57:38.313485 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2573 09:57:38.316803 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2574 09:57:38.320808 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2575 09:57:38.326909 1 0 28 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
2576 09:57:38.330487 1 1 0 | B1->B0 | 2727 3434 | 0 0 | (0 0) (0 0)
2577 09:57:38.333445 1 1 4 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
2578 09:57:38.340252 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2579 09:57:38.343589 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2580 09:57:38.347031 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2581 09:57:38.353582 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2582 09:57:38.357035 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2583 09:57:38.360327 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2584 09:57:38.366906 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2585 09:57:38.370398 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2586 09:57:38.373697 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2587 09:57:38.380506 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 09:57:38.383676 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 09:57:38.386924 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 09:57:38.390373 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 09:57:38.397000 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 09:57:38.400335 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 09:57:38.403788 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 09:57:38.410309 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 09:57:38.413535 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 09:57:38.417161 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 09:57:38.423975 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 09:57:38.426810 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 09:57:38.430193 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2600 09:57:38.437210 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2601 09:57:38.440322 Total UI for P1: 0, mck2ui 16
2602 09:57:38.443506 best dqsien dly found for B0: ( 1, 3, 28)
2603 09:57:38.447326 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2604 09:57:38.450246 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 09:57:38.453913 Total UI for P1: 0, mck2ui 16
2606 09:57:38.457239 best dqsien dly found for B1: ( 1, 4, 2)
2607 09:57:38.460509 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2608 09:57:38.463539 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2609 09:57:38.463623
2610 09:57:38.467214 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2611 09:57:38.473579 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2612 09:57:38.473673 [Gating] SW calibration Done
2613 09:57:38.473739 ==
2614 09:57:38.477083 Dram Type= 6, Freq= 0, CH_0, rank 0
2615 09:57:38.483508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2616 09:57:38.483611 ==
2617 09:57:38.483677 RX Vref Scan: 0
2618 09:57:38.483738
2619 09:57:38.487401 RX Vref 0 -> 0, step: 1
2620 09:57:38.487486
2621 09:57:38.490609 RX Delay -40 -> 252, step: 8
2622 09:57:38.493806 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2623 09:57:38.497081 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2624 09:57:38.500597 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2625 09:57:38.507039 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2626 09:57:38.510078 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2627 09:57:38.513615 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2628 09:57:38.517123 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2629 09:57:38.520043 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2630 09:57:38.523502 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2631 09:57:38.530763 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2632 09:57:38.533774 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2633 09:57:38.536934 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2634 09:57:38.540234 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2635 09:57:38.543918 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2636 09:57:38.550193 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2637 09:57:38.553825 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2638 09:57:38.553917 ==
2639 09:57:38.556835 Dram Type= 6, Freq= 0, CH_0, rank 0
2640 09:57:38.560442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2641 09:57:38.560528 ==
2642 09:57:38.563665 DQS Delay:
2643 09:57:38.563747 DQS0 = 0, DQS1 = 0
2644 09:57:38.563810 DQM Delay:
2645 09:57:38.566863 DQM0 = 112, DQM1 = 102
2646 09:57:38.566948 DQ Delay:
2647 09:57:38.570369 DQ0 =111, DQ1 =111, DQ2 =115, DQ3 =107
2648 09:57:38.573745 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2649 09:57:38.576748 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =99
2650 09:57:38.580667 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2651 09:57:38.583775
2652 09:57:38.583864
2653 09:57:38.583928 ==
2654 09:57:38.587095 Dram Type= 6, Freq= 0, CH_0, rank 0
2655 09:57:38.590210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2656 09:57:38.590295 ==
2657 09:57:38.590359
2658 09:57:38.590419
2659 09:57:38.593729 TX Vref Scan disable
2660 09:57:38.593812 == TX Byte 0 ==
2661 09:57:38.600419 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2662 09:57:38.603390 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2663 09:57:38.603478 == TX Byte 1 ==
2664 09:57:38.610411 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2665 09:57:38.613434 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2666 09:57:38.613524 ==
2667 09:57:38.616699 Dram Type= 6, Freq= 0, CH_0, rank 0
2668 09:57:38.620366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2669 09:57:38.620458 ==
2670 09:57:38.633436 TX Vref=22, minBit 0, minWin=25, winSum=419
2671 09:57:38.636210 TX Vref=24, minBit 5, minWin=25, winSum=423
2672 09:57:38.639825 TX Vref=26, minBit 0, minWin=26, winSum=427
2673 09:57:38.643303 TX Vref=28, minBit 4, minWin=26, winSum=435
2674 09:57:38.646603 TX Vref=30, minBit 0, minWin=27, winSum=438
2675 09:57:38.649755 TX Vref=32, minBit 2, minWin=26, winSum=434
2676 09:57:38.656338 [TxChooseVref] Worse bit 0, Min win 27, Win sum 438, Final Vref 30
2677 09:57:38.656446
2678 09:57:38.660058 Final TX Range 1 Vref 30
2679 09:57:38.660145
2680 09:57:38.660217 ==
2681 09:57:38.663127 Dram Type= 6, Freq= 0, CH_0, rank 0
2682 09:57:38.666235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2683 09:57:38.666322 ==
2684 09:57:38.666387
2685 09:57:38.669643
2686 09:57:38.669726 TX Vref Scan disable
2687 09:57:38.673005 == TX Byte 0 ==
2688 09:57:38.676445 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2689 09:57:38.679635 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2690 09:57:38.683512 == TX Byte 1 ==
2691 09:57:38.686487 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2692 09:57:38.689885 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2693 09:57:38.689971
2694 09:57:38.693062 [DATLAT]
2695 09:57:38.693145 Freq=1200, CH0 RK0
2696 09:57:38.693210
2697 09:57:38.696666 DATLAT Default: 0xd
2698 09:57:38.696757 0, 0xFFFF, sum = 0
2699 09:57:38.700118 1, 0xFFFF, sum = 0
2700 09:57:38.700209 2, 0xFFFF, sum = 0
2701 09:57:38.703401 3, 0xFFFF, sum = 0
2702 09:57:38.703484 4, 0xFFFF, sum = 0
2703 09:57:38.707037 5, 0xFFFF, sum = 0
2704 09:57:38.707122 6, 0xFFFF, sum = 0
2705 09:57:38.709955 7, 0xFFFF, sum = 0
2706 09:57:38.710089 8, 0xFFFF, sum = 0
2707 09:57:38.713297 9, 0xFFFF, sum = 0
2708 09:57:38.716712 10, 0xFFFF, sum = 0
2709 09:57:38.716800 11, 0xFFFF, sum = 0
2710 09:57:38.719922 12, 0x0, sum = 1
2711 09:57:38.720007 13, 0x0, sum = 2
2712 09:57:38.720074 14, 0x0, sum = 3
2713 09:57:38.723274 15, 0x0, sum = 4
2714 09:57:38.723359 best_step = 13
2715 09:57:38.723422
2716 09:57:38.726336 ==
2717 09:57:38.726419 Dram Type= 6, Freq= 0, CH_0, rank 0
2718 09:57:38.733242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2719 09:57:38.733344 ==
2720 09:57:38.733408 RX Vref Scan: 1
2721 09:57:38.733467
2722 09:57:38.736636 Set Vref Range= 32 -> 127
2723 09:57:38.736720
2724 09:57:38.739529 RX Vref 32 -> 127, step: 1
2725 09:57:38.739612
2726 09:57:38.743444 RX Delay -37 -> 252, step: 4
2727 09:57:38.743528
2728 09:57:38.746322 Set Vref, RX VrefLevel [Byte0]: 32
2729 09:57:38.749572 [Byte1]: 32
2730 09:57:38.749656
2731 09:57:38.753238 Set Vref, RX VrefLevel [Byte0]: 33
2732 09:57:38.756180 [Byte1]: 33
2733 09:57:38.756277
2734 09:57:38.759667 Set Vref, RX VrefLevel [Byte0]: 34
2735 09:57:38.762810 [Byte1]: 34
2736 09:57:38.767414
2737 09:57:38.767508 Set Vref, RX VrefLevel [Byte0]: 35
2738 09:57:38.770605 [Byte1]: 35
2739 09:57:38.775589
2740 09:57:38.775679 Set Vref, RX VrefLevel [Byte0]: 36
2741 09:57:38.779289 [Byte1]: 36
2742 09:57:38.783573
2743 09:57:38.783664 Set Vref, RX VrefLevel [Byte0]: 37
2744 09:57:38.786925 [Byte1]: 37
2745 09:57:38.791604
2746 09:57:38.791697 Set Vref, RX VrefLevel [Byte0]: 38
2747 09:57:38.794678 [Byte1]: 38
2748 09:57:38.799571
2749 09:57:38.799660 Set Vref, RX VrefLevel [Byte0]: 39
2750 09:57:38.802692 [Byte1]: 39
2751 09:57:38.807404
2752 09:57:38.807492 Set Vref, RX VrefLevel [Byte0]: 40
2753 09:57:38.810694 [Byte1]: 40
2754 09:57:38.815767
2755 09:57:38.815858 Set Vref, RX VrefLevel [Byte0]: 41
2756 09:57:38.819428 [Byte1]: 41
2757 09:57:38.823689
2758 09:57:38.823779 Set Vref, RX VrefLevel [Byte0]: 42
2759 09:57:38.827071 [Byte1]: 42
2760 09:57:38.831727
2761 09:57:38.831816 Set Vref, RX VrefLevel [Byte0]: 43
2762 09:57:38.834635 [Byte1]: 43
2763 09:57:38.839503
2764 09:57:38.839592 Set Vref, RX VrefLevel [Byte0]: 44
2765 09:57:38.843153 [Byte1]: 44
2766 09:57:38.847652
2767 09:57:38.847740 Set Vref, RX VrefLevel [Byte0]: 45
2768 09:57:38.850645 [Byte1]: 45
2769 09:57:38.855459
2770 09:57:38.855547 Set Vref, RX VrefLevel [Byte0]: 46
2771 09:57:38.858969 [Byte1]: 46
2772 09:57:38.863680
2773 09:57:38.863767 Set Vref, RX VrefLevel [Byte0]: 47
2774 09:57:38.866907 [Byte1]: 47
2775 09:57:38.871639
2776 09:57:38.871728 Set Vref, RX VrefLevel [Byte0]: 48
2777 09:57:38.874808 [Byte1]: 48
2778 09:57:38.879523
2779 09:57:38.879624 Set Vref, RX VrefLevel [Byte0]: 49
2780 09:57:38.882861 [Byte1]: 49
2781 09:57:38.887503
2782 09:57:38.887595 Set Vref, RX VrefLevel [Byte0]: 50
2783 09:57:38.891227 [Byte1]: 50
2784 09:57:38.895242
2785 09:57:38.895330 Set Vref, RX VrefLevel [Byte0]: 51
2786 09:57:38.899017 [Byte1]: 51
2787 09:57:38.903763
2788 09:57:38.903851 Set Vref, RX VrefLevel [Byte0]: 52
2789 09:57:38.906899 [Byte1]: 52
2790 09:57:38.911630
2791 09:57:38.911718 Set Vref, RX VrefLevel [Byte0]: 53
2792 09:57:38.917900 [Byte1]: 53
2793 09:57:38.917995
2794 09:57:38.921082 Set Vref, RX VrefLevel [Byte0]: 54
2795 09:57:38.924753 [Byte1]: 54
2796 09:57:38.924840
2797 09:57:38.928110 Set Vref, RX VrefLevel [Byte0]: 55
2798 09:57:38.931038 [Byte1]: 55
2799 09:57:38.935186
2800 09:57:38.939432 Set Vref, RX VrefLevel [Byte0]: 56
2801 09:57:38.939550 [Byte1]: 56
2802 09:57:38.943266
2803 09:57:38.943352 Set Vref, RX VrefLevel [Byte0]: 57
2804 09:57:38.947300 [Byte1]: 57
2805 09:57:38.951565
2806 09:57:38.951653 Set Vref, RX VrefLevel [Byte0]: 58
2807 09:57:38.954720 [Byte1]: 58
2808 09:57:38.959338
2809 09:57:38.959425 Set Vref, RX VrefLevel [Byte0]: 59
2810 09:57:38.962724 [Byte1]: 59
2811 09:57:38.967523
2812 09:57:38.967638 Set Vref, RX VrefLevel [Byte0]: 60
2813 09:57:38.971223 [Byte1]: 60
2814 09:57:38.975552
2815 09:57:38.975639 Set Vref, RX VrefLevel [Byte0]: 61
2816 09:57:38.978772 [Byte1]: 61
2817 09:57:38.983782
2818 09:57:38.983878 Set Vref, RX VrefLevel [Byte0]: 62
2819 09:57:38.986667 [Byte1]: 62
2820 09:57:38.991451
2821 09:57:38.991570 Set Vref, RX VrefLevel [Byte0]: 63
2822 09:57:38.994706 [Byte1]: 63
2823 09:57:38.999545
2824 09:57:38.999640 Set Vref, RX VrefLevel [Byte0]: 64
2825 09:57:39.002657 [Byte1]: 64
2826 09:57:39.007609
2827 09:57:39.007702 Set Vref, RX VrefLevel [Byte0]: 65
2828 09:57:39.010561 [Byte1]: 65
2829 09:57:39.015600
2830 09:57:39.015722 Set Vref, RX VrefLevel [Byte0]: 66
2831 09:57:39.018694 [Byte1]: 66
2832 09:57:39.023446
2833 09:57:39.023572 Set Vref, RX VrefLevel [Byte0]: 67
2834 09:57:39.027125 [Byte1]: 67
2835 09:57:39.031692
2836 09:57:39.031775 Set Vref, RX VrefLevel [Byte0]: 68
2837 09:57:39.034780 [Byte1]: 68
2838 09:57:39.039269
2839 09:57:39.039387 Set Vref, RX VrefLevel [Byte0]: 69
2840 09:57:39.042571 [Byte1]: 69
2841 09:57:39.047842
2842 09:57:39.047938 Set Vref, RX VrefLevel [Byte0]: 70
2843 09:57:39.050913 [Byte1]: 70
2844 09:57:39.055342
2845 09:57:39.055433 Set Vref, RX VrefLevel [Byte0]: 71
2846 09:57:39.058807 [Byte1]: 71
2847 09:57:39.063384
2848 09:57:39.063481 Set Vref, RX VrefLevel [Byte0]: 72
2849 09:57:39.066820 [Byte1]: 72
2850 09:57:39.071748
2851 09:57:39.071841 Set Vref, RX VrefLevel [Byte0]: 73
2852 09:57:39.074677 [Byte1]: 73
2853 09:57:39.079508
2854 09:57:39.079603 Final RX Vref Byte 0 = 62 to rank0
2855 09:57:39.082740 Final RX Vref Byte 1 = 51 to rank0
2856 09:57:39.086010 Final RX Vref Byte 0 = 62 to rank1
2857 09:57:39.089552 Final RX Vref Byte 1 = 51 to rank1==
2858 09:57:39.092656 Dram Type= 6, Freq= 0, CH_0, rank 0
2859 09:57:39.099343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2860 09:57:39.099467 ==
2861 09:57:39.099572 DQS Delay:
2862 09:57:39.099635 DQS0 = 0, DQS1 = 0
2863 09:57:39.102834 DQM Delay:
2864 09:57:39.102922 DQM0 = 112, DQM1 = 101
2865 09:57:39.105882 DQ Delay:
2866 09:57:39.109502 DQ0 =112, DQ1 =114, DQ2 =110, DQ3 =108
2867 09:57:39.113038 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2868 09:57:39.116068 DQ8 =92, DQ9 =84, DQ10 =104, DQ11 =94
2869 09:57:39.119522 DQ12 =106, DQ13 =106, DQ14 =116, DQ15 =110
2870 09:57:39.119614
2871 09:57:39.119678
2872 09:57:39.126490 [DQSOSCAuto] RK0, (LSB)MR18= 0xfafa, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
2873 09:57:39.129643 CH0 RK0: MR19=303, MR18=FAFA
2874 09:57:39.136197 CH0_RK0: MR19=0x303, MR18=0xFAFA, DQSOSC=412, MR23=63, INC=38, DEC=25
2875 09:57:39.136302
2876 09:57:39.139583 ----->DramcWriteLeveling(PI) begin...
2877 09:57:39.139668 ==
2878 09:57:39.142991 Dram Type= 6, Freq= 0, CH_0, rank 1
2879 09:57:39.145965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2880 09:57:39.146050 ==
2881 09:57:39.149891 Write leveling (Byte 0): 32 => 32
2882 09:57:39.152871 Write leveling (Byte 1): 31 => 31
2883 09:57:39.155997 DramcWriteLeveling(PI) end<-----
2884 09:57:39.156083
2885 09:57:39.156147 ==
2886 09:57:39.159503 Dram Type= 6, Freq= 0, CH_0, rank 1
2887 09:57:39.166285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2888 09:57:39.166384 ==
2889 09:57:39.166451 [Gating] SW mode calibration
2890 09:57:39.176011 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2891 09:57:39.179569 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2892 09:57:39.182737 0 15 0 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
2893 09:57:39.189568 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2894 09:57:39.192896 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2895 09:57:39.196146 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2896 09:57:39.203007 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2897 09:57:39.206189 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2898 09:57:39.209454 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2899 09:57:39.215992 0 15 28 | B1->B0 | 3434 2727 | 0 0 | (0 0) (1 0)
2900 09:57:39.219316 1 0 0 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
2901 09:57:39.222682 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2902 09:57:39.229203 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2903 09:57:39.232400 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 09:57:39.235513 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 09:57:39.242389 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 09:57:39.246161 1 0 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2907 09:57:39.249507 1 0 28 | B1->B0 | 2323 3f3e | 0 1 | (0 0) (0 0)
2908 09:57:39.255736 1 1 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
2909 09:57:39.259013 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2910 09:57:39.262544 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2911 09:57:39.269506 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 09:57:39.273039 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 09:57:39.276016 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 09:57:39.282533 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 09:57:39.285649 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2916 09:57:39.289041 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2917 09:57:39.292480 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 09:57:39.299476 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 09:57:39.302454 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 09:57:39.305838 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 09:57:39.312338 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 09:57:39.315642 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 09:57:39.319020 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 09:57:39.325569 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 09:57:39.329411 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 09:57:39.332388 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 09:57:39.339450 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 09:57:39.342835 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 09:57:39.345913 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 09:57:39.352347 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2931 09:57:39.356067 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2932 09:57:39.359254 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2933 09:57:39.362934 Total UI for P1: 0, mck2ui 16
2934 09:57:39.365799 best dqsien dly found for B0: ( 1, 3, 26)
2935 09:57:39.369404 Total UI for P1: 0, mck2ui 16
2936 09:57:39.372553 best dqsien dly found for B1: ( 1, 3, 28)
2937 09:57:39.376080 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2938 09:57:39.379415 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2939 09:57:39.379523
2940 09:57:39.382546 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2941 09:57:39.389618 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2942 09:57:39.389773 [Gating] SW calibration Done
2943 09:57:39.389842 ==
2944 09:57:39.392571 Dram Type= 6, Freq= 0, CH_0, rank 1
2945 09:57:39.399442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2946 09:57:39.399591 ==
2947 09:57:39.399660 RX Vref Scan: 0
2948 09:57:39.399719
2949 09:57:39.402675 RX Vref 0 -> 0, step: 1
2950 09:57:39.402776
2951 09:57:39.405803 RX Delay -40 -> 252, step: 8
2952 09:57:39.409189 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2953 09:57:39.412770 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
2954 09:57:39.416110 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2955 09:57:39.419453 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2956 09:57:39.425719 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2957 09:57:39.429239 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2958 09:57:39.432724 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2959 09:57:39.435807 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2960 09:57:39.439448 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2961 09:57:39.445588 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2962 09:57:39.449394 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2963 09:57:39.452253 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2964 09:57:39.455947 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2965 09:57:39.459028 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2966 09:57:39.465715 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2967 09:57:39.469100 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2968 09:57:39.469257 ==
2969 09:57:39.472311 Dram Type= 6, Freq= 0, CH_0, rank 1
2970 09:57:39.476138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2971 09:57:39.476307 ==
2972 09:57:39.479338 DQS Delay:
2973 09:57:39.479471 DQS0 = 0, DQS1 = 0
2974 09:57:39.479585 DQM Delay:
2975 09:57:44.287373 DQM0 = 112, DQM1 = 101
2976 09:57:44.287572 DQ Delay:
2977 09:57:44.287671 DQ0 =111, DQ1 =107, DQ2 =111, DQ3 =107
2978 09:57:44.287765 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =123
2979 09:57:44.287854 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2980 09:57:44.287955 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =107
2981 09:57:44.288045
2982 09:57:44.288130
2983 09:57:44.288254 ==
2984 09:57:44.288339 Dram Type= 6, Freq= 0, CH_0, rank 1
2985 09:57:44.288424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2986 09:57:44.288507 ==
2987 09:57:44.288597
2988 09:57:44.288689
2989 09:57:44.288747 TX Vref Scan disable
2990 09:57:44.288802 == TX Byte 0 ==
2991 09:57:44.288856 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2992 09:57:44.288910 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2993 09:57:44.288964 == TX Byte 1 ==
2994 09:57:44.289017 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2995 09:57:44.289070 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2996 09:57:44.289123 ==
2997 09:57:44.289177 Dram Type= 6, Freq= 0, CH_0, rank 1
2998 09:57:44.289230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2999 09:57:44.289284 ==
3000 09:57:44.289377 TX Vref=22, minBit 1, minWin=26, winSum=428
3001 09:57:44.289431 TX Vref=24, minBit 1, minWin=26, winSum=436
3002 09:57:44.289485 TX Vref=26, minBit 1, minWin=26, winSum=437
3003 09:57:44.289538 TX Vref=28, minBit 1, minWin=26, winSum=440
3004 09:57:44.289591 TX Vref=30, minBit 1, minWin=27, winSum=443
3005 09:57:44.289644 TX Vref=32, minBit 2, minWin=27, winSum=442
3006 09:57:44.289697 [TxChooseVref] Worse bit 1, Min win 27, Win sum 443, Final Vref 30
3007 09:57:44.289750
3008 09:57:44.289802 Final TX Range 1 Vref 30
3009 09:57:44.289855
3010 09:57:44.289907 ==
3011 09:57:44.289959 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 09:57:44.290012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 09:57:44.290065 ==
3014 09:57:44.290118
3015 09:57:44.290170
3016 09:57:44.290222 TX Vref Scan disable
3017 09:57:44.290275 == TX Byte 0 ==
3018 09:57:44.290328 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3019 09:57:44.290381 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3020 09:57:44.290434 == TX Byte 1 ==
3021 09:57:44.290486 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3022 09:57:44.290539 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3023 09:57:44.290591
3024 09:57:44.290643 [DATLAT]
3025 09:57:44.290695 Freq=1200, CH0 RK1
3026 09:57:44.290748
3027 09:57:44.290800 DATLAT Default: 0xd
3028 09:57:44.290852 0, 0xFFFF, sum = 0
3029 09:57:44.290906 1, 0xFFFF, sum = 0
3030 09:57:44.290959 2, 0xFFFF, sum = 0
3031 09:57:44.291012 3, 0xFFFF, sum = 0
3032 09:57:44.291065 4, 0xFFFF, sum = 0
3033 09:57:44.291118 5, 0xFFFF, sum = 0
3034 09:57:44.291172 6, 0xFFFF, sum = 0
3035 09:57:44.291225 7, 0xFFFF, sum = 0
3036 09:57:44.291278 8, 0xFFFF, sum = 0
3037 09:57:44.291332 9, 0xFFFF, sum = 0
3038 09:57:44.291385 10, 0xFFFF, sum = 0
3039 09:57:44.291439 11, 0xFFFF, sum = 0
3040 09:57:44.291492 12, 0x0, sum = 1
3041 09:57:44.291545 13, 0x0, sum = 2
3042 09:57:44.291599 14, 0x0, sum = 3
3043 09:57:44.291651 15, 0x0, sum = 4
3044 09:57:44.291704 best_step = 13
3045 09:57:44.291757
3046 09:57:44.291809 ==
3047 09:57:44.291862 Dram Type= 6, Freq= 0, CH_0, rank 1
3048 09:57:44.291915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3049 09:57:44.291967 ==
3050 09:57:44.292039 RX Vref Scan: 0
3051 09:57:44.292122
3052 09:57:44.292229 RX Vref 0 -> 0, step: 1
3053 09:57:44.292301
3054 09:57:44.292354 RX Delay -37 -> 252, step: 4
3055 09:57:44.292412 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3056 09:57:44.292467 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3057 09:57:44.292520 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3058 09:57:44.292576 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3059 09:57:44.292657 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3060 09:57:44.292712 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3061 09:57:44.292770 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3062 09:57:44.292868 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3063 09:57:44.292946 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3064 09:57:44.293001 iDelay=195, Bit 9, Center 82 (11 ~ 154) 144
3065 09:57:44.293053 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3066 09:57:44.293109 iDelay=195, Bit 11, Center 92 (23 ~ 162) 140
3067 09:57:44.293165 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3068 09:57:44.293219 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3069 09:57:44.293321 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3070 09:57:44.293376 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3071 09:57:44.293429 ==
3072 09:57:44.293482 Dram Type= 6, Freq= 0, CH_0, rank 1
3073 09:57:44.293535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3074 09:57:44.293588 ==
3075 09:57:44.293640 DQS Delay:
3076 09:57:44.293693 DQS0 = 0, DQS1 = 0
3077 09:57:44.293745 DQM Delay:
3078 09:57:44.293797 DQM0 = 111, DQM1 = 100
3079 09:57:44.293850 DQ Delay:
3080 09:57:44.293902 DQ0 =108, DQ1 =112, DQ2 =110, DQ3 =108
3081 09:57:44.293955 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3082 09:57:44.294007 DQ8 =90, DQ9 =82, DQ10 =104, DQ11 =92
3083 09:57:44.294061 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =108
3084 09:57:44.294113
3085 09:57:44.294165
3086 09:57:44.294217 [DQSOSCAuto] RK1, (LSB)MR18= 0x14fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 402 ps
3087 09:57:44.294271 CH0 RK1: MR19=403, MR18=14FC
3088 09:57:44.294324 CH0_RK1: MR19=0x403, MR18=0x14FC, DQSOSC=402, MR23=63, INC=40, DEC=27
3089 09:57:44.294377 [RxdqsGatingPostProcess] freq 1200
3090 09:57:44.294430 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3091 09:57:44.294483 best DQS0 dly(2T, 0.5T) = (0, 11)
3092 09:57:44.294535 best DQS1 dly(2T, 0.5T) = (0, 12)
3093 09:57:44.294588 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3094 09:57:44.294640 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3095 09:57:44.294692 best DQS0 dly(2T, 0.5T) = (0, 11)
3096 09:57:44.294745 best DQS1 dly(2T, 0.5T) = (0, 11)
3097 09:57:44.294797 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3098 09:57:44.294850 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3099 09:57:44.294902 Pre-setting of DQS Precalculation
3100 09:57:44.294955 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3101 09:57:44.295008 ==
3102 09:57:44.295061 Dram Type= 6, Freq= 0, CH_1, rank 0
3103 09:57:44.295113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3104 09:57:44.295166 ==
3105 09:57:44.295218 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3106 09:57:44.295271 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3107 09:57:44.295324 [CA 0] Center 37 (7~67) winsize 61
3108 09:57:44.295377 [CA 1] Center 37 (7~68) winsize 62
3109 09:57:44.295429 [CA 2] Center 34 (4~64) winsize 61
3110 09:57:44.295482 [CA 3] Center 33 (3~64) winsize 62
3111 09:57:44.295535 [CA 4] Center 34 (4~64) winsize 61
3112 09:57:44.295822 [CA 5] Center 33 (3~63) winsize 61
3113 09:57:44.295886
3114 09:57:44.295941 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3115 09:57:44.295996
3116 09:57:44.296050 [CATrainingPosCal] consider 1 rank data
3117 09:57:44.296104 u2DelayCellTimex100 = 270/100 ps
3118 09:57:44.296158 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3119 09:57:44.296224 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3120 09:57:44.296280 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3121 09:57:44.296348 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3122 09:57:44.296401 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3123 09:57:44.296454 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3124 09:57:44.296506
3125 09:57:44.296559 CA PerBit enable=1, Macro0, CA PI delay=33
3126 09:57:44.296612
3127 09:57:44.296664 [CBTSetCACLKResult] CA Dly = 33
3128 09:57:44.296716 CS Dly: 5 (0~36)
3129 09:57:44.296769 ==
3130 09:57:44.296822 Dram Type= 6, Freq= 0, CH_1, rank 1
3131 09:57:44.296875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3132 09:57:44.296945 ==
3133 09:57:44.296998 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3134 09:57:44.297051 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3135 09:57:44.297104 [CA 0] Center 37 (7~67) winsize 61
3136 09:57:44.297157 [CA 1] Center 37 (7~68) winsize 62
3137 09:57:44.297210 [CA 2] Center 34 (4~65) winsize 62
3138 09:57:44.297263 [CA 3] Center 33 (3~64) winsize 62
3139 09:57:44.297315 [CA 4] Center 34 (4~65) winsize 62
3140 09:57:44.297367 [CA 5] Center 33 (3~63) winsize 61
3141 09:57:44.297419
3142 09:57:44.297472 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3143 09:57:44.297529
3144 09:57:44.297581 [CATrainingPosCal] consider 2 rank data
3145 09:57:44.297634 u2DelayCellTimex100 = 270/100 ps
3146 09:57:44.297687 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3147 09:57:44.297739 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3148 09:57:44.297792 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3149 09:57:44.297845 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3150 09:57:44.297897 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3151 09:57:44.297949 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3152 09:57:44.298001
3153 09:57:44.298054 CA PerBit enable=1, Macro0, CA PI delay=33
3154 09:57:44.298106
3155 09:57:44.298158 [CBTSetCACLKResult] CA Dly = 33
3156 09:57:44.298211 CS Dly: 7 (0~40)
3157 09:57:44.298263
3158 09:57:44.298315 ----->DramcWriteLeveling(PI) begin...
3159 09:57:44.298369 ==
3160 09:57:44.298422 Dram Type= 6, Freq= 0, CH_1, rank 0
3161 09:57:44.298475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3162 09:57:44.298528 ==
3163 09:57:44.298580 Write leveling (Byte 0): 26 => 26
3164 09:57:44.298634 Write leveling (Byte 1): 28 => 28
3165 09:57:44.298686 DramcWriteLeveling(PI) end<-----
3166 09:57:44.298739
3167 09:57:44.298790 ==
3168 09:57:44.298843 Dram Type= 6, Freq= 0, CH_1, rank 0
3169 09:57:44.298895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3170 09:57:44.298948 ==
3171 09:57:44.299000 [Gating] SW mode calibration
3172 09:57:44.299052 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3173 09:57:44.299105 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3174 09:57:44.299157 0 15 0 | B1->B0 | 2f2f 2929 | 1 0 | (1 1) (0 0)
3175 09:57:44.299209 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3176 09:57:44.299293 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3177 09:57:44.299426 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3178 09:57:44.299532 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 09:57:44.299590 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 09:57:44.299659 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 09:57:44.299712 0 15 28 | B1->B0 | 2d2d 3232 | 1 0 | (1 1) (0 0)
3182 09:57:44.299765 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3183 09:57:44.299818 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3184 09:57:44.299871 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 09:57:44.299924 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 09:57:44.299976 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 09:57:44.300029 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 09:57:44.300082 1 0 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3189 09:57:44.300134 1 0 28 | B1->B0 | 4141 3e3e | 0 0 | (0 0) (1 1)
3190 09:57:44.300187 1 1 0 | B1->B0 | 4545 4444 | 0 0 | (0 0) (0 0)
3191 09:57:44.300281 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3192 09:57:44.300335 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 09:57:44.300388 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 09:57:44.300440 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 09:57:44.300492 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 09:57:44.300545 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 09:57:44.300597 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3198 09:57:44.300650 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 09:57:44.300702 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 09:57:44.300754 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 09:57:44.300807 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 09:57:44.300860 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 09:57:44.300912 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 09:57:44.300965 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 09:57:44.301018 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 09:57:44.301070 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 09:57:44.301122 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 09:57:44.301175 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 09:57:44.301228 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 09:57:44.301281 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 09:57:44.301332 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 09:57:44.301384 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 09:57:44.301437 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3214 09:57:44.301489 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 09:57:44.301542 Total UI for P1: 0, mck2ui 16
3216 09:57:44.301595 best dqsien dly found for B0: ( 1, 3, 28)
3217 09:57:44.301874 Total UI for P1: 0, mck2ui 16
3218 09:57:44.301938 best dqsien dly found for B1: ( 1, 3, 28)
3219 09:57:44.301993 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3220 09:57:44.302048 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3221 09:57:44.302101
3222 09:57:44.302155 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3223 09:57:44.302209 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3224 09:57:44.302262 [Gating] SW calibration Done
3225 09:57:44.302316 ==
3226 09:57:44.302383 Dram Type= 6, Freq= 0, CH_1, rank 0
3227 09:57:44.302436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3228 09:57:44.302490 ==
3229 09:57:44.302542 RX Vref Scan: 0
3230 09:57:44.302595
3231 09:57:44.302647 RX Vref 0 -> 0, step: 1
3232 09:57:44.302699
3233 09:57:44.302751 RX Delay -40 -> 252, step: 8
3234 09:57:44.302804 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3235 09:57:44.302856 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3236 09:57:44.302909 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3237 09:57:44.302961 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3238 09:57:44.303014 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3239 09:57:44.303067 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3240 09:57:44.303119 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3241 09:57:44.303171 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3242 09:57:44.303223 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3243 09:57:44.303276 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3244 09:57:44.303328 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3245 09:57:44.303380 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3246 09:57:44.303433 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3247 09:57:44.303485 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3248 09:57:44.303538 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3249 09:57:44.303590 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3250 09:57:44.303642 ==
3251 09:57:44.303694 Dram Type= 6, Freq= 0, CH_1, rank 0
3252 09:57:44.303747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3253 09:57:44.303800 ==
3254 09:57:44.303852 DQS Delay:
3255 09:57:44.303919 DQS0 = 0, DQS1 = 0
3256 09:57:44.304019 DQM Delay:
3257 09:57:44.304100 DQM0 = 113, DQM1 = 106
3258 09:57:44.304181 DQ Delay:
3259 09:57:44.304284 DQ0 =119, DQ1 =107, DQ2 =103, DQ3 =107
3260 09:57:44.304338 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3261 09:57:44.304392 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
3262 09:57:44.304445 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3263 09:57:44.304498
3264 09:57:44.304551
3265 09:57:44.304603 ==
3266 09:57:44.304656 Dram Type= 6, Freq= 0, CH_1, rank 0
3267 09:57:44.304709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3268 09:57:44.304763 ==
3269 09:57:44.304816
3270 09:57:44.304868
3271 09:57:44.304921 TX Vref Scan disable
3272 09:57:44.304974 == TX Byte 0 ==
3273 09:57:44.305027 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3274 09:57:44.305081 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3275 09:57:44.305133 == TX Byte 1 ==
3276 09:57:44.305186 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3277 09:57:44.305239 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3278 09:57:44.305292 ==
3279 09:57:44.305345 Dram Type= 6, Freq= 0, CH_1, rank 0
3280 09:57:44.305398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3281 09:57:44.305451 ==
3282 09:57:44.305504 TX Vref=22, minBit 11, minWin=24, winSum=405
3283 09:57:44.305558 TX Vref=24, minBit 11, minWin=24, winSum=415
3284 09:57:44.305611 TX Vref=26, minBit 10, minWin=24, winSum=419
3285 09:57:44.305665 TX Vref=28, minBit 9, minWin=25, winSum=422
3286 09:57:44.305718 TX Vref=30, minBit 9, minWin=25, winSum=424
3287 09:57:44.305771 TX Vref=32, minBit 9, minWin=25, winSum=424
3288 09:57:44.305824 [TxChooseVref] Worse bit 9, Min win 25, Win sum 424, Final Vref 30
3289 09:57:44.305877
3290 09:57:44.305930 Final TX Range 1 Vref 30
3291 09:57:44.305983
3292 09:57:44.306051 ==
3293 09:57:44.306132 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 09:57:44.306221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 09:57:44.306302 ==
3296 09:57:44.306358
3297 09:57:44.306411
3298 09:57:44.306464 TX Vref Scan disable
3299 09:57:44.306518 == TX Byte 0 ==
3300 09:57:44.306571 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3301 09:57:44.306624 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3302 09:57:44.306678 == TX Byte 1 ==
3303 09:57:44.306731 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3304 09:57:44.306784 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3305 09:57:44.306837
3306 09:57:44.306890 [DATLAT]
3307 09:57:44.306942 Freq=1200, CH1 RK0
3308 09:57:44.306996
3309 09:57:44.307049 DATLAT Default: 0xd
3310 09:57:44.307102 0, 0xFFFF, sum = 0
3311 09:57:44.307156 1, 0xFFFF, sum = 0
3312 09:57:44.307210 2, 0xFFFF, sum = 0
3313 09:57:44.307264 3, 0xFFFF, sum = 0
3314 09:57:44.307317 4, 0xFFFF, sum = 0
3315 09:57:44.307370 5, 0xFFFF, sum = 0
3316 09:57:44.307424 6, 0xFFFF, sum = 0
3317 09:57:44.307477 7, 0xFFFF, sum = 0
3318 09:57:44.307531 8, 0xFFFF, sum = 0
3319 09:57:44.307584 9, 0xFFFF, sum = 0
3320 09:57:44.307638 10, 0xFFFF, sum = 0
3321 09:57:44.307692 11, 0xFFFF, sum = 0
3322 09:57:44.307745 12, 0x0, sum = 1
3323 09:57:44.307798 13, 0x0, sum = 2
3324 09:57:44.307852 14, 0x0, sum = 3
3325 09:57:44.307905 15, 0x0, sum = 4
3326 09:57:44.307958 best_step = 13
3327 09:57:44.308011
3328 09:57:44.308063 ==
3329 09:57:44.308116 Dram Type= 6, Freq= 0, CH_1, rank 0
3330 09:57:44.308168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3331 09:57:44.308259 ==
3332 09:57:44.308328 RX Vref Scan: 1
3333 09:57:44.308381
3334 09:57:44.308433 Set Vref Range= 32 -> 127
3335 09:57:44.308485
3336 09:57:44.308538 RX Vref 32 -> 127, step: 1
3337 09:57:44.308590
3338 09:57:44.308642 RX Delay -21 -> 252, step: 4
3339 09:57:44.308693
3340 09:57:44.308745 Set Vref, RX VrefLevel [Byte0]: 32
3341 09:57:44.308798 [Byte1]: 32
3342 09:57:44.308851
3343 09:57:44.308902 Set Vref, RX VrefLevel [Byte0]: 33
3344 09:57:44.308954 [Byte1]: 33
3345 09:57:44.309007
3346 09:57:44.309058 Set Vref, RX VrefLevel [Byte0]: 34
3347 09:57:44.309110 [Byte1]: 34
3348 09:57:44.309163
3349 09:57:44.309215 Set Vref, RX VrefLevel [Byte0]: 35
3350 09:57:44.309268 [Byte1]: 35
3351 09:57:44.309320
3352 09:57:44.309372 Set Vref, RX VrefLevel [Byte0]: 36
3353 09:57:44.309424 [Byte1]: 36
3354 09:57:44.309477
3355 09:57:44.309553 Set Vref, RX VrefLevel [Byte0]: 37
3356 09:57:44.309651 [Byte1]: 37
3357 09:57:44.309741
3358 09:57:44.309796 Set Vref, RX VrefLevel [Byte0]: 38
3359 09:57:44.309849 [Byte1]: 38
3360 09:57:44.309903
3361 09:57:44.309955 Set Vref, RX VrefLevel [Byte0]: 39
3362 09:57:44.310008 [Byte1]: 39
3363 09:57:44.310061
3364 09:57:44.310113 Set Vref, RX VrefLevel [Byte0]: 40
3365 09:57:44.310165 [Byte1]: 40
3366 09:57:44.310217
3367 09:57:44.310269 Set Vref, RX VrefLevel [Byte0]: 41
3368 09:57:44.310322 [Byte1]: 41
3369 09:57:44.310375
3370 09:57:44.310426 Set Vref, RX VrefLevel [Byte0]: 42
3371 09:57:44.310687 [Byte1]: 42
3372 09:57:44.310800
3373 09:57:44.310871 Set Vref, RX VrefLevel [Byte0]: 43
3374 09:57:44.310924 [Byte1]: 43
3375 09:57:44.310976
3376 09:57:44.311028 Set Vref, RX VrefLevel [Byte0]: 44
3377 09:57:44.311095 [Byte1]: 44
3378 09:57:44.311148
3379 09:57:44.311201 Set Vref, RX VrefLevel [Byte0]: 45
3380 09:57:44.311269 [Byte1]: 45
3381 09:57:44.311321
3382 09:57:44.311372 Set Vref, RX VrefLevel [Byte0]: 46
3383 09:57:44.311425 [Byte1]: 46
3384 09:57:44.311477
3385 09:57:44.311528 Set Vref, RX VrefLevel [Byte0]: 47
3386 09:57:44.311581 [Byte1]: 47
3387 09:57:44.311633
3388 09:57:44.311734 Set Vref, RX VrefLevel [Byte0]: 48
3389 09:57:44.311788 [Byte1]: 48
3390 09:57:44.311841
3391 09:57:44.311893 Set Vref, RX VrefLevel [Byte0]: 49
3392 09:57:44.311945 [Byte1]: 49
3393 09:57:44.311997
3394 09:57:44.312049 Set Vref, RX VrefLevel [Byte0]: 50
3395 09:57:44.312101 [Byte1]: 50
3396 09:57:44.312153
3397 09:57:44.312233 Set Vref, RX VrefLevel [Byte0]: 51
3398 09:57:44.312302 [Byte1]: 51
3399 09:57:44.312355
3400 09:57:44.312407 Set Vref, RX VrefLevel [Byte0]: 52
3401 09:57:44.312460 [Byte1]: 52
3402 09:57:44.312512
3403 09:57:44.312563 Set Vref, RX VrefLevel [Byte0]: 53
3404 09:57:44.312615 [Byte1]: 53
3405 09:57:44.312667
3406 09:57:44.312719 Set Vref, RX VrefLevel [Byte0]: 54
3407 09:57:44.312771 [Byte1]: 54
3408 09:57:44.312823
3409 09:57:44.312875 Set Vref, RX VrefLevel [Byte0]: 55
3410 09:57:44.312927 [Byte1]: 55
3411 09:57:44.312979
3412 09:57:44.313031 Set Vref, RX VrefLevel [Byte0]: 56
3413 09:57:44.313083 [Byte1]: 56
3414 09:57:44.313136
3415 09:57:44.313187 Set Vref, RX VrefLevel [Byte0]: 57
3416 09:57:44.313240 [Byte1]: 57
3417 09:57:44.313293
3418 09:57:44.313345 Set Vref, RX VrefLevel [Byte0]: 58
3419 09:57:44.313398 [Byte1]: 58
3420 09:57:44.313450
3421 09:57:44.313501 Set Vref, RX VrefLevel [Byte0]: 59
3422 09:57:44.313554 [Byte1]: 59
3423 09:57:44.313605
3424 09:57:44.313657 Set Vref, RX VrefLevel [Byte0]: 60
3425 09:57:44.313709 [Byte1]: 60
3426 09:57:44.313761
3427 09:57:44.313814 Set Vref, RX VrefLevel [Byte0]: 61
3428 09:57:44.313866 [Byte1]: 61
3429 09:57:44.313918
3430 09:57:44.313970 Set Vref, RX VrefLevel [Byte0]: 62
3431 09:57:44.314022 [Byte1]: 62
3432 09:57:44.314074
3433 09:57:44.314125 Set Vref, RX VrefLevel [Byte0]: 63
3434 09:57:44.314177 [Byte1]: 63
3435 09:57:44.314229
3436 09:57:44.314281 Set Vref, RX VrefLevel [Byte0]: 64
3437 09:57:44.314334 [Byte1]: 64
3438 09:57:44.314386
3439 09:57:44.314437 Set Vref, RX VrefLevel [Byte0]: 65
3440 09:57:44.314489 [Byte1]: 65
3441 09:57:44.314541
3442 09:57:44.314593 Set Vref, RX VrefLevel [Byte0]: 66
3443 09:57:44.314644 [Byte1]: 66
3444 09:57:44.314697
3445 09:57:44.314748 Set Vref, RX VrefLevel [Byte0]: 67
3446 09:57:44.314800 [Byte1]: 67
3447 09:57:44.314853
3448 09:57:44.314905 Set Vref, RX VrefLevel [Byte0]: 68
3449 09:57:44.314957 [Byte1]: 68
3450 09:57:44.315009
3451 09:57:44.315061 Set Vref, RX VrefLevel [Byte0]: 69
3452 09:57:44.315113 [Byte1]: 69
3453 09:57:44.315165
3454 09:57:44.315216 Final RX Vref Byte 0 = 55 to rank0
3455 09:57:44.315269 Final RX Vref Byte 1 = 50 to rank0
3456 09:57:44.315322 Final RX Vref Byte 0 = 55 to rank1
3457 09:57:44.315374 Final RX Vref Byte 1 = 50 to rank1==
3458 09:57:44.315428 Dram Type= 6, Freq= 0, CH_1, rank 0
3459 09:57:44.315481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3460 09:57:44.315534 ==
3461 09:57:44.315586 DQS Delay:
3462 09:57:44.315678 DQS0 = 0, DQS1 = 0
3463 09:57:44.315776 DQM Delay:
3464 09:57:44.315840 DQM0 = 114, DQM1 = 106
3465 09:57:44.315895 DQ Delay:
3466 09:57:44.315948 DQ0 =116, DQ1 =110, DQ2 =104, DQ3 =112
3467 09:57:44.316001 DQ4 =112, DQ5 =120, DQ6 =126, DQ7 =112
3468 09:57:44.316053 DQ8 =92, DQ9 =100, DQ10 =104, DQ11 =100
3469 09:57:44.316106 DQ12 =116, DQ13 =110, DQ14 =116, DQ15 =112
3470 09:57:44.316159
3471 09:57:44.316238
3472 09:57:44.316305 [DQSOSCAuto] RK0, (LSB)MR18= 0xecf3, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 418 ps
3473 09:57:44.316360 CH1 RK0: MR19=303, MR18=ECF3
3474 09:57:44.316412 CH1_RK0: MR19=0x303, MR18=0xECF3, DQSOSC=415, MR23=63, INC=38, DEC=25
3475 09:57:44.316466
3476 09:57:44.316518 ----->DramcWriteLeveling(PI) begin...
3477 09:57:44.316572 ==
3478 09:57:44.316625 Dram Type= 6, Freq= 0, CH_1, rank 1
3479 09:57:44.316678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3480 09:57:44.316730 ==
3481 09:57:44.316783 Write leveling (Byte 0): 23 => 23
3482 09:57:44.316835 Write leveling (Byte 1): 28 => 28
3483 09:57:44.316888 DramcWriteLeveling(PI) end<-----
3484 09:57:44.316940
3485 09:57:44.316992 ==
3486 09:57:44.317044 Dram Type= 6, Freq= 0, CH_1, rank 1
3487 09:57:44.317097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3488 09:57:44.317150 ==
3489 09:57:44.317203 [Gating] SW mode calibration
3490 09:57:44.317255 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3491 09:57:44.317309 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3492 09:57:44.317362 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3493 09:57:44.317415 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3494 09:57:44.317467 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3495 09:57:44.317519 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3496 09:57:44.317572 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3497 09:57:44.317625 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3498 09:57:44.317695 0 15 24 | B1->B0 | 3333 2424 | 0 0 | (0 1) (1 0)
3499 09:57:44.317749 0 15 28 | B1->B0 | 2929 2323 | 0 0 | (0 1) (0 0)
3500 09:57:44.317802 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3501 09:57:44.317901 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3502 09:57:44.317973 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3503 09:57:44.318027 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3504 09:57:44.318081 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3505 09:57:44.318149 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3506 09:57:44.318232 1 0 24 | B1->B0 | 3131 4545 | 0 0 | (0 0) (0 0)
3507 09:57:44.318298 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3508 09:57:44.318621 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 09:57:44.318717 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 09:57:44.318772 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3511 09:57:44.318826 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 09:57:44.318880 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3513 09:57:44.318933 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3514 09:57:44.318987 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3515 09:57:44.319040 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3516 09:57:44.319094 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 09:57:44.319147 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 09:57:44.319202 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 09:57:44.319255 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 09:57:44.319309 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 09:57:44.319363 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 09:57:44.319417 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 09:57:44.319470 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 09:57:44.319537 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 09:57:44.319589 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 09:57:44.319641 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 09:57:44.319707 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 09:57:44.319760 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 09:57:44.319826 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3530 09:57:44.319880 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3531 09:57:44.319932 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3532 09:57:44.319985 Total UI for P1: 0, mck2ui 16
3533 09:57:44.320038 best dqsien dly found for B0: ( 1, 3, 22)
3534 09:57:44.320106 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 09:57:44.320159 Total UI for P1: 0, mck2ui 16
3536 09:57:44.320230 best dqsien dly found for B1: ( 1, 3, 24)
3537 09:57:44.320299 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3538 09:57:44.320352 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3539 09:57:44.320404
3540 09:57:44.320456 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3541 09:57:44.320509 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3542 09:57:44.320561 [Gating] SW calibration Done
3543 09:57:44.320614 ==
3544 09:57:44.320666 Dram Type= 6, Freq= 0, CH_1, rank 1
3545 09:57:44.320718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3546 09:57:44.320771 ==
3547 09:57:44.320823 RX Vref Scan: 0
3548 09:57:44.320876
3549 09:57:44.320928 RX Vref 0 -> 0, step: 1
3550 09:57:44.320980
3551 09:57:44.321033 RX Delay -40 -> 252, step: 8
3552 09:57:44.321085 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3553 09:57:44.321138 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3554 09:57:44.321190 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3555 09:57:44.321242 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3556 09:57:44.321295 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3557 09:57:44.321347 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3558 09:57:44.321398 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3559 09:57:44.321451 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3560 09:57:44.321503 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3561 09:57:44.321555 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3562 09:57:44.321607 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3563 09:57:44.321660 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3564 09:57:44.321712 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3565 09:57:44.321764 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3566 09:57:44.321860 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3567 09:57:44.321916 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3568 09:57:44.321970 ==
3569 09:57:44.322023 Dram Type= 6, Freq= 0, CH_1, rank 1
3570 09:57:44.322075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3571 09:57:44.322128 ==
3572 09:57:44.322180 DQS Delay:
3573 09:57:44.322232 DQS0 = 0, DQS1 = 0
3574 09:57:44.322283 DQM Delay:
3575 09:57:44.322335 DQM0 = 110, DQM1 = 106
3576 09:57:44.322387 DQ Delay:
3577 09:57:44.322439 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3578 09:57:44.322491 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3579 09:57:44.322544 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3580 09:57:44.322596 DQ12 =111, DQ13 =115, DQ14 =111, DQ15 =111
3581 09:57:44.322648
3582 09:57:44.322700
3583 09:57:44.322751 ==
3584 09:57:44.322803 Dram Type= 6, Freq= 0, CH_1, rank 1
3585 09:57:44.322855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3586 09:57:44.322908 ==
3587 09:57:44.322959
3588 09:57:44.323010
3589 09:57:44.323062 TX Vref Scan disable
3590 09:57:44.323115 == TX Byte 0 ==
3591 09:57:44.323167 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3592 09:57:44.323220 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3593 09:57:44.323272 == TX Byte 1 ==
3594 09:57:44.323325 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3595 09:57:44.323377 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3596 09:57:44.323429 ==
3597 09:57:44.323482 Dram Type= 6, Freq= 0, CH_1, rank 1
3598 09:57:44.323534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3599 09:57:44.323587 ==
3600 09:57:44.323640 TX Vref=22, minBit 0, minWin=25, winSum=422
3601 09:57:44.323693 TX Vref=24, minBit 9, minWin=25, winSum=427
3602 09:57:44.323746 TX Vref=26, minBit 1, minWin=26, winSum=431
3603 09:57:44.323798 TX Vref=28, minBit 1, minWin=26, winSum=433
3604 09:57:44.323851 TX Vref=30, minBit 1, minWin=26, winSum=433
3605 09:57:44.323948 TX Vref=32, minBit 1, minWin=26, winSum=430
3606 09:57:44.324057 [TxChooseVref] Worse bit 1, Min win 26, Win sum 433, Final Vref 28
3607 09:57:44.324162
3608 09:57:44.324258 Final TX Range 1 Vref 28
3609 09:57:44.324314
3610 09:57:44.324368 ==
3611 09:57:44.324420 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 09:57:44.324474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 09:57:44.324528 ==
3614 09:57:44.324580
3615 09:57:44.324631
3616 09:57:44.324683 TX Vref Scan disable
3617 09:57:44.324736 == TX Byte 0 ==
3618 09:57:44.324788 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3619 09:57:44.324841 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3620 09:57:44.324893 == TX Byte 1 ==
3621 09:57:44.324945 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3622 09:57:44.324998 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3623 09:57:44.325050
3624 09:57:44.325102 [DATLAT]
3625 09:57:44.325154 Freq=1200, CH1 RK1
3626 09:57:44.325206
3627 09:57:44.325259 DATLAT Default: 0xd
3628 09:57:44.325527 0, 0xFFFF, sum = 0
3629 09:57:44.325645 1, 0xFFFF, sum = 0
3630 09:57:44.325701 2, 0xFFFF, sum = 0
3631 09:57:44.325756 3, 0xFFFF, sum = 0
3632 09:57:44.325812 4, 0xFFFF, sum = 0
3633 09:57:44.325867 5, 0xFFFF, sum = 0
3634 09:57:44.325921 6, 0xFFFF, sum = 0
3635 09:57:44.325975 7, 0xFFFF, sum = 0
3636 09:57:44.326030 8, 0xFFFF, sum = 0
3637 09:57:44.326084 9, 0xFFFF, sum = 0
3638 09:57:44.326152 10, 0xFFFF, sum = 0
3639 09:57:44.326206 11, 0xFFFF, sum = 0
3640 09:57:44.326260 12, 0x0, sum = 1
3641 09:57:44.326313 13, 0x0, sum = 2
3642 09:57:44.326366 14, 0x0, sum = 3
3643 09:57:44.326438 15, 0x0, sum = 4
3644 09:57:44.326494 best_step = 13
3645 09:57:44.326553
3646 09:57:44.326605 ==
3647 09:57:44.326658 Dram Type= 6, Freq= 0, CH_1, rank 1
3648 09:57:44.326721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3649 09:57:44.326784 ==
3650 09:57:44.326847 RX Vref Scan: 0
3651 09:57:44.326910
3652 09:57:44.326994 RX Vref 0 -> 0, step: 1
3653 09:57:44.327082
3654 09:57:44.327168 RX Delay -21 -> 252, step: 4
3655 09:57:44.327254 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3656 09:57:44.327342 iDelay=195, Bit 1, Center 108 (39 ~ 178) 140
3657 09:57:44.327425 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3658 09:57:44.327507 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3659 09:57:44.327589 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3660 09:57:44.327670 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3661 09:57:44.327752 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3662 09:57:44.327839 iDelay=195, Bit 7, Center 108 (39 ~ 178) 140
3663 09:57:44.327935 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3664 09:57:44.328026 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3665 09:57:44.328110 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3666 09:57:44.328193 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3667 09:57:44.328316 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3668 09:57:44.328399 iDelay=195, Bit 13, Center 114 (47 ~ 182) 136
3669 09:57:44.328469 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3670 09:57:44.328531 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3671 09:57:44.328598 ==
3672 09:57:44.328661 Dram Type= 6, Freq= 0, CH_1, rank 1
3673 09:57:44.328722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3674 09:57:44.328804 ==
3675 09:57:44.328894 DQS Delay:
3676 09:57:44.328979 DQS0 = 0, DQS1 = 0
3677 09:57:44.329060 DQM Delay:
3678 09:57:44.329147 DQM0 = 111, DQM1 = 110
3679 09:57:44.329229 DQ Delay:
3680 09:57:44.329310 DQ0 =114, DQ1 =108, DQ2 =100, DQ3 =108
3681 09:57:44.329392 DQ4 =108, DQ5 =120, DQ6 =122, DQ7 =108
3682 09:57:44.329473 DQ8 =96, DQ9 =102, DQ10 =110, DQ11 =104
3683 09:57:44.329555 DQ12 =118, DQ13 =114, DQ14 =118, DQ15 =118
3684 09:57:44.329636
3685 09:57:44.329716
3686 09:57:44.329830 [DQSOSCAuto] RK1, (LSB)MR18= 0xf908, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 412 ps
3687 09:57:44.329912 CH1 RK1: MR19=304, MR18=F908
3688 09:57:44.329998 CH1_RK1: MR19=0x304, MR18=0xF908, DQSOSC=406, MR23=63, INC=39, DEC=26
3689 09:57:44.330070 [RxdqsGatingPostProcess] freq 1200
3690 09:57:44.330155 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3691 09:57:44.330237 best DQS0 dly(2T, 0.5T) = (0, 11)
3692 09:57:44.330320 best DQS1 dly(2T, 0.5T) = (0, 11)
3693 09:57:44.330402 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3694 09:57:44.330484 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3695 09:57:44.330575 best DQS0 dly(2T, 0.5T) = (0, 11)
3696 09:57:44.330662 best DQS1 dly(2T, 0.5T) = (0, 11)
3697 09:57:44.330747 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3698 09:57:44.330833 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3699 09:57:44.330915 Pre-setting of DQS Precalculation
3700 09:57:44.330997 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3701 09:57:44.331080 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3702 09:57:44.331164 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3703 09:57:44.331245
3704 09:57:44.331325
3705 09:57:44.331406 [Calibration Summary] 2400 Mbps
3706 09:57:44.331487 CH 0, Rank 0
3707 09:57:44.331569 SW Impedance : PASS
3708 09:57:44.331650 DUTY Scan : NO K
3709 09:57:44.331731 ZQ Calibration : PASS
3710 09:57:44.331813 Jitter Meter : NO K
3711 09:57:44.331929 CBT Training : PASS
3712 09:57:44.332026 Write leveling : PASS
3713 09:57:44.332109 RX DQS gating : PASS
3714 09:57:44.332192 RX DQ/DQS(RDDQC) : PASS
3715 09:57:44.332272 TX DQ/DQS : PASS
3716 09:57:44.332327 RX DATLAT : PASS
3717 09:57:44.332379 RX DQ/DQS(Engine): PASS
3718 09:57:44.332431 TX OE : NO K
3719 09:57:44.332484 All Pass.
3720 09:57:44.332536
3721 09:57:44.332588 CH 0, Rank 1
3722 09:57:44.332640 SW Impedance : PASS
3723 09:57:44.332693 DUTY Scan : NO K
3724 09:57:44.332745 ZQ Calibration : PASS
3725 09:57:44.332797 Jitter Meter : NO K
3726 09:57:44.332849 CBT Training : PASS
3727 09:57:44.332902 Write leveling : PASS
3728 09:57:44.332954 RX DQS gating : PASS
3729 09:57:44.333006 RX DQ/DQS(RDDQC) : PASS
3730 09:57:44.333058 TX DQ/DQS : PASS
3731 09:57:44.333110 RX DATLAT : PASS
3732 09:57:44.333162 RX DQ/DQS(Engine): PASS
3733 09:57:44.333215 TX OE : NO K
3734 09:57:44.333268 All Pass.
3735 09:57:44.333320
3736 09:57:44.333371 CH 1, Rank 0
3737 09:57:44.333423 SW Impedance : PASS
3738 09:57:44.333476 DUTY Scan : NO K
3739 09:57:44.333528 ZQ Calibration : PASS
3740 09:57:44.333580 Jitter Meter : NO K
3741 09:57:44.333633 CBT Training : PASS
3742 09:57:44.333685 Write leveling : PASS
3743 09:57:44.333737 RX DQS gating : PASS
3744 09:57:44.333789 RX DQ/DQS(RDDQC) : PASS
3745 09:57:44.333841 TX DQ/DQS : PASS
3746 09:57:44.333893 RX DATLAT : PASS
3747 09:57:44.333945 RX DQ/DQS(Engine): PASS
3748 09:57:44.333997 TX OE : NO K
3749 09:57:44.334049 All Pass.
3750 09:57:44.334101
3751 09:57:44.334152 CH 1, Rank 1
3752 09:57:44.334205 SW Impedance : PASS
3753 09:57:44.334257 DUTY Scan : NO K
3754 09:57:44.334309 ZQ Calibration : PASS
3755 09:57:44.334361 Jitter Meter : NO K
3756 09:57:44.334413 CBT Training : PASS
3757 09:57:44.334466 Write leveling : PASS
3758 09:57:44.334518 RX DQS gating : PASS
3759 09:57:44.334571 RX DQ/DQS(RDDQC) : PASS
3760 09:57:44.334624 TX DQ/DQS : PASS
3761 09:57:44.334676 RX DATLAT : PASS
3762 09:57:44.334728 RX DQ/DQS(Engine): PASS
3763 09:57:44.334780 TX OE : NO K
3764 09:57:44.334832 All Pass.
3765 09:57:44.334884
3766 09:57:44.334936 DramC Write-DBI off
3767 09:57:44.334988 PER_BANK_REFRESH: Hybrid Mode
3768 09:57:44.335041 TX_TRACKING: ON
3769 09:57:44.335093 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3770 09:57:44.335146 [FAST_K] Save calibration result to emmc
3771 09:57:44.335205 dramc_set_vcore_voltage set vcore to 650000
3772 09:57:44.335259 Read voltage for 600, 5
3773 09:57:44.335312 Vio18 = 0
3774 09:57:44.335363 Vcore = 650000
3775 09:57:44.335418 Vdram = 0
3776 09:57:44.335478 Vddq = 0
3777 09:57:44.335749 Vmddr = 0
3778 09:57:44.335896 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3779 09:57:44.335988 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3780 09:57:44.336073 MEM_TYPE=3, freq_sel=19
3781 09:57:44.336163 sv_algorithm_assistance_LP4_1600
3782 09:57:44.336266 ============ PULL DRAM RESETB DOWN ============
3783 09:57:44.336355 ========== PULL DRAM RESETB DOWN end =========
3784 09:57:44.336440 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3785 09:57:44.336544 ===================================
3786 09:57:44.336632 LPDDR4 DRAM CONFIGURATION
3787 09:57:44.336714 ===================================
3788 09:57:44.336796 EX_ROW_EN[0] = 0x0
3789 09:57:44.336877 EX_ROW_EN[1] = 0x0
3790 09:57:44.336974 LP4Y_EN = 0x0
3791 09:57:44.337071 WORK_FSP = 0x0
3792 09:57:44.337152 WL = 0x2
3793 09:57:44.337233 RL = 0x2
3794 09:57:44.337314 BL = 0x2
3795 09:57:44.337395 RPST = 0x0
3796 09:57:44.337475 RD_PRE = 0x0
3797 09:57:44.337556 WR_PRE = 0x1
3798 09:57:44.337637 WR_PST = 0x0
3799 09:57:44.337718 DBI_WR = 0x0
3800 09:57:44.337799 DBI_RD = 0x0
3801 09:57:44.337879 OTF = 0x1
3802 09:57:44.337961 ===================================
3803 09:57:44.338043 ===================================
3804 09:57:44.338124 ANA top config
3805 09:57:44.338208 ===================================
3806 09:57:44.338293 DLL_ASYNC_EN = 0
3807 09:57:44.338376 ALL_SLAVE_EN = 1
3808 09:57:44.338461 NEW_RANK_MODE = 1
3809 09:57:44.338563 DLL_IDLE_MODE = 1
3810 09:57:44.338676 LP45_APHY_COMB_EN = 1
3811 09:57:44.338761 TX_ODT_DIS = 1
3812 09:57:44.338845 NEW_8X_MODE = 1
3813 09:57:44.338929 ===================================
3814 09:57:44.339022 ===================================
3815 09:57:44.339108 data_rate = 1200
3816 09:57:44.339191 CKR = 1
3817 09:57:44.339276 DQ_P2S_RATIO = 8
3818 09:57:44.339360 ===================================
3819 09:57:44.339443 CA_P2S_RATIO = 8
3820 09:57:44.339526 DQ_CA_OPEN = 0
3821 09:57:44.339609 DQ_SEMI_OPEN = 0
3822 09:57:44.339692 CA_SEMI_OPEN = 0
3823 09:57:44.339775 CA_FULL_RATE = 0
3824 09:57:44.339857 DQ_CKDIV4_EN = 1
3825 09:57:44.339940 CA_CKDIV4_EN = 1
3826 09:57:44.340024 CA_PREDIV_EN = 0
3827 09:57:44.340106 PH8_DLY = 0
3828 09:57:44.340189 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3829 09:57:44.340271 DQ_AAMCK_DIV = 4
3830 09:57:44.340325 CA_AAMCK_DIV = 4
3831 09:57:44.340377 CA_ADMCK_DIV = 4
3832 09:57:44.340430 DQ_TRACK_CA_EN = 0
3833 09:57:44.340482 CA_PICK = 600
3834 09:57:44.340535 CA_MCKIO = 600
3835 09:57:44.340587 MCKIO_SEMI = 0
3836 09:57:44.340639 PLL_FREQ = 2288
3837 09:57:44.340692 DQ_UI_PI_RATIO = 32
3838 09:57:44.340745 CA_UI_PI_RATIO = 0
3839 09:57:44.340797 ===================================
3840 09:57:44.340850 ===================================
3841 09:57:44.340903 memory_type:LPDDR4
3842 09:57:44.340955 GP_NUM : 10
3843 09:57:44.341008 SRAM_EN : 1
3844 09:57:44.341060 MD32_EN : 0
3845 09:57:44.341112 ===================================
3846 09:57:44.341165 [ANA_INIT] >>>>>>>>>>>>>>
3847 09:57:44.341217 <<<<<< [CONFIGURE PHASE]: ANA_TX
3848 09:57:44.341270 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3849 09:57:44.341323 ===================================
3850 09:57:44.341376 data_rate = 1200,PCW = 0X5800
3851 09:57:44.341428 ===================================
3852 09:57:44.341480 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3853 09:57:44.341533 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3854 09:57:44.341586 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3855 09:57:44.341638 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3856 09:57:44.341692 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3857 09:57:44.341745 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3858 09:57:44.341799 [ANA_INIT] flow start
3859 09:57:44.341851 [ANA_INIT] PLL >>>>>>>>
3860 09:57:44.341903 [ANA_INIT] PLL <<<<<<<<
3861 09:57:44.341955 [ANA_INIT] MIDPI >>>>>>>>
3862 09:57:44.342007 [ANA_INIT] MIDPI <<<<<<<<
3863 09:57:44.342059 [ANA_INIT] DLL >>>>>>>>
3864 09:57:44.342111 [ANA_INIT] flow end
3865 09:57:44.342163 ============ LP4 DIFF to SE enter ============
3866 09:57:44.342216 ============ LP4 DIFF to SE exit ============
3867 09:57:44.342268 [ANA_INIT] <<<<<<<<<<<<<
3868 09:57:44.342320 [Flow] Enable top DCM control >>>>>
3869 09:57:44.342373 [Flow] Enable top DCM control <<<<<
3870 09:57:44.342425 Enable DLL master slave shuffle
3871 09:57:44.342478 ==============================================================
3872 09:57:44.342531 Gating Mode config
3873 09:57:44.342583 ==============================================================
3874 09:57:44.342636 Config description:
3875 09:57:44.342688 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3876 09:57:44.342742 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3877 09:57:44.342795 SELPH_MODE 0: By rank 1: By Phase
3878 09:57:44.342848 ==============================================================
3879 09:57:44.342902 GAT_TRACK_EN = 1
3880 09:57:44.342954 RX_GATING_MODE = 2
3881 09:57:44.343006 RX_GATING_TRACK_MODE = 2
3882 09:57:44.343059 SELPH_MODE = 1
3883 09:57:44.343111 PICG_EARLY_EN = 1
3884 09:57:44.343163 VALID_LAT_VALUE = 1
3885 09:57:44.343216 ==============================================================
3886 09:57:44.343268 Enter into Gating configuration >>>>
3887 09:57:44.343321 Exit from Gating configuration <<<<
3888 09:57:44.343374 Enter into DVFS_PRE_config >>>>>
3889 09:57:44.343426 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3890 09:57:44.343693 Exit from DVFS_PRE_config <<<<<
3891 09:57:44.343758 Enter into PICG configuration >>>>
3892 09:57:44.343813 Exit from PICG configuration <<<<
3893 09:57:44.343865 [RX_INPUT] configuration >>>>>
3894 09:57:44.343918 [RX_INPUT] configuration <<<<<
3895 09:57:44.343971 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3896 09:57:44.344023 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3897 09:57:44.344076 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3898 09:57:44.344129 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3899 09:57:44.344181 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3900 09:57:44.344276 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3901 09:57:44.344330 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3902 09:57:44.344383 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3903 09:57:44.344436 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3904 09:57:44.344488 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3905 09:57:44.344541 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3906 09:57:44.344593 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3907 09:57:44.344646 ===================================
3908 09:57:44.344698 LPDDR4 DRAM CONFIGURATION
3909 09:57:44.344751 ===================================
3910 09:57:44.344803 EX_ROW_EN[0] = 0x0
3911 09:57:44.344855 EX_ROW_EN[1] = 0x0
3912 09:57:44.344907 LP4Y_EN = 0x0
3913 09:57:44.344959 WORK_FSP = 0x0
3914 09:57:44.345010 WL = 0x2
3915 09:57:44.345062 RL = 0x2
3916 09:57:44.345114 BL = 0x2
3917 09:57:44.345166 RPST = 0x0
3918 09:57:44.345218 RD_PRE = 0x0
3919 09:57:44.345270 WR_PRE = 0x1
3920 09:57:44.345322 WR_PST = 0x0
3921 09:57:44.345373 DBI_WR = 0x0
3922 09:57:44.345425 DBI_RD = 0x0
3923 09:57:44.345477 OTF = 0x1
3924 09:57:44.345529 ===================================
3925 09:57:44.345582 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3926 09:57:44.345634 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3927 09:57:44.345687 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3928 09:57:44.345740 ===================================
3929 09:57:44.345793 LPDDR4 DRAM CONFIGURATION
3930 09:57:44.345845 ===================================
3931 09:57:44.345898 EX_ROW_EN[0] = 0x10
3932 09:57:44.345950 EX_ROW_EN[1] = 0x0
3933 09:57:44.346002 LP4Y_EN = 0x0
3934 09:57:44.346053 WORK_FSP = 0x0
3935 09:57:44.346105 WL = 0x2
3936 09:57:44.346157 RL = 0x2
3937 09:57:44.346208 BL = 0x2
3938 09:57:44.346260 RPST = 0x0
3939 09:57:44.346312 RD_PRE = 0x0
3940 09:57:44.346364 WR_PRE = 0x1
3941 09:57:44.346416 WR_PST = 0x0
3942 09:57:44.346468 DBI_WR = 0x0
3943 09:57:44.346520 DBI_RD = 0x0
3944 09:57:44.346572 OTF = 0x1
3945 09:57:44.346624 ===================================
3946 09:57:44.346676 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3947 09:57:44.346729 nWR fixed to 30
3948 09:57:44.346786 [ModeRegInit_LP4] CH0 RK0
3949 09:57:44.346840 [ModeRegInit_LP4] CH0 RK1
3950 09:57:44.346911 [ModeRegInit_LP4] CH1 RK0
3951 09:57:44.346995 [ModeRegInit_LP4] CH1 RK1
3952 09:57:44.347079 match AC timing 17
3953 09:57:44.347163 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3954 09:57:44.347238 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3955 09:57:44.347347 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3956 09:57:44.347486 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3957 09:57:44.347574 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3958 09:57:44.347659 ==
3959 09:57:44.347743 Dram Type= 6, Freq= 0, CH_0, rank 0
3960 09:57:44.347826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3961 09:57:44.347908 ==
3962 09:57:44.347993 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3963 09:57:44.348076 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3964 09:57:44.348172 [CA 0] Center 37 (7~67) winsize 61
3965 09:57:44.348278 [CA 1] Center 37 (7~67) winsize 61
3966 09:57:44.348361 [CA 2] Center 35 (5~65) winsize 61
3967 09:57:44.348419 [CA 3] Center 35 (5~65) winsize 61
3968 09:57:44.461940 [CA 4] Center 34 (4~65) winsize 62
3969 09:57:44.462088 [CA 5] Center 34 (4~64) winsize 61
3970 09:57:44.462155
3971 09:57:44.462217 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3972 09:57:44.462277
3973 09:57:44.462335 [CATrainingPosCal] consider 1 rank data
3974 09:57:44.462392 u2DelayCellTimex100 = 270/100 ps
3975 09:57:44.462449 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3976 09:57:44.462506 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3977 09:57:44.462561 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3978 09:57:44.462617 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3979 09:57:44.462673 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3980 09:57:44.462727 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3981 09:57:44.462781
3982 09:57:44.462834 CA PerBit enable=1, Macro0, CA PI delay=34
3983 09:57:44.462889
3984 09:57:44.462942 [CBTSetCACLKResult] CA Dly = 34
3985 09:57:44.462996 CS Dly: 5 (0~36)
3986 09:57:44.463050 ==
3987 09:57:44.463105 Dram Type= 6, Freq= 0, CH_0, rank 1
3988 09:57:44.463159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3989 09:57:44.463214 ==
3990 09:57:44.463268 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3991 09:57:44.463323 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3992 09:57:44.463378 [CA 0] Center 37 (7~67) winsize 61
3993 09:57:44.463432 [CA 1] Center 37 (7~67) winsize 61
3994 09:57:44.463486 [CA 2] Center 35 (5~65) winsize 61
3995 09:57:44.463540 [CA 3] Center 35 (5~65) winsize 61
3996 09:57:44.463594 [CA 4] Center 34 (4~65) winsize 62
3997 09:57:44.463648 [CA 5] Center 34 (3~65) winsize 63
3998 09:57:44.463702
3999 09:57:44.463756 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4000 09:57:44.463810
4001 09:57:44.463864 [CATrainingPosCal] consider 2 rank data
4002 09:57:44.463917 u2DelayCellTimex100 = 270/100 ps
4003 09:57:44.463971 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4004 09:57:44.464025 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4005 09:57:44.464078 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4006 09:57:44.464132 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4007 09:57:44.464185 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4008 09:57:44.464251 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4009 09:57:44.464306
4010 09:57:44.464573 CA PerBit enable=1, Macro0, CA PI delay=34
4011 09:57:44.464635
4012 09:57:44.464690 [CBTSetCACLKResult] CA Dly = 34
4013 09:57:44.464745 CS Dly: 5 (0~36)
4014 09:57:44.464799
4015 09:57:44.464853 ----->DramcWriteLeveling(PI) begin...
4016 09:57:44.464908 ==
4017 09:57:44.464962 Dram Type= 6, Freq= 0, CH_0, rank 0
4018 09:57:44.465015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4019 09:57:44.465070 ==
4020 09:57:44.465123 Write leveling (Byte 0): 31 => 31
4021 09:57:44.465177 Write leveling (Byte 1): 31 => 31
4022 09:57:44.465230 DramcWriteLeveling(PI) end<-----
4023 09:57:44.465284
4024 09:57:44.465337 ==
4025 09:57:44.465394 Dram Type= 6, Freq= 0, CH_0, rank 0
4026 09:57:44.465458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4027 09:57:44.465513 ==
4028 09:57:44.465567 [Gating] SW mode calibration
4029 09:57:44.465621 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4030 09:57:44.465676 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4031 09:57:44.465730 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4032 09:57:44.465784 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4033 09:57:44.465838 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4034 09:57:44.465892 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
4035 09:57:44.465945 0 9 16 | B1->B0 | 3030 2c2c | 1 0 | (1 1) (0 0)
4036 09:57:44.465999 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4037 09:57:44.466052 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 09:57:44.466106 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 09:57:44.466160 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4040 09:57:44.466213 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 09:57:44.466267 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 09:57:44.466321 0 10 12 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
4043 09:57:44.466374 0 10 16 | B1->B0 | 3434 3a3a | 0 0 | (0 0) (0 0)
4044 09:57:44.466428 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 09:57:44.466482 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 09:57:44.466536 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 09:57:44.466589 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 09:57:44.466643 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 09:57:44.466697 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 09:57:44.466750 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 09:57:44.466804 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4052 09:57:44.466857 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 09:57:44.466911 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 09:57:44.466965 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 09:57:44.467018 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 09:57:44.467071 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 09:57:44.467124 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 09:57:44.467178 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 09:57:44.467232 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 09:57:44.467285 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 09:57:44.467339 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 09:57:44.467391 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 09:57:44.467463 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 09:57:44.467518 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 09:57:44.467571 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 09:57:44.467624 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4067 09:57:44.467678 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4068 09:57:44.467731 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 09:57:44.467786 Total UI for P1: 0, mck2ui 16
4070 09:57:44.467840 best dqsien dly found for B0: ( 0, 13, 14)
4071 09:57:44.467894 Total UI for P1: 0, mck2ui 16
4072 09:57:44.467948 best dqsien dly found for B1: ( 0, 13, 18)
4073 09:57:44.468002 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4074 09:57:44.468056 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4075 09:57:44.468110
4076 09:57:44.468163 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4077 09:57:44.468224 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4078 09:57:44.468279 [Gating] SW calibration Done
4079 09:57:44.468333 ==
4080 09:57:44.468388 Dram Type= 6, Freq= 0, CH_0, rank 0
4081 09:57:44.468441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4082 09:57:44.468496 ==
4083 09:57:44.468549 RX Vref Scan: 0
4084 09:57:44.468603
4085 09:57:44.468657 RX Vref 0 -> 0, step: 1
4086 09:57:44.468711
4087 09:57:44.468764 RX Delay -230 -> 252, step: 16
4088 09:57:44.468818 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4089 09:57:44.468873 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4090 09:57:44.468927 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4091 09:57:44.468980 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4092 09:57:44.469034 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4093 09:57:44.469088 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4094 09:57:44.469142 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4095 09:57:44.469196 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4096 09:57:44.469249 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4097 09:57:44.469303 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4098 09:57:44.469360 iDelay=218, Bit 10, Center 25 (-150 ~ 201) 352
4099 09:57:44.469444 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4100 09:57:44.469530 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4101 09:57:44.469588 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4102 09:57:44.469643 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4103 09:57:44.469698 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4104 09:57:44.469752 ==
4105 09:57:44.469806 Dram Type= 6, Freq= 0, CH_0, rank 0
4106 09:57:44.469861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4107 09:57:44.469915 ==
4108 09:57:44.469970 DQS Delay:
4109 09:57:44.470023 DQS0 = 0, DQS1 = 0
4110 09:57:44.470078 DQM Delay:
4111 09:57:44.470131 DQM0 = 37, DQM1 = 28
4112 09:57:44.470185 DQ Delay:
4113 09:57:44.470238 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4114 09:57:44.470292 DQ4 =41, DQ5 =17, DQ6 =49, DQ7 =49
4115 09:57:44.470346 DQ8 =17, DQ9 =17, DQ10 =25, DQ11 =17
4116 09:57:44.470603 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4117 09:57:44.470665
4118 09:57:44.470720
4119 09:57:44.470775 ==
4120 09:57:44.470829 Dram Type= 6, Freq= 0, CH_0, rank 0
4121 09:57:44.470884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4122 09:57:44.470939 ==
4123 09:57:44.470993
4124 09:57:44.471046
4125 09:57:44.471099 TX Vref Scan disable
4126 09:57:44.471153 == TX Byte 0 ==
4127 09:57:44.471207 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4128 09:57:44.471262 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4129 09:57:44.471316 == TX Byte 1 ==
4130 09:57:44.471369 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4131 09:57:44.471423 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4132 09:57:44.471477 ==
4133 09:57:44.471530 Dram Type= 6, Freq= 0, CH_0, rank 0
4134 09:57:44.471584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4135 09:57:44.471638 ==
4136 09:57:44.471691
4137 09:57:44.471745
4138 09:57:44.471799 TX Vref Scan disable
4139 09:57:44.471853 == TX Byte 0 ==
4140 09:57:44.471906 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4141 09:57:44.471960 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4142 09:57:44.472015 == TX Byte 1 ==
4143 09:57:44.472068 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4144 09:57:44.472122 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4145 09:57:44.472175
4146 09:57:44.472242 [DATLAT]
4147 09:57:44.472297 Freq=600, CH0 RK0
4148 09:57:44.472351
4149 09:57:44.472405 DATLAT Default: 0x9
4150 09:57:44.472463 0, 0xFFFF, sum = 0
4151 09:57:44.472544 1, 0xFFFF, sum = 0
4152 09:57:44.472622 2, 0xFFFF, sum = 0
4153 09:57:44.472700 3, 0xFFFF, sum = 0
4154 09:57:44.472776 4, 0xFFFF, sum = 0
4155 09:57:44.472852 5, 0xFFFF, sum = 0
4156 09:57:44.472929 6, 0xFFFF, sum = 0
4157 09:57:44.473025 7, 0xFFFF, sum = 0
4158 09:57:44.473120 8, 0x0, sum = 1
4159 09:57:44.473216 9, 0x0, sum = 2
4160 09:57:44.473313 10, 0x0, sum = 3
4161 09:57:44.473410 11, 0x0, sum = 4
4162 09:57:44.473506 best_step = 9
4163 09:57:44.473600
4164 09:57:44.473693 ==
4165 09:57:44.473787 Dram Type= 6, Freq= 0, CH_0, rank 0
4166 09:57:44.473882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4167 09:57:44.473976 ==
4168 09:57:44.474070 RX Vref Scan: 1
4169 09:57:44.474164
4170 09:57:44.474257 RX Vref 0 -> 0, step: 1
4171 09:57:44.474351
4172 09:57:44.474443 RX Delay -195 -> 252, step: 8
4173 09:57:44.474537
4174 09:57:44.474633 Set Vref, RX VrefLevel [Byte0]: 62
4175 09:57:44.474726 [Byte1]: 51
4176 09:57:44.474820
4177 09:57:44.474912 Final RX Vref Byte 0 = 62 to rank0
4178 09:57:44.475007 Final RX Vref Byte 1 = 51 to rank0
4179 09:57:44.475100 Final RX Vref Byte 0 = 62 to rank1
4180 09:57:44.475194 Final RX Vref Byte 1 = 51 to rank1==
4181 09:57:44.475287 Dram Type= 6, Freq= 0, CH_0, rank 0
4182 09:57:44.475381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4183 09:57:44.475475 ==
4184 09:57:44.475569 DQS Delay:
4185 09:57:44.475662 DQS0 = 0, DQS1 = 0
4186 09:57:44.475756 DQM Delay:
4187 09:57:44.475849 DQM0 = 36, DQM1 = 29
4188 09:57:44.475943 DQ Delay:
4189 09:57:44.476036 DQ0 =36, DQ1 =36, DQ2 =36, DQ3 =32
4190 09:57:44.476129 DQ4 =36, DQ5 =24, DQ6 =44, DQ7 =44
4191 09:57:44.476231 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4192 09:57:44.476326 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =36
4193 09:57:44.476420
4194 09:57:44.476513
4195 09:57:44.476606 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f3e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4196 09:57:44.476712 CH0 RK0: MR19=808, MR18=3F3E
4197 09:57:44.476804 CH0_RK0: MR19=0x808, MR18=0x3F3E, DQSOSC=397, MR23=63, INC=166, DEC=110
4198 09:57:44.476897
4199 09:57:44.476988 ----->DramcWriteLeveling(PI) begin...
4200 09:57:44.477083 ==
4201 09:57:44.477175 Dram Type= 6, Freq= 0, CH_0, rank 1
4202 09:57:44.477267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4203 09:57:44.477359 ==
4204 09:57:44.477451 Write leveling (Byte 0): 33 => 33
4205 09:57:44.477543 Write leveling (Byte 1): 31 => 31
4206 09:57:44.477635 DramcWriteLeveling(PI) end<-----
4207 09:57:44.477726
4208 09:57:44.477817 ==
4209 09:57:44.477909 Dram Type= 6, Freq= 0, CH_0, rank 1
4210 09:57:44.478000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4211 09:57:44.478092 ==
4212 09:57:44.478183 [Gating] SW mode calibration
4213 09:57:44.478274 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4214 09:57:44.478367 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4215 09:57:44.478458 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4216 09:57:44.478550 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4217 09:57:44.478642 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4218 09:57:44.478733 0 9 12 | B1->B0 | 3333 2f2f | 0 0 | (0 1) (1 1)
4219 09:57:44.478825 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
4220 09:57:44.478916 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4221 09:57:44.479007 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4222 09:57:44.479099 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 09:57:44.479190 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 09:57:44.479282 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 09:57:44.479373 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 09:57:44.479464 0 10 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
4227 09:57:44.479555 0 10 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
4228 09:57:44.479647 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 09:57:44.479738 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 09:57:44.479829 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 09:57:44.479920 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 09:57:44.480012 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 09:57:44.480103 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 09:57:44.480194 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4235 09:57:44.480341 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4236 09:57:44.480435 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 09:57:44.480528 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 09:57:44.480620 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 09:57:44.480712 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 09:57:44.480804 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 09:57:44.480896 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 09:57:44.480988 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 09:57:44.481080 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 09:57:44.481174 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 09:57:44.481266 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 09:57:44.481358 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 09:57:44.481662 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 09:57:44.481756 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 09:57:44.481850 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 09:57:44.481944 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4251 09:57:44.482036 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4252 09:57:44.482129 Total UI for P1: 0, mck2ui 16
4253 09:57:44.482222 best dqsien dly found for B0: ( 0, 13, 12)
4254 09:57:44.482315 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4255 09:57:44.482407 Total UI for P1: 0, mck2ui 16
4256 09:57:44.482499 best dqsien dly found for B1: ( 0, 13, 18)
4257 09:57:44.482591 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4258 09:57:44.482683 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4259 09:57:44.482775
4260 09:57:44.482866 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4261 09:57:44.482959 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4262 09:57:44.483051 [Gating] SW calibration Done
4263 09:57:44.483143 ==
4264 09:57:44.483235 Dram Type= 6, Freq= 0, CH_0, rank 1
4265 09:57:44.483327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4266 09:57:44.483419 ==
4267 09:57:44.483510 RX Vref Scan: 0
4268 09:57:44.483601
4269 09:57:44.483693 RX Vref 0 -> 0, step: 1
4270 09:57:44.483785
4271 09:57:44.483877 RX Delay -230 -> 252, step: 16
4272 09:57:44.483970 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4273 09:57:44.484062 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4274 09:57:44.484154 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4275 09:57:44.484302 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4276 09:57:44.484396 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4277 09:57:44.484488 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4278 09:57:44.484580 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4279 09:57:44.484673 iDelay=218, Bit 7, Center 41 (-134 ~ 217) 352
4280 09:57:44.484765 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4281 09:57:44.484856 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4282 09:57:44.484948 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4283 09:57:44.485039 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4284 09:57:44.485130 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4285 09:57:44.485221 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4286 09:57:44.485312 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4287 09:57:44.485403 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4288 09:57:44.485494 ==
4289 09:57:44.485586 Dram Type= 6, Freq= 0, CH_0, rank 1
4290 09:57:44.485678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4291 09:57:44.485769 ==
4292 09:57:44.485861 DQS Delay:
4293 09:57:44.485952 DQS0 = 0, DQS1 = 0
4294 09:57:44.486043 DQM Delay:
4295 09:57:44.486134 DQM0 = 34, DQM1 = 29
4296 09:57:44.486225 DQ Delay:
4297 09:57:44.486316 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4298 09:57:44.486407 DQ4 =33, DQ5 =25, DQ6 =41, DQ7 =41
4299 09:57:44.486501 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4300 09:57:44.486593 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4301 09:57:44.486676
4302 09:57:44.486757
4303 09:57:44.486839 ==
4304 09:57:44.486922 Dram Type= 6, Freq= 0, CH_0, rank 1
4305 09:57:44.487005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4306 09:57:44.487087 ==
4307 09:57:44.487169
4308 09:57:44.487250
4309 09:57:44.487332 TX Vref Scan disable
4310 09:57:44.487414 == TX Byte 0 ==
4311 09:57:44.487496 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4312 09:57:44.487580 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4313 09:57:44.487662 == TX Byte 1 ==
4314 09:57:44.487744 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4315 09:57:44.487827 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4316 09:57:44.487908 ==
4317 09:57:44.487991 Dram Type= 6, Freq= 0, CH_0, rank 1
4318 09:57:44.488073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4319 09:57:44.488156 ==
4320 09:57:44.488252
4321 09:57:44.488334
4322 09:57:44.488416 TX Vref Scan disable
4323 09:57:44.488498 == TX Byte 0 ==
4324 09:57:44.488580 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4325 09:57:44.488663 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4326 09:57:44.488745 == TX Byte 1 ==
4327 09:57:44.488827 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4328 09:57:44.488916 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4329 09:57:44.489015
4330 09:57:44.489101 [DATLAT]
4331 09:57:44.489182 Freq=600, CH0 RK1
4332 09:57:44.489265
4333 09:57:44.489346 DATLAT Default: 0x9
4334 09:57:44.489427 0, 0xFFFF, sum = 0
4335 09:57:44.489511 1, 0xFFFF, sum = 0
4336 09:57:44.489594 2, 0xFFFF, sum = 0
4337 09:57:44.489678 3, 0xFFFF, sum = 0
4338 09:57:44.489761 4, 0xFFFF, sum = 0
4339 09:57:44.489845 5, 0xFFFF, sum = 0
4340 09:57:44.489928 6, 0xFFFF, sum = 0
4341 09:57:44.490011 7, 0xFFFF, sum = 0
4342 09:57:44.490095 8, 0x0, sum = 1
4343 09:57:44.490178 9, 0x0, sum = 2
4344 09:57:44.490261 10, 0x0, sum = 3
4345 09:57:44.490344 11, 0x0, sum = 4
4346 09:57:44.490428 best_step = 9
4347 09:57:44.490509
4348 09:57:44.490590 ==
4349 09:57:44.490672 Dram Type= 6, Freq= 0, CH_0, rank 1
4350 09:57:44.490754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 09:57:44.490836 ==
4352 09:57:44.490917 RX Vref Scan: 0
4353 09:57:44.490998
4354 09:57:44.491079 RX Vref 0 -> 0, step: 1
4355 09:57:44.491160
4356 09:57:44.491241 RX Delay -195 -> 252, step: 8
4357 09:57:44.491323 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4358 09:57:44.491405 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4359 09:57:44.491487 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4360 09:57:44.491569 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4361 09:57:44.491651 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4362 09:57:44.491733 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4363 09:57:44.491814 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4364 09:57:44.491896 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4365 09:57:44.491978 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4366 09:57:44.492060 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4367 09:57:44.492142 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4368 09:57:44.492245 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4369 09:57:44.492315 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4370 09:57:44.492369 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4371 09:57:44.492422 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4372 09:57:44.492475 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4373 09:57:44.492528 ==
4374 09:57:44.492581 Dram Type= 6, Freq= 0, CH_0, rank 1
4375 09:57:44.492633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4376 09:57:44.492687 ==
4377 09:57:44.492739 DQS Delay:
4378 09:57:44.492791 DQS0 = 0, DQS1 = 0
4379 09:57:44.492843 DQM Delay:
4380 09:57:44.492895 DQM0 = 34, DQM1 = 27
4381 09:57:44.492948 DQ Delay:
4382 09:57:44.493001 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4383 09:57:44.493054 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4384 09:57:44.493313 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4385 09:57:44.493373 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =36
4386 09:57:44.493427
4387 09:57:44.493479
4388 09:57:44.493532 [DQSOSCAuto] RK1, (LSB)MR18= 0x6736, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4389 09:57:44.493586 CH0 RK1: MR19=808, MR18=6736
4390 09:57:44.493639 CH0_RK1: MR19=0x808, MR18=0x6736, DQSOSC=390, MR23=63, INC=172, DEC=114
4391 09:57:44.493691 [RxdqsGatingPostProcess] freq 600
4392 09:57:44.493744 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4393 09:57:44.493797 Pre-setting of DQS Precalculation
4394 09:57:44.493850 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4395 09:57:44.493903 ==
4396 09:57:44.493955 Dram Type= 6, Freq= 0, CH_1, rank 0
4397 09:57:44.494008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4398 09:57:44.494061 ==
4399 09:57:44.494114 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4400 09:57:44.494167 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4401 09:57:44.494219 [CA 0] Center 36 (6~66) winsize 61
4402 09:57:44.494272 [CA 1] Center 35 (5~66) winsize 62
4403 09:57:44.494324 [CA 2] Center 34 (4~65) winsize 62
4404 09:57:44.494376 [CA 3] Center 34 (4~65) winsize 62
4405 09:57:44.494428 [CA 4] Center 34 (4~65) winsize 62
4406 09:57:44.494481 [CA 5] Center 34 (4~64) winsize 61
4407 09:57:44.494534
4408 09:57:44.494585 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4409 09:57:44.494638
4410 09:57:44.494690 [CATrainingPosCal] consider 1 rank data
4411 09:57:44.494743 u2DelayCellTimex100 = 270/100 ps
4412 09:57:44.494796 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4413 09:57:44.494849 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4414 09:57:44.494901 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4415 09:57:44.494953 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4416 09:57:44.495006 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4417 09:57:44.495058 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4418 09:57:44.495110
4419 09:57:44.495162 CA PerBit enable=1, Macro0, CA PI delay=34
4420 09:57:44.495214
4421 09:57:44.495266 [CBTSetCACLKResult] CA Dly = 34
4422 09:57:44.495318 CS Dly: 4 (0~35)
4423 09:57:44.495371 ==
4424 09:57:44.495423 Dram Type= 6, Freq= 0, CH_1, rank 1
4425 09:57:44.495476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4426 09:57:44.495529 ==
4427 09:57:44.495582 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4428 09:57:44.495634 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4429 09:57:44.495687 [CA 0] Center 36 (6~66) winsize 61
4430 09:57:44.495739 [CA 1] Center 36 (6~66) winsize 61
4431 09:57:44.495792 [CA 2] Center 34 (4~65) winsize 62
4432 09:57:44.495844 [CA 3] Center 34 (3~65) winsize 63
4433 09:57:44.495897 [CA 4] Center 34 (4~65) winsize 62
4434 09:57:44.495948 [CA 5] Center 33 (3~64) winsize 62
4435 09:57:44.496001
4436 09:57:44.496053 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4437 09:57:44.496106
4438 09:57:44.496158 [CATrainingPosCal] consider 2 rank data
4439 09:57:44.496221 u2DelayCellTimex100 = 270/100 ps
4440 09:57:44.496275 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4441 09:57:44.496328 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4442 09:57:44.496381 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4443 09:57:44.496434 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4444 09:57:44.496486 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4445 09:57:44.496538 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4446 09:57:44.496591
4447 09:57:44.496642 CA PerBit enable=1, Macro0, CA PI delay=34
4448 09:57:44.496695
4449 09:57:44.496747 [CBTSetCACLKResult] CA Dly = 34
4450 09:57:44.496800 CS Dly: 4 (0~36)
4451 09:57:44.496853
4452 09:57:44.496905 ----->DramcWriteLeveling(PI) begin...
4453 09:57:44.496958 ==
4454 09:57:44.497011 Dram Type= 6, Freq= 0, CH_1, rank 0
4455 09:57:44.497063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4456 09:57:44.497116 ==
4457 09:57:44.497168 Write leveling (Byte 0): 31 => 31
4458 09:57:44.497220 Write leveling (Byte 1): 31 => 31
4459 09:57:44.497273 DramcWriteLeveling(PI) end<-----
4460 09:57:44.497325
4461 09:57:44.497377 ==
4462 09:57:44.497430 Dram Type= 6, Freq= 0, CH_1, rank 0
4463 09:57:44.497482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4464 09:57:44.497536 ==
4465 09:57:44.497588 [Gating] SW mode calibration
4466 09:57:44.497640 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4467 09:57:44.497694 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4468 09:57:44.497747 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4469 09:57:44.497800 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4470 09:57:44.497853 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4471 09:57:44.497905 0 9 12 | B1->B0 | 3232 3333 | 0 1 | (0 1) (1 1)
4472 09:57:44.497958 0 9 16 | B1->B0 | 2626 2525 | 0 0 | (1 0) (0 0)
4473 09:57:44.498010 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 09:57:44.498062 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 09:57:44.498114 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 09:57:44.498166 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 09:57:44.498218 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 09:57:44.498271 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 09:57:44.498324 0 10 12 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 0)
4480 09:57:44.498376 0 10 16 | B1->B0 | 4444 4141 | 1 0 | (0 0) (0 0)
4481 09:57:44.498428 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 09:57:44.498480 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 09:57:44.498533 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 09:57:44.498586 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 09:57:44.498638 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 09:57:44.498690 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 09:57:44.498744 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4488 09:57:44.498797 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4489 09:57:44.498849 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 09:57:44.498901 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 09:57:44.498953 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 09:57:44.499005 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 09:57:44.499264 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 09:57:44.499328 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 09:57:44.499382 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 09:57:44.499435 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 09:57:44.499487 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 09:57:44.499540 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 09:57:44.499593 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 09:57:44.499646 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 09:57:44.499699 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 09:57:44.499752 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 09:57:44.499805 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4504 09:57:44.499858 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 09:57:44.499910 Total UI for P1: 0, mck2ui 16
4506 09:57:44.499964 best dqsien dly found for B0: ( 0, 13, 12)
4507 09:57:44.500016 Total UI for P1: 0, mck2ui 16
4508 09:57:44.500070 best dqsien dly found for B1: ( 0, 13, 12)
4509 09:57:44.500123 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4510 09:57:44.500176 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4511 09:57:44.500284
4512 09:57:44.500338 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4513 09:57:44.500391 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4514 09:57:44.500443 [Gating] SW calibration Done
4515 09:57:44.500496 ==
4516 09:57:44.500549 Dram Type= 6, Freq= 0, CH_1, rank 0
4517 09:57:44.500601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4518 09:57:44.500654 ==
4519 09:57:44.500707 RX Vref Scan: 0
4520 09:57:44.500759
4521 09:57:44.500811 RX Vref 0 -> 0, step: 1
4522 09:57:44.500864
4523 09:57:44.500916 RX Delay -230 -> 252, step: 16
4524 09:57:44.500970 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4525 09:57:44.501023 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4526 09:57:44.501076 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4527 09:57:44.501128 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4528 09:57:44.501181 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4529 09:57:44.501234 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4530 09:57:44.501287 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4531 09:57:44.501338 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4532 09:57:44.501391 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4533 09:57:44.501443 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4534 09:57:44.501494 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4535 09:57:44.501547 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4536 09:57:44.501599 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4537 09:57:44.501652 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4538 09:57:44.501704 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4539 09:57:44.501765 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4540 09:57:44.501820 ==
4541 09:57:44.501873 Dram Type= 6, Freq= 0, CH_1, rank 0
4542 09:57:44.501926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4543 09:57:44.501985 ==
4544 09:57:44.502043 DQS Delay:
4545 09:57:44.502097 DQS0 = 0, DQS1 = 0
4546 09:57:44.502149 DQM Delay:
4547 09:57:44.502210 DQM0 = 38, DQM1 = 29
4548 09:57:44.502274 DQ Delay:
4549 09:57:44.502333 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4550 09:57:44.502392 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4551 09:57:44.502446 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4552 09:57:44.502523 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4553 09:57:44.502606
4554 09:57:44.502689
4555 09:57:44.502773 ==
4556 09:57:44.502861 Dram Type= 6, Freq= 0, CH_1, rank 0
4557 09:57:44.502947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4558 09:57:44.503031 ==
4559 09:57:44.503116
4560 09:57:44.503200
4561 09:57:44.503281 TX Vref Scan disable
4562 09:57:44.503366 == TX Byte 0 ==
4563 09:57:44.503452 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4564 09:57:44.503541 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4565 09:57:44.503629 == TX Byte 1 ==
4566 09:57:44.503712 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4567 09:57:44.503800 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4568 09:57:44.503885 ==
4569 09:57:44.503968 Dram Type= 6, Freq= 0, CH_1, rank 0
4570 09:57:44.504050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4571 09:57:44.504131 ==
4572 09:57:44.504234
4573 09:57:44.504336
4574 09:57:44.504422 TX Vref Scan disable
4575 09:57:44.504507 == TX Byte 0 ==
4576 09:57:44.504594 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4577 09:57:44.504681 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4578 09:57:44.504766 == TX Byte 1 ==
4579 09:57:44.504849 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4580 09:57:44.504936 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4581 09:57:44.505021
4582 09:57:44.505105 [DATLAT]
4583 09:57:44.505189 Freq=600, CH1 RK0
4584 09:57:44.505275
4585 09:57:44.505360 DATLAT Default: 0x9
4586 09:57:44.505445 0, 0xFFFF, sum = 0
4587 09:57:44.505534 1, 0xFFFF, sum = 0
4588 09:57:44.505622 2, 0xFFFF, sum = 0
4589 09:57:44.505709 3, 0xFFFF, sum = 0
4590 09:57:44.505797 4, 0xFFFF, sum = 0
4591 09:57:44.505884 5, 0xFFFF, sum = 0
4592 09:57:44.505974 6, 0xFFFF, sum = 0
4593 09:57:44.506060 7, 0xFFFF, sum = 0
4594 09:57:44.506143 8, 0x0, sum = 1
4595 09:57:44.506227 9, 0x0, sum = 2
4596 09:57:44.506310 10, 0x0, sum = 3
4597 09:57:44.506393 11, 0x0, sum = 4
4598 09:57:44.506477 best_step = 9
4599 09:57:44.506558
4600 09:57:44.506638 ==
4601 09:57:44.506720 Dram Type= 6, Freq= 0, CH_1, rank 0
4602 09:57:44.506802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4603 09:57:44.506883 ==
4604 09:57:44.506964 RX Vref Scan: 1
4605 09:57:44.507045
4606 09:57:44.507125 RX Vref 0 -> 0, step: 1
4607 09:57:44.507206
4608 09:57:44.507289 RX Delay -195 -> 252, step: 8
4609 09:57:44.507370
4610 09:57:44.507451 Set Vref, RX VrefLevel [Byte0]: 55
4611 09:57:44.507533 [Byte1]: 50
4612 09:57:44.507614
4613 09:57:44.507695 Final RX Vref Byte 0 = 55 to rank0
4614 09:57:44.507777 Final RX Vref Byte 1 = 50 to rank0
4615 09:57:44.507859 Final RX Vref Byte 0 = 55 to rank1
4616 09:57:44.507941 Final RX Vref Byte 1 = 50 to rank1==
4617 09:57:44.508023 Dram Type= 6, Freq= 0, CH_1, rank 0
4618 09:57:44.508105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4619 09:57:44.508187 ==
4620 09:57:44.508309 DQS Delay:
4621 09:57:44.508391 DQS0 = 0, DQS1 = 0
4622 09:57:44.508472 DQM Delay:
4623 09:57:44.508553 DQM0 = 39, DQM1 = 28
4624 09:57:44.508634 DQ Delay:
4625 09:57:44.508715 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4626 09:57:44.508797 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4627 09:57:44.508878 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4628 09:57:44.508960 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4629 09:57:44.509041
4630 09:57:44.509122
4631 09:57:44.509204 [DQSOSCAuto] RK0, (LSB)MR18= 0x2734, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 402 ps
4632 09:57:44.509287 CH1 RK0: MR19=808, MR18=2734
4633 09:57:44.509576 CH1_RK0: MR19=0x808, MR18=0x2734, DQSOSC=400, MR23=63, INC=163, DEC=109
4634 09:57:44.509664
4635 09:57:44.509746 ----->DramcWriteLeveling(PI) begin...
4636 09:57:44.509829 ==
4637 09:57:44.509912 Dram Type= 6, Freq= 0, CH_1, rank 1
4638 09:57:44.510001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4639 09:57:44.510096 ==
4640 09:57:44.510183 Write leveling (Byte 0): 31 => 31
4641 09:57:44.510265 Write leveling (Byte 1): 31 => 31
4642 09:57:44.510347 DramcWriteLeveling(PI) end<-----
4643 09:57:44.510429
4644 09:57:44.510510 ==
4645 09:57:44.510591 Dram Type= 6, Freq= 0, CH_1, rank 1
4646 09:57:44.510689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4647 09:57:44.510832 ==
4648 09:57:44.510929 [Gating] SW mode calibration
4649 09:57:44.511012 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4650 09:57:44.511097 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4651 09:57:44.511179 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4652 09:57:44.511262 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4653 09:57:44.511345 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 1)
4654 09:57:44.511427 0 9 12 | B1->B0 | 3030 2d2d | 1 1 | (0 1) (1 1)
4655 09:57:44.511509 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4656 09:57:44.511591 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4657 09:57:44.511673 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4658 09:57:44.511755 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4659 09:57:44.511837 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4660 09:57:44.511919 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4661 09:57:44.512002 0 10 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
4662 09:57:44.512083 0 10 12 | B1->B0 | 3333 3d3d | 0 0 | (0 0) (0 0)
4663 09:57:44.512165 0 10 16 | B1->B0 | 3e3e 4646 | 0 0 | (1 1) (0 0)
4664 09:57:44.512275 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4665 09:57:44.512330 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4666 09:57:44.512383 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4667 09:57:44.512436 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 09:57:44.512489 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 09:57:44.512541 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 09:57:44.512594 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4671 09:57:44.512646 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 09:57:44.512699 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 09:57:44.512751 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 09:57:44.512804 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 09:57:44.512856 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 09:57:44.512909 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 09:57:44.512962 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 09:57:44.513015 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 09:57:44.513068 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 09:57:44.513120 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 09:57:44.513172 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 09:57:44.513225 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 09:57:44.513278 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 09:57:44.513331 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 09:57:44.513383 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4686 09:57:44.513435 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4687 09:57:44.513487 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4688 09:57:44.513540 Total UI for P1: 0, mck2ui 16
4689 09:57:44.513593 best dqsien dly found for B0: ( 0, 13, 10)
4690 09:57:44.513646 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4691 09:57:44.513698 Total UI for P1: 0, mck2ui 16
4692 09:57:44.513787 best dqsien dly found for B1: ( 0, 13, 14)
4693 09:57:44.513839 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4694 09:57:44.513892 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4695 09:57:44.513944
4696 09:57:44.514035 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4697 09:57:44.514117 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4698 09:57:44.514170 [Gating] SW calibration Done
4699 09:57:44.514222 ==
4700 09:57:44.514274 Dram Type= 6, Freq= 0, CH_1, rank 1
4701 09:57:44.514327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4702 09:57:44.514379 ==
4703 09:57:44.514431 RX Vref Scan: 0
4704 09:57:44.514483
4705 09:57:44.514535 RX Vref 0 -> 0, step: 1
4706 09:57:44.514588
4707 09:57:44.514639 RX Delay -230 -> 252, step: 16
4708 09:57:44.514692 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4709 09:57:44.514744 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4710 09:57:44.514797 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4711 09:57:44.514850 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4712 09:57:44.514902 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4713 09:57:44.514954 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4714 09:57:44.515007 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4715 09:57:44.515059 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4716 09:57:44.515117 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4717 09:57:44.515205 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4718 09:57:44.515288 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4719 09:57:44.515370 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4720 09:57:44.515453 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4721 09:57:44.515535 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4722 09:57:44.515618 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4723 09:57:44.515706 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4724 09:57:44.515787 ==
4725 09:57:44.515869 Dram Type= 6, Freq= 0, CH_1, rank 1
4726 09:57:44.515951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4727 09:57:44.516032 ==
4728 09:57:44.516113 DQS Delay:
4729 09:57:44.516194 DQS0 = 0, DQS1 = 0
4730 09:57:44.516307 DQM Delay:
4731 09:57:44.516379 DQM0 = 35, DQM1 = 29
4732 09:57:44.516435 DQ Delay:
4733 09:57:44.516488 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4734 09:57:44.517636 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4735 09:57:44.520879 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4736 09:57:44.523994 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4737 09:57:44.524081
4738 09:57:44.524145
4739 09:57:44.524233 ==
4740 09:57:44.526971 Dram Type= 6, Freq= 0, CH_1, rank 1
4741 09:57:44.530337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4742 09:57:44.530434 ==
4743 09:57:44.533608
4744 09:57:44.533724
4745 09:57:44.533794 TX Vref Scan disable
4746 09:57:44.536960 == TX Byte 0 ==
4747 09:57:44.540356 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4748 09:57:44.543828 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4749 09:57:44.547233 == TX Byte 1 ==
4750 09:57:44.550043 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4751 09:57:44.553444 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4752 09:57:44.556913 ==
4753 09:57:44.560007 Dram Type= 6, Freq= 0, CH_1, rank 1
4754 09:57:44.563321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4755 09:57:44.563418 ==
4756 09:57:44.563483
4757 09:57:44.563542
4758 09:57:44.566964 TX Vref Scan disable
4759 09:57:44.567048 == TX Byte 0 ==
4760 09:57:44.573359 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4761 09:57:44.577033 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4762 09:57:44.577129 == TX Byte 1 ==
4763 09:57:44.583109 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4764 09:57:44.586464 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4765 09:57:44.586592
4766 09:57:44.586685 [DATLAT]
4767 09:57:44.590098 Freq=600, CH1 RK1
4768 09:57:44.590184
4769 09:57:44.590249 DATLAT Default: 0x9
4770 09:57:44.593054 0, 0xFFFF, sum = 0
4771 09:57:44.593138 1, 0xFFFF, sum = 0
4772 09:57:44.596603 2, 0xFFFF, sum = 0
4773 09:57:44.596688 3, 0xFFFF, sum = 0
4774 09:57:44.600070 4, 0xFFFF, sum = 0
4775 09:57:44.603160 5, 0xFFFF, sum = 0
4776 09:57:44.603245 6, 0xFFFF, sum = 0
4777 09:57:44.606539 7, 0xFFFF, sum = 0
4778 09:57:44.606622 8, 0x0, sum = 1
4779 09:57:44.606689 9, 0x0, sum = 2
4780 09:57:44.609960 10, 0x0, sum = 3
4781 09:57:44.610044 11, 0x0, sum = 4
4782 09:57:44.613516 best_step = 9
4783 09:57:44.613602
4784 09:57:44.613666 ==
4785 09:57:44.616426 Dram Type= 6, Freq= 0, CH_1, rank 1
4786 09:57:44.619744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4787 09:57:44.619855 ==
4788 09:57:44.623421 RX Vref Scan: 0
4789 09:57:44.623505
4790 09:57:44.623570 RX Vref 0 -> 0, step: 1
4791 09:57:44.623629
4792 09:57:44.626325 RX Delay -195 -> 252, step: 8
4793 09:57:44.633848 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4794 09:57:44.637052 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4795 09:57:44.640482 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4796 09:57:44.643943 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4797 09:57:44.650803 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4798 09:57:44.653607 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4799 09:57:44.657090 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4800 09:57:44.660722 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4801 09:57:44.667052 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4802 09:57:44.670204 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4803 09:57:44.673321 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4804 09:57:44.676805 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4805 09:57:44.679930 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4806 09:57:44.686636 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4807 09:57:44.690110 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4808 09:57:44.693637 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4809 09:57:44.693733 ==
4810 09:57:44.696876 Dram Type= 6, Freq= 0, CH_1, rank 1
4811 09:57:44.703504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4812 09:57:44.703590 ==
4813 09:57:44.703655 DQS Delay:
4814 09:57:44.703715 DQS0 = 0, DQS1 = 0
4815 09:57:44.706828 DQM Delay:
4816 09:57:44.706910 DQM0 = 36, DQM1 = 30
4817 09:57:44.709912 DQ Delay:
4818 09:57:44.713337 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4819 09:57:44.716753 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4820 09:57:44.719775 DQ8 =16, DQ9 =20, DQ10 =36, DQ11 =24
4821 09:57:44.722936 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4822 09:57:44.723019
4823 09:57:44.723084
4824 09:57:44.729627 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c5b, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
4825 09:57:44.733511 CH1 RK1: MR19=808, MR18=3C5B
4826 09:57:44.739906 CH1_RK1: MR19=0x808, MR18=0x3C5B, DQSOSC=392, MR23=63, INC=170, DEC=113
4827 09:57:44.742900 [RxdqsGatingPostProcess] freq 600
4828 09:57:44.746782 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4829 09:57:44.749423 Pre-setting of DQS Precalculation
4830 09:57:44.756263 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4831 09:57:44.763019 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4832 09:57:44.769204 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4833 09:57:44.769290
4834 09:57:44.769353
4835 09:57:44.772947 [Calibration Summary] 1200 Mbps
4836 09:57:44.773029 CH 0, Rank 0
4837 09:57:44.776106 SW Impedance : PASS
4838 09:57:44.779695 DUTY Scan : NO K
4839 09:57:44.779777 ZQ Calibration : PASS
4840 09:57:44.782684 Jitter Meter : NO K
4841 09:57:44.786237 CBT Training : PASS
4842 09:57:44.786319 Write leveling : PASS
4843 09:57:44.789237 RX DQS gating : PASS
4844 09:57:44.793109 RX DQ/DQS(RDDQC) : PASS
4845 09:57:44.793191 TX DQ/DQS : PASS
4846 09:57:44.796118 RX DATLAT : PASS
4847 09:57:44.799263 RX DQ/DQS(Engine): PASS
4848 09:57:44.799353 TX OE : NO K
4849 09:57:44.799419 All Pass.
4850 09:57:44.799480
4851 09:57:44.802652 CH 0, Rank 1
4852 09:57:44.805845 SW Impedance : PASS
4853 09:57:44.805927 DUTY Scan : NO K
4854 09:57:44.809572 ZQ Calibration : PASS
4855 09:57:44.809656 Jitter Meter : NO K
4856 09:57:44.812725 CBT Training : PASS
4857 09:57:44.815767 Write leveling : PASS
4858 09:57:44.815850 RX DQS gating : PASS
4859 09:57:44.819568 RX DQ/DQS(RDDQC) : PASS
4860 09:57:44.823191 TX DQ/DQS : PASS
4861 09:57:44.823275 RX DATLAT : PASS
4862 09:57:44.826003 RX DQ/DQS(Engine): PASS
4863 09:57:44.829459 TX OE : NO K
4864 09:57:44.829542 All Pass.
4865 09:57:44.829605
4866 09:57:44.829664 CH 1, Rank 0
4867 09:57:44.832767 SW Impedance : PASS
4868 09:57:44.836074 DUTY Scan : NO K
4869 09:57:44.836156 ZQ Calibration : PASS
4870 09:57:44.839658 Jitter Meter : NO K
4871 09:57:44.842704 CBT Training : PASS
4872 09:57:44.842786 Write leveling : PASS
4873 09:57:44.845785 RX DQS gating : PASS
4874 09:57:44.849086 RX DQ/DQS(RDDQC) : PASS
4875 09:57:44.849167 TX DQ/DQS : PASS
4876 09:57:44.852159 RX DATLAT : PASS
4877 09:57:44.852288 RX DQ/DQS(Engine): PASS
4878 09:57:44.855654 TX OE : NO K
4879 09:57:44.855735 All Pass.
4880 09:57:44.855799
4881 09:57:44.859352 CH 1, Rank 1
4882 09:57:44.859433 SW Impedance : PASS
4883 09:57:44.862323 DUTY Scan : NO K
4884 09:57:44.865665 ZQ Calibration : PASS
4885 09:57:44.865749 Jitter Meter : NO K
4886 09:57:44.869057 CBT Training : PASS
4887 09:57:44.872646 Write leveling : PASS
4888 09:57:44.872728 RX DQS gating : PASS
4889 09:57:44.875938 RX DQ/DQS(RDDQC) : PASS
4890 09:57:44.878909 TX DQ/DQS : PASS
4891 09:57:44.878991 RX DATLAT : PASS
4892 09:57:44.882775 RX DQ/DQS(Engine): PASS
4893 09:57:44.885927 TX OE : NO K
4894 09:57:44.886008 All Pass.
4895 09:57:44.886072
4896 09:57:44.889093 DramC Write-DBI off
4897 09:57:44.889174 PER_BANK_REFRESH: Hybrid Mode
4898 09:57:44.892729 TX_TRACKING: ON
4899 09:57:44.898955 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4900 09:57:44.905433 [FAST_K] Save calibration result to emmc
4901 09:57:44.908723 dramc_set_vcore_voltage set vcore to 662500
4902 09:57:44.908808 Read voltage for 933, 3
4903 09:57:44.912150 Vio18 = 0
4904 09:57:44.912241 Vcore = 662500
4905 09:57:44.912306 Vdram = 0
4906 09:57:44.915363 Vddq = 0
4907 09:57:44.915504 Vmddr = 0
4908 09:57:44.918416 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4909 09:57:44.925263 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4910 09:57:44.928527 MEM_TYPE=3, freq_sel=17
4911 09:57:44.931961 sv_algorithm_assistance_LP4_1600
4912 09:57:44.935551 ============ PULL DRAM RESETB DOWN ============
4913 09:57:44.938475 ========== PULL DRAM RESETB DOWN end =========
4914 09:57:44.942030 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4915 09:57:44.945220 ===================================
4916 09:57:44.948529 LPDDR4 DRAM CONFIGURATION
4917 09:57:44.952174 ===================================
4918 09:57:44.955380 EX_ROW_EN[0] = 0x0
4919 09:57:44.955462 EX_ROW_EN[1] = 0x0
4920 09:57:44.958550 LP4Y_EN = 0x0
4921 09:57:44.958632 WORK_FSP = 0x0
4922 09:57:44.962334 WL = 0x3
4923 09:57:44.962415 RL = 0x3
4924 09:57:44.965078 BL = 0x2
4925 09:57:44.965159 RPST = 0x0
4926 09:57:44.968385 RD_PRE = 0x0
4927 09:57:44.968466 WR_PRE = 0x1
4928 09:57:44.971733 WR_PST = 0x0
4929 09:57:44.975233 DBI_WR = 0x0
4930 09:57:44.975340 DBI_RD = 0x0
4931 09:57:44.978520 OTF = 0x1
4932 09:57:44.982010 ===================================
4933 09:57:44.985186 ===================================
4934 09:57:44.985294 ANA top config
4935 09:57:44.988562 ===================================
4936 09:57:44.991580 DLL_ASYNC_EN = 0
4937 09:57:44.995222 ALL_SLAVE_EN = 1
4938 09:57:44.995304 NEW_RANK_MODE = 1
4939 09:57:44.998495 DLL_IDLE_MODE = 1
4940 09:57:45.001787 LP45_APHY_COMB_EN = 1
4941 09:57:45.005126 TX_ODT_DIS = 1
4942 09:57:45.005208 NEW_8X_MODE = 1
4943 09:57:45.008145 ===================================
4944 09:57:45.011498 ===================================
4945 09:57:45.014617 data_rate = 1866
4946 09:57:45.018263 CKR = 1
4947 09:57:45.021455 DQ_P2S_RATIO = 8
4948 09:57:45.024620 ===================================
4949 09:57:45.027960 CA_P2S_RATIO = 8
4950 09:57:45.031391 DQ_CA_OPEN = 0
4951 09:57:45.031473 DQ_SEMI_OPEN = 0
4952 09:57:45.034679 CA_SEMI_OPEN = 0
4953 09:57:45.038080 CA_FULL_RATE = 0
4954 09:57:45.041631 DQ_CKDIV4_EN = 1
4955 09:57:45.044770 CA_CKDIV4_EN = 1
4956 09:57:45.047867 CA_PREDIV_EN = 0
4957 09:57:45.047947 PH8_DLY = 0
4958 09:57:45.051641 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4959 09:57:45.055136 DQ_AAMCK_DIV = 4
4960 09:57:45.057925 CA_AAMCK_DIV = 4
4961 09:57:45.061430 CA_ADMCK_DIV = 4
4962 09:57:45.064389 DQ_TRACK_CA_EN = 0
4963 09:57:45.064470 CA_PICK = 933
4964 09:57:45.067932 CA_MCKIO = 933
4965 09:57:45.071629 MCKIO_SEMI = 0
4966 09:57:45.074771 PLL_FREQ = 3732
4967 09:57:45.077925 DQ_UI_PI_RATIO = 32
4968 09:57:45.081301 CA_UI_PI_RATIO = 0
4969 09:57:45.084838 ===================================
4970 09:57:45.088186 ===================================
4971 09:57:45.091248 memory_type:LPDDR4
4972 09:57:45.091330 GP_NUM : 10
4973 09:57:45.094365 SRAM_EN : 1
4974 09:57:45.094445 MD32_EN : 0
4975 09:57:45.097969 ===================================
4976 09:57:45.101359 [ANA_INIT] >>>>>>>>>>>>>>
4977 09:57:45.104603 <<<<<< [CONFIGURE PHASE]: ANA_TX
4978 09:57:45.107842 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4979 09:57:45.111629 ===================================
4980 09:57:45.114699 data_rate = 1866,PCW = 0X8f00
4981 09:57:45.118103 ===================================
4982 09:57:45.121204 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4983 09:57:45.124685 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4984 09:57:45.131053 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4985 09:57:45.134413 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4986 09:57:45.137753 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4987 09:57:45.144449 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4988 09:57:45.144532 [ANA_INIT] flow start
4989 09:57:45.147810 [ANA_INIT] PLL >>>>>>>>
4990 09:57:45.151553 [ANA_INIT] PLL <<<<<<<<
4991 09:57:45.151633 [ANA_INIT] MIDPI >>>>>>>>
4992 09:57:45.154378 [ANA_INIT] MIDPI <<<<<<<<
4993 09:57:45.157478 [ANA_INIT] DLL >>>>>>>>
4994 09:57:45.157559 [ANA_INIT] flow end
4995 09:57:45.160886 ============ LP4 DIFF to SE enter ============
4996 09:57:45.167435 ============ LP4 DIFF to SE exit ============
4997 09:57:45.167523 [ANA_INIT] <<<<<<<<<<<<<
4998 09:57:45.171501 [Flow] Enable top DCM control >>>>>
4999 09:57:45.174903 [Flow] Enable top DCM control <<<<<
5000 09:57:45.177614 Enable DLL master slave shuffle
5001 09:57:45.183966 ==============================================================
5002 09:57:45.187176 Gating Mode config
5003 09:57:45.191033 ==============================================================
5004 09:57:45.193893 Config description:
5005 09:57:45.203938 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5006 09:57:45.210631 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5007 09:57:45.213802 SELPH_MODE 0: By rank 1: By Phase
5008 09:57:45.220901 ==============================================================
5009 09:57:45.223913 GAT_TRACK_EN = 1
5010 09:57:45.226739 RX_GATING_MODE = 2
5011 09:57:45.230316 RX_GATING_TRACK_MODE = 2
5012 09:57:45.230399 SELPH_MODE = 1
5013 09:57:45.233950 PICG_EARLY_EN = 1
5014 09:57:45.237453 VALID_LAT_VALUE = 1
5015 09:57:45.244045 ==============================================================
5016 09:57:45.246832 Enter into Gating configuration >>>>
5017 09:57:45.250374 Exit from Gating configuration <<<<
5018 09:57:45.253622 Enter into DVFS_PRE_config >>>>>
5019 09:57:45.263439 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5020 09:57:45.266823 Exit from DVFS_PRE_config <<<<<
5021 09:57:45.270341 Enter into PICG configuration >>>>
5022 09:57:45.273433 Exit from PICG configuration <<<<
5023 09:57:45.277089 [RX_INPUT] configuration >>>>>
5024 09:57:45.280369 [RX_INPUT] configuration <<<<<
5025 09:57:45.283299 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5026 09:57:45.290161 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5027 09:57:45.296427 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5028 09:57:45.303851 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5029 09:57:45.310238 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5030 09:57:45.313226 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5031 09:57:45.319679 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5032 09:57:45.323264 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5033 09:57:45.326417 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5034 09:57:45.329598 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5035 09:57:45.336426 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5036 09:57:45.339341 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5037 09:57:45.342954 ===================================
5038 09:57:45.346381 LPDDR4 DRAM CONFIGURATION
5039 09:57:45.349720 ===================================
5040 09:57:45.349820 EX_ROW_EN[0] = 0x0
5041 09:57:45.352602 EX_ROW_EN[1] = 0x0
5042 09:57:45.352710 LP4Y_EN = 0x0
5043 09:57:45.356010 WORK_FSP = 0x0
5044 09:57:45.356106 WL = 0x3
5045 09:57:45.359144 RL = 0x3
5046 09:57:45.359249 BL = 0x2
5047 09:57:45.362753 RPST = 0x0
5048 09:57:45.365901 RD_PRE = 0x0
5049 09:57:45.365986 WR_PRE = 0x1
5050 09:57:45.369060 WR_PST = 0x0
5051 09:57:45.369132 DBI_WR = 0x0
5052 09:57:45.372637 DBI_RD = 0x0
5053 09:57:45.372726 OTF = 0x1
5054 09:57:45.375631 ===================================
5055 09:57:45.379198 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5056 09:57:45.385573 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5057 09:57:45.389495 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5058 09:57:45.392441 ===================================
5059 09:57:45.396021 LPDDR4 DRAM CONFIGURATION
5060 09:57:45.399070 ===================================
5061 09:57:45.399180 EX_ROW_EN[0] = 0x10
5062 09:57:45.402553 EX_ROW_EN[1] = 0x0
5063 09:57:45.402655 LP4Y_EN = 0x0
5064 09:57:45.405428 WORK_FSP = 0x0
5065 09:57:45.405531 WL = 0x3
5066 09:57:45.409176 RL = 0x3
5067 09:57:45.409281 BL = 0x2
5068 09:57:45.412193 RPST = 0x0
5069 09:57:45.412376 RD_PRE = 0x0
5070 09:57:45.416085 WR_PRE = 0x1
5071 09:57:45.418957 WR_PST = 0x0
5072 09:57:45.419061 DBI_WR = 0x0
5073 09:57:45.421966 DBI_RD = 0x0
5074 09:57:45.422067 OTF = 0x1
5075 09:57:45.425342 ===================================
5076 09:57:45.432147 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5077 09:57:45.435747 nWR fixed to 30
5078 09:57:45.439333 [ModeRegInit_LP4] CH0 RK0
5079 09:57:45.439415 [ModeRegInit_LP4] CH0 RK1
5080 09:57:45.442429 [ModeRegInit_LP4] CH1 RK0
5081 09:57:45.445542 [ModeRegInit_LP4] CH1 RK1
5082 09:57:45.445651 match AC timing 9
5083 09:57:45.452767 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5084 09:57:45.455399 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5085 09:57:45.458848 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5086 09:57:45.465682 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5087 09:57:45.469174 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5088 09:57:45.469254 ==
5089 09:57:45.472528 Dram Type= 6, Freq= 0, CH_0, rank 0
5090 09:57:45.475641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5091 09:57:45.475752 ==
5092 09:57:45.482188 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5093 09:57:45.489175 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5094 09:57:45.492030 [CA 0] Center 38 (8~69) winsize 62
5095 09:57:45.495980 [CA 1] Center 38 (7~69) winsize 63
5096 09:57:45.499013 [CA 2] Center 35 (5~65) winsize 61
5097 09:57:45.502036 [CA 3] Center 35 (5~65) winsize 61
5098 09:57:45.505606 [CA 4] Center 34 (4~65) winsize 62
5099 09:57:45.509133 [CA 5] Center 34 (4~64) winsize 61
5100 09:57:45.509207
5101 09:57:45.512094 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5102 09:57:45.512216
5103 09:57:45.515696 [CATrainingPosCal] consider 1 rank data
5104 09:57:45.519007 u2DelayCellTimex100 = 270/100 ps
5105 09:57:45.522577 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5106 09:57:45.525509 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5107 09:57:45.528542 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5108 09:57:45.531758 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5109 09:57:45.535318 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5110 09:57:45.538481 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5111 09:57:45.541941
5112 09:57:45.545008 CA PerBit enable=1, Macro0, CA PI delay=34
5113 09:57:45.545104
5114 09:57:45.548560 [CBTSetCACLKResult] CA Dly = 34
5115 09:57:45.548657 CS Dly: 7 (0~38)
5116 09:57:45.548747 ==
5117 09:57:45.552004 Dram Type= 6, Freq= 0, CH_0, rank 1
5118 09:57:45.555176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5119 09:57:45.555272 ==
5120 09:57:45.561983 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5121 09:57:45.568651 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5122 09:57:45.571928 [CA 0] Center 38 (8~69) winsize 62
5123 09:57:45.575210 [CA 1] Center 38 (8~69) winsize 62
5124 09:57:45.578328 [CA 2] Center 35 (5~66) winsize 62
5125 09:57:45.581895 [CA 3] Center 35 (5~66) winsize 62
5126 09:57:45.585272 [CA 4] Center 34 (4~65) winsize 62
5127 09:57:45.588431 [CA 5] Center 33 (3~64) winsize 62
5128 09:57:45.588535
5129 09:57:45.592085 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5130 09:57:45.592196
5131 09:57:45.594903 [CATrainingPosCal] consider 2 rank data
5132 09:57:45.598394 u2DelayCellTimex100 = 270/100 ps
5133 09:57:45.601937 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5134 09:57:45.605103 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5135 09:57:45.608477 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5136 09:57:45.611369 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5137 09:57:45.615115 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5138 09:57:45.621420 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5139 09:57:45.621533
5140 09:57:45.625108 CA PerBit enable=1, Macro0, CA PI delay=34
5141 09:57:45.625199
5142 09:57:45.628228 [CBTSetCACLKResult] CA Dly = 34
5143 09:57:45.628322 CS Dly: 7 (0~38)
5144 09:57:45.628385
5145 09:57:45.631467 ----->DramcWriteLeveling(PI) begin...
5146 09:57:45.631544 ==
5147 09:57:45.634670 Dram Type= 6, Freq= 0, CH_0, rank 0
5148 09:57:45.641421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5149 09:57:45.641514 ==
5150 09:57:45.644718 Write leveling (Byte 0): 30 => 30
5151 09:57:45.644812 Write leveling (Byte 1): 30 => 30
5152 09:57:45.648085 DramcWriteLeveling(PI) end<-----
5153 09:57:45.648207
5154 09:57:45.648329 ==
5155 09:57:45.651203 Dram Type= 6, Freq= 0, CH_0, rank 0
5156 09:57:45.657986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5157 09:57:45.658084 ==
5158 09:57:45.661302 [Gating] SW mode calibration
5159 09:57:45.668070 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5160 09:57:45.671026 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5161 09:57:45.677834 0 14 0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
5162 09:57:45.681277 0 14 4 | B1->B0 | 2c2c 3434 | 1 1 | (0 0) (1 1)
5163 09:57:45.684766 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5164 09:57:45.691092 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5165 09:57:45.694629 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5166 09:57:45.697440 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5167 09:57:45.704227 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5168 09:57:45.707505 0 14 28 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
5169 09:57:45.711076 0 15 0 | B1->B0 | 3333 2727 | 0 1 | (0 0) (1 0)
5170 09:57:45.717681 0 15 4 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
5171 09:57:45.721294 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5172 09:57:45.724102 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5173 09:57:45.731177 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5174 09:57:45.734377 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5175 09:57:45.737890 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5176 09:57:45.744167 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 09:57:45.747619 1 0 0 | B1->B0 | 2e2e 3d3d | 0 0 | (0 0) (0 0)
5178 09:57:45.750770 1 0 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5179 09:57:45.754225 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 09:57:45.760961 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 09:57:45.764014 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 09:57:45.767372 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 09:57:45.774192 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 09:57:45.777321 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5185 09:57:45.780565 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5186 09:57:45.787245 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5187 09:57:45.790659 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5188 09:57:45.793632 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 09:57:45.800455 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 09:57:45.803756 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 09:57:45.807191 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 09:57:45.813902 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 09:57:45.817148 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 09:57:45.820420 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 09:57:45.827374 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 09:57:45.830188 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 09:57:45.833384 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 09:57:45.840199 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 09:57:45.843904 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 09:57:45.846748 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 09:57:45.853536 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5202 09:57:45.857348 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5203 09:57:45.860047 Total UI for P1: 0, mck2ui 16
5204 09:57:45.863382 best dqsien dly found for B0: ( 1, 3, 0)
5205 09:57:45.866875 Total UI for P1: 0, mck2ui 16
5206 09:57:45.869952 best dqsien dly found for B1: ( 1, 3, 2)
5207 09:57:45.873824 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5208 09:57:45.877167 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5209 09:57:45.877318
5210 09:57:45.879870 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5211 09:57:45.883514 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5212 09:57:45.886370 [Gating] SW calibration Done
5213 09:57:45.886520 ==
5214 09:57:45.889743 Dram Type= 6, Freq= 0, CH_0, rank 0
5215 09:57:45.893074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5216 09:57:45.893234 ==
5217 09:57:45.896458 RX Vref Scan: 0
5218 09:57:45.896596
5219 09:57:45.899536 RX Vref 0 -> 0, step: 1
5220 09:57:45.899671
5221 09:57:45.899773 RX Delay -80 -> 252, step: 8
5222 09:57:45.920250 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5223 09:57:45.920432 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5224 09:57:45.920538 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5225 09:57:45.920631 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5226 09:57:45.920724 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5227 09:57:45.923147 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5228 09:57:45.929882 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5229 09:57:45.933288 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5230 09:57:45.936865 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5231 09:57:45.939746 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5232 09:57:45.943329 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5233 09:57:45.949771 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5234 09:57:45.953055 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5235 09:57:45.956781 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5236 09:57:45.959742 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5237 09:57:45.963413 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5238 09:57:45.966223 ==
5239 09:57:45.966339 Dram Type= 6, Freq= 0, CH_0, rank 0
5240 09:57:45.973052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5241 09:57:45.973185 ==
5242 09:57:45.973290 DQS Delay:
5243 09:57:45.976261 DQS0 = 0, DQS1 = 0
5244 09:57:45.976378 DQM Delay:
5245 09:57:45.979797 DQM0 = 94, DQM1 = 83
5246 09:57:45.979948 DQ Delay:
5247 09:57:45.982975 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5248 09:57:45.986514 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5249 09:57:45.989707 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5250 09:57:45.992798 DQ12 =91, DQ13 =87, DQ14 =91, DQ15 =91
5251 09:57:45.992941
5252 09:57:45.993044
5253 09:57:45.993145 ==
5254 09:57:45.996256 Dram Type= 6, Freq= 0, CH_0, rank 0
5255 09:57:45.999259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5256 09:57:45.999398 ==
5257 09:57:45.999472
5258 09:57:45.999538
5259 09:57:46.002557 TX Vref Scan disable
5260 09:57:46.006251 == TX Byte 0 ==
5261 09:57:46.009461 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5262 09:57:46.012846 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5263 09:57:46.015880 == TX Byte 1 ==
5264 09:57:46.019173 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5265 09:57:46.022341 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5266 09:57:46.022488 ==
5267 09:57:46.025862 Dram Type= 6, Freq= 0, CH_0, rank 0
5268 09:57:46.032698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5269 09:57:46.032890 ==
5270 09:57:46.032999
5271 09:57:46.033096
5272 09:57:46.033195 TX Vref Scan disable
5273 09:57:46.036366 == TX Byte 0 ==
5274 09:57:46.039994 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5275 09:57:46.046186 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5276 09:57:46.046360 == TX Byte 1 ==
5277 09:57:46.050036 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5278 09:57:46.056321 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5279 09:57:46.056493
5280 09:57:46.056603 [DATLAT]
5281 09:57:46.056716 Freq=933, CH0 RK0
5282 09:57:46.056809
5283 09:57:46.059691 DATLAT Default: 0xd
5284 09:57:46.059824 0, 0xFFFF, sum = 0
5285 09:57:46.063411 1, 0xFFFF, sum = 0
5286 09:57:46.063551 2, 0xFFFF, sum = 0
5287 09:57:46.066694 3, 0xFFFF, sum = 0
5288 09:57:46.066824 4, 0xFFFF, sum = 0
5289 09:57:46.069877 5, 0xFFFF, sum = 0
5290 09:57:46.073027 6, 0xFFFF, sum = 0
5291 09:57:46.073145 7, 0xFFFF, sum = 0
5292 09:57:46.076713 8, 0xFFFF, sum = 0
5293 09:57:46.076825 9, 0xFFFF, sum = 0
5294 09:57:46.079832 10, 0x0, sum = 1
5295 09:57:46.079962 11, 0x0, sum = 2
5296 09:57:46.083032 12, 0x0, sum = 3
5297 09:57:46.083127 13, 0x0, sum = 4
5298 09:57:46.083205 best_step = 11
5299 09:57:46.083319
5300 09:57:46.086333 ==
5301 09:57:46.089941 Dram Type= 6, Freq= 0, CH_0, rank 0
5302 09:57:46.092760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5303 09:57:46.092899 ==
5304 09:57:46.093013 RX Vref Scan: 1
5305 09:57:46.093121
5306 09:57:46.096298 RX Vref 0 -> 0, step: 1
5307 09:57:46.096443
5308 09:57:46.099638 RX Delay -69 -> 252, step: 4
5309 09:57:46.099772
5310 09:57:46.102504 Set Vref, RX VrefLevel [Byte0]: 62
5311 09:57:46.106621 [Byte1]: 51
5312 09:57:46.106789
5313 09:57:46.109271 Final RX Vref Byte 0 = 62 to rank0
5314 09:57:46.112882 Final RX Vref Byte 1 = 51 to rank0
5315 09:57:46.116098 Final RX Vref Byte 0 = 62 to rank1
5316 09:57:46.119294 Final RX Vref Byte 1 = 51 to rank1==
5317 09:57:46.122797 Dram Type= 6, Freq= 0, CH_0, rank 0
5318 09:57:46.125850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5319 09:57:46.129320 ==
5320 09:57:46.129442 DQS Delay:
5321 09:57:46.129552 DQS0 = 0, DQS1 = 0
5322 09:57:46.132444 DQM Delay:
5323 09:57:46.132620 DQM0 = 95, DQM1 = 82
5324 09:57:46.135895 DQ Delay:
5325 09:57:46.136048 DQ0 =94, DQ1 =98, DQ2 =92, DQ3 =92
5326 09:57:46.139197 DQ4 =94, DQ5 =84, DQ6 =102, DQ7 =106
5327 09:57:46.142500 DQ8 =76, DQ9 =68, DQ10 =82, DQ11 =76
5328 09:57:46.146280 DQ12 =86, DQ13 =88, DQ14 =94, DQ15 =90
5329 09:57:46.149077
5330 09:57:46.149236
5331 09:57:46.155952 [DQSOSCAuto] RK0, (LSB)MR18= 0x1615, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 414 ps
5332 09:57:46.159151 CH0 RK0: MR19=505, MR18=1615
5333 09:57:46.165718 CH0_RK0: MR19=0x505, MR18=0x1615, DQSOSC=414, MR23=63, INC=63, DEC=42
5334 09:57:46.165904
5335 09:57:46.169029 ----->DramcWriteLeveling(PI) begin...
5336 09:57:46.169169 ==
5337 09:57:46.172287 Dram Type= 6, Freq= 0, CH_0, rank 1
5338 09:57:46.175746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5339 09:57:46.175882 ==
5340 09:57:46.179425 Write leveling (Byte 0): 32 => 32
5341 09:57:46.182442 Write leveling (Byte 1): 32 => 32
5342 09:57:46.185562 DramcWriteLeveling(PI) end<-----
5343 09:57:46.185709
5344 09:57:46.185810 ==
5345 09:57:46.189305 Dram Type= 6, Freq= 0, CH_0, rank 1
5346 09:57:46.192593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5347 09:57:46.192738 ==
5348 09:57:46.195483 [Gating] SW mode calibration
5349 09:57:46.202254 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5350 09:57:46.209661 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5351 09:57:46.212132 0 14 0 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
5352 09:57:46.215539 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
5353 09:57:46.222352 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5354 09:57:46.225587 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5355 09:57:46.228712 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5356 09:57:46.235589 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5357 09:57:46.238640 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5358 09:57:46.242048 0 14 28 | B1->B0 | 3434 3030 | 1 0 | (1 1) (1 0)
5359 09:57:46.248844 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5360 09:57:46.251927 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 09:57:46.255596 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 09:57:46.261937 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5363 09:57:46.265193 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5364 09:57:46.269208 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5365 09:57:46.275520 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5366 09:57:46.278763 0 15 28 | B1->B0 | 2525 3636 | 0 0 | (0 0) (0 0)
5367 09:57:46.281830 1 0 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5368 09:57:46.288561 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 09:57:46.291907 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 09:57:46.295468 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 09:57:46.302125 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 09:57:46.305497 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 09:57:46.308521 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5374 09:57:46.315111 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5375 09:57:46.318173 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 09:57:46.321836 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 09:57:46.328938 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 09:57:46.331540 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 09:57:46.334857 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 09:57:46.341961 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 09:57:46.344796 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 09:57:46.348128 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 09:57:46.354763 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 09:57:46.358201 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 09:57:46.361651 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 09:57:46.365003 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 09:57:46.371251 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 09:57:46.374583 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 09:57:46.378291 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 09:57:46.384444 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5391 09:57:46.388118 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5392 09:57:46.391406 Total UI for P1: 0, mck2ui 16
5393 09:57:46.394652 best dqsien dly found for B0: ( 1, 2, 28)
5394 09:57:46.397873 Total UI for P1: 0, mck2ui 16
5395 09:57:46.401047 best dqsien dly found for B1: ( 1, 2, 30)
5396 09:57:46.404801 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5397 09:57:46.407892 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5398 09:57:46.408015
5399 09:57:46.411475 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5400 09:57:46.414410 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5401 09:57:46.417868 [Gating] SW calibration Done
5402 09:57:46.418002 ==
5403 09:57:46.421266 Dram Type= 6, Freq= 0, CH_0, rank 1
5404 09:57:46.428038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5405 09:57:46.428193 ==
5406 09:57:46.428316 RX Vref Scan: 0
5407 09:57:46.428451
5408 09:57:46.431563 RX Vref 0 -> 0, step: 1
5409 09:57:46.431679
5410 09:57:46.434445 RX Delay -80 -> 252, step: 8
5411 09:57:46.437876 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5412 09:57:46.440938 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5413 09:57:46.444937 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5414 09:57:46.447547 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5415 09:57:46.454592 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5416 09:57:46.457615 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5417 09:57:46.461377 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5418 09:57:46.464685 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5419 09:57:46.467700 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5420 09:57:46.470875 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5421 09:57:46.477735 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5422 09:57:46.481392 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5423 09:57:46.484465 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5424 09:57:46.487650 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5425 09:57:46.494175 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5426 09:57:46.497312 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5427 09:57:46.497456 ==
5428 09:57:46.500900 Dram Type= 6, Freq= 0, CH_0, rank 1
5429 09:57:46.504696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5430 09:57:46.504840 ==
5431 09:57:46.504940 DQS Delay:
5432 09:57:46.507652 DQS0 = 0, DQS1 = 0
5433 09:57:46.507764 DQM Delay:
5434 09:57:46.510700 DQM0 = 91, DQM1 = 82
5435 09:57:46.510816 DQ Delay:
5436 09:57:46.514547 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5437 09:57:46.517773 DQ4 =91, DQ5 =79, DQ6 =103, DQ7 =103
5438 09:57:46.520930 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5439 09:57:46.524478 DQ12 =91, DQ13 =87, DQ14 =91, DQ15 =87
5440 09:57:46.524600
5441 09:57:46.524688
5442 09:57:46.524760 ==
5443 09:57:46.527818 Dram Type= 6, Freq= 0, CH_0, rank 1
5444 09:57:46.530926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5445 09:57:46.534785 ==
5446 09:57:46.534938
5447 09:57:46.535046
5448 09:57:46.535145 TX Vref Scan disable
5449 09:57:46.537490 == TX Byte 0 ==
5450 09:57:46.540819 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5451 09:57:46.544082 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5452 09:57:46.547427 == TX Byte 1 ==
5453 09:57:46.550526 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5454 09:57:46.553904 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5455 09:57:46.557747 ==
5456 09:57:46.560614 Dram Type= 6, Freq= 0, CH_0, rank 1
5457 09:57:46.564160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5458 09:57:46.564303 ==
5459 09:57:46.564451
5460 09:57:46.564544
5461 09:57:46.567272 TX Vref Scan disable
5462 09:57:46.567366 == TX Byte 0 ==
5463 09:57:46.573921 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5464 09:57:46.577129 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5465 09:57:46.577306 == TX Byte 1 ==
5466 09:57:46.583932 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5467 09:57:46.587196 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5468 09:57:46.587339
5469 09:57:46.587450 [DATLAT]
5470 09:57:46.590428 Freq=933, CH0 RK1
5471 09:57:46.590556
5472 09:57:46.590652 DATLAT Default: 0xb
5473 09:57:46.594090 0, 0xFFFF, sum = 0
5474 09:57:46.594225 1, 0xFFFF, sum = 0
5475 09:57:46.597427 2, 0xFFFF, sum = 0
5476 09:57:46.597562 3, 0xFFFF, sum = 0
5477 09:57:46.600409 4, 0xFFFF, sum = 0
5478 09:57:46.600551 5, 0xFFFF, sum = 0
5479 09:57:46.603907 6, 0xFFFF, sum = 0
5480 09:57:46.604040 7, 0xFFFF, sum = 0
5481 09:57:46.607246 8, 0xFFFF, sum = 0
5482 09:57:46.610258 9, 0xFFFF, sum = 0
5483 09:57:46.610388 10, 0x0, sum = 1
5484 09:57:46.610491 11, 0x0, sum = 2
5485 09:57:46.614011 12, 0x0, sum = 3
5486 09:57:46.614151 13, 0x0, sum = 4
5487 09:57:46.617180 best_step = 11
5488 09:57:46.617313
5489 09:57:46.617420 ==
5490 09:57:46.620375 Dram Type= 6, Freq= 0, CH_0, rank 1
5491 09:57:46.623473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5492 09:57:46.623568 ==
5493 09:57:46.626844 RX Vref Scan: 0
5494 09:57:46.626963
5495 09:57:46.627070 RX Vref 0 -> 0, step: 1
5496 09:57:46.627172
5497 09:57:46.630402 RX Delay -69 -> 252, step: 4
5498 09:57:46.637847 iDelay=199, Bit 0, Center 88 (-5 ~ 182) 188
5499 09:57:46.640924 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5500 09:57:46.643987 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5501 09:57:46.647803 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5502 09:57:46.650577 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5503 09:57:46.657319 iDelay=199, Bit 5, Center 82 (-9 ~ 174) 184
5504 09:57:46.660868 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5505 09:57:46.663962 iDelay=199, Bit 7, Center 106 (15 ~ 198) 184
5506 09:57:46.667330 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5507 09:57:46.670971 iDelay=199, Bit 9, Center 68 (-21 ~ 158) 180
5508 09:57:46.677160 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5509 09:57:46.680483 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5510 09:57:46.684047 iDelay=199, Bit 12, Center 90 (-5 ~ 186) 192
5511 09:57:46.687604 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5512 09:57:46.690694 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5513 09:57:46.693612 iDelay=199, Bit 15, Center 90 (-1 ~ 182) 184
5514 09:57:46.697275 ==
5515 09:57:46.700461 Dram Type= 6, Freq= 0, CH_0, rank 1
5516 09:57:46.703607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5517 09:57:46.703738 ==
5518 09:57:46.703845 DQS Delay:
5519 09:57:46.706871 DQS0 = 0, DQS1 = 0
5520 09:57:46.706999 DQM Delay:
5521 09:57:46.710309 DQM0 = 92, DQM1 = 84
5522 09:57:46.710434 DQ Delay:
5523 09:57:46.713478 DQ0 =88, DQ1 =94, DQ2 =88, DQ3 =88
5524 09:57:46.717454 DQ4 =90, DQ5 =82, DQ6 =104, DQ7 =106
5525 09:57:46.720269 DQ8 =76, DQ9 =68, DQ10 =86, DQ11 =76
5526 09:57:46.723735 DQ12 =90, DQ13 =92, DQ14 =94, DQ15 =90
5527 09:57:46.723891
5528 09:57:46.723997
5529 09:57:46.730425 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f11, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 407 ps
5530 09:57:46.733455 CH0 RK1: MR19=505, MR18=2F11
5531 09:57:46.740636 CH0_RK1: MR19=0x505, MR18=0x2F11, DQSOSC=407, MR23=63, INC=65, DEC=43
5532 09:57:46.743608 [RxdqsGatingPostProcess] freq 933
5533 09:57:46.750384 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5534 09:57:46.753426 best DQS0 dly(2T, 0.5T) = (0, 11)
5535 09:57:46.756819 best DQS1 dly(2T, 0.5T) = (0, 11)
5536 09:57:46.756967 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5537 09:57:46.759811 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5538 09:57:46.763324 best DQS0 dly(2T, 0.5T) = (0, 10)
5539 09:57:46.766461 best DQS1 dly(2T, 0.5T) = (0, 10)
5540 09:57:46.769995 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5541 09:57:46.773242 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5542 09:57:46.776557 Pre-setting of DQS Precalculation
5543 09:57:46.783075 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5544 09:57:46.783254 ==
5545 09:57:46.786361 Dram Type= 6, Freq= 0, CH_1, rank 0
5546 09:57:46.789639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5547 09:57:46.789795 ==
5548 09:57:46.796343 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5549 09:57:46.799625 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5550 09:57:46.804084 [CA 0] Center 37 (7~67) winsize 61
5551 09:57:46.807191 [CA 1] Center 37 (7~67) winsize 61
5552 09:57:46.810430 [CA 2] Center 35 (6~64) winsize 59
5553 09:57:46.813810 [CA 3] Center 34 (5~64) winsize 60
5554 09:57:46.817521 [CA 4] Center 34 (5~64) winsize 60
5555 09:57:46.820323 [CA 5] Center 33 (3~64) winsize 62
5556 09:57:46.820463
5557 09:57:46.823816 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5558 09:57:46.823951
5559 09:57:46.827256 [CATrainingPosCal] consider 1 rank data
5560 09:57:46.830630 u2DelayCellTimex100 = 270/100 ps
5561 09:57:46.833694 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5562 09:57:46.840488 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5563 09:57:46.844054 CA2 delay=35 (6~64),Diff = 2 PI (12 cell)
5564 09:57:46.847412 CA3 delay=34 (5~64),Diff = 1 PI (6 cell)
5565 09:57:46.851075 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5566 09:57:46.854286 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5567 09:57:46.854429
5568 09:57:46.856878 CA PerBit enable=1, Macro0, CA PI delay=33
5569 09:57:46.857016
5570 09:57:46.860431 [CBTSetCACLKResult] CA Dly = 33
5571 09:57:46.863398 CS Dly: 6 (0~37)
5572 09:57:46.863522 ==
5573 09:57:46.867102 Dram Type= 6, Freq= 0, CH_1, rank 1
5574 09:57:46.870465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5575 09:57:46.870618 ==
5576 09:57:46.876801 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5577 09:57:46.879942 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5578 09:57:46.884216 [CA 0] Center 37 (8~67) winsize 60
5579 09:57:46.887557 [CA 1] Center 37 (7~68) winsize 62
5580 09:57:46.891163 [CA 2] Center 35 (6~65) winsize 60
5581 09:57:46.893798 [CA 3] Center 34 (4~64) winsize 61
5582 09:57:46.897195 [CA 4] Center 34 (5~64) winsize 60
5583 09:57:46.900717 [CA 5] Center 34 (4~64) winsize 61
5584 09:57:46.900863
5585 09:57:46.903760 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5586 09:57:46.903886
5587 09:57:46.907169 [CATrainingPosCal] consider 2 rank data
5588 09:57:46.910904 u2DelayCellTimex100 = 270/100 ps
5589 09:57:46.914045 CA0 delay=37 (8~67),Diff = 3 PI (18 cell)
5590 09:57:46.917403 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5591 09:57:46.924142 CA2 delay=35 (6~64),Diff = 1 PI (6 cell)
5592 09:57:46.927461 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5593 09:57:46.930534 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5594 09:57:46.934257 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5595 09:57:46.934420
5596 09:57:46.937301 CA PerBit enable=1, Macro0, CA PI delay=34
5597 09:57:46.937439
5598 09:57:46.940628 [CBTSetCACLKResult] CA Dly = 34
5599 09:57:46.940760 CS Dly: 6 (0~38)
5600 09:57:46.943836
5601 09:57:46.947068 ----->DramcWriteLeveling(PI) begin...
5602 09:57:46.947204 ==
5603 09:57:46.950318 Dram Type= 6, Freq= 0, CH_1, rank 0
5604 09:57:46.953529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5605 09:57:46.953639 ==
5606 09:57:46.957052 Write leveling (Byte 0): 28 => 28
5607 09:57:46.960259 Write leveling (Byte 1): 30 => 30
5608 09:57:46.963984 DramcWriteLeveling(PI) end<-----
5609 09:57:46.964123
5610 09:57:46.964238 ==
5611 09:57:46.966855 Dram Type= 6, Freq= 0, CH_1, rank 0
5612 09:57:46.970041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5613 09:57:46.970173 ==
5614 09:57:46.973945 [Gating] SW mode calibration
5615 09:57:46.980143 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5616 09:57:46.987316 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5617 09:57:46.990392 0 14 0 | B1->B0 | 3333 3333 | 1 1 | (1 1) (0 0)
5618 09:57:46.993462 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5619 09:57:47.000467 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5620 09:57:47.003416 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5621 09:57:47.006943 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5622 09:57:47.013473 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5623 09:57:47.017000 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5624 09:57:47.020422 0 14 28 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (1 0)
5625 09:57:47.023530 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5626 09:57:47.030319 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5627 09:57:47.033441 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5628 09:57:47.036544 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5629 09:57:47.043156 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5630 09:57:47.046842 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5631 09:57:47.050071 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5632 09:57:47.056904 0 15 28 | B1->B0 | 3636 3434 | 0 0 | (0 0) (0 0)
5633 09:57:47.060112 1 0 0 | B1->B0 | 4545 4545 | 0 0 | (0 0) (0 0)
5634 09:57:47.063350 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5635 09:57:47.069691 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 09:57:47.073233 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5637 09:57:47.076371 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 09:57:47.083418 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 09:57:47.087150 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 09:57:47.089591 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5641 09:57:47.096355 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5642 09:57:47.099510 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 09:57:47.103181 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 09:57:47.109892 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 09:57:47.112932 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 09:57:47.116619 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 09:57:47.122922 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 09:57:47.126156 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 09:57:47.129831 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 09:57:47.136363 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 09:57:47.139552 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 09:57:47.142622 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 09:57:47.149241 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 09:57:47.152704 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 09:57:47.156211 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 09:57:47.162716 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5657 09:57:47.166114 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5658 09:57:47.169284 Total UI for P1: 0, mck2ui 16
5659 09:57:47.172553 best dqsien dly found for B0: ( 1, 2, 28)
5660 09:57:47.176337 Total UI for P1: 0, mck2ui 16
5661 09:57:47.179606 best dqsien dly found for B1: ( 1, 2, 28)
5662 09:57:47.182705 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5663 09:57:47.185800 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5664 09:57:47.185928
5665 09:57:47.189809 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5666 09:57:47.192479 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5667 09:57:47.195771 [Gating] SW calibration Done
5668 09:57:47.195901 ==
5669 09:57:47.199186 Dram Type= 6, Freq= 0, CH_1, rank 0
5670 09:57:47.202613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5671 09:57:47.202748 ==
5672 09:57:47.205776 RX Vref Scan: 0
5673 09:57:47.205886
5674 09:57:47.209114 RX Vref 0 -> 0, step: 1
5675 09:57:47.209212
5676 09:57:47.209279 RX Delay -80 -> 252, step: 8
5677 09:57:47.216110 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5678 09:57:47.219419 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5679 09:57:47.222500 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5680 09:57:47.225845 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5681 09:57:47.229254 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5682 09:57:47.232505 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5683 09:57:47.239113 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5684 09:57:47.242701 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5685 09:57:47.246022 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5686 09:57:47.249216 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5687 09:57:47.252454 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5688 09:57:47.258736 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5689 09:57:47.262286 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5690 09:57:47.265494 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5691 09:57:47.269205 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5692 09:57:47.272291 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5693 09:57:47.275539 ==
5694 09:57:47.278760 Dram Type= 6, Freq= 0, CH_1, rank 0
5695 09:57:47.282159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5696 09:57:47.282290 ==
5697 09:57:47.282393 DQS Delay:
5698 09:57:47.285858 DQS0 = 0, DQS1 = 0
5699 09:57:47.285958 DQM Delay:
5700 09:57:47.288881 DQM0 = 94, DQM1 = 86
5701 09:57:47.289009 DQ Delay:
5702 09:57:47.292104 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5703 09:57:47.295618 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =91
5704 09:57:47.299208 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =83
5705 09:57:47.302255 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5706 09:57:47.302364
5707 09:57:47.302452
5708 09:57:47.302562 ==
5709 09:57:47.305380 Dram Type= 6, Freq= 0, CH_1, rank 0
5710 09:57:47.308871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5711 09:57:47.309001 ==
5712 09:57:47.309101
5713 09:57:47.309191
5714 09:57:47.312450 TX Vref Scan disable
5715 09:57:47.315586 == TX Byte 0 ==
5716 09:57:47.319113 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5717 09:57:47.322208 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5718 09:57:47.325307 == TX Byte 1 ==
5719 09:57:47.329174 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5720 09:57:47.331767 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5721 09:57:47.331911 ==
5722 09:57:47.335322 Dram Type= 6, Freq= 0, CH_1, rank 0
5723 09:57:47.342174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5724 09:57:47.342343 ==
5725 09:57:47.342449
5726 09:57:47.342551
5727 09:57:47.342649 TX Vref Scan disable
5728 09:57:47.345710 == TX Byte 0 ==
5729 09:57:47.348895 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5730 09:57:47.352249 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5731 09:57:47.356037 == TX Byte 1 ==
5732 09:57:47.359002 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5733 09:57:47.362589 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5734 09:57:47.365610
5735 09:57:47.365720 [DATLAT]
5736 09:57:47.365788 Freq=933, CH1 RK0
5737 09:57:47.365850
5738 09:57:47.368739 DATLAT Default: 0xd
5739 09:57:47.368837 0, 0xFFFF, sum = 0
5740 09:57:47.372437 1, 0xFFFF, sum = 0
5741 09:57:47.372534 2, 0xFFFF, sum = 0
5742 09:57:47.375569 3, 0xFFFF, sum = 0
5743 09:57:47.379066 4, 0xFFFF, sum = 0
5744 09:57:47.379204 5, 0xFFFF, sum = 0
5745 09:57:47.381921 6, 0xFFFF, sum = 0
5746 09:57:47.382024 7, 0xFFFF, sum = 0
5747 09:57:47.385606 8, 0xFFFF, sum = 0
5748 09:57:47.385708 9, 0xFFFF, sum = 0
5749 09:57:47.388933 10, 0x0, sum = 1
5750 09:57:47.389067 11, 0x0, sum = 2
5751 09:57:47.392066 12, 0x0, sum = 3
5752 09:57:47.392211 13, 0x0, sum = 4
5753 09:57:47.392292 best_step = 11
5754 09:57:47.392369
5755 09:57:47.395294 ==
5756 09:57:47.399001 Dram Type= 6, Freq= 0, CH_1, rank 0
5757 09:57:47.401971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5758 09:57:47.402115 ==
5759 09:57:47.402213 RX Vref Scan: 1
5760 09:57:47.402308
5761 09:57:47.405689 RX Vref 0 -> 0, step: 1
5762 09:57:47.405809
5763 09:57:47.408714 RX Delay -69 -> 252, step: 4
5764 09:57:47.408808
5765 09:57:47.411919 Set Vref, RX VrefLevel [Byte0]: 55
5766 09:57:47.415471 [Byte1]: 50
5767 09:57:47.415585
5768 09:57:47.418517 Final RX Vref Byte 0 = 55 to rank0
5769 09:57:47.421841 Final RX Vref Byte 1 = 50 to rank0
5770 09:57:47.425211 Final RX Vref Byte 0 = 55 to rank1
5771 09:57:47.428804 Final RX Vref Byte 1 = 50 to rank1==
5772 09:57:47.431680 Dram Type= 6, Freq= 0, CH_1, rank 0
5773 09:57:47.436134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5774 09:57:47.438297 ==
5775 09:57:47.438423 DQS Delay:
5776 09:57:47.438527 DQS0 = 0, DQS1 = 0
5777 09:57:47.441694 DQM Delay:
5778 09:57:47.441823 DQM0 = 95, DQM1 = 89
5779 09:57:47.444942 DQ Delay:
5780 09:57:47.448377 DQ0 =100, DQ1 =90, DQ2 =84, DQ3 =94
5781 09:57:47.448505 DQ4 =92, DQ5 =106, DQ6 =106, DQ7 =92
5782 09:57:47.454924 DQ8 =78, DQ9 =82, DQ10 =88, DQ11 =82
5783 09:57:47.458114 DQ12 =96, DQ13 =94, DQ14 =98, DQ15 =94
5784 09:57:47.458259
5785 09:57:47.458358
5786 09:57:47.464887 [DQSOSCAuto] RK0, (LSB)MR18= 0x30c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 421 ps
5787 09:57:47.468120 CH1 RK0: MR19=505, MR18=30C
5788 09:57:47.474583 CH1_RK0: MR19=0x505, MR18=0x30C, DQSOSC=418, MR23=63, INC=62, DEC=41
5789 09:57:47.474766
5790 09:57:47.478235 ----->DramcWriteLeveling(PI) begin...
5791 09:57:47.478363 ==
5792 09:57:47.481315 Dram Type= 6, Freq= 0, CH_1, rank 1
5793 09:57:47.484548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5794 09:57:47.484670 ==
5795 09:57:47.488338 Write leveling (Byte 0): 23 => 23
5796 09:57:47.491112 Write leveling (Byte 1): 27 => 27
5797 09:57:47.494884 DramcWriteLeveling(PI) end<-----
5798 09:57:47.495034
5799 09:57:47.495140 ==
5800 09:57:47.497766 Dram Type= 6, Freq= 0, CH_1, rank 1
5801 09:57:47.501112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5802 09:57:47.501272 ==
5803 09:57:47.504547 [Gating] SW mode calibration
5804 09:57:47.511052 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5805 09:57:47.517577 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5806 09:57:47.520805 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5807 09:57:47.527514 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5808 09:57:47.531130 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5809 09:57:47.534610 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5810 09:57:47.537590 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5811 09:57:47.544148 0 14 20 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5812 09:57:47.547590 0 14 24 | B1->B0 | 3232 2d2d | 1 0 | (1 0) (1 1)
5813 09:57:47.553941 0 14 28 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5814 09:57:47.557247 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5815 09:57:47.560411 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5816 09:57:47.567006 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5817 09:57:47.570546 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5818 09:57:47.574003 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5819 09:57:47.580105 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5820 09:57:47.583501 0 15 24 | B1->B0 | 2424 2929 | 1 1 | (1 1) (1 1)
5821 09:57:47.587614 0 15 28 | B1->B0 | 3b3a 4242 | 1 0 | (0 0) (0 0)
5822 09:57:47.590380 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 09:57:47.597025 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5824 09:57:47.600375 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 09:57:47.603468 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5826 09:57:47.610418 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5827 09:57:47.613546 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5828 09:57:47.616941 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5829 09:57:47.623344 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5830 09:57:47.627263 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 09:57:47.630109 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 09:57:47.636626 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 09:57:47.639855 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 09:57:47.643178 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 09:57:47.649680 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 09:57:47.653306 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 09:57:47.656296 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 09:57:47.663184 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 09:57:47.666553 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 09:57:47.669687 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 09:57:47.676265 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 09:57:47.679483 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 09:57:47.682860 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 09:57:47.689805 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 09:57:47.692876 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5846 09:57:47.696216 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5847 09:57:47.699818 Total UI for P1: 0, mck2ui 16
5848 09:57:47.702816 best dqsien dly found for B0: ( 1, 2, 28)
5849 09:57:47.706064 Total UI for P1: 0, mck2ui 16
5850 09:57:47.709233 best dqsien dly found for B1: ( 1, 2, 28)
5851 09:57:47.712734 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5852 09:57:47.716586 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5853 09:57:47.716745
5854 09:57:47.722631 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5855 09:57:47.725928 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5856 09:57:47.729090 [Gating] SW calibration Done
5857 09:57:47.729320 ==
5858 09:57:47.732750 Dram Type= 6, Freq= 0, CH_1, rank 1
5859 09:57:47.736027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5860 09:57:47.736171 ==
5861 09:57:47.736286 RX Vref Scan: 0
5862 09:57:47.736381
5863 09:57:47.739021 RX Vref 0 -> 0, step: 1
5864 09:57:47.739144
5865 09:57:47.742400 RX Delay -80 -> 252, step: 8
5866 09:57:47.745504 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5867 09:57:47.749039 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5868 09:57:47.755565 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5869 09:57:47.758741 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5870 09:57:47.762440 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5871 09:57:47.765504 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5872 09:57:47.768743 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5873 09:57:47.772421 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5874 09:57:47.779163 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5875 09:57:47.781884 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5876 09:57:47.785679 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5877 09:57:47.788791 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5878 09:57:47.792067 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5879 09:57:47.798375 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5880 09:57:47.801707 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5881 09:57:47.805043 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5882 09:57:47.805200 ==
5883 09:57:47.808755 Dram Type= 6, Freq= 0, CH_1, rank 1
5884 09:57:47.811879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5885 09:57:47.812021 ==
5886 09:57:47.815494 DQS Delay:
5887 09:57:47.815626 DQS0 = 0, DQS1 = 0
5888 09:57:47.815728 DQM Delay:
5889 09:57:47.818579 DQM0 = 94, DQM1 = 89
5890 09:57:47.818718 DQ Delay:
5891 09:57:47.822031 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5892 09:57:47.824884 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5893 09:57:47.828183 DQ8 =75, DQ9 =79, DQ10 =95, DQ11 =83
5894 09:57:47.831468 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =95
5895 09:57:47.831610
5896 09:57:47.831708
5897 09:57:47.835066 ==
5898 09:57:47.835218 Dram Type= 6, Freq= 0, CH_1, rank 1
5899 09:57:47.841541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5900 09:57:47.841709 ==
5901 09:57:47.841811
5902 09:57:47.841915
5903 09:57:47.845083 TX Vref Scan disable
5904 09:57:47.845210 == TX Byte 0 ==
5905 09:57:47.851123 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5906 09:57:47.854784 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5907 09:57:47.854935 == TX Byte 1 ==
5908 09:57:47.861587 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5909 09:57:47.864456 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5910 09:57:47.864597 ==
5911 09:57:47.867594 Dram Type= 6, Freq= 0, CH_1, rank 1
5912 09:57:47.870954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5913 09:57:47.871094 ==
5914 09:57:47.871195
5915 09:57:47.871288
5916 09:57:47.874479 TX Vref Scan disable
5917 09:57:47.877687 == TX Byte 0 ==
5918 09:57:47.880889 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5919 09:57:47.884347 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5920 09:57:47.887594 == TX Byte 1 ==
5921 09:57:47.891192 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5922 09:57:47.894385 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5923 09:57:47.894535
5924 09:57:47.897507 [DATLAT]
5925 09:57:47.897646 Freq=933, CH1 RK1
5926 09:57:47.897750
5927 09:57:47.900879 DATLAT Default: 0xb
5928 09:57:47.901016 0, 0xFFFF, sum = 0
5929 09:57:47.904937 1, 0xFFFF, sum = 0
5930 09:57:47.905090 2, 0xFFFF, sum = 0
5931 09:57:47.907959 3, 0xFFFF, sum = 0
5932 09:57:47.908092 4, 0xFFFF, sum = 0
5933 09:57:47.911057 5, 0xFFFF, sum = 0
5934 09:57:47.911189 6, 0xFFFF, sum = 0
5935 09:57:47.914301 7, 0xFFFF, sum = 0
5936 09:57:47.914429 8, 0xFFFF, sum = 0
5937 09:57:47.917938 9, 0xFFFF, sum = 0
5938 09:57:47.918074 10, 0x0, sum = 1
5939 09:57:47.921072 11, 0x0, sum = 2
5940 09:57:47.921196 12, 0x0, sum = 3
5941 09:57:47.924220 13, 0x0, sum = 4
5942 09:57:47.924351 best_step = 11
5943 09:57:47.924449
5944 09:57:47.924540 ==
5945 09:57:47.927461 Dram Type= 6, Freq= 0, CH_1, rank 1
5946 09:57:47.934115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5947 09:57:47.934290 ==
5948 09:57:47.934398 RX Vref Scan: 0
5949 09:57:47.934493
5950 09:57:47.937467 RX Vref 0 -> 0, step: 1
5951 09:57:47.937606
5952 09:57:47.941032 RX Delay -69 -> 252, step: 4
5953 09:57:47.944008 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5954 09:57:47.947342 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5955 09:57:47.954121 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5956 09:57:47.957186 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5957 09:57:47.960489 iDelay=203, Bit 4, Center 90 (-9 ~ 190) 200
5958 09:57:47.964100 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5959 09:57:47.967394 iDelay=203, Bit 6, Center 102 (3 ~ 202) 200
5960 09:57:47.970440 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5961 09:57:47.977188 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5962 09:57:47.980567 iDelay=203, Bit 9, Center 82 (-13 ~ 178) 192
5963 09:57:47.984048 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5964 09:57:47.987334 iDelay=203, Bit 11, Center 82 (-13 ~ 178) 192
5965 09:57:47.993747 iDelay=203, Bit 12, Center 100 (11 ~ 190) 180
5966 09:57:47.997063 iDelay=203, Bit 13, Center 96 (3 ~ 190) 188
5967 09:57:48.000385 iDelay=203, Bit 14, Center 100 (11 ~ 190) 180
5968 09:57:48.003890 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
5969 09:57:48.004023 ==
5970 09:57:48.007415 Dram Type= 6, Freq= 0, CH_1, rank 1
5971 09:57:48.010641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5972 09:57:48.010771 ==
5973 09:57:48.013722 DQS Delay:
5974 09:57:48.013843 DQS0 = 0, DQS1 = 0
5975 09:57:48.017314 DQM Delay:
5976 09:57:48.017429 DQM0 = 91, DQM1 = 90
5977 09:57:48.017521 DQ Delay:
5978 09:57:48.020333 DQ0 =96, DQ1 =86, DQ2 =82, DQ3 =88
5979 09:57:48.023710 DQ4 =90, DQ5 =102, DQ6 =102, DQ7 =88
5980 09:57:48.026896 DQ8 =78, DQ9 =82, DQ10 =92, DQ11 =82
5981 09:57:48.033614 DQ12 =100, DQ13 =96, DQ14 =100, DQ15 =96
5982 09:57:48.033792
5983 09:57:48.033937
5984 09:57:48.040191 [DQSOSCAuto] RK1, (LSB)MR18= 0x1225, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 416 ps
5985 09:57:48.043650 CH1 RK1: MR19=505, MR18=1225
5986 09:57:48.050351 CH1_RK1: MR19=0x505, MR18=0x1225, DQSOSC=410, MR23=63, INC=64, DEC=42
5987 09:57:48.053271 [RxdqsGatingPostProcess] freq 933
5988 09:57:48.056756 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5989 09:57:48.059772 best DQS0 dly(2T, 0.5T) = (0, 10)
5990 09:57:48.063168 best DQS1 dly(2T, 0.5T) = (0, 10)
5991 09:57:48.066866 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5992 09:57:48.069896 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5993 09:57:48.073592 best DQS0 dly(2T, 0.5T) = (0, 10)
5994 09:57:48.076692 best DQS1 dly(2T, 0.5T) = (0, 10)
5995 09:57:48.079974 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5996 09:57:48.083049 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5997 09:57:48.086618 Pre-setting of DQS Precalculation
5998 09:57:48.089836 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5999 09:57:48.096580 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6000 09:57:48.106404 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6001 09:57:48.106581
6002 09:57:48.106674
6003 09:57:48.109698 [Calibration Summary] 1866 Mbps
6004 09:57:48.109814 CH 0, Rank 0
6005 09:57:48.113107 SW Impedance : PASS
6006 09:57:48.113223 DUTY Scan : NO K
6007 09:57:48.116481 ZQ Calibration : PASS
6008 09:57:48.119671 Jitter Meter : NO K
6009 09:57:48.119799 CBT Training : PASS
6010 09:57:48.122841 Write leveling : PASS
6011 09:57:48.126236 RX DQS gating : PASS
6012 09:57:48.126360 RX DQ/DQS(RDDQC) : PASS
6013 09:57:48.129411 TX DQ/DQS : PASS
6014 09:57:48.129581 RX DATLAT : PASS
6015 09:57:48.132983 RX DQ/DQS(Engine): PASS
6016 09:57:48.136349 TX OE : NO K
6017 09:57:48.136480 All Pass.
6018 09:57:48.136577
6019 09:57:48.136669 CH 0, Rank 1
6020 09:57:48.139814 SW Impedance : PASS
6021 09:57:48.143085 DUTY Scan : NO K
6022 09:57:48.143229 ZQ Calibration : PASS
6023 09:57:48.145817 Jitter Meter : NO K
6024 09:57:48.149323 CBT Training : PASS
6025 09:57:48.149442 Write leveling : PASS
6026 09:57:48.152708 RX DQS gating : PASS
6027 09:57:48.155950 RX DQ/DQS(RDDQC) : PASS
6028 09:57:48.156094 TX DQ/DQS : PASS
6029 09:57:48.159295 RX DATLAT : PASS
6030 09:57:48.162753 RX DQ/DQS(Engine): PASS
6031 09:57:48.162873 TX OE : NO K
6032 09:57:48.166376 All Pass.
6033 09:57:48.166529
6034 09:57:48.166635 CH 1, Rank 0
6035 09:57:48.169493 SW Impedance : PASS
6036 09:57:48.169652 DUTY Scan : NO K
6037 09:57:48.173037 ZQ Calibration : PASS
6038 09:57:48.176036 Jitter Meter : NO K
6039 09:57:48.176177 CBT Training : PASS
6040 09:57:48.179104 Write leveling : PASS
6041 09:57:48.182654 RX DQS gating : PASS
6042 09:57:48.182809 RX DQ/DQS(RDDQC) : PASS
6043 09:57:48.186031 TX DQ/DQS : PASS
6044 09:57:48.186200 RX DATLAT : PASS
6045 09:57:48.189044 RX DQ/DQS(Engine): PASS
6046 09:57:48.192894 TX OE : NO K
6047 09:57:48.193037 All Pass.
6048 09:57:48.193138
6049 09:57:48.193229 CH 1, Rank 1
6050 09:57:48.195985 SW Impedance : PASS
6051 09:57:48.198863 DUTY Scan : NO K
6052 09:57:48.198984 ZQ Calibration : PASS
6053 09:57:48.202630 Jitter Meter : NO K
6054 09:57:48.205730 CBT Training : PASS
6055 09:57:48.205856 Write leveling : PASS
6056 09:57:48.208879 RX DQS gating : PASS
6057 09:57:48.212393 RX DQ/DQS(RDDQC) : PASS
6058 09:57:48.212523 TX DQ/DQS : PASS
6059 09:57:48.215724 RX DATLAT : PASS
6060 09:57:48.219175 RX DQ/DQS(Engine): PASS
6061 09:57:48.219314 TX OE : NO K
6062 09:57:48.222578 All Pass.
6063 09:57:48.222699
6064 09:57:48.222793 DramC Write-DBI off
6065 09:57:48.225424 PER_BANK_REFRESH: Hybrid Mode
6066 09:57:48.225540 TX_TRACKING: ON
6067 09:57:48.235380 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6068 09:57:48.239248 [FAST_K] Save calibration result to emmc
6069 09:57:48.242553 dramc_set_vcore_voltage set vcore to 650000
6070 09:57:48.245239 Read voltage for 400, 6
6071 09:57:48.245376 Vio18 = 0
6072 09:57:48.248624 Vcore = 650000
6073 09:57:48.248754 Vdram = 0
6074 09:57:48.248864 Vddq = 0
6075 09:57:48.252271 Vmddr = 0
6076 09:57:48.255687 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6077 09:57:48.261964 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6078 09:57:48.262132 MEM_TYPE=3, freq_sel=20
6079 09:57:48.265222 sv_algorithm_assistance_LP4_800
6080 09:57:48.268644 ============ PULL DRAM RESETB DOWN ============
6081 09:57:48.275223 ========== PULL DRAM RESETB DOWN end =========
6082 09:57:48.278764 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6083 09:57:48.282255 ===================================
6084 09:57:48.285119 LPDDR4 DRAM CONFIGURATION
6085 09:57:48.288654 ===================================
6086 09:57:48.288780 EX_ROW_EN[0] = 0x0
6087 09:57:48.291794 EX_ROW_EN[1] = 0x0
6088 09:57:48.295401 LP4Y_EN = 0x0
6089 09:57:48.295491 WORK_FSP = 0x0
6090 09:57:48.298815 WL = 0x2
6091 09:57:48.298935 RL = 0x2
6092 09:57:48.301791 BL = 0x2
6093 09:57:48.301913 RPST = 0x0
6094 09:57:48.305262 RD_PRE = 0x0
6095 09:57:48.305378 WR_PRE = 0x1
6096 09:57:48.308565 WR_PST = 0x0
6097 09:57:48.308689 DBI_WR = 0x0
6098 09:57:48.311945 DBI_RD = 0x0
6099 09:57:48.312063 OTF = 0x1
6100 09:57:48.315262 ===================================
6101 09:57:48.318710 ===================================
6102 09:57:48.321800 ANA top config
6103 09:57:48.325462 ===================================
6104 09:57:48.325597 DLL_ASYNC_EN = 0
6105 09:57:48.328354 ALL_SLAVE_EN = 1
6106 09:57:48.331667 NEW_RANK_MODE = 1
6107 09:57:48.335366 DLL_IDLE_MODE = 1
6108 09:57:48.335502 LP45_APHY_COMB_EN = 1
6109 09:57:48.338326 TX_ODT_DIS = 1
6110 09:57:48.341918 NEW_8X_MODE = 1
6111 09:57:48.344891 ===================================
6112 09:57:48.348404 ===================================
6113 09:57:48.351621 data_rate = 800
6114 09:57:48.355047 CKR = 1
6115 09:57:48.358541 DQ_P2S_RATIO = 4
6116 09:57:48.362226 ===================================
6117 09:57:48.362369 CA_P2S_RATIO = 4
6118 09:57:48.365132 DQ_CA_OPEN = 0
6119 09:57:48.368304 DQ_SEMI_OPEN = 1
6120 09:57:48.371406 CA_SEMI_OPEN = 1
6121 09:57:48.374847 CA_FULL_RATE = 0
6122 09:57:48.378847 DQ_CKDIV4_EN = 0
6123 09:57:48.379171 CA_CKDIV4_EN = 1
6124 09:57:48.381415 CA_PREDIV_EN = 0
6125 09:57:48.384978 PH8_DLY = 0
6126 09:57:48.388446 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6127 09:57:48.391480 DQ_AAMCK_DIV = 0
6128 09:57:48.394726 CA_AAMCK_DIV = 0
6129 09:57:48.394852 CA_ADMCK_DIV = 4
6130 09:57:48.397999 DQ_TRACK_CA_EN = 0
6131 09:57:48.401255 CA_PICK = 800
6132 09:57:48.404736 CA_MCKIO = 400
6133 09:57:48.407831 MCKIO_SEMI = 400
6134 09:57:48.411380 PLL_FREQ = 3016
6135 09:57:48.414582 DQ_UI_PI_RATIO = 32
6136 09:57:48.417707 CA_UI_PI_RATIO = 32
6137 09:57:48.421382 ===================================
6138 09:57:48.424716 ===================================
6139 09:57:48.424904 memory_type:LPDDR4
6140 09:57:48.428430 GP_NUM : 10
6141 09:57:48.428617 SRAM_EN : 1
6142 09:57:48.430899 MD32_EN : 0
6143 09:57:48.434433 ===================================
6144 09:57:48.437571 [ANA_INIT] >>>>>>>>>>>>>>
6145 09:57:48.441525 <<<<<< [CONFIGURE PHASE]: ANA_TX
6146 09:57:48.444525 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6147 09:57:48.447742 ===================================
6148 09:57:48.451344 data_rate = 800,PCW = 0X7400
6149 09:57:48.451523 ===================================
6150 09:57:48.457970 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6151 09:57:48.460878 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6152 09:57:48.474091 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6153 09:57:48.477631 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6154 09:57:48.480762 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6155 09:57:48.484093 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6156 09:57:48.487692 [ANA_INIT] flow start
6157 09:57:48.487811 [ANA_INIT] PLL >>>>>>>>
6158 09:57:48.490562 [ANA_INIT] PLL <<<<<<<<
6159 09:57:48.494456 [ANA_INIT] MIDPI >>>>>>>>
6160 09:57:48.497425 [ANA_INIT] MIDPI <<<<<<<<
6161 09:57:48.497547 [ANA_INIT] DLL >>>>>>>>
6162 09:57:48.501069 [ANA_INIT] flow end
6163 09:57:48.504342 ============ LP4 DIFF to SE enter ============
6164 09:57:48.507633 ============ LP4 DIFF to SE exit ============
6165 09:57:48.510732 [ANA_INIT] <<<<<<<<<<<<<
6166 09:57:48.514189 [Flow] Enable top DCM control >>>>>
6167 09:57:48.517322 [Flow] Enable top DCM control <<<<<
6168 09:57:48.520873 Enable DLL master slave shuffle
6169 09:57:48.527112 ==============================================================
6170 09:57:48.527222 Gating Mode config
6171 09:57:48.533840 ==============================================================
6172 09:57:48.534002 Config description:
6173 09:57:48.544103 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6174 09:57:48.550476 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6175 09:57:48.557202 SELPH_MODE 0: By rank 1: By Phase
6176 09:57:48.560334 ==============================================================
6177 09:57:48.563909 GAT_TRACK_EN = 0
6178 09:57:48.567363 RX_GATING_MODE = 2
6179 09:57:48.570535 RX_GATING_TRACK_MODE = 2
6180 09:57:48.573577 SELPH_MODE = 1
6181 09:57:48.576822 PICG_EARLY_EN = 1
6182 09:57:48.580372 VALID_LAT_VALUE = 1
6183 09:57:48.583731 ==============================================================
6184 09:57:48.590272 Enter into Gating configuration >>>>
6185 09:57:48.593495 Exit from Gating configuration <<<<
6186 09:57:48.593654 Enter into DVFS_PRE_config >>>>>
6187 09:57:48.606449 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6188 09:57:48.610440 Exit from DVFS_PRE_config <<<<<
6189 09:57:48.613085 Enter into PICG configuration >>>>
6190 09:57:48.616633 Exit from PICG configuration <<<<
6191 09:57:48.616807 [RX_INPUT] configuration >>>>>
6192 09:57:48.620129 [RX_INPUT] configuration <<<<<
6193 09:57:48.626367 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6194 09:57:48.629924 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6195 09:57:48.636752 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6196 09:57:48.643107 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6197 09:57:48.649750 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6198 09:57:48.656333 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6199 09:57:48.659903 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6200 09:57:48.663191 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6201 09:57:48.669869 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6202 09:57:48.673546 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6203 09:57:48.676667 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6204 09:57:48.679538 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6205 09:57:48.683204 ===================================
6206 09:57:48.686932 LPDDR4 DRAM CONFIGURATION
6207 09:57:48.689831 ===================================
6208 09:57:48.693258 EX_ROW_EN[0] = 0x0
6209 09:57:48.693566 EX_ROW_EN[1] = 0x0
6210 09:57:48.696477 LP4Y_EN = 0x0
6211 09:57:48.696668 WORK_FSP = 0x0
6212 09:57:48.699504 WL = 0x2
6213 09:57:48.699678 RL = 0x2
6214 09:57:48.702727 BL = 0x2
6215 09:57:48.702912 RPST = 0x0
6216 09:57:48.706669 RD_PRE = 0x0
6217 09:57:48.706850 WR_PRE = 0x1
6218 09:57:48.709850 WR_PST = 0x0
6219 09:57:48.710020 DBI_WR = 0x0
6220 09:57:48.712788 DBI_RD = 0x0
6221 09:57:48.716162 OTF = 0x1
6222 09:57:48.719697 ===================================
6223 09:57:48.722647 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6224 09:57:48.726291 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6225 09:57:48.729363 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6226 09:57:48.732723 ===================================
6227 09:57:48.736048 LPDDR4 DRAM CONFIGURATION
6228 09:57:48.739117 ===================================
6229 09:57:48.743007 EX_ROW_EN[0] = 0x10
6230 09:57:48.743226 EX_ROW_EN[1] = 0x0
6231 09:57:48.746235 LP4Y_EN = 0x0
6232 09:57:48.746422 WORK_FSP = 0x0
6233 09:57:48.749061 WL = 0x2
6234 09:57:48.749242 RL = 0x2
6235 09:57:48.752417 BL = 0x2
6236 09:57:48.752608 RPST = 0x0
6237 09:57:48.755649 RD_PRE = 0x0
6238 09:57:48.755831 WR_PRE = 0x1
6239 09:57:48.759473 WR_PST = 0x0
6240 09:57:48.759658 DBI_WR = 0x0
6241 09:57:48.762581 DBI_RD = 0x0
6242 09:57:48.765819 OTF = 0x1
6243 09:57:48.769146 ===================================
6244 09:57:48.772330 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6245 09:57:48.777346 nWR fixed to 30
6246 09:57:48.780686 [ModeRegInit_LP4] CH0 RK0
6247 09:57:48.780833 [ModeRegInit_LP4] CH0 RK1
6248 09:57:48.784057 [ModeRegInit_LP4] CH1 RK0
6249 09:57:48.787177 [ModeRegInit_LP4] CH1 RK1
6250 09:57:48.787317 match AC timing 19
6251 09:57:48.794065 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6252 09:57:48.797243 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6253 09:57:48.800539 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6254 09:57:48.807360 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6255 09:57:48.810928 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6256 09:57:48.811109 ==
6257 09:57:48.814065 Dram Type= 6, Freq= 0, CH_0, rank 0
6258 09:57:48.817586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6259 09:57:48.817745 ==
6260 09:57:48.823917 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6261 09:57:48.830626 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6262 09:57:48.834073 [CA 0] Center 36 (8~64) winsize 57
6263 09:57:48.837417 [CA 1] Center 36 (8~64) winsize 57
6264 09:57:48.840673 [CA 2] Center 36 (8~64) winsize 57
6265 09:57:48.840904 [CA 3] Center 36 (8~64) winsize 57
6266 09:57:48.844031 [CA 4] Center 36 (8~64) winsize 57
6267 09:57:48.847322 [CA 5] Center 36 (8~64) winsize 57
6268 09:57:48.847523
6269 09:57:48.854085 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6270 09:57:48.854325
6271 09:57:48.857206 [CATrainingPosCal] consider 1 rank data
6272 09:57:48.860938 u2DelayCellTimex100 = 270/100 ps
6273 09:57:48.863694 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 09:57:48.867214 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 09:57:48.870267 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 09:57:48.873647 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 09:57:48.877393 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 09:57:48.880891 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 09:57:48.881098
6280 09:57:48.884036 CA PerBit enable=1, Macro0, CA PI delay=36
6281 09:57:48.884173
6282 09:57:48.887233 [CBTSetCACLKResult] CA Dly = 36
6283 09:57:48.890683 CS Dly: 1 (0~32)
6284 09:57:48.890818 ==
6285 09:57:48.893697 Dram Type= 6, Freq= 0, CH_0, rank 1
6286 09:57:48.897364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6287 09:57:48.897577 ==
6288 09:57:48.903589 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6289 09:57:48.906748 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6290 09:57:48.910533 [CA 0] Center 36 (8~64) winsize 57
6291 09:57:48.913840 [CA 1] Center 36 (8~64) winsize 57
6292 09:57:48.916864 [CA 2] Center 36 (8~64) winsize 57
6293 09:57:48.920033 [CA 3] Center 36 (8~64) winsize 57
6294 09:57:48.923360 [CA 4] Center 36 (8~64) winsize 57
6295 09:57:48.926955 [CA 5] Center 36 (8~64) winsize 57
6296 09:57:48.927130
6297 09:57:48.929951 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6298 09:57:48.930106
6299 09:57:48.933825 [CATrainingPosCal] consider 2 rank data
6300 09:57:48.936950 u2DelayCellTimex100 = 270/100 ps
6301 09:57:48.940539 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 09:57:48.943518 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 09:57:48.946767 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 09:57:48.953406 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 09:57:48.957094 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 09:57:48.960294 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 09:57:48.960441
6308 09:57:48.963267 CA PerBit enable=1, Macro0, CA PI delay=36
6309 09:57:48.963390
6310 09:57:48.967132 [CBTSetCACLKResult] CA Dly = 36
6311 09:57:48.967262 CS Dly: 1 (0~32)
6312 09:57:48.967368
6313 09:57:48.969976 ----->DramcWriteLeveling(PI) begin...
6314 09:57:48.970100 ==
6315 09:57:48.973665 Dram Type= 6, Freq= 0, CH_0, rank 0
6316 09:57:48.980060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6317 09:57:48.980223 ==
6318 09:57:48.983290 Write leveling (Byte 0): 40 => 8
6319 09:57:48.986670 Write leveling (Byte 1): 40 => 8
6320 09:57:48.986829 DramcWriteLeveling(PI) end<-----
6321 09:57:48.989831
6322 09:57:48.989964 ==
6323 09:57:48.993611 Dram Type= 6, Freq= 0, CH_0, rank 0
6324 09:57:48.996655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6325 09:57:48.996788 ==
6326 09:57:49.000075 [Gating] SW mode calibration
6327 09:57:49.006523 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6328 09:57:49.009628 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6329 09:57:49.016820 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6330 09:57:49.020417 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6331 09:57:49.022827 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6332 09:57:49.029320 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6333 09:57:49.032817 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6334 09:57:49.036444 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6335 09:57:49.042803 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6336 09:57:49.045956 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6337 09:57:49.049779 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6338 09:57:49.052564 Total UI for P1: 0, mck2ui 16
6339 09:57:49.055849 best dqsien dly found for B0: ( 0, 14, 24)
6340 09:57:49.059448 Total UI for P1: 0, mck2ui 16
6341 09:57:49.062451 best dqsien dly found for B1: ( 0, 14, 24)
6342 09:57:49.066443 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6343 09:57:49.072416 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6344 09:57:49.072623
6345 09:57:49.075618 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6346 09:57:49.079460 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6347 09:57:49.082724 [Gating] SW calibration Done
6348 09:57:49.082895 ==
6349 09:57:49.085881 Dram Type= 6, Freq= 0, CH_0, rank 0
6350 09:57:49.088886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6351 09:57:49.088986 ==
6352 09:57:49.092269 RX Vref Scan: 0
6353 09:57:49.092405
6354 09:57:49.092502 RX Vref 0 -> 0, step: 1
6355 09:57:49.092606
6356 09:57:49.095732 RX Delay -410 -> 252, step: 16
6357 09:57:49.098679 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6358 09:57:49.105425 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6359 09:57:49.108792 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6360 09:57:49.112261 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6361 09:57:49.118596 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6362 09:57:49.121862 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6363 09:57:49.125319 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6364 09:57:49.128506 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6365 09:57:49.134836 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6366 09:57:49.138416 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6367 09:57:49.141580 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6368 09:57:49.145011 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6369 09:57:49.151889 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6370 09:57:49.154772 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6371 09:57:49.158294 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6372 09:57:49.161812 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6373 09:57:49.164660 ==
6374 09:57:49.164791 Dram Type= 6, Freq= 0, CH_0, rank 0
6375 09:57:49.171660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6376 09:57:49.171820 ==
6377 09:57:49.171939 DQS Delay:
6378 09:57:49.175060 DQS0 = 59, DQS1 = 59
6379 09:57:49.175192 DQM Delay:
6380 09:57:49.178137 DQM0 = 18, DQM1 = 10
6381 09:57:49.178273 DQ Delay:
6382 09:57:49.181810 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6383 09:57:49.184607 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6384 09:57:49.188188 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6385 09:57:49.191685 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6386 09:57:49.191842
6387 09:57:49.191944
6388 09:57:49.192042 ==
6389 09:57:49.195023 Dram Type= 6, Freq= 0, CH_0, rank 0
6390 09:57:49.198230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6391 09:57:49.198368 ==
6392 09:57:49.198471
6393 09:57:49.198566
6394 09:57:49.201382 TX Vref Scan disable
6395 09:57:49.201508 == TX Byte 0 ==
6396 09:57:49.207785 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6397 09:57:49.211620 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6398 09:57:49.211766 == TX Byte 1 ==
6399 09:57:49.218447 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6400 09:57:49.221151 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6401 09:57:49.221299 ==
6402 09:57:49.224698 Dram Type= 6, Freq= 0, CH_0, rank 0
6403 09:57:49.227988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6404 09:57:49.228122 ==
6405 09:57:49.228242
6406 09:57:49.228345
6407 09:57:49.231551 TX Vref Scan disable
6408 09:57:49.231681 == TX Byte 0 ==
6409 09:57:49.237988 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6410 09:57:49.241412 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6411 09:57:49.241519 == TX Byte 1 ==
6412 09:57:49.247947 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6413 09:57:49.250975 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6414 09:57:49.251126
6415 09:57:49.251230 [DATLAT]
6416 09:57:49.254459 Freq=400, CH0 RK0
6417 09:57:49.254595
6418 09:57:49.254695 DATLAT Default: 0xf
6419 09:57:49.257808 0, 0xFFFF, sum = 0
6420 09:57:49.257938 1, 0xFFFF, sum = 0
6421 09:57:49.261053 2, 0xFFFF, sum = 0
6422 09:57:49.261191 3, 0xFFFF, sum = 0
6423 09:57:49.264345 4, 0xFFFF, sum = 0
6424 09:57:49.264477 5, 0xFFFF, sum = 0
6425 09:57:49.268230 6, 0xFFFF, sum = 0
6426 09:57:49.268363 7, 0xFFFF, sum = 0
6427 09:57:49.271114 8, 0xFFFF, sum = 0
6428 09:57:49.271240 9, 0xFFFF, sum = 0
6429 09:57:49.274326 10, 0xFFFF, sum = 0
6430 09:57:49.278168 11, 0xFFFF, sum = 0
6431 09:57:49.278332 12, 0xFFFF, sum = 0
6432 09:57:49.281219 13, 0x0, sum = 1
6433 09:57:49.281350 14, 0x0, sum = 2
6434 09:57:49.284501 15, 0x0, sum = 3
6435 09:57:49.284653 16, 0x0, sum = 4
6436 09:57:49.284756 best_step = 14
6437 09:57:49.284855
6438 09:57:49.287489 ==
6439 09:57:49.291239 Dram Type= 6, Freq= 0, CH_0, rank 0
6440 09:57:49.294596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6441 09:57:49.294769 ==
6442 09:57:49.294889 RX Vref Scan: 1
6443 09:57:49.295031
6444 09:57:49.297943 RX Vref 0 -> 0, step: 1
6445 09:57:49.298075
6446 09:57:49.300982 RX Delay -359 -> 252, step: 8
6447 09:57:49.301181
6448 09:57:49.304434 Set Vref, RX VrefLevel [Byte0]: 62
6449 09:57:49.307840 [Byte1]: 51
6450 09:57:49.311018
6451 09:57:49.311151 Final RX Vref Byte 0 = 62 to rank0
6452 09:57:49.314914 Final RX Vref Byte 1 = 51 to rank0
6453 09:57:49.317932 Final RX Vref Byte 0 = 62 to rank1
6454 09:57:49.321053 Final RX Vref Byte 1 = 51 to rank1==
6455 09:57:49.324712 Dram Type= 6, Freq= 0, CH_0, rank 0
6456 09:57:49.331281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6457 09:57:49.331454 ==
6458 09:57:49.331557 DQS Delay:
6459 09:57:49.334797 DQS0 = 60, DQS1 = 68
6460 09:57:49.334930 DQM Delay:
6461 09:57:49.335031 DQM0 = 14, DQM1 = 13
6462 09:57:49.337619 DQ Delay:
6463 09:57:49.340878 DQ0 =12, DQ1 =16, DQ2 =12, DQ3 =12
6464 09:57:49.344242 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6465 09:57:49.344386 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6466 09:57:49.350921 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6467 09:57:49.351097
6468 09:57:49.351216
6469 09:57:49.357573 [DQSOSCAuto] RK0, (LSB)MR18= 0x8382, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6470 09:57:49.360704 CH0 RK0: MR19=C0C, MR18=8382
6471 09:57:49.367946 CH0_RK0: MR19=0xC0C, MR18=0x8382, DQSOSC=393, MR23=63, INC=382, DEC=254
6472 09:57:49.368118 ==
6473 09:57:49.370782 Dram Type= 6, Freq= 0, CH_0, rank 1
6474 09:57:49.374575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6475 09:57:49.374746 ==
6476 09:57:49.377394 [Gating] SW mode calibration
6477 09:57:49.384427 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6478 09:57:49.390811 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6479 09:57:49.394071 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6480 09:57:49.397398 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6481 09:57:49.403998 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6482 09:57:49.407323 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6483 09:57:49.410485 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6484 09:57:49.417220 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6485 09:57:49.420508 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6486 09:57:49.423766 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6487 09:57:49.430884 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6488 09:57:49.431072 Total UI for P1: 0, mck2ui 16
6489 09:57:49.434005 best dqsien dly found for B0: ( 0, 14, 24)
6490 09:57:49.437102 Total UI for P1: 0, mck2ui 16
6491 09:57:49.441132 best dqsien dly found for B1: ( 0, 14, 24)
6492 09:57:49.447327 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6493 09:57:49.450339 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6494 09:57:49.450504
6495 09:57:49.453880 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6496 09:57:49.457009 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6497 09:57:49.460456 [Gating] SW calibration Done
6498 09:57:49.460602 ==
6499 09:57:49.463899 Dram Type= 6, Freq= 0, CH_0, rank 1
6500 09:57:49.467025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6501 09:57:49.467162 ==
6502 09:57:49.470696 RX Vref Scan: 0
6503 09:57:49.470862
6504 09:57:49.470991 RX Vref 0 -> 0, step: 1
6505 09:57:49.471114
6506 09:57:49.473456 RX Delay -410 -> 252, step: 16
6507 09:57:49.480084 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6508 09:57:49.483726 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6509 09:57:49.486831 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6510 09:57:49.490045 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6511 09:57:49.496838 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6512 09:57:49.500800 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6513 09:57:49.503430 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6514 09:57:49.506884 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6515 09:57:49.513459 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6516 09:57:49.516609 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6517 09:57:49.520047 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6518 09:57:49.523376 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6519 09:57:49.530542 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6520 09:57:49.533435 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6521 09:57:49.537022 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6522 09:57:49.540195 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6523 09:57:49.540348 ==
6524 09:57:49.543405 Dram Type= 6, Freq= 0, CH_0, rank 1
6525 09:57:49.550870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6526 09:57:49.551044 ==
6527 09:57:49.551149 DQS Delay:
6528 09:57:49.553477 DQS0 = 59, DQS1 = 59
6529 09:57:49.553595 DQM Delay:
6530 09:57:49.556444 DQM0 = 16, DQM1 = 10
6531 09:57:49.556603 DQ Delay:
6532 09:57:49.560169 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6533 09:57:49.563057 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6534 09:57:49.566328 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6535 09:57:49.569912 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6536 09:57:49.570086
6537 09:57:49.570220
6538 09:57:49.570346 ==
6539 09:57:49.573176 Dram Type= 6, Freq= 0, CH_0, rank 1
6540 09:57:49.576720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6541 09:57:49.576874 ==
6542 09:57:49.576983
6543 09:57:49.577081
6544 09:57:49.579900 TX Vref Scan disable
6545 09:57:49.580025 == TX Byte 0 ==
6546 09:57:49.586363 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6547 09:57:49.589767 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6548 09:57:49.590020 == TX Byte 1 ==
6549 09:57:49.596372 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6550 09:57:49.599580 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6551 09:57:49.599727 ==
6552 09:57:49.602753 Dram Type= 6, Freq= 0, CH_0, rank 1
6553 09:57:49.606571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6554 09:57:49.606773 ==
6555 09:57:49.606878
6556 09:57:49.606978
6557 09:57:49.609866 TX Vref Scan disable
6558 09:57:49.613251 == TX Byte 0 ==
6559 09:57:49.616062 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6560 09:57:49.619807 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6561 09:57:49.623140 == TX Byte 1 ==
6562 09:57:49.626478 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6563 09:57:49.629629 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6564 09:57:49.629773
6565 09:57:49.629908 [DATLAT]
6566 09:57:49.632899 Freq=400, CH0 RK1
6567 09:57:49.633037
6568 09:57:49.633135 DATLAT Default: 0xe
6569 09:57:49.636338 0, 0xFFFF, sum = 0
6570 09:57:49.636489 1, 0xFFFF, sum = 0
6571 09:57:49.639610 2, 0xFFFF, sum = 0
6572 09:57:49.642714 3, 0xFFFF, sum = 0
6573 09:57:49.642850 4, 0xFFFF, sum = 0
6574 09:57:49.646150 5, 0xFFFF, sum = 0
6575 09:57:49.646286 6, 0xFFFF, sum = 0
6576 09:57:49.649493 7, 0xFFFF, sum = 0
6577 09:57:49.649627 8, 0xFFFF, sum = 0
6578 09:57:49.653012 9, 0xFFFF, sum = 0
6579 09:57:49.653151 10, 0xFFFF, sum = 0
6580 09:57:49.656316 11, 0xFFFF, sum = 0
6581 09:57:49.656444 12, 0xFFFF, sum = 0
6582 09:57:49.659541 13, 0x0, sum = 1
6583 09:57:49.659674 14, 0x0, sum = 2
6584 09:57:49.663032 15, 0x0, sum = 3
6585 09:57:49.663163 16, 0x0, sum = 4
6586 09:57:49.666069 best_step = 14
6587 09:57:49.666192
6588 09:57:49.666292 ==
6589 09:57:49.669231 Dram Type= 6, Freq= 0, CH_0, rank 1
6590 09:57:49.672764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6591 09:57:49.672895 ==
6592 09:57:49.672996 RX Vref Scan: 0
6593 09:57:49.676385
6594 09:57:49.676500 RX Vref 0 -> 0, step: 1
6595 09:57:49.676598
6596 09:57:49.679399 RX Delay -359 -> 252, step: 8
6597 09:57:49.687092 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6598 09:57:49.690202 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6599 09:57:49.693364 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6600 09:57:49.696644 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6601 09:57:49.703340 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6602 09:57:49.706698 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6603 09:57:49.709800 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6604 09:57:49.713556 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6605 09:57:49.720138 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6606 09:57:49.723260 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6607 09:57:49.726439 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6608 09:57:49.733086 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6609 09:57:49.736360 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6610 09:57:49.739892 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6611 09:57:49.743029 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6612 09:57:49.749890 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6613 09:57:49.750102 ==
6614 09:57:49.753362 Dram Type= 6, Freq= 0, CH_0, rank 1
6615 09:57:49.756224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6616 09:57:49.756401 ==
6617 09:57:49.756549 DQS Delay:
6618 09:57:49.759670 DQS0 = 60, DQS1 = 72
6619 09:57:49.759834 DQM Delay:
6620 09:57:49.762909 DQM0 = 11, DQM1 = 17
6621 09:57:49.763070 DQ Delay:
6622 09:57:49.766162 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6623 09:57:49.769411 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6624 09:57:49.772676 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6625 09:57:49.776386 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6626 09:57:49.776531
6627 09:57:49.776635
6628 09:57:49.782866 [DQSOSCAuto] RK1, (LSB)MR18= 0xc67c, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6629 09:57:49.786486 CH0 RK1: MR19=C0C, MR18=C67C
6630 09:57:49.792910 CH0_RK1: MR19=0xC0C, MR18=0xC67C, DQSOSC=385, MR23=63, INC=398, DEC=265
6631 09:57:49.796454 [RxdqsGatingPostProcess] freq 400
6632 09:57:49.802986 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6633 09:57:49.806067 best DQS0 dly(2T, 0.5T) = (0, 10)
6634 09:57:49.806199 best DQS1 dly(2T, 0.5T) = (0, 10)
6635 09:57:49.810041 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6636 09:57:49.812936 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6637 09:57:49.816208 best DQS0 dly(2T, 0.5T) = (0, 10)
6638 09:57:49.819744 best DQS1 dly(2T, 0.5T) = (0, 10)
6639 09:57:49.822542 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6640 09:57:49.826315 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6641 09:57:49.829605 Pre-setting of DQS Precalculation
6642 09:57:49.836171 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6643 09:57:49.836342 ==
6644 09:57:49.838951 Dram Type= 6, Freq= 0, CH_1, rank 0
6645 09:57:49.842252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6646 09:57:49.842379 ==
6647 09:57:49.849450 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6648 09:57:49.852609 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6649 09:57:49.855559 [CA 0] Center 36 (8~64) winsize 57
6650 09:57:49.858896 [CA 1] Center 36 (8~64) winsize 57
6651 09:57:49.862781 [CA 2] Center 36 (8~64) winsize 57
6652 09:57:49.866125 [CA 3] Center 36 (8~64) winsize 57
6653 09:57:49.869132 [CA 4] Center 36 (8~64) winsize 57
6654 09:57:49.872148 [CA 5] Center 36 (8~64) winsize 57
6655 09:57:49.872294
6656 09:57:49.875538 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6657 09:57:49.875667
6658 09:57:49.878837 [CATrainingPosCal] consider 1 rank data
6659 09:57:49.882399 u2DelayCellTimex100 = 270/100 ps
6660 09:57:49.885321 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 09:57:49.888943 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 09:57:49.895186 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 09:57:49.898869 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 09:57:49.902002 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 09:57:49.905398 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 09:57:49.905557
6667 09:57:49.908566 CA PerBit enable=1, Macro0, CA PI delay=36
6668 09:57:49.908696
6669 09:57:49.911831 [CBTSetCACLKResult] CA Dly = 36
6670 09:57:49.911956 CS Dly: 1 (0~32)
6671 09:57:49.915200 ==
6672 09:57:49.915328 Dram Type= 6, Freq= 0, CH_1, rank 1
6673 09:57:49.921734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6674 09:57:49.921891 ==
6675 09:57:49.925667 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6676 09:57:49.932098 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6677 09:57:49.935346 [CA 0] Center 36 (8~64) winsize 57
6678 09:57:49.938697 [CA 1] Center 36 (8~64) winsize 57
6679 09:57:49.942173 [CA 2] Center 36 (8~64) winsize 57
6680 09:57:49.945070 [CA 3] Center 36 (8~64) winsize 57
6681 09:57:49.948353 [CA 4] Center 36 (8~64) winsize 57
6682 09:57:49.951651 [CA 5] Center 36 (8~64) winsize 57
6683 09:57:49.951790
6684 09:57:49.955518 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6685 09:57:49.955646
6686 09:57:49.958573 [CATrainingPosCal] consider 2 rank data
6687 09:57:49.961808 u2DelayCellTimex100 = 270/100 ps
6688 09:57:49.965086 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 09:57:49.968493 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 09:57:49.971648 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 09:57:49.975102 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 09:57:49.978127 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 09:57:49.984884 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 09:57:49.985050
6695 09:57:49.988363 CA PerBit enable=1, Macro0, CA PI delay=36
6696 09:57:49.988501
6697 09:57:49.991656 [CBTSetCACLKResult] CA Dly = 36
6698 09:57:49.991783 CS Dly: 1 (0~32)
6699 09:57:49.991883
6700 09:57:49.994998 ----->DramcWriteLeveling(PI) begin...
6701 09:57:49.995117 ==
6702 09:57:49.998139 Dram Type= 6, Freq= 0, CH_1, rank 0
6703 09:57:50.004852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6704 09:57:50.005002 ==
6705 09:57:50.007975 Write leveling (Byte 0): 40 => 8
6706 09:57:50.008091 Write leveling (Byte 1): 40 => 8
6707 09:57:50.011217 DramcWriteLeveling(PI) end<-----
6708 09:57:50.011334
6709 09:57:50.011436 ==
6710 09:57:50.014717 Dram Type= 6, Freq= 0, CH_1, rank 0
6711 09:57:50.021484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6712 09:57:50.021639 ==
6713 09:57:50.024975 [Gating] SW mode calibration
6714 09:57:50.031377 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6715 09:57:50.034717 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6716 09:57:50.041171 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6717 09:57:50.044948 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6718 09:57:50.048312 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6719 09:57:50.054921 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6720 09:57:50.057721 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6721 09:57:50.061006 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6722 09:57:50.067902 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6723 09:57:50.071072 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6724 09:57:50.074520 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6725 09:57:50.077786 Total UI for P1: 0, mck2ui 16
6726 09:57:50.080808 best dqsien dly found for B0: ( 0, 14, 24)
6727 09:57:50.084184 Total UI for P1: 0, mck2ui 16
6728 09:57:50.087986 best dqsien dly found for B1: ( 0, 14, 24)
6729 09:57:50.091041 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6730 09:57:50.094498 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6731 09:57:50.094627
6732 09:57:50.098228 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6733 09:57:50.104389 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6734 09:57:50.104540 [Gating] SW calibration Done
6735 09:57:50.104639 ==
6736 09:57:50.107361 Dram Type= 6, Freq= 0, CH_1, rank 0
6737 09:57:50.114559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6738 09:57:50.114720 ==
6739 09:57:50.114824 RX Vref Scan: 0
6740 09:57:50.114925
6741 09:57:50.117389 RX Vref 0 -> 0, step: 1
6742 09:57:50.117510
6743 09:57:50.120738 RX Delay -410 -> 252, step: 16
6744 09:57:50.123983 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6745 09:57:50.127346 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6746 09:57:50.134193 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6747 09:57:50.137273 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6748 09:57:50.140485 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6749 09:57:50.144290 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6750 09:57:50.150719 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6751 09:57:50.153982 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6752 09:57:50.157094 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6753 09:57:50.160476 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6754 09:57:50.167179 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6755 09:57:50.170874 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6756 09:57:50.173795 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6757 09:57:50.177104 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6758 09:57:50.183759 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6759 09:57:50.186930 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6760 09:57:50.187071 ==
6761 09:57:50.190588 Dram Type= 6, Freq= 0, CH_1, rank 0
6762 09:57:50.193704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6763 09:57:50.193830 ==
6764 09:57:50.197240 DQS Delay:
6765 09:57:50.197359 DQS0 = 51, DQS1 = 67
6766 09:57:50.200470 DQM Delay:
6767 09:57:50.200588 DQM0 = 12, DQM1 = 19
6768 09:57:50.203777 DQ Delay:
6769 09:57:50.203909 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6770 09:57:50.207200 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6771 09:57:50.210219 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6772 09:57:50.213549 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6773 09:57:50.213674
6774 09:57:50.213771
6775 09:57:50.213862 ==
6776 09:57:50.217027 Dram Type= 6, Freq= 0, CH_1, rank 0
6777 09:57:50.224298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6778 09:57:50.224471 ==
6779 09:57:50.224582
6780 09:57:50.224675
6781 09:57:50.224772 TX Vref Scan disable
6782 09:57:50.226811 == TX Byte 0 ==
6783 09:57:50.230671 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6784 09:57:50.233704 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6785 09:57:50.236991 == TX Byte 1 ==
6786 09:57:50.240023 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6787 09:57:50.243606 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6788 09:57:50.246795 ==
6789 09:57:50.249914 Dram Type= 6, Freq= 0, CH_1, rank 0
6790 09:57:50.253336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6791 09:57:50.253530 ==
6792 09:57:50.253677
6793 09:57:50.253775
6794 09:57:50.256571 TX Vref Scan disable
6795 09:57:50.256686 == TX Byte 0 ==
6796 09:57:50.260102 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6797 09:57:50.266692 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6798 09:57:50.266838 == TX Byte 1 ==
6799 09:57:50.270011 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6800 09:57:50.272997 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6801 09:57:50.276704
6802 09:57:50.276819 [DATLAT]
6803 09:57:50.276947 Freq=400, CH1 RK0
6804 09:57:50.277046
6805 09:57:50.279816 DATLAT Default: 0xf
6806 09:57:50.279927 0, 0xFFFF, sum = 0
6807 09:57:50.283172 1, 0xFFFF, sum = 0
6808 09:57:50.283290 2, 0xFFFF, sum = 0
6809 09:57:50.286373 3, 0xFFFF, sum = 0
6810 09:57:50.290105 4, 0xFFFF, sum = 0
6811 09:57:50.290228 5, 0xFFFF, sum = 0
6812 09:57:50.293016 6, 0xFFFF, sum = 0
6813 09:57:50.293135 7, 0xFFFF, sum = 0
6814 09:57:50.296321 8, 0xFFFF, sum = 0
6815 09:57:50.296439 9, 0xFFFF, sum = 0
6816 09:57:50.299946 10, 0xFFFF, sum = 0
6817 09:57:50.300062 11, 0xFFFF, sum = 0
6818 09:57:50.303571 12, 0xFFFF, sum = 0
6819 09:57:50.303702 13, 0x0, sum = 1
6820 09:57:50.306183 14, 0x0, sum = 2
6821 09:57:50.306303 15, 0x0, sum = 3
6822 09:57:50.309520 16, 0x0, sum = 4
6823 09:57:50.309640 best_step = 14
6824 09:57:50.309735
6825 09:57:50.309825 ==
6826 09:57:50.312837 Dram Type= 6, Freq= 0, CH_1, rank 0
6827 09:57:50.316021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6828 09:57:50.319656 ==
6829 09:57:50.319791 RX Vref Scan: 1
6830 09:57:50.319890
6831 09:57:50.322660 RX Vref 0 -> 0, step: 1
6832 09:57:50.322778
6833 09:57:50.325858 RX Delay -375 -> 252, step: 8
6834 09:57:50.325981
6835 09:57:50.329562 Set Vref, RX VrefLevel [Byte0]: 55
6836 09:57:50.332617 [Byte1]: 50
6837 09:57:50.332743
6838 09:57:50.335818 Final RX Vref Byte 0 = 55 to rank0
6839 09:57:50.339344 Final RX Vref Byte 1 = 50 to rank0
6840 09:57:50.342468 Final RX Vref Byte 0 = 55 to rank1
6841 09:57:50.345851 Final RX Vref Byte 1 = 50 to rank1==
6842 09:57:50.349063 Dram Type= 6, Freq= 0, CH_1, rank 0
6843 09:57:50.352812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6844 09:57:50.352939 ==
6845 09:57:50.355982 DQS Delay:
6846 09:57:50.356098 DQS0 = 56, DQS1 = 64
6847 09:57:50.359000 DQM Delay:
6848 09:57:50.359115 DQM0 = 12, DQM1 = 10
6849 09:57:50.362777 DQ Delay:
6850 09:57:50.362897 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6851 09:57:50.365849 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
6852 09:57:50.368969 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6853 09:57:50.372472 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6854 09:57:50.372598
6855 09:57:50.372694
6856 09:57:50.382623 [DQSOSCAuto] RK0, (LSB)MR18= 0x5367, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
6857 09:57:50.385782 CH1 RK0: MR19=C0C, MR18=5367
6858 09:57:50.388966 CH1_RK0: MR19=0xC0C, MR18=0x5367, DQSOSC=396, MR23=63, INC=376, DEC=251
6859 09:57:50.392305 ==
6860 09:57:50.396045 Dram Type= 6, Freq= 0, CH_1, rank 1
6861 09:57:50.398895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6862 09:57:50.399024 ==
6863 09:57:50.402362 [Gating] SW mode calibration
6864 09:57:50.408783 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6865 09:57:50.412511 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6866 09:57:50.418797 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6867 09:57:50.422132 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6868 09:57:50.425469 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6869 09:57:50.432097 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6870 09:57:50.435676 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6871 09:57:50.438507 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6872 09:57:50.445006 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6873 09:57:50.448324 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6874 09:57:50.451911 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6875 09:57:50.455215 Total UI for P1: 0, mck2ui 16
6876 09:57:50.458589 best dqsien dly found for B0: ( 0, 14, 24)
6877 09:57:50.461957 Total UI for P1: 0, mck2ui 16
6878 09:57:50.465084 best dqsien dly found for B1: ( 0, 14, 24)
6879 09:57:50.468327 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6880 09:57:50.471437 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6881 09:57:50.474962
6882 09:57:50.478005 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6883 09:57:50.481545 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6884 09:57:50.485039 [Gating] SW calibration Done
6885 09:57:50.485172 ==
6886 09:57:50.488041 Dram Type= 6, Freq= 0, CH_1, rank 1
6887 09:57:50.491241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6888 09:57:50.491362 ==
6889 09:57:50.491462 RX Vref Scan: 0
6890 09:57:50.494620
6891 09:57:50.494742 RX Vref 0 -> 0, step: 1
6892 09:57:50.494842
6893 09:57:50.497979 RX Delay -410 -> 252, step: 16
6894 09:57:50.501350 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6895 09:57:50.508042 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6896 09:57:50.511455 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6897 09:57:50.514602 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6898 09:57:50.518281 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6899 09:57:50.524851 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6900 09:57:50.527747 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6901 09:57:50.531399 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6902 09:57:50.534440 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6903 09:57:50.541341 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6904 09:57:50.544138 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6905 09:57:50.547455 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6906 09:57:50.554212 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6907 09:57:50.557119 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6908 09:57:50.560443 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6909 09:57:50.563791 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6910 09:57:50.563932 ==
6911 09:57:50.567258 Dram Type= 6, Freq= 0, CH_1, rank 1
6912 09:57:50.574077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6913 09:57:50.574231 ==
6914 09:57:50.574332 DQS Delay:
6915 09:57:50.577423 DQS0 = 59, DQS1 = 59
6916 09:57:50.577544 DQM Delay:
6917 09:57:50.580892 DQM0 = 19, DQM1 = 13
6918 09:57:50.581028 DQ Delay:
6919 09:57:50.583583 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6920 09:57:50.587309 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6921 09:57:50.590388 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6922 09:57:50.593608 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
6923 09:57:50.593737
6924 09:57:50.593841
6925 09:57:50.593936 ==
6926 09:57:50.596845 Dram Type= 6, Freq= 0, CH_1, rank 1
6927 09:57:50.600352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6928 09:57:50.600482 ==
6929 09:57:50.600585
6930 09:57:50.600681
6931 09:57:50.603367 TX Vref Scan disable
6932 09:57:50.603527 == TX Byte 0 ==
6933 09:57:50.610028 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6934 09:57:50.613420 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6935 09:57:50.613564 == TX Byte 1 ==
6936 09:57:50.619949 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6937 09:57:50.623402 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6938 09:57:50.623534 ==
6939 09:57:50.626312 Dram Type= 6, Freq= 0, CH_1, rank 1
6940 09:57:50.629723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6941 09:57:50.629840 ==
6942 09:57:50.632918
6943 09:57:50.633037
6944 09:57:50.633154 TX Vref Scan disable
6945 09:57:50.636637 == TX Byte 0 ==
6946 09:57:50.639472 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6947 09:57:50.642954 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6948 09:57:50.646172 == TX Byte 1 ==
6949 09:57:50.649721 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6950 09:57:50.652995 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6951 09:57:50.653127
6952 09:57:50.656373 [DATLAT]
6953 09:57:50.656493 Freq=400, CH1 RK1
6954 09:57:50.656604
6955 09:57:50.659605 DATLAT Default: 0xe
6956 09:57:50.659735 0, 0xFFFF, sum = 0
6957 09:57:50.663091 1, 0xFFFF, sum = 0
6958 09:57:50.663215 2, 0xFFFF, sum = 0
6959 09:57:50.666358 3, 0xFFFF, sum = 0
6960 09:57:50.666475 4, 0xFFFF, sum = 0
6961 09:57:50.669677 5, 0xFFFF, sum = 0
6962 09:57:50.669854 6, 0xFFFF, sum = 0
6963 09:57:50.672962 7, 0xFFFF, sum = 0
6964 09:57:50.673099 8, 0xFFFF, sum = 0
6965 09:57:50.676208 9, 0xFFFF, sum = 0
6966 09:57:50.676336 10, 0xFFFF, sum = 0
6967 09:57:50.679574 11, 0xFFFF, sum = 0
6968 09:57:50.679704 12, 0xFFFF, sum = 0
6969 09:57:50.682943 13, 0x0, sum = 1
6970 09:57:50.683098 14, 0x0, sum = 2
6971 09:57:50.686199 15, 0x0, sum = 3
6972 09:57:50.686339 16, 0x0, sum = 4
6973 09:57:50.689569 best_step = 14
6974 09:57:50.689733
6975 09:57:50.689839 ==
6976 09:57:50.692933 Dram Type= 6, Freq= 0, CH_1, rank 1
6977 09:57:50.696068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6978 09:57:50.696273 ==
6979 09:57:50.699090 RX Vref Scan: 0
6980 09:57:50.699231
6981 09:57:50.699336 RX Vref 0 -> 0, step: 1
6982 09:57:50.699438
6983 09:57:50.702448 RX Delay -359 -> 252, step: 8
6984 09:57:50.710981 iDelay=217, Bit 0, Center -40 (-287 ~ 208) 496
6985 09:57:50.714359 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6986 09:57:50.717372 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6987 09:57:50.724101 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6988 09:57:50.727322 iDelay=217, Bit 4, Center -44 (-295 ~ 208) 504
6989 09:57:50.730437 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6990 09:57:50.733775 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6991 09:57:50.740865 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6992 09:57:50.743596 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6993 09:57:50.747543 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6994 09:57:50.750585 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6995 09:57:50.757050 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6996 09:57:50.760324 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6997 09:57:50.763651 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6998 09:57:50.767127 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6999 09:57:50.773484 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7000 09:57:50.773661 ==
7001 09:57:50.777254 Dram Type= 6, Freq= 0, CH_1, rank 1
7002 09:57:50.779977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7003 09:57:50.780109 ==
7004 09:57:50.780244 DQS Delay:
7005 09:57:50.783266 DQS0 = 60, DQS1 = 64
7006 09:57:50.783384 DQM Delay:
7007 09:57:50.786593 DQM0 = 13, DQM1 = 10
7008 09:57:50.786719 DQ Delay:
7009 09:57:50.790072 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
7010 09:57:50.793388 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
7011 09:57:50.796704 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
7012 09:57:50.800047 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7013 09:57:50.800167
7014 09:57:50.800279
7015 09:57:50.806592 [DQSOSCAuto] RK1, (LSB)MR18= 0x77a9, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
7016 09:57:50.809811 CH1 RK1: MR19=C0C, MR18=77A9
7017 09:57:50.816525 CH1_RK1: MR19=0xC0C, MR18=0x77A9, DQSOSC=388, MR23=63, INC=392, DEC=261
7018 09:57:50.820394 [RxdqsGatingPostProcess] freq 400
7019 09:57:50.826416 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7020 09:57:50.829943 best DQS0 dly(2T, 0.5T) = (0, 10)
7021 09:57:50.833163 best DQS1 dly(2T, 0.5T) = (0, 10)
7022 09:57:50.836492 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7023 09:57:50.836635 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7024 09:57:50.839899 best DQS0 dly(2T, 0.5T) = (0, 10)
7025 09:57:50.843171 best DQS1 dly(2T, 0.5T) = (0, 10)
7026 09:57:50.846512 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7027 09:57:50.849825 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7028 09:57:50.853112 Pre-setting of DQS Precalculation
7029 09:57:50.859790 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7030 09:57:50.866254 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7031 09:57:50.873020 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7032 09:57:50.873192
7033 09:57:50.873296
7034 09:57:50.876258 [Calibration Summary] 800 Mbps
7035 09:57:50.876382 CH 0, Rank 0
7036 09:57:50.879573 SW Impedance : PASS
7037 09:57:50.882553 DUTY Scan : NO K
7038 09:57:50.882675 ZQ Calibration : PASS
7039 09:57:50.886413 Jitter Meter : NO K
7040 09:57:50.889245 CBT Training : PASS
7041 09:57:50.889372 Write leveling : PASS
7042 09:57:50.892646 RX DQS gating : PASS
7043 09:57:50.895970 RX DQ/DQS(RDDQC) : PASS
7044 09:57:50.896097 TX DQ/DQS : PASS
7045 09:57:50.899433 RX DATLAT : PASS
7046 09:57:50.899551 RX DQ/DQS(Engine): PASS
7047 09:57:50.902856 TX OE : NO K
7048 09:57:50.902975 All Pass.
7049 09:57:50.903071
7050 09:57:50.906095 CH 0, Rank 1
7051 09:57:50.906210 SW Impedance : PASS
7052 09:57:50.909470 DUTY Scan : NO K
7053 09:57:50.912811 ZQ Calibration : PASS
7054 09:57:50.912929 Jitter Meter : NO K
7055 09:57:50.916010 CBT Training : PASS
7056 09:57:50.919337 Write leveling : NO K
7057 09:57:50.919459 RX DQS gating : PASS
7058 09:57:50.922810 RX DQ/DQS(RDDQC) : PASS
7059 09:57:50.925984 TX DQ/DQS : PASS
7060 09:57:50.926114 RX DATLAT : PASS
7061 09:57:50.929319 RX DQ/DQS(Engine): PASS
7062 09:57:50.932531 TX OE : NO K
7063 09:57:50.932655 All Pass.
7064 09:57:50.932753
7065 09:57:50.932848 CH 1, Rank 0
7066 09:57:50.936068 SW Impedance : PASS
7067 09:57:50.939135 DUTY Scan : NO K
7068 09:57:50.939259 ZQ Calibration : PASS
7069 09:57:50.942332 Jitter Meter : NO K
7070 09:57:50.945551 CBT Training : PASS
7071 09:57:50.945676 Write leveling : PASS
7072 09:57:50.949308 RX DQS gating : PASS
7073 09:57:50.952226 RX DQ/DQS(RDDQC) : PASS
7074 09:57:50.952357 TX DQ/DQS : PASS
7075 09:57:50.955631 RX DATLAT : PASS
7076 09:57:50.958771 RX DQ/DQS(Engine): PASS
7077 09:57:50.958900 TX OE : NO K
7078 09:57:50.959006 All Pass.
7079 09:57:50.962660
7080 09:57:50.962778 CH 1, Rank 1
7081 09:57:50.965553 SW Impedance : PASS
7082 09:57:50.965673 DUTY Scan : NO K
7083 09:57:50.969071 ZQ Calibration : PASS
7084 09:57:50.969193 Jitter Meter : NO K
7085 09:57:50.972270 CBT Training : PASS
7086 09:57:50.975474 Write leveling : NO K
7087 09:57:50.975602 RX DQS gating : PASS
7088 09:57:50.978538 RX DQ/DQS(RDDQC) : PASS
7089 09:57:50.981940 TX DQ/DQS : PASS
7090 09:57:50.982067 RX DATLAT : PASS
7091 09:57:50.985554 RX DQ/DQS(Engine): PASS
7092 09:57:50.988803 TX OE : NO K
7093 09:57:50.988903 All Pass.
7094 09:57:50.988972
7095 09:57:50.992235 DramC Write-DBI off
7096 09:57:50.992320 PER_BANK_REFRESH: Hybrid Mode
7097 09:57:50.995182 TX_TRACKING: ON
7098 09:57:51.005232 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7099 09:57:51.008480 [FAST_K] Save calibration result to emmc
7100 09:57:51.011782 dramc_set_vcore_voltage set vcore to 725000
7101 09:57:51.011906 Read voltage for 1600, 0
7102 09:57:51.020592 Vio18 = 0
7103 09:57:51.020799 Vcore = 725000
7104 09:57:51.020936 Vdram = 0
7105 09:57:51.021041 Vddq = 0
7106 09:57:51.021135 Vmddr = 0
7107 09:57:51.022907 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7108 09:57:51.028571 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7109 09:57:51.031847 MEM_TYPE=3, freq_sel=13
7110 09:57:51.035178 sv_algorithm_assistance_LP4_3733
7111 09:57:51.038946 ============ PULL DRAM RESETB DOWN ============
7112 09:57:51.042343 ========== PULL DRAM RESETB DOWN end =========
7113 09:57:51.048940 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7114 09:57:51.052050 ===================================
7115 09:57:51.052185 LPDDR4 DRAM CONFIGURATION
7116 09:57:51.054944 ===================================
7117 09:57:51.058676 EX_ROW_EN[0] = 0x0
7118 09:57:51.058809 EX_ROW_EN[1] = 0x0
7119 09:57:51.061740 LP4Y_EN = 0x0
7120 09:57:51.064819 WORK_FSP = 0x1
7121 09:57:51.064953 WL = 0x5
7122 09:57:51.068670 RL = 0x5
7123 09:57:51.068799 BL = 0x2
7124 09:57:51.071477 RPST = 0x0
7125 09:57:51.071610 RD_PRE = 0x0
7126 09:57:51.075241 WR_PRE = 0x1
7127 09:57:51.075392 WR_PST = 0x1
7128 09:57:51.078375 DBI_WR = 0x0
7129 09:57:51.078508 DBI_RD = 0x0
7130 09:57:51.081769 OTF = 0x1
7131 09:57:51.085005 ===================================
7132 09:57:51.088275 ===================================
7133 09:57:51.088407 ANA top config
7134 09:57:51.091839 ===================================
7135 09:57:51.094967 DLL_ASYNC_EN = 0
7136 09:57:51.098312 ALL_SLAVE_EN = 0
7137 09:57:51.098443 NEW_RANK_MODE = 1
7138 09:57:51.101553 DLL_IDLE_MODE = 1
7139 09:57:51.105117 LP45_APHY_COMB_EN = 1
7140 09:57:51.108410 TX_ODT_DIS = 0
7141 09:57:51.111373 NEW_8X_MODE = 1
7142 09:57:51.111469 ===================================
7143 09:57:51.115196 ===================================
7144 09:57:51.118078 data_rate = 3200
7145 09:57:51.121502 CKR = 1
7146 09:57:51.124691 DQ_P2S_RATIO = 8
7147 09:57:51.128356 ===================================
7148 09:57:51.131422 CA_P2S_RATIO = 8
7149 09:57:51.134837 DQ_CA_OPEN = 0
7150 09:57:51.138332 DQ_SEMI_OPEN = 0
7151 09:57:51.138460 CA_SEMI_OPEN = 0
7152 09:57:51.141460 CA_FULL_RATE = 0
7153 09:57:51.144844 DQ_CKDIV4_EN = 0
7154 09:57:51.148218 CA_CKDIV4_EN = 0
7155 09:57:51.151635 CA_PREDIV_EN = 0
7156 09:57:51.154883 PH8_DLY = 12
7157 09:57:51.155010 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7158 09:57:51.158271 DQ_AAMCK_DIV = 4
7159 09:57:51.161590 CA_AAMCK_DIV = 4
7160 09:57:51.164925 CA_ADMCK_DIV = 4
7161 09:57:51.168145 DQ_TRACK_CA_EN = 0
7162 09:57:51.171339 CA_PICK = 1600
7163 09:57:51.171468 CA_MCKIO = 1600
7164 09:57:51.174782 MCKIO_SEMI = 0
7165 09:57:51.177804 PLL_FREQ = 3068
7166 09:57:51.181341 DQ_UI_PI_RATIO = 32
7167 09:57:51.184633 CA_UI_PI_RATIO = 0
7168 09:57:51.188057 ===================================
7169 09:57:51.191435 ===================================
7170 09:57:51.194460 memory_type:LPDDR4
7171 09:57:51.194587 GP_NUM : 10
7172 09:57:51.197666 SRAM_EN : 1
7173 09:57:51.197786 MD32_EN : 0
7174 09:57:51.200974 ===================================
7175 09:57:51.204782 [ANA_INIT] >>>>>>>>>>>>>>
7176 09:57:51.207670 <<<<<< [CONFIGURE PHASE]: ANA_TX
7177 09:57:51.211633 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7178 09:57:51.214474 ===================================
7179 09:57:51.217804 data_rate = 3200,PCW = 0X7600
7180 09:57:51.221399 ===================================
7181 09:57:51.224039 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7182 09:57:51.231138 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7183 09:57:51.234524 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7184 09:57:51.240736 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7185 09:57:51.244054 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7186 09:57:51.247604 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7187 09:57:51.247732 [ANA_INIT] flow start
7188 09:57:51.250700 [ANA_INIT] PLL >>>>>>>>
7189 09:57:51.254106 [ANA_INIT] PLL <<<<<<<<
7190 09:57:51.254228 [ANA_INIT] MIDPI >>>>>>>>
7191 09:57:51.257443 [ANA_INIT] MIDPI <<<<<<<<
7192 09:57:51.261032 [ANA_INIT] DLL >>>>>>>>
7193 09:57:51.264302 [ANA_INIT] DLL <<<<<<<<
7194 09:57:51.264426 [ANA_INIT] flow end
7195 09:57:51.267288 ============ LP4 DIFF to SE enter ============
7196 09:57:51.274180 ============ LP4 DIFF to SE exit ============
7197 09:57:51.274336 [ANA_INIT] <<<<<<<<<<<<<
7198 09:57:51.277299 [Flow] Enable top DCM control >>>>>
7199 09:57:51.280663 [Flow] Enable top DCM control <<<<<
7200 09:57:51.284036 Enable DLL master slave shuffle
7201 09:57:51.290294 ==============================================================
7202 09:57:51.290428 Gating Mode config
7203 09:57:51.297110 ==============================================================
7204 09:57:51.300574 Config description:
7205 09:57:51.310477 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7206 09:57:51.316810 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7207 09:57:51.320362 SELPH_MODE 0: By rank 1: By Phase
7208 09:57:51.326882 ==============================================================
7209 09:57:51.330242 GAT_TRACK_EN = 1
7210 09:57:51.330376 RX_GATING_MODE = 2
7211 09:57:51.333446 RX_GATING_TRACK_MODE = 2
7212 09:57:51.336802 SELPH_MODE = 1
7213 09:57:51.340134 PICG_EARLY_EN = 1
7214 09:57:51.343755 VALID_LAT_VALUE = 1
7215 09:57:51.350514 ==============================================================
7216 09:57:51.353904 Enter into Gating configuration >>>>
7217 09:57:51.356665 Exit from Gating configuration <<<<
7218 09:57:51.360051 Enter into DVFS_PRE_config >>>>>
7219 09:57:51.370201 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7220 09:57:51.373423 Exit from DVFS_PRE_config <<<<<
7221 09:57:51.376816 Enter into PICG configuration >>>>
7222 09:57:51.380311 Exit from PICG configuration <<<<
7223 09:57:51.383395 [RX_INPUT] configuration >>>>>
7224 09:57:51.386495 [RX_INPUT] configuration <<<<<
7225 09:57:51.390104 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7226 09:57:51.396578 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7227 09:57:51.403402 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7228 09:57:51.409792 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7229 09:57:51.412916 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7230 09:57:51.419892 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7231 09:57:51.423384 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7232 09:57:51.429439 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7233 09:57:51.432983 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7234 09:57:51.436167 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7235 09:57:51.439445 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7236 09:57:51.446056 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7237 09:57:51.449688 ===================================
7238 09:57:51.452694 LPDDR4 DRAM CONFIGURATION
7239 09:57:51.455835 ===================================
7240 09:57:51.455970 EX_ROW_EN[0] = 0x0
7241 09:57:51.459309 EX_ROW_EN[1] = 0x0
7242 09:57:51.459435 LP4Y_EN = 0x0
7243 09:57:51.462716 WORK_FSP = 0x1
7244 09:57:51.462838 WL = 0x5
7245 09:57:51.465984 RL = 0x5
7246 09:57:51.466104 BL = 0x2
7247 09:57:51.469420 RPST = 0x0
7248 09:57:51.469540 RD_PRE = 0x0
7249 09:57:51.472407 WR_PRE = 0x1
7250 09:57:51.472523 WR_PST = 0x1
7251 09:57:51.476067 DBI_WR = 0x0
7252 09:57:51.476192 DBI_RD = 0x0
7253 09:57:51.479079 OTF = 0x1
7254 09:57:51.482439 ===================================
7255 09:57:51.485599 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7256 09:57:51.489230 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7257 09:57:51.495707 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7258 09:57:51.498998 ===================================
7259 09:57:51.499099 LPDDR4 DRAM CONFIGURATION
7260 09:57:51.502346 ===================================
7261 09:57:51.505682 EX_ROW_EN[0] = 0x10
7262 09:57:51.508951 EX_ROW_EN[1] = 0x0
7263 09:57:51.509083 LP4Y_EN = 0x0
7264 09:57:51.512352 WORK_FSP = 0x1
7265 09:57:51.512473 WL = 0x5
7266 09:57:51.515693 RL = 0x5
7267 09:57:51.515812 BL = 0x2
7268 09:57:51.519050 RPST = 0x0
7269 09:57:51.519165 RD_PRE = 0x0
7270 09:57:51.521995 WR_PRE = 0x1
7271 09:57:51.522109 WR_PST = 0x1
7272 09:57:51.525533 DBI_WR = 0x0
7273 09:57:51.525652 DBI_RD = 0x0
7274 09:57:51.529213 OTF = 0x1
7275 09:57:51.532228 ===================================
7276 09:57:51.538892 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7277 09:57:51.539050 ==
7278 09:57:51.542233 Dram Type= 6, Freq= 0, CH_0, rank 0
7279 09:57:51.545414 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7280 09:57:51.545539 ==
7281 09:57:51.548885 [Duty_Offset_Calibration]
7282 09:57:51.548984 B0:2 B1:0 CA:3
7283 09:57:51.549050
7284 09:57:51.552194 [DutyScan_Calibration_Flow] k_type=0
7285 09:57:51.562694
7286 09:57:51.562833 ==CLK 0==
7287 09:57:51.565945 Final CLK duty delay cell = 0
7288 09:57:51.569361 [0] MAX Duty = 5031%(X100), DQS PI = 12
7289 09:57:51.572919 [0] MIN Duty = 4907%(X100), DQS PI = 6
7290 09:57:51.573051 [0] AVG Duty = 4969%(X100)
7291 09:57:51.576009
7292 09:57:51.579366 CH0 CLK Duty spec in!! Max-Min= 124%
7293 09:57:51.582789 [DutyScan_Calibration_Flow] ====Done====
7294 09:57:51.582921
7295 09:57:51.586014 [DutyScan_Calibration_Flow] k_type=1
7296 09:57:51.602704
7297 09:57:51.602912 ==DQS 0 ==
7298 09:57:51.606009 Final DQS duty delay cell = 0
7299 09:57:51.609173 [0] MAX Duty = 5094%(X100), DQS PI = 20
7300 09:57:51.612369 [0] MIN Duty = 4875%(X100), DQS PI = 50
7301 09:57:51.615979 [0] AVG Duty = 4984%(X100)
7302 09:57:51.616107
7303 09:57:51.616215 ==DQS 1 ==
7304 09:57:51.619006 Final DQS duty delay cell = 0
7305 09:57:51.622355 [0] MAX Duty = 5156%(X100), DQS PI = 32
7306 09:57:51.625648 [0] MIN Duty = 5031%(X100), DQS PI = 12
7307 09:57:51.628886 [0] AVG Duty = 5093%(X100)
7308 09:57:51.629015
7309 09:57:51.632295 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7310 09:57:51.632427
7311 09:57:51.635530 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7312 09:57:51.639344 [DutyScan_Calibration_Flow] ====Done====
7313 09:57:51.639474
7314 09:57:51.642275 [DutyScan_Calibration_Flow] k_type=3
7315 09:57:51.660931
7316 09:57:51.661124 ==DQM 0 ==
7317 09:57:51.663977 Final DQM duty delay cell = 0
7318 09:57:51.666982 [0] MAX Duty = 5156%(X100), DQS PI = 12
7319 09:57:51.670300 [0] MIN Duty = 4875%(X100), DQS PI = 48
7320 09:57:51.673552 [0] AVG Duty = 5015%(X100)
7321 09:57:51.673674
7322 09:57:51.673776 ==DQM 1 ==
7323 09:57:51.676776 Final DQM duty delay cell = 4
7324 09:57:51.680150 [4] MAX Duty = 5156%(X100), DQS PI = 0
7325 09:57:51.683506 [4] MIN Duty = 5031%(X100), DQS PI = 16
7326 09:57:51.686829 [4] AVG Duty = 5093%(X100)
7327 09:57:51.686955
7328 09:57:51.690369 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7329 09:57:51.690469
7330 09:57:51.693746 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7331 09:57:51.696968 [DutyScan_Calibration_Flow] ====Done====
7332 09:57:51.697116
7333 09:57:51.700021 [DutyScan_Calibration_Flow] k_type=2
7334 09:57:51.716566
7335 09:57:51.716711 ==DQ 0 ==
7336 09:57:51.719757 Final DQ duty delay cell = -4
7337 09:57:51.723513 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7338 09:57:51.726381 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7339 09:57:51.729830 [-4] AVG Duty = 4938%(X100)
7340 09:57:51.729932
7341 09:57:51.729998 ==DQ 1 ==
7342 09:57:51.732981 Final DQ duty delay cell = 0
7343 09:57:51.736784 [0] MAX Duty = 5156%(X100), DQS PI = 60
7344 09:57:51.739996 [0] MIN Duty = 5000%(X100), DQS PI = 16
7345 09:57:51.743060 [0] AVG Duty = 5078%(X100)
7346 09:57:51.743187
7347 09:57:51.746192 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7348 09:57:51.746306
7349 09:57:51.750006 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7350 09:57:51.752892 [DutyScan_Calibration_Flow] ====Done====
7351 09:57:51.753019 ==
7352 09:57:51.756395 Dram Type= 6, Freq= 0, CH_1, rank 0
7353 09:57:51.759510 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7354 09:57:51.759638 ==
7355 09:57:51.763263 [Duty_Offset_Calibration]
7356 09:57:51.763387 B0:1 B1:-2 CA:1
7357 09:57:51.763484
7358 09:57:51.766512 [DutyScan_Calibration_Flow] k_type=0
7359 09:57:51.777459
7360 09:57:51.777651 ==CLK 0==
7361 09:57:51.780781 Final CLK duty delay cell = 0
7362 09:57:51.783915 [0] MAX Duty = 5062%(X100), DQS PI = 20
7363 09:57:51.787232 [0] MIN Duty = 4844%(X100), DQS PI = 2
7364 09:57:51.787355 [0] AVG Duty = 4953%(X100)
7365 09:57:51.790062
7366 09:57:51.793537 CH1 CLK Duty spec in!! Max-Min= 218%
7367 09:57:51.796775 [DutyScan_Calibration_Flow] ====Done====
7368 09:57:51.796900
7369 09:57:51.800123 [DutyScan_Calibration_Flow] k_type=1
7370 09:57:51.815619
7371 09:57:51.815802 ==DQS 0 ==
7372 09:57:51.819323 Final DQS duty delay cell = -4
7373 09:57:51.822595 [-4] MAX Duty = 4969%(X100), DQS PI = 24
7374 09:57:51.826036 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7375 09:57:51.829151 [-4] AVG Duty = 4906%(X100)
7376 09:57:51.829275
7377 09:57:51.829375 ==DQS 1 ==
7378 09:57:51.832215 Final DQS duty delay cell = 0
7379 09:57:51.835729 [0] MAX Duty = 5093%(X100), DQS PI = 62
7380 09:57:51.838995 [0] MIN Duty = 4844%(X100), DQS PI = 26
7381 09:57:51.842332 [0] AVG Duty = 4968%(X100)
7382 09:57:51.842461
7383 09:57:51.845803 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7384 09:57:51.845921
7385 09:57:51.849040 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7386 09:57:51.852488 [DutyScan_Calibration_Flow] ====Done====
7387 09:57:51.852608
7388 09:57:51.855613 [DutyScan_Calibration_Flow] k_type=3
7389 09:57:51.872773
7390 09:57:51.872949 ==DQM 0 ==
7391 09:57:51.876198 Final DQM duty delay cell = 0
7392 09:57:51.879468 [0] MAX Duty = 5031%(X100), DQS PI = 24
7393 09:57:51.883015 [0] MIN Duty = 4813%(X100), DQS PI = 54
7394 09:57:51.886533 [0] AVG Duty = 4922%(X100)
7395 09:57:51.886668
7396 09:57:51.886762 ==DQM 1 ==
7397 09:57:51.889332 Final DQM duty delay cell = 0
7398 09:57:51.892619 [0] MAX Duty = 5093%(X100), DQS PI = 36
7399 09:57:51.896048 [0] MIN Duty = 4875%(X100), DQS PI = 24
7400 09:57:51.899453 [0] AVG Duty = 4984%(X100)
7401 09:57:51.899595
7402 09:57:51.902815 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7403 09:57:51.902934
7404 09:57:51.906271 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7405 09:57:51.909268 [DutyScan_Calibration_Flow] ====Done====
7406 09:57:51.909364
7407 09:57:51.912475 [DutyScan_Calibration_Flow] k_type=2
7408 09:57:51.929896
7409 09:57:51.930028 ==DQ 0 ==
7410 09:57:51.933094 Final DQ duty delay cell = 0
7411 09:57:51.936233 [0] MAX Duty = 5093%(X100), DQS PI = 22
7412 09:57:51.939541 [0] MIN Duty = 4907%(X100), DQS PI = 60
7413 09:57:51.939662 [0] AVG Duty = 5000%(X100)
7414 09:57:51.943076
7415 09:57:51.943167 ==DQ 1 ==
7416 09:57:51.946441 Final DQ duty delay cell = 0
7417 09:57:51.949849 [0] MAX Duty = 5156%(X100), DQS PI = 36
7418 09:57:51.953331 [0] MIN Duty = 4969%(X100), DQS PI = 24
7419 09:57:51.953459 [0] AVG Duty = 5062%(X100)
7420 09:57:51.956507
7421 09:57:51.959542 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7422 09:57:51.959661
7423 09:57:51.963103 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7424 09:57:51.966203 [DutyScan_Calibration_Flow] ====Done====
7425 09:57:51.969598 nWR fixed to 30
7426 09:57:51.969721 [ModeRegInit_LP4] CH0 RK0
7427 09:57:51.973111 [ModeRegInit_LP4] CH0 RK1
7428 09:57:51.976226 [ModeRegInit_LP4] CH1 RK0
7429 09:57:51.979523 [ModeRegInit_LP4] CH1 RK1
7430 09:57:51.979645 match AC timing 5
7431 09:57:51.983206 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7432 09:57:51.989383 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7433 09:57:51.992979 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7434 09:57:51.999715 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7435 09:57:52.002967 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7436 09:57:52.003096 [MiockJmeterHQA]
7437 09:57:52.003197
7438 09:57:52.005987 [DramcMiockJmeter] u1RxGatingPI = 0
7439 09:57:52.009220 0 : 4368, 4142
7440 09:57:52.009350 4 : 4368, 4140
7441 09:57:52.009451 8 : 4368, 4140
7442 09:57:52.012852 12 : 4366, 4139
7443 09:57:52.012971 16 : 4370, 4142
7444 09:57:52.016334 20 : 4258, 4029
7445 09:57:52.016457 24 : 4255, 4029
7446 09:57:52.019452 28 : 4257, 4029
7447 09:57:52.019571 32 : 4365, 4140
7448 09:57:52.022509 36 : 4257, 4029
7449 09:57:52.022627 40 : 4365, 4140
7450 09:57:52.022727 44 : 4255, 4029
7451 09:57:52.025789 48 : 4255, 4029
7452 09:57:52.025906 52 : 4366, 4140
7453 09:57:52.029087 56 : 4250, 4027
7454 09:57:52.029205 60 : 4366, 4139
7455 09:57:52.032905 64 : 4253, 4029
7456 09:57:52.033029 68 : 4363, 4139
7457 09:57:52.036195 72 : 4252, 4029
7458 09:57:52.036322 76 : 4255, 4029
7459 09:57:52.036463 80 : 4254, 4030
7460 09:57:52.039415 84 : 4253, 4029
7461 09:57:52.039533 88 : 4257, 4031
7462 09:57:52.042542 92 : 4366, 4139
7463 09:57:52.042659 96 : 4255, 4029
7464 09:57:52.045752 100 : 4255, 4029
7465 09:57:52.045875 104 : 4366, 3463
7466 09:57:52.049230 108 : 4363, 3
7467 09:57:52.049351 112 : 4255, 0
7468 09:57:52.049450 116 : 4255, 0
7469 09:57:52.052644 120 : 4253, 0
7470 09:57:52.052758 124 : 4255, 0
7471 09:57:52.056019 128 : 4368, 0
7472 09:57:52.056136 132 : 4252, 0
7473 09:57:52.056245 136 : 4363, 0
7474 09:57:52.059454 140 : 4363, 0
7475 09:57:52.059568 144 : 4363, 0
7476 09:57:52.059672 148 : 4253, 0
7477 09:57:52.062320 152 : 4252, 0
7478 09:57:52.062441 156 : 4257, 0
7479 09:57:52.066107 160 : 4363, 0
7480 09:57:52.066228 164 : 4363, 0
7481 09:57:52.066328 168 : 4250, 0
7482 09:57:52.069207 172 : 4252, 0
7483 09:57:52.069324 176 : 4253, 0
7484 09:57:52.072329 180 : 4368, 0
7485 09:57:52.072451 184 : 4252, 0
7486 09:57:52.072549 188 : 4253, 0
7487 09:57:52.075521 192 : 4252, 0
7488 09:57:52.075637 196 : 4257, 0
7489 09:57:52.078840 200 : 4253, 0
7490 09:57:52.078956 204 : 4250, 0
7491 09:57:52.079054 208 : 4257, 0
7492 09:57:52.082087 212 : 4363, 0
7493 09:57:52.082178 216 : 4363, 0
7494 09:57:52.085724 220 : 4250, 0
7495 09:57:52.085842 224 : 4255, 0
7496 09:57:52.085941 228 : 4253, 0
7497 09:57:52.088950 232 : 4253, 1
7498 09:57:52.089078 236 : 4255, 1262
7499 09:57:52.092334 240 : 4257, 4032
7500 09:57:52.092454 244 : 4254, 4030
7501 09:57:52.095573 248 : 4363, 4140
7502 09:57:52.095698 252 : 4253, 4029
7503 09:57:52.095800 256 : 4255, 4029
7504 09:57:52.098847 260 : 4363, 4139
7505 09:57:52.098967 264 : 4252, 4029
7506 09:57:52.102341 268 : 4253, 4029
7507 09:57:52.102464 272 : 4252, 4029
7508 09:57:52.105537 276 : 4368, 4142
7509 09:57:52.105654 280 : 4254, 4030
7510 09:57:52.108938 284 : 4253, 4029
7511 09:57:52.109055 288 : 4253, 4029
7512 09:57:52.111840 292 : 4257, 4032
7513 09:57:52.111959 296 : 4255, 4029
7514 09:57:52.115275 300 : 4252, 4029
7515 09:57:52.115391 304 : 4253, 4029
7516 09:57:52.118310 308 : 4257, 4032
7517 09:57:52.118427 312 : 4363, 4139
7518 09:57:52.121912 316 : 4252, 4029
7519 09:57:52.122033 320 : 4363, 4140
7520 09:57:52.122133 324 : 4255, 4029
7521 09:57:52.125513 328 : 4253, 4029
7522 09:57:52.125638 332 : 4255, 4029
7523 09:57:52.128826 336 : 4253, 4029
7524 09:57:52.128940 340 : 4364, 4140
7525 09:57:52.131623 344 : 4253, 4029
7526 09:57:52.131737 348 : 4254, 4029
7527 09:57:52.135076 352 : 4255, 3995
7528 09:57:52.135192 356 : 4253, 2777
7529 09:57:52.138415 360 : 4257, 2
7530 09:57:52.138531
7531 09:57:52.138627 MIOCK jitter meter ch=0
7532 09:57:52.138723
7533 09:57:52.141532 1T = (360-108) = 252 dly cells
7534 09:57:52.148297 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7535 09:57:52.148432 ==
7536 09:57:52.151688 Dram Type= 6, Freq= 0, CH_0, rank 0
7537 09:57:52.155263 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7538 09:57:52.155381 ==
7539 09:57:52.161999 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7540 09:57:52.164903 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7541 09:57:52.168216 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7542 09:57:52.174570 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7543 09:57:52.184488 [CA 0] Center 43 (13~74) winsize 62
7544 09:57:52.187833 [CA 1] Center 43 (13~74) winsize 62
7545 09:57:52.191132 [CA 2] Center 39 (10~68) winsize 59
7546 09:57:52.194418 [CA 3] Center 38 (9~68) winsize 60
7547 09:57:52.198356 [CA 4] Center 36 (7~66) winsize 60
7548 09:57:52.201460 [CA 5] Center 36 (7~66) winsize 60
7549 09:57:52.201585
7550 09:57:52.204662 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7551 09:57:52.204781
7552 09:57:52.207672 [CATrainingPosCal] consider 1 rank data
7553 09:57:52.211813 u2DelayCellTimex100 = 258/100 ps
7554 09:57:52.217938 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7555 09:57:52.220921 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7556 09:57:52.224715 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7557 09:57:52.228038 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7558 09:57:52.230918 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7559 09:57:52.234370 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7560 09:57:52.234486
7561 09:57:52.237692 CA PerBit enable=1, Macro0, CA PI delay=36
7562 09:57:52.237811
7563 09:57:52.240920 [CBTSetCACLKResult] CA Dly = 36
7564 09:57:52.244163 CS Dly: 11 (0~42)
7565 09:57:52.247215 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7566 09:57:52.250515 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7567 09:57:52.250646 ==
7568 09:57:52.253811 Dram Type= 6, Freq= 0, CH_0, rank 1
7569 09:57:52.260427 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7570 09:57:52.260535 ==
7571 09:57:52.264071 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7572 09:57:52.270728 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7573 09:57:52.273948 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7574 09:57:52.280301 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7575 09:57:52.288661 [CA 0] Center 44 (14~74) winsize 61
7576 09:57:52.291772 [CA 1] Center 43 (13~74) winsize 62
7577 09:57:52.295161 [CA 2] Center 39 (10~68) winsize 59
7578 09:57:52.297949 [CA 3] Center 39 (10~68) winsize 59
7579 09:57:52.301324 [CA 4] Center 37 (8~66) winsize 59
7580 09:57:52.304745 [CA 5] Center 36 (7~66) winsize 60
7581 09:57:52.304864
7582 09:57:52.308218 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7583 09:57:52.308337
7584 09:57:52.314937 [CATrainingPosCal] consider 2 rank data
7585 09:57:52.315063 u2DelayCellTimex100 = 258/100 ps
7586 09:57:52.321374 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7587 09:57:52.324868 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7588 09:57:52.328125 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7589 09:57:52.331205 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7590 09:57:52.334501 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7591 09:57:52.337984 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7592 09:57:52.338107
7593 09:57:52.341468 CA PerBit enable=1, Macro0, CA PI delay=36
7594 09:57:52.341587
7595 09:57:52.345035 [CBTSetCACLKResult] CA Dly = 36
7596 09:57:52.347718 CS Dly: 11 (0~43)
7597 09:57:52.350981 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7598 09:57:52.354327 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7599 09:57:52.354450
7600 09:57:52.357753 ----->DramcWriteLeveling(PI) begin...
7601 09:57:52.361093 ==
7602 09:57:52.361214 Dram Type= 6, Freq= 0, CH_0, rank 0
7603 09:57:52.367578 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7604 09:57:52.367712 ==
7605 09:57:52.370969 Write leveling (Byte 0): 37 => 37
7606 09:57:52.374393 Write leveling (Byte 1): 28 => 28
7607 09:57:52.377891 DramcWriteLeveling(PI) end<-----
7608 09:57:52.378009
7609 09:57:52.378112 ==
7610 09:57:52.381069 Dram Type= 6, Freq= 0, CH_0, rank 0
7611 09:57:52.384579 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7612 09:57:52.384696 ==
7613 09:57:52.387680 [Gating] SW mode calibration
7614 09:57:52.394591 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7615 09:57:52.397895 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7616 09:57:52.404617 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7617 09:57:52.407632 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7618 09:57:52.411147 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7619 09:57:52.417799 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7620 09:57:52.421208 1 4 16 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7621 09:57:52.424469 1 4 20 | B1->B0 | 2828 3434 | 0 1 | (1 1) (1 1)
7622 09:57:52.431150 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7623 09:57:52.434479 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7624 09:57:52.437475 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7625 09:57:52.444159 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7626 09:57:52.447315 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7627 09:57:52.450763 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7628 09:57:52.457424 1 5 16 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
7629 09:57:52.460509 1 5 20 | B1->B0 | 3232 2323 | 1 0 | (1 1) (1 0)
7630 09:57:52.464106 1 5 24 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
7631 09:57:52.470736 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7632 09:57:52.474240 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7633 09:57:52.477184 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7634 09:57:52.483966 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7635 09:57:52.487282 1 6 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7636 09:57:52.490837 1 6 16 | B1->B0 | 2323 3939 | 0 1 | (0 0) (0 0)
7637 09:57:52.497223 1 6 20 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7638 09:57:52.500728 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7639 09:57:52.503805 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7640 09:57:52.510493 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7641 09:57:52.513942 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7642 09:57:52.517278 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7643 09:57:52.523797 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7644 09:57:52.527171 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7645 09:57:52.530520 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7646 09:57:52.533993 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7647 09:57:52.540478 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 09:57:52.543897 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 09:57:52.547307 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 09:57:52.553816 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 09:57:52.557143 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 09:57:52.560093 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 09:57:52.567256 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 09:57:52.570151 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 09:57:52.573899 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 09:57:52.580395 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 09:57:52.583546 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 09:57:52.586681 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 09:57:52.593402 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7660 09:57:52.597086 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7661 09:57:52.599949 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7662 09:57:52.603374 Total UI for P1: 0, mck2ui 16
7663 09:57:52.606647 best dqsien dly found for B0: ( 1, 9, 14)
7664 09:57:52.613426 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7665 09:57:52.616681 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7666 09:57:52.619934 Total UI for P1: 0, mck2ui 16
7667 09:57:52.623397 best dqsien dly found for B1: ( 1, 9, 24)
7668 09:57:52.626855 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7669 09:57:52.629957 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7670 09:57:52.630084
7671 09:57:52.633780 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7672 09:57:52.636524 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7673 09:57:52.639872 [Gating] SW calibration Done
7674 09:57:52.639994 ==
7675 09:57:52.643285 Dram Type= 6, Freq= 0, CH_0, rank 0
7676 09:57:52.650041 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7677 09:57:52.650184 ==
7678 09:57:52.650287 RX Vref Scan: 0
7679 09:57:52.650387
7680 09:57:52.653350 RX Vref 0 -> 0, step: 1
7681 09:57:52.653466
7682 09:57:52.656856 RX Delay 0 -> 252, step: 8
7683 09:57:52.660035 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7684 09:57:52.662875 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7685 09:57:52.666405 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7686 09:57:52.669413 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7687 09:57:52.676481 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7688 09:57:52.679569 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7689 09:57:52.683107 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7690 09:57:52.685861 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7691 09:57:52.689674 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7692 09:57:52.696259 iDelay=192, Bit 9, Center 107 (48 ~ 167) 120
7693 09:57:52.699050 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7694 09:57:52.702845 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7695 09:57:52.705849 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7696 09:57:52.712822 iDelay=192, Bit 13, Center 127 (64 ~ 191) 128
7697 09:57:52.715746 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7698 09:57:52.719002 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7699 09:57:52.719124 ==
7700 09:57:52.722498 Dram Type= 6, Freq= 0, CH_0, rank 0
7701 09:57:52.725897 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7702 09:57:52.726016 ==
7703 09:57:52.729352 DQS Delay:
7704 09:57:52.729472 DQS0 = 0, DQS1 = 0
7705 09:57:52.732130 DQM Delay:
7706 09:57:52.732251 DQM0 = 127, DQM1 = 123
7707 09:57:52.732353 DQ Delay:
7708 09:57:52.739034 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7709 09:57:52.742452 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =135
7710 09:57:52.745583 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =119
7711 09:57:52.749149 DQ12 =127, DQ13 =127, DQ14 =135, DQ15 =131
7712 09:57:52.749277
7713 09:57:52.749377
7714 09:57:52.749470 ==
7715 09:57:52.752089 Dram Type= 6, Freq= 0, CH_0, rank 0
7716 09:57:52.755460 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7717 09:57:52.755574 ==
7718 09:57:52.755676
7719 09:57:52.755770
7720 09:57:52.758869 TX Vref Scan disable
7721 09:57:52.761873 == TX Byte 0 ==
7722 09:57:52.765442 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
7723 09:57:52.768660 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7724 09:57:52.772004 == TX Byte 1 ==
7725 09:57:52.775384 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7726 09:57:52.778469 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7727 09:57:52.778587 ==
7728 09:57:52.781905 Dram Type= 6, Freq= 0, CH_0, rank 0
7729 09:57:52.788372 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7730 09:57:52.788524 ==
7731 09:57:52.801036
7732 09:57:52.804349 TX Vref early break, caculate TX vref
7733 09:57:52.807378 TX Vref=16, minBit 8, minWin=21, winSum=366
7734 09:57:52.810850 TX Vref=18, minBit 11, minWin=21, winSum=375
7735 09:57:52.814291 TX Vref=20, minBit 8, minWin=22, winSum=382
7736 09:57:52.817723 TX Vref=22, minBit 8, minWin=23, winSum=393
7737 09:57:52.820708 TX Vref=24, minBit 8, minWin=24, winSum=404
7738 09:57:52.827333 TX Vref=26, minBit 8, minWin=24, winSum=411
7739 09:57:52.831001 TX Vref=28, minBit 4, minWin=25, winSum=410
7740 09:57:52.833843 TX Vref=30, minBit 8, minWin=23, winSum=406
7741 09:57:52.837357 TX Vref=32, minBit 9, minWin=22, winSum=396
7742 09:57:52.840578 TX Vref=34, minBit 8, minWin=22, winSum=387
7743 09:57:52.847043 [TxChooseVref] Worse bit 4, Min win 25, Win sum 410, Final Vref 28
7744 09:57:52.847184
7745 09:57:52.850585 Final TX Range 0 Vref 28
7746 09:57:52.850714
7747 09:57:52.850811 ==
7748 09:57:52.853836 Dram Type= 6, Freq= 0, CH_0, rank 0
7749 09:57:52.857050 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7750 09:57:52.857139 ==
7751 09:57:52.857226
7752 09:57:52.857290
7753 09:57:52.860400 TX Vref Scan disable
7754 09:57:52.867309 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7755 09:57:52.867442 == TX Byte 0 ==
7756 09:57:52.870451 u2DelayCellOfst[0]=15 cells (4 PI)
7757 09:57:52.873880 u2DelayCellOfst[1]=18 cells (5 PI)
7758 09:57:52.877199 u2DelayCellOfst[2]=15 cells (4 PI)
7759 09:57:52.880614 u2DelayCellOfst[3]=15 cells (4 PI)
7760 09:57:52.883805 u2DelayCellOfst[4]=11 cells (3 PI)
7761 09:57:52.887342 u2DelayCellOfst[5]=0 cells (0 PI)
7762 09:57:52.890536 u2DelayCellOfst[6]=18 cells (5 PI)
7763 09:57:52.893846 u2DelayCellOfst[7]=18 cells (5 PI)
7764 09:57:52.896999 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7765 09:57:52.900574 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7766 09:57:52.903818 == TX Byte 1 ==
7767 09:57:52.907080 u2DelayCellOfst[8]=0 cells (0 PI)
7768 09:57:52.907207 u2DelayCellOfst[9]=3 cells (1 PI)
7769 09:57:52.910548 u2DelayCellOfst[10]=7 cells (2 PI)
7770 09:57:52.913854 u2DelayCellOfst[11]=3 cells (1 PI)
7771 09:57:52.917060 u2DelayCellOfst[12]=15 cells (4 PI)
7772 09:57:52.920768 u2DelayCellOfst[13]=11 cells (3 PI)
7773 09:57:52.923738 u2DelayCellOfst[14]=15 cells (4 PI)
7774 09:57:52.927136 u2DelayCellOfst[15]=11 cells (3 PI)
7775 09:57:52.930021 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7776 09:57:52.936819 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7777 09:57:52.936929 DramC Write-DBI on
7778 09:57:52.936999 ==
7779 09:57:52.940546 Dram Type= 6, Freq= 0, CH_0, rank 0
7780 09:57:52.946998 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7781 09:57:52.947123 ==
7782 09:57:52.947204
7783 09:57:52.947274
7784 09:57:52.947340 TX Vref Scan disable
7785 09:57:52.950945 == TX Byte 0 ==
7786 09:57:52.954125 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
7787 09:57:52.957484 == TX Byte 1 ==
7788 09:57:52.960861 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7789 09:57:52.963708 DramC Write-DBI off
7790 09:57:52.963800
7791 09:57:52.963870 [DATLAT]
7792 09:57:52.963932 Freq=1600, CH0 RK0
7793 09:57:52.964006
7794 09:57:52.967090 DATLAT Default: 0xf
7795 09:57:52.967185 0, 0xFFFF, sum = 0
7796 09:57:52.970400 1, 0xFFFF, sum = 0
7797 09:57:52.973832 2, 0xFFFF, sum = 0
7798 09:57:52.973958 3, 0xFFFF, sum = 0
7799 09:57:52.977172 4, 0xFFFF, sum = 0
7800 09:57:52.977291 5, 0xFFFF, sum = 0
7801 09:57:52.980297 6, 0xFFFF, sum = 0
7802 09:57:52.980412 7, 0xFFFF, sum = 0
7803 09:57:52.983698 8, 0xFFFF, sum = 0
7804 09:57:52.983820 9, 0xFFFF, sum = 0
7805 09:57:52.987098 10, 0xFFFF, sum = 0
7806 09:57:52.987213 11, 0xFFFF, sum = 0
7807 09:57:52.990393 12, 0xFFFF, sum = 0
7808 09:57:52.990513 13, 0xEFFF, sum = 0
7809 09:57:52.993798 14, 0x0, sum = 1
7810 09:57:52.993913 15, 0x0, sum = 2
7811 09:57:52.997204 16, 0x0, sum = 3
7812 09:57:52.997326 17, 0x0, sum = 4
7813 09:57:53.000311 best_step = 15
7814 09:57:53.000426
7815 09:57:53.000522 ==
7816 09:57:53.004058 Dram Type= 6, Freq= 0, CH_0, rank 0
7817 09:57:53.006983 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7818 09:57:53.007106 ==
7819 09:57:53.010299 RX Vref Scan: 1
7820 09:57:53.010418
7821 09:57:53.010515 Set Vref Range= 24 -> 127
7822 09:57:53.010615
7823 09:57:53.013809 RX Vref 24 -> 127, step: 1
7824 09:57:53.013927
7825 09:57:53.017054 RX Delay 3 -> 252, step: 4
7826 09:57:53.017175
7827 09:57:53.020283 Set Vref, RX VrefLevel [Byte0]: 24
7828 09:57:53.023472 [Byte1]: 24
7829 09:57:53.023569
7830 09:57:53.026883 Set Vref, RX VrefLevel [Byte0]: 25
7831 09:57:53.030424 [Byte1]: 25
7832 09:57:53.033182
7833 09:57:53.033298 Set Vref, RX VrefLevel [Byte0]: 26
7834 09:57:53.036473 [Byte1]: 26
7835 09:57:53.040990
7836 09:57:53.041125 Set Vref, RX VrefLevel [Byte0]: 27
7837 09:57:53.044151 [Byte1]: 27
7838 09:57:53.048467
7839 09:57:53.048597 Set Vref, RX VrefLevel [Byte0]: 28
7840 09:57:53.052402 [Byte1]: 28
7841 09:57:53.056450
7842 09:57:53.056596 Set Vref, RX VrefLevel [Byte0]: 29
7843 09:57:53.059701 [Byte1]: 29
7844 09:57:53.064106
7845 09:57:53.064244 Set Vref, RX VrefLevel [Byte0]: 30
7846 09:57:53.067515 [Byte1]: 30
7847 09:57:53.072133
7848 09:57:53.072271 Set Vref, RX VrefLevel [Byte0]: 31
7849 09:57:53.074847 [Byte1]: 31
7850 09:57:53.079405
7851 09:57:53.079544 Set Vref, RX VrefLevel [Byte0]: 32
7852 09:57:53.082694 [Byte1]: 32
7853 09:57:53.087127
7854 09:57:53.087279 Set Vref, RX VrefLevel [Byte0]: 33
7855 09:57:53.090479 [Byte1]: 33
7856 09:57:53.094850
7857 09:57:53.094974 Set Vref, RX VrefLevel [Byte0]: 34
7858 09:57:53.097995 [Byte1]: 34
7859 09:57:53.102396
7860 09:57:53.102500 Set Vref, RX VrefLevel [Byte0]: 35
7861 09:57:53.105718 [Byte1]: 35
7862 09:57:53.109848
7863 09:57:53.109950 Set Vref, RX VrefLevel [Byte0]: 36
7864 09:57:53.113338 [Byte1]: 36
7865 09:57:53.117429
7866 09:57:53.117563 Set Vref, RX VrefLevel [Byte0]: 37
7867 09:57:53.120981 [Byte1]: 37
7868 09:57:53.125114
7869 09:57:53.125235 Set Vref, RX VrefLevel [Byte0]: 38
7870 09:57:53.128407 [Byte1]: 38
7871 09:57:53.132698
7872 09:57:53.132803 Set Vref, RX VrefLevel [Byte0]: 39
7873 09:57:53.136045 [Byte1]: 39
7874 09:57:53.140643
7875 09:57:53.140753 Set Vref, RX VrefLevel [Byte0]: 40
7876 09:57:53.144079 [Byte1]: 40
7877 09:57:53.147993
7878 09:57:53.148124 Set Vref, RX VrefLevel [Byte0]: 41
7879 09:57:53.151415 [Byte1]: 41
7880 09:57:53.155938
7881 09:57:53.156069 Set Vref, RX VrefLevel [Byte0]: 42
7882 09:57:53.159207 [Byte1]: 42
7883 09:57:53.163470
7884 09:57:53.163604 Set Vref, RX VrefLevel [Byte0]: 43
7885 09:57:53.166864 [Byte1]: 43
7886 09:57:53.171405
7887 09:57:53.171545 Set Vref, RX VrefLevel [Byte0]: 44
7888 09:57:53.174683 [Byte1]: 44
7889 09:57:53.179079
7890 09:57:53.179211 Set Vref, RX VrefLevel [Byte0]: 45
7891 09:57:53.181977 [Byte1]: 45
7892 09:57:53.186289
7893 09:57:53.186421 Set Vref, RX VrefLevel [Byte0]: 46
7894 09:57:53.189967 [Byte1]: 46
7895 09:57:53.194321
7896 09:57:53.194449 Set Vref, RX VrefLevel [Byte0]: 47
7897 09:57:53.197670 [Byte1]: 47
7898 09:57:53.201558
7899 09:57:53.201695 Set Vref, RX VrefLevel [Byte0]: 48
7900 09:57:53.205374 [Byte1]: 48
7901 09:57:53.209178
7902 09:57:53.209286 Set Vref, RX VrefLevel [Byte0]: 49
7903 09:57:53.212885 [Byte1]: 49
7904 09:57:53.217241
7905 09:57:53.217380 Set Vref, RX VrefLevel [Byte0]: 50
7906 09:57:53.220698 [Byte1]: 50
7907 09:57:53.224802
7908 09:57:53.224937 Set Vref, RX VrefLevel [Byte0]: 51
7909 09:57:53.227808 [Byte1]: 51
7910 09:57:53.232225
7911 09:57:53.232327 Set Vref, RX VrefLevel [Byte0]: 52
7912 09:57:53.235476 [Byte1]: 52
7913 09:57:53.240405
7914 09:57:53.240540 Set Vref, RX VrefLevel [Byte0]: 53
7915 09:57:53.243299 [Byte1]: 53
7916 09:57:53.247824
7917 09:57:53.247953 Set Vref, RX VrefLevel [Byte0]: 54
7918 09:57:53.251028 [Byte1]: 54
7919 09:57:53.255215
7920 09:57:53.255338 Set Vref, RX VrefLevel [Byte0]: 55
7921 09:57:53.258687 [Byte1]: 55
7922 09:57:53.263074
7923 09:57:53.263176 Set Vref, RX VrefLevel [Byte0]: 56
7924 09:57:53.266204 [Byte1]: 56
7925 09:57:53.270873
7926 09:57:53.271001 Set Vref, RX VrefLevel [Byte0]: 57
7927 09:57:53.273971 [Byte1]: 57
7928 09:57:53.278162
7929 09:57:53.278260 Set Vref, RX VrefLevel [Byte0]: 58
7930 09:57:53.281938 [Byte1]: 58
7931 09:57:53.286246
7932 09:57:53.286343 Set Vref, RX VrefLevel [Byte0]: 59
7933 09:57:53.289169 [Byte1]: 59
7934 09:57:53.293927
7935 09:57:53.294025 Set Vref, RX VrefLevel [Byte0]: 60
7936 09:57:53.296890 [Byte1]: 60
7937 09:57:53.301301
7938 09:57:53.301394 Set Vref, RX VrefLevel [Byte0]: 61
7939 09:57:53.304642 [Byte1]: 61
7940 09:57:53.308968
7941 09:57:53.309105 Set Vref, RX VrefLevel [Byte0]: 62
7942 09:57:53.312103 [Byte1]: 62
7943 09:57:53.316661
7944 09:57:53.316782 Set Vref, RX VrefLevel [Byte0]: 63
7945 09:57:53.319986 [Byte1]: 63
7946 09:57:53.324373
7947 09:57:53.324464 Set Vref, RX VrefLevel [Byte0]: 64
7948 09:57:53.327695 [Byte1]: 64
7949 09:57:53.331905
7950 09:57:53.332015 Set Vref, RX VrefLevel [Byte0]: 65
7951 09:57:53.335189 [Byte1]: 65
7952 09:57:53.339451
7953 09:57:53.339588 Set Vref, RX VrefLevel [Byte0]: 66
7954 09:57:53.342597 [Byte1]: 66
7955 09:57:53.346965
7956 09:57:53.347092 Set Vref, RX VrefLevel [Byte0]: 67
7957 09:57:53.350381 [Byte1]: 67
7958 09:57:53.355033
7959 09:57:53.355167 Set Vref, RX VrefLevel [Byte0]: 68
7960 09:57:53.358383 [Byte1]: 68
7961 09:57:53.362435
7962 09:57:53.362568 Set Vref, RX VrefLevel [Byte0]: 69
7963 09:57:53.365795 [Byte1]: 69
7964 09:57:53.370091
7965 09:57:53.370240 Set Vref, RX VrefLevel [Byte0]: 70
7966 09:57:53.373425 [Byte1]: 70
7967 09:57:53.377798
7968 09:57:53.377929 Set Vref, RX VrefLevel [Byte0]: 71
7969 09:57:53.380949 [Byte1]: 71
7970 09:57:53.385772
7971 09:57:53.385908 Set Vref, RX VrefLevel [Byte0]: 72
7972 09:57:53.388758 [Byte1]: 72
7973 09:57:53.392994
7974 09:57:53.393126 Set Vref, RX VrefLevel [Byte0]: 73
7975 09:57:53.396220 [Byte1]: 73
7976 09:57:53.400688
7977 09:57:53.400819 Set Vref, RX VrefLevel [Byte0]: 74
7978 09:57:53.404037 [Byte1]: 74
7979 09:57:53.408474
7980 09:57:53.408611 Set Vref, RX VrefLevel [Byte0]: 75
7981 09:57:53.411876 [Byte1]: 75
7982 09:57:53.415969
7983 09:57:53.416107 Set Vref, RX VrefLevel [Byte0]: 76
7984 09:57:53.419440 [Byte1]: 76
7985 09:57:53.423857
7986 09:57:53.424002 Set Vref, RX VrefLevel [Byte0]: 77
7987 09:57:53.427266 [Byte1]: 77
7988 09:57:53.431866
7989 09:57:53.432006 Set Vref, RX VrefLevel [Byte0]: 78
7990 09:57:53.434430 [Byte1]: 78
7991 09:57:53.438986
7992 09:57:53.439163 Final RX Vref Byte 0 = 62 to rank0
7993 09:57:53.442067 Final RX Vref Byte 1 = 59 to rank0
7994 09:57:53.445774 Final RX Vref Byte 0 = 62 to rank1
7995 09:57:53.448716 Final RX Vref Byte 1 = 59 to rank1==
7996 09:57:53.452099 Dram Type= 6, Freq= 0, CH_0, rank 0
7997 09:57:53.458617 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7998 09:57:53.458770 ==
7999 09:57:53.458875 DQS Delay:
8000 09:57:53.462085 DQS0 = 0, DQS1 = 0
8001 09:57:53.462205 DQM Delay:
8002 09:57:53.462305 DQM0 = 126, DQM1 = 119
8003 09:57:53.465313 DQ Delay:
8004 09:57:53.468431 DQ0 =126, DQ1 =126, DQ2 =126, DQ3 =122
8005 09:57:53.471972 DQ4 =126, DQ5 =114, DQ6 =132, DQ7 =138
8006 09:57:53.475231 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
8007 09:57:53.478524 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =126
8008 09:57:53.478631
8009 09:57:53.478734
8010 09:57:53.478819
8011 09:57:53.481899 [DramC_TX_OE_Calibration] TA2
8012 09:57:53.485087 Original DQ_B0 (3 6) =30, OEN = 27
8013 09:57:53.488477 Original DQ_B1 (3 6) =30, OEN = 27
8014 09:57:53.491868 24, 0x0, End_B0=24 End_B1=24
8015 09:57:53.495058 25, 0x0, End_B0=25 End_B1=25
8016 09:57:53.495208 26, 0x0, End_B0=26 End_B1=26
8017 09:57:53.498418 27, 0x0, End_B0=27 End_B1=27
8018 09:57:53.501424 28, 0x0, End_B0=28 End_B1=28
8019 09:57:53.505079 29, 0x0, End_B0=29 End_B1=29
8020 09:57:53.505240 30, 0x0, End_B0=30 End_B1=30
8021 09:57:53.508503 31, 0x4545, End_B0=30 End_B1=30
8022 09:57:53.511980 Byte0 end_step=30 best_step=27
8023 09:57:53.514845 Byte1 end_step=30 best_step=27
8024 09:57:53.518203 Byte0 TX OE(2T, 0.5T) = (3, 3)
8025 09:57:53.521613 Byte1 TX OE(2T, 0.5T) = (3, 3)
8026 09:57:53.521710
8027 09:57:53.521800
8028 09:57:53.528149 [DQSOSCAuto] RK0, (LSB)MR18= 0x1111, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
8029 09:57:53.531440 CH0 RK0: MR19=303, MR18=1111
8030 09:57:53.538540 CH0_RK0: MR19=0x303, MR18=0x1111, DQSOSC=401, MR23=63, INC=22, DEC=15
8031 09:57:53.538733
8032 09:57:53.541516 ----->DramcWriteLeveling(PI) begin...
8033 09:57:53.541672 ==
8034 09:57:53.544676 Dram Type= 6, Freq= 0, CH_0, rank 1
8035 09:57:53.547952 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8036 09:57:53.548098 ==
8037 09:57:53.551558 Write leveling (Byte 0): 35 => 35
8038 09:57:53.554610 Write leveling (Byte 1): 30 => 30
8039 09:57:53.557954 DramcWriteLeveling(PI) end<-----
8040 09:57:53.558090
8041 09:57:53.558249 ==
8042 09:57:53.561210 Dram Type= 6, Freq= 0, CH_0, rank 1
8043 09:57:53.564591 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8044 09:57:53.564757 ==
8045 09:57:53.567958 [Gating] SW mode calibration
8046 09:57:53.574522 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8047 09:57:53.581206 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8048 09:57:53.584626 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8049 09:57:53.590995 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8050 09:57:53.594365 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8051 09:57:53.597920 1 4 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8052 09:57:53.604501 1 4 16 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
8053 09:57:53.607796 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8054 09:57:53.611102 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8055 09:57:53.617661 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8056 09:57:53.621051 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8057 09:57:53.624573 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8058 09:57:53.630788 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8059 09:57:53.634116 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 1)
8060 09:57:53.637722 1 5 16 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
8061 09:57:53.644322 1 5 20 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8062 09:57:53.647653 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8063 09:57:53.650856 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8064 09:57:53.657565 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8065 09:57:53.660763 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8066 09:57:53.663816 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8067 09:57:53.667212 1 6 12 | B1->B0 | 2323 3e3e | 0 1 | (0 0) (0 0)
8068 09:57:53.673859 1 6 16 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
8069 09:57:53.677053 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8070 09:57:53.680466 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8071 09:57:53.687283 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8072 09:57:53.690686 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8073 09:57:53.694151 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8074 09:57:53.700257 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8075 09:57:53.704062 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8076 09:57:53.706947 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8077 09:57:53.713561 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8078 09:57:53.716834 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8079 09:57:53.720497 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 09:57:53.726910 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 09:57:53.730022 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 09:57:53.733615 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 09:57:53.740335 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 09:57:53.743404 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 09:57:53.746675 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 09:57:53.753461 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 09:57:53.756812 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 09:57:53.759918 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 09:57:53.766745 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 09:57:53.769972 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8091 09:57:53.773318 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8092 09:57:53.780053 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8093 09:57:53.780241 Total UI for P1: 0, mck2ui 16
8094 09:57:53.786635 best dqsien dly found for B0: ( 1, 9, 10)
8095 09:57:53.789638 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8096 09:57:53.793398 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8097 09:57:53.796853 Total UI for P1: 0, mck2ui 16
8098 09:57:53.799563 best dqsien dly found for B1: ( 1, 9, 18)
8099 09:57:53.803063 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8100 09:57:53.806407 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8101 09:57:53.806542
8102 09:57:53.813463 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8103 09:57:53.816793 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8104 09:57:53.819532 [Gating] SW calibration Done
8105 09:57:53.819667 ==
8106 09:57:53.822907 Dram Type= 6, Freq= 0, CH_0, rank 1
8107 09:57:53.826474 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8108 09:57:53.826569 ==
8109 09:57:53.826636 RX Vref Scan: 0
8110 09:57:53.826697
8111 09:57:53.829573 RX Vref 0 -> 0, step: 1
8112 09:57:53.829681
8113 09:57:53.832882 RX Delay 0 -> 252, step: 8
8114 09:57:53.836343 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8115 09:57:53.839466 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8116 09:57:53.843188 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8117 09:57:53.849592 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8118 09:57:53.852704 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8119 09:57:53.856442 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8120 09:57:53.859543 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8121 09:57:53.862812 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8122 09:57:53.869438 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8123 09:57:53.872710 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8124 09:57:53.875951 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8125 09:57:53.879416 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8126 09:57:53.885920 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8127 09:57:53.889305 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8128 09:57:53.892553 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8129 09:57:53.895745 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8130 09:57:53.895833 ==
8131 09:57:53.899317 Dram Type= 6, Freq= 0, CH_0, rank 1
8132 09:57:53.906019 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8133 09:57:53.906174 ==
8134 09:57:53.906283 DQS Delay:
8135 09:57:53.906377 DQS0 = 0, DQS1 = 0
8136 09:57:53.908921 DQM Delay:
8137 09:57:53.909035 DQM0 = 128, DQM1 = 122
8138 09:57:53.912652 DQ Delay:
8139 09:57:53.915535 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
8140 09:57:53.918906 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8141 09:57:53.922169 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8142 09:57:53.925590 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8143 09:57:53.925718
8144 09:57:53.925816
8145 09:57:53.925911 ==
8146 09:57:53.929048 Dram Type= 6, Freq= 0, CH_0, rank 1
8147 09:57:53.932434 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8148 09:57:53.935728 ==
8149 09:57:53.935861
8150 09:57:53.935953
8151 09:57:53.936059 TX Vref Scan disable
8152 09:57:53.938892 == TX Byte 0 ==
8153 09:57:53.942221 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8154 09:57:53.945589 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8155 09:57:53.949068 == TX Byte 1 ==
8156 09:57:53.952074 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8157 09:57:53.955861 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8158 09:57:53.955990 ==
8159 09:57:53.958591 Dram Type= 6, Freq= 0, CH_0, rank 1
8160 09:57:53.965157 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8161 09:57:53.965303 ==
8162 09:57:53.979178
8163 09:57:53.982531 TX Vref early break, caculate TX vref
8164 09:57:53.985824 TX Vref=16, minBit 0, minWin=23, winSum=377
8165 09:57:53.988964 TX Vref=18, minBit 4, minWin=23, winSum=384
8166 09:57:53.992279 TX Vref=20, minBit 9, minWin=23, winSum=393
8167 09:57:53.995875 TX Vref=22, minBit 1, minWin=23, winSum=398
8168 09:57:53.998942 TX Vref=24, minBit 0, minWin=25, winSum=407
8169 09:57:54.005365 TX Vref=26, minBit 2, minWin=25, winSum=415
8170 09:57:54.008823 TX Vref=28, minBit 2, minWin=25, winSum=419
8171 09:57:54.012330 TX Vref=30, minBit 0, minWin=25, winSum=415
8172 09:57:54.015544 TX Vref=32, minBit 8, minWin=24, winSum=406
8173 09:57:54.019464 TX Vref=34, minBit 8, minWin=24, winSum=402
8174 09:57:54.022150 TX Vref=36, minBit 8, minWin=23, winSum=391
8175 09:57:54.028983 [TxChooseVref] Worse bit 2, Min win 25, Win sum 419, Final Vref 28
8176 09:57:54.029139
8177 09:57:54.032372 Final TX Range 0 Vref 28
8178 09:57:54.032460
8179 09:57:54.032526 ==
8180 09:57:54.035815 Dram Type= 6, Freq= 0, CH_0, rank 1
8181 09:57:54.038935 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8182 09:57:54.039047 ==
8183 09:57:54.039136
8184 09:57:54.039227
8185 09:57:54.041830 TX Vref Scan disable
8186 09:57:54.048936 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8187 09:57:54.049109 == TX Byte 0 ==
8188 09:57:54.051755 u2DelayCellOfst[0]=11 cells (3 PI)
8189 09:57:54.055187 u2DelayCellOfst[1]=18 cells (5 PI)
8190 09:57:54.058486 u2DelayCellOfst[2]=11 cells (3 PI)
8191 09:57:54.061859 u2DelayCellOfst[3]=11 cells (3 PI)
8192 09:57:54.065104 u2DelayCellOfst[4]=7 cells (2 PI)
8193 09:57:54.068349 u2DelayCellOfst[5]=0 cells (0 PI)
8194 09:57:54.071869 u2DelayCellOfst[6]=18 cells (5 PI)
8195 09:57:54.075188 u2DelayCellOfst[7]=18 cells (5 PI)
8196 09:57:54.078201 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8197 09:57:54.081726 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8198 09:57:54.084964 == TX Byte 1 ==
8199 09:57:54.088152 u2DelayCellOfst[8]=0 cells (0 PI)
8200 09:57:54.091430 u2DelayCellOfst[9]=0 cells (0 PI)
8201 09:57:54.094804 u2DelayCellOfst[10]=3 cells (1 PI)
8202 09:57:54.094954 u2DelayCellOfst[11]=3 cells (1 PI)
8203 09:57:54.098038 u2DelayCellOfst[12]=11 cells (3 PI)
8204 09:57:54.101783 u2DelayCellOfst[13]=11 cells (3 PI)
8205 09:57:54.104685 u2DelayCellOfst[14]=15 cells (4 PI)
8206 09:57:54.108085 u2DelayCellOfst[15]=11 cells (3 PI)
8207 09:57:54.114672 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8208 09:57:54.118096 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8209 09:57:54.118232 DramC Write-DBI on
8210 09:57:54.118331 ==
8211 09:57:54.121293 Dram Type= 6, Freq= 0, CH_0, rank 1
8212 09:57:54.128223 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8213 09:57:54.128380 ==
8214 09:57:54.128491
8215 09:57:54.128592
8216 09:57:54.131387 TX Vref Scan disable
8217 09:57:54.131519 == TX Byte 0 ==
8218 09:57:54.138215 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8219 09:57:54.138373 == TX Byte 1 ==
8220 09:57:54.141513 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8221 09:57:54.144812 DramC Write-DBI off
8222 09:57:54.144945
8223 09:57:54.145053 [DATLAT]
8224 09:57:54.148082 Freq=1600, CH0 RK1
8225 09:57:54.148227
8226 09:57:54.148340 DATLAT Default: 0xf
8227 09:57:54.151213 0, 0xFFFF, sum = 0
8228 09:57:54.151352 1, 0xFFFF, sum = 0
8229 09:57:54.154239 2, 0xFFFF, sum = 0
8230 09:57:54.154363 3, 0xFFFF, sum = 0
8231 09:57:54.157554 4, 0xFFFF, sum = 0
8232 09:57:54.157676 5, 0xFFFF, sum = 0
8233 09:57:54.160967 6, 0xFFFF, sum = 0
8234 09:57:54.161096 7, 0xFFFF, sum = 0
8235 09:57:54.164253 8, 0xFFFF, sum = 0
8236 09:57:54.164375 9, 0xFFFF, sum = 0
8237 09:57:54.167643 10, 0xFFFF, sum = 0
8238 09:57:54.171171 11, 0xFFFF, sum = 0
8239 09:57:54.171296 12, 0xFFFF, sum = 0
8240 09:57:54.174755 13, 0xCFFF, sum = 0
8241 09:57:54.174879 14, 0x0, sum = 1
8242 09:57:54.177658 15, 0x0, sum = 2
8243 09:57:54.177780 16, 0x0, sum = 3
8244 09:57:54.181229 17, 0x0, sum = 4
8245 09:57:54.181351 best_step = 15
8246 09:57:54.181457
8247 09:57:54.181558 ==
8248 09:57:54.184607 Dram Type= 6, Freq= 0, CH_0, rank 1
8249 09:57:54.187468 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8250 09:57:54.187595 ==
8251 09:57:54.190771 RX Vref Scan: 0
8252 09:57:54.190900
8253 09:57:54.194229 RX Vref 0 -> 0, step: 1
8254 09:57:54.194350
8255 09:57:54.194455 RX Delay 3 -> 252, step: 4
8256 09:57:54.201409 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8257 09:57:54.204386 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8258 09:57:54.207875 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8259 09:57:54.211005 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8260 09:57:54.214357 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8261 09:57:54.220947 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8262 09:57:54.224699 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8263 09:57:54.227745 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8264 09:57:54.231175 iDelay=191, Bit 8, Center 112 (55 ~ 170) 116
8265 09:57:54.234153 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8266 09:57:54.241069 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8267 09:57:54.244077 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8268 09:57:54.247823 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8269 09:57:54.250691 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8270 09:57:54.257338 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8271 09:57:54.260881 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8272 09:57:54.261032 ==
8273 09:57:54.264009 Dram Type= 6, Freq= 0, CH_0, rank 1
8274 09:57:54.267570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8275 09:57:54.267715 ==
8276 09:57:54.270854 DQS Delay:
8277 09:57:54.270985 DQS0 = 0, DQS1 = 0
8278 09:57:54.271085 DQM Delay:
8279 09:57:54.273986 DQM0 = 124, DQM1 = 118
8280 09:57:54.274122 DQ Delay:
8281 09:57:54.277294 DQ0 =124, DQ1 =126, DQ2 =122, DQ3 =122
8282 09:57:54.280648 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8283 09:57:54.283879 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
8284 09:57:54.290641 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8285 09:57:54.290800
8286 09:57:54.290904
8287 09:57:54.291002
8288 09:57:54.293696 [DramC_TX_OE_Calibration] TA2
8289 09:57:54.297463 Original DQ_B0 (3 6) =30, OEN = 27
8290 09:57:54.297592 Original DQ_B1 (3 6) =30, OEN = 27
8291 09:57:54.300372 24, 0x0, End_B0=24 End_B1=24
8292 09:57:54.303737 25, 0x0, End_B0=25 End_B1=25
8293 09:57:54.306897 26, 0x0, End_B0=26 End_B1=26
8294 09:57:54.310195 27, 0x0, End_B0=27 End_B1=27
8295 09:57:54.310327 28, 0x0, End_B0=28 End_B1=28
8296 09:57:54.313545 29, 0x0, End_B0=29 End_B1=29
8297 09:57:54.316878 30, 0x0, End_B0=30 End_B1=30
8298 09:57:54.320058 31, 0x4545, End_B0=30 End_B1=30
8299 09:57:54.323405 Byte0 end_step=30 best_step=27
8300 09:57:54.326856 Byte1 end_step=30 best_step=27
8301 09:57:54.326985 Byte0 TX OE(2T, 0.5T) = (3, 3)
8302 09:57:54.330347 Byte1 TX OE(2T, 0.5T) = (3, 3)
8303 09:57:54.330468
8304 09:57:54.330612
8305 09:57:54.339803 [DQSOSCAuto] RK1, (LSB)MR18= 0x220f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
8306 09:57:54.343110 CH0 RK1: MR19=303, MR18=220F
8307 09:57:54.346828 CH0_RK1: MR19=0x303, MR18=0x220F, DQSOSC=392, MR23=63, INC=24, DEC=16
8308 09:57:54.349753 [RxdqsGatingPostProcess] freq 1600
8309 09:57:54.356884 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8310 09:57:54.359655 best DQS0 dly(2T, 0.5T) = (1, 1)
8311 09:57:54.363619 best DQS1 dly(2T, 0.5T) = (1, 1)
8312 09:57:54.366601 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8313 09:57:54.369869 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8314 09:57:54.373046 best DQS0 dly(2T, 0.5T) = (1, 1)
8315 09:57:54.373212 best DQS1 dly(2T, 0.5T) = (1, 1)
8316 09:57:54.376346 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8317 09:57:54.379424 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8318 09:57:54.383040 Pre-setting of DQS Precalculation
8319 09:57:54.389645 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8320 09:57:54.389798 ==
8321 09:57:54.393138 Dram Type= 6, Freq= 0, CH_1, rank 0
8322 09:57:54.395931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8323 09:57:54.396042 ==
8324 09:57:54.402705 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8325 09:57:54.406499 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8326 09:57:54.409285 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8327 09:57:54.416085 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8328 09:57:54.425506 [CA 0] Center 42 (13~71) winsize 59
8329 09:57:54.429319 [CA 1] Center 42 (13~72) winsize 60
8330 09:57:54.432370 [CA 2] Center 37 (9~66) winsize 58
8331 09:57:54.435809 [CA 3] Center 37 (8~66) winsize 59
8332 09:57:54.439083 [CA 4] Center 37 (8~66) winsize 59
8333 09:57:54.442276 [CA 5] Center 36 (7~66) winsize 60
8334 09:57:54.442394
8335 09:57:54.445451 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8336 09:57:54.445571
8337 09:57:54.448796 [CATrainingPosCal] consider 1 rank data
8338 09:57:54.452112 u2DelayCellTimex100 = 258/100 ps
8339 09:57:54.458802 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8340 09:57:54.461915 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8341 09:57:54.464858 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8342 09:57:54.468309 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8343 09:57:54.471807 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8344 09:57:54.475015 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8345 09:57:54.475102
8346 09:57:54.478167 CA PerBit enable=1, Macro0, CA PI delay=36
8347 09:57:54.478247
8348 09:57:54.481480 [CBTSetCACLKResult] CA Dly = 36
8349 09:57:54.484761 CS Dly: 10 (0~41)
8350 09:57:54.488034 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8351 09:57:54.491381 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8352 09:57:54.491501 ==
8353 09:57:54.494475 Dram Type= 6, Freq= 0, CH_1, rank 1
8354 09:57:54.501440 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8355 09:57:54.501587 ==
8356 09:57:54.504862 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8357 09:57:54.511414 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8358 09:57:54.514626 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8359 09:57:54.521164 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8360 09:57:54.529265 [CA 0] Center 41 (12~71) winsize 60
8361 09:57:54.531927 [CA 1] Center 42 (12~72) winsize 61
8362 09:57:54.535309 [CA 2] Center 37 (8~67) winsize 60
8363 09:57:54.538728 [CA 3] Center 36 (7~66) winsize 60
8364 09:57:54.541858 [CA 4] Center 37 (7~67) winsize 61
8365 09:57:54.545582 [CA 5] Center 36 (6~66) winsize 61
8366 09:57:54.545668
8367 09:57:54.548730 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8368 09:57:54.548807
8369 09:57:54.551921 [CATrainingPosCal] consider 2 rank data
8370 09:57:54.555093 u2DelayCellTimex100 = 258/100 ps
8371 09:57:54.561672 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8372 09:57:54.564909 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8373 09:57:54.568187 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8374 09:57:54.571850 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8375 09:57:54.574779 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8376 09:57:54.578049 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8377 09:57:54.578133
8378 09:57:54.581872 CA PerBit enable=1, Macro0, CA PI delay=36
8379 09:57:54.581983
8380 09:57:54.584854 [CBTSetCACLKResult] CA Dly = 36
8381 09:57:54.588104 CS Dly: 11 (0~43)
8382 09:57:54.591550 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8383 09:57:54.594588 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8384 09:57:54.594712
8385 09:57:54.597995 ----->DramcWriteLeveling(PI) begin...
8386 09:57:54.598096 ==
8387 09:57:54.601475 Dram Type= 6, Freq= 0, CH_1, rank 0
8388 09:57:54.607904 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8389 09:57:54.608079 ==
8390 09:57:54.611808 Write leveling (Byte 0): 24 => 24
8391 09:57:54.614460 Write leveling (Byte 1): 28 => 28
8392 09:57:54.614604 DramcWriteLeveling(PI) end<-----
8393 09:57:54.614716
8394 09:57:54.618080 ==
8395 09:57:54.621353 Dram Type= 6, Freq= 0, CH_1, rank 0
8396 09:57:54.624611 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8397 09:57:54.624742 ==
8398 09:57:54.627967 [Gating] SW mode calibration
8399 09:57:54.634826 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8400 09:57:54.637958 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8401 09:57:54.644806 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8402 09:57:54.647626 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8403 09:57:54.651342 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8404 09:57:54.657623 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 09:57:54.661212 1 4 16 | B1->B0 | 3232 302f | 0 1 | (0 0) (0 0)
8406 09:57:54.664129 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8407 09:57:54.670820 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8408 09:57:54.674146 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8409 09:57:54.677999 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8410 09:57:54.684474 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8411 09:57:54.687902 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8412 09:57:54.691047 1 5 12 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)
8413 09:57:54.697276 1 5 16 | B1->B0 | 2424 2929 | 0 1 | (1 0) (1 0)
8414 09:57:54.701006 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8415 09:57:54.704468 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8416 09:57:54.710740 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8417 09:57:54.713955 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8418 09:57:54.717463 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8419 09:57:54.724080 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8420 09:57:54.727044 1 6 12 | B1->B0 | 2a2a 2424 | 0 0 | (0 0) (0 0)
8421 09:57:54.730727 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8422 09:57:54.737488 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8423 09:57:54.740831 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8424 09:57:54.743697 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8425 09:57:54.750830 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8426 09:57:54.753712 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8427 09:57:54.757196 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8428 09:57:54.763847 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8429 09:57:54.767022 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8430 09:57:54.770259 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8431 09:57:54.773870 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 09:57:54.780053 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 09:57:54.783867 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 09:57:54.786988 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 09:57:54.793780 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 09:57:54.796704 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 09:57:54.800053 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 09:57:54.806549 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 09:57:54.810081 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 09:57:54.813464 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 09:57:54.820082 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 09:57:54.823461 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 09:57:54.826884 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 09:57:54.833724 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8445 09:57:54.837042 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8446 09:57:54.840536 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8447 09:57:54.843416 Total UI for P1: 0, mck2ui 16
8448 09:57:54.847007 best dqsien dly found for B0: ( 1, 9, 14)
8449 09:57:54.850003 Total UI for P1: 0, mck2ui 16
8450 09:57:54.853631 best dqsien dly found for B1: ( 1, 9, 16)
8451 09:57:54.856671 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8452 09:57:54.860240 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8453 09:57:54.860334
8454 09:57:54.867056 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8455 09:57:54.870278 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8456 09:57:54.873216 [Gating] SW calibration Done
8457 09:57:54.873346 ==
8458 09:57:54.876670 Dram Type= 6, Freq= 0, CH_1, rank 0
8459 09:57:54.880108 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8460 09:57:54.880238 ==
8461 09:57:54.880345 RX Vref Scan: 0
8462 09:57:54.880451
8463 09:57:54.883225 RX Vref 0 -> 0, step: 1
8464 09:57:54.883379
8465 09:57:54.886672 RX Delay 0 -> 252, step: 8
8466 09:57:54.889856 iDelay=208, Bit 0, Center 135 (80 ~ 191) 112
8467 09:57:54.893281 iDelay=208, Bit 1, Center 127 (64 ~ 191) 128
8468 09:57:54.896424 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8469 09:57:54.903023 iDelay=208, Bit 3, Center 131 (72 ~ 191) 120
8470 09:57:54.906358 iDelay=208, Bit 4, Center 127 (72 ~ 183) 112
8471 09:57:54.909589 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8472 09:57:54.912981 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8473 09:57:54.916516 iDelay=208, Bit 7, Center 131 (72 ~ 191) 120
8474 09:57:54.923058 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8475 09:57:54.926455 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8476 09:57:54.929797 iDelay=208, Bit 10, Center 123 (72 ~ 175) 104
8477 09:57:54.933073 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8478 09:57:54.936387 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8479 09:57:54.943259 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8480 09:57:54.945985 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8481 09:57:54.949487 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8482 09:57:54.949579 ==
8483 09:57:54.952976 Dram Type= 6, Freq= 0, CH_1, rank 0
8484 09:57:54.959525 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8485 09:57:54.959662 ==
8486 09:57:54.959774 DQS Delay:
8487 09:57:54.959882 DQS0 = 0, DQS1 = 0
8488 09:57:54.962929 DQM Delay:
8489 09:57:54.963051 DQM0 = 132, DQM1 = 126
8490 09:57:54.966155 DQ Delay:
8491 09:57:54.969534 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8492 09:57:54.972703 DQ4 =127, DQ5 =147, DQ6 =143, DQ7 =131
8493 09:57:54.975833 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8494 09:57:54.979279 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8495 09:57:54.979408
8496 09:57:54.979519
8497 09:57:54.979618 ==
8498 09:57:54.982370 Dram Type= 6, Freq= 0, CH_1, rank 0
8499 09:57:54.985648 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8500 09:57:54.989052 ==
8501 09:57:54.989213
8502 09:57:54.989322
8503 09:57:54.989427 TX Vref Scan disable
8504 09:57:54.992265 == TX Byte 0 ==
8505 09:57:54.995561 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8506 09:57:54.998688 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8507 09:57:55.002175 == TX Byte 1 ==
8508 09:57:55.005812 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8509 09:57:55.009215 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8510 09:57:55.012503 ==
8511 09:57:55.012695 Dram Type= 6, Freq= 0, CH_1, rank 0
8512 09:57:55.019001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8513 09:57:55.019157 ==
8514 09:57:55.030742
8515 09:57:55.034079 TX Vref early break, caculate TX vref
8516 09:57:55.037457 TX Vref=16, minBit 11, minWin=20, winSum=357
8517 09:57:55.040738 TX Vref=18, minBit 11, minWin=22, winSum=370
8518 09:57:55.044182 TX Vref=20, minBit 11, minWin=21, winSum=378
8519 09:57:55.047550 TX Vref=22, minBit 1, minWin=23, winSum=391
8520 09:57:55.054079 TX Vref=24, minBit 11, minWin=22, winSum=401
8521 09:57:55.057621 TX Vref=26, minBit 1, minWin=25, winSum=412
8522 09:57:55.060908 TX Vref=28, minBit 5, minWin=25, winSum=417
8523 09:57:55.063741 TX Vref=30, minBit 1, minWin=24, winSum=410
8524 09:57:55.067141 TX Vref=32, minBit 0, minWin=24, winSum=407
8525 09:57:55.070631 TX Vref=34, minBit 0, minWin=23, winSum=390
8526 09:57:55.077111 [TxChooseVref] Worse bit 5, Min win 25, Win sum 417, Final Vref 28
8527 09:57:55.077215
8528 09:57:55.081032 Final TX Range 0 Vref 28
8529 09:57:55.081116
8530 09:57:55.081188 ==
8531 09:57:55.083997 Dram Type= 6, Freq= 0, CH_1, rank 0
8532 09:57:55.087229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8533 09:57:55.087335 ==
8534 09:57:55.087420
8535 09:57:55.087481
8536 09:57:55.090457 TX Vref Scan disable
8537 09:57:55.097499 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8538 09:57:55.097600 == TX Byte 0 ==
8539 09:57:55.100680 u2DelayCellOfst[0]=22 cells (6 PI)
8540 09:57:55.104073 u2DelayCellOfst[1]=18 cells (5 PI)
8541 09:57:55.107218 u2DelayCellOfst[2]=0 cells (0 PI)
8542 09:57:55.110644 u2DelayCellOfst[3]=7 cells (2 PI)
8543 09:57:55.113893 u2DelayCellOfst[4]=11 cells (3 PI)
8544 09:57:55.117113 u2DelayCellOfst[5]=26 cells (7 PI)
8545 09:57:55.120287 u2DelayCellOfst[6]=22 cells (6 PI)
8546 09:57:55.123707 u2DelayCellOfst[7]=7 cells (2 PI)
8547 09:57:55.126962 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8548 09:57:55.130487 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8549 09:57:55.133631 == TX Byte 1 ==
8550 09:57:55.137060 u2DelayCellOfst[8]=0 cells (0 PI)
8551 09:57:55.137206 u2DelayCellOfst[9]=7 cells (2 PI)
8552 09:57:55.140232 u2DelayCellOfst[10]=15 cells (4 PI)
8553 09:57:55.143505 u2DelayCellOfst[11]=11 cells (3 PI)
8554 09:57:55.146829 u2DelayCellOfst[12]=18 cells (5 PI)
8555 09:57:55.150635 u2DelayCellOfst[13]=22 cells (6 PI)
8556 09:57:55.153481 u2DelayCellOfst[14]=22 cells (6 PI)
8557 09:57:55.156961 u2DelayCellOfst[15]=22 cells (6 PI)
8558 09:57:55.160241 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8559 09:57:55.167059 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8560 09:57:55.167182 DramC Write-DBI on
8561 09:57:55.167265 ==
8562 09:57:55.169948 Dram Type= 6, Freq= 0, CH_1, rank 0
8563 09:57:55.176656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8564 09:57:55.176842 ==
8565 09:57:55.176979
8566 09:57:55.177101
8567 09:57:55.177223 TX Vref Scan disable
8568 09:57:55.180926 == TX Byte 0 ==
8569 09:57:55.183749 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8570 09:57:55.187082 == TX Byte 1 ==
8571 09:57:55.190527 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8572 09:57:55.193800 DramC Write-DBI off
8573 09:57:55.193903
8574 09:57:55.193970 [DATLAT]
8575 09:57:55.194032 Freq=1600, CH1 RK0
8576 09:57:55.194091
8577 09:57:55.197063 DATLAT Default: 0xf
8578 09:57:55.197154 0, 0xFFFF, sum = 0
8579 09:57:55.200398 1, 0xFFFF, sum = 0
8580 09:57:55.200492 2, 0xFFFF, sum = 0
8581 09:57:55.203727 3, 0xFFFF, sum = 0
8582 09:57:55.207609 4, 0xFFFF, sum = 0
8583 09:57:55.207781 5, 0xFFFF, sum = 0
8584 09:57:55.210972 6, 0xFFFF, sum = 0
8585 09:57:55.211121 7, 0xFFFF, sum = 0
8586 09:57:55.213850 8, 0xFFFF, sum = 0
8587 09:57:55.213970 9, 0xFFFF, sum = 0
8588 09:57:55.217686 10, 0xFFFF, sum = 0
8589 09:57:55.217781 11, 0xFFFF, sum = 0
8590 09:57:55.224290 12, 0xFFFF, sum = 0
8591 09:57:55.224401 13, 0x8FFF, sum = 0
8592 09:57:55.224662 14, 0x0, sum = 1
8593 09:57:55.224735 15, 0x0, sum = 2
8594 09:57:55.227139 16, 0x0, sum = 3
8595 09:57:55.227289 17, 0x0, sum = 4
8596 09:57:55.230549 best_step = 15
8597 09:57:55.230706
8598 09:57:55.230838 ==
8599 09:57:55.234021 Dram Type= 6, Freq= 0, CH_1, rank 0
8600 09:57:55.237681 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8601 09:57:55.237771 ==
8602 09:57:55.237838 RX Vref Scan: 1
8603 09:57:55.237918
8604 09:57:55.240726 Set Vref Range= 24 -> 127
8605 09:57:55.240804
8606 09:57:55.243906 RX Vref 24 -> 127, step: 1
8607 09:57:55.244002
8608 09:57:55.247271 RX Delay 11 -> 252, step: 4
8609 09:57:55.247409
8610 09:57:55.250225 Set Vref, RX VrefLevel [Byte0]: 24
8611 09:57:55.253619 [Byte1]: 24
8612 09:57:55.253766
8613 09:57:55.256922 Set Vref, RX VrefLevel [Byte0]: 25
8614 09:57:55.260401 [Byte1]: 25
8615 09:57:55.260550
8616 09:57:55.263646 Set Vref, RX VrefLevel [Byte0]: 26
8617 09:57:55.266969 [Byte1]: 26
8618 09:57:55.270842
8619 09:57:55.270987 Set Vref, RX VrefLevel [Byte0]: 27
8620 09:57:55.274313 [Byte1]: 27
8621 09:57:55.278768
8622 09:57:55.278902 Set Vref, RX VrefLevel [Byte0]: 28
8623 09:57:55.282026 [Byte1]: 28
8624 09:57:55.286215
8625 09:57:55.286305 Set Vref, RX VrefLevel [Byte0]: 29
8626 09:57:55.289434 [Byte1]: 29
8627 09:57:55.293906
8628 09:57:55.294017 Set Vref, RX VrefLevel [Byte0]: 30
8629 09:57:55.297417 [Byte1]: 30
8630 09:57:55.301189
8631 09:57:55.301299 Set Vref, RX VrefLevel [Byte0]: 31
8632 09:57:55.304986 [Byte1]: 31
8633 09:57:55.308978
8634 09:57:55.309089 Set Vref, RX VrefLevel [Byte0]: 32
8635 09:57:55.312194 [Byte1]: 32
8636 09:57:55.316866
8637 09:57:55.316961 Set Vref, RX VrefLevel [Byte0]: 33
8638 09:57:55.320193 [Byte1]: 33
8639 09:57:55.324066
8640 09:57:55.324175 Set Vref, RX VrefLevel [Byte0]: 34
8641 09:57:55.327396 [Byte1]: 34
8642 09:57:55.332015
8643 09:57:55.332167 Set Vref, RX VrefLevel [Byte0]: 35
8644 09:57:55.335282 [Byte1]: 35
8645 09:57:55.339858
8646 09:57:55.340007 Set Vref, RX VrefLevel [Byte0]: 36
8647 09:57:55.342805 [Byte1]: 36
8648 09:57:55.347413
8649 09:57:55.347581 Set Vref, RX VrefLevel [Byte0]: 37
8650 09:57:55.350426 [Byte1]: 37
8651 09:57:55.354621
8652 09:57:55.354777 Set Vref, RX VrefLevel [Byte0]: 38
8653 09:57:55.358021 [Byte1]: 38
8654 09:57:55.362343
8655 09:57:55.362501 Set Vref, RX VrefLevel [Byte0]: 39
8656 09:57:55.365457 [Byte1]: 39
8657 09:57:55.369848
8658 09:57:55.370015 Set Vref, RX VrefLevel [Byte0]: 40
8659 09:57:55.373260 [Byte1]: 40
8660 09:57:55.377450
8661 09:57:55.377620 Set Vref, RX VrefLevel [Byte0]: 41
8662 09:57:55.380855 [Byte1]: 41
8663 09:57:55.384997
8664 09:57:55.385103 Set Vref, RX VrefLevel [Byte0]: 42
8665 09:57:55.388369 [Byte1]: 42
8666 09:57:55.392885
8667 09:57:55.392982 Set Vref, RX VrefLevel [Byte0]: 43
8668 09:57:55.396277 [Byte1]: 43
8669 09:57:55.400160
8670 09:57:55.400271 Set Vref, RX VrefLevel [Byte0]: 44
8671 09:57:55.404081 [Byte1]: 44
8672 09:57:55.408292
8673 09:57:55.408382 Set Vref, RX VrefLevel [Byte0]: 45
8674 09:57:55.411419 [Byte1]: 45
8675 09:57:55.415968
8676 09:57:55.416095 Set Vref, RX VrefLevel [Byte0]: 46
8677 09:57:55.419189 [Byte1]: 46
8678 09:57:55.423347
8679 09:57:55.423457 Set Vref, RX VrefLevel [Byte0]: 47
8680 09:57:55.426676 [Byte1]: 47
8681 09:57:55.430633
8682 09:57:55.430758 Set Vref, RX VrefLevel [Byte0]: 48
8683 09:57:55.434440 [Byte1]: 48
8684 09:57:55.438438
8685 09:57:55.438523 Set Vref, RX VrefLevel [Byte0]: 49
8686 09:57:55.441747 [Byte1]: 49
8687 09:57:55.445970
8688 09:57:55.446127 Set Vref, RX VrefLevel [Byte0]: 50
8689 09:57:55.449368 [Byte1]: 50
8690 09:57:55.453745
8691 09:57:55.453845 Set Vref, RX VrefLevel [Byte0]: 51
8692 09:57:55.456915 [Byte1]: 51
8693 09:57:55.461433
8694 09:57:55.461537 Set Vref, RX VrefLevel [Byte0]: 52
8695 09:57:55.464361 [Byte1]: 52
8696 09:57:55.469145
8697 09:57:55.469309 Set Vref, RX VrefLevel [Byte0]: 53
8698 09:57:55.472290 [Byte1]: 53
8699 09:57:55.476489
8700 09:57:55.476642 Set Vref, RX VrefLevel [Byte0]: 54
8701 09:57:55.479716 [Byte1]: 54
8702 09:57:55.484161
8703 09:57:55.484314 Set Vref, RX VrefLevel [Byte0]: 55
8704 09:57:55.487214 [Byte1]: 55
8705 09:57:55.491617
8706 09:57:55.491762 Set Vref, RX VrefLevel [Byte0]: 56
8707 09:57:55.494887 [Byte1]: 56
8708 09:57:55.499131
8709 09:57:55.499275 Set Vref, RX VrefLevel [Byte0]: 57
8710 09:57:55.502551 [Byte1]: 57
8711 09:57:55.507081
8712 09:57:55.507227 Set Vref, RX VrefLevel [Byte0]: 58
8713 09:57:55.510092 [Byte1]: 58
8714 09:57:55.515003
8715 09:57:55.515190 Set Vref, RX VrefLevel [Byte0]: 59
8716 09:57:55.517829 [Byte1]: 59
8717 09:57:55.521918
8718 09:57:55.522028 Set Vref, RX VrefLevel [Byte0]: 60
8719 09:57:55.525730 [Byte1]: 60
8720 09:57:55.529743
8721 09:57:55.529852 Set Vref, RX VrefLevel [Byte0]: 61
8722 09:57:55.533247 [Byte1]: 61
8723 09:57:55.537667
8724 09:57:55.537778 Set Vref, RX VrefLevel [Byte0]: 62
8725 09:57:55.540919 [Byte1]: 62
8726 09:57:55.545467
8727 09:57:55.545593 Set Vref, RX VrefLevel [Byte0]: 63
8728 09:57:55.548345 [Byte1]: 63
8729 09:57:55.552875
8730 09:57:55.552999 Set Vref, RX VrefLevel [Byte0]: 64
8731 09:57:55.556240 [Byte1]: 64
8732 09:57:55.560535
8733 09:57:55.560730 Set Vref, RX VrefLevel [Byte0]: 65
8734 09:57:55.563713 [Byte1]: 65
8735 09:57:55.567693
8736 09:57:55.567872 Set Vref, RX VrefLevel [Byte0]: 66
8737 09:57:55.571513 [Byte1]: 66
8738 09:57:55.575518
8739 09:57:55.575702 Set Vref, RX VrefLevel [Byte0]: 67
8740 09:57:55.578726 [Byte1]: 67
8741 09:57:55.582992
8742 09:57:55.583184 Set Vref, RX VrefLevel [Byte0]: 68
8743 09:57:55.586230 [Byte1]: 68
8744 09:57:55.590720
8745 09:57:55.590903 Set Vref, RX VrefLevel [Byte0]: 69
8746 09:57:55.594137 [Byte1]: 69
8747 09:57:55.598253
8748 09:57:55.598427 Set Vref, RX VrefLevel [Byte0]: 70
8749 09:57:55.601784 [Byte1]: 70
8750 09:57:55.606126
8751 09:57:55.606253 Set Vref, RX VrefLevel [Byte0]: 71
8752 09:57:55.609300 [Byte1]: 71
8753 09:57:55.613303
8754 09:57:55.613449 Final RX Vref Byte 0 = 58 to rank0
8755 09:57:55.616773 Final RX Vref Byte 1 = 52 to rank0
8756 09:57:55.620478 Final RX Vref Byte 0 = 58 to rank1
8757 09:57:55.623830 Final RX Vref Byte 1 = 52 to rank1==
8758 09:57:55.626583 Dram Type= 6, Freq= 0, CH_1, rank 0
8759 09:57:55.633399 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8760 09:57:55.633572 ==
8761 09:57:55.633679 DQS Delay:
8762 09:57:55.633781 DQS0 = 0, DQS1 = 0
8763 09:57:55.636599 DQM Delay:
8764 09:57:55.636748 DQM0 = 130, DQM1 = 123
8765 09:57:55.640006 DQ Delay:
8766 09:57:55.643374 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =126
8767 09:57:55.646224 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =128
8768 09:57:55.649617 DQ8 =108, DQ9 =114, DQ10 =122, DQ11 =116
8769 09:57:55.652931 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8770 09:57:55.653108
8771 09:57:55.653241
8772 09:57:55.653369
8773 09:57:55.656310 [DramC_TX_OE_Calibration] TA2
8774 09:57:55.659665 Original DQ_B0 (3 6) =30, OEN = 27
8775 09:57:55.663006 Original DQ_B1 (3 6) =30, OEN = 27
8776 09:57:55.666536 24, 0x0, End_B0=24 End_B1=24
8777 09:57:55.666702 25, 0x0, End_B0=25 End_B1=25
8778 09:57:55.669740 26, 0x0, End_B0=26 End_B1=26
8779 09:57:55.672859 27, 0x0, End_B0=27 End_B1=27
8780 09:57:55.676419 28, 0x0, End_B0=28 End_B1=28
8781 09:57:55.679614 29, 0x0, End_B0=29 End_B1=29
8782 09:57:55.679741 30, 0x0, End_B0=30 End_B1=30
8783 09:57:55.683139 31, 0x4141, End_B0=30 End_B1=30
8784 09:57:55.686177 Byte0 end_step=30 best_step=27
8785 09:57:55.689248 Byte1 end_step=30 best_step=27
8786 09:57:55.692784 Byte0 TX OE(2T, 0.5T) = (3, 3)
8787 09:57:55.696368 Byte1 TX OE(2T, 0.5T) = (3, 3)
8788 09:57:55.696571
8789 09:57:55.696699
8790 09:57:55.702489 [DQSOSCAuto] RK0, (LSB)MR18= 0x80c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
8791 09:57:55.706233 CH1 RK0: MR19=303, MR18=80C
8792 09:57:55.712875 CH1_RK0: MR19=0x303, MR18=0x80C, DQSOSC=403, MR23=63, INC=22, DEC=15
8793 09:57:55.713033
8794 09:57:55.715823 ----->DramcWriteLeveling(PI) begin...
8795 09:57:55.715981 ==
8796 09:57:55.719067 Dram Type= 6, Freq= 0, CH_1, rank 1
8797 09:57:55.722744 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8798 09:57:55.722882 ==
8799 09:57:55.725626 Write leveling (Byte 0): 25 => 25
8800 09:57:55.728939 Write leveling (Byte 1): 27 => 27
8801 09:57:55.732576 DramcWriteLeveling(PI) end<-----
8802 09:57:55.732775
8803 09:57:55.732903 ==
8804 09:57:55.735494 Dram Type= 6, Freq= 0, CH_1, rank 1
8805 09:57:55.739441 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8806 09:57:55.739638 ==
8807 09:57:55.742667 [Gating] SW mode calibration
8808 09:57:55.748930 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8809 09:57:55.755824 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8810 09:57:55.759002 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 09:57:55.765734 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 09:57:55.768540 1 4 8 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
8813 09:57:55.771876 1 4 12 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
8814 09:57:55.778551 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8815 09:57:55.781956 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8816 09:57:55.785366 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8817 09:57:55.791777 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8818 09:57:55.795165 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8819 09:57:55.798788 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8820 09:57:55.804922 1 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
8821 09:57:55.808386 1 5 12 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
8822 09:57:55.811838 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8823 09:57:55.818046 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8824 09:57:55.821806 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8825 09:57:55.824905 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8826 09:57:55.831884 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8827 09:57:55.834915 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8828 09:57:55.838122 1 6 8 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
8829 09:57:55.844738 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8830 09:57:55.848000 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8831 09:57:55.851424 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8832 09:57:55.858289 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8833 09:57:55.861474 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8834 09:57:55.864901 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8835 09:57:55.871177 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8836 09:57:55.874635 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8837 09:57:55.877904 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8838 09:57:55.884641 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8839 09:57:55.887976 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 09:57:55.891069 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 09:57:55.897765 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 09:57:55.900756 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 09:57:55.903969 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 09:57:55.910593 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 09:57:55.914215 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 09:57:55.917276 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 09:57:55.924028 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 09:57:55.927226 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 09:57:55.930490 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 09:57:55.933775 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 09:57:55.940778 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 09:57:55.944159 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8853 09:57:55.947422 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8854 09:57:55.950619 Total UI for P1: 0, mck2ui 16
8855 09:57:55.953860 best dqsien dly found for B0: ( 1, 9, 8)
8856 09:57:55.960353 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8857 09:57:55.963611 Total UI for P1: 0, mck2ui 16
8858 09:57:55.967133 best dqsien dly found for B1: ( 1, 9, 10)
8859 09:57:55.970132 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8860 09:57:55.974028 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8861 09:57:55.974177
8862 09:57:55.976861 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8863 09:57:55.980347 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8864 09:57:55.983404 [Gating] SW calibration Done
8865 09:57:55.983539 ==
8866 09:57:55.986958 Dram Type= 6, Freq= 0, CH_1, rank 1
8867 09:57:55.989948 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8868 09:57:55.990131 ==
8869 09:57:55.993531 RX Vref Scan: 0
8870 09:57:55.993711
8871 09:57:55.996724 RX Vref 0 -> 0, step: 1
8872 09:57:55.996890
8873 09:57:55.996990 RX Delay 0 -> 252, step: 8
8874 09:57:56.003186 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8875 09:57:56.006582 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8876 09:57:56.010130 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8877 09:57:56.013347 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8878 09:57:56.016697 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8879 09:57:56.023324 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8880 09:57:56.026547 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8881 09:57:56.030301 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8882 09:57:56.033086 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8883 09:57:56.036447 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8884 09:57:56.042941 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8885 09:57:56.046533 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8886 09:57:56.049581 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8887 09:57:56.052873 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8888 09:57:56.056453 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8889 09:57:56.062840 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8890 09:57:56.063059 ==
8891 09:57:56.066457 Dram Type= 6, Freq= 0, CH_1, rank 1
8892 09:57:56.069769 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8893 09:57:56.069968 ==
8894 09:57:56.070114 DQS Delay:
8895 09:57:56.072746 DQS0 = 0, DQS1 = 0
8896 09:57:56.072861 DQM Delay:
8897 09:57:56.076573 DQM0 = 129, DQM1 = 128
8898 09:57:56.076707 DQ Delay:
8899 09:57:56.079500 DQ0 =135, DQ1 =127, DQ2 =115, DQ3 =123
8900 09:57:56.082766 DQ4 =127, DQ5 =139, DQ6 =139, DQ7 =127
8901 09:57:56.086196 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8902 09:57:56.089424 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =139
8903 09:57:56.092803
8904 09:57:56.093003
8905 09:57:56.093138 ==
8906 09:57:56.096212 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 09:57:56.099363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 09:57:56.099548 ==
8909 09:57:56.099682
8910 09:57:56.099804
8911 09:57:56.102875 TX Vref Scan disable
8912 09:57:56.103058 == TX Byte 0 ==
8913 09:57:56.109625 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8914 09:57:56.112679 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8915 09:57:56.112882 == TX Byte 1 ==
8916 09:57:56.119072 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8917 09:57:56.123011 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8918 09:57:56.123237 ==
8919 09:57:56.125691 Dram Type= 6, Freq= 0, CH_1, rank 1
8920 09:57:56.129422 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8921 09:57:56.129638 ==
8922 09:57:56.143741
8923 09:57:56.146973 TX Vref early break, caculate TX vref
8924 09:57:56.150368 TX Vref=16, minBit 0, minWin=22, winSum=385
8925 09:57:56.153829 TX Vref=18, minBit 0, minWin=24, winSum=396
8926 09:57:56.157022 TX Vref=20, minBit 0, minWin=24, winSum=407
8927 09:57:56.160171 TX Vref=22, minBit 0, minWin=24, winSum=408
8928 09:57:56.163363 TX Vref=24, minBit 0, minWin=24, winSum=422
8929 09:57:56.170332 TX Vref=26, minBit 5, minWin=24, winSum=422
8930 09:57:56.173679 TX Vref=28, minBit 0, minWin=26, winSum=427
8931 09:57:56.176904 TX Vref=30, minBit 1, minWin=25, winSum=423
8932 09:57:56.180738 TX Vref=32, minBit 1, minWin=24, winSum=411
8933 09:57:56.183740 TX Vref=34, minBit 5, minWin=23, winSum=407
8934 09:57:56.186926 TX Vref=36, minBit 0, minWin=23, winSum=397
8935 09:57:56.193561 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 28
8936 09:57:56.193706
8937 09:57:56.196922 Final TX Range 0 Vref 28
8938 09:57:56.197041
8939 09:57:56.197135 ==
8940 09:57:56.200594 Dram Type= 6, Freq= 0, CH_1, rank 1
8941 09:57:56.203878 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8942 09:57:56.204094 ==
8943 09:57:56.204254
8944 09:57:56.204375
8945 09:57:56.206773 TX Vref Scan disable
8946 09:57:56.213295 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8947 09:57:56.213518 == TX Byte 0 ==
8948 09:57:56.216890 u2DelayCellOfst[0]=18 cells (5 PI)
8949 09:57:56.219833 u2DelayCellOfst[1]=15 cells (4 PI)
8950 09:57:56.223189 u2DelayCellOfst[2]=0 cells (0 PI)
8951 09:57:56.226693 u2DelayCellOfst[3]=7 cells (2 PI)
8952 09:57:56.230297 u2DelayCellOfst[4]=11 cells (3 PI)
8953 09:57:56.233099 u2DelayCellOfst[5]=22 cells (6 PI)
8954 09:57:56.236818 u2DelayCellOfst[6]=22 cells (6 PI)
8955 09:57:56.239722 u2DelayCellOfst[7]=11 cells (3 PI)
8956 09:57:56.242999 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8957 09:57:56.246475 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8958 09:57:56.250054 == TX Byte 1 ==
8959 09:57:56.253617 u2DelayCellOfst[8]=0 cells (0 PI)
8960 09:57:56.256300 u2DelayCellOfst[9]=7 cells (2 PI)
8961 09:57:56.259685 u2DelayCellOfst[10]=15 cells (4 PI)
8962 09:57:56.259907 u2DelayCellOfst[11]=7 cells (2 PI)
8963 09:57:56.263143 u2DelayCellOfst[12]=15 cells (4 PI)
8964 09:57:56.266356 u2DelayCellOfst[13]=18 cells (5 PI)
8965 09:57:56.269637 u2DelayCellOfst[14]=18 cells (5 PI)
8966 09:57:56.272930 u2DelayCellOfst[15]=18 cells (5 PI)
8967 09:57:56.279624 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8968 09:57:56.282862 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8969 09:57:56.283017 DramC Write-DBI on
8970 09:57:56.286233 ==
8971 09:57:56.286370 Dram Type= 6, Freq= 0, CH_1, rank 1
8972 09:57:56.292970 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8973 09:57:56.293112 ==
8974 09:57:56.293186
8975 09:57:56.293249
8976 09:57:56.296230 TX Vref Scan disable
8977 09:57:56.296366 == TX Byte 0 ==
8978 09:57:56.302653 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8979 09:57:56.302844 == TX Byte 1 ==
8980 09:57:56.306386 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8981 09:57:56.309164 DramC Write-DBI off
8982 09:57:56.309360
8983 09:57:56.309477 [DATLAT]
8984 09:57:56.312748 Freq=1600, CH1 RK1
8985 09:57:56.312928
8986 09:57:56.313040 DATLAT Default: 0xf
8987 09:57:56.315864 0, 0xFFFF, sum = 0
8988 09:57:56.316030 1, 0xFFFF, sum = 0
8989 09:57:56.319324 2, 0xFFFF, sum = 0
8990 09:57:56.319499 3, 0xFFFF, sum = 0
8991 09:57:56.322520 4, 0xFFFF, sum = 0
8992 09:57:56.322651 5, 0xFFFF, sum = 0
8993 09:57:56.326015 6, 0xFFFF, sum = 0
8994 09:57:56.326181 7, 0xFFFF, sum = 0
8995 09:57:56.329141 8, 0xFFFF, sum = 0
8996 09:57:56.329344 9, 0xFFFF, sum = 0
8997 09:57:56.332641 10, 0xFFFF, sum = 0
8998 09:57:56.335761 11, 0xFFFF, sum = 0
8999 09:57:56.335903 12, 0xFFFF, sum = 0
9000 09:57:56.339263 13, 0x8FFF, sum = 0
9001 09:57:56.339481 14, 0x0, sum = 1
9002 09:57:56.342211 15, 0x0, sum = 2
9003 09:57:56.342414 16, 0x0, sum = 3
9004 09:57:56.345909 17, 0x0, sum = 4
9005 09:57:56.346130 best_step = 15
9006 09:57:56.346263
9007 09:57:56.346390 ==
9008 09:57:56.348871 Dram Type= 6, Freq= 0, CH_1, rank 1
9009 09:57:56.352522 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9010 09:57:56.352734 ==
9011 09:57:56.355770 RX Vref Scan: 0
9012 09:57:56.355984
9013 09:57:56.359005 RX Vref 0 -> 0, step: 1
9014 09:57:56.359196
9015 09:57:56.359330 RX Delay 3 -> 252, step: 4
9016 09:57:56.365943 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
9017 09:57:56.369260 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
9018 09:57:56.373155 iDelay=195, Bit 2, Center 114 (59 ~ 170) 112
9019 09:57:56.376479 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
9020 09:57:56.379499 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
9021 09:57:56.385905 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
9022 09:57:56.389670 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
9023 09:57:56.392771 iDelay=195, Bit 7, Center 124 (67 ~ 182) 116
9024 09:57:56.395980 iDelay=195, Bit 8, Center 110 (55 ~ 166) 112
9025 09:57:56.399404 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9026 09:57:56.406035 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9027 09:57:56.409231 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9028 09:57:56.412512 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9029 09:57:56.415928 iDelay=195, Bit 13, Center 134 (79 ~ 190) 112
9030 09:57:56.422524 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9031 09:57:56.425978 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9032 09:57:56.426185 ==
9033 09:57:56.428782 Dram Type= 6, Freq= 0, CH_1, rank 1
9034 09:57:56.432466 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9035 09:57:56.432665 ==
9036 09:57:56.435327 DQS Delay:
9037 09:57:56.435488 DQS0 = 0, DQS1 = 0
9038 09:57:56.435618 DQM Delay:
9039 09:57:56.438550 DQM0 = 127, DQM1 = 125
9040 09:57:56.438692 DQ Delay:
9041 09:57:56.442042 DQ0 =132, DQ1 =126, DQ2 =114, DQ3 =126
9042 09:57:56.445391 DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =124
9043 09:57:56.448846 DQ8 =110, DQ9 =112, DQ10 =128, DQ11 =120
9044 09:57:56.455478 DQ12 =132, DQ13 =134, DQ14 =130, DQ15 =136
9045 09:57:56.455674
9046 09:57:56.455810
9047 09:57:56.455932
9048 09:57:56.458824 [DramC_TX_OE_Calibration] TA2
9049 09:57:56.461985 Original DQ_B0 (3 6) =30, OEN = 27
9050 09:57:56.462160 Original DQ_B1 (3 6) =30, OEN = 27
9051 09:57:56.465480 24, 0x0, End_B0=24 End_B1=24
9052 09:57:56.468752 25, 0x0, End_B0=25 End_B1=25
9053 09:57:56.471693 26, 0x0, End_B0=26 End_B1=26
9054 09:57:56.475473 27, 0x0, End_B0=27 End_B1=27
9055 09:57:56.475699 28, 0x0, End_B0=28 End_B1=28
9056 09:57:56.478911 29, 0x0, End_B0=29 End_B1=29
9057 09:57:56.481718 30, 0x0, End_B0=30 End_B1=30
9058 09:57:56.485076 31, 0x4141, End_B0=30 End_B1=30
9059 09:57:56.488344 Byte0 end_step=30 best_step=27
9060 09:57:56.488538 Byte1 end_step=30 best_step=27
9061 09:57:56.491512 Byte0 TX OE(2T, 0.5T) = (3, 3)
9062 09:57:56.495364 Byte1 TX OE(2T, 0.5T) = (3, 3)
9063 09:57:56.495564
9064 09:57:56.495695
9065 09:57:56.504988 [DQSOSCAuto] RK1, (LSB)MR18= 0x121e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
9066 09:57:56.508068 CH1 RK1: MR19=303, MR18=121E
9067 09:57:56.511876 CH1_RK1: MR19=0x303, MR18=0x121E, DQSOSC=394, MR23=63, INC=23, DEC=15
9068 09:57:56.515059 [RxdqsGatingPostProcess] freq 1600
9069 09:57:56.521571 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9070 09:57:56.525073 best DQS0 dly(2T, 0.5T) = (1, 1)
9071 09:57:56.527903 best DQS1 dly(2T, 0.5T) = (1, 1)
9072 09:57:56.531302 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9073 09:57:56.534603 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9074 09:57:56.537811 best DQS0 dly(2T, 0.5T) = (1, 1)
9075 09:57:56.538016 best DQS1 dly(2T, 0.5T) = (1, 1)
9076 09:57:56.541279 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9077 09:57:56.544551 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9078 09:57:56.548087 Pre-setting of DQS Precalculation
9079 09:57:56.554782 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9080 09:57:56.561265 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9081 09:57:56.568227 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9082 09:57:56.568442
9083 09:57:56.568585
9084 09:57:56.571246 [Calibration Summary] 3200 Mbps
9085 09:57:56.571398 CH 0, Rank 0
9086 09:57:56.574575 SW Impedance : PASS
9087 09:57:56.578152 DUTY Scan : NO K
9088 09:57:56.578295 ZQ Calibration : PASS
9089 09:57:56.581282 Jitter Meter : NO K
9090 09:57:56.584686 CBT Training : PASS
9091 09:57:56.584849 Write leveling : PASS
9092 09:57:56.588021 RX DQS gating : PASS
9093 09:57:56.591373 RX DQ/DQS(RDDQC) : PASS
9094 09:57:56.591509 TX DQ/DQS : PASS
9095 09:57:56.594602 RX DATLAT : PASS
9096 09:57:56.597790 RX DQ/DQS(Engine): PASS
9097 09:57:56.597964 TX OE : PASS
9098 09:57:56.601146 All Pass.
9099 09:57:56.601297
9100 09:57:56.601424 CH 0, Rank 1
9101 09:57:56.604351 SW Impedance : PASS
9102 09:57:56.604500 DUTY Scan : NO K
9103 09:57:56.607692 ZQ Calibration : PASS
9104 09:57:56.611093 Jitter Meter : NO K
9105 09:57:56.611258 CBT Training : PASS
9106 09:57:56.614224 Write leveling : PASS
9107 09:57:56.617551 RX DQS gating : PASS
9108 09:57:56.617746 RX DQ/DQS(RDDQC) : PASS
9109 09:57:56.621068 TX DQ/DQS : PASS
9110 09:57:56.621256 RX DATLAT : PASS
9111 09:57:56.624118 RX DQ/DQS(Engine): PASS
9112 09:57:56.627498 TX OE : PASS
9113 09:57:56.627694 All Pass.
9114 09:57:56.627833
9115 09:57:56.630766 CH 1, Rank 0
9116 09:57:56.630937 SW Impedance : PASS
9117 09:57:56.633966 DUTY Scan : NO K
9118 09:57:56.634142 ZQ Calibration : PASS
9119 09:57:56.637348 Jitter Meter : NO K
9120 09:57:56.640841 CBT Training : PASS
9121 09:57:56.640989 Write leveling : PASS
9122 09:57:56.644081 RX DQS gating : PASS
9123 09:57:56.647521 RX DQ/DQS(RDDQC) : PASS
9124 09:57:56.647658 TX DQ/DQS : PASS
9125 09:57:56.650852 RX DATLAT : PASS
9126 09:57:56.654302 RX DQ/DQS(Engine): PASS
9127 09:57:56.654446 TX OE : PASS
9128 09:57:56.657099 All Pass.
9129 09:57:56.657228
9130 09:57:56.657302 CH 1, Rank 1
9131 09:57:56.660776 SW Impedance : PASS
9132 09:57:56.660971 DUTY Scan : NO K
9133 09:57:56.663980 ZQ Calibration : PASS
9134 09:57:56.667413 Jitter Meter : NO K
9135 09:57:56.667546 CBT Training : PASS
9136 09:57:56.670590 Write leveling : PASS
9137 09:57:56.674149 RX DQS gating : PASS
9138 09:57:56.674326 RX DQ/DQS(RDDQC) : PASS
9139 09:57:56.677104 TX DQ/DQS : PASS
9140 09:57:56.677234 RX DATLAT : PASS
9141 09:57:56.680627 RX DQ/DQS(Engine): PASS
9142 09:57:56.683967 TX OE : PASS
9143 09:57:56.684119 All Pass.
9144 09:57:56.684235
9145 09:57:56.687315 DramC Write-DBI on
9146 09:57:56.687415 PER_BANK_REFRESH: Hybrid Mode
9147 09:57:56.690291 TX_TRACKING: ON
9148 09:57:56.700425 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9149 09:57:56.706964 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9150 09:57:56.713699 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9151 09:57:56.716893 [FAST_K] Save calibration result to emmc
9152 09:57:56.720142 sync common calibartion params.
9153 09:57:56.723512 sync cbt_mode0:1, 1:1
9154 09:57:56.726686 dram_init: ddr_geometry: 2
9155 09:57:56.726834 dram_init: ddr_geometry: 2
9156 09:57:56.729987 dram_init: ddr_geometry: 2
9157 09:57:56.733269 0:dram_rank_size:100000000
9158 09:57:56.733406 1:dram_rank_size:100000000
9159 09:57:56.740087 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9160 09:57:56.743502 DFS_SHUFFLE_HW_MODE: ON
9161 09:57:56.746455 dramc_set_vcore_voltage set vcore to 725000
9162 09:57:56.749776 Read voltage for 1600, 0
9163 09:57:56.749976 Vio18 = 0
9164 09:57:56.750092 Vcore = 725000
9165 09:57:56.753030 Vdram = 0
9166 09:57:56.753195 Vddq = 0
9167 09:57:56.753313 Vmddr = 0
9168 09:57:56.756720 switch to 3200 Mbps bootup
9169 09:57:56.756884 [DramcRunTimeConfig]
9170 09:57:56.759757 PHYPLL
9171 09:57:56.759920 DPM_CONTROL_AFTERK: ON
9172 09:57:56.763523 PER_BANK_REFRESH: ON
9173 09:57:56.766723 REFRESH_OVERHEAD_REDUCTION: ON
9174 09:57:56.766902 CMD_PICG_NEW_MODE: OFF
9175 09:57:56.769918 XRTWTW_NEW_MODE: ON
9176 09:57:56.770090 XRTRTR_NEW_MODE: ON
9177 09:57:56.773272 TX_TRACKING: ON
9178 09:57:56.773445 RDSEL_TRACKING: OFF
9179 09:57:56.776472 DQS Precalculation for DVFS: ON
9180 09:57:56.779719 RX_TRACKING: OFF
9181 09:57:56.779954 HW_GATING DBG: ON
9182 09:57:56.783324 ZQCS_ENABLE_LP4: ON
9183 09:57:56.783437 RX_PICG_NEW_MODE: ON
9184 09:57:56.786373 TX_PICG_NEW_MODE: ON
9185 09:57:56.786518 ENABLE_RX_DCM_DPHY: ON
9186 09:57:56.790038 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9187 09:57:56.792975 DUMMY_READ_FOR_TRACKING: OFF
9188 09:57:56.796769 !!! SPM_CONTROL_AFTERK: OFF
9189 09:57:56.800132 !!! SPM could not control APHY
9190 09:57:56.800361 IMPEDANCE_TRACKING: ON
9191 09:57:56.803320 TEMP_SENSOR: ON
9192 09:57:56.803455 HW_SAVE_FOR_SR: OFF
9193 09:57:56.806677 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9194 09:57:56.809526 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9195 09:57:56.812947 Read ODT Tracking: ON
9196 09:57:56.816548 Refresh Rate DeBounce: ON
9197 09:57:56.816674 DFS_NO_QUEUE_FLUSH: ON
9198 09:57:56.819905 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9199 09:57:56.823097 ENABLE_DFS_RUNTIME_MRW: OFF
9200 09:57:56.826383 DDR_RESERVE_NEW_MODE: ON
9201 09:57:56.826521 MR_CBT_SWITCH_FREQ: ON
9202 09:57:56.829900 =========================
9203 09:57:56.848501 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9204 09:57:56.851868 dram_init: ddr_geometry: 2
9205 09:57:56.870019 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9206 09:57:56.873464 dram_init: dram init end (result: 0)
9207 09:57:56.880135 DRAM-K: Full calibration passed in 24592 msecs
9208 09:57:56.883154 MRC: failed to locate region type 0.
9209 09:57:56.883287 DRAM rank0 size:0x100000000,
9210 09:57:56.886376 DRAM rank1 size=0x100000000
9211 09:57:56.897052 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9212 09:57:56.903147 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9213 09:57:56.909852 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9214 09:57:56.919594 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9215 09:57:56.919710 DRAM rank0 size:0x100000000,
9216 09:57:56.922888 DRAM rank1 size=0x100000000
9217 09:57:56.922971 CBMEM:
9218 09:57:56.926151 IMD: root @ 0xfffff000 254 entries.
9219 09:57:56.929290 IMD: root @ 0xffffec00 62 entries.
9220 09:57:56.932628 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9221 09:57:56.939209 WARNING: RO_VPD is uninitialized or empty.
9222 09:57:56.943078 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9223 09:57:56.950145 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9224 09:57:56.963061 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9225 09:57:56.974369 BS: romstage times (exec / console): total (unknown) / 24051 ms
9226 09:57:56.974544
9227 09:57:56.974647
9228 09:57:56.984188 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9229 09:57:56.987451 ARM64: Exception handlers installed.
9230 09:57:56.991482 ARM64: Testing exception
9231 09:57:56.994634 ARM64: Done test exception
9232 09:57:56.994751 Enumerating buses...
9233 09:57:56.997393 Show all devs... Before device enumeration.
9234 09:57:57.000914 Root Device: enabled 1
9235 09:57:57.004335 CPU_CLUSTER: 0: enabled 1
9236 09:57:57.004455 CPU: 00: enabled 1
9237 09:57:57.007562 Compare with tree...
9238 09:57:57.007674 Root Device: enabled 1
9239 09:57:57.010759 CPU_CLUSTER: 0: enabled 1
9240 09:57:57.014107 CPU: 00: enabled 1
9241 09:57:57.014218 Root Device scanning...
9242 09:57:57.017183 scan_static_bus for Root Device
9243 09:57:57.020719 CPU_CLUSTER: 0 enabled
9244 09:57:57.024121 scan_static_bus for Root Device done
9245 09:57:57.027323 scan_bus: bus Root Device finished in 8 msecs
9246 09:57:57.027419 done
9247 09:57:57.033937 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9248 09:57:57.037485 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9249 09:57:57.043887 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9250 09:57:57.047125 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9251 09:57:57.050285 Allocating resources...
9252 09:57:57.053838 Reading resources...
9253 09:57:57.057631 Root Device read_resources bus 0 link: 0
9254 09:57:57.057775 DRAM rank0 size:0x100000000,
9255 09:57:57.060340 DRAM rank1 size=0x100000000
9256 09:57:57.063747 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9257 09:57:57.067114 CPU: 00 missing read_resources
9258 09:57:57.073808 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9259 09:57:57.076877 Root Device read_resources bus 0 link: 0 done
9260 09:57:57.076969 Done reading resources.
9261 09:57:57.083473 Show resources in subtree (Root Device)...After reading.
9262 09:57:57.087086 Root Device child on link 0 CPU_CLUSTER: 0
9263 09:57:57.090480 CPU_CLUSTER: 0 child on link 0 CPU: 00
9264 09:57:57.100832 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9265 09:57:57.100955 CPU: 00
9266 09:57:57.103433 Root Device assign_resources, bus 0 link: 0
9267 09:57:57.107036 CPU_CLUSTER: 0 missing set_resources
9268 09:57:57.113532 Root Device assign_resources, bus 0 link: 0 done
9269 09:57:57.113635 Done setting resources.
9270 09:57:57.120195 Show resources in subtree (Root Device)...After assigning values.
9271 09:57:57.123606 Root Device child on link 0 CPU_CLUSTER: 0
9272 09:57:57.126848 CPU_CLUSTER: 0 child on link 0 CPU: 00
9273 09:57:57.136757 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9274 09:57:57.136909 CPU: 00
9275 09:57:57.140072 Done allocating resources.
9276 09:57:57.143373 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9277 09:57:57.146484 Enabling resources...
9278 09:57:57.146625 done.
9279 09:57:57.153184 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9280 09:57:57.153302 Initializing devices...
9281 09:57:57.156748 Root Device init
9282 09:57:57.156858 init hardware done!
9283 09:57:57.160010 0x00000018: ctrlr->caps
9284 09:57:57.163179 52.000 MHz: ctrlr->f_max
9285 09:57:57.163300 0.400 MHz: ctrlr->f_min
9286 09:57:57.166539 0x40ff8080: ctrlr->voltages
9287 09:57:57.169892 sclk: 390625
9288 09:57:57.170018 Bus Width = 1
9289 09:57:57.170122 sclk: 390625
9290 09:57:57.173318 Bus Width = 1
9291 09:57:57.173413 Early init status = 3
9292 09:57:57.179866 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9293 09:57:57.183090 in-header: 03 fb 00 00 01 00 00 00
9294 09:57:57.186512 in-data: 01
9295 09:57:57.189534 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9296 09:57:57.194374 in-header: 03 fb 00 00 01 00 00 00
9297 09:57:57.197704 in-data: 01
9298 09:57:57.200819 [SSUSB] Setting up USB HOST controller...
9299 09:57:57.204041 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9300 09:57:57.207237 [SSUSB] phy power-on done.
9301 09:57:57.210695 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9302 09:57:57.217200 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9303 09:57:57.220620 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9304 09:57:57.227258 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9305 09:57:57.233775 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9306 09:57:57.240725 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9307 09:57:57.247135 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9308 09:57:57.253668 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9309 09:57:57.256996 SPM: binary array size = 0x9dc
9310 09:57:57.260559 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9311 09:57:57.267544 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9312 09:57:57.273501 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9313 09:57:57.280321 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9314 09:57:57.283454 configure_display: Starting display init
9315 09:57:57.317525 anx7625_power_on_init: Init interface.
9316 09:57:57.320909 anx7625_disable_pd_protocol: Disabled PD feature.
9317 09:57:57.324285 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9318 09:57:57.352281 anx7625_start_dp_work: Secure OCM version=00
9319 09:57:57.355045 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9320 09:57:57.370127 sp_tx_get_edid_block: EDID Block = 1
9321 09:57:57.472877 Extracted contents:
9322 09:57:57.476129 header: 00 ff ff ff ff ff ff 00
9323 09:57:57.479435 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9324 09:57:57.482740 version: 01 04
9325 09:57:57.485891 basic params: 95 1f 11 78 0a
9326 09:57:57.489036 chroma info: 76 90 94 55 54 90 27 21 50 54
9327 09:57:57.492295 established: 00 00 00
9328 09:57:57.498878 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9329 09:57:57.502414 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9330 09:57:57.508904 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9331 09:57:57.515575 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9332 09:57:57.522070 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9333 09:57:57.525421 extensions: 00
9334 09:57:57.525530 checksum: fb
9335 09:57:57.525623
9336 09:57:57.528768 Manufacturer: IVO Model 57d Serial Number 0
9337 09:57:57.532723 Made week 0 of 2020
9338 09:57:57.532832 EDID version: 1.4
9339 09:57:57.535523 Digital display
9340 09:57:57.538822 6 bits per primary color channel
9341 09:57:57.538930 DisplayPort interface
9342 09:57:57.542221 Maximum image size: 31 cm x 17 cm
9343 09:57:57.545482 Gamma: 220%
9344 09:57:57.545587 Check DPMS levels
9345 09:57:57.548781 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9346 09:57:57.555228 First detailed timing is preferred timing
9347 09:57:57.555346 Established timings supported:
9348 09:57:57.558845 Standard timings supported:
9349 09:57:57.562370 Detailed timings
9350 09:57:57.565478 Hex of detail: 383680a07038204018303c0035ae10000019
9351 09:57:57.568411 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9352 09:57:57.575162 0780 0798 07c8 0820 hborder 0
9353 09:57:57.578438 0438 043b 0447 0458 vborder 0
9354 09:57:57.581625 -hsync -vsync
9355 09:57:57.581706 Did detailed timing
9356 09:57:57.588393 Hex of detail: 000000000000000000000000000000000000
9357 09:57:57.591899 Manufacturer-specified data, tag 0
9358 09:57:57.595025 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9359 09:57:57.598437 ASCII string: InfoVision
9360 09:57:57.601553 Hex of detail: 000000fe00523134304e574635205248200a
9361 09:57:57.604777 ASCII string: R140NWF5 RH
9362 09:57:57.604916 Checksum
9363 09:57:57.608037 Checksum: 0xfb (valid)
9364 09:57:57.611543 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9365 09:57:57.614795 DSI data_rate: 832800000 bps
9366 09:57:57.621786 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9367 09:57:57.625118 anx7625_parse_edid: pixelclock(138800).
9368 09:57:57.628294 hactive(1920), hsync(48), hfp(24), hbp(88)
9369 09:57:57.631369 vactive(1080), vsync(12), vfp(3), vbp(17)
9370 09:57:57.634895 anx7625_dsi_config: config dsi.
9371 09:57:57.641472 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9372 09:57:57.654857 anx7625_dsi_config: success to config DSI
9373 09:57:57.657741 anx7625_dp_start: MIPI phy setup OK.
9374 09:57:57.661084 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9375 09:57:57.664383 mtk_ddp_mode_set invalid vrefresh 60
9376 09:57:57.668279 main_disp_path_setup
9377 09:57:57.668390 ovl_layer_smi_id_en
9378 09:57:57.671452 ovl_layer_smi_id_en
9379 09:57:57.671560 ccorr_config
9380 09:57:57.671655 aal_config
9381 09:57:57.674756 gamma_config
9382 09:57:57.674867 postmask_config
9383 09:57:57.677967 dither_config
9384 09:57:57.680900 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9385 09:57:57.687929 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9386 09:57:57.691009 Root Device init finished in 531 msecs
9387 09:57:57.694712 CPU_CLUSTER: 0 init
9388 09:57:57.700944 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9389 09:57:57.704365 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9390 09:57:57.707912 APU_MBOX 0x190000b0 = 0x10001
9391 09:57:57.710873 APU_MBOX 0x190001b0 = 0x10001
9392 09:57:57.714764 APU_MBOX 0x190005b0 = 0x10001
9393 09:57:57.718011 APU_MBOX 0x190006b0 = 0x10001
9394 09:57:57.720725 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9395 09:57:57.734054 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9396 09:57:57.745838 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9397 09:57:57.752552 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9398 09:57:57.764649 read SPI 0x61c74 0xe8ef: 6413 us, 9298 KB/s, 74.384 Mbps
9399 09:57:57.773354 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9400 09:57:57.777006 CPU_CLUSTER: 0 init finished in 81 msecs
9401 09:57:57.780124 Devices initialized
9402 09:57:57.783724 Show all devs... After init.
9403 09:57:57.783842 Root Device: enabled 1
9404 09:57:57.786937 CPU_CLUSTER: 0: enabled 1
9405 09:57:57.790307 CPU: 00: enabled 1
9406 09:57:57.793528 BS: BS_DEV_INIT run times (exec / console): 208 / 428 ms
9407 09:57:57.796492 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9408 09:57:57.799965 ELOG: NV offset 0x57f000 size 0x1000
9409 09:57:57.806926 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9410 09:57:57.813658 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9411 09:57:57.816833 ELOG: Event(17) added with size 13 at 2023-11-24 09:58:00 UTC
9412 09:57:57.819798 out: cmd=0x121: 03 db 21 01 00 00 00 00
9413 09:57:57.823809 in-header: 03 60 00 00 2c 00 00 00
9414 09:57:57.836996 in-data: ff 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9415 09:57:57.843883 ELOG: Event(A1) added with size 10 at 2023-11-24 09:58:00 UTC
9416 09:57:57.850572 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9417 09:57:57.856729 ELOG: Event(A0) added with size 9 at 2023-11-24 09:58:00 UTC
9418 09:57:57.860168 elog_add_boot_reason: Logged dev mode boot
9419 09:57:57.863567 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9420 09:57:57.867142 Finalize devices...
9421 09:57:57.867251 Devices finalized
9422 09:57:57.873773 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9423 09:57:57.876793 Writing coreboot table at 0xffe64000
9424 09:57:57.880108 0. 000000000010a000-0000000000113fff: RAMSTAGE
9425 09:57:57.883711 1. 0000000040000000-00000000400fffff: RAM
9426 09:57:57.886964 2. 0000000040100000-000000004032afff: RAMSTAGE
9427 09:57:57.893748 3. 000000004032b000-00000000545fffff: RAM
9428 09:57:57.897173 4. 0000000054600000-000000005465ffff: BL31
9429 09:57:57.900521 5. 0000000054660000-00000000ffe63fff: RAM
9430 09:57:57.903710 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9431 09:57:57.910422 7. 0000000100000000-000000023fffffff: RAM
9432 09:57:57.910518 Passing 5 GPIOs to payload:
9433 09:57:57.916692 NAME | PORT | POLARITY | VALUE
9434 09:57:57.920148 EC in RW | 0x000000aa | low | undefined
9435 09:57:57.926598 EC interrupt | 0x00000005 | low | undefined
9436 09:57:57.930100 TPM interrupt | 0x000000ab | high | undefined
9437 09:57:57.933405 SD card detect | 0x00000011 | high | undefined
9438 09:57:57.940076 speaker enable | 0x00000093 | high | undefined
9439 09:57:57.943448 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9440 09:57:57.946710 in-header: 03 f9 00 00 02 00 00 00
9441 09:57:57.950410 in-data: 02 00
9442 09:57:57.950559 ADC[4]: Raw value=896670 ID=7
9443 09:57:57.953416 ADC[3]: Raw value=213440 ID=1
9444 09:57:57.956445 RAM Code: 0x71
9445 09:57:57.956551 ADC[6]: Raw value=74722 ID=0
9446 09:57:57.959726 ADC[5]: Raw value=211960 ID=1
9447 09:57:57.963027 SKU Code: 0x1
9448 09:57:57.966547 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 15a3
9449 09:57:57.969527 coreboot table: 964 bytes.
9450 09:57:57.973094 IMD ROOT 0. 0xfffff000 0x00001000
9451 09:57:57.976614 IMD SMALL 1. 0xffffe000 0x00001000
9452 09:57:57.979943 RO MCACHE 2. 0xffffc000 0x00001104
9453 09:57:57.982932 CONSOLE 3. 0xfff7c000 0x00080000
9454 09:57:57.986432 FMAP 4. 0xfff7b000 0x00000452
9455 09:57:57.989986 TIME STAMP 5. 0xfff7a000 0x00000910
9456 09:57:57.992888 VBOOT WORK 6. 0xfff66000 0x00014000
9457 09:57:57.996360 RAMOOPS 7. 0xffe66000 0x00100000
9458 09:57:57.999481 COREBOOT 8. 0xffe64000 0x00002000
9459 09:57:57.999570 IMD small region:
9460 09:57:58.003190 IMD ROOT 0. 0xffffec00 0x00000400
9461 09:57:58.009498 VPD 1. 0xffffeb80 0x0000006c
9462 09:57:58.012892 MMC STATUS 2. 0xffffeb60 0x00000004
9463 09:57:58.016075 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9464 09:57:58.019024 Probing TPM: done!
9465 09:57:58.023102 Connected to device vid:did:rid of 1ae0:0028:00
9466 09:57:58.033045 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9467 09:57:58.036508 Initialized TPM device CR50 revision 0
9468 09:57:58.039887 Checking cr50 for pending updates
9469 09:57:58.043641 Reading cr50 TPM mode
9470 09:57:58.052332 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9471 09:57:58.058808 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9472 09:57:58.099031 read SPI 0x3990ec 0x4f1b0: 34859 us, 9295 KB/s, 74.360 Mbps
9473 09:57:58.102268 Checking segment from ROM address 0x40100000
9474 09:57:58.106182 Checking segment from ROM address 0x4010001c
9475 09:57:58.112056 Loading segment from ROM address 0x40100000
9476 09:57:58.112192 code (compression=0)
9477 09:57:58.122631 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9478 09:57:58.128911 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9479 09:57:58.129028 it's not compressed!
9480 09:57:58.135922 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9481 09:57:58.138867 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9482 09:57:58.159362 Loading segment from ROM address 0x4010001c
9483 09:57:58.159491 Entry Point 0x80000000
9484 09:57:58.162822 Loaded segments
9485 09:57:58.166355 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9486 09:57:58.172798 Jumping to boot code at 0x80000000(0xffe64000)
9487 09:57:58.179722 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9488 09:57:58.186243 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9489 09:57:58.193847 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9490 09:57:58.197323 Checking segment from ROM address 0x40100000
9491 09:57:58.200703 Checking segment from ROM address 0x4010001c
9492 09:57:58.207445 Loading segment from ROM address 0x40100000
9493 09:57:58.207565 code (compression=1)
9494 09:57:58.214173 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9495 09:57:58.224291 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9496 09:57:58.224444 using LZMA
9497 09:57:58.232149 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9498 09:57:58.239128 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9499 09:57:58.242683 Loading segment from ROM address 0x4010001c
9500 09:57:58.242798 Entry Point 0x54601000
9501 09:57:58.245576 Loaded segments
9502 09:57:58.249090 NOTICE: MT8192 bl31_setup
9503 09:57:58.256042 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9504 09:57:58.259523 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9505 09:57:58.262614 WARNING: region 0:
9506 09:57:58.266051 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9507 09:57:58.266126 WARNING: region 1:
9508 09:57:58.272928 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9509 09:57:58.275853 WARNING: region 2:
9510 09:57:58.279455 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9511 09:57:58.282877 WARNING: region 3:
9512 09:57:58.286326 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9513 09:57:58.289685 WARNING: region 4:
9514 09:57:58.292577 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9515 09:57:58.296118 WARNING: region 5:
9516 09:57:58.299682 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9517 09:57:58.303000 WARNING: region 6:
9518 09:57:58.306160 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9519 09:57:58.306259 WARNING: region 7:
9520 09:57:58.312578 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9521 09:57:58.319729 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9522 09:57:58.322971 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9523 09:57:58.326126 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9524 09:57:58.332737 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9525 09:57:58.336518 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9526 09:57:58.339758 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9527 09:57:58.346469 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9528 09:57:58.349385 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9529 09:57:58.352872 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9530 09:57:58.359148 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9531 09:57:58.362891 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9532 09:57:58.369765 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9533 09:57:58.372603 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9534 09:57:58.376041 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9535 09:57:58.382542 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9536 09:57:58.386049 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9537 09:57:58.392463 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9538 09:57:58.395856 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9539 09:57:58.399290 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9540 09:57:58.405850 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9541 09:57:58.409258 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9542 09:57:58.412409 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9543 09:57:58.419028 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9544 09:57:58.422391 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9545 09:57:58.428797 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9546 09:57:58.432188 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9547 09:57:58.435558 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9548 09:57:58.442668 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9549 09:57:58.445446 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9550 09:57:58.452488 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9551 09:57:58.455672 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9552 09:57:58.459102 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9553 09:57:58.465342 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9554 09:57:58.469051 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9555 09:57:58.472398 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9556 09:57:58.475379 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9557 09:57:58.481897 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9558 09:57:58.485465 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9559 09:57:58.489074 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9560 09:57:58.492042 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9561 09:57:58.498891 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9562 09:57:58.502244 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9563 09:57:58.505234 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9564 09:57:58.508679 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9565 09:57:58.515831 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9566 09:57:58.518944 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9567 09:57:58.522436 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9568 09:57:58.525490 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9569 09:57:58.532225 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9570 09:57:58.535243 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9571 09:57:58.542327 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9572 09:57:58.545175 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9573 09:57:58.551952 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9574 09:57:58.555448 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9575 09:57:58.558919 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9576 09:57:58.565588 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9577 09:57:58.568813 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9578 09:57:58.575523 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9579 09:57:58.579038 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9580 09:57:58.585272 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9581 09:57:58.588491 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9582 09:57:58.591970 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9583 09:57:58.598862 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9584 09:57:58.602336 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9585 09:57:58.608845 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9586 09:57:58.612431 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9587 09:57:58.618887 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9588 09:57:58.622310 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9589 09:57:58.625620 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9590 09:57:58.631791 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9591 09:57:58.635214 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9592 09:57:58.642330 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9593 09:57:58.645694 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9594 09:57:58.651737 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9595 09:57:58.655129 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9596 09:57:58.662145 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9597 09:57:58.665547 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9598 09:57:58.668580 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9599 09:57:58.675589 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9600 09:57:58.678460 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9601 09:57:58.685340 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9602 09:57:58.688518 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9603 09:57:58.695365 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9604 09:57:58.698653 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9605 09:57:58.701845 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9606 09:57:58.708919 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9607 09:57:58.711844 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9608 09:57:58.718658 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9609 09:57:58.722161 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9610 09:57:58.728462 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9611 09:57:58.731830 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9612 09:57:58.735159 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9613 09:57:58.742208 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9614 09:57:58.745788 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9615 09:57:58.752250 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9616 09:57:58.755453 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9617 09:57:58.759093 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9618 09:57:58.765877 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9619 09:57:58.768626 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9620 09:57:58.772072 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9621 09:57:58.775524 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9622 09:57:58.781945 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9623 09:57:58.785271 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9624 09:57:58.792152 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9625 09:57:58.795107 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9626 09:57:58.798966 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9627 09:57:58.805138 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9628 09:57:58.808550 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9629 09:57:58.815388 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9630 09:57:58.818859 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9631 09:57:58.821930 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9632 09:57:58.829049 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9633 09:57:58.832029 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9634 09:57:58.838900 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9635 09:57:58.842207 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9636 09:57:58.845705 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9637 09:57:58.848538 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9638 09:57:58.855506 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9639 09:57:58.858840 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9640 09:57:58.862652 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9641 09:57:58.868985 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9642 09:57:58.871868 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9643 09:57:58.875383 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9644 09:57:58.878882 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9645 09:57:58.885365 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9646 09:57:58.888793 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9647 09:57:58.895634 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9648 09:57:58.899172 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9649 09:57:58.902044 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9650 09:57:58.909140 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9651 09:57:58.912076 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9652 09:57:58.915344 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9653 09:57:58.922149 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9654 09:57:58.925560 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9655 09:57:58.932076 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9656 09:57:58.935389 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9657 09:57:58.939075 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9658 09:57:58.945484 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9659 09:57:58.948660 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9660 09:57:58.955496 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9661 09:57:58.959047 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9662 09:57:58.961858 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9663 09:57:58.968539 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9664 09:57:58.972416 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9665 09:57:58.975436 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9666 09:57:58.982274 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9667 09:57:58.985755 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9668 09:57:58.992162 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9669 09:57:58.995714 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9670 09:57:58.999013 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9671 09:57:59.005287 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9672 09:57:59.008910 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9673 09:57:59.015750 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9674 09:57:59.019102 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9675 09:57:59.022098 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9676 09:57:59.029160 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9677 09:57:59.032079 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9678 09:57:59.038902 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9679 09:57:59.042287 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9680 09:57:59.045629 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9681 09:57:59.052184 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9682 09:57:59.055105 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9683 09:57:59.061969 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9684 09:57:59.065262 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9685 09:57:59.068455 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9686 09:57:59.075020 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9687 09:57:59.078628 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9688 09:57:59.081523 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9689 09:57:59.088360 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9690 09:57:59.091867 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9691 09:57:59.098358 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9692 09:57:59.101732 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9693 09:57:59.105335 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9694 09:57:59.111526 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9695 09:57:59.114887 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9696 09:57:59.121761 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9697 09:57:59.124710 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9698 09:57:59.128119 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9699 09:57:59.134768 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9700 09:57:59.138365 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9701 09:57:59.144784 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9702 09:57:59.148108 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9703 09:57:59.151595 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9704 09:57:59.158087 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9705 09:57:59.161116 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9706 09:57:59.167676 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9707 09:57:59.171413 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9708 09:57:59.174823 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9709 09:57:59.181363 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9710 09:57:59.184615 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9711 09:57:59.191059 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9712 09:57:59.194646 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9713 09:57:59.201039 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9714 09:57:59.204539 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9715 09:57:59.207465 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9716 09:57:59.214521 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9717 09:57:59.217289 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9718 09:57:59.224029 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9719 09:57:59.227624 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9720 09:57:59.231002 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9721 09:57:59.237338 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9722 09:57:59.240848 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9723 09:57:59.247483 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9724 09:57:59.250900 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9725 09:57:59.257450 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9726 09:57:59.260684 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9727 09:57:59.263483 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9728 09:57:59.270245 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9729 09:57:59.273384 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9730 09:57:59.280608 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9731 09:57:59.283516 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9732 09:57:59.287048 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9733 09:57:59.293686 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9734 09:57:59.296855 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9735 09:57:59.303813 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9736 09:57:59.306778 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9737 09:57:59.313709 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9738 09:57:59.316613 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9739 09:57:59.320142 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9740 09:57:59.326812 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9741 09:57:59.329869 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9742 09:57:59.336759 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9743 09:57:59.340214 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9744 09:57:59.346702 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9745 09:57:59.349799 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9746 09:57:59.353419 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9747 09:57:59.359834 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9748 09:57:59.363361 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9749 09:57:59.370057 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9750 09:57:59.373131 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9751 09:57:59.376469 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9752 09:57:59.380069 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9753 09:57:59.383337 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9754 09:57:59.389682 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9755 09:57:59.393283 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9756 09:57:59.399829 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9757 09:57:59.403031 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9758 09:57:59.406437 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9759 09:57:59.412995 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9760 09:57:59.416440 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9761 09:57:59.419442 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9762 09:57:59.426044 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9763 09:57:59.429441 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9764 09:57:59.432765 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9765 09:57:59.439289 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9766 09:57:59.442647 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9767 09:57:59.449448 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9768 09:57:59.452944 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9769 09:57:59.455930 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9770 09:57:59.462631 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9771 09:57:59.466042 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9772 09:57:59.469580 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9773 09:57:59.476003 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9774 09:57:59.479495 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9775 09:57:59.482434 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9776 09:57:59.489305 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9777 09:57:59.492522 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9778 09:57:59.499131 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9779 09:57:59.502406 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9780 09:57:59.506097 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9781 09:57:59.512830 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9782 09:57:59.515739 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9783 09:57:59.519077 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9784 09:57:59.525999 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9785 09:57:59.528943 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9786 09:57:59.532509 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9787 09:57:59.538998 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9788 09:57:59.542323 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9789 09:57:59.545746 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9790 09:57:59.552805 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9791 09:57:59.555549 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9792 09:57:59.559011 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9793 09:57:59.562455 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9794 09:57:59.568755 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9795 09:57:59.572165 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9796 09:57:59.575525 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9797 09:57:59.578983 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9798 09:57:59.585420 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9799 09:57:59.588678 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9800 09:57:59.592076 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9801 09:57:59.598922 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9802 09:57:59.601794 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9803 09:57:59.605185 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9804 09:57:59.611795 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9805 09:57:59.615116 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9806 09:57:59.618906 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9807 09:57:59.625194 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9808 09:57:59.628625 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9809 09:57:59.635194 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9810 09:57:59.638580 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9811 09:57:59.642035 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9812 09:57:59.648663 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9813 09:57:59.651634 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9814 09:57:59.658434 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9815 09:57:59.661367 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9816 09:57:59.668348 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9817 09:57:59.671737 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9818 09:57:59.675207 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9819 09:57:59.681735 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9820 09:57:59.685080 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9821 09:57:59.691488 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9822 09:57:59.694798 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9823 09:57:59.698284 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9824 09:57:59.704732 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9825 09:57:59.708096 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9826 09:57:59.714781 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9827 09:57:59.718296 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9828 09:57:59.721733 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9829 09:57:59.728072 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9830 09:57:59.731436 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9831 09:57:59.737904 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9832 09:57:59.741467 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9833 09:57:59.747790 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9834 09:57:59.751299 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9835 09:57:59.754453 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9836 09:57:59.761410 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9837 09:57:59.764592 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9838 09:57:59.771456 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9839 09:57:59.774413 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9840 09:57:59.777889 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9841 09:57:59.784237 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9842 09:57:59.787651 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9843 09:57:59.794687 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9844 09:57:59.797438 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9845 09:57:59.800740 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9846 09:57:59.807718 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9847 09:57:59.811165 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9848 09:57:59.817439 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9849 09:57:59.820834 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9850 09:57:59.824209 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9851 09:57:59.830751 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9852 09:57:59.834122 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9853 09:57:59.840652 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9854 09:57:59.843530 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9855 09:57:59.850637 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9856 09:57:59.854071 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9857 09:57:59.868075 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9858 09:57:59.868238 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9859 09:57:59.868323 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9860 09:57:59.873726 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9861 09:57:59.877021 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9862 09:57:59.883310 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9863 09:57:59.886849 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9864 09:57:59.890271 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9865 09:57:59.896499 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9866 09:57:59.899963 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9867 09:57:59.906908 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9868 09:57:59.909877 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9869 09:57:59.913446 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9870 09:57:59.920036 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9871 09:57:59.923040 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9872 09:57:59.929680 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9873 09:57:59.933121 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9874 09:57:59.936691 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9875 09:57:59.942999 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9876 09:57:59.946525 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9877 09:57:59.952917 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9878 09:57:59.956293 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9879 09:57:59.963118 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9880 09:57:59.966139 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9881 09:57:59.973107 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9882 09:57:59.975923 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9883 09:57:59.979343 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9884 09:57:59.986167 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9885 09:57:59.989647 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9886 09:57:59.996148 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9887 09:57:59.999909 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9888 09:58:00.006107 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9889 09:58:00.009666 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9890 09:58:00.012585 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9891 09:58:00.019429 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9892 09:58:00.022757 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9893 09:58:00.029718 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9894 09:58:00.032729 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9895 09:58:00.039192 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9896 09:58:00.042688 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9897 09:58:00.049070 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9898 09:58:00.052664 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9899 09:58:00.055619 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9900 09:58:00.062459 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9901 09:58:00.065817 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9902 09:58:00.072393 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9903 09:58:00.075346 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9904 09:58:00.082277 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9905 09:58:00.085672 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9906 09:58:00.089212 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9907 09:58:00.095404 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9908 09:58:00.098737 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9909 09:58:00.105731 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9910 09:58:00.109005 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9911 09:58:00.115641 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9912 09:58:00.118918 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9913 09:58:00.125151 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9914 09:58:00.128519 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9915 09:58:00.131689 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9916 09:58:00.138378 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9917 09:58:00.142334 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9918 09:58:00.148712 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9919 09:58:00.152163 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9920 09:58:00.158551 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9921 09:58:00.162095 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9922 09:58:00.165083 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9923 09:58:00.171598 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9924 09:58:00.175402 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9925 09:58:00.181628 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9926 09:58:00.185109 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9927 09:58:00.192049 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9928 09:58:00.195036 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9929 09:58:00.201258 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9930 09:58:00.205162 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9931 09:58:00.208073 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9932 09:58:00.214632 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9933 09:58:00.218232 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9934 09:58:00.224511 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9935 09:58:00.227909 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9936 09:58:00.234503 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9937 09:58:00.237728 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9938 09:58:00.244582 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9939 09:58:00.247996 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9940 09:58:00.254659 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9941 09:58:00.257794 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9942 09:58:00.264485 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9943 09:58:00.267862 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9944 09:58:00.274327 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9945 09:58:00.277742 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9946 09:58:00.284330 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9947 09:58:00.287626 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9948 09:58:00.294233 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9949 09:58:00.297736 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9950 09:58:00.304179 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9951 09:58:00.307596 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9952 09:58:00.313959 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9953 09:58:00.317594 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9954 09:58:00.324057 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9955 09:58:00.327523 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9956 09:58:00.330554 INFO: [APUAPC] vio 0
9957 09:58:00.334124 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9958 09:58:00.340856 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9959 09:58:00.343976 INFO: [APUAPC] D0_APC_0: 0x400510
9960 09:58:00.347550 INFO: [APUAPC] D0_APC_1: 0x0
9961 09:58:00.350593 INFO: [APUAPC] D0_APC_2: 0x1540
9962 09:58:00.350677 INFO: [APUAPC] D0_APC_3: 0x0
9963 09:58:00.353981 INFO: [APUAPC] D1_APC_0: 0xffffffff
9964 09:58:00.356913 INFO: [APUAPC] D1_APC_1: 0xffffffff
9965 09:58:00.360470 INFO: [APUAPC] D1_APC_2: 0x3fffff
9966 09:58:00.363826 INFO: [APUAPC] D1_APC_3: 0x0
9967 09:58:00.367115 INFO: [APUAPC] D2_APC_0: 0xffffffff
9968 09:58:00.370804 INFO: [APUAPC] D2_APC_1: 0xffffffff
9969 09:58:00.373752 INFO: [APUAPC] D2_APC_2: 0x3fffff
9970 09:58:00.377244 INFO: [APUAPC] D2_APC_3: 0x0
9971 09:58:00.380162 INFO: [APUAPC] D3_APC_0: 0xffffffff
9972 09:58:00.383869 INFO: [APUAPC] D3_APC_1: 0xffffffff
9973 09:58:00.386765 INFO: [APUAPC] D3_APC_2: 0x3fffff
9974 09:58:00.390318 INFO: [APUAPC] D3_APC_3: 0x0
9975 09:58:00.393490 INFO: [APUAPC] D4_APC_0: 0xffffffff
9976 09:58:00.396819 INFO: [APUAPC] D4_APC_1: 0xffffffff
9977 09:58:00.399963 INFO: [APUAPC] D4_APC_2: 0x3fffff
9978 09:58:00.403288 INFO: [APUAPC] D4_APC_3: 0x0
9979 09:58:00.406764 INFO: [APUAPC] D5_APC_0: 0xffffffff
9980 09:58:00.410237 INFO: [APUAPC] D5_APC_1: 0xffffffff
9981 09:58:00.413508 INFO: [APUAPC] D5_APC_2: 0x3fffff
9982 09:58:00.416872 INFO: [APUAPC] D5_APC_3: 0x0
9983 09:58:00.420306 INFO: [APUAPC] D6_APC_0: 0xffffffff
9984 09:58:00.423177 INFO: [APUAPC] D6_APC_1: 0xffffffff
9985 09:58:00.426760 INFO: [APUAPC] D6_APC_2: 0x3fffff
9986 09:58:00.430178 INFO: [APUAPC] D6_APC_3: 0x0
9987 09:58:00.433062 INFO: [APUAPC] D7_APC_0: 0xffffffff
9988 09:58:00.436698 INFO: [APUAPC] D7_APC_1: 0xffffffff
9989 09:58:00.439704 INFO: [APUAPC] D7_APC_2: 0x3fffff
9990 09:58:00.443255 INFO: [APUAPC] D7_APC_3: 0x0
9991 09:58:00.446281 INFO: [APUAPC] D8_APC_0: 0xffffffff
9992 09:58:00.449661 INFO: [APUAPC] D8_APC_1: 0xffffffff
9993 09:58:00.452928 INFO: [APUAPC] D8_APC_2: 0x3fffff
9994 09:58:00.456393 INFO: [APUAPC] D8_APC_3: 0x0
9995 09:58:00.459994 INFO: [APUAPC] D9_APC_0: 0xffffffff
9996 09:58:00.462999 INFO: [APUAPC] D9_APC_1: 0xffffffff
9997 09:58:00.466506 INFO: [APUAPC] D9_APC_2: 0x3fffff
9998 09:58:00.469989 INFO: [APUAPC] D9_APC_3: 0x0
9999 09:58:00.472992 INFO: [APUAPC] D10_APC_0: 0xffffffff
10000 09:58:00.476358 INFO: [APUAPC] D10_APC_1: 0xffffffff
10001 09:58:00.479713 INFO: [APUAPC] D10_APC_2: 0x3fffff
10002 09:58:00.483369 INFO: [APUAPC] D10_APC_3: 0x0
10003 09:58:00.486469 INFO: [APUAPC] D11_APC_0: 0xffffffff
10004 09:58:00.489767 INFO: [APUAPC] D11_APC_1: 0xffffffff
10005 09:58:00.492903 INFO: [APUAPC] D11_APC_2: 0x3fffff
10006 09:58:00.496278 INFO: [APUAPC] D11_APC_3: 0x0
10007 09:58:00.499456 INFO: [APUAPC] D12_APC_0: 0xffffffff
10008 09:58:00.502877 INFO: [APUAPC] D12_APC_1: 0xffffffff
10009 09:58:00.506195 INFO: [APUAPC] D12_APC_2: 0x3fffff
10010 09:58:00.509351 INFO: [APUAPC] D12_APC_3: 0x0
10011 09:58:00.512909 INFO: [APUAPC] D13_APC_0: 0xffffffff
10012 09:58:00.516124 INFO: [APUAPC] D13_APC_1: 0xffffffff
10013 09:58:00.519300 INFO: [APUAPC] D13_APC_2: 0x3fffff
10014 09:58:00.522582 INFO: [APUAPC] D13_APC_3: 0x0
10015 09:58:00.526124 INFO: [APUAPC] D14_APC_0: 0xffffffff
10016 09:58:00.529576 INFO: [APUAPC] D14_APC_1: 0xffffffff
10017 09:58:00.532488 INFO: [APUAPC] D14_APC_2: 0x3fffff
10018 09:58:00.535998 INFO: [APUAPC] D14_APC_3: 0x0
10019 09:58:00.539621 INFO: [APUAPC] D15_APC_0: 0xffffffff
10020 09:58:00.542540 INFO: [APUAPC] D15_APC_1: 0xffffffff
10021 09:58:00.546036 INFO: [APUAPC] D15_APC_2: 0x3fffff
10022 09:58:00.549033 INFO: [APUAPC] D15_APC_3: 0x0
10023 09:58:00.552542 INFO: [APUAPC] APC_CON: 0x4
10024 09:58:00.556088 INFO: [NOCDAPC] D0_APC_0: 0x0
10025 09:58:00.556229 INFO: [NOCDAPC] D0_APC_1: 0x0
10026 09:58:00.559274 INFO: [NOCDAPC] D1_APC_0: 0x0
10027 09:58:00.562832 INFO: [NOCDAPC] D1_APC_1: 0xfff
10028 09:58:00.565656 INFO: [NOCDAPC] D2_APC_0: 0x0
10029 09:58:00.569089 INFO: [NOCDAPC] D2_APC_1: 0xfff
10030 09:58:00.572590 INFO: [NOCDAPC] D3_APC_0: 0x0
10031 09:58:00.575926 INFO: [NOCDAPC] D3_APC_1: 0xfff
10032 09:58:00.578904 INFO: [NOCDAPC] D4_APC_0: 0x0
10033 09:58:00.582290 INFO: [NOCDAPC] D4_APC_1: 0xfff
10034 09:58:00.585727 INFO: [NOCDAPC] D5_APC_0: 0x0
10035 09:58:00.589018 INFO: [NOCDAPC] D5_APC_1: 0xfff
10036 09:58:00.592320 INFO: [NOCDAPC] D6_APC_0: 0x0
10037 09:58:00.592475 INFO: [NOCDAPC] D6_APC_1: 0xfff
10038 09:58:00.595453 INFO: [NOCDAPC] D7_APC_0: 0x0
10039 09:58:00.599084 INFO: [NOCDAPC] D7_APC_1: 0xfff
10040 09:58:00.602405 INFO: [NOCDAPC] D8_APC_0: 0x0
10041 09:58:00.605442 INFO: [NOCDAPC] D8_APC_1: 0xfff
10042 09:58:00.608921 INFO: [NOCDAPC] D9_APC_0: 0x0
10043 09:58:00.612487 INFO: [NOCDAPC] D9_APC_1: 0xfff
10044 09:58:00.615492 INFO: [NOCDAPC] D10_APC_0: 0x0
10045 09:58:00.618939 INFO: [NOCDAPC] D10_APC_1: 0xfff
10046 09:58:00.622297 INFO: [NOCDAPC] D11_APC_0: 0x0
10047 09:58:00.625628 INFO: [NOCDAPC] D11_APC_1: 0xfff
10048 09:58:00.628536 INFO: [NOCDAPC] D12_APC_0: 0x0
10049 09:58:00.631912 INFO: [NOCDAPC] D12_APC_1: 0xfff
10050 09:58:00.632017 INFO: [NOCDAPC] D13_APC_0: 0x0
10051 09:58:00.635442 INFO: [NOCDAPC] D13_APC_1: 0xfff
10052 09:58:00.638609 INFO: [NOCDAPC] D14_APC_0: 0x0
10053 09:58:00.641967 INFO: [NOCDAPC] D14_APC_1: 0xfff
10054 09:58:00.645042 INFO: [NOCDAPC] D15_APC_0: 0x0
10055 09:58:00.648363 INFO: [NOCDAPC] D15_APC_1: 0xfff
10056 09:58:00.651711 INFO: [NOCDAPC] APC_CON: 0x4
10057 09:58:00.655229 INFO: [APUAPC] set_apusys_apc done
10058 09:58:00.658725 INFO: [DEVAPC] devapc_init done
10059 09:58:00.661626 INFO: GICv3 without legacy support detected.
10060 09:58:00.664982 INFO: ARM GICv3 driver initialized in EL3
10061 09:58:00.671884 INFO: Maximum SPI INTID supported: 639
10062 09:58:00.674852 INFO: BL31: Initializing runtime services
10063 09:58:00.681784 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10064 09:58:00.681888 INFO: SPM: enable CPC mode
10065 09:58:00.688320 INFO: mcdi ready for mcusys-off-idle and system suspend
10066 09:58:00.691707 INFO: BL31: Preparing for EL3 exit to normal world
10067 09:58:00.695165 INFO: Entry point address = 0x80000000
10068 09:58:00.698547 INFO: SPSR = 0x8
10069 09:58:00.703956
10070 09:58:00.704096
10071 09:58:00.704193
10072 09:58:00.707750 Starting depthcharge on Spherion...
10073 09:58:00.707875
10074 09:58:00.707972 Wipe memory regions:
10075 09:58:00.708068
10076 09:58:00.708909 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10077 09:58:00.709047 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10078 09:58:00.709166 Setting prompt string to ['asurada:']
10079 09:58:00.709284 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10080 09:58:00.710527 [0x00000040000000, 0x00000054600000)
10081 09:58:00.833087
10082 09:58:00.833229 [0x00000054660000, 0x00000080000000)
10083 09:58:01.093197
10084 09:58:01.093361 [0x000000821a7280, 0x000000ffe64000)
10085 09:58:01.837573
10086 09:58:01.837753 [0x00000100000000, 0x00000240000000)
10087 09:58:03.725890
10088 09:58:03.729301 Initializing XHCI USB controller at 0x11200000.
10089 09:58:04.767047
10090 09:58:04.769856 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10091 09:58:04.769969
10092 09:58:04.770064
10093 09:58:04.770154
10094 09:58:04.770469 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10096 09:58:04.870863 asurada: tftpboot 192.168.201.1 12073290/tftp-deploy-zjenkfgv/kernel/image.itb 12073290/tftp-deploy-zjenkfgv/kernel/cmdline
10097 09:58:04.871019 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10098 09:58:04.871110 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10099 09:58:04.875023 tftpboot 192.168.201.1 12073290/tftp-deploy-zjenkfgv/kernel/image.itp-deploy-zjenkfgv/kernel/cmdline
10100 09:58:04.875112
10101 09:58:04.875177 Waiting for link
10102 09:58:05.035461
10103 09:58:05.035615 R8152: Initializing
10104 09:58:05.035688
10105 09:58:05.038899 Version 6 (ocp_data = 5c30)
10106 09:58:05.038984
10107 09:58:05.042382 R8152: Done initializing
10108 09:58:05.042463
10109 09:58:05.042574 Adding net device
10110 09:58:07.041136
10111 09:58:07.041277 done.
10112 09:58:07.041346
10113 09:58:07.041408 MAC: 00:24:32:30:78:ff
10114 09:58:07.041467
10115 09:58:07.044060 Sending DHCP discover... done.
10116 09:58:07.044145
10117 09:58:07.047362 Waiting for reply... done.
10118 09:58:07.047447
10119 09:58:07.050572 Sending DHCP request... done.
10120 09:58:07.050659
10121 09:58:07.050739 Waiting for reply... done.
10122 09:58:07.053998
10123 09:58:07.054097 My ip is 192.168.201.21
10124 09:58:07.054166
10125 09:58:07.057430 The DHCP server ip is 192.168.201.1
10126 09:58:07.057541
10127 09:58:07.060903 TFTP server IP predefined by user: 192.168.201.1
10128 09:58:07.060983
10129 09:58:07.067364 Bootfile predefined by user: 12073290/tftp-deploy-zjenkfgv/kernel/image.itb
10130 09:58:07.067455
10131 09:58:07.070646 Sending tftp read request... done.
10132 09:58:07.070730
10133 09:58:07.074162 Waiting for the transfer...
10134 09:58:07.077113
10135 09:58:07.604702 00000000 ################################################################
10136 09:58:07.604889
10137 09:58:08.135027 00080000 ################################################################
10138 09:58:08.135193
10139 09:58:08.658916 00100000 ################################################################
10140 09:58:08.659080
10141 09:58:09.188060 00180000 ################################################################
10142 09:58:09.188241
10143 09:58:09.718359 00200000 ################################################################
10144 09:58:09.718520
10145 09:58:10.243102 00280000 ################################################################
10146 09:58:10.243269
10147 09:58:10.771492 00300000 ################################################################
10148 09:58:10.771648
10149 09:58:11.311684 00380000 ################################################################
10150 09:58:11.311819
10151 09:58:11.836549 00400000 ################################################################
10152 09:58:11.836685
10153 09:58:12.370105 00480000 ################################################################
10154 09:58:12.370246
10155 09:58:12.895463 00500000 ################################################################
10156 09:58:12.895605
10157 09:58:13.420844 00580000 ################################################################
10158 09:58:13.421010
10159 09:58:13.943843 00600000 ################################################################
10160 09:58:13.944020
10161 09:58:14.478012 00680000 ################################################################
10162 09:58:14.478147
10163 09:58:15.015204 00700000 ################################################################
10164 09:58:15.015367
10165 09:58:15.545039 00780000 ################################################################
10166 09:58:15.545224
10167 09:58:16.074739 00800000 ################################################################
10168 09:58:16.074903
10169 09:58:16.601028 00880000 ################################################################
10170 09:58:16.601165
10171 09:58:17.134916 00900000 ################################################################
10172 09:58:17.135085
10173 09:58:17.662377 00980000 ################################################################
10174 09:58:17.662538
10175 09:58:18.194230 00a00000 ################################################################
10176 09:58:18.194400
10177 09:58:18.732902 00a80000 ################################################################
10178 09:58:18.733033
10179 09:58:19.263607 00b00000 ################################################################
10180 09:58:19.263796
10181 09:58:19.790254 00b80000 ################################################################
10182 09:58:19.790416
10183 09:58:20.318542 00c00000 ################################################################
10184 09:58:20.318682
10185 09:58:20.848366 00c80000 ################################################################
10186 09:58:20.848519
10187 09:58:21.376515 00d00000 ################################################################
10188 09:58:21.376680
10189 09:58:21.907583 00d80000 ################################################################
10190 09:58:21.907722
10191 09:58:22.433661 00e00000 ################################################################
10192 09:58:22.433811
10193 09:58:22.960108 00e80000 ################################################################
10194 09:58:22.960288
10195 09:58:23.497620 00f00000 ################################################################
10196 09:58:23.497762
10197 09:58:24.052135 00f80000 ################################################################
10198 09:58:24.052288
10199 09:58:24.604772 01000000 ################################################################
10200 09:58:24.604943
10201 09:58:25.141837 01080000 ################################################################
10202 09:58:25.142021
10203 09:58:25.672340 01100000 ################################################################
10204 09:58:25.672485
10205 09:58:26.201023 01180000 ################################################################
10206 09:58:26.201176
10207 09:58:26.733833 01200000 ################################################################
10208 09:58:26.733980
10209 09:58:27.273175 01280000 ################################################################
10210 09:58:27.273323
10211 09:58:27.799427 01300000 ################################################################
10212 09:58:27.799595
10213 09:58:28.324845 01380000 ################################################################
10214 09:58:28.325012
10215 09:58:28.854298 01400000 ################################################################
10216 09:58:28.854474
10217 09:58:29.384756 01480000 ################################################################
10218 09:58:29.384894
10219 09:58:29.943194 01500000 ################################################################
10220 09:58:29.943347
10221 09:58:30.489656 01580000 ################################################################
10222 09:58:30.489819
10223 09:58:31.055459 01600000 ################################################################
10224 09:58:31.055599
10225 09:58:31.596424 01680000 ################################################################
10226 09:58:31.596564
10227 09:58:32.151324 01700000 ################################################################
10228 09:58:32.151454
10229 09:58:32.705869 01780000 ################################################################
10230 09:58:32.706010
10231 09:58:33.242441 01800000 ################################################################
10232 09:58:33.242585
10233 09:58:33.795249 01880000 ################################################################
10234 09:58:33.795409
10235 09:58:34.312659 01900000 ################################################################
10236 09:58:34.312825
10237 09:58:34.849664 01980000 ################################################################
10238 09:58:34.849827
10239 09:58:35.383049 01a00000 ################################################################
10240 09:58:35.383184
10241 09:58:35.917326 01a80000 ################################################################
10242 09:58:35.917463
10243 09:58:36.459568 01b00000 ################################################################
10244 09:58:36.459704
10245 09:58:36.515174 01b80000 ####### done.
10246 09:58:36.515329
10247 09:58:36.518767 The bootfile was 28890218 bytes long.
10248 09:58:36.518880
10249 09:58:36.522379 Sending tftp read request... done.
10250 09:58:36.522486
10251 09:58:36.522589 Waiting for the transfer...
10252 09:58:36.522678
10253 09:58:36.525402 00000000 # done.
10254 09:58:36.525508
10255 09:58:36.532286 Command line loaded dynamically from TFTP file: 12073290/tftp-deploy-zjenkfgv/kernel/cmdline
10256 09:58:36.532363
10257 09:58:36.555335 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12073290/extract-nfsrootfs-x41g6wi2,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10258 09:58:36.555436
10259 09:58:36.555502 Loading FIT.
10260 09:58:36.555562
10261 09:58:36.558420 Image ramdisk-1 has 17793361 bytes.
10262 09:58:36.558517
10263 09:58:36.561479 Image fdt-1 has 47278 bytes.
10264 09:58:36.561560
10265 09:58:36.565123 Image kernel-1 has 11047542 bytes.
10266 09:58:36.565205
10267 09:58:36.575089 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10268 09:58:36.575195
10269 09:58:36.591891 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10270 09:58:36.592030
10271 09:58:36.598457 Choosing best match conf-1 for compat google,spherion-rev2.
10272 09:58:36.598556
10273 09:58:36.605553 Connected to device vid:did:rid of 1ae0:0028:00
10274 09:58:36.612325
10275 09:58:36.615940 tpm_get_response: command 0x17b, return code 0x0
10276 09:58:36.616048
10277 09:58:36.619283 ec_init: CrosEC protocol v3 supported (256, 248)
10278 09:58:36.623048
10279 09:58:36.626255 tpm_cleanup: add release locality here.
10280 09:58:36.626354
10281 09:58:36.626481 Shutting down all USB controllers.
10282 09:58:36.629627
10283 09:58:36.629709 Removing current net device
10284 09:58:36.629798
10285 09:58:36.636154 Exiting depthcharge with code 4 at timestamp: 65239850
10286 09:58:36.636271
10287 09:58:36.639900 LZMA decompressing kernel-1 to 0x821a6718
10288 09:58:36.639982
10289 09:58:36.642639 LZMA decompressing kernel-1 to 0x40000000
10290 09:58:38.031957
10291 09:58:38.032096 jumping to kernel
10292 09:58:38.032548 end: 2.2.4 bootloader-commands (duration 00:00:37) [common]
10293 09:58:38.032648 start: 2.2.5 auto-login-action (timeout 00:03:48) [common]
10294 09:58:38.032726 Setting prompt string to ['Linux version [0-9]']
10295 09:58:38.032794 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10296 09:58:38.032864 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10297 09:58:38.115348
10298 09:58:38.118220 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10299 09:58:38.121912 start: 2.2.5.1 login-action (timeout 00:03:48) [common]
10300 09:58:38.122034 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10301 09:58:38.122133 Setting prompt string to []
10302 09:58:38.122247 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10303 09:58:38.122355 Using line separator: #'\n'#
10304 09:58:38.122453 No login prompt set.
10305 09:58:38.122546 Parsing kernel messages
10306 09:58:38.122630 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10307 09:58:38.122819 [login-action] Waiting for messages, (timeout 00:03:48)
10308 09:58:38.141922 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j22848-arm64-gcc-10-defconfig-arm64-chromebook-6q8mw) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Nov 24 09:44:51 UTC 2023
10309 09:58:38.145069 [ 0.000000] random: crng init done
10310 09:58:38.148494 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10311 09:58:38.151914 [ 0.000000] efi: UEFI not found.
10312 09:58:38.161882 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10313 09:58:38.168187 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10314 09:58:38.178120 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10315 09:58:38.187950 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10316 09:58:38.194787 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10317 09:58:38.201153 [ 0.000000] printk: bootconsole [mtk8250] enabled
10318 09:58:38.204331 [ 0.000000] NUMA: No NUMA configuration found
10319 09:58:38.214351 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10320 09:58:38.217665 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10321 09:58:38.220817 [ 0.000000] Zone ranges:
10322 09:58:38.227776 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10323 09:58:38.230788 [ 0.000000] DMA32 empty
10324 09:58:38.237480 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10325 09:58:38.241056 [ 0.000000] Movable zone start for each node
10326 09:58:38.244141 [ 0.000000] Early memory node ranges
10327 09:58:38.250630 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10328 09:58:38.257557 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10329 09:58:38.264378 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10330 09:58:38.267261 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10331 09:58:38.274174 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10332 09:58:38.280423 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10333 09:58:38.339350 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10334 09:58:38.345733 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10335 09:58:38.352149 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10336 09:58:38.355525 [ 0.000000] psci: probing for conduit method from DT.
10337 09:58:38.362259 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10338 09:58:38.365581 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10339 09:58:38.371996 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10340 09:58:38.375582 [ 0.000000] psci: SMC Calling Convention v1.2
10341 09:58:38.382172 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10342 09:58:38.385158 [ 0.000000] Detected VIPT I-cache on CPU0
10343 09:58:38.392125 [ 0.000000] CPU features: detected: GIC system register CPU interface
10344 09:58:38.398633 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10345 09:58:38.405132 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10346 09:58:38.411608 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10347 09:58:38.418592 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10348 09:58:38.428804 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10349 09:58:38.431820 [ 0.000000] alternatives: applying boot alternatives
10350 09:58:38.438750 [ 0.000000] Fallback order for Node 0: 0
10351 09:58:38.444939 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10352 09:58:38.448519 [ 0.000000] Policy zone: Normal
10353 09:58:38.471803 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12073290/extract-nfsrootfs-x41g6wi2,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10354 09:58:38.481388 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10355 09:58:38.492426 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10356 09:58:38.502076 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10357 09:58:38.508613 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10358 09:58:38.511573 <6>[ 0.000000] software IO TLB: area num 8.
10359 09:58:38.568525 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10360 09:58:38.717969 <6>[ 0.000000] Memory: 7952244K/8385536K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 400524K reserved, 32768K cma-reserved)
10361 09:58:38.724595 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10362 09:58:38.730934 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10363 09:58:38.734420 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10364 09:58:38.740877 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10365 09:58:38.747639 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10366 09:58:38.750999 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10367 09:58:38.760869 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10368 09:58:38.767215 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10369 09:58:38.773744 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10370 09:58:38.780773 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10371 09:58:38.783685 <6>[ 0.000000] GICv3: 608 SPIs implemented
10372 09:58:38.787189 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10373 09:58:38.794068 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10374 09:58:38.797094 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10375 09:58:38.804130 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10376 09:58:38.817362 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10377 09:58:38.826966 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10378 09:58:38.837137 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10379 09:58:38.844290 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10380 09:58:38.857826 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10381 09:58:38.864152 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10382 09:58:38.870741 <6>[ 0.009234] Console: colour dummy device 80x25
10383 09:58:38.880695 <6>[ 0.013950] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10384 09:58:38.887717 <6>[ 0.024391] pid_max: default: 32768 minimum: 301
10385 09:58:38.890751 <6>[ 0.029294] LSM: Security Framework initializing
10386 09:58:38.897289 <6>[ 0.034232] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10387 09:58:38.907222 <6>[ 0.042046] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10388 09:58:38.914269 <6>[ 0.051441] cblist_init_generic: Setting adjustable number of callback queues.
10389 09:58:38.920847 <6>[ 0.058883] cblist_init_generic: Setting shift to 3 and lim to 1.
10390 09:58:38.930788 <6>[ 0.065223] cblist_init_generic: Setting adjustable number of callback queues.
10391 09:58:38.934185 <6>[ 0.072696] cblist_init_generic: Setting shift to 3 and lim to 1.
10392 09:58:38.940380 <6>[ 0.079094] rcu: Hierarchical SRCU implementation.
10393 09:58:38.947520 <6>[ 0.084109] rcu: Max phase no-delay instances is 1000.
10394 09:58:38.953888 <6>[ 0.091131] EFI services will not be available.
10395 09:58:38.956807 <6>[ 0.096087] smp: Bringing up secondary CPUs ...
10396 09:58:38.965281 <6>[ 0.101132] Detected VIPT I-cache on CPU1
10397 09:58:38.971572 <6>[ 0.101202] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10398 09:58:38.978067 <6>[ 0.101234] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10399 09:58:38.981655 <6>[ 0.101567] Detected VIPT I-cache on CPU2
10400 09:58:38.988058 <6>[ 0.101621] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10401 09:58:38.998199 <6>[ 0.101639] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10402 09:58:39.001108 <6>[ 0.101900] Detected VIPT I-cache on CPU3
10403 09:58:39.008020 <6>[ 0.101945] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10404 09:58:39.014770 <6>[ 0.101958] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10405 09:58:39.017539 <6>[ 0.102262] CPU features: detected: Spectre-v4
10406 09:58:39.024427 <6>[ 0.102269] CPU features: detected: Spectre-BHB
10407 09:58:39.027936 <6>[ 0.102273] Detected PIPT I-cache on CPU4
10408 09:58:39.034254 <6>[ 0.102332] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10409 09:58:39.041261 <6>[ 0.102348] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10410 09:58:39.047730 <6>[ 0.102637] Detected PIPT I-cache on CPU5
10411 09:58:39.054192 <6>[ 0.102701] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10412 09:58:39.060669 <6>[ 0.102717] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10413 09:58:39.063889 <6>[ 0.102997] Detected PIPT I-cache on CPU6
10414 09:58:39.070812 <6>[ 0.103063] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10415 09:58:39.077423 <6>[ 0.103079] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10416 09:58:39.083988 <6>[ 0.103374] Detected PIPT I-cache on CPU7
10417 09:58:39.090334 <6>[ 0.103439] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10418 09:58:39.097285 <6>[ 0.103455] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10419 09:58:39.100195 <6>[ 0.103503] smp: Brought up 1 node, 8 CPUs
10420 09:58:39.107162 <6>[ 0.244846] SMP: Total of 8 processors activated.
10421 09:58:39.110280 <6>[ 0.249766] CPU features: detected: 32-bit EL0 Support
10422 09:58:39.120036 <6>[ 0.255129] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10423 09:58:39.126908 <6>[ 0.263929] CPU features: detected: Common not Private translations
10424 09:58:39.133230 <6>[ 0.270445] CPU features: detected: CRC32 instructions
10425 09:58:39.136626 <6>[ 0.275796] CPU features: detected: RCpc load-acquire (LDAPR)
10426 09:58:39.143600 <6>[ 0.281756] CPU features: detected: LSE atomic instructions
10427 09:58:39.149958 <6>[ 0.287537] CPU features: detected: Privileged Access Never
10428 09:58:39.156409 <6>[ 0.293316] CPU features: detected: RAS Extension Support
10429 09:58:39.163302 <6>[ 0.298925] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10430 09:58:39.166251 <6>[ 0.306146] CPU: All CPU(s) started at EL2
10431 09:58:39.173264 <6>[ 0.310463] alternatives: applying system-wide alternatives
10432 09:58:39.182566 <6>[ 0.321169] devtmpfs: initialized
10433 09:58:39.198250 <6>[ 0.330136] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10434 09:58:39.204623 <6>[ 0.340099] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10435 09:58:39.211433 <6>[ 0.348252] pinctrl core: initialized pinctrl subsystem
10436 09:58:39.214906 <6>[ 0.354917] DMI not present or invalid.
10437 09:58:39.221225 <6>[ 0.359330] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10438 09:58:39.231152 <6>[ 0.366131] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10439 09:58:39.237969 <6>[ 0.373711] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10440 09:58:39.247358 <6>[ 0.381928] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10441 09:58:39.250921 <6>[ 0.390174] audit: initializing netlink subsys (disabled)
10442 09:58:39.260714 <5>[ 0.395867] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10443 09:58:39.267732 <6>[ 0.396566] thermal_sys: Registered thermal governor 'step_wise'
10444 09:58:39.274203 <6>[ 0.403837] thermal_sys: Registered thermal governor 'power_allocator'
10445 09:58:39.277144 <6>[ 0.410092] cpuidle: using governor menu
10446 09:58:39.283608 <6>[ 0.421056] NET: Registered PF_QIPCRTR protocol family
10447 09:58:39.290550 <6>[ 0.426548] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10448 09:58:39.297004 <6>[ 0.433653] ASID allocator initialised with 32768 entries
10449 09:58:39.300318 <6>[ 0.440219] Serial: AMBA PL011 UART driver
10450 09:58:39.310491 <4>[ 0.448996] Trying to register duplicate clock ID: 134
10451 09:58:39.364880 <6>[ 0.506644] KASLR enabled
10452 09:58:39.378956 <6>[ 0.514387] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10453 09:58:39.386093 <6>[ 0.521402] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10454 09:58:39.392399 <6>[ 0.527891] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10455 09:58:39.398871 <6>[ 0.534897] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10456 09:58:39.405866 <6>[ 0.541385] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10457 09:58:39.412273 <6>[ 0.548391] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10458 09:58:39.418701 <6>[ 0.554878] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10459 09:58:39.425279 <6>[ 0.561882] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10460 09:58:39.428621 <6>[ 0.569389] ACPI: Interpreter disabled.
10461 09:58:39.437169 <6>[ 0.575803] iommu: Default domain type: Translated
10462 09:58:39.443697 <6>[ 0.580916] iommu: DMA domain TLB invalidation policy: strict mode
10463 09:58:39.446955 <5>[ 0.587576] SCSI subsystem initialized
10464 09:58:39.453557 <6>[ 0.591735] usbcore: registered new interface driver usbfs
10465 09:58:39.460179 <6>[ 0.597468] usbcore: registered new interface driver hub
10466 09:58:39.463853 <6>[ 0.603019] usbcore: registered new device driver usb
10467 09:58:39.470781 <6>[ 0.609124] pps_core: LinuxPPS API ver. 1 registered
10468 09:58:39.480629 <6>[ 0.614319] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10469 09:58:39.484061 <6>[ 0.623668] PTP clock support registered
10470 09:58:39.487043 <6>[ 0.627910] EDAC MC: Ver: 3.0.0
10471 09:58:39.494772 <6>[ 0.633066] FPGA manager framework
10472 09:58:39.501244 <6>[ 0.636745] Advanced Linux Sound Architecture Driver Initialized.
10473 09:58:39.504401 <6>[ 0.643513] vgaarb: loaded
10474 09:58:39.507924 <6>[ 0.646690] clocksource: Switched to clocksource arch_sys_counter
10475 09:58:39.514501 <5>[ 0.653124] VFS: Disk quotas dquot_6.6.0
10476 09:58:39.521495 <6>[ 0.657309] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10477 09:58:39.524577 <6>[ 0.664494] pnp: PnP ACPI: disabled
10478 09:58:39.532912 <6>[ 0.671154] NET: Registered PF_INET protocol family
10479 09:58:39.542559 <6>[ 0.676743] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10480 09:58:39.554068 <6>[ 0.689045] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10481 09:58:39.563656 <6>[ 0.697856] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10482 09:58:39.570373 <6>[ 0.705826] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10483 09:58:39.580072 <6>[ 0.714527] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10484 09:58:39.586654 <6>[ 0.724276] TCP: Hash tables configured (established 65536 bind 65536)
10485 09:58:39.593660 <6>[ 0.731133] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10486 09:58:39.603610 <6>[ 0.738333] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10487 09:58:39.609934 <6>[ 0.746029] NET: Registered PF_UNIX/PF_LOCAL protocol family
10488 09:58:39.613492 <6>[ 0.752202] RPC: Registered named UNIX socket transport module.
10489 09:58:39.619993 <6>[ 0.758356] RPC: Registered udp transport module.
10490 09:58:39.623448 <6>[ 0.763289] RPC: Registered tcp transport module.
10491 09:58:39.629751 <6>[ 0.768221] RPC: Registered tcp NFSv4.1 backchannel transport module.
10492 09:58:39.636632 <6>[ 0.774890] PCI: CLS 0 bytes, default 64
10493 09:58:39.639426 <6>[ 0.779291] Unpacking initramfs...
10494 09:58:39.663641 <6>[ 0.798802] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10495 09:58:39.673627 <6>[ 0.807460] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10496 09:58:39.677373 <6>[ 0.816315] kvm [1]: IPA Size Limit: 40 bits
10497 09:58:39.683244 <6>[ 0.820844] kvm [1]: GICv3: no GICV resource entry
10498 09:58:39.686854 <6>[ 0.825866] kvm [1]: disabling GICv2 emulation
10499 09:58:39.693606 <6>[ 0.830556] kvm [1]: GIC system register CPU interface enabled
10500 09:58:39.696642 <6>[ 0.836736] kvm [1]: vgic interrupt IRQ18
10501 09:58:39.703532 <6>[ 0.841092] kvm [1]: VHE mode initialized successfully
10502 09:58:39.710029 <5>[ 0.847561] Initialise system trusted keyrings
10503 09:58:39.716558 <6>[ 0.852392] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10504 09:58:39.724141 <6>[ 0.862515] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10505 09:58:39.730682 <5>[ 0.868892] NFS: Registering the id_resolver key type
10506 09:58:39.734297 <5>[ 0.874195] Key type id_resolver registered
10507 09:58:39.740508 <5>[ 0.878612] Key type id_legacy registered
10508 09:58:39.747392 <6>[ 0.882893] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10509 09:58:39.754060 <6>[ 0.889816] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10510 09:58:39.760649 <6>[ 0.897547] 9p: Installing v9fs 9p2000 file system support
10511 09:58:39.797175 <5>[ 0.935733] Key type asymmetric registered
10512 09:58:39.800459 <5>[ 0.940064] Asymmetric key parser 'x509' registered
10513 09:58:39.810336 <6>[ 0.945275] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10514 09:58:39.813552 <6>[ 0.952895] io scheduler mq-deadline registered
10515 09:58:39.817088 <6>[ 0.957665] io scheduler kyber registered
10516 09:58:39.836181 <6>[ 0.974655] EINJ: ACPI disabled.
10517 09:58:39.868363 <4>[ 1.000411] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10518 09:58:39.878351 <4>[ 1.011035] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10519 09:58:39.892982 <6>[ 1.031740] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10520 09:58:39.900978 <6>[ 1.039752] printk: console [ttyS0] disabled
10521 09:58:39.929236 <6>[ 1.064401] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10522 09:58:39.935607 <6>[ 1.073876] printk: console [ttyS0] enabled
10523 09:58:39.938888 <6>[ 1.073876] printk: console [ttyS0] enabled
10524 09:58:39.945750 <6>[ 1.082770] printk: bootconsole [mtk8250] disabled
10525 09:58:39.949062 <6>[ 1.082770] printk: bootconsole [mtk8250] disabled
10526 09:58:39.955649 <6>[ 1.094064] SuperH (H)SCI(F) driver initialized
10527 09:58:39.959093 <6>[ 1.099336] msm_serial: driver initialized
10528 09:58:39.973078 <6>[ 1.108325] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10529 09:58:39.983261 <6>[ 1.116871] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10530 09:58:39.989646 <6>[ 1.125414] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10531 09:58:39.999444 <6>[ 1.134042] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10532 09:58:40.009455 <6>[ 1.142751] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10533 09:58:40.016384 <6>[ 1.151473] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10534 09:58:40.026627 <6>[ 1.160014] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10535 09:58:40.032813 <6>[ 1.168820] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10536 09:58:40.042939 <6>[ 1.177364] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10537 09:58:40.054335 <6>[ 1.193033] loop: module loaded
10538 09:58:40.061317 <6>[ 1.199109] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10539 09:58:40.083939 <4>[ 1.222446] mtk-pmic-keys: Failed to locate of_node [id: -1]
10540 09:58:40.090788 <6>[ 1.229548] megasas: 07.719.03.00-rc1
10541 09:58:40.101176 <6>[ 1.239358] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10542 09:58:40.107519 <6>[ 1.246089] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10543 09:58:40.124363 <6>[ 1.262573] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10544 09:58:40.180130 <6>[ 1.312348] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10545 09:58:40.377850 <6>[ 1.516106] Freeing initrd memory: 17372K
10546 09:58:40.387805 <6>[ 1.526448] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10547 09:58:40.398717 <6>[ 1.537417] tun: Universal TUN/TAP device driver, 1.6
10548 09:58:40.402473 <6>[ 1.543473] thunder_xcv, ver 1.0
10549 09:58:40.405494 <6>[ 1.546980] thunder_bgx, ver 1.0
10550 09:58:40.408843 <6>[ 1.550469] nicpf, ver 1.0
10551 09:58:40.419311 <6>[ 1.554476] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10552 09:58:40.422808 <6>[ 1.561953] hns3: Copyright (c) 2017 Huawei Corporation.
10553 09:58:40.429146 <6>[ 1.567543] hclge is initializing
10554 09:58:40.432466 <6>[ 1.571124] e1000: Intel(R) PRO/1000 Network Driver
10555 09:58:40.439489 <6>[ 1.576254] e1000: Copyright (c) 1999-2006 Intel Corporation.
10556 09:58:40.442268 <6>[ 1.582266] e1000e: Intel(R) PRO/1000 Network Driver
10557 09:58:40.449130 <6>[ 1.587482] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10558 09:58:40.455550 <6>[ 1.593670] igb: Intel(R) Gigabit Ethernet Network Driver
10559 09:58:40.462487 <6>[ 1.599321] igb: Copyright (c) 2007-2014 Intel Corporation.
10560 09:58:40.468898 <6>[ 1.605157] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10561 09:58:40.475956 <6>[ 1.611675] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10562 09:58:40.478832 <6>[ 1.618142] sky2: driver version 1.30
10563 09:58:40.485622 <6>[ 1.623155] VFIO - User Level meta-driver version: 0.3
10564 09:58:40.492651 <6>[ 1.631410] usbcore: registered new interface driver usb-storage
10565 09:58:40.499648 <6>[ 1.637853] usbcore: registered new device driver onboard-usb-hub
10566 09:58:40.508794 <6>[ 1.647014] mt6397-rtc mt6359-rtc: registered as rtc0
10567 09:58:40.518792 <6>[ 1.652482] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-24T09:58:43 UTC (1700819923)
10568 09:58:40.521698 <6>[ 1.662047] i2c_dev: i2c /dev entries driver
10569 09:58:40.538246 <6>[ 1.673778] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10570 09:58:40.559347 <6>[ 1.697768] cpu cpu0: EM: created perf domain
10571 09:58:40.562565 <6>[ 1.702710] cpu cpu4: EM: created perf domain
10572 09:58:40.569983 <6>[ 1.708303] sdhci: Secure Digital Host Controller Interface driver
10573 09:58:40.576316 <6>[ 1.714737] sdhci: Copyright(c) Pierre Ossman
10574 09:58:40.583348 <6>[ 1.719695] Synopsys Designware Multimedia Card Interface Driver
10575 09:58:40.589470 <6>[ 1.726331] sdhci-pltfm: SDHCI platform and OF driver helper
10576 09:58:40.593289 <6>[ 1.726366] mmc0: CQHCI version 5.10
10577 09:58:40.599545 <6>[ 1.736688] ledtrig-cpu: registered to indicate activity on CPUs
10578 09:58:40.606312 <6>[ 1.743713] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10579 09:58:40.612648 <6>[ 1.750782] usbcore: registered new interface driver usbhid
10580 09:58:40.616075 <6>[ 1.756604] usbhid: USB HID core driver
10581 09:58:40.622960 <6>[ 1.760798] spi_master spi0: will run message pump with realtime priority
10582 09:58:40.667044 <6>[ 1.799011] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10583 09:58:40.686485 <6>[ 1.814994] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10584 09:58:40.693603 <6>[ 1.829610] cros-ec-spi spi0.0: Chrome EC device registered
10585 09:58:40.696505 <6>[ 1.835654] mmc0: Command Queue Engine enabled
10586 09:58:40.703474 <6>[ 1.840413] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10587 09:58:40.709892 <6>[ 1.848038] mmcblk0: mmc0:0001 DA4128 116 GiB
10588 09:58:40.722929 <6>[ 1.861468] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10589 09:58:40.732808 <6>[ 1.863223] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10590 09:58:40.739317 <6>[ 1.868769] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10591 09:58:40.742819 <6>[ 1.878029] NET: Registered PF_PACKET protocol family
10592 09:58:40.749851 <6>[ 1.882732] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10593 09:58:40.752775 <6>[ 1.887306] 9pnet: Installing 9P2000 support
10594 09:58:40.759589 <6>[ 1.893180] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10595 09:58:40.766068 <5>[ 1.896990] Key type dns_resolver registered
10596 09:58:40.769531 <6>[ 1.908330] registered taskstats version 1
10597 09:58:40.772385 <5>[ 1.912713] Loading compiled-in X.509 certificates
10598 09:58:40.803202 <4>[ 1.935423] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10599 09:58:40.813447 <4>[ 1.946342] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10600 09:58:40.820365 <3>[ 1.956891] debugfs: File 'uA_load' in directory '/' already present!
10601 09:58:40.826789 <3>[ 1.963652] debugfs: File 'min_uV' in directory '/' already present!
10602 09:58:40.833237 <3>[ 1.970289] debugfs: File 'max_uV' in directory '/' already present!
10603 09:58:40.840260 <3>[ 1.976998] debugfs: File 'constraint_flags' in directory '/' already present!
10604 09:58:40.851368 <3>[ 1.986580] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10605 09:58:40.861314 <6>[ 2.000106] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10606 09:58:40.868125 <6>[ 2.006865] xhci-mtk 11200000.usb: xHCI Host Controller
10607 09:58:40.875194 <6>[ 2.012374] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10608 09:58:40.884819 <6>[ 2.020228] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10609 09:58:40.891727 <6>[ 2.029666] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10610 09:58:40.898117 <6>[ 2.035731] xhci-mtk 11200000.usb: xHCI Host Controller
10611 09:58:40.905189 <6>[ 2.041206] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10612 09:58:40.911266 <6>[ 2.048850] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10613 09:58:40.918111 <6>[ 2.056664] hub 1-0:1.0: USB hub found
10614 09:58:40.921639 <6>[ 2.060697] hub 1-0:1.0: 1 port detected
10615 09:58:40.928409 <6>[ 2.064977] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10616 09:58:40.935431 <6>[ 2.073722] hub 2-0:1.0: USB hub found
10617 09:58:40.938300 <6>[ 2.077756] hub 2-0:1.0: 1 port detected
10618 09:58:40.946611 <6>[ 2.085367] mtk-msdc 11f70000.mmc: Got CD GPIO
10619 09:58:40.958077 <6>[ 2.093157] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10620 09:58:40.964547 <6>[ 2.101179] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10621 09:58:40.974287 <4>[ 2.109123] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10622 09:58:40.984480 <6>[ 2.118656] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10623 09:58:40.990844 <6>[ 2.126756] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10624 09:58:40.997753 <6>[ 2.134784] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10625 09:58:41.007769 <6>[ 2.142706] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10626 09:58:41.014185 <6>[ 2.150523] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10627 09:58:41.024131 <6>[ 2.158340] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10628 09:58:41.033941 <6>[ 2.168717] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10629 09:58:41.040988 <6>[ 2.177075] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10630 09:58:41.050786 <6>[ 2.185434] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10631 09:58:41.057868 <6>[ 2.193778] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10632 09:58:41.067756 <6>[ 2.202128] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10633 09:58:41.074177 <6>[ 2.210467] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10634 09:58:41.084235 <6>[ 2.218817] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10635 09:58:41.090826 <6>[ 2.227157] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10636 09:58:41.100595 <6>[ 2.235506] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10637 09:58:41.107845 <6>[ 2.243846] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10638 09:58:41.117754 <6>[ 2.252196] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10639 09:58:41.124128 <6>[ 2.260540] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10640 09:58:41.134117 <6>[ 2.268878] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10641 09:58:41.140924 <6>[ 2.277217] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10642 09:58:41.150720 <6>[ 2.285555] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10643 09:58:41.157528 <6>[ 2.294307] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10644 09:58:41.164195 <6>[ 2.301478] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10645 09:58:41.170507 <6>[ 2.308238] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10646 09:58:41.177532 <6>[ 2.314998] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10647 09:58:41.184062 <6>[ 2.321929] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10648 09:58:41.193844 <6>[ 2.328782] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10649 09:58:41.204005 <6>[ 2.337908] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10650 09:58:41.213431 <6>[ 2.347027] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10651 09:58:41.223362 <6>[ 2.356320] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10652 09:58:41.230419 <6>[ 2.365814] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10653 09:58:41.239884 <6>[ 2.375289] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10654 09:58:41.249975 <6>[ 2.384410] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10655 09:58:41.259963 <6>[ 2.393878] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10656 09:58:41.269846 <6>[ 2.402995] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10657 09:58:41.279379 <6>[ 2.412289] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10658 09:58:41.289830 <6>[ 2.422449] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10659 09:58:41.299578 <6>[ 2.433939] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10660 09:58:41.306186 <6>[ 2.443624] Trying to probe devices needed for running init ...
10661 09:58:41.327355 <6>[ 2.462961] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10662 09:58:41.355771 <6>[ 2.494492] hub 2-1:1.0: USB hub found
10663 09:58:41.359326 <6>[ 2.499023] hub 2-1:1.0: 3 ports detected
10664 09:58:41.367587 <6>[ 2.506397] hub 2-1:1.0: USB hub found
10665 09:58:41.370987 <6>[ 2.510798] hub 2-1:1.0: 3 ports detected
10666 09:58:41.479506 <6>[ 2.614902] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10667 09:58:41.634219 <6>[ 2.772805] hub 1-1:1.0: USB hub found
10668 09:58:41.637179 <6>[ 2.777279] hub 1-1:1.0: 4 ports detected
10669 09:58:41.646684 <6>[ 2.785601] hub 1-1:1.0: USB hub found
10670 09:58:41.650174 <6>[ 2.790117] hub 1-1:1.0: 4 ports detected
10671 09:58:41.719888 <6>[ 2.855210] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10672 09:58:41.971729 <6>[ 3.107004] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10673 09:58:42.104083 <6>[ 3.242796] hub 1-1.4:1.0: USB hub found
10674 09:58:42.107074 <6>[ 3.247462] hub 1-1.4:1.0: 2 ports detected
10675 09:58:42.117202 <6>[ 3.256027] hub 1-1.4:1.0: USB hub found
10676 09:58:42.120131 <6>[ 3.260633] hub 1-1.4:1.0: 2 ports detected
10677 09:58:42.419397 <6>[ 3.555016] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10678 09:58:42.611249 <6>[ 3.746986] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10679 09:58:53.592455 <6>[ 14.735989] ALSA device list:
10680 09:58:53.599218 <6>[ 14.739280] No soundcards found.
10681 09:58:53.607291 <6>[ 14.747204] Freeing unused kernel memory: 8384K
10682 09:58:53.610181 <6>[ 14.752192] Run /init as init process
10683 09:58:53.621392 Loading, please wait...
10684 09:58:53.641832 Starting version 247.3-7+deb11u2
10685 09:58:53.874812 <6>[ 15.011778] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10686 09:58:53.882971 <6>[ 15.023004] remoteproc remoteproc0: scp is available
10687 09:58:53.892654 <3>[ 15.024035] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10688 09:58:53.899257 <6>[ 15.024903] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10689 09:58:53.902672 <6>[ 15.028629] remoteproc remoteproc0: powering up scp
10690 09:58:53.912546 <3>[ 15.036434] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10691 09:58:53.919132 <6>[ 15.039732] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10692 09:58:53.929188 <6>[ 15.039758] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10693 09:58:53.936328 <6>[ 15.039768] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10694 09:58:53.946849 <6>[ 15.043994] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10695 09:58:53.953314 <4>[ 15.044642] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10696 09:58:53.959985 <3>[ 15.049184] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10697 09:58:53.966678 <6>[ 15.049480] mc: Linux media interface: v0.10
10698 09:58:53.970081 <6>[ 15.051843] usbcore: registered new interface driver r8152
10699 09:58:53.980064 <4>[ 15.054813] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10700 09:58:53.983199 <4>[ 15.054813] Fallback method does not support PEC.
10701 09:58:53.990131 <6>[ 15.057366] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10702 09:58:53.999811 <3>[ 15.064958] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10703 09:58:54.006325 <4>[ 15.074621] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10704 09:58:54.012799 <6>[ 15.074951] videodev: Linux video capture interface: v2.00
10705 09:58:54.019589 <3>[ 15.082219] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10706 09:58:54.026101 <3>[ 15.082226] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10707 09:58:54.036042 <3>[ 15.082236] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10708 09:58:54.046321 <3>[ 15.083644] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10709 09:58:54.052682 <3>[ 15.104713] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10710 09:58:54.062478 <3>[ 15.106102] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10711 09:58:54.069573 <3>[ 15.106228] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10712 09:58:54.076114 <6>[ 15.154940] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10713 09:58:54.085833 <3>[ 15.156881] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10714 09:58:54.092622 <6>[ 15.164109] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10715 09:58:54.099000 <6>[ 15.164119] pci_bus 0000:00: root bus resource [bus 00-ff]
10716 09:58:54.105950 <6>[ 15.164129] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10717 09:58:54.115426 <6>[ 15.164136] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10718 09:58:54.121801 <6>[ 15.164180] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10719 09:58:54.128673 <6>[ 15.164206] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10720 09:58:54.131815 <6>[ 15.164292] pci 0000:00:00.0: supports D1 D2
10721 09:58:54.138473 <6>[ 15.164296] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10722 09:58:54.148596 <6>[ 15.166195] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10723 09:58:54.155008 <3>[ 15.172999] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10724 09:58:54.164820 <3>[ 15.173002] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10725 09:58:54.171613 <3>[ 15.173030] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10726 09:58:54.178241 <6>[ 15.181244] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10727 09:58:54.188281 <3>[ 15.189868] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10728 09:58:54.194479 <3>[ 15.189871] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10729 09:58:54.201529 <3>[ 15.189873] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10730 09:58:54.211418 <3>[ 15.189876] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10731 09:58:54.221053 <6>[ 15.192214] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10732 09:58:54.230965 <6>[ 15.192599] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10733 09:58:54.237579 <4>[ 15.194636] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10734 09:58:54.247447 <4>[ 15.194642] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10735 09:58:54.253858 <6>[ 15.198683] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10736 09:58:54.260536 <6>[ 15.201293] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10737 09:58:54.270711 <6>[ 15.201370] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10738 09:58:54.276965 <6>[ 15.201378] remoteproc remoteproc0: remote processor scp is now up
10739 09:58:54.287021 <6>[ 15.203358] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10740 09:58:54.293415 <3>[ 15.206748] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10741 09:58:54.300179 <6>[ 15.214832] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10742 09:58:54.309899 <6>[ 15.230276] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10743 09:58:54.316492 <6>[ 15.230558] usbcore: registered new interface driver cdc_ether
10744 09:58:54.323166 <6>[ 15.237132] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10745 09:58:54.326557 <6>[ 15.237679] Bluetooth: Core ver 2.22
10746 09:58:54.333011 <6>[ 15.237701] usbcore: registered new interface driver r8153_ecm
10747 09:58:54.340065 <6>[ 15.237763] NET: Registered PF_BLUETOOTH protocol family
10748 09:58:54.346612 <6>[ 15.237765] Bluetooth: HCI device and connection manager initialized
10749 09:58:54.349507 <6>[ 15.237802] Bluetooth: HCI socket layer initialized
10750 09:58:54.356341 <6>[ 15.237813] Bluetooth: L2CAP socket layer initialized
10751 09:58:54.359386 <6>[ 15.237832] Bluetooth: SCO socket layer initialized
10752 09:58:54.366052 <6>[ 15.260048] r8152 2-1.3:1.0 eth0: v1.12.13
10753 09:58:54.373133 <6>[ 15.261677] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10754 09:58:54.385720 <6>[ 15.262694] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10755 09:58:54.388989 <6>[ 15.262786] usbcore: registered new interface driver uvcvideo
10756 09:58:54.395626 <6>[ 15.266260] pci 0000:01:00.0: supports D1 D2
10757 09:58:54.402236 <6>[ 15.275711] usbcore: registered new interface driver btusb
10758 09:58:54.412448 <4>[ 15.275908] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10759 09:58:54.419067 <3>[ 15.275919] Bluetooth: hci0: Failed to load firmware file (-2)
10760 09:58:54.422023 <3>[ 15.275923] Bluetooth: hci0: Failed to set up firmware (-2)
10761 09:58:54.431982 <4>[ 15.275927] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10762 09:58:54.441902 <6>[ 15.276064] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10763 09:58:54.448817 <6>[ 15.278428] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10764 09:58:54.455420 <6>[ 15.285815] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10765 09:58:54.461831 <6>[ 15.294076] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10766 09:58:54.468916 <6>[ 15.302876] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10767 09:58:54.475311 <6>[ 15.613398] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10768 09:58:54.484743 <6>[ 15.621478] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10769 09:58:54.491444 <6>[ 15.629476] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10770 09:58:54.501894 <6>[ 15.637475] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10771 09:58:54.508366 <6>[ 15.645476] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10772 09:58:54.514638 <6>[ 15.653477] pci 0000:00:00.0: PCI bridge to [bus 01]
10773 09:58:54.521516 <6>[ 15.658693] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10774 09:58:54.528095 <6>[ 15.666842] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10775 09:58:54.535077 <6>[ 15.673679] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10776 09:58:54.540894 <6>[ 15.680382] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10777 09:58:54.559713 <5>[ 15.696944] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10778 09:58:54.577189 <5>[ 15.714303] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10779 09:58:54.584098 <4>[ 15.721255] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10780 09:58:54.590582 <6>[ 15.730152] cfg80211: failed to load regulatory.db
10781 09:58:54.650439 <6>[ 15.787599] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10782 09:58:54.657055 <6>[ 15.795165] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10783 09:58:54.682058 <6>[ 15.822010] mt7921e 0000:01:00.0: ASIC revision: 79610010
10784 09:58:54.789688 <4>[ 15.923300] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10785 09:58:54.803055 Begin: Loading essential drivers ... done.
10786 09:58:54.806417 Begin: Running /scripts/init-premount ... done.
10787 09:58:54.813477 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10788 09:58:54.823230 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10789 09:58:54.826713 Device /sys/class/net/enx0024323078ff found
10790 09:58:54.826810 done.
10791 09:58:54.886068 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10792 09:58:54.913693 <4>[ 16.047671] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10793 09:58:55.032996 <4>[ 16.166652] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10794 09:58:55.152770 <4>[ 16.286619] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10795 09:58:55.272592 <4>[ 16.406577] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10796 09:58:55.392690 <4>[ 16.526552] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10797 09:58:55.513434 <4>[ 16.646730] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10798 09:58:55.633222 <4>[ 16.766608] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10799 09:58:55.753048 <4>[ 16.886654] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10800 09:58:55.815249 <6>[ 16.955642] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10801 09:58:55.872717 <4>[ 17.006569] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10802 09:58:55.984114 <3>[ 17.124479] mt7921e 0000:01:00.0: hardware init failed
10803 09:58:56.012349 IP-Config: no response after 2 secs - giving up
10804 09:58:56.053921 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10805 09:58:56.057353 IP-Config: enx0024323078ff complete (dhcp from 192.168.201.1):
10806 09:58:56.066828 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10807 09:58:56.073590 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10808 09:58:56.080331 host : mt8192-asurada-spherion-r0-cbg-8
10809 09:58:56.086661 domain : lava-rack
10810 09:58:56.090010 rootserver: 192.168.201.1 rootpath:
10811 09:58:56.090107 filename :
10812 09:58:56.169344 done.
10813 09:58:56.176624 Begin: Running /scripts/nfs-bottom ... done.
10814 09:58:56.192441 Begin: Running /scripts/init-bottom ... done.
10815 09:58:57.398295 <6>[ 18.538789] NET: Registered PF_INET6 protocol family
10816 09:58:57.405599 <6>[ 18.546231] Segment Routing with IPv6
10817 09:58:57.408992 <6>[ 18.550235] In-situ OAM (IOAM) with IPv6
10818 09:58:57.534127 <30>[ 18.654815] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10819 09:58:57.537406 <30>[ 18.679125] systemd[1]: Detected architecture arm64.
10820 09:58:57.558241
10821 09:58:57.561675 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10822 09:58:57.561768
10823 09:58:57.576530 <30>[ 18.717173] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10824 09:58:58.447190 <30>[ 19.584136] systemd[1]: Queued start job for default target Graphical Interface.
10825 09:58:58.480662 <30>[ 19.621454] systemd[1]: Created slice system-getty.slice.
10826 09:58:58.487324 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10827 09:58:58.503623 <30>[ 19.644461] systemd[1]: Created slice system-modprobe.slice.
10828 09:58:58.510615 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10829 09:58:58.527755 <30>[ 19.668231] systemd[1]: Created slice system-serial\x2dgetty.slice.
10830 09:58:58.537609 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10831 09:58:58.551484 <30>[ 19.692056] systemd[1]: Created slice User and Session Slice.
10832 09:58:58.558023 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10833 09:58:58.578422 <30>[ 19.715821] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10834 09:58:58.588681 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10835 09:58:58.606334 <30>[ 19.743741] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10836 09:58:58.612980 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10837 09:58:58.637271 <30>[ 19.771173] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10838 09:58:58.643746 <30>[ 19.783293] systemd[1]: Reached target Local Encrypted Volumes.
10839 09:58:58.650514 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10840 09:58:58.666625 <30>[ 19.807208] systemd[1]: Reached target Paths.
10841 09:58:58.670093 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10842 09:58:58.686685 <30>[ 19.826971] systemd[1]: Reached target Remote File Systems.
10843 09:58:58.692907 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10844 09:58:58.710534 <30>[ 19.851351] systemd[1]: Reached target Slices.
10845 09:58:58.717091 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10846 09:58:58.730564 <30>[ 19.871004] systemd[1]: Reached target Swap.
10847 09:58:58.733539 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10848 09:58:58.753971 <30>[ 19.891503] systemd[1]: Listening on initctl Compatibility Named Pipe.
10849 09:58:58.760757 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10850 09:58:58.767624 <30>[ 19.907736] systemd[1]: Listening on Journal Audit Socket.
10851 09:58:58.774126 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10852 09:58:58.791876 <30>[ 19.932342] systemd[1]: Listening on Journal Socket (/dev/log).
10853 09:58:58.798299 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10854 09:58:58.815054 <30>[ 19.955544] systemd[1]: Listening on Journal Socket.
10855 09:58:58.821371 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10856 09:58:58.839587 <30>[ 19.976656] systemd[1]: Listening on Network Service Netlink Socket.
10857 09:58:58.845782 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10858 09:58:58.861727 <30>[ 20.002079] systemd[1]: Listening on udev Control Socket.
10859 09:58:58.868340 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10860 09:58:58.882937 <30>[ 20.023418] systemd[1]: Listening on udev Kernel Socket.
10861 09:58:58.889186 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10862 09:58:58.946708 <30>[ 20.087223] systemd[1]: Mounting Huge Pages File System...
10863 09:58:58.953028 Mounting [0;1;39mHuge Pages File System[0m...
10864 09:58:58.970477 <30>[ 20.111271] systemd[1]: Mounting POSIX Message Queue File System...
10865 09:58:58.977672 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10866 09:58:58.999550 <30>[ 20.140176] systemd[1]: Mounting Kernel Debug File System...
10867 09:58:59.006132 Mounting [0;1;39mKernel Debug File System[0m...
10868 09:58:59.026381 <30>[ 20.163693] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10869 09:58:59.062710 <30>[ 20.199894] systemd[1]: Starting Create list of static device nodes for the current kernel...
10870 09:58:59.069469 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10871 09:58:59.089463 <30>[ 20.230421] systemd[1]: Starting Load Kernel Module configfs...
10872 09:58:59.096347 Starting [0;1;39mLoad Kernel Module configfs[0m...
10873 09:58:59.119312 <30>[ 20.259773] systemd[1]: Starting Load Kernel Module drm...
10874 09:58:59.125492 Starting [0;1;39mLoad Kernel Module drm[0m...
10875 09:58:59.146868 <30>[ 20.287794] systemd[1]: Starting Load Kernel Module fuse...
10876 09:58:59.153788 Starting [0;1;39mLoad Kernel Module fuse[0m...
10877 09:58:59.187136 <30>[ 20.324332] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10878 09:58:59.201984 <30>[ 20.342301] systemd[1]: Starting Journal Service...
10879 09:58:59.208185 Starting [0;1;39mJournal Service[0m...
10880 09:58:59.211218 <6>[ 20.353689] fuse: init (API version 7.37)
10881 09:58:59.231552 <30>[ 20.372163] systemd[1]: Starting Load Kernel Modules...
10882 09:58:59.238201 Starting [0;1;39mLoad Kernel Modules[0m...
10883 09:58:59.256776 <30>[ 20.393803] systemd[1]: Starting Remount Root and Kernel File Systems...
10884 09:58:59.263074 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10885 09:58:59.287069 <30>[ 20.427693] systemd[1]: Starting Coldplug All udev Devices...
10886 09:58:59.293649 Starting [0;1;39mColdplug All udev Devices[0m...
10887 09:58:59.314569 <30>[ 20.455299] systemd[1]: Mounted Huge Pages File System.
10888 09:58:59.320966 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10889 09:58:59.339032 <30>[ 20.479618] systemd[1]: Mounted POSIX Message Queue File System.
10890 09:58:59.345927 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10891 09:58:59.362799 <30>[ 20.503327] systemd[1]: Mounted Kernel Debug File System.
10892 09:58:59.372690 [[0;32m OK [<3>[ 20.510574] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 09:58:59.379658 0m] Mounted [0;1;39mKernel Debug File System[0m.
10894 09:58:59.399584 <30>[ 20.536448] systemd[1]: Finished Create list of static device nodes for the current kernel.
10895 09:58:59.412495 [[0;32m OK [0m] Finished [0<3>[ 20.546722] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10896 09:58:59.416431 ;1;39mCreate list of st… nodes for the current kernel[0m.
10897 09:58:59.431186 <30>[ 20.571978] systemd[1]: modprobe@configfs.service: Succeeded.
10898 09:58:59.438365 <30>[ 20.579010] systemd[1]: Finished Load Kernel Module configfs.
10899 09:58:59.444588 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10900 09:58:59.464447 <30>[ 20.605056] systemd[1]: modprobe@drm.service: Succeeded.
10901 09:58:59.471475 <30>[ 20.612273] systemd[1]: Finished Load Kernel Module drm.
10902 09:58:59.481527 [[0;32m OK [<3>[ 20.619525] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10903 09:58:59.487858 0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10904 09:58:59.503239 <30>[ 20.643689] systemd[1]: modprobe@fuse.service: Succeeded.
10905 09:58:59.509885 <30>[ 20.650605] systemd[1]: Finished Load Kernel Module fuse.
10906 09:58:59.519924 <3>[ 20.652002] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10907 09:58:59.526382 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10908 09:58:59.545588 <30>[ 20.685713] systemd[1]: Finished Load Kernel Modules.
10909 09:58:59.555204 <3>[ 20.687596] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10910 09:58:59.559175 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10911 09:58:59.577612 <30>[ 20.717213] systemd[1]: Finished Remount Root and Kernel File Systems.
10912 09:58:59.587059 <3>[ 20.723039] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 09:58:59.593685 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10914 09:58:59.616869 <3>[ 20.754333] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10915 09:58:59.634503 <30>[ 20.774895] systemd[1]: Mounting FUSE Control File System...
10916 09:58:59.648479 Mounting [0;1;39mFUSE Control File Sys<3>[ 20.784605] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10917 09:58:59.648608 tem[0m...
10918 09:58:59.666693 <30>[ 20.807485] systemd[1]: Mounting Kernel Configuration File System...
10919 09:58:59.680917 Mounting [0;1;39mKernel Configuration <3>[ 20.817451] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10920 09:58:59.683911 File System[0m...
10921 09:58:59.706778 <30>[ 20.843665] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10922 09:58:59.716971 <3>[ 20.849408] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 09:58:59.726465 <30>[ 20.852871] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10924 09:58:59.734751 <30>[ 20.875162] systemd[1]: Starting Load/Save Random Seed...
10925 09:58:59.741728 Starting [0;1;39mLoad/Save Random Seed[0m...
10926 09:58:59.756855 <30>[ 20.897566] systemd[1]: Starting Apply Kernel Variables...
10927 09:58:59.763871 Starting [0;1;39mApply Kernel Variables[0m...
10928 09:58:59.783244 <30>[ 20.923516] systemd[1]: Starting Create System Users...
10929 09:58:59.789634 Starting [0;1;39mCreate System Users[0m...
10930 09:58:59.802710 <4>[ 20.934600] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10931 09:58:59.813115 <3>[ 20.950646] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10932 09:58:59.816476 <30>[ 20.952718] systemd[1]: Started Journal Service.
10933 09:58:59.822865 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10934 09:58:59.850620 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10935 09:58:59.862107 See 'systemctl status systemd-udev-trigger.service' for details.
10936 09:58:59.879105 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10937 09:58:59.894739 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10938 09:58:59.911114 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10939 09:58:59.928141 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10940 09:58:59.944521 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10941 09:58:59.998562 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10942 09:59:00.016795 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10943 09:59:00.062687 <46>[ 21.200364] systemd-journald[300]: Received client request to flush runtime journal.
10944 09:59:00.102195 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10945 09:59:00.119731 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10946 09:59:00.138756 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10947 09:59:00.195522 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10948 09:59:01.488304 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10949 09:59:01.531214 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10950 09:59:01.589419 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10951 09:59:01.648562 Starting [0;1;39mNetwork Service[0m...
10952 09:59:01.950467 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10953 09:59:01.972691 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10954 09:59:02.018227 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10955 09:59:02.318177 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10956 09:59:02.337567 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10957 09:59:02.370851 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10958 09:59:02.396113 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10959 09:59:02.410878 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10960 09:59:02.430806 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10961 09:59:02.456722 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10962 09:59:02.510706 Starting [0;1;39mNetwork Name Resolution[0m...
10963 09:59:02.540302 Starting [0;1;39mNetwork Time Synchronization[0m...
10964 09:59:02.557423 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10965 09:59:02.606575 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10966 09:59:02.802185 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10967 09:59:02.823041 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10968 09:59:02.845678 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10969 09:59:02.861903 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10970 09:59:02.878072 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10971 09:59:02.993474 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10972 09:59:03.027414 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10973 09:59:03.067876 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10974 09:59:03.098124 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10975 09:59:03.110278 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10976 09:59:03.377706 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10977 09:59:03.380578 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10978 09:59:03.398264 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10979 09:59:03.462814 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10980 09:59:03.879051 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10981 09:59:04.246906 Starting [0;1;39mUser Login Management[0m...
10982 09:59:04.265419 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10983 09:59:04.284182 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10984 09:59:04.301972 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10985 09:59:04.351193 Starting [0;1;39mPermit User Sessions[0m...
10986 09:59:04.475691 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10987 09:59:04.526835 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10988 09:59:04.575099 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10989 09:59:04.594559 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10990 09:59:04.617449 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10991 09:59:04.637872 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10992 09:59:04.659926 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10993 09:59:04.678627 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10994 09:59:04.723167 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10995 09:59:04.772777 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10996 09:59:04.857604
10997 09:59:04.857753
10998 09:59:04.860950 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10999 09:59:04.861028
11000 09:59:04.864325 debian-bullseye-arm64 login: root (automatic login)
11001 09:59:04.864428
11002 09:59:04.864523
11003 09:59:05.250342 Linux debian-bullseye-arm64 6.1.62-cip9 #1 SMP PREEMPT Fri Nov 24 09:44:51 UTC 2023 aarch64
11004 09:59:05.250502
11005 09:59:05.256623 The programs included with the Debian GNU/Linux system are free software;
11006 09:59:05.263056 the exact distribution terms for each program are described in the
11007 09:59:05.266653 individual files in /usr/share/doc/*/copyright.
11008 09:59:05.266765
11009 09:59:05.273145 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11010 09:59:05.276589 permitted by applicable law.
11011 09:59:05.364899 Matched prompt #10: / #
11013 09:59:05.365276 Setting prompt string to ['/ #']
11014 09:59:05.365415 end: 2.2.5.1 login-action (duration 00:00:27) [common]
11016 09:59:05.365770 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
11017 09:59:05.365902 start: 2.2.6 expect-shell-connection (timeout 00:03:21) [common]
11018 09:59:05.366015 Setting prompt string to ['/ #']
11019 09:59:05.366112 Forcing a shell prompt, looking for ['/ #']
11021 09:59:05.416375 / #
11022 09:59:05.416519 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11023 09:59:05.416639 Waiting using forced prompt support (timeout 00:02:30)
11024 09:59:05.421603
11025 09:59:05.421905 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11026 09:59:05.422031 start: 2.2.7 export-device-env (timeout 00:03:21) [common]
11028 09:59:05.522382 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12073290/extract-nfsrootfs-x41g6wi2'
11029 09:59:05.527527 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12073290/extract-nfsrootfs-x41g6wi2'
11031 09:59:05.628107 / # export NFS_SERVER_IP='192.168.201.1'
11032 09:59:05.633471 export NFS_SERVER_IP='192.168.201.1'
11033 09:59:05.633791 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11034 09:59:05.633891 end: 2.2 depthcharge-retry (duration 00:01:40) [common]
11035 09:59:05.633981 end: 2 depthcharge-action (duration 00:01:40) [common]
11036 09:59:05.634070 start: 3 lava-test-retry (timeout 00:30:00) [common]
11037 09:59:05.634215 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
11038 09:59:05.634320 Using namespace: common
11040 09:59:05.734684 / # #
11041 09:59:05.734857 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
11042 09:59:05.739602 #
11043 09:59:05.739892 Using /lava-12073290
11045 09:59:05.840223 / # export SHELL=/bin/sh
11046 09:59:05.845629 export SHELL=/bin/sh
11048 09:59:05.946192 / # . /lava-12073290/environment
11049 09:59:05.951647 . /lava-12073290/environment
11051 09:59:06.057984 / # /lava-12073290/bin/lava-test-runner /lava-12073290/0
11052 09:59:06.058145 Test shell timeout: 10s (minimum of the action and connection timeout)
11053 09:59:06.063456 /lava-12073290/bin/lava-test-runner /lava-12073290/0
11054 09:59:06.326604 + export TESTRUN_ID=0_lc-compliance
11055 09:59:06.333246 + cd /lava-12073290/0/tests/0_lc-compliance
11056 09:59:06.333362 + cat uuid
11057 09:59:06.342667 + UUID=12073290_1.6.2.3.1
11058 09:59:06.342776 + set +x
11059 09:59:06.349006 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 12073290_1.6.2.3.1>
11060 09:59:06.349291 Received signal: <STARTRUN> 0_lc-compliance 12073290_1.6.2.3.1
11061 09:59:06.349395 Starting test lava.0_lc-compliance (12073290_1.6.2.3.1)
11062 09:59:06.349524 Skipping test definition patterns.
11063 09:59:06.352373 + /usr/bin/lc-compliance-parser.sh
11064 09:59:07.641651 [0:00:28.661582155] [410] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:297 [0mlibcamera v0.0.0+1-1f607da9
11065 09:59:07.645496 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
11066 09:59:07.659358 [0:00:28.679631385] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11067 09:59:07.719494 [0:00:28.739295693] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11068 09:59:07.762422 [==========] Running 120 tests from 1 test suite.
11069 09:59:07.777242 [0:00:28.796992693] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11070 09:59:07.830455 [0:00:28.850297462] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11071 09:59:07.865715 [----------] Global test environment set-up.
11072 09:59:07.966213 [----------] 120 tests from CaptureTests/SingleStream
11073 09:59:08.056836 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11074 09:59:08.130343 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11075 09:59:08.130674 Received signal: <TESTSET> START CaptureTests/SingleStream
11076 09:59:08.130768 Starting test_set CaptureTests/SingleStream
11077 09:59:08.133808 Camera needs 4 requests, can't test only 1
11078 09:59:08.234759 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11079 09:59:08.256863 [0:00:29.276888539] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11080 09:59:08.341135
11081 09:59:08.447280 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (61 ms)
11082 09:59:08.576503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11083 09:59:08.576867 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11085 09:59:08.597785 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11086 09:59:08.666532 Camera needs 4 requests, can't test only 2
11087 09:59:08.771897 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11088 09:59:08.861310
11089 09:59:08.950147 [0:00:29.970316078] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11090 09:59:08.970863 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (57 ms)
11091 09:59:09.079760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11092 09:59:09.080066 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11094 09:59:09.100355 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11095 09:59:09.157630 Camera needs 4 requests, can't test only 3
11096 09:59:09.246809 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11097 09:59:09.348791
11098 09:59:09.460468 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (52 ms)
11099 09:59:09.583144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11100 09:59:09.583890 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11102 09:59:09.605806 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11103 09:59:09.675677 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (428 ms)
11104 09:59:09.797921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11105 09:59:09.798678 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11107 09:59:09.823401 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11108 09:59:09.893796 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (692 ms)
11109 09:59:10.016512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11110 09:59:10.017089 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11112 09:59:10.039484 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11113 09:59:10.196867 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (1256 ms)
11114 09:59:10.206959 [0:00:31.226609539] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11115 09:59:10.309063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11116 09:59:10.309404 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11118 09:59:10.329418 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11119 09:59:12.011642 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (1815 ms)
11120 09:59:12.021316 [0:00:33.042794693] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11121 09:59:12.122820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11122 09:59:12.123119 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11124 09:59:12.142698 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11125 09:59:14.738472 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (2727 ms)
11126 09:59:14.747965 [0:00:35.769677155] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11127 09:59:14.838347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11128 09:59:14.838688 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11130 09:59:14.855775 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11131 09:59:18.934628 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (4197 ms)
11132 09:59:18.943988 [0:00:39.965912924] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11133 09:59:19.046946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11134 09:59:19.047263 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11136 09:59:19.066112 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11137 09:59:25.012273 <6>[ 46.158969] vpu: disabling
11138 09:59:25.015460 <6>[ 46.162198] vproc2: disabling
11139 09:59:25.019418 <6>[ 46.166184] vproc1: disabling
11140 09:59:25.022893 <6>[ 46.169816] vaud18: disabling
11141 09:59:25.030591 <6>[ 46.174404] vsram_others: disabling
11142 09:59:25.033973 <6>[ 46.178850] va09: disabling
11143 09:59:25.037209 <6>[ 46.182112] vsram_md: disabling
11144 09:59:25.040616 <6>[ 46.186210] Vgpu: disabling
11145 09:59:25.509710 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (6576 ms)
11146 09:59:25.519637 [0:00:46.542446771] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11147 09:59:25.571916 [0:00:46.594128694] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11148 09:59:25.618182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11149 09:59:25.618518 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11151 09:59:25.628109 [0:00:46.649669079] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11152 09:59:25.635645 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11153 09:59:25.681770 [0:00:46.703996540] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11154 09:59:25.695154 Camera needs 4 requests, can't test only 1
11155 09:59:25.781924 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11156 09:59:25.864081
11157 09:59:25.952144 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (54 ms)
11158 09:59:26.046635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11159 09:59:26.046968 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11161 09:59:26.063732 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11162 09:59:26.119171 Camera needs 4 requests, can't test only 2
11163 09:59:26.207117 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11164 09:59:26.291085
11165 09:59:26.376086 [0:00:47.398599386] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11166 09:59:26.388714 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (53 ms)
11167 09:59:26.490477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11168 09:59:26.490807 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11170 09:59:26.508782 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11171 09:59:26.567509 Camera needs 4 requests, can't test only 3
11172 09:59:26.647997 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11173 09:59:26.729117
11174 09:59:26.827432 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (55 ms)
11175 09:59:26.931086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11176 09:59:26.931443 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11178 09:59:26.949579 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11179 09:59:27.007617 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (695 ms)
11180 09:59:27.102605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11181 09:59:27.102976 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11183 09:59:27.119091 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11184 09:59:27.275188 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (908 ms)
11185 09:59:27.288357 [0:00:48.306489463] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11186 09:59:27.376508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11187 09:59:27.376829 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11189 09:59:27.394079 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11190 09:59:28.529977 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (1255 ms)
11191 09:59:28.542702 [0:00:49.561261771] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11192 09:59:28.637907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11193 09:59:28.638222 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11195 09:59:28.654870 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11196 09:59:30.345313 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (1816 ms)
11197 09:59:30.358549 [0:00:51.376885233] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11198 09:59:30.444348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11199 09:59:30.444711 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11201 09:59:30.461422 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11202 09:59:33.071641 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (2727 ms)
11203 09:59:33.085086 [0:00:54.104995464] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11204 09:59:33.166487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11205 09:59:33.166812 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11207 09:59:33.182597 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11208 09:59:37.266117 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (4195 ms)
11209 09:59:37.279621 [0:00:58.300065123] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11210 09:59:37.373797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11211 09:59:37.374111 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11213 09:59:37.389630 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11214 09:59:43.842339 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (6575 ms)
11215 09:59:43.855730 [0:01:04.875613536] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11216 09:59:43.903868 [0:01:04.926975509] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11217 09:59:43.955524 [0:01:04.978830675] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11218 09:59:43.968635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11219 09:59:43.969375 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11221 09:59:43.988783 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11222 09:59:44.006933 [0:01:05.030349636] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11223 09:59:44.059783 Camera needs 4 requests, can't test only 1
11224 09:59:44.159428 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11225 09:59:44.257329
11226 09:59:44.363154 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (53 ms)
11227 09:59:44.473320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11228 09:59:44.474210 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11230 09:59:44.493339 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11231 09:59:44.562776 Camera needs 4 requests, can't test only 2
11232 09:59:44.656740 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11233 09:59:44.701047 [0:01:05.724145212] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11234 09:59:44.755206
11235 09:59:44.860042 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (51 ms)
11236 09:59:44.969442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11237 09:59:44.969754 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11239 09:59:44.986969 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11240 09:59:45.048067 Camera needs 4 requests, can't test only 3
11241 09:59:45.132794 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11242 09:59:45.215784
11243 09:59:45.302926 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (52 ms)
11244 09:59:45.394465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11245 09:59:45.394790 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11247 09:59:45.411134 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11248 09:59:45.467375 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (694 ms)
11249 09:59:45.563493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11250 09:59:45.563871 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11252 09:59:45.580923 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11253 09:59:45.608802 [0:01:06.632595032] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11254 09:59:45.638598 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (908 ms)
11255 09:59:45.743489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11256 09:59:45.743906 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11258 09:59:45.759928 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11259 09:59:46.856927 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (1257 ms)
11260 09:59:46.870211 [0:01:07.890527572] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11261 09:59:46.959539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11262 09:59:46.959876 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11264 09:59:46.975794 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11265 09:59:48.675292 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (1818 ms)
11266 09:59:48.688394 [0:01:09.708235990] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11267 09:59:48.773547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11268 09:59:48.773882 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11270 09:59:48.789990 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11271 09:59:51.404474 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (2729 ms)
11272 09:59:51.417903 [0:01:12.436762584] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11273 09:59:51.509302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11274 09:59:51.509603 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11276 09:59:51.526845 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11277 09:59:55.601408 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (4197 ms)
11278 09:59:55.614764 [0:01:16.635147058] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11279 09:59:55.700842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11280 09:59:55.701169 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11282 09:59:55.717033 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11283 10:00:02.180036 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (6579 ms)
11284 10:00:02.192821 [0:01:23.214089622] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11285 10:00:02.245902 [0:01:23.270973929] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11286 10:00:02.279612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11287 10:00:02.279968 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11289 10:00:02.300135 [0:01:23.324796691] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11290 10:00:02.302948 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11291 10:00:02.353928 [0:01:23.378960830] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11292 10:00:02.357457 Camera needs 4 requests, can't test only 1
11293 10:00:02.438229 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11294 10:00:02.519914
11295 10:00:02.609189 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (57 ms)
11296 10:00:02.706037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11297 10:00:02.706350 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11299 10:00:02.722024 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11300 10:00:02.775710 Camera needs 4 requests, can't test only 2
11301 10:00:02.864040 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11302 10:00:02.948029
11303 10:00:03.038660 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (55 ms)
11304 10:00:03.048445 [0:01:24.075167329] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11305 10:00:03.139250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11306 10:00:03.139560 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11308 10:00:03.156533 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11309 10:00:03.214675 Camera needs 4 requests, can't test only 3
11310 10:00:03.305449 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11311 10:00:03.391392
11312 10:00:03.481120 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (54 ms)
11313 10:00:03.585252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11314 10:00:03.585571 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11316 10:00:03.602217 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11317 10:00:03.660544 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (695 ms)
11318 10:00:03.762833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11319 10:00:03.763128 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11321 10:00:03.780510 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11322 10:00:03.948377 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (906 ms)
11323 10:00:03.958113 [0:01:24.982868911] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11324 10:00:04.052732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11325 10:00:04.053032 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11327 10:00:04.070004 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11328 10:00:05.206033 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (1258 ms)
11329 10:00:05.219021 [0:01:26.239815600] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11330 10:00:05.307614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11331 10:00:05.307933 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11333 10:00:05.324111 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11334 10:00:07.022938 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (1817 ms)
11335 10:00:07.036300 [0:01:28.056766460] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11336 10:00:07.126392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11337 10:00:07.126696 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11339 10:00:07.142395 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11340 10:00:09.750664 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (2727 ms)
11341 10:00:09.764061 [0:01:30.784690718] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11342 10:00:09.854599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11343 10:00:09.854892 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11345 10:00:09.871410 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11346 10:00:13.947159 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (4197 ms)
11347 10:00:13.960282 [0:01:34.982593282] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11348 10:00:14.052830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11349 10:00:14.053126 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11351 10:00:14.069510 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11352 10:00:20.524811 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (6578 ms)
11353 10:00:20.537827 [0:01:41.560232040] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11354 10:00:20.590166 [0:01:41.616924940] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11355 10:00:20.618934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11356 10:00:20.619326 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11358 10:00:20.635484 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11359 10:00:20.645391 [0:01:41.672960383] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11360 10:00:20.691162 Camera needs 4 requests, can't test only 1
11361 10:00:20.701051 [0:01:41.727876526] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11362 10:00:20.770696 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11363 10:00:20.852921
11364 10:00:20.941987 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (57 ms)
11365 10:00:21.042777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11366 10:00:21.043141 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11368 10:00:21.059826 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11369 10:00:21.113659 Camera needs 4 requests, can't test only 2
11370 10:00:21.201254 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11371 10:00:21.283033
11372 10:00:21.369218 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (57 ms)
11373 10:00:21.467278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11374 10:00:21.467662 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11376 10:00:21.483889 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11377 10:00:21.536488 Camera needs 4 requests, can't test only 3
11378 10:00:21.620703 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11379 10:00:21.704590
11380 10:00:21.796409 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (55 ms)
11381 10:00:21.892901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11382 10:00:21.893320 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11384 10:00:21.908914 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11385 10:00:22.774482 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (2081 ms)
11386 10:00:22.787394 [0:01:43.810848809] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11387 10:00:22.873218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11388 10:00:22.873554 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11390 10:00:22.889082 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11391 10:00:25.491263 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (2716 ms)
11392 10:00:25.503936 [0:01:46.527507171] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11393 10:00:25.594227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11394 10:00:25.594589 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11396 10:00:25.612594 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11397 10:00:29.252077 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (3762 ms)
11398 10:00:29.265536 [0:01:50.288499197] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11399 10:00:29.361228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11400 10:00:29.361605 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11402 10:00:29.379226 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11403 10:00:34.692324 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (5440 ms)
11404 10:00:34.705137 [0:01:55.728767343] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11405 10:00:34.795753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11406 10:00:34.796073 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11408 10:00:34.812227 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11409 10:00:42.864447 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (8172 ms)
11410 10:00:42.877757 [0:02:03.902412106] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11411 10:00:42.980391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11412 10:00:42.980693 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11414 10:00:42.997108 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11415 10:00:55.445126 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (12579 ms)
11416 10:00:55.457931 [0:02:16.480565706] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11417 10:00:55.580545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11418 10:00:55.581294 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11420 10:00:55.601465 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11421 10:01:15.166141 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (19720 ms)
11422 10:01:15.179176 [0:02:36.200796915] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11423 10:01:15.230165 [0:02:36.256549062] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11424 10:01:15.283948 [0:02:36.310622157] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11425 10:01:15.290565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11426 10:01:15.291344 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11428 10:01:15.309555 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11429 10:01:15.339845 [0:02:36.365968501] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11430 10:01:15.378972 Camera needs 4 requests, can't test only 1
11431 10:01:15.483688 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11432 10:01:15.582049
11433 10:01:15.695316 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (55 ms)
11434 10:01:15.815010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11435 10:01:15.816009 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11437 10:01:15.832147 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11438 10:01:15.903618 Camera needs 4 requests, can't test only 2
11439 10:01:16.007630 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11440 10:01:16.104995
11441 10:01:16.205650 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (54 ms)
11442 10:01:16.319645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11443 10:01:16.320470 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11445 10:01:16.336454 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11446 10:01:16.404044 Camera needs 4 requests, can't test only 3
11447 10:01:16.507550 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11448 10:01:16.592098
11449 10:01:16.687519 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (54 ms)
11450 10:01:16.785346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11451 10:01:16.785655 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11453 10:01:16.799476 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11454 10:01:17.417799 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (2084 ms)
11455 10:01:17.427880 [0:02:38.450562908] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11456 10:01:17.535543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11457 10:01:17.536326 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11459 10:01:17.550033 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11460 10:01:20.128088 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (2711 ms)
11461 10:01:20.137968 [0:02:41.160632942] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11462 10:01:20.236505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11463 10:01:20.236850 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11465 10:01:20.250019 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11466 10:01:23.888124 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (3760 ms)
11467 10:01:23.897677 [0:02:44.920356515] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11468 10:01:23.999012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11469 10:01:23.999355 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11471 10:01:24.011422 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11472 10:01:29.327800 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (5439 ms)
11473 10:01:29.337481 [0:02:50.360332224] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11474 10:01:29.434433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11475 10:01:29.434869 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11477 10:01:29.449150 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11478 10:01:37.500650 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (8173 ms)
11479 10:01:37.510665 [0:02:58.534086851] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11480 10:01:37.611591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11481 10:01:37.611932 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11483 10:01:37.624632 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11484 10:01:50.081315 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (12581 ms)
11485 10:01:50.091417 [0:03:11.115538163] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11486 10:01:50.192228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11487 10:01:50.192573 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11489 10:01:50.205591 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11490 10:02:09.803172 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (19722 ms)
11491 10:02:09.812920 [0:03:30.838775396] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11492 10:02:09.865268 [0:03:30.894835823] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11493 10:02:09.911882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11494 10:02:09.912188 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11496 10:02:09.921867 [0:03:30.949793221] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11497 10:02:09.928476 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11498 10:02:09.974805 [0:03:31.004446401] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11499 10:02:09.986849 Camera needs 4 requests, can't test only 1
11500 10:02:10.075264 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11501 10:02:10.156480
11502 10:02:10.249366 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (57 ms)
11503 10:02:10.352465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11504 10:02:10.352849 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11506 10:02:10.366543 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11507 10:02:10.423243 Camera needs 4 requests, can't test only 2
11508 10:02:10.510655 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11509 10:02:10.597493
11510 10:02:10.690459 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (56 ms)
11511 10:02:10.791445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11512 10:02:10.791760 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11514 10:02:10.805213 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11515 10:02:10.862457 Camera needs 4 requests, can't test only 3
11516 10:02:10.954896 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11517 10:02:11.039345
11518 10:02:11.128477 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (53 ms)
11519 10:02:11.233154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11520 10:02:11.233464 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11522 10:02:11.247429 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11523 10:02:12.047744 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (2079 ms)
11524 10:02:12.058010 [0:03:33.083398185] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11525 10:02:12.151229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11526 10:02:12.151529 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11528 10:02:12.164382 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11529 10:02:14.759602 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (2712 ms)
11530 10:02:14.769239 [0:03:35.794904884] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11531 10:02:14.867046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11532 10:02:14.867401 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11534 10:02:14.880852 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11535 10:02:18.519300 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (3760 ms)
11536 10:02:18.529489 [0:03:39.555485244] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11537 10:02:18.630302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11538 10:02:18.630610 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11540 10:02:18.643979 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11541 10:02:23.960427 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (5442 ms)
11542 10:02:23.970375 [0:03:44.996666915] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11543 10:02:24.063407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11544 10:02:24.063734 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11546 10:02:24.077464 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11547 10:02:32.133354 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (8173 ms)
11548 10:02:32.143444 [0:03:53.170504743] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11549 10:02:32.233897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11550 10:02:32.234236 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11552 10:02:32.246313 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11553 10:02:44.714576 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (12582 ms)
11554 10:02:44.724378 [0:04:05.752475878] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11555 10:02:44.816973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11556 10:02:44.817321 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11558 10:02:44.828380 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11559 10:03:04.436168 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (19720 ms)
11560 10:03:04.445925 [0:04:25.472239601] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11561 10:03:04.496861 [0:04:25.527771620] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11562 10:03:04.540817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11563 10:03:04.541108 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11565 10:03:04.550660 [0:04:25.584207780] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11566 10:03:04.557109 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11567 10:03:04.608987 [0:04:25.639671427] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11568 10:03:04.611900 Camera needs 4 requests, can't test only 1
11569 10:03:04.691890 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11570 10:03:04.773312
11571 10:03:04.864327 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (55 ms)
11572 10:03:04.961849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11573 10:03:04.962200 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11575 10:03:04.975662 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11576 10:03:05.031260 Camera needs 4 requests, can't test only 2
11577 10:03:05.116040 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11578 10:03:05.196467
11579 10:03:05.286111 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (57 ms)
11580 10:03:05.383558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11581 10:03:05.383907 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11583 10:03:05.397084 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11584 10:03:05.450833 Camera needs 4 requests, can't test only 3
11585 10:03:05.538232 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11586 10:03:05.616025
11587 10:03:05.709391 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (55 ms)
11588 10:03:05.807822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11589 10:03:05.808151 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11591 10:03:05.821136 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11592 10:03:06.683537 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (2080 ms)
11593 10:03:06.693516 [0:04:27.720055133] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11594 10:03:06.787916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11595 10:03:06.788243 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11597 10:03:06.801444 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11598 10:03:09.394616 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (2711 ms)
11599 10:03:09.404522 [0:04:30.430896265] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11600 10:03:09.492771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11601 10:03:09.493075 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11603 10:03:09.506457 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11604 10:03:13.155170 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (3760 ms)
11605 10:03:13.164921 [0:04:34.191245012] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11606 10:03:13.257559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11607 10:03:13.257882 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11609 10:03:13.270604 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11610 10:03:18.595631 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (5440 ms)
11611 10:03:18.605396 [0:04:39.631484252] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11612 10:03:18.696577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11613 10:03:18.696907 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11615 10:03:18.709731 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11616 10:03:26.768174 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (8172 ms)
11617 10:03:26.778560 [0:04:47.803962853] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11618 10:03:26.873555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11619 10:03:26.873888 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11621 10:03:26.887192 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11622 10:03:39.349117 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (12580 ms)
11623 10:03:39.358656 [0:05:00.384258114] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11624 10:03:39.451371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11625 10:03:39.451680 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11627 10:03:39.464724 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11628 10:03:59.070395 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (19722 ms)
11629 10:03:59.080243 [0:05:20.104948920] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11630 10:03:59.195386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11631 10:03:59.195710 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11633 10:03:59.211604 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11634 10:03:59.483954 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (416 ms)
11635 10:03:59.496756 [0:05:20.522738108] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11636 10:03:59.596086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11637 10:03:59.596445 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11639 10:03:59.611271 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11640 10:03:59.973237 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (489 ms)
11641 10:03:59.983354 [0:05:21.011794307] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11642 10:04:00.080732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11643 10:04:00.081051 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11645 10:04:00.096314 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11646 10:04:00.530808 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (557 ms)
11647 10:04:00.544028 [0:05:21.568799334] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11648 10:04:00.637932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11649 10:04:00.638242 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11651 10:04:00.655960 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11652 10:04:01.228039 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (697 ms)
11653 10:04:01.240744 [0:05:22.266718132] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11654 10:04:01.328423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11655 10:04:01.328747 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11657 10:04:01.345003 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11658 10:04:02.134342 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (907 ms)
11659 10:04:02.147762 [0:05:23.172575697] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11660 10:04:02.235328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11661 10:04:02.235652 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11663 10:04:02.252527 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11664 10:04:03.391396 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (1257 ms)
11665 10:04:03.404938 [0:05:24.430456438] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11666 10:04:03.513656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11667 10:04:03.514371 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11669 10:04:03.531673 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11670 10:04:05.209551 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (1818 ms)
11671 10:04:05.222828 [0:05:26.247826429] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11672 10:04:05.346077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11673 10:04:05.346834 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11675 10:04:05.366747 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11676 10:04:07.937262 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (2727 ms)
11677 10:04:07.950201 [0:05:28.975452582] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11678 10:04:08.049737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11679 10:04:08.050147 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11681 10:04:08.068817 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11682 10:04:12.134687 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (4197 ms)
11683 10:04:12.147684 [0:05:33.173096221] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11684 10:04:12.257667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11685 10:04:12.258484 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11687 10:04:12.274376 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11688 10:04:18.712950 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (6578 ms)
11689 10:04:18.726254 [0:05:39.751497732] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11690 10:04:18.840283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11691 10:04:18.841087 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11693 10:04:18.860022 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11694 10:04:19.133287 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (417 ms)
11695 10:04:19.143230 [0:05:40.168314069] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11696 10:04:19.250862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11697 10:04:19.251174 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11699 10:04:19.265999 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11700 10:04:19.620952 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (487 ms)
11701 10:04:19.630683 [0:05:40.655926879] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11702 10:04:19.738714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11703 10:04:19.739043 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11705 10:04:19.752750 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11706 10:04:20.178284 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (557 ms)
11707 10:04:20.187743 [0:05:41.213219573] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11708 10:04:20.293875 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11710 10:04:20.296729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11711 10:04:20.312355 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11712 10:04:20.875814 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (698 ms)
11713 10:04:20.885285 [0:05:41.910885594] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11714 10:04:21.006238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11715 10:04:21.006537 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11717 10:04:21.022479 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11718 10:04:21.785247 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (910 ms)
11719 10:04:21.794973 [0:05:42.820288929] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11720 10:04:21.886986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11721 10:04:21.887277 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11723 10:04:21.900673 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11724 10:04:23.042181 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (1257 ms)
11725 10:04:23.052118 [0:05:44.076908577] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11726 10:04:23.163170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11727 10:04:23.164007 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11729 10:04:23.179852 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11730 10:04:24.858714 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (1816 ms)
11731 10:04:24.868794 [0:05:45.894689785] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11732 10:04:24.962457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11733 10:04:24.962788 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11735 10:04:24.975728 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11736 10:04:27.589138 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (2730 ms)
11737 10:04:27.599070 [0:05:48.624198916] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11738 10:04:27.704553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11739 10:04:27.705305 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11741 10:04:27.721175 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11742 10:04:31.786091 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (4197 ms)
11743 10:04:31.795804 [0:05:52.820840533] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11744 10:04:31.911078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11745 10:04:31.911815 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11747 10:04:31.926937 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11748 10:04:38.362996 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (6577 ms)
11749 10:04:38.372568 [0:05:59.398859107] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11750 10:04:38.468375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11751 10:04:38.468755 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11753 10:04:38.482577 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11754 10:04:38.780853 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (417 ms)
11755 10:04:38.790473 [0:05:59.816104849] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11756 10:04:38.902195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11757 10:04:38.902928 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11759 10:04:38.917886 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11760 10:04:39.267278 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (488 ms)
11761 10:04:39.277562 [0:06:00.303653714] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11762 10:04:39.368243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11763 10:04:39.368599 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11765 10:04:39.381779 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11766 10:04:39.824972 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (557 ms)
11767 10:04:39.834713 [0:06:00.860490797] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11768 10:04:39.930534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11769 10:04:39.930839 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11771 10:04:39.944866 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11772 10:04:40.522047 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (697 ms)
11773 10:04:40.531683 [0:06:01.558457450] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11774 10:04:40.621572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11775 10:04:40.621909 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11777 10:04:40.634770 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11778 10:04:41.431784 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (910 ms)
11779 10:04:41.441778 [0:06:02.468115743] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11780 10:04:41.530077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11781 10:04:41.530417 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11783 10:04:41.541163 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11784 10:04:42.688910 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (1257 ms)
11785 10:04:42.699017 [0:06:03.725201603] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11786 10:04:42.788684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11787 10:04:42.789041 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11789 10:04:42.801498 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11790 10:04:44.506932 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (1818 ms)
11791 10:04:44.516545 [0:06:05.543400354] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11792 10:04:44.609343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11793 10:04:44.609753 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11795 10:04:44.623036 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11796 10:04:47.234751 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (2728 ms)
11797 10:04:47.244773 [0:06:08.271329891] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11798 10:04:47.333067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11799 10:04:47.333382 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11801 10:04:47.347447 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11802 10:04:51.432749 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (4198 ms)
11803 10:04:51.442321 [0:06:12.468764386] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11804 10:04:51.540054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11805 10:04:51.540423 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11807 10:04:51.555456 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11808 10:04:58.009606 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (6578 ms)
11809 10:04:58.019849 [0:06:19.046784789] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11810 10:04:58.115894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11811 10:04:58.116238 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11813 10:04:58.130548 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11814 10:04:58.426943 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (417 ms)
11815 10:04:58.437231 [0:06:19.463614209] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11816 10:04:58.525973 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11818 10:04:58.529232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11819 10:04:58.541988 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11820 10:04:58.914714 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (488 ms)
11821 10:04:58.924565 [0:06:19.951660213] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11822 10:04:59.017845 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11824 10:04:59.020909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11825 10:04:59.036327 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11826 10:04:59.471652 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (557 ms)
11827 10:04:59.481458 [0:06:20.508318692] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11828 10:04:59.574198 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11830 10:04:59.576679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11831 10:04:59.588868 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11832 10:05:00.168882 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (697 ms)
11833 10:05:00.178607 [0:06:21.204824122] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11834 10:05:00.271695 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11836 10:05:00.274941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11837 10:05:00.288090 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11838 10:05:01.075945 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (907 ms)
11839 10:05:01.085633 [0:06:22.112216086] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11840 10:05:01.178578 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11842 10:05:01.181986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11843 10:05:01.195543 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11844 10:05:02.333166 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (1257 ms)
11845 10:05:02.342918 [0:06:23.369651309] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11846 10:05:02.453831 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11848 10:05:02.457012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11849 10:05:02.472132 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11850 10:05:04.150708 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (1817 ms)
11851 10:05:04.160652 [0:06:25.187380602] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11852 10:05:04.271596 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11854 10:05:04.274314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11855 10:05:04.288113 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11856 10:05:06.878515 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (2728 ms)
11857 10:05:06.888166 [0:06:27.915306052] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11858 10:05:07.013072 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11860 10:05:07.015734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11861 10:05:07.032496 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11862 10:05:11.075444 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (4198 ms)
11863 10:05:11.085664 [0:06:32.112534934] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11864 10:05:11.171450 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11866 10:05:11.174264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11867 10:05:11.188150 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11868 10:05:17.653175 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (6578 ms)
11869 10:05:17.743818 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11871 10:05:17.747086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11872 10:05:17.760034 [----------] 120 tests from CaptureTests/SingleStream (370011 ms total)
11873 10:05:17.832937
11874 10:05:17.914360 [----------] Global test environment tear-down
11875 10:05:17.995804 [==========] 120 tests from 1 test suite ran. (370011 ms total)
11876 10:05:18.082010 <LAVA_SIGNAL_TESTSET STOP>
11877 10:05:18.082339 Received signal: <TESTSET> STOP
11878 10:05:18.082419 Closing test_set CaptureTests/SingleStream
11879 10:05:18.095871 + set +x
11880 10:05:18.098824 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 12073290_1.6.2.3.1>
11881 10:05:18.099076 Received signal: <ENDRUN> 0_lc-compliance 12073290_1.6.2.3.1
11882 10:05:18.099157 Ending use of test pattern.
11883 10:05:18.099246 Ending test lava.0_lc-compliance (12073290_1.6.2.3.1), duration 371.75
11885 10:05:18.102368 <LAVA_TEST_RUNNER EXIT>
11886 10:05:18.102646 ok: lava_test_shell seems to have completed
11887 10:05:18.104933 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
11888 10:05:18.105112 end: 3.1 lava-test-shell (duration 00:06:12) [common]
11889 10:05:18.105197 end: 3 lava-test-retry (duration 00:06:12) [common]
11890 10:05:18.105305 start: 4 finalize (timeout 00:10:00) [common]
11891 10:05:18.105413 start: 4.1 power-off (timeout 00:00:30) [common]
11892 10:05:18.105559 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11893 10:05:18.177840 >> Command sent successfully.
11894 10:05:18.180446 Returned 0 in 0 seconds
11895 10:05:18.280857 end: 4.1 power-off (duration 00:00:00) [common]
11897 10:05:18.281313 start: 4.2 read-feedback (timeout 00:10:00) [common]
11898 10:05:18.281672 Listened to connection for namespace 'common' for up to 1s
11899 10:05:19.282533 Finalising connection for namespace 'common'
11900 10:05:19.282724 Disconnecting from shell: Finalise
11901 10:05:19.282813 / #
11902 10:05:19.383215 end: 4.2 read-feedback (duration 00:00:01) [common]
11903 10:05:19.383401 end: 4 finalize (duration 00:00:01) [common]
11904 10:05:19.383542 Cleaning after the job
11905 10:05:19.383661 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073290/tftp-deploy-zjenkfgv/ramdisk
11906 10:05:19.386600 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073290/tftp-deploy-zjenkfgv/kernel
11907 10:05:19.400025 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073290/tftp-deploy-zjenkfgv/dtb
11908 10:05:19.400257 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073290/tftp-deploy-zjenkfgv/nfsrootfs
11909 10:05:19.461518 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073290/tftp-deploy-zjenkfgv/modules
11910 10:05:19.469200 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12073290
11911 10:05:19.796957 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12073290
11912 10:05:19.797132 Job finished correctly