Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 40
- Kernel Warnings: 27
- Boot result: PASS
- Errors: 1
1 09:56:29.277617 lava-dispatcher, installed at version: 2023.10
2 09:56:29.277812 start: 0 validate
3 09:56:29.277940 Start time: 2023-11-24 09:56:29.277933+00:00 (UTC)
4 09:56:29.278056 Using caching service: 'http://localhost/cache/?uri=%s'
5 09:56:29.278183 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 09:56:29.537491 Using caching service: 'http://localhost/cache/?uri=%s'
7 09:56:29.537661 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 09:56:29.802940 Using caching service: 'http://localhost/cache/?uri=%s'
9 09:56:29.803192 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 09:57:24.660782 Using caching service: 'http://localhost/cache/?uri=%s'
11 09:57:24.661561 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.62-cip9-12-g3a5321f469b07%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 09:57:25.195030 validate duration: 55.92
14 09:57:25.196299 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 09:57:25.196811 start: 1.1 download-retry (timeout 00:10:00) [common]
16 09:57:25.197259 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 09:57:25.197907 Not decompressing ramdisk as can be used compressed.
18 09:57:25.198392 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 09:57:25.198819 saving as /var/lib/lava/dispatcher/tmp/12073291/tftp-deploy-s0zgjjin/ramdisk/rootfs.cpio.gz
20 09:57:25.199278 total size: 26246609 (25 MB)
21 09:57:39.409645 progress 0 % (0 MB)
22 09:57:39.444113 progress 5 % (1 MB)
23 09:57:39.458510 progress 10 % (2 MB)
24 09:57:39.468394 progress 15 % (3 MB)
25 09:57:39.476427 progress 20 % (5 MB)
26 09:57:39.483541 progress 25 % (6 MB)
27 09:57:39.490423 progress 30 % (7 MB)
28 09:57:39.497225 progress 35 % (8 MB)
29 09:57:39.504092 progress 40 % (10 MB)
30 09:57:39.511022 progress 45 % (11 MB)
31 09:57:39.517896 progress 50 % (12 MB)
32 09:57:39.524736 progress 55 % (13 MB)
33 09:57:39.531649 progress 60 % (15 MB)
34 09:57:39.538542 progress 65 % (16 MB)
35 09:57:39.545481 progress 70 % (17 MB)
36 09:57:39.552321 progress 75 % (18 MB)
37 09:57:39.559175 progress 80 % (20 MB)
38 09:57:39.566038 progress 85 % (21 MB)
39 09:57:39.572726 progress 90 % (22 MB)
40 09:57:39.579491 progress 95 % (23 MB)
41 09:57:39.586318 progress 100 % (25 MB)
42 09:57:39.586581 25 MB downloaded in 14.39 s (1.74 MB/s)
43 09:57:39.586734 end: 1.1.1 http-download (duration 00:00:14) [common]
45 09:57:39.586972 end: 1.1 download-retry (duration 00:00:14) [common]
46 09:57:39.587056 start: 1.2 download-retry (timeout 00:09:46) [common]
47 09:57:39.587138 start: 1.2.1 http-download (timeout 00:09:46) [common]
48 09:57:39.587264 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 09:57:39.587335 saving as /var/lib/lava/dispatcher/tmp/12073291/tftp-deploy-s0zgjjin/kernel/Image
50 09:57:39.587394 total size: 49107456 (46 MB)
51 09:57:39.587453 No compression specified
52 09:57:39.854522 progress 0 % (0 MB)
53 09:57:39.867342 progress 5 % (2 MB)
54 09:57:39.880102 progress 10 % (4 MB)
55 09:57:39.892972 progress 15 % (7 MB)
56 09:57:39.905848 progress 20 % (9 MB)
57 09:57:39.918787 progress 25 % (11 MB)
58 09:57:39.931597 progress 30 % (14 MB)
59 09:57:39.944379 progress 35 % (16 MB)
60 09:57:39.957205 progress 40 % (18 MB)
61 09:57:39.969997 progress 45 % (21 MB)
62 09:57:39.983031 progress 50 % (23 MB)
63 09:57:39.995864 progress 55 % (25 MB)
64 09:57:40.008868 progress 60 % (28 MB)
65 09:57:40.021816 progress 65 % (30 MB)
66 09:57:40.034572 progress 70 % (32 MB)
67 09:57:40.047149 progress 75 % (35 MB)
68 09:57:40.060061 progress 80 % (37 MB)
69 09:57:40.072811 progress 85 % (39 MB)
70 09:57:40.085983 progress 90 % (42 MB)
71 09:57:40.098606 progress 95 % (44 MB)
72 09:57:40.111884 progress 100 % (46 MB)
73 09:57:40.112133 46 MB downloaded in 0.52 s (89.25 MB/s)
74 09:57:40.112288 end: 1.2.1 http-download (duration 00:00:01) [common]
76 09:57:40.112514 end: 1.2 download-retry (duration 00:00:01) [common]
77 09:57:40.112604 start: 1.3 download-retry (timeout 00:09:45) [common]
78 09:57:40.112688 start: 1.3.1 http-download (timeout 00:09:45) [common]
79 09:57:40.112830 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 09:57:40.112899 saving as /var/lib/lava/dispatcher/tmp/12073291/tftp-deploy-s0zgjjin/dtb/mt8192-asurada-spherion-r0.dtb
81 09:57:40.112960 total size: 47278 (0 MB)
82 09:57:40.113021 No compression specified
83 09:57:40.380813 progress 69 % (0 MB)
84 09:57:40.381149 progress 100 % (0 MB)
85 09:57:40.381314 0 MB downloaded in 0.27 s (0.17 MB/s)
86 09:57:40.381507 end: 1.3.1 http-download (duration 00:00:00) [common]
88 09:57:40.381750 end: 1.3 download-retry (duration 00:00:00) [common]
89 09:57:40.381836 start: 1.4 download-retry (timeout 00:09:45) [common]
90 09:57:40.381917 start: 1.4.1 http-download (timeout 00:09:45) [common]
91 09:57:40.382059 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.62-cip9-12-g3a5321f469b07/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 09:57:40.382125 saving as /var/lib/lava/dispatcher/tmp/12073291/tftp-deploy-s0zgjjin/modules/modules.tar
93 09:57:40.382185 total size: 8622040 (8 MB)
94 09:57:40.382245 Using unxz to decompress xz
95 09:57:40.386473 progress 0 % (0 MB)
96 09:57:40.407448 progress 5 % (0 MB)
97 09:57:40.430994 progress 10 % (0 MB)
98 09:57:40.454582 progress 15 % (1 MB)
99 09:57:40.478053 progress 20 % (1 MB)
100 09:57:40.502383 progress 25 % (2 MB)
101 09:57:40.528324 progress 30 % (2 MB)
102 09:57:40.554526 progress 35 % (2 MB)
103 09:57:40.577844 progress 40 % (3 MB)
104 09:57:40.602014 progress 45 % (3 MB)
105 09:57:40.627555 progress 50 % (4 MB)
106 09:57:40.651775 progress 55 % (4 MB)
107 09:57:40.676711 progress 60 % (4 MB)
108 09:57:40.704280 progress 65 % (5 MB)
109 09:57:40.729890 progress 70 % (5 MB)
110 09:57:40.753738 progress 75 % (6 MB)
111 09:57:40.782446 progress 80 % (6 MB)
112 09:57:40.810132 progress 85 % (7 MB)
113 09:57:40.836854 progress 90 % (7 MB)
114 09:57:40.867633 progress 95 % (7 MB)
115 09:57:40.897972 progress 100 % (8 MB)
116 09:57:40.903037 8 MB downloaded in 0.52 s (15.79 MB/s)
117 09:57:40.903306 end: 1.4.1 http-download (duration 00:00:01) [common]
119 09:57:40.903572 end: 1.4 download-retry (duration 00:00:01) [common]
120 09:57:40.903667 start: 1.5 prepare-tftp-overlay (timeout 00:09:44) [common]
121 09:57:40.903765 start: 1.5.1 extract-nfsrootfs (timeout 00:09:44) [common]
122 09:57:40.903847 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 09:57:40.903929 start: 1.5.2 lava-overlay (timeout 00:09:44) [common]
124 09:57:40.904168 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12073291/lava-overlay-26tbiu3d
125 09:57:40.904306 makedir: /var/lib/lava/dispatcher/tmp/12073291/lava-overlay-26tbiu3d/lava-12073291/bin
126 09:57:40.904414 makedir: /var/lib/lava/dispatcher/tmp/12073291/lava-overlay-26tbiu3d/lava-12073291/tests
127 09:57:40.904514 makedir: /var/lib/lava/dispatcher/tmp/12073291/lava-overlay-26tbiu3d/lava-12073291/results
128 09:57:40.904635 Creating /var/lib/lava/dispatcher/tmp/12073291/lava-overlay-26tbiu3d/lava-12073291/bin/lava-add-keys
129 09:57:40.904789 Creating /var/lib/lava/dispatcher/tmp/12073291/lava-overlay-26tbiu3d/lava-12073291/bin/lava-add-sources
130 09:57:40.904926 Creating /var/lib/lava/dispatcher/tmp/12073291/lava-overlay-26tbiu3d/lava-12073291/bin/lava-background-process-start
131 09:57:40.905062 Creating /var/lib/lava/dispatcher/tmp/12073291/lava-overlay-26tbiu3d/lava-12073291/bin/lava-background-process-stop
132 09:57:40.905196 Creating /var/lib/lava/dispatcher/tmp/12073291/lava-overlay-26tbiu3d/lava-12073291/bin/lava-common-functions
133 09:57:40.905326 Creating /var/lib/lava/dispatcher/tmp/12073291/lava-overlay-26tbiu3d/lava-12073291/bin/lava-echo-ipv4
134 09:57:40.905467 Creating /var/lib/lava/dispatcher/tmp/12073291/lava-overlay-26tbiu3d/lava-12073291/bin/lava-install-packages
135 09:57:40.905597 Creating /var/lib/lava/dispatcher/tmp/12073291/lava-overlay-26tbiu3d/lava-12073291/bin/lava-installed-packages
136 09:57:40.905733 Creating /var/lib/lava/dispatcher/tmp/12073291/lava-overlay-26tbiu3d/lava-12073291/bin/lava-os-build
137 09:57:40.905862 Creating /var/lib/lava/dispatcher/tmp/12073291/lava-overlay-26tbiu3d/lava-12073291/bin/lava-probe-channel
138 09:57:40.905989 Creating /var/lib/lava/dispatcher/tmp/12073291/lava-overlay-26tbiu3d/lava-12073291/bin/lava-probe-ip
139 09:57:40.906116 Creating /var/lib/lava/dispatcher/tmp/12073291/lava-overlay-26tbiu3d/lava-12073291/bin/lava-target-ip
140 09:57:40.906242 Creating /var/lib/lava/dispatcher/tmp/12073291/lava-overlay-26tbiu3d/lava-12073291/bin/lava-target-mac
141 09:57:40.906373 Creating /var/lib/lava/dispatcher/tmp/12073291/lava-overlay-26tbiu3d/lava-12073291/bin/lava-target-storage
142 09:57:40.906507 Creating /var/lib/lava/dispatcher/tmp/12073291/lava-overlay-26tbiu3d/lava-12073291/bin/lava-test-case
143 09:57:40.906636 Creating /var/lib/lava/dispatcher/tmp/12073291/lava-overlay-26tbiu3d/lava-12073291/bin/lava-test-event
144 09:57:40.906773 Creating /var/lib/lava/dispatcher/tmp/12073291/lava-overlay-26tbiu3d/lava-12073291/bin/lava-test-feedback
145 09:57:40.906929 Creating /var/lib/lava/dispatcher/tmp/12073291/lava-overlay-26tbiu3d/lava-12073291/bin/lava-test-raise
146 09:57:40.907113 Creating /var/lib/lava/dispatcher/tmp/12073291/lava-overlay-26tbiu3d/lava-12073291/bin/lava-test-reference
147 09:57:40.907254 Creating /var/lib/lava/dispatcher/tmp/12073291/lava-overlay-26tbiu3d/lava-12073291/bin/lava-test-runner
148 09:57:40.907408 Creating /var/lib/lava/dispatcher/tmp/12073291/lava-overlay-26tbiu3d/lava-12073291/bin/lava-test-set
149 09:57:40.907541 Creating /var/lib/lava/dispatcher/tmp/12073291/lava-overlay-26tbiu3d/lava-12073291/bin/lava-test-shell
150 09:57:40.907677 Updating /var/lib/lava/dispatcher/tmp/12073291/lava-overlay-26tbiu3d/lava-12073291/bin/lava-install-packages (oe)
151 09:57:40.907837 Updating /var/lib/lava/dispatcher/tmp/12073291/lava-overlay-26tbiu3d/lava-12073291/bin/lava-installed-packages (oe)
152 09:57:40.907969 Creating /var/lib/lava/dispatcher/tmp/12073291/lava-overlay-26tbiu3d/lava-12073291/environment
153 09:57:40.908083 LAVA metadata
154 09:57:40.908159 - LAVA_JOB_ID=12073291
155 09:57:40.908235 - LAVA_DISPATCHER_IP=192.168.201.1
156 09:57:40.908352 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:44) [common]
157 09:57:40.908422 skipped lava-vland-overlay
158 09:57:40.908497 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 09:57:40.908577 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:44) [common]
160 09:57:40.908646 skipped lava-multinode-overlay
161 09:57:40.908718 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 09:57:40.908803 start: 1.5.2.3 test-definition (timeout 00:09:44) [common]
163 09:57:40.908890 Loading test definitions
164 09:57:40.909044 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:44) [common]
165 09:57:40.909156 Using /lava-12073291 at stage 0
166 09:57:40.909518 uuid=12073291_1.5.2.3.1 testdef=None
167 09:57:40.909611 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 09:57:40.909699 start: 1.5.2.3.2 test-overlay (timeout 00:09:44) [common]
169 09:57:40.910257 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 09:57:40.910565 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:44) [common]
172 09:57:40.911383 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 09:57:40.911734 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:44) [common]
175 09:57:40.912370 runner path: /var/lib/lava/dispatcher/tmp/12073291/lava-overlay-26tbiu3d/lava-12073291/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 12073291_1.5.2.3.1
176 09:57:40.912535 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 09:57:40.912755 Creating lava-test-runner.conf files
179 09:57:40.912819 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12073291/lava-overlay-26tbiu3d/lava-12073291/0 for stage 0
180 09:57:40.912915 - 0_v4l2-compliance-mtk-vcodec-enc
181 09:57:40.913054 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 09:57:40.913175 start: 1.5.2.4 compress-overlay (timeout 00:09:44) [common]
183 09:57:40.920567 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 09:57:40.920701 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:44) [common]
185 09:57:40.920828 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 09:57:40.920946 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 09:57:40.921050 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:44) [common]
188 09:57:41.671119 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 09:57:41.671510 start: 1.5.4 extract-modules (timeout 00:09:44) [common]
190 09:57:41.671623 extracting modules file /var/lib/lava/dispatcher/tmp/12073291/tftp-deploy-s0zgjjin/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12073291/extract-overlay-ramdisk-fv189jnt/ramdisk
191 09:57:41.909694 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 09:57:41.909862 start: 1.5.5 apply-overlay-tftp (timeout 00:09:43) [common]
193 09:57:41.909958 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12073291/compress-overlay-bdzwbg_c/overlay-1.5.2.4.tar.gz to ramdisk
194 09:57:41.910029 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12073291/compress-overlay-bdzwbg_c/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12073291/extract-overlay-ramdisk-fv189jnt/ramdisk
195 09:57:41.917266 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 09:57:41.917439 start: 1.5.6 configure-preseed-file (timeout 00:09:43) [common]
197 09:57:41.917556 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 09:57:41.917644 start: 1.5.7 compress-ramdisk (timeout 00:09:43) [common]
199 09:57:41.917727 Building ramdisk /var/lib/lava/dispatcher/tmp/12073291/extract-overlay-ramdisk-fv189jnt/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12073291/extract-overlay-ramdisk-fv189jnt/ramdisk
200 09:57:42.562693 >> 228427 blocks
201 09:57:46.577517 rename /var/lib/lava/dispatcher/tmp/12073291/extract-overlay-ramdisk-fv189jnt/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12073291/tftp-deploy-s0zgjjin/ramdisk/ramdisk.cpio.gz
202 09:57:46.578016 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 09:57:46.578140 start: 1.5.8 prepare-kernel (timeout 00:09:39) [common]
204 09:57:46.578241 start: 1.5.8.1 prepare-fit (timeout 00:09:39) [common]
205 09:57:46.578348 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12073291/tftp-deploy-s0zgjjin/kernel/Image'
206 09:58:00.892124 Returned 0 in 14 seconds
207 09:58:00.992744 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12073291/tftp-deploy-s0zgjjin/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12073291/tftp-deploy-s0zgjjin/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12073291/tftp-deploy-s0zgjjin/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12073291/tftp-deploy-s0zgjjin/kernel/image.itb
208 09:58:01.617535 output: FIT description: Kernel Image image with one or more FDT blobs
209 09:58:01.617907 output: Created: Fri Nov 24 09:58:01 2023
210 09:58:01.617986 output: Image 0 (kernel-1)
211 09:58:01.618056 output: Description:
212 09:58:01.618125 output: Created: Fri Nov 24 09:58:01 2023
213 09:58:01.618190 output: Type: Kernel Image
214 09:58:01.618252 output: Compression: lzma compressed
215 09:58:01.618314 output: Data Size: 11047542 Bytes = 10788.62 KiB = 10.54 MiB
216 09:58:01.618378 output: Architecture: AArch64
217 09:58:01.618438 output: OS: Linux
218 09:58:01.618496 output: Load Address: 0x00000000
219 09:58:01.618552 output: Entry Point: 0x00000000
220 09:58:01.618612 output: Hash algo: crc32
221 09:58:01.618666 output: Hash value: 2edffaa3
222 09:58:01.618721 output: Image 1 (fdt-1)
223 09:58:01.618782 output: Description: mt8192-asurada-spherion-r0
224 09:58:01.618838 output: Created: Fri Nov 24 09:58:01 2023
225 09:58:01.618892 output: Type: Flat Device Tree
226 09:58:01.618945 output: Compression: uncompressed
227 09:58:01.619008 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 09:58:01.619098 output: Architecture: AArch64
229 09:58:01.619182 output: Hash algo: crc32
230 09:58:01.619240 output: Hash value: cc4352de
231 09:58:01.619319 output: Image 2 (ramdisk-1)
232 09:58:01.619412 output: Description: unavailable
233 09:58:01.619497 output: Created: Fri Nov 24 09:58:01 2023
234 09:58:01.619581 output: Type: RAMDisk Image
235 09:58:01.619669 output: Compression: Unknown Compression
236 09:58:01.619753 output: Data Size: 39370829 Bytes = 38448.08 KiB = 37.55 MiB
237 09:58:01.619842 output: Architecture: AArch64
238 09:58:01.619931 output: OS: Linux
239 09:58:01.619993 output: Load Address: unavailable
240 09:58:01.620065 output: Entry Point: unavailable
241 09:58:01.620127 output: Hash algo: crc32
242 09:58:01.620182 output: Hash value: 1037f93d
243 09:58:01.620236 output: Default Configuration: 'conf-1'
244 09:58:01.620290 output: Configuration 0 (conf-1)
245 09:58:01.620371 output: Description: mt8192-asurada-spherion-r0
246 09:58:01.620455 output: Kernel: kernel-1
247 09:58:01.620537 output: Init Ramdisk: ramdisk-1
248 09:58:01.620623 output: FDT: fdt-1
249 09:58:01.620704 output: Loadables: kernel-1
250 09:58:01.620761 output:
251 09:58:01.620959 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 09:58:01.621062 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 09:58:01.621171 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 09:58:01.621265 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:24) [common]
255 09:58:01.621343 No LXC device requested
256 09:58:01.621433 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 09:58:01.621520 start: 1.7 deploy-device-env (timeout 00:09:24) [common]
258 09:58:01.621599 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 09:58:01.621675 Checking files for TFTP limit of 4294967296 bytes.
260 09:58:01.622269 end: 1 tftp-deploy (duration 00:00:36) [common]
261 09:58:01.622378 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 09:58:01.622472 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 09:58:01.622602 substitutions:
264 09:58:01.622705 - {DTB}: 12073291/tftp-deploy-s0zgjjin/dtb/mt8192-asurada-spherion-r0.dtb
265 09:58:01.622774 - {INITRD}: 12073291/tftp-deploy-s0zgjjin/ramdisk/ramdisk.cpio.gz
266 09:58:01.622835 - {KERNEL}: 12073291/tftp-deploy-s0zgjjin/kernel/Image
267 09:58:01.622894 - {LAVA_MAC}: None
268 09:58:01.622951 - {PRESEED_CONFIG}: None
269 09:58:01.623006 - {PRESEED_LOCAL}: None
270 09:58:01.623061 - {RAMDISK}: 12073291/tftp-deploy-s0zgjjin/ramdisk/ramdisk.cpio.gz
271 09:58:01.623115 - {ROOT_PART}: None
272 09:58:01.623201 - {ROOT}: None
273 09:58:01.623296 - {SERVER_IP}: 192.168.201.1
274 09:58:01.623384 - {TEE}: None
275 09:58:01.623443 Parsed boot commands:
276 09:58:01.623500 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 09:58:01.623688 Parsed boot commands: tftpboot 192.168.201.1 12073291/tftp-deploy-s0zgjjin/kernel/image.itb 12073291/tftp-deploy-s0zgjjin/kernel/cmdline
278 09:58:01.623779 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 09:58:01.623870 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 09:58:01.623989 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 09:58:01.624109 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 09:58:01.624215 Not connected, no need to disconnect.
283 09:58:01.624321 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 09:58:01.624433 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 09:58:01.624517 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
286 09:58:01.628839 Setting prompt string to ['lava-test: # ']
287 09:58:01.629233 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 09:58:01.629347 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 09:58:01.629507 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 09:58:01.629610 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 09:58:01.629825 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
292 09:58:06.762844 >> Command sent successfully.
293 09:58:06.765863 Returned 0 in 5 seconds
294 09:58:06.866226 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 09:58:06.866585 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 09:58:06.866699 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 09:58:06.866795 Setting prompt string to 'Starting depthcharge on Spherion...'
299 09:58:06.866860 Changing prompt to 'Starting depthcharge on Spherion...'
300 09:58:06.866928 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 09:58:06.867211 [Enter `^Ec?' for help]
302 09:58:07.038346
303 09:58:07.038505
304 09:58:07.038607 F0: 102B 0000
305 09:58:07.038705
306 09:58:07.038797 F3: 1001 0000 [0200]
307 09:58:07.038864
308 09:58:07.042057 F3: 1001 0000
309 09:58:07.042170
310 09:58:07.042267 F7: 102D 0000
311 09:58:07.042358
312 09:58:07.042460 F1: 0000 0000
313 09:58:07.045047
314 09:58:07.045125 V0: 0000 0000 [0001]
315 09:58:07.045188
316 09:58:07.045248 00: 0007 8000
317 09:58:07.048286
318 09:58:07.048377 01: 0000 0000
319 09:58:07.048483
320 09:58:07.048579 BP: 0C00 0209 [0000]
321 09:58:07.048677
322 09:58:07.052184 G0: 1182 0000
323 09:58:07.052288
324 09:58:07.052385 EC: 0000 0021 [4000]
325 09:58:07.052473
326 09:58:07.055656 S7: 0000 0000 [0000]
327 09:58:07.055733
328 09:58:07.055805 CC: 0000 0000 [0001]
329 09:58:07.055866
330 09:58:07.059491 T0: 0000 0040 [010F]
331 09:58:07.059573
332 09:58:07.059637 Jump to BL
333 09:58:07.059697
334 09:58:07.084897
335 09:58:07.085038
336 09:58:07.085112
337 09:58:07.091954 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 09:58:07.095552 ARM64: Exception handlers installed.
339 09:58:07.099470 ARM64: Testing exception
340 09:58:07.102935 ARM64: Done test exception
341 09:58:07.109719 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 09:58:07.120807 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 09:58:07.127730 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 09:58:07.134821 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 09:58:07.142088 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 09:58:07.152593 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 09:58:07.162445 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 09:58:07.169166 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 09:58:07.187745 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 09:58:07.190860 WDT: Last reset was cold boot
351 09:58:07.194342 SPI1(PAD0) initialized at 2873684 Hz
352 09:58:07.197693 SPI5(PAD0) initialized at 992727 Hz
353 09:58:07.200768 VBOOT: Loading verstage.
354 09:58:07.207398 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 09:58:07.210902 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 09:58:07.214408 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 09:58:07.217620 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 09:58:07.225404 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 09:58:07.231534 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 09:58:07.242867 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 09:58:07.242959
362 09:58:07.243025
363 09:58:07.252523 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 09:58:07.255998 ARM64: Exception handlers installed.
365 09:58:07.258847 ARM64: Testing exception
366 09:58:07.258932 ARM64: Done test exception
367 09:58:07.265493 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 09:58:07.269659 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 09:58:07.283564 Probing TPM: . done!
370 09:58:07.283685 TPM ready after 0 ms
371 09:58:07.290168 Connected to device vid:did:rid of 1ae0:0028:00
372 09:58:07.296988 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 09:58:07.338956 Initialized TPM device CR50 revision 0
374 09:58:07.350651 tlcl_send_startup: Startup return code is 0
375 09:58:07.350750 TPM: setup succeeded
376 09:58:07.362234 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 09:58:07.370566 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 09:58:07.381256 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 09:58:07.389479 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 09:58:07.392885 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 09:58:07.396051 in-header: 03 07 00 00 08 00 00 00
382 09:58:07.399591 in-data: aa e4 47 04 13 02 00 00
383 09:58:07.402683 Chrome EC: UHEPI supported
384 09:58:07.409301 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 09:58:07.412845 in-header: 03 ad 00 00 08 00 00 00
386 09:58:07.415937 in-data: 00 20 20 08 00 00 00 00
387 09:58:07.416014 Phase 1
388 09:58:07.422725 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 09:58:07.425755 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 09:58:07.432829 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 09:58:07.436039 Recovery requested (1009000e)
392 09:58:07.440507 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 09:58:07.448513 tlcl_extend: response is 0
394 09:58:07.456984 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 09:58:07.462456 tlcl_extend: response is 0
396 09:58:07.468551 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 09:58:07.489031 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 09:58:07.495888 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 09:58:07.495984
400 09:58:07.496070
401 09:58:07.506607 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 09:58:07.510055 ARM64: Exception handlers installed.
403 09:58:07.510170 ARM64: Testing exception
404 09:58:07.512968 ARM64: Done test exception
405 09:58:07.535130 pmic_efuse_setting: Set efuses in 11 msecs
406 09:58:07.538160 pmwrap_interface_init: Select PMIF_VLD_RDY
407 09:58:07.545740 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 09:58:07.549257 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 09:58:07.552399 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 09:58:07.558502 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 09:58:07.562198 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 09:58:07.568920 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 09:58:07.572565 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 09:58:07.578773 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 09:58:07.582559 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 09:58:07.585512 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 09:58:07.592340 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 09:58:07.595870 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 09:58:07.602387 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 09:58:07.605345 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 09:58:07.611727 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 09:58:07.618791 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 09:58:07.625277 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 09:58:07.628441 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 09:58:07.634770 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 09:58:07.641719 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 09:58:07.644913 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 09:58:07.652241 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 09:58:07.659432 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 09:58:07.662894 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 09:58:07.666913 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 09:58:07.673388 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 09:58:07.680047 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 09:58:07.683352 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 09:58:07.690882 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 09:58:07.693748 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 09:58:07.697419 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 09:58:07.704585 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 09:58:07.707716 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 09:58:07.714031 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 09:58:07.717377 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 09:58:07.723958 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 09:58:07.727191 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 09:58:07.734103 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 09:58:07.737819 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 09:58:07.741637 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 09:58:07.748358 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 09:58:07.751907 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 09:58:07.755133 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 09:58:07.758758 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 09:58:07.765803 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 09:58:07.768590 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 09:58:07.772205 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 09:58:07.778625 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 09:58:07.781944 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 09:58:07.785624 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 09:58:07.788757 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 09:58:07.798787 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 09:58:07.805051 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 09:58:07.811896 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 09:58:07.818813 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 09:58:07.828586 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 09:58:07.832010 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 09:58:07.835152 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 09:58:07.841745 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 09:58:07.848224 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x0
467 09:58:07.851767 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 09:58:07.859134 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
469 09:58:07.862077 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 09:58:07.871674 [RTC]rtc_get_frequency_meter,154: input=15, output=835
471 09:58:07.881380 [RTC]rtc_get_frequency_meter,154: input=7, output=709
472 09:58:07.890486 [RTC]rtc_get_frequency_meter,154: input=11, output=771
473 09:58:07.900441 [RTC]rtc_get_frequency_meter,154: input=13, output=804
474 09:58:07.909509 [RTC]rtc_get_frequency_meter,154: input=12, output=788
475 09:58:07.919467 [RTC]rtc_get_frequency_meter,154: input=12, output=788
476 09:58:07.929297 [RTC]rtc_get_frequency_meter,154: input=13, output=803
477 09:58:07.932075 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
478 09:58:07.939220 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
479 09:58:07.943021 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 09:58:07.945824 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 09:58:07.952406 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 09:58:07.955849 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 09:58:07.959067 ADC[4]: Raw value=904509 ID=7
484 09:58:07.959158 ADC[3]: Raw value=212912 ID=1
485 09:58:07.962283 RAM Code: 0x71
486 09:58:07.965550 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 09:58:07.972286 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 09:58:07.979085 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 09:58:07.985483 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 09:58:07.988802 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 09:58:07.992445 in-header: 03 07 00 00 08 00 00 00
492 09:58:07.995767 in-data: aa e4 47 04 13 02 00 00
493 09:58:07.999101 Chrome EC: UHEPI supported
494 09:58:08.005937 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 09:58:08.008888 in-header: 03 dd 00 00 08 00 00 00
496 09:58:08.012634 in-data: 90 20 60 08 00 00 00 00
497 09:58:08.015810 MRC: failed to locate region type 0.
498 09:58:08.022407 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 09:58:08.025525 DRAM-K: Running full calibration
500 09:58:08.032083 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 09:58:08.032169 header.status = 0x0
502 09:58:08.035599 header.version = 0x6 (expected: 0x6)
503 09:58:08.039374 header.size = 0xd00 (expected: 0xd00)
504 09:58:08.042299 header.flags = 0x0
505 09:58:08.048614 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 09:58:08.065566 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 09:58:08.072577 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 09:58:08.075632 dram_init: ddr_geometry: 2
509 09:58:08.079180 [EMI] MDL number = 2
510 09:58:08.079273 [EMI] Get MDL freq = 0
511 09:58:08.082320 dram_init: ddr_type: 0
512 09:58:08.082423 is_discrete_lpddr4: 1
513 09:58:08.085946 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 09:58:08.086032
515 09:58:08.086101
516 09:58:08.089301 [Bian_co] ETT version 0.0.0.1
517 09:58:08.095332 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 09:58:08.095416
519 09:58:08.098791 dramc_set_vcore_voltage set vcore to 650000
520 09:58:08.102154 Read voltage for 800, 4
521 09:58:08.102230 Vio18 = 0
522 09:58:08.102294 Vcore = 650000
523 09:58:08.102373 Vdram = 0
524 09:58:08.106255 Vddq = 0
525 09:58:08.106341 Vmddr = 0
526 09:58:08.108893 dram_init: config_dvfs: 1
527 09:58:08.112528 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 09:58:08.118919 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 09:58:08.122590 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
530 09:58:08.125587 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
531 09:58:08.129414 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
532 09:58:08.132645 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
533 09:58:08.135735 MEM_TYPE=3, freq_sel=18
534 09:58:08.139178 sv_algorithm_assistance_LP4_1600
535 09:58:08.142237 ============ PULL DRAM RESETB DOWN ============
536 09:58:08.149183 ========== PULL DRAM RESETB DOWN end =========
537 09:58:08.152177 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 09:58:08.155413 ===================================
539 09:58:08.158738 LPDDR4 DRAM CONFIGURATION
540 09:58:08.162122 ===================================
541 09:58:08.162233 EX_ROW_EN[0] = 0x0
542 09:58:08.165178 EX_ROW_EN[1] = 0x0
543 09:58:08.165290 LP4Y_EN = 0x0
544 09:58:08.168870 WORK_FSP = 0x0
545 09:58:08.168996 WL = 0x2
546 09:58:08.172215 RL = 0x2
547 09:58:08.172329 BL = 0x2
548 09:58:08.175443 RPST = 0x0
549 09:58:08.175524 RD_PRE = 0x0
550 09:58:08.178896 WR_PRE = 0x1
551 09:58:08.179018 WR_PST = 0x0
552 09:58:08.182149 DBI_WR = 0x0
553 09:58:08.182240 DBI_RD = 0x0
554 09:58:08.185682 OTF = 0x1
555 09:58:08.188482 ===================================
556 09:58:08.191783 ===================================
557 09:58:08.191892 ANA top config
558 09:58:08.195426 ===================================
559 09:58:08.198461 DLL_ASYNC_EN = 0
560 09:58:08.202189 ALL_SLAVE_EN = 1
561 09:58:08.205248 NEW_RANK_MODE = 1
562 09:58:08.208201 DLL_IDLE_MODE = 1
563 09:58:08.208286 LP45_APHY_COMB_EN = 1
564 09:58:08.212101 TX_ODT_DIS = 1
565 09:58:08.214996 NEW_8X_MODE = 1
566 09:58:08.218359 ===================================
567 09:58:08.221660 ===================================
568 09:58:08.224962 data_rate = 1600
569 09:58:08.228535 CKR = 1
570 09:58:08.228630 DQ_P2S_RATIO = 8
571 09:58:08.231975 ===================================
572 09:58:08.234861 CA_P2S_RATIO = 8
573 09:58:08.238648 DQ_CA_OPEN = 0
574 09:58:08.241864 DQ_SEMI_OPEN = 0
575 09:58:08.244949 CA_SEMI_OPEN = 0
576 09:58:08.248272 CA_FULL_RATE = 0
577 09:58:08.248386 DQ_CKDIV4_EN = 1
578 09:58:08.252049 CA_CKDIV4_EN = 1
579 09:58:08.255015 CA_PREDIV_EN = 0
580 09:58:08.258523 PH8_DLY = 0
581 09:58:08.261602 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 09:58:08.264722 DQ_AAMCK_DIV = 4
583 09:58:08.264834 CA_AAMCK_DIV = 4
584 09:58:08.268252 CA_ADMCK_DIV = 4
585 09:58:08.271791 DQ_TRACK_CA_EN = 0
586 09:58:08.275010 CA_PICK = 800
587 09:58:08.278251 CA_MCKIO = 800
588 09:58:08.281444 MCKIO_SEMI = 0
589 09:58:08.284752 PLL_FREQ = 3068
590 09:58:08.284834 DQ_UI_PI_RATIO = 32
591 09:58:08.287905 CA_UI_PI_RATIO = 0
592 09:58:08.291141 ===================================
593 09:58:08.294777 ===================================
594 09:58:08.298086 memory_type:LPDDR4
595 09:58:08.301361 GP_NUM : 10
596 09:58:08.301451 SRAM_EN : 1
597 09:58:08.304401 MD32_EN : 0
598 09:58:08.308418 ===================================
599 09:58:08.311406 [ANA_INIT] >>>>>>>>>>>>>>
600 09:58:08.311527 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 09:58:08.314531 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 09:58:08.318462 ===================================
603 09:58:08.321321 data_rate = 1600,PCW = 0X7600
604 09:58:08.324353 ===================================
605 09:58:08.327880 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 09:58:08.334720 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 09:58:08.341578 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 09:58:08.344415 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 09:58:08.348189 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 09:58:08.351287 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 09:58:08.354197 [ANA_INIT] flow start
612 09:58:08.354288 [ANA_INIT] PLL >>>>>>>>
613 09:58:08.357900 [ANA_INIT] PLL <<<<<<<<
614 09:58:08.360912 [ANA_INIT] MIDPI >>>>>>>>
615 09:58:08.361018 [ANA_INIT] MIDPI <<<<<<<<
616 09:58:08.364620 [ANA_INIT] DLL >>>>>>>>
617 09:58:08.367842 [ANA_INIT] flow end
618 09:58:08.370833 ============ LP4 DIFF to SE enter ============
619 09:58:08.374507 ============ LP4 DIFF to SE exit ============
620 09:58:08.377515 [ANA_INIT] <<<<<<<<<<<<<
621 09:58:08.380915 [Flow] Enable top DCM control >>>>>
622 09:58:08.384161 [Flow] Enable top DCM control <<<<<
623 09:58:08.387944 Enable DLL master slave shuffle
624 09:58:08.391241 ==============================================================
625 09:58:08.393981 Gating Mode config
626 09:58:08.401129 ==============================================================
627 09:58:08.401245 Config description:
628 09:58:08.410772 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 09:58:08.417211 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 09:58:08.423950 SELPH_MODE 0: By rank 1: By Phase
631 09:58:08.427114 ==============================================================
632 09:58:08.430844 GAT_TRACK_EN = 1
633 09:58:08.434163 RX_GATING_MODE = 2
634 09:58:08.437596 RX_GATING_TRACK_MODE = 2
635 09:58:08.440437 SELPH_MODE = 1
636 09:58:08.443748 PICG_EARLY_EN = 1
637 09:58:08.447198 VALID_LAT_VALUE = 1
638 09:58:08.450373 ==============================================================
639 09:58:08.453922 Enter into Gating configuration >>>>
640 09:58:08.457529 Exit from Gating configuration <<<<
641 09:58:08.460627 Enter into DVFS_PRE_config >>>>>
642 09:58:08.473851 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 09:58:08.477348 Exit from DVFS_PRE_config <<<<<
644 09:58:08.477460 Enter into PICG configuration >>>>
645 09:58:08.480427 Exit from PICG configuration <<<<
646 09:58:08.483485 [RX_INPUT] configuration >>>>>
647 09:58:08.487269 [RX_INPUT] configuration <<<<<
648 09:58:08.493833 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 09:58:08.497288 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 09:58:08.504479 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 09:58:08.511546 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 09:58:08.515003 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 09:58:08.521616 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 09:58:08.524995 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 09:58:08.532253 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 09:58:08.536055 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 09:58:08.539031 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 09:58:08.543279 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 09:58:08.546917 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 09:58:08.550013 ===================================
661 09:58:08.554063 LPDDR4 DRAM CONFIGURATION
662 09:58:08.557350 ===================================
663 09:58:08.557462 EX_ROW_EN[0] = 0x0
664 09:58:08.561482 EX_ROW_EN[1] = 0x0
665 09:58:08.561570 LP4Y_EN = 0x0
666 09:58:08.564525 WORK_FSP = 0x0
667 09:58:08.564611 WL = 0x2
668 09:58:08.568146 RL = 0x2
669 09:58:08.568233 BL = 0x2
670 09:58:08.572252 RPST = 0x0
671 09:58:08.572334 RD_PRE = 0x0
672 09:58:08.575357 WR_PRE = 0x1
673 09:58:08.575439 WR_PST = 0x0
674 09:58:08.579073 DBI_WR = 0x0
675 09:58:08.579166 DBI_RD = 0x0
676 09:58:08.582758 OTF = 0x1
677 09:58:08.582869 ===================================
678 09:58:08.586556 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 09:58:08.594509 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 09:58:08.597991 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 09:58:08.601698 ===================================
682 09:58:08.601812 LPDDR4 DRAM CONFIGURATION
683 09:58:08.604983 ===================================
684 09:58:08.608490 EX_ROW_EN[0] = 0x10
685 09:58:08.608603 EX_ROW_EN[1] = 0x0
686 09:58:08.612574 LP4Y_EN = 0x0
687 09:58:08.612661 WORK_FSP = 0x0
688 09:58:08.615960 WL = 0x2
689 09:58:08.616071 RL = 0x2
690 09:58:08.619573 BL = 0x2
691 09:58:08.619689 RPST = 0x0
692 09:58:08.623230 RD_PRE = 0x0
693 09:58:08.623313 WR_PRE = 0x1
694 09:58:08.626685 WR_PST = 0x0
695 09:58:08.626768 DBI_WR = 0x0
696 09:58:08.630595 DBI_RD = 0x0
697 09:58:08.630679 OTF = 0x1
698 09:58:08.634087 ===================================
699 09:58:08.640712 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 09:58:08.644490 nWR fixed to 40
701 09:58:08.648207 [ModeRegInit_LP4] CH0 RK0
702 09:58:08.648292 [ModeRegInit_LP4] CH0 RK1
703 09:58:08.652001 [ModeRegInit_LP4] CH1 RK0
704 09:58:08.652088 [ModeRegInit_LP4] CH1 RK1
705 09:58:08.655757 match AC timing 13
706 09:58:08.659439 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 09:58:08.663097 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 09:58:08.669628 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 09:58:08.673428 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 09:58:08.677106 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 09:58:08.680063 [EMI DOE] emi_dcm 0
712 09:58:08.683068 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 09:58:08.683155 ==
714 09:58:08.686846 Dram Type= 6, Freq= 0, CH_0, rank 0
715 09:58:08.689953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 09:58:08.690063 ==
717 09:58:08.696803 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 09:58:08.702762 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 09:58:08.711606 [CA 0] Center 37 (6~68) winsize 63
720 09:58:08.714753 [CA 1] Center 36 (6~67) winsize 62
721 09:58:08.718282 [CA 2] Center 34 (4~65) winsize 62
722 09:58:08.721571 [CA 3] Center 34 (4~65) winsize 62
723 09:58:08.724506 [CA 4] Center 33 (3~64) winsize 62
724 09:58:08.728435 [CA 5] Center 33 (3~64) winsize 62
725 09:58:08.728522
726 09:58:08.731406 [CmdBusTrainingLP45] Vref(ca) range 1: 32
727 09:58:08.731492
728 09:58:08.734649 [CATrainingPosCal] consider 1 rank data
729 09:58:08.738398 u2DelayCellTimex100 = 270/100 ps
730 09:58:08.741313 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
731 09:58:08.747793 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
732 09:58:08.751389 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 09:58:08.755011 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 09:58:08.758295 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 09:58:08.761265 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 09:58:08.761382
737 09:58:08.764791 CA PerBit enable=1, Macro0, CA PI delay=33
738 09:58:08.764881
739 09:58:08.767890 [CBTSetCACLKResult] CA Dly = 33
740 09:58:08.768002 CS Dly: 6 (0~37)
741 09:58:08.771721 ==
742 09:58:08.771837 Dram Type= 6, Freq= 0, CH_0, rank 1
743 09:58:08.777981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 09:58:08.778066 ==
745 09:58:08.781440 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 09:58:08.788389 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 09:58:08.798030 [CA 0] Center 37 (6~68) winsize 63
748 09:58:08.800991 [CA 1] Center 37 (7~68) winsize 62
749 09:58:08.804757 [CA 2] Center 34 (3~65) winsize 63
750 09:58:08.807917 [CA 3] Center 34 (4~65) winsize 62
751 09:58:08.811072 [CA 4] Center 33 (3~64) winsize 62
752 09:58:08.814711 [CA 5] Center 33 (3~64) winsize 62
753 09:58:08.814804
754 09:58:08.818059 [CmdBusTrainingLP45] Vref(ca) range 1: 32
755 09:58:08.818139
756 09:58:08.820983 [CATrainingPosCal] consider 2 rank data
757 09:58:08.824624 u2DelayCellTimex100 = 270/100 ps
758 09:58:08.827996 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
759 09:58:08.831128 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
760 09:58:08.837776 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
761 09:58:08.840850 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 09:58:08.844656 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 09:58:08.847449 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 09:58:08.847531
765 09:58:08.851835 CA PerBit enable=1, Macro0, CA PI delay=33
766 09:58:08.851959
767 09:58:08.855430 [CBTSetCACLKResult] CA Dly = 33
768 09:58:08.855548 CS Dly: 6 (0~38)
769 09:58:08.855659
770 09:58:08.858773 ----->DramcWriteLeveling(PI) begin...
771 09:58:08.858859 ==
772 09:58:08.862367 Dram Type= 6, Freq= 0, CH_0, rank 0
773 09:58:08.866254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 09:58:08.866340 ==
775 09:58:08.869754 Write leveling (Byte 0): 32 => 32
776 09:58:08.872810 Write leveling (Byte 1): 31 => 31
777 09:58:08.876023 DramcWriteLeveling(PI) end<-----
778 09:58:08.876106
779 09:58:08.876174 ==
780 09:58:08.879986 Dram Type= 6, Freq= 0, CH_0, rank 0
781 09:58:08.882722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 09:58:08.882833 ==
783 09:58:08.886489 [Gating] SW mode calibration
784 09:58:08.893194 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 09:58:08.899380 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 09:58:08.902993 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 09:58:08.909939 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 09:58:08.912857 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
789 09:58:08.916013 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 09:58:08.922673 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 09:58:08.926014 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 09:58:08.929374 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 09:58:08.935878 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 09:58:08.939253 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 09:58:08.942750 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 09:58:08.945991 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 09:58:08.953065 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 09:58:08.955799 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 09:58:08.959267 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 09:58:08.965577 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 09:58:08.969400 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 09:58:08.972765 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 09:58:08.979096 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 09:58:08.982627 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 09:58:08.985765 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 09:58:08.992209 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 09:58:08.995652 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 09:58:08.999321 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 09:58:09.005770 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 09:58:09.008748 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 09:58:09.012409 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 09:58:09.019135 0 9 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)
813 09:58:09.022096 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (1 1) (1 1)
814 09:58:09.025527 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 09:58:09.032323 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 09:58:09.035892 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 09:58:09.038742 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 09:58:09.045525 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 09:58:09.048987 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
820 09:58:09.052116 0 10 8 | B1->B0 | 3333 2929 | 0 0 | (1 0) (0 0)
821 09:58:09.058713 0 10 12 | B1->B0 | 2929 2323 | 0 0 | (0 1) (0 0)
822 09:58:09.062206 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 09:58:09.065431 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 09:58:09.071912 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 09:58:09.075447 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 09:58:09.078642 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 09:58:09.081953 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
828 09:58:09.088627 0 11 8 | B1->B0 | 2727 3a3a | 0 1 | (0 0) (0 0)
829 09:58:09.092381 0 11 12 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
830 09:58:09.098337 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 09:58:09.101712 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 09:58:09.105495 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 09:58:09.108496 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 09:58:09.115176 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 09:58:09.118252 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 09:58:09.121882 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
837 09:58:09.128431 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 09:58:09.131377 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 09:58:09.134989 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 09:58:09.141511 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 09:58:09.144638 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 09:58:09.148315 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 09:58:09.154794 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 09:58:09.157930 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 09:58:09.161522 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 09:58:09.168168 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 09:58:09.171459 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 09:58:09.174602 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 09:58:09.181380 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 09:58:09.184941 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 09:58:09.187839 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 09:58:09.194501 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
853 09:58:09.197742 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
854 09:58:09.201114 Total UI for P1: 0, mck2ui 16
855 09:58:09.204581 best dqsien dly found for B0: ( 0, 14, 6)
856 09:58:09.207646 Total UI for P1: 0, mck2ui 16
857 09:58:09.211014 best dqsien dly found for B1: ( 0, 14, 8)
858 09:58:09.214153 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
859 09:58:09.217833 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 09:58:09.217936
861 09:58:09.220865 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
862 09:58:09.224399 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 09:58:09.228035 [Gating] SW calibration Done
864 09:58:09.228111 ==
865 09:58:09.231416 Dram Type= 6, Freq= 0, CH_0, rank 0
866 09:58:09.235173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 09:58:09.235254 ==
868 09:58:09.238372 RX Vref Scan: 0
869 09:58:09.238482
870 09:58:09.238558 RX Vref 0 -> 0, step: 1
871 09:58:09.241953
872 09:58:09.242020 RX Delay -130 -> 252, step: 16
873 09:58:09.248612 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 09:58:09.251978 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 09:58:09.255137 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
876 09:58:09.259107 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
877 09:58:09.262388 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 09:58:09.265939 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
879 09:58:09.269700 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
880 09:58:09.273383 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
881 09:58:09.277291 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
882 09:58:09.284595 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
883 09:58:09.288287 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
884 09:58:09.291626 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 09:58:09.295166 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
886 09:58:09.299373 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
887 09:58:09.302601 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
888 09:58:09.306382 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
889 09:58:09.306471 ==
890 09:58:09.309238 Dram Type= 6, Freq= 0, CH_0, rank 0
891 09:58:09.316028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 09:58:09.316118 ==
893 09:58:09.316207 DQS Delay:
894 09:58:09.319629 DQS0 = 0, DQS1 = 0
895 09:58:09.319716 DQM Delay:
896 09:58:09.319805 DQM0 = 84, DQM1 = 70
897 09:58:09.322644 DQ Delay:
898 09:58:09.326243 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
899 09:58:09.329391 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
900 09:58:09.332906 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
901 09:58:09.336448 DQ12 =69, DQ13 =77, DQ14 =77, DQ15 =77
902 09:58:09.336535
903 09:58:09.336603
904 09:58:09.336665 ==
905 09:58:09.339482 Dram Type= 6, Freq= 0, CH_0, rank 0
906 09:58:09.342793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 09:58:09.342884 ==
908 09:58:09.342966
909 09:58:09.343029
910 09:58:09.346459 TX Vref Scan disable
911 09:58:09.346530 == TX Byte 0 ==
912 09:58:09.352583 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
913 09:58:09.356212 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
914 09:58:09.356301 == TX Byte 1 ==
915 09:58:09.362942 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
916 09:58:09.366448 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
917 09:58:09.366573 ==
918 09:58:09.369841 Dram Type= 6, Freq= 0, CH_0, rank 0
919 09:58:09.373807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 09:58:09.373931 ==
921 09:58:09.387183 TX Vref=22, minBit 5, minWin=27, winSum=443
922 09:58:09.390519 TX Vref=24, minBit 8, minWin=27, winSum=444
923 09:58:09.394191 TX Vref=26, minBit 4, minWin=27, winSum=444
924 09:58:09.397202 TX Vref=28, minBit 8, minWin=27, winSum=447
925 09:58:09.401097 TX Vref=30, minBit 10, minWin=27, winSum=448
926 09:58:09.403951 TX Vref=32, minBit 10, minWin=27, winSum=446
927 09:58:09.410981 [TxChooseVref] Worse bit 10, Min win 27, Win sum 448, Final Vref 30
928 09:58:09.411066
929 09:58:09.414026 Final TX Range 1 Vref 30
930 09:58:09.414106
931 09:58:09.414186 ==
932 09:58:09.417932 Dram Type= 6, Freq= 0, CH_0, rank 0
933 09:58:09.420627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 09:58:09.420708 ==
935 09:58:09.420774
936 09:58:09.420853
937 09:58:09.423791 TX Vref Scan disable
938 09:58:09.427345 == TX Byte 0 ==
939 09:58:09.430552 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
940 09:58:09.434048 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
941 09:58:09.437244 == TX Byte 1 ==
942 09:58:09.440737 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
943 09:58:09.443830 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
944 09:58:09.443909
945 09:58:09.447592 [DATLAT]
946 09:58:09.447700 Freq=800, CH0 RK0
947 09:58:09.447769
948 09:58:09.450617 DATLAT Default: 0xa
949 09:58:09.450697 0, 0xFFFF, sum = 0
950 09:58:09.453994 1, 0xFFFF, sum = 0
951 09:58:09.454077 2, 0xFFFF, sum = 0
952 09:58:09.457427 3, 0xFFFF, sum = 0
953 09:58:09.457504 4, 0xFFFF, sum = 0
954 09:58:09.460612 5, 0xFFFF, sum = 0
955 09:58:09.460729 6, 0xFFFF, sum = 0
956 09:58:09.464232 7, 0xFFFF, sum = 0
957 09:58:09.464336 8, 0xFFFF, sum = 0
958 09:58:09.467289 9, 0x0, sum = 1
959 09:58:09.467373 10, 0x0, sum = 2
960 09:58:09.470470 11, 0x0, sum = 3
961 09:58:09.470551 12, 0x0, sum = 4
962 09:58:09.473967 best_step = 10
963 09:58:09.474066
964 09:58:09.474135 ==
965 09:58:09.476878 Dram Type= 6, Freq= 0, CH_0, rank 0
966 09:58:09.480594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 09:58:09.480698 ==
968 09:58:09.480802 RX Vref Scan: 1
969 09:58:09.483652
970 09:58:09.483736 Set Vref Range= 32 -> 127
971 09:58:09.483804
972 09:58:09.487213 RX Vref 32 -> 127, step: 1
973 09:58:09.487332
974 09:58:09.490468 RX Delay -111 -> 252, step: 8
975 09:58:09.490553
976 09:58:09.493962 Set Vref, RX VrefLevel [Byte0]: 32
977 09:58:09.497049 [Byte1]: 32
978 09:58:09.497161
979 09:58:09.500739 Set Vref, RX VrefLevel [Byte0]: 33
980 09:58:09.503829 [Byte1]: 33
981 09:58:09.507410
982 09:58:09.507493 Set Vref, RX VrefLevel [Byte0]: 34
983 09:58:09.510838 [Byte1]: 34
984 09:58:09.514686
985 09:58:09.514793 Set Vref, RX VrefLevel [Byte0]: 35
986 09:58:09.518169 [Byte1]: 35
987 09:58:09.522558
988 09:58:09.522641 Set Vref, RX VrefLevel [Byte0]: 36
989 09:58:09.525516 [Byte1]: 36
990 09:58:09.530597
991 09:58:09.530682 Set Vref, RX VrefLevel [Byte0]: 37
992 09:58:09.534032 [Byte1]: 37
993 09:58:09.537457
994 09:58:09.537558 Set Vref, RX VrefLevel [Byte0]: 38
995 09:58:09.541200 [Byte1]: 38
996 09:58:09.545506
997 09:58:09.545587 Set Vref, RX VrefLevel [Byte0]: 39
998 09:58:09.548572 [Byte1]: 39
999 09:58:09.552687
1000 09:58:09.552775 Set Vref, RX VrefLevel [Byte0]: 40
1001 09:58:09.556576 [Byte1]: 40
1002 09:58:09.560899
1003 09:58:09.560994 Set Vref, RX VrefLevel [Byte0]: 41
1004 09:58:09.563970 [Byte1]: 41
1005 09:58:09.568310
1006 09:58:09.568398 Set Vref, RX VrefLevel [Byte0]: 42
1007 09:58:09.571565 [Byte1]: 42
1008 09:58:09.576124
1009 09:58:09.576231 Set Vref, RX VrefLevel [Byte0]: 43
1010 09:58:09.579026 [Byte1]: 43
1011 09:58:09.583770
1012 09:58:09.583879 Set Vref, RX VrefLevel [Byte0]: 44
1013 09:58:09.587003 [Byte1]: 44
1014 09:58:09.591281
1015 09:58:09.591361 Set Vref, RX VrefLevel [Byte0]: 45
1016 09:58:09.594758 [Byte1]: 45
1017 09:58:09.598873
1018 09:58:09.598986 Set Vref, RX VrefLevel [Byte0]: 46
1019 09:58:09.601974 [Byte1]: 46
1020 09:58:09.606334
1021 09:58:09.606437 Set Vref, RX VrefLevel [Byte0]: 47
1022 09:58:09.609533 [Byte1]: 47
1023 09:58:09.614025
1024 09:58:09.614109 Set Vref, RX VrefLevel [Byte0]: 48
1025 09:58:09.617252 [Byte1]: 48
1026 09:58:09.621931
1027 09:58:09.622011 Set Vref, RX VrefLevel [Byte0]: 49
1028 09:58:09.625372 [Byte1]: 49
1029 09:58:09.629370
1030 09:58:09.629503 Set Vref, RX VrefLevel [Byte0]: 50
1031 09:58:09.632484 [Byte1]: 50
1032 09:58:09.637049
1033 09:58:09.637130 Set Vref, RX VrefLevel [Byte0]: 51
1034 09:58:09.640186 [Byte1]: 51
1035 09:58:09.644726
1036 09:58:09.644839 Set Vref, RX VrefLevel [Byte0]: 52
1037 09:58:09.647805 [Byte1]: 52
1038 09:58:09.652126
1039 09:58:09.652238 Set Vref, RX VrefLevel [Byte0]: 53
1040 09:58:09.655810 [Byte1]: 53
1041 09:58:09.660115
1042 09:58:09.660215 Set Vref, RX VrefLevel [Byte0]: 54
1043 09:58:09.663406 [Byte1]: 54
1044 09:58:09.667568
1045 09:58:09.667679 Set Vref, RX VrefLevel [Byte0]: 55
1046 09:58:09.670740 [Byte1]: 55
1047 09:58:09.675385
1048 09:58:09.675507 Set Vref, RX VrefLevel [Byte0]: 56
1049 09:58:09.678475 [Byte1]: 56
1050 09:58:09.683038
1051 09:58:09.683150 Set Vref, RX VrefLevel [Byte0]: 57
1052 09:58:09.686171 [Byte1]: 57
1053 09:58:09.690366
1054 09:58:09.690501 Set Vref, RX VrefLevel [Byte0]: 58
1055 09:58:09.693835 [Byte1]: 58
1056 09:58:09.698229
1057 09:58:09.698340 Set Vref, RX VrefLevel [Byte0]: 59
1058 09:58:09.701604 [Byte1]: 59
1059 09:58:09.705715
1060 09:58:09.705826 Set Vref, RX VrefLevel [Byte0]: 60
1061 09:58:09.709482 [Byte1]: 60
1062 09:58:09.713667
1063 09:58:09.713777 Set Vref, RX VrefLevel [Byte0]: 61
1064 09:58:09.716950 [Byte1]: 61
1065 09:58:09.721017
1066 09:58:09.721127 Set Vref, RX VrefLevel [Byte0]: 62
1067 09:58:09.724182 [Byte1]: 62
1068 09:58:09.729127
1069 09:58:09.729206 Set Vref, RX VrefLevel [Byte0]: 63
1070 09:58:09.731856 [Byte1]: 63
1071 09:58:09.736416
1072 09:58:09.736503 Set Vref, RX VrefLevel [Byte0]: 64
1073 09:58:09.739521 [Byte1]: 64
1074 09:58:09.743762
1075 09:58:09.743866 Set Vref, RX VrefLevel [Byte0]: 65
1076 09:58:09.747221 [Byte1]: 65
1077 09:58:09.751392
1078 09:58:09.751472 Set Vref, RX VrefLevel [Byte0]: 66
1079 09:58:09.755083 [Byte1]: 66
1080 09:58:09.759461
1081 09:58:09.759568 Set Vref, RX VrefLevel [Byte0]: 67
1082 09:58:09.762675 [Byte1]: 67
1083 09:58:09.766894
1084 09:58:09.766977 Set Vref, RX VrefLevel [Byte0]: 68
1085 09:58:09.770521 [Byte1]: 68
1086 09:58:09.774840
1087 09:58:09.774946 Set Vref, RX VrefLevel [Byte0]: 69
1088 09:58:09.778151 [Byte1]: 69
1089 09:58:09.782455
1090 09:58:09.782539 Set Vref, RX VrefLevel [Byte0]: 70
1091 09:58:09.785529 [Byte1]: 70
1092 09:58:09.790060
1093 09:58:09.793497 Set Vref, RX VrefLevel [Byte0]: 71
1094 09:58:09.796413 [Byte1]: 71
1095 09:58:09.796519
1096 09:58:09.799619 Set Vref, RX VrefLevel [Byte0]: 72
1097 09:58:09.802824 [Byte1]: 72
1098 09:58:09.802940
1099 09:58:09.806506 Set Vref, RX VrefLevel [Byte0]: 73
1100 09:58:09.809885 [Byte1]: 73
1101 09:58:09.809967
1102 09:58:09.813239 Set Vref, RX VrefLevel [Byte0]: 74
1103 09:58:09.816343 [Byte1]: 74
1104 09:58:09.820484
1105 09:58:09.820598 Set Vref, RX VrefLevel [Byte0]: 75
1106 09:58:09.823607 [Byte1]: 75
1107 09:58:09.827990
1108 09:58:09.828069 Set Vref, RX VrefLevel [Byte0]: 76
1109 09:58:09.831694 [Byte1]: 76
1110 09:58:09.836017
1111 09:58:09.836128 Set Vref, RX VrefLevel [Byte0]: 77
1112 09:58:09.838914 [Byte1]: 77
1113 09:58:09.843692
1114 09:58:09.843793 Set Vref, RX VrefLevel [Byte0]: 78
1115 09:58:09.847155 [Byte1]: 78
1116 09:58:09.851203
1117 09:58:09.851315 Set Vref, RX VrefLevel [Byte0]: 79
1118 09:58:09.854632 [Byte1]: 79
1119 09:58:09.858473
1120 09:58:09.862017 Set Vref, RX VrefLevel [Byte0]: 80
1121 09:58:09.862122 [Byte1]: 80
1122 09:58:09.866661
1123 09:58:09.866762 Final RX Vref Byte 0 = 69 to rank0
1124 09:58:09.870456 Final RX Vref Byte 1 = 56 to rank0
1125 09:58:09.874339 Final RX Vref Byte 0 = 69 to rank1
1126 09:58:09.877316 Final RX Vref Byte 1 = 56 to rank1==
1127 09:58:09.881006 Dram Type= 6, Freq= 0, CH_0, rank 0
1128 09:58:09.884442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1129 09:58:09.884536 ==
1130 09:58:09.884608 DQS Delay:
1131 09:58:09.887852 DQS0 = 0, DQS1 = 0
1132 09:58:09.887968 DQM Delay:
1133 09:58:09.891238 DQM0 = 88, DQM1 = 75
1134 09:58:09.891343 DQ Delay:
1135 09:58:09.894906 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1136 09:58:09.899031 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =100
1137 09:58:09.902365 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1138 09:58:09.905644 DQ12 =80, DQ13 =76, DQ14 =88, DQ15 =84
1139 09:58:09.905728
1140 09:58:09.905796
1141 09:58:09.913264 [DQSOSCAuto] RK0, (LSB)MR18= 0x4223, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
1142 09:58:09.916735 CH0 RK0: MR19=606, MR18=4223
1143 09:58:09.920444 CH0_RK0: MR19=0x606, MR18=0x4223, DQSOSC=393, MR23=63, INC=95, DEC=63
1144 09:58:09.920531
1145 09:58:09.923673 ----->DramcWriteLeveling(PI) begin...
1146 09:58:09.927404 ==
1147 09:58:09.927490 Dram Type= 6, Freq= 0, CH_0, rank 1
1148 09:58:09.935381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1149 09:58:09.935473 ==
1150 09:58:09.935540 Write leveling (Byte 0): 36 => 36
1151 09:58:09.938909 Write leveling (Byte 1): 31 => 31
1152 09:58:09.942697 DramcWriteLeveling(PI) end<-----
1153 09:58:09.942780
1154 09:58:09.942855 ==
1155 09:58:09.946378 Dram Type= 6, Freq= 0, CH_0, rank 1
1156 09:58:09.949293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1157 09:58:09.949398 ==
1158 09:58:09.953351 [Gating] SW mode calibration
1159 09:58:09.961001 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1160 09:58:10.004510 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1161 09:58:10.005119 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1162 09:58:10.005376 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1163 09:58:10.005465 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1164 09:58:10.005539 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 09:58:10.005610 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 09:58:10.006468 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 09:58:10.006766 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 09:58:10.006834 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 09:58:10.006904 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 09:58:10.048845 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 09:58:10.049405 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 09:58:10.050224 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 09:58:10.050299 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 09:58:10.050581 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 09:58:10.050666 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 09:58:10.050924 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 09:58:10.051237 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 09:58:10.051342 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 09:58:10.051447 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1180 09:58:10.092709 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 09:58:10.093307 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 09:58:10.093614 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 09:58:10.093689 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 09:58:10.093766 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 09:58:10.093840 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 09:58:10.093902 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 09:58:10.094610 0 9 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
1188 09:58:10.094678 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1189 09:58:10.094921 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1190 09:58:10.136799 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1191 09:58:10.137121 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1192 09:58:10.137238 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1193 09:58:10.137335 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1194 09:58:10.137460 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1195 09:58:10.137553 0 10 8 | B1->B0 | 3131 2727 | 0 1 | (0 0) (1 0)
1196 09:58:10.137641 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1197 09:58:10.137923 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 09:58:10.138016 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 09:58:10.138115 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 09:58:10.181137 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 09:58:10.181459 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 09:58:10.181563 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1203 09:58:10.181656 0 11 8 | B1->B0 | 2b2b 4444 | 0 1 | (0 0) (0 0)
1204 09:58:10.181969 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 09:58:10.182462 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 09:58:10.183086 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 09:58:10.183640 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 09:58:10.183738 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 09:58:10.184235 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 09:58:10.214681 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1211 09:58:10.215257 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1212 09:58:10.216033 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1213 09:58:10.216134 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 09:58:10.216422 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 09:58:10.216519 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 09:58:10.216621 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 09:58:10.220351 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 09:58:10.220454 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 09:58:10.223381 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 09:58:10.229985 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 09:58:10.234230 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 09:58:10.237673 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 09:58:10.241043 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 09:58:10.245389 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 09:58:10.252310 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 09:58:10.256003 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 09:58:10.259480 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1228 09:58:10.263440 Total UI for P1: 0, mck2ui 16
1229 09:58:10.266721 best dqsien dly found for B0: ( 0, 14, 6)
1230 09:58:10.270321 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1231 09:58:10.274383 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1232 09:58:10.277958 Total UI for P1: 0, mck2ui 16
1233 09:58:10.281431 best dqsien dly found for B1: ( 0, 14, 10)
1234 09:58:10.284762 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1235 09:58:10.288686 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1236 09:58:10.288779
1237 09:58:10.292488 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1238 09:58:10.296449 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1239 09:58:10.299572 [Gating] SW calibration Done
1240 09:58:10.299683 ==
1241 09:58:10.303331 Dram Type= 6, Freq= 0, CH_0, rank 1
1242 09:58:10.306830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1243 09:58:10.306936 ==
1244 09:58:10.307034 RX Vref Scan: 0
1245 09:58:10.310455
1246 09:58:10.310560 RX Vref 0 -> 0, step: 1
1247 09:58:10.310663
1248 09:58:10.313791 RX Delay -130 -> 252, step: 16
1249 09:58:10.317532 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1250 09:58:10.320352 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1251 09:58:10.327008 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1252 09:58:10.330177 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1253 09:58:10.333937 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1254 09:58:10.337414 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1255 09:58:10.340628 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1256 09:58:10.347254 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1257 09:58:10.350217 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1258 09:58:10.354033 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1259 09:58:10.356887 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1260 09:58:10.360502 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1261 09:58:10.367259 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1262 09:58:10.370269 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1263 09:58:10.373767 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1264 09:58:10.377018 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1265 09:58:10.377097 ==
1266 09:58:10.380420 Dram Type= 6, Freq= 0, CH_0, rank 1
1267 09:58:10.387387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1268 09:58:10.387469 ==
1269 09:58:10.387535 DQS Delay:
1270 09:58:10.387596 DQS0 = 0, DQS1 = 0
1271 09:58:10.390389 DQM Delay:
1272 09:58:10.390466 DQM0 = 84, DQM1 = 75
1273 09:58:10.393787 DQ Delay:
1274 09:58:10.397087 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =69
1275 09:58:10.400313 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
1276 09:58:10.403677 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1277 09:58:10.406940 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1278 09:58:10.407020
1279 09:58:10.407083
1280 09:58:10.407142 ==
1281 09:58:10.410660 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 09:58:10.413761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 09:58:10.413833 ==
1284 09:58:10.413895
1285 09:58:10.413952
1286 09:58:10.416727 TX Vref Scan disable
1287 09:58:10.416800 == TX Byte 0 ==
1288 09:58:10.423431 Update DQ dly =588 (2 ,2, 12) DQ OEN =(1 ,7)
1289 09:58:10.427023 Update DQM dly =588 (2 ,2, 12) DQM OEN =(1 ,7)
1290 09:58:10.427101 == TX Byte 1 ==
1291 09:58:10.433746 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1292 09:58:10.436743 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1293 09:58:10.436825 ==
1294 09:58:10.439805 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 09:58:10.443421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 09:58:10.443505 ==
1297 09:58:10.458140 TX Vref=22, minBit 3, minWin=27, winSum=441
1298 09:58:10.461567 TX Vref=24, minBit 3, minWin=27, winSum=446
1299 09:58:10.464760 TX Vref=26, minBit 2, minWin=27, winSum=444
1300 09:58:10.468292 TX Vref=28, minBit 7, minWin=27, winSum=445
1301 09:58:10.471241 TX Vref=30, minBit 5, minWin=27, winSum=442
1302 09:58:10.474780 TX Vref=32, minBit 2, minWin=27, winSum=441
1303 09:58:10.481301 [TxChooseVref] Worse bit 3, Min win 27, Win sum 446, Final Vref 24
1304 09:58:10.481397
1305 09:58:10.484325 Final TX Range 1 Vref 24
1306 09:58:10.484410
1307 09:58:10.484470 ==
1308 09:58:10.487698 Dram Type= 6, Freq= 0, CH_0, rank 1
1309 09:58:10.491040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1310 09:58:10.494426 ==
1311 09:58:10.494538
1312 09:58:10.494603
1313 09:58:10.494666 TX Vref Scan disable
1314 09:58:10.497966 == TX Byte 0 ==
1315 09:58:10.501742 Update DQ dly =587 (2 ,2, 11) DQ OEN =(1 ,7)
1316 09:58:10.507947 Update DQM dly =587 (2 ,2, 11) DQM OEN =(1 ,7)
1317 09:58:10.508053 == TX Byte 1 ==
1318 09:58:10.511456 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1319 09:58:10.517849 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1320 09:58:10.517926
1321 09:58:10.517988 [DATLAT]
1322 09:58:10.518047 Freq=800, CH0 RK1
1323 09:58:10.518103
1324 09:58:10.521443 DATLAT Default: 0xa
1325 09:58:10.521526 0, 0xFFFF, sum = 0
1326 09:58:10.524725 1, 0xFFFF, sum = 0
1327 09:58:10.524798 2, 0xFFFF, sum = 0
1328 09:58:10.528333 3, 0xFFFF, sum = 0
1329 09:58:10.531223 4, 0xFFFF, sum = 0
1330 09:58:10.531295 5, 0xFFFF, sum = 0
1331 09:58:10.534405 6, 0xFFFF, sum = 0
1332 09:58:10.534503 7, 0xFFFF, sum = 0
1333 09:58:10.538082 8, 0xFFFF, sum = 0
1334 09:58:10.538158 9, 0x0, sum = 1
1335 09:58:10.538222 10, 0x0, sum = 2
1336 09:58:10.541165 11, 0x0, sum = 3
1337 09:58:10.541230 12, 0x0, sum = 4
1338 09:58:10.544915 best_step = 10
1339 09:58:10.544994
1340 09:58:10.545060 ==
1341 09:58:10.547896 Dram Type= 6, Freq= 0, CH_0, rank 1
1342 09:58:10.551024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1343 09:58:10.551104 ==
1344 09:58:10.554199 RX Vref Scan: 0
1345 09:58:10.554318
1346 09:58:10.554409 RX Vref 0 -> 0, step: 1
1347 09:58:10.557921
1348 09:58:10.558056 RX Delay -111 -> 252, step: 8
1349 09:58:10.565065 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1350 09:58:10.568181 iDelay=217, Bit 1, Center 88 (-23 ~ 200) 224
1351 09:58:10.571670 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
1352 09:58:10.574820 iDelay=217, Bit 3, Center 80 (-31 ~ 192) 224
1353 09:58:10.578330 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1354 09:58:10.584932 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1355 09:58:10.587975 iDelay=217, Bit 6, Center 96 (-15 ~ 208) 224
1356 09:58:10.591520 iDelay=217, Bit 7, Center 100 (-15 ~ 216) 232
1357 09:58:10.594489 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1358 09:58:10.598454 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1359 09:58:10.604987 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
1360 09:58:10.608082 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1361 09:58:10.611521 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1362 09:58:10.614560 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1363 09:58:10.621364 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
1364 09:58:10.624848 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1365 09:58:10.624952 ==
1366 09:58:10.628323 Dram Type= 6, Freq= 0, CH_0, rank 1
1367 09:58:10.631219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1368 09:58:10.631327 ==
1369 09:58:10.631426 DQS Delay:
1370 09:58:10.634803 DQS0 = 0, DQS1 = 0
1371 09:58:10.634881 DQM Delay:
1372 09:58:10.638025 DQM0 = 86, DQM1 = 77
1373 09:58:10.638102 DQ Delay:
1374 09:58:10.641686 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1375 09:58:10.644814 DQ4 =84, DQ5 =76, DQ6 =96, DQ7 =100
1376 09:58:10.647740 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =68
1377 09:58:10.651446 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1378 09:58:10.651531
1379 09:58:10.651628
1380 09:58:10.661273 [DQSOSCAuto] RK1, (LSB)MR18= 0x450b, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 392 ps
1381 09:58:10.661355 CH0 RK1: MR19=606, MR18=450B
1382 09:58:10.667985 CH0_RK1: MR19=0x606, MR18=0x450B, DQSOSC=392, MR23=63, INC=96, DEC=64
1383 09:58:10.671355 [RxdqsGatingPostProcess] freq 800
1384 09:58:10.678678 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1385 09:58:10.681029 Pre-setting of DQS Precalculation
1386 09:58:10.684676 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1387 09:58:10.684749 ==
1388 09:58:10.687905 Dram Type= 6, Freq= 0, CH_1, rank 0
1389 09:58:10.690976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1390 09:58:10.694564 ==
1391 09:58:10.697710 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1392 09:58:10.704284 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1393 09:58:10.713560 [CA 0] Center 36 (6~67) winsize 62
1394 09:58:10.716784 [CA 1] Center 36 (6~67) winsize 62
1395 09:58:10.719879 [CA 2] Center 34 (4~65) winsize 62
1396 09:58:10.723182 [CA 3] Center 34 (3~65) winsize 63
1397 09:58:10.726656 [CA 4] Center 34 (4~65) winsize 62
1398 09:58:10.730383 [CA 5] Center 34 (3~65) winsize 63
1399 09:58:10.730521
1400 09:58:10.733328 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1401 09:58:10.733532
1402 09:58:10.736649 [CATrainingPosCal] consider 1 rank data
1403 09:58:10.739860 u2DelayCellTimex100 = 270/100 ps
1404 09:58:10.743526 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1405 09:58:10.746557 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1406 09:58:10.753302 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1407 09:58:10.756594 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1408 09:58:10.760090 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1409 09:58:10.763089 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1410 09:58:10.763173
1411 09:58:10.766395 CA PerBit enable=1, Macro0, CA PI delay=34
1412 09:58:10.766479
1413 09:58:10.769933 [CBTSetCACLKResult] CA Dly = 34
1414 09:58:10.770042 CS Dly: 4 (0~35)
1415 09:58:10.772923 ==
1416 09:58:10.773005 Dram Type= 6, Freq= 0, CH_1, rank 1
1417 09:58:10.779805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1418 09:58:10.779892 ==
1419 09:58:10.783072 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1420 09:58:10.789749 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1421 09:58:10.799303 [CA 0] Center 36 (6~67) winsize 62
1422 09:58:10.802928 [CA 1] Center 36 (6~67) winsize 62
1423 09:58:10.806630 [CA 2] Center 34 (4~65) winsize 62
1424 09:58:10.809504 [CA 3] Center 34 (3~65) winsize 63
1425 09:58:10.812591 [CA 4] Center 34 (4~65) winsize 62
1426 09:58:10.816431 [CA 5] Center 33 (3~64) winsize 62
1427 09:58:10.816599
1428 09:58:10.819307 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1429 09:58:10.819471
1430 09:58:10.822877 [CATrainingPosCal] consider 2 rank data
1431 09:58:10.826172 u2DelayCellTimex100 = 270/100 ps
1432 09:58:10.829283 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1433 09:58:10.836029 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1434 09:58:10.839263 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1435 09:58:10.842521 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1436 09:58:10.846206 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1437 09:58:10.849454 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1438 09:58:10.849585
1439 09:58:10.852920 CA PerBit enable=1, Macro0, CA PI delay=33
1440 09:58:10.853036
1441 09:58:10.855834 [CBTSetCACLKResult] CA Dly = 33
1442 09:58:10.855953 CS Dly: 5 (0~38)
1443 09:58:10.859075
1444 09:58:10.862629 ----->DramcWriteLeveling(PI) begin...
1445 09:58:10.862771 ==
1446 09:58:10.865655 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 09:58:10.869319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 09:58:10.869479 ==
1449 09:58:10.872318 Write leveling (Byte 0): 26 => 26
1450 09:58:10.876009 Write leveling (Byte 1): 27 => 27
1451 09:58:10.879100 DramcWriteLeveling(PI) end<-----
1452 09:58:10.879238
1453 09:58:10.879382 ==
1454 09:58:10.882745 Dram Type= 6, Freq= 0, CH_1, rank 0
1455 09:58:10.885658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1456 09:58:10.885806 ==
1457 09:58:10.889225 [Gating] SW mode calibration
1458 09:58:10.895511 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1459 09:58:10.902307 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1460 09:58:10.905831 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1461 09:58:10.909195 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1462 09:58:10.915848 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 09:58:10.919007 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 09:58:10.922592 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 09:58:10.929188 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 09:58:10.932510 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 09:58:10.935298 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 09:58:10.939163 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 09:58:10.945606 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 09:58:10.948647 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 09:58:10.952281 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 09:58:10.958689 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 09:58:10.962005 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 09:58:10.965729 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 09:58:10.971923 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 09:58:10.975691 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1477 09:58:10.978813 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1478 09:58:10.985219 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1479 09:58:10.989004 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 09:58:10.991994 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 09:58:10.998957 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 09:58:11.002208 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 09:58:11.005326 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 09:58:11.011953 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 09:58:11.014967 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1486 09:58:11.018297 0 9 8 | B1->B0 | 2d2d 3333 | 1 0 | (1 1) (0 0)
1487 09:58:11.024933 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1488 09:58:11.028474 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1489 09:58:11.031926 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1490 09:58:11.038041 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1491 09:58:11.041336 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1492 09:58:11.044703 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1493 09:58:11.051347 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (0 0) (0 1)
1494 09:58:11.054836 0 10 8 | B1->B0 | 2727 2727 | 0 0 | (0 0) (0 0)
1495 09:58:11.057899 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 09:58:11.064945 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 09:58:11.068225 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 09:58:11.071695 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 09:58:11.078298 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 09:58:11.081552 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 09:58:11.084500 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1502 09:58:11.091069 0 11 8 | B1->B0 | 3939 3f3f | 0 0 | (0 0) (1 1)
1503 09:58:11.094689 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 09:58:11.097812 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 09:58:11.104546 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1506 09:58:11.108015 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 09:58:11.111353 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1508 09:58:11.114527 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1509 09:58:11.121205 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1510 09:58:11.124729 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1511 09:58:11.127790 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 09:58:11.134438 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 09:58:11.138121 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 09:58:11.141128 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 09:58:11.147793 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 09:58:11.150964 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 09:58:11.154647 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 09:58:11.161316 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 09:58:11.164357 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 09:58:11.167744 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 09:58:11.174310 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 09:58:11.177484 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 09:58:11.181022 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 09:58:11.187741 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 09:58:11.191198 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1526 09:58:11.194291 Total UI for P1: 0, mck2ui 16
1527 09:58:11.198183 best dqsien dly found for B0: ( 0, 14, 2)
1528 09:58:11.201204 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1529 09:58:11.204822 Total UI for P1: 0, mck2ui 16
1530 09:58:11.207941 best dqsien dly found for B1: ( 0, 14, 4)
1531 09:58:11.211423 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1532 09:58:11.214433 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1533 09:58:11.214517
1534 09:58:11.218028 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1535 09:58:11.224500 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1536 09:58:11.224583 [Gating] SW calibration Done
1537 09:58:11.224650 ==
1538 09:58:11.227909 Dram Type= 6, Freq= 0, CH_1, rank 0
1539 09:58:11.234664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1540 09:58:11.234780 ==
1541 09:58:11.234876 RX Vref Scan: 0
1542 09:58:11.234971
1543 09:58:11.237691 RX Vref 0 -> 0, step: 1
1544 09:58:11.237766
1545 09:58:11.240724 RX Delay -130 -> 252, step: 16
1546 09:58:11.244363 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1547 09:58:11.247491 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1548 09:58:11.250883 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1549 09:58:11.257744 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1550 09:58:11.260812 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1551 09:58:11.264364 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1552 09:58:11.267263 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1553 09:58:11.270907 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1554 09:58:11.277151 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1555 09:58:11.280507 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1556 09:58:11.283929 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1557 09:58:11.287252 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1558 09:58:11.293969 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1559 09:58:11.296896 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1560 09:58:11.300679 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1561 09:58:11.303758 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1562 09:58:11.303835 ==
1563 09:58:11.306778 Dram Type= 6, Freq= 0, CH_1, rank 0
1564 09:58:11.313378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1565 09:58:11.313498 ==
1566 09:58:11.313564 DQS Delay:
1567 09:58:11.313623 DQS0 = 0, DQS1 = 0
1568 09:58:11.317079 DQM Delay:
1569 09:58:11.317146 DQM0 = 89, DQM1 = 79
1570 09:58:11.320139 DQ Delay:
1571 09:58:11.323591 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1572 09:58:11.326758 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1573 09:58:11.330326 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1574 09:58:11.333259 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =93
1575 09:58:11.333371
1576 09:58:11.333489
1577 09:58:11.333549 ==
1578 09:58:11.336999 Dram Type= 6, Freq= 0, CH_1, rank 0
1579 09:58:11.340010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1580 09:58:11.340091 ==
1581 09:58:11.340155
1582 09:58:11.340214
1583 09:58:11.343262 TX Vref Scan disable
1584 09:58:11.343343 == TX Byte 0 ==
1585 09:58:11.349839 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1586 09:58:11.353355 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1587 09:58:11.353490 == TX Byte 1 ==
1588 09:58:11.359999 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1589 09:58:11.363571 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1590 09:58:11.363683 ==
1591 09:58:11.366508 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 09:58:11.369984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 09:58:11.370088 ==
1594 09:58:11.384203 TX Vref=22, minBit 15, minWin=26, winSum=439
1595 09:58:11.387518 TX Vref=24, minBit 1, minWin=27, winSum=447
1596 09:58:11.391138 TX Vref=26, minBit 1, minWin=27, winSum=448
1597 09:58:11.394219 TX Vref=28, minBit 15, minWin=27, winSum=450
1598 09:58:11.397626 TX Vref=30, minBit 15, minWin=27, winSum=452
1599 09:58:11.404193 TX Vref=32, minBit 9, minWin=27, winSum=448
1600 09:58:11.407426 [TxChooseVref] Worse bit 15, Min win 27, Win sum 452, Final Vref 30
1601 09:58:11.407511
1602 09:58:11.410928 Final TX Range 1 Vref 30
1603 09:58:11.411019
1604 09:58:11.411104 ==
1605 09:58:11.414044 Dram Type= 6, Freq= 0, CH_1, rank 0
1606 09:58:11.417705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1607 09:58:11.420723 ==
1608 09:58:11.420819
1609 09:58:11.420902
1610 09:58:11.420982 TX Vref Scan disable
1611 09:58:11.424352 == TX Byte 0 ==
1612 09:58:11.427544 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1613 09:58:11.434099 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1614 09:58:11.434183 == TX Byte 1 ==
1615 09:58:11.437603 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1616 09:58:11.444404 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1617 09:58:11.444508
1618 09:58:11.444593 [DATLAT]
1619 09:58:11.444674 Freq=800, CH1 RK0
1620 09:58:11.444754
1621 09:58:11.447739 DATLAT Default: 0xa
1622 09:58:11.447825 0, 0xFFFF, sum = 0
1623 09:58:11.450528 1, 0xFFFF, sum = 0
1624 09:58:11.450628 2, 0xFFFF, sum = 0
1625 09:58:11.454296 3, 0xFFFF, sum = 0
1626 09:58:11.457421 4, 0xFFFF, sum = 0
1627 09:58:11.457508 5, 0xFFFF, sum = 0
1628 09:58:11.460447 6, 0xFFFF, sum = 0
1629 09:58:11.460530 7, 0xFFFF, sum = 0
1630 09:58:11.464327 8, 0xFFFF, sum = 0
1631 09:58:11.464409 9, 0x0, sum = 1
1632 09:58:11.467203 10, 0x0, sum = 2
1633 09:58:11.467314 11, 0x0, sum = 3
1634 09:58:11.467394 12, 0x0, sum = 4
1635 09:58:11.470744 best_step = 10
1636 09:58:11.470817
1637 09:58:11.470878 ==
1638 09:58:11.473741 Dram Type= 6, Freq= 0, CH_1, rank 0
1639 09:58:11.477357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1640 09:58:11.477458 ==
1641 09:58:11.480422 RX Vref Scan: 1
1642 09:58:11.480494
1643 09:58:11.484034 Set Vref Range= 32 -> 127
1644 09:58:11.484114
1645 09:58:11.484182 RX Vref 32 -> 127, step: 1
1646 09:58:11.484242
1647 09:58:11.487008 RX Delay -95 -> 252, step: 8
1648 09:58:11.487084
1649 09:58:11.490334 Set Vref, RX VrefLevel [Byte0]: 32
1650 09:58:11.493578 [Byte1]: 32
1651 09:58:11.497060
1652 09:58:11.497176 Set Vref, RX VrefLevel [Byte0]: 33
1653 09:58:11.500469 [Byte1]: 33
1654 09:58:11.504464
1655 09:58:11.504554 Set Vref, RX VrefLevel [Byte0]: 34
1656 09:58:11.507632 [Byte1]: 34
1657 09:58:11.512426
1658 09:58:11.512513 Set Vref, RX VrefLevel [Byte0]: 35
1659 09:58:11.515325 [Byte1]: 35
1660 09:58:11.519604
1661 09:58:11.519685 Set Vref, RX VrefLevel [Byte0]: 36
1662 09:58:11.522930 [Byte1]: 36
1663 09:58:11.527053
1664 09:58:11.527138 Set Vref, RX VrefLevel [Byte0]: 37
1665 09:58:11.530710 [Byte1]: 37
1666 09:58:11.534987
1667 09:58:11.535069 Set Vref, RX VrefLevel [Byte0]: 38
1668 09:58:11.538022 [Byte1]: 38
1669 09:58:11.542494
1670 09:58:11.542569 Set Vref, RX VrefLevel [Byte0]: 39
1671 09:58:11.546047 [Byte1]: 39
1672 09:58:11.549926
1673 09:58:11.550001 Set Vref, RX VrefLevel [Byte0]: 40
1674 09:58:11.553706 [Byte1]: 40
1675 09:58:11.557691
1676 09:58:11.557765 Set Vref, RX VrefLevel [Byte0]: 41
1677 09:58:11.561310 [Byte1]: 41
1678 09:58:11.565336
1679 09:58:11.565429 Set Vref, RX VrefLevel [Byte0]: 42
1680 09:58:11.568667 [Byte1]: 42
1681 09:58:11.572971
1682 09:58:11.573060 Set Vref, RX VrefLevel [Byte0]: 43
1683 09:58:11.576329 [Byte1]: 43
1684 09:58:11.580332
1685 09:58:11.580414 Set Vref, RX VrefLevel [Byte0]: 44
1686 09:58:11.583736 [Byte1]: 44
1687 09:58:11.588085
1688 09:58:11.588168 Set Vref, RX VrefLevel [Byte0]: 45
1689 09:58:11.591217 [Byte1]: 45
1690 09:58:11.595821
1691 09:58:11.595902 Set Vref, RX VrefLevel [Byte0]: 46
1692 09:58:11.599061 [Byte1]: 46
1693 09:58:11.603286
1694 09:58:11.603365 Set Vref, RX VrefLevel [Byte0]: 47
1695 09:58:11.606926 [Byte1]: 47
1696 09:58:11.610761
1697 09:58:11.610853 Set Vref, RX VrefLevel [Byte0]: 48
1698 09:58:11.614349 [Byte1]: 48
1699 09:58:11.618713
1700 09:58:11.618793 Set Vref, RX VrefLevel [Byte0]: 49
1701 09:58:11.621759 [Byte1]: 49
1702 09:58:11.626020
1703 09:58:11.626105 Set Vref, RX VrefLevel [Byte0]: 50
1704 09:58:11.629719 [Byte1]: 50
1705 09:58:11.633986
1706 09:58:11.634064 Set Vref, RX VrefLevel [Byte0]: 51
1707 09:58:11.637170 [Byte1]: 51
1708 09:58:11.641394
1709 09:58:11.641476 Set Vref, RX VrefLevel [Byte0]: 52
1710 09:58:11.644546 [Byte1]: 52
1711 09:58:11.648728
1712 09:58:11.648808 Set Vref, RX VrefLevel [Byte0]: 53
1713 09:58:11.652391 [Byte1]: 53
1714 09:58:11.656464
1715 09:58:11.656542 Set Vref, RX VrefLevel [Byte0]: 54
1716 09:58:11.660302 [Byte1]: 54
1717 09:58:11.664446
1718 09:58:11.664521 Set Vref, RX VrefLevel [Byte0]: 55
1719 09:58:11.667591 [Byte1]: 55
1720 09:58:11.671928
1721 09:58:11.672025 Set Vref, RX VrefLevel [Byte0]: 56
1722 09:58:11.674952 [Byte1]: 56
1723 09:58:11.679218
1724 09:58:11.679308 Set Vref, RX VrefLevel [Byte0]: 57
1725 09:58:11.682723 [Byte1]: 57
1726 09:58:11.686701
1727 09:58:11.686781 Set Vref, RX VrefLevel [Byte0]: 58
1728 09:58:11.690299 [Byte1]: 58
1729 09:58:11.694546
1730 09:58:11.694661 Set Vref, RX VrefLevel [Byte0]: 59
1731 09:58:11.698001 [Byte1]: 59
1732 09:58:11.702431
1733 09:58:11.702545 Set Vref, RX VrefLevel [Byte0]: 60
1734 09:58:11.705509 [Byte1]: 60
1735 09:58:11.709699
1736 09:58:11.709827 Set Vref, RX VrefLevel [Byte0]: 61
1737 09:58:11.713058 [Byte1]: 61
1738 09:58:11.717242
1739 09:58:11.717354 Set Vref, RX VrefLevel [Byte0]: 62
1740 09:58:11.720734 [Byte1]: 62
1741 09:58:11.725325
1742 09:58:11.725439 Set Vref, RX VrefLevel [Byte0]: 63
1743 09:58:11.728170 [Byte1]: 63
1744 09:58:11.732471
1745 09:58:11.732580 Set Vref, RX VrefLevel [Byte0]: 64
1746 09:58:11.735532 [Byte1]: 64
1747 09:58:11.740325
1748 09:58:11.740436 Set Vref, RX VrefLevel [Byte0]: 65
1749 09:58:11.743371 [Byte1]: 65
1750 09:58:11.747505
1751 09:58:11.747611 Set Vref, RX VrefLevel [Byte0]: 66
1752 09:58:11.751310 [Byte1]: 66
1753 09:58:11.755383
1754 09:58:11.755493 Set Vref, RX VrefLevel [Byte0]: 67
1755 09:58:11.758527 [Byte1]: 67
1756 09:58:11.763071
1757 09:58:11.763180 Set Vref, RX VrefLevel [Byte0]: 68
1758 09:58:11.766041 [Byte1]: 68
1759 09:58:11.770551
1760 09:58:11.770673 Set Vref, RX VrefLevel [Byte0]: 69
1761 09:58:11.773656 [Byte1]: 69
1762 09:58:11.777815
1763 09:58:11.777925 Set Vref, RX VrefLevel [Byte0]: 70
1764 09:58:11.781594 [Byte1]: 70
1765 09:58:11.785501
1766 09:58:11.785588 Set Vref, RX VrefLevel [Byte0]: 71
1767 09:58:11.789073 [Byte1]: 71
1768 09:58:11.793433
1769 09:58:11.793543 Set Vref, RX VrefLevel [Byte0]: 72
1770 09:58:11.796836 [Byte1]: 72
1771 09:58:11.800939
1772 09:58:11.801021 Set Vref, RX VrefLevel [Byte0]: 73
1773 09:58:11.804006 [Byte1]: 73
1774 09:58:11.808329
1775 09:58:11.808433 Set Vref, RX VrefLevel [Byte0]: 74
1776 09:58:11.811868 [Byte1]: 74
1777 09:58:11.815739
1778 09:58:11.815834 Set Vref, RX VrefLevel [Byte0]: 75
1779 09:58:11.819055 [Byte1]: 75
1780 09:58:11.823523
1781 09:58:11.823616 Set Vref, RX VrefLevel [Byte0]: 76
1782 09:58:11.826877 [Byte1]: 76
1783 09:58:11.831537
1784 09:58:11.831654 Set Vref, RX VrefLevel [Byte0]: 77
1785 09:58:11.834644 [Byte1]: 77
1786 09:58:11.838813
1787 09:58:11.838895 Set Vref, RX VrefLevel [Byte0]: 78
1788 09:58:11.841953 [Byte1]: 78
1789 09:58:11.846238
1790 09:58:11.846319 Final RX Vref Byte 0 = 55 to rank0
1791 09:58:11.849967 Final RX Vref Byte 1 = 66 to rank0
1792 09:58:11.852927 Final RX Vref Byte 0 = 55 to rank1
1793 09:58:11.856646 Final RX Vref Byte 1 = 66 to rank1==
1794 09:58:11.859818 Dram Type= 6, Freq= 0, CH_1, rank 0
1795 09:58:11.866204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1796 09:58:11.866308 ==
1797 09:58:11.866375 DQS Delay:
1798 09:58:11.866437 DQS0 = 0, DQS1 = 0
1799 09:58:11.869690 DQM Delay:
1800 09:58:11.869774 DQM0 = 86, DQM1 = 78
1801 09:58:11.872657 DQ Delay:
1802 09:58:11.876425 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1803 09:58:11.879285 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =80
1804 09:58:11.883146 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1805 09:58:11.886180 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
1806 09:58:11.886259
1807 09:58:11.886324
1808 09:58:11.892625 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f1b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1809 09:58:11.896493 CH1 RK0: MR19=606, MR18=2F1B
1810 09:58:11.903055 CH1_RK0: MR19=0x606, MR18=0x2F1B, DQSOSC=397, MR23=63, INC=93, DEC=62
1811 09:58:11.903167
1812 09:58:11.906037 ----->DramcWriteLeveling(PI) begin...
1813 09:58:11.906145 ==
1814 09:58:11.909560 Dram Type= 6, Freq= 0, CH_1, rank 1
1815 09:58:11.912449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1816 09:58:11.912554 ==
1817 09:58:11.915826 Write leveling (Byte 0): 25 => 25
1818 09:58:11.919161 Write leveling (Byte 1): 27 => 27
1819 09:58:11.922770 DramcWriteLeveling(PI) end<-----
1820 09:58:11.922888
1821 09:58:11.922983 ==
1822 09:58:11.926415 Dram Type= 6, Freq= 0, CH_1, rank 1
1823 09:58:11.930096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1824 09:58:11.930175 ==
1825 09:58:11.932892 [Gating] SW mode calibration
1826 09:58:11.939123 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1827 09:58:11.946282 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1828 09:58:11.949416 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1829 09:58:11.952405 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1830 09:58:11.959077 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1831 09:58:11.962918 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 09:58:11.965749 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 09:58:11.972210 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 09:58:11.975882 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 09:58:11.978976 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 09:58:11.985712 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 09:58:11.989385 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 09:58:11.992374 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 09:58:11.998791 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 09:58:12.002658 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 09:58:12.005894 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 09:58:12.012373 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 09:58:12.015583 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 09:58:12.019034 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1845 09:58:12.025629 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1846 09:58:12.028985 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 09:58:12.032306 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 09:58:12.038649 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 09:58:12.042225 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 09:58:12.045521 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 09:58:12.051996 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 09:58:12.055816 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 09:58:12.058678 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 09:58:12.065385 0 9 8 | B1->B0 | 3333 2929 | 0 1 | (0 0) (1 1)
1855 09:58:12.068968 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1856 09:58:12.071979 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1857 09:58:12.078458 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1858 09:58:12.082055 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1859 09:58:12.085239 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1860 09:58:12.092007 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1861 09:58:12.095221 0 10 4 | B1->B0 | 3030 3434 | 0 1 | (0 1) (1 0)
1862 09:58:12.098741 0 10 8 | B1->B0 | 2727 2e2e | 0 0 | (0 0) (0 0)
1863 09:58:12.105481 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 09:58:12.108511 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 09:58:12.112061 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 09:58:12.115012 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 09:58:12.121916 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 09:58:12.125314 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 09:58:12.128448 0 11 4 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
1870 09:58:12.135124 0 11 8 | B1->B0 | 4342 3939 | 1 0 | (0 0) (0 0)
1871 09:58:12.138158 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1872 09:58:12.141601 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1873 09:58:12.148287 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1874 09:58:12.152074 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1875 09:58:12.154875 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1876 09:58:12.161705 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1877 09:58:12.164795 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1878 09:58:12.168255 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1879 09:58:12.175379 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 09:58:12.178348 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 09:58:12.182000 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 09:58:12.188384 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 09:58:12.191851 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 09:58:12.195173 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 09:58:12.201628 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 09:58:12.205293 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 09:58:12.208286 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 09:58:12.214877 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 09:58:12.218701 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 09:58:12.221714 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 09:58:12.228227 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 09:58:12.231876 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1893 09:58:12.234994 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1894 09:58:12.238125 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1895 09:58:12.241694 Total UI for P1: 0, mck2ui 16
1896 09:58:12.244836 best dqsien dly found for B1: ( 0, 14, 4)
1897 09:58:12.251818 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1898 09:58:12.255126 Total UI for P1: 0, mck2ui 16
1899 09:58:12.258190 best dqsien dly found for B0: ( 0, 14, 8)
1900 09:58:12.261220 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1901 09:58:12.264957 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1902 09:58:12.265058
1903 09:58:12.267953 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1904 09:58:12.271320 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1905 09:58:12.274475 [Gating] SW calibration Done
1906 09:58:12.274555 ==
1907 09:58:12.277787 Dram Type= 6, Freq= 0, CH_1, rank 1
1908 09:58:12.281237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1909 09:58:12.281352 ==
1910 09:58:12.284778 RX Vref Scan: 0
1911 09:58:12.284856
1912 09:58:12.284918 RX Vref 0 -> 0, step: 1
1913 09:58:12.287641
1914 09:58:12.287717 RX Delay -130 -> 252, step: 16
1915 09:58:12.294710 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1916 09:58:12.298157 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1917 09:58:12.301271 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1918 09:58:12.304218 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1919 09:58:12.307875 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1920 09:58:12.314582 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1921 09:58:12.317622 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1922 09:58:12.321220 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1923 09:58:12.324196 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1924 09:58:12.327471 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1925 09:58:12.333990 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1926 09:58:12.337623 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1927 09:58:12.341317 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1928 09:58:12.344191 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1929 09:58:12.350809 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1930 09:58:12.354005 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1931 09:58:12.354088 ==
1932 09:58:12.357267 Dram Type= 6, Freq= 0, CH_1, rank 1
1933 09:58:12.360442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1934 09:58:12.360551 ==
1935 09:58:12.364188 DQS Delay:
1936 09:58:12.364300 DQS0 = 0, DQS1 = 0
1937 09:58:12.364405 DQM Delay:
1938 09:58:12.367172 DQM0 = 86, DQM1 = 78
1939 09:58:12.367258 DQ Delay:
1940 09:58:12.370646 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1941 09:58:12.373629 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1942 09:58:12.377260 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1943 09:58:12.380788 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1944 09:58:12.380880
1945 09:58:12.380946
1946 09:58:12.381007 ==
1947 09:58:12.384120 Dram Type= 6, Freq= 0, CH_1, rank 1
1948 09:58:12.390340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1949 09:58:12.390428 ==
1950 09:58:12.390502
1951 09:58:12.390571
1952 09:58:12.390632 TX Vref Scan disable
1953 09:58:12.394224 == TX Byte 0 ==
1954 09:58:12.397141 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1955 09:58:12.403745 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1956 09:58:12.403835 == TX Byte 1 ==
1957 09:58:12.406891 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1958 09:58:12.413703 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1959 09:58:12.413787 ==
1960 09:58:12.416829 Dram Type= 6, Freq= 0, CH_1, rank 1
1961 09:58:12.420592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1962 09:58:12.420681 ==
1963 09:58:12.433148 TX Vref=22, minBit 1, minWin=27, winSum=442
1964 09:58:12.436671 TX Vref=24, minBit 1, minWin=27, winSum=440
1965 09:58:12.439735 TX Vref=26, minBit 3, minWin=27, winSum=449
1966 09:58:12.442786 TX Vref=28, minBit 8, minWin=27, winSum=448
1967 09:58:12.446444 TX Vref=30, minBit 1, minWin=27, winSum=445
1968 09:58:12.453310 TX Vref=32, minBit 2, minWin=27, winSum=446
1969 09:58:12.456177 [TxChooseVref] Worse bit 3, Min win 27, Win sum 449, Final Vref 26
1970 09:58:12.456260
1971 09:58:12.459755 Final TX Range 1 Vref 26
1972 09:58:12.459833
1973 09:58:12.459903 ==
1974 09:58:12.462819 Dram Type= 6, Freq= 0, CH_1, rank 1
1975 09:58:12.466439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1976 09:58:12.466520 ==
1977 09:58:12.469290
1978 09:58:12.469428
1979 09:58:12.469525 TX Vref Scan disable
1980 09:58:12.472998 == TX Byte 0 ==
1981 09:58:12.476602 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1982 09:58:12.479621 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1983 09:58:12.483240 == TX Byte 1 ==
1984 09:58:12.486247 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1985 09:58:12.492963 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1986 09:58:12.493090
1987 09:58:12.493188 [DATLAT]
1988 09:58:12.493278 Freq=800, CH1 RK1
1989 09:58:12.493374
1990 09:58:12.496358 DATLAT Default: 0xa
1991 09:58:12.496473 0, 0xFFFF, sum = 0
1992 09:58:12.499343 1, 0xFFFF, sum = 0
1993 09:58:12.499452 2, 0xFFFF, sum = 0
1994 09:58:12.502829 3, 0xFFFF, sum = 0
1995 09:58:12.506078 4, 0xFFFF, sum = 0
1996 09:58:12.506188 5, 0xFFFF, sum = 0
1997 09:58:12.509492 6, 0xFFFF, sum = 0
1998 09:58:12.509600 7, 0xFFFF, sum = 0
1999 09:58:12.512510 8, 0xFFFF, sum = 0
2000 09:58:12.512619 9, 0x0, sum = 1
2001 09:58:12.516137 10, 0x0, sum = 2
2002 09:58:12.516245 11, 0x0, sum = 3
2003 09:58:12.516349 12, 0x0, sum = 4
2004 09:58:12.519591 best_step = 10
2005 09:58:12.519699
2006 09:58:12.519791 ==
2007 09:58:12.522584 Dram Type= 6, Freq= 0, CH_1, rank 1
2008 09:58:12.526332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2009 09:58:12.526444 ==
2010 09:58:12.529321 RX Vref Scan: 0
2011 09:58:12.529434
2012 09:58:12.529530 RX Vref 0 -> 0, step: 1
2013 09:58:12.532398
2014 09:58:12.532512 RX Delay -95 -> 252, step: 8
2015 09:58:12.539581 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2016 09:58:12.543038 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2017 09:58:12.546682 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2018 09:58:12.549783 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2019 09:58:12.553303 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2020 09:58:12.559606 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2021 09:58:12.563265 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2022 09:58:12.566279 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2023 09:58:12.569734 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2024 09:58:12.572815 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2025 09:58:12.580117 iDelay=217, Bit 10, Center 84 (-31 ~ 200) 232
2026 09:58:12.583139 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2027 09:58:12.586089 iDelay=217, Bit 12, Center 88 (-23 ~ 200) 224
2028 09:58:12.589722 iDelay=217, Bit 13, Center 88 (-23 ~ 200) 224
2029 09:58:12.596359 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2030 09:58:12.599553 iDelay=217, Bit 15, Center 92 (-23 ~ 208) 232
2031 09:58:12.599644 ==
2032 09:58:12.602555 Dram Type= 6, Freq= 0, CH_1, rank 1
2033 09:58:12.606208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2034 09:58:12.606290 ==
2035 09:58:12.606364 DQS Delay:
2036 09:58:12.609837 DQS0 = 0, DQS1 = 0
2037 09:58:12.609955 DQM Delay:
2038 09:58:12.613098 DQM0 = 87, DQM1 = 80
2039 09:58:12.613214 DQ Delay:
2040 09:58:12.616212 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2041 09:58:12.619215 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2042 09:58:12.622611 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68
2043 09:58:12.626254 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =92
2044 09:58:12.626375
2045 09:58:12.626489
2046 09:58:12.636067 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c15, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
2047 09:58:12.636191 CH1 RK1: MR19=606, MR18=1C15
2048 09:58:12.642618 CH1_RK1: MR19=0x606, MR18=0x1C15, DQSOSC=402, MR23=63, INC=91, DEC=60
2049 09:58:12.646231 [RxdqsGatingPostProcess] freq 800
2050 09:58:12.652890 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2051 09:58:12.655930 Pre-setting of DQS Precalculation
2052 09:58:12.659568 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2053 09:58:12.665675 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2054 09:58:12.675902 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2055 09:58:12.676016
2056 09:58:12.676087
2057 09:58:12.679029 [Calibration Summary] 1600 Mbps
2058 09:58:12.679114 CH 0, Rank 0
2059 09:58:12.682669 SW Impedance : PASS
2060 09:58:12.682795 DUTY Scan : NO K
2061 09:58:12.685722 ZQ Calibration : PASS
2062 09:58:12.689159 Jitter Meter : NO K
2063 09:58:12.689281 CBT Training : PASS
2064 09:58:12.692675 Write leveling : PASS
2065 09:58:12.695101 RX DQS gating : PASS
2066 09:58:12.695232 RX DQ/DQS(RDDQC) : PASS
2067 09:58:12.698463 TX DQ/DQS : PASS
2068 09:58:12.701994 RX DATLAT : PASS
2069 09:58:12.702119 RX DQ/DQS(Engine): PASS
2070 09:58:12.705059 TX OE : NO K
2071 09:58:12.705182 All Pass.
2072 09:58:12.705290
2073 09:58:12.708757 CH 0, Rank 1
2074 09:58:12.708841 SW Impedance : PASS
2075 09:58:12.711796 DUTY Scan : NO K
2076 09:58:12.714772 ZQ Calibration : PASS
2077 09:58:12.714901 Jitter Meter : NO K
2078 09:58:12.718462 CBT Training : PASS
2079 09:58:12.718587 Write leveling : PASS
2080 09:58:12.721487 RX DQS gating : PASS
2081 09:58:12.724913 RX DQ/DQS(RDDQC) : PASS
2082 09:58:12.725026 TX DQ/DQS : PASS
2083 09:58:12.728544 RX DATLAT : PASS
2084 09:58:12.731594 RX DQ/DQS(Engine): PASS
2085 09:58:12.731678 TX OE : NO K
2086 09:58:12.734815 All Pass.
2087 09:58:12.734897
2088 09:58:12.734971 CH 1, Rank 0
2089 09:58:12.737860 SW Impedance : PASS
2090 09:58:12.737942 DUTY Scan : NO K
2091 09:58:12.741449 ZQ Calibration : PASS
2092 09:58:12.744540 Jitter Meter : NO K
2093 09:58:12.744618 CBT Training : PASS
2094 09:58:12.748057 Write leveling : PASS
2095 09:58:12.751792 RX DQS gating : PASS
2096 09:58:12.751872 RX DQ/DQS(RDDQC) : PASS
2097 09:58:12.754789 TX DQ/DQS : PASS
2098 09:58:12.758304 RX DATLAT : PASS
2099 09:58:12.758414 RX DQ/DQS(Engine): PASS
2100 09:58:12.761326 TX OE : NO K
2101 09:58:12.761438 All Pass.
2102 09:58:12.761539
2103 09:58:12.764547 CH 1, Rank 1
2104 09:58:12.764625 SW Impedance : PASS
2105 09:58:12.767427 DUTY Scan : NO K
2106 09:58:12.770963 ZQ Calibration : PASS
2107 09:58:12.771064 Jitter Meter : NO K
2108 09:58:12.774534 CBT Training : PASS
2109 09:58:12.777803 Write leveling : PASS
2110 09:58:12.777899 RX DQS gating : PASS
2111 09:58:12.780984 RX DQ/DQS(RDDQC) : PASS
2112 09:58:12.784302 TX DQ/DQS : PASS
2113 09:58:12.784388 RX DATLAT : PASS
2114 09:58:12.787333 RX DQ/DQS(Engine): PASS
2115 09:58:12.787415 TX OE : NO K
2116 09:58:12.791201 All Pass.
2117 09:58:12.791295
2118 09:58:12.791362 DramC Write-DBI off
2119 09:58:12.794039 PER_BANK_REFRESH: Hybrid Mode
2120 09:58:12.797357 TX_TRACKING: ON
2121 09:58:12.800835 [GetDramInforAfterCalByMRR] Vendor 6.
2122 09:58:12.804062 [GetDramInforAfterCalByMRR] Revision 606.
2123 09:58:12.807461 [GetDramInforAfterCalByMRR] Revision 2 0.
2124 09:58:12.807556 MR0 0x3b3b
2125 09:58:12.811010 MR8 0x5151
2126 09:58:12.813999 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2127 09:58:12.814096
2128 09:58:12.814164 MR0 0x3b3b
2129 09:58:12.814226 MR8 0x5151
2130 09:58:12.817424 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2131 09:58:12.817508
2132 09:58:12.827292 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2133 09:58:12.830794 [FAST_K] Save calibration result to emmc
2134 09:58:12.833859 [FAST_K] Save calibration result to emmc
2135 09:58:12.837506 dram_init: config_dvfs: 1
2136 09:58:12.840585 dramc_set_vcore_voltage set vcore to 662500
2137 09:58:12.843887 Read voltage for 1200, 2
2138 09:58:12.843990 Vio18 = 0
2139 09:58:12.847283 Vcore = 662500
2140 09:58:12.847374 Vdram = 0
2141 09:58:12.847441 Vddq = 0
2142 09:58:12.847503 Vmddr = 0
2143 09:58:12.853833 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2144 09:58:12.860708 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2145 09:58:12.860870 MEM_TYPE=3, freq_sel=15
2146 09:58:12.863534 sv_algorithm_assistance_LP4_1600
2147 09:58:12.867374 ============ PULL DRAM RESETB DOWN ============
2148 09:58:12.873573 ========== PULL DRAM RESETB DOWN end =========
2149 09:58:12.876986 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2150 09:58:12.880549 ===================================
2151 09:58:12.883918 LPDDR4 DRAM CONFIGURATION
2152 09:58:12.886778 ===================================
2153 09:58:12.886870 EX_ROW_EN[0] = 0x0
2154 09:58:12.890556 EX_ROW_EN[1] = 0x0
2155 09:58:12.890642 LP4Y_EN = 0x0
2156 09:58:12.893357 WORK_FSP = 0x0
2157 09:58:12.893440 WL = 0x4
2158 09:58:12.897101 RL = 0x4
2159 09:58:12.900002 BL = 0x2
2160 09:58:12.900086 RPST = 0x0
2161 09:58:12.903594 RD_PRE = 0x0
2162 09:58:12.903676 WR_PRE = 0x1
2163 09:58:12.907032 WR_PST = 0x0
2164 09:58:12.907112 DBI_WR = 0x0
2165 09:58:12.910246 DBI_RD = 0x0
2166 09:58:12.910326 OTF = 0x1
2167 09:58:12.913888 ===================================
2168 09:58:12.917165 ===================================
2169 09:58:12.920040 ANA top config
2170 09:58:12.923401 ===================================
2171 09:58:12.923483 DLL_ASYNC_EN = 0
2172 09:58:12.926605 ALL_SLAVE_EN = 0
2173 09:58:12.930390 NEW_RANK_MODE = 1
2174 09:58:12.933308 DLL_IDLE_MODE = 1
2175 09:58:12.936290 LP45_APHY_COMB_EN = 1
2176 09:58:12.936373 TX_ODT_DIS = 1
2177 09:58:12.940142 NEW_8X_MODE = 1
2178 09:58:12.942997 ===================================
2179 09:58:12.946233 ===================================
2180 09:58:12.949372 data_rate = 2400
2181 09:58:12.952898 CKR = 1
2182 09:58:12.956365 DQ_P2S_RATIO = 8
2183 09:58:12.959553 ===================================
2184 09:58:12.962745 CA_P2S_RATIO = 8
2185 09:58:12.962853 DQ_CA_OPEN = 0
2186 09:58:12.965742 DQ_SEMI_OPEN = 0
2187 09:58:12.969183 CA_SEMI_OPEN = 0
2188 09:58:12.972639 CA_FULL_RATE = 0
2189 09:58:12.976031 DQ_CKDIV4_EN = 0
2190 09:58:12.979297 CA_CKDIV4_EN = 0
2191 09:58:12.979386 CA_PREDIV_EN = 0
2192 09:58:12.982601 PH8_DLY = 17
2193 09:58:12.986043 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2194 09:58:12.988894 DQ_AAMCK_DIV = 4
2195 09:58:12.992594 CA_AAMCK_DIV = 4
2196 09:58:12.995673 CA_ADMCK_DIV = 4
2197 09:58:12.995761 DQ_TRACK_CA_EN = 0
2198 09:58:12.999358 CA_PICK = 1200
2199 09:58:13.002304 CA_MCKIO = 1200
2200 09:58:13.005837 MCKIO_SEMI = 0
2201 09:58:13.008852 PLL_FREQ = 2366
2202 09:58:13.012438 DQ_UI_PI_RATIO = 32
2203 09:58:13.015483 CA_UI_PI_RATIO = 0
2204 09:58:13.019034 ===================================
2205 09:58:13.022641 ===================================
2206 09:58:13.022741 memory_type:LPDDR4
2207 09:58:13.025436 GP_NUM : 10
2208 09:58:13.028644 SRAM_EN : 1
2209 09:58:13.028752 MD32_EN : 0
2210 09:58:13.032002 ===================================
2211 09:58:13.035177 [ANA_INIT] >>>>>>>>>>>>>>
2212 09:58:13.038746 <<<<<< [CONFIGURE PHASE]: ANA_TX
2213 09:58:13.041847 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2214 09:58:13.045464 ===================================
2215 09:58:13.048512 data_rate = 2400,PCW = 0X5b00
2216 09:58:13.052376 ===================================
2217 09:58:13.055421 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2218 09:58:13.058344 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2219 09:58:13.065174 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2220 09:58:13.068290 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2221 09:58:13.071850 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2222 09:58:13.078201 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2223 09:58:13.078302 [ANA_INIT] flow start
2224 09:58:13.081726 [ANA_INIT] PLL >>>>>>>>
2225 09:58:13.081817 [ANA_INIT] PLL <<<<<<<<
2226 09:58:13.084801 [ANA_INIT] MIDPI >>>>>>>>
2227 09:58:13.088386 [ANA_INIT] MIDPI <<<<<<<<
2228 09:58:13.091692 [ANA_INIT] DLL >>>>>>>>
2229 09:58:13.091781 [ANA_INIT] DLL <<<<<<<<
2230 09:58:13.095221 [ANA_INIT] flow end
2231 09:58:13.097971 ============ LP4 DIFF to SE enter ============
2232 09:58:13.101258 ============ LP4 DIFF to SE exit ============
2233 09:58:13.105010 [ANA_INIT] <<<<<<<<<<<<<
2234 09:58:13.107956 [Flow] Enable top DCM control >>>>>
2235 09:58:13.111234 [Flow] Enable top DCM control <<<<<
2236 09:58:13.115178 Enable DLL master slave shuffle
2237 09:58:13.121716 ==============================================================
2238 09:58:13.121820 Gating Mode config
2239 09:58:13.128167 ==============================================================
2240 09:58:13.128271 Config description:
2241 09:58:13.138269 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2242 09:58:13.144597 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2243 09:58:13.151451 SELPH_MODE 0: By rank 1: By Phase
2244 09:58:13.154548 ==============================================================
2245 09:58:13.157550 GAT_TRACK_EN = 1
2246 09:58:13.161166 RX_GATING_MODE = 2
2247 09:58:13.164238 RX_GATING_TRACK_MODE = 2
2248 09:58:13.168004 SELPH_MODE = 1
2249 09:58:13.170957 PICG_EARLY_EN = 1
2250 09:58:13.174761 VALID_LAT_VALUE = 1
2251 09:58:13.181265 ==============================================================
2252 09:58:13.184624 Enter into Gating configuration >>>>
2253 09:58:13.187768 Exit from Gating configuration <<<<
2254 09:58:13.187848 Enter into DVFS_PRE_config >>>>>
2255 09:58:13.201121 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2256 09:58:13.204305 Exit from DVFS_PRE_config <<<<<
2257 09:58:13.207717 Enter into PICG configuration >>>>
2258 09:58:13.211025 Exit from PICG configuration <<<<
2259 09:58:13.211105 [RX_INPUT] configuration >>>>>
2260 09:58:13.214255 [RX_INPUT] configuration <<<<<
2261 09:58:13.221246 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2262 09:58:13.224364 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2263 09:58:13.231023 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2264 09:58:13.237694 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2265 09:58:13.244189 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2266 09:58:13.250908 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2267 09:58:13.254608 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2268 09:58:13.257665 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2269 09:58:13.264479 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2270 09:58:13.267542 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2271 09:58:13.270652 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2272 09:58:13.274013 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2273 09:58:13.277340 ===================================
2274 09:58:13.280515 LPDDR4 DRAM CONFIGURATION
2275 09:58:13.284034 ===================================
2276 09:58:13.287571 EX_ROW_EN[0] = 0x0
2277 09:58:13.287647 EX_ROW_EN[1] = 0x0
2278 09:58:13.290505 LP4Y_EN = 0x0
2279 09:58:13.290579 WORK_FSP = 0x0
2280 09:58:13.294311 WL = 0x4
2281 09:58:13.294385 RL = 0x4
2282 09:58:13.297193 BL = 0x2
2283 09:58:13.297294 RPST = 0x0
2284 09:58:13.300908 RD_PRE = 0x0
2285 09:58:13.300985 WR_PRE = 0x1
2286 09:58:13.304106 WR_PST = 0x0
2287 09:58:13.306991 DBI_WR = 0x0
2288 09:58:13.307075 DBI_RD = 0x0
2289 09:58:13.310301 OTF = 0x1
2290 09:58:13.313795 ===================================
2291 09:58:13.317372 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2292 09:58:13.320542 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2293 09:58:13.323731 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2294 09:58:13.327173 ===================================
2295 09:58:13.330855 LPDDR4 DRAM CONFIGURATION
2296 09:58:13.333648 ===================================
2297 09:58:13.337131 EX_ROW_EN[0] = 0x10
2298 09:58:13.337236 EX_ROW_EN[1] = 0x0
2299 09:58:13.340182 LP4Y_EN = 0x0
2300 09:58:13.340290 WORK_FSP = 0x0
2301 09:58:13.343493 WL = 0x4
2302 09:58:13.343591 RL = 0x4
2303 09:58:13.347085 BL = 0x2
2304 09:58:13.347186 RPST = 0x0
2305 09:58:13.350805 RD_PRE = 0x0
2306 09:58:13.350884 WR_PRE = 0x1
2307 09:58:13.353451 WR_PST = 0x0
2308 09:58:13.353534 DBI_WR = 0x0
2309 09:58:13.357081 DBI_RD = 0x0
2310 09:58:13.357163 OTF = 0x1
2311 09:58:13.360441 ===================================
2312 09:58:13.366862 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2313 09:58:13.366953 ==
2314 09:58:13.370549 Dram Type= 6, Freq= 0, CH_0, rank 0
2315 09:58:13.376635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2316 09:58:13.376727 ==
2317 09:58:13.376794 [Duty_Offset_Calibration]
2318 09:58:13.380133 B0:1 B1:-1 CA:0
2319 09:58:13.380218
2320 09:58:13.383307 [DutyScan_Calibration_Flow] k_type=0
2321 09:58:13.392427
2322 09:58:13.392508 ==CLK 0==
2323 09:58:13.395929 Final CLK duty delay cell = 0
2324 09:58:13.399091 [0] MAX Duty = 5125%(X100), DQS PI = 24
2325 09:58:13.402670 [0] MIN Duty = 4907%(X100), DQS PI = 10
2326 09:58:13.406089 [0] AVG Duty = 5016%(X100)
2327 09:58:13.406169
2328 09:58:13.409170 CH0 CLK Duty spec in!! Max-Min= 218%
2329 09:58:13.412939 [DutyScan_Calibration_Flow] ====Done====
2330 09:58:13.413021
2331 09:58:13.415627 [DutyScan_Calibration_Flow] k_type=1
2332 09:58:13.430158
2333 09:58:13.430275 ==DQS 0 ==
2334 09:58:13.433836 Final DQS duty delay cell = -4
2335 09:58:13.437430 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2336 09:58:13.440542 [-4] MIN Duty = 4875%(X100), DQS PI = 56
2337 09:58:13.443487 [-4] AVG Duty = 4968%(X100)
2338 09:58:13.443577
2339 09:58:13.443644 ==DQS 1 ==
2340 09:58:13.447067 Final DQS duty delay cell = -4
2341 09:58:13.450184 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2342 09:58:13.453569 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2343 09:58:13.456789 [-4] AVG Duty = 4938%(X100)
2344 09:58:13.456869
2345 09:58:13.460427 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2346 09:58:13.460512
2347 09:58:13.463301 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2348 09:58:13.467102 [DutyScan_Calibration_Flow] ====Done====
2349 09:58:13.467192
2350 09:58:13.470212 [DutyScan_Calibration_Flow] k_type=3
2351 09:58:13.488268
2352 09:58:13.488378 ==DQM 0 ==
2353 09:58:13.491510 Final DQM duty delay cell = 0
2354 09:58:13.495021 [0] MAX Duty = 5031%(X100), DQS PI = 16
2355 09:58:13.498481 [0] MIN Duty = 4875%(X100), DQS PI = 8
2356 09:58:13.498567 [0] AVG Duty = 4953%(X100)
2357 09:58:13.501655
2358 09:58:13.501744 ==DQM 1 ==
2359 09:58:13.505111 Final DQM duty delay cell = 4
2360 09:58:13.508262 [4] MAX Duty = 5187%(X100), DQS PI = 14
2361 09:58:13.511825 [4] MIN Duty = 5000%(X100), DQS PI = 24
2362 09:58:13.514795 [4] AVG Duty = 5093%(X100)
2363 09:58:13.514877
2364 09:58:13.518480 CH0 DQM 0 Duty spec in!! Max-Min= 156%
2365 09:58:13.518568
2366 09:58:13.521737 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2367 09:58:13.524717 [DutyScan_Calibration_Flow] ====Done====
2368 09:58:13.524794
2369 09:58:13.528051 [DutyScan_Calibration_Flow] k_type=2
2370 09:58:13.543349
2371 09:58:13.543440 ==DQ 0 ==
2372 09:58:13.546958 Final DQ duty delay cell = -4
2373 09:58:13.549895 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2374 09:58:13.553740 [-4] MIN Duty = 4907%(X100), DQS PI = 48
2375 09:58:13.556885 [-4] AVG Duty = 4969%(X100)
2376 09:58:13.556967
2377 09:58:13.557051 ==DQ 1 ==
2378 09:58:13.559614 Final DQ duty delay cell = -4
2379 09:58:13.563498 [-4] MAX Duty = 5000%(X100), DQS PI = 54
2380 09:58:13.566236 [-4] MIN Duty = 4876%(X100), DQS PI = 40
2381 09:58:13.569971 [-4] AVG Duty = 4938%(X100)
2382 09:58:13.570051
2383 09:58:13.573177 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2384 09:58:13.573288
2385 09:58:13.576514 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2386 09:58:13.579545 [DutyScan_Calibration_Flow] ====Done====
2387 09:58:13.579658 ==
2388 09:58:13.582968 Dram Type= 6, Freq= 0, CH_1, rank 0
2389 09:58:13.586253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2390 09:58:13.586360 ==
2391 09:58:13.589458 [Duty_Offset_Calibration]
2392 09:58:13.592998 B0:-1 B1:1 CA:1
2393 09:58:13.593104
2394 09:58:13.595864 [DutyScan_Calibration_Flow] k_type=0
2395 09:58:13.604387
2396 09:58:13.604474 ==CLK 0==
2397 09:58:13.607456 Final CLK duty delay cell = 0
2398 09:58:13.610789 [0] MAX Duty = 5156%(X100), DQS PI = 20
2399 09:58:13.613819 [0] MIN Duty = 4969%(X100), DQS PI = 60
2400 09:58:13.617505 [0] AVG Duty = 5062%(X100)
2401 09:58:13.617579
2402 09:58:13.620714 CH1 CLK Duty spec in!! Max-Min= 187%
2403 09:58:13.623841 [DutyScan_Calibration_Flow] ====Done====
2404 09:58:13.623942
2405 09:58:13.627099 [DutyScan_Calibration_Flow] k_type=1
2406 09:58:13.643212
2407 09:58:13.643329 ==DQS 0 ==
2408 09:58:13.646889 Final DQS duty delay cell = 0
2409 09:58:13.649907 [0] MAX Duty = 5125%(X100), DQS PI = 18
2410 09:58:13.653461 [0] MIN Duty = 4938%(X100), DQS PI = 6
2411 09:58:13.656531 [0] AVG Duty = 5031%(X100)
2412 09:58:13.656614
2413 09:58:13.656679 ==DQS 1 ==
2414 09:58:13.659707 Final DQS duty delay cell = 0
2415 09:58:13.663304 [0] MAX Duty = 5094%(X100), DQS PI = 12
2416 09:58:13.666420 [0] MIN Duty = 4969%(X100), DQS PI = 58
2417 09:58:13.670101 [0] AVG Duty = 5031%(X100)
2418 09:58:13.670191
2419 09:58:13.673301 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2420 09:58:13.673438
2421 09:58:13.676908 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2422 09:58:13.680027 [DutyScan_Calibration_Flow] ====Done====
2423 09:58:13.680144
2424 09:58:13.682801 [DutyScan_Calibration_Flow] k_type=3
2425 09:58:13.699358
2426 09:58:13.699482 ==DQM 0 ==
2427 09:58:13.702361 Final DQM duty delay cell = -4
2428 09:58:13.705468 [-4] MAX Duty = 5062%(X100), DQS PI = 36
2429 09:58:13.709158 [-4] MIN Duty = 4876%(X100), DQS PI = 6
2430 09:58:13.712488 [-4] AVG Duty = 4969%(X100)
2431 09:58:13.712608
2432 09:58:13.712696 ==DQM 1 ==
2433 09:58:13.715870 Final DQM duty delay cell = 0
2434 09:58:13.718696 [0] MAX Duty = 5187%(X100), DQS PI = 6
2435 09:58:13.722089 [0] MIN Duty = 5000%(X100), DQS PI = 28
2436 09:58:13.725946 [0] AVG Duty = 5093%(X100)
2437 09:58:13.726043
2438 09:58:13.728851 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2439 09:58:13.728936
2440 09:58:13.732608 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2441 09:58:13.735357 [DutyScan_Calibration_Flow] ====Done====
2442 09:58:13.735447
2443 09:58:13.738999 [DutyScan_Calibration_Flow] k_type=2
2444 09:58:13.755692
2445 09:58:13.755814 ==DQ 0 ==
2446 09:58:13.759176 Final DQ duty delay cell = 0
2447 09:58:13.762245 [0] MAX Duty = 5187%(X100), DQS PI = 30
2448 09:58:13.766092 [0] MIN Duty = 4907%(X100), DQS PI = 6
2449 09:58:13.766203 [0] AVG Duty = 5047%(X100)
2450 09:58:13.768928
2451 09:58:13.769006 ==DQ 1 ==
2452 09:58:13.772555 Final DQ duty delay cell = 0
2453 09:58:13.775933 [0] MAX Duty = 5124%(X100), DQS PI = 10
2454 09:58:13.778883 [0] MIN Duty = 4969%(X100), DQS PI = 0
2455 09:58:13.778971 [0] AVG Duty = 5046%(X100)
2456 09:58:13.779038
2457 09:58:13.782553 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2458 09:58:13.785655
2459 09:58:13.789100 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2460 09:58:13.792005 [DutyScan_Calibration_Flow] ====Done====
2461 09:58:13.795342 nWR fixed to 30
2462 09:58:13.795427 [ModeRegInit_LP4] CH0 RK0
2463 09:58:13.798573 [ModeRegInit_LP4] CH0 RK1
2464 09:58:13.802146 [ModeRegInit_LP4] CH1 RK0
2465 09:58:13.805297 [ModeRegInit_LP4] CH1 RK1
2466 09:58:13.805400 match AC timing 7
2467 09:58:13.808970 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2468 09:58:13.815295 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2469 09:58:13.819090 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2470 09:58:13.825503 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2471 09:58:13.828551 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2472 09:58:13.828635 ==
2473 09:58:13.831863 Dram Type= 6, Freq= 0, CH_0, rank 0
2474 09:58:13.835355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2475 09:58:13.835438 ==
2476 09:58:13.841860 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2477 09:58:13.848103 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2478 09:58:13.855464 [CA 0] Center 39 (9~70) winsize 62
2479 09:58:13.858952 [CA 1] Center 39 (9~69) winsize 61
2480 09:58:13.862034 [CA 2] Center 35 (5~66) winsize 62
2481 09:58:13.865714 [CA 3] Center 35 (5~66) winsize 62
2482 09:58:13.868567 [CA 4] Center 33 (4~63) winsize 60
2483 09:58:13.872366 [CA 5] Center 33 (3~63) winsize 61
2484 09:58:13.872474
2485 09:58:13.875377 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2486 09:58:13.875464
2487 09:58:13.878569 [CATrainingPosCal] consider 1 rank data
2488 09:58:13.882147 u2DelayCellTimex100 = 270/100 ps
2489 09:58:13.885421 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2490 09:58:13.891998 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2491 09:58:13.895547 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2492 09:58:13.898625 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2493 09:58:13.901973 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2494 09:58:13.905166 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2495 09:58:13.905255
2496 09:58:13.909080 CA PerBit enable=1, Macro0, CA PI delay=33
2497 09:58:13.909166
2498 09:58:13.912103 [CBTSetCACLKResult] CA Dly = 33
2499 09:58:13.912181 CS Dly: 8 (0~39)
2500 09:58:13.915325 ==
2501 09:58:13.915401 Dram Type= 6, Freq= 0, CH_0, rank 1
2502 09:58:13.922410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2503 09:58:13.922529 ==
2504 09:58:13.925315 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2505 09:58:13.932005 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2506 09:58:13.941432 [CA 0] Center 39 (9~70) winsize 62
2507 09:58:13.944875 [CA 1] Center 39 (9~70) winsize 62
2508 09:58:13.947936 [CA 2] Center 35 (5~66) winsize 62
2509 09:58:13.951192 [CA 3] Center 34 (4~65) winsize 62
2510 09:58:13.954553 [CA 4] Center 33 (3~64) winsize 62
2511 09:58:13.957723 [CA 5] Center 33 (3~63) winsize 61
2512 09:58:13.957821
2513 09:58:13.960847 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2514 09:58:13.960969
2515 09:58:13.964404 [CATrainingPosCal] consider 2 rank data
2516 09:58:13.968017 u2DelayCellTimex100 = 270/100 ps
2517 09:58:13.970985 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2518 09:58:13.977840 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2519 09:58:13.980879 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2520 09:58:13.984512 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2521 09:58:13.987578 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2522 09:58:13.991381 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2523 09:58:13.991470
2524 09:58:13.994344 CA PerBit enable=1, Macro0, CA PI delay=33
2525 09:58:13.994417
2526 09:58:13.997968 [CBTSetCACLKResult] CA Dly = 33
2527 09:58:13.998052 CS Dly: 8 (0~40)
2528 09:58:14.000945
2529 09:58:14.004723 ----->DramcWriteLeveling(PI) begin...
2530 09:58:14.004809 ==
2531 09:58:14.007701 Dram Type= 6, Freq= 0, CH_0, rank 0
2532 09:58:14.010716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2533 09:58:14.010803 ==
2534 09:58:14.013909 Write leveling (Byte 0): 32 => 32
2535 09:58:14.017706 Write leveling (Byte 1): 28 => 28
2536 09:58:14.020635 DramcWriteLeveling(PI) end<-----
2537 09:58:14.020722
2538 09:58:14.020814 ==
2539 09:58:14.024140 Dram Type= 6, Freq= 0, CH_0, rank 0
2540 09:58:14.027769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2541 09:58:14.027864 ==
2542 09:58:14.030824 [Gating] SW mode calibration
2543 09:58:14.037355 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2544 09:58:14.043961 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2545 09:58:14.047407 0 15 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
2546 09:58:14.051099 0 15 4 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
2547 09:58:14.057619 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2548 09:58:14.060611 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2549 09:58:14.064124 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2550 09:58:14.070917 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2551 09:58:14.074028 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2552 09:58:14.077497 0 15 28 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
2553 09:58:14.084262 1 0 0 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
2554 09:58:14.087450 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2555 09:58:14.090294 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2556 09:58:14.097345 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2557 09:58:14.100368 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2558 09:58:14.103550 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2559 09:58:14.110197 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2560 09:58:14.113859 1 0 28 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
2561 09:58:14.116833 1 1 0 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
2562 09:58:14.120544 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2563 09:58:14.126735 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2564 09:58:14.130408 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2565 09:58:14.133433 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2566 09:58:14.140076 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2567 09:58:14.143748 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2568 09:58:14.146888 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2569 09:58:14.153841 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2570 09:58:14.156695 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 09:58:14.160227 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 09:58:14.166965 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 09:58:14.169954 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 09:58:14.173849 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 09:58:14.179993 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 09:58:14.183286 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 09:58:14.186962 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 09:58:14.193776 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 09:58:14.196806 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 09:58:14.200386 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2581 09:58:14.207011 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2582 09:58:14.210017 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2583 09:58:14.213221 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2584 09:58:14.220004 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2585 09:58:14.223765 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2586 09:58:14.226795 Total UI for P1: 0, mck2ui 16
2587 09:58:14.230009 best dqsien dly found for B0: ( 1, 3, 28)
2588 09:58:14.233027 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2589 09:58:14.236603 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2590 09:58:14.239972 Total UI for P1: 0, mck2ui 16
2591 09:58:14.243533 best dqsien dly found for B1: ( 1, 4, 0)
2592 09:58:14.246995 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2593 09:58:14.253042 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2594 09:58:14.253153
2595 09:58:14.256431 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2596 09:58:14.259823 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2597 09:58:14.263032 [Gating] SW calibration Done
2598 09:58:14.263110 ==
2599 09:58:14.266620 Dram Type= 6, Freq= 0, CH_0, rank 0
2600 09:58:14.269884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2601 09:58:14.269962 ==
2602 09:58:14.270025 RX Vref Scan: 0
2603 09:58:14.273338
2604 09:58:14.273418 RX Vref 0 -> 0, step: 1
2605 09:58:14.273482
2606 09:58:14.276452 RX Delay -40 -> 252, step: 8
2607 09:58:14.280134 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2608 09:58:14.283319 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2609 09:58:14.289970 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2610 09:58:14.293176 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2611 09:58:14.296504 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2612 09:58:14.300114 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2613 09:58:14.303288 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2614 09:58:14.309482 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2615 09:58:14.312790 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2616 09:58:14.316397 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2617 09:58:14.319473 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2618 09:58:14.323159 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2619 09:58:14.329257 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2620 09:58:14.332926 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2621 09:58:14.336165 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2622 09:58:14.339571 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2623 09:58:14.339676 ==
2624 09:58:14.342730 Dram Type= 6, Freq= 0, CH_0, rank 0
2625 09:58:14.349465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2626 09:58:14.349550 ==
2627 09:58:14.349615 DQS Delay:
2628 09:58:14.352788 DQS0 = 0, DQS1 = 0
2629 09:58:14.352871 DQM Delay:
2630 09:58:14.352936 DQM0 = 119, DQM1 = 106
2631 09:58:14.356240 DQ Delay:
2632 09:58:14.359744 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2633 09:58:14.362686 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2634 09:58:14.366174 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2635 09:58:14.369458 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2636 09:58:14.369544
2637 09:58:14.369632
2638 09:58:14.369715 ==
2639 09:58:14.373009 Dram Type= 6, Freq= 0, CH_0, rank 0
2640 09:58:14.375907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2641 09:58:14.379510 ==
2642 09:58:14.379628
2643 09:58:14.379715
2644 09:58:14.379814 TX Vref Scan disable
2645 09:58:14.382540 == TX Byte 0 ==
2646 09:58:14.386158 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2647 09:58:14.389227 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2648 09:58:14.392785 == TX Byte 1 ==
2649 09:58:14.395834 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2650 09:58:14.398971 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2651 09:58:14.402336 ==
2652 09:58:14.402424 Dram Type= 6, Freq= 0, CH_0, rank 0
2653 09:58:14.409224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2654 09:58:14.409313 ==
2655 09:58:14.420334 TX Vref=22, minBit 13, minWin=24, winSum=415
2656 09:58:14.423717 TX Vref=24, minBit 5, minWin=25, winSum=421
2657 09:58:14.426875 TX Vref=26, minBit 1, minWin=26, winSum=427
2658 09:58:14.430427 TX Vref=28, minBit 8, minWin=26, winSum=430
2659 09:58:14.433581 TX Vref=30, minBit 4, minWin=26, winSum=429
2660 09:58:14.440494 TX Vref=32, minBit 4, minWin=26, winSum=429
2661 09:58:14.443277 [TxChooseVref] Worse bit 8, Min win 26, Win sum 430, Final Vref 28
2662 09:58:14.443367
2663 09:58:14.447039 Final TX Range 1 Vref 28
2664 09:58:14.447127
2665 09:58:14.447216 ==
2666 09:58:14.450415 Dram Type= 6, Freq= 0, CH_0, rank 0
2667 09:58:14.453283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2668 09:58:14.453393 ==
2669 09:58:14.456588
2670 09:58:14.456672
2671 09:58:14.456758 TX Vref Scan disable
2672 09:58:14.459948 == TX Byte 0 ==
2673 09:58:14.463754 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2674 09:58:14.470173 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2675 09:58:14.470263 == TX Byte 1 ==
2676 09:58:14.473901 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2677 09:58:14.479954 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2678 09:58:14.480072
2679 09:58:14.480189 [DATLAT]
2680 09:58:14.480282 Freq=1200, CH0 RK0
2681 09:58:14.480373
2682 09:58:14.483510 DATLAT Default: 0xd
2683 09:58:14.483600 0, 0xFFFF, sum = 0
2684 09:58:14.486802 1, 0xFFFF, sum = 0
2685 09:58:14.489749 2, 0xFFFF, sum = 0
2686 09:58:14.489846 3, 0xFFFF, sum = 0
2687 09:58:14.493461 4, 0xFFFF, sum = 0
2688 09:58:14.493547 5, 0xFFFF, sum = 0
2689 09:58:14.496525 6, 0xFFFF, sum = 0
2690 09:58:14.496610 7, 0xFFFF, sum = 0
2691 09:58:14.500350 8, 0xFFFF, sum = 0
2692 09:58:14.500434 9, 0xFFFF, sum = 0
2693 09:58:14.503481 10, 0xFFFF, sum = 0
2694 09:58:14.503592 11, 0xFFFF, sum = 0
2695 09:58:14.506344 12, 0x0, sum = 1
2696 09:58:14.506441 13, 0x0, sum = 2
2697 09:58:14.510123 14, 0x0, sum = 3
2698 09:58:14.510206 15, 0x0, sum = 4
2699 09:58:14.513205 best_step = 13
2700 09:58:14.513331
2701 09:58:14.513431 ==
2702 09:58:14.516375 Dram Type= 6, Freq= 0, CH_0, rank 0
2703 09:58:14.519866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2704 09:58:14.519945 ==
2705 09:58:14.520053 RX Vref Scan: 1
2706 09:58:14.520144
2707 09:58:14.523234 Set Vref Range= 32 -> 127
2708 09:58:14.523311
2709 09:58:14.526507 RX Vref 32 -> 127, step: 1
2710 09:58:14.526583
2711 09:58:14.529660 RX Delay -21 -> 252, step: 4
2712 09:58:14.529757
2713 09:58:14.532889 Set Vref, RX VrefLevel [Byte0]: 32
2714 09:58:14.535976 [Byte1]: 32
2715 09:58:14.536096
2716 09:58:14.539386 Set Vref, RX VrefLevel [Byte0]: 33
2717 09:58:14.543268 [Byte1]: 33
2718 09:58:14.546951
2719 09:58:14.547039 Set Vref, RX VrefLevel [Byte0]: 34
2720 09:58:14.550004 [Byte1]: 34
2721 09:58:14.555058
2722 09:58:14.555142 Set Vref, RX VrefLevel [Byte0]: 35
2723 09:58:14.557819 [Byte1]: 35
2724 09:58:14.562200
2725 09:58:14.562285 Set Vref, RX VrefLevel [Byte0]: 36
2726 09:58:14.565544 [Byte1]: 36
2727 09:58:14.570443
2728 09:58:14.570529 Set Vref, RX VrefLevel [Byte0]: 37
2729 09:58:14.573582 [Byte1]: 37
2730 09:58:14.578177
2731 09:58:14.578271 Set Vref, RX VrefLevel [Byte0]: 38
2732 09:58:14.581405 [Byte1]: 38
2733 09:58:14.586256
2734 09:58:14.586336 Set Vref, RX VrefLevel [Byte0]: 39
2735 09:58:14.589752 [Byte1]: 39
2736 09:58:14.593987
2737 09:58:14.594068 Set Vref, RX VrefLevel [Byte0]: 40
2738 09:58:14.597595 [Byte1]: 40
2739 09:58:14.601837
2740 09:58:14.601929 Set Vref, RX VrefLevel [Byte0]: 41
2741 09:58:14.605439 [Byte1]: 41
2742 09:58:14.609936
2743 09:58:14.610018 Set Vref, RX VrefLevel [Byte0]: 42
2744 09:58:14.613595 [Byte1]: 42
2745 09:58:14.617735
2746 09:58:14.617820 Set Vref, RX VrefLevel [Byte0]: 43
2747 09:58:14.621377 [Byte1]: 43
2748 09:58:14.625586
2749 09:58:14.625688 Set Vref, RX VrefLevel [Byte0]: 44
2750 09:58:14.629221 [Byte1]: 44
2751 09:58:14.633954
2752 09:58:14.634052 Set Vref, RX VrefLevel [Byte0]: 45
2753 09:58:14.636902 [Byte1]: 45
2754 09:58:14.641664
2755 09:58:14.641748 Set Vref, RX VrefLevel [Byte0]: 46
2756 09:58:14.645041 [Byte1]: 46
2757 09:58:14.649681
2758 09:58:14.649759 Set Vref, RX VrefLevel [Byte0]: 47
2759 09:58:14.652862 [Byte1]: 47
2760 09:58:14.657458
2761 09:58:14.657545 Set Vref, RX VrefLevel [Byte0]: 48
2762 09:58:14.660580 [Byte1]: 48
2763 09:58:14.665504
2764 09:58:14.665623 Set Vref, RX VrefLevel [Byte0]: 49
2765 09:58:14.669074 [Byte1]: 49
2766 09:58:14.673293
2767 09:58:14.673418 Set Vref, RX VrefLevel [Byte0]: 50
2768 09:58:14.679674 [Byte1]: 50
2769 09:58:14.679764
2770 09:58:14.683508 Set Vref, RX VrefLevel [Byte0]: 51
2771 09:58:14.686495 [Byte1]: 51
2772 09:58:14.686577
2773 09:58:14.689782 Set Vref, RX VrefLevel [Byte0]: 52
2774 09:58:14.693201 [Byte1]: 52
2775 09:58:14.697247
2776 09:58:14.697364 Set Vref, RX VrefLevel [Byte0]: 53
2777 09:58:14.700374 [Byte1]: 53
2778 09:58:14.705387
2779 09:58:14.705481 Set Vref, RX VrefLevel [Byte0]: 54
2780 09:58:14.708473 [Byte1]: 54
2781 09:58:14.713264
2782 09:58:14.713372 Set Vref, RX VrefLevel [Byte0]: 55
2783 09:58:14.716243 [Byte1]: 55
2784 09:58:14.721149
2785 09:58:14.721230 Set Vref, RX VrefLevel [Byte0]: 56
2786 09:58:14.724291 [Byte1]: 56
2787 09:58:14.729253
2788 09:58:14.729362 Set Vref, RX VrefLevel [Byte0]: 57
2789 09:58:14.732252 [Byte1]: 57
2790 09:58:14.736798
2791 09:58:14.736908 Set Vref, RX VrefLevel [Byte0]: 58
2792 09:58:14.740316 [Byte1]: 58
2793 09:58:14.744555
2794 09:58:14.744638 Set Vref, RX VrefLevel [Byte0]: 59
2795 09:58:14.748190 [Byte1]: 59
2796 09:58:14.753017
2797 09:58:14.753097 Set Vref, RX VrefLevel [Byte0]: 60
2798 09:58:14.755791 [Byte1]: 60
2799 09:58:14.760429
2800 09:58:14.760516 Set Vref, RX VrefLevel [Byte0]: 61
2801 09:58:14.764404 [Byte1]: 61
2802 09:58:14.768274
2803 09:58:14.768354 Set Vref, RX VrefLevel [Byte0]: 62
2804 09:58:14.771895 [Byte1]: 62
2805 09:58:14.775974
2806 09:58:14.779625 Set Vref, RX VrefLevel [Byte0]: 63
2807 09:58:14.782644 [Byte1]: 63
2808 09:58:14.782723
2809 09:58:14.786347 Set Vref, RX VrefLevel [Byte0]: 64
2810 09:58:14.789612 [Byte1]: 64
2811 09:58:14.789690
2812 09:58:14.792877 Set Vref, RX VrefLevel [Byte0]: 65
2813 09:58:14.796320 [Byte1]: 65
2814 09:58:14.799893
2815 09:58:14.799972 Set Vref, RX VrefLevel [Byte0]: 66
2816 09:58:14.803384 [Byte1]: 66
2817 09:58:14.808379
2818 09:58:14.808461 Set Vref, RX VrefLevel [Byte0]: 67
2819 09:58:14.811659 [Byte1]: 67
2820 09:58:14.816251
2821 09:58:14.816332 Set Vref, RX VrefLevel [Byte0]: 68
2822 09:58:14.819362 [Byte1]: 68
2823 09:58:14.824164
2824 09:58:14.824247 Set Vref, RX VrefLevel [Byte0]: 69
2825 09:58:14.827126 [Byte1]: 69
2826 09:58:14.832142
2827 09:58:14.832227 Set Vref, RX VrefLevel [Byte0]: 70
2828 09:58:14.835155 [Byte1]: 70
2829 09:58:14.839810
2830 09:58:14.839894 Set Vref, RX VrefLevel [Byte0]: 71
2831 09:58:14.843195 [Byte1]: 71
2832 09:58:14.847965
2833 09:58:14.848045 Set Vref, RX VrefLevel [Byte0]: 72
2834 09:58:14.851000 [Byte1]: 72
2835 09:58:14.855824
2836 09:58:14.855903 Set Vref, RX VrefLevel [Byte0]: 73
2837 09:58:14.858871 [Byte1]: 73
2838 09:58:14.863745
2839 09:58:14.863861 Set Vref, RX VrefLevel [Byte0]: 74
2840 09:58:14.867151 [Byte1]: 74
2841 09:58:14.871718
2842 09:58:14.871796 Set Vref, RX VrefLevel [Byte0]: 75
2843 09:58:14.874881 [Byte1]: 75
2844 09:58:14.879348
2845 09:58:14.879436 Set Vref, RX VrefLevel [Byte0]: 76
2846 09:58:14.882898 [Byte1]: 76
2847 09:58:14.887720
2848 09:58:14.887803 Set Vref, RX VrefLevel [Byte0]: 77
2849 09:58:14.890655 [Byte1]: 77
2850 09:58:14.895532
2851 09:58:14.895618 Set Vref, RX VrefLevel [Byte0]: 78
2852 09:58:14.898425 [Byte1]: 78
2853 09:58:14.903180
2854 09:58:14.903262 Final RX Vref Byte 0 = 55 to rank0
2855 09:58:14.906549 Final RX Vref Byte 1 = 48 to rank0
2856 09:58:14.910129 Final RX Vref Byte 0 = 55 to rank1
2857 09:58:14.913147 Final RX Vref Byte 1 = 48 to rank1==
2858 09:58:14.916479 Dram Type= 6, Freq= 0, CH_0, rank 0
2859 09:58:14.923338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2860 09:58:14.923453 ==
2861 09:58:14.923561 DQS Delay:
2862 09:58:14.923669 DQS0 = 0, DQS1 = 0
2863 09:58:14.926579 DQM Delay:
2864 09:58:14.926688 DQM0 = 118, DQM1 = 106
2865 09:58:14.930167 DQ Delay:
2866 09:58:14.933216 DQ0 =118, DQ1 =120, DQ2 =116, DQ3 =114
2867 09:58:14.936352 DQ4 =120, DQ5 =110, DQ6 =126, DQ7 =126
2868 09:58:14.940022 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =100
2869 09:58:14.943008 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =116
2870 09:58:14.943140
2871 09:58:14.943264
2872 09:58:14.953064 [DQSOSCAuto] RK0, (LSB)MR18= 0x10fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 403 ps
2873 09:58:14.953168 CH0 RK0: MR19=403, MR18=10FC
2874 09:58:14.959688 CH0_RK0: MR19=0x403, MR18=0x10FC, DQSOSC=403, MR23=63, INC=40, DEC=26
2875 09:58:14.959773
2876 09:58:14.963210 ----->DramcWriteLeveling(PI) begin...
2877 09:58:14.963296 ==
2878 09:58:14.966155 Dram Type= 6, Freq= 0, CH_0, rank 1
2879 09:58:14.973038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2880 09:58:14.973148 ==
2881 09:58:14.975949 Write leveling (Byte 0): 32 => 32
2882 09:58:14.976055 Write leveling (Byte 1): 30 => 30
2883 09:58:14.979530 DramcWriteLeveling(PI) end<-----
2884 09:58:14.979614
2885 09:58:14.979686 ==
2886 09:58:14.982769 Dram Type= 6, Freq= 0, CH_0, rank 1
2887 09:58:14.989193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2888 09:58:14.989309 ==
2889 09:58:14.992726 [Gating] SW mode calibration
2890 09:58:14.999397 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2891 09:58:15.002473 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2892 09:58:15.009320 0 15 0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
2893 09:58:15.012602 0 15 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2894 09:58:15.015913 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2895 09:58:15.022691 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2896 09:58:15.025651 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2897 09:58:15.029369 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2898 09:58:15.035562 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2899 09:58:15.039257 0 15 28 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
2900 09:58:15.042284 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
2901 09:58:15.048989 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2902 09:58:15.052392 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2903 09:58:15.055948 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 09:58:15.062329 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 09:58:15.065471 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 09:58:15.068930 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2907 09:58:15.075797 1 0 28 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
2908 09:58:15.078749 1 1 0 | B1->B0 | 3636 4444 | 0 0 | (0 0) (0 0)
2909 09:58:15.082262 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2910 09:58:15.085846 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2911 09:58:15.091957 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 09:58:15.095480 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 09:58:15.098708 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 09:58:15.105576 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2915 09:58:15.108652 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2916 09:58:15.112409 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2917 09:58:15.118562 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 09:58:15.122093 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 09:58:15.125021 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 09:58:15.131698 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 09:58:15.135339 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 09:58:15.138383 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 09:58:15.144937 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 09:58:15.148567 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 09:58:15.151638 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 09:58:15.158275 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 09:58:15.161671 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 09:58:15.165302 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 09:58:15.171865 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 09:58:15.174896 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2931 09:58:15.178626 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2932 09:58:15.184891 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2933 09:58:15.185005 Total UI for P1: 0, mck2ui 16
2934 09:58:15.191814 best dqsien dly found for B0: ( 1, 3, 26)
2935 09:58:15.194908 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 09:58:15.198484 Total UI for P1: 0, mck2ui 16
2937 09:58:15.201346 best dqsien dly found for B1: ( 1, 3, 30)
2938 09:58:15.205109 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2939 09:58:15.207973 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2940 09:58:15.208087
2941 09:58:15.211349 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2942 09:58:15.214591 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2943 09:58:15.217955 [Gating] SW calibration Done
2944 09:58:15.218048 ==
2945 09:58:15.221117 Dram Type= 6, Freq= 0, CH_0, rank 1
2946 09:58:15.224759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2947 09:58:15.228108 ==
2948 09:58:15.228220 RX Vref Scan: 0
2949 09:58:15.228315
2950 09:58:15.231315 RX Vref 0 -> 0, step: 1
2951 09:58:15.231434
2952 09:58:15.234967 RX Delay -40 -> 252, step: 8
2953 09:58:15.238188 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2954 09:58:15.241191 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2955 09:58:15.244649 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2956 09:58:15.248186 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2957 09:58:15.254231 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2958 09:58:15.257918 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2959 09:58:15.261126 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2960 09:58:15.264666 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2961 09:58:15.267899 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2962 09:58:15.274106 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2963 09:58:15.277568 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2964 09:58:15.281164 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2965 09:58:15.284217 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2966 09:58:15.287999 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2967 09:58:15.294367 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2968 09:58:15.297578 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2969 09:58:15.297693 ==
2970 09:58:15.300443 Dram Type= 6, Freq= 0, CH_0, rank 1
2971 09:58:15.304222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2972 09:58:15.304340 ==
2973 09:58:15.307178 DQS Delay:
2974 09:58:15.307296 DQS0 = 0, DQS1 = 0
2975 09:58:15.307400 DQM Delay:
2976 09:58:15.310786 DQM0 = 117, DQM1 = 108
2977 09:58:15.310898 DQ Delay:
2978 09:58:15.314043 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
2979 09:58:15.317518 DQ4 =119, DQ5 =107, DQ6 =127, DQ7 =127
2980 09:58:15.320354 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2981 09:58:15.327528 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
2982 09:58:15.327705
2983 09:58:15.327841
2984 09:58:15.327966 ==
2985 09:58:15.330537 Dram Type= 6, Freq= 0, CH_0, rank 1
2986 09:58:15.334038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2987 09:58:15.334179 ==
2988 09:58:15.334294
2989 09:58:15.334402
2990 09:58:15.336898 TX Vref Scan disable
2991 09:58:15.337032 == TX Byte 0 ==
2992 09:58:15.343544 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2993 09:58:15.347418 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2994 09:58:15.350414 == TX Byte 1 ==
2995 09:58:15.354060 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2996 09:58:15.356954 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2997 09:58:15.357051 ==
2998 09:58:15.360503 Dram Type= 6, Freq= 0, CH_0, rank 1
2999 09:58:15.363547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3000 09:58:15.363658 ==
3001 09:58:15.376677 TX Vref=22, minBit 5, minWin=25, winSum=419
3002 09:58:15.380115 TX Vref=24, minBit 1, minWin=26, winSum=422
3003 09:58:15.383248 TX Vref=26, minBit 12, minWin=25, winSum=421
3004 09:58:15.386930 TX Vref=28, minBit 13, minWin=25, winSum=431
3005 09:58:15.389885 TX Vref=30, minBit 10, minWin=25, winSum=430
3006 09:58:15.396575 TX Vref=32, minBit 11, minWin=25, winSum=428
3007 09:58:15.400117 [TxChooseVref] Worse bit 1, Min win 26, Win sum 422, Final Vref 24
3008 09:58:15.400249
3009 09:58:15.403169 Final TX Range 1 Vref 24
3010 09:58:15.403282
3011 09:58:15.403382 ==
3012 09:58:15.407020 Dram Type= 6, Freq= 0, CH_0, rank 1
3013 09:58:15.409895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3014 09:58:15.413454 ==
3015 09:58:15.413569
3016 09:58:15.413644
3017 09:58:15.413705 TX Vref Scan disable
3018 09:58:15.417134 == TX Byte 0 ==
3019 09:58:15.420327 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3020 09:58:15.426868 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3021 09:58:15.427010 == TX Byte 1 ==
3022 09:58:15.430250 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3023 09:58:15.436371 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3024 09:58:15.436524
3025 09:58:15.436601 [DATLAT]
3026 09:58:15.436665 Freq=1200, CH0 RK1
3027 09:58:15.436731
3028 09:58:15.439968 DATLAT Default: 0xd
3029 09:58:15.443258 0, 0xFFFF, sum = 0
3030 09:58:15.443391 1, 0xFFFF, sum = 0
3031 09:58:15.446629 2, 0xFFFF, sum = 0
3032 09:58:15.446752 3, 0xFFFF, sum = 0
3033 09:58:15.450222 4, 0xFFFF, sum = 0
3034 09:58:15.450352 5, 0xFFFF, sum = 0
3035 09:58:15.452994 6, 0xFFFF, sum = 0
3036 09:58:15.453117 7, 0xFFFF, sum = 0
3037 09:58:15.456544 8, 0xFFFF, sum = 0
3038 09:58:15.456639 9, 0xFFFF, sum = 0
3039 09:58:15.459824 10, 0xFFFF, sum = 0
3040 09:58:15.459944 11, 0xFFFF, sum = 0
3041 09:58:15.462929 12, 0x0, sum = 1
3042 09:58:15.463037 13, 0x0, sum = 2
3043 09:58:15.466479 14, 0x0, sum = 3
3044 09:58:15.466591 15, 0x0, sum = 4
3045 09:58:15.469383 best_step = 13
3046 09:58:15.469473
3047 09:58:15.469558 ==
3048 09:58:15.473055 Dram Type= 6, Freq= 0, CH_0, rank 1
3049 09:58:15.476057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3050 09:58:15.476135 ==
3051 09:58:15.479595 RX Vref Scan: 0
3052 09:58:15.479681
3053 09:58:15.479748 RX Vref 0 -> 0, step: 1
3054 09:58:15.479809
3055 09:58:15.482921 RX Delay -21 -> 252, step: 4
3056 09:58:15.489305 iDelay=199, Bit 0, Center 114 (51 ~ 178) 128
3057 09:58:15.493035 iDelay=199, Bit 1, Center 120 (51 ~ 190) 140
3058 09:58:15.496277 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3059 09:58:15.499533 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3060 09:58:15.502774 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3061 09:58:15.509484 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3062 09:58:15.513004 iDelay=199, Bit 6, Center 128 (59 ~ 198) 140
3063 09:58:15.516127 iDelay=199, Bit 7, Center 126 (59 ~ 194) 136
3064 09:58:15.519331 iDelay=199, Bit 8, Center 96 (27 ~ 166) 140
3065 09:58:15.522938 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3066 09:58:15.529072 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3067 09:58:15.532687 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3068 09:58:15.535805 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
3069 09:58:15.539361 iDelay=199, Bit 13, Center 114 (47 ~ 182) 136
3070 09:58:15.542553 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3071 09:58:15.549207 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3072 09:58:15.549296 ==
3073 09:58:15.552313 Dram Type= 6, Freq= 0, CH_0, rank 1
3074 09:58:15.556075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3075 09:58:15.556186 ==
3076 09:58:15.556285 DQS Delay:
3077 09:58:15.559350 DQS0 = 0, DQS1 = 0
3078 09:58:15.559445 DQM Delay:
3079 09:58:15.562170 DQM0 = 117, DQM1 = 107
3080 09:58:15.562284 DQ Delay:
3081 09:58:15.565478 DQ0 =114, DQ1 =120, DQ2 =110, DQ3 =114
3082 09:58:15.568709 DQ4 =116, DQ5 =110, DQ6 =128, DQ7 =126
3083 09:58:15.572547 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3084 09:58:15.575273 DQ12 =112, DQ13 =114, DQ14 =118, DQ15 =116
3085 09:58:15.575432
3086 09:58:15.579009
3087 09:58:15.585553 [DQSOSCAuto] RK1, (LSB)MR18= 0x10eb, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 403 ps
3088 09:58:15.588515 CH0 RK1: MR19=403, MR18=10EB
3089 09:58:15.595386 CH0_RK1: MR19=0x403, MR18=0x10EB, DQSOSC=403, MR23=63, INC=40, DEC=26
3090 09:58:15.598460 [RxdqsGatingPostProcess] freq 1200
3091 09:58:15.602047 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3092 09:58:15.605474 best DQS0 dly(2T, 0.5T) = (0, 11)
3093 09:58:15.608465 best DQS1 dly(2T, 0.5T) = (0, 12)
3094 09:58:15.612025 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3095 09:58:15.615125 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3096 09:58:15.618917 best DQS0 dly(2T, 0.5T) = (0, 11)
3097 09:58:15.621820 best DQS1 dly(2T, 0.5T) = (0, 11)
3098 09:58:15.625631 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3099 09:58:15.628587 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3100 09:58:15.632243 Pre-setting of DQS Precalculation
3101 09:58:15.635366 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3102 09:58:15.635474 ==
3103 09:58:15.638979 Dram Type= 6, Freq= 0, CH_1, rank 0
3104 09:58:15.641832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3105 09:58:15.645380 ==
3106 09:58:15.648864 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3107 09:58:15.655201 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3108 09:58:15.663644 [CA 0] Center 37 (7~68) winsize 62
3109 09:58:15.666615 [CA 1] Center 37 (7~68) winsize 62
3110 09:58:15.669814 [CA 2] Center 34 (4~64) winsize 61
3111 09:58:15.673032 [CA 3] Center 33 (3~64) winsize 62
3112 09:58:15.676790 [CA 4] Center 34 (5~64) winsize 60
3113 09:58:15.680273 [CA 5] Center 33 (3~64) winsize 62
3114 09:58:15.680390
3115 09:58:15.683332 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3116 09:58:15.683436
3117 09:58:15.686296 [CATrainingPosCal] consider 1 rank data
3118 09:58:15.689758 u2DelayCellTimex100 = 270/100 ps
3119 09:58:15.693308 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3120 09:58:15.699752 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3121 09:58:15.702846 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3122 09:58:15.706388 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3123 09:58:15.709835 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3124 09:58:15.712881 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3125 09:58:15.712997
3126 09:58:15.716506 CA PerBit enable=1, Macro0, CA PI delay=33
3127 09:58:15.716619
3128 09:58:15.719670 [CBTSetCACLKResult] CA Dly = 33
3129 09:58:15.719776 CS Dly: 6 (0~37)
3130 09:58:15.723262 ==
3131 09:58:15.726207 Dram Type= 6, Freq= 0, CH_1, rank 1
3132 09:58:15.729272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3133 09:58:15.729375 ==
3134 09:58:15.732884 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3135 09:58:15.739566 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3136 09:58:15.749039 [CA 0] Center 37 (7~68) winsize 62
3137 09:58:15.752013 [CA 1] Center 38 (8~68) winsize 61
3138 09:58:15.755458 [CA 2] Center 34 (4~65) winsize 62
3139 09:58:15.758982 [CA 3] Center 33 (3~64) winsize 62
3140 09:58:15.762165 [CA 4] Center 34 (3~65) winsize 63
3141 09:58:15.765190 [CA 5] Center 33 (3~64) winsize 62
3142 09:58:15.765302
3143 09:58:15.769142 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3144 09:58:15.769248
3145 09:58:15.772419 [CATrainingPosCal] consider 2 rank data
3146 09:58:15.775333 u2DelayCellTimex100 = 270/100 ps
3147 09:58:15.778914 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3148 09:58:15.785254 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3149 09:58:15.788883 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3150 09:58:15.792034 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3151 09:58:15.795535 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3152 09:58:15.798522 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3153 09:58:15.798605
3154 09:58:15.802044 CA PerBit enable=1, Macro0, CA PI delay=33
3155 09:58:15.802159
3156 09:58:15.805091 [CBTSetCACLKResult] CA Dly = 33
3157 09:58:15.805208 CS Dly: 7 (0~40)
3158 09:58:15.808606
3159 09:58:15.812131 ----->DramcWriteLeveling(PI) begin...
3160 09:58:15.812238 ==
3161 09:58:15.814922 Dram Type= 6, Freq= 0, CH_1, rank 0
3162 09:58:15.818629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3163 09:58:15.818742 ==
3164 09:58:15.821678 Write leveling (Byte 0): 25 => 25
3165 09:58:15.824907 Write leveling (Byte 1): 27 => 27
3166 09:58:15.828315 DramcWriteLeveling(PI) end<-----
3167 09:58:15.828425
3168 09:58:15.828492 ==
3169 09:58:15.831493 Dram Type= 6, Freq= 0, CH_1, rank 0
3170 09:58:15.835051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3171 09:58:15.835135 ==
3172 09:58:15.838710 [Gating] SW mode calibration
3173 09:58:15.844736 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3174 09:58:15.851940 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3175 09:58:15.854923 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3176 09:58:15.858257 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3177 09:58:15.864999 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3178 09:58:15.868362 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 09:58:15.871670 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 09:58:15.878285 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 09:58:15.881520 0 15 24 | B1->B0 | 3434 2828 | 1 1 | (1 1) (1 1)
3182 09:58:15.885029 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (1 0)
3183 09:58:15.891565 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3184 09:58:15.894423 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 09:58:15.897732 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 09:58:15.904592 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 09:58:15.908028 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 09:58:15.910973 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 09:58:15.918254 1 0 24 | B1->B0 | 2626 3130 | 0 1 | (0 0) (0 0)
3190 09:58:15.921299 1 0 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3191 09:58:15.924374 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3192 09:58:15.930841 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 09:58:15.934517 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 09:58:15.937647 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 09:58:15.944483 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 09:58:15.947315 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 09:58:15.950519 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3198 09:58:15.957687 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3199 09:58:15.960781 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 09:58:15.963914 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 09:58:15.967617 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 09:58:15.973822 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 09:58:15.977375 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 09:58:15.980620 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 09:58:15.987578 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 09:58:15.990627 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 09:58:15.993812 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 09:58:16.000532 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 09:58:16.004232 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 09:58:16.007117 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 09:58:16.014183 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 09:58:16.017400 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 09:58:16.020676 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3214 09:58:16.027001 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3215 09:58:16.030767 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3216 09:58:16.033512 Total UI for P1: 0, mck2ui 16
3217 09:58:16.037176 best dqsien dly found for B0: ( 1, 3, 26)
3218 09:58:16.040369 Total UI for P1: 0, mck2ui 16
3219 09:58:16.043873 best dqsien dly found for B1: ( 1, 3, 26)
3220 09:58:16.046978 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3221 09:58:16.050449 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3222 09:58:16.050529
3223 09:58:16.053768 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3224 09:58:16.056991 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3225 09:58:16.060612 [Gating] SW calibration Done
3226 09:58:16.060704 ==
3227 09:58:16.063620 Dram Type= 6, Freq= 0, CH_1, rank 0
3228 09:58:16.067240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3229 09:58:16.070320 ==
3230 09:58:16.070411 RX Vref Scan: 0
3231 09:58:16.070514
3232 09:58:16.073929 RX Vref 0 -> 0, step: 1
3233 09:58:16.074020
3234 09:58:16.077157 RX Delay -40 -> 252, step: 8
3235 09:58:16.080094 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3236 09:58:16.083698 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3237 09:58:16.086762 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3238 09:58:16.089938 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3239 09:58:16.097032 iDelay=208, Bit 4, Center 115 (48 ~ 183) 136
3240 09:58:16.100291 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3241 09:58:16.103912 iDelay=208, Bit 6, Center 127 (56 ~ 199) 144
3242 09:58:16.106743 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3243 09:58:16.110018 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3244 09:58:16.113619 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3245 09:58:16.119830 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3246 09:58:16.123416 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3247 09:58:16.126757 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3248 09:58:16.130213 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3249 09:58:16.136394 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3250 09:58:16.139975 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3251 09:58:16.140059 ==
3252 09:58:16.143086 Dram Type= 6, Freq= 0, CH_1, rank 0
3253 09:58:16.146891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3254 09:58:16.146976 ==
3255 09:58:16.149790 DQS Delay:
3256 09:58:16.149893 DQS0 = 0, DQS1 = 0
3257 09:58:16.149961 DQM Delay:
3258 09:58:16.152889 DQM0 = 118, DQM1 = 109
3259 09:58:16.152973 DQ Delay:
3260 09:58:16.156465 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3261 09:58:16.159549 DQ4 =115, DQ5 =131, DQ6 =127, DQ7 =115
3262 09:58:16.163214 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3263 09:58:16.169348 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3264 09:58:16.169459
3265 09:58:16.169526
3266 09:58:16.169586 ==
3267 09:58:16.173063 Dram Type= 6, Freq= 0, CH_1, rank 0
3268 09:58:16.176152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3269 09:58:16.176259 ==
3270 09:58:16.176350
3271 09:58:16.176448
3272 09:58:16.179931 TX Vref Scan disable
3273 09:58:16.180010 == TX Byte 0 ==
3274 09:58:16.186454 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3275 09:58:16.189538 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3276 09:58:16.189614 == TX Byte 1 ==
3277 09:58:16.195875 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3278 09:58:16.199623 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3279 09:58:16.199708 ==
3280 09:58:16.202666 Dram Type= 6, Freq= 0, CH_1, rank 0
3281 09:58:16.206217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3282 09:58:16.206300 ==
3283 09:58:16.218539 TX Vref=22, minBit 8, minWin=25, winSum=417
3284 09:58:16.221732 TX Vref=24, minBit 9, minWin=25, winSum=422
3285 09:58:16.225242 TX Vref=26, minBit 9, minWin=25, winSum=428
3286 09:58:16.228670 TX Vref=28, minBit 8, minWin=26, winSum=435
3287 09:58:16.231814 TX Vref=30, minBit 11, minWin=25, winSum=430
3288 09:58:16.238468 TX Vref=32, minBit 4, minWin=26, winSum=429
3289 09:58:16.241718 [TxChooseVref] Worse bit 8, Min win 26, Win sum 435, Final Vref 28
3290 09:58:16.241798
3291 09:58:16.244976 Final TX Range 1 Vref 28
3292 09:58:16.245093
3293 09:58:16.245188 ==
3294 09:58:16.248146 Dram Type= 6, Freq= 0, CH_1, rank 0
3295 09:58:16.251494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3296 09:58:16.255196 ==
3297 09:58:16.255302
3298 09:58:16.255394
3299 09:58:16.255483 TX Vref Scan disable
3300 09:58:16.258471 == TX Byte 0 ==
3301 09:58:16.261924 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3302 09:58:16.264964 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3303 09:58:16.268881 == TX Byte 1 ==
3304 09:58:16.271594 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3305 09:58:16.275246 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3306 09:58:16.278262
3307 09:58:16.278373 [DATLAT]
3308 09:58:16.278468 Freq=1200, CH1 RK0
3309 09:58:16.278567
3310 09:58:16.282058 DATLAT Default: 0xd
3311 09:58:16.282182 0, 0xFFFF, sum = 0
3312 09:58:16.284938 1, 0xFFFF, sum = 0
3313 09:58:16.285023 2, 0xFFFF, sum = 0
3314 09:58:16.288811 3, 0xFFFF, sum = 0
3315 09:58:16.291722 4, 0xFFFF, sum = 0
3316 09:58:16.291810 5, 0xFFFF, sum = 0
3317 09:58:16.294976 6, 0xFFFF, sum = 0
3318 09:58:16.295095 7, 0xFFFF, sum = 0
3319 09:58:16.298680 8, 0xFFFF, sum = 0
3320 09:58:16.298786 9, 0xFFFF, sum = 0
3321 09:58:16.301441 10, 0xFFFF, sum = 0
3322 09:58:16.301528 11, 0xFFFF, sum = 0
3323 09:58:16.304893 12, 0x0, sum = 1
3324 09:58:16.305010 13, 0x0, sum = 2
3325 09:58:16.308061 14, 0x0, sum = 3
3326 09:58:16.308165 15, 0x0, sum = 4
3327 09:58:16.308271 best_step = 13
3328 09:58:16.311522
3329 09:58:16.311627 ==
3330 09:58:16.314784 Dram Type= 6, Freq= 0, CH_1, rank 0
3331 09:58:16.318435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3332 09:58:16.318546 ==
3333 09:58:16.318613 RX Vref Scan: 1
3334 09:58:16.318673
3335 09:58:16.321594 Set Vref Range= 32 -> 127
3336 09:58:16.321696
3337 09:58:16.324812 RX Vref 32 -> 127, step: 1
3338 09:58:16.324917
3339 09:58:16.327967 RX Delay -21 -> 252, step: 4
3340 09:58:16.328070
3341 09:58:16.331803 Set Vref, RX VrefLevel [Byte0]: 32
3342 09:58:16.335212 [Byte1]: 32
3343 09:58:16.335327
3344 09:58:16.338115 Set Vref, RX VrefLevel [Byte0]: 33
3345 09:58:16.341562 [Byte1]: 33
3346 09:58:16.345328
3347 09:58:16.345446 Set Vref, RX VrefLevel [Byte0]: 34
3348 09:58:16.348283 [Byte1]: 34
3349 09:58:16.353122
3350 09:58:16.353223 Set Vref, RX VrefLevel [Byte0]: 35
3351 09:58:16.355939 [Byte1]: 35
3352 09:58:16.360694
3353 09:58:16.360814 Set Vref, RX VrefLevel [Byte0]: 36
3354 09:58:16.363763 [Byte1]: 36
3355 09:58:16.368712
3356 09:58:16.368821 Set Vref, RX VrefLevel [Byte0]: 37
3357 09:58:16.371732 [Byte1]: 37
3358 09:58:16.376701
3359 09:58:16.376816 Set Vref, RX VrefLevel [Byte0]: 38
3360 09:58:16.379604 [Byte1]: 38
3361 09:58:16.384388
3362 09:58:16.384492 Set Vref, RX VrefLevel [Byte0]: 39
3363 09:58:16.387661 [Byte1]: 39
3364 09:58:16.392320
3365 09:58:16.392423 Set Vref, RX VrefLevel [Byte0]: 40
3366 09:58:16.396055 [Byte1]: 40
3367 09:58:16.400309
3368 09:58:16.400416 Set Vref, RX VrefLevel [Byte0]: 41
3369 09:58:16.403936 [Byte1]: 41
3370 09:58:16.408387
3371 09:58:16.408475 Set Vref, RX VrefLevel [Byte0]: 42
3372 09:58:16.411800 [Byte1]: 42
3373 09:58:16.416312
3374 09:58:16.416389 Set Vref, RX VrefLevel [Byte0]: 43
3375 09:58:16.419447 [Byte1]: 43
3376 09:58:16.424321
3377 09:58:16.424428 Set Vref, RX VrefLevel [Byte0]: 44
3378 09:58:16.427601 [Byte1]: 44
3379 09:58:16.432140
3380 09:58:16.432245 Set Vref, RX VrefLevel [Byte0]: 45
3381 09:58:16.435125 [Byte1]: 45
3382 09:58:16.439919
3383 09:58:16.440024 Set Vref, RX VrefLevel [Byte0]: 46
3384 09:58:16.443460 [Byte1]: 46
3385 09:58:16.447751
3386 09:58:16.447858 Set Vref, RX VrefLevel [Byte0]: 47
3387 09:58:16.451132 [Byte1]: 47
3388 09:58:16.455819
3389 09:58:16.455928 Set Vref, RX VrefLevel [Byte0]: 48
3390 09:58:16.459071 [Byte1]: 48
3391 09:58:16.463744
3392 09:58:16.463854 Set Vref, RX VrefLevel [Byte0]: 49
3393 09:58:16.467433 [Byte1]: 49
3394 09:58:16.471880
3395 09:58:16.471961 Set Vref, RX VrefLevel [Byte0]: 50
3396 09:58:16.474631 [Byte1]: 50
3397 09:58:16.479695
3398 09:58:16.479800 Set Vref, RX VrefLevel [Byte0]: 51
3399 09:58:16.482906 [Byte1]: 51
3400 09:58:16.487514
3401 09:58:16.487624 Set Vref, RX VrefLevel [Byte0]: 52
3402 09:58:16.490873 [Byte1]: 52
3403 09:58:16.495691
3404 09:58:16.495796 Set Vref, RX VrefLevel [Byte0]: 53
3405 09:58:16.498612 [Byte1]: 53
3406 09:58:16.502998
3407 09:58:16.503113 Set Vref, RX VrefLevel [Byte0]: 54
3408 09:58:16.506663 [Byte1]: 54
3409 09:58:16.511127
3410 09:58:16.511240 Set Vref, RX VrefLevel [Byte0]: 55
3411 09:58:16.514219 [Byte1]: 55
3412 09:58:16.519104
3413 09:58:16.519213 Set Vref, RX VrefLevel [Byte0]: 56
3414 09:58:16.522151 [Byte1]: 56
3415 09:58:16.527193
3416 09:58:16.527300 Set Vref, RX VrefLevel [Byte0]: 57
3417 09:58:16.530571 [Byte1]: 57
3418 09:58:16.534941
3419 09:58:16.535052 Set Vref, RX VrefLevel [Byte0]: 58
3420 09:58:16.538128 [Byte1]: 58
3421 09:58:16.542954
3422 09:58:16.543045 Set Vref, RX VrefLevel [Byte0]: 59
3423 09:58:16.546280 [Byte1]: 59
3424 09:58:16.550707
3425 09:58:16.550825 Set Vref, RX VrefLevel [Byte0]: 60
3426 09:58:16.554201 [Byte1]: 60
3427 09:58:16.558678
3428 09:58:16.558783 Set Vref, RX VrefLevel [Byte0]: 61
3429 09:58:16.561899 [Byte1]: 61
3430 09:58:16.566743
3431 09:58:16.566852 Set Vref, RX VrefLevel [Byte0]: 62
3432 09:58:16.569619 [Byte1]: 62
3433 09:58:16.574759
3434 09:58:16.574840 Set Vref, RX VrefLevel [Byte0]: 63
3435 09:58:16.577779 [Byte1]: 63
3436 09:58:16.582287
3437 09:58:16.582394 Set Vref, RX VrefLevel [Byte0]: 64
3438 09:58:16.585655 [Byte1]: 64
3439 09:58:16.590074
3440 09:58:16.590168 Set Vref, RX VrefLevel [Byte0]: 65
3441 09:58:16.593308 [Byte1]: 65
3442 09:58:16.597942
3443 09:58:16.598049 Set Vref, RX VrefLevel [Byte0]: 66
3444 09:58:16.601750 [Byte1]: 66
3445 09:58:16.606164
3446 09:58:16.606250 Set Vref, RX VrefLevel [Byte0]: 67
3447 09:58:16.609766 [Byte1]: 67
3448 09:58:16.613981
3449 09:58:16.614064 Set Vref, RX VrefLevel [Byte0]: 68
3450 09:58:16.617624 [Byte1]: 68
3451 09:58:16.622301
3452 09:58:16.622381 Final RX Vref Byte 0 = 51 to rank0
3453 09:58:16.625440 Final RX Vref Byte 1 = 53 to rank0
3454 09:58:16.628542 Final RX Vref Byte 0 = 51 to rank1
3455 09:58:16.632058 Final RX Vref Byte 1 = 53 to rank1==
3456 09:58:16.634972 Dram Type= 6, Freq= 0, CH_1, rank 0
3457 09:58:16.641867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3458 09:58:16.642043 ==
3459 09:58:16.642143 DQS Delay:
3460 09:58:16.642235 DQS0 = 0, DQS1 = 0
3461 09:58:16.645401 DQM Delay:
3462 09:58:16.645561 DQM0 = 116, DQM1 = 110
3463 09:58:16.648382 DQ Delay:
3464 09:58:16.651926 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =112
3465 09:58:16.655592 DQ4 =114, DQ5 =128, DQ6 =124, DQ7 =112
3466 09:58:16.658661 DQ8 =96, DQ9 =102, DQ10 =112, DQ11 =100
3467 09:58:16.662211 DQ12 =118, DQ13 =118, DQ14 =120, DQ15 =118
3468 09:58:16.662362
3469 09:58:16.662478
3470 09:58:16.668784 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 409 ps
3471 09:58:16.671824 CH1 RK0: MR19=403, MR18=2F5
3472 09:58:16.678759 CH1_RK0: MR19=0x403, MR18=0x2F5, DQSOSC=409, MR23=63, INC=39, DEC=26
3473 09:58:16.678859
3474 09:58:16.681998 ----->DramcWriteLeveling(PI) begin...
3475 09:58:16.682121 ==
3476 09:58:16.684860 Dram Type= 6, Freq= 0, CH_1, rank 1
3477 09:58:16.688653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3478 09:58:16.691764 ==
3479 09:58:16.691874 Write leveling (Byte 0): 24 => 24
3480 09:58:16.695413 Write leveling (Byte 1): 28 => 28
3481 09:58:16.698330 DramcWriteLeveling(PI) end<-----
3482 09:58:16.698422
3483 09:58:16.698493 ==
3484 09:58:16.701657 Dram Type= 6, Freq= 0, CH_1, rank 1
3485 09:58:16.708201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3486 09:58:16.708341 ==
3487 09:58:16.711483 [Gating] SW mode calibration
3488 09:58:16.718143 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3489 09:58:16.721609 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3490 09:58:16.728241 0 15 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
3491 09:58:16.731296 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3492 09:58:16.735138 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3493 09:58:16.741337 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3494 09:58:16.744188 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3495 09:58:16.747493 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3496 09:58:16.754465 0 15 24 | B1->B0 | 3030 3434 | 0 0 | (0 0) (0 0)
3497 09:58:16.757306 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3498 09:58:16.760588 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3499 09:58:16.767861 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3500 09:58:16.770693 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3501 09:58:16.774463 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3502 09:58:16.780775 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3503 09:58:16.784136 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3504 09:58:16.787357 1 0 24 | B1->B0 | 3535 2323 | 0 0 | (1 1) (0 0)
3505 09:58:16.793822 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3506 09:58:16.797616 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3507 09:58:16.800581 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3508 09:58:16.807196 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 09:58:16.810161 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 09:58:16.813914 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3511 09:58:16.820536 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3512 09:58:16.823697 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3513 09:58:16.826856 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3514 09:58:16.833524 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 09:58:16.836826 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 09:58:16.840115 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 09:58:16.846901 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 09:58:16.849849 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 09:58:16.853350 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 09:58:16.860101 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 09:58:16.863490 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 09:58:16.866478 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 09:58:16.873095 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 09:58:16.876294 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 09:58:16.879844 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 09:58:16.886605 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 09:58:16.889508 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 09:58:16.892824 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3529 09:58:16.899449 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3530 09:58:16.899597 Total UI for P1: 0, mck2ui 16
3531 09:58:16.906171 best dqsien dly found for B1: ( 1, 3, 24)
3532 09:58:16.909182 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3533 09:58:16.912321 Total UI for P1: 0, mck2ui 16
3534 09:58:16.915883 best dqsien dly found for B0: ( 1, 3, 28)
3535 09:58:16.918848 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3536 09:58:16.922555 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3537 09:58:16.922677
3538 09:58:16.925632 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3539 09:58:16.928800 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3540 09:58:16.932269 [Gating] SW calibration Done
3541 09:58:16.932388 ==
3542 09:58:16.935757 Dram Type= 6, Freq= 0, CH_1, rank 1
3543 09:58:16.939310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3544 09:58:16.942208 ==
3545 09:58:16.942338 RX Vref Scan: 0
3546 09:58:16.942442
3547 09:58:16.945858 RX Vref 0 -> 0, step: 1
3548 09:58:16.945984
3549 09:58:16.948692 RX Delay -40 -> 252, step: 8
3550 09:58:16.951705 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
3551 09:58:16.955356 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3552 09:58:16.959014 iDelay=208, Bit 2, Center 107 (40 ~ 175) 136
3553 09:58:16.961982 iDelay=208, Bit 3, Center 111 (40 ~ 183) 144
3554 09:58:16.968611 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3555 09:58:16.971877 iDelay=208, Bit 5, Center 127 (56 ~ 199) 144
3556 09:58:16.975064 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3557 09:58:16.978621 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3558 09:58:16.981946 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3559 09:58:16.988427 iDelay=208, Bit 9, Center 103 (32 ~ 175) 144
3560 09:58:16.992089 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3561 09:58:16.994918 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3562 09:58:16.998185 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3563 09:58:17.004608 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3564 09:58:17.008116 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3565 09:58:17.011225 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3566 09:58:17.011325 ==
3567 09:58:17.014766 Dram Type= 6, Freq= 0, CH_1, rank 1
3568 09:58:17.018115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3569 09:58:17.018246 ==
3570 09:58:17.021581 DQS Delay:
3571 09:58:17.021705 DQS0 = 0, DQS1 = 0
3572 09:58:17.024743 DQM Delay:
3573 09:58:17.024836 DQM0 = 117, DQM1 = 110
3574 09:58:17.024899 DQ Delay:
3575 09:58:17.027756 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =111
3576 09:58:17.034528 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =115
3577 09:58:17.037999 DQ8 =95, DQ9 =103, DQ10 =111, DQ11 =103
3578 09:58:17.041183 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3579 09:58:17.041304
3580 09:58:17.041405
3581 09:58:17.041490 ==
3582 09:58:17.044916 Dram Type= 6, Freq= 0, CH_1, rank 1
3583 09:58:17.047756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3584 09:58:17.047880 ==
3585 09:58:17.047987
3586 09:58:17.048082
3587 09:58:17.051019 TX Vref Scan disable
3588 09:58:17.054681 == TX Byte 0 ==
3589 09:58:17.057562 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3590 09:58:17.060713 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3591 09:58:17.064308 == TX Byte 1 ==
3592 09:58:17.067319 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3593 09:58:17.070846 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3594 09:58:17.070954 ==
3595 09:58:17.074327 Dram Type= 6, Freq= 0, CH_1, rank 1
3596 09:58:17.080504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3597 09:58:17.080636 ==
3598 09:58:17.090812 TX Vref=22, minBit 9, minWin=25, winSum=424
3599 09:58:17.094500 TX Vref=24, minBit 8, minWin=25, winSum=427
3600 09:58:17.097555 TX Vref=26, minBit 8, minWin=25, winSum=430
3601 09:58:17.101211 TX Vref=28, minBit 8, minWin=26, winSum=433
3602 09:58:17.104435 TX Vref=30, minBit 8, minWin=26, winSum=434
3603 09:58:17.111231 TX Vref=32, minBit 9, minWin=25, winSum=432
3604 09:58:17.114346 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 30
3605 09:58:17.114436
3606 09:58:17.117607 Final TX Range 1 Vref 30
3607 09:58:17.117693
3608 09:58:17.117765 ==
3609 09:58:17.120570 Dram Type= 6, Freq= 0, CH_1, rank 1
3610 09:58:17.124035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3611 09:58:17.127204 ==
3612 09:58:17.127329
3613 09:58:17.127436
3614 09:58:17.127538 TX Vref Scan disable
3615 09:58:17.130696 == TX Byte 0 ==
3616 09:58:17.133953 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3617 09:58:17.140900 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3618 09:58:17.141048 == TX Byte 1 ==
3619 09:58:17.143886 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3620 09:58:17.150366 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3621 09:58:17.150519
3622 09:58:17.150620 [DATLAT]
3623 09:58:17.150718 Freq=1200, CH1 RK1
3624 09:58:17.150811
3625 09:58:17.154201 DATLAT Default: 0xd
3626 09:58:17.157274 0, 0xFFFF, sum = 0
3627 09:58:17.157402 1, 0xFFFF, sum = 0
3628 09:58:17.160677 2, 0xFFFF, sum = 0
3629 09:58:17.160806 3, 0xFFFF, sum = 0
3630 09:58:17.163462 4, 0xFFFF, sum = 0
3631 09:58:17.163598 5, 0xFFFF, sum = 0
3632 09:58:17.167358 6, 0xFFFF, sum = 0
3633 09:58:17.167486 7, 0xFFFF, sum = 0
3634 09:58:17.170297 8, 0xFFFF, sum = 0
3635 09:58:17.170398 9, 0xFFFF, sum = 0
3636 09:58:17.173430 10, 0xFFFF, sum = 0
3637 09:58:17.173562 11, 0xFFFF, sum = 0
3638 09:58:17.176916 12, 0x0, sum = 1
3639 09:58:17.177031 13, 0x0, sum = 2
3640 09:58:17.180233 14, 0x0, sum = 3
3641 09:58:17.180336 15, 0x0, sum = 4
3642 09:58:17.183446 best_step = 13
3643 09:58:17.183549
3644 09:58:17.183639 ==
3645 09:58:17.186634 Dram Type= 6, Freq= 0, CH_1, rank 1
3646 09:58:17.190270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3647 09:58:17.190380 ==
3648 09:58:17.193600 RX Vref Scan: 0
3649 09:58:17.193705
3650 09:58:17.193798 RX Vref 0 -> 0, step: 1
3651 09:58:17.193881
3652 09:58:17.196450 RX Delay -21 -> 252, step: 4
3653 09:58:17.203356 iDelay=199, Bit 0, Center 122 (55 ~ 190) 136
3654 09:58:17.206435 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3655 09:58:17.209953 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3656 09:58:17.212987 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3657 09:58:17.216563 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3658 09:58:17.222744 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3659 09:58:17.226348 iDelay=199, Bit 6, Center 128 (59 ~ 198) 140
3660 09:58:17.229332 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3661 09:58:17.232811 iDelay=199, Bit 8, Center 96 (31 ~ 162) 132
3662 09:58:17.239474 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3663 09:58:17.242375 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3664 09:58:17.245586 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3665 09:58:17.248964 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3666 09:58:17.252316 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3667 09:58:17.258859 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3668 09:58:17.262537 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3669 09:58:17.262641 ==
3670 09:58:17.266218 Dram Type= 6, Freq= 0, CH_1, rank 1
3671 09:58:17.269154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3672 09:58:17.269248 ==
3673 09:58:17.272644 DQS Delay:
3674 09:58:17.272738 DQS0 = 0, DQS1 = 0
3675 09:58:17.272804 DQM Delay:
3676 09:58:17.275602 DQM0 = 117, DQM1 = 110
3677 09:58:17.275683 DQ Delay:
3678 09:58:17.279339 DQ0 =122, DQ1 =110, DQ2 =106, DQ3 =112
3679 09:58:17.282519 DQ4 =116, DQ5 =126, DQ6 =128, DQ7 =116
3680 09:58:17.289002 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =100
3681 09:58:17.292088 DQ12 =118, DQ13 =118, DQ14 =120, DQ15 =120
3682 09:58:17.292245
3683 09:58:17.292388
3684 09:58:17.298756 [DQSOSCAuto] RK1, (LSB)MR18= 0xf2ed, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
3685 09:58:17.302256 CH1 RK1: MR19=303, MR18=F2ED
3686 09:58:17.308533 CH1_RK1: MR19=0x303, MR18=0xF2ED, DQSOSC=415, MR23=63, INC=38, DEC=25
3687 09:58:17.311629 [RxdqsGatingPostProcess] freq 1200
3688 09:58:17.315266 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3689 09:58:17.318495 best DQS0 dly(2T, 0.5T) = (0, 11)
3690 09:58:17.322033 best DQS1 dly(2T, 0.5T) = (0, 11)
3691 09:58:17.325112 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3692 09:58:17.328766 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3693 09:58:17.331780 best DQS0 dly(2T, 0.5T) = (0, 11)
3694 09:58:17.334810 best DQS1 dly(2T, 0.5T) = (0, 11)
3695 09:58:17.338323 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3696 09:58:17.341379 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3697 09:58:17.345116 Pre-setting of DQS Precalculation
3698 09:58:17.351895 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3699 09:58:17.358515 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3700 09:58:17.364693 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3701 09:58:17.364845
3702 09:58:17.364938
3703 09:58:17.368312 [Calibration Summary] 2400 Mbps
3704 09:58:17.368401 CH 0, Rank 0
3705 09:58:17.371203 SW Impedance : PASS
3706 09:58:17.374427 DUTY Scan : NO K
3707 09:58:17.374558 ZQ Calibration : PASS
3708 09:58:17.378136 Jitter Meter : NO K
3709 09:58:17.381324 CBT Training : PASS
3710 09:58:17.381449 Write leveling : PASS
3711 09:58:17.384758 RX DQS gating : PASS
3712 09:58:17.384883 RX DQ/DQS(RDDQC) : PASS
3713 09:58:17.387881 TX DQ/DQS : PASS
3714 09:58:17.390986 RX DATLAT : PASS
3715 09:58:17.391070 RX DQ/DQS(Engine): PASS
3716 09:58:17.394671 TX OE : NO K
3717 09:58:17.394768 All Pass.
3718 09:58:17.394835
3719 09:58:17.397779 CH 0, Rank 1
3720 09:58:17.397858 SW Impedance : PASS
3721 09:58:17.400850 DUTY Scan : NO K
3722 09:58:17.404369 ZQ Calibration : PASS
3723 09:58:17.404483 Jitter Meter : NO K
3724 09:58:17.407226 CBT Training : PASS
3725 09:58:17.411057 Write leveling : PASS
3726 09:58:17.411171 RX DQS gating : PASS
3727 09:58:17.414143 RX DQ/DQS(RDDQC) : PASS
3728 09:58:17.417558 TX DQ/DQS : PASS
3729 09:58:17.417677 RX DATLAT : PASS
3730 09:58:17.420529 RX DQ/DQS(Engine): PASS
3731 09:58:17.423992 TX OE : NO K
3732 09:58:17.424082 All Pass.
3733 09:58:17.424156
3734 09:58:17.424238 CH 1, Rank 0
3735 09:58:17.426990 SW Impedance : PASS
3736 09:58:17.430645 DUTY Scan : NO K
3737 09:58:17.430783 ZQ Calibration : PASS
3738 09:58:17.433894 Jitter Meter : NO K
3739 09:58:17.437382 CBT Training : PASS
3740 09:58:17.437497 Write leveling : PASS
3741 09:58:17.440429 RX DQS gating : PASS
3742 09:58:17.444060 RX DQ/DQS(RDDQC) : PASS
3743 09:58:17.444160 TX DQ/DQS : PASS
3744 09:58:17.446783 RX DATLAT : PASS
3745 09:58:17.450192 RX DQ/DQS(Engine): PASS
3746 09:58:17.450309 TX OE : NO K
3747 09:58:17.453619 All Pass.
3748 09:58:17.453707
3749 09:58:17.453773 CH 1, Rank 1
3750 09:58:17.456778 SW Impedance : PASS
3751 09:58:17.456865 DUTY Scan : NO K
3752 09:58:17.460542 ZQ Calibration : PASS
3753 09:58:17.463773 Jitter Meter : NO K
3754 09:58:17.463898 CBT Training : PASS
3755 09:58:17.466749 Write leveling : PASS
3756 09:58:17.470293 RX DQS gating : PASS
3757 09:58:17.470422 RX DQ/DQS(RDDQC) : PASS
3758 09:58:17.473378 TX DQ/DQS : PASS
3759 09:58:17.473512 RX DATLAT : PASS
3760 09:58:17.476805 RX DQ/DQS(Engine): PASS
3761 09:58:17.480044 TX OE : NO K
3762 09:58:17.480208 All Pass.
3763 09:58:17.480339
3764 09:58:17.483308 DramC Write-DBI off
3765 09:58:17.486634 PER_BANK_REFRESH: Hybrid Mode
3766 09:58:17.486762 TX_TRACKING: ON
3767 09:58:17.496269 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3768 09:58:17.499519 [FAST_K] Save calibration result to emmc
3769 09:58:17.503228 dramc_set_vcore_voltage set vcore to 650000
3770 09:58:17.506189 Read voltage for 600, 5
3771 09:58:17.506390 Vio18 = 0
3772 09:58:17.506516 Vcore = 650000
3773 09:58:17.509816 Vdram = 0
3774 09:58:17.509920 Vddq = 0
3775 09:58:17.510014 Vmddr = 0
3776 09:58:17.516411 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3777 09:58:17.519243 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3778 09:58:17.522494 MEM_TYPE=3, freq_sel=19
3779 09:58:17.525776 sv_algorithm_assistance_LP4_1600
3780 09:58:17.529534 ============ PULL DRAM RESETB DOWN ============
3781 09:58:17.532517 ========== PULL DRAM RESETB DOWN end =========
3782 09:58:17.539343 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3783 09:58:17.542267 ===================================
3784 09:58:17.542417 LPDDR4 DRAM CONFIGURATION
3785 09:58:17.546207 ===================================
3786 09:58:17.549206 EX_ROW_EN[0] = 0x0
3787 09:58:17.552559 EX_ROW_EN[1] = 0x0
3788 09:58:17.552660 LP4Y_EN = 0x0
3789 09:58:17.555985 WORK_FSP = 0x0
3790 09:58:17.556098 WL = 0x2
3791 09:58:17.559083 RL = 0x2
3792 09:58:17.559213 BL = 0x2
3793 09:58:17.562678 RPST = 0x0
3794 09:58:17.562773 RD_PRE = 0x0
3795 09:58:17.565900 WR_PRE = 0x1
3796 09:58:17.566019 WR_PST = 0x0
3797 09:58:17.569555 DBI_WR = 0x0
3798 09:58:17.569652 DBI_RD = 0x0
3799 09:58:17.572698 OTF = 0x1
3800 09:58:17.575729 ===================================
3801 09:58:17.579381 ===================================
3802 09:58:17.579484 ANA top config
3803 09:58:17.582236 ===================================
3804 09:58:17.585643 DLL_ASYNC_EN = 0
3805 09:58:17.588949 ALL_SLAVE_EN = 1
3806 09:58:17.592113 NEW_RANK_MODE = 1
3807 09:58:17.592253 DLL_IDLE_MODE = 1
3808 09:58:17.595524 LP45_APHY_COMB_EN = 1
3809 09:58:17.598637 TX_ODT_DIS = 1
3810 09:58:17.602239 NEW_8X_MODE = 1
3811 09:58:17.605474 ===================================
3812 09:58:17.609014 ===================================
3813 09:58:17.612249 data_rate = 1200
3814 09:58:17.615049 CKR = 1
3815 09:58:17.615173 DQ_P2S_RATIO = 8
3816 09:58:17.618119 ===================================
3817 09:58:17.621743 CA_P2S_RATIO = 8
3818 09:58:17.625458 DQ_CA_OPEN = 0
3819 09:58:17.628222 DQ_SEMI_OPEN = 0
3820 09:58:17.631623 CA_SEMI_OPEN = 0
3821 09:58:17.634989 CA_FULL_RATE = 0
3822 09:58:17.635124 DQ_CKDIV4_EN = 1
3823 09:58:17.637909 CA_CKDIV4_EN = 1
3824 09:58:17.641510 CA_PREDIV_EN = 0
3825 09:58:17.644558 PH8_DLY = 0
3826 09:58:17.647810 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3827 09:58:17.651309 DQ_AAMCK_DIV = 4
3828 09:58:17.651413 CA_AAMCK_DIV = 4
3829 09:58:17.654248 CA_ADMCK_DIV = 4
3830 09:58:17.657920 DQ_TRACK_CA_EN = 0
3831 09:58:17.660802 CA_PICK = 600
3832 09:58:17.664360 CA_MCKIO = 600
3833 09:58:17.667407 MCKIO_SEMI = 0
3834 09:58:17.671004 PLL_FREQ = 2288
3835 09:58:17.674123 DQ_UI_PI_RATIO = 32
3836 09:58:17.674223 CA_UI_PI_RATIO = 0
3837 09:58:17.677701 ===================================
3838 09:58:17.680851 ===================================
3839 09:58:17.683801 memory_type:LPDDR4
3840 09:58:17.687365 GP_NUM : 10
3841 09:58:17.687489 SRAM_EN : 1
3842 09:58:17.690464 MD32_EN : 0
3843 09:58:17.694013 ===================================
3844 09:58:17.696943 [ANA_INIT] >>>>>>>>>>>>>>
3845 09:58:17.700450 <<<<<< [CONFIGURE PHASE]: ANA_TX
3846 09:58:17.703415 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3847 09:58:17.706693 ===================================
3848 09:58:17.710414 data_rate = 1200,PCW = 0X5800
3849 09:58:17.713621 ===================================
3850 09:58:17.716786 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3851 09:58:17.719825 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3852 09:58:17.727091 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3853 09:58:17.730166 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3854 09:58:17.733544 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3855 09:58:17.736640 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3856 09:58:17.739967 [ANA_INIT] flow start
3857 09:58:17.743328 [ANA_INIT] PLL >>>>>>>>
3858 09:58:17.743421 [ANA_INIT] PLL <<<<<<<<
3859 09:58:17.746413 [ANA_INIT] MIDPI >>>>>>>>
3860 09:58:17.749444 [ANA_INIT] MIDPI <<<<<<<<
3861 09:58:17.753100 [ANA_INIT] DLL >>>>>>>>
3862 09:58:17.753209 [ANA_INIT] flow end
3863 09:58:17.755996 ============ LP4 DIFF to SE enter ============
3864 09:58:17.762691 ============ LP4 DIFF to SE exit ============
3865 09:58:17.762829 [ANA_INIT] <<<<<<<<<<<<<
3866 09:58:17.766245 [Flow] Enable top DCM control >>>>>
3867 09:58:17.769712 [Flow] Enable top DCM control <<<<<
3868 09:58:17.772762 Enable DLL master slave shuffle
3869 09:58:17.779523 ==============================================================
3870 09:58:17.779655 Gating Mode config
3871 09:58:17.786358 ==============================================================
3872 09:58:17.789284 Config description:
3873 09:58:17.799516 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3874 09:58:17.805581 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3875 09:58:17.809283 SELPH_MODE 0: By rank 1: By Phase
3876 09:58:17.815608 ==============================================================
3877 09:58:17.819042 GAT_TRACK_EN = 1
3878 09:58:17.822150 RX_GATING_MODE = 2
3879 09:58:17.822272 RX_GATING_TRACK_MODE = 2
3880 09:58:17.825438 SELPH_MODE = 1
3881 09:58:17.828830 PICG_EARLY_EN = 1
3882 09:58:17.832230 VALID_LAT_VALUE = 1
3883 09:58:17.838672 ==============================================================
3884 09:58:17.841746 Enter into Gating configuration >>>>
3885 09:58:17.845438 Exit from Gating configuration <<<<
3886 09:58:17.848241 Enter into DVFS_PRE_config >>>>>
3887 09:58:17.858407 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3888 09:58:17.861703 Exit from DVFS_PRE_config <<<<<
3889 09:58:17.864916 Enter into PICG configuration >>>>
3890 09:58:17.868686 Exit from PICG configuration <<<<
3891 09:58:17.871373 [RX_INPUT] configuration >>>>>
3892 09:58:17.874924 [RX_INPUT] configuration <<<<<
3893 09:58:17.878045 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3894 09:58:17.884776 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3895 09:58:17.891478 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3896 09:58:17.897876 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3897 09:58:17.904560 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3898 09:58:17.910675 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3899 09:58:17.913998 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3900 09:58:17.917568 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3901 09:58:17.920712 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3902 09:58:17.927554 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3903 09:58:17.930633 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3904 09:58:17.934003 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3905 09:58:17.937289 ===================================
3906 09:58:17.940540 LPDDR4 DRAM CONFIGURATION
3907 09:58:17.943987 ===================================
3908 09:58:17.944094 EX_ROW_EN[0] = 0x0
3909 09:58:17.947032 EX_ROW_EN[1] = 0x0
3910 09:58:17.950305 LP4Y_EN = 0x0
3911 09:58:17.950426 WORK_FSP = 0x0
3912 09:58:17.953914 WL = 0x2
3913 09:58:17.954006 RL = 0x2
3914 09:58:17.957013 BL = 0x2
3915 09:58:17.957122 RPST = 0x0
3916 09:58:17.960129 RD_PRE = 0x0
3917 09:58:17.960242 WR_PRE = 0x1
3918 09:58:17.963832 WR_PST = 0x0
3919 09:58:17.963951 DBI_WR = 0x0
3920 09:58:17.967264 DBI_RD = 0x0
3921 09:58:17.967377 OTF = 0x1
3922 09:58:17.970566 ===================================
3923 09:58:17.973534 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3924 09:58:17.980222 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3925 09:58:17.983803 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3926 09:58:17.986885 ===================================
3927 09:58:17.989953 LPDDR4 DRAM CONFIGURATION
3928 09:58:17.993607 ===================================
3929 09:58:17.993731 EX_ROW_EN[0] = 0x10
3930 09:58:17.996692 EX_ROW_EN[1] = 0x0
3931 09:58:17.996808 LP4Y_EN = 0x0
3932 09:58:18.000484 WORK_FSP = 0x0
3933 09:58:18.003276 WL = 0x2
3934 09:58:18.003373 RL = 0x2
3935 09:58:18.006884 BL = 0x2
3936 09:58:18.006966 RPST = 0x0
3937 09:58:18.009879 RD_PRE = 0x0
3938 09:58:18.009976 WR_PRE = 0x1
3939 09:58:18.013559 WR_PST = 0x0
3940 09:58:18.013667 DBI_WR = 0x0
3941 09:58:18.016732 DBI_RD = 0x0
3942 09:58:18.016821 OTF = 0x1
3943 09:58:18.020474 ===================================
3944 09:58:18.026552 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3945 09:58:18.030850 nWR fixed to 30
3946 09:58:18.033988 [ModeRegInit_LP4] CH0 RK0
3947 09:58:18.034091 [ModeRegInit_LP4] CH0 RK1
3948 09:58:18.037329 [ModeRegInit_LP4] CH1 RK0
3949 09:58:18.040691 [ModeRegInit_LP4] CH1 RK1
3950 09:58:18.040786 match AC timing 17
3951 09:58:18.047467 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3952 09:58:18.050634 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3953 09:58:18.053815 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3954 09:58:18.060307 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3955 09:58:18.063534 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3956 09:58:18.063684 ==
3957 09:58:18.067328 Dram Type= 6, Freq= 0, CH_0, rank 0
3958 09:58:18.070034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3959 09:58:18.070160 ==
3960 09:58:18.077022 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3961 09:58:18.083038 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3962 09:58:18.086585 [CA 0] Center 36 (6~66) winsize 61
3963 09:58:18.089705 [CA 1] Center 36 (6~66) winsize 61
3964 09:58:18.092957 [CA 2] Center 34 (3~65) winsize 63
3965 09:58:18.096617 [CA 3] Center 34 (3~65) winsize 63
3966 09:58:18.099582 [CA 4] Center 33 (3~64) winsize 62
3967 09:58:18.103173 [CA 5] Center 33 (3~64) winsize 62
3968 09:58:18.103288
3969 09:58:18.106435 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3970 09:58:18.106575
3971 09:58:18.109291 [CATrainingPosCal] consider 1 rank data
3972 09:58:18.113026 u2DelayCellTimex100 = 270/100 ps
3973 09:58:18.116131 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3974 09:58:18.119209 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3975 09:58:18.125854 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
3976 09:58:18.129070 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3977 09:58:18.132670 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3978 09:58:18.135605 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3979 09:58:18.135725
3980 09:58:18.139362 CA PerBit enable=1, Macro0, CA PI delay=33
3981 09:58:18.139532
3982 09:58:18.142095 [CBTSetCACLKResult] CA Dly = 33
3983 09:58:18.142202 CS Dly: 5 (0~36)
3984 09:58:18.145520 ==
3985 09:58:18.148840 Dram Type= 6, Freq= 0, CH_0, rank 1
3986 09:58:18.152173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3987 09:58:18.152285 ==
3988 09:58:18.158865 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3989 09:58:18.162304 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3990 09:58:18.166315 [CA 0] Center 35 (5~66) winsize 62
3991 09:58:18.169482 [CA 1] Center 36 (6~66) winsize 61
3992 09:58:18.172644 [CA 2] Center 33 (3~64) winsize 62
3993 09:58:18.175958 [CA 3] Center 34 (4~64) winsize 61
3994 09:58:18.179299 [CA 4] Center 33 (3~64) winsize 62
3995 09:58:18.182379 [CA 5] Center 33 (2~64) winsize 63
3996 09:58:18.182474
3997 09:58:18.185960 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3998 09:58:18.186089
3999 09:58:18.189303 [CATrainingPosCal] consider 2 rank data
4000 09:58:18.192106 u2DelayCellTimex100 = 270/100 ps
4001 09:58:18.195921 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4002 09:58:18.202509 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4003 09:58:18.206020 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4004 09:58:18.209206 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4005 09:58:18.212171 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4006 09:58:18.215492 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4007 09:58:18.215624
4008 09:58:18.219019 CA PerBit enable=1, Macro0, CA PI delay=33
4009 09:58:18.219115
4010 09:58:18.222117 [CBTSetCACLKResult] CA Dly = 33
4011 09:58:18.225673 CS Dly: 6 (0~38)
4012 09:58:18.225790
4013 09:58:18.228865 ----->DramcWriteLeveling(PI) begin...
4014 09:58:18.228966 ==
4015 09:58:18.232356 Dram Type= 6, Freq= 0, CH_0, rank 0
4016 09:58:18.235472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4017 09:58:18.235594 ==
4018 09:58:18.239100 Write leveling (Byte 0): 32 => 32
4019 09:58:18.242275 Write leveling (Byte 1): 29 => 29
4020 09:58:18.245130 DramcWriteLeveling(PI) end<-----
4021 09:58:18.245274
4022 09:58:18.245375 ==
4023 09:58:18.248581 Dram Type= 6, Freq= 0, CH_0, rank 0
4024 09:58:18.252114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4025 09:58:18.252242 ==
4026 09:58:18.255686 [Gating] SW mode calibration
4027 09:58:18.261799 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4028 09:58:18.268194 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4029 09:58:18.271902 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4030 09:58:18.274892 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4031 09:58:18.281586 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4032 09:58:18.284980 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4033 09:58:18.288560 0 9 16 | B1->B0 | 2f2f 2b2b | 0 0 | (1 1) (1 1)
4034 09:58:18.295143 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4035 09:58:18.298145 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4036 09:58:18.301633 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 09:58:18.308382 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 09:58:18.311384 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 09:58:18.314906 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4040 09:58:18.321101 0 10 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4041 09:58:18.324738 0 10 16 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
4042 09:58:18.327938 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 09:58:18.334595 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 09:58:18.337790 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 09:58:18.341451 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 09:58:18.347424 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 09:58:18.351173 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 09:58:18.354157 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 09:58:18.361084 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4050 09:58:18.364033 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 09:58:18.367737 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 09:58:18.374271 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 09:58:18.377439 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 09:58:18.381038 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 09:58:18.387536 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 09:58:18.390525 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 09:58:18.394275 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 09:58:18.400593 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 09:58:18.404090 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 09:58:18.407171 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 09:58:18.413786 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 09:58:18.417287 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 09:58:18.420412 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 09:58:18.427310 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4065 09:58:18.430375 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4066 09:58:18.433252 Total UI for P1: 0, mck2ui 16
4067 09:58:18.437115 best dqsien dly found for B0: ( 0, 13, 12)
4068 09:58:18.439973 Total UI for P1: 0, mck2ui 16
4069 09:58:18.443673 best dqsien dly found for B1: ( 0, 13, 14)
4070 09:58:18.446735 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4071 09:58:18.449977 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4072 09:58:18.450087
4073 09:58:18.453533 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4074 09:58:18.456489 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4075 09:58:18.459916 [Gating] SW calibration Done
4076 09:58:18.460042 ==
4077 09:58:18.463313 Dram Type= 6, Freq= 0, CH_0, rank 0
4078 09:58:18.466503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4079 09:58:18.470117 ==
4080 09:58:18.470243 RX Vref Scan: 0
4081 09:58:18.470342
4082 09:58:18.473440 RX Vref 0 -> 0, step: 1
4083 09:58:18.473529
4084 09:58:18.476245 RX Delay -230 -> 252, step: 16
4085 09:58:18.479743 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4086 09:58:18.482808 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4087 09:58:18.486249 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4088 09:58:18.492743 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4089 09:58:18.496040 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4090 09:58:18.499263 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4091 09:58:18.502835 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4092 09:58:18.509140 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4093 09:58:18.512781 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4094 09:58:18.515535 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4095 09:58:18.518941 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4096 09:58:18.525567 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4097 09:58:18.529208 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4098 09:58:18.532280 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4099 09:58:18.535360 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4100 09:58:18.542081 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4101 09:58:18.542234 ==
4102 09:58:18.545100 Dram Type= 6, Freq= 0, CH_0, rank 0
4103 09:58:18.548746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4104 09:58:18.548874 ==
4105 09:58:18.548989 DQS Delay:
4106 09:58:18.551843 DQS0 = 0, DQS1 = 0
4107 09:58:18.551957 DQM Delay:
4108 09:58:18.555018 DQM0 = 43, DQM1 = 28
4109 09:58:18.555139 DQ Delay:
4110 09:58:18.558413 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4111 09:58:18.562073 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4112 09:58:18.564847 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4113 09:58:18.568267 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4114 09:58:18.568396
4115 09:58:18.568504
4116 09:58:18.568603 ==
4117 09:58:18.572029 Dram Type= 6, Freq= 0, CH_0, rank 0
4118 09:58:18.575003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4119 09:58:18.578257 ==
4120 09:58:18.578344
4121 09:58:18.578409
4122 09:58:18.578470 TX Vref Scan disable
4123 09:58:18.581961 == TX Byte 0 ==
4124 09:58:18.584787 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4125 09:58:18.588200 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4126 09:58:18.591440 == TX Byte 1 ==
4127 09:58:18.594870 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4128 09:58:18.598359 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4129 09:58:18.601709 ==
4130 09:58:18.605111 Dram Type= 6, Freq= 0, CH_0, rank 0
4131 09:58:18.608199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4132 09:58:18.608337 ==
4133 09:58:18.608433
4134 09:58:18.608532
4135 09:58:18.611872 TX Vref Scan disable
4136 09:58:18.611983 == TX Byte 0 ==
4137 09:58:18.617919 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4138 09:58:18.621112 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4139 09:58:18.624529 == TX Byte 1 ==
4140 09:58:18.627783 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4141 09:58:18.630960 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4142 09:58:18.631082
4143 09:58:18.631254 [DATLAT]
4144 09:58:18.634486 Freq=600, CH0 RK0
4145 09:58:18.634605
4146 09:58:18.637642 DATLAT Default: 0x9
4147 09:58:18.637760 0, 0xFFFF, sum = 0
4148 09:58:18.640833 1, 0xFFFF, sum = 0
4149 09:58:18.640956 2, 0xFFFF, sum = 0
4150 09:58:18.644448 3, 0xFFFF, sum = 0
4151 09:58:18.644565 4, 0xFFFF, sum = 0
4152 09:58:18.647619 5, 0xFFFF, sum = 0
4153 09:58:18.647740 6, 0xFFFF, sum = 0
4154 09:58:18.650694 7, 0xFFFF, sum = 0
4155 09:58:18.650825 8, 0x0, sum = 1
4156 09:58:18.654267 9, 0x0, sum = 2
4157 09:58:18.654407 10, 0x0, sum = 3
4158 09:58:18.657385 11, 0x0, sum = 4
4159 09:58:18.657520 best_step = 9
4160 09:58:18.657620
4161 09:58:18.657712 ==
4162 09:58:18.660464 Dram Type= 6, Freq= 0, CH_0, rank 0
4163 09:58:18.664117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4164 09:58:18.664246 ==
4165 09:58:18.667216 RX Vref Scan: 1
4166 09:58:18.667354
4167 09:58:18.670846 RX Vref 0 -> 0, step: 1
4168 09:58:18.670985
4169 09:58:18.671084 RX Delay -195 -> 252, step: 8
4170 09:58:18.671175
4171 09:58:18.673666 Set Vref, RX VrefLevel [Byte0]: 55
4172 09:58:18.677213 [Byte1]: 48
4173 09:58:18.682012
4174 09:58:18.682159 Final RX Vref Byte 0 = 55 to rank0
4175 09:58:18.685710 Final RX Vref Byte 1 = 48 to rank0
4176 09:58:18.688814 Final RX Vref Byte 0 = 55 to rank1
4177 09:58:18.692037 Final RX Vref Byte 1 = 48 to rank1==
4178 09:58:18.695609 Dram Type= 6, Freq= 0, CH_0, rank 0
4179 09:58:18.701761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4180 09:58:18.701919 ==
4181 09:58:18.702024 DQS Delay:
4182 09:58:18.702121 DQS0 = 0, DQS1 = 0
4183 09:58:18.705285 DQM Delay:
4184 09:58:18.705435 DQM0 = 44, DQM1 = 33
4185 09:58:18.708528 DQ Delay:
4186 09:58:18.711667 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =44
4187 09:58:18.715111 DQ4 =44, DQ5 =36, DQ6 =52, DQ7 =52
4188 09:58:18.718267 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4189 09:58:18.721814 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4190 09:58:18.721920
4191 09:58:18.721989
4192 09:58:18.727955 [DQSOSCAuto] RK0, (LSB)MR18= 0x683f, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 390 ps
4193 09:58:18.731430 CH0 RK0: MR19=808, MR18=683F
4194 09:58:18.738306 CH0_RK0: MR19=0x808, MR18=0x683F, DQSOSC=390, MR23=63, INC=172, DEC=114
4195 09:58:18.738460
4196 09:58:18.741503 ----->DramcWriteLeveling(PI) begin...
4197 09:58:18.741617 ==
4198 09:58:18.744657 Dram Type= 6, Freq= 0, CH_0, rank 1
4199 09:58:18.747772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4200 09:58:18.747895 ==
4201 09:58:18.751312 Write leveling (Byte 0): 34 => 34
4202 09:58:18.754427 Write leveling (Byte 1): 29 => 29
4203 09:58:18.757949 DramcWriteLeveling(PI) end<-----
4204 09:58:18.758070
4205 09:58:18.758170 ==
4206 09:58:18.761093 Dram Type= 6, Freq= 0, CH_0, rank 1
4207 09:58:18.764808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4208 09:58:18.767719 ==
4209 09:58:18.767834 [Gating] SW mode calibration
4210 09:58:18.777361 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4211 09:58:18.780977 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4212 09:58:18.784604 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4213 09:58:18.790834 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4214 09:58:18.794323 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4215 09:58:18.797395 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (0 0) (0 1)
4216 09:58:18.804036 0 9 16 | B1->B0 | 2f2f 2828 | 1 1 | (1 0) (0 0)
4217 09:58:18.807263 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4218 09:58:18.810253 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4219 09:58:18.817192 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4220 09:58:18.820407 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4221 09:58:18.823706 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4222 09:58:18.830181 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 09:58:18.833557 0 10 12 | B1->B0 | 2525 2828 | 0 0 | (0 0) (0 0)
4224 09:58:18.836990 0 10 16 | B1->B0 | 3a3a 4545 | 1 0 | (0 0) (0 0)
4225 09:58:18.843481 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4226 09:58:18.846485 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 09:58:18.850030 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 09:58:18.856702 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 09:58:18.859676 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 09:58:18.863254 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 09:58:18.869527 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4232 09:58:18.873183 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 09:58:18.876194 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 09:58:18.882848 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 09:58:18.886343 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 09:58:18.889326 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 09:58:18.895986 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 09:58:18.899130 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 09:58:18.902709 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 09:58:18.909306 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 09:58:18.912236 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 09:58:18.915588 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 09:58:18.922220 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 09:58:18.925765 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 09:58:18.928666 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 09:58:18.935584 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 09:58:18.938852 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 09:58:18.942116 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 09:58:18.945451 Total UI for P1: 0, mck2ui 16
4250 09:58:18.948563 best dqsien dly found for B0: ( 0, 13, 14)
4251 09:58:18.952227 Total UI for P1: 0, mck2ui 16
4252 09:58:18.955318 best dqsien dly found for B1: ( 0, 13, 14)
4253 09:58:18.958793 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4254 09:58:18.965554 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4255 09:58:18.965708
4256 09:58:18.968473 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4257 09:58:18.971435 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4258 09:58:18.975174 [Gating] SW calibration Done
4259 09:58:18.975269 ==
4260 09:58:18.978375 Dram Type= 6, Freq= 0, CH_0, rank 1
4261 09:58:18.981587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4262 09:58:18.981688 ==
4263 09:58:18.985164 RX Vref Scan: 0
4264 09:58:18.985257
4265 09:58:18.985323 RX Vref 0 -> 0, step: 1
4266 09:58:18.985383
4267 09:58:18.988340 RX Delay -230 -> 252, step: 16
4268 09:58:18.994388 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4269 09:58:18.998046 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4270 09:58:19.001256 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4271 09:58:19.004873 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4272 09:58:19.007833 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4273 09:58:19.014479 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4274 09:58:19.018046 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4275 09:58:19.020854 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4276 09:58:19.024345 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4277 09:58:19.030849 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4278 09:58:19.034280 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4279 09:58:19.037393 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4280 09:58:19.040796 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4281 09:58:19.047181 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4282 09:58:19.050720 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4283 09:58:19.053739 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4284 09:58:19.053836 ==
4285 09:58:19.057122 Dram Type= 6, Freq= 0, CH_0, rank 1
4286 09:58:19.060625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4287 09:58:19.063577 ==
4288 09:58:19.063671 DQS Delay:
4289 09:58:19.063737 DQS0 = 0, DQS1 = 0
4290 09:58:19.067278 DQM Delay:
4291 09:58:19.067392 DQM0 = 41, DQM1 = 34
4292 09:58:19.070247 DQ Delay:
4293 09:58:19.073728 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4294 09:58:19.073844 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4295 09:58:19.077012 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4296 09:58:19.080504 DQ12 =33, DQ13 =49, DQ14 =49, DQ15 =33
4297 09:58:19.083612
4298 09:58:19.083709
4299 09:58:19.083781 ==
4300 09:58:19.087097 Dram Type= 6, Freq= 0, CH_0, rank 1
4301 09:58:19.090361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4302 09:58:19.090455 ==
4303 09:58:19.090523
4304 09:58:19.090586
4305 09:58:19.093323 TX Vref Scan disable
4306 09:58:19.093444 == TX Byte 0 ==
4307 09:58:19.100399 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4308 09:58:19.103752 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4309 09:58:19.103899 == TX Byte 1 ==
4310 09:58:19.109813 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4311 09:58:19.113689 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4312 09:58:19.113793 ==
4313 09:58:19.116567 Dram Type= 6, Freq= 0, CH_0, rank 1
4314 09:58:19.120288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4315 09:58:19.120380 ==
4316 09:58:19.120445
4317 09:58:19.120504
4318 09:58:19.123333 TX Vref Scan disable
4319 09:58:19.127165 == TX Byte 0 ==
4320 09:58:19.130261 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4321 09:58:19.136493 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4322 09:58:19.136623 == TX Byte 1 ==
4323 09:58:19.140018 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4324 09:58:19.146550 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4325 09:58:19.146677
4326 09:58:19.146744 [DATLAT]
4327 09:58:19.146817 Freq=600, CH0 RK1
4328 09:58:19.146880
4329 09:58:19.149922 DATLAT Default: 0x9
4330 09:58:19.150002 0, 0xFFFF, sum = 0
4331 09:58:19.153501 1, 0xFFFF, sum = 0
4332 09:58:19.156459 2, 0xFFFF, sum = 0
4333 09:58:19.156585 3, 0xFFFF, sum = 0
4334 09:58:19.159436 4, 0xFFFF, sum = 0
4335 09:58:19.159555 5, 0xFFFF, sum = 0
4336 09:58:19.163264 6, 0xFFFF, sum = 0
4337 09:58:19.163385 7, 0xFFFF, sum = 0
4338 09:58:19.165947 8, 0x0, sum = 1
4339 09:58:19.166062 9, 0x0, sum = 2
4340 09:58:19.169491 10, 0x0, sum = 3
4341 09:58:19.169585 11, 0x0, sum = 4
4342 09:58:19.169663 best_step = 9
4343 09:58:19.169725
4344 09:58:19.172711 ==
4345 09:58:19.176147 Dram Type= 6, Freq= 0, CH_0, rank 1
4346 09:58:19.179191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4347 09:58:19.179285 ==
4348 09:58:19.179349 RX Vref Scan: 0
4349 09:58:19.179408
4350 09:58:19.182658 RX Vref 0 -> 0, step: 1
4351 09:58:19.182776
4352 09:58:19.186010 RX Delay -179 -> 252, step: 8
4353 09:58:19.192738 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4354 09:58:19.195773 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4355 09:58:19.199396 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4356 09:58:19.202481 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4357 09:58:19.205647 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4358 09:58:19.212534 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4359 09:58:19.215586 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4360 09:58:19.219058 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4361 09:58:19.222238 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4362 09:58:19.228850 iDelay=205, Bit 9, Center 24 (-123 ~ 172) 296
4363 09:58:19.232033 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4364 09:58:19.235688 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4365 09:58:19.238991 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4366 09:58:19.245556 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4367 09:58:19.248812 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4368 09:58:19.251856 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4369 09:58:19.251984 ==
4370 09:58:19.255247 Dram Type= 6, Freq= 0, CH_0, rank 1
4371 09:58:19.258802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4372 09:58:19.258957 ==
4373 09:58:19.262246 DQS Delay:
4374 09:58:19.262376 DQS0 = 0, DQS1 = 0
4375 09:58:19.265371 DQM Delay:
4376 09:58:19.265527 DQM0 = 42, DQM1 = 37
4377 09:58:19.265633 DQ Delay:
4378 09:58:19.268780 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4379 09:58:19.271607 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4380 09:58:19.275005 DQ8 =28, DQ9 =24, DQ10 =40, DQ11 =28
4381 09:58:19.278792 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4382 09:58:19.278921
4383 09:58:19.278995
4384 09:58:19.288579 [DQSOSCAuto] RK1, (LSB)MR18= 0x6113, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 391 ps
4385 09:58:19.291445 CH0 RK1: MR19=808, MR18=6113
4386 09:58:19.298209 CH0_RK1: MR19=0x808, MR18=0x6113, DQSOSC=391, MR23=63, INC=171, DEC=114
4387 09:58:19.301742 [RxdqsGatingPostProcess] freq 600
4388 09:58:19.304731 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4389 09:58:19.308381 Pre-setting of DQS Precalculation
4390 09:58:19.314474 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4391 09:58:19.314652 ==
4392 09:58:19.318073 Dram Type= 6, Freq= 0, CH_1, rank 0
4393 09:58:19.321317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4394 09:58:19.321472 ==
4395 09:58:19.327991 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4396 09:58:19.331351 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4397 09:58:19.335379 [CA 0] Center 35 (5~66) winsize 62
4398 09:58:19.338403 [CA 1] Center 35 (5~66) winsize 62
4399 09:58:19.342228 [CA 2] Center 34 (4~65) winsize 62
4400 09:58:19.345161 [CA 3] Center 33 (3~64) winsize 62
4401 09:58:19.348584 [CA 4] Center 34 (4~64) winsize 61
4402 09:58:19.351427 [CA 5] Center 33 (3~64) winsize 62
4403 09:58:19.351554
4404 09:58:19.355150 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4405 09:58:19.355287
4406 09:58:19.361326 [CATrainingPosCal] consider 1 rank data
4407 09:58:19.361493 u2DelayCellTimex100 = 270/100 ps
4408 09:58:19.368109 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4409 09:58:19.371492 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4410 09:58:19.375007 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4411 09:58:19.377914 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4412 09:58:19.381399 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4413 09:58:19.384691 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4414 09:58:19.384805
4415 09:58:19.387814 CA PerBit enable=1, Macro0, CA PI delay=33
4416 09:58:19.387923
4417 09:58:19.391530 [CBTSetCACLKResult] CA Dly = 33
4418 09:58:19.394426 CS Dly: 4 (0~35)
4419 09:58:19.394520 ==
4420 09:58:19.397852 Dram Type= 6, Freq= 0, CH_1, rank 1
4421 09:58:19.401341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4422 09:58:19.401472 ==
4423 09:58:19.407886 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4424 09:58:19.410930 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4425 09:58:19.415666 [CA 0] Center 35 (5~66) winsize 62
4426 09:58:19.418512 [CA 1] Center 36 (6~66) winsize 61
4427 09:58:19.421811 [CA 2] Center 34 (4~65) winsize 62
4428 09:58:19.425382 [CA 3] Center 34 (3~65) winsize 63
4429 09:58:19.428380 [CA 4] Center 34 (4~65) winsize 62
4430 09:58:19.432279 [CA 5] Center 34 (3~65) winsize 63
4431 09:58:19.432397
4432 09:58:19.435323 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4433 09:58:19.435420
4434 09:58:19.439060 [CATrainingPosCal] consider 2 rank data
4435 09:58:19.442010 u2DelayCellTimex100 = 270/100 ps
4436 09:58:19.445465 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4437 09:58:19.451782 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4438 09:58:19.455245 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4439 09:58:19.458326 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4440 09:58:19.461675 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4441 09:58:19.464933 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4442 09:58:19.465073
4443 09:58:19.468020 CA PerBit enable=1, Macro0, CA PI delay=33
4444 09:58:19.468135
4445 09:58:19.471394 [CBTSetCACLKResult] CA Dly = 33
4446 09:58:19.474812 CS Dly: 4 (0~36)
4447 09:58:19.474919
4448 09:58:19.478009 ----->DramcWriteLeveling(PI) begin...
4449 09:58:19.478108 ==
4450 09:58:19.481301 Dram Type= 6, Freq= 0, CH_1, rank 0
4451 09:58:19.485063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4452 09:58:19.485204 ==
4453 09:58:19.487930 Write leveling (Byte 0): 30 => 30
4454 09:58:19.491217 Write leveling (Byte 1): 31 => 31
4455 09:58:19.494551 DramcWriteLeveling(PI) end<-----
4456 09:58:19.494689
4457 09:58:19.494786 ==
4458 09:58:19.497585 Dram Type= 6, Freq= 0, CH_1, rank 0
4459 09:58:19.501144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4460 09:58:19.501266 ==
4461 09:58:19.504678 [Gating] SW mode calibration
4462 09:58:19.510950 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4463 09:58:19.517492 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4464 09:58:19.521212 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4465 09:58:19.524318 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4466 09:58:19.530956 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4467 09:58:19.534631 0 9 12 | B1->B0 | 3030 2c2c | 0 1 | (0 1) (1 0)
4468 09:58:19.537806 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4469 09:58:19.544423 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4470 09:58:19.547632 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4471 09:58:19.550703 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 09:58:19.557278 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 09:58:19.560348 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 09:58:19.564171 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4475 09:58:19.570617 0 10 12 | B1->B0 | 2c2c 3b3b | 0 1 | (0 0) (0 0)
4476 09:58:19.573719 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 09:58:19.576708 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4478 09:58:19.583764 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 09:58:19.586560 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 09:58:19.590392 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 09:58:19.596972 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 09:58:19.599884 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 09:58:19.603499 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4484 09:58:19.609705 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 09:58:19.613341 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 09:58:19.616344 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 09:58:19.623054 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 09:58:19.626569 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 09:58:19.629611 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 09:58:19.636098 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 09:58:19.639395 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 09:58:19.642549 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 09:58:19.649198 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 09:58:19.652784 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 09:58:19.655869 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 09:58:19.662288 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 09:58:19.665787 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 09:58:19.668871 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4499 09:58:19.675511 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4500 09:58:19.678886 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 09:58:19.682379 Total UI for P1: 0, mck2ui 16
4502 09:58:19.685718 best dqsien dly found for B0: ( 0, 13, 10)
4503 09:58:19.688832 Total UI for P1: 0, mck2ui 16
4504 09:58:19.692355 best dqsien dly found for B1: ( 0, 13, 14)
4505 09:58:19.695693 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4506 09:58:19.699050 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4507 09:58:19.699173
4508 09:58:19.702120 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4509 09:58:19.708582 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4510 09:58:19.708719 [Gating] SW calibration Done
4511 09:58:19.708795 ==
4512 09:58:19.712187 Dram Type= 6, Freq= 0, CH_1, rank 0
4513 09:58:19.718931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4514 09:58:19.719094 ==
4515 09:58:19.719193 RX Vref Scan: 0
4516 09:58:19.719283
4517 09:58:19.721887 RX Vref 0 -> 0, step: 1
4518 09:58:19.721984
4519 09:58:19.725474 RX Delay -230 -> 252, step: 16
4520 09:58:19.728655 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4521 09:58:19.732514 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4522 09:58:19.738407 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4523 09:58:19.742083 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4524 09:58:19.745033 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4525 09:58:19.748214 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4526 09:58:19.751501 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4527 09:58:19.758136 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4528 09:58:19.761231 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4529 09:58:19.764931 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4530 09:58:19.768062 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4531 09:58:19.774764 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4532 09:58:19.778031 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4533 09:58:19.781485 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4534 09:58:19.784628 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4535 09:58:19.791352 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4536 09:58:19.791483 ==
4537 09:58:19.794811 Dram Type= 6, Freq= 0, CH_1, rank 0
4538 09:58:19.797927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4539 09:58:19.798040 ==
4540 09:58:19.798116 DQS Delay:
4541 09:58:19.800831 DQS0 = 0, DQS1 = 0
4542 09:58:19.800943 DQM Delay:
4543 09:58:19.804137 DQM0 = 45, DQM1 = 38
4544 09:58:19.804241 DQ Delay:
4545 09:58:19.807471 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4546 09:58:19.811013 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4547 09:58:19.814297 DQ8 =25, DQ9 =33, DQ10 =33, DQ11 =25
4548 09:58:19.817604 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4549 09:58:19.817691
4550 09:58:19.817766
4551 09:58:19.817827 ==
4552 09:58:19.820660 Dram Type= 6, Freq= 0, CH_1, rank 0
4553 09:58:19.827090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4554 09:58:19.827209 ==
4555 09:58:19.827294
4556 09:58:19.827362
4557 09:58:19.827422 TX Vref Scan disable
4558 09:58:19.831002 == TX Byte 0 ==
4559 09:58:19.833945 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4560 09:58:19.840624 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4561 09:58:19.840741 == TX Byte 1 ==
4562 09:58:19.844183 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4563 09:58:19.850389 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4564 09:58:19.850519 ==
4565 09:58:19.853837 Dram Type= 6, Freq= 0, CH_1, rank 0
4566 09:58:19.856896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4567 09:58:19.857035 ==
4568 09:58:19.857120
4569 09:58:19.857184
4570 09:58:19.860260 TX Vref Scan disable
4571 09:58:19.863488 == TX Byte 0 ==
4572 09:58:19.867238 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4573 09:58:19.869982 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4574 09:58:19.873603 == TX Byte 1 ==
4575 09:58:19.876790 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4576 09:58:19.879885 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4577 09:58:19.879990
4578 09:58:19.883312 [DATLAT]
4579 09:58:19.883410 Freq=600, CH1 RK0
4580 09:58:19.883485
4581 09:58:19.886447 DATLAT Default: 0x9
4582 09:58:19.886531 0, 0xFFFF, sum = 0
4583 09:58:19.889862 1, 0xFFFF, sum = 0
4584 09:58:19.889952 2, 0xFFFF, sum = 0
4585 09:58:19.893569 3, 0xFFFF, sum = 0
4586 09:58:19.893671 4, 0xFFFF, sum = 0
4587 09:58:19.896349 5, 0xFFFF, sum = 0
4588 09:58:19.896478 6, 0xFFFF, sum = 0
4589 09:58:19.899682 7, 0xFFFF, sum = 0
4590 09:58:19.899780 8, 0x0, sum = 1
4591 09:58:19.902795 9, 0x0, sum = 2
4592 09:58:19.902883 10, 0x0, sum = 3
4593 09:58:19.906158 11, 0x0, sum = 4
4594 09:58:19.906254 best_step = 9
4595 09:58:19.906339
4596 09:58:19.906422 ==
4597 09:58:19.909928 Dram Type= 6, Freq= 0, CH_1, rank 0
4598 09:58:19.912836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4599 09:58:19.916280 ==
4600 09:58:19.916386 RX Vref Scan: 1
4601 09:58:19.916474
4602 09:58:19.919819 RX Vref 0 -> 0, step: 1
4603 09:58:19.919914
4604 09:58:19.922650 RX Delay -179 -> 252, step: 8
4605 09:58:19.922776
4606 09:58:19.926116 Set Vref, RX VrefLevel [Byte0]: 51
4607 09:58:19.929268 [Byte1]: 53
4608 09:58:19.929372
4609 09:58:19.932794 Final RX Vref Byte 0 = 51 to rank0
4610 09:58:19.935993 Final RX Vref Byte 1 = 53 to rank0
4611 09:58:19.939248 Final RX Vref Byte 0 = 51 to rank1
4612 09:58:19.942673 Final RX Vref Byte 1 = 53 to rank1==
4613 09:58:19.945669 Dram Type= 6, Freq= 0, CH_1, rank 0
4614 09:58:19.948894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4615 09:58:19.948998 ==
4616 09:58:19.952286 DQS Delay:
4617 09:58:19.952397 DQS0 = 0, DQS1 = 0
4618 09:58:19.952491 DQM Delay:
4619 09:58:19.955291 DQM0 = 47, DQM1 = 38
4620 09:58:19.955398 DQ Delay:
4621 09:58:19.959089 DQ0 =52, DQ1 =44, DQ2 =40, DQ3 =44
4622 09:58:19.962089 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4623 09:58:19.965158 DQ8 =28, DQ9 =24, DQ10 =40, DQ11 =28
4624 09:58:19.968621 DQ12 =48, DQ13 =40, DQ14 =48, DQ15 =48
4625 09:58:19.968723
4626 09:58:19.968819
4627 09:58:19.979061 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e34, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4628 09:58:19.982047 CH1 RK0: MR19=808, MR18=4E34
4629 09:58:19.988569 CH1_RK0: MR19=0x808, MR18=0x4E34, DQSOSC=395, MR23=63, INC=168, DEC=112
4630 09:58:19.988729
4631 09:58:19.991681 ----->DramcWriteLeveling(PI) begin...
4632 09:58:19.991806 ==
4633 09:58:19.994825 Dram Type= 6, Freq= 0, CH_1, rank 1
4634 09:58:19.998391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4635 09:58:19.998495 ==
4636 09:58:20.001524 Write leveling (Byte 0): 30 => 30
4637 09:58:20.004904 Write leveling (Byte 1): 33 => 33
4638 09:58:20.008023 DramcWriteLeveling(PI) end<-----
4639 09:58:20.008138
4640 09:58:20.008231 ==
4641 09:58:20.011424 Dram Type= 6, Freq= 0, CH_1, rank 1
4642 09:58:20.014630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4643 09:58:20.014724 ==
4644 09:58:20.018182 [Gating] SW mode calibration
4645 09:58:20.024285 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4646 09:58:20.031004 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4647 09:58:20.034544 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4648 09:58:20.037666 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4649 09:58:20.044134 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4650 09:58:20.047444 0 9 12 | B1->B0 | 3131 3333 | 0 1 | (0 0) (1 1)
4651 09:58:20.050776 0 9 16 | B1->B0 | 2424 2727 | 0 0 | (0 0) (0 0)
4652 09:58:20.057298 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4653 09:58:20.061069 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4654 09:58:20.063938 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4655 09:58:20.070675 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4656 09:58:20.073811 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4657 09:58:20.077405 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4658 09:58:20.084008 0 10 12 | B1->B0 | 3232 2727 | 0 1 | (1 1) (0 0)
4659 09:58:20.087104 0 10 16 | B1->B0 | 4545 3f3f | 0 1 | (0 0) (0 0)
4660 09:58:20.090268 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4661 09:58:20.096874 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4662 09:58:20.100411 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4663 09:58:20.103424 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 09:58:20.110325 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4665 09:58:20.113534 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4666 09:58:20.116733 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4667 09:58:20.123735 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 09:58:20.126792 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 09:58:20.130242 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 09:58:20.136813 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 09:58:20.140129 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 09:58:20.143118 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 09:58:20.149844 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 09:58:20.153243 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 09:58:20.156852 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 09:58:20.163331 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 09:58:20.166456 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 09:58:20.170111 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 09:58:20.176744 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 09:58:20.179721 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 09:58:20.182985 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 09:58:20.190221 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4683 09:58:20.193157 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 09:58:20.196678 Total UI for P1: 0, mck2ui 16
4685 09:58:20.199752 best dqsien dly found for B0: ( 0, 13, 12)
4686 09:58:20.202735 Total UI for P1: 0, mck2ui 16
4687 09:58:20.206612 best dqsien dly found for B1: ( 0, 13, 12)
4688 09:58:20.209507 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4689 09:58:20.213181 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4690 09:58:20.213322
4691 09:58:20.216301 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4692 09:58:20.219845 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4693 09:58:20.222691 [Gating] SW calibration Done
4694 09:58:20.222790 ==
4695 09:58:20.226016 Dram Type= 6, Freq= 0, CH_1, rank 1
4696 09:58:20.229130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4697 09:58:20.232559 ==
4698 09:58:20.232709 RX Vref Scan: 0
4699 09:58:20.232802
4700 09:58:20.235966 RX Vref 0 -> 0, step: 1
4701 09:58:20.236078
4702 09:58:20.239143 RX Delay -230 -> 252, step: 16
4703 09:58:20.242730 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4704 09:58:20.245907 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4705 09:58:20.249017 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4706 09:58:20.256098 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4707 09:58:20.258930 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4708 09:58:20.262145 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4709 09:58:20.265458 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4710 09:58:20.268858 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4711 09:58:20.275878 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4712 09:58:20.278938 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4713 09:58:20.282598 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4714 09:58:20.285670 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4715 09:58:20.292515 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4716 09:58:20.295433 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4717 09:58:20.299051 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4718 09:58:20.302248 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4719 09:58:20.302374 ==
4720 09:58:20.305779 Dram Type= 6, Freq= 0, CH_1, rank 1
4721 09:58:20.311995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4722 09:58:20.312124 ==
4723 09:58:20.312201 DQS Delay:
4724 09:58:20.315629 DQS0 = 0, DQS1 = 0
4725 09:58:20.315727 DQM Delay:
4726 09:58:20.315817 DQM0 = 44, DQM1 = 37
4727 09:58:20.318883 DQ Delay:
4728 09:58:20.322286 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4729 09:58:20.325350 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =33
4730 09:58:20.328450 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4731 09:58:20.331986 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4732 09:58:20.332128
4733 09:58:20.332238
4734 09:58:20.332352 ==
4735 09:58:20.335256 Dram Type= 6, Freq= 0, CH_1, rank 1
4736 09:58:20.338400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4737 09:58:20.338500 ==
4738 09:58:20.338606
4739 09:58:20.338714
4740 09:58:20.342235 TX Vref Scan disable
4741 09:58:20.345148 == TX Byte 0 ==
4742 09:58:20.348331 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4743 09:58:20.351785 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4744 09:58:20.355300 == TX Byte 1 ==
4745 09:58:20.358599 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4746 09:58:20.361591 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4747 09:58:20.361736 ==
4748 09:58:20.365110 Dram Type= 6, Freq= 0, CH_1, rank 1
4749 09:58:20.371822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4750 09:58:20.372007 ==
4751 09:58:20.372132
4752 09:58:20.372227
4753 09:58:20.372390 TX Vref Scan disable
4754 09:58:20.375808 == TX Byte 0 ==
4755 09:58:20.379435 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4756 09:58:20.385950 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4757 09:58:20.386081 == TX Byte 1 ==
4758 09:58:20.389064 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4759 09:58:20.395844 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4760 09:58:20.395974
4761 09:58:20.396067 [DATLAT]
4762 09:58:20.396165 Freq=600, CH1 RK1
4763 09:58:20.396247
4764 09:58:20.398602 DATLAT Default: 0x9
4765 09:58:20.401968 0, 0xFFFF, sum = 0
4766 09:58:20.402070 1, 0xFFFF, sum = 0
4767 09:58:20.405307 2, 0xFFFF, sum = 0
4768 09:58:20.405442 3, 0xFFFF, sum = 0
4769 09:58:20.408986 4, 0xFFFF, sum = 0
4770 09:58:20.409141 5, 0xFFFF, sum = 0
4771 09:58:20.412197 6, 0xFFFF, sum = 0
4772 09:58:20.412338 7, 0xFFFF, sum = 0
4773 09:58:20.415126 8, 0x0, sum = 1
4774 09:58:20.415310 9, 0x0, sum = 2
4775 09:58:20.418743 10, 0x0, sum = 3
4776 09:58:20.418867 11, 0x0, sum = 4
4777 09:58:20.418967 best_step = 9
4778 09:58:20.419061
4779 09:58:20.422013 ==
4780 09:58:20.425601 Dram Type= 6, Freq= 0, CH_1, rank 1
4781 09:58:20.428417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4782 09:58:20.428537 ==
4783 09:58:20.428633 RX Vref Scan: 0
4784 09:58:20.428725
4785 09:58:20.431448 RX Vref 0 -> 0, step: 1
4786 09:58:20.431562
4787 09:58:20.435310 RX Delay -195 -> 252, step: 8
4788 09:58:20.441672 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4789 09:58:20.444804 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4790 09:58:20.448516 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4791 09:58:20.451895 iDelay=213, Bit 3, Center 44 (-99 ~ 188) 288
4792 09:58:20.455184 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4793 09:58:20.461377 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4794 09:58:20.464973 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4795 09:58:20.467807 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4796 09:58:20.471215 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4797 09:58:20.477594 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4798 09:58:20.481138 iDelay=213, Bit 10, Center 32 (-123 ~ 188) 312
4799 09:58:20.484552 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4800 09:58:20.488030 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4801 09:58:20.494180 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4802 09:58:20.497993 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4803 09:58:20.500886 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4804 09:58:20.501007 ==
4805 09:58:20.504110 Dram Type= 6, Freq= 0, CH_1, rank 1
4806 09:58:20.507517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4807 09:58:20.511177 ==
4808 09:58:20.511289 DQS Delay:
4809 09:58:20.511358 DQS0 = 0, DQS1 = 0
4810 09:58:20.514231 DQM Delay:
4811 09:58:20.514321 DQM0 = 46, DQM1 = 36
4812 09:58:20.517727 DQ Delay:
4813 09:58:20.517824 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =44
4814 09:58:20.520634 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4815 09:58:20.524466 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4816 09:58:20.527289 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4817 09:58:20.530523
4818 09:58:20.530621
4819 09:58:20.537126 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d22, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4820 09:58:20.540704 CH1 RK1: MR19=808, MR18=2D22
4821 09:58:20.547258 CH1_RK1: MR19=0x808, MR18=0x2D22, DQSOSC=401, MR23=63, INC=163, DEC=108
4822 09:58:20.550456 [RxdqsGatingPostProcess] freq 600
4823 09:58:20.553873 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4824 09:58:20.556755 Pre-setting of DQS Precalculation
4825 09:58:20.563720 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4826 09:58:20.570205 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4827 09:58:20.576719 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4828 09:58:20.576855
4829 09:58:20.576950
4830 09:58:20.579833 [Calibration Summary] 1200 Mbps
4831 09:58:20.579943 CH 0, Rank 0
4832 09:58:20.583001 SW Impedance : PASS
4833 09:58:20.586486 DUTY Scan : NO K
4834 09:58:20.586622 ZQ Calibration : PASS
4835 09:58:20.589803 Jitter Meter : NO K
4836 09:58:20.593310 CBT Training : PASS
4837 09:58:20.593443 Write leveling : PASS
4838 09:58:20.596370 RX DQS gating : PASS
4839 09:58:20.599869 RX DQ/DQS(RDDQC) : PASS
4840 09:58:20.599967 TX DQ/DQS : PASS
4841 09:58:20.603112 RX DATLAT : PASS
4842 09:58:20.606325 RX DQ/DQS(Engine): PASS
4843 09:58:20.606441 TX OE : NO K
4844 09:58:20.609756 All Pass.
4845 09:58:20.609852
4846 09:58:20.609940 CH 0, Rank 1
4847 09:58:20.612694 SW Impedance : PASS
4848 09:58:20.612782 DUTY Scan : NO K
4849 09:58:20.616261 ZQ Calibration : PASS
4850 09:58:20.619611 Jitter Meter : NO K
4851 09:58:20.619707 CBT Training : PASS
4852 09:58:20.622910 Write leveling : PASS
4853 09:58:20.626097 RX DQS gating : PASS
4854 09:58:20.626197 RX DQ/DQS(RDDQC) : PASS
4855 09:58:20.629147 TX DQ/DQS : PASS
4856 09:58:20.629265 RX DATLAT : PASS
4857 09:58:20.632824 RX DQ/DQS(Engine): PASS
4858 09:58:20.635868 TX OE : NO K
4859 09:58:20.635988 All Pass.
4860 09:58:20.636089
4861 09:58:20.636187 CH 1, Rank 0
4862 09:58:20.639460 SW Impedance : PASS
4863 09:58:20.642588 DUTY Scan : NO K
4864 09:58:20.642684 ZQ Calibration : PASS
4865 09:58:20.646124 Jitter Meter : NO K
4866 09:58:20.649707 CBT Training : PASS
4867 09:58:20.649804 Write leveling : PASS
4868 09:58:20.652635 RX DQS gating : PASS
4869 09:58:20.655694 RX DQ/DQS(RDDQC) : PASS
4870 09:58:20.655779 TX DQ/DQS : PASS
4871 09:58:20.659182 RX DATLAT : PASS
4872 09:58:20.662759 RX DQ/DQS(Engine): PASS
4873 09:58:20.662859 TX OE : NO K
4874 09:58:20.665644 All Pass.
4875 09:58:20.665776
4876 09:58:20.665873 CH 1, Rank 1
4877 09:58:20.669117 SW Impedance : PASS
4878 09:58:20.669231 DUTY Scan : NO K
4879 09:58:20.672551 ZQ Calibration : PASS
4880 09:58:20.675525 Jitter Meter : NO K
4881 09:58:20.675626 CBT Training : PASS
4882 09:58:20.679216 Write leveling : PASS
4883 09:58:20.682092 RX DQS gating : PASS
4884 09:58:20.682201 RX DQ/DQS(RDDQC) : PASS
4885 09:58:20.685745 TX DQ/DQS : PASS
4886 09:58:20.689186 RX DATLAT : PASS
4887 09:58:20.689312 RX DQ/DQS(Engine): PASS
4888 09:58:20.691938 TX OE : NO K
4889 09:58:20.692031 All Pass.
4890 09:58:20.692099
4891 09:58:20.695301 DramC Write-DBI off
4892 09:58:20.698816 PER_BANK_REFRESH: Hybrid Mode
4893 09:58:20.698908 TX_TRACKING: ON
4894 09:58:20.708822 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4895 09:58:20.711801 [FAST_K] Save calibration result to emmc
4896 09:58:20.714942 dramc_set_vcore_voltage set vcore to 662500
4897 09:58:20.718640 Read voltage for 933, 3
4898 09:58:20.718743 Vio18 = 0
4899 09:58:20.718818 Vcore = 662500
4900 09:58:20.721830 Vdram = 0
4901 09:58:20.721929 Vddq = 0
4902 09:58:20.722006 Vmddr = 0
4903 09:58:20.728135 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4904 09:58:20.731665 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4905 09:58:20.735205 MEM_TYPE=3, freq_sel=17
4906 09:58:20.738706 sv_algorithm_assistance_LP4_1600
4907 09:58:20.741733 ============ PULL DRAM RESETB DOWN ============
4908 09:58:20.744812 ========== PULL DRAM RESETB DOWN end =========
4909 09:58:20.751485 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4910 09:58:20.755338 ===================================
4911 09:58:20.755453 LPDDR4 DRAM CONFIGURATION
4912 09:58:20.758173 ===================================
4913 09:58:20.761710 EX_ROW_EN[0] = 0x0
4914 09:58:20.764597 EX_ROW_EN[1] = 0x0
4915 09:58:20.764690 LP4Y_EN = 0x0
4916 09:58:20.768180 WORK_FSP = 0x0
4917 09:58:20.768275 WL = 0x3
4918 09:58:20.771332 RL = 0x3
4919 09:58:20.771419 BL = 0x2
4920 09:58:20.774902 RPST = 0x0
4921 09:58:20.774997 RD_PRE = 0x0
4922 09:58:20.777851 WR_PRE = 0x1
4923 09:58:20.777952 WR_PST = 0x0
4924 09:58:20.781656 DBI_WR = 0x0
4925 09:58:20.781762 DBI_RD = 0x0
4926 09:58:20.784983 OTF = 0x1
4927 09:58:20.788211 ===================================
4928 09:58:20.791194 ===================================
4929 09:58:20.791299 ANA top config
4930 09:58:20.794766 ===================================
4931 09:58:20.798099 DLL_ASYNC_EN = 0
4932 09:58:20.801228 ALL_SLAVE_EN = 1
4933 09:58:20.804383 NEW_RANK_MODE = 1
4934 09:58:20.804480 DLL_IDLE_MODE = 1
4935 09:58:20.807795 LP45_APHY_COMB_EN = 1
4936 09:58:20.811302 TX_ODT_DIS = 1
4937 09:58:20.814265 NEW_8X_MODE = 1
4938 09:58:20.817869 ===================================
4939 09:58:20.821266 ===================================
4940 09:58:20.824244 data_rate = 1866
4941 09:58:20.824343 CKR = 1
4942 09:58:20.827792 DQ_P2S_RATIO = 8
4943 09:58:20.830945 ===================================
4944 09:58:20.834383 CA_P2S_RATIO = 8
4945 09:58:20.837306 DQ_CA_OPEN = 0
4946 09:58:20.840692 DQ_SEMI_OPEN = 0
4947 09:58:20.844168 CA_SEMI_OPEN = 0
4948 09:58:20.844300 CA_FULL_RATE = 0
4949 09:58:20.847751 DQ_CKDIV4_EN = 1
4950 09:58:20.850726 CA_CKDIV4_EN = 1
4951 09:58:20.854382 CA_PREDIV_EN = 0
4952 09:58:20.857236 PH8_DLY = 0
4953 09:58:20.860929 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4954 09:58:20.861051 DQ_AAMCK_DIV = 4
4955 09:58:20.863826 CA_AAMCK_DIV = 4
4956 09:58:20.867337 CA_ADMCK_DIV = 4
4957 09:58:20.870862 DQ_TRACK_CA_EN = 0
4958 09:58:20.873905 CA_PICK = 933
4959 09:58:20.877626 CA_MCKIO = 933
4960 09:58:20.880780 MCKIO_SEMI = 0
4961 09:58:20.880905 PLL_FREQ = 3732
4962 09:58:20.883641 DQ_UI_PI_RATIO = 32
4963 09:58:20.887149 CA_UI_PI_RATIO = 0
4964 09:58:20.890376 ===================================
4965 09:58:20.894201 ===================================
4966 09:58:20.897153 memory_type:LPDDR4
4967 09:58:20.900419 GP_NUM : 10
4968 09:58:20.900536 SRAM_EN : 1
4969 09:58:20.903775 MD32_EN : 0
4970 09:58:20.907105 ===================================
4971 09:58:20.907202 [ANA_INIT] >>>>>>>>>>>>>>
4972 09:58:20.910402 <<<<<< [CONFIGURE PHASE]: ANA_TX
4973 09:58:20.913324 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4974 09:58:20.916700 ===================================
4975 09:58:20.920119 data_rate = 1866,PCW = 0X8f00
4976 09:58:20.923222 ===================================
4977 09:58:20.927077 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4978 09:58:20.933073 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4979 09:58:20.939556 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4980 09:58:20.943303 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4981 09:58:20.946757 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4982 09:58:20.949576 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4983 09:58:20.953170 [ANA_INIT] flow start
4984 09:58:20.953295 [ANA_INIT] PLL >>>>>>>>
4985 09:58:20.956104 [ANA_INIT] PLL <<<<<<<<
4986 09:58:20.959608 [ANA_INIT] MIDPI >>>>>>>>
4987 09:58:20.963151 [ANA_INIT] MIDPI <<<<<<<<
4988 09:58:20.963248 [ANA_INIT] DLL >>>>>>>>
4989 09:58:20.966214 [ANA_INIT] flow end
4990 09:58:20.969234 ============ LP4 DIFF to SE enter ============
4991 09:58:20.972787 ============ LP4 DIFF to SE exit ============
4992 09:58:20.975843 [ANA_INIT] <<<<<<<<<<<<<
4993 09:58:20.979571 [Flow] Enable top DCM control >>>>>
4994 09:58:20.982549 [Flow] Enable top DCM control <<<<<
4995 09:58:20.986188 Enable DLL master slave shuffle
4996 09:58:20.992871 ==============================================================
4997 09:58:20.993017 Gating Mode config
4998 09:58:20.999166 ==============================================================
4999 09:58:20.999282 Config description:
5000 09:58:21.009264 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5001 09:58:21.015524 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5002 09:58:21.022135 SELPH_MODE 0: By rank 1: By Phase
5003 09:58:21.025514 ==============================================================
5004 09:58:21.029029 GAT_TRACK_EN = 1
5005 09:58:21.032100 RX_GATING_MODE = 2
5006 09:58:21.035334 RX_GATING_TRACK_MODE = 2
5007 09:58:21.038995 SELPH_MODE = 1
5008 09:58:21.041870 PICG_EARLY_EN = 1
5009 09:58:21.045294 VALID_LAT_VALUE = 1
5010 09:58:21.052102 ==============================================================
5011 09:58:21.055563 Enter into Gating configuration >>>>
5012 09:58:21.058859 Exit from Gating configuration <<<<
5013 09:58:21.062152 Enter into DVFS_PRE_config >>>>>
5014 09:58:21.071740 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5015 09:58:21.075266 Exit from DVFS_PRE_config <<<<<
5016 09:58:21.078243 Enter into PICG configuration >>>>
5017 09:58:21.081619 Exit from PICG configuration <<<<
5018 09:58:21.084720 [RX_INPUT] configuration >>>>>
5019 09:58:21.084843 [RX_INPUT] configuration <<<<<
5020 09:58:21.091530 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5021 09:58:21.098247 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5022 09:58:21.101676 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5023 09:58:21.107923 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5024 09:58:21.114386 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5025 09:58:21.121187 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5026 09:58:21.124371 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5027 09:58:21.128139 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5028 09:58:21.134295 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5029 09:58:21.137818 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5030 09:58:21.141016 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5031 09:58:21.147955 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5032 09:58:21.151006 ===================================
5033 09:58:21.151143 LPDDR4 DRAM CONFIGURATION
5034 09:58:21.154332 ===================================
5035 09:58:21.157726 EX_ROW_EN[0] = 0x0
5036 09:58:21.160799 EX_ROW_EN[1] = 0x0
5037 09:58:21.160929 LP4Y_EN = 0x0
5038 09:58:21.164456 WORK_FSP = 0x0
5039 09:58:21.164576 WL = 0x3
5040 09:58:21.167705 RL = 0x3
5041 09:58:21.167827 BL = 0x2
5042 09:58:21.170945 RPST = 0x0
5043 09:58:21.171058 RD_PRE = 0x0
5044 09:58:21.173847 WR_PRE = 0x1
5045 09:58:21.173947 WR_PST = 0x0
5046 09:58:21.177391 DBI_WR = 0x0
5047 09:58:21.177504 DBI_RD = 0x0
5048 09:58:21.180516 OTF = 0x1
5049 09:58:21.184054 ===================================
5050 09:58:21.187465 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5051 09:58:21.190781 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5052 09:58:21.197376 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5053 09:58:21.200369 ===================================
5054 09:58:21.200513 LPDDR4 DRAM CONFIGURATION
5055 09:58:21.204299 ===================================
5056 09:58:21.207094 EX_ROW_EN[0] = 0x10
5057 09:58:21.210303 EX_ROW_EN[1] = 0x0
5058 09:58:21.210428 LP4Y_EN = 0x0
5059 09:58:21.213778 WORK_FSP = 0x0
5060 09:58:21.213891 WL = 0x3
5061 09:58:21.217118 RL = 0x3
5062 09:58:21.217254 BL = 0x2
5063 09:58:21.220399 RPST = 0x0
5064 09:58:21.220512 RD_PRE = 0x0
5065 09:58:21.223754 WR_PRE = 0x1
5066 09:58:21.223864 WR_PST = 0x0
5067 09:58:21.226985 DBI_WR = 0x0
5068 09:58:21.227095 DBI_RD = 0x0
5069 09:58:21.230536 OTF = 0x1
5070 09:58:21.233629 ===================================
5071 09:58:21.240214 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5072 09:58:21.243480 nWR fixed to 30
5073 09:58:21.243623 [ModeRegInit_LP4] CH0 RK0
5074 09:58:21.247103 [ModeRegInit_LP4] CH0 RK1
5075 09:58:21.250196 [ModeRegInit_LP4] CH1 RK0
5076 09:58:21.253132 [ModeRegInit_LP4] CH1 RK1
5077 09:58:21.253262 match AC timing 9
5078 09:58:21.259750 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5079 09:58:21.263570 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5080 09:58:21.266522 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5081 09:58:21.273120 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5082 09:58:21.276359 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5083 09:58:21.276467 ==
5084 09:58:21.279900 Dram Type= 6, Freq= 0, CH_0, rank 0
5085 09:58:21.283168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5086 09:58:21.283281 ==
5087 09:58:21.290150 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5088 09:58:21.296281 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5089 09:58:21.299944 [CA 0] Center 37 (7~68) winsize 62
5090 09:58:21.302933 [CA 1] Center 37 (7~68) winsize 62
5091 09:58:21.306722 [CA 2] Center 34 (4~65) winsize 62
5092 09:58:21.309743 [CA 3] Center 34 (4~65) winsize 62
5093 09:58:21.313307 [CA 4] Center 33 (3~64) winsize 62
5094 09:58:21.316297 [CA 5] Center 33 (3~63) winsize 61
5095 09:58:21.316432
5096 09:58:21.319361 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5097 09:58:21.319447
5098 09:58:21.322760 [CATrainingPosCal] consider 1 rank data
5099 09:58:21.326568 u2DelayCellTimex100 = 270/100 ps
5100 09:58:21.329246 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5101 09:58:21.332679 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5102 09:58:21.335796 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5103 09:58:21.339159 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5104 09:58:21.342307 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5105 09:58:21.345932 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5106 09:58:21.349313
5107 09:58:21.352710 CA PerBit enable=1, Macro0, CA PI delay=33
5108 09:58:21.352829
5109 09:58:21.355588 [CBTSetCACLKResult] CA Dly = 33
5110 09:58:21.355728 CS Dly: 7 (0~38)
5111 09:58:21.355834 ==
5112 09:58:21.359260 Dram Type= 6, Freq= 0, CH_0, rank 1
5113 09:58:21.362412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5114 09:58:21.362584 ==
5115 09:58:21.369024 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5116 09:58:21.375799 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5117 09:58:21.378755 [CA 0] Center 37 (7~68) winsize 62
5118 09:58:21.382539 [CA 1] Center 37 (7~68) winsize 62
5119 09:58:21.386014 [CA 2] Center 34 (4~65) winsize 62
5120 09:58:21.388893 [CA 3] Center 34 (4~65) winsize 62
5121 09:58:21.392223 [CA 4] Center 33 (3~64) winsize 62
5122 09:58:21.395435 [CA 5] Center 33 (3~63) winsize 61
5123 09:58:21.395578
5124 09:58:21.399143 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5125 09:58:21.399287
5126 09:58:21.402310 [CATrainingPosCal] consider 2 rank data
5127 09:58:21.405461 u2DelayCellTimex100 = 270/100 ps
5128 09:58:21.408540 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5129 09:58:21.412149 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5130 09:58:21.415405 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5131 09:58:21.418548 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5132 09:58:21.425184 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5133 09:58:21.428795 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5134 09:58:21.428928
5135 09:58:21.431779 CA PerBit enable=1, Macro0, CA PI delay=33
5136 09:58:21.431913
5137 09:58:21.435021 [CBTSetCACLKResult] CA Dly = 33
5138 09:58:21.435107 CS Dly: 8 (0~40)
5139 09:58:21.435184
5140 09:58:21.438629 ----->DramcWriteLeveling(PI) begin...
5141 09:58:21.438718 ==
5142 09:58:21.442292 Dram Type= 6, Freq= 0, CH_0, rank 0
5143 09:58:21.448689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5144 09:58:21.448877 ==
5145 09:58:21.451809 Write leveling (Byte 0): 35 => 35
5146 09:58:21.454717 Write leveling (Byte 1): 30 => 30
5147 09:58:21.454835 DramcWriteLeveling(PI) end<-----
5148 09:58:21.454929
5149 09:58:21.458130 ==
5150 09:58:21.461621 Dram Type= 6, Freq= 0, CH_0, rank 0
5151 09:58:21.465061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5152 09:58:21.465154 ==
5153 09:58:21.468351 [Gating] SW mode calibration
5154 09:58:21.475034 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5155 09:58:21.478184 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5156 09:58:21.484858 0 14 0 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
5157 09:58:21.488033 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5158 09:58:21.491630 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5159 09:58:21.497480 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5160 09:58:21.500935 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5161 09:58:21.504347 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5162 09:58:21.510987 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5163 09:58:21.514080 0 14 28 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
5164 09:58:21.517740 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5165 09:58:21.524070 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5166 09:58:21.527262 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5167 09:58:21.530731 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5168 09:58:21.537254 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5169 09:58:21.540391 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5170 09:58:21.543502 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 09:58:21.550593 0 15 28 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5172 09:58:21.553946 1 0 0 | B1->B0 | 2d2d 4545 | 1 0 | (0 0) (0 0)
5173 09:58:21.557332 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5174 09:58:21.563473 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5175 09:58:21.566857 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5176 09:58:21.570207 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 09:58:21.576703 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 09:58:21.580545 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 09:58:21.583592 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5180 09:58:21.589863 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5181 09:58:21.593482 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5182 09:58:21.596558 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 09:58:21.603344 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 09:58:21.606192 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 09:58:21.609601 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 09:58:21.616175 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 09:58:21.619737 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 09:58:21.626016 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 09:58:21.629167 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 09:58:21.632778 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 09:58:21.639095 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 09:58:21.642773 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 09:58:21.645922 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 09:58:21.652795 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5195 09:58:21.655957 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 09:58:21.659342 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5197 09:58:21.665673 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5198 09:58:21.665793 Total UI for P1: 0, mck2ui 16
5199 09:58:21.669249 best dqsien dly found for B0: ( 1, 3, 0)
5200 09:58:21.675716 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5201 09:58:21.678575 Total UI for P1: 0, mck2ui 16
5202 09:58:21.682123 best dqsien dly found for B1: ( 1, 3, 4)
5203 09:58:21.685283 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5204 09:58:21.688708 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5205 09:58:21.688827
5206 09:58:21.692415 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5207 09:58:21.695331 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5208 09:58:21.699002 [Gating] SW calibration Done
5209 09:58:21.699157 ==
5210 09:58:21.702032 Dram Type= 6, Freq= 0, CH_0, rank 0
5211 09:58:21.704996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5212 09:58:21.705107 ==
5213 09:58:21.708842 RX Vref Scan: 0
5214 09:58:21.708971
5215 09:58:21.711905 RX Vref 0 -> 0, step: 1
5216 09:58:21.712011
5217 09:58:21.712109 RX Delay -80 -> 252, step: 8
5218 09:58:21.718395 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5219 09:58:21.722064 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5220 09:58:21.725178 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5221 09:58:21.728091 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5222 09:58:21.731317 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5223 09:58:21.735085 iDelay=208, Bit 5, Center 87 (-16 ~ 191) 208
5224 09:58:21.741439 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5225 09:58:21.744856 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5226 09:58:21.748208 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5227 09:58:21.751382 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5228 09:58:21.754574 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5229 09:58:21.761232 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5230 09:58:21.764257 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5231 09:58:21.767814 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5232 09:58:21.771399 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5233 09:58:21.777851 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5234 09:58:21.777992 ==
5235 09:58:21.780710 Dram Type= 6, Freq= 0, CH_0, rank 0
5236 09:58:21.784461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5237 09:58:21.784589 ==
5238 09:58:21.784706 DQS Delay:
5239 09:58:21.787354 DQS0 = 0, DQS1 = 0
5240 09:58:21.787482 DQM Delay:
5241 09:58:21.790581 DQM0 = 97, DQM1 = 85
5242 09:58:21.790671 DQ Delay:
5243 09:58:21.794417 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5244 09:58:21.797487 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5245 09:58:21.800604 DQ8 =79, DQ9 =79, DQ10 =83, DQ11 =79
5246 09:58:21.804247 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5247 09:58:21.804394
5248 09:58:21.804483
5249 09:58:21.804561 ==
5250 09:58:21.807343 Dram Type= 6, Freq= 0, CH_0, rank 0
5251 09:58:21.810467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5252 09:58:21.810604 ==
5253 09:58:21.810709
5254 09:58:21.814188
5255 09:58:21.814321 TX Vref Scan disable
5256 09:58:21.817238 == TX Byte 0 ==
5257 09:58:21.820421 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5258 09:58:21.824030 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5259 09:58:21.826722 == TX Byte 1 ==
5260 09:58:21.830716 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5261 09:58:21.833435 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5262 09:58:21.833574 ==
5263 09:58:21.837129 Dram Type= 6, Freq= 0, CH_0, rank 0
5264 09:58:21.843281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5265 09:58:21.843433 ==
5266 09:58:21.843505
5267 09:58:21.843604
5268 09:58:21.847025 TX Vref Scan disable
5269 09:58:21.847165 == TX Byte 0 ==
5270 09:58:21.853425 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5271 09:58:21.857032 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5272 09:58:21.857187 == TX Byte 1 ==
5273 09:58:21.863181 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5274 09:58:21.866759 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5275 09:58:21.866873
5276 09:58:21.866942 [DATLAT]
5277 09:58:21.869755 Freq=933, CH0 RK0
5278 09:58:21.869861
5279 09:58:21.869951 DATLAT Default: 0xd
5280 09:58:21.873378 0, 0xFFFF, sum = 0
5281 09:58:21.873475 1, 0xFFFF, sum = 0
5282 09:58:21.876456 2, 0xFFFF, sum = 0
5283 09:58:21.876540 3, 0xFFFF, sum = 0
5284 09:58:21.880081 4, 0xFFFF, sum = 0
5285 09:58:21.880174 5, 0xFFFF, sum = 0
5286 09:58:21.882888 6, 0xFFFF, sum = 0
5287 09:58:21.882976 7, 0xFFFF, sum = 0
5288 09:58:21.886345 8, 0xFFFF, sum = 0
5289 09:58:21.889938 9, 0xFFFF, sum = 0
5290 09:58:21.890042 10, 0x0, sum = 1
5291 09:58:21.890111 11, 0x0, sum = 2
5292 09:58:21.892885 12, 0x0, sum = 3
5293 09:58:21.893012 13, 0x0, sum = 4
5294 09:58:21.896587 best_step = 11
5295 09:58:21.896673
5296 09:58:21.896749 ==
5297 09:58:21.899364 Dram Type= 6, Freq= 0, CH_0, rank 0
5298 09:58:21.903210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5299 09:58:21.903303 ==
5300 09:58:21.906180 RX Vref Scan: 1
5301 09:58:21.906267
5302 09:58:21.906339 RX Vref 0 -> 0, step: 1
5303 09:58:21.909332
5304 09:58:21.909459 RX Delay -61 -> 252, step: 4
5305 09:58:21.909533
5306 09:58:21.913032 Set Vref, RX VrefLevel [Byte0]: 55
5307 09:58:21.916015 [Byte1]: 48
5308 09:58:21.920323
5309 09:58:21.920420 Final RX Vref Byte 0 = 55 to rank0
5310 09:58:21.924005 Final RX Vref Byte 1 = 48 to rank0
5311 09:58:21.927119 Final RX Vref Byte 0 = 55 to rank1
5312 09:58:21.930094 Final RX Vref Byte 1 = 48 to rank1==
5313 09:58:21.933611 Dram Type= 6, Freq= 0, CH_0, rank 0
5314 09:58:21.940283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5315 09:58:21.940455 ==
5316 09:58:21.940569 DQS Delay:
5317 09:58:21.943558 DQS0 = 0, DQS1 = 0
5318 09:58:21.943685 DQM Delay:
5319 09:58:21.943786 DQM0 = 96, DQM1 = 85
5320 09:58:21.947115 DQ Delay:
5321 09:58:21.950328 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =94
5322 09:58:21.953432 DQ4 =98, DQ5 =88, DQ6 =104, DQ7 =104
5323 09:58:21.956521 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5324 09:58:21.959957 DQ12 =88, DQ13 =88, DQ14 =98, DQ15 =90
5325 09:58:21.960086
5326 09:58:21.960180
5327 09:58:21.966313 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c13, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 408 ps
5328 09:58:21.970160 CH0 RK0: MR19=505, MR18=2C13
5329 09:58:21.976555 CH0_RK0: MR19=0x505, MR18=0x2C13, DQSOSC=408, MR23=63, INC=65, DEC=43
5330 09:58:21.976687
5331 09:58:21.979844 ----->DramcWriteLeveling(PI) begin...
5332 09:58:21.979972 ==
5333 09:58:21.982762 Dram Type= 6, Freq= 0, CH_0, rank 1
5334 09:58:21.986330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5335 09:58:21.986455 ==
5336 09:58:21.989595 Write leveling (Byte 0): 33 => 33
5337 09:58:21.992952 Write leveling (Byte 1): 28 => 28
5338 09:58:21.996079 DramcWriteLeveling(PI) end<-----
5339 09:58:21.996210
5340 09:58:21.996316 ==
5341 09:58:21.999716 Dram Type= 6, Freq= 0, CH_0, rank 1
5342 09:58:22.002881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5343 09:58:22.006208 ==
5344 09:58:22.006340 [Gating] SW mode calibration
5345 09:58:22.016049 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5346 09:58:22.019831 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5347 09:58:22.022945 0 14 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5348 09:58:22.029089 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5349 09:58:22.032770 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5350 09:58:22.035892 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5351 09:58:22.042583 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5352 09:58:22.046124 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5353 09:58:22.049486 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5354 09:58:22.055759 0 14 28 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
5355 09:58:22.058855 0 15 0 | B1->B0 | 2c2c 2525 | 0 0 | (0 0) (0 0)
5356 09:58:22.062034 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5357 09:58:22.069124 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5358 09:58:22.071916 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5359 09:58:22.075631 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 09:58:22.081703 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 09:58:22.085338 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 09:58:22.088359 0 15 28 | B1->B0 | 2a2a 3939 | 0 1 | (0 0) (0 0)
5363 09:58:22.094893 1 0 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5364 09:58:22.098322 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 09:58:22.101820 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5366 09:58:22.108430 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 09:58:22.111513 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 09:58:22.114984 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 09:58:22.121499 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 09:58:22.124510 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 09:58:22.128225 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 09:58:22.134969 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 09:58:22.138083 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 09:58:22.141609 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 09:58:22.147831 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 09:58:22.151587 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 09:58:22.154341 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 09:58:22.161188 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 09:58:22.164669 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 09:58:22.167684 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 09:58:22.174477 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 09:58:22.177795 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 09:58:22.181349 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 09:58:22.187678 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 09:58:22.190805 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 09:58:22.194439 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5387 09:58:22.200695 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5388 09:58:22.204202 Total UI for P1: 0, mck2ui 16
5389 09:58:22.207464 best dqsien dly found for B0: ( 1, 2, 28)
5390 09:58:22.210934 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5391 09:58:22.213916 Total UI for P1: 0, mck2ui 16
5392 09:58:22.217591 best dqsien dly found for B1: ( 1, 2, 30)
5393 09:58:22.220649 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5394 09:58:22.224130 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5395 09:58:22.224253
5396 09:58:22.227470 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5397 09:58:22.230921 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5398 09:58:22.233786 [Gating] SW calibration Done
5399 09:58:22.233897 ==
5400 09:58:22.236862 Dram Type= 6, Freq= 0, CH_0, rank 1
5401 09:58:22.243597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5402 09:58:22.243735 ==
5403 09:58:22.243829 RX Vref Scan: 0
5404 09:58:22.243893
5405 09:58:22.247118 RX Vref 0 -> 0, step: 1
5406 09:58:22.247204
5407 09:58:22.250328 RX Delay -80 -> 252, step: 8
5408 09:58:22.253405 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5409 09:58:22.257192 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5410 09:58:22.260282 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5411 09:58:22.263431 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5412 09:58:22.269947 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5413 09:58:22.273422 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5414 09:58:22.276477 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5415 09:58:22.279562 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5416 09:58:22.283207 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5417 09:58:22.289751 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5418 09:58:22.292846 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5419 09:58:22.296726 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5420 09:58:22.299815 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5421 09:58:22.303004 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5422 09:58:22.309669 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5423 09:58:22.312674 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5424 09:58:22.312822 ==
5425 09:58:22.316528 Dram Type= 6, Freq= 0, CH_0, rank 1
5426 09:58:22.319254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5427 09:58:22.319352 ==
5428 09:58:22.319458 DQS Delay:
5429 09:58:22.322822 DQS0 = 0, DQS1 = 0
5430 09:58:22.322924 DQM Delay:
5431 09:58:22.325964 DQM0 = 96, DQM1 = 87
5432 09:58:22.326057 DQ Delay:
5433 09:58:22.329091 DQ0 =95, DQ1 =99, DQ2 =87, DQ3 =91
5434 09:58:22.332732 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =107
5435 09:58:22.335793 DQ8 =79, DQ9 =75, DQ10 =91, DQ11 =83
5436 09:58:22.339232 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5437 09:58:22.339326
5438 09:58:22.339417
5439 09:58:22.339519 ==
5440 09:58:22.342715 Dram Type= 6, Freq= 0, CH_0, rank 1
5441 09:58:22.348824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5442 09:58:22.348981 ==
5443 09:58:22.349089
5444 09:58:22.349188
5445 09:58:22.349291 TX Vref Scan disable
5446 09:58:22.352484 == TX Byte 0 ==
5447 09:58:22.356258 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5448 09:58:22.362443 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5449 09:58:22.362611 == TX Byte 1 ==
5450 09:58:22.365555 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5451 09:58:22.372411 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5452 09:58:22.372585 ==
5453 09:58:22.375366 Dram Type= 6, Freq= 0, CH_0, rank 1
5454 09:58:22.378872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5455 09:58:22.378981 ==
5456 09:58:22.379079
5457 09:58:22.379166
5458 09:58:22.382166 TX Vref Scan disable
5459 09:58:22.382269 == TX Byte 0 ==
5460 09:58:22.388980 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5461 09:58:22.392277 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5462 09:58:22.392453 == TX Byte 1 ==
5463 09:58:22.398967 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5464 09:58:22.402209 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5465 09:58:22.402312
5466 09:58:22.402401 [DATLAT]
5467 09:58:22.405136 Freq=933, CH0 RK1
5468 09:58:22.405245
5469 09:58:22.405361 DATLAT Default: 0xb
5470 09:58:22.408943 0, 0xFFFF, sum = 0
5471 09:58:22.411978 1, 0xFFFF, sum = 0
5472 09:58:22.412102 2, 0xFFFF, sum = 0
5473 09:58:22.415471 3, 0xFFFF, sum = 0
5474 09:58:22.415597 4, 0xFFFF, sum = 0
5475 09:58:22.418639 5, 0xFFFF, sum = 0
5476 09:58:22.418759 6, 0xFFFF, sum = 0
5477 09:58:22.422353 7, 0xFFFF, sum = 0
5478 09:58:22.422492 8, 0xFFFF, sum = 0
5479 09:58:22.425241 9, 0xFFFF, sum = 0
5480 09:58:22.425356 10, 0x0, sum = 1
5481 09:58:22.428748 11, 0x0, sum = 2
5482 09:58:22.428854 12, 0x0, sum = 3
5483 09:58:22.431905 13, 0x0, sum = 4
5484 09:58:22.432027 best_step = 11
5485 09:58:22.432136
5486 09:58:22.432214 ==
5487 09:58:22.435029 Dram Type= 6, Freq= 0, CH_0, rank 1
5488 09:58:22.438792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5489 09:58:22.438916 ==
5490 09:58:22.441715 RX Vref Scan: 0
5491 09:58:22.441869
5492 09:58:22.445045 RX Vref 0 -> 0, step: 1
5493 09:58:22.445213
5494 09:58:22.445326 RX Delay -69 -> 252, step: 4
5495 09:58:22.452970 iDelay=203, Bit 0, Center 94 (7 ~ 182) 176
5496 09:58:22.456511 iDelay=203, Bit 1, Center 100 (7 ~ 194) 188
5497 09:58:22.459650 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5498 09:58:22.462769 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5499 09:58:22.466533 iDelay=203, Bit 4, Center 96 (7 ~ 186) 180
5500 09:58:22.469652 iDelay=203, Bit 5, Center 88 (-5 ~ 182) 188
5501 09:58:22.476515 iDelay=203, Bit 6, Center 108 (15 ~ 202) 188
5502 09:58:22.479340 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5503 09:58:22.482496 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5504 09:58:22.485980 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5505 09:58:22.489346 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5506 09:58:22.495687 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5507 09:58:22.499435 iDelay=203, Bit 12, Center 96 (7 ~ 186) 180
5508 09:58:22.502804 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5509 09:58:22.506128 iDelay=203, Bit 14, Center 96 (7 ~ 186) 180
5510 09:58:22.509236 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5511 09:58:22.512274 ==
5512 09:58:22.515984 Dram Type= 6, Freq= 0, CH_0, rank 1
5513 09:58:22.518937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5514 09:58:22.519067 ==
5515 09:58:22.519170 DQS Delay:
5516 09:58:22.522324 DQS0 = 0, DQS1 = 0
5517 09:58:22.522442 DQM Delay:
5518 09:58:22.525885 DQM0 = 96, DQM1 = 86
5519 09:58:22.526003 DQ Delay:
5520 09:58:22.528689 DQ0 =94, DQ1 =100, DQ2 =90, DQ3 =92
5521 09:58:22.532375 DQ4 =96, DQ5 =88, DQ6 =108, DQ7 =104
5522 09:58:22.535373 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =78
5523 09:58:22.539088 DQ12 =96, DQ13 =92, DQ14 =96, DQ15 =92
5524 09:58:22.539182
5525 09:58:22.539248
5526 09:58:22.545259 [DQSOSCAuto] RK1, (LSB)MR18= 0x2cfc, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 408 ps
5527 09:58:22.549043 CH0 RK1: MR19=504, MR18=2CFC
5528 09:58:22.555372 CH0_RK1: MR19=0x504, MR18=0x2CFC, DQSOSC=408, MR23=63, INC=65, DEC=43
5529 09:58:22.558654 [RxdqsGatingPostProcess] freq 933
5530 09:58:22.565356 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5531 09:58:22.568493 best DQS0 dly(2T, 0.5T) = (0, 11)
5532 09:58:22.571604 best DQS1 dly(2T, 0.5T) = (0, 11)
5533 09:58:22.575355 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5534 09:58:22.578426 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5535 09:58:22.578552 best DQS0 dly(2T, 0.5T) = (0, 10)
5536 09:58:22.581593 best DQS1 dly(2T, 0.5T) = (0, 10)
5537 09:58:22.585162 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5538 09:58:22.588306 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5539 09:58:22.591544 Pre-setting of DQS Precalculation
5540 09:58:22.597810 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5541 09:58:22.597960 ==
5542 09:58:22.601513 Dram Type= 6, Freq= 0, CH_1, rank 0
5543 09:58:22.604455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5544 09:58:22.604552 ==
5545 09:58:22.611438 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5546 09:58:22.617929 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5547 09:58:22.621344 [CA 0] Center 36 (6~67) winsize 62
5548 09:58:22.624218 [CA 1] Center 36 (6~67) winsize 62
5549 09:58:22.628180 [CA 2] Center 34 (4~65) winsize 62
5550 09:58:22.631214 [CA 3] Center 33 (3~64) winsize 62
5551 09:58:22.634751 [CA 4] Center 34 (4~64) winsize 61
5552 09:58:22.637733 [CA 5] Center 33 (3~64) winsize 62
5553 09:58:22.637855
5554 09:58:22.641404 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5555 09:58:22.641514
5556 09:58:22.644513 [CATrainingPosCal] consider 1 rank data
5557 09:58:22.647767 u2DelayCellTimex100 = 270/100 ps
5558 09:58:22.650820 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5559 09:58:22.654585 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5560 09:58:22.657630 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5561 09:58:22.660742 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5562 09:58:22.664112 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5563 09:58:22.667103 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5564 09:58:22.667229
5565 09:58:22.674141 CA PerBit enable=1, Macro0, CA PI delay=33
5566 09:58:22.674289
5567 09:58:22.676974 [CBTSetCACLKResult] CA Dly = 33
5568 09:58:22.677093 CS Dly: 6 (0~37)
5569 09:58:22.677194 ==
5570 09:58:22.680608 Dram Type= 6, Freq= 0, CH_1, rank 1
5571 09:58:22.683888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5572 09:58:22.684009 ==
5573 09:58:22.690596 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5574 09:58:22.696831 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5575 09:58:22.700074 [CA 0] Center 36 (6~67) winsize 62
5576 09:58:22.703554 [CA 1] Center 37 (7~67) winsize 61
5577 09:58:22.706979 [CA 2] Center 34 (4~65) winsize 62
5578 09:58:22.709978 [CA 3] Center 33 (3~64) winsize 62
5579 09:58:22.713769 [CA 4] Center 34 (3~65) winsize 63
5580 09:58:22.716500 [CA 5] Center 33 (3~64) winsize 62
5581 09:58:22.716599
5582 09:58:22.719870 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5583 09:58:22.719991
5584 09:58:22.723273 [CATrainingPosCal] consider 2 rank data
5585 09:58:22.726923 u2DelayCellTimex100 = 270/100 ps
5586 09:58:22.730010 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5587 09:58:22.733453 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5588 09:58:22.736503 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5589 09:58:22.743213 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5590 09:58:22.746140 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5591 09:58:22.749771 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5592 09:58:22.749884
5593 09:58:22.752843 CA PerBit enable=1, Macro0, CA PI delay=33
5594 09:58:22.752932
5595 09:58:22.755935 [CBTSetCACLKResult] CA Dly = 33
5596 09:58:22.756025 CS Dly: 7 (0~39)
5597 09:58:22.756099
5598 09:58:22.759749 ----->DramcWriteLeveling(PI) begin...
5599 09:58:22.759866 ==
5600 09:58:22.762942 Dram Type= 6, Freq= 0, CH_1, rank 0
5601 09:58:22.769120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5602 09:58:22.769234 ==
5603 09:58:22.772756 Write leveling (Byte 0): 25 => 25
5604 09:58:22.775680 Write leveling (Byte 1): 30 => 30
5605 09:58:22.779334 DramcWriteLeveling(PI) end<-----
5606 09:58:22.779432
5607 09:58:22.779505 ==
5608 09:58:22.782243 Dram Type= 6, Freq= 0, CH_1, rank 0
5609 09:58:22.785699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5610 09:58:22.785796 ==
5611 09:58:22.788654 [Gating] SW mode calibration
5612 09:58:22.795595 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5613 09:58:22.801777 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5614 09:58:22.805416 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5615 09:58:22.808632 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5616 09:58:22.815374 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5617 09:58:22.818512 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5618 09:58:22.821793 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5619 09:58:22.828469 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5620 09:58:22.831855 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
5621 09:58:22.834856 0 14 28 | B1->B0 | 2f2f 2d2d | 1 1 | (1 1) (1 0)
5622 09:58:22.841839 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
5623 09:58:22.844988 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5624 09:58:22.848317 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5625 09:58:22.854902 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5626 09:58:22.858042 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5627 09:58:22.861219 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5628 09:58:22.867935 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5629 09:58:22.871142 0 15 28 | B1->B0 | 3232 3737 | 0 0 | (0 0) (0 0)
5630 09:58:22.874891 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 09:58:22.880927 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 09:58:22.884644 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 09:58:22.887632 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 09:58:22.894431 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5635 09:58:22.897526 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 09:58:22.900681 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5637 09:58:22.907548 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 09:58:22.910763 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 09:58:22.913823 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 09:58:22.920785 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 09:58:22.923641 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 09:58:22.927403 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 09:58:22.933964 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 09:58:22.936783 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 09:58:22.940289 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 09:58:22.946995 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 09:58:22.950165 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 09:58:22.953119 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 09:58:22.960155 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 09:58:22.963094 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 09:58:22.966614 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5652 09:58:22.973377 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5653 09:58:22.976481 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5654 09:58:22.979886 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5655 09:58:22.982987 Total UI for P1: 0, mck2ui 16
5656 09:58:22.986630 best dqsien dly found for B0: ( 1, 2, 24)
5657 09:58:22.989675 Total UI for P1: 0, mck2ui 16
5658 09:58:22.992846 best dqsien dly found for B1: ( 1, 2, 24)
5659 09:58:22.996453 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5660 09:58:22.999590 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5661 09:58:22.999714
5662 09:58:23.006166 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5663 09:58:23.009214 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5664 09:58:23.012989 [Gating] SW calibration Done
5665 09:58:23.013092 ==
5666 09:58:23.016274 Dram Type= 6, Freq= 0, CH_1, rank 0
5667 09:58:23.019840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5668 09:58:23.019969 ==
5669 09:58:23.020075 RX Vref Scan: 0
5670 09:58:23.020170
5671 09:58:23.022933 RX Vref 0 -> 0, step: 1
5672 09:58:23.023026
5673 09:58:23.025909 RX Delay -80 -> 252, step: 8
5674 09:58:23.029391 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5675 09:58:23.032809 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5676 09:58:23.039455 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5677 09:58:23.042413 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5678 09:58:23.045992 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5679 09:58:23.048861 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5680 09:58:23.052295 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5681 09:58:23.055768 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5682 09:58:23.062363 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5683 09:58:23.065706 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5684 09:58:23.068740 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5685 09:58:23.071890 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5686 09:58:23.075546 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5687 09:58:23.081752 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5688 09:58:23.085369 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5689 09:58:23.088501 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5690 09:58:23.088623 ==
5691 09:58:23.092072 Dram Type= 6, Freq= 0, CH_1, rank 0
5692 09:58:23.095357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5693 09:58:23.095455 ==
5694 09:58:23.098445 DQS Delay:
5695 09:58:23.098545 DQS0 = 0, DQS1 = 0
5696 09:58:23.101544 DQM Delay:
5697 09:58:23.101652 DQM0 = 103, DQM1 = 92
5698 09:58:23.105152 DQ Delay:
5699 09:58:23.108748 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =103
5700 09:58:23.108847 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5701 09:58:23.111657 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =79
5702 09:58:23.118491 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5703 09:58:23.118623
5704 09:58:23.118692
5705 09:58:23.118753 ==
5706 09:58:23.121579 Dram Type= 6, Freq= 0, CH_1, rank 0
5707 09:58:23.124711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5708 09:58:23.124835 ==
5709 09:58:23.124937
5710 09:58:23.125030
5711 09:58:23.128492 TX Vref Scan disable
5712 09:58:23.128607 == TX Byte 0 ==
5713 09:58:23.134467 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5714 09:58:23.137890 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5715 09:58:23.138017 == TX Byte 1 ==
5716 09:58:23.144886 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5717 09:58:23.147783 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5718 09:58:23.147985 ==
5719 09:58:23.151452 Dram Type= 6, Freq= 0, CH_1, rank 0
5720 09:58:23.154485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5721 09:58:23.154573 ==
5722 09:58:23.157971
5723 09:58:23.158131
5724 09:58:23.158200 TX Vref Scan disable
5725 09:58:23.161533 == TX Byte 0 ==
5726 09:58:23.164449 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5727 09:58:23.171157 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5728 09:58:23.171291 == TX Byte 1 ==
5729 09:58:23.174203 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5730 09:58:23.180991 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5731 09:58:23.181143
5732 09:58:23.181244 [DATLAT]
5733 09:58:23.181337 Freq=933, CH1 RK0
5734 09:58:23.181443
5735 09:58:23.184642 DATLAT Default: 0xd
5736 09:58:23.184743 0, 0xFFFF, sum = 0
5737 09:58:23.187714 1, 0xFFFF, sum = 0
5738 09:58:23.190819 2, 0xFFFF, sum = 0
5739 09:58:23.190965 3, 0xFFFF, sum = 0
5740 09:58:23.194302 4, 0xFFFF, sum = 0
5741 09:58:23.194395 5, 0xFFFF, sum = 0
5742 09:58:23.197418 6, 0xFFFF, sum = 0
5743 09:58:23.197524 7, 0xFFFF, sum = 0
5744 09:58:23.200974 8, 0xFFFF, sum = 0
5745 09:58:23.201057 9, 0xFFFF, sum = 0
5746 09:58:23.204144 10, 0x0, sum = 1
5747 09:58:23.204234 11, 0x0, sum = 2
5748 09:58:23.207290 12, 0x0, sum = 3
5749 09:58:23.207386 13, 0x0, sum = 4
5750 09:58:23.207476 best_step = 11
5751 09:58:23.210950
5752 09:58:23.211096 ==
5753 09:58:23.213939 Dram Type= 6, Freq= 0, CH_1, rank 0
5754 09:58:23.217549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5755 09:58:23.217661 ==
5756 09:58:23.217752 RX Vref Scan: 1
5757 09:58:23.217849
5758 09:58:23.221070 RX Vref 0 -> 0, step: 1
5759 09:58:23.221172
5760 09:58:23.224102 RX Delay -69 -> 252, step: 4
5761 09:58:23.224200
5762 09:58:23.227269 Set Vref, RX VrefLevel [Byte0]: 51
5763 09:58:23.230336 [Byte1]: 53
5764 09:58:23.233546
5765 09:58:23.233641 Final RX Vref Byte 0 = 51 to rank0
5766 09:58:23.237293 Final RX Vref Byte 1 = 53 to rank0
5767 09:58:23.240351 Final RX Vref Byte 0 = 51 to rank1
5768 09:58:23.243827 Final RX Vref Byte 1 = 53 to rank1==
5769 09:58:23.246856 Dram Type= 6, Freq= 0, CH_1, rank 0
5770 09:58:23.253548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5771 09:58:23.253673 ==
5772 09:58:23.253749 DQS Delay:
5773 09:58:23.256854 DQS0 = 0, DQS1 = 0
5774 09:58:23.256946 DQM Delay:
5775 09:58:23.257014 DQM0 = 101, DQM1 = 93
5776 09:58:23.260645 DQ Delay:
5777 09:58:23.263625 DQ0 =104, DQ1 =98, DQ2 =92, DQ3 =98
5778 09:58:23.266954 DQ4 =98, DQ5 =110, DQ6 =112, DQ7 =98
5779 09:58:23.269855 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =86
5780 09:58:23.273524 DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =102
5781 09:58:23.273629
5782 09:58:23.273698
5783 09:58:23.280132 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d0c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 412 ps
5784 09:58:23.283543 CH1 RK0: MR19=505, MR18=1D0C
5785 09:58:23.290208 CH1_RK0: MR19=0x505, MR18=0x1D0C, DQSOSC=412, MR23=63, INC=63, DEC=42
5786 09:58:23.290333
5787 09:58:23.293261 ----->DramcWriteLeveling(PI) begin...
5788 09:58:23.293353 ==
5789 09:58:23.296374 Dram Type= 6, Freq= 0, CH_1, rank 1
5790 09:58:23.300174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5791 09:58:23.300293 ==
5792 09:58:23.303524 Write leveling (Byte 0): 30 => 30
5793 09:58:23.306491 Write leveling (Byte 1): 31 => 31
5794 09:58:23.310197 DramcWriteLeveling(PI) end<-----
5795 09:58:23.310296
5796 09:58:23.310366 ==
5797 09:58:23.313277 Dram Type= 6, Freq= 0, CH_1, rank 1
5798 09:58:23.319593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5799 09:58:23.319750 ==
5800 09:58:23.319859 [Gating] SW mode calibration
5801 09:58:23.329589 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5802 09:58:23.332708 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5803 09:58:23.339617 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5804 09:58:23.342846 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5805 09:58:23.345925 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5806 09:58:23.352301 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5807 09:58:23.355914 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5808 09:58:23.375161 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5809 09:58:23.375354 0 14 24 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
5810 09:58:23.375458 0 14 28 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
5811 09:58:23.375552 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5812 09:58:23.378801 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5813 09:58:23.381983 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5814 09:58:23.385448 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5815 09:58:23.392343 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5816 09:58:23.395224 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5817 09:58:23.398905 0 15 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
5818 09:58:23.405523 0 15 28 | B1->B0 | 3d3d 3333 | 0 1 | (0 0) (0 0)
5819 09:58:23.408559 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5820 09:58:23.412160 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5821 09:58:23.415264 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5822 09:58:23.422193 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 09:58:23.425279 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5824 09:58:23.431683 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 09:58:23.435078 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5826 09:58:23.438250 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5827 09:58:23.444992 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 09:58:23.448166 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 09:58:23.451795 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 09:58:23.454797 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 09:58:23.461435 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 09:58:23.465101 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 09:58:23.468259 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 09:58:23.474428 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 09:58:23.478196 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 09:58:23.484424 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 09:58:23.487772 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 09:58:23.490954 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 09:58:23.494176 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 09:58:23.501141 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 09:58:23.504348 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5842 09:58:23.507767 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5843 09:58:23.511227 Total UI for P1: 0, mck2ui 16
5844 09:58:23.514079 best dqsien dly found for B0: ( 1, 2, 26)
5845 09:58:23.517663 Total UI for P1: 0, mck2ui 16
5846 09:58:23.520775 best dqsien dly found for B1: ( 1, 2, 24)
5847 09:58:23.523941 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5848 09:58:23.530870 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5849 09:58:23.531011
5850 09:58:23.533840 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5851 09:58:23.537508 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5852 09:58:23.540400 [Gating] SW calibration Done
5853 09:58:23.540502 ==
5854 09:58:23.543811 Dram Type= 6, Freq= 0, CH_1, rank 1
5855 09:58:23.546893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5856 09:58:23.546992 ==
5857 09:58:23.550572 RX Vref Scan: 0
5858 09:58:23.550678
5859 09:58:23.550767 RX Vref 0 -> 0, step: 1
5860 09:58:23.550847
5861 09:58:23.553627 RX Delay -80 -> 252, step: 8
5862 09:58:23.557370 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5863 09:58:23.564112 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5864 09:58:23.567068 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5865 09:58:23.570177 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5866 09:58:23.573839 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5867 09:58:23.576780 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5868 09:58:23.580488 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5869 09:58:23.583633 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5870 09:58:23.590498 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5871 09:58:23.593441 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5872 09:58:23.596910 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5873 09:58:23.600104 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5874 09:58:23.603166 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5875 09:58:23.610166 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5876 09:58:23.613132 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5877 09:58:23.616493 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5878 09:58:23.616595 ==
5879 09:58:23.619918 Dram Type= 6, Freq= 0, CH_1, rank 1
5880 09:58:23.623158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5881 09:58:23.623256 ==
5882 09:58:23.626225 DQS Delay:
5883 09:58:23.626323 DQS0 = 0, DQS1 = 0
5884 09:58:23.629817 DQM Delay:
5885 09:58:23.629930 DQM0 = 99, DQM1 = 91
5886 09:58:23.630016 DQ Delay:
5887 09:58:23.632878 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5888 09:58:23.636601 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
5889 09:58:23.639582 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =83
5890 09:58:23.642735 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5891 09:58:23.642827
5892 09:58:23.646336
5893 09:58:23.646430 ==
5894 09:58:23.649230 Dram Type= 6, Freq= 0, CH_1, rank 1
5895 09:58:23.652659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5896 09:58:23.652760 ==
5897 09:58:23.652849
5898 09:58:23.652928
5899 09:58:23.656396 TX Vref Scan disable
5900 09:58:23.656508 == TX Byte 0 ==
5901 09:58:23.662711 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5902 09:58:23.666261 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5903 09:58:23.666361 == TX Byte 1 ==
5904 09:58:23.672787 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5905 09:58:23.675839 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5906 09:58:23.675959 ==
5907 09:58:23.678917 Dram Type= 6, Freq= 0, CH_1, rank 1
5908 09:58:23.682070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5909 09:58:23.682173 ==
5910 09:58:23.682262
5911 09:58:23.682344
5912 09:58:23.685729 TX Vref Scan disable
5913 09:58:23.688884 == TX Byte 0 ==
5914 09:58:23.691958 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5915 09:58:23.695658 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5916 09:58:23.698771 == TX Byte 1 ==
5917 09:58:23.702182 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5918 09:58:23.705605 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5919 09:58:23.708690
5920 09:58:23.708812 [DATLAT]
5921 09:58:23.708918 Freq=933, CH1 RK1
5922 09:58:23.709009
5923 09:58:23.712409 DATLAT Default: 0xb
5924 09:58:23.712527 0, 0xFFFF, sum = 0
5925 09:58:23.715142 1, 0xFFFF, sum = 0
5926 09:58:23.715227 2, 0xFFFF, sum = 0
5927 09:58:23.718765 3, 0xFFFF, sum = 0
5928 09:58:23.718859 4, 0xFFFF, sum = 0
5929 09:58:23.721781 5, 0xFFFF, sum = 0
5930 09:58:23.725530 6, 0xFFFF, sum = 0
5931 09:58:23.725646 7, 0xFFFF, sum = 0
5932 09:58:23.728871 8, 0xFFFF, sum = 0
5933 09:58:23.728958 9, 0xFFFF, sum = 0
5934 09:58:23.731689 10, 0x0, sum = 1
5935 09:58:23.731787 11, 0x0, sum = 2
5936 09:58:23.731872 12, 0x0, sum = 3
5937 09:58:23.735015 13, 0x0, sum = 4
5938 09:58:23.735148 best_step = 11
5939 09:58:23.735289
5940 09:58:23.738163 ==
5941 09:58:23.742002 Dram Type= 6, Freq= 0, CH_1, rank 1
5942 09:58:23.745108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5943 09:58:23.745197 ==
5944 09:58:23.745265 RX Vref Scan: 0
5945 09:58:23.745330
5946 09:58:23.748073 RX Vref 0 -> 0, step: 1
5947 09:58:23.748153
5948 09:58:23.751917 RX Delay -61 -> 252, step: 4
5949 09:58:23.758139 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
5950 09:58:23.761773 iDelay=207, Bit 1, Center 96 (7 ~ 186) 180
5951 09:58:23.764749 iDelay=207, Bit 2, Center 88 (-1 ~ 178) 180
5952 09:58:23.767801 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
5953 09:58:23.771431 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
5954 09:58:23.774407 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
5955 09:58:23.781735 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
5956 09:58:23.784682 iDelay=207, Bit 7, Center 96 (3 ~ 190) 188
5957 09:58:23.787768 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
5958 09:58:23.791453 iDelay=207, Bit 9, Center 82 (-9 ~ 174) 184
5959 09:58:23.794474 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
5960 09:58:23.797654 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
5961 09:58:23.804547 iDelay=207, Bit 12, Center 104 (15 ~ 194) 180
5962 09:58:23.807402 iDelay=207, Bit 13, Center 98 (7 ~ 190) 184
5963 09:58:23.810810 iDelay=207, Bit 14, Center 98 (7 ~ 190) 184
5964 09:58:23.814530 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
5965 09:58:23.814630 ==
5966 09:58:23.817578 Dram Type= 6, Freq= 0, CH_1, rank 1
5967 09:58:23.823782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5968 09:58:23.823954 ==
5969 09:58:23.824068 DQS Delay:
5970 09:58:23.827346 DQS0 = 0, DQS1 = 0
5971 09:58:23.827454 DQM Delay:
5972 09:58:23.827566 DQM0 = 100, DQM1 = 93
5973 09:58:23.830531 DQ Delay:
5974 09:58:23.834218 DQ0 =104, DQ1 =96, DQ2 =88, DQ3 =98
5975 09:58:23.837252 DQ4 =98, DQ5 =110, DQ6 =114, DQ7 =96
5976 09:58:23.840328 DQ8 =82, DQ9 =82, DQ10 =94, DQ11 =84
5977 09:58:23.844026 DQ12 =104, DQ13 =98, DQ14 =98, DQ15 =102
5978 09:58:23.844166
5979 09:58:23.844269
5980 09:58:23.850376 [DQSOSCAuto] RK1, (LSB)MR18= 0xc06, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 418 ps
5981 09:58:23.853546 CH1 RK1: MR19=505, MR18=C06
5982 09:58:23.860472 CH1_RK1: MR19=0x505, MR18=0xC06, DQSOSC=418, MR23=63, INC=62, DEC=41
5983 09:58:23.863522 [RxdqsGatingPostProcess] freq 933
5984 09:58:23.870467 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5985 09:58:23.870601 best DQS0 dly(2T, 0.5T) = (0, 10)
5986 09:58:23.873547 best DQS1 dly(2T, 0.5T) = (0, 10)
5987 09:58:23.876606 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5988 09:58:23.880271 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5989 09:58:23.883115 best DQS0 dly(2T, 0.5T) = (0, 10)
5990 09:58:23.886493 best DQS1 dly(2T, 0.5T) = (0, 10)
5991 09:58:23.890290 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5992 09:58:23.893402 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5993 09:58:23.896412 Pre-setting of DQS Precalculation
5994 09:58:23.903410 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5995 09:58:23.909524 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5996 09:58:23.916440 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5997 09:58:23.916591
5998 09:58:23.916663
5999 09:58:23.919625 [Calibration Summary] 1866 Mbps
6000 09:58:23.919723 CH 0, Rank 0
6001 09:58:23.922658 SW Impedance : PASS
6002 09:58:23.926302 DUTY Scan : NO K
6003 09:58:23.926392 ZQ Calibration : PASS
6004 09:58:23.929678 Jitter Meter : NO K
6005 09:58:23.932648 CBT Training : PASS
6006 09:58:23.932756 Write leveling : PASS
6007 09:58:23.935916 RX DQS gating : PASS
6008 09:58:23.939500 RX DQ/DQS(RDDQC) : PASS
6009 09:58:23.939593 TX DQ/DQS : PASS
6010 09:58:23.942605 RX DATLAT : PASS
6011 09:58:23.942714 RX DQ/DQS(Engine): PASS
6012 09:58:23.945840 TX OE : NO K
6013 09:58:23.945930 All Pass.
6014 09:58:23.946012
6015 09:58:23.949467 CH 0, Rank 1
6016 09:58:23.952283 SW Impedance : PASS
6017 09:58:23.952377 DUTY Scan : NO K
6018 09:58:23.956071 ZQ Calibration : PASS
6019 09:58:23.956169 Jitter Meter : NO K
6020 09:58:23.959286 CBT Training : PASS
6021 09:58:23.962531 Write leveling : PASS
6022 09:58:23.962633 RX DQS gating : PASS
6023 09:58:23.965661 RX DQ/DQS(RDDQC) : PASS
6024 09:58:23.968689 TX DQ/DQS : PASS
6025 09:58:23.968808 RX DATLAT : PASS
6026 09:58:23.972159 RX DQ/DQS(Engine): PASS
6027 09:58:23.975414 TX OE : NO K
6028 09:58:23.975509 All Pass.
6029 09:58:23.975610
6030 09:58:23.975707 CH 1, Rank 0
6031 09:58:23.978478 SW Impedance : PASS
6032 09:58:23.982163 DUTY Scan : NO K
6033 09:58:23.982273 ZQ Calibration : PASS
6034 09:58:23.985315 Jitter Meter : NO K
6035 09:58:23.988285 CBT Training : PASS
6036 09:58:23.988373 Write leveling : PASS
6037 09:58:23.991807 RX DQS gating : PASS
6038 09:58:23.995352 RX DQ/DQS(RDDQC) : PASS
6039 09:58:23.995456 TX DQ/DQS : PASS
6040 09:58:23.998752 RX DATLAT : PASS
6041 09:58:24.001828 RX DQ/DQS(Engine): PASS
6042 09:58:24.001919 TX OE : NO K
6043 09:58:24.005067 All Pass.
6044 09:58:24.005179
6045 09:58:24.005279 CH 1, Rank 1
6046 09:58:24.008764 SW Impedance : PASS
6047 09:58:24.008882 DUTY Scan : NO K
6048 09:58:24.011944 ZQ Calibration : PASS
6049 09:58:24.015139 Jitter Meter : NO K
6050 09:58:24.015225 CBT Training : PASS
6051 09:58:24.018321 Write leveling : PASS
6052 09:58:24.021714 RX DQS gating : PASS
6053 09:58:24.021803 RX DQ/DQS(RDDQC) : PASS
6054 09:58:24.025125 TX DQ/DQS : PASS
6055 09:58:24.028219 RX DATLAT : PASS
6056 09:58:24.028337 RX DQ/DQS(Engine): PASS
6057 09:58:24.031281 TX OE : NO K
6058 09:58:24.031394 All Pass.
6059 09:58:24.031487
6060 09:58:24.034905 DramC Write-DBI off
6061 09:58:24.037882 PER_BANK_REFRESH: Hybrid Mode
6062 09:58:24.037964 TX_TRACKING: ON
6063 09:58:24.048303 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6064 09:58:24.051440 [FAST_K] Save calibration result to emmc
6065 09:58:24.055032 dramc_set_vcore_voltage set vcore to 650000
6066 09:58:24.058213 Read voltage for 400, 6
6067 09:58:24.058317 Vio18 = 0
6068 09:58:24.058387 Vcore = 650000
6069 09:58:24.061101 Vdram = 0
6070 09:58:24.061213 Vddq = 0
6071 09:58:24.061310 Vmddr = 0
6072 09:58:24.067791 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6073 09:58:24.071424 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6074 09:58:24.074530 MEM_TYPE=3, freq_sel=20
6075 09:58:24.077620 sv_algorithm_assistance_LP4_800
6076 09:58:24.081101 ============ PULL DRAM RESETB DOWN ============
6077 09:58:24.084425 ========== PULL DRAM RESETB DOWN end =========
6078 09:58:24.091311 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6079 09:58:24.094595 ===================================
6080 09:58:24.094719 LPDDR4 DRAM CONFIGURATION
6081 09:58:24.097970 ===================================
6082 09:58:24.100832 EX_ROW_EN[0] = 0x0
6083 09:58:24.104241 EX_ROW_EN[1] = 0x0
6084 09:58:24.104377 LP4Y_EN = 0x0
6085 09:58:24.107786 WORK_FSP = 0x0
6086 09:58:24.107904 WL = 0x2
6087 09:58:24.110883 RL = 0x2
6088 09:58:24.110980 BL = 0x2
6089 09:58:24.114121 RPST = 0x0
6090 09:58:24.114212 RD_PRE = 0x0
6091 09:58:24.117856 WR_PRE = 0x1
6092 09:58:24.117952 WR_PST = 0x0
6093 09:58:24.120975 DBI_WR = 0x0
6094 09:58:24.121064 DBI_RD = 0x0
6095 09:58:24.123937 OTF = 0x1
6096 09:58:24.127593 ===================================
6097 09:58:24.130490 ===================================
6098 09:58:24.130615 ANA top config
6099 09:58:24.133795 ===================================
6100 09:58:24.137432 DLL_ASYNC_EN = 0
6101 09:58:24.140536 ALL_SLAVE_EN = 1
6102 09:58:24.143780 NEW_RANK_MODE = 1
6103 09:58:24.143876 DLL_IDLE_MODE = 1
6104 09:58:24.147144 LP45_APHY_COMB_EN = 1
6105 09:58:24.150401 TX_ODT_DIS = 1
6106 09:58:24.153876 NEW_8X_MODE = 1
6107 09:58:24.156901 ===================================
6108 09:58:24.160386 ===================================
6109 09:58:24.163571 data_rate = 800
6110 09:58:24.167105 CKR = 1
6111 09:58:24.167223 DQ_P2S_RATIO = 4
6112 09:58:24.170079 ===================================
6113 09:58:24.173704 CA_P2S_RATIO = 4
6114 09:58:24.176787 DQ_CA_OPEN = 0
6115 09:58:24.179902 DQ_SEMI_OPEN = 1
6116 09:58:24.183652 CA_SEMI_OPEN = 1
6117 09:58:24.186694 CA_FULL_RATE = 0
6118 09:58:24.186788 DQ_CKDIV4_EN = 0
6119 09:58:24.189679 CA_CKDIV4_EN = 1
6120 09:58:24.193097 CA_PREDIV_EN = 0
6121 09:58:24.196885 PH8_DLY = 0
6122 09:58:24.199909 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6123 09:58:24.203503 DQ_AAMCK_DIV = 0
6124 09:58:24.203605 CA_AAMCK_DIV = 0
6125 09:58:24.206457 CA_ADMCK_DIV = 4
6126 09:58:24.209989 DQ_TRACK_CA_EN = 0
6127 09:58:24.213286 CA_PICK = 800
6128 09:58:24.216325 CA_MCKIO = 400
6129 09:58:24.219692 MCKIO_SEMI = 400
6130 09:58:24.223408 PLL_FREQ = 3016
6131 09:58:24.223505 DQ_UI_PI_RATIO = 32
6132 09:58:24.226277 CA_UI_PI_RATIO = 32
6133 09:58:24.230083 ===================================
6134 09:58:24.233117 ===================================
6135 09:58:24.236149 memory_type:LPDDR4
6136 09:58:24.239654 GP_NUM : 10
6137 09:58:24.239746 SRAM_EN : 1
6138 09:58:24.243052 MD32_EN : 0
6139 09:58:24.246549 ===================================
6140 09:58:24.249636 [ANA_INIT] >>>>>>>>>>>>>>
6141 09:58:24.249730 <<<<<< [CONFIGURE PHASE]: ANA_TX
6142 09:58:24.252714 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6143 09:58:24.256273 ===================================
6144 09:58:24.259781 data_rate = 800,PCW = 0X7400
6145 09:58:24.263069 ===================================
6146 09:58:24.266416 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6147 09:58:24.272849 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6148 09:58:24.282596 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6149 09:58:24.289400 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6150 09:58:24.292633 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6151 09:58:24.295687 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6152 09:58:24.298978 [ANA_INIT] flow start
6153 09:58:24.299108 [ANA_INIT] PLL >>>>>>>>
6154 09:58:24.302513 [ANA_INIT] PLL <<<<<<<<
6155 09:58:24.305643 [ANA_INIT] MIDPI >>>>>>>>
6156 09:58:24.305740 [ANA_INIT] MIDPI <<<<<<<<
6157 09:58:24.309356 [ANA_INIT] DLL >>>>>>>>
6158 09:58:24.312531 [ANA_INIT] flow end
6159 09:58:24.315673 ============ LP4 DIFF to SE enter ============
6160 09:58:24.319005 ============ LP4 DIFF to SE exit ============
6161 09:58:24.322584 [ANA_INIT] <<<<<<<<<<<<<
6162 09:58:24.325588 [Flow] Enable top DCM control >>>>>
6163 09:58:24.328713 [Flow] Enable top DCM control <<<<<
6164 09:58:24.332440 Enable DLL master slave shuffle
6165 09:58:24.335398 ==============================================================
6166 09:58:24.338594 Gating Mode config
6167 09:58:24.345247 ==============================================================
6168 09:58:24.345375 Config description:
6169 09:58:24.355365 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6170 09:58:24.361723 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6171 09:58:24.368346 SELPH_MODE 0: By rank 1: By Phase
6172 09:58:24.372002 ==============================================================
6173 09:58:24.374942 GAT_TRACK_EN = 0
6174 09:58:24.378315 RX_GATING_MODE = 2
6175 09:58:24.381895 RX_GATING_TRACK_MODE = 2
6176 09:58:24.384877 SELPH_MODE = 1
6177 09:58:24.388531 PICG_EARLY_EN = 1
6178 09:58:24.391641 VALID_LAT_VALUE = 1
6179 09:58:24.395368 ==============================================================
6180 09:58:24.398455 Enter into Gating configuration >>>>
6181 09:58:24.401545 Exit from Gating configuration <<<<
6182 09:58:24.405089 Enter into DVFS_PRE_config >>>>>
6183 09:58:24.418620 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6184 09:58:24.421577 Exit from DVFS_PRE_config <<<<<
6185 09:58:24.421685 Enter into PICG configuration >>>>
6186 09:58:24.424701 Exit from PICG configuration <<<<
6187 09:58:24.428165 [RX_INPUT] configuration >>>>>
6188 09:58:24.431646 [RX_INPUT] configuration <<<<<
6189 09:58:24.437895 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6190 09:58:24.441630 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6191 09:58:24.448250 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6192 09:58:24.454422 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6193 09:58:24.461213 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6194 09:58:24.467880 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6195 09:58:24.471020 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6196 09:58:24.474514 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6197 09:58:24.477606 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6198 09:58:24.484119 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6199 09:58:24.487643 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6200 09:58:24.491285 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6201 09:58:24.494264 ===================================
6202 09:58:24.497389 LPDDR4 DRAM CONFIGURATION
6203 09:58:24.501262 ===================================
6204 09:58:24.504375 EX_ROW_EN[0] = 0x0
6205 09:58:24.504495 EX_ROW_EN[1] = 0x0
6206 09:58:24.507478 LP4Y_EN = 0x0
6207 09:58:24.507586 WORK_FSP = 0x0
6208 09:58:24.511293 WL = 0x2
6209 09:58:24.511403 RL = 0x2
6210 09:58:24.514097 BL = 0x2
6211 09:58:24.514200 RPST = 0x0
6212 09:58:24.517504 RD_PRE = 0x0
6213 09:58:24.517584 WR_PRE = 0x1
6214 09:58:24.521061 WR_PST = 0x0
6215 09:58:24.521173 DBI_WR = 0x0
6216 09:58:24.523941 DBI_RD = 0x0
6217 09:58:24.524049 OTF = 0x1
6218 09:58:24.527569 ===================================
6219 09:58:24.534153 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6220 09:58:24.537538 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6221 09:58:24.540501 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6222 09:58:24.543759 ===================================
6223 09:58:24.547509 LPDDR4 DRAM CONFIGURATION
6224 09:58:24.550555 ===================================
6225 09:58:24.553636 EX_ROW_EN[0] = 0x10
6226 09:58:24.553716 EX_ROW_EN[1] = 0x0
6227 09:58:24.557431 LP4Y_EN = 0x0
6228 09:58:24.557511 WORK_FSP = 0x0
6229 09:58:24.560487 WL = 0x2
6230 09:58:24.560562 RL = 0x2
6231 09:58:24.563935 BL = 0x2
6232 09:58:24.564037 RPST = 0x0
6233 09:58:24.567249 RD_PRE = 0x0
6234 09:58:24.567362 WR_PRE = 0x1
6235 09:58:24.570521 WR_PST = 0x0
6236 09:58:24.570600 DBI_WR = 0x0
6237 09:58:24.573883 DBI_RD = 0x0
6238 09:58:24.573996 OTF = 0x1
6239 09:58:24.576751 ===================================
6240 09:58:24.583378 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6241 09:58:24.588651 nWR fixed to 30
6242 09:58:24.591715 [ModeRegInit_LP4] CH0 RK0
6243 09:58:24.591799 [ModeRegInit_LP4] CH0 RK1
6244 09:58:24.595349 [ModeRegInit_LP4] CH1 RK0
6245 09:58:24.598319 [ModeRegInit_LP4] CH1 RK1
6246 09:58:24.598431 match AC timing 19
6247 09:58:24.604827 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6248 09:58:24.608157 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6249 09:58:24.611748 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6250 09:58:24.618112 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6251 09:58:24.621817 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6252 09:58:24.621910 ==
6253 09:58:24.624685 Dram Type= 6, Freq= 0, CH_0, rank 0
6254 09:58:24.627891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6255 09:58:24.627971 ==
6256 09:58:24.635317 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6257 09:58:24.641321 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6258 09:58:24.644617 [CA 0] Center 36 (8~64) winsize 57
6259 09:58:24.647666 [CA 1] Center 36 (8~64) winsize 57
6260 09:58:24.651379 [CA 2] Center 36 (8~64) winsize 57
6261 09:58:24.654478 [CA 3] Center 36 (8~64) winsize 57
6262 09:58:24.657491 [CA 4] Center 36 (8~64) winsize 57
6263 09:58:24.661232 [CA 5] Center 36 (8~64) winsize 57
6264 09:58:24.661337
6265 09:58:24.664250 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6266 09:58:24.664325
6267 09:58:24.667816 [CATrainingPosCal] consider 1 rank data
6268 09:58:24.670985 u2DelayCellTimex100 = 270/100 ps
6269 09:58:24.674411 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 09:58:24.677751 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 09:58:24.680896 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 09:58:24.684325 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 09:58:24.687316 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 09:58:24.690488 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 09:58:24.690566
6276 09:58:24.697296 CA PerBit enable=1, Macro0, CA PI delay=36
6277 09:58:24.697421
6278 09:58:24.697496 [CBTSetCACLKResult] CA Dly = 36
6279 09:58:24.700314 CS Dly: 1 (0~32)
6280 09:58:24.700414 ==
6281 09:58:24.704054 Dram Type= 6, Freq= 0, CH_0, rank 1
6282 09:58:24.707055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6283 09:58:24.707160 ==
6284 09:58:24.713358 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6285 09:58:24.719973 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6286 09:58:24.723800 [CA 0] Center 36 (8~64) winsize 57
6287 09:58:24.726744 [CA 1] Center 36 (8~64) winsize 57
6288 09:58:24.729887 [CA 2] Center 36 (8~64) winsize 57
6289 09:58:24.733526 [CA 3] Center 36 (8~64) winsize 57
6290 09:58:24.736965 [CA 4] Center 36 (8~64) winsize 57
6291 09:58:24.737073 [CA 5] Center 36 (8~64) winsize 57
6292 09:58:24.740101
6293 09:58:24.743095 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6294 09:58:24.743200
6295 09:58:24.746853 [CATrainingPosCal] consider 2 rank data
6296 09:58:24.749783 u2DelayCellTimex100 = 270/100 ps
6297 09:58:24.753200 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 09:58:24.756711 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 09:58:24.759816 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 09:58:24.762964 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 09:58:24.766583 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 09:58:24.769710 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 09:58:24.769796
6304 09:58:24.772747 CA PerBit enable=1, Macro0, CA PI delay=36
6305 09:58:24.772845
6306 09:58:24.776379 [CBTSetCACLKResult] CA Dly = 36
6307 09:58:24.779665 CS Dly: 1 (0~32)
6308 09:58:24.779741
6309 09:58:24.782574 ----->DramcWriteLeveling(PI) begin...
6310 09:58:24.782649 ==
6311 09:58:24.785975 Dram Type= 6, Freq= 0, CH_0, rank 0
6312 09:58:24.789508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6313 09:58:24.789592 ==
6314 09:58:24.792487 Write leveling (Byte 0): 40 => 8
6315 09:58:24.795932 Write leveling (Byte 1): 32 => 0
6316 09:58:24.799097 DramcWriteLeveling(PI) end<-----
6317 09:58:24.799202
6318 09:58:24.799307 ==
6319 09:58:24.802867 Dram Type= 6, Freq= 0, CH_0, rank 0
6320 09:58:24.806032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6321 09:58:24.808969 ==
6322 09:58:24.809070 [Gating] SW mode calibration
6323 09:58:24.818878 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6324 09:58:24.821950 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6325 09:58:24.825823 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6326 09:58:24.832073 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6327 09:58:24.835214 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6328 09:58:24.838374 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6329 09:58:24.845360 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6330 09:58:24.848378 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6331 09:58:24.851456 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6332 09:58:24.858059 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6333 09:58:24.861446 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6334 09:58:24.864926 Total UI for P1: 0, mck2ui 16
6335 09:58:24.868057 best dqsien dly found for B0: ( 0, 14, 24)
6336 09:58:24.871515 Total UI for P1: 0, mck2ui 16
6337 09:58:24.874592 best dqsien dly found for B1: ( 0, 14, 24)
6338 09:58:24.877752 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6339 09:58:24.880890 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6340 09:58:24.880970
6341 09:58:24.887735 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6342 09:58:24.890688 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6343 09:58:24.890771 [Gating] SW calibration Done
6344 09:58:24.894077 ==
6345 09:58:24.897623 Dram Type= 6, Freq= 0, CH_0, rank 0
6346 09:58:24.900597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6347 09:58:24.900703 ==
6348 09:58:24.900799 RX Vref Scan: 0
6349 09:58:24.900887
6350 09:58:24.904320 RX Vref 0 -> 0, step: 1
6351 09:58:24.904419
6352 09:58:24.907502 RX Delay -410 -> 252, step: 16
6353 09:58:24.910797 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6354 09:58:24.917085 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6355 09:58:24.920400 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6356 09:58:24.924082 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6357 09:58:24.927323 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6358 09:58:24.934089 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6359 09:58:24.937031 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6360 09:58:24.940233 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6361 09:58:24.943316 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6362 09:58:24.950096 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6363 09:58:24.953609 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6364 09:58:24.956734 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6365 09:58:24.959675 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6366 09:58:24.966303 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6367 09:58:24.969710 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6368 09:58:24.973363 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6369 09:58:24.973509 ==
6370 09:58:24.976447 Dram Type= 6, Freq= 0, CH_0, rank 0
6371 09:58:24.982779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6372 09:58:24.982903 ==
6373 09:58:24.983008 DQS Delay:
6374 09:58:24.986457 DQS0 = 43, DQS1 = 59
6375 09:58:24.986576 DQM Delay:
6376 09:58:24.989710 DQM0 = 10, DQM1 = 12
6377 09:58:24.989787 DQ Delay:
6378 09:58:24.992693 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6379 09:58:24.996417 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6380 09:58:24.996495 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6381 09:58:25.002833 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6382 09:58:25.002957
6383 09:58:25.003051
6384 09:58:25.003160 ==
6385 09:58:25.006418 Dram Type= 6, Freq= 0, CH_0, rank 0
6386 09:58:25.009480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6387 09:58:25.009555 ==
6388 09:58:25.009695
6389 09:58:25.009770
6390 09:58:25.012452 TX Vref Scan disable
6391 09:58:25.012548 == TX Byte 0 ==
6392 09:58:25.019354 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6393 09:58:25.022494 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6394 09:58:25.022581 == TX Byte 1 ==
6395 09:58:25.029377 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6396 09:58:25.032837 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6397 09:58:25.032922 ==
6398 09:58:25.035565 Dram Type= 6, Freq= 0, CH_0, rank 0
6399 09:58:25.038990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6400 09:58:25.039069 ==
6401 09:58:25.039133
6402 09:58:25.039192
6403 09:58:25.042595 TX Vref Scan disable
6404 09:58:25.042714 == TX Byte 0 ==
6405 09:58:25.048818 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6406 09:58:25.052481 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6407 09:58:25.052566 == TX Byte 1 ==
6408 09:58:25.058974 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6409 09:58:25.062451 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6410 09:58:25.062562
6411 09:58:25.062666 [DATLAT]
6412 09:58:25.065530 Freq=400, CH0 RK0
6413 09:58:25.065618
6414 09:58:25.065693 DATLAT Default: 0xf
6415 09:58:25.068633 0, 0xFFFF, sum = 0
6416 09:58:25.068743 1, 0xFFFF, sum = 0
6417 09:58:25.072201 2, 0xFFFF, sum = 0
6418 09:58:25.072309 3, 0xFFFF, sum = 0
6419 09:58:25.075540 4, 0xFFFF, sum = 0
6420 09:58:25.075651 5, 0xFFFF, sum = 0
6421 09:58:25.078508 6, 0xFFFF, sum = 0
6422 09:58:25.082161 7, 0xFFFF, sum = 0
6423 09:58:25.082246 8, 0xFFFF, sum = 0
6424 09:58:25.085234 9, 0xFFFF, sum = 0
6425 09:58:25.085351 10, 0xFFFF, sum = 0
6426 09:58:25.088399 11, 0xFFFF, sum = 0
6427 09:58:25.088516 12, 0xFFFF, sum = 0
6428 09:58:25.092083 13, 0x0, sum = 1
6429 09:58:25.092192 14, 0x0, sum = 2
6430 09:58:25.095247 15, 0x0, sum = 3
6431 09:58:25.095354 16, 0x0, sum = 4
6432 09:58:25.095450 best_step = 14
6433 09:58:25.098903
6434 09:58:25.099006 ==
6435 09:58:25.101993 Dram Type= 6, Freq= 0, CH_0, rank 0
6436 09:58:25.105071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6437 09:58:25.105152 ==
6438 09:58:25.105228 RX Vref Scan: 1
6439 09:58:25.105317
6440 09:58:25.108700 RX Vref 0 -> 0, step: 1
6441 09:58:25.108778
6442 09:58:25.111987 RX Delay -359 -> 252, step: 8
6443 09:58:25.112095
6444 09:58:25.115066 Set Vref, RX VrefLevel [Byte0]: 55
6445 09:58:25.118002 [Byte1]: 48
6446 09:58:25.122466
6447 09:58:25.122576 Final RX Vref Byte 0 = 55 to rank0
6448 09:58:25.126001 Final RX Vref Byte 1 = 48 to rank0
6449 09:58:25.129138 Final RX Vref Byte 0 = 55 to rank1
6450 09:58:25.132270 Final RX Vref Byte 1 = 48 to rank1==
6451 09:58:25.135659 Dram Type= 6, Freq= 0, CH_0, rank 0
6452 09:58:25.142029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6453 09:58:25.142154 ==
6454 09:58:25.142253 DQS Delay:
6455 09:58:25.145448 DQS0 = 44, DQS1 = 60
6456 09:58:25.145529 DQM Delay:
6457 09:58:25.145596 DQM0 = 8, DQM1 = 13
6458 09:58:25.148707 DQ Delay:
6459 09:58:25.152086 DQ0 =12, DQ1 =12, DQ2 =0, DQ3 =4
6460 09:58:25.155597 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6461 09:58:25.155717 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6462 09:58:25.158655 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6463 09:58:25.162259
6464 09:58:25.162339
6465 09:58:25.168583 [DQSOSCAuto] RK0, (LSB)MR18= 0xc78b, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 385 ps
6466 09:58:25.172187 CH0 RK0: MR19=C0C, MR18=C78B
6467 09:58:25.178362 CH0_RK0: MR19=0xC0C, MR18=0xC78B, DQSOSC=385, MR23=63, INC=398, DEC=265
6468 09:58:25.178514 ==
6469 09:58:25.181873 Dram Type= 6, Freq= 0, CH_0, rank 1
6470 09:58:25.184657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6471 09:58:25.184741 ==
6472 09:58:25.188395 [Gating] SW mode calibration
6473 09:58:25.194642 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6474 09:58:25.201601 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6475 09:58:25.204761 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6476 09:58:25.208031 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6477 09:58:25.214588 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6478 09:58:25.218120 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6479 09:58:25.221085 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6480 09:58:25.227521 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6481 09:58:25.231071 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6482 09:58:25.234106 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6483 09:58:25.241037 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6484 09:58:25.243816 Total UI for P1: 0, mck2ui 16
6485 09:58:25.247517 best dqsien dly found for B0: ( 0, 14, 24)
6486 09:58:25.250475 Total UI for P1: 0, mck2ui 16
6487 09:58:25.254105 best dqsien dly found for B1: ( 0, 14, 24)
6488 09:58:25.257039 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6489 09:58:25.260398 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6490 09:58:25.260481
6491 09:58:25.263552 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6492 09:58:25.267231 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6493 09:58:25.270347 [Gating] SW calibration Done
6494 09:58:25.270453 ==
6495 09:58:25.274076 Dram Type= 6, Freq= 0, CH_0, rank 1
6496 09:58:25.277414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6497 09:58:25.277525 ==
6498 09:58:25.280169 RX Vref Scan: 0
6499 09:58:25.280261
6500 09:58:25.283930 RX Vref 0 -> 0, step: 1
6501 09:58:25.284033
6502 09:58:25.284101 RX Delay -410 -> 252, step: 16
6503 09:58:25.290719 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6504 09:58:25.293809 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6505 09:58:25.296935 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6506 09:58:25.303945 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6507 09:58:25.306906 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6508 09:58:25.310707 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6509 09:58:25.313777 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6510 09:58:25.319953 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6511 09:58:25.323638 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6512 09:58:25.327048 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6513 09:58:25.329729 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6514 09:58:25.336603 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6515 09:58:25.339979 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6516 09:58:25.343650 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6517 09:58:25.346546 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6518 09:58:25.353106 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6519 09:58:25.353278 ==
6520 09:58:25.356214 Dram Type= 6, Freq= 0, CH_0, rank 1
6521 09:58:25.359796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6522 09:58:25.359895 ==
6523 09:58:25.359963 DQS Delay:
6524 09:58:25.362743 DQS0 = 43, DQS1 = 59
6525 09:58:25.362837 DQM Delay:
6526 09:58:25.366323 DQM0 = 10, DQM1 = 16
6527 09:58:25.366439 DQ Delay:
6528 09:58:25.369923 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6529 09:58:25.372709 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6530 09:58:25.376457 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6531 09:58:25.379408 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6532 09:58:25.379523
6533 09:58:25.379617
6534 09:58:25.379724 ==
6535 09:58:25.383099 Dram Type= 6, Freq= 0, CH_0, rank 1
6536 09:58:25.385941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6537 09:58:25.386031 ==
6538 09:58:25.386107
6539 09:58:25.389320
6540 09:58:25.389415 TX Vref Scan disable
6541 09:58:25.392785 == TX Byte 0 ==
6542 09:58:25.395786 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6543 09:58:25.399520 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6544 09:58:25.402679 == TX Byte 1 ==
6545 09:58:25.405760 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6546 09:58:25.408933 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6547 09:58:25.409030 ==
6548 09:58:25.412664 Dram Type= 6, Freq= 0, CH_0, rank 1
6549 09:58:25.415869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6550 09:58:25.419038 ==
6551 09:58:25.419119
6552 09:58:25.419183
6553 09:58:25.419245 TX Vref Scan disable
6554 09:58:25.422601 == TX Byte 0 ==
6555 09:58:25.425737 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6556 09:58:25.428874 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6557 09:58:25.432518 == TX Byte 1 ==
6558 09:58:25.435408 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6559 09:58:25.438720 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6560 09:58:25.438801
6561 09:58:25.442084 [DATLAT]
6562 09:58:25.442166 Freq=400, CH0 RK1
6563 09:58:25.442236
6564 09:58:25.445303 DATLAT Default: 0xe
6565 09:58:25.445415 0, 0xFFFF, sum = 0
6566 09:58:25.448803 1, 0xFFFF, sum = 0
6567 09:58:25.448892 2, 0xFFFF, sum = 0
6568 09:58:25.452016 3, 0xFFFF, sum = 0
6569 09:58:25.452139 4, 0xFFFF, sum = 0
6570 09:58:25.455588 5, 0xFFFF, sum = 0
6571 09:58:25.455678 6, 0xFFFF, sum = 0
6572 09:58:25.458592 7, 0xFFFF, sum = 0
6573 09:58:25.458679 8, 0xFFFF, sum = 0
6574 09:58:25.462341 9, 0xFFFF, sum = 0
6575 09:58:25.462429 10, 0xFFFF, sum = 0
6576 09:58:25.465405 11, 0xFFFF, sum = 0
6577 09:58:25.468892 12, 0xFFFF, sum = 0
6578 09:58:25.468982 13, 0x0, sum = 1
6579 09:58:25.469092 14, 0x0, sum = 2
6580 09:58:25.471924 15, 0x0, sum = 3
6581 09:58:25.472014 16, 0x0, sum = 4
6582 09:58:25.475733 best_step = 14
6583 09:58:25.475845
6584 09:58:25.475947 ==
6585 09:58:25.478610 Dram Type= 6, Freq= 0, CH_0, rank 1
6586 09:58:25.482149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6587 09:58:25.482238 ==
6588 09:58:25.485262 RX Vref Scan: 0
6589 09:58:25.485369
6590 09:58:25.485475 RX Vref 0 -> 0, step: 1
6591 09:58:25.488404
6592 09:58:25.488486 RX Delay -359 -> 252, step: 8
6593 09:58:25.496969 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6594 09:58:25.500619 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6595 09:58:25.503308 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6596 09:58:25.506970 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6597 09:58:25.513758 iDelay=217, Bit 4, Center -40 (-279 ~ 200) 480
6598 09:58:25.516902 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6599 09:58:25.519929 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6600 09:58:25.523733 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6601 09:58:25.529970 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6602 09:58:25.533671 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6603 09:58:25.536666 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6604 09:58:25.543246 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6605 09:58:25.547155 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6606 09:58:25.550171 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6607 09:58:25.552863 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6608 09:58:25.559479 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6609 09:58:25.559568 ==
6610 09:58:25.563301 Dram Type= 6, Freq= 0, CH_0, rank 1
6611 09:58:25.566290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6612 09:58:25.566376 ==
6613 09:58:25.566441 DQS Delay:
6614 09:58:25.569522 DQS0 = 44, DQS1 = 60
6615 09:58:25.569606 DQM Delay:
6616 09:58:25.573078 DQM0 = 8, DQM1 = 15
6617 09:58:25.573159 DQ Delay:
6618 09:58:25.576069 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =8
6619 09:58:25.579758 DQ4 =4, DQ5 =0, DQ6 =16, DQ7 =16
6620 09:58:25.582869 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6621 09:58:25.586256 DQ12 =20, DQ13 =24, DQ14 =24, DQ15 =24
6622 09:58:25.586371
6623 09:58:25.586474
6624 09:58:25.592577 [DQSOSCAuto] RK1, (LSB)MR18= 0xbf49, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 386 ps
6625 09:58:25.596232 CH0 RK1: MR19=C0C, MR18=BF49
6626 09:58:25.602854 CH0_RK1: MR19=0xC0C, MR18=0xBF49, DQSOSC=386, MR23=63, INC=396, DEC=264
6627 09:58:25.605876 [RxdqsGatingPostProcess] freq 400
6628 09:58:25.612693 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6629 09:58:25.615735 best DQS0 dly(2T, 0.5T) = (0, 10)
6630 09:58:25.619449 best DQS1 dly(2T, 0.5T) = (0, 10)
6631 09:58:25.619570 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6632 09:58:25.622487 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6633 09:58:25.625651 best DQS0 dly(2T, 0.5T) = (0, 10)
6634 09:58:25.628798 best DQS1 dly(2T, 0.5T) = (0, 10)
6635 09:58:25.632565 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6636 09:58:25.635649 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6637 09:58:25.638837 Pre-setting of DQS Precalculation
6638 09:58:25.645655 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6639 09:58:25.645772 ==
6640 09:58:25.648863 Dram Type= 6, Freq= 0, CH_1, rank 0
6641 09:58:25.652012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6642 09:58:25.652130 ==
6643 09:58:25.658846 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6644 09:58:25.665658 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6645 09:58:25.668422 [CA 0] Center 36 (8~64) winsize 57
6646 09:58:25.668540 [CA 1] Center 36 (8~64) winsize 57
6647 09:58:25.671767 [CA 2] Center 36 (8~64) winsize 57
6648 09:58:25.675240 [CA 3] Center 36 (8~64) winsize 57
6649 09:58:25.678217 [CA 4] Center 36 (8~64) winsize 57
6650 09:58:25.681770 [CA 5] Center 36 (8~64) winsize 57
6651 09:58:25.681881
6652 09:58:25.685068 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6653 09:58:25.685176
6654 09:58:25.691522 [CATrainingPosCal] consider 1 rank data
6655 09:58:25.691639 u2DelayCellTimex100 = 270/100 ps
6656 09:58:25.695401 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 09:58:25.701854 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 09:58:25.705014 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 09:58:25.708578 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 09:58:25.711540 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 09:58:25.715124 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 09:58:25.715234
6663 09:58:25.718150 CA PerBit enable=1, Macro0, CA PI delay=36
6664 09:58:25.718259
6665 09:58:25.721532 [CBTSetCACLKResult] CA Dly = 36
6666 09:58:25.724577 CS Dly: 1 (0~32)
6667 09:58:25.724680 ==
6668 09:58:25.728226 Dram Type= 6, Freq= 0, CH_1, rank 1
6669 09:58:25.731294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6670 09:58:25.731405 ==
6671 09:58:25.738110 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6672 09:58:25.741509 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6673 09:58:25.744382 [CA 0] Center 36 (8~64) winsize 57
6674 09:58:25.748086 [CA 1] Center 36 (8~64) winsize 57
6675 09:58:25.751343 [CA 2] Center 36 (8~64) winsize 57
6676 09:58:25.754664 [CA 3] Center 36 (8~64) winsize 57
6677 09:58:25.757638 [CA 4] Center 36 (8~64) winsize 57
6678 09:58:25.761128 [CA 5] Center 36 (8~64) winsize 57
6679 09:58:25.761214
6680 09:58:25.764573 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6681 09:58:25.764682
6682 09:58:25.767573 [CATrainingPosCal] consider 2 rank data
6683 09:58:25.771149 u2DelayCellTimex100 = 270/100 ps
6684 09:58:25.774246 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 09:58:25.777492 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 09:58:25.784300 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 09:58:25.787464 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 09:58:25.790963 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 09:58:25.794548 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 09:58:25.794667
6691 09:58:25.797458 CA PerBit enable=1, Macro0, CA PI delay=36
6692 09:58:25.797565
6693 09:58:25.800952 [CBTSetCACLKResult] CA Dly = 36
6694 09:58:25.801065 CS Dly: 1 (0~32)
6695 09:58:25.801163
6696 09:58:25.804074 ----->DramcWriteLeveling(PI) begin...
6697 09:58:25.807302 ==
6698 09:58:25.810835 Dram Type= 6, Freq= 0, CH_1, rank 0
6699 09:58:25.813758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6700 09:58:25.813868 ==
6701 09:58:25.817184 Write leveling (Byte 0): 40 => 8
6702 09:58:25.820307 Write leveling (Byte 1): 32 => 0
6703 09:58:25.823901 DramcWriteLeveling(PI) end<-----
6704 09:58:25.824015
6705 09:58:25.824112 ==
6706 09:58:25.826820 Dram Type= 6, Freq= 0, CH_1, rank 0
6707 09:58:25.830203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6708 09:58:25.830309 ==
6709 09:58:25.833799 [Gating] SW mode calibration
6710 09:58:25.840148 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6711 09:58:25.846862 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6712 09:58:25.850077 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6713 09:58:25.853106 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6714 09:58:25.859985 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6715 09:58:25.862981 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6716 09:58:25.866689 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6717 09:58:25.873446 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6718 09:58:25.876283 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6719 09:58:25.879538 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6720 09:58:25.886590 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6721 09:58:25.886691 Total UI for P1: 0, mck2ui 16
6722 09:58:25.892885 best dqsien dly found for B0: ( 0, 14, 24)
6723 09:58:25.892974 Total UI for P1: 0, mck2ui 16
6724 09:58:25.899592 best dqsien dly found for B1: ( 0, 14, 24)
6725 09:58:25.902939 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6726 09:58:25.906370 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6727 09:58:25.906451
6728 09:58:25.909279 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6729 09:58:25.912989 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6730 09:58:25.916124 [Gating] SW calibration Done
6731 09:58:25.916230 ==
6732 09:58:25.919087 Dram Type= 6, Freq= 0, CH_1, rank 0
6733 09:58:25.922574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6734 09:58:25.922657 ==
6735 09:58:25.925804 RX Vref Scan: 0
6736 09:58:25.925884
6737 09:58:25.925948 RX Vref 0 -> 0, step: 1
6738 09:58:25.926015
6739 09:58:25.929349 RX Delay -410 -> 252, step: 16
6740 09:58:25.935478 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6741 09:58:25.939403 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6742 09:58:25.942417 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6743 09:58:25.946183 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6744 09:58:25.952309 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6745 09:58:25.956094 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6746 09:58:25.959126 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6747 09:58:25.962257 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6748 09:58:25.968757 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6749 09:58:25.972309 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6750 09:58:25.975351 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6751 09:58:25.978957 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6752 09:58:25.985450 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6753 09:58:25.988764 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6754 09:58:25.991896 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6755 09:58:25.998643 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6756 09:58:25.998740 ==
6757 09:58:26.001574 Dram Type= 6, Freq= 0, CH_1, rank 0
6758 09:58:26.004942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6759 09:58:26.005058 ==
6760 09:58:26.005162 DQS Delay:
6761 09:58:26.008490 DQS0 = 43, DQS1 = 51
6762 09:58:26.008598 DQM Delay:
6763 09:58:26.011508 DQM0 = 12, DQM1 = 14
6764 09:58:26.011597 DQ Delay:
6765 09:58:26.015035 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6766 09:58:26.018255 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6767 09:58:26.021533 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6768 09:58:26.024653 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6769 09:58:26.024771
6770 09:58:26.024874
6771 09:58:26.024964 ==
6772 09:58:26.028118 Dram Type= 6, Freq= 0, CH_1, rank 0
6773 09:58:26.031676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6774 09:58:26.031797 ==
6775 09:58:26.031898
6776 09:58:26.031989
6777 09:58:26.034775 TX Vref Scan disable
6778 09:58:26.037816 == TX Byte 0 ==
6779 09:58:26.041418 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6780 09:58:26.044252 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6781 09:58:26.047647 == TX Byte 1 ==
6782 09:58:26.051395 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6783 09:58:26.054533 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6784 09:58:26.054616 ==
6785 09:58:26.057689 Dram Type= 6, Freq= 0, CH_1, rank 0
6786 09:58:26.061303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6787 09:58:26.064376 ==
6788 09:58:26.064485
6789 09:58:26.064576
6790 09:58:26.064664 TX Vref Scan disable
6791 09:58:26.067566 == TX Byte 0 ==
6792 09:58:26.071299 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6793 09:58:26.074475 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6794 09:58:26.077706 == TX Byte 1 ==
6795 09:58:26.080748 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6796 09:58:26.084388 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6797 09:58:26.084562
6798 09:58:26.087339 [DATLAT]
6799 09:58:26.087454 Freq=400, CH1 RK0
6800 09:58:26.087543
6801 09:58:26.090783 DATLAT Default: 0xf
6802 09:58:26.090912 0, 0xFFFF, sum = 0
6803 09:58:26.094143 1, 0xFFFF, sum = 0
6804 09:58:26.094304 2, 0xFFFF, sum = 0
6805 09:58:26.097172 3, 0xFFFF, sum = 0
6806 09:58:26.097293 4, 0xFFFF, sum = 0
6807 09:58:26.100893 5, 0xFFFF, sum = 0
6808 09:58:26.100976 6, 0xFFFF, sum = 0
6809 09:58:26.103875 7, 0xFFFF, sum = 0
6810 09:58:26.103959 8, 0xFFFF, sum = 0
6811 09:58:26.107092 9, 0xFFFF, sum = 0
6812 09:58:26.107174 10, 0xFFFF, sum = 0
6813 09:58:26.110862 11, 0xFFFF, sum = 0
6814 09:58:26.114125 12, 0xFFFF, sum = 0
6815 09:58:26.114216 13, 0x0, sum = 1
6816 09:58:26.117148 14, 0x0, sum = 2
6817 09:58:26.117260 15, 0x0, sum = 3
6818 09:58:26.117361 16, 0x0, sum = 4
6819 09:58:26.120231 best_step = 14
6820 09:58:26.120330
6821 09:58:26.120437 ==
6822 09:58:26.123832 Dram Type= 6, Freq= 0, CH_1, rank 0
6823 09:58:26.126761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6824 09:58:26.126837 ==
6825 09:58:26.130088 RX Vref Scan: 1
6826 09:58:26.130164
6827 09:58:26.133860 RX Vref 0 -> 0, step: 1
6828 09:58:26.133982
6829 09:58:26.134079 RX Delay -343 -> 252, step: 8
6830 09:58:26.134181
6831 09:58:26.137233 Set Vref, RX VrefLevel [Byte0]: 51
6832 09:58:26.140358 [Byte1]: 53
6833 09:58:26.145539
6834 09:58:26.145646 Final RX Vref Byte 0 = 51 to rank0
6835 09:58:26.148616 Final RX Vref Byte 1 = 53 to rank0
6836 09:58:26.151961 Final RX Vref Byte 0 = 51 to rank1
6837 09:58:26.155421 Final RX Vref Byte 1 = 53 to rank1==
6838 09:58:26.158495 Dram Type= 6, Freq= 0, CH_1, rank 0
6839 09:58:26.165323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6840 09:58:26.165459 ==
6841 09:58:26.165529 DQS Delay:
6842 09:58:26.168466 DQS0 = 44, DQS1 = 56
6843 09:58:26.168542 DQM Delay:
6844 09:58:26.168605 DQM0 = 8, DQM1 = 11
6845 09:58:26.171642 DQ Delay:
6846 09:58:26.174738 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6847 09:58:26.178608 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6848 09:58:26.178723 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6849 09:58:26.181679 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6850 09:58:26.184757
6851 09:58:26.184867
6852 09:58:26.191583 [DQSOSCAuto] RK0, (LSB)MR18= 0x986f, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6853 09:58:26.194692 CH1 RK0: MR19=C0C, MR18=986F
6854 09:58:26.201211 CH1_RK0: MR19=0xC0C, MR18=0x986F, DQSOSC=390, MR23=63, INC=388, DEC=258
6855 09:58:26.201327 ==
6856 09:58:26.204810 Dram Type= 6, Freq= 0, CH_1, rank 1
6857 09:58:26.207972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6858 09:58:26.208070 ==
6859 09:58:26.211485 [Gating] SW mode calibration
6860 09:58:26.218179 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6861 09:58:26.224572 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6862 09:58:26.227697 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6863 09:58:26.230807 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6864 09:58:26.237387 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6865 09:58:26.240988 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6866 09:58:26.244095 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6867 09:58:26.250685 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6868 09:58:26.253979 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6869 09:58:26.257089 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6870 09:58:26.263981 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6871 09:58:26.266982 Total UI for P1: 0, mck2ui 16
6872 09:58:26.270177 best dqsien dly found for B0: ( 0, 14, 24)
6873 09:58:26.270262 Total UI for P1: 0, mck2ui 16
6874 09:58:26.277131 best dqsien dly found for B1: ( 0, 14, 24)
6875 09:58:26.280273 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6876 09:58:26.283367 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6877 09:58:26.283483
6878 09:58:26.287043 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6879 09:58:26.290073 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6880 09:58:26.293198 [Gating] SW calibration Done
6881 09:58:26.293300 ==
6882 09:58:26.296922 Dram Type= 6, Freq= 0, CH_1, rank 1
6883 09:58:26.300060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6884 09:58:26.300176 ==
6885 09:58:26.303153 RX Vref Scan: 0
6886 09:58:26.303266
6887 09:58:26.306687 RX Vref 0 -> 0, step: 1
6888 09:58:26.306794
6889 09:58:26.306895 RX Delay -410 -> 252, step: 16
6890 09:58:26.313216 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6891 09:58:26.316814 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6892 09:58:26.319932 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6893 09:58:26.326478 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6894 09:58:26.329954 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6895 09:58:26.333123 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6896 09:58:26.336756 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6897 09:58:26.343439 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6898 09:58:26.346395 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6899 09:58:26.350098 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6900 09:58:26.353216 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6901 09:58:26.359762 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6902 09:58:26.363263 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6903 09:58:26.366328 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6904 09:58:26.369826 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6905 09:58:26.376360 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6906 09:58:26.376463 ==
6907 09:58:26.379352 Dram Type= 6, Freq= 0, CH_1, rank 1
6908 09:58:26.383136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6909 09:58:26.383234 ==
6910 09:58:26.383321 DQS Delay:
6911 09:58:26.386169 DQS0 = 43, DQS1 = 59
6912 09:58:26.386248 DQM Delay:
6913 09:58:26.389189 DQM0 = 13, DQM1 = 21
6914 09:58:26.389269 DQ Delay:
6915 09:58:26.392885 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6916 09:58:26.395909 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6917 09:58:26.399027 DQ8 =0, DQ9 =16, DQ10 =16, DQ11 =8
6918 09:58:26.402790 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6919 09:58:26.402872
6920 09:58:26.402936
6921 09:58:26.402994 ==
6922 09:58:26.405795 Dram Type= 6, Freq= 0, CH_1, rank 1
6923 09:58:26.409577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6924 09:58:26.409670 ==
6925 09:58:26.412580
6926 09:58:26.412672
6927 09:58:26.412751 TX Vref Scan disable
6928 09:58:26.415523 == TX Byte 0 ==
6929 09:58:26.418901 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6930 09:58:26.422139 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6931 09:58:26.425405 == TX Byte 1 ==
6932 09:58:26.429255 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6933 09:58:26.432304 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6934 09:58:26.432423 ==
6935 09:58:26.435598 Dram Type= 6, Freq= 0, CH_1, rank 1
6936 09:58:26.442368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6937 09:58:26.442490 ==
6938 09:58:26.442575
6939 09:58:26.442639
6940 09:58:26.442697 TX Vref Scan disable
6941 09:58:26.445693 == TX Byte 0 ==
6942 09:58:26.448518 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6943 09:58:26.451975 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6944 09:58:26.455094 == TX Byte 1 ==
6945 09:58:26.458737 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6946 09:58:26.462271 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6947 09:58:26.462361
6948 09:58:26.465391 [DATLAT]
6949 09:58:26.465493 Freq=400, CH1 RK1
6950 09:58:26.465562
6951 09:58:26.468335 DATLAT Default: 0xe
6952 09:58:26.468438 0, 0xFFFF, sum = 0
6953 09:58:26.472168 1, 0xFFFF, sum = 0
6954 09:58:26.472256 2, 0xFFFF, sum = 0
6955 09:58:26.475343 3, 0xFFFF, sum = 0
6956 09:58:26.475460 4, 0xFFFF, sum = 0
6957 09:58:26.478438 5, 0xFFFF, sum = 0
6958 09:58:26.478561 6, 0xFFFF, sum = 0
6959 09:58:26.482056 7, 0xFFFF, sum = 0
6960 09:58:26.482137 8, 0xFFFF, sum = 0
6961 09:58:26.485201 9, 0xFFFF, sum = 0
6962 09:58:26.485335 10, 0xFFFF, sum = 0
6963 09:58:26.488176 11, 0xFFFF, sum = 0
6964 09:58:26.492039 12, 0xFFFF, sum = 0
6965 09:58:26.492132 13, 0x0, sum = 1
6966 09:58:26.495356 14, 0x0, sum = 2
6967 09:58:26.495444 15, 0x0, sum = 3
6968 09:58:26.495522 16, 0x0, sum = 4
6969 09:58:26.498280 best_step = 14
6970 09:58:26.498365
6971 09:58:26.498428 ==
6972 09:58:26.501417 Dram Type= 6, Freq= 0, CH_1, rank 1
6973 09:58:26.505290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6974 09:58:26.505395 ==
6975 09:58:26.508439 RX Vref Scan: 0
6976 09:58:26.508518
6977 09:58:26.508579 RX Vref 0 -> 0, step: 1
6978 09:58:26.511599
6979 09:58:26.511678 RX Delay -359 -> 252, step: 8
6980 09:58:26.519790 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
6981 09:58:26.523472 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
6982 09:58:26.526540 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
6983 09:58:26.533275 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
6984 09:58:26.536766 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6985 09:58:26.539933 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
6986 09:58:26.543090 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
6987 09:58:26.549779 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6988 09:58:26.553262 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
6989 09:58:26.556268 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
6990 09:58:26.559839 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
6991 09:58:26.566404 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
6992 09:58:26.569563 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
6993 09:58:26.573115 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6994 09:58:26.576232 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6995 09:58:26.582661 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
6996 09:58:26.582797 ==
6997 09:58:26.585822 Dram Type= 6, Freq= 0, CH_1, rank 1
6998 09:58:26.589566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6999 09:58:26.589671 ==
7000 09:58:26.589740 DQS Delay:
7001 09:58:26.592807 DQS0 = 48, DQS1 = 56
7002 09:58:26.592889 DQM Delay:
7003 09:58:26.595848 DQM0 = 12, DQM1 = 11
7004 09:58:26.595932 DQ Delay:
7005 09:58:26.599263 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
7006 09:58:26.602802 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
7007 09:58:26.605814 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7008 09:58:26.608895 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7009 09:58:26.609023
7010 09:58:26.609092
7011 09:58:26.615919 [DQSOSCAuto] RK1, (LSB)MR18= 0x6856, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7012 09:58:26.619082 CH1 RK1: MR19=C0C, MR18=6856
7013 09:58:26.625259 CH1_RK1: MR19=0xC0C, MR18=0x6856, DQSOSC=396, MR23=63, INC=376, DEC=251
7014 09:58:26.628935 [RxdqsGatingPostProcess] freq 400
7015 09:58:26.635709 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7016 09:58:26.638552 best DQS0 dly(2T, 0.5T) = (0, 10)
7017 09:58:26.641866 best DQS1 dly(2T, 0.5T) = (0, 10)
7018 09:58:26.645097 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7019 09:58:26.648532 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7020 09:58:26.652145 best DQS0 dly(2T, 0.5T) = (0, 10)
7021 09:58:26.652233 best DQS1 dly(2T, 0.5T) = (0, 10)
7022 09:58:26.655215 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7023 09:58:26.658667 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7024 09:58:26.661843 Pre-setting of DQS Precalculation
7025 09:58:26.668443 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7026 09:58:26.675053 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7027 09:58:26.681818 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7028 09:58:26.681970
7029 09:58:26.682072
7030 09:58:26.685031 [Calibration Summary] 800 Mbps
7031 09:58:26.688622 CH 0, Rank 0
7032 09:58:26.688751 SW Impedance : PASS
7033 09:58:26.691714 DUTY Scan : NO K
7034 09:58:26.691862 ZQ Calibration : PASS
7035 09:58:26.694731 Jitter Meter : NO K
7036 09:58:26.697930 CBT Training : PASS
7037 09:58:26.698041 Write leveling : PASS
7038 09:58:26.701534 RX DQS gating : PASS
7039 09:58:26.704687 RX DQ/DQS(RDDQC) : PASS
7040 09:58:26.704800 TX DQ/DQS : PASS
7041 09:58:26.707821 RX DATLAT : PASS
7042 09:58:26.711744 RX DQ/DQS(Engine): PASS
7043 09:58:26.711874 TX OE : NO K
7044 09:58:26.714548 All Pass.
7045 09:58:26.714668
7046 09:58:26.714766 CH 0, Rank 1
7047 09:58:26.717886 SW Impedance : PASS
7048 09:58:26.718000 DUTY Scan : NO K
7049 09:58:26.721162 ZQ Calibration : PASS
7050 09:58:26.724615 Jitter Meter : NO K
7051 09:58:26.724727 CBT Training : PASS
7052 09:58:26.727815 Write leveling : NO K
7053 09:58:26.730909 RX DQS gating : PASS
7054 09:58:26.731031 RX DQ/DQS(RDDQC) : PASS
7055 09:58:26.734756 TX DQ/DQS : PASS
7056 09:58:26.737618 RX DATLAT : PASS
7057 09:58:26.737786 RX DQ/DQS(Engine): PASS
7058 09:58:26.740834 TX OE : NO K
7059 09:58:26.740960 All Pass.
7060 09:58:26.741058
7061 09:58:26.744374 CH 1, Rank 0
7062 09:58:26.744483 SW Impedance : PASS
7063 09:58:26.747904 DUTY Scan : NO K
7064 09:58:26.751186 ZQ Calibration : PASS
7065 09:58:26.751320 Jitter Meter : NO K
7066 09:58:26.754067 CBT Training : PASS
7067 09:58:26.757261 Write leveling : PASS
7068 09:58:26.757376 RX DQS gating : PASS
7069 09:58:26.761100 RX DQ/DQS(RDDQC) : PASS
7070 09:58:26.761220 TX DQ/DQS : PASS
7071 09:58:26.764164 RX DATLAT : PASS
7072 09:58:26.767290 RX DQ/DQS(Engine): PASS
7073 09:58:26.767422 TX OE : NO K
7074 09:58:26.770740 All Pass.
7075 09:58:26.770826
7076 09:58:26.770892 CH 1, Rank 1
7077 09:58:26.774123 SW Impedance : PASS
7078 09:58:26.774235 DUTY Scan : NO K
7079 09:58:26.777079 ZQ Calibration : PASS
7080 09:58:26.780620 Jitter Meter : NO K
7081 09:58:26.780741 CBT Training : PASS
7082 09:58:26.783797 Write leveling : NO K
7083 09:58:26.787474 RX DQS gating : PASS
7084 09:58:26.787621 RX DQ/DQS(RDDQC) : PASS
7085 09:58:26.790663 TX DQ/DQS : PASS
7086 09:58:26.793884 RX DATLAT : PASS
7087 09:58:26.793997 RX DQ/DQS(Engine): PASS
7088 09:58:26.797091 TX OE : NO K
7089 09:58:26.797225 All Pass.
7090 09:58:26.797320
7091 09:58:26.800216 DramC Write-DBI off
7092 09:58:26.803883 PER_BANK_REFRESH: Hybrid Mode
7093 09:58:26.804020 TX_TRACKING: ON
7094 09:58:26.813432 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7095 09:58:26.816555 [FAST_K] Save calibration result to emmc
7096 09:58:26.820345 dramc_set_vcore_voltage set vcore to 725000
7097 09:58:26.823417 Read voltage for 1600, 0
7098 09:58:26.823538 Vio18 = 0
7099 09:58:26.826683 Vcore = 725000
7100 09:58:26.826827 Vdram = 0
7101 09:58:26.826949 Vddq = 0
7102 09:58:26.827068 Vmddr = 0
7103 09:58:26.833168 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7104 09:58:26.839890 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7105 09:58:26.840049 MEM_TYPE=3, freq_sel=13
7106 09:58:26.842831 sv_algorithm_assistance_LP4_3733
7107 09:58:26.846106 ============ PULL DRAM RESETB DOWN ============
7108 09:58:26.852922 ========== PULL DRAM RESETB DOWN end =========
7109 09:58:26.856285 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7110 09:58:26.859255 ===================================
7111 09:58:26.862647 LPDDR4 DRAM CONFIGURATION
7112 09:58:26.866112 ===================================
7113 09:58:26.866233 EX_ROW_EN[0] = 0x0
7114 09:58:26.869218 EX_ROW_EN[1] = 0x0
7115 09:58:26.869327 LP4Y_EN = 0x0
7116 09:58:26.872958 WORK_FSP = 0x1
7117 09:58:26.873081 WL = 0x5
7118 09:58:26.875812 RL = 0x5
7119 09:58:26.879255 BL = 0x2
7120 09:58:26.879373 RPST = 0x0
7121 09:58:26.882638 RD_PRE = 0x0
7122 09:58:26.882727 WR_PRE = 0x1
7123 09:58:26.886372 WR_PST = 0x1
7124 09:58:26.886480 DBI_WR = 0x0
7125 09:58:26.889372 DBI_RD = 0x0
7126 09:58:26.889476 OTF = 0x1
7127 09:58:26.892583 ===================================
7128 09:58:26.895667 ===================================
7129 09:58:26.898852 ANA top config
7130 09:58:26.902571 ===================================
7131 09:58:26.902699 DLL_ASYNC_EN = 0
7132 09:58:26.905751 ALL_SLAVE_EN = 0
7133 09:58:26.908843 NEW_RANK_MODE = 1
7134 09:58:26.912549 DLL_IDLE_MODE = 1
7135 09:58:26.915540 LP45_APHY_COMB_EN = 1
7136 09:58:26.915671 TX_ODT_DIS = 0
7137 09:58:26.918736 NEW_8X_MODE = 1
7138 09:58:26.922505 ===================================
7139 09:58:26.925457 ===================================
7140 09:58:26.928606 data_rate = 3200
7141 09:58:26.932394 CKR = 1
7142 09:58:26.935533 DQ_P2S_RATIO = 8
7143 09:58:26.939190 ===================================
7144 09:58:26.939336 CA_P2S_RATIO = 8
7145 09:58:26.941874 DQ_CA_OPEN = 0
7146 09:58:26.945519 DQ_SEMI_OPEN = 0
7147 09:58:26.948977 CA_SEMI_OPEN = 0
7148 09:58:26.951778 CA_FULL_RATE = 0
7149 09:58:26.955544 DQ_CKDIV4_EN = 0
7150 09:58:26.955674 CA_CKDIV4_EN = 0
7151 09:58:26.958679 CA_PREDIV_EN = 0
7152 09:58:26.961746 PH8_DLY = 12
7153 09:58:26.964902 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7154 09:58:26.968294 DQ_AAMCK_DIV = 4
7155 09:58:26.971804 CA_AAMCK_DIV = 4
7156 09:58:26.971923 CA_ADMCK_DIV = 4
7157 09:58:26.975280 DQ_TRACK_CA_EN = 0
7158 09:58:26.978301 CA_PICK = 1600
7159 09:58:26.981900 CA_MCKIO = 1600
7160 09:58:26.984851 MCKIO_SEMI = 0
7161 09:58:26.988338 PLL_FREQ = 3068
7162 09:58:26.991955 DQ_UI_PI_RATIO = 32
7163 09:58:26.995048 CA_UI_PI_RATIO = 0
7164 09:58:26.998179 ===================================
7165 09:58:27.001572 ===================================
7166 09:58:27.001691 memory_type:LPDDR4
7167 09:58:27.005194 GP_NUM : 10
7168 09:58:27.008305 SRAM_EN : 1
7169 09:58:27.008430 MD32_EN : 0
7170 09:58:27.011336 ===================================
7171 09:58:27.015146 [ANA_INIT] >>>>>>>>>>>>>>
7172 09:58:27.018295 <<<<<< [CONFIGURE PHASE]: ANA_TX
7173 09:58:27.021429 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7174 09:58:27.024488 ===================================
7175 09:58:27.028347 data_rate = 3200,PCW = 0X7600
7176 09:58:27.031432 ===================================
7177 09:58:27.034691 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7178 09:58:27.037837 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7179 09:58:27.044667 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7180 09:58:27.048132 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7181 09:58:27.051072 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7182 09:58:27.054224 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7183 09:58:27.057631 [ANA_INIT] flow start
7184 09:58:27.061316 [ANA_INIT] PLL >>>>>>>>
7185 09:58:27.061450 [ANA_INIT] PLL <<<<<<<<
7186 09:58:27.064175 [ANA_INIT] MIDPI >>>>>>>>
7187 09:58:27.067985 [ANA_INIT] MIDPI <<<<<<<<
7188 09:58:27.070824 [ANA_INIT] DLL >>>>>>>>
7189 09:58:27.070947 [ANA_INIT] DLL <<<<<<<<
7190 09:58:27.074342 [ANA_INIT] flow end
7191 09:58:27.077913 ============ LP4 DIFF to SE enter ============
7192 09:58:27.081265 ============ LP4 DIFF to SE exit ============
7193 09:58:27.084110 [ANA_INIT] <<<<<<<<<<<<<
7194 09:58:27.087470 [Flow] Enable top DCM control >>>>>
7195 09:58:27.090953 [Flow] Enable top DCM control <<<<<
7196 09:58:27.094410 Enable DLL master slave shuffle
7197 09:58:27.100607 ==============================================================
7198 09:58:27.100739 Gating Mode config
7199 09:58:27.107430 ==============================================================
7200 09:58:27.107566 Config description:
7201 09:58:27.117322 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7202 09:58:27.123699 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7203 09:58:27.130159 SELPH_MODE 0: By rank 1: By Phase
7204 09:58:27.133962 ==============================================================
7205 09:58:27.136907 GAT_TRACK_EN = 1
7206 09:58:27.140091 RX_GATING_MODE = 2
7207 09:58:27.143779 RX_GATING_TRACK_MODE = 2
7208 09:58:27.146940 SELPH_MODE = 1
7209 09:58:27.149874 PICG_EARLY_EN = 1
7210 09:58:27.153616 VALID_LAT_VALUE = 1
7211 09:58:27.159708 ==============================================================
7212 09:58:27.163264 Enter into Gating configuration >>>>
7213 09:58:27.166355 Exit from Gating configuration <<<<
7214 09:58:27.170011 Enter into DVFS_PRE_config >>>>>
7215 09:58:27.179529 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7216 09:58:27.182739 Exit from DVFS_PRE_config <<<<<
7217 09:58:27.186271 Enter into PICG configuration >>>>
7218 09:58:27.189243 Exit from PICG configuration <<<<
7219 09:58:27.192627 [RX_INPUT] configuration >>>>>
7220 09:58:27.196072 [RX_INPUT] configuration <<<<<
7221 09:58:27.199360 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7222 09:58:27.205808 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7223 09:58:27.212489 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7224 09:58:27.216211 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7225 09:58:27.222506 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7226 09:58:27.229468 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7227 09:58:27.232717 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7228 09:58:27.238886 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7229 09:58:27.242089 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7230 09:58:27.245778 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7231 09:58:27.248978 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7232 09:58:27.255539 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7233 09:58:27.259243 ===================================
7234 09:58:27.259346 LPDDR4 DRAM CONFIGURATION
7235 09:58:27.262449 ===================================
7236 09:58:27.265519 EX_ROW_EN[0] = 0x0
7237 09:58:27.268512 EX_ROW_EN[1] = 0x0
7238 09:58:27.268600 LP4Y_EN = 0x0
7239 09:58:27.272402 WORK_FSP = 0x1
7240 09:58:27.272520 WL = 0x5
7241 09:58:27.275414 RL = 0x5
7242 09:58:27.275531 BL = 0x2
7243 09:58:27.279054 RPST = 0x0
7244 09:58:27.279136 RD_PRE = 0x0
7245 09:58:27.282154 WR_PRE = 0x1
7246 09:58:27.282241 WR_PST = 0x1
7247 09:58:27.285189 DBI_WR = 0x0
7248 09:58:27.285271 DBI_RD = 0x0
7249 09:58:27.288557 OTF = 0x1
7250 09:58:27.292116 ===================================
7251 09:58:27.295174 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7252 09:58:27.298738 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7253 09:58:27.305238 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7254 09:58:27.308237 ===================================
7255 09:58:27.308346 LPDDR4 DRAM CONFIGURATION
7256 09:58:27.311723 ===================================
7257 09:58:27.315236 EX_ROW_EN[0] = 0x10
7258 09:58:27.318564 EX_ROW_EN[1] = 0x0
7259 09:58:27.318682 LP4Y_EN = 0x0
7260 09:58:27.321585 WORK_FSP = 0x1
7261 09:58:27.321688 WL = 0x5
7262 09:58:27.325283 RL = 0x5
7263 09:58:27.325434 BL = 0x2
7264 09:58:27.328535 RPST = 0x0
7265 09:58:27.328648 RD_PRE = 0x0
7266 09:58:27.331534 WR_PRE = 0x1
7267 09:58:27.331627 WR_PST = 0x1
7268 09:58:27.334580 DBI_WR = 0x0
7269 09:58:27.334672 DBI_RD = 0x0
7270 09:58:27.338419 OTF = 0x1
7271 09:58:27.341581 ===================================
7272 09:58:27.347778 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7273 09:58:27.347922 ==
7274 09:58:27.351542 Dram Type= 6, Freq= 0, CH_0, rank 0
7275 09:58:27.354605 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7276 09:58:27.354700 ==
7277 09:58:27.357631 [Duty_Offset_Calibration]
7278 09:58:27.357713 B0:1 B1:-1 CA:0
7279 09:58:27.357777
7280 09:58:27.361197 [DutyScan_Calibration_Flow] k_type=0
7281 09:58:27.372546
7282 09:58:27.372680 ==CLK 0==
7283 09:58:27.375610 Final CLK duty delay cell = 0
7284 09:58:27.378646 [0] MAX Duty = 5125%(X100), DQS PI = 20
7285 09:58:27.382267 [0] MIN Duty = 4907%(X100), DQS PI = 6
7286 09:58:27.382434 [0] AVG Duty = 5016%(X100)
7287 09:58:27.385756
7288 09:58:27.388902 CH0 CLK Duty spec in!! Max-Min= 218%
7289 09:58:27.391970 [DutyScan_Calibration_Flow] ====Done====
7290 09:58:27.392108
7291 09:58:27.395362 [DutyScan_Calibration_Flow] k_type=1
7292 09:58:27.411160
7293 09:58:27.411351 ==DQS 0 ==
7294 09:58:27.414590 Final DQS duty delay cell = -4
7295 09:58:27.417962 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7296 09:58:27.421665 [-4] MIN Duty = 4844%(X100), DQS PI = 54
7297 09:58:27.424570 [-4] AVG Duty = 4906%(X100)
7298 09:58:27.424700
7299 09:58:27.424822 ==DQS 1 ==
7300 09:58:27.427795 Final DQS duty delay cell = 0
7301 09:58:27.430931 [0] MAX Duty = 5187%(X100), DQS PI = 4
7302 09:58:27.434744 [0] MIN Duty = 5031%(X100), DQS PI = 18
7303 09:58:27.437768 [0] AVG Duty = 5109%(X100)
7304 09:58:27.437900
7305 09:58:27.440847 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7306 09:58:27.440951
7307 09:58:27.444579 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7308 09:58:27.447764 [DutyScan_Calibration_Flow] ====Done====
7309 09:58:27.447873
7310 09:58:27.450847 [DutyScan_Calibration_Flow] k_type=3
7311 09:58:27.468753
7312 09:58:27.468876 ==DQM 0 ==
7313 09:58:27.471891 Final DQM duty delay cell = 0
7314 09:58:27.475482 [0] MAX Duty = 5093%(X100), DQS PI = 18
7315 09:58:27.478569 [0] MIN Duty = 4907%(X100), DQS PI = 10
7316 09:58:27.482298 [0] AVG Duty = 5000%(X100)
7317 09:58:27.482379
7318 09:58:27.482469 ==DQM 1 ==
7319 09:58:27.485305 Final DQM duty delay cell = 0
7320 09:58:27.488815 [0] MAX Duty = 5031%(X100), DQS PI = 6
7321 09:58:27.491930 [0] MIN Duty = 4813%(X100), DQS PI = 20
7322 09:58:27.494957 [0] AVG Duty = 4922%(X100)
7323 09:58:27.495059
7324 09:58:27.498671 CH0 DQM 0 Duty spec in!! Max-Min= 186%
7325 09:58:27.498773
7326 09:58:27.501578 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7327 09:58:27.504875 [DutyScan_Calibration_Flow] ====Done====
7328 09:58:27.504976
7329 09:58:27.508077 [DutyScan_Calibration_Flow] k_type=2
7330 09:58:27.525099
7331 09:58:27.525243 ==DQ 0 ==
7332 09:58:27.528167 Final DQ duty delay cell = -4
7333 09:58:27.531779 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7334 09:58:27.534882 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7335 09:58:27.538710 [-4] AVG Duty = 4953%(X100)
7336 09:58:27.538814
7337 09:58:27.538880 ==DQ 1 ==
7338 09:58:27.541896 Final DQ duty delay cell = 0
7339 09:58:27.544890 [0] MAX Duty = 5125%(X100), DQS PI = 2
7340 09:58:27.548310 [0] MIN Duty = 5000%(X100), DQS PI = 36
7341 09:58:27.551908 [0] AVG Duty = 5062%(X100)
7342 09:58:27.552033
7343 09:58:27.555163 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7344 09:58:27.555265
7345 09:58:27.558198 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7346 09:58:27.561367 [DutyScan_Calibration_Flow] ====Done====
7347 09:58:27.561488 ==
7348 09:58:27.564645 Dram Type= 6, Freq= 0, CH_1, rank 0
7349 09:58:27.568235 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7350 09:58:27.568361 ==
7351 09:58:27.571367 [Duty_Offset_Calibration]
7352 09:58:27.571444 B0:-1 B1:1 CA:2
7353 09:58:27.571551
7354 09:58:27.574990 [DutyScan_Calibration_Flow] k_type=0
7355 09:58:27.585902
7356 09:58:27.585999 ==CLK 0==
7357 09:58:27.589054 Final CLK duty delay cell = 0
7358 09:58:27.592077 [0] MAX Duty = 5156%(X100), DQS PI = 22
7359 09:58:27.595632 [0] MIN Duty = 5062%(X100), DQS PI = 0
7360 09:58:27.595741 [0] AVG Duty = 5109%(X100)
7361 09:58:27.598787
7362 09:58:27.602450 CH1 CLK Duty spec in!! Max-Min= 94%
7363 09:58:27.605537 [DutyScan_Calibration_Flow] ====Done====
7364 09:58:27.605643
7365 09:58:27.608630 [DutyScan_Calibration_Flow] k_type=1
7366 09:58:27.625602
7367 09:58:27.625757 ==DQS 0 ==
7368 09:58:27.628577 Final DQS duty delay cell = 0
7369 09:58:27.631964 [0] MAX Duty = 5156%(X100), DQS PI = 20
7370 09:58:27.635049 [0] MIN Duty = 4907%(X100), DQS PI = 40
7371 09:58:27.638242 [0] AVG Duty = 5031%(X100)
7372 09:58:27.638360
7373 09:58:27.638436 ==DQS 1 ==
7374 09:58:27.641592 Final DQS duty delay cell = 0
7375 09:58:27.645265 [0] MAX Duty = 5093%(X100), DQS PI = 6
7376 09:58:27.648520 [0] MIN Duty = 5000%(X100), DQS PI = 22
7377 09:58:27.652288 [0] AVG Duty = 5046%(X100)
7378 09:58:27.652404
7379 09:58:27.655146 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7380 09:58:27.655262
7381 09:58:27.658374 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7382 09:58:27.661497 [DutyScan_Calibration_Flow] ====Done====
7383 09:58:27.661600
7384 09:58:27.664593 [DutyScan_Calibration_Flow] k_type=3
7385 09:58:27.682072
7386 09:58:27.682182 ==DQM 0 ==
7387 09:58:27.685275 Final DQM duty delay cell = 0
7388 09:58:27.688875 [0] MAX Duty = 5218%(X100), DQS PI = 24
7389 09:58:27.691968 [0] MIN Duty = 5000%(X100), DQS PI = 42
7390 09:58:27.695561 [0] AVG Duty = 5109%(X100)
7391 09:58:27.695666
7392 09:58:27.695761 ==DQM 1 ==
7393 09:58:27.698594 Final DQM duty delay cell = 0
7394 09:58:27.701786 [0] MAX Duty = 5187%(X100), DQS PI = 34
7395 09:58:27.705467 [0] MIN Duty = 5000%(X100), DQS PI = 0
7396 09:58:27.708633 [0] AVG Duty = 5093%(X100)
7397 09:58:27.708733
7398 09:58:27.711793 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7399 09:58:27.711879
7400 09:58:27.714947 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7401 09:58:27.718646 [DutyScan_Calibration_Flow] ====Done====
7402 09:58:27.718732
7403 09:58:27.721468 [DutyScan_Calibration_Flow] k_type=2
7404 09:58:27.739061
7405 09:58:27.739165 ==DQ 0 ==
7406 09:58:27.742400 Final DQ duty delay cell = 0
7407 09:58:27.745706 [0] MAX Duty = 5156%(X100), DQS PI = 0
7408 09:58:27.749276 [0] MIN Duty = 4906%(X100), DQS PI = 40
7409 09:58:27.749382 [0] AVG Duty = 5031%(X100)
7410 09:58:27.752154
7411 09:58:27.752261 ==DQ 1 ==
7412 09:58:27.755479 Final DQ duty delay cell = 0
7413 09:58:27.759192 [0] MAX Duty = 5125%(X100), DQS PI = 40
7414 09:58:27.762156 [0] MIN Duty = 4969%(X100), DQS PI = 26
7415 09:58:27.762270 [0] AVG Duty = 5047%(X100)
7416 09:58:27.762376
7417 09:58:27.765252 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7418 09:58:27.769097
7419 09:58:27.772289 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7420 09:58:27.775151 [DutyScan_Calibration_Flow] ====Done====
7421 09:58:27.778683 nWR fixed to 30
7422 09:58:27.778799 [ModeRegInit_LP4] CH0 RK0
7423 09:58:27.781871 [ModeRegInit_LP4] CH0 RK1
7424 09:58:27.785502 [ModeRegInit_LP4] CH1 RK0
7425 09:58:27.788460 [ModeRegInit_LP4] CH1 RK1
7426 09:58:27.788573 match AC timing 5
7427 09:58:27.795285 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7428 09:58:27.798595 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7429 09:58:27.802245 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7430 09:58:27.808812 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7431 09:58:27.811850 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7432 09:58:27.811960 [MiockJmeterHQA]
7433 09:58:27.812053
7434 09:58:27.815069 [DramcMiockJmeter] u1RxGatingPI = 0
7435 09:58:27.818288 0 : 4363, 4137
7436 09:58:27.818462 4 : 4252, 4027
7437 09:58:27.821394 8 : 4363, 4137
7438 09:58:27.821520 12 : 4252, 4027
7439 09:58:27.821617 16 : 4252, 4027
7440 09:58:27.825176 20 : 4252, 4027
7441 09:58:27.825290 24 : 4365, 4140
7442 09:58:27.828120 28 : 4252, 4026
7443 09:58:27.828224 32 : 4255, 4029
7444 09:58:27.831479 36 : 4253, 4027
7445 09:58:27.831594 40 : 4363, 4137
7446 09:58:27.834597 44 : 4253, 4026
7447 09:58:27.834702 48 : 4363, 4138
7448 09:58:27.834796 52 : 4252, 4027
7449 09:58:27.838046 56 : 4250, 4027
7450 09:58:27.838160 60 : 4252, 4027
7451 09:58:27.841076 64 : 4252, 4029
7452 09:58:27.841183 68 : 4361, 4138
7453 09:58:27.844619 72 : 4250, 4027
7454 09:58:27.844724 76 : 4361, 4137
7455 09:58:27.847927 80 : 4250, 4026
7456 09:58:27.848025 84 : 4250, 4027
7457 09:58:27.848120 88 : 4250, 4026
7458 09:58:27.850940 92 : 4361, 708
7459 09:58:27.851049 96 : 4250, 0
7460 09:58:27.854277 100 : 4250, 0
7461 09:58:27.854394 104 : 4360, 0
7462 09:58:27.854493 108 : 4360, 0
7463 09:58:27.857600 112 : 4250, 0
7464 09:58:27.857707 116 : 4250, 0
7465 09:58:27.861155 120 : 4250, 0
7466 09:58:27.861271 124 : 4250, 0
7467 09:58:27.861376 128 : 4250, 0
7468 09:58:27.864601 132 : 4250, 0
7469 09:58:27.864717 136 : 4250, 0
7470 09:58:27.867870 140 : 4252, 0
7471 09:58:27.867958 144 : 4361, 0
7472 09:58:27.868054 148 : 4250, 0
7473 09:58:27.870838 152 : 4250, 0
7474 09:58:27.870914 156 : 4360, 0
7475 09:58:27.873986 160 : 4361, 0
7476 09:58:27.874061 164 : 4363, 0
7477 09:58:27.874147 168 : 4250, 0
7478 09:58:27.877812 172 : 4361, 0
7479 09:58:27.877889 176 : 4361, 0
7480 09:58:27.880847 180 : 4250, 0
7481 09:58:27.880953 184 : 4250, 0
7482 09:58:27.881050 188 : 4250, 0
7483 09:58:27.884473 192 : 4250, 0
7484 09:58:27.884592 196 : 4250, 0
7485 09:58:27.884705 200 : 4250, 0
7486 09:58:27.887540 204 : 4252, 0
7487 09:58:27.887644 208 : 4250, 0
7488 09:58:27.890610 212 : 4360, 0
7489 09:58:27.890712 216 : 4250, 0
7490 09:58:27.890808 220 : 4250, 0
7491 09:58:27.894419 224 : 4361, 168
7492 09:58:27.894497 228 : 4250, 3180
7493 09:58:27.897355 232 : 4360, 4138
7494 09:58:27.897464 236 : 4250, 4027
7495 09:58:27.900540 240 : 4250, 4027
7496 09:58:27.900622 244 : 4250, 4027
7497 09:58:27.903735 248 : 4252, 4029
7498 09:58:27.903841 252 : 4250, 4027
7499 09:58:27.907544 256 : 4250, 4027
7500 09:58:27.907652 260 : 4250, 4027
7501 09:58:27.910497 264 : 4252, 4030
7502 09:58:27.910606 268 : 4250, 4027
7503 09:58:27.913528 272 : 4361, 4137
7504 09:58:27.913631 276 : 4361, 4137
7505 09:58:27.913734 280 : 4250, 4027
7506 09:58:27.917394 284 : 4363, 4140
7507 09:58:27.917526 288 : 4250, 4027
7508 09:58:27.920423 292 : 4250, 4026
7509 09:58:27.920538 296 : 4250, 4027
7510 09:58:27.923532 300 : 4252, 4030
7511 09:58:27.923645 304 : 4250, 4027
7512 09:58:27.927169 308 : 4250, 4026
7513 09:58:27.927285 312 : 4250, 4027
7514 09:58:27.930270 316 : 4252, 4029
7515 09:58:27.930385 320 : 4250, 4027
7516 09:58:27.933223 324 : 4361, 4137
7517 09:58:27.933337 328 : 4361, 4138
7518 09:58:27.936722 332 : 4250, 4027
7519 09:58:27.936834 336 : 4363, 4063
7520 09:58:27.939905 340 : 4250, 2286
7521 09:58:27.940011 344 : 4250, 29
7522 09:58:27.940112
7523 09:58:27.943440 MIOCK jitter meter ch=0
7524 09:58:27.943542
7525 09:58:27.947022 1T = (344-92) = 252 dly cells
7526 09:58:27.950158 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7527 09:58:27.950263 ==
7528 09:58:27.953138 Dram Type= 6, Freq= 0, CH_0, rank 0
7529 09:58:27.959832 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7530 09:58:27.959952 ==
7531 09:58:27.963379 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7532 09:58:27.969870 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7533 09:58:27.973173 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7534 09:58:27.979765 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7535 09:58:27.987467 [CA 0] Center 43 (12~74) winsize 63
7536 09:58:27.990485 [CA 1] Center 42 (12~73) winsize 62
7537 09:58:27.993770 [CA 2] Center 38 (9~68) winsize 60
7538 09:58:27.997348 [CA 3] Center 38 (8~68) winsize 61
7539 09:58:28.000489 [CA 4] Center 36 (7~66) winsize 60
7540 09:58:28.003763 [CA 5] Center 35 (6~65) winsize 60
7541 09:58:28.003875
7542 09:58:28.007319 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7543 09:58:28.007402
7544 09:58:28.013617 [CATrainingPosCal] consider 1 rank data
7545 09:58:28.013729 u2DelayCellTimex100 = 258/100 ps
7546 09:58:28.020246 CA0 delay=43 (12~74),Diff = 8 PI (30 cell)
7547 09:58:28.023944 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7548 09:58:28.026856 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7549 09:58:28.030055 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7550 09:58:28.033749 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7551 09:58:28.036732 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7552 09:58:28.036814
7553 09:58:28.040309 CA PerBit enable=1, Macro0, CA PI delay=35
7554 09:58:28.040417
7555 09:58:28.043506 [CBTSetCACLKResult] CA Dly = 35
7556 09:58:28.047076 CS Dly: 12 (0~43)
7557 09:58:28.050127 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7558 09:58:28.053095 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7559 09:58:28.053199 ==
7560 09:58:28.056707 Dram Type= 6, Freq= 0, CH_0, rank 1
7561 09:58:28.063577 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7562 09:58:28.063704 ==
7563 09:58:28.066636 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7564 09:58:28.073509 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7565 09:58:28.076592 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7566 09:58:28.082797 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7567 09:58:28.090830 [CA 0] Center 43 (13~74) winsize 62
7568 09:58:28.094190 [CA 1] Center 44 (14~74) winsize 61
7569 09:58:28.097428 [CA 2] Center 38 (9~68) winsize 60
7570 09:58:28.100781 [CA 3] Center 38 (9~68) winsize 60
7571 09:58:28.103878 [CA 4] Center 36 (7~66) winsize 60
7572 09:58:28.107519 [CA 5] Center 36 (6~66) winsize 61
7573 09:58:28.107633
7574 09:58:28.110659 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7575 09:58:28.110763
7576 09:58:28.113825 [CATrainingPosCal] consider 2 rank data
7577 09:58:28.117072 u2DelayCellTimex100 = 258/100 ps
7578 09:58:28.124083 CA0 delay=43 (13~74),Diff = 8 PI (30 cell)
7579 09:58:28.127207 CA1 delay=43 (14~73),Diff = 8 PI (30 cell)
7580 09:58:28.130209 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7581 09:58:28.134094 CA3 delay=38 (9~68),Diff = 3 PI (11 cell)
7582 09:58:28.137204 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7583 09:58:28.140199 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7584 09:58:28.140321
7585 09:58:28.143629 CA PerBit enable=1, Macro0, CA PI delay=35
7586 09:58:28.143742
7587 09:58:28.147252 [CBTSetCACLKResult] CA Dly = 35
7588 09:58:28.150172 CS Dly: 12 (0~43)
7589 09:58:28.153836 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7590 09:58:28.156833 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7591 09:58:28.156940
7592 09:58:28.160006 ----->DramcWriteLeveling(PI) begin...
7593 09:58:28.160122 ==
7594 09:58:28.163966 Dram Type= 6, Freq= 0, CH_0, rank 0
7595 09:58:28.170213 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7596 09:58:28.170329 ==
7597 09:58:28.173195 Write leveling (Byte 0): 34 => 34
7598 09:58:28.176847 Write leveling (Byte 1): 27 => 27
7599 09:58:28.176964 DramcWriteLeveling(PI) end<-----
7600 09:58:28.179766
7601 09:58:28.179869 ==
7602 09:58:28.183400 Dram Type= 6, Freq= 0, CH_0, rank 0
7603 09:58:28.186611 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7604 09:58:28.186716 ==
7605 09:58:28.190323 [Gating] SW mode calibration
7606 09:58:28.196292 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7607 09:58:28.199742 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7608 09:58:28.206576 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7609 09:58:28.209881 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7610 09:58:28.213179 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7611 09:58:28.219961 1 4 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7612 09:58:28.223131 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7613 09:58:28.226117 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7614 09:58:28.232924 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7615 09:58:28.236097 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7616 09:58:28.239818 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7617 09:58:28.246031 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7618 09:58:28.249427 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7619 09:58:28.252525 1 5 12 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 0)
7620 09:58:28.259080 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7621 09:58:28.262530 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7622 09:58:28.265613 1 5 24 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
7623 09:58:28.272720 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7624 09:58:28.275683 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7625 09:58:28.278826 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7626 09:58:28.285574 1 6 8 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7627 09:58:28.288838 1 6 12 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
7628 09:58:28.292516 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7629 09:58:28.298680 1 6 20 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7630 09:58:28.301950 1 6 24 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
7631 09:58:28.305624 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7632 09:58:28.312114 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7633 09:58:28.315453 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7634 09:58:28.318858 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7635 09:58:28.325479 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7636 09:58:28.328538 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7637 09:58:28.332120 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7638 09:58:28.338843 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7639 09:58:28.341469 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 09:58:28.345107 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 09:58:28.351778 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 09:58:28.354698 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 09:58:28.358247 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 09:58:28.364839 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 09:58:28.367959 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 09:58:28.371579 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 09:58:28.378096 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 09:58:28.381123 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 09:58:28.384315 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 09:58:28.391160 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 09:58:28.394207 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7652 09:58:28.398001 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7653 09:58:28.401291 Total UI for P1: 0, mck2ui 16
7654 09:58:28.404155 best dqsien dly found for B0: ( 1, 9, 12)
7655 09:58:28.410935 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7656 09:58:28.414332 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7657 09:58:28.417863 Total UI for P1: 0, mck2ui 16
7658 09:58:28.420908 best dqsien dly found for B1: ( 1, 9, 18)
7659 09:58:28.424377 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7660 09:58:28.427381 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7661 09:58:28.427496
7662 09:58:28.431094 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7663 09:58:28.437443 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7664 09:58:28.437533 [Gating] SW calibration Done
7665 09:58:28.437600 ==
7666 09:58:28.440794 Dram Type= 6, Freq= 0, CH_0, rank 0
7667 09:58:28.447539 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7668 09:58:28.447637 ==
7669 09:58:28.447707 RX Vref Scan: 0
7670 09:58:28.447776
7671 09:58:28.450622 RX Vref 0 -> 0, step: 1
7672 09:58:28.450699
7673 09:58:28.454165 RX Delay 0 -> 252, step: 8
7674 09:58:28.457190 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7675 09:58:28.460262 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7676 09:58:28.463895 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7677 09:58:28.466887 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7678 09:58:28.473737 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7679 09:58:28.477254 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7680 09:58:28.480266 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7681 09:58:28.483958 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7682 09:58:28.487273 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7683 09:58:28.493902 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7684 09:58:28.497202 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7685 09:58:28.500307 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7686 09:58:28.504063 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7687 09:58:28.507096 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7688 09:58:28.513944 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7689 09:58:28.516832 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7690 09:58:28.516918 ==
7691 09:58:28.520489 Dram Type= 6, Freq= 0, CH_0, rank 0
7692 09:58:28.523554 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7693 09:58:28.523662 ==
7694 09:58:28.527189 DQS Delay:
7695 09:58:28.527295 DQS0 = 0, DQS1 = 0
7696 09:58:28.530271 DQM Delay:
7697 09:58:28.530357 DQM0 = 136, DQM1 = 126
7698 09:58:28.530426 DQ Delay:
7699 09:58:28.533486 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7700 09:58:28.540035 DQ4 =135, DQ5 =123, DQ6 =147, DQ7 =147
7701 09:58:28.543376 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7702 09:58:28.546627 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7703 09:58:28.546721
7704 09:58:28.546788
7705 09:58:28.546854 ==
7706 09:58:28.550259 Dram Type= 6, Freq= 0, CH_0, rank 0
7707 09:58:28.553160 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7708 09:58:28.553255 ==
7709 09:58:28.553328
7710 09:58:28.553392
7711 09:58:28.556767 TX Vref Scan disable
7712 09:58:28.559723 == TX Byte 0 ==
7713 09:58:28.563422 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7714 09:58:28.566442 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7715 09:58:28.569495 == TX Byte 1 ==
7716 09:58:28.573387 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7717 09:58:28.576153 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7718 09:58:28.576273 ==
7719 09:58:28.579404 Dram Type= 6, Freq= 0, CH_0, rank 0
7720 09:58:28.586021 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7721 09:58:28.586118 ==
7722 09:58:28.597897
7723 09:58:28.601644 TX Vref early break, caculate TX vref
7724 09:58:28.604686 TX Vref=16, minBit 0, minWin=23, winSum=372
7725 09:58:28.607790 TX Vref=18, minBit 4, minWin=22, winSum=380
7726 09:58:28.611587 TX Vref=20, minBit 1, minWin=24, winSum=391
7727 09:58:28.614661 TX Vref=22, minBit 1, minWin=24, winSum=404
7728 09:58:28.617904 TX Vref=24, minBit 5, minWin=24, winSum=411
7729 09:58:28.624585 TX Vref=26, minBit 4, minWin=25, winSum=419
7730 09:58:28.628065 TX Vref=28, minBit 0, minWin=25, winSum=415
7731 09:58:28.630847 TX Vref=30, minBit 4, minWin=25, winSum=412
7732 09:58:28.634358 TX Vref=32, minBit 1, minWin=24, winSum=401
7733 09:58:28.637552 TX Vref=34, minBit 4, minWin=23, winSum=387
7734 09:58:28.644418 [TxChooseVref] Worse bit 4, Min win 25, Win sum 419, Final Vref 26
7735 09:58:28.644534
7736 09:58:28.647659 Final TX Range 0 Vref 26
7737 09:58:28.647764
7738 09:58:28.647869 ==
7739 09:58:28.651075 Dram Type= 6, Freq= 0, CH_0, rank 0
7740 09:58:28.654017 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7741 09:58:28.654130 ==
7742 09:58:28.654233
7743 09:58:28.654330
7744 09:58:28.657382 TX Vref Scan disable
7745 09:58:28.664366 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7746 09:58:28.664493 == TX Byte 0 ==
7747 09:58:28.667722 u2DelayCellOfst[0]=15 cells (4 PI)
7748 09:58:28.670631 u2DelayCellOfst[1]=18 cells (5 PI)
7749 09:58:28.674160 u2DelayCellOfst[2]=15 cells (4 PI)
7750 09:58:28.677234 u2DelayCellOfst[3]=15 cells (4 PI)
7751 09:58:28.680482 u2DelayCellOfst[4]=11 cells (3 PI)
7752 09:58:28.684249 u2DelayCellOfst[5]=0 cells (0 PI)
7753 09:58:28.687352 u2DelayCellOfst[6]=18 cells (5 PI)
7754 09:58:28.690238 u2DelayCellOfst[7]=18 cells (5 PI)
7755 09:58:28.694079 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7756 09:58:28.697075 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7757 09:58:28.700507 == TX Byte 1 ==
7758 09:58:28.703604 u2DelayCellOfst[8]=0 cells (0 PI)
7759 09:58:28.707258 u2DelayCellOfst[9]=0 cells (0 PI)
7760 09:58:28.707387 u2DelayCellOfst[10]=3 cells (1 PI)
7761 09:58:28.710366 u2DelayCellOfst[11]=0 cells (0 PI)
7762 09:58:28.713556 u2DelayCellOfst[12]=7 cells (2 PI)
7763 09:58:28.717111 u2DelayCellOfst[13]=7 cells (2 PI)
7764 09:58:28.720310 u2DelayCellOfst[14]=11 cells (3 PI)
7765 09:58:28.723420 u2DelayCellOfst[15]=7 cells (2 PI)
7766 09:58:28.727100 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7767 09:58:28.733755 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7768 09:58:28.733874 DramC Write-DBI on
7769 09:58:28.733971 ==
7770 09:58:28.736698 Dram Type= 6, Freq= 0, CH_0, rank 0
7771 09:58:28.743559 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7772 09:58:28.743666 ==
7773 09:58:28.743738
7774 09:58:28.743800
7775 09:58:28.743862 TX Vref Scan disable
7776 09:58:28.747226 == TX Byte 0 ==
7777 09:58:28.750905 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7778 09:58:28.753980 == TX Byte 1 ==
7779 09:58:28.757109 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7780 09:58:28.760661 DramC Write-DBI off
7781 09:58:28.760747
7782 09:58:28.760816 [DATLAT]
7783 09:58:28.760881 Freq=1600, CH0 RK0
7784 09:58:28.760947
7785 09:58:28.764155 DATLAT Default: 0xf
7786 09:58:28.764240 0, 0xFFFF, sum = 0
7787 09:58:28.767177 1, 0xFFFF, sum = 0
7788 09:58:28.770600 2, 0xFFFF, sum = 0
7789 09:58:28.770690 3, 0xFFFF, sum = 0
7790 09:58:28.773964 4, 0xFFFF, sum = 0
7791 09:58:28.774077 5, 0xFFFF, sum = 0
7792 09:58:28.776881 6, 0xFFFF, sum = 0
7793 09:58:28.776993 7, 0xFFFF, sum = 0
7794 09:58:28.780093 8, 0xFFFF, sum = 0
7795 09:58:28.780203 9, 0xFFFF, sum = 0
7796 09:58:28.783591 10, 0xFFFF, sum = 0
7797 09:58:28.783701 11, 0xFFFF, sum = 0
7798 09:58:28.786881 12, 0xFFFF, sum = 0
7799 09:58:28.786997 13, 0xFFFF, sum = 0
7800 09:58:28.789961 14, 0x0, sum = 1
7801 09:58:28.790070 15, 0x0, sum = 2
7802 09:58:28.793659 16, 0x0, sum = 3
7803 09:58:28.793770 17, 0x0, sum = 4
7804 09:58:28.796885 best_step = 15
7805 09:58:28.796992
7806 09:58:28.797087 ==
7807 09:58:28.800166 Dram Type= 6, Freq= 0, CH_0, rank 0
7808 09:58:28.803610 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7809 09:58:28.803731 ==
7810 09:58:28.806655 RX Vref Scan: 1
7811 09:58:28.806742
7812 09:58:28.806811 Set Vref Range= 24 -> 127
7813 09:58:28.806878
7814 09:58:28.809811 RX Vref 24 -> 127, step: 1
7815 09:58:28.809894
7816 09:58:28.813510 RX Delay 19 -> 252, step: 4
7817 09:58:28.813614
7818 09:58:28.816526 Set Vref, RX VrefLevel [Byte0]: 24
7819 09:58:28.820336 [Byte1]: 24
7820 09:58:28.820420
7821 09:58:28.823444 Set Vref, RX VrefLevel [Byte0]: 25
7822 09:58:28.826529 [Byte1]: 25
7823 09:58:28.830178
7824 09:58:28.830265 Set Vref, RX VrefLevel [Byte0]: 26
7825 09:58:28.833506 [Byte1]: 26
7826 09:58:28.838014
7827 09:58:28.838144 Set Vref, RX VrefLevel [Byte0]: 27
7828 09:58:28.841186 [Byte1]: 27
7829 09:58:28.845199
7830 09:58:28.845320 Set Vref, RX VrefLevel [Byte0]: 28
7831 09:58:28.848598 [Byte1]: 28
7832 09:58:28.852989
7833 09:58:28.853100 Set Vref, RX VrefLevel [Byte0]: 29
7834 09:58:28.856167 [Byte1]: 29
7835 09:58:28.860394
7836 09:58:28.860511 Set Vref, RX VrefLevel [Byte0]: 30
7837 09:58:28.863516 [Byte1]: 30
7838 09:58:28.868259
7839 09:58:28.868393 Set Vref, RX VrefLevel [Byte0]: 31
7840 09:58:28.871108 [Byte1]: 31
7841 09:58:28.875402
7842 09:58:28.878457 Set Vref, RX VrefLevel [Byte0]: 32
7843 09:58:28.882158 [Byte1]: 32
7844 09:58:28.882253
7845 09:58:28.885308 Set Vref, RX VrefLevel [Byte0]: 33
7846 09:58:28.888415 [Byte1]: 33
7847 09:58:28.888521
7848 09:58:28.891722 Set Vref, RX VrefLevel [Byte0]: 34
7849 09:58:28.895322 [Byte1]: 34
7850 09:58:28.895433
7851 09:58:28.898460 Set Vref, RX VrefLevel [Byte0]: 35
7852 09:58:28.901669 [Byte1]: 35
7853 09:58:28.905590
7854 09:58:28.905683 Set Vref, RX VrefLevel [Byte0]: 36
7855 09:58:28.909184 [Byte1]: 36
7856 09:58:28.913513
7857 09:58:28.913605 Set Vref, RX VrefLevel [Byte0]: 37
7858 09:58:28.916551 [Byte1]: 37
7859 09:58:28.920925
7860 09:58:28.921030 Set Vref, RX VrefLevel [Byte0]: 38
7861 09:58:28.924497 [Byte1]: 38
7862 09:58:28.928446
7863 09:58:28.928566 Set Vref, RX VrefLevel [Byte0]: 39
7864 09:58:28.931991 [Byte1]: 39
7865 09:58:28.936373
7866 09:58:28.936484 Set Vref, RX VrefLevel [Byte0]: 40
7867 09:58:28.939478 [Byte1]: 40
7868 09:58:28.943901
7869 09:58:28.944013 Set Vref, RX VrefLevel [Byte0]: 41
7870 09:58:28.946984 [Byte1]: 41
7871 09:58:28.951270
7872 09:58:28.951382 Set Vref, RX VrefLevel [Byte0]: 42
7873 09:58:28.954283 [Byte1]: 42
7874 09:58:28.958765
7875 09:58:28.958882 Set Vref, RX VrefLevel [Byte0]: 43
7876 09:58:28.962197 [Byte1]: 43
7877 09:58:28.966555
7878 09:58:28.966671 Set Vref, RX VrefLevel [Byte0]: 44
7879 09:58:28.969483 [Byte1]: 44
7880 09:58:28.973711
7881 09:58:28.973797 Set Vref, RX VrefLevel [Byte0]: 45
7882 09:58:28.977757 [Byte1]: 45
7883 09:58:28.981665
7884 09:58:28.981777 Set Vref, RX VrefLevel [Byte0]: 46
7885 09:58:28.984643 [Byte1]: 46
7886 09:58:28.988998
7887 09:58:28.989125 Set Vref, RX VrefLevel [Byte0]: 47
7888 09:58:28.992755 [Byte1]: 47
7889 09:58:28.997011
7890 09:58:28.997126 Set Vref, RX VrefLevel [Byte0]: 48
7891 09:58:28.999888 [Byte1]: 48
7892 09:58:29.004038
7893 09:58:29.004153 Set Vref, RX VrefLevel [Byte0]: 49
7894 09:58:29.007360 [Byte1]: 49
7895 09:58:29.011653
7896 09:58:29.011765 Set Vref, RX VrefLevel [Byte0]: 50
7897 09:58:29.014899 [Byte1]: 50
7898 09:58:29.019449
7899 09:58:29.019571 Set Vref, RX VrefLevel [Byte0]: 51
7900 09:58:29.022628 [Byte1]: 51
7901 09:58:29.026898
7902 09:58:29.027011 Set Vref, RX VrefLevel [Byte0]: 52
7903 09:58:29.030099 [Byte1]: 52
7904 09:58:29.034310
7905 09:58:29.034425 Set Vref, RX VrefLevel [Byte0]: 53
7906 09:58:29.037974 [Byte1]: 53
7907 09:58:29.042268
7908 09:58:29.042382 Set Vref, RX VrefLevel [Byte0]: 54
7909 09:58:29.045291 [Byte1]: 54
7910 09:58:29.049677
7911 09:58:29.049765 Set Vref, RX VrefLevel [Byte0]: 55
7912 09:58:29.052842 [Byte1]: 55
7913 09:58:29.057278
7914 09:58:29.057394 Set Vref, RX VrefLevel [Byte0]: 56
7915 09:58:29.060278 [Byte1]: 56
7916 09:58:29.064853
7917 09:58:29.064959 Set Vref, RX VrefLevel [Byte0]: 57
7918 09:58:29.068356 [Byte1]: 57
7919 09:58:29.072305
7920 09:58:29.072426 Set Vref, RX VrefLevel [Byte0]: 58
7921 09:58:29.075889 [Byte1]: 58
7922 09:58:29.080008
7923 09:58:29.080118 Set Vref, RX VrefLevel [Byte0]: 59
7924 09:58:29.083095 [Byte1]: 59
7925 09:58:29.087334
7926 09:58:29.087450 Set Vref, RX VrefLevel [Byte0]: 60
7927 09:58:29.090976 [Byte1]: 60
7928 09:58:29.095423
7929 09:58:29.095539 Set Vref, RX VrefLevel [Byte0]: 61
7930 09:58:29.098513 [Byte1]: 61
7931 09:58:29.102730
7932 09:58:29.102840 Set Vref, RX VrefLevel [Byte0]: 62
7933 09:58:29.105801 [Byte1]: 62
7934 09:58:29.110059
7935 09:58:29.110171 Set Vref, RX VrefLevel [Byte0]: 63
7936 09:58:29.113845 [Byte1]: 63
7937 09:58:29.117947
7938 09:58:29.118058 Set Vref, RX VrefLevel [Byte0]: 64
7939 09:58:29.121235 [Byte1]: 64
7940 09:58:29.125163
7941 09:58:29.125274 Set Vref, RX VrefLevel [Byte0]: 65
7942 09:58:29.128480 [Byte1]: 65
7943 09:58:29.133143
7944 09:58:29.133256 Set Vref, RX VrefLevel [Byte0]: 66
7945 09:58:29.136172 [Byte1]: 66
7946 09:58:29.140638
7947 09:58:29.140749 Set Vref, RX VrefLevel [Byte0]: 67
7948 09:58:29.143693 [Byte1]: 67
7949 09:58:29.148087
7950 09:58:29.148193 Set Vref, RX VrefLevel [Byte0]: 68
7951 09:58:29.151175 [Byte1]: 68
7952 09:58:29.155496
7953 09:58:29.155609 Set Vref, RX VrefLevel [Byte0]: 69
7954 09:58:29.159357 [Byte1]: 69
7955 09:58:29.163046
7956 09:58:29.163154 Set Vref, RX VrefLevel [Byte0]: 70
7957 09:58:29.166251 [Byte1]: 70
7958 09:58:29.171095
7959 09:58:29.171202 Set Vref, RX VrefLevel [Byte0]: 71
7960 09:58:29.174076 [Byte1]: 71
7961 09:58:29.178713
7962 09:58:29.178824 Set Vref, RX VrefLevel [Byte0]: 72
7963 09:58:29.182057 [Byte1]: 72
7964 09:58:29.185837
7965 09:58:29.185950 Set Vref, RX VrefLevel [Byte0]: 73
7966 09:58:29.189211 [Byte1]: 73
7967 09:58:29.193445
7968 09:58:29.193555 Set Vref, RX VrefLevel [Byte0]: 74
7969 09:58:29.197049 [Byte1]: 74
7970 09:58:29.201428
7971 09:58:29.201543 Set Vref, RX VrefLevel [Byte0]: 75
7972 09:58:29.204536 [Byte1]: 75
7973 09:58:29.208727
7974 09:58:29.208838 Set Vref, RX VrefLevel [Byte0]: 76
7975 09:58:29.212312 [Byte1]: 76
7976 09:58:29.216598
7977 09:58:29.216710 Set Vref, RX VrefLevel [Byte0]: 77
7978 09:58:29.219672 [Byte1]: 77
7979 09:58:29.224048
7980 09:58:29.224159 Set Vref, RX VrefLevel [Byte0]: 78
7981 09:58:29.227023 [Byte1]: 78
7982 09:58:29.231292
7983 09:58:29.231403 Set Vref, RX VrefLevel [Byte0]: 79
7984 09:58:29.234797 [Byte1]: 79
7985 09:58:29.238790
7986 09:58:29.241957 Set Vref, RX VrefLevel [Byte0]: 80
7987 09:58:29.245585 [Byte1]: 80
7988 09:58:29.245704
7989 09:58:29.248591 Final RX Vref Byte 0 = 65 to rank0
7990 09:58:29.252304 Final RX Vref Byte 1 = 58 to rank0
7991 09:58:29.255395 Final RX Vref Byte 0 = 65 to rank1
7992 09:58:29.258619 Final RX Vref Byte 1 = 58 to rank1==
7993 09:58:29.262409 Dram Type= 6, Freq= 0, CH_0, rank 0
7994 09:58:29.265537 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7995 09:58:29.265649 ==
7996 09:58:29.265744 DQS Delay:
7997 09:58:29.269154 DQS0 = 0, DQS1 = 0
7998 09:58:29.269260 DQM Delay:
7999 09:58:29.272382 DQM0 = 133, DQM1 = 123
8000 09:58:29.272489 DQ Delay:
8001 09:58:29.275346 DQ0 =130, DQ1 =136, DQ2 =132, DQ3 =132
8002 09:58:29.278460 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =142
8003 09:58:29.282228 DQ8 =114, DQ9 =112, DQ10 =122, DQ11 =118
8004 09:58:29.285160 DQ12 =128, DQ13 =126, DQ14 =134, DQ15 =130
8005 09:58:29.285275
8006 09:58:29.285369
8007 09:58:29.285467
8008 09:58:29.288538 [DramC_TX_OE_Calibration] TA2
8009 09:58:29.292076 Original DQ_B0 (3 6) =30, OEN = 27
8010 09:58:29.294976 Original DQ_B1 (3 6) =30, OEN = 27
8011 09:58:29.298277 24, 0x0, End_B0=24 End_B1=24
8012 09:58:29.301681 25, 0x0, End_B0=25 End_B1=25
8013 09:58:29.304857 26, 0x0, End_B0=26 End_B1=26
8014 09:58:29.304970 27, 0x0, End_B0=27 End_B1=27
8015 09:58:29.308452 28, 0x0, End_B0=28 End_B1=28
8016 09:58:29.311657 29, 0x0, End_B0=29 End_B1=29
8017 09:58:29.315140 30, 0x0, End_B0=30 End_B1=30
8018 09:58:29.318141 31, 0x4141, End_B0=30 End_B1=30
8019 09:58:29.318265 Byte0 end_step=30 best_step=27
8020 09:58:29.321265 Byte1 end_step=30 best_step=27
8021 09:58:29.325106 Byte0 TX OE(2T, 0.5T) = (3, 3)
8022 09:58:29.328267 Byte1 TX OE(2T, 0.5T) = (3, 3)
8023 09:58:29.328380
8024 09:58:29.328474
8025 09:58:29.335011 [DQSOSCAuto] RK0, (LSB)MR18= 0x2415, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
8026 09:58:29.338090 CH0 RK0: MR19=303, MR18=2415
8027 09:58:29.344642 CH0_RK0: MR19=0x303, MR18=0x2415, DQSOSC=391, MR23=63, INC=24, DEC=16
8028 09:58:29.344762
8029 09:58:29.347648 ----->DramcWriteLeveling(PI) begin...
8030 09:58:29.347760 ==
8031 09:58:29.351066 Dram Type= 6, Freq= 0, CH_0, rank 1
8032 09:58:29.357569 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8033 09:58:29.357690 ==
8034 09:58:29.361280 Write leveling (Byte 0): 33 => 33
8035 09:58:29.361389 Write leveling (Byte 1): 29 => 29
8036 09:58:29.364379 DramcWriteLeveling(PI) end<-----
8037 09:58:29.364487
8038 09:58:29.367652 ==
8039 09:58:29.367761 Dram Type= 6, Freq= 0, CH_0, rank 1
8040 09:58:29.374607 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8041 09:58:29.374723 ==
8042 09:58:29.377607 [Gating] SW mode calibration
8043 09:58:29.384320 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8044 09:58:29.387474 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8045 09:58:29.393942 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8046 09:58:29.397525 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8047 09:58:29.400640 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8048 09:58:29.407603 1 4 12 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 1)
8049 09:58:29.410355 1 4 16 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8050 09:58:29.413626 1 4 20 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8051 09:58:29.420363 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8052 09:58:29.423869 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8053 09:58:29.426856 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8054 09:58:29.433818 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8055 09:58:29.436797 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8056 09:58:29.439869 1 5 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
8057 09:58:29.446701 1 5 16 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
8058 09:58:29.449880 1 5 20 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
8059 09:58:29.453377 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8060 09:58:29.459834 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8061 09:58:29.463287 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8062 09:58:29.466327 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8063 09:58:29.472730 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8064 09:58:29.476392 1 6 12 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
8065 09:58:29.479554 1 6 16 | B1->B0 | 3131 4545 | 0 0 | (0 0) (0 0)
8066 09:58:29.486430 1 6 20 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8067 09:58:29.489314 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8068 09:58:29.492359 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8069 09:58:29.499279 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8070 09:58:29.502254 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8071 09:58:29.505899 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8072 09:58:29.512112 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8073 09:58:29.515471 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8074 09:58:29.519204 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8075 09:58:29.525819 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 09:58:29.528699 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 09:58:29.531955 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 09:58:29.539140 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 09:58:29.542180 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 09:58:29.545414 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 09:58:29.552052 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 09:58:29.555309 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 09:58:29.558283 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 09:58:29.565259 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 09:58:29.568140 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 09:58:29.571530 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 09:58:29.578473 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 09:58:29.581758 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8089 09:58:29.584790 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8090 09:58:29.588399 Total UI for P1: 0, mck2ui 16
8091 09:58:29.591620 best dqsien dly found for B0: ( 1, 9, 12)
8092 09:58:29.598230 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8093 09:58:29.601427 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8094 09:58:29.605125 Total UI for P1: 0, mck2ui 16
8095 09:58:29.607998 best dqsien dly found for B1: ( 1, 9, 18)
8096 09:58:29.611613 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8097 09:58:29.614815 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8098 09:58:29.614898
8099 09:58:29.618334 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8100 09:58:29.624443 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8101 09:58:29.624536 [Gating] SW calibration Done
8102 09:58:29.624618 ==
8103 09:58:29.628139 Dram Type= 6, Freq= 0, CH_0, rank 1
8104 09:58:29.634719 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8105 09:58:29.634820 ==
8106 09:58:29.634887 RX Vref Scan: 0
8107 09:58:29.634949
8108 09:58:29.638193 RX Vref 0 -> 0, step: 1
8109 09:58:29.638279
8110 09:58:29.641232 RX Delay 0 -> 252, step: 8
8111 09:58:29.644316 iDelay=208, Bit 0, Center 135 (80 ~ 191) 112
8112 09:58:29.647795 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8113 09:58:29.650906 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8114 09:58:29.657853 iDelay=208, Bit 3, Center 127 (72 ~ 183) 112
8115 09:58:29.660821 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8116 09:58:29.664275 iDelay=208, Bit 5, Center 123 (64 ~ 183) 120
8117 09:58:29.667921 iDelay=208, Bit 6, Center 139 (80 ~ 199) 120
8118 09:58:29.671121 iDelay=208, Bit 7, Center 147 (88 ~ 207) 120
8119 09:58:29.677511 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8120 09:58:29.680651 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8121 09:58:29.683792 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8122 09:58:29.687490 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8123 09:58:29.690747 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8124 09:58:29.697329 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8125 09:58:29.700433 iDelay=208, Bit 14, Center 143 (88 ~ 199) 112
8126 09:58:29.704183 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8127 09:58:29.704296 ==
8128 09:58:29.707496 Dram Type= 6, Freq= 0, CH_0, rank 1
8129 09:58:29.710439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8130 09:58:29.713748 ==
8131 09:58:29.713857 DQS Delay:
8132 09:58:29.713948 DQS0 = 0, DQS1 = 0
8133 09:58:29.716979 DQM Delay:
8134 09:58:29.717084 DQM0 = 133, DQM1 = 129
8135 09:58:29.720070 DQ Delay:
8136 09:58:29.723735 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8137 09:58:29.726858 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =147
8138 09:58:29.730596 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8139 09:58:29.733272 DQ12 =135, DQ13 =135, DQ14 =143, DQ15 =135
8140 09:58:29.733378
8141 09:58:29.733508
8142 09:58:29.733596 ==
8143 09:58:29.736667 Dram Type= 6, Freq= 0, CH_0, rank 1
8144 09:58:29.740232 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8145 09:58:29.740322 ==
8146 09:58:29.743189
8147 09:58:29.743271
8148 09:58:29.743335 TX Vref Scan disable
8149 09:58:29.746752 == TX Byte 0 ==
8150 09:58:29.750029 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8151 09:58:29.753247 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8152 09:58:29.756862 == TX Byte 1 ==
8153 09:58:29.759726 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8154 09:58:29.763531 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8155 09:58:29.763640 ==
8156 09:58:29.766648 Dram Type= 6, Freq= 0, CH_0, rank 1
8157 09:58:29.773251 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8158 09:58:29.773367 ==
8159 09:58:29.785259
8160 09:58:29.788736 TX Vref early break, caculate TX vref
8161 09:58:29.791796 TX Vref=16, minBit 1, minWin=22, winSum=382
8162 09:58:29.795353 TX Vref=18, minBit 1, minWin=22, winSum=386
8163 09:58:29.798354 TX Vref=20, minBit 1, minWin=23, winSum=402
8164 09:58:29.802133 TX Vref=22, minBit 7, minWin=23, winSum=405
8165 09:58:29.805302 TX Vref=24, minBit 1, minWin=24, winSum=412
8166 09:58:29.811542 TX Vref=26, minBit 1, minWin=25, winSum=418
8167 09:58:29.815344 TX Vref=28, minBit 2, minWin=24, winSum=414
8168 09:58:29.818283 TX Vref=30, minBit 1, minWin=23, winSum=403
8169 09:58:29.821617 TX Vref=32, minBit 0, minWin=24, winSum=400
8170 09:58:29.824688 TX Vref=34, minBit 1, minWin=23, winSum=391
8171 09:58:29.831632 [TxChooseVref] Worse bit 1, Min win 25, Win sum 418, Final Vref 26
8172 09:58:29.831717
8173 09:58:29.834854 Final TX Range 0 Vref 26
8174 09:58:29.834932
8175 09:58:29.834994 ==
8176 09:58:29.837852 Dram Type= 6, Freq= 0, CH_0, rank 1
8177 09:58:29.841510 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8178 09:58:29.841634 ==
8179 09:58:29.841727
8180 09:58:29.841816
8181 09:58:29.844897 TX Vref Scan disable
8182 09:58:29.851507 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8183 09:58:29.851615 == TX Byte 0 ==
8184 09:58:29.854541 u2DelayCellOfst[0]=15 cells (4 PI)
8185 09:58:29.857998 u2DelayCellOfst[1]=22 cells (6 PI)
8186 09:58:29.861570 u2DelayCellOfst[2]=15 cells (4 PI)
8187 09:58:29.864359 u2DelayCellOfst[3]=18 cells (5 PI)
8188 09:58:29.867919 u2DelayCellOfst[4]=11 cells (3 PI)
8189 09:58:29.870901 u2DelayCellOfst[5]=0 cells (0 PI)
8190 09:58:29.874548 u2DelayCellOfst[6]=22 cells (6 PI)
8191 09:58:29.877680 u2DelayCellOfst[7]=22 cells (6 PI)
8192 09:58:29.881400 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8193 09:58:29.884492 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8194 09:58:29.887696 == TX Byte 1 ==
8195 09:58:29.891275 u2DelayCellOfst[8]=0 cells (0 PI)
8196 09:58:29.891385 u2DelayCellOfst[9]=3 cells (1 PI)
8197 09:58:29.894732 u2DelayCellOfst[10]=7 cells (2 PI)
8198 09:58:29.897622 u2DelayCellOfst[11]=3 cells (1 PI)
8199 09:58:29.900749 u2DelayCellOfst[12]=15 cells (4 PI)
8200 09:58:29.904553 u2DelayCellOfst[13]=15 cells (4 PI)
8201 09:58:29.907600 u2DelayCellOfst[14]=18 cells (5 PI)
8202 09:58:29.910798 u2DelayCellOfst[15]=11 cells (3 PI)
8203 09:58:29.917818 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8204 09:58:29.920840 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8205 09:58:29.920951 DramC Write-DBI on
8206 09:58:29.921041 ==
8207 09:58:29.923841 Dram Type= 6, Freq= 0, CH_0, rank 1
8208 09:58:29.930422 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8209 09:58:29.930547 ==
8210 09:58:29.930642
8211 09:58:29.930731
8212 09:58:29.930821 TX Vref Scan disable
8213 09:58:29.934696 == TX Byte 0 ==
8214 09:58:29.938407 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8215 09:58:29.941500 == TX Byte 1 ==
8216 09:58:29.944624 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8217 09:58:29.948208 DramC Write-DBI off
8218 09:58:29.948317
8219 09:58:29.948408 [DATLAT]
8220 09:58:29.948497 Freq=1600, CH0 RK1
8221 09:58:29.948587
8222 09:58:29.951209 DATLAT Default: 0xf
8223 09:58:29.951315 0, 0xFFFF, sum = 0
8224 09:58:29.954426 1, 0xFFFF, sum = 0
8225 09:58:29.957817 2, 0xFFFF, sum = 0
8226 09:58:29.957924 3, 0xFFFF, sum = 0
8227 09:58:29.961373 4, 0xFFFF, sum = 0
8228 09:58:29.961487 5, 0xFFFF, sum = 0
8229 09:58:29.964318 6, 0xFFFF, sum = 0
8230 09:58:29.964425 7, 0xFFFF, sum = 0
8231 09:58:29.967970 8, 0xFFFF, sum = 0
8232 09:58:29.968076 9, 0xFFFF, sum = 0
8233 09:58:29.971570 10, 0xFFFF, sum = 0
8234 09:58:29.971678 11, 0xFFFF, sum = 0
8235 09:58:29.974329 12, 0xFFFF, sum = 0
8236 09:58:29.974436 13, 0xFFFF, sum = 0
8237 09:58:29.977821 14, 0x0, sum = 1
8238 09:58:29.977926 15, 0x0, sum = 2
8239 09:58:29.980784 16, 0x0, sum = 3
8240 09:58:29.980890 17, 0x0, sum = 4
8241 09:58:29.984470 best_step = 15
8242 09:58:29.984576
8243 09:58:29.984668 ==
8244 09:58:29.987614 Dram Type= 6, Freq= 0, CH_0, rank 1
8245 09:58:29.990763 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8246 09:58:29.990871 ==
8247 09:58:29.993968 RX Vref Scan: 0
8248 09:58:29.994072
8249 09:58:29.994168 RX Vref 0 -> 0, step: 1
8250 09:58:29.994257
8251 09:58:29.997525 RX Delay 11 -> 252, step: 4
8252 09:58:30.004302 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8253 09:58:30.007833 iDelay=195, Bit 1, Center 136 (83 ~ 190) 108
8254 09:58:30.010970 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8255 09:58:30.013868 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8256 09:58:30.017190 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8257 09:58:30.024035 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8258 09:58:30.027059 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8259 09:58:30.030584 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8260 09:58:30.034046 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8261 09:58:30.037126 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8262 09:58:30.043961 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8263 09:58:30.047129 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8264 09:58:30.050270 iDelay=195, Bit 12, Center 130 (75 ~ 186) 112
8265 09:58:30.053363 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8266 09:58:30.057013 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8267 09:58:30.063406 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8268 09:58:30.063493 ==
8269 09:58:30.066644 Dram Type= 6, Freq= 0, CH_0, rank 1
8270 09:58:30.070424 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8271 09:58:30.070509 ==
8272 09:58:30.070576 DQS Delay:
8273 09:58:30.073601 DQS0 = 0, DQS1 = 0
8274 09:58:30.073689 DQM Delay:
8275 09:58:30.076601 DQM0 = 130, DQM1 = 125
8276 09:58:30.076694 DQ Delay:
8277 09:58:30.080071 DQ0 =128, DQ1 =136, DQ2 =124, DQ3 =128
8278 09:58:30.083407 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =140
8279 09:58:30.087011 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8280 09:58:30.090144 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =132
8281 09:58:30.093368
8282 09:58:30.093454
8283 09:58:30.093518
8284 09:58:30.093578 [DramC_TX_OE_Calibration] TA2
8285 09:58:30.096520 Original DQ_B0 (3 6) =30, OEN = 27
8286 09:58:30.100212 Original DQ_B1 (3 6) =30, OEN = 27
8287 09:58:30.103341 24, 0x0, End_B0=24 End_B1=24
8288 09:58:30.106467 25, 0x0, End_B0=25 End_B1=25
8289 09:58:30.110114 26, 0x0, End_B0=26 End_B1=26
8290 09:58:30.110194 27, 0x0, End_B0=27 End_B1=27
8291 09:58:30.113227 28, 0x0, End_B0=28 End_B1=28
8292 09:58:30.116705 29, 0x0, End_B0=29 End_B1=29
8293 09:58:30.120115 30, 0x0, End_B0=30 End_B1=30
8294 09:58:30.123303 31, 0x4141, End_B0=30 End_B1=30
8295 09:58:30.126437 Byte0 end_step=30 best_step=27
8296 09:58:30.126548 Byte1 end_step=30 best_step=27
8297 09:58:30.129642 Byte0 TX OE(2T, 0.5T) = (3, 3)
8298 09:58:30.132784 Byte1 TX OE(2T, 0.5T) = (3, 3)
8299 09:58:30.132885
8300 09:58:30.132976
8301 09:58:30.142932 [DQSOSCAuto] RK1, (LSB)MR18= 0x2306, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
8302 09:58:30.143057 CH0 RK1: MR19=303, MR18=2306
8303 09:58:30.149494 CH0_RK1: MR19=0x303, MR18=0x2306, DQSOSC=392, MR23=63, INC=24, DEC=16
8304 09:58:30.152746 [RxdqsGatingPostProcess] freq 1600
8305 09:58:30.159717 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8306 09:58:30.162923 best DQS0 dly(2T, 0.5T) = (1, 1)
8307 09:58:30.166099 best DQS1 dly(2T, 0.5T) = (1, 1)
8308 09:58:30.169163 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8309 09:58:30.172784 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8310 09:58:30.176254 best DQS0 dly(2T, 0.5T) = (1, 1)
8311 09:58:30.176356 best DQS1 dly(2T, 0.5T) = (1, 1)
8312 09:58:30.179139 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8313 09:58:30.182487 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8314 09:58:30.185800 Pre-setting of DQS Precalculation
8315 09:58:30.192460 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8316 09:58:30.192569 ==
8317 09:58:30.195929 Dram Type= 6, Freq= 0, CH_1, rank 0
8318 09:58:30.198985 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8319 09:58:30.199088 ==
8320 09:58:30.205298 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8321 09:58:30.208920 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8322 09:58:30.212127 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8323 09:58:30.218582 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8324 09:58:30.227715 [CA 0] Center 41 (12~71) winsize 60
8325 09:58:30.231404 [CA 1] Center 42 (13~72) winsize 60
8326 09:58:30.234511 [CA 2] Center 37 (8~66) winsize 59
8327 09:58:30.237720 [CA 3] Center 35 (6~65) winsize 60
8328 09:58:30.240815 [CA 4] Center 36 (7~66) winsize 60
8329 09:58:30.244279 [CA 5] Center 36 (7~66) winsize 60
8330 09:58:30.244391
8331 09:58:30.247797 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8332 09:58:30.247904
8333 09:58:30.250834 [CATrainingPosCal] consider 1 rank data
8334 09:58:30.254107 u2DelayCellTimex100 = 258/100 ps
8335 09:58:30.260931 CA0 delay=41 (12~71),Diff = 6 PI (22 cell)
8336 09:58:30.263933 CA1 delay=42 (13~72),Diff = 7 PI (26 cell)
8337 09:58:30.267789 CA2 delay=37 (8~66),Diff = 2 PI (7 cell)
8338 09:58:30.270960 CA3 delay=35 (6~65),Diff = 0 PI (0 cell)
8339 09:58:30.274003 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
8340 09:58:30.277036 CA5 delay=36 (7~66),Diff = 1 PI (3 cell)
8341 09:58:30.277130
8342 09:58:30.280827 CA PerBit enable=1, Macro0, CA PI delay=35
8343 09:58:30.280896
8344 09:58:30.283705 [CBTSetCACLKResult] CA Dly = 35
8345 09:58:30.287439 CS Dly: 8 (0~39)
8346 09:58:30.290515 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8347 09:58:30.294001 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8348 09:58:30.294073 ==
8349 09:58:30.297305 Dram Type= 6, Freq= 0, CH_1, rank 1
8350 09:58:30.303810 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8351 09:58:30.303913 ==
8352 09:58:30.306998 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8353 09:58:30.313319 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8354 09:58:30.317007 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8355 09:58:30.323310 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8356 09:58:30.331302 [CA 0] Center 42 (13~71) winsize 59
8357 09:58:30.334208 [CA 1] Center 43 (13~73) winsize 61
8358 09:58:30.337454 [CA 2] Center 38 (9~67) winsize 59
8359 09:58:30.341244 [CA 3] Center 36 (7~66) winsize 60
8360 09:58:30.344252 [CA 4] Center 37 (8~67) winsize 60
8361 09:58:30.347904 [CA 5] Center 37 (8~66) winsize 59
8362 09:58:30.348035
8363 09:58:30.350861 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8364 09:58:30.350940
8365 09:58:30.354174 [CATrainingPosCal] consider 2 rank data
8366 09:58:30.357180 u2DelayCellTimex100 = 258/100 ps
8367 09:58:30.364013 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8368 09:58:30.367083 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8369 09:58:30.370957 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8370 09:58:30.374046 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8371 09:58:30.377234 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8372 09:58:30.380932 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8373 09:58:30.381139
8374 09:58:30.383864 CA PerBit enable=1, Macro0, CA PI delay=36
8375 09:58:30.384002
8376 09:58:30.387454 [CBTSetCACLKResult] CA Dly = 36
8377 09:58:30.390356 CS Dly: 10 (0~44)
8378 09:58:30.393600 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8379 09:58:30.397356 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8380 09:58:30.397483
8381 09:58:30.400332 ----->DramcWriteLeveling(PI) begin...
8382 09:58:30.400420 ==
8383 09:58:30.403740 Dram Type= 6, Freq= 0, CH_1, rank 0
8384 09:58:30.410590 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8385 09:58:30.410707 ==
8386 09:58:30.413517 Write leveling (Byte 0): 23 => 23
8387 09:58:30.416909 Write leveling (Byte 1): 28 => 28
8388 09:58:30.416984 DramcWriteLeveling(PI) end<-----
8389 09:58:30.417045
8390 09:58:30.420134 ==
8391 09:58:30.423414 Dram Type= 6, Freq= 0, CH_1, rank 0
8392 09:58:30.427130 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8393 09:58:30.427245 ==
8394 09:58:30.430306 [Gating] SW mode calibration
8395 09:58:30.436495 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8396 09:58:30.440255 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8397 09:58:30.446405 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 09:58:30.449910 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8399 09:58:30.452933 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 09:58:30.459747 1 4 12 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
8401 09:58:30.463100 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8402 09:58:30.466680 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8403 09:58:30.472865 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8404 09:58:30.476584 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8405 09:58:30.479729 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8406 09:58:30.486315 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8407 09:58:30.489452 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8408 09:58:30.493015 1 5 12 | B1->B0 | 3434 2424 | 1 1 | (1 0) (1 0)
8409 09:58:30.499788 1 5 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8410 09:58:30.502813 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8411 09:58:30.506104 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8412 09:58:30.513033 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8413 09:58:30.516014 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8414 09:58:30.519795 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8415 09:58:30.525919 1 6 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8416 09:58:30.529304 1 6 12 | B1->B0 | 3434 4545 | 1 0 | (0 0) (0 0)
8417 09:58:30.532382 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8418 09:58:30.539357 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8419 09:58:30.542488 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8420 09:58:30.545642 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8421 09:58:30.552666 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8422 09:58:30.555745 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8423 09:58:30.558684 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8424 09:58:30.565819 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8425 09:58:30.568716 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 09:58:30.572103 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 09:58:30.579002 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 09:58:30.582277 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 09:58:30.585397 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 09:58:30.592131 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 09:58:30.595039 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 09:58:30.598665 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 09:58:30.604896 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 09:58:30.608256 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 09:58:30.611771 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 09:58:30.618428 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 09:58:30.621699 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 09:58:30.624754 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 09:58:30.631523 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8440 09:58:30.634621 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8441 09:58:30.638113 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8442 09:58:30.641505 Total UI for P1: 0, mck2ui 16
8443 09:58:30.644742 best dqsien dly found for B0: ( 1, 9, 10)
8444 09:58:30.648246 Total UI for P1: 0, mck2ui 16
8445 09:58:30.651362 best dqsien dly found for B1: ( 1, 9, 10)
8446 09:58:30.654535 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8447 09:58:30.658229 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8448 09:58:30.658309
8449 09:58:30.664559 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8450 09:58:30.667994 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8451 09:58:30.671238 [Gating] SW calibration Done
8452 09:58:30.671317 ==
8453 09:58:30.674582 Dram Type= 6, Freq= 0, CH_1, rank 0
8454 09:58:30.677326 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8455 09:58:30.677435 ==
8456 09:58:30.677503 RX Vref Scan: 0
8457 09:58:30.680654
8458 09:58:30.680731 RX Vref 0 -> 0, step: 1
8459 09:58:30.680794
8460 09:58:30.684155 RX Delay 0 -> 252, step: 8
8461 09:58:30.687270 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8462 09:58:30.690535 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8463 09:58:30.697203 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8464 09:58:30.700905 iDelay=208, Bit 3, Center 135 (88 ~ 183) 96
8465 09:58:30.703829 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8466 09:58:30.707443 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8467 09:58:30.710471 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8468 09:58:30.716740 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8469 09:58:30.720569 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8470 09:58:30.723744 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8471 09:58:30.726999 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8472 09:58:30.733263 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8473 09:58:30.736551 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8474 09:58:30.739735 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8475 09:58:30.743163 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8476 09:58:30.746780 iDelay=208, Bit 15, Center 139 (88 ~ 191) 104
8477 09:58:30.749713 ==
8478 09:58:30.749791 Dram Type= 6, Freq= 0, CH_1, rank 0
8479 09:58:30.756491 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8480 09:58:30.756599 ==
8481 09:58:30.756694 DQS Delay:
8482 09:58:30.759745 DQS0 = 0, DQS1 = 0
8483 09:58:30.759823 DQM Delay:
8484 09:58:30.763510 DQM0 = 138, DQM1 = 129
8485 09:58:30.763594 DQ Delay:
8486 09:58:30.766627 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =135
8487 09:58:30.769640 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8488 09:58:30.772718 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
8489 09:58:30.776252 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8490 09:58:30.776358
8491 09:58:30.776453
8492 09:58:30.776543 ==
8493 09:58:30.779738 Dram Type= 6, Freq= 0, CH_1, rank 0
8494 09:58:30.786483 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8495 09:58:30.786576 ==
8496 09:58:30.786660
8497 09:58:30.786738
8498 09:58:30.786814 TX Vref Scan disable
8499 09:58:30.789807 == TX Byte 0 ==
8500 09:58:30.793215 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8501 09:58:30.800040 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8502 09:58:30.800120 == TX Byte 1 ==
8503 09:58:30.803109 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8504 09:58:30.809682 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8505 09:58:30.809763 ==
8506 09:58:30.813362 Dram Type= 6, Freq= 0, CH_1, rank 0
8507 09:58:30.816416 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8508 09:58:30.816495 ==
8509 09:58:30.829050
8510 09:58:30.832536 TX Vref early break, caculate TX vref
8511 09:58:30.835455 TX Vref=16, minBit 0, minWin=21, winSum=373
8512 09:58:30.838992 TX Vref=18, minBit 5, minWin=22, winSum=384
8513 09:58:30.842230 TX Vref=20, minBit 0, minWin=23, winSum=393
8514 09:58:30.845501 TX Vref=22, minBit 0, minWin=24, winSum=399
8515 09:58:30.848555 TX Vref=24, minBit 0, minWin=24, winSum=412
8516 09:58:30.855429 TX Vref=26, minBit 0, minWin=24, winSum=417
8517 09:58:30.858628 TX Vref=28, minBit 0, minWin=24, winSum=417
8518 09:58:30.862039 TX Vref=30, minBit 0, minWin=24, winSum=408
8519 09:58:30.865035 TX Vref=32, minBit 0, minWin=23, winSum=401
8520 09:58:30.868723 TX Vref=34, minBit 1, minWin=22, winSum=389
8521 09:58:30.874991 [TxChooseVref] Worse bit 0, Min win 24, Win sum 417, Final Vref 26
8522 09:58:30.875072
8523 09:58:30.878137 Final TX Range 0 Vref 26
8524 09:58:30.878218
8525 09:58:30.878289 ==
8526 09:58:30.881754 Dram Type= 6, Freq= 0, CH_1, rank 0
8527 09:58:30.884856 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8528 09:58:30.884937 ==
8529 09:58:30.885002
8530 09:58:30.885064
8531 09:58:30.888605 TX Vref Scan disable
8532 09:58:30.894831 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8533 09:58:30.894916 == TX Byte 0 ==
8534 09:58:30.898520 u2DelayCellOfst[0]=18 cells (5 PI)
8535 09:58:30.901322 u2DelayCellOfst[1]=15 cells (4 PI)
8536 09:58:30.904758 u2DelayCellOfst[2]=0 cells (0 PI)
8537 09:58:30.907827 u2DelayCellOfst[3]=7 cells (2 PI)
8538 09:58:30.911517 u2DelayCellOfst[4]=7 cells (2 PI)
8539 09:58:30.914519 u2DelayCellOfst[5]=26 cells (7 PI)
8540 09:58:30.918269 u2DelayCellOfst[6]=22 cells (6 PI)
8541 09:58:30.921481 u2DelayCellOfst[7]=7 cells (2 PI)
8542 09:58:30.924568 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8543 09:58:30.927710 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8544 09:58:30.931003 == TX Byte 1 ==
8545 09:58:30.934813 u2DelayCellOfst[8]=0 cells (0 PI)
8546 09:58:30.934896 u2DelayCellOfst[9]=3 cells (1 PI)
8547 09:58:30.938021 u2DelayCellOfst[10]=11 cells (3 PI)
8548 09:58:30.941079 u2DelayCellOfst[11]=3 cells (1 PI)
8549 09:58:30.944600 u2DelayCellOfst[12]=15 cells (4 PI)
8550 09:58:30.947606 u2DelayCellOfst[13]=15 cells (4 PI)
8551 09:58:30.950768 u2DelayCellOfst[14]=18 cells (5 PI)
8552 09:58:30.954576 u2DelayCellOfst[15]=18 cells (5 PI)
8553 09:58:30.960948 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8554 09:58:30.963973 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8555 09:58:30.964060 DramC Write-DBI on
8556 09:58:30.964145 ==
8557 09:58:30.967632 Dram Type= 6, Freq= 0, CH_1, rank 0
8558 09:58:30.973866 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8559 09:58:30.973949 ==
8560 09:58:30.974015
8561 09:58:30.974075
8562 09:58:30.974151 TX Vref Scan disable
8563 09:58:30.978283 == TX Byte 0 ==
8564 09:58:30.981614 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8565 09:58:30.985122 == TX Byte 1 ==
8566 09:58:30.987908 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8567 09:58:30.991400 DramC Write-DBI off
8568 09:58:30.991479
8569 09:58:30.991543 [DATLAT]
8570 09:58:30.991602 Freq=1600, CH1 RK0
8571 09:58:30.991659
8572 09:58:30.994553 DATLAT Default: 0xf
8573 09:58:30.998266 0, 0xFFFF, sum = 0
8574 09:58:30.998344 1, 0xFFFF, sum = 0
8575 09:58:31.001340 2, 0xFFFF, sum = 0
8576 09:58:31.001478 3, 0xFFFF, sum = 0
8577 09:58:31.004485 4, 0xFFFF, sum = 0
8578 09:58:31.004587 5, 0xFFFF, sum = 0
8579 09:58:31.007955 6, 0xFFFF, sum = 0
8580 09:58:31.008061 7, 0xFFFF, sum = 0
8581 09:58:31.011515 8, 0xFFFF, sum = 0
8582 09:58:31.011601 9, 0xFFFF, sum = 0
8583 09:58:31.014272 10, 0xFFFF, sum = 0
8584 09:58:31.014350 11, 0xFFFF, sum = 0
8585 09:58:31.017814 12, 0xFFFF, sum = 0
8586 09:58:31.017894 13, 0xFFFF, sum = 0
8587 09:58:31.020862 14, 0x0, sum = 1
8588 09:58:31.020940 15, 0x0, sum = 2
8589 09:58:31.024102 16, 0x0, sum = 3
8590 09:58:31.024208 17, 0x0, sum = 4
8591 09:58:31.027747 best_step = 15
8592 09:58:31.027822
8593 09:58:31.027903 ==
8594 09:58:31.030848 Dram Type= 6, Freq= 0, CH_1, rank 0
8595 09:58:31.034035 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8596 09:58:31.034136 ==
8597 09:58:31.037872 RX Vref Scan: 1
8598 09:58:31.037945
8599 09:58:31.038037 Set Vref Range= 24 -> 127
8600 09:58:31.038167
8601 09:58:31.041009 RX Vref 24 -> 127, step: 1
8602 09:58:31.041108
8603 09:58:31.044046 RX Delay 11 -> 252, step: 4
8604 09:58:31.044147
8605 09:58:31.047770 Set Vref, RX VrefLevel [Byte0]: 24
8606 09:58:31.050590 [Byte1]: 24
8607 09:58:31.050667
8608 09:58:31.054294 Set Vref, RX VrefLevel [Byte0]: 25
8609 09:58:31.057428 [Byte1]: 25
8610 09:58:31.061079
8611 09:58:31.061191 Set Vref, RX VrefLevel [Byte0]: 26
8612 09:58:31.064175 [Byte1]: 26
8613 09:58:31.068696
8614 09:58:31.068775 Set Vref, RX VrefLevel [Byte0]: 27
8615 09:58:31.071824 [Byte1]: 27
8616 09:58:31.076201
8617 09:58:31.076283 Set Vref, RX VrefLevel [Byte0]: 28
8618 09:58:31.079709 [Byte1]: 28
8619 09:58:31.083878
8620 09:58:31.084022 Set Vref, RX VrefLevel [Byte0]: 29
8621 09:58:31.087010 [Byte1]: 29
8622 09:58:31.091501
8623 09:58:31.091585 Set Vref, RX VrefLevel [Byte0]: 30
8624 09:58:31.095001 [Byte1]: 30
8625 09:58:31.099263
8626 09:58:31.099345 Set Vref, RX VrefLevel [Byte0]: 31
8627 09:58:31.102291 [Byte1]: 31
8628 09:58:31.106852
8629 09:58:31.106935 Set Vref, RX VrefLevel [Byte0]: 32
8630 09:58:31.109836 [Byte1]: 32
8631 09:58:31.114239
8632 09:58:31.114319 Set Vref, RX VrefLevel [Byte0]: 33
8633 09:58:31.117370 [Byte1]: 33
8634 09:58:31.121915
8635 09:58:31.121995 Set Vref, RX VrefLevel [Byte0]: 34
8636 09:58:31.125360 [Byte1]: 34
8637 09:58:31.129756
8638 09:58:31.129856 Set Vref, RX VrefLevel [Byte0]: 35
8639 09:58:31.132902 [Byte1]: 35
8640 09:58:31.137459
8641 09:58:31.137555 Set Vref, RX VrefLevel [Byte0]: 36
8642 09:58:31.140511 [Byte1]: 36
8643 09:58:31.145096
8644 09:58:31.145197 Set Vref, RX VrefLevel [Byte0]: 37
8645 09:58:31.148206 [Byte1]: 37
8646 09:58:31.152498
8647 09:58:31.152601 Set Vref, RX VrefLevel [Byte0]: 38
8648 09:58:31.155762 [Byte1]: 38
8649 09:58:31.159913
8650 09:58:31.160015 Set Vref, RX VrefLevel [Byte0]: 39
8651 09:58:31.163284 [Byte1]: 39
8652 09:58:31.167536
8653 09:58:31.167620 Set Vref, RX VrefLevel [Byte0]: 40
8654 09:58:31.170779 [Byte1]: 40
8655 09:58:31.175214
8656 09:58:31.175297 Set Vref, RX VrefLevel [Byte0]: 41
8657 09:58:31.178744 [Byte1]: 41
8658 09:58:31.183238
8659 09:58:31.183319 Set Vref, RX VrefLevel [Byte0]: 42
8660 09:58:31.186099 [Byte1]: 42
8661 09:58:31.190153
8662 09:58:31.190234 Set Vref, RX VrefLevel [Byte0]: 43
8663 09:58:31.194054 [Byte1]: 43
8664 09:58:31.197869
8665 09:58:31.197949 Set Vref, RX VrefLevel [Byte0]: 44
8666 09:58:31.201245 [Byte1]: 44
8667 09:58:31.205468
8668 09:58:31.205564 Set Vref, RX VrefLevel [Byte0]: 45
8669 09:58:31.209109 [Byte1]: 45
8670 09:58:31.213465
8671 09:58:31.213545 Set Vref, RX VrefLevel [Byte0]: 46
8672 09:58:31.216714 [Byte1]: 46
8673 09:58:31.220868
8674 09:58:31.220949 Set Vref, RX VrefLevel [Byte0]: 47
8675 09:58:31.223968 [Byte1]: 47
8676 09:58:31.228209
8677 09:58:31.228289 Set Vref, RX VrefLevel [Byte0]: 48
8678 09:58:31.231716 [Byte1]: 48
8679 09:58:31.235918
8680 09:58:31.236000 Set Vref, RX VrefLevel [Byte0]: 49
8681 09:58:31.239255 [Byte1]: 49
8682 09:58:31.243594
8683 09:58:31.243676 Set Vref, RX VrefLevel [Byte0]: 50
8684 09:58:31.247400 [Byte1]: 50
8685 09:58:31.251174
8686 09:58:31.251259 Set Vref, RX VrefLevel [Byte0]: 51
8687 09:58:31.254970 [Byte1]: 51
8688 09:58:31.258909
8689 09:58:31.258991 Set Vref, RX VrefLevel [Byte0]: 52
8690 09:58:31.261968 [Byte1]: 52
8691 09:58:31.266361
8692 09:58:31.266442 Set Vref, RX VrefLevel [Byte0]: 53
8693 09:58:31.269943 [Byte1]: 53
8694 09:58:31.274264
8695 09:58:31.274345 Set Vref, RX VrefLevel [Byte0]: 54
8696 09:58:31.277546 [Byte1]: 54
8697 09:58:31.281921
8698 09:58:31.282003 Set Vref, RX VrefLevel [Byte0]: 55
8699 09:58:31.284980 [Byte1]: 55
8700 09:58:31.289256
8701 09:58:31.289332 Set Vref, RX VrefLevel [Byte0]: 56
8702 09:58:31.292901 [Byte1]: 56
8703 09:58:31.296931
8704 09:58:31.297018 Set Vref, RX VrefLevel [Byte0]: 57
8705 09:58:31.300696 [Byte1]: 57
8706 09:58:31.304887
8707 09:58:31.304969 Set Vref, RX VrefLevel [Byte0]: 58
8708 09:58:31.308169 [Byte1]: 58
8709 09:58:31.312280
8710 09:58:31.312362 Set Vref, RX VrefLevel [Byte0]: 59
8711 09:58:31.315334 [Byte1]: 59
8712 09:58:31.319592
8713 09:58:31.319684 Set Vref, RX VrefLevel [Byte0]: 60
8714 09:58:31.323149 [Byte1]: 60
8715 09:58:31.327540
8716 09:58:31.327622 Set Vref, RX VrefLevel [Byte0]: 61
8717 09:58:31.330639 [Byte1]: 61
8718 09:58:31.335110
8719 09:58:31.335187 Set Vref, RX VrefLevel [Byte0]: 62
8720 09:58:31.338775 [Byte1]: 62
8721 09:58:31.342627
8722 09:58:31.342725 Set Vref, RX VrefLevel [Byte0]: 63
8723 09:58:31.346132 [Byte1]: 63
8724 09:58:31.350560
8725 09:58:31.350636 Set Vref, RX VrefLevel [Byte0]: 64
8726 09:58:31.353772 [Byte1]: 64
8727 09:58:31.358027
8728 09:58:31.358142 Set Vref, RX VrefLevel [Byte0]: 65
8729 09:58:31.361256 [Byte1]: 65
8730 09:58:31.365739
8731 09:58:31.365823 Set Vref, RX VrefLevel [Byte0]: 66
8732 09:58:31.368849 [Byte1]: 66
8733 09:58:31.373300
8734 09:58:31.373405 Set Vref, RX VrefLevel [Byte0]: 67
8735 09:58:31.376546 [Byte1]: 67
8736 09:58:31.380904
8737 09:58:31.380984 Set Vref, RX VrefLevel [Byte0]: 68
8738 09:58:31.384318 [Byte1]: 68
8739 09:58:31.388169
8740 09:58:31.388270 Set Vref, RX VrefLevel [Byte0]: 69
8741 09:58:31.391894 [Byte1]: 69
8742 09:58:31.395716
8743 09:58:31.395790 Set Vref, RX VrefLevel [Byte0]: 70
8744 09:58:31.399352 [Byte1]: 70
8745 09:58:31.403525
8746 09:58:31.403624 Set Vref, RX VrefLevel [Byte0]: 71
8747 09:58:31.407058 [Byte1]: 71
8748 09:58:31.411404
8749 09:58:31.411483 Set Vref, RX VrefLevel [Byte0]: 72
8750 09:58:31.414472 [Byte1]: 72
8751 09:58:31.418890
8752 09:58:31.418987 Final RX Vref Byte 0 = 51 to rank0
8753 09:58:31.421822 Final RX Vref Byte 1 = 60 to rank0
8754 09:58:31.425550 Final RX Vref Byte 0 = 51 to rank1
8755 09:58:31.428646 Final RX Vref Byte 1 = 60 to rank1==
8756 09:58:31.431923 Dram Type= 6, Freq= 0, CH_1, rank 0
8757 09:58:31.438971 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8758 09:58:31.439054 ==
8759 09:58:31.439139 DQS Delay:
8760 09:58:31.442024 DQS0 = 0, DQS1 = 0
8761 09:58:31.442105 DQM Delay:
8762 09:58:31.442168 DQM0 = 134, DQM1 = 128
8763 09:58:31.445164 DQ Delay:
8764 09:58:31.448303 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =132
8765 09:58:31.452064 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =128
8766 09:58:31.455308 DQ8 =116, DQ9 =114, DQ10 =130, DQ11 =118
8767 09:58:31.458291 DQ12 =136, DQ13 =136, DQ14 =138, DQ15 =138
8768 09:58:31.458372
8769 09:58:31.458435
8770 09:58:31.458493
8771 09:58:31.461760 [DramC_TX_OE_Calibration] TA2
8772 09:58:31.464952 Original DQ_B0 (3 6) =30, OEN = 27
8773 09:58:31.468441 Original DQ_B1 (3 6) =30, OEN = 27
8774 09:58:31.471643 24, 0x0, End_B0=24 End_B1=24
8775 09:58:31.471725 25, 0x0, End_B0=25 End_B1=25
8776 09:58:31.474925 26, 0x0, End_B0=26 End_B1=26
8777 09:58:31.478193 27, 0x0, End_B0=27 End_B1=27
8778 09:58:31.481189 28, 0x0, End_B0=28 End_B1=28
8779 09:58:31.484996 29, 0x0, End_B0=29 End_B1=29
8780 09:58:31.485078 30, 0x0, End_B0=30 End_B1=30
8781 09:58:31.488345 31, 0x4141, End_B0=30 End_B1=30
8782 09:58:31.491381 Byte0 end_step=30 best_step=27
8783 09:58:31.494473 Byte1 end_step=30 best_step=27
8784 09:58:31.498199 Byte0 TX OE(2T, 0.5T) = (3, 3)
8785 09:58:31.501338 Byte1 TX OE(2T, 0.5T) = (3, 3)
8786 09:58:31.501429
8787 09:58:31.501550
8788 09:58:31.507662 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
8789 09:58:31.511344 CH1 RK0: MR19=303, MR18=1A0F
8790 09:58:31.517818 CH1_RK0: MR19=0x303, MR18=0x1A0F, DQSOSC=396, MR23=63, INC=23, DEC=15
8791 09:58:31.517901
8792 09:58:31.521189 ----->DramcWriteLeveling(PI) begin...
8793 09:58:31.521291 ==
8794 09:58:31.524236 Dram Type= 6, Freq= 0, CH_1, rank 1
8795 09:58:31.528068 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8796 09:58:31.528151 ==
8797 09:58:31.530945 Write leveling (Byte 0): 24 => 24
8798 09:58:31.534594 Write leveling (Byte 1): 29 => 29
8799 09:58:31.537749 DramcWriteLeveling(PI) end<-----
8800 09:58:31.537830
8801 09:58:31.537924 ==
8802 09:58:31.540767 Dram Type= 6, Freq= 0, CH_1, rank 1
8803 09:58:31.544201 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8804 09:58:31.547223 ==
8805 09:58:31.547304 [Gating] SW mode calibration
8806 09:58:31.557314 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8807 09:58:31.560464 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8808 09:58:31.564269 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8809 09:58:31.570402 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8810 09:58:31.573911 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 09:58:31.577287 1 4 12 | B1->B0 | 3232 2828 | 1 0 | (1 1) (0 0)
8812 09:58:31.583965 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8813 09:58:31.587204 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8814 09:58:31.590256 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8815 09:58:31.596928 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8816 09:58:31.600257 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8817 09:58:31.603465 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8818 09:58:31.609862 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8819 09:58:31.613176 1 5 12 | B1->B0 | 3030 3434 | 0 1 | (0 1) (1 0)
8820 09:58:31.616435 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8821 09:58:31.623150 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8822 09:58:31.626813 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8823 09:58:31.630076 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8824 09:58:31.636535 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8825 09:58:31.639500 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8826 09:58:31.643075 1 6 8 | B1->B0 | 2827 2323 | 1 0 | (0 0) (0 0)
8827 09:58:31.649539 1 6 12 | B1->B0 | 3f3f 2929 | 0 1 | (0 0) (0 0)
8828 09:58:31.653227 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8829 09:58:31.656423 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8830 09:58:31.662812 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8831 09:58:31.665998 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8832 09:58:31.669166 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8833 09:58:31.676171 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8834 09:58:31.679317 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8835 09:58:31.682433 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8836 09:58:31.688894 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8837 09:58:31.692241 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8838 09:58:31.695706 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 09:58:31.702372 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 09:58:31.705857 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 09:58:31.709023 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 09:58:31.716036 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 09:58:31.718599 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 09:58:31.722394 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 09:58:31.728542 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 09:58:31.732447 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 09:58:31.735490 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 09:58:31.742072 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 09:58:31.745585 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 09:58:31.748393 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8851 09:58:31.755243 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8852 09:58:31.758571 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8853 09:58:31.761710 Total UI for P1: 0, mck2ui 16
8854 09:58:31.765426 best dqsien dly found for B0: ( 1, 9, 10)
8855 09:58:31.768706 Total UI for P1: 0, mck2ui 16
8856 09:58:31.771714 best dqsien dly found for B1: ( 1, 9, 10)
8857 09:58:31.774953 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8858 09:58:31.778130 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8859 09:58:31.778211
8860 09:58:31.781435 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8861 09:58:31.785243 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8862 09:58:31.788530 [Gating] SW calibration Done
8863 09:58:31.788613 ==
8864 09:58:31.791698 Dram Type= 6, Freq= 0, CH_1, rank 1
8865 09:58:31.798330 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8866 09:58:31.798429 ==
8867 09:58:31.798495 RX Vref Scan: 0
8868 09:58:31.798555
8869 09:58:31.801157 RX Vref 0 -> 0, step: 1
8870 09:58:31.801239
8871 09:58:31.804797 RX Delay 0 -> 252, step: 8
8872 09:58:31.808254 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8873 09:58:31.811331 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8874 09:58:31.814671 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8875 09:58:31.817957 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8876 09:58:31.824856 iDelay=208, Bit 4, Center 139 (80 ~ 199) 120
8877 09:58:31.828302 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8878 09:58:31.831279 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8879 09:58:31.834451 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8880 09:58:31.837678 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8881 09:58:31.844305 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8882 09:58:31.847595 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8883 09:58:31.850721 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8884 09:58:31.853948 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8885 09:58:31.860808 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8886 09:58:31.864278 iDelay=208, Bit 14, Center 135 (72 ~ 199) 128
8887 09:58:31.867362 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8888 09:58:31.867463 ==
8889 09:58:31.870573 Dram Type= 6, Freq= 0, CH_1, rank 1
8890 09:58:31.873813 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8891 09:58:31.873887 ==
8892 09:58:31.876925 DQS Delay:
8893 09:58:31.876997 DQS0 = 0, DQS1 = 0
8894 09:58:31.880761 DQM Delay:
8895 09:58:31.880862 DQM0 = 138, DQM1 = 129
8896 09:58:31.883860 DQ Delay:
8897 09:58:31.887098 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8898 09:58:31.890306 DQ4 =139, DQ5 =151, DQ6 =147, DQ7 =135
8899 09:58:31.893908 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8900 09:58:31.897047 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8901 09:58:31.897150
8902 09:58:31.897240
8903 09:58:31.897327 ==
8904 09:58:31.900186 Dram Type= 6, Freq= 0, CH_1, rank 1
8905 09:58:31.903813 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8906 09:58:31.903886 ==
8907 09:58:31.903948
8908 09:58:31.906904
8909 09:58:31.906975 TX Vref Scan disable
8910 09:58:31.910203 == TX Byte 0 ==
8911 09:58:31.913644 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8912 09:58:31.917212 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8913 09:58:31.920093 == TX Byte 1 ==
8914 09:58:31.923593 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8915 09:58:31.926878 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8916 09:58:31.926957 ==
8917 09:58:31.930125 Dram Type= 6, Freq= 0, CH_1, rank 1
8918 09:58:31.937078 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8919 09:58:31.937184 ==
8920 09:58:31.948791
8921 09:58:31.951955 TX Vref early break, caculate TX vref
8922 09:58:31.955274 TX Vref=16, minBit 0, minWin=23, winSum=385
8923 09:58:31.958358 TX Vref=18, minBit 1, minWin=22, winSum=394
8924 09:58:31.961612 TX Vref=20, minBit 1, minWin=23, winSum=401
8925 09:58:31.965069 TX Vref=22, minBit 1, minWin=25, winSum=413
8926 09:58:31.968502 TX Vref=24, minBit 0, minWin=26, winSum=422
8927 09:58:31.974860 TX Vref=26, minBit 1, minWin=25, winSum=427
8928 09:58:31.978158 TX Vref=28, minBit 0, minWin=26, winSum=426
8929 09:58:31.981333 TX Vref=30, minBit 1, minWin=25, winSum=420
8930 09:58:31.985138 TX Vref=32, minBit 0, minWin=24, winSum=406
8931 09:58:31.988395 TX Vref=34, minBit 0, minWin=23, winSum=398
8932 09:58:31.994638 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 28
8933 09:58:31.994725
8934 09:58:31.998420 Final TX Range 0 Vref 28
8935 09:58:31.998506
8936 09:58:31.998568 ==
8937 09:58:32.001614 Dram Type= 6, Freq= 0, CH_1, rank 1
8938 09:58:32.004785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8939 09:58:32.004889 ==
8940 09:58:32.004984
8941 09:58:32.005072
8942 09:58:32.007825 TX Vref Scan disable
8943 09:58:32.014211 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8944 09:58:32.014387 == TX Byte 0 ==
8945 09:58:32.017336 u2DelayCellOfst[0]=18 cells (5 PI)
8946 09:58:32.021126 u2DelayCellOfst[1]=15 cells (4 PI)
8947 09:58:32.024228 u2DelayCellOfst[2]=0 cells (0 PI)
8948 09:58:32.027407 u2DelayCellOfst[3]=7 cells (2 PI)
8949 09:58:32.030970 u2DelayCellOfst[4]=7 cells (2 PI)
8950 09:58:32.033875 u2DelayCellOfst[5]=22 cells (6 PI)
8951 09:58:32.037111 u2DelayCellOfst[6]=22 cells (6 PI)
8952 09:58:32.040673 u2DelayCellOfst[7]=7 cells (2 PI)
8953 09:58:32.044136 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8954 09:58:32.047299 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8955 09:58:32.050431 == TX Byte 1 ==
8956 09:58:32.054109 u2DelayCellOfst[8]=0 cells (0 PI)
8957 09:58:32.057295 u2DelayCellOfst[9]=3 cells (1 PI)
8958 09:58:32.060470 u2DelayCellOfst[10]=11 cells (3 PI)
8959 09:58:32.063614 u2DelayCellOfst[11]=3 cells (1 PI)
8960 09:58:32.063691 u2DelayCellOfst[12]=15 cells (4 PI)
8961 09:58:32.066631 u2DelayCellOfst[13]=18 cells (5 PI)
8962 09:58:32.070508 u2DelayCellOfst[14]=18 cells (5 PI)
8963 09:58:32.073707 u2DelayCellOfst[15]=18 cells (5 PI)
8964 09:58:32.080523 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8965 09:58:32.083529 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8966 09:58:32.083616 DramC Write-DBI on
8967 09:58:32.086830 ==
8968 09:58:32.090148 Dram Type= 6, Freq= 0, CH_1, rank 1
8969 09:58:32.093263 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8970 09:58:32.093364 ==
8971 09:58:32.093457
8972 09:58:32.093521
8973 09:58:32.096488 TX Vref Scan disable
8974 09:58:32.096593 == TX Byte 0 ==
8975 09:58:32.103379 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8976 09:58:32.103490 == TX Byte 1 ==
8977 09:58:32.106537 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8978 09:58:32.109655 DramC Write-DBI off
8979 09:58:32.109754
8980 09:58:32.109822 [DATLAT]
8981 09:58:32.113312 Freq=1600, CH1 RK1
8982 09:58:32.113417
8983 09:58:32.113486 DATLAT Default: 0xf
8984 09:58:32.116591 0, 0xFFFF, sum = 0
8985 09:58:32.116669 1, 0xFFFF, sum = 0
8986 09:58:32.120120 2, 0xFFFF, sum = 0
8987 09:58:32.120226 3, 0xFFFF, sum = 0
8988 09:58:32.123063 4, 0xFFFF, sum = 0
8989 09:58:32.126300 5, 0xFFFF, sum = 0
8990 09:58:32.126404 6, 0xFFFF, sum = 0
8991 09:58:32.129300 7, 0xFFFF, sum = 0
8992 09:58:32.129404 8, 0xFFFF, sum = 0
8993 09:58:32.133247 9, 0xFFFF, sum = 0
8994 09:58:32.133351 10, 0xFFFF, sum = 0
8995 09:58:32.136420 11, 0xFFFF, sum = 0
8996 09:58:32.136521 12, 0xFFFF, sum = 0
8997 09:58:32.139702 13, 0xFFFF, sum = 0
8998 09:58:32.139800 14, 0x0, sum = 1
8999 09:58:32.142741 15, 0x0, sum = 2
9000 09:58:32.142815 16, 0x0, sum = 3
9001 09:58:32.146257 17, 0x0, sum = 4
9002 09:58:32.146331 best_step = 15
9003 09:58:32.146393
9004 09:58:32.146455 ==
9005 09:58:32.149566 Dram Type= 6, Freq= 0, CH_1, rank 1
9006 09:58:32.152663 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9007 09:58:32.156237 ==
9008 09:58:32.156339 RX Vref Scan: 0
9009 09:58:32.156430
9010 09:58:32.159417 RX Vref 0 -> 0, step: 1
9011 09:58:32.159516
9012 09:58:32.162423 RX Delay 11 -> 252, step: 4
9013 09:58:32.165635 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9014 09:58:32.168928 iDelay=203, Bit 1, Center 126 (75 ~ 178) 104
9015 09:58:32.172732 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9016 09:58:32.179062 iDelay=203, Bit 3, Center 132 (83 ~ 182) 100
9017 09:58:32.182286 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9018 09:58:32.185359 iDelay=203, Bit 5, Center 144 (95 ~ 194) 100
9019 09:58:32.188880 iDelay=203, Bit 6, Center 148 (95 ~ 202) 108
9020 09:58:32.192372 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9021 09:58:32.198799 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9022 09:58:32.201867 iDelay=203, Bit 9, Center 114 (59 ~ 170) 112
9023 09:58:32.205664 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9024 09:58:32.208889 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9025 09:58:32.211971 iDelay=203, Bit 12, Center 136 (83 ~ 190) 108
9026 09:58:32.218951 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9027 09:58:32.222081 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9028 09:58:32.225406 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9029 09:58:32.225497 ==
9030 09:58:32.228898 Dram Type= 6, Freq= 0, CH_1, rank 1
9031 09:58:32.232305 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9032 09:58:32.235316 ==
9033 09:58:32.235400 DQS Delay:
9034 09:58:32.235467 DQS0 = 0, DQS1 = 0
9035 09:58:32.238760 DQM Delay:
9036 09:58:32.238868 DQM0 = 134, DQM1 = 126
9037 09:58:32.241817 DQ Delay:
9038 09:58:32.245058 DQ0 =138, DQ1 =126, DQ2 =122, DQ3 =132
9039 09:58:32.248233 DQ4 =134, DQ5 =144, DQ6 =148, DQ7 =130
9040 09:58:32.251685 DQ8 =112, DQ9 =114, DQ10 =126, DQ11 =116
9041 09:58:32.255187 DQ12 =136, DQ13 =134, DQ14 =134, DQ15 =138
9042 09:58:32.255270
9043 09:58:32.255336
9044 09:58:32.255407
9045 09:58:32.258086 [DramC_TX_OE_Calibration] TA2
9046 09:58:32.261692 Original DQ_B0 (3 6) =30, OEN = 27
9047 09:58:32.264679 Original DQ_B1 (3 6) =30, OEN = 27
9048 09:58:32.268066 24, 0x0, End_B0=24 End_B1=24
9049 09:58:32.268151 25, 0x0, End_B0=25 End_B1=25
9050 09:58:32.271276 26, 0x0, End_B0=26 End_B1=26
9051 09:58:32.274885 27, 0x0, End_B0=27 End_B1=27
9052 09:58:32.278149 28, 0x0, End_B0=28 End_B1=28
9053 09:58:32.281208 29, 0x0, End_B0=29 End_B1=29
9054 09:58:32.281294 30, 0x0, End_B0=30 End_B1=30
9055 09:58:32.284365 31, 0x5151, End_B0=30 End_B1=30
9056 09:58:32.288292 Byte0 end_step=30 best_step=27
9057 09:58:32.291427 Byte1 end_step=30 best_step=27
9058 09:58:32.294646 Byte0 TX OE(2T, 0.5T) = (3, 3)
9059 09:58:32.298169 Byte1 TX OE(2T, 0.5T) = (3, 3)
9060 09:58:32.298252
9061 09:58:32.298317
9062 09:58:32.304143 [DQSOSCAuto] RK1, (LSB)MR18= 0xc08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
9063 09:58:32.308011 CH1 RK1: MR19=303, MR18=C08
9064 09:58:32.314507 CH1_RK1: MR19=0x303, MR18=0xC08, DQSOSC=403, MR23=63, INC=22, DEC=15
9065 09:58:32.317428 [RxdqsGatingPostProcess] freq 1600
9066 09:58:32.321141 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9067 09:58:32.324158 best DQS0 dly(2T, 0.5T) = (1, 1)
9068 09:58:32.327248 best DQS1 dly(2T, 0.5T) = (1, 1)
9069 09:58:32.331111 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9070 09:58:32.334120 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9071 09:58:32.337344 best DQS0 dly(2T, 0.5T) = (1, 1)
9072 09:58:32.341414 best DQS1 dly(2T, 0.5T) = (1, 1)
9073 09:58:32.343888 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9074 09:58:32.347585 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9075 09:58:32.350695 Pre-setting of DQS Precalculation
9076 09:58:32.353762 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9077 09:58:32.360774 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9078 09:58:32.370456 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9079 09:58:32.370541
9080 09:58:32.370609
9081 09:58:32.373591 [Calibration Summary] 3200 Mbps
9082 09:58:32.373662 CH 0, Rank 0
9083 09:58:32.377206 SW Impedance : PASS
9084 09:58:32.377303 DUTY Scan : NO K
9085 09:58:32.380056 ZQ Calibration : PASS
9086 09:58:32.383733 Jitter Meter : NO K
9087 09:58:32.383811 CBT Training : PASS
9088 09:58:32.387035 Write leveling : PASS
9089 09:58:32.387136 RX DQS gating : PASS
9090 09:58:32.389996 RX DQ/DQS(RDDQC) : PASS
9091 09:58:32.393516 TX DQ/DQS : PASS
9092 09:58:32.393594 RX DATLAT : PASS
9093 09:58:32.397033 RX DQ/DQS(Engine): PASS
9094 09:58:32.400221 TX OE : PASS
9095 09:58:32.400296 All Pass.
9096 09:58:32.400362
9097 09:58:32.400422 CH 0, Rank 1
9098 09:58:32.403185 SW Impedance : PASS
9099 09:58:32.406797 DUTY Scan : NO K
9100 09:58:32.406871 ZQ Calibration : PASS
9101 09:58:32.410007 Jitter Meter : NO K
9102 09:58:32.413607 CBT Training : PASS
9103 09:58:32.413683 Write leveling : PASS
9104 09:58:32.416606 RX DQS gating : PASS
9105 09:58:32.419717 RX DQ/DQS(RDDQC) : PASS
9106 09:58:32.419791 TX DQ/DQS : PASS
9107 09:58:32.423566 RX DATLAT : PASS
9108 09:58:32.426648 RX DQ/DQS(Engine): PASS
9109 09:58:32.426739 TX OE : PASS
9110 09:58:32.429760 All Pass.
9111 09:58:32.429860
9112 09:58:32.429955 CH 1, Rank 0
9113 09:58:32.432925 SW Impedance : PASS
9114 09:58:32.433022 DUTY Scan : NO K
9115 09:58:32.436544 ZQ Calibration : PASS
9116 09:58:32.439563 Jitter Meter : NO K
9117 09:58:32.439666 CBT Training : PASS
9118 09:58:32.442949 Write leveling : PASS
9119 09:58:32.446112 RX DQS gating : PASS
9120 09:58:32.446188 RX DQ/DQS(RDDQC) : PASS
9121 09:58:32.449282 TX DQ/DQS : PASS
9122 09:58:32.453224 RX DATLAT : PASS
9123 09:58:32.453330 RX DQ/DQS(Engine): PASS
9124 09:58:32.456254 TX OE : PASS
9125 09:58:32.456352 All Pass.
9126 09:58:32.456443
9127 09:58:32.459383 CH 1, Rank 1
9128 09:58:32.459456 SW Impedance : PASS
9129 09:58:32.462680 DUTY Scan : NO K
9130 09:58:32.462763 ZQ Calibration : PASS
9131 09:58:32.465920 Jitter Meter : NO K
9132 09:58:32.469659 CBT Training : PASS
9133 09:58:32.469755 Write leveling : PASS
9134 09:58:32.472904 RX DQS gating : PASS
9135 09:58:32.476085 RX DQ/DQS(RDDQC) : PASS
9136 09:58:32.476166 TX DQ/DQS : PASS
9137 09:58:32.479318 RX DATLAT : PASS
9138 09:58:32.482926 RX DQ/DQS(Engine): PASS
9139 09:58:32.483007 TX OE : PASS
9140 09:58:32.485872 All Pass.
9141 09:58:32.485971
9142 09:58:32.486070 DramC Write-DBI on
9143 09:58:32.489138 PER_BANK_REFRESH: Hybrid Mode
9144 09:58:32.489236 TX_TRACKING: ON
9145 09:58:32.499528 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9146 09:58:32.508909 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9147 09:58:32.515678 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9148 09:58:32.519200 [FAST_K] Save calibration result to emmc
9149 09:58:32.522108 sync common calibartion params.
9150 09:58:32.522190 sync cbt_mode0:1, 1:1
9151 09:58:32.525699 dram_init: ddr_geometry: 2
9152 09:58:32.529206 dram_init: ddr_geometry: 2
9153 09:58:32.532361 dram_init: ddr_geometry: 2
9154 09:58:32.532475 0:dram_rank_size:100000000
9155 09:58:32.535702 1:dram_rank_size:100000000
9156 09:58:32.542571 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9157 09:58:32.542653 DFS_SHUFFLE_HW_MODE: ON
9158 09:58:32.545805 dramc_set_vcore_voltage set vcore to 725000
9159 09:58:32.548860 Read voltage for 1600, 0
9160 09:58:32.548942 Vio18 = 0
9161 09:58:32.552025 Vcore = 725000
9162 09:58:32.552106 Vdram = 0
9163 09:58:32.552170 Vddq = 0
9164 09:58:32.555225 Vmddr = 0
9165 09:58:32.555306 switch to 3200 Mbps bootup
9166 09:58:32.558404 [DramcRunTimeConfig]
9167 09:58:32.558483 PHYPLL
9168 09:58:32.562150 DPM_CONTROL_AFTERK: ON
9169 09:58:32.562245 PER_BANK_REFRESH: ON
9170 09:58:32.565296 REFRESH_OVERHEAD_REDUCTION: ON
9171 09:58:32.568326 CMD_PICG_NEW_MODE: OFF
9172 09:58:32.568407 XRTWTW_NEW_MODE: ON
9173 09:58:32.571715 XRTRTR_NEW_MODE: ON
9174 09:58:32.571824 TX_TRACKING: ON
9175 09:58:32.574940 RDSEL_TRACKING: OFF
9176 09:58:32.578158 DQS Precalculation for DVFS: ON
9177 09:58:32.578260 RX_TRACKING: OFF
9178 09:58:32.581528 HW_GATING DBG: ON
9179 09:58:32.581643 ZQCS_ENABLE_LP4: ON
9180 09:58:32.585282 RX_PICG_NEW_MODE: ON
9181 09:58:32.585387 TX_PICG_NEW_MODE: ON
9182 09:58:32.588378 ENABLE_RX_DCM_DPHY: ON
9183 09:58:32.591523 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9184 09:58:32.595068 DUMMY_READ_FOR_TRACKING: OFF
9185 09:58:32.598155 !!! SPM_CONTROL_AFTERK: OFF
9186 09:58:32.598251 !!! SPM could not control APHY
9187 09:58:32.601939 IMPEDANCE_TRACKING: ON
9188 09:58:32.602015 TEMP_SENSOR: ON
9189 09:58:32.605114 HW_SAVE_FOR_SR: OFF
9190 09:58:32.608298 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9191 09:58:32.611355 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9192 09:58:32.614778 Read ODT Tracking: ON
9193 09:58:32.614882 Refresh Rate DeBounce: ON
9194 09:58:32.618116 DFS_NO_QUEUE_FLUSH: ON
9195 09:58:32.621928 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9196 09:58:32.625100 ENABLE_DFS_RUNTIME_MRW: OFF
9197 09:58:32.625209 DDR_RESERVE_NEW_MODE: ON
9198 09:58:32.628367 MR_CBT_SWITCH_FREQ: ON
9199 09:58:32.631131 =========================
9200 09:58:32.649164 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9201 09:58:32.652214 dram_init: ddr_geometry: 2
9202 09:58:32.671077 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9203 09:58:32.674116 dram_init: dram init end (result: 0)
9204 09:58:32.680496 DRAM-K: Full calibration passed in 24643 msecs
9205 09:58:32.683719 MRC: failed to locate region type 0.
9206 09:58:32.683824 DRAM rank0 size:0x100000000,
9207 09:58:32.686932 DRAM rank1 size=0x100000000
9208 09:58:32.696948 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9209 09:58:32.703721 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9210 09:58:32.710196 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9211 09:58:32.741626 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9212 09:58:32.741794 DRAM rank0 size:0x100000000,
9213 09:58:32.741900 DRAM rank1 size=0x100000000
9214 09:58:32.741974 CBMEM:
9215 09:58:32.742063 IMD: root @ 0xfffff000 254 entries.
9216 09:58:32.742161 IMD: root @ 0xffffec00 62 entries.
9217 09:58:32.742256 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9218 09:58:32.742347 WARNING: RO_VPD is uninitialized or empty.
9219 09:58:32.743173 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9220 09:58:32.750637 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9221 09:58:32.763483 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9222 09:58:32.774880 BS: romstage times (exec / console): total (unknown) / 24133 ms
9223 09:58:32.774973
9224 09:58:32.775052
9225 09:58:32.784982 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9226 09:58:32.788199 ARM64: Exception handlers installed.
9227 09:58:32.791376 ARM64: Testing exception
9228 09:58:32.794999 ARM64: Done test exception
9229 09:58:32.795075 Enumerating buses...
9230 09:58:32.798003 Show all devs... Before device enumeration.
9231 09:58:32.801097 Root Device: enabled 1
9232 09:58:32.804729 CPU_CLUSTER: 0: enabled 1
9233 09:58:32.804814 CPU: 00: enabled 1
9234 09:58:32.807853 Compare with tree...
9235 09:58:32.807933 Root Device: enabled 1
9236 09:58:32.811116 CPU_CLUSTER: 0: enabled 1
9237 09:58:32.814362 CPU: 00: enabled 1
9238 09:58:32.814474 Root Device scanning...
9239 09:58:32.818091 scan_static_bus for Root Device
9240 09:58:32.821328 CPU_CLUSTER: 0 enabled
9241 09:58:32.824354 scan_static_bus for Root Device done
9242 09:58:32.827697 scan_bus: bus Root Device finished in 8 msecs
9243 09:58:32.827811 done
9244 09:58:32.834633 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9245 09:58:32.837728 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9246 09:58:32.843906 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9247 09:58:32.850850 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9248 09:58:32.850985 Allocating resources...
9249 09:58:32.854302 Reading resources...
9250 09:58:32.857213 Root Device read_resources bus 0 link: 0
9251 09:58:32.860904 DRAM rank0 size:0x100000000,
9252 09:58:32.860989 DRAM rank1 size=0x100000000
9253 09:58:32.867276 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9254 09:58:32.867361 CPU: 00 missing read_resources
9255 09:58:32.874029 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9256 09:58:32.877427 Root Device read_resources bus 0 link: 0 done
9257 09:58:32.880687 Done reading resources.
9258 09:58:32.883574 Show resources in subtree (Root Device)...After reading.
9259 09:58:32.886884 Root Device child on link 0 CPU_CLUSTER: 0
9260 09:58:32.890666 CPU_CLUSTER: 0 child on link 0 CPU: 00
9261 09:58:32.900223 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9262 09:58:32.900314 CPU: 00
9263 09:58:32.906815 Root Device assign_resources, bus 0 link: 0
9264 09:58:32.909955 CPU_CLUSTER: 0 missing set_resources
9265 09:58:32.913193 Root Device assign_resources, bus 0 link: 0 done
9266 09:58:32.916882 Done setting resources.
9267 09:58:32.920089 Show resources in subtree (Root Device)...After assigning values.
9268 09:58:32.923261 Root Device child on link 0 CPU_CLUSTER: 0
9269 09:58:32.929610 CPU_CLUSTER: 0 child on link 0 CPU: 00
9270 09:58:32.936481 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9271 09:58:32.939606 CPU: 00
9272 09:58:32.939691 Done allocating resources.
9273 09:58:32.946075 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9274 09:58:32.946161 Enabling resources...
9275 09:58:32.949212 done.
9276 09:58:32.952801 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9277 09:58:32.956183 Initializing devices...
9278 09:58:32.956295 Root Device init
9279 09:58:32.959538 init hardware done!
9280 09:58:32.959624 0x00000018: ctrlr->caps
9281 09:58:32.962372 52.000 MHz: ctrlr->f_max
9282 09:58:32.965969 0.400 MHz: ctrlr->f_min
9283 09:58:32.969198 0x40ff8080: ctrlr->voltages
9284 09:58:32.969292 sclk: 390625
9285 09:58:32.969359 Bus Width = 1
9286 09:58:32.972389 sclk: 390625
9287 09:58:32.972475 Bus Width = 1
9288 09:58:32.976041 Early init status = 3
9289 09:58:32.978920 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9290 09:58:32.982504 in-header: 03 fc 00 00 01 00 00 00
9291 09:58:32.985954 in-data: 00
9292 09:58:32.989258 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9293 09:58:32.994426 in-header: 03 fd 00 00 00 00 00 00
9294 09:58:32.997591 in-data:
9295 09:58:33.000362 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9296 09:58:33.004231 in-header: 03 fc 00 00 01 00 00 00
9297 09:58:33.007398 in-data: 00
9298 09:58:33.010481 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9299 09:58:33.016012 in-header: 03 fd 00 00 00 00 00 00
9300 09:58:33.019181 in-data:
9301 09:58:33.022485 [SSUSB] Setting up USB HOST controller...
9302 09:58:33.025766 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9303 09:58:33.029539 [SSUSB] phy power-on done.
9304 09:58:33.032824 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9305 09:58:33.039251 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9306 09:58:33.042521 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9307 09:58:33.049343 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9308 09:58:33.055653 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9309 09:58:33.061965 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9310 09:58:33.068725 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9311 09:58:33.075291 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9312 09:58:33.078962 SPM: binary array size = 0x9dc
9313 09:58:33.082164 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9314 09:58:33.088486 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9315 09:58:33.095337 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9316 09:58:33.101636 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9317 09:58:33.104967 configure_display: Starting display init
9318 09:58:33.139602 anx7625_power_on_init: Init interface.
9319 09:58:33.142567 anx7625_disable_pd_protocol: Disabled PD feature.
9320 09:58:33.145862 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9321 09:58:33.173629 anx7625_start_dp_work: Secure OCM version=00
9322 09:58:33.176760 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9323 09:58:33.192029 sp_tx_get_edid_block: EDID Block = 1
9324 09:58:33.294575 Extracted contents:
9325 09:58:33.297931 header: 00 ff ff ff ff ff ff 00
9326 09:58:33.301097 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9327 09:58:33.304124 version: 01 04
9328 09:58:33.307302 basic params: 95 1f 11 78 0a
9329 09:58:33.311088 chroma info: 76 90 94 55 54 90 27 21 50 54
9330 09:58:33.314310 established: 00 00 00
9331 09:58:33.320552 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9332 09:58:33.324248 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9333 09:58:33.330576 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9334 09:58:33.337324 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9335 09:58:33.344040 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9336 09:58:33.347230 extensions: 00
9337 09:58:33.347335 checksum: fb
9338 09:58:33.347427
9339 09:58:33.350448 Manufacturer: IVO Model 57d Serial Number 0
9340 09:58:33.353661 Made week 0 of 2020
9341 09:58:33.356883 EDID version: 1.4
9342 09:58:33.357009 Digital display
9343 09:58:33.360583 6 bits per primary color channel
9344 09:58:33.360687 DisplayPort interface
9345 09:58:33.363592 Maximum image size: 31 cm x 17 cm
9346 09:58:33.366785 Gamma: 220%
9347 09:58:33.366873 Check DPMS levels
9348 09:58:33.370056 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9349 09:58:33.376541 First detailed timing is preferred timing
9350 09:58:33.376664 Established timings supported:
9351 09:58:33.380149 Standard timings supported:
9352 09:58:33.383352 Detailed timings
9353 09:58:33.386576 Hex of detail: 383680a07038204018303c0035ae10000019
9354 09:58:33.393151 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9355 09:58:33.396868 0780 0798 07c8 0820 hborder 0
9356 09:58:33.399988 0438 043b 0447 0458 vborder 0
9357 09:58:33.403302 -hsync -vsync
9358 09:58:33.403415 Did detailed timing
9359 09:58:33.410119 Hex of detail: 000000000000000000000000000000000000
9360 09:58:33.413345 Manufacturer-specified data, tag 0
9361 09:58:33.416452 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9362 09:58:33.419520 ASCII string: InfoVision
9363 09:58:33.423167 Hex of detail: 000000fe00523134304e574635205248200a
9364 09:58:33.426404 ASCII string: R140NWF5 RH
9365 09:58:33.426493 Checksum
9366 09:58:33.429646 Checksum: 0xfb (valid)
9367 09:58:33.432847 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9368 09:58:33.435949 DSI data_rate: 832800000 bps
9369 09:58:33.442870 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9370 09:58:33.445935 anx7625_parse_edid: pixelclock(138800).
9371 09:58:33.449768 hactive(1920), hsync(48), hfp(24), hbp(88)
9372 09:58:33.452769 vactive(1080), vsync(12), vfp(3), vbp(17)
9373 09:58:33.455736 anx7625_dsi_config: config dsi.
9374 09:58:33.462470 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9375 09:58:33.476101 anx7625_dsi_config: success to config DSI
9376 09:58:33.479309 anx7625_dp_start: MIPI phy setup OK.
9377 09:58:33.483283 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9378 09:58:33.486205 mtk_ddp_mode_set invalid vrefresh 60
9379 09:58:33.489579 main_disp_path_setup
9380 09:58:33.489710 ovl_layer_smi_id_en
9381 09:58:33.492659 ovl_layer_smi_id_en
9382 09:58:33.492770 ccorr_config
9383 09:58:33.492863 aal_config
9384 09:58:33.495949 gamma_config
9385 09:58:33.496031 postmask_config
9386 09:58:33.499565 dither_config
9387 09:58:33.502840 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9388 09:58:33.509619 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9389 09:58:33.512506 Root Device init finished in 552 msecs
9390 09:58:33.515913 CPU_CLUSTER: 0 init
9391 09:58:33.522432 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9392 09:58:33.529108 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9393 09:58:33.529197 APU_MBOX 0x190000b0 = 0x10001
9394 09:58:33.532269 APU_MBOX 0x190001b0 = 0x10001
9395 09:58:33.535527 APU_MBOX 0x190005b0 = 0x10001
9396 09:58:33.538710 APU_MBOX 0x190006b0 = 0x10001
9397 09:58:33.545031 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9398 09:58:33.555310 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9399 09:58:33.567684 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9400 09:58:33.574259 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9401 09:58:33.586115 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9402 09:58:33.594829 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9403 09:58:33.598534 CPU_CLUSTER: 0 init finished in 81 msecs
9404 09:58:33.601885 Devices initialized
9405 09:58:33.604921 Show all devs... After init.
9406 09:58:33.605006 Root Device: enabled 1
9407 09:58:33.608104 CPU_CLUSTER: 0: enabled 1
9408 09:58:33.611555 CPU: 00: enabled 1
9409 09:58:33.614639 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9410 09:58:33.617943 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9411 09:58:33.621340 ELOG: NV offset 0x57f000 size 0x1000
9412 09:58:33.627799 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9413 09:58:33.635105 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9414 09:58:33.638279 ELOG: Event(17) added with size 13 at 2023-11-24 09:58:35 UTC
9415 09:58:33.644611 out: cmd=0x121: 03 db 21 01 00 00 00 00
9416 09:58:33.647825 in-header: 03 b6 00 00 2c 00 00 00
9417 09:58:33.660958 in-data: a9 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9418 09:58:33.664304 ELOG: Event(A1) added with size 10 at 2023-11-24 09:58:35 UTC
9419 09:58:33.674522 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9420 09:58:33.677727 ELOG: Event(A0) added with size 9 at 2023-11-24 09:58:35 UTC
9421 09:58:33.680926 elog_add_boot_reason: Logged dev mode boot
9422 09:58:33.687905 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9423 09:58:33.687990 Finalize devices...
9424 09:58:33.691269 Devices finalized
9425 09:58:33.697374 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9426 09:58:33.700801 Writing coreboot table at 0xffe64000
9427 09:58:33.704081 0. 000000000010a000-0000000000113fff: RAMSTAGE
9428 09:58:33.707437 1. 0000000040000000-00000000400fffff: RAM
9429 09:58:33.710506 2. 0000000040100000-000000004032afff: RAMSTAGE
9430 09:58:33.713746 3. 000000004032b000-00000000545fffff: RAM
9431 09:58:33.720138 4. 0000000054600000-000000005465ffff: BL31
9432 09:58:33.723911 5. 0000000054660000-00000000ffe63fff: RAM
9433 09:58:33.727093 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9434 09:58:33.730276 7. 0000000100000000-000000023fffffff: RAM
9435 09:58:33.734009 Passing 5 GPIOs to payload:
9436 09:58:33.740285 NAME | PORT | POLARITY | VALUE
9437 09:58:33.743954 EC in RW | 0x000000aa | low | undefined
9438 09:58:33.747237 EC interrupt | 0x00000005 | low | undefined
9439 09:58:33.753552 TPM interrupt | 0x000000ab | high | undefined
9440 09:58:33.757095 SD card detect | 0x00000011 | high | undefined
9441 09:58:33.763671 speaker enable | 0x00000093 | high | undefined
9442 09:58:33.766892 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9443 09:58:33.770072 in-header: 03 f9 00 00 02 00 00 00
9444 09:58:33.770154 in-data: 02 00
9445 09:58:33.773167 ADC[4]: Raw value=901922 ID=7
9446 09:58:33.776280 ADC[3]: Raw value=213652 ID=1
9447 09:58:33.780016 RAM Code: 0x71
9448 09:58:33.780093 ADC[6]: Raw value=75036 ID=0
9449 09:58:33.783393 ADC[5]: Raw value=213652 ID=1
9450 09:58:33.786479 SKU Code: 0x1
9451 09:58:33.789644 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a1a9
9452 09:58:33.792734 coreboot table: 964 bytes.
9453 09:58:33.796584 IMD ROOT 0. 0xfffff000 0x00001000
9454 09:58:33.799604 IMD SMALL 1. 0xffffe000 0x00001000
9455 09:58:33.802903 RO MCACHE 2. 0xffffc000 0x00001104
9456 09:58:33.806578 CONSOLE 3. 0xfff7c000 0x00080000
9457 09:58:33.809690 FMAP 4. 0xfff7b000 0x00000452
9458 09:58:33.812657 TIME STAMP 5. 0xfff7a000 0x00000910
9459 09:58:33.816004 VBOOT WORK 6. 0xfff66000 0x00014000
9460 09:58:33.819102 RAMOOPS 7. 0xffe66000 0x00100000
9461 09:58:33.823149 COREBOOT 8. 0xffe64000 0x00002000
9462 09:58:33.823232 IMD small region:
9463 09:58:33.826124 IMD ROOT 0. 0xffffec00 0x00000400
9464 09:58:33.829174 VPD 1. 0xffffeb80 0x0000006c
9465 09:58:33.836016 MMC STATUS 2. 0xffffeb60 0x00000004
9466 09:58:33.839138 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9467 09:58:33.842770 Probing TPM: done!
9468 09:58:33.845784 Connected to device vid:did:rid of 1ae0:0028:00
9469 09:58:33.856073 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9470 09:58:33.859061 Initialized TPM device CR50 revision 0
9471 09:58:33.862919 Checking cr50 for pending updates
9472 09:58:33.866589 Reading cr50 TPM mode
9473 09:58:33.875562 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9474 09:58:33.881996 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9475 09:58:33.921858 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9476 09:58:33.925630 Checking segment from ROM address 0x40100000
9477 09:58:33.928500 Checking segment from ROM address 0x4010001c
9478 09:58:33.935190 Loading segment from ROM address 0x40100000
9479 09:58:33.935273 code (compression=0)
9480 09:58:33.945185 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9481 09:58:33.951842 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9482 09:58:33.951957 it's not compressed!
9483 09:58:33.958458 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9484 09:58:33.964934 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9485 09:58:33.982627 Loading segment from ROM address 0x4010001c
9486 09:58:33.982720 Entry Point 0x80000000
9487 09:58:33.985763 Loaded segments
9488 09:58:33.988957 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9489 09:58:33.996022 Jumping to boot code at 0x80000000(0xffe64000)
9490 09:58:34.002151 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9491 09:58:34.008958 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9492 09:58:34.016552 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9493 09:58:34.020522 Checking segment from ROM address 0x40100000
9494 09:58:34.023647 Checking segment from ROM address 0x4010001c
9495 09:58:34.030254 Loading segment from ROM address 0x40100000
9496 09:58:34.030396 code (compression=1)
9497 09:58:34.036459 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9498 09:58:34.046900 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9499 09:58:34.046985 using LZMA
9500 09:58:34.055137 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9501 09:58:34.061819 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9502 09:58:34.064899 Loading segment from ROM address 0x4010001c
9503 09:58:34.068372 Entry Point 0x54601000
9504 09:58:34.068458 Loaded segments
9505 09:58:34.071910 NOTICE: MT8192 bl31_setup
9506 09:58:34.079137 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9507 09:58:34.082463 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9508 09:58:34.085377 WARNING: region 0:
9509 09:58:34.089334 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9510 09:58:34.089426 WARNING: region 1:
9511 09:58:34.095707 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9512 09:58:34.098933 WARNING: region 2:
9513 09:58:34.101932 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9514 09:58:34.105233 WARNING: region 3:
9515 09:58:34.108965 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9516 09:58:34.112181 WARNING: region 4:
9517 09:58:34.118557 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9518 09:58:34.118667 WARNING: region 5:
9519 09:58:34.122468 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9520 09:58:34.125661 WARNING: region 6:
9521 09:58:34.128871 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9522 09:58:34.132006 WARNING: region 7:
9523 09:58:34.135169 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9524 09:58:34.142233 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9525 09:58:34.145505 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9526 09:58:34.148405 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9527 09:58:34.155786 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9528 09:58:34.158870 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9529 09:58:34.161825 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9530 09:58:34.168760 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9531 09:58:34.171919 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9532 09:58:34.178285 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9533 09:58:34.181652 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9534 09:58:34.184825 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9535 09:58:34.191788 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9536 09:58:34.194882 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9537 09:58:34.198575 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9538 09:58:34.204924 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9539 09:58:34.208246 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9540 09:58:34.214996 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9541 09:58:34.218190 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9542 09:58:34.221610 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9543 09:58:34.228173 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9544 09:58:34.231188 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9545 09:58:34.238241 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9546 09:58:34.241336 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9547 09:58:34.244591 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9548 09:58:34.251717 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9549 09:58:34.254850 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9550 09:58:34.261269 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9551 09:58:34.265093 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9552 09:58:34.267839 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9553 09:58:34.274647 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9554 09:58:34.277731 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9555 09:58:34.284418 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9556 09:58:34.288314 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9557 09:58:34.291079 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9558 09:58:34.294657 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9559 09:58:34.301349 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9560 09:58:34.304196 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9561 09:58:34.307523 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9562 09:58:34.311220 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9563 09:58:34.318273 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9564 09:58:34.321181 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9565 09:58:34.324328 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9566 09:58:34.328057 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9567 09:58:34.334437 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9568 09:58:34.337870 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9569 09:58:34.341556 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9570 09:58:34.344293 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9571 09:58:34.351291 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9572 09:58:34.354520 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9573 09:58:34.360680 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9574 09:58:34.364554 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9575 09:58:34.367623 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9576 09:58:34.374057 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9577 09:58:34.377779 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9578 09:58:34.384544 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9579 09:58:34.387662 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9580 09:58:34.390753 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9581 09:58:34.397716 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9582 09:58:34.400768 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9583 09:58:34.407601 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9584 09:58:34.410671 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9585 09:58:34.417531 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9586 09:58:34.420917 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9587 09:58:34.427126 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9588 09:58:34.430335 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9589 09:58:34.437371 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9590 09:58:34.440587 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9591 09:58:34.443810 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9592 09:58:34.450323 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9593 09:58:34.453898 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9594 09:58:34.460364 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9595 09:58:34.463451 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9596 09:58:34.469914 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9597 09:58:34.473307 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9598 09:58:34.479704 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9599 09:58:34.483701 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9600 09:58:34.486864 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9601 09:58:34.493637 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9602 09:58:34.496736 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9603 09:58:34.503672 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9604 09:58:34.506758 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9605 09:58:34.513691 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9606 09:58:34.516934 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9607 09:58:34.519999 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9608 09:58:34.526467 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9609 09:58:34.530010 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9610 09:58:34.536625 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9611 09:58:34.540488 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9612 09:58:34.546813 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9613 09:58:34.550488 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9614 09:58:34.553645 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9615 09:58:34.560058 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9616 09:58:34.563288 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9617 09:58:34.570122 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9618 09:58:34.573523 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9619 09:58:34.579992 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9620 09:58:34.583151 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9621 09:58:34.586244 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9622 09:58:34.590019 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9623 09:58:34.596218 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9624 09:58:34.599870 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9625 09:58:34.602946 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9626 09:58:34.609912 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9627 09:58:34.613055 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9628 09:58:34.619361 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9629 09:58:34.623085 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9630 09:58:34.626180 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9631 09:58:34.633067 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9632 09:58:34.636221 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9633 09:58:34.642925 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9634 09:58:34.645708 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9635 09:58:34.649095 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9636 09:58:34.656248 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9637 09:58:34.659455 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9638 09:58:34.665680 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9639 09:58:34.669564 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9640 09:58:34.672610 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9641 09:58:34.678971 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9642 09:58:34.682696 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9643 09:58:34.685874 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9644 09:58:34.689523 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9645 09:58:34.695563 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9646 09:58:34.699344 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9647 09:58:34.702488 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9648 09:58:34.708819 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9649 09:58:34.712623 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9650 09:58:34.715667 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9651 09:58:34.722306 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9652 09:58:34.725540 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9653 09:58:34.732061 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9654 09:58:34.735104 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9655 09:58:34.739057 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9656 09:58:34.745404 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9657 09:58:34.748541 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9658 09:58:34.755542 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9659 09:58:34.758472 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9660 09:58:34.761833 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9661 09:58:34.768498 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9662 09:58:34.771686 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9663 09:58:34.778469 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9664 09:58:34.781736 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9665 09:58:34.784911 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9666 09:58:34.791887 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9667 09:58:34.794966 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9668 09:58:34.798710 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9669 09:58:34.804809 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9670 09:58:34.808423 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9671 09:58:34.815133 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9672 09:58:34.818390 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9673 09:58:34.824649 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9674 09:58:34.827893 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9675 09:58:34.831612 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9676 09:58:34.837984 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9677 09:58:34.841577 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9678 09:58:34.844906 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9679 09:58:34.850991 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9680 09:58:34.854790 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9681 09:58:34.861443 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9682 09:58:34.864719 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9683 09:58:34.867862 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9684 09:58:34.874177 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9685 09:58:34.877653 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9686 09:58:34.884519 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9687 09:58:34.887685 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9688 09:58:34.894281 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9689 09:58:34.897363 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9690 09:58:34.901011 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9691 09:58:34.907651 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9692 09:58:34.910546 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9693 09:58:34.914048 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9694 09:58:34.920736 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9695 09:58:34.924002 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9696 09:58:34.930335 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9697 09:58:34.933706 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9698 09:58:34.936809 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9699 09:58:34.943733 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9700 09:58:34.946837 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9701 09:58:34.953598 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9702 09:58:34.956594 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9703 09:58:34.959839 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9704 09:58:34.966637 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9705 09:58:34.969658 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9706 09:58:34.976783 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9707 09:58:34.979745 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9708 09:58:34.986358 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9709 09:58:34.989859 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9710 09:58:34.992827 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9711 09:58:34.999273 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9712 09:58:35.003196 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9713 09:58:35.009431 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9714 09:58:35.012561 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9715 09:58:35.016125 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9716 09:58:35.022490 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9717 09:58:35.025877 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9718 09:58:35.032073 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9719 09:58:35.035835 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9720 09:58:35.042227 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9721 09:58:35.045375 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9722 09:58:35.049050 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9723 09:58:35.055275 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9724 09:58:35.059075 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9725 09:58:35.065587 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9726 09:58:35.068570 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9727 09:58:35.075580 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9728 09:58:35.078911 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9729 09:58:35.082104 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9730 09:58:35.088348 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9731 09:58:35.092029 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9732 09:58:35.098092 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9733 09:58:35.101649 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9734 09:58:35.108531 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9735 09:58:35.111256 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9736 09:58:35.115168 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9737 09:58:35.121532 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9738 09:58:35.124493 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9739 09:58:35.130998 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9740 09:58:35.134737 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9741 09:58:35.140724 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9742 09:58:35.144471 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9743 09:58:35.150834 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9744 09:58:35.154437 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9745 09:58:35.157208 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9746 09:58:35.163834 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9747 09:58:35.166925 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9748 09:58:35.173929 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9749 09:58:35.177089 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9750 09:58:35.180838 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9751 09:58:35.187203 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9752 09:58:35.190282 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9753 09:58:35.196776 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9754 09:58:35.200447 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9755 09:58:35.203581 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9756 09:58:35.206619 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9757 09:58:35.209977 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9758 09:58:35.216602 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9759 09:58:35.219789 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9760 09:58:35.226904 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9761 09:58:35.230185 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9762 09:58:35.233352 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9763 09:58:35.239735 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9764 09:58:35.242898 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9765 09:58:35.249794 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9766 09:58:35.253318 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9767 09:58:35.256617 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9768 09:58:35.262734 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9769 09:58:35.266639 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9770 09:58:35.269416 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9771 09:58:35.276352 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9772 09:58:35.279373 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9773 09:58:35.282568 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9774 09:58:35.289487 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9775 09:58:35.292731 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9776 09:58:35.299208 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9777 09:58:35.302487 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9778 09:58:35.305586 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9779 09:58:35.312768 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9780 09:58:35.315681 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9781 09:58:35.322285 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9782 09:58:35.325538 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9783 09:58:35.328879 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9784 09:58:35.335770 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9785 09:58:35.338801 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9786 09:58:35.341851 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9787 09:58:35.348404 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9788 09:58:35.352151 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9789 09:58:35.355524 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9790 09:58:35.361941 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9791 09:58:35.365550 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9792 09:58:35.368370 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9793 09:58:35.375000 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9794 09:58:35.378325 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9795 09:58:35.382101 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9796 09:58:35.385274 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9797 09:58:35.388360 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9798 09:58:35.394899 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9799 09:58:35.398176 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9800 09:58:35.401971 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9801 09:58:35.408285 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9802 09:58:35.411486 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9803 09:58:35.414678 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9804 09:58:35.421344 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9805 09:58:35.424241 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9806 09:58:35.427934 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9807 09:58:35.434237 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9808 09:58:35.438131 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9809 09:58:35.444504 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9810 09:58:35.447750 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9811 09:58:35.450712 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9812 09:58:35.457567 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9813 09:58:35.461069 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9814 09:58:35.467499 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9815 09:58:35.470863 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9816 09:58:35.474226 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9817 09:58:35.480768 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9818 09:58:35.483776 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9819 09:58:35.490757 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9820 09:58:35.494114 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9821 09:58:35.500419 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9822 09:58:35.503978 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9823 09:58:35.507119 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9824 09:58:35.513594 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9825 09:58:35.516818 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9826 09:58:35.523236 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9827 09:58:35.527055 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9828 09:58:35.533178 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9829 09:58:35.536834 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9830 09:58:35.539925 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9831 09:58:35.546368 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9832 09:58:35.549728 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9833 09:58:35.556182 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9834 09:58:35.560056 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9835 09:58:35.563006 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9836 09:58:35.569811 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9837 09:58:35.573241 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9838 09:58:35.579617 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9839 09:58:35.582468 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9840 09:58:35.589806 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9841 09:58:35.592557 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9842 09:58:35.595881 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9843 09:58:35.602853 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9844 09:58:35.605940 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9845 09:58:35.612370 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9846 09:58:35.616305 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9847 09:58:35.619499 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9848 09:58:35.625892 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9849 09:58:35.628891 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9850 09:58:35.635471 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9851 09:58:35.639108 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9852 09:58:35.645360 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9853 09:58:35.649151 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9854 09:58:35.652485 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9855 09:58:35.658765 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9856 09:58:35.662076 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9857 09:58:35.668902 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9858 09:58:35.671942 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9859 09:58:35.675168 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9860 09:58:35.681935 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9861 09:58:35.685151 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9862 09:58:35.692059 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9863 09:58:35.695004 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9864 09:58:35.698476 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9865 09:58:35.705418 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9866 09:58:35.708558 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9867 09:58:35.715319 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9868 09:58:35.718309 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9869 09:58:35.721999 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9870 09:58:35.728411 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9871 09:58:35.731660 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9872 09:58:35.738055 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9873 09:58:35.741730 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9874 09:58:35.748366 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9875 09:58:35.751517 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9876 09:58:35.757899 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9877 09:58:35.761231 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9878 09:58:35.764788 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9879 09:58:35.771145 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9880 09:58:35.774573 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9881 09:58:35.780685 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9882 09:58:35.784269 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9883 09:58:35.791244 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9884 09:58:35.794242 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9885 09:58:35.797506 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9886 09:58:35.803720 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9887 09:58:35.807557 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9888 09:58:35.814307 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9889 09:58:35.817225 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9890 09:58:35.823608 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9891 09:58:35.827172 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9892 09:58:35.834019 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9893 09:58:35.837123 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9894 09:58:35.840277 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9895 09:58:35.846795 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9896 09:58:35.849932 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9897 09:58:35.856620 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9898 09:58:35.859847 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9899 09:58:35.866724 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9900 09:58:35.869886 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9901 09:58:35.873027 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9902 09:58:35.879404 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9903 09:58:35.882801 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9904 09:58:35.889511 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9905 09:58:35.893078 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9906 09:58:35.899402 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9907 09:58:35.902753 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9908 09:58:35.909587 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9909 09:58:35.912228 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9910 09:58:35.919439 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9911 09:58:35.922436 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9912 09:58:35.925580 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9913 09:58:35.932190 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9914 09:58:35.935694 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9915 09:58:35.942600 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9916 09:58:35.945418 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9917 09:58:35.952169 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9918 09:58:35.955319 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9919 09:58:35.962274 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9920 09:58:35.965227 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9921 09:58:35.968516 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9922 09:58:35.975274 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9923 09:58:35.978685 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9924 09:58:35.984860 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9925 09:58:35.988552 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9926 09:58:35.995083 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9927 09:58:35.998075 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9928 09:58:36.001674 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9929 09:58:36.007873 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9930 09:58:36.011595 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9931 09:58:36.017734 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9932 09:58:36.021476 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9933 09:58:36.027697 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9934 09:58:36.030858 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9935 09:58:36.037927 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9936 09:58:36.040934 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9937 09:58:36.048032 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9938 09:58:36.050971 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9939 09:58:36.057503 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9940 09:58:36.060654 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9941 09:58:36.067376 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9942 09:58:36.071084 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9943 09:58:36.077356 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9944 09:58:36.080593 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9945 09:58:36.087449 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9946 09:58:36.090581 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9947 09:58:36.097656 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9948 09:58:36.100848 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9949 09:58:36.107110 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9950 09:58:36.110578 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9951 09:58:36.116973 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9952 09:58:36.120664 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9953 09:58:36.127296 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9954 09:58:36.130260 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9955 09:58:36.136965 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9956 09:58:36.140205 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9957 09:58:36.146411 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9958 09:58:36.150232 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9959 09:58:36.153129 INFO: [APUAPC] vio 0
9960 09:58:36.156602 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9961 09:58:36.163000 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9962 09:58:36.166219 INFO: [APUAPC] D0_APC_0: 0x400510
9963 09:58:36.169711 INFO: [APUAPC] D0_APC_1: 0x0
9964 09:58:36.173229 INFO: [APUAPC] D0_APC_2: 0x1540
9965 09:58:36.173314 INFO: [APUAPC] D0_APC_3: 0x0
9966 09:58:36.179739 INFO: [APUAPC] D1_APC_0: 0xffffffff
9967 09:58:36.182946 INFO: [APUAPC] D1_APC_1: 0xffffffff
9968 09:58:36.185933 INFO: [APUAPC] D1_APC_2: 0x3fffff
9969 09:58:36.186012 INFO: [APUAPC] D1_APC_3: 0x0
9970 09:58:36.189642 INFO: [APUAPC] D2_APC_0: 0xffffffff
9971 09:58:36.192753 INFO: [APUAPC] D2_APC_1: 0xffffffff
9972 09:58:36.196076 INFO: [APUAPC] D2_APC_2: 0x3fffff
9973 09:58:36.199281 INFO: [APUAPC] D2_APC_3: 0x0
9974 09:58:36.202518 INFO: [APUAPC] D3_APC_0: 0xffffffff
9975 09:58:36.205746 INFO: [APUAPC] D3_APC_1: 0xffffffff
9976 09:58:36.209640 INFO: [APUAPC] D3_APC_2: 0x3fffff
9977 09:58:36.212752 INFO: [APUAPC] D3_APC_3: 0x0
9978 09:58:36.215739 INFO: [APUAPC] D4_APC_0: 0xffffffff
9979 09:58:36.219236 INFO: [APUAPC] D4_APC_1: 0xffffffff
9980 09:58:36.222273 INFO: [APUAPC] D4_APC_2: 0x3fffff
9981 09:58:36.226037 INFO: [APUAPC] D4_APC_3: 0x0
9982 09:58:36.228925 INFO: [APUAPC] D5_APC_0: 0xffffffff
9983 09:58:36.232162 INFO: [APUAPC] D5_APC_1: 0xffffffff
9984 09:58:36.235405 INFO: [APUAPC] D5_APC_2: 0x3fffff
9985 09:58:36.239124 INFO: [APUAPC] D5_APC_3: 0x0
9986 09:58:36.242170 INFO: [APUAPC] D6_APC_0: 0xffffffff
9987 09:58:36.245376 INFO: [APUAPC] D6_APC_1: 0xffffffff
9988 09:58:36.248594 INFO: [APUAPC] D6_APC_2: 0x3fffff
9989 09:58:36.251755 INFO: [APUAPC] D6_APC_3: 0x0
9990 09:58:36.255009 INFO: [APUAPC] D7_APC_0: 0xffffffff
9991 09:58:36.258764 INFO: [APUAPC] D7_APC_1: 0xffffffff
9992 09:58:36.261608 INFO: [APUAPC] D7_APC_2: 0x3fffff
9993 09:58:36.265549 INFO: [APUAPC] D7_APC_3: 0x0
9994 09:58:36.268547 INFO: [APUAPC] D8_APC_0: 0xffffffff
9995 09:58:36.271720 INFO: [APUAPC] D8_APC_1: 0xffffffff
9996 09:58:36.274978 INFO: [APUAPC] D8_APC_2: 0x3fffff
9997 09:58:36.278562 INFO: [APUAPC] D8_APC_3: 0x0
9998 09:58:36.281768 INFO: [APUAPC] D9_APC_0: 0xffffffff
9999 09:58:36.284681 INFO: [APUAPC] D9_APC_1: 0xffffffff
10000 09:58:36.288132 INFO: [APUAPC] D9_APC_2: 0x3fffff
10001 09:58:36.291424 INFO: [APUAPC] D9_APC_3: 0x0
10002 09:58:36.294655 INFO: [APUAPC] D10_APC_0: 0xffffffff
10003 09:58:36.297871 INFO: [APUAPC] D10_APC_1: 0xffffffff
10004 09:58:36.301179 INFO: [APUAPC] D10_APC_2: 0x3fffff
10005 09:58:36.304933 INFO: [APUAPC] D10_APC_3: 0x0
10006 09:58:36.308184 INFO: [APUAPC] D11_APC_0: 0xffffffff
10007 09:58:36.311369 INFO: [APUAPC] D11_APC_1: 0xffffffff
10008 09:58:36.314502 INFO: [APUAPC] D11_APC_2: 0x3fffff
10009 09:58:36.317730 INFO: [APUAPC] D11_APC_3: 0x0
10010 09:58:36.321428 INFO: [APUAPC] D12_APC_0: 0xffffffff
10011 09:58:36.324334 INFO: [APUAPC] D12_APC_1: 0xffffffff
10012 09:58:36.327618 INFO: [APUAPC] D12_APC_2: 0x3fffff
10013 09:58:36.330696 INFO: [APUAPC] D12_APC_3: 0x0
10014 09:58:36.334410 INFO: [APUAPC] D13_APC_0: 0xffffffff
10015 09:58:36.337547 INFO: [APUAPC] D13_APC_1: 0xffffffff
10016 09:58:36.340990 INFO: [APUAPC] D13_APC_2: 0x3fffff
10017 09:58:36.343880 INFO: [APUAPC] D13_APC_3: 0x0
10018 09:58:36.347503 INFO: [APUAPC] D14_APC_0: 0xffffffff
10019 09:58:36.350665 INFO: [APUAPC] D14_APC_1: 0xffffffff
10020 09:58:36.353769 INFO: [APUAPC] D14_APC_2: 0x3fffff
10021 09:58:36.357044 INFO: [APUAPC] D14_APC_3: 0x0
10022 09:58:36.360194 INFO: [APUAPC] D15_APC_0: 0xffffffff
10023 09:58:36.363992 INFO: [APUAPC] D15_APC_1: 0xffffffff
10024 09:58:36.366939 INFO: [APUAPC] D15_APC_2: 0x3fffff
10025 09:58:36.370655 INFO: [APUAPC] D15_APC_3: 0x0
10026 09:58:36.373738 INFO: [APUAPC] APC_CON: 0x4
10027 09:58:36.376815 INFO: [NOCDAPC] D0_APC_0: 0x0
10028 09:58:36.380085 INFO: [NOCDAPC] D0_APC_1: 0x0
10029 09:58:36.383302 INFO: [NOCDAPC] D1_APC_0: 0x0
10030 09:58:36.386909 INFO: [NOCDAPC] D1_APC_1: 0xfff
10031 09:58:36.390267 INFO: [NOCDAPC] D2_APC_0: 0x0
10032 09:58:36.393472 INFO: [NOCDAPC] D2_APC_1: 0xfff
10033 09:58:36.396401 INFO: [NOCDAPC] D3_APC_0: 0x0
10034 09:58:36.400037 INFO: [NOCDAPC] D3_APC_1: 0xfff
10035 09:58:36.400129 INFO: [NOCDAPC] D4_APC_0: 0x0
10036 09:58:36.403735 INFO: [NOCDAPC] D4_APC_1: 0xfff
10037 09:58:36.406818 INFO: [NOCDAPC] D5_APC_0: 0x0
10038 09:58:36.410063 INFO: [NOCDAPC] D5_APC_1: 0xfff
10039 09:58:36.413220 INFO: [NOCDAPC] D6_APC_0: 0x0
10040 09:58:36.417033 INFO: [NOCDAPC] D6_APC_1: 0xfff
10041 09:58:36.420188 INFO: [NOCDAPC] D7_APC_0: 0x0
10042 09:58:36.423408 INFO: [NOCDAPC] D7_APC_1: 0xfff
10043 09:58:36.426555 INFO: [NOCDAPC] D8_APC_0: 0x0
10044 09:58:36.430286 INFO: [NOCDAPC] D8_APC_1: 0xfff
10045 09:58:36.430367 INFO: [NOCDAPC] D9_APC_0: 0x0
10046 09:58:36.433124 INFO: [NOCDAPC] D9_APC_1: 0xfff
10047 09:58:36.436662 INFO: [NOCDAPC] D10_APC_0: 0x0
10048 09:58:36.439655 INFO: [NOCDAPC] D10_APC_1: 0xfff
10049 09:58:36.443424 INFO: [NOCDAPC] D11_APC_0: 0x0
10050 09:58:36.446243 INFO: [NOCDAPC] D11_APC_1: 0xfff
10051 09:58:36.449772 INFO: [NOCDAPC] D12_APC_0: 0x0
10052 09:58:36.452709 INFO: [NOCDAPC] D12_APC_1: 0xfff
10053 09:58:36.456282 INFO: [NOCDAPC] D13_APC_0: 0x0
10054 09:58:36.459523 INFO: [NOCDAPC] D13_APC_1: 0xfff
10055 09:58:36.462898 INFO: [NOCDAPC] D14_APC_0: 0x0
10056 09:58:36.466338 INFO: [NOCDAPC] D14_APC_1: 0xfff
10057 09:58:36.469541 INFO: [NOCDAPC] D15_APC_0: 0x0
10058 09:58:36.472553 INFO: [NOCDAPC] D15_APC_1: 0xfff
10059 09:58:36.475696 INFO: [NOCDAPC] APC_CON: 0x4
10060 09:58:36.479308 INFO: [APUAPC] set_apusys_apc done
10061 09:58:36.482413 INFO: [DEVAPC] devapc_init done
10062 09:58:36.485535 INFO: GICv3 without legacy support detected.
10063 09:58:36.489258 INFO: ARM GICv3 driver initialized in EL3
10064 09:58:36.492361 INFO: Maximum SPI INTID supported: 639
10065 09:58:36.495865 INFO: BL31: Initializing runtime services
10066 09:58:36.502158 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10067 09:58:36.505824 INFO: SPM: enable CPC mode
10068 09:58:36.512440 INFO: mcdi ready for mcusys-off-idle and system suspend
10069 09:58:36.515590 INFO: BL31: Preparing for EL3 exit to normal world
10070 09:58:36.518689 INFO: Entry point address = 0x80000000
10071 09:58:36.521828 INFO: SPSR = 0x8
10072 09:58:36.526841
10073 09:58:36.526949
10074 09:58:36.527043
10075 09:58:36.530173 Starting depthcharge on Spherion...
10076 09:58:36.530255
10077 09:58:36.530320 Wipe memory regions:
10078 09:58:36.530381
10079 09:58:36.531040 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10080 09:58:36.531141 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10081 09:58:36.531224 Setting prompt string to ['asurada:']
10082 09:58:36.531302 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10083 09:58:36.533347 [0x00000040000000, 0x00000054600000)
10084 09:58:36.655604
10085 09:58:36.655739 [0x00000054660000, 0x00000080000000)
10086 09:58:36.915989
10087 09:58:36.916125 [0x000000821a7280, 0x000000ffe64000)
10088 09:58:37.661009
10089 09:58:37.661145 [0x00000100000000, 0x00000240000000)
10090 09:58:39.550969
10091 09:58:39.554145 Initializing XHCI USB controller at 0x11200000.
10092 09:58:40.535619
10093 09:58:40.535761 R8152: Initializing
10094 09:58:40.535830
10095 09:58:40.538981 Version 9 (ocp_data = 6010)
10096 09:58:40.539064
10097 09:58:40.542691 R8152: Done initializing
10098 09:58:40.542773
10099 09:58:40.542838 Adding net device
10100 09:58:41.065344
10101 09:58:41.068535 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10102 09:58:41.068624
10103 09:58:41.068689
10104 09:58:41.068770
10105 09:58:41.069099 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10107 09:58:41.169436 asurada: tftpboot 192.168.201.1 12073291/tftp-deploy-s0zgjjin/kernel/image.itb 12073291/tftp-deploy-s0zgjjin/kernel/cmdline
10108 09:58:41.169619 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10109 09:58:41.169739 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10110 09:58:41.174331 tftpboot 192.168.201.1 12073291/tftp-deploy-s0zgjjin/kernel/image.itp-deploy-s0zgjjin/kernel/cmdline
10111 09:58:41.174440
10112 09:58:41.174536 Waiting for link
10113 09:58:41.376538
10114 09:58:41.376697 done.
10115 09:58:41.376791
10116 09:58:41.376886 MAC: f4:f5:e8:50:de:0a
10117 09:58:41.376979
10118 09:58:41.379667 Sending DHCP discover... done.
10119 09:58:41.379766
10120 09:58:41.382930 Waiting for reply... done.
10121 09:58:41.383039
10122 09:58:41.386486 Sending DHCP request... done.
10123 09:58:41.386584
10124 09:58:41.390883 Waiting for reply... done.
10125 09:58:41.391004
10126 09:58:41.391097 My ip is 192.168.201.14
10127 09:58:41.391189
10128 09:58:41.394270 The DHCP server ip is 192.168.201.1
10129 09:58:41.394381
10130 09:58:41.400744 TFTP server IP predefined by user: 192.168.201.1
10131 09:58:41.400851
10132 09:58:41.407207 Bootfile predefined by user: 12073291/tftp-deploy-s0zgjjin/kernel/image.itb
10133 09:58:41.407291
10134 09:58:41.411062 Sending tftp read request... done.
10135 09:58:41.411149
10136 09:58:41.414701 Waiting for the transfer...
10137 09:58:41.414784
10138 09:58:41.649800 00000000 ################################################################
10139 09:58:41.649936
10140 09:58:41.882430 00080000 ################################################################
10141 09:58:41.882562
10142 09:58:42.118054 00100000 ################################################################
10143 09:58:42.118206
10144 09:58:42.351165 00180000 ################################################################
10145 09:58:42.351296
10146 09:58:42.589355 00200000 ################################################################
10147 09:58:42.589512
10148 09:58:42.826874 00280000 ################################################################
10149 09:58:42.827035
10150 09:58:43.062432 00300000 ################################################################
10151 09:58:43.062595
10152 09:58:43.295146 00380000 ################################################################
10153 09:58:43.295312
10154 09:58:43.530445 00400000 ################################################################
10155 09:58:43.530621
10156 09:58:43.769235 00480000 ################################################################
10157 09:58:43.769403
10158 09:58:43.997393 00500000 ################################################################
10159 09:58:43.997559
10160 09:58:44.226457 00580000 ################################################################
10161 09:58:44.226592
10162 09:58:44.459125 00600000 ################################################################
10163 09:58:44.459258
10164 09:58:44.695712 00680000 ################################################################
10165 09:58:44.695838
10166 09:58:44.931323 00700000 ################################################################
10167 09:58:44.931453
10168 09:58:45.166504 00780000 ################################################################
10169 09:58:45.166643
10170 09:58:45.400120 00800000 ################################################################
10171 09:58:45.400258
10172 09:58:45.634886 00880000 ################################################################
10173 09:58:45.635041
10174 09:58:45.871232 00900000 ################################################################
10175 09:58:45.871379
10176 09:58:46.107075 00980000 ################################################################
10177 09:58:46.107245
10178 09:58:46.341420 00a00000 ################################################################
10179 09:58:46.341585
10180 09:58:46.582036 00a80000 ################################################################
10181 09:58:46.582170
10182 09:58:46.824127 00b00000 ################################################################
10183 09:58:46.824300
10184 09:58:47.063083 00b80000 ################################################################
10185 09:58:47.063249
10186 09:58:47.298297 00c00000 ################################################################
10187 09:58:47.298428
10188 09:58:47.533365 00c80000 ################################################################
10189 09:58:47.533509
10190 09:58:47.760619 00d00000 ################################################################
10191 09:58:47.760766
10192 09:58:47.996036 00d80000 ################################################################
10193 09:58:47.996200
10194 09:58:48.224291 00e00000 ################################################################
10195 09:58:48.224438
10196 09:58:48.447690 00e80000 ################################################################
10197 09:58:48.447830
10198 09:58:48.671719 00f00000 ################################################################
10199 09:58:48.671872
10200 09:58:48.901962 00f80000 ################################################################
10201 09:58:48.902107
10202 09:58:49.127621 01000000 ################################################################
10203 09:58:49.127765
10204 09:58:49.351089 01080000 ################################################################
10205 09:58:49.351252
10206 09:58:49.574643 01100000 ################################################################
10207 09:58:49.574800
10208 09:58:49.803984 01180000 ################################################################
10209 09:58:49.804111
10210 09:58:50.031120 01200000 ################################################################
10211 09:58:50.031263
10212 09:58:50.253493 01280000 ################################################################
10213 09:58:50.253626
10214 09:58:50.482784 01300000 ################################################################
10215 09:58:50.482953
10216 09:58:50.710465 01380000 ################################################################
10217 09:58:50.710596
10218 09:58:50.951278 01400000 ################################################################
10219 09:58:50.951416
10220 09:58:51.191046 01480000 ################################################################
10221 09:58:51.191207
10222 09:58:51.419519 01500000 ################################################################
10223 09:58:51.419652
10224 09:58:51.654947 01580000 ################################################################
10225 09:58:51.655117
10226 09:58:51.904186 01600000 ################################################################
10227 09:58:51.904363
10228 09:58:52.125380 01680000 ################################################################
10229 09:58:52.125558
10230 09:58:52.350536 01700000 ################################################################
10231 09:58:52.350699
10232 09:58:52.574953 01780000 ################################################################
10233 09:58:52.575106
10234 09:58:52.811483 01800000 ################################################################
10235 09:58:52.811632
10236 09:58:53.040989 01880000 ################################################################
10237 09:58:53.041117
10238 09:58:53.264559 01900000 ################################################################
10239 09:58:53.264688
10240 09:58:53.491757 01980000 ################################################################
10241 09:58:53.491915
10242 09:58:53.725120 01a00000 ################################################################
10243 09:58:53.725257
10244 09:58:53.955916 01a80000 ################################################################
10245 09:58:53.956052
10246 09:58:54.186678 01b00000 ################################################################
10247 09:58:54.186809
10248 09:58:54.420701 01b80000 ################################################################
10249 09:58:54.420835
10250 09:58:54.647419 01c00000 ################################################################
10251 09:58:54.647549
10252 09:58:54.883668 01c80000 ################################################################
10253 09:58:54.883797
10254 09:58:55.112971 01d00000 ################################################################
10255 09:58:55.113125
10256 09:58:55.343389 01d80000 ################################################################
10257 09:58:55.343517
10258 09:58:55.570009 01e00000 ################################################################
10259 09:58:55.570139
10260 09:58:55.795928 01e80000 ################################################################
10261 09:58:55.796061
10262 09:58:56.026587 01f00000 ################################################################
10263 09:58:56.026750
10264 09:58:56.264005 01f80000 ################################################################
10265 09:58:56.264135
10266 09:58:56.516952 02000000 ################################################################
10267 09:58:56.517109
10268 09:58:56.778033 02080000 ################################################################
10269 09:58:56.778178
10270 09:58:57.017975 02100000 ################################################################
10271 09:58:57.018114
10272 09:58:57.258741 02180000 ################################################################
10273 09:58:57.258903
10274 09:58:57.515642 02200000 ################################################################
10275 09:58:57.515807
10276 09:58:57.754108 02280000 ################################################################
10277 09:58:57.754269
10278 09:58:57.992306 02300000 ################################################################
10279 09:58:57.992451
10280 09:58:58.232610 02380000 ################################################################
10281 09:58:58.232748
10282 09:58:58.474339 02400000 ################################################################
10283 09:58:58.474479
10284 09:58:58.708953 02480000 ################################################################
10285 09:58:58.709093
10286 09:58:58.937566 02500000 ################################################################
10287 09:58:58.937696
10288 09:58:59.162564 02580000 ################################################################
10289 09:58:59.162696
10290 09:58:59.391001 02600000 ################################################################
10291 09:58:59.391135
10292 09:58:59.621129 02680000 ################################################################
10293 09:58:59.621265
10294 09:58:59.849378 02700000 ################################################################
10295 09:58:59.849516
10296 09:59:00.101838 02780000 ################################################################
10297 09:59:00.101972
10298 09:59:00.365792 02800000 ################################################################
10299 09:59:00.365935
10300 09:59:00.628444 02880000 ################################################################
10301 09:59:00.628574
10302 09:59:00.874186 02900000 ################################################################
10303 09:59:00.874355
10304 09:59:01.107241 02980000 ################################################################
10305 09:59:01.107406
10306 09:59:01.335128 02a00000 ################################################################
10307 09:59:01.335261
10308 09:59:01.571716 02a80000 ################################################################
10309 09:59:01.571887
10310 09:59:01.846981 02b00000 ################################################################
10311 09:59:01.847135
10312 09:59:02.096471 02b80000 ################################################################
10313 09:59:02.096620
10314 09:59:02.353036 02c00000 ################################################################
10315 09:59:02.353177
10316 09:59:02.610141 02c80000 ################################################################
10317 09:59:02.610281
10318 09:59:02.855464 02d00000 ################################################################
10319 09:59:02.855608
10320 09:59:03.096194 02d80000 ################################################################
10321 09:59:03.096350
10322 09:59:03.327984 02e00000 ################################################################
10323 09:59:03.328124
10324 09:59:03.563308 02e80000 ################################################################
10325 09:59:03.563438
10326 09:59:03.796009 02f00000 ################################################################
10327 09:59:03.796147
10328 09:59:04.033342 02f80000 ################################################################
10329 09:59:04.033509
10330 09:59:04.093334 03000000 ################# done.
10331 09:59:04.093488
10332 09:59:04.096477 The bootfile was 50467686 bytes long.
10333 09:59:04.096560
10334 09:59:04.099805 Sending tftp read request... done.
10335 09:59:04.099944
10336 09:59:04.103297 Waiting for the transfer...
10337 09:59:04.103381
10338 09:59:04.106231 00000000 # done.
10339 09:59:04.106315
10340 09:59:04.112974 Command line loaded dynamically from TFTP file: 12073291/tftp-deploy-s0zgjjin/kernel/cmdline
10341 09:59:04.113057
10342 09:59:04.126264 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10343 09:59:04.126348
10344 09:59:04.126419 Loading FIT.
10345 09:59:04.129577
10346 09:59:04.129658 Image ramdisk-1 has 39370829 bytes.
10347 09:59:04.132690
10348 09:59:04.132796 Image fdt-1 has 47278 bytes.
10349 09:59:04.132930
10350 09:59:04.136160 Image kernel-1 has 11047542 bytes.
10351 09:59:04.136278
10352 09:59:04.146352 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10353 09:59:04.146491
10354 09:59:04.162417 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10355 09:59:04.162604
10356 09:59:04.169169 Choosing best match conf-1 for compat google,spherion-rev2.
10357 09:59:04.173352
10358 09:59:04.177090 Connected to device vid:did:rid of 1ae0:0028:00
10359 09:59:04.184420
10360 09:59:04.187698 tpm_get_response: command 0x17b, return code 0x0
10361 09:59:04.188008
10362 09:59:04.191006 ec_init: CrosEC protocol v3 supported (256, 248)
10363 09:59:04.194973
10364 09:59:04.198379 tpm_cleanup: add release locality here.
10365 09:59:04.198681
10366 09:59:04.198921 Shutting down all USB controllers.
10367 09:59:04.202004
10368 09:59:04.202301 Removing current net device
10369 09:59:04.202540
10370 09:59:04.208118 Exiting depthcharge with code 4 at timestamp: 57119619
10371 09:59:04.208420
10372 09:59:04.211853 LZMA decompressing kernel-1 to 0x821a6718
10373 09:59:04.212275
10374 09:59:04.215541 LZMA decompressing kernel-1 to 0x40000000
10375 09:59:05.604188
10376 09:59:05.604337 jumping to kernel
10377 09:59:05.605336 end: 2.2.4 bootloader-commands (duration 00:00:29) [common]
10378 09:59:05.605498 start: 2.2.5 auto-login-action (timeout 00:03:56) [common]
10379 09:59:05.605581 Setting prompt string to ['Linux version [0-9]']
10380 09:59:05.605651 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10381 09:59:05.605723 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10382 09:59:05.686259
10383 09:59:05.689529 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10384 09:59:05.693060 start: 2.2.5.1 login-action (timeout 00:03:56) [common]
10385 09:59:05.693178 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10386 09:59:05.693277 Setting prompt string to []
10387 09:59:05.693389 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10388 09:59:05.693520 Using line separator: #'\n'#
10389 09:59:05.693582 No login prompt set.
10390 09:59:05.693646 Parsing kernel messages
10391 09:59:05.693709 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10392 09:59:05.693811 [login-action] Waiting for messages, (timeout 00:03:56)
10393 09:59:05.712452 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j22848-arm64-gcc-10-defconfig-arm64-chromebook-6q8mw) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Nov 24 09:44:51 UTC 2023
10394 09:59:05.715739 [ 0.000000] random: crng init done
10395 09:59:05.722493 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10396 09:59:05.726261 [ 0.000000] efi: UEFI not found.
10397 09:59:05.732537 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10398 09:59:05.739096 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10399 09:59:05.748906 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10400 09:59:05.758980 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10401 09:59:05.765510 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10402 09:59:05.771654 [ 0.000000] printk: bootconsole [mtk8250] enabled
10403 09:59:05.778629 [ 0.000000] NUMA: No NUMA configuration found
10404 09:59:05.785209 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10405 09:59:05.788720 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10406 09:59:05.791461 [ 0.000000] Zone ranges:
10407 09:59:05.798095 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10408 09:59:05.801656 [ 0.000000] DMA32 empty
10409 09:59:05.808659 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10410 09:59:05.811566 [ 0.000000] Movable zone start for each node
10411 09:59:05.814975 [ 0.000000] Early memory node ranges
10412 09:59:05.821695 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10413 09:59:05.828658 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10414 09:59:05.834930 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10415 09:59:05.842438 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10416 09:59:05.848071 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10417 09:59:05.854626 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10418 09:59:05.911014 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10419 09:59:05.917686 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10420 09:59:05.924133 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10421 09:59:05.927683 [ 0.000000] psci: probing for conduit method from DT.
10422 09:59:05.933484 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10423 09:59:05.937213 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10424 09:59:05.943594 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10425 09:59:05.946799 [ 0.000000] psci: SMC Calling Convention v1.2
10426 09:59:05.953151 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10427 09:59:05.956437 [ 0.000000] Detected VIPT I-cache on CPU0
10428 09:59:05.962923 [ 0.000000] CPU features: detected: GIC system register CPU interface
10429 09:59:05.969559 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10430 09:59:05.976288 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10431 09:59:05.982647 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10432 09:59:05.992475 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10433 09:59:05.999181 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10434 09:59:06.002479 [ 0.000000] alternatives: applying boot alternatives
10435 09:59:06.009605 [ 0.000000] Fallback order for Node 0: 0
10436 09:59:06.016125 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10437 09:59:06.019440 [ 0.000000] Policy zone: Normal
10438 09:59:06.032973 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10439 09:59:06.042448 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10440 09:59:06.054329 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10441 09:59:06.064269 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10442 09:59:06.070877 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10443 09:59:06.074269 <6>[ 0.000000] software IO TLB: area num 8.
10444 09:59:06.130772 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10445 09:59:06.280110 <6>[ 0.000000] Memory: 7931172K/8385536K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 421596K reserved, 32768K cma-reserved)
10446 09:59:06.286712 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10447 09:59:06.293282 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10448 09:59:06.296508 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10449 09:59:06.303377 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10450 09:59:06.309373 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10451 09:59:06.312794 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10452 09:59:06.322599 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10453 09:59:06.329360 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10454 09:59:06.336150 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10455 09:59:06.342406 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10456 09:59:06.345865 <6>[ 0.000000] GICv3: 608 SPIs implemented
10457 09:59:06.349199 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10458 09:59:06.356234 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10459 09:59:06.359112 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10460 09:59:06.365756 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10461 09:59:06.378674 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10462 09:59:06.391935 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10463 09:59:06.398960 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10464 09:59:06.406707 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10465 09:59:06.419888 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10466 09:59:06.426550 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10467 09:59:06.433183 <6>[ 0.009179] Console: colour dummy device 80x25
10468 09:59:06.442928 <6>[ 0.013931] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10469 09:59:06.449636 <6>[ 0.024373] pid_max: default: 32768 minimum: 301
10470 09:59:06.453124 <6>[ 0.029238] LSM: Security Framework initializing
10471 09:59:06.459419 <6>[ 0.034176] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10472 09:59:06.469554 <6>[ 0.042037] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10473 09:59:06.479160 <6>[ 0.051445] cblist_init_generic: Setting adjustable number of callback queues.
10474 09:59:06.482266 <6>[ 0.058887] cblist_init_generic: Setting shift to 3 and lim to 1.
10475 09:59:06.492701 <6>[ 0.065266] cblist_init_generic: Setting adjustable number of callback queues.
10476 09:59:06.499036 <6>[ 0.072693] cblist_init_generic: Setting shift to 3 and lim to 1.
10477 09:59:06.501992 <6>[ 0.079092] rcu: Hierarchical SRCU implementation.
10478 09:59:06.508632 <6>[ 0.084138] rcu: Max phase no-delay instances is 1000.
10479 09:59:06.515262 <6>[ 0.091163] EFI services will not be available.
10480 09:59:06.518803 <6>[ 0.096105] smp: Bringing up secondary CPUs ...
10481 09:59:06.527530 <6>[ 0.101151] Detected VIPT I-cache on CPU1
10482 09:59:06.533933 <6>[ 0.101219] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10483 09:59:06.540746 <6>[ 0.101251] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10484 09:59:06.544103 <6>[ 0.101587] Detected VIPT I-cache on CPU2
10485 09:59:06.550649 <6>[ 0.101637] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10486 09:59:06.560475 <6>[ 0.101653] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10487 09:59:06.563687 <6>[ 0.101916] Detected VIPT I-cache on CPU3
10488 09:59:06.570208 <6>[ 0.101962] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10489 09:59:06.576677 <6>[ 0.101976] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10490 09:59:06.580017 <6>[ 0.102280] CPU features: detected: Spectre-v4
10491 09:59:06.587144 <6>[ 0.102287] CPU features: detected: Spectre-BHB
10492 09:59:06.590230 <6>[ 0.102292] Detected PIPT I-cache on CPU4
10493 09:59:06.596367 <6>[ 0.102347] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10494 09:59:06.603106 <6>[ 0.102364] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10495 09:59:06.609921 <6>[ 0.102657] Detected PIPT I-cache on CPU5
10496 09:59:06.616155 <6>[ 0.102720] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10497 09:59:06.622663 <6>[ 0.102736] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10498 09:59:06.626038 <6>[ 0.103016] Detected PIPT I-cache on CPU6
10499 09:59:06.632765 <6>[ 0.103080] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10500 09:59:06.642451 <6>[ 0.103096] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10501 09:59:06.645919 <6>[ 0.103392] Detected PIPT I-cache on CPU7
10502 09:59:06.653206 <6>[ 0.103458] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10503 09:59:06.659272 <6>[ 0.103474] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10504 09:59:06.662198 <6>[ 0.103521] smp: Brought up 1 node, 8 CPUs
10505 09:59:06.669296 <6>[ 0.244838] SMP: Total of 8 processors activated.
10506 09:59:06.675407 <6>[ 0.249789] CPU features: detected: 32-bit EL0 Support
10507 09:59:06.682154 <6>[ 0.255152] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10508 09:59:06.688804 <6>[ 0.263952] CPU features: detected: Common not Private translations
10509 09:59:06.695444 <6>[ 0.270427] CPU features: detected: CRC32 instructions
10510 09:59:06.702114 <6>[ 0.275779] CPU features: detected: RCpc load-acquire (LDAPR)
10511 09:59:06.705367 <6>[ 0.281739] CPU features: detected: LSE atomic instructions
10512 09:59:06.712127 <6>[ 0.287520] CPU features: detected: Privileged Access Never
10513 09:59:06.718678 <6>[ 0.293300] CPU features: detected: RAS Extension Support
10514 09:59:06.725192 <6>[ 0.298943] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10515 09:59:06.728269 <6>[ 0.306164] CPU: All CPU(s) started at EL2
10516 09:59:06.734859 <6>[ 0.310480] alternatives: applying system-wide alternatives
10517 09:59:06.744949 <6>[ 0.321186] devtmpfs: initialized
10518 09:59:06.760546 <6>[ 0.330088] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10519 09:59:06.766999 <6>[ 0.340052] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10520 09:59:06.773918 <6>[ 0.347772] pinctrl core: initialized pinctrl subsystem
10521 09:59:06.777472 <6>[ 0.354440] DMI not present or invalid.
10522 09:59:06.783520 <6>[ 0.358864] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10523 09:59:06.793535 <6>[ 0.365755] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10524 09:59:06.800216 <6>[ 0.373340] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10525 09:59:06.810546 <6>[ 0.381566] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10526 09:59:06.813803 <6>[ 0.389819] audit: initializing netlink subsys (disabled)
10527 09:59:06.823051 <5>[ 0.395516] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10528 09:59:06.830027 <6>[ 0.396238] thermal_sys: Registered thermal governor 'step_wise'
10529 09:59:06.836457 <6>[ 0.403484] thermal_sys: Registered thermal governor 'power_allocator'
10530 09:59:06.839696 <6>[ 0.409742] cpuidle: using governor menu
10531 09:59:06.846334 <6>[ 0.420701] NET: Registered PF_QIPCRTR protocol family
10532 09:59:06.852859 <6>[ 0.426212] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10533 09:59:06.859582 <6>[ 0.433317] ASID allocator initialised with 32768 entries
10534 09:59:06.862846 <6>[ 0.439896] Serial: AMBA PL011 UART driver
10535 09:59:06.872455 <4>[ 0.448723] Trying to register duplicate clock ID: 134
10536 09:59:06.926698 <6>[ 0.506388] KASLR enabled
10537 09:59:06.941248 <6>[ 0.514093] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10538 09:59:06.947549 <6>[ 0.521106] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10539 09:59:06.954155 <6>[ 0.527597] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10540 09:59:06.960851 <6>[ 0.534603] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10541 09:59:06.967544 <6>[ 0.541092] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10542 09:59:06.974356 <6>[ 0.548098] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10543 09:59:06.980620 <6>[ 0.554587] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10544 09:59:06.987403 <6>[ 0.561593] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10545 09:59:06.990736 <6>[ 0.569082] ACPI: Interpreter disabled.
10546 09:59:06.999196 <6>[ 0.575473] iommu: Default domain type: Translated
10547 09:59:07.005779 <6>[ 0.580585] iommu: DMA domain TLB invalidation policy: strict mode
10548 09:59:07.008923 <5>[ 0.587240] SCSI subsystem initialized
10549 09:59:07.015660 <6>[ 0.591404] usbcore: registered new interface driver usbfs
10550 09:59:07.022155 <6>[ 0.597132] usbcore: registered new interface driver hub
10551 09:59:07.025314 <6>[ 0.602683] usbcore: registered new device driver usb
10552 09:59:07.032982 <6>[ 0.608774] pps_core: LinuxPPS API ver. 1 registered
10553 09:59:07.042529 <6>[ 0.613968] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10554 09:59:07.046003 <6>[ 0.623316] PTP clock support registered
10555 09:59:07.048999 <6>[ 0.627556] EDAC MC: Ver: 3.0.0
10556 09:59:07.056331 <6>[ 0.632697] FPGA manager framework
10557 09:59:07.063240 <6>[ 0.636376] Advanced Linux Sound Architecture Driver Initialized.
10558 09:59:07.066539 <6>[ 0.643136] vgaarb: loaded
10559 09:59:07.072812 <6>[ 0.646306] clocksource: Switched to clocksource arch_sys_counter
10560 09:59:07.076044 <5>[ 0.652739] VFS: Disk quotas dquot_6.6.0
10561 09:59:07.083295 <6>[ 0.656924] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10562 09:59:07.086174 <6>[ 0.664110] pnp: PnP ACPI: disabled
10563 09:59:07.094494 <6>[ 0.670726] NET: Registered PF_INET protocol family
10564 09:59:07.104082 <6>[ 0.676312] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10565 09:59:07.115535 <6>[ 0.688612] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10566 09:59:07.125692 <6>[ 0.697428] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10567 09:59:07.132272 <6>[ 0.705400] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10568 09:59:07.141955 <6>[ 0.714101] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10569 09:59:07.148846 <6>[ 0.723847] TCP: Hash tables configured (established 65536 bind 65536)
10570 09:59:07.155136 <6>[ 0.730708] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10571 09:59:07.165324 <6>[ 0.737909] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10572 09:59:07.171576 <6>[ 0.745609] NET: Registered PF_UNIX/PF_LOCAL protocol family
10573 09:59:07.178320 <6>[ 0.751769] RPC: Registered named UNIX socket transport module.
10574 09:59:07.181520 <6>[ 0.757921] RPC: Registered udp transport module.
10575 09:59:07.188141 <6>[ 0.762854] RPC: Registered tcp transport module.
10576 09:59:07.194640 <6>[ 0.767784] RPC: Registered tcp NFSv4.1 backchannel transport module.
10577 09:59:07.197962 <6>[ 0.774454] PCI: CLS 0 bytes, default 64
10578 09:59:07.201628 <6>[ 0.778844] Unpacking initramfs...
10579 09:59:07.217842 <6>[ 0.790914] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10580 09:59:07.228214 <6>[ 0.799581] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10581 09:59:07.231640 <6>[ 0.808442] kvm [1]: IPA Size Limit: 40 bits
10582 09:59:07.237964 <6>[ 0.812974] kvm [1]: GICv3: no GICV resource entry
10583 09:59:07.241078 <6>[ 0.817995] kvm [1]: disabling GICv2 emulation
10584 09:59:07.247852 <6>[ 0.822683] kvm [1]: GIC system register CPU interface enabled
10585 09:59:07.254443 <6>[ 0.830375] kvm [1]: vgic interrupt IRQ18
10586 09:59:07.257315 <6>[ 0.834753] kvm [1]: VHE mode initialized successfully
10587 09:59:07.264773 <5>[ 0.841125] Initialise system trusted keyrings
10588 09:59:07.271562 <6>[ 0.845923] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10589 09:59:07.279720 <6>[ 0.855875] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10590 09:59:07.286523 <5>[ 0.862252] NFS: Registering the id_resolver key type
10591 09:59:07.289278 <5>[ 0.867550] Key type id_resolver registered
10592 09:59:07.296068 <5>[ 0.871965] Key type id_legacy registered
10593 09:59:07.302689 <6>[ 0.876240] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10594 09:59:07.309269 <6>[ 0.883163] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10595 09:59:07.315898 <6>[ 0.890902] 9p: Installing v9fs 9p2000 file system support
10596 09:59:07.352828 <5>[ 0.928972] Key type asymmetric registered
10597 09:59:07.356141 <5>[ 0.933303] Asymmetric key parser 'x509' registered
10598 09:59:07.366561 <6>[ 0.938446] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10599 09:59:07.369894 <6>[ 0.946063] io scheduler mq-deadline registered
10600 09:59:07.373015 <6>[ 0.950845] io scheduler kyber registered
10601 09:59:07.391996 <6>[ 0.967923] EINJ: ACPI disabled.
10602 09:59:07.424365 <4>[ 0.993638] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10603 09:59:07.433996 <4>[ 1.004274] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10604 09:59:07.449169 <6>[ 1.024929] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10605 09:59:07.456943 <6>[ 1.032909] printk: console [ttyS0] disabled
10606 09:59:07.485097 <6>[ 1.057555] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10607 09:59:07.491796 <6>[ 1.067049] printk: console [ttyS0] enabled
10608 09:59:07.494782 <6>[ 1.067049] printk: console [ttyS0] enabled
10609 09:59:07.501230 <6>[ 1.075942] printk: bootconsole [mtk8250] disabled
10610 09:59:07.505120 <6>[ 1.075942] printk: bootconsole [mtk8250] disabled
10611 09:59:07.511547 <6>[ 1.087221] SuperH (H)SCI(F) driver initialized
10612 09:59:07.514890 <6>[ 1.092482] msm_serial: driver initialized
10613 09:59:07.528943 <6>[ 1.101453] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10614 09:59:07.538588 <6>[ 1.110004] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10615 09:59:07.545393 <6>[ 1.118547] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10616 09:59:07.555028 <6>[ 1.127175] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10617 09:59:07.565062 <6>[ 1.135882] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10618 09:59:07.571627 <6>[ 1.144604] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10619 09:59:07.581882 <6>[ 1.153144] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10620 09:59:07.588346 <6>[ 1.161950] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10621 09:59:07.598068 <6>[ 1.170499] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10622 09:59:07.610513 <6>[ 1.186090] loop: module loaded
10623 09:59:07.616584 <6>[ 1.192193] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10624 09:59:07.639464 <4>[ 1.215566] mtk-pmic-keys: Failed to locate of_node [id: -1]
10625 09:59:07.646221 <6>[ 1.222460] megasas: 07.719.03.00-rc1
10626 09:59:07.656529 <6>[ 1.232050] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10627 09:59:07.670099 <6>[ 1.245676] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10628 09:59:07.686409 <6>[ 1.262102] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10629 09:59:07.746806 <6>[ 1.315980] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10630 09:59:08.784686 <6>[ 2.360628] Freeing initrd memory: 38444K
10631 09:59:08.794730 <6>[ 2.371163] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10632 09:59:08.805919 <6>[ 2.382148] tun: Universal TUN/TAP device driver, 1.6
10633 09:59:08.809274 <6>[ 2.388206] thunder_xcv, ver 1.0
10634 09:59:08.812690 <6>[ 2.391712] thunder_bgx, ver 1.0
10635 09:59:08.816535 <6>[ 2.395209] nicpf, ver 1.0
10636 09:59:08.826871 <6>[ 2.399221] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10637 09:59:08.830175 <6>[ 2.406697] hns3: Copyright (c) 2017 Huawei Corporation.
10638 09:59:08.836608 <6>[ 2.412287] hclge is initializing
10639 09:59:08.839692 <6>[ 2.415866] e1000: Intel(R) PRO/1000 Network Driver
10640 09:59:08.846376 <6>[ 2.420995] e1000: Copyright (c) 1999-2006 Intel Corporation.
10641 09:59:08.849727 <6>[ 2.427009] e1000e: Intel(R) PRO/1000 Network Driver
10642 09:59:08.856358 <6>[ 2.432225] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10643 09:59:08.862668 <6>[ 2.438408] igb: Intel(R) Gigabit Ethernet Network Driver
10644 09:59:08.869787 <6>[ 2.444057] igb: Copyright (c) 2007-2014 Intel Corporation.
10645 09:59:08.876319 <6>[ 2.449892] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10646 09:59:08.883044 <6>[ 2.456410] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10647 09:59:08.885902 <6>[ 2.462877] sky2: driver version 1.30
10648 09:59:08.892847 <6>[ 2.467863] VFIO - User Level meta-driver version: 0.3
10649 09:59:08.900195 <6>[ 2.476068] usbcore: registered new interface driver usb-storage
10650 09:59:08.906436 <6>[ 2.482510] usbcore: registered new device driver onboard-usb-hub
10651 09:59:08.915518 <6>[ 2.491677] mt6397-rtc mt6359-rtc: registered as rtc0
10652 09:59:08.926037 <6>[ 2.497166] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-24T09:59:11 UTC (1700819951)
10653 09:59:08.928909 <6>[ 2.506793] i2c_dev: i2c /dev entries driver
10654 09:59:08.945692 <6>[ 2.518597] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10655 09:59:08.965318 <6>[ 2.541598] cpu cpu0: EM: created perf domain
10656 09:59:08.969036 <6>[ 2.546544] cpu cpu4: EM: created perf domain
10657 09:59:08.975865 <6>[ 2.552137] sdhci: Secure Digital Host Controller Interface driver
10658 09:59:08.982574 <6>[ 2.558570] sdhci: Copyright(c) Pierre Ossman
10659 09:59:08.989626 <6>[ 2.563525] Synopsys Designware Multimedia Card Interface Driver
10660 09:59:08.995730 <6>[ 2.570156] sdhci-pltfm: SDHCI platform and OF driver helper
10661 09:59:08.999140 <6>[ 2.570292] mmc0: CQHCI version 5.10
10662 09:59:09.005858 <6>[ 2.580339] ledtrig-cpu: registered to indicate activity on CPUs
10663 09:59:09.012424 <6>[ 2.587364] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10664 09:59:09.019015 <6>[ 2.594436] usbcore: registered new interface driver usbhid
10665 09:59:09.022274 <6>[ 2.600259] usbhid: USB HID core driver
10666 09:59:09.028787 <6>[ 2.604450] spi_master spi0: will run message pump with realtime priority
10667 09:59:09.076087 <6>[ 2.645542] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10668 09:59:09.094937 <6>[ 2.661041] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10669 09:59:09.098931 <6>[ 2.674620] mmc0: Command Queue Engine enabled
10670 09:59:09.105737 <6>[ 2.679371] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10671 09:59:09.111856 <6>[ 2.686315] cros-ec-spi spi0.0: Chrome EC device registered
10672 09:59:09.115130 <6>[ 2.686624] mmcblk0: mmc0:0001 DA4128 116 GiB
10673 09:59:09.128440 <6>[ 2.704601] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10674 09:59:09.138598 <6>[ 2.708844] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10675 09:59:09.145085 <6>[ 2.711865] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10676 09:59:09.148337 <6>[ 2.721147] NET: Registered PF_PACKET protocol family
10677 09:59:09.154961 <6>[ 2.725738] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10678 09:59:09.158322 <6>[ 2.730445] 9pnet: Installing 9P2000 support
10679 09:59:09.165047 <6>[ 2.736240] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10680 09:59:09.171949 <5>[ 2.740139] Key type dns_resolver registered
10681 09:59:09.175043 <6>[ 2.751614] registered taskstats version 1
10682 09:59:09.181227 <5>[ 2.755989] Loading compiled-in X.509 certificates
10683 09:59:09.207593 <4>[ 2.777214] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10684 09:59:09.217514 <4>[ 2.787979] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10685 09:59:09.223969 <3>[ 2.798512] debugfs: File 'uA_load' in directory '/' already present!
10686 09:59:09.230976 <3>[ 2.805216] debugfs: File 'min_uV' in directory '/' already present!
10687 09:59:09.237553 <3>[ 2.811882] debugfs: File 'max_uV' in directory '/' already present!
10688 09:59:09.243688 <3>[ 2.818500] debugfs: File 'constraint_flags' in directory '/' already present!
10689 09:59:09.254966 <3>[ 2.828080] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10690 09:59:09.264190 <6>[ 2.840466] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10691 09:59:09.271133 <6>[ 2.847293] xhci-mtk 11200000.usb: xHCI Host Controller
10692 09:59:09.277336 <6>[ 2.852783] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10693 09:59:09.287477 <6>[ 2.860621] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10694 09:59:09.293927 <6>[ 2.870035] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10695 09:59:09.300770 <6>[ 2.876104] xhci-mtk 11200000.usb: xHCI Host Controller
10696 09:59:09.307344 <6>[ 2.881582] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10697 09:59:09.313516 <6>[ 2.889234] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10698 09:59:09.320703 <6>[ 2.896902] hub 1-0:1.0: USB hub found
10699 09:59:09.323649 <6>[ 2.900911] hub 1-0:1.0: 1 port detected
10700 09:59:09.333868 <6>[ 2.905172] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10701 09:59:09.337298 <6>[ 2.913730] hub 2-0:1.0: USB hub found
10702 09:59:09.340049 <6>[ 2.917733] hub 2-0:1.0: 1 port detected
10703 09:59:09.349069 <6>[ 2.925592] mtk-msdc 11f70000.mmc: Got CD GPIO
10704 09:59:09.359320 <6>[ 2.932025] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10705 09:59:09.365585 <6>[ 2.940058] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10706 09:59:09.375461 <4>[ 2.947972] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10707 09:59:09.385693 <6>[ 2.957496] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10708 09:59:09.392006 <6>[ 2.965572] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10709 09:59:09.398668 <6>[ 2.973585] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10710 09:59:09.408766 <6>[ 2.981509] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10711 09:59:09.415234 <6>[ 2.989329] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10712 09:59:09.425316 <6>[ 2.997146] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10713 09:59:09.435179 <6>[ 3.007674] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10714 09:59:09.441533 <6>[ 3.016042] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10715 09:59:09.452115 <6>[ 3.024392] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10716 09:59:09.458092 <6>[ 3.032732] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10717 09:59:09.467802 <6>[ 3.041070] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10718 09:59:09.478015 <6>[ 3.049408] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10719 09:59:09.484580 <6>[ 3.057748] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10720 09:59:09.494219 <6>[ 3.066086] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10721 09:59:09.501179 <6>[ 3.074425] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10722 09:59:09.510933 <6>[ 3.082764] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10723 09:59:09.517335 <6>[ 3.091106] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10724 09:59:09.527493 <6>[ 3.099444] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10725 09:59:09.534154 <6>[ 3.107782] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10726 09:59:09.544044 <6>[ 3.116120] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10727 09:59:09.550417 <6>[ 3.124459] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10728 09:59:09.557128 <6>[ 3.133222] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10729 09:59:09.563695 <6>[ 3.140413] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10730 09:59:09.571053 <6>[ 3.147183] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10731 09:59:09.580645 <6>[ 3.153938] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10732 09:59:09.587370 <6>[ 3.160865] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10733 09:59:09.594089 <6>[ 3.167747] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10734 09:59:09.603711 <6>[ 3.176874] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10735 09:59:09.614121 <6>[ 3.185992] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10736 09:59:09.623470 <6>[ 3.195285] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10737 09:59:09.633324 <6>[ 3.204756] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10738 09:59:09.644177 <6>[ 3.214224] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10739 09:59:09.650422 <6>[ 3.223345] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10740 09:59:09.659762 <6>[ 3.232814] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10741 09:59:09.669713 <6>[ 3.241932] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10742 09:59:09.679888 <6>[ 3.251234] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10743 09:59:09.689293 <6>[ 3.261395] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10744 09:59:09.700071 <6>[ 3.273124] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10745 09:59:09.729621 <6>[ 3.302878] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10746 09:59:09.758605 <6>[ 3.334566] hub 2-1:1.0: USB hub found
10747 09:59:09.761694 <6>[ 3.339063] hub 2-1:1.0: 3 ports detected
10748 09:59:09.769856 <6>[ 3.346416] hub 2-1:1.0: USB hub found
10749 09:59:09.773606 <6>[ 3.350762] hub 2-1:1.0: 3 ports detected
10750 09:59:09.881732 <6>[ 3.454588] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10751 09:59:10.037079 <6>[ 3.612532] hub 1-1:1.0: USB hub found
10752 09:59:10.040084 <6>[ 3.617050] hub 1-1:1.0: 4 ports detected
10753 09:59:10.050616 <6>[ 3.626706] hub 1-1:1.0: USB hub found
10754 09:59:10.053775 <6>[ 3.631281] hub 1-1:1.0: 4 ports detected
10755 09:59:10.377659 <6>[ 3.950615] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10756 09:59:10.508611 <6>[ 4.084284] hub 1-1.1:1.0: USB hub found
10757 09:59:10.511506 <6>[ 4.088612] hub 1-1.1:1.0: 4 ports detected
10758 09:59:10.625320 <6>[ 4.198423] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10759 09:59:10.757749 <6>[ 4.333813] hub 1-1.4:1.0: USB hub found
10760 09:59:10.760747 <6>[ 4.338435] hub 1-1.4:1.0: 2 ports detected
10761 09:59:10.769805 <6>[ 4.346024] hub 1-1.4:1.0: USB hub found
10762 09:59:10.773077 <6>[ 4.350674] hub 1-1.4:1.0: 2 ports detected
10763 09:59:10.841709 <6>[ 4.414589] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10764 09:59:11.025755 <6>[ 4.598614] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10765 09:59:11.110643 <3>[ 4.686797] usb 1-1.1.4: device descriptor read/64, error -32
10766 09:59:11.302473 <3>[ 4.878792] usb 1-1.1.4: device descriptor read/64, error -32
10767 09:59:11.497792 <6>[ 5.070618] usb 1-1.1.4: new full-speed USB device number 7 using xhci-mtk
10768 09:59:11.582643 <3>[ 5.158806] usb 1-1.1.4: device descriptor read/64, error -32
10769 09:59:11.773990 <3>[ 5.350690] usb 1-1.1.4: device descriptor read/64, error -32
10770 09:59:11.886782 <6>[ 5.463166] usb 1-1.1-port4: attempt power cycle
10771 09:59:11.969539 <6>[ 5.542623] usb 1-1.4.1: new high-speed USB device number 8 using xhci-mtk
10772 09:59:12.160992 <6>[ 5.734544] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10773 09:59:12.557611 <6>[ 6.130592] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10774 09:59:12.564094 <4>[ 6.138021] usb 1-1.1.4: Device not responding to setup address.
10775 09:59:12.774181 <4>[ 6.350906] usb 1-1.1.4: Device not responding to setup address.
10776 09:59:12.985671 <3>[ 6.562623] usb 1-1.1.4: device not accepting address 10, error -71
10777 09:59:13.073362 <6>[ 6.646630] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10778 09:59:13.079690 <4>[ 6.654142] usb 1-1.1.4: Device not responding to setup address.
10779 09:59:13.290019 <4>[ 6.866835] usb 1-1.1.4: Device not responding to setup address.
10780 09:59:13.502424 <3>[ 7.078672] usb 1-1.1.4: device not accepting address 11, error -71
10781 09:59:13.508858 <3>[ 7.085676] usb 1-1.1-port4: unable to enumerate USB device
10782 09:59:21.986875 <6>[ 15.567673] ALSA device list:
10783 09:59:21.993921 <6>[ 15.570975] No soundcards found.
10784 09:59:22.002338 <6>[ 15.579104] Freeing unused kernel memory: 8384K
10785 09:59:22.005226 <6>[ 15.584161] Run /init as init process
10786 09:59:22.058813 <6>[ 15.636189] NET: Registered PF_INET6 protocol family
10787 09:59:22.065405 <6>[ 15.642562] Segment Routing with IPv6
10788 09:59:22.068824 <6>[ 15.646591] In-situ OAM (IOAM) with IPv6
10789 09:59:22.103146 <30>[ 15.661193] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10790 09:59:22.106247 <30>[ 15.685223] systemd[1]: Detected architecture arm64.
10791 09:59:22.110095
10792 09:59:22.113210 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10793 09:59:22.113306
10794 09:59:22.128952 <30>[ 15.706751] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10795 09:59:22.317751 <30>[ 15.892546] systemd[1]: Queued start job for default target Graphical Interface.
10796 09:59:22.353357 <30>[ 15.931283] systemd[1]: Created slice system-getty.slice.
10797 09:59:22.359851 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10798 09:59:22.377662 <30>[ 15.955150] systemd[1]: Created slice system-modprobe.slice.
10799 09:59:22.383642 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10800 09:59:22.402294 <30>[ 15.980157] systemd[1]: Created slice system-serial\x2dgetty.slice.
10801 09:59:22.412309 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10802 09:59:22.424909 <30>[ 16.003006] systemd[1]: Created slice User and Session Slice.
10803 09:59:22.432058 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10804 09:59:22.452417 <30>[ 16.027120] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10805 09:59:22.462087 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10806 09:59:22.480741 <30>[ 16.055275] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10807 09:59:22.487115 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10808 09:59:22.511686 <30>[ 16.083092] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10809 09:59:22.518340 <30>[ 16.095370] systemd[1]: Reached target Local Encrypted Volumes.
10810 09:59:22.524744 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10811 09:59:22.541518 <30>[ 16.119202] systemd[1]: Reached target Paths.
10812 09:59:22.547628 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10813 09:59:22.560962 <30>[ 16.138629] systemd[1]: Reached target Remote File Systems.
10814 09:59:22.567467 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10815 09:59:22.584828 <30>[ 16.162582] systemd[1]: Reached target Slices.
10816 09:59:22.591377 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10817 09:59:22.605134 <30>[ 16.182629] systemd[1]: Reached target Swap.
10818 09:59:22.607800 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10819 09:59:22.628609 <30>[ 16.203191] systemd[1]: Listening on initctl Compatibility Named Pipe.
10820 09:59:22.635281 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10821 09:59:22.641544 <30>[ 16.218629] systemd[1]: Listening on Journal Audit Socket.
10822 09:59:22.648483 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10823 09:59:22.661365 <30>[ 16.239163] systemd[1]: Listening on Journal Socket (/dev/log).
10824 09:59:22.667858 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10825 09:59:22.686436 <30>[ 16.263919] systemd[1]: Listening on Journal Socket.
10826 09:59:22.692833 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10827 09:59:22.708816 <30>[ 16.283394] systemd[1]: Listening on Network Service Netlink Socket.
10828 09:59:22.715525 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10829 09:59:22.729844 <30>[ 16.307876] systemd[1]: Listening on udev Control Socket.
10830 09:59:22.736470 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10831 09:59:22.753628 <30>[ 16.331732] systemd[1]: Listening on udev Kernel Socket.
10832 09:59:22.760402 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10833 09:59:22.809035 <30>[ 16.386835] systemd[1]: Mounting Huge Pages File System...
10834 09:59:22.815592 Mounting [0;1;39mHuge Pages File System[0m...
10835 09:59:22.830365 <30>[ 16.408557] systemd[1]: Mounting POSIX Message Queue File System...
10836 09:59:22.837439 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10837 09:59:22.860407 <30>[ 16.438346] systemd[1]: Mounting Kernel Debug File System...
10838 09:59:22.866739 Mounting [0;1;39mKernel Debug File System[0m...
10839 09:59:22.884732 <30>[ 16.459063] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10840 09:59:22.898195 <30>[ 16.472680] systemd[1]: Starting Create list of static device nodes for the current kernel...
10841 09:59:22.905047 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10842 09:59:22.925395 <30>[ 16.503540] systemd[1]: Starting Load Kernel Module configfs...
10843 09:59:22.932503 Starting [0;1;39mLoad Kernel Module configfs[0m...
10844 09:59:22.949619 <30>[ 16.527374] systemd[1]: Starting Load Kernel Module drm...
10845 09:59:22.955937 Starting [0;1;39mLoad Kernel Module drm[0m...
10846 09:59:22.971977 <30>[ 16.546735] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10847 09:59:22.987230 <30>[ 16.565167] systemd[1]: Starting Journal Service...
10848 09:59:22.990130 Starting [0;1;39mJournal Service[0m...
10849 09:59:23.015444 <30>[ 16.593328] systemd[1]: Starting Load Kernel Modules...
10850 09:59:23.021593 Starting [0;1;39mLoad Kernel Modules[0m...
10851 09:59:23.045155 <30>[ 16.619723] systemd[1]: Starting Remount Root and Kernel File Systems...
10852 09:59:23.051696 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10853 09:59:23.073274 <30>[ 16.651348] systemd[1]: Starting Coldplug All udev Devices...
10854 09:59:23.079720 Starting [0;1;39mColdplug All udev Devices[0m...
10855 09:59:23.098895 <30>[ 16.677148] systemd[1]: Started Journal Service.
10856 09:59:23.105966 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10857 09:59:23.122652 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10858 09:59:23.137499 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10859 09:59:23.153477 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10860 09:59:23.173486 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10861 09:59:23.190772 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10862 09:59:23.212245 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10863 09:59:23.231158 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10864 09:59:23.251188 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10865 09:59:23.264960 See 'systemctl status systemd-remount-fs.service' for details.
10866 09:59:23.315100 Mounting [0;1;39mKernel Configuration File System[0m...
10867 09:59:23.340753 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10868 09:59:23.363603 <46>[ 16.938273] systemd-journald[175]: Received client request to flush runtime journal.
10869 09:59:23.373549 Starting [0;1;39mLoad/Save Random Seed[0m...
10870 09:59:23.394626 Starting [0;1;39mApply Kernel Variables[0m...
10871 09:59:23.413974 Starting [0;1;39mCreate System Users[0m...
10872 09:59:23.435918 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10873 09:59:23.458371 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10874 09:59:23.482047 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10875 09:59:23.495196 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10876 09:59:23.514668 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10877 09:59:23.530541 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10878 09:59:23.569278 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10879 09:59:23.595902 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10880 09:59:23.608998 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10881 09:59:23.624670 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10882 09:59:23.673118 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10883 09:59:23.697907 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10884 09:59:23.717496 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10885 09:59:23.727414 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10886 09:59:23.811632 Starting [0;1;39mNetwork Service[0m...
10887 09:59:23.834592 Starting [0;1;39mNetwork Time Synchronization[0m...
10888 09:59:23.847955 <6>[ 17.422942] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10889 09:59:23.866494 Startin<6>[ 17.444346] remoteproc remoteproc0: scp is available
10890 09:59:23.876746 g [0;1;39mUpdate UTMP about System Boot/Shutdow<6>[ 17.453639] remoteproc remoteproc0: powering up scp
10891 09:59:23.879718 n[0m...
10892 09:59:23.886025 <6>[ 17.461783] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10893 09:59:23.892948 <6>[ 17.471207] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10894 09:59:23.920769 <3>[ 17.495250] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10895 09:59:23.926767 <3>[ 17.503530] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10896 09:59:23.936819 <3>[ 17.511731] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10897 09:59:23.945023 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10898 09:59:23.955270 <6>[ 17.529289] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10899 09:59:23.961159 <6>[ 17.537042] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10900 09:59:23.971397 <6>[ 17.545925] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10901 09:59:23.981618 <3>[ 17.548144] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10902 09:59:23.987749 <3>[ 17.562831] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10903 09:59:23.994768 <6>[ 17.563290] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10904 09:59:24.004298 <4>[ 17.565086] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10905 09:59:24.010726 <4>[ 17.569306] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10906 09:59:24.017701 <3>[ 17.570968] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10907 09:59:24.027270 [[0;32m OK [<3>[ 17.601507] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10908 09:59:24.037309 0m] Started [0;<6>[ 17.602974] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10909 09:59:24.046928 1;39mNetwork Tim<6>[ 17.602981] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10910 09:59:24.057177 e Synchronizatio<3>[ 17.611007] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10911 09:59:24.057280 n[0m.
10912 09:59:24.064284 <6>[ 17.620753] remoteproc remoteproc0: remote processor scp is now up
10913 09:59:24.070742 <3>[ 17.629506] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10914 09:59:24.077117 <6>[ 17.629750] mc: Linux media interface: v0.10
10915 09:59:24.083734 <4>[ 17.638741] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10916 09:59:24.087323 <4>[ 17.638741] Fallback method does not support PEC.
10917 09:59:24.094007 <6>[ 17.639584] usbcore: registered new interface driver r8152
10918 09:59:24.104268 <3>[ 17.646978] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10919 09:59:24.107379 <6>[ 17.661686] videodev: Linux video capture interface: v2.00
10920 09:59:24.117169 <3>[ 17.671874] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 09:59:24.127079 <3>[ 17.672083] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10922 09:59:24.134020 <3>[ 17.672103] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10923 09:59:24.140566 <3>[ 17.673074] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10924 09:59:24.150868 <6>[ 17.678723] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10925 09:59:24.160900 <3>[ 17.686147] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10926 09:59:24.167555 <3>[ 17.686163] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10927 09:59:24.175087 <3>[ 17.686170] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10928 09:59:24.185064 <3>[ 17.686175] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10929 09:59:24.192152 <3>[ 17.686244] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10930 09:59:24.199082 <6>[ 17.695051] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10931 09:59:24.208952 <3>[ 17.736884] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 09:59:24.216073 <3>[ 17.737926] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10933 09:59:24.222517 <6>[ 17.742738] pci_bus 0000:00: root bus resource [bus 00-ff]
10934 09:59:24.229164 <6>[ 17.743042] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10935 09:59:24.238659 <6>[ 17.744250] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10936 09:59:24.245307 <6>[ 17.746546] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10937 09:59:24.255297 <6>[ 17.751523] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10938 09:59:24.265539 <3>[ 17.758007] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10939 09:59:24.272356 <6>[ 17.759408] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10940 09:59:24.282104 <6>[ 17.767526] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10941 09:59:24.292754 <6>[ 17.775069] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10942 09:59:24.295660 <6>[ 17.775123] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10943 09:59:24.305911 <6>[ 17.775138] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10944 09:59:24.309650 <6>[ 17.775215] pci 0000:00:00.0: supports D1 D2
10945 09:59:24.319451 <3>[ 17.782850] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10946 09:59:24.326112 <6>[ 17.790816] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10947 09:59:24.332962 <6>[ 17.792094] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10948 09:59:24.340091 <6>[ 17.800198] usbcore: registered new interface driver cdc_ether
10949 09:59:24.346361 <6>[ 17.806255] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10950 09:59:24.352857 <6>[ 17.829973] usbcore: registered new interface driver r8153_ecm
10951 09:59:24.356445 <6>[ 17.830002] Bluetooth: Core ver 2.22
10952 09:59:24.359667 <6>[ 17.830083] NET: Registered PF_BLUETOOTH protocol family
10953 09:59:24.366210 <6>[ 17.830087] Bluetooth: HCI device and connection manager initialized
10954 09:59:24.373070 <6>[ 17.830106] Bluetooth: HCI socket layer initialized
10955 09:59:24.379654 <6>[ 17.830112] Bluetooth: L2CAP socket layer initialized
10956 09:59:24.382759 <6>[ 17.830122] Bluetooth: SCO socket layer initialized
10957 09:59:24.389187 <6>[ 17.839337] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10958 09:59:24.398958 <6>[ 17.856605] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10959 09:59:24.406043 <4>[ 17.857298] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10960 09:59:24.416468 <4>[ 17.857307] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10961 09:59:24.423466 <3>[ 17.862925] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10962 09:59:24.429967 <6>[ 17.864288] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10963 09:59:24.440273 <3>[ 17.864848] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10964 09:59:24.450589 <3>[ 17.867942] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10965 09:59:24.460000 <6>[ 17.875864] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10966 09:59:24.470320 <6>[ 17.880469] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10967 09:59:24.473321 <6>[ 17.888117] usbcore: registered new interface driver uvcvideo
10968 09:59:24.479924 <6>[ 17.888715] usbcore: registered new interface driver btusb
10969 09:59:24.486935 <6>[ 17.888886] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10970 09:59:24.496316 <4>[ 17.889519] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10971 09:59:24.503224 <3>[ 17.889538] Bluetooth: hci0: Failed to load firmware file (-2)
10972 09:59:24.509722 <3>[ 17.889541] Bluetooth: hci0: Failed to set up firmware (-2)
10973 09:59:24.519237 <4>[ 17.889549] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10974 09:59:24.522563 <6>[ 17.892609] pci 0000:01:00.0: supports D1 D2
10975 09:59:24.532776 <3>[ 17.893776] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10976 09:59:24.539513 <6>[ 17.906485] r8152 1-1.1.1:1.0 eth0: v1.12.13
10977 09:59:24.545966 <6>[ 17.908163] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10978 09:59:24.552388 <3>[ 17.920112] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10979 09:59:24.558991 <6>[ 17.928496] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10980 09:59:24.565525 <6>[ 17.934537] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10981 09:59:24.575450 <6>[ 18.149626] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10982 09:59:24.582056 <6>[ 18.149630] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10983 09:59:24.592530 <6>[ 18.149638] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10984 09:59:24.598953 <6>[ 18.149651] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10985 09:59:24.605265 <6>[ 18.149664] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10986 09:59:24.612592 <6>[ 18.149677] pci 0000:00:00.0: PCI bridge to [bus 01]
10987 09:59:24.618706 <6>[ 18.149683] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10988 09:59:24.628345 [[0;32m OK [<6>[ 18.203112] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10989 09:59:24.635240 0m] Finished [0<6>[ 18.211506] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10990 09:59:24.641614 ;1;39mUpdate UTM<6>[ 18.219521] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10991 09:59:24.645029 P about System Boot/Shutdown[0m.
10992 09:59:24.661254 <5>[ 18.236441] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10993 09:59:24.670278 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10994 09:59:24.683289 <5>[ 18.258118] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10995 09:59:24.693353 <4>[ 18.265821] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10996 09:59:24.696355 <6>[ 18.274911] cfg80211: failed to load regulatory.db
10997 09:59:24.746380 <6>[ 18.320955] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10998 09:59:24.752623 <6>[ 18.328451] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10999 09:59:24.764905 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11000 09:59:24.777110 <6>[ 18.355143] mt7921e 0000:01:00.0: ASIC revision: 79610010
11001 09:59:24.783494 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11002 09:59:24.796925 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11003 09:59:24.812552 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11004 09:59:24.831857 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11005 09:59:24.882495 <4>[ 18.454165] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11006 09:59:24.892424 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11007 09:59:24.912765 Starting [0;1;39mNetwork Name Resolution[0m...
11008 09:59:24.937725 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11009 09:59:24.957895 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11010 09:59:24.980480 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11011 09:59:25.006561 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.<4>[ 18.578089] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11012 09:59:25.006779
11013 09:59:25.021604 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11014 09:59:25.041336 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11015 09:59:25.053373 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11016 09:59:25.069102 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11017 09:59:25.119735 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11018 09:59:25.135110 <4>[ 18.706109] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11019 09:59:25.169397 Starting [0;1;39mUser Login Management[0m...
11020 09:59:25.190029 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11021 09:59:25.206424 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11022 09:59:25.225125 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11023 09:59:25.242992 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11024 09:59:25.259450 <4>[ 18.830601] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11025 09:59:25.265880 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11026 09:59:25.314416 Starting [0;1;39mPermit User Sessions[0m...
11027 09:59:25.329609 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11028 09:59:25.345805 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11029 09:59:25.382140 [[0;32m OK [0m] Started [0;1;39mGetty on tt<4>[ 18.953402] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11030 09:59:25.382579 y1[0m.
11031 09:59:25.407886 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11032 09:59:25.426298 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11033 09:59:25.442194 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11034 09:59:25.457692 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11035 09:59:25.507677 <4>[ 19.079230] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11036 09:59:25.514808 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11037 09:59:25.559396 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11038 09:59:25.601352
11039 09:59:25.601828
11040 09:59:25.604724 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11041 09:59:25.605203
11042 09:59:25.607344 debian-bullseye-arm64 login: root (automatic login)
11043 09:59:25.607753
11044 09:59:25.608075
11045 09:59:25.627643 Linux debian-bullseye-arm64 6.1.62-cip9 #1 SMP PREEMPT Fri Nov 24 09:44:51 UTC 2023 aarch64
11046 09:59:25.628058
11047 09:59:25.637342 T<4>[ 19.209353] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11048 09:59:25.643859 he programs included with the Debian GNU/Linux system are free software;
11049 09:59:25.650208 the exact distribution terms for each program are described in the
11050 09:59:25.653625 individual files in /usr/share/doc/*/copyright.
11051 09:59:25.657355
11052 09:59:25.660690 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11053 09:59:25.663897 permitted by applicable law.
11054 09:59:25.665167 Matched prompt #10: / #
11056 09:59:25.666196 Setting prompt string to ['/ #']
11057 09:59:25.666611 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11059 09:59:25.667551 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11060 09:59:25.667984 start: 2.2.6 expect-shell-connection (timeout 00:03:36) [common]
11061 09:59:25.668322 Setting prompt string to ['/ #']
11062 09:59:25.668622 Forcing a shell prompt, looking for ['/ #']
11064 09:59:25.719355 / #
11065 09:59:25.719839 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11066 09:59:25.720225 Waiting using forced prompt support (timeout 00:02:30)
11067 09:59:25.725857
11068 09:59:25.726625 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11069 09:59:25.727095 start: 2.2.7 export-device-env (timeout 00:03:36) [common]
11070 09:59:25.727573 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11071 09:59:25.727992 end: 2.2 depthcharge-retry (duration 00:01:24) [common]
11072 09:59:25.728466 end: 2 depthcharge-action (duration 00:01:24) [common]
11073 09:59:25.728909 start: 3 lava-test-retry (timeout 00:07:59) [common]
11074 09:59:25.729330 start: 3.1 lava-test-shell (timeout 00:07:59) [common]
11075 09:59:25.729736 Using namespace: common
11077 09:59:25.830758 / # #
11078 09:59:25.831354 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11079 09:59:25.831919 <4>[ 19.335636] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11080 09:59:25.837278 #
11081 09:59:25.838026 Using /lava-12073291
11083 09:59:25.939017 / # export SHELL=/bin/sh
11084 09:59:25.939234 <4>[ 19.459757] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11085 09:59:25.944410 export SHELL=/bin/sh
11087 09:59:26.044909 / # . /lava-12073291/environment
11088 09:59:26.045067 <6>[ 19.542847] IPv6: ADDRCONF(NETDEV_CHANGE): enxf4f5e850de0a: link becomes ready
11089 09:59:26.045142 <6>[ 19.550976] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
11090 09:59:26.045206 . /lava-12073291/envir<4>[ 19.583006] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11091 09:59:26.050201 onment
11093 09:59:26.150762 / # /lava-12073291/bin/lava-test-runner /lava-12073291/0
11094 09:59:26.150892 Test shell timeout: 10s (minimum of the action and connection timeout)
11095 09:59:26.151211 /lava-12073291/bin/lava-test-runner /lava-12073291/0<3>[ 19.705325] mt7921e 0000:01:00.0: hardware init failed
11096 09:59:26.156063
11097 09:59:26.197868 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11098 09:59:26.198314 + cd /lava-12073291/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11099 09:59:26.198654 + cat uuid
11100 09:59:26.198970 + UUID=12073291_1.5.2.3.1
11101 09:59:26.199273 + set +x
11102 09:59:26.199566 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 12073291_1.5.2.3.1>
11103 09:59:26.200136 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 12073291_1.5.2.3.1
11104 09:59:26.200491 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (12073291_1.5.2.3.1)
11105 09:59:26.200877 Skipping test definition patterns.
11106 09:59:26.201343 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11107 09:59:26.207227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11108 09:59:26.207896 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11110 09:59:26.217038 device: /dev/vide<4>[ 19.789616] use of bytesused == 0 is deprecated and will be removed in the future,
11111 09:59:26.217537 o2
11112 09:59:26.220402 <4>[ 19.798597] use the actual size instead.
11113 09:59:26.234330 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11114 09:59:26.244812 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
11115 09:59:26.251534
11116 09:59:26.264878 Compliance test for mtk-vcodec-enc device /dev/video2:
11117 09:59:26.274324
11118 09:59:26.288348 Driver Info:
11119 09:59:26.298927 Driver name : mtk-vcodec-enc
11120 09:59:26.313158 Card type : MT8192 video encoder
11121 09:59:26.325096 Bus info : platform:17020000.vcodec
11122 09:59:26.332474 Driver version : 6.1.62
11123 09:59:26.343540 Capabilities : 0x84204000
11124 09:59:26.354165 Video Memory-to-Memory Multiplanar
11125 09:59:26.365649 Streaming
11126 09:59:26.383590 Extended Pix Format
11127 09:59:26.394028 Device Capabilities
11128 09:59:26.407242 Device Caps : 0x04204000
11129 09:59:26.422214 Video Memory-to-Memory Multiplanar
11130 09:59:26.433896 Streaming
11131 09:59:26.446687 Extended Pix Format
11132 09:59:26.461506 Detected Stateful Encoder
11133 09:59:26.475458
11134 09:59:26.487937 Required ioctls:
11135 09:59:26.503806 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11136 09:59:26.504223 test VIDIOC_QUERYCAP: OK
11137 09:59:26.504816 Received signal: <TESTSET> START Required-ioctls
11138 09:59:26.505176 Starting test_set Required-ioctls
11139 09:59:26.529083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11140 09:59:26.529956 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11142 09:59:26.532293 test invalid ioctls: OK
11143 09:59:26.558464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11144 09:59:26.558880
11145 09:59:26.559454 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11147 09:59:26.569690 Allow for multiple opens:
11148 09:59:26.576841 <LAVA_SIGNAL_TESTSET STOP>
11149 09:59:26.577524 Received signal: <TESTSET> STOP
11150 09:59:26.577898 Closing test_set Required-ioctls
11151 09:59:26.587394 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11152 09:59:26.588204 Received signal: <TESTSET> START Allow-for-multiple-opens
11153 09:59:26.588555 Starting test_set Allow-for-multiple-opens
11154 09:59:26.590580 test second /dev/video2 open: OK
11155 09:59:26.612969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11156 09:59:26.613633 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11158 09:59:26.616668 test VIDIOC_QUERYCAP: OK
11159 09:59:26.638911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11160 09:59:26.639572 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11162 09:59:26.642485 test VIDIOC_G/S_PRIORITY: OK
11163 09:59:26.661570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11164 09:59:26.662232 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11166 09:59:26.665223 test for unlimited opens: OK
11167 09:59:26.688387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11168 09:59:26.688804
11169 09:59:26.689380 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11171 09:59:26.699414 Debug ioctls:
11172 09:59:26.708784 <LAVA_SIGNAL_TESTSET STOP>
11173 09:59:26.709477 Received signal: <TESTSET> STOP
11174 09:59:26.709823 Closing test_set Allow-for-multiple-opens
11175 09:59:26.718328 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11176 09:59:26.718994 Received signal: <TESTSET> START Debug-ioctls
11177 09:59:26.719338 Starting test_set Debug-ioctls
11178 09:59:26.721721 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11179 09:59:26.743940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11180 09:59:26.744615 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11182 09:59:26.750437 test VIDIOC_LOG_STATUS: OK (Not Supported)
11183 09:59:26.769867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11184 09:59:26.770288
11185 09:59:26.770871 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11187 09:59:26.779973 Input ioctls:
11188 09:59:26.787159 <LAVA_SIGNAL_TESTSET STOP>
11189 09:59:26.787831 Received signal: <TESTSET> STOP
11190 09:59:26.788181 Closing test_set Debug-ioctls
11191 09:59:26.796840 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11192 09:59:26.797529 Received signal: <TESTSET> START Input-ioctls
11193 09:59:26.797885 Starting test_set Input-ioctls
11194 09:59:26.799764 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11195 09:59:26.824205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11196 09:59:26.824887 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11198 09:59:26.828074 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11199 09:59:26.845730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11200 09:59:26.846406 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11202 09:59:26.852696 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11203 09:59:26.869589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11204 09:59:26.870265 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11206 09:59:26.876146 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11207 09:59:26.900696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11208 09:59:26.901373 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11210 09:59:26.903856 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11211 09:59:26.925903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11212 09:59:26.926572 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11214 09:59:26.929395 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11215 09:59:26.952526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11216 09:59:26.952777 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11218 09:59:26.955847 Inputs: 0 Audio Inputs: 0 Tuners: 0
11219 09:59:26.968206
11220 09:59:26.989595 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11221 09:59:27.012731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11222 09:59:27.013512 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11224 09:59:27.018951 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11225 09:59:27.039178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11226 09:59:27.039961 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11228 09:59:27.045734 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11229 09:59:27.062499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11230 09:59:27.063215 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11232 09:59:27.069130 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11233 09:59:27.088451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11234 09:59:27.089122 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11236 09:59:27.094941 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11237 09:59:27.112659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11238 09:59:27.113089
11239 09:59:27.113707 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11241 09:59:27.133109 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11242 09:59:27.159939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11243 09:59:27.160611 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11245 09:59:27.166204 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11246 09:59:27.186971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11247 09:59:27.187644 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11249 09:59:27.190672 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11250 09:59:27.207338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11251 09:59:27.208011 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11253 09:59:27.210974 test VIDIOC_G/S_EDID: OK (Not Supported)
11254 09:59:27.232440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11255 09:59:27.232900
11256 09:59:27.233509 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11258 09:59:27.247782 Control ioctls:
11259 09:59:27.254984 <LAVA_SIGNAL_TESTSET STOP>
11260 09:59:27.255714 Received signal: <TESTSET> STOP
11261 09:59:27.256075 Closing test_set Input-ioctls
11262 09:59:27.265169 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11263 09:59:27.265922 Received signal: <TESTSET> START Control-ioctls
11264 09:59:27.266290 Starting test_set Control-ioctls
11265 09:59:27.268347 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11266 09:59:27.293530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11267 09:59:27.294022 test VIDIOC_QUERYCTRL: OK
11268 09:59:27.294727 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11270 09:59:27.313090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11271 09:59:27.313953 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11273 09:59:27.317021 test VIDIOC_G/S_CTRL: OK
11274 09:59:27.338622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11275 09:59:27.339316 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11277 09:59:27.341688 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11278 09:59:27.361834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11279 09:59:27.362578 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11281 09:59:27.371902 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11282 09:59:27.375177 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11283 09:59:27.400772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11284 09:59:27.401557 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11286 09:59:27.403692 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11287 09:59:27.422855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11288 09:59:27.423720 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11290 09:59:27.426558 Standard Controls: 16 Private Controls: 0
11291 09:59:27.434259
11292 09:59:27.452333 Format ioctls:
11293 09:59:27.459653 <LAVA_SIGNAL_TESTSET STOP>
11294 09:59:27.460379 Received signal: <TESTSET> STOP
11295 09:59:27.460760 Closing test_set Control-ioctls
11296 09:59:27.469865 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11297 09:59:27.470711 Received signal: <TESTSET> START Format-ioctls
11298 09:59:27.471112 Starting test_set Format-ioctls
11299 09:59:27.473081 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11300 09:59:27.495115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11301 09:59:27.495821 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11303 09:59:27.498565 test VIDIOC_G/S_PARM: OK
11304 09:59:27.525062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11305 09:59:27.525768 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11307 09:59:27.528037 test VIDIOC_G_FBUF: OK (Not Supported)
11308 09:59:27.551601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11309 09:59:27.552281 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11311 09:59:27.554631 test VIDIOC_G_FMT: OK
11312 09:59:27.578451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11313 09:59:27.579185 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11315 09:59:27.582325 test VIDIOC_TRY_FMT: OK
11316 09:59:27.603332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11317 09:59:27.604023 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11319 09:59:27.613094 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11320 09:59:27.613667 test VIDIOC_S_FMT: FAIL
11321 09:59:27.638648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11322 09:59:27.639384 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11324 09:59:27.641353 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11325 09:59:27.663159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11326 09:59:27.663954 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11328 09:59:27.666439 test Cropping: OK
11329 09:59:27.687124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11330 09:59:27.687792 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11332 09:59:27.690166 test Composing: OK (Not Supported)
11333 09:59:27.713468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11334 09:59:27.714139 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11336 09:59:27.716924 test Scaling: OK (Not Supported)
11337 09:59:27.737650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11338 09:59:27.738148
11339 09:59:27.738731 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11341 09:59:27.754316 Codec ioctls:
11342 09:59:27.767320 <LAVA_SIGNAL_TESTSET STOP>
11343 09:59:27.768093 Received signal: <TESTSET> STOP
11344 09:59:27.768526 Closing test_set Format-ioctls
11345 09:59:27.777732 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11346 09:59:27.778412 Received signal: <TESTSET> START Codec-ioctls
11347 09:59:27.778761 Starting test_set Codec-ioctls
11348 09:59:27.780876 test VIDIOC_(TRY_)ENCODER_CMD: OK
11349 09:59:27.802163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11350 09:59:27.802432 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11352 09:59:27.808545 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11353 09:59:27.825300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11354 09:59:27.825552 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11356 09:59:27.831491 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11357 09:59:27.846846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11358 09:59:27.846928
11359 09:59:27.847161 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11361 09:59:27.857298 Buffer ioctls:
11362 09:59:27.865144 <LAVA_SIGNAL_TESTSET STOP>
11363 09:59:27.865432 Received signal: <TESTSET> STOP
11364 09:59:27.865528 Closing test_set Codec-ioctls
11365 09:59:27.875123 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11366 09:59:27.875415 Received signal: <TESTSET> START Buffer-ioctls
11367 09:59:27.875500 Starting test_set Buffer-ioctls
11368 09:59:27.878100 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11369 09:59:27.906197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11370 09:59:27.906414 test VIDIOC_EXPBUF: OK
11371 09:59:27.906746 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11373 09:59:27.929788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11374 09:59:27.930520 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11376 09:59:27.933513 test Requests: OK (Not Supported)
11377 09:59:27.953624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11378 09:59:27.954161
11379 09:59:27.954789 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11381 09:59:27.965068 Test input 0:
11382 09:59:27.974696
11383 09:59:27.985562 Streaming ioctls:
11384 09:59:27.992881 <LAVA_SIGNAL_TESTSET STOP>
11385 09:59:27.993664 Received signal: <TESTSET> STOP
11386 09:59:27.994049 Closing test_set Buffer-ioctls
11387 09:59:28.001931 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11388 09:59:28.002602 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11389 09:59:28.002949 Starting test_set Streaming-ioctls_Test-input-0
11390 09:59:28.005281 test read/write: OK (Not Supported)
11391 09:59:28.028729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11392 09:59:28.029551 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11394 09:59:28.035386 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2798): node->streamon(q.g_type())
11395 09:59:28.047566 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2845): testBlockingDQBuf(node, q)
11396 09:59:28.055646 test blocking wait: FAIL
11397 09:59:28.081352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11398 09:59:28.082141 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11400 09:59:28.090187 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11401 09:59:28.090616 test MMAP (select): FAIL
11402 09:59:28.117872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11403 09:59:28.118635 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11405 09:59:28.124224 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11406 09:59:28.131795 test MMAP (epoll): FAIL
11407 09:59:28.159850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11408 09:59:28.160597 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11410 09:59:28.169531 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11411 09:59:28.176102 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11412 09:59:28.182146 test USERPTR (select): FAIL
11413 09:59:28.212200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11414 09:59:28.213032 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11416 09:59:28.218205 test DMABUF: Cannot test, specify --expbuf-device
11417 09:59:28.222966
11418 09:59:28.240569 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11419 09:59:28.244035 <LAVA_TEST_RUNNER EXIT>
11420 09:59:28.244813 ok: lava_test_shell seems to have completed
11421 09:59:28.245195 Marking unfinished test run as failed
11423 09:59:28.250374 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11424 09:59:28.251018 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11425 09:59:28.251462 end: 3 lava-test-retry (duration 00:00:03) [common]
11426 09:59:28.251945 start: 4 finalize (timeout 00:07:57) [common]
11427 09:59:28.252429 start: 4.1 power-off (timeout 00:00:30) [common]
11428 09:59:28.253178 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11429 09:59:28.370978 >> Command sent successfully.
11430 09:59:28.374879 Returned 0 in 0 seconds
11431 09:59:28.475784 end: 4.1 power-off (duration 00:00:00) [common]
11433 09:59:28.477520 start: 4.2 read-feedback (timeout 00:07:57) [common]
11434 09:59:28.479152 Listened to connection for namespace 'common' for up to 1s
11435 09:59:29.479541 Finalising connection for namespace 'common'
11436 09:59:29.479720 Disconnecting from shell: Finalise
11437 09:59:29.479804 / #
11438 09:59:29.580144 end: 4.2 read-feedback (duration 00:00:01) [common]
11439 09:59:29.580324 end: 4 finalize (duration 00:00:01) [common]
11440 09:59:29.580452 Cleaning after the job
11441 09:59:29.580553 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073291/tftp-deploy-s0zgjjin/ramdisk
11442 09:59:29.586258 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073291/tftp-deploy-s0zgjjin/kernel
11443 09:59:29.595035 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073291/tftp-deploy-s0zgjjin/dtb
11444 09:59:29.595226 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12073291/tftp-deploy-s0zgjjin/modules
11445 09:59:29.602366 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12073291
11446 09:59:29.679645 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12073291
11447 09:59:29.679824 Job finished correctly